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authorWaldemar Brodkorb <wbx@openadk.org>2014-05-16 09:41:57 +0200
committerWaldemar Brodkorb <wbx@openadk.org>2014-05-16 09:42:19 +0200
commita37955570287dd5ec690c229b1f30d97578a975f (patch)
treea283a43f6a4b8f72cc70627f61d44c4729d4e502 /target/arm/cubox-i
parent40a104be0f8087bf063a6d8421b52dcc679ef39c (diff)
add support for 3.10.30 stable from Jon Nettleton
Diffstat (limited to 'target/arm/cubox-i')
-rw-r--r--target/arm/cubox-i/patches/3.10.30/linux4kix.patch584646
1 files changed, 584646 insertions, 0 deletions
diff --git a/target/arm/cubox-i/patches/3.10.30/linux4kix.patch b/target/arm/cubox-i/patches/3.10.30/linux4kix.patch
new file mode 100644
index 000000000..50ed15121
--- /dev/null
+++ b/target/arm/cubox-i/patches/3.10.30/linux4kix.patch
@@ -0,0 +1,584646 @@
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/clcd-panels.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/clcd-panels.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/clcd-panels.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/clcd-panels.dtsi 2014-05-15 20:33:34.137841852 +0200
+@@ -0,0 +1,52 @@
++/*
++ * ARM Ltd. Versatile Express
++ *
++ */
++
++/ {
++ panels {
++ panel@0 {
++ compatible = "panel";
++ mode = "VGA";
++ refresh = <60>;
++ xres = <640>;
++ yres = <480>;
++ pixclock = <39721>;
++ left_margin = <40>;
++ right_margin = <24>;
++ upper_margin = <32>;
++ lower_margin = <11>;
++ hsync_len = <96>;
++ vsync_len = <2>;
++ sync = <0>;
++ vmode = "FB_VMODE_NONINTERLACED";
++
++ tim2 = "TIM2_BCD", "TIM2_IPC";
++ cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
++ caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
++ bpp = <16>;
++ };
++
++ panel@1 {
++ compatible = "panel";
++ mode = "XVGA";
++ refresh = <60>;
++ xres = <1024>;
++ yres = <768>;
++ pixclock = <15748>;
++ left_margin = <152>;
++ right_margin = <48>;
++ upper_margin = <23>;
++ lower_margin = <3>;
++ hsync_len = <104>;
++ vsync_len = <4>;
++ sync = <0>;
++ vmode = "FB_VMODE_NONINTERLACED";
++
++ tim2 = "TIM2_BCD", "TIM2_IPC";
++ cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
++ caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
++ bpp = <16>;
++ };
++ };
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/exynos5440.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/exynos5440.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/exynos5440.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/exynos5440.dtsi 2014-05-15 20:33:34.169842082 +0200
+@@ -113,7 +113,7 @@
+ clock-names = "spi", "spi_busclk0";
+ };
+
+- pinctrl {
++ pin_ctrl: pinctrl {
+ compatible = "samsung,exynos5440-pinctrl";
+ reg = <0xE0000 0x1000>;
+ interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
+@@ -216,4 +216,44 @@
+ clock-names = "rtc";
+ status = "disabled";
+ };
++
++ pcie@290000 {
++ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
++ reg = <0x290000 0x1000
++ 0x270000 0x1000
++ 0x271000 0x40>;
++ interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
++ clocks = <&clock 28>, <&clock 27>;
++ clock-names = "pcie", "pcie_bus";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
++ 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
++ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0x0 0 &gic 53>;
++ num-lanes = <4>;
++ };
++
++ pcie@2a0000 {
++ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
++ reg = <0x2a0000 0x1000
++ 0x272000 0x1000
++ 0x271040 0x40>;
++ interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
++ clocks = <&clock 29>, <&clock 27>;
++ clock-names = "pcie", "pcie_bus";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
++ 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
++ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0x0 0 &gic 56>;
++ num-lanes = <4>;
++ };
+ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/exynos5440-ssdk5440.dts linux-linaro-stable-mx6/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/exynos5440-ssdk5440.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/exynos5440-ssdk5440.dts 2014-05-15 20:33:34.169842082 +0200
+@@ -30,4 +30,12 @@
+ clock-frequency = <50000000>;
+ };
+ };
++
++ pcie@290000 {
++ reset-gpio = <&pin_ctrl 5 0>;
++ };
++
++ pcie@2a0000 {
++ reset-gpio = <&pin_ctrl 22 0>;
++ };
+ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx23.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx23.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx23.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx23.dtsi 2014-05-15 20:33:34.173842112 +0200
+@@ -20,6 +20,7 @@
+ gpio2 = &gpio2;
+ serial0 = &auart0;
+ serial1 = &auart1;
++ usbphy0 = &usbphy0;
+ };
+
+ cpus {
+@@ -360,7 +361,8 @@
+ compatible = "fsl,imx23-lcdif";
+ reg = <0x80030000 2000>;
+ interrupts = <46 45>;
+- clocks = <&clks 38>;
++ clocks = <&clks 38>, <&clks 38>;
++ clock-names = "pix", "axi";
+ status = "disabled";
+ };
+
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx28.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx28.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx28.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx28.dtsi 2014-05-15 20:33:34.189842227 +0200
+@@ -29,6 +29,8 @@
+ serial4 = &auart4;
+ ethernet0 = &mac0;
+ ethernet1 = &mac1;
++ usbphy0 = &usbphy0;
++ usbphy1 = &usbphy1;
+ };
+
+ cpus {
+@@ -727,7 +729,8 @@
+ compatible = "fsl,imx28-lcdif";
+ reg = <0x80030000 0x2000>;
+ interrupts = <38 86>;
+- clocks = <&clks 55>;
++ clocks = <&clks 55>, <&clks 55>;
++ clock-names = "pix", "axi";
+ dmas = <&dma_apbh 13>;
+ dma-names = "rx";
+ status = "disabled";
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx53.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx53.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx53.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx53.dtsi 2014-05-15 20:33:34.209842371 +0200
+@@ -782,5 +782,10 @@
+ status = "disabled";
+ };
+ };
++
++ ocram: sram@f8000000 {
++ compatible = "mmio-sram";
++ reg = <0xf8000000 0x20000>;
++ };
+ };
+ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-cubox-i.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-cubox-i.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-cubox-i.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-cubox-i.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,12 @@
++/*
++ * Copyright (C) 2014 Russell King
++ */
++/dts-v1/;
++
++#include "imx6dl.dtsi"
++#include "imx6qdl-cubox-i.dtsi"
++
++/ {
++ model = "SolidRun Cubox-i Solo/DualLite";
++ compatible = "solidrun,cubox-i/dl", "fsl,imx6dl";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl.dtsi 2014-05-15 20:33:34.209842371 +0200
+@@ -8,19 +8,39 @@
+ *
+ */
+
+-#include "imx6qdl.dtsi"
+ #include "imx6dl-pinfunc.h"
++#include "imx6qdl.dtsi"
+
+ / {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- cpu@0 {
++ cpu0: cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
++ operating-points = <
++ /* kHz uV */
++ 996000 1275000
++ 792000 1175000
++ 396000 1075000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 996000 1175000
++ 792000 1175000
++ 396000 1175000
++ >;
++ clock-latency = <61036>; /* two CLK32 periods */
++ clocks = <&clks 104>, <&clks 6>, <&clks 16>,
++ <&clks 17>, <&clks 170>;
++ clock-names = "arm", "pll2_pfd2_396m", "step",
++ "pll1_sw", "pll1_sys";
++ arm-supply = <&reg_arm>;
++ pu-supply = <&reg_pu>;
++ soc-supply = <&reg_soc>;
+ };
+
+ cpu@1 {
+@@ -28,140 +48,125 @@
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
++ operating-points = <
++ /* kHz uV */
++ 996000 1250000
++ 792000 1175000
++ 396000 1075000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 996000 1175000
++ 792000 1175000
++ 396000 1175000
++ >;
++ clock-latency = <61036>; /* two CLK32 periods */
++ clocks = <&clks 104>, <&clks 6>, <&clks 16>,
++ <&clks 17>, <&clks 170>;
++ clock-names = "arm", "pll2_pfd2_396m", "step",
++ "pll1_sw", "pll1_sys";
++ arm-supply = <&reg_arm>;
++ pu-supply = <&reg_pu>;
++ soc-supply = <&reg_soc>;
+ };
+ };
+
+ soc {
+- aips1: aips-bus@02000000 {
+- iomuxc: iomuxc@020e0000 {
+- compatible = "fsl,imx6dl-iomuxc";
+- reg = <0x020e0000 0x4000>;
+
+- enet {
+- pinctrl_enet_1: enetgrp-1 {
+- fsl,pins = <
+- MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+- MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+- MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+- MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+- MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+- MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+- MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+- MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+- MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+- MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+- MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+- MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+- MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+- MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+- >;
+- };
+-
+- pinctrl_enet_2: enetgrp-2 {
+- fsl,pins = <
+- MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
+- MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
+- MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+- MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+- MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+- MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+- MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+- MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+- MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+- MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+- MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+- MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+- MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+- MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+- MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+- >;
+- };
+- };
+-
+- uart1 {
+- pinctrl_uart1_1: uart1grp-1 {
+- fsl,pins = <
+- MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+- MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+- >;
+- };
+- };
+-
+- uart4 {
+- pinctrl_uart4_1: uart4grp-1 {
+- fsl,pins = <
+- MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+- MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+- >;
+- };
+- };
+-
+- usbotg {
+- pinctrl_usbotg_2: usbotggrp-2 {
+- fsl,pins = <
+- MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+- >;
+- };
+- };
+-
+- usdhc2 {
+- pinctrl_usdhc2_1: usdhc2grp-1 {
+- fsl,pins = <
+- MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
+- MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
+- MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+- MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+- MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+- MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+- MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
+- MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
+- MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
+- MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
+- >;
+- };
+- };
+-
+- usdhc3 {
+- pinctrl_usdhc3_1: usdhc3grp-1 {
+- fsl,pins = <
+- MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
+- MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
+- MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+- MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+- MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+- MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+- MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+- MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+- MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+- MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc3_2: usdhc3grp_2 {
+- fsl,pins = <
+- MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
+- MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
+- MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+- MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+- MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+- MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+- >;
+- };
+- };
++ busfreq { /* BUSFREQ */
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
++ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m";
++ interrupts = <0 107 0x04>, <0 112 0x4>;
++ interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
++ fsl,max_ddr_freq = <400000000>;
++ };
++
++ gpu: gpu@00130000 {
++ compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
++ reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
++ <0x0 0x0>;
++ reg-names = "iobase_3d", "iobase_2d",
++ "phys_baseaddr";
++ interrupts = <0 9 0x04>, <0 10 0x04>;
++ interrupt-names = "irq_3d", "irq_2d";
++ clocks = <&clks 143>, <&clks 27>,
++ <&clks 121>, <&clks 122>,
++ <&clks 0>;
++ clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
++ "gpu2d_clk", "gpu3d_clk",
++ "gpu3d_shader_clk";
++ resets = <&src 0>, <&src 3>;
++ reset-names = "gpu3d", "gpu2d";
++ pu-supply = <&reg_pu>;
++ };
++
++ ocram: sram@00900000 {
++ compatible = "mmio-sram";
++ reg = <0x00900000 0x20000>;
++ clocks = <&clks 142>;
++ };
+
++ hdmi_core: hdmi_core@00120000 {
++ compatible = "fsl,imx6dl-hdmi-core";
++ reg = <0x00120000 0x9000>;
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ status = "disabled";
++ };
++
++ hdmi_video: hdmi_video@020e0000 {
++ compatible = "fsl,imx6dl-hdmi-video";
++ reg = <0x020e0000 0x1000>;
++ reg-names = "hdmi_gpr";
++ interrupts = <0 115 0x04>;
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ status = "disabled";
++ };
++
++ hdmi_audio: hdmi_audio@00120000 {
++ compatible = "fsl,imx6dl-hdmi-audio";
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ dmas = <&sdma 2 22 0>;
++ dma-names = "tx";
++ status = "disabled";
++ };
++
++ hdmi_cec: hdmi_cec@00120000 {
++ compatible = "fsl,imx6dl-hdmi-cec";
++ interrupts = <0 115 0x04>;
++ status = "disabled";
++ };
++
++ aips1: aips-bus@02000000 {
++ vpu@02040000 {
++ iramsize = <0>;
++ status = "okay";
++ };
+
++ iomuxc: iomuxc@020e0000 {
++ compatible = "fsl,imx6dl-iomuxc";
+ };
+
+ pxp: pxp@020f0000 {
++ compatible = "fsl,imx6dl-pxp-dma";
+ reg = <0x020f0000 0x4000>;
+ interrupts = <0 98 0x04>;
++ clocks = <&clks 133>;
++ clock-names = "pxp-axi";
++ status = "disabled";
+ };
+
+ epdc: epdc@020f4000 {
++ compatible = "fsl,imx6dl-epdc";
+ reg = <0x020f4000 0x4000>;
+ interrupts = <0 97 0x04>;
++ clocks = <&clks 133>, <&clks 137>;
++ clock-names = "epdc_axi", "epdc_pix";
+ };
+
+ lcdif: lcdif@020f8000 {
+@@ -171,6 +176,16 @@
+ };
+
+ aips2: aips-bus@02100000 {
++ mipi_dsi: mipi@021e0000 {
++ compatible = "fsl,imx6dl-mipi-dsi";
++ reg = <0x021e0000 0x4000>;
++ interrupts = <0 102 0x04>;
++ gpr = <&gpr>;
++ clocks = <&clks 138>, <&clks 204>;
++ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
++ status = "disabled";
++ };
++
+ i2c4: i2c@021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+@@ -182,3 +197,54 @@
+ };
+ };
+ };
++
++&ldb {
++ clocks = <&clks 33>, <&clks 34>,
++ <&clks 39>, <&clks 40>,
++ <&clks 135>, <&clks 136>;
++ clock-names = "di0_pll", "di1_pll",
++ "di0_sel", "di1_sel",
++ "di0", "di1";
++
++ lvds-channel@0 {
++ crtcs = <&ipu1 0>, <&ipu1 1>;
++ };
++
++ lvds-channel@1 {
++ crtcs = <&ipu1 0>, <&ipu1 1>;
++ };
++};
++
++&iomuxc {
++ epdc {
++ pinctrl_epdc_0: epdcgrp-0 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000
++ MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
++ MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
++ MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
++ MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
++ MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
++ MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
++ MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000
++ MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
++ MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000
++ MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000
++ MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000
++ MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
++ MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000
++ MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
++ MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
++ MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
++ MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
++ MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
++ MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
++ >;
++ };
++ };
++};
++
++&hdmi {
++ compatible = "fsl,imx6dl-hdmi";
++ crtcs = <&ipu1 0>, <&ipu1 1>;
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-hummingboard.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-hummingboard.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,258 @@
++/*
++ * Copyright (C) 2013 Russell King
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License version 2.
++ */
++/dts-v1/;
++
++#include "imx6dl.dtsi"
++#include "imx6qdl-microsom.dtsi"
++#include "imx6qdl-microsom-ar8035.dtsi"
++
++/ {
++ model = "SolidRun HummingBoard DL/Solo";
++ compatible = "solidrun,hummingboard", "fsl,imx6dl";
++
++ aliases {
++ mxcfb0 = &mxcfb1;
++ };
++
++ ir_recv: ir-receiver {
++ compatible = "gpio-ir-receiver";
++ gpios = <&gpio1 2 1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_usbh1_vbus: usb-h1-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio1 0 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ reg_usbotg_vbus: usb-otg-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 22 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++ };
++
++ codec: spdif-transmitter {
++ compatible = "linux,spdif-dit";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_spdif>;
++ };
++
++ imx-drm {
++ compatible = "fsl,imx-drm";
++ crtcs = <&ipu1 0>, <&ipu1 1>;
++ connectors = <&hdmi>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "imx-spdif";
++ /* IMX6 doesn't implement this yet */
++ spdif-controller = <&spdif>;
++ spdif-out;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ mxcfb1: mxc_sdc_fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1280x720@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_1 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++};
++
++&flexcan1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
++ status = "okay";
++};
++
++&hdmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
++ ddc = <&i2c2>;
++ status = "okay";
++ crtcs = <&ipu1 0>;
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <1>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_hdcp_1>;
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ fsl,hdcp;
++ status = "okay";
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1_1>;
++
++ /*
++ * Not fitted on Carrier-1 board... yet
++ status = "okay";
++
++ rtc: pcf8523@68 {
++ compatible = "nxp,pcf8523";
++ reg = <0x68>;
++ };
++ */
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2_2>;
++ status = "okay";
++};
++
++&iomuxc {
++ hummingboard {
++ pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
++ MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
++ >;
++ };
++
++ pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
++ >;
++ };
++
++ pinctrl_hummingboard_hdmi: hummingboard-hdmi {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_hummingboard_spdif: hummingboard-spdif {
++ fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
++ fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
++ fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
++ >;
++ };
++
++ pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
++ >;
++ };
++ };
++};
++
++&spdif {
++ status = "okay";
++};
++
++&usbh1 {
++ vbus-supply = <&reg_usbh1_vbus>;
++ status = "okay";
++};
++
++&usbotg {
++ vbus-supply = <&reg_usbotg_vbus>;
++ status = "okay";
++};
++
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &pinctrl_hummingboard_usdhc2_aux
++ &pinctrl_hummingboard_usdhc2
++ >;
++ vmmc-supply = <&reg_3p3v>;
++ cd-gpios = <&gpio1 4 0>;
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-pinfunc.h linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-pinfunc.h
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-pinfunc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-pinfunc.h 2014-05-15 20:33:34.209842371 +0200
+@@ -14,1072 +14,1076 @@
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+-#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1
+-#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0
+-#define MX6DL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0
+-#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0
+-#define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0
+-#define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0
+-#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0
+-#define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0
+-#define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0
+-#define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0
+-#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0
+-#define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0
+-#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0
+-#define MX6DL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0
+-#define MX6DL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0
+-#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0
+-#define MX6DL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0
+-#define MX6DL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0
+-#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0
+-#define MX6DL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0
+-#define MX6DL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0
+-#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0
+-#define MX6DL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1
+-#define MX6DL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0
+-#define MX6DL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0
+-#define MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0
+-#define MX6DL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0
+-#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0
+-#define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0
+-#define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0
+-#define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0
+-#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0
+-#define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0
+-#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1
+-#define MX6DL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0
+-#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0
+-#define MX6DL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0
+-#define MX6DL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0
+-#define MX6DL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0
+-#define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0
+-#define MX6DL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0
+-#define MX6DL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0
+-#define MX6DL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0
+-#define MX6DL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0
+-#define MX6DL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0
+-#define MX6DL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
+-#define MX6DL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0
+-#define MX6DL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0
+-#define MX6DL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0
+-#define MX6DL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0
+-#define MX6DL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2
+-#define MX6DL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2
+-#define MX6DL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2
+-#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1
+-#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0
+-#define MX6DL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0
+-#define MX6DL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2
+-#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1
+-#define MX6DL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0
+-#define MX6DL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2
+-#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1
+-#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0
+-#define MX6DL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1
+-#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1
+-#define MX6DL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0
+-#define MX6DL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0
+-#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1
+-#define MX6DL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1
+-#define MX6DL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0
+-#define MX6DL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0
+-#define MX6DL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1
+-#define MX6DL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0
+-#define MX6DL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0
+-#define MX6DL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0
+-#define MX6DL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0
+-#define MX6DL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0
+-#define MX6DL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0
+-#define MX6DL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1
+-#define MX6DL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1
+-#define MX6DL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0
+-#define MX6DL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1
+-#define MX6DL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1
+-#define MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0
+-#define MX6DL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1
+-#define MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1
+-#define MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1
+-#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1
+-#define MX6DL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0
+-#define MX6DL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1
+-#define MX6DL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1
+-#define MX6DL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0
+-#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1
+-#define MX6DL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0
+-#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2
+-#define MX6DL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0
+-#define MX6DL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0
+-#define MX6DL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1
+-#define MX6DL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0
+-#define MX6DL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1
+-#define MX6DL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1
+-#define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0
+-#define MX6DL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1
+-#define MX6DL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2
+-#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1
+-#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0
+-#define MX6DL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0
+-#define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3
+-#define MX6DL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0
+-#define MX6DL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0
+-#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1
+-#define MX6DL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0
+-#define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0
+-#define MX6DL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1
+-#define MX6DL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2
+-#define MX6DL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2
+-#define MX6DL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0
+-#define MX6DL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0
+-#define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0
+-#define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0
+-#define MX6DL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0
+-#define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0
+-#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0
+-#define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0
+-#define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0
+-#define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0
+-#define MX6DL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0
+-#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0
+-#define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0
+-#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0
+-#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0
+-#define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0
+-#define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0
+-#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0
+-#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1
+-#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0
+-#define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0
+-#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0
+-#define MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0
+-#define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0
+-#define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0
+-#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0
+-#define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0
+-#define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0
+-#define MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0
+-#define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0
+-#define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0
+-#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0
+-#define MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0
+-#define MX6DL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0
+-#define MX6DL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0
+-#define MX6DL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1
+-#define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0
+-#define MX6DL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1
+-#define MX6DL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1
+-#define MX6DL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1
+-#define MX6DL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1
+-#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0
+-#define MX6DL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2
+-#define MX6DL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1
+-#define MX6DL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0
+-#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1
+-#define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1
+-#define MX6DL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0
+-#define MX6DL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0
+-#define MX6DL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0
+-#define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1
+-#define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1
+-#define MX6DL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2
+-#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0
+-#define MX6DL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1
+-#define MX6DL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1
+-#define MX6DL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1
+-#define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1
+-#define MX6DL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1
+-#define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1
+-#define MX6DL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1
+-#define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1
+-#define MX6DL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1
+-#define MX6DL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1
+-#define MX6DL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1
+-#define MX6DL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
+-#define MX6DL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
+-#define MX6DL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
+-#define MX6DL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1
+-#define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1
+-#define MX6DL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0
+-#define MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2
+-#define MX6DL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1
+-#define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1
+-#define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0
+-#define MX6DL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0
+-#define MX6DL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3
+-#define MX6DL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0
+-#define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0
+-#define MX6DL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1
+-#define MX6DL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1
+-#define MX6DL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0
+-#define MX6DL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1
+-#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0
+-#define MX6DL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0
+-#define MX6DL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0
+-#define MX6DL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1
+-#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3
+-#define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0
+-#define MX6DL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1
+-#define MX6DL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2
+-#define MX6DL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3
+-#define MX6DL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1
+-#define MX6DL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1
+-#define MX6DL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2
+-#define MX6DL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2
+-#define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0
+-#define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0
+-#define MX6DL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1
+-#define MX6DL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1
+-#define MX6DL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1
+-#define MX6DL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3
+-#define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0
+-#define MX6DL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1
+-#define MX6DL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2
+-#define MX6DL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3
+-#define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1
+-#define MX6DL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3
+-#define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3
+-#define MX6DL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1
+-#define MX6DL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3
+-#define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1
+-#define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1
+-#define MX6DL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1
+-#define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2
+-#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1
+-#define MX6DL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1
+-#define MX6DL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0
+-#define MX6DL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0
+-#define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0
+-#define MX6DL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0
+-#define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0
+-#define MX6DL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0
+-#define MX6DL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0
+-#define MX6DL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3
+-#define MX6DL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0
+-#define MX6DL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1
+-#define MX6DL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0
+-#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0
+-#define MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1
+-#define MX6DL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0
+-#define MX6DL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2
+-#define MX6DL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0
+-#define MX6DL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0
+-#define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0
+-#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2
+-#define MX6DL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1
+-#define MX6DL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1
+-#define MX6DL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1
+-#define MX6DL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1
+-#define MX6DL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1
+-#define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1
+-#define MX6DL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1
+-#define MX6DL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0
+-#define MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0
+-#define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1
+-#define MX6DL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0
+-#define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0
+-#define MX6DL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1
+-#define MX6DL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0
+-#define MX6DL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0
+-#define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0
+-#define MX6DL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0
+-#define MX6DL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0
+-#define MX6DL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0
+-#define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0
+-#define MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0
+-#define MX6DL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0
+-#define MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0
+-#define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0
+-#define MX6DL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1
+-#define MX6DL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3
+-#define MX6DL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1
+-#define MX6DL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2
+-#define MX6DL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1
+-#define MX6DL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1
+-#define MX6DL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2
+-#define MX6DL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0
+-#define MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0
+-#define MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1
+-#define MX6DL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2
+-#define MX6DL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0
+-#define MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1
+-#define MX6DL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2
+-#define MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0
+-#define MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0
+-#define MX6DL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2
+-#define MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1
+-#define MX6DL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1
+-#define MX6DL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2
+-#define MX6DL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2
+-#define MX6DL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3
+-#define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0
+-#define MX6DL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2
+-#define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0
+-#define MX6DL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3
+-#define MX6DL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1
+-#define MX6DL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4
+-#define MX6DL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4
+-#define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5
+-#define MX6DL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2
+-#define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3
+-#define MX6DL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0
+-#define MX6DL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0
+-#define MX6DL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5
+-#define MX6DL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0
+-#define MX6DL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1
+-#define MX6DL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2
+-#define MX6DL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0
+-#define MX6DL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3
+-#define MX6DL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6
+-#define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4
+-#define MX6DL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5
+-#define MX6DL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0
+-#define MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0
+-#define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0
+-#define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7
+-#define MX6DL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0
++#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0
++#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0
++#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0
++#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0
++#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1
++#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0
++#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0
++#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0
++#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0
++#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0
++#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0
++#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0
++#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0
++#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0
++#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0
++#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
++#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0
++#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0
++#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2
++#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2
++#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2
++#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1
++#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0
++#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0
++#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2
++#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1
++#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0
++#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2
++#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1
++#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0
++#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1
++#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1
++#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0
++#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0
++#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1
++#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1
++#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0
++#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0
++#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1
++#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0
++#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0
++#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0
++#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0
++#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1
++#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1
++#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1
++#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1
++#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0
++#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1
++#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1
++#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1
++#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1
++#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1
++#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1
++#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1
++#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1
++#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0
++#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2
++#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0
++#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1
++#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0
++#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1
++#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1
++#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0
++#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1
++#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2
++#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1
++#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0
++#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0
++#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3
++#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1
++#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0
++#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1
++#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2
++#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2
++#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0
++#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0
++#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0
++#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0
++#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0
++#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0
++#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0
++#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0
++#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1
++#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0
++#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0
++#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0
++#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0
++#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0
++#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0
++#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0
++#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0
++#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0
++#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0
++#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0
++#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0
++#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0
++#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1
++#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0
++#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1
++#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1
++#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1
++#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1
++#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0
++#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2
++#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1
++#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0
++#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1
++#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1
++#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0
++#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0
++#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1
++#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1
++#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2
++#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1
++#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1
++#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1
++#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1
++#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1
++#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1
++#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1
++#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1
++#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1
++#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1
++#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1
++#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
++#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
++#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
++#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1
++#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1
++#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2
++#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1
++#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1
++#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0
++#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3
++#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1
++#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1
++#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1
++#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1
++#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3
++#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0
++#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1
++#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2
++#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3
++#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1
++#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1
++#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2
++#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2
++#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0
++#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0
++#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1
++#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1
++#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1
++#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3
++#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0
++#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1
++#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2
++#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3
++#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3
++#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3
++#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3
++#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1
++#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1
++#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2
++#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0
++#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0
++#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3
++#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0
++#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1
++#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0
++#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0
++#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1
++#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0
++#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2
++#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2
++#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1
++#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1
++#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1
++#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1
++#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1
++#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1
++#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1
++#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1
++#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0
++#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1
++#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0
++#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0
++#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0
++#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0
++#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1
++#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3
++#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1
++#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2
++#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1
++#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2
++#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0
++#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2
++#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0
++#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2
++#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2
++#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1
++#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2
++#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2
++#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3
++#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2
++#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0
++#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3
++#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1
++#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4
++#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4
++#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5
++#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2
++#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3
++#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5
++#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1
++#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2
++#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0
++#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3
++#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6
++#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4
++#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5
++#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7
++#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0
+
+ #endif /* __DTS_IMX6DL_PINFUNC_H */
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabreauto.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabreauto.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabreauto.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabreauto.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -16,16 +16,15 @@
+ compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
+ };
+
+-&iomuxc {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hog>;
++&ldb {
++ ipu_id = <0>;
++ sec_ipu_id = <0>;
++};
++
++&mxcfb1 {
++ status = "okay";
++};
+
+- hog {
+- pinctrl_hog: hoggrp {
+- fsl,pins = <
+- MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+- MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
+- >;
+- };
+- };
++&mxcfb2 {
++ status = "okay";
+ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,38 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabreauto.dts"
++
++&ecspi1 {
++ status = "okay";
++};
++
++&flexcan2 {
++ /* max7310_c on i2c3 is gone */
++ status = "disabled";
++};
++
++&i2c3 {
++ /* pin conflict with ecspi1 */
++ status = "disabled";
++};
++
++&uart3 {
++ /* the uart3 depends on the i2c3, so disable it too. */
++ status = "disabled";
++};
++
++&usbh1 {
++ /* max7310_b on i2c3 is gone */
++ status = "disabled";
++};
++
++&usbotg {
++ dr_mode = "peripheral";
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabreauto.dts"
++
++&flexcan1{
++ status = "okay";
++};
++
++&fec {
++ /* pin conflict with flexcan1 */
++ status = "disabled";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabreauto.dts"
++
++&ecspi1 {
++ /* pin conflict with weim */
++ status = "disabled";
++};
++
++&flexcan2 {
++ /* max7310_c on i2c3 is gone */
++ status = "disabled";
++};
++
++&gpmi {
++ status = "okay";
++};
++
++&i2c3 {
++ /* pin conflict with weim */
++ status = "disabled";
++};
++
++&uart3 {
++ /* pin conflict with gpmi and weim */
++ status = "disabled";
++};
++
++&usbh1 {
++ /* max7310_b on i2c3 is gone */
++ status = "disabled";
++};
++
++&usbotg {
++ dr_mode = "peripheral";
++ status = "okay";
++};
++
++&weim {
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabresd.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabresd.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabresd.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabresd.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -16,20 +16,126 @@
+ compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+ };
+
++&i2c3 {
++ max17135@48 {
++ compatible = "maxim,max17135";
++ reg = <0x48>;
++ vneg_pwrup = <1>;
++ gvee_pwrup = <1>;
++ vpos_pwrup = <2>;
++ gvdd_pwrup = <1>;
++ gvdd_pwrdn = <1>;
++ vpos_pwrdn = <2>;
++ gvee_pwrdn = <1>;
++ vneg_pwrdn = <1>;
++ SENSOR-supply = <&reg_sensor>;
++ gpio_pmic_pwrgood = <&gpio2 21 0>;
++ gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
++ gpio_pmic_wakeup = <&gpio3 20 0>;
++ gpio_pmic_v3p3 = <&gpio2 20 0>;
++ gpio_pmic_intr = <&gpio2 25 0>;
++
++ regulators {
++ DISPLAY_reg: DISPLAY {
++ regulator-name = "DISPLAY";
++ };
++
++ GVDD_reg: GVDD {
++ /* 20v */
++ regulator-name = "GVDD";
++ };
++
++ GVEE_reg: GVEE {
++ /* -22v */
++ regulator-name = "GVEE";
++ };
++
++ HVINN_reg: HVINN {
++ /* -22v */
++ regulator-name = "HVINN";
++ };
++
++ HVINP_reg: HVINP {
++ /* 20v */
++ regulator-name = "HVINP";
++ };
++
++ VCOM_reg: VCOM {
++ regulator-name = "VCOM";
++ /* 2's-compliment, -4325000 */
++ regulator-min-microvolt = <0xffbe0178>;
++ /* 2's-compliment, -500000 */
++ regulator-max-microvolt = <0xfff85ee0>;
++ };
++
++ VNEG_reg: VNEG {
++ /* -15v */
++ regulator-name = "VNEG";
++ };
++
++ VPOS_reg: VPOS {
++ /* 15v */
++ regulator-name = "VPOS";
++ };
++
++ V3P3_reg: V3P3 {
++ regulator-name = "V3P3";
++ };
++ };
++ };
++};
++
+ &iomuxc {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hog>;
++ pinctrl-0 = <&pinctrl_hog_1>, <&pinctrl_hog_2>;
+
+ hog {
+- pinctrl_hog: hoggrp {
++ pinctrl_hog_2: hoggrp-2 {
+ fsl,pins = <
+- MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000
+- MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000
+- MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+- MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+- MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+- MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
++ /* MAX17135 */
++ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
++ MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x80000000
++ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
++ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x80000000
++ MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000
++ /* elan touch */
++ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000
++ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x80000000
++ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x170b0
+ >;
+ };
+ };
+ };
++
++&epdc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_epdc_0>;
++ V3P3-supply = <&V3P3_reg>;
++ VCOM-supply = <&VCOM_reg>;
++ DISPLAY-supply = <&DISPLAY_reg>;
++ status = "okay";
++};
++
++&ldb {
++ ipu_id = <0>;
++ sec_ipu_id = <0>;
++};
++
++&pxp {
++ status = "okay";
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
++
++&battery {
++ offset-charger = <1485>;
++ offset-discharger = <1464>;
++ offset-usb-charger = <1285>;
++};
++
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,19 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabresd.dts"
++
++&hdmi_video {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_hdcp_1>;
++ fsl,hdcp;
++};
++
++&i2c2 {
++ status = "disable";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabresd.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++ pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&gpc {
++ fsl,ldo-bypass = <0>; /* use ldo-bypass, u-boot will check it and configure */
++ fsl,wdog-reset = <1>; /* watchdog select of reset source */
++ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&gpu {
++ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&vpu {
++ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-wandboard.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-wandboard.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6dl-wandboard.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6dl-wandboard.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -10,6 +10,7 @@
+ */
+ /dts-v1/;
+ #include "imx6dl.dtsi"
++#include "imx6qdl-wandboard.dtsi"
+
+ / {
+ model = "Wandboard i.MX6 Dual Lite Board";
+@@ -19,26 +20,3 @@
+ reg = <0x10000000 0x40000000>;
+ };
+ };
+-
+-&fec {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_1>;
+- phy-mode = "rgmii";
+- status = "okay";
+-};
+-
+-&uart1 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart1_1>;
+- status = "okay";
+-};
+-
+-&usbh1 {
+- status = "okay";
+-};
+-
+-&usdhc3 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc3_2>;
+- status = "okay";
+-};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-arm2.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-arm2.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-arm2.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-arm2.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -31,6 +31,15 @@
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
++
++ reg_usb_otg_vbus: usb_otg_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio3 22 0>;
++ enable-active-high;
++ };
+ };
+
+ leds {
+@@ -42,6 +51,15 @@
+ linux,default-trigger = "heartbeat";
+ };
+ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif",
++ "fsl,imx-sabreauto-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ spdif-in;
++ };
+ };
+
+ &gpmi {
+@@ -57,7 +75,7 @@
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+- MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
++ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
+ >;
+ };
+ };
+@@ -65,8 +83,8 @@
+ arm2 {
+ pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
+ fsl,pins = <
+- MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
+- MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
++ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
++ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
+ >;
+ };
+ };
+@@ -79,6 +97,14 @@
+ status = "okay";
+ };
+
++&usbotg {
++ vbus-supply = <&reg_usb_otg_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg_1>;
++ disable-over-current;
++ status = "okay";
++};
++
+ &usdhc3 {
+ cd-gpios = <&gpio6 11 0>;
+ wp-gpios = <&gpio6 14 0>;
+@@ -97,6 +123,30 @@
+ status = "okay";
+ };
+
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2_2>;
++ fsl,dte-mode;
++ fsl,uart-has-rtscts;
++ status = "okay";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif_2>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2_2>;
++ fsl,dte-mode;
++ fsl,uart-has-rtscts;
++ dma-names = "rx", "tx";
++ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
++ status = "okay";
++};
++
+ &uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4_1>;
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-cubox-i.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-cubox-i.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-cubox-i.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-cubox-i.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,16 @@
++/*
++ * Copyright (C) 2014 Russell King
++ */
++/dts-v1/;
++
++#include "imx6q.dtsi"
++#include "imx6qdl-cubox-i.dtsi"
++
++/ {
++ model = "SolidRun Cubox-i Dual/Quad";
++ compatible = "solidrun,cubox-i/q", "fsl,imx6q";
++};
++
++&sata {
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,289 @@
++/*
++ * Copyright (C) 2014 Russell King
++ */
++#include "imx6qdl-microsom.dtsi"
++#include "imx6qdl-microsom-ar8035.dtsi"
++
++/ {
++ aliases {
++ mxcfb0 = &mxcfb1;
++ };
++
++ ir_recv: ir-receiver {
++ compatible = "gpio-ir-receiver";
++ gpios = <&gpio3 9 1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_ir>;
++ };
++
++ pwmleds {
++ compatible = "pwm-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_pwm1>;
++
++ front {
++ active-low;
++ default-brightness = <128>;
++ label = "imx6:red:front";
++ max-brightness = <248>;
++ pwms = <&pwm1 0 50000>;
++ };
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_usbh1_vbus: usb-h1-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio1 0 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_usbh1_vbus>;
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ reg_usbotg_vbus: usb-otg-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 22 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_usbotg_vbus>;
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++ };
++
++ codec: spdif-transmitter {
++ compatible = "linux,spdif-dit";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_spdif>;
++ };
++
++ imx-drm {
++ compatible = "fsl,imx-drm";
++ crtcs = <&ipu1 0>, <&ipu1 1>;
++ connectors = <&hdmi>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ mxcfb1: mxc_sdc_fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1280x720@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_1 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++};
++
++&hdmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_hdmi>;
++ ddc = <&i2c2>;
++ status = "okay";
++ crtcs = <&ipu1 0>;
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_hdmi>;
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <1>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_hdcp_1>;
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ fsl,hdcp;
++ status = "okay";
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2_2>;
++ status = "disable";
++};
++
++&i2c3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3_1>;
++
++ status = "okay";
++
++ rtc: pcf8523@68 {
++ compatible = "nxp,pcf8523";
++ reg = <0x68>;
++ };
++};
++
++&iomuxc {
++ cubox_i {
++ pinctrl_cubox_i_ir: cubox-i-ir {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
++ >;
++ };
++
++ pinctrl_cubox_i_hdmi: cubox-i-hdmi {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led {
++ fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0>;
++ };
++
++ pinctrl_cubox_i_spdif: cubox-i-spdif {
++ fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
++ };
++
++ pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
++ fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
++ };
++
++ pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
++ fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>;
++ };
++
++ pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
++ MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071
++ >;
++ };
++
++ pinctrl_cubox_i_usdhc2: cubox-i-usdhc2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
++ >;
++ };
++
++ pinctrl_cubox_i_usdhc2_100mhz: cubox-i-usdhc2-100mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9
++ >;
++ };
++
++ pinctrl_cubox_i_usdhc2_200mhz: cubox-i-usdhc2-200mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9
++ >;
++ };
++ };
++};
++
++&spdif {
++ status = "okay";
++};
++
++&usbh1 {
++ vbus-supply = <&reg_usbh1_vbus>;
++ status = "okay";
++};
++
++&usbotg {
++ vbus-supply = <&reg_usbotg_vbus>;
++ status = "okay";
++};
++
++&uart4 {
++ status = "okay";
++};
++
++&usdhc1 {
++ status = "disabled";
++};
++
++&uart4 {
++ status = "okay";
++};
++
++&usdhc1 {
++ status = "okay";
++};
++
++&usdhc2 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>;
++ pinctrl-1 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_100mhz>;
++ pinctrl-2 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_200mhz>;
++ vmmc-supply = <&reg_3p3v>;
++ cd-gpios = <&gpio1 4 0>;
++ no-1-8-v;
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl.dtsi 2014-05-15 20:33:34.213842400 +0200
+@@ -11,14 +11,12 @@
+ */
+
+ #include "skeleton.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+
+ / {
+ aliases {
+- serial0 = &uart1;
+- serial1 = &uart2;
+- serial2 = &uart3;
+- serial3 = &uart4;
+- serial4 = &uart5;
++ flexcan0 = &flexcan1;
++ flexcan1 = &flexcan2;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+@@ -26,6 +24,21 @@
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
++ i2c0 = &i2c1;
++ i2c1 = &i2c2;
++ i2c2 = &i2c3;
++ ipu0 = &ipu1;
++ serial0 = &uart1;
++ serial1 = &uart2;
++ serial2 = &uart3;
++ serial3 = &uart4;
++ serial4 = &uart5;
++ spi0 = &ecspi1;
++ spi1 = &ecspi2;
++ spi2 = &ecspi3;
++ spi3 = &ecspi4;
++ usbphy0 = &usbphy1;
++ usbphy1 = &usbphy2;
+ };
+
+ intc: interrupt-controller@00a01000 {
+@@ -58,6 +71,10 @@
+ };
+ };
+
++ pu_dummy: pudummy_reg {
++ compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
++ };
++
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+@@ -65,6 +82,11 @@
+ interrupt-parent = <&intc>;
+ ranges;
+
++ caam_sm: caam-sm@00100000 {
++ compatible = "fsl,imx6q-caam-sm";
++ reg = <0x00100000 0x3fff>;
++ };
++
+ dma_apbh: dma-apbh@00110000 {
+ compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x00110000 0x2000>;
+@@ -75,24 +97,35 @@
+ clocks = <&clks 106>;
+ };
+
++ irq_sec_vio: caam_secvio {
++ compatible = "fsl,imx6q-caam-secvio";
++ interrupts = <0 20 0x04>;
++ secvio_src = <0x8000001d>;
++ };
++
+ gpmi: gpmi-nand@00112000 {
+ compatible = "fsl,imx6q-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+- interrupts = <0 13 0x04>, <0 15 0x04>;
+- interrupt-names = "gpmi-dma", "bch";
++ interrupts = <0 15 0x04>;
++ interrupt-names = "bch";
+ clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+ <&clks 150>, <&clks 149>;
+ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+- fsl,gpmi-dma-channel = <0>;
+ status = "disabled";
+ };
+
++ ocram: sram@00900000 {
++ compatible = "mmio-sram";
++ reg = <0x00900000 0x3f000>;
++ clocks = <&clks 142>;
++ };
++
+ timer@00a00600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x00a00600 0x20>;
+@@ -106,6 +139,24 @@
+ interrupts = <0 92 0x04>;
+ cache-unified;
+ cache-level = <2>;
++ arm,tag-latency = <4 2 3>;
++ arm,data-latency = <4 2 3>;
++ };
++
++ pcie: pcie@0x01000000 {
++ compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
++ reg = <0x01ffc000 0x4000>; /* DBI */
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
++ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
++ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
++ num-lanes = <1>;
++ interrupts = <0 123 0x04>;
++ clocks = <&clks 189>, <&clks 187>, <&clks 144>, <&clks 212>;
++ clock-names = "pcie_ref_125m", "sata_ref_100m", "pcie_axi", "lvds_gate";
++ status = "disabled";
+ };
+
+ pmu {
+@@ -128,8 +179,24 @@
+ ranges;
+
+ spdif: spdif@02004000 {
++ compatible = "fsl,imx6q-spdif",
++ "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <0 52 0x04>;
++ dmas = <&sdma 14 18 0>,
++ <&sdma 15 18 0>;
++ dma-names = "rx", "tx";
++ clocks = <&clks 197>, <&clks 3>,
++ <&clks 197>, <&clks 107>,
++ <&clks 0>, <&clks 118>,
++ <&clks 0>, <&clks 139>,
++ <&clks 0>, <&clks 156>;
++ clock-names = "core", "rxtx0",
++ "rxtx1", "rxtx2",
++ "rxtx3", "rxtx4",
++ "rxtx5", "rxtx6",
++ "rxtx7", "dma";
++ status = "disabled";
+ };
+
+ ecspi1: ecspi@02008000 {
+@@ -182,19 +249,31 @@
+ interrupts = <0 26 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ esai: esai@02024000 {
++ compatible = "fsl,imx6q-esai";
+ reg = <0x02024000 0x4000>;
+ interrupts = <0 51 0x04>;
++ clocks = <&clks 118>, <&clks 156>;
++ clock-names = "core", "dma";
++ fsl,esai-dma-events = <24 23>;
++ fsl,flags = <1>;
++ status = "disabled";
+ };
+
+ ssi1: ssi@02028000 {
+ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+ reg = <0x02028000 0x4000>;
+ interrupts = <0 46 0x04>;
+- clocks = <&clks 178>;
++ clocks = <&clks 178>, <&clks 157>;
++ clock-names = "ipg", "baud";
++ dmas = <&sdma 37 1 0>,
++ <&sdma 38 1 0>;
++ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ fsl,ssi-dma-events = <38 37>;
+ status = "disabled";
+@@ -204,7 +283,11 @@
+ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+ reg = <0x0202c000 0x4000>;
+ interrupts = <0 47 0x04>;
+- clocks = <&clks 179>;
++ clocks = <&clks 179>, <&clks 158>;
++ clock-names = "ipg", "baud";
++ dmas = <&sdma 41 1 0>,
++ <&sdma 42 1 0>;
++ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ fsl,ssi-dma-events = <42 41>;
+ status = "disabled";
+@@ -214,15 +297,36 @@
+ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+ reg = <0x02030000 0x4000>;
+ interrupts = <0 48 0x04>;
+- clocks = <&clks 180>;
++ clocks = <&clks 180>, <&clks 159>;
++ clock-names = "ipg", "baud";
++ dmas = <&sdma 45 1 0>,
++ <&sdma 46 1 0>;
++ dma-names = "rx", "tx";
+ fsl,fifo-depth = <15>;
+ fsl,ssi-dma-events = <46 45>;
+ status = "disabled";
+ };
+
+ asrc: asrc@02034000 {
++ compatible = "fsl,imx53-asrc";
+ reg = <0x02034000 0x4000>;
+ interrupts = <0 50 0x04>;
++ clocks = <&clks 107>, <&clks 156>;
++ clock-names = "core", "dma";
++ dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>,
++ <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>;
++ dma-names = "rxa", "rxb", "rxc",
++ "txa", "txb", "txc";
++ status = "okay";
++ };
++
++ asrc_p2p: asrc_p2p {
++ compatible = "fsl,imx6q-asrc-p2p";
++ fsl,output-rate = <48000>;
++ fsl,output-width = <16>;
++ fsl,asrc-dma-rx-events = <17 18 19>;
++ fsl,asrc-dma-tx-events = <20 21 22>;
++ status = "okay";
+ };
+
+ spba@0203c000 {
+@@ -231,8 +335,18 @@
+ };
+
+ vpu: vpu@02040000 {
++ compatible = "fsl,imx6-vpu";
+ reg = <0x02040000 0x3c000>;
+- interrupts = <0 3 0x04 0 12 0x04>;
++ reg-names = "vpu_regs";
++ interrupts = <0 3 0x01>, <0 12 0x04>;
++ interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
++ clocks = <&clks 168>, <&clks 140>, <&clks 142>;
++ clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
++ iramsize = <0x21000>;
++ iram = <&ocram>;
++ resets = <&src 1>;
++ pu-supply = <&reg_pu>;
++ status = "disabled";
+ };
+
+ aipstz@0207c000 { /* AIPSTZ1 */
+@@ -275,18 +389,28 @@
+ clock-names = "ipg", "per";
+ };
+
+- can1: flexcan@02090000 {
++ flexcan1: flexcan@02090000 {
++ compatible = "fsl,imx6q-flexcan";
+ reg = <0x02090000 0x4000>;
+ interrupts = <0 110 0x04>;
++ clocks = <&clks 108>, <&clks 109>;
++ clock-names = "ipg", "per";
++ gpr = <&gpr>;
++ status = "disabled";
+ };
+
+- can2: flexcan@02094000 {
++ flexcan2: flexcan@02094000 {
++ compatible = "fsl,imx6q-flexcan";
+ reg = <0x02094000 0x4000>;
+ interrupts = <0 111 0x04>;
++ clocks = <&clks 110>, <&clks 111>;
++ clock-names = "ipg", "per";
++ gpr = <&gpr>;
++ status = "disabled";
+ };
+
+ gpt: gpt@02098000 {
+- compatible = "fsl,imx6q-gpt";
++ compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <0 55 0x04>;
+ clocks = <&clks 119>, <&clks 120>;
+@@ -459,7 +583,6 @@
+ regulator-name = "vddpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+- regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <9>;
+ anatop-vol-bit-width = <5>;
+@@ -489,11 +612,20 @@
+ };
+ };
+
++ tempmon: tempmon {
++ compatible = "fsl,imx6q-tempmon";
++ interrupts = <0 49 0x04>;
++ fsl,tempmon = <&anatop>;
++ fsl,tempmon-data = <&ocotp>;
++ clocks = <&clks 172>;
++ };
++
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <0 44 0x04>;
+ clocks = <&clks 182>;
++ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy@020ca000 {
+@@ -501,6 +633,12 @@
+ reg = <0x020ca000 0x1000>;
+ interrupts = <0 45 0x04>;
+ clocks = <&clks 183>;
++ fsl,anatop = <&anatop>;
++ };
++
++ caam_snvs: caam-snvs@020cc000 {
++ compatible = "fsl,imx6q-caam-snvs";
++ reg = <0x020cc000 0x4000>;
+ };
+
+ snvs@020cc000 {
+@@ -537,6 +675,11 @@
+ compatible = "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupts = <0 89 0x04 0 90 0x04>;
++ clocks = <&clks 122>, <&clks 74>, <&clks 121>,
++ <&clks 26>, <&clks 143>, <&clks 168>, <&clks 62>;
++ clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core",
++ "gpu2d_axi", "openvg_axi", "vpu_axi", "ipg";
++ pu-supply = <&reg_pu>;
+ };
+
+ gpr: iomuxc-gpr@020e0000 {
+@@ -544,24 +687,775 @@
+ reg = <0x020e0000 0x38>;
+ };
+
++ iomuxc: iomuxc@020e0000 {
++ compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
++ reg = <0x020e0000 0x4000>;
++
++ audmux {
++ pinctrl_audmux_1: audmux-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
++ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
++ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x130b0
++ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
++ >;
++ };
++
++ pinctrl_audmux_2: audmux-2 {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
++ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
++ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130b0
++ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
++ >;
++ };
++
++ pinctrl_audmux_3: audmux-3 {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
++ MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
++ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
++ >;
++ };
++ };
++
++ ecspi1 {
++ pinctrl_ecspi1_1: ecspi1grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
++ >;
++ };
++
++ pinctrl_ecspi1_2: ecspi1grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
++ >;
++ };
++ };
++
++ ecspi3 {
++ pinctrl_ecspi3_1: ecspi3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
++ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
++ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
++ >;
++ };
++ };
++
++ enet {
++ pinctrl_enet_1: enetgrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ >;
++ };
++
++ pinctrl_enet_2: enetgrp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ >;
++ };
++
++ pinctrl_enet_3: enetgrp-3 {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
++ >;
++ };
++ };
++
++ esai {
++ pinctrl_esai_1: esaigrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
++ MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
++ MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
++ MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
++ MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
++ MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
++ MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
++ MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
++ MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
++ >;
++ };
++
++ pinctrl_esai_2: esaigrp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
++ MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
++ MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
++ MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
++ MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
++ MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
++ MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
++ MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
++ MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
++ MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
++ >;
++ };
++ };
++
++ flexcan1 {
++ pinctrl_flexcan1_1: flexcan1grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
++ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
++ >;
++ };
++
++ pinctrl_flexcan1_2: flexcan1grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
++ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
++ >;
++ };
++ };
++
++ flexcan2 {
++ pinctrl_flexcan2_1: flexcan2grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
++ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
++ >;
++ };
++ };
++
++ gpmi-nand {
++ pinctrl_gpmi_nand_1: gpmi-nand-1 {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
++ >;
++ };
++ };
++
++ hdmi_hdcp {
++ pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
++ >;
++ };
++ };
++
++ hdmi_cec {
++ pinctrl_hdmi_cec_1: hdmicecgrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_hdmi_cec_2: hdmicecgrp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++ };
++
++ i2c1 {
++ pinctrl_i2c1_1: i2c1grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c1_2: i2c1grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c2 {
++ pinctrl_i2c2_1: i2c2grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2_2: i2c2grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2_3: i2c2grp-3 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c3 {
++ pinctrl_i2c3_1: i2c3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3_2: i2c3grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3_3: i2c3grp-3 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3_4: i2c3grp-4 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
++ >;
++ };
++ };
++
++ ipu1 {
++ pinctrl_ipu1_1: ipu1grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
++ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
++ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
++ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
++ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
++ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
++ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
++ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
++ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
++ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
++ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
++ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
++ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
++ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
++ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
++ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
++ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
++ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
++ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
++ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
++ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
++ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
++ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
++ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
++ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
++ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
++ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
++ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
++ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
++ >;
++ };
++
++ pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
++ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
++ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
++ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
++ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
++ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
++ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
++ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
++ MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
++ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
++ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
++ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
++ >;
++ };
++
++ pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
++ MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
++ MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
++ MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
++ MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
++ MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
++ MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
++ MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
++ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
++ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
++ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
++ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
++ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
++ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
++ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
++ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
++ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
++ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
++ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
++ >;
++ };
++ };
++
++ mlb {
++ pinctrl_mlb_1: mlbgrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
++ MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
++ MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
++ >;
++ };
++
++ pinctrl_mlb_2: mlbgrp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
++ MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000
++ MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000
++ >;
++ };
++ };
++
++ pwm1 {
++ pinctrl_pwm1_1: pwm1grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
++ >;
++ };
++ };
++
++ pwm3 {
++ pinctrl_pwm3_1: pwm3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
++ };
++
++ spdif {
++ pinctrl_spdif_1: spdifgrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
++ >;
++ };
++
++ pinctrl_spdif_2: spdifgrp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
++ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
++ >;
++ };
++
++ pinctrl_spdif_3: spdifgrp-3 {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
++ >;
++ };
++ };
++
++ uart1 {
++ pinctrl_uart1_1: uart1grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++ };
++
++ uart2 {
++ pinctrl_uart2_1: uart2grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
++ >;
++ };
++ };
++
++ uart3 {
++ pinctrl_uart3_1: uart3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart3_2: uart3grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
++ >;
++ };
++ };
++
++ uart4 {
++ pinctrl_uart4_1: uart4grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
++ >;
++ };
++ };
++
++ usbotg {
++ pinctrl_usbotg_1: usbotggrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg_2: usbotggrp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
++ >;
++ };
++ };
++
++ usbh2 {
++ pinctrl_usbh2_1: usbh2grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
++ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
++ >;
++ };
++
++ pinctrl_usbh2_2: usbh2grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
++ >;
++ };
++ };
++
++ usbh3 {
++ pinctrl_usbh3_1: usbh3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
++ MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
++ >;
++ };
++
++ pinctrl_usbh3_2: usbh3grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
++ >;
++ };
++ };
++
++ usdhc1 {
++ pinctrl_usdhc1_1: usdhc1grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++ MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
++ MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
++ MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
++ MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc1_2: usdhc1grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++ >;
++ };
++ };
++
++ usdhc2 {
++ pinctrl_usdhc2_1: usdhc2grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
++ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
++ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
++ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc2_2: usdhc2grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ >;
++ };
++ };
++
++ usdhc3 {
++ pinctrl_usdhc3_1: usdhc3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc3_2: usdhc3grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ >;
++ };
++ };
++
++ usdhc4 {
++ pinctrl_usdhc4_1: usdhc4grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
++ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
++ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
++ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
++ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
++ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
++ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
++ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
++ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
++ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc4_2: usdhc4grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
++ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
++ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
++ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
++ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
++ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
++ >;
++ };
++ };
++
++ weim {
++ pinctrl_weim_cs0_1: weim_cs0grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
++ >;
++ };
++
++ pinctrl_weim_nor_1: weim_norgrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
++ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
++ MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
++ /* data */
++ MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
++ MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
++ MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
++ MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
++ MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
++ MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
++ MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
++ MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
++ MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
++ MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
++ MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
++ MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
++ MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
++ MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
++ MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
++ MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
++ /* address */
++ MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
++ MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
++ MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
++ MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
++ MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
++ MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
++ MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
++ MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
++ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
++ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
++ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
++ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
++ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
++ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
++ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
++ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
++ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
++ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
++ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
++ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
++ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
++ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
++ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
++ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
++ >;
++ };
++ };
++ };
++
+ ldb: ldb@020e0008 {
+- #address-cells = <1>;
+- #size-cells = <0>;
+ compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+- gpr = <&gpr>;
++ reg = <0x020e0000 0x4000>;
++ clocks = <&clks 135>, <&clks 136>,
++ <&clks 39>, <&clks 40>,
++ <&clks 41>, <&clks 42>,
++ <&clks 184>, <&clks 185>,
++ <&clks 205>, <&clks 206>,
++ <&clks 207>, <&clks 208>;
++ clock-names = "ldb_di0", "ldb_di1",
++ "ipu1_di0_sel", "ipu1_di1_sel",
++ "ipu2_di0_sel", "ipu2_di1_sel",
++ "di0_div_3_5", "di1_div_3_5",
++ "di0_div_7", "di1_div_7",
++ "di0_div_sel", "di1_div_sel";
+ status = "disabled";
++ };
+
+- lvds-channel@0 {
+- reg = <0>;
+- crtcs = <&ipu1 0>;
+- status = "disabled";
+- };
+-
+- lvds-channel@1 {
+- reg = <1>;
+- crtcs = <&ipu1 1>;
+- status = "disabled";
+- };
++ hdmi: hdmi@0120000 {
++ reg = <0x00120000 0x9000>;
++ interrupts = <0 115 0x04>;
++ gpr = <&gpr>;
++ clocks = <&clks 123>, <&clks 124>;
++ clock-names = "iahb", "isfr";
++ status = "disabled";
+ };
+
+ dcic1: dcic@020e4000 {
+@@ -580,6 +1474,8 @@
+ interrupts = <0 2 0x04>;
+ clocks = <&clks 155>, <&clks 155>;
+ clock-names = "ipg", "ahb";
++ #dma-cells = <3>;
++ iram = <&ocram>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+ };
+@@ -591,9 +1487,29 @@
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+- caam@02100000 {
+- reg = <0x02100000 0x40000>;
+- interrupts = <0 105 0x04 0 106 0x04>;
++ crypto: caam@2100000 {
++ compatible = "fsl,sec-v4.0";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x2100000 0x40000>;
++ ranges = <0 0x2100000 0x40000>;
++ interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
++ clocks = <&clks 213>, <&clks 214>, <&clks 215>;
++ clock-names = "caam_mem", "caam_aclk", "caam_ipg";
++
++ sec_jr0: jr0@1000 {
++ compatible = "fsl,sec-v4.0-job-ring";
++ reg = <0x1000 0x1000>;
++ interrupt-parent = <&intc>;
++ interrupts = <0 105 0x4>;
++ };
++
++ sec_jr1: jr1@2000 {
++ compatible = "fsl,sec-v4.0-job-ring";
++ reg = <0x2000 0x1000>;
++ interrupt-parent = <&intc>;
++ interrupts = <0 106 0x4>;
++ };
+ };
+
+ aipstz@0217c000 { /* AIPSTZ2 */
+@@ -607,6 +1523,7 @@
+ clocks = <&clks 162>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
++ fsl,anatop = <&anatop>;
+ status = "disabled";
+ };
+
+@@ -638,7 +1555,7 @@
+ status = "disabled";
+ };
+
+- usbmisc: usbmisc: usbmisc@02184800 {
++ usbmisc: usbmisc@02184800 {
+ #index-cells = <1>;
+ compatible = "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+@@ -654,9 +1571,14 @@
+ status = "disabled";
+ };
+
+- mlb@0218c000 {
++ mlb: mlb@0218c000 {
++ compatible = "fsl,imx6q-mlb150";
+ reg = <0x0218c000 0x4000>;
+ interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
++ clocks = <&clks 139>, <&clks 175>;
++ clock-names = "mlb", "pll8_mlb";
++ iram = <&ocram>;
++ status = "disabled";
+ };
+
+ usdhc1: usdhc@02190000 {
+@@ -733,6 +1655,11 @@
+ reg = <0x021ac000 0x4000>;
+ };
+
++ mmdc0-1@021b0000 { /* MMDC0-1 */
++ compatible = "fsl,imx6q-mmdc-combine";
++ reg = <0x021b0000 0x8000>;
++ };
++
+ mmdc0: mmdc@021b0000 { /* MMDC0 */
+ compatible = "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+@@ -742,20 +1669,23 @@
+ reg = <0x021b4000 0x4000>;
+ };
+
+- weim@021b8000 {
++ weim: weim@021b8000 {
++ compatible = "fsl,imx6q-weim";
+ reg = <0x021b8000 0x4000>;
+ interrupts = <0 14 0x04>;
++ clocks = <&clks 196>;
+ };
+
+- ocotp@021bc000 {
+- compatible = "fsl,imx6q-ocotp";
++ ocotp: ocotp-ctrl@021bc000 {
++ compatible = "syscon";
+ reg = <0x021bc000 0x4000>;
+ };
+
+- ocotp@021c0000 {
+- reg = <0x021c0000 0x4000>;
+- interrupts = <0 21 0x04>;
+- };
++ ocotp-fuse@021bc000 {
++ compatible = "fsl,imx6q-ocotp";
++ reg = <0x021bc000 0x4000>;
++ clocks = <&clks 128>;
++ };
+
+ tzasc@021d0000 { /* TZASC1 */
+ reg = <0x021d0000 0x4000>;
+@@ -773,17 +1703,26 @@
+ status = "disabled";
+ };
+
+- mipi@021dc000 { /* MIPI-CSI */
++ mipi_csi: mipi_csi@021dc000 {
++ compatible = "fsl,imx6q-mipi-csi2";
+ reg = <0x021dc000 0x4000>;
+- };
+-
+- mipi@021e0000 { /* MIPI-DSI */
+- reg = <0x021e0000 0x4000>;
++ interrupts = <0 100 0x04>, <0 101 0x04>;
++ clocks = <&clks 138>, <&clks 53>;
++ /* Note: clks 138 is hsi_tx, however, the dphy_c
++ * hsi_tx and pll_refclk use the same clk gate.
++ * In current clk driver, open/close clk gate do
++ * use hsi_tx for a temporary debug purpose.
++ */
++ clock-names = "dphy_clk", "pixel_clk";
++ status = "disabled";
+ };
+
+ vdoa@021e4000 {
++ compatible = "fsl,imx6q-vdoa";
+ reg = <0x021e4000 0x4000>;
+ interrupts = <0 18 0x04>;
++ clocks = <&clks 202>;
++ iram = <&ocram>;
+ };
+
+ uart2: serial@021e8000 {
+@@ -792,6 +1731,8 @@
+ interrupts = <0 27 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+@@ -801,6 +1742,8 @@
+ interrupts = <0 28 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+@@ -810,6 +1753,8 @@
+ interrupts = <0 29 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+@@ -819,18 +1764,24 @@
+ interrupts = <0 30 0x04>;
+ clocks = <&clks 160>, <&clks 161>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+ };
+
+ ipu1: ipu@02400000 {
+- #crtc-cells = <1>;
+ compatible = "fsl,imx6q-ipu";
+ reg = <0x02400000 0x400000>;
+ interrupts = <0 6 0x4 0 5 0x4>;
+- clocks = <&clks 130>, <&clks 131>, <&clks 132>;
+- clock-names = "bus", "di0", "di1";
++ clocks = <&clks 130>, <&clks 131>, <&clks 132>,
++ <&clks 39>, <&clks 40>,
++ <&clks 135>, <&clks 136>;
++ clock-names = "bus", "di0", "di1",
++ "di0_sel", "di1_sel",
++ "ldb_di0", "ldb_di1";
+ resets = <&src 2>;
++ bypass_reset = <0>;
+ };
+ };
+ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,58 @@
++/*
++ * Copyright 2013 Russell King
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License version 2.
++ *
++ * This describes the hookup for an AR8035 to the IMX6 on the Cubox-i
++ * MicroSOM.
++ *
++ * FIXME: we need to configure PLL_ENET to produce 25MHz, but there
++ * doesn't seem to be a way to do that yet from DT. (Writing 0x2000
++ * to 0x020c80e0 phys will do this.)
++ */
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
++ phy-mode = "rgmii";
++ phy-reset-duration = <2>;
++ phy-reset-gpios = <&gpio4 15 0>;
++ status = "okay";
++};
++
++&iomuxc {
++ enet {
++ pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ /* AR8035 reset */
++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
++ /* AR8035 interrupt */
++ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000
++ /* GPIO16 -> AR8035 25MHz */
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
++ /* AR8035 pin strapping: IO voltage: pull up */
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ /* AR8035 pin strapping: PHYADDR#0: pull down */
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
++ /* AR8035 pin strapping: PHYADDR#1: pull down */
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
++ /* AR8035 pin strapping: MODE#1: pull up */
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ /* AR8035 pin strapping: MODE#3: pull up */
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ /* AR8035 pin strapping: MODE#0: pull down */
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
++ >;
++ };
++ };
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,120 @@
++/*
++ * Copyright (C) 2013,2014 Russell King
++ */
++#include <dt-bindings/gpio/gpio.h>
++/ {
++ regulators {
++ compatible = "simple-bus";
++
++ reg_brcm_osc: brcm-osc-reg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio5 5 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_osc_reg>;
++ regulator-name = "brcm_osc_reg";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-boot-on;
++ };
++
++ reg_brcm: brcm-reg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 19 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_reg>;
++ regulator-name = "brcm_reg";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <200000>;
++ };
++ };
++};
++
++&iomuxc {
++ microsom {
++ pinctrl_microsom_brcm_osc_reg: microsom-brcm-osc-reg {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_reg: microsom-brcm-reg {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_wifi: microsom-brcm-wifi {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0
++ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070
++ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070
++ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_bt: microsom-brcm-bt {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070
++ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070
++ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_uart1: microsom-uart1 {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_microsom_uart4_1: microsom-uart4 {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_microsom_usbotg: microsom-usbotg {
++ /*
++ * Similar to pinctrl_usbotg_2, but we want it
++ * pulled down for a fixed host connection.
++ */
++ fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
++ };
++ };
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_uart1>;
++ status = "okay";
++};
++
++/* UART4 - Connected to optional BRCM Wifi/BT/FM */
++&uart4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4_1>;
++ fsl,uart-has-rtscts;
++};
++
++&usbotg {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_usbotg>;
++};
++
++/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */
++&usdhc1 {
++ card-external-vcc-supply = <&reg_brcm>;
++ card-reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, <&gpio6 0 GPIO_ACTIVE_LOW>;
++ keep-power-in-suspend;
++ non-removable;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_usdhc1_2>;
++ vmmc-supply = <&reg_brcm>;
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi 2014-05-15 20:33:34.213842400 +0200
+@@ -11,9 +11,282 @@
+ */
+
+ / {
++ aliases {
++ mxcfb0 = &mxcfb1;
++ mxcfb1 = &mxcfb2;
++ mxcfb2 = &mxcfb3;
++ mxcfb3 = &mxcfb4;
++ };
++
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ home {
++ label = "Home";
++ gpios = <&gpio1 11 0>;
++ linux,code = <102>; /* KEY_HOME */
++ gpio-key,wakeup;
++ };
++
++ back {
++ label = "Back";
++ gpios = <&gpio1 12 0>;
++ linux,code = <158>; /* KEY_BACK */
++ gpio-key,wakeup;
++ };
++
++ program {
++ label = "Program";
++ gpios = <&gpio2 12 0>;
++ linux,code = <362>; /* KEY_PROGRAM */
++ gpio-key,wakeup;
++ };
++
++ volume-up {
++ label = "Volume Up";
++ gpios = <&gpio2 15 0>;
++ linux,code = <115>; /* KEY_VOLUMEUP */
++ gpio-key,wakeup;
++ };
++
++ volume-down {
++ label = "Volume Down";
++ gpios = <&gpio5 14 0>;
++ linux,code = <114>; /* KEY_VOLUMEDOWN */
++ gpio-key,wakeup;
++ };
++ };
++
++ max7310_reset: max7310-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <1>;
++ #reset-cells = <0>;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <24>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb3: fb@2 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "lcd";
++ interface_pix_fmt = "RGB565";
++ mode_str ="CLAA-WVGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb4: fb@3 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm3 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <7>;
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ reg_audio: cs42888_supply {
++ compatible = "regulator-fixed";
++ regulator-name = "cs42888_supply";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ si4763_vio1: vio1_tnr {
++ compatible = "regulator-fixed";
++ regulator-name = "vio1";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ si4763_vio2: vio2_tnr {
++ compatible = "regulator-fixed";
++ regulator-name = "vio2";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ si4763_vd: f3v3_tnr {
++ compatible = "regulator-fixed";
++ regulator-name = "vd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ si4763_va: f5v_tnr {
++ compatible = "regulator-fixed";
++ regulator-name = "va";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++
++ reg_usb_h1_vbus: usb_h1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_usb_otg_vbus: usb_otg_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++
++ sound-cs42888 {
++ compatible = "fsl,imx6-sabreauto-cs42888",
++ "fsl,imx-audio-cs42888";
++ model = "imx-cs42888";
++ esai-controller = <&esai>;
++ asrc-controller = <&asrc_p2p>;
++ audio-codec = <&codec>;
++ };
++
++ clocks {
++ codec_osc: codec_osc {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <24576000>;
++ };
++ };
++
++ sound-fm {
++ compatible = "fsl,imx-audio-si476x",
++ "fsl,imx-tuner-si476x";
++ model = "imx-radio-si4763";
++
++ ssi-controller = <&ssi2>;
++ fm-controller = <&si4763>;
++ mux-int-port = <2>;
++ mux-ext-port = <5>;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif",
++ "fsl,imx-sabreauto-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-in;
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_1 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux_3>;
++ status = "okay";
++};
++
++&ecspi1 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio3 19 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
++ status = "disabled"; /* pin conflict with WEIM NOR */
++
++ flash: m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25p32";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++};
++
++&ecspi1 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio3 19 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi1_1>;
++
++ flash: m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25p32";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
+ };
+
+ &fec {
+@@ -23,16 +296,409 @@
+ status = "okay";
+ };
+
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++ status = "okay";
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2_3>;
++ status = "okay";
++
++ egalax_ts@04 {
++ compatible = "eeti,egalax_ts";
++ reg = <0x04>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <28 2>;
++ wakeup-gpios = <&gpio2 28 0>;
++ };
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++
++ codec: cs42888@048 {
++ compatible = "cirrus,cs42888";
++ reg = <0x048>;
++ clocks = <&codec_osc 0>;
++ clock-names = "codec_osc";
++ VA-supply = <&reg_audio>;
++ VD-supply = <&reg_audio>;
++ VLS-supply = <&reg_audio>;
++ VLC-supply = <&reg_audio>;
++ };
++
++ hdmi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++
++ si4763: si4763@63 {
++ compatible = "si4761";
++ reg = <0x63>;
++ va-supply = <&si4763_va>;
++ vd-supply = <&si4763_vd>;
++ vio1-supply = <&si4763_vio1>;
++ vio2-supply = <&si4763_vio2>;
++ };
++};
++
++&i2c3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3_4>;
++ pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++
++ max7310_a: gpio@30 {
++ compatible = "maxim,max7310";
++ reg = <0x30>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7310_reset>;
++ };
++
++ max7310_b: gpio@32 {
++ compatible = "maxim,max7310";
++ reg = <0x32>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ max7310_c: gpio@34 {
++ compatible = "maxim,max7310";
++ reg = <0x34>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ mma8451@1c {
++ compatible = "fsl,mma8451";
++ reg = <0x1c>;
++ position = <3>;
++ };
++
++ mag3110@0e {
++ compatible = "fsl,mag3110";
++ reg = <0x0e>;
++ position = <2>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <29 2>;
++ };
++
++ isl29023@44 {
++ compatible = "fsl,isl29023";
++ reg = <0x44>;
++ rext = <499>;
++ interrupt-parent = <&gpio5>;
++ interrupts = <17 2>;
++ };
++
++ adv7180: adv7180@21 {
++ compatible = "adv,adv7180";
++ reg = <0x21>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_3>;
++ clocks = <&clks 201>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
++ AVDD-supply = <&reg_3p3v>; /* 1.8v */
++ DVDD-supply = <&reg_3p3v>; /* 1.8v */
++ PVDD-supply = <&reg_3p3v>; /* 1.8v */
++ pwn-gpios = <&max7310_b 2 0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ cvbs = <1>;
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++
++ hog {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
++ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
++ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
++ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000
++ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
++ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
++ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
++ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000
++ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000
++ MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x80000000
++ MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000
++ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x80000000
++ MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
++ >;
++ };
++ };
++
++ ecspi1 {
++ pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
++ >;
++ };
++ };
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif_1>;
++ status = "okay";
++};
++
++&ssi2 {
++ fsl,mode = "i2s-master";
++ status = "okay";
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart3_1>;
++ pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */
++ <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */
++ fsl,uart-has-rtscts;
++ status = "okay";
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++ status = "disabled"; /* pin conflict with uart3 */
++};
++
+ &uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4_1>;
+ status = "okay";
+ };
+
+-&usdhc3 {
++&usbh1 {
++ vbus-supply = <&reg_usb_h1_vbus>;
++ status = "okay";
++};
++
++&usbotg {
++ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg_2>;
++ imx6-usb-charger-detection;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3_1>;
++ pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
+ cd-gpios = <&gpio6 15 0>;
+ wp-gpios = <&gpio1 13 0>;
+ status = "okay";
+ };
++
++&weim {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0x08000000 0x08000000>;
++ status = "disabled"; /* pin conflict with ecspi1, i2c3 and uart3 */
++
++ nor@0,0 {
++ compatible = "cfi-flash";
++ reg = <0 0 0x02000000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ bank-width = <2>;
++ fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
++ 0x0000c000 0x1404a38e 0x00000000>;
++ };
++};
++
++&flexcan1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan1_1>;
++ pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */
++ trx-en-gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
++ status = "disabled"; /* pin conflict with fec */
++};
++
++&flexcan2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan2_1>;
++ trx-en-gpio = <&max7310_c 6 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&max7310_c 5 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&ldb {
++ ipu_id = <1>;
++ disp_id = <0>;
++ ext_ref = <1>;
++ mode = "sep0";
++ sec_ipu_id = <1>;
++ sec_disp_id = <1>;
++ status = "okay";
++};
++
++&mipi_csi {
++ status = "okay";
++ ipu_id = <0>;
++ csi_id = <1>;
++ v_channel = <0>;
++ lanes = <1>;
++};
++
++&mlb {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mlb_2>;
++ status = "okay";
++};
++
++&pcie {
++ status = "okay";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3_1>;
++ status = "okay";
++};
++
++&esai {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_esai_2>;
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <1>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_cec_1>;
++ status = "okay";
++};
++
++&gpc {
++ fsl,cpu_pupscr_sw2iso = <0xf>;
++ fsl,cpu_pupscr_sw = <0xf>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-sabresd.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2014-05-15 20:33:34.213842400 +0200
+@@ -11,10 +11,30 @@
+ */
+
+ / {
++ aliases {
++ mxcfb0 = &mxcfb1;
++ mxcfb1 = &mxcfb2;
++ mxcfb2 = &mxcfb3;
++ mxcfb3 = &mxcfb4;
++ };
++
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
++ battery: max8903@0 {
++ compatible = "fsl,max8903-charger";
++ pinctrl-names = "default";
++ dok_input = <&gpio2 24 1>;
++ uok_input = <&gpio1 27 1>;
++ chg_input = <&gpio3 23 1>;
++ flt_input = <&gpio5 2 1>;
++ fsl,dcm_always_high;
++ fsl,dc_valid;
++ fsl,usb_valid;
++ status = "okay";
++ };
++
+ regulators {
+ compatible = "simple-bus";
+
+@@ -26,29 +46,605 @@
+ gpio = <&gpio3 22 0>;
+ enable-active-high;
+ };
++
++ reg_usb_h1_vbus: usb_h1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 29 0>;
++ enable-active-high;
++ };
++
++ reg_usb_h1_vbus: usb_h1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 29 0>;
++ enable-active-high;
++ };
++
++ reg_audio: wm8962_supply {
++ compatible = "regulator-fixed";
++ regulator-name = "wm8962-supply";
++ gpio = <&gpio4 10 0>;
++ enable-active-high;
++ };
++
++ reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
++ compatible = "regulator-fixed";
++ regulator-name = "mipi_dsi_pwr_on";
++ gpio = <&gpio6 14 0>;
++ enable-active-high;
++ };
++
++ reg_sensor: sensor_supply {
++ compatible = "regulator-fixed";
++ regulator-name = "sensor-supply";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio2 31 0>;
++ startup-delay-us = <500>;
++ enable-active-high;
++ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
++ power {
++ label = "Power Button";
++ gpios = <&gpio3 29 0>;
++ linux,code = <116>; /* KEY_POWER */
++ gpio-key,wakeup;
++ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio1 4 0>;
++ gpio-key,wakeup;
+ linux,code = <115>; /* KEY_VOLUMEUP */
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio1 5 0>;
++ gpio-key,wakeup;
+ linux,code = <114>; /* KEY_VOLUMEDOWN */
+ };
+ };
++
++ imx_drm: imx-drm {
++ compatible = "fsl,imx-drm";
++ crtcs = <&ipu1 0>, <&ipu1 1>;
++ connectors = <&ldb>;
++ };
++
++ sound {
++ compatible = "fsl,imx6q-sabresd-wm8962",
++ "fsl,imx-audio-wm8962";
++ model = "wm8962-audio";
++ ssi-controller = <&ssi2>;
++ audio-codec = <&codec>;
++ audio-routing =
++ "Headphone Jack", "HPOUTL",
++ "Headphone Jack", "HPOUTR",
++ "Ext Spk", "SPKOUTL",
++ "Ext Spk", "SPKOUTR",
++ "MICBIAS", "AMIC",
++ "IN3R", "MICBIAS",
++ "DMIC", "MICBIAS",
++ "DMICDAT", "DMIC";
++ mux-int-port = <2>;
++ mux-ext-port = <3>;
++ hp-det-gpios = <&gpio7 8 1>;
++ mic-det-gpios = <&gpio1 9 1>;
++ };
++
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm1 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <7>;
++ status = "okay";
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <24>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb3: fb@2 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "lcd";
++ interface_pix_fmt = "RGB565";
++ mode_str ="CLAA-WVGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb4: fb@3 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ lcd@0 {
++ compatible = "fsl,lcd";
++ ipu_id = <0>;
++ disp_id = <0>;
++ default_ifmt = "RGB565";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_1>;
++ status = "okay";
++ };
++
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm1 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <7>;
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_1 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++
++ lvds_cabc_ctrl {
++ lvds0-gpios = <&gpio6 15 0>;
++ lvds1-gpios = <&gpio6 16 0>;
++ };
++
++ mipi_dsi_reset: mipi-dsi-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <50>;
++ #reset-cells = <0>;
++ };
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux_2>;
++ status = "okay";
++};
++
++&cpu0 {
++ arm-supply = <&sw1a_reg>;
++ soc-supply = <&sw1c_reg>;
++ pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&ecspi1 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio4 9 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi1_2>;
++ status = "okay";
++
++ flash: m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25p32";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
+ };
+
+ &fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet_1>;
+ phy-mode = "rgmii";
++ phy-reset-gpios = <&gpio1 25 0>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1_2>;
++ status = "okay";
++
++ codec: wm8962@1a {
++ compatible = "wlf,wm8962";
++ reg = <0x1a>;
++ clocks = <&clks 201>;
++ DCVDD-supply = <&reg_audio>;
++ DBVDD-supply = <&reg_audio>;
++ AVDD-supply = <&reg_audio>;
++ CPVDD-supply = <&reg_audio>;
++ MICVDD-supply = <&reg_audio>;
++ PLLVDD-supply = <&reg_audio>;
++ SPKVDD1-supply = <&reg_audio>;
++ SPKVDD2-supply = <&reg_audio>;
++ amic-mono;
++ gpio-cfg = <
++ 0x0000 /* 0:Default */
++ 0x0000 /* 1:Default */
++ 0x0013 /* 2:FN_DMICCLK */
++ 0x0000 /* 3:Default */
++ 0x8014 /* 4:FN_DMICCDAT */
++ 0x0000 /* 5:Default */
++ >;
++ };
++
++ ov564x: ov564x@3c {
++ compatible = "ovti,ov564x";
++ reg = <0x3c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_2>;
++ clocks = <&clks 201>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
++ AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3,
++ on rev B board is VGEN5 */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */
++ rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ };
++
++ mma8451@1c {
++ compatible = "fsl,mma8451";
++ reg = <0x1c>;
++ position = <1>;
++ vdd-supply = <&reg_sensor>;
++ vddio-supply = <&reg_sensor>;
++ };
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3_2>;
++ status = "okay";
++
++ egalax_ts@04 {
++ compatible = "eeti,egalax_ts";
++ reg = <0x04>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <7 2>;
++ wakeup-gpios = <&gpio6 7 0>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2_2>;
++ status = "okay";
++
++ hdmi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++
++ max11801@48 {
++ compatible = "maxim,max11801";
++ reg = <0x48>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <26 2>;
++ work-mode = <1>;/*DCM mode*/
++ };
++
++ ov5640_mipi: ov5640_mipi@3c { /* i2c2 driver */
++ compatible = "ovti,ov5640_mipi";
++ reg = <0x3c>;
++ clocks = <&clks 201>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
++ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
++ rev B board is VGEN5 */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */
++ rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */
++ csi_id = <1>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ };
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++
++ egalax_ts@04 {
++ compatible = "eeti,egalax_ts";
++ reg = <0x04>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <8 2>;
++ wakeup-gpios = <&gpio6 8 0>;
++ };
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3_2>;
++ status = "okay";
++
++ egalax_ts@04 {
++ compatible = "eeti,egalax_ts";
++ reg = <0x04>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <7 2>;
++ wakeup-gpios = <&gpio6 7 0>;
++ };
++
++ mag3110@0e {
++ compatible = "fsl,mag3110";
++ reg = <0x0e>;
++ position = <2>;
++ vdd-supply = <&reg_sensor>;
++ vddio-supply = <&reg_sensor>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <16 2>;
++ };
++
++ elan@10 {
++ compatible = "elan,elan-touch";
++ reg = <0x10>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <28 3>;
++ gpio_elan_cs = <&gpio2 18 0>;
++ gpio_elan_rst = <&gpio3 8 0>;
++ gpio_intr = <&gpio3 28 0>;
++ status = "okay";
++ };
++
++ isl29023@44 {
++ compatible = "fsl,isl29023";
++ reg = <0x44>;
++ rext = <499>;
++ vdd-supply = <&reg_sensor>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <9 2>;
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog_1>;
++
++ hog {
++ pinctrl_hog_1: hoggrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
++ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
++ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
++ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
++ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
++ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
++ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
++ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
++ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
++ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
++ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
++ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
++ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
++ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
++ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
++ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
++ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
++ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
++ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
++ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
++ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
++ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
++ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
++ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
++ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
++ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
++ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
++ MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
++ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
++ >;
++ };
++ };
++};
++
++&ldb {
++ status = "okay";
++
++ lvds-channel@1 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ status = "okay";
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm0_1>;
++ status = "okay";
++};
++
++&ldb {
++ ipu_id = <1>;
++ disp_id = <1>;
++ ext_ref = <1>;
++ mode = "sep1";
++ sec_ipu_id = <1>;
++ sec_disp_id = <0>;
++ status = "okay";
++};
++
++&pcie {
++ power-on-gpio = <&gpio3 19 0>;
++ reset-gpio = <&gpio7 12 0>;
++ status = "okay";
++};
++
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm1_1>;
++ status = "okay";
++};
++
++&ssi2 {
++ fsl,mode = "i2s-slave";
+ status = "okay";
+ };
+
+@@ -58,7 +654,25 @@
+ status = "okay";
+ };
+
++&mipi_csi {
++ status = "okay";
++ ipu_id = <0>;
++ csi_id = <1>;
++ v_channel = <0>;
++ lanes = <2>;
++};
++
++&mipi_dsi {
++ dev_id = <0>;
++ disp_id = <0>;
++ lcd_panel = "TRULY-WVGA";
++ disp-power-on-supply = <&reg_mipi_dsi_pwr_on>;
++ resets = <&mipi_dsi_reset>;
++ status = "okay";
++};
++
+ &usbh1 {
++ vbus-supply = <&reg_usb_h1_vbus>;
+ status = "okay";
+ };
+
+@@ -73,15 +687,68 @@
+ &usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_1>;
++ bus-width = <8>;
+ cd-gpios = <&gpio2 2 0>;
+ wp-gpios = <&gpio2 3 0>;
++ no-1-8-v;
+ status = "okay";
+ };
+
+ &usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3_1>;
++ bus-width = <8>;
+ cd-gpios = <&gpio2 0 0>;
+ wp-gpios = <&gpio2 1 0>;
++ no-1-8-v;
++ status = "okay";
++};
++
++&usdhc4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc4_1>;
++ bus-width = <8>;
++ non-removable;
++ no-1-8-v;
++ status = "okay";
++};
++
++&vpu {
++ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_cec_2>;
+ status = "okay";
+ };
++
++&gpc {
++ fsl,cpu_pupscr_sw2iso = <0xf>;
++ fsl,cpu_pupscr_sw = <0xf>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++ fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
++ fsl,wdog-reset = <2>; /* watchdog select of reset source */
++ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&gpu {
++ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q.dtsi 2014-05-15 20:33:34.213842400 +0200
+@@ -8,15 +8,19 @@
+ *
+ */
+
+-#include "imx6qdl.dtsi"
+ #include "imx6q-pinfunc.h"
++#include "imx6qdl.dtsi"
+
+ / {
++ aliases {
++ ipu1 = &ipu2;
++ };
++
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- cpu@0 {
++ cpu0: cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+@@ -25,8 +29,17 @@
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1250000
++ 852000 1250000
+ 792000 1150000
+- 396000 950000
++ 396000 975000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 1200000 1275000
++ 996000 1250000
++ 852000 1250000
++ 792000 1175000
++ 396000 1175000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ clocks = <&clks 104>, <&clks 6>, <&clks 16>,
+@@ -61,6 +74,77 @@
+ };
+
+ soc {
++
++ busfreq { /* BUSFREQ */
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
++ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
++ interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
++ interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
++ fsl,max_ddr_freq = <528000000>;
++ };
++
++ gpu: gpu@00130000 {
++ compatible = "fsl,imx6q-gpu";
++ reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
++ <0x02204000 0x4000>, <0x0 0x0>;
++ reg-names = "iobase_3d", "iobase_2d",
++ "iobase_vg", "phys_baseaddr";
++ interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>;
++ interrupt-names = "irq_3d", "irq_2d", "irq_vg";
++ clocks = <&clks 26>, <&clks 143>,
++ <&clks 27>, <&clks 121>,
++ <&clks 122>, <&clks 74>;
++ clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
++ "gpu3d_axi_clk", "gpu2d_clk",
++ "gpu3d_clk", "gpu3d_shader_clk";
++ resets = <&src 0>, <&src 3>, <&src 3>;
++ reset-names = "gpu3d", "gpu2d", "gpuvg";
++ pu-supply = <&reg_pu>;
++ };
++
++ ocram: sram@00900000 {
++ compatible = "mmio-sram";
++ reg = <0x00900000 0x40000>;
++ clocks = <&clks 142>;
++ };
++
++ hdmi_core: hdmi_core@00120000 {
++ compatible = "fsl,imx6q-hdmi-core";
++ reg = <0x00120000 0x9000>;
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ status = "disabled";
++ };
++
++ hdmi_video: hdmi_video@020e0000 {
++ compatible = "fsl,imx6q-hdmi-video";
++ reg = <0x020e0000 0x1000>;
++ reg-names = "hdmi_gpr";
++ interrupts = <0 115 0x04>;
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ status = "disabled";
++ };
++
++ hdmi_audio: hdmi_audio@00120000 {
++ compatible = "fsl,imx6q-hdmi-audio";
++ clocks = <&clks 124>, <&clks 123>;
++ clock-names = "hdmi_isfr", "hdmi_iahb";
++ dmas = <&sdma 2 22 0>;
++ dma-names = "tx";
++ status = "disabled";
++ };
++
++ hdmi_cec: hdmi_cec@00120000 {
++ compatible = "fsl,imx6q-hdmi-cec";
++ interrupts = <0 115 0x04>;
++ status = "disabled";
++ };
++
++
+ aips-bus@02000000 { /* AIPS1 */
+ spba-bus@02000000 {
+ ecspi5: ecspi@02018000 {
+@@ -75,288 +159,91 @@
+ };
+ };
+
++ vpu@02040000 {
++ status = "okay";
++ };
++
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6q-iomuxc";
+- reg = <0x020e0000 0x4000>;
+-
+- /* shared pinctrl settings */
+- audmux {
+- pinctrl_audmux_1: audmux-1 {
+- fsl,pins = <
+- MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
+- MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
+- MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
+- MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
+- >;
+- };
+-
+- pinctrl_audmux_2: audmux-2 {
+- fsl,pins = <
+- MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
+- MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
+- MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
+- MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+- >;
+- };
+- };
+-
+- ecspi1 {
+- pinctrl_ecspi1_1: ecspi1grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+- MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+- MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+- >;
+- };
+- };
+-
+- ecspi3 {
+- pinctrl_ecspi3_1: ecspi3grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+- MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+- MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+- >;
+- };
+- };
+-
+- enet {
+- pinctrl_enet_1: enetgrp-1 {
+- fsl,pins = <
+- MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+- MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+- MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+- MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+- MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+- MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+- MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+- MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+- MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+- MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+- MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+- MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+- MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+- >;
+- };
+-
+- pinctrl_enet_2: enetgrp-2 {
+- fsl,pins = <
+- MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
+- MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
+- MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+- MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+- MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+- MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+- MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+- MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+- MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+- MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+- MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+- MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+- MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+- MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+- MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+- >;
+- };
+- };
+-
+- gpmi-nand {
+- pinctrl_gpmi_nand_1: gpmi-nand-1 {
+- fsl,pins = <
+- MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+- MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+- MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+- MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
+- MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+- MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+- MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
+- MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
+- MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+- MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+- MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+- MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+- MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+- MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+- MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+- MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+- MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+- MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+- MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
+- >;
+- };
+- };
+-
+- i2c1 {
+- pinctrl_i2c1_1: i2c1grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+- MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+- >;
+- };
+- };
+-
+- i2c2 {
+- pinctrl_i2c2_1: i2c2grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+- MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+- >;
+- };
+- };
+-
+- i2c3 {
+- pinctrl_i2c3_1: i2c3grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+- MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+- >;
+- };
+- };
+-
+- uart1 {
+- pinctrl_uart1_1: uart1grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+- MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+- >;
+- };
+- };
+-
+- uart2 {
+- pinctrl_uart2_1: uart2grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+- MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+- >;
+- };
+- };
+-
+- uart4 {
+- pinctrl_uart4_1: uart4grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+- MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+- >;
+- };
+- };
+-
+- usbotg {
+- pinctrl_usbotg_1: usbotggrp-1 {
+- fsl,pins = <
+- MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg_2: usbotggrp-2 {
+- fsl,pins = <
+- MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+- >;
+- };
+- };
+-
+- usdhc2 {
+- pinctrl_usdhc2_1: usdhc2grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
+- MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
+- MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
+- MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
+- MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
+- MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+- MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
+- MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
+- MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
+- MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
+- >;
+- };
+- };
+-
+- usdhc3 {
+- pinctrl_usdhc3_1: usdhc3grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
+- MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
+- MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
+- MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
+- MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
+- MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
+- MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
+- MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
+- MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
+- MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc3_2: usdhc3grp-2 {
+- fsl,pins = <
+- MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
+- MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
+- MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
+- MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
+- MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
+- MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
+- >;
+- };
+- };
++ };
++ };
+
+- usdhc4 {
+- pinctrl_usdhc4_1: usdhc4grp-1 {
+- fsl,pins = <
+- MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
+- MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
+- MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
+- MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
+- MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
+- MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
+- MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
+- MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
+- MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
+- MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc4_2: usdhc4grp-2 {
+- fsl,pins = <
+- MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
+- MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
+- MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
+- MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
+- MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
+- MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
+- >;
+- };
+- };
++ aips-bus@02100000 { /* AIPS2 */
++ mipi_dsi: mipi@021e0000 {
++ compatible = "fsl,imx6q-mipi-dsi";
++ reg = <0x021e0000 0x4000>;
++ interrupts = <0 102 0x04>;
++ gpr = <&gpr>;
++ clocks = <&clks 138>, <&clks 204>;
++ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
++ status = "disabled";
+ };
+ };
+
++ sata: sata@02200000 {
++ compatible = "fsl,imx6q-ahci";
++ reg = <0x02200000 0x4000>;
++ interrupts = <0 39 0x04>;
++ clocks = <&clks 154>, <&clks 187>, <&clks 105>;
++ clock-names = "sata", "sata_ref", "ahb";
++ status = "disabled";
++ };
++
+ ipu2: ipu@02800000 {
+- #crtc-cells = <1>;
+ compatible = "fsl,imx6q-ipu";
+ reg = <0x02800000 0x400000>;
+ interrupts = <0 8 0x4 0 7 0x4>;
+- clocks = <&clks 133>, <&clks 134>, <&clks 137>;
+- clock-names = "bus", "di0", "di1";
++ clocks = <&clks 133>, <&clks 134>, <&clks 137>,
++ <&clks 41>, <&clks 42>,
++ <&clks 135>, <&clks 136>;
++ clock-names = "bus", "di0", "di1",
++ "di0_sel", "di1_sel",
++ "ldb_di0", "ldb_di1";
+ resets = <&src 4>;
++ bypass_reset = <0>;
+ };
+ };
+ };
+
+-&ldb {
+- clocks = <&clks 33>, <&clks 34>,
+- <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
+- <&clks 135>, <&clks 136>;
+- clock-names = "di0_pll", "di1_pll",
+- "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+- "di0", "di1";
+-
+- lvds-channel@0 {
+- crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
++&iomuxc {
++ ipu2 {
++ pinctrl_ipu2_1: ipu2grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
++ MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
++ MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
++ MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
++ MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
++ MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
++ MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
++ MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
++ MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
++ MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
++ MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
++ MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
++ MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
++ MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
++ MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
++ MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
++ MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
++ MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
++ MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
++ MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
++ MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
++ MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
++ MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
++ MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
++ MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
++ MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
++ MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
++ MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
++ MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
++ >;
++ };
+ };
++};
+
+- lvds-channel@1 {
+- crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+- };
++&hdmi {
++ compatible = "fsl,imx6q-hdmi";
++ crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-pinfunc.h linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-pinfunc.h
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-pinfunc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-pinfunc.h 2014-05-15 20:33:34.209842371 +0200
+@@ -14,1028 +14,1032 @@
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+-#define MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
+-#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
+-#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
+-#define MX6Q_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
+-#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
+-#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
+-#define MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
+-#define MX6Q_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0
+-#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
+-#define MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0
+-#define MX6Q_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0
+-#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0
+-#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
+-#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0
+-#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
+-#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
+-#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0
+-#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0
+-#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
+-#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
+-#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0
+-#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0
+-#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0
+-#define MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0
+-#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0
+-#define MX6Q_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0
+-#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0
+-#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0
+-#define MX6Q_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0
+-#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0
+-#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0
+-#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0
+-#define MX6Q_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0
+-#define MX6Q_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0
+-#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0
+-#define MX6Q_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0
+-#define MX6Q_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0
+-#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0
+-#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0
+-#define MX6Q_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0
+-#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0
+-#define MX6Q_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0
+-#define MX6Q_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0
+-#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0
+-#define MX6Q_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1
+-#define MX6Q_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0
+-#define MX6Q_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0
+-#define MX6Q_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0
+-#define MX6Q_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0
+-#define MX6Q_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0
+-#define MX6Q_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
+-#define MX6Q_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0
+-#define MX6Q_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
+-#define MX6Q_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0
+-#define MX6Q_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
+-#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0
+-#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0
+-#define MX6Q_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
+-#define MX6Q_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0
+-#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0
+-#define MX6Q_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0
+-#define MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0
+-#define MX6Q_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0
+-#define MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1
+-#define MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0
+-#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0
+-#define MX6Q_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0
+-#define MX6Q_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
+-#define MX6Q_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
+-#define MX6Q_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
+-#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
+-#define MX6Q_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0
+-#define MX6Q_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3
+-#define MX6Q_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0
+-#define MX6Q_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
+-#define MX6Q_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
+-#define MX6Q_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0
+-#define MX6Q_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0
+-#define MX6Q_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
+-#define MX6Q_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
+-#define MX6Q_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
+-#define MX6Q_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
+-#define MX6Q_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
+-#define MX6Q_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
+-#define MX6Q_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
+-#define MX6Q_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
+-#define MX6Q_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
+-#define MX6Q_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
+-#define MX6Q_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
+-#define MX6Q_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
+-#define MX6Q_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
+-#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0
+-#define MX6Q_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
+-#define MX6Q_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
+-#define MX6Q_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
+-#define MX6Q_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
+-#define MX6Q_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
+-#define MX6Q_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0
+-#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0
+-#define MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0
+-#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0
+-#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
+-#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
+-#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
+-#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0
+-#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0
+-#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0
+-#define MX6Q_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
+-#define MX6Q_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0
+-#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
+-#define MX6Q_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0
+-#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0
+-#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0
+-#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0
+-#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0
+-#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0
+-#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0
+-#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0
+-#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0
+-#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0
+-#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
+-#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1
+-#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0
+-#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
+-#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0
+-#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
+-#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
+-#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0
+-#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
+-#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
+-#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1
+-#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
+-#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1
+-#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0
+-#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1
+-#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
+-#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
+-#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
+-#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0
+-#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
+-#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0
+-#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
+-#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
+-#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0
+-#define MX6Q_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0
+-#define MX6Q_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0
+-#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
+-#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0
+-#define MX6Q_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
+-#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1
+-#define MX6Q_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
+-#define MX6Q_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0
+-#define MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
+-#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
+-#define MX6Q_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1
+-#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
+-#define MX6Q_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1
+-#define MX6Q_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
+-#define MX6Q_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0
+-#define MX6Q_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
+-#define MX6Q_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
+-#define MX6Q_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1
+-#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
+-#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1
+-#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
+-#define MX6Q_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1
+-#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
+-#define MX6Q_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1
+-#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1
+-#define MX6Q_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
+-#define MX6Q_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1
+-#define MX6Q_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
+-#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
+-#define MX6Q_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1
+-#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0
+-#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0
+-#define MX6Q_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
+-#define MX6Q_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0
+-#define MX6Q_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0
+-#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0
+-#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0
+-#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
+-#define MX6Q_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0
+-#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0
+-#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1
+-#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0
+-#define MX6Q_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
+-#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1
+-#define MX6Q_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
+-#define MX6Q_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
+-#define MX6Q_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1
+-#define MX6Q_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
+-#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1
+-#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1
+-#define MX6Q_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
+-#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
+-#define MX6Q_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
+-#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
+-#define MX6Q_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
+-#define MX6Q_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1
+-#define MX6Q_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
+-#define MX6Q_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
+-#define MX6Q_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
+-#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1
+-#define MX6Q_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
+-#define MX6Q_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1
+-#define MX6Q_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
+-#define MX6Q_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
+-#define MX6Q_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
+-#define MX6Q_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
+-#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
+-#define MX6Q_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1
+-#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
+-#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1
+-#define MX6Q_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3
+-#define MX6Q_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
+-#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
+-#define MX6Q_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
+-#define MX6Q_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
+-#define MX6Q_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
+-#define MX6Q_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0
+-#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
+-#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1
+-#define MX6Q_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
+-#define MX6Q_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
+-#define MX6Q_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
+-#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
+-#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
+-#define MX6Q_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
+-#define MX6Q_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
+-#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
+-#define MX6Q_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
+-#define MX6Q_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
+-#define MX6Q_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
+-#define MX6Q_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
+-#define MX6Q_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
+-#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
+-#define MX6Q_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0
+-#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
+-#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1
+-#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0
+-#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
+-#define MX6Q_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1
+-#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0
+-#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
+-#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0
+-#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
+-#define MX6Q_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1
+-#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
+-#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1
+-#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
+-#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
+-#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1
+-#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3
+-#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3
+-#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1
+-#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
+-#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0
+-#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0
+-#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0
+-#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0
+-#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0
+-#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3
+-#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
+-#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3
+-#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4
+-#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5
+-#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
+-#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
+-#define MX6Q_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3
+-#define MX6Q_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
+-#define MX6Q_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
+-#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
+-#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3
+-#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
+-#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4
+-#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0
+-#define MX6Q_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0
+-#define MX6Q_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5
+-#define MX6Q_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0
+-#define MX6Q_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
+-#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
+-#define MX6Q_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0
+-#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0
+-#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0
+-#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
+-#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0
+-#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0
+-#define MX6Q_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0
+-#define MX6Q_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
+-#define MX6Q_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0
+-#define MX6Q_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
+-#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0
+-#define MX6Q_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0
+-#define MX6Q_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0
+-#define MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
+-#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
+-#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
+-#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0
+-#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
+-#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
+-#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1
+-#define MX6Q_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
+-#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1
+-#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0
+-#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
+-#define MX6Q_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0
+-#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0
+-#define MX6Q_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0
+-#define MX6Q_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
+-#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1
+-#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
+-#define MX6Q_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0
+-#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0
+-#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
+-#define MX6Q_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
+-#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
+-#define MX6Q_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
+-#define MX6Q_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1
+-#define MX6Q_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
+-#define MX6Q_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1
+-#define MX6Q_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1
+-#define MX6Q_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
+-#define MX6Q_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1
+-#define MX6Q_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0
+-#define MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0
+-#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0
+-#define MX6Q_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
+-#define MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1
+-#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
++#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
++#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
++#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
++#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
++#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
++#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
++#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0
++#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
++#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0
++#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0
++#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0
++#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
++#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0
++#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
++#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
++#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0
++#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
++#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
++#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0
++#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0
++#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0
++#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0
++#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0
++#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0
++#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0
++#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0
++#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0
++#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0
++#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0
++#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0
++#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0
++#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0
++#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0
++#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0
++#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0
++#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0
++#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0
++#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0
++#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0
++#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0
++#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0
++#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0
++#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1
++#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0
++#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0
++#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0
++#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0
++#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0
++#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
++#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0
++#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
++#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0
++#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0
++#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0
++#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
++#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0
++#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0
++#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0
++#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0
++#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0
++#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1
++#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0
++#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
++#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
++#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1
++#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
++#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
++#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0
++#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3
++#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0
++#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
++#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
++#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0
++#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0
++#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
++#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
++#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
++#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
++#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
++#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
++#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
++#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
++#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
++#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
++#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
++#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
++#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
++#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0
++#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
++#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
++#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
++#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
++#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
++#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0
++#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0
++#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0
++#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0
++#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0
++#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0
++#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0
++#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
++#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0
++#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
++#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0
++#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0
++#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0
++#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0
++#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0
++#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0
++#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0
++#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
++#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1
++#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0
++#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
++#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
++#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x004 0x0 0xff0d0100
++#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
++#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
++#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1
++#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
++#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1
++#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0
++#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1
++#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
++#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
++#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
++#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0
++#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
++#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0
++#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
++#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
++#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0
++#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0
++#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0
++#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
++#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0
++#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
++#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1
++#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
++#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0
++#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
++#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
++#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1
++#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
++#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0
++#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
++#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
++#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1
++#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
++#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1
++#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
++#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1
++#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1
++#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
++#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1
++#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
++#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
++#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0
++#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0
++#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
++#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0
++#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0
++#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0
++#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0
++#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
++#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0
++#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0
++#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1
++#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0
++#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
++#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1
++#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
++#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
++#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x004 0x3 0xff0d0101
++#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1
++#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
++#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1
++#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1
++#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
++#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
++#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
++#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
++#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
++#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1
++#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
++#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
++#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
++#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1
++#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
++#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1
++#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
++#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
++#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
++#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
++#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1
++#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1
++#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3
++#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
++#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
++#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
++#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
++#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
++#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0
++#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
++#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1
++#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
++#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
++#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
++#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
++#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
++#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
++#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
++#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
++#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
++#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
++#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
++#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
++#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
++#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
++#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
++#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0
++#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
++#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1
++#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
++#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1
++#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
++#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
++#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3
++#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3
++#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1
++#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
++#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0
++#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0
++#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0
++#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0
++#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0
++#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3
++#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
++#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3
++#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4
++#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5
++#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
++#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
++#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3
++#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
++#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
++#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
++#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3
++#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
++#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4
++#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0
++#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0
++#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5
++#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0
++#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
++#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
++#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0
++#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0
++#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0
++#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
++#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0
++#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0
++#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0
++#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
++#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0
++#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
++#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0
++#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0
++#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0
++#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
++#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
++#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
++#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0
++#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
++#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
++#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1
++#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1
++#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0
++#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0
++#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0
++#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0
++#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1
++#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
++#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0
++#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0
++#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
++#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
++#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
++#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
++#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1
++#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
++#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1
++#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1
++#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
++#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1
++#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0
++#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0
++#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0
++#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
++#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1
++#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0
+
+ #endif /* __DTS_IMX6Q_PINFUNC_H */
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabreauto.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabreauto.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabreauto.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabreauto.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -20,16 +20,22 @@
+ compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+ };
+
+-&iomuxc {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hog>;
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
++
++&mxcfb3 {
++ status = "okay";
++};
++
++&mxcfb4 {
++ status = "okay";
++};
+
+- hog {
+- pinctrl_hog: hoggrp {
+- fsl,pins = <
+- MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
+- MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
+- >;
+- };
+- };
++&sata {
++ status = "okay";
+ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts 2014-05-15 20:33:34.209842371 +0200
+@@ -0,0 +1,39 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabreauto.dts"
++
++&ecspi1 {
++ status = "okay";
++};
++
++&flexcan2 {
++ /* max7310_c on i2c3 is gone */
++ status = "disabled";
++};
++
++&i2c3 {
++ /* pin conflict with ecspi1 */
++ status = "disabled";
++};
++
++&uart3 {
++ /* the uart3 depends on the i2c3, so disable it too. */
++ status = "disabled";
++};
++
++&usbh1 {
++ /* max7310_b on i2c3 is gone */
++ status = "disabled";
++};
++
++&usbotg {
++ /* max7310_c on i2c3 is gone */
++ status = "okay";
++ dr_mode = "peripheral";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabreauto.dts"
++
++&flexcan1{
++ status = "okay";
++};
++
++&fec {
++ /* pin conflict with flexcan1 */
++ status = "disabled";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,48 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabreauto.dts"
++
++&ecspi1 {
++ /* pin conflict with weim */
++ status = "disabled";
++};
++
++&flexcan2 {
++ /* max7310_c on i2c3 is gone */
++ status = "disabled";
++};
++
++&gpmi {
++ status = "okay";
++};
++
++&i2c3 {
++ /* pin conflict with weim */
++ status = "disabled";
++};
++
++&uart3 {
++ /* pin conflict with gpmi and weim */
++ status = "disabled";
++};
++
++&usbh1 {
++ /* max7310_b on i2c3 is gone */
++ status = "disabled";
++};
++
++&usbotg {
++ /* max7310_c on i2c3 is gone */
++ status = "okay";
++ dr_mode = "peripheral";
++};
++
++&weim {
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabrelite.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabrelite.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabrelite.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabrelite.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -65,6 +65,12 @@
+ };
+ };
+
++&audmux {
++ status = "okay";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux_1>;
++};
++
+ &ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 19 0>;
+@@ -79,9 +85,27 @@
+ };
+ };
+
+-&ssi1 {
+- fsl,mode = "i2s-slave";
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet_1>;
++ phy-mode = "rgmii";
++ phy-reset-gpios = <&gpio3 23 0>;
++ status = "okay";
++};
++
++&i2c1 {
+ status = "okay";
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1_1>;
++
++ codec: sgtl5000@0a {
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ clocks = <&clks 201>;
++ VDDA-supply = <&reg_2p5v>;
++ VDDIO-supply = <&reg_3p3v>;
++ };
+ };
+
+ &iomuxc {
+@@ -91,36 +115,69 @@
+ hog {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+- MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
+- MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
+- MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
+- MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
+- MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
+- MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
+- MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
+- MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
++ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
++ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
++ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
++ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
++ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
++ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
++ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+ >;
+ };
+ };
+ };
+
+-&usbotg {
+- vbus-supply = <&reg_usb_otg_vbus>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usbotg_1>;
+- disable-over-current;
++&ldb {
++ status = "okay";
++
++ lvds-channel@0 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ status = "okay";
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&sata {
+ status = "okay";
+ };
+
++&ssi1 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2_1>;
++};
++
+ &usbh1 {
+ status = "okay";
+ };
+
+-&fec {
++&usbotg {
++ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_1>;
+- phy-mode = "rgmii";
+- phy-reset-gpios = <&gpio3 23 0>;
++ pinctrl-0 = <&pinctrl_usbotg_1>;
++ disable-over-current;
+ status = "okay";
+ };
+
+@@ -141,30 +198,3 @@
+ vmmc-supply = <&reg_3p3v>;
+ status = "okay";
+ };
+-
+-&audmux {
+- status = "okay";
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_audmux_1>;
+-};
+-
+-&uart2 {
+- status = "okay";
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart2_1>;
+-};
+-
+-&i2c1 {
+- status = "okay";
+- clock-frequency = <100000>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_i2c1_1>;
+-
+- codec: sgtl5000@0a {
+- compatible = "fsl,sgtl5000";
+- reg = <0x0a>;
+- clocks = <&clks 169>;
+- VDDA-supply = <&reg_2p5v>;
+- VDDIO-supply = <&reg_3p3v>;
+- };
+-};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabresd.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabresd.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabresd.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabresd.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -20,20 +20,32 @@
+ compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+ };
+
+-&iomuxc {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hog>;
+-
+- hog {
+- pinctrl_hog: hoggrp {
+- fsl,pins = <
+- MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000
+- MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000
+- MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+- MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+- MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+- MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+- >;
+- };
+- };
++&imx_drm {
++ crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
++};
++
++&sata {
++ status = "okay";
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
++
++&mxcfb3 {
++ status = "okay";
++};
++
++&mxcfb4 {
++ status = "okay";
++};
++
++&battery {
++ offset-charger = <1900>;
++ offset-discharger = <1694>;
++ offset-usb-charger = <1685>;
+ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,23 @@
++/*
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include "imx6q-sabresd.dts"
++
++&hdmi_video {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_hdcp_1>;
++ fsl,hdcp;
++};
++
++&i2c2 {
++ status = "disable";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabresd-ldo.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabresd-ldo.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6q-sabresd-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6q-sabresd-ldo.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,34 @@
++/*
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++
++#include "imx6q-sabresd.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++ pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&gpc {
++ fsl,ldo-bypass = <0>; /* use ldo-bypass, u-boot will check it and configure */
++ fsl,wdog-reset = <1>; /* watchdog select of reset source */
++ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&gpu {
++ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&vpu {
++ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6sl.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/imx6sl.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6sl.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6sl.dtsi 2014-05-15 20:33:34.217842428 +0200
+@@ -0,0 +1,1255 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include "skeleton.dtsi"
++#include "imx6sl-pinfunc.h"
++#include <dt-bindings/clock/imx6sl-clock.h>
++
++/ {
++ aliases {
++ serial0 = &uart1;
++ serial1 = &uart2;
++ serial2 = &uart3;
++ serial3 = &uart4;
++ serial4 = &uart5;
++ gpio0 = &gpio1;
++ gpio1 = &gpio2;
++ gpio2 = &gpio3;
++ gpio3 = &gpio4;
++ gpio4 = &gpio5;
++ usbphy0 = &usbphy1;
++ usbphy1 = &usbphy2;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ compatible = "arm,cortex-a9";
++ device_type = "cpu";
++ reg = <0x0>;
++ next-level-cache = <&L2>;
++ operating-points = <
++ /* kHz uV */
++ 996000 1275000
++ 792000 1175000
++ 396000 975000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 996000 1225000
++ 792000 1175000
++ 396000 1175000
++ >;
++ clock-latency = <61036>; /* two CLK32 periods */
++ clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
++ <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
++ <&clks IMX6SL_CLK_PLL1_SYS>;
++ clock-names = "arm", "pll2_pfd2_396m", "step",
++ "pll1_sw", "pll1_sys";
++ arm-supply = <&reg_arm>;
++ pu-supply = <&reg_pu>;
++ soc-supply = <&reg_soc>;
++ };
++ };
++
++ intc: interrupt-controller@00a01000 {
++ compatible = "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ interrupt-controller;
++ reg = <0x00a01000 0x1000>,
++ <0x00a00100 0x100>;
++ };
++
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ckil {
++ compatible = "fixed-clock";
++ clock-frequency = <32768>;
++ };
++
++ osc {
++ compatible = "fixed-clock";
++ clock-frequency = <24000000>;
++ };
++ };
++
++ pu_dummy: pudummy_reg {
++ compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
++ };
++
++ soc {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ interrupt-parent = <&intc>;
++ ranges;
++
++ busfreq { /* BUSFREQ */
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>,
++ <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>,
++ <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>,
++ <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2>,
++ <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>,
++ <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>,
++ <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM>,
++ <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
++ <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2>,
++ <&clks IMX6SL_CLK_STEP>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
++ "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step";
++ fsl,max_ddr_freq = <400000000>;
++ };
++
++ L2: l2-cache@00a02000 {
++ compatible = "arm,pl310-cache";
++ reg = <0x00a02000 0x1000>;
++ interrupts = <0 92 0x04>;
++ cache-unified;
++ cache-level = <2>;
++ arm,tag-latency = <4 2 3>;
++ arm,data-latency = <4 2 3>;
++ };
++
++ pmu {
++ compatible = "arm,cortex-a9-pmu";
++ interrupts = <0 94 0x04>;
++ };
++
++ aips1: aips-bus@02000000 {
++ compatible = "fsl,aips-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x02000000 0x100000>;
++ ranges;
++
++ spba: spba-bus@02000000 {
++ compatible = "fsl,spba-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x02000000 0x40000>;
++ ranges;
++
++ spdif: spdif@02004000 {
++ compatible = "fsl,imx6sl-spdif",
++ "fsl,imx35-spdif";
++ reg = <0x02004000 0x4000>;
++ interrupts = <0 52 0x04>;
++ dmas = <&sdma 14 18 0>,
++ <&sdma 15 18 0>;
++ dma-names = "rx", "tx";
++ clocks = <&clks IMX6SL_CLK_SPDIF>,
++ <&clks IMX6SL_CLK_OSC>,
++ <&clks IMX6SL_CLK_SPDIF>,
++ <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks IMX6SL_CLK_IPG>,
++ <&clks 0>, <&clks 0>,
++ <&clks IMX6SL_CLK_SPBA>;
++ clock-names = "core", "rxtx0",
++ "rxtx1", "rxtx2",
++ "rxtx3", "rxtx4",
++ "rxtx5", "rxtx6",
++ "rxtx7", "dma";
++ status = "disabled";
++ };
++
++ ecspi1: ecspi@02008000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
++ reg = <0x02008000 0x4000>;
++ interrupts = <0 31 0x04>;
++ clocks = <&clks IMX6SL_CLK_ECSPI1>,
++ <&clks IMX6SL_CLK_ECSPI1>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ ecspi2: ecspi@0200c000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
++ reg = <0x0200c000 0x4000>;
++ interrupts = <0 32 0x04>;
++ clocks = <&clks IMX6SL_CLK_ECSPI2>,
++ <&clks IMX6SL_CLK_ECSPI2>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ ecspi3: ecspi@02010000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
++ reg = <0x02010000 0x4000>;
++ interrupts = <0 33 0x04>;
++ clocks = <&clks IMX6SL_CLK_ECSPI3>,
++ <&clks IMX6SL_CLK_ECSPI3>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ ecspi4: ecspi@02014000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
++ reg = <0x02014000 0x4000>;
++ interrupts = <0 34 0x04>;
++ clocks = <&clks IMX6SL_CLK_ECSPI4>,
++ <&clks IMX6SL_CLK_ECSPI4>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ uart5: serial@02018000 {
++ compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
++ reg = <0x02018000 0x4000>;
++ interrupts = <0 30 0x04>;
++ clocks = <&clks IMX6SL_CLK_UART>,
++ <&clks IMX6SL_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ uart1: serial@02020000 {
++ compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
++ reg = <0x02020000 0x4000>;
++ interrupts = <0 26 0x04>;
++ clocks = <&clks IMX6SL_CLK_UART>,
++ <&clks IMX6SL_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ uart2: serial@02024000 {
++ compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
++ reg = <0x02024000 0x4000>;
++ interrupts = <0 27 0x04>;
++ clocks = <&clks IMX6SL_CLK_UART>,
++ <&clks IMX6SL_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ ssi1: ssi@02028000 {
++ compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
++ reg = <0x02028000 0x4000>;
++ interrupts = <0 46 0x04>;
++ clocks = <&clks IMX6SL_CLK_SSI1>, <&clks IMX6SL_CLK_SSI1>;
++ clock-names = "ipg", "baud";
++ status = "disabled";
++ };
++
++ ssi2: ssi@0202c000 {
++ compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
++ reg = <0x0202c000 0x4000>;
++ interrupts = <0 47 0x04>;
++ clocks = <&clks IMX6SL_CLK_SSI2>, <&clks IMX6SL_CLK_SSI2>;
++ clock-names = "ipg", "baud";
++ status = "disabled";
++ };
++
++ ssi3: ssi@02030000 {
++ compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
++ reg = <0x02030000 0x4000>;
++ interrupts = <0 48 0x04>;
++ clocks = <&clks IMX6SL_CLK_SSI3>, <&clks IMX6SL_CLK_SSI3>;
++ clock-names = "ipg", "baud";
++ status = "disabled";
++ };
++
++ uart3: serial@02034000 {
++ compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
++ reg = <0x02034000 0x4000>;
++ interrupts = <0 28 0x04>;
++ clocks = <&clks IMX6SL_CLK_UART>,
++ <&clks IMX6SL_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ uart4: serial@02038000 {
++ compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
++ reg = <0x02038000 0x4000>;
++ interrupts = <0 29 0x04>;
++ clocks = <&clks IMX6SL_CLK_UART>,
++ <&clks IMX6SL_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++ };
++
++ pwm1: pwm@02080000 {
++ #pwm-cells = <2>;
++ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
++ reg = <0x02080000 0x4000>;
++ interrupts = <0 83 0x04>;
++ clocks = <&clks IMX6SL_CLK_PWM1>,
++ <&clks IMX6SL_CLK_PWM1>;
++ clock-names = "ipg", "per";
++ };
++
++ pwm2: pwm@02084000 {
++ #pwm-cells = <2>;
++ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
++ reg = <0x02084000 0x4000>;
++ interrupts = <0 84 0x04>;
++ clocks = <&clks IMX6SL_CLK_PWM2>,
++ <&clks IMX6SL_CLK_PWM2>;
++ clock-names = "ipg", "per";
++ };
++
++ pwm3: pwm@02088000 {
++ #pwm-cells = <2>;
++ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
++ reg = <0x02088000 0x4000>;
++ interrupts = <0 85 0x04>;
++ clocks = <&clks IMX6SL_CLK_PWM3>,
++ <&clks IMX6SL_CLK_PWM3>;
++ clock-names = "ipg", "per";
++ };
++
++ pwm4: pwm@0208c000 {
++ #pwm-cells = <2>;
++ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
++ reg = <0x0208c000 0x4000>;
++ interrupts = <0 86 0x04>;
++ clocks = <&clks IMX6SL_CLK_PWM4>,
++ <&clks IMX6SL_CLK_PWM4>;
++ clock-names = "ipg", "per";
++ };
++
++ gpt: gpt@02098000 {
++ compatible = "fsl,imx6sl-gpt";
++ reg = <0x02098000 0x4000>;
++ interrupts = <0 55 0x04>;
++ clocks = <&clks IMX6SL_CLK_GPT>,
++ <&clks IMX6SL_CLK_GPT_SERIAL>;
++ clock-names = "ipg", "per";
++ };
++
++ gpio1: gpio@0209c000 {
++ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
++ reg = <0x0209c000 0x4000>;
++ interrupts = <0 66 0x04 0 67 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio2: gpio@020a0000 {
++ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
++ reg = <0x020a0000 0x4000>;
++ interrupts = <0 68 0x04 0 69 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio3: gpio@020a4000 {
++ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
++ reg = <0x020a4000 0x4000>;
++ interrupts = <0 70 0x04 0 71 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio4: gpio@020a8000 {
++ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
++ reg = <0x020a8000 0x4000>;
++ interrupts = <0 72 0x04 0 73 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio5: gpio@020ac000 {
++ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
++ reg = <0x020ac000 0x4000>;
++ interrupts = <0 74 0x04 0 75 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ kpp: kpp@020b8000 {
++ compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
++ reg = <0x020b8000 0x4000>;
++ interrupts = <0 82 0x04>;
++ clocks = <&clks IMX6SL_CLK_DUMMY>;
++ };
++
++ wdog1: wdog@020bc000 {
++ compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
++ reg = <0x020bc000 0x4000>;
++ interrupts = <0 80 0x04>;
++ clocks = <&clks IMX6SL_CLK_DUMMY>;
++ };
++
++ wdog2: wdog@020c0000 {
++ compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
++ reg = <0x020c0000 0x4000>;
++ interrupts = <0 81 0x04>;
++ clocks = <&clks IMX6SL_CLK_DUMMY>;
++ status = "disabled";
++ };
++
++ clks: ccm@020c4000 {
++ compatible = "fsl,imx6sl-ccm";
++ reg = <0x020c4000 0x4000>;
++ interrupts = <0 87 0x04 0 88 0x04>;
++ #clock-cells = <1>;
++ };
++
++ anatop: anatop@020c8000 {
++ compatible = "fsl,imx6sl-anatop",
++ "fsl,imx6q-anatop",
++ "syscon", "simple-bus";
++ reg = <0x020c8000 0x1000>;
++ interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
++
++ regulator-1p1@110 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vdd1p1";
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1375000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x110>;
++ anatop-vol-bit-shift = <8>;
++ anatop-vol-bit-width = <5>;
++ anatop-min-bit-val = <4>;
++ anatop-min-voltage = <800000>;
++ anatop-max-voltage = <1375000>;
++ };
++
++ regulator-3p0@120 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vdd3p0";
++ regulator-min-microvolt = <2800000>;
++ regulator-max-microvolt = <3150000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x120>;
++ anatop-vol-bit-shift = <8>;
++ anatop-vol-bit-width = <5>;
++ anatop-min-bit-val = <0>;
++ anatop-min-voltage = <2625000>;
++ anatop-max-voltage = <3400000>;
++ };
++
++ regulator-2p5@130 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vdd2p5";
++ regulator-min-microvolt = <2100000>;
++ regulator-max-microvolt = <2850000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x130>;
++ anatop-vol-bit-shift = <8>;
++ anatop-vol-bit-width = <5>;
++ anatop-min-bit-val = <0>;
++ anatop-min-voltage = <2100000>;
++ anatop-max-voltage = <2850000>;
++ };
++
++ reg_arm: regulator-vddcore@140 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "cpu";
++ regulator-min-microvolt = <725000>;
++ regulator-max-microvolt = <1450000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x140>;
++ anatop-vol-bit-shift = <0>;
++ anatop-vol-bit-width = <5>;
++ anatop-delay-reg-offset = <0x170>;
++ anatop-delay-bit-shift = <24>;
++ anatop-delay-bit-width = <2>;
++ anatop-min-bit-val = <1>;
++ anatop-min-voltage = <725000>;
++ anatop-max-voltage = <1450000>;
++ };
++
++ reg_pu: regulator-vddpu@140 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vddpu";
++ regulator-min-microvolt = <725000>;
++ regulator-max-microvolt = <1450000>;
++ anatop-reg-offset = <0x140>;
++ anatop-vol-bit-shift = <9>;
++ anatop-vol-bit-width = <5>;
++ anatop-delay-reg-offset = <0x170>;
++ anatop-delay-bit-shift = <26>;
++ anatop-delay-bit-width = <2>;
++ anatop-min-bit-val = <1>;
++ anatop-min-voltage = <725000>;
++ anatop-max-voltage = <1450000>;
++ };
++
++ reg_soc: regulator-vddsoc@140 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vddsoc";
++ regulator-min-microvolt = <725000>;
++ regulator-max-microvolt = <1450000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x140>;
++ anatop-vol-bit-shift = <18>;
++ anatop-vol-bit-width = <5>;
++ anatop-delay-reg-offset = <0x170>;
++ anatop-delay-bit-shift = <28>;
++ anatop-delay-bit-width = <2>;
++ anatop-min-bit-val = <1>;
++ anatop-min-voltage = <725000>;
++ anatop-max-voltage = <1450000>;
++ };
++ };
++
++ tempmon: tempmon {
++ compatible = "fsl,imx6sl-tempmon", "fsl,imx6q-tempmon";
++ interrupts = <0 49 0x04>;
++ fsl,tempmon = <&anatop>;
++ fsl,tempmon-data = <&ocotp>;
++ clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
++ };
++
++ usbphy1: usbphy@020c9000 {
++ compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
++ reg = <0x020c9000 0x1000>;
++ interrupts = <0 44 0x04>;
++ clocks = <&clks IMX6SL_CLK_USBPHY1>;
++ fsl,anatop = <&anatop>;
++ };
++
++ usbphy2: usbphy@020ca000 {
++ compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
++ reg = <0x020ca000 0x1000>;
++ interrupts = <0 45 0x04>;
++ clocks = <&clks IMX6SL_CLK_USBPHY2>;
++ fsl,anatop = <&anatop>;
++ };
++
++ snvs@020cc000 {
++ compatible = "fsl,sec-v4.0-mon", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x020cc000 0x4000>;
++
++ snvs-rtc-lp@34 {
++ compatible = "fsl,sec-v4.0-mon-rtc-lp";
++ reg = <0x34 0x58>;
++ interrupts = <0 19 0x04 0 20 0x04>;
++ };
++ };
++
++ epit1: epit@020d0000 {
++ reg = <0x020d0000 0x4000>;
++ interrupts = <0 56 0x04>;
++ };
++
++ epit2: epit@020d4000 {
++ reg = <0x020d4000 0x4000>;
++ interrupts = <0 57 0x04>;
++ };
++
++ src: src@020d8000 {
++ compatible = "fsl,imx6sl-src", "fsl,imx51-src";
++ reg = <0x020d8000 0x4000>;
++ interrupts = <0 91 0x04 0 96 0x04>;
++ #reset-cells = <1>;
++ };
++
++ ocram: sram@00900000 {
++ compatible = "mmio-sram";
++ reg = <0x00900000 0x20000>;
++ clocks = <&clks IMX6SL_CLK_OCRAM>;
++ };
++
++ gpc: gpc@020dc000 {
++ compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
++ reg = <0x020dc000 0x4000>;
++ interrupts = <0 89 0x04>;
++ clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>,
++ <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>,
++ <&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>,
++ <&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>;
++ clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi",
++ "lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi";
++ pu-supply = <&reg_pu>;
++ };
++
++ gpr: iomuxc-gpr@020e0000 {
++ compatible = "fsl,imx6sl-iomuxc-gpr", "syscon";
++ reg = <0x020e0000 0x38>;
++ };
++
++ iomuxc: iomuxc@020e0000 {
++ compatible = "fsl,imx6sl-iomuxc";
++ reg = <0x020e0000 0x4000>;
++
++ audmux {
++ pinctrl_audmux_1: audmux-1 {
++ fsl,pins = <
++ MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130B0
++ MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130B0
++ MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110B0
++ MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130B0
++ MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130B0
++ >;
++ };
++ };
++
++ csi {
++ pinctrl_csi_0: csigrp-0 {
++ fsl,pins = <
++ MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0
++ MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
++ MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0
++ MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0
++ MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
++ MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
++ MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0
++ MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0
++ MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0
++ MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0
++ MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0
++ MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0
++ MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0
++ MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0
++ MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
++ MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
++ >;
++ };
++ };
++
++ ecspi1 {
++ pinctrl_ecspi1_1: ecspi1grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
++ MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
++ MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
++ >;
++ };
++ };
++
++ epdc {
++ pinctrl_epdc_0: epdcgrp-0 {
++ fsl,pins = <
++ MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000
++ MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000
++ MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000
++ MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000
++ MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000
++ MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000
++ MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000
++ MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000
++ MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000
++ MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000
++ MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
++ MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
++ MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
++ MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
++ MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
++ MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
++ MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
++ MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000
++ MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000
++ MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000
++ MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
++ MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000
++ MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000
++ MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
++ MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000
++ MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
++ MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
++ MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
++ >;
++ };
++ };
++
++ fec {
++ pinctrl_fec_1: fecgrp-1 {
++ fsl,pins = <
++ MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
++ MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
++ MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
++ MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
++ MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
++ MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
++ MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
++ MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
++ MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
++ >;
++ };
++ };
++
++ spdif {
++ pinctrl_spdif_1: spdifgrp-1 {
++ fsl,pins = <
++ MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000
++ >;
++ };
++ };
++
++ uart1 {
++ pinctrl_uart1_1: uart1grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
++ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
++ >;
++ };
++ };
++
++ usbotg1 {
++ pinctrl_usbotg1_1: usbotg1grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg1_2: usbotg1grp-2 {
++ fsl,pins = <
++ MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg1_3: usbotg1grp-3 {
++ fsl,pins = <
++ MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg1_4: usbotg1grp-4 {
++ fsl,pins = <
++ MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg1_5: usbotg1grp-5 {
++ fsl,pins = <
++ MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
++ >;
++ };
++ };
++
++ usbotg2 {
++ pinctrl_usbotg2_1: usbotg2grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
++ >;
++ };
++
++ pinctrl_usbotg2_2: usbotg2grp-2 {
++ fsl,pins = <
++ MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
++ >;
++ };
++
++ pinctrl_usbotg2_3: usbotg2grp-3 {
++ fsl,pins = <
++ MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
++ >;
++ };
++
++ pinctrl_usbotg2_4: usbotg2grp-4 {
++ fsl,pins = <
++ MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
++ >;
++ };
++ };
++
++ usdhc1 {
++ pinctrl_usdhc1_1: usdhc1grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
++ MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
++ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
++ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
++ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
++ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
++ >;
++ };
++ };
++
++ usdhc2 {
++ pinctrl_usdhc2_1: usdhc2grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
++ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
++ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
++ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
++ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
++ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
++ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
++ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
++ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
++ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
++ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
++ >;
++ };
++ };
++
++ usdhc3 {
++ pinctrl_usdhc3_1: usdhc3grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
++ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
++ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
++ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
++ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
++ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
++ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
++ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
++ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
++ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
++ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
++ >;
++ };
++ };
++
++ i2c1 {
++ pinctrl_i2c1_1: i2c1grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
++ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c2 {
++ pinctrl_i2c2_1: i2c2grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
++ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c3 {
++ pinctrl_i2c3_1: i2c3grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
++ MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
++ >;
++ };
++ };
++
++ kpp {
++ pinctrl_kpp_1: kpp_grp_1 {
++ fsl,pins = <
++ MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
++ MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
++ MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
++ MX6SL_PAD_KEY_COL0__KEY_COL0 0x1b0b0
++ MX6SL_PAD_KEY_COL1__KEY_COL1 0x1b0b0
++ MX6SL_PAD_KEY_COL2__KEY_COL2 0x1b0b0
++ >;
++ };
++
++ pinctrl_kpp_1_sleep: kpp_grp_1_sleep {
++ fsl,pins = <
++ MX6SL_PAD_KEY_ROW0__GPIO3_IO25 0x3080
++ MX6SL_PAD_KEY_ROW1__GPIO3_IO27 0x3080
++ MX6SL_PAD_KEY_ROW2__GPIO3_IO29 0x3080
++ MX6SL_PAD_KEY_COL0__GPIO3_IO24 0x3080
++ MX6SL_PAD_KEY_COL1__GPIO3_IO26 0x3080
++ MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x3080
++ >;
++ };
++ };
++
++ lcdif {
++ pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
++ fsl,pins = <
++ MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
++ MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
++ MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
++ MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
++ MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
++ MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
++ MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
++ MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
++ MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
++ MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
++ MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
++ MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
++ MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
++ MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
++ MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
++ MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
++ MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
++ MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
++ MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
++ MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
++ MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
++ MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
++ MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
++ MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
++ >;
++ };
++
++ pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
++ fsl,pins = <
++ MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
++ MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
++ MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
++ MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
++ >;
++ };
++ };
++
++ pwm1 {
++ pinctrl_pwm1_0: pwm1grp-0 {
++ fsl,pins = <
++ MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
++ >;
++ };
++ };
++ };
++
++ csi: csi@020e4000 {
++ compatible = "fsl,imx6sl-csi";
++ reg = <0x020e4000 0x4000>;
++ interrupts = <0 7 0x04>;
++ status = "disabled";
++ };
++
++ spdc: spdc@020e8000 {
++ reg = <0x020e8000 0x4000>;
++ interrupts = <0 6 0x04>;
++ };
++
++ sdma: sdma@020ec000 {
++ compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
++ reg = <0x020ec000 0x4000>;
++ interrupts = <0 2 0x04>;
++ clocks = <&clks IMX6SL_CLK_SDMA>,
++ <&clks IMX6SL_CLK_SDMA>;
++ clock-names = "ipg", "ahb";
++ iram = <&ocram>;
++ /* imx6sl reuses imx6q sdma firmware */
++ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
++ };
++
++ pxp: pxp@020f0000 {
++ compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
++ reg = <0x020f0000 0x4000>;
++ interrupts = <0 98 0x04>;
++ clocks = <&clks 111>;
++ clock-names = "pxp-axi";
++ status = "disabled";
++ };
++
++ epdc: epdc@020f4000 {
++ compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
++ reg = <0x020f4000 0x4000>;
++ interrupts = <0 97 0x04>;
++ clocks = <&clks IMX6SL_CLK_EPDC_AXI>,
++ <&clks IMX6SL_CLK_EPDC_PIX>;
++ clock-names = "epdc_axi", "epdc_pix";
++ };
++
++ lcdif: lcdif@020f8000 {
++ compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
++ reg = <0x020f8000 0x4000>;
++ interrupts = <0 39 0x04>;
++ clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
++ <&clks IMX6SL_CLK_LCDIF_AXI>;
++ clock-names = "pix", "axi";
++ status = "disabled";
++ };
++
++ dcp: dcp@020fc000 {
++ reg = <0x020fc000 0x4000>;
++ interrupts = <0 99 0x04>;
++ };
++ };
++
++ aips2: aips-bus@02100000 {
++ compatible = "fsl,aips-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x02100000 0x100000>;
++ ranges;
++
++ usbotg1: usb@02184000 {
++ compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
++ reg = <0x02184000 0x200>;
++ interrupts = <0 43 0x04>;
++ clocks = <&clks IMX6SL_CLK_USBOH3>;
++ fsl,usbphy = <&usbphy1>;
++ fsl,usbmisc = <&usbmisc 0>;
++ fsl,anatop = <&anatop>;
++ status = "disabled";
++ };
++
++ usbotg2: usb@02184200 {
++ compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
++ reg = <0x02184200 0x200>;
++ interrupts = <0 42 0x04>;
++ clocks = <&clks IMX6SL_CLK_USBOH3>;
++ fsl,usbphy = <&usbphy2>;
++ fsl,usbmisc = <&usbmisc 1>;
++ status = "disabled";
++ };
++
++ usbh: usb@02184400 {
++ compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
++ reg = <0x02184400 0x200>;
++ interrupts = <0 40 0x04>;
++ clocks = <&clks IMX6SL_CLK_USBOH3>;
++ fsl,usbmisc = <&usbmisc 2>;
++ status = "disabled";
++ };
++
++ usbmisc: usbmisc@02184800 {
++ #index-cells = <1>;
++ compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
++ reg = <0x02184800 0x200>;
++ clocks = <&clks IMX6SL_CLK_USBOH3>;
++ };
++
++ fec: ethernet@02188000 {
++ compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
++ reg = <0x02188000 0x4000>;
++ interrupts = <0 114 0x04>;
++ clocks = <&clks IMX6SL_CLK_ENET>,
++ <&clks IMX6SL_CLK_ENET_REF>;
++ clock-names = "ipg", "ahb";
++ status = "disabled";
++ };
++
++ usdhc1: usdhc@02190000 {
++ compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
++ reg = <0x02190000 0x4000>;
++ interrupts = <0 22 0x04>;
++ clocks = <&clks IMX6SL_CLK_USDHC1>,
++ <&clks IMX6SL_CLK_USDHC1>,
++ <&clks IMX6SL_CLK_USDHC1>;
++ clock-names = "ipg", "ahb", "per";
++ bus-width = <4>;
++ status = "disabled";
++ };
++
++ usdhc2: usdhc@02194000 {
++ compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
++ reg = <0x02194000 0x4000>;
++ interrupts = <0 23 0x04>;
++ clocks = <&clks IMX6SL_CLK_USDHC2>,
++ <&clks IMX6SL_CLK_USDHC2>,
++ <&clks IMX6SL_CLK_USDHC2>;
++ clock-names = "ipg", "ahb", "per";
++ bus-width = <4>;
++ status = "disabled";
++ };
++
++ usdhc3: usdhc@02198000 {
++ compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
++ reg = <0x02198000 0x4000>;
++ interrupts = <0 24 0x04>;
++ clocks = <&clks IMX6SL_CLK_USDHC3>,
++ <&clks IMX6SL_CLK_USDHC3>,
++ <&clks IMX6SL_CLK_USDHC3>;
++ clock-names = "ipg", "ahb", "per";
++ bus-width = <4>;
++ status = "disabled";
++ };
++
++ usdhc4: usdhc@0219c000 {
++ compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
++ reg = <0x0219c000 0x4000>;
++ interrupts = <0 25 0x04>;
++ clocks = <&clks IMX6SL_CLK_USDHC4>,
++ <&clks IMX6SL_CLK_USDHC4>,
++ <&clks IMX6SL_CLK_USDHC4>;
++ clock-names = "ipg", "ahb", "per";
++ bus-width = <4>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@021a0000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
++ reg = <0x021a0000 0x4000>;
++ interrupts = <0 36 0x04>;
++ clocks = <&clks IMX6SL_CLK_I2C1>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@021a4000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
++ reg = <0x021a4000 0x4000>;
++ interrupts = <0 37 0x04>;
++ clocks = <&clks IMX6SL_CLK_I2C2>;
++ status = "disabled";
++ };
++
++ i2c3: i2c@021a8000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
++ reg = <0x021a8000 0x4000>;
++ interrupts = <0 38 0x04>;
++ clocks = <&clks IMX6SL_CLK_I2C3>;
++ status = "disabled";
++ };
++
++ mmdc: mmdc@021b0000 {
++ compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
++ reg = <0x021b0000 0x4000>;
++ };
++
++ rngb: rngb@021b4000 {
++ reg = <0x021b4000 0x4000>;
++ interrupts = <0 5 0x04>;
++ };
++
++ weim: weim@021b8000 {
++ reg = <0x021b8000 0x4000>;
++ interrupts = <0 14 0x04>;
++ };
++
++ ocotp: ocotp-ctrl@021bc000 {
++ compatible = "syscon";
++ reg = <0x021bc000 0x4000>;
++ };
++
++ ocotp-fuse@021bc000 {
++ compatible = "fsl,imx6sl-ocotp", "fsl,imx6q-ocotp";
++ reg = <0x021bc000 0x4000>;
++ clocks = <&clks IMX6SL_CLK_OCOTP>;
++ };
++
++ audmux: audmux@021d8000 {
++ compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
++ reg = <0x021d8000 0x4000>;
++ status = "disabled";
++ };
++
++ gpu: gpu@02200000 {
++ compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
++ reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
++ <0x80000000 0x0>;
++ reg-names = "iobase_2d", "iobase_vg",
++ "phys_baseaddr";
++ interrupts = <0 10 0x04>, <0 11 0x04>;
++ interrupt-names = "irq_2d", "irq_vg";
++ clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
++ <&clks IMX6SL_CLK_MMDC_ROOT>,
++ <&clks IMX6SL_CLK_GPU2D_OVG>;
++ clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
++ "gpu2d_clk";
++ resets = <&src 3>, <&src 3>;
++ reset-names = "gpu2d", "gpuvg";
++ pu-supply = <&reg_pu>;
++ };
++
++ };
++
++ pinctrl_fec_1_sleep: fecgrp-1-sleep {
++ fsl,pins = <
++ MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
++ MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
++ MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
++ MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
++ MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
++ MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
++ MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
++ MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
++ >;
++ };
++
++ pinctrl_pwm1_0_sleep: pwm1grp-0-sleep {
++ fsl,pins = <
++ MX6SL_PAD_PWM1__GPIO3_IO23 0x3080
++ >;
++ };
++
++ pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
++ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
++ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
++ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
++ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
++ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
++ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
++ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
++ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
++ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
++ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
++ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
++ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
++ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
++ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
++ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
++ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
++ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
++ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
++ >;
++ };
++
++ };
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6sl-evk-csi.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6sl-evk-csi.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6sl-evk-csi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6sl-evk-csi.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sl-evk.dts"
++
++/ {
++ csi_v4l2_cap {
++ status = "okay";
++ };
++};
++
++&csi {
++ status = "okay";
++};
++
++&i2c3 {
++ status = "okay";
++};
++
++&epdc {
++ status = "disabled";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6sl-evk.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6sl-evk.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6sl-evk.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6sl-evk.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,604 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/dts-v1/;
++
++#include "imx6sl.dtsi"
++
++/ {
++ model = "Freescale i.MX6 SoloLite EVK Board";
++ compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
++
++ memory {
++ reg = <0x80000000 0x40000000>;
++ };
++
++ battery: max8903@0 {
++ compatible = "fsl,max8903-charger";
++ pinctrl-names = "default";
++ dok_input = <&gpio4 13 1>;
++ uok_input = <&gpio4 13 1>;
++ chg_input = <&gpio4 15 1>;
++ flt_input = <&gpio4 14 1>;
++ fsl,dcm_always_high;
++ fsl,dc_valid;
++ fsl,adc_disable;
++ status = "okay";
++ };
++ regulators {
++ compatible = "simple-bus";
++
++ reg_lcd_3v3: lcd-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "lcd-3v3";
++ gpio = <&gpio4 3 0>;
++ enable-active-high;
++ };
++
++ reg_aud3v: wm8962_supply_3v15 {
++ compatible = "regulator-fixed";
++ regulator-name = "wm8962-supply-3v15";
++ regulator-min-microvolt = <3150000>;
++ regulator-max-microvolt = <3150000>;
++ regulator-boot-on;
++ };
++
++ reg_aud4v: wm8962_supply_4v2 {
++ compatible = "regulator-fixed";
++ regulator-name = "wm8962-supply-4v2";
++ regulator-min-microvolt = <4325000>;
++ regulator-max-microvolt = <4325000>;
++ regulator-boot-on;
++ };
++
++ reg_usb_otg1_vbus: usb_otg1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio4 0 0>;
++ enable-active-high;
++ };
++
++ reg_usb_otg2_vbus: usb_otg2_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg2_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio4 2 0>;
++ enable-active-high;
++ };
++ };
++
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm1 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ };
++
++ csi_v4l2_cap {
++ compatible = "fsl,imx6sl-csi-v4l2";
++ status = "disabled";
++ };
++
++ pxp_v4l2_out {
++ compatible = "fsl,imx6sl-pxp-v4l2";
++ status = "okay";
++ };
++
++ sound {
++ compatible = "fsl,imx6q-sabresd-wm8962",
++ "fsl,imx-audio-wm8962";
++ model = "wm8962-audio";
++ ssi-controller = <&ssi2>;
++ audio-codec = <&codec>;
++ audio-routing =
++ "Headphone Jack", "HPOUTL",
++ "Headphone Jack", "HPOUTR",
++ "Ext Spk", "SPKOUTL",
++ "Ext Spk", "SPKOUTR",
++ "AMIC", "MICBIAS",
++ "IN3R", "AMIC";
++ amic-mono;
++ mux-int-port = <2>;
++ mux-ext-port = <3>;
++ hp-det-gpios = <&gpio4 19 1>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif",
++ "fsl,imx6sl-evk-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ };
++
++ sii902x_reset: sii902x-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio2 19 1>;
++ reset-delay-us = <100000>;
++ #reset-cells = <0>;
++ };
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux_1>;
++ status = "okay";
++};
++
++&csi {
++ status = "disabled";
++};
++
++&ecspi1 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio4 11 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi1_1>;
++ status = "okay";
++
++ flash: m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25p32";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++};
++
++&epdc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_epdc_0>;
++ V3P3-supply = <&V3P3_reg>;
++ VCOM-supply = <&VCOM_reg>;
++ DISPLAY-supply = <&DISPLAY_reg>;
++ status = "okay";
++};
++
++&cpu0 {
++ arm-supply = <&sw1a_reg>;
++ soc-supply = <&sw1c_reg>;
++ pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&fec {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&pinctrl_fec_1>;
++ pinctrl-1 = <&pinctrl_fec_1_sleep>;
++ phy-mode = "rmii";
++ phy-reset-gpios = <&gpio4 21 0>; /* GPIO4_21 */
++ phy-reset-duration = <1>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1_1>;
++ status = "okay";
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++
++ elan@10 {
++ compatible = "elan,elan-touch";
++ reg = <0x10>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <10 2>;
++ gpio_elan_cs = <&gpio2 9 0>;
++ gpio_elan_rst = <&gpio4 4 0>;
++ gpio_intr = <&gpio2 10 0>;
++ status = "okay";
++ };
++
++ max17135@48 {
++ compatible = "maxim,max17135";
++ reg = <0x48>;
++ vneg_pwrup = <1>;
++ gvee_pwrup = <2>;
++ vpos_pwrup = <10>;
++ gvdd_pwrup = <12>;
++ gvdd_pwrdn = <1>;
++ vpos_pwrdn = <2>;
++ gvee_pwrdn = <8>;
++ vneg_pwrdn = <10>;
++ gpio_pmic_pwrgood = <&gpio2 13 0>;
++ gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
++ gpio_pmic_wakeup = <&gpio2 14 0>;
++ gpio_pmic_v3p3 = <&gpio2 7 0>;
++ gpio_pmic_intr = <&gpio2 12 0>;
++
++ regulators {
++ DISPLAY_reg: DISPLAY {
++ regulator-name = "DISPLAY";
++ };
++
++ GVDD_reg: GVDD {
++ /* 20v */
++ regulator-name = "GVDD";
++ };
++
++ GVEE_reg: GVEE {
++ /* -22v */
++ regulator-name = "GVEE";
++ };
++
++ HVINN_reg: HVINN {
++ /* -22v */
++ regulator-name = "HVINN";
++ };
++
++ HVINP_reg: HVINP {
++ /* 20v */
++ regulator-name = "HVINP";
++ };
++
++ VCOM_reg: VCOM {
++ regulator-name = "VCOM";
++ /* 2's-compliment, -4325000 */
++ regulator-min-microvolt = <0xffbe0178>;
++ /* 2's-compliment, -500000 */
++ regulator-max-microvolt = <0xfff85ee0>;
++ };
++
++ VNEG_reg: VNEG {
++ /* -15v */
++ regulator-name = "VNEG";
++ };
++
++ VPOS_reg: VPOS {
++ /* 15v */
++ regulator-name = "VPOS";
++ };
++
++ V3P3_reg: V3P3 {
++ regulator-name = "V3P3";
++ };
++ };
++ };
++
++ mma8450@1c {
++ compatible = "fsl,mma8450";
++ reg = <0x1c>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2_1>;
++ status = "okay";
++
++ codec: wm8962@1a {
++ compatible = "wlf,wm8962";
++ reg = <0x1a>;
++ clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
++ DCVDD-supply = <&vgen3_reg>;
++ DBVDD-supply = <&reg_aud3v>;
++ AVDD-supply = <&vgen3_reg>;
++ CPVDD-supply = <&vgen3_reg>;
++ MICVDD-supply = <&reg_aud3v>;
++ PLLVDD-supply = <&vgen3_reg>;
++ SPKVDD1-supply = <&reg_aud4v>;
++ SPKVDD2-supply = <&reg_aud4v>;
++ amic-mono;
++ };
++
++ sii902x@39 {
++ compatible = "SiI,sii902x";
++ interrupt-parent = <&gpio2>;
++ interrupts = <10 2>;
++ mode_str ="1280x720M@60";
++ bits-per-pixel = <32>;
++ resets = <&sii902x_reset>;
++ reg = <0x39>;
++ };
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3_1>;
++ status = "disabled";
++
++ ov564x: ov564x@3c {
++ compatible = "ovti,ov564x";
++ reg = <0x3c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_csi_0>;
++ clocks = <&clks IMX6SL_CLK_CSI>;
++ clock-names = "csi_mclk";
++ AVDD-supply = <&vgen6_reg>; /* 2.8v */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio1 25 1>;
++ rst-gpios = <&gpio1 26 0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&pinctrl_hog>;
++ pinctrl-1 = <&pinctrl_hog_sleep>;
++
++ hog {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
++ MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
++ MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
++ MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
++ MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
++ MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x80000000
++ MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x110b0
++ MX6SL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000
++ MX6SL_PAD_EPDC_PWRSTAT__GPIO2_IO13 0x80000000
++ MX6SL_PAD_EPDC_PWRCTRL0__GPIO2_IO07 0x80000000
++ MX6SL_PAD_EPDC_PWRWAKEUP__GPIO2_IO14 0x80000000
++ MX6SL_PAD_EPDC_PWRINT__GPIO2_IO12 0x80000000
++ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x170b0
++ MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
++ MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0
++ MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
++ MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
++ MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
++ MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
++ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0
++ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
++ MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
++ >;
++ };
++
++ pinctrl_hog_sleep: hoggrp_sleep {
++ fsl,pins = <
++ MX6SL_PAD_KEY_ROW5__GPIO4_IO03 0x3080
++ MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x3080
++ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x3080
++ >;
++ };
++ };
++};
++
++&kpp {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&pinctrl_kpp_1>;
++ pinctrl-1 = <&pinctrl_kpp_1_sleep>;
++ linux,keymap = <
++ 0x00000067 /* KEY_UP */
++ 0x0001006c /* KEY_DOWN */
++ 0x0002001c /* KEY_ENTER */
++ 0x01000066 /* KEY_HOME */
++ 0x0101006a /* KEY_RIGHT */
++ 0x01020069 /* KEY_LEFT */
++ 0x02000072 /* KEY_VOLUMEDOWN */
++ 0x02010073 /* KEY_VOLUMEUP */
++ >;
++ status = "okay";
++};
++
++&lcdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_lcdif_dat_0
++ &pinctrl_lcdif_ctrl_0>;
++ lcd-supply = <&reg_lcd_3v3>;
++ display = <&display>;
++ status = "okay";
++
++ display: display {
++ bits-per-pixel = <16>;
++ bus-width = <24>;
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: timing0 {
++ clock-frequency = <33500000>;
++ hactive = <800>;
++ vactive = <480>;
++ hback-porch = <89>;
++ hfront-porch = <164>;
++ vback-porch = <23>;
++ vfront-porch = <10>;
++ hsync-len = <10>;
++ vsync-len = <10>;
++ hsync-active = <0>;
++ vsync-active = <0>;
++ de-active = <1>;
++ pixelclk-active = <0>;
++ };
++ };
++ };
++};
++
++&pwm1 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&pinctrl_pwm1_0>;
++ pinctrl-1 = <&pinctrl_pwm1_0_sleep>;
++ status = "okay";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif_1>;
++ status = "okay";
++};
++
++&ssi2 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1_1>;
++ status = "okay";
++};
++
++&usbotg1 {
++ vbus-supply = <&reg_usb_otg1_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg1_1>;
++ disable-over-current;
++ imx6-usb-charger-detection;
++ status = "okay";
++};
++
++&usbotg2 {
++ vbus-supply = <&reg_usb_otg2_vbus>;
++ dr_mode = "host";
++ disable-over-current;
++ status = "okay";
++};
++
++&usdhc1 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc1_1>;
++ pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
++ bus-width = <8>;
++ cd-gpios = <&gpio4 7 0>;
++ wp-gpios = <&gpio4 6 0>;
++ status = "okay";
++};
++
++&usdhc2 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc2_1>;
++ pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
++ cd-gpios = <&gpio5 0 0>;
++ wp-gpios = <&gpio4 29 0>;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3_1>;
++ pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
++ cd-gpios = <&gpio3 22 0>;
++ status = "okay";
++};
++
++&pxp {
++ status = "okay";
++};
++
++&gpc {
++ fsl,cpu_pupscr_sw2iso = <0xf>;
++ fsl,cpu_pupscr_sw = <0xf>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++ fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
++ fsl,wdog-reset = <1>; /* watchdog select of reset source */
++ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&gpu {
++ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/imx6sl-evk-ldo.dts linux-linaro-stable-mx6/arch/arm/boot/dts/imx6sl-evk-ldo.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/imx6sl-evk-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/imx6sl-evk-ldo.dts 2014-05-15 20:33:34.213842400 +0200
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sl-evk.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++ pu-supply = <&reg_pu>; /* use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&gpc {
++ fsl,ldo-bypass = <0>; /* use ldo-bypass, u-boot will check it and configure */
++ fsl,wdog-reset = <1>; /* watchdog select of reset source */
++ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
++
++&gpu {
++ pu-supply = <&reg_pu>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/include/dt-bindings/clock/imx6sl-clock.h linux-linaro-stable-mx6/arch/arm/boot/dts/include/dt-bindings/clock/imx6sl-clock.h
+--- linux-3.10.30.orig/arch/arm/boot/dts/include/dt-bindings/clock/imx6sl-clock.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/include/dt-bindings/clock/imx6sl-clock.h 2014-05-15 20:34:14.046129478 +0200
+@@ -0,0 +1,152 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
++#define __DT_BINDINGS_CLOCK_IMX6SL_H
++
++#define IMX6SL_CLK_DUMMY 0
++#define IMX6SL_CLK_CKIL 1
++#define IMX6SL_CLK_OSC 2
++#define IMX6SL_CLK_PLL1_SYS 3
++#define IMX6SL_CLK_PLL2_BUS 4
++#define IMX6SL_CLK_PLL3_USB_OTG 5
++#define IMX6SL_CLK_PLL4_AUDIO 6
++#define IMX6SL_CLK_PLL5_VIDEO 7
++#define IMX6SL_CLK_PLL6_ENET 8
++#define IMX6SL_CLK_PLL7_USB_HOST 9
++#define IMX6SL_CLK_USBPHY1 10
++#define IMX6SL_CLK_USBPHY2 11
++#define IMX6SL_CLK_USBPHY1_GATE 12
++#define IMX6SL_CLK_USBPHY2_GATE 13
++#define IMX6SL_CLK_PLL4_POST_DIV 14
++#define IMX6SL_CLK_PLL5_POST_DIV 15
++#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
++#define IMX6SL_CLK_ENET_REF 17
++#define IMX6SL_CLK_PLL2_PFD0 18
++#define IMX6SL_CLK_PLL2_PFD1 19
++#define IMX6SL_CLK_PLL2_PFD2 20
++#define IMX6SL_CLK_PLL3_PFD0 21
++#define IMX6SL_CLK_PLL3_PFD1 22
++#define IMX6SL_CLK_PLL3_PFD2 23
++#define IMX6SL_CLK_PLL3_PFD3 24
++#define IMX6SL_CLK_PLL2_198M 25
++#define IMX6SL_CLK_PLL3_120M 26
++#define IMX6SL_CLK_PLL3_80M 27
++#define IMX6SL_CLK_PLL3_60M 28
++#define IMX6SL_CLK_STEP 29
++#define IMX6SL_CLK_PLL1_SW 30
++#define IMX6SL_CLK_OCRAM_ALT_SEL 31
++#define IMX6SL_CLK_OCRAM_SEL 32
++#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
++#define IMX6SL_CLK_PRE_PERIPH_SEL 34
++#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
++#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
++#define IMX6SL_CLK_CSI_SEL 37
++#define IMX6SL_CLK_LCDIF_AXI_SEL 38
++#define IMX6SL_CLK_USDHC1_SEL 39
++#define IMX6SL_CLK_USDHC2_SEL 40
++#define IMX6SL_CLK_USDHC3_SEL 41
++#define IMX6SL_CLK_USDHC4_SEL 42
++#define IMX6SL_CLK_SSI1_SEL 43
++#define IMX6SL_CLK_SSI2_SEL 44
++#define IMX6SL_CLK_SSI3_SEL 45
++#define IMX6SL_CLK_PERCLK_SEL 46
++#define IMX6SL_CLK_PXP_AXI_SEL 47
++#define IMX6SL_CLK_EPDC_AXI_SEL 48
++#define IMX6SL_CLK_GPU2D_OVG_SEL 49
++#define IMX6SL_CLK_GPU2D_SEL 50
++#define IMX6SL_CLK_LCDIF_PIX_SEL 51
++#define IMX6SL_CLK_EPDC_PIX_SEL 52
++#define IMX6SL_CLK_SPDIF0_SEL 53
++#define IMX6SL_CLK_SPDIF1_SEL 54
++#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
++#define IMX6SL_CLK_ECSPI_SEL 56
++#define IMX6SL_CLK_UART_SEL 57
++#define IMX6SL_CLK_PERIPH 58
++#define IMX6SL_CLK_PERIPH2 59
++#define IMX6SL_CLK_OCRAM_PODF 60
++#define IMX6SL_CLK_PERIPH_CLK2 61
++#define IMX6SL_CLK_PERIPH2_CLK2 62
++#define IMX6SL_CLK_IPG 63
++#define IMX6SL_CLK_CSI_PODF 64
++#define IMX6SL_CLK_LCDIF_AXI_PODF 65
++#define IMX6SL_CLK_USDHC1_PODF 66
++#define IMX6SL_CLK_USDHC2_PODF 67
++#define IMX6SL_CLK_USDHC3_PODF 68
++#define IMX6SL_CLK_USDHC4_PODF 69
++#define IMX6SL_CLK_SSI1_PRED 70
++#define IMX6SL_CLK_SSI1_PODF 71
++#define IMX6SL_CLK_SSI2_PRED 72
++#define IMX6SL_CLK_SSI2_PODF 73
++#define IMX6SL_CLK_SSI3_PRED 74
++#define IMX6SL_CLK_SSI3_PODF 75
++#define IMX6SL_CLK_PERCLK 76
++#define IMX6SL_CLK_PXP_AXI_PODF 77
++#define IMX6SL_CLK_EPDC_AXI_PODF 78
++#define IMX6SL_CLK_GPU2D_OVG_PODF 79
++#define IMX6SL_CLK_GPU2D_PODF 80
++#define IMX6SL_CLK_LCDIF_PIX_PRED 81
++#define IMX6SL_CLK_EPDC_PIX_PRED 82
++#define IMX6SL_CLK_LCDIF_PIX_PODF 83
++#define IMX6SL_CLK_EPDC_PIX_PODF 84
++#define IMX6SL_CLK_SPDIF0_PRED 85
++#define IMX6SL_CLK_SPDIF0_PODF 86
++#define IMX6SL_CLK_SPDIF1_PRED 87
++#define IMX6SL_CLK_SPDIF1_PODF 88
++#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
++#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
++#define IMX6SL_CLK_ECSPI_ROOT 91
++#define IMX6SL_CLK_UART_ROOT 92
++#define IMX6SL_CLK_AHB 93
++#define IMX6SL_CLK_MMDC_ROOT 94
++#define IMX6SL_CLK_ARM 95
++#define IMX6SL_CLK_ECSPI1 96
++#define IMX6SL_CLK_ECSPI2 97
++#define IMX6SL_CLK_ECSPI3 98
++#define IMX6SL_CLK_ECSPI4 99
++#define IMX6SL_CLK_EPIT1 100
++#define IMX6SL_CLK_EPIT2 101
++#define IMX6SL_CLK_EXTERN_AUDIO 102
++#define IMX6SL_CLK_GPT 103
++#define IMX6SL_CLK_GPT_SERIAL 104
++#define IMX6SL_CLK_GPU2D_OVG 105
++#define IMX6SL_CLK_I2C1 106
++#define IMX6SL_CLK_I2C2 107
++#define IMX6SL_CLK_I2C3 108
++#define IMX6SL_CLK_OCOTP 109
++#define IMX6SL_CLK_CSI 110
++#define IMX6SL_CLK_PXP_AXI 111
++#define IMX6SL_CLK_EPDC_AXI 112
++#define IMX6SL_CLK_LCDIF_AXI 113
++#define IMX6SL_CLK_LCDIF_PIX 114
++#define IMX6SL_CLK_EPDC_PIX 115
++#define IMX6SL_CLK_OCRAM 116
++#define IMX6SL_CLK_PWM1 117
++#define IMX6SL_CLK_PWM2 118
++#define IMX6SL_CLK_PWM3 119
++#define IMX6SL_CLK_PWM4 120
++#define IMX6SL_CLK_SDMA 121
++#define IMX6SL_CLK_SPDIF 122
++#define IMX6SL_CLK_SSI1 123
++#define IMX6SL_CLK_SSI2 124
++#define IMX6SL_CLK_SSI3 125
++#define IMX6SL_CLK_UART 126
++#define IMX6SL_CLK_UART_SERIAL 127
++#define IMX6SL_CLK_USBOH3 128
++#define IMX6SL_CLK_USDHC1 129
++#define IMX6SL_CLK_USDHC2 130
++#define IMX6SL_CLK_USDHC3 131
++#define IMX6SL_CLK_USDHC4 132
++#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
++#define IMX6SL_CLK_ENET 134
++#define IMX6SL_CLK_UART_OSC_4M 135
++#define IMX6SL_CLK_SPBA 136
++#define IMX6SL_CLK_CLK_END 137
++
++#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/include/dt-bindings/clock/vf610-clock.h linux-linaro-stable-mx6/arch/arm/boot/dts/include/dt-bindings/clock/vf610-clock.h
+--- linux-3.10.30.orig/arch/arm/boot/dts/include/dt-bindings/clock/vf610-clock.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/include/dt-bindings/clock/vf610-clock.h 2014-05-15 20:34:14.046129478 +0200
+@@ -0,0 +1,165 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_VF610_H
++#define __DT_BINDINGS_CLOCK_VF610_H
++
++#define VF610_CLK_DUMMY 0
++#define VF610_CLK_SIRC_128K 1
++#define VF610_CLK_SIRC_32K 2
++#define VF610_CLK_FIRC 3
++#define VF610_CLK_SXOSC 4
++#define VF610_CLK_FXOSC 5
++#define VF610_CLK_FXOSC_HALF 6
++#define VF610_CLK_SLOW_CLK_SEL 7
++#define VF610_CLK_FASK_CLK_SEL 8
++#define VF610_CLK_AUDIO_EXT 9
++#define VF610_CLK_ENET_EXT 10
++#define VF610_CLK_PLL1_MAIN 11
++#define VF610_CLK_PLL1_PFD1 12
++#define VF610_CLK_PLL1_PFD2 13
++#define VF610_CLK_PLL1_PFD3 14
++#define VF610_CLK_PLL1_PFD4 15
++#define VF610_CLK_PLL2_MAIN 16
++#define VF610_CLK_PLL2_PFD1 17
++#define VF610_CLK_PLL2_PFD2 18
++#define VF610_CLK_PLL2_PFD3 19
++#define VF610_CLK_PLL2_PFD4 20
++#define VF610_CLK_PLL3_MAIN 21
++#define VF610_CLK_PLL3_PFD1 22
++#define VF610_CLK_PLL3_PFD2 23
++#define VF610_CLK_PLL3_PFD3 24
++#define VF610_CLK_PLL3_PFD4 25
++#define VF610_CLK_PLL4_MAIN 26
++#define VF610_CLK_PLL5_MAIN 27
++#define VF610_CLK_PLL6_MAIN 28
++#define VF610_CLK_PLL3_MAIN_DIV 29
++#define VF610_CLK_PLL4_MAIN_DIV 30
++#define VF610_CLK_PLL6_MAIN_DIV 31
++#define VF610_CLK_PLL1_PFD_SEL 32
++#define VF610_CLK_PLL2_PFD_SEL 33
++#define VF610_CLK_SYS_SEL 34
++#define VF610_CLK_DDR_SEL 35
++#define VF610_CLK_SYS_BUS 36
++#define VF610_CLK_PLATFORM_BUS 37
++#define VF610_CLK_IPG_BUS 38
++#define VF610_CLK_UART0 39
++#define VF610_CLK_UART1 40
++#define VF610_CLK_UART2 41
++#define VF610_CLK_UART3 42
++#define VF610_CLK_UART4 43
++#define VF610_CLK_UART5 44
++#define VF610_CLK_PIT 45
++#define VF610_CLK_I2C0 46
++#define VF610_CLK_I2C1 47
++#define VF610_CLK_I2C2 48
++#define VF610_CLK_I2C3 49
++#define VF610_CLK_FTM0_EXT_SEL 50
++#define VF610_CLK_FTM0_FIX_SEL 51
++#define VF610_CLK_FTM0_EXT_FIX_EN 52
++#define VF610_CLK_FTM1_EXT_SEL 53
++#define VF610_CLK_FTM1_FIX_SEL 54
++#define VF610_CLK_FTM1_EXT_FIX_EN 55
++#define VF610_CLK_FTM2_EXT_SEL 56
++#define VF610_CLK_FTM2_FIX_SEL 57
++#define VF610_CLK_FTM2_EXT_FIX_EN 58
++#define VF610_CLK_FTM3_EXT_SEL 59
++#define VF610_CLK_FTM3_FIX_SEL 60
++#define VF610_CLK_FTM3_EXT_FIX_EN 61
++#define VF610_CLK_FTM0 62
++#define VF610_CLK_FTM1 63
++#define VF610_CLK_FTM2 64
++#define VF610_CLK_FTM3 65
++#define VF610_CLK_ENET_50M 66
++#define VF610_CLK_ENET_25M 67
++#define VF610_CLK_ENET_SEL 68
++#define VF610_CLK_ENET 69
++#define VF610_CLK_ENET_TS_SEL 70
++#define VF610_CLK_ENET_TS 71
++#define VF610_CLK_DSPI0 72
++#define VF610_CLK_DSPI1 73
++#define VF610_CLK_DSPI2 74
++#define VF610_CLK_DSPI3 75
++#define VF610_CLK_WDT 76
++#define VF610_CLK_ESDHC0_SEL 77
++#define VF610_CLK_ESDHC0_EN 78
++#define VF610_CLK_ESDHC0_DIV 79
++#define VF610_CLK_ESDHC0 80
++#define VF610_CLK_ESDHC1_SEL 81
++#define VF610_CLK_ESDHC1_EN 82
++#define VF610_CLK_ESDHC1_DIV 83
++#define VF610_CLK_ESDHC1 84
++#define VF610_CLK_DCU0_SEL 85
++#define VF610_CLK_DCU0_EN 86
++#define VF610_CLK_DCU0_DIV 87
++#define VF610_CLK_DCU0 88
++#define VF610_CLK_DCU1_SEL 89
++#define VF610_CLK_DCU1_EN 90
++#define VF610_CLK_DCU1_DIV 91
++#define VF610_CLK_DCU1 92
++#define VF610_CLK_ESAI_SEL 93
++#define VF610_CLK_ESAI_EN 94
++#define VF610_CLK_ESAI_DIV 95
++#define VF610_CLK_ESAI 96
++#define VF610_CLK_SAI0_SEL 97
++#define VF610_CLK_SAI0_EN 98
++#define VF610_CLK_SAI0_DIV 99
++#define VF610_CLK_SAI0 100
++#define VF610_CLK_SAI1_SEL 101
++#define VF610_CLK_SAI1_EN 102
++#define VF610_CLK_SAI1_DIV 103
++#define VF610_CLK_SAI1 104
++#define VF610_CLK_SAI2_SEL 105
++#define VF610_CLK_SAI2_EN 106
++#define VF610_CLK_SAI2_DIV 107
++#define VF610_CLK_SAI2 108
++#define VF610_CLK_SAI3_SEL 109
++#define VF610_CLK_SAI3_EN 110
++#define VF610_CLK_SAI3_DIV 111
++#define VF610_CLK_SAI3 112
++#define VF610_CLK_USBC0 113
++#define VF610_CLK_USBC1 114
++#define VF610_CLK_QSPI0_SEL 115
++#define VF610_CLK_QSPI0_EN 116
++#define VF610_CLK_QSPI0_X4_DIV 117
++#define VF610_CLK_QSPI0_X2_DIV 118
++#define VF610_CLK_QSPI0_X1_DIV 119
++#define VF610_CLK_QSPI1_SEL 120
++#define VF610_CLK_QSPI1_EN 121
++#define VF610_CLK_QSPI1_X4_DIV 122
++#define VF610_CLK_QSPI1_X2_DIV 123
++#define VF610_CLK_QSPI1_X1_DIV 124
++#define VF610_CLK_QSPI0 125
++#define VF610_CLK_QSPI1 126
++#define VF610_CLK_NFC_SEL 127
++#define VF610_CLK_NFC_EN 128
++#define VF610_CLK_NFC_PRE_DIV 129
++#define VF610_CLK_NFC_FRAC_DIV 130
++#define VF610_CLK_NFC_INV 131
++#define VF610_CLK_NFC 132
++#define VF610_CLK_VADC_SEL 133
++#define VF610_CLK_VADC_EN 134
++#define VF610_CLK_VADC_DIV 135
++#define VF610_CLK_VADC_DIV_HALF 136
++#define VF610_CLK_VADC 137
++#define VF610_CLK_ADC0 138
++#define VF610_CLK_ADC1 139
++#define VF610_CLK_DAC0 140
++#define VF610_CLK_DAC1 141
++#define VF610_CLK_FLEXCAN0 142
++#define VF610_CLK_FLEXCAN1 143
++#define VF610_CLK_ASRC 144
++#define VF610_CLK_GPU_SEL 145
++#define VF610_CLK_GPU_EN 146
++#define VF610_CLK_GPU2D 147
++#define VF610_CLK_ENET0 148
++#define VF610_CLK_ENET1 149
++#define VF610_CLK_END 150
++
++#endif /* __DT_BINDINGS_CLOCK_VF610_H */
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/Makefile linux-linaro-stable-mx6/arch/arm/boot/dts/Makefile
+--- linux-3.10.30.orig/arch/arm/boot/dts/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/Makefile 2014-05-15 20:33:34.117841707 +0200
+@@ -113,14 +113,31 @@
+ imx53-mba53.dtb \
+ imx53-qsb.dtb \
+ imx53-smd.dtb \
++ imx6dl-cubox-i.dtb \
++ imx6dl-hummingboard.dtb \
+ imx6dl-sabreauto.dtb \
++ imx6dl-sabreauto-ecspi.dtb \
++ imx6dl-sabreauto-flexcan1.dtb \
++ imx6dl-sabreauto-gpmi-weim.dtb \
+ imx6dl-sabresd.dtb \
++ imx6dl-sabresd-hdcp.dtb \
++ imx6dl-sabresd-ldo.dtb \
+ imx6dl-wandboard.dtb \
+ imx6q-arm2.dtb \
++ imx6q-cubox-i.dtb \
+ imx6q-sabreauto.dtb \
++ imx6q-sabreauto-ecspi.dtb \
++ imx6q-sabreauto-flexcan1.dtb \
++ imx6q-sabreauto-gpmi-weim.dtb \
+ imx6q-sabrelite.dtb \
+ imx6q-sabresd.dtb \
+- imx6q-sbc6x.dtb
++ imx6q-sabresd-hdcp.dtb \
++ imx6q-sabresd-ldo.dtb \
++ imx6q-sbc6x.dtb \
++ imx6sl-evk.dtb \
++ imx6sl-evk-csi.dtb \
++ imx6sl-evk-ldo.dtb \
++ vf610-twr.dtb
+ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
+ imx23-olinuxino.dtb \
+ imx23-stmp378x_devb.dtb \
+@@ -202,7 +219,14 @@
+ dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
+ vexpress-v2p-ca9.dtb \
+ vexpress-v2p-ca15-tc1.dtb \
+- vexpress-v2p-ca15_a7.dtb
++ vexpress-v2p-ca15_a7.dtb \
++ rtsm_ve-cortex_a9x2.dtb \
++ rtsm_ve-cortex_a9x4.dtb \
++ rtsm_ve-cortex_a15x1.dtb \
++ rtsm_ve-cortex_a15x2.dtb \
++ rtsm_ve-cortex_a15x4.dtb \
++ rtsm_ve-v2p-ca15x1-ca7x1.dtb \
++ rtsm_ve-v2p-ca15x4-ca7x4.dtb
+ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
+ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
+ wm8505-ref.dtb \
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a15x1.dts linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a15x1.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a15x1.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a15x1.dts 2014-05-15 20:33:34.241842601 +0200
+@@ -0,0 +1,159 @@
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * ARMCortexA15x1CT
++ *
++ * RTSM_VE_Cortex_A15x1.lisa
++ */
++
++/dts-v1/;
++
++/ {
++ model = "RTSM_VE_CortexA15x1";
++ arm,vexpress,site = <0xf>;
++ compatible = "arm,rtsm_ve,cortex_a15x1", "arm,vexpress";
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ chosen { };
++
++ aliases {
++ serial0 = &v2m_serial0;
++ serial1 = &v2m_serial1;
++ serial2 = &v2m_serial2;
++ serial3 = &v2m_serial3;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <0>;
++ };
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0 0x80000000 0 0x80000000>;
++ };
++
++ gic: interrupt-controller@2c001000 {
++ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0 0x2c001000 0 0x1000>,
++ <0 0x2c002000 0 0x1000>,
++ <0 0x2c004000 0 0x2000>,
++ <0 0x2c006000 0 0x2000>;
++ interrupts = <1 9 0xf04>;
++ };
++
++ timer {
++ compatible = "arm,armv7-timer";
++ interrupts = <1 13 0xf08>,
++ <1 14 0xf08>,
++ <1 11 0xf08>,
++ <1 10 0xf08>;
++ };
++
++ dcc {
++ compatible = "arm,vexpress,config-bus";
++ arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++ osc@0 {
++ /* ACLK clock to the AXI master port on the test chip */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 0>;
++ freq-range = <30000000 50000000>;
++ #clock-cells = <0>;
++ clock-output-names = "extsaxiclk";
++ };
++
++ oscclk1: osc@1 {
++ /* Reference clock for the CLCD */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 1>;
++ freq-range = <10000000 80000000>;
++ #clock-cells = <0>;
++ clock-output-names = "clcdclk";
++ };
++
++ smbclk: oscclk2: osc@2 {
++ /* Reference clock for the test chip internal PLLs */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 2>;
++ freq-range = <33000000 100000000>;
++ #clock-cells = <0>;
++ clock-output-names = "tcrefclk";
++ };
++ };
++
++ smb {
++ compatible = "simple-bus";
++
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0 0x08000000 0x04000000>,
++ <1 0 0 0x14000000 0x04000000>,
++ <2 0 0 0x18000000 0x04000000>,
++ <3 0 0 0x1c000000 0x04000000>,
++ <4 0 0 0x0c000000 0x04000000>,
++ <5 0 0 0x10000000 0x04000000>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 63>;
++ interrupt-map = <0 0 0 &gic 0 0 4>,
++ <0 0 1 &gic 0 1 4>,
++ <0 0 2 &gic 0 2 4>,
++ <0 0 3 &gic 0 3 4>,
++ <0 0 4 &gic 0 4 4>,
++ <0 0 5 &gic 0 5 4>,
++ <0 0 6 &gic 0 6 4>,
++ <0 0 7 &gic 0 7 4>,
++ <0 0 8 &gic 0 8 4>,
++ <0 0 9 &gic 0 9 4>,
++ <0 0 10 &gic 0 10 4>,
++ <0 0 11 &gic 0 11 4>,
++ <0 0 12 &gic 0 12 4>,
++ <0 0 13 &gic 0 13 4>,
++ <0 0 14 &gic 0 14 4>,
++ <0 0 15 &gic 0 15 4>,
++ <0 0 16 &gic 0 16 4>,
++ <0 0 17 &gic 0 17 4>,
++ <0 0 18 &gic 0 18 4>,
++ <0 0 19 &gic 0 19 4>,
++ <0 0 20 &gic 0 20 4>,
++ <0 0 21 &gic 0 21 4>,
++ <0 0 22 &gic 0 22 4>,
++ <0 0 23 &gic 0 23 4>,
++ <0 0 24 &gic 0 24 4>,
++ <0 0 25 &gic 0 25 4>,
++ <0 0 26 &gic 0 26 4>,
++ <0 0 27 &gic 0 27 4>,
++ <0 0 28 &gic 0 28 4>,
++ <0 0 29 &gic 0 29 4>,
++ <0 0 30 &gic 0 30 4>,
++ <0 0 31 &gic 0 31 4>,
++ <0 0 32 &gic 0 32 4>,
++ <0 0 33 &gic 0 33 4>,
++ <0 0 34 &gic 0 34 4>,
++ <0 0 35 &gic 0 35 4>,
++ <0 0 36 &gic 0 36 4>,
++ <0 0 37 &gic 0 37 4>,
++ <0 0 38 &gic 0 38 4>,
++ <0 0 39 &gic 0 39 4>,
++ <0 0 40 &gic 0 40 4>,
++ <0 0 41 &gic 0 41 4>,
++ <0 0 42 &gic 0 42 4>;
++
++ /include/ "rtsm_ve-motherboard.dtsi"
++ };
++};
++
++/include/ "clcd-panels.dtsi"
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a15x2.dts linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a15x2.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a15x2.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a15x2.dts 2014-05-15 20:33:34.241842601 +0200
+@@ -0,0 +1,165 @@
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * ARMCortexA15x2CT
++ *
++ * RTSM_VE_Cortex_A15x2.lisa
++ */
++
++/dts-v1/;
++
++/ {
++ model = "RTSM_VE_CortexA15x2";
++ arm,vexpress,site = <0xf>;
++ compatible = "arm,rtsm_ve,cortex_a15x2", "arm,vexpress";
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ chosen { };
++
++ aliases {
++ serial0 = &v2m_serial0;
++ serial1 = &v2m_serial1;
++ serial2 = &v2m_serial2;
++ serial3 = &v2m_serial3;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <0>;
++ };
++
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <1>;
++ };
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0 0x80000000 0 0x80000000>;
++ };
++
++ gic: interrupt-controller@2c001000 {
++ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0 0x2c001000 0 0x1000>,
++ <0 0x2c002000 0 0x1000>,
++ <0 0x2c004000 0 0x2000>,
++ <0 0x2c006000 0 0x2000>;
++ interrupts = <1 9 0xf04>;
++ };
++
++ timer {
++ compatible = "arm,armv7-timer";
++ interrupts = <1 13 0xf08>,
++ <1 14 0xf08>,
++ <1 11 0xf08>,
++ <1 10 0xf08>;
++ };
++
++ dcc {
++ compatible = "arm,vexpress,config-bus";
++ arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++ osc@0 {
++ /* ACLK clock to the AXI master port on the test chip */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 0>;
++ freq-range = <30000000 50000000>;
++ #clock-cells = <0>;
++ clock-output-names = "extsaxiclk";
++ };
++
++ oscclk1: osc@1 {
++ /* Reference clock for the CLCD */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 1>;
++ freq-range = <10000000 80000000>;
++ #clock-cells = <0>;
++ clock-output-names = "clcdclk";
++ };
++
++ smbclk: oscclk2: osc@2 {
++ /* Reference clock for the test chip internal PLLs */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 2>;
++ freq-range = <33000000 100000000>;
++ #clock-cells = <0>;
++ clock-output-names = "tcrefclk";
++ };
++ };
++
++ smb {
++ compatible = "simple-bus";
++
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0 0x08000000 0x04000000>,
++ <1 0 0 0x14000000 0x04000000>,
++ <2 0 0 0x18000000 0x04000000>,
++ <3 0 0 0x1c000000 0x04000000>,
++ <4 0 0 0x0c000000 0x04000000>,
++ <5 0 0 0x10000000 0x04000000>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 63>;
++ interrupt-map = <0 0 0 &gic 0 0 4>,
++ <0 0 1 &gic 0 1 4>,
++ <0 0 2 &gic 0 2 4>,
++ <0 0 3 &gic 0 3 4>,
++ <0 0 4 &gic 0 4 4>,
++ <0 0 5 &gic 0 5 4>,
++ <0 0 6 &gic 0 6 4>,
++ <0 0 7 &gic 0 7 4>,
++ <0 0 8 &gic 0 8 4>,
++ <0 0 9 &gic 0 9 4>,
++ <0 0 10 &gic 0 10 4>,
++ <0 0 11 &gic 0 11 4>,
++ <0 0 12 &gic 0 12 4>,
++ <0 0 13 &gic 0 13 4>,
++ <0 0 14 &gic 0 14 4>,
++ <0 0 15 &gic 0 15 4>,
++ <0 0 16 &gic 0 16 4>,
++ <0 0 17 &gic 0 17 4>,
++ <0 0 18 &gic 0 18 4>,
++ <0 0 19 &gic 0 19 4>,
++ <0 0 20 &gic 0 20 4>,
++ <0 0 21 &gic 0 21 4>,
++ <0 0 22 &gic 0 22 4>,
++ <0 0 23 &gic 0 23 4>,
++ <0 0 24 &gic 0 24 4>,
++ <0 0 25 &gic 0 25 4>,
++ <0 0 26 &gic 0 26 4>,
++ <0 0 27 &gic 0 27 4>,
++ <0 0 28 &gic 0 28 4>,
++ <0 0 29 &gic 0 29 4>,
++ <0 0 30 &gic 0 30 4>,
++ <0 0 31 &gic 0 31 4>,
++ <0 0 32 &gic 0 32 4>,
++ <0 0 33 &gic 0 33 4>,
++ <0 0 34 &gic 0 34 4>,
++ <0 0 35 &gic 0 35 4>,
++ <0 0 36 &gic 0 36 4>,
++ <0 0 37 &gic 0 37 4>,
++ <0 0 38 &gic 0 38 4>,
++ <0 0 39 &gic 0 39 4>,
++ <0 0 40 &gic 0 40 4>,
++ <0 0 41 &gic 0 41 4>,
++ <0 0 42 &gic 0 42 4>;
++
++ /include/ "rtsm_ve-motherboard.dtsi"
++ };
++};
++
++/include/ "clcd-panels.dtsi"
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a15x4.dts linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a15x4.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a15x4.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a15x4.dts 2014-05-15 20:33:34.241842601 +0200
+@@ -0,0 +1,177 @@
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * ARMCortexA15x4CT
++ *
++ * RTSM_VE_Cortex_A15x4.lisa
++ */
++
++/dts-v1/;
++
++/ {
++ model = "RTSM_VE_CortexA15x4";
++ arm,vexpress,site = <0xf>;
++ compatible = "arm,rtsm_ve,cortex_a15x4", "arm,vexpress";
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ chosen { };
++
++ aliases {
++ serial0 = &v2m_serial0;
++ serial1 = &v2m_serial1;
++ serial2 = &v2m_serial2;
++ serial3 = &v2m_serial3;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <0>;
++ };
++
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <1>;
++ };
++
++ cpu@2 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <2>;
++ };
++
++ cpu@3 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <3>;
++ };
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0 0x80000000 0 0x80000000>;
++ };
++
++ gic: interrupt-controller@2c001000 {
++ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0 0x2c001000 0 0x1000>,
++ <0 0x2c002000 0 0x1000>,
++ <0 0x2c004000 0 0x2000>,
++ <0 0x2c006000 0 0x2000>;
++ interrupts = <1 9 0xf04>;
++ };
++
++ timer {
++ compatible = "arm,armv7-timer";
++ interrupts = <1 13 0xf08>,
++ <1 14 0xf08>,
++ <1 11 0xf08>,
++ <1 10 0xf08>;
++ };
++
++ dcc {
++ compatible = "arm,vexpress,config-bus";
++ arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++ osc@0 {
++ /* ACLK clock to the AXI master port on the test chip */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 0>;
++ freq-range = <30000000 50000000>;
++ #clock-cells = <0>;
++ clock-output-names = "extsaxiclk";
++ };
++
++ oscclk1: osc@1 {
++ /* Reference clock for the CLCD */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 1>;
++ freq-range = <10000000 80000000>;
++ #clock-cells = <0>;
++ clock-output-names = "clcdclk";
++ };
++
++ smbclk: oscclk2: osc@2 {
++ /* Reference clock for the test chip internal PLLs */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 2>;
++ freq-range = <33000000 100000000>;
++ #clock-cells = <0>;
++ clock-output-names = "tcrefclk";
++ };
++ };
++
++ smb {
++ compatible = "simple-bus";
++
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0 0x08000000 0x04000000>,
++ <1 0 0 0x14000000 0x04000000>,
++ <2 0 0 0x18000000 0x04000000>,
++ <3 0 0 0x1c000000 0x04000000>,
++ <4 0 0 0x0c000000 0x04000000>,
++ <5 0 0 0x10000000 0x04000000>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 63>;
++ interrupt-map = <0 0 0 &gic 0 0 4>,
++ <0 0 1 &gic 0 1 4>,
++ <0 0 2 &gic 0 2 4>,
++ <0 0 3 &gic 0 3 4>,
++ <0 0 4 &gic 0 4 4>,
++ <0 0 5 &gic 0 5 4>,
++ <0 0 6 &gic 0 6 4>,
++ <0 0 7 &gic 0 7 4>,
++ <0 0 8 &gic 0 8 4>,
++ <0 0 9 &gic 0 9 4>,
++ <0 0 10 &gic 0 10 4>,
++ <0 0 11 &gic 0 11 4>,
++ <0 0 12 &gic 0 12 4>,
++ <0 0 13 &gic 0 13 4>,
++ <0 0 14 &gic 0 14 4>,
++ <0 0 15 &gic 0 15 4>,
++ <0 0 16 &gic 0 16 4>,
++ <0 0 17 &gic 0 17 4>,
++ <0 0 18 &gic 0 18 4>,
++ <0 0 19 &gic 0 19 4>,
++ <0 0 20 &gic 0 20 4>,
++ <0 0 21 &gic 0 21 4>,
++ <0 0 22 &gic 0 22 4>,
++ <0 0 23 &gic 0 23 4>,
++ <0 0 24 &gic 0 24 4>,
++ <0 0 25 &gic 0 25 4>,
++ <0 0 26 &gic 0 26 4>,
++ <0 0 27 &gic 0 27 4>,
++ <0 0 28 &gic 0 28 4>,
++ <0 0 29 &gic 0 29 4>,
++ <0 0 30 &gic 0 30 4>,
++ <0 0 31 &gic 0 31 4>,
++ <0 0 32 &gic 0 32 4>,
++ <0 0 33 &gic 0 33 4>,
++ <0 0 34 &gic 0 34 4>,
++ <0 0 35 &gic 0 35 4>,
++ <0 0 36 &gic 0 36 4>,
++ <0 0 37 &gic 0 37 4>,
++ <0 0 38 &gic 0 38 4>,
++ <0 0 39 &gic 0 39 4>,
++ <0 0 40 &gic 0 40 4>,
++ <0 0 41 &gic 0 41 4>,
++ <0 0 42 &gic 0 42 4>;
++
++ /include/ "rtsm_ve-motherboard.dtsi"
++ };
++};
++
++/include/ "clcd-panels.dtsi"
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a9x2.dts linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a9x2.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a9x2.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a9x2.dts 2014-05-15 20:33:34.241842601 +0200
+@@ -0,0 +1,171 @@
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * ARMCortexA9MPx2CT
++ *
++ * RTSM_VE_Cortex_A9x2.lisa
++ */
++
++/dts-v1/;
++
++/ {
++ model = "RTSM_VE_CortexA9x2";
++ arm,vexpress,site = <0xf>;
++ compatible = "arm,rtsm_ve,cortex_a9x2", "arm,vexpress";
++ interrupt-parent = <&gic>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ chosen { };
++
++ aliases {
++ serial0 = &v2m_serial0;
++ serial1 = &v2m_serial1;
++ serial2 = &v2m_serial2;
++ serial3 = &v2m_serial3;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ reg = <0>;
++ };
++
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ reg = <1>;
++ };
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0x80000000 0x80000000>;
++ };
++
++ scu@2c000000 {
++ compatible = "arm,cortex-a9-scu";
++ reg = <0x2c000000 0x58>;
++ };
++
++ timer@2c000600 {
++ compatible = "arm,cortex-a9-twd-timer";
++ reg = <0x2c000600 0x20>;
++ interrupts = <1 13 0xf04>;
++ };
++
++ watchdog@2c000620 {
++ compatible = "arm,cortex-a9-twd-wdt";
++ reg = <0x2c000620 0x20>;
++ interrupts = <1 14 0xf04>;
++ };
++
++ gic: interrupt-controller@2c001000 {
++ compatible = "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0x2c001000 0x1000>,
++ <0x2c000100 0x100>;
++ };
++
++ dcc {
++ compatible = "arm,vexpress,config-bus";
++ arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++ osc@0 {
++ /* ACLK clock to the AXI master port on the test chip */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 0>;
++ freq-range = <30000000 50000000>;
++ #clock-cells = <0>;
++ clock-output-names = "extsaxiclk";
++ };
++
++ oscclk1: osc@1 {
++ /* Reference clock for the CLCD */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 1>;
++ freq-range = <10000000 80000000>;
++ #clock-cells = <0>;
++ clock-output-names = "clcdclk";
++ };
++
++ smbclk: oscclk2: osc@2 {
++ /* Reference clock for the test chip internal PLLs */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 2>;
++ freq-range = <33000000 100000000>;
++ #clock-cells = <0>;
++ clock-output-names = "tcrefclk";
++ };
++ };
++
++ smb {
++ compatible = "simple-bus";
++
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0x08000000 0x04000000>,
++ <1 0 0x14000000 0x04000000>,
++ <2 0 0x18000000 0x04000000>,
++ <3 0 0x1c000000 0x04000000>,
++ <4 0 0x0c000000 0x04000000>,
++ <5 0 0x10000000 0x04000000>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 63>;
++ interrupt-map = <0 0 0 &gic 0 0 4>,
++ <0 0 1 &gic 0 1 4>,
++ <0 0 2 &gic 0 2 4>,
++ <0 0 3 &gic 0 3 4>,
++ <0 0 4 &gic 0 4 4>,
++ <0 0 5 &gic 0 5 4>,
++ <0 0 6 &gic 0 6 4>,
++ <0 0 7 &gic 0 7 4>,
++ <0 0 8 &gic 0 8 4>,
++ <0 0 9 &gic 0 9 4>,
++ <0 0 10 &gic 0 10 4>,
++ <0 0 11 &gic 0 11 4>,
++ <0 0 12 &gic 0 12 4>,
++ <0 0 13 &gic 0 13 4>,
++ <0 0 14 &gic 0 14 4>,
++ <0 0 15 &gic 0 15 4>,
++ <0 0 16 &gic 0 16 4>,
++ <0 0 17 &gic 0 17 4>,
++ <0 0 18 &gic 0 18 4>,
++ <0 0 19 &gic 0 19 4>,
++ <0 0 20 &gic 0 20 4>,
++ <0 0 21 &gic 0 21 4>,
++ <0 0 22 &gic 0 22 4>,
++ <0 0 23 &gic 0 23 4>,
++ <0 0 24 &gic 0 24 4>,
++ <0 0 25 &gic 0 25 4>,
++ <0 0 26 &gic 0 26 4>,
++ <0 0 27 &gic 0 27 4>,
++ <0 0 28 &gic 0 28 4>,
++ <0 0 29 &gic 0 29 4>,
++ <0 0 30 &gic 0 30 4>,
++ <0 0 31 &gic 0 31 4>,
++ <0 0 32 &gic 0 32 4>,
++ <0 0 33 &gic 0 33 4>,
++ <0 0 34 &gic 0 34 4>,
++ <0 0 35 &gic 0 35 4>,
++ <0 0 36 &gic 0 36 4>,
++ <0 0 37 &gic 0 37 4>,
++ <0 0 38 &gic 0 38 4>,
++ <0 0 39 &gic 0 39 4>,
++ <0 0 40 &gic 0 40 4>,
++ <0 0 41 &gic 0 41 4>,
++ <0 0 42 &gic 0 42 4>;
++
++ /include/ "rtsm_ve-motherboard.dtsi"
++ };
++};
++
++/include/ "clcd-panels.dtsi"
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a9x4.dts linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a9x4.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-cortex_a9x4.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-cortex_a9x4.dts 2014-05-15 20:33:34.245842631 +0200
+@@ -0,0 +1,183 @@
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * ARMCortexA9MPx4CT
++ *
++ * RTSM_VE_Cortex_A9x4.lisa
++ */
++
++/dts-v1/;
++
++/ {
++ model = "RTSM_VE_CortexA9x4";
++ arm,vexpress,site = <0xf>;
++ compatible = "arm,rtsm_ve,cortex_a9x4", "arm,vexpress";
++ interrupt-parent = <&gic>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ chosen { };
++
++ aliases {
++ serial0 = &v2m_serial0;
++ serial1 = &v2m_serial1;
++ serial2 = &v2m_serial2;
++ serial3 = &v2m_serial3;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ reg = <0>;
++ };
++
++ cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ reg = <1>;
++ };
++
++ cpu@2 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ reg = <2>;
++ };
++
++ cpu@3 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a9";
++ reg = <3>;
++ };
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0x80000000 0x80000000>;
++ };
++
++ scu@2c000000 {
++ compatible = "arm,cortex-a9-scu";
++ reg = <0x2c000000 0x58>;
++ };
++
++ timer@2c000600 {
++ compatible = "arm,cortex-a9-twd-timer";
++ reg = <0x2c000600 0x20>;
++ interrupts = <1 13 0xf04>;
++ };
++
++ watchdog@2c000620 {
++ compatible = "arm,cortex-a9-twd-wdt";
++ reg = <0x2c000620 0x20>;
++ interrupts = <1 14 0xf04>;
++ };
++
++ gic: interrupt-controller@2c001000 {
++ compatible = "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0x2c001000 0x1000>,
++ <0x2c000100 0x100>;
++ };
++
++ dcc {
++ compatible = "arm,vexpress,config-bus";
++ arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++ osc@0 {
++ /* ACLK clock to the AXI master port on the test chip */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 0>;
++ freq-range = <30000000 50000000>;
++ #clock-cells = <0>;
++ clock-output-names = "extsaxiclk";
++ };
++
++ oscclk1: osc@1 {
++ /* Reference clock for the CLCD */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 1>;
++ freq-range = <10000000 80000000>;
++ #clock-cells = <0>;
++ clock-output-names = "clcdclk";
++ };
++
++ smbclk: oscclk2: osc@2 {
++ /* Reference clock for the test chip internal PLLs */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 2>;
++ freq-range = <33000000 100000000>;
++ #clock-cells = <0>;
++ clock-output-names = "tcrefclk";
++ };
++ };
++
++ smb {
++ compatible = "simple-bus";
++
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0x08000000 0x04000000>,
++ <1 0 0x14000000 0x04000000>,
++ <2 0 0x18000000 0x04000000>,
++ <3 0 0x1c000000 0x04000000>,
++ <4 0 0x0c000000 0x04000000>,
++ <5 0 0x10000000 0x04000000>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 63>;
++ interrupt-map = <0 0 0 &gic 0 0 4>,
++ <0 0 1 &gic 0 1 4>,
++ <0 0 2 &gic 0 2 4>,
++ <0 0 3 &gic 0 3 4>,
++ <0 0 4 &gic 0 4 4>,
++ <0 0 5 &gic 0 5 4>,
++ <0 0 6 &gic 0 6 4>,
++ <0 0 7 &gic 0 7 4>,
++ <0 0 8 &gic 0 8 4>,
++ <0 0 9 &gic 0 9 4>,
++ <0 0 10 &gic 0 10 4>,
++ <0 0 11 &gic 0 11 4>,
++ <0 0 12 &gic 0 12 4>,
++ <0 0 13 &gic 0 13 4>,
++ <0 0 14 &gic 0 14 4>,
++ <0 0 15 &gic 0 15 4>,
++ <0 0 16 &gic 0 16 4>,
++ <0 0 17 &gic 0 17 4>,
++ <0 0 18 &gic 0 18 4>,
++ <0 0 19 &gic 0 19 4>,
++ <0 0 20 &gic 0 20 4>,
++ <0 0 21 &gic 0 21 4>,
++ <0 0 22 &gic 0 22 4>,
++ <0 0 23 &gic 0 23 4>,
++ <0 0 24 &gic 0 24 4>,
++ <0 0 25 &gic 0 25 4>,
++ <0 0 26 &gic 0 26 4>,
++ <0 0 27 &gic 0 27 4>,
++ <0 0 28 &gic 0 28 4>,
++ <0 0 29 &gic 0 29 4>,
++ <0 0 30 &gic 0 30 4>,
++ <0 0 31 &gic 0 31 4>,
++ <0 0 32 &gic 0 32 4>,
++ <0 0 33 &gic 0 33 4>,
++ <0 0 34 &gic 0 34 4>,
++ <0 0 35 &gic 0 35 4>,
++ <0 0 36 &gic 0 36 4>,
++ <0 0 37 &gic 0 37 4>,
++ <0 0 38 &gic 0 38 4>,
++ <0 0 39 &gic 0 39 4>,
++ <0 0 40 &gic 0 40 4>,
++ <0 0 41 &gic 0 41 4>,
++ <0 0 42 &gic 0 42 4>;
++
++ /include/ "rtsm_ve-motherboard.dtsi"
++ };
++};
++
++/include/ "clcd-panels.dtsi"
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-motherboard.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-motherboard.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-motherboard.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-motherboard.dtsi 2014-05-15 20:33:34.249842659 +0200
+@@ -0,0 +1,231 @@
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * Motherboard component
++ *
++ * VEMotherBoard.lisa
++ */
++
++ motherboard {
++ compatible = "arm,vexpress,v2m-p1", "simple-bus";
++ arm,hbi = <0x190>;
++ arm,vexpress,site = <0>;
++ arm,v2m-memory-map = "rs1";
++ #address-cells = <2>; /* SMB chipselect number and offset */
++ #size-cells = <1>;
++ #interrupt-cells = <1>;
++ ranges;
++
++ flash@0,00000000 {
++ compatible = "arm,vexpress-flash", "cfi-flash";
++ reg = <0 0x00000000 0x04000000>,
++ <4 0x00000000 0x04000000>;
++ bank-width = <4>;
++ };
++
++ vram@2,00000000 {
++ compatible = "arm,vexpress-vram";
++ reg = <2 0x00000000 0x00800000>;
++ };
++
++ ethernet@2,02000000 {
++ compatible = "smsc,lan91c111";
++ reg = <2 0x02000000 0x10000>;
++ interrupts = <15>;
++ };
++
++ iofpga@3,00000000 {
++ compatible = "arm,amba-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 3 0 0x200000>;
++
++ v2m_sysreg: sysreg@010000 {
++ compatible = "arm,vexpress-sysreg";
++ reg = <0x010000 0x1000>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ v2m_sysctl: sysctl@020000 {
++ compatible = "arm,sp810", "arm,primecell";
++ reg = <0x020000 0x1000>;
++ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
++ clock-names = "refclk", "timclk", "apb_pclk";
++ #clock-cells = <1>;
++ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
++ };
++
++ aaci@040000 {
++ compatible = "arm,pl041", "arm,primecell";
++ reg = <0x040000 0x1000>;
++ interrupts = <11>;
++ clocks = <&smbclk>;
++ clock-names = "apb_pclk";
++ };
++
++ mmci@050000 {
++ compatible = "arm,pl180", "arm,primecell";
++ reg = <0x050000 0x1000>;
++ interrupts = <9 10>;
++ cd-gpios = <&v2m_sysreg 0 0>;
++ wp-gpios = <&v2m_sysreg 1 0>;
++ max-frequency = <12000000>;
++ vmmc-supply = <&v2m_fixed_3v3>;
++ clocks = <&v2m_clk24mhz>, <&smbclk>;
++ clock-names = "mclk", "apb_pclk";
++ };
++
++ kmi@060000 {
++ compatible = "arm,pl050", "arm,primecell";
++ reg = <0x060000 0x1000>;
++ interrupts = <12>;
++ clocks = <&v2m_clk24mhz>, <&smbclk>;
++ clock-names = "KMIREFCLK", "apb_pclk";
++ };
++
++ kmi@070000 {
++ compatible = "arm,pl050", "arm,primecell";
++ reg = <0x070000 0x1000>;
++ interrupts = <13>;
++ clocks = <&v2m_clk24mhz>, <&smbclk>;
++ clock-names = "KMIREFCLK", "apb_pclk";
++ };
++
++ v2m_serial0: uart@090000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x090000 0x1000>;
++ interrupts = <5>;
++ clocks = <&v2m_clk24mhz>, <&smbclk>;
++ clock-names = "uartclk", "apb_pclk";
++ };
++
++ v2m_serial1: uart@0a0000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x0a0000 0x1000>;
++ interrupts = <6>;
++ clocks = <&v2m_clk24mhz>, <&smbclk>;
++ clock-names = "uartclk", "apb_pclk";
++ };
++
++ v2m_serial2: uart@0b0000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x0b0000 0x1000>;
++ interrupts = <7>;
++ clocks = <&v2m_clk24mhz>, <&smbclk>;
++ clock-names = "uartclk", "apb_pclk";
++ };
++
++ v2m_serial3: uart@0c0000 {
++ compatible = "arm,pl011", "arm,primecell";
++ reg = <0x0c0000 0x1000>;
++ interrupts = <8>;
++ clocks = <&v2m_clk24mhz>, <&smbclk>;
++ clock-names = "uartclk", "apb_pclk";
++ };
++
++ wdt@0f0000 {
++ compatible = "arm,sp805", "arm,primecell";
++ reg = <0x0f0000 0x1000>;
++ interrupts = <0>;
++ clocks = <&v2m_refclk32khz>, <&smbclk>;
++ clock-names = "wdogclk", "apb_pclk";
++ };
++
++ v2m_timer01: timer@110000 {
++ compatible = "arm,sp804", "arm,primecell";
++ reg = <0x110000 0x1000>;
++ interrupts = <2>;
++ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
++ clock-names = "timclken1", "timclken2", "apb_pclk";
++ };
++
++ v2m_timer23: timer@120000 {
++ compatible = "arm,sp804", "arm,primecell";
++ reg = <0x120000 0x1000>;
++ interrupts = <3>;
++ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
++ clock-names = "timclken1", "timclken2", "apb_pclk";
++ };
++
++ rtc@170000 {
++ compatible = "arm,pl031", "arm,primecell";
++ reg = <0x170000 0x1000>;
++ interrupts = <4>;
++ clocks = <&smbclk>;
++ clock-names = "apb_pclk";
++ };
++
++ clcd@1f0000 {
++ compatible = "arm,pl111", "arm,primecell";
++ reg = <0x1f0000 0x1000>;
++ interrupts = <14>;
++ clocks = <&v2m_oscclk1>, <&smbclk>;
++ clock-names = "v2m:oscclk1", "apb_pclk";
++ mode = "VGA";
++ use_dma = <0>;
++ framebuffer = <0x18000000 0x00180000>;
++ };
++
++ virtio_block@0130000 {
++ compatible = "virtio,mmio";
++ reg = <0x130000 0x200>;
++ interrupts = <42>;
++ };
++
++ };
++
++ v2m_fixed_3v3: fixedregulator@0 {
++ compatible = "regulator-fixed";
++ regulator-name = "3V3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ v2m_clk24mhz: clk24mhz {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <24000000>;
++ clock-output-names = "v2m:clk24mhz";
++ };
++
++ v2m_refclk1mhz: refclk1mhz {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <1000000>;
++ clock-output-names = "v2m:refclk1mhz";
++ };
++
++ v2m_refclk32khz: refclk32khz {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <32768>;
++ clock-output-names = "v2m:refclk32khz";
++ };
++
++ mcc {
++ compatible = "simple-bus";
++ arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++ v2m_oscclk1: osc@1 {
++ /* CLCD clock */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 1>;
++ freq-range = <23750000 63500000>;
++ #clock-cells = <0>;
++ clock-output-names = "v2m:oscclk1";
++ };
++
++ muxfpga@0 {
++ compatible = "arm,vexpress-muxfpga";
++ arm,vexpress-sysreg,func = <7 0>;
++ };
++
++ shutdown@0 {
++ compatible = "arm,vexpress-shutdown";
++ arm,vexpress-sysreg,func = <8 0>;
++ };
++ };
++ };
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-v2p-ca15x1-ca7x1.dts 2014-05-15 20:33:34.249842659 +0200
+@@ -0,0 +1,244 @@
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * ARMCortexA15x4CT
++ * ARMCortexA7x4CT
++ * RTSM_VE_Cortex_A15x1_A7x1.lisa
++ */
++
++/dts-v1/;
++
++/memreserve/ 0xff000000 0x01000000;
++
++/ {
++ model = "RTSM_VE_CortexA15x1-A7x1";
++ arm,vexpress,site = <0xf>;
++ compatible = "arm,rtsm_ve,cortex_a15x1_a7x1", "arm,vexpress";
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ chosen { };
++
++ aliases {
++ serial0 = &v2m_serial0;
++ serial1 = &v2m_serial1;
++ serial2 = &v2m_serial2;
++ serial3 = &v2m_serial3;
++ };
++
++ clusters {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cluster0: cluster@0 {
++ reg = <0>;
++// freqs = <500000000 600000000 700000000 800000000 900000000 1000000000 1100000000 1200000000>;
++ cores {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ core0: core@0 {
++ reg = <0>;
++ };
++
++ };
++ };
++
++ cluster1: cluster@1 {
++ reg = <1>;
++// freqs = <350000000 400000000 500000000 600000000 700000000 800000000 900000000 1000000000>;
++ cores {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ core1: core@0 {
++ reg = <0>;
++ };
++
++ };
++ };
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <0>;
++ cluster = <&cluster0>;
++ core = <&core0>;
++// clock-frequency = <1000000000>;
++ cci-control-port = <&cci_control1>;
++ };
++
++ cpu1: cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0x100>;
++ cluster = <&cluster1>;
++ core = <&core1>;
++// clock-frequency = <800000000>;
++ cci-control-port = <&cci_control2>;
++ };
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0 0x80000000 0 0x80000000>;
++ };
++
++ cci@2c090000 {
++ compatible = "arm,cci-400", "arm,cci";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0 0x2c090000 0 0x1000>;
++ ranges = <0x0 0x0 0x2c090000 0x10000>;
++
++ cci_control1: slave-if@4000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace";
++ reg = <0x4000 0x1000>;
++ };
++
++ cci_control2: slave-if@5000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace";
++ reg = <0x5000 0x1000>;
++ };
++ };
++
++ dcscb@60000000 {
++ compatible = "arm,rtsm,dcscb";
++ reg = <0 0x60000000 0 0x1000>;
++ };
++
++ gic: interrupt-controller@2c001000 {
++ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0 0x2c001000 0 0x1000>,
++ <0 0x2c002000 0 0x1000>,
++ <0 0x2c004000 0 0x2000>,
++ <0 0x2c006000 0 0x2000>;
++ interrupts = <1 9 0xf04>;
++
++ gic-cpuif@0 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <0>;
++ cpu = <&cpu0>;
++ };
++ gic-cpuif@1 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <1>;
++ cpu = <&cpu1>;
++ };
++ };
++
++ timer {
++ compatible = "arm,armv7-timer";
++ interrupts = <1 13 0xf08>,
++ <1 14 0xf08>,
++ <1 11 0xf08>,
++ <1 10 0xf08>;
++ };
++
++ dcc {
++ compatible = "arm,vexpress,config-bus";
++ arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++ osc@0 {
++ /* ACLK clock to the AXI master port on the test chip */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 0>;
++ freq-range = <30000000 50000000>;
++ #clock-cells = <0>;
++ clock-output-names = "extsaxiclk";
++ };
++
++ oscclk1: osc@1 {
++ /* Reference clock for the CLCD */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 1>;
++ freq-range = <10000000 80000000>;
++ #clock-cells = <0>;
++ clock-output-names = "clcdclk";
++ };
++
++ smbclk: oscclk2: osc@2 {
++ /* Reference clock for the test chip internal PLLs */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 2>;
++ freq-range = <33000000 100000000>;
++ #clock-cells = <0>;
++ clock-output-names = "tcrefclk";
++ };
++ };
++
++ smb {
++ compatible = "simple-bus";
++
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0 0x08000000 0x04000000>,
++ <1 0 0 0x14000000 0x04000000>,
++ <2 0 0 0x18000000 0x04000000>,
++ <3 0 0 0x1c000000 0x04000000>,
++ <4 0 0 0x0c000000 0x04000000>,
++ <5 0 0 0x10000000 0x04000000>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 63>;
++ interrupt-map = <0 0 0 &gic 0 0 4>,
++ <0 0 1 &gic 0 1 4>,
++ <0 0 2 &gic 0 2 4>,
++ <0 0 3 &gic 0 3 4>,
++ <0 0 4 &gic 0 4 4>,
++ <0 0 5 &gic 0 5 4>,
++ <0 0 6 &gic 0 6 4>,
++ <0 0 7 &gic 0 7 4>,
++ <0 0 8 &gic 0 8 4>,
++ <0 0 9 &gic 0 9 4>,
++ <0 0 10 &gic 0 10 4>,
++ <0 0 11 &gic 0 11 4>,
++ <0 0 12 &gic 0 12 4>,
++ <0 0 13 &gic 0 13 4>,
++ <0 0 14 &gic 0 14 4>,
++ <0 0 15 &gic 0 15 4>,
++ <0 0 16 &gic 0 16 4>,
++ <0 0 17 &gic 0 17 4>,
++ <0 0 18 &gic 0 18 4>,
++ <0 0 19 &gic 0 19 4>,
++ <0 0 20 &gic 0 20 4>,
++ <0 0 21 &gic 0 21 4>,
++ <0 0 22 &gic 0 22 4>,
++ <0 0 23 &gic 0 23 4>,
++ <0 0 24 &gic 0 24 4>,
++ <0 0 25 &gic 0 25 4>,
++ <0 0 26 &gic 0 26 4>,
++ <0 0 27 &gic 0 27 4>,
++ <0 0 28 &gic 0 28 4>,
++ <0 0 29 &gic 0 29 4>,
++ <0 0 30 &gic 0 30 4>,
++ <0 0 31 &gic 0 31 4>,
++ <0 0 32 &gic 0 32 4>,
++ <0 0 33 &gic 0 33 4>,
++ <0 0 34 &gic 0 34 4>,
++ <0 0 35 &gic 0 35 4>,
++ <0 0 36 &gic 0 36 4>,
++ <0 0 37 &gic 0 37 4>,
++ <0 0 38 &gic 0 38 4>,
++ <0 0 39 &gic 0 39 4>,
++ <0 0 40 &gic 0 40 4>,
++ <0 0 41 &gic 0 41 4>,
++ <0 0 42 &gic 0 42 4>;
++
++ /include/ "rtsm_ve-motherboard.dtsi"
++ };
++};
++
++/include/ "clcd-panels.dtsi"
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/rtsm_ve-v2p-ca15x4-ca7x4.dts 2014-05-15 20:33:34.249842659 +0200
+@@ -0,0 +1,358 @@
++/*
++ * ARM Ltd. Fast Models
++ *
++ * Versatile Express (VE) system model
++ * ARMCortexA15x4CT
++ * ARMCortexA7x4CT
++ * RTSM_VE_Cortex_A15x4_A7x4.lisa
++ */
++
++/dts-v1/;
++
++/memreserve/ 0xff000000 0x01000000;
++
++/ {
++ model = "RTSM_VE_CortexA15x4-A7x4";
++ arm,vexpress,site = <0xf>;
++ compatible = "arm,rtsm_ve,cortex_a15x4_a7x4", "arm,vexpress";
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ chosen { };
++
++ aliases {
++ serial0 = &v2m_serial0;
++ serial1 = &v2m_serial1;
++ serial2 = &v2m_serial2;
++ serial3 = &v2m_serial3;
++ };
++
++ clusters {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cluster0: cluster@0 {
++ reg = <0>;
++// freqs = <500000000 600000000 700000000 800000000 900000000 1000000000 1100000000 1200000000>;
++ cores {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ core0: core@0 {
++ reg = <0>;
++ };
++
++ core1: core@1 {
++ reg = <1>;
++ };
++
++ core2: core@2 {
++ reg = <2>;
++ };
++
++ core3: core@3 {
++ reg = <3>;
++ };
++
++ };
++ };
++
++ cluster1: cluster@1 {
++ reg = <1>;
++// freqs = <350000000 400000000 500000000 600000000 700000000 800000000 900000000 1000000000>;
++ cores {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ core4: core@0 {
++ reg = <0>;
++ };
++
++ core5: core@1 {
++ reg = <1>;
++ };
++
++ core6: core@2 {
++ reg = <2>;
++ };
++
++ core7: core@3 {
++ reg = <3>;
++ };
++
++ };
++ };
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <0>;
++ cluster = <&cluster0>;
++ core = <&core0>;
++// clock-frequency = <1000000000>;
++ cci-control-port = <&cci_control1>;
++ };
++
++ cpu1: cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <1>;
++ cluster = <&cluster0>;
++ core = <&core1>;
++// clock-frequency = <1000000000>;
++ cci-control-port = <&cci_control1>;
++ };
++
++ cpu2: cpu@2 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <2>;
++ cluster = <&cluster0>;
++ core = <&core2>;
++// clock-frequency = <1000000000>;
++ cci-control-port = <&cci_control1>;
++ };
++
++ cpu3: cpu@3 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <3>;
++ cluster = <&cluster0>;
++ core = <&core3>;
++// clock-frequency = <1000000000>;
++ cci-control-port = <&cci_control1>;
++ };
++
++ cpu4: cpu@4 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0x100>;
++ cluster = <&cluster1>;
++ core = <&core4>;
++// clock-frequency = <800000000>;
++ cci-control-port = <&cci_control2>;
++ };
++
++ cpu5: cpu@5 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0x101>;
++ cluster = <&cluster1>;
++ core = <&core5>;
++// clock-frequency = <800000000>;
++ cci-control-port = <&cci_control2>;
++ };
++
++ cpu6: cpu@6 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0x102>;
++ cluster = <&cluster1>;
++ core = <&core6>;
++// clock-frequency = <800000000>;
++ cci-control-port = <&cci_control2>;
++ };
++
++ cpu7: cpu@7 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ reg = <0x103>;
++ cluster = <&cluster1>;
++ core = <&core7>;
++// clock-frequency = <800000000>;
++ cci-control-port = <&cci_control2>;
++ };
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0 0x80000000 0 0x80000000>;
++ };
++
++ cci@2c090000 {
++ compatible = "arm,cci-400", "arm,cci";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0 0x2c090000 0 0x1000>;
++ ranges = <0x0 0x0 0x2c090000 0x10000>;
++
++ cci_control1: slave-if@4000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace";
++ reg = <0x4000 0x1000>;
++ };
++
++ cci_control2: slave-if@5000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace";
++ reg = <0x5000 0x1000>;
++ };
++ };
++
++ dcscb@60000000 {
++ compatible = "arm,rtsm,dcscb";
++ reg = <0 0x60000000 0 0x1000>;
++ };
++
++ gic: interrupt-controller@2c001000 {
++ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0 0x2c001000 0 0x1000>,
++ <0 0x2c002000 0 0x1000>,
++ <0 0x2c004000 0 0x2000>,
++ <0 0x2c006000 0 0x2000>;
++ interrupts = <1 9 0xf04>;
++
++ gic-cpuif@0 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <0>;
++ cpu = <&cpu0>;
++ };
++ gic-cpuif@1 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <1>;
++ cpu = <&cpu1>;
++ };
++ gic-cpuif@2 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <2>;
++ cpu = <&cpu2>;
++ };
++ gic-cpuif@3 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <3>;
++ cpu = <&cpu3>;
++ };
++ gic-cpuif@4 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <4>;
++ cpu = <&cpu4>;
++ };
++ gic-cpuif@5 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <5>;
++ cpu = <&cpu5>;
++ };
++ gic-cpuif@6 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <6>;
++ cpu = <&cpu6>;
++ };
++ gic-cpuif@7 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <7>;
++ cpu = <&cpu7>;
++ };
++ };
++
++ timer {
++ compatible = "arm,armv7-timer";
++ interrupts = <1 13 0xf08>,
++ <1 14 0xf08>,
++ <1 11 0xf08>,
++ <1 10 0xf08>;
++ };
++
++ dcc {
++ compatible = "arm,vexpress,config-bus";
++ arm,vexpress,config-bridge = <&v2m_sysreg>;
++
++ osc@0 {
++ /* ACLK clock to the AXI master port on the test chip */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 0>;
++ freq-range = <30000000 50000000>;
++ #clock-cells = <0>;
++ clock-output-names = "extsaxiclk";
++ };
++
++ oscclk1: osc@1 {
++ /* Reference clock for the CLCD */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 1>;
++ freq-range = <10000000 80000000>;
++ #clock-cells = <0>;
++ clock-output-names = "clcdclk";
++ };
++
++ smbclk: oscclk2: osc@2 {
++ /* Reference clock for the test chip internal PLLs */
++ compatible = "arm,vexpress-osc";
++ arm,vexpress-sysreg,func = <1 2>;
++ freq-range = <33000000 100000000>;
++ #clock-cells = <0>;
++ clock-output-names = "tcrefclk";
++ };
++ };
++
++ smb {
++ compatible = "simple-bus";
++
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0 0x08000000 0x04000000>,
++ <1 0 0 0x14000000 0x04000000>,
++ <2 0 0 0x18000000 0x04000000>,
++ <3 0 0 0x1c000000 0x04000000>,
++ <4 0 0 0x0c000000 0x04000000>,
++ <5 0 0 0x10000000 0x04000000>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 63>;
++ interrupt-map = <0 0 0 &gic 0 0 4>,
++ <0 0 1 &gic 0 1 4>,
++ <0 0 2 &gic 0 2 4>,
++ <0 0 3 &gic 0 3 4>,
++ <0 0 4 &gic 0 4 4>,
++ <0 0 5 &gic 0 5 4>,
++ <0 0 6 &gic 0 6 4>,
++ <0 0 7 &gic 0 7 4>,
++ <0 0 8 &gic 0 8 4>,
++ <0 0 9 &gic 0 9 4>,
++ <0 0 10 &gic 0 10 4>,
++ <0 0 11 &gic 0 11 4>,
++ <0 0 12 &gic 0 12 4>,
++ <0 0 13 &gic 0 13 4>,
++ <0 0 14 &gic 0 14 4>,
++ <0 0 15 &gic 0 15 4>,
++ <0 0 16 &gic 0 16 4>,
++ <0 0 17 &gic 0 17 4>,
++ <0 0 18 &gic 0 18 4>,
++ <0 0 19 &gic 0 19 4>,
++ <0 0 20 &gic 0 20 4>,
++ <0 0 21 &gic 0 21 4>,
++ <0 0 22 &gic 0 22 4>,
++ <0 0 23 &gic 0 23 4>,
++ <0 0 24 &gic 0 24 4>,
++ <0 0 25 &gic 0 25 4>,
++ <0 0 26 &gic 0 26 4>,
++ <0 0 27 &gic 0 27 4>,
++ <0 0 28 &gic 0 28 4>,
++ <0 0 29 &gic 0 29 4>,
++ <0 0 30 &gic 0 30 4>,
++ <0 0 31 &gic 0 31 4>,
++ <0 0 32 &gic 0 32 4>,
++ <0 0 33 &gic 0 33 4>,
++ <0 0 34 &gic 0 34 4>,
++ <0 0 35 &gic 0 35 4>,
++ <0 0 36 &gic 0 36 4>,
++ <0 0 37 &gic 0 37 4>,
++ <0 0 38 &gic 0 38 4>,
++ <0 0 39 &gic 0 39 4>,
++ <0 0 40 &gic 0 40 4>,
++ <0 0 41 &gic 0 41 4>,
++ <0 0 42 &gic 0 42 4>;
++
++ /include/ "rtsm_ve-motherboard.dtsi"
++ };
++};
++
++/include/ "clcd-panels.dtsi"
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2m.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2m.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2m.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2m.dtsi 2014-05-15 20:33:34.281842890 +0200
+@@ -227,6 +227,7 @@
+ };
+
+ clcd@1f000 {
++ status = "disabled";
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f000 0x1000>;
+ interrupts = <14>;
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi 2014-05-15 20:33:34.281842890 +0200
+@@ -228,6 +228,7 @@
+ };
+
+ clcd@1f0000 {
++ status = "disabled";
+ compatible = "arm,pl111", "arm,primecell";
+ reg = <0x1f0000 0x1000>;
+ interrupts = <14>;
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts 2014-05-15 20:33:34.281842890 +0200
+@@ -9,11 +9,13 @@
+
+ /dts-v1/;
+
++/memreserve/ 0xff000000 0x01000000;
++
+ / {
+ model = "V2P-CA15_CA7";
+ arm,hbi = <0x249>;
+ arm,vexpress,site = <0xf>;
+- compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
++ compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress", "arm,generic";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+@@ -29,44 +31,106 @@
+ i2c1 = &v2m_i2c_pcie;
+ };
+
+- cpus {
++ clusters {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- cpu0: cpu@0 {
+- device_type = "cpu";
+- compatible = "arm,cortex-a15";
++ cluster0: cluster@0 {
+ reg = <0>;
++ cores {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ core0: core@0 {
++ reg = <0>;
++ };
++
++ core1: core@1 {
++ reg = <1>;
++ };
++
++ };
+ };
+
+- cpu1: cpu@1 {
+- device_type = "cpu";
+- compatible = "arm,cortex-a15";
++ cluster1: cluster@1 {
+ reg = <1>;
++ cores {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ core2: core@0 {
++ reg = <0>;
++ };
++
++ core3: core@1 {
++ reg = <1>;
++ };
++
++ core4: core@2 {
++ reg = <2>;
++ };
++ };
+ };
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
++ cluster = <&cluster1>;
++ core = <&core2>;
++ clock-frequency = <800000000>;
++ cci-control-port = <&cci_control2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
++ cluster = <&cluster1>;
++ core = <&core3>;
++ clock-frequency = <800000000>;
++ cci-control-port = <&cci_control2>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
++ cluster = <&cluster1>;
++ core = <&core4>;
++ clock-frequency = <800000000>;
++ cci-control-port = <&cci_control2>;
++ };
++
++ cpu0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <0>;
++ cluster = <&cluster0>;
++ core = <&core0>;
++ clock-frequency = <1000000000>;
++ cci-control-port = <&cci_control1>;
++ };
++
++ cpu1: cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ reg = <1>;
++ cluster = <&cluster0>;
++ core = <&core1>;
++ clock-frequency = <1000000000>;
++ cci-control-port = <&cci_control1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+- reg = <0 0x80000000 0 0x40000000>;
++ reg = <0 0x80000000 0 0x80000000>;
+ };
+
+ wdt@2a490000 {
+@@ -81,6 +145,8 @@
+ compatible = "arm,hdlcd";
+ reg = <0 0x2b000000 0 0x1000>;
+ interrupts = <0 85 4>;
++ mode = "1024x768-16@60";
++ framebuffer = <0 0xff000000 0 0x01000000>;
+ clocks = <&oscclk5>;
+ clock-names = "pxlclk";
+ };
+@@ -102,6 +168,64 @@
+ <0 0x2c004000 0 0x2000>,
+ <0 0x2c006000 0 0x2000>;
+ interrupts = <1 9 0xf04>;
++
++ gic-cpuif@0 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <0>;
++ cpu = <&cpu0>;
++ };
++ gic-cpuif@1 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <1>;
++ cpu = <&cpu1>;
++ };
++ gic-cpuif@2 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <2>;
++ cpu = <&cpu2>;
++ };
++
++ gic-cpuif@3 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <3>;
++ cpu = <&cpu3>;
++ };
++
++ gic-cpuif@4 {
++ compatible = "arm,gic-cpuif";
++ cpuif-id = <4>;
++ cpu = <&cpu4>;
++ };
++ };
++
++ cci@2c090000 {
++ compatible = "arm,cci-400";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0 0x2c090000 0 0x1000>;
++ ranges = <0x0 0x0 0x2c090000 0x10000>;
++
++ cci_control1: slave-if@4000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace";
++ reg = <0x4000 0x1000>;
++ };
++
++ cci_control2: slave-if@5000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace";
++ reg = <0x5000 0x1000>;
++ };
++ };
++
++ cci-pmu@2c099000 {
++ compatible = "arm,cci-400-pmu";
++ reg = <0 0x2c099000 0 0x6000>;
++ interrupts = <0 101 4>,
++ <0 102 4>,
++ <0 103 4>,
++ <0 104 4>,
++ <0 105 4>;
+ };
+
+ memory-controller@7ffd0000 {
+@@ -125,6 +249,12 @@
+ clock-names = "apb_pclk";
+ };
+
++ spc@7fff0000 {
++ compatible = "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc";
++ reg = <0 0x7fff0000 0 0x1000>;
++ interrupts = <0 95 4>;
++ };
++
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+@@ -133,12 +263,21 @@
+ <1 10 0xf08>;
+ };
+
+- pmu {
++ pmu_a15 {
+ compatible = "arm,cortex-a15-pmu";
++ cluster = <&cluster0>;
+ interrupts = <0 68 4>,
+ <0 69 4>;
+ };
+
++ pmu_a7 {
++ compatible = "arm,cortex-a7-pmu";
++ cluster = <&cluster1>;
++ interrupts = <0 128 4>,
++ <0 129 4>,
++ <0 130 4>;
++ };
++
+ oscclk6a: oscclk6a {
+ /* Reference 24MHz clock */
+ compatible = "fixed-clock";
+@@ -147,6 +286,15 @@
+ clock-output-names = "oscclk6a";
+ };
+
++ psci {
++ compatible = "arm,psci";
++ method = "smc";
++ cpu_suspend = <0x80100001>;
++ cpu_off = <0x80100002>;
++ cpu_on = <0x80100003>;
++ migrate = <0x80100004>;
++ };
++
+ dcc {
+ compatible = "arm,vexpress,config-bus";
+ arm,vexpress,config-bridge = <&v2m_sysreg>;
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts 2014-05-15 20:33:34.281842890 +0200
+@@ -9,6 +9,8 @@
+
+ /dts-v1/;
+
++/memreserve/ 0xbf000000 0x01000000;
++
+ / {
+ model = "V2P-CA15";
+ arm,hbi = <0x237>;
+@@ -57,6 +59,8 @@
+ interrupts = <0 85 4>;
+ clocks = <&oscclk5>;
+ clock-names = "pxlclk";
++ mode = "1024x768-16@60";
++ framebuffer = <0 0xff000000 0 0x01000000>;
+ };
+
+ memory-controller@2b0a0000 {
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2p-ca5s.dts linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2p-ca5s.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2p-ca5s.dts 2014-05-15 20:33:34.281842890 +0200
+@@ -9,6 +9,8 @@
+
+ /dts-v1/;
+
++/memreserve/ 0xbf000000 0x01000000;
++
+ / {
+ model = "V2P-CA5s";
+ arm,hbi = <0x225>;
+@@ -59,6 +61,8 @@
+ interrupts = <0 85 4>;
+ clocks = <&oscclk3>;
+ clock-names = "pxlclk";
++ mode = "640x480-16@60";
++ framebuffer = <0xbf000000 0x01000000>;
+ };
+
+ memory-controller@2a150000 {
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2p-ca9.dts linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/vexpress-v2p-ca9.dts 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vexpress-v2p-ca9.dts 2014-05-15 20:33:34.281842890 +0200
+@@ -9,6 +9,8 @@
+
+ /dts-v1/;
+
++/include/ "clcd-panels.dtsi"
++
+ / {
+ model = "V2P-CA9";
+ arm,hbi = <0x191>;
+@@ -73,6 +75,8 @@
+ interrupts = <0 44 4>;
+ clocks = <&oscclk1>, <&oscclk2>;
+ clock-names = "clcdclk", "apb_pclk";
++ mode = "XVGA";
++ use_dma = <1>;
+ };
+
+ memory-controller@100e0000 {
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vf610.dtsi linux-linaro-stable-mx6/arch/arm/boot/dts/vf610.dtsi
+--- linux-3.10.30.orig/arch/arm/boot/dts/vf610.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vf610.dtsi 2014-05-15 20:33:34.285842919 +0200
+@@ -0,0 +1,464 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include "skeleton.dtsi"
++#include "vf610-pinfunc.h"
++#include <dt-bindings/clock/vf610-clock.h>
++
++/ {
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
++ serial4 = &uart4;
++ serial5 = &uart5;
++ gpio0 = &gpio1;
++ gpio1 = &gpio2;
++ gpio2 = &gpio3;
++ gpio3 = &gpio4;
++ gpio4 = &gpio5;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ compatible = "arm,cortex-a5";
++ device_type = "cpu";
++ reg = <0x0>;
++ next-level-cache = <&L2>;
++ };
++ };
++
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ sxosc {
++ compatible = "fixed-clock";
++ clock-frequency = <32768>;
++ };
++
++ fxosc {
++ compatible = "fixed-clock";
++ clock-frequency = <24000000>;
++ };
++ };
++
++ soc {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ interrupt-parent = <&intc>;
++ ranges;
++
++ aips0: aips-bus@40000000 {
++ compatible = "fsl,aips-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ interrupt-parent = <&intc>;
++ reg = <0x40000000 0x70000>;
++ ranges;
++
++ intc: interrupt-controller@40002000 {
++ compatible = "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ interrupt-controller;
++ reg = <0x40003000 0x1000>,
++ <0x40002100 0x100>;
++ };
++
++ L2: l2-cache@40006000 {
++ compatible = "arm,pl310-cache";
++ reg = <0x40006000 0x1000>;
++ cache-unified;
++ cache-level = <2>;
++ arm,data-latency = <1 1 1>;
++ arm,tag-latency = <2 2 2>;
++ };
++
++ uart0: serial@40027000 {
++ compatible = "fsl,vf610-lpuart";
++ reg = <0x40027000 0x1000>;
++ interrupts = <0 61 0x00>;
++ clocks = <&clks VF610_CLK_UART0>;
++ clock-names = "ipg";
++ status = "disabled";
++ };
++
++ uart1: serial@40028000 {
++ compatible = "fsl,vf610-lpuart";
++ reg = <0x40028000 0x1000>;
++ interrupts = <0 62 0x04>;
++ clocks = <&clks VF610_CLK_UART1>;
++ clock-names = "ipg";
++ status = "disabled";
++ };
++
++ uart2: serial@40029000 {
++ compatible = "fsl,vf610-lpuart";
++ reg = <0x40029000 0x1000>;
++ interrupts = <0 63 0x04>;
++ clocks = <&clks VF610_CLK_UART2>;
++ clock-names = "ipg";
++ status = "disabled";
++ };
++
++ uart3: serial@4002a000 {
++ compatible = "fsl,vf610-lpuart";
++ reg = <0x4002a000 0x1000>;
++ interrupts = <0 64 0x04>;
++ clocks = <&clks VF610_CLK_UART3>;
++ clock-names = "ipg";
++ status = "disabled";
++ };
++
++ sai2: sai@40031000 {
++ compatible = "fsl,vf610-sai";
++ reg = <0x40031000 0x1000>;
++ interrupts = <0 86 0x04>;
++ clocks = <&clks VF610_CLK_SAI2>;
++ clock-names = "sai";
++ status = "disabled";
++ };
++
++ pit: pit@40037000 {
++ compatible = "fsl,vf610-pit";
++ reg = <0x40037000 0x1000>;
++ interrupts = <0 39 0x04>;
++ clocks = <&clks VF610_CLK_PIT>;
++ clock-names = "pit";
++ };
++
++ wdog@4003e000 {
++ compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
++ reg = <0x4003e000 0x1000>;
++ clocks = <&clks VF610_CLK_WDT>;
++ clock-names = "wdog";
++ };
++
++ qspi0: quadspi@40044000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,vf610-qspi";
++ reg = <0x40044000 0x1000>;
++ interrupts = <0 24 0x04>;
++ clocks = <&clks VF610_CLK_QSPI0_EN>,
++ <&clks VF610_CLK_QSPI0>;
++ clock-names = "qspi_en", "qspi";
++ status = "disabled";
++ };
++
++ iomuxc: iomuxc@40048000 {
++ compatible = "fsl,vf610-iomuxc";
++ reg = <0x40048000 0x1000>;
++ #gpio-range-cells = <2>;
++
++ /* functions and groups pins */
++
++ dcu0 {
++ pinctrl_dcu0_1: dcu0grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTB8__GPIO_30 0x42
++ VF610_PAD_PTE0__DCU0_HSYNC 0x42
++ VF610_PAD_PTE1__DCU0_VSYNC 0x42
++ VF610_PAD_PTE2__DCU0_PCLK 0x42
++ VF610_PAD_PTE4__DCU0_DE 0x42
++ VF610_PAD_PTE5__DCU0_R0 0x42
++ VF610_PAD_PTE6__DCU0_R1 0x42
++ VF610_PAD_PTE7__DCU0_R2 0x42
++ VF610_PAD_PTE8__DCU0_R3 0x42
++ VF610_PAD_PTE9__DCU0_R4 0x42
++ VF610_PAD_PTE10__DCU0_R5 0x42
++ VF610_PAD_PTE11__DCU0_R6 0x42
++ VF610_PAD_PTE12__DCU0_R7 0x42
++ VF610_PAD_PTE13__DCU0_G0 0x42
++ VF610_PAD_PTE14__DCU0_G1 0x42
++ VF610_PAD_PTE15__DCU0_G2 0x42
++ VF610_PAD_PTE16__DCU0_G3 0x42
++ VF610_PAD_PTE17__DCU0_G4 0x42
++ VF610_PAD_PTE18__DCU0_G5 0x42
++ VF610_PAD_PTE19__DCU0_G6 0x42
++ VF610_PAD_PTE20__DCU0_G7 0x42
++ VF610_PAD_PTE21__DCU0_B0 0x42
++ VF610_PAD_PTE22__DCU0_B1 0x42
++ VF610_PAD_PTE23__DCU0_B2 0x42
++ VF610_PAD_PTE24__DCU0_B3 0x42
++ VF610_PAD_PTE25__DCU0_B4 0x42
++ VF610_PAD_PTE26__DCU0_B5 0x42
++ VF610_PAD_PTE27__DCU0_B6 0x42
++ VF610_PAD_PTE28__DCU0_B7 0x42
++ >;
++ };
++ };
++
++ dspi0 {
++ pinctrl_dspi0_1: dspi0grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTB19__DSPI0_CS0 0x1182
++ VF610_PAD_PTB20__DSPI0_SIN 0x1181
++ VF610_PAD_PTB21__DSPI0_SOUT 0x1182
++ VF610_PAD_PTB22__DSPI0_SCK 0x1182
++ >;
++ };
++ };
++
++ esdhc1 {
++ pinctrl_esdhc1_1: esdhc1grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
++ VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
++ VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
++ VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
++ VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
++ VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
++ VF610_PAD_PTA7__GPIO_134 0x219d
++ >;
++ };
++ };
++
++ fec0 {
++ pinctrl_fec0_1: fec0grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTA6__RMII_CLKIN 0x30d1
++ VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
++ VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
++ VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
++ VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
++ VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
++ VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
++ VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
++ VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
++ VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
++ >;
++ };
++ };
++
++ fec1 {
++ pinctrl_fec1_1: fec1grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
++ VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
++ VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
++ VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
++ VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
++ VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
++ VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
++ VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
++ VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
++ >;
++ };
++ };
++
++ i2c0 {
++ pinctrl_i2c0_1: i2c0grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTB14__I2C0_SCL 0x30d3
++ VF610_PAD_PTB15__I2C0_SDA 0x30d3
++ >;
++ };
++ };
++
++ pwm0 {
++ pinctrl_pwm0_1: pwm0grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTB0__FTM0_CH0 0x1582
++ VF610_PAD_PTB1__FTM0_CH1 0x1582
++ VF610_PAD_PTB2__FTM0_CH2 0x1582
++ VF610_PAD_PTB3__FTM0_CH3 0x1582
++ VF610_PAD_PTB6__FTM0_CH6 0x1582
++ VF610_PAD_PTB7__FTM0_CH7 0x1582
++ >;
++ };
++ };
++
++ qspi0 {
++ pinctrl_qspi0_1: qspi0grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b
++ VF610_PAD_PTD1__QSPI0_A_CS0 0x307f
++ VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073
++ VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073
++ VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073
++ VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b
++ VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b
++ VF610_PAD_PTD8__QSPI0_B_CS0 0x307f
++ VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073
++ VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073
++ VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073
++ VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b
++ >;
++ };
++ };
++
++ sai2 {
++ pinctrl_sai2_1: sai2grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
++ VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
++ VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
++ VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
++ VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
++ VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
++ VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
++ >;
++ };
++ };
++
++ uart1 {
++ pinctrl_uart1_1: uart1grp_1 {
++ fsl,pins = <
++ VF610_PAD_PTB4__UART1_TX 0x21a2
++ VF610_PAD_PTB5__UART1_RX 0x21a1
++ >;
++ };
++ };
++
++ usbvbus {
++ pinctrl_usbvbus_1: usbvbusgrp_1 {
++ fsl,pins = <
++ VF610_PAD_PTA24__USB1_VBUS_EN 0x219c
++ VF610_PAD_PTA16__USB0_VBUS_EN 0x219c
++ >;
++ };
++ };
++
++ };
++
++ gpio1: gpio@40049000 {
++ compatible = "fsl,vf610-gpio";
++ reg = <0x40049000 0x1000 0x400ff000 0x40>;
++ interrupts = <0 107 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ gpio-ranges = <&iomuxc 0 32>;
++ };
++
++ gpio2: gpio@4004a000 {
++ compatible = "fsl,vf610-gpio";
++ reg = <0x4004a000 0x1000 0x400ff040 0x40>;
++ interrupts = <0 108 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ gpio-ranges = <&iomuxc 32 32>;
++ };
++
++ gpio3: gpio@4004b000 {
++ compatible = "fsl,vf610-gpio";
++ reg = <0x4004b000 0x1000 0x400ff080 0x40>;
++ interrupts = <0 109 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ gpio-ranges = <&iomuxc 64 32>;
++ };
++
++ gpio4: gpio@4004c000 {
++ compatible = "fsl,vf610-gpio";
++ reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
++ interrupts = <0 110 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ gpio-ranges = <&iomuxc 96 32>;
++ };
++
++ gpio5: gpio@4004d000 {
++ compatible = "fsl,vf610-gpio";
++ reg = <0x4004d000 0x1000 0x400ff100 0x40>;
++ interrupts = <0 111 0x04>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ gpio-ranges = <&iomuxc 128 7>;
++ };
++
++ anatop@40050000 {
++ compatible = "fsl,vf610-anatop";
++ reg = <0x40050000 0x1000>;
++ };
++
++ i2c0: i2c@40066000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,vf610-i2c";
++ reg = <0x40066000 0x1000>;
++ interrupts =<0 71 0x04>;
++ clocks = <&clks VF610_CLK_I2C0>;
++ clock-names = "ipg";
++ status = "disabled";
++ };
++
++ clks: ccm@4006b000 {
++ compatible = "fsl,vf610-ccm";
++ reg = <0x4006b000 0x1000>;
++ #clock-cells = <1>;
++ };
++ };
++
++ aips1: aips-bus@40080000 {
++ compatible = "fsl,aips-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x40080000 0x80000>;
++ ranges;
++
++ uart4: serial@400a9000 {
++ compatible = "fsl,vf610-lpuart";
++ reg = <0x400a9000 0x1000>;
++ interrupts = <0 65 0x04>;
++ clocks = <&clks VF610_CLK_UART4>;
++ clock-names = "ipg";
++ status = "disabled";
++ };
++
++ uart5: serial@400aa000 {
++ compatible = "fsl,vf610-lpuart";
++ reg = <0x400aa000 0x1000>;
++ interrupts = <0 66 0x04>;
++ clocks = <&clks VF610_CLK_UART5>;
++ clock-names = "ipg";
++ status = "disabled";
++ };
++
++ fec0: ethernet@400d0000 {
++ compatible = "fsl,mvf600-fec";
++ reg = <0x400d0000 0x1000>;
++ interrupts = <0 78 0x04>;
++ clocks = <&clks VF610_CLK_ENET0>,
++ <&clks VF610_CLK_ENET0>,
++ <&clks VF610_CLK_ENET>;
++ clock-names = "ipg", "ahb", "ptp";
++ status = "disabled";
++ };
++
++ fec1: ethernet@400d1000 {
++ compatible = "fsl,mvf600-fec";
++ reg = <0x400d1000 0x1000>;
++ interrupts = <0 79 0x04>;
++ clocks = <&clks VF610_CLK_ENET1>,
++ <&clks VF610_CLK_ENET1>,
++ <&clks VF610_CLK_ENET>;
++ clock-names = "ipg", "ahb", "ptp";
++ status = "disabled";
++ };
++ };
++ };
++};
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vf610-pinfunc.h linux-linaro-stable-mx6/arch/arm/boot/dts/vf610-pinfunc.h
+--- linux-3.10.30.orig/arch/arm/boot/dts/vf610-pinfunc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vf610-pinfunc.h 2014-05-15 20:33:34.285842919 +0200
+@@ -0,0 +1,810 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DTS_VF610_PINFUNC_H
++#define __DTS_VF610_PINFUNC_H
++
++/*
++ * The pin function ID for VF610 is a tuple of:
++ * <mux_reg input_reg mux_mode input_val>
++ */
++
++#define ALT0 0x0
++#define ALT1 0x1
++#define ALT2 0x2
++#define ALT3 0x3
++#define ALT4 0x4
++#define ALT5 0x5
++#define ALT6 0x6
++#define ALT7 0x7
++
++
++#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
++#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
++#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0
++#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0
++#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0
++#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0
++#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0
++#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0
++#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0
++#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0
++#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0
++#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0
++#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1
++#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0
++#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0
++#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0
++#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0
++#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0
++#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0
++#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0
++#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0
++#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0
++#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0
++#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0
++#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0
++#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0
++#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0
++#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1
++#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0
++#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0
++#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0
++#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0
++#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0
++#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0
++#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0
++#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0
++#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0
++#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0
++#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0
++#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0
++#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0
++#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0
++#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0
++#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0
++#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0
++#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0
++#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0
++#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0
++#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0
++#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0
++#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0
++#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0
++#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0
++#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0
++#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0
++#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0
++#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0
++#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0
++#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0
++#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0
++#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0
++#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0
++#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0
++#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0
++#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0
++#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0
++#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0
++#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0
++#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0
++#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0
++#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0
++#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0
++#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0
++#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0
++#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0
++#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0
++#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0
++#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0
++#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0
++#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0
++#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0
++#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0
++#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0
++#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0
++#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0
++#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0
++#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0
++#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0
++#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0
++#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0
++#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0
++#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0
++#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0
++#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0
++#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0
++#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0
++#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0
++#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0
++#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0
++#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0
++#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0
++#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0
++#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0
++#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0
++#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0
++#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0
++#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0
++#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0
++#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0
++#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0
++#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0
++#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0
++#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0
++#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0
++#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0
++#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0
++#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0
++#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0
++#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0
++#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0
++#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0
++#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0
++#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0
++#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1
++#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0
++#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0
++#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0
++#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0
++#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0
++#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0
++#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1
++#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0
++#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0
++#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0
++#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0
++#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0
++#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1
++#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0
++#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0
++#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0
++#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0
++#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0
++#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0
++#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0
++#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1
++#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0
++#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0
++#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0
++#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0
++#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0
++#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0
++#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0
++#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1
++#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0
++#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0
++#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0
++#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0
++#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0
++#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0
++#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0
++#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0
++#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0
++#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0
++#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0
++#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0
++#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0
++#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0
++#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0
++#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0
++#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0
++#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0
++#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0
++#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0
++#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0
++#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0
++#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0
++#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0
++#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0
++#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0
++#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0
++#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0
++#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0
++#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0
++#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0
++#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0
++#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0
++#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0
++#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0
++#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0
++#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0
++#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0
++#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0
++#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0
++#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0
++#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1
++#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1
++#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0
++#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0
++#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0
++#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1
++#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0
++#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0
++#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0
++#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0
++#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2
++#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0
++#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1
++#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0
++#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0
++#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0
++#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0
++#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0
++#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0
++#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0
++#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0
++#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0
++#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0
++#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0
++#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0
++#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0
++#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0
++#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0
++#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0
++#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0
++#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0
++#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0
++#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0
++#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0
++#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1
++#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0
++#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0
++#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0
++#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0
++#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1
++#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0
++#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0
++#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0
++#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0
++#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1
++#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0
++#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0
++#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0
++#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1
++#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0
++#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0
++#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0
++#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2
++#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0
++#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0
++#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0
++#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0
++#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0
++#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0
++#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0
++#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0
++#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0
++#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0
++#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0
++#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0
++#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0
++#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0
++#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0
++#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0
++#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1
++#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0
++#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0
++#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1
++#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0
++#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0
++#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0
++#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0
++#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0
++#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0
++#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0
++#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1
++#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0
++#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0
++#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0
++#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0
++#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0
++#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0
++#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0
++#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1
++#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0
++#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0
++#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0
++#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0
++#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0
++#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0
++#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1
++#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0
++#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0
++#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0
++#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0
++#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0
++#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0
++#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0
++#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0
++#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0
++#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0
++#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0
++#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0
++#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0
++#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0
++#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1
++#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0
++#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0
++#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0
++#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0
++#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0
++#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0
++#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0
++#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0
++#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0
++#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0
++#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0
++#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0
++#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0
++#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0
++#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0
++#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0
++#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0
++#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0
++#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0
++#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0
++#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0
++#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0
++#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0
++#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0
++#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0
++#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1
++#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1
++#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0
++#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0
++#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0
++#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1
++#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1
++#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0
++#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0
++#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0
++#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1
++#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1
++#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0
++#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0
++#define VF610_PAD_PTC12__ENET_RMII_RXD1 0x0E4 0x000 ALT1 0x0
++#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1
++#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1
++#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0
++#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0
++#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0
++#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1
++#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2
++#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0
++#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0
++#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0
++#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1
++#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0
++#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2
++#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0
++#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0
++#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0
++#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0
++#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1
++#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0
++#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0
++#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0
++#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0
++#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0
++#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0
++#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1
++#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0
++#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2
++#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0
++#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0
++#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0
++#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0
++#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0
++#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0
++#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1
++#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0
++#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0
++#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0
++#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0
++#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0
++#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0
++#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0
++#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0
++#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0
++#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0
++#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0
++#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0
++#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0
++#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0
++#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0
++#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0
++#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0
++#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
++#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
++#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
++#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
++#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
++#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
++#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
++#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0
++#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0
++#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0
++#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0
++#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0
++#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0
++#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1
++#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0
++#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0
++#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0
++#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0
++#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0
++#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0
++#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0
++#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0
++#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0
++#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0
++#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0
++#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0
++#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0
++#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0
++#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0
++#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0
++#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0
++#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0
++#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0
++#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0
++#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0
++#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0
++#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0
++#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1
++#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0
++#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1
++#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0
++#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0
++#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0
++#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0
++#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0
++#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1
++#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0
++#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1
++#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0
++#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0
++#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0
++#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0
++#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0
++#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0
++#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0
++#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0
++#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0
++#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0
++#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0
++#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0
++#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0
++#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0
++#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0
++#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0
++#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0
++#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0
++#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0
++#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2
++#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0
++#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0
++#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0
++#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0
++#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0
++#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0
++#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2
++#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0
++#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0
++#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0
++#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0
++#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0
++#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0
++#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2
++#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0
++#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0
++#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0
++#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0
++#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0
++#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2
++#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0
++#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0
++#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0
++#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2
++#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0
++#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0
++#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0
++#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0
++#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0
++#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2
++#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0
++#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0
++#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0
++#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0
++#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0
++#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0
++#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0
++#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0
++#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0
++#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0
++#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0
++#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0
++#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1
++#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0
++#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0
++#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0
++#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0
++#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0
++#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0
++#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0
++#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0
++#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0
++#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0
++#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0
++#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0
++#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1
++#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0
++#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0
++#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0
++#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0
++#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1
++#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0
++#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0
++#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0
++#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0
++#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0
++#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0
++#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0
++#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0
++#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0
++#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0
++#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1
++#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0
++#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0
++#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0
++#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0
++#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0
++#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0
++#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0
++#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0
++#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0
++#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0
++#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0
++#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0
++#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0
++#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0
++#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0
++#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0
++#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0
++#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0
++#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0
++#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0
++#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0
++#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0
++#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0
++#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0
++#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0
++#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0
++#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0
++#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0
++#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0
++#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0
++#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2
++#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1
++#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0
++#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0
++#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0
++#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0
++#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0
++#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0
++#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2
++#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1
++#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0
++#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0
++#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0
++#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0
++#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0
++#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0
++#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0
++#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1
++#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0
++#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0
++#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0
++#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0
++#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0
++#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2
++#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0
++#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0
++#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0
++#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0
++#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0
++#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0
++#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0
++#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0
++#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0
++#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0
++#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0
++#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0
++#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0
++#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0
++#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0
++#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0
++#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0
++#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0
++#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0
++#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0
++#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0
++#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0
++#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0
++#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0
++#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0
++#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0
++#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0
++#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0
++#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0
++#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0
++#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0
++#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0
++#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0
++#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0
++#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0
++#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0
++#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0
++#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0
++#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0
++#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0
++#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0
++#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0
++#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0
++#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0
++#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0
++#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0
++#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0
++#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0
++#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0
++#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0
++#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0
++#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0
++#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0
++#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0
++#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0
++#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1
++#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0
++#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0
++#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0
++#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0
++#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0
++#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0
++#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0
++#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0
++#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0
++#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0
++#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0
++#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0
++#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0
++#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0
++#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0
++#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0
++#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0
++#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0
++#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0
++#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0
++#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0
++#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0
++#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0
++#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0
++#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0
++#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0
++#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0
++#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0
++#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0
++#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0
++#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0
++#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0
++#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0
++#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0
++#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0
++#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0
++#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0
++#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0
++#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0
++#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0
++#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0
++#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0
++#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0
++#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0
++#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0
++#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0
++#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0
++#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0
++#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0
++#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0
++#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0
++#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0
++#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0
++#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0
++#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0
++#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0
++#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0
++#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0
++#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0
++#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0
++#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0
++#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0
++#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0
++#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0
++#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0
++#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0
++#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0
++#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0
++#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0
++#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0
++#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0
++#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0
++#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0
++#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0
++#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0
++#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0
++#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0
++#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0
++#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0
++#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0
++#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0
++#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0
++#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0
++#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0
++#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0
++#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0
++#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0
++#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0
++#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0
++#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0
++#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0
++#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0
++#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0
++#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3
++#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0
++#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0
++#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0
++#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0
++#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3
++#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0
++#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0
++#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0
++#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0
++#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0
++#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0
++#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0
++#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0
++#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0
++#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0
++#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0
++#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0
++#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0
++#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0
++#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0
++#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0
++#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0
++#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0
++#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0
++#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0
++#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0
++#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0
++#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0
++#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0
++#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0
++#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0
++#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0
++#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3
++#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0
++#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0
++#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0
++#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0
++#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3
++#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0
++#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0
++#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
++
++#endif
+diff -Nur linux-3.10.30.orig/arch/arm/boot/dts/vf610-twr.dts linux-linaro-stable-mx6/arch/arm/boot/dts/vf610-twr.dts
+--- linux-3.10.30.orig/arch/arm/boot/dts/vf610-twr.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/boot/dts/vf610-twr.dts 2014-05-15 20:33:34.285842919 +0200
+@@ -0,0 +1,57 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++/dts-v1/;
++#include "vf610.dtsi"
++
++/ {
++ model = "VF610 Tower Board";
++ compatible = "fsl,vf610-twr", "fsl,vf610";
++
++ chosen {
++ bootargs = "console=ttyLP1,115200";
++ };
++
++ memory {
++ reg = <0x80000000 0x8000000>;
++ };
++
++ clocks {
++ audio_ext {
++ compatible = "fixed-clock";
++ clock-frequency = <24576000>;
++ };
++
++ enet_ext {
++ compatible = "fixed-clock";
++ clock-frequency = <50000000>;
++ };
++ };
++
++};
++
++&fec0 {
++ phy-mode = "rmii";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_fec0_1>;
++ status = "okay";
++};
++
++&fec1 {
++ phy-mode = "rmii";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_fec1_1>;
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1_1>;
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/arch/arm/common/bL_switcher.c linux-linaro-stable-mx6/arch/arm/common/bL_switcher.c
+--- linux-3.10.30.orig/arch/arm/common/bL_switcher.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/common/bL_switcher.c 2014-05-15 20:33:34.301843035 +0200
+@@ -0,0 +1,864 @@
++/*
++ * arch/arm/common/bL_switcher.c -- big.LITTLE cluster switcher core driver
++ *
++ * Created by: Nicolas Pitre, March 2012
++ * Copyright: (C) 2012 Linaro Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/atomic.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/sched.h>
++#include <linux/interrupt.h>
++#include <linux/cpu_pm.h>
++#include <linux/cpu.h>
++#include <linux/cpumask.h>
++#include <linux/kthread.h>
++#include <linux/wait.h>
++#include <linux/time.h>
++#include <linux/clockchips.h>
++#include <linux/hrtimer.h>
++#include <linux/tick.h>
++#include <linux/notifier.h>
++#include <linux/mm.h>
++#include <linux/mutex.h>
++#include <linux/smp.h>
++#include <linux/spinlock.h>
++#include <linux/string.h>
++#include <linux/sysfs.h>
++#include <linux/irqchip/arm-gic.h>
++#include <linux/moduleparam.h>
++
++#include <asm/smp_plat.h>
++#include <asm/cacheflush.h>
++#include <asm/cputype.h>
++#include <asm/suspend.h>
++#include <asm/mcpm.h>
++#include <asm/bL_switcher.h>
++
++#define CREATE_TRACE_POINTS
++#include <trace/events/power_cpu_migrate.h>
++
++
++/*
++ * Use our own MPIDR accessors as the generic ones in asm/cputype.h have
++ * __attribute_const__ and we don't want the compiler to assume any
++ * constness here as the value _does_ change along some code paths.
++ */
++
++static int read_mpidr(void)
++{
++ unsigned int id;
++ asm volatile ("mrc\tp15, 0, %0, c0, c0, 5" : "=r" (id));
++ return id & MPIDR_HWID_BITMASK;
++}
++
++/*
++ * Get a global nanosecond time stamp for tracing.
++ */
++static s64 get_ns(void)
++{
++ struct timespec ts;
++ getnstimeofday(&ts);
++ return timespec_to_ns(&ts);
++}
++
++/*
++ * bL switcher core code.
++ */
++
++static void bL_do_switch(void *_arg)
++{
++ unsigned ib_mpidr, ib_cpu, ib_cluster;
++ long volatile handshake, **handshake_ptr = _arg;
++
++ pr_debug("%s\n", __func__);
++
++ ib_mpidr = cpu_logical_map(smp_processor_id());
++ ib_cpu = MPIDR_AFFINITY_LEVEL(ib_mpidr, 0);
++ ib_cluster = MPIDR_AFFINITY_LEVEL(ib_mpidr, 1);
++
++ /* Advertise our handshake location */
++ if (handshake_ptr) {
++ handshake = 0;
++ *handshake_ptr = &handshake;
++ } else
++ handshake = -1;
++
++ /*
++ * Our state has been saved at this point. Let's release our
++ * inbound CPU.
++ */
++ mcpm_set_entry_vector(ib_cpu, ib_cluster, cpu_resume);
++ sev();
++
++ /*
++ * From this point, we must assume that our counterpart CPU might
++ * have taken over in its parallel world already, as if execution
++ * just returned from cpu_suspend(). It is therefore important to
++ * be very careful not to make any change the other guy is not
++ * expecting. This is why we need stack isolation.
++ *
++ * Fancy under cover tasks could be performed here. For now
++ * we have none.
++ */
++
++ /*
++ * Let's wait until our inbound is alive.
++ */
++ while (!handshake) {
++ wfe();
++ smp_mb();
++ }
++
++ /* Let's put ourself down. */
++ mcpm_cpu_power_down();
++
++ /* should never get here */
++ BUG();
++}
++
++/*
++ * Stack isolation. To ensure 'current' remains valid, we just use another
++ * piece of our thread's stack space which should be fairly lightly used.
++ * The selected area starts just above the thread_info structure located
++ * at the very bottom of the stack, aligned to a cache line, and indexed
++ * with the cluster number.
++ */
++#define STACK_SIZE 512
++extern void call_with_stack(void (*fn)(void *), void *arg, void *sp);
++static int bL_switchpoint(unsigned long _arg)
++{
++ unsigned int mpidr = read_mpidr();
++ unsigned int clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++ void *stack = current_thread_info() + 1;
++ stack = PTR_ALIGN(stack, L1_CACHE_BYTES);
++ stack += clusterid * STACK_SIZE + STACK_SIZE;
++ call_with_stack(bL_do_switch, (void *)_arg, stack);
++ BUG();
++}
++
++/*
++ * Generic switcher interface
++ */
++
++static unsigned int bL_gic_id[MAX_CPUS_PER_CLUSTER][MAX_NR_CLUSTERS];
++static int bL_switcher_cpu_pairing[NR_CPUS];
++
++/*
++ * bL_switch_to - Switch to a specific cluster for the current CPU
++ * @new_cluster_id: the ID of the cluster to switch to.
++ *
++ * This function must be called on the CPU to be switched.
++ * Returns 0 on success, else a negative status code.
++ */
++static int bL_switch_to(unsigned int new_cluster_id)
++{
++ unsigned int mpidr, this_cpu, that_cpu;
++ unsigned int ob_mpidr, ob_cpu, ob_cluster, ib_mpidr, ib_cpu, ib_cluster;
++ struct completion inbound_alive;
++ struct tick_device *tdev;
++ enum clock_event_mode tdev_mode;
++ long volatile *handshake_ptr;
++ int ipi_nr, ret;
++
++ this_cpu = smp_processor_id();
++ ob_mpidr = read_mpidr();
++ ob_cpu = MPIDR_AFFINITY_LEVEL(ob_mpidr, 0);
++ ob_cluster = MPIDR_AFFINITY_LEVEL(ob_mpidr, 1);
++ BUG_ON(cpu_logical_map(this_cpu) != ob_mpidr);
++
++ if (new_cluster_id == ob_cluster)
++ return 0;
++
++ that_cpu = bL_switcher_cpu_pairing[this_cpu];
++ ib_mpidr = cpu_logical_map(that_cpu);
++ ib_cpu = MPIDR_AFFINITY_LEVEL(ib_mpidr, 0);
++ ib_cluster = MPIDR_AFFINITY_LEVEL(ib_mpidr, 1);
++
++ pr_debug("before switch: CPU %d MPIDR %#x -> %#x\n",
++ this_cpu, ob_mpidr, ib_mpidr);
++
++ this_cpu = smp_processor_id();
++
++ /* Close the gate for our entry vectors */
++ mcpm_set_entry_vector(ob_cpu, ob_cluster, NULL);
++ mcpm_set_entry_vector(ib_cpu, ib_cluster, NULL);
++
++ /* Install our "inbound alive" notifier. */
++ init_completion(&inbound_alive);
++ ipi_nr = register_ipi_completion(&inbound_alive, this_cpu);
++ ipi_nr |= ((1 << 16) << bL_gic_id[ob_cpu][ob_cluster]);
++ mcpm_set_early_poke(ib_cpu, ib_cluster, gic_get_sgir_physaddr(), ipi_nr);
++
++ /*
++ * Let's wake up the inbound CPU now in case it requires some delay
++ * to come online, but leave it gated in our entry vector code.
++ */
++ ret = mcpm_cpu_power_up(ib_cpu, ib_cluster);
++ if (ret) {
++ pr_err("%s: mcpm_cpu_power_up() returned %d\n", __func__, ret);
++ return ret;
++ }
++
++ /*
++ * Raise a SGI on the inbound CPU to make sure it doesn't stall
++ * in a possible WFI, such as in bL_power_down().
++ */
++ gic_send_sgi(bL_gic_id[ib_cpu][ib_cluster], 0);
++
++ /*
++ * Wait for the inbound to come up. This allows for other
++ * tasks to be scheduled in the mean time.
++ */
++ wait_for_completion(&inbound_alive);
++ mcpm_set_early_poke(ib_cpu, ib_cluster, 0, 0);
++
++ /*
++ * From this point we are entering the switch critical zone
++ * and can't sleep/schedule anymore.
++ */
++ local_irq_disable();
++ local_fiq_disable();
++ trace_cpu_migrate_begin(get_ns(), ob_mpidr);
++
++ /* redirect GIC's SGIs to our counterpart */
++ gic_migrate_target(bL_gic_id[ib_cpu][ib_cluster]);
++
++ tdev = tick_get_device(this_cpu);
++ if (tdev && !cpumask_equal(tdev->evtdev->cpumask, cpumask_of(this_cpu)))
++ tdev = NULL;
++ if (tdev) {
++ tdev_mode = tdev->evtdev->mode;
++ clockevents_set_mode(tdev->evtdev, CLOCK_EVT_MODE_SHUTDOWN);
++ }
++
++ ret = cpu_pm_enter();
++
++ /* we can not tolerate errors at this point */
++ if (ret)
++ panic("%s: cpu_pm_enter() returned %d\n", __func__, ret);
++
++ /*
++ * Swap the physical CPUs in the logical map for this logical CPU.
++ * This must be flushed to RAM as the resume code
++ * needs to access it while the caches are still disabled.
++ */
++ cpu_logical_map(this_cpu) = ib_mpidr;
++ cpu_logical_map(that_cpu) = ob_mpidr;
++ sync_cache_w(&cpu_logical_map(this_cpu));
++
++ /* Let's do the actual CPU switch. */
++ ret = cpu_suspend((unsigned long)&handshake_ptr, bL_switchpoint);
++ if (ret > 0)
++ panic("%s: cpu_suspend() returned %d\n", __func__, ret);
++
++ /* We are executing on the inbound CPU at this point */
++ mpidr = read_mpidr();
++ pr_debug("after switch: CPU %d MPIDR %#x\n", this_cpu, mpidr);
++ BUG_ON(mpidr != ib_mpidr);
++
++ mcpm_cpu_powered_up();
++
++ ret = cpu_pm_exit();
++
++ if (tdev) {
++ clockevents_set_mode(tdev->evtdev, tdev_mode);
++ clockevents_program_event(tdev->evtdev,
++ tdev->evtdev->next_event, 1);
++ }
++
++ trace_cpu_migrate_finish(get_ns(), ib_mpidr);
++ local_fiq_enable();
++ local_irq_enable();
++
++ *handshake_ptr = 1;
++ dsb_sev();
++
++ if (ret)
++ pr_err("%s exiting with error %d\n", __func__, ret);
++ return ret;
++}
++
++struct bL_thread {
++ spinlock_t lock;
++ struct task_struct *task;
++ wait_queue_head_t wq;
++ int wanted_cluster;
++ struct completion started;
++ bL_switch_completion_handler completer;
++ void *completer_cookie;
++};
++
++static struct bL_thread bL_threads[NR_CPUS];
++
++static int bL_switcher_thread(void *arg)
++{
++ struct bL_thread *t = arg;
++ struct sched_param param = { .sched_priority = 1 };
++ int cluster;
++ bL_switch_completion_handler completer;
++ void *completer_cookie;
++
++ sched_setscheduler_nocheck(current, SCHED_FIFO, &param);
++ complete(&t->started);
++
++ do {
++ if (signal_pending(current))
++ flush_signals(current);
++ wait_event_interruptible(t->wq,
++ t->wanted_cluster != -1 ||
++ kthread_should_stop());
++
++ spin_lock(&t->lock);
++ cluster = t->wanted_cluster;
++ completer = t->completer;
++ completer_cookie = t->completer_cookie;
++ t->wanted_cluster = -1;
++ t->completer = NULL;
++ spin_unlock(&t->lock);
++
++ if (cluster != -1) {
++ bL_switch_to(cluster);
++
++ if (completer)
++ completer(completer_cookie);
++ }
++ } while (!kthread_should_stop());
++
++ return 0;
++}
++
++static struct task_struct * bL_switcher_thread_create(int cpu, void *arg)
++{
++ struct task_struct *task;
++
++ task = kthread_create_on_node(bL_switcher_thread, arg,
++ cpu_to_node(cpu), "kswitcher_%d", cpu);
++ if (!IS_ERR(task)) {
++ kthread_bind(task, cpu);
++ wake_up_process(task);
++ } else
++ pr_err("%s failed for CPU %d\n", __func__, cpu);
++ return task;
++}
++
++/*
++ * bL_switch_request_cb - Switch to a specific cluster for the given CPU,
++ * with completion notification via a callback
++ *
++ * @cpu: the CPU to switch
++ * @new_cluster_id: the ID of the cluster to switch to.
++ * @completer: switch completion callback. if non-NULL,
++ * @completer(@completer_cookie) will be called on completion of
++ * the switch, in non-atomic context.
++ * @completer_cookie: opaque context argument for @completer.
++ *
++ * This function causes a cluster switch on the given CPU by waking up
++ * the appropriate switcher thread. This function may or may not return
++ * before the switch has occurred.
++ *
++ * If a @completer callback function is supplied, it will be called when
++ * the switch is complete. This can be used to determine asynchronously
++ * when the switch is complete, regardless of when bL_switch_request()
++ * returns. When @completer is supplied, no new switch request is permitted
++ * for the affected CPU until after the switch is complete, and @completer
++ * has returned.
++ */
++int bL_switch_request_cb(unsigned int cpu, unsigned int new_cluster_id,
++ bL_switch_completion_handler completer,
++ void *completer_cookie)
++{
++ struct bL_thread *t;
++
++ if (cpu >= ARRAY_SIZE(bL_threads)) {
++ pr_err("%s: cpu %d out of bounds\n", __func__, cpu);
++ return -EINVAL;
++ }
++
++ t = &bL_threads[cpu];
++
++ if (IS_ERR(t->task))
++ return PTR_ERR(t->task);
++ if (!t->task)
++ return -ESRCH;
++
++ spin_lock(&t->lock);
++ if (t->completer) {
++ spin_unlock(&t->lock);
++ return -EBUSY;
++ }
++ t->completer = completer;
++ t->completer_cookie = completer_cookie;
++ t->wanted_cluster = new_cluster_id;
++ spin_unlock(&t->lock);
++ wake_up(&t->wq);
++ return 0;
++}
++
++EXPORT_SYMBOL_GPL(bL_switch_request_cb);
++
++/*
++ * Detach an outstanding switch request.
++ *
++ * The switcher will continue with the switch request in the background,
++ * but the completer function will not be called.
++ *
++ * This may be necessary if the completer is in a kernel module which is
++ * about to be unloaded.
++ */
++void bL_switch_request_detach(unsigned int cpu,
++ bL_switch_completion_handler completer)
++{
++ struct bL_thread *t;
++
++ if (cpu >= ARRAY_SIZE(bL_threads)) {
++ pr_err("%s: cpu %d out of bounds\n", __func__, cpu);
++ return;
++ }
++
++ t = &bL_threads[cpu];
++
++ if (IS_ERR(t->task) || !t->task)
++ return;
++
++ spin_lock(&t->lock);
++ if (t->completer == completer)
++ t->completer = NULL;
++ spin_unlock(&t->lock);
++}
++
++EXPORT_SYMBOL_GPL(bL_switch_request_detach);
++
++/*
++ * Activation and configuration code.
++ */
++
++static DEFINE_MUTEX(bL_switcher_activation_lock);
++static BLOCKING_NOTIFIER_HEAD(bL_activation_notifier);
++static unsigned int bL_switcher_active;
++static unsigned int bL_switcher_cpu_original_cluster[NR_CPUS];
++static cpumask_t bL_switcher_removed_logical_cpus;
++
++int bL_switcher_register_notifier(struct notifier_block *nb)
++{
++ return blocking_notifier_chain_register(&bL_activation_notifier, nb);
++}
++EXPORT_SYMBOL_GPL(bL_switcher_register_notifier);
++
++int bL_switcher_unregister_notifier(struct notifier_block *nb)
++{
++ return blocking_notifier_chain_unregister(&bL_activation_notifier, nb);
++}
++EXPORT_SYMBOL_GPL(bL_switcher_unregister_notifier);
++
++static int bL_activation_notify(unsigned long val)
++{
++ int ret;
++
++ ret = blocking_notifier_call_chain(&bL_activation_notifier, val, NULL);
++ if (ret & NOTIFY_STOP_MASK)
++ pr_err("%s: notifier chain failed with status 0x%x\n",
++ __func__, ret);
++ return notifier_to_errno(ret);
++}
++
++static void bL_switcher_restore_cpus(void)
++{
++ int i;
++
++ for_each_cpu(i, &bL_switcher_removed_logical_cpus)
++ cpu_up(i);
++}
++
++static int bL_switcher_halve_cpus(void)
++{
++ int i, j, cluster_0, gic_id, ret;
++ unsigned int cpu, cluster, mask;
++ cpumask_t available_cpus;
++
++ /* First pass to validate what we have */
++ mask = 0;
++ for_each_online_cpu(i) {
++ cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0);
++ cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 1);
++ if (cluster >= 2) {
++ pr_err("%s: only dual cluster systems are supported\n", __func__);
++ return -EINVAL;
++ }
++ if (WARN_ON(cpu >= MAX_CPUS_PER_CLUSTER))
++ return -EINVAL;
++ mask |= (1 << cluster);
++ }
++ if (mask != 3) {
++ pr_err("%s: no CPU pairing possible\n", __func__);
++ return -EINVAL;
++ }
++
++ /*
++ * Now let's do the pairing. We match each CPU with another CPU
++ * from a different cluster. To get a uniform scheduling behavior
++ * without fiddling with CPU topology and compute capacity data,
++ * we'll use logical CPUs initially belonging to the same cluster.
++ */
++ memset(bL_switcher_cpu_pairing, -1, sizeof(bL_switcher_cpu_pairing));
++ cpumask_copy(&available_cpus, cpu_online_mask);
++ cluster_0 = -1;
++ for_each_cpu(i, &available_cpus) {
++ int match = -1;
++ cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 1);
++ if (cluster_0 == -1)
++ cluster_0 = cluster;
++ if (cluster != cluster_0)
++ continue;
++ cpumask_clear_cpu(i, &available_cpus);
++ for_each_cpu(j, &available_cpus) {
++ cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(j), 1);
++ /*
++ * Let's remember the last match to create "odd"
++ * pairing on purpose in order for other code not
++ * to assume any relation between physical and
++ * logical CPU numbers.
++ */
++ if (cluster != cluster_0)
++ match = j;
++ }
++ if (match != -1) {
++ bL_switcher_cpu_pairing[i] = match;
++ cpumask_clear_cpu(match, &available_cpus);
++ pr_info("CPU%d paired with CPU%d\n", i, match);
++ }
++ }
++
++ /*
++ * Now we disable the unwanted CPUs i.e. everything that has no
++ * pairing information (that includes the pairing counterparts).
++ */
++ cpumask_clear(&bL_switcher_removed_logical_cpus);
++ for_each_online_cpu(i) {
++ cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0);
++ cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 1);
++
++ /* Let's take note of the GIC ID for this CPU */
++ gic_id = gic_get_cpu_id(i);
++ if (gic_id < 0) {
++ pr_err("%s: bad GIC ID for CPU %d\n", __func__, i);
++ bL_switcher_restore_cpus();
++ return -EINVAL;
++ }
++ bL_gic_id[cpu][cluster] = gic_id;
++ pr_info("GIC ID for CPU %u cluster %u is %u\n",
++ cpu, cluster, gic_id);
++
++ if (bL_switcher_cpu_pairing[i] != -1) {
++ bL_switcher_cpu_original_cluster[i] = cluster;
++ continue;
++ }
++
++ ret = cpu_down(i);
++ if (ret) {
++ bL_switcher_restore_cpus();
++ return ret;
++ }
++ cpumask_set_cpu(i, &bL_switcher_removed_logical_cpus);
++ }
++
++ return 0;
++}
++
++/* Determine the logical CPU a given physical CPU is grouped on. */
++int bL_switcher_get_logical_index(u32 mpidr)
++{
++ int cpu;
++
++ if (!bL_switcher_active)
++ return -EUNATCH;
++
++ mpidr &= MPIDR_HWID_BITMASK;
++ for_each_online_cpu(cpu) {
++ int pairing = bL_switcher_cpu_pairing[cpu];
++ if (pairing == -1)
++ continue;
++ if ((mpidr == cpu_logical_map(cpu)) ||
++ (mpidr == cpu_logical_map(pairing)))
++ return cpu;
++ }
++ return -EINVAL;
++}
++
++static void bL_switcher_trace_trigger_cpu(void *__always_unused info)
++{
++ trace_cpu_migrate_current(get_ns(), read_mpidr());
++}
++
++int bL_switcher_trace_trigger(void)
++{
++ int ret;
++
++ preempt_disable();
++
++ bL_switcher_trace_trigger_cpu(NULL);
++ ret = smp_call_function(bL_switcher_trace_trigger_cpu, NULL, true);
++
++ preempt_enable();
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(bL_switcher_trace_trigger);
++
++static int bL_switcher_enable(void)
++{
++ int cpu, ret;
++
++ mutex_lock(&bL_switcher_activation_lock);
++ cpu_hotplug_driver_lock();
++ if (bL_switcher_active) {
++ cpu_hotplug_driver_unlock();
++ mutex_unlock(&bL_switcher_activation_lock);
++ return 0;
++ }
++
++ pr_info("big.LITTLE switcher initializing\n");
++
++ ret = bL_activation_notify(BL_NOTIFY_PRE_ENABLE);
++ if (ret)
++ goto error;
++
++ ret = bL_switcher_halve_cpus();
++ if (ret)
++ goto error;
++
++ bL_switcher_trace_trigger();
++
++ for_each_online_cpu(cpu) {
++ struct bL_thread *t = &bL_threads[cpu];
++ spin_lock_init(&t->lock);
++ init_waitqueue_head(&t->wq);
++ init_completion(&t->started);
++ t->wanted_cluster = -1;
++ t->task = bL_switcher_thread_create(cpu, t);
++ }
++
++ bL_switcher_active = 1;
++ bL_activation_notify(BL_NOTIFY_POST_ENABLE);
++ pr_info("big.LITTLE switcher initialized\n");
++ goto out;
++
++error:
++ pr_warning("big.LITTLE switcher initialization failed\n");
++ bL_activation_notify(BL_NOTIFY_POST_DISABLE);
++
++out:
++ cpu_hotplug_driver_unlock();
++ mutex_unlock(&bL_switcher_activation_lock);
++ return ret;
++}
++
++#ifdef CONFIG_SYSFS
++
++static void bL_switcher_disable(void)
++{
++ unsigned int cpu, cluster;
++ struct bL_thread *t;
++ struct task_struct *task;
++
++ mutex_lock(&bL_switcher_activation_lock);
++ cpu_hotplug_driver_lock();
++
++ if (!bL_switcher_active)
++ goto out;
++
++ if (bL_activation_notify(BL_NOTIFY_PRE_DISABLE) != 0) {
++ bL_activation_notify(BL_NOTIFY_POST_ENABLE);
++ goto out;
++ }
++
++ bL_switcher_active = 0;
++
++ /*
++ * To deactivate the switcher, we must shut down the switcher
++ * threads to prevent any other requests from being accepted.
++ * Then, if the final cluster for given logical CPU is not the
++ * same as the original one, we'll recreate a switcher thread
++ * just for the purpose of switching the CPU back without any
++ * possibility for interference from external requests.
++ */
++ for_each_online_cpu(cpu) {
++ t = &bL_threads[cpu];
++ task = t->task;
++ t->task = NULL;
++ if (!task || IS_ERR(task))
++ continue;
++ kthread_stop(task);
++ /* no more switch may happen on this CPU at this point */
++ cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1);
++ if (cluster == bL_switcher_cpu_original_cluster[cpu])
++ continue;
++ init_completion(&t->started);
++ t->wanted_cluster = bL_switcher_cpu_original_cluster[cpu];
++ task = bL_switcher_thread_create(cpu, t);
++ if (!IS_ERR(task)) {
++ wait_for_completion(&t->started);
++ kthread_stop(task);
++ cluster = MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1);
++ if (cluster == bL_switcher_cpu_original_cluster[cpu])
++ continue;
++ }
++ /* If execution gets here, we're in trouble. */
++ pr_crit("%s: unable to restore original cluster for CPU %d\n",
++ __func__, cpu);
++ pr_crit("%s: CPU %d can't be restored\n",
++ __func__, bL_switcher_cpu_pairing[cpu]);
++ cpumask_clear_cpu(bL_switcher_cpu_pairing[cpu],
++ &bL_switcher_removed_logical_cpus);
++ }
++
++ bL_switcher_restore_cpus();
++ bL_switcher_trace_trigger();
++
++ bL_activation_notify(BL_NOTIFY_POST_DISABLE);
++
++out:
++ cpu_hotplug_driver_unlock();
++ mutex_unlock(&bL_switcher_activation_lock);
++}
++
++static ssize_t bL_switcher_active_show(struct kobject *kobj,
++ struct kobj_attribute *attr, char *buf)
++{
++ return sprintf(buf, "%u\n", bL_switcher_active);
++}
++
++static ssize_t bL_switcher_active_store(struct kobject *kobj,
++ struct kobj_attribute *attr, const char *buf, size_t count)
++{
++ int ret;
++
++ switch (buf[0]) {
++ case '0':
++ bL_switcher_disable();
++ ret = 0;
++ break;
++ case '1':
++ ret = bL_switcher_enable();
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return (ret >= 0) ? count : ret;
++}
++
++static ssize_t bL_switcher_trace_trigger_store(struct kobject *kobj,
++ struct kobj_attribute *attr, const char *buf, size_t count)
++{
++ int ret = bL_switcher_trace_trigger();
++
++ return ret ? ret : count;
++}
++
++static struct kobj_attribute bL_switcher_active_attr =
++ __ATTR(active, 0644, bL_switcher_active_show, bL_switcher_active_store);
++
++static struct kobj_attribute bL_switcher_trace_trigger_attr =
++ __ATTR(trace_trigger, 0200, NULL, bL_switcher_trace_trigger_store);
++
++static struct attribute *bL_switcher_attrs[] = {
++ &bL_switcher_active_attr.attr,
++ &bL_switcher_trace_trigger_attr.attr,
++ NULL,
++};
++
++static struct attribute_group bL_switcher_attr_group = {
++ .attrs = bL_switcher_attrs,
++};
++
++static struct kobject *bL_switcher_kobj;
++
++static int __init bL_switcher_sysfs_init(void)
++{
++ int ret;
++
++ bL_switcher_kobj = kobject_create_and_add("bL_switcher", kernel_kobj);
++ if (!bL_switcher_kobj)
++ return -ENOMEM;
++ ret = sysfs_create_group(bL_switcher_kobj, &bL_switcher_attr_group);
++ if (ret)
++ kobject_put(bL_switcher_kobj);
++ return ret;
++}
++
++#endif /* CONFIG_SYSFS */
++
++bool bL_switcher_get_enabled(void)
++{
++ mutex_lock(&bL_switcher_activation_lock);
++
++ return bL_switcher_active;
++}
++EXPORT_SYMBOL_GPL(bL_switcher_get_enabled);
++
++void bL_switcher_put_enabled(void)
++{
++ mutex_unlock(&bL_switcher_activation_lock);
++}
++EXPORT_SYMBOL_GPL(bL_switcher_put_enabled);
++
++/*
++ * Veto any CPU hotplug operation while the switcher is active.
++ * We're just not ready to deal with that given the trickery involved.
++ */
++static int bL_switcher_hotplug_callback(struct notifier_block *nfb,
++ unsigned long action, void *hcpu)
++{
++ switch (action) {
++ case CPU_UP_PREPARE:
++ case CPU_DOWN_PREPARE:
++ if (bL_switcher_active)
++ return NOTIFY_BAD;
++ }
++ return NOTIFY_DONE;
++}
++
++static struct notifier_block bL_switcher_hotplug_notifier =
++ { &bL_switcher_hotplug_callback, NULL, 0 };
++
++#ifdef CONFIG_SCHED_HMP
++static bool no_bL_switcher = true;
++#else
++static bool no_bL_switcher;
++#endif
++core_param(no_bL_switcher, no_bL_switcher, bool, 0644);
++
++static int __init bL_switcher_init(void)
++{
++ int ret;
++
++ if (MAX_NR_CLUSTERS != 2) {
++ pr_err("%s: only dual cluster systems are supported\n", __func__);
++ return -EINVAL;
++ }
++
++ register_cpu_notifier(&bL_switcher_hotplug_notifier);
++
++ if (!no_bL_switcher) {
++ ret = bL_switcher_enable();
++ if (ret)
++ return ret;
++ }
++
++#ifdef CONFIG_SYSFS
++ ret = bL_switcher_sysfs_init();
++ if (ret)
++ pr_err("%s: unable to create sysfs entry\n", __func__);
++#endif
++
++ return 0;
++}
++
++late_initcall(bL_switcher_init);
+diff -Nur linux-3.10.30.orig/arch/arm/common/bL_switcher_dummy_if.c linux-linaro-stable-mx6/arch/arm/common/bL_switcher_dummy_if.c
+--- linux-3.10.30.orig/arch/arm/common/bL_switcher_dummy_if.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/common/bL_switcher_dummy_if.c 2014-05-15 20:33:34.301843035 +0200
+@@ -0,0 +1,71 @@
++/*
++ * arch/arm/common/bL_switcher_dummy_if.c -- b.L switcher dummy interface
++ *
++ * Created by: Nicolas Pitre, November 2012
++ * Copyright: (C) 2012 Linaro Limited
++ *
++ * Dummy interface to user space for debugging purpose only.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <asm/uaccess.h>
++#include <asm/bL_switcher.h>
++
++static ssize_t bL_switcher_write(struct file *file, const char __user *buf,
++ size_t len, loff_t *pos)
++{
++ unsigned char val[3];
++ unsigned int cpu, cluster;
++ int ret;
++
++ pr_debug("%s\n", __func__);
++
++ if (len < 3)
++ return -EINVAL;
++
++ if (copy_from_user(val, buf, 3))
++ return -EFAULT;
++
++ /* format: <cpu#>,<cluster#> */
++ if (val[0] < '0' || val[0] > '4' ||
++ val[1] != ',' ||
++ val[2] < '0' || val[2] > '1')
++ return -EINVAL;
++
++ cpu = val[0] - '0';
++ cluster = val[2] - '0';
++ ret = bL_switch_request(cpu, cluster);
++
++ return ret ? : len;
++}
++
++static const struct file_operations bL_switcher_fops = {
++ .write = bL_switcher_write,
++ .owner = THIS_MODULE,
++};
++
++static struct miscdevice bL_switcher_device = {
++ MISC_DYNAMIC_MINOR,
++ "b.L_switcher",
++ &bL_switcher_fops
++};
++
++static int __init bL_switcher_dummy_if_init(void)
++{
++ return misc_register(&bL_switcher_device);
++}
++
++static void __exit bL_switcher_dummy_if_exit(void)
++{
++ misc_deregister(&bL_switcher_device);
++}
++
++module_init(bL_switcher_dummy_if_init);
++module_exit(bL_switcher_dummy_if_exit);
+diff -Nur linux-3.10.30.orig/arch/arm/common/Makefile linux-linaro-stable-mx6/arch/arm/common/Makefile
+--- linux-3.10.30.orig/arch/arm/common/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/common/Makefile 2014-05-15 20:33:34.297843005 +0200
+@@ -14,5 +14,9 @@
+ obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
+ obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
+ obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
++obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o
++obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o
++
+ AFLAGS_mcpm_head.o := -march=armv7-a
+ AFLAGS_vlock.o := -march=armv7-a
++CFLAGS_REMOVE_mcpm_entry.o = -pg
+diff -Nur linux-3.10.30.orig/arch/arm/common/mcpm_entry.c linux-linaro-stable-mx6/arch/arm/common/mcpm_entry.c
+--- linux-3.10.30.orig/arch/arm/common/mcpm_entry.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/common/mcpm_entry.c 2014-05-15 20:33:34.301843035 +0200
+@@ -27,6 +27,18 @@
+ sync_cache_w(&mcpm_entry_vectors[cluster][cpu]);
+ }
+
++extern unsigned long mcpm_entry_early_pokes[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER][2];
++
++void mcpm_set_early_poke(unsigned cpu, unsigned cluster,
++ unsigned long poke_phys_addr, unsigned long poke_val)
++{
++ unsigned long *poke = &mcpm_entry_early_pokes[cluster][cpu][0];
++ poke[0] = poke_phys_addr;
++ poke[1] = poke_val;
++ __cpuc_flush_dcache_area((void *)poke, 8);
++ outer_clean_range(__pa(poke), __pa(poke + 2));
++}
++
+ static const struct mcpm_platform_ops *platform_ops;
+
+ int __init mcpm_platform_register(const struct mcpm_platform_ops *ops)
+diff -Nur linux-3.10.30.orig/arch/arm/common/mcpm_head.S linux-linaro-stable-mx6/arch/arm/common/mcpm_head.S
+--- linux-3.10.30.orig/arch/arm/common/mcpm_head.S 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/common/mcpm_head.S 2014-05-15 20:33:34.309843092 +0200
+@@ -71,12 +71,19 @@
+ * position independent way.
+ */
+ adr r5, 3f
+- ldmia r5, {r6, r7, r8, r11}
++ ldmia r5, {r0, r6, r7, r8, r11}
++ add r0, r5, r0 @ r0 = mcpm_entry_early_pokes
+ add r6, r5, r6 @ r6 = mcpm_entry_vectors
+ ldr r7, [r5, r7] @ r7 = mcpm_power_up_setup_phys
+ add r8, r5, r8 @ r8 = mcpm_sync
+ add r11, r5, r11 @ r11 = first_man_locks
+
++ @ Perform an early poke, if any
++ add r0, r0, r4, lsl #3
++ ldmia r0, {r0, r1}
++ teq r0, #0
++ strne r1, [r0]
++
+ mov r0, #MCPM_SYNC_CLUSTER_SIZE
+ mla r8, r0, r10, r8 @ r8 = sync cluster base
+
+@@ -195,7 +202,8 @@
+
+ .align 2
+
+-3: .word mcpm_entry_vectors - .
++3: .word mcpm_entry_early_pokes - .
++ .word mcpm_entry_vectors - 3b
+ .word mcpm_power_up_setup_phys - 3b
+ .word mcpm_sync - 3b
+ .word first_man_locks - 3b
+@@ -214,6 +222,10 @@
+ ENTRY(mcpm_entry_vectors)
+ .space 4 * MAX_NR_CLUSTERS * MAX_CPUS_PER_CLUSTER
+
++ .type mcpm_entry_early_pokes, #object
++ENTRY(mcpm_entry_early_pokes)
++ .space 8 * MAX_NR_CLUSTERS * MAX_CPUS_PER_CLUSTER
++
+ .type mcpm_power_up_setup_phys, #object
+ ENTRY(mcpm_power_up_setup_phys)
+ .space 4 @ set by mcpm_sync_init()
+diff -Nur linux-3.10.30.orig/arch/arm/configs/imx_v6_v7_defconfig linux-linaro-stable-mx6/arch/arm/configs/imx_v6_v7_defconfig
+--- linux-3.10.30.orig/arch/arm/configs/imx_v6_v7_defconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/configs/imx_v6_v7_defconfig 2014-05-15 20:33:34.345843352 +0200
+@@ -1,4 +1,3 @@
+-CONFIG_EXPERIMENTAL=y
+ # CONFIG_LOCALVERSION_AUTO is not set
+ CONFIG_KERNEL_LZO=y
+ CONFIG_SYSVIPC=y
+@@ -17,10 +16,9 @@
+ CONFIG_MODVERSIONS=y
+ CONFIG_MODULE_SRCVERSION_ALL=y
+ # CONFIG_BLK_DEV_BSG is not set
+-CONFIG_ARCH_MXC=y
+ CONFIG_ARCH_MULTI_V6=y
+-CONFIG_ARCH_MULTI_V7=y
+-CONFIG_MACH_IMX31_DT=y
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
+ CONFIG_MACH_MX31LILLY=y
+ CONFIG_MACH_MX31LITE=y
+ CONFIG_MACH_PCM037=y
+@@ -30,6 +28,7 @@
+ CONFIG_MACH_QONG=y
+ CONFIG_MACH_ARMADILLO5X0=y
+ CONFIG_MACH_KZM_ARM11_01=y
++CONFIG_MACH_IMX31_DT=y
+ CONFIG_MACH_PCM043=y
+ CONFIG_MACH_MX35_3DS=y
+ CONFIG_MACH_VPR200=y
+@@ -37,16 +36,26 @@
+ CONFIG_MACH_EUKREA_CPUIMX51SD=y
+ CONFIG_SOC_IMX53=y
+ CONFIG_SOC_IMX6Q=y
+-CONFIG_MXC_PWM=y
++CONFIG_SOC_IMX6SL=y
++CONFIG_SOC_VF610=y
+ CONFIG_SMP=y
+ CONFIG_VMSPLIT_2G=y
+ CONFIG_PREEMPT_VOLUNTARY=y
+ CONFIG_AEABI=y
+ # CONFIG_OABI_COMPAT is not set
+ CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6_CPUFREQ=y
++CONFIG_CPU_IDLE=y
+ CONFIG_VFP=y
+ CONFIG_NEON=y
+ CONFIG_BINFMT_MISC=m
++CONFIG_PM_RUNTIME=y
+ CONFIG_PM_DEBUG=y
+ CONFIG_PM_TEST_SUSPEND=y
+ CONFIG_NET=y
+@@ -65,16 +74,19 @@
+ CONFIG_DEVTMPFS=y
+ CONFIG_DEVTMPFS_MOUNT=y
+ # CONFIG_STANDALONE is not set
++CONFIG_CMA=y
++CONFIG_CMA_SIZE_MBYTES=256
++CONFIG_IMX_WEIM=y
+ CONFIG_CONNECTOR=y
+ CONFIG_MTD=y
+ CONFIG_MTD_CMDLINE_PARTS=y
+-CONFIG_MTD_CHAR=y
+ CONFIG_MTD_BLOCK=y
+ CONFIG_MTD_CFI=y
+ CONFIG_MTD_JEDECPROBE=y
+ CONFIG_MTD_CFI_INTELEXT=y
+ CONFIG_MTD_CFI_AMDSTD=y
+ CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP_OF=y
+ CONFIG_MTD_DATAFLASH=y
+ CONFIG_MTD_M25P80=y
+ CONFIG_MTD_SST25L=y
+@@ -95,10 +107,11 @@
+ CONFIG_SCSI_SCAN_ASYNC=y
+ # CONFIG_SCSI_LOWLEVEL is not set
+ CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
+ CONFIG_PATA_IMX=y
+ CONFIG_NETDEVICES=y
+ # CONFIG_NET_VENDOR_BROADCOM is not set
+-# CONFIG_NET_VENDOR_CHELSIO is not set
+ CONFIG_CS89x0=y
+ CONFIG_CS89x0_PLATFORM=y
+ # CONFIG_NET_VENDOR_FARADAY is not set
+@@ -112,6 +125,7 @@
+ CONFIG_SMC911X=y
+ CONFIG_SMSC911X=y
+ # CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_AT803X_PHY=y
+ # CONFIG_WLAN is not set
+ # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+ CONFIG_INPUT_EVDEV=y
+@@ -121,22 +135,26 @@
+ CONFIG_MOUSE_PS2=m
+ CONFIG_MOUSE_PS2_ELANTECH=y
+ CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EGALAX=y
++CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH=y
++CONFIG_TOUCHSCREEN_MAX11801=y
+ CONFIG_TOUCHSCREEN_MC13783=y
+ CONFIG_INPUT_MISC=y
+ CONFIG_INPUT_MMA8450=y
++CONFIG_INPUT_ISL29023=y
+ CONFIG_SERIO_SERPORT=m
+ CONFIG_VT_HW_CONSOLE_BINDING=y
+ # CONFIG_LEGACY_PTYS is not set
+ # CONFIG_DEVKMEM is not set
+ CONFIG_SERIAL_IMX=y
+ CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+ CONFIG_HW_RANDOM=y
+ CONFIG_HW_RANDOM_MXC_RNGA=y
+-CONFIG_I2C=y
+ # CONFIG_I2C_COMPAT is not set
+ CONFIG_I2C_CHARDEV=y
+ # CONFIG_I2C_HELPER_AUTO is not set
+-CONFIG_I2C_ALGOBIT=m
+ CONFIG_I2C_ALGOPCF=m
+ CONFIG_I2C_ALGOPCA=m
+ CONFIG_I2C_IMX=y
+@@ -144,7 +162,13 @@
+ CONFIG_SPI_IMX=y
+ CONFIG_GPIO_SYSFS=y
+ CONFIG_GPIO_MC9S08DZ60=y
+-# CONFIG_HWMON is not set
++CONFIG_POWER_SUPPLY=y
++CONFIG_SABRESD_MAX8903=y
++CONFIG_SENSORS_MAG3110=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
+ CONFIG_WATCHDOG=y
+ CONFIG_IMX2_WDT=y
+ CONFIG_MFD_DA9052_I2C=y
+@@ -156,20 +180,35 @@
+ CONFIG_REGULATOR_ANATOP=y
+ CONFIG_REGULATOR_MC13783=y
+ CONFIG_REGULATOR_MC13892=y
++CONFIG_REGULATOR_PFUZE100=y
+ CONFIG_MEDIA_SUPPORT=y
+-CONFIG_VIDEO_DEV=y
+-CONFIG_V4L_PLATFORM_DRIVERS=y
+ CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_MEDIA_RC_SUPPORT=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+ CONFIG_SOC_CAMERA=y
++CONFIG_VIDEO_MX3=y
+ CONFIG_SOC_CAMERA_OV2640=y
+ CONFIG_DRM=y
+-CONFIG_VIDEO_MX3=y
++CONFIG_DRM_VIVANTE=y
+ CONFIG_FB=y
+-CONFIG_LCD_PLATFORM=y
++CONFIG_FB_MXS=y
+ CONFIG_BACKLIGHT_LCD_SUPPORT=y
+ CONFIG_LCD_CLASS_DEVICE=y
+ CONFIG_LCD_L4F00242T03=y
++CONFIG_LCD_PLATFORM=y
+ CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_MIPI_DSI=y
++CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
++CONFIG_FB_MXC_HDMI=y
+ CONFIG_FRAMEBUFFER_CONSOLE=y
+ CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+ CONFIG_FONTS=y
+@@ -178,24 +217,36 @@
+ CONFIG_LOGO=y
+ CONFIG_SOUND=y
+ CONFIG_SND=y
++CONFIG_SND_USB_AUDIO=m
+ CONFIG_SND_SOC=y
+ CONFIG_SND_IMX_SOC=y
+ CONFIG_SND_SOC_PHYCORE_AC97=y
+ CONFIG_SND_SOC_EUKREA_TLV320=y
++CONFIG_SND_SOC_IMX_CS42888=y
++CONFIG_SND_SOC_IMX_WM8962=y
+ CONFIG_SND_SOC_IMX_SGTL5000=y
+ CONFIG_SND_SOC_IMX_MC13783=y
+ CONFIG_USB=y
+ CONFIG_USB_EHCI_HCD=y
+-CONFIG_USB_EHCI_MXC=y
++CONFIG_USB_STORAGE=y
+ CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
+ CONFIG_USB_CHIPIDEA_HOST=y
+ CONFIG_USB_PHY=y
+ CONFIG_USB_MXS_PHY=y
+-CONFIG_USB_STORAGE=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
+ CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_PLTFM=y
+ CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++CONFIG_MXC_GPU_VIV=y
++CONFIG_MXC_ASRC=y
+ CONFIG_NEW_LEDS=y
+ CONFIG_LEDS_CLASS=y
+ CONFIG_RTC_CLASS=y
+@@ -204,14 +255,14 @@
+ CONFIG_RTC_DRV_MXC=y
+ CONFIG_RTC_DRV_SNVS=y
+ CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
+ CONFIG_IMX_SDMA=y
+ CONFIG_MXS_DMA=y
+ CONFIG_STAGING=y
+-CONFIG_DRM_IMX=y
+-CONFIG_DRM_IMX_IPUV3_CORE=y
+-CONFIG_DRM_IMX_IPUV3=y
+ CONFIG_COMMON_CLK_DEBUG=y
+ # CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PWM=y
++CONFIG_PWM_IMX=y
+ CONFIG_EXT2_FS=y
+ CONFIG_EXT2_FS_XATTR=y
+ CONFIG_EXT2_FS_POSIX_ACL=y
+@@ -234,7 +285,6 @@
+ CONFIG_MSDOS_FS=m
+ CONFIG_VFAT_FS=y
+ CONFIG_TMPFS=y
+-CONFIG_CONFIGFS_FS=m
+ CONFIG_JFFS2_FS=y
+ CONFIG_UBIFS_FS=y
+ CONFIG_NFS_FS=y
+diff -Nur linux-3.10.30.orig/arch/arm/configs/imx_v7_cubox-i_hummingboard_defconfig linux-linaro-stable-mx6/arch/arm/configs/imx_v7_cubox-i_hummingboard_defconfig
+--- linux-3.10.30.orig/arch/arm/configs/imx_v7_cubox-i_hummingboard_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/configs/imx_v7_cubox-i_hummingboard_defconfig 2014-05-15 20:33:34.345843352 +0200
+@@ -0,0 +1,384 @@
++CONFIG_KERNEL_LZO=y
++CONFIG_SYSVIPC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_CGROUPS=y
++CONFIG_RELAY=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
++CONFIG_MXC_DEBUG_BOARD=y
++CONFIG_HAVE_IMX_ANATOP=y
++CONFIG_HAVE_IMX_GPC=y
++CONFIG_HAVE_IMX_MMDC=y
++CONFIG_HAVE_IMX_SRC=y
++CONFIG_ARCH_MXC_IOMUX_V3=y
++CONFIG_SOC_IMX6Q=y
++CONFIG_SOC_IMX6SL=y
++CONFIG_IMX_HAVE_PLATFORM_FEC=y
++CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y
++CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS=y
++CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y
++CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y
++CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y
++CONFIG_IMX_HAVE_PLATFORM_MXC_NAND=y
++CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y
++CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y
++CONFIG_PCI=y
++CONFIG_PCI_IMX6=y
++# CONFIG_SWP_EMULATE is not set
++CONFIG_SMP=y
++CONFIG_VMSPLIT_2G=y
++CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_BINFMT_MISC=m
++CONFIG_PM_RUNTIME=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_TEST_SUSPEND=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++CONFIG_IPV6=y
++CONFIG_NETFILTER=y
++CONFIG_VLAN_8021Q=y
++CONFIG_CAN=y
++CONFIG_CAN_FLEXCAN=y
++CONFIG_BT=y
++CONFIG_BT_L2CAP=y
++CONFIG_BT_SCO=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++
++#
++# Bluetooth device drivers
++#
++CONFIG_BT_HCIBTUSB=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_ATH3K=y
++CONFIG_BT_HCIVHCI=y
++CONFIG_WIRELESS=y
++CONFIG_WIRELESS_EXT=y
++CONFIG_WEXT_CORE=y
++CONFIG_WEXT_PROC=y
++CONFIG_WEXT_SPY=y
++CONFIG_WEXT_PRIV=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEFAULT_PS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_WIRELESS_EXT_SYSFS=y
++CONFIG_LIB80211=y
++CONFIG_LIB80211_CRYPT_WEP=y
++CONFIG_LIB80211_CRYPT_CCMP=y
++CONFIG_LIB80211_CRYPT_TKIP=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_LEDS=y
++CONFIG_RFKILL_INPUT=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++CONFIG_CMA=y
++CONFIG_CMA_SIZE_MBYTES=256
++CONFIG_IMX_WEIM=y
++CONFIG_CONNECTOR=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_M25P80=y
++CONFIG_MTD_SST25L=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_GPMI_NAND=y
++CONFIG_MTD_NAND_MXC=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_EEPROM_AT24=y
++CONFIG_EEPROM_AT25=y
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
++CONFIG_PATA_IMX=y
++CONFIG_NETDEVICES=y
++CONFIG_NET_VENDOR_FREESCALE=y
++CONFIG_FEC=y
++CONFIG_PHYLIB=y
++CONFIG_AT803X_PHY=y
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_CS89x0=y
++CONFIG_CS89x0_PLATFORM=y
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_SMC91X=y
++CONFIG_SMC911X=y
++CONFIG_SMSC911X=y
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_ATH_CARDS=y
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_SDIO=m
++CONFIG_BRCMUTIL=y
++# CONFIG_BRCMSMAC is not set
++CONFIG_BRCMFMAC=m
++CONFIG_BRCMFMAC_SDIO=y
++CONFIG_HOSTAP=y
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_EVDEV=y
++CONFIG_INPUT_EVBUG=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_IMX=y
++CONFIG_MOUSE_PS2=m
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_MMA8450=y
++CONFIG_INPUT_ISL29023=y
++CONFIG_SERIO_SERPORT=m
++CONFIG_VT_HW_CONSOLE_BINDING=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_HELPER_AUTO is not set
++CONFIG_I2C_ALGOPCF=m
++CONFIG_I2C_ALGOPCA=m
++CONFIG_I2C_IMX=y
++CONFIG_SPI=y
++CONFIG_SPI_IMX=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_MXC_MMA8451=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_MFD_DA9052_I2C=y
++CONFIG_MFD_MC13XXX_SPI=y
++CONFIG_MFD_MC13XXX_I2C=y
++CONFIG_MFD_SI476X_CORE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_DA9052=y
++CONFIG_REGULATOR_ANATOP=y
++CONFIG_REGULATOR_MC13783=y
++CONFIG_REGULATOR_MC13892=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_VIDEO_V4L2=y
++CONFIG_VIDEO_CAPTURE_DRIVERS=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_RC_SUPPORT=y
++CONFIG_VIDEO_DEV=y
++CONFIG_VIDEO_V4L2_COMMON=y
++CONFIG_VIDEO_MEDIA=y
++CONFIG_VIDEOBUF_GEN=y
++CONFIG_VIDEOBUF_DMA_CONTIG=y
++CONFIG_VIDEOBUF2_CORE=y
++CONFIG_VIDEOBUF2_MEMOPS=y
++CONFIG_VIDEOBUF2_DMA_CONTIG=y
++CONFIG_VIDEOBUF2_VMALLOC=m
++CONFIG_VIDEO_V4L2_INT_DEVICE=y
++CONFIG_RC_CORE=y
++CONFIG_RC_MAP=y
++CONFIG_RC_DECODERS=y
++CONFIG_LIRC=y
++CONFIG_IR_LIRC_CODEC=y
++CONFIG_IR_NEC_DECODER=y
++CONFIG_IR_RC5_DECODER=y
++CONFIG_IR_RC6_DECODER=y
++CONFIG_IR_JVC_DECODER=y
++CONFIG_IR_SONY_DECODER=y
++CONFIG_IR_RC5_SZ_DECODER=y
++CONFIG_IR_SANYO_DECODER=y
++CONFIG_IR_MCE_KBD_DECODER=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_CAPTURE=m
++CONFIG_VIDEO_MXC_CSI_CAMERA=m
++CONFIG_MXC_CAMERA_OV5640=m
++CONFIG_MXC_CAMERA_OV5642=m
++CONFIG_MXC_CAMERA_OV5640_MIPI=m
++CONFIG_MXC_TVIN_ADV7180=m
++CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++CONFIG_VIDEO_MXC_PXP_V4L2=y
++CONFIG_SOC_CAMERA=y
++CONFIG_VIDEO_MX3=y
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++CONFIG_VIDEO_IR_I2C=y
++CONFIG_DRM=y
++CONFIG_DRM_VIVANTE=y
++CONFIG_FB=y
++CONFIG_FB_MXS=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_HDMI=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_SND_SOC_FSL_SPDIF=y
++CONFIG_SND_SOC_FSL_HDMI=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_PHY=y
++CONFIG_USB_MXS_PHY=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++CONFIG_MXC_GPU_VIV=y
++CONFIG_MXC_ASRC=y
++CONFIG_MXC_HDMI_CEC=y
++CONFIG_MXC_VPU=y
++CONFIG_MXC_MIPI_CSI2=y
++CONFIG_MXC_MLB150=m
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_PWM=y
++CONFIG_LEDS_REGULATOR=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_INTF_DEV_UIE_EMUL=y
++CONFIG_RTC_DRV_MC13XXX=y
++CONFIG_RTC_DRV_MXC=y
++CONFIG_RTC_DRV_SNVS=y
++CONFIG_RTC_DRV_PCF8523=y
++CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
++CONFIG_IMX_SDMA=y
++CONFIG_MXS_DMA=y
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_LIRC_STAGING=y
++CONFIG_LIRC_SERIAL=y
++CONFIG_LIRC_SERIAL_TRANSMITTER=y
++CONFIG_COMMON_CLK_DEBUG=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PWM=y
++CONFIG_PWM_IMX=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT23=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_QUOTA=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_UTF8=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_FTRACE is not set
++CONFIG_SECURITYFS=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=y
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
+diff -Nur linux-3.10.30.orig/arch/arm/configs/imx_v7_defconfig linux-linaro-stable-mx6/arch/arm/configs/imx_v7_defconfig
+--- linux-3.10.30.orig/arch/arm/configs/imx_v7_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/configs/imx_v7_defconfig 2014-05-15 20:33:34.345843352 +0200
+@@ -0,0 +1,332 @@
++CONFIG_KERNEL_LZO=y
++CONFIG_SYSVIPC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_CGROUPS=y
++CONFIG_RELAY=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
++CONFIG_MXC_DEBUG_BOARD=y
++CONFIG_MACH_IMX51_DT=y
++CONFIG_MACH_EUKREA_CPUIMX51SD=y
++CONFIG_SOC_IMX53=y
++CONFIG_SOC_IMX6Q=y
++CONFIG_SOC_IMX6SL=y
++CONFIG_SOC_VF610=y
++# CONFIG_SWP_EMULATE is not set
++CONFIG_SMP=y
++CONFIG_VMSPLIT_2G=y
++CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_BINFMT_MISC=m
++CONFIG_PM_RUNTIME=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_TEST_SUSPEND=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++CONFIG_IPV6=y
++CONFIG_NETFILTER=y
++CONFIG_VLAN_8021Q=y
++CONFIG_CAN=y
++CONFIG_CAN_FLEXCAN=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++CONFIG_CMA=y
++CONFIG_CMA_SIZE_MBYTES=256
++CONFIG_IMX_WEIM=y
++CONFIG_CONNECTOR=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_M25P80=y
++CONFIG_MTD_SST25L=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_GPMI_NAND=y
++CONFIG_MTD_NAND_MXC=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_EEPROM_AT24=y
++CONFIG_EEPROM_AT25=y
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
++CONFIG_PATA_IMX=y
++CONFIG_NETDEVICES=y
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_CS89x0=y
++CONFIG_CS89x0_PLATFORM=y
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_SMC91X=y
++CONFIG_SMC911X=y
++CONFIG_SMSC911X=y
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_ATH_CARDS=y
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_SDIO=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_EVDEV=y
++CONFIG_INPUT_EVBUG=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_IMX=y
++CONFIG_MOUSE_PS2=m
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EGALAX=y
++CONFIG_TOUCHSCREEN_ELAN=y
++CONFIG_TOUCHSCREEN_MAX11801=y
++CONFIG_TOUCHSCREEN_MC13783=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_MMA8450=y
++CONFIG_INPUT_ISL29023=y
++CONFIG_SERIO_SERPORT=m
++CONFIG_VT_HW_CONSOLE_BINDING=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_FSL_OTP=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_HELPER_AUTO is not set
++CONFIG_I2C_ALGOPCF=m
++CONFIG_I2C_ALGOPCA=m
++CONFIG_I2C_IMX=y
++CONFIG_SPI=y
++CONFIG_SPI_IMX=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_SABRESD_MAX8903=y
++CONFIG_IMX6_USB_CHARGER=y
++CONFIG_SENSORS_MAX17135=y
++CONFIG_SENSORS_MAG3110=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_MFD_DA9052_I2C=y
++CONFIG_MFD_MC13XXX_SPI=y
++CONFIG_MFD_MC13XXX_I2C=y
++CONFIG_MFD_MAX17135=y
++CONFIG_MFD_SI476X_CORE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_DA9052=y
++CONFIG_REGULATOR_ANATOP=y
++CONFIG_REGULATOR_MC13783=y
++CONFIG_REGULATOR_MC13892=y
++CONFIG_REGULATOR_MAX17135=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_RADIO_SUPPORT=y
++CONFIG_VIDEO_V4L2_INT_DEVICE=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_CAPTURE=m
++CONFIG_VIDEO_MXC_CSI_CAMERA=m
++CONFIG_MXC_CAMERA_OV5640=m
++CONFIG_MXC_CAMERA_OV5642=m
++CONFIG_MXC_CAMERA_OV5640_MIPI=m
++CONFIG_MXC_TVIN_ADV7180=m
++CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++CONFIG_VIDEO_MXC_PXP_V4L2=y
++CONFIG_SOC_CAMERA=y
++CONFIG_VIDEO_MX3=y
++CONFIG_RADIO_SI476X=y
++CONFIG_SOC_CAMERA_OV2640=y
++CONFIG_DRM=y
++CONFIG_DRM_VIVANTE=y
++CONFIG_FB=y
++CONFIG_FB_MXS=y
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_LCD_L4F00242T03=y
++CONFIG_LCD_PLATFORM=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_MIPI_DSI=y
++CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
++CONFIG_FB_MXC_HDMI=y
++CONFIG_FB_MXC_EINK_PANEL=y
++CONFIG_FB_MXS_SII902X=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_SOC_EUKREA_TLV320=y
++CONFIG_SND_SOC_IMX_CS42888=y
++CONFIG_SND_SOC_IMX_WM8962=y
++CONFIG_SND_SOC_IMX_SGTL5000=y
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_MC13783=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_SND_SOC_IMX_SI476X=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_PHY=y
++CONFIG_USB_MXS_PHY=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++CONFIG_MXC_GPU_VIV=y
++CONFIG_MXC_ASRC=y
++CONFIG_MXC_MIPI_CSI2=y
++CONFIG_MXC_MLB150=m
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_INTF_DEV_UIE_EMUL=y
++CONFIG_RTC_DRV_MC13XXX=y
++CONFIG_RTC_DRV_MXC=y
++CONFIG_RTC_DRV_SNVS=y
++CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
++CONFIG_IMX_SDMA=y
++CONFIG_MXS_DMA=y
++CONFIG_STAGING=y
++CONFIG_COMMON_CLK_DEBUG=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PWM=y
++CONFIG_PWM_IMX=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_QUOTA=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_UTF8=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_FTRACE is not set
++CONFIG_SECURITYFS=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=y
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
+diff -Nur linux-3.10.30.orig/arch/arm/configs/imx_v7_mfg_defconfig linux-linaro-stable-mx6/arch/arm/configs/imx_v7_mfg_defconfig
+--- linux-3.10.30.orig/arch/arm/configs/imx_v7_mfg_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/configs/imx_v7_mfg_defconfig 2014-05-15 20:33:34.345843352 +0200
+@@ -0,0 +1,341 @@
++CONFIG_KERNEL_LZO=y
++CONFIG_SYSVIPC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_CGROUPS=y
++CONFIG_RELAY=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
++CONFIG_MXC_DEBUG_BOARD=y
++CONFIG_MACH_IMX51_DT=y
++CONFIG_MACH_EUKREA_CPUIMX51SD=y
++CONFIG_SOC_IMX53=y
++CONFIG_SOC_IMX6Q=y
++CONFIG_SOC_IMX6SL=y
++CONFIG_SOC_VF610=y
++# CONFIG_SWP_EMULATE is not set
++CONFIG_SMP=y
++CONFIG_VMSPLIT_2G=y
++CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_BINFMT_MISC=m
++CONFIG_PM_RUNTIME=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_TEST_SUSPEND=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++CONFIG_IPV6=y
++CONFIG_NETFILTER=y
++CONFIG_VLAN_8021Q=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++CONFIG_CMA=y
++CONFIG_CMA_SIZE_MBYTES=256
++CONFIG_IMX_WEIM=y
++CONFIG_CONNECTOR=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_M25P80=y
++CONFIG_MTD_SST25L=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_GPMI_NAND=y
++CONFIG_MTD_NAND_MXC=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_EEPROM_AT24=y
++CONFIG_EEPROM_AT25=y
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
++CONFIG_PATA_IMX=y
++CONFIG_NETDEVICES=y
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_CS89x0=y
++CONFIG_CS89x0_PLATFORM=y
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_SMC91X=y
++CONFIG_SMC911X=y
++CONFIG_SMSC911X=y
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_ATH_CARDS=y
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_SDIO=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_EVDEV=y
++CONFIG_INPUT_EVBUG=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_IMX=y
++CONFIG_MOUSE_PS2=m
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EGALAX=y
++CONFIG_TOUCHSCREEN_ELAN=y
++CONFIG_TOUCHSCREEN_MAX11801=y
++CONFIG_TOUCHSCREEN_MC13783=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_MMA8450=y
++CONFIG_INPUT_ISL29023=y
++CONFIG_SERIO_SERPORT=m
++CONFIG_VT_HW_CONSOLE_BINDING=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_FSL_OTP=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_HELPER_AUTO is not set
++CONFIG_I2C_ALGOPCF=m
++CONFIG_I2C_ALGOPCA=m
++CONFIG_I2C_IMX=y
++CONFIG_SPI=y
++CONFIG_SPI_IMX=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_SABRESD_MAX8903=y
++CONFIG_SENSORS_MAX17135=y
++CONFIG_SENSORS_MAG3110=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_MFD_DA9052_I2C=y
++CONFIG_MFD_MC13XXX_SPI=y
++CONFIG_MFD_MC13XXX_I2C=y
++CONFIG_MFD_MAX17135=y
++CONFIG_MFD_SI476X_CORE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_DA9052=y
++CONFIG_REGULATOR_ANATOP=y
++CONFIG_REGULATOR_MC13783=y
++CONFIG_REGULATOR_MC13892=y
++CONFIG_REGULATOR_MAX17135=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_RADIO_SUPPORT=y
++CONFIG_VIDEO_V4L2_INT_DEVICE=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_CAPTURE=m
++CONFIG_VIDEO_MXC_CSI_CAMERA=m
++CONFIG_MXC_CAMERA_OV5640=m
++CONFIG_MXC_CAMERA_OV5642=m
++CONFIG_MXC_CAMERA_OV5640_MIPI=m
++CONFIG_MXC_TVIN_ADV7180=m
++CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++CONFIG_VIDEO_MXC_PXP_V4L2=y
++CONFIG_SOC_CAMERA=y
++CONFIG_VIDEO_MX3=y
++CONFIG_RADIO_SI476X=y
++CONFIG_SOC_CAMERA_OV2640=y
++CONFIG_DRM=y
++CONFIG_DRM_VIVANTE=y
++CONFIG_FB=y
++CONFIG_FB_MXS=y
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_LCD_L4F00242T03=y
++CONFIG_LCD_PLATFORM=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_MIPI_DSI=y
++CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
++CONFIG_FB_MXC_HDMI=y
++CONFIG_FB_MXC_EINK_PANEL=y
++CONFIG_FB_MXS_SII902X=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_SOC_EUKREA_TLV320=y
++CONFIG_SND_SOC_IMX_CS42888=y
++CONFIG_SND_SOC_IMX_WM8962=y
++CONFIG_SND_SOC_IMX_SGTL5000=y
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_MC13783=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_SND_SOC_IMX_SI476X=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_PHY=y
++CONFIG_USB_MXS_PHY=y
++CONFIG_USB_GADGET=y
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_AUDIO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=y
++CONFIG_FSL_UTP=y
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++CONFIG_MXC_GPU_VIV=y
++CONFIG_MXC_ASRC=y
++CONFIG_MXC_MIPI_CSI2=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_INTF_DEV_UIE_EMUL=y
++CONFIG_RTC_DRV_MC13XXX=y
++CONFIG_RTC_DRV_MXC=y
++CONFIG_RTC_DRV_SNVS=y
++CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
++CONFIG_IMX_SDMA=y
++CONFIG_MXS_DMA=y
++CONFIG_STAGING=y
++CONFIG_COMMON_CLK_DEBUG=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PWM=y
++CONFIG_PWM_IMX=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_QUOTA=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_UTF8=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_FTRACE is not set
++CONFIG_SECURITYFS=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=y
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/arch_timer.h linux-linaro-stable-mx6/arch/arm/include/asm/arch_timer.h
+--- linux-3.10.30.orig/arch/arm/include/asm/arch_timer.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/arch_timer.h 2014-05-15 20:33:34.393843699 +0200
+@@ -96,7 +96,7 @@
+ asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl));
+
+ /* disable user access to everything */
+- cntkctl &= ~((3 << 8) | (7 << 0));
++ cntkctl &= ~((3 << 8) | (3 << 0));
+
+ asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl));
+ }
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/bL_switcher.h linux-linaro-stable-mx6/arch/arm/include/asm/bL_switcher.h
+--- linux-3.10.30.orig/arch/arm/include/asm/bL_switcher.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/bL_switcher.h 2014-05-15 20:33:34.393843699 +0200
+@@ -0,0 +1,83 @@
++/*
++ * arch/arm/include/asm/bL_switcher.h
++ *
++ * Created by: Nicolas Pitre, April 2012
++ * Copyright: (C) 2012 Linaro Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef ASM_BL_SWITCHER_H
++#define ASM_BL_SWITCHER_H
++
++#include <linux/compiler.h>
++#include <linux/types.h>
++
++typedef void (*bL_switch_completion_handler)(void *cookie);
++
++int bL_switch_request_cb(unsigned int cpu, unsigned int new_cluster_id,
++ bL_switch_completion_handler completer,
++ void *completer_cookie);
++static inline int bL_switch_request(unsigned int cpu, unsigned int new_cluster_id)
++{
++ return bL_switch_request_cb(cpu, new_cluster_id, NULL, NULL);
++}
++
++/*
++ * Register here to be notified about runtime enabling/disabling of
++ * the switcher.
++ *
++ * The notifier chain is called with the switcher activation lock held:
++ * the switcher will not be enabled or disabled during callbacks.
++ * Callbacks must not call bL_switcher_{get,put}_enabled().
++ */
++#define BL_NOTIFY_PRE_ENABLE 0
++#define BL_NOTIFY_POST_ENABLE 1
++#define BL_NOTIFY_PRE_DISABLE 2
++#define BL_NOTIFY_POST_DISABLE 3
++
++#ifdef CONFIG_BL_SWITCHER
++
++void bL_switch_request_detach(unsigned int cpu,
++ bL_switch_completion_handler completer);
++
++int bL_switcher_register_notifier(struct notifier_block *nb);
++int bL_switcher_unregister_notifier(struct notifier_block *nb);
++
++/*
++ * Use these functions to temporarily prevent enabling/disabling of
++ * the switcher.
++ * bL_switcher_get_enabled() returns true if the switcher is currently
++ * enabled. Each call to bL_switcher_get_enabled() must be followed
++ * by a call to bL_switcher_put_enabled(). These functions are not
++ * recursive.
++ */
++bool bL_switcher_get_enabled(void);
++void bL_switcher_put_enabled(void);
++
++int bL_switcher_trace_trigger(void);
++int bL_switcher_get_logical_index(u32 mpidr);
++
++#else
++static void bL_switch_request_detach(unsigned int cpu,
++ bL_switch_completion_handler completer) { }
++
++static inline int bL_switcher_register_notifier(struct notifier_block *nb)
++{
++ return 0;
++}
++
++static inline int bL_switcher_unregister_notifier(struct notifier_block *nb)
++{
++ return 0;
++}
++
++static inline bool bL_switcher_get_enabled(void) { return false; }
++static inline void bL_switcher_put_enabled(void) { }
++static inline int bL_switcher_trace_trigger(void) { return 0; }
++static inline int bL_switcher_get_logical_index(u32 mpidr) { return -EUNATCH; }
++#endif /* CONFIG_BL_SWITCHER */
++
++#endif
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/cacheflush.h linux-linaro-stable-mx6/arch/arm/include/asm/cacheflush.h
+--- linux-3.10.30.orig/arch/arm/include/asm/cacheflush.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/cacheflush.h 2014-05-15 20:33:34.393843699 +0200
+@@ -436,4 +436,50 @@
+ #define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr))
+ #define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr))
+
++/*
++ * Disabling cache access for one CPU in an ARMv7 SMP system is tricky.
++ * To do so we must:
++ *
++ * - Clear the SCTLR.C bit to prevent further cache allocations
++ * - Flush the desired level of cache
++ * - Clear the ACTLR "SMP" bit to disable local coherency
++ *
++ * ... and so without any intervening memory access in between those steps,
++ * not even to the stack.
++ *
++ * WARNING -- After this has been called:
++ *
++ * - No ldrex/strex (and similar) instructions must be used.
++ * - The CPU is obviously no longer coherent with the other CPUs.
++ * - This is unlikely to work as expected if Linux is running non-secure.
++ *
++ * Note:
++ *
++ * - This is known to apply to several ARMv7 processor implementations,
++ * however some exceptions may exist. Caveat emptor.
++ *
++ * - The clobber list is dictated by the call to v7_flush_dcache_*.
++ * fp is preserved to the stack explicitly prior disabling the cache
++ * since adding it to the clobber list is incompatible with having
++ * CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering
++ * trampoline are inserted by the linker and to keep sp 64-bit aligned.
++ */
++#define v7_exit_coherency_flush(level) \
++ asm volatile( \
++ "stmfd sp!, {fp, ip} \n\t" \
++ "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \
++ "bic r0, r0, #"__stringify(CR_C)" \n\t" \
++ "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \
++ "isb \n\t" \
++ "bl v7_flush_dcache_"__stringify(level)" \n\t" \
++ "clrex \n\t" \
++ "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR \n\t" \
++ "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \
++ "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
++ "isb \n\t" \
++ "dsb \n\t" \
++ "ldmfd sp!, {fp, ip}" \
++ : : : "r0","r1","r2","r3","r4","r5","r6","r7", \
++ "r9","r10","lr","memory" )
++
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/cp15.h linux-linaro-stable-mx6/arch/arm/include/asm/cp15.h
+--- linux-3.10.30.orig/arch/arm/include/asm/cp15.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/cp15.h 2014-05-15 20:33:34.393843699 +0200
+@@ -61,6 +61,20 @@
+ isb();
+ }
+
++static inline unsigned int get_auxcr(void)
++{
++ unsigned int val;
++ asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val));
++ return val;
++}
++
++static inline void set_auxcr(unsigned int val)
++{
++ asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
++ : : "r" (val));
++ isb();
++}
++
+ #ifndef CONFIG_SMP
+ extern void adjust_cr(unsigned long mask, unsigned long set);
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/glue-cache.h linux-linaro-stable-mx6/arch/arm/include/asm/glue-cache.h
+--- linux-3.10.30.orig/arch/arm/include/asm/glue-cache.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/glue-cache.h 2014-05-15 20:33:34.393843699 +0200
+@@ -102,19 +102,19 @@
+ #endif
+
+ #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
+-# ifdef _CACHE
++//# ifdef _CACHE
+ # define MULTI_CACHE 1
+-# else
+-# define _CACHE v6
+-# endif
++//# else
++//# define _CACHE v6
++//# endif
+ #endif
+
+ #if defined(CONFIG_CPU_V7)
+-# ifdef _CACHE
++//# ifdef _CACHE
+ # define MULTI_CACHE 1
+-# else
+-# define _CACHE v7
+-# endif
++//# else
++//# define _CACHE v7
++//# endif
+ #endif
+
+ #if !defined(_CACHE) && !defined(MULTI_CACHE)
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/hardirq.h linux-linaro-stable-mx6/arch/arm/include/asm/hardirq.h
+--- linux-3.10.30.orig/arch/arm/include/asm/hardirq.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/hardirq.h 2014-05-15 20:33:34.417843871 +0200
+@@ -5,7 +5,7 @@
+ #include <linux/threads.h>
+ #include <asm/irq.h>
+
+-#define NR_IPI 6
++#define NR_IPI 7
+
+ typedef struct {
+ unsigned int __softirq_pending;
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/mach/arch.h linux-linaro-stable-mx6/arch/arm/include/asm/mach/arch.h
+--- linux-3.10.30.orig/arch/arm/include/asm/mach/arch.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/mach/arch.h 2014-05-15 20:33:34.425843929 +0200
+@@ -8,6 +8,8 @@
+ * published by the Free Software Foundation.
+ */
+
++#include <linux/types.h>
++
+ #ifndef __ASSEMBLY__
+
+ struct tag;
+@@ -16,8 +18,10 @@
+ struct smp_operations;
+ #ifdef CONFIG_SMP
+ #define smp_ops(ops) (&(ops))
++#define smp_init_ops(ops) (&(ops))
+ #else
+ #define smp_ops(ops) (struct smp_operations *)NULL
++#define smp_init_ops(ops) (bool (*)(void))NULL
+ #endif
+
+ struct machine_desc {
+@@ -41,6 +45,7 @@
+ unsigned char reserve_lp2 :1; /* never has lp2 */
+ char restart_mode; /* default restart mode */
+ struct smp_operations *smp; /* SMP operations */
++ bool (*smp_init)(void);
+ void (*fixup)(struct tag *, char **,
+ struct meminfo *);
+ void (*reserve)(void);/* reserve mem blocks */
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/mach/pci.h linux-linaro-stable-mx6/arch/arm/include/asm/mach/pci.h
+--- linux-3.10.30.orig/arch/arm/include/asm/mach/pci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/mach/pci.h 2014-05-15 20:33:34.449844101 +0200
+@@ -35,6 +35,8 @@
+ resource_size_t start,
+ resource_size_t size,
+ resource_size_t align);
++ void (*add_bus)(struct pci_bus *bus);
++ void (*remove_bus)(struct pci_bus *bus);
+ };
+
+ /*
+@@ -62,6 +64,8 @@
+ resource_size_t start,
+ resource_size_t size,
+ resource_size_t align);
++ void (*add_bus)(struct pci_bus *bus);
++ void (*remove_bus)(struct pci_bus *bus);
+ void *private_data; /* platform controller private data */
+ };
+
+@@ -96,9 +100,4 @@
+ extern int via82c505_setup(int nr, struct pci_sys_data *);
+ extern void via82c505_init(void *sysdata);
+
+-extern struct pci_ops pci_v3_ops;
+-extern int pci_v3_setup(int nr, struct pci_sys_data *);
+-extern void pci_v3_preinit(void);
+-extern void pci_v3_postinit(void);
+-
+ #endif /* __ASM_MACH_PCI_H */
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/mcpm.h linux-linaro-stable-mx6/arch/arm/include/asm/mcpm.h
+--- linux-3.10.30.orig/arch/arm/include/asm/mcpm.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/mcpm.h 2014-05-15 20:33:34.449844101 +0200
+@@ -42,6 +42,14 @@
+ void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr);
+
+ /*
++ * This sets an early poke i.e a value to be poked into some address
++ * from very early assembly code before the CPU is ungated. The
++ * address must be physical, and if 0 then nothing will happen.
++ */
++void mcpm_set_early_poke(unsigned cpu, unsigned cluster,
++ unsigned long poke_phys_addr, unsigned long poke_val);
++
++/*
+ * CPU/cluster power operations API for higher subsystems to use.
+ */
+
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/pmu.h linux-linaro-stable-mx6/arch/arm/include/asm/pmu.h
+--- linux-3.10.30.orig/arch/arm/include/asm/pmu.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/pmu.h 2014-05-15 20:33:34.469844246 +0200
+@@ -62,9 +62,19 @@
+ raw_spinlock_t pmu_lock;
+ };
+
++struct cpupmu_regs {
++ u32 pmc;
++ u32 pmcntenset;
++ u32 pmuseren;
++ u32 pmintenset;
++ u32 pmxevttype[8];
++ u32 pmxevtcnt[8];
++};
++
+ struct arm_pmu {
+ struct pmu pmu;
+ cpumask_t active_irqs;
++ cpumask_t valid_cpus;
+ char *name;
+ irqreturn_t (*handle_irq)(int irq_num, void *dev);
+ void (*enable)(struct perf_event *event);
+@@ -81,6 +91,8 @@
+ int (*request_irq)(struct arm_pmu *, irq_handler_t handler);
+ void (*free_irq)(struct arm_pmu *);
+ int (*map_event)(struct perf_event *event);
++ void (*save_regs)(struct arm_pmu *, struct cpupmu_regs *);
++ void (*restore_regs)(struct arm_pmu *, struct cpupmu_regs *);
+ int num_events;
+ atomic_t active_events;
+ struct mutex reserve_mutex;
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/psci.h linux-linaro-stable-mx6/arch/arm/include/asm/psci.h
+--- linux-3.10.30.orig/arch/arm/include/asm/psci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/psci.h 2014-05-15 20:33:34.481844332 +0200
+@@ -16,6 +16,10 @@
+
+ #define PSCI_POWER_STATE_TYPE_STANDBY 0
+ #define PSCI_POWER_STATE_TYPE_POWER_DOWN 1
++#define PSCI_POWER_STATE_AFFINITY_LEVEL0 0
++#define PSCI_POWER_STATE_AFFINITY_LEVEL1 1
++#define PSCI_POWER_STATE_AFFINITY_LEVEL2 2
++#define PSCI_POWER_STATE_AFFINITY_LEVEL3 3
+
+ struct psci_power_state {
+ u16 id;
+@@ -32,5 +36,22 @@
+ };
+
+ extern struct psci_operations psci_ops;
++extern struct smp_operations psci_smp_ops;
+
++#ifdef CONFIG_ARM_PSCI
++void psci_init(void);
++bool psci_smp_available(void);
++#else
++static inline void psci_init(void) { }
++static inline bool psci_smp_available(void) { return false; }
++#endif
++
++#ifdef CONFIG_ARM_PSCI
++extern int __init psci_probe(void);
++#else
++static inline int psci_probe(void)
++{
++ return -ENODEV;
++}
++#endif
+ #endif /* __ASM_ARM_PSCI_H */
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/smp.h linux-linaro-stable-mx6/arch/arm/include/asm/smp.h
+--- linux-3.10.30.orig/arch/arm/include/asm/smp.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/smp.h 2014-05-15 20:33:34.481844332 +0200
+@@ -81,6 +81,8 @@
+ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+ extern void arch_send_wakeup_ipi_mask(const struct cpumask *mask);
+
++extern int register_ipi_completion(struct completion *completion, int cpu);
++
+ struct smp_operations {
+ #ifdef CONFIG_SMP
+ /*
+diff -Nur linux-3.10.30.orig/arch/arm/include/asm/topology.h linux-linaro-stable-mx6/arch/arm/include/asm/topology.h
+--- linux-3.10.30.orig/arch/arm/include/asm/topology.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/asm/topology.h 2014-05-15 20:33:34.481844332 +0200
+@@ -26,11 +26,45 @@
+ void init_cpu_topology(void);
+ void store_cpu_topology(unsigned int cpuid);
+ const struct cpumask *cpu_coregroup_mask(int cpu);
++int cluster_to_logical_mask(unsigned int socket_id, cpumask_t *cluster_mask);
++
++#ifdef CONFIG_DISABLE_CPU_SCHED_DOMAIN_BALANCE
++/* Common values for CPUs */
++#ifndef SD_CPU_INIT
++#define SD_CPU_INIT (struct sched_domain) { \
++ .min_interval = 1, \
++ .max_interval = 4, \
++ .busy_factor = 64, \
++ .imbalance_pct = 125, \
++ .cache_nice_tries = 1, \
++ .busy_idx = 2, \
++ .idle_idx = 1, \
++ .newidle_idx = 0, \
++ .wake_idx = 0, \
++ .forkexec_idx = 0, \
++ \
++ .flags = 0*SD_LOAD_BALANCE \
++ | 1*SD_BALANCE_NEWIDLE \
++ | 1*SD_BALANCE_EXEC \
++ | 1*SD_BALANCE_FORK \
++ | 0*SD_BALANCE_WAKE \
++ | 1*SD_WAKE_AFFINE \
++ | 0*SD_SHARE_CPUPOWER \
++ | 0*SD_SHARE_PKG_RESOURCES \
++ | 0*SD_SERIALIZE \
++ , \
++ .last_balance = jiffies, \
++ .balance_interval = 1, \
++}
++#endif
++#endif /* CONFIG_DISABLE_CPU_SCHED_DOMAIN_BALANCE */
+
+ #else
+
+ static inline void init_cpu_topology(void) { }
+ static inline void store_cpu_topology(unsigned int cpuid) { }
++static inline int cluster_to_logical_mask(unsigned int socket_id,
++ cpumask_t *cluster_mask) { return -EINVAL; }
+
+ #endif
+
+diff -Nur linux-3.10.30.orig/arch/arm/include/debug/imx-uart.h linux-linaro-stable-mx6/arch/arm/include/debug/imx-uart.h
+--- linux-3.10.30.orig/arch/arm/include/debug/imx-uart.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/debug/imx-uart.h 2014-05-15 20:33:34.493844419 +0200
+@@ -65,6 +65,14 @@
+ #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
+ #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
+
++#define IMX6SL_UART1_BASE_ADDR 0x02020000
++#define IMX6SL_UART2_BASE_ADDR 0x02024000
++#define IMX6SL_UART3_BASE_ADDR 0x02034000
++#define IMX6SL_UART4_BASE_ADDR 0x02038000
++#define IMX6SL_UART5_BASE_ADDR 0x02018000
++#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
++#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
++
+ #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
+
+ #ifdef CONFIG_DEBUG_IMX1_UART
+@@ -83,6 +91,8 @@
+ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
+ #elif defined(CONFIG_DEBUG_IMX6Q_UART)
+ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
++#elif defined(CONFIG_DEBUG_IMX6SL_UART)
++#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
+ #endif
+
+ #endif /* __DEBUG_IMX_UART_H */
+diff -Nur linux-3.10.30.orig/arch/arm/include/debug/vf.S linux-linaro-stable-mx6/arch/arm/include/debug/vf.S
+--- linux-3.10.30.orig/arch/arm/include/debug/vf.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/include/debug/vf.S 2014-05-15 20:33:34.513844563 +0200
+@@ -0,0 +1,26 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++ .macro addruart, rp, rv, tmp
++ ldr \rp, =0x40028000 @ physical
++ ldr \rv, =0xfe028000 @ virtual
++ .endm
++
++ .macro senduart, rd, rx
++ strb \rd, [\rx, #0x7] @ Data Register
++ .endm
++
++ .macro busyuart, rd, rx
++1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
++ tst \rd, #1 << 6 @ TC
++ beq 1001b @ wait until transmit done
++ .endm
++
++ .macro waituart,rd,rx
++ .endm
+diff -Nur linux-3.10.30.orig/arch/arm/Kconfig linux-linaro-stable-mx6/arch/arm/Kconfig
+--- linux-3.10.30.orig/arch/arm/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/Kconfig 2014-05-15 20:33:34.029841073 +0200
+@@ -1494,6 +1494,109 @@
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
++config DISABLE_CPU_SCHED_DOMAIN_BALANCE
++ bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
++ help
++ Disables scheduler load-balancing at CPU sched domain level.
++
++config SCHED_HMP
++ bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
++ depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
++ help
++ Experimental scheduler optimizations for heterogeneous platforms.
++ Attempts to introspectively select task affinity to optimize power
++ and performance. Basic support for multiple (>2) cpu types is in place,
++ but it has only been tested with two types of cpus.
++ There is currently no support for migration of task groups, hence
++ !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
++ between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
++ When turned on, this option adds sys/kernel/hmp directory which
++ contains the following files:
++ up_threshold - the load average threshold used for up migration
++ (0 - 1023)
++ down_threshold - the load average threshold used for down migration
++ (0 - 1023)
++ hmp_domains - a list of cpumasks for the present HMP domains,
++ starting with the 'biggest' and ending with the
++ 'smallest'.
++ Note that both the threshold files can be written at runtime to
++ control scheduler behaviour.
++
++config SCHED_HMP_PRIO_FILTER
++ bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
++ depends on SCHED_HMP
++ help
++ Enables task priority based HMP migration filter. Any task with
++ a NICE value above the threshold will always be on low-power cpus
++ with less compute capacity.
++
++config SCHED_HMP_PRIO_FILTER_VAL
++ int "NICE priority threshold"
++ default 5
++ depends on SCHED_HMP_PRIO_FILTER
++
++config HMP_FAST_CPU_MASK
++ string "HMP scheduler fast CPU mask"
++ depends on SCHED_HMP
++ help
++ Leave empty to use device tree information.
++ Specify the cpuids of the fast CPUs in the system as a list string,
++ e.g. cpuid 0+1 should be specified as 0-1.
++
++config HMP_SLOW_CPU_MASK
++ string "HMP scheduler slow CPU mask"
++ depends on SCHED_HMP
++ help
++ Leave empty to use device tree information.
++ Specify the cpuids of the slow CPUs in the system as a list string,
++ e.g. cpuid 0+1 should be specified as 0-1.
++
++config HMP_VARIABLE_SCALE
++ bool "Allows changing the load tracking scale through sysfs"
++ depends on SCHED_HMP
++ help
++ When turned on, this option exports the load average period value
++ for the load tracking patches through sysfs.
++ The values can be modified to change the rate of load accumulation
++ used for HMP migration. 'load_avg_period_ms' is the time in ms to
++ reach a load average of 0.5 for an idle task of 0 load average
++ ratio which becomes 100% busy.
++ For example, with load_avg_period_ms = 128 and up_threshold = 512,
++ a running task with a load of 0 will be migrated to a bigger CPU after
++ 128ms, because after 128ms its load_avg_ratio is 0.5 and the real
++ up_threshold is 0.5.
++ This patch has the same behavior as changing the Y of the load
++ average computation to
++ (1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
++ but removes intermediate overflows in computation.
++
++config HMP_FREQUENCY_INVARIANT_SCALE
++ bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
++ depends on SCHED_HMP && CPU_FREQ
++ help
++ Scales the current load contribution in line with the frequency
++ of the CPU that the task was executed on.
++ In this version, we use a simple linear scale derived from the
++ maximum frequency reported by CPUFreq.
++ Restricting tracked load to be scaled by the CPU's frequency
++ represents the consumption of possible compute capacity
++ (rather than consumption of actual instantaneous capacity as
++ normal) and allows the HMP migration's simple threshold
++ migration strategy to interact more predictably with CPUFreq's
++ asynchronous compute capacity changes.
++
++config SCHED_HMP_LITTLE_PACKING
++ bool "Small task packing for HMP"
++ depends on SCHED_HMP
++ default n
++ help
++ Allows the HMP Scheduler to pack small tasks into CPUs in the
++ smallest HMP domain.
++ Controlled by two sysfs files in sys/kernel/hmp.
++ packing_enable: 1 to enable, 0 to disable packing. Default 1.
++ packing_limit: runqueue load ratio where a RQ is considered
++ to be full. Default is NICE_0_LOAD * 9/8.
++
+ config HAVE_ARM_SCU
+ bool
+ help
+@@ -1521,6 +1624,31 @@
+ for (multi-)cluster based systems, such as big.LITTLE based
+ systems.
+
++config BIG_LITTLE
++ bool "big.LITTLE support (Experimental)"
++ depends on CPU_V7 && SMP
++ select MCPM
++ help
++ This option enables support for the big.LITTLE architecture.
++
++config BL_SWITCHER
++ bool "big.LITTLE switcher support"
++ depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
++ select CPU_PM
++ select ARM_CPU_SUSPEND
++ help
++ The big.LITTLE "switcher" provides the core functionality to
++ transparently handle transition between a cluster of A15's
++ and a cluster of A7's in a big.LITTLE system.
++
++config BL_SWITCHER_DUMMY_IF
++ tristate "Simple big.LITTLE switcher user interface"
++ depends on BL_SWITCHER && DEBUG_KERNEL
++ help
++ This is a simple and dummy char dev interface to control
++ the big.LITTLE switcher core code. It is meant for
++ debugging purposes only.
++
+ choice
+ prompt "Memory split"
+ default VMSPLIT_3G
+@@ -1738,6 +1866,7 @@
+ range 11 64 if ARCH_SHMOBILE
+ default "12" if SOC_AM33XX
+ default "9" if SA1111
++ default "14" if ARCH_MXC
+ default "11"
+ help
+ The kernel memory allocator divides physically contiguous memory
+diff -Nur linux-3.10.30.orig/arch/arm/Kconfig.debug linux-linaro-stable-mx6/arch/arm/Kconfig.debug
+--- linux-3.10.30.orig/arch/arm/Kconfig.debug 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/Kconfig.debug 2014-05-15 20:33:34.029841073 +0200
+@@ -251,6 +251,13 @@
+ Say Y here if you want kernel low-level debugging support
+ on i.MX6Q/DL.
+
++ config DEBUG_IMX6SL_UART
++ bool "i.MX6SL Debug UART"
++ depends on SOC_IMX6SL
++ help
++ Say Y here if you want kernel low-level debugging support
++ on i.MX6SL.
++
+ config DEBUG_MMP_UART2
+ bool "Kernel low-level debugging message via MMP UART2"
+ depends on ARCH_MMP
+@@ -309,6 +316,13 @@
+ Say Y here if you want kernel low-level debugging support
+ on MVEBU based platforms.
+
++ config DEBUG_VF_UART
++ bool "Vybrid UART"
++ depends on SOC_VF610
++ help
++ Say Y here if you want kernel low-level debugging support
++ on Vybrid based platforms.
++
+ config DEBUG_NOMADIK_UART
+ bool "Kernel low-level debugging messages via NOMADIK UART"
+ depends on ARCH_NOMADIK
+@@ -532,7 +546,8 @@
+ DEBUG_IMX35_UART || \
+ DEBUG_IMX51_UART || \
+ DEBUG_IMX53_UART || \
+- DEBUG_IMX6Q_UART
++ DEBUG_IMX6Q_UART || \
++ DEBUG_IMX6SL_UART
+ default 1
+ depends on ARCH_MXC
+ help
+@@ -631,7 +646,8 @@
+ DEBUG_IMX35_UART || \
+ DEBUG_IMX51_UART || \
+ DEBUG_IMX53_UART ||\
+- DEBUG_IMX6Q_UART
++ DEBUG_IMX6Q_UART || \
++ DEBUG_IMX6SL_UART
+ default "debug/mvebu.S" if DEBUG_MVEBU_UART
+ default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
+ default "debug/nomadik.S" if DEBUG_NOMADIK_UART
+@@ -646,6 +662,7 @@
+ default "debug/ux500.S" if DEBUG_UX500_UART
+ default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
+ DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
++ default "debug/vf.S" if DEBUG_VF_UART
+ default "debug/vt8500.S" if DEBUG_VT8500_UART0
+ default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
+ default "mach/debug-macro.S"
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/bios32.c linux-linaro-stable-mx6/arch/arm/kernel/bios32.c
+--- linux-3.10.30.orig/arch/arm/kernel/bios32.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/bios32.c 2014-05-15 20:33:34.521844622 +0200
+@@ -363,6 +363,20 @@
+ }
+ EXPORT_SYMBOL(pcibios_fixup_bus);
+
++void pcibios_add_bus(struct pci_bus *bus)
++{
++ struct pci_sys_data *sys = bus->sysdata;
++ if (sys->add_bus)
++ sys->add_bus(bus);
++}
++
++void pcibios_remove_bus(struct pci_bus *bus)
++{
++ struct pci_sys_data *sys = bus->sysdata;
++ if (sys->remove_bus)
++ sys->remove_bus(bus);
++}
++
+ /*
+ * Swizzle the device pin each time we cross a bridge. If a platform does
+ * not provide a swizzle function, we perform the standard PCI swizzling.
+@@ -463,6 +477,8 @@
+ sys->swizzle = hw->swizzle;
+ sys->map_irq = hw->map_irq;
+ sys->align_resource = hw->align_resource;
++ sys->add_bus = hw->add_bus;
++ sys->remove_bus = hw->remove_bus;
+ INIT_LIST_HEAD(&sys->resources);
+
+ if (hw->private_data)
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/head.S linux-linaro-stable-mx6/arch/arm/kernel/head.S
+--- linux-3.10.30.orig/arch/arm/kernel/head.S 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/head.S 2014-05-15 20:33:34.545844794 +0200
+@@ -342,7 +342,6 @@
+ .long __turn_mmu_on_end
+
+ #if defined(CONFIG_SMP)
+- __CPUINIT
+ ENTRY(secondary_startup)
+ /*
+ * Common entry point for secondary CPUs.
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/hw_breakpoint.c linux-linaro-stable-mx6/arch/arm/kernel/hw_breakpoint.c
+--- linux-3.10.30.orig/arch/arm/kernel/hw_breakpoint.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/hw_breakpoint.c 2014-05-15 20:33:34.545844794 +0200
+@@ -1049,7 +1049,8 @@
+
+ static void __init pm_init(void)
+ {
+- cpu_pm_register_notifier(&dbg_cpu_pm_nb);
++ if (has_ossr)
++ cpu_pm_register_notifier(&dbg_cpu_pm_nb);
+ }
+ #else
+ static inline void pm_init(void)
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/Makefile linux-linaro-stable-mx6/arch/arm/kernel/Makefile
+--- linux-3.10.30.orig/arch/arm/kernel/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/Makefile 2014-05-15 20:33:34.517844592 +0200
+@@ -82,6 +82,9 @@
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+
+ obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o
+-obj-$(CONFIG_ARM_PSCI) += psci.o
++ifeq ($(CONFIG_ARM_PSCI),y)
++obj-y += psci.o
++obj-$(CONFIG_SMP) += psci_smp.o
++endif
+
+ extra-y := $(head-y) vmlinux.lds
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/perf_event.c linux-linaro-stable-mx6/arch/arm/kernel/perf_event.c
+--- linux-3.10.30.orig/arch/arm/kernel/perf_event.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/perf_event.c 2014-05-15 20:33:34.589845112 +0200
+@@ -12,6 +12,7 @@
+ */
+ #define pr_fmt(fmt) "hw perfevents: " fmt
+
++#include <linux/cpumask.h>
+ #include <linux/kernel.h>
+ #include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+@@ -86,6 +87,9 @@
+ return armpmu_map_cache_event(cache_map, config);
+ case PERF_TYPE_RAW:
+ return armpmu_map_raw_event(raw_event_mask, config);
++ default:
++ if (event->attr.type >= PERF_TYPE_MAX)
++ return armpmu_map_raw_event(raw_event_mask, config);
+ }
+
+ return -ENOENT;
+@@ -163,6 +167,8 @@
+ struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
++ if (!cpumask_test_cpu(smp_processor_id(), &armpmu->valid_cpus))
++ return;
+ /*
+ * ARM pmu always has to update the counter, so ignore
+ * PERF_EF_UPDATE, see comments in armpmu_start().
+@@ -179,6 +185,8 @@
+ struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
+ struct hw_perf_event *hwc = &event->hw;
+
++ if (!cpumask_test_cpu(smp_processor_id(), &armpmu->valid_cpus))
++ return;
+ /*
+ * ARM pmu always has to reprogram the period, so ignore
+ * PERF_EF_RELOAD, see the comment below.
+@@ -206,6 +214,9 @@
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
++ if (!cpumask_test_cpu(smp_processor_id(), &armpmu->valid_cpus))
++ return;
++
+ armpmu_stop(event, PERF_EF_UPDATE);
+ hw_events->events[idx] = NULL;
+ clear_bit(idx, hw_events->used_mask);
+@@ -222,6 +233,10 @@
+ int idx;
+ int err = 0;
+
++ /* An event following a process won't be stopped earlier */
++ if (!cpumask_test_cpu(smp_processor_id(), &armpmu->valid_cpus))
++ return 0;
++
+ perf_pmu_disable(event->pmu);
+
+ /* If we don't have a space for the counter then finish early. */
+@@ -424,6 +439,10 @@
+ int err = 0;
+ atomic_t *active_events = &armpmu->active_events;
+
++ if (event->cpu != -1 &&
++ !cpumask_test_cpu(event->cpu, &armpmu->valid_cpus))
++ return -ENOENT;
++
+ /* does not support taken branch sampling */
+ if (has_branch_stack(event))
+ return -EOPNOTSUPP;
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/perf_event_cpu.c linux-linaro-stable-mx6/arch/arm/kernel/perf_event_cpu.c
+--- linux-3.10.30.orig/arch/arm/kernel/perf_event_cpu.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/perf_event_cpu.c 2014-05-15 20:33:34.589845112 +0200
+@@ -19,6 +19,7 @@
+ #define pr_fmt(fmt) "CPU PMU: " fmt
+
+ #include <linux/bitmap.h>
++#include <linux/cpu_pm.h>
+ #include <linux/export.h>
+ #include <linux/kernel.h>
+ #include <linux/of.h>
+@@ -31,33 +32,36 @@
+ #include <asm/pmu.h>
+
+ /* Set at runtime when we know what CPU type we are. */
+-static struct arm_pmu *cpu_pmu;
++static DEFINE_PER_CPU(struct arm_pmu *, cpu_pmu);
+
+ static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+ static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+ static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
+
++static DEFINE_PER_CPU(struct cpupmu_regs, cpu_pmu_regs);
++
+ /*
+ * Despite the names, these two functions are CPU-specific and are used
+ * by the OProfile/perf code.
+ */
+ const char *perf_pmu_name(void)
+ {
+- if (!cpu_pmu)
++ struct arm_pmu *pmu = per_cpu(cpu_pmu, 0);
++ if (!pmu)
+ return NULL;
+
+- return cpu_pmu->name;
++ return pmu->name;
+ }
+ EXPORT_SYMBOL_GPL(perf_pmu_name);
+
+ int perf_num_counters(void)
+ {
+- int max_events = 0;
++ struct arm_pmu *pmu = per_cpu(cpu_pmu, 0);
+
+- if (cpu_pmu != NULL)
+- max_events = cpu_pmu->num_events;
++ if (!pmu)
++ return 0;
+
+- return max_events;
++ return pmu->num_events;
+ }
+ EXPORT_SYMBOL_GPL(perf_num_counters);
+
+@@ -75,11 +79,13 @@
+ {
+ int i, irq, irqs;
+ struct platform_device *pmu_device = cpu_pmu->plat_device;
++ int cpu = -1;
+
+ irqs = min(pmu_device->num_resources, num_possible_cpus());
+
+ for (i = 0; i < irqs; ++i) {
+- if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
++ cpu = cpumask_next(cpu, &cpu_pmu->valid_cpus);
++ if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
+ continue;
+ irq = platform_get_irq(pmu_device, i);
+ if (irq >= 0)
+@@ -91,6 +97,7 @@
+ {
+ int i, err, irq, irqs;
+ struct platform_device *pmu_device = cpu_pmu->plat_device;
++ int cpu = -1;
+
+ if (!pmu_device)
+ return -ENODEV;
+@@ -103,6 +110,7 @@
+
+ for (i = 0; i < irqs; ++i) {
+ err = 0;
++ cpu = cpumask_next(cpu, &cpu_pmu->valid_cpus);
+ irq = platform_get_irq(pmu_device, i);
+ if (irq < 0)
+ continue;
+@@ -112,7 +120,7 @@
+ * assume that we're running on a uniprocessor machine and
+ * continue. Otherwise, continue without this interrupt.
+ */
+- if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
++ if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
+ pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+ irq, i);
+ continue;
+@@ -126,7 +134,7 @@
+ return err;
+ }
+
+- cpumask_set_cpu(i, &cpu_pmu->active_irqs);
++ cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
+ }
+
+ return 0;
+@@ -135,7 +143,7 @@
+ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
+ {
+ int cpu;
+- for_each_possible_cpu(cpu) {
++ for_each_cpu_mask(cpu, cpu_pmu->valid_cpus) {
+ struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+ events->events = per_cpu(hw_events, cpu);
+ events->used_mask = per_cpu(used_mask, cpu);
+@@ -148,7 +156,7 @@
+
+ /* Ensure the PMU has sane values out of reset. */
+ if (cpu_pmu->reset)
+- on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
++ on_each_cpu_mask(&cpu_pmu->valid_cpus, cpu_pmu->reset, cpu_pmu, 1);
+ }
+
+ /*
+@@ -160,21 +168,46 @@
+ static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+ unsigned long action, void *hcpu)
+ {
++ struct arm_pmu *pmu = per_cpu(cpu_pmu, (long)hcpu);
++
+ if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+ return NOTIFY_DONE;
+
+- if (cpu_pmu && cpu_pmu->reset)
+- cpu_pmu->reset(cpu_pmu);
++ if (pmu && pmu->reset)
++ pmu->reset(pmu);
+ else
+ return NOTIFY_DONE;
+
+ return NOTIFY_OK;
+ }
+
++static int cpu_pmu_pm_notify(struct notifier_block *b,
++ unsigned long action, void *hcpu)
++{
++ int cpu = smp_processor_id();
++ struct arm_pmu *pmu = per_cpu(cpu_pmu, cpu);
++ struct cpupmu_regs *pmuregs = &per_cpu(cpu_pmu_regs, cpu);
++
++ if (!pmu)
++ return NOTIFY_DONE;
++
++ if (action == CPU_PM_ENTER && pmu->save_regs) {
++ pmu->save_regs(pmu, pmuregs);
++ } else if (action == CPU_PM_EXIT && pmu->restore_regs) {
++ pmu->restore_regs(pmu, pmuregs);
++ }
++
++ return NOTIFY_OK;
++}
++
+ static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+ .notifier_call = cpu_pmu_notify,
+ };
+
++static struct notifier_block __cpuinitdata cpu_pmu_pm_notifier = {
++ .notifier_call = cpu_pmu_pm_notify,
++};
++
+ /*
+ * PMU platform driver and devicetree bindings.
+ */
+@@ -246,6 +279,9 @@
+ }
+ }
+
++ /* assume PMU support all the CPUs in this case */
++ cpumask_setall(&pmu->valid_cpus);
++
+ put_cpu();
+ return ret;
+ }
+@@ -253,15 +289,10 @@
+ static int cpu_pmu_device_probe(struct platform_device *pdev)
+ {
+ const struct of_device_id *of_id;
+- int (*init_fn)(struct arm_pmu *);
+ struct device_node *node = pdev->dev.of_node;
+ struct arm_pmu *pmu;
+- int ret = -ENODEV;
+-
+- if (cpu_pmu) {
+- pr_info("attempt to register multiple PMU devices!");
+- return -ENOSPC;
+- }
++ int ret = 0;
++ int cpu;
+
+ pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
+ if (!pmu) {
+@@ -270,8 +301,28 @@
+ }
+
+ if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
+- init_fn = of_id->data;
+- ret = init_fn(pmu);
++ smp_call_func_t init_fn = (smp_call_func_t)of_id->data;
++ struct device_node *ncluster;
++ int cluster = -1;
++ cpumask_t sibling_mask;
++
++ ncluster = of_parse_phandle(node, "cluster", 0);
++ if (ncluster) {
++ int len;
++ const u32 *hwid;
++ hwid = of_get_property(ncluster, "reg", &len);
++ if (hwid && len == 4)
++ cluster = be32_to_cpup(hwid);
++ }
++ /* set sibling mask to all cpu mask if socket is not specified */
++ if (cluster == -1 ||
++ cluster_to_logical_mask(cluster, &sibling_mask))
++ cpumask_setall(&sibling_mask);
++
++ smp_call_function_any(&sibling_mask, init_fn, pmu, 1);
++
++ /* now set the valid_cpus after init */
++ cpumask_copy(&pmu->valid_cpus, &sibling_mask);
+ } else {
+ ret = probe_current_pmu(pmu);
+ }
+@@ -281,10 +332,12 @@
+ goto out_free;
+ }
+
+- cpu_pmu = pmu;
+- cpu_pmu->plat_device = pdev;
+- cpu_pmu_init(cpu_pmu);
+- ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
++ for_each_cpu_mask(cpu, pmu->valid_cpus)
++ per_cpu(cpu_pmu, cpu) = pmu;
++
++ pmu->plat_device = pdev;
++ cpu_pmu_init(pmu);
++ ret = armpmu_register(pmu, -1);
+
+ if (!ret)
+ return 0;
+@@ -313,9 +366,17 @@
+ if (err)
+ return err;
+
++ err = cpu_pm_register_notifier(&cpu_pmu_pm_notifier);
++ if (err) {
++ unregister_cpu_notifier(&cpu_pmu_hotplug_notifier);
++ return err;
++ }
++
+ err = platform_driver_register(&cpu_pmu_driver);
+- if (err)
++ if (err) {
++ cpu_pm_unregister_notifier(&cpu_pmu_pm_notifier);
+ unregister_cpu_notifier(&cpu_pmu_hotplug_notifier);
++ }
+
+ return err;
+ }
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/perf_event_v7.c linux-linaro-stable-mx6/arch/arm/kernel/perf_event_v7.c
+--- linux-3.10.30.orig/arch/arm/kernel/perf_event_v7.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/perf_event_v7.c 2014-05-15 20:33:34.589845112 +0200
+@@ -950,6 +950,51 @@
+ }
+ #endif
+
++static void armv7pmu_save_regs(struct arm_pmu *cpu_pmu,
++ struct cpupmu_regs *regs)
++{
++ unsigned int cnt;
++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (regs->pmc));
++ if (!(regs->pmc & ARMV7_PMNC_E))
++ return;
++
++ asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (regs->pmcntenset));
++ asm volatile("mrc p15, 0, %0, c9, c14, 0" : "=r" (regs->pmuseren));
++ asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (regs->pmintenset));
++ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (regs->pmxevtcnt[0]));
++ for (cnt = ARMV7_IDX_COUNTER0;
++ cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) {
++ armv7_pmnc_select_counter(cnt);
++ asm volatile("mrc p15, 0, %0, c9, c13, 1"
++ : "=r"(regs->pmxevttype[cnt]));
++ asm volatile("mrc p15, 0, %0, c9, c13, 2"
++ : "=r"(regs->pmxevtcnt[cnt]));
++ }
++ return;
++}
++
++static void armv7pmu_restore_regs(struct arm_pmu *cpu_pmu,
++ struct cpupmu_regs *regs)
++{
++ unsigned int cnt;
++ if (!(regs->pmc & ARMV7_PMNC_E))
++ return;
++
++ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (regs->pmcntenset));
++ asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r" (regs->pmuseren));
++ asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (regs->pmintenset));
++ asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (regs->pmxevtcnt[0]));
++ for (cnt = ARMV7_IDX_COUNTER0;
++ cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) {
++ armv7_pmnc_select_counter(cnt);
++ asm volatile("mcr p15, 0, %0, c9, c13, 1"
++ : : "r"(regs->pmxevttype[cnt]));
++ asm volatile("mcr p15, 0, %0, c9, c13, 2"
++ : : "r"(regs->pmxevtcnt[cnt]));
++ }
++ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (regs->pmc));
++}
++
+ static void armv7pmu_enable_event(struct perf_event *event)
+ {
+ unsigned long flags;
+@@ -1223,6 +1268,8 @@
+ cpu_pmu->start = armv7pmu_start;
+ cpu_pmu->stop = armv7pmu_stop;
+ cpu_pmu->reset = armv7pmu_reset;
++ cpu_pmu->save_regs = armv7pmu_save_regs;
++ cpu_pmu->restore_regs = armv7pmu_restore_regs;
+ cpu_pmu->max_period = (1LLU << 32) - 1;
+ };
+
+@@ -1240,7 +1287,7 @@
+ static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu)
+ {
+ armv7pmu_init(cpu_pmu);
+- cpu_pmu->name = "ARMv7 Cortex-A8";
++ cpu_pmu->name = "ARMv7_Cortex_A8";
+ cpu_pmu->map_event = armv7_a8_map_event;
+ cpu_pmu->num_events = armv7_read_num_pmnc_events();
+ return 0;
+@@ -1249,7 +1296,7 @@
+ static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu)
+ {
+ armv7pmu_init(cpu_pmu);
+- cpu_pmu->name = "ARMv7 Cortex-A9";
++ cpu_pmu->name = "ARMv7_Cortex_A9";
+ cpu_pmu->map_event = armv7_a9_map_event;
+ cpu_pmu->num_events = armv7_read_num_pmnc_events();
+ return 0;
+@@ -1258,7 +1305,7 @@
+ static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu)
+ {
+ armv7pmu_init(cpu_pmu);
+- cpu_pmu->name = "ARMv7 Cortex-A5";
++ cpu_pmu->name = "ARMv7_Cortex_A5";
+ cpu_pmu->map_event = armv7_a5_map_event;
+ cpu_pmu->num_events = armv7_read_num_pmnc_events();
+ return 0;
+@@ -1267,7 +1314,7 @@
+ static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu)
+ {
+ armv7pmu_init(cpu_pmu);
+- cpu_pmu->name = "ARMv7 Cortex-A15";
++ cpu_pmu->name = "ARMv7_Cortex_A15";
+ cpu_pmu->map_event = armv7_a15_map_event;
+ cpu_pmu->num_events = armv7_read_num_pmnc_events();
+ cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
+@@ -1277,7 +1324,7 @@
+ static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu)
+ {
+ armv7pmu_init(cpu_pmu);
+- cpu_pmu->name = "ARMv7 Cortex-A7";
++ cpu_pmu->name = "ARMv7_Cortex_A7";
+ cpu_pmu->map_event = armv7_a7_map_event;
+ cpu_pmu->num_events = armv7_read_num_pmnc_events();
+ cpu_pmu->set_event_filter = armv7pmu_set_event_filter;
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/process.c linux-linaro-stable-mx6/arch/arm/kernel/process.c
+--- linux-3.10.30.orig/arch/arm/kernel/process.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/process.c 2014-05-15 20:33:34.589845112 +0200
+@@ -170,8 +170,10 @@
+ */
+ void arch_cpu_idle(void)
+ {
++ idle_notifier_call_chain(IDLE_START);
+ if (cpuidle_idle_call())
+ default_idle();
++ idle_notifier_call_chain(IDLE_END);
+ }
+
+ static char reboot_mode = 'h';
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/psci.c linux-linaro-stable-mx6/arch/arm/kernel/psci.c
+--- linux-3.10.30.orig/arch/arm/kernel/psci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/psci.c 2014-05-15 20:33:34.609845255 +0200
+@@ -17,6 +17,7 @@
+
+ #include <linux/init.h>
+ #include <linux/of.h>
++#include <linux/string.h>
+
+ #include <asm/compiler.h>
+ #include <asm/errno.h>
+@@ -26,6 +27,11 @@
+
+ struct psci_operations psci_ops;
+
++/* Type of psci support. Currently can only be enabled or disabled */
++#define PSCI_SUP_DISABLED 0
++#define PSCI_SUP_ENABLED 1
++
++static unsigned int psci;
+ static int (*invoke_psci_fn)(u32, u32, u32, u32);
+
+ enum psci_function {
+@@ -42,6 +48,7 @@
+ #define PSCI_RET_EOPNOTSUPP -1
+ #define PSCI_RET_EINVAL -2
+ #define PSCI_RET_EPERM -3
++#define PSCI_RET_EALREADYON -4
+
+ static int psci_to_linux_errno(int errno)
+ {
+@@ -54,6 +61,8 @@
+ return -EINVAL;
+ case PSCI_RET_EPERM:
+ return -EPERM;
++ case PSCI_RET_EALREADYON:
++ return -EAGAIN;
+ };
+
+ return -EINVAL;
+@@ -158,15 +167,18 @@
+ {},
+ };
+
+-static int __init psci_init(void)
++void __init psci_init(void)
+ {
+ struct device_node *np;
+ const char *method;
+ u32 id;
+
++ if (psci == PSCI_SUP_DISABLED)
++ return;
++
+ np = of_find_matching_node(NULL, psci_of_match);
+ if (!np)
+- return 0;
++ return;
+
+ pr_info("probing function IDs from device-tree\n");
+
+@@ -206,6 +218,35 @@
+
+ out_put_node:
+ of_node_put(np);
+- return 0;
++ return;
++}
++
++int __init psci_probe(void)
++{
++ struct device_node *np;
++ int ret = -ENODEV;
++
++ if (psci == PSCI_SUP_ENABLED) {
++ np = of_find_matching_node(NULL, psci_of_match);
++ if (np)
++ ret = 0;
++ }
++
++ of_node_put(np);
++ return ret;
++}
++
++static int __init early_psci(char *val)
++{
++ int ret = 0;
++
++ if (strcmp(val, "enable") == 0)
++ psci = PSCI_SUP_ENABLED;
++ else if (strcmp(val, "disable") == 0)
++ psci = PSCI_SUP_DISABLED;
++ else
++ ret = -EINVAL;
++
++ return ret;
+ }
+-early_initcall(psci_init);
++early_param("psci", early_psci);
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/psci_smp.c linux-linaro-stable-mx6/arch/arm/kernel/psci_smp.c
+--- linux-3.10.30.orig/arch/arm/kernel/psci_smp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/psci_smp.c 2014-05-15 20:33:34.609845255 +0200
+@@ -0,0 +1,84 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Copyright (C) 2012 ARM Limited
++ *
++ * Author: Will Deacon <will.deacon@arm.com>
++ */
++
++#include <linux/init.h>
++#include <linux/irqchip/arm-gic.h>
++#include <linux/smp.h>
++#include <linux/of.h>
++
++#include <asm/psci.h>
++#include <asm/smp_plat.h>
++
++/*
++ * psci_smp assumes that the following is true about PSCI:
++ *
++ * cpu_suspend Suspend the execution on a CPU
++ * @state we don't currently describe affinity levels, so just pass 0.
++ * @entry_point the first instruction to be executed on return
++ * returns 0 success, < 0 on failure
++ *
++ * cpu_off Power down a CPU
++ * @state we don't currently describe affinity levels, so just pass 0.
++ * no return on successful call
++ *
++ * cpu_on Power up a CPU
++ * @cpuid cpuid of target CPU, as from MPIDR
++ * @entry_point the first instruction to be executed on return
++ * returns 0 success, < 0 on failure
++ *
++ * migrate Migrate the context to a different CPU
++ * @cpuid cpuid of target CPU, as from MPIDR
++ * returns 0 success, < 0 on failure
++ *
++ */
++
++extern void secondary_startup(void);
++
++static int __cpuinit psci_boot_secondary(unsigned int cpu,
++ struct task_struct *idle)
++{
++ if (psci_ops.cpu_on)
++ return psci_ops.cpu_on(cpu_logical_map(cpu),
++ __pa(secondary_startup));
++ return -ENODEV;
++}
++
++#ifdef CONFIG_HOTPLUG_CPU
++void __ref psci_cpu_die(unsigned int cpu)
++{
++ const struct psci_power_state ps = {
++ .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
++ };
++
++ if (psci_ops.cpu_off)
++ psci_ops.cpu_off(ps);
++
++ /* We should never return */
++ panic("psci: cpu %d failed to shutdown\n", cpu);
++}
++#else
++#define psci_cpu_die NULL
++#endif
++
++bool __init psci_smp_available(void)
++{
++ /* is cpu_on available at least? */
++ return (psci_ops.cpu_on != NULL);
++}
++
++struct smp_operations __initdata psci_smp_ops = {
++ .smp_boot_secondary = psci_boot_secondary,
++ .cpu_die = psci_cpu_die,
++};
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/setup.c linux-linaro-stable-mx6/arch/arm/kernel/setup.c
+--- linux-3.10.30.orig/arch/arm/kernel/setup.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/setup.c 2014-05-15 20:33:34.613845284 +0200
+@@ -37,6 +37,7 @@
+ #include <asm/cputype.h>
+ #include <asm/elf.h>
+ #include <asm/procinfo.h>
++#include <asm/psci.h>
+ #include <asm/sections.h>
+ #include <asm/setup.h>
+ #include <asm/smp_plat.h>
+@@ -261,6 +262,19 @@
+ int aliasing_icache;
+ unsigned int id_reg, num_sets, line_size;
+
++#ifdef CONFIG_BIG_LITTLE
++ /*
++ * We expect a combination of Cortex-A15 and Cortex-A7 cores.
++ * A7 = VIPT aliasing I-cache
++ * A15 = PIPT (non-aliasing) I-cache
++ * To cater for this discrepancy, let's assume aliasing I-cache
++ * all the time. This means unneeded extra work on the A15 but
++ * only ptrace is affected which is not performance critical.
++ */
++ if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc0f0)
++ return 1;
++#endif
++
+ /* PIPT caches never alias. */
+ if (icache_is_pipt())
+ return 0;
+@@ -796,9 +810,15 @@
+ unflatten_device_tree();
+
+ arm_dt_init_cpu_maps();
++ psci_init();
+ #ifdef CONFIG_SMP
+ if (is_smp()) {
+- smp_set_ops(mdesc->smp);
++ if (!mdesc->smp_init || !mdesc->smp_init()) {
++ if (psci_smp_available())
++ smp_set_ops(&psci_smp_ops);
++ else if (mdesc->smp)
++ smp_set_ops(mdesc->smp);
++ }
+ smp_init_cpus();
+ }
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/sleep.S linux-linaro-stable-mx6/arch/arm/kernel/sleep.S
+--- linux-3.10.30.orig/arch/arm/kernel/sleep.S 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/sleep.S 2014-05-15 20:33:34.613845284 +0200
+@@ -4,6 +4,7 @@
+ #include <asm/assembler.h>
+ #include <asm/glue-cache.h>
+ #include <asm/glue-proc.h>
++#include "entry-header.S"
+ .text
+
+ /*
+@@ -30,9 +31,8 @@
+ mov r2, r5 @ virtual SP
+ ldr r3, =sleep_save_sp
+ #ifdef CONFIG_SMP
+- ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
+- ALT_UP(mov lr, #0)
+- and lr, lr, #15
++ get_thread_info r5
++ ldr lr, [r5, #TI_CPU] @ cpu logical index
+ add r3, r3, lr, lsl #2
+ #endif
+ bl __cpu_suspend_save
+@@ -82,10 +82,13 @@
+ .align
+ ENTRY(cpu_resume)
+ #ifdef CONFIG_SMP
++ mov r1, #0 @ fall-back logical index for UP
++ ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
++ ALT_UP_B(1f)
++ bic r0, #0xff000000
++ bl cpu_logical_index @ return logical index in r1
++1:
+ adr r0, sleep_save_sp
+- ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
+- ALT_UP(mov r1, #0)
+- and r1, r1, #15
+ ldr r0, [r0, r1, lsl #2] @ stack phys addr
+ #else
+ ldr r0, sleep_save_sp @ stack phys addr
+@@ -102,3 +105,20 @@
+ .rept CONFIG_NR_CPUS
+ .long 0 @ preserve stack phys ptr here
+ .endr
++
++#ifdef CONFIG_SMP
++cpu_logical_index:
++ adr r3, cpu_map_ptr
++ ldr r2, [r3]
++ add r3, r3, r2 @ virt_to_phys(__cpu_logical_map)
++ mov r1, #0
++1:
++ ldr r2, [r3, r1, lsl #2]
++ cmp r2, r0
++ moveq pc, lr
++ add r1, r1, #1
++ b 1b
++
++cpu_map_ptr:
++ .long __cpu_logical_map - .
++#endif
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/smp.c linux-linaro-stable-mx6/arch/arm/kernel/smp.c
+--- linux-3.10.30.orig/arch/arm/kernel/smp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/smp.c 2014-05-15 20:33:34.613845284 +0200
+@@ -46,6 +46,9 @@
+ #include <asm/virt.h>
+ #include <asm/mach/arch.h>
+
++#define CREATE_TRACE_POINTS
++#include <trace/events/arm-ipi.h>
++
+ /*
+ * as from 2.5, kernels no longer have an init_tasks structure
+ * so we need some other way of telling a new secondary core
+@@ -57,7 +60,7 @@
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+-volatile int __cpuinitdata pen_release = -1;
++volatile int pen_release = -1;
+
+ enum ipi_msg_type {
+ IPI_WAKEUP,
+@@ -66,6 +69,7 @@
+ IPI_CALL_FUNC,
+ IPI_CALL_FUNC_SINGLE,
+ IPI_CPU_STOP,
++ IPI_COMPLETION,
+ };
+
+ static DECLARE_COMPLETION(cpu_running);
+@@ -463,6 +467,7 @@
+ S(IPI_CALL_FUNC, "Function call interrupts"),
+ S(IPI_CALL_FUNC_SINGLE, "Single function call interrupts"),
+ S(IPI_CPU_STOP, "CPU stop interrupts"),
++ S(IPI_COMPLETION, "completion interrupts"),
+ };
+
+ void show_ipi_list(struct seq_file *p, int prec)
+@@ -588,6 +593,19 @@
+ cpu_relax();
+ }
+
++static DEFINE_PER_CPU(struct completion *, cpu_completion);
++
++int register_ipi_completion(struct completion *completion, int cpu)
++{
++ per_cpu(cpu_completion, cpu) = completion;
++ return IPI_COMPLETION;
++}
++
++static void ipi_complete(unsigned int cpu)
++{
++ complete(per_cpu(cpu_completion, cpu));
++}
++
+ /*
+ * Main handler for inter-processor interrupts
+ */
+@@ -604,6 +622,7 @@
+ if (ipinr < NR_IPI)
+ __inc_irq_stat(cpu, ipi_irqs[ipinr]);
+
++ trace_arm_ipi_entry(ipinr);
+ switch (ipinr) {
+ case IPI_WAKEUP:
+ break;
+@@ -638,11 +657,18 @@
+ irq_exit();
+ break;
+
++ case IPI_COMPLETION:
++ irq_enter();
++ ipi_complete(cpu);
++ irq_exit();
++ break;
++
+ default:
+ printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%x\n",
+ cpu, ipinr);
+ break;
+ }
++ trace_arm_ipi_exit(ipinr);
+ set_irq_regs(old_regs);
+ }
+
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/topology.c linux-linaro-stable-mx6/arch/arm/kernel/topology.c
+--- linux-3.10.30.orig/arch/arm/kernel/topology.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/topology.c 2014-05-15 20:33:34.665845660 +0200
+@@ -23,6 +23,7 @@
+ #include <linux/slab.h>
+
+ #include <asm/cputype.h>
++#include <asm/smp_plat.h>
+ #include <asm/topology.h>
+
+ /*
+@@ -289,6 +290,140 @@
+ cpu_topology[cpuid].socket_id, mpidr);
+ }
+
++
++#ifdef CONFIG_SCHED_HMP
++
++static const char * const little_cores[] = {
++ "arm,cortex-a7",
++ NULL,
++};
++
++static bool is_little_cpu(struct device_node *cn)
++{
++ const char * const *lc;
++ for (lc = little_cores; *lc; lc++)
++ if (of_device_is_compatible(cn, *lc))
++ return true;
++ return false;
++}
++
++void __init arch_get_fast_and_slow_cpus(struct cpumask *fast,
++ struct cpumask *slow)
++{
++ struct device_node *cn = NULL;
++ int cpu;
++
++ cpumask_clear(fast);
++ cpumask_clear(slow);
++
++ /*
++ * Use the config options if they are given. This helps testing
++ * HMP scheduling on systems without a big.LITTLE architecture.
++ */
++ if (strlen(CONFIG_HMP_FAST_CPU_MASK) && strlen(CONFIG_HMP_SLOW_CPU_MASK)) {
++ if (cpulist_parse(CONFIG_HMP_FAST_CPU_MASK, fast))
++ WARN(1, "Failed to parse HMP fast cpu mask!\n");
++ if (cpulist_parse(CONFIG_HMP_SLOW_CPU_MASK, slow))
++ WARN(1, "Failed to parse HMP slow cpu mask!\n");
++ return;
++ }
++
++ /*
++ * Else, parse device tree for little cores.
++ */
++ while ((cn = of_find_node_by_type(cn, "cpu"))) {
++
++ const u32 *mpidr;
++ int len;
++
++ mpidr = of_get_property(cn, "reg", &len);
++ if (!mpidr || len != 4) {
++ pr_err("* %s missing reg property\n", cn->full_name);
++ continue;
++ }
++
++ cpu = get_logical_index(be32_to_cpup(mpidr));
++ if (cpu == -EINVAL) {
++ pr_err("couldn't get logical index for mpidr %x\n",
++ be32_to_cpup(mpidr));
++ break;
++ }
++
++ if (is_little_cpu(cn))
++ cpumask_set_cpu(cpu, slow);
++ else
++ cpumask_set_cpu(cpu, fast);
++ }
++
++ if (!cpumask_empty(fast) && !cpumask_empty(slow))
++ return;
++
++ /*
++ * We didn't find both big and little cores so let's call all cores
++ * fast as this will keep the system running, with all cores being
++ * treated equal.
++ */
++ cpumask_setall(fast);
++ cpumask_clear(slow);
++}
++
++struct cpumask hmp_slow_cpu_mask;
++
++void __init arch_get_hmp_domains(struct list_head *hmp_domains_list)
++{
++ struct cpumask hmp_fast_cpu_mask;
++ struct hmp_domain *domain;
++
++ arch_get_fast_and_slow_cpus(&hmp_fast_cpu_mask, &hmp_slow_cpu_mask);
++
++ /*
++ * Initialize hmp_domains
++ * Must be ordered with respect to compute capacity.
++ * Fastest domain at head of list.
++ */
++ if(!cpumask_empty(&hmp_slow_cpu_mask)) {
++ domain = (struct hmp_domain *)
++ kmalloc(sizeof(struct hmp_domain), GFP_KERNEL);
++ cpumask_copy(&domain->possible_cpus, &hmp_slow_cpu_mask);
++ cpumask_and(&domain->cpus, cpu_online_mask, &domain->possible_cpus);
++ list_add(&domain->hmp_domains, hmp_domains_list);
++ }
++ domain = (struct hmp_domain *)
++ kmalloc(sizeof(struct hmp_domain), GFP_KERNEL);
++ cpumask_copy(&domain->possible_cpus, &hmp_fast_cpu_mask);
++ cpumask_and(&domain->cpus, cpu_online_mask, &domain->possible_cpus);
++ list_add(&domain->hmp_domains, hmp_domains_list);
++}
++#endif /* CONFIG_SCHED_HMP */
++
++
++/*
++ * cluster_to_logical_mask - return cpu logical mask of CPUs in a cluster
++ * @socket_id: cluster HW identifier
++ * @cluster_mask: the cpumask location to be initialized, modified by the
++ * function only if return value == 0
++ *
++ * Return:
++ *
++ * 0 on success
++ * -EINVAL if cluster_mask is NULL or there is no record matching socket_id
++ */
++int cluster_to_logical_mask(unsigned int socket_id, cpumask_t *cluster_mask)
++{
++ int cpu;
++
++ if (!cluster_mask)
++ return -EINVAL;
++
++ for_each_online_cpu(cpu)
++ if (socket_id == topology_physical_package_id(cpu)) {
++ cpumask_copy(cluster_mask, topology_core_cpumask(cpu));
++ return 0;
++ }
++
++ return -EINVAL;
++}
++
+ /*
+ * init_cpu_topology is called at boot when only one cpu is running
+ * which prevent simultaneous write access to cpu_topology array
+diff -Nur linux-3.10.30.orig/arch/arm/kernel/traps.c linux-linaro-stable-mx6/arch/arm/kernel/traps.c
+--- linux-3.10.30.orig/arch/arm/kernel/traps.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/kernel/traps.c 2014-05-15 20:33:34.665845660 +0200
+@@ -61,7 +61,7 @@
+ void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame)
+ {
+ #ifdef CONFIG_KALLSYMS
+- printk("[<%08lx>] (%pS) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
++ printk("[<%08lx>] (%ps) from [<%08lx>] (%pS)\n", where, (void *)where, from, (void *)from);
+ #else
+ printk("Function entered at [<%08lx>] from [<%08lx>]\n", where, from);
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm/lib/backtrace.S linux-linaro-stable-mx6/arch/arm/lib/backtrace.S
+--- linux-3.10.30.orig/arch/arm/lib/backtrace.S 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/lib/backtrace.S 2014-05-15 20:33:34.717846034 +0200
+@@ -80,14 +80,14 @@
+
+ ldr r1, [sv_pc, #-4] @ if stmfd sp!, {args} exists,
+ ldr r3, .Ldsi+4
+- teq r3, r1, lsr #10
++ teq r3, r1, lsr #11
+ ldreq r0, [frame, #-8] @ get sp
+ subeq r0, r0, #4 @ point at the last arg
+ bleq .Ldumpstm @ dump saved registers
+
+ 1004: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, ip, lr, pc}
+ ldr r3, .Ldsi @ instruction exists,
+- teq r3, r1, lsr #10
++ teq r3, r1, lsr #11
+ subeq r0, frame, #16
+ bleq .Ldumpstm @ dump saved registers
+
+@@ -128,11 +128,11 @@
+ beq 2f
+ add r7, r7, #1
+ teq r7, #6
+- moveq r7, #1
+- moveq r1, #'\n'
+- movne r1, #' '
+- ldr r3, [stack], #-4
+- mov r2, reg
++ moveq r7, #0
++ adr r3, .Lcr
++ addne r3, r3, #1 @ skip newline
++ ldr r2, [stack], #-4
++ mov r1, reg
+ adr r0, .Lfp
+ bl printk
+ 2: subs reg, reg, #1
+@@ -142,11 +142,11 @@
+ blne printk
+ ldmfd sp!, {instr, reg, stack, r7, pc}
+
+-.Lfp: .asciz "%cr%d:%08x"
++.Lfp: .asciz " r%d:%08x%s"
+ .Lcr: .asciz "\n"
+ .Lbad: .asciz "Backtrace aborted due to bad frame pointer <%p>\n"
+ .align
+-.Ldsi: .word 0xe92dd800 >> 10 @ stmfd sp!, {... fp, ip, lr, pc}
+- .word 0xe92d0000 >> 10 @ stmfd sp!, {}
++.Ldsi: .word 0xe92dd800 >> 11 @ stmfd sp!, {... fp, ip, lr, pc}
++ .word 0xe92d0000 >> 11 @ stmfd sp!, {}
+
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm/mach-exynos/mach-exynos5-dt.c linux-linaro-stable-mx6/arch/arm/mach-exynos/mach-exynos5-dt.c
+--- linux-3.10.30.orig/arch/arm/mach-exynos/mach-exynos5-dt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-exynos/mach-exynos5-dt.c 2014-05-15 20:33:35.129849006 +0200
+@@ -14,6 +14,7 @@
+ #include <linux/memblock.h>
+ #include <linux/io.h>
+ #include <linux/clocksource.h>
++#include <linux/dma-mapping.h>
+
+ #include <asm/mach/arch.h>
+ #include <mach/regs-pmu.h>
+@@ -23,11 +24,31 @@
+
+ #include "common.h"
+
++static u64 dma_mask64 = DMA_BIT_MASK(64);
++
+ static void __init exynos5_dt_map_io(void)
+ {
+ exynos_init_io(NULL, 0);
+ }
+
++static int exynos5250_platform_notifier(struct notifier_block *nb,
++ unsigned long event, void *__dev)
++{
++ struct device *dev = __dev;
++
++ if (event != BUS_NOTIFY_ADD_DEVICE)
++ return NOTIFY_DONE;
++
++ dev->dma_mask = &dma_mask64;
++ dev->coherent_dma_mask = DMA_BIT_MASK(64);
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block exynos5250_platform_nb = {
++ .notifier_call = exynos5250_platform_notifier,
++};
++
+ static void __init exynos5_dt_machine_init(void)
+ {
+ struct device_node *i2c_np;
+@@ -52,6 +73,11 @@
+ }
+ }
+
++ if (config_enabled(CONFIG_ARM_LPAE) &&
++ of_machine_is_compatible("samsung,exynos5250"))
++ bus_register_notifier(&platform_bus_type,
++ &exynos5250_platform_nb);
++
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ }
+
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/anatop.c linux-linaro-stable-mx6/arch/arm/mach-imx/anatop.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/anatop.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/anatop.c 2014-05-15 20:33:35.353850621 +0200
+@@ -9,6 +9,7 @@
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
++#include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
+@@ -16,6 +17,7 @@
+ #include <linux/mfd/syscon.h>
+ #include <linux/regmap.h>
+ #include "common.h"
++#include "hardware.h"
+
+ #define REG_SET 0x4
+ #define REG_CLR 0x8
+@@ -26,13 +28,20 @@
+ #define ANADIG_USB1_CHRG_DETECT 0x1b0
+ #define ANADIG_USB2_CHRG_DETECT 0x210
+ #define ANADIG_DIGPROG 0x260
++#define ANADIG_DIGPROG_IMX6SL 0x280
+
+ #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
++#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
+ #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
+ #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
++#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
+ #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
+ #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
+
++#define ANADIG_REG_TARG_MASK 0x1f
++#define ANADIG_REG1_TARG_SHIFT 9 /* VDDPU */
++#define ANADIG_REG2_TARG_SHIFT 18 /* VDDSOC */
++
+ static struct regmap *anatop;
+
+ static void imx_anatop_enable_weak2p5(bool enable)
+@@ -48,25 +57,48 @@
+ regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
+ }
+
+-static void imx_anatop_enable_fet_odrive(bool enable)
++static inline void imx_anatop_enable_2p5_pulldown(bool enable)
++{
++ regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
++ BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
++}
++
++static inline void imx_anatop_enable_fet_odrive(bool enable)
+ {
+ regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR),
+ BM_ANADIG_REG_CORE_FET_ODRIVE);
+ }
+
++static inline void imx_anatop_disconnect_high_snvs(bool enable)
++{
++ regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
++ BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
++}
++
+ void imx_anatop_pre_suspend(void)
+ {
+- imx_anatop_enable_weak2p5(true);
++ if (cpu_is_imx6sl()) {
++ imx_anatop_enable_2p5_pulldown(true);
++ imx_anatop_disconnect_high_snvs(true);
++ } else {
++ imx_anatop_enable_weak2p5(true);
++ }
++
+ imx_anatop_enable_fet_odrive(true);
+ }
+
+ void imx_anatop_post_resume(void)
+ {
+ imx_anatop_enable_fet_odrive(false);
+- imx_anatop_enable_weak2p5(false);
++ if (cpu_is_imx6sl()) {
++ imx_anatop_enable_2p5_pulldown(false);
++ imx_anatop_disconnect_high_snvs(false);
++ } else {
++ imx_anatop_enable_weak2p5(false);
++ }
+ }
+
+-void imx_anatop_usb_chrg_detect_disable(void)
++static void imx_anatop_usb_chrg_detect_disable(void)
+ {
+ regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
+ BM_ANADIG_USB_CHRG_DETECT_EN_B
+@@ -76,21 +108,70 @@
+ BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+ }
+
+-u32 imx_anatop_get_digprog(void)
++void imx_anatop_pu_enable(bool enable)
++{
++ u32 val;
++
++ regmap_read(anatop, ANADIG_REG_CORE, &val);
++ val &= ANADIG_REG_TARG_MASK << ANADIG_REG2_TARG_SHIFT;
++ /*
++ * set pu regulator only in LDO_BYPASS mode(know by VDDSOC reg 0x1f),
++ * else handled by anatop regulator driver.
++ */
++ if (((val >> (ANADIG_REG2_TARG_SHIFT)) & ANADIG_REG_TARG_MASK)
++ == ANADIG_REG_TARG_MASK) {
++ if (enable) {
++ regmap_write(anatop, ANADIG_REG_CORE + REG_SET,
++ ANADIG_REG_TARG_MASK << ANADIG_REG1_TARG_SHIFT);
++ udelay(70); /* bypass need 70us to be stable */
++ } else {
++ regmap_write(anatop, ANADIG_REG_CORE + REG_CLR,
++ ANADIG_REG_TARG_MASK << ANADIG_REG1_TARG_SHIFT);
++ }
++ }
++}
++void __init imx_init_revision_from_anatop(void)
+ {
+ struct device_node *np;
+ void __iomem *anatop_base;
+- static u32 digprog;
+-
+- if (digprog)
+- return digprog;
++ unsigned int revision;
++ u32 digprog;
++ u16 offset = ANADIG_DIGPROG;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
+ anatop_base = of_iomap(np, 0);
+ WARN_ON(!anatop_base);
+- digprog = readl_relaxed(anatop_base + ANADIG_DIGPROG);
++ if (of_device_is_compatible(np, "fsl,imx6sl-anatop"))
++ offset = ANADIG_DIGPROG_IMX6SL;
++ digprog = readl_relaxed(anatop_base + offset);
++ iounmap(anatop_base);
++
++ switch (digprog & 0xff) {
++ case 0:
++ revision = IMX_CHIP_REVISION_1_0;
++ break;
++ case 1:
++ revision = IMX_CHIP_REVISION_1_1;
++ break;
++ case 2:
++ revision = IMX_CHIP_REVISION_1_2;
++ break;
++ case 3:
++ revision = IMX_CHIP_REVISION_1_3;
++ break;
++ case 4:
++ revision = IMX_CHIP_REVISION_1_4;
++ break;
++ case 5:
++ revision = IMX_CHIP_REVISION_1_5;
++ break;
++ default:
++ revision = IMX_CHIP_REVISION_UNKNOWN;
++ }
+
+- return digprog;
++ mxc_set_cpu_type(digprog >> 16 & 0xff);
++ mxc_set_system_rev(((digprog >> 16 & 0xff) << 12) | ((digprog & 0xff) + 0x10));
++ imx_set_soc_revision(revision);
+ }
+
+ void __init imx_anatop_init(void)
+@@ -100,4 +181,6 @@
+ pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
+ return;
+ }
++
++ imx_anatop_usb_chrg_detect_disable();
+ }
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/busfreq_ddr3.c linux-linaro-stable-mx6/arch/arm/mach-imx/busfreq_ddr3.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/busfreq_ddr3.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/busfreq_ddr3.c 2014-05-15 20:33:35.353850621 +0200
+@@ -0,0 +1,476 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file busfreq_ddr3.c
++ *
++ * @brief iMX6 DDR3 frequency change specific file.
++ *
++ * @ingroup PM
++ */
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/clk.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/genalloc.h>
++#include <linux/interrupt.h>
++#include <linux/irqchip/arm-gic.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/sched.h>
++#include <linux/smp.h>
++
++#include "hardware.h"
++
++/* DDR settings */
++static unsigned long (*iram_ddr_settings)[2];
++static unsigned long (*normal_mmdc_settings)[2];
++static unsigned long (*iram_iomux_settings)[2];
++
++static void __iomem *mmdc_base;
++static void __iomem *iomux_base;
++static void __iomem *ccm_base;
++static void __iomem *l2_base;
++static void __iomem *gic_dist_base;
++static u32 *irqs_used;
++
++static void *ddr_freq_change_iram_base;
++static int ddr_settings_size;
++static int iomux_settings_size;
++static volatile unsigned int cpus_in_wfe;
++static volatile bool wait_for_ddr_freq_update;
++static int curr_ddr_rate;
++
++void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings,
++ bool dll_mode, void *iomux_offsets) = NULL;
++
++extern unsigned int ddr_med_rate;
++extern unsigned int ddr_normal_rate;
++extern int low_bus_freq_mode;
++extern int audio_bus_freq_mode;
++extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings,
++ bool dll_mode, void *iomux_offsets);
++
++#define MIN_DLL_ON_FREQ 333000000
++#define MAX_DLL_OFF_FREQ 125000000
++#define DDR_FREQ_CHANGE_SIZE 0x2000
++
++unsigned long ddr3_dll_mx6q[][2] = {
++ {0x0c, 0x0},
++ {0x10, 0x0},
++ {0x1C, 0x04088032},
++ {0x1C, 0x0408803a},
++ {0x1C, 0x08408030},
++ {0x1C, 0x08408038},
++ {0x818, 0x0},
++};
++
++unsigned long ddr3_calibration[][2] = {
++ {0x83c, 0x0},
++ {0x840, 0x0},
++ {0x483c, 0x0},
++ {0x4840, 0x0},
++ {0x848, 0x0},
++ {0x4848, 0x0},
++ {0x850, 0x0},
++ {0x4850, 0x0},
++};
++
++unsigned long ddr3_dll_mx6dl[][2] = {
++ {0x0c, 0x0},
++ {0x10, 0x0},
++ {0x1C, 0x04008032},
++ {0x1C, 0x0400803a},
++ {0x1C, 0x07208030},
++ {0x1C, 0x07208038},
++ {0x818, 0x0},
++};
++
++unsigned long iomux_offsets_mx6q[][2] = {
++ {0x5A8, 0x0},
++ {0x5B0, 0x0},
++ {0x524, 0x0},
++ {0x51C, 0x0},
++ {0x518, 0x0},
++ {0x50C, 0x0},
++ {0x5B8, 0x0},
++ {0x5C0, 0x0},
++};
++
++unsigned long iomux_offsets_mx6dl[][2] = {
++ {0x4BC, 0x0},
++ {0x4C0, 0x0},
++ {0x4C4, 0x0},
++ {0x4C8, 0x0},
++ {0x4CC, 0x0},
++ {0x4D0, 0x0},
++ {0x4D4, 0x0},
++ {0x4D8, 0x0},
++};
++
++unsigned long ddr3_400[][2] = {
++ {0x83c, 0x42490249},
++ {0x840, 0x02470247},
++ {0x483c, 0x42570257},
++ {0x4840, 0x02400240},
++ {0x848, 0x4039363C},
++ {0x4848, 0x3A39333F},
++ {0x850, 0x38414441},
++ {0x4850, 0x472D4833}
++};
++
++int can_change_ddr_freq(void)
++{
++ return 1;
++}
++
++/*
++ * each active core apart from the one changing
++ * the DDR frequency will execute this function.
++ * the rest of the cores have to remain in WFE
++ * state until the frequency is changed.
++ */
++irqreturn_t wait_in_wfe_irq(int irq, void *dev_id)
++{
++ u32 me = smp_processor_id();
++
++ *((char *)(&cpus_in_wfe) + (u8)me) = 0xff;
++
++ while (wait_for_ddr_freq_update)
++ wfe();
++
++ *((char *)(&cpus_in_wfe) + (u8)me) = 0;
++
++ return IRQ_HANDLED;
++}
++
++/* change the DDR frequency. */
++int update_ddr_freq(int ddr_rate)
++{
++ int i, j;
++ unsigned int reg;
++ bool dll_off = false;
++ unsigned int online_cpus = 0;
++ int cpu = 0;
++ int me;
++
++ if (!can_change_ddr_freq())
++ return -1;
++
++ if (ddr_rate == curr_ddr_rate)
++ return 0;
++
++ printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate);
++
++ if (low_bus_freq_mode || audio_bus_freq_mode)
++ dll_off = true;
++
++ iram_ddr_settings[0][0] = ddr_settings_size;
++ iram_iomux_settings[0][0] = iomux_settings_size;
++ if (ddr_rate == ddr_med_rate && cpu_is_imx6q()) {
++ for (i = 0; i < ARRAY_SIZE(ddr3_dll_mx6q); i++) {
++ iram_ddr_settings[i + 1][0] =
++ normal_mmdc_settings[i][0];
++ iram_ddr_settings[i + 1][1] =
++ normal_mmdc_settings[i][1];
++ }
++ for (j = 0, i = ARRAY_SIZE(ddr3_dll_mx6q);
++ i < iram_ddr_settings[0][0]; j++, i++) {
++ iram_ddr_settings[i + 1][0] =
++ ddr3_400[j][0];
++ iram_ddr_settings[i + 1][1] =
++ ddr3_400[j][1];
++ }
++ } else if (ddr_rate == ddr_normal_rate) {
++ for (i = 0; i < iram_ddr_settings[0][0]; i++) {
++ iram_ddr_settings[i + 1][0] =
++ normal_mmdc_settings[i][0];
++ iram_ddr_settings[i + 1][1] =
++ normal_mmdc_settings[i][1];
++ }
++ }
++
++ /* ensure that all Cores are in WFE. */
++ local_irq_disable();
++
++ me = smp_processor_id();
++
++ *((char *)(&cpus_in_wfe) + (u8)me) = 0xff;
++ wait_for_ddr_freq_update = true;
++ for_each_online_cpu(cpu) {
++ *((char *)(&online_cpus) + (u8)cpu) = 0xff;
++ if (cpu != me) {
++ /* set the interrupt to be pending in the GIC. */
++ reg = 1 << (irqs_used[cpu] % 32);
++ writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET
++ + (irqs_used[cpu] / 32) * 4);
++ }
++ }
++ while (cpus_in_wfe != online_cpus)
++ udelay(5);
++
++ /*
++ * Flush the TLB, to ensure no TLB maintenance occurs
++ * when DDR is in self-refresh.
++ */
++ local_flush_tlb_all();
++ /* Now we can change the DDR frequency. */
++ mx6_change_ddr_freq(ddr_rate, iram_ddr_settings,
++ dll_off, iram_iomux_settings);
++
++ curr_ddr_rate = ddr_rate;
++
++ /* DDR frequency change is done . */
++ wait_for_ddr_freq_update = false;
++
++ /* wake up all the cores. */
++ sev();
++
++ *((char *)(&cpus_in_wfe) + (u8)me) = 0;
++
++ local_irq_enable();
++
++ printk(KERN_DEBUG "Bus freq set to %d done!\n", ddr_rate);
++
++ return 0;
++}
++
++int init_mmdc_ddr3_settings(struct platform_device *busfreq_pdev)
++{
++ struct device *dev = &busfreq_pdev->dev;
++ struct platform_device *ocram_dev;
++ unsigned int iram_paddr;
++ int i, err;
++ u32 cpu;
++ struct device_node *node;
++ struct gen_pool *iram_pool;
++ void *iram_addr;
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6q-mmdc device tree data!\n");
++ return -EINVAL;
++ }
++ mmdc_base = of_iomap(node, 0);
++ WARN(!mmdc_base, "unable to map mmdc registers\n");
++
++ node = NULL;
++ if (cpu_is_imx6q())
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc");
++ if (cpu_is_imx6dl())
++ node = of_find_compatible_node(NULL, NULL,
++ "fsl,imx6dl-iomuxc");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6q-iomux device tree data!\n");
++ return -EINVAL;
++ }
++ iomux_base = of_iomap(node, 0);
++ WARN(!iomux_base, "unable to map iomux registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6q-ccm device tree data!\n");
++ return -EINVAL;
++ }
++ ccm_base = of_iomap(node, 0);
++ WARN(!ccm_base, "unable to map mmdc registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6q-pl310-cache device tree data!\n");
++ return -EINVAL;
++ }
++ l2_base = of_iomap(node, 0);
++ WARN(!ccm_base, "unable to map mmdc registers\n");
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n");
++ return -EINVAL;
++ }
++ gic_dist_base = of_iomap(node, 0);
++ WARN(!gic_dist_base, "unable to map gic dist registers\n");
++
++ if (cpu_is_imx6q())
++ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) +
++ ARRAY_SIZE(ddr3_calibration);
++ if (cpu_is_imx6dl())
++ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) +
++ ARRAY_SIZE(ddr3_calibration);
++
++ normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL);
++ if (cpu_is_imx6q()) {
++ memcpy(normal_mmdc_settings, ddr3_dll_mx6q,
++ sizeof(ddr3_dll_mx6q));
++ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)),
++ ddr3_calibration, sizeof(ddr3_calibration));
++ }
++ if (cpu_is_imx6dl()) {
++ memcpy(normal_mmdc_settings, ddr3_dll_mx6dl,
++ sizeof(ddr3_dll_mx6dl));
++ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)),
++ ddr3_calibration, sizeof(ddr3_calibration));
++ }
++ /* store the original DDR settings at boot. */
++ for (i = 0; i < ddr_settings_size; i++) {
++ /*
++ * writes via command mode register cannot be read back.
++ * hence hardcode them in the initial static array.
++ * this may require modification on a per customer basis.
++ */
++ if (normal_mmdc_settings[i][0] != 0x1C)
++ normal_mmdc_settings[i][1] =
++ readl_relaxed(mmdc_base
++ + normal_mmdc_settings[i][0]);
++ }
++
++ irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(),
++ GFP_KERNEL);
++
++ for_each_online_cpu(cpu) {
++ int irq;
++
++ /*
++ * set up a reserved interrupt to get all
++ * the active cores into a WFE state
++ * before changing the DDR frequency.
++ */
++ irq = platform_get_irq(busfreq_pdev, cpu);
++ err = request_irq(irq, wait_in_wfe_irq,
++ IRQF_PERCPU, "mmdc_1", NULL);
++ if (err) {
++ dev_err(dev,
++ "Busfreq:request_irq failed %d, err = %d\n",
++ irq, err);
++ return err;
++ }
++ err = irq_set_affinity(irq, cpumask_of(cpu));
++ if (err) {
++ dev_err(dev,
++ "Busfreq: Cannot set irq affinity irq=%d,\n",
++ irq);
++ return err;
++ }
++ irqs_used[cpu] = irq;
++ }
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "mmio-sram");
++ if (!node) {
++ dev_err(dev, "%s: failed to find ocram node\n",
++ __func__);
++ return -EINVAL;
++ }
++
++ ocram_dev = of_find_device_by_node(node);
++ if (!ocram_dev) {
++ dev_err(dev, "failed to find ocram device!\n");
++ return -EINVAL;
++ }
++
++ iram_pool = dev_get_gen_pool(&ocram_dev->dev);
++ if (!iram_pool) {
++ dev_err(dev, "iram pool unavailable!\n");
++ return -EINVAL;
++ }
++
++ iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q);
++ iram_addr = (void *)gen_pool_alloc(iram_pool,
++ (iomux_settings_size * 8) + 8);
++ iram_iomux_settings = iram_addr;
++ if (!iram_iomux_settings) {
++ dev_err(dev, "unable to alloc iram for IOMUX settings!\n");
++ return -ENOMEM;
++ }
++
++ /*
++ * Allocate extra space to store the number of entries in the
++ * ddr_settings plus 4 extra regsiter information that needs
++ * to be passed to the frequency change code.
++ * sizeof(iram_ddr_settings) = sizeof(ddr_settings) +
++ * entries in ddr_settings + 16.
++ * The last 4 enties store the addresses of the registers:
++ * CCM_BASE_ADDR
++ * MMDC_BASE_ADDR
++ * IOMUX_BASE_ADDR
++ * L2X0_BASE_ADDR
++ */
++ iram_addr = (void *)gen_pool_alloc(iram_pool,
++ (ddr_settings_size * 8) + 8 + 32);
++ iram_ddr_settings = iram_addr;
++ if (!iram_ddr_settings) {
++ dev_err(dev, "unable to alloc iram for ddr settings!\n");
++ return -ENOMEM;
++ }
++
++ i = ddr_settings_size + 1;
++ iram_ddr_settings[i][0] = (unsigned long)mmdc_base;
++ iram_ddr_settings[i+1][0] = (unsigned long)ccm_base;
++ iram_ddr_settings[i+2][0] = (unsigned long)iomux_base;
++ iram_ddr_settings[i+3][0] = (unsigned long)l2_base;
++
++ if (cpu_is_imx6q()) {
++ /* store the IOMUX settings at boot. */
++ for (i = 0; i < iomux_settings_size; i++) {
++ iomux_offsets_mx6q[i][1] =
++ readl_relaxed(iomux_base +
++ iomux_offsets_mx6q[i][0]);
++ iram_iomux_settings[i+1][0] = iomux_offsets_mx6q[i][0];
++ iram_iomux_settings[i+1][1] = iomux_offsets_mx6q[i][1];
++ }
++ }
++
++ if (cpu_is_imx6dl()) {
++ for (i = 0; i < iomux_settings_size; i++) {
++ iomux_offsets_mx6dl[i][1] =
++ readl_relaxed(iomux_base +
++ iomux_offsets_mx6dl[i][0]);
++ iram_iomux_settings[i+1][0] = iomux_offsets_mx6dl[i][0];
++ iram_iomux_settings[i+1][1] = iomux_offsets_mx6dl[i][1];
++ }
++ }
++
++ ddr_freq_change_iram_base = (void *)gen_pool_alloc(iram_pool,
++ DDR_FREQ_CHANGE_SIZE);
++ if (!ddr_freq_change_iram_base) {
++ dev_err(dev, "Cannot alloc iram for ddr freq change code!\n");
++ return -ENOMEM;
++ }
++
++ iram_paddr = gen_pool_virt_to_phys(iram_pool,
++ (unsigned long)ddr_freq_change_iram_base);
++ /*
++ * Need to remap the area here since we want
++ * the memory region to be executable.
++ */
++ ddr_freq_change_iram_base = __arm_ioremap(iram_paddr,
++ DDR_FREQ_CHANGE_SIZE,
++ MT_MEMORY_NONCACHED);
++ mx6_change_ddr_freq = (void *)fncpy(ddr_freq_change_iram_base,
++ &mx6_ddr3_freq_change, DDR_FREQ_CHANGE_SIZE);
++
++ curr_ddr_rate = ddr_normal_rate;
++
++ return 0;
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/busfreq-imx6.c linux-linaro-stable-mx6/arch/arm/mach-imx/busfreq-imx6.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/busfreq-imx6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/busfreq-imx6.c 2014-05-15 20:33:35.353850621 +0200
+@@ -0,0 +1,938 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file busfreq-imx6.c
++ *
++ * @brief A common API for the Freescale Semiconductor iMX6 Busfreq API
++ *
++ * The APIs are for setting bus frequency to different values based on the
++ * highest freqeuncy requested.
++ *
++ * @ingroup PM
++ */
++
++#include <asm/cacheflush.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/reboot.h>
++#include <linux/regulator/consumer.h>
++#include <linux/sched.h>
++#include <linux/suspend.h>
++#include "hardware.h"
++
++#define LPAPM_CLK 24000000
++#define DDR3_AUDIO_CLK 50000000
++#define LPDDR2_AUDIO_CLK 100000000
++
++int high_bus_freq_mode;
++int med_bus_freq_mode;
++int audio_bus_freq_mode;
++int low_bus_freq_mode;
++int ultra_low_bus_freq_mode;
++unsigned int ddr_med_rate;
++unsigned int ddr_normal_rate;
++
++static int bus_freq_scaling_initialized;
++static struct device *busfreq_dev;
++static int busfreq_suspended;
++static u32 org_arm_rate;
++static int bus_freq_scaling_is_active;
++static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count;
++static unsigned int ddr_low_rate;
++
++extern int init_mmdc_lpddr2_settings(struct platform_device *dev);
++extern int init_mmdc_ddr3_settings(struct platform_device *dev);
++extern int update_ddr_freq(int ddr_rate);
++extern int update_lpddr2_freq(int ddr_rate);
++
++DEFINE_MUTEX(bus_freq_mutex);
++static DEFINE_SPINLOCK(freq_lock);
++
++static struct clk *pll2_400;
++static struct clk *periph_clk;
++static struct clk *periph_pre_clk;
++static struct clk *periph_clk2_sel;
++static struct clk *periph_clk2;
++static struct clk *osc_clk;
++static struct clk *cpu_clk;
++static struct clk *pll3;
++static struct clk *pll2;
++static struct clk *pll2_200;
++static struct clk *pll1_sys;
++static struct clk *periph2_clk;
++static struct clk *ocram_clk;
++static struct clk *ahb_clk;
++static struct clk *pll1_sw_clk;
++static struct clk *periph2_pre_clk;
++static struct clk *periph2_clk2_sel;
++static struct clk *periph2_clk2;
++static struct clk *step_clk;
++static struct clk *axi_sel_clk;
++static struct clk *pll3_pfd1_540m;
++
++static u32 pll2_org_rate;
++static struct delayed_work low_bus_freq_handler;
++static struct delayed_work bus_freq_daemon;
++
++static void enter_lpm_imx6sl(void)
++{
++ unsigned long flags;
++
++ if (high_bus_freq_mode) {
++ pll2_org_rate = clk_get_rate(pll2);
++ /* Set periph_clk to be sourced from OSC_CLK */
++ clk_set_parent(periph_clk2_sel, osc_clk);
++ clk_set_parent(periph_clk, periph_clk2);
++ /* Ensure AHB/AXI clks are at 24MHz. */
++ clk_set_rate(ahb_clk, LPAPM_CLK);
++ clk_set_rate(ocram_clk, LPAPM_CLK);
++ }
++ if (audio_bus_count) {
++ /* Set AHB to 8MHz to lower pwer.*/
++ clk_set_rate(ahb_clk, LPAPM_CLK / 3);
++
++ /* Set up DDR to 100MHz. */
++ spin_lock_irqsave(&freq_lock, flags);
++ update_lpddr2_freq(LPDDR2_AUDIO_CLK);
++ spin_unlock_irqrestore(&freq_lock, flags);
++
++ /* Fix the clock tree in kernel */
++ clk_set_rate(pll2, pll2_org_rate);
++ clk_set_parent(periph2_pre_clk, pll2_200);
++ clk_set_parent(periph2_clk, periph2_pre_clk);
++
++ if (low_bus_freq_mode || ultra_low_bus_freq_mode) {
++ /*
++ * Swtich ARM to run off PLL2_PFD2_400MHz
++ * since DDR is anyway at 100MHz.
++ */
++ clk_set_parent(step_clk, pll2_400);
++ clk_set_parent(pll1_sw_clk, step_clk);
++ /*
++ * Ensure that the clock will be
++ * at original speed.
++ */
++ clk_set_rate(cpu_clk, org_arm_rate);
++ }
++ low_bus_freq_mode = 0;
++ ultra_low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 1;
++ } else {
++ u32 arm_div, pll1_rate;
++ org_arm_rate = clk_get_rate(cpu_clk);
++ if (low_bus_freq_mode && low_bus_count == 0) {
++ /*
++ * We are already in DDR @ 24MHz state, but
++ * no one but ARM needs the DDR. In this case,
++ * we can lower the DDR freq to 1MHz when ARM
++ * enters WFI in this state. Keep track of this state.
++ */
++ ultra_low_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++ } else {
++ if (!ultra_low_bus_freq_mode && !low_bus_freq_mode) {
++ /*
++ * Set DDR to 24MHz.
++ * Since we are going to bypass PLL2,
++ * we need to move ARM clk off PLL2_PFD2
++ * to PLL1. Make sure the PLL1 is running
++ * at the lowest possible freq.
++ */
++ clk_set_rate(pll1_sys,
++ clk_round_rate(pll1_sys, org_arm_rate));
++ pll1_rate = clk_get_rate(pll1_sys);
++ arm_div = pll1_rate / org_arm_rate + 1;
++ /*
++ * Ensure ARM CLK is lower before
++ * changing the parent.
++ */
++ clk_set_rate(cpu_clk, org_arm_rate / arm_div);
++ /* Now set the ARM clk parent to PLL1_SYS. */
++ clk_set_parent(pll1_sw_clk, pll1_sys);
++
++ /*
++ * Set STEP_CLK back to OSC to save power and
++ * also to maintain the parent.The WFI iram code
++ * will switch step_clk to osc, but the clock API
++ * is not aware of the change and when a new request
++ * to change the step_clk parent to pll2_pfd2_400M
++ * is requested sometime later, the change is ignored.
++ */
++ clk_set_parent(step_clk, osc_clk);
++ /* Now set DDR to 24MHz. */
++ spin_lock_irqsave(&freq_lock, flags);
++ update_lpddr2_freq(LPAPM_CLK);
++ spin_unlock_irqrestore(&freq_lock, flags);
++
++ /*
++ * Fix the clock tree in kernel.
++ * Make sure PLL2 rate is updated as it gets
++ * bypassed in the DDR freq change code.
++ */
++ clk_set_rate(pll2, LPAPM_CLK);
++ clk_set_parent(periph2_clk2_sel, pll2);
++ clk_set_parent(periph2_clk, periph2_clk2_sel);
++
++ }
++ if (low_bus_count == 0) {
++ ultra_low_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ } else {
++ ultra_low_bus_freq_mode = 0;
++ low_bus_freq_mode = 1;
++ }
++ audio_bus_freq_mode = 0;
++ }
++ }
++}
++
++static void exit_lpm_imx6sl(void)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&freq_lock, flags);
++ /* Change DDR freq in IRAM. */
++ update_lpddr2_freq(ddr_normal_rate);
++ spin_unlock_irqrestore(&freq_lock, flags);
++
++ /*
++ * Fix the clock tree in kernel.
++ * Make sure PLL2 rate is updated as it gets
++ * un-bypassed in the DDR freq change code.
++ */
++ clk_set_rate(pll2, pll2_org_rate);
++ clk_set_parent(periph2_pre_clk, pll2_400);
++ clk_set_parent(periph2_clk, periph2_pre_clk);
++
++ /* Ensure that periph_clk is sourced from PLL2_400. */
++ clk_set_parent(periph_pre_clk, pll2_400);
++ /*
++ * Before switching the perhiph_clk, ensure that the
++ * AHB/AXI will not be too fast.
++ */
++ clk_set_rate(ahb_clk, LPAPM_CLK / 3);
++ clk_set_rate(ocram_clk, LPAPM_CLK / 2);
++ clk_set_parent(periph_clk, periph_pre_clk);
++
++ if (low_bus_freq_mode || ultra_low_bus_freq_mode) {
++ /* Move ARM from PLL1_SW_CLK to PLL2_400. */
++ clk_set_parent(step_clk, pll2_400);
++ clk_set_parent(pll1_sw_clk, step_clk);
++ clk_set_rate(cpu_clk, org_arm_rate);
++ ultra_low_bus_freq_mode = 0;
++ }
++}
++
++int reduce_bus_freq(void)
++{
++ int ret = 0;
++ clk_prepare_enable(pll3);
++ if (cpu_is_imx6sl())
++ enter_lpm_imx6sl();
++ else {
++ if (cpu_is_imx6dl() && (clk_get_parent(axi_sel_clk)
++ != periph_clk))
++ /* Set axi to periph_clk */
++ clk_set_parent(axi_sel_clk, periph_clk);
++
++ if (audio_bus_count) {
++ /* Need to ensure that PLL2_PFD_400M is kept ON. */
++ clk_prepare_enable(pll2_400);
++ update_ddr_freq(DDR3_AUDIO_CLK);
++ /* Make sure periph clk's parent also got updated */
++ ret = clk_set_parent(periph_clk2_sel, pll3);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_pre_clk, pll2_200);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_clk, periph_pre_clk);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ audio_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ } else {
++ update_ddr_freq(LPAPM_CLK);
++ /* Make sure periph clk's parent also got updated */
++ ret = clk_set_parent(periph_clk2_sel, osc_clk);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ /* Set periph_clk parent to OSC via periph_clk2_sel */
++ ret = clk_set_parent(periph_clk, periph_clk2);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ if (audio_bus_freq_mode)
++ clk_disable_unprepare(pll2_400);
++ low_bus_freq_mode = 1;
++ audio_bus_freq_mode = 0;
++ }
++ }
++ clk_disable_unprepare(pll3);
++
++ med_bus_freq_mode = 0;
++ high_bus_freq_mode = 0;
++
++ if (audio_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to audio mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++ if (low_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to low mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++
++ return ret;
++}
++
++static void reduce_bus_freq_handler(struct work_struct *work)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ reduce_bus_freq();
++
++ mutex_unlock(&bus_freq_mutex);
++}
++
++/*
++ * Set the DDR, AHB to 24MHz.
++ * This mode will be activated only when none of the modules that
++ * need a higher DDR or AHB frequency are active.
++ */
++int set_low_bus_freq(void)
++{
++ if (busfreq_suspended)
++ return 0;
++
++ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
++ return 0;
++
++ /*
++ * Check to see if we need to got from
++ * low bus freq mode to audio bus freq mode.
++ * If so, the change needs to be done immediately.
++ */
++ if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode))
++ reduce_bus_freq();
++ else
++ /*
++ * Don't lower the frequency immediately. Instead
++ * scheduled a delayed work and drop the freq if
++ * the conditions still remain the same.
++ */
++ schedule_delayed_work(&low_bus_freq_handler,
++ usecs_to_jiffies(3000000));
++ return 0;
++}
++
++/*
++ * Set the DDR to either 528MHz or 400MHz for iMX6qd
++ * or 400MHz for iMX6dl.
++ */
++int set_high_bus_freq(int high_bus_freq)
++{
++ int ret = 0;
++ struct clk *periph_clk_parent;
++
++ if (bus_freq_scaling_initialized && bus_freq_scaling_is_active)
++ cancel_delayed_work_sync(&low_bus_freq_handler);
++
++ if (busfreq_suspended)
++ return 0;
++
++ if (cpu_is_imx6q())
++ periph_clk_parent = pll2;
++ else
++ periph_clk_parent = pll2_400;
++
++ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
++ return 0;
++
++ if (high_bus_freq_mode)
++ return 0;
++
++ /* medium bus freq is only supported for MX6DQ */
++ if (med_bus_freq_mode && !high_bus_freq)
++ return 0;
++
++ clk_prepare_enable(pll3);
++ if (cpu_is_imx6sl())
++ exit_lpm_imx6sl();
++ else {
++ if (high_bus_freq) {
++ update_ddr_freq(ddr_normal_rate);
++ /* Make sure periph clk's parent also got updated */
++ ret = clk_set_parent(periph_clk2_sel, pll3);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_pre_clk, periph_clk_parent);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_clk, periph_pre_clk);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ if (cpu_is_imx6dl() && (clk_get_parent(axi_sel_clk)
++ != pll3_pfd1_540m))
++ /* Set axi to pll3_pfd1_540m */
++ clk_set_parent(axi_sel_clk, pll3_pfd1_540m);
++ } else {
++ update_ddr_freq(ddr_med_rate);
++ /* Make sure periph clk's parent also got updated */
++ ret = clk_set_parent(periph_clk2_sel, pll3);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_pre_clk, pll2_400);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ ret = clk_set_parent(periph_clk, periph_pre_clk);
++ if (ret)
++ dev_WARN(busfreq_dev,
++ "%s: %d: clk set parent fail!\n",
++ __func__, __LINE__);
++ }
++ if (audio_bus_freq_mode)
++ clk_disable_unprepare(pll2_400);
++ }
++
++ high_bus_freq_mode = 1;
++ med_bus_freq_mode = 0;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++
++ clk_disable_unprepare(pll3);
++
++ if (high_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to high mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++ if (med_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to med mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++
++ return 0;
++}
++
++void request_bus_freq(enum bus_freq_mode mode)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ if (mode == BUS_FREQ_HIGH)
++ high_bus_count++;
++ else if (mode == BUS_FREQ_MED)
++ med_bus_count++;
++ else if (mode == BUS_FREQ_AUDIO)
++ audio_bus_count++;
++ else if (mode == BUS_FREQ_LOW)
++ low_bus_count++;
++
++ if (busfreq_suspended || !bus_freq_scaling_initialized ||
++ !bus_freq_scaling_is_active) {
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ cancel_delayed_work_sync(&low_bus_freq_handler);
++
++ if (cpu_is_imx6dl()) {
++ /* No support for medium setpoint on MX6DL. */
++ if (mode == BUS_FREQ_MED) {
++ high_bus_count++;
++ mode = BUS_FREQ_HIGH;
++ }
++ }
++
++ if ((mode == BUS_FREQ_HIGH) && (!high_bus_freq_mode)) {
++ set_high_bus_freq(1);
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ if ((mode == BUS_FREQ_MED) && (!high_bus_freq_mode) &&
++ (!med_bus_freq_mode)) {
++ set_high_bus_freq(0);
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((mode == BUS_FREQ_AUDIO) && (!high_bus_freq_mode) &&
++ (!med_bus_freq_mode) && (!audio_bus_freq_mode)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ mutex_unlock(&bus_freq_mutex);
++ return;
++}
++EXPORT_SYMBOL(request_bus_freq);
++
++void release_bus_freq(enum bus_freq_mode mode)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ if (mode == BUS_FREQ_HIGH) {
++ if (high_bus_count == 0) {
++ dev_err(busfreq_dev, "high bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ high_bus_count--;
++ } else if (mode == BUS_FREQ_MED) {
++ if (med_bus_count == 0) {
++ dev_err(busfreq_dev, "med bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ med_bus_count--;
++ } else if (mode == BUS_FREQ_AUDIO) {
++ if (audio_bus_count == 0) {
++ dev_err(busfreq_dev, "audio bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ audio_bus_count--;
++ } else if (mode == BUS_FREQ_LOW) {
++ if (low_bus_count == 0) {
++ dev_err(busfreq_dev, "low bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ low_bus_count--;
++ }
++
++ if (busfreq_suspended || !bus_freq_scaling_initialized ||
++ !bus_freq_scaling_is_active) {
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ if (cpu_is_imx6dl()) {
++ /* No support for medium setpoint on MX6DL. */
++ if (mode == BUS_FREQ_MED) {
++ high_bus_count--;
++ mode = BUS_FREQ_HIGH;
++ }
++ }
++
++ if ((!audio_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count != 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((!low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0) &&
++ (low_bus_count != 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((!ultra_low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0) &&
++ (low_bus_count == 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ mutex_unlock(&bus_freq_mutex);
++ return;
++}
++EXPORT_SYMBOL(release_bus_freq);
++
++static void bus_freq_daemon_handler(struct work_struct *work)
++{
++ mutex_lock(&bus_freq_mutex);
++ if ((!low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0))
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++}
++
++static ssize_t bus_freq_scaling_enable_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ if (bus_freq_scaling_is_active)
++ return sprintf(buf, "Bus frequency scaling is enabled\n");
++ else
++ return sprintf(buf, "Bus frequency scaling is disabled\n");
++}
++
++static ssize_t bus_freq_scaling_enable_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t size)
++{
++ if (strncmp(buf, "1", 1) == 0) {
++ bus_freq_scaling_is_active = 1;
++ set_high_bus_freq(1);
++ /*
++ * We set bus freq to highest at the beginning,
++ * so we use this daemon thread to make sure system
++ * can enter low bus mode if
++ * there is no high bus request pending
++ */
++ schedule_delayed_work(&bus_freq_daemon,
++ usecs_to_jiffies(5000000));
++ } else if (strncmp(buf, "0", 1) == 0) {
++ if (bus_freq_scaling_is_active)
++ set_high_bus_freq(1);
++ bus_freq_scaling_is_active = 0;
++ }
++ return size;
++}
++
++static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event,
++ void *dummy)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ if (event == PM_SUSPEND_PREPARE) {
++ high_bus_count++;
++ set_high_bus_freq(1);
++ busfreq_suspended = 1;
++ } else if (event == PM_POST_SUSPEND) {
++ busfreq_suspended = 0;
++ high_bus_count--;
++ schedule_delayed_work(&bus_freq_daemon,
++ usecs_to_jiffies(5000000));
++ }
++
++ mutex_unlock(&bus_freq_mutex);
++
++ return NOTIFY_OK;
++}
++
++static int busfreq_reboot_notifier_event(struct notifier_block *this,
++ unsigned long event, void *ptr)
++{
++ /* System is rebooting. Set the system into high_bus_freq_mode. */
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ return 0;
++}
++
++static struct notifier_block imx_bus_freq_pm_notifier = {
++ .notifier_call = bus_freq_pm_notify,
++};
++
++static struct notifier_block imx_busfreq_reboot_notifier = {
++ .notifier_call = busfreq_reboot_notifier_event,
++};
++
++
++static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show,
++ bus_freq_scaling_enable_store);
++
++/*!
++ * This is the probe routine for the bus frequency driver.
++ *
++ * @param pdev The platform device structure
++ *
++ * @return The function returns 0 on success
++ *
++ */
++
++static int busfreq_probe(struct platform_device *pdev)
++{
++ u32 err;
++
++ busfreq_dev = &pdev->dev;
++
++ pll2_400 = devm_clk_get(&pdev->dev, "pll2_pfd2_396m");
++ if (IS_ERR(pll2_400)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_pfd2_396m\n",
++ __func__);
++ return PTR_ERR(pll2_400);
++ }
++
++ pll2_200 = devm_clk_get(&pdev->dev, "pll2_198m");
++ if (IS_ERR(pll2_200)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_198m\n",
++ __func__);
++ return PTR_ERR(pll2_200);
++ }
++
++ pll2 = devm_clk_get(&pdev->dev, "pll2_bus");
++ if (IS_ERR(pll2)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_bus\n",
++ __func__);
++ return PTR_ERR(pll2);
++ }
++
++ cpu_clk = devm_clk_get(&pdev->dev, "arm");
++ if (IS_ERR(cpu_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get cpu_clk\n",
++ __func__);
++ return PTR_ERR(cpu_clk);
++ }
++
++ pll3 = devm_clk_get(&pdev->dev, "pll3_usb_otg");
++ if (IS_ERR(pll3)) {
++ dev_err(busfreq_dev, "%s: failed to get pll3_usb_otg\n",
++ __func__);
++ return PTR_ERR(pll3);
++ }
++
++ periph_clk = devm_clk_get(&pdev->dev, "periph");
++ if (IS_ERR(periph_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph\n",
++ __func__);
++ return PTR_ERR(periph_clk);
++ }
++
++ periph_pre_clk = devm_clk_get(&pdev->dev, "periph_pre");
++ if (IS_ERR(periph_pre_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_pre\n",
++ __func__);
++ return PTR_ERR(periph_pre_clk);
++ }
++
++ periph_clk2 = devm_clk_get(&pdev->dev, "periph_clk2");
++ if (IS_ERR(periph_clk2)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_clk2\n",
++ __func__);
++ return PTR_ERR(periph_clk2);
++ }
++
++ periph_clk2_sel = devm_clk_get(&pdev->dev, "periph_clk2_sel");
++ if (IS_ERR(periph_clk2_sel)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_clk2_sel\n",
++ __func__);
++ return PTR_ERR(periph_clk2_sel);
++ }
++
++ osc_clk = devm_clk_get(&pdev->dev, "osc");
++ if (IS_ERR(osc_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get osc_clk\n",
++ __func__);
++ return PTR_ERR(osc_clk);
++ }
++
++ if (cpu_is_imx6dl()) {
++ axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel");
++ if (IS_ERR(axi_sel_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get axi_sel_clk\n",
++ __func__);
++ return PTR_ERR(axi_sel_clk);
++ }
++
++ pll3_pfd1_540m = devm_clk_get(&pdev->dev, "pll3_pfd1_540m");
++ if (IS_ERR(pll3_pfd1_540m)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get pll3_pfd1_540m\n", __func__);
++ return PTR_ERR(pll3_pfd1_540m);
++ }
++ }
++
++ if (cpu_is_imx6sl()) {
++ pll1_sys = devm_clk_get(&pdev->dev, "pll1_sys");
++ if (IS_ERR(pll1_sys)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1_sys\n",
++ __func__);
++ return PTR_ERR(pll1_sys);
++ }
++
++ ahb_clk = devm_clk_get(&pdev->dev, "ahb");
++ if (IS_ERR(ahb_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get ahb_clk\n",
++ __func__);
++ return PTR_ERR(ahb_clk);
++ }
++
++ ocram_clk = devm_clk_get(&pdev->dev, "ocram");
++ if (IS_ERR(ocram_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get ocram_clk\n",
++ __func__);
++ return PTR_ERR(ocram_clk);
++ }
++
++ pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw");
++ if (IS_ERR(pll1_sw_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1_sw_clk\n",
++ __func__);
++ return PTR_ERR(pll1_sw_clk);
++ }
++
++ periph2_clk = devm_clk_get(&pdev->dev, "periph2");
++ if (IS_ERR(periph2_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph2\n",
++ __func__);
++ return PTR_ERR(periph2_clk);
++ }
++
++ periph2_pre_clk = devm_clk_get(&pdev->dev, "periph2_pre");
++ if (IS_ERR(periph2_pre_clk)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_pre_clk\n",
++ __func__);
++ return PTR_ERR(periph2_pre_clk);
++ }
++
++ periph2_clk2 = devm_clk_get(&pdev->dev, "periph2_clk2");
++ if (IS_ERR(periph2_clk2)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_clk2\n",
++ __func__);
++ return PTR_ERR(periph2_clk2);
++ }
++
++ periph2_clk2_sel = devm_clk_get(&pdev->dev, "periph2_clk2_sel");
++ if (IS_ERR(periph2_clk2_sel)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_clk2_sel\n",
++ __func__);
++ return PTR_ERR(periph2_clk2_sel);
++ }
++
++ step_clk = devm_clk_get(&pdev->dev, "step");
++ if (IS_ERR(step_clk)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get step_clk\n",
++ __func__);
++ return PTR_ERR(periph2_clk2_sel);
++ }
++
++ }
++
++ err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
++ if (err) {
++ dev_err(busfreq_dev,
++ "Unable to register sysdev entry for BUSFREQ");
++ return err;
++ }
++
++ if (of_property_read_u32(pdev->dev.of_node, "fsl,max_ddr_freq",
++ &ddr_normal_rate)) {
++ dev_err(busfreq_dev, "max_ddr_freq entry missing\n");
++ return -EINVAL;
++ }
++
++ high_bus_freq_mode = 1;
++ med_bus_freq_mode = 0;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++ ultra_low_bus_freq_mode = 0;
++
++ bus_freq_scaling_is_active = 1;
++ bus_freq_scaling_initialized = 1;
++
++ ddr_low_rate = LPAPM_CLK;
++ if (cpu_is_imx6q()) {
++ if (of_property_read_u32(pdev->dev.of_node, "fsl,med_ddr_freq",
++ &ddr_med_rate)) {
++ dev_info(busfreq_dev,
++ "DDR medium rate not supported.\n");
++ ddr_med_rate = ddr_normal_rate;
++ }
++ }
++
++ INIT_DELAYED_WORK(&low_bus_freq_handler, reduce_bus_freq_handler);
++ INIT_DELAYED_WORK(&bus_freq_daemon, bus_freq_daemon_handler);
++ register_pm_notifier(&imx_bus_freq_pm_notifier);
++ register_reboot_notifier(&imx_busfreq_reboot_notifier);
++
++ if (cpu_is_imx6sl())
++ err = init_mmdc_lpddr2_settings(pdev);
++ else
++ err = init_mmdc_ddr3_settings(pdev);
++ if (err) {
++ dev_err(busfreq_dev, "Busfreq init of MMDC failed\n");
++ return err;
++ }
++ return 0;
++}
++
++static const struct of_device_id imx6_busfreq_ids[] = {
++ { .compatible = "fsl,imx6_busfreq", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver busfreq_driver = {
++ .driver = {
++ .name = "imx6_busfreq",
++ .owner = THIS_MODULE,
++ .of_match_table = imx6_busfreq_ids,
++ },
++ .probe = busfreq_probe,
++};
++
++/*!
++ * Initialise the busfreq_driver.
++ *
++ * @return The function always returns 0.
++ */
++
++static int __init busfreq_init(void)
++{
++ if (platform_driver_register(&busfreq_driver) != 0)
++ return -ENODEV;
++
++ printk(KERN_INFO "Bus freq driver module loaded\n");
++
++ return 0;
++}
++
++static void __exit busfreq_cleanup(void)
++{
++ sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
++
++ /* Unregister the device structure */
++ platform_driver_unregister(&busfreq_driver);
++ bus_freq_scaling_initialized = 0;
++}
++
++module_init(busfreq_init);
++module_exit(busfreq_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("BusFreq driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/busfreq_lpddr2.c linux-linaro-stable-mx6/arch/arm/mach-imx/busfreq_lpddr2.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/busfreq_lpddr2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/busfreq_lpddr2.c 2014-05-15 20:33:35.353850621 +0200
+@@ -0,0 +1,183 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file busfreq_lpddr2.c
++ *
++ * @brief iMX6 LPDDR2 frequency change specific file.
++ *
++ * @ingroup PM
++ */
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/clk.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/genalloc.h>
++#include <linux/interrupt.h>
++#include <linux/irqchip/arm-gic.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/sched.h>
++#include <linux/smp.h>
++
++#include "hardware.h"
++
++/* DDR settings */
++static void __iomem *mmdc_base;
++static void __iomem *anatop_base;
++static void __iomem *ccm_base;
++static void __iomem *l2_base;
++static struct device *busfreq_dev;
++static void *ddr_freq_change_iram_base;
++static int curr_ddr_rate;
++
++unsigned long reg_addrs[4];
++
++void (*mx6_change_lpddr2_freq)(u32 ddr_freq, int bus_freq_mode,
++ void *iram_addr) = NULL;
++
++extern unsigned int ddr_normal_rate;
++extern int low_bus_freq_mode;
++extern int ultra_low_bus_freq_mode;
++extern void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode,
++ void *iram_addr);
++
++
++#define LPDDR2_FREQ_CHANGE_SIZE 0x1000
++
++
++/* change the DDR frequency. */
++int update_lpddr2_freq(int ddr_rate)
++{
++ if (ddr_rate == curr_ddr_rate)
++ return 0;
++
++ dev_dbg(busfreq_dev, "\nBus freq set to %d start...\n", ddr_rate);
++
++ /*
++ * Flush the TLB, to ensure no TLB maintenance occurs
++ * when DDR is in self-refresh.
++ */
++ local_flush_tlb_all();
++ /* Now change DDR frequency. */
++ mx6_change_lpddr2_freq(ddr_rate,
++ (low_bus_freq_mode | ultra_low_bus_freq_mode),
++ reg_addrs);
++
++ curr_ddr_rate = ddr_rate;
++
++ dev_dbg(busfreq_dev, "\nBus freq set to %d done...\n", ddr_rate);
++
++ return 0;
++}
++
++int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev)
++{
++ struct platform_device *ocram_dev;
++ unsigned int iram_paddr;
++ struct device_node *node;
++ struct gen_pool *iram_pool;
++
++ busfreq_dev = &busfreq_pdev->dev;
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-mmdc");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6sl-mmdc device tree data!\n");
++ return -EINVAL;
++ }
++ mmdc_base = of_iomap(node, 0);
++ WARN(!mmdc_base, "unable to map mmdc registers\n");
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-ccm");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6sl-ccm device tree data!\n");
++ return -EINVAL;
++ }
++ ccm_base = of_iomap(node, 0);
++ WARN(!ccm_base, "unable to map ccm registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6sl-pl310-cache device tree data!\n");
++ return -EINVAL;
++ }
++ l2_base = of_iomap(node, 0);
++ WARN(!l2_base, "unable to map PL310 registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6sl-pl310-cache device tree data!\n");
++ return -EINVAL;
++ }
++ anatop_base = of_iomap(node, 0);
++ WARN(!anatop_base, "unable to map anatop registers\n");
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "mmio-sram");
++ if (!node) {
++ dev_err(busfreq_dev, "%s: failed to find ocram node\n",
++ __func__);
++ return -EINVAL;
++ }
++
++ ocram_dev = of_find_device_by_node(node);
++ if (!ocram_dev) {
++ dev_err(busfreq_dev, "failed to find ocram device!\n");
++ return -EINVAL;
++ }
++
++ iram_pool = dev_get_gen_pool(&ocram_dev->dev);
++ if (!iram_pool) {
++ dev_err(busfreq_dev, "iram pool unavailable!\n");
++ return -EINVAL;
++ }
++
++ reg_addrs[0] = (unsigned long)anatop_base;
++ reg_addrs[1] = (unsigned long)ccm_base;
++ reg_addrs[2] = (unsigned long)mmdc_base;
++ reg_addrs[3] = (unsigned long)l2_base;
++
++ ddr_freq_change_iram_base = (void *)gen_pool_alloc(iram_pool,
++ LPDDR2_FREQ_CHANGE_SIZE);
++ if (!ddr_freq_change_iram_base) {
++ dev_err(busfreq_dev,
++ "Cannot alloc iram for ddr freq change code!\n");
++ return -ENOMEM;
++ }
++
++ iram_paddr = gen_pool_virt_to_phys(iram_pool,
++ (unsigned long)ddr_freq_change_iram_base);
++ /*
++ * Need to remap the area here since we want
++ * the memory region to be executable.
++ */
++ ddr_freq_change_iram_base = __arm_ioremap(iram_paddr,
++ LPDDR2_FREQ_CHANGE_SIZE,
++ MT_MEMORY_NONCACHED);
++ mx6_change_lpddr2_freq = (void *)fncpy(ddr_freq_change_iram_base,
++ &mx6_lpddr2_freq_change, LPDDR2_FREQ_CHANGE_SIZE);
++
++ curr_ddr_rate = ddr_normal_rate;
++
++ return 0;
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk.c 2014-05-15 20:33:35.373850766 +0200
+@@ -1,4 +1,65 @@
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/slab.h>
+ #include <linux/spinlock.h>
+ #include "clk.h"
+
+ DEFINE_SPINLOCK(imx_ccm_lock);
++
++static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
++{
++ struct of_phandle_args phandle = {0};
++ struct clk *clk = ERR_PTR(-ENODEV);
++ char *path;
++
++ path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
++ if (!path)
++ return ERR_PTR(-ENOMEM);
++
++ phandle.np = of_find_node_by_path(path);
++ kfree(path);
++
++ if (phandle.np) {
++ clk = of_clk_get_from_provider(&phandle);
++ of_node_put(phandle.np);
++ }
++ return clk;
++}
++
++struct clk * __init imx_obtain_fixed_clock(
++ const char *name, unsigned long rate)
++{
++ struct clk *clk;
++
++ clk = imx_obtain_fixed_clock_from_dt(name);
++ if (IS_ERR(clk))
++ clk = imx_clk_fixed(name, rate);
++ return clk;
++}
++
++/*
++ * This fixups the register CCM_CSCMR1 write value.
++ * The write/read/divider values of the aclk_podf field
++ * of that register have the relationship described by
++ * the following table:
++ *
++ * write value read value divider
++ * 3b'000 3b'110 7
++ * 3b'001 3b'111 8
++ * 3b'010 3b'100 5
++ * 3b'011 3b'101 6
++ * 3b'100 3b'010 3
++ * 3b'101 3b'011 4
++ * 3b'110 3b'000 1
++ * 3b'111 3b'001 2(default)
++ *
++ * That's why we do the xor operation below.
++ */
++#define CSCMR1_FIXUP 0x00600000
++
++void imx_cscmr1_fixup(u32 *val)
++{
++ *val ^= CSCMR1_FIXUP;
++ return;
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-fixup-div.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-fixup-div.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-fixup-div.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-fixup-div.c 2014-05-15 20:33:35.353850621 +0200
+@@ -0,0 +1,129 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include "clk.h"
++
++#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
++#define div_mask(d) ((1 << (d->width)) - 1)
++
++/**
++ * struct clk_fixup_div - imx integer fixup divider clock
++ * @divider: the parent class
++ * @ops: pointer to clk_ops of parent class
++ * @fixup: a hook to fixup the write value
++ *
++ * The imx fixup divider clock is a subclass of basic clk_divider
++ * with an addtional fixup hook.
++ */
++struct clk_fixup_div {
++ struct clk_divider divider;
++ const struct clk_ops *ops;
++ void (*fixup)(u32 *val);
++};
++
++static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
++{
++ struct clk_divider *divider = to_clk_div(hw);
++
++ return container_of(divider, struct clk_fixup_div, divider);
++}
++
++static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
++
++ return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
++}
++
++static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long *prate)
++{
++ struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
++
++ return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate);
++}
++
++static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long parent_rate)
++{
++ struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
++ struct clk_divider *div = to_clk_div(hw);
++ unsigned int divider, value;
++ unsigned long flags = 0;
++ u32 val;
++
++ divider = parent_rate / rate;
++
++ /* Zero based divider */
++ value = divider - 1;
++
++ if (value > div_mask(div))
++ value = div_mask(div);
++
++ spin_lock_irqsave(div->lock, flags);
++
++ val = readl(div->reg);
++ val &= ~(div_mask(div) << div->shift);
++ val |= value << div->shift;
++ fixup_div->fixup(&val);
++ writel(val, div->reg);
++
++ spin_unlock_irqrestore(div->lock, flags);
++
++ return 0;
++}
++
++static const struct clk_ops clk_fixup_div_ops = {
++ .recalc_rate = clk_fixup_div_recalc_rate,
++ .round_rate = clk_fixup_div_round_rate,
++ .set_rate = clk_fixup_div_set_rate,
++};
++
++struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
++ void __iomem *reg, u8 shift, u8 width,
++ void (*fixup)(u32 *val))
++{
++ struct clk_fixup_div *fixup_div;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ if (!fixup)
++ return ERR_PTR(-EINVAL);
++
++ fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL);
++ if (!fixup_div)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ init.ops = &clk_fixup_div_ops;
++ init.flags = CLK_SET_RATE_PARENT;
++ init.parent_names = parent ? &parent : NULL;
++ init.num_parents = parent ? 1 : 0;
++
++ fixup_div->divider.reg = reg;
++ fixup_div->divider.shift = shift;
++ fixup_div->divider.width = width;
++ fixup_div->divider.lock = &imx_ccm_lock;
++ fixup_div->divider.hw.init = &init;
++ fixup_div->ops = &clk_divider_ops;
++ fixup_div->fixup = fixup;
++
++ clk = clk_register(NULL, &fixup_div->divider.hw);
++ if (IS_ERR(clk))
++ kfree(fixup_div);
++
++ return clk;
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-fixup-mux.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-fixup-mux.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-fixup-mux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-fixup-mux.c 2014-05-15 20:33:35.353850621 +0200
+@@ -0,0 +1,107 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include "clk.h"
++
++#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
++
++/**
++ * struct clk_fixup_mux - imx integer fixup multiplexer clock
++ * @mux: the parent class
++ * @ops: pointer to clk_ops of parent class
++ * @fixup: a hook to fixup the write value
++ *
++ * The imx fixup multiplexer clock is a subclass of basic clk_mux
++ * with an addtional fixup hook.
++ */
++struct clk_fixup_mux {
++ struct clk_mux mux;
++ const struct clk_ops *ops;
++ void (*fixup)(u32 *val);
++};
++
++static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw)
++{
++ struct clk_mux *mux = to_clk_mux(hw);
++
++ return container_of(mux, struct clk_fixup_mux, mux);
++}
++
++static u8 clk_fixup_mux_get_parent(struct clk_hw *hw)
++{
++ struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
++
++ return fixup_mux->ops->get_parent(&fixup_mux->mux.hw);
++}
++
++static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
++{
++ struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
++ struct clk_mux *mux = to_clk_mux(hw);
++ unsigned long flags = 0;
++ u32 val;
++
++ spin_lock_irqsave(mux->lock, flags);
++
++ val = readl(mux->reg);
++ val &= ~(mux->mask << mux->shift);
++ val |= index << mux->shift;
++ fixup_mux->fixup(&val);
++ writel(val, mux->reg);
++
++ spin_unlock_irqrestore(mux->lock, flags);
++
++ return 0;
++}
++
++static const struct clk_ops clk_fixup_mux_ops = {
++ .get_parent = clk_fixup_mux_get_parent,
++ .set_parent = clk_fixup_mux_set_parent,
++};
++
++struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
++ u8 shift, u8 width, const char **parents,
++ int num_parents, void (*fixup)(u32 *val))
++{
++ struct clk_fixup_mux *fixup_mux;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ if (!fixup)
++ return ERR_PTR(-EINVAL);
++
++ fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL);
++ if (!fixup_mux)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ init.ops = &clk_fixup_mux_ops;
++ init.parent_names = parents;
++ init.num_parents = num_parents;
++
++ fixup_mux->mux.reg = reg;
++ fixup_mux->mux.shift = shift;
++ fixup_mux->mux.mask = BIT(width) - 1;
++ fixup_mux->mux.lock = &imx_ccm_lock;
++ fixup_mux->mux.hw.init = &init;
++ fixup_mux->ops = &clk_mux_ops;
++ fixup_mux->fixup = fixup;
++
++ clk = clk_register(NULL, &fixup_mux->mux.hw);
++ if (IS_ERR(clk))
++ kfree(fixup_mux);
++
++ return clk;
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-gate2.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-gate2.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-gate2.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-gate2.c 2014-05-15 20:33:35.373850766 +0200
+@@ -1,6 +1,7 @@
+ /*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -72,7 +73,7 @@
+
+ reg = readl(gate->reg);
+
+- if (((reg >> gate->bit_idx) & 3) == 3)
++ if (((reg >> gate->bit_idx) & 1) == 1)
+ return 1;
+
+ return 0;
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk.h linux-linaro-stable-mx6/arch/arm/mach-imx/clk.h
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk.h 2014-05-15 20:33:35.373850766 +0200
+@@ -6,6 +6,8 @@
+
+ extern spinlock_t imx_ccm_lock;
+
++extern void imx_cscmr1_fixup(u32 *val);
++
+ struct clk *imx_clk_pllv1(const char *name, const char *parent,
+ void __iomem *base);
+
+@@ -22,13 +24,17 @@
+ };
+
+ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+- const char *parent_name, void __iomem *base, u32 div_mask);
++ const char *parent_name, void __iomem *base,
++ u32 div_mask, bool always_on);
+
+ struct clk *clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock);
+
++struct clk * imx_obtain_fixed_clock(
++ const char *name, unsigned long rate);
++
+ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+ {
+@@ -47,6 +53,14 @@
+ u8 width, void __iomem *busy_reg, u8 busy_shift,
+ const char **parent_names, int num_parents);
+
++struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
++ void __iomem *reg, u8 shift, u8 width,
++ void (*fixup)(u32 *val));
++
++struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
++ u8 shift, u8 width, const char **parents,
++ int num_parents, void (*fixup)(u32 *val));
++
+ static inline struct clk *imx_clk_fixed(const char *name, int rate)
+ {
+ return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-imx51-imx53.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-imx51-imx53.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-imx51-imx53.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-imx51-imx53.c 2014-05-15 20:33:35.373850766 +0200
+@@ -123,11 +123,13 @@
+ {
+ int i;
+
++ of_clk_init(NULL);
++
+ clk[dummy] = imx_clk_fixed("dummy", 0);
+- clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
+- clk[osc] = imx_clk_fixed("osc", rate_osc);
+- clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
+- clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
++ clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
++ clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
++ clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
++ clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
+
+ clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
+ lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
+@@ -542,42 +544,12 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_OF
+-static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
+- unsigned long *ckih1, unsigned long *ckih2)
+-{
+- struct device_node *np;
+-
+- /* retrieve the freqency of fixed clocks from device tree */
+- for_each_compatible_node(np, NULL, "fixed-clock") {
+- u32 rate;
+- if (of_property_read_u32(np, "clock-frequency", &rate))
+- continue;
+-
+- if (of_device_is_compatible(np, "fsl,imx-ckil"))
+- *ckil = rate;
+- else if (of_device_is_compatible(np, "fsl,imx-osc"))
+- *osc = rate;
+- else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+- *ckih1 = rate;
+- else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
+- *ckih2 = rate;
+- }
+-}
+-
+ int __init mx51_clocks_init_dt(void)
+ {
+- unsigned long ckil, osc, ckih1, ckih2;
+-
+- clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+- return mx51_clocks_init(ckil, osc, ckih1, ckih2);
++ return mx51_clocks_init(0, 0, 0, 0);
+ }
+
+ int __init mx53_clocks_init_dt(void)
+ {
+- unsigned long ckil, osc, ckih1, ckih2;
+-
+- clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
+- return mx53_clocks_init(ckil, osc, ckih1, ckih2);
++ return mx53_clocks_init(0, 0, 0, 0);
+ }
+-#endif
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-imx6q.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-imx6q.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-imx6q.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-imx6q.c 2014-05-15 20:33:35.373850766 +0200
+@@ -14,7 +14,6 @@
+ #include <linux/types.h>
+ #include <linux/clk.h>
+ #include <linux/clkdev.h>
+-#include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
+@@ -25,154 +24,7 @@
+ #include "common.h"
+ #include "hardware.h"
+
+-#define CCR 0x0
+-#define BM_CCR_WB_COUNT (0x7 << 16)
+-#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
+-#define BM_CCR_RBC_EN (0x1 << 27)
+-
+-#define CCGR0 0x68
+-#define CCGR1 0x6c
+-#define CCGR2 0x70
+-#define CCGR3 0x74
+-#define CCGR4 0x78
+-#define CCGR5 0x7c
+-#define CCGR6 0x80
+-#define CCGR7 0x84
+-
+-#define CLPCR 0x54
+-#define BP_CLPCR_LPM 0
+-#define BM_CLPCR_LPM (0x3 << 0)
+-#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
+-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+-#define BM_CLPCR_SBYOS (0x1 << 6)
+-#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
+-#define BM_CLPCR_VSTBY (0x1 << 8)
+-#define BP_CLPCR_STBY_COUNT 9
+-#define BM_CLPCR_STBY_COUNT (0x3 << 9)
+-#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+-#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
+-#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
+-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
+-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
+-#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
+-#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
+-#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
+-#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
+-#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
+-#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
+-
+-#define CGPR 0x64
+-#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
+-
+-static void __iomem *ccm_base;
+-
+-void imx6q_set_chicken_bit(void)
+-{
+- u32 val = readl_relaxed(ccm_base + CGPR);
+-
+- val |= BM_CGPR_CHICKEN_BIT;
+- writel_relaxed(val, ccm_base + CGPR);
+-}
+-
+-static void imx6q_enable_rbc(bool enable)
+-{
+- u32 val;
+- static bool last_rbc_mode;
+-
+- if (last_rbc_mode == enable)
+- return;
+- /*
+- * need to mask all interrupts in GPC before
+- * operating RBC configurations
+- */
+- imx_gpc_mask_all();
+-
+- /* configure RBC enable bit */
+- val = readl_relaxed(ccm_base + CCR);
+- val &= ~BM_CCR_RBC_EN;
+- val |= enable ? BM_CCR_RBC_EN : 0;
+- writel_relaxed(val, ccm_base + CCR);
+-
+- /* configure RBC count */
+- val = readl_relaxed(ccm_base + CCR);
+- val &= ~BM_CCR_RBC_BYPASS_COUNT;
+- val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
+- writel(val, ccm_base + CCR);
+-
+- /*
+- * need to delay at least 2 cycles of CKIL(32K)
+- * due to hardware design requirement, which is
+- * ~61us, here we use 65us for safe
+- */
+- udelay(65);
+-
+- /* restore GPC interrupt mask settings */
+- imx_gpc_restore_all();
+-
+- last_rbc_mode = enable;
+-}
+-
+-static void imx6q_enable_wb(bool enable)
+-{
+- u32 val;
+- static bool last_wb_mode;
+-
+- if (last_wb_mode == enable)
+- return;
+-
+- /* configure well bias enable bit */
+- val = readl_relaxed(ccm_base + CLPCR);
+- val &= ~BM_CLPCR_WB_PER_AT_LPM;
+- val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+- writel_relaxed(val, ccm_base + CLPCR);
+-
+- /* configure well bias count */
+- val = readl_relaxed(ccm_base + CCR);
+- val &= ~BM_CCR_WB_COUNT;
+- val |= enable ? BM_CCR_WB_COUNT : 0;
+- writel_relaxed(val, ccm_base + CCR);
+-
+- last_wb_mode = enable;
+-}
+-
+-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+-{
+- u32 val = readl_relaxed(ccm_base + CLPCR);
+-
+- val &= ~BM_CLPCR_LPM;
+- switch (mode) {
+- case WAIT_CLOCKED:
+- imx6q_enable_wb(false);
+- imx6q_enable_rbc(false);
+- break;
+- case WAIT_UNCLOCKED:
+- val |= 0x1 << BP_CLPCR_LPM;
+- val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
+- break;
+- case STOP_POWER_ON:
+- val |= 0x2 << BP_CLPCR_LPM;
+- break;
+- case WAIT_UNCLOCKED_POWER_OFF:
+- val |= 0x1 << BP_CLPCR_LPM;
+- val &= ~BM_CLPCR_VSTBY;
+- val &= ~BM_CLPCR_SBYOS;
+- break;
+- case STOP_POWER_OFF:
+- val |= 0x2 << BP_CLPCR_LPM;
+- val |= 0x3 << BP_CLPCR_STBY_COUNT;
+- val |= BM_CLPCR_VSTBY;
+- val |= BM_CLPCR_SBYOS;
+- imx6q_enable_wb(true);
+- imx6q_enable_rbc(true);
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- writel_relaxed(val, ccm_base + CLPCR);
+-
+- return 0;
+-}
++#define CCM_CCGR_OFFSET(index) (index * 2)
+
+ static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
+ static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
+@@ -182,13 +34,15 @@
+ static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
+ static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
+ static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
+-static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
++static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
+ static const char *gpu_axi_sels[] = { "axi", "ahb", };
+ static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
+ static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
+ static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
+ static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
+ static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
++static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
++static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
+ static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+ static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+ static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+@@ -196,15 +50,29 @@
+ static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+ static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
+ static const char *pcie_axi_sels[] = { "axi", "ahb", };
+-static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
++static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
+ static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+ static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
+-static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
++static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
++static const char *emi_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+ static const char *vdo_axi_sels[] = { "axi", "ahb", };
+ static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+ static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
+ "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
+- "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
++ "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
++static const char *cko2_sels[] = {
++ "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
++ "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
++ "usdhc3", "dummy", "arm", "ipu1",
++ "ipu2", "vdo_axi", "osc", "gpu2d_core",
++ "gpu3d_core", "usdhc2", "ssi1", "ssi2",
++ "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
++ "ldb_di0", "ldb_di1", "esai", "eim_slow",
++ "uart_serial", "spdif", "asrc", "hsi_tx",
++};
++static const char *cko_sels[] = { "cko1", "cko2", };
++static const char *lvds_sels[] = { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
++ "dummy", "dummy", "pcie_ref", "sata_ref", "usbphy1", "usbphy2", };
+
+ enum mx6q_clks {
+ dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
+@@ -221,11 +89,11 @@
+ periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
+ asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
+ gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
+- ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
+- ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
+- ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
+- usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
+- emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
++ ldb_di0_podf_unused, ldb_di1_podf_unused, ipu1_di0_pre, ipu1_di1_pre,
++ ipu2_di0_pre, ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf,
++ ssi2_pred, ssi2_podf, ssi3_pred, ssi3_podf, uart_serial_podf,
++ usdhc1_podf, usdhc2_podf, usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf,
++ emi_podf, emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
+ mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
+ can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
+ esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
+@@ -238,14 +106,18 @@
+ pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
+ ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
+ sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
+- usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
++ usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
++ spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, gpt_3m, video_27m,
++ ldb_di0_div_7, ldb_di1_div_7, ldb_di0_div_sel, ldb_di1_div_sel,
++ pll4_audio_div, lvds1_sel, lvds1_in, lvds1_out, caam_mem, caam_aclk,
++ caam_ipg, epit1, epit2, tzasc2, clk_max
+ };
+
+ static struct clk *clk[clk_max];
+ static struct clk_onecell_data clk_data;
+
+ static enum mx6q_clks const clks_init_on[] __initconst = {
+- mmdc_ch0_axi, rom, pll1_sys,
++ mmdc_ch0_axi, rom, arm,
+ };
+
+ static struct clk_div_table clk_enet_ref_table[] = {
+@@ -270,34 +142,24 @@
+ { }
+ };
+
+-int __init mx6q_clocks_init(void)
++static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ {
+ struct device_node *np;
+ void __iomem *base;
+ int i, irq;
++ int ret;
+
+ clk[dummy] = imx_clk_fixed("dummy", 0);
+-
+- /* retrieve the freqency of fixed clocks from device tree */
+- for_each_compatible_node(np, NULL, "fixed-clock") {
+- u32 rate;
+- if (of_property_read_u32(np, "clock-frequency", &rate))
+- continue;
+-
+- if (of_device_is_compatible(np, "fsl,imx-ckil"))
+- clk[ckil] = imx_clk_fixed("ckil", rate);
+- else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
+- clk[ckih] = imx_clk_fixed("ckih", rate);
+- else if (of_device_is_compatible(np, "fsl,imx-osc"))
+- clk[osc] = imx_clk_fixed("osc", rate);
+- }
++ clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
++ clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
++ clk[osc] = imx_obtain_fixed_clock("osc", 0);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+
+ /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
+- if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) {
++ if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
+ post_div_table[1].div = 1;
+ post_div_table[2].div = 1;
+ video_div_table[1].div = 1;
+@@ -305,14 +167,16 @@
+ };
+
+ /* type name parent_name base div_mask */
+- clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
+- clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
+- clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
+- clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
+- clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
+- clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
+- clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
+- clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
++ clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f, false);
++ clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1, false);
++ clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3, false);
++ clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f, false);
++ clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f, false);
++ clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3, false);
++ clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3, false);
++
++ /* name reg shift width parent_names num_parents */
++ clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+
+ /*
+ * Bit 20 is the reserved and read-only bit, we do this only for:
+@@ -332,6 +196,9 @@
+
+ clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
+ clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
++ /* NOTICE: The gate of the lvds1 in/out is used to select the clk direction */
++ clk[lvds1_in] = imx_clk_gate("lvds1_in", NULL, base + 0x160, 12);
++ clk[lvds1_out] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);
+
+ clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
+ clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+@@ -355,15 +222,18 @@
+ clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
+ clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
+ clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
++ clk[gpt_3m] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
++ clk[video_27m] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
+
+ clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+ clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
+ clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+
+- np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
++ np = ccm_node;
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+- ccm_base = base;
++ imx6_pm_set_ccm_base(base);
+
+ /* name reg shift width parent_names num_parents */
+ clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
+@@ -385,29 +255,33 @@
+ clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
+ clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+ clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+- clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+- clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+- clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+- clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+- clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
+- clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
+- clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
+- clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
++ clk[ldb_di0_div_sel] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
++ clk[ldb_di1_div_sel] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
++ clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
++ clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
++ clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
++ clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
++ clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
++ clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
++ clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
++ clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
+ clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
+ clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
+- clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
+- clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
+- clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
+- clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+- clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+- clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
+- clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
++ clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+ clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
+- clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
+- clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
++ clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
++ clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
+ clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
+ clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
+ clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
++ clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
++ clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
+
+ /* name reg shift width busy: reg, shift parent_names num_parents */
+ clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
+@@ -417,7 +291,7 @@
+ clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
+ clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
+ clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
+- clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
++ clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
+ clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
+ clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
+ clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
+@@ -432,9 +306,9 @@
+ clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
+ clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
+ clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+- clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
++ clk[ldb_di0_div_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
+ clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+- clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
++ clk[ldb_di1_div_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
+ clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
+ clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
+ clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
+@@ -453,10 +327,11 @@
+ clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
+ clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
+ clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
+- clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3);
+- clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3);
++ clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
++ clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
+ clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
+ clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
++ clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
+
+ /* name parent_name reg shift width busy: reg, shift */
+ clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
+@@ -468,6 +343,9 @@
+ /* name parent_name reg shift */
+ clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
+ clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
++ clk[caam_mem] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
++ clk[caam_aclk] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
++ clk[caam_ipg] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
+ clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
+ clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
+ clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
+@@ -478,10 +356,19 @@
+ clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
+ clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
+ clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
++ clk[epit1] = imx_clk_gate2("epit1", "ipg", base + 0x6c, 12);
++ clk[epit2] = imx_clk_gate2("epit2", "ipg", base + 0x6c, 14);
+ clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
+ clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
+ clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
+- clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
++ if (cpu_is_imx6dl())
++ /*
++ * The multiplexer and divider of imx6q clock gpu3d_shader get
++ * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
++ */
++ clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
++ else
++ clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
+ clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
+ clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
+ clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
+@@ -490,16 +377,25 @@
+ clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
+ clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
+ clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
++ clk[tzasc2] = imx_clk_gate2("tzasc2", "mmdc_ch0_axi_podf", base + 0x70, 24);
++ clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
+ clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
+ clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
+ clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
+ clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
+ clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
+- clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
+- clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
+ clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
++ clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
++ clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_div_sel", base + 0x74, 14);
+ clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
+- clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
++ if (cpu_is_imx6dl())
++ /*
++ * The multiplexer and divider of the imx6q clock gpu2d get
++ * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
++ */
++ clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
++ else
++ clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
+ clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
+ clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
+ clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
+@@ -518,9 +414,13 @@
+ clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
+ clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
+ clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
++ clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
+ clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
+ clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
+ clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
++ clk[ssi1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
++ clk[ssi2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
++ clk[ssi3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
+ clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
+ clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
+ clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
+@@ -528,31 +428,63 @@
+ clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
+ clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
+ clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
++ clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
+ clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
+ clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
+ clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
++ clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
+
+ for (i = 0; i < ARRAY_SIZE(clk); i++)
+ if (IS_ERR(clk[i]))
+ pr_err("i.MX6q clk %d: register failed with %ld\n",
+ i, PTR_ERR(clk[i]));
+
++ /* Initialize clock gate status */
++ writel_relaxed(1 << CCM_CCGR_OFFSET(11) |
++ 3 << CCM_CCGR_OFFSET(1) |
++ 3 << CCM_CCGR_OFFSET(0), base + 0x68);
++ if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
++ writel_relaxed(3 << CCM_CCGR_OFFSET(11) |
++ 3 << CCM_CCGR_OFFSET(10), base + 0x6c);
++ else
++ writel_relaxed(3 << CCM_CCGR_OFFSET(10), base + 0x6c);
++ writel_relaxed(1 << CCM_CCGR_OFFSET(12) |
++ 3 << CCM_CCGR_OFFSET(11) |
++ 3 << CCM_CCGR_OFFSET(10) |
++ 3 << CCM_CCGR_OFFSET(9) |
++ 3 << CCM_CCGR_OFFSET(8), base + 0x70);
++ writel_relaxed(3 << CCM_CCGR_OFFSET(14) |
++ 1 << CCM_CCGR_OFFSET(13) |
++ 3 << CCM_CCGR_OFFSET(12) |
++ 1 << CCM_CCGR_OFFSET(11) |
++ 3 << CCM_CCGR_OFFSET(10), base + 0x74);
++ writel_relaxed(3 << CCM_CCGR_OFFSET(7) |
++ 3 << CCM_CCGR_OFFSET(6) |
++ 3 << CCM_CCGR_OFFSET(4), base + 0x78);
++ writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c);
++ writel_relaxed(0, base + 0x80);
++
+ clk_data.clks = clk;
+ clk_data.clk_num = ARRAY_SIZE(clk);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+ clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
+ clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
++ clk_register_clkdev(clk[gpt_3m], "gpt_3m", "imx-gpt.0");
+ clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
+ clk_register_clkdev(clk[ahb], "ahb", NULL);
+ clk_register_clkdev(clk[cko1], "cko1", NULL);
+ clk_register_clkdev(clk[arm], NULL, "cpu0");
+
+- if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
++ if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
+ clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
+ clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
+ }
+
++ if (cpu_is_imx6dl()) {
++ clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]);
++ }
++
+ /*
+ * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+ * We can not get the 100MHz from the pll2_pfd0_352m.
+@@ -560,6 +492,20 @@
+ */
+ clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+
++ /* Set the parent clks of PCIe lvds1 and pcie_axi to be sata ref, axi */
++ if (clk_set_parent(clk[lvds1_sel], clk[sata_ref]))
++ pr_err("Failed to set PCIe bus parent clk.\n");
++ if (clk_set_parent(clk[pcie_axi_sel], clk[axi]))
++ pr_err("Failed to set PCIe parent clk.\n");
++
++
++ /* gpu clock initilazation */
++ clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]);
++ clk_set_rate(clk[gpu3d_shader], 594000000);
++ clk_set_parent(clk[gpu3d_core_sel], clk[mmdc_ch0_axi]);
++ clk_set_rate(clk[gpu3d_core], 528000000);
++ clk_set_parent(clk[gpu2d_core_sel], clk[pll3_usb_otg]);
++
+ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+ clk_prepare_enable(clk[clks_init_on[i]]);
+
+@@ -568,14 +514,57 @@
+ clk_prepare_enable(clk[usbphy2_gate]);
+ }
+
++ /* ipu clock initialization */
++ clk_set_parent(clk[ldb_di0_sel], clk[pll2_pfd0_352m]);
++ clk_set_parent(clk[ldb_di1_sel], clk[pll2_pfd0_352m]);
++ clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
++ clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
++ clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
++ clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
++ clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
++ clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
++ clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
++ clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
++ if (cpu_is_imx6dl()) {
++ clk_set_rate(clk[pll3_pfd1_540m], 540000000);
++ clk_set_parent(clk[ipu1_sel], clk[pll3_pfd1_540m]);
++ clk_set_parent(clk[axi_sel], clk[pll3_pfd1_540m]);
++ /* set epdc/pxp axi clock to 200Mhz */
++ clk_set_parent(clk[ipu2_sel], clk[pll2_pfd2_396m]);
++ clk_set_rate(clk[ipu2], 200000000);
++ } else if (cpu_is_imx6q()) {
++ clk_set_parent(clk[ipu1_sel], clk[mmdc_ch0_axi]);
++ clk_set_parent(clk[ipu2_sel], clk[mmdc_ch0_axi]);
++ }
++
++ /*
++ * Let's initially set up CLKO with OSC24M, since this configuration
++ * is widely used by imx6q board designs to clock audio codec.
++ */
++ ret = clk_set_parent(clk[cko2_sel], clk[osc]);
++ if (!ret)
++ ret = clk_set_parent(clk[cko], clk[cko2]);
++ if (ret)
++ pr_warn("failed to set up CLKO: %d\n", ret);
++
++ /* Audio clocks */
++ clk_set_parent(clk[ssi1_sel], clk[pll4_audio_div]);
++ clk_set_parent(clk[ssi2_sel], clk[pll4_audio_div]);
++ clk_set_parent(clk[ssi3_sel], clk[pll4_audio_div]);
++ clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
++ clk_set_parent(clk[asrc_sel], clk[pll3_usb_otg]);
++ clk_set_rate(clk[asrc_sel], 7500000);
++
++ /* Set pll4_audio to a value that can derive 5K-88.2KHz and 8K-96KHz */
++ clk_set_rate(clk[pll4_audio_div], 541900800);
++
+ /* Set initial power mode */
+- imx6q_set_lpm(WAIT_CLOCKED);
++ imx6_set_lpm(WAIT_CLOCKED);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
+ irq = irq_of_parse_and_map(np, 0);
+ mxc_timer_init(base, irq);
+-
+- return 0;
+ }
++CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-imx6sl.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-imx6sl.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-imx6sl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-imx6sl.c 2014-05-15 20:33:35.373850766 +0200
+@@ -0,0 +1,493 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#define CCM_CCDR_OFFSET 0x4
++#define ANATOP_PLL_USB1 0x10
++#define ANATOP_PLL_USB2 0x20
++#define ANATOP_PLL_ENET 0xE0
++#define ANATOP_PLL_BYPASS_OFFSET (1 << 16)
++#define ANATOP_PLL_ENABLE_OFFSET (1 << 13)
++#define ANATOP_PLL_POWER_OFFSET (1 << 12)
++#define ANATOP_PFD_480n_OFFSET 0xf0
++#define ANATOP_PFD_528n_OFFSET 0x100
++#define PFD0_CLKGATE (1 << 7)
++#define PFD1_CLK_GATE (1 << 15)
++#define PFD2_CLK_GATE (1 << 23)
++#define PFD3_CLK_GATE (1 << 31)
++#define CCDR_CH0_HS_BYP 17
++#define OSC_RATE 24000000
++
++#define CCM_CCGR_OFFSET(index) (index * 2)
++
++#include <linux/clk.h>
++#include <linux/clkdev.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <dt-bindings/clock/imx6sl-clock.h>
++
++#include "clk.h"
++#include "common.h"
++
++static bool uart_from_osc;
++static const char const *step_sels[] = { "osc", "pll2_pfd2", };
++static const char const *pll1_sw_sels[] = { "pll1_sys", "step", };
++static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
++static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", };
++static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
++static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
++static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
++static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2", };
++static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2", };
++static const char const *csi_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
++static const char const *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
++static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
++static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
++static const char const *perclk_sels[] = { "ipg", "osc", };
++static const char const *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
++static const char const *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
++static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
++static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
++static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
++static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
++static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
++static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
++static const char const *uart_sels[] = { "pll3_80m", "uart_osc_4M", };
++
++static struct clk_div_table clk_enet_ref_table[] = {
++ { .val = 0, .div = 20, },
++ { .val = 1, .div = 10, },
++ { .val = 2, .div = 5, },
++ { .val = 3, .div = 4, },
++ { }
++};
++
++static struct clk_div_table post_div_table[] = {
++ { .val = 2, .div = 1, },
++ { .val = 1, .div = 2, },
++ { .val = 0, .div = 4, },
++ { }
++};
++
++static struct clk_div_table video_div_table[] = {
++ { .val = 0, .div = 1, },
++ { .val = 1, .div = 2, },
++ { .val = 2, .div = 1, },
++ { .val = 3, .div = 4, },
++ { }
++};
++
++static struct clk *clks[IMX6SL_CLK_CLK_END];
++static struct clk_onecell_data clk_data;
++static u32 cur_arm_podf;
++static u32 pll1_org_rate;
++
++extern int low_bus_freq_mode;
++extern int audio_bus_freq_mode;
++
++/*
++ * On MX6SL, need to ensure that the ARM:IPG clock ratio is maintained
++ * within 12:5 when the clocks to ARM are gated when the SOC enters
++ * WAIT mode. This is necessary to avoid WAIT mode issue (an early
++ * interrupt waking up the ARM).
++ * This function will set the ARM clk to max value within the 12:5 limit.
++ */
++void imx6sl_set_wait_clk(bool enter)
++{
++ u32 parent_rate;
++
++ if (enter) {
++ u32 wait_podf;
++ u32 new_parent_rate = OSC_RATE;
++ u32 ipg_rate = clk_get_rate(clks[IMX6SL_CLK_IPG]);
++ u32 max_arm_wait_clk = (12 * ipg_rate) / 5;
++ parent_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SW]);
++ cur_arm_podf = parent_rate / clk_get_rate(clks[IMX6SL_CLK_ARM]);
++ if (low_bus_freq_mode) {
++ /*
++ * IPG clk is at 12MHz at this point, we can only run
++ * ARM at a max of 28.8MHz. So we need to set ARM
++ * to run from the 24MHz OSC, as there is no way to
++ * get 28.8MHz when ARM is sourced from PLL1.
++ */
++ clk_set_parent(clks[IMX6SL_CLK_STEP],
++ clks[IMX6SL_CLK_OSC]);
++ clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
++ clks[IMX6SL_CLK_STEP]);
++ } else if (audio_bus_freq_mode) {
++ /*
++ * In this mode ARM is from PLL2_PFD2 (396MHz),
++ * but IPG is at 12MHz. Need to switch ARM to run
++ * from the bypassed PLL1 clocks so that we can run
++ * ARM at 24MHz.
++ */
++ pll1_org_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SYS]);
++ /* Ensure PLL1 is at 24MHz. */
++ clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], OSC_RATE);
++ clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_PLL1_SYS]);
++ } else
++ new_parent_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SW]);
++ wait_podf = (new_parent_rate + max_arm_wait_clk - 1) /
++ max_arm_wait_clk;
++
++ clk_set_rate(clks[IMX6SL_CLK_ARM], new_parent_rate / wait_podf);
++ } else {
++ if (low_bus_freq_mode)
++ /* Move ARM back to PLL1. */
++ clk_set_parent(clks[IMX6SL_CLK_PLL1_SW],
++ clks[IMX6SL_CLK_PLL1_SYS]);
++ else if (audio_bus_freq_mode) {
++ /* Move ARM back to PLL2_PFD2 via STEP_CLK. */
++ clk_set_parent(clks[IMX6SL_CLK_PLL1_SW], clks[IMX6SL_CLK_STEP]);
++ clk_set_rate(clks[IMX6SL_CLK_PLL1_SYS], pll1_org_rate);
++ }
++ parent_rate = clk_get_rate(clks[IMX6SL_CLK_PLL1_SW]);
++ clk_set_rate(clks[IMX6SL_CLK_ARM], parent_rate / cur_arm_podf);
++ }
++}
++
++static int __init setup_uart_clk(char *uart_rate)
++{
++ uart_from_osc = true;
++ return 1;
++}
++
++__setup("uart_at_4M", setup_uart_clk);
++
++static void __init imx6sl_clocks_init(struct device_node *ccm_node)
++{
++ struct device_node *np;
++ void __iomem *base;
++ int irq;
++ int ret;
++ int i;
++ u32 reg;
++
++ clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
++ clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
++ clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
++ base = of_iomap(np, 0);
++ WARN_ON(!base);
++
++ /* type name parent base div_mask */
++ clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f, true);
++ clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1, true);
++ clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3, false);
++ clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f, false);
++ clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f, false);
++ clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3, false);
++ clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3, false);
++
++ /*
++ * usbphy1 and usbphy2 are implemented as dummy gates using reserve
++ * bit 20. They are used by phy driver to keep the refcount of
++ * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
++ * turned on during boot, and software will not need to control it
++ * anymore after that.
++ */
++ clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
++ clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
++ clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
++ clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
++
++ /* dev name parent_name flags reg shift width div: flags, div_table lock */
++ clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
++ clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
++ clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
++
++ /* name parent_name reg idx */
++ clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0);
++ clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1);
++ clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2);
++ clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0);
++ clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1);
++ clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2);
++ clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3);
++
++ /* name parent_name mult div */
++ clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2);
++ clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
++ clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
++ clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
++ clks[IMX6SL_CLK_UART_OSC_4M] = imx_clk_fixed_factor("uart_osc_4M", "osc", 1, 6);
++
++ /* Ensure all PFDs but PLL2_PFD2 are disabled. */
++ reg = readl_relaxed(base + ANATOP_PFD_480n_OFFSET);
++ reg |= (PFD0_CLKGATE | PFD1_CLK_GATE | PFD2_CLK_GATE | PFD3_CLK_GATE);
++ writel_relaxed(reg, base + ANATOP_PFD_480n_OFFSET);
++ reg = readl_relaxed(base + ANATOP_PFD_528n_OFFSET);
++ reg |= (PFD0_CLKGATE | PFD1_CLK_GATE);
++ writel_relaxed(reg, base + ANATOP_PFD_528n_OFFSET);
++
++ /* Ensure Unused PLLs are disabled. */
++ reg = readl_relaxed(base + ANATOP_PLL_USB1);
++ reg |= ANATOP_PLL_BYPASS_OFFSET;
++ reg &= ~(ANATOP_PLL_ENABLE_OFFSET | ANATOP_PLL_POWER_OFFSET);
++ writel_relaxed(reg, base + ANATOP_PLL_USB1);
++
++ reg = readl_relaxed(base + ANATOP_PLL_USB2);
++ reg |= ANATOP_PLL_BYPASS_OFFSET;
++ reg &= ~(ANATOP_PLL_ENABLE_OFFSET | ANATOP_PLL_POWER_OFFSET);
++ writel_relaxed(reg, base + ANATOP_PLL_USB2);
++
++ reg = readl_relaxed(base + ANATOP_PLL_ENET);
++ reg |= (ANATOP_PLL_BYPASS_OFFSET | ANATOP_PLL_POWER_OFFSET);
++ reg &= ~ANATOP_PLL_ENABLE_OFFSET;
++ writel_relaxed(reg, base + ANATOP_PLL_ENET);
++
++ np = ccm_node;
++ base = of_iomap(np, 0);
++ WARN_ON(!base);
++ imx6_pm_set_ccm_base(base);
++
++ /* name reg shift width parent_names num_parents */
++ clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
++ clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
++ clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels));
++ clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
++ clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
++ clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
++ clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
++ clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
++ clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
++ clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels));
++ clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
++ clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
++ clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
++ clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
++ clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux_flags("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux_flags("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
++ clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
++ clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux_flags("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
++ clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
++
++ /* name reg shift width busy: reg, shift parent_names num_parents */
++ clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
++ clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
++
++ /* name parent_name reg shift width */
++ clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3);
++ clks[IMX6SL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
++ clks[IMX6SL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
++ clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
++ clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
++ clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3);
++ clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
++ clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
++ clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
++ clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
++ clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
++ clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
++ clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
++ clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
++ clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
++ clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
++ clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3);
++ clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3);
++ clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3);
++ clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3);
++ clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3);
++ clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3);
++ clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup);
++ clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3);
++ clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3);
++ clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3);
++ clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3);
++ clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3);
++ clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3);
++ clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
++ clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
++ clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6);
++
++ /* name parent_name reg shift width busy: reg, shift */
++ clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
++ clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
++ clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
++
++ /* name parent_name reg shift */
++ clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
++ clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
++ clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
++ clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
++ clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
++ clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
++ clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
++ clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
++ clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20);
++ clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
++ clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26);
++ clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
++ clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
++ clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
++ clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
++ clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0);
++ clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2);
++ clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4);
++ clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6);
++ clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8);
++ clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10);
++ clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28);
++ clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
++ clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
++ clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
++ clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
++ clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
++ clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
++ clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
++ clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
++ clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
++ clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
++ clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
++ clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
++ clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
++ clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
++ clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
++ clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
++ clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
++
++ for (i = 0; i < ARRAY_SIZE(clks); i++)
++ if (IS_ERR(clks[i]))
++ pr_err("i.MX6SL clk %d: register failed with %ld\n",
++ i, PTR_ERR(clks[i]));
++
++ /* Initialize clock gate status */
++ writel_relaxed(1 << CCM_CCGR_OFFSET(11) |
++ 3 << CCM_CCGR_OFFSET(1) |
++ 3 << CCM_CCGR_OFFSET(0), base + 0x68);
++ writel_relaxed(3 << CCM_CCGR_OFFSET(10), base + 0x6c);
++ writel_relaxed(1 << CCM_CCGR_OFFSET(11) |
++ 3 << CCM_CCGR_OFFSET(10) |
++ 3 << CCM_CCGR_OFFSET(9) |
++ 3 << CCM_CCGR_OFFSET(8), base + 0x70);
++ writel_relaxed(3 << CCM_CCGR_OFFSET(14) |
++ 3 << CCM_CCGR_OFFSET(13) |
++ 3 << CCM_CCGR_OFFSET(12) |
++ 3 << CCM_CCGR_OFFSET(11) |
++ 3 << CCM_CCGR_OFFSET(10), base + 0x74);
++ writel_relaxed(3 << CCM_CCGR_OFFSET(7) |
++ 3 << CCM_CCGR_OFFSET(4), base + 0x78);
++ writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c);
++ writel_relaxed(0, base + 0x80);
++
++ clk_data.clks = clks;
++ clk_data.clk_num = ARRAY_SIZE(clks);
++ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
++
++ clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
++ clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
++
++ /* Ensure the AHB clk is at 132MHz. */
++ ret = clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
++ if (ret)
++ pr_warn("%s: failed to set AHB clock rate %d\n", __func__, ret);
++
++ /*
++ * To prevent the bus clock from being disabled accidently when
++ * clk_disable() gets called on child clock, let's increment the use
++ * count of IPG clock by initially calling clk_prepare_enable() on it.
++ */
++ ret = clk_prepare_enable(clks[IMX6SL_CLK_IPG]);
++ if (ret)
++ pr_warn("%s: failed to enable IPG clock %d\n", __func__, ret);
++
++ /*
++ * Make sure the ARM clk is enabled to maintain the correct usecount
++ * and enabling/disabling of parent PLLs.
++ */
++ ret = clk_prepare_enable(clks[IMX6SL_CLK_ARM]);
++ if (ret)
++ pr_warn("%s: failed to enable ARM core clock %d\n",
++ __func__, ret);
++
++ /*
++ * Make sure the MMDC clk is enabled to maintain the correct usecount
++ * and enabling/disabling of parent PLLs.
++ */
++ ret = clk_prepare_enable(clks[IMX6SL_CLK_MMDC_ROOT]);
++ if (ret)
++ pr_warn("%s: failed to enable MMDC clock %d\n",
++ __func__, ret);
++
++ if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
++ clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
++ clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
++ }
++
++ clk_set_parent(clks[IMX6SL_CLK_GPU2D_OVG_SEL],
++ clks[IMX6SL_CLK_PLL2_BUS]);
++ clk_set_parent(clks[IMX6SL_CLK_GPU2D_SEL], clks[IMX6SL_CLK_PLL2_BUS]);
++
++ /* Initialize Video PLLs to valid frequency (650MHz). */
++ clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO], 650000000);
++ /* set PLL5 video as lcdif pix parent clock */
++ clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
++ clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
++ clk_set_parent(clks[IMX6SL_CLK_EPDC_PIX_SEL],
++ clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
++
++ clk_set_parent(clks[IMX6SL_CLK_EPDC_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
++ clk_set_rate(clks[IMX6SL_CLK_EPDC_AXI], 200000000);
++ clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
++ clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
++ clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
++ clk_set_rate(clks[IMX6SL_CLK_LCDIF_AXI], 200000000);
++
++ /* Audio clocks */
++ clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
++
++ /* set extern_audio to be sourced from PLL4/audio PLL */
++ clk_set_parent(clks[IMX6SL_CLK_EXTERN_AUDIO_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
++ /* set extern_audio to 24MHz */
++ clk_set_rate(clks[IMX6SL_CLK_PLL4_AUDIO], 24000000);
++ clk_set_rate(clks[IMX6SL_CLK_EXTERN_AUDIO], 24000000);
++
++ /* set SSI2 parent to PLL4 */
++ clk_set_parent(clks[IMX6SL_CLK_SSI2_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);
++ clk_set_rate(clks[IMX6SL_CLK_SSI2], 24000000);
++
++ /* set perclk to source from OSC 24MHz */
++ clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
++
++ /* Set initial power mode */
++ imx6_set_lpm(WAIT_CLOCKED);
++
++ /* Ensure that CH0 handshake is bypassed. */
++ reg = readl_relaxed(base + CCM_CCDR_OFFSET);
++ reg |= 1 << CCDR_CH0_HS_BYP;
++ writel_relaxed(reg, base + CCM_CCDR_OFFSET);
++
++ /* Set the UART parent if needed. */
++ if (uart_from_osc)
++ ret = clk_set_parent(clks[IMX6SL_CLK_UART_SEL], clks[IMX6SL_CLK_UART_OSC_4M]);
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
++ base = of_iomap(np, 0);
++ WARN_ON(!base);
++ irq = irq_of_parse_and_map(np, 0);
++ mxc_timer_init(base, irq);
++}
++CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-pfd.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-pfd.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-pfd.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-pfd.c 2014-05-15 20:33:35.373850766 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -17,6 +17,8 @@
+ #include <linux/err.h>
+ #include "clk.h"
+
++#define BYPASS_RATE 24000000
++
+ /**
+ * struct clk_pfd - IMX PFD clock
+ * @clk_hw: clock source
+@@ -62,9 +64,14 @@
+ u64 tmp = parent_rate;
+ u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
+
+- tmp *= 18;
+- do_div(tmp, frac);
+-
++ /*
++ * If the parent PLL is in bypass state, the PFDs
++ * are also in bypass state.
++ */
++ if (tmp != BYPASS_RATE) {
++ tmp *= 18;
++ do_div(tmp, frac);
++ }
+ return tmp;
+ }
+
+@@ -74,17 +81,22 @@
+ u64 tmp = *prate;
+ u8 frac;
+
+- tmp = tmp * 18 + rate / 2;
+- do_div(tmp, rate);
+- frac = tmp;
+- if (frac < 12)
+- frac = 12;
+- else if (frac > 35)
+- frac = 35;
+- tmp = *prate;
+- tmp *= 18;
+- do_div(tmp, frac);
+-
++ /*
++ * If the parent PLL is in bypass state, the PFDs
++ * are also in bypass state.
++ */
++ if (tmp != BYPASS_RATE) {
++ tmp = tmp * 18 + rate / 2;
++ do_div(tmp, rate);
++ frac = tmp;
++ if (frac < 12)
++ frac = 12;
++ else if (frac > 35)
++ frac = 35;
++ tmp = *prate;
++ tmp *= 18;
++ do_div(tmp, frac);
++ }
+ return tmp;
+ }
+
+@@ -95,6 +107,9 @@
+ u64 tmp = parent_rate;
+ u8 frac;
+
++ if (tmp == BYPASS_RATE)
++ return 0;
++
+ tmp = tmp * 18 + rate / 2;
+ do_div(tmp, rate);
+ frac = tmp;
+@@ -109,12 +124,24 @@
+ return 0;
+ }
+
++static int clk_pfd_is_enabled(struct clk_hw *hw)
++{
++ struct clk_pfd *pfd = to_clk_pfd(hw);
++
++ if (readl_relaxed(pfd->reg) &
++ (1 << ((pfd->idx + 1) * 8 - 1)))
++ return 0;
++
++ return 1;
++}
++
+ static const struct clk_ops clk_pfd_ops = {
+ .enable = clk_pfd_enable,
+ .disable = clk_pfd_disable,
+ .recalc_rate = clk_pfd_recalc_rate,
+ .round_rate = clk_pfd_round_rate,
+ .set_rate = clk_pfd_set_rate,
++ .is_enabled = clk_pfd_is_enabled,
+ };
+
+ struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-pllv3.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-pllv3.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-pllv3.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-pllv3.c 2014-05-15 20:33:35.373850766 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -25,12 +25,15 @@
+ #define BM_PLL_ENABLE (0x1 << 13)
+ #define BM_PLL_BYPASS (0x1 << 16)
+ #define BM_PLL_LOCK (0x1 << 31)
++#define BYPASS_RATE 24000000
++#define BYPASS_MASK 0x10000
+
+ /**
+ * struct clk_pllv3 - IMX PLL clock version 3
+ * @clk_hw: clock source
+ * @base: base address of PLL registers
+ * @powerup_set: set POWER bit to power up the PLL
++ * @always_on : Leave the PLL powered up all the time.
+ * @div_mask: mask of divider bits
+ *
+ * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
+@@ -40,52 +43,72 @@
+ struct clk_hw hw;
+ void __iomem *base;
+ bool powerup_set;
++ bool always_on;
+ u32 div_mask;
++ u32 rate_req;
+ };
+
+ #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
+
+-static int clk_pllv3_prepare(struct clk_hw *hw)
++static int clk_pllv3_wait_for_lock(struct clk_pllv3 *pll, u32 timeout_ms)
+ {
+- struct clk_pllv3 *pll = to_clk_pllv3(hw);
+- unsigned long timeout = jiffies + msecs_to_jiffies(10);
+- u32 val;
++ unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
++ u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
+
+- val = readl_relaxed(pll->base);
+- val &= ~BM_PLL_BYPASS;
+- if (pll->powerup_set)
+- val |= BM_PLL_POWER;
+- else
+- val &= ~BM_PLL_POWER;
+- writel_relaxed(val, pll->base);
++ /* No need to wait for lock when pll is power down */
++ if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
++ return 0;
+
+ /* Wait for PLL to lock */
+- while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
++ do {
++ if (readl_relaxed(pll->base) & BM_PLL_LOCK)
++ break;
+ if (time_after(jiffies, timeout))
+- return -ETIMEDOUT;
++ break;
++ } while (1);
+
+- return 0;
++ if (readl_relaxed(pll->base) & BM_PLL_LOCK)
++ return 0;
++ else
++ return -ETIMEDOUT;
+ }
+
+-static void clk_pllv3_unprepare(struct clk_hw *hw)
++static int clk_pllv3_power_up_down(struct clk_hw *hw, bool enable)
+ {
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+- u32 val;
++ u32 val, ret = 0;
+
+- val = readl_relaxed(pll->base);
+- val |= BM_PLL_BYPASS;
+- if (pll->powerup_set)
+- val &= ~BM_PLL_POWER;
+- else
+- val |= BM_PLL_POWER;
+- writel_relaxed(val, pll->base);
++ if (enable) {
++ val = readl_relaxed(pll->base);
++ val &= ~BM_PLL_BYPASS;
++ if (pll->powerup_set)
++ val |= BM_PLL_POWER;
++ else
++ val &= ~BM_PLL_POWER;
++ writel_relaxed(val, pll->base);
++
++ ret = clk_pllv3_wait_for_lock(pll, 10);
++ } else {
++ val = readl_relaxed(pll->base);
++ val |= BM_PLL_BYPASS;
++ if (pll->powerup_set)
++ val &= ~BM_PLL_POWER;
++ else
++ val |= BM_PLL_POWER;
++ writel_relaxed(val, pll->base);
++ }
++ return ret;
+ }
+
++
+ static int clk_pllv3_enable(struct clk_hw *hw)
+ {
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ u32 val;
+
++ if (pll->rate_req != BYPASS_RATE)
++ clk_pllv3_power_up_down(hw, true);
++
+ val = readl_relaxed(pll->base);
+ val |= BM_PLL_ENABLE;
+ writel_relaxed(val, pll->base);
+@@ -99,8 +122,12 @@
+ u32 val;
+
+ val = readl_relaxed(pll->base);
+- val &= ~BM_PLL_ENABLE;
++ if (!pll->always_on)
++ val &= ~BM_PLL_ENABLE;
+ writel_relaxed(val, pll->base);
++
++ if (pll->rate_req != BYPASS_RATE)
++ clk_pllv3_power_up_down(hw, false);
+ }
+
+ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
+@@ -108,8 +135,15 @@
+ {
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ u32 div = readl_relaxed(pll->base) & pll->div_mask;
++ u32 bypass = readl_relaxed(pll->base) & BYPASS_MASK;
++ u32 rate;
++
++ if (pll->rate_req == BYPASS_RATE && bypass)
++ rate = BYPASS_RATE;
++ else
++ rate = (div == 1) ? parent_rate * 22 : parent_rate * 20;
+
+- return (div == 1) ? parent_rate * 22 : parent_rate * 20;
++ return rate;
+ }
+
+ static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
+@@ -117,6 +151,10 @@
+ {
+ unsigned long parent_rate = *prate;
+
++ /* If the PLL is bypassed, its rate is 24MHz. */
++ if (rate == BYPASS_RATE)
++ return BYPASS_RATE;
++
+ return (rate >= parent_rate * 22) ? parent_rate * 22 :
+ parent_rate * 20;
+ }
+@@ -127,6 +165,22 @@
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ u32 val, div;
+
++ pll->rate_req = rate;
++ val = readl_relaxed(pll->base);
++
++ /* If the PLL is bypassed, its rate is 24MHz. */
++ if (rate == BYPASS_RATE) {
++ /* Set the bypass bit. */
++ val |= BM_PLL_BYPASS;
++ /* Power down the PLL. */
++ if (pll->powerup_set)
++ val &= ~BM_PLL_POWER;
++ else
++ val |= BM_PLL_POWER;
++ writel_relaxed(val, pll->base);
++
++ return 0;
++ }
+ if (rate == parent_rate * 22)
+ div = 1;
+ else if (rate == parent_rate * 20)
+@@ -139,12 +193,10 @@
+ val |= div;
+ writel_relaxed(val, pll->base);
+
+- return 0;
++ return clk_pllv3_wait_for_lock(pll, 10);
+ }
+
+ static const struct clk_ops clk_pllv3_ops = {
+- .prepare = clk_pllv3_prepare,
+- .unprepare = clk_pllv3_unprepare,
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_recalc_rate,
+@@ -157,6 +209,10 @@
+ {
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ u32 div = readl_relaxed(pll->base) & pll->div_mask;
++ u32 bypass = readl_relaxed(pll->base) & BYPASS_MASK;
++
++ if (pll->rate_req == BYPASS_RATE && bypass)
++ return BYPASS_RATE;
+
+ return parent_rate * div / 2;
+ }
+@@ -169,6 +225,9 @@
+ unsigned long max_rate = parent_rate * 108 / 2;
+ u32 div;
+
++ if (rate == BYPASS_RATE)
++ return BYPASS_RATE;
++
+ if (rate > max_rate)
+ rate = max_rate;
+ else if (rate < min_rate)
+@@ -186,21 +245,36 @@
+ unsigned long max_rate = parent_rate * 108 / 2;
+ u32 val, div;
+
+- if (rate < min_rate || rate > max_rate)
++ if (rate != BYPASS_RATE && (rate < min_rate || rate > max_rate))
+ return -EINVAL;
+
++ pll->rate_req = rate;
++ val = readl_relaxed(pll->base);
++
++ if (rate == BYPASS_RATE) {
++ /*
++ * Set the PLL in bypass mode if rate requested is
++ * BYPASS_RATE.
++ */
++ val |= BM_PLL_BYPASS;
++ /* Power down the PLL. */
++ if (pll->powerup_set)
++ val &= ~BM_PLL_POWER;
++ else
++ val |= BM_PLL_POWER;
++ writel_relaxed(val, pll->base);
++ return 0;
++ }
+ div = rate * 2 / parent_rate;
+ val = readl_relaxed(pll->base);
+ val &= ~pll->div_mask;
+ val |= div;
+ writel_relaxed(val, pll->base);
+
+- return 0;
++ return clk_pllv3_wait_for_lock(pll, 10);
+ }
+
+ static const struct clk_ops clk_pllv3_sys_ops = {
+- .prepare = clk_pllv3_prepare,
+- .unprepare = clk_pllv3_unprepare,
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_sys_recalc_rate,
+@@ -215,6 +289,10 @@
+ u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
+ u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
+ u32 div = readl_relaxed(pll->base) & pll->div_mask;
++ u32 bypass = readl_relaxed(pll->base) & BYPASS_MASK;
++
++ if (pll->rate_req == BYPASS_RATE && bypass)
++ return BYPASS_RATE;
+
+ return (parent_rate * div) + ((parent_rate / mfd) * mfn);
+ }
+@@ -229,6 +307,9 @@
+ u32 mfn, mfd = 1000000;
+ s64 temp64;
+
++ if (rate == BYPASS_RATE)
++ return BYPASS_RATE;
++
+ if (rate > max_rate)
+ rate = max_rate;
+ else if (rate < min_rate)
+@@ -249,13 +330,36 @@
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ unsigned long min_rate = parent_rate * 27;
+ unsigned long max_rate = parent_rate * 54;
+- u32 val, div;
++ u32 val, newval, div;
+ u32 mfn, mfd = 1000000;
+ s64 temp64;
++ int ret;
+
+- if (rate < min_rate || rate > max_rate)
++ if (rate != BYPASS_RATE && (rate < min_rate || rate > max_rate))
+ return -EINVAL;
+
++ pll->rate_req = rate;
++ val = readl_relaxed(pll->base);
++
++ if (rate == BYPASS_RATE) {
++ /*
++ * Set the PLL in bypass mode if rate requested is
++ * BYPASS_RATE.
++ */
++ /* Bypass the PLL */
++ val |= BM_PLL_BYPASS;
++ /* Power down the PLL. */
++ if (pll->powerup_set)
++ val &= ~BM_PLL_POWER;
++ else
++ val |= BM_PLL_POWER;
++ writel_relaxed(val, pll->base);
++ return 0;
++ }
++ /* Else clear the bypass bit. */
++ val &= ~BM_PLL_BYPASS;
++ writel_relaxed(val, pll->base);
++
+ div = rate / parent_rate;
+ temp64 = (u64) (rate - div * parent_rate);
+ temp64 *= mfd;
+@@ -263,18 +367,30 @@
+ mfn = temp64;
+
+ val = readl_relaxed(pll->base);
+- val &= ~pll->div_mask;
+- val |= div;
+- writel_relaxed(val, pll->base);
++
++ /* set the PLL into bypass mode */
++ newval = val | BM_PLL_BYPASS;
++ writel_relaxed(newval, pll->base);
++
++ /* configure the new frequency */
++ newval &= ~pll->div_mask;
++ newval |= div;
++ writel_relaxed(newval, pll->base);
+ writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
+- writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
++ writel(mfd, pll->base + PLL_DENOM_OFFSET);
+
+- return 0;
++ ret = clk_pllv3_wait_for_lock(pll, 10);
++ if (ret == 0 && val & BM_PLL_POWER) {
++ /* only if it locked can we switch back to the PLL */
++ newval &= ~BM_PLL_BYPASS;
++ newval |= val & BM_PLL_BYPASS;
++ writel(newval, pll->base);
++ }
++
++ return ret;
+ }
+
+ static const struct clk_ops clk_pllv3_av_ops = {
+- .prepare = clk_pllv3_prepare,
+- .unprepare = clk_pllv3_unprepare,
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_av_recalc_rate,
+@@ -289,23 +405,19 @@
+ }
+
+ static const struct clk_ops clk_pllv3_enet_ops = {
+- .prepare = clk_pllv3_prepare,
+- .unprepare = clk_pllv3_unprepare,
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_enet_recalc_rate,
+ };
+
+ static const struct clk_ops clk_pllv3_mlb_ops = {
+- .prepare = clk_pllv3_prepare,
+- .unprepare = clk_pllv3_unprepare,
+ .enable = clk_pllv3_enable,
+ .disable = clk_pllv3_disable,
+ };
+
+ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base,
+- u32 div_mask)
++ u32 div_mask, bool always_on)
+ {
+ struct clk_pllv3 *pll;
+ const struct clk_ops *ops;
+@@ -338,6 +450,7 @@
+ }
+ pll->base = base;
+ pll->div_mask = div_mask;
++ pll->always_on = always_on;
+
+ init.name = name;
+ init.ops = ops;
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/clk-vf610.c linux-linaro-stable-mx6/arch/arm/mach-imx/clk-vf610.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/clk-vf610.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/clk-vf610.c 2014-05-15 20:33:35.373850766 +0200
+@@ -0,0 +1,321 @@
++/*
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ */
++
++#include <linux/of_address.h>
++#include <linux/clk.h>
++#include <dt-bindings/clock/vf610-clock.h>
++
++#include "clk.h"
++
++#define CCM_CCR (ccm_base + 0x00)
++#define CCM_CSR (ccm_base + 0x04)
++#define CCM_CCSR (ccm_base + 0x08)
++#define CCM_CACRR (ccm_base + 0x0c)
++#define CCM_CSCMR1 (ccm_base + 0x10)
++#define CCM_CSCDR1 (ccm_base + 0x14)
++#define CCM_CSCDR2 (ccm_base + 0x18)
++#define CCM_CSCDR3 (ccm_base + 0x1c)
++#define CCM_CSCMR2 (ccm_base + 0x20)
++#define CCM_CSCDR4 (ccm_base + 0x24)
++#define CCM_CLPCR (ccm_base + 0x2c)
++#define CCM_CISR (ccm_base + 0x30)
++#define CCM_CIMR (ccm_base + 0x34)
++#define CCM_CGPR (ccm_base + 0x3c)
++#define CCM_CCGR0 (ccm_base + 0x40)
++#define CCM_CCGR1 (ccm_base + 0x44)
++#define CCM_CCGR2 (ccm_base + 0x48)
++#define CCM_CCGR3 (ccm_base + 0x4c)
++#define CCM_CCGR4 (ccm_base + 0x50)
++#define CCM_CCGR5 (ccm_base + 0x54)
++#define CCM_CCGR6 (ccm_base + 0x58)
++#define CCM_CCGR7 (ccm_base + 0x5c)
++#define CCM_CCGR8 (ccm_base + 0x60)
++#define CCM_CCGR9 (ccm_base + 0x64)
++#define CCM_CCGR10 (ccm_base + 0x68)
++#define CCM_CCGR11 (ccm_base + 0x6c)
++#define CCM_CMEOR0 (ccm_base + 0x70)
++#define CCM_CMEOR1 (ccm_base + 0x74)
++#define CCM_CMEOR2 (ccm_base + 0x78)
++#define CCM_CMEOR3 (ccm_base + 0x7c)
++#define CCM_CMEOR4 (ccm_base + 0x80)
++#define CCM_CMEOR5 (ccm_base + 0x84)
++#define CCM_CPPDSR (ccm_base + 0x88)
++#define CCM_CCOWR (ccm_base + 0x8c)
++#define CCM_CCPGR0 (ccm_base + 0x90)
++#define CCM_CCPGR1 (ccm_base + 0x94)
++#define CCM_CCPGR2 (ccm_base + 0x98)
++#define CCM_CCPGR3 (ccm_base + 0x9c)
++
++#define CCM_CCGRx_CGn(n) ((n) * 2)
++
++#define PFD_PLL1_BASE (anatop_base + 0x2b0)
++#define PFD_PLL2_BASE (anatop_base + 0x100)
++#define PFD_PLL3_BASE (anatop_base + 0xf0)
++
++static void __iomem *anatop_base;
++static void __iomem *ccm_base;
++
++/* sources for multiplexer clocks, this is used multiple times */
++static const char const *fast_sels[] = { "firc", "fxosc", };
++static const char const *slow_sels[] = { "sirc_32k", "sxosc", };
++static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
++static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
++static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
++static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", };
++static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
++static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
++static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
++static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
++static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
++static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
++static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
++static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", };
++static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", };
++static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", };
++/* FTM counter clock source, not module clock */
++static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
++static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
++
++static struct clk_div_table pll4_main_div_table[] = {
++ { .val = 0, .div = 1 },
++ { .val = 1, .div = 2 },
++ { .val = 2, .div = 6 },
++ { .val = 3, .div = 8 },
++ { .val = 4, .div = 10 },
++ { .val = 5, .div = 12 },
++ { .val = 6, .div = 14 },
++ { .val = 7, .div = 16 },
++ { }
++};
++
++static struct clk *clk[VF610_CLK_END];
++static struct clk_onecell_data clk_data;
++
++static void __init vf610_clocks_init(struct device_node *ccm_node)
++{
++ struct device_node *np;
++
++ clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
++ clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
++ clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
++ clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
++
++ clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
++ clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
++ clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
++ clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
++
++ clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
++ anatop_base = of_iomap(np, 0);
++ BUG_ON(!anatop_base);
++
++ np = ccm_node;
++ ccm_base = of_iomap(np, 0);
++ BUG_ON(!ccm_base);
++
++ clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
++ clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
++
++ clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
++ clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
++ clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
++ clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
++ clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
++
++ clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
++ clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
++ clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
++ clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
++ clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
++
++ clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
++ clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
++ clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
++ clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
++ clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
++
++ clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
++ /* Enet pll: fixed 50Mhz */
++ clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
++ /* pll6: default 960Mhz */
++ clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
++ clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
++ clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
++ clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
++ clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
++ clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
++ clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
++ clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
++
++ clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
++ clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
++ clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
++
++ clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
++ clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
++
++ clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
++ clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
++ clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);
++ clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
++ clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
++ clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4));
++
++ clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4);
++ clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);
++ clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);
++ clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
++ clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
++ clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
++
++ clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
++ clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
++ clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
++ clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
++ clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
++ clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
++ clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
++ clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
++
++ clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
++
++ clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
++ clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
++ clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
++ clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
++
++ clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
++ clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
++
++ clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
++ clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
++ clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
++ clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
++
++ clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
++
++ clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4);
++ clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28);
++ clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4);
++ clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
++
++ clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4);
++ clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29);
++ clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4);
++ clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
++
++ /*
++ * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
++ * selectable clock sources, both use a common enable bit
++ * in CCM_CSCDR1, selecting "dummy" clock as parent of
++ * "ftm0_ext_fix" make it serve only for enable/disable.
++ */
++ clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4);
++ clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2);
++ clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25);
++ clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4);
++ clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2);
++ clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26);
++ clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4);
++ clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2);
++ clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27);
++ clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4);
++ clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2);
++ clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28);
++
++ /* ftm(n)_clk are FTM module operation clock */
++ clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
++ clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
++ clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
++ clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
++
++ clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
++ clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
++ clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
++ clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
++ clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
++ clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
++ clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
++ clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
++
++ clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
++ clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
++ clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
++ clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
++
++ clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4);
++ clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16);
++ clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4);
++ clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
++
++ clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4);
++ clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17);
++ clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4);
++ clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
++
++ clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4);
++ clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18);
++ clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4);
++ clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
++
++ clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4);
++ clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19);
++ clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4);
++ clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
++
++ clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4);
++ clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
++ clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);
++ clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
++ clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
++
++ clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2);
++ clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10);
++ clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15));
++
++ clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3);
++ clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22);
++ clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2);
++ clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
++ clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
++
++ clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
++ clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
++ clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
++ clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
++
++ clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
++
++ clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
++ clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
++
++ clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
++ clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
++ clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
++ clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2);
++
++ clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]);
++ clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2);
++ clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2);
++ clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2);
++
++ clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]);
++ clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]);
++ clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
++ clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
++
++ /* Add the clocks to provider list */
++ clk_data.clks = clk;
++ clk_data.clk_num = ARRAY_SIZE(clk);
++ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
++}
++CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/common.h linux-linaro-stable-mx6/arch/arm/mach-imx/common.h
+--- linux-3.10.30.orig/arch/arm/mach-imx/common.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/common.h 2014-05-15 20:33:35.373850766 +0200
+@@ -14,6 +14,7 @@
+ struct platform_device;
+ struct pt_regs;
+ struct clk;
++struct irq_data;
+ enum mxc_cpu_pwr_mode;
+
+ extern void mx1_map_io(void);
+@@ -68,17 +69,21 @@
+ extern int mx31_clocks_init_dt(void);
+ extern int mx51_clocks_init_dt(void);
+ extern int mx53_clocks_init_dt(void);
+-extern int mx6q_clocks_init(void);
+ extern struct platform_device *mxc_register_gpio(char *name, int id,
+ resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
+ extern void mxc_set_cpu_type(unsigned int type);
++extern void mxc_set_system_rev(unsigned int sysrev);
+ extern void mxc_restart(char, const char *);
+ extern void mxc_arch_reset_init(void __iomem *);
++extern void mxc_arch_reset_init_dt(void);
+ extern int mx53_revision(void);
+-extern int imx6q_revision(void);
+ extern int mx53_display_revision(void);
+ extern void imx_set_aips(void __iomem *);
+ extern int mxc_device_init(void);
++extern void imx_set_soc_revision(unsigned int rev);
++extern unsigned int imx_get_soc_revision(void);
++extern void imx_init_revision_from_anatop(void);
++extern struct device *imx_soc_device_init(void);
+
+ enum mxc_cpu_pwr_mode {
+ WAIT_CLOCKED, /* wfi only */
+@@ -125,30 +130,41 @@
+ static inline void imx_smp_prepare(void) {}
+ static inline void imx_scu_standby_enable(void) {}
+ #endif
++extern void imx6_pm_map_io(void);
++extern void imx6_suspend(void);
+ extern void imx_src_init(void);
++#ifdef CONFIG_HAVE_IMX_SRC
+ extern void imx_src_prepare_restart(void);
++#else
++static inline void imx_src_prepare_restart(void) {}
++#endif
+ extern void imx_gpc_init(void);
+-extern void imx_gpc_pre_suspend(void);
++extern void imx_gpc_pre_suspend(bool arm_power_off);
+ extern void imx_gpc_post_resume(void);
+ extern void imx_gpc_mask_all(void);
++extern void imx_gpc_irq_mask(struct irq_data *d);
++extern void imx_gpc_irq_unmask(struct irq_data *d);
+ extern void imx_gpc_restore_all(void);
+ extern void imx_anatop_init(void);
+ extern void imx_anatop_pre_suspend(void);
+ extern void imx_anatop_post_resume(void);
+-extern void imx_anatop_usb_chrg_detect_disable(void);
+-extern u32 imx_anatop_get_digprog(void);
+-extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
+-extern void imx6q_set_chicken_bit(void);
++extern void imx_anatop_pu_enable(bool enable);
++extern int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
++extern void imx6_set_cache_lpm_in_wait(bool enable);
++extern void imx6sl_set_wait_clk(bool enter);
++extern void imx6_enet_mac_init(const char *compatible);
+
+ extern void imx_cpu_die(unsigned int cpu);
+ extern int imx_cpu_kill(unsigned int cpu);
+
+ #ifdef CONFIG_PM
+-extern void imx6q_pm_init(void);
++extern void imx6_pm_init(void);
++extern void imx6_pm_set_ccm_base(void __iomem *base);
+ extern void imx51_pm_init(void);
+ extern void imx53_pm_init(void);
+ #else
+-static inline void imx6q_pm_init(void) {}
++static inline void imx6_pm_init(void) {}
++static inline void imx6_pm_set_ccm_base(void __iomem *base) {}
+ static inline void imx51_pm_init(void) {}
+ static inline void imx53_pm_init(void) {}
+ #endif
+@@ -159,6 +175,12 @@
+ static inline int mx51_neon_fixup(void) { return 0; }
+ #endif
+
++#ifdef CONFIG_CACHE_L2X0
++extern void imx_init_l2cache(void);
++#else
++static inline void imx_init_l2cache(void) {}
++#endif
++
+ extern struct smp_operations imx_smp_ops;
+
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/cpu.c linux-linaro-stable-mx6/arch/arm/mach-imx/cpu.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/cpu.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/cpu.c 2014-05-15 20:33:35.373850766 +0200
+@@ -1,6 +1,9 @@
+
+ #include <linux/module.h>
+ #include <linux/io.h>
++#include <linux/of.h>
++#include <linux/slab.h>
++#include <linux/sys_soc.h>
+
+ #include "hardware.h"
+ #include "common.h"
+@@ -8,11 +11,30 @@
+ unsigned int __mxc_cpu_type;
+ EXPORT_SYMBOL(__mxc_cpu_type);
+
++extern unsigned int system_rev;
++
++static unsigned int imx_soc_revision;
++
+ void mxc_set_cpu_type(unsigned int type)
+ {
+ __mxc_cpu_type = type;
+ }
+
++void mxc_set_system_rev(unsigned int sysrev)
++{
++ system_rev = sysrev;
++}
++
++void imx_set_soc_revision(unsigned int rev)
++{
++ imx_soc_revision = rev;
++}
++
++unsigned int imx_get_soc_revision(void)
++{
++ return imx_soc_revision;
++}
++
+ void imx_print_silicon_rev(const char *cpu, int srev)
+ {
+ if (srev == IMX_CHIP_REVISION_UNKNOWN)
+@@ -44,3 +66,80 @@
+ reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
+ __raw_writel(reg, base + 0x50);
+ }
++
++struct device * __init imx_soc_device_init(void)
++{
++ struct soc_device_attribute *soc_dev_attr;
++ struct soc_device *soc_dev;
++ struct device_node *root;
++ const char *soc_id;
++ int ret;
++
++ soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
++ if (!soc_dev_attr)
++ return NULL;
++
++ soc_dev_attr->family = "Freescale i.MX";
++
++ root = of_find_node_by_path("/");
++ ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
++ if (ret)
++ goto free_soc;
++
++ switch (__mxc_cpu_type) {
++ case MXC_CPU_MX1:
++ soc_id = "i.MX1";
++ break;
++ case MXC_CPU_MX21:
++ soc_id = "i.MX21";
++ break;
++ case MXC_CPU_MX25:
++ soc_id = "i.MX25";
++ break;
++ case MXC_CPU_MX27:
++ soc_id = "i.MX27";
++ break;
++ case MXC_CPU_MX31:
++ soc_id = "i.MX31";
++ break;
++ case MXC_CPU_MX35:
++ soc_id = "i.MX35";
++ break;
++ case MXC_CPU_MX51:
++ soc_id = "i.MX51";
++ break;
++ case MXC_CPU_MX53:
++ soc_id = "i.MX53";
++ break;
++ case MXC_CPU_IMX6SL:
++ soc_id = "i.MX6SL";
++ break;
++ case MXC_CPU_IMX6DL:
++ soc_id = "i.MX6DL";
++ break;
++ case MXC_CPU_IMX6Q:
++ soc_id = "i.MX6Q";
++ break;
++ default:
++ soc_id = "Unknown";
++ }
++ soc_dev_attr->soc_id = soc_id;
++
++ soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
++ (imx_soc_revision >> 4) & 0xf,
++ imx_soc_revision & 0xf);
++ if (!soc_dev_attr->revision)
++ goto free_soc;
++
++ soc_dev = soc_device_register(soc_dev_attr);
++ if (IS_ERR(soc_dev))
++ goto free_rev;
++
++ return soc_device_to_device(soc_dev);
++
++free_rev:
++ kfree(soc_dev_attr->revision);
++free_soc:
++ kfree(soc_dev_attr);
++ return NULL;
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/cpuidle.h linux-linaro-stable-mx6/arch/arm/mach-imx/cpuidle.h
+--- linux-3.10.30.orig/arch/arm/mach-imx/cpuidle.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/cpuidle.h 2014-05-15 20:33:35.377850795 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -13,6 +13,7 @@
+ #ifdef CONFIG_CPU_IDLE
+ extern int imx5_cpuidle_init(void);
+ extern int imx6q_cpuidle_init(void);
++extern int imx6sl_cpuidle_init(void);
+ #else
+ static inline int imx5_cpuidle_init(void)
+ {
+@@ -22,4 +23,8 @@
+ {
+ return 0;
+ }
++static inline int imx6sl_cpuidle_init(void)
++{
++ return 0;
++}
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/cpuidle-imx6q.c linux-linaro-stable-mx6/arch/arm/mach-imx/cpuidle-imx6q.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/cpuidle-imx6q.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/cpuidle-imx6q.c 2014-05-15 20:33:35.377850795 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -27,9 +27,9 @@
+ */
+ if (!spin_trylock(&master_lock))
+ goto idle;
+- imx6q_set_lpm(WAIT_UNCLOCKED);
++ imx6_set_lpm(WAIT_UNCLOCKED);
+ cpu_do_idle();
+- imx6q_set_lpm(WAIT_CLOCKED);
++ imx6_set_lpm(WAIT_CLOCKED);
+ spin_unlock(&master_lock);
+ goto done;
+ }
+@@ -68,8 +68,8 @@
+ /* Need to enable SCU standby for entering WAIT modes */
+ imx_scu_standby_enable();
+
+- /* Set chicken bit to get a reliable WAIT mode support */
+- imx6q_set_chicken_bit();
++ /* Set cache lpm bit for reliable WAIT mode support */
++ imx6_set_cache_lpm_in_wait(true);
+
+ return cpuidle_register(&imx6q_cpuidle_driver, NULL);
+ }
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/cpuidle-imx6sl.c linux-linaro-stable-mx6/arch/arm/mach-imx/cpuidle-imx6sl.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/cpuidle-imx6sl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/cpuidle-imx6sl.c 2014-05-15 20:33:35.377850795 +0200
+@@ -0,0 +1,145 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/cpuidle.h>
++#include <linux/genalloc.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <asm/cpuidle.h>
++#include <asm/fncpy.h>
++#include <asm/mach/map.h>
++#include <asm/proc-fns.h>
++#include <asm/tlb.h>
++
++#include "common.h"
++#include "cpuidle.h"
++
++extern u32 audio_bus_freq_mode;
++extern u32 ultra_low_bus_freq_mode;
++extern unsigned long reg_addrs[];
++extern void imx6sl_low_power_wfi(void);
++
++static void __iomem *iomux_base;
++static void *wfi_iram_base;
++
++void (*imx6sl_wfi_in_iram_fn)(void *wfi_iram_base,
++ void *iomux_addr, void *regs_addr, u32 audio_mode) = NULL;
++
++#define WFI_IN_IRAM_SIZE 0x1000
++
++static int imx6sl_enter_wait(struct cpuidle_device *dev,
++ struct cpuidle_driver *drv, int index)
++{
++ imx6_set_lpm(WAIT_UNCLOCKED);
++ if (ultra_low_bus_freq_mode || audio_bus_freq_mode) {
++ /*
++ * Flush the TLB, to ensure no TLB maintenance occurs
++ * when DDR is in self-refresh.
++ */
++ local_flush_tlb_all();
++ /*
++ * Run WFI code from IRAM.
++ * Drop the DDR freq to 1MHz and AHB to 3MHz
++ * Also float DDR IO pads.
++ */
++ imx6sl_wfi_in_iram_fn(wfi_iram_base, iomux_base, reg_addrs, audio_bus_freq_mode);
++ } else {
++ imx6sl_set_wait_clk(true);
++ cpu_do_idle();
++ imx6sl_set_wait_clk(false);
++ }
++ imx6_set_lpm(WAIT_CLOCKED);
++
++ return index;
++}
++
++static struct cpuidle_driver imx6sl_cpuidle_driver = {
++ .name = "imx6sl_cpuidle",
++ .owner = THIS_MODULE,
++ .states = {
++ /* WFI */
++ ARM_CPUIDLE_WFI_STATE,
++ /* WAIT */
++ {
++ .exit_latency = 50,
++ .target_residency = 75,
++ .flags = CPUIDLE_FLAG_TIME_VALID |
++ CPUIDLE_FLAG_TIMER_STOP,
++ .enter = imx6sl_enter_wait,
++ .name = "WAIT",
++ .desc = "Clock off",
++ },
++ },
++ .state_count = 2,
++ .safe_state_index = 0,
++};
++
++int __init imx6sl_cpuidle_init(void)
++{
++ struct platform_device *ocram_dev;
++ unsigned int iram_paddr;
++ struct device_node *node;
++ struct gen_pool *iram_pool;
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-iomuxc");
++ if (!node) {
++ pr_err("failed to find imx6sl-iomuxc device tree data!\n");
++ return -EINVAL;
++ }
++ iomux_base = of_iomap(node, 0);
++ WARN(!iomux_base, "unable to map iomux registers\n");
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "mmio-sram");
++ if (!node) {
++ pr_err("%s: failed to find ocram node\n",
++ __func__);
++ return -EINVAL;
++ }
++
++ ocram_dev = of_find_device_by_node(node);
++ if (!ocram_dev) {
++ pr_err("failed to find ocram device!\n");
++ return -EINVAL;
++ }
++
++ iram_pool = dev_get_gen_pool(&ocram_dev->dev);
++ if (!iram_pool) {
++ pr_err("iram pool unavailable!\n");
++ return -EINVAL;
++ }
++ /*
++ * Allocate IRAM memory when ARM executes WFI in
++ * ultra_low_power_mode.
++ */
++ wfi_iram_base = (void *)gen_pool_alloc(iram_pool,
++ WFI_IN_IRAM_SIZE);
++ if (!wfi_iram_base) {
++ pr_err("Cannot alloc iram for wfi code!\n");
++ return -ENOMEM;
++ }
++
++ iram_paddr = gen_pool_virt_to_phys(iram_pool,
++ (unsigned long)wfi_iram_base);
++ /*
++ * Need to remap the area here since we want
++ * the memory region to be executable.
++ */
++ wfi_iram_base = __arm_ioremap(iram_paddr,
++ WFI_IN_IRAM_SIZE,
++ MT_MEMORY_NONCACHED);
++ if (!wfi_iram_base)
++ pr_err("wfi_ram_base NOT remapped\n");
++
++ imx6sl_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base,
++ &imx6sl_low_power_wfi, WFI_IN_IRAM_SIZE);
++
++ return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/ddr3_freq_imx6.S linux-linaro-stable-mx6/arch/arm/mach-imx/ddr3_freq_imx6.S
+--- linux-3.10.30.orig/arch/arm/mach-imx/ddr3_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/ddr3_freq_imx6.S 2014-05-15 20:33:35.377850795 +0200
+@@ -0,0 +1,893 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/linkage.h>
++
++#define MMDC0_MDPDC 0x4
++#define MMDC0_MDCF0 0x0c
++#define MMDC0_MDCF1 0x10
++#define MMDC0_MDMISC 0x18
++#define MMDC0_MDSCR 0x1c
++#define MMDC0_MAPSR 0x404
++#define MMDC0_MADPCR0 0x410
++#define MMDC0_MPZQHWCTRL 0x800
++#define MMDC1_MPZQHWCTRL 0x4800
++#define MMDC0_MPODTCTRL 0x818
++#define MMDC1_MPODTCTRL 0x4818
++#define MMDC0_MPDGCTRL0 0x83c
++#define MMDC1_MPDGCTRL0 0x483c
++#define MMDC0_MPMUR0 0x8b8
++#define MMDC1_MPMUR0 0x48b8
++
++#define CCM_CBCDR 0x14
++#define CCM_CBCMR 0x18
++#define CCM_CSCMR1 0x1c
++#define CCM_CDHIPR 0x48
++
++#define L2_CACHE_SYNC 0x730
++
++ .align 3
++
++ .macro switch_to_528MHz
++
++ /* check if periph_clk_sel is already set */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq set_ahb_podf_before_switch
++
++ /* change periph_clk to be sourced from pll3_clk. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 20)
++ str r0, [r6, #CCM_CBCDR]
++
++ /*
++ * set the AHB dividers before the switch,
++ * don't change AXI clock divider,
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #0xd00
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update528:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update528
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch3:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch3
++
++ b switch_pre_periph_clk_528
++
++set_ahb_podf_before_switch:
++ /*
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #0xd00
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update528_1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update528_1
++
++switch_pre_periph_clk_528:
++
++ /* now switch pre_periph_clk to PLL2_528MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0xc << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch4:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch4
++
++ .endm
++
++ .macro switch_to_400MHz
++
++ /* check if periph_clk_sel is already set. */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq set_ahb_podf_before_switch1
++
++ /* change periph_clk to be sourced from pll3_clk. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch5:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch5
++
++ b switch_pre_periph_clk_400
++
++set_ahb_podf_before_switch1:
++ /*
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x9 << 8)
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update400_1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update400_1
++
++switch_pre_periph_clk_400:
++
++ /* now switch pre_periph_clk to PFD_400MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0xc << 16)
++ orr r0, r0, #(0x4 << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch6:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch6
++
++ /*
++ * change AHB divider so that we are at 400/3=133MHz.
++ * don't change AXI clock divider.
++ * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x9 << 8)
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update400_2:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update400_2
++
++ .endm
++
++ .macro switch_to_50MHz
++
++ /* check if periph_clk_sel is already set. */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq switch_pre_periph_clk_50
++
++ /*
++ * set the periph_clk to be sourced from PLL2_PFD_200M
++ * change periph_clk to be sourced from pll3_clk.
++ * ensure PLL3 is the source and set the divider to 1.
++ */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0x3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch_50:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch_50
++
++switch_pre_periph_clk_50:
++
++ /* now switch pre_periph_clk to PFD_200MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ orr r0, r0, #(0xc << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /*
++ * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x18 << 16)
++ orr r0, r0, #(0x3 << 16)
++
++ /*
++ * if changing AHB divider remember to change
++ * the IPGPER divider too below.
++ */
++ orr r0, r0, #0x1d00
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update_50:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update_50
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch2:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch2
++
++ .endm
++
++ .macro switch_to_24MHz
++ /*
++ * change the freq now try setting DDR to 24MHz.
++ * source it from the periph_clk2 ensure the
++ * periph_clk2 is sourced from 24MHz and the
++ * divider is 1.
++ */
++
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0x3 << 12)
++ orr r0, r0, #(1 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to 24MHz. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch1
++
++ /* change all the dividers to 1. */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(1 << 8)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* Wait for the divider to change. */
++wait_div_update:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update
++
++ .endm
++
++/*
++ * mx6_ddr3_freq_change
++ *
++ * idle the processor (eg, wait for interrupt).
++ * make sure DDR is in self-refresh.
++ * IRQs are already disabled.
++ */
++ENTRY(mx6_ddr3_freq_change)
++
++ stmfd sp!, {r4-r12}
++
++ /*
++ * r5 -> mmdc_base
++ * r6 -> ccm_base
++ * r7 -> iomux_base
++ * r12 -> l2_base
++ */
++ mov r4, r0
++ mov r8, r1
++ mov r9, r2
++ mov r11, r3
++
++ /*
++ * Get the addresses of the registers.
++ * They are last few entries in the
++ * ddr_settings parameter.
++ * The first entry contains the count,
++ * and each entry is 2 words.
++ */
++ ldr r0, [r1]
++ add r0, r0, #1
++ lsl r0, r0, #3
++ add r1, r0, r1
++ /* mmdc_base. */
++ ldr r5, [r1]
++ add r1, #8
++ /* ccm_base */
++ ldr r6, [r1]
++ add r1, #8
++ /*iomux_base */
++ ldr r7, [r1]
++ add r1, #8
++ /*l2_base */
++ ldr r12, [r1]
++
++ddr_freq_change:
++ /*
++ * make sure no TLB miss will occur when
++ * the DDR is in self refresh. invalidate
++ * TLB single entry to ensure that the
++ * address is not already in the TLB.
++ */
++
++ adr r10, ddr_freq_change
++
++ ldr r2, [r6]
++ ldr r2, [r5]
++ ldr r2, [r7]
++ ldr r2, [r8]
++ ldr r2, [r10]
++ ldr r2, [r11]
++ ldr r2, [r12]
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * Make sure the L2 buffers are drained.
++ * Sync operation on L2 drains the buffers.
++ */
++ mov r1, #0x0
++ str r1, [r12, #L2_CACHE_SYNC]
++#endif
++
++ /* disable automatic power saving. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #0x01
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* disable MMDC power down timer. */
++ ldr r0, [r5, #MMDC0_MDPDC]
++ bic r0, r0, #(0xff << 8)
++ str r0, [r5, #MMDC0_MDPDC]
++
++ /* delay for a while */
++ ldr r1, =4
++delay1:
++ ldr r2, =0
++cont1:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont1
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay1
++
++ /* set CON_REG */
++ ldr r0, =0x8000
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_set_1:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ bne poll_conreq_set_1
++
++ ldr r0, =0x00008010
++ str r0, [r5, #MMDC0_MDSCR]
++ ldr r0, =0x00008018
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /*
++ * if requested frequency is greater than
++ * 300MHz go to DLL on mode.
++ */
++ ldr r1, =300000000
++ cmp r4, r1
++ bge dll_on_mode
++
++dll_off_mode:
++
++ /* if DLL is currently on, turn it off. */
++ cmp r9, #1
++ beq continue_dll_off_1
++
++ ldr r0, =0x00018031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00018039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r1, =10
++delay1a:
++ ldr r2, =0
++cont1a:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont1a
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay1a
++
++continue_dll_off_1:
++ /* set DVFS - enter self refresh mode */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* de-assert con_req */
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++
++poll_dvfs_set_1:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ bne poll_dvfs_set_1
++
++ ldr r1, =24000000
++ cmp r4, r1
++ beq switch_freq_24
++
++ switch_to_50MHz
++ b continue_dll_off_2
++
++switch_freq_24:
++ switch_to_24MHz
++
++continue_dll_off_2:
++
++ /* set SBS - block ddr accesses */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ orr r0, r0, #(1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ /* clear DVFS - exit from self refresh mode */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++poll_dvfs_clear_1:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq poll_dvfs_clear_1
++
++ /* if DLL was previously on, continue DLL off routine. */
++ cmp r9, #1
++ beq continue_dll_off_3
++
++ ldr r0, =0x00018031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00018039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x08208030
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x08208038
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00088032
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x0008803A
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for a while. */
++ ldr r1, =4
++delay_1:
++ ldr r2, =0
++cont_1:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont_1
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay_1
++
++ ldr r0, [r5, #MMDC0_MDCF0]
++ bic r0, r0, #0xf
++ orr r0, r0, #0x3
++ str r0, [r5, #MMDC0_MDCF0]
++
++ ldr r0, [r5, #MMDC0_MDCF1]
++ bic r0, r0, #0x7
++ orr r0, r0, #0x4
++ str r0, [r5, #MMDC0_MDCF1]
++
++ ldr r0, =0x00091680
++ str r0, [r5, #MMDC0_MDMISC]
++
++ /* enable dqs pull down in the IOMUX. */
++ ldr r1, [r11]
++ add r11, r11, #8
++ ldr r2, =0x3028
++update_iomux:
++ ldr r0, [r11, #0x0]
++ ldr r3, [r7, r0]
++ bic r3, r3, r2
++ orr r3, r3, #(0x3 << 12)
++ orr r3, r3, #0x28
++ str r3, [r7, r0]
++ add r11, r11, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_iomux
++
++ /* ODT disabled. */
++ ldr r0, =0x0
++ ldr r2, =MMDC0_MPODTCTRL
++ str r0, [r5, r2]
++ ldr r2, =MMDC1_MPODTCTRL
++ str r0, [r5, r2]
++
++ /* DQS gating disabled. */
++ ldr r2, =MMDC0_MPDGCTRL0
++ ldr r0, [r5, r2]
++ orr r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ ldr r2, =MMDC1_MPDGCTRL0
++ ldr r0, [r5, r2]
++ orr r0, r0, #(0x1 << 29)
++ str r0, [r5, r2]
++
++ /* MMDC0_MAPSR adopt power down enable. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #0x01
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* frc_msr + mu bypass */
++ ldr r0, =0x00000060
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++ ldr r0, =0x00000460
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++ ldr r0, =0x00000c60
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++
++continue_dll_off_3:
++ /* clear SBS - unblock accesses to DDR. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ bic r0, r0, #(0x1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_clear_1:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ beq poll_conreq_clear_1
++
++ b done
++
++dll_on_mode:
++ /* assert DVFS - enter self refresh mode. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* de-assert CON_REQ. */
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* poll DVFS ack. */
++poll_dvfs_set_2:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ bne poll_dvfs_set_2
++
++ ldr r1, =528000000
++ cmp r4, r1
++ beq switch_freq_528
++
++ switch_to_400MHz
++
++ b continue_dll_on
++
++switch_freq_528:
++ switch_to_528MHz
++
++continue_dll_on:
++
++ /* set SBS step-by-step mode. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ orr r0, r0, #( 1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ /* clear DVFS - exit self refresh mode. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++poll_dvfs_clear_2:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq poll_dvfs_clear_2
++
++ /* if DLL is currently off, turn it back on. */
++ cmp r9, #0
++ beq update_calibration_only
++
++ ldr r0, =0xa5390003
++ str r0, [r5, #MMDC0_MPZQHWCTRL]
++ ldr r2, =MMDC1_MPZQHWCTRL
++ str r0, [r5, r2]
++
++ /* enable DQS gating. */
++ ldr r2, =MMDC0_MPDGCTRL0
++ ldr r0, [r5, r2]
++ bic r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ ldr r2, =MMDC1_MPDGCTRL0
++ ldr r0, [r5, r2]
++ bic r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ /* force measure. */
++ ldr r0, =0x00000800
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++
++ /* delay for while. */
++ ldr r1, =4
++delay5:
++ ldr r2, =0
++cont5:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont5
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay5
++
++ /* disable dqs pull down in the IOMUX. */
++ ldr r1, [r11]
++ add r11, r11, #8
++update_iomux1:
++ ldr r0, [r11, #0x0]
++ ldr r3, [r11, #0x4]
++ str r3, [r7, r0]
++ add r11, r11, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_iomux1
++
++ /* config MMDC timings to 528MHz. */
++ ldr r9, [r8]
++ add r8, r8, #8
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ /* update MISC register: WALAT, RALAT */
++ ldr r0, =0x00081740
++ str r0, [r5, #MMDC0_MDMISC]
++
++ /* configure ddr devices to dll on, odt. */
++ ldr r0, =0x00028031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00028039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for while. */
++ ldr r1, =4
++delay7:
++ ldr r2, =0
++cont7:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont7
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay7
++
++ /* reset dll. */
++ ldr r0, =0x09208030
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x09208038
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for while. */
++ ldr r1, =100
++delay8:
++ ldr r2, =0
++cont8:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, =0x00428031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00428039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ /* issue a zq command. */
++ ldr r0, =0x04008040
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x04008048
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* MMDC ODT enable. */
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r2, =0x4818
++ str r0, [r5, r2]
++
++ /* delay for while. */
++ ldr r1, =40
++delay15:
++ ldr r2, =0
++cont15:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont15
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay15
++
++ /* MMDC0_MAPSR adopt power down enable. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #0x01
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* enable MMDC power down timer. */
++ ldr r0, [r5, #MMDC0_MDPDC]
++ orr r0, r0, #(0x55 << 8)
++ str r0, [r5, #MMDC0_MDPDC]
++
++ b update_calibration
++
++update_calibration_only:
++ ldr r1, [r8]
++ sub r1, r1, #7
++ add r8, r8, #64
++ b update_calib
++
++update_calibration:
++ /* write the new calibration values. */
++ mov r1, r9
++ sub r1, r1, #7
++
++update_calib:
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_calib
++
++ /* perform a force measurement. */
++ ldr r0, =0x800
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++
++ /* clear SBS - unblock DDR accesses. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ bic r0, r0, #(1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_clear_2:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ beq poll_conreq_clear_2
++
++done:
++ /* restore registers */
++
++ ldmfd sp!, {r4-r12}
++ mov pc, lr
++
++ .type mx6_do_ddr3_freq_change, #object
++ENTRY(mx6_do_ddr_freq_change)
++ .word mx6_ddr3_freq_change
++ .size mx6_ddr3_freq_change, . - mx6_ddr3_freq_change
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/gpc.c linux-linaro-stable-mx6/arch/arm/mach-imx/gpc.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/gpc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/gpc.c 2014-05-15 20:33:35.381850824 +0200
+@@ -10,30 +10,127 @@
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
++#include <linux/clk.h>
++#include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
++#include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <linux/platform_device.h>
+ #include <linux/irqchip/arm-gic.h>
++#include <linux/regulator/consumer.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/machine.h>
+ #include "common.h"
++#include "hardware.h"
+
+ #define GPC_IMR1 0x008
+ #define GPC_PGC_CPU_PDN 0x2a0
++#define GPC_PGC_GPU_PDN 0x260
++#define GPC_PGC_GPU_PUPSCR 0x264
++#define GPC_PGC_GPU_PDNSCR 0x268
++#define GPC_PGC_DISP_PGCR_OFFSET 0x240
++#define GPC_PGC_DISP_PUPSCR_OFFSET 0x244
++#define GPC_PGC_DISP_PDNSCR_OFFSET 0x248
++#define GPC_PGC_DISP_SR_OFFSET 0x24c
++#define GPC_PGC_GPU_SW_SHIFT 0
++#define GPC_PGC_GPU_SW_MASK 0x3f
++#define GPC_PGC_GPU_SW2ISO_SHIFT 8
++#define GPC_PGC_GPU_SW2ISO_MASK 0x3f
++#define GPC_PGC_CPU_PUPSCR 0x2a4
++#define GPC_PGC_CPU_PDNSCR 0x2a8
++#define GPC_PGC_CPU_SW_SHIFT 0
++#define GPC_PGC_CPU_SW_MASK 0x3f
++#define GPC_PGC_CPU_SW2ISO_SHIFT 8
++#define GPC_PGC_CPU_SW2ISO_MASK 0x3f
++#define GPC_CNTR 0x0
++#define GPC_CNTR_PU_UP_REQ_SHIFT 0x1
++#define GPC_CNTR_PU_DOWN_REQ_SHIFT 0x0
+
+ #define IMR_NUM 4
+
+ static void __iomem *gpc_base;
+ static u32 gpc_wake_irqs[IMR_NUM];
+ static u32 gpc_saved_imrs[IMR_NUM];
++static struct clk *gpu3d_clk, *gpu3d_shader_clk, *gpu2d_clk, *gpu2d_axi_clk;
++static struct clk *lcd_axi_clk, *lcd_pix_clk, *epdc_axi_clk, *epdc_pix_clk;
++static struct clk *pxp_axi_clk;
++static struct clk *openvg_axi_clk, *vpu_clk, *ipg_clk;
++static struct device *gpc_dev;
++struct regulator *pu_reg;
++struct notifier_block nb;
++static struct regulator_dev *pu_dummy_regulator_rdev;
++static struct regulator_init_data pu_dummy_initdata = {
++ .constraints = {
++ .max_uV = 1450000, /* allign with real max of anatop */
++ .valid_ops_mask = REGULATOR_CHANGE_STATUS |
++ REGULATOR_CHANGE_VOLTAGE,
++ },
++};
++static int pu_dummy_enable;
+
+-void imx_gpc_pre_suspend(void)
++static void imx_disp_clk(bool enable)
++{
++ if (enable) {
++ clk_prepare_enable(lcd_axi_clk);
++ clk_prepare_enable(lcd_pix_clk);
++ clk_prepare_enable(epdc_axi_clk);
++ clk_prepare_enable(epdc_pix_clk);
++ clk_prepare_enable(pxp_axi_clk);
++ } else {
++ clk_disable_unprepare(lcd_axi_clk);
++ clk_disable_unprepare(lcd_pix_clk);
++ clk_disable_unprepare(epdc_axi_clk);
++ clk_disable_unprepare(epdc_pix_clk);
++ clk_disable_unprepare(pxp_axi_clk);
++ }
++}
++
++static void imx_gpc_dispmix_on(void)
++{
++ if (cpu_is_imx6sl()) {
++ imx_disp_clk(true);
++
++ writel_relaxed(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
++ writel_relaxed(0x20, gpc_base + GPC_CNTR);
++ while (readl_relaxed(gpc_base + GPC_CNTR) & 0x20)
++ ;
++ writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET);
++
++ imx_disp_clk(false);
++ }
++}
++
++static void imx_gpc_dispmix_off(void)
++{
++ if (cpu_is_imx6sl()) {
++ imx_disp_clk(true);
++
++ writel_relaxed(0xFFFFFFFF,
++ gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
++ writel_relaxed(0xFFFFFFFF,
++ gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
++ writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
++ writel_relaxed(0x10, gpc_base + GPC_CNTR);
++ while (readl_relaxed(gpc_base + GPC_CNTR) & 0x10)
++ ;
++
++ imx_disp_clk(false);
++ }
++}
++
++void imx_gpc_pre_suspend(bool arm_power_off)
+ {
+ void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
+ int i;
+
+- /* Tell GPC to power off ARM core when suspend */
+- writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
++ imx_gpc_dispmix_off();
++
++ if (arm_power_off)
++ /* Tell GPC to power off ARM core when suspend */
++ writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+
+ for (i = 0; i < IMR_NUM; i++) {
+ gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
+@@ -51,6 +148,8 @@
+
+ for (i = 0; i < IMR_NUM; i++)
+ writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
++
++ imx_gpc_dispmix_on();
+ }
+
+ static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
+@@ -90,7 +189,7 @@
+ writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
+ }
+
+-static void imx_gpc_irq_unmask(struct irq_data *d)
++void imx_gpc_irq_unmask(struct irq_data *d)
+ {
+ void __iomem *reg;
+ u32 val;
+@@ -105,7 +204,7 @@
+ writel_relaxed(val, reg);
+ }
+
+-static void imx_gpc_irq_mask(struct irq_data *d)
++void imx_gpc_irq_mask(struct irq_data *d)
+ {
+ void __iomem *reg;
+ u32 val;
+@@ -120,10 +219,119 @@
+ writel_relaxed(val, reg);
+ }
+
++static void imx_pu_clk(bool enable)
++{
++ if (enable) {
++ if (cpu_is_imx6sl()) {
++ clk_prepare_enable(gpu2d_clk);
++ clk_prepare_enable(openvg_axi_clk);
++ } else {
++ clk_prepare_enable(gpu3d_clk);
++ clk_prepare_enable(gpu3d_shader_clk);
++ clk_prepare_enable(vpu_clk);
++ clk_prepare_enable(gpu2d_clk);
++ clk_prepare_enable(gpu2d_axi_clk);
++ clk_prepare_enable(openvg_axi_clk);
++ }
++ } else {
++ if (cpu_is_imx6sl()) {
++ clk_disable_unprepare(gpu2d_clk);
++ clk_disable_unprepare(openvg_axi_clk);
++ } else {
++ clk_disable_unprepare(gpu3d_clk);
++ clk_disable_unprepare(gpu3d_shader_clk);
++ clk_disable_unprepare(vpu_clk);
++ clk_disable_unprepare(gpu2d_clk);
++ clk_disable_unprepare(gpu2d_axi_clk);
++ clk_disable_unprepare(openvg_axi_clk);
++ }
++ }
++}
++
++static void imx_gpc_pu_enable(bool enable)
++{
++ u32 rate, delay_us;
++ u32 gpu_pupscr_sw2iso, gpu_pdnscr_iso2sw;
++ u32 gpu_pupscr_sw, gpu_pdnscr_iso;
++
++ /* get ipg clk rate for PGC delay */
++ rate = clk_get_rate(ipg_clk);
++
++ if (enable) {
++ imx_anatop_pu_enable(true);
++ /*
++ * need to add necessary delay between powering up PU LDO and
++ * disabling PU isolation in PGC, the counter of PU isolation
++ * is based on ipg clk.
++ */
++ gpu_pupscr_sw2iso = (readl_relaxed(gpc_base +
++ GPC_PGC_GPU_PUPSCR) >> GPC_PGC_GPU_SW2ISO_SHIFT)
++ & GPC_PGC_GPU_SW2ISO_MASK;
++ gpu_pupscr_sw = (readl_relaxed(gpc_base +
++ GPC_PGC_GPU_PUPSCR) >> GPC_PGC_GPU_SW_SHIFT)
++ & GPC_PGC_GPU_SW_MASK;
++ delay_us = (gpu_pupscr_sw2iso + gpu_pupscr_sw) * 1000000
++ / rate + 1;
++ udelay(delay_us);
++
++ imx_pu_clk(true);
++ writel_relaxed(1, gpc_base + GPC_PGC_GPU_PDN);
++ writel_relaxed(1 << GPC_CNTR_PU_UP_REQ_SHIFT,
++ gpc_base + GPC_CNTR);
++ while (readl_relaxed(gpc_base + GPC_CNTR) &
++ (1 << GPC_CNTR_PU_UP_REQ_SHIFT))
++ ;
++ imx_pu_clk(false);
++ } else {
++ writel_relaxed(1, gpc_base + GPC_PGC_GPU_PDN);
++ writel_relaxed(1 << GPC_CNTR_PU_DOWN_REQ_SHIFT,
++ gpc_base + GPC_CNTR);
++ while (readl_relaxed(gpc_base + GPC_CNTR) &
++ (1 << GPC_CNTR_PU_DOWN_REQ_SHIFT))
++ ;
++ /*
++ * need to add necessary delay between enabling PU isolation
++ * in PGC and powering down PU LDO , the counter of PU isolation
++ * is based on ipg clk.
++ */
++ gpu_pdnscr_iso2sw = (readl_relaxed(gpc_base +
++ GPC_PGC_GPU_PDNSCR) >> GPC_PGC_GPU_SW2ISO_SHIFT)
++ & GPC_PGC_GPU_SW2ISO_MASK;
++ gpu_pdnscr_iso = (readl_relaxed(gpc_base +
++ GPC_PGC_GPU_PDNSCR) >> GPC_PGC_GPU_SW_SHIFT)
++ & GPC_PGC_GPU_SW_MASK;
++ delay_us = (gpu_pdnscr_iso2sw + gpu_pdnscr_iso) * 1000000
++ / rate + 1;
++ udelay(delay_us);
++ imx_anatop_pu_enable(false);
++ }
++}
++
++static int imx_gpc_regulator_notify(struct notifier_block *nb,
++ unsigned long event,
++ void *ignored)
++{
++ switch (event) {
++ case REGULATOR_EVENT_PRE_DISABLE:
++ imx_gpc_pu_enable(false);
++ break;
++ case REGULATOR_EVENT_ENABLE:
++ imx_gpc_pu_enable(true);
++ break;
++ default:
++ break;
++ }
++
++ return NOTIFY_OK;
++}
++
+ void __init imx_gpc_init(void)
+ {
+ struct device_node *np;
+ int i;
++ u32 val;
++ u32 cpu_pupscr_sw2iso, cpu_pupscr_sw;
++ u32 cpu_pdnscr_iso2sw, cpu_pdnscr_iso;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
+ gpc_base = of_iomap(np, 0);
+@@ -137,4 +345,197 @@
+ gic_arch_extn.irq_mask = imx_gpc_irq_mask;
+ gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
+ gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
++
++ /*
++ * If there are CPU isolation timing settings in dts,
++ * update them according to dts, otherwise, keep them
++ * with default value in registers.
++ */
++ cpu_pupscr_sw2iso = cpu_pupscr_sw =
++ cpu_pdnscr_iso2sw = cpu_pdnscr_iso = 0;
++
++ /* Read CPU isolation setting for GPC */
++ of_property_read_u32(np, "fsl,cpu_pupscr_sw2iso", &cpu_pupscr_sw2iso);
++ of_property_read_u32(np, "fsl,cpu_pupscr_sw", &cpu_pupscr_sw);
++ of_property_read_u32(np, "fsl,cpu_pdnscr_iso2sw", &cpu_pdnscr_iso2sw);
++ of_property_read_u32(np, "fsl,cpu_pdnscr_iso", &cpu_pdnscr_iso);
++
++ /* Update CPU PUPSCR timing if it is defined in dts */
++ val = readl_relaxed(gpc_base + GPC_PGC_CPU_PUPSCR);
++ if (cpu_pupscr_sw2iso)
++ val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
++ if (cpu_pupscr_sw)
++ val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT);
++ val |= cpu_pupscr_sw2iso << GPC_PGC_CPU_SW2ISO_SHIFT;
++ val |= cpu_pupscr_sw << GPC_PGC_CPU_SW_SHIFT;
++ writel_relaxed(val, gpc_base + GPC_PGC_CPU_PUPSCR);
++
++ /* Update CPU PDNSCR timing if it is defined in dts */
++ val = readl_relaxed(gpc_base + GPC_PGC_CPU_PDNSCR);
++ if (cpu_pdnscr_iso2sw)
++ val &= ~(GPC_PGC_CPU_SW2ISO_MASK << GPC_PGC_CPU_SW2ISO_SHIFT);
++ if (cpu_pdnscr_iso)
++ val &= ~(GPC_PGC_CPU_SW_MASK << GPC_PGC_CPU_SW_SHIFT);
++ val |= cpu_pdnscr_iso2sw << GPC_PGC_CPU_SW2ISO_SHIFT;
++ val |= cpu_pdnscr_iso << GPC_PGC_CPU_SW_SHIFT;
++ writel_relaxed(val, gpc_base + GPC_PGC_CPU_PDNSCR);
++}
++
++static int imx_pureg_set_voltage(struct regulator_dev *reg, int min_uV,
++ int max_uV, unsigned *selector)
++{
++ return 0;
++}
++
++static int imx_pureg_enable(struct regulator_dev *rdev)
++{
++ pu_dummy_enable = 1;
++
++ return 0;
++}
++
++static int imx_pureg_disable(struct regulator_dev *rdev)
++{
++ pu_dummy_enable = 0;
++
++ return 0;
++}
++
++static int imx_pureg_is_enable(struct regulator_dev *rdev)
++{
++ return pu_dummy_enable;
++}
++
++static int imx_pureg_list_voltage(struct regulator_dev *rdev,
++ unsigned int selector)
++{
++ return 0;
++}
++
++static struct regulator_ops pu_dummy_ops = {
++ .set_voltage = imx_pureg_set_voltage,
++ .enable = imx_pureg_enable,
++ .disable = imx_pureg_disable,
++ .is_enabled = imx_pureg_is_enable,
++ .list_voltage = imx_pureg_list_voltage,
++};
++
++static struct regulator_desc pu_dummy_desc = {
++ .name = "pureg-dummy",
++ .id = -1,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++ .ops = &pu_dummy_ops,
++};
++
++static int pu_dummy_probe(struct platform_device *pdev)
++{
++ struct regulator_config config = { };
++ int ret;
++
++ config.dev = &pdev->dev;
++ config.init_data = &pu_dummy_initdata;
++ config.of_node = pdev->dev.of_node;
++
++ pu_dummy_regulator_rdev = regulator_register(&pu_dummy_desc, &config);
++ if (IS_ERR(pu_dummy_regulator_rdev)) {
++ ret = PTR_ERR(pu_dummy_regulator_rdev);
++ dev_err(&pdev->dev, "Failed to register regulator: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
+ }
++
++static const struct of_device_id imx_pudummy_ids[] = {
++ { .compatible = "fsl,imx6-dummy-pureg" },
++};
++MODULE_DEVICE_TABLE(of, imx_pudummy_ids);
++
++static struct platform_driver pu_dummy_driver = {
++ .probe = pu_dummy_probe,
++ .driver = {
++ .name = "pu-dummy",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_pudummy_ids,
++ },
++};
++
++static int imx_gpc_probe(struct platform_device *pdev)
++{
++ int ret;
++
++ gpc_dev = &pdev->dev;
++
++ pu_reg = devm_regulator_get(gpc_dev, "pu");
++ if (IS_ERR(pu_reg)) {
++ ret = PTR_ERR(pu_reg);
++ dev_info(gpc_dev, "pu regulator not ready.\n");
++ return ret;
++ }
++ nb.notifier_call = &imx_gpc_regulator_notify;
++
++ /* Get gpu&vpu clk for power up PU by GPC */
++ if (cpu_is_imx6sl()) {
++ gpu2d_clk = devm_clk_get(gpc_dev, "gpu2d_podf");
++ openvg_axi_clk = devm_clk_get(gpc_dev, "gpu2d_ovg");
++ ipg_clk = devm_clk_get(gpc_dev, "ipg");
++ lcd_axi_clk = devm_clk_get(gpc_dev, "lcd_axi");
++ lcd_pix_clk = devm_clk_get(gpc_dev, "lcd_pix");
++ epdc_axi_clk = devm_clk_get(gpc_dev, "epdc_axi");
++ epdc_pix_clk = devm_clk_get(gpc_dev, "epdc_pix");
++ pxp_axi_clk = devm_clk_get(gpc_dev, "pxp_axi");
++ if (IS_ERR(gpu2d_clk) || IS_ERR(openvg_axi_clk)
++ || IS_ERR(ipg_clk) || IS_ERR(lcd_axi_clk)
++ || IS_ERR(lcd_pix_clk) || IS_ERR(epdc_axi_clk)
++ || IS_ERR(epdc_pix_clk) || IS_ERR(pxp_axi_clk)) {
++ dev_err(gpc_dev, "failed to get clk!\n");
++ return -ENOENT;
++ }
++ } else {
++ gpu3d_clk = devm_clk_get(gpc_dev, "gpu3d_core");
++ gpu3d_shader_clk = devm_clk_get(gpc_dev, "gpu3d_shader");
++ gpu2d_clk = devm_clk_get(gpc_dev, "gpu2d_core");
++ gpu2d_axi_clk = devm_clk_get(gpc_dev, "gpu2d_axi");
++ openvg_axi_clk = devm_clk_get(gpc_dev, "openvg_axi");
++ vpu_clk = devm_clk_get(gpc_dev, "vpu_axi");
++ ipg_clk = devm_clk_get(gpc_dev, "ipg");
++ if (IS_ERR(gpu3d_clk) || IS_ERR(gpu3d_shader_clk)
++ || IS_ERR(gpu2d_clk) || IS_ERR(gpu2d_axi_clk)
++ || IS_ERR(openvg_axi_clk) || IS_ERR(vpu_clk)
++ || IS_ERR(ipg_clk)) {
++ dev_err(gpc_dev, "failed to get clk!\n");
++ return -ENOENT;
++ }
++ }
++
++ ret = regulator_register_notifier(pu_reg, &nb);
++ if (ret) {
++ dev_err(gpc_dev,
++ "regulator notifier request failed\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static const struct of_device_id imx_gpc_ids[] = {
++ { .compatible = "fsl,imx6q-gpc" },
++};
++MODULE_DEVICE_TABLE(of, imx_gpc_ids);
++
++static struct platform_driver imx_gpc_platdrv = {
++ .driver = {
++ .name = "imx-gpc",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_gpc_ids,
++ },
++ .probe = imx_gpc_probe,
++};
++module_platform_driver(imx_gpc_platdrv);
++
++module_platform_driver(pu_dummy_driver);
++
++MODULE_AUTHOR("Anson Huang <b20788@freescale.com>");
++MODULE_DESCRIPTION("Freescale i.MX GPC driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/hardware.h linux-linaro-stable-mx6/arch/arm/mach-imx/hardware.h
+--- linux-3.10.30.orig/arch/arm/mach-imx/hardware.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/hardware.h 2014-05-15 20:33:35.381850824 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+@@ -20,6 +20,9 @@
+ #ifndef __ASM_ARCH_MXC_HARDWARE_H__
+ #define __ASM_ARCH_MXC_HARDWARE_H__
+
++#ifndef __ASSEMBLY__
++#include <asm/io.h>
++#endif
+ #include <asm/sizes.h>
+
+ #define addr_in_module(addr, mod) \
+@@ -104,6 +107,7 @@
+
+ #include "mx51.h"
+ #include "mx53.h"
++#include "mx6.h"
+ #include "mx3x.h"
+ #include "mx31.h"
+ #include "mx35.h"
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/hotplug.c linux-linaro-stable-mx6/arch/arm/mach-imx/hotplug.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/hotplug.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/hotplug.c 2014-05-15 20:33:35.381850824 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011, 2013 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -52,7 +52,8 @@
+ * the register being cleared to kill the cpu.
+ */
+ imx_set_cpu_arg(cpu, ~0);
+- cpu_do_idle();
++ for (;;)
++ cpu_do_idle();
+ }
+
+ int imx_cpu_kill(unsigned int cpu)
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/imx25-dt.c linux-linaro-stable-mx6/arch/arm/mach-imx/imx25-dt.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/imx25-dt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/imx25-dt.c 2014-05-15 20:33:35.381850824 +0200
+@@ -19,6 +19,8 @@
+
+ static void __init imx25_dt_init(void)
+ {
++ mxc_arch_reset_init_dt();
++
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ }
+
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/imx27-dt.c linux-linaro-stable-mx6/arch/arm/mach-imx/imx27-dt.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/imx27-dt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/imx27-dt.c 2014-05-15 20:33:35.381850824 +0200
+@@ -22,6 +22,8 @@
+ {
+ struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+
++ mxc_arch_reset_init_dt();
++
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+ platform_device_register_full(&devinfo);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/imx31-dt.c linux-linaro-stable-mx6/arch/arm/mach-imx/imx31-dt.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/imx31-dt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/imx31-dt.c 2014-05-15 20:33:35.381850824 +0200
+@@ -20,6 +20,8 @@
+
+ static void __init imx31_dt_init(void)
+ {
++ mxc_arch_reset_init_dt();
++
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ }
+
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/imx51-dt.c linux-linaro-stable-mx6/arch/arm/mach-imx/imx51-dt.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/imx51-dt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/imx51-dt.c 2014-05-15 20:33:35.381850824 +0200
+@@ -23,6 +23,8 @@
+ {
+ struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+
++ mxc_arch_reset_init_dt();
++
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ platform_device_register_full(&devinfo);
+ }
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/imx6sl_wfi.S linux-linaro-stable-mx6/arch/arm/mach-imx/imx6sl_wfi.S
+--- linux-3.10.30.orig/arch/arm/mach-imx/imx6sl_wfi.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/imx6sl_wfi.S 2014-05-15 20:33:35.381850824 +0200
+@@ -0,0 +1,639 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/linkage.h>
++#define IRAM_WAIT_SIZE (1 << 11)
++
++ .macro sl_ddr_io_save
++
++ ldr r4, [r1, #0x30c] /* DRAM_DQM0 */
++ ldr r5, [r1, #0x310] /* DRAM_DQM1 */
++ ldr r6, [r1, #0x314] /* DRAM_DQM2 */
++ ldr r7, [r1, #0x318] /* DRAM_DQM3 */
++ stmfd r9!, {r4-r7}
++
++ ldr r4, [r1, #0x5c4] /* GPR_B0DS */
++ ldr r5, [r1, #0x5cc] /* GPR_B1DS */
++ ldr r6, [r1, #0x5d4] /* GPR_B2DS */
++ ldr r7, [r1, #0x5d8] /* GPR_B3DS */
++ stmfd r9!, {r4-r7}
++
++ ldr r4, [r1, #0x300] /* DRAM_CAS */
++ ldr r5, [r1, #0x31c] /* DRAM_RAS */
++ ldr r6, [r1, #0x338] /* DRAM_SDCLK_0 */
++ ldr r7, [r1, #0x5ac] /* GPR_ADDS*/
++ stmfd r9!, {r4-r7}
++
++ ldr r4, [r1, #0x5b0] /* DDRMODE_CTL */
++ ldr r5, [r1, #0x5c0] /* DDRMODE */
++ ldr r6, [r1, #0x33c] /* DRAM_SODT0*/
++ ldr r7, [r1, #0x340] /* DRAM_SODT1*/
++ stmfd r9!, {r4-r7}
++
++ ldr r4, [r1, #0x330] /* DRAM_SDCKE0 */
++ ldr r5, [r1, #0x334] /* DRAM_SDCKE1 */
++ ldr r6, [r1, #0x320] /* DRAM_RESET */
++ stmfd r9!, {r4-r6}
++
++ .endm
++
++ .macro sl_ddr_io_restore
++
++ /*
++ * r9 points to IRAM stack.
++ * r1 points to IOMUX base address.
++ * r8 points to MMDC base address.
++ */
++ ldmea r9!, {r4-r7}
++ str r4, [r1, #0x30c] /* DRAM_DQM0 */
++ str r5, [r1, #0x310] /* DRAM_DQM1 */
++ str r6, [r1, #0x314] /* DRAM_DQM2 */
++ str r7, [r1, #0x318] /* DRAM_DQM3 */
++
++ ldmea r9!, {r4-r7}
++ str r4, [r1, #0x5c4] /* GPR_B0DS */
++ str r5, [r1, #0x5cc] /* GPR_B1DS */
++ str r6, [r1, #0x5d4] /* GPR_B2DS */
++ str r7, [r1, #0x5d8] /* GPR_B3DS */
++
++ ldmea r9!, {r4-r7}
++ str r4, [r1, #0x300] /* DRAM_CAS */
++ str r5, [r1, #0x31c] /* DRAM_RAS */
++ str r6, [r1, #0x338] /* DRAM_SDCLK_0 */
++ str r7, [r1, #0x5ac] /* GPR_ADDS*/
++
++ ldmea r9!, {r4-r7}
++ str r4, [r1, #0x5b0] /* DDRMODE_CTL */
++ str r5, [r1, #0x5c0] /* DDRMODE */
++ str r6, [r1, #0x33c] /* DRAM_SODT0*/
++ str r7, [r1, #0x340] /* DRAM_SODT1*/
++
++ ldmea r9!, {r4-r6}
++ str r4, [r1, #0x330] /* DRAM_SDCKE0 */
++ str r5, [r1, #0x334] /* DRAM_SDCKE1 */
++ str r6, [r1, #0x320] /* DRAM_RESET */
++
++ /*
++ * Need to reset the FIFO to avoid MMDC lockup
++ * caused because of floating/changing the
++ * configuration of many DDR IO pads.
++ */
++ ldr r7, =0x83c
++ ldr r6, [r8, r7]
++ orr r6, r6, #0x80000000
++ str r6, [r8, r7]
++fifo_reset1_wait:
++ ldr r6, [r8, r7]
++ and r6, r6, #0x80000000
++ cmp r6, #0
++ bne fifo_reset1_wait
++
++ /* reset FIFO a second time */
++ ldr r6, [r8, r7]
++ orr r6, r6, #0x80000000
++ str r6, [r8, r7]
++fifo_reset2_wait:
++ ldr r6, [r8, r7]
++ and r6, r6, #0x80000000
++ cmp r6, #0
++ bne fifo_reset2_wait
++
++ .endm
++
++ .macro sl_ddr_io_set_lpm
++
++ mov r4, #0
++ str r4, [r1, #0x30c] /* DRAM_DQM0 */
++ str r4, [r1, #0x310] /* DRAM_DQM1 */
++ str r4, [r1, #0x314] /* DRAM_DQM2 */
++ str r4, [r1, #0x318] /* DRAM_DQM3 */
++
++ str r4, [r1, #0x5c4] /* GPR_B0DS */
++ str r4, [r1, #0x5cc] /* GPR_B1DS */
++ str r4, [r1, #0x5d4] /* GPR_B2DS */
++ str r4, [r1, #0x5d8] /* GPR_B3DS */
++
++ str r4, [r1, #0x300] /* DRAM_CAS */
++ str r4, [r1, #0x31c] /* DRAM_RAS */
++ str r4, [r1, #0x338] /* DRAM_SDCLK_0 */
++ str r4, [r1, #0x5ac] /* GPR_ADDS*/
++
++ str r4, [r1, #0x5b0] /* DDRMODE_CTL */
++ str r4, [r1, #0x5c0] /* DDRMODE */
++ str r4, [r1, #0x33c] /* DRAM_SODT0*/
++ str r4, [r1, #0x340] /* DRAM_SODT1*/
++
++ mov r4, #0x80000
++ str r4, [r1, #0x320] /* DRAM_RESET */
++ mov r4, #0x1000
++ str r4, [r1, #0x330] /* DRAM_SDCKE0 */
++ str r4, [r1, #0x334] /* DRAM_SDCKE1 */
++
++ .endm
++
++/*
++ * imx6sl_low_power_wfi
++ *
++ * Idle the processor (eg, wait for interrupt).
++ * Make sure DDR is in self-refresh.
++ * IRQs are already disabled.
++ * r0: WFI IRAMcode base address.
++ * r1: IOMUX base address
++ * r2: Base address of CCM, ANATOP and MMDC
++ * r3: 1 if in audio_bus_freq_mode
++ */
++ .align 3
++ENTRY(imx6sl_low_power_wfi)
++
++ push {r4-r11}
++
++mx6sl_lpm_wfi:
++ /* Store audio_bus_freq_mode */
++ mov r11, r3
++
++ mov r4,r2
++ /* Get the IRAM data storage address. */
++ mov r10, r0
++ mov r9, r0 /* get suspend_iram_base */
++ add r9, r9, #IRAM_WAIT_SIZE
++
++ /* Anatop Base address in r3. */
++ ldr r3, [r4]
++ /* CCM Base Address in r2 */
++ ldr r2, [r4, #0x4]
++ /* MMDC Base Address in r8 */
++ ldr r8, [r4, #0x8]
++ /* L2 Base Address in r7 */
++ ldr r7, [r4, #0xC]
++
++ ldr r6, [r8]
++ ldr r6, [r3]
++ ldr r6, [r2]
++ ldr r6, [r1]
++
++ /* Store the original ARM PODF. */
++ ldr r0, [r2, #0x10]
++
++ /* Drain all the L1 buffers. */
++ dsb
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * Need to make sure the buffers in L2 are drained.
++ * Performing a sync operation does this.
++ */
++ mov r6, #0x0
++ str r6, [r7, #0x730]
++#endif
++
++ /*
++ * The second dsb might be needed to keep cache sync (device write)
++ * ordering with the memory accesses before it.
++ */
++ dsb
++ isb
++
++ /* Save the DDR IO state. */
++ sl_ddr_io_save
++
++ /* Disable Automatic power savings. */
++ ldr r6, [r8, #0x404]
++ orr r6, r6, #0x01
++ str r6, [r8, #0x404]
++
++ /* Make the DDR explicitly enter self-refresh. */
++ ldr r6, [r8, #0x404]
++ orr r6, r6, #0x200000
++ str r6, [r8, #0x404]
++
++poll_dvfs_set_1:
++ ldr r6, [r8, #0x404]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ bne poll_dvfs_set_1
++
++ /* set SBS step-by-step mode */
++ ldr r6, [r8, #0x410]
++ orr r6, r6, #0x100
++ str r6, [r8, #0x410]
++
++ cmp r11, #1
++ beq audio_mode
++ /*
++ * Now set DDR rate to 1MHz.
++ * DDR is from bypassed PLL2 on periph2_clk2 path.
++ * Set the periph2_clk2_podf to divide by 8.
++ */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x07
++ str r6, [r2, #0x14]
++
++ /* Now set MMDC PODF to divide by 3. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ orr r6, r6, #0x10
++ str r6, [r2, #0x14]
++ b mmdc_podf
++
++audio_mode:
++ /* MMDC is from PLL2_200M.
++ * Set the mmdc_podf to div by 8.
++ */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x38
++ str r6, [r2, #0x14]
++
++ /* Loop till podf is accepted. */
++mmdc_podf:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0x0
++ bne mmdc_podf
++
++ /* Set the DDR IO in LPM state. */
++ sl_ddr_io_set_lpm
++
++ cmp r11, #1
++ beq do_audio_arm_clk
++
++ /*
++ * Check if none of the PLLs are
++ * locked, except PLL1 which will get
++ * bypassed below.
++ * We should not be here if PLL2 is not
++ * bypassed.
++ */
++ ldr r7, =1
++ /* USB1 PLL3 */
++ ldr r6, [r3, #0x10]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ beq no_analog_saving
++
++ /* USB2 PLL7 */
++ ldr r6, [r3, #0x20]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ beq no_analog_saving
++
++ /* Audio PLL4 */
++ ldr r6, [r3, #0x70]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ beq no_analog_saving
++
++ /* Video PLL5 */
++ ldr r6, [r3, #0xA0]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ beq no_analog_saving
++
++ /* ENET PLL8 */
++ ldr r6, [r3, #0xE0]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ beq no_analog_saving
++
++ b cont
++
++no_analog_saving:
++ ldr r7, =0
++
++cont:
++ /* Set the AHB to 3MHz. AXI to 3MHz. */
++ ldr r9, [r2, #0x14]
++ mov r6, r9
++ orr r6, r6, #0x1c00
++ orr r6, r6, #0x70000
++ str r6, [r2, #0x14]
++
++ /* Loop till podf is accepted. */
++ahb_podf:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0x0
++ bne podf_loop
++
++ /*
++ * Now set ARM to 24MHz.
++ * Move ARM to be sourced from STEP_CLK
++ * after setting STEP_CLK to 24MHz.
++ */
++ ldr r6, [r2, #0xc]
++ bic r6, r6, #0x100
++ str r6, [r2, #0x0c]
++ /* Now PLL1_SW_CLK to step_clk. */
++ ldr r6, [r2, #0x0c]
++ orr r6, r6, #0x4
++ str r6, [r2, #0x0c]
++
++ /* Bypass PLL1 and power it down. */
++ ldr r6, =(1 << 16)
++ orr r6, r6, #0x1000
++ str r6, [r3, #0x04]
++
++ /*
++ * Set the ARM PODF to divide by 8.
++ * IPG is at 1.5MHz here, we need ARM to
++ * run at the 12:5 ratio (WAIT mode issue).
++ */
++ ldr r6, =0x7
++ str r6, [r2, #0x10]
++
++ /* Loop till podf is accepted. */
++podf_loop:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0x0
++ bne podf_loop
++
++ /*
++ * Check if we can save some
++ * power in the Analog section.
++ */
++ cmp r7, #0x1
++ bne do_wfi
++
++ /* Disable 1p1 brown out. */
++ ldr r6, [r3, #0x110]
++ bic r6, r6, #0x2
++ str r6, [r3, #0x110]
++
++ /* Enable the weak 2P5 */
++ ldr r6, [r3, #0x130]
++ orr r6, r6, #0x40000
++ str r6, [r3, #0x130]
++
++ /* Disable main 2p5. */
++ ldr r6, [r3, #0x130]
++ bic r6, r6, #0x1
++ str r6, [r3, #0x130]
++
++ /*
++ * Set the OSC bias current to -37.5%
++ * to drop the power on VDDHIGH.
++ */
++ ldr r6, [r3, #0x150]
++ orr r6, r6, #0xC000
++ str r6, [r3, #0x150]
++
++ /* Enable low power bandgap */
++ ldr r6, [r3, #0x260]
++ orr r6, r6, #0x20
++ str r6, [r3, #0x260]
++
++ /*
++ * Turn off the bias current
++ * from the regular bandgap.
++ */
++ ldr r6, [r3, #0x260]
++ orr r6, r6, #0x80
++ str r6, [r3, #0x260]
++
++ /*
++ * Clear the REFTOP_SELFBIASOFF,
++ * self-bias circuit of the band gap.
++ * Per RM, should be cleared when
++ * band gap is powered down.
++ */
++ ldr r6, [r3, #0x150]
++ bic r6, r6, #0x8
++ str r6, [r3, #0x150]
++
++ /* Power down the regular bandgap. */
++ ldr r6, [r3, #0x150]
++ orr r6, r6, #0x1
++ str r6, [r3, #0x150]
++
++ b do_wfi
++
++do_audio_arm_clk:
++ /*
++ * ARM is from PLL2_PFD2_400M here.
++ * Switch ARM to bypassed PLL1.
++ */
++ ldr r6, [r2, #0xC]
++ bic r6, r6, #0x4
++ str r6, [r2, #0xC]
++
++ /*
++ * Set the ARM_PODF to divide by 2
++ * as IPG is at 4MHz, we cannot run
++ * ARM_CLK above 9.6MHz when
++ * system enters WAIT mode.
++ */
++ ldr r6, =0x2
++ str r6, [r2, #0x10]
++
++ /* Loop till podf is accepted. */
++podf_loop_audio:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0x0
++ bne podf_loop_audio
++
++do_wfi:
++ /* Now do WFI. */
++ wfi
++
++ /* Set original ARM PODF back. */
++ str r0, [r2, #0x10]
++
++ /* Loop till podf is accepted. */
++podf_loop1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0x0
++ bne podf_loop1
++
++ cmp r11, #1
++ beq audio_arm_clk_restore
++
++ /*
++ * Check if powered down
++ * analog components.
++ */
++ cmp r7, #0x1
++ bne skip_analog_restore
++
++ /* Power up the regular bandgap. */
++ ldr r6, [r3, #0x150]
++ bic r6, r6, #0x1
++ str r6, [r3, #0x150]
++
++ /*
++ * Turn on the bias current
++ * from the regular bandgap.
++ */
++ ldr r6, [r3, #0x260]
++ bic r6, r6, #0x80
++ str r6, [r3, #0x260]
++
++ /* Disable the low power bandgap */
++ ldr r6, [r3, #0x260]
++ bic r6, r6, #0x20
++ str r6, [r3, #0x260]
++
++ /*
++ * Set the OSC bias current to max
++ * value for normal operation.
++ */
++ ldr r6, [r3, #0x150]
++ bic r6, r6, #0xC000
++ str r6, [r3, #0x150]
++
++ /* Enable main 2p5. */
++ ldr r6, [r3, #0x130]
++ orr r6, r6, #0x1
++ str r6, [r3, #0x130]
++
++ /* Ensure the 2P5 is up. */
++loop_2p5:
++ ldr r6, [r3, #0x130]
++ and r6, r6, #0x20000
++ cmp r6, #0x20000
++ bne loop_2p5
++
++ /* Disable the weak 2P5 */
++ ldr r6, [r3, #0x130]
++ bic r6, r6, #0x40000
++ str r6, [r3, #0x130]
++
++ /* Enable 1p1 brown out. */
++ ldr r6, [r3, #0x110]
++ orr r6, r6, #0x2
++ str r6, [r3, #0x110]
++
++skip_analog_restore:
++
++ /* Power up PLL1 and un-bypass it. */
++ ldr r6, =(1 << 12)
++ str r6, [r3, #0x08]
++
++ /* Wait for PLL1 to relock. */
++wait_for_pll_lock:
++ ldr r6, [r3, #0x0]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ bne wait_for_pll_lock
++
++ ldr r6, =(1 << 16)
++ str r6, [r3, #0x08]
++
++ /* Set PLL1_sw_clk back to PLL1. */
++ ldr r6, [r2, #0x0c]
++ bic r6, r6, #0x4
++ str r6, [r2, #0xc]
++
++ /* Restore AHB/AXI back. */
++ str r9, [r2, #0x14]
++
++ /* Loop till podf is accepted. */
++ahb_podf1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0x0
++ bne podf_loop1
++
++ b wfi_restore
++
++ audio_arm_clk_restore:
++ /* Move ARM back to PLL2_PFD2_400M */
++ ldr r6, [r2, #0xC]
++ orr r6, r6, #0x4
++ str r6, [r2, #0xC]
++
++wfi_restore:
++ /* get suspend_iram_base */
++ mov r9, r10
++ add r9, r9, #IRAM_WAIT_SIZE
++
++ /* Restore the DDR IO before exiting self-refresh. */
++ sl_ddr_io_restore
++
++ /*
++ * Set MMDC back to 24MHz.
++ * Set periph2_clk2_podf to divide by 1
++ * Now set MMDC PODF to divide by 1.
++ */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x3f
++ str r6, [r2, #0x14]
++
++mmdc_podf1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0x0
++ bne mmdc_podf1
++
++ /* clear DVFS - exit from self refresh mode */
++ ldr r6, [r8, #0x404]
++ bic r6, r6, #0x200000
++ str r6, [r8, #0x404]
++
++poll_dvfs_clear_1:
++ ldr r6, [r8, #0x404]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ beq poll_dvfs_clear_1
++
++ /*
++ * Add these nops so that the
++ * prefetcher will not try to get
++ * any instructions from DDR.
++ * The prefetch depth is about 23
++ * on A9, so adding 25 nops.
++ */
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ /* Enable Automatic power savings. */
++ ldr r6, [r8, #0x404]
++ bic r6, r6, #0x01
++ str r6, [r8, #0x404]
++
++ /* clear SBS - unblock DDR accesses */
++ ldr r6, [r8, #0x410]
++ bic r6, r6, #0x100
++ str r6, [r8, #0x410]
++
++
++ pop {r4-r11}
++
++ /* Restore registers */
++ mov pc, lr
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/Kconfig linux-linaro-stable-mx6/arch/arm/mach-imx/Kconfig
+--- linux-3.10.30.orig/arch/arm/mach-imx/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/Kconfig 2014-05-15 20:33:35.353850621 +0200
+@@ -1,5 +1,6 @@
+ config ARCH_MXC
+ bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
++ select ARCH_HAS_RESET_CONTROLLER
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_PATCH_PHYS_VIRT
+ select AUTO_ZRELADDR if !ZBOOT_ROM
+@@ -8,8 +9,11 @@
+ select GENERIC_ALLOCATOR
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
++ select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
+ select MULTI_IRQ_HANDLER
++ select SOC_BUS
+ select SPARSE_IRQ
++ select SRAM
+ select USE_OF
+ help
+ Support for Freescale MXC/iMX-based family of processors
+@@ -73,7 +77,6 @@
+
+ config HAVE_IMX_SRC
+ def_bool y if SMP
+- select ARCH_HAS_RESET_CONTROLLER
+
+ config IMX_HAVE_IOMUX_V1
+ bool
+@@ -806,16 +809,54 @@
+ select HAVE_IMX_SRC
+ select HAVE_SMP
+ select MFD_SYSCON
++ select MIGHT_HAVE_PCI
++ select PCI_DOMAINS if PCI
++ select ARCH_SUPPORTS_MSI
+ select PINCTRL
+ select PINCTRL_IMX6Q
+ select PL310_ERRATA_588369 if CACHE_PL310
+ select PL310_ERRATA_727915 if CACHE_PL310
+ select PL310_ERRATA_769419 if CACHE_PL310
+ select PM_OPP if PM
++ select ZONE_DMA
+
+ help
+ This enables support for Freescale i.MX6 Quad processor.
+
++config SOC_IMX6SL
++ bool "i.MX6 SoloLite support"
++ select ARM_ERRATA_754322
++ select ARM_ERRATA_775420
++ select ARM_GIC
++ select CPU_V7
++ select HAVE_IMX_ANATOP
++ select HAVE_IMX_GPC
++ select HAVE_IMX_MMDC
++ select HAVE_IMX_SRC
++ select PINCTRL
++ select PINCTRL_IMX6SL
++ select PL310_ERRATA_588369 if CACHE_PL310
++ select PL310_ERRATA_727915 if CACHE_PL310
++ select PL310_ERRATA_769419 if CACHE_PL310
++
++ help
++ This enables support for Freescale i.MX6 SoloLite processor.
++
++config SOC_VF610
++ bool "Vybrid Family VF610 support"
++ select CPU_V7
++ select ARM_GIC
++ select CLKSRC_OF
++ select PINCTRL
++ select PINCTRL_VF610
++ select VF_PIT_TIMER
++ select PL310_ERRATA_588369 if CACHE_PL310
++ select PL310_ERRATA_727915 if CACHE_PL310
++ select PL310_ERRATA_769419 if CACHE_PL310
++
++ help
++ This enable support for Freescale Vybrid VF610 processor.
++
+ endif
+
+ source "arch/arm/mach-imx/devices/Kconfig"
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/lpddr2_freq_imx6.S linux-linaro-stable-mx6/arch/arm/mach-imx/lpddr2_freq_imx6.S
+--- linux-3.10.30.orig/arch/arm/mach-imx/lpddr2_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/lpddr2_freq_imx6.S 2014-05-15 20:33:35.385850852 +0200
+@@ -0,0 +1,484 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/linkage.h>
++
++ .macro mx6sl_switch_to_24MHz
++
++ /*
++ * Set MMDC clock to be sourced from PLL3.
++ * Ensure first periph2_clk2 is sourced from PLL3.
++ * Set the PERIPH2_CLK2_PODF to divide by 2.
++ */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x7
++ orr r6, r6, #0x1
++ str r6, [r2, #0x14]
++
++ /* Select PLL3 to source MMDC. */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* Swtich periph2_clk_sel to run from PLL3. */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch1
++
++ /*
++ * Need to clock gate the 528 PFDs before
++ * powering down PLL2.
++ * Only the PLL2_PFD2_400M should be ON
++ * at this time, so only clock gate that one.
++ */
++ ldr r6, [r3, #0x100]
++ orr r6, r6, #0x800000
++ str r6, [r3, #0x100]
++
++ /*
++ * Set PLL2 to bypass state. We should be here
++ * only if MMDC is not sourced from PLL2.
++ */
++ ldr r6, [r3, #0x30]
++ orr r6, r6, #0x10000
++ str r6, [r3, #0x30]
++
++ ldr r6, [r3, #0x30]
++ orr r6, r6, #0x1000
++ str r6, [r3, #0x30]
++
++ /* Ensure pre_periph2_clk_mux is set to pll2 */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x600000
++ str r6, [r2, #0x18]
++
++ /* Set MMDC clock to be sourced from the bypassed PLL2. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch2:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch2
++
++ /*
++ * Now move MMDC back to periph2_clk2 source.
++ * after selecting PLL2 as the option.
++ * Select PLL2 as the source.
++ */
++ ldr r6, [r2, #0x18]
++ orr r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* set periph2_clk2_podf to divide by 1. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x7
++ str r6, [r2, #0x14]
++
++ /* Now move periph2_clk to periph2_clk2 source */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch3:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch3
++
++ /* Now set the MMDC PODF back to 1.*/
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ str r6, [r2, #0x14]
++
++mmdc_podf0:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf0
++
++ .endm
++
++ .macro ddr_switch_400MHz
++
++ /* Set MMDC divider first, in case PLL3 is at 480MHz. */
++ ldr r6, [r3, #0x10]
++ and r6, r6, #0x10000
++ cmp r6, #0x10000
++ beq pll3_in_bypass
++
++ /* Set MMDC divder to divide by 2. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ orr r6, r6, #0x8
++ str r6, [r2, #0x14]
++
++mmdc_podf:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf
++
++pll3_in_bypass:
++ /*
++ * Check if we are switching between
++ * 400Mhz <-> 100MHz.If so, we should
++ * try to source MMDC from PLL2_200M.
++ */
++ cmp r1, #0
++ beq not_low_bus_freq
++
++ /* Ensure that MMDC is sourced from PLL2 mux first. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch4:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch4
++
++not_low_bus_freq:
++ /* Now ensure periph2_clk2_sel mux is set to PLL3 */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* Now switch MMDC to PLL3. */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch5:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch5
++
++ /*
++ * Check if PLL2 is already unlocked.
++ * If so do nothing with PLL2.
++ */
++ cmp r1, #0
++ beq pll2_already_on
++
++ /* Now power up PLL2 and unbypass it. */
++ ldr r6, [r3, #0x30]
++ bic r6, r6, #0x1000
++ str r6, [r3, #0x30]
++
++ /* Make sure PLL2 has locked.*/
++wait_for_pll_lock:
++ ldr r6, [r3, #0x30]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ bne wait_for_pll_lock
++
++ ldr r6, [r3, #0x30]
++ bic r6, r6, #0x10000
++ str r6, [r3, #0x30]
++
++ /*
++ * Need to enable the 528 PFDs after
++ * powering up PLL2.
++ * Only the PLL2_PFD2_400M should be ON
++ * as it feeds the MMDC. Rest should have
++ * been managed by clock code.
++ */
++ ldr r6, [r3, #0x100]
++ bic r6, r6, #0x800000
++ str r6, [r3, #0x100]
++
++pll2_already_on:
++ /*
++ * Now switch MMDC clk back to pll2_mux option.
++ * Ensure pre_periph2_clk2 is set to pll2_pfd_400M.
++ * If switching to audio DDR freq, set the
++ * pre_periph2_clk2 to PLL2_PFD_200M
++ */
++ ldr r6, =400000000
++ cmp r6, r0
++ bne use_pll2_pfd_200M
++
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x600000
++ orr r6, r6, #0x200000
++ str r6, [r2, #0x18]
++ ldr r6, =400000000
++ b cont2
++
++use_pll2_pfd_200M:
++ ldr r6, [r2, #0x18]
++ orr r6, r6, #0x600000
++ str r6, [r2, #0x18]
++ ldr r6, =200000000
++
++cont2:
++ ldr r4, [r2, #0x14]
++ bic r4, r4, #0x4000000
++ str r4, [r2, #0x14]
++
++periph2_clk_switch6:
++ ldr r4, [r2, #0x48]
++ cmp r4, #0
++ bne periph2_clk_switch6
++
++change_divider_only:
++ /*
++ * Calculate the MMDC divider
++ * based on the requested freq.
++ */
++ ldr r4, =0
++Loop2:
++ sub r6, r6, r0
++ cmp r6, r0
++ blt Div_Found
++ add r4, r4, #1
++ bgt Loop2
++
++ /* Shift divider into correct offset. */
++ lsl r4, r4, #3
++Div_Found:
++ /* Set the MMDC PODF. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ orr r6, r6, r4
++ str r6, [r2, #0x14]
++
++mmdc_podf1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf1
++
++ .endm
++
++ .macro mmdc_clk_lower_100MHz
++
++ /*
++ * Prior to reducing the DDR frequency (at 528/400 MHz),
++ * read the Measure unit count bits (MU_UNIT_DEL_NUM)
++ */
++ ldr r5, =0x8B8
++ ldr r6, [r8, r5]
++ /* Original MU unit count */
++ mov r6, r6, LSR #16
++ ldr r4, =0x3FF
++ and r6, r6, r4
++ /* Original MU unit count * 2 */
++ mov r7, r6, LSL #1
++ /*
++ * Bypass the automatic measure unit when below 100 MHz
++ * by setting the Measure unit bypass enable bit (MU_BYP_EN)
++ */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x400
++ str r6, [r8, r5]
++ /*
++ * Double the measure count value read in step 1 and program it in the
++ * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit
++ * Register for the reduced frequency operation below 100 MHz
++ */
++ ldr r6, [r8, r5]
++ ldr r4, =0x3FF
++ bic r6, r6, r4
++ orr r6, r6, r7
++ str r6, [r8, r5]
++ /* Now perform a Force Measurement. */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x800
++ str r6, [r8, r5]
++ /* Wait for FRC_MSR to clear. */
++force_measure:
++ ldr r6, [r8, r5]
++ and r6, r6, #0x800
++ cmp r6, #0x0
++ bne force_measure
++
++ .endm
++
++ .macro mmdc_clk_above_100MHz
++
++ /* Make sure that the PHY measurement unit is NOT in bypass mode */
++ ldr r5, =0x8B8
++ ldr r6, [r8, r5]
++ bic r6, r6, #0x400
++ str r6, [r8, r5]
++ /* Now perform a Force Measurement. */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x800
++ str r6, [r8, r5]
++ /* Wait for FRC_MSR to clear. */
++force_measure1:
++ ldr r6, [r8, r5]
++ and r6, r6, #0x800
++ cmp r6, #0x0
++ bne force_measure1
++ .endm
++
++/*
++ * mx6_lpddr2_freq_change
++ *
++ * Make sure DDR is in self-refresh.
++ * IRQs are already disabled.
++ * r0 : DDR freq.
++ * r1: low_bus_freq_mode flag
++ * r2: Pointer to array containing addresses of registers.
++ */
++ .align 3
++ENTRY(mx6_lpddr2_freq_change)
++
++ push {r4-r10}
++
++ mov r4, r2
++ ldr r3, [r4] @ANATOP_BASE_ADDR
++ ldr r2, [r4, #0x4] @CCM_BASE_ADDR
++ ldr r8, [r4, #0x8] @MMDC_P0_BASE_ADDR
++ ldr r7, [r4, #0xC] @L2_BASE_ADDR
++
++lpddr2_freq_change:
++ adr r9, lpddr2_freq_change
++
++ /* Prime all TLB entries. */
++ ldr r6, [r9]
++ ldr r6, [r8]
++ ldr r6, [r3]
++ ldr r6, [r2]
++
++ /* Drain all the L1 buffers. */
++ dsb
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * Need to make sure the buffers in L2 are drained.
++ * Performing a sync operation does this.
++ */
++ mov r6, #0x0
++ str r6, [r7, #0x730]
++#endif
++
++ /*
++ * The second dsb might be needed to keep cache sync (device write)
++ * ordering with the memory accesses before it.
++ */
++ dsb
++ isb
++
++ /* Disable Automatic power savings. */
++ ldr r6, [r8, #0x404]
++ orr r6, r6, #0x01
++ str r6, [r8, #0x404]
++
++ /* MMDC0_MDPDC disable power down timer */
++ ldr r6, [r8, #0x4]
++ bic r6, r6, #0xff00
++ str r6, [r8, #0x4]
++
++ /* Delay for a while */
++ ldr r10, =10
++delay1:
++ ldr r7, =0
++cont1:
++ ldr r6, [r8, r7]
++ add r7, r7, #4
++ cmp r7, #16
++ bne cont1
++ sub r10, r10, #1
++ cmp r10, #0
++ bgt delay1
++
++ /* Make the DDR explicitly enter self-refresh. */
++ ldr r6, [r8, #0x404]
++ orr r6, r6, #0x200000
++ str r6, [r8, #0x404]
++
++poll_dvfs_set_1:
++ ldr r6, [r8, #0x404]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ bne poll_dvfs_set_1
++
++ /* set SBS step-by-step mode */
++ ldr r6, [r8, #0x410]
++ orr r6, r6, #0x100
++ str r6, [r8, #0x410]
++
++ ldr r10, =100000000
++ cmp r0, r10
++ bgt set_ddr_mu_above_100
++ mmdc_clk_lower_100MHz
++
++set_ddr_mu_above_100:
++ ldr r10, =24000000
++ cmp r0, r10
++ beq set_to_24MHz
++
++ ddr_switch_400MHz
++
++ ldr r10,=100000000
++ cmp r0, r10
++ blt done
++ mmdc_clk_above_100MHz
++
++ b done
++
++set_to_24MHz:
++ mx6sl_switch_to_24MHz
++
++done:
++ /* clear DVFS - exit from self refresh mode */
++ ldr r6, [r8, #0x404]
++ bic r6, r6, #0x200000
++ str r6, [r8, #0x404]
++
++poll_dvfs_clear_1:
++ ldr r6, [r8, #0x404]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ beq poll_dvfs_clear_1
++
++ /* Enable Automatic power savings. */
++ ldr r6, [r8, #0x404]
++ bic r6, r6, #0x01
++ str r6, [r8, #0x404]
++
++ ldr r10, =24000000
++ cmp r0, r10
++ beq skip_power_down
++
++ /* Enable MMDC power down timer. */
++ ldr r6, [r8, #0x4]
++ orr r6, r6, #0x5500
++ str r6, [r8, #0x4]
++
++skip_power_down:
++ /* clear SBS - unblock DDR accesses */
++ ldr r6, [r8, #0x410]
++ bic r6, r6, #0x100
++ str r6, [r8, #0x410]
++
++ pop {r4-r10}
++
++ /* Restore registers */
++ mov pc, lr
++
++ .type mx6_lpddr2_do_iram, #object
++ENTRY(mx6_lpddr2_do_iram)
++ .word mx6_lpddr2_freq_change
++ .size mx6_lpddr2_freq_change, . - mx6_lpddr2_freq_change
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mach-imx53.c linux-linaro-stable-mx6/arch/arm/mach-imx/mach-imx53.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mach-imx53.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mach-imx53.c 2014-05-15 20:33:35.385850852 +0200
+@@ -21,6 +21,7 @@
+ #include <asm/mach/time.h>
+
+ #include "common.h"
++#include "hardware.h"
+ #include "mx53.h"
+
+ static void __init imx53_qsb_init(void)
+@@ -38,6 +39,8 @@
+
+ static void __init imx53_dt_init(void)
+ {
++ mxc_arch_reset_init_dt();
++
+ if (of_machine_is_compatible("fsl,imx53-qsb"))
+ imx53_qsb_init();
+
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mach-imx6q.c linux-linaro-stable-mx6/arch/arm/mach-imx/mach-imx6q.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mach-imx6q.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mach-imx6q.c 2014-05-15 20:33:35.385850852 +0200
+@@ -10,12 +10,14 @@
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
++#include <linux/can/platform/flexcan.h>
+ #include <linux/clk.h>
++#include <linux/clk-provider.h>
+ #include <linux/clkdev.h>
+ #include <linux/clocksource.h>
+ #include <linux/cpu.h>
+-#include <linux/delay.h>
+ #include <linux/export.h>
++#include <linux/gpio.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+@@ -23,13 +25,15 @@
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <linux/of_gpio.h>
+ #include <linux/of_platform.h>
+ #include <linux/opp.h>
+ #include <linux/phy.h>
+ #include <linux/regmap.h>
+ #include <linux/micrel_phy.h>
+ #include <linux/mfd/syscon.h>
+-#include <asm/hardware/cache-l2x0.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/of_net.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/system_misc.h>
+@@ -38,62 +42,67 @@
+ #include "cpuidle.h"
+ #include "hardware.h"
+
+-static u32 chip_revision;
++static struct flexcan_platform_data flexcan_pdata[2];
++static int flexcan_en_gpio;
++static int flexcan_stby_gpio;
++static int flexcan0_en;
++static int flexcan1_en;
++static void mx6q_flexcan_switch(void)
++{
++ if (flexcan0_en || flexcan1_en) {
++ /*
++ * The transceiver TJA1041A on sabreauto RevE baseboard will
++ * fail to transit to Normal state if EN/STBY is high by default
++ * after board power up. So we set the EN/STBY initial state to low
++ * first then to high to guarantee the state transition successfully.
++ */
++ gpio_set_value_cansleep(flexcan_en_gpio, 0);
++ gpio_set_value_cansleep(flexcan_stby_gpio, 0);
++
++ gpio_set_value_cansleep(flexcan_en_gpio, 1);
++ gpio_set_value_cansleep(flexcan_stby_gpio, 1);
++ } else {
++ /*
++ * avoid to disable CAN xcvr if any of the CAN interfaces
++ * are down. XCRV will be disabled only if both CAN2
++ * interfaces are DOWN.
++ */
++ gpio_set_value_cansleep(flexcan_en_gpio, 0);
++ gpio_set_value_cansleep(flexcan_stby_gpio, 0);
++ }
++}
+
+-int imx6q_revision(void)
++static void imx6q_flexcan0_switch_auto(int enable)
+ {
+- return chip_revision;
++ flexcan0_en = enable;
++ mx6q_flexcan_switch();
+ }
+
+-static void __init imx6q_init_revision(void)
++static void imx6q_flexcan1_switch_auto(int enable)
+ {
+- u32 rev = imx_anatop_get_digprog();
+-
+- switch (rev & 0xff) {
+- case 0:
+- chip_revision = IMX_CHIP_REVISION_1_0;
+- break;
+- case 1:
+- chip_revision = IMX_CHIP_REVISION_1_1;
+- break;
+- case 2:
+- chip_revision = IMX_CHIP_REVISION_1_2;
+- break;
+- default:
+- chip_revision = IMX_CHIP_REVISION_UNKNOWN;
+- }
+-
+- mxc_set_cpu_type(rev >> 16 & 0xff);
++ flexcan1_en = enable;
++ mx6q_flexcan_switch();
+ }
+
+-static void imx6q_restart(char mode, const char *cmd)
++static int __init imx6q_flexcan_fixup_auto(void)
+ {
+ struct device_node *np;
+- void __iomem *wdog_base;
+-
+- np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
+- wdog_base = of_iomap(np, 0);
+- if (!wdog_base)
+- goto soft;
+-
+- imx_src_prepare_restart();
+
+- /* enable wdog */
+- writew_relaxed(1 << 2, wdog_base);
+- /* write twice to ensure the request will not get ignored */
+- writew_relaxed(1 << 2, wdog_base);
+-
+- /* wait for reset to assert ... */
+- mdelay(500);
+-
+- pr_err("Watchdog reset failed to assert reset\n");
+-
+- /* delay to allow the serial port to show the message */
+- mdelay(50);
++ np = of_find_node_by_path("/soc/aips-bus@02000000/can@02090000");
++ if (!np)
++ return -ENODEV;
++
++ flexcan_en_gpio = of_get_named_gpio(np, "trx-en-gpio", 0);
++ flexcan_stby_gpio = of_get_named_gpio(np, "trx-stby-gpio", 0);
++ if (gpio_is_valid(flexcan_en_gpio) && gpio_is_valid(flexcan_stby_gpio) &&
++ !gpio_request_one(flexcan_en_gpio, GPIOF_DIR_OUT, "flexcan-trx-en") &&
++ !gpio_request_one(flexcan_stby_gpio, GPIOF_DIR_OUT, "flexcan-trx-stby")) {
++ /* flexcan 0 & 1 are using the same GPIOs for transceiver */
++ flexcan_pdata[0].transceiver_switch = imx6q_flexcan0_switch_auto;
++ flexcan_pdata[1].transceiver_switch = imx6q_flexcan1_switch_auto;
++ }
+
+-soft:
+- /* we'll take a jump through zero as a poor second */
+- soft_restart(0);
++ return 0;
+ }
+
+ /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
+@@ -113,36 +122,105 @@
+ return 0;
+ }
+
+-static void __init imx6q_sabrelite_cko1_setup(void)
++static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
+ {
+- struct clk *cko1_sel, *ahb, *cko1;
+- unsigned long rate;
++ phy_write(dev, 0x0d, device);
++ phy_write(dev, 0x0e, reg);
++ phy_write(dev, 0x0d, (1 << 14) | device);
++ phy_write(dev, 0x0e, val);
++}
+
+- cko1_sel = clk_get_sys(NULL, "cko1_sel");
+- ahb = clk_get_sys(NULL, "ahb");
+- cko1 = clk_get_sys(NULL, "cko1");
+- if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
+- pr_err("cko1 setup failed!\n");
+- goto put_clk;
+- }
+- clk_set_parent(cko1_sel, ahb);
+- rate = clk_round_rate(cko1, 16000000);
+- clk_set_rate(cko1, rate);
+-put_clk:
+- if (!IS_ERR(cko1_sel))
+- clk_put(cko1_sel);
+- if (!IS_ERR(ahb))
+- clk_put(ahb);
+- if (!IS_ERR(cko1))
+- clk_put(cko1);
++static int ksz9031rn_phy_fixup(struct phy_device *dev)
++{
++ /*
++ * min rx data delay, max rx/tx clock delay,
++ * min rx/tx control delay
++ */
++ mmd_write_reg(dev, 2, 4, 0);
++ mmd_write_reg(dev, 2, 5, 0);
++ mmd_write_reg(dev, 2, 8, 0x003ff);
++
++ return 0;
++}
++
++static int ar8031_phy_fixup(struct phy_device *dev)
++{
++ u16 val;
++
++ /* disable phy AR8031 SmartEEE function. */
++ phy_write(dev, 0xd, 0x3);
++ phy_write(dev, 0xe, 0x805d);
++ phy_write(dev, 0xd, 0x4003);
++ val = phy_read(dev, 0xe);
++ val &= ~(0x1 << 8);
++ phy_write(dev, 0xe, val);
++
++ /* To enable AR8031 output a 125MHz clk from CLK_25M */
++ phy_write(dev, 0xd, 0x7);
++ phy_write(dev, 0xe, 0x8016);
++ phy_write(dev, 0xd, 0x4007);
++
++ val = phy_read(dev, 0xe);
++ val &= 0xffe3;
++ val |= 0x18;
++ phy_write(dev, 0xe, val);
++
++ /* introduce tx clock delay */
++ phy_write(dev, 0x1d, 0x5);
++ val = phy_read(dev, 0x1e);
++ val |= 0x0100;
++ phy_write(dev, 0x1e, val);
++
++ return 0;
+ }
+
+-static void __init imx6q_sabrelite_init(void)
++#define PHY_ID_AR8031 0x004dd074
++
++static int ar8035_phy_fixup(struct phy_device *dev)
+ {
+- if (IS_BUILTIN(CONFIG_PHYLIB))
++ u16 val;
++
++ /* Ar803x phy SmartEEE feature cause link status generates glitch,
++ * which cause ethernet link down/up issue, so disable SmartEEE
++ */
++ phy_write(dev, 0xd, 0x3);
++ phy_write(dev, 0xe, 0x805d);
++ phy_write(dev, 0xd, 0x4003);
++
++ val = phy_read(dev, 0xe);
++ phy_write(dev, 0xe, val & ~(1 << 8));
++
++ /*
++ * Enable 125MHz clock from CLK_25M on the AR8031. This
++ * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
++ * Also, introduce a tx clock delay.
++ *
++ * This is the same as is the AR8031 fixup.
++ */
++ ar8031_phy_fixup(dev);
++
++ /*check phy power*/
++ val = phy_read(dev, 0x0);
++ if (val & BMCR_PDOWN)
++ phy_write(dev, 0x0, val & ~BMCR_PDOWN);
++
++ return 0;
++}
++
++#define PHY_ID_AR8035 0x004dd072
++
++static void __init imx6q_enet_phy_init(void)
++{
++ if (IS_BUILTIN(CONFIG_PHYLIB)) {
+ phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+ ksz9021rn_phy_fixup);
+- imx6q_sabrelite_cko1_setup();
++ phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
++ ksz9031rn_phy_fixup);
++ phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
++ ar8031_phy_fixup);
++ phy_register_fixup_for_uid(PHY_ID_AR8035, 0xffffffef,
++ ar8035_phy_fixup);
++ }
+ }
+
+ static void __init imx6q_1588_init(void)
+@@ -151,34 +229,175 @@
+
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr))
+- regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
++ regmap_update_bits(gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_ENET_CLK_SEL_MASK,
++ IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
+ else
+ pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+
+ }
+-static void __init imx6q_usb_init(void)
++
++static void __init imx6q_csi_mux_init(void)
+ {
+- imx_anatop_usb_chrg_detect_disable();
++ /*
++ * MX6Q SabreSD board:
++ * IPU1 CSI0 connects to parallel interface.
++ * Set GPR1 bit 19 to 0x1.
++ *
++ * MX6DL SabreSD board:
++ * IPU1 CSI0 connects to parallel interface.
++ * Set GPR13 bit 0-2 to 0x4.
++ * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1.
++ * Set GPR13 bit 3-5 to 0x1.
++ */
++ struct regmap *gpr;
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
++ of_machine_is_compatible("fsl,imx6q-sabreauto"))
++ regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19);
++ else if (of_machine_is_compatible("fsl,imx6dl-sabresd") ||
++ of_machine_is_compatible("fsl,imx6dl-sabreauto"))
++ regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C);
++ } else {
++ pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n",
++ __func__);
++ }
+ }
+
++/*
++ * Disable Hannstar LVDS panel CABC function.
++ * This function turns the panel's backlight density automatically
++ * according to the content shown on the panel which may cause
++ * annoying unstable backlight issue.
++ */
++static void __init imx6q_lvds_cabc_init(void)
++{
++ struct device_node *np = NULL;
++ int ret, lvds0_gpio, lvds1_gpio;
++
++ np = of_find_node_by_name(NULL, "lvds_cabc_ctrl");
++ if (!np)
++ return;
++
++ lvds0_gpio = of_get_named_gpio(np, "lvds0-gpios", 0);
++ if (gpio_is_valid(lvds0_gpio)) {
++ ret = gpio_request_one(lvds0_gpio, GPIOF_OUT_INIT_LOW,
++ "LVDS0 CABC enable");
++ if (ret)
++ pr_warn("failed to request LVDS0 CABC gpio\n");
++ }
++
++ lvds1_gpio = of_get_named_gpio(np, "lvds1-gpios", 0);
++ if (gpio_is_valid(lvds1_gpio)) {
++ ret = gpio_request_one(lvds1_gpio, GPIOF_OUT_INIT_LOW,
++ "LVDS1 CABC enable");
++ if (ret)
++ pr_warn("failed to request LVDS1 CABC gpio\n");
++ }
++}
++
++#define OCOTP_MACn(n) (0x00000620 + (n) * 0x10)
++void __init imx6_enet_mac_init(const char *compatible)
++{
++ struct device_node *ocotp_np, *enet_np;
++ void __iomem *base;
++ struct property *newmac;
++ u32 macaddr_low, macaddr_high;
++ u8 *macaddr;
++
++ enet_np = of_find_compatible_node(NULL, NULL, compatible);
++ if (!enet_np)
++ return;
++
++ if (of_get_mac_address(enet_np))
++ goto put_enet_node;
++
++ ocotp_np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
++ if (!ocotp_np) {
++ pr_warn("failed to find ocotp node\n");
++ goto put_enet_node;
++ }
++
++ base = of_iomap(ocotp_np, 0);
++ if (!base) {
++ pr_warn("failed to map ocotp\n");
++ goto put_ocotp_node;
++ }
++
++ macaddr_high = readl_relaxed(base + OCOTP_MACn(0));
++ macaddr_low = readl_relaxed(base + OCOTP_MACn(1));
++
++ newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
++ if (!newmac)
++ goto put_ocotp_node;
++
++ newmac->value = newmac + 1;
++ newmac->length = 6;
++ newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
++ if (!newmac->name) {
++ kfree(newmac);
++ goto put_ocotp_node;
++ }
++
++ macaddr = newmac->value;
++ macaddr[5] = macaddr_high & 0xff;
++ macaddr[4] = (macaddr_high >> 8) & 0xff;
++ macaddr[3] = (macaddr_high >> 16) & 0xff;
++ macaddr[2] = (macaddr_high >> 24) & 0xff;
++ macaddr[1] = macaddr_low & 0xff;
++ macaddr[0] = (macaddr_low >> 8) & 0xff;
++
++ of_update_property(enet_np, newmac);
++
++put_ocotp_node:
++ of_node_put(ocotp_np);
++put_enet_node:
++ of_node_put(enet_np);
++}
++
++static inline void imx6q_enet_init(void)
++{
++ imx6_enet_mac_init("fsl,imx6q-fec");
++ imx6q_enet_phy_init();
++ imx6q_1588_init();
++}
++
++/* Add auxdata to pass platform data */
++static const struct of_dev_auxdata imx6q_auxdata_lookup[] __initconst = {
++ OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02090000, NULL, &flexcan_pdata[0]),
++ OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02094000, NULL, &flexcan_pdata[1]),
++ { /* sentinel */ }
++};
++
+ static void __init imx6q_init_machine(void)
+ {
+- if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
+- imx6q_sabrelite_init();
++ struct device *parent;
++
++ mxc_arch_reset_init_dt();
++ parent = imx_soc_device_init();
++ if (parent == NULL)
++ pr_warn("failed to initialize soc device\n");
+
+- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
++ of_platform_populate(NULL, of_default_bus_match_table,
++ imx6q_auxdata_lookup, parent);
+
++ imx6q_enet_init();
+ imx_anatop_init();
+- imx6q_pm_init();
+- imx6q_usb_init();
+- imx6q_1588_init();
++ imx6_pm_init();
++ imx6q_csi_mux_init();
++ imx6q_lvds_cabc_init();
+ }
+
+ #define OCOTP_CFG3 0x440
+ #define OCOTP_CFG3_SPEED_SHIFT 16
+ #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
++#define OCOTP_CFG3_SPEED_1GHZ 0x2
++#define OCOTP_CFG3_SPEED_850MHZ 0x1
++#define OCOTP_CFG3_SPEED_800MHZ 0x0
+
+-static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
++static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
+ {
+ struct device_node *np;
+ void __iomem *base;
+@@ -196,11 +415,36 @@
+ goto put_node;
+ }
+
++ /*
++ * SPEED_GRADING[1:0] defines the max speed of ARM:
++ * 2b'11: 1200000000Hz; -- i.MX6Q only.
++ * 2b'10: 1000000000Hz;
++ * 2b'01: 850000000Hz; -- i.MX6Q Only, exclusive with 1GHz.
++ * 2b'00: 800000000Hz;
++ * We need to set the max speed of ARM according to fuse map.
++ */
+ val = readl_relaxed(base + OCOTP_CFG3);
+ val >>= OCOTP_CFG3_SPEED_SHIFT;
+- if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
+- if (opp_disable(cpu_dev, 1200000000))
+- pr_warn("failed to disable 1.2 GHz OPP\n");
++ val &= 3;
++ if (cpu_is_imx6q()) {
++ if (!val) {
++ /* fuses not set for IMX_CHIP_REVISION_1_0 */
++ if (imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
++ val = OCOTP_CFG3_SPEED_1GHZ;
++ }
++ if (val < OCOTP_CFG3_SPEED_1P2GHZ)
++ if (opp_disable(cpu_dev, 1200000000))
++ pr_warn("failed to disable 1.2 GHz OPP\n");
++ }
++ if (val < OCOTP_CFG3_SPEED_1GHZ)
++ if (opp_disable(cpu_dev, 996000000))
++ pr_warn("failed to disable 1 GHz OPP\n");
++ if (cpu_is_imx6q()) {
++ if (val < OCOTP_CFG3_SPEED_850MHZ ||
++ val == OCOTP_CFG3_SPEED_1GHZ)
++ if (opp_disable(cpu_dev, 852000000))
++ pr_warn("failed to disable 850 MHz OPP\n");
++ }
+
+ put_node:
+ of_node_put(np);
+@@ -222,41 +466,60 @@
+ goto put_node;
+ }
+
+- imx6q_opp_check_1p2ghz(cpu_dev);
++ imx6q_opp_check_speed_grading(cpu_dev);
+
+ put_node:
+ of_node_put(np);
+ }
+
+ static struct platform_device imx6q_cpufreq_pdev = {
+- .name = "imx6q-cpufreq",
++ .name = "imx6-cpufreq",
+ };
+
+ static void __init imx6q_init_late(void)
+ {
++ struct regmap *gpr;
++
++ /*
++ * Need to force IOMUXC irq pending to meet CCM low power mode
++ * restriction, this is recommended by hardware team.
++ */
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (!IS_ERR(gpr))
++ regmap_update_bits(gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_GINT_MASK,
++ IMX6Q_GPR1_GINT_ASSERT);
++
+ /*
+ * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
+ * to run cpuidle on them.
+ */
+- if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
++ if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
++ || (cpu_is_imx6dl() && imx_get_soc_revision() >
++ IMX_CHIP_REVISION_1_0))
+ imx6q_cpuidle_init();
+
+- if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
++ if (IS_ENABLED(CONFIG_ARM_IMX6_CPUFREQ)) {
+ imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
+ platform_device_register(&imx6q_cpufreq_pdev);
+ }
++
++ if (of_machine_is_compatible("fsl,imx6q-sabreauto")
++ || of_machine_is_compatible("fsl,imx6dl-sabreauto"))
++ imx6q_flexcan_fixup_auto();
+ }
+
+ static void __init imx6q_map_io(void)
+ {
+ debug_ll_io_init();
+ imx_scu_map_io();
++ imx6_pm_map_io();
+ }
+
+ static void __init imx6q_init_irq(void)
+ {
+- imx6q_init_revision();
+- l2x0_of_init(0, ~0UL);
++ imx_init_revision_from_anatop();
++ imx_init_l2cache();
+ imx_src_init();
+ imx_gpc_init();
+ irqchip_init();
+@@ -264,10 +527,10 @@
+
+ static void __init imx6q_timer_init(void)
+ {
+- mx6q_clocks_init();
++ of_clk_init(NULL);
+ clocksource_of_init();
+ imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
+- imx6q_revision());
++ imx_get_soc_revision());
+ }
+
+ static const char *imx6q_dt_compat[] __initdata = {
+@@ -277,6 +540,12 @@
+ };
+
+ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
++ /*
++ * i.MX6Q/DL maps system memory at 0x10000000 (offset 256MiB), and
++ * GPU has a limit on physical address that it accesses, which must
++ * be below 2GiB.
++ */
++ .dma_zone_size = (SZ_2G - SZ_256M),
+ .smp = smp_ops(imx_smp_ops),
+ .map_io = imx6q_map_io,
+ .init_irq = imx6q_init_irq,
+@@ -284,5 +553,5 @@
+ .init_machine = imx6q_init_machine,
+ .init_late = imx6q_init_late,
+ .dt_compat = imx6q_dt_compat,
+- .restart = imx6q_restart,
++ .restart = mxc_restart,
+ MACHINE_END
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mach-imx6sl.c linux-linaro-stable-mx6/arch/arm/mach-imx/mach-imx6sl.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mach-imx6sl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mach-imx6sl.c 2014-05-15 20:33:35.385850852 +0200
+@@ -0,0 +1,149 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/irqchip.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_platform.h>
++#include <linux/opp.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/system_misc.h>
++
++#include "common.h"
++#include "cpuidle.h"
++#include "hardware.h"
++
++static struct platform_device imx6sl_cpufreq_pdev = {
++ .name = "imx6-cpufreq",
++};
++
++static void __init imx6sl_fec_clk_init(void)
++{
++ struct regmap *gpr;
++
++ /* set FEC clock from internal PLL clock source */
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ regmap_update_bits(gpr, IOMUXC_GPR1,
++ IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0);
++ regmap_update_bits(gpr, IOMUXC_GPR1,
++ IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0);
++ } else
++ pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n");
++}
++
++static inline void imx6sl_fec_init(void)
++{
++ imx6sl_fec_clk_init();
++ imx6_enet_mac_init("fsl,imx6sl-fec");
++}
++
++static void __init imx6sl_init_machine(void)
++{
++ struct device *parent;
++
++ mxc_arch_reset_init_dt();
++
++ parent = imx_soc_device_init();
++ if (parent == NULL)
++ pr_warn("failed to initialize soc device\n");
++
++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
++
++ imx6sl_fec_init();
++ imx_anatop_init();
++ imx6_pm_init();
++}
++
++static void __init imx6sl_opp_init(struct device *cpu_dev)
++{
++ struct device_node *np;
++
++ np = of_find_node_by_path("/cpus/cpu@0");
++ if (!np) {
++ pr_warn("failed to find cpu0 node\n");
++ return;
++ }
++
++ cpu_dev->of_node = np;
++ if (of_init_opp_table(cpu_dev)) {
++ pr_warn("failed to init OPP table\n");
++ goto put_node;
++ }
++
++put_node:
++ of_node_put(np);
++}
++
++static void __init imx6sl_init_late(void)
++{
++ struct regmap *gpr;
++
++ /*
++ * Need to force IOMUXC irq pending to meet CCM low power mode
++ * restriction, this is recommended by hardware team.
++ */
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sl-iomuxc-gpr");
++ if (!IS_ERR(gpr))
++ regmap_update_bits(gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_GINT_MASK,
++ IMX6Q_GPR1_GINT_ASSERT);
++ else
++ pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n");
++
++ /* Init CPUIDLE */
++ imx6sl_cpuidle_init();
++
++ if (IS_ENABLED(CONFIG_ARM_IMX6_CPUFREQ)) {
++ imx6sl_opp_init(&imx6sl_cpufreq_pdev.dev);
++ platform_device_register(&imx6sl_cpufreq_pdev);
++ }
++
++}
++
++static void __init imx6sl_map_io(void)
++{
++ debug_ll_io_init();
++ imx6_pm_map_io();
++}
++
++static void __init imx6sl_init_irq(void)
++{
++ imx_init_revision_from_anatop();
++ imx_init_l2cache();
++ imx_src_init();
++ imx_gpc_init();
++ irqchip_init();
++}
++
++static void __init imx6sl_timer_init(void)
++{
++ of_clk_init(NULL);
++}
++
++static const char *imx6sl_dt_compat[] __initdata = {
++ "fsl,imx6sl",
++ NULL,
++};
++
++DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
++ .map_io = imx6sl_map_io,
++ .init_irq = imx6sl_init_irq,
++ .init_time = imx6sl_timer_init,
++ .init_machine = imx6sl_init_machine,
++ .init_late = imx6sl_init_late,
++ .dt_compat = imx6sl_dt_compat,
++ .restart = mxc_restart,
++MACHINE_END
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mach-vf610.c linux-linaro-stable-mx6/arch/arm/mach-imx/mach-vf610.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mach-vf610.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mach-vf610.c 2014-05-15 20:33:35.389850881 +0200
+@@ -0,0 +1,50 @@
++/*
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/of_platform.h>
++#include <linux/clocksource.h>
++#include <linux/irqchip.h>
++#include <linux/clk-provider.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++#include <asm/hardware/cache-l2x0.h>
++
++#include "common.h"
++
++static void __init vf610_init_machine(void)
++{
++ mxc_arch_reset_init_dt();
++ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
++}
++
++static void __init vf610_init_irq(void)
++{
++ l2x0_of_init(0, ~0UL);
++ irqchip_init();
++}
++
++static void __init vf610_init_time(void)
++{
++ of_clk_init(NULL);
++ clocksource_of_init();
++}
++
++static const char *vf610_dt_compat[] __initdata = {
++ "fsl,vf610",
++ NULL,
++};
++
++DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
++ .map_io = debug_ll_io_init,
++ .init_irq = vf610_init_irq,
++ .init_time = vf610_init_time,
++ .init_machine = vf610_init_machine,
++ .dt_compat = vf610_dt_compat,
++ .restart = mxc_restart,
++MACHINE_END
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/Makefile linux-linaro-stable-mx6/arch/arm/mach-imx/Makefile
+--- linux-3.10.30.orig/arch/arm/mach-imx/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/Makefile 2014-05-15 20:33:35.353850621 +0200
+@@ -15,7 +15,8 @@
+ obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
+
+ obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
+- clk-pfd.o clk-busy.o clk.o
++ clk-pfd.o clk-busy.o clk.o \
++ clk-fixup-div.o clk-fixup-mux.o
+
+ obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
+ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
+@@ -30,6 +31,7 @@
+ ifeq ($(CONFIG_CPU_IDLE),y)
+ obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
+ obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
++obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
+ endif
+
+ ifdef CONFIG_SND_IMX_SOC
+@@ -98,11 +100,20 @@
+ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+ obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
++obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
+
+-ifeq ($(CONFIG_PM),y)
+-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
++AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
++obj-$(CONFIG_PM) += pm-imx6.o headsmp.o suspend-imx6.o
++
++ifeq ($(CONFIG_ARM_IMX6_CPUFREQ),y)
++obj-y += busfreq-imx6.o
++obj-$(CONFIG_SOC_IMX6Q) += ddr3_freq_imx6.o busfreq_ddr3.o
++AFLAGS_lpddr2_freq_imx6.o := -march=armv7-a
++AFLAGS_imx6sl_wfi.o := -march=armv7-a
++obj-$(CONFIG_SOC_IMX6SL) += lpddr2_freq_imx6.o busfreq_lpddr2.o imx6sl_wfi.o
+ endif
+
++
+ # i.MX5 based machines
+ obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
+ obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
+@@ -111,4 +122,6 @@
+ obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
+ obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
+
++obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
++
+ obj-y += devices/
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mm-imx1.c linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx1.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mm-imx1.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx1.c 2014-05-15 20:33:35.389850881 +0200
+@@ -39,7 +39,6 @@
+ void __init imx1_init_early(void)
+ {
+ mxc_set_cpu_type(MXC_CPU_MX1);
+- mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
+ imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+ MX1_NUM_GPIO_PORT);
+ }
+@@ -51,6 +50,7 @@
+
+ void __init imx1_soc_init(void)
+ {
++ mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
+ mxc_device_init();
+
+ mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mm-imx21.c linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx21.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mm-imx21.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx21.c 2014-05-15 20:33:35.389850881 +0200
+@@ -66,7 +66,6 @@
+ void __init imx21_init_early(void)
+ {
+ mxc_set_cpu_type(MXC_CPU_MX21);
+- mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
+ imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
+ MX21_NUM_GPIO_PORT);
+ }
+@@ -82,6 +81,7 @@
+
+ void __init imx21_soc_init(void)
+ {
++ mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
+ mxc_device_init();
+
+ mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mm-imx25.c linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx25.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mm-imx25.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx25.c 2014-05-15 20:33:35.389850881 +0200
+@@ -54,7 +54,6 @@
+ {
+ mxc_set_cpu_type(MXC_CPU_MX25);
+ mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
+- mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
+ }
+
+ void __init mx25_init_irq(void)
+@@ -89,6 +88,7 @@
+
+ void __init imx25_soc_init(void)
+ {
++ mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
+ mxc_device_init();
+
+ /* i.mx25 has the i.mx35 type gpio */
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mm-imx27.c linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx27.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mm-imx27.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx27.c 2014-05-15 20:33:35.389850881 +0200
+@@ -66,7 +66,6 @@
+ void __init imx27_init_early(void)
+ {
+ mxc_set_cpu_type(MXC_CPU_MX27);
+- mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
+ imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
+ MX27_NUM_GPIO_PORT);
+ }
+@@ -82,6 +81,7 @@
+
+ void __init imx27_soc_init(void)
+ {
++ mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
+ mxc_device_init();
+
+ /* i.mx27 has the i.mx21 type gpio */
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mm-imx3.c linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx3.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mm-imx3.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx3.c 2014-05-15 20:33:35.389850881 +0200
+@@ -138,7 +138,6 @@
+ void __init imx31_init_early(void)
+ {
+ mxc_set_cpu_type(MXC_CPU_MX31);
+- mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+ arch_ioremap_caller = imx3_ioremap_caller;
+ arm_pm_idle = imx3_idle;
+ mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
+@@ -174,6 +173,7 @@
+
+ imx3_init_l2x0();
+
++ mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+ mxc_device_init();
+
+ mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
+@@ -216,7 +216,6 @@
+ {
+ mxc_set_cpu_type(MXC_CPU_MX35);
+ mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
+- mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+ arm_pm_idle = imx3_idle;
+ arch_ioremap_caller = imx3_ioremap_caller;
+ mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
+@@ -272,6 +271,7 @@
+
+ imx3_init_l2x0();
+
++ mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+ mxc_device_init();
+
+ mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mm-imx5.c linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx5.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/mm-imx5.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mm-imx5.c 2014-05-15 20:33:35.389850881 +0200
+@@ -83,7 +83,6 @@
+ imx51_ipu_mipi_setup();
+ mxc_set_cpu_type(MXC_CPU_MX51);
+ mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
+- mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+ imx_src_init();
+ }
+
+@@ -91,7 +90,6 @@
+ {
+ mxc_set_cpu_type(MXC_CPU_MX53);
+ mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
+- mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
+ imx_src_init();
+ }
+
+@@ -129,6 +127,7 @@
+
+ void __init imx51_soc_init(void)
+ {
++ mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+ mxc_device_init();
+
+ /* i.mx51 has the i.mx35 type gpio */
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mx6.h linux-linaro-stable-mx6/arch/arm/mach-imx/mx6.h
+--- linux-3.10.30.orig/arch/arm/mach-imx/mx6.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mx6.h 2014-05-15 20:33:35.397850939 +0200
+@@ -0,0 +1,35 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_MXC_IOMAP_H__
++#define __ASM_ARCH_MXC_IOMAP_H__
++
++#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
++#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
++
++#define MX6Q_L2_BASE_ADDR 0x00a02000
++#define MX6Q_L2_SIZE 0x1000
++#define MX6Q_IOMUXC_BASE_ADDR 0x020e0000
++#define MX6Q_IOMUXC_SIZE 0x4000
++#define MX6Q_SRC_BASE_ADDR 0x020d8000
++#define MX6Q_SRC_SIZE 0x4000
++#define MX6Q_CCM_BASE_ADDR 0x020c4000
++#define MX6Q_CCM_SIZE 0x4000
++#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
++#define MX6Q_ANATOP_SIZE 0x1000
++#define MX6Q_GPC_BASE_ADDR 0x020dc000
++#define MX6Q_GPC_SIZE 0x4000
++#define MX6Q_MMDC_P0_BASE_ADDR 0x021b0000
++#define MX6Q_MMDC_P0_SIZE 0x4000
++#define MX6Q_MMDC_P1_BASE_ADDR 0x021b4000
++#define MX6Q_MMDC_P1_SIZE 0x4000
++
++#define MX6_SUSPEND_IRAM_SIZE 0x1000
++#endif
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/mxc.h linux-linaro-stable-mx6/arch/arm/mach-imx/mxc.h
+--- linux-3.10.30.orig/arch/arm/mach-imx/mxc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/mxc.h 2014-05-15 20:33:35.397850939 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2004-2007, 2010 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2007, 2010, 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+@@ -34,6 +34,7 @@
+ #define MXC_CPU_MX35 35
+ #define MXC_CPU_MX51 51
+ #define MXC_CPU_MX53 53
++#define MXC_CPU_IMX6SL 0x60
+ #define MXC_CPU_IMX6DL 0x61
+ #define MXC_CPU_IMX6Q 0x63
+
+@@ -41,6 +42,8 @@
+ #define IMX_CHIP_REVISION_1_1 0x11
+ #define IMX_CHIP_REVISION_1_2 0x12
+ #define IMX_CHIP_REVISION_1_3 0x13
++#define IMX_CHIP_REVISION_1_4 0x14
++#define IMX_CHIP_REVISION_1_5 0x15
+ #define IMX_CHIP_REVISION_2_0 0x20
+ #define IMX_CHIP_REVISION_2_1 0x21
+ #define IMX_CHIP_REVISION_2_2 0x22
+@@ -152,6 +155,11 @@
+ #endif
+
+ #ifndef __ASSEMBLY__
++static inline bool cpu_is_imx6sl(void)
++{
++ return __mxc_cpu_type == MXC_CPU_IMX6SL;
++}
++
+ static inline bool cpu_is_imx6dl(void)
+ {
+ return __mxc_cpu_type == MXC_CPU_IMX6DL;
+@@ -171,6 +179,7 @@
+ extern struct cpu_op *(*get_cpu_op)(int *op);
+ #endif
+
++#define cpu_is_imx6() (cpu_is_imx6q() || cpu_is_imx6dl() || cpu_is_imx6sl())
+ #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
+ #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
+
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/pm-imx6.c linux-linaro-stable-mx6/arch/arm/mach-imx/pm-imx6.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/pm-imx6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/pm-imx6.c 2014-05-15 20:33:35.397850939 +0200
+@@ -0,0 +1,379 @@
++/*
++ * Copyright 2011-2013 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_irq.h>
++#include <linux/suspend.h>
++#include <linux/genalloc.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/proc-fns.h>
++#include <asm/suspend.h>
++#include <asm/tlb.h>
++#include <asm/hardware/cache-l2x0.h>
++#include <asm/mach/map.h>
++
++#include "common.h"
++#include "hardware.h"
++
++#define CCR 0x0
++#define BM_CCR_WB_COUNT (0x7 << 16)
++#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
++#define BM_CCR_RBC_EN (0x1 << 27)
++
++#define CLPCR 0x54
++#define BP_CLPCR_LPM 0
++#define BM_CLPCR_LPM (0x3 << 0)
++#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
++#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
++#define BM_CLPCR_SBYOS (0x1 << 6)
++#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
++#define BM_CLPCR_VSTBY (0x1 << 8)
++#define BP_CLPCR_STBY_COUNT 9
++#define BM_CLPCR_STBY_COUNT (0x3 << 9)
++#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
++#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
++#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
++#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
++#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
++#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
++#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
++#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
++#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
++#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
++#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
++
++#define CGPR 0x64
++#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
++
++#define MX6_INT_IOMUXC 32
++
++static struct gen_pool *iram_pool;
++static void *suspend_iram_base;
++static unsigned long iram_size, iram_paddr;
++static int (*suspend_in_iram_fn)(void *iram_vbase,
++ unsigned long iram_pbase, unsigned int cpu_type);
++static unsigned int cpu_type;
++static void __iomem *ccm_base;
++
++void imx6_set_cache_lpm_in_wait(bool enable)
++{
++ if ((cpu_is_imx6q() && imx_get_soc_revision() >
++ IMX_CHIP_REVISION_1_1) ||
++ (cpu_is_imx6dl() && imx_get_soc_revision() >
++ IMX_CHIP_REVISION_1_0)) {
++ u32 val;
++
++ val = readl_relaxed(ccm_base + CGPR);
++ if (enable)
++ val |= BM_CGPR_INT_MEM_CLK_LPM;
++ else
++ val &= ~BM_CGPR_INT_MEM_CLK_LPM;
++ writel_relaxed(val, ccm_base + CGPR);
++ }
++}
++
++static void imx6_enable_rbc(bool enable)
++{
++ u32 val;
++
++ /*
++ * need to mask all interrupts in GPC before
++ * operating RBC configurations
++ */
++ imx_gpc_mask_all();
++
++ /* configure RBC enable bit */
++ val = readl_relaxed(ccm_base + CCR);
++ val &= ~BM_CCR_RBC_EN;
++ val |= enable ? BM_CCR_RBC_EN : 0;
++ writel_relaxed(val, ccm_base + CCR);
++
++ /* configure RBC count */
++ val = readl_relaxed(ccm_base + CCR);
++ val &= ~BM_CCR_RBC_BYPASS_COUNT;
++ val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
++ writel(val, ccm_base + CCR);
++
++ /*
++ * need to delay at least 2 cycles of CKIL(32K)
++ * due to hardware design requirement, which is
++ * ~61us, here we use 65us for safe
++ */
++ udelay(65);
++
++ /* restore GPC interrupt mask settings */
++ imx_gpc_restore_all();
++}
++
++static void imx6_enable_wb(bool enable)
++{
++ u32 val;
++
++ /* configure well bias enable bit */
++ val = readl_relaxed(ccm_base + CLPCR);
++ val &= ~BM_CLPCR_WB_PER_AT_LPM;
++ val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
++ writel_relaxed(val, ccm_base + CLPCR);
++
++ /* configure well bias count */
++ val = readl_relaxed(ccm_base + CCR);
++ val &= ~BM_CCR_WB_COUNT;
++ val |= enable ? BM_CCR_WB_COUNT : 0;
++ writel_relaxed(val, ccm_base + CCR);
++}
++
++int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
++{
++ u32 val = readl_relaxed(ccm_base + CLPCR);
++ struct irq_desc *desc = irq_to_desc(MX6_INT_IOMUXC);
++
++ /*
++ * CCM state machine has restriction, before enabling
++ * LPM mode, need to make sure last LPM mode is waked up
++ * by dsm_wakeup_signal, which means the wakeup source
++ * must be seen by GPC, then CCM will clean its state machine
++ * and re-sample necessary signal to decide whether it can
++ * enter LPM mode. We force irq #32 to be always pending,
++ * unmask it before we enable LPM mode and mask it after LPM
++ * is enabled, this flow will make sure CCM state machine in
++ * reliable status before entering LPM mode. Otherwise, CCM
++ * may enter LPM mode by mistake which will cause system bus
++ * locked by CPU access not finished, as when CCM enter
++ * LPM mode, CPU will stop running.
++ */
++ imx_gpc_irq_unmask(&desc->irq_data);
++
++ val &= ~BM_CLPCR_LPM;
++ switch (mode) {
++ case WAIT_CLOCKED:
++ break;
++ case WAIT_UNCLOCKED:
++ val |= 0x1 << BP_CLPCR_LPM;
++ val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
++ val &= ~BM_CLPCR_VSTBY;
++ val &= ~BM_CLPCR_SBYOS;
++ if (cpu_is_imx6sl())
++ val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
++ else
++ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
++ break;
++ case STOP_POWER_ON:
++ val |= 0x2 << BP_CLPCR_LPM;
++ val &= ~BM_CLPCR_VSTBY;
++ val &= ~BM_CLPCR_SBYOS;
++ if (cpu_is_imx6sl()) {
++ val |= BM_CLPCR_BYPASS_PMIC_READY;
++ val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
++ } else {
++ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
++ }
++ break;
++ case WAIT_UNCLOCKED_POWER_OFF:
++ val |= 0x1 << BP_CLPCR_LPM;
++ val &= ~BM_CLPCR_VSTBY;
++ val &= ~BM_CLPCR_SBYOS;
++ break;
++ case STOP_POWER_OFF:
++ val |= 0x2 << BP_CLPCR_LPM;
++ val |= 0x3 << BP_CLPCR_STBY_COUNT;
++ val |= BM_CLPCR_VSTBY;
++ val |= BM_CLPCR_SBYOS;
++ if (cpu_is_imx6sl()) {
++ val |= BM_CLPCR_BYPASS_PMIC_READY;
++ val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
++ } else {
++ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
++ }
++ break;
++ default:
++ imx_gpc_irq_mask(&desc->irq_data);
++ return -EINVAL;
++ }
++
++ writel_relaxed(val, ccm_base + CLPCR);
++ imx_gpc_irq_mask(&desc->irq_data);
++
++ return 0;
++}
++
++static int imx6_suspend_finish(unsigned long val)
++{
++ /*
++ * call low level suspend function in iram,
++ * as we need to float DDR IO.
++ */
++ local_flush_tlb_all();
++ suspend_in_iram_fn(suspend_iram_base, iram_paddr, cpu_type);
++ return 0;
++}
++
++static int imx6_pm_enter(suspend_state_t state)
++{
++ struct regmap *g;
++
++ /*
++ * L2 can exit by 'reset' or Inband beacon (from remote EP)
++ * toggling phy_powerdown has same effect as 'inband beacon'
++ * So, toggle bit18 of GPR1, used as a workaround of errata
++ * "PCIe PCIe does not support L2 Power Down"
++ */
++ if (IS_ENABLED(CONFIG_PCI_IMX6)) {
++ g = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (IS_ERR(g)) {
++ pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
++ return PTR_ERR(g);
++ }
++ regmap_update_bits(g, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
++ IMX6Q_GPR1_PCIE_TEST_PD);
++ }
++
++ switch (state) {
++ case PM_SUSPEND_STANDBY:
++ imx6_set_lpm(STOP_POWER_ON);
++ imx6_set_cache_lpm_in_wait(true);
++ imx_gpc_pre_suspend(false);
++ if (cpu_is_imx6sl())
++ imx6sl_set_wait_clk(true);
++ /* Zzz ... */
++ cpu_do_idle();
++ if (cpu_is_imx6sl())
++ imx6sl_set_wait_clk(false);
++ imx_gpc_post_resume();
++ imx6_set_lpm(WAIT_CLOCKED);
++ break;
++ case PM_SUSPEND_MEM:
++ imx6_enable_wb(true);
++ imx6_set_cache_lpm_in_wait(false);
++ imx6_set_lpm(STOP_POWER_OFF);
++ imx_gpc_pre_suspend(true);
++ imx_anatop_pre_suspend();
++ imx_set_cpu_jump(0, v7_cpu_resume);
++ /* Zzz ... */
++ cpu_suspend(0, imx6_suspend_finish);
++ if (!cpu_is_imx6sl())
++ imx_smp_prepare();
++ imx_anatop_post_resume();
++ imx_gpc_post_resume();
++ imx6_enable_rbc(false);
++ imx6_enable_wb(false);
++ imx6_set_cache_lpm_in_wait(true);
++ imx6_set_lpm(WAIT_CLOCKED);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /*
++ * L2 can exit by 'reset' or Inband beacon (from remote EP)
++ * toggling phy_powerdown has same effect as 'inband beacon'
++ * So, toggle bit18 of GPR1, used as a workaround of errata
++ * "PCIe PCIe does not support L2 Power Down"
++ */
++ if (IS_ENABLED(CONFIG_PCI_IMX6)) {
++ regmap_update_bits(g, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD,
++ !IMX6Q_GPR1_PCIE_TEST_PD);
++ }
++
++ return 0;
++}
++
++static struct map_desc imx6_pm_io_desc[] __initdata = {
++ imx_map_entry(MX6Q, MMDC_P0, MT_DEVICE),
++ imx_map_entry(MX6Q, MMDC_P1, MT_DEVICE),
++ imx_map_entry(MX6Q, SRC, MT_DEVICE),
++ imx_map_entry(MX6Q, IOMUXC, MT_DEVICE),
++ imx_map_entry(MX6Q, CCM, MT_DEVICE),
++ imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
++ imx_map_entry(MX6Q, GPC, MT_DEVICE),
++ imx_map_entry(MX6Q, L2, MT_DEVICE),
++};
++
++void __init imx6_pm_map_io(void)
++{
++ iotable_init(imx6_pm_io_desc, ARRAY_SIZE(imx6_pm_io_desc));
++}
++
++static int imx6_pm_valid(suspend_state_t state)
++{
++ return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
++}
++
++static const struct platform_suspend_ops imx6_pm_ops = {
++ .enter = imx6_pm_enter,
++ .valid = imx6_pm_valid,
++};
++
++void imx6_pm_set_ccm_base(void __iomem *base)
++{
++ if (!base)
++ pr_warn("ccm base is NULL!\n");
++ ccm_base = base;
++}
++
++void __init imx6_pm_init(void)
++{
++ struct device_node *node;
++ unsigned long iram_base;
++ struct platform_device *pdev;
++
++ node = of_find_compatible_node(NULL, NULL, "mmio-sram");
++ if (!node) {
++ pr_err("failed to find ocram node!\n");
++ return;
++ }
++
++ pdev = of_find_device_by_node(node);
++ if (!pdev) {
++ pr_err("failed to find ocram device!\n");
++ return;
++ }
++
++ iram_pool = dev_get_gen_pool(&pdev->dev);
++ if (!iram_pool) {
++ pr_err("iram pool unavailable!\n");
++ return;
++ }
++
++ iram_size = MX6_SUSPEND_IRAM_SIZE;
++
++ iram_base = gen_pool_alloc(iram_pool, iram_size);
++ if (!iram_base) {
++ pr_err("unable to alloc iram!\n");
++ return;
++ }
++
++ iram_paddr = gen_pool_virt_to_phys(iram_pool, iram_base);
++
++ suspend_iram_base = __arm_ioremap(iram_paddr, iram_size,
++ MT_MEMORY_NONCACHED);
++
++ suspend_in_iram_fn = (void *)fncpy(suspend_iram_base,
++ &imx6_suspend, iram_size);
++
++ suspend_set_ops(&imx6_pm_ops);
++
++ /* Set cpu_type for DSM */
++ if (cpu_is_imx6q())
++ cpu_type = MXC_CPU_IMX6Q;
++ else if (cpu_is_imx6dl())
++ cpu_type = MXC_CPU_IMX6DL;
++ else
++ cpu_type = MXC_CPU_IMX6SL;
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/pm-imx6q.c linux-linaro-stable-mx6/arch/arm/mach-imx/pm-imx6q.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/pm-imx6q.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/pm-imx6q.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,61 +0,0 @@
+-/*
+- * Copyright 2011-2013 Freescale Semiconductor, Inc.
+- * Copyright 2011 Linaro Ltd.
+- *
+- * The code contained herein is licensed under the GNU General Public
+- * License. You may obtain a copy of the GNU General Public License
+- * Version 2 or later at the following locations:
+- *
+- * http://www.opensource.org/licenses/gpl-license.html
+- * http://www.gnu.org/copyleft/gpl.html
+- */
+-
+-#include <linux/init.h>
+-#include <linux/io.h>
+-#include <linux/of.h>
+-#include <linux/suspend.h>
+-#include <asm/cacheflush.h>
+-#include <asm/proc-fns.h>
+-#include <asm/suspend.h>
+-#include <asm/hardware/cache-l2x0.h>
+-
+-#include "common.h"
+-#include "hardware.h"
+-
+-static int imx6q_suspend_finish(unsigned long val)
+-{
+- cpu_do_idle();
+- return 0;
+-}
+-
+-static int imx6q_pm_enter(suspend_state_t state)
+-{
+- switch (state) {
+- case PM_SUSPEND_MEM:
+- imx6q_set_lpm(STOP_POWER_OFF);
+- imx_gpc_pre_suspend();
+- imx_anatop_pre_suspend();
+- imx_set_cpu_jump(0, v7_cpu_resume);
+- /* Zzz ... */
+- cpu_suspend(0, imx6q_suspend_finish);
+- imx_smp_prepare();
+- imx_anatop_post_resume();
+- imx_gpc_post_resume();
+- imx6q_set_lpm(WAIT_CLOCKED);
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- return 0;
+-}
+-
+-static const struct platform_suspend_ops imx6q_pm_ops = {
+- .enter = imx6q_pm_enter,
+- .valid = suspend_valid_only_mem,
+-};
+-
+-void __init imx6q_pm_init(void)
+-{
+- suspend_set_ops(&imx6q_pm_ops);
+-}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/src.c linux-linaro-stable-mx6/arch/arm/mach-imx/src.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/src.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/src.c 2014-05-15 20:33:35.397850939 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011, 2013 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -91,6 +91,7 @@
+ spin_lock(&scr_lock);
+ val = readl_relaxed(src_base + SRC_SCR);
+ val = enable ? val | mask : val & ~mask;
++ val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
+ writel_relaxed(val, src_base + SRC_SCR);
+ spin_unlock(&scr_lock);
+ }
+@@ -114,21 +115,6 @@
+ writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
+ }
+
+-void imx_src_prepare_restart(void)
+-{
+- u32 val;
+-
+- /* clear enable bits of secondary cores */
+- spin_lock(&scr_lock);
+- val = readl_relaxed(src_base + SRC_SCR);
+- val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
+- writel_relaxed(val, src_base + SRC_SCR);
+- spin_unlock(&scr_lock);
+-
+- /* clear persistent entry register of primary core */
+- writel_relaxed(0, src_base + SRC_GPR1);
+-}
+-
+ void __init imx_src_init(void)
+ {
+ struct device_node *np;
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/suspend-imx6.S linux-linaro-stable-mx6/arch/arm/mach-imx/suspend-imx6.S
+--- linux-3.10.30.orig/arch/arm/mach-imx/suspend-imx6.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/suspend-imx6.S 2014-05-15 20:33:35.397850939 +0200
+@@ -0,0 +1,801 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/linkage.h>
++#include <asm/hardware/cache-l2x0.h>
++#include "hardware.h"
++
++#define MX6Q_SRC_GPR1 0x20
++#define MX6Q_SRC_GPR2 0x24
++#define MX6Q_MMDC_MAPSR 0x404
++#define MX6Q_MMDC_MPDGCTRL0 0x83c
++#define MX6Q_GPC_IMR1 0x08
++#define MX6Q_GPC_IMR2 0x0c
++#define MX6Q_GPC_IMR3 0x10
++#define MX6Q_GPC_IMR4 0x14
++#define MX6Q_CCM_CCR 0x0
++#define MX6Q_ANATOP_CORE 0x140
++
++ .align 3
++
++ .macro imx6sl_ddr_io_save
++
++ ldr r4, [r8, #0x30c] /* DRAM_DQM0 */
++ ldr r5, [r8, #0x310] /* DRAM_DQM1 */
++ ldr r6, [r8, #0x314] /* DRAM_DQM2 */
++ ldr r7, [r8, #0x318] /* DRAM_DQM3 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x5c4] /* GPR_B0DS */
++ ldr r5, [r8, #0x5cc] /* GPR_B1DS */
++ ldr r6, [r8, #0x5d4] /* GPR_B2DS */
++ ldr r7, [r8, #0x5d8] /* GPR_B3DS */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x300] /* DRAM_CAS */
++ ldr r5, [r8, #0x31c] /* DRAM_RAS */
++ ldr r6, [r8, #0x338] /* DRAM_SDCLK_0 */
++ ldr r7, [r8, #0x5ac] /* GPR_ADDS*/
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x5b0] /* DDRMODE_CTL */
++ ldr r5, [r8, #0x5c0] /* DDRMODE */
++ ldr r6, [r8, #0x33c] /* DRAM_SODT0*/
++ ldr r7, [r8, #0x340] /* DRAM_SODT1*/
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x330] /* DRAM_SDCKE0 */
++ ldr r5, [r8, #0x334] /* DRAM_SDCKE1 */
++ ldr r6, [r8, #0x320] /* DRAM_RESET */
++ stmfd r10!, {r4-r6}
++
++ .endm
++
++ .macro imx6sl_ddr_io_restore
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x30c] /* DRAM_DQM0 */
++ str r5, [r8, #0x310] /* DRAM_DQM1 */
++ str r6, [r8, #0x314] /* DRAM_DQM2 */
++ str r7, [r8, #0x318] /* DRAM_DQM3 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x5c4] /* GPR_B0DS */
++ str r5, [r8, #0x5cc] /* GPR_B1DS */
++ str r6, [r8, #0x5d4] /* GPR_B2DS */
++ str r7, [r8, #0x5d8] /* GPR_B3DS */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x300] /* DRAM_CAS */
++ str r5, [r8, #0x31c] /* DRAM_RAS */
++ str r6, [r8, #0x338] /* DRAM_SDCLK_0 */
++ str r7, [r8, #0x5ac] /* GPR_ADDS*/
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x5b0] /* DDRMODE_CTL */
++ str r5, [r8, #0x5c0] /* DDRMODE */
++ str r6, [r8, #0x33c] /* DRAM_SODT0*/
++ str r7, [r8, #0x340] /* DRAM_SODT1*/
++
++ ldmea r10!, {r4-r6}
++ str r4, [r8, #0x330] /* DRAM_SDCKE0 */
++ str r5, [r8, #0x334] /* DRAM_SDCKE1 */
++ str r6, [r8, #0x320] /* DRAM_RESET */
++
++ .endm
++
++ .macro imx6sl_ddr_io_set_lpm
++
++ mov r10, #0
++ str r10, [r8, #0x30c] /* DRAM_DQM0 */
++ str r10, [r8, #0x310] /* DRAM_DQM1 */
++ str r10, [r8, #0x314] /* DRAM_DQM2 */
++ str r10, [r8, #0x318] /* DRAM_DQM3 */
++
++ str r10, [r8, #0x5c4] /* GPR_B0DS */
++ str r10, [r8, #0x5cc] /* GPR_B1DS */
++ str r10, [r8, #0x5d4] /* GPR_B2DS */
++ str r10, [r8, #0x5d8] /* GPR_B3DS */
++
++ str r10, [r8, #0x300] /* DRAM_CAS */
++ str r10, [r8, #0x31c] /* DRAM_RAS */
++ str r10, [r8, #0x338] /* DRAM_SDCLK_0 */
++ str r10, [r8, #0x5ac] /* GPR_ADDS*/
++
++ str r10, [r8, #0x5b0] /* DDRMODE_CTL */
++ str r10, [r8, #0x5c0] /* DDRMODE */
++ str r10, [r8, #0x33c] /* DRAM_SODT0*/
++ str r10, [r8, #0x340] /* DRAM_SODT1*/
++
++ mov r10, #0x80000
++ str r10, [r8, #0x320] /* DRAM_RESET */
++ mov r10, #0x1000
++ str r10, [r8, #0x330] /* DRAM_SDCKE0 */
++ str r10, [r8, #0x334] /* DRAM_SDCKE1 */
++
++ .endm
++
++ .macro imx6dl_ddr_io_save
++
++ ldr r4, [r8, #0x470] /* DRAM_DQM0 */
++ ldr r5, [r8, #0x474] /* DRAM_DQM1 */
++ ldr r6, [r8, #0x478] /* DRAM_DQM2 */
++ ldr r7, [r8, #0x47c] /* DRAM_DQM3 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x480] /* DRAM_DQM4 */
++ ldr r5, [r8, #0x484] /* DRAM_DQM5 */
++ ldr r6, [r8, #0x488] /* DRAM_DQM6 */
++ ldr r7, [r8, #0x48c] /* DRAM_DQM7 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x464] /* DRAM_CAS */
++ ldr r5, [r8, #0x490] /* DRAM_RAS */
++ ldr r6, [r8, #0x4ac] /* DRAM_SDCLK_0 */
++ ldr r7, [r8, #0x4b0] /* DRAM_SDCLK_1 */
++ stmfd r10!, {r4-r7}
++
++ ldr r5, [r8, #0x750] /* DDRMODE_CTL */
++ ldr r6, [r8, #0x760] /* DDRMODE */
++ stmfd r10!, {r5-r6}
++
++ ldr r4, [r8, #0x4bc] /* DRAM_SDQS0 */
++ ldr r5, [r8, #0x4c0] /* DRAM_SDQS1 */
++ ldr r6, [r8, #0x4c4] /* DRAM_SDQS2 */
++ ldr r7, [r8, #0x4c8] /* DRAM_SDQS3 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x4cc] /* DRAM_SDQS4 */
++ ldr r5, [r8, #0x4d0] /* DRAM_SDQS5 */
++ ldr r6, [r8, #0x4d4] /* DRAM_SDQS6 */
++ ldr r7, [r8, #0x4d8] /* DRAM_SDQS7 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x764] /* GPR_B0DS */
++ ldr r5, [r8, #0x770] /* GPR_B1DS */
++ ldr r6, [r8, #0x778] /* GPR_B2DS */
++ ldr r7, [r8, #0x77c] /* GPR_B3DS */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x780] /* GPR_B4DS */
++ ldr r5, [r8, #0x784] /* GPR_B5DS */
++ ldr r6, [r8, #0x78c] /* GPR_B6DS */
++ ldr r7, [r8, #0x748] /* GPR_B7DS */
++ stmfd r10!, {r4-r7}
++
++ ldr r5, [r8, #0x74c] /* GPR_ADDS*/
++ ldr r6, [r8, #0x4b4] /* DRAM_SODT0*/
++ ldr r7, [r8, #0x4b8] /* DRAM_SODT1*/
++ stmfd r10!, {r5-r7}
++
++ .endm
++
++ .macro imx6dl_ddr_io_restore
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x470] /* DRAM_DQM0 */
++ str r5, [r8, #0x474] /* DRAM_DQM1 */
++ str r6, [r8, #0x478] /* DRAM_DQM2 */
++ str r7, [r8, #0x47c] /* DRAM_DQM3 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x480] /* DRAM_DQM4 */
++ str r5, [r8, #0x484] /* DRAM_DQM5 */
++ str r6, [r8, #0x488] /* DRAM_DQM6 */
++ str r7, [r8, #0x48c] /* DRAM_DQM7 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x464] /* DRAM_CAS */
++ str r5, [r8, #0x490] /* DRAM_RAS */
++ str r6, [r8, #0x4ac] /* DRAM_SDCLK_0 */
++ str r7, [r8, #0x4b0] /* DRAM_SDCLK_1 */
++
++ ldmea r10!, {r5-r6}
++ str r5, [r8, #0x750] /* DDRMODE_CTL */
++ str r6, [r8, #0x760] /* DDRMODE */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x4bc] /* DRAM_SDQS0 */
++ str r5, [r8, #0x4c0] /* DRAM_SDQS1 */
++ str r6, [r8, #0x4c4] /* DRAM_SDQS2 */
++ str r7, [r8, #0x4c8] /* DRAM_SDQS3 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x4cc] /* DRAM_SDQS4 */
++ str r5, [r8, #0x4d0] /* DRAM_SDQS5 */
++ str r6, [r8, #0x4d4] /* DRAM_SDQS6 */
++ str r7, [r8, #0x4d8] /* DRAM_SDQS7 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x764] /* GPR_B0DS */
++ str r5, [r8, #0x770] /* GPR_B1DS */
++ str r6, [r8, #0x778] /* GPR_B2DS */
++ str r7, [r8, #0x77c] /* GPR_B3DS */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x780] /* GPR_B4DS */
++ str r5, [r8, #0x784] /* GPR_B5DS */
++ str r6, [r8, #0x78c] /* GPR_B6DS */
++ str r7, [r8, #0x748] /* GPR_B7DS */
++
++ ldmea r10!, {r5-r7}
++ str r5, [r8, #0x74c] /* GPR_ADDS*/
++ str r6, [r8, #0x4b4] /* DRAM_SODT0*/
++ str r7, [r8, #0x4b8] /* DRAM_SODT1*/
++
++ .endm
++
++ .macro imx6dl_ddr_io_set_lpm
++
++ mov r10, #0
++ str r10, [r8, #0x470] /* DRAM_DQM0 */
++ str r10, [r8, #0x474] /* DRAM_DQM1 */
++ str r10, [r8, #0x478] /* DRAM_DQM2 */
++ str r10, [r8, #0x47c] /* DRAM_DQM3 */
++
++ str r10, [r8, #0x480] /* DRAM_DQM4 */
++ str r10, [r8, #0x484] /* DRAM_DQM5 */
++ str r10, [r8, #0x488] /* DRAM_DQM6 */
++ str r10, [r8, #0x48c] /* DRAM_DQM7 */
++
++ str r10, [r8, #0x464] /* DRAM_CAS */
++ str r10, [r8, #0x490] /* DRAM_RAS */
++ str r10, [r8, #0x4ac] /* DRAM_SDCLK_0 */
++ str r10, [r8, #0x4b0] /* DRAM_SDCLK_1 */
++
++ str r10, [r8, #0x750] /* DDRMODE_CTL */
++ str r10, [r8, #0x760] /* DDRMODE */
++
++ str r10, [r8, #0x4bc] /* DRAM_SDQS0 */
++ str r10, [r8, #0x4c0] /* DRAM_SDQS1 */
++ str r10, [r8, #0x4c4] /* DRAM_SDQS2 */
++ str r10, [r8, #0x4c8] /* DRAM_SDQS3 */
++
++ str r10, [r8, #0x4cc] /* DRAM_SDQS4 */
++ str r10, [r8, #0x4d0] /* DRAM_SDQS5 */
++ str r10, [r8, #0x4d4] /* DRAM_SDQS6 */
++ str r10, [r8, #0x4d8] /* DRAM_SDQS7 */
++
++ str r10, [r8, #0x764] /* GPR_B0DS */
++ str r10, [r8, #0x770] /* GPR_B1DS */
++ str r10, [r8, #0x778] /* GPR_B2DS */
++ str r10, [r8, #0x77c] /* GPR_B3DS */
++
++ str r10, [r8, #0x780] /* GPR_B4DS */
++ str r10, [r8, #0x784] /* GPR_B5DS */
++ str r10, [r8, #0x78c] /* GPR_B6DS */
++ str r10, [r8, #0x748] /* GPR_B7DS */
++
++ str r10, [r8, #0x74c] /* GPR_ADDS*/
++ str r10, [r8, #0x4b4] /* DRAM_SODT0*/
++ str r10, [r8, #0x4b8] /* DRAM_SODT1*/
++
++ .endm
++
++ .macro imx6dq_ddr_io_save
++
++ ldr r4, [r8, #0x5ac] /* DRAM_DQM0 */
++ ldr r5, [r8, #0x5b4] /* DRAM_DQM1 */
++ ldr r6, [r8, #0x528] /* DRAM_DQM2 */
++ ldr r7, [r8, #0x520] /* DRAM_DQM3 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x514] /* DRAM_DQM4 */
++ ldr r5, [r8, #0x510] /* DRAM_DQM5 */
++ ldr r6, [r8, #0x5bc] /* DRAM_DQM6 */
++ ldr r7, [r8, #0x5c4] /* DRAM_DQM7 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x56c] /* DRAM_CAS */
++ ldr r5, [r8, #0x578] /* DRAM_RAS */
++ ldr r6, [r8, #0x588] /* DRAM_SDCLK_0 */
++ ldr r7, [r8, #0x594] /* DRAM_SDCLK_1 */
++ stmfd r10!, {r4-r7}
++
++ ldr r5, [r8, #0x750] /* DDRMODE_CTL */
++ ldr r6, [r8, #0x774] /* DDRMODE */
++ stmfd r10!, {r5-r6}
++
++ ldr r4, [r8, #0x5a8] /* DRAM_SDQS0 */
++ ldr r5, [r8, #0x5b0] /* DRAM_SDQS1 */
++ ldr r6, [r8, #0x524] /* DRAM_SDQS2 */
++ ldr r7, [r8, #0x51c] /* DRAM_SDQS3 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x518] /* DRAM_SDQS4 */
++ ldr r5, [r8, #0x50c] /* DRAM_SDQS5 */
++ ldr r6, [r8, #0x5b8] /* DRAM_SDQS6 */
++ ldr r7, [r8, #0x5c0] /* DRAM_SDQS7 */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x784] /* GPR_B0DS */
++ ldr r5, [r8, #0x788] /* GPR_B1DS */
++ ldr r6, [r8, #0x794] /* GPR_B2DS */
++ ldr r7, [r8, #0x79c] /* GPR_B3DS */
++ stmfd r10!, {r4-r7}
++
++ ldr r4, [r8, #0x7a0] /* GPR_B4DS */
++ ldr r5, [r8, #0x7a4] /* GPR_B5DS */
++ ldr r6, [r8, #0x7a8] /* GPR_B6DS */
++ ldr r7, [r8, #0x748] /* GPR_B7DS */
++ stmfd r10!, {r4-r7}
++
++ ldr r5, [r8, #0x74c] /* GPR_ADDS*/
++ ldr r6, [r8, #0x59c] /* DRAM_SODT0*/
++ ldr r7, [r8, #0x5a0] /* DRAM_SODT1*/
++ stmfd r10!, {r5-r7}
++
++ .endm
++
++ .macro imx6dq_ddr_io_restore
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x5ac] /* DRAM_DQM0 */
++ str r5, [r8, #0x5b4] /* DRAM_DQM1 */
++ str r6, [r8, #0x528] /* DRAM_DQM2 */
++ str r7, [r8, #0x520] /* DRAM_DQM3 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x514] /* DRAM_DQM4 */
++ str r5, [r8, #0x510] /* DRAM_DQM5 */
++ str r6, [r8, #0x5bc] /* DRAM_DQM6 */
++ str r7, [r8, #0x5c4] /* DRAM_DQM7 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x56c] /* DRAM_CAS */
++ str r5, [r8, #0x578] /* DRAM_RAS */
++ str r6, [r8, #0x588] /* DRAM_SDCLK_0 */
++ str r7, [r8, #0x594] /* DRAM_SDCLK_1 */
++
++ ldmea r10!, {r5-r6}
++ str r5, [r8, #0x750] /* DDRMODE_CTL */
++ str r6, [r8, #0x774] /* DDRMODE */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x5a8] /* DRAM_SDQS0 */
++ str r5, [r8, #0x5b0] /* DRAM_SDQS1 */
++ str r6, [r8, #0x524] /* DRAM_SDQS2 */
++ str r7, [r8, #0x51c] /* DRAM_SDQS3 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x518] /* DRAM_SDQS4 */
++ str r5, [r8, #0x50c] /* DRAM_SDQS5 */
++ str r6, [r8, #0x5b8] /* DRAM_SDQS6 */
++ str r7, [r8, #0x5c0] /* DRAM_SDQS7 */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x784] /* GPR_B0DS */
++ str r5, [r8, #0x788] /* GPR_B1DS */
++ str r6, [r8, #0x794] /* GPR_B2DS */
++ str r7, [r8, #0x79c] /* GPR_B3DS */
++
++ ldmea r10!, {r4-r7}
++ str r4, [r8, #0x7a0] /* GPR_B4DS */
++ str r5, [r8, #0x7a4] /* GPR_B5DS */
++ str r6, [r8, #0x7a8] /* GPR_B6DS */
++ str r7, [r8, #0x748] /* GPR_B7DS */
++
++ ldmea r10!, {r5-r7}
++ str r5, [r8, #0x74c] /* GPR_ADDS*/
++ str r6, [r8, #0x59c] /* DRAM_SODT0*/
++ str r7, [r8, #0x5a0] /* DRAM_SODT1*/
++
++ .endm
++
++ .macro imx6dq_ddr_io_set_lpm
++
++ mov r10, #0
++ str r10, [r8, #0x5ac] /* DRAM_DQM0 */
++ str r10, [r8, #0x5b4] /* DRAM_DQM1 */
++ str r10, [r8, #0x528] /* DRAM_DQM2 */
++ str r10, [r8, #0x520] /* DRAM_DQM3 */
++
++ str r10, [r8, #0x514] /* DRAM_DQM4 */
++ str r10, [r8, #0x510] /* DRAM_DQM5 */
++ str r10, [r8, #0x5bc] /* DRAM_DQM6 */
++ str r10, [r8, #0x5c4] /* DRAM_DQM7 */
++
++ str r10, [r8, #0x56c] /* DRAM_CAS */
++ str r10, [r8, #0x578] /* DRAM_RAS */
++ str r10, [r8, #0x588] /* DRAM_SDCLK_0 */
++ str r10, [r8, #0x594] /* DRAM_SDCLK_1 */
++
++ str r10, [r8, #0x750] /* DDRMODE_CTL */
++ str r10, [r8, #0x774] /* DDRMODE */
++
++ str r10, [r8, #0x5a8] /* DRAM_SDQS0 */
++ str r10, [r8, #0x5b0] /* DRAM_SDQS1 */
++ str r10, [r8, #0x524] /* DRAM_SDQS2 */
++ str r10, [r8, #0x51c] /* DRAM_SDQS3 */
++
++ str r10, [r8, #0x518] /* DRAM_SDQS4 */
++ str r10, [r8, #0x50c] /* DRAM_SDQS5 */
++ str r10, [r8, #0x5b8] /* DRAM_SDQS6 */
++ str r10, [r8, #0x5c0] /* DRAM_SDQS7 */
++
++ str r10, [r8, #0x784] /* GPR_B0DS */
++ str r10, [r8, #0x788] /* GPR_B1DS */
++ str r10, [r8, #0x794] /* GPR_B2DS */
++ str r10, [r8, #0x79c] /* GPR_B3DS */
++
++ str r10, [r8, #0x7a0] /* GPR_B4DS */
++ str r10, [r8, #0x7a4] /* GPR_B5DS */
++ str r10, [r8, #0x7a8] /* GPR_B6DS */
++ str r10, [r8, #0x748] /* GPR_B7DS */
++
++ str r10, [r8, #0x74c] /* GPR_ADDS*/
++ str r10, [r8, #0x59c] /* DRAM_SODT0*/
++ str r10, [r8, #0x5a0] /* DRAM_SODT1*/
++
++ .endm
++
++ .macro sync_l2_cache
++
++ /* sync L2 cache to drain L2's buffers to DRAM. */
++#ifdef CONFIG_CACHE_L2X0
++ ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++ mov r5, #0x0
++ str r5, [r8, #L2X0_CACHE_SYNC]
++1:
++ ldr r5, [r8, #L2X0_CACHE_SYNC]
++ ands r5, r5, #0x1
++ bne 1b
++#endif
++ .endm
++
++ENTRY(imx6_suspend)
++
++ /*
++ * counting the resume address in iram
++ * to set it in SRC register.
++ */
++ ldr r4, =imx6_suspend
++ ldr r5, =resume
++ sub r5, r5, r4
++ add r9, r1, r5
++
++ /*
++ * make sure TLB contain the addr we want,
++ * as we will access after DDR IO floated.
++ */
++
++ ldr r8, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR)
++ ldr r7, [r8, #MX6Q_ANATOP_CORE]
++ ldr r8, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
++ ldr r7, [r8, #0x0]
++ ldr r8, =IMX_IO_P2V(MX6Q_GPC_BASE_ADDR)
++ ldr r7, [r8, #0x0]
++
++ /* use r8 to store the IO address */
++ ldr r8, =IMX_IO_P2V(MX6Q_SRC_BASE_ADDR)
++
++ /*
++ * read previous resume address from SRC
++ * register, which is v7_cpu_resume, this
++ * is for the jump when we finish DDR IO
++ * restore.
++ */
++ ldr r5, [r8, #MX6Q_SRC_GPR1]
++ add r10, r0, #MX6_SUSPEND_IRAM_SIZE
++ stmfd r10!, {r5}
++
++ /* save cpu type */
++ stmfd r10!, {r2}
++
++ str r9, [r8, #MX6Q_SRC_GPR1]
++ add r3, r1, #MX6_SUSPEND_IRAM_SIZE
++ str r3, [r8, #MX6Q_SRC_GPR2]
++
++ ldr r8, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR)
++
++ cmp r2, #MXC_CPU_IMX6Q
++ bne dl_io_dsm_save
++ imx6dq_ddr_io_save
++ b ddr_io_save_dsm_done
++dl_io_dsm_save:
++ cmp r2, #MXC_CPU_IMX6DL
++ bne sl_io_save
++ imx6dl_ddr_io_save
++ b ddr_io_save_dsm_done
++sl_io_save:
++ imx6sl_ddr_io_save
++ddr_io_save_dsm_done:
++
++ /* need to sync L2 cache before DSM. */
++ sync_l2_cache
++
++ ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
++ /*
++ * put DDR explicitly into self-refresh and
++ * disable Automatic power savings.
++ */
++ ldr r7, [r8, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #0x01
++ str r7, [r8, #MX6Q_MMDC_MAPSR]
++
++ /* make the DDR explicitly enter self-refresh. */
++ ldr r7, [r8, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #(1 << 21)
++ str r7, [r8, #MX6Q_MMDC_MAPSR]
++
++poll_dvfs_set_1:
++ ldr r7, [r8, #0x404]
++ ands r7, r7, #(1 << 25)
++ beq poll_dvfs_set_1
++
++ ldr r8, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR)
++
++ cmp r2, #MXC_CPU_IMX6Q
++ bne dl_io_dsm_set_lpm
++ imx6dq_ddr_io_set_lpm
++ b ddr_io_set_lpm_dsm_done
++dl_io_dsm_set_lpm:
++ cmp r2, #MXC_CPU_IMX6DL
++ bne sl_io_dsm_set_lpm
++ imx6dl_ddr_io_set_lpm
++ b ddr_io_set_lpm_dsm_done
++sl_io_dsm_set_lpm:
++ imx6sl_ddr_io_set_lpm
++ddr_io_set_lpm_dsm_done:
++
++ /*
++ * mask all GPC interrupts before
++ * enabling the RBC counters to
++ * avoid the counter starting too
++ * early if an interupt is already
++ * pending.
++ */
++ ldr r8, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
++ /* save CCM base in r9 */
++ mov r9, r8
++ ldr r8, =IMX_IO_P2V(MX6Q_GPC_BASE_ADDR)
++ ldr r4, [r8, #MX6Q_GPC_IMR1]
++ ldr r5, [r8, #MX6Q_GPC_IMR2]
++ ldr r6, [r8, #MX6Q_GPC_IMR3]
++ ldr r7, [r8, #MX6Q_GPC_IMR4]
++
++ ldr r3, =0xffffffff
++ str r3, [r8, #MX6Q_GPC_IMR1]
++ str r3, [r8, #MX6Q_GPC_IMR2]
++ str r3, [r8, #MX6Q_GPC_IMR3]
++ str r3, [r8, #MX6Q_GPC_IMR4]
++
++ /*
++ * enable the RBC bypass counter here
++ * to hold off the interrupts. RBC counter
++ * = 32 (1ms), Minimum RBC delay should be
++ * 400us for the analog LDOs to power down.
++ */
++ ldr r3, [r9, #MX6Q_CCM_CCR]
++ bic r3, r3, #(0x3f << 21)
++ orr r3, r3, #(0x20 << 21)
++ str r3, [r9, #MX6Q_CCM_CCR]
++
++ /* enable the counter. */
++ ldr r3, [r9, #MX6Q_CCM_CCR]
++ orr r3, r3, #(0x1 << 27)
++ str r3, [r9, #MX6Q_CCM_CCR]
++
++ /* unmask all the GPC interrupts. */
++ str r4, [r8, #MX6Q_GPC_IMR1]
++ str r5, [r8, #MX6Q_GPC_IMR2]
++ str r6, [r8, #MX6Q_GPC_IMR3]
++ str r7, [r8, #MX6Q_GPC_IMR4]
++
++ /*
++ * now delay for a short while (3usec)
++ * ARM is at 1GHz at this point
++ * so a short loop should be enough.
++ * this delay is required to ensure that
++ * the RBC counter can start counting in
++ * case an interrupt is already pending
++ * or in case an interrupt arrives just
++ * as ARM is about to assert DSM_request.
++ */
++ ldr r4, =2000
++rbc_loop:
++ sub r4, r4, #0x1
++ cmp r4, #0x0
++ bne rbc_loop
++
++ /*
++ * if internal ldo(VDDARM) bypassed,analog bypass
++ * it for DSM(0x1e) and restore it when resume(0x1f).
++ */
++ ldr r8, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR)
++ ldr r7, [r8, #MX6Q_ANATOP_CORE]
++ and r7, r7, #0x1f
++ cmp r7, #0x1f
++ bne ldo_check_done1
++ldo_analog_bypass:
++ ldr r7, [r8, #MX6Q_ANATOP_CORE]
++ bic r7, r7, #0x1f
++ orr r7, r7, #0x1e
++ str r7, [r8, #MX6Q_ANATOP_CORE]
++ldo_check_done1:
++
++ /* Zzz, enter stop mode */
++ wfi
++ nop
++ nop
++ nop
++ nop
++
++ /*
++ * run to here means there is pending
++ * wakeup source, system should auto
++ * resume, we need to restore DDR IO first
++ */
++
++ /* restore it with 0x1f if use ldo bypass mode.*/
++ ldr r8, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR)
++ ldr r7, [r8, #MX6Q_ANATOP_CORE]
++ and r7, r7, #0x1f
++ cmp r7, #0x1e
++ bne ldo_check_done2
++ldo_bypass_restore:
++ ldr r7, [r8, #MX6Q_ANATOP_CORE]
++ orr r7, r7, #0x1f
++ str r7, [r8, #MX6Q_ANATOP_CORE]
++ldo_check_done2:
++
++ add r10, r0, #MX6_SUSPEND_IRAM_SIZE
++ /* skip the lr saved in iram */
++ sub r10, r10, #0x4
++ /* skip the cpu type saved in iram */
++ sub r10, r10, #0x4
++
++ ldr r8, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR)
++
++ cmp r2, #MXC_CPU_IMX6Q
++ bne dl_io_restore
++ imx6dq_ddr_io_restore
++ b ddr_io_restore_done
++dl_io_restore:
++ cmp r2, #MXC_CPU_IMX6DL
++ bne sl_io_restore
++ imx6dl_ddr_io_restore
++ b ddr_io_restore_done
++sl_io_restore:
++ imx6sl_ddr_io_restore
++ ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
++ /* reset read FIFO, RST_RD_FIFO */
++ ldr r7, =MX6Q_MMDC_MPDGCTRL0
++ ldr r6, [r8, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r8, r7]
++fifo_reset1_wait:
++ ldr r6, [r8, r7]
++ and r6, r6, #(1 << 31)
++ cmp r6, #0
++ bne fifo_reset1_wait
++
++ /* reset FIFO a second time */
++ ldr r6, [r8, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r8, r7]
++fifo_reset2_wait:
++ ldr r6, [r8, r7]
++ and r6, r6, #(1 << 31)
++ cmp r6, #0
++ bne fifo_reset2_wait
++ddr_io_restore_done:
++
++ ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
++ /* let DDR out of self-refresh. */
++ ldr r7, [r8, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #(1 << 21)
++ str r7, [r8, #MX6Q_MMDC_MAPSR]
++
++poll_dvfs_clear_2:
++ ldr r7, [r8, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 25)
++ bne poll_dvfs_clear_2
++ /* enable DDR auto power saving */
++ ldr r7, [r8, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #0x1
++ str r7, [r8, #MX6Q_MMDC_MAPSR]
++ /* return to suspend finish */
++ mov pc, lr
++
++resume:
++ /* invalidate L1 I-cache first */
++ mov r1, #0x0
++ mcr p15, 0, r1, c7, c5, 0
++ mcr p15, 0, r1, c7, c5, 0
++ mcr p15, 0, r1, c7, c5, 6
++ /* enable the Icache and branch prediction */
++ mov r1, #0x1800
++ mcr p15, 0, r1, c1, c0, 0
++ isb
++
++ /* restore it with 0x1f if use ldo bypass mode.*/
++ ldr r8, =MX6Q_ANATOP_BASE_ADDR
++ ldr r7, [r8, #MX6Q_ANATOP_CORE]
++ and r7, r7, #0x1f
++ cmp r7, #0x1e
++ bne ldo_check_done3
++ ldr r7, [r8, #MX6Q_ANATOP_CORE]
++ orr r7, r7, #0x1f
++ str r7, [r8, #MX6Q_ANATOP_CORE]
++ldo_check_done3:
++
++ ldr r5, =MX6Q_SRC_BASE_ADDR
++ ldr r10, [r5, #MX6Q_SRC_GPR2]
++ ldmea r10!, {lr}
++
++ /* get cpu tpye */
++ ldmea r10!, {r2}
++
++ /* clear core0's entry and parameter */
++ ldr r8, =MX6Q_SRC_BASE_ADDR
++ mov r7, #0
++ str r7, [r8, #MX6Q_SRC_GPR1]
++ str r7, [r8, #MX6Q_SRC_GPR2]
++
++ ldr r8, =MX6Q_IOMUXC_BASE_ADDR
++
++ cmp r2, #MXC_CPU_IMX6Q
++ bne dl_io_dsm_restore
++ imx6dq_ddr_io_restore
++ b ddr_io_restore_dsm_done
++dl_io_dsm_restore:
++ cmp r2, #MXC_CPU_IMX6DL
++ bne sl_io_dsm_restore
++ imx6dl_ddr_io_restore
++ b ddr_io_restore_dsm_done
++sl_io_dsm_restore:
++ imx6sl_ddr_io_restore
++ ldr r8, =MX6Q_MMDC_P0_BASE_ADDR
++ /* reset read FIFO, RST_RD_FIFO */
++ ldr r7, =MX6Q_MMDC_MPDGCTRL0
++ ldr r6, [r8, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r8, r7]
++dsm_fifo_reset1_wait:
++ ldr r6, [r8, r7]
++ and r6, r6, #(1 << 31)
++ cmp r6, #0
++ bne dsm_fifo_reset1_wait
++
++ /* reset FIFO a second time */
++ ldr r6, [r8, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r8, r7]
++dsm_fifo_reset2_wait:
++ ldr r6, [r8, r7]
++ and r6, r6, #(1 << 31)
++ cmp r6, #0
++ bne dsm_fifo_reset2_wait
++ddr_io_restore_dsm_done:
++
++ ldr r8, =MX6Q_MMDC_P0_BASE_ADDR
++ /* let DDR out of self-refresh */
++ ldr r7, [r8, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #(1 << 21)
++ str r7, [r8, #MX6Q_MMDC_MAPSR]
++
++poll_dvfs_clear_1:
++ ldr r7, [r8, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 25)
++ bne poll_dvfs_clear_1
++ /* enable DDR auto power saving */
++ ldr r7, [r8, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #0x1
++ str r7, [r8, #MX6Q_MMDC_MAPSR]
++ mov pc, lr
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/system.c linux-linaro-stable-mx6/arch/arm/mach-imx/system.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/system.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/system.c 2014-05-15 20:33:35.397850939 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2006-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
+ *
+@@ -21,15 +21,20 @@
+ #include <linux/io.h>
+ #include <linux/err.h>
+ #include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
+
+ #include <asm/system_misc.h>
+ #include <asm/proc-fns.h>
+ #include <asm/mach-types.h>
++#include <asm/hardware/cache-l2x0.h>
+
+ #include "common.h"
+ #include "hardware.h"
+
+ static void __iomem *wdog_base;
++static struct clk *wdog_clk;
++static u32 wdog_source = 1; /* use WDOG1 default */
+
+ /*
+ * Reset the system. It is called by machine_restart().
+@@ -38,24 +43,32 @@
+ {
+ unsigned int wcr_enable;
+
+- if (cpu_is_mx1()) {
+- wcr_enable = (1 << 0);
+- } else {
+- struct clk *clk;
++ if (wdog_clk)
++ clk_enable(wdog_clk);
+
+- clk = clk_get_sys("imx2-wdt.0", NULL);
+- if (!IS_ERR(clk))
+- clk_prepare_enable(clk);
++ if (cpu_is_mx1())
++ wcr_enable = (1 << 0);
++ /*
++ * Some i.MX6 boards use WDOG2 to reset external pmic in bypass mode,
++ * so do WDOG2 reset here. Do not set SRS, since we will
++ * trigger external POR later. Use WDOG1 to reset in ldo-enable
++ * mode. You can set it by "fsl,wdog-reset" in dts.
++ */
++ else if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
++ cpu_is_imx6sl()))
++ wcr_enable = 0x14;
++ else
+ wcr_enable = (1 << 2);
+- }
+
+ /* Assert SRS signal */
+ __raw_writew(wcr_enable, wdog_base);
++ /* write twice to ensure the request will not get ignored */
++ __raw_writew(wcr_enable, wdog_base);
+
+ /* wait for reset to assert... */
+ mdelay(500);
+
+- printk(KERN_ERR "Watchdog reset failed to assert reset\n");
++ pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
+
+ /* delay to allow the serial port to show the message */
+ mdelay(50);
+@@ -64,7 +77,94 @@
+ soft_restart(0);
+ }
+
+-void mxc_arch_reset_init(void __iomem *base)
++void __init mxc_arch_reset_init(void __iomem *base)
+ {
+ wdog_base = base;
++
++ wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
++ if (IS_ERR(wdog_clk)) {
++ pr_warn("%s: failed to get wdog clock\n", __func__);
++ wdog_clk = NULL;
++ return;
++ }
++
++ clk_prepare(wdog_clk);
++}
++
++void __init mxc_arch_reset_init_dt(void)
++{
++ struct device_node *np = NULL;
++
++ if (cpu_is_imx6q() || cpu_is_imx6dl())
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
++ else if (cpu_is_imx6sl())
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpc");
++
++ if (np)
++ of_property_read_u32(np, "fsl,wdog-reset", &wdog_source);
++ pr_info("Use WDOG%d as reset source\n", wdog_source);
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
++ wdog_base = of_iomap(np, 0);
++ WARN_ON(!wdog_base);
++
++ /* Some i.MX6 boards use WDOG2 to reset board in ldo-bypass mode */
++ if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
++ cpu_is_imx6sl())) {
++ np = of_find_compatible_node(np, NULL, "fsl,imx21-wdt");
++ wdog_base = of_iomap(np, 0);
++ WARN_ON(!wdog_base);
++ }
++
++ wdog_clk = of_clk_get(np, 0);
++ if (IS_ERR(wdog_clk)) {
++ pr_warn("%s: failed to get wdog clock\n", __func__);
++ wdog_clk = NULL;
++ return;
++ }
++
++ clk_prepare(wdog_clk);
++}
++
++#ifdef CONFIG_CACHE_L2X0
++void __init imx_init_l2cache(void)
++{
++ void __iomem *l2x0_base;
++ struct device_node *np;
++ unsigned int val;
++
++ np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
++ if (!np)
++ goto out;
++
++ l2x0_base = of_iomap(np, 0);
++ if (!l2x0_base) {
++ of_node_put(np);
++ goto out;
++ }
++
++ /* Configure the L2 PREFETCH and POWER registers */
++ val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
++ val |= 0x30000000;
++ /*
++ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
++ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
++ * But according to ARM PL310 errata: 752271
++ * ID: 752271: Double linefill feature can cause data corruption
++ * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
++ * Workaround: The only workaround to this erratum is to disable the
++ * double linefill feature. This is the default behavior.
++ */
++ if (!of_machine_is_compatible("fsl,imx6q"))
++ val |= 0x40800000;
++ writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
++ val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
++ writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
++
++ iounmap(l2x0_base);
++ of_node_put(np);
++
++out:
++ l2x0_of_init(0, ~0UL);
+ }
++#endif
+diff -Nur linux-3.10.30.orig/arch/arm/mach-imx/time.c linux-linaro-stable-mx6/arch/arm/mach-imx/time.c
+--- linux-3.10.30.orig/arch/arm/mach-imx/time.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-imx/time.c 2014-05-15 20:33:35.397850939 +0200
+@@ -60,7 +60,11 @@
+ #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
+ #define V2_TCTL_CLK_IPG (1 << 6)
+ #define V2_TCTL_CLK_PER (2 << 6)
++#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
++#define V2_TCTL_CLK_OSC (7 << 6)
++#define V2_TCTL_24MEN (1 << 10)
+ #define V2_TCTL_FRR (1 << 9)
++#define V2_TPRER_PRE24M 12
+ #define V2_IR 0x0c
+ #define V2_TSTAT 0x08
+ #define V2_TSTAT_OF1 (1 << 0)
+@@ -277,11 +281,20 @@
+
+ void __init mxc_timer_init(void __iomem *base, int irq)
+ {
+- uint32_t tctl_val;
++ uint32_t tctl_val, tprer_val;
+ struct clk *timer_clk;
+ struct clk *timer_ipg_clk;
+
+- timer_clk = clk_get_sys("imx-gpt.0", "per");
++ /*
++ * gpt clk source from 24M OSC on imx6q > TO1.0 and
++ * imx6dl, others from per clk.
++ */
++ if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0)
++ || cpu_is_imx6dl())
++ timer_clk = clk_get_sys("imx-gpt.0", "gpt_3m");
++ else
++ timer_clk = clk_get_sys("imx-gpt.0", "per");
++
+ if (IS_ERR(timer_clk)) {
+ pr_err("i.MX timer: unable to get clk\n");
+ return;
+@@ -302,10 +315,24 @@
+ __raw_writel(0, timer_base + MXC_TCTL);
+ __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
+
+- if (timer_is_v2())
+- tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
+- else
++ if (timer_is_v2()) {
++ if ((cpu_is_imx6q() && imx_get_soc_revision() >
++ IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
++ tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR |
++ V2_TCTL_WAITEN | MXC_TCTL_TEN;
++ if (cpu_is_imx6dl()) {
++ /* 24 / 8 = 3 MHz */
++ tprer_val = 7 << V2_TPRER_PRE24M;
++ __raw_writel(tprer_val, timer_base + MXC_TPRER);
++ tctl_val |= V2_TCTL_24MEN;
++ }
++ } else {
++ tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR |
++ V2_TCTL_WAITEN | MXC_TCTL_TEN;
++ }
++ } else {
+ tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
++ }
+
+ __raw_writel(tctl_val, timer_base + MXC_TCTL);
+
+diff -Nur linux-3.10.30.orig/arch/arm/mach-integrator/Makefile linux-linaro-stable-mx6/arch/arm/mach-integrator/Makefile
+--- linux-3.10.30.orig/arch/arm/mach-integrator/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-integrator/Makefile 2014-05-15 20:33:35.405850997 +0200
+@@ -8,5 +8,5 @@
+ obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
+ obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
+
+-obj-$(CONFIG_PCI) += pci_v3.o pci.o
++obj-$(CONFIG_PCI) += pci_v3.o
+ obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
+diff -Nur linux-3.10.30.orig/arch/arm/mach-integrator/pci.c linux-linaro-stable-mx6/arch/arm/mach-integrator/pci.c
+--- linux-3.10.30.orig/arch/arm/mach-integrator/pci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-integrator/pci.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,113 +0,0 @@
+-/*
+- * linux/arch/arm/mach-integrator/pci-integrator.c
+- *
+- * Copyright (C) 1999 ARM Limited
+- * Copyright (C) 2000 Deep Blue Solutions Ltd
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program; if not, write to the Free Software
+- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+- *
+- *
+- * PCI functions for Integrator
+- */
+-#include <linux/kernel.h>
+-#include <linux/pci.h>
+-#include <linux/interrupt.h>
+-#include <linux/init.h>
+-
+-#include <asm/mach/pci.h>
+-#include <asm/mach-types.h>
+-
+-#include <mach/irqs.h>
+-
+-/*
+- * A small note about bridges and interrupts. The DECchip 21050 (and
+- * later) adheres to the PCI-PCI bridge specification. This says that
+- * the interrupts on the other side of a bridge are swizzled in the
+- * following manner:
+- *
+- * Dev Interrupt Interrupt
+- * Pin on Pin on
+- * Device Connector
+- *
+- * 4 A A
+- * B B
+- * C C
+- * D D
+- *
+- * 5 A B
+- * B C
+- * C D
+- * D A
+- *
+- * 6 A C
+- * B D
+- * C A
+- * D B
+- *
+- * 7 A D
+- * B A
+- * C B
+- * D C
+- *
+- * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
+- * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
+- */
+-
+-/*
+- * This routine handles multiple bridges.
+- */
+-static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
+-{
+- if (*pinp == 0)
+- *pinp = 1;
+-
+- return pci_common_swizzle(dev, pinp);
+-}
+-
+-static int irq_tab[4] __initdata = {
+- IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
+-};
+-
+-/*
+- * map the specified device/slot/pin to an IRQ. This works out such
+- * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
+- */
+-static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+-{
+- int intnr = ((slot - 9) + (pin - 1)) & 3;
+-
+- return irq_tab[intnr];
+-}
+-
+-extern void pci_v3_init(void *);
+-
+-static struct hw_pci integrator_pci __initdata = {
+- .swizzle = integrator_swizzle,
+- .map_irq = integrator_map_irq,
+- .setup = pci_v3_setup,
+- .nr_controllers = 1,
+- .ops = &pci_v3_ops,
+- .preinit = pci_v3_preinit,
+- .postinit = pci_v3_postinit,
+-};
+-
+-static int __init integrator_pci_init(void)
+-{
+- if (machine_is_integrator())
+- pci_common_init(&integrator_pci);
+- return 0;
+-}
+-
+-subsys_initcall(integrator_pci_init);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-integrator/pci_v3.c linux-linaro-stable-mx6/arch/arm/mach-integrator/pci_v3.c
+--- linux-3.10.30.orig/arch/arm/mach-integrator/pci_v3.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-integrator/pci_v3.c 2014-05-15 20:33:35.405850997 +0200
+@@ -35,6 +35,7 @@
+ #include <asm/signal.h>
+ #include <asm/mach/pci.h>
+ #include <asm/irq_regs.h>
++#include <asm/mach-types.h>
+
+ #include <asm/hardware/pci_v3.h>
+
+@@ -337,7 +338,7 @@
+ return PCIBIOS_SUCCESSFUL;
+ }
+
+-struct pci_ops pci_v3_ops = {
++static struct pci_ops pci_v3_ops = {
+ .read = v3_read_config,
+ .write = v3_write_config,
+ };
+@@ -471,7 +472,7 @@
+ return IRQ_HANDLED;
+ }
+
+-int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
++static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
+ {
+ int ret = 0;
+
+@@ -490,7 +491,7 @@
+ * V3_LB_BASE? - local bus address
+ * V3_LB_MAP? - pci bus address
+ */
+-void __init pci_v3_preinit(void)
++static void __init pci_v3_preinit(void)
+ {
+ unsigned long flags;
+ unsigned int temp;
+@@ -589,7 +590,7 @@
+ raw_spin_unlock_irqrestore(&v3_lock, flags);
+ }
+
+-void __init pci_v3_postinit(void)
++static void __init pci_v3_postinit(void)
+ {
+ unsigned int pci_cmd;
+
+@@ -610,3 +611,82 @@
+
+ register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
+ }
++
++/*
++ * A small note about bridges and interrupts. The DECchip 21050 (and
++ * later) adheres to the PCI-PCI bridge specification. This says that
++ * the interrupts on the other side of a bridge are swizzled in the
++ * following manner:
++ *
++ * Dev Interrupt Interrupt
++ * Pin on Pin on
++ * Device Connector
++ *
++ * 4 A A
++ * B B
++ * C C
++ * D D
++ *
++ * 5 A B
++ * B C
++ * C D
++ * D A
++ *
++ * 6 A C
++ * B D
++ * C A
++ * D B
++ *
++ * 7 A D
++ * B A
++ * C B
++ * D C
++ *
++ * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
++ * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
++ */
++
++/*
++ * This routine handles multiple bridges.
++ */
++static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
++{
++ if (*pinp == 0)
++ *pinp = 1;
++
++ return pci_common_swizzle(dev, pinp);
++}
++
++static int irq_tab[4] __initdata = {
++ IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
++};
++
++/*
++ * map the specified device/slot/pin to an IRQ. This works out such
++ * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
++ */
++static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ int intnr = ((slot - 9) + (pin - 1)) & 3;
++
++ return irq_tab[intnr];
++}
++
++static struct hw_pci integrator_pci __initdata = {
++ .swizzle = integrator_swizzle,
++ .map_irq = integrator_map_irq,
++ .setup = pci_v3_setup,
++ .nr_controllers = 1,
++ .ops = &pci_v3_ops,
++ .preinit = pci_v3_preinit,
++ .postinit = pci_v3_postinit,
++};
++
++static int __init integrator_pci_init(void)
++{
++ if (machine_is_integrator())
++ pci_common_init(&integrator_pci);
++ return 0;
++}
++
++subsys_initcall(integrator_pci_init);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/core.h linux-linaro-stable-mx6/arch/arm/mach-vexpress/core.h
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/core.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/core.h 2014-05-15 20:33:37.481865968 +0200
+@@ -6,6 +6,8 @@
+
+ void vexpress_dt_smp_map_io(void);
+
++bool vexpress_smp_init_ops(void);
++
+ extern struct smp_operations vexpress_smp_ops;
+
+ extern void vexpress_cpu_die(unsigned int cpu);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/dcscb.c linux-linaro-stable-mx6/arch/arm/mach-vexpress/dcscb.c
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/dcscb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/dcscb.c 2014-05-15 20:33:37.485865997 +0200
+@@ -0,0 +1,236 @@
++/*
++ * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block
++ *
++ * Created by: Nicolas Pitre, May 2012
++ * Copyright: (C) 2012-2013 Linaro Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/spinlock.h>
++#include <linux/errno.h>
++#include <linux/of_address.h>
++#include <linux/vexpress.h>
++#include <linux/arm-cci.h>
++
++#include <asm/mcpm.h>
++#include <asm/proc-fns.h>
++#include <asm/cacheflush.h>
++#include <asm/cputype.h>
++#include <asm/cp15.h>
++#include <asm/psci.h>
++
++
++#define RST_HOLD0 0x0
++#define RST_HOLD1 0x4
++#define SYS_SWRESET 0x8
++#define RST_STAT0 0xc
++#define RST_STAT1 0x10
++#define EAG_CFG_R 0x20
++#define EAG_CFG_W 0x24
++#define KFC_CFG_R 0x28
++#define KFC_CFG_W 0x2c
++#define DCS_CFG_R 0x30
++
++/*
++ * We can't use regular spinlocks. In the switcher case, it is possible
++ * for an outbound CPU to call power_down() while its inbound counterpart
++ * is already live using the same logical CPU number which trips lockdep
++ * debugging.
++ */
++static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
++
++static void __iomem *dcscb_base;
++static int dcscb_use_count[4][2];
++static int dcscb_allcpus_mask[2];
++
++static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
++{
++ unsigned int rst_hold, cpumask = (1 << cpu);
++ unsigned int all_mask = dcscb_allcpus_mask[cluster];
++
++ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
++ if (cpu >= 4 || cluster >= 2)
++ return -EINVAL;
++
++ /*
++ * Since this is called with IRQs enabled, and no arch_spin_lock_irq
++ * variant exists, we need to disable IRQs manually here.
++ */
++ local_irq_disable();
++ arch_spin_lock(&dcscb_lock);
++
++ dcscb_use_count[cpu][cluster]++;
++ if (dcscb_use_count[cpu][cluster] == 1) {
++ rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
++ if (rst_hold & (1 << 8)) {
++ /* remove cluster reset and add individual CPU's reset */
++ rst_hold &= ~(1 << 8);
++ rst_hold |= all_mask;
++ }
++ rst_hold &= ~(cpumask | (cpumask << 4));
++ writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
++ } else if (dcscb_use_count[cpu][cluster] != 2) {
++ /*
++ * The only possible values are:
++ * 0 = CPU down
++ * 1 = CPU (still) up
++ * 2 = CPU requested to be up before it had a chance
++ * to actually make itself down.
++ * Any other value is a bug.
++ */
++ BUG();
++ }
++
++ arch_spin_unlock(&dcscb_lock);
++ local_irq_enable();
++
++ return 0;
++}
++
++static void dcscb_power_down(void)
++{
++ unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask;
++ bool last_man = false, skip_wfi = false;
++
++ mpidr = read_cpuid_mpidr();
++ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
++ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++ cpumask = (1 << cpu);
++ all_mask = dcscb_allcpus_mask[cluster];
++
++ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
++ BUG_ON(cpu >= 4 || cluster >= 2);
++
++ __mcpm_cpu_going_down(cpu, cluster);
++
++ arch_spin_lock(&dcscb_lock);
++ BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
++ dcscb_use_count[cpu][cluster]--;
++ if (dcscb_use_count[cpu][cluster] == 0) {
++ rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
++ rst_hold |= cpumask;
++ if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) {
++ rst_hold |= (1 << 8);
++ last_man = true;
++ }
++ writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
++ } else if (dcscb_use_count[cpu][cluster] == 1) {
++ /*
++ * A power_up request went ahead of us.
++ * Even if we do not want to shut this CPU down,
++ * the caller expects a certain state as if the WFI
++ * was aborted. So let's continue with cache cleaning.
++ */
++ skip_wfi = true;
++ } else
++ BUG();
++
++ if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
++ arch_spin_unlock(&dcscb_lock);
++
++ /* Flush all cache levels for this cluster. */
++ v7_exit_coherency_flush(all);
++
++ /*
++ * This is a harmless no-op. On platforms with a real
++ * outer cache this might either be needed or not,
++ * depending on where the outer cache sits.
++ */
++ outer_flush_all();
++
++ /*
++ * Disable cluster-level coherency by masking
++ * incoming snoops and DVM messages:
++ */
++ cci_disable_port_by_cpu(mpidr);
++
++ __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
++ } else {
++ arch_spin_unlock(&dcscb_lock);
++
++ /* Disable and flush the local CPU cache. */
++ v7_exit_coherency_flush(louis);
++ }
++
++ __mcpm_cpu_down(cpu, cluster);
++
++ /* Now we are prepared for power-down, do it: */
++ dsb();
++ if (!skip_wfi)
++ wfi();
++
++ /* Not dead at this point? Let our caller cope. */
++}
++
++static const struct mcpm_platform_ops dcscb_power_ops = {
++ .power_up = dcscb_power_up,
++ .power_down = dcscb_power_down,
++};
++
++static void __init dcscb_usage_count_init(void)
++{
++ unsigned int mpidr, cpu, cluster;
++
++ mpidr = read_cpuid_mpidr();
++ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
++ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++
++ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
++ BUG_ON(cpu >= 4 || cluster >= 2);
++ dcscb_use_count[cpu][cluster] = 1;
++}
++
++extern void dcscb_power_up_setup(unsigned int affinity_level);
++
++static int __init dcscb_init(void)
++{
++ struct device_node *node;
++ unsigned int cfg;
++ int ret;
++
++ ret = psci_probe();
++ if (!ret) {
++ pr_debug("psci found. Aborting native init\n");
++ return -ENODEV;
++ }
++
++ if (!cci_probed())
++ return -ENODEV;
++
++ node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
++ if (!node)
++ return -ENODEV;
++ dcscb_base = of_iomap(node, 0);
++ if (!dcscb_base)
++ return -EADDRNOTAVAIL;
++ cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
++ dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
++ dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
++ dcscb_usage_count_init();
++
++ ret = mcpm_platform_register(&dcscb_power_ops);
++ if (!ret)
++ ret = mcpm_sync_init(dcscb_power_up_setup);
++ if (ret) {
++ iounmap(dcscb_base);
++ return ret;
++ }
++
++ pr_info("VExpress DCSCB support installed\n");
++
++ /*
++ * Future entries into the kernel can now go
++ * through the cluster entry vectors.
++ */
++ vexpress_flags_set(virt_to_phys(mcpm_entry_point));
++
++ return 0;
++}
++
++early_initcall(dcscb_init);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/dcscb_setup.S linux-linaro-stable-mx6/arch/arm/mach-vexpress/dcscb_setup.S
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/dcscb_setup.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/dcscb_setup.S 2014-05-15 20:33:37.485865997 +0200
+@@ -0,0 +1,38 @@
++/*
++ * arch/arm/include/asm/dcscb_setup.S
++ *
++ * Created by: Dave Martin, 2012-06-22
++ * Copyright: (C) 2012-2013 Linaro Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/linkage.h>
++
++
++ENTRY(dcscb_power_up_setup)
++
++ cmp r0, #0 @ check affinity level
++ beq 2f
++
++/*
++ * Enable cluster-level coherency, in preparation for turning on the MMU.
++ * The ACTLR SMP bit does not need to be set here, because cpu_resume()
++ * already restores that.
++ *
++ * A15/A7 may not require explicit L2 invalidation on reset, dependent
++ * on hardware integration decisions.
++ * For now, this code assumes that L2 is either already invalidated,
++ * or invalidation is not required.
++ */
++
++ b cci_enable_port_for_self
++
++2: @ Implementation-specific local CPU setup operations should go here,
++ @ if any. In this case, there is nothing to do.
++
++ bx lr
++
++ENDPROC(dcscb_power_up_setup)
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/include/mach/tc2.h linux-linaro-stable-mx6/arch/arm/mach-vexpress/include/mach/tc2.h
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/include/mach/tc2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/include/mach/tc2.h 2014-05-15 20:33:37.485865997 +0200
+@@ -0,0 +1,10 @@
++#ifndef __MACH_TC2_H
++#define __MACH_TC2_H
++
++/*
++ * cpu and cluster limits
++ */
++#define TC2_MAX_CPUS 3
++#define TC2_MAX_CLUSTERS 2
++
++#endif
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/Kconfig linux-linaro-stable-mx6/arch/arm/mach-vexpress/Kconfig
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/Kconfig 2014-05-15 20:33:37.481865968 +0200
+@@ -1,5 +1,7 @@
+ config ARCH_VEXPRESS
+ bool "ARM Ltd. Versatile Express family" if ARCH_MULTI_V7
++ select ARCH_HAS_CPUFREQ
++ select ARCH_HAS_OPP
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_AMBA
+ select ARM_GIC
+@@ -56,5 +58,23 @@
+
+ config ARCH_VEXPRESS_CA9X4
+ bool "Versatile Express Cortex-A9x4 tile"
++ select ARM_ERRATA_643719
++
++config ARCH_VEXPRESS_DCSCB
++ bool "Dual Cluster System Control Block (DCSCB) support"
++ depends on MCPM
++ select ARM_CCI
++ help
++ Support for the Dual Cluster System Configuration Block (DCSCB).
++ This is needed to provide CPU and cluster power management
++ on RTSM implementing big.LITTLE.
++
++config ARCH_VEXPRESS_TC2
++ bool "TC2 cluster management"
++ depends on MCPM
++ select VEXPRESS_SPC
++ select ARM_CCI
++ help
++ Support for CPU and cluster power management on TC2.
+
+ endmenu
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/Makefile linux-linaro-stable-mx6/arch/arm/mach-vexpress/Makefile
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/Makefile 2014-05-15 20:33:37.481865968 +0200
+@@ -6,5 +6,13 @@
+
+ obj-y := v2m.o
+ obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
++obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o
++CFLAGS_REMOVE_dcscb.o = -pg
++obj-$(CONFIG_ARCH_VEXPRESS_TC2) += tc2_pm.o tc2_pm_setup.o
++CFLAGS_REMOVE_tc2_pm.o = -pg
++ifeq ($(CONFIG_ARCH_VEXPRESS_TC2),y)
++obj-$(CONFIG_ARM_PSCI) += tc2_pm_psci.o
++CFLAGS_REMOVE_tc2_pm_psci.o = -pg
++endif
+ obj-$(CONFIG_SMP) += platsmp.o
+ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/platsmp.c linux-linaro-stable-mx6/arch/arm/mach-vexpress/platsmp.c
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/platsmp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/platsmp.c 2014-05-15 20:33:37.485865997 +0200
+@@ -12,9 +12,11 @@
+ #include <linux/errno.h>
+ #include <linux/smp.h>
+ #include <linux/io.h>
++#include <linux/of.h>
+ #include <linux/of_fdt.h>
+ #include <linux/vexpress.h>
+
++#include <asm/mcpm.h>
+ #include <asm/smp_scu.h>
+ #include <asm/mach/map.h>
+
+@@ -203,3 +205,21 @@
+ .cpu_die = vexpress_cpu_die,
+ #endif
+ };
++
++bool __init vexpress_smp_init_ops(void)
++{
++#ifdef CONFIG_MCPM
++ /*
++ * The best way to detect a multi-cluster configuration at the moment
++ * is to look for the presence of a CCI in the system.
++ * Override the default vexpress_smp_ops if so.
++ */
++ struct device_node *node;
++ node = of_find_compatible_node(NULL, NULL, "arm,cci-400");
++ if (node && of_device_is_available(node)) {
++ mcpm_smp_set_ops();
++ return true;
++ }
++#endif
++ return false;
++}
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/tc2_pm.c linux-linaro-stable-mx6/arch/arm/mach-vexpress/tc2_pm.c
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/tc2_pm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/tc2_pm.c 2014-05-15 20:33:37.485865997 +0200
+@@ -0,0 +1,277 @@
++/*
++ * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
++ *
++ * Created by: Nicolas Pitre, October 2012
++ * Copyright: (C) 2012 Linaro Limited
++ *
++ * Some portions of this file were originally written by Achin Gupta
++ * Copyright: (C) 2012 ARM Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/errno.h>
++#include <linux/irqchip/arm-gic.h>
++
++#include <asm/mcpm.h>
++#include <asm/proc-fns.h>
++#include <asm/cacheflush.h>
++#include <asm/cputype.h>
++#include <asm/cp15.h>
++#include <asm/psci.h>
++
++#include <mach/motherboard.h>
++#include <mach/tc2.h>
++
++#include <linux/vexpress.h>
++#include <linux/arm-cci.h>
++
++/*
++ * We can't use regular spinlocks. In the switcher case, it is possible
++ * for an outbound CPU to call power_down() after its inbound counterpart
++ * is already live using the same logical CPU number which trips lockdep
++ * debugging.
++ */
++static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
++
++static int tc2_pm_use_count[TC2_MAX_CPUS][TC2_MAX_CLUSTERS];
++
++static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
++{
++ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
++ if (cluster >= TC2_MAX_CLUSTERS ||
++ cpu >= vexpress_spc_get_nb_cpus(cluster))
++ return -EINVAL;
++
++ /*
++ * Since this is called with IRQs enabled, and no arch_spin_lock_irq
++ * variant exists, we need to disable IRQs manually here.
++ */
++ local_irq_disable();
++ arch_spin_lock(&tc2_pm_lock);
++
++ if (!tc2_pm_use_count[0][cluster] &&
++ !tc2_pm_use_count[1][cluster] &&
++ !tc2_pm_use_count[2][cluster])
++ vexpress_spc_powerdown_enable(cluster, 0);
++
++ tc2_pm_use_count[cpu][cluster]++;
++ if (tc2_pm_use_count[cpu][cluster] == 1) {
++ vexpress_spc_write_resume_reg(cluster, cpu,
++ virt_to_phys(mcpm_entry_point));
++ vexpress_spc_set_cpu_wakeup_irq(cpu, cluster, 1);
++ } else if (tc2_pm_use_count[cpu][cluster] != 2) {
++ /*
++ * The only possible values are:
++ * 0 = CPU down
++ * 1 = CPU (still) up
++ * 2 = CPU requested to be up before it had a chance
++ * to actually make itself down.
++ * Any other value is a bug.
++ */
++ BUG();
++ }
++
++ arch_spin_unlock(&tc2_pm_lock);
++ local_irq_enable();
++
++ return 0;
++}
++
++static void tc2_pm_down(u64 residency)
++{
++ unsigned int mpidr, cpu, cluster;
++ bool last_man = false, skip_wfi = false;
++
++ mpidr = read_cpuid_mpidr();
++ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
++ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++
++ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
++ BUG_ON(cluster >= TC2_MAX_CLUSTERS ||
++ cpu >= vexpress_spc_get_nb_cpus(cluster));
++
++ __mcpm_cpu_going_down(cpu, cluster);
++
++ arch_spin_lock(&tc2_pm_lock);
++ BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
++ tc2_pm_use_count[cpu][cluster]--;
++ if (tc2_pm_use_count[cpu][cluster] == 0) {
++ vexpress_spc_set_cpu_wakeup_irq(cpu, cluster, 1);
++ if (!tc2_pm_use_count[0][cluster] &&
++ !tc2_pm_use_count[1][cluster] &&
++ !tc2_pm_use_count[2][cluster] &&
++ (!residency || residency > 5000)) {
++ vexpress_spc_powerdown_enable(cluster, 1);
++ vexpress_spc_set_global_wakeup_intr(1);
++ last_man = true;
++ }
++ } else if (tc2_pm_use_count[cpu][cluster] == 1) {
++ /*
++ * A power_up request went ahead of us.
++ * Even if we do not want to shut this CPU down,
++ * the caller expects a certain state as if the WFI
++ * was aborted. So let's continue with cache cleaning.
++ */
++ skip_wfi = true;
++ } else
++ BUG();
++
++ /*
++ * If the CPU is committed to power down, make sure
++ * the power controller will be in charge of waking it
++ * up upon IRQ, ie IRQ lines are cut from GIC CPU IF
++ * to the CPU by disabling the GIC CPU IF to prevent wfi
++ * from completing execution behind power controller back
++ */
++ if (!skip_wfi)
++ gic_cpu_if_down();
++
++ if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
++ arch_spin_unlock(&tc2_pm_lock);
++
++ if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
++ /*
++ * On the Cortex-A15 we need to disable
++ * L2 prefetching before flushing the cache.
++ */
++ asm volatile(
++ "mcr p15, 1, %0, c15, c0, 3 \n\t"
++ "isb \n\t"
++ "dsb "
++ : : "r" (0x400) );
++ }
++
++ v7_exit_coherency_flush(all);
++
++ cci_disable_port_by_cpu(mpidr);
++
++ __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
++ } else {
++ /*
++ * If last man then undo any setup done previously.
++ */
++ if (last_man) {
++ vexpress_spc_powerdown_enable(cluster, 0);
++ vexpress_spc_set_global_wakeup_intr(0);
++ }
++
++ arch_spin_unlock(&tc2_pm_lock);
++
++ v7_exit_coherency_flush(louis);
++ }
++
++ __mcpm_cpu_down(cpu, cluster);
++
++ /* Now we are prepared for power-down, do it: */
++ if (!skip_wfi)
++ wfi();
++
++ /* Not dead at this point? Let our caller cope. */
++}
++
++static void tc2_pm_power_down(void)
++{
++ tc2_pm_down(0);
++}
++
++static void tc2_pm_suspend(u64 residency)
++{
++ extern void tc2_resume(void);
++ unsigned int mpidr, cpu, cluster;
++
++ mpidr = read_cpuid_mpidr();
++ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
++ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++ vexpress_spc_write_resume_reg(cluster, cpu,
++ virt_to_phys(tc2_resume));
++
++ tc2_pm_down(residency);
++}
++
++static void tc2_pm_powered_up(void)
++{
++ unsigned int mpidr, cpu, cluster;
++ unsigned long flags;
++
++ mpidr = read_cpuid_mpidr();
++ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
++ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++
++ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
++ BUG_ON(cluster >= TC2_MAX_CLUSTERS ||
++ cpu >= vexpress_spc_get_nb_cpus(cluster));
++
++ local_irq_save(flags);
++ arch_spin_lock(&tc2_pm_lock);
++
++ if (!tc2_pm_use_count[0][cluster] &&
++ !tc2_pm_use_count[1][cluster] &&
++ !tc2_pm_use_count[2][cluster]) {
++ vexpress_spc_powerdown_enable(cluster, 0);
++ vexpress_spc_set_global_wakeup_intr(0);
++ }
++
++ if (!tc2_pm_use_count[cpu][cluster])
++ tc2_pm_use_count[cpu][cluster] = 1;
++
++ vexpress_spc_set_cpu_wakeup_irq(cpu, cluster, 0);
++ vexpress_spc_write_resume_reg(cluster, cpu, 0);
++
++ arch_spin_unlock(&tc2_pm_lock);
++ local_irq_restore(flags);
++}
++
++static const struct mcpm_platform_ops tc2_pm_power_ops = {
++ .power_up = tc2_pm_power_up,
++ .power_down = tc2_pm_power_down,
++ .suspend = tc2_pm_suspend,
++ .powered_up = tc2_pm_powered_up,
++};
++
++static void __init tc2_pm_usage_count_init(void)
++{
++ unsigned int mpidr, cpu, cluster;
++
++ mpidr = read_cpuid_mpidr();
++ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
++ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++
++ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
++ BUG_ON(cluster >= TC2_MAX_CLUSTERS ||
++ cpu >= vexpress_spc_get_nb_cpus(cluster));
++
++ tc2_pm_use_count[cpu][cluster] = 1;
++}
++
++extern void tc2_pm_power_up_setup(unsigned int affinity_level);
++
++static int __init tc2_pm_init(void)
++{
++ int ret;
++
++ ret = psci_probe();
++ if (!ret) {
++ pr_debug("psci found. Aborting native init\n");
++ return -ENODEV;
++ }
++
++ if (!vexpress_spc_check_loaded())
++ return -ENODEV;
++
++ tc2_pm_usage_count_init();
++
++ ret = mcpm_platform_register(&tc2_pm_power_ops);
++ if (!ret)
++ ret = mcpm_sync_init(tc2_pm_power_up_setup);
++ if (!ret)
++ pr_info("TC2 power management initialized\n");
++ return ret;
++}
++
++early_initcall(tc2_pm_init);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/tc2_pm_psci.c linux-linaro-stable-mx6/arch/arm/mach-vexpress/tc2_pm_psci.c
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/tc2_pm_psci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/tc2_pm_psci.c 2014-05-15 20:33:37.485865997 +0200
+@@ -0,0 +1,173 @@
++/*
++ * arch/arm/mach-vexpress/tc2_pm_psci.c - TC2 PSCI support
++ *
++ * Created by: Achin Gupta, December 2012
++ * Copyright: (C) 2012 ARM Limited
++ *
++ * Some portions of this file were originally written by Nicolas Pitre
++ * Copyright: (C) 2012 Linaro Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/spinlock.h>
++#include <linux/errno.h>
++
++#include <asm/mcpm.h>
++#include <asm/proc-fns.h>
++#include <asm/cacheflush.h>
++#include <asm/psci.h>
++#include <asm/atomic.h>
++#include <asm/cputype.h>
++#include <asm/cp15.h>
++
++#include <mach/motherboard.h>
++#include <mach/tc2.h>
++
++#include <linux/vexpress.h>
++
++/*
++ * Platform specific state id understood by the firmware and used to
++ * program the power controller
++ */
++#define PSCI_POWER_STATE_ID 0
++
++static atomic_t tc2_pm_use_count[TC2_MAX_CPUS][TC2_MAX_CLUSTERS];
++
++static int tc2_pm_psci_power_up(unsigned int cpu, unsigned int cluster)
++{
++ unsigned int mpidr = (cluster << 8) | cpu;
++ int ret = 0;
++
++ BUG_ON(!psci_ops.cpu_on);
++
++ switch (atomic_inc_return(&tc2_pm_use_count[cpu][cluster])) {
++ case 1:
++ /*
++ * This is a request to power up a cpu that linux thinks has
++ * been powered down. Retries are needed if the firmware has
++ * seen the power down request as yet.
++ */
++ do
++ ret = psci_ops.cpu_on(mpidr,
++ virt_to_phys(mcpm_entry_point));
++ while (ret == -EAGAIN);
++
++ return ret;
++ case 2:
++ /* This power up request has overtaken a power down request */
++ return ret;
++ default:
++ /* Any other value is a bug */
++ BUG();
++ }
++}
++
++static void tc2_pm_psci_power_down(void)
++{
++ struct psci_power_state power_state;
++ unsigned int mpidr, cpu, cluster;
++
++ mpidr = read_cpuid_mpidr();
++ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
++ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++
++ BUG_ON(!psci_ops.cpu_off);
++
++ switch (atomic_dec_return(&tc2_pm_use_count[cpu][cluster])) {
++ case 1:
++ /*
++ * Overtaken by a power up. Flush caches, exit coherency,
++ * return & fake a reset
++ */
++ set_cr(get_cr() & ~CR_C);
++
++ flush_cache_louis();
++
++ asm volatile ("clrex");
++ set_auxcr(get_auxcr() & ~(1 << 6));
++
++ return;
++ case 0:
++ /* A normal request to possibly power down the cluster */
++ power_state.id = PSCI_POWER_STATE_ID;
++ power_state.type = PSCI_POWER_STATE_TYPE_POWER_DOWN;
++ power_state.affinity_level = PSCI_POWER_STATE_AFFINITY_LEVEL1;
++
++ psci_ops.cpu_off(power_state);
++
++ /* On success this function never returns */
++ default:
++ /* Any other value is a bug */
++ BUG();
++ }
++}
++
++static void tc2_pm_psci_suspend(u64 unused)
++{
++ struct psci_power_state power_state;
++
++ BUG_ON(!psci_ops.cpu_suspend);
++
++ /* On TC2 always attempt to power down the cluster */
++ power_state.id = PSCI_POWER_STATE_ID;
++ power_state.type = PSCI_POWER_STATE_TYPE_POWER_DOWN;
++ power_state.affinity_level = PSCI_POWER_STATE_AFFINITY_LEVEL1;
++
++ psci_ops.cpu_suspend(power_state, virt_to_phys(mcpm_entry_point));
++
++ /* On success this function never returns */
++ BUG();
++}
++
++static const struct mcpm_platform_ops tc2_pm_power_ops = {
++ .power_up = tc2_pm_psci_power_up,
++ .power_down = tc2_pm_psci_power_down,
++ .suspend = tc2_pm_psci_suspend,
++};
++
++static void __init tc2_pm_usage_count_init(void)
++{
++ unsigned int mpidr, cpu, cluster;
++
++ mpidr = read_cpuid_mpidr();
++ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
++ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
++
++ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
++ BUG_ON(cluster >= TC2_MAX_CLUSTERS ||
++ cpu >= vexpress_spc_get_nb_cpus(cluster));
++
++ atomic_set(&tc2_pm_use_count[cpu][cluster], 1);
++}
++
++static int __init tc2_pm_psci_init(void)
++{
++ int ret;
++
++ ret = psci_probe();
++ if (ret) {
++ pr_debug("psci not found. Aborting psci init\n");
++ return -ENODEV;
++ }
++
++ if (!vexpress_spc_check_loaded()) {
++ pr_debug("spc not found. Aborting psci init\n");
++ return -ENODEV;
++ }
++
++ tc2_pm_usage_count_init();
++
++ ret = mcpm_platform_register(&tc2_pm_power_ops);
++ if (!ret)
++ ret = mcpm_sync_init(NULL);
++ if (!ret)
++ pr_info("TC2 power management initialized\n");
++ return ret;
++}
++
++early_initcall(tc2_pm_psci_init);
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/tc2_pm_setup.S linux-linaro-stable-mx6/arch/arm/mach-vexpress/tc2_pm_setup.S
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/tc2_pm_setup.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/tc2_pm_setup.S 2014-05-15 20:33:37.485865997 +0200
+@@ -0,0 +1,68 @@
++/*
++ * arch/arm/include/asm/tc2_pm_setup.S
++ *
++ * Created by: Nicolas Pitre, October 2012
++ ( (based on dcscb_setup.S by Dave Martin)
++ * Copyright: (C) 2012 Linaro Limited
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++
++#include <linux/linkage.h>
++#include <asm/mcpm.h>
++
++
++#define SPC_PHYS_BASE 0x7FFF0000
++#define SPC_WAKE_INT_STAT 0xb2c
++
++#define SNOOP_CTL_A15 0x404
++#define SNOOP_CTL_A7 0x504
++
++#define A15_SNOOP_MASK (0x3 << 7)
++#define A7_SNOOP_MASK (0x1 << 13)
++
++#define A15_BX_ADDR0 0xB68
++
++
++ENTRY(tc2_resume)
++ mrc p15, 0, r0, c0, c0, 5
++ ubfx r1, r0, #0, #4 @ r1 = cpu
++ ubfx r2, r0, #8, #4 @ r2 = cluster
++ add r1, r1, r2, lsl #2 @ r1 = index of CPU in WAKE_INT_STAT
++ ldr r3, =SPC_PHYS_BASE + SPC_WAKE_INT_STAT
++ ldr r3, [r3]
++ lsr r3, r1
++ tst r3, #1
++ wfieq @ if no pending IRQ reenters wfi
++ b mcpm_entry_point
++ENDPROC(tc2_resume)
++
++/*
++ * Enable cluster-level coherency, in preparation for turning on the MMU.
++ * The ACTLR SMP bit does not need to be set here, because cpu_resume()
++ * already restores that.
++ */
++
++ENTRY(tc2_pm_power_up_setup)
++
++ cmp r0, #0
++ beq 2f
++
++ b cci_enable_port_for_self
++
++2: @ Clear the BX addr register
++ ldr r3, =SPC_PHYS_BASE + A15_BX_ADDR0
++ mrc p15, 0, r0, c0, c0, 5 @ MPIDR
++ ubfx r1, r0, #8, #4 @ cluster
++ ubfx r0, r0, #0, #4 @ cpu
++ add r3, r3, r1, lsl #4
++ mov r1, #0
++ str r1, [r3, r0, lsl #2]
++ dsb
++
++ bx lr
++
++ENDPROC(tc2_pm_power_up_setup)
+diff -Nur linux-3.10.30.orig/arch/arm/mach-vexpress/v2m.c linux-linaro-stable-mx6/arch/arm/mach-vexpress/v2m.c
+--- linux-3.10.30.orig/arch/arm/mach-vexpress/v2m.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-vexpress/v2m.c 2014-05-15 20:33:37.485865997 +0200
+@@ -10,6 +10,7 @@
+ #include <linux/smp.h>
+ #include <linux/init.h>
+ #include <linux/irqchip.h>
++#include <linux/memblock.h>
+ #include <linux/of_address.h>
+ #include <linux/of_fdt.h>
+ #include <linux/of_irq.h>
+@@ -373,6 +374,31 @@
+ .init_machine = v2m_init,
+ MACHINE_END
+
++static void __init v2m_dt_hdlcd_init(void)
++{
++ struct device_node *node;
++ int len, na, ns;
++ const __be32 *prop;
++ phys_addr_t fb_base, fb_size;
++
++ node = of_find_compatible_node(NULL, NULL, "arm,hdlcd");
++ if (!node)
++ return;
++
++ na = of_n_addr_cells(node);
++ ns = of_n_size_cells(node);
++
++ prop = of_get_property(node, "framebuffer", &len);
++ if (WARN_ON(!prop || len < (na + ns) * sizeof(*prop)))
++ return;
++
++ fb_base = of_read_number(prop, na);
++ fb_size = of_read_number(prop + na, ns);
++
++ if (WARN_ON(memblock_remove(fb_base, fb_size)))
++ return;
++};
++
+ static struct map_desc v2m_rs1_io_desc __initdata = {
+ .virtual = V2M_PERIPH,
+ .pfn = __phys_to_pfn(0x1c000000),
+@@ -423,6 +449,8 @@
+ pr_warning("vexpress: DT HBI (%x) is not matching "
+ "hardware (%x)!\n", dt_hbi, hbi);
+ }
++
++ v2m_dt_hdlcd_init();
+ }
+
+ static void __init v2m_dt_timer_init(void)
+@@ -456,6 +484,7 @@
+ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
+ .dt_compat = v2m_dt_match,
+ .smp = smp_ops(vexpress_smp_ops),
++ .smp_init = smp_init_ops(vexpress_smp_init_ops),
+ .map_io = v2m_dt_map_io,
+ .init_early = v2m_dt_init_early,
+ .init_irq = irqchip_init,
+diff -Nur linux-3.10.30.orig/arch/arm/mach-virt/Makefile linux-linaro-stable-mx6/arch/arm/mach-virt/Makefile
+--- linux-3.10.30.orig/arch/arm/mach-virt/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-virt/Makefile 2014-05-15 20:33:37.485865997 +0200
+@@ -3,4 +3,3 @@
+ #
+
+ obj-y := virt.o
+-obj-$(CONFIG_SMP) += platsmp.o
+diff -Nur linux-3.10.30.orig/arch/arm/mach-virt/platsmp.c linux-linaro-stable-mx6/arch/arm/mach-virt/platsmp.c
+--- linux-3.10.30.orig/arch/arm/mach-virt/platsmp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-virt/platsmp.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,50 +0,0 @@
+-/*
+- * Dummy Virtual Machine - does what it says on the tin.
+- *
+- * Copyright (C) 2012 ARM Ltd
+- * Author: Will Deacon <will.deacon@arm.com>
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#include <linux/init.h>
+-#include <linux/smp.h>
+-#include <linux/of.h>
+-
+-#include <asm/psci.h>
+-#include <asm/smp_plat.h>
+-
+-extern void secondary_startup(void);
+-
+-static void __init virt_smp_init_cpus(void)
+-{
+-}
+-
+-static void __init virt_smp_prepare_cpus(unsigned int max_cpus)
+-{
+-}
+-
+-static int __cpuinit virt_boot_secondary(unsigned int cpu,
+- struct task_struct *idle)
+-{
+- if (psci_ops.cpu_on)
+- return psci_ops.cpu_on(cpu_logical_map(cpu),
+- __pa(secondary_startup));
+- return -ENODEV;
+-}
+-
+-struct smp_operations __initdata virt_smp_ops = {
+- .smp_init_cpus = virt_smp_init_cpus,
+- .smp_prepare_cpus = virt_smp_prepare_cpus,
+- .smp_boot_secondary = virt_boot_secondary,
+-};
+diff -Nur linux-3.10.30.orig/arch/arm/mach-virt/virt.c linux-linaro-stable-mx6/arch/arm/mach-virt/virt.c
+--- linux-3.10.30.orig/arch/arm/mach-virt/virt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mach-virt/virt.c 2014-05-15 20:33:37.485865997 +0200
+@@ -36,11 +36,8 @@
+ NULL
+ };
+
+-extern struct smp_operations virt_smp_ops;
+-
+ DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
+ .init_irq = irqchip_init,
+ .init_machine = virt_init,
+- .smp = smp_ops(virt_smp_ops),
+ .dt_compat = virt_dt_match,
+ MACHINE_END
+diff -Nur linux-3.10.30.orig/arch/arm/mm/cache-v7.S linux-linaro-stable-mx6/arch/arm/mm/cache-v7.S
+--- linux-3.10.30.orig/arch/arm/mm/cache-v7.S 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mm/cache-v7.S 2014-05-15 20:33:37.521866257 +0200
+@@ -146,18 +146,18 @@
+ ldr r7, =0x7fff
+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
+ loop1:
+- mov r9, r4 @ create working copy of max way size
++ mov r9, r7 @ create working copy of max index
+ loop2:
+- ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
+- THUMB( lsl r6, r9, r5 )
++ ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
++ THUMB( lsl r6, r4, r5 )
+ THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
+- ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
+- THUMB( lsl r6, r7, r2 )
++ ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
++ THUMB( lsl r6, r9, r2 )
+ THUMB( orr r11, r11, r6 ) @ factor index number into r11
+ mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
+- subs r9, r9, #1 @ decrement the way
++ subs r9, r9, #1 @ decrement the index
+ bge loop2
+- subs r7, r7, #1 @ decrement the index
++ subs r4, r4, #1 @ decrement the way
+ bge loop1
+ skip:
+ add r10, r10, #2 @ increment cache number
+diff -Nur linux-3.10.30.orig/arch/arm/mm/fault.c linux-linaro-stable-mx6/arch/arm/mm/fault.c
+--- linux-3.10.30.orig/arch/arm/mm/fault.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/mm/fault.c 2014-05-15 20:33:37.525866286 +0200
+@@ -446,8 +446,16 @@
+
+ if (pud_none(*pud_k))
+ goto bad_area;
+- if (!pud_present(*pud))
++ if (!pud_present(*pud)) {
+ set_pud(pud, *pud_k);
++ /*
++ * There is a small window during free_pgtables() where the
++ * user *pud entry is 0 but the TLB has not been invalidated
++ * and we get a level 2 (pmd) translation fault caused by the
++ * intermediate TLB caching of the old level 1 (pud) entry.
++ */
++ flush_tlb_kernel_page(addr);
++ }
+
+ pmd = pmd_offset(pud, addr);
+ pmd_k = pmd_offset(pud_k, addr);
+@@ -470,8 +478,9 @@
+ #endif
+ if (pmd_none(pmd_k[index]))
+ goto bad_area;
++ if (!pmd_present(pmd[index]))
++ copy_pmd(pmd, pmd_k);
+
+- copy_pmd(pmd, pmd_k);
+ return 0;
+
+ bad_area:
+diff -Nur linux-3.10.30.orig/arch/arm/plat-versatile/headsmp.S linux-linaro-stable-mx6/arch/arm/plat-versatile/headsmp.S
+--- linux-3.10.30.orig/arch/arm/plat-versatile/headsmp.S 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm/plat-versatile/headsmp.S 2014-05-15 20:33:37.653867209 +0200
+@@ -11,8 +11,6 @@
+ #include <linux/linkage.h>
+ #include <linux/init.h>
+
+- __INIT
+-
+ /*
+ * Realview/Versatile Express specific entry point for secondary CPUs.
+ * This provides a "holding pen" into which all secondary cores are held
+diff -Nur linux-3.10.30.orig/arch/arm64/boot/dts/fvp-base-gicv2-psci.dts linux-linaro-stable-mx6/arch/arm64/boot/dts/fvp-base-gicv2-psci.dts
+--- linux-3.10.30.orig/arch/arm64/boot/dts/fvp-base-gicv2-psci.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/boot/dts/fvp-base-gicv2-psci.dts 2014-05-15 20:33:37.681867411 +0200
+@@ -0,0 +1,287 @@
++/*
++ * Copyright (c) 2013, ARM Limited. All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ *
++ * Redistributions of source code must retain the above copyright notice, this
++ * list of conditions and the following disclaimer.
++ *
++ * Redistributions in binary form must reproduce the above copyright notice,
++ * this list of conditions and the following disclaimer in the documentation
++ * and/or other materials provided with the distribution.
++ *
++ * Neither the name of ARM nor the names of its contributors may be used
++ * to endorse or promote products derived from this software without specific
++ * prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
++ * POSSIBILITY OF SUCH DAMAGE.
++ */
++
++/dts-v1/;
++
++/memreserve/ 0x80000000 0x00010000;
++
++/ {
++};
++
++/ {
++ model = "FVP Base";
++ compatible = "arm,vfp-base", "arm,vexpress";
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ chosen { };
++
++ aliases {
++ serial0 = &v2m_serial0;
++ serial1 = &v2m_serial1;
++ serial2 = &v2m_serial2;
++ serial3 = &v2m_serial3;
++ };
++
++ psci {
++ compatible = "arm,psci";
++ method = "smc";
++ cpu_suspend = <0xc4000001>;
++ cpu_off = <0x84000002>;
++ cpu_on = <0xc4000003>;
++ };
++
++ cpus {
++ #address-cells = <2>;
++ #size-cells = <0>;
++
++ big0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a57", "arm,armv8";
++ reg = <0x0 0x0>;
++ enable-method = "psci";
++ clock-frequency = <1000000>;
++ };
++ big1: cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a57", "arm,armv8";
++ reg = <0x0 0x1>;
++ enable-method = "psci";
++ clock-frequency = <1000000>;
++ };
++ big2: cpu@2 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a57", "arm,armv8";
++ reg = <0x0 0x2>;
++ enable-method = "psci";
++ clock-frequency = <1000000>;
++ };
++ big3: cpu@3 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a57", "arm,armv8";
++ reg = <0x0 0x3>;
++ enable-method = "psci";
++ clock-frequency = <1000000>;
++ };
++ little0: cpu@100 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53", "arm,armv8";
++ reg = <0x0 0x100>;
++ enable-method = "psci";
++ clock-frequency = <1000000>;
++ };
++ little1: cpu@101 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53", "arm,armv8";
++ reg = <0x0 0x101>;
++ enable-method = "psci";
++ clock-frequency = <1000000>;
++ };
++ little2: cpu@102 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53", "arm,armv8";
++ reg = <0x0 0x102>;
++ enable-method = "psci";
++ clock-frequency = <1000000>;
++ };
++ little3: cpu@103 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53", "arm,armv8";
++ reg = <0x0 0x103>;
++ enable-method = "psci";
++ clock-frequency = <1000000>;
++ };
++
++ cpu-map {
++ cluster0 {
++ core0 {
++ cpu = <&big0>;
++ };
++ core1 {
++ cpu = <&big1>;
++ };
++ core2 {
++ cpu = <&big2>;
++ };
++ core3 {
++ cpu = <&big3>;
++ };
++ };
++ cluster1 {
++ core0 {
++ cpu = <&little0>;
++ };
++ core1 {
++ cpu = <&little1>;
++ };
++ core2 {
++ cpu = <&little2>;
++ };
++ core3 {
++ cpu = <&little3>;
++ };
++ };
++ };
++ };
++
++ memory@80000000 {
++ device_type = "memory";
++ reg = <0x00000000 0x80000000 0 0x80000000>,
++ <0x00000008 0x80000000 0 0x80000000>;
++ };
++
++ gic: interrupt-controller@2f000000 {
++ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ #address-cells = <0>;
++ interrupt-controller;
++ reg = <0x0 0x2f000000 0 0x10000>,
++ <0x0 0x2c000000 0 0x2000>,
++ <0x0 0x2c010000 0 0x2000>,
++ <0x0 0x2c02F000 0 0x2000>;
++ interrupts = <1 9 0xf04>;
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <1 13 0xff01>,
++ <1 14 0xff01>,
++ <1 11 0xff01>,
++ <1 10 0xff01>;
++ clock-frequency = <100000000>;
++ };
++
++ timer@2a810000 {
++ compatible = "arm,armv7-timer-mem";
++ reg = <0x0 0x2a810000 0x0 0x10000>;
++ clock-frequency = <100000000>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++ frame@2a820000 {
++ frame-number = <0>;
++ interrupts = <0 25 4>;
++ reg = <0x0 0x2a820000 0x0 0x10000>;
++ };
++ };
++
++ pmu {
++ compatible = "arm,armv8-pmuv3";
++ interrupts = <0 60 4>,
++ <0 61 4>,
++ <0 62 4>,
++ <0 63 4>;
++ };
++
++ smb {
++ compatible = "simple-bus";
++
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0 0x08000000 0x04000000>,
++ <1 0 0 0x14000000 0x04000000>,
++ <2 0 0 0x18000000 0x04000000>,
++ <3 0 0 0x1c000000 0x04000000>,
++ <4 0 0 0x0c000000 0x04000000>,
++ <5 0 0 0x10000000 0x04000000>;
++
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 63>;
++ interrupt-map = <0 0 0 &gic 0 0 4>,
++ <0 0 1 &gic 0 1 4>,
++ <0 0 2 &gic 0 2 4>,
++ <0 0 3 &gic 0 3 4>,
++ <0 0 4 &gic 0 4 4>,
++ <0 0 5 &gic 0 5 4>,
++ <0 0 6 &gic 0 6 4>,
++ <0 0 7 &gic 0 7 4>,
++ <0 0 8 &gic 0 8 4>,
++ <0 0 9 &gic 0 9 4>,
++ <0 0 10 &gic 0 10 4>,
++ <0 0 11 &gic 0 11 4>,
++ <0 0 12 &gic 0 12 4>,
++ <0 0 13 &gic 0 13 4>,
++ <0 0 14 &gic 0 14 4>,
++ <0 0 15 &gic 0 15 4>,
++ <0 0 16 &gic 0 16 4>,
++ <0 0 17 &gic 0 17 4>,
++ <0 0 18 &gic 0 18 4>,
++ <0 0 19 &gic 0 19 4>,
++ <0 0 20 &gic 0 20 4>,
++ <0 0 21 &gic 0 21 4>,
++ <0 0 22 &gic 0 22 4>,
++ <0 0 23 &gic 0 23 4>,
++ <0 0 24 &gic 0 24 4>,
++ <0 0 25 &gic 0 25 4>,
++ <0 0 26 &gic 0 26 4>,
++ <0 0 27 &gic 0 27 4>,
++ <0 0 28 &gic 0 28 4>,
++ <0 0 29 &gic 0 29 4>,
++ <0 0 30 &gic 0 30 4>,
++ <0 0 31 &gic 0 31 4>,
++ <0 0 32 &gic 0 32 4>,
++ <0 0 33 &gic 0 33 4>,
++ <0 0 34 &gic 0 34 4>,
++ <0 0 35 &gic 0 35 4>,
++ <0 0 36 &gic 0 36 4>,
++ <0 0 37 &gic 0 37 4>,
++ <0 0 38 &gic 0 38 4>,
++ <0 0 39 &gic 0 39 4>,
++ <0 0 40 &gic 0 40 4>,
++ <0 0 41 &gic 0 41 4>,
++ <0 0 42 &gic 0 42 4>;
++
++ /include/ "rtsm_ve-motherboard.dtsi"
++ };
++
++ panels {
++ panel@0 {
++ compatible = "panel";
++ mode = "XVGA";
++ refresh = <60>;
++ xres = <1024>;
++ yres = <768>;
++ pixclock = <15748>;
++ left_margin = <152>;
++ right_margin = <48>;
++ upper_margin = <23>;
++ lower_margin = <3>;
++ hsync_len = <104>;
++ vsync_len = <4>;
++ sync = <0>;
++ vmode = "FB_VMODE_NONINTERLACED";
++ tim2 = "TIM2_BCD", "TIM2_IPC";
++ cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
++ caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
++ bpp = <16>;
++ };
++ };
++};
+diff -Nur linux-3.10.30.orig/arch/arm64/boot/dts/Makefile linux-linaro-stable-mx6/arch/arm64/boot/dts/Makefile
+--- linux-3.10.30.orig/arch/arm64/boot/dts/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/boot/dts/Makefile 2014-05-15 20:33:37.681867411 +0200
+@@ -1,4 +1,5 @@
+-dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
++dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb \
++ fvp-base-gicv2-psci.dtb
+
+ targets += dtbs
+ targets += $(dtb-y)
+diff -Nur linux-3.10.30.orig/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi linux-linaro-stable-mx6/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi
+--- linux-3.10.30.orig/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi 2014-05-15 20:33:37.681867411 +0200
+@@ -182,6 +182,15 @@
+ interrupts = <14>;
+ clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
+ clock-names = "clcdclk", "apb_pclk";
++ mode = "XVGA";
++ use_dma = <0>;
++ framebuffer = <0x18000000 0x00180000>;
++ };
++
++ virtio_block@0130000 {
++ compatible = "virtio,mmio";
++ reg = <0x130000 0x200>;
++ interrupts = <42>;
+ };
+ };
+
+diff -Nur linux-3.10.30.orig/arch/arm64/include/asm/cmpxchg.h linux-linaro-stable-mx6/arch/arm64/include/asm/cmpxchg.h
+--- linux-3.10.30.orig/arch/arm64/include/asm/cmpxchg.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/include/asm/cmpxchg.h 2014-05-15 20:33:37.685867440 +0200
+@@ -158,17 +158,23 @@
+ return ret;
+ }
+
+-#define cmpxchg(ptr,o,n) \
+- ((__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
+- (unsigned long)(o), \
+- (unsigned long)(n), \
+- sizeof(*(ptr))))
++#define cmpxchg(ptr, o, n) \
++({ \
++ __typeof__(*(ptr)) __ret; \
++ __ret = (__typeof__(*(ptr))) \
++ __cmpxchg_mb((ptr), (unsigned long)(o), (unsigned long)(n), \
++ sizeof(*(ptr))); \
++ __ret; \
++})
+
+-#define cmpxchg_local(ptr,o,n) \
+- ((__typeof__(*(ptr)))__cmpxchg((ptr), \
+- (unsigned long)(o), \
+- (unsigned long)(n), \
+- sizeof(*(ptr))))
++#define cmpxchg_local(ptr, o, n) \
++({ \
++ __typeof__(*(ptr)) __ret; \
++ __ret = (__typeof__(*(ptr))) \
++ __cmpxchg((ptr), (unsigned long)(o), \
++ (unsigned long)(n), sizeof(*(ptr))); \
++ __ret; \
++})
+
+ #define cmpxchg64(ptr,o,n) cmpxchg((ptr),(o),(n))
+ #define cmpxchg64_local(ptr,o,n) cmpxchg_local((ptr),(o),(n))
+diff -Nur linux-3.10.30.orig/arch/arm64/include/asm/cpu_ops.h linux-linaro-stable-mx6/arch/arm64/include/asm/cpu_ops.h
+--- linux-3.10.30.orig/arch/arm64/include/asm/cpu_ops.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/include/asm/cpu_ops.h 2014-05-15 20:33:37.685867440 +0200
+@@ -0,0 +1,59 @@
++/*
++ * Copyright (C) 2013 ARM Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++#ifndef __ASM_CPU_OPS_H
++#define __ASM_CPU_OPS_H
++
++#include <linux/init.h>
++#include <linux/threads.h>
++
++struct device_node;
++
++/**
++ * struct cpu_operations - Callback operations for hotplugging CPUs.
++ *
++ * @name: Name of the property as appears in a devicetree cpu node's
++ * enable-method property.
++ * @cpu_init: Reads any data necessary for a specific enable-method from the
++ * devicetree, for a given cpu node and proposed logical id.
++ * @cpu_prepare: Early one-time preparation step for a cpu. If there is a
++ * mechanism for doing so, tests whether it is possible to boot
++ * the given CPU.
++ * @cpu_boot: Boots a cpu into the kernel.
++ * @cpu_postboot: Optionally, perform any post-boot cleanup or necesary
++ * synchronisation. Called from the cpu being booted.
++ * @cpu_disable: Prepares a cpu to die. May fail for some mechanism-specific
++ * reason, which will cause the hot unplug to be aborted. Called
++ * from the cpu to be killed.
++ * @cpu_die: Makes a cpu leave the kernel. Must not fail. Called from the
++ * cpu being killed.
++ */
++struct cpu_operations {
++ const char *name;
++ int (*cpu_init)(struct device_node *, unsigned int);
++ int (*cpu_prepare)(unsigned int);
++ int (*cpu_boot)(unsigned int);
++ void (*cpu_postboot)(void);
++#ifdef CONFIG_HOTPLUG_CPU
++ int (*cpu_disable)(unsigned int cpu);
++ void (*cpu_die)(unsigned int cpu);
++#endif
++};
++
++extern const struct cpu_operations *cpu_ops[NR_CPUS];
++extern int __init cpu_read_ops(struct device_node *dn, int cpu);
++extern void __init cpu_read_bootcpu_ops(void);
++
++#endif /* ifndef __ASM_CPU_OPS_H */
+diff -Nur linux-3.10.30.orig/arch/arm64/include/asm/irq.h linux-linaro-stable-mx6/arch/arm64/include/asm/irq.h
+--- linux-3.10.30.orig/arch/arm64/include/asm/irq.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/include/asm/irq.h 2014-05-15 20:33:37.685867440 +0200
+@@ -4,6 +4,7 @@
+ #include <asm-generic/irq.h>
+
+ extern void (*handle_arch_irq)(struct pt_regs *);
++extern void migrate_irqs(void);
+ extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
+
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm64/include/asm/pgtable-3level-types.h linux-linaro-stable-mx6/arch/arm64/include/asm/pgtable-3level-types.h
+--- linux-3.10.30.orig/arch/arm64/include/asm/pgtable-3level-types.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/include/asm/pgtable-3level-types.h 2014-05-15 20:33:37.709867612 +0200
+@@ -16,6 +16,8 @@
+ #ifndef __ASM_PGTABLE_3LEVEL_TYPES_H
+ #define __ASM_PGTABLE_3LEVEL_TYPES_H
+
++#include <asm/types.h>
++
+ typedef u64 pteval_t;
+ typedef u64 pmdval_t;
+ typedef u64 pgdval_t;
+diff -Nur linux-3.10.30.orig/arch/arm64/include/asm/psci.h linux-linaro-stable-mx6/arch/arm64/include/asm/psci.h
+--- linux-3.10.30.orig/arch/arm64/include/asm/psci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/include/asm/psci.h 2014-05-15 20:33:37.709867612 +0200
+@@ -14,25 +14,6 @@
+ #ifndef __ASM_PSCI_H
+ #define __ASM_PSCI_H
+
+-#define PSCI_POWER_STATE_TYPE_STANDBY 0
+-#define PSCI_POWER_STATE_TYPE_POWER_DOWN 1
+-
+-struct psci_power_state {
+- u16 id;
+- u8 type;
+- u8 affinity_level;
+-};
+-
+-struct psci_operations {
+- int (*cpu_suspend)(struct psci_power_state state,
+- unsigned long entry_point);
+- int (*cpu_off)(struct psci_power_state state);
+- int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
+- int (*migrate)(unsigned long cpuid);
+-};
+-
+-extern struct psci_operations psci_ops;
+-
+ int psci_init(void);
+
+ #endif /* __ASM_PSCI_H */
+diff -Nur linux-3.10.30.orig/arch/arm64/include/asm/smp.h linux-linaro-stable-mx6/arch/arm64/include/asm/smp.h
+--- linux-3.10.30.orig/arch/arm64/include/asm/smp.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/include/asm/smp.h 2014-05-15 20:33:37.709867612 +0200
+@@ -60,21 +60,14 @@
+ void *stack;
+ };
+ extern struct secondary_data secondary_data;
+-extern void secondary_holding_pen(void);
+-extern volatile unsigned long secondary_holding_pen_release;
++extern void secondary_entry(void);
+
+ extern void arch_send_call_function_single_ipi(int cpu);
+ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+
+-struct device_node;
++extern int __cpu_disable(void);
+
+-struct smp_enable_ops {
+- const char *name;
+- int (*init_cpu)(struct device_node *, int);
+- int (*prepare_cpu)(int);
+-};
+-
+-extern const struct smp_enable_ops smp_spin_table_ops;
+-extern const struct smp_enable_ops smp_psci_ops;
++extern void __cpu_die(unsigned int cpu);
++extern void cpu_die(void);
+
+ #endif /* ifndef __ASM_SMP_H */
+diff -Nur linux-3.10.30.orig/arch/arm64/include/asm/topology.h linux-linaro-stable-mx6/arch/arm64/include/asm/topology.h
+--- linux-3.10.30.orig/arch/arm64/include/asm/topology.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/include/asm/topology.h 2014-05-15 20:33:37.713867642 +0200
+@@ -0,0 +1,73 @@
++#ifndef _ASM_ARM_TOPOLOGY_H
++#define _ASM_ARM_TOPOLOGY_H
++
++#ifdef CONFIG_ARM_CPU_TOPOLOGY
++
++#include <linux/cpumask.h>
++
++struct cputopo_arm {
++ int thread_id;
++ int core_id;
++ int socket_id;
++ cpumask_t thread_sibling;
++ cpumask_t core_sibling;
++};
++
++extern struct cputopo_arm cpu_topology[NR_CPUS];
++
++#define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id)
++#define topology_core_id(cpu) (cpu_topology[cpu].core_id)
++#define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling)
++#define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling)
++
++#define mc_capable() (cpu_topology[0].socket_id != -1)
++#define smt_capable() (cpu_topology[0].thread_id != -1)
++
++void init_cpu_topology(void);
++void store_cpu_topology(unsigned int cpuid);
++const struct cpumask *cpu_coregroup_mask(int cpu);
++int cluster_to_logical_mask(unsigned int socket_id, cpumask_t *cluster_mask);
++
++#ifdef CONFIG_DISABLE_CPU_SCHED_DOMAIN_BALANCE
++/* Common values for CPUs */
++#ifndef SD_CPU_INIT
++#define SD_CPU_INIT (struct sched_domain) { \
++ .min_interval = 1, \
++ .max_interval = 4, \
++ .busy_factor = 64, \
++ .imbalance_pct = 125, \
++ .cache_nice_tries = 1, \
++ .busy_idx = 2, \
++ .idle_idx = 1, \
++ .newidle_idx = 0, \
++ .wake_idx = 0, \
++ .forkexec_idx = 0, \
++ \
++ .flags = 0*SD_LOAD_BALANCE \
++ | 1*SD_BALANCE_NEWIDLE \
++ | 1*SD_BALANCE_EXEC \
++ | 1*SD_BALANCE_FORK \
++ | 0*SD_BALANCE_WAKE \
++ | 1*SD_WAKE_AFFINE \
++ | 0*SD_SHARE_CPUPOWER \
++ | 0*SD_SHARE_PKG_RESOURCES \
++ | 0*SD_SERIALIZE \
++ , \
++ .last_balance = jiffies, \
++ .balance_interval = 1, \
++}
++#endif
++#endif /* CONFIG_DISABLE_CPU_SCHED_DOMAIN_BALANCE */
++
++#else
++
++static inline void init_cpu_topology(void) { }
++static inline void store_cpu_topology(unsigned int cpuid) { }
++static inline int cluster_to_logical_mask(unsigned int socket_id,
++ cpumask_t *cluster_mask) { return -EINVAL; }
++
++#endif
++
++#include <asm-generic/topology.h>
++
++#endif /* _ASM_ARM_TOPOLOGY_H */
+diff -Nur linux-3.10.30.orig/arch/arm64/Kconfig linux-linaro-stable-mx6/arch/arm64/Kconfig
+--- linux-3.10.30.orig/arch/arm64/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/Kconfig 2014-05-15 20:33:37.657867237 +0200
+@@ -144,12 +144,139 @@
+
+ If you don't know what to do here, say N.
+
++config ARM_CPU_TOPOLOGY
++ bool "Support CPU topology definition"
++ depends on SMP
++ default y
++ help
++ Support CPU topology definition, based on configuration
++ provided by the firmware.
++
++config SCHED_MC
++ bool "Multi-core scheduler support"
++ depends on ARM_CPU_TOPOLOGY
++ help
++ Multi-core scheduler support improves the CPU scheduler's decision
++ making when dealing with multi-core CPU chips at a cost of slightly
++ increased overhead in some places. If unsure say N here.
++
++config SCHED_SMT
++ bool "SMT scheduler support"
++ depends on ARM_CPU_TOPOLOGY
++ help
++ Improves the CPU scheduler's decision making when dealing with
++ MultiThreading at a cost of slightly increased overhead in some
++ places. If unsure say N here.
++
++config DISABLE_CPU_SCHED_DOMAIN_BALANCE
++ bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
++ help
++ Disables scheduler load-balancing at CPU sched domain level.
++
++config SCHED_HMP
++ bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
++ depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
++ help
++ Experimental scheduler optimizations for heterogeneous platforms.
++ Attempts to introspectively select task affinity to optimize power
++ and performance. Basic support for multiple (>2) cpu types is in place,
++ but it has only been tested with two types of cpus.
++ There is currently no support for migration of task groups, hence
++ !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
++ between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
++
++config SCHED_HMP_PRIO_FILTER
++ bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
++ depends on SCHED_HMP
++ help
++ Enables task priority based HMP migration filter. Any task with
++ a NICE value above the threshold will always be on low-power cpus
++ with less compute capacity.
++
++config SCHED_HMP_PRIO_FILTER_VAL
++ int "NICE priority threshold"
++ default 5
++ depends on SCHED_HMP_PRIO_FILTER
++
++config HMP_FAST_CPU_MASK
++ string "HMP scheduler fast CPU mask"
++ depends on SCHED_HMP
++ help
++ Leave empty to use device tree information.
++ Specify the cpuids of the fast CPUs in the system as a list string,
++ e.g. cpuid 0+1 should be specified as 0-1.
++
++config HMP_SLOW_CPU_MASK
++ string "HMP scheduler slow CPU mask"
++ depends on SCHED_HMP
++ help
++ Leave empty to use device tree information.
++ Specify the cpuids of the slow CPUs in the system as a list string,
++ e.g. cpuid 0+1 should be specified as 0-1.
++
++config HMP_VARIABLE_SCALE
++ bool "Allows changing the load tracking scale through sysfs"
++ depends on SCHED_HMP
++ help
++ When turned on, this option exports the thresholds and load average
++ period value for the load tracking patches through sysfs.
++ The values can be modified to change the rate of load accumulation
++ and the thresholds used for HMP migration.
++ The load_avg_period_ms is the time in ms to reach a load average of
++ 0.5 for an idle task of 0 load average ratio that start a busy loop.
++ The up_threshold and down_threshold is the value to go to a faster
++ CPU or to go back to a slower cpu.
++ The {up,down}_threshold are devided by 1024 before being compared
++ to the load average.
++ For examples, with load_avg_period_ms = 128 and up_threshold = 512,
++ a running task with a load of 0 will be migrated to a bigger CPU after
++ 128ms, because after 128ms its load_avg_ratio is 0.5 and the real
++ up_threshold is 0.5.
++ This patch has the same behavior as changing the Y of the load
++ average computation to
++ (1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
++ but it remove intermadiate overflows in computation.
++
++config HMP_FREQUENCY_INVARIANT_SCALE
++ bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
++ depends on HMP_VARIABLE_SCALE && CPU_FREQ
++ help
++ Scales the current load contribution in line with the frequency
++ of the CPU that the task was executed on.
++ In this version, we use a simple linear scale derived from the
++ maximum frequency reported by CPUFreq.
++ Restricting tracked load to be scaled by the CPU's frequency
++ represents the consumption of possible compute capacity
++ (rather than consumption of actual instantaneous capacity as
++ normal) and allows the HMP migration's simple threshold
++ migration strategy to interact more predictably with CPUFreq's
++ asynchronous compute capacity changes.
++
++config SCHED_HMP_LITTLE_PACKING
++ bool "Small task packing for HMP"
++ depends on SCHED_HMP
++ default n
++ help
++ Allows the HMP Scheduler to pack small tasks into CPUs in the
++ smallest HMP domain.
++ Controlled by two sysfs files in sys/kernel/hmp.
++ packing_enable: 1 to enable, 0 to disable packing. Default 1.
++ packing_limit: runqueue load ratio where a RQ is considered
++ to be full. Default is NICE_0_LOAD * 9/8.
++
+ config NR_CPUS
+ int "Maximum number of CPUs (2-32)"
+ range 2 32
+ depends on SMP
+ default "4"
+
++config HOTPLUG_CPU
++ bool "Support for hot-pluggable CPUs"
++ depends on SMP
++ help
++ Say Y here to experiment with turning CPUs off and on. CPUs
++ can be controlled through /sys/devices/system/cpu.
++
+ source kernel/Kconfig.preempt
+
+ config HZ
+@@ -229,6 +356,14 @@
+
+ endmenu
+
++menu "Power management options"
++
++source "kernel/power/Kconfig"
++
++source "drivers/cpufreq/Kconfig"
++
++endmenu
++
+ source "net/Kconfig"
+
+ source "drivers/Kconfig"
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/cpu_ops.c linux-linaro-stable-mx6/arch/arm64/kernel/cpu_ops.c
+--- linux-3.10.30.orig/arch/arm64/kernel/cpu_ops.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/cpu_ops.c 2014-05-15 20:33:37.713867642 +0200
+@@ -0,0 +1,99 @@
++/*
++ * CPU kernel entry/exit control
++ *
++ * Copyright (C) 2013 ARM Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <asm/cpu_ops.h>
++#include <asm/smp_plat.h>
++#include <linux/errno.h>
++#include <linux/of.h>
++#include <linux/string.h>
++
++extern const struct cpu_operations smp_spin_table_ops;
++extern const struct cpu_operations cpu_psci_ops;
++
++const struct cpu_operations *cpu_ops[NR_CPUS];
++
++static const struct cpu_operations *supported_cpu_ops[] __initconst = {
++#ifdef CONFIG_SMP
++ &smp_spin_table_ops,
++ &cpu_psci_ops,
++#endif
++ NULL,
++};
++
++static const struct cpu_operations * __init cpu_get_ops(const char *name)
++{
++ const struct cpu_operations **ops = supported_cpu_ops;
++
++ while (*ops) {
++ if (!strcmp(name, (*ops)->name))
++ return *ops;
++
++ ops++;
++ }
++
++ return NULL;
++}
++
++/*
++ * Read a cpu's enable method from the device tree and record it in cpu_ops.
++ */
++int __init cpu_read_ops(struct device_node *dn, int cpu)
++{
++ const char *enable_method = of_get_property(dn, "enable-method", NULL);
++ if (!enable_method) {
++ /*
++ * The boot CPU may not have an enable method (e.g. when
++ * spin-table is used for secondaries). Don't warn spuriously.
++ */
++ if (cpu != 0)
++ pr_err("%s: missing enable-method property\n",
++ dn->full_name);
++ return -ENOENT;
++ }
++
++ cpu_ops[cpu] = cpu_get_ops(enable_method);
++ if (!cpu_ops[cpu]) {
++ pr_warn("%s: unsupported enable-method property: %s\n",
++ dn->full_name, enable_method);
++ return -EOPNOTSUPP;
++ }
++
++ return 0;
++}
++
++void __init cpu_read_bootcpu_ops(void)
++{
++ struct device_node *dn = NULL;
++ u64 mpidr = cpu_logical_map(0);
++
++ while ((dn = of_find_node_by_type(dn, "cpu"))) {
++ u64 hwid;
++ const __be32 *prop;
++
++ prop = of_get_property(dn, "reg", NULL);
++ if (!prop)
++ continue;
++
++ hwid = of_read_number(prop, of_n_addr_cells(dn));
++ if (hwid == mpidr) {
++ cpu_read_ops(dn, 0);
++ of_node_put(dn);
++ return;
++ }
++ }
++}
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/cputable.c linux-linaro-stable-mx6/arch/arm64/kernel/cputable.c
+--- linux-3.10.30.orig/arch/arm64/kernel/cputable.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/cputable.c 2014-05-15 20:33:37.713867642 +0200
+@@ -22,7 +22,7 @@
+
+ extern unsigned long __cpu_setup(void);
+
+-struct cpu_info __initdata cpu_table[] = {
++struct cpu_info cpu_table[] = {
+ {
+ .cpu_id_val = 0x000f0000,
+ .cpu_id_mask = 0x000f0000,
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/head.S linux-linaro-stable-mx6/arch/arm64/kernel/head.S
+--- linux-3.10.30.orig/arch/arm64/kernel/head.S 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/head.S 2014-05-15 20:33:37.717867670 +0200
+@@ -217,7 +217,6 @@
+ .quad PAGE_OFFSET
+
+ #ifdef CONFIG_SMP
+- .pushsection .smp.pen.text, "ax"
+ .align 3
+ 1: .quad .
+ .quad secondary_holding_pen_release
+@@ -242,7 +241,16 @@
+ wfe
+ b pen
+ ENDPROC(secondary_holding_pen)
+- .popsection
++
++ /*
++ * Secondary entry point that jumps straight into the kernel. Only to
++ * be used where CPUs are brought online dynamically by the kernel.
++ */
++ENTRY(secondary_entry)
++ bl __calc_phys_offset // x2=phys offset
++ bl el2_setup // Drop to EL1
++ b secondary_startup
++ENDPROC(secondary_entry)
+
+ ENTRY(secondary_startup)
+ /*
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/irq.c linux-linaro-stable-mx6/arch/arm64/kernel/irq.c
+--- linux-3.10.30.orig/arch/arm64/kernel/irq.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/irq.c 2014-05-15 20:33:37.717867670 +0200
+@@ -81,3 +81,64 @@
+ if (!handle_arch_irq)
+ panic("No interrupt controller found.");
+ }
++
++#ifdef CONFIG_HOTPLUG_CPU
++static bool migrate_one_irq(struct irq_desc *desc)
++{
++ struct irq_data *d = irq_desc_get_irq_data(desc);
++ const struct cpumask *affinity = d->affinity;
++ struct irq_chip *c;
++ bool ret = false;
++
++ /*
++ * If this is a per-CPU interrupt, or the affinity does not
++ * include this CPU, then we have nothing to do.
++ */
++ if (irqd_is_per_cpu(d) || !cpumask_test_cpu(smp_processor_id(), affinity))
++ return false;
++
++ if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
++ affinity = cpu_online_mask;
++ ret = true;
++ }
++
++ c = irq_data_get_irq_chip(d);
++ if (!c->irq_set_affinity)
++ pr_debug("IRQ%u: unable to set affinity\n", d->irq);
++ else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
++ cpumask_copy(d->affinity, affinity);
++
++ return ret;
++}
++
++/*
++ * The current CPU has been marked offline. Migrate IRQs off this CPU.
++ * If the affinity settings do not allow other CPUs, force them onto any
++ * available CPU.
++ *
++ * Note: we must iterate over all IRQs, whether they have an attached
++ * action structure or not, as we need to get chained interrupts too.
++ */
++void migrate_irqs(void)
++{
++ unsigned int i;
++ struct irq_desc *desc;
++ unsigned long flags;
++
++ local_irq_save(flags);
++
++ for_each_irq_desc(i, desc) {
++ bool affinity_broken;
++
++ raw_spin_lock(&desc->lock);
++ affinity_broken = migrate_one_irq(desc);
++ raw_spin_unlock(&desc->lock);
++
++ if (affinity_broken)
++ pr_warn_ratelimited("IRQ%u no longer affine to CPU%u\n",
++ i, smp_processor_id());
++ }
++
++ local_irq_restore(flags);
++}
++#endif /* CONFIG_HOTPLUG_CPU */
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/Makefile linux-linaro-stable-mx6/arch/arm64/kernel/Makefile
+--- linux-3.10.30.orig/arch/arm64/kernel/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/Makefile 2014-05-15 20:33:37.713867642 +0200
+@@ -9,15 +9,16 @@
+ arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \
+ entry-fpsimd.o process.o ptrace.o setup.o signal.o \
+ sys.o stacktrace.o time.o traps.o io.o vdso.o \
+- hyp-stub.o psci.o
++ hyp-stub.o psci.o cpu_ops.o
+
+ arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
+ sys_compat.o
+ arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o
+-arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o smp_psci.o
++arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o
+ arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
+ arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o
+ arm64-obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
++arm64-obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o
+
+ obj-y += $(arm64-obj-y) vdso/
+ obj-m += $(arm64-obj-m)
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/process.c linux-linaro-stable-mx6/arch/arm64/kernel/process.c
+--- linux-3.10.30.orig/arch/arm64/kernel/process.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/process.c 2014-05-15 20:33:37.717867670 +0200
+@@ -102,6 +102,13 @@
+ local_irq_enable();
+ }
+
++#ifdef CONFIG_HOTPLUG_CPU
++void arch_cpu_idle_dead(void)
++{
++ cpu_die();
++}
++#endif
++
+ void machine_shutdown(void)
+ {
+ #ifdef CONFIG_SMP
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/psci.c linux-linaro-stable-mx6/arch/arm64/kernel/psci.c
+--- linux-3.10.30.orig/arch/arm64/kernel/psci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/psci.c 2014-05-15 20:33:37.717867670 +0200
+@@ -17,12 +17,32 @@
+
+ #include <linux/init.h>
+ #include <linux/of.h>
++#include <linux/smp.h>
+
+ #include <asm/compiler.h>
++#include <asm/cpu_ops.h>
+ #include <asm/errno.h>
+ #include <asm/psci.h>
++#include <asm/smp_plat.h>
+
+-struct psci_operations psci_ops;
++#define PSCI_POWER_STATE_TYPE_STANDBY 0
++#define PSCI_POWER_STATE_TYPE_POWER_DOWN 1
++
++struct psci_power_state {
++ u16 id;
++ u8 type;
++ u8 affinity_level;
++};
++
++struct psci_operations {
++ int (*cpu_suspend)(struct psci_power_state state,
++ unsigned long entry_point);
++ int (*cpu_off)(struct psci_power_state state);
++ int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
++ int (*migrate)(unsigned long cpuid);
++};
++
++static struct psci_operations psci_ops;
+
+ static int (*invoke_psci_fn)(u64, u64, u64, u64);
+
+@@ -209,3 +229,68 @@
+ of_node_put(np);
+ return err;
+ }
++
++#ifdef CONFIG_SMP
++
++static int __init cpu_psci_cpu_init(struct device_node *dn, unsigned int cpu)
++{
++ return 0;
++}
++
++static int __init cpu_psci_cpu_prepare(unsigned int cpu)
++{
++ if (!psci_ops.cpu_on) {
++ pr_err("no cpu_on method, not booting CPU%d\n", cpu);
++ return -ENODEV;
++ }
++
++ return 0;
++}
++
++static int cpu_psci_cpu_boot(unsigned int cpu)
++{
++ int err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa(secondary_entry));
++ if (err)
++ pr_err("psci: failed to boot CPU%d (%d)\n", cpu, err);
++
++ return err;
++}
++
++#ifdef CONFIG_HOTPLUG_CPU
++static int cpu_psci_cpu_disable(unsigned int cpu)
++{
++ /* Fail early if we don't have CPU_OFF support */
++ if (!psci_ops.cpu_off)
++ return -EOPNOTSUPP;
++ return 0;
++}
++
++static void cpu_psci_cpu_die(unsigned int cpu)
++{
++ int ret;
++ /*
++ * There are no known implementations of PSCI actually using the
++ * power state field, pass a sensible default for now.
++ */
++ struct psci_power_state state = {
++ .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
++ };
++
++ ret = psci_ops.cpu_off(state);
++
++ pr_crit("psci: unable to power off CPU%u (%d)\n", cpu, ret);
++}
++#endif
++
++const struct cpu_operations cpu_psci_ops = {
++ .name = "psci",
++ .cpu_init = cpu_psci_cpu_init,
++ .cpu_prepare = cpu_psci_cpu_prepare,
++ .cpu_boot = cpu_psci_cpu_boot,
++#ifdef CONFIG_HOTPLUG_CPU
++ .cpu_disable = cpu_psci_cpu_disable,
++ .cpu_die = cpu_psci_cpu_die,
++#endif
++};
++
++#endif
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/setup.c linux-linaro-stable-mx6/arch/arm64/kernel/setup.c
+--- linux-3.10.30.orig/arch/arm64/kernel/setup.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/setup.c 2014-05-15 20:33:37.717867670 +0200
+@@ -45,6 +45,7 @@
+ #include <asm/cputype.h>
+ #include <asm/elf.h>
+ #include <asm/cputable.h>
++#include <asm/cpu_ops.h>
+ #include <asm/sections.h>
+ #include <asm/setup.h>
+ #include <asm/smp_plat.h>
+@@ -97,6 +98,11 @@
+ printk("%s", buf);
+ }
+
++bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
++{
++ return phys_id == cpu_logical_map(cpu);
++}
++
+ static void __init setup_processor(void)
+ {
+ struct cpu_info *cpu_info;
+@@ -269,6 +275,7 @@
+ psci_init();
+
+ cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
++ cpu_read_bootcpu_ops();
+ #ifdef CONFIG_SMP
+ smp_init_cpus();
+ #endif
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/smp.c linux-linaro-stable-mx6/arch/arm64/kernel/smp.c
+--- linux-3.10.30.orig/arch/arm64/kernel/smp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/smp.c 2014-05-15 20:33:37.717867670 +0200
+@@ -39,6 +39,7 @@
+ #include <asm/atomic.h>
+ #include <asm/cacheflush.h>
+ #include <asm/cputype.h>
++#include <asm/cpu_ops.h>
+ #include <asm/mmu_context.h>
+ #include <asm/pgtable.h>
+ #include <asm/pgalloc.h>
+@@ -48,13 +49,15 @@
+ #include <asm/tlbflush.h>
+ #include <asm/ptrace.h>
+
++#define CREATE_TRACE_POINTS
++#include <trace/events/arm-ipi.h>
++
+ /*
+ * as from 2.5, kernels no longer have an init_tasks structure
+ * so we need some other way of telling a new secondary core
+ * where to place its SVC stack
+ */
+ struct secondary_data secondary_data;
+-volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
+
+ enum ipi_msg_type {
+ IPI_RESCHEDULE,
+@@ -63,61 +66,16 @@
+ IPI_CPU_STOP,
+ };
+
+-static DEFINE_RAW_SPINLOCK(boot_lock);
+-
+-/*
+- * Write secondary_holding_pen_release in a way that is guaranteed to be
+- * visible to all observers, irrespective of whether they're taking part
+- * in coherency or not. This is necessary for the hotplug code to work
+- * reliably.
+- */
+-static void __cpuinit write_pen_release(u64 val)
+-{
+- void *start = (void *)&secondary_holding_pen_release;
+- unsigned long size = sizeof(secondary_holding_pen_release);
+-
+- secondary_holding_pen_release = val;
+- __flush_dcache_area(start, size);
+-}
+-
+ /*
+ * Boot a secondary CPU, and assign it the specified idle task.
+ * This also gives us the initial stack to use for this CPU.
+ */
+ static int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+ {
+- unsigned long timeout;
+-
+- /*
+- * Set synchronisation state between this boot processor
+- * and the secondary one
+- */
+- raw_spin_lock(&boot_lock);
+-
+- /*
+- * Update the pen release flag.
+- */
+- write_pen_release(cpu_logical_map(cpu));
+-
+- /*
+- * Send an event, causing the secondaries to read pen_release.
+- */
+- sev();
+-
+- timeout = jiffies + (1 * HZ);
+- while (time_before(jiffies, timeout)) {
+- if (secondary_holding_pen_release == INVALID_HWID)
+- break;
+- udelay(10);
+- }
++ if (cpu_ops[cpu]->cpu_boot)
++ return cpu_ops[cpu]->cpu_boot(cpu);
+
+- /*
+- * Now the secondary core is starting up let it run its
+- * calibrations, then wait for it to finish
+- */
+- raw_spin_unlock(&boot_lock);
+-
+- return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
++ return -EOPNOTSUPP;
+ }
+
+ static DECLARE_COMPLETION(cpu_running);
+@@ -158,6 +116,11 @@
+ return ret;
+ }
+
++static void __cpuinit smp_store_cpu_info(unsigned int cpuid)
++{
++ store_cpu_topology(cpuid);
++}
++
+ /*
+ * This is the secondary CPU boot entry. We're using this CPUs
+ * idle thread stack, but a set of temporary page tables.
+@@ -187,17 +150,15 @@
+ preempt_disable();
+ trace_hardirqs_off();
+
+- /*
+- * Let the primary processor know we're out of the
+- * pen, then head off into the C entry point
+- */
+- write_pen_release(INVALID_HWID);
++ if (cpu_ops[cpu]->cpu_postboot)
++ cpu_ops[cpu]->cpu_postboot();
++
++ smp_store_cpu_info(cpu);
+
+ /*
+- * Synchronise with the boot thread.
++ * Enable GIC and timers.
+ */
+- raw_spin_lock(&boot_lock);
+- raw_spin_unlock(&boot_lock);
++ notify_cpu_starting(cpu);
+
+ /*
+ * OK, now it's safe to let the boot CPU continue. Wait for
+@@ -207,11 +168,6 @@
+ set_cpu_online(cpu, true);
+ complete(&cpu_running);
+
+- /*
+- * Enable GIC and timers.
+- */
+- notify_cpu_starting(cpu);
+-
+ local_irq_enable();
+ local_fiq_enable();
+
+@@ -221,43 +177,117 @@
+ cpu_startup_entry(CPUHP_ONLINE);
+ }
+
+-void __init smp_cpus_done(unsigned int max_cpus)
++#ifdef CONFIG_HOTPLUG_CPU
++static int op_cpu_disable(unsigned int cpu)
+ {
+- unsigned long bogosum = loops_per_jiffy * num_online_cpus();
++ /*
++ * If we don't have a cpu_die method, abort before we reach the point
++ * of no return. CPU0 may not have an cpu_ops, so test for it.
++ */
++ if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die)
++ return -EOPNOTSUPP;
+
+- pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
+- num_online_cpus(), bogosum / (500000/HZ),
+- (bogosum / (5000/HZ)) % 100);
++ /*
++ * We may need to abort a hot unplug for some other mechanism-specific
++ * reason.
++ */
++ if (cpu_ops[cpu]->cpu_disable)
++ return cpu_ops[cpu]->cpu_disable(cpu);
++
++ return 0;
+ }
+
+-void __init smp_prepare_boot_cpu(void)
++/*
++ * __cpu_disable runs on the processor to be shutdown.
++ */
++int __cpu_disable(void)
+ {
+-}
++ unsigned int cpu = smp_processor_id();
++ int ret;
+
+-static void (*smp_cross_call)(const struct cpumask *, unsigned int);
++ ret = op_cpu_disable(cpu);
++ if (ret)
++ return ret;
+
+-static const struct smp_enable_ops *enable_ops[] __initconst = {
+- &smp_spin_table_ops,
+- &smp_psci_ops,
+- NULL,
+-};
++ /*
++ * Take this CPU offline. Once we clear this, we can't return,
++ * and we must not schedule until we're ready to give up the cpu.
++ */
++ set_cpu_online(cpu, false);
+
+-static const struct smp_enable_ops *smp_enable_ops[NR_CPUS];
++ /*
++ * OK - migrate IRQs away from this CPU
++ */
++ migrate_irqs();
+
+-static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name)
+-{
+- const struct smp_enable_ops **ops = enable_ops;
++ /*
++ * Remove this CPU from the vm mask set of all processes.
++ */
++ clear_tasks_mm_cpumask(cpu);
++
++ return 0;
++}
+
+- while (*ops) {
+- if (!strcmp(name, (*ops)->name))
+- return *ops;
++static DECLARE_COMPLETION(cpu_died);
+
+- ops++;
++/*
++ * called on the thread which is asking for a CPU to be shutdown -
++ * waits until shutdown has completed, or it is timed out.
++ */
++void __cpu_die(unsigned int cpu)
++{
++ if (!wait_for_completion_timeout(&cpu_died, msecs_to_jiffies(5000))) {
++ pr_crit("CPU%u: cpu didn't die\n", cpu);
++ return;
+ }
++ pr_notice("CPU%u: shutdown\n", cpu);
++}
++
++/*
++ * Called from the idle thread for the CPU which has been shutdown.
++ *
++ * Note that we disable IRQs here, but do not re-enable them
++ * before returning to the caller. This is also the behaviour
++ * of the other hotplug-cpu capable cores, so presumably coming
++ * out of idle fixes this.
++ */
++void cpu_die(void)
++{
++ unsigned int cpu = smp_processor_id();
++
++ idle_task_exit();
++
++ local_irq_disable();
++
++ /* Tell __cpu_die() that this CPU is now safe to dispose of */
++ complete(&cpu_died);
++
++ /*
++ * Actually shutdown the CPU. This must never fail. The specific hotplug
++ * mechanism must perform all required cache maintenance to ensure that
++ * no dirty lines are lost in the process of shutting down the CPU.
++ */
++ cpu_ops[cpu]->cpu_die(cpu);
++
++ BUG();
++}
++#endif
++
++void __init smp_cpus_done(unsigned int max_cpus)
++{
++ unsigned long bogosum = loops_per_jiffy * num_online_cpus();
+
+- return NULL;
++ pr_info("SMP: Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
++ num_online_cpus(), bogosum / (500000/HZ),
++ (bogosum / (5000/HZ)) % 100);
++}
++
++void __init smp_prepare_boot_cpu(void)
++{
+ }
+
++static void (*smp_cross_call)(const struct cpumask *, unsigned int);
++
+ /*
+ * Enumerate the possible CPU set from the device tree and build the
+ * cpu logical map array containing MPIDR values related to logical
+@@ -265,9 +295,8 @@
+ */
+ void __init smp_init_cpus(void)
+ {
+- const char *enable_method;
+ struct device_node *dn = NULL;
+- int i, cpu = 1;
++ unsigned int i, cpu = 1;
+ bool bootcpu_valid = false;
+
+ while ((dn = of_find_node_by_type(dn, "cpu"))) {
+@@ -336,25 +365,10 @@
+ if (cpu >= NR_CPUS)
+ goto next;
+
+- /*
+- * We currently support only the "spin-table" enable-method.
+- */
+- enable_method = of_get_property(dn, "enable-method", NULL);
+- if (!enable_method) {
+- pr_err("%s: missing enable-method property\n",
+- dn->full_name);
++ if (cpu_read_ops(dn, cpu) != 0)
+ goto next;
+- }
+-
+- smp_enable_ops[cpu] = smp_get_enable_ops(enable_method);
+
+- if (!smp_enable_ops[cpu]) {
+- pr_err("%s: invalid enable-method property: %s\n",
+- dn->full_name, enable_method);
+- goto next;
+- }
+-
+- if (smp_enable_ops[cpu]->init_cpu(dn, cpu))
++ if (cpu_ops[cpu]->cpu_init(dn, cpu))
+ goto next;
+
+ pr_debug("cpu logical map 0x%llx\n", hwid);
+@@ -384,8 +398,13 @@
+
+ void __init smp_prepare_cpus(unsigned int max_cpus)
+ {
+- int cpu, err;
+- unsigned int ncores = num_possible_cpus();
++ int err;
++ unsigned int cpu, ncores = num_possible_cpus();
++
++ init_cpu_topology();
++
++ smp_store_cpu_info(smp_processor_id());
++
+
+ /*
+ * are we trying to boot more cores than exist?
+@@ -412,10 +431,10 @@
+ if (cpu == smp_processor_id())
+ continue;
+
+- if (!smp_enable_ops[cpu])
++ if (!cpu_ops[cpu])
+ continue;
+
+- err = smp_enable_ops[cpu]->prepare_cpu(cpu);
++ err = cpu_ops[cpu]->cpu_prepare(cpu);
+ if (err)
+ continue;
+
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/smp_psci.c linux-linaro-stable-mx6/arch/arm64/kernel/smp_psci.c
+--- linux-3.10.30.orig/arch/arm64/kernel/smp_psci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/smp_psci.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,53 +0,0 @@
+-/*
+- * PSCI SMP initialisation
+- *
+- * Copyright (C) 2013 ARM Ltd.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License
+- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+- */
+-
+-#include <linux/init.h>
+-#include <linux/of.h>
+-#include <linux/smp.h>
+-
+-#include <asm/psci.h>
+-#include <asm/smp_plat.h>
+-
+-static int __init smp_psci_init_cpu(struct device_node *dn, int cpu)
+-{
+- return 0;
+-}
+-
+-static int __init smp_psci_prepare_cpu(int cpu)
+-{
+- int err;
+-
+- if (!psci_ops.cpu_on) {
+- pr_err("psci: no cpu_on method, not booting CPU%d\n", cpu);
+- return -ENODEV;
+- }
+-
+- err = psci_ops.cpu_on(cpu_logical_map(cpu), __pa(secondary_holding_pen));
+- if (err) {
+- pr_err("psci: failed to boot CPU%d (%d)\n", cpu, err);
+- return err;
+- }
+-
+- return 0;
+-}
+-
+-const struct smp_enable_ops smp_psci_ops __initconst = {
+- .name = "psci",
+- .init_cpu = smp_psci_init_cpu,
+- .prepare_cpu = smp_psci_prepare_cpu,
+-};
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/smp_spin_table.c linux-linaro-stable-mx6/arch/arm64/kernel/smp_spin_table.c
+--- linux-3.10.30.orig/arch/arm64/kernel/smp_spin_table.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/smp_spin_table.c 2014-05-15 20:33:37.717867670 +0200
+@@ -16,15 +16,39 @@
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
++#include <linux/delay.h>
+ #include <linux/init.h>
+ #include <linux/of.h>
+ #include <linux/smp.h>
+
+ #include <asm/cacheflush.h>
++#include <asm/cpu_ops.h>
++#include <asm/cputype.h>
++#include <asm/smp_plat.h>
++
++extern void secondary_holding_pen(void);
++volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
+
+ static phys_addr_t cpu_release_addr[NR_CPUS];
++static DEFINE_RAW_SPINLOCK(boot_lock);
+
+-static int __init smp_spin_table_init_cpu(struct device_node *dn, int cpu)
++/*
++ * Write secondary_holding_pen_release in a way that is guaranteed to be
++ * visible to all observers, irrespective of whether they're taking part
++ * in coherency or not. This is necessary for the hotplug code to work
++ * reliably.
++ */
++static void write_pen_release(u64 val)
++{
++ void *start = (void *)&secondary_holding_pen_release;
++ unsigned long size = sizeof(secondary_holding_pen_release);
++
++ secondary_holding_pen_release = val;
++ __flush_dcache_area(start, size);
++}
++
++
++static int smp_spin_table_cpu_init(struct device_node *dn, unsigned int cpu)
+ {
+ /*
+ * Determine the address from which the CPU is polling.
+@@ -40,7 +64,7 @@
+ return 0;
+ }
+
+-static int __init smp_spin_table_prepare_cpu(int cpu)
++static int smp_spin_table_cpu_prepare(unsigned int cpu)
+ {
+ void **release_addr;
+
+@@ -59,8 +83,60 @@
+ return 0;
+ }
+
+-const struct smp_enable_ops smp_spin_table_ops __initconst = {
++static int smp_spin_table_cpu_boot(unsigned int cpu)
++{
++ unsigned long timeout;
++
++ /*
++ * Set synchronisation state between this boot processor
++ * and the secondary one
++ */
++ raw_spin_lock(&boot_lock);
++
++ /*
++ * Update the pen release flag.
++ */
++ write_pen_release(cpu_logical_map(cpu));
++
++ /*
++ * Send an event, causing the secondaries to read pen_release.
++ */
++ sev();
++
++ timeout = jiffies + (1 * HZ);
++ while (time_before(jiffies, timeout)) {
++ if (secondary_holding_pen_release == INVALID_HWID)
++ break;
++ udelay(10);
++ }
++
++ /*
++ * Now the secondary core is starting up let it run its
++ * calibrations, then wait for it to finish
++ */
++ raw_spin_unlock(&boot_lock);
++
++ return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
++}
++
++void smp_spin_table_cpu_postboot(void)
++{
++ /*
++ * Let the primary processor know we're out of the pen.
++ */
++ write_pen_release(INVALID_HWID);
++
++ /*
++ * Synchronise with the boot thread.
++ */
++ raw_spin_lock(&boot_lock);
++ raw_spin_unlock(&boot_lock);
++}
++
++const struct cpu_operations smp_spin_table_ops = {
+ .name = "spin-table",
+- .init_cpu = smp_spin_table_init_cpu,
+- .prepare_cpu = smp_spin_table_prepare_cpu,
++ .cpu_init = smp_spin_table_cpu_init,
++ .cpu_prepare = smp_spin_table_cpu_prepare,
++ .cpu_boot = smp_spin_table_cpu_boot,
++ .cpu_postboot = smp_spin_table_cpu_postboot,
+ };
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/topology.c linux-linaro-stable-mx6/arch/arm64/kernel/topology.c
+--- linux-3.10.30.orig/arch/arm64/kernel/topology.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/topology.c 2014-05-15 20:33:37.717867670 +0200
+@@ -0,0 +1,537 @@
++/*
++ * arch/arm64/kernel/topology.c
++ *
++ * Copyright (C) 2011,2013 Linaro Limited.
++ * Written by: Vincent Guittot
++ *
++ * based on arch/sh/kernel/topology.c
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file "COPYING" in the main directory of this archive
++ * for more details.
++ */
++
++#include <linux/cpu.h>
++#include <linux/cpumask.h>
++#include <linux/export.h>
++#include <linux/init.h>
++#include <linux/percpu.h>
++#include <linux/node.h>
++#include <linux/nodemask.h>
++#include <linux/of.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++
++#include <asm/cputype.h>
++#include <asm/smp_plat.h>
++#include <asm/topology.h>
++
++/*
++ * cpu power scale management
++ */
++
++/*
++ * cpu power table
++ * This per cpu data structure describes the relative capacity of each core.
++ * On a heteregenous system, cores don't have the same computation capacity
++ * and we reflect that difference in the cpu_power field so the scheduler can
++ * take this difference into account during load balance. A per cpu structure
++ * is preferred because each CPU updates its own cpu_power field during the
++ * load balance except for idle cores. One idle core is selected to run the
++ * rebalance_domains for all idle cores and the cpu_power can be updated
++ * during this sequence.
++ */
++static DEFINE_PER_CPU(unsigned long, cpu_scale);
++
++unsigned long arch_scale_freq_power(struct sched_domain *sd, int cpu)
++{
++ return per_cpu(cpu_scale, cpu);
++}
++
++static void set_power_scale(unsigned int cpu, unsigned long power)
++{
++ per_cpu(cpu_scale, cpu) = power;
++}
++
++#ifdef CONFIG_OF
++struct cpu_efficiency {
++ const char *compatible;
++ unsigned long efficiency;
++};
++
++/*
++ * Table of relative efficiency of each processors
++ * The efficiency value must fit in 20bit and the final
++ * cpu_scale value must be in the range
++ * 0 < cpu_scale < 3*SCHED_POWER_SCALE/2
++ * in order to return at most 1 when DIV_ROUND_CLOSEST
++ * is used to compute the capacity of a CPU.
++ * Processors that are not defined in the table,
++ * use the default SCHED_POWER_SCALE value for cpu_scale.
++ */
++static const struct cpu_efficiency table_efficiency[] = {
++ { "arm,cortex-a57", 3891 },
++ { "arm,cortex-a53", 2048 },
++ { NULL, },
++};
++
++static unsigned long *__cpu_capacity;
++#define cpu_capacity(cpu) __cpu_capacity[cpu]
++
++static unsigned long middle_capacity = 1;
++static int cluster_id;
++
++static int __init get_cpu_for_node(struct device_node *node)
++{
++ struct device_node *cpu_node;
++ int cpu;
++
++ cpu_node = of_parse_phandle(node, "cpu", 0);
++ if (!cpu_node) {
++ pr_crit("%s: Unable to parse CPU phandle\n", node->full_name);
++ return -1;
++ }
++
++ for_each_possible_cpu(cpu) {
++ if (of_get_cpu_node(cpu, NULL) == cpu_node)
++ return cpu;
++ }
++
++ pr_crit("Unable to find CPU node for %s\n", cpu_node->full_name);
++ return -1;
++}
++
++static void __init parse_core(struct device_node *core, int core_id)
++{
++ char name[10];
++ bool leaf = true;
++ int i, cpu;
++ struct device_node *t;
++
++ i = 0;
++ do {
++ snprintf(name, sizeof(name), "thread%d", i);
++ t = of_get_child_by_name(core, name);
++ if (t) {
++ leaf = false;
++ cpu = get_cpu_for_node(t);
++ if (cpu) {
++ pr_info("CPU%d: socket %d core %d thread %d\n",
++ cpu, cluster_id, core_id, i);
++ cpu_topology[cpu].socket_id = cluster_id;
++ cpu_topology[cpu].core_id = core_id;
++ cpu_topology[cpu].thread_id = i;
++ } else {
++ pr_err("%s: Can't get CPU for thread\n",
++ t->full_name);
++ }
++ }
++ i++;
++ } while (t);
++
++ cpu = get_cpu_for_node(core);
++ if (cpu >= 0) {
++ if (!leaf) {
++ pr_err("%s: Core has both threads and CPU\n",
++ core->full_name);
++ return;
++ }
++
++ pr_info("CPU%d: socket %d core %d\n",
++ cpu, cluster_id, core_id);
++ cpu_topology[cpu].socket_id = cluster_id;
++ cpu_topology[cpu].core_id = core_id;
++ } else if (leaf) {
++ pr_err("%s: Can't get CPU for leaf core\n", core->full_name);
++ }
++}
++
++static void __init parse_cluster(struct device_node *cluster)
++{
++ char name[10];
++ bool leaf = true;
++ bool has_cores = false;
++ struct device_node *c;
++ int core_id = 0;
++ int i;
++
++ /*
++ * First check for child clusters; we currently ignore any
++ * information about the nesting of clusters and present the
++ * scheduler with a flat list of them.
++ */
++ i = 0;
++ do {
++ snprintf(name, sizeof(name), "cluster%d", i);
++ c = of_get_child_by_name(cluster, name);
++ if (c) {
++ parse_cluster(c);
++ leaf = false;
++ }
++ i++;
++ } while (c);
++
++ /* Now check for cores */
++ i = 0;
++ do {
++ snprintf(name, sizeof(name), "core%d", i);
++ c = of_get_child_by_name(cluster, name);
++ if (c) {
++ has_cores = true;
++
++ if (leaf)
++ parse_core(c, core_id++);
++ else
++ pr_err("%s: Non-leaf cluster with core %s\n",
++ cluster->full_name, name);
++ }
++ i++;
++ } while (c);
++
++ if (leaf && !has_cores)
++ pr_warn("%s: empty cluster\n", cluster->full_name);
++
++ if (leaf)
++ cluster_id++;
++}
++
++/*
++ * Iterate all CPUs' descriptor in DT and compute the efficiency
++ * (as per table_efficiency). Also calculate a middle efficiency
++ * as close as possible to (max{eff_i} - min{eff_i}) / 2
++ * This is later used to scale the cpu_power field such that an
++ * 'average' CPU is of middle power. Also see the comments near
++ * table_efficiency[] and update_cpu_power().
++ */
++static void __init parse_dt_topology(void)
++{
++ const struct cpu_efficiency *cpu_eff;
++ struct device_node *cn = NULL;
++ unsigned long min_capacity = (unsigned long)(-1);
++ unsigned long max_capacity = 0;
++ unsigned long capacity = 0;
++ int alloc_size, cpu;
++
++ alloc_size = nr_cpu_ids * sizeof(*__cpu_capacity);
++ __cpu_capacity = kzalloc(alloc_size, GFP_NOWAIT);
++
++ cn = of_find_node_by_path("/cpus");
++ if (!cn) {
++ pr_err("No CPU information found in DT\n");
++ return;
++ }
++
++ /*
++ * If topology is provided as a cpu-map it is essentially a
++ * root cluster.
++ */
++ cn = of_find_node_by_name(cn, "cpu-map");
++ if (!cn)
++ return;
++ parse_cluster(cn);
++
++ for_each_possible_cpu(cpu) {
++ const u32 *rate;
++ int len;
++
++ /* Too early to use cpu->of_node */
++ cn = of_get_cpu_node(cpu, NULL);
++ if (!cn) {
++ pr_err("Missing device node for CPU %d\n", cpu);
++ continue;
++ }
++
++ /* check if the cpu is marked as "disabled", if so ignore */
++ if (!of_device_is_available(cn))
++ continue;
++
++ for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)
++ if (of_device_is_compatible(cn, cpu_eff->compatible))
++ break;
++
++ if (cpu_eff->compatible == NULL) {
++ pr_warn("%s: Unknown CPU type\n", cn->full_name);
++ continue;
++ }
++
++ rate = of_get_property(cn, "clock-frequency", &len);
++ if (!rate || len != 4) {
++ pr_err("%s: Missing clock-frequency property\n",
++ cn->full_name);
++ continue;
++ }
++
++ capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;
++
++ /* Save min capacity of the system */
++ if (capacity < min_capacity)
++ min_capacity = capacity;
++
++ /* Save max capacity of the system */
++ if (capacity > max_capacity)
++ max_capacity = capacity;
++
++ cpu_capacity(cpu) = capacity;
++ }
++
++ /* If min and max capacities are equal we bypass the update of the
++ * cpu_scale because all CPUs have the same capacity. Otherwise, we
++ * compute a middle_capacity factor that will ensure that the capacity
++ * of an 'average' CPU of the system will be as close as possible to
++ * SCHED_POWER_SCALE, which is the default value, but with the
++ * constraint explained near table_efficiency[].
++ */
++ if (min_capacity == max_capacity)
++ return;
++ else if (4 * max_capacity < (3 * (max_capacity + min_capacity)))
++ middle_capacity = (min_capacity + max_capacity)
++ >> (SCHED_POWER_SHIFT+1);
++ else
++ middle_capacity = ((max_capacity / 3)
++ >> (SCHED_POWER_SHIFT-1)) + 1;
++
++}
++
++/*
++ * Look for a customed capacity of a CPU in the cpu_topo_data table during the
++ * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
++ * function returns directly for SMP system.
++ */
++static void update_cpu_power(unsigned int cpu)
++{
++ if (!cpu_capacity(cpu))
++ return;
++
++ set_power_scale(cpu, cpu_capacity(cpu) / middle_capacity);
++
++ pr_info("CPU%u: update cpu_power %lu\n",
++ cpu, arch_scale_freq_power(NULL, cpu));
++}
++
++#else
++static inline void parse_dt_topology(void) {}
++static inline void update_cpu_power(unsigned int cpuid) {}
++#endif
++
++/*
++ * cpu topology table
++ */
++struct cputopo_arm cpu_topology[NR_CPUS];
++EXPORT_SYMBOL_GPL(cpu_topology);
++
++const struct cpumask *cpu_coregroup_mask(int cpu)
++{
++ return &cpu_topology[cpu].core_sibling;
++}
++
++static void update_siblings_masks(unsigned int cpuid)
++{
++ struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
++ int cpu;
++
++ /* update core and thread sibling masks */
++ for_each_possible_cpu(cpu) {
++ cpu_topo = &cpu_topology[cpu];
++
++ if (cpuid_topo->socket_id != cpu_topo->socket_id)
++ continue;
++
++ cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
++ if (cpu != cpuid)
++ cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
++
++ if (cpuid_topo->core_id != cpu_topo->core_id)
++ continue;
++
++ cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
++ if (cpu != cpuid)
++ cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
++ }
++ smp_wmb();
++}
++
++void store_cpu_topology(unsigned int cpuid)
++{
++ struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
++
++ /* DT should have been parsed by the time we get here */
++ if (cpuid_topo->core_id == -1)
++ pr_info("CPU%u: No topology information configured\n", cpuid);
++ else
++ update_siblings_masks(cpuid);
++
++ update_cpu_power(cpuid);
++}
++
++#ifdef CONFIG_SCHED_HMP
++
++/*
++ * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
++ * - mpidr: MPIDR[23:0] to be used for the look-up
++ *
++ * Returns the cpu logical index or -EINVAL on look-up error
++ */
++static inline int get_logical_index(u32 mpidr)
++{
++ int cpu;
++ for (cpu = 0; cpu < nr_cpu_ids; cpu++)
++ if (cpu_logical_map(cpu) == mpidr)
++ return cpu;
++ return -EINVAL;
++}
++
++static const char * const little_cores[] = {
++ "arm,cortex-a53",
++ NULL,
++};
++
++static bool is_little_cpu(struct device_node *cn)
++{
++ const char * const *lc;
++ for (lc = little_cores; *lc; lc++)
++ if (of_device_is_compatible(cn, *lc))
++ return true;
++ return false;
++}
++
++void __init arch_get_fast_and_slow_cpus(struct cpumask *fast,
++ struct cpumask *slow)
++{
++ struct device_node *cn = NULL;
++ int cpu;
++
++ cpumask_clear(fast);
++ cpumask_clear(slow);
++
++ /*
++ * Use the config options if they are given. This helps testing
++ * HMP scheduling on systems without a big.LITTLE architecture.
++ */
++ if (strlen(CONFIG_HMP_FAST_CPU_MASK) && strlen(CONFIG_HMP_SLOW_CPU_MASK)) {
++ if (cpulist_parse(CONFIG_HMP_FAST_CPU_MASK, fast))
++ WARN(1, "Failed to parse HMP fast cpu mask!\n");
++ if (cpulist_parse(CONFIG_HMP_SLOW_CPU_MASK, slow))
++ WARN(1, "Failed to parse HMP slow cpu mask!\n");
++ return;
++ }
++
++ /*
++ * Else, parse device tree for little cores.
++ */
++ while ((cn = of_find_node_by_type(cn, "cpu"))) {
++
++ const u32 *mpidr;
++ int len;
++
++ mpidr = of_get_property(cn, "reg", &len);
++ if (!mpidr || len != 8) {
++ pr_err("%s missing reg property\n", cn->full_name);
++ continue;
++ }
++
++ cpu = get_logical_index(be32_to_cpup(mpidr+1));
++ if (cpu == -EINVAL) {
++ pr_err("couldn't get logical index for mpidr %x\n",
++ be32_to_cpup(mpidr+1));
++ break;
++ }
++
++ if (is_little_cpu(cn))
++ cpumask_set_cpu(cpu, slow);
++ else
++ cpumask_set_cpu(cpu, fast);
++ }
++
++ if (!cpumask_empty(fast) && !cpumask_empty(slow))
++ return;
++
++ /*
++ * We didn't find both big and little cores so let's call all cores
++ * fast as this will keep the system running, with all cores being
++ * treated equal.
++ */
++ cpumask_setall(fast);
++ cpumask_clear(slow);
++}
++
++struct cpumask hmp_slow_cpu_mask;
++
++void __init arch_get_hmp_domains(struct list_head *hmp_domains_list)
++{
++ struct cpumask hmp_fast_cpu_mask;
++ struct hmp_domain *domain;
++
++ arch_get_fast_and_slow_cpus(&hmp_fast_cpu_mask, &hmp_slow_cpu_mask);
++
++ /*
++ * Initialize hmp_domains
++ * Must be ordered with respect to compute capacity.
++ * Fastest domain at head of list.
++ */
++ if(!cpumask_empty(&hmp_slow_cpu_mask)) {
++ domain = (struct hmp_domain *)
++ kmalloc(sizeof(struct hmp_domain), GFP_KERNEL);
++ cpumask_copy(&domain->possible_cpus, &hmp_slow_cpu_mask);
++ cpumask_and(&domain->cpus, cpu_online_mask, &domain->possible_cpus);
++ list_add(&domain->hmp_domains, hmp_domains_list);
++ }
++ domain = (struct hmp_domain *)
++ kmalloc(sizeof(struct hmp_domain), GFP_KERNEL);
++ cpumask_copy(&domain->possible_cpus, &hmp_fast_cpu_mask);
++ cpumask_and(&domain->cpus, cpu_online_mask, &domain->possible_cpus);
++ list_add(&domain->hmp_domains, hmp_domains_list);
++}
++#endif /* CONFIG_SCHED_HMP */
++
++/*
++ * cluster_to_logical_mask - return cpu logical mask of CPUs in a cluster
++ * @socket_id: cluster HW identifier
++ * @cluster_mask: the cpumask location to be initialized, modified by the
++ * function only if return value == 0
++ *
++ * Return:
++ *
++ * 0 on success
++ * -EINVAL if cluster_mask is NULL or there is no record matching socket_id
++ */
++int cluster_to_logical_mask(unsigned int socket_id, cpumask_t *cluster_mask)
++{
++ int cpu;
++
++ if (!cluster_mask)
++ return -EINVAL;
++
++ for_each_online_cpu(cpu) {
++ if (socket_id == topology_physical_package_id(cpu)) {
++ cpumask_copy(cluster_mask, topology_core_cpumask(cpu));
++ return 0;
++ }
++ }
++
++ return -EINVAL;
++}
++
++/*
++ * init_cpu_topology is called at boot when only one cpu is running
++ * which prevent simultaneous write access to cpu_topology array
++ */
++void __init init_cpu_topology(void)
++{
++ unsigned int cpu;
++
++ /* init core mask and power*/
++ for_each_possible_cpu(cpu) {
++ struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);
++
++ cpu_topo->thread_id = -1;
++ cpu_topo->core_id = -1;
++ cpu_topo->socket_id = -1;
++ cpumask_clear(&cpu_topo->core_sibling);
++ cpumask_clear(&cpu_topo->thread_sibling);
++
++ set_power_scale(cpu, SCHED_POWER_SCALE);
++ }
++ smp_wmb();
++
++ parse_dt_topology();
++}
+diff -Nur linux-3.10.30.orig/arch/arm64/kernel/vmlinux.lds.S linux-linaro-stable-mx6/arch/arm64/kernel/vmlinux.lds.S
+--- linux-3.10.30.orig/arch/arm64/kernel/vmlinux.lds.S 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/arm64/kernel/vmlinux.lds.S 2014-05-15 20:33:37.721867699 +0200
+@@ -41,7 +41,6 @@
+ }
+ .text : { /* Real text segment */
+ _stext = .; /* Text and read-only data */
+- *(.smp.pen.text)
+ __exception_text_start = .;
+ *(.exception.text)
+ __exception_text_end = .;
+diff -Nur linux-3.10.30.orig/arch/mips/include/asm/pci.h linux-linaro-stable-mx6/arch/mips/include/asm/pci.h
+--- linux-3.10.30.orig/arch/mips/include/asm/pci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/mips/include/asm/pci.h 2014-05-15 20:33:39.817882813 +0200
+@@ -137,11 +137,6 @@
+ return channel ? 15 : 14;
+ }
+
+-#ifdef CONFIG_CPU_CAVIUM_OCTEON
+-/* MSI arch hook for OCTEON */
+-#define arch_setup_msi_irqs arch_setup_msi_irqs
+-#endif
+-
+ extern char * (*pcibios_plat_setup)(char *str);
+
+ #ifdef CONFIG_OF
+diff -Nur linux-3.10.30.orig/arch/powerpc/include/asm/pci.h linux-linaro-stable-mx6/arch/powerpc/include/asm/pci.h
+--- linux-3.10.30.orig/arch/powerpc/include/asm/pci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/powerpc/include/asm/pci.h 2014-05-15 20:33:41.013891438 +0200
+@@ -113,11 +113,6 @@
+ /* Decide whether to display the domain number in /proc */
+ extern int pci_proc_domain(struct pci_bus *bus);
+
+-/* MSI arch hooks */
+-#define arch_setup_msi_irqs arch_setup_msi_irqs
+-#define arch_teardown_msi_irqs arch_teardown_msi_irqs
+-#define arch_msi_check_device arch_msi_check_device
+-
+ struct vm_area_struct;
+ /* Map a range of PCI memory or I/O space for a device into user space */
+ int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
+diff -Nur linux-3.10.30.orig/arch/powerpc/include/asm/prom.h linux-linaro-stable-mx6/arch/powerpc/include/asm/prom.h
+--- linux-3.10.30.orig/arch/powerpc/include/asm/prom.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/powerpc/include/asm/prom.h 2014-05-15 20:33:41.033891582 +0200
+@@ -43,9 +43,6 @@
+
+ extern void kdump_move_device_tree(void);
+
+-/* CPU OF node matching */
+-struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
+-
+ /* cache lookup */
+ struct device_node *of_find_next_cache_node(struct device_node *np);
+
+diff -Nur linux-3.10.30.orig/arch/powerpc/kernel/prom.c linux-linaro-stable-mx6/arch/powerpc/kernel/prom.c
+--- linux-3.10.30.orig/arch/powerpc/kernel/prom.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/powerpc/kernel/prom.c 2014-05-15 20:33:41.437894495 +0200
+@@ -827,49 +827,10 @@
+ __initcall(prom_reconfig_setup);
+ #endif
+
+-/* Find the device node for a given logical cpu number, also returns the cpu
+- * local thread number (index in ibm,interrupt-server#s) if relevant and
+- * asked for (non NULL)
+- */
+-struct device_node *of_get_cpu_node(int cpu, unsigned int *thread)
++bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
+ {
+- int hardid;
+- struct device_node *np;
+-
+- hardid = get_hard_smp_processor_id(cpu);
+-
+- for_each_node_by_type(np, "cpu") {
+- const u32 *intserv;
+- unsigned int plen, t;
+-
+- /* Check for ibm,ppc-interrupt-server#s. If it doesn't exist
+- * fallback to "reg" property and assume no threads
+- */
+- intserv = of_get_property(np, "ibm,ppc-interrupt-server#s",
+- &plen);
+- if (intserv == NULL) {
+- const u32 *reg = of_get_property(np, "reg", NULL);
+- if (reg == NULL)
+- continue;
+- if (*reg == hardid) {
+- if (thread)
+- *thread = 0;
+- return np;
+- }
+- } else {
+- plen /= sizeof(u32);
+- for (t = 0; t < plen; t++) {
+- if (hardid == intserv[t]) {
+- if (thread)
+- *thread = t;
+- return np;
+- }
+- }
+- }
+- }
+- return NULL;
++ return (int)phys_id == get_hard_smp_processor_id(cpu);
+ }
+-EXPORT_SYMBOL(of_get_cpu_node);
+
+ #if defined(CONFIG_DEBUG_FS) && defined(DEBUG)
+ static struct debugfs_blob_wrapper flat_dt_blob;
+diff -Nur linux-3.10.30.orig/arch/s390/include/asm/pci.h linux-linaro-stable-mx6/arch/s390/include/asm/pci.h
+--- linux-3.10.30.orig/arch/s390/include/asm/pci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/s390/include/asm/pci.h 2014-05-15 20:33:42.549902513 +0200
+@@ -21,10 +21,6 @@
+ int pci_domain_nr(struct pci_bus *);
+ int pci_proc_domain(struct pci_bus *);
+
+-/* MSI arch hooks */
+-#define arch_setup_msi_irqs arch_setup_msi_irqs
+-#define arch_teardown_msi_irqs arch_teardown_msi_irqs
+-
+ #define ZPCI_BUS_NR 0 /* default bus number */
+ #define ZPCI_DEVFN 0 /* default device number */
+
+diff -Nur linux-3.10.30.orig/arch/x86/include/asm/pci.h linux-linaro-stable-mx6/arch/x86/include/asm/pci.h
+--- linux-3.10.30.orig/arch/x86/include/asm/pci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/x86/include/asm/pci.h 2014-05-15 20:33:44.465916327 +0200
+@@ -100,29 +100,6 @@
+ extern void pci_iommu_alloc(void);
+
+ #ifdef CONFIG_PCI_MSI
+-/* MSI arch specific hooks */
+-static inline int x86_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+-{
+- return x86_msi.setup_msi_irqs(dev, nvec, type);
+-}
+-
+-static inline void x86_teardown_msi_irqs(struct pci_dev *dev)
+-{
+- x86_msi.teardown_msi_irqs(dev);
+-}
+-
+-static inline void x86_teardown_msi_irq(unsigned int irq)
+-{
+- x86_msi.teardown_msi_irq(irq);
+-}
+-static inline void x86_restore_msi_irqs(struct pci_dev *dev, int irq)
+-{
+- x86_msi.restore_msi_irqs(dev, irq);
+-}
+-#define arch_setup_msi_irqs x86_setup_msi_irqs
+-#define arch_teardown_msi_irqs x86_teardown_msi_irqs
+-#define arch_teardown_msi_irq x86_teardown_msi_irq
+-#define arch_restore_msi_irqs x86_restore_msi_irqs
+ /* implemented in arch/x86/kernel/apic/io_apic. */
+ struct msi_desc;
+ int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
+@@ -130,16 +107,9 @@
+ void native_restore_msi_irqs(struct pci_dev *dev, int irq);
+ int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
+ unsigned int irq_base, unsigned int irq_offset);
+-/* default to the implementation in drivers/lib/msi.c */
+-#define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
+-#define HAVE_DEFAULT_MSI_RESTORE_IRQS
+-void default_teardown_msi_irqs(struct pci_dev *dev);
+-void default_restore_msi_irqs(struct pci_dev *dev, int irq);
+ #else
+ #define native_setup_msi_irqs NULL
+ #define native_teardown_msi_irq NULL
+-#define default_teardown_msi_irqs NULL
+-#define default_restore_msi_irqs NULL
+ #endif
+
+ #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
+diff -Nur linux-3.10.30.orig/arch/x86/kernel/x86_init.c linux-linaro-stable-mx6/arch/x86/kernel/x86_init.c
+--- linux-3.10.30.orig/arch/x86/kernel/x86_init.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/arch/x86/kernel/x86_init.c 2014-05-15 20:33:44.553916962 +0200
+@@ -107,6 +107,8 @@
+ };
+
+ EXPORT_SYMBOL_GPL(x86_platform);
++
++#if defined(CONFIG_PCI_MSI)
+ struct x86_msi_ops x86_msi = {
+ .setup_msi_irqs = native_setup_msi_irqs,
+ .compose_msi_msg = native_compose_msi_msg,
+@@ -116,6 +118,28 @@
+ .setup_hpet_msi = default_setup_hpet_msi,
+ };
+
++/* MSI arch specific hooks */
++int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
++{
++ return x86_msi.setup_msi_irqs(dev, nvec, type);
++}
++
++void arch_teardown_msi_irqs(struct pci_dev *dev)
++{
++ x86_msi.teardown_msi_irqs(dev);
++}
++
++void arch_teardown_msi_irq(unsigned int irq)
++{
++ x86_msi.teardown_msi_irq(irq);
++}
++
++void arch_restore_msi_irqs(struct pci_dev *dev, int irq)
++{
++ x86_msi.restore_msi_irqs(dev, irq);
++}
++#endif
++
+ struct x86_io_apic_ops x86_io_apic_ops = {
+ .init = native_io_apic_init_mappings,
+ .read = native_io_apic_read,
+diff -Nur linux-3.10.30.orig/block/blk-core.c linux-linaro-stable-mx6/block/blk-core.c
+--- linux-3.10.30.orig/block/blk-core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/block/blk-core.c 2014-05-15 20:33:44.881919327 +0200
+@@ -3191,7 +3191,8 @@
+
+ /* used for unplugging and affects IO latency/throughput - HIGHPRI */
+ kblockd_workqueue = alloc_workqueue("kblockd",
+- WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
++ WQ_MEM_RECLAIM | WQ_HIGHPRI |
++ WQ_POWER_EFFICIENT, 0);
+ if (!kblockd_workqueue)
+ panic("Failed to create kblockd\n");
+
+diff -Nur linux-3.10.30.orig/block/blk-ioc.c linux-linaro-stable-mx6/block/blk-ioc.c
+--- linux-3.10.30.orig/block/blk-ioc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/block/blk-ioc.c 2014-05-15 20:33:44.881919327 +0200
+@@ -144,7 +144,8 @@
+ if (atomic_long_dec_and_test(&ioc->refcount)) {
+ spin_lock_irqsave(&ioc->lock, flags);
+ if (!hlist_empty(&ioc->icq_list))
+- schedule_work(&ioc->release_work);
++ queue_work(system_power_efficient_wq,
++ &ioc->release_work);
+ else
+ free_ioc = true;
+ spin_unlock_irqrestore(&ioc->lock, flags);
+diff -Nur linux-3.10.30.orig/block/genhd.c linux-linaro-stable-mx6/block/genhd.c
+--- linux-3.10.30.orig/block/genhd.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/block/genhd.c 2014-05-15 20:33:44.885919355 +0200
+@@ -1489,9 +1489,11 @@
+ intv = disk_events_poll_jiffies(disk);
+ set_timer_slack(&ev->dwork.timer, intv / 4);
+ if (check_now)
+- queue_delayed_work(system_freezable_wq, &ev->dwork, 0);
++ queue_delayed_work(system_freezable_power_efficient_wq,
++ &ev->dwork, 0);
+ else if (intv)
+- queue_delayed_work(system_freezable_wq, &ev->dwork, intv);
++ queue_delayed_work(system_freezable_power_efficient_wq,
++ &ev->dwork, intv);
+ out_unlock:
+ spin_unlock_irqrestore(&ev->lock, flags);
+ }
+@@ -1534,7 +1536,8 @@
+ spin_lock_irq(&ev->lock);
+ ev->clearing |= mask;
+ if (!ev->block)
+- mod_delayed_work(system_freezable_wq, &ev->dwork, 0);
++ mod_delayed_work(system_freezable_power_efficient_wq,
++ &ev->dwork, 0);
+ spin_unlock_irq(&ev->lock);
+ }
+
+@@ -1627,7 +1630,8 @@
+
+ intv = disk_events_poll_jiffies(disk);
+ if (!ev->block && intv)
+- queue_delayed_work(system_freezable_wq, &ev->dwork, intv);
++ queue_delayed_work(system_freezable_power_efficient_wq,
++ &ev->dwork, intv);
+
+ spin_unlock_irq(&ev->lock);
+
+diff -Nur linux-3.10.30.orig/Documentation/ABI/testing/sysfs-class-mtd linux-linaro-stable-mx6/Documentation/ABI/testing/sysfs-class-mtd
+--- linux-3.10.30.orig/Documentation/ABI/testing/sysfs-class-mtd 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/ABI/testing/sysfs-class-mtd 2014-05-15 20:33:31.513822926 +0200
+@@ -104,7 +104,7 @@
+ One of the following ASCII strings, representing the device
+ type:
+
+- absent, ram, rom, nor, nand, dataflash, ubi, unknown
++ absent, ram, rom, nor, nand, mlc-nand, dataflash, ubi, unknown
+
+ What: /sys/class/mtd/mtdX/writesize
+ Date: April 2009
+@@ -128,9 +128,8 @@
+ Contact: linux-mtd@lists.infradead.org
+ Description:
+ Maximum number of bit errors that the device is capable of
+- correcting within each region covering an ecc step. This will
+- always be a non-negative integer. Note that some devices will
+- have multiple ecc steps within each writesize region.
++ correcting within each region covering an ECC step (see
++ ecc_step_size). This will always be a non-negative integer.
+
+ In the case of devices lacking any ECC capability, it is 0.
+
+@@ -173,3 +172,15 @@
+ This is generally applicable only to NAND flash devices with ECC
+ capability. It is ignored on devices lacking ECC capability;
+ i.e., devices for which ecc_strength is zero.
++
++What: /sys/class/mtd/mtdX/ecc_step_size
++Date: May 2013
++KernelVersion: 3.10
++Contact: linux-mtd@lists.infradead.org
++Description:
++ The size of a single region covered by ECC, known as the ECC
++ step. Devices may have several equally sized ECC steps within
++ each writesize region.
++
++ It will always be a non-negative integer. In the case of
++ devices lacking any ECC capability, it is 0.
+diff -Nur linux-3.10.30.orig/Documentation/arm/small_task_packing.txt linux-linaro-stable-mx6/Documentation/arm/small_task_packing.txt
+--- linux-3.10.30.orig/Documentation/arm/small_task_packing.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/arm/small_task_packing.txt 2014-05-15 20:33:31.841825292 +0200
+@@ -0,0 +1,136 @@
++Small Task Packing in the big.LITTLE MP Reference Patch Set
++
++What is small task packing?
++----
++Simply that the scheduler will fit as many small tasks on a single CPU
++as possible before using other CPUs. A small task is defined as one
++whose tracked load is less than 90% of a NICE_0 task. This is a change
++from the usual behavior since the scheduler will normally use an idle
++CPU for a waking task unless that task is considered cache hot.
++
++
++How is it implemented?
++----
++Since all small tasks must wake up relatively frequently, the main
++requirement for packing small tasks is to select a partly-busy CPU when
++waking rather than looking for an idle CPU. We use the tracked load of
++the CPU runqueue to determine how heavily loaded each CPU is and the
++tracked load of the task to determine if it will fit on the CPU. We
++always start with the lowest-numbered CPU in a sched domain and stop
++looking when we find a CPU with enough space for the task.
++
++Some further tweaks are necessary to suppress load balancing when the
++CPU is not fully loaded, otherwise the scheduler attempts to spread
++tasks evenly across the domain.
++
++
++How does it interact with the HMP patches?
++----
++Firstly, we only enable packing on the little domain. The intent is that
++the big domain is intended to spread tasks amongst the available CPUs
++one-task-per-CPU. The little domain however is attempting to use as
++little power as possible while servicing its tasks.
++
++Secondly, since we offload big tasks onto little CPUs in order to try
++to devote one CPU to each task, we have a threshold above which we do
++not try to pack a task and instead will select an idle CPU if possible.
++This maintains maximum forward progress for busy tasks temporarily
++demoted from big CPUs.
++
++
++Can the behaviour be tuned?
++----
++Yes, the load level of a 'full' CPU can be easily modified in the source
++and is exposed through sysfs as /sys/kernel/hmp/packing_limit to be
++changed at runtime. The presence of the packing behaviour is controlled
++by CONFIG_SCHED_HMP_LITTLE_PACKING and can be disabled at run-time
++using /sys/kernel/hmp/packing_enable.
++The definition of a small task is hard coded as 90% of NICE_0_LOAD
++and cannot be modified at run time.
++
++
++Why do I need to tune it?
++----
++The optimal configuration is likely to be different depending upon the
++design and manufacturing of your SoC.
++
++In the main, there are two system effects from enabling small task
++packing.
++
++1. CPU operating point may increase
++2. wakeup latency of tasks may be increased
++
++There are also likely to be secondary effects from loading one CPU
++rather than spreading tasks.
++
++Note that all of these system effects are dependent upon the workload
++under consideration.
++
++
++CPU Operating Point
++----
++The primary impact of loading one CPU with a number of light tasks is to
++increase the compute requirement of that CPU since it is no longer idle
++as often. Increased compute requirement causes an increase in the
++frequency of the CPU through CPUfreq.
++
++Consider this example:
++We have a system with 3 CPUs which can operate at any frequency between
++350MHz and 1GHz. The system has 6 tasks which would each produce 10%
++load at 1GHz. The scheduler has frequency-invariant load scaling
++enabled. Our DVFS governor aims for 80% utilization at the chosen
++frequency.
++
++Without task packing, these tasks will be spread out amongst all CPUs
++such that each has 2. This will produce roughly 20% system load, and
++the frequency of the package will remain at 350MHz.
++
++With task packing set to the default packing_limit, all of these tasks
++will sit on one CPU and require a package frequency of ~750MHz to reach
++80% utilization. (0.75 = 0.6 * 0.8).
++
++When a package operates on a single frequency domain, all CPUs in that
++package share frequency and voltage.
++
++Depending upon the SoC implementation there can be a significant amount
++of energy lost to leakage from idle CPUs. The decision about how
++loaded a CPU must be to be considered 'full' is therefore controllable
++through sysfs (sys/kernel/hmp/packing_limit) and directly in the code.
++
++Continuing the example, lets set packing_limit to 450 which means we
++will pack tasks until the total load of all running tasks >= 450. In
++practise, this is very similar to a 55% idle 1Ghz CPU.
++
++Now we are only able to place 4 tasks on CPU0, and two will overflow
++onto CPU1. CPU0 will have a load of 40% and CPU1 will have a load of
++20%. In order to still hit 80% utilization, CPU0 now only needs to
++operate at (0.4*0.8=0.32) 320MHz, which means that the lowest operating
++point will be selected, the same as in the non-packing case, except that
++now CPU2 is no longer needed and can be power-gated.
++
++In order to use less energy, the saving from power-gating CPU2 must be
++more than the energy spent running CPU0 for the extra cycles. This
++depends upon the SoC implementation.
++
++This is obviously a contrived example requiring all the tasks to
++be runnable at the same time, but it illustrates the point.
++
++
++Wakeup Latency
++----
++This is an unavoidable consequence of trying to pack tasks together
++rather than giving them a CPU each. If you cannot find an acceptable
++level of wakeup latency, you should turn packing off.
++
++Cyclictest is a good test application for determining the added latency
++when configuring packing.
++
++
++Why is it turned off for the VersatileExpress V2P_CA15A7 CoreTile?
++----
++Simply, this core tile only has power gating for the whole A7 package.
++When small task packing is enabled, all our low-energy use cases
++normally fit onto one A7 CPU. We therefore end up with 2 mostly-idle
++CPUs and one mostly-busy CPU. This decreases the amount of time
++available where the whole package is idle and can be turned off.
++
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/arm/cci.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/cci.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/arm/cci.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/cci.txt 2014-05-15 20:33:32.017826561 +0200
+@@ -0,0 +1,172 @@
++=======================================================
++ARM CCI cache coherent interconnect binding description
++=======================================================
++
++ARM multi-cluster systems maintain intra-cluster coherency through a
++cache coherent interconnect (CCI) that is capable of monitoring bus
++transactions and manage coherency, TLB invalidations and memory barriers.
++
++It allows snooping and distributed virtual memory message broadcast across
++clusters, through memory mapped interface, with a global control register
++space and multiple sets of interface control registers, one per slave
++interface.
++
++Bindings for the CCI node follow the ePAPR standard, available from:
++
++www.power.org/documentation/epapr-version-1-1/
++
++with the addition of the bindings described in this document which are
++specific to ARM.
++
++* CCI interconnect node
++
++ Description: Describes a CCI cache coherent Interconnect component
++
++ Node name must be "cci".
++ Node's parent must be the root node /, and the address space visible
++ through the CCI interconnect is the same as the one seen from the
++ root node (ie from CPUs perspective as per DT standard).
++ Every CCI node has to define the following properties:
++
++ - compatible
++ Usage: required
++ Value type: <string>
++ Definition: must be set to
++ "arm,cci-400"
++
++ - reg
++ Usage: required
++ Value type: <prop-encoded-array>
++ Definition: A standard property. Specifies base physical
++ address of CCI control registers common to all
++ interfaces.
++
++ - ranges:
++ Usage: required
++ Value type: <prop-encoded-array>
++ Definition: A standard property. Follow rules in the ePAPR for
++ hierarchical bus addressing. CCI interfaces
++ addresses refer to the parent node addressing
++ scheme to declare their register bases.
++
++ CCI interconnect node can define the following child nodes:
++
++ - CCI control interface nodes
++
++ Node name must be "slave-if".
++ Parent node must be CCI interconnect node.
++
++ A CCI control interface node must contain the following
++ properties:
++
++ - compatible
++ Usage: required
++ Value type: <string>
++ Definition: must be set to
++ "arm,cci-400-ctrl-if"
++
++ - interface-type:
++ Usage: required
++ Value type: <string>
++ Definition: must be set to one of {"ace", "ace-lite"}
++ depending on the interface type the node
++ represents.
++
++ - reg:
++ Usage: required
++ Value type: <prop-encoded-array>
++ Definition: the base address and size of the
++ corresponding interface programming
++ registers.
++
++* CCI interconnect bus masters
++
++ Description: masters in the device tree connected to a CCI port
++ (inclusive of CPUs and their cpu nodes).
++
++ A CCI interconnect bus master node must contain the following
++ properties:
++
++ - cci-control-port:
++ Usage: required
++ Value type: <phandle>
++ Definition: a phandle containing the CCI control interface node
++ the master is connected to.
++
++Example:
++
++ cpus {
++ #size-cells = <0>;
++ #address-cells = <1>;
++
++ CPU0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ cci-control-port = <&cci_control1>;
++ reg = <0x0>;
++ };
++
++ CPU1: cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a15";
++ cci-control-port = <&cci_control1>;
++ reg = <0x1>;
++ };
++
++ CPU2: cpu@100 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ cci-control-port = <&cci_control2>;
++ reg = <0x100>;
++ };
++
++ CPU3: cpu@101 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a7";
++ cci-control-port = <&cci_control2>;
++ reg = <0x101>;
++ };
++
++ };
++
++ dma0: dma@3000000 {
++ compatible = "arm,pl330", "arm,primecell";
++ cci-control-port = <&cci_control0>;
++ reg = <0x0 0x3000000 0x0 0x1000>;
++ interrupts = <10>;
++ #dma-cells = <1>;
++ #dma-channels = <8>;
++ #dma-requests = <32>;
++ };
++
++ cci@2c090000 {
++ compatible = "arm,cci-400";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x0 0x2c090000 0 0x1000>;
++ ranges = <0x0 0x0 0x2c090000 0x6000>;
++
++ cci_control0: slave-if@1000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace-lite";
++ reg = <0x1000 0x1000>;
++ };
++
++ cci_control1: slave-if@4000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace";
++ reg = <0x4000 0x1000>;
++ };
++
++ cci_control2: slave-if@5000 {
++ compatible = "arm,cci-400-ctrl-if";
++ interface-type = "ace";
++ reg = <0x5000 0x1000>;
++ };
++ };
++
++This CCI node corresponds to a CCI component whose control registers sits
++at address 0x000000002c090000.
++CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
++CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
++CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/arm/imx/busfreq-imx6.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/imx/busfreq-imx6.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/arm/imx/busfreq-imx6.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/imx/busfreq-imx6.txt 2014-05-15 20:33:32.017826561 +0200
+@@ -0,0 +1,64 @@
++Freescale Busfreq driver
++
++It is a generic driver that manages the frequency of the DDR, AHB and AXI buses in the iMX6x architecture.
++It works for both SMP and UP systems and for both DDR3 and LPDDR2 memory types.
++
++Required properties are listed below:
++- compatible: should be "fsl,imx6_busfreq"
++- clocks: Lists the various clocks used by the busfreq driver
++- interrupts - Lists the interrupts used by the busfreq driver. This is needed only for SMP architecutre.
++- fsl,max_ddr_freq - The max ddr freq for this chip
++
++Examples:
++For SOC imx6q.dtsi:
++ busfreq { /* BUSFREQ */
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
++ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
++ interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
++ interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
++ fsl,max_ddr_freq = <528000000>;
++ };
++
++The Freescale Busfreq driver supports the following setpoints for the DDR freq:
++enum bus_freq_mode {
++ BUS_FREQ_HIGH, -> The max freq the SOC supports
++ BUS_FREQ_MED, -> Medium setpoint (ex 400MHz for DDR3 when the max is 528MHz)
++ BUS_FREQ_AUDIO, -> Audio playback freq (50MHz)
++ BUS_FREQ_LOW, -> Low power IDLE freq (24MHz)
++};
++
++Currently the Freescale Busfreq driver implementation requires drivers to call the following APIs:
++1. request_bus_freq(enum bus_freq_mode):
++ The driver is requesting the system and ddr freq to be set to the requested value. The driver should call this
++ API before it even enables its clocks.
++
++2. release_bus_freq(enum bus_freq_mode):
++ The driver no longer needs the system and ddr freq at the required value. The driver should call this API after
++ its work is done and it has disabled its clocks.
++
++Examples:
++In the IPU driver, the requesting and releasing of the required bus frequency is tied into the runtime PM implementation:
++
++int ipu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "ipu busfreq high release.\n");
++
++ return 0;
++}
++
++int ipu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "ipu busfreq high requst.\n");
++
++ return 0;
++}
++
++static const struct dev_pm_ops ipu_pm_ops = {
++ SET_RUNTIME_PM_OPS(ipu_runtime_suspend, ipu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(ipu_suspend, ipu_resume)
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/arm/imx/gpc.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/imx/gpc.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/arm/imx/gpc.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/imx/gpc.txt 2014-05-15 20:33:32.017826561 +0200
+@@ -0,0 +1,20 @@
++Freescale imx GPC bindings
++
++Optional properties:
++- fsl,cpu_pupscr_sw2iso: for powering up CPU, number of 32K clock cycle PGC will wait before negating isolation signal.
++- fsl,cpu_pupscr_sw: for powering up CPU, number of 32K clock cycle PGC will wait before asserting isolation signal.
++- fsl,cpu_pdnscr_iso2sw: for powering down CPU, number of ipg clock cycle PGC will wait before negating isolation signal.
++- fsl,cpu_pdnscr_iso: for powering down CPU, number of ipg clock cycle PGC will wait before asserting isolation signal.
++
++These properties are for adjusting the GPC PGC CPU power up/down setting, if there is no such property in dts, then default
++value in GPC PGC registers will be used.
++
++
++Example:
++
++ &gpc {
++ fsl,cpu_pupscr_sw2iso = <0xf>;
++ fsl,cpu_pupscr_sw = <0xf>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/arm/pmu.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/pmu.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/arm/pmu.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/pmu.txt 2014-05-15 20:33:32.021826590 +0200
+@@ -16,6 +16,9 @@
+ "arm,arm1176-pmu"
+ "arm,arm1136-pmu"
+ - interrupts : 1 combined interrupt or 1 per core.
++- cluster : a phandle to the cluster to which it belongs
++ If there are more than one cluster with same CPU type
++ then there should be separate PMU nodes per cluster.
+
+ Example:
+
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt 2014-05-15 20:33:32.021826590 +0200
+@@ -0,0 +1,19 @@
++ARM Dual Cluster System Configuration Block
++-------------------------------------------
++
++The Dual Cluster System Configuration Block (DCSCB) provides basic
++functionality for controlling clocks, resets and configuration pins in
++the Dual Cluster System implemented by the Real-Time System Model (RTSM).
++
++Required properties:
++
++- compatible : should be "arm,rtsm,dcscb"
++
++- reg : physical base address and the size of the registers window
++
++Example:
++
++ dcscb@60000000 {
++ compatible = "arm,rtsm,dcscb";
++ reg = <0x60000000 0x1000>;
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/bus/imx-weim.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/bus/imx-weim.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/bus/imx-weim.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/bus/imx-weim.txt 2014-05-15 20:33:32.025826619 +0200
+@@ -0,0 +1,49 @@
++Device tree bindings for i.MX Wireless External Interface Module (WEIM)
++
++The term "wireless" does not imply that the WEIM is literally an interface
++without wires. It simply means that this module was originally designed for
++wireless and mobile applications that use low-power technology.
++
++The actual devices are instantiated from the child nodes of a WEIM node.
++
++Required properties:
++
++ - compatible: Should be set to "fsl,imx6q-weim"
++ - reg: A resource specifier for the register space
++ (see the example below)
++ - clocks: the clock, see the example below.
++ - #address-cells: Must be set to 2 to allow memory address translation
++ - #size-cells: Must be set to 1 to allow CS address passing
++ - ranges: Must be set up to reflect the memory layout with four
++ integer values for each chip-select line in use:
++
++ <cs-number> 0 <physical address of mapping> <size>
++
++Timing property for child nodes. It is mandatory, not optional.
++
++ - fsl,weim-cs-timing: The timing array, contains 6 timing values for the
++ child node. We can get the CS index from the child
++ node's "reg" property. This property contains the values
++ for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
++ EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
++
++Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
++
++ weim: weim@021b8000 {
++ compatible = "fsl,imx6q-weim";
++ reg = <0x021b8000 0x4000>;
++ clocks = <&clks 196>;
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0x08000000 0x08000000>;
++
++ nor@0,0 {
++ compatible = "cfi-flash";
++ reg = <0 0 0x02000000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ bank-width = <2>;
++ fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
++ 0x0000c000 0x1404a38e 0x00000000>;
++ };
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/clock/imx6q-clock.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/clock/imx6q-clock.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/clock/imx6q-clock.txt 2014-05-15 20:33:32.077826993 +0200
+@@ -89,8 +89,6 @@
+ gpu3d_shader 74
+ ipu1_podf 75
+ ipu2_podf 76
+- ldb_di0_podf 77
+- ldb_di1_podf 78
+ ipu1_di0_pre 79
+ ipu1_di1_pre 80
+ ipu2_di0_pre 81
+@@ -208,6 +206,29 @@
+ pll4_post_div 193
+ pll5_post_div 194
+ pll5_video_div 195
++ eim_slow 196
++ spdif 197
++ cko2_sel 198
++ cko2_podf 199
++ cko2 200
++ cko 201
++ vdoa 202
++ gpt_3m 203
++ video_27m 204
++ ldb_di0_div_7 205
++ ldb_di1_div_7 206
++ ldb_di0_div_sel 207
++ ldb_di1_div_sel 208
++ pll4_audio_div 209
++ lvds1_sel 210
++ lvds1_in 211
++ lvds1_out 212
++ caam_mem 213
++ caam_aclk 214
++ caam_ipg 215
++ epit1 216
++ epit2 217
++ tzasc2 218
+
+ Examples:
+
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/clock/imx6sl-clock.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/clock/imx6sl-clock.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/clock/imx6sl-clock.txt 2014-05-15 20:33:32.077826993 +0200
+@@ -0,0 +1,10 @@
++* Clock bindings for Freescale i.MX6 SoloLite
++
++Required properties:
++- compatible: Should be "fsl,imx6sl-ccm"
++- reg: Address and length of the register set
++- #clock-cells: Should be <1>
++
++The clock consumer should specify the desired clock by having the clock
++ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sl-clock.h
++for the full list of i.MX6 SoloLite clock IDs.
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/clock/vf610-clock.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/clock/vf610-clock.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/clock/vf610-clock.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/clock/vf610-clock.txt 2014-05-15 20:33:32.121827311 +0200
+@@ -0,0 +1,26 @@
++* Clock bindings for Freescale Vybrid VF610 SOC
++
++Required properties:
++- compatible: Should be "fsl,vf610-ccm"
++- reg: Address and length of the register set
++- #clock-cells: Should be <1>
++
++The clock consumer should specify the desired clock by having the clock
++ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
++for the full list of VF610 clock IDs.
++
++Examples:
++
++clks: ccm@4006b000 {
++ compatible = "fsl,vf610-ccm";
++ reg = <0x4006b000 0x1000>;
++ #clock-cells = <1>;
++};
++
++uart1: serial@40028000 {
++ compatible = "fsl,vf610-uart";
++ reg = <0x40028000 0x1000>;
++ interrupts = <0 62 0x04>;
++ clocks = <&clks VF610_CLK_UART1>;
++ clock-names = "ipg";
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6q.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6q.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6q.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/cpufreq/cpufreq-imx6q.txt 2014-05-15 20:33:32.121827311 +0200
+@@ -0,0 +1,59 @@
++iMX6q/iMX6dl/iMX6sl specific CPUFREQ settings
++
++iMX6q/iMX6dl/iMX6sl has limitation that a couple of voltage rails (VDDSOC_CAP and VDDPU_CAP)
++must track VDDARM_CAP within 50mV:
++VDDARM_CAP - VDDSOC_CAP/VDDPU_CAP <= 50mV
++
++The VDDSOC_CAP and VDDPU_CAP operating points for various VDDARM_CAP settings are listed below.
++
++Required properties:
++- fsl,soc-operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
++ for details. It is a voltage frequency tuple.
++
++- For other entries in the example below please refer to Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
++
++Examples:
++
++cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu@0 {
++ compatible = "arm,cortex-a9";
++ reg = <0>;
++ next-level-cache = <&L2>;
++ operating-points = <
++ /* kHz uV */
++ 1200000 1275000
++ 996000 1250000
++ 792000 1175000
++ 396000 1075000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 1200000 1275000
++ 996000 1250000
++ 792000 1175000
++ 396000 1175000
++ >;
++ clock-latency = <61036>; /* two CLK32 periods */
++ };
++
++ cpu@1 {
++ compatible = "arm,cortex-a9";
++ reg = <1>;
++ next-level-cache = <&L2>;
++ };
++
++ cpu@2 {
++ compatible = "arm,cortex-a9";
++ reg = <2>;
++ next-level-cache = <&L2>;
++ };
++
++ cpu@3 {
++ compatible = "arm,cortex-a9";
++ reg = <3>;
++ next-level-cache = <&L2>;
++ };
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt 2014-05-15 20:33:32.121827311 +0200
+@@ -4,14 +4,71 @@
+ - compatible : Should be "fsl,<chip>-sdma"
+ - reg : Should contain SDMA registers location and length
+ - interrupts : Should contain SDMA interrupt
++- #dma-cells : Must be <3>.
++ The first cell specifies the DMA request/event ID. See details below
++ about the second and third cell.
+ - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
+ scripts firmware
+
++The second cell of dma phandle specifies the peripheral type of DMA transfer.
++The full ID of peripheral types can be found below.
++
++ ID transfer type
++ ---------------------
++ 0 MCU domain SSI
++ 1 Shared SSI
++ 2 MMC
++ 3 SDHC
++ 4 MCU domain UART
++ 5 Shared UART
++ 6 FIRI
++ 7 MCU domain CSPI
++ 8 Shared CSPI
++ 9 SIM
++ 10 ATA
++ 11 CCM
++ 12 External peripheral
++ 13 Memory Stick Host Controller
++ 14 Shared Memory Stick Host Controller
++ 15 DSP
++ 16 Memory
++ 17 FIFO type Memory
++ 18 SPDIF
++ 19 IPU Memory
++ 20 ASRC
++ 21 ESAI
++ 22 HDMI Audio
++
++The third cell specifies the transfer priority as below.
++
++ ID transfer priority
++ -------------------------
++ 0 High
++ 1 Medium
++ 2 Low
++
+ Examples:
+
+ sdma@83fb0000 {
+ compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
+ reg = <0x83fb0000 0x4000>;
+ interrupts = <6>;
++ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "sdma-imx51.bin";
+ };
++
++DMA clients connected to the i.MX SDMA controller must use the format
++described in the dma.txt file.
++
++Examples:
++
++ssi2: ssi@70014000 {
++ compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
++ reg = <0x70014000 0x4000>;
++ interrupts = <30>;
++ clocks = <&clks 49>;
++ dmas = <&sdma 24 1 0>,
++ <&sdma 25 1 0>;
++ dma-names = "rx", "tx";
++ fsl,fifo-depth = <15>;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/fb/fsl_epdc_fb.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/fb/fsl_epdc_fb.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/fb/fsl_epdc_fb.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/fb/fsl_epdc_fb.txt 2014-05-15 20:33:32.141827456 +0200
+@@ -0,0 +1,30 @@
++* Freescale MXC Electrophoretic Display Controller (EPDC)
++
++Required properties:
++- compatible: Should be "fsl,<chip>-epdc". Supported chips include
++ imx6dl and imx6sl
++- reg: Address and length of the register set for EPDC
++- interrupts: Should contain EPDC interrupts
++- clocks: the clocks for EPDC
++- pinctrl-names: should be "default"
++- pinctrl-0: should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the
++ IPU connected.
++- V3P3_supply: power supply for EPDC_PWRCTRL0 from pmic
++- VCOM_supply: power supply for EPDC_VCOM0 from pmic
++- DISPLAY_supply: power supply enable for pmic
++
++Examples:
++
++imx6_epdc@0x020f8000 {
++ compatible = "fsl,imx6dl-epdc";
++ reg = <0x020f8000 4000>;
++ interrupts = <0 97 0x04>;
++ clocks = <&clks 133>, <&clks 137>; /* ipu2, ipu2_di1 */
++ clock-names = "epdc-axi", "epdc-pix";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_epdc_0>;
++ V3P3_supply = <&V3P3_reg>;
++ VCOM_supply = <&VCOM_reg>;
++ DISPLAY_supply = <&DISPLAY_reg>;
++ status = "disabled";
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt 2014-05-15 20:33:32.173827687 +0200
+@@ -0,0 +1,146 @@
++* FSL IPUv3 Display/FB
++
++The FSL IPUv3 is Image Processing Unit version 3, a part of video and graphics
++subsystem in an application processor. The goal of the IPU is to provide
++comprehensive support for the flow of data from an image sensor or/and to a
++display device.
++
++Two IPU units are on the imx6q SOC while only one IPU unit on the imx6dl SOC.
++Each IPU unit has two display interfaces.
++
++For LDB/LVDS panel, there are two LVDS channels(LVDS0 and LVDS1) which can
++transfer video data, these two channels can be used as
++split/dual/single/separate mode.
++-split mode means display data from DI0 or DI1 will send to both channels
++ LVDS0+LVDS1.
++-dual mode means display data from DI0 or DI1 will be duplicated on LVDS0
++ and LVDS1, it said, LVDS0 and LVDS1 has the same content.
++-single mode means only work for DI0/DI1->LVDS0 or DI0/DI1->LVDS1.
++-separate mode means you can make DI0/DI1->LVDS0 and DI0/DI1->LVDS1 work
++ at the same time.
++ "ldb=spl0/1" -- split mode on DI0/1
++ "ldb=dul0/1" -- dual mode on DI0/1
++ "ldb=sin0/1" -- single mode on LVDS0/1
++ "ldb=sep0/1" -- separate mode begin from LVDS0/1
++
++Required properties for IPU:
++- bypass_reset :Bypass reset to avoid display channel being.
++ stopped by probe since it may start to work in bootloader: 0 or 1.
++- compatible : should be "fsl,imx6q-ipu".
++- reg : the register address range.
++- interrupts : the error and sync interrupts request.
++- clocks : the clock sources that it depends on.
++- clock-names: the related clock names.
++- resets : IPU reset specifier. See reset.txt and fsl,imx-src.txt in
++ Documentation/devicetree/bindings/reset/ for details.
++
++Required properties for fb:
++- compatible : should be "fsl,mxc_sdc_fb".
++- disp_dev : display device: "ldb", "lcd", "hdmi", "mipi_dsi".
++- mode_str : video mode string: "LDB-XGA" or "LDB-1080P60" for ldb,
++ "CLAA-WVGA" for lcd, "TRULY-WVGA" for TRULY mipi_dsi lcd panel,
++ "1920x1080M@60" for hdmi.
++- default_bpp : default bits per pixel: 8/16/24/32
++- int_clk : use internal clock as pixel clock: 0 or 1
++- late_init : to avoid display channel being re-initialized
++ as we've probably setup the channel in bootloader: 0 or 1
++- interface_pix_fmt : display interface pixel format as below:
++ RGB666 IPU_PIX_FMT_RGB666
++ RGB565 IPU_PIX_FMT_RGB565
++ RGB24 IPU_PIX_FMT_RGB24
++ BGR24 IPU_PIX_FMT_BGR24
++ GBR24 IPU_PIX_FMT_GBR24
++ YUV444 IPU_PIX_FMT_YUV444
++ LVDS666 IPU_PIX_FMT_LVDS666
++ YUYV IPU_PIX_FMT_YUYV
++ UYVY IPU_PIX_FMT_UYVY
++ YVYV IPU_PIX_FMT_YVYU
++ VYUY IPU_PIX_FMT_VYUY
++
++Required properties for display:
++- compatible : should be "fsl,lcd" for lcd panel, "fsl,imx6q-ldb" for ldb
++- reg : the register address range if necessary to have.
++- interrupts : the error and sync interrupts if necessary to have.
++- clocks : the clock sources that it depends on if necessary to have.
++- clock-names: the related clock names if necessary to have.
++- ipu_id : ipu id for the first display device: 0 or 1
++- disp_id : display interface id for the first display interface: 0 or 1
++- default_ifmt : save as above display interface pixel format for lcd
++- pinctrl-names : should be "default"
++- pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the
++ IPU connected.
++- sec_ipu_id : secondary ipu id for the second display device(ldb only): 0 or 1
++- sec_disp_id : secondary display interface id for the second display
++ device(ldb only): 0 or 1
++- ext_ref : reference resistor select for ldb only: 0 or 1
++- mode : ldb mode as below:
++ spl0 LDB_SPL_DI0
++ spl1 LDB_SPL_DI1
++ dul0 LDB_DUL_DI0
++ dul1 LDB_DUL_DI1
++ sin0 LDB_SIN0
++ sin1 LDB_SIN1
++ sep0 LDB_SEP0
++ sep1 LDB_SEP1
++- gpr : the mux controller for the display engine's display interfaces and the display encoder
++ (only valid for mipi dsi now).
++- disp-power-on-supply : the regulator to control display panel's power.
++ (only valid for mipi dsi now).
++- resets : the gpio pin to reset the display device(only valid for mipi display panel now).
++- lcd_panel : the video mode name for the display device(only valid for mipi display panel now).
++- dev_id : the display engine's identity within the system, which intends to replace ipu_id
++ (only valid for mipi dsi now).
++
++Example for IPU:
++ ipu1: ipu@02400000 {
++ compatible = "fsl,imx6q-ipu";
++ reg = <0x02400000 0x400000>;
++ interrupts = <0 6 0x4 0 5 0x4>;
++ clocks = <&clks 130>, <&clks 131>, <&clks 132>,
++ <&clks 39>, <&clks 40>,
++ <&clks 135>, <&clks 136>;
++ clock-names = "bus", "di0", "di1",
++ "di0_sel", "di1_sel",
++ "ldb_di0", "ldb_di1";
++ resets = <&src 2>;
++ bypass_reset = <0>;
++ };
++
++Example for fb:
++ fb0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++Example for ldb display:
++ ldb@020e0000 {
++ ipu_id = <1>;
++ disp_id = <0>;
++ ext_ref = <1>;
++ mode = "sep0";
++ sec_ipu_id = <1>;
++ sec_disp_id = <1>;
++ status = "okay";
++ };
++
++Example for mipi dsi display:
++ mipi_dsi: mipi@021e0000 {
++ compatible = "fsl,imx6q-mipi-dsi";
++ reg = <0x021e0000 0x4000>;
++ interrupts = <0 102 0x04>;
++ gpr = <&gpr>;
++ clocks = <&clks 138>, <&clks 204>;
++ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
++ dev_id = <0>;
++ disp_id = <0>;
++ lcd_panel = "TRULY-WVGA";
++ disp-power-on-supply = <&reg_mipi_dsi_pwr_on>
++ resets = <&mipi_dsi_reset>;
++ status = "okay";
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/fb/mxsfb.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/fb/mxsfb.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/fb/mxsfb.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/fb/mxsfb.txt 2014-05-15 20:33:32.173827687 +0200
+@@ -3,6 +3,9 @@
+ Required properties:
+ - compatible: Should be "fsl,<chip>-lcdif". Supported chips include
+ imx23 and imx28.
++- pinctrl-names: Should be "default"
++- pinctrl-0: pinctrl setting for lcd
++- lcd-supply: lcd power supply, usually via GPIO
+ - reg: Address and length of the register set for lcdif
+ - interrupts: Should contain lcdif interrupts
+ - display : phandle to display node (see below for details)
+@@ -22,6 +25,10 @@
+ compatible = "fsl,imx28-lcdif";
+ reg = <0x80030000 2000>;
+ interrupts = <38 86>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&lcdif_24bit_pins_a
++ &lcdif_pins_evk>;
++ lcd-supply = <&reg_lcd_3v3>;
+
+ display: display {
+ bits-per-pixel = <32>;
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/input/touchscreen/elan-ts.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/input/touchscreen/elan-ts.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/input/touchscreen/elan-ts.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/input/touchscreen/elan-ts.txt 2014-05-15 20:33:32.281828465 +0200
+@@ -0,0 +1,23 @@
++* ELAN Resistive Touch Controller
++
++Required properties:
++- compatible: must be "elan,elan-touch"
++- reg: i2c slave address
++- interrupt-parent: the phandle for the interrupt controller
++- interrupts: touch controller interrupt
++- gpio_elan_cs: the gpio pin for chip select
++- gpio_elan_rst: the gpio pin for chip reset
++- gpio_intr: the gpio pin to be used for interrupt pin
++
++Example:
++
++ elan@10 {
++ compatible = "elan,elan-touch";
++ reg = <0x10>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <28 3>;
++ gpio_elan_cs = <&gpio2 18 0>;
++ gpio_elan_rst = <&gpio3 8 0>;
++ gpio_intr = <&gpio3 28 0>;
++ status = "okay";
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/leds/leds-pwm.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/leds/leds-pwm.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/leds/leds-pwm.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/leds/leds-pwm.txt 2014-05-15 20:33:32.281828465 +0200
+@@ -13,6 +13,9 @@
+ For the pwms and pwm-names property please refer to:
+ Documentation/devicetree/bindings/pwm/pwm.txt
+ - max-brightness : Maximum brightness possible for the LED
++- default-brightness : (optional) Default brightness for the LED
++- active-low : (optional) For PWMs where the LED is wired to supply
++ rather than ground.
+ - label : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+ - linux,default-trigger : (optional)
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/mfd/vexpress-spc.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/mfd/vexpress-spc.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/mfd/vexpress-spc.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/mfd/vexpress-spc.txt 2014-05-15 20:33:32.289828523 +0200
+@@ -0,0 +1,35 @@
++* ARM Versatile Express Serial Power Controller device tree bindings
++
++Latest ARM development boards implement a power management interface (serial
++power controller - SPC) that is capable of managing power/voltage and
++operating point transitions, through memory mapped registers interface.
++
++On testchips like TC2 it also provides a configuration interface that can
++be used to read/write values which cannot be read/written through simple
++memory mapped reads/writes.
++
++- spc node
++
++ - compatible:
++ Usage: required
++ Value type: <stringlist>
++ Definition: must be
++ "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc"
++ - reg:
++ Usage: required
++ Value type: <prop-encode-array>
++ Definition: A standard property that specifies the base address
++ and the size of the SPC address space
++ - interrupts:
++ Usage: required
++ Value type: <prop-encoded-array>
++ Definition: SPC interrupt configuration. A standard property
++ that follows ePAPR interrupts specifications
++
++Example:
++
++spc: spc@7fff0000 {
++ compatible = "arm,vexpress-spc,v2p-ca15_a7","arm,vexpress-spc";
++ reg = <0 0x7FFF0000 0 0x1000>;
++ interrupts = <0 95 4>;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/mlb/mlb150.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/mlb/mlb150.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/mlb/mlb150.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/mlb/mlb150.txt 2014-05-15 20:33:32.293828552 +0200
+@@ -0,0 +1,22 @@
++* Freescale Media Local Bus Host Controller (MLB) for i.MX6Q/DL
++
++The Media Local Bus Host Controller on Freescale i.MX family
++provides an interface for MOST network.
++
++Required properties:
++- compatible : Should be "fsl,<chip>-mlb150"
++- reg : Should contain mlb registers location and length
++- interrupts : Should contain mlb interrupt
++- clocks: Should contain the mlb clock sources
++- clock-names: Should be the names of mlb clock sources
++- iram : phandle pointing to the SRAM device node
++
++Examples:
++mlb@0218c000 {
++ compatible = "fsl,imx6q-mlb150";
++ reg = <0x0218c000 0x4000>;
++ interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
++ clocks = <&clks 139>, <&clks 175>;
++ clock-names = "mlb", "pll8_mlb";
++ iram = <&ocram>;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt 2014-05-15 20:33:32.293828552 +0200
+@@ -12,6 +12,11 @@
+ Optional properties:
+ - fsl,cd-controller : Indicate to use controller internal card detection
+ - fsl,wp-controller : Indicate to use controller internal write protection
++- fsl,delay-line : Specify the number of delay cells for override mode.
++ This is used to set the clock delay for DLL(Delay Line) on override mode
++ to select a proper data sampling window in case the clock quality is not good
++ due to signal path is too long on the board. Please refer to eSDHC/uSDHC
++ chapter, DLL (Delay Line) section in RM for details.
+
+ Examples:
+
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/mmc/mmc.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/mmc/mmc.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/mmc/mmc.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/mmc/mmc.txt 2014-05-15 20:33:32.293828552 +0200
+@@ -5,6 +5,8 @@
+ Interpreted by the OF core:
+ - reg: Registers location and length.
+ - interrupts: Interrupts used by the MMC controller.
++- clocks: Clocks needed for the host controller, if any.
++- clock-names: Goes with clocks above.
+
+ Card detection:
+ If no property below is supplied, host native card detect is used.
+@@ -29,6 +31,15 @@
+ - cap-power-off-card: powering off the card is safe
+ - cap-sdio-irq: enable SDIO IRQ signalling on this interface
+
++Card power and reset control:
++The following properties can be specified for cases where the MMC
++peripheral needs additional reset, regulator and clock lines. It is for
++example common for WiFi/BT adapters to have these separate from the main
++MMC bus:
++ - card-reset-gpios: Specify GPIOs for card reset (reset active low)
++ - card-external-vcc-supply: Regulator to drive (independent) card VCC
++ - clock with name "card_ext_clock": External clock provided to the card
++
+ *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
+ polarity properties, we have to fix the meaning of the "normal" and "inverted"
+ line levels. We choose to follow the SDHCI standard, which specifies both those
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/mtd/gpmi-nand.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/mtd/gpmi-nand.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/mtd/gpmi-nand.txt 2014-05-15 20:33:32.297828580 +0200
+@@ -17,6 +17,14 @@
+ Optional properties:
+ - nand-on-flash-bbt: boolean to enable on flash bbt option if not
+ present false
++ - fsl,use-minimum-ecc: Protect this NAND flash with the minimum ECC
++ strength required. The required ECC strength is
++ automatically discoverable for some flash
++ (e.g., according to the ONFI standard).
++ However, note that if this strength is not
++ discoverable or this property is not enabled,
++ the software may chooses an implementation-defined
++ ECC scheme.
+
+ The device tree may optionally contain sub-nodes describing partitions of the
+ address space. See partition.txt for more detail.
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt 2014-05-15 20:33:32.297828580 +0200
+@@ -15,6 +15,13 @@
+ Optional properties:
+
+ - clock-frequency : The oscillator frequency driving the flexcan device
++- gpr: phandle to general purpose register node. The remote wakeup control
++ bits is stored here.
++
++Below are gpios for tranceiver:
++- trx_en_gpio : enable gpio
++- trx_stby_gpio : standby gpio
++- trx_nerr_gpio : NERR gpio
+
+ Example:
+
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/pci/designware-pcie.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/pci/designware-pcie.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/pci/designware-pcie.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/pci/designware-pcie.txt 2014-05-15 20:33:32.321828754 +0200
+@@ -0,0 +1,81 @@
++* Synopsis Designware PCIe interface
++
++Required properties:
++- compatible: should contain "snps,dw-pcie" to identify the
++ core, plus an identifier for the specific instance, such
++ as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
++- reg: base addresses and lengths of the pcie controller,
++ the phy controller, additional register for the phy controller.
++- interrupts: interrupt values for level interrupt,
++ pulse interrupt, special interrupt.
++- clocks: from common clock binding: handle to pci clock.
++- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
++- #address-cells: set to <3>
++- #size-cells: set to <2>
++- device_type: set to "pci"
++- ranges: ranges for the PCI memory and I/O regions
++- #interrupt-cells: set to <1>
++- interrupt-map-mask and interrupt-map: standard PCI properties
++ to define the mapping of the PCIe interface to interrupt
++ numbers.
++- num-lanes: number of lanes to use
++- reset-gpio: gpio pin number of power good signal
++
++Optional properties for fsl,imx6q-pcie
++- power-on-gpio: gpio pin number of power-enable signal
++- wake-up-gpio: gpio pin number of incoming wakeup signal
++- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
++
++Example:
++
++SoC specific DT Entry:
++
++ pcie@290000 {
++ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
++ reg = <0x290000 0x1000
++ 0x270000 0x1000
++ 0x271000 0x40>;
++ interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
++ clocks = <&clock 28>, <&clock 27>;
++ clock-names = "pcie", "pcie_bus";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
++ 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
++ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0x0 0 &gic 53>;
++ num-lanes = <4>;
++ };
++
++ pcie@2a0000 {
++ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
++ reg = <0x2a0000 0x1000
++ 0x272000 0x1000
++ 0x271040 0x40>;
++ interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
++ clocks = <&clock 29>, <&clock 27>;
++ clock-names = "pcie", "pcie_bus";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
++ 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
++ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0x0 0 &gic 56>;
++ num-lanes = <4>;
++ };
++
++Board specific DT Entry:
++
++ pcie@290000 {
++ reset-gpio = <&pin_ctrl 5 0>;
++ };
++
++ pcie@2a0000 {
++ reset-gpio = <&pin_ctrl 22 0>;
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/pci/mvebu-pci.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/pci/mvebu-pci.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/pci/mvebu-pci.txt 2014-05-15 20:33:32.321828754 +0200
+@@ -0,0 +1,221 @@
++* Marvell EBU PCIe interfaces
++
++Mandatory properties:
++- compatible: one of the following values:
++ marvell,armada-370-pcie
++ marvell,armada-xp-pcie
++ marvell,kirkwood-pcie
++- #address-cells, set to <3>
++- #size-cells, set to <2>
++- #interrupt-cells, set to <1>
++- bus-range: PCI bus numbers covered
++- device_type, set to "pci"
++- ranges: ranges for the PCI memory and I/O regions, as well as the
++ MMIO registers to control the PCIe interfaces.
++
++In addition, the Device Tree node must have sub-nodes describing each
++PCIe interface, having the following mandatory properties:
++- reg: used only for interrupt mapping, so only the first four bytes
++ are used to refer to the correct bus number and device number.
++- assigned-addresses: reference to the MMIO registers used to control
++ this PCIe interface.
++- clocks: the clock associated to this PCIe interface
++- marvell,pcie-port: the physical PCIe port number
++- status: either "disabled" or "okay"
++- device_type, set to "pci"
++- #address-cells, set to <3>
++- #size-cells, set to <2>
++- #interrupt-cells, set to <1>
++- ranges, empty property.
++- interrupt-map-mask and interrupt-map, standard PCI properties to
++ define the mapping of the PCIe interface to interrupt numbers.
++
++and the following optional properties:
++- marvell,pcie-lane: the physical PCIe lane number, for ports having
++ multiple lanes. If this property is not found, we assume that the
++ value is 0.
++
++Example:
++
++pcie-controller {
++ compatible = "marvell,armada-xp-pcie";
++ status = "disabled";
++ device_type = "pci";
++
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ bus-range = <0x00 0xff>;
++
++ ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
++ 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
++ 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
++ 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
++ 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
++ 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
++ 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
++ 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
++ 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
++ 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
++ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
++ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
++
++ pcie@1,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
++ reg = <0x0800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 58>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gateclk 5>;
++ status = "disabled";
++ };
++
++ pcie@2,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
++ reg = <0x1000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 59>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <1>;
++ clocks = <&gateclk 6>;
++ status = "disabled";
++ };
++
++ pcie@3,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
++ reg = <0x1800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 60>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <2>;
++ clocks = <&gateclk 7>;
++ status = "disabled";
++ };
++
++ pcie@4,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
++ reg = <0x2000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 61>;
++ marvell,pcie-port = <0>;
++ marvell,pcie-lane = <3>;
++ clocks = <&gateclk 8>;
++ status = "disabled";
++ };
++
++ pcie@5,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
++ reg = <0x2800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 62>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gateclk 9>;
++ status = "disabled";
++ };
++
++ pcie@6,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
++ reg = <0x3000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 63>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <1>;
++ clocks = <&gateclk 10>;
++ status = "disabled";
++ };
++
++ pcie@7,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
++ reg = <0x3800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 64>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <2>;
++ clocks = <&gateclk 11>;
++ status = "disabled";
++ };
++
++ pcie@8,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
++ reg = <0x4000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 65>;
++ marvell,pcie-port = <1>;
++ marvell,pcie-lane = <3>;
++ clocks = <&gateclk 12>;
++ status = "disabled";
++ };
++ pcie@9,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
++ reg = <0x4800 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 99>;
++ marvell,pcie-port = <2>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gateclk 26>;
++ status = "disabled";
++ };
++
++ pcie@10,0 {
++ device_type = "pci";
++ assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
++ reg = <0x5000 0 0 0 0>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ #interrupt-cells = <1>;
++ ranges;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &mpic 103>;
++ marvell,pcie-port = <3>;
++ marvell,pcie-lane = <0>;
++ clocks = <&gateclk 27>;
++ status = "disabled";
++ };
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt 2014-05-15 20:33:32.345828926 +0200
+@@ -0,0 +1,41 @@
++Freescale Vybrid VF610 IOMUX Controller
++
++Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
++and usage.
++
++Required properties:
++- compatible: "fsl,vf610-iomuxc"
++- fsl,pins: two integers array, represents a group of pins mux and config
++ setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
++ a pin working on a specific function, CONFIG is the pad setting value
++ such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
++ datasheet for the valid pad config settings.
++
++CONFIG bits definition:
++PAD_CTL_SPEED_LOW (1 << 12)
++PAD_CTL_SPEED_MED (2 << 12)
++PAD_CTL_SPEED_HIGH (3 << 12)
++PAD_CTL_SRE_FAST (1 << 11)
++PAD_CTL_SRE_SLOW (0 << 11)
++PAD_CTL_ODE (1 << 10)
++PAD_CTL_HYS (1 << 9)
++PAD_CTL_DSE_DISABLE (0 << 6)
++PAD_CTL_DSE_150ohm (1 << 6)
++PAD_CTL_DSE_75ohm (2 << 6)
++PAD_CTL_DSE_50ohm (3 << 6)
++PAD_CTL_DSE_37ohm (4 << 6)
++PAD_CTL_DSE_30ohm (5 << 6)
++PAD_CTL_DSE_25ohm (6 << 6)
++PAD_CTL_DSE_20ohm (7 << 6)
++PAD_CTL_PUS_100K_DOWN (0 << 4)
++PAD_CTL_PUS_47K_UP (1 << 4)
++PAD_CTL_PUS_100K_UP (2 << 4)
++PAD_CTL_PUS_22K_UP (3 << 4)
++PAD_CTL_PKE (1 << 3)
++PAD_CTL_PUE (1 << 2)
++PAD_CTL_OBE_ENABLE (1 << 1)
++PAD_CTL_IBE_ENABLE (1 << 0)
++PAD_CTL_OBE_IBE_ENABLE (3 << 0)
++
++Please refer to vf610-pinfunc.h in device tree source folder
++for all available PIN_FUNC_ID for Vybrid VF610.
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 2014-05-15 20:33:32.349828956 +0200
+@@ -71,6 +71,13 @@
+ name for integer state ID 0, list entry 1 for state ID 1, and
+ so on.
+
++pinctrl-assert-gpios:
++ List of phandles, each pointing at a GPIO which is used by some
++ board design to steer pins between two peripherals on the board.
++ It plays like a board level pin multiplexer to choose different
++ functions for given pins by pulling up/down the GPIOs. See
++ bindings/gpio/gpio.txt for details of how to specify GPIO.
++
+ For example:
+
+ /* For a client device requiring named states */
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/regulator/max17135-regulator.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/regulator/max17135-regulator.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/regulator/max17135-regulator.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/regulator/max17135-regulator.txt 2014-05-15 20:33:32.473829850 +0200
+@@ -0,0 +1,112 @@
++Maxim MAX17135 Voltage Regulator
++
++The MAX17135 is a complete power-management IC for E-paper displays that
++provides source- and gate-driver power supplies, a high-speed VCOM amplifier,
++and a temperature sensor. It is interfaced to the host controller using an
++i2c interface.
++
++Required properties :
++- compatible : "maxim,max17135"
++- reg: Specifies the i2c slave address of the pmic block.
++- vneg_pwrup: the timing for VNEG power up
++- gvee_pwrup: the timing for GVEE power up
++- vpos_pwrup: the timing for VPOS power up
++- gvdd_pwrup: the timing for GVDD power up
++- gvdd_pwrdn: the timing for GVDD power down
++- vpos_pwrdn: the timing for VPOS power down
++- gvee_pwrdn: the timing for GVEE power down
++- vneg_pwrdn: the timing for VNEG power down
++- gpio_pmic_pwrgood: gpio setting for EPDC_PWRSTAT
++- gpio_pmic_vcom_ctrl: gpio setting for EPDC_VCOM
++- gpio_pmic_wakeup: gpio setting for EPDC_PWRWAKEUP
++- gpio_pmic_v3p3: gpio setting for EPDC_PWRCTRL0
++- gpio_pmic_intr: gpio setting for EPDC_PWRINT
++
++Optional properties :
++- SENSOR-supply: the gpio regulator to control the supply for this chip
++
++
++Regulators: The regulators of max17135 that have to be instantiated should be
++included in a sub-node named 'regulators'. Regulator nodes included in this
++sub-node should be of the format as listed below.
++
++ regulator_name {
++ standard regulator bindings here
++ };
++
++Example:
++ max17135@48 {
++ compatible = "maxim,max17135";
++ reg = <0x48>;
++ vneg_pwrup = <1>;
++ gvee_pwrup = <1>;
++ vpos_pwrup = <2>;
++ gvdd_pwrup = <1>;
++ gvdd_pwrdn = <1>;
++ vpos_pwrdn = <2>;
++ gvee_pwrdn = <1>;
++ vneg_pwrdn = <1>;
++ SENSOR-supply = <&reg_sensor>;
++ gpio_pmic_pwrgood = <&gpio2 21 0>;
++ gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
++ gpio_pmic_wakeup = <&gpio3 20 0>;
++ gpio_pmic_v3p3 = <&gpio2 20 0>;
++ gpio_pmic_intr = <&gpio2 25 0>;
++
++ regulators {
++ DISPLAY_reg: DISPLAY {
++ regulator-name = "DISPLAY";
++ };
++
++ GVDD_reg: GVDD {
++ regulator-name = "GVDD";
++ regulator-min-microvolt = <20000000>;
++ regulator-max-microvolt = <20000000>;
++ };
++
++ GVEE_reg: GVEE {
++ regulator-name = "GVEE";
++ /* 2's-compliment, -22000000 */
++ regulator-min-microvolt = <0xfeb04e80>;
++ regulator-max-microvolt = <0xfeb04e80>;
++ };
++
++ HVINN_reg: HVINN {
++ regulator-name = "HVINN";
++ /* 2's-compliment, -22000000 */
++ regulator-min-microvolt = <0xfeb04e80>;
++ regulator-max-microvolt = <0xfeb04e80>;
++ };
++
++ HVINP_reg: HVINP {
++ regulator-name = "HVINP";
++ regulator-min-microvolt = <20000000>;
++ regulator-max-microvolt = <20000000>;
++ };
++
++ VCOM_reg: VCOM {
++ regulator-name = "VCOM";
++ /* 2's-compliment, -4325000 */
++ regulator-min-microvolt = <0xffbe0178>;
++ /* 2's-compliment, -500000 */
++ regulator-max-microvolt = <0xfff85ee0>;
++ };
++
++ VNEG_reg: VNEG {
++ regulator-name = "VNEG";
++ /* 2's-compliment, -15000000 */
++ regulator-min-microvolt = <0xff1b1e40>;
++ regulator-max-microvolt = <0xff1b1e40>;
++ };
++
++ VPOS_reg: VPOS {
++ regulator-name = "VPOS";
++ regulator-min-microvolt = <15000000>;
++ regulator-max-microvolt = <15000000>;
++ };
++
++ V3P3_reg: V3P3 {
++ regulator-name = "V3P3";
++ };
++ };
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/regulator/pfuze100.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/regulator/pfuze100.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/regulator/pfuze100.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/regulator/pfuze100.txt 2014-05-15 20:33:32.489829966 +0200
+@@ -0,0 +1,115 @@
++PFUZE100 family of regulators
++
++Required properties:
++- compatible: "fsl,pfuze100"
++- reg: I2C slave address
++
++Required child node:
++- regulators: This is the list of child nodes that specify the regulator
++ initialization data for defined regulators. Please refer to below doc
++ Documentation/devicetree/bindings/regulator/regulator.txt.
++
++ The valid names for regulators are:
++ sw1ab,sw1c,sw2,sw3a,sw3b,sw4,swbst,vsnvs,vrefddr,vgen1~vgen6
++
++Each regulator is defined using the standard binding for regulators.
++
++Example:
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/reset/gpio-reset.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/reset/gpio-reset.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/reset/gpio-reset.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/reset/gpio-reset.txt 2014-05-15 20:33:32.493829994 +0200
+@@ -0,0 +1,35 @@
++GPIO reset controller
++=====================
++
++A GPIO reset controller controls a single GPIO that is connected to the reset
++pin of a peripheral IC. Please also refer to reset.txt in this directory for
++common reset controller binding usage.
++
++Required properties:
++- compatible: Should be "gpio-reset"
++- reset-gpios: A gpio used as reset line. The gpio specifier for this property
++ depends on the gpio controller that provides the gpio.
++- #reset-cells: 0, see below
++
++Optional properties:
++- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for
++ this duration to reset.
++- initially-in-reset: boolean. If not set, the initial state should be a
++ deasserted reset line. If this property exists, the
++ reset line should be kept in reset.
++
++example:
++
++sii902x_reset: gpio-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <10000>;
++ initially-in-reset;
++ #reset-cells = <0>;
++};
++
++/* Device with nRESET pin connected to GPIO5_0 */
++sii902x@39 {
++ /* ... */
++ resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/cs42888.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/cs42888.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/cs42888.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/cs42888.txt 2014-05-15 20:33:32.501830053 +0200
+@@ -0,0 +1,29 @@
++CS42888 audio CODEC
++
++This device supports I2C only.
++
++Required properties:
++
++ - compatible: "cirrus,cs42888"
++ - reg: the I2C address of the device.
++ - clocks: Phandle to the clock node.
++ - clock-names: Contains name for each entry in clocks.
++ "codec_osc" : the external oscillator.
++ "esai" : the hckt clock from esai.
++ - <name>-supply: Phandle to the regulator <name>.
++
++Note: cs42888 needs a regulators node and a clocks node.
++
++Example:
++In this case, the clock is external oscillator.
++
++codec: cs42888@48 {
++ compatible = "cirrus,cs42888";
++ reg = <0x048>;
++ clocks = <&codec_osc 0>;
++ clock-names = "codec_osc";
++ VA-supply = <&reg_audio>;
++ VD-supply = <&reg_audio>;
++ VLS-supply = <&reg_audio>;
++ VLC-supply = <&reg_audio>;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/fsl-asrc-p2p.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/fsl-asrc-p2p.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/fsl-asrc-p2p.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/fsl-asrc-p2p.txt 2014-05-15 20:33:32.501830053 +0200
+@@ -0,0 +1,23 @@
++* Freescale Asynchronous Sample Rate Converter (ASRC)
++
++This document is for asrc p2p node. p2p is one of asrc mode. asrc p2p depend on
++MXC_ASRC.
++
++Required properties:
++ - compatible: Should be "fsl,<chip>-asrc-p2p".
++ - fsl,output-rate: the output rate of asrc p2p. which can be <32000> to <192000>,
++ - fsl,output-width: the output width of asrc p2p. which can be <16>, <24>.
++ - fsl,asrc-dma-rx-events: The rx dma event of the asrc, <a b c> corresponding
++ to 3 pair of asrc.
++ - fsl,asrc-dma-tx-events: The tx dma event of the esai, <a b c> corresponding
++ to 3 pair of asrc.
++
++Example:
++asrc_p2p: asrc_p2p {
++ compatible = "fsl,imx6q-asrc-p2p";
++ fsl,output-rate = <48000>;
++ fsl,output-width = <16>;
++ fsl,asrc-dma-rx-events = <17 18 19>;
++ fsl,asrc-dma-tx-events = <20 21 22>;
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/fsl-easi.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/fsl-easi.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/fsl-easi.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/fsl-easi.txt 2014-05-15 20:33:32.501830053 +0200
+@@ -0,0 +1,26 @@
++* Freescale Enhanced Serial Audio Interface (ESAI)
++
++Required properties:
++ - compatible: Should be "fsl,<chip>-esai".
++ - reg: Offset and length of the register set for the device.
++ - interrupts: Contains ESAI interrupt.
++ - clocks: Contains an entry for each entry in clock-names.
++ - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
++ This number is the maximum allowed value for TFCR[TFWM].
++ - fsl,esai-dma-events: The dma event of the esai, <a b>, a is the tx dma.
++ b is the rx dma.
++ - fsl,flags: <1> is for ESAI network mode, <2> is for ESAI SYNC mode.
++ <3> is for network and SYNC mode.
++
++Example:
++
++esai: esai@02024000 {
++ compatible = "fsl,imx6q-esai";
++ reg = <0x02024000 0x4000>;
++ interrupts = <0 51 0x04>;
++ clocks = <&clks 118>;
++ fsl,fifo-depth = <128>;
++ fsl,esai-dma-events = <24 23>;
++ fsl,flags = <1>;
++ status = "disabled";
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/fsl,spdif.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/fsl,spdif.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/fsl,spdif.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/fsl,spdif.txt 2014-05-15 20:33:32.501830053 +0200
+@@ -0,0 +1,54 @@
++Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
++
++The Freescale S/PDIF audio block is a stereo transceiver that allows the
++processor to receive and transmit digital audio via an coaxial cable or
++a fibre cable.
++
++Required properties:
++
++ - compatible : Compatible list, must contain "fsl,imx35-spdif".
++
++ - reg : Offset and length of the register set for the device.
++
++ - interrupts : Contains the spdif interrupt.
++
++ - dmas : Generic dma devicetree binding as described in
++ Documentation/devicetree/bindings/dma/dma.txt.
++
++ - dma-names : Two dmas have to be defined, "tx" and "rx".
++
++ - clocks : Contains an entry for each entry in clock-names.
++
++ - clock-names : Includes the following entries:
++ "core" The core clock of spdif controller
++ "rxtx<0-7>" Clock source list for tx and rx clock.
++ This clock list should be identical to
++ the source list connecting to the spdif
++ clock mux in "SPDIF Transceiver Clock
++ Diagram" of SoC reference manual. It
++ can also be referred to TxClk_Source
++ bit of register SPDIF_STC.
++
++Example:
++
++spdif: spdif@02004000 {
++ compatible = "fsl,imx35-spdif";
++ reg = <0x02004000 0x4000>;
++ interrupts = <0 52 0x04>;
++ dmas = <&sdma 14 18 0>,
++ <&sdma 15 18 0>;
++ dma-names = "rx", "tx";
++
++ clocks = <&clks 197>, <&clks 3>,
++ <&clks 197>, <&clks 107>,
++ <&clks 0>, <&clks 118>,
++ <&clks 62>, <&clks 139>,
++ <&clks 0>;
++ clock-names = "core", "rxtx0",
++ "rxtx1", "rxtx2",
++ "rxtx3", "rxtx4",
++ "rxtx5", "rxtx6",
++ "rxtx7";
++
++ status = "okay";
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt 2014-05-15 20:33:32.501830053 +0200
+@@ -0,0 +1,25 @@
++Freescale i.MX audio complex with CS42888 codec
++
++Required properties:
++- compatible : "fsl,imx-audio-cs42888"
++- model : The user-visible name of this sound complex
++- esai-controller : The phandle of the i.MX SSI controller
++- audio-codec : The phandle of the CS42888 audio codec
++
++Optional properties:
++- asrc-controller : The phandle of the i.MX ASRC controller
++- audio-routing : A list of the connections between audio components.
++ Each entry is a pair of strings, the first being the connection's sink,
++ the second being the connection's source. Valid names could be power
++ supplies, CS42888 pins, and the jacks on the board:
++
++Example:
++
++sound {
++ compatible = "fsl,imx6q-sabresd-wm8962",
++ "fsl,imx-audio-wm8962";
++ model = "cs42888-audio";
++ esai-controller = <&esai>;
++ asrc-controller = <&asrc_p2p>;
++ audio-codec = <&codec>;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt 2014-05-15 20:33:32.501830053 +0200
+@@ -0,0 +1,24 @@
++Freescale i.MX audio complex with si476x codec
++
++Required properties:
++- compatible : "fsl,imx-audio-si476x"
++- model : The user-visible name of this sound complex
++- ssi-controller : The phandle of the i.MX SSI controller
++
++- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
++- mux-ext-port : The external port of the i.MX audio muxer
++
++Note: The AUDMUX port numbering should start at 1, which is consistent with
++hardware manual.
++
++Example:
++
++sound {
++ compatible = "fsl,imx-audio-si476x",
++ "fsl,imx-tuner-si476x";
++ model = "imx-radio-si476x";
++
++ ssi-controller = <&ssi1>;
++ mux-int-port = <2>;
++ mux-ext-port = <5>;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt 2014-05-15 20:33:32.501830053 +0200
+@@ -0,0 +1,34 @@
++Freescale i.MX audio complex with S/PDIF transceiver
++
++Required properties:
++
++ - compatible : "fsl,imx-audio-spdif"
++
++ - model : The user-visible name of this sound complex
++
++ - spdif-controller : The phandle of the i.MX S/PDIF controller
++
++
++Optional properties:
++
++ - spdif-out : This is a boolean property. If present, the transmitting
++ function of S/PDIF will be enabled, indicating there's a physical
++ S/PDIF out connector/jack on the board or it's connecting to some
++ other IP block, such as an HDMI encoder/display-controller.
++
++ - spdif-in : This is a boolean property. If present, the receiving
++ function of S/PDIF will be enabled, indicating there's a physical
++ S/PDIF in connector/jack on the board.
++
++* Note: At least one of these two properties should be set in the DT binding.
++
++
++Example:
++
++sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ spdif-in;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt 2014-05-15 20:33:32.501830053 +0200
+@@ -0,0 +1,54 @@
++Freescale i.MX audio complex with WM8962 codec
++
++Required properties:
++- compatible : "fsl,imx-audio-wm8962"
++- model : The user-visible name of this sound complex
++- ssi-controller : The phandle of the i.MX SSI controller
++- audio-codec : The phandle of the WM8962 audio codec
++- audio-routing : A list of the connections between audio components.
++ Each entry is a pair of strings, the first being the connection's sink,
++ the second being the connection's source. Valid names could be power
++ supplies, WM8962 pins, and the jacks on the board:
++
++ Power supplies:
++ * Mic Bias
++
++ Board connectors:
++ * Mic Jack
++ * Headphone Jack
++ * Ext Spk
++
++- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
++- mux-ext-port : The external port of the i.MX audio muxer
++
++Note: The AUDMUX port numbering should start at 1, which is consistent with
++hardware manual.
++
++Optional properties:
++- hp-det-gpios : The gpio pin to detect plug in/out event that happens to
++ Headphone jack.
++- mic-det-gpios: The gpio pin to detect plug in/out event that happens to
++ Microphone jack.
++
++Example:
++
++sound {
++ compatible = "fsl,imx6q-sabresd-wm8962",
++ "fsl,imx-audio-wm8962";
++ model = "wm8962-audio";
++ ssi-controller = <&ssi2>;
++ audio-codec = <&codec>;
++ audio-routing =
++ "Headphone Jack", "HPOUTL",
++ "Headphone Jack", "HPOUTR",
++ "Ext Spk", "SPKOUTL",
++ "Ext Spk", "SPKOUTR",
++ "MICBIAS", "AMIC",
++ "IN3R", "MICBIAS",
++ "DMIC", "MICBIAS",
++ "DMICDAT", "DMIC";
++ mux-int-port = <2>;
++ mux-ext-port = <3>;
++ hp-det-gpios = <&gpio7 8 1>;
++ mic-det-gpios = <&gpio1 9 1>;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/sound/wm8962.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/wm8962.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/sound/wm8962.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/sound/wm8962.txt 2014-05-15 20:33:32.525830225 +0200
+@@ -8,9 +8,40 @@
+
+ - reg : the I2C address of the device.
+
++Optional properties:
++ - spk-mono: This is a boolean property. If present, the SPK_MONO bit
++ of R51 (Class D Control 2) gets set, indicating that the speaker is
++ in mono mode.
++
++ - amic-mono: This is a boolean property. If present, indicating that the
++ analog micphone is hardware mono input, the driver would enable monomix
++ for it.
++
++ - dmic-mono: This is a boolean property. If present, indicating that the
++ digital micphone is hardware mono input, the driver would enable monomix
++ for it.
++
++ - mic-cfg : Default register value for R48 (Additional Control 4).
++ If absent, the default should be the register default.
++
++ - gpio-cfg : A list of GPIO configuration register values. The list must
++ be 6 entries long. If absent, no configuration of these registers is
++ performed. And note that only the value within [0x0, 0xffff] is valid.
++ Any other value is regarded as setting the GPIO register by its reset
++ value 0x0.
++
+ Example:
+
+ codec: wm8962@1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
++
++ gpio-cfg = <
++ 0x0000 /* 0:Default */
++ 0x0000 /* 1:Default */
++ 0x0013 /* 2:FN_DMICCLK */
++ 0x0000 /* 3:Default */
++ 0x8014 /* 4:FN_DMICCDAT */
++ 0x0000 /* 5:Default */
++ >;
+ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/spi/spi-bus.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/spi/spi-bus.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/spi/spi-bus.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/spi/spi-bus.txt 2014-05-15 20:33:32.529830254 +0200
+@@ -55,6 +55,16 @@
+ chip select active high
+ - spi-3wire - (optional) Empty property indicating device requires
+ 3-wire mode.
++- spi-tx-bus-width - (optional) The bus width(number of data wires) that
++ used for MOSI. Defaults to 1 if not present.
++- spi-rx-bus-width - (optional) The bus width(number of data wires) that
++ used for MISO. Defaults to 1 if not present.
++
++Some SPI controllers and devices support Dual and Quad SPI transfer mode.
++It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
++Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
++only 1(SINGLE), 2(DUAL) and 4(QUAD).
++Dual/Quad mode is not allowed when 3-wire mode is used.
+
+ If a gpio chipselect is used for the SPI slave the gpio number will be passed
+ via the cs_gpio
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/thermal/imx-thermal.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/thermal/imx-thermal.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/thermal/imx-thermal.txt 2014-05-15 20:33:32.585830658 +0200
+@@ -0,0 +1,17 @@
++* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
++
++Required properties:
++- compatible : "fsl,imx6q-thermal"
++- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
++ control registers, e.g. ANATOP on imx6q.
++- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
++ calibration data, e.g. OCOTP on imx6q. The details about calibration data
++ can be found in SoC Reference Manual.
++
++Example:
++
++tempmon {
++ compatible = "fsl,imx6q-tempmon";
++ fsl,tempmon = <&anatop>;
++ fsl,tempmon-data = <&ocotp>;
++};
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt 2014-05-15 20:33:32.589830686 +0200
+@@ -8,6 +8,8 @@
+ Optional properties:
+ - fsl,uart-has-rtscts : Indicate the uart has rts and cts
+ - fsl,irda-mode : Indicate the uart supports irda mode
++- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
++ is DCE mode by default.
+
+ Example:
+
+@@ -16,4 +18,5 @@
+ reg = <0x73fbc000 0x4000>;
+ interrupts = <31>;
+ fsl,uart-has-rtscts;
++ fsl,dte-mode;
+ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt 2014-05-15 20:33:32.589830686 +0200
+@@ -0,0 +1,14 @@
++* Freescale low power universal asynchronous receiver/transmitter (lpuart)
++
++Required properties:
++- compatible : Should be "fsl,<soc>-lpuart"
++- reg : Address and length of the register set for the device
++- interrupts : Should contain uart interrupt
++
++Example:
++
++uart0: serial@40027000 {
++ compatible = "fsl,vf610-lpuart";
++ reg = <0x40027000 0x1000>;
++ interrupts = <0 61 0x00>;
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt 2014-05-15 20:33:32.589830686 +0200
+@@ -5,6 +5,12 @@
+ - reg: Should contain registers location and length
+ - interrupts: Should contain controller interrupt
+
++Recommended properies:
++- phy_type: the type of the phy connected to the core. Should be one
++ of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
++ property the PORTSC register won't be touched
++- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
++
+ Optional properties:
+ - fsl,usbphy: phandler of usb phy that connects to the only one port
+ - fsl,usbmisc: phandler of non-core register device, with one argument
+@@ -12,6 +18,12 @@
+ - vbus-supply: regulator for vbus
+ - disable-over-current: disable over current detect
+ - external-vbus-divider: enables off-chip resistor divider for Vbus
++- imx6-usb-charger-detection: enable imx6 usb charger detect function,
++only set it when the user wants SoC usb charger detection capabilities.
++If the user wants to use charger IC's usb charger detection capabilities,
++please do not set it.
++- fsl,anatop: phandle for anatop module, anatop module is only existed
++at imx6 SoC series
+
+ Examples:
+ usb@02184000 { /* USB OTG */
+@@ -22,4 +34,6 @@
+ fsl,usbmisc = <&usbmisc 0>;
+ disable-over-current;
+ external-vbus-divider;
++ imx6-usb-charger-detection;
++ fsl,anatop = <&anatop>;
+ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/usb/mxs-phy.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/usb/mxs-phy.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/usb/mxs-phy.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/usb/mxs-phy.txt 2014-05-15 20:33:32.589830686 +0200
+@@ -1,13 +1,16 @@
+ * Freescale MXS USB Phy Device
+
+ Required properties:
+-- compatible: Should be "fsl,imx23-usbphy"
++- compatible: "fsl,imx23-usbphy" for imx23 and imx28, "fsl,imx6q-usbphy"
++for imx6dq and imx6dl, "fsl,imx6sl-usbphy" for imx6sl
+ - reg: Should contain registers location and length
+ - interrupts: Should contain phy interrupt
++- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series
+
+ Example:
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <0 44 0x04>;
++ fsl,anatop = <&anatop>;
+ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/video/fsl,csi-v4l2-capture.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/fsl,csi-v4l2-capture.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/video/fsl,csi-v4l2-capture.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/fsl,csi-v4l2-capture.txt 2014-05-15 20:33:32.613830860 +0200
+@@ -0,0 +1,61 @@
++* Freescale CMOS Sensor Interface (CSI) V4L2 Capture
++
++Required properties for CSI
++- compatible: "fsl,<soc>-csi". Supported chip includes imx6sl
++- reg: Address and length of the register set for CSI
++- interrupts: Should contain CSI interrupts
++
++Required properties for v4l2_capture
++- compatible: should be "fsl,<soc>-csi-v4l2", supported socs include imx6sl
++
++Required properties for sensor
++- compatible: "<vendor>,<sensor>"
++ please check the supported sensor in the Supported Sensor fields.
++- reg: sensor I2C slave address
++- pinctrl-names: should be "default" for parallel sensor
++- pinctrl-0: should depend on the connection between sensor and i.MX
++ connection between sensor and i.MX could be only legacy parallel on i.MX6SL
++- clocks: should be the clock source provided to sensor.
++- clock-names: should be "csi_mclk"
++- AVDD-supply: set according to the board.
++- DVDD-supply: set according to the board.
++- pwn-gpios: set according to the board.
++- rst-gpios: set according to the board.
++- csi_id: csi id for v4l2 capture device
++ should be 0 for i.MX6SL
++- mclk: should the value of mclk clock send out the sensor. unit is Hz.
++- mclk_source: should be 0 for i.MX6SL
++
++Supported Sensor
++- ovti, ov5640
++
++Example for CSI:
++ csi: csi@020e4000 {
++ compatible = "fsl,imx6sl-csi";
++ reg = <0x020e4000 0x4000>;
++ interrupts = <0 7 0x04>;
++ status = "disabled";
++ };
++
++Examples for v4l2_capture:
++ csi_v4l2_cap {
++ compatible = "fsl,imx6q-v4l2-capture";
++ status = "okay";
++ };
++
++Examples for sensors:
++ ov564x: ov564x@3c {
++ compatible = "ovti,ov564x";
++ reg = <0x3c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_csi_0>;
++ clocks = <&clks IMX6SL_CLK_CSI>;
++ clock-names = "csi_mclk";
++ AVDD-supply = <&vgen6_reg>; /* 2.8v */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio1 25 1>;
++ rst-gpios = <&gpio1 26 0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/fsl,mipi-csi2.txt 2014-05-15 20:33:32.629830976 +0200
+@@ -0,0 +1,42 @@
++* Freescale MIPI CSI2 Controller for i.MX6DQ/i.MX6SDL
++
++Required properties for mipi csi2 controller:
++- compatible: should be "fsl,imx6q-mipi-csi2"
++- reg: <base addr, range> contains mipi csi2 register base address and range
++- interrupts: <type num flag> where type is a interrupt type, num is the
++ interrupt number and flag is a field that level/trigger information for
++ the interrupt.
++- clocks: the clock sources that mipi csi2 depends on.
++- clock-names: the name is related to the clock source one by one.
++- status: should be set to "disable".
++
++Required properties for mipi csi2 on specified board:
++- ipu_id: ipu id which mipi csi2 connected to.
++ should be 0 or 1 for i.MX6DQ; should be 0 for i.MX6SDL
++- csi_id: csi id which mipi csi2 connected to.
++ should be 0 or 1 for i.MX6DQ/i.MX6SDL
++- v_channel: virtual channel which send to MIPI CSI2 controller
++ should keep consistent with the input MIPI signal.
++- lanes: data lanes of input MIPI signal. The maximum data lanes is 4.
++ should keep consistent with the input MIPI signal.
++- status: should be set to "okay".
++
++Examples:
++for SOC imx6qdl.dtsi:
++ mipi_csi@021dc000 {
++ compatible = "fsl,imx6q-mipi-csi2";
++ reg = <0x021dc000 0x4000>;
++ interrupts = <0 100 0x04>, <0 101 0x04>;
++ clocks = <&clks 138>, <&clks 53>;
++ clock-names = "dphy_clk", "pixel_clk";
++ status = "disabled";
++ };
++
++for board imx6qdl-sabresd.dtsi:
++ mipi_csi@021dc000 {
++ status = "okay";
++ ipu_id = <0>;
++ csi_id = <1>;
++ v_channel = <0>;
++ lanes = <2>;
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/video/fsl,pxp.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/fsl,pxp.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/video/fsl,pxp.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/fsl,pxp.txt 2014-05-15 20:33:32.629830976 +0200
+@@ -0,0 +1,30 @@
++* Freescale PxP Controller for i.MX6DL, i.MX6SL
++
++Required properties for PxP controller:
++- compatible: should be "fsl,<soc>-pxp-dma"
++- reg: <base addr, range> contains pxp register base address and range
++- interrupts: <type num flag> where type is an interrupt type, num is the
++ interrupt number and flag is a field that level/trigger information for
++ the interrupt.
++- clocks: the clock sources that pxp depends on.
++- clock-names: the name is related to the clock source
++
++Required properties for pxp on specified board:
++- status: should be set to "okay" if want to use PxP
++
++Examples:
++for SOC imx6dl.dtsi:
++ pxp@020f0000 {
++ compatible = "fsl,imx6dl-pxp-dma";
++ reg = <0x020f0000 0x4000>;
++ interrupts = <0 98 0x04>;
++ clocks = <&clks 133>;
++ clock-names = "pxp-axi";
++ status = "disabled";
++ };
++
++
++for board imx6dl-sabresd.dts:
++ &pxp {
++ status = "okay";
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/video/fsl,v4l2-capture.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/fsl,v4l2-capture.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/video/fsl,v4l2-capture.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/fsl,v4l2-capture.txt 2014-05-15 20:33:32.629830976 +0200
+@@ -0,0 +1,102 @@
++* Freescale V4L2 Capture for i.MX6DQ/i.MX6SDL
++
++Required board properties for IPUv3 capture:
++- clocks: should include the clock provided by i.MX6 to sensor
++- clock-names: sensor clock's name should be "ipux_csiy"
++ x should be 1 or 2 for i.MX6DQ; should be 1 for i.MX6SDL
++ y is 0 or 1 for i.MX6DQ/i.MX6SDL
++Note: other detailed information for IPUv3, please refer to
++Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt
++
++Required properties for v4l2_capture
++- compatible: should be "fsl,imx6q-v4l2-capture"
++- ipu_id: ipu id for v4l2 capture device
++ should be 0 or 1 for i.MX6DQ; should be 0 for i.MX6SDL
++- csi_id: csi id for v4l2 capture device
++ should be 0 or 1 for i.MX6DQ/i.MX6SDL
++- mclk_source: should be 0 or 1. two mclk sources at most now
++- status: should be set to "okay" to enable this device
++
++Required properties for sensor
++- compatible: "<vendor>,<sensor>"
++ please check the supported sensor in the Supported Sensor fields.
++- reg: sensor I2C slave address
++- pinctrl-names: should be "default" for parallel sensor
++- pinctrl-0: should depend on the connection between sensor and i.MX
++ connection between sensor and i.MX could be MIPI-CSI2 or legacy parallel
++- clocks: should be the clock source provided to sensor.
++- clock-names: should be "csi_mclk"
++- DOVDD-supply: set according to the board.
++- AVDD-supply: set according to the board.
++- DVDD-supply: set according to the board.
++- pwn-gpios: set according to the board.
++- rst-gpios: set according to the board.
++- csi_id: csi id for v4l2 capture device
++ should be 0 or 1 for i.MX6DQ/i.MX6SDL.
++- mclk: should the value of mclk clock send out the sensor. unit is Hz.
++- mclk_source: should be 0 or 1 and should be the same as the setting in
++ v4l2_capture.
++- cvbs: 1 for CVBS input, 0 YPbPr input. This property is only needed for
++ adv7180 tv decoder.
++
++Supported Sensor
++- ov5640
++- ov5642
++- ov5640_mipi
++- adv7180
++
++
++Example for IPUv3 including capture settings on imx6q-sabresd.dts:
++ ipu1: ipu@02400000 { /* IPU1 */
++ compatible = "fsl,imx6q-ipuv3";
++ reg = <0x02400000 0x400000>;
++ interrupts = <0 5 0x04>, < 0 6 0x04>;
++ clocks = <&clks 130>, <&clks 131>, <&clks 132>, <&clks 39>, <&clks 40>, <&clks 169>;
++ clock-names = "ipu1", "ipu1_di0", "ipu1_di1", "ipu1_di0_sel", "ipu1_di1_sel", "ipu1_csi0";
++ status = "disabled";
++ };
++
++Examples for v4l2_capture:
++ v4l2_cap {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++Examples for sensors:
++ ov5642: ov5642@3c {
++ compatible = "ovti,ov5642";
++ reg = <0x3c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_2>;
++ clocks = <&clks 201>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
++ AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3 */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */
++ rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ };
++
++ adv7180: adv7180@21 {
++ compatible = "adv,adv7180";
++ reg = <0x21>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_3>;
++ clocks = <&clks 201>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
++ AVDD-supply = <&reg_3p3v>; /* 1.8v */
++ DVDD-supply = <&reg_3p3v>; /* 1.8v */
++ PVDD-supply = <&reg_3p3v>; /* 1.8v */
++ pwn-gpios = <&max7310_b 2 0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ cvbs = <1>;
++ };
+diff -Nur linux-3.10.30.orig/Documentation/devicetree/bindings/video/mxc_hdmi_video.txt linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/mxc_hdmi_video.txt
+--- linux-3.10.30.orig/Documentation/devicetree/bindings/video/mxc_hdmi_video.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/devicetree/bindings/video/mxc_hdmi_video.txt 2014-05-15 20:33:32.629830976 +0200
+@@ -0,0 +1,20 @@
++Device-Tree bindings for hdmi video driver
++
++Required properties:
++- compatible: value should be "fsl,imx6q-hdmi-video".
++- fsl,hdcp: define the property in dts, hdmi driver will initalize for hdcp,
++ otherwise hdcp function will not supported.
++- fsl,phy_reg_vlev: hdmi phy register,Voltage Level Control Register offset 0x0e,
++ adjust hdmi phy signal voltage level.
++- fsl,phy_reg_cksymtx: hdmi phy register, clock symbol and transmitter control
++ register offset 0x09, adjust hdmi signal pre-emphasis.
++
++Example:
++
++ hdmi_video {
++ compatible = "fsl,imx6q-hdmi-video";
++ fsl,hdcp;
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ };
++
+diff -Nur linux-3.10.30.orig/Documentation/DocBook/mtdnand.tmpl linux-linaro-stable-mx6/Documentation/DocBook/mtdnand.tmpl
+--- linux-3.10.30.orig/Documentation/DocBook/mtdnand.tmpl 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/DocBook/mtdnand.tmpl 2014-05-15 20:33:31.737824541 +0200
+@@ -1222,10 +1222,6 @@
+ #define NAND_BBT_VERSION 0x00000100
+ /* Create a bbt if none axists */
+ #define NAND_BBT_CREATE 0x00000200
+-/* Search good / bad pattern through all pages of a block */
+-#define NAND_BBT_SCANALLPAGES 0x00000400
+-/* Scan block empty during good / bad block scan */
+-#define NAND_BBT_SCANEMPTY 0x00000800
+ /* Write bbt if neccecary */
+ #define NAND_BBT_WRITE 0x00001000
+ /* Read and write back block contents when writing bbt */
+diff -Nur linux-3.10.30.orig/Documentation/driver-model/devres.txt linux-linaro-stable-mx6/Documentation/driver-model/devres.txt
+--- linux-3.10.30.orig/Documentation/driver-model/devres.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/driver-model/devres.txt 2014-05-15 20:33:32.653831149 +0200
+@@ -293,3 +293,6 @@
+ PHY
+ devm_usb_get_phy()
+ devm_usb_put_phy()
++
++SPI
++ devm_spi_register_master()
+diff -Nur linux-3.10.30.orig/Documentation/kernel-parameters.txt linux-linaro-stable-mx6/Documentation/kernel-parameters.txt
+--- linux-3.10.30.orig/Documentation/kernel-parameters.txt 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/kernel-parameters.txt 2014-05-15 20:33:33.053834033 +0200
+@@ -1240,6 +1240,15 @@
+ See comment before ip2_setup() in
+ drivers/char/ip2/ip2base.c.
+
++ irqaffinity= [SMP] Set the default irq affinity mask
++ Format:
++ <cpu number>,...,<cpu number>
++ or
++ <cpu number>-<cpu number>
++ (must be a positive range in ascending order)
++ or a mixture
++ <cpu number>,...,<cpu number>-<cpu number>
++
+ irqfixup [HW]
+ When an interrupt is not handled search all handlers
+ for it. Intended to get systems with badly broken
+@@ -3345,6 +3354,21 @@
+ that this also can be controlled per-workqueue for
+ workqueues visible under /sys/bus/workqueue/.
+
++ workqueue.power_efficient
++ Per-cpu workqueues are generally preferred because
++ they show better performance thanks to cache
++ locality; unfortunately, per-cpu workqueues tend to
++ be more power hungry than unbound workqueues.
++
++ Enabling this makes the per-cpu workqueues which
++ were observed to contribute significantly to power
++ consumption unbound, leading to measurably lower
++ power usage at the cost of small performance
++ overhead.
++
++ The default value of this parameter is determined by
++ the config option CONFIG_WQ_POWER_EFFICIENT_DEFAULT.
++
+ x2apic_phys [X86-64,APIC] Use x2apic physical mode instead of
+ default x2apic cluster mode on platforms
+ supporting x2apic.
+diff -Nur linux-3.10.30.orig/Documentation/vm/zswap.txt linux-linaro-stable-mx6/Documentation/vm/zswap.txt
+--- linux-3.10.30.orig/Documentation/vm/zswap.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/Documentation/vm/zswap.txt 2014-05-15 20:33:33.625838158 +0200
+@@ -0,0 +1,72 @@
++Overview:
++
++Zswap is a lightweight compressed cache for swap pages. It takes pages that are
++in the process of being swapped out and attempts to compress them into a
++dynamically allocated RAM-based memory pool. If this process is successful,
++the writeback to the swap device is deferred and, in many cases, avoided
++completely. This results in a significant I/O reduction and performance gains
++for systems that are swapping.
++
++Zswap provides compressed swap caching that basically trades CPU cycles for
++reduced swap I/O. This trade-off can result in a significant performance
++improvement as reads to/writes from to the compressed cache almost always
++faster that reading from a swap device which incurs the latency of an
++asynchronous block I/O read.
++
++Some potential benefits:
++* Desktop/laptop users with limited RAM capacities can mitigate the
++ performance impact of swapping.
++* Overcommitted guests that share a common I/O resource can
++ dramatically reduce their swap I/O pressure, avoiding heavy handed I/O
++ throttling by the hypervisor. This allows more work to get done with less
++ impact to the guest workload and guests sharing the I/O subsystem
++* Users with SSDs as swap devices can extend the life of the device by
++ drastically reducing life-shortening writes.
++
++Zswap evicts pages from compressed cache on an LRU basis to the backing swap
++device when the compressed pool reaches it size limit. This requirement had
++been identified in prior community discussions.
++
++To enabled zswap, the "enabled" attribute must be set to 1 at boot time. e.g.
++zswap.enabled=1
++
++Design:
++
++Zswap receives pages for compression through the Frontswap API and is able to
++evict pages from its own compressed pool on an LRU basis and write them back to
++the backing swap device in the case that the compressed pool is full.
++
++Zswap makes use of zbud for the managing the compressed memory pool. Each
++allocation in zbud is not directly accessible by address. Rather, a handle is
++return by the allocation routine and that handle must be mapped before being
++accessed. The compressed memory pool grows on demand and shrinks as compressed
++pages are freed. The pool is not preallocated.
++
++When a swap page is passed from frontswap to zswap, zswap maintains a mapping
++of the swap entry, a combination of the swap type and swap offset, to the zbud
++handle that references that compressed swap page. This mapping is achieved
++with a red-black tree per swap type. The swap offset is the search key for the
++tree nodes.
++
++During a page fault on a PTE that is a swap entry, frontswap calls the zswap
++load function to decompress the page into the page allocated by the page fault
++handler.
++
++Once there are no PTEs referencing a swap page stored in zswap (i.e. the count
++in the swap_map goes to 0) the swap code calls the zswap invalidate function,
++via frontswap, to free the compressed entry.
++
++Zswap seeks to be simple in its policies. Sysfs attributes allow for two user
++controlled policies:
++* max_compression_ratio - Maximum compression ratio, as as percentage,
++ for an acceptable compressed page. Any page that does not compress by at
++ least this ratio will be rejected.
++* max_pool_percent - The maximum percentage of memory that the compressed
++ pool can occupy.
++
++Zswap allows the compressor to be selected at kernel boot time by setting the
++“compressor” attribute. The default compressor is lzo. e.g.
++zswap.compressor=deflate
++
++A debugfs interface is provided for various statistic about pool size, number
++of pages stored, and various counters for the reasons pages are rejected.
+diff -Nur linux-3.10.30.orig/drivers/ata/ahci.h linux-linaro-stable-mx6/drivers/ata/ahci.h
+--- linux-3.10.30.orig/drivers/ata/ahci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/ata/ahci.h 2014-05-15 20:33:45.049920537 +0200
+@@ -337,6 +337,7 @@
+ .sdev_attrs = ahci_sdev_attrs
+
+ extern struct ata_port_operations ahci_ops;
++extern struct ata_port_operations ahci_platform_ops;
+ extern struct ata_port_operations ahci_pmp_retry_srst_ops;
+
+ unsigned int ahci_dev_classify(struct ata_port *ap);
+@@ -366,6 +367,7 @@
+ irqreturn_t ahci_thread_fn(int irq, void *dev_instance);
+ void ahci_print_info(struct ata_host *host, const char *scc_s);
+ int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis);
++void ahci_error_handler(struct ata_port *ap);
+
+ static inline void __iomem *__ahci_port_base(struct ata_host *host,
+ unsigned int port_no)
+diff -Nur linux-3.10.30.orig/drivers/ata/ahci_imx.c linux-linaro-stable-mx6/drivers/ata/ahci_imx.c
+--- linux-3.10.30.orig/drivers/ata/ahci_imx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/ata/ahci_imx.c 2014-05-15 20:33:45.049920537 +0200
+@@ -0,0 +1,351 @@
++/*
++ * copyright (c) 2013 Freescale Semiconductor, Inc.
++ * Freescale IMX AHCI SATA platform driver
++ *
++ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/ahci_platform.h>
++#include <linux/of_device.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/libata.h>
++#include <linux/busfreq-imx6.h>
++#include "ahci.h"
++
++enum {
++ PORT_PHY_CTL = 0x178, /* Port0 PHY Control */
++ PORT_PHY_CTL_PDDQ_LOC = 0x100000, /* PORT_PHY_CTL bits */
++ HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
++};
++
++struct imx_ahci_priv {
++ struct platform_device *ahci_pdev;
++ struct clk *sata_ref_clk;
++ struct clk *ahb_clk;
++ struct regmap *gpr;
++ bool no_device;
++ bool first_time;
++};
++
++static int ahci_imx_hotplug;
++module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
++MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
++
++static void ahci_imx_error_handler(struct ata_port *ap)
++{
++ u32 reg_val;
++ struct ata_device *dev;
++ struct ata_host *host = dev_get_drvdata(ap->dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++ void __iomem *mmio = hpriv->mmio;
++ struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
++
++ ahci_error_handler(ap);
++
++ if (!(imxpriv->first_time) || ahci_imx_hotplug)
++ return;
++
++ imxpriv->first_time = false;
++
++ ata_for_each_dev(dev, &ap->link, ENABLED)
++ return;
++ /*
++ * Disable link to save power. An imx ahci port can't be recovered
++ * without full reset once the pddq mode is enabled making it
++ * impossible to use as part of libata LPM.
++ */
++ reg_val = readl(mmio + PORT_PHY_CTL);
++ writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
++ regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
++ IMX6Q_GPR13_SATA_MPLL_CLK_EN,
++ !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
++ clk_disable_unprepare(imxpriv->sata_ref_clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++ imxpriv->no_device = true;
++
++ dev_info(ap->dev, "no device found, disabling link.\n");
++ dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX
++ ".hotplug=1 to enable hotplug\n");
++}
++
++static struct ata_port_operations ahci_imx_ops = {
++ .inherits = &ahci_platform_ops,
++ .error_handler = ahci_imx_error_handler,
++};
++
++static const struct ata_port_info ahci_imx_port_info = {
++ .flags = AHCI_FLAG_COMMON,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &ahci_imx_ops,
++};
++
++static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
++{
++ int ret = 0;
++ unsigned int reg_val;
++ struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
++
++ imxpriv->gpr =
++ syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (IS_ERR(imxpriv->gpr)) {
++ dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
++ return PTR_ERR(imxpriv->gpr);
++ }
++
++ ret = clk_prepare_enable(imxpriv->sata_ref_clk);
++ if (ret < 0) {
++ dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
++ return ret;
++ }
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ /*
++ * set PHY Paremeters, two steps to configure the GPR13,
++ * one write for rest of parameters, mask of first write
++ * is 0x07fffffd, and the other one write for setting
++ * the mpll_clk_en.
++ */
++ regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
++ | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
++ | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
++ | IMX6Q_GPR13_SATA_SPD_MODE_MASK
++ | IMX6Q_GPR13_SATA_MPLL_SS_EN
++ | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
++ | IMX6Q_GPR13_SATA_TX_BOOST_MASK
++ | IMX6Q_GPR13_SATA_TX_LVL_MASK
++ | IMX6Q_GPR13_SATA_TX_EDGE_RATE
++ , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
++ | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
++ | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
++ | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
++ | /* IMX6Q_GPR13_SATA_MPLL_SS_EN */ 0
++ | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
++ | /* IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
++ | IMX6Q_GPR13_SATA_TX_LVL_1_025_V */
++ IMX6Q_GPR13_SATA_TX_LVL_1_104_V);
++ regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
++ IMX6Q_GPR13_SATA_MPLL_CLK_EN);
++ usleep_range(100, 200);
++
++ /*
++ * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
++ * and IP vendor specific register HOST_TIMER1MS.
++ * Configure CAP_SSS (support stagered spin up).
++ * Implement the port0.
++ * Get the ahb clock rate, and configure the TIMER1MS register.
++ */
++ reg_val = readl(mmio + HOST_CAP);
++ if (!(reg_val & HOST_CAP_SSS)) {
++ reg_val |= HOST_CAP_SSS;
++ writel(reg_val, mmio + HOST_CAP);
++ }
++ reg_val = readl(mmio + HOST_PORTS_IMPL);
++ if (!(reg_val & 0x1)) {
++ reg_val |= 0x1;
++ writel(reg_val, mmio + HOST_PORTS_IMPL);
++ }
++
++ reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
++ writel(reg_val, mmio + HOST_TIMER1MS);
++
++ return 0;
++}
++
++static void imx6q_sata_exit(struct device *dev)
++{
++ struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
++
++ if (!imxpriv->no_device) {
++ regmap_update_bits(imxpriv->gpr, 0x34,
++ IMX6Q_GPR13_SATA_MPLL_CLK_EN,
++ !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
++ clk_disable_unprepare(imxpriv->sata_ref_clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++ }
++}
++
++static int imx_ahci_suspend(struct device *dev)
++{
++ struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
++
++ /*
++ * If no_device is set, The CLKs had been gated off in the
++ * initialization so don't do it again here.
++ */
++ if (!imxpriv->no_device) {
++ regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
++ IMX6Q_GPR13_SATA_MPLL_CLK_EN,
++ !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
++ clk_disable_unprepare(imxpriv->sata_ref_clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++ }
++
++ return 0;
++}
++
++static int imx_ahci_resume(struct device *dev)
++{
++ struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
++ int ret;
++
++ if (!imxpriv->no_device) {
++ ret = clk_prepare_enable(imxpriv->sata_ref_clk);
++ if (ret < 0) {
++ dev_err(dev, "pre-enable sata_ref clock err:%d\n", ret);
++ return ret;
++ }
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
++ IMX6Q_GPR13_SATA_MPLL_CLK_EN,
++ IMX6Q_GPR13_SATA_MPLL_CLK_EN);
++ usleep_range(1000, 2000);
++ }
++
++ return 0;
++}
++
++static struct ahci_platform_data imx6q_sata_pdata = {
++ .init = imx6q_sata_init,
++ .exit = imx6q_sata_exit,
++ .ata_port_info = &ahci_imx_port_info,
++ .suspend = imx_ahci_suspend,
++ .resume = imx_ahci_resume,
++};
++
++static const struct of_device_id imx_ahci_of_match[] = {
++ { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata},
++ {},
++};
++MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
++
++static int imx_ahci_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct resource *mem, *irq, res[2];
++ const struct of_device_id *of_id;
++ const struct ahci_platform_data *pdata = NULL;
++ struct imx_ahci_priv *imxpriv;
++ struct device *ahci_dev;
++ struct platform_device *ahci_pdev;
++ int ret;
++
++ /* Prevent our child ahci device coming back to us */
++ if (!strcmp(dev_name(&pdev->dev), "ahci"))
++ return -ENODEV;
++
++ imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
++ if (!imxpriv) {
++ dev_err(dev, "can't alloc ahci_host_priv\n");
++ return -ENOMEM;
++ }
++
++ ahci_pdev = platform_device_alloc("ahci", -1);
++ if (!ahci_pdev)
++ return -ENODEV;
++
++ ahci_dev = &ahci_pdev->dev;
++ ahci_dev->parent = dev;
++
++ imxpriv->no_device = false;
++ imxpriv->first_time = true;
++ imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
++ if (IS_ERR(imxpriv->ahb_clk)) {
++ dev_err(dev, "can't get ahb clock.\n");
++ ret = PTR_ERR(imxpriv->ahb_clk);
++ goto err_out;
++ }
++
++ imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
++ if (IS_ERR(imxpriv->sata_ref_clk)) {
++ dev_err(dev, "can't get sata_ref clock.\n");
++ ret = PTR_ERR(imxpriv->sata_ref_clk);
++ goto err_out;
++ }
++
++ imxpriv->ahci_pdev = ahci_pdev;
++ platform_set_drvdata(pdev, imxpriv);
++
++ of_id = of_match_device(imx_ahci_of_match, dev);
++ if (of_id) {
++ pdata = of_id->data;
++ } else {
++ ret = -EINVAL;
++ goto err_out;
++ }
++
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (!mem || !irq) {
++ dev_err(dev, "no mmio/irq resource\n");
++ ret = -ENOMEM;
++ goto err_out;
++ }
++
++ res[0] = *mem;
++ res[1] = *irq;
++
++ ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
++ ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
++ ahci_dev->of_node = dev->of_node;
++
++ ret = platform_device_add_resources(ahci_pdev, res, 2);
++ if (ret)
++ goto err_out;
++
++ ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
++ if (ret)
++ goto err_out;
++
++ ret = platform_device_add(ahci_pdev);
++ if (ret) {
++err_out:
++ platform_device_put(ahci_pdev);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int imx_ahci_remove(struct platform_device *pdev)
++{
++ struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
++ struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
++
++ platform_device_unregister(ahci_pdev);
++ return 0;
++}
++
++static struct platform_driver imx_ahci_driver = {
++ .probe = imx_ahci_probe,
++ .remove = imx_ahci_remove,
++ .driver = {
++ .name = "ahci-imx",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_ahci_of_match,
++ },
++};
++module_platform_driver(imx_ahci_driver);
++
++MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
++MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("ahci:imx");
+diff -Nur linux-3.10.30.orig/drivers/ata/ahci_platform.c linux-linaro-stable-mx6/drivers/ata/ahci_platform.c
+--- linux-3.10.30.orig/drivers/ata/ahci_platform.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/ata/ahci_platform.c 2014-05-15 20:33:45.049920537 +0200
+@@ -49,10 +49,11 @@
+ };
+ MODULE_DEVICE_TABLE(platform, ahci_devtype);
+
+-static struct ata_port_operations ahci_platform_ops = {
++struct ata_port_operations ahci_platform_ops = {
+ .inherits = &ahci_ops,
+ .host_stop = ahci_host_stop,
+ };
++EXPORT_SYMBOL_GPL(ahci_platform_ops);
+
+ static struct ata_port_operations ahci_platform_retry_srst_ops = {
+ .inherits = &ahci_pmp_retry_srst_ops,
+diff -Nur linux-3.10.30.orig/drivers/ata/Kconfig linux-linaro-stable-mx6/drivers/ata/Kconfig
+--- linux-3.10.30.orig/drivers/ata/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/ata/Kconfig 2014-05-15 20:33:45.045920509 +0200
+@@ -97,6 +97,15 @@
+
+ If unsure, say N.
+
++config AHCI_IMX
++ tristate "Freescale i.MX AHCI SATA support"
++ depends on SATA_AHCI_PLATFORM
++ help
++ This option enables support for the Freescale i.MX SoC's
++ onboard AHCI SATA.
++
++ If unsure, say N.
++
+ config SATA_FSL
+ tristate "Freescale 3.0Gbps SATA support"
+ depends on FSL_SOC
+diff -Nur linux-3.10.30.orig/drivers/ata/libahci.c linux-linaro-stable-mx6/drivers/ata/libahci.c
+--- linux-3.10.30.orig/drivers/ata/libahci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/ata/libahci.c 2014-05-15 20:33:45.049920537 +0200
+@@ -89,7 +89,6 @@
+ static int ahci_hardreset(struct ata_link *link, unsigned int *class,
+ unsigned long deadline);
+ static void ahci_postreset(struct ata_link *link, unsigned int *class);
+-static void ahci_error_handler(struct ata_port *ap);
+ static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
+ static void ahci_dev_config(struct ata_device *dev);
+ #ifdef CONFIG_PM
+@@ -1996,7 +1995,7 @@
+ writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
+ }
+
+-static void ahci_error_handler(struct ata_port *ap)
++void ahci_error_handler(struct ata_port *ap)
+ {
+ if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
+ /* restart engine */
+@@ -2009,6 +2008,7 @@
+ if (!ata_dev_enabled(ap->link.device))
+ ahci_stop_engine(ap);
+ }
++EXPORT_SYMBOL_GPL(ahci_error_handler);
+
+ static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
+ {
+diff -Nur linux-3.10.30.orig/drivers/ata/Makefile linux-linaro-stable-mx6/drivers/ata/Makefile
+--- linux-3.10.30.orig/drivers/ata/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/ata/Makefile 2014-05-15 20:33:45.045920509 +0200
+@@ -10,6 +10,7 @@
+ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
+ obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
+ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
++obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
+
+ # SFF w/ custom DMA
+ obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
+diff -Nur linux-3.10.30.orig/drivers/base/base.h linux-linaro-stable-mx6/drivers/base/base.h
+--- linux-3.10.30.orig/drivers/base/base.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/base/base.h 2014-05-15 20:33:45.257922037 +0200
+@@ -119,6 +119,11 @@
+ return drv->bus->match ? drv->bus->match(dev, drv) : 1;
+ }
+
++extern int device_add_groups(struct device *dev,
++ const struct attribute_group **groups);
++extern void device_remove_groups(struct device *dev,
++ const struct attribute_group **groups);
++
+ extern char *make_class_name(const char *name, struct kobject *kobj);
+
+ extern int devres_release_all(struct device *dev);
+diff -Nur linux-3.10.30.orig/drivers/base/bus.c linux-linaro-stable-mx6/drivers/base/bus.c
+--- linux-3.10.30.orig/drivers/base/bus.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/base/bus.c 2014-05-15 20:33:45.277922181 +0200
+@@ -499,6 +499,9 @@
+ error = device_add_attrs(bus, dev);
+ if (error)
+ goto out_put;
++ error = device_add_groups(dev, bus->dev_groups);
++ if (error)
++ goto out_groups;
+ error = sysfs_create_link(&bus->p->devices_kset->kobj,
+ &dev->kobj, dev_name(dev));
+ if (error)
+@@ -513,6 +516,8 @@
+
+ out_subsys:
+ sysfs_remove_link(&bus->p->devices_kset->kobj, dev_name(dev));
++out_groups:
++ device_remove_groups(dev, bus->dev_groups);
+ out_id:
+ device_remove_attrs(bus, dev);
+ out_put:
+@@ -575,6 +580,7 @@
+ sysfs_remove_link(&dev->bus->p->devices_kset->kobj,
+ dev_name(dev));
+ device_remove_attrs(dev->bus, dev);
++ device_remove_groups(dev, dev->bus->dev_groups);
+ if (klist_node_attached(&dev->p->knode_bus))
+ klist_del(&dev->p->knode_bus);
+
+diff -Nur linux-3.10.30.orig/drivers/base/component.c linux-linaro-stable-mx6/drivers/base/component.c
+--- linux-3.10.30.orig/drivers/base/component.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/base/component.c 2014-05-15 20:33:45.277922181 +0200
+@@ -0,0 +1,382 @@
++/*
++ * Componentized device handling.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This is work in progress. We gather up the component devices into a list,
++ * and bind them when instructed. At the moment, we're specific to the DRM
++ * subsystem, and only handles one master device, but this doesn't have to be
++ * the case.
++ */
++#include <linux/component.h>
++#include <linux/device.h>
++#include <linux/kref.h>
++#include <linux/list.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/slab.h>
++
++struct master {
++ struct list_head node;
++ struct list_head components;
++ bool bound;
++
++ const struct component_master_ops *ops;
++ struct device *dev;
++};
++
++struct component {
++ struct list_head node;
++ struct list_head master_node;
++ struct master *master;
++ bool bound;
++
++ const struct component_ops *ops;
++ struct device *dev;
++};
++
++static DEFINE_MUTEX(component_mutex);
++static LIST_HEAD(component_list);
++static LIST_HEAD(masters);
++
++static struct master *__master_find(struct device *dev,
++ const struct component_master_ops *ops)
++{
++ struct master *m;
++
++ list_for_each_entry(m, &masters, node)
++ if (m->dev == dev && (!ops || m->ops == ops))
++ return m;
++
++ return NULL;
++}
++
++/* Attach an unattached component to a master. */
++static void component_attach_master(struct master *master, struct component *c)
++{
++ c->master = master;
++
++ list_add_tail(&c->master_node, &master->components);
++}
++
++/* Detach a component from a master. */
++static void component_detach_master(struct master *master, struct component *c)
++{
++ list_del(&c->master_node);
++
++ c->master = NULL;
++}
++
++int component_master_add_child(struct master *master,
++ int (*compare)(struct device *, void *), void *compare_data)
++{
++ struct component *c;
++ int ret = -ENXIO;
++
++ list_for_each_entry(c, &component_list, node) {
++ if (c->master)
++ continue;
++
++ if (compare(c->dev, compare_data)) {
++ component_attach_master(master, c);
++ ret = 0;
++ break;
++ }
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(component_master_add_child);
++
++/* Detach all attached components from this master */
++static void master_remove_components(struct master *master)
++{
++ while (!list_empty(&master->components)) {
++ struct component *c = list_first_entry(&master->components,
++ struct component, master_node);
++
++ WARN_ON(c->master != master);
++
++ component_detach_master(master, c);
++ }
++}
++
++/*
++ * Try to bring up a master. If component is NULL, we're interested in
++ * this master, otherwise it's a component which must be present to try
++ * and bring up the master.
++ *
++ * Returns 1 for successful bringup, 0 if not ready, or -ve errno.
++ */
++static int try_to_bring_up_master(struct master *master,
++ struct component *component)
++{
++ int ret = 0;
++
++ if (!master->bound) {
++ /*
++ * Search the list of components, looking for components that
++ * belong to this master, and attach them to the master.
++ */
++ if (master->ops->add_components(master->dev, master)) {
++ /* Failed to find all components */
++ master_remove_components(master);
++ ret = 0;
++ goto out;
++ }
++
++ if (component && component->master != master) {
++ master_remove_components(master);
++ ret = 0;
++ goto out;
++ }
++
++ /* Found all components */
++ ret = master->ops->bind(master->dev);
++ if (ret < 0) {
++ master_remove_components(master);
++ goto out;
++ }
++
++ master->bound = true;
++ ret = 1;
++ }
++out:
++
++ return ret;
++}
++
++static int try_to_bring_up_masters(struct component *component)
++{
++ struct master *m;
++ int ret = 0;
++
++ list_for_each_entry(m, &masters, node) {
++ ret = try_to_bring_up_master(m, component);
++ if (ret != 0)
++ break;
++ }
++
++ return ret;
++}
++
++static void take_down_master(struct master *master)
++{
++ if (master->bound) {
++ master->ops->unbind(master->dev);
++ master->bound = false;
++ }
++
++ master_remove_components(master);
++}
++
++int component_master_add(struct device *dev,
++ const struct component_master_ops *ops)
++{
++ struct master *master;
++ int ret;
++
++ master = kzalloc(sizeof(*master), GFP_KERNEL);
++ if (!master)
++ return -ENOMEM;
++
++ master->dev = dev;
++ master->ops = ops;
++ INIT_LIST_HEAD(&master->components);
++
++ /* Add to the list of available masters. */
++ mutex_lock(&component_mutex);
++ list_add(&master->node, &masters);
++
++ ret = try_to_bring_up_master(master, NULL);
++
++ if (ret < 0) {
++ /* Delete off the list if we weren't successful */
++ list_del(&master->node);
++ kfree(master);
++ }
++ mutex_unlock(&component_mutex);
++
++ return ret < 0 ? ret : 0;
++}
++EXPORT_SYMBOL_GPL(component_master_add);
++
++void component_master_del(struct device *dev,
++ const struct component_master_ops *ops)
++{
++ struct master *master;
++
++ mutex_lock(&component_mutex);
++ master = __master_find(dev, ops);
++ if (master) {
++ take_down_master(master);
++
++ list_del(&master->node);
++ kfree(master);
++ }
++ mutex_unlock(&component_mutex);
++}
++EXPORT_SYMBOL_GPL(component_master_del);
++
++static void component_unbind(struct component *component,
++ struct master *master, void *data)
++{
++ WARN_ON(!component->bound);
++
++ component->ops->unbind(component->dev, master->dev, data);
++ component->bound = false;
++
++ /* Release all resources claimed in the binding of this component */
++ devres_release_group(component->dev, component);
++}
++
++void component_unbind_all(struct device *master_dev, void *data)
++{
++ struct master *master;
++ struct component *c;
++
++ WARN_ON(!mutex_is_locked(&component_mutex));
++
++ master = __master_find(master_dev, NULL);
++ if (!master)
++ return;
++
++ list_for_each_entry_reverse(c, &master->components, master_node)
++ component_unbind(c, master, data);
++}
++EXPORT_SYMBOL_GPL(component_unbind_all);
++
++static int component_bind(struct component *component, struct master *master,
++ void *data)
++{
++ int ret;
++
++ /*
++ * Each component initialises inside its own devres group.
++ * This allows us to roll-back a failed component without
++ * affecting anything else.
++ */
++ if (!devres_open_group(master->dev, NULL, GFP_KERNEL))
++ return -ENOMEM;
++
++ /*
++ * Also open a group for the device itself: this allows us
++ * to release the resources claimed against the sub-device
++ * at the appropriate moment.
++ */
++ if (!devres_open_group(component->dev, component, GFP_KERNEL)) {
++ devres_release_group(master->dev, NULL);
++ return -ENOMEM;
++ }
++
++ dev_dbg(master->dev, "binding %s (ops %ps)\n",
++ dev_name(component->dev), component->ops);
++
++ ret = component->ops->bind(component->dev, master->dev, data);
++ if (!ret) {
++ component->bound = true;
++
++ /*
++ * Close the component device's group so that resources
++ * allocated in the binding are encapsulated for removal
++ * at unbind. Remove the group on the DRM device as we
++ * can clean those resources up independently.
++ */
++ devres_close_group(component->dev, NULL);
++ devres_remove_group(master->dev, NULL);
++
++ dev_info(master->dev, "bound %s (ops %ps)\n",
++ dev_name(component->dev), component->ops);
++ } else {
++ devres_release_group(component->dev, NULL);
++ devres_release_group(master->dev, NULL);
++
++ dev_err(master->dev, "failed to bind %s (ops %ps): %d\n",
++ dev_name(component->dev), component->ops, ret);
++ }
++
++ return ret;
++}
++
++int component_bind_all(struct device *master_dev, void *data)
++{
++ struct master *master;
++ struct component *c;
++ int ret = 0;
++
++ WARN_ON(!mutex_is_locked(&component_mutex));
++
++ master = __master_find(master_dev, NULL);
++ if (!master)
++ return -EINVAL;
++
++ list_for_each_entry(c, &master->components, master_node) {
++ ret = component_bind(c, master, data);
++ if (ret)
++ break;
++ }
++
++ if (ret != 0) {
++ list_for_each_entry_continue_reverse(c, &master->components,
++ master_node)
++ component_unbind(c, master, data);
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(component_bind_all);
++
++int component_add(struct device *dev, const struct component_ops *ops)
++{
++ struct component *component;
++ int ret;
++
++ component = kzalloc(sizeof(*component), GFP_KERNEL);
++ if (!component)
++ return -ENOMEM;
++
++ component->ops = ops;
++ component->dev = dev;
++
++ dev_dbg(dev, "adding component (ops %ps)\n", ops);
++
++ mutex_lock(&component_mutex);
++ list_add_tail(&component->node, &component_list);
++
++ ret = try_to_bring_up_masters(component);
++ if (ret < 0) {
++ list_del(&component->node);
++
++ kfree(component);
++ }
++ mutex_unlock(&component_mutex);
++
++ return ret < 0 ? ret : 0;
++}
++EXPORT_SYMBOL_GPL(component_add);
++
++void component_del(struct device *dev, const struct component_ops *ops)
++{
++ struct component *c, *component = NULL;
++
++ mutex_lock(&component_mutex);
++ list_for_each_entry(c, &component_list, node)
++ if (c->dev == dev && c->ops == ops) {
++ list_del(&c->node);
++ component = c;
++ break;
++ }
++
++ if (component && component->master)
++ take_down_master(component->master);
++
++ mutex_unlock(&component_mutex);
++
++ WARN_ON(!component);
++ kfree(component);
++}
++EXPORT_SYMBOL_GPL(component_del);
++
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/base/core.c linux-linaro-stable-mx6/drivers/base/core.c
+--- linux-3.10.30.orig/drivers/base/core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/base/core.c 2014-05-15 20:33:45.289922268 +0200
+@@ -461,8 +461,7 @@
+ device_remove_bin_file(dev, &attrs[i]);
+ }
+
+-static int device_add_groups(struct device *dev,
+- const struct attribute_group **groups)
++int device_add_groups(struct device *dev, const struct attribute_group **groups)
+ {
+ int error = 0;
+ int i;
+@@ -481,8 +480,8 @@
+ return error;
+ }
+
+-static void device_remove_groups(struct device *dev,
+- const struct attribute_group **groups)
++void device_remove_groups(struct device *dev,
++ const struct attribute_group **groups)
+ {
+ int i;
+
+diff -Nur linux-3.10.30.orig/drivers/base/Makefile linux-linaro-stable-mx6/drivers/base/Makefile
+--- linux-3.10.30.orig/drivers/base/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/base/Makefile 2014-05-15 20:33:45.257922037 +0200
+@@ -1,6 +1,6 @@
+ # Makefile for the Linux device tree
+
+-obj-y := core.o bus.o dd.o syscore.o \
++obj-y := component.o core.o bus.o dd.o syscore.o \
+ driver.o class.o platform.o \
+ cpu.o firmware.o init.o map.o devres.o \
+ attribute_container.o transport_class.o \
+diff -Nur linux-3.10.30.orig/drivers/base/pinctrl.c linux-linaro-stable-mx6/drivers/base/pinctrl.c
+--- linux-3.10.30.orig/drivers/base/pinctrl.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/base/pinctrl.c 2014-05-15 20:33:45.293922296 +0200
+@@ -48,6 +48,25 @@
+ goto cleanup_get;
+ }
+
++#ifdef CONFIG_PM
++ /*
++ * If power management is enabled, we also look for the optional
++ * sleep and idle pin states, with semantics as defined in
++ * <linux/pinctrl/pinctrl-state.h>
++ */
++ dev->pins->sleep_state = pinctrl_lookup_state(dev->pins->p,
++ PINCTRL_STATE_SLEEP);
++ if (IS_ERR(dev->pins->sleep_state))
++ /* Not supplying this state is perfectly legal */
++ dev_dbg(dev, "no sleep pinctrl state\n");
++
++ dev->pins->idle_state = pinctrl_lookup_state(dev->pins->p,
++ PINCTRL_STATE_IDLE);
++ if (IS_ERR(dev->pins->idle_state))
++ /* Not supplying this state is perfectly legal */
++ dev_dbg(dev, "no idle pinctrl state\n");
++#endif
++
+ return 0;
+
+ /*
+diff -Nur linux-3.10.30.orig/drivers/base/regmap/internal.h linux-linaro-stable-mx6/drivers/base/regmap/internal.h
+--- linux-3.10.30.orig/drivers/base/regmap/internal.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/base/regmap/internal.h 2014-05-15 20:33:45.297922326 +0200
+@@ -52,6 +52,7 @@
+ struct regmap {
+ struct mutex mutex;
+ spinlock_t spinlock;
++ unsigned long spinlock_flags;
+ regmap_lock lock;
+ regmap_unlock unlock;
+ void *lock_arg; /* This is passed to lock/unlock functions */
+diff -Nur linux-3.10.30.orig/drivers/base/regmap/regmap.c linux-linaro-stable-mx6/drivers/base/regmap/regmap.c
+--- linux-3.10.30.orig/drivers/base/regmap/regmap.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/base/regmap/regmap.c 2014-05-15 20:33:45.297922326 +0200
+@@ -302,13 +302,16 @@
+ static void regmap_lock_spinlock(void *__map)
+ {
+ struct regmap *map = __map;
+- spin_lock(&map->spinlock);
++ unsigned long flags;
++
++ spin_lock_irqsave(&map->spinlock, flags);
++ map->spinlock_flags = flags;
+ }
+
+ static void regmap_unlock_spinlock(void *__map)
+ {
+ struct regmap *map = __map;
+- spin_unlock(&map->spinlock);
++ spin_unlock_irqrestore(&map->spinlock, map->spinlock_flags);
+ }
+
+ static void dev_get_regmap_release(struct device *dev, void *res)
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_conf.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_conf.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_conf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_conf.c 2014-05-15 20:33:45.317922470 +0200
+@@ -0,0 +1,2630 @@
++/*
++ * eio_conf.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ * Amit Kale <akale@stec-inc.com>
++ * Restructured much of the io code to split bio within map function instead
++ * of letting dm do it.
++ * Simplified queued logic for write through.
++ * Amit Kale <akale@stec-inc.com>
++ * Harish Pujari <hpujari@stec-inc.com>
++ * Designed and implemented the writeback caching mode
++ *
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include "eio.h"
++#include "eio_ttc.h"
++
++#define KMEM_CACHE_JOB "eio-kcached-jobs"
++#define KMEM_EIO_IO "eio-io-context"
++#define KMEM_DMC_BIO_PAIR "eio-dmc-bio-pair"
++/* #define KMEM_CACHE_PENDING_JOB "eio-pending-jobs" */
++
++static struct cache_c *cache_list_head;
++struct work_struct _kcached_wq;
++
++static struct kmem_cache *_job_cache;
++struct kmem_cache *_io_cache; /* cache of eio_context objects */
++mempool_t *_job_pool;
++mempool_t *_io_pool; /* pool of eio_context object */
++
++atomic_t nr_cache_jobs;
++
++
++LIST_HEAD(ssd_rm_list);
++int ssd_rm_list_not_empty;
++spinlock_t ssd_rm_list_lock;
++
++struct eio_control_s *eio_control;
++
++int eio_force_warm_boot;
++static int eio_notify_reboot(struct notifier_block *nb, unsigned long action,
++ void *x);
++void eio_stop_async_tasks(struct cache_c *dmc);
++static int eio_notify_ssd_rm(struct notifier_block *nb, unsigned long action,
++ void *x);
++
++/*
++ * The notifiers are registered in descending order of priority and
++ * executed in descending order or priority. We should be run before
++ * any notifiers of ssd's or other block devices. Typically, devices
++ * use a priority of 0.
++ * XXX - If in the future we happen to use a md device as the cache
++ * block device, we have a problem because md uses a priority of
++ * INT_MAX as well. But we want to run before the md's reboot notifier !
++ */
++static struct notifier_block eio_reboot_notifier = {
++ .notifier_call = eio_notify_reboot,
++ .next = NULL,
++ .priority = INT_MAX, /* should be > ssd pri's and disk dev pri's */
++};
++
++static struct notifier_block eio_ssd_rm_notifier = {
++ .notifier_call = eio_notify_ssd_rm,
++ .next = NULL,
++ .priority = 0,
++};
++
++int eio_wait_schedule(void *unused)
++{
++
++ schedule();
++ return 0;
++}
++
++/*
++ * Check if the System RAM threshold > requested memory, don't care
++ * if threshold is set to 0. Return value is 0 for fail and 1 for success.
++ */
++static inline int eio_mem_available(struct cache_c *dmc, size_t size)
++{
++ struct sysinfo si;
++
++ if (unlikely
++ (dmc->sysctl_active.mem_limit_pct <= 0
++ || dmc->sysctl_active.mem_limit_pct >= 100))
++ return 1;
++
++ si_meminfo(&si);
++ return (((si.freeram << PAGE_SHIFT) *
++ dmc->sysctl_active.mem_limit_pct) / 100) > size;
++}
++
++/* create a new thread and call the specified function */
++void *eio_create_thread(int (*func)(void *), void *context, char *name)
++{
++ return kthread_run(func, context, "%s", name);
++}
++
++/* wait for the given thread to exit */
++void eio_wait_thread_exit(void *thrdptr, int *running)
++{
++ while (*running)
++ msleep(1);
++
++ /*do_exit() would be called within the thread func itself*/
++
++ return;
++}
++
++/* thread exit self */
++void eio_thread_exit(long exit_code)
++{
++ do_exit(exit_code);
++}
++const char *eio_policy_to_name(u8 p)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(eio_policy_names); i++)
++ if (eio_policy_names[i].p == p)
++ return eio_policy_names[i].n;
++
++ return NULL;
++}
++
++
++inline int eio_policy_init(struct cache_c *dmc)
++{
++
++ if (dmc->req_policy == 0)
++ dmc->req_policy = CACHE_REPL_DEFAULT;
++ dmc->policy_ops = eio_get_policy(dmc->req_policy);
++ if (dmc->policy_ops == NULL) {
++ pr_err("eio_policy_init: Failed to initialize %s(%d) policy",
++ eio_policy_to_name(dmc->req_policy), dmc->req_policy);
++ return -EINVAL;
++ } else {
++ /* Back pointer to reference dmc from policy_ops */
++ dmc->policy_ops->sp_dmc = dmc;
++ pr_info("Setting replacement policy to %s (%d)",
++ eio_policy_to_name(dmc->policy_ops->sp_name),
++ dmc->policy_ops->sp_name);
++ return 0;
++ }
++}
++
++static int eio_jobs_init(void)
++{
++
++ _job_cache = _io_cache = NULL;
++ _job_pool = _io_pool = NULL;
++
++ _job_cache = kmem_cache_create(KMEM_CACHE_JOB,
++ sizeof(struct kcached_job),
++ __alignof__(struct kcached_job),
++ 0, NULL);
++ if (!_job_cache)
++ return -ENOMEM;
++
++ _job_pool = mempool_create(MIN_JOBS, mempool_alloc_slab,
++ mempool_free_slab, _job_cache);
++ if (!_job_pool)
++ goto out;
++
++ _io_cache = kmem_cache_create(KMEM_EIO_IO,
++ sizeof(struct eio_context),
++ __alignof__(struct eio_context), 0, NULL);
++ if (!_io_cache)
++ goto out;
++
++ _io_pool = mempool_create(MIN_EIO_IO, mempool_alloc_slab,
++ mempool_free_slab, _io_cache);
++ if (!_io_pool)
++ goto out;
++
++ return 0;
++
++out:
++ if (_io_pool)
++ mempool_destroy(_io_pool);
++ if (_io_cache)
++ kmem_cache_destroy(_io_cache);
++ if (_job_pool)
++ mempool_destroy(_job_pool);
++ if (_job_cache)
++ kmem_cache_destroy(_job_cache);
++
++ _job_pool = _io_pool = NULL;
++ _job_cache = _io_cache = NULL;
++ return -ENOMEM;
++}
++
++static void eio_jobs_exit(void)
++{
++
++ mempool_destroy(_io_pool);
++ mempool_destroy(_job_pool);
++ kmem_cache_destroy(_io_cache);
++ kmem_cache_destroy(_job_cache);
++
++ _job_pool = _io_pool = NULL;
++ _job_cache = _io_cache = NULL;
++}
++
++static int eio_kcached_init(struct cache_c *dmc)
++{
++
++ /* init_waitqueue_head(&dmc->destroyq); */
++ atomic_set(&dmc->nr_jobs, 0);
++ return 0;
++}
++
++static void eio_kcached_client_destroy(struct cache_c *dmc)
++{
++
++ /* Wait for all IOs
++ /wait_event(dmc->destroyq, !atomic_read(&dmc->nr_jobs));*/
++}
++
++/* Store the cache superblock on ssd */
++int eio_sb_store(struct cache_c *dmc)
++{
++ union eio_superblock *sb = NULL;
++ struct eio_io_region where;
++ int error;
++
++ struct bio_vec *sb_pages;
++ int nr_pages;
++ int page_count, page_index;
++
++ if ((unlikely(CACHE_FAILED_IS_SET(dmc)) || CACHE_DEGRADED_IS_SET(dmc))
++ && (!CACHE_SSD_ADD_INPROG_IS_SET(dmc))) {
++ pr_err
++ ("sb_store: Cannot write superblock for cache \"%s\", in degraded/failed mode.\n",
++ dmc->cache_name);
++ return -ENODEV;
++ }
++
++ page_count = 0;
++ nr_pages = EIO_SUPERBLOCK_SIZE / PAGE_SIZE;
++ EIO_ASSERT(nr_pages != 0);
++
++ sb_pages = eio_alloc_pages(nr_pages, &page_count);
++ if (sb_pages == NULL) {
++ pr_err("sb_store: System memory too low.\n");
++ return -ENOMEM;
++ }
++
++ EIO_ASSERT(page_count == nr_pages);
++
++ nr_pages = page_count;
++ page_index = 0;
++ sb = (union eio_superblock *)kmap(sb_pages[page_index].bv_page);
++
++ sb->sbf.cache_sb_state = cpu_to_le32(dmc->sb_state);
++ sb->sbf.block_size = cpu_to_le32(dmc->block_size);
++ sb->sbf.size = cpu_to_le32(dmc->size);
++ sb->sbf.assoc = cpu_to_le32(dmc->assoc);
++ sb->sbf.cache_md_start_sect = cpu_to_le64(dmc->md_start_sect);
++ sb->sbf.cache_data_start_sect = cpu_to_le64(dmc->md_sectors);
++ strncpy(sb->sbf.disk_devname, dmc->disk_devname, DEV_PATHLEN);
++ strncpy(sb->sbf.cache_devname, dmc->cache_devname, DEV_PATHLEN);
++ strncpy(sb->sbf.ssd_uuid, dmc->ssd_uuid, DEV_PATHLEN - 1);
++ sb->sbf.cache_devsize = cpu_to_le64(eio_to_sector(eio_get_device_size(dmc->cache_dev)));
++ sb->sbf.disk_devsize = cpu_to_le64(eio_to_sector(eio_get_device_size(dmc->disk_dev)));
++ sb->sbf.cache_version = cpu_to_le32(dmc->sb_version);
++ strncpy(sb->sbf.cache_name, dmc->cache_name, DEV_PATHLEN);
++ sb->sbf.cache_name[DEV_PATHLEN - 1] = '\0';
++ sb->sbf.mode = cpu_to_le32(dmc->mode);
++ spin_lock_irqsave(&dmc->cache_spin_lock, dmc->cache_spin_lock_flags);
++ sb->sbf.repl_policy = cpu_to_le32(dmc->req_policy);
++ sb->sbf.cache_flags = cpu_to_le32(dmc->cache_flags & ~CACHE_FLAGS_INCORE_ONLY);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ if (dmc->sb_version)
++ sb->sbf.magic = cpu_to_le32(EIO_MAGIC);
++ else
++ sb->sbf.magic = cpu_to_le32(EIO_BAD_MAGIC);
++
++ sb->sbf.cold_boot = cpu_to_le32(dmc->cold_boot);
++ if (le32_to_cpu(sb->sbf.cold_boot) && eio_force_warm_boot)
++ sb->sbf.cold_boot = cpu_to_le32(le32_to_cpu(sb->sbf.cold_boot) |
++ BOOT_FLAG_FORCE_WARM);
++
++ sb->sbf.dirty_high_threshold = cpu_to_le32(dmc->sysctl_active.dirty_high_threshold);
++ sb->sbf.dirty_low_threshold = cpu_to_le32(dmc->sysctl_active.dirty_low_threshold);
++ sb->sbf.dirty_set_high_threshold =
++ cpu_to_le32(dmc->sysctl_active.dirty_set_high_threshold);
++ sb->sbf.dirty_set_low_threshold =
++ cpu_to_le32(dmc->sysctl_active.dirty_set_low_threshold);
++ sb->sbf.time_based_clean_interval =
++ cpu_to_le32(dmc->sysctl_active.time_based_clean_interval);
++ sb->sbf.autoclean_threshold = cpu_to_le32(dmc->sysctl_active.autoclean_threshold);
++
++ /* write out to ssd */
++ where.bdev = dmc->cache_dev->bdev;
++ where.sector = EIO_SUPERBLOCK_START;
++ where.count = eio_to_sector(EIO_SUPERBLOCK_SIZE);
++ error = eio_io_sync_vm(dmc, &where, WRITE, sb_pages, nr_pages);
++ if (error) {
++ pr_err
++ ("sb_store: Could not write out superblock to sector %llu (error %d) for cache \"%s\".\n",
++ (unsigned long long)where.sector, error, dmc->cache_name);
++ }
++
++ /* free the allocated pages here */
++ if (sb_pages) {
++ kunmap(sb_pages[0].bv_page);
++ for (page_index = 0; page_index < nr_pages; page_index++)
++ put_page(sb_pages[page_index].bv_page);
++ kfree(sb_pages);
++ sb_pages = NULL;
++ }
++
++ return error;
++}
++
++/*
++ * Write out the metadata one sector at a time.
++ * Then dump out the superblock.
++ */
++int eio_md_store(struct cache_c *dmc)
++{
++ struct flash_cacheblock *next_ptr;
++ struct eio_io_region where;
++ sector_t i;
++ int j, k;
++ int num_valid = 0, num_dirty = 0;
++ int error;
++ int write_errors = 0;
++ sector_t sectors_written = 0, sectors_expected = 0; /* debug */
++ int slots_written = 0; /* How many cache slots did we fill in this MD io block ? */
++
++ struct bio_vec *pages;
++ int nr_pages;
++ int page_count, page_index;
++ void **pg_virt_addr;
++
++ if (unlikely(CACHE_FAILED_IS_SET(dmc))
++ || unlikely(CACHE_DEGRADED_IS_SET(dmc))) {
++ pr_err
++ ("md_store: Cannot write metadata in failed/degraded mode for cache \"%s\".",
++ dmc->cache_name);
++ return -ENODEV;
++ }
++
++ if (CACHE_FAST_REMOVE_IS_SET(dmc)) {
++ if (CACHE_VERBOSE_IS_SET(dmc))
++ pr_info("Skipping writing out metadata to cache");
++ if (!dmc->sb_version) {
++
++ /*
++ * Incase of delete, flush the superblock
++ * irrespective of fast_remove being set.
++ */
++
++ goto sb_store;
++ }
++ return 0;
++ }
++
++ if (!eio_mem_available(dmc, METADATA_IO_BLOCKSIZE_SECT)) {
++ pr_err
++ ("md_store: System memory too low for allocating metadata IO buffers");
++ return -ENOMEM;
++ }
++
++ page_count = 0;
++ pages = eio_alloc_pages(dmc->bio_nr_pages, &page_count);
++ if (pages == NULL) {
++ pr_err("eio_md_store: System memory too low.");
++ return -ENOMEM;
++ }
++
++ /* get the exact number of pages allocated */
++ nr_pages = page_count;
++ where.bdev = dmc->cache_dev->bdev;
++ where.sector = dmc->md_start_sect;
++ slots_written = 0;
++ page_index = 0;
++
++ pg_virt_addr = kmalloc(nr_pages * (sizeof(void *)), GFP_KERNEL);
++ if (pg_virt_addr == NULL) {
++ pr_err("eio_md_store: System memory too low.");
++ for (k = 0; k < nr_pages; k++)
++ put_page(pages[k].bv_page);
++ kfree(pages);
++ return -ENOMEM;
++ }
++
++ for (k = 0; k < nr_pages; k++)
++ pg_virt_addr[k] = kmap(pages[k].bv_page);
++
++ next_ptr = (struct flash_cacheblock *)pg_virt_addr[page_index];
++ j = MD_BLOCKS_PER_PAGE;
++
++ pr_info("Writing out metadata to cache device. Please wait...");
++
++ for (i = 0; i < dmc->size; i++) {
++ if (EIO_CACHE_STATE_GET(dmc, (index_t)i) & VALID)
++ num_valid++;
++ if (EIO_CACHE_STATE_GET(dmc, (index_t)i) & DIRTY)
++ num_dirty++;
++ next_ptr->dbn = cpu_to_le64(EIO_DBN_GET(dmc, i));
++ next_ptr->cache_state = cpu_to_le64(EIO_CACHE_STATE_GET(dmc, (index_t)i) &
++ (INVALID | VALID | DIRTY));
++
++ next_ptr++;
++ slots_written++;
++ j--;
++ if (j == 0) {
++ /*
++ * Filled the page, goto the next page.
++ */
++ page_index++;
++
++ if (slots_written ==
++ (int)(MD_BLOCKS_PER_PAGE * nr_pages)) {
++ /*
++ * Wrote out an entire metadata IO block, write the block to the ssd.
++ */
++ where.count =
++ slots_written / MD_BLOCKS_PER_SECTOR;
++ slots_written = 0;
++ page_index = 0;
++ sectors_written += where.count; /* debug */
++
++ error =
++ eio_io_sync_vm(dmc, &where, WRITE, pages,
++ nr_pages);
++
++ if (error) {
++ write_errors++;
++ pr_err
++ ("md_store: Could not write out metadata to sector %llu (error %d)",
++ (unsigned long long)where.sector, error);
++ }
++ where.sector += where.count; /* Advance offset */
++ }
++ /* Move next slot pointer into next sector */
++ next_ptr =
++ (struct flash_cacheblock *)pg_virt_addr[page_index];
++ j = MD_BLOCKS_PER_PAGE;
++ }
++ }
++
++ if (next_ptr != (struct flash_cacheblock *)pg_virt_addr[0]) {
++ /* Write the remaining last page out */
++ EIO_ASSERT(slots_written > 0);
++
++ where.count = slots_written / MD_BLOCKS_PER_SECTOR;
++
++ if (slots_written % MD_BLOCKS_PER_SECTOR)
++ where.count++;
++
++ sectors_written += where.count;
++
++ /*
++ * This may happen that we are at the beginning of the next page
++ * and did not fill up any slots in this page. Verify this condition
++ * and set page_index accordingly.
++ */
++
++ if (next_ptr !=
++ (struct flash_cacheblock *)pg_virt_addr[page_index]) {
++ unsigned offset;
++
++ slots_written = slots_written % MD_BLOCKS_PER_PAGE;
++
++ /*
++ * We have some extra slots written at this page_index.
++ * Let us try to zero out the remaining page size before submitting
++ * this page.
++ */
++ offset =
++ slots_written * (sizeof(struct flash_cacheblock));
++ memset(pg_virt_addr[page_index] + offset, 0,
++ PAGE_SIZE - offset);
++
++ page_index++;
++ }
++
++ error = eio_io_sync_vm(dmc, &where, WRITE, pages, page_index);
++ /* XXX: should we call eio_sb_store() on error ?? */
++ if (error) {
++ write_errors++;
++ pr_err
++ ("md_store: Could not write out metadata to sector %llu (error %d)",
++ (unsigned long long)where.sector, error);
++ }
++ }
++
++ /* Debug Tests */
++ sectors_expected = EIO_DIV(dmc->size, MD_BLOCKS_PER_SECTOR);
++ if (EIO_REM(dmc->size, MD_BLOCKS_PER_SECTOR))
++ sectors_expected++;
++ EIO_ASSERT(sectors_expected == sectors_written);
++ /* XXX: should we call eio_sb_store() on error ?? */
++ if (sectors_expected != sectors_written) {
++ pr_err
++ ("md_store: Sector mismatch! sectors_expected=%llu, sectors_written=%llu\n",
++ (unsigned long long)sectors_expected, (unsigned long long)sectors_written);
++ }
++
++ for (k = 0; k < nr_pages; k++)
++ kunmap(pages[k].bv_page);
++ kfree(pg_virt_addr);
++
++ if (pages)
++ for (k = 0; k < nr_pages; k++)
++ put_page(pages[k].bv_page);
++ kfree(pages);
++ pages = NULL;
++
++ if (write_errors == 0) {
++ if (num_dirty == 0)
++ dmc->sb_state = CACHE_MD_STATE_CLEAN;
++ else
++ dmc->sb_state = CACHE_MD_STATE_FASTCLEAN;
++ } else
++ dmc->sb_state = CACHE_MD_STATE_UNSTABLE;
++
++sb_store:
++ error = eio_sb_store(dmc);
++ if (error) {
++ /* TBD. should we return error */
++ write_errors++;
++ pr_err("md_store: superblock store failed(error %d)", error);
++ }
++ if (!dmc->sb_version && CACHE_FAST_REMOVE_IS_SET(dmc))
++ return 0;
++
++ if (write_errors == 0)
++ pr_info("Metadata saved on the cache device");
++ else {
++ pr_info
++ ("CRITICAL: There were %d errors in saving metadata on cache device",
++ write_errors);
++ if (num_dirty)
++ pr_info
++ ("CRITICAL: %d dirty blocks could not be written out",
++ num_dirty);
++ }
++
++ pr_info("Valid blocks: %d, Dirty blocks: %d, Metadata sectors: %llu",
++ num_valid, num_dirty, (long long unsigned int)dmc->md_sectors);
++
++ return 0;
++}
++
++static int eio_md_create(struct cache_c *dmc, int force, int cold)
++{
++ struct flash_cacheblock *next_ptr;
++ union eio_superblock *header;
++ struct eio_io_region where;
++ sector_t i;
++ int j, error;
++ uint64_t cache_size, dev_size;
++ sector_t order;
++ sector_t sectors_written = 0, sectors_expected = 0; /* debug */
++ int slots_written = 0; /* How many cache slots did we fill in this MD io block ? */
++
++ struct bio_vec *header_page = NULL; /* Header page */
++ struct bio_vec *pages = NULL; /* Metadata pages */
++ int nr_pages = 0;
++ int page_count, page_index;
++ int ret = 0, k;
++ void **pg_virt_addr = NULL;
++
++ /* Allocate single page for superblock header.*/
++ page_count = 0;
++ header_page = eio_alloc_pages(1, &page_count);
++ if (header_page == NULL) {
++ pr_err("eio_md_create: System memory too low.");
++ return -ENOMEM;
++ }
++
++ EIO_ASSERT(page_count = 1);
++ header = (union eio_superblock *)kmap(header_page[0].bv_page);
++
++ /*
++ * Apart from normal cache creation, eio_md_create() is also called when
++ * the SSD is added as part of eio_resume_caching(). At this point,
++ * the CACHE_FLAGS_DEGRADED is set, but we do want to write to the md area.
++ * Therefore, if the CACHE_FLAGS_SSD_ADD_INPROG is set, then proceed instead
++ * of returning -ENODEV.
++ */
++ if ((unlikely(CACHE_FAILED_IS_SET(dmc))
++ || unlikely(CACHE_DEGRADED_IS_SET(dmc)))
++ && (!CACHE_SSD_ADD_INPROG_IS_SET(dmc))) {
++ pr_err
++ ("md_create: Cannot write metadata in failed/degraded mode for cache \"%s\".\n",
++ dmc->cache_name);
++ ret = -ENODEV;
++ goto free_header;
++ }
++
++ where.bdev = dmc->cache_dev->bdev;
++ where.sector = EIO_SUPERBLOCK_START;
++ where.count = eio_to_sector(EIO_SUPERBLOCK_SIZE);
++ error = eio_io_sync_vm(dmc, &where, READ, header_page, 1);
++ if (error) {
++ pr_err
++ ("md_create: Could not read superblock sector %llu error %d for cache \"%s\".\n",
++ (unsigned long long)where.sector, error, dmc->cache_name);
++ ret = -EINVAL;
++ goto free_header;
++ }
++
++ if (!force &&
++ ((le32_to_cpu(header->sbf.cache_sb_state) == CACHE_MD_STATE_DIRTY) ||
++ (le32_to_cpu(header->sbf.cache_sb_state) == CACHE_MD_STATE_CLEAN) ||
++ (le32_to_cpu(header->sbf.cache_sb_state) == CACHE_MD_STATE_FASTCLEAN))) {
++ pr_err
++ ("md_create: Existing cache detected, use force to re-create.\n");
++ ret = -EINVAL;
++ goto free_header;
++ }
++
++ /*
++ * Compute the size of the metadata including header.
++ * and here we also are making sure that metadata and userdata
++ * on SSD is aligned at 8K boundary.
++ *
++ * Note dmc->size is in raw sectors
++ */
++ dmc->md_start_sect = EIO_METADATA_START(dmc->cache_dev_start_sect);
++ dmc->md_sectors =
++ INDEX_TO_MD_SECTOR(EIO_DIV(dmc->size, (sector_t)dmc->block_size));
++ dmc->md_sectors +=
++ EIO_EXTRA_SECTORS(dmc->cache_dev_start_sect, dmc->md_sectors);
++ dmc->size -= dmc->md_sectors; /* total sectors available for cache */
++ do_div(dmc->size, dmc->block_size);
++ dmc->size = EIO_DIV(dmc->size, dmc->assoc) * (sector_t)dmc->assoc;
++ /* Recompute since dmc->size was possibly trunc'ed down */
++ dmc->md_sectors = INDEX_TO_MD_SECTOR(dmc->size);
++ dmc->md_sectors +=
++ EIO_EXTRA_SECTORS(dmc->cache_dev_start_sect, dmc->md_sectors);
++
++ error = eio_mem_init(dmc);
++ if (error == -1) {
++ ret = -EINVAL;
++ goto free_header;
++ }
++ if ((unlikely(CACHE_FAILED_IS_SET(dmc))
++ || unlikely(CACHE_DEGRADED_IS_SET(dmc)))
++ && (!CACHE_SSD_ADD_INPROG_IS_SET(dmc))) {
++ pr_err
++ ("md_create: Cannot write metadata in failed/degraded mode for cache \"%s\".\n",
++ dmc->cache_name);
++ ret = -ENODEV;
++ goto free_header;
++ }
++ dev_size = eio_to_sector(eio_get_device_size(dmc->cache_dev));
++ cache_size = dmc->md_sectors + (dmc->size * dmc->block_size);
++ if (cache_size > dev_size) {
++ pr_err
++ ("md_create: Requested cache size exceeds the cache device's capacity (%llu > %llu)",
++ (unsigned long long)cache_size, (unsigned long long)dev_size);
++ ret = -EINVAL;
++ goto free_header;
++ }
++
++ order =
++ dmc->size *
++ (EIO_MD8(dmc) ? sizeof(struct cacheblock_md8) :
++ sizeof(struct cacheblock));
++ i = EIO_MD8(dmc) ? sizeof(struct cacheblock_md8) : sizeof(struct
++ cacheblock);
++ pr_info("Allocate %lluKB (%lluB per) mem for %llu-entry cache " \
++ "(capacity:%lluMB, associativity:%u, block size:%u bytes)",
++ (unsigned long long)order >> 10, (unsigned long long)i,
++ (long long unsigned int)dmc->size,
++ (unsigned long long)(cache_size >> (20 - SECTOR_SHIFT)), dmc->assoc,
++ dmc->block_size << SECTOR_SHIFT);
++
++ if (!eio_mem_available(dmc, order) && !CACHE_SSD_ADD_INPROG_IS_SET(dmc)) {
++ pr_err
++ ("md_create: System memory too low for allocating cache metadata.\n");
++ ret = -ENOMEM;
++ goto free_header;
++ }
++
++ /*
++ * If we are called due to SSD add, the memory was already allocated
++ * as part of cache creation (i.e., eio_ctr()) in the past.
++ */
++ if (!CACHE_SSD_ADD_INPROG_IS_SET(dmc)) {
++ if (EIO_MD8(dmc))
++ dmc->cache_md8 = vmalloc((size_t)order);
++ else
++ dmc->cache = vmalloc((size_t)order);
++ if ((EIO_MD8(dmc) && !dmc->cache_md8)
++ || (!EIO_MD8(dmc) && !dmc->cache)) {
++ pr_err
++ ("md_create: Unable to allocate cache md for cache \"%s\".\n",
++ dmc->cache_name);
++ ret = -ENOMEM;
++ goto free_header;
++ }
++ }
++ if (eio_repl_blk_init(dmc->policy_ops) != 0) {
++ pr_err
++ ("md_create: Unable to allocate memory for policy cache block for cache \"%s\".\n",
++ dmc->cache_name);
++ ret = -ENOMEM;
++ goto free_header;
++ }
++
++ if (cold) {
++ int retry = 0;
++ do {
++ for (i = 0; i < dmc->size; i++) {
++ if (CACHE_SSD_ADD_INPROG_IS_SET(dmc)) {
++ u_int8_t cache_state =
++ EIO_CACHE_STATE_GET(dmc, i);
++ if (cache_state & BLOCK_IO_INPROG) {
++ /* sleep for 1 sec and retry */
++ msleep(1000);
++ break;
++ }
++ }
++ eio_invalidate_md(dmc, i);
++ }
++ } while ((retry++ < 10) && (i < dmc->size));
++
++ if (i < dmc->size) {
++ pr_err
++ ("md_create: Cache \"%s\" is not in quiesce state. Can't proceed to resume.\n",
++ dmc->cache_name);
++ ret = -EBUSY;
++ goto free_header;
++ }
++
++ /* Allocate pages of the order dmc->bio_nr_pages */
++ page_count = 0;
++ pages = eio_alloc_pages(dmc->bio_nr_pages, &page_count);
++ if (!pages) {
++ pr_err
++ ("md_create: Unable to allocate pages for cache \"%s\".\n",
++ dmc->cache_name);
++ pr_err
++ ("md_create: Could not write out cache metadata.\n");
++ ret = -ENOMEM;
++ goto free_header;
++ }
++
++ /* nr_pages is used for freeing the pages */
++ nr_pages = page_count;
++
++ where.bdev = dmc->cache_dev->bdev;
++ where.sector = dmc->md_start_sect;
++ slots_written = 0;
++ page_index = 0;
++
++ pg_virt_addr = kmalloc(nr_pages * (sizeof(void *)), GFP_KERNEL);
++ if (pg_virt_addr == NULL) {
++ pr_err("md_create: System memory too low.\n");
++ for (k = 0; k < nr_pages; k++)
++ put_page(pages[k].bv_page);
++ kfree(pages);
++ ret = -ENOMEM;
++ goto free_header;
++ }
++
++ for (k = 0; k < nr_pages; k++)
++ pg_virt_addr[k] = kmap(pages[k].bv_page);
++
++ next_ptr = (struct flash_cacheblock *)pg_virt_addr[page_index];
++ j = MD_BLOCKS_PER_PAGE;
++
++ for (i = 0; i < dmc->size; i++) {
++ next_ptr->dbn = cpu_to_le64(EIO_DBN_GET(dmc, i));
++ next_ptr->cache_state =
++ cpu_to_le64(EIO_CACHE_STATE_GET(dmc,
++ (index_t)i) & (INVALID | VALID | DIRTY));
++ next_ptr++;
++ slots_written++;
++ j--;
++
++ if (j == 0) {
++
++ page_index++;
++
++ if ((unsigned)slots_written ==
++ MD_BLOCKS_PER_PAGE * nr_pages) {
++
++ where.count =
++ slots_written /
++ MD_BLOCKS_PER_SECTOR;
++ slots_written = 0;
++ page_index = 0;
++ sectors_written += where.count; /* debug */
++ error =
++ eio_io_sync_vm(dmc, &where, WRITE,
++ pages, nr_pages);
++
++ if (error) {
++ if (!CACHE_SSD_ADD_INPROG_IS_SET
++ (dmc))
++ vfree(EIO_CACHE(dmc));
++ pr_err
++ ("md_create: Could not write cache metadata sector %llu error %d.\n for cache \"%s\".\n",
++ (unsigned long long)where.sector, error,
++ dmc->cache_name);
++ ret = -EIO;
++ goto free_md;
++ }
++ where.sector += where.count; /* Advance offset */
++ }
++
++ /* Move next slot pointer into next page */
++ next_ptr =
++ (struct flash_cacheblock *)
++ pg_virt_addr[page_index];
++ j = MD_BLOCKS_PER_PAGE;
++ }
++ }
++
++ if (next_ptr != (struct flash_cacheblock *)pg_virt_addr[0]) {
++ /* Write the remaining last page out */
++ EIO_ASSERT(slots_written > 0);
++
++ where.count = slots_written / MD_BLOCKS_PER_SECTOR;
++
++ if (slots_written % MD_BLOCKS_PER_SECTOR)
++ where.count++;
++
++ sectors_written += where.count;
++
++ if (next_ptr !=
++ (struct flash_cacheblock *)pg_virt_addr[page_index]) {
++ unsigned offset;
++
++ slots_written =
++ slots_written % MD_BLOCKS_PER_PAGE;
++
++ /*
++ * We have some extra slots written at this page_index.
++ * Let us try to zero out the remaining page size before submitting
++ * this page.
++ */
++ offset =
++ slots_written *
++ (sizeof(struct flash_cacheblock));
++ memset(pg_virt_addr[page_index] + offset, 0,
++ PAGE_SIZE - offset);
++
++ page_index = page_index + 1;
++ }
++
++ error =
++ eio_io_sync_vm(dmc, &where, WRITE, pages,
++ page_index);
++ if (error) {
++ if (!CACHE_SSD_ADD_INPROG_IS_SET(dmc))
++ vfree((void *)EIO_CACHE(dmc));
++ pr_err
++ ("md_create: Could not write cache metadata sector %llu error %d for cache \"%s\".\n",
++ (unsigned long long)where.sector, error, dmc->cache_name);
++ ret = -EIO;
++ goto free_md;
++ }
++ }
++
++ /* Debug Tests */
++ sectors_expected = EIO_DIV(dmc->size, MD_BLOCKS_PER_SECTOR);
++ if (EIO_REM(dmc->size, MD_BLOCKS_PER_SECTOR))
++ sectors_expected++;
++ if (sectors_expected != sectors_written) {
++ pr_err
++ ("md_create: Sector mismatch! sectors_expected=%llu, sectors_written=%llu for cache \"%s\".\n",
++ (unsigned long long)sectors_expected, (unsigned long long)sectors_written,
++ dmc->cache_name);
++ ret = -EIO;
++ goto free_md;
++ }
++ }
++
++ /* if cold ends here */
++ /* Write the superblock */
++ if ((unlikely(CACHE_FAILED_IS_SET(dmc))
++ || unlikely(CACHE_DEGRADED_IS_SET(dmc)))
++ && (!CACHE_SSD_ADD_INPROG_IS_SET(dmc))) {
++ pr_err
++ ("md_create: Cannot write metadata in failed/degraded mode for cache \"%s\".\n",
++ dmc->cache_name);
++ vfree((void *)EIO_CACHE(dmc));
++ ret = -ENODEV;
++ goto free_md;
++ }
++
++ dmc->sb_state = CACHE_MD_STATE_DIRTY;
++ dmc->sb_version = EIO_SB_VERSION;
++ error = eio_sb_store(dmc);
++ if (error) {
++ if (!CACHE_SSD_ADD_INPROG_IS_SET(dmc))
++ vfree((void *)EIO_CACHE(dmc));
++ pr_err
++ ("md_create: Could not write cache superblock sector(error %d) for cache \"%s\"\n",
++ error, dmc->cache_name);
++ ret = -EIO;
++ goto free_md;
++ }
++
++free_md:
++ for (k = 0; k < nr_pages; k++)
++ kunmap(pages[k].bv_page);
++ kfree(pg_virt_addr);
++
++ /* Free metadata pages here. */
++ if (pages) {
++ for (k = 0; k < nr_pages; k++)
++ put_page(pages[k].bv_page);
++ kfree(pages);
++ pages = NULL;
++ }
++
++free_header:
++ /* Free header page here */
++ if (header_page) {
++ kunmap(header_page[0].bv_page);
++ put_page(header_page[0].bv_page);
++ kfree(header_page);
++ header_page = NULL;
++ }
++
++ return ret;
++}
++
++static int eio_md_load(struct cache_c *dmc)
++{
++ struct flash_cacheblock *meta_data_cacheblock, *next_ptr;
++ union eio_superblock *header;
++ struct eio_io_region where;
++ int i;
++ index_t j, slots_read;
++ sector_t size;
++ int clean_shutdown;
++ int dirty_loaded = 0;
++ sector_t order, data_size;
++ int num_valid = 0;
++ int error;
++ sector_t sectors_read = 0, sectors_expected = 0; /* Debug */
++ int force_warm_boot = 0;
++
++ struct bio_vec *header_page, *pages;
++ int nr_pages, page_count, page_index;
++ int ret = 0;
++ void **pg_virt_addr;
++
++ page_count = 0;
++ header_page = eio_alloc_pages(1, &page_count);
++ if (header_page == NULL) {
++ pr_err("md_load: Unable to allocate memory");
++ return -ENOMEM;
++ }
++
++ EIO_ASSERT(page_count == 1);
++ header = (union eio_superblock *)kmap(header_page[0].bv_page);
++
++ if (CACHE_FAILED_IS_SET(dmc) || CACHE_DEGRADED_IS_SET(dmc)) {
++ pr_err
++ ("md_load: Cannot load metadata in failed / degraded mode");
++ ret = -ENODEV;
++ goto free_header;
++ }
++
++ where.bdev = dmc->cache_dev->bdev;
++ where.sector = EIO_SUPERBLOCK_START;
++ where.count = eio_to_sector(EIO_SUPERBLOCK_SIZE);
++ error = eio_io_sync_vm(dmc, &where, READ, header_page, 1);
++ if (error) {
++ pr_err
++ ("md_load: Could not read cache superblock sector %llu error %d",
++ (unsigned long long)where.sector, error);
++ ret = -EINVAL;
++ goto free_header;
++ }
++
++ /* check ondisk superblock version */
++ if (le32_to_cpu(header->sbf.cache_version) != EIO_SB_VERSION) {
++ pr_info("md_load: Cache superblock mismatch detected." \
++ " (current: %u, ondisk: %u)", EIO_SB_VERSION,
++ header->sbf.cache_version);
++
++ if (le32_to_cpu(header->sbf.cache_version) == 0) {
++ pr_err("md_load: Can't enable cache %s. Either " \
++ "superblock version is invalid or cache has" \
++ " been deleted", header->sbf.cache_name);
++ ret = 1;
++ goto free_header;
++ }
++
++ if (le32_to_cpu(header->sbf.cache_version) > EIO_SB_VERSION) {
++ pr_err("md_load: Can't enable cache %s with newer " \
++ " superblock version.", header->sbf.cache_name);
++ ret = 1;
++ goto free_header;
++ }
++
++ if (le32_to_cpu(header->sbf.mode) == CACHE_MODE_WB) {
++ pr_err("md_load: Can't enable write-back cache %s" \
++ " with newer superblock version.",
++ header->sbf.cache_name);
++ ret = 1;
++ goto free_header;
++ } else if ((le32_to_cpu(header->sbf.mode) == CACHE_MODE_RO) ||
++ (le32_to_cpu(header->sbf.mode) == CACHE_MODE_WT)) {
++ dmc->persistence = CACHE_FORCECREATE;
++ pr_info("md_load: Can't enable cache, recreating" \
++ " cache %s with newer superblock version.",
++ header->sbf.cache_name);
++ ret = 0;
++ goto free_header;
++ }
++ }
++
++ /* check ondisk magic number */
++
++ if (le32_to_cpu(header->sbf.cache_version) >= EIO_SB_MAGIC_VERSION &&
++ le32_to_cpu(header->sbf.magic) != EIO_MAGIC) {
++ pr_err("md_load: Magic number mismatch in superblock detected." \
++ " (current: %u, ondisk: %u)", EIO_MAGIC,
++ le32_to_cpu(header->sbf.magic));
++ ret = 1;
++ goto free_header;
++ }
++
++ dmc->sb_version = EIO_SB_VERSION;
++
++ /*
++ * TBD
++ * For writeback, only when the dirty blocks are non-zero
++ * and header state is unexpected, we should treat it as md corrupted.
++ * Otherwise, a bad write in last shutdown, can lead to data inaccessible
++ * in writeback case.
++ */
++ if (!((le32_to_cpu(header->sbf.cache_sb_state) == CACHE_MD_STATE_DIRTY) ||
++ (le32_to_cpu(header->sbf.cache_sb_state) == CACHE_MD_STATE_CLEAN) ||
++ (le32_to_cpu(header->sbf.cache_sb_state) == CACHE_MD_STATE_FASTCLEAN))) {
++ pr_err("md_load: Corrupt cache superblock");
++ ret = -EINVAL;
++ goto free_header;
++ }
++
++ if (le32_to_cpu(header->sbf.cold_boot) & BOOT_FLAG_FORCE_WARM) {
++ force_warm_boot = 1;
++ header->sbf.cold_boot = cpu_to_le32(le32_to_cpu(header->sbf.cold_boot) &
++ ~BOOT_FLAG_FORCE_WARM);
++ }
++
++ /*
++ * Determine if we can start as cold or hot cache
++ * - if cold_boot is set(unless force_warm_boot), start as cold cache
++ * - else if it is unclean shutdown, start as cold cache
++ * cold cache will still treat the dirty blocks as hot
++ */
++ if (dmc->cold_boot != le32_to_cpu(header->sbf.cold_boot)) {
++ pr_info
++ ("superblock(%u) and config(%u) cold boot values do not match. Relying on config",
++ le32_to_cpu(header->sbf.cold_boot), dmc->cold_boot);
++ }
++ if (dmc->cold_boot && !force_warm_boot) {
++ pr_info
++ ("Cold boot is set, starting as if unclean shutdown(only dirty blocks will be hot)");
++ clean_shutdown = 0;
++ } else {
++ if (le32_to_cpu(header->sbf.cache_sb_state) == CACHE_MD_STATE_DIRTY) {
++ pr_info("Unclean shutdown detected");
++ pr_info("Only dirty blocks exist in cache");
++ clean_shutdown = 0;
++ } else if (le32_to_cpu(header->sbf.cache_sb_state) == CACHE_MD_STATE_CLEAN) {
++ pr_info("Slow (clean) shutdown detected");
++ pr_info("Only clean blocks exist in cache");
++ clean_shutdown = 1;
++ } else if (le32_to_cpu(header->sbf.cache_sb_state) ==
++ CACHE_MD_STATE_FASTCLEAN) {
++ pr_info("Fast (clean) shutdown detected");
++ pr_info("Both clean and dirty blocks exist in cache");
++ clean_shutdown = 1;
++ } else {
++ /* Won't reach here, but TBD may change the previous if condition */
++ pr_info
++ ("cache state is %d. Treating as unclean shutdown",
++ le32_to_cpu(header->sbf.cache_sb_state));
++ pr_info("Only dirty blocks exist in cache");
++ clean_shutdown = 0;
++ }
++ }
++
++ if (!dmc->mode)
++ dmc->mode = le32_to_cpu(header->sbf.mode);
++ if (!dmc->req_policy)
++ dmc->req_policy = le32_to_cpu(header->sbf.repl_policy);
++
++ if (!dmc->cache_flags)
++ dmc->cache_flags = le32_to_cpu(header->sbf.cache_flags);
++
++ error = eio_policy_init(dmc);
++ if (error)
++ goto free_header;
++
++ dmc->block_size = le64_to_cpu(header->sbf.block_size);
++ dmc->block_shift = ffs(dmc->block_size) - 1;
++ dmc->block_mask = dmc->block_size - 1;
++ dmc->size = le32_to_cpu(header->sbf.size);
++ dmc->cache_size = le64_to_cpu(header->sbf.cache_devsize);
++ dmc->assoc = le32_to_cpu(header->sbf.assoc);
++ dmc->consecutive_shift = ffs(dmc->assoc) - 1;
++ dmc->md_start_sect = le64_to_cpu(header->sbf.cache_md_start_sect);
++ dmc->md_sectors = le64_to_cpu(header->sbf.cache_data_start_sect);
++ dmc->sysctl_active.dirty_high_threshold =
++ le32_to_cpu(header->sbf.dirty_high_threshold);
++ dmc->sysctl_active.dirty_low_threshold =
++ le32_to_cpu(header->sbf.dirty_low_threshold);
++ dmc->sysctl_active.dirty_set_high_threshold =
++ le32_to_cpu(header->sbf.dirty_set_high_threshold);
++ dmc->sysctl_active.dirty_set_low_threshold =
++ le32_to_cpu(header->sbf.dirty_set_low_threshold);
++ dmc->sysctl_active.time_based_clean_interval =
++ le32_to_cpu(header->sbf.time_based_clean_interval);
++ dmc->sysctl_active.autoclean_threshold =
++ le32_to_cpu(header->sbf.autoclean_threshold);
++
++ i = eio_mem_init(dmc);
++ if (i == -1) {
++ pr_err("eio_md_load: Failed to initialize memory.");
++ ret = -EINVAL;
++ goto free_header;
++ }
++
++ order =
++ dmc->size *
++ ((i ==
++ 1) ? sizeof(struct cacheblock_md8) : sizeof(struct cacheblock));
++ data_size = dmc->size * dmc->block_size;
++ size =
++ EIO_MD8(dmc) ? sizeof(struct cacheblock_md8) : sizeof(struct
++ cacheblock);
++ pr_info("Allocate %lluKB (%lluB per) mem for %llu-entry cache " \
++ "(capacity:%lluMB, associativity:%u, block size:%u bytes)",
++ (unsigned long long)order >> 10, (unsigned long long)size,
++ (long long unsigned int)dmc->size,
++ (long long unsigned int)(dmc->md_sectors + data_size) >> (20 -
++ SECTOR_SHIFT),
++ dmc->assoc, dmc->block_size << SECTOR_SHIFT);
++
++ if (EIO_MD8(dmc))
++ dmc->cache_md8 = vmalloc((size_t)order);
++ else
++ dmc->cache = vmalloc((size_t)order);
++
++ if ((EIO_MD8(dmc) && !dmc->cache_md8) || (!EIO_MD8(dmc) && !dmc->cache)) {
++ pr_err("md_load: Unable to allocate memory");
++ vfree((void *)header);
++ return 1;
++ }
++
++ if (eio_repl_blk_init(dmc->policy_ops) != 0) {
++ vfree((void *)EIO_CACHE(dmc));
++ pr_err
++ ("md_load: Unable to allocate memory for policy cache block");
++ ret = -EINVAL;
++ goto free_header;
++ }
++
++ /* Allocate pages of the order dmc->bio_nr_pages */
++ page_count = 0;
++ pages = eio_alloc_pages(dmc->bio_nr_pages, &page_count);
++ if (!pages) {
++ pr_err("md_create: unable to allocate pages");
++ pr_err("md_create: Could not write out cache metadata");
++ vfree((void *)EIO_CACHE(dmc));
++ ret = -ENOMEM;
++ goto free_header;
++ }
++
++ /* nr_pages is used for freeing the pages */
++ nr_pages = page_count;
++
++ pg_virt_addr = kmalloc(nr_pages * (sizeof(void *)), GFP_KERNEL);
++ if (pg_virt_addr == NULL) {
++ pr_err("eio_md_store: System memory too low.");
++ for (i = 0; i < nr_pages; i++)
++ put_page(pages[i].bv_page);
++ kfree(pages);
++ ret = -ENOMEM;
++ goto free_header;
++ }
++
++ for (i = 0; i < nr_pages; i++)
++ pg_virt_addr[i] = kmap(pages[i].bv_page);
++
++ /*
++ * Read 1 PAGE of the metadata at a time and load up the
++ * incore metadata struct.
++ */
++
++ page_index = 0;
++ page_count = 0;
++ meta_data_cacheblock =
++ (struct flash_cacheblock *)pg_virt_addr[page_index];
++
++ where.bdev = dmc->cache_dev->bdev;
++ where.sector = dmc->md_start_sect;
++ size = dmc->size;
++ i = 0;
++ while (size > 0) {
++ slots_read =
++ min((long)size, ((long)MD_BLOCKS_PER_PAGE * nr_pages));
++
++ if (slots_read % MD_BLOCKS_PER_SECTOR)
++ where.count = 1 + (slots_read / MD_BLOCKS_PER_SECTOR);
++ else
++ where.count = slots_read / MD_BLOCKS_PER_SECTOR;
++
++ if (slots_read % MD_BLOCKS_PER_PAGE)
++ page_count = 1 + (slots_read / MD_BLOCKS_PER_PAGE);
++ else
++ page_count = slots_read / MD_BLOCKS_PER_PAGE;
++
++ sectors_read += where.count; /* Debug */
++ error = eio_io_sync_vm(dmc, &where, READ, pages, page_count);
++ if (error) {
++ vfree((void *)EIO_CACHE(dmc));
++ pr_err
++ ("md_load: Could not read cache metadata sector %llu error %d",
++ (unsigned long long)where.sector, error);
++ ret = -EIO;
++ goto free_md;
++ }
++
++ where.sector += where.count;
++ next_ptr = meta_data_cacheblock;
++
++ for (j = 0, page_index = 0; j < slots_read; j++) {
++
++ if ((j % MD_BLOCKS_PER_PAGE) == 0)
++ next_ptr =
++ (struct flash_cacheblock *)
++ pg_virt_addr[page_index++];
++
++ /* If unclean shutdown, only the DIRTY blocks are loaded.*/
++ if (clean_shutdown || (next_ptr->cache_state & DIRTY)) {
++
++ if (next_ptr->cache_state & DIRTY)
++ dirty_loaded++;
++
++ EIO_CACHE_STATE_SET(dmc, i,
++ (u_int8_t)le64_to_cpu(next_ptr->
++ cache_state) & ~QUEUED);
++
++ EIO_ASSERT((EIO_CACHE_STATE_GET(dmc, i) &
++ (VALID | INVALID))
++ != (VALID | INVALID));
++
++ if (EIO_CACHE_STATE_GET(dmc, i) & VALID)
++ num_valid++;
++ EIO_DBN_SET(dmc, i, le64_to_cpu(next_ptr->dbn));
++ } else
++ eio_invalidate_md(dmc, i);
++ next_ptr++;
++ i++;
++ }
++ size -= slots_read;
++ }
++
++ /*
++ * If the cache contains dirty data, the only valid mode is write back.
++ */
++ if (dirty_loaded && dmc->mode != CACHE_MODE_WB) {
++ vfree((void *)EIO_CACHE(dmc));
++ pr_err
++ ("md_load: Cannot use %s mode because dirty data exists in the cache",
++ (dmc->mode ==
++ CACHE_MODE_RO) ? "read only" : "write through");
++ ret = -EINVAL;
++ goto free_md;
++ }
++
++ /* Debug Tests */
++ sectors_expected = EIO_DIV(dmc->size, MD_BLOCKS_PER_SECTOR);
++ if (EIO_REM(dmc->size, MD_BLOCKS_PER_SECTOR))
++ sectors_expected++;
++ if (sectors_expected != sectors_read) {
++ pr_err
++ ("md_load: Sector mismatch! sectors_expected=%llu, sectors_read=%llu\n",
++ (unsigned long long)sectors_expected, (unsigned long long)sectors_read);
++ vfree((void *)EIO_CACHE(dmc));
++ ret = -EIO;
++ goto free_md;
++ }
++
++ /* Before we finish loading, we need to dirty the superblock and write it out */
++ dmc->sb_state = CACHE_MD_STATE_DIRTY;
++ error = eio_sb_store(dmc);
++ if (error) {
++ vfree((void *)EIO_CACHE(dmc));
++ pr_err
++ ("md_load: Could not write cache superblock sector(error %d)",
++ error);
++ ret = 1;
++ goto free_md;
++ }
++
++free_md:
++ for (i = 0; i < nr_pages; i++)
++ kunmap(pages[i].bv_page);
++ kfree(pg_virt_addr);
++
++ if (pages) {
++ for (i = 0; i < nr_pages; i++)
++ put_page(pages[i].bv_page);
++ kfree(pages);
++ pages = NULL;
++ }
++
++free_header:
++ /* Free header page here */
++ if (header_page) {
++ kunmap(header_page[0].bv_page);
++ put_page(header_page[0].bv_page);
++ kfree(header_page);
++ header_page = NULL;
++ }
++
++ pr_info("Cache metadata loaded from disk with %d valid %d dirty blocks",
++ num_valid, dirty_loaded);
++ return ret;
++}
++
++void eio_policy_free(struct cache_c *dmc)
++{
++
++ if (dmc->policy_ops != NULL) {
++ eio_put_policy(dmc->policy_ops);
++ vfree(dmc->policy_ops);
++ }
++ if (dmc->sp_cache_blk != NULL)
++ vfree(dmc->sp_cache_blk);
++ if (dmc->sp_cache_set != NULL)
++ vfree(dmc->sp_cache_set);
++
++ dmc->policy_ops = NULL;
++ dmc->sp_cache_blk = dmc->sp_cache_set = NULL;
++ return;
++}
++
++static int eio_clean_thread_init(struct cache_c *dmc)
++{
++ INIT_LIST_HEAD(&dmc->cleanq);
++ spin_lock_init(&dmc->clean_sl);
++ EIO_INIT_EVENT(&dmc->clean_event);
++ return eio_start_clean_thread(dmc);
++}
++
++int
++eio_handle_ssd_message(char *cache_name, char *ssd_name, enum dev_notifier note)
++{
++ struct cache_c *dmc;
++
++ dmc = eio_cache_lookup(cache_name);
++ if (NULL == dmc) {
++ pr_err("eio_handle_ssd_message: cache %s does not exist",
++ cache_name);
++ return -EINVAL;
++ }
++
++ switch (note) {
++
++ case NOTIFY_SSD_ADD:
++ /* Making sure that CACHE state is not active */
++ if (CACHE_FAILED_IS_SET(dmc) || CACHE_DEGRADED_IS_SET(dmc))
++ eio_resume_caching(dmc, ssd_name);
++ else
++ pr_err
++ ("eio_handle_ssd_message: SSD_ADD event called for ACTIVE cache \"%s\", ignoring!!!",
++ dmc->cache_name);
++ break;
++
++ case NOTIFY_SSD_REMOVED:
++ eio_suspend_caching(dmc, note);
++ break;
++
++ default:
++ pr_err("Wrong notifier passed for eio_handle_ssd_message\n");
++ }
++
++ return 0;
++}
++
++static void eio_init_ssddev_props(struct cache_c *dmc)
++{
++ struct request_queue *rq;
++ uint32_t max_hw_sectors, max_nr_pages;
++ uint32_t nr_pages = 0;
++
++ rq = bdev_get_queue(dmc->cache_dev->bdev);
++ max_hw_sectors = to_bytes(queue_max_hw_sectors(rq)) / PAGE_SIZE;
++ max_nr_pages = (u_int32_t)bio_get_nr_vecs(dmc->cache_dev->bdev);
++ nr_pages = min_t(u_int32_t, max_hw_sectors, max_nr_pages);
++ dmc->bio_nr_pages = nr_pages;
++
++ /*
++ * If the cache device is not a physical device (eg: lv), then
++ * driverfs_dev will be null and we make cache_gendisk_name a null
++ * string. The eio_notify_ssd_rm() function in this case,
++ * cannot detect device removal, and therefore, we will have to rely
++ * on user space udev for the notification.
++ */
++
++ if (dmc->cache_dev && dmc->cache_dev->bdev &&
++ dmc->cache_dev->bdev->bd_disk &&
++ dmc->cache_dev->bdev->bd_disk->driverfs_dev) {
++ strncpy(dmc->cache_gendisk_name,
++ dev_name(dmc->cache_dev->bdev->bd_disk->driverfs_dev),
++ DEV_PATHLEN);
++ } else
++ dmc->cache_gendisk_name[0] = '\0';
++}
++
++static void eio_init_srcdev_props(struct cache_c *dmc)
++{
++ /* Same applies for source device as well. */
++ if (dmc->disk_dev && dmc->disk_dev->bdev &&
++ dmc->disk_dev->bdev->bd_disk &&
++ dmc->disk_dev->bdev->bd_disk->driverfs_dev) {
++ strncpy(dmc->cache_srcdisk_name,
++ dev_name(dmc->disk_dev->bdev->bd_disk->driverfs_dev),
++ DEV_PATHLEN);
++ } else
++ dmc->cache_srcdisk_name[0] = '\0';
++}
++
++int eio_cache_create(struct cache_rec_short *cache)
++{
++ struct cache_c *dmc;
++ struct cache_c **nodepp;
++ unsigned int consecutive_blocks;
++ u_int64_t i;
++ index_t prev_set;
++ index_t cur_set;
++ sector_t order;
++ int error = -EINVAL;
++ uint32_t persistence = 0;
++ fmode_t mode = (FMODE_READ | FMODE_WRITE);
++ char *strerr = NULL;
++
++ dmc = kzalloc(sizeof(*dmc), GFP_KERNEL);
++ if (dmc == NULL) {
++ strerr = "Failed to allocate memory for cache context";
++ error = -ENOMEM;
++ goto bad;
++ }
++
++ /*
++ * Source device.
++ */
++
++ error = eio_ttc_get_device(cache->cr_src_devname, mode, &dmc->disk_dev);
++ if (error) {
++ strerr = "get_device for source device failed";
++ goto bad1;
++ }
++
++ dmc->disk_size = eio_to_sector(eio_get_device_size(dmc->disk_dev));
++ if (dmc->disk_size >= EIO_MAX_SECTOR) {
++ strerr = "Source device too big to support";
++ error = -EFBIG;
++ goto bad2;
++ }
++ strncpy(dmc->disk_devname, cache->cr_src_devname, DEV_PATHLEN);
++
++ /*
++ * Cache device.
++ */
++
++ error =
++ eio_ttc_get_device(cache->cr_ssd_devname, mode | FMODE_EXCL, &dmc->cache_dev);
++ if (error) {
++ strerr = "get_device for cache device failed";
++ goto bad2;
++ }
++
++ if (dmc->disk_dev == dmc->cache_dev) {
++ error = -EINVAL;
++ strerr = "Same devices specified";
++ goto bad3;
++ }
++ strncpy(dmc->cache_devname, cache->cr_ssd_devname, DEV_PATHLEN);
++
++ if (cache->cr_name[0] != '\0') {
++ strncpy(dmc->cache_name, cache->cr_name,
++ sizeof(dmc->cache_name));
++ /* make sure it is zero terminated */
++ dmc->cache_name[sizeof(dmc->cache_name) - 1] = '\x00';
++ } else {
++ strerr = "Need cache name";
++ error = -EINVAL;
++ goto bad3;
++ }
++
++ strncpy(dmc->ssd_uuid, cache->cr_ssd_uuid, DEV_PATHLEN - 1);
++
++ dmc->cache_dev_start_sect = eio_get_device_start_sect(dmc->cache_dev);
++ error = eio_do_preliminary_checks(dmc);
++ if (error) {
++ if (error == -EINVAL)
++ strerr = "Either Source and Cache devices belong to "
++ "same device or a cache already exists on"
++ " specified source device";
++ else if (error == -EEXIST)
++ strerr = "Cache already exists";
++ goto bad3;
++ }
++
++ eio_init_ssddev_props(dmc);
++ eio_init_srcdev_props(dmc);
++
++ /*
++ * Initialize the io callback queue.
++ */
++
++ dmc->callback_q = create_singlethread_workqueue("eio_callback");
++ if (!dmc->callback_q) {
++ error = -ENOMEM;
++ strerr = "Failed to initialize callback workqueue";
++ goto bad4;
++ }
++ error = eio_kcached_init(dmc);
++ if (error) {
++ strerr = "Failed to initialize kcached";
++ goto bad4;
++ }
++
++ /*
++ * We read policy before reading other args. The reason is that
++ * if there is a policy module loaded, we first need dmc->p_ops to be
++ * allocated so that it is non NULL. Once p_ops is !NULL, cache_blk_init
++ * and cache_set_init can set their pointers to dmc->p_ops->xxx
++ *
++ * policy_ops == NULL is not really an error. It just means that there
++ * is no registered policy and therefore we use EIO_REPL_RANDOM (random)
++ * as the replacement policy.
++ */
++
++ /* We do a kzalloc for dmc, but being extra careful here */
++ dmc->sp_cache_blk = NULL;
++ dmc->sp_cache_set = NULL;
++ dmc->policy_ops = NULL;
++ if (cache->cr_policy) {
++ dmc->req_policy = cache->cr_policy;
++ if (dmc->req_policy && (dmc->req_policy < CACHE_REPL_FIRST ||
++ dmc->req_policy > CACHE_REPL_LAST)) {
++ strerr = "Invalid cache policy";
++ error = -EINVAL;
++ goto bad5;
++ }
++ }
++
++ /*
++ * We need to determine the requested cache mode before we call
++ * eio_md_load becuase it examines dmc->mode. The cache mode is
++ * set as follows:
++ * 1. For a "reload" operation:
++ * - if mode is not provided as an argument,
++ it is read from superblock.
++ * - if mode is provided as an argument,
++ eio_md_load verifies that it is valid.
++ * 2. For a "create" operation:
++ * - if mode is not provided, it is set to CACHE_MODE_DEFAULT.
++ * - if mode is provided, it is validate and set.
++ */
++ if (cache->cr_mode) {
++ dmc->mode = cache->cr_mode;
++ if (dmc->mode && (dmc->mode < CACHE_MODE_FIRST ||
++ dmc->mode > CACHE_MODE_LAST)) {
++ strerr = "Invalid cache mode";
++ error = -EINVAL;
++ goto bad5;
++ }
++ }
++
++ dmc->cold_boot = cache->cr_cold_boot;
++ if ((dmc->cold_boot != 0) && (dmc->cold_boot != BOOT_FLAG_COLD_ENABLE)) {
++ strerr = "Invalid cold boot option";
++ error = -EINVAL;
++ goto bad5;
++ }
++
++ if (cache->cr_persistence) {
++ persistence = cache->cr_persistence;
++ if (persistence < CACHE_RELOAD ||
++ persistence > CACHE_FORCECREATE) {
++ pr_err("ctr: persistence = %d", persistence);
++ strerr = "Invalid cache persistence";
++ error = -EINVAL;
++ goto bad5;
++ }
++ dmc->persistence = persistence;
++ }
++ if (persistence == CACHE_RELOAD) {
++ if (eio_md_load(dmc)) {
++ strerr = "Failed to reload cache";
++ error = -EINVAL;
++ goto bad5;
++ }
++
++ /*
++ * "eio_md_load" will reset "dmc->persistence" from
++ * CACHE_RELOAD to CACHE_FORCECREATE in the case of
++ * cache superblock version mismatch and cache mode
++ * is Read-Only or Write-Through.
++ */
++ if (dmc->persistence != persistence)
++ persistence = dmc->persistence;
++ }
++
++ /*
++ * Now that we're back from "eio_md_load" in the case of a reload,
++ * we're ready to finish setting up the mode and policy.
++ */
++ if (dmc->mode == 0) {
++ dmc->mode = CACHE_MODE_DEFAULT;
++ pr_info("Setting mode to default");
++ } else {
++ pr_info("Setting mode to %s ",
++ (dmc->mode == CACHE_MODE_WB) ? "write back" :
++ ((dmc->mode == CACHE_MODE_RO) ? "read only" :
++ "write through"));
++ }
++
++ /* eio_policy_init() is already called from within eio_md_load() */
++ if (persistence != CACHE_RELOAD) {
++ error = eio_policy_init(dmc);
++ if (error) {
++ strerr = "Failed to initialize policy";
++ goto bad5;
++ }
++ }
++
++ if (cache->cr_flags) {
++ int flags;
++ flags = cache->cr_flags;
++ if (flags == 0)
++ dmc->cache_flags &= ~CACHE_FLAGS_INVALIDATE;
++ else if (flags == 1) {
++ dmc->cache_flags |= CACHE_FLAGS_INVALIDATE;
++ pr_info("Enabling invalidate API");
++ } else
++ pr_info("Ignoring unknown flags value: %u", flags);
++ }
++
++ if (persistence == CACHE_RELOAD)
++ goto init; /* Skip reading cache parameters from command line */
++
++ if (cache->cr_blksize && cache->cr_ssd_sector_size) {
++ dmc->block_size = EIO_DIV(cache->cr_blksize, cache->cr_ssd_sector_size);
++ if (dmc->block_size & (dmc->block_size - 1)) {
++ strerr = "Invalid block size";
++ error = -EINVAL;
++ goto bad5;
++ }
++ if (dmc->block_size == 0)
++ dmc->block_size = DEFAULT_CACHE_BLKSIZE;
++ } else
++ dmc->block_size = DEFAULT_CACHE_BLKSIZE;
++ dmc->block_shift = ffs(dmc->block_size) - 1;
++ dmc->block_mask = dmc->block_size - 1;
++
++ /*
++ * dmc->size is specified in sectors here, and converted to blocks later
++ *
++ * Giving preference to kernel got cache size.
++ * Only when we can't get the cache size in kernel, we accept user passed size.
++ * User mode may be using a different API or could also do some rounding, so we
++ * prefer kernel getting the cache size. In case of device failure and coming back, we
++ * rely on the device size got in kernel and we hope that it is equal to the
++ * one we used for creating the cache, so we ideally should always use the kernel
++ * got cache size.
++ */
++ dmc->size = eio_to_sector(eio_get_device_size(dmc->cache_dev));
++ if (dmc->size == 0) {
++ if (cache->cr_ssd_dev_size && cache->cr_ssd_sector_size)
++ dmc->size =
++ EIO_DIV(cache->cr_ssd_dev_size, cache->cr_ssd_sector_size);
++
++ if (dmc->size == 0) {
++ strerr = "Invalid cache size or can't be fetched";
++ error = -EINVAL;
++ goto bad5;
++ }
++ }
++
++ dmc->cache_size = dmc->size;
++
++ if (cache->cr_assoc) {
++ dmc->assoc = cache->cr_assoc;
++ if ((dmc->assoc & (dmc->assoc - 1)) ||
++ dmc->assoc > EIO_MAX_ASSOC || dmc->size < dmc->assoc) {
++ strerr = "Invalid cache associativity";
++ error = -EINVAL;
++ goto bad5;
++ }
++ if (dmc->assoc == 0)
++ dmc->assoc = DEFAULT_CACHE_ASSOC;
++ } else
++ dmc->assoc = DEFAULT_CACHE_ASSOC;
++
++ /*
++ * initialize to an invalid index
++ */
++
++ dmc->index_zero = dmc->assoc + 1;
++
++ /*
++ * Although it's very unlikely, we need to make sure that
++ * for the given associativity and block size our source
++ * device will have less than 4 billion sets.
++ */
++
++ i = EIO_DIV(eio_to_sector(eio_get_device_size(dmc->disk_dev)),
++ (dmc->assoc * dmc->block_size));
++ if (i >= (((u_int64_t)1) << 32)) {
++ strerr = "Too many cache sets to support";
++ goto bad5;
++ }
++
++ consecutive_blocks = dmc->assoc;
++ dmc->consecutive_shift = ffs(consecutive_blocks) - 1;
++
++ /* Initialize persistent thresholds */
++ dmc->sysctl_active.dirty_high_threshold = DIRTY_HIGH_THRESH_DEF;
++ dmc->sysctl_active.dirty_low_threshold = DIRTY_LOW_THRESH_DEF;
++ dmc->sysctl_active.dirty_set_high_threshold = DIRTY_SET_HIGH_THRESH_DEF;
++ dmc->sysctl_active.dirty_set_low_threshold = DIRTY_SET_LOW_THRESH_DEF;
++ dmc->sysctl_active.autoclean_threshold = AUTOCLEAN_THRESH_DEF;
++ dmc->sysctl_active.time_based_clean_interval =
++ TIME_BASED_CLEAN_INTERVAL_DEF(dmc);
++
++ spin_lock_init(&dmc->cache_spin_lock);
++ if (persistence == CACHE_CREATE) {
++ error = eio_md_create(dmc, /* force */ 0, /* cold */ 1);
++ if (error) {
++ strerr = "Failed to create cache";
++ goto bad5;
++ }
++ } else {
++ error = eio_md_create(dmc, /* force */ 1, /* cold */ 1);
++ if (error) {
++ strerr = "Failed to force create cache";
++ goto bad5;
++ }
++ }
++
++init:
++ order = (dmc->size >> dmc->consecutive_shift) *
++ sizeof(struct cache_set);
++
++ if (!eio_mem_available(dmc, order)) {
++ strerr = "System memory too low"
++ " for allocating cache set metadata";
++ error = -ENOMEM;
++ vfree((void *)EIO_CACHE(dmc));
++ goto bad5;
++ }
++
++ dmc->cache_sets = vmalloc((size_t)order);
++ if (!dmc->cache_sets) {
++ strerr = "Failed to allocate memory";
++ error = -ENOMEM;
++ vfree((void *)EIO_CACHE(dmc));
++ goto bad5;
++ }
++
++ for (i = 0; i < (dmc->size >> dmc->consecutive_shift); i++) {
++ dmc->cache_sets[i].nr_dirty = 0;
++ spin_lock_init(&dmc->cache_sets[i].cs_lock);
++ init_rwsem(&dmc->cache_sets[i].rw_lock);
++ dmc->cache_sets[i].mdreq = NULL;
++ dmc->cache_sets[i].flags = 0;
++ }
++ error = eio_repl_sets_init(dmc->policy_ops);
++ if (error < 0) {
++ strerr = "Failed to allocate memory for cache policy";
++ vfree((void *)dmc->cache_sets);
++ vfree((void *)EIO_CACHE(dmc));
++ goto bad5;
++ }
++ eio_policy_lru_pushblks(dmc->policy_ops);
++
++ if (dmc->mode == CACHE_MODE_WB) {
++ error = eio_allocate_wb_resources(dmc);
++ if (error) {
++ vfree((void *)dmc->cache_sets);
++ vfree((void *)EIO_CACHE(dmc));
++ goto bad5;
++ }
++ }
++
++ dmc->sysctl_active.error_inject = 0;
++ dmc->sysctl_active.fast_remove = 0;
++ dmc->sysctl_active.zerostats = 0;
++ dmc->sysctl_active.do_clean = 0;
++
++ atomic_set(&dmc->clean_index, 0);
++
++ atomic64_set(&dmc->nr_ios, 0);
++
++ /*
++ * sysctl_mem_limit_pct [0 - 100]. Before doing a vmalloc()
++ * make sure that the allocation size requested is less than
++ * sysctl_mem_limit_pct percentage of the free RAM available
++ * in the system. This is to avoid OOM errors in Linux.
++ * 0 => do the vmalloc without checking system memory.
++ */
++
++ dmc->sysctl_active.mem_limit_pct = 75;
++
++ (void)wait_on_bit_lock((void *)&eio_control->synch_flags,
++ EIO_UPDATE_LIST, eio_wait_schedule,
++ TASK_UNINTERRUPTIBLE);
++ dmc->next_cache = cache_list_head;
++ cache_list_head = dmc;
++ clear_bit(EIO_UPDATE_LIST, (void *)&eio_control->synch_flags);
++ smp_mb__after_clear_bit();
++ wake_up_bit((void *)&eio_control->synch_flags, EIO_UPDATE_LIST);
++
++ prev_set = -1;
++ for (i = 0; i < dmc->size; i++) {
++ if (EIO_CACHE_STATE_GET(dmc, i) & VALID)
++ atomic64_inc(&dmc->eio_stats.cached_blocks);
++ if (EIO_CACHE_STATE_GET(dmc, i) & DIRTY) {
++ dmc->cache_sets[EIO_DIV(i, dmc->assoc)].nr_dirty++;
++ atomic64_inc(&dmc->nr_dirty);
++ cur_set = EIO_DIV(i, dmc->assoc);
++ if (prev_set != cur_set) {
++ /* Move the given set at the head of the set LRU list */
++ eio_touch_set_lru(dmc, cur_set);
++ prev_set = cur_set;
++ }
++ }
++ }
++
++ INIT_WORK(&dmc->readfill_wq, eio_do_readfill);
++
++ /*
++ * invalid index, but signifies cache successfully built
++ */
++
++ dmc->index_zero = dmc->assoc;
++
++ eio_procfs_ctr(dmc);
++
++ /*
++ * Activate Application Transparent Caching.
++ */
++
++ error = eio_ttc_activate(dmc);
++ if (error)
++ goto bad6;
++
++ /*
++ * In future if anyone adds code here and something fails,
++ * do call eio_ttc_deactivate(dmc) as part of cleanup.
++ */
++
++ return 0;
++
++bad6:
++ eio_procfs_dtr(dmc);
++ if (dmc->mode == CACHE_MODE_WB) {
++ eio_stop_async_tasks(dmc);
++ eio_free_wb_resources(dmc);
++ }
++ vfree((void *)dmc->cache_sets);
++ vfree((void *)EIO_CACHE(dmc));
++
++ (void)wait_on_bit_lock((void *)&eio_control->synch_flags,
++ EIO_UPDATE_LIST, eio_wait_schedule,
++ TASK_UNINTERRUPTIBLE);
++ nodepp = &cache_list_head;
++ while (*nodepp != NULL) {
++ if (*nodepp == dmc) {
++ *nodepp = dmc->next_cache;
++ break;
++ }
++ nodepp = &((*nodepp)->next_cache);
++ }
++ clear_bit(EIO_UPDATE_LIST, (void *)&eio_control->synch_flags);
++ smp_mb__after_clear_bit();
++ wake_up_bit((void *)&eio_control->synch_flags, EIO_UPDATE_LIST);
++bad5:
++ eio_kcached_client_destroy(dmc);
++bad4:
++bad3:
++ eio_put_cache_device(dmc);
++bad2:
++ eio_ttc_put_device(&dmc->disk_dev);
++bad1:
++ eio_policy_free(dmc);
++ kfree(dmc);
++bad:
++ if (strerr)
++ pr_err("Cache creation failed: %s.\n", strerr);
++ return error;
++}
++
++/*
++ * Destroy the cache mapping.
++ */
++
++int eio_cache_delete(char *cache_name, int do_delete)
++{
++ struct cache_c *dmc;
++ struct cache_c **nodepp;
++ int ret, error;
++ int restart_async_task;
++
++ ret = 0;
++ restart_async_task = 0;
++
++ dmc = eio_cache_lookup(cache_name);
++ if (NULL == dmc) {
++ pr_err("cache delete: cache \"%s\" doesn't exist.", cache_name);
++ return -EINVAL;
++ }
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, dmc->cache_spin_lock_flags);
++ if (dmc->cache_flags & CACHE_FLAGS_SHUTDOWN_INPROG) {
++ pr_err("cache_delete: system shutdown in progress, cannot " \
++ "delete cache %s", cache_name);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return -EINVAL;
++ }
++ if (dmc->cache_flags & CACHE_FLAGS_MOD_INPROG) {
++ pr_err
++ ("cache_delete: simultaneous edit/delete operation " \
++ " on cache %s is not permitted", cache_name);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return -EINVAL;
++ }
++ dmc->cache_flags |= CACHE_FLAGS_MOD_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++
++ /*
++ * Earlier attempt to delete failed.
++ * Allow force deletes only for FAILED caches.
++ */
++ if (unlikely(CACHE_STALE_IS_SET(dmc))) {
++ if (likely(CACHE_FAILED_IS_SET(dmc))) {
++ pr_err
++ ("cache_delete: Cache \"%s\" is in STALE state. Force deleting!!!",
++ dmc->cache_name);
++ goto force_delete;
++ } else {
++ if (atomic64_read(&dmc->nr_dirty) != 0) {
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_MOD_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->
++ cache_spin_lock_flags);
++ pr_err
++ ("cache_delete: Stale Cache detected with dirty blocks=%lld.\n",
++ (long long)atomic64_read(&dmc->nr_dirty));
++ pr_err
++ ("cache_delete: Cache \"%s\" wont be deleted. Deleting will result in data corruption.\n",
++ dmc->cache_name);
++ return -EINVAL;
++ }
++ }
++ }
++
++ eio_stop_async_tasks(dmc);
++
++ /*
++ * Deactivate Application Transparent Caching.
++ * For wb cache, finish_nr_dirty may take long time.
++ * It should be guaranteed that normal cache delete should succeed
++ * only when finish_nr_dirty is completely done.
++ */
++
++ if (eio_ttc_deactivate(dmc, 0)) {
++
++ /* If deactivate fails; only option is to delete cache. */
++ pr_err("cache_delete: Failed to deactivate the cache \"%s\".",
++ dmc->cache_name);
++ if (CACHE_FAILED_IS_SET(dmc))
++ pr_err
++ ("cache_delete: Use -f option to delete the cache \"%s\".",
++ dmc->cache_name);
++ ret = -EPERM;
++ dmc->cache_flags |= CACHE_FLAGS_STALE;
++
++ /* Restart async tasks. */
++ restart_async_task = 1;
++ goto out;
++ }
++
++ if (!CACHE_FAILED_IS_SET(dmc))
++ EIO_ASSERT(dmc->sysctl_active.fast_remove
++ || (atomic64_read(&dmc->nr_dirty) == 0));
++
++ /*
++ * If ttc_deactivate succeeded... proceed with cache delete.
++ * Dont entertain device failure hereafter.
++ */
++ if (unlikely(CACHE_FAILED_IS_SET(dmc)) ||
++ unlikely(CACHE_DEGRADED_IS_SET(dmc))) {
++ pr_err
++ ("cache_delete: Cannot update metadata of cache \"%s\" in failed/degraded mode.",
++ dmc->cache_name);
++ } else
++ eio_md_store(dmc);
++
++force_delete:
++ eio_procfs_dtr(dmc);
++
++ if (CACHE_STALE_IS_SET(dmc)) {
++ pr_info("Force deleting cache \"%s\"!!!.", dmc->cache_name);
++ eio_ttc_deactivate(dmc, 1);
++ }
++
++ eio_free_wb_resources(dmc);
++ vfree((void *)EIO_CACHE(dmc));
++ vfree((void *)dmc->cache_sets);
++ eio_ttc_put_device(&dmc->disk_dev);
++ eio_put_cache_device(dmc);
++ (void)wait_on_bit_lock((void *)&eio_control->synch_flags,
++ EIO_UPDATE_LIST, eio_wait_schedule,
++ TASK_UNINTERRUPTIBLE);
++ nodepp = &cache_list_head;
++ while (*nodepp != NULL) {
++ if (*nodepp == dmc) {
++ *nodepp = dmc->next_cache;
++ break;
++ }
++ nodepp = &((*nodepp)->next_cache);
++ }
++ clear_bit(EIO_UPDATE_LIST, &eio_control->synch_flags);
++ smp_mb__after_clear_bit();
++ wake_up_bit((void *)&eio_control->synch_flags, EIO_UPDATE_LIST);
++
++out:
++ if (restart_async_task) {
++ EIO_ASSERT(dmc->clean_thread == NULL);
++ error = eio_start_clean_thread(dmc);
++ if (error)
++ pr_err
++ ("cache_delete: Failed to restart async tasks. error=%d\n",
++ error);
++ }
++ spin_lock_irqsave(&dmc->cache_spin_lock, dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_MOD_INPROG;
++ if (!ret)
++ dmc->cache_flags |= CACHE_FLAGS_DELETED;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++
++ if (!ret) {
++ eio_policy_free(dmc);
++
++ /*
++ * We don't need synchronisation since at this point the dmc is
++ * no more accessible via lookup.
++ */
++
++ if (!(dmc->cache_flags & CACHE_FLAGS_SHUTDOWN_INPROG))
++ kfree(dmc);
++ }
++
++ return ret;
++}
++
++/*
++ * Reconstruct a degraded cache after the SSD is added.
++ * This function mimics the constructor eio_ctr() except
++ * for code that does not require re-initialization.
++ */
++int eio_ctr_ssd_add(struct cache_c *dmc, char *dev)
++{
++ int r = 0;
++ struct eio_bdev *prev_cache_dev;
++ u_int32_t prev_persistence = dmc->persistence;
++ fmode_t mode = (FMODE_READ | FMODE_WRITE);
++
++ /* verify if source device is present */
++ EIO_ASSERT(dmc->eio_errors.no_source_dev == 0);
++
++ /* mimic relevant portions from eio_ctr() */
++
++ prev_cache_dev = dmc->cache_dev;
++ r = eio_ttc_get_device(dev, mode, &dmc->cache_dev);
++ if (r) {
++ dmc->cache_dev = prev_cache_dev;
++ pr_err("ctr_ssd_add: Failed to lookup cache device %s", dev);
++ return -EINVAL;
++ }
++ /*
++ * For Linux, we have to put the old SSD device now because
++ * we did not do so during SSD removal.
++ */
++ eio_ttc_put_device(&prev_cache_dev);
++
++ /* sanity check */
++ if (dmc->cache_size != eio_to_sector(eio_get_device_size(dmc->cache_dev))) {
++ pr_err("ctr_ssd_add: Cache device size has changed," \
++ "expected (%llu) found (%llu)" \
++ "continuing in degraded mode",
++ (unsigned long long)dmc->cache_size,
++ (unsigned long long)eio_to_sector(
++ eio_get_device_size(dmc->cache_dev)));
++ r = -EINVAL;
++ goto out;
++ }
++
++ /* sanity check for cache device start sector */
++ if (dmc->cache_dev_start_sect !=
++ eio_get_device_start_sect(dmc->cache_dev)) {
++ pr_err("ctr_ssd_add: Cache device starting sector changed," \
++ "expected (%llu) found (%llu) continuing in" \
++ "degraded mode", (unsigned long long)dmc->cache_dev_start_sect,
++ (unsigned long long)eio_get_device_start_sect(dmc->cache_dev));
++ r = -EINVAL;
++ goto out;
++ }
++
++ strncpy(dmc->cache_devname, dev, DEV_PATHLEN);
++ eio_init_ssddev_props(dmc);
++ dmc->size = dmc->cache_size; /* dmc->size will be recalculated in eio_md_create() */
++
++ /*
++ * In case of writeback mode, trust the content of SSD and reload the MD.
++ */
++ dmc->persistence = CACHE_FORCECREATE;
++
++ eio_policy_free(dmc);
++ r = eio_policy_init(dmc);
++ if (r) {
++ pr_err("ctr_ssd_add: Failed to initialize policy");
++ goto out;
++ }
++
++ r = eio_md_create(dmc, /* force */ 1, /* cold */
++ (dmc->mode != CACHE_MODE_WB));
++ if (r) {
++ pr_err
++ ("ctr_ssd_add: Failed to create md, continuing in degraded mode");
++ goto out;
++ }
++
++ r = eio_repl_sets_init(dmc->policy_ops);
++ if (r < 0) {
++ pr_err
++ ("ctr_ssd_add: Failed to allocate memory for cache policy");
++ goto out;
++ }
++ eio_policy_lru_pushblks(dmc->policy_ops);
++ if (dmc->mode != CACHE_MODE_WB)
++ /* Cold cache will reset the stats */
++ memset(&dmc->eio_stats, 0, sizeof(dmc->eio_stats));
++
++ return 0;
++out:
++ dmc->persistence = prev_persistence;
++
++ return r;
++}
++
++/*
++ * Stop the async tasks for a cache(threads, scheduled works).
++ * Used during the cache remove
++ */
++void eio_stop_async_tasks(struct cache_c *dmc)
++{
++ unsigned long flags = 0;
++
++ if (dmc->clean_thread) {
++ dmc->sysctl_active.fast_remove = 1;
++ spin_lock_irqsave(&dmc->clean_sl, flags);
++ EIO_SET_EVENT_AND_UNLOCK(&dmc->clean_event, &dmc->clean_sl,
++ flags);
++ eio_wait_thread_exit(dmc->clean_thread,
++ &dmc->clean_thread_running);
++ EIO_CLEAR_EVENT(&dmc->clean_event);
++ dmc->clean_thread = NULL;
++ }
++
++ dmc->sysctl_active.fast_remove = CACHE_FAST_REMOVE_IS_SET(dmc) ? 1 : 0;
++
++ if (dmc->mode == CACHE_MODE_WB) {
++ /*
++ * Prevent new I/Os to schedule the time based cleaning.
++ * Cancel existing delayed work
++ */
++ dmc->sysctl_active.time_based_clean_interval = 0;
++ cancel_delayed_work_sync(&dmc->clean_aged_sets_work);
++ }
++}
++
++int eio_start_clean_thread(struct cache_c *dmc)
++{
++ EIO_ASSERT(dmc->clean_thread == NULL);
++ EIO_ASSERT(dmc->mode == CACHE_MODE_WB);
++ EIO_ASSERT(dmc->clean_thread_running == 0);
++ EIO_ASSERT(!(dmc->sysctl_active.do_clean & EIO_CLEAN_START));
++
++ dmc->clean_thread = eio_create_thread(eio_clean_thread_proc,
++ (void *)dmc, "eio_clean_thread");
++ if (!dmc->clean_thread)
++ return -EFAULT;
++ return 0;
++}
++
++int eio_allocate_wb_resources(struct cache_c *dmc)
++{
++ int nr_bvecs, nr_pages;
++ unsigned iosize;
++ int ret;
++
++ EIO_ASSERT(dmc->clean_dbvecs == NULL);
++ EIO_ASSERT(dmc->clean_mdpages == NULL);
++ EIO_ASSERT(dmc->dbvec_count == 0);
++ EIO_ASSERT(dmc->mdpage_count == 0);
++
++ /* Data page allocations are done in terms of "bio_vec" structures */
++ iosize = (dmc->block_size * dmc->assoc) << SECTOR_SHIFT;
++ nr_bvecs = IO_BVEC_COUNT(iosize, dmc->block_size);
++ dmc->clean_dbvecs = kmalloc(sizeof(struct bio_vec) * nr_bvecs,
++ GFP_KERNEL);
++ if (dmc->clean_dbvecs == NULL) {
++ pr_err("cache_create: Failed to allocated memory.\n");
++ ret = -ENOMEM;
++ goto errout;
++ }
++ /* Allocate pages for each bio_vec */
++ ret = eio_alloc_wb_bvecs(dmc->clean_dbvecs, nr_bvecs, dmc->block_size);
++ if (ret)
++ goto errout;
++ EIO_ASSERT(dmc->clean_dbvecs != NULL);
++ dmc->dbvec_count = nr_bvecs;
++
++ /* Metadata page allocations are done in terms of pages only */
++ iosize = dmc->assoc * sizeof(struct flash_cacheblock);
++ nr_pages = IO_PAGE_COUNT(iosize);
++ dmc->clean_mdpages = kmalloc(sizeof(struct page *) * nr_pages,
++ GFP_KERNEL);
++ if (dmc->clean_mdpages == NULL) {
++ pr_err("cache_create: Failed to allocated memory.\n");
++ ret = -ENOMEM;
++ eio_free_wb_bvecs(dmc->clean_dbvecs, dmc->dbvec_count,
++ dmc->block_size);
++ goto errout;
++ }
++ ret = eio_alloc_wb_pages(dmc->clean_mdpages, nr_pages);
++ if (ret) {
++ eio_free_wb_bvecs(dmc->clean_dbvecs, dmc->dbvec_count,
++ dmc->block_size);
++ goto errout;
++ }
++ EIO_ASSERT(dmc->clean_mdpages != NULL);
++ dmc->mdpage_count = nr_pages;
++
++ /*
++ * For writeback cache:
++ * 1. Initialize the time based clean work queue
++ * 2. Initialize the dirty set lru
++ * 3. Initialize clean thread
++ */
++
++ /*
++ * Reset dmc->is_clean_aged_sets_sched.
++ * Time based clean will be enabled in eio_touch_set_lru()
++ * only when dmc->is_clean_aged_sets_sched is zero and
++ * dmc->sysctl_active.time_based_clean_interval > 0.
++ */
++
++ dmc->is_clean_aged_sets_sched = 0;
++ INIT_DELAYED_WORK(&dmc->clean_aged_sets_work, eio_clean_aged_sets);
++ dmc->dirty_set_lru = NULL;
++ ret =
++ lru_init(&dmc->dirty_set_lru,
++ (dmc->size >> dmc->consecutive_shift));
++ if (ret == 0) {
++ spin_lock_init(&dmc->dirty_set_lru_lock);
++ ret = eio_clean_thread_init(dmc);
++ }
++ EIO_ASSERT(dmc->mdupdate_q == NULL);
++ dmc->mdupdate_q = create_singlethread_workqueue("eio_mdupdate");
++ if (!dmc->mdupdate_q)
++ ret = -ENOMEM;
++
++ if (ret < 0) {
++ pr_err("cache_create: Failed to initialize dirty lru set or" \
++ "clean/mdupdate thread for wb cache.\n");
++ if (dmc->dirty_set_lru) {
++ lru_uninit(dmc->dirty_set_lru);
++ dmc->dirty_set_lru = NULL;
++ }
++
++ eio_free_wb_pages(dmc->clean_mdpages, dmc->mdpage_count);
++ eio_free_wb_bvecs(dmc->clean_dbvecs, dmc->dbvec_count,
++ dmc->block_size);
++ goto errout;
++ }
++
++ goto out;
++
++errout:
++ if (dmc->clean_mdpages) {
++ kfree(dmc->clean_mdpages);
++ dmc->clean_mdpages = NULL;
++ dmc->mdpage_count = 0;
++ }
++ if (dmc->clean_dbvecs) {
++ kfree(dmc->clean_dbvecs);
++ dmc->clean_dbvecs = NULL;
++ dmc->dbvec_count = 0;
++ }
++
++out:
++ return ret;
++}
++
++void eio_free_wb_resources(struct cache_c *dmc)
++{
++
++ if (dmc->mdupdate_q) {
++ flush_workqueue(dmc->mdupdate_q);
++ destroy_workqueue(dmc->mdupdate_q);
++ dmc->mdupdate_q = NULL;
++ }
++ if (dmc->dirty_set_lru) {
++ lru_uninit(dmc->dirty_set_lru);
++ dmc->dirty_set_lru = NULL;
++ }
++ if (dmc->clean_mdpages) {
++ eio_free_wb_pages(dmc->clean_mdpages, dmc->mdpage_count);
++ kfree(dmc->clean_mdpages);
++ dmc->clean_mdpages = NULL;
++ }
++ if (dmc->clean_dbvecs) {
++ eio_free_wb_bvecs(dmc->clean_dbvecs, dmc->dbvec_count,
++ dmc->block_size);
++ kfree(dmc->clean_dbvecs);
++ dmc->clean_dbvecs = NULL;
++ }
++
++ dmc->dbvec_count = dmc->mdpage_count = 0;
++ return;
++}
++
++static int
++eio_notify_reboot(struct notifier_block *this, unsigned long code, void *x)
++{
++ struct cache_c *dmc;
++
++ if (eio_reboot_notified == EIO_REBOOT_HANDLING_DONE)
++ return NOTIFY_DONE;
++
++ (void)wait_on_bit_lock((void *)&eio_control->synch_flags,
++ EIO_HANDLE_REBOOT, eio_wait_schedule,
++ TASK_UNINTERRUPTIBLE);
++ if (eio_reboot_notified == EIO_REBOOT_HANDLING_DONE) {
++ clear_bit(EIO_HANDLE_REBOOT, (void *)&eio_control->synch_flags);
++ smp_mb__after_clear_bit();
++ wake_up_bit((void *)&eio_control->synch_flags,
++ EIO_HANDLE_REBOOT);
++ return NOTIFY_DONE;
++ }
++ EIO_ASSERT(eio_reboot_notified == 0);
++ eio_reboot_notified = EIO_REBOOT_HANDLING_INPROG;
++
++ (void)wait_on_bit_lock((void *)&eio_control->synch_flags,
++ EIO_UPDATE_LIST, eio_wait_schedule,
++ TASK_UNINTERRUPTIBLE);
++ for (dmc = cache_list_head; dmc != NULL; dmc = dmc->next_cache) {
++ if (unlikely(CACHE_FAILED_IS_SET(dmc))
++ || unlikely(CACHE_DEGRADED_IS_SET(dmc))) {
++ pr_err
++ ("notify_reboot: Cannot sync in failed / degraded mode");
++ continue;
++ }
++ if (dmc->cold_boot && atomic64_read(&dmc->nr_dirty)
++ && !eio_force_warm_boot) {
++ pr_info
++ ("Cold boot set for cache %s: Draining dirty blocks: %lld",
++ dmc->cache_name, (long long)atomic64_read(&dmc->nr_dirty));
++ eio_clean_for_reboot(dmc);
++ }
++ eio_md_store(dmc);
++ }
++ clear_bit(EIO_UPDATE_LIST, (void *)&eio_control->synch_flags);
++ smp_mb__after_clear_bit();
++ wake_up_bit((void *)&eio_control->synch_flags, EIO_UPDATE_LIST);
++
++ eio_reboot_notified = EIO_REBOOT_HANDLING_DONE;
++ clear_bit(EIO_HANDLE_REBOOT, (void *)&eio_control->synch_flags);
++ smp_mb__after_clear_bit();
++ wake_up_bit((void *)&eio_control->synch_flags, EIO_HANDLE_REBOOT);
++ return NOTIFY_DONE;
++}
++
++/*
++ * The SSD add/remove is handled using udev from the user space. The driver
++ * is notified from the user space via dmsetup message. Both device addition
++ * and removal events are handled in the driver by eio_handle_message().
++ *
++ * The device remove has a special case. From the time the device is removed,
++ * until the time the driver gets notified from the user space could be a few msec
++ * or a couple of seconds. During this time, any IO to the SSD fails. While this
++ * is handled gracefully, the logs can get filled with IO error messages.
++ *
++ * In order to cover that gap, we handle the device removal within the kernel
++ * using this function. Note that using the scsi notifier function in the kernel
++ * (vs. receiving the message from user space) minimizes the notification delay
++ * between the time the SSD is removed until the driver is notified. This cannot,
++ * however, make this delay zero. Therefore, there will be a small window during
++ * which eio_io_callback() may fail on CACHEWRITE action.
++ *
++ * We still need the user space (udev) method of handling for the following
++ * reasons:
++ * (i) This notifier is only for a scsi device.
++ * (ii) The add/remove feature in user space can also be used to dynamically
++ * turn the cache on and off.
++ *
++ * This notifier is used only when SSD is removed. The add event can
++ * be caught using the BUS_NOTIFY_ADD_DEVICE in action. However, we only
++ * get a scsi handle and do not have a reference to our device pointer.
++ */
++static int
++eio_notify_ssd_rm(struct notifier_block *nb, unsigned long action, void *data)
++{
++ struct device *dev = data;
++ struct cache_c *dmc;
++ const char *device_name;
++ size_t len;
++ unsigned long int flags = 0;
++ struct ssd_rm_list *ssd_list_ptr;
++ unsigned check_src = 0, check_ssd = 0;
++ enum dev_notifier notify = NOTIFY_INITIALIZER;
++
++ if (likely(action != BUS_NOTIFY_DEL_DEVICE))
++ return 0;
++
++ if (unlikely(dev == NULL)) {
++ pr_info("notify_cache_dev: device is NULL!");
++ return 0;
++ }
++
++ if (!scsi_is_sdev_device(dev))
++ return 0;
++ device_name = dev_name(dev);
++ if (device_name == NULL)
++ return 0;
++ len = strlen(device_name);
++
++ /* push to a list for future processing as we could be in an interrupt context */
++ for (dmc = cache_list_head; dmc != NULL; dmc = dmc->next_cache) {
++ notify = NOTIFY_INITIALIZER;
++ check_src = ('\0' == dmc->cache_srcdisk_name[0] ? 0 : 1);
++ check_ssd = ('\0' == dmc->cache_gendisk_name[0] ? 0 : 1);
++
++ if (check_src == 0 && check_ssd == 0)
++ continue;
++
++ /*Check if source dev name or ssd dev name is available or not. */
++ if (check_ssd
++ && 0 == strncmp(device_name, dmc->cache_gendisk_name,
++ len)) {
++ pr_info("SSD Removed for cache name %s",
++ dmc->cache_name);
++ notify = NOTIFY_SSD_REMOVED;
++ }
++
++ if (check_src
++ && 0 == strncmp(device_name, dmc->cache_srcdisk_name,
++ len)) {
++ pr_info("SRC Removed for cache name %s",
++ dmc->cache_name);
++ notify = NOTIFY_SRC_REMOVED;
++ }
++
++ if (notify == NOTIFY_INITIALIZER)
++ continue;
++
++ ssd_list_ptr = kmalloc(sizeof(struct ssd_rm_list), GFP_ATOMIC);
++ if (unlikely(ssd_list_ptr == NULL)) {
++ pr_err("Cannot allocate memory for ssd_rm_list");
++ return -ENOMEM;
++ }
++ ssd_list_ptr->dmc = dmc;
++ ssd_list_ptr->action = action;
++ ssd_list_ptr->devt = dev->devt;
++ ssd_list_ptr->note = notify;
++ spin_lock_irqsave(&ssd_rm_list_lock, flags);
++ list_add_tail(&ssd_list_ptr->list, &ssd_rm_list);
++ ssd_rm_list_not_empty = 1;
++ spin_unlock_irqrestore(&ssd_rm_list_lock, flags);
++ }
++
++ spin_lock_irqsave(&ssd_rm_list_lock, flags);
++ if (ssd_rm_list_not_empty) {
++ spin_unlock_irqrestore(&ssd_rm_list_lock, flags);
++ schedule_work(&_kcached_wq);
++ } else
++ spin_unlock_irqrestore(&ssd_rm_list_lock, flags);
++
++ return 0;
++}
++
++/*
++ * Initiate a cache target.
++ */
++static int __init eio_init(void)
++{
++ int r;
++ extern struct bus_type scsi_bus_type;
++
++ eio_ttc_init();
++ r = eio_create_misc_device();
++ if (r)
++ return r;
++
++ r = eio_jobs_init();
++ if (r) {
++ (void)eio_delete_misc_device();
++ return r;
++ }
++ atomic_set(&nr_cache_jobs, 0);
++ INIT_WORK(&_kcached_wq, eio_do_work);
++
++ eio_module_procfs_init();
++ eio_control = kmalloc(sizeof(*eio_control), GFP_KERNEL);
++ if (eio_control == NULL) {
++ pr_err("init: Cannot allocate memory for eio_control");
++ (void)eio_delete_misc_device();
++ return -ENOMEM;
++ }
++ eio_control->synch_flags = 0;
++
++ register_reboot_notifier(&eio_reboot_notifier);
++ r = bus_register_notifier(&scsi_bus_type, &eio_ssd_rm_notifier);
++ if (r) {
++ pr_err("init: bus register notifier failed %d", r);
++ (void)eio_delete_misc_device();
++ }
++ return r;
++}
++
++/*
++ * Destroy a cache target.
++ */
++static void eio_exit(void)
++{
++ int r;
++ extern struct bus_type scsi_bus_type;
++
++ unregister_reboot_notifier(&eio_reboot_notifier);
++ r = bus_unregister_notifier(&scsi_bus_type, &eio_ssd_rm_notifier);
++ if (r)
++ pr_err("exit: Bus unregister notifier failed %d", r);
++
++ eio_jobs_exit();
++ eio_module_procfs_exit();
++ if (eio_control) {
++ eio_control->synch_flags = 0;
++ kfree(eio_control);
++ eio_control = NULL;
++ }
++ (void)eio_delete_misc_device();
++}
++
++/*
++ * eio_get_device_size
++ */
++sector_t eio_get_device_size(struct eio_bdev *dev)
++{
++
++ return dev->bdev->bd_inode->i_size;
++}
++
++/*
++ * To get starting sector of the device
++ */
++sector_t eio_get_device_start_sect(struct eio_bdev *dev)
++{
++
++ if (dev == NULL || dev->bdev == NULL || dev->bdev->bd_part == NULL)
++ return 0;
++
++ return dev->bdev->bd_part->start_sect;
++}
++
++module_init(eio_init);
++module_exit(eio_exit);
++
++MODULE_DESCRIPTION(DM_NAME "STEC EnhanceIO target");
++MODULE_AUTHOR("STEC, Inc. based on code by Facebook");
++
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_fifo.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_fifo.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_fifo.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_fifo.c 2014-05-15 20:33:45.317922470 +0200
+@@ -0,0 +1,239 @@
++/*
++ * eio_fifo.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include "eio.h"
++/* Generic policy functions prototypes */
++int eio_fifo_init(struct cache_c *);
++void eio_fifo_exit(void);
++int eio_fifo_cache_sets_init(struct eio_policy *);
++int eio_fifo_cache_blk_init(struct eio_policy *);
++void eio_fifo_find_reclaim_dbn(struct eio_policy *, index_t, index_t *);
++int eio_fifo_clean_set(struct eio_policy *, index_t, int);
++
++/* Per policy instance initialization */
++struct eio_policy *eio_fifo_instance_init(void);
++
++/* Per cache set data structure */
++struct eio_fifo_cache_set {
++ index_t set_fifo_next;
++ index_t set_clean_next;
++};
++
++/*
++ * Context that captures the FIFO replacement policy
++ */
++static struct eio_policy_header eio_fifo_ops = {
++ .sph_name = CACHE_REPL_FIFO,
++ .sph_instance_init = eio_fifo_instance_init,
++};
++
++/*
++ * Initialize FIFO policy.
++ */
++int eio_fifo_init(struct cache_c *dmc)
++{
++ return 0;
++}
++
++/*
++ * Initialize FIFO data structure called from ctr.
++ */
++int eio_fifo_cache_sets_init(struct eio_policy *p_ops)
++{
++ int i;
++ sector_t order;
++ struct cache_c *dmc = p_ops->sp_dmc;
++ struct eio_fifo_cache_set *cache_sets;
++
++ pr_info("Initializing fifo cache sets\n");
++ order = (dmc->size >> dmc->consecutive_shift) *
++ sizeof(struct eio_fifo_cache_set);
++
++ dmc->sp_cache_set = vmalloc((size_t)order);
++ if (dmc->sp_cache_set == NULL)
++ return -ENOMEM;
++
++ cache_sets = (struct eio_fifo_cache_set *)dmc->sp_cache_set;
++
++ for (i = 0; i < (int)(dmc->size >> dmc->consecutive_shift); i++) {
++ cache_sets[i].set_fifo_next = i * dmc->assoc;
++ cache_sets[i].set_clean_next = i * dmc->assoc;
++ }
++
++ return 0;
++}
++
++/*
++ * The actual function that returns a victim block in index.
++ */
++void
++eio_fifo_find_reclaim_dbn(struct eio_policy *p_ops, index_t start_index,
++ index_t *index)
++{
++ index_t end_index;
++ int slots_searched = 0;
++ index_t i;
++ index_t set;
++ struct eio_fifo_cache_set *cache_sets;
++ struct cache_c *dmc = p_ops->sp_dmc;
++
++ set = start_index / dmc->assoc;
++ end_index = start_index + dmc->assoc;
++ cache_sets = (struct eio_fifo_cache_set *)dmc->sp_cache_set;
++
++ i = cache_sets[set].set_fifo_next;
++ while (slots_searched < (int)dmc->assoc) {
++ EIO_ASSERT(i >= start_index);
++ EIO_ASSERT(i < end_index);
++ if (EIO_CACHE_STATE_GET(dmc, i) == VALID) {
++ *index = i;
++ break;
++ }
++ slots_searched++;
++ i++;
++ if (i == end_index)
++ i = start_index;
++ }
++ i++;
++ if (i == end_index)
++ i = start_index;
++ cache_sets[set].set_fifo_next = i;
++}
++
++/*
++ * Go through the entire set and clean.
++ */
++int eio_fifo_clean_set(struct eio_policy *p_ops, index_t set, int to_clean)
++{
++ index_t i;
++ int scanned = 0, nr_writes = 0;
++ index_t start_index;
++ index_t end_index;
++ struct eio_fifo_cache_set *cache_sets;
++ struct cache_c *dmc;
++
++ dmc = p_ops->sp_dmc;
++ cache_sets = (struct eio_fifo_cache_set *)dmc->sp_cache_set;
++ start_index = set * dmc->assoc;
++ end_index = start_index + dmc->assoc;
++ i = cache_sets[set].set_clean_next;
++
++ while ((scanned < (int)dmc->assoc) && (nr_writes < to_clean)) {
++ if ((EIO_CACHE_STATE_GET(dmc, i) & (DIRTY | BLOCK_IO_INPROG)) ==
++ DIRTY) {
++ EIO_CACHE_STATE_ON(dmc, i, DISKWRITEINPROG);
++ nr_writes++;
++ }
++ scanned++;
++ i++;
++ if (i == end_index)
++ i = start_index;
++ }
++ cache_sets[set].set_clean_next = i;
++
++ return nr_writes;
++}
++
++/*
++ * FIFO is per set, so do nothing on a per block init.
++ */
++int eio_fifo_cache_blk_init(struct eio_policy *p_ops)
++{
++ return 0;
++}
++
++/*
++ * Allocate a new instance of eio_policy per dmc
++ */
++struct eio_policy *eio_fifo_instance_init(void)
++{
++ struct eio_policy *new_instance;
++
++ new_instance = vmalloc(sizeof(struct eio_policy));
++ if (new_instance == NULL) {
++ pr_err("ssdscache_fifo_instance_init: vmalloc failed");
++ return NULL;
++ }
++
++ /* Initialize the FIFO specific functions and variables */
++ new_instance->sp_name = CACHE_REPL_FIFO;
++ new_instance->sp_policy.lru = NULL;
++ new_instance->sp_repl_init = eio_fifo_init;
++ new_instance->sp_repl_exit = eio_fifo_exit;
++ new_instance->sp_repl_sets_init = eio_fifo_cache_sets_init;
++ new_instance->sp_repl_blk_init = eio_fifo_cache_blk_init;
++ new_instance->sp_find_reclaim_dbn = eio_fifo_find_reclaim_dbn;
++ new_instance->sp_clean_set = eio_fifo_clean_set;
++ new_instance->sp_dmc = NULL;
++
++ try_module_get(THIS_MODULE);
++
++ pr_info("eio_fifo_instance_init: created new instance of FIFO");
++
++ return new_instance;
++}
++
++/*
++ * Cleanup an instance of eio_policy (called from dtr).
++ */
++void eio_fifo_exit(void)
++{
++ module_put(THIS_MODULE);
++}
++
++static
++int __init fifo_register(void)
++{
++ int ret;
++
++ ret = eio_register_policy(&eio_fifo_ops);
++ if (ret != 0)
++ pr_info("eio_fifo already registered");
++
++ return ret;
++}
++
++static
++void __exit fifo_unregister(void)
++{
++ int ret;
++
++ ret = eio_unregister_policy(&eio_fifo_ops);
++ if (ret != 0)
++ pr_err("eio_fifo unregister failed");
++}
++
++module_init(fifo_register);
++module_exit(fifo_unregister);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("FIFO policy for EnhanceIO");
++MODULE_AUTHOR("STEC, Inc. based on code by Facebook");
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio.h linux-linaro-stable-mx6/drivers/block/enhanceio/eio.h
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio.h 2014-05-15 20:33:45.317922470 +0200
+@@ -0,0 +1,1150 @@
++/*
++ * eio.h
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Added EnhanceIO-specific code.
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ * Common data structures and definitions between Windows and Linux.
++ * Amit Kale <akale@stec-inc.com>
++ * Restructured much of the io code to split bio within map function instead
++ * of letting dm do it.
++ * Amit Kale <akale@stec-inc.com>
++ * Harish Pujari <hpujari@stec-inc.com>
++ * Designed and implemented the writeback caching mode
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <asm/atomic.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/blkdev.h>
++#include <linux/bio.h>
++#include <linux/slab.h>
++#include <linux/hash.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/pagemap.h>
++#include <linux/random.h>
++#include <linux/hardirq.h>
++#include <linux/sysctl.h>
++#include <linux/version.h>
++#include <linux/reboot.h>
++#include <linux/delay.h>
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#include <linux/device-mapper.h>
++#include <linux/dm-kcopyd.h>
++#include <linux/sort.h> /* required for eio_subr.c */
++#include <linux/kthread.h>
++#include <linux/jiffies.h>
++#include <linux/vmalloc.h> /* for sysinfo (mem) variables */
++#include <linux/mm.h>
++#include <scsi/scsi_device.h> /* required for SSD failure handling */
++/* resolve conflict with scsi/scsi_device.h */
++#ifdef QUEUED
++#undef QUEUED
++#endif
++
++#if defined(__KERNEL__) && !defined(CONFIG_PROC_FS)
++#error "EnhanceIO requires CONFIG_PROC_FS"
++#endif /* __KERNEL__ && !CONFIG_PROC_FS */
++
++#ifndef EIO_INC_H
++#define EIO_INC_H
++
++/* Bit offsets for wait_on_bit_lock() */
++#define EIO_UPDATE_LIST 0
++#define EIO_HANDLE_REBOOT 1
++
++/*
++ * It is to carry out 64bit division
++ * on 32bit architecture.
++ */
++static inline uint64_t
++EIO_CALCULATE_PERCENTAGE(uint64_t x64, uint64_t y64)
++{
++ uint64_t result;
++ uint32_t h_y32 = y64 >> 32;
++
++ result = x64 * 100;
++
++ while (h_y32) {
++ h_y32 >>= 1;
++ y64 >>= 1;
++ result >>= 1;
++ }
++ do_div(result, y64);
++ return result;
++}
++
++
++static inline uint64_t
++EIO_DIV(uint64_t dividend_64, uint32_t divisor_32)
++{
++ uint64_t result;
++
++ result = dividend_64;
++ do_div(result, divisor_32);
++ return result;
++}
++
++
++static inline uint32_t
++EIO_REM(uint64_t dividend_64, uint32_t divisor_32)
++{
++ uint64_t temp;
++
++ temp = dividend_64;
++ return do_div(temp, divisor_32);
++}
++
++static inline sector_t
++eio_to_sector(uint64_t size_in_bytes)
++{
++ return size_in_bytes >> 9;
++}
++
++struct eio_control_s {
++ unsigned long synch_flags;
++};
++
++int eio_wait_schedule(void *unused);
++
++struct eio_event {
++ struct task_struct *process; /* handle of the sleeping process */
++};
++
++typedef long int index_t;
++
++extern int eio_reboot_notified;
++extern mempool_t *_io_pool;
++extern struct eio_control_s *eio_control;
++extern struct work_struct _kcached_wq;
++extern int eio_force_warm_boot;
++extern atomic_t nr_cache_jobs;
++extern mempool_t *_job_pool;
++
++/*
++ * This file has three sections as follows:
++ *
++ * Section 1: User space only
++ * Section 2: User space and kernel
++ * Section 3: Kernel only
++ *
++ * Each section may contain its own subsections.
++ */
++
++/*
++ * Begin Section 1: User space only.
++ */
++
++/*
++ * End Section 1: User space only.
++ */
++
++/*
++ * Begin Section 2: User space and kernel.
++ */
++
++/* States of a cache block */
++#define INVALID 0x0001
++#define VALID 0x0002 /* Valid */
++#define DISKREADINPROG 0x0004 /* Read from disk in progress */
++#define DISKWRITEINPROG 0x0008 /* Write to disk in progress */
++#define CACHEREADINPROG 0x0010 /* Read from cache in progress */
++#define CACHEWRITEINPROG 0x0020 /* Write to cache in progress */
++#define DIRTY 0x0040 /* Dirty, needs writeback to disk */
++#define QUEUED 0x0080 /* Other requests are queued for this block */
++
++#define BLOCK_IO_INPROG (DISKREADINPROG | DISKWRITEINPROG | \
++ CACHEREADINPROG | CACHEWRITEINPROG)
++#define DIRTY_INPROG (VALID | DIRTY | CACHEWRITEINPROG) /* block being dirtied */
++#define CLEAN_INPROG (VALID | DIRTY | DISKWRITEINPROG) /* ongoing clean */
++#define ALREADY_DIRTY (VALID | DIRTY) /* block which is dirty to begin with for an I/O */
++
++/*
++ * This is a special state used only in the following scenario as
++ * part of device (SSD) failure handling:
++ *
++ * ------| dev fail |------| dev resume |------------
++ * ...-<--- Tf --><- Td -><---- Tr ---><-- Tn ---...
++ * |---- Normal ----|-- Degraded -------|-- Normal ---|
++ *
++ * Tf: Time during device failure.
++ * Td: Time after failure when the cache is in degraded mode.
++ * Tr: Time when the SSD comes back online.
++ *
++ * When a failed SSD is added back again, it should be treated
++ * as a cold SSD.
++ *
++ * If Td is very small, then there can be IOs that were initiated
++ * before or during Tf, and did not finish until the end of Tr. From
++ * the IO's viewpoint, the SSD was there when the IO was initiated
++ * and it was there when the IO was finished. These IOs need special
++ * handling as described below.
++ *
++ * To add the SSD as a cold cache device, we initialize all blocks
++ * to INVALID, execept for the ones that had IOs in progress before
++ * or during Tf. We mark such blocks as both VALID and INVALID.
++ * These blocks will be marked INVALID when finished.
++ */
++#define NO_SSD_IO_INPROG (VALID | INVALID)
++
++/*
++ * On Flash (cache metadata) Structures
++ */
++#define CACHE_MD_STATE_DIRTY 0x55daddee
++#define CACHE_MD_STATE_CLEAN 0xacceded1
++#define CACHE_MD_STATE_FASTCLEAN 0xcafebabf
++#define CACHE_MD_STATE_UNSTABLE 0xdeaddeee
++
++/* Do we have a read cache or a read-write cache */
++#define CACHE_MODE_WB 1
++#define CACHE_MODE_RO 2
++#define CACHE_MODE_WT 3
++#define CACHE_MODE_FIRST CACHE_MODE_WB
++#define CACHE_MODE_LAST CACHE_MODE_WT
++#define CACHE_MODE_DEFAULT CACHE_MODE_WT
++
++#define DEV_PATHLEN 128
++#define EIO_SUPERBLOCK_SIZE 4096
++
++#define EIO_CLEAN_ABORT 0x00000000
++#define EIO_CLEAN_START 0x00000001
++#define EIO_CLEAN_KEEP 0x00000002
++
++/* EIO magic number */
++#define EIO_MAGIC 0xE10CAC6E
++#define EIO_BAD_MAGIC 0xBADCAC6E
++
++/* EIO version */
++#define EIO_SB_VERSION 3 /* kernel superblock version */
++#define EIO_SB_MAGIC_VERSION 3 /* version in which magic number was introduced */
++
++union eio_superblock {
++ struct superblock_fields {
++ __le64 size; /* Cache size */
++ __le32 block_size; /* Cache block size */
++ __le32 assoc; /* Cache associativity */
++ __le32 cache_sb_state; /* Clean shutdown ? */
++ char cache_devname[DEV_PATHLEN];
++ __le64 cache_devsize;
++ char disk_devname[DEV_PATHLEN];
++ __le64 disk_devsize;
++ __le32 cache_version;
++ char cache_name[DEV_PATHLEN];
++ __le32 mode;
++ __le32 repl_policy;
++ __le32 cache_flags;
++ __le32 magic;
++ __le32 cold_boot; /* cache to be started as cold after boot */
++ char ssd_uuid[DEV_PATHLEN];
++ __le64 cache_md_start_sect; /* cache metadata start (8K aligned) */
++ __le64 cache_data_start_sect; /* cache data start (8K aligned) */
++ __le32 dirty_high_threshold;
++ __le32 dirty_low_threshold;
++ __le32 dirty_set_high_threshold;
++ __le32 dirty_set_low_threshold;
++ __le32 time_based_clean_interval;
++ __le32 autoclean_threshold;
++ } sbf;
++ u_int8_t padding[EIO_SUPERBLOCK_SIZE];
++};
++
++/*
++ * For EnhanceIO, we move the superblock from sector 0 to 128
++ * and give it a full 4K. Also, in addition to the single
++ * "red-zone" buffer that separates metadata sectors from the
++ * data sectors, we allocate extra sectors so that we can
++ * align the data sectors on a 4K boundary.
++ *
++ * 64K 4K variable variable 8K variable variable
++ * +--------+--+--------+---------+---+--------+---------+
++ * | unused |SB| align1 |metadata | Z | align2 | data... |
++ * +--------+--+--------+---------+---+--------+---------+
++ * <------------- dmc->md_sectors ------------>
++ */
++#define EIO_UNUSED_SECTORS 128
++#define EIO_SUPERBLOCK_SECTORS 8
++#define EIO_REDZONE_SECTORS 16
++#define EIO_START 0
++
++#define EIO_ALIGN1_SECTORS(index) ((index % 16) ? (24 - (index % 16)) : 8)
++#define EIO_ALIGN2_SECTORS(index) ((index % 16) ? (16 - (index % 16)) : 0)
++#define EIO_SUPERBLOCK_START (EIO_START + EIO_UNUSED_SECTORS)
++#define EIO_METADATA_START(hd_start_sect) (EIO_SUPERBLOCK_START + \
++ EIO_SUPERBLOCK_SECTORS + \
++ EIO_ALIGN1_SECTORS(hd_start_sect))
++
++#define EIO_EXTRA_SECTORS(start_sect, md_sects) (EIO_METADATA_START(start_sect) + \
++ EIO_REDZONE_SECTORS + \
++ EIO_ALIGN2_SECTORS(md_sects))
++
++/*
++ * We do metadata updates only when a block trasitions from DIRTY -> CLEAN
++ * or from CLEAN -> DIRTY. Consequently, on an unclean shutdown, we only
++ * pick up blocks that are marked (DIRTY | CLEAN), we clean these and stick
++ * them in the cache.
++ * On a clean shutdown, we will sync the state for every block, and we will
++ * load every block back into cache on a restart.
++ */
++struct flash_cacheblock {
++ __le64 dbn; /* Sector number of the cached block */
++ __le64 cache_state;
++};
++
++/* blksize in terms of no. of sectors */
++#define BLKSIZE_2K 4
++#define BLKSIZE_4K 8
++#define BLKSIZE_8K 16
++
++/*
++ * Give me number of pages to allocated for the
++ * iosize x specified in terms of bytes.
++ */
++#define IO_PAGE_COUNT(x) (((x) + (PAGE_SIZE - 1)) / PAGE_SIZE)
++
++/*
++ * Macro that calculates number of biovecs to be
++ * allocated depending on the iosize and cache
++ * block size.
++ */
++#define IO_BVEC_COUNT(x, blksize) ({ \
++ int count = IO_PAGE_COUNT(x); \
++ switch ((blksize)) { \
++ case BLKSIZE_2K: \
++ count = count * 2; \
++ break; \
++ case BLKSIZE_4K: \
++ case BLKSIZE_8K: \
++ break; \
++ } \
++ count; \
++ })
++
++#define MD_MAX_NR_PAGES 16
++#define MD_BLOCKS_PER_PAGE ((PAGE_SIZE) / sizeof(struct flash_cacheblock))
++#define INDEX_TO_MD_PAGE(INDEX) ((INDEX) / MD_BLOCKS_PER_PAGE)
++#define INDEX_TO_MD_PAGE_OFFSET(INDEX) ((INDEX) % MD_BLOCKS_PER_PAGE)
++
++#define MD_BLOCKS_PER_SECTOR (512 / (sizeof(struct flash_cacheblock)))
++#define INDEX_TO_MD_SECTOR(INDEX) (EIO_DIV((INDEX), MD_BLOCKS_PER_SECTOR))
++#define INDEX_TO_MD_SECTOR_OFFSET(INDEX) (EIO_REM((INDEX), MD_BLOCKS_PER_SECTOR))
++#define MD_BLOCKS_PER_CBLOCK(dmc) (MD_BLOCKS_PER_SECTOR * (dmc)->block_size)
++
++#define METADATA_IO_BLOCKSIZE (256 * 1024)
++#define METADATA_IO_BLOCKSIZE_SECT (METADATA_IO_BLOCKSIZE / 512)
++#define SECTORS_PER_PAGE ((PAGE_SIZE) / 512)
++
++/*
++ * Cache persistence.
++ */
++#define CACHE_RELOAD 1
++#define CACHE_CREATE 2
++#define CACHE_FORCECREATE 3
++
++/*
++ * Cache replacement policy.
++ */
++#define CACHE_REPL_FIFO 1
++#define CACHE_REPL_LRU 2
++#define CACHE_REPL_RANDOM 3
++#define CACHE_REPL_FIRST CACHE_REPL_FIFO
++#define CACHE_REPL_LAST CACHE_REPL_RANDOM
++#define CACHE_REPL_DEFAULT CACHE_REPL_FIFO
++
++struct eio_policy_and_name {
++ u8 p;
++ char *n;
++};
++
++
++static const struct eio_policy_and_name eio_policy_names[] = {
++ { CACHE_REPL_FIFO, "fifo" },
++ { CACHE_REPL_LRU, "lru" },
++ { CACHE_REPL_RANDOM, "rand" },
++};
++
++
++/*
++ * Default cache parameters.
++ */
++#define DEFAULT_CACHE_ASSOC 512
++#define DEFAULT_CACHE_BLKSIZE 8 /* 4 KB */
++
++/*
++ * Valid commands that can be written to "control".
++ * NOTE: Update CACHE_CONTROL_FLAG_MAX value whenever a new control flag is added
++ */
++#define CACHE_CONTROL_FLAG_MAX 7
++#define CACHE_VERBOSE_OFF 0
++#define CACHE_VERBOSE_ON 1
++#define CACHE_WRITEBACK_ON 2 /* register write back variables */
++#define CACHE_WRITEBACK_OFF 3
++#define CACHE_INVALIDATE_ON 4 /* register invalidate variables */
++#define CACHE_INVALIDATE_OFF 5
++#define CACHE_FAST_REMOVE_ON 6 /* do not write MD when destroying cache */
++#define CACHE_FAST_REMOVE_OFF 7
++
++/*
++ * Bit definitions in "cache_flags". These are exported in Linux as
++ * hex in the "flags" output line of /proc/enhanceio/<cache_name>/config.
++ */
++
++#define CACHE_FLAGS_VERBOSE (1 << 0)
++#define CACHE_FLAGS_INVALIDATE (1 << 1)
++#define CACHE_FLAGS_FAST_REMOVE (1 << 2)
++#define CACHE_FLAGS_DEGRADED (1 << 3)
++#define CACHE_FLAGS_SSD_ADD_INPROG (1 << 4)
++#define CACHE_FLAGS_MD8 (1 << 5) /* using 8-byte metadata (instead of 4-byte md) */
++#define CACHE_FLAGS_FAILED (1 << 6)
++#define CACHE_FLAGS_STALE (1 << 7)
++#define CACHE_FLAGS_SHUTDOWN_INPROG (1 << 8)
++#define CACHE_FLAGS_MOD_INPROG (1 << 9) /* cache modification such as edit/delete in progress */
++#define CACHE_FLAGS_DELETED (1 << 10)
++#define CACHE_FLAGS_INCORE_ONLY (CACHE_FLAGS_DEGRADED | \
++ CACHE_FLAGS_SSD_ADD_INPROG | \
++ CACHE_FLAGS_FAILED | \
++ CACHE_FLAGS_SHUTDOWN_INPROG | \
++ CACHE_FLAGS_MOD_INPROG | \
++ CACHE_FLAGS_STALE | \
++ CACHE_FLAGS_DELETED) /* need a proper definition */
++
++/* flags that govern cold/warm enable after reboot */
++#define BOOT_FLAG_COLD_ENABLE (1 << 0) /* enable the cache as cold */
++#define BOOT_FLAG_FORCE_WARM (1 << 1) /* override the cold enable flag */
++
++enum dev_notifier {
++ NOTIFY_INITIALIZER,
++ NOTIFY_SSD_ADD,
++ NOTIFY_SSD_REMOVED,
++ NOTIFY_SRC_REMOVED
++};
++
++/*
++ * End Section 2: User space and kernel.
++ */
++
++/*
++ * Begin Section 3: Kernel only.
++ */
++#if defined(__KERNEL__)
++
++/*
++ * Subsection 3.1: Definitions.
++ */
++
++#define EIO_SB_VERSION 3 /* kernel superblock version */
++
++/* kcached/pending job states */
++#define READCACHE 1
++#define WRITECACHE 2
++#define READDISK 3
++#define WRITEDISK 4
++#define READFILL 5 /* Read Cache Miss Fill */
++#define INVALIDATE 6
++
++/* Cache persistence */
++#define CACHE_RELOAD 1
++#define CACHE_CREATE 2
++#define CACHE_FORCECREATE 3
++
++/* Sysctl defined */
++#define MAX_CLEAN_IOS_SET 2
++#define MAX_CLEAN_IOS_TOTAL 4
++
++/*
++ * TBD
++ * Rethink on max, min, default values
++ */
++#define DIRTY_HIGH_THRESH_DEF 30
++#define DIRTY_LOW_THRESH_DEF 10
++#define DIRTY_SET_HIGH_THRESH_DEF 100
++#define DIRTY_SET_LOW_THRESH_DEF 30
++
++#define CLEAN_FACTOR(sectors) ((sectors) >> 25) /* in 16 GB multiples */
++#define TIME_BASED_CLEAN_INTERVAL_DEF(dmc) (uint32_t)(CLEAN_FACTOR((dmc)->cache_size) ? \
++ CLEAN_FACTOR((dmc)->cache_size) : 1)
++#define TIME_BASED_CLEAN_INTERVAL_MAX 720 /* in minutes */
++
++#define AUTOCLEAN_THRESH_DEF 128 /* Number of I/Os which puts a hold on time based cleaning */
++#define AUTOCLEAN_THRESH_MAX 1024 /* Number of I/Os which puts a hold on time based cleaning */
++
++/* Inject a 5s delay between cleaning blocks and metadata */
++#define CLEAN_REMOVE_DELAY 5000
++
++/*
++ * Subsection 2: Data structures.
++ */
++
++typedef void (*eio_notify_fn)(int error, void *context);
++
++/*
++ * 4-byte metadata support.
++ */
++
++#define EIO_MAX_SECTOR (((u_int64_t)1) << 40)
++#ifdef __BIG_ENDIAN
++struct md4 {
++ u_int8_t cache_state;
++ char dbn_bytes[3];
++};
++#else /* Little Endian */
++struct md4 {
++ char dbn_bytes[3];
++ u_int8_t cache_state;
++};
++#endif
++
++struct cacheblock {
++ union {
++ u_int32_t u_i_md4;
++ struct md4 u_s_md4;
++ } md4_u;
++};
++
++#define EIO_MD4_DBN_BITS (32 - 8) /* 8 bits for state */
++#define EIO_MD4_DBN_MASK ((1 << EIO_MD4_DBN_BITS) - 1)
++#define EIO_MD4_INVALID (INVALID << EIO_MD4_DBN_BITS)
++
++/*
++ * 8-byte metadata support.
++ */
++#ifdef __BIG_ENDIAN
++struct md8 {
++ u_int8_t cache_state;
++ char dbn_bytes[7];
++};
++#else /* little endian*/
++struct md8 {
++ char dbn_bytes[7];
++ u_int8_t cache_state;
++};
++#endif
++struct cacheblock_md8 {
++ union {
++ u_int64_t u_i_md8;
++ struct md8 u_s_md8;
++ } md8_u;
++};
++
++#define EIO_MD8_DBN_BITS (64 - 8) /* 8 bits for state */
++#define EIO_MD8_DBN_MASK ((((u_int64_t)1) << EIO_MD8_DBN_BITS) - 1)
++#define EIO_MD8_INVALID (((u_int64_t)INVALID) << EIO_MD8_DBN_BITS)
++#define EIO_MD8(dmc) CACHE_MD8_IS_SET(dmc)
++
++/* Structure used for metadata update on-disk and in-core for writeback cache */
++struct mdupdate_request {
++ struct list_head list; /* to build mdrequest chain */
++ struct work_struct work; /* work structure */
++ struct cache_c *dmc; /* cache pointer */
++ index_t set; /* set index */
++ unsigned md_size; /* metadata size */
++ unsigned mdbvec_count; /* count of bvecs allocated. */
++ struct bio_vec *mdblk_bvecs; /* bvecs for updating md_blocks */
++ atomic_t holdcount; /* I/O hold count */
++ struct eio_bio *pending_mdlist; /* ebios pending for md update */
++ struct eio_bio *inprog_mdlist; /* ebios processed for md update */
++ int error; /* error during md update */
++ struct mdupdate_request *next; /* next mdreq in the mdreq list .TBD. Deprecate */
++};
++
++#define SETFLAG_CLEAN_INPROG 0x00000001 /* clean in progress on a set */
++#define SETFLAG_CLEAN_WHOLE 0x00000002 /* clean the set fully */
++
++/* Structure used for doing operations and storing cache set level info */
++struct cache_set {
++ struct list_head list;
++ u_int32_t nr_dirty; /* number of dirty blocks */
++ spinlock_t cs_lock; /* spin lock to protect struct fields */
++ struct rw_semaphore rw_lock; /* reader-writer lock used for clean */
++ unsigned int flags; /* misc cache set specific flags */
++ struct mdupdate_request *mdreq; /* metadata update request pointer */
++};
++
++struct eio_errors {
++ int disk_read_errors;
++ int disk_write_errors;
++ int ssd_read_errors;
++ int ssd_write_errors;
++ int memory_alloc_errors;
++ int no_cache_dev;
++ int no_source_dev;
++};
++
++/*
++ * Stats. Note that everything should be "atomic64_t" as
++ * code relies on it.
++ */
++#define SECTOR_STATS(statval, io_size) \
++ atomic64_add(eio_to_sector(io_size), &statval);
++
++struct eio_stats {
++ atomic64_t reads; /* Number of reads */
++ atomic64_t writes; /* Number of writes */
++ atomic64_t read_hits; /* Number of cache hits */
++ atomic64_t write_hits; /* Number of write hits (includes dirty write hits) */
++ atomic64_t dirty_write_hits; /* Number of "dirty" write hits */
++ atomic64_t cached_blocks; /* Number of cached blocks */
++ atomic64_t rd_replace; /* Number of read cache replacements. TBD modify def doc */
++ atomic64_t wr_replace; /* Number of write cache replacements. TBD modify def doc */
++ atomic64_t noroom; /* No room in set */
++ atomic64_t cleanings; /* blocks cleaned TBD modify def doc */
++ atomic64_t md_write_dirty; /* Metadata sector writes dirtying block */
++ atomic64_t md_write_clean; /* Metadata sector writes cleaning block */
++ atomic64_t md_ssd_writes; /* How many md ssd writes did we do ? */
++ atomic64_t uncached_reads;
++ atomic64_t uncached_writes;
++ atomic64_t uncached_map_size;
++ atomic64_t uncached_map_uncacheable;
++ atomic64_t disk_reads;
++ atomic64_t disk_writes;
++ atomic64_t ssd_reads;
++ atomic64_t ssd_writes;
++ atomic64_t ssd_readfills;
++ atomic64_t ssd_readfill_unplugs;
++ atomic64_t readdisk;
++ atomic64_t writedisk;
++ atomic64_t readcache;
++ atomic64_t readfill;
++ atomic64_t writecache;
++ atomic64_t wrtime_ms; /* total write time in ms */
++ atomic64_t rdtime_ms; /* total read time in ms */
++ atomic64_t readcount; /* total reads received so far */
++ atomic64_t writecount; /* total writes received so far */
++};
++
++#define PENDING_JOB_HASH_SIZE 32
++#define PENDING_JOB_HASH(index) ((index) % PENDING_JOB_HASH_SIZE)
++#define SIZE_HIST (128 + 1)
++#define EIO_COPY_PAGES 1024 /* Number of pages for I/O */
++#define MIN_JOBS 1024
++#define MIN_EIO_IO 4096
++#define MIN_DMC_BIO_PAIR 8192
++
++/* Structure representing a sequence of sets(first to last set index) */
++struct set_seq {
++ index_t first_set;
++ index_t last_set;
++ struct set_seq *next;
++};
++
++/* EIO system control variables(tunables) */
++/*
++ * Adding synchonization is not worth the benefits.
++ */
++struct eio_sysctl {
++ uint32_t error_inject;
++ int32_t fast_remove;
++ int32_t zerostats;
++ int32_t do_clean;
++ uint32_t dirty_high_threshold;
++ uint32_t dirty_low_threshold;
++ uint32_t dirty_set_high_threshold;
++ uint32_t dirty_set_low_threshold;
++ uint32_t time_based_clean_interval; /* time after which dirty sets should clean */
++ int32_t autoclean_threshold;
++ int32_t mem_limit_pct;
++ int32_t control;
++ u_int64_t invalidate;
++};
++
++/* forward declaration */
++struct lru_ls;
++
++/* Replacement for 'struct dm_dev' */
++struct eio_bdev {
++ struct block_device *bdev;
++ fmode_t mode;
++ char name[16];
++};
++
++/* Replacement for 'struct dm_io_region */
++struct eio_io_region {
++ struct block_device *bdev;
++ sector_t sector;
++ sector_t count; /* If zero the region is ignored */
++};
++
++/*
++ * Cache context
++ */
++struct cache_c {
++ struct list_head cachelist;
++ make_request_fn *origmfn;
++ char dev_info; /* partition or whole device */
++
++ sector_t dev_start_sect;
++ sector_t dev_end_sect;
++ int cache_rdonly; /* protected by ttc_write lock */
++ struct eio_bdev *disk_dev; /* Source device */
++ struct eio_bdev *cache_dev; /* Cache device */
++ struct cacheblock *cache; /* Hash table for cache blocks */
++ struct cache_set *cache_sets;
++ struct cache_c *next_cache;
++ struct kcached_job *readfill_queue;
++ struct work_struct readfill_wq;
++
++ struct list_head cleanq; /* queue of sets to awaiting clean */
++ struct eio_event clean_event; /* event to wait for, when cleanq is empty */
++ spinlock_t clean_sl; /* spinlock to protect cleanq etc */
++ void *clean_thread; /* OS specific thread object to handle cleanq */
++ int clean_thread_running; /* to indicate that clean thread is running */
++ atomic64_t clean_pendings; /* Number of sets pending to be cleaned */
++ struct bio_vec *clean_dbvecs; /* Data bvecs for clean set */
++ struct page **clean_mdpages; /* Metadata pages for clean set */
++ int dbvec_count;
++ int mdpage_count;
++ int clean_excess_dirty; /* Clean in progress to bring cache dirty blocks in limits */
++ atomic_t clean_index; /* set being cleaned, in case of force clean */
++
++ u_int64_t md_start_sect; /* Sector no. at which Metadata starts */
++ u_int64_t md_sectors; /* Numbers of metadata sectors, including header */
++ u_int64_t disk_size; /* Source size */
++ u_int64_t size; /* Cache size */
++ u_int32_t assoc; /* Cache associativity */
++ u_int32_t block_size; /* Cache block size */
++ u_int32_t block_shift; /* Cache block size in bits */
++ u_int32_t block_mask; /* Cache block mask */
++ u_int32_t consecutive_shift; /* Consecutive blocks size in bits */
++ u_int32_t persistence; /* Create | Force create | Reload */
++ u_int32_t mode; /* CACHE_MODE_{WB, RO, WT} */
++ u_int32_t cold_boot; /* Cache should be started as cold after boot */
++ u_int32_t bio_nr_pages; /* number of hardware sectors supported by SSD in terms of PAGE_SIZE */
++
++ spinlock_t cache_spin_lock;
++ long unsigned int cache_spin_lock_flags; /* See comments above spin_lock_irqsave_FLAGS */
++ atomic_t nr_jobs; /* Number of I/O jobs */
++
++ u_int32_t cache_flags;
++ u_int32_t sb_state; /* Superblock state */
++ u_int32_t sb_version; /* Superblock version */
++
++ int readfill_in_prog;
++ struct eio_stats eio_stats; /* Run time stats */
++ struct eio_errors eio_errors; /* Error stats */
++ int max_clean_ios_set; /* Max cleaning IOs per set */
++ int max_clean_ios_total; /* Total max cleaning IOs */
++ int clean_inprog;
++ atomic64_t nr_dirty;
++ atomic64_t nr_ios;
++ atomic64_t size_hist[SIZE_HIST];
++
++ void *sysctl_handle_common;
++ void *sysctl_handle_writeback;
++ void *sysctl_handle_invalidate;
++
++ struct eio_sysctl sysctl_pending; /* sysctl values pending to become active */
++ struct eio_sysctl sysctl_active; /* sysctl currently active */
++
++ char cache_devname[DEV_PATHLEN];
++ char disk_devname[DEV_PATHLEN];
++ char cache_name[DEV_PATHLEN];
++ char cache_gendisk_name[DEV_PATHLEN]; /* Used for SSD failure checks */
++ char cache_srcdisk_name[DEV_PATHLEN]; /* Used for SRC failure checks */
++ char ssd_uuid[DEV_PATHLEN];
++
++ struct cacheblock_md8 *cache_md8;
++ sector_t cache_size; /* Cache size passed to ctr(), used by dmsetup info */
++ sector_t cache_dev_start_sect; /* starting sector of cache device */
++ u_int64_t index_zero; /* index of cache block with starting sector 0 */
++ u_int32_t num_sets; /* number of cache sets */
++ u_int32_t num_sets_bits; /* number of bits to encode "num_sets" */
++ u_int64_t num_sets_mask; /* mask value for bits in "num_sets" */
++
++ struct eio_policy *policy_ops; /* Cache block Replacement policy */
++ u_int32_t req_policy; /* Policy requested by the user */
++ u_int32_t random; /* Use for random replacement policy */
++ void *sp_cache_blk; /* Per cache-block data structure */
++ void *sp_cache_set; /* Per cache-set data structure */
++ struct lru_ls *dirty_set_lru; /* lru for dirty sets : lru_list_t */
++ spinlock_t dirty_set_lru_lock; /* spinlock for dirty set lru */
++ struct delayed_work clean_aged_sets_work; /* work item for clean_aged_sets */
++ int is_clean_aged_sets_sched; /* to know whether clean aged sets is scheduled */
++ struct workqueue_struct *mdupdate_q; /* Workqueue to handle md updates */
++ struct workqueue_struct *callback_q; /* Workqueue to handle io callbacks */
++};
++
++#define EIO_CACHE_IOSIZE 0
++
++#define EIO_ROUND_SECTOR(dmc, sector) (sector & (~(unsigned long)(dmc->block_size - 1)))
++#define EIO_ROUND_SET_SECTOR(dmc, sector) (sector & (~(unsigned long)((dmc->block_size * dmc->assoc) - 1)))
++
++/*
++ * The bit definitions are exported to the user space and are in the very beginning of the file.
++ */
++#define CACHE_VERBOSE_IS_SET(dmc) (((dmc)->cache_flags & CACHE_FLAGS_VERBOSE) ? 1 : 0)
++#define CACHE_INVALIDATE_IS_SET(dmc) (((dmc)->cache_flags & CACHE_FLAGS_INVALIDATE) ? 1 : 0)
++#define CACHE_FAST_REMOVE_IS_SET(dmc) (((dmc)->cache_flags & CACHE_FLAGS_FAST_REMOVE) ? 1 : 0)
++#define CACHE_DEGRADED_IS_SET(dmc) (((dmc)->cache_flags & CACHE_FLAGS_DEGRADED) ? 1 : 0)
++#define CACHE_SSD_ADD_INPROG_IS_SET(dmc) (((dmc)->cache_flags & CACHE_FLAGS_SSD_ADD_INPROG) ? 1 : 0)
++#define CACHE_MD8_IS_SET(dmc) (((dmc)->cache_flags & CACHE_FLAGS_MD8) ? 1 : 0)
++#define CACHE_FAILED_IS_SET(dmc) (((dmc)->cache_flags & CACHE_FLAGS_FAILED) ? 1 : 0)
++#define CACHE_STALE_IS_SET(dmc) (((dmc)->cache_flags & CACHE_FLAGS_STALE) ? 1 : 0)
++
++/* Device failure handling. */
++#define CACHE_SRC_IS_ABSENT(dmc) (((dmc)->eio_errors.no_source_dev == 1) ? 1 : 0)
++
++#define AUTOCLEAN_THRESHOLD_CROSSED(dmc) \
++ ((atomic64_read(&(dmc)->nr_ios) > (int64_t)(dmc)->sysctl_active.autoclean_threshold) || \
++ ((dmc)->sysctl_active.autoclean_threshold == 0))
++
++#define DIRTY_CACHE_THRESHOLD_CROSSED(dmc) \
++ ((atomic64_read(&(dmc)->nr_dirty) - atomic64_read(&(dmc)->clean_pendings)) >= \
++ (int64_t)((dmc)->sysctl_active.dirty_high_threshold * EIO_DIV((dmc)->size, 100)) && \
++ ((dmc)->sysctl_active.dirty_high_threshold > (dmc)->sysctl_active.dirty_low_threshold))
++
++#define DIRTY_SET_THRESHOLD_CROSSED(dmc, set) \
++ (((dmc)->cache_sets[(set)].nr_dirty >= (u_int32_t)((dmc)->sysctl_active.dirty_set_high_threshold * (dmc)->assoc) / 100) && \
++ ((dmc)->sysctl_active.dirty_set_high_threshold > (dmc)->sysctl_active.dirty_set_low_threshold))
++
++/*
++ * Do not reverse the order of disk and cache! Code
++ * relies on this ordering. (Eg: eio_dm_io_async_bvec()).
++ */
++struct job_io_regions {
++ struct eio_io_region disk; /* has to be the first member */
++ struct eio_io_region cache; /* has to be the second member */
++};
++
++#define EB_MAIN_IO 1
++#define EB_SUBORDINATE_IO 2
++#define EB_INVAL 4
++#define GET_BIO_FLAGS(ebio) ((ebio)->eb_bc->bc_bio->bi_rw)
++#define VERIFY_BIO_FLAGS(ebio) EIO_ASSERT((ebio) && (ebio)->eb_bc && (ebio)->eb_bc->bc_bio)
++
++#define SET_BARRIER_FLAGS(rw_flags) (rw_flags |= (REQ_WRITE | REQ_FLUSH))
++
++struct eio_bio {
++ int eb_iotype;
++ struct bio_container *eb_bc;
++ unsigned eb_cacheset;
++ sector_t eb_sector; /*sector number*/
++ unsigned eb_size; /*size in bytes*/
++ struct bio_vec *eb_bv; /*bvec pointer*/
++ unsigned eb_nbvec; /*number of bio_vecs*/
++ int eb_dir; /* io direction*/
++ struct eio_bio *eb_next; /*used for splitting reads*/
++ index_t eb_index; /*for read bios*/
++ atomic_t eb_holdcount; /* ebio hold count, currently used only for dirty block I/O */
++ struct bio_vec eb_rbv[0];
++};
++
++enum eio_io_dir {
++ EIO_IO_INVALID_DIR = 0,
++ CACHED_WRITE,
++ CACHED_READ,
++ UNCACHED_WRITE,
++ UNCACHED_READ,
++ UNCACHED_READ_AND_READFILL
++};
++
++/* ASK
++ * Container for all eio_bio corresponding to a given bio
++ */
++struct bio_container {
++ spinlock_t bc_lock; /* lock protecting the bc fields */
++ atomic_t bc_holdcount; /* number of ebios referencing bc */
++ struct bio *bc_bio; /* bio for the bc */
++ struct cache_c *bc_dmc; /* cache structure */
++ struct eio_bio *bc_mdlist; /* ebios waiting for md update */
++ int bc_mdwait; /* count of ebios that will do md update */
++ struct mdupdate_request *mdreqs; /* mdrequest structures required for md update */
++ struct set_seq *bc_setspan; /* sets spanned by the bc(used only for wb) */
++ struct set_seq bc_singlesspan; /* used(by wb) if bc spans a single set sequence */
++ enum eio_io_dir bc_dir; /* bc I/O direction */
++ int bc_error; /* error encountered during processing bc */
++ unsigned long bc_iotime; /* maintains i/o time in jiffies */
++ struct bio_container *bc_next; /* next bc in the chain */
++};
++
++/* structure used as callback context during synchronous I/O */
++struct sync_io_context {
++ struct rw_semaphore sio_lock;
++ unsigned long sio_error;
++};
++
++struct kcached_job {
++ struct list_head list;
++ struct work_struct work;
++ struct cache_c *dmc;
++ struct eio_bio *ebio;
++ struct job_io_regions job_io_regions;
++ index_t index;
++ int action;
++ int error;
++ struct flash_cacheblock *md_sector;
++ struct bio_vec md_io_bvec;
++ struct kcached_job *next;
++};
++
++struct ssd_rm_list {
++ struct cache_c *dmc;
++ int action;
++ dev_t devt;
++ enum dev_notifier note;
++ struct list_head list;
++};
++
++struct dbn_index_pair {
++ sector_t dbn;
++ index_t index;
++};
++
++/*
++ * Subsection 3: Function prototypes and definitions.
++ */
++
++struct kcached_job *eio_alloc_cache_job(void);
++void eio_free_cache_job(struct kcached_job *job);
++struct kcached_job *pop(struct list_head *jobs);
++void push(struct list_head *jobs, struct kcached_job *job);
++void do_work(struct work_struct *unused);
++void update_job_cacheregion(struct kcached_job *job, struct cache_c *dmc,
++ struct eio_bio *bio);
++void push_io(struct kcached_job *job);
++void push_md_io(struct kcached_job *job);
++void push_md_complete(struct kcached_job *job);
++void push_uncached_io_complete(struct kcached_job *job);
++int eio_io_empty(void);
++int eio_md_io_empty(void);
++int eio_md_complete_empty(void);
++void eio_md_write_done(struct kcached_job *job);
++void eio_ssderror_diskread(struct kcached_job *job);
++void eio_md_write(struct kcached_job *job);
++void eio_md_write_kickoff(struct kcached_job *job);
++void eio_do_readfill(struct work_struct *work);
++void eio_comply_dirty_thresholds(struct cache_c *dmc, index_t set);
++void eio_clean_all(struct cache_c *dmc);
++void eio_clean_for_reboot(struct cache_c *dmc);
++void eio_clean_aged_sets(struct work_struct *work);
++void eio_comply_dirty_thresholds(struct cache_c *dmc, index_t set);
++#ifndef SSDCACHE
++void eio_reclaim_lru_movetail(struct cache_c *dmc, index_t index,
++ struct eio_policy *);
++#endif /* !SSDCACHE */
++int eio_io_sync_vm(struct cache_c *dmc, struct eio_io_region *where, int rw,
++ struct bio_vec *bvec, int nbvec);
++int eio_io_sync_pages(struct cache_c *dmc, struct eio_io_region *where, int rw,
++ struct page **pages, int num_bvecs);
++void eio_update_sync_progress(struct cache_c *dmc);
++void eio_plug_cache_device(struct cache_c *dmc);
++void eio_unplug_cache_device(struct cache_c *dmc);
++void eio_plug_disk_device(struct cache_c *dmc);
++void eio_unplug_disk_device(struct cache_c *dmc);
++int dm_io_async_bvec(unsigned int num_regions, struct eio_io_region *where,
++ int rw, struct bio_vec *bvec, eio_notify_fn fn,
++ void *context);
++void eio_put_cache_device(struct cache_c *dmc);
++void eio_suspend_caching(struct cache_c *dmc, enum dev_notifier note);
++void eio_resume_caching(struct cache_c *dmc, char *dev);
++int eio_ctr_ssd_add(struct cache_c *dmc, char *dev);
++
++/* procfs */
++void eio_module_procfs_init(void);
++void eio_module_procfs_exit(void);
++void eio_procfs_ctr(struct cache_c *dmc);
++void eio_procfs_dtr(struct cache_c *dmc);
++
++int eio_sb_store(struct cache_c *dmc);
++
++int eio_md_destroy(struct dm_target *tip, char *namep, char *srcp, char *cachep,
++ int force);
++
++/* eio_conf.c */
++extern int eio_ctr(struct dm_target *ti, unsigned int argc, char **argv);
++extern void eio_dtr(struct dm_target *ti);
++extern int eio_md_destroy(struct dm_target *tip, char *namep, char *srcp,
++ char *cachep, int force);
++extern int eio_ctr_ssd_add(struct cache_c *dmc, char *dev);
++
++/* thread related functions */
++void *eio_create_thread(int (*func)(void *), void *context, char *name);
++void eio_thread_exit(long exit_code);
++void eio_wait_thread_exit(void *thrdptr, int *notifier);
++
++/* eio_main.c */
++extern int eio_map(struct cache_c *, struct request_queue *, struct bio *);
++extern void eio_md_write_done(struct kcached_job *job);
++extern void eio_ssderror_diskread(struct kcached_job *job);
++extern void eio_md_write(struct kcached_job *job);
++extern void eio_md_write_kickoff(struct kcached_job *job);
++extern void eio_do_readfill(struct work_struct *work);
++extern void eio_check_dirty_thresholds(struct cache_c *dmc, index_t set);
++extern void eio_clean_all(struct cache_c *dmc);
++extern int eio_clean_thread_proc(void *context);
++extern void eio_touch_set_lru(struct cache_c *dmc, index_t set);
++extern void eio_inval_range(struct cache_c *dmc, sector_t iosector,
++ unsigned iosize);
++extern int eio_invalidate_sanity_check(struct cache_c *dmc, u_int64_t iosector,
++ u_int64_t *iosize);
++/*
++ * Invalidates all cached blocks without waiting for them to complete
++ * Should be called with incoming IO suspended
++ */
++extern int eio_invalidate_cache(struct cache_c *dmc);
++
++/* eio_mem.c */
++extern int eio_mem_init(struct cache_c *dmc);
++extern u_int32_t eio_hash_block(struct cache_c *dmc, sector_t dbn);
++extern unsigned int eio_shrink_dbn(struct cache_c *dmc, sector_t dbn);
++extern sector_t eio_expand_dbn(struct cache_c *dmc, u_int64_t index);
++extern void eio_invalidate_md(struct cache_c *dmc, u_int64_t index);
++extern void eio_md4_dbn_set(struct cache_c *dmc, u_int64_t index,
++ u_int32_t dbn_24);
++extern void eio_md8_dbn_set(struct cache_c *dmc, u_int64_t index, sector_t dbn);
++
++/* eio_procfs.c */
++extern void eio_module_procfs_init(void);
++extern void eio_module_procfs_exit(void);
++extern void eio_procfs_ctr(struct cache_c *dmc);
++extern void eio_procfs_dtr(struct cache_c *dmc);
++extern int eio_version_query(size_t buf_sz, char *bufp);
++
++/* eio_subr.c */
++extern void eio_free_cache_job(struct kcached_job *job);
++extern void eio_do_work(struct work_struct *unused);
++extern struct kcached_job *eio_new_job(struct cache_c *dmc, struct eio_bio *bio,
++ index_t index);
++extern void eio_push_ssdread_failures(struct kcached_job *job);
++extern void eio_push_md_io(struct kcached_job *job);
++extern void eio_push_md_complete(struct kcached_job *job);
++extern void eio_push_uncached_io_complete(struct kcached_job *job);
++extern int eio_io_empty(void);
++extern int eio_io_sync_vm(struct cache_c *dmc, struct eio_io_region *where,
++ int rw, struct bio_vec *bvec, int nbvec);
++extern void eio_unplug_cache_device(struct cache_c *dmc);
++extern void eio_put_cache_device(struct cache_c *dmc);
++extern void eio_suspend_caching(struct cache_c *dmc, enum dev_notifier note);
++extern void eio_resume_caching(struct cache_c *dmc, char *dev);
++
++static inline void
++EIO_DBN_SET(struct cache_c *dmc, u_int64_t index, sector_t dbn)
++{
++ if (EIO_MD8(dmc))
++ eio_md8_dbn_set(dmc, index, dbn);
++ else
++ eio_md4_dbn_set(dmc, index, eio_shrink_dbn(dmc, dbn));
++ if (dbn == 0)
++ dmc->index_zero = index;
++}
++
++static inline u_int64_t EIO_DBN_GET(struct cache_c *dmc, u_int64_t index)
++{
++ if (EIO_MD8(dmc))
++ return dmc->cache_md8[index].md8_u.u_i_md8 & EIO_MD8_DBN_MASK;
++
++ return eio_expand_dbn(dmc, index);
++}
++
++static inline void
++EIO_CACHE_STATE_SET(struct cache_c *dmc, u_int64_t index, u_int8_t cache_state)
++{
++ if (EIO_MD8(dmc))
++ dmc->cache_md8[index].md8_u.u_s_md8.cache_state = cache_state;
++ else
++ dmc->cache[index].md4_u.u_s_md4.cache_state = cache_state;
++}
++
++static inline u_int8_t
++EIO_CACHE_STATE_GET(struct cache_c *dmc, u_int64_t index)
++{
++ u_int8_t cache_state;
++
++ if (EIO_MD8(dmc))
++ cache_state = dmc->cache_md8[index].md8_u.u_s_md8.cache_state;
++ else
++ cache_state = dmc->cache[index].md4_u.u_s_md4.cache_state;
++ return cache_state;
++}
++
++static inline void
++EIO_CACHE_STATE_OFF(struct cache_c *dmc, index_t index, u_int8_t bitmask)
++{
++ u_int8_t cache_state = EIO_CACHE_STATE_GET(dmc, index);
++
++ cache_state &= ~bitmask;
++ EIO_CACHE_STATE_SET(dmc, index, cache_state);
++}
++
++static inline void
++EIO_CACHE_STATE_ON(struct cache_c *dmc, index_t index, u_int8_t bitmask)
++{
++ u_int8_t cache_state = EIO_CACHE_STATE_GET(dmc, index);
++
++ cache_state |= bitmask;
++ EIO_CACHE_STATE_SET(dmc, index, cache_state);
++}
++
++void eio_set_warm_boot(void);
++#endif /* defined(__KERNEL__) */
++
++#include "eio_ioctl.h"
++
++/* resolve conflict with scsi/scsi_device.h */
++#ifdef __KERNEL__
++
++#ifdef EIO_ASSERT
++#undef EIO_ASSERT
++#endif
++/*Always compiled in*/
++#define EIO_ASSERT(x) BUG_ON(unlikely(!(x)))
++
++extern sector_t eio_get_device_size(struct eio_bdev *);
++extern sector_t eio_get_device_start_sect(struct eio_bdev *);
++#endif /* __KERNEL__ */
++
++#define EIO_INIT_EVENT(ev) ((ev)->process = NULL)
++
++/*Assumes that the macro gets called under the same spinlock as in wait event*/
++#define EIO_SET_EVENT_AND_UNLOCK(ev, sl, flags) \
++ do { \
++ struct task_struct *p = NULL; \
++ if ((ev)->process) { \
++ (p) = (ev)->process; \
++ (ev)->process = NULL; \
++ } \
++ spin_unlock_irqrestore((sl), flags); \
++ if (p) { \
++ (void)wake_up_process(p); \
++ } \
++ } while (0)
++
++/*Assumes that the spin lock sl is taken while calling this macro*/
++#define EIO_WAIT_EVENT(ev, sl, flags) \
++ do { \
++ (ev)->process = current; \
++ set_current_state(TASK_INTERRUPTIBLE); \
++ spin_unlock_irqrestore((sl), flags); \
++ (void)schedule_timeout(10 * HZ); \
++ spin_lock_irqsave((sl), flags); \
++ (ev)->process = NULL; \
++ } while (0)
++
++#define EIO_CLEAR_EVENT(ev) ((ev)->process = NULL)
++
++#include "eio_setlru.h"
++#include "eio_policy.h"
++#define EIO_CACHE(dmc) (EIO_MD8(dmc) ? (void *)dmc->cache_md8 : (void *)dmc->cache)
++
++#endif /* !EIO_INC_H */
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_ioctl.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_ioctl.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_ioctl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_ioctl.c 2014-05-15 20:33:45.317922470 +0200
+@@ -0,0 +1,157 @@
++/*
++ * eio_ioctl.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "eio.h"
++#include "eio_ttc.h"
++
++long eio_ioctl(struct file *filp, unsigned cmd, unsigned long arg)
++{
++ int error = 0;
++ struct cache_rec_short *cache;
++ uint64_t ncaches;
++ enum dev_notifier note;
++ int do_delete = 0;
++
++ switch (cmd) {
++ case EIO_IOC_CREATE:
++ case EIO_IOC_ENABLE:
++
++ cache = vmalloc(sizeof(struct cache_rec_short));
++ if (!cache)
++ return -ENOMEM;
++
++ if (copy_from_user(cache, (void __user *)arg,
++ sizeof(struct cache_rec_short))) {
++ vfree(cache);
++ return -EFAULT;
++ }
++ error = eio_cache_create(cache);
++ vfree(cache);
++ break;
++
++ case EIO_IOC_DELETE:
++ do_delete = 1;
++
++ case EIO_IOC_DISABLE:
++
++ cache = vmalloc(sizeof(struct cache_rec_short));
++ if (!cache)
++ return -ENOMEM;
++
++ if (copy_from_user(cache, (void __user *)arg,
++ sizeof(struct cache_rec_short))) {
++ vfree(cache);
++ return -EFAULT;
++ }
++ error = eio_cache_delete(cache->cr_name, do_delete);
++ vfree(cache);
++ break;
++
++ case EIO_IOC_EDIT:
++ cache = vmalloc(sizeof(struct cache_rec_short));
++ if (!cache)
++ return -ENOMEM;
++
++ if (copy_from_user(cache, (void __user *)arg,
++ sizeof(struct cache_rec_short))) {
++ vfree(cache);
++ return -EFAULT;
++ }
++ error = eio_cache_edit(cache->cr_name,
++ (u_int32_t)cache->cr_mode,
++ (u_int32_t)cache->cr_policy);
++ vfree(cache);
++ break;
++
++ case EIO_IOC_NCACHES:
++ ncaches = eio_get_cache_count();
++ if (copy_to_user((uint64_t __user *)arg, &ncaches,
++ sizeof(uint64_t)))
++ return -EFAULT;
++ break;
++
++ case EIO_IOC_CACHE_LIST:
++ error = eio_get_cache_list((unsigned long __user *)arg);
++ break;
++
++ case EIO_IOC_SET_WARM_BOOT:
++ eio_set_warm_boot();
++ break;
++
++ case EIO_IOC_SSD_ADD:
++ cache = vmalloc(sizeof(struct cache_rec_short));
++ if (!cache)
++ return -ENOMEM;
++
++ if (copy_from_user(cache, (void __user *)arg,
++ sizeof(struct cache_rec_short))) {
++ vfree(cache);
++ return -EFAULT;
++ }
++ note = NOTIFY_SSD_ADD;
++ error =
++ eio_handle_ssd_message(cache->cr_name,
++ cache->cr_ssd_devname, note);
++ vfree(cache);
++
++ break;
++
++ case EIO_IOC_SSD_REMOVE:
++ cache = vmalloc(sizeof(struct cache_rec_short));
++ if (!cache)
++ return -ENOMEM;
++ if (copy_from_user(cache, (void __user *)arg,
++ sizeof(struct cache_rec_short))) {
++ vfree(cache);
++ return -EFAULT;
++ }
++ note = NOTIFY_SSD_REMOVED;
++ error =
++ eio_handle_ssd_message(cache->cr_name,
++ cache->cr_ssd_devname, note);
++ vfree(cache);
++ break;
++
++ case EIO_IOC_SRC_ADD:
++ break;
++
++ case EIO_IOC_NOTIFY_REBOOT:
++ eio_reboot_handling();
++ break;
++
++ default:
++ error = EINVAL;
++ }
++ return error;
++}
++
++long eio_compact_ioctl(struct file *filp, unsigned cmd, unsigned long arg)
++{
++ return eio_ioctl(filp, cmd, arg);
++}
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_ioctl.h linux-linaro-stable-mx6/drivers/block/enhanceio/eio_ioctl.h
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_ioctl.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_ioctl.h 2014-05-15 20:33:45.317922470 +0200
+@@ -0,0 +1,86 @@
++/*
++ * eio_ioctl.h
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ ****************************************************************************/
++
++#ifndef EIO_IOCTL_H
++#define EIO_IOCTL_H
++
++#define EIO_DEVPATH "/dev/eiodev"
++#define MISC_DEVICE "eiodev"
++
++#define CACHE_NAME_LEN 31
++#define CACHE_NAME_SZ (CACHE_NAME_LEN + 1)
++
++#define NAME_LEN 127
++#define NAME_SZ (NAME_LEN + 1)
++
++#define EIO_IOC_CREATE _IOW('E', 0, struct cache_rec_short)
++#define EIO_IOC_DELETE _IOW('E', 1, struct cache_rec_short)
++#define EIO_IOC_ENABLE _IOW('E', 2, struct cache_rec_short)
++#define EIO_IOC_DISABLE _IOW('E', 3, struct cache_rec_short)
++#define EIO_IOC_EDIT _IOW('E', 4, struct cache_rec_short)
++#define EIO_IOC_NCACHES _IOR('E', 5, uint64_t)
++#define EIO_IOC_CACHE_LIST _IOWR('E', 6, struct cache_list)
++#define EIO_IOC_SSD_ADD _IOW('E', 7, struct cache_rec_short)
++#define EIO_IOC_SSD_REMOVE _IOW('E', 8, struct cache_rec_short)
++#define EIO_IOC_SRC_ADD _IOW('E', 9, struct cache_rec_short)
++#define EIO_IOC_SRC_REMOVE _IOW('E', 10, struct cache_rec_short)
++#define EIO_IOC_NOTIFY_REBOOT _IO('E', 11)
++#define EIO_IOC_SET_WARM_BOOT _IO('E', 12)
++#define EIO_IOC_UNUSED _IO('E', 13)
++
++
++struct cache_rec_short {
++ char cr_name[CACHE_NAME_SZ];
++ char cr_src_devname[NAME_SZ];
++ char cr_ssd_devname[NAME_SZ];
++ char cr_ssd_uuid[NAME_SZ];
++ uint64_t cr_src_dev_size;
++ uint64_t cr_ssd_dev_size;
++ uint32_t cr_src_sector_size;
++ uint32_t cr_ssd_sector_size;
++ uint32_t cr_flags; /* CACHE_FLAGS_INV* etc. */
++ char cr_policy;
++ char cr_mode;
++ char cr_persistence;
++ char cr_cold_boot;
++ uint64_t cr_blksize;
++ uint64_t cr_assoc;
++};
++
++struct cache_list {
++ uint64_t ncaches;
++ struct cache_rec_short *cachelist;
++};
++
++#ifdef __KERNEL__
++long eio_ioctl(struct file *filp, unsigned cmd, unsigned long arg);
++long eio_compact_ioctl(struct file *filp, unsigned cmd, unsigned long arg);
++#endif /* __KERNEL__ */
++
++#endif /* !EIO_IOCTL_H */
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_lru.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_lru.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_lru.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_lru.c 2014-05-15 20:33:45.317922470 +0200
+@@ -0,0 +1,322 @@
++/*
++ * eio_lru.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include "eio.h"
++/* Generic policy functions prototyes */
++int eio_lru_init(struct cache_c *);
++void eio_lru_exit(void);
++int eio_lru_cache_sets_init(struct eio_policy *);
++int eio_lru_cache_blk_init(struct eio_policy *);
++void eio_lru_find_reclaim_dbn(struct eio_policy *, index_t, index_t *);
++int eio_lru_clean_set(struct eio_policy *, index_t, int);
++/* Per policy instance initialization */
++struct eio_policy *eio_lru_instance_init(void);
++
++/* LRU specific policy functions prototype */
++void eio_lru_pushblks(struct eio_policy *);
++void eio_reclaim_lru_movetail(struct cache_c *, index_t, struct eio_policy *);
++
++/* Per cache set data structure */
++struct eio_lru_cache_set {
++ u_int16_t lru_head, lru_tail;
++};
++
++/* Per cache block data structure */
++struct eio_lru_cache_block {
++ u_int16_t lru_prev, lru_next;
++};
++
++/* LRU specifc data structures */
++static struct eio_lru eio_lru = {
++ .sl_lru_pushblks = eio_lru_pushblks,
++ .sl_reclaim_lru_movetail = eio_reclaim_lru_movetail,
++};
++
++/*
++ * Context that captures the LRU replacement policy
++ */
++static struct eio_policy_header eio_lru_ops = {
++ .sph_name = CACHE_REPL_LRU,
++ .sph_instance_init = eio_lru_instance_init,
++};
++
++/*
++ * Intialize LRU. Called from ctr.
++ */
++int eio_lru_init(struct cache_c *dmc)
++{
++ return 0;
++}
++
++/*
++ * Initialize per set LRU data structures.
++ */
++int eio_lru_cache_sets_init(struct eio_policy *p_ops)
++{
++ sector_t order;
++ int i;
++ struct cache_c *dmc = p_ops->sp_dmc;
++ struct eio_lru_cache_set *cache_sets;
++
++ order =
++ (dmc->size >> dmc->consecutive_shift) *
++ sizeof(struct eio_lru_cache_set);
++
++ dmc->sp_cache_set = vmalloc((size_t)order);
++ if (dmc->sp_cache_set == NULL)
++ return -ENOMEM;
++
++ cache_sets = (struct eio_lru_cache_set *)dmc->sp_cache_set;
++
++ for (i = 0; i < (int)(dmc->size >> dmc->consecutive_shift); i++) {
++ cache_sets[i].lru_tail = EIO_LRU_NULL;
++ cache_sets[i].lru_head = EIO_LRU_NULL;
++ }
++ pr_info("Initialized %d sets in LRU", i);
++
++ return 0;
++}
++
++/*
++ * Initialize per block LRU data structures
++ */
++int eio_lru_cache_blk_init(struct eio_policy *p_ops)
++{
++ sector_t order;
++ struct cache_c *dmc = p_ops->sp_dmc;
++
++ order = dmc->size * sizeof(struct eio_lru_cache_block);
++
++ dmc->sp_cache_blk = vmalloc((size_t)order);
++ if (dmc->sp_cache_blk == NULL)
++ return -ENOMEM;
++
++ return 0;
++}
++
++/*
++ * Allocate a new instance of eio_policy per dmc
++ */
++struct eio_policy *eio_lru_instance_init(void)
++{
++ struct eio_policy *new_instance;
++
++ new_instance = vmalloc(sizeof(struct eio_policy));
++ if (new_instance == NULL) {
++ pr_err("eio_lru_instance_init: vmalloc failed");
++ return NULL;
++ }
++
++ /* Initialize the LRU specific functions and variables */
++ new_instance->sp_name = CACHE_REPL_LRU;
++ new_instance->sp_policy.lru = &eio_lru;
++ new_instance->sp_repl_init = eio_lru_init;
++ new_instance->sp_repl_exit = eio_lru_exit;
++ new_instance->sp_repl_sets_init = eio_lru_cache_sets_init;
++ new_instance->sp_repl_blk_init = eio_lru_cache_blk_init;
++ new_instance->sp_find_reclaim_dbn = eio_lru_find_reclaim_dbn;
++ new_instance->sp_clean_set = eio_lru_clean_set;
++ new_instance->sp_dmc = NULL;
++
++ try_module_get(THIS_MODULE);
++
++ pr_info("eio_lru_instance_init: created new instance of LRU");
++
++ return new_instance;
++}
++
++/*
++ * Cleanup an instance of eio_policy (called from dtr).
++ */
++void eio_lru_exit(void)
++{
++ module_put(THIS_MODULE);
++}
++
++/*
++ * Find a victim block to evict and return it in index.
++ */
++void
++eio_lru_find_reclaim_dbn(struct eio_policy *p_ops,
++ index_t start_index, index_t *index)
++{
++ index_t lru_rel_index;
++ struct eio_lru_cache_set *lru_sets;
++ struct eio_lru_cache_block *lru_blk;
++ struct cache_c *dmc = p_ops->sp_dmc;
++ index_t set;
++
++ set = start_index / dmc->assoc;
++ lru_sets = (struct eio_lru_cache_set *)(dmc->sp_cache_set);
++
++ lru_rel_index = lru_sets[set].lru_head;
++ while (lru_rel_index != EIO_LRU_NULL) {
++ lru_blk =
++ ((struct eio_lru_cache_block *)dmc->sp_cache_blk +
++ lru_rel_index + start_index);
++ if (EIO_CACHE_STATE_GET(dmc, (lru_rel_index + start_index)) ==
++ VALID) {
++ EIO_ASSERT((lru_blk - (struct eio_lru_cache_block *)
++ dmc->sp_cache_blk) ==
++ (lru_rel_index + start_index));
++ *index = lru_rel_index + start_index;
++ eio_reclaim_lru_movetail(dmc, *index, p_ops);
++ break;
++ }
++ lru_rel_index = lru_blk->lru_next;
++ }
++
++ return;
++}
++
++/*
++ * Go through the entire set and clean.
++ */
++int eio_lru_clean_set(struct eio_policy *p_ops, index_t set, int to_clean)
++{
++ struct cache_c *dmc = p_ops->sp_dmc;
++ index_t lru_rel_index;
++ int nr_writes = 0;
++ struct eio_lru_cache_set *lru_cache_sets;
++ struct eio_lru_cache_block *lru_cacheblk;
++ index_t dmc_idx;
++ index_t start_index;
++
++ lru_cache_sets = (struct eio_lru_cache_set *)dmc->sp_cache_set;
++ start_index = set * dmc->assoc;
++ lru_rel_index = lru_cache_sets[set].lru_head;
++
++ while ((lru_rel_index != EIO_LRU_NULL) && (nr_writes < to_clean)) {
++ dmc_idx = lru_rel_index + start_index;
++ lru_cacheblk =
++ ((struct eio_lru_cache_block *)dmc->sp_cache_blk +
++ lru_rel_index + start_index);
++ EIO_ASSERT((lru_cacheblk -
++ (struct eio_lru_cache_block *)dmc->sp_cache_blk) ==
++ (lru_rel_index + start_index));
++ if ((EIO_CACHE_STATE_GET(dmc, dmc_idx) &
++ (DIRTY | BLOCK_IO_INPROG)) == DIRTY) {
++ EIO_CACHE_STATE_ON(dmc, dmc_idx, DISKWRITEINPROG);
++ nr_writes++;
++ }
++ lru_rel_index = lru_cacheblk->lru_next;
++ }
++
++ return nr_writes;
++}
++
++/*
++ * LRU specific functions.
++ */
++void
++eio_reclaim_lru_movetail(struct cache_c *dmc, index_t index,
++ struct eio_policy *p_ops)
++{
++ index_t set = index / dmc->assoc;
++ index_t start_index = set * dmc->assoc;
++ index_t my_index = index - start_index;
++ struct eio_lru_cache_block *cacheblk;
++ struct eio_lru_cache_set *cache_sets;
++ struct eio_lru_cache_block *blkptr;
++
++ cacheblk =
++ (((struct eio_lru_cache_block *)(dmc->sp_cache_blk)) + index);
++ cache_sets = (struct eio_lru_cache_set *)dmc->sp_cache_set;
++ blkptr = (struct eio_lru_cache_block *)(dmc->sp_cache_blk);
++
++ /* Remove from LRU */
++ if (likely((cacheblk->lru_prev != EIO_LRU_NULL) ||
++ (cacheblk->lru_next != EIO_LRU_NULL))) {
++ if (cacheblk->lru_prev != EIO_LRU_NULL)
++ blkptr[cacheblk->lru_prev + start_index].lru_next =
++ cacheblk->lru_next;
++ else
++ cache_sets[set].lru_head = cacheblk->lru_next;
++ if (cacheblk->lru_next != EIO_LRU_NULL)
++ blkptr[cacheblk->lru_next + start_index].lru_prev =
++ cacheblk->lru_prev;
++ else
++ cache_sets[set].lru_tail = cacheblk->lru_prev;
++ }
++ /* And add it to LRU Tail */
++ cacheblk->lru_next = EIO_LRU_NULL;
++ cacheblk->lru_prev = cache_sets[set].lru_tail;
++ if (cache_sets[set].lru_tail == EIO_LRU_NULL)
++ cache_sets[set].lru_head = (u_int16_t)my_index;
++ else
++ blkptr[cache_sets[set].lru_tail + start_index].lru_next =
++ (u_int16_t)my_index;
++ cache_sets[set].lru_tail = (u_int16_t)my_index;
++}
++
++void eio_lru_pushblks(struct eio_policy *p_ops)
++{
++ struct cache_c *dmc = p_ops->sp_dmc;
++ struct eio_lru_cache_block *cache_block;
++ int i;
++
++ cache_block = dmc->sp_cache_blk;
++ for (i = 0; i < (int)dmc->size; i++) {
++ cache_block[i].lru_prev = EIO_LRU_NULL;
++ cache_block[i].lru_next = EIO_LRU_NULL;
++ eio_reclaim_lru_movetail(dmc, i, p_ops);
++ }
++ return;
++}
++
++static
++int __init lru_register(void)
++{
++ int ret;
++
++ ret = eio_register_policy(&eio_lru_ops);
++ if (ret != 0)
++ pr_info("eio_lru already registered");
++
++ return ret;
++}
++
++static
++void __exit lru_unregister(void)
++{
++ int ret;
++
++ ret = eio_unregister_policy(&eio_lru_ops);
++ if (ret != 0)
++ pr_err("eio_lru unregister failed");
++}
++
++module_init(lru_register);
++module_exit(lru_unregister);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("LRU policy for EnhanceIO");
++MODULE_AUTHOR("STEC, Inc. based on code by Facebook");
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_main.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_main.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_main.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_main.c 2014-05-15 20:33:45.317922470 +0200
+@@ -0,0 +1,3546 @@
++/*
++ * eio_main.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ * Amit Kale <akale@stec-inc.com>
++ * Restructured much of the io code to split bio within map function instead
++ * of letting dm do it.
++ * Simplified queued logic for write through.
++ * Created per-cache spinlocks for reducing contention in IO codepath.
++ * Amit Kale <akale@stec-inc.com>
++ * Harish Pujari <hpujari@stec-inc.com>
++ * Designed and implemented the writeback caching mode
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "eio.h"
++#include "eio_ttc.h"
++
++#define CTRACE(X) { }
++
++/*
++ * TODO List :
++ * 1) sysctls : Create per-cache device sysctls instead of global sysctls.
++ * 2) Management of non cache pids : Needs improvement. Remove registration
++ * on process exits (with a pseudo filesstem'ish approach perhaps) ?
++ * 3) Breaking up the cache spinlock : Right now contention on the spinlock
++ * is not a problem. Might need change in future.
++ * 4) Use the standard linked list manipulation macros instead rolling our own.
++ * 5) Fix a security hole : A malicious process with 'ro' access to a file can
++ * potentially corrupt file data. This can be fixed by copying the data on a
++ * cache read miss.
++ */
++
++static int eio_read_peek(struct cache_c *dmc, struct eio_bio *ebio);
++static int eio_write_peek(struct cache_c *dmc, struct eio_bio *ebio);
++static void eio_read(struct cache_c *dmc, struct bio_container *bc,
++ struct eio_bio *ebegin);
++static void eio_write(struct cache_c *dmc, struct bio_container *bc,
++ struct eio_bio *ebegin);
++static int eio_inval_block(struct cache_c *dmc, sector_t iosector);
++static void eio_enqueue_readfill(struct cache_c *dmc, struct kcached_job *job);
++static int eio_acquire_set_locks(struct cache_c *dmc, struct bio_container *bc);
++static int eio_release_io_resources(struct cache_c *dmc,
++ struct bio_container *bc);
++static void eio_clean_set(struct cache_c *dmc, index_t set, int whole,
++ int force);
++static void eio_do_mdupdate(struct work_struct *work);
++static void eio_mdupdate_callback(int error, void *context);
++static void eio_enq_mdupdate(struct bio_container *bc);
++static void eio_uncached_read_done(struct kcached_job *job);
++static void eio_addto_cleanq(struct cache_c *dmc, index_t set, int whole);
++static int eio_alloc_mdreqs(struct cache_c *, struct bio_container *);
++static void eio_check_dirty_set_thresholds(struct cache_c *dmc, index_t set);
++static void eio_check_dirty_cache_thresholds(struct cache_c *dmc);
++static void eio_post_mdupdate(struct work_struct *work);
++static void eio_post_io_callback(struct work_struct *work);
++
++static void bc_addfb(struct bio_container *bc, struct eio_bio *ebio)
++{
++
++ atomic_inc(&bc->bc_holdcount);
++
++ ebio->eb_bc = bc;
++}
++
++static void bc_put(struct bio_container *bc, unsigned int doneio)
++{
++ struct cache_c *dmc;
++ int data_dir;
++ long elapsed;
++
++ if (atomic_dec_and_test(&bc->bc_holdcount)) {
++ if (bc->bc_dmc->mode == CACHE_MODE_WB)
++ eio_release_io_resources(bc->bc_dmc, bc);
++ bc->bc_bio->bi_size = 0;
++ dmc = bc->bc_dmc;
++
++ /* update iotime for latency */
++ data_dir = bio_data_dir(bc->bc_bio);
++ elapsed = (long)jiffies_to_msecs(jiffies - bc->bc_iotime);
++
++ if (data_dir == READ)
++ atomic64_add(elapsed, &dmc->eio_stats.rdtime_ms);
++ else
++ atomic64_add(elapsed, &dmc->eio_stats.wrtime_ms);
++
++ bio_endio(bc->bc_bio, bc->bc_error);
++ atomic64_dec(&bc->bc_dmc->nr_ios);
++ kfree(bc);
++ }
++}
++
++static void eb_endio(struct eio_bio *ebio, int error)
++{
++
++ EIO_ASSERT(ebio->eb_bc);
++
++ /*Propagate only main io errors and sizes*/
++ if (ebio->eb_iotype == EB_MAIN_IO) {
++ if (error)
++ ebio->eb_bc->bc_error = error;
++ bc_put(ebio->eb_bc, ebio->eb_size);
++ } else
++ bc_put(ebio->eb_bc, 0);
++ ebio->eb_bc = NULL;
++ kfree(ebio);
++}
++
++static int
++eio_io_async_bvec(struct cache_c *dmc, struct eio_io_region *where, int rw,
++ struct bio_vec *pages, unsigned nr_bvecs, eio_notify_fn fn,
++ void *context, int hddio)
++{
++ struct eio_io_request req;
++ int error = 0;
++
++ memset((char *)&req, 0, sizeof(req));
++
++ if (unlikely(CACHE_DEGRADED_IS_SET(dmc))) {
++ if (where->bdev != dmc->disk_dev->bdev) {
++ pr_err
++ ("eio_io_async_bvec: Cache is in degraded mode.\n");
++ pr_err
++ ("eio_io_async_Bvec: Can not issue i/o to ssd device.\n");
++ return -ENODEV;
++ }
++ }
++
++ req.mtype = EIO_BVECS;
++ req.dptr.pages = pages;
++ req.num_bvecs = nr_bvecs;
++ req.notify = fn;
++ req.context = context;
++ req.hddio = hddio;
++
++ error = eio_do_io(dmc, where, rw, &req);
++
++ return error;
++}
++
++static void
++eio_flag_abios(struct cache_c *dmc, struct eio_bio *abio, int invalidated)
++{
++ struct eio_bio *nbio;
++
++ while (abio) {
++ int invalidate;
++ unsigned long flags;
++ int cwip_on = 0;
++ int dirty_on = 0;
++ int callendio = 0;
++ nbio = abio->eb_next;
++
++ EIO_ASSERT(!(abio->eb_iotype & EB_INVAL) || abio->eb_index == -1);
++ invalidate = !invalidated && (abio->eb_iotype & EB_INVAL);
++
++ spin_lock_irqsave(&dmc->cache_sets[abio->eb_cacheset].cs_lock,
++ flags);
++
++ if (abio->eb_index != -1) {
++ if (EIO_CACHE_STATE_GET(dmc, abio->eb_index) & DIRTY)
++ dirty_on = 1;
++
++ if (unlikely
++ (EIO_CACHE_STATE_GET(dmc, abio->eb_index) &
++ CACHEWRITEINPROG))
++ cwip_on = 1;
++ }
++
++ if (dirty_on) {
++ /*
++ * For dirty blocks, we don't change the cache state flags.
++ * We however, need to end the ebio, if this was the last
++ * hold on it.
++ */
++ if (atomic_dec_and_test(&abio->eb_holdcount)) {
++ callendio = 1;
++ /* We shouldn't reach here when the DIRTY_INPROG flag
++ * is set on the cache block. It should either have been
++ * cleared to become DIRTY or INVALID elsewhere.
++ */
++ EIO_ASSERT(EIO_CACHE_STATE_GET(dmc, abio->eb_index)
++ != DIRTY_INPROG);
++ }
++ } else if (abio->eb_index != -1) {
++ if (invalidate) {
++ if (cwip_on)
++ EIO_CACHE_STATE_ON(dmc, abio->eb_index,
++ QUEUED);
++ else {
++ EIO_CACHE_STATE_SET(dmc, abio->eb_index,
++ INVALID);
++ atomic64_dec_if_positive(&dmc->
++ eio_stats.
++ cached_blocks);
++ }
++ } else {
++ if (cwip_on)
++ EIO_CACHE_STATE_OFF(dmc, abio->eb_index,
++ DISKWRITEINPROG);
++ else {
++ if (EIO_CACHE_STATE_GET
++ (dmc, abio->eb_index) & QUEUED) {
++ EIO_CACHE_STATE_SET(dmc,
++ abio->
++ eb_index,
++ INVALID);
++ atomic64_dec_if_positive(&dmc->
++ eio_stats.
++ cached_blocks);
++ } else {
++ EIO_CACHE_STATE_SET(dmc,
++ abio->
++ eb_index,
++ VALID);
++ }
++ }
++ }
++ } else {
++ EIO_ASSERT(invalidated || invalidate);
++ if (invalidate)
++ eio_inval_block(dmc, abio->eb_sector);
++ }
++ spin_unlock_irqrestore(&dmc->cache_sets[abio->eb_cacheset].
++ cs_lock, flags);
++ if (!cwip_on && (!dirty_on || callendio))
++ eb_endio(abio, 0);
++ abio = nbio;
++ }
++}
++
++static void eio_disk_io_callback(int error, void *context)
++{
++ struct kcached_job *job;
++ struct eio_bio *ebio;
++ struct cache_c *dmc;
++ unsigned long flags;
++ unsigned eb_cacheset;
++
++ flags = 0;
++ job = (struct kcached_job *)context;
++ dmc = job->dmc;
++ ebio = job->ebio;
++
++ EIO_ASSERT(ebio != NULL);
++ eb_cacheset = ebio->eb_cacheset;
++
++ if (unlikely(error))
++ dmc->eio_errors.disk_read_errors++;
++
++ spin_lock_irqsave(&dmc->cache_sets[eb_cacheset].cs_lock, flags);
++ /* Invalidate the cache block */
++ EIO_CACHE_STATE_SET(dmc, ebio->eb_index, INVALID);
++ atomic64_dec_if_positive(&dmc->eio_stats.cached_blocks);
++ spin_unlock_irqrestore(&dmc->cache_sets[eb_cacheset].cs_lock, flags);
++
++ if (unlikely(error))
++ pr_err("disk_io_callback: io error %d block %llu action %d",
++ error,
++ (unsigned long long)job->job_io_regions.disk.sector,
++ job->action);
++
++ eb_endio(ebio, error);
++ ebio = NULL;
++ job->ebio = NULL;
++ eio_free_cache_job(job);
++ job = NULL;
++}
++
++static void eio_uncached_read_done(struct kcached_job *job)
++{
++ struct eio_bio *ebio = job->ebio;
++ struct cache_c *dmc = job->dmc;
++ struct eio_bio *iebio;
++ struct eio_bio *nebio;
++ unsigned long flags = 0;
++
++ if (ebio->eb_bc->bc_dir == UNCACHED_READ) {
++ EIO_ASSERT(ebio != NULL);
++ iebio = ebio->eb_next;
++ while (iebio != NULL) {
++ nebio = iebio->eb_next;
++ if (iebio->eb_index != -1) {
++ spin_lock_irqsave(&dmc->
++ cache_sets[iebio->
++ eb_cacheset].
++ cs_lock, flags);
++ if (unlikely
++ (EIO_CACHE_STATE_GET(dmc, iebio->eb_index) &
++ QUEUED)) {
++ EIO_CACHE_STATE_SET(dmc,
++ iebio->eb_index,
++ INVALID);
++ atomic64_dec_if_positive(&dmc->
++ eio_stats.
++ cached_blocks);
++ } else
++ if (EIO_CACHE_STATE_GET
++ (dmc,
++ iebio->eb_index) & CACHEREADINPROG) {
++ /*turn off the cache read in prog flag*/
++ EIO_CACHE_STATE_OFF(dmc,
++ iebio->eb_index,
++ BLOCK_IO_INPROG);
++ } else
++ /*Should never reach here*/
++ EIO_ASSERT(0);
++ spin_unlock_irqrestore(&dmc->
++ cache_sets[iebio->
++ eb_cacheset].
++ cs_lock, flags);
++ }
++ eb_endio(iebio, 0);
++ iebio = nebio;
++ }
++ eb_endio(ebio, 0);
++ eio_free_cache_job(job);
++ } else if (ebio->eb_bc->bc_dir == UNCACHED_READ_AND_READFILL) {
++ /*
++ * Kick off the READFILL. It will also do a read
++ * from SSD, in case of ALREADY_DIRTY block
++ */
++ job->action = READFILL;
++ eio_enqueue_readfill(dmc, job);
++ } else
++ /* Should never reach here for uncached read */
++ EIO_ASSERT(0);
++}
++
++static void eio_io_callback(int error, void *context)
++{
++ struct kcached_job *job = (struct kcached_job *)context;
++ struct cache_c *dmc = job->dmc;
++
++ job->error = error;
++ INIT_WORK(&job->work, eio_post_io_callback);
++ queue_work(dmc->callback_q, &job->work);
++ return;
++}
++
++static void eio_post_io_callback(struct work_struct *work)
++{
++ struct kcached_job *job;
++ struct cache_c *dmc;
++ struct eio_bio *ebio;
++ unsigned long flags = 0;
++ index_t index;
++ unsigned eb_cacheset;
++ u_int8_t cstate;
++ int callendio = 0;
++ int error;
++
++ job = container_of(work, struct kcached_job, work);
++ dmc = job->dmc;
++ index = job->index;
++ error = job->error;
++
++ EIO_ASSERT(index != -1 || job->action == WRITEDISK
++ || job->action == READDISK);
++ ebio = job->ebio;
++ EIO_ASSERT(ebio != NULL);
++ EIO_ASSERT(ebio->eb_bc);
++
++ eb_cacheset = ebio->eb_cacheset;
++ if (error)
++ pr_err("io_callback: io error %d block %llu action %d",
++ error,
++ (unsigned long long)job->job_io_regions.disk.sector,
++ job->action);
++
++ switch (job->action) {
++ case WRITEDISK:
++
++ atomic64_inc(&dmc->eio_stats.writedisk);
++ if (unlikely(error))
++ dmc->eio_errors.disk_write_errors++;
++ if (unlikely(error) || (ebio->eb_iotype & EB_INVAL))
++ eio_inval_range(dmc, ebio->eb_sector, ebio->eb_size);
++ if (ebio->eb_next)
++ eio_flag_abios(dmc, ebio->eb_next,
++ error || (ebio->eb_iotype & EB_INVAL));
++ eb_endio(ebio, error);
++ job->ebio = NULL;
++ eio_free_cache_job(job);
++ return;
++
++ case READDISK:
++
++ if (unlikely(error) || unlikely(ebio->eb_iotype & EB_INVAL)
++ || CACHE_DEGRADED_IS_SET(dmc)) {
++ if (error)
++ dmc->eio_errors.disk_read_errors++;
++ eio_inval_range(dmc, ebio->eb_sector, ebio->eb_size);
++ eio_flag_abios(dmc, ebio->eb_next, 1);
++ } else if (ebio->eb_next) {
++ eio_uncached_read_done(job);
++ return;
++ }
++ eb_endio(ebio, error);
++ job->ebio = NULL;
++ eio_free_cache_job(job);
++ return;
++
++ case READCACHE:
++
++ /*atomic64_inc(&dmc->eio_stats.readcache);*/
++ /*SECTOR_STATS(dmc->eio_stats.ssd_reads, ebio->eb_size);*/
++ EIO_ASSERT(EIO_DBN_GET(dmc, index) ==
++ EIO_ROUND_SECTOR(dmc, ebio->eb_sector));
++ cstate = EIO_CACHE_STATE_GET(dmc, index);
++ /* We shouldn't reach here for DIRTY_INPROG blocks. */
++ EIO_ASSERT(cstate != DIRTY_INPROG);
++ if (unlikely(error)) {
++ dmc->eio_errors.ssd_read_errors++;
++ /* Retry read from HDD for non-DIRTY blocks. */
++ if (cstate != ALREADY_DIRTY) {
++ spin_lock_irqsave(&dmc->cache_sets[eb_cacheset].
++ cs_lock, flags);
++ EIO_CACHE_STATE_OFF(dmc, ebio->eb_index,
++ CACHEREADINPROG);
++ EIO_CACHE_STATE_ON(dmc, ebio->eb_index,
++ DISKREADINPROG);
++ spin_unlock_irqrestore(&dmc->
++ cache_sets[eb_cacheset].
++ cs_lock, flags);
++
++ eio_push_ssdread_failures(job);
++ schedule_work(&_kcached_wq);
++
++ return;
++ }
++ }
++ callendio = 1;
++ break;
++
++ case READFILL:
++
++ /*atomic64_inc(&dmc->eio_stats.readfill);*/
++ /*SECTOR_STATS(dmc->eio_stats.ssd_writes, ebio->eb_size);*/
++ EIO_ASSERT(EIO_DBN_GET(dmc, index) == ebio->eb_sector);
++ if (unlikely(error))
++ dmc->eio_errors.ssd_write_errors++;
++ if (!(EIO_CACHE_STATE_GET(dmc, index) & CACHEWRITEINPROG)) {
++ pr_debug("DISKWRITEINPROG absent in READFILL \
++ sector %llu io size %u\n",
++ (unsigned long long)ebio->eb_sector,
++ ebio->eb_size);
++ }
++ callendio = 1;
++ break;
++
++ case WRITECACHE:
++
++ /*SECTOR_STATS(dmc->eio_stats.ssd_writes, ebio->eb_size);*/
++ /*atomic64_inc(&dmc->eio_stats.writecache);*/
++ cstate = EIO_CACHE_STATE_GET(dmc, index);
++ EIO_ASSERT(EIO_DBN_GET(dmc, index) ==
++ EIO_ROUND_SECTOR(dmc, ebio->eb_sector));
++ /* CWIP is a must for WRITECACHE, except when it is DIRTY */
++ EIO_ASSERT(cstate & (CACHEWRITEINPROG | DIRTY));
++ if (likely(error == 0)) {
++ /* If it is a DIRTY inprog block, proceed for metadata update */
++ if (cstate == DIRTY_INPROG) {
++ eio_md_write(job);
++ return;
++ }
++ } else {
++ /* TODO: ask if this if condition is required */
++ if (dmc->mode == CACHE_MODE_WT)
++ dmc->eio_errors.disk_write_errors++;
++ dmc->eio_errors.ssd_write_errors++;
++ }
++ job->ebio = NULL;
++ break;
++
++ default:
++ pr_err("io_callback: invalid action %d", job->action);
++ return;
++ }
++
++ spin_lock_irqsave(&dmc->cache_sets[eb_cacheset].cs_lock, flags);
++
++ cstate = EIO_CACHE_STATE_GET(dmc, index);
++ EIO_ASSERT(!(cstate & INVALID));
++
++ if (unlikely
++ ((job->action == WRITECACHE) && !(cstate & DISKWRITEINPROG))) {
++ /*
++ * Can reach here in 2 cases:
++ * 1. Uncached write case, where WRITEDISK has finished first
++ * 2. Cached write case
++ *
++ * For DIRTY or DIRTY inprog cases, use eb holdcount to determine
++ * if end ebio can be called. This is because, we don't set DWIP etc
++ * flags on those and we have to avoid double end ebio call
++ */
++ EIO_ASSERT((cstate != DIRTY_INPROG) || error);
++ callendio = 1;
++ if ((cstate & DIRTY)
++ && !atomic_dec_and_test(&ebio->eb_holdcount))
++ callendio = 0;
++ }
++
++ if (cstate & DISKWRITEINPROG) {
++ /* uncached write and WRITEDISK is not yet finished */
++ EIO_ASSERT(!(cstate & DIRTY)); /* For dirty blocks, we can't have DWIP flag */
++ if (error)
++ EIO_CACHE_STATE_ON(dmc, index, QUEUED);
++ EIO_CACHE_STATE_OFF(dmc, index, CACHEWRITEINPROG);
++ } else if (unlikely(error || (cstate & QUEUED))) {
++ /* Error or QUEUED is set: mark block as INVALID for non-DIRTY blocks */
++ if (cstate != ALREADY_DIRTY) {
++ EIO_CACHE_STATE_SET(dmc, index, INVALID);
++ atomic64_dec_if_positive(&dmc->eio_stats.cached_blocks);
++ }
++ } else if (cstate & VALID) {
++ EIO_CACHE_STATE_OFF(dmc, index, BLOCK_IO_INPROG);
++ /*
++ * If we have NO_SSD_IO_INPROG flag set, then this block needs to be
++ * invalidated. There are three things that can happen -- (i) error,
++ * (ii) IOs are queued on this block, and (iii) success.
++ *
++ * If there was an error or if the QUEUED bit was set, then the logic
++ * in the if part will take care of setting the block to INVALID.
++ * Therefore, this is the success path where we invalidate if need be.
++ */
++
++ /*
++ * TBD
++ * NO_SSD_IO_INPROG need to be differently handled, in case block is DIRTY
++ */
++ if ((cstate & NO_SSD_IO_INPROG) == NO_SSD_IO_INPROG)
++ EIO_CACHE_STATE_OFF(dmc, index, VALID);
++ }
++
++ spin_unlock_irqrestore(&dmc->cache_sets[eb_cacheset].cs_lock, flags);
++
++ if (callendio)
++ eb_endio(ebio, error);
++
++ eio_free_cache_job(job);
++ job = NULL;
++
++}
++
++/*
++ * This function processes the kcached_job that
++ * needs to be scheduled on disk after ssd read failures.
++ */
++void eio_ssderror_diskread(struct kcached_job *job)
++{
++ struct cache_c *dmc;
++ struct eio_bio *ebio;
++ index_t index;
++ int error;
++ unsigned long flags = 0;
++
++ dmc = job->dmc;
++ error = 0;
++
++ /*
++ * 1. Extract the ebio which needs to be scheduled on disk.
++ * 2. Verify cache block state is VALID
++ * 3. Make sure that the cache state in not IOINPROG
++ */
++ /* Reset the ssd read error in the job. */
++ job->error = 0;
++ ebio = job->ebio;
++ index = ebio->eb_index;
++
++ EIO_ASSERT(index != -1);
++
++ spin_lock_irqsave(&dmc->cache_sets[index / dmc->assoc].cs_lock, flags);
++ EIO_ASSERT(EIO_CACHE_STATE_GET(dmc, index) & DISKREADINPROG);
++ spin_unlock_irqrestore(&dmc->cache_sets[index / dmc->assoc].cs_lock,
++ flags);
++
++ EIO_ASSERT(ebio->eb_dir == READ);
++
++ atomic64_inc(&dmc->eio_stats.readdisk);
++ SECTOR_STATS(dmc->eio_stats.disk_reads, ebio->eb_size);
++ job->action = READDISK;
++
++ error = eio_io_async_bvec(dmc, &job->job_io_regions.disk, ebio->eb_dir,
++ ebio->eb_bv, ebio->eb_nbvec,
++ eio_disk_io_callback, job, 1);
++
++ /*
++ * In case of disk i/o submission error clear ebio and kcached_job.
++ * This would return the actual read that was issued on ssd.
++ */
++ if (error)
++ goto out;
++
++ return;
++
++out:
++ /* We failed to submit the I/O to dm layer. The corresponding
++ * block should be marked as INVALID by turning off already set
++ * flags.
++ */
++ spin_lock_irqsave(&dmc->cache_sets[index / dmc->assoc].cs_lock, flags);
++ EIO_CACHE_STATE_SET(dmc, ebio->eb_index, INVALID);
++ spin_unlock_irqrestore(&dmc->cache_sets[index / dmc->assoc].cs_lock,
++ flags);
++
++ atomic64_dec_if_positive(&dmc->eio_stats.cached_blocks);
++
++ eb_endio(ebio, error);
++ ebio = NULL;
++ job->ebio = NULL;
++ eio_free_cache_job(job);
++}
++
++/* Adds clean set request to clean queue. */
++static void eio_addto_cleanq(struct cache_c *dmc, index_t set, int whole)
++{
++ unsigned long flags = 0;
++
++ spin_lock_irqsave(&dmc->cache_sets[set].cs_lock, flags);
++
++ if (dmc->cache_sets[set].flags & SETFLAG_CLEAN_INPROG) {
++ /* Clean already in progress, just add to clean pendings */
++ spin_unlock_irqrestore(&dmc->cache_sets[set].cs_lock, flags);
++ return;
++ }
++
++ dmc->cache_sets[set].flags |= SETFLAG_CLEAN_INPROG;
++ if (whole)
++ dmc->cache_sets[set].flags |= SETFLAG_CLEAN_WHOLE;
++
++ spin_unlock_irqrestore(&dmc->cache_sets[set].cs_lock, flags);
++
++ spin_lock_irqsave(&dmc->clean_sl, flags);
++ list_add_tail(&dmc->cache_sets[set].list, &dmc->cleanq);
++ atomic64_inc(&dmc->clean_pendings);
++ EIO_SET_EVENT_AND_UNLOCK(&dmc->clean_event, &dmc->clean_sl, flags);
++ return;
++}
++
++/*
++ * Clean thread loops forever in this, waiting for
++ * new clean set requests in the clean queue.
++ */
++int eio_clean_thread_proc(void *context)
++{
++ struct cache_c *dmc = (struct cache_c *)context;
++ unsigned long flags = 0;
++ u_int64_t systime;
++ index_t index;
++
++ /* Sync makes sense only for writeback cache */
++ EIO_ASSERT(dmc->mode == CACHE_MODE_WB);
++
++ dmc->clean_thread_running = 1;
++
++ /*
++ * Using sysctl_fast_remove to stop the clean thread
++ * works for now. Should have another flag specifically
++ * for such notification.
++ */
++ for (; !dmc->sysctl_active.fast_remove; ) {
++ LIST_HEAD(setlist);
++ struct cache_set *set;
++
++ eio_comply_dirty_thresholds(dmc, -1);
++
++ if (dmc->sysctl_active.do_clean) {
++ /* pause the periodic clean */
++ cancel_delayed_work_sync(&dmc->clean_aged_sets_work);
++
++ /* clean all the sets */
++ eio_clean_all(dmc);
++
++ /* resume the periodic clean */
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock, flags);
++ dmc->is_clean_aged_sets_sched = 0;
++ if (dmc->sysctl_active.time_based_clean_interval
++ && atomic64_read(&dmc->nr_dirty)) {
++ /* there is a potential race here, If a sysctl changes
++ the time_based_clean_interval to 0. However a strong
++ synchronisation is not necessary here
++ */
++ schedule_delayed_work(&dmc->
++ clean_aged_sets_work,
++ dmc->sysctl_active.
++ time_based_clean_interval
++ * 60 * HZ);
++ dmc->is_clean_aged_sets_sched = 1;
++ }
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock, flags);
++ }
++
++ if (dmc->sysctl_active.fast_remove)
++ break;
++
++ spin_lock_irqsave(&dmc->clean_sl, flags);
++
++ while (!
++ ((!list_empty(&dmc->cleanq))
++ || dmc->sysctl_active.fast_remove
++ || dmc->sysctl_active.do_clean))
++ EIO_WAIT_EVENT(&dmc->clean_event, &dmc->clean_sl,
++ flags);
++
++ /*
++ * Move cleanq elements to a private list for processing.
++ */
++
++ list_add(&setlist, &dmc->cleanq);
++ list_del(&dmc->cleanq);
++ INIT_LIST_HEAD(&dmc->cleanq);
++
++ spin_unlock_irqrestore(&dmc->clean_sl, flags);
++
++ systime = jiffies;
++ while (!list_empty(&setlist)) {
++ set =
++ list_entry((&setlist)->next, struct cache_set,
++ list);
++ list_del(&set->list);
++ index = set - dmc->cache_sets;
++ if (!(dmc->sysctl_active.fast_remove)) {
++ eio_clean_set(dmc, index,
++ set->flags & SETFLAG_CLEAN_WHOLE,
++ 0);
++ } else {
++
++ /*
++ * Since we are not cleaning the set, we should
++ * put the set back in the lru list so that
++ * it is picked up at a later point.
++ * We also need to clear the clean inprog flag
++ * otherwise this set would never be cleaned.
++ */
++
++ spin_lock_irqsave(&dmc->cache_sets[index].
++ cs_lock, flags);
++ dmc->cache_sets[index].flags &=
++ ~(SETFLAG_CLEAN_INPROG |
++ SETFLAG_CLEAN_WHOLE);
++ spin_unlock_irqrestore(&dmc->cache_sets[index].
++ cs_lock, flags);
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock,
++ flags);
++ lru_touch(dmc->dirty_set_lru, index, systime);
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock,
++ flags);
++ }
++ atomic64_dec(&dmc->clean_pendings);
++ }
++ }
++
++ /* notifier for cache delete that the clean thread has stopped running */
++ dmc->clean_thread_running = 0;
++
++ eio_thread_exit(0);
++
++ /*Should never reach here*/
++ return 0;
++}
++
++/*
++ * Cache miss support. We read the data from disk, write it to the ssd.
++ * To avoid doing 1 IO at a time to the ssd, when the IO is kicked off,
++ * we enqueue it to a "readfill" queue in the cache in cache sector order.
++ * The worker thread can then issue all of these IOs and do 1 unplug to
++ * start them all.
++ *
++ */
++static void eio_enqueue_readfill(struct cache_c *dmc, struct kcached_job *job)
++{
++ unsigned long flags = 0;
++ struct kcached_job **j1, *next;
++ int do_schedule = 0;
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ /* Insert job in sorted order of cache sector */
++ j1 = &dmc->readfill_queue;
++ while (*j1 != NULL && (*j1)->job_io_regions.cache.sector <
++ job->job_io_regions.cache.sector)
++ j1 = &(*j1)->next;
++ next = *j1;
++ *j1 = job;
++ job->next = next;
++ do_schedule = (dmc->readfill_in_prog == 0);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ if (do_schedule)
++ schedule_work(&dmc->readfill_wq);
++}
++
++void eio_do_readfill(struct work_struct *work)
++{
++ struct kcached_job *job, *joblist;
++ struct eio_bio *ebio;
++ unsigned long flags = 0;
++ struct kcached_job *nextjob = NULL;
++ struct cache_c *dmc = container_of(work, struct cache_c, readfill_wq);
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ if (dmc->readfill_in_prog)
++ goto out;
++ dmc->readfill_in_prog = 1;
++ while (dmc->readfill_queue != NULL) {
++ joblist = dmc->readfill_queue;
++ dmc->readfill_queue = NULL;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ for (job = joblist; job != NULL; job = nextjob) {
++ struct eio_bio *iebio;
++ struct eio_bio *next;
++
++ nextjob = job->next; /* save for later because 'job' will be freed */
++ EIO_ASSERT(job->action == READFILL);
++ /* Write to cache device */
++ ebio = job->ebio;
++ iebio = ebio->eb_next;
++ EIO_ASSERT(iebio);
++ /* other iebios are anchored on this bio. Create
++ * jobs for them and then issue ios
++ */
++ do {
++ struct kcached_job *job;
++ int err;
++ unsigned long flags;
++ index_t index;
++ next = iebio->eb_next;
++ index = iebio->eb_index;
++ if (index == -1) {
++ CTRACE("eio_do_readfill:1\n");
++ /* Any INPROG(including DIRTY_INPROG) case would fall here */
++ eb_endio(iebio, 0);
++ iebio = NULL;
++ } else {
++ spin_lock_irqsave(&dmc->
++ cache_sets[iebio->
++ eb_cacheset].
++ cs_lock, flags);
++ /* If this block was already valid, we don't need to write it */
++ if (unlikely
++ (EIO_CACHE_STATE_GET(dmc, index) &
++ QUEUED)) {
++ /*An invalidation request is queued. Can't do anything*/
++ CTRACE("eio_do_readfill:2\n");
++ EIO_CACHE_STATE_SET(dmc, index,
++ INVALID);
++ spin_unlock_irqrestore(&dmc->
++ cache_sets
++ [iebio->
++ eb_cacheset].
++ cs_lock,
++ flags);
++ atomic64_dec_if_positive(&dmc->
++ eio_stats.
++ cached_blocks);
++ eb_endio(iebio, 0);
++ iebio = NULL;
++ } else
++ if ((EIO_CACHE_STATE_GET(dmc, index)
++ & (VALID | DISKREADINPROG))
++ == (VALID | DISKREADINPROG)) {
++ /* Do readfill. */
++ EIO_CACHE_STATE_SET(dmc, index,
++ VALID |
++ CACHEWRITEINPROG);
++ EIO_ASSERT(EIO_DBN_GET(dmc, index)
++ == iebio->eb_sector);
++ spin_unlock_irqrestore(&dmc->
++ cache_sets
++ [iebio->
++ eb_cacheset].
++ cs_lock,
++ flags);
++ job =
++ eio_new_job(dmc, iebio,
++ iebio->
++ eb_index);
++ if (unlikely(job == NULL))
++ err = -ENOMEM;
++ else {
++ err = 0;
++ job->action = READFILL;
++ atomic_inc(&dmc->
++ nr_jobs);
++ SECTOR_STATS(dmc->
++ eio_stats.
++ ssd_readfills,
++ iebio->
++ eb_size);
++ SECTOR_STATS(dmc->
++ eio_stats.
++ ssd_writes,
++ iebio->
++ eb_size);
++ atomic64_inc(&dmc->
++ eio_stats.
++ readfill);
++ atomic64_inc(&dmc->
++ eio_stats.
++ writecache);
++ err =
++ eio_io_async_bvec
++ (dmc,
++ &job->
++ job_io_regions.
++ cache, WRITE,
++ iebio->eb_bv,
++ iebio->eb_nbvec,
++ eio_io_callback,
++ job, 0);
++ }
++ if (err) {
++ pr_err
++ ("eio_do_readfill: IO submission failed, block %llu",
++ EIO_DBN_GET(dmc,
++ index));
++ spin_lock_irqsave(&dmc->
++ cache_sets
++ [iebio->
++ eb_cacheset].
++ cs_lock,
++ flags);
++ EIO_CACHE_STATE_SET(dmc,
++ iebio->
++ eb_index,
++ INVALID);
++ spin_unlock_irqrestore
++ (&dmc->
++ cache_sets[iebio->
++ eb_cacheset].
++ cs_lock, flags);
++ atomic64_dec_if_positive
++ (&dmc->eio_stats.
++ cached_blocks);
++ eb_endio(iebio, err);
++
++ if (job) {
++ eio_free_cache_job
++ (job);
++ job = NULL;
++ }
++ }
++ } else
++ if (EIO_CACHE_STATE_GET(dmc, index)
++ == ALREADY_DIRTY) {
++
++ spin_unlock_irqrestore(&dmc->
++ cache_sets
++ [iebio->
++ eb_cacheset].
++ cs_lock,
++ flags);
++
++ /*
++ * DIRTY block handling:
++ * Read the dirty data from the cache block to update
++ * the data buffer already read from the disk
++ */
++ job =
++ eio_new_job(dmc, iebio,
++ iebio->
++ eb_index);
++ if (unlikely(job == NULL))
++ err = -ENOMEM;
++ else {
++ job->action = READCACHE;
++ SECTOR_STATS(dmc->
++ eio_stats.
++ ssd_reads,
++ iebio->
++ eb_size);
++ atomic64_inc(&dmc->
++ eio_stats.
++ readcache);
++ err =
++ eio_io_async_bvec
++ (dmc,
++ &job->
++ job_io_regions.
++ cache, READ,
++ iebio->eb_bv,
++ iebio->eb_nbvec,
++ eio_io_callback,
++ job, 0);
++ }
++
++ if (err) {
++ pr_err
++ ("eio_do_readfill: dirty block read IO submission failed, block %llu",
++ EIO_DBN_GET(dmc,
++ index));
++ /* can't invalidate the DIRTY block, just return error */
++ eb_endio(iebio, err);
++ if (job) {
++ eio_free_cache_job
++ (job);
++ job = NULL;
++ }
++ }
++ } else
++ if ((EIO_CACHE_STATE_GET(dmc, index)
++ & (VALID | CACHEREADINPROG))
++ == (VALID | CACHEREADINPROG)) {
++ /*turn off the cache read in prog flag
++ don't need to write the cache block*/
++ CTRACE("eio_do_readfill:3\n");
++ EIO_CACHE_STATE_OFF(dmc, index,
++ BLOCK_IO_INPROG);
++ spin_unlock_irqrestore(&dmc->
++ cache_sets
++ [iebio->
++ eb_cacheset].
++ cs_lock,
++ flags);
++ eb_endio(iebio, 0);
++ iebio = NULL;
++ } else {
++ panic("Unknown condition");
++ spin_unlock_irqrestore(&dmc->
++ cache_sets
++ [iebio->
++ eb_cacheset].
++ cs_lock,
++ flags);
++ }
++ }
++ iebio = next;
++ } while (iebio);
++ eb_endio(ebio, 0);
++ ebio = NULL;
++ eio_free_cache_job(job);
++ }
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ }
++ dmc->readfill_in_prog = 0;
++out:
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ atomic64_inc(&dmc->eio_stats.ssd_readfill_unplugs);
++ eio_unplug_cache_device(dmc);
++}
++
++/*
++ * Map a block from the source device to a block in the cache device.
++ */
++static u_int32_t hash_block(struct cache_c *dmc, sector_t dbn)
++{
++ u_int32_t set_number;
++
++ set_number = eio_hash_block(dmc, dbn);
++ return set_number;
++}
++
++static void
++find_valid_dbn(struct cache_c *dmc, sector_t dbn,
++ index_t start_index, index_t *index)
++{
++ index_t i;
++ index_t end_index = start_index + dmc->assoc;
++
++ for (i = start_index; i < end_index; i++) {
++ if ((EIO_CACHE_STATE_GET(dmc, i) & VALID)
++ && EIO_DBN_GET(dmc, i) == dbn) {
++ *index = i;
++ if ((EIO_CACHE_STATE_GET(dmc, i) & BLOCK_IO_INPROG) ==
++ 0)
++ eio_policy_reclaim_lru_movetail(dmc, i,
++ dmc->
++ policy_ops);
++ return;
++ }
++ }
++ *index = -1;
++}
++
++static index_t find_invalid_dbn(struct cache_c *dmc, index_t start_index)
++{
++ index_t i;
++ index_t end_index = start_index + dmc->assoc;
++
++ /* Find INVALID slot that we can reuse */
++ for (i = start_index; i < end_index; i++) {
++ if (EIO_CACHE_STATE_GET(dmc, i) == INVALID) {
++ eio_policy_reclaim_lru_movetail(dmc, i,
++ dmc->policy_ops);
++ return i;
++ }
++ }
++ return -1;
++}
++
++/* Search for a slot that we can reclaim */
++static void
++find_reclaim_dbn(struct cache_c *dmc, index_t start_index, index_t *index)
++{
++ eio_find_reclaim_dbn(dmc->policy_ops, start_index, index);
++}
++
++void eio_set_warm_boot(void)
++{
++ eio_force_warm_boot = 1;
++ return;
++}
++
++/*
++ * dbn is the starting sector.
++ */
++static int
++eio_lookup(struct cache_c *dmc, struct eio_bio *ebio, index_t *index)
++{
++ sector_t dbn = EIO_ROUND_SECTOR(dmc, ebio->eb_sector);
++ u_int32_t set_number;
++ index_t invalid, oldest_clean = -1;
++ index_t start_index;
++
++ /*ASK it is assumed that the lookup is being done for a single block*/
++ set_number = hash_block(dmc, dbn);
++ start_index = dmc->assoc * set_number;
++ find_valid_dbn(dmc, dbn, start_index, index);
++ if (*index >= 0)
++ /* We found the exact range of blocks we are looking for */
++ return VALID;
++
++ invalid = find_invalid_dbn(dmc, start_index);
++ if (invalid == -1)
++ /* We didn't find an invalid entry, search for oldest valid entry */
++ find_reclaim_dbn(dmc, start_index, &oldest_clean);
++ /*
++ * Cache miss :
++ * We can't choose an entry marked INPROG, but choose the oldest
++ * INVALID or the oldest VALID entry.
++ */
++ *index = start_index + dmc->assoc;
++ if (invalid != -1) {
++ *index = invalid;
++ return INVALID;
++ } else if (oldest_clean != -1) {
++ *index = oldest_clean;
++ return VALID;
++ }
++ return -1;
++}
++
++/* Do metadata update for a set */
++static void eio_do_mdupdate(struct work_struct *work)
++{
++ struct mdupdate_request *mdreq;
++ struct cache_set *set;
++ struct cache_c *dmc;
++ unsigned long flags;
++ index_t i;
++ index_t start_index;
++ index_t end_index;
++ index_t min_index;
++ index_t max_index;
++ struct flash_cacheblock *md_blocks;
++ struct eio_bio *ebio;
++ u_int8_t cstate;
++ struct eio_io_region region;
++ unsigned pindex;
++ int error, j;
++ index_t blk_index;
++ int k;
++ void *pg_virt_addr[2] = { NULL };
++ u_int8_t sector_bits[2] = { 0 };
++ int startbit, endbit;
++ int rw_flags = 0;
++
++ mdreq = container_of(work, struct mdupdate_request, work);
++ dmc = mdreq->dmc;
++ set = &dmc->cache_sets[mdreq->set];
++
++ mdreq->error = 0;
++ EIO_ASSERT(mdreq->mdblk_bvecs);
++
++ /*
++ * md_size = dmc->assoc * sizeof(struct flash_cacheblock);
++ * Currently, md_size is 8192 bytes, mdpage_count is 2 pages maximum.
++ */
++
++ EIO_ASSERT(mdreq->mdbvec_count && mdreq->mdbvec_count <= 2);
++ EIO_ASSERT((dmc->assoc == 512) || mdreq->mdbvec_count == 1);
++ for (k = 0; k < (int)mdreq->mdbvec_count; k++)
++ pg_virt_addr[k] = kmap(mdreq->mdblk_bvecs[k].bv_page);
++
++ spin_lock_irqsave(&set->cs_lock, flags);
++
++ start_index = mdreq->set * dmc->assoc;
++ end_index = start_index + dmc->assoc;
++
++ pindex = 0;
++ md_blocks = (struct flash_cacheblock *)pg_virt_addr[pindex];
++ j = MD_BLOCKS_PER_PAGE;
++
++ /* initialize the md blocks to write */
++ for (i = start_index; i < end_index; i++) {
++ cstate = EIO_CACHE_STATE_GET(dmc, i);
++ md_blocks->dbn = cpu_to_le64(EIO_DBN_GET(dmc, i));
++ if (cstate == ALREADY_DIRTY)
++ md_blocks->cache_state = cpu_to_le64((VALID | DIRTY));
++ else
++ md_blocks->cache_state = cpu_to_le64(INVALID);
++ md_blocks++;
++ j--;
++
++ if ((j == 0) && (++pindex < mdreq->mdbvec_count)) {
++ md_blocks =
++ (struct flash_cacheblock *)pg_virt_addr[pindex];
++ j = MD_BLOCKS_PER_PAGE;
++ }
++
++ }
++
++ /* Update the md blocks with the pending mdlist */
++ min_index = start_index;
++ max_index = start_index;
++
++ pindex = 0;
++ md_blocks = (struct flash_cacheblock *)pg_virt_addr[pindex];
++
++ ebio = mdreq->pending_mdlist;
++ while (ebio) {
++ EIO_ASSERT(EIO_CACHE_STATE_GET(dmc, ebio->eb_index) ==
++ DIRTY_INPROG);
++
++ blk_index = ebio->eb_index - start_index;
++ pindex = INDEX_TO_MD_PAGE(blk_index);
++ blk_index = INDEX_TO_MD_PAGE_OFFSET(blk_index);
++ sector_bits[pindex] |= (1 << INDEX_TO_MD_SECTOR(blk_index));
++
++ md_blocks = (struct flash_cacheblock *)pg_virt_addr[pindex];
++ md_blocks[blk_index].cache_state = (VALID | DIRTY);
++
++ if (min_index > ebio->eb_index)
++ min_index = ebio->eb_index;
++
++ if (max_index < ebio->eb_index)
++ max_index = ebio->eb_index;
++
++ ebio = ebio->eb_next;
++ }
++
++ /*
++ * Below code may be required when selective pages need to be
++ * submitted for metadata update. Currently avoiding the optimization
++ * for correctness validation.
++ */
++
++ /*
++ min_cboff = (min_index - start_index) / MD_BLOCKS_PER_CBLOCK(dmc);
++ max_cboff = (max_index - start_index) / MD_BLOCKS_PER_CBLOCK(dmc);
++ write_size = ((uint32_t)(max_cboff - min_cboff + 1)) << dmc->block_shift;
++ EIO_ASSERT(write_size && (write_size <= eio_to_sector(mdreq->md_size)));
++ */
++
++ /* Move the pending mdlist to inprog list */
++ mdreq->inprog_mdlist = mdreq->pending_mdlist;
++ mdreq->pending_mdlist = NULL;
++
++ spin_unlock_irqrestore(&set->cs_lock, flags);
++
++ for (k = 0; k < (int)mdreq->mdbvec_count; k++)
++ kunmap(mdreq->mdblk_bvecs[k].bv_page);
++
++ /*
++ * Initiate the I/O to SSD for on-disk md update.
++ * TBD. Optimize to write only the affected blocks
++ */
++
++ region.bdev = dmc->cache_dev->bdev;
++ /*region.sector = dmc->md_start_sect + INDEX_TO_MD_SECTOR(start_index) +
++ (min_cboff << dmc->block_shift); */
++
++ atomic_set(&mdreq->holdcount, 1);
++ for (i = 0; i < mdreq->mdbvec_count; i++) {
++ if (!sector_bits[i])
++ continue;
++ startbit = -1;
++ j = 0;
++ while (startbit == -1) {
++ if (sector_bits[i] & (1 << j))
++ startbit = j;
++ j++;
++ }
++ endbit = -1;
++ j = 7;
++ while (endbit == -1) {
++ if (sector_bits[i] & (1 << j))
++ endbit = j;
++ j--;
++ }
++ EIO_ASSERT(startbit <= endbit && startbit >= 0 && startbit <= 7 &&
++ endbit >= 0 && endbit <= 7);
++ EIO_ASSERT(dmc->assoc != 128 || endbit <= 3);
++ region.sector =
++ dmc->md_start_sect + INDEX_TO_MD_SECTOR(start_index) +
++ i * SECTORS_PER_PAGE + startbit;
++ region.count = endbit - startbit + 1;
++ mdreq->mdblk_bvecs[i].bv_offset = to_bytes(startbit);
++ mdreq->mdblk_bvecs[i].bv_len = to_bytes(region.count);
++
++ EIO_ASSERT(region.sector <=
++ (dmc->md_start_sect + INDEX_TO_MD_SECTOR(end_index)));
++ atomic64_inc(&dmc->eio_stats.md_ssd_writes);
++ SECTOR_STATS(dmc->eio_stats.ssd_writes, to_bytes(region.count));
++ atomic_inc(&mdreq->holdcount);
++
++ /*
++ * Set SYNC for making metadata
++ * writes as high priority.
++ */
++ rw_flags = WRITE | REQ_SYNC;
++ error = eio_io_async_bvec(dmc, &region, rw_flags,
++ &mdreq->mdblk_bvecs[i], 1,
++ eio_mdupdate_callback, work, 0);
++ if (error && !(mdreq->error))
++ mdreq->error = error;
++ }
++ if (atomic_dec_and_test(&mdreq->holdcount)) {
++ INIT_WORK(&mdreq->work, eio_post_mdupdate);
++ queue_work(dmc->mdupdate_q, &mdreq->work);
++ }
++}
++
++/* Callback function for ondisk metadata update */
++static void eio_mdupdate_callback(int error, void *context)
++{
++ struct work_struct *work = (struct work_struct *)context;
++ struct mdupdate_request *mdreq;
++
++ mdreq = container_of(work, struct mdupdate_request, work);
++ if (error && !(mdreq->error))
++ mdreq->error = error;
++ if (!atomic_dec_and_test(&mdreq->holdcount))
++ return;
++ INIT_WORK(&mdreq->work, eio_post_mdupdate);
++ queue_work(mdreq->dmc->mdupdate_q, &mdreq->work);
++}
++
++static void eio_post_mdupdate(struct work_struct *work)
++{
++ struct mdupdate_request *mdreq;
++ struct cache_set *set;
++ struct cache_c *dmc;
++ unsigned long flags;
++ struct eio_bio *ebio;
++ struct eio_bio *nebio;
++ int more_pending_mdupdates = 0;
++ int error;
++ index_t set_index;
++
++ mdreq = container_of(work, struct mdupdate_request, work);
++
++ dmc = mdreq->dmc;
++ EIO_ASSERT(dmc);
++ set_index = mdreq->set;
++ set = &dmc->cache_sets[set_index];
++ error = mdreq->error;
++
++ /* Update in-core cache metadata */
++
++ spin_lock_irqsave(&set->cs_lock, flags);
++
++ /*
++ * Update dirty inprog blocks.
++ * On error, convert them to INVALID
++ * On success, convert them to ALREADY_DIRTY
++ */
++ ebio = mdreq->inprog_mdlist;
++ while (ebio) {
++ EIO_ASSERT(EIO_CACHE_STATE_GET(dmc, ebio->eb_index) ==
++ DIRTY_INPROG);
++ if (unlikely(error)) {
++ EIO_CACHE_STATE_SET(dmc, ebio->eb_index, INVALID);
++ atomic64_dec_if_positive(&dmc->eio_stats.cached_blocks);
++ } else {
++ EIO_CACHE_STATE_SET(dmc, ebio->eb_index, ALREADY_DIRTY);
++ set->nr_dirty++;
++ atomic64_inc(&dmc->nr_dirty);
++ atomic64_inc(&dmc->eio_stats.md_write_dirty);
++ }
++ ebio = ebio->eb_next;
++ }
++
++ /*
++ * If there are more pending requests for md update,
++ * need to pick up those using the current mdreq.
++ */
++ if (mdreq->pending_mdlist)
++ more_pending_mdupdates = 1;
++ else
++ /* No request pending, we can free the mdreq */
++ set->mdreq = NULL;
++
++ /*
++ * After we unlock the set, we need to end the I/Os,
++ * which were processed as part of this md update
++ */
++
++ ebio = mdreq->inprog_mdlist;
++ mdreq->inprog_mdlist = NULL;
++
++ spin_unlock_irqrestore(&set->cs_lock, flags);
++
++ /* End the processed I/Os */
++ while (ebio) {
++ nebio = ebio->eb_next;
++ eb_endio(ebio, error);
++ ebio = nebio;
++ }
++
++ /*
++ * if dirty block was added
++ * 1. update the cache set lru list
++ * 2. check and initiate cleaning if thresholds are crossed
++ */
++ if (!error) {
++ eio_touch_set_lru(dmc, set_index);
++ eio_comply_dirty_thresholds(dmc, set_index);
++ }
++
++ if (more_pending_mdupdates) {
++ /*
++ * Schedule work to process the new
++ * pending mdupdate requests
++ */
++ INIT_WORK(&mdreq->work, eio_do_mdupdate);
++ queue_work(dmc->mdupdate_q, &mdreq->work);
++ } else {
++ /*
++ * No more pending mdupdates.
++ * Free the mdreq.
++ */
++ if (mdreq->mdblk_bvecs) {
++ eio_free_wb_bvecs(mdreq->mdblk_bvecs,
++ mdreq->mdbvec_count,
++ SECTORS_PER_PAGE);
++ kfree(mdreq->mdblk_bvecs);
++ }
++
++ kfree(mdreq);
++ }
++}
++
++/* Enqueue metadata update for marking dirty blocks on-disk/in-core */
++static void eio_enq_mdupdate(struct bio_container *bc)
++{
++ unsigned long flags = 0;
++ index_t set_index;
++ struct eio_bio *ebio;
++ struct cache_c *dmc = bc->bc_dmc;
++ struct cache_set *set = NULL;
++ struct mdupdate_request *mdreq;
++ int do_schedule;
++
++ ebio = bc->bc_mdlist;
++ set_index = -1;
++ do_schedule = 0;
++ while (ebio) {
++ if (ebio->eb_cacheset != set_index) {
++ set_index = ebio->eb_cacheset;
++ set = &dmc->cache_sets[set_index];
++ spin_lock_irqsave(&set->cs_lock, flags);
++ }
++ EIO_ASSERT(ebio->eb_cacheset == set_index);
++
++ bc->bc_mdlist = ebio->eb_next;
++
++ if (!set->mdreq) {
++ /* Pick up one mdreq from bc */
++ mdreq = bc->mdreqs;
++ EIO_ASSERT(mdreq != NULL);
++ bc->mdreqs = bc->mdreqs->next;
++ mdreq->next = NULL;
++ mdreq->pending_mdlist = ebio;
++ mdreq->dmc = dmc;
++ mdreq->set = set_index;
++ set->mdreq = mdreq;
++ ebio->eb_next = NULL;
++ do_schedule = 1;
++ } else {
++ mdreq = set->mdreq;
++ EIO_ASSERT(mdreq != NULL);
++ ebio->eb_next = mdreq->pending_mdlist;
++ mdreq->pending_mdlist = ebio;
++ }
++
++ ebio = bc->bc_mdlist;
++ if (!ebio || ebio->eb_cacheset != set_index) {
++ spin_unlock_irqrestore(&set->cs_lock, flags);
++ if (do_schedule) {
++ INIT_WORK(&mdreq->work, eio_do_mdupdate);
++ queue_work(dmc->mdupdate_q, &mdreq->work);
++ do_schedule = 0;
++ }
++ }
++ }
++
++ EIO_ASSERT(bc->bc_mdlist == NULL);
++}
++
++/* Kick-off a cache metadata update for marking the blocks dirty */
++void eio_md_write(struct kcached_job *job)
++{
++ struct eio_bio *ebio = job->ebio;
++ struct eio_bio *nebio;
++ struct eio_bio *pebio;
++ struct bio_container *bc = ebio->eb_bc;
++ unsigned long flags;
++ int enqueue = 0;
++
++ /*
++ * ebios are stored in ascending order of cache sets.
++ */
++
++ spin_lock_irqsave(&bc->bc_lock, flags);
++ EIO_ASSERT(bc->bc_mdwait > 0);
++ nebio = bc->bc_mdlist;
++ pebio = NULL;
++ while (nebio) {
++ if (nebio->eb_cacheset > ebio->eb_cacheset)
++ break;
++ pebio = nebio;
++ nebio = nebio->eb_next;
++ }
++ ebio->eb_next = nebio;
++ if (!pebio)
++ bc->bc_mdlist = ebio;
++ else
++ pebio->eb_next = ebio;
++ bc->bc_mdwait--;
++ if (bc->bc_mdwait == 0)
++ enqueue = 1;
++ spin_unlock_irqrestore(&bc->bc_lock, flags);
++
++ eio_free_cache_job(job);
++
++ if (enqueue)
++ eio_enq_mdupdate(bc);
++}
++
++/* Ensure cache level dirty thresholds compliance. If required, trigger cache-wide clean */
++static void eio_check_dirty_cache_thresholds(struct cache_c *dmc)
++{
++ if (DIRTY_CACHE_THRESHOLD_CROSSED(dmc)) {
++ int64_t required_cleans;
++ int64_t enqueued_cleans;
++ u_int64_t set_time;
++ index_t set_index;
++ unsigned long flags;
++
++ spin_lock_irqsave(&dmc->clean_sl, flags);
++ if (atomic64_read(&dmc->clean_pendings)
++ || dmc->clean_excess_dirty) {
++ /* Already excess dirty block cleaning is in progress */
++ spin_unlock_irqrestore(&dmc->clean_sl, flags);
++ return;
++ }
++ dmc->clean_excess_dirty = 1;
++ spin_unlock_irqrestore(&dmc->clean_sl, flags);
++
++ /* Clean needs to be triggered on the cache */
++ required_cleans = atomic64_read(&dmc->nr_dirty) -
++ (EIO_DIV((dmc->sysctl_active.dirty_low_threshold * dmc->size),
++ 100));
++ enqueued_cleans = 0;
++
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock, flags);
++ do {
++ lru_rem_head(dmc->dirty_set_lru, &set_index, &set_time);
++ if (set_index == LRU_NULL)
++ break;
++
++ enqueued_cleans += dmc->cache_sets[set_index].nr_dirty;
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock, flags);
++ eio_addto_cleanq(dmc, set_index, 1);
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock, flags);
++ } while (enqueued_cleans <= required_cleans);
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock, flags);
++ spin_lock_irqsave(&dmc->clean_sl, flags);
++ dmc->clean_excess_dirty = 0;
++ spin_unlock_irqrestore(&dmc->clean_sl, flags);
++ }
++}
++
++/* Ensure set level dirty thresholds compliance. If required, trigger set clean */
++static void eio_check_dirty_set_thresholds(struct cache_c *dmc, index_t set)
++{
++ if (DIRTY_SET_THRESHOLD_CROSSED(dmc, set)) {
++ eio_addto_cleanq(dmc, set, 0);
++ return;
++ }
++}
++
++/* Ensure various cache thresholds compliance. If required trigger clean */
++void eio_comply_dirty_thresholds(struct cache_c *dmc, index_t set)
++{
++ /*
++ * 1. Don't trigger new cleanings if
++ * - cache is not wb
++ * - autoclean threshold is crossed
++ * - fast remove in progress is set
++ * - cache is in failed mode.
++ * 2. Initiate set-wide clean, if set level dirty threshold is crossed
++ * 3. Initiate cache-wide clean, if cache level dirty threshold is crossed
++ */
++
++ if (unlikely(CACHE_FAILED_IS_SET(dmc))) {
++ pr_debug
++ ("eio_comply_dirty_thresholds: Cache %s is in failed mode.\n",
++ dmc->cache_name);
++ return;
++ }
++
++ if (AUTOCLEAN_THRESHOLD_CROSSED(dmc) || (dmc->mode != CACHE_MODE_WB))
++ return;
++
++ if (set != -1)
++ eio_check_dirty_set_thresholds(dmc, set);
++ eio_check_dirty_cache_thresholds(dmc);
++}
++
++/* Do read from cache */
++static void
++eio_cached_read(struct cache_c *dmc, struct eio_bio *ebio, int rw_flags)
++{
++ struct kcached_job *job;
++ index_t index = ebio->eb_index;
++ int err = 0;
++
++ job = eio_new_job(dmc, ebio, index);
++
++ if (unlikely(job == NULL))
++ err = -ENOMEM;
++ else {
++ job->action = READCACHE; /* Fetch data from cache */
++ atomic_inc(&dmc->nr_jobs);
++
++ SECTOR_STATS(dmc->eio_stats.read_hits, ebio->eb_size);
++ SECTOR_STATS(dmc->eio_stats.ssd_reads, ebio->eb_size);
++ atomic64_inc(&dmc->eio_stats.readcache);
++ err =
++ eio_io_async_bvec(dmc, &job->job_io_regions.cache, rw_flags,
++ ebio->eb_bv, ebio->eb_nbvec,
++ eio_io_callback, job, 0);
++
++ }
++ if (err) {
++ unsigned long flags;
++ pr_err("eio_cached_read: IO submission failed, block %llu",
++ EIO_DBN_GET(dmc, index));
++ spin_lock_irqsave(&dmc->cache_sets[ebio->eb_cacheset].cs_lock,
++ flags);
++ /*
++ * For already DIRTY block, invalidation is too costly, skip it.
++ * For others, mark the block as INVALID and return error.
++ */
++ if (EIO_CACHE_STATE_GET(dmc, ebio->eb_index) != ALREADY_DIRTY) {
++ EIO_CACHE_STATE_SET(dmc, ebio->eb_index, INVALID);
++ atomic64_dec_if_positive(&dmc->eio_stats.cached_blocks);
++ }
++ spin_unlock_irqrestore(&dmc->cache_sets[ebio->eb_cacheset].
++ cs_lock, flags);
++ eb_endio(ebio, err);
++ ebio = NULL;
++ if (job) {
++ job->ebio = NULL;
++ eio_free_cache_job(job);
++ job = NULL;
++ }
++ }
++}
++
++/*
++ * Invalidate any colliding blocks if they are !BUSY and !DIRTY. In BUSY case,
++ * we need to wait until the underlying IO is finished, and then proceed with
++ * the invalidation, so a QUEUED flag is added.
++ */
++static int
++eio_inval_block_set_range(struct cache_c *dmc, int set, sector_t iosector,
++ unsigned iosize, int multiblk)
++{
++ int start_index, end_index, i;
++ sector_t endsector = iosector + eio_to_sector(iosize);
++
++ start_index = dmc->assoc * set;
++ end_index = start_index + dmc->assoc;
++ for (i = start_index; i < end_index; i++) {
++ sector_t start_dbn;
++ sector_t end_dbn;
++
++ if (EIO_CACHE_STATE_GET(dmc, i) & INVALID)
++ continue;
++ start_dbn = EIO_DBN_GET(dmc, i);
++ end_dbn = start_dbn + dmc->block_size;
++
++ if (!(endsector <= start_dbn || iosector >= end_dbn)) {
++
++ if (!
++ (EIO_CACHE_STATE_GET(dmc, i) &
++ (BLOCK_IO_INPROG | DIRTY | QUEUED))) {
++ EIO_CACHE_STATE_SET(dmc, i, INVALID);
++ atomic64_dec_if_positive(&dmc->eio_stats.
++ cached_blocks);
++ if (multiblk)
++ continue;
++ return 0;
++ }
++
++ /* Skip queued flag for DIRTY(inprog or otherwise) blocks. */
++ if (!(EIO_CACHE_STATE_GET(dmc, i) & (DIRTY | QUEUED)))
++ /* BLOCK_IO_INPROG is set. Set QUEUED flag */
++ EIO_CACHE_STATE_ON(dmc, i, QUEUED);
++
++ if (!multiblk)
++ return 1;
++ }
++ }
++ return 0;
++}
++
++int
++eio_invalidate_sanity_check(struct cache_c *dmc, u_int64_t iosector,
++ u_int64_t *num_sectors)
++{
++ u_int64_t disk_size;
++
++ /*
++ * Sanity check the arguements
++ */
++ if (unlikely(*num_sectors == 0)) {
++ pr_info
++ ("invaldate_sector_range: nothing to do because number of sectors specified is zero");
++ return -EINVAL;
++ }
++
++ disk_size = eio_to_sector(eio_get_device_size(dmc->disk_dev));
++ if (iosector >= disk_size) {
++ pr_err
++ ("eio_inval_range: nothing to do because starting sector is past last sector (%lu > %lu)",
++ (long unsigned int)iosector, (long unsigned int)disk_size);
++ return -EINVAL;
++ }
++
++ if ((iosector + (*num_sectors)) > disk_size) {
++ pr_info
++ ("eio_inval_range: trimming range because there are less sectors to invalidate than requested. (%lu < %lu)",
++ (long unsigned int)(disk_size - iosector),
++ (long unsigned int)*num_sectors);
++ *num_sectors = (disk_size - iosector);
++ }
++
++ return 0;
++}
++
++void eio_inval_range(struct cache_c *dmc, sector_t iosector, unsigned iosize)
++{
++ u_int32_t bset;
++ sector_t snum;
++ sector_t snext;
++ unsigned ioinset;
++ unsigned long flags;
++ int totalsshift = dmc->block_shift + dmc->consecutive_shift;
++
++ snum = iosector;
++ while (iosize) {
++ bset = hash_block(dmc, snum);
++ snext = ((snum >> totalsshift) + 1) << totalsshift;
++ ioinset = (unsigned)to_bytes(snext - snum);
++ if (ioinset > iosize)
++ ioinset = iosize;
++ spin_lock_irqsave(&dmc->cache_sets[bset].cs_lock, flags);
++ eio_inval_block_set_range(dmc, bset, snum, ioinset, 1);
++ spin_unlock_irqrestore(&dmc->cache_sets[bset].cs_lock, flags);
++ snum = snext;
++ iosize -= ioinset;
++ }
++}
++
++/*
++ * Invalidates all cached blocks without waiting for them to complete
++ * Should be called with incoming IO suspended
++ */
++int eio_invalidate_cache(struct cache_c *dmc)
++{
++ u_int64_t i = 0;
++ unsigned long flags = 0;
++ sector_t disk_dev_size = to_bytes(eio_get_device_size(dmc->disk_dev));
++
++ /* invalidate the whole cache */
++ for (i = 0; i < (dmc->size >> dmc->consecutive_shift); i++) {
++ spin_lock_irqsave(&dmc->cache_sets[i].cs_lock, flags);
++ /* TBD. Apply proper fix for the cast to disk_dev_size */
++ (void)eio_inval_block_set_range(dmc, (int)i, 0,
++ (unsigned)disk_dev_size, 0);
++ spin_unlock_irqrestore(&dmc->cache_sets[i].cs_lock, flags);
++ } /* end - for all cachesets (i) */
++
++ return 0; /* i suspect we may need to return different statuses in the future */
++} /* eio_invalidate_cache */
++
++static int eio_inval_block(struct cache_c *dmc, sector_t iosector)
++{
++ u_int32_t bset;
++ int queued;
++
++ /*Chop lower bits of iosector*/
++ iosector = EIO_ROUND_SECTOR(dmc, iosector);
++ bset = hash_block(dmc, iosector);
++ queued = eio_inval_block_set_range(dmc, bset, iosector,
++ (unsigned)to_bytes(dmc->block_size),
++ 0);
++
++ return queued;
++}
++
++/* Serving write I/Os, that involves both SSD and HDD */
++static int eio_uncached_write(struct cache_c *dmc, struct eio_bio *ebio)
++{
++ struct kcached_job *job;
++ int err = 0;
++ index_t index = ebio->eb_index;
++ unsigned long flags = 0;
++ u_int8_t cstate;
++
++ if (index == -1) {
++ /*
++ * No work, if block is not allocated.
++ * Ensure, invalidation of the block at the end
++ */
++ ebio->eb_iotype |= EB_INVAL;
++ return 0;
++ }
++
++ spin_lock_irqsave(&dmc->cache_sets[ebio->eb_cacheset].cs_lock, flags);
++ cstate = EIO_CACHE_STATE_GET(dmc, index);
++ EIO_ASSERT(cstate & (DIRTY | CACHEWRITEINPROG));
++ if (cstate == ALREADY_DIRTY) {
++ /*
++ * Treat the dirty block cache write failure as
++ * I/O failure for the entire I/O
++ * TBD
++ * Can we live without this restriction
++ */
++ ebio->eb_iotype = EB_MAIN_IO;
++
++ /*
++ * We don't set inprog flag on dirty block.
++ * In lieu of the inprog flag, we are using the
++ * eb_holdcount for dirty block, so that the
++ * endio can be called, only when the write to disk
++ * and the write to cache both complete for the ebio
++ */
++ atomic_inc(&ebio->eb_holdcount);
++ } else
++ /* ensure DISKWRITEINPROG for uncached write on non-DIRTY blocks */
++ EIO_CACHE_STATE_ON(dmc, index, DISKWRITEINPROG);
++
++ spin_unlock_irqrestore(&dmc->cache_sets[ebio->eb_cacheset].cs_lock,
++ flags);
++
++ job = eio_new_job(dmc, ebio, index);
++ if (unlikely(job == NULL))
++ err = -ENOMEM;
++ else {
++ job->action = WRITECACHE;
++ SECTOR_STATS(dmc->eio_stats.ssd_writes, ebio->eb_size);
++ atomic64_inc(&dmc->eio_stats.writecache);
++ err = eio_io_async_bvec(dmc, &job->job_io_regions.cache, WRITE,
++ ebio->eb_bv, ebio->eb_nbvec,
++ eio_io_callback, job, 0);
++ }
++
++ if (err) {
++ pr_err("eio_uncached_write: IO submission failed, block %llu",
++ EIO_DBN_GET(dmc, index));
++ spin_lock_irqsave(&dmc->cache_sets[ebio->eb_cacheset].cs_lock,
++ flags);
++ if (EIO_CACHE_STATE_GET(dmc, ebio->eb_index) == ALREADY_DIRTY)
++ /*
++ * Treat I/O failure on a DIRTY block as failure of entire I/O.
++ * TBD
++ * Can do better error handling by invalidation of the dirty
++ * block, if the cache block write failed, but disk write succeeded
++ */
++ ebio->eb_bc->bc_error = err;
++ else {
++ /* Mark the block as INVALID for non-DIRTY block. */
++ EIO_CACHE_STATE_SET(dmc, ebio->eb_index, INVALID);
++ atomic64_dec_if_positive(&dmc->eio_stats.cached_blocks);
++ /* Set the INVAL flag to ensure block is marked invalid at the end */
++ ebio->eb_iotype |= EB_INVAL;
++ ebio->eb_index = -1;
++ }
++ spin_unlock_irqrestore(&dmc->cache_sets[ebio->eb_cacheset].
++ cs_lock, flags);
++ if (job) {
++ job->ebio = NULL;
++ eio_free_cache_job(job);
++ job = NULL;
++ }
++ }
++
++ return err;
++}
++
++/* Serving write I/Os that can be fulfilled just by SSD */
++static int
++eio_cached_write(struct cache_c *dmc, struct eio_bio *ebio, int rw_flags)
++{
++ struct kcached_job *job;
++ int err = 0;
++ index_t index = ebio->eb_index;
++ unsigned long flags = 0;
++ u_int8_t cstate;
++
++ /*
++ * WRITE (I->DV)
++ * WRITE (V->DV)
++ * WRITE (V1->DV2)
++ * WRITE (DV->DV)
++ */
++
++ /* Possible only in writeback caching mode */
++ EIO_ASSERT(dmc->mode == CACHE_MODE_WB);
++
++ /*
++ * TBD
++ * Possibly don't need the spinlock-unlock here
++ */
++ spin_lock_irqsave(&dmc->cache_sets[ebio->eb_cacheset].cs_lock, flags);
++ cstate = EIO_CACHE_STATE_GET(dmc, index);
++ if (!(cstate & DIRTY)) {
++ EIO_ASSERT(cstate & CACHEWRITEINPROG);
++ /* make sure the block is marked DIRTY inprogress */
++ EIO_CACHE_STATE_SET(dmc, index, DIRTY_INPROG);
++ }
++ spin_unlock_irqrestore(&dmc->cache_sets[ebio->eb_cacheset].cs_lock,
++ flags);
++
++ job = eio_new_job(dmc, ebio, index);
++ if (unlikely(job == NULL))
++ err = -ENOMEM;
++ else {
++ job->action = WRITECACHE;
++
++ SECTOR_STATS(dmc->eio_stats.ssd_writes, ebio->eb_size);
++ atomic64_inc(&dmc->eio_stats.writecache);
++ EIO_ASSERT((rw_flags & 1) == WRITE);
++ err =
++ eio_io_async_bvec(dmc, &job->job_io_regions.cache, rw_flags,
++ ebio->eb_bv, ebio->eb_nbvec,
++ eio_io_callback, job, 0);
++
++ }
++
++ if (err) {
++ pr_err("eio_cached_write: IO submission failed, block %llu",
++ EIO_DBN_GET(dmc, index));
++ spin_lock_irqsave(&dmc->cache_sets[ebio->eb_cacheset].cs_lock,
++ flags);
++ cstate = EIO_CACHE_STATE_GET(dmc, index);
++ if (cstate == DIRTY_INPROG) {
++ /* A DIRTY(inprog) block should be invalidated on error */
++ EIO_CACHE_STATE_SET(dmc, ebio->eb_index, INVALID);
++ atomic64_dec_if_positive(&dmc->eio_stats.cached_blocks);
++ } else
++ /* An already DIRTY block don't have an option but just return error. */
++ EIO_ASSERT(cstate == ALREADY_DIRTY);
++ spin_unlock_irqrestore(&dmc->cache_sets[ebio->eb_cacheset].
++ cs_lock, flags);
++ eb_endio(ebio, err);
++ ebio = NULL;
++ if (job) {
++ job->ebio = NULL;
++ eio_free_cache_job(job);
++ job = NULL;
++ }
++ }
++
++ return err;
++}
++
++static struct eio_bio *eio_new_ebio(struct cache_c *dmc, struct bio *bio,
++ unsigned *presidual_biovec, sector_t snum,
++ int iosize, struct bio_container *bc,
++ int iotype)
++{
++ struct eio_bio *ebio;
++ int residual_biovec = *presidual_biovec;
++ int numbvecs = 0;
++ int ios;
++
++ if (residual_biovec) {
++ int bvecindex = bio->bi_idx;
++ int rbvindex;
++
++ /* Calculate the number of bvecs required */
++ ios = iosize;
++ while (ios > 0) {
++ int len;
++
++ if (ios == iosize)
++ len =
++ bio->bi_io_vec[bvecindex].bv_len -
++ residual_biovec;
++ else
++ len = bio->bi_io_vec[bvecindex].bv_len;
++
++ numbvecs++;
++ if (len > ios)
++ len = ios;
++ ios -= len;
++ bvecindex++;
++ }
++ ebio =
++ kmalloc(sizeof(struct eio_bio) +
++ numbvecs * sizeof(struct bio_vec), GFP_NOWAIT);
++
++ if (!ebio)
++ return ERR_PTR(-ENOMEM);
++
++ rbvindex = 0;
++ ios = iosize;
++ while (ios > 0) {
++ ebio->eb_rbv[rbvindex].bv_page =
++ bio->bi_io_vec[bio->bi_idx].bv_page;
++ ebio->eb_rbv[rbvindex].bv_offset =
++ bio->bi_io_vec[bio->bi_idx].bv_offset +
++ residual_biovec;
++ ebio->eb_rbv[rbvindex].bv_len =
++ bio->bi_io_vec[bio->bi_idx].bv_len -
++ residual_biovec;
++ if (ebio->eb_rbv[rbvindex].bv_len > (unsigned)ios) {
++ residual_biovec += ios;
++ ebio->eb_rbv[rbvindex].bv_len = ios;
++ } else {
++ residual_biovec = 0;
++ bio->bi_idx++;
++ }
++ ios -= ebio->eb_rbv[rbvindex].bv_len;
++ rbvindex++;
++ }
++ EIO_ASSERT(rbvindex == numbvecs);
++ ebio->eb_bv = ebio->eb_rbv;
++ } else {
++ ebio = kmalloc(sizeof(struct eio_bio), GFP_NOWAIT);
++
++ if (!ebio)
++ return ERR_PTR(-ENOMEM);
++ ebio->eb_bv = bio->bi_io_vec + bio->bi_idx;
++ ios = iosize;
++ while (ios > 0) {
++ numbvecs++;
++ if ((unsigned)ios < bio->bi_io_vec[bio->bi_idx].bv_len) {
++ residual_biovec = ios;
++ ios = 0;
++ } else {
++ ios -= bio->bi_io_vec[bio->bi_idx].bv_len;
++ bio->bi_idx++;
++ }
++ }
++ }
++ EIO_ASSERT(ios == 0);
++ EIO_ASSERT(numbvecs != 0);
++ *presidual_biovec = residual_biovec;
++
++ ebio->eb_sector = snum;
++ ebio->eb_cacheset = hash_block(dmc, snum);
++ ebio->eb_size = iosize;
++ ebio->eb_dir = bio_data_dir(bio);
++ ebio->eb_next = NULL;
++ ebio->eb_index = -1;
++ ebio->eb_iotype = iotype;
++ ebio->eb_nbvec = numbvecs;
++
++ bc_addfb(bc, ebio);
++
++ /* Always set the holdcount for eb to 1, to begin with. */
++ atomic_set(&ebio->eb_holdcount, 1);
++
++ return ebio;
++}
++
++/* Issues HDD I/O */
++static void
++eio_disk_io(struct cache_c *dmc, struct bio *bio,
++ struct eio_bio *anchored_bios, struct bio_container *bc,
++ int force_inval)
++{
++ struct eio_bio *ebio;
++ struct kcached_job *job;
++ int residual_biovec = 0;
++ int error = 0;
++
++ /*disk io happens on whole bio. Reset bi_idx*/
++ bio->bi_idx = 0;
++ ebio =
++ eio_new_ebio(dmc, bio, &residual_biovec, bio->bi_sector,
++ bio->bi_size, bc, EB_MAIN_IO);
++
++ if (unlikely(IS_ERR(ebio))) {
++ bc->bc_error = error = PTR_ERR(ebio);
++ ebio = NULL;
++ goto errout;
++ }
++
++ if (force_inval)
++ ebio->eb_iotype |= EB_INVAL;
++ ebio->eb_next = anchored_bios; /*Anchor the ebio list to this super bio*/
++ job = eio_new_job(dmc, ebio, -1);
++
++ if (unlikely(job == NULL)) {
++ error = -ENOMEM;
++ goto errout;
++ }
++ atomic_inc(&dmc->nr_jobs);
++ if (ebio->eb_dir == READ) {
++ job->action = READDISK;
++ SECTOR_STATS(dmc->eio_stats.disk_reads, bio->bi_size);
++ atomic64_inc(&dmc->eio_stats.readdisk);
++ } else {
++ job->action = WRITEDISK;
++ SECTOR_STATS(dmc->eio_stats.disk_writes, bio->bi_size);
++ atomic64_inc(&dmc->eio_stats.writedisk);
++ }
++
++ /*
++ * Pass the original bio flags as is, while doing
++ * read / write to HDD.
++ */
++ VERIFY_BIO_FLAGS(ebio);
++ error = eio_io_async_bvec(dmc, &job->job_io_regions.disk,
++ GET_BIO_FLAGS(ebio),
++ ebio->eb_bv, ebio->eb_nbvec,
++ eio_io_callback, job, 1);
++
++ if (error) {
++ job->ebio = NULL;
++ eio_free_cache_job(job);
++ goto errout;
++ }
++ return;
++
++errout:
++ eio_inval_range(dmc, bio->bi_sector, bio->bi_size);
++ eio_flag_abios(dmc, anchored_bios, error);
++
++ if (ebio)
++ eb_endio(ebio, error);
++ return;
++}
++
++/*Given a sector number and biosize, returns cache io size*/
++static unsigned int
++eio_get_iosize(struct cache_c *dmc, sector_t snum, unsigned int biosize)
++{
++ unsigned int iosize;
++ unsigned int swithinblock = snum & (dmc->block_size - 1);
++
++ /*Check whether io starts at a cache block boundary*/
++ if (swithinblock)
++ iosize = (unsigned int)to_bytes(dmc->block_size - swithinblock);
++ else
++ iosize = (unsigned int)to_bytes(dmc->block_size);
++ if (iosize > biosize)
++ iosize = biosize;
++ return iosize;
++}
++
++/* Insert a new set sequence in sorted order to existing set sequence list */
++static int
++insert_set_seq(struct set_seq **seq_list, index_t first_set, index_t last_set)
++{
++ struct set_seq *cur_seq = NULL;
++ struct set_seq *prev_seq = NULL;
++ struct set_seq *new_seq = NULL;
++
++ EIO_ASSERT((first_set != -1) && (last_set != -1)
++ && (last_set >= first_set));
++
++ for (cur_seq = *seq_list; cur_seq;
++ prev_seq = cur_seq, cur_seq = cur_seq->next) {
++ if (first_set > cur_seq->last_set)
++ /* go for the next seq in the sorted seq list */
++ continue;
++
++ if (last_set < cur_seq->first_set)
++ /* break here to insert the new seq to seq list at this point */
++ break;
++
++ /*
++ * There is an overlap of the new seq with the current seq.
++ * Adjust the first_set field of the current seq to consume
++ * the overlap.
++ */
++ if (first_set < cur_seq->first_set)
++ cur_seq->first_set = first_set;
++
++ if (last_set <= cur_seq->last_set)
++ /* The current seq now fully encompasses the first and last sets */
++ return 0;
++
++ /* Increment the first set so as to start from, where the current seq left */
++ first_set = cur_seq->last_set + 1;
++ }
++
++ new_seq = kmalloc(sizeof(struct set_seq), GFP_NOWAIT);
++ if (new_seq == NULL)
++ return -ENOMEM;
++ new_seq->first_set = first_set;
++ new_seq->last_set = last_set;
++ if (prev_seq) {
++ new_seq->next = prev_seq->next;
++ prev_seq->next = new_seq;
++ } else {
++ new_seq->next = *seq_list;
++ *seq_list = new_seq;
++ }
++
++ return 0;
++}
++
++/* Acquire read/shared lock for the sets covering the entire I/O range */
++static int eio_acquire_set_locks(struct cache_c *dmc, struct bio_container *bc)
++{
++ struct bio *bio = bc->bc_bio;
++ sector_t round_sector;
++ sector_t end_sector;
++ sector_t set_size;
++ index_t cur_set;
++ index_t first_set;
++ index_t last_set;
++ index_t i;
++ struct set_seq *cur_seq;
++ struct set_seq *next_seq;
++ int error;
++
++ /*
++ * Find first set using start offset of the I/O and lock it.
++ * Find next sets by adding the set offsets to the previous set
++ * Identify all the sequences of set numbers that need locking.
++ * Keep the sequences in sorted list.
++ * For each set in each sequence
++ * - acquire read lock on the set.
++ */
++
++ round_sector = EIO_ROUND_SET_SECTOR(dmc, bio->bi_sector);
++ set_size = dmc->block_size * dmc->assoc;
++ end_sector = bio->bi_sector + eio_to_sector(bio->bi_size);
++ first_set = -1;
++ last_set = -1;
++ cur_set = -1;
++ bc->bc_setspan = NULL;
++
++ while (round_sector < end_sector) {
++ cur_set = hash_block(dmc, round_sector);
++ if (first_set == -1) {
++ first_set = cur_set;
++ last_set = cur_set;
++ } else if (cur_set == (last_set + 1))
++ last_set = cur_set;
++ else {
++ /*
++ * Add the seq of start, end set to sorted (first, last) seq list
++ * and reinit the first and last set
++ */
++ error =
++ insert_set_seq(&bc->bc_setspan, first_set,
++ last_set);
++ if (error)
++ goto err_out;
++ first_set = cur_set;
++ last_set = cur_set;
++ }
++
++ round_sector += set_size;
++ }
++
++ /* Add the remaining first, last set sequence */
++
++ EIO_ASSERT((first_set != -1) && (last_set == cur_set));
++
++ if (bc->bc_setspan == NULL) {
++ /* No sequence was added, can use singlespan */
++ cur_seq = &bc->bc_singlesspan;
++ cur_seq->first_set = first_set;
++ cur_seq->last_set = last_set;
++ cur_seq->next = NULL;
++ bc->bc_setspan = cur_seq;
++ } else {
++ error = insert_set_seq(&bc->bc_setspan, first_set, last_set);
++ if (error)
++ goto err_out;
++ }
++
++ /* Acquire read locks on the sets in the set span */
++ for (cur_seq = bc->bc_setspan; cur_seq; cur_seq = cur_seq->next)
++ for (i = cur_seq->first_set; i <= cur_seq->last_set; i++)
++ down_read(&dmc->cache_sets[i].rw_lock);
++
++ return 0;
++
++err_out:
++
++ /* Free the seqs in the seq list, unless it is just the local seq */
++ if (bc->bc_setspan != &bc->bc_singlesspan) {
++ for (cur_seq = bc->bc_setspan; cur_seq; cur_seq = next_seq) {
++ next_seq = cur_seq->next;
++ kfree(cur_seq);
++ }
++ }
++ return error;
++}
++
++/*
++ * Allocate mdreq and md_blocks for each set.
++ */
++static int eio_alloc_mdreqs(struct cache_c *dmc, struct bio_container *bc)
++{
++ index_t i;
++ struct mdupdate_request *mdreq;
++ int nr_bvecs, ret;
++ struct set_seq *cur_seq;
++
++ bc->mdreqs = NULL;
++
++ for (cur_seq = bc->bc_setspan; cur_seq; cur_seq = cur_seq->next) {
++ for (i = cur_seq->first_set; i <= cur_seq->last_set; i++) {
++ mdreq = kzalloc(sizeof(*mdreq), GFP_NOWAIT);
++ if (mdreq) {
++ mdreq->md_size =
++ dmc->assoc *
++ sizeof(struct flash_cacheblock);
++ nr_bvecs =
++ IO_BVEC_COUNT(mdreq->md_size,
++ SECTORS_PER_PAGE);
++
++ mdreq->mdblk_bvecs =
++ (struct bio_vec *)
++ kmalloc(sizeof(struct bio_vec) * nr_bvecs,
++ GFP_KERNEL);
++ if (mdreq->mdblk_bvecs) {
++
++ ret =
++ eio_alloc_wb_bvecs(mdreq->
++ mdblk_bvecs,
++ nr_bvecs,
++ SECTORS_PER_PAGE);
++ if (ret) {
++ pr_err
++ ("eio_alloc_mdreqs: failed to allocated pages\n");
++ kfree(mdreq->mdblk_bvecs);
++ mdreq->mdblk_bvecs = NULL;
++ }
++ mdreq->mdbvec_count = nr_bvecs;
++ }
++ }
++
++ if (unlikely
++ ((mdreq == NULL) || (mdreq->mdblk_bvecs == NULL))) {
++ struct mdupdate_request *nmdreq;
++
++ mdreq = bc->mdreqs;
++ while (mdreq) {
++ nmdreq = mdreq->next;
++ if (mdreq->mdblk_bvecs) {
++ eio_free_wb_bvecs(mdreq->
++ mdblk_bvecs,
++ mdreq->
++ mdbvec_count,
++ SECTORS_PER_PAGE);
++ kfree(mdreq->mdblk_bvecs);
++ }
++ kfree(mdreq);
++ mdreq = nmdreq;
++ }
++ bc->mdreqs = NULL;
++ return -ENOMEM;
++ } else {
++ mdreq->next = bc->mdreqs;
++ bc->mdreqs = mdreq;
++ }
++ }
++ }
++
++ return 0;
++
++}
++
++/*
++ * Release:
++ * 1. the set locks covering the entire I/O range
++ * 2. any previously allocated memory for md update
++ */
++static int
++eio_release_io_resources(struct cache_c *dmc, struct bio_container *bc)
++{
++ index_t i;
++ struct mdupdate_request *mdreq;
++ struct mdupdate_request *nmdreq;
++ struct set_seq *cur_seq;
++ struct set_seq *next_seq;
++
++ /* Release read locks on the sets in the set span */
++ for (cur_seq = bc->bc_setspan; cur_seq; cur_seq = cur_seq->next)
++ for (i = cur_seq->first_set; i <= cur_seq->last_set; i++)
++ up_read(&dmc->cache_sets[i].rw_lock);
++
++ /* Free the seqs in the set span, unless it is single span */
++ if (bc->bc_setspan != &bc->bc_singlesspan) {
++ for (cur_seq = bc->bc_setspan; cur_seq; cur_seq = next_seq) {
++ next_seq = cur_seq->next;
++ kfree(cur_seq);
++ }
++ }
++
++ mdreq = bc->mdreqs;
++ while (mdreq) {
++ nmdreq = mdreq->next;
++ if (mdreq->mdblk_bvecs) {
++ eio_free_wb_bvecs(mdreq->mdblk_bvecs,
++ mdreq->mdbvec_count,
++ SECTORS_PER_PAGE);
++ kfree(mdreq->mdblk_bvecs);
++ }
++ kfree(mdreq);
++ mdreq = nmdreq;
++ }
++ bc->mdreqs = NULL;
++
++ return 0;
++}
++
++/*
++ * Decide the mapping and perform necessary cache operations for a bio request.
++ */
++int eio_map(struct cache_c *dmc, struct request_queue *rq, struct bio *bio)
++{
++ sector_t sectors = eio_to_sector(bio->bi_size);
++ struct eio_bio *ebio = NULL;
++ struct bio_container *bc;
++ sector_t snum;
++ unsigned int iosize;
++ unsigned int totalio;
++ unsigned int biosize;
++ unsigned int residual_biovec;
++ unsigned int force_uncached = 0;
++ int data_dir = bio_data_dir(bio);
++
++ /*bio list*/
++ struct eio_bio *ebegin = NULL;
++ struct eio_bio *eend = NULL;
++ struct eio_bio *enext = NULL;
++
++ EIO_ASSERT(bio->bi_idx == 0);
++
++ pr_debug("this needs to be removed immediately\n");
++
++ if (bio_rw_flagged(bio, REQ_DISCARD)) {
++ pr_debug
++ ("eio_map: Discard IO received. Invalidate incore start=%lu totalsectors=%d.\n",
++ (unsigned long)bio->bi_sector,
++ (int)eio_to_sector(bio->bi_size));
++ bio_endio(bio, 0);
++ pr_err
++ ("eio_map: I/O with Discard flag received. Discard flag is not supported.\n");
++ return 0;
++ }
++
++ if (unlikely(dmc->cache_rdonly)) {
++ if (data_dir != READ) {
++ bio_endio(bio, -EPERM);
++ pr_debug
++ ("eio_map: cache is read only, write not permitted\n");
++ return 0;
++ }
++ }
++
++ if (sectors < SIZE_HIST)
++ atomic64_inc(&dmc->size_hist[sectors]);
++
++ if (data_dir == READ) {
++ SECTOR_STATS(dmc->eio_stats.reads, bio->bi_size);
++ atomic64_inc(&dmc->eio_stats.readcount);
++ } else {
++ SECTOR_STATS(dmc->eio_stats.writes, bio->bi_size);
++ atomic64_inc(&dmc->eio_stats.writecount);
++ }
++
++ /*
++ * Cache FAILED mode is like Hard failure.
++ * Dont allow I/Os to go through.
++ */
++ if (unlikely(CACHE_FAILED_IS_SET(dmc))) {
++ /*ASK confirm that once failed is set, it's never reset*/
++ /* Source device is not available. */
++ CTRACE
++ ("eio_map:2 source device is not present. Cache is in Failed state\n");
++ bio_endio(bio, -ENODEV);
++ bio = NULL;
++ return DM_MAPIO_SUBMITTED;
++ }
++
++ /* WB cache will never be in degraded mode. */
++ if (unlikely(CACHE_DEGRADED_IS_SET(dmc))) {
++ EIO_ASSERT(dmc->mode != CACHE_MODE_WB);
++ force_uncached = 1;
++ }
++
++ /*
++ * Process zero sized bios by passing original bio flags
++ * to both HDD and SSD.
++ */
++ if (bio->bi_size == 0) {
++ eio_process_zero_size_bio(dmc, bio);
++ return DM_MAPIO_SUBMITTED;
++ }
++
++ /* Create a bio container */
++
++ bc = kzalloc(sizeof(struct bio_container), GFP_NOWAIT);
++ if (!bc) {
++ bio_endio(bio, -ENOMEM);
++ return DM_MAPIO_SUBMITTED;
++ }
++ bc->bc_iotime = jiffies;
++ bc->bc_bio = bio;
++ bc->bc_dmc = dmc;
++ spin_lock_init(&bc->bc_lock);
++ atomic_set(&bc->bc_holdcount, 1);
++ bc->bc_error = 0;
++
++ snum = bio->bi_sector;
++ totalio = bio->bi_size;
++ biosize = bio->bi_size;
++ residual_biovec = 0;
++
++ if (dmc->mode == CACHE_MODE_WB) {
++ int ret;
++ /*
++ * For writeback, the app I/O and the clean I/Os
++ * need to be exclusive for a cache set. Acquire shared
++ * lock on the cache set for app I/Os and exclusive
++ * lock on the cache set for clean I/Os.
++ */
++ ret = eio_acquire_set_locks(dmc, bc);
++ if (ret) {
++ bio_endio(bio, ret);
++ kfree(bc);
++ return DM_MAPIO_SUBMITTED;
++ }
++ }
++
++ atomic64_inc(&dmc->nr_ios);
++
++ /*
++ * Prepare for I/O processing.
++ * - Allocate ebios.
++ * - For reads, identify if we need to do uncached read
++ * - If force uncached I/O is set, invalidate the cache blocks for the I/O
++ */
++
++ if (force_uncached)
++ eio_inval_range(dmc, snum, totalio);
++ else {
++ while (biosize) {
++ iosize = eio_get_iosize(dmc, snum, biosize);
++ ebio = eio_new_ebio(dmc, bio, &residual_biovec, snum,
++ iosize, bc, EB_SUBORDINATE_IO);
++ if (IS_ERR(ebio)) {
++ bc->bc_error = -ENOMEM;
++ break;
++ }
++
++ /* Anchor this ebio on ebio list. Preserve the order */
++ if (ebegin)
++ eend->eb_next = ebio;
++ else
++ ebegin = ebio;
++ eend = ebio;
++
++ biosize -= iosize;
++ snum += eio_to_sector(iosize);
++ }
++ }
++
++ if (bc->bc_error) {
++ /* Error. Do ebio and bc cleanup. */
++ ebio = ebegin;
++ while (ebio) {
++ enext = ebio->eb_next;
++ eb_endio(ebio, bc->bc_error);
++ ebio = enext;
++ }
++
++ /* By now, the bc_holdcount must be 1 */
++ EIO_ASSERT(atomic_read(&bc->bc_holdcount) == 1);
++
++ /* Goto out to cleanup the bc(in bc_put()) */
++ goto out;
++ }
++
++ /*
++ * Start processing of the ebios.
++ *
++ * Note: don't return error from this point on.
++ * Error handling would be done as part of
++ * the processing of the ebios internally.
++ */
++ if (force_uncached) {
++ EIO_ASSERT(dmc->mode != CACHE_MODE_WB);
++ if (data_dir == READ)
++ atomic64_inc(&dmc->eio_stats.uncached_reads);
++ else
++ atomic64_inc(&dmc->eio_stats.uncached_writes);
++ eio_disk_io(dmc, bio, ebegin, bc, 1);
++ } else if (data_dir == READ) {
++
++ /* read io processing */
++ eio_read(dmc, bc, ebegin);
++ } else
++ /* write io processing */
++ eio_write(dmc, bc, ebegin);
++
++out:
++
++ if (bc)
++ bc_put(bc, 0);
++
++ return DM_MAPIO_SUBMITTED;
++}
++
++/*
++ * Checks the cache block state, for deciding cached/uncached read.
++ * Also reserves/allocates the cache block, wherever necessary.
++ *
++ * Return values
++ * 1: cache hit
++ * 0: cache miss
++ */
++static int eio_read_peek(struct cache_c *dmc, struct eio_bio *ebio)
++{
++ index_t index;
++ int res;
++ int retval = 0;
++ unsigned long flags;
++ u_int8_t cstate;
++
++ spin_lock_irqsave(&dmc->cache_sets[ebio->eb_cacheset].cs_lock, flags);
++
++ res = eio_lookup(dmc, ebio, &index);
++ ebio->eb_index = -1;
++
++ if (res < 0) {
++ atomic64_inc(&dmc->eio_stats.noroom);
++ goto out;
++ }
++
++ cstate = EIO_CACHE_STATE_GET(dmc, index);
++
++ if (cstate & (BLOCK_IO_INPROG | QUEUED))
++ /*
++ * We found a valid or invalid block but an io is on, so we can't
++ * proceed. Don't invalidate it. This implies that we'll
++ * have to read from disk.
++ * Read on a DIRTY | INPROG block (block which is going to be DIRTY)
++ * is also redirected to read from disk.
++ */
++ goto out;
++
++ if (res == VALID) {
++ EIO_ASSERT(cstate & VALID);
++ if ((EIO_DBN_GET(dmc, index) ==
++ EIO_ROUND_SECTOR(dmc, ebio->eb_sector))) {
++ /*
++ * Read/write should be done on already DIRTY block
++ * without any inprog flag.
++ * Ensure that a failure of DIRTY block read is propagated to app.
++ * non-DIRTY valid blocks should have inprog flag.
++ */
++ if (cstate == ALREADY_DIRTY) {
++ ebio->eb_iotype = EB_MAIN_IO;
++ /*
++ * Set to uncached read and readfill for now.
++ * It may change to CACHED_READ later, if all
++ * the blocks are found to be cached
++ */
++ ebio->eb_bc->bc_dir =
++ UNCACHED_READ_AND_READFILL;
++ } else
++ EIO_CACHE_STATE_ON(dmc, index, CACHEREADINPROG);
++ retval = 1;
++ ebio->eb_index = index;
++ goto out;
++ }
++
++ /* cache is marked readonly. Do not allow READFILL on SSD */
++ if (unlikely(dmc->cache_rdonly))
++ goto out;
++
++ /*
++ * Found a block to be recycled.
++ * Its guranteed that it will be a non-DIRTY block
++ */
++ EIO_ASSERT(!(cstate & DIRTY));
++ if (eio_to_sector(ebio->eb_size) == dmc->block_size) {
++ /*We can recycle and then READFILL only if iosize is block size*/
++ atomic64_inc(&dmc->eio_stats.rd_replace);
++ EIO_CACHE_STATE_SET(dmc, index, VALID | DISKREADINPROG);
++ EIO_DBN_SET(dmc, index, (sector_t)ebio->eb_sector);
++ ebio->eb_index = index;
++ ebio->eb_bc->bc_dir = UNCACHED_READ_AND_READFILL;
++ }
++ goto out;
++ }
++ EIO_ASSERT(res == INVALID);
++
++ /* cache is marked readonly. Do not allow READFILL on SSD */
++ if (unlikely(dmc->cache_rdonly))
++ goto out;
++ /*
++ * Found an invalid block to be used.
++ * Can recycle only if iosize is block size
++ */
++ if (eio_to_sector(ebio->eb_size) == dmc->block_size) {
++ EIO_ASSERT(cstate & INVALID);
++ EIO_CACHE_STATE_SET(dmc, index, VALID | DISKREADINPROG);
++ atomic64_inc(&dmc->eio_stats.cached_blocks);
++ EIO_DBN_SET(dmc, index, (sector_t)ebio->eb_sector);
++ ebio->eb_index = index;
++ ebio->eb_bc->bc_dir = UNCACHED_READ_AND_READFILL;
++ }
++
++out:
++
++ spin_unlock_irqrestore(&dmc->cache_sets[ebio->eb_cacheset].cs_lock,
++ flags);
++
++ /*
++ * Enqueue clean set if there is no room in the set
++ * TBD
++ * Ensure, a force clean
++ */
++ if (res < 0)
++ eio_comply_dirty_thresholds(dmc, ebio->eb_cacheset);
++
++ return retval;
++}
++
++/*
++ * Checks the cache block state, for deciding cached/uncached write.
++ * Also reserves/allocates the cache block, wherever necessary.
++ *
++ * Return values
++ * 1: cache block is available or newly allocated
++ * 0: cache block could not be got for the ebio
++ */
++static int eio_write_peek(struct cache_c *dmc, struct eio_bio *ebio)
++{
++ index_t index;
++ int res;
++ int retval;
++ u_int8_t cstate;
++ unsigned long flags;
++
++ spin_lock_irqsave(&dmc->cache_sets[ebio->eb_cacheset].cs_lock, flags);
++
++ res = eio_lookup(dmc, ebio, &index);
++ ebio->eb_index = -1;
++ retval = 0;
++
++ if (res < 0) {
++ /* cache block not found and new block couldn't be allocated */
++ atomic64_inc(&dmc->eio_stats.noroom);
++ ebio->eb_iotype |= EB_INVAL;
++ goto out;
++ }
++
++ cstate = EIO_CACHE_STATE_GET(dmc, index);
++
++ if (cstate & (BLOCK_IO_INPROG | QUEUED)) {
++ ebio->eb_iotype |= EB_INVAL;
++ /* treat as if cache block is not available */
++ goto out;
++ }
++
++ if ((res == VALID) && (EIO_DBN_GET(dmc, index) ==
++ EIO_ROUND_SECTOR(dmc, ebio->eb_sector))) {
++ /*
++ * Cache hit.
++ * All except an already DIRTY block should have an INPROG flag.
++ * If it is a cached write, a DIRTY flag would be added later.
++ */
++ SECTOR_STATS(dmc->eio_stats.write_hits, ebio->eb_size);
++ if (cstate != ALREADY_DIRTY)
++ EIO_CACHE_STATE_ON(dmc, index, CACHEWRITEINPROG);
++ else
++ atomic64_inc(&dmc->eio_stats.dirty_write_hits);
++ ebio->eb_index = index;
++ /*
++ * A VALID block should get upgraded to DIRTY, only when we
++ * are updating the entire cache block(not partially).
++ * Otherwise, 2 sequential partial writes can lead to missing
++ * data when one write upgrades the cache block to DIRTY, while
++ * the other just writes to HDD. Subsequent read would be
++ * served from the cache block, which won't have the data from
++ * 2nd write.
++ */
++ if ((cstate == ALREADY_DIRTY) ||
++ (eio_to_sector(ebio->eb_size) == dmc->block_size))
++ retval = 1;
++ else
++ retval = 0;
++ goto out;
++
++ }
++
++ /*
++ * cache miss with a new block allocated for recycle.
++ * Set INPROG flag, if the ebio size is equal to cache block size
++ */
++ EIO_ASSERT(!(EIO_CACHE_STATE_GET(dmc, index) & DIRTY));
++ if (eio_to_sector(ebio->eb_size) == dmc->block_size) {
++ if (res == VALID)
++ atomic64_inc(&dmc->eio_stats.wr_replace);
++ else
++ atomic64_inc(&dmc->eio_stats.cached_blocks);
++ EIO_CACHE_STATE_SET(dmc, index, VALID | CACHEWRITEINPROG);
++ EIO_DBN_SET(dmc, index, (sector_t)ebio->eb_sector);
++ ebio->eb_index = index;
++ retval = 1;
++ } else {
++ /*
++ * eb iosize smaller than cache block size shouldn't
++ * do cache write on a cache miss
++ */
++ retval = 0;
++ ebio->eb_iotype |= EB_INVAL;
++ }
++
++out:
++ if ((retval == 1) && (dmc->mode == CACHE_MODE_WB) &&
++ (cstate != ALREADY_DIRTY))
++ ebio->eb_bc->bc_mdwait++;
++
++ spin_unlock_irqrestore(&dmc->cache_sets[ebio->eb_cacheset].cs_lock,
++ flags);
++
++ /*
++ * Enqueue clean set if there is no room in the set
++ * TBD
++ * Ensure, a force clean
++ */
++ if (res < 0)
++ eio_comply_dirty_thresholds(dmc, ebio->eb_cacheset);
++
++ return retval;
++}
++
++/* Top level read function, called from eio_map */
++static void
++eio_read(struct cache_c *dmc, struct bio_container *bc, struct eio_bio *ebegin)
++{
++ int ucread = 0;
++ struct eio_bio *ebio;
++ struct eio_bio *enext;
++
++ bc->bc_dir = UNCACHED_READ;
++ ebio = ebegin;
++ while (ebio) {
++ enext = ebio->eb_next;
++ if (eio_read_peek(dmc, ebio) == 0)
++ ucread = 1;
++ ebio = enext;
++ }
++
++ if (ucread) {
++ /*
++ * Uncached read.
++ * Start HDD I/O. Once that is finished
++ * readfill or dirty block re-read would start
++ */
++ atomic64_inc(&dmc->eio_stats.uncached_reads);
++ eio_disk_io(dmc, bc->bc_bio, ebegin, bc, 0);
++ } else {
++ /* Cached read. Serve the read from SSD */
++
++ /*
++ * Pass all orig bio flags except UNPLUG.
++ * Unplug in the end if flagged.
++ */
++ int rw_flags;
++
++ rw_flags = 0;
++
++ bc->bc_dir = CACHED_READ;
++ ebio = ebegin;
++
++ VERIFY_BIO_FLAGS(ebio);
++
++ EIO_ASSERT((rw_flags & 1) == READ);
++ while (ebio) {
++ enext = ebio->eb_next;
++ ebio->eb_iotype = EB_MAIN_IO;
++
++ eio_cached_read(dmc, ebio, rw_flags);
++ ebio = enext;
++ }
++ }
++}
++
++/* Top level write function called from eio_map */
++static void
++eio_write(struct cache_c *dmc, struct bio_container *bc, struct eio_bio *ebegin)
++{
++ int ucwrite = 0;
++ int error = 0;
++ struct eio_bio *ebio;
++ struct eio_bio *enext;
++
++ if ((dmc->mode != CACHE_MODE_WB) ||
++ (dmc->sysctl_active.do_clean & EIO_CLEAN_KEEP))
++ ucwrite = 1;
++
++ ebio = ebegin;
++ while (ebio) {
++ enext = ebio->eb_next;
++ if (eio_write_peek(dmc, ebio) == 0)
++ ucwrite = 1;
++ ebio = enext;
++ }
++
++ if (ucwrite) {
++ /*
++ * Uncached write.
++ * Start both SSD and HDD writes
++ */
++ atomic64_inc(&dmc->eio_stats.uncached_writes);
++ bc->bc_mdwait = 0;
++ bc->bc_dir = UNCACHED_WRITE;
++ ebio = ebegin;
++ while (ebio) {
++ enext = ebio->eb_next;
++ eio_uncached_write(dmc, ebio);
++ ebio = enext;
++ }
++
++ eio_disk_io(dmc, bc->bc_bio, ebegin, bc, 0);
++ } else {
++ /* Cached write. Start writes to SSD blocks */
++
++ int rw_flags;
++ rw_flags = 0;
++
++ bc->bc_dir = CACHED_WRITE;
++ if (bc->bc_mdwait) {
++
++ /*
++ * mdreqs are required only if the write would cause a metadata
++ * update.
++ */
++
++ error = eio_alloc_mdreqs(dmc, bc);
++ }
++
++ /*
++ * Pass all orig bio flags except UNPLUG.
++ * UNPLUG in the end if flagged.
++ */
++ ebio = ebegin;
++ VERIFY_BIO_FLAGS(ebio);
++
++ while (ebio) {
++ enext = ebio->eb_next;
++ ebio->eb_iotype = EB_MAIN_IO;
++
++ if (!error) {
++
++ eio_cached_write(dmc, ebio, WRITE | rw_flags);
++
++ } else {
++ unsigned long flags;
++ u_int8_t cstate;
++
++ pr_err
++ ("eio_write: IO submission failed, block %llu",
++ EIO_DBN_GET(dmc, ebio->eb_index));
++ spin_lock_irqsave(&dmc->
++ cache_sets[ebio->eb_cacheset].
++ cs_lock, flags);
++ cstate =
++ EIO_CACHE_STATE_GET(dmc, ebio->eb_index);
++ if (cstate != ALREADY_DIRTY) {
++
++ /*
++ * A DIRTY(inprog) block should be invalidated on error.
++ */
++
++ EIO_CACHE_STATE_SET(dmc, ebio->eb_index,
++ INVALID);
++ atomic64_dec_if_positive(&dmc->
++ eio_stats.
++ cached_blocks);
++ }
++ spin_unlock_irqrestore(&dmc->
++ cache_sets[ebio->
++ eb_cacheset].
++ cs_lock, flags);
++ eb_endio(ebio, error);
++ }
++ ebio = enext;
++ }
++ }
++}
++
++/*
++ * Synchronous clean of all the cache sets. Callers of this function needs
++ * to handle the situation that clean operation was aborted midway.
++ */
++
++void eio_clean_all(struct cache_c *dmc)
++{
++ unsigned long flags = 0;
++
++ EIO_ASSERT(dmc->mode == CACHE_MODE_WB);
++ for (atomic_set(&dmc->clean_index, 0);
++ (atomic_read(&dmc->clean_index) <
++ (s32)(dmc->size >> dmc->consecutive_shift))
++ && (dmc->sysctl_active.do_clean & EIO_CLEAN_START)
++ && (atomic64_read(&dmc->nr_dirty) > 0)
++ && (!(dmc->cache_flags & CACHE_FLAGS_SHUTDOWN_INPROG)
++ && !dmc->sysctl_active.fast_remove);
++ atomic_inc(&dmc->clean_index)) {
++
++ if (unlikely(CACHE_FAILED_IS_SET(dmc))) {
++ pr_err("clean_all: CACHE \"%s\" is in FAILED state.",
++ dmc->cache_name);
++ break;
++ }
++
++ eio_clean_set(dmc, (index_t)(atomic_read(&dmc->clean_index)),
++ /* whole */ 1, /* force */ 1);
++ }
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.do_clean &= ~EIO_CLEAN_START;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++}
++
++/*
++ * Do unconditional clean of a cache.
++ * Useful for a cold enabled writeback cache.
++ */
++void eio_clean_for_reboot(struct cache_c *dmc)
++{
++ index_t i;
++
++ for (i = 0; i < (index_t)(dmc->size >> dmc->consecutive_shift); i++)
++ eio_clean_set(dmc, i, /* whole */ 1, /* force */ 1);
++}
++
++/*
++ * Used during the partial cache set clean.
++ * Uses reclaim policy(LRU/FIFO) information to
++ * identify the cache blocks that needs cleaning.
++ * The number of such cache blocks is determined
++ * by the high and low thresholds set.
++ */
++static void
++eio_get_setblks_to_clean(struct cache_c *dmc, index_t set, int *ncleans)
++{
++ int i = 0;
++ int max_clean;
++ index_t start_index;
++ int nr_writes = 0;
++
++ *ncleans = 0;
++
++ max_clean = dmc->cache_sets[set].nr_dirty -
++ ((dmc->sysctl_active.dirty_set_low_threshold * dmc->assoc) / 100);
++ if (max_clean <= 0)
++ /* Nothing to clean */
++ return;
++
++ start_index = set * dmc->assoc;
++
++ /*
++ * Spinlock is not required here, as we assume that we have
++ * taken a write lock on the cache set, when we reach here
++ */
++ if (dmc->policy_ops == NULL) {
++ /* Scan sequentially in the set and pick blocks to clean */
++ while ((i < (int)dmc->assoc) && (nr_writes < max_clean)) {
++ if ((EIO_CACHE_STATE_GET(dmc, start_index + i) &
++ (DIRTY | BLOCK_IO_INPROG)) == DIRTY) {
++ EIO_CACHE_STATE_ON(dmc, start_index + i,
++ DISKWRITEINPROG);
++ nr_writes++;
++ }
++ i++;
++ }
++ } else
++ nr_writes =
++ eio_policy_clean_set(dmc->policy_ops, set, max_clean);
++
++ *ncleans = nr_writes;
++}
++
++/* Callback function, when synchronous I/O completes */
++static void eio_sync_io_callback(int error, void *context)
++{
++ struct sync_io_context *sioc = (struct sync_io_context *)context;
++
++ if (error)
++ sioc->sio_error = error;
++ up_read(&sioc->sio_lock);
++}
++
++/*
++ * Setup biovecs for preallocated biovecs per cache set.
++ */
++
++struct bio_vec *setup_bio_vecs(struct bio_vec *bvec, index_t block_index,
++ unsigned block_size, unsigned total,
++ unsigned *num_bvecs)
++{
++ struct bio_vec *data = NULL;
++ index_t iovec_index;
++
++ switch (block_size) {
++ case BLKSIZE_2K:
++ *num_bvecs = total;
++ iovec_index = block_index;
++ data = &bvec[iovec_index];
++ break;
++
++ case BLKSIZE_4K:
++ *num_bvecs = total;
++ iovec_index = block_index;
++ data = &bvec[iovec_index];
++ break;
++
++ case BLKSIZE_8K:
++ /*
++ * For 8k data block size, we need 2 bio_vecs
++ * per data block.
++ */
++ *num_bvecs = total * 2;
++ iovec_index = block_index * 2;
++ data = &bvec[iovec_index];
++ break;
++ }
++
++ return data;
++}
++
++/* Cleans a given cache set */
++static void
++eio_clean_set(struct cache_c *dmc, index_t set, int whole, int force)
++{
++ struct eio_io_region where;
++ int error;
++ index_t i;
++ index_t j;
++ index_t start_index;
++ index_t end_index;
++ struct sync_io_context sioc;
++ int ncleans = 0;
++ int alloc_size;
++ struct flash_cacheblock *md_blocks = NULL;
++ unsigned long flags;
++
++ int pindex, k;
++ index_t blkindex;
++ struct bio_vec *bvecs;
++ unsigned nr_bvecs = 0, total;
++ void *pg_virt_addr[2] = { NULL };
++
++ /* Cache is failed mode, do nothing. */
++ if (unlikely(CACHE_FAILED_IS_SET(dmc))) {
++ pr_debug("clean_set: CACHE \"%s\" is in FAILED state.",
++ dmc->cache_name);
++ goto err_out1;
++ }
++
++ /* Nothing to clean, if there are no dirty blocks */
++ if (dmc->cache_sets[set].nr_dirty == 0)
++ goto err_out1;
++
++ /* If this is not the suitable time to clean, postpone it */
++ if ((!force) && AUTOCLEAN_THRESHOLD_CROSSED(dmc)) {
++ eio_touch_set_lru(dmc, set);
++ goto err_out1;
++ }
++
++ /*
++ * 1. Take exclusive lock on the cache set
++ * 2. Verify that there are dirty blocks to clean
++ * 3. Identify the cache blocks to clean
++ * 4. Read the cache blocks data from ssd
++ * 5. Write the cache blocks data to hdd
++ * 6. Update on-disk cache metadata
++ * 7. Update in-core cache metadata
++ */
++
++ start_index = set * dmc->assoc;
++ end_index = start_index + dmc->assoc;
++
++ /* 1. exclusive lock. Let the ongoing writes to finish. Pause new writes */
++ down_write(&dmc->cache_sets[set].rw_lock);
++
++ /* 2. Return if there are no dirty blocks to clean */
++ if (dmc->cache_sets[set].nr_dirty == 0)
++ goto err_out2;
++
++ /* 3. identify and mark cache blocks to clean */
++ if (!whole)
++ eio_get_setblks_to_clean(dmc, set, &ncleans);
++ else {
++ for (i = start_index; i < end_index; i++) {
++ if (EIO_CACHE_STATE_GET(dmc, i) == ALREADY_DIRTY) {
++ EIO_CACHE_STATE_SET(dmc, i, CLEAN_INPROG);
++ ncleans++;
++ }
++ }
++ }
++
++ /* If nothing to clean, return */
++ if (!ncleans)
++ goto err_out2;
++
++ /*
++ * From this point onwards, make sure to reset
++ * the clean inflag on cache blocks before returning
++ */
++
++ /* 4. read cache set data */
++
++ init_rwsem(&sioc.sio_lock);
++ sioc.sio_error = 0;
++
++ for (i = start_index; i < end_index; i++) {
++ if (EIO_CACHE_STATE_GET(dmc, i) == CLEAN_INPROG) {
++
++ for (j = i; ((j < end_index) &&
++ (EIO_CACHE_STATE_GET(dmc, j) == CLEAN_INPROG));
++ j++);
++
++ blkindex = (i - start_index);
++ total = (j - i);
++
++ /*
++ * Get the correct index and number of bvecs
++ * setup from dmc->clean_dbvecs before issuing i/o.
++ */
++ bvecs =
++ setup_bio_vecs(dmc->clean_dbvecs, blkindex,
++ dmc->block_size, total, &nr_bvecs);
++ EIO_ASSERT(bvecs != NULL);
++ EIO_ASSERT(nr_bvecs > 0);
++
++ where.bdev = dmc->cache_dev->bdev;
++ where.sector =
++ (i << dmc->block_shift) + dmc->md_sectors;
++ where.count = total * dmc->block_size;
++
++ SECTOR_STATS(dmc->eio_stats.ssd_reads,
++ to_bytes(where.count));
++ down_read(&sioc.sio_lock);
++ error =
++ eio_io_async_bvec(dmc, &where, READ, bvecs,
++ nr_bvecs, eio_sync_io_callback,
++ &sioc, 0);
++ if (error) {
++ sioc.sio_error = error;
++ up_read(&sioc.sio_lock);
++ }
++
++ bvecs = NULL;
++ i = j;
++ }
++ }
++ /*
++ * In above for loop, submit all READ I/Os to SSD
++ * and unplug the device for immediate submission to
++ * underlying device driver.
++ */
++ eio_unplug_cache_device(dmc);
++
++ /* wait for all I/Os to complete and release sync lock */
++ down_write(&sioc.sio_lock);
++ up_write(&sioc.sio_lock);
++
++ error = sioc.sio_error;
++ if (error)
++ goto err_out3;
++
++ /* 5. write to hdd */
++ /*
++ * While writing the data to HDD, explicitly enable
++ * BIO_RW_SYNC flag to hint higher priority for these
++ * I/Os.
++ */
++ for (i = start_index; i < end_index; i++) {
++ if (EIO_CACHE_STATE_GET(dmc, i) == CLEAN_INPROG) {
++
++ blkindex = (i - start_index);
++ total = 1;
++
++ bvecs =
++ setup_bio_vecs(dmc->clean_dbvecs, blkindex,
++ dmc->block_size, total, &nr_bvecs);
++ EIO_ASSERT(bvecs != NULL);
++ EIO_ASSERT(nr_bvecs > 0);
++
++ where.bdev = dmc->disk_dev->bdev;
++ where.sector = EIO_DBN_GET(dmc, i);
++ where.count = dmc->block_size;
++
++ SECTOR_STATS(dmc->eio_stats.disk_writes,
++ to_bytes(where.count));
++ down_read(&sioc.sio_lock);
++ error = eio_io_async_bvec(dmc, &where, WRITE | REQ_SYNC,
++ bvecs, nr_bvecs,
++ eio_sync_io_callback, &sioc,
++ 1);
++
++ if (error) {
++ sioc.sio_error = error;
++ up_read(&sioc.sio_lock);
++ }
++ bvecs = NULL;
++ }
++ }
++
++ /* wait for all I/Os to complete and release sync lock */
++ down_write(&sioc.sio_lock);
++ up_write(&sioc.sio_lock);
++
++ error = sioc.sio_error;
++ if (error)
++ goto err_out3;
++
++ /* 6. update on-disk cache metadata */
++
++ /* TBD. Do we have to consider sector alignment here ? */
++
++ /*
++ * md_size = dmc->assoc * sizeof(struct flash_cacheblock);
++ * Currently, md_size is 8192 bytes, mdpage_count is 2 pages maximum.
++ */
++
++ EIO_ASSERT(dmc->mdpage_count <= 2);
++ for (k = 0; k < dmc->mdpage_count; k++)
++ pg_virt_addr[k] = kmap(dmc->clean_mdpages[k]);
++
++ alloc_size = dmc->assoc * sizeof(struct flash_cacheblock);
++ pindex = 0;
++ md_blocks = (struct flash_cacheblock *)pg_virt_addr[pindex];
++ k = MD_BLOCKS_PER_PAGE;
++
++ for (i = start_index; i < end_index; i++) {
++
++ md_blocks->dbn = cpu_to_le64(EIO_DBN_GET(dmc, i));
++
++ if (EIO_CACHE_STATE_GET(dmc, i) == CLEAN_INPROG)
++ md_blocks->cache_state = cpu_to_le64(INVALID);
++ else if (EIO_CACHE_STATE_GET(dmc, i) == ALREADY_DIRTY)
++ md_blocks->cache_state = cpu_to_le64((VALID | DIRTY));
++ else
++ md_blocks->cache_state = cpu_to_le64(INVALID);
++
++ /* This was missing earlier. */
++ md_blocks++;
++ k--;
++
++ if (k == 0) {
++ md_blocks =
++ (struct flash_cacheblock *)pg_virt_addr[++pindex];
++ k = MD_BLOCKS_PER_PAGE;
++ }
++ }
++
++ for (k = 0; k < dmc->mdpage_count; k++)
++ kunmap(dmc->clean_mdpages[k]);
++
++ where.bdev = dmc->cache_dev->bdev;
++ where.sector = dmc->md_start_sect + INDEX_TO_MD_SECTOR(start_index);
++ where.count = eio_to_sector(alloc_size);
++ error =
++ eio_io_sync_pages(dmc, &where, WRITE, dmc->clean_mdpages,
++ dmc->mdpage_count);
++
++ if (error)
++ goto err_out3;
++
++err_out3:
++
++ /*
++ * 7. update in-core cache metadata for clean_inprog blocks.
++ * If there was an error, set them back to ALREADY_DIRTY
++ * If no error, set them to VALID
++ */
++ for (i = start_index; i < end_index; i++) {
++ if (EIO_CACHE_STATE_GET(dmc, i) == CLEAN_INPROG) {
++ if (error)
++ EIO_CACHE_STATE_SET(dmc, i, ALREADY_DIRTY);
++ else {
++ EIO_CACHE_STATE_SET(dmc, i, VALID);
++ EIO_ASSERT(dmc->cache_sets[set].nr_dirty > 0);
++ dmc->cache_sets[set].nr_dirty--;
++ atomic64_dec(&dmc->nr_dirty);
++ }
++ }
++ }
++
++err_out2:
++
++ up_write(&dmc->cache_sets[set].rw_lock);
++
++err_out1:
++
++ /* Reset clean flags on the set */
++
++ if (!force) {
++ spin_lock_irqsave(&dmc->cache_sets[set].cs_lock, flags);
++ dmc->cache_sets[set].flags &=
++ ~(SETFLAG_CLEAN_INPROG | SETFLAG_CLEAN_WHOLE);
++ spin_unlock_irqrestore(&dmc->cache_sets[set].cs_lock, flags);
++ }
++
++ if (dmc->cache_sets[set].nr_dirty)
++ /*
++ * Lru touch the set, so that it can be picked
++ * up for whole set clean by clean thread later
++ */
++ eio_touch_set_lru(dmc, set);
++
++ return;
++}
++
++/*
++ * Enqueues the dirty sets for clean, which had got dirtied long
++ * time back(aged). User tunable values to determine if a set has aged
++ */
++void eio_clean_aged_sets(struct work_struct *work)
++{
++ struct cache_c *dmc;
++ unsigned long flags = 0;
++ index_t set_index;
++ u_int64_t set_time;
++ u_int64_t cur_time;
++
++ dmc = container_of(work, struct cache_c, clean_aged_sets_work.work);
++
++ /*
++ * In FAILED state, dont schedule cleaning of sets.
++ */
++ if (unlikely(CACHE_FAILED_IS_SET(dmc))) {
++ pr_debug("clean_aged_sets: Cache \"%s\" is in failed mode.\n",
++ dmc->cache_name);
++ /*
++ * This is to make sure that this thread is rescheduled
++ * once CACHE is ACTIVE again.
++ */
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock, flags);
++ dmc->is_clean_aged_sets_sched = 0;
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock, flags);
++
++ return;
++ }
++
++ cur_time = jiffies;
++
++ /* Use the set LRU list to pick up the most aged sets. */
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock, flags);
++ do {
++ lru_read_head(dmc->dirty_set_lru, &set_index, &set_time);
++ if (set_index == LRU_NULL)
++ break;
++
++ if ((EIO_DIV((cur_time - set_time), HZ)) <
++ (dmc->sysctl_active.time_based_clean_interval * 60))
++ break;
++ lru_rem(dmc->dirty_set_lru, set_index);
++
++ if (dmc->cache_sets[set_index].nr_dirty > 0) {
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock, flags);
++ eio_addto_cleanq(dmc, set_index, 1);
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock, flags);
++ }
++ } while (1);
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock, flags);
++
++ /* Re-schedule the aged set clean, unless the clean has to stop now */
++
++ if (dmc->sysctl_active.time_based_clean_interval == 0)
++ goto out;
++
++ schedule_delayed_work(&dmc->clean_aged_sets_work,
++ dmc->sysctl_active.time_based_clean_interval *
++ 60 * HZ);
++out:
++ return;
++}
++
++/* Move the given set at the head of the set LRU list */
++void eio_touch_set_lru(struct cache_c *dmc, index_t set)
++{
++ u_int64_t systime;
++ unsigned long flags;
++
++ systime = jiffies;
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock, flags);
++ lru_touch(dmc->dirty_set_lru, set, systime);
++
++ if ((dmc->sysctl_active.time_based_clean_interval > 0) &&
++ (dmc->is_clean_aged_sets_sched == 0)) {
++ schedule_delayed_work(&dmc->clean_aged_sets_work,
++ dmc->sysctl_active.
++ time_based_clean_interval * 60 * HZ);
++ dmc->is_clean_aged_sets_sched = 1;
++ }
++
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock, flags);
++}
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_mem.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_mem.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_mem.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_mem.c 2014-05-15 20:33:46.537931265 +0200
+@@ -0,0 +1,236 @@
++/*
++ * eio_mem.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "eio.h"
++
++#define SECTORS_PER_SET (dmc->assoc * dmc->block_size)
++#define SECTORS_PER_SET_SHIFT (dmc->consecutive_shift + dmc->block_shift)
++#define SECTORS_PER_SET_MASK (SECTORS_PER_SET - 1)
++
++#define EIO_DBN_TO_SET(dmc, dbn, set_number, wrapped) do { \
++ u_int64_t value; \
++ u_int64_t mid_i; \
++ value = (dbn) >> SECTORS_PER_SET_SHIFT; \
++ mid_i = (value) & (dmc)->num_sets_mask; \
++ if (mid_i >= (dmc)->num_sets) { \
++ (wrapped) = 1; \
++ (set_number) = mid_i - (dmc)->num_sets; \
++ } else { \
++ (wrapped) = 0; \
++ (set_number) = mid_i; \
++ } \
++} while (0)
++
++/*
++ * eio_mem_init
++ */
++int eio_mem_init(struct cache_c *dmc)
++{
++ u_int32_t lsb_bits;
++ u_int32_t msb_bits_24; /* most significant bits in shrunk dbn */
++ u_int64_t max_dbn;
++ u_int64_t num_sets_64;
++
++ /*
++ * Sanity check the number of sets.
++ */
++ num_sets_64 = EIO_DIV(dmc->size, dmc->assoc);
++ if (num_sets_64 > UINT_MAX) {
++ pr_err("Number of cache sets (%lu) greater than maximum" \
++ "allowed (%u)",
++ (long unsigned int)num_sets_64, UINT_MAX);
++ return -1;
++ }
++
++ /*
++ * Find the number of bits required to encode the set number and
++ * its corresponding mask value.
++ */
++ dmc->num_sets = (u_int32_t)num_sets_64;
++ for (dmc->num_sets_bits = 0; (dmc->num_sets >> dmc->num_sets_bits);
++ dmc->num_sets_bits++);
++
++ dmc->num_sets_mask = ULLONG_MAX >> (64 - dmc->num_sets_bits);
++
++ /*
++ * If we don't have at least 16 bits to save,
++ * we can't use small metadata.
++ */
++ if (dmc->num_sets_bits < 16) {
++ dmc->cache_flags |= CACHE_FLAGS_MD8;
++ pr_info("Not enough sets to use small metadata");
++ return 1;
++ }
++
++ /*
++ * Now compute the largest sector number that we can shrink; then see
++ * if the source volume is smaller.
++ */
++ lsb_bits = dmc->consecutive_shift + dmc->block_shift;
++ msb_bits_24 = 24 - 1 - lsb_bits; /* 1 for wrapped bit */
++ max_dbn =
++ ((u_int64_t)1) << (msb_bits_24 + dmc->num_sets_bits + lsb_bits);
++ if (eio_to_sector(eio_get_device_size(dmc->disk_dev)) > max_dbn) {
++ dmc->cache_flags |= CACHE_FLAGS_MD8;
++ pr_info("Source volume too big to use small metadata");
++ return 1;
++ }
++
++ return 0;
++}
++
++/*
++ * eio_hash_block
++ */
++u_int32_t eio_hash_block(struct cache_c *dmc, sector_t dbn)
++{
++ int wrapped;
++ u_int64_t set_number;
++
++ EIO_DBN_TO_SET(dmc, dbn, set_number, wrapped);
++ EIO_ASSERT(set_number < dmc->num_sets);
++
++ return (u_int32_t)set_number;
++}
++
++/*
++ * eio_shrink_dbn
++ *
++ * Shrink a 5-byte "dbn" into a 3-byte "dbn" by eliminating 16 lower bits
++ * of the set number this "dbn" belongs to.
++ */
++unsigned int eio_shrink_dbn(struct cache_c *dmc, sector_t dbn)
++{
++ u_int32_t dbn_24;
++ sector_t lsb;
++ sector_t wrapped;
++ sector_t msb;
++ sector_t set_number;
++
++ EIO_ASSERT(!EIO_MD8(dmc));
++ if (unlikely(dbn == 0))
++ return 0;
++
++ lsb = dbn & SECTORS_PER_SET_MASK;
++ EIO_DBN_TO_SET(dmc, dbn, set_number, wrapped);
++ msb = dbn >> (dmc->num_sets_bits + SECTORS_PER_SET_SHIFT);
++ dbn_24 =
++ (unsigned int)(lsb | (wrapped << SECTORS_PER_SET_SHIFT) |
++ (msb << (SECTORS_PER_SET_SHIFT + 1)));
++
++ return dbn_24;
++}
++
++/*
++ * eio_expand_dbn
++ *
++ * Expand a 3-byte "dbn" into a 5-byte "dbn" by adding 16 lower bits
++ * of the set number this "dbn" belongs to.
++ */
++sector_t eio_expand_dbn(struct cache_c *dmc, u_int64_t index)
++{
++ u_int32_t dbn_24;
++ u_int64_t set_number;
++ sector_t lsb;
++ sector_t msb;
++ sector_t dbn_40;
++
++ EIO_ASSERT(!EIO_MD8(dmc));
++ /*
++ * Expanding "dbn" zero?
++ */
++ if (index == dmc->index_zero &&
++ dmc->index_zero < (u_int64_t)dmc->assoc)
++ return 0;
++
++ dbn_24 = dmc->cache[index].md4_u.u_i_md4 & EIO_MD4_DBN_MASK;
++ if (dbn_24 == 0 && EIO_CACHE_STATE_GET(dmc, index) == INVALID)
++ return (sector_t)0;
++
++ set_number = EIO_DIV(index, dmc->assoc);
++ lsb = dbn_24 & SECTORS_PER_SET_MASK;
++ msb = dbn_24 >> (SECTORS_PER_SET_SHIFT + 1); /* 1 for wrapped */
++ /* had we wrapped? */
++ if ((dbn_24 & SECTORS_PER_SET) != 0) {
++ dbn_40 = msb << (dmc->num_sets_bits + SECTORS_PER_SET_SHIFT);
++ dbn_40 |= (set_number + dmc->num_sets) << SECTORS_PER_SET_SHIFT;
++ dbn_40 |= lsb;
++ } else {
++ dbn_40 = msb << (dmc->num_sets_bits + SECTORS_PER_SET_SHIFT);
++ dbn_40 |= set_number << SECTORS_PER_SET_SHIFT;
++ dbn_40 |= lsb;
++ }
++ EIO_ASSERT(unlikely(dbn_40 < EIO_MAX_SECTOR));
++
++ return (sector_t)dbn_40;
++}
++EXPORT_SYMBOL(eio_expand_dbn);
++
++/*
++ * eio_invalidate_md
++ */
++void eio_invalidate_md(struct cache_c *dmc, u_int64_t index)
++{
++
++ if (EIO_MD8(dmc))
++ dmc->cache_md8[index].md8_u.u_i_md8 = EIO_MD8_INVALID;
++ else
++ dmc->cache[index].md4_u.u_i_md4 = EIO_MD4_INVALID;
++}
++
++/*
++ * eio_md4_dbn_set
++ */
++void eio_md4_dbn_set(struct cache_c *dmc, u_int64_t index, u_int32_t dbn_24)
++{
++
++ EIO_ASSERT((dbn_24 & ~EIO_MD4_DBN_MASK) == 0);
++
++ /* retain "cache_state" */
++ dmc->cache[index].md4_u.u_i_md4 &= ~EIO_MD4_DBN_MASK;
++ dmc->cache[index].md4_u.u_i_md4 |= dbn_24;
++
++ /* XXX excessive debugging */
++ if (dmc->index_zero < (u_int64_t)dmc->assoc && /* sector 0 cached */
++ index == dmc->index_zero && /* we're accessing sector 0 */
++ dbn_24 != 0) /* we're replacing sector 0 */
++ dmc->index_zero = dmc->assoc;
++}
++
++/*
++ * eio_md8_dbn_set
++ */
++void eio_md8_dbn_set(struct cache_c *dmc, u_int64_t index, sector_t dbn)
++{
++
++ EIO_ASSERT((dbn & ~EIO_MD8_DBN_MASK) == 0);
++
++ /* retain "cache_state" */
++ dmc->cache_md8[index].md8_u.u_i_md8 &= ~EIO_MD8_DBN_MASK;
++ dmc->cache_md8[index].md8_u.u_i_md8 |= dbn;
++
++ /* XXX excessive debugging */
++ if (dmc->index_zero < (u_int64_t)dmc->assoc && /* sector 0 cached */
++ index == dmc->index_zero && /* we're accessing sector 0 */
++ dbn != 0) /* we're replacing sector 0 */
++ dmc->index_zero = dmc->assoc;
++}
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_policy.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_policy.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_policy.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_policy.c 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,146 @@
++/*
++ * eio_policy.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "eio.h"
++
++LIST_HEAD(eio_policy_list);
++
++int eio_register_policy(struct eio_policy_header *new_policy)
++{
++ struct list_head *ptr;
++ struct eio_policy_header *curr;
++
++ list_for_each(ptr, &eio_policy_list) {
++ curr = list_entry(ptr, struct eio_policy_header, sph_list);
++ if (curr->sph_name == new_policy->sph_name)
++ return 1;
++ }
++ list_add_tail(&new_policy->sph_list, &eio_policy_list);
++
++ pr_info("register_policy: policy %d added", new_policy->sph_name);
++
++ return 0;
++}
++EXPORT_SYMBOL(eio_register_policy);
++
++int eio_unregister_policy(struct eio_policy_header *p_ops)
++{
++ struct list_head *ptr;
++ struct eio_policy_header *curr;
++
++ list_for_each(ptr, &eio_policy_list) {
++ curr = list_entry(ptr, struct eio_policy_header, sph_list);
++ if (curr->sph_name == p_ops->sph_name) {
++ list_del(&curr->sph_list);
++ pr_info("unregister_policy: policy %d removed",
++ (int)p_ops->sph_name);
++ return 0;
++ }
++ }
++
++ return 1;
++}
++EXPORT_SYMBOL(eio_unregister_policy);
++
++struct eio_policy *eio_get_policy(int policy)
++{
++ struct list_head *ptr;
++ struct eio_policy_header *curr;
++
++ list_for_each(ptr, &eio_policy_list) {
++ curr = list_entry(ptr, struct eio_policy_header, sph_list);
++ if (curr->sph_name == policy) {
++ pr_info("get_policy: policy %d found", policy);
++ return curr->sph_instance_init();
++ }
++ }
++ pr_info("get_policy: cannot find policy %d", policy);
++
++ return NULL;
++}
++
++/*
++ * Decrement the reference count of the policy specific module
++ * and any other cleanup that is required when an instance of a
++ * policy is no longer required.
++ */
++void eio_put_policy(struct eio_policy *p_ops)
++{
++
++ if (p_ops == NULL) {
++ pr_err("put_policy: Cannot decrement reference" \
++ "count of NULL policy");
++ return;
++ }
++ p_ops->sp_repl_exit();
++}
++
++/*
++ * Wrappers for policy specific functions. These default to nothing if the
++ * default policy is being used.
++ */
++int eio_repl_sets_init(struct eio_policy *p_ops)
++{
++
++ return (p_ops &&
++ p_ops->sp_repl_sets_init) ? p_ops->sp_repl_sets_init(p_ops) : 0;
++}
++
++int eio_repl_blk_init(struct eio_policy *p_ops)
++{
++
++ return (p_ops &&
++ p_ops->sp_repl_blk_init) ? p_ops->sp_repl_blk_init(p_ops) : 0;
++}
++
++void
++eio_find_reclaim_dbn(struct eio_policy *p_ops,
++ index_t start_index, index_t *index)
++{
++
++ p_ops->sp_find_reclaim_dbn(p_ops, start_index, index);
++}
++
++int eio_policy_clean_set(struct eio_policy *p_ops, index_t set, int to_clean)
++{
++
++ return p_ops->sp_clean_set(p_ops, set, to_clean);
++}
++
++/*
++ * LRU Specific functions
++ */
++void eio_policy_lru_pushblks(struct eio_policy *p_ops)
++{
++
++ if (p_ops && p_ops->sp_name == CACHE_REPL_LRU)
++ p_ops->sp_policy.lru->sl_lru_pushblks(p_ops);
++}
++
++void
++eio_policy_reclaim_lru_movetail(struct cache_c *dmc, index_t i,
++ struct eio_policy *p_ops)
++{
++
++ if (p_ops && p_ops->sp_name == CACHE_REPL_LRU)
++ p_ops->sp_policy.lru->sl_reclaim_lru_movetail(dmc, i, p_ops);
++}
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_policy.h linux-linaro-stable-mx6/drivers/block/enhanceio/eio_policy.h
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_policy.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_policy.h 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,105 @@
++/*
++ * eio_policy.h
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef EIO_POLICY_H
++#define EIO_POLICY_H
++
++#include <linux/module.h>
++#include <linux/list.h>
++
++/*
++ * Defines for policy types (EIO_REPL_XXX are in eio.h
++ * so that user space utilties can use those definitions.
++ */
++
++/*
++ * The LRU pointers are maintained as set-relative offsets, instead of
++ * pointers. This enables us to store the LRU pointers per cacheblock
++ * using 4 bytes instead of 16 bytes. The upshot of this is that we
++ * are required to clamp the associativity at an 8K max.
++ *
++ * XXX - The above comment is from the original code. Looks like an error,
++ * maximum associativity should be 32K (2^15) and not 8K.
++ */
++#define EIO_MAX_ASSOC 8192
++#define EIO_LRU_NULL 0xFFFF
++
++/* Declerations to keep the compiler happy */
++struct cache_c;
++struct eio_policy;
++struct eio_lru;
++
++/* LRU specific data structures and functions */
++struct eio_lru {
++ void (*sl_lru_pushblks)(struct eio_policy *);
++ void (*sl_reclaim_lru_movetail)(struct cache_c *, index_t,
++ struct eio_policy *);
++};
++
++/* Function prototypes for LRU wrappers in eio_policy.c */
++void eio_policy_lru_pushblks(struct eio_policy *);
++void eio_policy_reclaim_lru_movetail(struct cache_c *, index_t,
++ struct eio_policy *);
++
++/*
++ * Context that captures the cache block replacement policy.
++ * There is one instance of this struct per dmc (cache)
++ */
++struct eio_policy {
++ int sp_name;
++ union {
++ struct eio_lru *lru;
++ } sp_policy;
++ int (*sp_repl_init)(struct cache_c *);
++ void (*sp_repl_exit)(void);
++ int (*sp_repl_sets_init)(struct eio_policy *);
++ int (*sp_repl_blk_init)(struct eio_policy *);
++ void (*sp_find_reclaim_dbn)(struct eio_policy *,
++ index_t start_index, index_t *index);
++ int (*sp_clean_set)(struct eio_policy *, index_t set, int);
++ struct cache_c *sp_dmc;
++};
++
++/*
++ * List of registered policies. There is one instance
++ * of this structure per policy type.
++ */
++struct eio_policy_header {
++ int sph_name;
++ struct eio_policy *(*sph_instance_init)(void);
++ struct list_head sph_list;
++};
++
++/* Prototypes of generic functions in eio_policy */
++int *eio_repl_init(struct cache_c *);
++int eio_repl_sets_init(struct eio_policy *);
++int eio_repl_blk_init(struct eio_policy *);
++void eio_find_reclaim_dbn(struct eio_policy *, index_t start_index,
++ index_t *index);
++int eio_policy_clean_set(struct eio_policy *, index_t, int);
++
++int eio_register_policy(struct eio_policy_header *);
++int eio_unregister_policy(struct eio_policy_header *);
++struct eio_policy *eio_get_policy(int);
++void eio_put_policy(struct eio_policy *);
++
++#endif /* EIO_POLICY_H */
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_procfs.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_procfs.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_procfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_procfs.c 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,1932 @@
++/*
++ * eio_procfs.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "eio.h"
++#define EIO_RELEASE "ENHANCEIO"
++
++#ifndef ENHANCEIO_GIT_COMMIT_HASH
++#define ENHANCEIO_GIT_COMMIT_HASH "unknown-git-version"
++#endif /* !ENHANCEIO_GIT_COMMIT_HASH */
++
++int eio_version_query(size_t buf_sz, char *bufp)
++{
++ if (unlikely(buf_sz == 0) || unlikely(bufp == NULL))
++ return -EINVAL;
++ snprintf(bufp, buf_sz, "EnhanceIO Version: %s %s (checksum disabled)",
++ EIO_RELEASE, ENHANCEIO_GIT_COMMIT_HASH);
++
++ bufp[buf_sz - 1] = '\0';
++
++ return 0;
++}
++
++static struct sysctl_table_dir *sysctl_handle_dir;
++
++/*
++ * eio_zerostats_sysctl
++ */
++static int
++eio_zerostats_sysctl(ctl_table *table, int write, void __user *buffer,
++ size_t *length, loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ long long cached_blocks;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post the existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.zerostats = dmc->sysctl_active.zerostats;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ /* do sanity check */
++
++ if ((dmc->sysctl_pending.zerostats != 0) &&
++ (dmc->sysctl_pending.zerostats != 1)) {
++ pr_err
++ ("0 or 1 are the only valid values for zerostats");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.zerostats ==
++ dmc->sysctl_active.zerostats)
++ /* same value. Nothing to work */
++ return 0;
++
++ /* Copy to active */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.zerostats = dmc->sysctl_pending.zerostats;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ if (dmc->sysctl_active.zerostats) {
++ /*
++ * The number of cached blocks should not be zero'd since
++ * these blocks are already on cache dev. Making this zero
++ * may lead to -ve count during block invalidate, and also,
++ * incorrectly indicating how much data is cached.
++ *
++ * TODO - should have used an spinlock, but existing spinlocks
++ * are inadequate to fully protect this
++ */
++
++ cached_blocks =
++ atomic64_read(&dmc->eio_stats.cached_blocks);
++ memset(&dmc->eio_stats, 0, sizeof(struct eio_stats));
++ atomic64_set(&dmc->eio_stats.cached_blocks,
++ cached_blocks);
++ }
++ }
++
++ return 0;
++}
++
++/*
++ * eio_mem_limit_pct_sysctl
++ * - sets the eio sysctl mem_limit_pct value
++ */
++static int
++eio_mem_limit_pct_sysctl(ctl_table *table, int write, void __user *buffer,
++ size_t *length, loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post the existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.mem_limit_pct =
++ dmc->sysctl_active.mem_limit_pct;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ /* do sanity check */
++ if ((dmc->sysctl_pending.mem_limit_pct < 0) ||
++ (dmc->sysctl_pending.mem_limit_pct > 100)) {
++ pr_err
++ ("only valid percents are [0 - 100] for mem_limit_pct");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.mem_limit_pct ==
++ dmc->sysctl_active.mem_limit_pct)
++ /* same value. Nothing more to do */
++ return 0;
++
++ /* Copy to active */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.mem_limit_pct =
++ dmc->sysctl_pending.mem_limit_pct;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ return 0;
++}
++
++/*
++ * eio_clean_sysctl
++ */
++static int
++eio_clean_sysctl(ctl_table *table, int write, void __user *buffer,
++ size_t *length, loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post the existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.do_clean = dmc->sysctl_active.do_clean;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ /* Do sanity check */
++
++ if (dmc->mode != CACHE_MODE_WB) {
++ /* do_clean is only valid for writeback cache */
++ pr_err("do_clean is only valid for writeback cache");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.
++ do_clean & ~(EIO_CLEAN_START | EIO_CLEAN_KEEP)) {
++ pr_err
++ ("do_clean should be either clean start/clean keep");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.do_clean == dmc->sysctl_active.do_clean)
++ /* New and old values are same. No work required */
++ return 0;
++
++ /* Copy to active and apply the new tunable value */
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++
++ if (dmc->cache_flags & CACHE_FLAGS_MOD_INPROG) {
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ pr_err
++ ("do_clean called while cache modification in progress");
++ return -EBUSY;
++ } else {
++ dmc->sysctl_active.do_clean =
++ dmc->sysctl_pending.do_clean;
++
++ if (dmc->sysctl_active.do_clean) {
++ atomic_set(&dmc->clean_index, 0);
++ dmc->sysctl_active.do_clean |= EIO_CLEAN_START;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ flags);
++
++ /*
++ * Wake up the clean thread.
++ * Sync thread will do the clean and once complete
++ * will reset the clean_start flag.
++ * The clean_keep flag will remain set(unless reset
++ * by user) and will prevent new I/Os from making
++ * the blocks dirty.
++ */
++
++ spin_lock_irqsave(&dmc->clean_sl, flags);
++ EIO_SET_EVENT_AND_UNLOCK(&dmc->clean_event,
++ &dmc->clean_sl, flags);
++ } else
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ flags);
++ }
++ }
++
++ return 0;
++}
++
++/*
++ * eio_dirty_high_threshold_sysctl
++ */
++static int
++eio_dirty_high_threshold_sysctl(ctl_table *table, int write,
++ void __user *buffer, size_t *length,
++ loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post the existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.dirty_high_threshold =
++ dmc->sysctl_active.dirty_high_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ int error;
++ uint32_t old_value;
++
++ /* do sanity check */
++
++ if (dmc->mode != CACHE_MODE_WB) {
++ pr_err
++ ("dirty_high_threshold is only valid for writeback cache");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_high_threshold > 100) {
++ pr_err
++ ("dirty_high_threshold percentage should be [0 - 100]");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_high_threshold <
++ dmc->sysctl_active.dirty_low_threshold) {
++ pr_err
++ ("dirty high shouldn't be less than dirty low threshold");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_high_threshold ==
++ dmc->sysctl_active.dirty_high_threshold)
++ /* new is same as old value. No need to take any action */
++ return 0;
++
++ /* update the active value with the new tunable value */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ old_value = dmc->sysctl_active.dirty_high_threshold;
++ dmc->sysctl_active.dirty_high_threshold =
++ dmc->sysctl_pending.dirty_high_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ /* Store the change persistently */
++ error = eio_sb_store(dmc);
++ if (error) {
++ /* restore back the old value and return error */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.dirty_high_threshold = old_value;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ return error;
++ }
++
++ /* if we reduced the high threshold, check if we require cache cleaning */
++ if (old_value > dmc->sysctl_active.dirty_high_threshold)
++ eio_comply_dirty_thresholds(dmc, -1);
++ }
++
++ return 0;
++}
++
++/*
++ * eio_dirty_low_threshold_sysctl
++ */
++static int
++eio_dirty_low_threshold_sysctl(ctl_table *table, int write,
++ void __user *buffer, size_t *length,
++ loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post the existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.dirty_low_threshold =
++ dmc->sysctl_active.dirty_low_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ int error;
++ uint32_t old_value;
++
++ /* do sanity check */
++
++ if (dmc->mode != CACHE_MODE_WB) {
++ pr_err
++ ("dirty_low_threshold is valid for only writeback cache");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_low_threshold > 100) {
++ pr_err
++ ("dirty_low_threshold percentage should be [0 - 100]");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_low_threshold >
++ dmc->sysctl_active.dirty_high_threshold) {
++ pr_err
++ ("dirty low shouldn't be more than dirty high threshold");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_low_threshold ==
++ dmc->sysctl_active.dirty_low_threshold)
++ /* new is same as old value. No need to take any action */
++ return 0;
++
++ /* update the active value with the new tunable value */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ old_value = dmc->sysctl_active.dirty_low_threshold;
++ dmc->sysctl_active.dirty_low_threshold =
++ dmc->sysctl_pending.dirty_low_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ /* Store the change persistently */
++ error = eio_sb_store(dmc);
++ if (error) {
++ /* restore back the old value and return error */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.dirty_low_threshold = old_value;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ return error;
++ }
++
++ if (old_value > dmc->sysctl_active.dirty_low_threshold)
++ /*
++ * Although the low threshold set shouldn't trigger new cleans,
++ * but because we set the tunables one at a time from user mode,
++ * it is possible that the high threshold value triggering clean
++ * did not happen and should get triggered now that the low value
++ * has been changed, so we are calling the comply function here
++ */
++ eio_comply_dirty_thresholds(dmc, -1);
++ }
++
++ return 0;
++}
++
++/*
++ * eio_dirty_set_high_threshold_sysctl
++ */
++static int
++eio_dirty_set_high_threshold_sysctl(ctl_table *table, int write,
++ void __user *buffer, size_t *length,
++ loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post the existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.dirty_set_high_threshold =
++ dmc->sysctl_active.dirty_set_high_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ int error;
++ uint32_t old_value;
++ u_int64_t i;
++
++ /* do sanity check */
++
++ if (dmc->mode != CACHE_MODE_WB) {
++ pr_err
++ ("dirty_set_high_threshold is valid only for writeback cache");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_set_high_threshold > 100) {
++ pr_err
++ ("dirty_set_high_threshold percentage should be [0 - 100]");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_set_high_threshold <
++ dmc->sysctl_active.dirty_set_low_threshold) {
++ pr_err
++ ("dirty_set_high_threshold shouldn't be less than dirty low threshold");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_set_high_threshold ==
++ dmc->sysctl_active.dirty_set_high_threshold)
++ /* new is same as old value. No need to take any action */
++ return 0;
++
++ /* update the active value with the new tunable value */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ old_value = dmc->sysctl_active.dirty_set_high_threshold;
++ dmc->sysctl_active.dirty_set_high_threshold =
++ dmc->sysctl_pending.dirty_set_high_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ /* Store the change persistently */
++ error = eio_sb_store(dmc);
++ if (error) {
++ /* restore back the old value and return error */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.dirty_set_high_threshold = old_value;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ return error;
++ }
++
++ if (old_value > dmc->sysctl_active.dirty_set_high_threshold) {
++ /* Check each set for dirty blocks cleaning */
++ for (i = 0; i < (dmc->size >> dmc->consecutive_shift);
++ i++)
++ eio_comply_dirty_thresholds(dmc, i);
++ }
++ }
++
++ return 0;
++}
++
++/*
++ * eio_dirty_set_low_threshold_sysctl
++ */
++static int
++eio_dirty_set_low_threshold_sysctl(ctl_table *table, int write,
++ void __user *buffer, size_t *length,
++ loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post the existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.dirty_set_low_threshold =
++ dmc->sysctl_active.dirty_set_low_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ int error;
++ uint32_t old_value;
++ u_int64_t i;
++
++ /* do sanity check */
++
++ if (dmc->mode != CACHE_MODE_WB) {
++ pr_err
++ ("dirty_set_low_threshold is valid only for writeback cache");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_set_low_threshold > 100) {
++ pr_err
++ ("dirty_set_low_threshold percentage should be [0 - 100]");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_set_low_threshold >
++ dmc->sysctl_active.dirty_set_high_threshold) {
++ pr_err
++ ("dirty_set_low_threshold shouldn't be more than dirty_set_high_threshold");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.dirty_set_low_threshold ==
++ dmc->sysctl_active.dirty_set_low_threshold)
++ /* new is same as old value. No need to take any action */
++ return 0;
++
++ /* update the active value with the new tunable value */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ old_value = dmc->sysctl_active.dirty_set_low_threshold;
++ dmc->sysctl_active.dirty_set_low_threshold =
++ dmc->sysctl_pending.dirty_set_low_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ /* Store the change persistently */
++ error = eio_sb_store(dmc);
++ if (error) {
++ /* restore back the old value and return error */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.dirty_set_low_threshold = old_value;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ return error;
++ }
++
++ /*
++ * Although the low threshold value shouldn't trigger new cleans,
++ * but because we set the tunables one at a time from user mode,
++ * it is possible that the high threshold value triggering clean
++ * did not happen and should get triggered now that the low value
++ * has been changed, so we are calling the comply function again
++ */
++ if (old_value > dmc->sysctl_active.dirty_set_low_threshold) {
++ /* Check each set for dirty blocks cleaning */
++ for (i = 0; i < (dmc->size >> dmc->consecutive_shift);
++ i++)
++ eio_comply_dirty_thresholds(dmc, i);
++ }
++ }
++
++ return 0;
++}
++
++/*
++ * eio_autoclean_threshold_sysctl
++ */
++static int
++eio_autoclean_threshold_sysctl(ctl_table *table, int write,
++ void __user *buffer, size_t *length,
++ loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.autoclean_threshold =
++ dmc->sysctl_active.autoclean_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ int error;
++ int old_value;
++
++ /* do sanity check */
++
++ if (dmc->mode != CACHE_MODE_WB) {
++ pr_err
++ ("autoclean_threshold is valid only for writeback cache");
++ return -EINVAL;
++ }
++
++ if ((dmc->sysctl_pending.autoclean_threshold < 0) ||
++ (dmc->sysctl_pending.autoclean_threshold >
++ AUTOCLEAN_THRESH_MAX)) {
++ pr_err("autoclean_threshold is valid range is 0 to %d",
++ AUTOCLEAN_THRESH_MAX);
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.autoclean_threshold ==
++ dmc->sysctl_active.autoclean_threshold)
++ /* new is same as old value. No need to take any action */
++ return 0;
++
++ /* update the active value with the new tunable value */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ old_value = dmc->sysctl_active.autoclean_threshold;
++ dmc->sysctl_active.autoclean_threshold =
++ dmc->sysctl_pending.autoclean_threshold;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ /* Store the change persistently */
++ error = eio_sb_store(dmc);
++ if (error) {
++ /* restore back the old value and return error */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.autoclean_threshold = old_value;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ return error;
++ }
++
++ /* Ensure new thresholds are being complied */
++ eio_comply_dirty_thresholds(dmc, -1);
++ }
++
++ return 0;
++}
++
++/*
++ * eio_time_based_clean_interval_sysctl
++ */
++static int
++eio_time_based_clean_interval_sysctl(ctl_table *table, int write,
++ void __user *buffer, size_t *length,
++ loff_t *ppos)
++{
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value or post existing value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.time_based_clean_interval =
++ dmc->sysctl_active.time_based_clean_interval;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ int error;
++ uint32_t old_value;
++
++ /* do sanity check */
++
++ if (dmc->mode != CACHE_MODE_WB) {
++ pr_err
++ ("time_based_clean_interval is valid only for writeback cache");
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.time_based_clean_interval >
++ TIME_BASED_CLEAN_INTERVAL_MAX) {
++ /* valid values are 0 to TIME_BASED_CLEAN_INTERVAL_MAX */
++ pr_err
++ ("time_based_clean_interval valid range is 0 to %u",
++ TIME_BASED_CLEAN_INTERVAL_MAX);
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.time_based_clean_interval ==
++ dmc->sysctl_active.time_based_clean_interval)
++ /* new is same as old value */
++ return 0;
++
++ /* update the active value with the new tunable value */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ old_value = dmc->sysctl_active.time_based_clean_interval;
++ dmc->sysctl_active.time_based_clean_interval =
++ dmc->sysctl_pending.time_based_clean_interval;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ /* Store the change persistently */
++ error = eio_sb_store(dmc);
++ if (error) {
++ /* restore back the old value and return error */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.time_based_clean_interval =
++ old_value;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ return error;
++ }
++
++ /* Reschedule the time based clean, based on new interval */
++ cancel_delayed_work_sync(&dmc->clean_aged_sets_work);
++ spin_lock_irqsave(&dmc->dirty_set_lru_lock, flags);
++ dmc->is_clean_aged_sets_sched = 0;
++ if (dmc->sysctl_active.time_based_clean_interval
++ && atomic64_read(&dmc->nr_dirty)) {
++ schedule_delayed_work(&dmc->clean_aged_sets_work,
++ dmc->sysctl_active.
++ time_based_clean_interval * 60 *
++ HZ);
++ dmc->is_clean_aged_sets_sched = 1;
++ }
++ spin_unlock_irqrestore(&dmc->dirty_set_lru_lock, flags);
++ }
++
++ return 0;
++}
++
++static void eio_sysctl_register_writeback(struct cache_c *dmc);
++static void eio_sysctl_unregister_writeback(struct cache_c *dmc);
++static void eio_sysctl_register_invalidate(struct cache_c *dmc);
++static void eio_sysctl_unregister_invalidate(struct cache_c *dmc);
++
++/*
++ * eio_control_sysctl
++ */
++int
++eio_control_sysctl(ctl_table *table, int write, void __user *buffer,
++ size_t *length, loff_t *ppos)
++{
++ int rv = 0;
++ struct cache_c *dmc = (struct cache_c *)table->extra1;
++ unsigned long flags = 0;
++
++ /* fetch the new tunable value */
++
++ if (!write) {
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_pending.control = dmc->sysctl_active.control;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++ }
++
++ proc_dointvec(table, write, buffer, length, ppos);
++
++ /* do write processing */
++
++ if (write) {
++ /* do sanity check */
++
++ if (dmc->sysctl_pending.control > CACHE_CONTROL_FLAG_MAX ||
++ dmc->sysctl_pending.control < 0) {
++ /* valid values are from 0 till CACHE_CONTROL_FLAG_MAX */
++ pr_err("control valid values are from 0 till %d",
++ CACHE_CONTROL_FLAG_MAX);
++ return -EINVAL;
++ }
++
++ if (dmc->sysctl_pending.control == dmc->sysctl_active.control)
++ /* new is same as old value. No work required */
++ return 0;
++
++ /* update the active value with the new tunable value */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.control = dmc->sysctl_pending.control;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ switch (dmc->sysctl_active.control) {
++ case CACHE_VERBOSE_OFF:
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_VERBOSE;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ pr_info("Turning off verbose mode");
++ break;
++ case CACHE_VERBOSE_ON:
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags |= CACHE_FLAGS_VERBOSE;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ pr_info("Turning on verbose mode");
++ break;
++ case CACHE_WRITEBACK_ON:
++ if (dmc->sysctl_handle_writeback == NULL)
++ eio_sysctl_register_writeback(dmc);
++ break;
++ case CACHE_WRITEBACK_OFF:
++ if (dmc->sysctl_handle_writeback)
++ eio_sysctl_unregister_writeback(dmc);
++ break;
++ case CACHE_INVALIDATE_ON:
++ if (dmc->sysctl_handle_invalidate == NULL) {
++ eio_sysctl_register_invalidate(dmc);
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags |= CACHE_FLAGS_INVALIDATE;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->
++ cache_spin_lock_flags);
++ } else
++ pr_info("Invalidate API already registered");
++ break;
++ case CACHE_INVALIDATE_OFF:
++ if (dmc->sysctl_handle_invalidate) {
++ eio_sysctl_unregister_invalidate(dmc);
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_INVALIDATE;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->
++ cache_spin_lock_flags);
++ } else
++ pr_info("Invalidate API not registered");
++ break;
++ case CACHE_FAST_REMOVE_ON:
++ if (dmc->mode != CACHE_MODE_WB) {
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags |= CACHE_FLAGS_FAST_REMOVE;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->
++ cache_spin_lock_flags);
++ if (CACHE_VERBOSE_IS_SET(dmc))
++ pr_info("Turning on fast remove");
++ } else {
++#ifdef EIO_DEBUG
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags |= CACHE_FLAGS_FAST_REMOVE;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->
++ cache_spin_lock_flags);
++ if (CACHE_VERBOSE_IS_SET(dmc))
++ pr_info("Turning on fast remove");
++#else
++ pr_err("Invalid control value: 0x%x",
++ dmc->sysctl_active.control);
++ rv = -1;
++#endif /* EIO_DEBUG */
++ }
++ break;
++ case CACHE_FAST_REMOVE_OFF:
++ if (dmc->mode != CACHE_MODE_WB) {
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_FAST_REMOVE;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->
++ cache_spin_lock_flags);
++ if (CACHE_VERBOSE_IS_SET(dmc))
++ pr_info("Turning off fast remove");
++ } else {
++#ifdef EIO_DEBUG
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_FAST_REMOVE;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->
++ cache_spin_lock_flags);
++ if (CACHE_VERBOSE_IS_SET(dmc))
++ pr_info("Turning off fast remove");
++#else
++ pr_err("Invalid control value: 0x%x",
++ dmc->sysctl_active.control);
++ rv = -1;
++#endif /* EIO_DEBUG */
++ }
++ break;
++ default:
++ pr_err("Invalid control value: 0x%x",
++ dmc->sysctl_active.control);
++ rv = -1;
++ }
++ }
++
++ return rv;
++}
++
++#define PROC_STR "enhanceio"
++#define PROC_VER_STR "enhanceio/version"
++#define PROC_STATS "stats"
++#define PROC_ERRORS "errors"
++#define PROC_IOSZ_HIST "io_hist"
++#define PROC_CONFIG "config"
++
++static int eio_invalidate_sysctl(ctl_table *table, int write,
++ void __user *buffer, size_t *length,
++ loff_t *ppos);
++static void *eio_find_sysctl_data(struct cache_c *dmc, ctl_table *vars);
++static char *eio_cons_sysctl_devname(struct cache_c *dmc);
++static char *eio_cons_procfs_cachename(struct cache_c *dmc,
++ char *path_component);
++static void eio_sysctl_register_common(struct cache_c *dmc);
++static void eio_sysctl_unregister_common(struct cache_c *dmc);
++static void eio_sysctl_register_dir(void);
++static void eio_sysctl_unregister_dir(void);
++static int eio_stats_show(struct seq_file *seq, void *v);
++static int eio_stats_open(struct inode *inode, struct file *file);
++static int eio_errors_show(struct seq_file *seq, void *v);
++static int eio_errors_open(struct inode *inode, struct file *file);
++static int eio_iosize_hist_show(struct seq_file *seq, void *v);
++static int eio_iosize_hist_open(struct inode *inode, struct file *file);
++static int eio_version_show(struct seq_file *seq, void *v);
++static int eio_version_open(struct inode *inode, struct file *file);
++static int eio_config_show(struct seq_file *seq, void *v);
++static int eio_config_open(struct inode *inode, struct file *file);
++
++static const struct file_operations eio_version_operations = {
++ .open = eio_version_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static const struct file_operations eio_stats_operations = {
++ .open = eio_stats_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static const struct file_operations eio_errors_operations = {
++ .open = eio_errors_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static const struct file_operations eio_iosize_hist_operations = {
++ .open = eio_iosize_hist_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static const struct file_operations eio_config_operations = {
++ .open = eio_config_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++/*
++ * Each ctl_table array needs to be 1 more than the actual number of
++ * entries - zero padded at the end ! Therefore the NUM_*_SYSCTLS
++ * is 1 more than then number of sysctls.
++ */
++
++#define PROC_SYS_ROOT_NAME "dev"
++#define PROC_SYS_DIR_NAME "enhanceio"
++#define PROC_SYS_CACHE_NAME "enhanceio-dev"
++
++/*
++ * The purpose of sysctl_table_dir is to create the "enhanceio"
++ * dir under /proc/sys/dev/. The creation is done during module
++ * load time and the dir is removed when module is removed.
++ *
++ * This was added because otherwise, the first cache instance
++ * falsely assumes that /proc/sys/kernel/ is its parent instead
++ * of /proc/sys/dev leading to an incorrect number of reference
++ * count. When you have multiple cache instances, removing the
++ * last one results in the kernel's reference count to be 0
++ * leading to a kernel warning at runtime. Hopefully, this will
++ * be fixed in the kernel sometime.
++ */
++static struct sysctl_table_dir {
++ struct ctl_table_header *sysctl_header;
++ ctl_table vars[0 + 1];
++ ctl_table dev[0 + 1];
++ ctl_table dir[1 + 1];
++ ctl_table root[1 + 1];
++} sysctl_template_dir = {
++ .vars = {
++ }, .dev = {
++ }, .dir = {
++ {
++ .procname = PROC_SYS_DIR_NAME,
++ .maxlen = 0,
++ .mode = S_IRUGO | S_IXUGO,
++ .child = sysctl_template_dir.dev,
++ },
++ }, .root = {
++ {
++ .procname = PROC_SYS_ROOT_NAME,
++ .maxlen = 0,
++ .mode = 0555,
++ .child = sysctl_template_dir.dir,
++ },
++ },
++};
++
++#define NUM_COMMON_SYSCTLS 3
++
++static struct sysctl_table_common {
++ struct ctl_table_header *sysctl_header;
++ ctl_table vars[NUM_COMMON_SYSCTLS + 1];
++ ctl_table dev[1 + 1];
++ ctl_table dir[1 + 1];
++ ctl_table root[1 + 1];
++} sysctl_template_common = {
++ .vars = {
++ { /* 1 */
++ .procname = "zero_stats",
++ .maxlen = sizeof(int),
++ .mode = 0644,
++ .proc_handler = &eio_zerostats_sysctl,
++ }, { /* 2 */
++ .procname = "mem_limit_pct",
++ .maxlen = sizeof(int),
++ .mode = 0644,
++ .proc_handler = &eio_mem_limit_pct_sysctl,
++ }, { /* 3 */
++ .procname = "control",
++ .maxlen = sizeof(int),
++ .mode = 0644,
++ .proc_handler = &eio_control_sysctl,
++ },
++ }, .dev = {
++ {
++ .procname = PROC_SYS_CACHE_NAME,
++ .maxlen = 0,
++ .mode = S_IRUGO | S_IXUGO,
++ .child = sysctl_template_common.vars,
++ },
++ }, .dir = {
++ {
++ .procname = PROC_SYS_DIR_NAME,
++ .maxlen = 0,
++ .mode = S_IRUGO | S_IXUGO,
++ .child = sysctl_template_common.dev,
++ },
++ }, .root = {
++ {
++ .procname = PROC_SYS_ROOT_NAME,
++ .maxlen = 0,
++ .mode = 0555,
++ .child = sysctl_template_common.dir,
++ },
++ },
++};
++
++#define NUM_WRITEBACK_SYSCTLS 7
++
++static struct sysctl_table_writeback {
++ struct ctl_table_header *sysctl_header;
++ ctl_table vars[NUM_WRITEBACK_SYSCTLS + 1];
++ ctl_table dev[1 + 1];
++ ctl_table dir[1 + 1];
++ ctl_table root[1 + 1];
++} sysctl_template_writeback = {
++ .vars = {
++ { /* 1 */
++ .procname = "do_clean",
++ .maxlen = sizeof(int),
++ .mode = 0644,
++ .proc_handler = &eio_clean_sysctl,
++ }, { /* 2 */
++ .procname = "time_based_clean_interval",
++ .maxlen = sizeof(unsigned int),
++ .mode = 0644,
++ .proc_handler = &eio_time_based_clean_interval_sysctl,
++ }, { /* 3 */
++ .procname = "autoclean_threshold",
++ .maxlen = sizeof(int),
++ .mode = 0644,
++ .proc_handler = &eio_autoclean_threshold_sysctl,
++ }, { /* 4 */
++ .procname = "dirty_high_threshold",
++ .maxlen = sizeof(uint32_t),
++ .mode = 0644,
++ .proc_handler = &eio_dirty_high_threshold_sysctl,
++ }
++ , { /* 5 */
++ .procname = "dirty_low_threshold",
++ .maxlen = sizeof(uint32_t),
++ .mode = 0644,
++ .proc_handler = &eio_dirty_low_threshold_sysctl,
++ }
++ , { /* 6 */
++ .procname = "dirty_set_high_threshold",
++ .maxlen = sizeof(uint32_t),
++ .mode = 0644,
++ .proc_handler = &eio_dirty_set_high_threshold_sysctl,
++ }
++ , { /* 7 */
++ .procname = "dirty_set_low_threshold",
++ .maxlen = sizeof(uint32_t),
++ .mode = 0644,
++ .proc_handler = &eio_dirty_set_low_threshold_sysctl,
++ }
++ ,
++ }
++ , .dev = {
++ {
++ .procname = PROC_SYS_CACHE_NAME,
++ .maxlen = 0,
++ .mode = S_IRUGO | S_IXUGO,
++ .child = sysctl_template_writeback.vars,
++ }
++ ,
++ }
++ , .dir = {
++ {
++ .procname = PROC_SYS_DIR_NAME,
++ .maxlen = 0,
++ .mode = S_IRUGO | S_IXUGO,
++ .child = sysctl_template_writeback.dev,
++ }
++ ,
++ }
++ , .root = {
++ {
++ .procname = PROC_SYS_ROOT_NAME,
++ .maxlen = 0,
++ .mode = 0555,
++ .child = sysctl_template_writeback.dir,
++ }
++ ,
++ }
++ ,
++};
++
++#define NUM_INVALIDATE_SYSCTLS (1)
++static struct sysctl_table_invalidate {
++ struct ctl_table_header *sysctl_header;
++ ctl_table vars[NUM_INVALIDATE_SYSCTLS + 1];
++ ctl_table dev[1 + 1];
++ ctl_table dir[1 + 1];
++ ctl_table root[1 + 1];
++} sysctl_template_invalidate = {
++ .vars = {
++ { /* 1 */
++ .procname = "invalidate",
++ .maxlen = sizeof(u_int64_t),
++ .mode = 0644,
++ .proc_handler = &eio_invalidate_sysctl,
++ }
++ ,
++ }
++ , .dev = {
++ {
++ .procname = PROC_SYS_CACHE_NAME,
++ .maxlen = 0,
++ .mode = S_IRUGO | S_IXUGO,
++ .child = sysctl_template_invalidate.vars,
++ }
++ ,
++ }
++ , .dir = {
++ {
++ .procname = PROC_SYS_DIR_NAME,
++ .maxlen = 0,
++ .mode = S_IRUGO | S_IXUGO,
++ .child = sysctl_template_invalidate.dev,
++ }
++ ,
++ }
++ , .root = {
++ {
++ .procname = PROC_SYS_ROOT_NAME,
++ .maxlen = 0,
++ .mode = 0555,
++ .child = sysctl_template_invalidate.dir,
++ }
++ ,
++ }
++ ,
++};
++
++/*
++ * eio_module_procfs_init -- called from "eio_init()"
++ */
++void eio_module_procfs_init(void)
++{
++ struct proc_dir_entry *entry;
++
++ if (proc_mkdir(PROC_STR, NULL)) {
++ entry = proc_create_data(PROC_VER_STR, 0, NULL,
++ &eio_version_operations, NULL);
++ }
++ eio_sysctl_register_dir();
++}
++
++/*
++ * eio_module_procfs_exit -- called from "eio_exit()"
++ */
++void eio_module_procfs_exit(void)
++{
++ (void)remove_proc_entry(PROC_VER_STR, NULL);
++ (void)remove_proc_entry(PROC_STR, NULL);
++
++ eio_sysctl_unregister_dir();
++}
++
++/*
++ * eio_procfs_ctr -- called from "eio_ctr()"
++ */
++void eio_procfs_ctr(struct cache_c *dmc)
++{
++ char *s;
++ struct proc_dir_entry *entry;
++
++ s = eio_cons_procfs_cachename(dmc, "");
++ entry = proc_mkdir(s, NULL);
++ kfree(s);
++ if (entry == NULL) {
++ pr_err("Failed to create /proc/%s", s);
++ return;
++ }
++
++ s = eio_cons_procfs_cachename(dmc, PROC_STATS);
++ entry = proc_create_data(s, 0, NULL, &eio_stats_operations, dmc);
++ kfree(s);
++
++ s = eio_cons_procfs_cachename(dmc, PROC_ERRORS);
++ entry = proc_create_data(s, 0, NULL, &eio_errors_operations, dmc);
++ kfree(s);
++
++ s = eio_cons_procfs_cachename(dmc, PROC_IOSZ_HIST);
++ entry = proc_create_data(s, 0, NULL, &eio_iosize_hist_operations, dmc);
++ kfree(s);
++
++ s = eio_cons_procfs_cachename(dmc, PROC_CONFIG);
++ entry = proc_create_data(s, 0, NULL, &eio_config_operations, dmc);
++ kfree(s);
++
++ eio_sysctl_register_common(dmc);
++ if (dmc->mode == CACHE_MODE_WB)
++ eio_sysctl_register_writeback(dmc);
++ if (CACHE_INVALIDATE_IS_SET(dmc))
++ eio_sysctl_register_invalidate(dmc);
++}
++
++/*
++ * eio_procfs_dtr -- called from "eio_dtr()"
++ */
++void eio_procfs_dtr(struct cache_c *dmc)
++{
++ char *s;
++
++ s = eio_cons_procfs_cachename(dmc, PROC_STATS);
++ remove_proc_entry(s, NULL);
++ kfree(s);
++
++ s = eio_cons_procfs_cachename(dmc, PROC_ERRORS);
++ remove_proc_entry(s, NULL);
++ kfree(s);
++
++ s = eio_cons_procfs_cachename(dmc, PROC_IOSZ_HIST);
++ remove_proc_entry(s, NULL);
++ kfree(s);
++
++ s = eio_cons_procfs_cachename(dmc, PROC_CONFIG);
++ remove_proc_entry(s, NULL);
++ kfree(s);
++
++ s = eio_cons_procfs_cachename(dmc, "");
++ remove_proc_entry(s, NULL);
++ kfree(s);
++
++ if (dmc->sysctl_handle_invalidate)
++ eio_sysctl_unregister_invalidate(dmc);
++ if (dmc->sysctl_handle_writeback)
++ eio_sysctl_unregister_writeback(dmc);
++ eio_sysctl_unregister_common(dmc);
++}
++
++static spinlock_t invalidate_spin_lock;
++
++/*
++ * eio_invalidate_sysctl
++ */
++static int
++eio_invalidate_sysctl(ctl_table *table, int write, void __user *buffer,
++ size_t *length, loff_t *ppos)
++{
++ static int have_sector;
++ static u_int64_t sector;
++ static u_int64_t num_sectors;
++ int rv;
++ unsigned long int flags;
++ struct cache_c *dmc;
++
++ spin_lock_irqsave(&invalidate_spin_lock, flags);
++
++ dmc = (struct cache_c *)table->extra1;
++ if (dmc == NULL) {
++ pr_err
++ ("Cannot invalidate due to unexpected NULL cache pointer");
++ spin_unlock_irqrestore(&invalidate_spin_lock, flags);
++ return -EBUSY;
++ }
++
++ table->extra1 = NULL;
++ proc_doulongvec_minmax(table, write, buffer, length, ppos);
++ table->extra1 = dmc;
++
++ spin_unlock_irqrestore(&invalidate_spin_lock, flags);
++
++ rv = 0;
++
++ if (write) {
++ /* TBD. Need to put appropriate sanity checks */
++
++ /* update the active value with the new tunable value */
++ spin_lock_irqsave(&dmc->cache_spin_lock, flags);
++ dmc->sysctl_active.invalidate = dmc->sysctl_pending.invalidate;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock, flags);
++
++ /* apply the new tunable value */
++
++ if (have_sector) {
++ num_sectors = dmc->sysctl_active.invalidate;
++
++ rv = eio_invalidate_sanity_check(dmc, sector,
++ &num_sectors);
++
++ /* Invalidate only if sanity passes and reset the return value. */
++ if (rv == 0)
++ eio_inval_range(dmc, sector,
++ (unsigned)
++ to_bytes(num_sectors));
++
++ rv = 0;
++ have_sector = 0;
++
++ } else {
++ sector = dmc->sysctl_active.invalidate;
++ have_sector = 1;
++ num_sectors = 0;
++ }
++ }
++
++ if (CACHE_VERBOSE_IS_SET(dmc) && num_sectors) {
++ pr_info
++ ("eio_inval_range: Invalidated sector range from sector=%lu to sector=%lu",
++ (long unsigned int)sector, (long unsigned int)num_sectors);
++ }
++
++ return rv;
++}
++
++/*
++ * eio_find_sysctl_data
++ */
++static void *eio_find_sysctl_data(struct cache_c *dmc, ctl_table *vars)
++{
++
++ if (strcmp(vars->procname, "do_clean") == 0)
++ return (void *)&dmc->sysctl_pending.do_clean;
++ if (strcmp(vars->procname, "time_based_clean_interval") == 0)
++ return (void *)&dmc->sysctl_pending.time_based_clean_interval;
++ if (strcmp(vars->procname, "dirty_high_threshold") == 0)
++ return (void *)&dmc->sysctl_pending.dirty_high_threshold;
++ if (strcmp(vars->procname, "dirty_low_threshold") == 0)
++ return (void *)&dmc->sysctl_pending.dirty_low_threshold;
++ if (strcmp(vars->procname, "dirty_set_high_threshold") == 0)
++ return (void *)&dmc->sysctl_pending.dirty_set_high_threshold;
++ if (strcmp(vars->procname, "dirty_set_low_threshold") == 0)
++ return (void *)&dmc->sysctl_pending.dirty_set_low_threshold;
++ if (strcmp(vars->procname, "autoclean_threshold") == 0)
++ return (void *)&dmc->sysctl_pending.autoclean_threshold;
++ if (strcmp(vars->procname, "zero_stats") == 0)
++ return (void *)&dmc->sysctl_pending.zerostats;
++ if (strcmp(vars->procname, "mem_limit_pct") == 0)
++ return (void *)&dmc->sysctl_pending.mem_limit_pct;
++ if (strcmp(vars->procname, "control") == 0)
++ return (void *)&dmc->sysctl_pending.control;
++ if (strcmp(vars->procname, "invalidate") == 0)
++ return (void *)&dmc->sysctl_pending.invalidate;
++
++ pr_err("Cannot find sysctl data for %s", vars->procname);
++ return NULL;
++}
++
++/*
++ * eio_cons_sysctl_devname
++ */
++static char *eio_cons_sysctl_devname(struct cache_c *dmc)
++{
++ char *pathname;
++
++ if (dmc->cache_name[0]) {
++ pathname = kzalloc(strlen(dmc->cache_name) + 1, GFP_KERNEL);
++ if (pathname)
++ strcpy(pathname, dmc->cache_name);
++ else
++ pr_err("Failed to allocate memory");
++ } else {
++ pr_err("Cache name is NULL");
++ pathname = NULL;
++ }
++
++ return pathname;
++}
++
++/*
++ * eio_cons_procfs_cachename
++ */
++static char *eio_cons_procfs_cachename(struct cache_c *dmc,
++ char *path_component)
++{
++ char *pathname;
++
++ if (dmc->cache_name[0]) {
++ pathname =
++ kzalloc(strlen(PROC_SYS_DIR_NAME) + 1 +
++ strlen(dmc->cache_name) + 1 +
++ strlen(path_component) + 1, GFP_KERNEL);
++ if (pathname) {
++ strcpy(pathname, PROC_SYS_DIR_NAME);
++ strcat(pathname, "/");
++ strcat(pathname, dmc->cache_name);
++ if (strcmp(path_component, "") != 0) {
++ strcat(pathname, "/");
++ strcat(pathname, path_component);
++ }
++ } else
++ pr_err("Failed to allocate memory");
++ } else {
++ pr_err("Cache name is NULL");
++ pathname = NULL;
++ }
++
++ return pathname;
++}
++
++static void eio_sysctl_register_dir(void)
++{
++ struct sysctl_table_dir *dir;
++
++ dir =
++ kmemdup(&sysctl_template_dir, sizeof(sysctl_template_dir),
++ GFP_KERNEL);
++ if (unlikely(dir == NULL)) {
++ pr_err("Failed to allocate memory for dir sysctl");
++ return;
++ }
++
++ dir->dir[0].child = dir->dev;
++ dir->root[0].child = dir->dir;
++ dir->sysctl_header = register_sysctl_table(dir->root);
++ if (unlikely(dir->sysctl_header == NULL)) {
++ pr_err("Failed to register dir sysctl");
++ goto out;
++ }
++
++ sysctl_handle_dir = dir;
++ return;
++out:
++ kfree(dir);
++}
++
++static void eio_sysctl_unregister_dir(void)
++{
++ if (sysctl_handle_dir != NULL) {
++ unregister_sysctl_table(sysctl_handle_dir->sysctl_header);
++ kfree(sysctl_handle_dir);
++ sysctl_handle_dir = NULL;
++ }
++}
++
++/*
++ * eio_sysctl_register_common
++ */
++static void eio_sysctl_register_common(struct cache_c *dmc)
++{
++ unsigned int i;
++ struct sysctl_table_common *common;
++
++ common =
++ kmemdup(&sysctl_template_common, sizeof(sysctl_template_common),
++ GFP_KERNEL);
++ if (common == NULL) {
++ pr_err("Failed to allocate memory for common sysctl");
++ return;
++ }
++ for (i = 0; i < ARRAY_SIZE(common->vars) - 1; i++) {
++ common->vars[i].data =
++ eio_find_sysctl_data(dmc, &common->vars[i]);
++ common->vars[i].extra1 = dmc;
++ }
++
++ common->dev[0].procname = eio_cons_sysctl_devname(dmc);
++ common->dev[0].child = common->vars;
++ common->dir[0].child = common->dev;
++ common->root[0].child = common->dir;
++ common->sysctl_header = register_sysctl_table(common->root);
++ if (common->sysctl_header == NULL) {
++ pr_err("Failed to register common sysctl");
++ goto out;
++ }
++
++ dmc->sysctl_handle_common = common;
++ return;
++out:
++ kfree(common->dev[0].procname);
++ kfree(common);
++}
++
++/*
++ * eio_sysctl_unregister_common
++ */
++static void eio_sysctl_unregister_common(struct cache_c *dmc)
++{
++ struct sysctl_table_common *common;
++
++ common = dmc->sysctl_handle_common;
++ if (common != NULL) {
++ dmc->sysctl_handle_common = NULL;
++ unregister_sysctl_table(common->sysctl_header);
++ kfree(common->dev[0].procname);
++ kfree(common);
++ }
++}
++
++/*
++ * eio_sysctl_register_writeback
++ */
++static void eio_sysctl_register_writeback(struct cache_c *dmc)
++{
++ unsigned int i;
++ struct sysctl_table_writeback *writeback;
++
++ writeback =
++ kmemdup(&sysctl_template_writeback,
++ sizeof(sysctl_template_writeback), GFP_KERNEL);
++ if (writeback == NULL) {
++ pr_err("Failed to allocate memory for writeback sysctl");
++ return;
++ }
++ for (i = 0; i < ARRAY_SIZE(writeback->vars) - 1; i++) {
++ writeback->vars[i].data =
++ eio_find_sysctl_data(dmc, &writeback->vars[i]);
++ writeback->vars[i].extra1 = dmc;
++ }
++
++ writeback->dev[0].procname = eio_cons_sysctl_devname(dmc);
++ writeback->dev[0].child = writeback->vars;
++ writeback->dir[0].child = writeback->dev;
++ writeback->root[0].child = writeback->dir;
++ writeback->sysctl_header = register_sysctl_table(writeback->root);
++ if (writeback->sysctl_header == NULL) {
++ pr_err("Failed to register writeback sysctl");
++ goto out;
++ }
++
++ dmc->sysctl_handle_writeback = writeback;
++ return;
++out:
++ kfree(writeback->dev[0].procname);
++ kfree(writeback);
++}
++
++/*
++ * eio_sysctl_unregister_writeback
++ */
++static void eio_sysctl_unregister_writeback(struct cache_c *dmc)
++{
++ struct sysctl_table_writeback *writeback;
++
++ writeback = dmc->sysctl_handle_writeback;
++ if (writeback != NULL) {
++ dmc->sysctl_handle_writeback = NULL;
++ unregister_sysctl_table(writeback->sysctl_header);
++ kfree(writeback->dev[0].procname);
++ kfree(writeback);
++ }
++}
++
++/*
++ * eio_sysctl_register_invalidate
++ */
++static void eio_sysctl_register_invalidate(struct cache_c *dmc)
++{
++ unsigned int i;
++ struct sysctl_table_invalidate *invalidate;
++
++ invalidate =
++ kmemdup(&sysctl_template_invalidate,
++ sizeof(sysctl_template_invalidate), GFP_KERNEL);
++ if (invalidate == NULL) {
++ pr_err("Failed to allocate memory for invalidate sysctl");
++ return;
++ }
++ for (i = 0; i < ARRAY_SIZE(invalidate->vars) - 1; i++) {
++ invalidate->vars[i].data =
++ eio_find_sysctl_data(dmc, &invalidate->vars[i]);
++ invalidate->vars[i].extra1 = dmc;
++ }
++
++ invalidate->dev[0].procname = eio_cons_sysctl_devname(dmc);
++ invalidate->dev[0].child = invalidate->vars;
++ invalidate->dir[0].child = invalidate->dev;
++ invalidate->root[0].child = invalidate->dir;
++ invalidate->sysctl_header = register_sysctl_table(invalidate->root);
++ if (invalidate->sysctl_header == NULL) {
++ pr_err("Failed to register invalidate sysctl");
++ goto out;
++ }
++
++ dmc->sysctl_handle_invalidate = invalidate;
++ spin_lock_init(&invalidate_spin_lock);
++ return;
++out:
++ kfree(invalidate->dev[0].procname);
++ kfree(invalidate);
++}
++
++/*
++ * eio_sysctl_unregister_invalidate
++ */
++static void eio_sysctl_unregister_invalidate(struct cache_c *dmc)
++{
++ struct sysctl_table_invalidate *invalidate;
++
++ invalidate = dmc->sysctl_handle_invalidate;
++ if (invalidate != NULL) {
++ dmc->sysctl_handle_invalidate = NULL;
++ unregister_sysctl_table(invalidate->sysctl_header);
++ kfree(invalidate->dev[0].procname);
++ kfree(invalidate);
++ }
++}
++
++/*
++ * eio_stats_show
++ */
++static int eio_stats_show(struct seq_file *seq, void *v)
++{
++ struct cache_c *dmc = seq->private;
++ struct eio_stats *stats = &dmc->eio_stats;
++ int read_hit_pct, write_hit_pct, dirty_write_hit_pct;
++
++ if (atomic64_read(&stats->reads) > 0)
++ read_hit_pct =
++ EIO_CALCULATE_PERCENTAGE(
++ atomic64_read(&stats->read_hits),
++ atomic64_read(&stats->reads));
++ else
++ read_hit_pct = 0;
++
++ if (atomic64_read(&stats->writes) > 0) {
++ write_hit_pct =
++ EIO_CALCULATE_PERCENTAGE(
++ atomic64_read(&stats->write_hits),
++ atomic64_read(&stats->writes));
++ dirty_write_hit_pct =
++ EIO_CALCULATE_PERCENTAGE(
++ atomic64_read(&stats->dirty_write_hits),
++ atomic64_read(&stats->writes));
++ } else {
++ write_hit_pct = 0;
++ dirty_write_hit_pct = 0;
++ }
++
++ seq_printf(seq, "%-26s %12lld\n", "reads",
++ (int64_t)atomic64_read(&stats->reads));
++ seq_printf(seq, "%-26s %12lld\n", "writes",
++ (int64_t)atomic64_read(&stats->writes));
++
++ seq_printf(seq, "%-26s %12lld\n", "read_hits",
++ (int64_t)atomic64_read(&stats->read_hits));
++ seq_printf(seq, "%-26s %12d\n", "read_hit_pct", read_hit_pct);
++
++ seq_printf(seq, "%-26s %12lld\n", "write_hits",
++ (int64_t)atomic64_read(&stats->write_hits));
++ seq_printf(seq, "%-26s %12u\n", "write_hit_pct", write_hit_pct);
++
++ seq_printf(seq, "%-26s %12lld\n", "dirty_write_hits",
++ (int64_t)atomic64_read(&stats->dirty_write_hits));
++ seq_printf(seq, "%-26s %12d\n", "dirty_write_hit_pct",
++ dirty_write_hit_pct);
++
++ if ((int64_t)(atomic64_read(&stats->cached_blocks)) < 0)
++ atomic64_set(&stats->cached_blocks, 0);
++ seq_printf(seq, "%-26s %12lld\n", "cached_blocks",
++ (int64_t)atomic64_read(&stats->cached_blocks));
++
++ seq_printf(seq, "%-26s %12lld\n", "rd_replace",
++ (int64_t)atomic64_read(&stats->rd_replace));
++ seq_printf(seq, "%-26s %12lld\n", "wr_replace",
++ (int64_t)atomic64_read(&stats->wr_replace));
++
++ seq_printf(seq, "%-26s %12lld\n", "noroom",
++ (int64_t)atomic64_read(&stats->noroom));
++
++ seq_printf(seq, "%-26s %12lld\n", "cleanings",
++ (int64_t)atomic64_read(&stats->cleanings));
++ seq_printf(seq, "%-26s %12lld\n", "md_write_dirty",
++ (int64_t)atomic64_read(&stats->md_write_dirty));
++ seq_printf(seq, "%-26s %12lld\n", "md_write_clean",
++ (int64_t)atomic64_read(&stats->md_write_clean));
++ seq_printf(seq, "%-26s %12lld\n", "md_ssd_writes",
++ (int64_t)atomic64_read(&stats->md_ssd_writes));
++ seq_printf(seq, "%-26s %12d\n", "do_clean",
++ dmc->sysctl_active.do_clean);
++ seq_printf(seq, "%-26s %12lld\n", "nr_blocks", dmc->size);
++ seq_printf(seq, "%-26s %12lld\n", "nr_dirty",
++ (int64_t)atomic64_read(&dmc->nr_dirty));
++ seq_printf(seq, "%-26s %12u\n", "nr_sets", (uint32_t)dmc->num_sets);
++ seq_printf(seq, "%-26s %12d\n", "clean_index",
++ (uint32_t)atomic_read(&dmc->clean_index));
++
++ seq_printf(seq, "%-26s %12lld\n", "uncached_reads",
++ (int64_t)atomic64_read(&stats->uncached_reads));
++ seq_printf(seq, "%-26s %12lld\n", "uncached_writes",
++ (int64_t)atomic64_read(&stats->uncached_writes));
++ seq_printf(seq, "%-26s %12lld\n", "uncached_map_size",
++ (int64_t)atomic64_read(&stats->uncached_map_size));
++ seq_printf(seq, "%-26s %12lld\n", "uncached_map_uncacheable",
++ (int64_t)atomic64_read(&stats->uncached_map_uncacheable));
++
++ seq_printf(seq, "%-26s %12lld\n", "disk_reads",
++ (int64_t)atomic64_read(&stats->disk_reads));
++ seq_printf(seq, "%-26s %12lld\n", "disk_writes",
++ (int64_t)atomic64_read(&stats->disk_writes));
++ seq_printf(seq, "%-26s %12lld\n", "ssd_reads",
++ (int64_t)atomic64_read(&stats->ssd_reads));
++ seq_printf(seq, "%-26s %12lld\n", "ssd_writes",
++ (int64_t)atomic64_read(&stats->ssd_writes));
++ seq_printf(seq, "%-26s %12lld\n", "ssd_readfills",
++ (int64_t)atomic64_read(&stats->ssd_readfills));
++ seq_printf(seq, "%-26s %12lld\n", "ssd_readfill_unplugs",
++ (int64_t)atomic64_read(&stats->ssd_readfill_unplugs));
++
++ seq_printf(seq, "%-26s %12lld\n", "readdisk",
++ (int64_t)atomic64_read(&stats->readdisk));
++ seq_printf(seq, "%-26s %12lld\n", "writedisk",
++ (int64_t)atomic64_read(&stats->readdisk));
++ seq_printf(seq, "%-26s %12lld\n", "readcache",
++ (int64_t)atomic64_read(&stats->readcache));
++ seq_printf(seq, "%-26s %12lld\n", "readfill",
++ (int64_t)atomic64_read(&stats->readfill));
++ seq_printf(seq, "%-26s %12lld\n", "writecache",
++ (int64_t)atomic64_read(&stats->writecache));
++
++ seq_printf(seq, "%-26s %12lld\n", "readcount",
++ (int64_t)atomic64_read(&stats->readcount));
++ seq_printf(seq, "%-26s %12lld\n", "writecount",
++ (int64_t)atomic64_read(&stats->writecount));
++ seq_printf(seq, "%-26s %12lld\n", "kb_reads",
++ (int64_t)atomic64_read(&stats->reads) / 2);
++ seq_printf(seq, "%-26s %12lld\n", "kb_writes",
++ (int64_t)atomic64_read(&stats->writes) / 2);
++ seq_printf(seq, "%-26s %12lld\n", "rdtime_ms",
++ (int64_t)atomic64_read(&stats->rdtime_ms));
++ seq_printf(seq, "%-26s %12lld\n", "wrtime_ms",
++ (int64_t)atomic64_read(&stats->wrtime_ms));
++ return 0;
++}
++
++/*
++ * eio_stats_open
++ */
++static int eio_stats_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, &eio_stats_show, PDE_DATA(inode));
++}
++
++/*
++ * eio_errors_show
++ */
++static int eio_errors_show(struct seq_file *seq, void *v)
++{
++ struct cache_c *dmc = seq->private;
++
++ seq_printf(seq, "disk_read_errors %4u\n",
++ dmc->eio_errors.disk_read_errors);
++ seq_printf(seq, "disk_write_errors %4u\n",
++ dmc->eio_errors.disk_write_errors);
++ seq_printf(seq, "ssd_read_errors %4u\n",
++ dmc->eio_errors.ssd_read_errors);
++ seq_printf(seq, "ssd_write_errors %4u\n",
++ dmc->eio_errors.ssd_write_errors);
++ seq_printf(seq, "memory_alloc_errors %4u\n",
++ dmc->eio_errors.memory_alloc_errors);
++ seq_printf(seq, "no_cache_dev %4u\n",
++ dmc->eio_errors.no_cache_dev);
++ seq_printf(seq, "no_source_dev %4u\n",
++ dmc->eio_errors.no_source_dev);
++
++ return 0;
++}
++
++/*
++ * eio_errors_open
++ */
++static int eio_errors_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, &eio_errors_show, PDE_DATA(inode));
++}
++
++/*
++ * eio_iosize_hist_show
++ */
++static int eio_iosize_hist_show(struct seq_file *seq, void *v)
++{
++ int i;
++ struct cache_c *dmc = seq->private;
++
++ for (i = 1; i <= SIZE_HIST - 1; i++) {
++ if (atomic64_read(&dmc->size_hist[i]) == 0)
++ continue;
++
++ if (i == 1)
++ seq_printf(seq, "%u %12lld\n", i * 512,
++ (int64_t)atomic64_read(&dmc->size_hist[i]));
++ else if (i < 20)
++ seq_printf(seq, "%u %12lld\n", i * 512,
++ (int64_t)atomic64_read(&dmc->size_hist[i]));
++ else
++ seq_printf(seq, "%u %12lld\n", i * 512,
++ (int64_t)atomic64_read(&dmc->size_hist[i]));
++ }
++
++ return 0;
++}
++
++/*
++ * eio_iosize_hist_open
++ */
++static int eio_iosize_hist_open(struct inode *inode, struct file *file)
++{
++
++ return single_open(file, &eio_iosize_hist_show, PDE_DATA(inode));
++}
++
++/*
++ * eio_version_show
++ */
++static int eio_version_show(struct seq_file *seq, void *v)
++{
++ char buf[128];
++
++ memset(buf, 0, sizeof(buf));
++ eio_version_query(sizeof(buf), buf);
++ seq_printf(seq, "%s\n", buf);
++
++ return 0;
++}
++
++/*
++ * eio_version_open
++ */
++static int eio_version_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, &eio_version_show, PDE_DATA(inode));
++}
++
++/*
++ * eio_config_show
++ */
++static int eio_config_show(struct seq_file *seq, void *v)
++{
++ struct cache_c *dmc = seq->private;
++
++ seq_printf(seq, "src_name %s\n", dmc->disk_devname);
++ seq_printf(seq, "ssd_name %s\n", dmc->cache_devname);
++ seq_printf(seq, "src_size %lu\n", (long unsigned int)dmc->disk_size);
++ seq_printf(seq, "ssd_size %lu\n", (long unsigned int)dmc->size);
++
++ seq_printf(seq, "set_size %10u\n", dmc->assoc);
++ seq_printf(seq, "block_size %10u\n", (dmc->block_size) << SECTOR_SHIFT);
++ seq_printf(seq, "mode %10u\n", dmc->mode);
++ seq_printf(seq, "eviction %10u\n", dmc->req_policy);
++ seq_printf(seq, "num_sets %10u\n", dmc->num_sets);
++ seq_printf(seq, "num_blocks %10lu\n", (long unsigned int)dmc->size);
++ seq_printf(seq, "metadata %s\n",
++ CACHE_MD8_IS_SET(dmc) ? "large" : "small");
++ seq_printf(seq, "state %s\n",
++ CACHE_DEGRADED_IS_SET(dmc) ? "degraded"
++ : (CACHE_FAILED_IS_SET(dmc) ? "failed" : "normal"));
++ seq_printf(seq, "flags 0x%08x\n", dmc->cache_flags);
++
++ return 0;
++}
++
++/*
++ * eio_config_open
++ */
++static int eio_config_open(struct inode *inode, struct file *file)
++{
++
++ return single_open(file, &eio_config_show, PDE_DATA(inode));
++}
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_rand.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_rand.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_rand.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_rand.c 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,201 @@
++/*
++ * eio_rand.c
++ *
++ * Copyright (C) 2013 ProfitBricks, GmbH.
++ * Jack Wang <jinpu.wang@profitbricks.com>
++ * Dongsu Park <dongsu.park@profitbricks.com>
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include "eio.h"
++/* Generic policy functions prototypes */
++int eio_rand_init(struct cache_c *);
++void eio_rand_exit(void);
++int eio_rand_cache_sets_init(struct eio_policy *);
++int eio_rand_cache_blk_init(struct eio_policy *);
++void eio_rand_find_reclaim_dbn(struct eio_policy *, index_t, index_t *);
++int eio_rand_clean_set(struct eio_policy *, index_t, int);
++
++/* Per policy instance initialization */
++struct eio_policy *eio_rand_instance_init(void);
++
++
++/*
++ * Context that captures the rand replacement policy
++ */
++static struct eio_policy_header eio_rand_ops = {
++ .sph_name = CACHE_REPL_RANDOM,
++ .sph_instance_init = eio_rand_instance_init,
++};
++
++/*
++ * Initialize RAND policy.
++ */
++int eio_rand_init(struct cache_c *dmc)
++{
++ return 0;
++}
++
++/*
++ * Initialize rand data structure called from ctr.
++ */
++int eio_rand_cache_sets_init(struct eio_policy *p_ops)
++{
++ return 0;
++}
++
++/*
++ * The actual function that returns a victim block in index.
++ */
++void
++eio_rand_find_reclaim_dbn(struct eio_policy *p_ops, index_t start_index,
++ index_t *index)
++{
++ int i = 0;
++ index_t idx;
++
++ struct cache_c *dmc = p_ops->sp_dmc;
++
++ /*
++ * "start_index" should already be the beginning index of the set.
++ * We're just being cautious here.
++ */
++ start_index = (start_index / dmc->assoc) * dmc->assoc;
++ for (i = 0; i < (int)dmc->assoc; i++) {
++ idx = dmc->random++ % dmc->assoc;
++ if (EIO_CACHE_STATE_GET(dmc, start_index + idx) == VALID) {
++ *index = start_index + idx;
++ return;
++ }
++ }
++}
++
++/*
++ * Go through the entire set and clean.
++ */
++int eio_rand_clean_set(struct eio_policy *p_ops, index_t set, int to_clean)
++{
++ int i = 0, nr_writes = 0;
++ index_t start_index;
++
++ struct cache_c *dmc;
++
++ dmc = p_ops->sp_dmc;
++
++ start_index = set * dmc->assoc;
++
++ /* Scan sequentially in the set and pick blocks to clean */
++ while ((i < (int)dmc->assoc) && (nr_writes < to_clean)) {
++ if ((EIO_CACHE_STATE_GET(dmc, start_index + i) &
++ (DIRTY | BLOCK_IO_INPROG)) == DIRTY) {
++ EIO_CACHE_STATE_ON(dmc, start_index + i,
++ DISKWRITEINPROG);
++ nr_writes++;
++ }
++ i++;
++ }
++
++ return nr_writes;
++}
++
++/*
++ * rand is per set, so do nothing on a per block init.
++ */
++int eio_rand_cache_blk_init(struct eio_policy *p_ops)
++{
++ return 0;
++}
++
++/*
++ * Allocate a new instance of eio_policy per dmc
++ */
++struct eio_policy *eio_rand_instance_init(void)
++{
++ struct eio_policy *new_instance;
++
++ new_instance = vmalloc(sizeof(struct eio_policy));
++ if (new_instance == NULL) {
++ pr_err("ssdscache_rand_instance_init: vmalloc failed");
++ return NULL;
++ }
++
++ /* Initialize the rand specific functions and variables */
++ new_instance->sp_name = CACHE_REPL_RANDOM;
++ new_instance->sp_policy.lru = NULL;
++ new_instance->sp_repl_init = eio_rand_init;
++ new_instance->sp_repl_exit = eio_rand_exit;
++ new_instance->sp_repl_sets_init = eio_rand_cache_sets_init;
++ new_instance->sp_repl_blk_init = eio_rand_cache_blk_init;
++ new_instance->sp_find_reclaim_dbn = eio_rand_find_reclaim_dbn;
++ new_instance->sp_clean_set = eio_rand_clean_set;
++ new_instance->sp_dmc = NULL;
++
++ try_module_get(THIS_MODULE);
++
++ pr_info("eio_rand_instance_init: created new instance of RAND");
++
++ return new_instance;
++}
++
++/*
++ * Cleanup an instance of eio_policy (called from dtr).
++ */
++void eio_rand_exit(void)
++{
++ module_put(THIS_MODULE);
++}
++
++static
++int __init rand_register(void)
++{
++ int ret;
++
++ ret = eio_register_policy(&eio_rand_ops);
++ if (ret != 0)
++ pr_info("eio_rand already registered");
++
++ return ret;
++}
++
++static
++void __exit rand_unregister(void)
++{
++ int ret;
++
++ ret = eio_unregister_policy(&eio_rand_ops);
++ if (ret != 0)
++ pr_err("eio_rand unregister failed");
++}
++
++module_init(rand_register);
++module_exit(rand_unregister);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("RAND policy for EnhanceIO");
++MODULE_AUTHOR("STEC, Inc. based on code by Facebook");
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_setlru.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_setlru.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_setlru.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_setlru.c 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,170 @@
++/*
++ * eio_setlru.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Amit Kale <akale@stec-inc.com>
++ * Harish Pujari <hpujari@stec-inc.com>
++ * Generic lru implementation used mainly for cache sets.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ */
++
++#include "eio.h"
++
++/* Initialize the lru list */
++int lru_init(struct lru_ls **llist, index_t max)
++{
++ index_t i = 0;
++
++ EIO_ASSERT(max > 0);
++ *llist = vmalloc((sizeof(struct lru_ls) + (max - 1) * sizeof(struct lru_elem)));
++ if (*llist == NULL)
++ return -ENOMEM;
++
++ (*llist)->ll_head = LRU_NULL;
++ (*llist)->ll_tail = LRU_NULL;
++ (*llist)->ll_max = max;
++ (*llist)->ll_size = 0;
++
++ for (i = 0; i < max; i++) {
++ (*llist)->ll_elem[i].le_next = LRU_NULL;
++ (*llist)->ll_elem[i].le_prev = LRU_NULL;
++ (*llist)->ll_elem[i].le_key = 0;
++ }
++
++ return 0;
++}
++
++/* Uninitialize the lru list */
++void lru_uninit(struct lru_ls *llist)
++{
++ if (llist)
++ vfree(llist);
++}
++
++/* Add a new entry to lru list */
++int lru_add(struct lru_ls *llist, index_t index, u_int64_t key)
++{
++ if (!llist || (index >= llist->ll_max))
++ return -EINVAL;
++
++ llist->ll_elem[index].le_prev = llist->ll_tail;
++ llist->ll_elem[index].le_next = LRU_NULL;
++ llist->ll_elem[index].le_key = key;
++
++ if (llist->ll_tail != LRU_NULL)
++ llist->ll_elem[llist->ll_tail].le_next = index;
++ else {
++ EIO_ASSERT(llist->ll_head == LRU_NULL);
++ llist->ll_head = index;
++ }
++ llist->ll_tail = index;
++ llist->ll_size++;
++
++ return 0;
++}
++
++/* Remove an entry from the lru list */
++int lru_rem(struct lru_ls *llist, index_t index)
++{
++ if (!llist || (index >= llist->ll_max) || (index == LRU_NULL))
++ return -EINVAL;
++
++ if (llist->ll_head == LRU_NULL && llist->ll_tail == LRU_NULL)
++ /*
++ * No element in the list.
++ */
++ return -EINVAL;
++
++ if (llist->ll_elem[index].le_prev == LRU_NULL &&
++ llist->ll_elem[index].le_next == LRU_NULL &&
++ llist->ll_head != index && llist->ll_tail != index)
++ /*
++ * Element not in list.
++ */
++ return 0;
++
++ if (llist->ll_elem[index].le_prev != LRU_NULL)
++ llist->ll_elem[llist->ll_elem[index].le_prev].le_next =
++ llist->ll_elem[index].le_next;
++
++ if (llist->ll_elem[index].le_next != LRU_NULL)
++ llist->ll_elem[llist->ll_elem[index].le_next].le_prev =
++ llist->ll_elem[index].le_prev;
++
++ if (llist->ll_head == index)
++ llist->ll_head = llist->ll_elem[index].le_next;
++
++ if (llist->ll_tail == index)
++ llist->ll_tail = llist->ll_elem[index].le_prev;
++
++ llist->ll_elem[index].le_prev = LRU_NULL;
++ llist->ll_elem[index].le_next = LRU_NULL;
++ EIO_ASSERT(llist->ll_size != 0);
++ llist->ll_size--;
++
++ return 0;
++}
++
++/* Move up the given lru element */
++int lru_touch(struct lru_ls *llist, index_t index, u_int64_t key)
++{
++ if (!llist || (index >= llist->ll_max))
++ return -EINVAL;
++
++ if (llist->ll_tail == index)
++ llist->ll_elem[index].le_key = key;
++ else {
++ lru_rem(llist, index);
++ lru_add(llist, index, key);
++ }
++
++ return 0;
++}
++
++/* Read the element at the head of the lru */
++int lru_read_head(struct lru_ls *llist, index_t *index, u_int64_t *key)
++{
++ if (!llist || !index || !key)
++ return -EINVAL;
++
++ *index = llist->ll_head;
++ if (llist->ll_head == LRU_NULL) {
++ *index = LRU_NULL;
++ *key = 0;
++ } else {
++ *index = llist->ll_head;
++ *key = llist->ll_elem[*index].le_key;
++ }
++
++ return 0;
++}
++
++/* Remove the element at the head of the lru */
++int lru_rem_head(struct lru_ls *llist, index_t *index, u_int64_t *key)
++{
++ if (!llist || !index || !key)
++ return -EINVAL;
++
++ *index = llist->ll_head;
++ if (llist->ll_head == LRU_NULL) {
++ *index = LRU_NULL;
++ *key = 0;
++ } else {
++ *index = llist->ll_head;
++ *key = llist->ll_elem[*index].le_key;
++ lru_rem(llist, *index);
++ }
++
++ return 0;
++}
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_setlru.h linux-linaro-stable-mx6/drivers/block/enhanceio/eio_setlru.h
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_setlru.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_setlru.h 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,49 @@
++/*
++ * eio_setlru.h
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Amit Kale <akale@stec-inc.com>
++ * Harish Pujari <hpujari@stec-inc.com>
++ * Generic lru implementation used mainly for cache sets
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ */
++
++#ifndef _EIO_SETLRU_H_
++#define _EIO_SETLRU_H_
++
++#define LRU_NULL -1
++
++struct lru_elem {
++ index_t le_next;
++ index_t le_prev;
++ u_int64_t le_key;
++};
++
++struct lru_ls {
++ index_t ll_head;
++ index_t ll_tail;
++ index_t ll_max;
++ u_int64_t ll_size;
++ struct lru_elem ll_elem[1];
++};
++
++int lru_init(struct lru_ls **llist, index_t max);
++void lru_uninit(struct lru_ls *llist);
++int lru_add(struct lru_ls *llist, index_t index, u_int64_t key);
++int lru_rem(struct lru_ls *llist, index_t index);
++int lru_touch(struct lru_ls *llist, index_t index, u_int64_t key);
++int lru_read_head(struct lru_ls *llist, index_t *index, u_int64_t *key);
++int lru_rem_head(struct lru_ls *llist, index_t *index, u_int64_t *key);
++
++#endif /* _EIO_SETLRU_H_ */
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_subr.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_subr.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_subr.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_subr.c 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,444 @@
++/*
++ * eio_subr.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ * Made EnhanceIO specific changes.
++ * Saied Kazemi <skazemi@stec-inc.com>
++ * Siddharth Choudhuri <schoudhuri@stec-inc.com>
++ *
++ * Copyright 2010 Facebook, Inc.
++ * Author: Mohan Srinivasan (mohan@facebook.com)
++ *
++ * Based on DM-Cache:
++ * Copyright (C) International Business Machines Corp., 2006
++ * Author: Ming Zhao (mingzhao@ufl.edu)
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include "eio.h"
++#include "eio_ttc.h"
++
++static DEFINE_SPINLOCK(_job_lock);
++static LIST_HEAD(_io_jobs);
++static LIST_HEAD(_disk_read_jobs);
++
++int eio_io_empty(void)
++{
++
++ return list_empty(&_io_jobs);
++}
++
++struct kcached_job *eio_alloc_cache_job(void)
++{
++ struct kcached_job *job;
++
++ job = mempool_alloc(_job_pool, GFP_NOIO);
++ if (likely(job))
++ atomic_inc(&nr_cache_jobs);
++ return job;
++}
++
++void eio_free_cache_job(struct kcached_job *job)
++{
++
++ mempool_free(job, _job_pool);
++ atomic_dec(&nr_cache_jobs);
++}
++
++/*
++ * Functions to push and pop a job onto the head of a given job list.
++ */
++static struct kcached_job *eio_pop(struct list_head *jobs)
++{
++ struct kcached_job *job = NULL;
++ unsigned long flags = 0;
++
++ spin_lock_irqsave(&_job_lock, flags);
++ if (!list_empty(jobs)) {
++ job = list_entry(jobs->next, struct kcached_job, list);
++ list_del(&job->list);
++ }
++ spin_unlock_irqrestore(&_job_lock, flags);
++ return job;
++}
++
++static void eio_push(struct list_head *jobs, struct kcached_job *job)
++{
++ unsigned long flags = 0;
++
++ spin_lock_irqsave(&_job_lock, flags);
++ list_add_tail(&job->list, jobs);
++ spin_unlock_irqrestore(&_job_lock, flags);
++}
++
++void eio_push_ssdread_failures(struct kcached_job *job)
++{
++
++ eio_push(&_disk_read_jobs, job);
++}
++
++static void
++eio_process_jobs(struct list_head *jobs, void (*fn) (struct kcached_job *))
++{
++ struct kcached_job *job;
++
++ while ((job = eio_pop(jobs)) != NULL)
++ (void)fn(job);
++}
++
++static void eio_process_ssd_rm_list(void)
++{
++ unsigned long int flags = 0;
++ struct ssd_rm_list *ssd_list_ptr;
++ extern int ssd_rm_list_not_empty;
++ extern spinlock_t ssd_rm_list_lock;
++ extern struct list_head ssd_rm_list;
++
++ spin_lock_irqsave(&ssd_rm_list_lock, flags);
++ if (likely(list_empty(&ssd_rm_list))) {
++ spin_unlock_irqrestore(&ssd_rm_list_lock, flags);
++ return;
++ }
++
++ while (!list_empty(&ssd_rm_list)) {
++ ssd_list_ptr =
++ list_entry(ssd_rm_list.next, struct ssd_rm_list, list);
++ if (ssd_list_ptr->action == BUS_NOTIFY_DEL_DEVICE)
++ eio_suspend_caching(ssd_list_ptr->dmc,
++ ssd_list_ptr->note);
++ else
++ pr_err("eio_process_ssd_rm_list:"
++ "Unknown status (0x%x)\n", ssd_list_ptr->action);
++ list_del(&ssd_list_ptr->list);
++ kfree(ssd_list_ptr);
++ }
++ ssd_rm_list_not_empty = 0;
++ spin_unlock_irqrestore(&ssd_rm_list_lock, flags);
++}
++
++/*
++ * Entry point of the "events" kernel thread.
++ */
++void eio_do_work(struct work_struct *unused)
++{
++ extern int ssd_rm_list_not_empty;
++
++ if (unlikely(ssd_rm_list_not_empty))
++ eio_process_ssd_rm_list();
++ eio_process_jobs(&_disk_read_jobs, eio_ssderror_diskread);
++}
++
++struct kcached_job *eio_new_job(struct cache_c *dmc, struct eio_bio *bio,
++ index_t index)
++{
++ struct kcached_job *job;
++
++ EIO_ASSERT((bio != NULL) || (index != -1));
++
++ job = eio_alloc_cache_job();
++ if (unlikely(job == NULL)) {
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->eio_errors.memory_alloc_errors++;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return NULL;
++ }
++ job->dmc = dmc;
++ job->index = index;
++ job->error = 0;
++ job->ebio = bio;
++ if (index != -1) {
++ job->job_io_regions.cache.bdev = dmc->cache_dev->bdev;
++ if (bio) {
++ job->job_io_regions.cache.sector =
++ (index << dmc->block_shift) + dmc->md_sectors +
++ (bio->eb_sector -
++ EIO_ROUND_SECTOR(dmc, bio->eb_sector));
++ EIO_ASSERT(eio_to_sector(bio->eb_size) <=
++ dmc->block_size);
++ job->job_io_regions.cache.count =
++ eio_to_sector(bio->eb_size);
++ } else {
++ job->job_io_regions.cache.sector =
++ (index << dmc->block_shift) + dmc->md_sectors;
++ job->job_io_regions.cache.count = dmc->block_size;
++ }
++ }
++
++ job->job_io_regions.disk.bdev = dmc->disk_dev->bdev;
++ if (bio) {
++ job->job_io_regions.disk.sector = bio->eb_sector;
++ job->job_io_regions.disk.count = eio_to_sector(bio->eb_size);
++ } else {
++ job->job_io_regions.disk.sector = EIO_DBN_GET(dmc, index);
++ job->job_io_regions.disk.count = dmc->block_size;
++ }
++ job->next = NULL;
++ job->md_sector = NULL;
++
++ return job;
++}
++
++int
++eio_io_sync_pages(struct cache_c *dmc, struct eio_io_region *where, int rw,
++ struct page **pages, int num_bvecs)
++{
++ struct eio_io_request req;
++ int error;
++
++ req.mtype = EIO_PAGES;
++ req.dptr.plist = pages;
++ req.num_bvecs = num_bvecs;
++ req.notify = NULL;
++ req.context = NULL;
++ req.hddio = 0;
++
++ if ((unlikely(CACHE_FAILED_IS_SET(dmc)) ||
++ unlikely(CACHE_DEGRADED_IS_SET(dmc))) &&
++ (!CACHE_SSD_ADD_INPROG_IS_SET(dmc)))
++ error = -ENODEV;
++ else
++ error = eio_do_io(dmc, where, rw, &req);
++
++ if (error)
++ return error;
++
++ return 0;
++}
++
++int
++eio_io_sync_vm(struct cache_c *dmc, struct eio_io_region *where, int rw,
++ struct bio_vec *pages, int num_bvecs)
++{
++ struct eio_io_request req;
++ int error;
++
++ memset((char *)&req, 0, sizeof(req));
++ /* Fill up the appropriate fields
++ * in eio_io_request */
++ req.mtype = EIO_BVECS;
++ req.dptr.pages = pages;
++ req.num_bvecs = num_bvecs;
++ req.notify = NULL;
++ req.context = NULL;
++ req.hddio = 0;
++ if ((unlikely(CACHE_FAILED_IS_SET(dmc)) ||
++ unlikely(CACHE_DEGRADED_IS_SET(dmc))) &&
++ (!CACHE_SSD_ADD_INPROG_IS_SET(dmc)))
++ error = -ENODEV;
++ else
++ error = eio_do_io(dmc, where, rw, &req);
++ if (error)
++ return error;
++ return 0;
++}
++
++void eio_unplug_cache_device(struct cache_c *dmc)
++{
++ struct request_queue *q;
++ struct block_device *bdev;
++
++ if (unlikely(CACHE_FAILED_IS_SET(dmc)) ||
++ unlikely(CACHE_DEGRADED_IS_SET(dmc)))
++ return;
++ bdev = dmc->cache_dev->bdev;
++ q = bdev_get_queue(bdev);
++}
++
++void eio_unplug_disk_device(struct cache_c *dmc)
++{
++ struct request_queue *q;
++ struct block_device *bdev;
++
++ if (unlikely(CACHE_DEGRADED_IS_SET(dmc)))
++ return;
++ bdev = dmc->disk_dev->bdev;
++ q = bdev_get_queue(bdev);
++}
++
++void eio_plug_cache_device(struct cache_c *dmc)
++{
++ struct block_device *bdev;
++ struct request_queue *q;
++
++ if (unlikely(CACHE_FAILED_IS_SET(dmc)) ||
++ unlikely(CACHE_DEGRADED_IS_SET(dmc)))
++ return;
++ bdev = dmc->cache_dev->bdev;
++ q = bdev_get_queue(bdev);
++}
++
++void eio_plug_disk_device(struct cache_c *dmc)
++{
++ struct block_device *bdev;
++ struct request_queue *q;
++
++ if (unlikely(CACHE_DEGRADED_IS_SET(dmc)))
++ return;
++ bdev = dmc->disk_dev->bdev;
++ q = bdev_get_queue(bdev);
++}
++
++/*
++ * For Linux, we do not do a dm_put_device() when the device underneath
++ * disappears. The logic to handle the IOs to a missing device is handled
++ * by the kernel proper. We will get an IO error if an IO is done on a
++ * device that does not exist.
++ */
++void eio_suspend_caching(struct cache_c *dmc, enum dev_notifier note)
++{
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, dmc->cache_spin_lock_flags);
++ if (dmc->mode != CACHE_MODE_WB && CACHE_FAILED_IS_SET(dmc)) {
++ pr_err("suspend caching: Cache "
++ "%s is already in FAILED state\n", dmc->cache_name);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return;
++ }
++
++ switch (note) {
++
++ case NOTIFY_SRC_REMOVED:
++ if (CACHE_DEGRADED_IS_SET(dmc))
++ dmc->cache_flags &= ~CACHE_FLAGS_DEGRADED;
++ dmc->cache_flags |= CACHE_FLAGS_FAILED;
++ dmc->eio_errors.no_source_dev = 1;
++ atomic64_set(&dmc->eio_stats.cached_blocks, 0);
++ pr_info("suspend_caching: Source Device Removed."
++ "Cache \"%s\" is in Failed mode.\n", dmc->cache_name);
++ break;
++ case NOTIFY_SSD_REMOVED:
++ if (dmc->mode == CACHE_MODE_WB) {
++ /*
++ * For writeback
++ * - Cache should never be in degraded mode
++ * - ssd removal should result in FAILED state
++ * - the cached block should not be reset.
++ */
++ EIO_ASSERT(!CACHE_DEGRADED_IS_SET(dmc));
++ dmc->cache_flags |= CACHE_FLAGS_FAILED;
++ pr_info("suspend caching: SSD Device Removed.\
++ Cache \"%s\" is in Failed mode.\n", dmc->cache_name);
++ } else {
++ if (CACHE_DEGRADED_IS_SET(dmc) ||
++ CACHE_SSD_ADD_INPROG_IS_SET(dmc)) {
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->
++ cache_spin_lock_flags);
++ pr_err("suspend_caching: Cache \
++ \"%s\" is either degraded \
++ or device add in progress, exiting.\n", dmc->cache_name);
++ return;
++ }
++ dmc->cache_flags |= CACHE_FLAGS_DEGRADED;
++ atomic64_set(&dmc->eio_stats.cached_blocks, 0);
++ pr_info("suspend caching: Cache \"%s\" \
++ is in Degraded mode.\n", dmc->cache_name);
++ }
++ dmc->eio_errors.no_cache_dev = 1;
++ break;
++ default:
++ pr_err("suspend_caching: incorrect notify message.\n");
++ break;
++ }
++
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++}
++
++void eio_put_cache_device(struct cache_c *dmc)
++{
++
++ eio_ttc_put_device(&dmc->cache_dev);
++}
++
++void eio_resume_caching(struct cache_c *dmc, char *dev)
++{
++ int r;
++
++ if (dmc == NULL || dev == NULL) {
++ pr_err("resume_caching: Null device or"
++ "cache instance when resuming caching.\n");
++ return;
++ }
++ if (strlen(dev) >= DEV_PATHLEN) {
++ pr_err("resume_caching: Device name %s too long.\n", dev);
++ return;
++ }
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, dmc->cache_spin_lock_flags);
++ if (CACHE_STALE_IS_SET(dmc)) {
++ pr_err("eio_resume_caching: Hard Failure Detected!!"
++ "Cache \"%s\" can not be resumed.", dmc->cache_name);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return;
++ }
++
++ /* sanity check for writeback */
++ if (dmc->mode == CACHE_MODE_WB) {
++ if (!CACHE_FAILED_IS_SET(dmc) || CACHE_SRC_IS_ABSENT(dmc) ||
++ CACHE_SSD_ADD_INPROG_IS_SET(dmc)) {
++ pr_debug("eio_resume_caching: Cache not in Failed "
++ "state or Source is absent"
++ "or SSD add already in progress for cache \"%s\".\n",
++ dmc->cache_name);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return;
++ }
++ } else {
++ /* sanity check for WT or RO cache. */
++ if (CACHE_FAILED_IS_SET(dmc) || !CACHE_DEGRADED_IS_SET(dmc) ||
++ CACHE_SSD_ADD_INPROG_IS_SET(dmc)) {
++ pr_err("resume_caching: Cache \"%s\" "
++ "is either in failed mode or "
++ "cache device add in progress, ignoring.\n ",
++ dmc->cache_name);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return;
++ }
++ }
++
++ dmc->cache_flags |= CACHE_FLAGS_SSD_ADD_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ r = eio_ctr_ssd_add(dmc, dev);
++ if (r) {
++ /* error */
++ pr_debug(" resume caching: returned error: %d\n ", r);
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_SSD_ADD_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return;
++ }
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, dmc->cache_spin_lock_flags);
++ dmc->eio_errors.no_cache_dev = 0;
++ if (dmc->mode != CACHE_MODE_WB)
++ dmc->cache_flags &= ~CACHE_FLAGS_DEGRADED;
++ else
++ dmc->cache_flags &= ~CACHE_FLAGS_FAILED;
++ dmc->cache_flags &= ~CACHE_FLAGS_SSD_ADD_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ pr_info(" resume_caching:cache %s is restored to ACTIVE mode.\n",
++ dmc->cache_name);
++}
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_ttc.c linux-linaro-stable-mx6/drivers/block/enhanceio/eio_ttc.c
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_ttc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_ttc.c 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,1665 @@
++/*
++ * True Transparent Caching (TTC) code.
++ * eio_ttc.c
++ *
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved
++ *
++ * Made EIO fully transparent with respect to applications. A cache can be
++ * created or deleted while a filesystem or applications are online
++ * Amit Kale <akale@stec-inc.com>
++ * Ramprasad Chinthekindi <rchinthekindi@stec-inc.com>
++ * Akhil Bhansali <abhansali@stec-inc.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ */
++
++#include <linux/blkdev.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include "eio.h"
++#include "eio_ttc.h"
++static struct rw_semaphore eio_ttc_lock[EIO_HASHTBL_SIZE];
++static struct list_head eio_ttc_list[EIO_HASHTBL_SIZE];
++
++int eio_reboot_notified;
++
++static void eio_make_request_fn(struct request_queue *, struct bio *);
++static void eio_cache_rec_fill(struct cache_c *, struct cache_rec_short *);
++static void eio_bio_end_empty_barrier(struct bio *, int);
++static void eio_issue_empty_barrier_flush(struct block_device *, struct bio *,
++ int, make_request_fn *, int rw_flags);
++static int eio_finish_nrdirty(struct cache_c *);
++static int eio_mode_switch(struct cache_c *, u_int32_t);
++static int eio_policy_switch(struct cache_c *, u_int32_t);
++
++static int eio_overlap_split_bio(struct request_queue *, struct bio *);
++static struct bio *eio_split_new_bio(struct bio *, struct bio_container *,
++ unsigned *, unsigned *, sector_t);
++static void eio_split_endio(struct bio *, int);
++
++static int eio_open(struct inode *ip, struct file *filp)
++{
++ __module_get(THIS_MODULE);
++ return 0;
++}
++
++static int eio_release(struct inode *ip, struct file *filp)
++{
++ module_put(THIS_MODULE);
++ return 0;
++}
++
++static const struct file_operations eio_fops = {
++ .open = eio_open,
++ .release = eio_release,
++ .unlocked_ioctl = eio_ioctl,
++ .compat_ioctl = eio_compact_ioctl,
++ .owner = THIS_MODULE,
++};
++
++static struct miscdevice eio_misc = {
++ .minor = MISC_DYNAMIC_MINOR,
++ .name = MISC_DEVICE,
++ .fops = &eio_fops,
++};
++
++int eio_create_misc_device()
++{
++ return misc_register(&eio_misc);
++}
++
++int eio_delete_misc_device()
++{
++ return misc_deregister(&eio_misc);
++}
++
++int eio_ttc_get_device(const char *path, fmode_t mode, struct eio_bdev **result)
++{
++ struct block_device *bdev;
++ struct eio_bdev *eio_bdev;
++
++ static char *eio_holder = "EnhanceIO";
++
++ bdev = blkdev_get_by_path(path, mode, eio_holder);
++ if (IS_ERR(bdev))
++ return PTR_ERR(bdev);
++
++ eio_bdev = kzalloc(sizeof(*eio_bdev), GFP_KERNEL);
++ if (eio_bdev == NULL) {
++ blkdev_put(bdev, mode);
++ return -ENOMEM;
++ }
++
++ eio_bdev->bdev = bdev;
++ eio_bdev->mode = mode;
++ *result = eio_bdev;
++ return 0;
++}
++
++void eio_ttc_put_device(struct eio_bdev **d)
++{
++ struct eio_bdev *eio_bdev;
++
++ eio_bdev = *d;
++ blkdev_put(eio_bdev->bdev, eio_bdev->mode);
++ kfree(eio_bdev);
++ *d = NULL;
++ return;
++}
++
++struct cache_c *eio_cache_lookup(char *name)
++{
++ struct cache_c *dmc = NULL;
++ int i;
++
++ for (i = 0; i < EIO_HASHTBL_SIZE; i++) {
++ down_read(&eio_ttc_lock[i]);
++ list_for_each_entry(dmc, &eio_ttc_list[i], cachelist) {
++ if (!strcmp(name, dmc->cache_name)) {
++ up_read(&eio_ttc_lock[i]);
++ return dmc;
++ }
++ }
++ up_read(&eio_ttc_lock[i]);
++ }
++ return NULL;
++}
++
++int eio_ttc_activate(struct cache_c *dmc)
++{
++ struct block_device *bdev;
++ struct request_queue *rq;
++ make_request_fn *origmfn;
++ struct cache_c *dmc1;
++ int wholedisk;
++ int error;
++ int index;
++ int rw_flags = 0;
++
++ bdev = dmc->disk_dev->bdev;
++ if (bdev == NULL) {
++ pr_err("cache_create: Source device not found\n");
++ return -ENODEV;
++ }
++ rq = bdev->bd_disk->queue;
++
++ wholedisk = 0;
++ if (bdev == bdev->bd_contains)
++ wholedisk = 1;
++
++ dmc->dev_start_sect = bdev->bd_part->start_sect;
++ dmc->dev_end_sect =
++ bdev->bd_part->start_sect + bdev->bd_part->nr_sects - 1;
++
++ pr_debug("eio_ttc_activate: Device/Partition" \
++ " sector_start: %llu, end: %llu\n",
++ (uint64_t)dmc->dev_start_sect, (uint64_t)dmc->dev_end_sect);
++
++ error = 0;
++ origmfn = NULL;
++ index = EIO_HASH_BDEV(bdev->bd_contains->bd_dev);
++
++ down_write(&eio_ttc_lock[index]);
++ list_for_each_entry(dmc1, &eio_ttc_list[index], cachelist) {
++ if (dmc1->disk_dev->bdev->bd_contains != bdev->bd_contains)
++ continue;
++
++ if ((wholedisk) || (dmc1->dev_info == EIO_DEV_WHOLE_DISK) ||
++ (dmc1->disk_dev->bdev == bdev)) {
++ error = -EINVAL;
++ up_write(&eio_ttc_lock[index]);
++ goto out;
++ }
++
++ /* some partition of same device already cached */
++ EIO_ASSERT(dmc1->dev_info == EIO_DEV_PARTITION);
++ origmfn = dmc1->origmfn;
++ break;
++ }
++
++ /*
++ * Save original make_request_fn. Switch make_request_fn only once.
++ */
++
++ if (origmfn) {
++ dmc->origmfn = origmfn;
++ dmc->dev_info = EIO_DEV_PARTITION;
++ EIO_ASSERT(wholedisk == 0);
++ } else {
++ dmc->origmfn = rq->make_request_fn;
++ rq->make_request_fn = eio_make_request_fn;
++ dmc->dev_info =
++ (wholedisk) ? EIO_DEV_WHOLE_DISK : EIO_DEV_PARTITION;
++ }
++
++ list_add_tail(&dmc->cachelist, &eio_ttc_list[index]);
++
++ /*
++ * Sleep for sometime, to allow previous I/Os to hit
++ * Issue a barrier I/O on Source device.
++ */
++
++ msleep(1);
++ SET_BARRIER_FLAGS(rw_flags);
++ eio_issue_empty_barrier_flush(dmc->disk_dev->bdev, NULL,
++ EIO_HDD_DEVICE, dmc->origmfn, rw_flags);
++ up_write(&eio_ttc_lock[index]);
++
++out:
++ if (error == -EINVAL) {
++ if (wholedisk)
++ pr_err
++ ("cache_create: A partition of this device is already cached.\n");
++ else
++ pr_err("cache_create: Device is already cached.\n");
++ }
++ return error;
++}
++
++int eio_ttc_deactivate(struct cache_c *dmc, int force)
++{
++ struct block_device *bdev;
++ struct request_queue *rq;
++ struct cache_c *dmc1;
++ int found_partitions;
++ int index;
++ int ret;
++
++ ret = 0;
++ bdev = dmc->disk_dev->bdev;
++ rq = bdev->bd_disk->queue;
++
++ if (force)
++ goto deactivate;
++
++ /* Process and wait for nr_dirty to drop to zero */
++ if (dmc->mode == CACHE_MODE_WB) {
++ if (!CACHE_FAILED_IS_SET(dmc)) {
++ ret = eio_finish_nrdirty(dmc);
++ if (ret) {
++ pr_err
++ ("ttc_deactivate: nrdirty failed to finish for cache \"%s\".",
++ dmc->cache_name);
++ return ret;
++ }
++ } else
++ pr_debug
++ ("ttc_deactivate: Cache \"%s\" failed is already set. Continue with cache delete.",
++ dmc->cache_name);
++ }
++
++ /*
++ * Traverse the list and see if other partitions of this device are
++ * cached. Switch mfn if this is the only partition of the device
++ * in the list.
++ */
++deactivate:
++ index = EIO_HASH_BDEV(bdev->bd_contains->bd_dev);
++ found_partitions = 0;
++
++ /* check if barrier QUEUE is empty or not */
++ down_write(&eio_ttc_lock[index]);
++
++ if (dmc->dev_info != EIO_DEV_WHOLE_DISK)
++ list_for_each_entry(dmc1, &eio_ttc_list[index], cachelist) {
++ if (dmc == dmc1)
++ continue;
++
++ if (dmc1->disk_dev->bdev->bd_contains != bdev->bd_contains)
++ continue;
++
++ EIO_ASSERT(dmc1->dev_info == EIO_DEV_PARTITION);
++
++ /*
++ * There are still other partitions which are cached.
++ * Do not switch the make_request_fn.
++ */
++
++ found_partitions = 1;
++ break;
++ }
++
++ if ((dmc->dev_info == EIO_DEV_WHOLE_DISK) || (found_partitions == 0))
++ rq->make_request_fn = dmc->origmfn;
++
++ list_del_init(&dmc->cachelist);
++ up_write(&eio_ttc_lock[index]);
++
++ /* wait for nr_ios to drain-out */
++ while (atomic64_read(&dmc->nr_ios) != 0)
++ schedule_timeout(msecs_to_jiffies(100));
++
++ return ret;
++}
++
++void eio_ttc_init(void)
++{
++ int i;
++
++ for (i = 0; i < EIO_HASHTBL_SIZE; i++) {
++ init_rwsem(&eio_ttc_lock[i]);
++ INIT_LIST_HEAD(&eio_ttc_list[i]);
++ }
++}
++
++/*
++ * Cases:-
++ * 1. Full device cached.
++ * if (ENQUEUE || barrier(bio))
++ * enqueue (dmc, bio) and return
++ * else
++ * call eio_map(dmc, bio)
++ * 2. Some partitions of the device cached.
++ * if (ENQUEUE || barrier(bio))
++ * All I/Os (both on cached and uncached partitions) are enqueued.
++ * else
++ * if (I/O on cached partition)
++ * call eio_map(dmc, bio)
++ * else
++ * origmfn(bio); // uncached partition
++ * 3. q->mfn got switched back to original
++ * call origmfn(q, bio)
++ * 4. Race condition:
++ */
++
++static void eio_make_request_fn(struct request_queue *q, struct bio *bio)
++{
++ int ret;
++ int overlap;
++ int index;
++ make_request_fn *origmfn;
++ struct cache_c *dmc, *dmc1;
++ struct block_device *bdev;
++
++ bdev = bio->bi_bdev;
++
++re_lookup:
++ dmc = NULL;
++ origmfn = NULL;
++ overlap = ret = 0;
++
++ index = EIO_HASH_BDEV(bdev->bd_contains->bd_dev);
++
++ down_read(&eio_ttc_lock[index]);
++
++ list_for_each_entry(dmc1, &eio_ttc_list[index], cachelist) {
++ if (dmc1->disk_dev->bdev->bd_contains != bdev->bd_contains)
++ continue;
++
++ if (dmc1->dev_info == EIO_DEV_WHOLE_DISK) {
++ dmc = dmc1; /* found cached device */
++ break;
++ }
++
++ /* Handle partitions */
++ if (!origmfn)
++ origmfn = dmc1->origmfn;
++
++ /* I/O perfectly fit within cached partition */
++ if ((bio->bi_sector >= dmc1->dev_start_sect) &&
++ ((bio->bi_sector + eio_to_sector(bio->bi_size) - 1) <=
++ dmc1->dev_end_sect)) {
++ EIO_ASSERT(overlap == 0);
++ dmc = dmc1; /* found cached partition */
++ break;
++ }
++
++ /* Check if I/O is overlapping with cached partitions */
++ if (((bio->bi_sector >= dmc1->dev_start_sect) &&
++ (bio->bi_sector <= dmc1->dev_end_sect)) ||
++ ((bio->bi_sector + eio_to_sector(bio->bi_size) - 1 >=
++ dmc1->dev_start_sect) &&
++ (bio->bi_sector + eio_to_sector(bio->bi_size) - 1 <=
++ dmc1->dev_end_sect))) {
++ overlap = 1;
++ pr_err
++ ("Overlapping I/O detected on %s cache at sector: %llu, size: %u\n",
++ dmc1->cache_name, (uint64_t)bio->bi_sector,
++ bio->bi_size);
++ break;
++ }
++ }
++
++ if (unlikely(overlap)) {
++ up_read(&eio_ttc_lock[index]);
++
++ if (bio_rw_flagged(bio, REQ_DISCARD)) {
++ pr_err
++ ("eio_mfn: Overlap I/O with Discard flag." \
++ " Discard flag is not supported.\n");
++ bio_endio(bio, -EOPNOTSUPP);
++ } else
++ ret = eio_overlap_split_bio(q, bio);
++ } else if (dmc) { /* found cached partition or device */
++ /*
++ * Start sector of cached partition may or may not be
++ * aligned with cache blocksize.
++ * Map start of the partition to zero reference.
++ */
++
++ if (bio->bi_sector) {
++ EIO_ASSERT(bio->bi_sector >= dmc->dev_start_sect);
++ bio->bi_sector -= dmc->dev_start_sect;
++ }
++ ret = eio_map(dmc, q, bio);
++ if (ret)
++ /* Error case: restore the start sector of bio */
++ bio->bi_sector += dmc->dev_start_sect;
++ }
++
++ if (!overlap)
++ up_read(&eio_ttc_lock[index]);
++
++ if (overlap || dmc)
++ return;
++
++ /*
++ * Race condition:-
++ * origmfn can be NULL if all partitions or whole disk got uncached.
++ * We set origmfn = q->mfn if origmfn is NULL.
++ * The origmfn may now again be eio_make_request_fn because
++ * someone else switched the q->mfn because of a new
++ * partition or whole disk being cached.
++ * Since, we cannot protect q->make_request_fn() by any lock,
++ * this situation may occur. However, this is a very rare event.
++ * In this case restart the lookup.
++ */
++
++ if (origmfn == NULL)
++ origmfn = q->make_request_fn;
++ if (origmfn == eio_make_request_fn)
++ goto re_lookup;
++
++ origmfn(q, bio);
++ return;
++}
++
++uint64_t eio_get_cache_count(void)
++{
++ struct cache_c *dmc;
++ uint64_t cnt = 0;
++ int i;
++
++ for (i = 0; i < EIO_HASHTBL_SIZE; i++) {
++ down_read(&eio_ttc_lock[i]);
++ list_for_each_entry(dmc, &eio_ttc_list[i], cachelist) {
++ cnt++;
++ }
++ up_read(&eio_ttc_lock[i]);
++ }
++ return cnt;
++}
++
++int eio_get_cache_list(unsigned long *arg)
++{
++ int error = 0;
++ unsigned int size, i, j;
++ struct cache_list reclist;
++ struct cache_rec_short *cache_recs;
++ struct cache_c *dmc;
++
++ if (copy_from_user(&reclist, (struct cache_list __user *)arg,
++ sizeof(struct cache_list))) {
++ error = -EFAULT;
++ goto out;
++ }
++
++ size = reclist.ncaches * sizeof(struct cache_rec_short);
++ cache_recs = vmalloc(size);
++ if (!cache_recs) {
++ error = -ENOMEM;
++ goto out;
++ }
++ memset(cache_recs, 0, size);
++
++ i = 0;
++ for (j = 0; j < EIO_HASHTBL_SIZE; j++) {
++ down_read(&eio_ttc_lock[j]);
++ list_for_each_entry(dmc, &eio_ttc_list[j], cachelist) {
++ eio_cache_rec_fill(dmc, &cache_recs[i]);
++ i++;
++
++ if (i == reclist.ncaches)
++ break;
++ }
++ up_read(&eio_ttc_lock[j]);
++
++ if (i == reclist.ncaches)
++ break;
++ }
++
++ if (copy_to_user((char __user *)reclist.cachelist,
++ (char *)cache_recs, size)) {
++ error = -EFAULT;
++ goto out;
++ }
++
++ if (copy_to_user((struct cache_list __user *)arg, &reclist,
++ sizeof(struct cache_list))) {
++ error = -EFAULT;
++ goto out;
++ }
++
++out:
++ return error;
++}
++
++static void eio_cache_rec_fill(struct cache_c *dmc, struct cache_rec_short *rec)
++{
++ strncpy(rec->cr_name, dmc->cache_name, sizeof(rec->cr_name) - 1);
++ strncpy(rec->cr_src_devname, dmc->disk_devname,
++ sizeof(rec->cr_src_devname) - 1);
++ strncpy(rec->cr_ssd_devname, dmc->cache_devname,
++ sizeof(rec->cr_ssd_devname) - 1);
++ rec->cr_src_dev_size = eio_get_device_size(dmc->disk_dev);
++ rec->cr_ssd_dev_size = eio_get_device_size(dmc->cache_dev);
++ rec->cr_src_sector_size = 0; /* unused in userspace */
++ rec->cr_ssd_sector_size = 0; /* unused in userspace */
++ rec->cr_flags = dmc->cache_flags;
++ rec->cr_policy = dmc->req_policy;
++ rec->cr_mode = dmc->mode;
++ rec->cr_persistence = dmc->persistence;
++ rec->cr_blksize = dmc->block_size; /* In sectors */
++ rec->cr_assoc = dmc->assoc;
++ return;
++}
++
++/*
++ * Few sanity checks before cache creation.
++ */
++
++int eio_do_preliminary_checks(struct cache_c *dmc)
++{
++ struct block_device *bdev, *ssd_bdev;
++ struct cache_c *dmc1;
++ int error;
++ int wholedisk;
++ int index;
++
++ error = wholedisk = 0;
++ bdev = dmc->disk_dev->bdev;
++ ssd_bdev = dmc->cache_dev->bdev;
++
++ /*
++ * Disallow cache creation if source and cache device
++ * belong to same device.
++ */
++
++ if (bdev->bd_contains == ssd_bdev->bd_contains)
++ return -EINVAL;
++
++ /*
++ * Check if cache with same name exists.
++ */
++
++ if (eio_cache_lookup(dmc->cache_name))
++ return -EEXIST;
++
++ if (bdev == bdev->bd_contains)
++ wholedisk = 1;
++
++ index = EIO_HASH_BDEV(bdev->bd_contains->bd_dev);
++
++ down_read(&eio_ttc_lock[index]);
++ list_for_each_entry(dmc1, &eio_ttc_list[index], cachelist) {
++ if (dmc1->disk_dev->bdev->bd_contains != bdev->bd_contains)
++ continue;
++
++ if ((wholedisk) || (dmc1->dev_info == EIO_DEV_WHOLE_DISK) ||
++ (dmc1->disk_dev->bdev == bdev)) {
++ error = -EINVAL;
++ break;
++ }
++ }
++ up_read(&eio_ttc_lock[index]);
++ return error;
++}
++
++/* Use mempool_alloc and free for io in sync_io as well */
++static void eio_dec_count(struct eio_context *io, int error)
++{
++ if (error)
++ io->error = error;
++
++ if (atomic_dec_and_test(&io->count)) {
++ if (io->event)
++ complete(io->event);
++ else {
++ int err = io->error;
++ eio_notify_fn fn = io->callback;
++ void *context = io->context;
++
++ mempool_free(io, _io_pool);
++ io = NULL;
++ fn(err, context);
++ }
++ }
++}
++
++static void eio_endio(struct bio *bio, int error)
++{
++ struct eio_context *io;
++
++ io = bio->bi_private;
++ EIO_ASSERT(io != NULL);
++
++ bio_put(bio);
++
++ eio_dec_count(io, error);
++}
++
++static int eio_dispatch_io_pages(struct cache_c *dmc,
++ struct eio_io_region *where, int rw,
++ struct page **pagelist, struct eio_context *io,
++ int hddio, int num_vecs, int sync)
++{
++ struct bio *bio;
++ struct page *page;
++ unsigned long len;
++ unsigned offset;
++ int num_bvecs;
++ int remaining_bvecs = num_vecs;
++ int ret = 0;
++ int pindex = 0;
++
++ sector_t remaining = where->count;
++
++ do {
++ /* Verify that num_vecs should not cross the threshhold */
++ /* Check how many max bvecs bdev supports */
++ num_bvecs =
++ min_t(int, bio_get_nr_vecs(where->bdev), remaining_bvecs);
++ bio = bio_alloc(GFP_NOIO, num_bvecs);
++ bio->bi_bdev = where->bdev;
++ bio->bi_sector = where->sector + (where->count - remaining);
++
++ /* Remap the start sector of partition */
++ if (hddio)
++ bio->bi_sector += dmc->dev_start_sect;
++ bio->bi_rw |= rw;
++ bio->bi_end_io = eio_endio;
++ bio->bi_private = io;
++
++ while (remaining) {
++ page = pagelist[pindex];
++ len =
++ min_t(unsigned long, PAGE_SIZE,
++ to_bytes(remaining));
++ offset = 0;
++
++ if (!bio_add_page(bio, page, len, offset))
++ break;
++
++ remaining -= eio_to_sector(len);
++ pindex++;
++ remaining_bvecs--;
++ }
++
++ atomic_inc(&io->count);
++ if (hddio)
++ dmc->origmfn(bdev_get_queue(bio->bi_bdev), bio);
++
++ else
++ submit_bio(rw, bio);
++
++ } while (remaining);
++
++ EIO_ASSERT(remaining_bvecs == 0);
++ return ret;
++}
++
++/*
++ * This function will dispatch the i/o. It also takes care of
++ * splitting the large I/O requets to smaller I/Os which may not
++ * fit into single bio.
++ */
++
++static int eio_dispatch_io(struct cache_c *dmc, struct eio_io_region *where,
++ int rw, struct bio_vec *bvec, struct eio_context *io,
++ int hddio, int num_vecs, int sync)
++{
++ struct bio *bio;
++ struct page *page;
++ unsigned long len;
++ unsigned offset;
++ int num_bvecs;
++ int remaining_bvecs = num_vecs;
++ int ret = 0;
++
++ sector_t remaining = where->count;
++
++ do {
++ /* Verify that num_vecs should not cross the threshhold */
++ /* Check how many max bvecs bdev supports */
++ num_bvecs =
++ min_t(int, bio_get_nr_vecs(where->bdev), remaining_bvecs);
++ bio = bio_alloc(GFP_NOIO, num_bvecs);
++ bio->bi_bdev = where->bdev;
++ bio->bi_sector = where->sector + (where->count - remaining);
++
++ /* Remap the start sector of partition */
++ if (hddio)
++ bio->bi_sector += dmc->dev_start_sect;
++ bio->bi_rw |= rw;
++ bio->bi_end_io = eio_endio;
++ bio->bi_private = io;
++
++ while (remaining) {
++ page = bvec->bv_page;
++ len =
++ min_t(unsigned long, bvec->bv_len,
++ to_bytes(remaining));
++ offset = bvec->bv_offset;
++
++ if (!bio_add_page(bio, page, len, offset))
++ break;
++
++ offset = 0;
++ remaining -= eio_to_sector(len);
++ bvec = bvec + 1;
++ remaining_bvecs--;
++ }
++
++ atomic_inc(&io->count);
++ if (hddio)
++ dmc->origmfn(bdev_get_queue(bio->bi_bdev), bio);
++ else
++ submit_bio(rw, bio);
++
++ } while (remaining);
++
++ EIO_ASSERT(remaining_bvecs == 0);
++ return ret;
++}
++
++static int eio_async_io(struct cache_c *dmc, struct eio_io_region *where,
++ int rw, struct eio_io_request *req)
++{
++ struct eio_context *io;
++ int err = 0;
++
++ io = mempool_alloc(_io_pool, GFP_NOIO);
++ if (unlikely(io == NULL)) {
++ pr_err("eio_async_io: failed to allocate eio_context.\n");
++ return -ENOMEM;
++ }
++ memset((char *)io, 0, sizeof(struct eio_context));
++
++ atomic_set(&io->count, 1);
++ io->callback = req->notify;
++ io->context = req->context;
++ io->event = NULL;
++
++ switch (req->mtype) {
++ case EIO_BVECS:
++ err =
++ eio_dispatch_io(dmc, where, rw, req->dptr.pages, io,
++ req->hddio, req->num_bvecs, 0);
++ break;
++
++ case EIO_PAGES:
++ err =
++ eio_dispatch_io_pages(dmc, where, rw, req->dptr.plist, io,
++ req->hddio, req->num_bvecs, 0);
++ break;
++ }
++
++ /* Check if i/o submission has returned any error */
++ if (unlikely(err)) {
++ /* Wait for any i/os which are submitted, to end. */
++retry:
++ if (atomic_read(&io->count) != 1) {
++ schedule_timeout(msecs_to_jiffies(1));
++ goto retry;
++ }
++
++ EIO_ASSERT(io != NULL);
++ mempool_free(io, _io_pool);
++ io = NULL;
++ return err;
++ }
++
++ /* Drop the extra reference count here */
++ eio_dec_count(io, err);
++ return err;
++}
++
++static int eio_sync_io(struct cache_c *dmc, struct eio_io_region *where,
++ int rw, struct eio_io_request *req)
++{
++ int ret = 0;
++ struct eio_context io;
++
++ DECLARE_COMPLETION_ONSTACK(wait);
++
++ memset((char *)&io, 0, sizeof(io));
++
++ atomic_set(&io.count, 1);
++ io.event = &wait;
++ io.callback = NULL;
++ io.context = NULL;
++
++ /* For synchronous I/Os pass SYNC */
++ rw |= REQ_SYNC;
++
++ switch (req->mtype) {
++ case EIO_BVECS:
++ ret = eio_dispatch_io(dmc, where, rw, req->dptr.pages,
++ &io, req->hddio, req->num_bvecs, 1);
++ break;
++ case EIO_PAGES:
++ ret = eio_dispatch_io_pages(dmc, where, rw, req->dptr.plist,
++ &io, req->hddio, req->num_bvecs, 1);
++ break;
++ }
++
++ /* Check if i/o submission has returned any error */
++ if (unlikely(ret)) {
++ /* Wait for any i/os which are submitted, to end. */
++retry:
++ if (atomic_read(&(io.count)) != 1) {
++ schedule_timeout(msecs_to_jiffies(1));
++ goto retry;
++ }
++
++ return ret;
++ }
++
++ /* Drop extra reference count here */
++ eio_dec_count(&io, ret);
++ wait_for_completion(&wait);
++
++ if (io.error)
++ ret = io.error;
++
++ return ret;
++}
++
++int eio_do_io(struct cache_c *dmc, struct eio_io_region *where, int rw,
++ struct eio_io_request *io_req)
++{
++ if (!io_req->notify)
++ return eio_sync_io(dmc, where, rw, io_req);
++
++ return eio_async_io(dmc, where, rw, io_req);
++}
++
++void eio_process_zero_size_bio(struct cache_c *dmc, struct bio *origbio)
++{
++ unsigned long rw_flags = 0;
++
++ /* Extract bio flags from original bio */
++ rw_flags = origbio->bi_rw;
++
++ EIO_ASSERT(origbio->bi_size == 0);
++ EIO_ASSERT(rw_flags != 0);
++
++ eio_issue_empty_barrier_flush(dmc->cache_dev->bdev, NULL,
++ EIO_SSD_DEVICE, NULL, rw_flags);
++ eio_issue_empty_barrier_flush(dmc->disk_dev->bdev, origbio,
++ EIO_HDD_DEVICE, dmc->origmfn, rw_flags);
++}
++
++static void eio_bio_end_empty_barrier(struct bio *bio, int err)
++{
++ if (bio->bi_private)
++ bio_endio(bio->bi_private, err);
++ bio_put(bio);
++ return;
++}
++
++static void eio_issue_empty_barrier_flush(struct block_device *bdev,
++ struct bio *orig_bio, int device,
++ make_request_fn *origmfn,
++ int rw_flags)
++{
++ struct bio *bio;
++
++ bio = bio_alloc(GFP_KERNEL, 0);
++ if (!bio)
++ if (orig_bio)
++ bio_endio(orig_bio, -ENOMEM);
++ bio->bi_end_io = eio_bio_end_empty_barrier;
++ bio->bi_private = orig_bio;
++ bio->bi_bdev = bdev;
++ bio->bi_rw |= rw_flags;
++
++ bio_get(bio);
++ if (device == EIO_HDD_DEVICE)
++ origmfn(bdev_get_queue(bio->bi_bdev), bio);
++
++ else
++ submit_bio(0, bio);
++ bio_put(bio);
++ return;
++}
++
++static int eio_finish_nrdirty(struct cache_c *dmc)
++{
++ int index;
++ int ret = 0;
++ int retry_count;
++
++ /*
++ * Due to any transient errors, finish_nr_dirty may not drop
++ * to zero. Retry the clean operations for FINISH_NRDIRTY_RETRY_COUNT.
++ */
++ retry_count = FINISH_NRDIRTY_RETRY_COUNT;
++
++ index = EIO_HASH_BDEV(dmc->disk_dev->bdev->bd_contains->bd_dev);
++ down_write(&eio_ttc_lock[index]);
++
++ /* Wait for the in-flight I/Os to drain out */
++ while (atomic64_read(&dmc->nr_ios) != 0) {
++ pr_debug("finish_nrdirty: Draining I/O inflight\n");
++ schedule_timeout(msecs_to_jiffies(1));
++ }
++ EIO_ASSERT(!(dmc->sysctl_active.do_clean & EIO_CLEAN_START));
++
++ dmc->sysctl_active.do_clean |= EIO_CLEAN_KEEP | EIO_CLEAN_START;
++ up_write(&eio_ttc_lock[index]);
++
++ /*
++ * In the process of cleaning CACHE if CACHE turns to FAILED state,
++ * its a severe error.
++ */
++ do {
++ if (unlikely(CACHE_FAILED_IS_SET(dmc))) {
++ pr_err
++ ("finish_nrdirty: CACHE \"%s\" is in FAILED state.",
++ dmc->cache_name);
++ ret = -ENODEV;
++ break;
++ }
++
++ if (!dmc->sysctl_active.fast_remove)
++ eio_clean_all(dmc);
++ } while (!dmc->sysctl_active.fast_remove &&
++ (atomic64_read(&dmc->nr_dirty) > 0)
++ && (!(dmc->cache_flags & CACHE_FLAGS_SHUTDOWN_INPROG)));
++ dmc->sysctl_active.do_clean &= ~EIO_CLEAN_START;
++
++ /*
++ * If all retry_count exhausted and nr_dirty is still not zero.
++ * Return error.
++ */
++ if (((dmc->cache_flags & CACHE_FLAGS_SHUTDOWN_INPROG) ||
++ (retry_count == 0)) && (atomic64_read(&dmc->nr_dirty) > 0))
++ ret = -EINVAL;
++ if (ret)
++ pr_err
++ ("finish_nrdirty: Failed to finish %llu dirty blocks for cache \"%s\".",
++ (unsigned long long)atomic64_read(&dmc->nr_dirty), dmc->cache_name);
++
++ return ret;
++}
++
++int eio_cache_edit(char *cache_name, u_int32_t mode, u_int32_t policy)
++{
++ int error = 0;
++ int index;
++ struct cache_c *dmc;
++ uint32_t old_time_thresh = 0;
++ int restart_async_task = 0;
++ int ret;
++
++ EIO_ASSERT((mode != 0) || (policy != 0));
++
++ dmc = eio_cache_lookup(cache_name);
++ if (NULL == dmc) {
++ pr_err("cache_edit: cache %s do not exist", cache_name);
++ return -EINVAL;
++ }
++
++ if ((dmc->mode == mode) && (dmc->req_policy == policy))
++ return 0;
++
++ if (unlikely(CACHE_FAILED_IS_SET(dmc)) ||
++ unlikely(CACHE_DEGRADED_IS_SET(dmc))) {
++ pr_err("cache_edit: Cannot proceed with edit on cache \"%s\"" \
++ ". Cache is in failed or degraded state.",
++ dmc->cache_name);
++ return -EINVAL;
++ }
++
++ spin_lock_irqsave(&dmc->cache_spin_lock, dmc->cache_spin_lock_flags);
++ if (dmc->cache_flags & CACHE_FLAGS_SHUTDOWN_INPROG) {
++ pr_err("cache_edit: system shutdown in progress, cannot edit" \
++ " cache %s", cache_name);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return -EINVAL;
++ }
++ if (dmc->cache_flags & CACHE_FLAGS_MOD_INPROG) {
++ pr_err("cache_edit: simultaneous edit/delete operation on " \
++ "cache %s is not permitted", cache_name);
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ return -EINVAL;
++ }
++ dmc->cache_flags |= CACHE_FLAGS_MOD_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ old_time_thresh = dmc->sysctl_active.time_based_clean_interval;
++
++ if (dmc->mode == CACHE_MODE_WB) {
++ if (CACHE_FAILED_IS_SET(dmc)) {
++ pr_err
++ ("cache_edit: Can not proceed with edit for Failed cache \"%s\".",
++ dmc->cache_name);
++ error = -EINVAL;
++ goto out;
++ }
++ eio_stop_async_tasks(dmc);
++ restart_async_task = 1;
++ }
++
++ /* Wait for nr_dirty to drop to zero */
++ if (dmc->mode == CACHE_MODE_WB && mode != CACHE_MODE_WB) {
++ if (CACHE_FAILED_IS_SET(dmc)) {
++ pr_err
++ ("cache_edit: Can not proceed with edit for Failed cache \"%s\".",
++ dmc->cache_name);
++ error = -EINVAL;
++ goto out;
++ }
++
++ error = eio_finish_nrdirty(dmc);
++ /* This error can mostly occur due to Device removal */
++ if (unlikely(error)) {
++ pr_err
++ ("cache_edit: nr_dirty FAILED to finish for cache \"%s\".",
++ dmc->cache_name);
++ goto out;
++ }
++ EIO_ASSERT((dmc->sysctl_active.do_clean & EIO_CLEAN_KEEP) &&
++ !(dmc->sysctl_active.do_clean & EIO_CLEAN_START));
++ EIO_ASSERT(dmc->sysctl_active.fast_remove ||
++ (atomic64_read(&dmc->nr_dirty) == 0));
++ }
++
++ index = EIO_HASH_BDEV(dmc->disk_dev->bdev->bd_contains->bd_dev);
++ down_write(&eio_ttc_lock[index]);
++
++ /* Wait for the in-flight I/Os to drain out */
++ while (atomic64_read(&dmc->nr_ios) != 0) {
++ pr_debug("cache_edit: Draining I/O inflight\n");
++ schedule_timeout(msecs_to_jiffies(1));
++ }
++
++ pr_debug("cache_edit: Blocking application I/O\n");
++
++ EIO_ASSERT(atomic64_read(&dmc->nr_ios) == 0);
++
++ /* policy change */
++ if ((policy != 0) && (policy != dmc->req_policy)) {
++ error = eio_policy_switch(dmc, policy);
++ if (error) {
++ up_write(&eio_ttc_lock[index]);
++ goto out;
++ }
++ }
++
++ /* mode change */
++ if ((mode != 0) && (mode != dmc->mode)) {
++ error = eio_mode_switch(dmc, mode);
++ if (error) {
++ up_write(&eio_ttc_lock[index]);
++ goto out;
++ }
++ }
++
++ dmc->sysctl_active.time_based_clean_interval = old_time_thresh;
++ /* write updated superblock */
++ error = eio_sb_store(dmc);
++ if (error) {
++ /* XXX: In case of error put the cache in degraded mode. */
++ pr_err("eio_cache_edit: superblock update failed(error %d)",
++ error);
++ goto out;
++ }
++
++ eio_procfs_dtr(dmc);
++ eio_procfs_ctr(dmc);
++
++ up_write(&eio_ttc_lock[index]);
++
++out:
++ dmc->sysctl_active.time_based_clean_interval = old_time_thresh;
++
++ /*
++ * Resetting EIO_CLEAN_START and EIO_CLEAN_KEEP flags.
++ * EIO_CLEAN_START flag should be restored if eio_stop_async_tasks()
++ * is not called in future.
++ */
++
++ dmc->sysctl_active.do_clean &= ~(EIO_CLEAN_START | EIO_CLEAN_KEEP);
++
++ /* Restart async-task for "WB" cache. */
++ if ((dmc->mode == CACHE_MODE_WB) && (restart_async_task == 1)) {
++ pr_debug("cache_edit: Restarting the clean_thread.\n");
++ EIO_ASSERT(dmc->clean_thread == NULL);
++ ret = eio_start_clean_thread(dmc);
++ if (ret) {
++ error = ret;
++ pr_err
++ ("cache_edit: Failed to restart async tasks. error=%d.\n",
++ ret);
++ }
++ if (dmc->sysctl_active.time_based_clean_interval &&
++ atomic64_read(&dmc->nr_dirty)) {
++ schedule_delayed_work(&dmc->clean_aged_sets_work,
++ dmc->
++ sysctl_active.time_based_clean_interval
++ * 60 * HZ);
++ dmc->is_clean_aged_sets_sched = 1;
++ }
++ }
++ spin_lock_irqsave(&dmc->cache_spin_lock, dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_MOD_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ pr_debug("eio_cache_edit: Allowing application I/O\n");
++ return error;
++}
++
++static int eio_mode_switch(struct cache_c *dmc, u_int32_t mode)
++{
++ int error = 0;
++ u_int32_t orig_mode;
++
++ EIO_ASSERT(dmc->mode != mode);
++ pr_debug("eio_mode_switch: mode switch from %u to %u\n",
++ dmc->mode, mode);
++
++ if (mode == CACHE_MODE_WB) {
++ orig_mode = dmc->mode;
++ dmc->mode = mode;
++
++ error = eio_allocate_wb_resources(dmc);
++ if (error) {
++ dmc->mode = orig_mode;
++ goto out;
++ }
++ } else if (dmc->mode == CACHE_MODE_WB) {
++ eio_free_wb_resources(dmc);
++ dmc->mode = mode;
++ } else { /* (RO -> WT) or (WT -> RO) */
++ EIO_ASSERT(((dmc->mode == CACHE_MODE_RO) && (mode == CACHE_MODE_WT))
++ || ((dmc->mode == CACHE_MODE_WT) &&
++ (mode == CACHE_MODE_RO)));
++ dmc->mode = mode;
++ }
++
++out:
++ if (error)
++ pr_err("mode_switch: Failed to switch mode, error: %d\n",
++ error);
++ return error;
++}
++
++/*
++ * XXX: Error handling.
++ * In case of error put the cache in degraded mode.
++ */
++
++static int eio_policy_switch(struct cache_c *dmc, u_int32_t policy)
++{
++ int error = -EINVAL;
++ struct eio_policy *old_policy_ops;
++
++ EIO_ASSERT(dmc->req_policy != policy);
++ old_policy_ops = dmc->policy_ops;
++
++ error = eio_policy_init(dmc);
++ if (error)
++ goto out;
++
++ error = eio_repl_blk_init(dmc->policy_ops);
++ if (error) {
++ error = -ENOMEM;
++ pr_err ("eio_policy_swtich: Unable to allocate memory for policy cache block");
++ goto out;
++ }
++
++ error = eio_repl_sets_init(dmc->policy_ops);
++ if (error) {
++ error = -ENOMEM;
++ pr_err ("eio_policy_switch: Failed to allocate memory for cache policy");
++ goto out;
++ }
++
++ eio_policy_lru_pushblks(dmc->policy_ops);
++ dmc->req_policy = policy;
++ return 0;
++
++out:
++ if (dmc->policy_ops != old_policy_ops)
++ eio_policy_free(dmc);
++ dmc->policy_ops = old_policy_ops;
++ return error;
++}
++
++void eio_free_wb_pages(struct page **pages, int allocated)
++{
++ /* Verify that allocated is never 0 or less that zero. */
++ if (allocated <= 0)
++ return;
++
++ do
++ put_page(pages[--allocated]);
++ while (allocated);
++
++ *pages = NULL;
++}
++
++void eio_free_wb_bvecs(struct bio_vec *bvec, int allocated, int blksize)
++{
++ int i;
++
++ if (allocated <= 0)
++ return;
++
++ for (i = 0; i < allocated; i++) {
++ switch (blksize) {
++ case BLKSIZE_2K:
++ /*
++ * For 2k blocksize, each page is shared between two
++ * bio_vecs. Hence make sure to put_page only for even
++ * indexes.
++ */
++ if (((i % 2) == 0) && bvec[i].bv_page) {
++ put_page(bvec[i].bv_page);
++ bvec[i].bv_page = NULL;
++ continue;
++ }
++
++ /* For odd index page should already have been freed. */
++ if ((i % 2))
++ bvec[i].bv_page = NULL;
++
++ continue;
++
++ case BLKSIZE_4K:
++ case BLKSIZE_8K:
++ if (bvec[i].bv_page) {
++ put_page(bvec[i].bv_page);
++ bvec[i].bv_page = NULL;
++ }
++
++ continue;
++ }
++ }
++}
++
++/*
++ * This function allocates pages to array of bvecs allocated by caller.
++ * It has special handling of blocksize of 2k where single page is
++ * shared between two bio_vecs.
++ */
++
++int eio_alloc_wb_bvecs(struct bio_vec *bvec, int max, int blksize)
++{
++ int i, ret;
++ struct bio_vec *iovec;
++ struct page *page;
++
++ ret = 0;
++ iovec = bvec;
++ page = NULL;
++
++ for (i = 0; i < max; i++) {
++ switch (blksize) {
++ case BLKSIZE_2K:
++ /*
++ * In case of 2k blocksize, two biovecs will be sharing
++ * same page address. This is handled below.
++ */
++
++ if ((i % 2) == 0) {
++ /* Allocate page only for even bio vector */
++ page = alloc_page(GFP_KERNEL | __GFP_ZERO);
++ if (unlikely(!page)) {
++ pr_err
++ ("eio_alloc_wb_bvecs: System memory too low.\n");
++ goto err;
++ }
++ iovec[i].bv_page = page;
++ iovec[i].bv_len = to_bytes(blksize);
++ iovec[i].bv_offset = 0;
++ } else {
++ /* Let the odd biovec share page allocated earlier. */
++ EIO_ASSERT(page != NULL);
++ iovec[i].bv_page = page;
++ iovec[i].bv_len = to_bytes(blksize);
++ iovec[i].bv_offset =
++ PAGE_SIZE - to_bytes(blksize);
++
++ /* Mark page NULL here as it is not required anymore. */
++ page = NULL;
++ }
++
++ continue;
++
++ case BLKSIZE_4K:
++ case BLKSIZE_8K:
++ page = alloc_page(GFP_KERNEL | __GFP_ZERO);
++ if (unlikely(!page)) {
++ pr_err("eio_alloc_wb_bvecs:" \
++ " System memory too low.\n");
++ goto err;
++ }
++ iovec[i].bv_page = page;
++ iovec[i].bv_offset = 0;
++ iovec[i].bv_len = PAGE_SIZE;
++
++ page = NULL;
++ continue;
++ }
++ }
++
++ goto out;
++
++err:
++ if (i != max) {
++ if (i > 0)
++ eio_free_wb_bvecs(bvec, i, blksize);
++ ret = -ENOMEM;
++ }
++
++out:
++ return ret;
++}
++
++int eio_alloc_wb_pages(struct page **pages, int max)
++{
++ int i, ret = 0;
++ struct page *page;
++
++ for (i = 0; i < max; i++) {
++ page = alloc_page(GFP_KERNEL | __GFP_ZERO);
++ if (unlikely(!page)) {
++ pr_err("alloc_wb_pages: System memory too low.\n");
++ break;
++ }
++ pages[i] = page;
++ }
++
++ if (i != max) {
++ if (i > 0)
++ eio_free_wb_pages(pages, i);
++ ret = -ENOMEM;
++ goto out;
++ }
++
++out:
++ return ret;
++}
++
++/*
++ ****************************************************************************
++ * struct bio_vec *eio_alloc_pages(int max_pages, int *page_count)
++ * dmc : cache object
++ * pages : bio_vec to be allocated for synchronous I/O.
++ * page_count : total number of pages allocated.
++ ****************************************************************************
++ *
++ * This function allocates pages capped to minimum of
++ * MD_MAX_NR_PAGES OR maximun number of pages supported by
++ * block device.
++ * This is to ensure that the pages allocated should fit
++ * into single bio request.
++ */
++
++struct bio_vec *eio_alloc_pages(u_int32_t max_pages, int *page_count)
++{
++ int pcount, i;
++ struct bio_vec *pages;
++ int nr_pages;
++
++ /*
++ * Find out no. of pages supported by block device max capped to
++ * MD_MAX_NR_PAGES;
++ */
++ nr_pages = min_t(u_int32_t, max_pages, MD_MAX_NR_PAGES);
++
++ pages = kzalloc(nr_pages * sizeof(struct bio_vec), GFP_NOIO);
++ if (unlikely(!pages)) {
++ pr_err("eio_alloc_pages: System memory too low.\n");
++ return NULL;
++ }
++
++ pcount = 0;
++ for (i = 0; i < nr_pages; i++) {
++ pages[i].bv_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
++ if (unlikely(!pages[i].bv_page)) {
++ pr_err("eio_alloc_pages: System memory too low.\n");
++ break;
++ } else {
++ pages[i].bv_len = PAGE_SIZE;
++ pages[i].bv_offset = 0;
++ pcount++;
++ }
++ }
++
++ if (pcount == 0) {
++ pr_err("Single page allocation failed. System memory too low.");
++ kfree(pages);
++ return NULL;
++ }
++
++ /* following can be commented out later...
++ * we may have less pages allocated.
++ */
++ EIO_ASSERT(pcount == nr_pages);
++
++ /* Set the return values here */
++ *page_count = pcount;
++ return pages;
++}
++
++/*
++ * As part of reboot handling, stop all activies and mark the devices as
++ * read only.
++ */
++
++int eio_reboot_handling(void)
++{
++ struct cache_c *dmc, *tempdmc = NULL;
++ int i, error;
++ uint32_t old_time_thresh;
++
++ if (eio_reboot_notified == EIO_REBOOT_HANDLING_DONE)
++ return 0;
++
++ (void)wait_on_bit_lock((void *)&eio_control->synch_flags,
++ EIO_HANDLE_REBOOT, eio_wait_schedule,
++ TASK_UNINTERRUPTIBLE);
++ if (eio_reboot_notified == EIO_REBOOT_HANDLING_DONE) {
++ clear_bit(EIO_HANDLE_REBOOT, (void *)&eio_control->synch_flags);
++ smp_mb__after_clear_bit();
++ wake_up_bit((void *)&eio_control->synch_flags,
++ EIO_HANDLE_REBOOT);
++ return 0;
++ }
++ EIO_ASSERT(eio_reboot_notified == 0);
++ eio_reboot_notified = EIO_REBOOT_HANDLING_INPROG;
++
++ for (i = 0; i < EIO_HASHTBL_SIZE; i++) {
++ down_write(&eio_ttc_lock[i]);
++ list_for_each_entry(dmc, &eio_ttc_list[i], cachelist) {
++
++ kfree(tempdmc);
++ tempdmc = NULL;
++ if (unlikely(CACHE_FAILED_IS_SET(dmc)) ||
++ unlikely(CACHE_DEGRADED_IS_SET(dmc))) {
++ pr_err
++ ("Cache \"%s\" is in failed/degraded " \
++ "mode. Cannot mark cache read only.\n",
++ dmc->cache_name);
++ continue;
++ }
++
++ while (atomic64_read(&dmc->nr_ios) != 0) {
++ pr_debug("rdonly: Draining I/O inflight\n");
++ schedule_timeout(msecs_to_jiffies(10));
++ }
++
++ EIO_ASSERT(atomic64_read(&dmc->nr_ios) == 0);
++ EIO_ASSERT(dmc->cache_rdonly == 0);
++
++ /*
++ * Shutdown processing has the highest priority.
++ * Stop all ongoing activities.
++ */
++
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ EIO_ASSERT(!
++ (dmc->
++ cache_flags & CACHE_FLAGS_SHUTDOWN_INPROG));
++ dmc->cache_flags |= CACHE_FLAGS_SHUTDOWN_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++
++ /*
++ * Wait for ongoing edit/delete to complete.
++ */
++
++ while (dmc->cache_flags & CACHE_FLAGS_MOD_INPROG) {
++ up_write(&eio_ttc_lock[i]);
++ schedule_timeout(msecs_to_jiffies(1));
++ down_write(&eio_ttc_lock[i]);
++ }
++ if (dmc->cache_flags & CACHE_FLAGS_DELETED) {
++ /*
++ * Cache got deleted. Free the dmc.
++ */
++
++ tempdmc = dmc;
++ continue;
++ }
++ old_time_thresh =
++ dmc->sysctl_active.time_based_clean_interval;
++ eio_stop_async_tasks(dmc);
++ dmc->sysctl_active.time_based_clean_interval =
++ old_time_thresh;
++
++ dmc->cache_rdonly = 1;
++ pr_info("Cache \"%s\" marked read only\n",
++ dmc->cache_name);
++ up_write(&eio_ttc_lock[i]);
++
++ if (dmc->cold_boot && atomic64_read(&dmc->nr_dirty) &&
++ !eio_force_warm_boot) {
++ pr_info
++ ("Cold boot set for cache %s: Draining dirty blocks: %llu",
++ dmc->cache_name,
++ (unsigned long long)atomic64_read(&dmc->nr_dirty));
++ eio_clean_for_reboot(dmc);
++ }
++
++ error = eio_md_store(dmc);
++ if (error)
++ pr_err("Cannot mark cache \"%s\" read only\n",
++ dmc->cache_name);
++
++ spin_lock_irqsave(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++ dmc->cache_flags &= ~CACHE_FLAGS_SHUTDOWN_INPROG;
++ spin_unlock_irqrestore(&dmc->cache_spin_lock,
++ dmc->cache_spin_lock_flags);
++
++ down_write(&eio_ttc_lock[i]);
++ }
++ kfree(tempdmc);
++ tempdmc = NULL;
++ up_write(&eio_ttc_lock[i]);
++ }
++
++ eio_reboot_notified = EIO_REBOOT_HANDLING_DONE;
++ clear_bit(EIO_HANDLE_REBOOT, (void *)&eio_control->synch_flags);
++ smp_mb__after_clear_bit();
++ wake_up_bit((void *)&eio_control->synch_flags, EIO_HANDLE_REBOOT);
++ return 0;
++}
++
++static int eio_overlap_split_bio(struct request_queue *q, struct bio *bio)
++{
++ int i, nbios;
++ void **bioptr;
++ sector_t snum;
++ struct bio_container *bc;
++ unsigned bvec_idx;
++ unsigned bvec_consumed;
++
++ nbios = bio->bi_size >> SECTOR_SHIFT;
++ snum = bio->bi_sector;
++
++ bioptr = kmalloc(nbios * (sizeof(void *)), GFP_KERNEL);
++ if (!bioptr) {
++ bio_endio(bio, -ENOMEM);
++ return 0;
++ }
++ bc = kmalloc(sizeof(struct bio_container), GFP_NOWAIT);
++ if (!bc) {
++ bio_endio(bio, -ENOMEM);
++ kfree(bioptr);
++ return 0;
++ }
++
++ atomic_set(&bc->bc_holdcount, nbios);
++ bc->bc_bio = bio;
++ bc->bc_error = 0;
++
++ bvec_idx = bio->bi_idx;
++ bvec_consumed = 0;
++ for (i = 0; i < nbios; i++) {
++ bioptr[i] =
++ eio_split_new_bio(bio, bc, &bvec_idx,
++ &bvec_consumed, snum);
++ if (!bioptr[i])
++ break;
++ snum++;
++ }
++
++ /* Error: cleanup */
++ if (i < nbios) {
++ for (i--; i >= 0; i--)
++ bio_put(bioptr[i]);
++ bio_endio(bio, -ENOMEM);
++ kfree(bc);
++ goto out;
++ }
++
++ for (i = 0; i < nbios; i++)
++ eio_make_request_fn(q, bioptr[i]);
++
++out:
++ kfree(bioptr);
++ return 0;
++}
++
++static struct bio *eio_split_new_bio(struct bio *bio, struct bio_container *bc,
++ unsigned *bvec_idx,
++ unsigned *bvec_consumed, sector_t snum)
++{
++ struct bio *cbio;
++ unsigned iosize = 1 << SECTOR_SHIFT;
++
++ cbio = bio_alloc(GFP_NOIO, 1);
++ if (!cbio)
++ return NULL;
++
++ EIO_ASSERT(bio->bi_io_vec[*bvec_idx].bv_len >= iosize);
++
++ if (bio->bi_io_vec[*bvec_idx].bv_len <= *bvec_consumed) {
++ EIO_ASSERT(bio->bi_io_vec[*bvec_idx].bv_len == *bvec_consumed);
++ (*bvec_idx)++;
++ EIO_ASSERT(bio->bi_vcnt > *bvec_idx);
++ *bvec_consumed = 0;
++ }
++
++ cbio->bi_io_vec[0].bv_page = bio->bi_io_vec[*bvec_idx].bv_page;
++ cbio->bi_io_vec[0].bv_offset =
++ bio->bi_io_vec[*bvec_idx].bv_offset + *bvec_consumed;
++ cbio->bi_io_vec[0].bv_len = iosize;
++ *bvec_consumed += iosize;
++
++ cbio->bi_sector = snum;
++ cbio->bi_size = iosize;
++ cbio->bi_bdev = bio->bi_bdev;
++ cbio->bi_rw = bio->bi_rw;
++ cbio->bi_vcnt = 1;
++ cbio->bi_idx = 0;
++ cbio->bi_end_io = eio_split_endio;
++ cbio->bi_private = bc;
++ return cbio;
++}
++
++static void eio_split_endio(struct bio *bio, int error)
++{
++ struct bio_container *bc = bio->bi_private;
++
++ if (error)
++ bc->bc_error = error;
++ bio_put(bio);
++ if (atomic_dec_and_test(&bc->bc_holdcount)) {
++ bio_endio(bc->bc_bio, bc->bc_error);
++ kfree(bc);
++ }
++ return;
++}
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/eio_ttc.h linux-linaro-stable-mx6/drivers/block/enhanceio/eio_ttc.h
+--- linux-3.10.30.orig/drivers/block/enhanceio/eio_ttc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/eio_ttc.h 2014-05-15 20:33:46.541931294 +0200
+@@ -0,0 +1,152 @@
++/*
++ * Copyright (C) 2012 STEC, Inc. All rights not specifically granted
++ * under a license included herein are reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; under version 2 of the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ */
++
++#ifndef EIO_TTC_H
++#define EIO_TTC_H
++
++#ifdef __KERNEL__
++#include <linux/device-mapper.h>
++#define curthread get_current()
++#else
++#include <stdint.h>
++#endif /* __KERNEL__ */
++
++static inline bool bio_rw_flagged(struct bio *bio, int flag)
++{
++ return (bio->bi_rw & flag) != 0;
++}
++
++/*
++ * Whether the cached (source) device is a partition or a whole device.
++ * dmc->dev_info stores this info.
++ */
++enum eio_io_mem_type {
++ EIO_BVECS, /* bio vectors */
++ EIO_PAGES, /* array of pages */
++};
++
++struct eio_io_request {
++ enum eio_io_mem_type mtype;
++
++ union {
++ struct bio_vec *pages;
++ struct page **plist;
++ } dptr;
++
++ unsigned num_bvecs;
++ eio_notify_fn notify;
++ void *context;
++ unsigned hddio;
++};
++
++struct eio_context {
++ atomic_t count;
++ int error;
++ struct completion *event;
++ eio_notify_fn callback;
++ void *context;
++};
++
++int eio_do_io(struct cache_c *dmc, struct eio_io_region *where, int rw,
++ struct eio_io_request *io_req);
++
++enum eio_device {
++ EIO_HDD_DEVICE = 1,
++ EIO_SSD_DEVICE,
++};
++
++enum eio_dev_info {
++ EIO_DEV_PARTITION = 1,
++ EIO_DEV_WHOLE_DISK
++};
++
++enum eio_cache_state {
++ DMC_TTC_INITIALIZING = 1,
++ DMC_TTC_READY,
++ DMC_TTC_IO_FREEZE,
++ DMC_TTC_UNINITIALIZING,
++ DMC_TTC_UNINITIALIZED
++};
++
++#ifdef __KERNEL__
++
++#define EIO_HASHTBL_SIZE 1024
++
++/*
++ * In case of i/o errors while eio_clean_all, retry for
++ * finish_nrdirty_retry count.
++ */
++#define FINISH_NRDIRTY_RETRY_COUNT 2
++
++#define EIO_HASH_BDEV(dev) \
++ ((MAJOR(dev) * EIO_MAGIC + MINOR(dev)) % EIO_HASHTBL_SIZE)
++
++/*
++ * Reboot status flags.
++ */
++
++#define EIO_REBOOT_HANDLING_INPROG 0x01
++#define EIO_REBOOT_HANDLING_DONE 0x02
++
++/*
++ * kernel function prototypes.
++ */
++
++extern int eio_create_misc_device(void);
++extern int eio_delete_misc_device(void);
++
++extern int eio_ttc_get_device(const char *, fmode_t, struct eio_bdev **);
++extern void eio_ttc_put_device(struct eio_bdev **);
++
++extern struct cache_c *eio_cache_lookup(char *);
++extern int eio_ttc_activate(struct cache_c *);
++extern int eio_ttc_deactivate(struct cache_c *, int);
++extern void eio_ttc_init(void);
++
++extern int eio_cache_create(struct cache_rec_short *);
++extern int eio_cache_delete(char *, int);
++extern uint64_t eio_get_cache_count(void);
++extern int eio_get_cache_list(unsigned long *);
++
++extern int eio_handle_ssd_message(char *cache_name, char *ssd_name,
++ enum dev_notifier note);
++
++int eio_do_preliminary_checks(struct cache_c *);
++
++extern int eio_allocate_wb_resources(struct cache_c *);
++extern void eio_free_wb_resources(struct cache_c *);
++
++extern int eio_cache_edit(char *, u_int32_t, u_int32_t);
++
++extern void eio_stop_async_tasks(struct cache_c *dmc);
++extern int eio_start_clean_thread(struct cache_c *dmc);
++
++extern int eio_policy_init(struct cache_c *);
++extern void eio_policy_free(struct cache_c *);
++extern int eio_alloc_wb_pages(struct page **pages, int max);
++extern void eio_free_wb_pages(struct page **pages, int allocated);
++extern int eio_alloc_wb_bvecs(struct bio_vec *bvec, int max, int blksize);
++extern void eio_free_wb_bvecs(struct bio_vec *bvec, int allocated, int blksize);
++extern struct bio_vec *eio_alloc_pages(u_int32_t max_pages, int *page_count);
++extern int eio_md_store(struct cache_c *);
++extern int eio_reboot_handling(void);
++extern void eio_process_zero_size_bio(struct cache_c *dmc, struct bio *origbio);
++extern long eio_ioctl(struct file *filp, unsigned cmd, unsigned long arg);
++extern long eio_compact_ioctl(struct file *filp, unsigned cmd,
++ unsigned long arg);
++#endif /* __KERNEL__ */
++
++#endif /* EIO_TTC_H */
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/Kconfig linux-linaro-stable-mx6/drivers/block/enhanceio/Kconfig
+--- linux-3.10.30.orig/drivers/block/enhanceio/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/Kconfig 2014-05-15 20:33:45.313922441 +0200
+@@ -0,0 +1,21 @@
++#
++# EnhanceIO caching solution by STEC INC.
++#
++
++config ENHANCEIO
++ tristate "Enable EnhanceIO"
++ depends on PROC_FS
++ default m
++ ---help---
++ Based on Facebook's open source Flashcache project developed by
++ Mohan Srinivasan and hosted at "http://github.com", EnhanceIO is
++ a collection of (currently three) loadable kernel modules for
++ using SSDs as cache devices for traditional rotating hard disk
++
++ The caching engine is a loadable kernel module ("enhanceio.ko")
++ implemented as a device mapper target. The cache replacement
++ policies are implemented as loadable kernel modules
++ ("enhanceio_fifo.ko", "enhanceio_lru.ko") that register with
++ the caching engine module.
++
++ If unsure, say N.
+diff -Nur linux-3.10.30.orig/drivers/block/enhanceio/Makefile linux-linaro-stable-mx6/drivers/block/enhanceio/Makefile
+--- linux-3.10.30.orig/drivers/block/enhanceio/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/enhanceio/Makefile 2014-05-15 20:33:45.313922441 +0200
+@@ -0,0 +1,66 @@
++# test
++# Makefile for EnhanceIO block device caching.
++#
++
++COMMIT_REV ?= $(shell echo)
++KERNEL_SOURCE_VERSION ?= $(shell uname -r)
++KERNEL_TREE ?= /lib/modules/$(KERNEL_SOURCE_VERSION)/build
++EXTRA_CFLAGS += -I$(KERNEL_TREE)/drivers/md -I./ -DCOMMIT_REV="\"$(COMMIT_REV)\""
++EXTRA_CFLAGS += -I$(KERNEL_TREE)/include/ -I$(KERNEL_TREE)/include/linux
++# Check for RHEL/CentOS
++RHEL5_VER ?= $(shell if [ -e /etc/redhat-release ]; then grep 5.[0-9] /etc/redhat-release; else false; fi)
++RHEL5_SETUP :=
++ifneq "$(RHEL5_VER)" ""
++ RHEL5_SETUP := rhel5-setup
++ RHEL5_SPEC := /usr/src/redhat/SPECS/kernel.spec
++ RHEL5_TREE := /usr/src/redhat/BUILD/kernel-2.6.18/linux-$(shell uname -r).$(shell uname -i)
++ RHEL5_SRC := /usr/src/kernels/$(shell uname -r)-$(shell uname -i)
++ KERNEL_TREE := $(RHEL5_TREE)
++endif
++# Check for OpenVZ (/proc/vz)
++OPENVZ_VER ?= $(shell if [ -e /proc/vz ]; then grep 5.[0-9] /etc/redhat-release; else false; fi)
++ifneq "$(OPENVZ_VER)" ""
++ RHEL5_SPEC := /usr/src/redhat/SPECS/kernel-ovz.spec
++ RHEL5_TREE := /usr/src/redhat/BUILD/ovzkernel-2.6.18/linux-$(shell uname -r).$(shell uname -i)
++ KERNEL_TREE := $(RHEL5_TREE)
++endif
++obj-m += enhanceio.o enhanceio_lru.o enhanceio_fifo.o enhanceio_rand.o
++enhanceio-y += \
++ eio_conf.o \
++ eio_ioctl.o \
++ eio_main.o \
++ eio_mem.o \
++ eio_policy.o \
++ eio_procfs.o \
++ eio_setlru.o \
++ eio_subr.o \
++ eio_ttc.o
++enhanceio_fifo-y += eio_fifo.o
++enhanceio_rand-y += eio_rand.o
++enhanceio_lru-y += eio_lru.o
++.PHONY: all
++all: modules
++.PHONY: modules
++modules: $(RHEL5_SETUP)
++ make -C $(KERNEL_TREE) M=$(PWD) modules V=0
++.PHONY: modules_install
++modules_install: modules
++ install -o root -g root -m 0755 -d $(DESTDIR)/lib/modules/$(KERNEL_SOURCE_VERSION)/extra/enhanceio/
++ install -o root -g root -m 0755 enhanceio.ko $(DESTDIR)/lib/modules/$(KERNEL_SOURCE_VERSION)/extra/enhanceio/
++ install -o root -g root -m 0755 enhanceio_rand.ko $(DESTDIR)/lib/modules/$(KERNEL_SOURCE_VERSION)/extra/enhanceio/
++ install -o root -g root -m 0755 enhanceio_fifo.ko $(DESTDIR)/lib/modules/$(KERNEL_SOURCE_VERSION)/extra/enhanceio/
++ install -o root -g root -m 0755 enhanceio_lru.ko $(DESTDIR)/lib/modules/$(KERNEL_SOURCE_VERSION)/extra/enhanceio/
++ depmod -a
++.PHONY: install
++install: modules_install
++.PHONY: clean
++clean:
++ make -C $(KERNEL_TREE) M=$(PWD) clean
++.PHONY: rhel5-setup
++rhel5-setup: $(RHEL5_TREE)
++ make -C $(RHEL5_TREE) oldconfig ; \
++ make -C $(RHEL5_TREE) prepare modules_prepare
++ ln -s -f $(RHEL5_SRC)/Module.symvers $(RHEL5_TREE)/Module.symvers
++$(RHEL5_TREE):
++ rpmbuild -bp --target=`uname -m` $(RHEL5_SPEC) 2>&1 | tee `dirname $(RHEL5_SPEC)`/prep.log
++
+diff -Nur linux-3.10.30.orig/drivers/block/Kconfig linux-linaro-stable-mx6/drivers/block/Kconfig
+--- linux-3.10.30.orig/drivers/block/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/Kconfig 2014-05-15 20:33:45.301922354 +0200
+@@ -541,4 +541,6 @@
+ To compile this driver as a module, choose M here: the
+ module will be called rsxx.
+
++source "drivers/block/enhanceio/Kconfig"
++
+ endif # BLK_DEV
+diff -Nur linux-3.10.30.orig/drivers/block/Makefile linux-linaro-stable-mx6/drivers/block/Makefile
+--- linux-3.10.30.orig/drivers/block/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/block/Makefile 2014-05-15 20:33:45.301922354 +0200
+@@ -42,5 +42,7 @@
+
+ obj-$(CONFIG_BLK_DEV_RSXX) += rsxx/
+
++obj-$(CONFIG_ENHANCEIO) += enhanceio/
++
+ nvme-y := nvme-core.o nvme-scsi.o
+ swim_mod-y := swim.o swim_asm.o
+diff -Nur linux-3.10.30.orig/drivers/bus/arm-cci.c linux-linaro-stable-mx6/drivers/bus/arm-cci.c
+--- linux-3.10.30.orig/drivers/bus/arm-cci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/bus/arm-cci.c 2014-05-15 20:33:46.649932072 +0200
+@@ -0,0 +1,945 @@
++/*
++ * CCI cache coherent interconnect driver
++ *
++ * Copyright (C) 2013 ARM Ltd.
++ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/arm-cci.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of_address.h>
++#include <linux/slab.h>
++
++#include <asm/cacheflush.h>
++#include <asm/irq_regs.h>
++#include <asm/pmu.h>
++#include <asm/smp_plat.h>
++
++#define DRIVER_NAME "CCI"
++
++#define CCI_PORT_CTRL 0x0
++#define CCI_CTRL_STATUS 0xc
++
++#define CCI_ENABLE_SNOOP_REQ 0x1
++#define CCI_ENABLE_DVM_REQ 0x2
++#define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
++
++struct cci_nb_ports {
++ unsigned int nb_ace;
++ unsigned int nb_ace_lite;
++};
++
++enum cci_ace_port_type {
++ ACE_INVALID_PORT = 0x0,
++ ACE_PORT,
++ ACE_LITE_PORT,
++};
++
++struct cci_ace_port {
++ void __iomem *base;
++ unsigned long phys;
++ enum cci_ace_port_type type;
++ struct device_node *dn;
++};
++
++static struct cci_ace_port *ports;
++static unsigned int nb_cci_ports;
++
++static void __iomem *cci_ctrl_base;
++static unsigned long cci_ctrl_phys;
++
++#ifdef CONFIG_HW_PERF_EVENTS
++
++static void __iomem *cci_pmu_base;
++
++#define CCI400_PMCR 0x0100
++
++#define CCI400_PMU_CYCLE_CNTR_BASE 0x0000
++#define CCI400_PMU_CNTR_BASE(idx) (CCI400_PMU_CYCLE_CNTR_BASE + (idx) * 0x1000)
++
++#define CCI400_PMCR_CEN 0x00000001
++#define CCI400_PMCR_RST 0x00000002
++#define CCI400_PMCR_CCR 0x00000004
++#define CCI400_PMCR_CCD 0x00000008
++#define CCI400_PMCR_EX 0x00000010
++#define CCI400_PMCR_DP 0x00000020
++#define CCI400_PMCR_NCNT_MASK 0x0000F800
++#define CCI400_PMCR_NCNT_SHIFT 11
++
++#define CCI400_PMU_EVT_SEL 0x000
++#define CCI400_PMU_CNTR 0x004
++#define CCI400_PMU_CNTR_CTRL 0x008
++#define CCI400_PMU_OVERFLOW 0x00C
++
++#define CCI400_PMU_OVERFLOW_FLAG 1
++
++enum cci400_perf_events {
++ CCI400_PMU_CYCLES = 0xFF
++};
++
++#define CCI400_PMU_EVENT_MASK 0xff
++#define CCI400_PMU_EVENT_SOURCE(event) ((event >> 5) & 0x7)
++#define CCI400_PMU_EVENT_CODE(event) (event & 0x1f)
++
++#define CCI400_PMU_EVENT_SOURCE_S0 0
++#define CCI400_PMU_EVENT_SOURCE_S4 4
++#define CCI400_PMU_EVENT_SOURCE_M0 5
++#define CCI400_PMU_EVENT_SOURCE_M2 7
++
++#define CCI400_PMU_EVENT_SLAVE_MIN 0x0
++#define CCI400_PMU_EVENT_SLAVE_MAX 0x13
++
++#define CCI400_PMU_EVENT_MASTER_MIN 0x14
++#define CCI400_PMU_EVENT_MASTER_MAX 0x1A
++
++#define CCI400_PMU_MAX_HW_EVENTS 5 /* CCI PMU has 4 counters + 1 cycle counter */
++
++#define CCI400_PMU_CYCLE_COUNTER_IDX 0
++#define CCI400_PMU_COUNTER0_IDX 1
++#define CCI400_PMU_COUNTER_LAST(cci_pmu) (CCI400_PMU_CYCLE_COUNTER_IDX + cci_pmu->num_events - 1)
++
++
++static struct perf_event *events[CCI400_PMU_MAX_HW_EVENTS];
++static unsigned long used_mask[BITS_TO_LONGS(CCI400_PMU_MAX_HW_EVENTS)];
++static struct pmu_hw_events cci_hw_events = {
++ .events = events,
++ .used_mask = used_mask,
++};
++
++static int cci_pmu_validate_hw_event(u8 hw_event)
++{
++ u8 ev_source = CCI400_PMU_EVENT_SOURCE(hw_event);
++ u8 ev_code = CCI400_PMU_EVENT_CODE(hw_event);
++
++ if (ev_source <= CCI400_PMU_EVENT_SOURCE_S4 &&
++ ev_code <= CCI400_PMU_EVENT_SLAVE_MAX)
++ return hw_event;
++ else if (CCI400_PMU_EVENT_SOURCE_M0 <= ev_source &&
++ ev_source <= CCI400_PMU_EVENT_SOURCE_M2 &&
++ CCI400_PMU_EVENT_MASTER_MIN <= ev_code &&
++ ev_code <= CCI400_PMU_EVENT_MASTER_MAX)
++ return hw_event;
++
++ return -EINVAL;
++}
++
++static inline int cci_pmu_counter_is_valid(struct arm_pmu *cci_pmu, int idx)
++{
++ return CCI400_PMU_CYCLE_COUNTER_IDX <= idx &&
++ idx <= CCI400_PMU_COUNTER_LAST(cci_pmu);
++}
++
++static inline u32 cci_pmu_read_register(int idx, unsigned int offset)
++{
++ return readl_relaxed(cci_pmu_base + CCI400_PMU_CNTR_BASE(idx) + offset);
++}
++
++static inline void cci_pmu_write_register(u32 value, int idx, unsigned int offset)
++{
++ return writel_relaxed(value, cci_pmu_base + CCI400_PMU_CNTR_BASE(idx) + offset);
++}
++
++static inline void cci_pmu_disable_counter(int idx)
++{
++ cci_pmu_write_register(0, idx, CCI400_PMU_CNTR_CTRL);
++}
++
++static inline void cci_pmu_enable_counter(int idx)
++{
++ cci_pmu_write_register(1, idx, CCI400_PMU_CNTR_CTRL);
++}
++
++static inline void cci_pmu_select_event(int idx, unsigned long event)
++{
++ event &= CCI400_PMU_EVENT_MASK;
++ cci_pmu_write_register(event, idx, CCI400_PMU_EVT_SEL);
++}
++
++static u32 cci_pmu_get_max_counters(void)
++{
++ u32 n_cnts = (readl_relaxed(cci_ctrl_base + CCI400_PMCR) &
++ CCI400_PMCR_NCNT_MASK) >> CCI400_PMCR_NCNT_SHIFT;
++
++ /* add 1 for cycle counter */
++ return n_cnts + 1;
++}
++
++static struct pmu_hw_events *cci_pmu_get_hw_events(void)
++{
++ return &cci_hw_events;
++}
++
++static int cci_pmu_get_event_idx(struct pmu_hw_events *hw, struct perf_event *event)
++{
++ struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
++ struct hw_perf_event *hw_event = &event->hw;
++ unsigned long cci_event = hw_event->config_base & CCI400_PMU_EVENT_MASK;
++ int idx;
++
++ if (cci_event == CCI400_PMU_CYCLES) {
++ if (test_and_set_bit(CCI400_PMU_CYCLE_COUNTER_IDX, hw->used_mask))
++ return -EAGAIN;
++
++ return CCI400_PMU_CYCLE_COUNTER_IDX;
++ }
++
++ for (idx = CCI400_PMU_COUNTER0_IDX; idx <= CCI400_PMU_COUNTER_LAST(cci_pmu); ++idx) {
++ if (!test_and_set_bit(idx, hw->used_mask))
++ return idx;
++ }
++
++ /* No counters available */
++ return -EAGAIN;
++}
++
++static int cci_pmu_map_event(struct perf_event *event)
++{
++ int mapping;
++ u8 config = event->attr.config & CCI400_PMU_EVENT_MASK;
++
++ if (event->attr.type < PERF_TYPE_MAX)
++ return -ENOENT;
++
++ /* 0xff is used to represent CCI Cycles */
++ if (config == 0xff)
++ mapping = config;
++ else
++ mapping = cci_pmu_validate_hw_event(config);
++
++ return mapping;
++}
++
++static int cci_pmu_request_irq(struct arm_pmu *cci_pmu, irq_handler_t handler)
++{
++ int irq, err, i = 0;
++ struct platform_device *pmu_device = cci_pmu->plat_device;
++
++ if (unlikely(!pmu_device))
++ return -ENODEV;
++
++ /* CCI exports 6 interrupts - 1 nERRORIRQ + 5 nEVNTCNTOVERFLOW (PMU)
++ nERRORIRQ will be handled by secure firmware on TC2. So we
++ assume that all CCI interrupts listed in the linux device
++ tree are PMU interrupts.
++
++ The following code should then be able to handle different routing
++ of the CCI PMU interrupts.
++ */
++ while ((irq = platform_get_irq(pmu_device, i)) > 0) {
++ err = request_irq(irq, handler, 0, "arm-cci-pmu", cci_pmu);
++ if (err) {
++ dev_err(&pmu_device->dev, "unable to request IRQ%d for ARM CCI PMU counters\n",
++ irq);
++ return err;
++ }
++ i++;
++ }
++
++ return 0;
++}
++
++static irqreturn_t cci_pmu_handle_irq(int irq_num, void *dev)
++{
++ struct arm_pmu *cci_pmu = (struct arm_pmu *)dev;
++ struct pmu_hw_events *events = cci_pmu->get_hw_events();
++ struct perf_sample_data data;
++ struct pt_regs *regs;
++ int idx;
++
++ regs = get_irq_regs();
++
++ /* Iterate over counters and update the corresponding perf events.
++ This should work regardless of whether we have per-counter overflow
++ interrupt or a combined overflow interrupt. */
++ for (idx = CCI400_PMU_CYCLE_COUNTER_IDX; idx <= CCI400_PMU_COUNTER_LAST(cci_pmu); idx++) {
++ struct perf_event *event = events->events[idx];
++ struct hw_perf_event *hw_counter;
++
++ if (!event)
++ continue;
++
++ hw_counter = &event->hw;
++
++ /* Did this counter overflow? */
++ if (!(cci_pmu_read_register(idx, CCI400_PMU_OVERFLOW) & CCI400_PMU_OVERFLOW_FLAG))
++ continue;
++ cci_pmu_write_register(CCI400_PMU_OVERFLOW_FLAG, idx, CCI400_PMU_OVERFLOW);
++
++ armpmu_event_update(event);
++ perf_sample_data_init(&data, 0, hw_counter->last_period);
++ if (!armpmu_event_set_period(event))
++ continue;
++
++ if (perf_event_overflow(event, &data, regs))
++ cci_pmu->disable(event);
++ }
++
++ irq_work_run();
++ return IRQ_HANDLED;
++}
++
++static void cci_pmu_free_irq(struct arm_pmu *cci_pmu)
++{
++ int irq, i = 0;
++ struct platform_device *pmu_device = cci_pmu->plat_device;
++
++ while ((irq = platform_get_irq(pmu_device, i)) > 0) {
++ free_irq(irq, cci_pmu);
++ i++;
++ }
++}
++
++static void cci_pmu_enable_event(struct perf_event *event)
++{
++ unsigned long flags;
++ struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
++ struct pmu_hw_events *events = cci_pmu->get_hw_events();
++ struct hw_perf_event *hw_counter = &event->hw;
++ int idx = hw_counter->idx;
++
++ if (unlikely(!cci_pmu_counter_is_valid(cci_pmu, idx))) {
++ dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
++ return;
++ }
++
++ raw_spin_lock_irqsave(&events->pmu_lock, flags);
++
++ /* Configure the event to count, unless you are counting cycles */
++ if (idx != CCI400_PMU_CYCLE_COUNTER_IDX)
++ cci_pmu_select_event(idx, hw_counter->config_base);
++
++ cci_pmu_enable_counter(idx);
++
++ raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
++}
++
++static void cci_pmu_disable_event(struct perf_event *event)
++{
++ unsigned long flags;
++ struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
++ struct pmu_hw_events *events = cci_pmu->get_hw_events();
++ struct hw_perf_event *hw_counter = &event->hw;
++ int idx = hw_counter->idx;
++
++ if (unlikely(!cci_pmu_counter_is_valid(cci_pmu, idx))) {
++ dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
++ return;
++ }
++
++ raw_spin_lock_irqsave(&events->pmu_lock, flags);
++
++ cci_pmu_disable_counter(idx);
++
++ raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
++}
++
++static void cci_pmu_start(struct arm_pmu *cci_pmu)
++{
++ u32 val;
++ unsigned long flags;
++ struct pmu_hw_events *events = cci_pmu->get_hw_events();
++
++ raw_spin_lock_irqsave(&events->pmu_lock, flags);
++
++ /* Enable all the PMU counters. */
++ val = readl(cci_ctrl_base + CCI400_PMCR) | CCI400_PMCR_CEN;
++ writel(val, cci_ctrl_base + CCI400_PMCR);
++
++ raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
++}
++
++static void cci_pmu_stop(struct arm_pmu *cci_pmu)
++{
++ u32 val;
++ unsigned long flags;
++ struct pmu_hw_events *events = cci_pmu->get_hw_events();
++
++ raw_spin_lock_irqsave(&events->pmu_lock, flags);
++
++ /* Disable all the PMU counters. */
++ val = readl(cci_ctrl_base + CCI400_PMCR) & ~CCI400_PMCR_CEN;
++ writel(val, cci_ctrl_base + CCI400_PMCR);
++
++ raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
++}
++
++static u32 cci_pmu_read_counter(struct perf_event *event)
++{
++ struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
++ struct hw_perf_event *hw_counter = &event->hw;
++ int idx = hw_counter->idx;
++ u32 value;
++
++ if (unlikely(!cci_pmu_counter_is_valid(cci_pmu, idx))) {
++ dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
++ return 0;
++ }
++ value = cci_pmu_read_register(idx, CCI400_PMU_CNTR);
++
++ return value;
++}
++
++static void cci_pmu_write_counter(struct perf_event *event, u32 value)
++{
++ struct arm_pmu *cci_pmu = to_arm_pmu(event->pmu);
++ struct hw_perf_event *hw_counter = &event->hw;
++ int idx = hw_counter->idx;
++
++ if (unlikely(!cci_pmu_counter_is_valid(cci_pmu, idx)))
++ dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
++ else
++ cci_pmu_write_register(value, idx, CCI400_PMU_CNTR);
++}
++
++static struct arm_pmu cci_pmu = {
++ .name = DRIVER_NAME,
++ .max_period = (1LLU << 32) - 1,
++ .get_hw_events = cci_pmu_get_hw_events,
++ .get_event_idx = cci_pmu_get_event_idx,
++ .map_event = cci_pmu_map_event,
++ .request_irq = cci_pmu_request_irq,
++ .handle_irq = cci_pmu_handle_irq,
++ .free_irq = cci_pmu_free_irq,
++ .enable = cci_pmu_enable_event,
++ .disable = cci_pmu_disable_event,
++ .start = cci_pmu_start,
++ .stop = cci_pmu_stop,
++ .read_counter = cci_pmu_read_counter,
++ .write_counter = cci_pmu_write_counter,
++};
++
++static int cci_pmu_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ cci_pmu_base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(cci_pmu_base))
++ return PTR_ERR(cci_pmu_base);
++
++ cci_pmu.plat_device = pdev;
++ cci_pmu.num_events = cci_pmu_get_max_counters();
++ raw_spin_lock_init(&cci_hw_events.pmu_lock);
++ cpumask_setall(&cci_pmu.valid_cpus);
++
++ return armpmu_register(&cci_pmu, -1);
++}
++
++static const struct of_device_id arm_cci_pmu_matches[] = {
++ {.compatible = "arm,cci-400-pmu"},
++ {},
++};
++
++static struct platform_driver cci_pmu_platform_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .of_match_table = arm_cci_pmu_matches,
++ },
++ .probe = cci_pmu_probe,
++};
++
++static int __init cci_pmu_init(void)
++{
++ if (platform_driver_register(&cci_pmu_platform_driver))
++ WARN(1, "unable to register CCI platform driver\n");
++ return 0;
++}
++
++#else
++
++static int __init cci_pmu_init(void)
++{
++ return 0;
++}
++
++#endif /* CONFIG_HW_PERF_EVENTS */
++
++struct cpu_port {
++ u64 mpidr;
++ u32 port;
++};
++
++/*
++ * Use the port MSB as valid flag, shift can be made dynamic
++ * by computing number of bits required for port indexes.
++ * Code disabling CCI cpu ports runs with D-cache invalidated
++ * and SCTLR bit clear so data accesses must be kept to a minimum
++ * to improve performance; for now shift is left static to
++ * avoid one more data access while disabling the CCI port.
++ */
++#define PORT_VALID_SHIFT 31
++#define PORT_VALID (0x1 << PORT_VALID_SHIFT)
++
++static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
++{
++ port->port = PORT_VALID | index;
++ port->mpidr = mpidr;
++}
++
++static inline bool cpu_port_is_valid(struct cpu_port *port)
++{
++ return !!(port->port & PORT_VALID);
++}
++
++static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
++{
++ return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
++}
++
++static struct cpu_port cpu_port[NR_CPUS];
++
++/**
++ * __cci_ace_get_port - Function to retrieve the port index connected to
++ * a cpu or device.
++ *
++ * @dn: device node of the device to look-up
++ * @type: port type
++ *
++ * Return value:
++ * - CCI port index if success
++ * - -ENODEV if failure
++ */
++static int __cci_ace_get_port(struct device_node *dn, int type)
++{
++ int i;
++ bool ace_match;
++ struct device_node *cci_portn;
++
++ cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
++ for (i = 0; i < nb_cci_ports; i++) {
++ ace_match = ports[i].type == type;
++ if (ace_match && cci_portn == ports[i].dn)
++ return i;
++ }
++ return -ENODEV;
++}
++
++int cci_ace_get_port(struct device_node *dn)
++{
++ return __cci_ace_get_port(dn, ACE_LITE_PORT);
++}
++EXPORT_SYMBOL_GPL(cci_ace_get_port);
++
++static void __init cci_ace_init_ports(void)
++{
++ int port, ac, cpu;
++ u64 hwid;
++ const u32 *cell;
++ struct device_node *cpun, *cpus;
++
++ cpus = of_find_node_by_path("/cpus");
++ if (WARN(!cpus, "Missing cpus node, bailing out\n"))
++ return;
++
++ if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
++ ac = of_n_addr_cells(cpus);
++
++ /*
++ * Port index look-up speeds up the function disabling ports by CPU,
++ * since the logical to port index mapping is done once and does
++ * not change after system boot.
++ * The stashed index array is initialized for all possible CPUs
++ * at probe time.
++ */
++ for_each_child_of_node(cpus, cpun) {
++ if (of_node_cmp(cpun->type, "cpu"))
++ continue;
++ cell = of_get_property(cpun, "reg", NULL);
++ if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
++ continue;
++
++ hwid = of_read_number(cell, ac);
++ cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
++
++ if (cpu < 0 || !cpu_possible(cpu))
++ continue;
++ port = __cci_ace_get_port(cpun, ACE_PORT);
++ if (port < 0)
++ continue;
++
++ init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
++ }
++
++ for_each_possible_cpu(cpu) {
++ WARN(!cpu_port_is_valid(&cpu_port[cpu]),
++ "CPU %u does not have an associated CCI port\n",
++ cpu);
++ }
++}
++/*
++ * Functions to enable/disable a CCI interconnect slave port
++ *
++ * They are called by low-level power management code to disable slave
++ * interfaces snoops and DVM broadcast.
++ * Since they may execute with cache data allocation disabled and
++ * after the caches have been cleaned and invalidated the functions provide
++ * no explicit locking since they may run with D-cache disabled, so normal
++ * cacheable kernel locks based on ldrex/strex may not work.
++ * Locking has to be provided by BSP implementations to ensure proper
++ * operations.
++ */
++
++/**
++ * cci_port_control() - function to control a CCI port
++ *
++ * @port: index of the port to setup
++ * @enable: if true enables the port, if false disables it
++ */
++static void notrace cci_port_control(unsigned int port, bool enable)
++{
++ void __iomem *base = ports[port].base;
++
++ writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
++ /*
++ * This function is called from power down procedures
++ * and must not execute any instruction that might
++ * cause the processor to be put in a quiescent state
++ * (eg wfi). Hence, cpu_relax() can not be added to this
++ * read loop to optimize power, since it might hide possibly
++ * disruptive operations.
++ */
++ while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
++ ;
++}
++
++/**
++ * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
++ * reference
++ *
++ * @mpidr: mpidr of the CPU whose CCI port should be disabled
++ *
++ * Disabling a CCI port for a CPU implies disabling the CCI port
++ * controlling that CPU cluster. Code disabling CPU CCI ports
++ * must make sure that the CPU running the code is the last active CPU
++ * in the cluster ie all other CPUs are quiescent in a low power state.
++ *
++ * Return:
++ * 0 on success
++ * -ENODEV on port look-up failure
++ */
++int notrace cci_disable_port_by_cpu(u64 mpidr)
++{
++ int cpu;
++ bool is_valid;
++ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
++ is_valid = cpu_port_is_valid(&cpu_port[cpu]);
++ if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
++ cci_port_control(cpu_port[cpu].port, false);
++ return 0;
++ }
++ }
++ return -ENODEV;
++}
++EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
++
++/**
++ * cci_enable_port_for_self() - enable a CCI port for calling CPU
++ *
++ * Enabling a CCI port for the calling CPU implies enabling the CCI
++ * port controlling that CPU's cluster. Caller must make sure that the
++ * CPU running the code is the first active CPU in the cluster and all
++ * other CPUs are quiescent in a low power state or waiting for this CPU
++ * to complete the CCI initialization.
++ *
++ * Because this is called when the MMU is still off and with no stack,
++ * the code must be position independent and ideally rely on callee
++ * clobbered registers only. To achieve this we must code this function
++ * entirely in assembler.
++ *
++ * On success this returns with the proper CCI port enabled. In case of
++ * any failure this never returns as the inability to enable the CCI is
++ * fatal and there is no possible recovery at this stage.
++ */
++asmlinkage void __naked cci_enable_port_for_self(void)
++{
++ asm volatile ("\n"
++
++" mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n"
++" and r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
++" adr r1, 5f \n"
++" ldr r2, [r1] \n"
++" add r1, r1, r2 @ &cpu_port \n"
++" add ip, r1, %[sizeof_cpu_port] \n"
++
++ /* Loop over the cpu_port array looking for a matching MPIDR */
++"1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
++" cmp r2, r0 @ compare MPIDR \n"
++" bne 2f \n"
++
++ /* Found a match, now test port validity */
++" ldr r3, [r1, %[offsetof_cpu_port_port]] \n"
++" tst r3, #"__stringify(PORT_VALID)" \n"
++" bne 3f \n"
++
++ /* no match, loop with the next cpu_port entry */
++"2: add r1, r1, %[sizeof_struct_cpu_port] \n"
++" cmp r1, ip @ done? \n"
++" blo 1b \n"
++
++ /* CCI port not found -- cheaply try to stall this CPU */
++"cci_port_not_found: \n"
++" wfi \n"
++" wfe \n"
++" b cci_port_not_found \n"
++
++ /* Use matched port index to look up the corresponding ports entry */
++"3: bic r3, r3, #"__stringify(PORT_VALID)" \n"
++" adr r0, 6f \n"
++" ldmia r0, {r1, r2} \n"
++" sub r1, r1, r0 @ virt - phys \n"
++" ldr r0, [r0, r2] @ *(&ports) \n"
++" mov r2, %[sizeof_struct_ace_port] \n"
++" mla r0, r2, r3, r0 @ &ports[index] \n"
++" sub r0, r0, r1 @ virt_to_phys() \n"
++
++ /* Enable the CCI port */
++" ldr r0, [r0, %[offsetof_port_phys]] \n"
++" mov r3, #"__stringify(CCI_ENABLE_REQ)" \n"
++" str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
++
++ /* poll the status reg for completion */
++" adr r1, 7f \n"
++" ldr r0, [r1] \n"
++" ldr r0, [r0, r1] @ cci_ctrl_base \n"
++"4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
++" tst r1, #1 \n"
++" bne 4b \n"
++
++" mov r0, #0 \n"
++" bx lr \n"
++
++" .align 2 \n"
++"5: .word cpu_port - . \n"
++"6: .word . \n"
++" .word ports - 6b \n"
++"7: .word cci_ctrl_phys - . \n"
++ : :
++ [sizeof_cpu_port] "i" (sizeof(cpu_port)),
++#ifndef __ARMEB__
++ [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
++#else
++ [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
++#endif
++ [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
++ [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
++ [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
++ [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
++
++ unreachable();
++}
++
++/**
++ * __cci_control_port_by_device() - function to control a CCI port by device
++ * reference
++ *
++ * @dn: device node pointer of the device whose CCI port should be
++ * controlled
++ * @enable: if true enables the port, if false disables it
++ *
++ * Return:
++ * 0 on success
++ * -ENODEV on port look-up failure
++ */
++int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
++{
++ int port;
++
++ if (!dn)
++ return -ENODEV;
++
++ port = __cci_ace_get_port(dn, ACE_LITE_PORT);
++ if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
++ dn->full_name))
++ return -ENODEV;
++ cci_port_control(port, enable);
++ return 0;
++}
++EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
++
++/**
++ * __cci_control_port_by_index() - function to control a CCI port by port index
++ *
++ * @port: port index previously retrieved with cci_ace_get_port()
++ * @enable: if true enables the port, if false disables it
++ *
++ * Return:
++ * 0 on success
++ * -ENODEV on port index out of range
++ * -EPERM if operation carried out on an ACE PORT
++ */
++int notrace __cci_control_port_by_index(u32 port, bool enable)
++{
++ if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
++ return -ENODEV;
++ /*
++ * CCI control for ports connected to CPUS is extremely fragile
++ * and must be made to go through a specific and controlled
++ * interface (ie cci_disable_port_by_cpu(); control by general purpose
++ * indexing is therefore disabled for ACE ports.
++ */
++ if (ports[port].type == ACE_PORT)
++ return -EPERM;
++
++ cci_port_control(port, enable);
++ return 0;
++}
++EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
++
++static const struct cci_nb_ports cci400_ports = {
++ .nb_ace = 2,
++ .nb_ace_lite = 3
++};
++
++static const struct of_device_id arm_cci_matches[] = {
++ {.compatible = "arm,cci-400", .data = &cci400_ports },
++ {},
++};
++
++static const struct of_device_id arm_cci_ctrl_if_matches[] = {
++ {.compatible = "arm,cci-400-ctrl-if", },
++ {},
++};
++
++static int __init cci_probe(void)
++{
++ struct cci_nb_ports const *cci_config;
++ int ret, i, nb_ace = 0, nb_ace_lite = 0;
++ struct device_node *np, *cp;
++ struct resource res;
++ const char *match_str;
++ bool is_ace;
++
++ np = of_find_matching_node(NULL, arm_cci_matches);
++ if (!np)
++ return -ENODEV;
++
++ cci_config = of_match_node(arm_cci_matches, np)->data;
++ if (!cci_config)
++ return -ENODEV;
++
++ nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
++
++ ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
++ if (!ports)
++ return -ENOMEM;
++
++ ret = of_address_to_resource(np, 0, &res);
++ if (!ret) {
++ cci_ctrl_base = ioremap(res.start, resource_size(&res));
++ cci_ctrl_phys = res.start;
++ }
++ if (ret || !cci_ctrl_base) {
++ WARN(1, "unable to ioremap CCI ctrl\n");
++ ret = -ENXIO;
++ goto memalloc_err;
++ }
++
++ for_each_child_of_node(np, cp) {
++ if (!of_match_node(arm_cci_ctrl_if_matches, cp))
++ continue;
++
++ i = nb_ace + nb_ace_lite;
++
++ if (i >= nb_cci_ports)
++ break;
++
++ if (of_property_read_string(cp, "interface-type",
++ &match_str)) {
++ WARN(1, "node %s missing interface-type property\n",
++ cp->full_name);
++ continue;
++ }
++ is_ace = strcmp(match_str, "ace") == 0;
++ if (!is_ace && strcmp(match_str, "ace-lite")) {
++ WARN(1, "node %s containing invalid interface-type property, skipping it\n",
++ cp->full_name);
++ continue;
++ }
++
++ ret = of_address_to_resource(cp, 0, &res);
++ if (!ret) {
++ ports[i].base = ioremap(res.start, resource_size(&res));
++ ports[i].phys = res.start;
++ }
++ if (ret || !ports[i].base) {
++ WARN(1, "unable to ioremap CCI port %d\n", i);
++ continue;
++ }
++
++ if (is_ace) {
++ if (WARN_ON(nb_ace >= cci_config->nb_ace))
++ continue;
++ ports[i].type = ACE_PORT;
++ ++nb_ace;
++ } else {
++ if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
++ continue;
++ ports[i].type = ACE_LITE_PORT;
++ ++nb_ace_lite;
++ }
++ ports[i].dn = cp;
++ }
++
++ /* initialize a stashed array of ACE ports to speed-up look-up */
++ cci_ace_init_ports();
++
++ /*
++ * Multi-cluster systems may need this data when non-coherent, during
++ * cluster power-up/power-down. Make sure it reaches main memory.
++ */
++ sync_cache_w(&cci_ctrl_base);
++ sync_cache_w(&cci_ctrl_phys);
++ sync_cache_w(&ports);
++ sync_cache_w(&cpu_port);
++ __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
++ pr_info("ARM CCI driver probed\n");
++ return 0;
++
++memalloc_err:
++
++ kfree(ports);
++ return ret;
++}
++
++static int cci_init_status = -EAGAIN;
++static DEFINE_MUTEX(cci_probing);
++
++static int __init cci_init(void)
++{
++ if (cci_init_status != -EAGAIN)
++ return cci_init_status;
++
++ mutex_lock(&cci_probing);
++ if (cci_init_status == -EAGAIN)
++ cci_init_status = cci_probe();
++ mutex_unlock(&cci_probing);
++ return cci_init_status;
++}
++
++/*
++ * To sort out early init calls ordering a helper function is provided to
++ * check if the CCI driver has beed initialized. Function check if the driver
++ * has been initialized, if not it calls the init function that probes
++ * the driver and updates the return value.
++ */
++bool __init cci_probed(void)
++{
++ return cci_init() == 0;
++}
++EXPORT_SYMBOL_GPL(cci_probed);
++
++early_initcall(cci_init);
++core_initcall(cci_pmu_init);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("ARM CCI support");
+diff -Nur linux-3.10.30.orig/drivers/bus/imx-weim.c linux-linaro-stable-mx6/drivers/bus/imx-weim.c
+--- linux-3.10.30.orig/drivers/bus/imx-weim.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/bus/imx-weim.c 2014-05-15 20:33:46.649932072 +0200
+@@ -0,0 +1,138 @@
++/*
++ * EIM driver for Freescale's i.MX chips
++ *
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/of_device.h>
++
++struct imx_weim {
++ void __iomem *base;
++ struct clk *clk;
++};
++
++static const struct of_device_id weim_id_table[] = {
++ { .compatible = "fsl,imx6q-weim", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, weim_id_table);
++
++#define CS_TIMING_LEN 6
++#define CS_REG_RANGE 0x18
++
++/* Parse and set the timing for this device. */
++static int
++weim_timing_setup(struct platform_device *pdev, struct device_node *np)
++{
++ struct imx_weim *weim = platform_get_drvdata(pdev);
++ u32 value[CS_TIMING_LEN];
++ u32 cs_idx;
++ int ret;
++ int i;
++
++ /* get the CS index from this child node's "reg" property. */
++ ret = of_property_read_u32(np, "reg", &cs_idx);
++ if (ret)
++ return ret;
++
++ /* The weim has four chip selects. */
++ if (cs_idx > 3)
++ return -EINVAL;
++
++ ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
++ value, CS_TIMING_LEN);
++ if (ret)
++ return ret;
++
++ /* set the timing for WEIM */
++ for (i = 0; i < CS_TIMING_LEN; i++)
++ writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
++ return 0;
++}
++
++static int weim_parse_dt(struct platform_device *pdev)
++{
++ struct device_node *child;
++ int ret;
++
++ for_each_child_of_node(pdev->dev.of_node, child) {
++ if (!child->name)
++ continue;
++
++ ret = weim_timing_setup(pdev, child);
++ if (ret) {
++ dev_err(&pdev->dev, "%s set timing failed.\n",
++ child->full_name);
++ return ret;
++ }
++ }
++
++ ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
++ if (ret)
++ dev_err(&pdev->dev, "%s fail to create devices.\n",
++ pdev->dev.of_node->full_name);
++ return ret;
++}
++
++static int weim_probe(struct platform_device *pdev)
++{
++ struct imx_weim *weim;
++ struct resource *res;
++ int ret = -EINVAL;
++
++ weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
++ if (!weim) {
++ ret = -ENOMEM;
++ goto weim_err;
++ }
++ platform_set_drvdata(pdev, weim);
++
++ /* get the resource */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ weim->base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(weim->base)) {
++ ret = PTR_ERR(weim->base);
++ goto weim_err;
++ }
++
++ /* get the clock */
++ weim->clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(weim->clk))
++ goto weim_err;
++
++ ret = clk_prepare_enable(weim->clk);
++ if (ret)
++ goto weim_err;
++
++ /* parse the device node */
++ ret = weim_parse_dt(pdev);
++ if (ret) {
++ clk_disable_unprepare(weim->clk);
++ goto weim_err;
++ }
++
++ dev_info(&pdev->dev, "WEIM driver registered.\n");
++ return 0;
++
++weim_err:
++ return ret;
++}
++
++static struct platform_driver weim_driver = {
++ .driver = {
++ .name = "imx-weim",
++ .of_match_table = weim_id_table,
++ },
++ .probe = weim_probe,
++};
++
++module_platform_driver(weim_driver);
++MODULE_AUTHOR("Freescale Semiconductor Inc.");
++MODULE_DESCRIPTION("i.MX EIM Controller Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/bus/Kconfig linux-linaro-stable-mx6/drivers/bus/Kconfig
+--- linux-3.10.30.orig/drivers/bus/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/bus/Kconfig 2014-05-15 20:33:46.649932072 +0200
+@@ -4,6 +4,15 @@
+
+ menu "Bus devices"
+
++config IMX_WEIM
++ bool "Freescale EIM DRIVER"
++ depends on ARCH_MXC
++ help
++ Driver for i.MX6 WEIM controller.
++ The WEIM(Wireless External Interface Module) works like a bus.
++ You can attach many different devices on it, such as NOR, onenand.
++ But now, we only support the Parallel NOR.
++
+ config MVEBU_MBUS
+ bool
+ depends on PLAT_ORION
+@@ -26,4 +35,11 @@
+
+ help
+ Driver to enable OMAP interconnect error handling driver.
++
++config ARM_CCI
++ bool "ARM CCI driver support"
++ depends on ARM
++ help
++ Driver supporting the CCI cache coherent interconnect for ARM
++ platforms.
+ endmenu
+diff -Nur linux-3.10.30.orig/drivers/bus/Makefile linux-linaro-stable-mx6/drivers/bus/Makefile
+--- linux-3.10.30.orig/drivers/bus/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/bus/Makefile 2014-05-15 20:33:46.649932072 +0200
+@@ -2,8 +2,11 @@
+ # Makefile for the bus drivers.
+ #
+
++obj-$(CONFIG_IMX_WEIM) += imx-weim.o
+ obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
+ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
+
+ # Interconnect bus driver for OMAP SoCs.
+ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
++# CCI cache coherent interconnect for ARM platforms
++obj-$(CONFIG_ARM_CCI) += arm-cci.o
+diff -Nur linux-3.10.30.orig/drivers/char/fsl_otp.c linux-linaro-stable-mx6/drivers/char/fsl_otp.c
+--- linux-3.10.30.orig/drivers/char/fsl_otp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/char/fsl_otp.c 2014-05-15 20:33:46.661932159 +0200
+@@ -0,0 +1,299 @@
++/*
++ * Freescale On-Chip OTP driver
++ *
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/kobject.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/sysfs.h>
++
++#define HW_OCOTP_CTRL 0x00000000
++#define HW_OCOTP_CTRL_SET 0x00000004
++#define BP_OCOTP_CTRL_WR_UNLOCK 16
++#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
++#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00000400
++#define BM_OCOTP_CTRL_ERROR 0x00000200
++#define BM_OCOTP_CTRL_BUSY 0x00000100
++#define BP_OCOTP_CTRL_ADDR 0
++#define BM_OCOTP_CTRL_ADDR 0x0000007F
++
++#define HW_OCOTP_TIMING 0x00000010
++#define BP_OCOTP_TIMING_STROBE_READ 16
++#define BM_OCOTP_TIMING_STROBE_READ 0x003F0000
++#define BP_OCOTP_TIMING_RELAX 12
++#define BM_OCOTP_TIMING_RELAX 0x0000F000
++#define BP_OCOTP_TIMING_STROBE_PROG 0
++#define BM_OCOTP_TIMING_STROBE_PROG 0x00000FFF
++
++#define HW_OCOTP_DATA 0x00000020
++
++#define HW_OCOTP_CUST_N(n) (0x00000400 + (n) * 0x10)
++#define BF(value, field) (((value) << BP_##field) & BM_##field)
++
++#define DEF_RELAX 20 /* > 16.5ns */
++
++#define BANK(a, b, c, d, e, f, g, h) { \
++ "HW_OCOTP_"#a, "HW_OCOTP_"#b, "HW_OCOTP_"#c, "HW_OCOTP_"#d, \
++ "HW_OCOTP_"#e, "HW_OCOTP_"#f, "HW_OCOTP_"#g, "HW_OCOTP_"#h, \
++}
++
++static const char *imx6q_otp_desc[16][8] = {
++ BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6),
++ BANK(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, ANA2),
++ BANK(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7),
++ BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7),
++ BANK(RESP0, HSJC_RESP1, MAC0, MAC1, HDCP_KSV0, HDCP_KSV1, GP1, GP2),
++ BANK(DTCP_KEY0, DTCP_KEY1, DTCP_KEY2, DTCP_KEY3, DTCP_KEY4, MISC_CONF, FIELD_RETURN, SRK_REVOKE),
++ BANK(HDCP_KEY0, HDCP_KEY1, HDCP_KEY2, HDCP_KEY3, HDCP_KEY4, HDCP_KEY5, HDCP_KEY6, HDCP_KEY7),
++ BANK(HDCP_KEY8, HDCP_KEY9, HDCP_KEY10, HDCP_KEY11, HDCP_KEY12, HDCP_KEY13, HDCP_KEY14, HDCP_KEY15),
++ BANK(HDCP_KEY16, HDCP_KEY17, HDCP_KEY18, HDCP_KEY19, HDCP_KEY20, HDCP_KEY21, HDCP_KEY22, HDCP_KEY23),
++ BANK(HDCP_KEY24, HDCP_KEY25, HDCP_KEY26, HDCP_KEY27, HDCP_KEY28, HDCP_KEY29, HDCP_KEY30, HDCP_KEY31),
++ BANK(HDCP_KEY32, HDCP_KEY33, HDCP_KEY34, HDCP_KEY35, HDCP_KEY36, HDCP_KEY37, HDCP_KEY38, HDCP_KEY39),
++ BANK(HDCP_KEY40, HDCP_KEY41, HDCP_KEY42, HDCP_KEY43, HDCP_KEY44, HDCP_KEY45, HDCP_KEY46, HDCP_KEY47),
++ BANK(HDCP_KEY48, HDCP_KEY49, HDCP_KEY50, HDCP_KEY51, HDCP_KEY52, HDCP_KEY53, HDCP_KEY54, HDCP_KEY55),
++ BANK(HDCP_KEY56, HDCP_KEY57, HDCP_KEY58, HDCP_KEY59, HDCP_KEY60, HDCP_KEY61, HDCP_KEY62, HDCP_KEY63),
++ BANK(HDCP_KEY64, HDCP_KEY65, HDCP_KEY66, HDCP_KEY67, HDCP_KEY68, HDCP_KEY69, HDCP_KEY70, HDCP_KEY71),
++ BANK(CRC0, CRC1, CRC2, CRC3, CRC4, CRC5, CRC6, CRC7),
++};
++
++static DEFINE_MUTEX(otp_mutex);
++static void __iomem *otp_base;
++static struct clk *otp_clk;
++struct kobject *otp_kobj;
++struct kobj_attribute *otp_kattr;
++struct attribute_group *otp_attr_group;
++
++static void set_otp_timing(void)
++{
++ unsigned long clk_rate = 0;
++ unsigned long strobe_read, relex, strobe_prog;
++ u32 timing = 0;
++
++ clk_rate = clk_get_rate(otp_clk);
++
++ /* do optimization for too many zeros */
++ relex = clk_rate / (1000000000 / DEF_RELAX) - 1;
++ strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
++ strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
++
++ timing = BF(relex, OCOTP_TIMING_RELAX);
++ timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ);
++ timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG);
++
++ __raw_writel(timing, otp_base + HW_OCOTP_TIMING);
++}
++
++static int otp_wait_busy(u32 flags)
++{
++ int count;
++ u32 c;
++
++ for (count = 10000; count >= 0; count--) {
++ c = __raw_readl(otp_base + HW_OCOTP_CTRL);
++ if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags)))
++ break;
++ cpu_relax();
++ }
++
++ if (count < 0)
++ return -ETIMEDOUT;
++
++ return 0;
++}
++
++static ssize_t fsl_otp_show(struct kobject *kobj, struct kobj_attribute *attr,
++ char *buf)
++{
++ unsigned int index = attr - otp_kattr;
++ u32 value = 0;
++ int ret;
++
++ ret = clk_prepare_enable(otp_clk);
++ if (ret)
++ return 0;
++
++ mutex_lock(&otp_mutex);
++
++ set_otp_timing();
++ ret = otp_wait_busy(0);
++ if (ret)
++ goto out;
++
++ value = __raw_readl(otp_base + HW_OCOTP_CUST_N(index));
++
++out:
++ mutex_unlock(&otp_mutex);
++ clk_disable_unprepare(otp_clk);
++ return ret ? 0 : sprintf(buf, "0x%x\n", value);
++}
++
++static int otp_write_bits(int addr, u32 data, u32 magic)
++{
++ u32 c; /* for control register */
++
++ /* init the control register */
++ c = __raw_readl(otp_base + HW_OCOTP_CTRL);
++ c &= ~BM_OCOTP_CTRL_ADDR;
++ c |= BF(addr, OCOTP_CTRL_ADDR);
++ c |= BF(magic, OCOTP_CTRL_WR_UNLOCK);
++ __raw_writel(c, otp_base + HW_OCOTP_CTRL);
++
++ /* init the data register */
++ __raw_writel(data, otp_base + HW_OCOTP_DATA);
++ otp_wait_busy(0);
++
++ mdelay(2); /* Write Postamble */
++
++ return 0;
++}
++
++static ssize_t fsl_otp_store(struct kobject *kobj, struct kobj_attribute *attr,
++ const char *buf, size_t count)
++{
++ unsigned int index = attr - otp_kattr;
++ u32 value;
++ int ret;
++
++ sscanf(buf, "0x%x", &value);
++
++ ret = clk_prepare_enable(otp_clk);
++ if (ret)
++ return 0;
++
++ mutex_lock(&otp_mutex);
++
++ set_otp_timing();
++ ret = otp_wait_busy(0);
++ if (ret)
++ goto out;
++
++ otp_write_bits(index, value, 0x3e77);
++
++ /* Reload all the shadow registers */
++ __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS,
++ otp_base + HW_OCOTP_CTRL_SET);
++ udelay(1);
++ otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS);
++
++out:
++ mutex_unlock(&otp_mutex);
++ clk_disable_unprepare(otp_clk);
++ return ret ? 0 : count;
++}
++
++static int fsl_otp_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ struct attribute **attrs;
++ const char **desc;
++ int i, num;
++ int ret;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ otp_base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(otp_base)) {
++ ret = PTR_ERR(otp_base);
++ dev_err(&pdev->dev, "failed to ioremap resource: %d\n", ret);
++ return ret;
++ }
++
++ otp_clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(otp_clk)) {
++ ret = PTR_ERR(otp_clk);
++ dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
++ return ret;
++ }
++
++ desc = (const char **) imx6q_otp_desc;
++ num = sizeof(imx6q_otp_desc) / sizeof(void *);
++
++ /* The last one is NULL, which is used to detect the end */
++ attrs = devm_kzalloc(&pdev->dev, (num + 1) * sizeof(*attrs),
++ GFP_KERNEL);
++ otp_kattr = devm_kzalloc(&pdev->dev, num * sizeof(*otp_kattr),
++ GFP_KERNEL);
++ otp_attr_group = devm_kzalloc(&pdev->dev, sizeof(*otp_attr_group),
++ GFP_KERNEL);
++ if (!attrs || !otp_kattr || !otp_attr_group)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++) {
++ sysfs_attr_init(&otp_kattr[i].attr);
++ otp_kattr[i].attr.name = desc[i];
++ otp_kattr[i].attr.mode = 0600;
++ otp_kattr[i].show = fsl_otp_show;
++ otp_kattr[i].store = fsl_otp_store;
++ attrs[i] = &otp_kattr[i].attr;
++ }
++ otp_attr_group->attrs = attrs;
++
++ otp_kobj = kobject_create_and_add("fsl_otp", NULL);
++ if (!otp_kobj) {
++ dev_err(&pdev->dev, "failed to add kobject\n");
++ return -ENOMEM;
++ }
++
++ ret = sysfs_create_group(otp_kobj, otp_attr_group);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to create sysfs group: %d\n", ret);
++ kobject_put(otp_kobj);
++ return ret;
++ }
++
++ mutex_init(&otp_mutex);
++
++ return 0;
++}
++
++static int fsl_otp_remove(struct platform_device *pdev)
++{
++ sysfs_remove_group(otp_kobj, otp_attr_group);
++ kobject_put(otp_kobj);
++
++ return 0;
++}
++
++static const struct of_device_id fsl_otp_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ocotp", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, fsl_otp_dt_ids);
++
++static struct platform_driver fsl_otp_driver = {
++ .driver = {
++ .name = "imx-ocotp",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_otp_dt_ids,
++ },
++ .probe = fsl_otp_probe,
++ .remove = fsl_otp_remove,
++};
++module_platform_driver(fsl_otp_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Huang Shijie <b32955@freescale.com>");
++MODULE_DESCRIPTION("Freescale i.MX OCOTP driver");
+diff -Nur linux-3.10.30.orig/drivers/char/Kconfig linux-linaro-stable-mx6/drivers/char/Kconfig
+--- linux-3.10.30.orig/drivers/char/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/char/Kconfig 2014-05-15 20:33:46.653932101 +0200
+@@ -94,6 +94,21 @@
+
+ If unsure, say N.
+
++config FSL_OTP
++ tristate "Freescale On-Chip OTP Memory Support"
++ depends on HAS_IOMEM && OF
++ help
++ If you say Y here, you will get support for a character device
++ interface into the One Time Programmable memory pages that are
++ stored on the some Freescale i.MX processors. This will not get
++ you access to the secure memory pages however. You will need to
++ write your own secure code and reader for that.
++
++ To compile this driver as a module, choose M here: the module
++ will be called fsl_otp.
++
++ If unsure, it is safe to say Y.
++
+ config PRINTER
+ tristate "Parallel printer support"
+ depends on PARPORT
+diff -Nur linux-3.10.30.orig/drivers/char/Makefile linux-linaro-stable-mx6/drivers/char/Makefile
+--- linux-3.10.30.orig/drivers/char/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/char/Makefile 2014-05-15 20:33:46.653932101 +0200
+@@ -17,6 +17,7 @@
+ obj-$(CONFIG_IBM_BSR) += bsr.o
+ obj-$(CONFIG_SGI_MBCS) += mbcs.o
+ obj-$(CONFIG_BFIN_OTP) += bfin-otp.o
++obj-$(CONFIG_FSL_OTP) += fsl_otp.o
+
+ obj-$(CONFIG_PRINTER) += lp.o
+
+diff -Nur linux-3.10.30.orig/drivers/clk/clk-divider.c linux-linaro-stable-mx6/drivers/clk/clk-divider.c
+--- linux-3.10.30.orig/drivers/clk/clk-divider.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/clk/clk-divider.c 2014-05-15 20:33:46.721932591 +0200
+@@ -150,6 +150,7 @@
+ struct clk_divider *divider = to_clk_divider(hw);
+ int i, bestdiv = 0;
+ unsigned long parent_rate, best = 0, now, maxdiv;
++ unsigned long parent_rate_saved = *best_parent_rate;
+
+ if (!rate)
+ rate = 1;
+@@ -173,6 +174,15 @@
+ for (i = 1; i <= maxdiv; i++) {
+ if (!_is_valid_div(divider, i))
+ continue;
++ if (rate * i == parent_rate_saved) {
++ /*
++ * It's the most ideal case if the requested rate can be
++ * divided from parent clock without needing to change
++ * parent rate, so return the divider immediately.
++ */
++ *best_parent_rate = parent_rate_saved;
++ return i;
++ }
+ parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
+ MULT_ROUND_UP(rate, i));
+ now = parent_rate / i;
+diff -Nur linux-3.10.30.orig/drivers/clk/Kconfig linux-linaro-stable-mx6/drivers/clk/Kconfig
+--- linux-3.10.30.orig/drivers/clk/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/clk/Kconfig 2014-05-15 20:33:46.713932534 +0200
+@@ -42,7 +42,7 @@
+
+ config COMMON_CLK_VERSATILE
+ bool "Clock driver for ARM Reference designs"
+- depends on ARCH_INTEGRATOR || ARCH_REALVIEW || ARCH_VEXPRESS
++ depends on ARCH_INTEGRATOR || ARCH_REALVIEW || ARCH_VEXPRESS || ARM64
+ ---help---
+ Supports clocking on ARM Reference designs:
+ - Integrator/AP and Integrator/CP
+diff -Nur linux-3.10.30.orig/drivers/clk/versatile/clk-vexpress-osc.c linux-linaro-stable-mx6/drivers/clk/versatile/clk-vexpress-osc.c
+--- linux-3.10.30.orig/drivers/clk/versatile/clk-vexpress-osc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/clk/versatile/clk-vexpress-osc.c 2014-05-15 20:33:46.757932851 +0200
+@@ -107,7 +107,7 @@
+ osc->func = vexpress_config_func_get_by_node(node);
+ if (!osc->func) {
+ pr_err("Failed to obtain config func for node '%s'!\n",
+- node->name);
++ node->full_name);
+ goto error;
+ }
+
+@@ -119,7 +119,7 @@
+
+ of_property_read_string(node, "clock-output-names", &init.name);
+ if (!init.name)
+- init.name = node->name;
++ init.name = node->full_name;
+
+ init.ops = &vexpress_osc_ops;
+ init.flags = CLK_IS_ROOT;
+diff -Nur linux-3.10.30.orig/drivers/clk/versatile/clk-vexpress-spc.c linux-linaro-stable-mx6/drivers/clk/versatile/clk-vexpress-spc.c
+--- linux-3.10.30.orig/drivers/clk/versatile/clk-vexpress-spc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/clk/versatile/clk-vexpress-spc.c 2014-05-15 20:33:46.757932851 +0200
+@@ -0,0 +1,131 @@
++/*
++ * Copyright (C) 2012 ARM Limited
++ * Copyright (C) 2012 Linaro
++ *
++ * Author: Viresh Kumar <viresh.kumar@linaro.org>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++/* SPC clock programming interface for Vexpress cpus */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/vexpress.h>
++
++struct clk_spc {
++ struct clk_hw hw;
++ spinlock_t *lock;
++ int cluster;
++};
++
++#define to_clk_spc(spc) container_of(spc, struct clk_spc, hw)
++
++static unsigned long spc_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct clk_spc *spc = to_clk_spc(hw);
++ u32 freq;
++
++ if (vexpress_spc_get_performance(spc->cluster, &freq)) {
++ return -EIO;
++ pr_err("%s: Failed", __func__);
++ }
++
++ return freq * 1000;
++}
++
++static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
++ unsigned long *parent_rate)
++{
++ return drate;
++}
++
++static int spc_set_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long parent_rate)
++{
++ struct clk_spc *spc = to_clk_spc(hw);
++
++ return vexpress_spc_set_performance(spc->cluster, rate / 1000);
++}
++
++static struct clk_ops clk_spc_ops = {
++ .recalc_rate = spc_recalc_rate,
++ .round_rate = spc_round_rate,
++ .set_rate = spc_set_rate,
++};
++
++struct clk *vexpress_clk_register_spc(const char *name, int cluster_id)
++{
++ struct clk_init_data init;
++ struct clk_spc *spc;
++ struct clk *clk;
++
++ if (!name) {
++ pr_err("Invalid name passed");
++ return ERR_PTR(-EINVAL);
++ }
++
++ spc = kzalloc(sizeof(*spc), GFP_KERNEL);
++ if (!spc) {
++ pr_err("could not allocate spc clk\n");
++ return ERR_PTR(-ENOMEM);
++ }
++
++ spc->hw.init = &init;
++ spc->cluster = cluster_id;
++
++ init.name = name;
++ init.ops = &clk_spc_ops;
++ init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
++ init.num_parents = 0;
++
++ clk = clk_register(NULL, &spc->hw);
++ if (!IS_ERR_OR_NULL(clk))
++ return clk;
++
++ pr_err("clk register failed\n");
++ kfree(spc);
++
++ return NULL;
++}
++
++#if defined(CONFIG_OF)
++void __init vexpress_clk_of_register_spc(void)
++{
++ char name[14] = "cpu-cluster.X";
++ struct device_node *node = NULL;
++ struct clk *clk;
++ const u32 *val;
++ int cluster_id = 0, len;
++
++ if (!of_find_compatible_node(NULL, NULL, "arm,vexpress-spc")) {
++ pr_debug("%s: No SPC found, Exiting!!\n", __func__);
++ return;
++ }
++
++ while ((node = of_find_node_by_name(node, "cluster"))) {
++ val = of_get_property(node, "reg", &len);
++ if (val && len == 4)
++ cluster_id = be32_to_cpup(val);
++
++ name[12] = cluster_id + '0';
++ clk = vexpress_clk_register_spc(name, cluster_id);
++ if (IS_ERR(clk))
++ return;
++
++ pr_debug("Registered clock '%s'\n", name);
++ clk_register_clkdev(clk, NULL, name);
++ }
++}
++CLK_OF_DECLARE(spc, "arm,vexpress-spc", vexpress_clk_of_register_spc);
++#endif
+diff -Nur linux-3.10.30.orig/drivers/clk/versatile/Makefile linux-linaro-stable-mx6/drivers/clk/versatile/Makefile
+--- linux-3.10.30.orig/drivers/clk/versatile/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/clk/versatile/Makefile 2014-05-15 20:33:46.757932851 +0200
+@@ -4,4 +4,4 @@
+ obj-$(CONFIG_INTEGRATOR_IMPD1) += clk-impd1.o
+ obj-$(CONFIG_ARCH_REALVIEW) += clk-realview.o
+ obj-$(CONFIG_ARCH_VEXPRESS) += clk-vexpress.o clk-sp810.o
+-obj-$(CONFIG_VEXPRESS_CONFIG) += clk-vexpress-osc.o
++obj-$(CONFIG_VEXPRESS_CONFIG) += clk-vexpress-osc.o clk-vexpress-spc.o
+diff -Nur linux-3.10.30.orig/drivers/clocksource/Kconfig linux-linaro-stable-mx6/drivers/clocksource/Kconfig
+--- linux-3.10.30.orig/drivers/clocksource/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/clocksource/Kconfig 2014-05-15 20:33:46.781933025 +0200
+@@ -85,3 +85,8 @@
+ Samsung S3C, S5P and Exynos SoCs, replacing an earlier driver
+ for all devicetree enabled platforms. This driver will be
+ needed only on systems that do not have the Exynos MCT available.
++
++config VF_PIT_TIMER
++ bool
++ help
++ Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
+diff -Nur linux-3.10.30.orig/drivers/clocksource/Makefile linux-linaro-stable-mx6/drivers/clocksource/Makefile
+--- linux-3.10.30.orig/drivers/clocksource/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/clocksource/Makefile 2014-05-15 20:33:46.781933025 +0200
+@@ -26,6 +26,7 @@
+ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o
+ obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
+ obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
++obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
+
+ obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
+ obj-$(CONFIG_CLKSRC_METAG_GENERIC) += metag_generic.o
+diff -Nur linux-3.10.30.orig/drivers/clocksource/vf_pit_timer.c linux-linaro-stable-mx6/drivers/clocksource/vf_pit_timer.c
+--- linux-3.10.30.orig/drivers/clocksource/vf_pit_timer.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/clocksource/vf_pit_timer.c 2014-05-15 20:33:46.805933197 +0200
+@@ -0,0 +1,194 @@
++/*
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ */
++
++#include <linux/interrupt.h>
++#include <linux/clockchips.h>
++#include <linux/clk.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <asm/sched_clock.h>
++
++/*
++ * Each pit takes 0x10 Bytes register space
++ */
++#define PITMCR 0x00
++#define PIT0_OFFSET 0x100
++#define PITn_OFFSET(n) (PIT0_OFFSET + 0x10 * (n))
++#define PITLDVAL 0x00
++#define PITCVAL 0x04
++#define PITTCTRL 0x08
++#define PITTFLG 0x0c
++
++#define PITMCR_MDIS (0x1 << 1)
++
++#define PITTCTRL_TEN (0x1 << 0)
++#define PITTCTRL_TIE (0x1 << 1)
++#define PITCTRL_CHN (0x1 << 2)
++
++#define PITTFLG_TIF 0x1
++
++static void __iomem *clksrc_base;
++static void __iomem *clkevt_base;
++static unsigned long cycle_per_jiffy;
++
++static inline void pit_timer_enable(void)
++{
++ __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
++}
++
++static inline void pit_timer_disable(void)
++{
++ __raw_writel(0, clkevt_base + PITTCTRL);
++}
++
++static inline void pit_irq_acknowledge(void)
++{
++ __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
++}
++
++static unsigned int pit_read_sched_clock(void)
++{
++ return __raw_readl(clksrc_base + PITCVAL);
++}
++
++static int __init pit_clocksource_init(unsigned long rate)
++{
++ /* set the max load value and start the clock source counter */
++ __raw_writel(0, clksrc_base + PITTCTRL);
++ __raw_writel(~0UL, clksrc_base + PITLDVAL);
++ __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
++
++ setup_sched_clock(pit_read_sched_clock, 32, rate);
++ return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
++ 300, 32, clocksource_mmio_readl_down);
++}
++
++static int pit_set_next_event(unsigned long delta,
++ struct clock_event_device *unused)
++{
++ /*
++ * set a new value to PITLDVAL register will not restart the timer,
++ * to abort the current cycle and start a timer period with the new
++ * value, the timer must be disabled and enabled again.
++ * and the PITLAVAL should be set to delta minus one according to pit
++ * hardware requirement.
++ */
++ pit_timer_disable();
++ __raw_writel(delta - 1, clkevt_base + PITLDVAL);
++ pit_timer_enable();
++
++ return 0;
++}
++
++static void pit_set_mode(enum clock_event_mode mode,
++ struct clock_event_device *evt)
++{
++ switch (mode) {
++ case CLOCK_EVT_MODE_PERIODIC:
++ pit_set_next_event(cycle_per_jiffy, evt);
++ break;
++ default:
++ break;
++ }
++}
++
++static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
++{
++ struct clock_event_device *evt = dev_id;
++
++ pit_irq_acknowledge();
++
++ /*
++ * pit hardware doesn't support oneshot, it will generate an interrupt
++ * and reload the counter value from PITLDVAL when PITCVAL reach zero,
++ * and start the counter again. So software need to disable the timer
++ * to stop the counter loop in ONESHOT mode.
++ */
++ if (likely(evt->mode == CLOCK_EVT_MODE_ONESHOT))
++ pit_timer_disable();
++
++ evt->event_handler(evt);
++
++ return IRQ_HANDLED;
++}
++
++static struct clock_event_device clockevent_pit = {
++ .name = "VF pit timer",
++ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
++ .set_mode = pit_set_mode,
++ .set_next_event = pit_set_next_event,
++ .rating = 300,
++};
++
++static struct irqaction pit_timer_irq = {
++ .name = "VF pit timer",
++ .flags = IRQF_TIMER | IRQF_IRQPOLL,
++ .handler = pit_timer_interrupt,
++ .dev_id = &clockevent_pit,
++};
++
++static int __init pit_clockevent_init(unsigned long rate, int irq)
++{
++ __raw_writel(0, clkevt_base + PITTCTRL);
++ __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
++
++ BUG_ON(setup_irq(irq, &pit_timer_irq));
++
++ clockevent_pit.cpumask = cpumask_of(0);
++ clockevent_pit.irq = irq;
++ /*
++ * The value for the LDVAL register trigger is calculated as:
++ * LDVAL trigger = (period / clock period) - 1
++ * The pit is a 32-bit down count timer, when the conter value
++ * reaches 0, it will generate an interrupt, thus the minimal
++ * LDVAL trigger value is 1. And then the min_delta is
++ * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
++ */
++ clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
++
++ return 0;
++}
++
++static void __init pit_timer_init(struct device_node *np)
++{
++ struct clk *pit_clk;
++ void __iomem *timer_base;
++ unsigned long clk_rate;
++ int irq;
++
++ timer_base = of_iomap(np, 0);
++ BUG_ON(!timer_base);
++
++ /*
++ * PIT0 and PIT1 can be chained to build a 64-bit timer,
++ * so choose PIT2 as clocksource, PIT3 as clockevent device,
++ * and leave PIT0 and PIT1 unused for anyone else who needs them.
++ */
++ clksrc_base = timer_base + PITn_OFFSET(2);
++ clkevt_base = timer_base + PITn_OFFSET(3);
++
++ irq = irq_of_parse_and_map(np, 0);
++ BUG_ON(irq <= 0);
++
++ pit_clk = of_clk_get(np, 0);
++ BUG_ON(IS_ERR(pit_clk));
++
++ BUG_ON(clk_prepare_enable(pit_clk));
++
++ clk_rate = clk_get_rate(pit_clk);
++ cycle_per_jiffy = clk_rate / (HZ);
++
++ /* enable the pit module */
++ __raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
++
++ BUG_ON(pit_clocksource_init(clk_rate));
++
++ pit_clockevent_init(clk_rate, irq);
++}
++CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/arm_big_little.c linux-linaro-stable-mx6/drivers/cpufreq/arm_big_little.c
+--- linux-3.10.30.orig/drivers/cpufreq/arm_big_little.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/arm_big_little.c 2014-05-15 20:33:46.805933197 +0200
+@@ -24,27 +24,148 @@
+ #include <linux/cpufreq.h>
+ #include <linux/cpumask.h>
+ #include <linux/export.h>
++#include <linux/mutex.h>
+ #include <linux/of_platform.h>
+ #include <linux/opp.h>
+ #include <linux/slab.h>
+ #include <linux/topology.h>
+ #include <linux/types.h>
++#include <asm/bL_switcher.h>
+
+ #include "arm_big_little.h"
+
+-/* Currently we support only two clusters */
+-#define MAX_CLUSTERS 2
++#ifdef CONFIG_BL_SWITCHER
++bool bL_switching_enabled;
++#endif
++
++#define ACTUAL_FREQ(cluster, freq) ((cluster == A7_CLUSTER) ? freq << 1 : freq)
++#define VIRT_FREQ(cluster, freq) ((cluster == A7_CLUSTER) ? freq >> 1 : freq)
+
+ static struct cpufreq_arm_bL_ops *arm_bL_ops;
+ static struct clk *clk[MAX_CLUSTERS];
+-static struct cpufreq_frequency_table *freq_table[MAX_CLUSTERS];
+-static atomic_t cluster_usage[MAX_CLUSTERS] = {ATOMIC_INIT(0), ATOMIC_INIT(0)};
++static struct cpufreq_frequency_table *freq_table[MAX_CLUSTERS + 1];
++static atomic_t cluster_usage[MAX_CLUSTERS + 1] = {ATOMIC_INIT(0),
++ ATOMIC_INIT(0)};
++
++static unsigned int clk_big_min; /* (Big) clock frequencies */
++static unsigned int clk_little_max; /* Maximum clock frequency (Little) */
++
++static DEFINE_PER_CPU(unsigned int, physical_cluster);
++static DEFINE_PER_CPU(unsigned int, cpu_last_req_freq);
++
++static struct mutex cluster_lock[MAX_CLUSTERS];
++
++static unsigned int find_cluster_maxfreq(int cluster)
++{
++ int j;
++ u32 max_freq = 0, cpu_freq;
++
++ for_each_online_cpu(j) {
++ cpu_freq = per_cpu(cpu_last_req_freq, j);
++
++ if ((cluster == per_cpu(physical_cluster, j)) &&
++ (max_freq < cpu_freq))
++ max_freq = cpu_freq;
++ }
++
++ pr_debug("%s: cluster: %d, max freq: %d\n", __func__, cluster,
++ max_freq);
++
++ return max_freq;
++}
++
++static unsigned int clk_get_cpu_rate(unsigned int cpu)
++{
++ u32 cur_cluster = per_cpu(physical_cluster, cpu);
++ u32 rate = clk_get_rate(clk[cur_cluster]) / 1000;
++
++ /* For switcher we use virtual A15 clock rates */
++ if (is_bL_switching_enabled())
++ rate = VIRT_FREQ(cur_cluster, rate);
++
++ pr_debug("%s: cpu: %d, cluster: %d, freq: %u\n", __func__, cpu,
++ cur_cluster, rate);
++
++ return rate;
++}
+
+-static unsigned int bL_cpufreq_get(unsigned int cpu)
++static unsigned int bL_cpufreq_get_rate(unsigned int cpu)
+ {
+- u32 cur_cluster = cpu_to_cluster(cpu);
++ if (is_bL_switching_enabled()) {
++ pr_debug("%s: freq: %d\n", __func__, per_cpu(cpu_last_req_freq,
++ cpu));
++
++ return per_cpu(cpu_last_req_freq, cpu);
++ } else {
++ return clk_get_cpu_rate(cpu);
++ }
++}
++
++static unsigned int
++bL_cpufreq_set_rate(u32 cpu, u32 old_cluster, u32 new_cluster, u32 rate)
++{
++ u32 new_rate, prev_rate;
++ int ret;
++ bool bLs = is_bL_switching_enabled();
++
++ mutex_lock(&cluster_lock[new_cluster]);
++
++ if (bLs) {
++ prev_rate = per_cpu(cpu_last_req_freq, cpu);
++ per_cpu(cpu_last_req_freq, cpu) = rate;
++ per_cpu(physical_cluster, cpu) = new_cluster;
++
++ new_rate = find_cluster_maxfreq(new_cluster);
++ new_rate = ACTUAL_FREQ(new_cluster, new_rate);
++ } else {
++ new_rate = rate;
++ }
++
++ pr_debug("%s: cpu: %d, old cluster: %d, new cluster: %d, freq: %d\n",
++ __func__, cpu, old_cluster, new_cluster, new_rate);
++
++ ret = clk_set_rate(clk[new_cluster], new_rate * 1000);
++ if (WARN_ON(ret)) {
++ pr_err("clk_set_rate failed: %d, new cluster: %d\n", ret,
++ new_cluster);
++ if (bLs) {
++ per_cpu(cpu_last_req_freq, cpu) = prev_rate;
++ per_cpu(physical_cluster, cpu) = old_cluster;
++ }
++
++ mutex_unlock(&cluster_lock[new_cluster]);
++
++ return ret;
++ }
++
++ mutex_unlock(&cluster_lock[new_cluster]);
+
+- return clk_get_rate(clk[cur_cluster]) / 1000;
++ /* Recalc freq for old cluster when switching clusters */
++ if (old_cluster != new_cluster) {
++ pr_debug("%s: cpu: %d, old cluster: %d, new cluster: %d\n",
++ __func__, cpu, old_cluster, new_cluster);
++
++ /* Switch cluster */
++ bL_switch_request(cpu, new_cluster);
++
++ mutex_lock(&cluster_lock[old_cluster]);
++
++ /* Set freq of old cluster if there are cpus left on it */
++ new_rate = find_cluster_maxfreq(old_cluster);
++ new_rate = ACTUAL_FREQ(old_cluster, new_rate);
++
++ if (new_rate) {
++ pr_debug("%s: Updating rate of old cluster: %d, to freq: %d\n",
++ __func__, old_cluster, new_rate);
++
++ if (clk_set_rate(clk[old_cluster], new_rate * 1000))
++ pr_err("%s: clk_set_rate failed: %d, old cluster: %d\n",
++ __func__, ret, old_cluster);
++ }
++ mutex_unlock(&cluster_lock[old_cluster]);
++ }
++
++ return 0;
+ }
+
+ /* Validate policy frequency range */
+@@ -60,12 +181,14 @@
+ unsigned int target_freq, unsigned int relation)
+ {
+ struct cpufreq_freqs freqs;
+- u32 cpu = policy->cpu, freq_tab_idx, cur_cluster;
++ u32 cpu = policy->cpu, freq_tab_idx, cur_cluster, new_cluster,
++ actual_cluster;
+ int ret = 0;
+
+- cur_cluster = cpu_to_cluster(policy->cpu);
++ cur_cluster = cpu_to_cluster(cpu);
++ new_cluster = actual_cluster = per_cpu(physical_cluster, cpu);
+
+- freqs.old = bL_cpufreq_get(policy->cpu);
++ freqs.old = bL_cpufreq_get_rate(cpu);
+
+ /* Determine valid target frequency using freq_table */
+ cpufreq_frequency_table_target(policy, freq_table[cur_cluster],
+@@ -79,13 +202,21 @@
+ if (freqs.old == freqs.new)
+ return 0;
+
++ if (is_bL_switching_enabled()) {
++ if ((actual_cluster == A15_CLUSTER) &&
++ (freqs.new < clk_big_min)) {
++ new_cluster = A7_CLUSTER;
++ } else if ((actual_cluster == A7_CLUSTER) &&
++ (freqs.new > clk_little_max)) {
++ new_cluster = A15_CLUSTER;
++ }
++ }
++
+ cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
+
+- ret = clk_set_rate(clk[cur_cluster], freqs.new * 1000);
+- if (ret) {
+- pr_err("clk_set_rate failed: %d\n", ret);
++ ret = bL_cpufreq_set_rate(cpu, actual_cluster, new_cluster, freqs.new);
++ if (ret)
+ return ret;
+- }
+
+ policy->cur = freqs.new;
+
+@@ -94,7 +225,73 @@
+ return ret;
+ }
+
+-static void put_cluster_clk_and_freq_table(struct device *cpu_dev)
++static inline u32 get_table_count(struct cpufreq_frequency_table *table)
++{
++ int count;
++
++ for (count = 0; table[count].frequency != CPUFREQ_TABLE_END; count++)
++ ;
++
++ return count;
++}
++
++/* get the minimum frequency in the cpufreq_frequency_table */
++static inline u32 get_table_min(struct cpufreq_frequency_table *table)
++{
++ int i;
++ uint32_t min_freq = ~0;
++ for (i = 0; (table[i].frequency != CPUFREQ_TABLE_END); i++)
++ if (table[i].frequency < min_freq)
++ min_freq = table[i].frequency;
++ return min_freq;
++}
++
++/* get the maximum frequency in the cpufreq_frequency_table */
++static inline u32 get_table_max(struct cpufreq_frequency_table *table)
++{
++ int i;
++ uint32_t max_freq = 0;
++ for (i = 0; (table[i].frequency != CPUFREQ_TABLE_END); i++)
++ if (table[i].frequency > max_freq)
++ max_freq = table[i].frequency;
++ return max_freq;
++}
++
++static int merge_cluster_tables(void)
++{
++ int i, j, k = 0, count = 1;
++ struct cpufreq_frequency_table *table;
++
++ for (i = 0; i < MAX_CLUSTERS; i++)
++ count += get_table_count(freq_table[i]);
++
++ table = kzalloc(sizeof(*table) * count, GFP_KERNEL);
++ if (!table)
++ return -ENOMEM;
++
++ freq_table[MAX_CLUSTERS] = table;
++
++ /* Add in reverse order to get freqs in increasing order */
++ for (i = MAX_CLUSTERS - 1; i >= 0; i--) {
++ for (j = 0; freq_table[i][j].frequency != CPUFREQ_TABLE_END;
++ j++) {
++ table[k].frequency = VIRT_FREQ(i,
++ freq_table[i][j].frequency);
++ pr_debug("%s: index: %d, freq: %d\n", __func__, k,
++ table[k].frequency);
++ k++;
++ }
++ }
++
++ table[k].index = k;
++ table[k].frequency = CPUFREQ_TABLE_END;
++
++ pr_debug("%s: End, table: %p, count: %d\n", __func__, table, k);
++
++ return 0;
++}
++
++static void _put_cluster_clk_and_freq_table(struct device *cpu_dev)
+ {
+ u32 cluster = cpu_to_cluster(cpu_dev->id);
+
+@@ -105,10 +302,35 @@
+ }
+ }
+
+-static int get_cluster_clk_and_freq_table(struct device *cpu_dev)
++static void put_cluster_clk_and_freq_table(struct device *cpu_dev)
++{
++ u32 cluster = cpu_to_cluster(cpu_dev->id);
++ int i;
++
++ if (cluster < MAX_CLUSTERS)
++ return _put_cluster_clk_and_freq_table(cpu_dev);
++
++ if (atomic_dec_return(&cluster_usage[MAX_CLUSTERS]))
++ return;
++
++ for (i = 0; i < MAX_CLUSTERS; i++) {
++ struct device *cdev = get_cpu_device(i);
++ if (!cdev) {
++ pr_err("%s: failed to get cpu%d device\n", __func__, i);
++ return;
++ }
++
++ _put_cluster_clk_and_freq_table(cdev);
++ }
++
++ /* free virtual table */
++ kfree(freq_table[MAX_CLUSTERS]);
++}
++
++static int _get_cluster_clk_and_freq_table(struct device *cpu_dev)
+ {
+ u32 cluster = cpu_to_cluster(cpu_dev->id);
+- char name[14] = "cpu-cluster.";
++ char name[14] = "cpu-cluster.X";
+ int ret;
+
+ if (atomic_inc_return(&cluster_usage[cluster]) != 1)
+@@ -149,6 +371,62 @@
+ return ret;
+ }
+
++static int get_cluster_clk_and_freq_table(struct device *cpu_dev)
++{
++ u32 cluster = cpu_to_cluster(cpu_dev->id);
++ int i, ret;
++
++ if (cluster < MAX_CLUSTERS)
++ return _get_cluster_clk_and_freq_table(cpu_dev);
++
++ if (atomic_inc_return(&cluster_usage[MAX_CLUSTERS]) != 1)
++ return 0;
++
++ /*
++ * Get data for all clusters and fill virtual cluster with a merge of
++ * both
++ */
++ for (i = 0; i < MAX_CLUSTERS; i++) {
++ struct device *cdev = get_cpu_device(i);
++ if (!cdev) {
++ pr_err("%s: failed to get cpu%d device\n", __func__, i);
++ return -ENODEV;
++ }
++
++ ret = _get_cluster_clk_and_freq_table(cdev);
++ if (ret)
++ goto put_clusters;
++ }
++
++ ret = merge_cluster_tables();
++ if (ret)
++ goto put_clusters;
++
++ /* Assuming 2 cluster, set clk_big_min and clk_little_max */
++ clk_big_min = get_table_min(freq_table[0]);
++ clk_little_max = VIRT_FREQ(1, get_table_max(freq_table[1]));
++
++ pr_debug("%s: cluster: %d, clk_big_min: %d, clk_little_max: %d\n",
++ __func__, cluster, clk_big_min, clk_little_max);
++
++ return 0;
++
++put_clusters:
++ while (i--) {
++ struct device *cdev = get_cpu_device(i);
++ if (!cdev) {
++ pr_err("%s: failed to get cpu%d device\n", __func__, i);
++ return -ENODEV;
++ }
++
++ _put_cluster_clk_and_freq_table(cdev);
++ }
++
++ atomic_dec(&cluster_usage[MAX_CLUSTERS]);
++
++ return ret;
++}
++
+ /* Per-CPU initialization */
+ static int bL_cpufreq_init(struct cpufreq_policy *policy)
+ {
+@@ -177,37 +455,30 @@
+
+ cpufreq_frequency_table_get_attr(freq_table[cur_cluster], policy->cpu);
+
++ if (cur_cluster < MAX_CLUSTERS) {
++ cpumask_copy(policy->cpus, topology_core_cpumask(policy->cpu));
++
++ per_cpu(physical_cluster, policy->cpu) = cur_cluster;
++ } else {
++ /* Assumption: during init, we are always running on A15 */
++ per_cpu(physical_cluster, policy->cpu) = A15_CLUSTER;
++ }
++
+ if (arm_bL_ops->get_transition_latency)
+ policy->cpuinfo.transition_latency =
+ arm_bL_ops->get_transition_latency(cpu_dev);
+ else
+ policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
+
+- policy->cur = bL_cpufreq_get(policy->cpu);
++ policy->cur = clk_get_cpu_rate(policy->cpu);
+
+- cpumask_copy(policy->cpus, topology_core_cpumask(policy->cpu));
++ if (is_bL_switching_enabled())
++ per_cpu(cpu_last_req_freq, policy->cpu) = policy->cur;
+
+ dev_info(cpu_dev, "%s: CPU %d initialized\n", __func__, policy->cpu);
+ return 0;
+ }
+
+-static int bL_cpufreq_exit(struct cpufreq_policy *policy)
+-{
+- struct device *cpu_dev;
+-
+- cpu_dev = get_cpu_device(policy->cpu);
+- if (!cpu_dev) {
+- pr_err("%s: failed to get cpu%d device\n", __func__,
+- policy->cpu);
+- return -ENODEV;
+- }
+-
+- put_cluster_clk_and_freq_table(cpu_dev);
+- dev_dbg(cpu_dev, "%s: Exited, cpu: %d\n", __func__, policy->cpu);
+-
+- return 0;
+-}
+-
+ /* Export freq_table to sysfs */
+ static struct freq_attr *bL_cpufreq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+@@ -219,16 +490,47 @@
+ .flags = CPUFREQ_STICKY,
+ .verify = bL_cpufreq_verify_policy,
+ .target = bL_cpufreq_set_target,
+- .get = bL_cpufreq_get,
++ .get = bL_cpufreq_get_rate,
+ .init = bL_cpufreq_init,
+- .exit = bL_cpufreq_exit,
+ .have_governor_per_policy = true,
+ .attr = bL_cpufreq_attr,
+ };
+
++static int bL_cpufreq_switcher_notifier(struct notifier_block *nfb,
++ unsigned long action, void *_arg)
++{
++ pr_debug("%s: action: %ld\n", __func__, action);
++
++ switch (action) {
++ case BL_NOTIFY_PRE_ENABLE:
++ case BL_NOTIFY_PRE_DISABLE:
++ cpufreq_unregister_driver(&bL_cpufreq_driver);
++ break;
++
++ case BL_NOTIFY_POST_ENABLE:
++ set_switching_enabled(true);
++ cpufreq_register_driver(&bL_cpufreq_driver);
++ break;
++
++ case BL_NOTIFY_POST_DISABLE:
++ set_switching_enabled(false);
++ cpufreq_register_driver(&bL_cpufreq_driver);
++ break;
++
++ default:
++ return NOTIFY_DONE;
++ }
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block bL_switcher_notifier = {
++ .notifier_call = bL_cpufreq_switcher_notifier,
++};
++
+ int bL_cpufreq_register(struct cpufreq_arm_bL_ops *ops)
+ {
+- int ret;
++ int ret, i;
+
+ if (arm_bL_ops) {
+ pr_debug("%s: Already registered: %s, exiting\n", __func__,
+@@ -243,16 +545,29 @@
+
+ arm_bL_ops = ops;
+
++ ret = bL_switcher_get_enabled();
++ set_switching_enabled(ret);
++
++ for (i = 0; i < MAX_CLUSTERS; i++)
++ mutex_init(&cluster_lock[i]);
++
+ ret = cpufreq_register_driver(&bL_cpufreq_driver);
+ if (ret) {
+ pr_info("%s: Failed registering platform driver: %s, err: %d\n",
+ __func__, ops->name, ret);
+ arm_bL_ops = NULL;
+ } else {
+- pr_info("%s: Registered platform driver: %s\n", __func__,
+- ops->name);
++ ret = bL_switcher_register_notifier(&bL_switcher_notifier);
++ if (ret) {
++ cpufreq_unregister_driver(&bL_cpufreq_driver);
++ arm_bL_ops = NULL;
++ } else {
++ pr_info("%s: Registered platform driver: %s\n",
++ __func__, ops->name);
++ }
+ }
+
++ bL_switcher_put_enabled();
+ return ret;
+ }
+ EXPORT_SYMBOL_GPL(bL_cpufreq_register);
+@@ -265,9 +580,31 @@
+ return;
+ }
+
++ bL_switcher_get_enabled();
++ bL_switcher_unregister_notifier(&bL_switcher_notifier);
+ cpufreq_unregister_driver(&bL_cpufreq_driver);
++ bL_switcher_put_enabled();
+ pr_info("%s: Un-registered platform driver: %s\n", __func__,
+ arm_bL_ops->name);
++
++ /* For saving table get/put on every cpu in/out */
++ if (is_bL_switching_enabled()) {
++ put_cluster_clk_and_freq_table(get_cpu_device(0));
++ } else {
++ int i;
++
++ for (i = 0; i < MAX_CLUSTERS; i++) {
++ struct device *cdev = get_cpu_device(i);
++ if (!cdev) {
++ pr_err("%s: failed to get cpu%d device\n",
++ __func__, i);
++ return;
++ }
++
++ put_cluster_clk_and_freq_table(cdev);
++ }
++ }
++
+ arm_bL_ops = NULL;
+ }
+ EXPORT_SYMBOL_GPL(bL_cpufreq_unregister);
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/arm_big_little.h linux-linaro-stable-mx6/drivers/cpufreq/arm_big_little.h
+--- linux-3.10.30.orig/drivers/cpufreq/arm_big_little.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/arm_big_little.h 2014-05-15 20:33:46.805933197 +0200
+@@ -23,6 +23,20 @@
+ #include <linux/device.h>
+ #include <linux/types.h>
+
++/* Currently we support only two clusters */
++#define A15_CLUSTER 0
++#define A7_CLUSTER 1
++#define MAX_CLUSTERS 2
++
++#ifdef CONFIG_BL_SWITCHER
++extern bool bL_switching_enabled;
++#define is_bL_switching_enabled() bL_switching_enabled
++#define set_switching_enabled(x) (bL_switching_enabled = (x))
++#else
++#define is_bL_switching_enabled() false
++#define set_switching_enabled(x) do { } while (0)
++#endif
++
+ struct cpufreq_arm_bL_ops {
+ char name[CPUFREQ_NAME_LEN];
+ int (*get_transition_latency)(struct device *cpu_dev);
+@@ -36,7 +50,8 @@
+
+ static inline int cpu_to_cluster(int cpu)
+ {
+- return topology_physical_package_id(cpu);
++ return is_bL_switching_enabled() ? MAX_CLUSTERS:
++ topology_physical_package_id(cpu);
+ }
+
+ int bL_cpufreq_register(struct cpufreq_arm_bL_ops *ops);
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/cpufreq-imx6.c linux-linaro-stable-mx6/drivers/cpufreq/cpufreq-imx6.c
+--- linux-3.10.30.orig/drivers/cpufreq/cpufreq-imx6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/cpufreq-imx6.c 2014-05-15 20:33:46.825933341 +0200
+@@ -0,0 +1,483 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/cpufreq.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/opp.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/slab.h>
++#include <linux/suspend.h>
++
++static struct regulator *arm_reg;
++static struct regulator *pu_reg;
++static struct regulator *soc_reg;
++
++static struct clk *arm_clk;
++static struct clk *pll1_sys_clk;
++static struct clk *pll1_sw_clk;
++static struct clk *step_clk;
++static struct clk *pll2_pfd2_396m_clk;
++
++static struct device *cpu_dev;
++static struct cpufreq_frequency_table *freq_table;
++static unsigned int transition_latency;
++static DEFINE_MUTEX(set_cpufreq_lock);
++
++struct soc_opp {
++ u32 arm_freq;
++ u32 soc_volt;
++};
++
++static struct soc_opp *imx6_soc_opp;
++static u32 soc_opp_count;
++
++static int imx6_verify_speed(struct cpufreq_policy *policy)
++{
++ return cpufreq_frequency_table_verify(policy, freq_table);
++}
++
++static unsigned int imx6_get_speed(unsigned int cpu)
++{
++ return clk_get_rate(arm_clk) / 1000;
++}
++
++static int imx6_set_target(struct cpufreq_policy *policy,
++ unsigned int target_freq, unsigned int relation)
++{
++ struct cpufreq_freqs freqs;
++ struct opp *opp;
++ unsigned long freq_hz, volt, volt_old;
++ unsigned int index, soc_opp_index = 0;
++ int ret;
++
++ mutex_lock(&set_cpufreq_lock);
++
++ ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
++ relation, &index);
++ if (ret) {
++ dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
++ target_freq, ret);
++ mutex_unlock(&set_cpufreq_lock);
++ return ret;
++ }
++
++ freqs.new = freq_table[index].frequency;
++ freq_hz = freqs.new * 1000;
++ freqs.old = clk_get_rate(arm_clk) / 1000;
++
++ if (freqs.old == freqs.new) {
++ mutex_unlock(&set_cpufreq_lock);
++ return 0;
++ }
++
++ cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
++
++ rcu_read_lock();
++ opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
++ if (IS_ERR(opp)) {
++ rcu_read_unlock();
++ dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
++ mutex_unlock(&set_cpufreq_lock);
++ return PTR_ERR(opp);
++ }
++
++ volt = opp_get_voltage(opp);
++ rcu_read_unlock();
++ volt_old = regulator_get_voltage(arm_reg);
++
++ /* Find the matching VDDSOC/VDDPU operating voltage */
++ while (soc_opp_index < soc_opp_count) {
++ if (freqs.new == imx6_soc_opp[soc_opp_index].arm_freq)
++ break;
++ soc_opp_index++;
++ }
++ if (soc_opp_index >= soc_opp_count) {
++ dev_err(cpu_dev,
++ "Cannot find matching imx6_soc_opp voltage\n");
++ mutex_unlock(&set_cpufreq_lock);
++ return -EINVAL;
++ }
++
++ dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
++ freqs.old / 1000, volt_old / 1000,
++ freqs.new / 1000, volt / 1000);
++
++ /*
++ * CPU freq is increasing, so need to ensure
++ * that bus frequency is increased too.
++ */
++ if (freqs.old == freq_table[0].frequency)
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ /* scaling up? scale voltage before frequency */
++ if (freqs.new > freqs.old) {
++ if (regulator_is_enabled(pu_reg)) {
++ ret = regulator_set_voltage_tol(pu_reg,
++ imx6_soc_opp[soc_opp_index].soc_volt,
++ 0);
++ if (ret) {
++ dev_err(cpu_dev,
++ "failed to scale vddpu up: %d\n", ret);
++ goto err1;
++ }
++ }
++ ret = regulator_set_voltage_tol(soc_reg,
++ imx6_soc_opp[soc_opp_index].soc_volt, 0);
++ if (ret) {
++ dev_err(cpu_dev,
++ "failed to scale vddsoc up: %d\n", ret);
++ goto err1;
++ }
++ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
++ if (ret) {
++ dev_err(cpu_dev,
++ "failed to scale vddarm up: %d\n", ret);
++ goto err1;
++ }
++ }
++
++ /*
++ * The setpoints are selected per PLL/PDF frequencies, so we need to
++ * reprogram PLL for frequency scaling. The procedure of reprogramming
++ * PLL1 is as below.
++ *
++ * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
++ * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
++ * - Disable pll2_pfd2_396m_clk
++ */
++ clk_set_parent(step_clk, pll2_pfd2_396m_clk);
++ clk_set_parent(pll1_sw_clk, step_clk);
++ if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
++ clk_set_rate(pll1_sys_clk, freqs.new * 1000);
++ clk_set_parent(pll1_sw_clk, pll1_sys_clk);
++ }
++
++ /* Ensure the arm clock divider is what we expect */
++ ret = clk_set_rate(arm_clk, freqs.new * 1000);
++ if (ret) {
++ dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
++ goto err1;
++ }
++
++ /* scaling down? scale voltage after frequency */
++ if (freqs.new < freqs.old) {
++ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
++ if (ret) {
++ dev_warn(cpu_dev,
++ "failed to scale vddarm down: %d\n", ret);
++ goto err1;
++ }
++
++ ret = regulator_set_voltage_tol(soc_reg,
++ imx6_soc_opp[soc_opp_index].soc_volt, 0);
++ if (ret) {
++ dev_err(cpu_dev,
++ "failed to scale vddsoc down: %d\n", ret);
++ goto err1;
++ }
++
++ if (regulator_is_enabled(pu_reg)) {
++ ret = regulator_set_voltage_tol(pu_reg,
++ imx6_soc_opp[soc_opp_index].soc_volt,
++ 0);
++ if (ret) {
++ dev_err(cpu_dev,
++ "failed to scale vddpu down: %d\n", ret);
++ goto err1;
++ }
++ }
++ }
++ /*
++ * If CPU is dropped to the lowest level, release the need
++ * for a high bus frequency.
++ */
++ if (freqs.new == freq_table[0].frequency)
++ release_bus_freq(BUS_FREQ_HIGH);
++
++ cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
++
++ mutex_unlock(&set_cpufreq_lock);
++ return 0;
++err1:
++ mutex_unlock(&set_cpufreq_lock);
++ return -1;
++}
++
++static int imx6_cpufreq_init(struct cpufreq_policy *policy)
++{
++ int ret;
++
++ ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
++ if (ret) {
++ dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
++ return ret;
++ }
++
++ policy->cpuinfo.transition_latency = transition_latency;
++ policy->cur = clk_get_rate(arm_clk) / 1000;
++ cpumask_setall(policy->cpus);
++ cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
++
++ if (policy->cur > freq_table[0].frequency)
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ return 0;
++}
++
++static int imx6_cpufreq_exit(struct cpufreq_policy *policy)
++{
++ cpufreq_frequency_table_put_attr(policy->cpu);
++ return 0;
++}
++
++static struct freq_attr *imx6_cpufreq_attr[] = {
++ &cpufreq_freq_attr_scaling_available_freqs,
++ NULL,
++};
++
++static struct cpufreq_driver imx6_cpufreq_driver = {
++ .verify = imx6_verify_speed,
++ .target = imx6_set_target,
++ .get = imx6_get_speed,
++ .init = imx6_cpufreq_init,
++ .exit = imx6_cpufreq_exit,
++ .name = "imx6-cpufreq",
++ .attr = imx6_cpufreq_attr,
++};
++
++static int imx6_cpufreq_pm_notify(struct notifier_block *nb,
++ unsigned long event, void *dummy)
++{
++ struct cpufreq_policy *data = cpufreq_cpu_get(0);
++ static u32 cpufreq_policy_min_pre_suspend;
++
++ /*
++ * During suspend/resume, When cpufreq driver try to increase
++ * voltage/freq, it needs to control I2C/SPI to communicate
++ * with external PMIC to adjust voltage, but these I2C/SPI
++ * devices may be already suspended, to avoid such scenario,
++ * we just increase cpufreq to highest setpoint before suspend.
++ */
++ switch (event) {
++ case PM_SUSPEND_PREPARE:
++ cpufreq_policy_min_pre_suspend = data->user_policy.min;
++ data->user_policy.min = data->user_policy.max;
++ break;
++ case PM_POST_SUSPEND:
++ data->user_policy.min = cpufreq_policy_min_pre_suspend;
++ break;
++ default:
++ break;
++ }
++
++ cpufreq_update_policy(0);
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block imx6_cpufreq_pm_notifier = {
++ .notifier_call = imx6_cpufreq_pm_notify,
++};
++
++static int imx6_cpufreq_probe(struct platform_device *pdev)
++{
++ struct device_node *np;
++ struct opp *opp;
++ unsigned long min_volt = 0, max_volt = 0;
++ int num, ret;
++ const struct property *prop;
++ const __be32 *val;
++ u32 nr, i;
++
++ cpu_dev = &pdev->dev;
++
++ np = of_find_node_by_path("/cpus/cpu@0");
++ if (!np) {
++ dev_err(cpu_dev, "failed to find cpu0 node\n");
++ return -ENOENT;
++ }
++
++ cpu_dev->of_node = np;
++
++ arm_clk = devm_clk_get(cpu_dev, "arm");
++ pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
++ pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
++ step_clk = devm_clk_get(cpu_dev, "step");
++ pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
++ if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
++ IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
++ dev_err(cpu_dev, "failed to get clocks\n");
++ ret = -ENOENT;
++ goto put_node;
++ }
++
++ arm_reg = devm_regulator_get(cpu_dev, "arm");
++ pu_reg = devm_regulator_get(cpu_dev, "pu");
++ soc_reg = devm_regulator_get(cpu_dev, "soc");
++ if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
++ dev_err(cpu_dev, "failed to get regulators\n");
++ ret = -ENOENT;
++ goto put_node;
++ }
++
++ /* We expect an OPP table supplied by platform */
++ num = opp_get_opp_count(cpu_dev);
++ if (num < 0) {
++ ret = num;
++ dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
++ goto put_node;
++ }
++
++ ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
++ if (ret) {
++ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
++ goto put_node;
++ }
++
++ prop = of_find_property(np, "fsl,soc-operating-points", NULL);
++ if (!prop) {
++ dev_err(cpu_dev,
++ "fsl,soc-operating-points node not found\n");
++ goto free_freq_table;
++ }
++ if (!prop->value) {
++ dev_err(cpu_dev,
++ "No entries in fsl-soc-operating-points node.\n");
++ goto free_freq_table;
++ }
++
++ /*
++ * Each OPP is a set of tuples consisting of frequency and
++ * voltage like <freq-kHz vol-uV>.
++ */
++ nr = prop->length / sizeof(u32);
++ if (nr % 2) {
++ dev_err(cpu_dev, "Invalid fsl-soc-operating-points list\n");
++ goto free_freq_table;
++ }
++
++ /* Get the VDDSOC/VDDPU voltages that need to track the CPU voltages. */
++ imx6_soc_opp = devm_kzalloc(cpu_dev,
++ sizeof(struct soc_opp) * (nr / 2),
++ GFP_KERNEL);
++
++ if (imx6_soc_opp == NULL) {
++ dev_err(cpu_dev, "No Memory for VDDSOC/PU table\n");
++ goto free_freq_table;
++ }
++
++ rcu_read_lock();
++ val = prop->value;
++
++ for (i = 0; i < nr / 2; i++) {
++ unsigned long freq = be32_to_cpup(val++);
++ unsigned long volt = be32_to_cpup(val++);
++
++ if (i == 0)
++ min_volt = max_volt = volt;
++ if (volt < min_volt)
++ min_volt = volt;
++ if (volt > max_volt)
++ max_volt = volt;
++ opp = opp_find_freq_exact(cpu_dev,
++ freq * 1000, true);
++ if (IS_ERR(opp)) {
++ opp = opp_find_freq_exact(cpu_dev,
++ freq * 1000, false);
++ if (IS_ERR(opp)) {
++ dev_err(cpu_dev,
++ "freq in soc-operating-points does not \
++ match cpufreq table\n");
++ rcu_read_unlock();
++ goto free_freq_table;
++ }
++ }
++ imx6_soc_opp[i].arm_freq = freq;
++ imx6_soc_opp[i].soc_volt = volt;
++ soc_opp_count++;
++ }
++ rcu_read_unlock();
++
++ if (of_property_read_u32(np, "clock-latency", &transition_latency))
++ transition_latency = CPUFREQ_ETERNAL;
++
++ /*
++ * Calculate the ramp time for max voltage change in the
++ * VDDSOC and VDDPU regulators.
++ */
++ ret = regulator_set_voltage_time(soc_reg, min_volt, max_volt);
++ if (ret > 0)
++ transition_latency += ret * 1000;
++
++ ret = regulator_set_voltage_time(pu_reg, min_volt, max_volt);
++ if (ret > 0)
++ transition_latency += ret * 1000;
++
++ /*
++ * OPP is maintained in order of increasing frequency, and
++ * freq_table initialised from OPP is therefore sorted in the
++ * same order.
++ */
++ rcu_read_lock();
++ opp = opp_find_freq_exact(cpu_dev,
++ freq_table[0].frequency * 1000, true);
++ min_volt = opp_get_voltage(opp);
++ opp = opp_find_freq_exact(cpu_dev,
++ freq_table[num - 1].frequency * 1000, true);
++ max_volt = opp_get_voltage(opp);
++ rcu_read_unlock();
++ ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
++ if (ret > 0)
++ transition_latency += ret * 1000;
++
++ mutex_init(&set_cpufreq_lock);
++ register_pm_notifier(&imx6_cpufreq_pm_notifier);
++
++ ret = cpufreq_register_driver(&imx6_cpufreq_driver);
++ if (ret) {
++ dev_err(cpu_dev, "failed register driver: %d\n", ret);
++ goto free_freq_table;
++ }
++
++ of_node_put(np);
++ return 0;
++
++free_freq_table:
++ opp_free_cpufreq_table(cpu_dev, &freq_table);
++put_node:
++ of_node_put(np);
++ return ret;
++}
++
++static int imx6_cpufreq_remove(struct platform_device *pdev)
++{
++ cpufreq_unregister_driver(&imx6_cpufreq_driver);
++ opp_free_cpufreq_table(cpu_dev, &freq_table);
++
++ return 0;
++}
++
++static struct platform_driver imx6_cpufreq_platdrv = {
++ .driver = {
++ .name = "imx6-cpufreq",
++ .owner = THIS_MODULE,
++ },
++ .probe = imx6_cpufreq_probe,
++ .remove = imx6_cpufreq_remove,
++};
++module_platform_driver(imx6_cpufreq_platdrv);
++
++MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
++MODULE_DESCRIPTION("Freescale i.MX6 cpufreq driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/cpufreq_interactive.c linux-linaro-stable-mx6/drivers/cpufreq/cpufreq_interactive.c
+--- linux-3.10.30.orig/drivers/cpufreq/cpufreq_interactive.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/cpufreq_interactive.c 2014-05-15 20:33:46.825933341 +0200
+@@ -0,0 +1,705 @@
++/*
++ * drivers/cpufreq/cpufreq_interactive.c
++ *
++ * Copyright (C) 2010 Google, Inc.
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Author: Mike Chan (mike@android.com)
++ *
++ */
++
++#include <linux/cpu.h>
++#include <linux/cpumask.h>
++#include <linux/cpufreq.h>
++#include <linux/mutex.h>
++#include <linux/sched.h>
++#include <linux/tick.h>
++#include <linux/time.h>
++#include <linux/timer.h>
++#include <linux/workqueue.h>
++#include <linux/kthread.h>
++#include <linux/mutex.h>
++#include <linux/kernel_stat.h>
++#include <linux/module.h>
++#include <asm/cputime.h>
++
++static atomic_t active_count = ATOMIC_INIT(0);
++
++struct cpufreq_interactive_cpuinfo {
++ struct timer_list cpu_timer;
++ int timer_idlecancel;
++ u64 time_in_idle;
++ u64 idle_exit_time;
++ u64 timer_run_time;
++ int idling;
++ u64 freq_change_time;
++ u64 freq_change_time_in_idle;
++ struct cpufreq_policy *policy;
++ struct cpufreq_frequency_table *freq_table;
++ unsigned int target_freq;
++ int governor_enabled;
++};
++
++static DEFINE_PER_CPU(struct cpufreq_interactive_cpuinfo, cpuinfo);
++
++/* Workqueues handle frequency scaling */
++static struct task_struct *up_task;
++static struct workqueue_struct *down_wq;
++static struct work_struct freq_scale_down_work;
++static cpumask_t up_cpumask;
++static spinlock_t up_cpumask_lock;
++static cpumask_t down_cpumask;
++static spinlock_t down_cpumask_lock;
++static struct mutex set_speed_lock;
++
++/* Hi speed to bump to from lo speed when load burst (default max) */
++static u64 hispeed_freq;
++
++/* Go to hi speed when CPU load at or above this value. */
++#define DEFAULT_GO_HISPEED_LOAD 95
++static unsigned long go_hispeed_load;
++
++/*
++ * The minimum amount of time to spend at a frequency before we can ramp down.
++ */
++#define DEFAULT_MIN_SAMPLE_TIME (20 * USEC_PER_MSEC)
++static unsigned long min_sample_time;
++
++/*
++ * The sample rate of the timer used to increase frequency
++ */
++#define DEFAULT_TIMER_RATE (50 * USEC_PER_MSEC)
++#define CPUFREQ_IRQ_LEN 60
++#define CPUFREQ_NOTE_LEN 120
++static unsigned long timer_rate;
++
++static int cpufreq_governor_interactive(struct cpufreq_policy *policy,
++ unsigned int event);
++
++#ifndef CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE
++static
++#endif
++struct cpufreq_governor cpufreq_gov_interactive = {
++ .name = "interactive",
++ .governor = cpufreq_governor_interactive,
++ .max_transition_latency = 10000000,
++ .owner = THIS_MODULE,
++};
++
++static void cpufreq_interactive_timer(unsigned long data)
++{
++ unsigned int delta_idle;
++ unsigned int delta_time;
++ int cpu_load;
++ int load_since_change;
++ u64 time_in_idle;
++ u64 idle_exit_time;
++ struct cpufreq_interactive_cpuinfo *pcpu =
++ &per_cpu(cpuinfo, data);
++ u64 now_idle;
++ unsigned int new_freq;
++ unsigned int index;
++ unsigned long flags;
++
++ smp_rmb();
++
++ if (!pcpu->governor_enabled)
++ goto exit;
++
++ /*
++ * Once pcpu->timer_run_time is updated to >= pcpu->idle_exit_time,
++ * this lets idle exit know the current idle time sample has
++ * been processed, and idle exit can generate a new sample and
++ * re-arm the timer. This prevents a concurrent idle
++ * exit on that CPU from writing a new set of info at the same time
++ * the timer function runs (the timer function can't use that info
++ * until more time passes).
++ */
++ time_in_idle = pcpu->time_in_idle;
++ idle_exit_time = pcpu->idle_exit_time;
++ now_idle = get_cpu_idle_time_us(data, &pcpu->timer_run_time);
++ smp_wmb();
++
++ /* If we raced with cancelling a timer, skip. */
++ if (!idle_exit_time)
++ goto exit;
++
++ delta_idle = (unsigned int)(now_idle - time_in_idle);
++ delta_time = (unsigned int)(pcpu->timer_run_time - idle_exit_time);
++
++ /*
++ * If timer ran less than 1ms after short-term sample started, retry.
++ */
++ if (delta_time < 1000)
++ goto rearm;
++
++ if (delta_idle > delta_time)
++ cpu_load = 0;
++ else
++ cpu_load = 100 * (delta_time - delta_idle) / delta_time;
++
++ delta_idle = (unsigned int)(now_idle - pcpu->freq_change_time_in_idle);
++ delta_time = (unsigned int)(pcpu->timer_run_time -
++ pcpu->freq_change_time);
++
++ if ((delta_time == 0) || (delta_idle > delta_time))
++ load_since_change = 0;
++ else
++ load_since_change =
++ 100 * (delta_time - delta_idle) / delta_time;
++
++ /*
++ * Choose greater of short-term load (since last idle timer
++ * started or timer function re-armed itself) or long-term load
++ * (since last frequency change).
++ */
++ if (load_since_change > cpu_load)
++ cpu_load = load_since_change;
++
++ if (cpu_load >= go_hispeed_load) {
++ if (pcpu->policy->cur == pcpu->policy->min)
++ new_freq = hispeed_freq;
++ else
++ new_freq = pcpu->policy->max * cpu_load / 100;
++ } else {
++ new_freq = pcpu->policy->cur * cpu_load / 100;
++ }
++
++ if (cpufreq_frequency_table_target(pcpu->policy, pcpu->freq_table,
++ new_freq, CPUFREQ_RELATION_H,
++ &index)) {
++ pr_warn_once("timer %d: cpufreq_frequency_table_target error\n",
++ (int) data);
++ goto rearm;
++ }
++
++ new_freq = pcpu->freq_table[index].frequency;
++ if (pcpu->target_freq == new_freq)
++ goto rearm_if_notmax;
++
++ /*
++ * Do not scale down unless we have been at this frequency for the
++ * minimum sample time.
++ */
++ if (new_freq < pcpu->target_freq) {
++ if ((pcpu->timer_run_time - pcpu->freq_change_time)
++ < min_sample_time)
++ goto rearm;
++ }
++
++ if (new_freq < pcpu->target_freq) {
++ pcpu->target_freq = new_freq;
++ spin_lock_irqsave(&down_cpumask_lock, flags);
++ cpumask_set_cpu(data, &down_cpumask);
++ spin_unlock_irqrestore(&down_cpumask_lock, flags);
++ queue_work(down_wq, &freq_scale_down_work);
++ } else {
++ pcpu->target_freq = new_freq;
++ spin_lock_irqsave(&up_cpumask_lock, flags);
++ cpumask_set_cpu(data, &up_cpumask);
++ spin_unlock_irqrestore(&up_cpumask_lock, flags);
++ wake_up_process(up_task);
++ }
++
++rearm_if_notmax:
++ /*
++ * Already set max speed and don't see a need to change that,
++ * wait until next idle to re-evaluate, don't need timer.
++ */
++ if (pcpu->target_freq == pcpu->policy->max)
++ goto exit;
++
++rearm:
++ if (!timer_pending(&pcpu->cpu_timer)) {
++ /*
++ * If already at min: if that CPU is idle, don't set timer.
++ * Else cancel the timer if that CPU goes idle. We don't
++ * need to re-evaluate speed until the next idle exit.
++ */
++ if (pcpu->target_freq == pcpu->policy->min) {
++ smp_rmb();
++
++ if (pcpu->idling)
++ goto exit;
++
++ pcpu->timer_idlecancel = 1;
++ }
++
++ pcpu->time_in_idle = get_cpu_idle_time_us(
++ data, &pcpu->idle_exit_time);
++ mod_timer(&pcpu->cpu_timer,
++ jiffies + usecs_to_jiffies(timer_rate));
++ }
++
++exit:
++ return;
++}
++
++static void cpufreq_interactive_idle_start(void)
++{
++ struct cpufreq_interactive_cpuinfo *pcpu =
++ &per_cpu(cpuinfo, smp_processor_id());
++ int pending;
++
++ pcpu->idling = 1;
++ smp_wmb();
++ if (!pcpu->governor_enabled)
++ return;
++ pending = timer_pending(&pcpu->cpu_timer);
++
++ if (pcpu->target_freq != pcpu->policy->min) {
++#ifdef CONFIG_SMP
++ /*
++ * Entering idle while not at lowest speed. On some
++ * platforms this can hold the other CPU(s) at that speed
++ * even though the CPU is idle. Set a timer to re-evaluate
++ * speed so this idle CPU doesn't hold the other CPUs above
++ * min indefinitely. This should probably be a quirk of
++ * the CPUFreq driver.
++ */
++ if (!pending) {
++ pcpu->time_in_idle = get_cpu_idle_time_us(
++ smp_processor_id(), &pcpu->idle_exit_time);
++ pcpu->timer_idlecancel = 0;
++ mod_timer(&pcpu->cpu_timer,
++ jiffies + usecs_to_jiffies(timer_rate));
++ }
++#endif
++ } else {
++ /*
++ * If at min speed and entering idle after load has
++ * already been evaluated, and a timer has been set just in
++ * case the CPU suddenly goes busy, cancel that timer. The
++ * CPU didn't go busy; we'll recheck things upon idle exit.
++ */
++ if (pending && pcpu->timer_idlecancel) {
++ del_timer(&pcpu->cpu_timer);
++ /*
++ * Ensure last timer run time is after current idle
++ * sample start time, so next idle exit will always
++ * start a new idle sampling period.
++ */
++ pcpu->idle_exit_time = 0;
++ pcpu->timer_idlecancel = 0;
++ }
++ }
++
++}
++
++static void cpufreq_interactive_idle_end(void)
++{
++ struct cpufreq_interactive_cpuinfo *pcpu =
++ &per_cpu(cpuinfo, smp_processor_id());
++
++ pcpu->idling = 0;
++ smp_wmb();
++
++ /*
++ * Arm the timer for 1-2 ticks later if not already, and if the timer
++ * function has already processed the previous load sampling
++ * interval. (If the timer is not pending but has not processed
++ * the previous interval, it is probably racing with us on another
++ * CPU. Let it compute load based on the previous sample and then
++ * re-arm the timer for another interval when it's done, rather
++ * than updating the interval start time to be "now", which doesn't
++ * give the timer function enough time to make a decision on this
++ * run.)
++ */
++ if (timer_pending(&pcpu->cpu_timer) == 0 &&
++ pcpu->timer_run_time >= pcpu->idle_exit_time &&
++ pcpu->governor_enabled) {
++ pcpu->time_in_idle =
++ get_cpu_idle_time_us(smp_processor_id(),
++ &pcpu->idle_exit_time);
++ pcpu->timer_idlecancel = 0;
++ mod_timer(&pcpu->cpu_timer,
++ jiffies + usecs_to_jiffies(timer_rate));
++ }
++
++}
++
++static int cpufreq_interactive_up_task(void *data)
++{
++ unsigned int cpu;
++ unsigned long flags;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++
++ while (1) {
++ set_current_state(TASK_INTERRUPTIBLE);
++ spin_lock_irqsave(&up_cpumask_lock, flags);
++
++ if (cpumask_empty(&up_cpumask)) {
++ spin_unlock_irqrestore(&up_cpumask_lock, flags);
++ schedule();
++
++ if (kthread_should_stop())
++ break;
++
++ spin_lock_irqsave(&up_cpumask_lock, flags);
++ }
++
++ set_current_state(TASK_RUNNING);
++ cpumask_clear(&up_cpumask);
++ spin_unlock_irqrestore(&up_cpumask_lock, flags);
++
++ for_each_online_cpu(cpu) {
++ unsigned int j;
++ unsigned int max_freq = 0;
++
++ pcpu = &per_cpu(cpuinfo, cpu);
++ smp_rmb();
++
++ if (!pcpu->governor_enabled)
++ continue;
++
++ mutex_lock(&set_speed_lock);
++
++ for_each_online_cpu(j) {
++ struct cpufreq_interactive_cpuinfo *pjcpu =
++ &per_cpu(cpuinfo, j);
++ if (pjcpu->target_freq > max_freq)
++ max_freq = pjcpu->target_freq;
++ }
++ if (max_freq != pcpu->policy->cur)
++ __cpufreq_driver_target(pcpu->policy,
++ max_freq,
++ CPUFREQ_RELATION_H);
++ mutex_unlock(&set_speed_lock);
++
++ pcpu->freq_change_time_in_idle =
++ get_cpu_idle_time_us(cpu,
++ &pcpu->freq_change_time);
++ }
++ }
++
++ return 0;
++}
++
++static void cpufreq_interactive_freq_down(struct work_struct *work)
++{
++ unsigned int cpu;
++ unsigned long flags;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++
++ spin_lock_irqsave(&down_cpumask_lock, flags);
++ cpumask_clear(&down_cpumask);
++ spin_unlock_irqrestore(&down_cpumask_lock, flags);
++
++ for_each_online_cpu(cpu) {
++ unsigned int j;
++ unsigned int max_freq = 0;
++
++ pcpu = &per_cpu(cpuinfo, cpu);
++ smp_rmb();
++
++ if (!pcpu->governor_enabled)
++ continue;
++
++ mutex_lock(&set_speed_lock);
++
++ for_each_online_cpu(j) {
++ struct cpufreq_interactive_cpuinfo *pjcpu =
++ &per_cpu(cpuinfo, j);
++
++ if (pjcpu->target_freq > max_freq)
++ max_freq = pjcpu->target_freq;
++ }
++
++ if (max_freq != pcpu->policy->cur)
++ __cpufreq_driver_target(pcpu->policy, max_freq,
++ CPUFREQ_RELATION_H);
++
++ mutex_unlock(&set_speed_lock);
++ pcpu->freq_change_time_in_idle =
++ get_cpu_idle_time_us(cpu,
++ &pcpu->freq_change_time);
++ }
++}
++
++static ssize_t show_hispeed_freq(struct kobject *kobj,
++ struct attribute *attr, char *buf)
++{
++ return sprintf(buf, "%llu\n", hispeed_freq);
++}
++
++static ssize_t store_hispeed_freq(struct kobject *kobj,
++ struct attribute *attr, const char *buf,
++ size_t count)
++{
++ int ret;
++ u64 val;
++
++ ret = strict_strtoull(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ hispeed_freq = val;
++ return count;
++}
++
++static struct global_attr hispeed_freq_attr = __ATTR(hispeed_freq, 0644,
++ show_hispeed_freq, store_hispeed_freq);
++
++
++static ssize_t show_go_hispeed_load(struct kobject *kobj,
++ struct attribute *attr, char *buf)
++{
++ return sprintf(buf, "%lu\n", go_hispeed_load);
++}
++
++static ssize_t store_go_hispeed_load(struct kobject *kobj,
++ struct attribute *attr, const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = strict_strtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ go_hispeed_load = val;
++ return count;
++}
++
++static struct global_attr go_hispeed_load_attr = __ATTR(go_hispeed_load, 0644,
++ show_go_hispeed_load, store_go_hispeed_load);
++
++static ssize_t show_min_sample_time(struct kobject *kobj,
++ struct attribute *attr, char *buf)
++{
++ return sprintf(buf, "%lu\n", min_sample_time);
++}
++
++static ssize_t store_min_sample_time(struct kobject *kobj,
++ struct attribute *attr, const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = strict_strtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ min_sample_time = val;
++ return count;
++}
++
++static struct global_attr min_sample_time_attr = __ATTR(min_sample_time, 0644,
++ show_min_sample_time, store_min_sample_time);
++
++static ssize_t show_timer_rate(struct kobject *kobj,
++ struct attribute *attr, char *buf)
++{
++ return sprintf(buf, "%lu\n", timer_rate);
++}
++
++static ssize_t store_timer_rate(struct kobject *kobj,
++ struct attribute *attr, const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = strict_strtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ timer_rate = val;
++ return count;
++}
++
++static struct global_attr timer_rate_attr = __ATTR(timer_rate, 0644,
++ show_timer_rate, store_timer_rate);
++
++static struct attribute *interactive_attributes[] = {
++ &hispeed_freq_attr.attr,
++ &go_hispeed_load_attr.attr,
++ &min_sample_time_attr.attr,
++ &timer_rate_attr.attr,
++ NULL,
++};
++
++static struct attribute_group interactive_attr_group = {
++ .attrs = interactive_attributes,
++ .name = "interactive",
++};
++
++static int cpufreq_governor_interactive(struct cpufreq_policy *policy,
++ unsigned int event)
++{
++ int rc;
++ unsigned int j;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++ struct cpufreq_frequency_table *freq_table;
++
++ switch (event) {
++ case CPUFREQ_GOV_START:
++ if (!cpu_online(policy->cpu))
++ return -EINVAL;
++
++ freq_table =
++ cpufreq_frequency_get_table(policy->cpu);
++
++ for_each_cpu(j, policy->cpus) {
++ pcpu = &per_cpu(cpuinfo, j);
++ pcpu->policy = policy;
++ if (pcpu->idling)
++ pcpu->target_freq = policy->min;
++ else
++ pcpu->target_freq = policy->cur;
++
++ pcpu->freq_table = freq_table;
++ pcpu->freq_change_time_in_idle =
++ get_cpu_idle_time_us(j,
++ &pcpu->freq_change_time);
++ pcpu->governor_enabled = 1;
++ smp_wmb();
++ }
++
++ if (!hispeed_freq)
++ hispeed_freq = policy->max;
++
++ /*
++ * Do not register the idle hook and create sysfs
++ * entries if we have already done so.
++ */
++ if (atomic_inc_return(&active_count) > 1)
++ return 0;
++
++ rc = sysfs_create_group(cpufreq_global_kobject,
++ &interactive_attr_group);
++ if (rc)
++ return rc;
++
++ break;
++
++ case CPUFREQ_GOV_STOP:
++ for_each_cpu(j, policy->cpus) {
++ pcpu = &per_cpu(cpuinfo, j);
++ pcpu->governor_enabled = 0;
++ smp_wmb();
++ del_timer_sync(&pcpu->cpu_timer);
++
++ /*
++ * Reset idle exit time since we may cancel the timer
++ * before it can run after the last idle exit time,
++ * to avoid tripping the check in idle exit for a timer
++ * that is trying to run.
++ */
++ pcpu->idle_exit_time = 0;
++ }
++
++ flush_work(&freq_scale_down_work);
++ if (atomic_dec_return(&active_count) > 0)
++ return 0;
++
++ sysfs_remove_group(cpufreq_global_kobject,
++ &interactive_attr_group);
++
++ break;
++
++ case CPUFREQ_GOV_LIMITS:
++ if (policy->max < policy->cur)
++ __cpufreq_driver_target(policy,
++ policy->max, CPUFREQ_RELATION_H);
++ else if (policy->min > policy->cur)
++ __cpufreq_driver_target(policy,
++ policy->min, CPUFREQ_RELATION_L);
++ break;
++ }
++ return 0;
++}
++
++static int cpufreq_interactive_idle_notifier(struct notifier_block *nb,
++ unsigned long val,
++ void *data)
++{
++ switch (val) {
++ case IDLE_START:
++ cpufreq_interactive_idle_start();
++ break;
++ case IDLE_END:
++ cpufreq_interactive_idle_end();
++ break;
++ }
++
++ return 0;
++}
++
++static struct notifier_block cpufreq_interactive_idle_nb = {
++ .notifier_call = cpufreq_interactive_idle_notifier,
++};
++
++static int __init cpufreq_interactive_init(void)
++{
++ unsigned int i;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++ struct sched_param param = { .sched_priority = 99 };
++
++ go_hispeed_load = DEFAULT_GO_HISPEED_LOAD;
++ min_sample_time = DEFAULT_MIN_SAMPLE_TIME;
++ timer_rate = DEFAULT_TIMER_RATE;
++
++ /* Initalize per-cpu timers */
++ for_each_possible_cpu(i) {
++ pcpu = &per_cpu(cpuinfo, i);
++ init_timer(&pcpu->cpu_timer);
++ pcpu->cpu_timer.function = cpufreq_interactive_timer;
++ pcpu->cpu_timer.data = i;
++ }
++
++ up_task = kthread_create(cpufreq_interactive_up_task, NULL,
++ "kinteractiveup");
++ if (IS_ERR(up_task))
++ return PTR_ERR(up_task);
++
++ sched_setscheduler_nocheck(up_task, SCHED_FIFO, &param);
++ get_task_struct(up_task);
++
++ /* No rescuer thread, bind to CPU queuing the work for possibly
++ warm cache (probably doesn't matter much). */
++ down_wq = alloc_workqueue("kinteractive_down", 0, 1);
++
++ if (!down_wq)
++ goto err_freeuptask;
++
++ INIT_WORK(&freq_scale_down_work,
++ cpufreq_interactive_freq_down);
++
++ spin_lock_init(&up_cpumask_lock);
++ spin_lock_init(&down_cpumask_lock);
++ mutex_init(&set_speed_lock);
++
++ idle_notifier_register(&cpufreq_interactive_idle_nb);
++
++ return cpufreq_register_governor(&cpufreq_gov_interactive);
++
++err_freeuptask:
++ put_task_struct(up_task);
++ return -ENOMEM;
++}
++
++#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE
++late_initcall(cpufreq_interactive_init);
++#else
++module_init(cpufreq_interactive_init);
++#endif
++
++static void __exit cpufreq_interactive_exit(void)
++{
++ cpufreq_unregister_governor(&cpufreq_gov_interactive);
++ kthread_stop(up_task);
++ put_task_struct(up_task);
++ destroy_workqueue(down_wq);
++}
++
++module_exit(cpufreq_interactive_exit);
++
++MODULE_AUTHOR("Mike Chan <mike@android.com>");
++MODULE_DESCRIPTION("'cpufreq_interactive' - A cpufreq governor for "
++ "Latency sensitive workloads");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/cpufreq_ondemand.c linux-linaro-stable-mx6/drivers/cpufreq/cpufreq_ondemand.c
+--- linux-3.10.30.orig/drivers/cpufreq/cpufreq_ondemand.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/cpufreq_ondemand.c 2014-05-15 20:33:46.825933341 +0200
+@@ -76,6 +76,8 @@
+ boot_cpu_data.x86 == 6 &&
+ boot_cpu_data.x86_model >= 15)
+ return 1;
++#else if defined(CONFIG_ARM_IMX6_CPUFREQ)
++ return 1;
+ #endif
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/cpufreq_stats.c linux-linaro-stable-mx6/drivers/cpufreq/cpufreq_stats.c
+--- linux-3.10.30.orig/drivers/cpufreq/cpufreq_stats.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/cpufreq_stats.c 2014-05-15 20:33:46.825933341 +0200
+@@ -21,6 +21,9 @@
+ #include <linux/spinlock.h>
+ #include <linux/notifier.h>
+ #include <asm/cputime.h>
++#ifdef CONFIG_BL_SWITCHER
++#include <asm/bL_switcher.h>
++#endif
+
+ static spinlock_t cpufreq_stats_lock;
+
+@@ -378,7 +381,7 @@
+ .notifier_call = cpufreq_stat_notifier_trans
+ };
+
+-static int __init cpufreq_stats_init(void)
++static int cpufreq_stats_setup(void)
+ {
+ int ret;
+ unsigned int cpu;
+@@ -406,7 +409,8 @@
+
+ return 0;
+ }
+-static void __exit cpufreq_stats_exit(void)
++
++static void cpufreq_stats_cleanup(void)
+ {
+ unsigned int cpu;
+
+@@ -421,6 +425,54 @@
+ }
+ }
+
++#ifdef CONFIG_BL_SWITCHER
++static int cpufreq_stats_switcher_notifier(struct notifier_block *nfb,
++ unsigned long action, void *_arg)
++{
++ switch (action) {
++ case BL_NOTIFY_PRE_ENABLE:
++ case BL_NOTIFY_PRE_DISABLE:
++ cpufreq_stats_cleanup();
++ break;
++
++ case BL_NOTIFY_POST_ENABLE:
++ case BL_NOTIFY_POST_DISABLE:
++ cpufreq_stats_setup();
++ break;
++
++ default:
++ return NOTIFY_DONE;
++ }
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block switcher_notifier = {
++ .notifier_call = cpufreq_stats_switcher_notifier,
++};
++#endif
++
++static int __init cpufreq_stats_init(void)
++{
++ int ret;
++ spin_lock_init(&cpufreq_stats_lock);
++
++ ret = cpufreq_stats_setup();
++#ifdef CONFIG_BL_SWITCHER
++ if (!ret)
++ bL_switcher_register_notifier(&switcher_notifier);
++#endif
++ return ret;
++}
++
++static void __exit cpufreq_stats_exit(void)
++{
++#ifdef CONFIG_BL_SWITCHER
++ bL_switcher_unregister_notifier(&switcher_notifier);
++#endif
++ cpufreq_stats_cleanup();
++}
++
+ MODULE_AUTHOR("Zou Nan hai <nanhai.zou@intel.com>");
+ MODULE_DESCRIPTION("'cpufreq_stats' - A driver to export cpufreq stats "
+ "through sysfs filesystem");
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/imx6q-cpufreq.c linux-linaro-stable-mx6/drivers/cpufreq/imx6q-cpufreq.c
+--- linux-3.10.30.orig/drivers/cpufreq/imx6q-cpufreq.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/imx6q-cpufreq.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,330 +0,0 @@
+-/*
+- * Copyright (C) 2013 Freescale Semiconductor, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#include <linux/clk.h>
+-#include <linux/cpufreq.h>
+-#include <linux/delay.h>
+-#include <linux/err.h>
+-#include <linux/module.h>
+-#include <linux/of.h>
+-#include <linux/opp.h>
+-#include <linux/platform_device.h>
+-#include <linux/regulator/consumer.h>
+-
+-#define PU_SOC_VOLTAGE_NORMAL 1250000
+-#define PU_SOC_VOLTAGE_HIGH 1275000
+-#define FREQ_1P2_GHZ 1200000000
+-
+-static struct regulator *arm_reg;
+-static struct regulator *pu_reg;
+-static struct regulator *soc_reg;
+-
+-static struct clk *arm_clk;
+-static struct clk *pll1_sys_clk;
+-static struct clk *pll1_sw_clk;
+-static struct clk *step_clk;
+-static struct clk *pll2_pfd2_396m_clk;
+-
+-static struct device *cpu_dev;
+-static struct cpufreq_frequency_table *freq_table;
+-static unsigned int transition_latency;
+-
+-static int imx6q_verify_speed(struct cpufreq_policy *policy)
+-{
+- return cpufreq_frequency_table_verify(policy, freq_table);
+-}
+-
+-static unsigned int imx6q_get_speed(unsigned int cpu)
+-{
+- return clk_get_rate(arm_clk) / 1000;
+-}
+-
+-static int imx6q_set_target(struct cpufreq_policy *policy,
+- unsigned int target_freq, unsigned int relation)
+-{
+- struct cpufreq_freqs freqs;
+- struct opp *opp;
+- unsigned long freq_hz, volt, volt_old;
+- unsigned int index;
+- int ret;
+-
+- ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
+- relation, &index);
+- if (ret) {
+- dev_err(cpu_dev, "failed to match target frequency %d: %d\n",
+- target_freq, ret);
+- return ret;
+- }
+-
+- freqs.new = freq_table[index].frequency;
+- freq_hz = freqs.new * 1000;
+- freqs.old = clk_get_rate(arm_clk) / 1000;
+-
+- if (freqs.old == freqs.new)
+- return 0;
+-
+- cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
+-
+- rcu_read_lock();
+- opp = opp_find_freq_ceil(cpu_dev, &freq_hz);
+- if (IS_ERR(opp)) {
+- rcu_read_unlock();
+- dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
+- return PTR_ERR(opp);
+- }
+-
+- volt = opp_get_voltage(opp);
+- rcu_read_unlock();
+- volt_old = regulator_get_voltage(arm_reg);
+-
+- dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
+- freqs.old / 1000, volt_old / 1000,
+- freqs.new / 1000, volt / 1000);
+-
+- /* scaling up? scale voltage before frequency */
+- if (freqs.new > freqs.old) {
+- ret = regulator_set_voltage_tol(arm_reg, volt, 0);
+- if (ret) {
+- dev_err(cpu_dev,
+- "failed to scale vddarm up: %d\n", ret);
+- return ret;
+- }
+-
+- /*
+- * Need to increase vddpu and vddsoc for safety
+- * if we are about to run at 1.2 GHz.
+- */
+- if (freqs.new == FREQ_1P2_GHZ / 1000) {
+- regulator_set_voltage_tol(pu_reg,
+- PU_SOC_VOLTAGE_HIGH, 0);
+- regulator_set_voltage_tol(soc_reg,
+- PU_SOC_VOLTAGE_HIGH, 0);
+- }
+- }
+-
+- /*
+- * The setpoints are selected per PLL/PDF frequencies, so we need to
+- * reprogram PLL for frequency scaling. The procedure of reprogramming
+- * PLL1 is as below.
+- *
+- * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
+- * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
+- * - Disable pll2_pfd2_396m_clk
+- */
+- clk_prepare_enable(pll2_pfd2_396m_clk);
+- clk_set_parent(step_clk, pll2_pfd2_396m_clk);
+- clk_set_parent(pll1_sw_clk, step_clk);
+- if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
+- clk_set_rate(pll1_sys_clk, freqs.new * 1000);
+- /*
+- * If we are leaving 396 MHz set-point, we need to enable
+- * pll1_sys_clk and disable pll2_pfd2_396m_clk to keep
+- * their use count correct.
+- */
+- if (freqs.old * 1000 <= clk_get_rate(pll2_pfd2_396m_clk)) {
+- clk_prepare_enable(pll1_sys_clk);
+- clk_disable_unprepare(pll2_pfd2_396m_clk);
+- }
+- clk_set_parent(pll1_sw_clk, pll1_sys_clk);
+- clk_disable_unprepare(pll2_pfd2_396m_clk);
+- } else {
+- /*
+- * Disable pll1_sys_clk if pll2_pfd2_396m_clk is sufficient
+- * to provide the frequency.
+- */
+- clk_disable_unprepare(pll1_sys_clk);
+- }
+-
+- /* Ensure the arm clock divider is what we expect */
+- ret = clk_set_rate(arm_clk, freqs.new * 1000);
+- if (ret) {
+- dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
+- regulator_set_voltage_tol(arm_reg, volt_old, 0);
+- return ret;
+- }
+-
+- /* scaling down? scale voltage after frequency */
+- if (freqs.new < freqs.old) {
+- ret = regulator_set_voltage_tol(arm_reg, volt, 0);
+- if (ret)
+- dev_warn(cpu_dev,
+- "failed to scale vddarm down: %d\n", ret);
+-
+- if (freqs.old == FREQ_1P2_GHZ / 1000) {
+- regulator_set_voltage_tol(pu_reg,
+- PU_SOC_VOLTAGE_NORMAL, 0);
+- regulator_set_voltage_tol(soc_reg,
+- PU_SOC_VOLTAGE_NORMAL, 0);
+- }
+- }
+-
+- cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
+-
+- return 0;
+-}
+-
+-static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
+-{
+- int ret;
+-
+- ret = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+- if (ret) {
+- dev_err(cpu_dev, "invalid frequency table: %d\n", ret);
+- return ret;
+- }
+-
+- policy->cpuinfo.transition_latency = transition_latency;
+- policy->cur = clk_get_rate(arm_clk) / 1000;
+- cpumask_setall(policy->cpus);
+- cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+-
+- return 0;
+-}
+-
+-static int imx6q_cpufreq_exit(struct cpufreq_policy *policy)
+-{
+- cpufreq_frequency_table_put_attr(policy->cpu);
+- return 0;
+-}
+-
+-static struct freq_attr *imx6q_cpufreq_attr[] = {
+- &cpufreq_freq_attr_scaling_available_freqs,
+- NULL,
+-};
+-
+-static struct cpufreq_driver imx6q_cpufreq_driver = {
+- .verify = imx6q_verify_speed,
+- .target = imx6q_set_target,
+- .get = imx6q_get_speed,
+- .init = imx6q_cpufreq_init,
+- .exit = imx6q_cpufreq_exit,
+- .name = "imx6q-cpufreq",
+- .attr = imx6q_cpufreq_attr,
+-};
+-
+-static int imx6q_cpufreq_probe(struct platform_device *pdev)
+-{
+- struct device_node *np;
+- struct opp *opp;
+- unsigned long min_volt, max_volt;
+- int num, ret;
+-
+- cpu_dev = &pdev->dev;
+-
+- np = of_find_node_by_path("/cpus/cpu@0");
+- if (!np) {
+- dev_err(cpu_dev, "failed to find cpu0 node\n");
+- return -ENOENT;
+- }
+-
+- cpu_dev->of_node = np;
+-
+- arm_clk = devm_clk_get(cpu_dev, "arm");
+- pll1_sys_clk = devm_clk_get(cpu_dev, "pll1_sys");
+- pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
+- step_clk = devm_clk_get(cpu_dev, "step");
+- pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
+- if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
+- IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
+- dev_err(cpu_dev, "failed to get clocks\n");
+- ret = -ENOENT;
+- goto put_node;
+- }
+-
+- arm_reg = devm_regulator_get(cpu_dev, "arm");
+- pu_reg = devm_regulator_get(cpu_dev, "pu");
+- soc_reg = devm_regulator_get(cpu_dev, "soc");
+- if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
+- dev_err(cpu_dev, "failed to get regulators\n");
+- ret = -ENOENT;
+- goto put_node;
+- }
+-
+- /* We expect an OPP table supplied by platform */
+- num = opp_get_opp_count(cpu_dev);
+- if (num < 0) {
+- ret = num;
+- dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
+- goto put_node;
+- }
+-
+- ret = opp_init_cpufreq_table(cpu_dev, &freq_table);
+- if (ret) {
+- dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
+- goto put_node;
+- }
+-
+- if (of_property_read_u32(np, "clock-latency", &transition_latency))
+- transition_latency = CPUFREQ_ETERNAL;
+-
+- /*
+- * OPP is maintained in order of increasing frequency, and
+- * freq_table initialised from OPP is therefore sorted in the
+- * same order.
+- */
+- rcu_read_lock();
+- opp = opp_find_freq_exact(cpu_dev,
+- freq_table[0].frequency * 1000, true);
+- min_volt = opp_get_voltage(opp);
+- opp = opp_find_freq_exact(cpu_dev,
+- freq_table[--num].frequency * 1000, true);
+- max_volt = opp_get_voltage(opp);
+- rcu_read_unlock();
+- ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
+- if (ret > 0)
+- transition_latency += ret * 1000;
+-
+- /* Count vddpu and vddsoc latency in for 1.2 GHz support */
+- if (freq_table[num].frequency == FREQ_1P2_GHZ / 1000) {
+- ret = regulator_set_voltage_time(pu_reg, PU_SOC_VOLTAGE_NORMAL,
+- PU_SOC_VOLTAGE_HIGH);
+- if (ret > 0)
+- transition_latency += ret * 1000;
+- ret = regulator_set_voltage_time(soc_reg, PU_SOC_VOLTAGE_NORMAL,
+- PU_SOC_VOLTAGE_HIGH);
+- if (ret > 0)
+- transition_latency += ret * 1000;
+- }
+-
+- ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
+- if (ret) {
+- dev_err(cpu_dev, "failed register driver: %d\n", ret);
+- goto free_freq_table;
+- }
+-
+- of_node_put(np);
+- return 0;
+-
+-free_freq_table:
+- opp_free_cpufreq_table(cpu_dev, &freq_table);
+-put_node:
+- of_node_put(np);
+- return ret;
+-}
+-
+-static int imx6q_cpufreq_remove(struct platform_device *pdev)
+-{
+- cpufreq_unregister_driver(&imx6q_cpufreq_driver);
+- opp_free_cpufreq_table(cpu_dev, &freq_table);
+-
+- return 0;
+-}
+-
+-static struct platform_driver imx6q_cpufreq_platdrv = {
+- .driver = {
+- .name = "imx6q-cpufreq",
+- .owner = THIS_MODULE,
+- },
+- .probe = imx6q_cpufreq_probe,
+- .remove = imx6q_cpufreq_remove,
+-};
+-module_platform_driver(imx6q_cpufreq_platdrv);
+-
+-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
+-MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/Kconfig linux-linaro-stable-mx6/drivers/cpufreq/Kconfig
+--- linux-3.10.30.orig/drivers/cpufreq/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/Kconfig 2014-05-15 20:33:46.805933197 +0200
+@@ -102,6 +102,18 @@
+ Be aware that not all cpufreq drivers support the conservative
+ governor. If unsure have a look at the help section of the
+ driver. Fallback governor will be the performance governor.
++
++config CPU_FREQ_DEFAULT_GOV_INTERACTIVE
++ bool "interactive"
++ select CPU_FREQ_GOV_INTERACTIVE
++ select CPU_FREQ_GOV_PERFORMANCE
++ help
++ Use the CPUFreq governor 'interactive' as default. This allows
++ you to get a full dynamic cpu frequency capable system by simply
++ loading your cpufreq low-level hardware driver, using the
++ 'interactive' governor for latency-sensitive workloads. Fallback
++ governor will be the performance governor.
++
+ endchoice
+
+ config CPU_FREQ_GOV_PERFORMANCE
+@@ -184,6 +196,23 @@
+
+ If in doubt, say N.
+
++config CPU_FREQ_GOV_INTERACTIVE
++ tristate "'interactive' cpufreq policy governor"
++ help
++ 'interactive' - This driver adds a dynamic cpufreq policy governor
++ designed for latency-sensitive workloads.
++
++ This governor attempts to reduce the latency of clock
++ increases so that the system is more responsive to
++ interactive workloads.
++
++ To compile this driver as a module, choose M here: the
++ module will be called cpufreq_interactive.
++
++ For details, take a look at linux/Documentation/cpu-freq.
++
++ If in doubt, say N.
++
+ config GENERIC_CPUFREQ_CPU0
+ tristate "Generic CPU0 cpufreq driver"
+ depends on HAVE_CLK && REGULATOR && PM_OPP && OF
+@@ -201,7 +230,7 @@
+ endmenu
+
+ menu "ARM CPU frequency scaling drivers"
+-depends on ARM
++depends on ARM || ARM64
+ source "drivers/cpufreq/Kconfig.arm"
+ endmenu
+
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/Kconfig.arm linux-linaro-stable-mx6/drivers/cpufreq/Kconfig.arm
+--- linux-3.10.30.orig/drivers/cpufreq/Kconfig.arm 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/Kconfig.arm 2014-05-15 20:33:46.805933197 +0200
+@@ -4,7 +4,7 @@
+
+ config ARM_BIG_LITTLE_CPUFREQ
+ tristate "Generic ARM big LITTLE CPUfreq driver"
+- depends on ARM_CPU_TOPOLOGY && PM_OPP && HAVE_CLK
++ depends on ARM_CPU_TOPOLOGY && PM_OPP && HAVE_CLK && BIG_LITTLE
+ help
+ This enables the Generic CPUfreq driver for ARM big.LITTLE platforms.
+
+@@ -15,6 +15,14 @@
+ This enables probing via DT for Generic CPUfreq driver for ARM
+ big.LITTLE platform. This gets frequency tables from DT.
+
++config ARM_VEXPRESS_BL_CPUFREQ
++ tristate "ARM Vexpress big LITTLE CPUfreq driver"
++ select ARM_BIG_LITTLE_CPUFREQ
++ depends on VEXPRESS_SPC
++ help
++ This enables the CPUfreq driver for ARM Vexpress big.LITTLE platform.
++ If in doubt, say N.
++
+ config ARM_EXYNOS_CPUFREQ
+ bool "SAMSUNG EXYNOS SoCs"
+ depends on ARCH_EXYNOS
+@@ -67,12 +75,12 @@
+
+ If in doubt, say N.
+
+-config ARM_IMX6Q_CPUFREQ
+- tristate "Freescale i.MX6Q cpufreq support"
+- depends on SOC_IMX6Q
++config ARM_IMX6_CPUFREQ
++ tristate "Freescale i.MX6 cpufreq support"
++ depends on SOC_IMX6Q || SOC_IMX6SL
+ depends on REGULATOR_ANATOP
+ help
+- This adds cpufreq driver support for Freescale i.MX6Q SOC.
++ This adds cpufreq driver support for Freescale i.MX6 series SOC.
+
+ If in doubt, say N.
+
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/Makefile linux-linaro-stable-mx6/drivers/cpufreq/Makefile
+--- linux-3.10.30.orig/drivers/cpufreq/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/Makefile 2014-05-15 20:33:46.805933197 +0200
+@@ -9,6 +9,7 @@
+ obj-$(CONFIG_CPU_FREQ_GOV_USERSPACE) += cpufreq_userspace.o
+ obj-$(CONFIG_CPU_FREQ_GOV_ONDEMAND) += cpufreq_ondemand.o
+ obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE) += cpufreq_conservative.o
++obj-$(CONFIG_CPU_FREQ_GOV_INTERACTIVE) += cpufreq_interactive.o
+ obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o
+
+ # CPUfreq cross-arch helpers
+@@ -48,6 +49,7 @@
+ obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ) += arm_big_little.o
+ # big LITTLE per platform glues. Keep DT_BL_CPUFREQ as the last entry in all big
+ # LITTLE drivers, so that it is probed last.
++obj-$(CONFIG_ARM_VEXPRESS_BL_CPUFREQ) += vexpress_big_little.o
+ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o
+
+ obj-$(CONFIG_ARCH_DAVINCI_DA850) += davinci-cpufreq.o
+@@ -58,7 +60,7 @@
+ obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
+ obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
+ obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
+-obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
++obj-$(CONFIG_ARM_IMX6_CPUFREQ) += cpufreq-imx6.o
+ obj-$(CONFIG_ARM_INTEGRATOR) += integrator-cpufreq.o
+ obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
+ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
+diff -Nur linux-3.10.30.orig/drivers/cpufreq/vexpress_big_little.c linux-linaro-stable-mx6/drivers/cpufreq/vexpress_big_little.c
+--- linux-3.10.30.orig/drivers/cpufreq/vexpress_big_little.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpufreq/vexpress_big_little.c 2014-05-15 20:33:46.841933457 +0200
+@@ -0,0 +1,86 @@
++/*
++ * Vexpress big.LITTLE CPUFreq Interface driver
++ *
++ * It provides necessary ops to arm_big_little cpufreq driver and gets
++ * Frequency information from Device Tree. Freq table in DT must be in KHz.
++ *
++ * Copyright (C) 2013 Linaro.
++ * Viresh Kumar <viresh.kumar@linaro.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/cpufreq.h>
++#include <linux/export.h>
++#include <linux/opp.h>
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/vexpress.h>
++#include "arm_big_little.h"
++
++static int vexpress_init_opp_table(struct device *cpu_dev)
++{
++ int i = -1, count, cluster = cpu_to_cluster(cpu_dev->id);
++ u32 *table;
++ int ret;
++
++ count = vexpress_spc_get_freq_table(cluster, &table);
++ if (!table || !count) {
++ pr_err("SPC controller returned invalid freq table");
++ return -EINVAL;
++ }
++
++ while (++i < count) {
++ /* FIXME: Voltage value */
++ ret = opp_add(cpu_dev, table[i] * 1000, 900000);
++ if (ret) {
++ dev_warn(cpu_dev, "%s: Failed to add OPP %d, err: %d\n",
++ __func__, table[i] * 1000, ret);
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static int vexpress_get_transition_latency(struct device *cpu_dev)
++{
++ /* 1 ms */
++ return 1000000;
++}
++
++static struct cpufreq_arm_bL_ops vexpress_bL_ops = {
++ .name = "vexpress-bL",
++ .get_transition_latency = vexpress_get_transition_latency,
++ .init_opp_table = vexpress_init_opp_table,
++};
++
++static int vexpress_bL_init(void)
++{
++ if (!vexpress_spc_check_loaded()) {
++ pr_info("%s: No SPC found\n", __func__);
++ return -ENOENT;
++ }
++
++ return bL_cpufreq_register(&vexpress_bL_ops);
++}
++module_init(vexpress_bL_init);
++
++static void vexpress_bL_exit(void)
++{
++ return bL_cpufreq_unregister(&vexpress_bL_ops);
++}
++module_exit(vexpress_bL_exit);
++
++MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
++MODULE_DESCRIPTION("ARM Vexpress big LITTLE cpufreq driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/cpuidle/arm_big_little.c linux-linaro-stable-mx6/drivers/cpuidle/arm_big_little.c
+--- linux-3.10.30.orig/drivers/cpuidle/arm_big_little.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpuidle/arm_big_little.c 2014-05-15 20:33:46.841933457 +0200
+@@ -0,0 +1,183 @@
++/*
++ * big.LITTLE CPU idle driver.
++ *
++ * Copyright (C) 2012 ARM Ltd.
++ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/arm-cci.h>
++#include <linux/bitmap.h>
++#include <linux/cpuidle.h>
++#include <linux/cpu_pm.h>
++#include <linux/clockchips.h>
++#include <linux/debugfs.h>
++#include <linux/hrtimer.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/tick.h>
++#include <linux/vexpress.h>
++#include <asm/mcpm.h>
++#include <asm/cpuidle.h>
++#include <asm/cputype.h>
++#include <asm/idmap.h>
++#include <asm/proc-fns.h>
++#include <asm/suspend.h>
++#include <linux/of.h>
++
++static int bl_cpuidle_simple_enter(struct cpuidle_device *dev,
++ struct cpuidle_driver *drv, int index)
++{
++ ktime_t time_start, time_end;
++ s64 diff;
++
++ time_start = ktime_get();
++
++ cpu_do_idle();
++
++ time_end = ktime_get();
++
++ local_irq_enable();
++
++ diff = ktime_to_us(ktime_sub(time_end, time_start));
++ if (diff > INT_MAX)
++ diff = INT_MAX;
++
++ dev->last_residency = (int) diff;
++
++ return index;
++}
++
++static int bl_enter_powerdown(struct cpuidle_device *dev,
++ struct cpuidle_driver *drv, int idx);
++
++static struct cpuidle_state bl_cpuidle_set[] __initdata = {
++ [0] = {
++ .enter = bl_cpuidle_simple_enter,
++ .exit_latency = 1,
++ .target_residency = 1,
++ .power_usage = UINT_MAX,
++ .flags = CPUIDLE_FLAG_TIME_VALID,
++ .name = "WFI",
++ .desc = "ARM WFI",
++ },
++ [1] = {
++ .enter = bl_enter_powerdown,
++ .exit_latency = 300,
++ .target_residency = 1000,
++ .flags = CPUIDLE_FLAG_TIME_VALID,
++ .name = "C1",
++ .desc = "ARM power down",
++ },
++};
++
++struct cpuidle_driver bl_idle_driver = {
++ .name = "bl_idle",
++ .owner = THIS_MODULE,
++ .safe_state_index = 0
++};
++
++static DEFINE_PER_CPU(struct cpuidle_device, bl_idle_dev);
++
++static int notrace bl_powerdown_finisher(unsigned long arg)
++{
++ unsigned int mpidr = read_cpuid_mpidr();
++ unsigned int cluster = (mpidr >> 8) & 0xf;
++ unsigned int cpu = mpidr & 0xf;
++
++ mcpm_set_entry_vector(cpu, cluster, cpu_resume);
++ mcpm_cpu_suspend(0); /* 0 should be replaced with better value here */
++ return 1;
++}
++
++/*
++ * bl_enter_powerdown - Programs CPU to enter the specified state
++ * @dev: cpuidle device
++ * @drv: The target state to be programmed
++ * @idx: state index
++ *
++ * Called from the CPUidle framework to program the device to the
++ * specified target state selected by the governor.
++ */
++static int bl_enter_powerdown(struct cpuidle_device *dev,
++ struct cpuidle_driver *drv, int idx)
++{
++ struct timespec ts_preidle, ts_postidle, ts_idle;
++ int ret;
++
++ /* Used to keep track of the total time in idle */
++ getnstimeofday(&ts_preidle);
++
++ BUG_ON(!irqs_disabled());
++
++ cpu_pm_enter();
++
++ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
++
++ ret = cpu_suspend((unsigned long) dev, bl_powerdown_finisher);
++ if (ret)
++ BUG();
++
++ mcpm_cpu_powered_up();
++
++ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
++
++ cpu_pm_exit();
++
++ getnstimeofday(&ts_postidle);
++ local_irq_enable();
++ ts_idle = timespec_sub(ts_postidle, ts_preidle);
++
++ dev->last_residency = ts_idle.tv_nsec / NSEC_PER_USEC +
++ ts_idle.tv_sec * USEC_PER_SEC;
++ return idx;
++}
++
++/*
++ * bl_idle_init
++ *
++ * Registers the bl specific cpuidle driver with the cpuidle
++ * framework with the valid set of states.
++ */
++int __init bl_idle_init(void)
++{
++ struct cpuidle_device *dev;
++ int i, cpu_id;
++ struct cpuidle_driver *drv = &bl_idle_driver;
++
++ if (!of_find_compatible_node(NULL, NULL, "arm,generic")) {
++ pr_info("%s: No compatible node found\n", __func__);
++ return -ENODEV;
++ }
++
++ drv->state_count = (sizeof(bl_cpuidle_set) /
++ sizeof(struct cpuidle_state));
++
++ for (i = 0; i < drv->state_count; i++) {
++ memcpy(&drv->states[i], &bl_cpuidle_set[i],
++ sizeof(struct cpuidle_state));
++ }
++
++ cpuidle_register_driver(drv);
++
++ for_each_cpu(cpu_id, cpu_online_mask) {
++ pr_err("CPUidle for CPU%d registered\n", cpu_id);
++ dev = &per_cpu(bl_idle_dev, cpu_id);
++ dev->cpu = cpu_id;
++
++ dev->state_count = drv->state_count;
++
++ if (cpuidle_register_device(dev)) {
++ printk(KERN_ERR "%s: Cpuidle register device failed\n",
++ __func__);
++ return -EIO;
++ }
++ }
++
++ return 0;
++}
++
++device_initcall(bl_idle_init);
+diff -Nur linux-3.10.30.orig/drivers/cpuidle/cpuidle-calxeda.c linux-linaro-stable-mx6/drivers/cpuidle/cpuidle-calxeda.c
+--- linux-3.10.30.orig/drivers/cpuidle/cpuidle-calxeda.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpuidle/cpuidle-calxeda.c 2014-05-15 20:33:46.841933457 +0200
+@@ -37,20 +37,6 @@
+ extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
+ extern void *scu_base_addr;
+
+-static inline unsigned int get_auxcr(void)
+-{
+- unsigned int val;
+- asm("mrc p15, 0, %0, c1, c0, 1 @ get AUXCR" : "=r" (val) : : "cc");
+- return val;
+-}
+-
+-static inline void set_auxcr(unsigned int val)
+-{
+- asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
+- : : "r" (val) : "cc");
+- isb();
+-}
+-
+ static noinline void calxeda_idle_restore(void)
+ {
+ set_cr(get_cr() | CR_C);
+diff -Nur linux-3.10.30.orig/drivers/cpuidle/Kconfig linux-linaro-stable-mx6/drivers/cpuidle/Kconfig
+--- linux-3.10.30.orig/drivers/cpuidle/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpuidle/Kconfig 2014-05-15 20:33:46.841933457 +0200
+@@ -20,7 +20,7 @@
+
+ config CPU_IDLE_GOV_LADDER
+ bool
+- depends on CPU_IDLE
++ depends on CPU_IDLE && !NO_HZ
+ default y
+
+ config CPU_IDLE_GOV_MENU
+diff -Nur linux-3.10.30.orig/drivers/cpuidle/Makefile linux-linaro-stable-mx6/drivers/cpuidle/Makefile
+--- linux-3.10.30.orig/drivers/cpuidle/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/cpuidle/Makefile 2014-05-15 20:33:46.841933457 +0200
+@@ -4,6 +4,6 @@
+
+ obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
+ obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
+-
++obj-$(CONFIG_BIG_LITTLE) += arm_big_little.o
+ obj-$(CONFIG_CPU_IDLE_CALXEDA) += cpuidle-calxeda.o
+ obj-$(CONFIG_ARCH_KIRKWOOD) += cpuidle-kirkwood.o
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/caamalg.c linux-linaro-stable-mx6/drivers/crypto/caam/caamalg.c
+--- linux-3.10.30.orig/drivers/crypto/caam/caamalg.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/caamalg.c 2014-05-15 20:33:46.849933515 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for crypto API
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ *
+ * Based on talitos crypto API driver.
+ *
+@@ -53,6 +53,7 @@
+ #include "error.h"
+ #include "sg_sw_sec4.h"
+ #include "key_gen.h"
++#include <linux/string.h>
+
+ /*
+ * crypto alg
+@@ -290,6 +291,8 @@
+ desc_bytes(desc), 1);
+ #endif
+
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_enc_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
+ /*
+ * Job Descriptor and Shared Descriptors
+ * must all fit into the 64-word Descriptor h/w Buffer
+@@ -357,6 +360,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_dec_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
+
+ /*
+ * Job Descriptor and Shared Descriptors
+@@ -440,6 +445,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_givenc_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return 0;
+ }
+@@ -523,6 +530,9 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
+ ctx->split_key_pad_len + enckeylen, 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->key_dma,
++ ctx->split_key_pad_len + enckeylen,
++ DMA_TO_DEVICE);
+
+ ctx->enckeylen = enckeylen;
+
+@@ -561,6 +571,7 @@
+ return -ENOMEM;
+ }
+ ctx->enckeylen = keylen;
++ dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE);
+
+ /* ablkcipher_encrypt shared descriptor */
+ desc = ctx->sh_desc_enc;
+@@ -579,10 +590,15 @@
+ /* Propagate errors from shared to job descriptor */
+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+
+- /* Load iv */
+- append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+- LDST_CLASS_1_CCB | tfm->ivsize);
+-
++ /* load IV */
++ if (strncmp(ablkcipher->base.__crt_alg->cra_name, "ctr(aes)", 8) == 0) {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize |
++ (16 << LDST_OFFSET_SHIFT));
++ } else {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize);
++ }
+ /* Load operation */
+ append_operation(desc, ctx->class1_alg_type |
+ OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+@@ -602,6 +618,9 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
+ /* ablkcipher_decrypt shared descriptor */
+ desc = ctx->sh_desc_dec;
+
+@@ -622,11 +641,20 @@
+ set_jump_tgt_here(desc, jump_cmd);
+
+ /* load IV */
+- append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+- LDST_CLASS_1_CCB | tfm->ivsize);
++ if (strncmp(ablkcipher->base.__crt_alg->cra_name, "ctr(aes)", 8) == 0) {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize |
++ (16 << LDST_OFFSET_SHIFT));
+
+- /* Choose operation */
+- append_dec_op1(desc, ctx->class1_alg_type);
++ append_operation(desc, ctx->class1_alg_type |
++ OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
++ } else {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize);
++
++ /* Choose operation */
++ append_dec_op1(desc, ctx->class1_alg_type);
++ }
+
+ /* Perform operation */
+ ablkcipher_append_src_dst(desc);
+@@ -647,6 +675,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return ret;
+ }
+@@ -1154,7 +1184,7 @@
+ dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
+
+ sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
+- DMA_TO_DEVICE, assoc_chained);
++ DMA_BIDIRECTIONAL, assoc_chained);
+ if (likely(req->src == req->dst)) {
+ sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
+ DMA_BIDIRECTIONAL, src_chained);
+@@ -1178,9 +1208,10 @@
+ sec4_sg_len += dst_nents;
+
+ sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1221,6 +1252,8 @@
+ sg_to_sec4_sg_last(req->dst, dst_nents,
+ edesc->sec4_sg + sec4_sg_index, 0);
+ }
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ return edesc;
+ }
+@@ -1336,7 +1369,7 @@
+ dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
+
+ sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
+- DMA_TO_DEVICE, assoc_chained);
++ DMA_BIDIRECTIONAL, assoc_chained);
+ if (likely(req->src == req->dst)) {
+ sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
+ DMA_BIDIRECTIONAL, src_chained);
+@@ -1369,8 +1402,10 @@
+
+ sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
+
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
++
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1412,6 +1447,8 @@
+ sg_to_sec4_sg_last(req->dst, dst_nents,
+ edesc->sec4_sg + sec4_sg_index, 0);
+ }
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ return edesc;
+ }
+@@ -1505,6 +1542,7 @@
+ * If so, include it. If not, create scatterlist.
+ */
+ iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
+ if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
+ iv_contig = true;
+ else
+@@ -1513,7 +1551,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1545,6 +1583,9 @@
+ sec4_sg_bytes, DMA_TO_DEVICE);
+ edesc->iv_dma = iv_dma;
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
+@@ -2008,6 +2049,70 @@
+ },
+ /* ablkcipher descriptor */
+ {
++ .name = "ecb(des)",
++ .driver_name = "ecb-des-caam",
++ .blocksize = DES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = DES_KEY_SIZE,
++ .max_keysize = DES_KEY_SIZE,
++ .ivsize = DES_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_ECB,
++ },
++ {
++ .name = "ecb(arc4)",
++ .driver_name = "ecb-arc4-caam",
++ .blocksize = ARC4_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = ARC4_MIN_KEY_SIZE,
++ .max_keysize = ARC4_MAX_KEY_SIZE,
++ .ivsize = ARC4_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_ARC4 | OP_ALG_AAI_ECB
++ },
++ {
++ .name = "ecb(aes)",
++ .driver_name = "ecb-aes-caam",
++ .blocksize = AES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB,
++ },
++ {
++ .name = "ctr(aes)",
++ .driver_name = "ctr-aes-caam",
++ .blocksize = AES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
++ },
++ {
+ .name = "cbc(aes)",
+ .driver_name = "cbc-aes-caam",
+ .blocksize = AES_BLOCK_SIZE,
+@@ -2024,6 +2129,22 @@
+ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ },
+ {
++ .name = "ecb(des3_ede)",
++ .driver_name = "ecb-des3-caam",
++ .blocksize = DES3_EDE_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = DES3_EDE_KEY_SIZE,
++ .max_keysize = DES3_EDE_KEY_SIZE,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_ECB,
++ },
++ {
+ .name = "cbc(des3_ede)",
+ .driver_name = "cbc-3des-caam",
+ .blocksize = DES3_EDE_BLOCK_SIZE,
+@@ -2079,7 +2200,7 @@
+ * distribute tfms across job rings to ensure in-order
+ * crypto request processing per tfm
+ */
+- ctx->jrdev = priv->jrdev[(tgt_jr / 2) % priv->total_jobrs];
++ ctx->jrdev = priv->algapi_jr[(tgt_jr / 2) % priv->num_jrs_for_algapi];
+
+ /* copy descriptor header template value */
+ ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
+@@ -2116,6 +2237,7 @@
+ struct device *ctrldev;
+ struct caam_drv_private *priv;
+ struct caam_crypto_alg *t_alg, *n;
++ int i, err;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+@@ -2125,21 +2247,33 @@
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+- if (!pdev)
++ if (!pdev) {
++ of_node_put(dev_node);
+ return;
++ }
+
+ ctrldev = &pdev->dev;
+- of_node_put(dev_node);
+ priv = dev_get_drvdata(ctrldev);
+
+- if (!priv->alg_list.next)
++ if (!priv->alg_list.next) {
++ of_node_put(dev_node);
+ return;
++ }
+
+ list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
+ crypto_unregister_alg(&t_alg->crypto_alg);
+ list_del(&t_alg->entry);
+ kfree(t_alg);
+ }
++
++ for (i = 0; i < priv->total_jobrs; i++) {
++ err = caam_jr_deregister(priv->algapi_jr[i]);
++ if (err < 0)
++ break;
++ }
++ kfree(priv->algapi_jr);
++
++ of_node_put(dev_node);
+ }
+
+ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev,
+@@ -2167,8 +2301,12 @@
+ alg->cra_blocksize = template->blocksize;
+ alg->cra_alignmask = 0;
+ alg->cra_ctxsize = sizeof(struct caam_ctx);
+- alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
+- template->type;
++ alg->cra_flags = CRYPTO_ALG_ASYNC | template->type;
++
++#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY
++ alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
++#endif
++
+ switch (template->type) {
+ case CRYPTO_ALG_TYPE_ABLKCIPHER:
+ alg->cra_type = &crypto_ablkcipher_type;
+@@ -2192,9 +2330,11 @@
+ {
+ struct device_node *dev_node;
+ struct platform_device *pdev;
+- struct device *ctrldev;
++ struct device *ctrldev, **jrdev;
+ struct caam_drv_private *priv;
+- int i = 0, err = 0;
++ int i = 0, err = 0, md_limit = 0;
++ int des_inst, aes_inst, md_inst;
++ u64 cha_inst;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+@@ -2204,21 +2344,81 @@
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+- if (!pdev)
++ if (!pdev) {
++ of_node_put(dev_node);
+ return -ENODEV;
++ }
+
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+- of_node_put(dev_node);
+
+ INIT_LIST_HEAD(&priv->alg_list);
+
++ jrdev = kmalloc(sizeof(*jrdev) * priv->total_jobrs, GFP_KERNEL);
++ if (!jrdev) {
++ of_node_put(dev_node);
++ return -ENOMEM;
++ }
++
++ for (i = 0; i < priv->total_jobrs; i++) {
++ err = caam_jr_register(ctrldev, &jrdev[i]);
++ if (err < 0)
++ break;
++ }
++ if (err < 0 && i == 0) {
++ dev_err(ctrldev, "algapi error in job ring registration: %d\n",
++ err);
++ of_node_put(dev_node);
++ kfree(jrdev);
++ return err;
++ }
++
++ priv->num_jrs_for_algapi = i;
++ priv->algapi_jr = jrdev;
+ atomic_set(&priv->tfm_count, -1);
+
+- /* register crypto algorithms the device supports */
++ /*
++ * register crypto algorithms the device supports
++ * first, detect presence of DES, AES, and MD blocks. If MD present,
++ * determine limit of supported digest size
++ */
++ cha_inst = rd_reg64(&priv->ctrl->perfmon.cha_num);
++ des_inst = (cha_inst & CHA_ID_DES_MASK) >> CHA_ID_DES_SHIFT;
++ aes_inst = (cha_inst & CHA_ID_AES_MASK) >> CHA_ID_AES_SHIFT;
++ md_inst = (cha_inst & CHA_ID_MD_MASK) >> CHA_ID_MD_SHIFT;
++ if (md_inst) {
++ md_limit = SHA512_DIGEST_SIZE;
++ if ((rd_reg64(&priv->ctrl->perfmon.cha_id) & CHA_ID_MD_MASK)
++ == CHA_ID_MD_LP256) /* LP256 limits digest size */
++ md_limit = SHA256_DIGEST_SIZE;
++ }
++
+ for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
+- /* TODO: check if h/w supports alg */
+ struct caam_crypto_alg *t_alg;
++ bool done = false;
++
++authencesn:
++ /*
++ * All registrable algs in this module require a blockcipher
++ * All aead algs require message digests, so check them for
++ * instantiation and size.
++ */
++ if (driver_algs[i].type == CRYPTO_ALG_TYPE_AEAD) {
++ /* If no MD instantiated, or MD too small, skip */
++ if ((!md_inst) ||
++ (driver_algs[i].template_aead.maxauthsize >
++ md_limit))
++ continue;
++ }
++ /* If DES alg, and CHA not instantiated, skip */
++ if ((driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_3DES) ||
++ (driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_DES))
++ if (!des_inst)
++ continue;
++ /* If AES alg, and CHA not instantiated, skip */
++ if (driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_AES)
++ if (!aes_inst)
++ continue;
+
+ t_alg = caam_alg_alloc(ctrldev, &driver_algs[i]);
+ if (IS_ERR(t_alg)) {
+@@ -2233,13 +2433,35 @@
+ dev_warn(ctrldev, "%s alg registration failed\n",
+ t_alg->crypto_alg.cra_driver_name);
+ kfree(t_alg);
+- } else
++ } else {
+ list_add_tail(&t_alg->entry, &priv->alg_list);
++ dev_info(ctrldev, "%s\n",
++ t_alg->crypto_alg.cra_driver_name);
++
++ if (driver_algs[i].type == CRYPTO_ALG_TYPE_AEAD &&
++ !memcmp(driver_algs[i].name, "authenc", 7) &&
++ !done) {
++ char *name;
++
++ name = driver_algs[i].name;
++ memmove(name + 10, name + 7, strlen(name) - 7);
++ memcpy(name + 7, "esn", 3);
++
++ name = driver_algs[i].driver_name;
++ memmove(name + 10, name + 7, strlen(name) - 7);
++ memcpy(name + 7, "esn", 3);
++
++ done = true;
++ goto authencesn;
++ }
++ }
+ }
++
+ if (!list_empty(&priv->alg_list))
+ dev_info(ctrldev, "%s algorithms registered in /proc/crypto\n",
+ (char *)of_get_property(dev_node, "compatible", NULL));
+
++ of_node_put(dev_node);
+ return err;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/caamhash.c linux-linaro-stable-mx6/drivers/crypto/caam/caamhash.c
+--- linux-3.10.30.orig/drivers/crypto/caam/caamhash.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/caamhash.c 2014-05-15 20:33:46.849933515 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for ahash functions of crypto API
+ *
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * Based on caamalg.c crypto API driver.
+ *
+@@ -62,6 +62,7 @@
+ #include "error.h"
+ #include "sg_sw_sec4.h"
+ #include "key_gen.h"
++#include <linux/string.h>
+
+ #define CAAM_CRA_PRIORITY 3000
+
+@@ -116,6 +117,7 @@
+ u8 key[CAAM_MAX_HASH_KEY_SIZE];
+ dma_addr_t key_dma;
+ int ctx_len;
++ unsigned int key_len;
+ unsigned int split_key_len;
+ unsigned int split_key_pad_len;
+ };
+@@ -167,6 +169,7 @@
+ dma_addr_t buf_dma;
+
+ buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, buf_dma, buflen, DMA_TO_DEVICE);
+ dma_to_sec4_sg_one(sec4_sg, buf_dma, buflen, 0);
+
+ return buf_dma;
+@@ -209,6 +212,9 @@
+ u32 flag)
+ {
+ state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, ctx_len, flag);
++ if ((flag == DMA_TO_DEVICE) || (flag == DMA_BIDIRECTIONAL))
++ dma_sync_single_for_device(jrdev, state->ctx_dma, ctx_len,
++ flag);
+ dma_to_sec4_sg_one(sec4_sg, state->ctx_dma, ctx_len, 0);
+ }
+
+@@ -220,6 +226,13 @@
+ KEY_DEST_MDHA_SPLIT | KEY_ENC);
+ }
+
++static inline void append_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx)
++{
++ append_key_as_imm(desc, ctx->key, ctx->key_len,
++ ctx->key_len, CLASS_1 |
++ KEY_DEST_CLASS_REG);
++}
++
+ /* Append key if it has been set */
+ static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
+ {
+@@ -241,6 +254,25 @@
+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+ }
+
++static inline void init_sh_desc_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx)
++{
++ u32 *key_jump_cmd;
++
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++ if (ctx->key_len) {
++ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++ JUMP_COND_SHRD);
++
++ append_key_axcbc(desc, ctx);
++
++ set_jump_tgt_here(desc, key_jump_cmd);
++ }
++
++ /* Propagate errors from shared to job descriptor */
++ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
++
++}
+ /*
+ * For ahash read data from seqin following state->caam_ctx,
+ * and write resulting class2 context to seqout, which may be state->caam_ctx
+@@ -260,6 +292,20 @@
+ LDST_SRCDST_BYTE_CONTEXT);
+ }
+
++static inline void axcbc_append_load_str(u32 *desc, int digestsize)
++{
++ /* Calculate remaining bytes to read */
++ append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++ /* Read remaining bytes */
++ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_LAST1 |
++ FIFOLD_TYPE_MSG | KEY_VLF);
++
++ /* Store class1 context bytes */
++ append_seq_store(desc, digestsize, LDST_CLASS_1_CCB |
++ LDST_SRCDST_BYTE_CONTEXT);
++}
++
+ /*
+ * For ahash update, final and finup, import context, read and write to seqout
+ */
+@@ -282,6 +328,27 @@
+ ahash_append_load_str(desc, digestsize);
+ }
+
++/*
++ * For ahash update, final and finup, import context, read and write to seqout
++ */
++static inline void axcbc_ctx_data_to_out(u32 *desc, u32 op, u32 state,
++ int digestsize,
++ struct caam_hash_ctx *ctx)
++{
++ init_sh_desc_key_axcbc(desc, ctx);
++
++ /* Import context from software */
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | ctx->ctx_len);
++
++ /* Class 1 operation */
++ append_operation(desc, op | state | OP_ALG_ENCRYPT);
++
++ /*
++ * Load from buf and/or src and write to req->result or state->context
++ */
++ axcbc_append_load_str(desc, digestsize);
++}
+ /* For ahash firsts and digest, read and write to seqout */
+ static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state,
+ int digestsize, struct caam_hash_ctx *ctx)
+@@ -297,6 +364,21 @@
+ ahash_append_load_str(desc, digestsize);
+ }
+
++/* For ahash firsts and digest, read and write to seqout */
++static inline void axcbc_data_to_out(u32 *desc, u32 op, u32 state,
++ int digestsize, struct caam_hash_ctx *ctx)
++{
++ init_sh_desc_key_axcbc(desc, ctx);
++
++ /* Class 1 operation */
++ append_operation(desc, op | state | OP_ALG_ENCRYPT);
++
++ /*
++ * Load from buf and/or src and write to req->result or state->context
++ */
++ axcbc_append_load_str(desc, digestsize);
++}
++
+ static int ahash_set_sh_desc(struct crypto_ahash *ahash)
+ {
+ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+@@ -352,6 +434,8 @@
+ print_hex_dump(KERN_ERR, "ahash update first shdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_final shared descriptor */
+ desc = ctx->sh_desc_fin;
+@@ -370,6 +454,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_finup shared descriptor */
+ desc = ctx->sh_desc_finup;
+@@ -388,6 +474,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_digest shared descriptor */
+ desc = ctx->sh_desc_digest;
+@@ -407,10 +495,130 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return 0;
+ }
+
++static int axcbc_set_sh_desc(struct crypto_ahash *ahash)
++{
++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++ int digestsize = crypto_ahash_digestsize(ahash);
++ struct device *jrdev = ctx->jrdev;
++ u32 have_key = 0;
++ u32 *desc;
++
++ /* ahash_update shared descriptor */
++ desc = ctx->sh_desc_update;
++
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++ /* Import context from software */
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | ctx->ctx_len);
++
++ /* Class 1 operation */
++ append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE |
++ OP_ALG_ENCRYPT);
++
++ /* Load data and write to result or context */
++ axcbc_append_load_str(desc, ctx->ctx_len);
++
++ ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash update shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++
++ /* ahash_update_first shared descriptor */
++ desc = ctx->sh_desc_update_first;
++
++ axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT,
++ ctx->ctx_len, ctx);
++
++ ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc,
++ desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash update first shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_final shared descriptor */
++ desc = ctx->sh_desc_fin;
++
++ axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type,
++ OP_ALG_AS_FINALIZE, digestsize, ctx);
++
++ ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash final shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_finup shared descriptor */
++ desc = ctx->sh_desc_finup;
++
++ axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type,
++ OP_ALG_AS_FINALIZE, digestsize, ctx);
++
++ ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash finup shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_digest shared descriptor */
++ desc = ctx->sh_desc_digest;
++
++ axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL,
++ digestsize, ctx);
++
++ ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc,
++ desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash digest shdesc@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ return 0;
++}
+ static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
+ u32 keylen)
+ {
+@@ -444,6 +652,8 @@
+ kfree(desc);
+ return -ENOMEM;
+ }
++ dma_sync_single_for_device(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
++
+ dst_dma = dma_map_single(jrdev, (void *)key_out, digestsize,
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(jrdev, dst_dma)) {
+@@ -487,6 +697,7 @@
+ *keylen = digestsize;
+
+ dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
++ dma_sync_single_for_cpu(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
+
+ kfree(desc);
+@@ -544,6 +755,10 @@
+ dev_err(jrdev, "unable to map key i/o memory\n");
+ return -ENOMEM;
+ }
++
++ dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->split_key_pad_len,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
+@@ -564,6 +779,25 @@
+ return -EINVAL;
+ }
+
++static int axcbc_setkey(struct crypto_ahash *ahash,
++ const u8 *key, unsigned int keylen)
++{
++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++ int ret = 0;
++
++ ctx->key_len = keylen;
++ memcpy(ctx->key, key, keylen);
++
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
++ ctx->key_len, 1);
++#endif
++
++ ret = axcbc_set_sh_desc(ahash);
++
++ return ret;
++}
+ /*
+ * ahash_edesc - s/w-extended ahash descriptor
+ * @dst_dma: physical mapped address of req->result
+@@ -591,8 +825,11 @@
+ if (edesc->src_nents)
+ dma_unmap_sg_chained(dev, req->src, edesc->src_nents,
+ DMA_TO_DEVICE, edesc->chained);
+- if (edesc->dst_dma)
++ if (edesc->dst_dma) {
++ dma_sync_single_for_cpu(dev, edesc->dst_dma, dst_len,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE);
++ }
+
+ if (edesc->sec4_sg_bytes)
+ dma_unmap_single(dev, edesc->sec4_sg_dma,
+@@ -607,8 +844,12 @@
+ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ struct caam_hash_state *state = ahash_request_ctx(req);
+
+- if (state->ctx_dma)
++ if (state->ctx_dma) {
++ if ((flag == DMA_FROM_DEVICE) || (flag == DMA_BIDIRECTIONAL))
++ dma_sync_single_for_cpu(dev, state->ctx_dma,
++ ctx->ctx_len, flag);
+ dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag);
++ }
+ ahash_unmap(dev, edesc, req, dst_len);
+ }
+
+@@ -802,7 +1043,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -851,6 +1092,9 @@
+
+ append_seq_out_ptr(desc, state->ctx_dma, ctx->ctx_len, 0);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+@@ -904,7 +1148,7 @@
+ sec4_sg_bytes = (1 + (buflen ? 1 : 0)) * sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -936,6 +1180,9 @@
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+@@ -980,7 +1227,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1015,6 +1262,9 @@
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+@@ -1055,7 +1305,7 @@
+ sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
+ DESC_JOB_IO_LEN, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1065,6 +1315,7 @@
+ DESC_JOB_IO_LEN;
+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+ sec4_sg_bytes, DMA_TO_DEVICE);
++ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->src_nents = src_nents;
+ edesc->chained = chained;
+
+@@ -1082,6 +1333,9 @@
+ }
+ append_seq_in_ptr(desc, src_dma, req->nbytes, options);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ edesc->sec4_sg_bytes, DMA_TO_DEVICE);
++
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+
+@@ -1120,7 +1374,7 @@
+ int sh_len;
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
+ GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1139,6 +1393,8 @@
+ digestsize);
+ edesc->src_nents = 0;
+
++ dma_sync_single_for_device(jrdev, state->buf_dma, buflen,
++ DMA_TO_DEVICE);
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+@@ -1191,7 +1447,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -1227,6 +1483,8 @@
+
+ map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+@@ -1288,7 +1546,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1320,6 +1578,9 @@
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+@@ -1374,7 +1635,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -1413,6 +1674,8 @@
+
+ map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+@@ -1460,6 +1723,8 @@
+ state->final = ahash_final_no_ctx;
+
+ state->current_buf = 0;
++ state->buflen_0 = 0;
++ state->buflen_1 = 0;
+
+ return 0;
+ }
+@@ -1649,6 +1914,28 @@
+ .alg_type = OP_ALG_ALGSEL_MD5,
+ .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
+ },
++ {
++ .name = "xcbc(aes)",
++ .driver_name = "xcbc-aes-caam",
++ .hmac_name = "xcbc(aes)",
++ .hmac_driver_name = "xcbc-aes-caam",
++ .blocksize = XCBC_MAC_BLOCK_WORDS * 4,
++ .template_ahash = {
++ .init = ahash_init,
++ .update = ahash_update,
++ .final = ahash_final,
++ .finup = ahash_finup,
++ .digest = ahash_digest,
++ .export = ahash_export,
++ .import = ahash_import,
++ .setkey = axcbc_setkey,
++ .halg = {
++ .digestsize = XCBC_MAC_DIGEST_SIZE,
++ },
++ },
++ .alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XCBC_MAC,
++ .alg_op = OP_ALG_ALGSEL_AES,
++ },
+ };
+
+ struct caam_hash_alg {
+@@ -1702,6 +1989,39 @@
+ return ret;
+ }
+
++static int caam_axcbc_cra_init(struct crypto_tfm *tfm)
++{
++ struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
++ struct crypto_alg *base = tfm->__crt_alg;
++ struct hash_alg_common *halg =
++ container_of(base, struct hash_alg_common, base);
++ struct ahash_alg *alg =
++ container_of(halg, struct ahash_alg, halg);
++ struct caam_hash_alg *caam_hash =
++ container_of(alg, struct caam_hash_alg, ahash_alg);
++ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
++ struct caam_drv_private *priv = dev_get_drvdata(caam_hash->ctrldev);
++ int tgt_jr = atomic_inc_return(&priv->tfm_count);
++ int ret = 0;
++
++ /*
++ * distribute tfms across job rings to ensure in-order
++ * crypto request processing per tfm
++ */
++ ctx->jrdev = priv->jrdev[tgt_jr % priv->total_jobrs];
++
++ /* copy descriptor header template value */
++ ctx->alg_type = OP_TYPE_CLASS1_ALG | caam_hash->alg_type;
++ ctx->alg_op = OP_TYPE_CLASS1_ALG | caam_hash->alg_op;
++
++ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
++ sizeof(struct caam_hash_state));
++
++ ret = axcbc_set_sh_desc(ahash);
++
++ return ret;
++}
++
+ static void caam_hash_cra_exit(struct crypto_tfm *tfm)
+ {
+ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
+@@ -1747,21 +2067,26 @@
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+- if (!pdev)
++ if (!pdev) {
++ of_node_put(dev_node);
+ return;
++ }
+
+ ctrldev = &pdev->dev;
+- of_node_put(dev_node);
+ priv = dev_get_drvdata(ctrldev);
+
+- if (!priv->hash_list.next)
++ if (!priv->hash_list.next) {
++ of_node_put(dev_node);
+ return;
++ }
+
+ list_for_each_entry_safe(t_alg, n, &priv->hash_list, entry) {
+ crypto_unregister_ahash(&t_alg->ahash_alg);
+ list_del(&t_alg->entry);
+ kfree(t_alg);
+ }
++
++ of_node_put(dev_node);
+ }
+
+ static struct caam_hash_alg *
+@@ -1794,7 +2119,11 @@
+ template->driver_name);
+ }
+ alg->cra_module = THIS_MODULE;
+- alg->cra_init = caam_hash_cra_init;
++
++ if (strstr(alg->cra_name, "xcbc") > 0)
++ alg->cra_init = caam_axcbc_cra_init;
++ else
++ alg->cra_init = caam_hash_cra_init;
+ alg->cra_exit = caam_hash_cra_exit;
+ alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
+ alg->cra_priority = CAAM_CRA_PRIORITY;
+@@ -1816,7 +2145,8 @@
+ struct platform_device *pdev;
+ struct device *ctrldev;
+ struct caam_drv_private *priv;
+- int i = 0, err = 0;
++ int i = 0, err = 0, md_limit = 0, md_inst;
++ u64 cha_inst;
+
+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
+ if (!dev_node) {
+@@ -1826,22 +2156,36 @@
+ }
+
+ pdev = of_find_device_by_node(dev_node);
+- if (!pdev)
++ if (!pdev) {
++ of_node_put(dev_node);
+ return -ENODEV;
+-
++ }
+ ctrldev = &pdev->dev;
+ priv = dev_get_drvdata(ctrldev);
+- of_node_put(dev_node);
+
+ INIT_LIST_HEAD(&priv->hash_list);
+
+ atomic_set(&priv->tfm_count, -1);
+
+- /* register crypto algorithms the device supports */
++ /* register algorithms the device supports */
++ cha_inst = rd_reg64(&priv->ctrl->perfmon.cha_num);
++ md_inst = (cha_inst & CHA_ID_MD_MASK) >> CHA_ID_MD_SHIFT;
++ if (md_inst) {
++ md_limit = SHA512_DIGEST_SIZE;
++ if ((rd_reg64(&priv->ctrl->perfmon.cha_id) & CHA_ID_MD_MASK)
++ == CHA_ID_MD_LP256) /* LP256 limits digest size */
++ md_limit = SHA256_DIGEST_SIZE;
++ }
++
+ for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
+- /* TODO: check if h/w supports alg */
+ struct caam_hash_alg *t_alg;
+
++ /* If no MD instantiated, or MD too small, skip */
++ if ((!md_inst) ||
++ (driver_hash[i].template_ahash.halg.digestsize >
++ md_limit))
++ continue;
++
+ /* register hmac version */
+ t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], true);
+ if (IS_ERR(t_alg)) {
+@@ -1877,6 +2221,7 @@
+ list_add_tail(&t_alg->entry, &priv->hash_list);
+ }
+
++ of_node_put(dev_node);
+ return err;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/caamrng.c linux-linaro-stable-mx6/drivers/crypto/caam/caamrng.c
+--- linux-3.10.30.orig/drivers/crypto/caam/caamrng.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/caamrng.c 2014-05-15 20:33:46.849933515 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for hw_random
+ *
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * Based on caamalg.c crypto API driver.
+ *
+@@ -76,13 +76,16 @@
+ struct buf_data bufs[2];
+ };
+
+-static struct caam_rng_ctx rng_ctx;
++static struct caam_rng_ctx *rng_ctx;
+
+ static inline void rng_unmap_buf(struct device *jrdev, struct buf_data *bd)
+ {
+- if (bd->addr)
++ if (bd->addr) {
++ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, bd->addr, RN_BUF_SIZE,
+ DMA_FROM_DEVICE);
++ }
+ }
+
+ static inline void rng_unmap_ctx(struct caam_rng_ctx *ctx)
+@@ -137,7 +140,7 @@
+
+ static int caam_read(struct hwrng *rng, void *data, size_t max, bool wait)
+ {
+- struct caam_rng_ctx *ctx = &rng_ctx;
++ struct caam_rng_ctx *ctx = rng_ctx;
+ struct buf_data *bd = &ctx->bufs[ctx->current_buf];
+ int next_buf_idx, copied_idx;
+ int err;
+@@ -206,6 +209,9 @@
+
+ ctx->sh_desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
+ DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "rng shdesc@: ", DUMP_PREFIX_ADDRESS, 16, 4,
+ desc, desc_bytes(desc), 1);
+@@ -237,13 +243,56 @@
+ struct buf_data *bd;
+
+ for (i = 0; i < 2; i++) {
+- bd = &rng_ctx.bufs[i];
++ bd = &rng_ctx->bufs[i];
+ if (atomic_read(&bd->empty) == BUF_PENDING)
+ wait_for_completion(&bd->filled);
+ }
+
+- rng_unmap_ctx(&rng_ctx);
++ rng_unmap_ctx(rng_ctx);
++}
++
++#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST
++static inline void test_len(struct hwrng *rng, size_t len, bool wait)
++{
++ u8 *buf;
++ int real_len;
++
++ buf = kzalloc(sizeof(u8) * len, GFP_KERNEL);
++ real_len = rng->read(rng, buf, len, wait);
++ if (real_len == 0 && wait)
++ pr_err("WAITING FAILED\n");
++ pr_info("wanted %d bytes, got %d\n", len, real_len);
++ print_hex_dump(KERN_INFO, "random bytes@: ", DUMP_PREFIX_ADDRESS,
++ 16, 4, buf, real_len, 1);
++ kfree(buf);
++}
++
++static inline void test_mode_once(struct hwrng *rng, bool wait)
++{
++#define TEST_CHUNK (RN_BUF_SIZE / 4)
++
++ test_len(rng, TEST_CHUNK, wait);
++ test_len(rng, RN_BUF_SIZE * 2, wait);
++ test_len(rng, RN_BUF_SIZE * 2 - TEST_CHUNK, wait);
++}
++
++static inline void test_mode(struct hwrng *rng, bool wait)
++{
++#define TEST_PASS 1
++ int i;
++
++ for (i = 0; i < TEST_PASS; i++)
++ test_mode_once(rng, wait);
++}
++
++static void self_test(struct hwrng *rng)
++{
++ pr_info("testing without waiting\n");
++ test_mode(rng, false);
++ pr_info("testing with waiting\n");
++ test_mode(rng, true);
+ }
++#endif
+
+ static void caam_init_buf(struct caam_rng_ctx *ctx, int buf_id)
+ {
+@@ -298,7 +347,17 @@
+ priv = dev_get_drvdata(ctrldev);
+ of_node_put(dev_node);
+
+- caam_init_rng(&rng_ctx, priv->jrdev[0]);
++ /* Check RNG present in hardware before registration */
++ if (!(rd_reg64(&priv->ctrl->perfmon.cha_num) & CHA_ID_RNG_MASK))
++ return -ENODEV;
++
++ rng_ctx = kmalloc(sizeof(struct caam_rng_ctx), GFP_KERNEL | GFP_DMA);
++
++ caam_init_rng(rng_ctx, priv->jrdev[0]);
++
++#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST
++ self_test(&caam_rng);
++#endif
+
+ dev_info(priv->jrdev[0], "registering rng-caam\n");
+ return hwrng_register(&caam_rng);
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/compat.h linux-linaro-stable-mx6/drivers/crypto/caam/compat.h
+--- linux-3.10.30.orig/drivers/crypto/caam/compat.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/compat.h 2014-05-15 20:33:46.849933515 +0200
+@@ -14,6 +14,8 @@
+ #include <linux/hash.h>
+ #include <linux/hw_random.h>
+ #include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/io.h>
+ #include <linux/spinlock.h>
+@@ -23,6 +25,10 @@
+ #include <linux/types.h>
+ #include <linux/debugfs.h>
+ #include <linux/circ_buf.h>
++
++#ifdef CONFIG_ARM /* needs the clock control subsystem */
++#include <linux/clk.h>
++#endif
+ #include <net/xfrm.h>
+
+ #include <crypto/algapi.h>
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/ctrl.c linux-linaro-stable-mx6/drivers/crypto/caam/ctrl.c
+--- linux-3.10.30.orig/drivers/crypto/caam/ctrl.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/ctrl.c 2014-05-15 20:33:46.849933515 +0200
+@@ -2,7 +2,7 @@
+ * CAAM control-plane driver backend
+ * Controller-level driver, kernel property detection, initialization
+ *
+- * Copyright 2008-2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+ #include "compat.h"
+@@ -12,6 +12,10 @@
+ #include "desc_constr.h"
+ #include "error.h"
+ #include "ctrl.h"
++#include "sm.h"
++
++/* Used to capture the array of job rings */
++struct device **caam_jr_dev;
+
+ static int caam_remove(struct platform_device *pdev)
+ {
+@@ -40,6 +44,13 @@
+ /* Unmap controller region */
+ iounmap(&topregs->ctrl);
+
++#ifdef CONFIG_ARM
++ /* shut clocks off before finalizing shutdown */
++ clk_disable(ctrlpriv->caam_ipg);
++ clk_disable(ctrlpriv->caam_mem);
++ clk_disable(ctrlpriv->caam_aclk);
++#endif
++
+ kfree(ctrlpriv->jrdev);
+ kfree(ctrlpriv);
+
+@@ -70,9 +81,13 @@
+ */
+ append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
+
++}
++
++static void generate_secure_keys_desc(u32 *desc)
++{
+ /* generate secure keys (non-test) */
+ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
+- OP_ALG_RNG4_SK);
++ OP_ALG_RNG4_SK);
+ }
+
+ struct instantiate_result {
+@@ -95,7 +110,7 @@
+ complete(&instantiation->completion);
+ }
+
+-static int instantiate_rng(struct device *jrdev)
++static int instantiate_rng(struct device *jrdev, u32 keys_generated)
+ {
+ struct instantiate_result instantiation;
+
+@@ -110,7 +125,14 @@
+ }
+
+ build_instantiation_desc(desc);
++
++ /* If keys have not been generated, add op code to generate key. */
++ if (!keys_generated)
++ generate_secure_keys_desc(desc);
++
+ desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc), DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, desc_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
+ init_completion(&instantiation.completion);
+ ret = caam_jr_enqueue(jrdev, desc, rng4_init_done, &instantiation);
+ if (!ret) {
+@@ -142,16 +164,18 @@
+ topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
+ r4tst = &topregs->ctrl.r4tst[0];
+
++ val = rd_reg32(&r4tst->rtmctl);
+ /* put RNG4 into program mode */
+ setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+- /* 1600 clocks per sample */
++ /* Set clocks per sample to the default, and divider to zero */
+ val = rd_reg32(&r4tst->rtsdctl);
+- val = (val & ~RTSDCTL_ENT_DLY_MASK) | (1600 << RTSDCTL_ENT_DLY_SHIFT);
++ val = (val & ~RTSDCTL_ENT_DLY_MASK) |
++ (RNG4_ENT_CLOCKS_SAMPLE << RTSDCTL_ENT_DLY_SHIFT);
+ wr_reg32(&r4tst->rtsdctl, val);
+ /* min. freq. count */
+- wr_reg32(&r4tst->rtfrqmin, 400);
++ wr_reg32(&r4tst->rtfrqmin, RNG4_ENT_CLOCKS_SAMPLE / 4);
+ /* max. freq. count */
+- wr_reg32(&r4tst->rtfrqmax, 6400);
++ wr_reg32(&r4tst->rtfrqmax, RNG4_ENT_CLOCKS_SAMPLE * 8);
+ /* put RNG4 into run mode */
+ clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+ }
+@@ -176,7 +200,20 @@
+ {0x0A14, 1, 3},
+ {0x0A14, 2, 4},
+ {0x0A16, 1, 4},
+- {0x0A11, 1, 4}
++ {0x0A11, 1, 4},
++ {0x0A10, 3, 4},
++ {0x0A18, 1, 4},
++ {0x0A11, 2, 5},
++ {0x0A12, 2, 5},
++ {0x0A13, 1, 5},
++ {0x0A1C, 1, 5},
++ {0x0A12, 4, 6},
++ {0x0A13, 2, 6},
++ {0x0A16, 2, 6},
++ {0x0A18, 2, 6},
++ {0x0A1A, 1, 6},
++ {0x0A1C, 2, 6},
++ {0x0A17, 1, 6}
+ };
+ int i;
+
+@@ -189,6 +226,18 @@
+ }
+ EXPORT_SYMBOL(caam_get_era);
+
++/*
++ * Return a job ring device. This is available so outside
++ * entities can gain direct access to the job ring. For now,
++ * this function returns the first job ring (at index 0).
++ */
++struct device *caam_get_jrdev(void)
++{
++ return caam_jr_dev[0];
++}
++EXPORT_SYMBOL(caam_get_jrdev);
++
++
+ /* Probe routine for CAAM top (controller) level */
+ static int caam_probe(struct platform_device *pdev)
+ {
+@@ -198,6 +247,7 @@
+ struct device_node *nprop, *np;
+ struct caam_ctrl __iomem *ctrl;
+ struct caam_full __iomem *topregs;
++ struct snvs_full __iomem *snvsregs;
+ struct caam_drv_private *ctrlpriv;
+ #ifdef CONFIG_DEBUG_FS
+ struct caam_perfmon *perfmon;
+@@ -227,6 +277,90 @@
+ /* Get the IRQ of the controller (for security violations only) */
+ ctrlpriv->secvio_irq = of_irq_to_resource(nprop, 0, NULL);
+
++ /* Get SNVS register Page */
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-snvs");
++
++ if (!np)
++ return -ENODEV;
++
++ snvsregs = of_iomap(np, 0);
++ ctrlpriv->snvs = snvsregs;
++ /* Get CAAM-SM node and of_iomap() and save */
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm");
++
++ if (!np)
++ return -ENODEV;
++
++ ctrlpriv->sm_base = of_iomap(np, 0);
++ ctrlpriv->sm_size = 0x3fff;
++
++/*
++ * ARM targets tend to have clock control subsystems that can
++ * enable/disable clocking to our device. Turn clocking on to proceed
++ */
++#ifdef CONFIG_ARM
++ ctrlpriv->caam_ipg = devm_clk_get(&ctrlpriv->pdev->dev, "caam_ipg");
++ if (IS_ERR(ctrlpriv->caam_ipg)) {
++ ret = PTR_ERR(ctrlpriv->caam_ipg);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM ipg clk: %d\n", ret);
++ return -ENODEV;
++ }
++ ctrlpriv->caam_mem = devm_clk_get(&ctrlpriv->pdev->dev, "caam_mem");
++ if (IS_ERR(ctrlpriv->caam_mem)) {
++ ret = PTR_ERR(ctrlpriv->caam_mem);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM secure mem clk: %d\n", ret);
++ return -ENODEV;
++ }
++ ctrlpriv->caam_aclk = devm_clk_get(&ctrlpriv->pdev->dev, "caam_aclk");
++ if (IS_ERR(ctrlpriv->caam_aclk)) {
++ ret = PTR_ERR(ctrlpriv->caam_aclk);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM aclk clk: %d\n", ret);
++ return -ENODEV;
++ }
++
++ ret = clk_prepare(ctrlpriv->caam_ipg);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM ipg clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_prepare(ctrlpriv->caam_mem);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM secure mem clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_prepare(ctrlpriv->caam_aclk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM aclk clock: %d\n", ret);
++ return -ENODEV;
++ }
++
++ ret = clk_enable(ctrlpriv->caam_ipg);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_enable(ctrlpriv->caam_mem);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_enable(ctrlpriv->caam_aclk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
++ return -ENODEV;
++ }
++
++ pr_debug("%s caam_ipg clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_ipg));
++ pr_debug("%s caam_mem clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_mem));
++ pr_debug("%s caam_aclk clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_aclk));
++#endif
++
+ /*
+ * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
+ * long pointers in master configuration register
+@@ -234,6 +368,22 @@
+ setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
+ (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
+
++#ifdef CONFIG_ARCH_MX6
++ /*
++ * ERRATA: mx6 devices have an issue wherein AXI bus transactions
++ * may not occur in the correct order. This isn't a problem running
++ * single descriptors, but can be if running multiple concurrent
++ * descriptors. Reworking the driver to throttle to single requests
++ * is impractical, thus the workaround is to limit the AXI pipeline
++ * to a depth of 1 (from it's default of 4) to preclude this situation
++ * from occurring.
++ */
++ wr_reg32(&topregs->ctrl.mcr,
++ (rd_reg32(&topregs->ctrl.mcr) & ~(MCFGR_AXIPIPE_MASK)) |
++ ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK));
++#endif
++
++ /* Set DMA masks according to platform ranging */
+ if (sizeof(dma_addr_t) == sizeof(u64))
+ if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
+ dma_set_mask(dev, DMA_BIT_MASK(40));
+@@ -265,13 +415,36 @@
+ ring = 0;
+ ctrlpriv->total_jobrs = 0;
+ for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") {
+- caam_jr_probe(pdev, np, ring);
++ ret = caam_jr_probe(pdev, np, ring);
++ if (ret < 0) {
++ /*
++ * Job ring not found, error out. At some
++ * point, we should enhance job ring handling
++ * to allow for non-consecutive job rings to
++ * be found.
++ */
++ pr_err("fsl,sec-v4.0-job-ring not found ");
++ pr_err("(ring %d)\n", ring);
++ return ret;
++ }
+ ctrlpriv->total_jobrs++;
+ ring++;
+ }
++
+ if (!ring) {
+ for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") {
+- caam_jr_probe(pdev, np, ring);
++ ret = caam_jr_probe(pdev, np, ring);
++ if (ret < 0) {
++ /*
++ * Job ring not found, error out. At some
++ * point, we should enhance job ring handling
++ * to allow for non-consecutive job rings to
++ * be found.
++ */
++ pr_err("fsl,sec4.0-job-ring not found ");
++ pr_err("(ring %d)\n", ring);
++ return ret;
++ }
+ ctrlpriv->total_jobrs++;
+ ring++;
+ }
+@@ -294,19 +467,40 @@
+ }
+
+ /*
+- * RNG4 based SECs (v5+) need special initialization prior
+- * to executing any descriptors
++ * RNG4 based SECs (v5+ | >= i.MX6) need special initialization prior
++ * to executing any descriptors. If there's a problem with init,
++ * remove other subsystems and return; internal padding functions
++ * cannot run without an RNG. This procedure assumes a single RNG4
++ * instance.
+ */
+- if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) {
+- kick_trng(pdev);
+- ret = instantiate_rng(ctrlpriv->jrdev[0]);
+- if (ret) {
+- caam_remove(pdev);
+- return ret;
++ if ((rd_reg64(&topregs->ctrl.perfmon.cha_id) & CHA_ID_RNG_MASK)
++ == CHA_ID_RNG_4) {
++ struct rng4tst __iomem *r4tst;
++ u32 rdsta, rng_if, rng_skvn;
++
++ /*
++ * Check to see if the RNG has already been instantiated.
++ * If either the state 0 or 1 instantiated flags are set,
++ * then don't continue on and try to instantiate the RNG
++ * again.
++ */
++ r4tst = &topregs->ctrl.r4tst[0];
++ rdsta = rd_reg32(&r4tst->rdsta); /* Read RDSTA register */
++
++ /* Check IF bit for non-deterministic instantiation */
++ rng_if = rdsta & RDSTA_IF;
++
++ /* Check SKVN bit for non-deterministic key generation */
++ rng_skvn = rdsta & RDSTA_SKVN;
++ if (!rng_if) {
++ kick_trng(pdev);
++ ret = instantiate_rng(ctrlpriv->jrdev[0], rng_skvn);
++ if (ret) {
++ caam_remove(pdev);
++ return -ENODEV;
++ }
++ ctrlpriv->rng_inst++;
+ }
+-
+- /* Enable RDB bit so that RNG works faster */
+- setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
+ }
+
+ /* NOTE: RTIC detection ought to go here, around Si time */
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/desc.h linux-linaro-stable-mx6/drivers/crypto/caam/desc.h
+--- linux-3.10.30.orig/drivers/crypto/caam/desc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/desc.h 2014-05-15 20:33:46.849933515 +0200
+@@ -2,19 +2,35 @@
+ * CAAM descriptor composition header
+ * Definitions to support CAAM descriptor instruction generation
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef DESC_H
+ #define DESC_H
+
++/*
++ * 16-byte hardware scatter/gather table
++ * An 8-byte table exists in the hardware spec, but has never been
++ * implemented to date. The 8/16 option is selected at RTL-compile-time.
++ * and this selection is visible in the Compile Time Parameters Register
++ */
++
++#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */
++#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */
++#define SEC4_SG_BPID_MASK 0x000000ff
++#define SEC4_SG_BPID_SHIFT 16
++#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
++#define SEC4_SG_OFFS_MASK 0x00001fff
++
+ struct sec4_sg_entry {
++#ifdef CONFIG_64BIT
+ u64 ptr;
+-#define SEC4_SG_LEN_FIN 0x40000000
+-#define SEC4_SG_LEN_EXT 0x80000000
++#else
++ u32 reserved;
++ u32 ptr;
++#endif
+ u32 len;
+- u8 reserved;
+- u8 buf_pool_id;
++ u16 buf_pool_id;
+ u16 offset;
+ };
+
+@@ -1087,6 +1103,23 @@
+ #define OP_PCL_PKPROT_ECC 0x0002
+ #define OP_PCL_PKPROT_F2M 0x0001
+
++/* Blob protocol protinfo bits */
++#define OP_PCL_BLOB_TK 0x0200
++#define OP_PCL_BLOB_EKT 0x0100
++
++#define OP_PCL_BLOB_K2KR_MEM 0x0000
++#define OP_PCL_BLOB_K2KR_C1KR 0x0010
++#define OP_PCL_BLOB_K2KR_C2KR 0x0030
++#define OP_PCL_BLOB_K2KR_AFHAS 0x0050
++#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070
++
++#define OP_PCL_BLOB_PTXT_SECMEM 0x0008
++#define OP_PCL_BLOB_BLACK 0x0004
++
++#define OP_PCL_BLOB_FMT_NORMAL 0x0000
++#define OP_PCL_BLOB_FMT_MSTR 0x0002
++#define OP_PCL_BLOB_FMT_TEST 0x0003
++
+ /* For non-protocol/alg-only op commands */
+ #define OP_ALG_TYPE_SHIFT 24
+ #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT)
+@@ -1600,4 +1633,28 @@
+ #define NFIFOENTRY_PLEN_SHIFT 0
+ #define NFIFOENTRY_PLEN_MASK (0xFF << NFIFOENTRY_PLEN_SHIFT)
+
++/*
++ * PDB internal definitions
++ */
++
++/* IPSec ESP CBC Encap/Decap Options */
++#define PDBOPTS_ESPCBC_ARSNONE 0x00 /* no antireplay window */
++#define PDBOPTS_ESPCBC_ARS32 0x40 /* 32-entry antireplay window */
++#define PDBOPTS_ESPCBC_ARS64 0xc0 /* 64-entry antireplay window */
++#define PDBOPTS_ESPCBC_IVSRC 0x20 /* IV comes from internal random gen */
++#define PDBOPTS_ESPCBC_ESN 0x10 /* extended sequence included */
++#define PDBOPTS_ESPCBC_OUTFMT 0x08 /* output only decapsulation (decap) */
++#define PDBOPTS_ESPCBC_IPHDRSRC 0x08 /* IP header comes from PDB (encap) */
++#define PDBOPTS_ESPCBC_INCIPHDR 0x04 /* Prepend IP header to output frame */
++#define PDBOPTS_ESPCBC_IPVSN 0x02 /* process IPv6 header */
++#define PDBOPTS_ESPCBC_TUNNEL 0x01 /* tunnel mode next-header byte */
++
++#define ARC4_BLOCK_SIZE 1
++#define ARC4_MAX_KEY_SIZE 256
++#define ARC4_MIN_KEY_SIZE 1
++
++#define XCBC_MAC_DIGEST_SIZE 16
++#define XCBC_MAC_BLOCK_WORDS 16
++
++
+ #endif /* DESC_H */
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/intern.h linux-linaro-stable-mx6/drivers/crypto/caam/intern.h
+--- linux-3.10.30.orig/drivers/crypto/caam/intern.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/intern.h 2014-05-15 20:33:46.849933515 +0200
+@@ -2,7 +2,7 @@
+ * CAAM/SEC 4.x driver backend
+ * Private/internal definitions between modules
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ *
+ */
+
+@@ -12,6 +12,9 @@
+ #define JOBR_UNASSIGNED 0
+ #define JOBR_ASSIGNED 1
+
++/* Default clock/sample settings for an RNG4 entropy source */
++#define RNG4_ENT_CLOCKS_SAMPLE 1600
++
+ /* Currently comes from Kconfig param as a ^2 (driver-required) */
+ #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE)
+
+@@ -67,6 +70,8 @@
+ struct caam_drv_private {
+
+ struct device *dev;
++ struct device *smdev;
++ struct device *secviodev;
+ struct device **jrdev; /* Alloc'ed array per sub-device */
+ spinlock_t jr_alloc_lock;
+ struct platform_device *pdev;
+@@ -76,6 +81,9 @@
+ struct caam_deco **deco; /* DECO/CCB views */
+ struct caam_assurance *ac;
+ struct caam_queue_if *qi; /* QI control region */
++ struct snvs_full __iomem *snvs; /* SNVS HP+LP register space */
++ dma_addr_t __iomem *sm_base; /* Secure memory storage base */
++ u32 sm_size;
+
+ /*
+ * Detected geometry block. Filled in from device tree if powerpc,
+@@ -84,14 +92,22 @@
+ u8 total_jobrs; /* Total Job Rings in device */
+ u8 qi_present; /* Nonzero if QI present in device */
+ int secvio_irq; /* Security violation interrupt number */
++ int rng_inst; /* Total instantiated RNGs */
+
+ /* which jr allocated to scatterlist crypto */
+ atomic_t tfm_count ____cacheline_aligned;
++ int num_jrs_for_algapi;
++ struct device **algapi_jr;
+ /* list of registered crypto algorithms (mk generic context handle?) */
+ struct list_head alg_list;
+ /* list of registered hash algorithms (mk generic context handle?) */
+ struct list_head hash_list;
+
++#ifdef CONFIG_ARM
++ struct clk *caam_ipg;
++ struct clk *caam_mem;
++ struct clk *caam_aclk;
++#endif
+ /*
+ * debugfs entries for developer view into driver/device
+ * variables at runtime.
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/jr.c linux-linaro-stable-mx6/drivers/crypto/caam/jr.c
+--- linux-3.10.30.orig/drivers/crypto/caam/jr.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/jr.c 2014-05-15 20:33:46.849933515 +0200
+@@ -2,7 +2,7 @@
+ * CAAM/SEC 4.x transport/backend driver
+ * JobR backend functionality
+ *
+- * Copyright 2008-2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+ #include "compat.h"
+@@ -58,6 +58,9 @@
+ void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg);
+ u32 *userdesc, userstatus;
+ void *userarg;
++ dma_addr_t outbusaddr;
++
++ outbusaddr = rd_reg64(&jrp->rregs->outring_base);
+
+ while (rd_reg32(&jrp->rregs->outring_used)) {
+
+@@ -67,6 +70,9 @@
+
+ sw_idx = tail = jrp->tail;
+ hw_idx = jrp->out_ring_read_index;
++ dma_sync_single_for_cpu(dev, outbusaddr,
++ sizeof(struct jr_outentry) * JOBR_DEPTH,
++ DMA_FROM_DEVICE);
+
+ for (i = 0; CIRC_CNT(head, tail + i, JOBR_DEPTH) >= 1; i++) {
+ sw_idx = (tail + i) & (JOBR_DEPTH - 1);
+@@ -94,6 +100,8 @@
+ userdesc = jrp->entinfo[sw_idx].desc_addr_virt;
+ userstatus = jrp->outring[hw_idx].jrstatus;
+
++ smp_mb();
++
+ /* set done */
+ wr_reg32(&jrp->rregs->outring_rmvd, 1);
+
+@@ -227,7 +235,7 @@
+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
+ struct caam_jrentry_info *head_entry;
+ int head, tail, desc_size;
+- dma_addr_t desc_dma;
++ dma_addr_t desc_dma, inpbusaddr;
+
+ desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32);
+ desc_dma = dma_map_single(dev, desc, desc_size, DMA_TO_DEVICE);
+@@ -236,6 +244,13 @@
+ return -EIO;
+ }
+
++ dma_sync_single_for_device(dev, desc_dma, desc_size, DMA_TO_DEVICE);
++
++ inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
++ dma_sync_single_for_device(dev, inpbusaddr,
++ sizeof(dma_addr_t) * JOBR_DEPTH,
++ DMA_TO_DEVICE);
++
+ spin_lock_bh(&jrp->inplock);
+
+ head = jrp->head;
+@@ -257,12 +272,18 @@
+
+ jrp->inpring[jrp->inp_ring_write_index] = desc_dma;
+
++ dma_sync_single_for_device(dev, inpbusaddr,
++ sizeof(dma_addr_t) * JOBR_DEPTH,
++ DMA_TO_DEVICE);
++
+ smp_wmb();
+
+ jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) &
+ (JOBR_DEPTH - 1);
+ jrp->head = (head + 1) & (JOBR_DEPTH - 1);
+
++ wmb();
++
+ wr_reg32(&jrp->rregs->inpring_jobadd, 1);
+
+ spin_unlock_bh(&jrp->inplock);
+@@ -423,7 +444,8 @@
+ struct platform_device *jr_pdev;
+ struct caam_drv_private *ctrlpriv;
+ struct caam_drv_private_jr *jrpriv;
+- u32 *jroffset;
++ const __be32 *jroffset_addr;
++ u32 jroffset;
+ int error;
+
+ ctrldev = &pdev->dev;
+@@ -445,9 +467,21 @@
+ * need to add in the offset to this JobR. Don't know if I
+ * like this long-term, but it'll run
+ */
+- jroffset = (u32 *)of_get_property(np, "reg", NULL);
++ jroffset_addr = of_get_property(np, "reg", NULL);
++
++ if (jroffset_addr == NULL) {
++ kfree(jrpriv);
++ return -EINVAL;
++ }
++
++ /*
++ * Fix the endianness of this value read from the device
++ * tree if running on ARM.
++ */
++ jroffset = be32_to_cpup(jroffset_addr);
++
+ jrpriv->rregs = (struct caam_job_ring __iomem *)((void *)ctrlpriv->ctrl
+- + *jroffset);
++ + jroffset);
+
+ /* Build a local dev for each detected queue */
+ jr_pdev = of_platform_device_create(np, NULL, ctrldev);
+@@ -471,6 +505,10 @@
+
+ /* Identify the interrupt */
+ jrpriv->irq = of_irq_to_resource(np, 0, NULL);
++ if (jrpriv->irq <= 0) {
++ kfree(jrpriv);
++ return -EINVAL;
++ }
+
+ /* Now do the platform independent part */
+ error = caam_jr_init(jrdev); /* now turn on hardware */
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/jr.h linux-linaro-stable-mx6/drivers/crypto/caam/jr.h
+--- linux-3.10.30.orig/drivers/crypto/caam/jr.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/jr.h 2014-05-15 20:33:46.849933515 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM public-level include definitions for the JobR backend
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef JR_H
+@@ -18,4 +18,5 @@
+ extern int caam_jr_probe(struct platform_device *pdev, struct device_node *np,
+ int ring);
+ extern int caam_jr_shutdown(struct device *dev);
++extern struct device *caam_get_jrdev(void);
+ #endif /* JR_H */
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/Kconfig linux-linaro-stable-mx6/drivers/crypto/caam/Kconfig
+--- linux-3.10.30.orig/drivers/crypto/caam/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/Kconfig 2014-05-15 20:33:46.849933515 +0200
+@@ -1,6 +1,6 @@
+ config CRYPTO_DEV_FSL_CAAM
+ tristate "Freescale CAAM-Multicore driver backend"
+- depends on FSL_SOC
++ depends on FSL_SOC || ARCH_MXC
+ help
+ Enables the driver module for Freescale's Cryptographic Accelerator
+ and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
+@@ -98,3 +98,51 @@
+
+ To compile this as a module, choose M here: the module
+ will be called caamrng.
++
++config CRYPTO_DEV_FSL_CAAM_RNG_TEST
++ boolean "Test caam rng"
++ depends on CRYPTO_DEV_FSL_CAAM_RNG_API
++ default n
++ help
++ Selecting this will enable self-test for caam rng.
++
++config CRYPTO_DEV_FSL_CAAM_SM
++ tristate "CAAM Secure Memory / Keystore API (EXPERIMENTAL)"
++ default n
++ help
++ Enables use of a prototype kernel-level Keystore API with CAAM
++ Secure Memory for insertion/extraction of bus-protected secrets.
++
++config CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE
++ int "Size of each keystore slot in Secure Memory"
++ depends on CRYPTO_DEV_FSL_CAAM_SM
++ range 5 9
++ default 7
++ help
++ Select size of allocation units to divide Secure Memory pages into
++ (the size of a "slot" as referenced inside the API code).
++ Established as powers of two.
++ Examples:
++ 5 => 32 bytes
++ 6 => 64 bytes
++ 7 => 128 bytes
++ 8 => 256 bytes
++ 9 => 512 bytes
++
++config CRYPTO_DEV_FSL_CAAM_SM_TEST
++ tristate "CAAM Secure Memory - Keystore Test/Example (EXPERIMENTAL)"
++ depends on CRYPTO_DEV_FSL_CAAM_SM
++ default n
++ help
++ Example thread to exercise the Keystore API and to verify that
++ stored and recovered secrets can be used for general purpose
++ encryption/decryption.
++
++config CRYPTO_DEV_FSL_CAAM_SECVIO
++ tristate "CAAM/SNVS Security Violation Handler (EXPERIMENTAL)"
++ depends on CRYPTO_DEV_FSL_CAAM
++ default n
++ help
++ Enables installation of an interrupt handler with registrable
++ handler functions which can be specified to act on the consequences
++ of a security violation.
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/key_gen.c linux-linaro-stable-mx6/drivers/crypto/caam/key_gen.c
+--- linux-3.10.30.orig/drivers/crypto/caam/key_gen.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/key_gen.c 2014-05-15 20:33:46.849933515 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM/SEC 4.x functions for handling key-generation jobs
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ *
+ */
+ #include "compat.h"
+@@ -68,6 +68,7 @@
+ kfree(desc);
+ return -ENOMEM;
+ }
++ dma_sync_single_for_device(jrdev, dma_addr_in, keylen, DMA_TO_DEVICE);
+ append_key(desc, dma_addr_in, keylen, CLASS_2 | KEY_DEST_CLASS_REG);
+
+ /* Sets MDHA up into an HMAC-INIT */
+@@ -115,7 +116,8 @@
+ split_key_pad_len, 1);
+ #endif
+ }
+-
++ dma_sync_single_for_cpu(jrdev, dma_addr_out, split_key_pad_len,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, dma_addr_out, split_key_pad_len,
+ DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, dma_addr_in, keylen, DMA_TO_DEVICE);
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/Makefile linux-linaro-stable-mx6/drivers/crypto/caam/Makefile
+--- linux-3.10.30.orig/drivers/crypto/caam/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/Makefile 2014-05-15 20:33:46.849933515 +0200
+@@ -6,5 +6,8 @@
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM) += sm_store.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST) += sm_test.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o
+
+ caam-objs := ctrl.o jr.o error.o key_gen.o
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/regs.h linux-linaro-stable-mx6/drivers/crypto/caam/regs.h
+--- linux-3.10.30.orig/drivers/crypto/caam/regs.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/regs.h 2014-05-15 20:33:46.849933515 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM hardware register-level view
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef REGS_H
+@@ -74,15 +74,21 @@
+ #endif
+ #else
+ #ifdef __LITTLE_ENDIAN
+-#define wr_reg32(reg, data) __raw_writel(reg, data)
+-#define rd_reg32(reg) __raw_readl(reg)
++#define wr_reg32(reg, data) writel(data, reg)
++#define rd_reg32(reg) readl(reg)
+ #ifdef CONFIG_64BIT
+-#define wr_reg64(reg, data) __raw_writeq(reg, data)
+-#define rd_reg64(reg) __raw_readq(reg)
++#define wr_reg64(reg, data) writeq(data, reg)
++#define rd_reg64(reg) readq(reg)
+ #endif
+ #endif
+ #endif
+
++#ifdef CONFIG_ARM
++/* These are common macros for Power, put here for ARMs */
++#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
++#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
++#endif
++
+ #ifndef CONFIG_64BIT
+ static inline void wr_reg64(u64 __iomem *reg, u64 data)
+ {
+@@ -107,6 +113,98 @@
+ } __packed;
+
+ /*
++ * CHA version ID / instantiation bitfields
++ * Defined for use within cha_id in perfmon
++ * Note that the same shift/mask selectors can be used to pull out number
++ * of instantiated blocks within cha_num in perfmon, the locations are
++ * the same.
++ */
++
++/* Job Ring */
++#define CHA_ID_JR_SHIFT 60
++#define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT)
++
++/* DEscriptor COntroller */
++#define CHA_ID_DECO_SHIFT 56
++#define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT)
++#define CHA_NUM_DECONUM_SHIFT 56 /* legacy definition */
++#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
++
++/* ZUC-Authentication */
++#define CHA_ID_ZA_SHIFT 44
++#define CHA_ID_ZA_MASK (0xfull << CHA_ID_ZA_SHIFT)
++
++/* ZUC-Encryption */
++#define CHA_ID_ZE_SHIFT 40
++#define CHA_ID_ZE_MASK (0xfull << CHA_ID_ZE_SHIFT)
++
++/* SNOW f9 */
++#define CHA_ID_SNW9_SHIFT 36
++#define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT)
++
++/* CRC */
++#define CHA_ID_CRC_SHIFT 32
++#define CHA_ID_CRC_MASK (0xfull << CHA_ID_CRC_SHIFT)
++
++/* Public Key */
++#define CHA_ID_PK_SHIFT 28
++#define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT)
++
++/* Kasumi */
++#define CHA_ID_KAS_SHIFT 24
++#define CHA_ID_KAS_MASK (0xfull << CHA_ID_KAS_SHIFT)
++
++/* SNOW f8 */
++#define CHA_ID_SNW8_SHIFT 20
++#define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT)
++
++/*
++ * Random Generator
++ * RNG4 = FIPS-verification-compliant, requires init kickstart for use
++ */
++#define CHA_ID_RNG_SHIFT 16
++#define CHA_ID_RNG_MASK (0xfull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_A (0x1ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_B (0x2ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_C (0x3ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_4 (0x4ull << CHA_ID_RNG_SHIFT)
++
++/*
++ * Message Digest
++ * LP256 = Low Power (MD5/SHA1/SHA224/SHA256 + HMAC)
++ * LP512 = Low Power (LP256 + SHA384/SHA512)
++ * HP = High Power (LP512 + SMAC)
++ */
++#define CHA_ID_MD_SHIFT 12
++#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_LP256 (0x0ull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_LP512 (0x1ull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_HP (0x2ull << CHA_ID_MD_SHIFT)
++
++/* ARC4 Streamcipher */
++#define CHA_ID_ARC4_SHIFT 8
++#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
++#define CHA_ID_ARC4_LP (0x0ull << CHA_ID_ARC4_SHIFT)
++#define CHA_ID_ARC4_HP (0x1ull << CHA_ID_ARC4_SHIFT)
++
++/* DES Blockcipher Accelerator */
++#define CHA_ID_DES_SHIFT 4
++#define CHA_ID_DES_MASK (0xfull << CHA_ID_DES_SHIFT)
++
++/*
++ * AES Blockcipher + Combo Mode Accelerator
++ * LP = Low Power (includes ECB/CBC/CFB128/OFB/CTR/CCM/CMAC/XCBC-MAC)
++ * HP = High Power (LP + CBCXCBC/CTRXCBC/XTS/GCM)
++ * DIFFPWR = ORed in if differential-power-analysis resistance implemented
++ */
++#define CHA_ID_AES_SHIFT 0
++#define CHA_ID_AES_MASK (0xfull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_LP (0x3ull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_HP (0x4ull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_DIFFPWR (0x1ull << CHA_ID_AES_SHIFT)
++
++
++/*
+ * caam_perfmon - Performance Monitor/Secure Memory Status/
+ * CAAM Global Status/Component Version IDs
+ *
+@@ -123,6 +221,10 @@
+ u8 min_rev;
+ };
+
++#define SEC_VID_IPID_SHIFT 16
++#define SEC_VID_MAJ_SHIFT 8
++#define SEC_VID_MAJ_MASK 0xFF00
++
+ struct caam_perfmon {
+ /* Performance Monitor Registers f00-f9f */
+ u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
+@@ -139,15 +241,21 @@
+ #define CTPR_QI_SHIFT 57
+ #define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT)
+ u64 comp_parms; /* CTPR - Compile Parameters Register */
+- u64 rsvd1[2];
++
++ /* Secure Memory State Visibility */
++ u32 rsvd1;
++ u32 smstatus; /* Secure memory status */
++ u32 rsvd2;
++ u32 smpartown; /* Secure memory partition owner */
+
+ /* CAAM Global Status fc0-fdf */
+ u64 faultaddr; /* FAR - Fault Address */
+ u32 faultliodn; /* FALR - Fault Address LIODN */
+ u32 faultdetail; /* FADR - Fault Addr Detail */
+- u32 rsvd2;
++ u32 rsvd3;
+ u32 status; /* CSTA - CAAM Status */
+- u64 rsvd3;
++ u32 smpart; /* Secure Memory Partition Parameters */
++ u32 smvid; /* Secure Memory Version ID */
+
+ /* Component Instantiation Parameters fe0-fff */
+ u32 rtic_id; /* RVID - RTIC Version ID */
+@@ -157,6 +265,62 @@
+ u64 caam_id; /* CAAMVID - CAAM Version ID */
+ };
+
++#define SMSTATUS_PART_SHIFT 28
++#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT)
++#define SMSTATUS_PAGE_SHIFT 16
++#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT)
++#define SMSTATUS_MID_SHIFT 8
++#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT)
++#define SMSTATUS_ACCERR_SHIFT 4
++#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT)
++#define SMSTATUS_ACCERR_NONE 0
++#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */
++#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */
++#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */
++#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */
++#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */
++#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */
++#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */
++#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */
++#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */
++#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */
++#define SMSTATUS_STATE_SHIFT 0
++#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT)
++#define SMSTATUS_STATE_RESET 0
++#define SMSTATUS_STATE_INIT 1
++#define SMSTATUS_STATE_NORMAL 2
++#define SMSTATUS_STATE_FAIL 3
++
++/* up to 15 rings, 2 bits shifted by ring number */
++#define SMPARTOWN_RING_SHIFT 2
++#define SMPARTOWN_RING_MASK 3
++#define SMPARTOWN_AVAILABLE 0
++#define SMPARTOWN_NOEXIST 1
++#define SMPARTOWN_UNAVAILABLE 2
++#define SMPARTOWN_OURS 3
++
++/* Maximum number of pages possible */
++#define SMPART_MAX_NUMPG_SHIFT 16
++#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT)
++
++/* Maximum partition number */
++#define SMPART_MAX_PNUM_SHIFT 12
++#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT)
++
++/* Highest possible page number */
++#define SMPART_MAX_PG_SHIFT 0
++#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT)
++
++/* Max size of a page */
++#define SMVID_PG_SIZE_SHIFT 16
++#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT)
++
++/* Major/Minor Version ID */
++#define SMVID_MAJ_VERS_SHIFT 8
++#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT)
++#define SMVID_MIN_VERS_SHIFT 0
++#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT)
++
+ /* LIODN programming for DMA configuration */
+ #define MSTRID_LOCK_LIODN 0x80000000
+ #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
+@@ -228,7 +392,13 @@
+ u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
+ u32 rtfrqcnt; /* PRGM=0: freq. count register */
+ };
+- u32 rsvd1[56];
++ u32 rsvd1[40];
++#define RDSTA_IF 0x00000003 /* state handle instantiated flags 0 and 1 */
++#define RDSTA_SKVN 0x40000000 /* Secure Key Valid Non-Test mode */
++#define RDSTA_SKVT 0x80000000 /* Secure Key Valid Test. non-test mode */
++#define RDSTA_TF 0x00000300 /* State handle instantiated Test-mode */
++ u32 rdsta; /* DRNG status register */
++ u32 rsvd2[15];
+ };
+
+ /*
+@@ -359,7 +529,18 @@
+ u32 rsvd11;
+ u32 jrcommand; /* JRCRx - JobR command */
+
+- u32 rsvd12[932];
++ u32 rsvd12[33];
++
++ /* Secure Memory Configuration - if you have it */
++ u32 sm_cmd; /* SMCJRx - Secure memory command */
++ u32 rsvd13;
++ u32 sm_status; /* SMCSJRx - Secure memory status */
++ u32 rsvd14;
++ u32 sm_perm; /* SMAPJRx - Secure memory access perms */
++ u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */
++ u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */
++
++ u32 rsvd15[891];
+
+ /* Performance Monitor f00-fff */
+ struct caam_perfmon perfmon;
+@@ -482,6 +663,62 @@
+
+ #define JRCR_RESET 0x01
+
++/* secure memory command */
++#define SMC_PAGE_SHIFT 16
++#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT)
++#define SMC_PART_SHIFT 8
++#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT)
++#define SMC_CMD_SHIFT 0
++#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT)
++
++#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */
++#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */
++#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */
++#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */
++
++/* secure memory (command) status */
++#define SMCS_PAGE_SHIFT 16
++#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT)
++#define SMCS_CMDERR_SHIFT 14
++#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT)
++#define SMCS_ALCERR_SHIFT 12
++#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT)
++#define SMCS_PGOWN_SHIFT 6
++#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT)
++#define SMCS_PART_SHIFT 0
++#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT)
++
++#define SMCS_CMDERR_NONE 0
++#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */
++#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */
++#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */
++
++#define SMCS_ALCERR_NONE 0
++#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */
++#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */
++#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */
++
++#define SMCS_PGOWN_AVAIL 0 /* Page is available */
++#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */
++#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */
++#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */
++
++/* secure memory access permissions */
++#define SMCS_PERM_KEYMOD_SHIFT 16
++#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT)
++#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */
++#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */
++#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */
++#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */
++#define SMCA_PERM_RINGID_SHIFT 10
++#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT)
++#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */
++#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */
++#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */
++#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */
++#define SMCA_PERM_G1_WRITE 0x0002
++#define SMCA_PERM_G1_READ 0x0001
++
+ /*
+ * caam_assurance - Assurance Controller View
+ * base + 0x6000 padded out to 0x1000
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/secvio.c linux-linaro-stable-mx6/drivers/crypto/caam/secvio.c
+--- linux-3.10.30.orig/drivers/crypto/caam/secvio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/secvio.c 2014-05-15 20:33:46.849933515 +0200
+@@ -0,0 +1,333 @@
++
++/*
++ * CAAM/SEC 4.x Security Violation Handler
++ * Copyright (C) 2013 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#include "compat.h"
++#include "intern.h"
++#include "secvio.h"
++#include "regs.h"
++
++/*
++ * These names are associated with each violation handler.
++ * The source names were taken from MX6, and are based on recommendations
++ * for most common SoCs.
++ */
++static const u8 *violation_src_name[] = {
++ "CAAM Security Violation",
++ "JTAG Alarm",
++ "Watchdog",
++ "(reserved)",
++ "External Boot",
++ "Tamper Detect",
++};
++
++/* Top-level security violation interrupt */
++static irqreturn_t caam_secvio_interrupt(int irq, void *snvsdev)
++{
++ struct device *dev = snvsdev;
++ struct caam_drv_private_secvio *svpriv = dev_get_drvdata(dev);
++ u32 irqstate;
++
++ /* Check the HP secvio status register */
++ irqstate = rd_reg32(&svpriv->svregs->hp.secvio_status) |
++ HP_SECVIOST_SECVIOMASK;
++
++ if (!irqstate)
++ return IRQ_NONE;
++
++ /* Mask out one or more causes for deferred service */
++ clrbits32(&svpriv->svregs->hp.secvio_int_ctl, irqstate);
++
++ /* Now ACK causes */
++ setbits32(&svpriv->svregs->hp.secvio_status, irqstate);
++
++ /* And run deferred service */
++ preempt_disable();
++ tasklet_schedule(&svpriv->irqtask[smp_processor_id()]);
++ preempt_enable();
++
++ return IRQ_HANDLED;
++}
++
++/* Deferred service handler. Tasklet arg is simply the SNVS dev */
++static void caam_secvio_dispatch(unsigned long indev)
++{
++ struct device *dev = (struct device *)indev;
++ struct caam_drv_private_secvio *svpriv = dev_get_drvdata(dev);
++ unsigned long flags, cause;
++ int i;
++
++
++ /*
++ * Capture the interrupt cause, using masked interrupts as
++ * identification. This only works if all are enabled; if
++ * this changes in the future, a "cause queue" will have to
++ * be built
++ */
++ cause = rd_reg32(&svpriv->svregs->hp.secvio_int_ctl) &
++ (HP_SECVIO_INTEN_SRC5 | HP_SECVIO_INTEN_SRC4 |
++ HP_SECVIO_INTEN_SRC3 | HP_SECVIO_INTEN_SRC2 |
++ HP_SECVIO_INTEN_SRC1 | HP_SECVIO_INTEN_SRC0);
++
++ /* Look through causes, call each handler if exists */
++ for (i = 0; i < MAX_SECVIO_SOURCES; i++)
++ if (cause & (1 << i)) {
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[i].handler(dev, i,
++ svpriv->intsrc[i].ext);
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++ };
++
++ /* Re-enable now-serviced interrupts */
++ setbits32(&svpriv->svregs->hp.secvio_int_ctl, cause);
++}
++
++/*
++ * Default cause handler, used in lieu of an application-defined handler.
++ * All it does at this time is print a console message. It could force a halt.
++ */
++static void caam_secvio_default(struct device *dev, u32 cause, void *ext)
++{
++ struct caam_drv_private_secvio *svpriv = dev_get_drvdata(dev);
++
++ dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n",
++ cause, svpriv->intsrc[cause].intname);
++}
++
++/*
++ * Install an application-defined handler for a specified cause
++ * Arguments:
++ * - dev points to SNVS-owning device
++ * - cause interrupt source cause
++ * - handler application-defined handler, gets called with dev
++ * source cause, and locally-defined handler argument
++ * - cause_description points to a string to override the default cause
++ * name, this can be used as an alternate for error
++ * messages and such. If left NULL, the default
++ * description string is used.
++ * - ext pointer to any extra data needed by the handler.
++ */
++int caam_secvio_install_handler(struct device *dev, enum secvio_cause cause,
++ void (*handler)(struct device *dev, u32 cause,
++ void *ext),
++ u8 *cause_description, void *ext)
++{
++ unsigned long flags;
++ struct caam_drv_private_secvio *svpriv;
++
++ svpriv = dev_get_drvdata(dev);
++
++ if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5))
++ return -EINVAL;
++
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[cause].handler = handler;
++ if (cause_description != NULL)
++ svpriv->intsrc[cause].intname = cause_description;
++ if (ext != NULL)
++ svpriv->intsrc[cause].ext = ext;
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(caam_secvio_install_handler);
++
++/*
++ * Remove an application-defined handler for a specified cause (and, by
++ * implication, restore the "default".
++ * Arguments:
++ * - dev points to SNVS-owning device
++ * - cause interrupt source cause
++ */
++int caam_secvio_remove_handler(struct device *dev, enum secvio_cause cause)
++{
++ unsigned long flags;
++ struct caam_drv_private_secvio *svpriv;
++
++ svpriv = dev_get_drvdata(dev);
++
++ if (cause > SECVIO_CAUSE_SOURCE_5)
++ return -EINVAL;
++
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[cause].intname = violation_src_name[cause];
++ svpriv->intsrc[cause].handler = caam_secvio_default;
++ svpriv->intsrc[cause].ext = NULL;
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++ return 0;
++}
++EXPORT_SYMBOL(caam_secvio_remove_handler);
++
++int caam_secvio_startup(struct platform_device *pdev)
++{
++ struct device *ctrldev, *svdev;
++ struct caam_drv_private *ctrlpriv;
++ struct caam_drv_private_secvio *svpriv;
++ struct platform_device *svpdev;
++ struct device_node *np;
++ const void *prop;
++ int i, error, secvio_inten_src;
++
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++ /*
++ * Set up the private block for secure memory
++ * Only one instance is possible
++ */
++ svpriv = kzalloc(sizeof(struct caam_drv_private_secvio), GFP_KERNEL);
++ if (svpriv == NULL) {
++ dev_err(ctrldev, "can't alloc private mem for secvio\n");
++ return -ENOMEM;
++ }
++ svpriv->parentdev = ctrldev;
++
++ /* Create the security violation dev */
++#ifdef CONFIG_OF
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio");
++ if (!np)
++ return -ENODEV;
++
++ ctrlpriv->secvio_irq = of_irq_to_resource(np, 0, NULL);
++
++ prop = of_get_property(np, "secvio_src", NULL);
++ if (prop)
++ secvio_inten_src = of_read_ulong(prop, 1);
++ else
++ secvio_inten_src = HP_SECVIO_INTEN_ALL;
++
++ svpdev = of_platform_device_create(np, NULL, ctrldev);
++ if (!svpdev)
++ return -ENODEV;
++
++#else
++ svpdev = platform_device_register_data(ctrldev, "caam_secvio", 0,
++ svpriv,
++ sizeof(struct caam_drv_private_secvio));
++
++ secvio_inten_src = HP_SECVIO_INTEN_ALL;
++#endif
++ if (svpdev == NULL) {
++ kfree(svpriv);
++ return -EINVAL;
++ }
++ svdev = &svpdev->dev;
++ dev_set_drvdata(svdev, svpriv);
++ ctrlpriv->secviodev = svdev;
++ svpriv->svregs = ctrlpriv->snvs;
++
++ /*
++ * Now we have all the dev data set up. Init interrupt
++ * source descriptions
++ */
++ for (i = 0; i < MAX_SECVIO_SOURCES; i++) {
++ svpriv->intsrc[i].intname = violation_src_name[i];
++ svpriv->intsrc[i].handler = caam_secvio_default;
++ }
++
++ /* Connect main handler */
++ for_each_possible_cpu(i)
++ tasklet_init(&svpriv->irqtask[i], caam_secvio_dispatch,
++ (unsigned long)svdev);
++
++ error = request_irq(ctrlpriv->secvio_irq, caam_secvio_interrupt,
++ IRQF_SHARED, "caam_secvio", svdev);
++ if (error) {
++ dev_err(svdev, "can't connect secvio interrupt\n");
++ irq_dispose_mapping(ctrlpriv->secvio_irq);
++ ctrlpriv->secvio_irq = 0;
++ return -EINVAL;
++ }
++
++ /* Enable all sources */
++ wr_reg32(&svpriv->svregs->hp.secvio_int_ctl, secvio_inten_src);
++
++ dev_info(svdev, "security violation service handlers armed\n");
++
++ return 0;
++}
++
++void caam_secvio_shutdown(struct platform_device *pdev)
++{
++ struct device *ctrldev, *svdev;
++ struct caam_drv_private *priv;
++ struct caam_drv_private_secvio *svpriv;
++ int i;
++
++ ctrldev = &pdev->dev;
++ priv = dev_get_drvdata(ctrldev);
++ svdev = priv->secviodev;
++ svpriv = dev_get_drvdata(svdev);
++
++ /* Shut off all sources */
++
++ wr_reg32(&svpriv->svregs->hp.secvio_int_ctl, 0);
++
++ /* Remove tasklets and release interrupt */
++ for_each_possible_cpu(i)
++ tasklet_kill(&svpriv->irqtask[i]);
++
++ free_irq(priv->secvio_irq, svdev);
++
++ kfree(svpriv);
++}
++
++
++#ifdef CONFIG_OF
++static void __exit caam_secvio_exit(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return;
++
++ of_node_get(dev_node);
++
++ caam_secvio_shutdown(pdev);
++
++}
++
++static int __init caam_secvio_init(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL,
++ "arm,imx6-caam-secvio");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return -ENODEV;
++
++ of_node_put(dev_node);
++
++ return caam_secvio_startup(pdev);
++}
++
++module_init(caam_secvio_init);
++module_exit(caam_secvio_exit);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM/SNVS Security Violation Handler");
++MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD");
++#endif
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/secvio.h linux-linaro-stable-mx6/drivers/crypto/caam/secvio.h
+--- linux-3.10.30.orig/drivers/crypto/caam/secvio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/secvio.h 2014-05-15 20:33:46.849933515 +0200
+@@ -0,0 +1,64 @@
++
++/*
++ * CAAM Security Violation Handler
++ * Copyright (C) 2013 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#ifndef SECVIO_H
++#define SECVIO_H
++
++#include "snvsregs.h"
++
++
++/*
++ * Defines the published interfaces to install/remove application-specified
++ * handlers for catching violations
++ */
++
++#define MAX_SECVIO_SOURCES 6
++
++/* these are the untranslated causes */
++enum secvio_cause {
++ SECVIO_CAUSE_SOURCE_0,
++ SECVIO_CAUSE_SOURCE_1,
++ SECVIO_CAUSE_SOURCE_2,
++ SECVIO_CAUSE_SOURCE_3,
++ SECVIO_CAUSE_SOURCE_4,
++ SECVIO_CAUSE_SOURCE_5
++};
++
++/* These are common "recommended" cause definitions for most devices */
++#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0
++#define SECVIO_CAUSE JTAG_ALARM SECVIO_CAUSE_SOURCE_1
++#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2
++#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4
++#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5
++
++int caam_secvio_install_handler(struct device *dev, enum secvio_cause cause,
++ void (*handler)(struct device *dev, u32 cause,
++ void *ext),
++ u8 *cause_description, void *ext);
++int caam_secvio_remove_handler(struct device *dev, enum secvio_cause cause);
++
++/*
++ * Private data definitions for the secvio "driver"
++ */
++
++struct secvio_int_src {
++ const u8 *intname; /* Points to a descriptive name for source */
++ void *ext; /* Extended data to pass to the handler */
++ void (*handler)(struct device *dev, u32 cause, void *ext);
++};
++
++struct caam_drv_private_secvio {
++ struct device *parentdev; /* points back to the controller */
++ spinlock_t svlock ____cacheline_aligned;
++ struct tasklet_struct irqtask[NR_CPUS];
++ struct snvs_full __iomem *svregs; /* both HP and LP domains */
++
++ /* Registered handlers for each violation */
++ struct secvio_int_src intsrc[MAX_SECVIO_SOURCES];
++
++};
++
++#endif /* SECVIO_H */
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/sg_sw_sec4.h linux-linaro-stable-mx6/drivers/crypto/caam/sg_sw_sec4.h
+--- linux-3.10.30.orig/drivers/crypto/caam/sg_sw_sec4.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/sg_sw_sec4.h 2014-05-15 20:33:46.849933515 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM/SEC 4.x functions for using scatterlists in caam driver
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
+ *
+ */
+
+@@ -91,13 +91,22 @@
+ {
+ if (unlikely(chained)) {
+ int i;
++ struct scatterlist *tsg = sg;
++
++ /* We use a local copy of the sg pointer to avoid moving the
++ * head of the list pointed to by sg as we wall the list.
++ */
+ for (i = 0; i < nents; i++) {
+- dma_map_sg(dev, sg, 1, dir);
+- sg = scatterwalk_sg_next(sg);
++ dma_map_sg(dev, tsg, 1, dir);
++ tsg = scatterwalk_sg_next(tsg);
+ }
+ } else {
+ dma_map_sg(dev, sg, nents, dir);
+ }
++
++ if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL))
++ dma_sync_sg_for_device(dev, sg, nents, dir);
++
+ return nents;
+ }
+
+@@ -105,6 +114,9 @@
+ unsigned int nents, enum dma_data_direction dir,
+ bool chained)
+ {
++ if ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))
++ dma_sync_sg_for_cpu(dev, sg, nents, dir);
++
+ if (unlikely(chained)) {
+ int i;
+ for (i = 0; i < nents; i++) {
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/sm.h linux-linaro-stable-mx6/drivers/crypto/caam/sm.h
+--- linux-3.10.30.orig/drivers/crypto/caam/sm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/sm.h 2014-05-15 20:33:46.849933515 +0200
+@@ -0,0 +1,88 @@
++
++/*
++ * CAAM Secure Memory/Keywrap API Definitions
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
++ */
++
++#ifndef SM_H
++#define SM_H
++
++
++/* Storage access permissions */
++#define SM_PERM_READ 0x01
++#define SM_PERM_WRITE 0x02
++#define SM_PERM_BLOB 0x03
++
++
++/* Keystore maintenance functions */
++void sm_init_keystore(struct device *dev);
++u32 sm_detect_keystore_units(struct device *dev);
++int sm_establish_keystore(struct device *dev, u32 unit);
++void sm_release_keystore(struct device *dev, u32 unit);
++void caam_sm_shutdown(struct platform_device *pdev);
++int caam_sm_example_init(struct platform_device *pdev);
++
++/* Keystore accessor functions */
++extern int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size,
++ u32 *slot);
++extern int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot);
++extern int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot,
++ const u8 *key_data, u32 key_length);
++extern int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot,
++ u32 key_length, u8 *key_data);
++extern int sm_keystore_slot_encapsulate(struct device *dev, u32 unit,
++ u32 inslot, u32 outslot, u16 secretlen,
++ u8 *keymod, u16 keymodlen);
++extern int sm_keystore_slot_decapsulate(struct device *dev, u32 unit,
++ u32 inslot, u32 outslot, u16 secretlen,
++ u8 *keymod, u16 keymodlen);
++
++/* Data structure to hold per-slot information */
++struct keystore_data_slot_info {
++ u8 allocated; /* Track slot assignments */
++ u32 key_length; /* Size of the key */
++};
++
++/* Data structure to hold keystore information */
++struct keystore_data {
++ void *base_address; /* Base of the Secure Partition */
++ u32 slot_count; /* Number of slots in the keystore */
++ struct keystore_data_slot_info *slot; /* Per-slot information */
++};
++
++/* store the detected attributes of a secure memory page */
++struct sm_page_descriptor {
++ u16 phys_pagenum; /* may be discontiguous */
++ u16 own_part; /* Owning partition */
++ void *pg_base; /* Calculated virtual address */
++ struct keystore_data *ksdata;
++};
++
++struct caam_drv_private_sm {
++ struct device *parentdev; /* this ends up as the controller */
++ struct device *smringdev; /* ring that owns this instance */
++ spinlock_t kslock ____cacheline_aligned;
++
++ /* Default parameters for geometry */
++ u32 max_pages; /* maximum pages this instance can support */
++ u32 top_partition; /* highest partition number in this instance */
++ u32 top_page; /* highest page number in this instance */
++ u32 page_size; /* page size */
++ u32 slot_size; /* selected size of each storage block */
++
++ /* Partition/Page Allocation Map */
++ u32 localpages; /* Number of pages we can access */
++ struct sm_page_descriptor *pagedesc; /* Allocated per-page */
++
++ /* Installed handlers for keystore access */
++ int (*data_init)(struct device *dev, u32 unit);
++ void (*data_cleanup)(struct device *dev, u32 unit);
++ int (*slot_alloc)(struct device *dev, u32 unit, u32 size, u32 *slot);
++ int (*slot_dealloc)(struct device *dev, u32 unit, u32 slot);
++ void *(*slot_get_address)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_base)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_offset)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_slot_size)(struct device *dev, u32 unit, u32 handle);
++};
++
++#endif /* SM_H */
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/sm_store.c linux-linaro-stable-mx6/drivers/crypto/caam/sm_store.c
+--- linux-3.10.30.orig/drivers/crypto/caam/sm_store.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/sm_store.c 2014-05-15 20:33:46.849933515 +0200
+@@ -0,0 +1,896 @@
++
++/*
++ * CAAM Secure Memory Storage Interface
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc.
++ *
++ * Loosely based on the SHW Keystore API for SCC/SCC2
++ * Experimental implementation and NOT intended for upstream use. Expect
++ * this interface to be amended significantly in the future once it becomes
++ * integrated into live applications.
++ *
++ * Known issues:
++ *
++ * - Executes one instance of an secure memory "driver". This is tied to the
++ * fact that job rings can't run as standalone instances in the present
++ * configuration.
++ *
++ * - It does not expose a userspace interface. The value of a userspace
++ * interface for access to secrets is a point for further architectural
++ * discussion.
++ *
++ * - Partition/permission management is not part of this interface. It
++ * depends on some level of "knowledge" agreed upon between bootloader,
++ * provisioning applications, and OS-hosted software (which uses this
++ * driver).
++ *
++ * - No means of identifying the location or purpose of secrets managed by
++ * this interface exists; "slot location" and format of a given secret
++ * needs to be agreed upon between bootloader, provisioner, and OS-hosted
++ * application.
++ */
++
++#include "compat.h"
++#include "regs.h"
++#include "jr.h"
++#include "desc.h"
++#include "intern.h"
++#include "error.h"
++#include "sm.h"
++
++#ifdef SM_DEBUG_CONT
++void sm_show_page(struct device *dev, struct sm_page_descriptor *pgdesc)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ u32 i, *smdata;
++
++ dev_info(dev, "physical page %d content at 0x%08x\n",
++ pgdesc->phys_pagenum, pgdesc->pg_base);
++ smdata = pgdesc->pg_base;
++ for (i = 0; i < (smpriv->page_size / sizeof(u32)); i += 4)
++ dev_info(dev, "[0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ (u32)&smdata[i], smdata[i], smdata[i+1], smdata[i+2],
++ smdata[i+3]);
++}
++#endif
++
++/*
++ * Construct a secure memory blob encapsulation job descriptor
++ *
++ * - desc pointer to hold new (to be allocated) pointer to the generated
++ * descriptor for later use. Calling thread can kfree the
++ * descriptor after execution.
++ * - keymod Physical pointer to key modifier (contiguous piece).
++ * - keymodsz Size of key modifier in bytes (should normally be 8).
++ * - secretbuf Physical pointer (within an accessible secure memory page)
++ * of the secret to be encapsulated.
++ * - outbuf Physical pointer (within an accessible secure memory page)
++ * of the encapsulated output. This will be larger than the
++ * input secret because of the added encapsulation data.
++ * - secretsz Size of input secret, in bytes.
++ * - auth If nonzero, use AES-CCM for encapsulation, else use ECB
++ *
++ * Note: this uses 32-bit pointers at present
++ */
++#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */
++static int blob_encap_desc(u32 **desc, dma_addr_t keymod, u16 keymodsz,
++ dma_addr_t secretbuf, dma_addr_t outbuf,
++ u16 secretsz, bool auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /* Load key modifier */
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY |
++ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) |
++ (keymodsz & LDST_LEN_MASK);
++
++ tmpdesc[idx++] = (u32)keymod;
++
++ /* Encapsulate to secure memory */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz;
++ tmpdesc[idx++] = (u32)secretbuf;
++
++ /* Add space for BKEK and MAC tag */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + (32 + 16));
++
++ tmpdesc[idx++] = (u32)outbuf;
++ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB |
++ OP_PCL_BLOB_PTXT_SECMEM;
++ if (auth)
++ tmpdesc[idx] |= OP_PCL_BLOB_EKT;
++
++ idx++;
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++ return dsize;
++}
++
++/*
++ * Construct a secure memory blob decapsulation job descriptor
++ *
++ * - desc pointer to hold new (to be allocated) pointer to the generated
++ * descriptor for later use. Calling thread can kfree the
++ * descriptor after execution.
++ * - keymod Physical pointer to key modifier (contiguous piece).
++ * - keymodsz Size of key modifier in bytes (should normally be 16).
++ * - blobbuf Physical pointer (within an accessible secure memory page)
++ * of the blob to be decapsulated.
++ * - outbuf Physical pointer (within an accessible secure memory page)
++ * of the decapsulated output.
++ * - secretsz Size of input blob, in bytes.
++ * - auth If nonzero, assume AES-CCM for decapsulation, else use ECB
++ *
++ * Note: this uses 32-bit pointers at present
++ */
++static int blob_decap_desc(u32 **desc, dma_addr_t keymod, u16 keymodsz,
++ dma_addr_t blobbuf, dma_addr_t outbuf,
++ u16 blobsz, bool auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /* Load key modifier */
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY |
++ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) |
++ (keymodsz & LDST_LEN_MASK);
++
++ tmpdesc[idx++] = (u32)keymod;
++
++ /* Compensate BKEK + MAC tag */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (blobsz + 32 + 16);
++
++ tmpdesc[idx++] = (u32)blobbuf;
++ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | blobsz;
++ tmpdesc[idx++] = (u32)outbuf;
++
++ /* Decapsulate from secure memory partition to black blob */
++ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB |
++ OP_PCL_BLOB_PTXT_SECMEM | OP_PCL_BLOB_BLACK;
++ if (auth)
++ tmpdesc[idx] |= OP_PCL_BLOB_EKT;
++
++ idx++;
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++ return dsize;
++}
++
++/*
++ * Pseudo-synchronous ring access functions for carrying out key
++ * encapsulation and decapsulation
++ */
++
++struct sm_key_job_result {
++ int error;
++ struct completion completion;
++};
++
++void sm_key_job_done(struct device *dev, u32 *desc, u32 err, void *context)
++{
++ struct sm_key_job_result *res = context;
++
++ res->error = err; /* save off the error for postprocessing */
++ complete(&res->completion); /* mark us complete */
++}
++
++static int sm_key_job(struct device *ksdev, u32 *jobdesc)
++{
++ struct sm_key_job_result testres;
++ struct caam_drv_private_sm *kspriv;
++ int rtn = 0;
++
++ kspriv = dev_get_drvdata(ksdev);
++
++ init_completion(&testres.completion);
++
++ rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, sm_key_job_done,
++ &testres);
++ if (!rtn) {
++ wait_for_completion_interruptible(&testres.completion);
++ rtn = testres.error;
++ }
++ return rtn;
++}
++
++/*
++ * Following section establishes the default methods for keystore access
++ * They are NOT intended for use external to this module
++ *
++ * In the present version, these are the only means for the higher-level
++ * interface to deal with the mechanics of accessing the phyiscal keystore
++ */
++
++
++int slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++ u32 i;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_alloc(): requesting slot for %d bytes\n", size);
++#endif
++
++ if (size > smpriv->slot_size)
++ return -EKEYREJECTED;
++
++ for (i = 0; i < ksdata->slot_count; i++) {
++ if (ksdata->slot[i].allocated == 0) {
++ ksdata->slot[i].allocated = 1;
++ (*slot) = i;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_alloc(): new slot %d allocated\n",
++ *slot);
++#endif
++ return 0;
++ }
++ }
++
++ return -ENOSPC;
++}
++EXPORT_SYMBOL(slot_alloc);
++
++int slot_dealloc(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++ u8 __iomem *slotdata;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_dealloc(): releasing slot %d\n", slot);
++#endif
++ if (slot >= ksdata->slot_count)
++ return -EINVAL;
++ slotdata = ksdata->base_address + slot * smpriv->slot_size;
++
++ if (ksdata->slot[slot].allocated == 1) {
++ /* Forcibly overwrite the data from the keystore */
++ memset(ksdata->base_address + slot * smpriv->slot_size, 0,
++ smpriv->slot_size);
++
++ ksdata->slot[slot].allocated = 0;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_dealloc(): slot %d released\n", slot);
++#endif
++ return 0;
++ }
++
++ return -EINVAL;
++}
++EXPORT_SYMBOL(slot_dealloc);
++
++void *slot_get_address(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ if (slot >= ksdata->slot_count)
++ return NULL;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_address(): slot %d is 0x%08x\n", slot,
++ (u32)ksdata->base_address + slot * smpriv->slot_size);
++#endif
++
++ return ksdata->base_address + slot * smpriv->slot_size;
++}
++
++u32 slot_get_base(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ /*
++ * There could potentially be more than one secure partition object
++ * associated with this keystore. For now, there is just one.
++ */
++
++ (void)slot;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_base(): slot %d = 0x%08x\n",
++ slot, (u32)ksdata->base_address);
++#endif
++
++ return (u32)(ksdata->base_address);
++}
++
++u32 slot_get_offset(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ if (slot >= ksdata->slot_count)
++ return -EINVAL;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_offset(): slot %d = %d\n", slot,
++ slot * smpriv->slot_size);
++#endif
++
++ return slot * smpriv->slot_size;
++}
++
++u32 slot_get_slot_size(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_slot_size(): slot %d = %d\n", slot,
++ smpriv->slot_size);
++#endif
++ /* All slots are the same size in the default implementation */
++ return smpriv->slot_size;
++}
++
++
++
++int kso_init_data(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ struct keystore_data *keystore_data = NULL;
++ u32 slot_count;
++ u32 keystore_data_size;
++
++ /*
++ * Calculate the required size of the keystore data structure, based
++ * on the number of keys that can fit in the partition.
++ */
++ slot_count = smpriv->page_size / smpriv->slot_size;
++#ifdef SM_DEBUG
++ dev_info(dev, "kso_init_data: %d slots initializing\n", slot_count);
++#endif
++
++ keystore_data_size = sizeof(struct keystore_data) +
++ slot_count *
++ sizeof(struct keystore_data_slot_info);
++
++ keystore_data = kzalloc(keystore_data_size, GFP_KERNEL);
++
++ if (keystore_data == NULL) {
++ retval = -ENOSPC;
++ goto out;
++ }
++
++#ifdef SM_DEBUG
++ dev_info(dev, "kso_init_data: keystore data size = %d\n",
++ keystore_data_size);
++#endif
++
++ /*
++ * Place the slot information structure directly after the keystore data
++ * structure.
++ */
++ keystore_data->slot = (struct keystore_data_slot_info *)
++ (keystore_data + 1);
++ keystore_data->slot_count = slot_count;
++
++ smpriv->pagedesc[unit].ksdata = keystore_data;
++ smpriv->pagedesc[unit].ksdata->base_address =
++ smpriv->pagedesc[unit].pg_base;
++
++ retval = 0;
++
++out:
++ if (retval != 0)
++ if (keystore_data != NULL)
++ kfree(keystore_data);
++
++
++ return retval;
++}
++
++void kso_cleanup_data(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *keystore_data = NULL;
++
++ if (smpriv->pagedesc[unit].ksdata != NULL)
++ keystore_data = smpriv->pagedesc[unit].ksdata;
++
++ /* Release the allocated keystore management data */
++ kfree(smpriv->pagedesc[unit].ksdata);
++
++ return;
++}
++
++
++
++/*
++ * Keystore management section
++ */
++
++void sm_init_keystore(struct device *dev)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++ smpriv->data_init = kso_init_data;
++ smpriv->data_cleanup = kso_cleanup_data;
++ smpriv->slot_alloc = slot_alloc;
++ smpriv->slot_dealloc = slot_dealloc;
++ smpriv->slot_get_address = slot_get_address;
++ smpriv->slot_get_base = slot_get_base;
++ smpriv->slot_get_offset = slot_get_offset;
++ smpriv->slot_get_slot_size = slot_get_slot_size;
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_init_keystore(): handlers installed\n");
++#endif
++}
++EXPORT_SYMBOL(sm_init_keystore);
++
++/* Return available pages/units */
++u32 sm_detect_keystore_units(struct device *dev)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++ return smpriv->localpages;
++}
++EXPORT_SYMBOL(sm_detect_keystore_units);
++
++/*
++ * Do any keystore specific initializations
++ */
++int sm_establish_keystore(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_establish_keystore(): unit %d initializing\n", unit);
++#endif
++
++ if (smpriv->data_init == NULL)
++ return -EINVAL;
++
++ /* Call the data_init function for any user setup */
++ return smpriv->data_init(dev, unit);
++}
++EXPORT_SYMBOL(sm_establish_keystore);
++
++void sm_release_keystore(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_establish_keystore(): unit %d releasing\n", unit);
++#endif
++ if ((smpriv != NULL) && (smpriv->data_cleanup != NULL))
++ smpriv->data_cleanup(dev, unit);
++
++ return;
++}
++EXPORT_SYMBOL(sm_release_keystore);
++
++/*
++ * Subsequent interfacce (sm_keystore_*) forms the accessor interfacce to
++ * the keystore
++ */
++int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++
++ spin_lock(&smpriv->kslock);
++
++ if ((smpriv->slot_alloc == NULL) ||
++ (smpriv->pagedesc[unit].ksdata == NULL))
++ goto out;
++
++ retval = smpriv->slot_alloc(dev, unit, size, slot);
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_alloc);
++
++int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++
++ spin_lock(&smpriv->kslock);
++
++ if ((smpriv->slot_alloc == NULL) ||
++ (smpriv->pagedesc[unit].ksdata == NULL))
++ goto out;
++
++ retval = smpriv->slot_dealloc(dev, unit, slot);
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_dealloc);
++
++int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot,
++ const u8 *key_data, u32 key_length)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ u32 slot_size;
++ u32 i;
++ u8 __iomem *slot_location;
++
++ spin_lock(&smpriv->kslock);
++
++ slot_size = smpriv->slot_get_slot_size(dev, unit, slot);
++
++ if (key_length > slot_size) {
++ retval = -EFBIG;
++ goto out;
++ }
++
++ slot_location = smpriv->slot_get_address(dev, unit, slot);
++
++ for (i = 0; i < key_length; i++)
++ slot_location[i] = key_data[i];
++
++ retval = 0;
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_load);
++
++int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot,
++ u32 key_length, u8 *key_data)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ u8 __iomem *slot_addr;
++ u32 slot_size;
++
++ spin_lock(&smpriv->kslock);
++
++ slot_addr = smpriv->slot_get_address(dev, unit, slot);
++ slot_size = smpriv->slot_get_slot_size(dev, unit, slot);
++
++ if (key_length > slot_size) {
++ retval = -EKEYREJECTED;
++ goto out;
++ }
++
++ memcpy(key_data, slot_addr, key_length);
++ retval = 0;
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_read);
++
++int sm_keystore_slot_encapsulate(struct device *dev, u32 unit, u32 inslot,
++ u32 outslot, u16 secretlen, u8 *keymod,
++ u16 keymodlen)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = 0;
++ u32 slot_length, dsize, jstat;
++ u32 __iomem *encapdesc = NULL;
++ u8 __iomem *lkeymod, *inpslotaddr, *outslotaddr;
++ dma_addr_t keymod_dma;
++
++ /* Ensure that the full blob will fit in the key slot */
++ slot_length = smpriv->slot_get_slot_size(dev, unit, outslot);
++ if ((secretlen + 48) > slot_length)
++ goto out;
++
++ /* Get the base addresses of both keystore slots */
++ inpslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, inslot);
++ outslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, outslot);
++
++ /* Build the key modifier */
++ lkeymod = kmalloc(keymodlen, GFP_KERNEL | GFP_DMA);
++ memcpy(lkeymod, keymod, keymodlen);
++ keymod_dma = dma_map_single(dev, lkeymod, keymodlen, DMA_TO_DEVICE);
++ dma_sync_single_for_device(dev, keymod_dma, keymodlen, DMA_TO_DEVICE);
++
++ /* Build the encapsulation job descriptor */
++ dsize = blob_encap_desc(&encapdesc, keymod_dma, keymodlen,
++ __pa(inpslotaddr), __pa(outslotaddr),
++ secretlen, 0);
++ if (!dsize) {
++ dev_err(dev, "can't alloc an encap descriptor\n");
++ retval = -ENOMEM;
++ goto out;
++ }
++ jstat = sm_key_job(dev, encapdesc);
++
++ dma_unmap_single(dev, keymod_dma, keymodlen, DMA_TO_DEVICE);
++ kfree(encapdesc);
++
++out:
++ return retval;
++
++}
++EXPORT_SYMBOL(sm_keystore_slot_encapsulate);
++
++int sm_keystore_slot_decapsulate(struct device *dev, u32 unit, u32 inslot,
++ u32 outslot, u16 secretlen, u8 *keymod,
++ u16 keymodlen)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = 0;
++ u32 slot_length, dsize, jstat;
++ u32 __iomem *decapdesc = NULL;
++ u8 __iomem *lkeymod, *inpslotaddr, *outslotaddr;
++ dma_addr_t keymod_dma;
++
++ /* Ensure that the decap data will fit in the key slot */
++ slot_length = smpriv->slot_get_slot_size(dev, unit, outslot);
++ if (secretlen > slot_length)
++ goto out;
++
++ /* Get the base addresses of both keystore slots */
++ inpslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, inslot);
++ outslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, outslot);
++
++ /* Build the key modifier */
++ lkeymod = kmalloc(keymodlen, GFP_KERNEL | GFP_DMA);
++ memcpy(lkeymod, keymod, keymodlen);
++ keymod_dma = dma_map_single(dev, lkeymod, keymodlen, DMA_TO_DEVICE);
++ dma_sync_single_for_device(dev, keymod_dma, keymodlen, DMA_TO_DEVICE);
++
++ /* Build the decapsulation job descriptor */
++ dsize = blob_decap_desc(&decapdesc, keymod_dma, keymodlen,
++ __pa(inpslotaddr), __pa(outslotaddr),
++ secretlen, 0);
++ if (!dsize) {
++ dev_err(dev, "can't alloc a decap descriptor\n");
++ retval = -ENOMEM;
++ goto out;
++ }
++ jstat = sm_key_job(dev, decapdesc);
++
++ dma_unmap_single(dev, keymod_dma, keymodlen, DMA_TO_DEVICE);
++ kfree(decapdesc);
++
++out:
++ return retval;
++
++}
++EXPORT_SYMBOL(sm_keystore_slot_decapsulate);
++
++
++/*
++ * Initialization/shutdown subsystem
++ * Assumes statically-invoked startup/shutdown from the controller driver
++ * for the present time, to be reworked when a device tree becomes
++ * available. This code will not modularize in present form.
++ *
++ * Also, simply uses ring 0 for execution at the present
++ */
++
++int caam_sm_startup(struct platform_device *pdev)
++{
++ struct device *ctrldev, *smdev;
++ struct caam_drv_private *ctrlpriv;
++ struct caam_drv_private_sm *smpriv;
++ struct caam_drv_private_jr *jrpriv; /* need this for reg page */
++ struct platform_device *sm_pdev;
++ struct sm_page_descriptor *lpagedesc;
++ u32 page, pgstat, lpagect, detectedpage;
++
++ struct device_node *np;
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++
++ /*
++ * Set up the private block for secure memory
++ * Only one instance is possible
++ */
++ smpriv = kzalloc(sizeof(struct caam_drv_private_sm), GFP_KERNEL);
++ if (smpriv == NULL) {
++ dev_err(ctrldev, "can't alloc private mem for secure memory\n");
++ return -ENOMEM;
++ }
++ smpriv->parentdev = ctrldev; /* copy of parent dev is handy */
++
++ /* Create the dev */
++#ifdef CONFIG_OF
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm");
++ sm_pdev = of_platform_device_create(np, "caam_sm", ctrldev);
++#else
++ sm_pdev = platform_device_register_data(ctrldev, "caam_sm", 0,
++ smpriv,
++ sizeof(struct caam_drv_private_sm));
++#endif
++ if (sm_pdev == NULL) {
++ kfree(smpriv);
++ return -EINVAL;
++ }
++ smdev = &sm_pdev->dev;
++ dev_set_drvdata(smdev, smpriv);
++ ctrlpriv->smdev = smdev;
++
++ /*
++ * Collect configuration limit data for reference
++ * This batch comes from the partition data/vid registers in perfmon
++ */
++ smpriv->max_pages = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_NUMPG_MASK) >>
++ SMPART_MAX_NUMPG_SHIFT) + 1;
++ smpriv->top_partition = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_PNUM_MASK) >>
++ SMPART_MAX_PNUM_SHIFT) + 1;
++ smpriv->top_page = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_PG_MASK) >> SMPART_MAX_PG_SHIFT) + 1;
++ smpriv->page_size = 1024 << ((rd_reg32(&ctrlpriv->ctrl->perfmon.smvid)
++ & SMVID_PG_SIZE_MASK) >> SMVID_PG_SIZE_SHIFT);
++ smpriv->slot_size = 1 << CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE;
++
++#ifdef SM_DEBUG
++ dev_info(smdev, "max pages = %d, top partition = %d\n",
++ smpriv->max_pages, smpriv->top_partition);
++ dev_info(smdev, "top page = %d, page size = %d (total = %d)\n",
++ smpriv->top_page, smpriv->page_size,
++ smpriv->top_page * smpriv->page_size);
++ dev_info(smdev, "selected slot size = %d\n", smpriv->slot_size);
++#endif
++
++ /*
++ * Now probe for partitions/pages to which we have access. Note that
++ * these have likely been set up by a bootloader or platform
++ * provisioning application, so we have to assume that we "inherit"
++ * a configuration and work within the constraints of what it might be.
++ *
++ * Assume use of the zeroth ring in the present iteration (until
++ * we can divorce the controller and ring drivers, and then assign
++ * an SM instance to any ring instance).
++ */
++ smpriv->smringdev = ctrlpriv->jrdev[0];
++ jrpriv = dev_get_drvdata(smpriv->smringdev);
++ lpagect = 0;
++ lpagedesc = kzalloc(sizeof(struct sm_page_descriptor)
++ * smpriv->max_pages, GFP_KERNEL);
++ if (lpagedesc == NULL) {
++ kfree(smpriv);
++ return -ENOMEM;
++ }
++
++ for (page = 0; page < smpriv->max_pages; page++) {
++ wr_reg32(&jrpriv->rregs->sm_cmd,
++ ((page << SMC_PAGE_SHIFT) & SMC_PAGE_MASK) |
++ (SMC_CMD_PAGE_INQUIRY & SMC_CMD_MASK));
++ pgstat = rd_reg32(&jrpriv->rregs->sm_status);
++ if (((pgstat & SMCS_PGWON_MASK) >> SMCS_PGOWN_SHIFT)
++ == SMCS_PGOWN_OWNED) { /* our page? */
++ lpagedesc[page].phys_pagenum =
++ (pgstat & SMCS_PAGE_MASK) >> SMCS_PAGE_SHIFT;
++ lpagedesc[page].own_part =
++ (pgstat & SMCS_PART_SHIFT) >> SMCS_PART_MASK;
++ lpagedesc[page].pg_base = ctrlpriv->sm_base +
++ ((smpriv->page_size * page) / sizeof(u32));
++ lpagect++;
++#ifdef SM_DEBUG
++ dev_info(smdev,
++ "physical page %d, owning partition = %d\n",
++ lpagedesc[page].phys_pagenum,
++ lpagedesc[page].own_part);
++#endif
++ }
++ }
++
++ smpriv->pagedesc = kzalloc(sizeof(struct sm_page_descriptor) * lpagect,
++ GFP_KERNEL);
++ if (smpriv->pagedesc == NULL) {
++ kfree(lpagedesc);
++ kfree(smpriv);
++ return -ENOMEM;
++ }
++ smpriv->localpages = lpagect;
++
++ detectedpage = 0;
++ for (page = 0; page < smpriv->max_pages; page++) {
++ if (lpagedesc[page].pg_base != NULL) { /* e.g. live entry */
++ memcpy(&smpriv->pagedesc[detectedpage],
++ &lpagedesc[page],
++ sizeof(struct sm_page_descriptor));
++#ifdef SM_DEBUG_CONT
++ sm_show_page(smdev, &smpriv->pagedesc[detectedpage]);
++#endif
++ detectedpage++;
++ }
++ }
++
++ kfree(lpagedesc);
++
++ sm_init_keystore(smdev);
++
++ return 0;
++}
++
++void caam_sm_shutdown(struct platform_device *pdev)
++{
++ struct device *ctrldev, *smdev;
++ struct caam_drv_private *priv;
++ struct caam_drv_private_sm *smpriv;
++
++ ctrldev = &pdev->dev;
++ priv = dev_get_drvdata(ctrldev);
++ smdev = priv->smdev;
++ smpriv = dev_get_drvdata(smdev);
++
++ kfree(smpriv->pagedesc);
++ kfree(smpriv);
++}
++EXPORT_SYMBOL(caam_sm_shutdown);
++#ifdef CONFIG_OF
++static void __exit caam_sm_exit(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return;
++
++ of_node_put(dev_node);
++
++ caam_sm_shutdown(pdev);
++
++ return;
++}
++
++static int __init caam_sm_init(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return -ENODEV;
++
++ of_node_get(dev_node);
++
++ caam_sm_startup(pdev);
++
++ return 0;
++}
++
++module_init(caam_sm_init);
++module_exit(caam_sm_exit);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM Secure Memory / Keystore");
++MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD");
++#endif
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/sm_test.c linux-linaro-stable-mx6/drivers/crypto/caam/sm_test.c
+--- linux-3.10.30.orig/drivers/crypto/caam/sm_test.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/sm_test.c 2014-05-15 20:33:46.849933515 +0200
+@@ -0,0 +1,844 @@
++/*
++ * Secure Memory / Keystore Exemplification Module
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ *
++ * Serves as a functional example, and as a self-contained unit test for
++ * the functionality contained in sm_store.c.
++ *
++ * The example function, caam_sm_example_init(), runs a thread that:
++ *
++ * - initializes a set of fixed keys
++ * - stores one copy in clear buffers
++ * - stores them again in secure memory
++ * - extracts stored keys back out for use
++ * - intializes 3 data buffers for a test:
++ * (1) containing cleartext
++ * (2) to hold ciphertext encrypted with an extracted black key
++ * (3) to hold extracted cleartext decrypted with an equivalent clear key
++ *
++ * The function then builds simple job descriptors that reference the key
++ * material and buffers as initialized, and executes an encryption job
++ * with a black key, and a decryption job using a the same key held in the
++ * clear. The output of the decryption job is compared to the original
++ * cleartext; if they don't compare correctly, one can assume a key problem
++ * exists, where the function will exit with an error.
++ *
++ * This module can use a substantial amount of refactoring, which may occur
++ * after the API gets some mileage. Furthermore, expect this module to
++ * eventually disappear once the API is integrated into "real" software.
++ */
++
++#include "compat.h"
++#include "intern.h"
++#include "desc.h"
++#include "error.h"
++#include "jr.h"
++#include "sm.h"
++
++static u8 skeymod[] = {
++ 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
++ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00
++};
++static u8 symkey[] = {
++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
++ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
++};
++
++static u8 symdata[] = {
++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x0f, 0x06, 0x07,
++ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
++ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
++ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
++ 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
++ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
++ 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
++ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
++ 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
++ 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
++ 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
++ 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
++ 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
++ 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
++ 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
++ 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
++ 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
++ 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
++ 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
++ 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
++ 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
++ 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
++ 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
++ 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
++ 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
++ 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
++ 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
++ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
++ 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff
++};
++
++static int mk_job_desc(u32 *desc, dma_addr_t key, u16 keysz, dma_addr_t indata,
++ dma_addr_t outdata, u16 sz, u32 cipherdir, u32 keymode)
++{
++ desc[1] = CMD_KEY | CLASS_1 | (keysz & KEY_LENGTH_MASK) | keymode;
++ desc[2] = (u32)key;
++ desc[3] = CMD_OPERATION | OP_TYPE_CLASS1_ALG | OP_ALG_AAI_ECB |
++ cipherdir;
++ desc[4] = CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 |
++ FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1 | sz;
++ desc[5] = (u32)indata;
++ desc[6] = CMD_FIFO_STORE | FIFOST_TYPE_MESSAGE_DATA | sz;
++ desc[7] = (u32)outdata;
++
++ desc[0] = CMD_DESC_HDR | HDR_ONE | (8 & HDR_DESCLEN_MASK);
++ return 8 * sizeof(u32);
++}
++
++struct exec_test_result {
++ int error;
++ struct completion completion;
++};
++
++void exec_test_done(struct device *dev, u32 *desc, u32 err, void *context)
++{
++ struct exec_test_result *res = context;
++
++ if (err) {
++ char tmp[CAAM_ERROR_STR_MAX];
++ dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
++ }
++
++ res->error = err;
++ complete(&res->completion);
++}
++
++static int exec_test_job(struct device *ksdev, u32 *jobdesc)
++{
++ struct exec_test_result testres;
++ struct caam_drv_private_sm *kspriv;
++ int rtn = 0;
++
++ kspriv = dev_get_drvdata(ksdev);
++
++ init_completion(&testres.completion);
++
++ rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, exec_test_done,
++ &testres);
++ if (!rtn) {
++ wait_for_completion_interruptible(&testres.completion);
++ rtn = testres.error;
++ }
++ return rtn;
++}
++
++
++int caam_sm_example_init(struct platform_device *pdev)
++{
++ struct device *ctrldev, *ksdev;
++ struct caam_drv_private *ctrlpriv;
++ struct caam_drv_private_sm *kspriv;
++ u32 unit, units, jdescsz;
++ int stat, jstat, rtnval = 0;
++ u8 __iomem *syminp, *symint, *symout = NULL;
++ dma_addr_t syminp_dma, symint_dma, symout_dma;
++ u8 __iomem *black_key_des, *black_key_aes128;
++ u8 __iomem *black_key_aes256;
++ dma_addr_t black_key_des_dma, black_key_aes128_dma;
++ dma_addr_t black_key_aes256_dma;
++ u8 __iomem *clear_key_des, *clear_key_aes128, *clear_key_aes256;
++ dma_addr_t clear_key_des_dma, clear_key_aes128_dma;
++ dma_addr_t clear_key_aes256_dma;
++ u32 __iomem *jdesc;
++ u32 keyslot_des, keyslot_aes128, keyslot_aes256 = 0;
++
++ jdesc = NULL;
++ black_key_des = black_key_aes128 = black_key_aes256 = NULL;
++ clear_key_des = clear_key_aes128 = clear_key_aes256 = NULL;
++
++ /* We can lose this cruft once we can get a pdev by name */
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++ ksdev = ctrlpriv->smdev;
++ kspriv = dev_get_drvdata(ksdev);
++ if (kspriv == NULL)
++ return -ENODEV;
++
++ /* Now that we have the dev for the single SM instance, connect */
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test_init() running\n");
++#endif
++ /* Probe to see what keystores are available to us */
++ units = sm_detect_keystore_units(ksdev);
++ if (!units)
++ dev_err(ksdev, "caam_sm_test: no keystore units available\n");
++
++ /*
++ * MX6 bootloader stores some stuff in unit 0, so let's
++ * use 1 or above
++ */
++ if (units < 2) {
++ dev_err(ksdev, "caam_sm_test: insufficient keystore units\n");
++ return -ENODEV;
++ }
++ unit = 1;
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: %d keystore units available\n", units);
++#endif
++
++ /* Initialize/Establish Keystore */
++ sm_establish_keystore(ksdev, unit); /* Initalize store in #1 */
++
++ /*
++ * Top of main test thread
++ */
++
++ /* Allocate test data blocks (input, intermediate, output) */
++ syminp = kmalloc(256, GFP_KERNEL | GFP_DMA);
++ symint = kmalloc(256, GFP_KERNEL | GFP_DMA);
++ symout = kmalloc(256, GFP_KERNEL | GFP_DMA);
++ if ((syminp == NULL) || (symint == NULL) || (symout == NULL)) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "caam_sm_test: can't get test data buffers\n");
++ goto freemem;
++ }
++
++ /* Allocate storage for 3 black keys: encapsulated 8, 16, 32 */
++ black_key_des = kmalloc(16, GFP_KERNEL | GFP_DMA); /* padded to 16... */
++ black_key_aes128 = kmalloc(16, GFP_KERNEL | GFP_DMA);
++ black_key_aes256 = kmalloc(16, GFP_KERNEL | GFP_DMA);
++ if ((black_key_des == NULL) || (black_key_aes128 == NULL) ||
++ (black_key_aes256 == NULL)) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "caam_sm_test: can't black key buffers\n");
++ goto freemem;
++ }
++
++ clear_key_des = kmalloc(8, GFP_KERNEL | GFP_DMA);
++ clear_key_aes128 = kmalloc(16, GFP_KERNEL | GFP_DMA);
++ clear_key_aes256 = kmalloc(32, GFP_KERNEL | GFP_DMA);
++ if ((clear_key_des == NULL) || (clear_key_aes128 == NULL) ||
++ (clear_key_aes256 == NULL)) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "caam_sm_test: can't get clear key buffers\n");
++ goto freemem;
++ }
++
++ /* Allocate storage for job descriptor */
++ jdesc = kmalloc(8 * sizeof(u32), GFP_KERNEL | GFP_DMA);
++ if (jdesc == NULL) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "caam_sm_test: can't get descriptor buffers\n");
++ goto freemem;
++ }
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: all buffers allocated\n");
++#endif
++
++ /* Load up input data block, clear outputs */
++ memcpy(syminp, symdata, 256);
++ memset(symint, 0, 256);
++ memset(symout, 0, 256);
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[0], syminp[1], syminp[2], syminp[3],
++ syminp[4], syminp[5], syminp[6], syminp[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[0], symout[1], symout[2], symout[3],
++ symout[4], symout[5], symout[6], symout[7]);
++
++ dev_info(ksdev, "caam_sm_test: data buffers initialized\n");
++#endif
++
++ /* Load up clear keys */
++ memcpy(clear_key_des, symkey, 8);
++ memcpy(clear_key_aes128, symkey, 16);
++ memcpy(clear_key_aes256, symkey, 32);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: all clear keys loaded\n");
++#endif
++
++ /*
++ * Place clear keys in keystore.
++ * All the interesting stuff happens here.
++ */
++ /* 8 bit DES key */
++ stat = sm_keystore_slot_alloc(ksdev, unit, 8, &keyslot_des);
++ if (stat)
++ goto freemem;
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: 8 byte key slot in %d\n", keyslot_des);
++#endif
++ stat = sm_keystore_slot_load(ksdev, unit, keyslot_des, clear_key_des,
++ 8);
++ if (stat) {
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: can't load 8 byte key in %d\n",
++ keyslot_des);
++#endif
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++
++ /* 16 bit AES key */
++ stat = sm_keystore_slot_alloc(ksdev, unit, 16, &keyslot_aes128);
++ if (stat) {
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: 16 byte key slot in %d\n",
++ keyslot_aes128);
++#endif
++ stat = sm_keystore_slot_load(ksdev, unit, keyslot_aes128,
++ clear_key_aes128, 16);
++ if (stat) {
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: can't load 16 byte key in %d\n",
++ keyslot_aes128);
++#endif
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++
++ /* 32 bit AES key */
++ stat = sm_keystore_slot_alloc(ksdev, unit, 32, &keyslot_aes256);
++ if (stat) {
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: 32 byte key slot in %d\n",
++ keyslot_aes256);
++#endif
++ stat = sm_keystore_slot_load(ksdev, unit, keyslot_aes256,
++ clear_key_aes256, 32);
++ if (stat) {
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: can't load 32 byte key in %d\n",
++ keyslot_aes128);
++#endif
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes256);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ goto freemem;
++ }
++
++ /* Encapsulate all keys as SM blobs */
++ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_des,
++ keyslot_des, 8, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't encapsulate DES key\n");
++ goto freekeys;
++ }
++
++ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_aes128,
++ keyslot_aes128, 16, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't encapsulate AES128 key\n");
++ goto freekeys;
++ }
++
++ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_aes256,
++ keyslot_aes256, 32, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't encapsulate AES256 key\n");
++ goto freekeys;
++ }
++
++ /* Now decapsulate as black key blobs */
++ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_des,
++ keyslot_des, 8, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't decapsulate DES key\n");
++ goto freekeys;
++ }
++
++ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_aes128,
++ keyslot_aes128, 16, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't decapsulate AES128 key\n");
++ goto freekeys;
++ }
++
++ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_aes256,
++ keyslot_aes256, 32, skeymod, 8);
++ if (stat) {
++ dev_info(ksdev, "caam_sm_test: can't decapsulate AES128 key\n");
++ goto freekeys;
++ }
++
++ /* Extract 8/16/32 byte black keys */
++ sm_keystore_slot_read(ksdev, unit, keyslot_des, 8, black_key_des);
++ sm_keystore_slot_read(ksdev, unit, keyslot_aes128, 16,
++ black_key_aes128);
++ sm_keystore_slot_read(ksdev, unit, keyslot_aes256, 32,
++ black_key_aes256);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: all black keys extracted\n");
++#endif
++
++ /* DES encrypt using 8 byte black key */
++ black_key_des_dma = dma_map_single(ksdev, black_key_des, 8,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, black_key_des_dma, 8, DMA_TO_DEVICE);
++ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, black_key_des_dma, 8, syminp_dma,
++ symint_dma, 256,
++ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_DES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, black_key_des_dma, 8, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "input block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[0], syminp[1], syminp[2], syminp[3],
++ syminp[4], syminp[5], syminp[6], syminp[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[8], syminp[9], syminp[10], syminp[11],
++ syminp[12], syminp[13], syminp[14], syminp[15]);
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "caam_sm_test: encrypt cycle with 8 byte key\n");
++#endif
++
++ /* DES decrypt using 8 byte clear key */
++ clear_key_des_dma = dma_map_single(ksdev, clear_key_des, 8,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, clear_key_des_dma, 8, DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, clear_key_des_dma, 8, symint_dma,
++ symout_dma, 256,
++ OP_ALG_DECRYPT | OP_ALG_ALGSEL_DES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, clear_key_des_dma, 8, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "decrypted block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[0], symout[1], symout[2], symout[3],
++ symout[4], symout[5], symout[6], symout[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[8], symout[9], symout[10], symout[11],
++ symout[12], symout[13], symout[14], symout[15]);
++ dev_info(ksdev, "caam_sm_test: decrypt cycle with 8 byte key\n");
++#endif
++
++ /* Check result */
++ if (memcmp(symout, syminp, 256)) {
++ dev_info(ksdev, "caam_sm_test: 8-byte key test mismatch\n");
++ rtnval = -1;
++ goto freekeys;
++ } else
++ dev_info(ksdev, "caam_sm_test: 8-byte key test match OK\n");
++
++ /* AES-128 encrypt using 16 byte black key */
++ black_key_aes128_dma = dma_map_single(ksdev, black_key_aes128, 16,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, black_key_aes128_dma, 16,
++ DMA_TO_DEVICE);
++ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, black_key_aes128_dma, 16, syminp_dma,
++ symint_dma, 256,
++ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_AES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, black_key_aes128_dma, 16, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "input block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[0], syminp[1], syminp[2], syminp[3],
++ syminp[4], syminp[5], syminp[6], syminp[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[8], syminp[9], syminp[10], syminp[11],
++ syminp[12], syminp[13], syminp[14], syminp[15]);
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "caam_sm_test: encrypt cycle with 16 byte key\n");
++#endif
++
++ /* AES-128 decrypt using 16 byte clear key */
++ clear_key_aes128_dma = dma_map_single(ksdev, clear_key_aes128, 16,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, clear_key_aes128_dma, 16,
++ DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, clear_key_aes128_dma, 16, symint_dma,
++ symout_dma, 256,
++ OP_ALG_DECRYPT | OP_ALG_ALGSEL_AES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, clear_key_aes128_dma, 16, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "decrypted block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[0], symout[1], symout[2], symout[3],
++ symout[4], symout[5], symout[6], symout[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[8], symout[9], symout[10], symout[11],
++ symout[12], symout[13], symout[14], symout[15]);
++ dev_info(ksdev, "caam_sm_test: decrypt cycle with 16 byte key\n");
++#endif
++
++ /* Check result */
++ if (memcmp(symout, syminp, 256)) {
++ dev_info(ksdev, "caam_sm_test: 16-byte key test mismatch\n");
++ rtnval = -1;
++ goto freekeys;
++ } else
++ dev_info(ksdev, "caam_sm_test: 16-byte key test match OK\n");
++
++ /* AES-256 encrypt using 32 byte black key */
++ black_key_aes256_dma = dma_map_single(ksdev, black_key_aes256, 32,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, black_key_aes256_dma, 32,
++ DMA_TO_DEVICE);
++ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, black_key_aes256_dma, 32, syminp_dma,
++ symint_dma, 256,
++ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_AES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, black_key_aes256_dma, 32, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "input block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[0], syminp[1], syminp[2], syminp[3],
++ syminp[4], syminp[5], syminp[6], syminp[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ syminp[8], syminp[9], syminp[10], syminp[11],
++ syminp[12], syminp[13], syminp[14], syminp[15]);
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "caam_sm_test: encrypt cycle with 32 byte key\n");
++#endif
++
++ /* AES-256 decrypt using 32-byte black key */
++ clear_key_aes256_dma = dma_map_single(ksdev, clear_key_aes256, 32,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, clear_key_aes256_dma, 32,
++ DMA_TO_DEVICE);
++ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE);
++ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE);
++
++ jdescsz = mk_job_desc(jdesc, clear_key_aes256_dma, 32, symint_dma,
++ symout_dma, 256,
++ OP_ALG_DECRYPT | OP_ALG_ALGSEL_AES, 0);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "jobdesc:\n");
++ dev_info(ksdev, "0x%08x\n", jdesc[0]);
++ dev_info(ksdev, "0x%08x\n", jdesc[1]);
++ dev_info(ksdev, "0x%08x\n", jdesc[2]);
++ dev_info(ksdev, "0x%08x\n", jdesc[3]);
++ dev_info(ksdev, "0x%08x\n", jdesc[4]);
++ dev_info(ksdev, "0x%08x\n", jdesc[5]);
++ dev_info(ksdev, "0x%08x\n", jdesc[6]);
++ dev_info(ksdev, "0x%08x\n", jdesc[7]);
++#endif
++
++ jstat = exec_test_job(ksdev, jdesc);
++
++ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE);
++ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE);
++ dma_unmap_single(ksdev, clear_key_aes256_dma, 32, DMA_TO_DEVICE);
++
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "intermediate block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[0], symint[1], symint[2], symint[3],
++ symint[4], symint[5], symint[6], symint[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symint[8], symint[9], symint[10], symint[11],
++ symint[12], symint[13], symint[14], symint[15]);
++ dev_info(ksdev, "decrypted block:\n");
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[0], symout[1], symout[2], symout[3],
++ symout[4], symout[5], symout[6], symout[7]);
++ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \
++ "0x%02x 0x%02x 0x%02x 0x%02x\n",
++ symout[8], symout[9], symout[10], symout[11],
++ symout[12], symout[13], symout[14], symout[15]);
++ dev_info(ksdev, "caam_sm_test: decrypt cycle with 32 byte key\n");
++#endif
++
++ /* Check result */
++ if (memcmp(symout, syminp, 256)) {
++ dev_info(ksdev, "caam_sm_test: 32-byte key test mismatch\n");
++ rtnval = -1;
++ goto freekeys;
++ } else
++ dev_info(ksdev, "caam_sm_test: 32-byte key test match OK\n");
++
++
++ /* Remove 8/16/32 byte keys from keystore */
++freekeys:
++ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_des);
++ if (stat)
++ dev_info(ksdev, "caam_sm_test: can't release slot %d\n",
++ keyslot_des);
++
++ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128);
++ if (stat)
++ dev_info(ksdev, "caam_sm_test: can't release slot %d\n",
++ keyslot_aes128);
++
++ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes256);
++ if (stat)
++ dev_info(ksdev, "caam_sm_test: can't release slot %d\n",
++ keyslot_aes256);
++
++
++ /* Free resources */
++freemem:
++#ifdef SM_TEST_DETAIL
++ dev_info(ksdev, "caam_sm_test: cleaning up\n");
++#endif
++ kfree(syminp);
++ kfree(symint);
++ kfree(symout);
++ kfree(clear_key_des);
++ kfree(clear_key_aes128);
++ kfree(clear_key_aes256);
++ kfree(black_key_des);
++ kfree(black_key_aes128);
++ kfree(black_key_aes256);
++ kfree(jdesc);
++
++ /* Disconnect from keystore and leave */
++ sm_release_keystore(ksdev, unit);
++
++ return rtnval;
++}
++EXPORT_SYMBOL(caam_sm_example_init);
++
++void caam_sm_example_shutdown(void)
++{
++ /* unused in present version */
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return;
++
++ of_node_get(dev_node);
++
++}
++
++static int __init caam_sm_test_init(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return -ENODEV;
++
++ of_node_put(dev_node);
++
++ caam_sm_example_init(pdev);
++
++ return 0;
++}
++
++
++/* Module-based initialization needs to wait for dev tree */
++#ifdef CONFIG_OF
++module_init(caam_sm_test_init);
++module_exit(caam_sm_example_shutdown);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM Keystore Usage Example");
++MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD");
++#endif
+diff -Nur linux-3.10.30.orig/drivers/crypto/caam/snvsregs.h linux-linaro-stable-mx6/drivers/crypto/caam/snvsregs.h
+--- linux-3.10.30.orig/drivers/crypto/caam/snvsregs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/crypto/caam/snvsregs.h 2014-05-15 20:33:46.853933543 +0200
+@@ -0,0 +1,237 @@
++/*
++ * SNVS hardware register-level view
++ *
++ * Copyright (C) 2013 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#ifndef SNVSREGS_H
++#define SNVSREGS_H
++
++#include <linux/types.h>
++#include <linux/io.h>
++
++/*
++ * SNVS High Power Domain
++ * Includes security violations, HA counter, RTC, alarm
++ */
++struct snvs_hp {
++ u32 lock;
++ u32 cmd;
++ u32 ctl;
++ u32 secvio_int_en; /* Security Violation Interrupt Enable */
++ u32 secvio_int_ctl; /* Security Violation Interrupt Control */
++ u32 status;
++ u32 secvio_status; /* Security Violation Status */
++ u32 ha_counteriv; /* High Assurance Counter IV */
++ u32 ha_counter; /* High Assurance Counter */
++ u32 rtc_msb; /* Real Time Clock/Counter MSB */
++ u32 rtc_lsb; /* Real Time Counter LSB */
++ u32 time_alarm_msb; /* Time Alarm MSB */
++ u32 time_alarm_lsb; /* Time Alarm LSB */
++};
++
++#define HP_LOCK_HAC_LCK 0x00040000
++#define HP_LOCK_HPSICR_LCK 0x00020000
++#define HP_LOCK_HPSVCR_LCK 0x00010000
++#define HP_LOCK_MKEYSEL_LCK 0x00000200
++#define HP_LOCK_TAMPCFG_LCK 0x00000100
++#define HP_LOCK_TAMPFLT_LCK 0x00000080
++#define HP_LOCK_SECVIO_LCK 0x00000040
++#define HP_LOCK_GENP_LCK 0x00000020
++#define HP_LOCK_MONOCTR_LCK 0x00000010
++#define HP_LOCK_CALIB_LCK 0x00000008
++#define HP_LOCK_SRTC_LCK 0x00000004
++#define HP_LOCK_ZMK_RD_LCK 0x00000002
++#define HP_LOCK_ZMK_WT_LCK 0x00000001
++
++#define HP_CMD_NONPRIV_AXS 0x80000000
++#define HP_CMD_HAC_STOP 0x00080000
++#define HP_CMD_HAC_CLEAR 0x00040000
++#define HP_CMD_HAC_LOAD 0x00020000
++#define HP_CMD_HAC_CFG_EN 0x00010000
++#define HP_CMD_SNVS_MSTR_KEY 0x00002000
++#define HP_CMD_PROG_ZMK 0x00001000
++#define HP_CMD_SW_LPSV 0x00000400
++#define HP_CMD_SW_FSV 0x00000200
++#define HP_CMD_SW_SV 0x00000100
++#define HP_CMD_LP_SWR_DIS 0x00000020
++#define HP_CMD_LP_SWR 0x00000010
++#define HP_CMD_SSM_SFNS_DIS 0x00000004
++#define HP_CMD_SSM_ST_DIS 0x00000002
++#define HP_CMD_SMM_ST 0x00000001
++
++#define HP_CTL_TIME_SYNC 0x00010000
++#define HP_CTL_CAL_VAL_SHIFT 10
++#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT)
++#define HP_CTL_CALIB_EN 0x00000100
++#define HP_CTL_PI_FREQ_SHIFT 4
++#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT)
++#define HP_CTL_PI_EN 0x00000008
++#define HP_CTL_TIMEALARM_EN 0x00000002
++#define HP_CTL_RTC_EN 0x00000001
++
++#define HP_SECVIO_INTEN_EN 0x10000000
++#define HP_SECVIO_INTEN_SRC5 0x00000020
++#define HP_SECVIO_INTEN_SRC4 0x00000010
++#define HP_SECVIO_INTEN_SRC3 0x00000008
++#define HP_SECVIO_INTEN_SRC2 0x00000004
++#define HP_SECVIO_INTEN_SRC1 0x00000002
++#define HP_SECVIO_INTEN_SRC0 0x00000001
++#define HP_SECVIO_INTEN_ALL 0x8000003f
++
++#define HP_SECVIO_ICTL_CFG_SHIFT 30
++#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT)
++#define HP_SECVIO_ICTL_CFG5_SHIFT 5
++#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT)
++#define HP_SECVIO_ICTL_CFG_DISABLE 0
++#define HP_SECVIO_ICTL_CFG_NONFATAL 1
++#define HP_SECVIO_ICTL_CFG_FATAL 2
++#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010
++#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008
++#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004
++#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002
++#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001
++
++#define HP_STATUS_ZMK_ZERO 0x80000000
++#define HP_STATUS_OTPMK_ZERO 0x08000000
++#define HP_STATUS_OTPMK_SYN_SHIFT 16
++#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT)
++#define HP_STATUS_SSM_ST_SHIFT 8
++#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT)
++#define HP_STATUS_SSM_ST_INIT 0
++#define HP_STATUS_SSM_ST_HARDFAIL 1
++#define HP_STATUS_SSM_ST_SOFTFAIL 3
++#define HP_STATUS_SSM_ST_INITINT 8
++#define HP_STATUS_SSM_ST_CHECK 9
++#define HP_STATUS_SSM_ST_NONSECURE 11
++#define HP_STATUS_SSM_ST_TRUSTED 13
++#define HP_STATUS_SSM_ST_SECURE 15
++
++#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */
++#define HP_SECVIOST_ZMK_SYN_SHIFT 16
++#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT)
++#define HP_SECVIOST_SECVIO5 0x00000020
++#define HP_SECVIOST_SECVIO4 0x00000010
++#define HP_SECVIOST_SECVIO3 0x00000008
++#define HP_SECVIOST_SECVIO2 0x00000004
++#define HP_SECVIOST_SECVIO1 0x00000002
++#define HP_SECVIOST_SECVIO0 0x00000001
++#define HP_SECVIOST_SECVIOMASK 0x0000003f
++
++/*
++ * SNVS Low Power Domain
++ * Includes glitch detector, SRTC, alarm, monotonic counter, ZMK
++ */
++struct snvs_lp {
++ u32 lock;
++ u32 ctl;
++ u32 mstr_key_ctl; /* Master Key Control */
++ u32 secvio_ctl; /* Security Violation Control */
++ u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */
++ u32 tamper_det_cfg; /* Tamper Detectors Configuration */
++ u32 status;
++ u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */
++ u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */
++ u32 time_alarm; /* Time Alarm */
++ u32 smc_msb; /* Secure Monotonic Counter MSB */
++ u32 smc_lsb; /* Secure Monotonic Counter LSB */
++ u32 pwr_glitch_det; /* Power Glitch Detector */
++ u32 gen_purpose;
++ u32 zmk[8]; /* Zeroizable Master Key */
++};
++
++#define LP_LOCK_MKEYSEL_LCK 0x00000200
++#define LP_LOCK_TAMPDET_LCK 0x00000100
++#define LP_LOCK_TAMPFLT_LCK 0x00000080
++#define LP_LOCK_SECVIO_LCK 0x00000040
++#define LP_LOCK_GENP_LCK 0x00000020
++#define LP_LOCK_MONOCTR_LCK 0x00000010
++#define LP_LOCK_CALIB_LCK 0x00000008
++#define LP_LOCK_SRTC_LCK 0x00000004
++#define LP_LOCK_ZMK_RD_LCK 0x00000002
++#define LP_LOCK_ZMK_WT_LCK 0x00000001
++
++#define LP_CTL_CAL_VAL_SHIFT 10
++#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT)
++#define LP_CTL_CALIB_EN 0x00000100
++#define LP_CTL_SRTC_INVAL_EN 0x00000010
++#define LP_CTL_WAKE_INT_EN 0x00000008
++#define LP_CTL_MONOCTR_EN 0x00000004
++#define LP_CTL_TIMEALARM_EN 0x00000002
++#define LP_CTL_SRTC_EN 0x00000001
++
++#define LP_MKEYCTL_ZMKECC_SHIFT 8
++#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT)
++#define LP_MKEYCTL_ZMKECC_EN 0x00000010
++#define LP_MKEYCTL_ZMKECC_VAL 0x00000008
++#define LP_MKEYCTL_ZMKECC_PROG 0x00000004
++#define LP_MKEYCTL_MKSEL_SHIFT 0
++#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT)
++#define LP_MKEYCTL_MK_OTP 0
++#define LP_MKEYCTL_MK_ZMK 2
++#define LP_MKEYCTL_MK_COMB 3
++
++#define LP_SECVIO_CTL_SRC5 0x20
++#define LP_SECVIO_CTL_SRC4 0x10
++#define LP_SECVIO_CTL_SRC3 0x08
++#define LP_SECVIO_CTL_SRC2 0x04
++#define LP_SECVIO_CTL_SRC1 0x02
++#define LP_SECVIO_CTL_SRC0 0x01
++
++#define LP_TAMPFILT_EXT2_EN 0x80000000
++#define LP_TAMPFILT_EXT2_SHIFT 24
++#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT)
++#define LP_TAMPFILT_EXT1_EN 0x00800000
++#define LP_TAMPFILT_EXT1_SHIFT 16
++#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT)
++#define LP_TAMPFILT_WM_EN 0x00000080
++#define LP_TAMPFILT_WM_SHIFT 0
++#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT)
++
++#define LP_TAMPDET_OSC_BPS 0x10000000
++#define LP_TAMPDET_VRC_SHIFT 24
++#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT)
++#define LP_TAMPDET_HTDC_SHIFT 20
++#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT)
++#define LP_TAMPDET_LTDC_SHIFT 16
++#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT)
++#define LP_TAMPDET_POR_OBS 0x00008000
++#define LP_TAMPDET_PFD_OBS 0x00004000
++#define LP_TAMPDET_ET2_EN 0x00000400
++#define LP_TAMPDET_ET1_EN 0x00000200
++#define LP_TAMPDET_WMT2_EN 0x00000100
++#define LP_TAMPDET_WMT1_EN 0x00000080
++#define LP_TAMPDET_VT_EN 0x00000040
++#define LP_TAMPDET_TT_EN 0x00000020
++#define LP_TAMPDET_CT_EN 0x00000010
++#define LP_TAMPDET_MCR_EN 0x00000004
++#define LP_TAMPDET_SRTCR_EN 0x00000002
++
++#define LP_STATUS_SECURE
++#define LP_STATUS_NONSECURE
++#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */
++#define LP_STATUS_EXT_SECVIO 0x00010000
++#define LP_STATUS_ET2 0x00000400
++#define LP_STATUS_ET1 0x00000200
++#define LP_STATUS_WMT2 0x00000100
++#define LP_STATUS_WMT1 0x00000080
++#define LP_STATUS_VTD 0x00000040
++#define LP_STATUS_TTD 0x00000020
++#define LP_STATUS_CTD 0x00000010
++#define LP_STATUS_PGD 0x00000008
++#define LP_STATUS_MCR 0x00000004
++#define LP_STATUS_SRTCR 0x00000002
++#define LP_STATUS_LPTA 0x00000001
++
++/* Full SNVS register page, including version/options */
++struct snvs_full {
++ struct snvs_hp hp;
++ struct snvs_lp lp;
++ u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */
++
++ /* Version / Revision / Option ID space - end of register page */
++ u32 vid; /* 0xbf8 HP Version ID (VID 1) */
++ u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */
++};
++
++#endif /* SNVSREGS_H */
+diff -Nur linux-3.10.30.orig/drivers/dma/imx-sdma.c linux-linaro-stable-mx6/drivers/dma/imx-sdma.c
+--- linux-3.10.30.orig/drivers/dma/imx-sdma.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/dma/imx-sdma.c 2014-05-15 20:33:46.909933947 +0200
+@@ -7,7 +7,7 @@
+ *
+ * Based on code from Freescale:
+ *
+- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+@@ -29,6 +29,7 @@
+ #include <linux/semaphore.h>
+ #include <linux/spinlock.h>
+ #include <linux/device.h>
++#include <linux/genalloc.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/firmware.h>
+ #include <linux/slab.h>
+@@ -36,6 +37,7 @@
+ #include <linux/dmaengine.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <linux/of_dma.h>
+
+ #include <asm/irq.h>
+ #include <linux/platform_data/dma-imx-sdma.h>
+@@ -231,6 +233,14 @@
+
+ struct sdma_engine;
+
++enum sdma_mode {
++ SDMA_MODE_INVALID = 0,
++ SDMA_MODE_LOOP,
++ SDMA_MODE_NORMAL,
++ SDMA_MODE_P2P,
++ SDMA_MODE_NO_BD,
++};
++
+ /**
+ * struct sdma_channel - housekeeping for a SDMA channel
+ *
+@@ -244,6 +254,7 @@
+ * @buf_tail ID of the buffer that was processed
+ * @done channel completion
+ * @num_bd max NUM_BD. number of descriptors currently handling
++ * @bd_iram flag indicating the memory location of buffer descriptor
+ */
+ struct sdma_channel {
+ struct sdma_engine *sdma;
+@@ -258,12 +269,16 @@
+ unsigned int num_bd;
+ struct sdma_buffer_descriptor *bd;
+ dma_addr_t bd_phys;
++ bool bd_iram;
+ unsigned int pc_from_device, pc_to_device;
+- unsigned long flags;
+- dma_addr_t per_address;
++ unsigned int device_to_device;
++ unsigned int other_script;
++ enum sdma_mode mode;
++ dma_addr_t per_address, per_address2;
+ unsigned long event_mask[2];
+ unsigned long watermark_level;
+ u32 shp_addr, per_addr;
++ u32 data_addr1, data_addr2;
+ struct dma_chan chan;
+ spinlock_t lock;
+ struct dma_async_tx_descriptor desc;
+@@ -273,8 +288,6 @@
+ struct tasklet_struct tasklet;
+ };
+
+-#define IMX_DMA_SG_LOOP BIT(0)
+-
+ #define MAX_DMA_CHANNELS 32
+ #define MXC_SDMA_DEFAULT_PRIORITY 1
+ #define MXC_SDMA_MIN_PRIORITY 1
+@@ -326,6 +339,7 @@
+ struct clk *clk_ahb;
+ spinlock_t channel_0_lock;
+ struct sdma_script_start_addrs *script_addrs;
++ struct gen_pool *iram_pool;
+ };
+
+ static struct platform_device_id sdma_devtypes[] = {
+@@ -435,12 +449,14 @@
+ dma_addr_t buf_phys;
+ int ret;
+ unsigned long flags;
++ bool use_iram = true;
+
+- buf_virt = dma_alloc_coherent(NULL,
+- size,
+- &buf_phys, GFP_KERNEL);
++ buf_virt = gen_pool_dma_alloc(sdma->iram_pool, size, &buf_phys);
+ if (!buf_virt) {
+- return -ENOMEM;
++ use_iram = false;
++ buf_virt = dma_alloc_coherent(NULL, size, &buf_phys, GFP_KERNEL);
++ if (!buf_virt)
++ return -ENOMEM;
+ }
+
+ spin_lock_irqsave(&sdma->channel_0_lock, flags);
+@@ -457,7 +473,10 @@
+
+ spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
+
+- dma_free_coherent(NULL, size, buf_virt, buf_phys);
++ if (use_iram)
++ gen_pool_free(sdma->iram_pool, (unsigned long)buf_virt, size);
++ else
++ dma_free_coherent(NULL, size, buf_virt, buf_phys);
+
+ return ret;
+ }
+@@ -542,16 +561,33 @@
+ sdmac->desc.callback(sdmac->desc.callback_param);
+ }
+
++static void sdma_handle_other_intr(struct sdma_channel *sdmac)
++{
++ if (sdmac->desc.callback)
++ sdmac->desc.callback(sdmac->desc.callback_param);
++}
++
+ static void sdma_tasklet(unsigned long data)
+ {
+ struct sdma_channel *sdmac = (struct sdma_channel *) data;
++ struct sdma_engine *sdma = sdmac->sdma;
+
+ complete(&sdmac->done);
+
+- if (sdmac->flags & IMX_DMA_SG_LOOP)
++ switch (sdmac->mode) {
++ case SDMA_MODE_LOOP:
+ sdma_handle_channel_loop(sdmac);
+- else
++ break;
++ case SDMA_MODE_NORMAL:
+ mxc_sdma_handle_channel_normal(sdmac);
++ break;
++ case SDMA_MODE_NO_BD:
++ sdma_handle_other_intr(sdmac);
++ break;
++ default:
++ dev_err(sdma->dev, "invalid SDMA MODE!\n");
++ break;
++ }
+ }
+
+ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
+@@ -589,9 +625,12 @@
+ * two peripherals or memory-to-memory transfers
+ */
+ int per_2_per = 0, emi_2_emi = 0;
++ int other = 0;
+
+ sdmac->pc_from_device = 0;
+ sdmac->pc_to_device = 0;
++ sdmac->device_to_device = 0;
++ sdmac->other_script = 0;
+
+ switch (peripheral_type) {
+ case IMX_DMATYPE_MEMORY:
+@@ -624,6 +663,9 @@
+ emi_2_per = sdma->script_addrs->mcu_2_app_addr;
+ break;
+ case IMX_DMATYPE_SSI_SP:
++ per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
++ emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
++ break;
+ case IMX_DMATYPE_MMC:
+ case IMX_DMATYPE_SDHC:
+ case IMX_DMATYPE_CSPI_SP:
+@@ -633,8 +675,8 @@
+ emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
+ break;
+ case IMX_DMATYPE_ASRC:
+- per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
+- emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
++ per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
++ emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
+ per_2_per = sdma->script_addrs->per_2_per_addr;
+ break;
+ case IMX_DMATYPE_MSHC:
+@@ -651,12 +693,17 @@
+ case IMX_DMATYPE_IPU_MEMORY:
+ emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
+ break;
++ case IMX_DMATYPE_HDMI:
++ other = sdma->script_addrs->hdmi_dma_addr;
++ break;
+ default:
+ break;
+ }
+
+ sdmac->pc_from_device = per_2_emi;
+ sdmac->pc_to_device = emi_2_per;
++ sdmac->device_to_device = per_2_per;
++ sdmac->other_script = other;
+ }
+
+ static int sdma_load_context(struct sdma_channel *sdmac)
+@@ -669,11 +716,14 @@
+ int ret;
+ unsigned long flags;
+
+- if (sdmac->direction == DMA_DEV_TO_MEM) {
++ if (sdmac->direction == DMA_DEV_TO_MEM)
+ load_address = sdmac->pc_from_device;
+- } else {
++ else if (sdmac->direction == DMA_DEV_TO_DEV)
++ load_address = sdmac->device_to_device;
++ else if (sdmac->direction == DMA_MEM_TO_DEV)
+ load_address = sdmac->pc_to_device;
+- }
++ else
++ load_address = sdmac->other_script;
+
+ if (load_address < 0)
+ return load_address;
+@@ -693,11 +743,16 @@
+ /* Send by context the event mask,base address for peripheral
+ * and watermark level
+ */
+- context->gReg[0] = sdmac->event_mask[1];
+- context->gReg[1] = sdmac->event_mask[0];
+- context->gReg[2] = sdmac->per_addr;
+- context->gReg[6] = sdmac->shp_addr;
+- context->gReg[7] = sdmac->watermark_level;
++ if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
++ context->gReg[4] = sdmac->data_addr1;
++ context->gReg[6] = sdmac->data_addr2;
++ } else {
++ context->gReg[0] = sdmac->event_mask[1];
++ context->gReg[1] = sdmac->event_mask[0];
++ context->gReg[2] = sdmac->per_addr;
++ context->gReg[6] = sdmac->shp_addr;
++ context->gReg[7] = sdmac->watermark_level;
++ }
+
+ bd0->mode.command = C0_SETDM;
+ bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+@@ -722,6 +777,7 @@
+
+ static int sdma_config_channel(struct sdma_channel *sdmac)
+ {
++ struct imx_dma_data *data = sdmac->chan.private;
+ int ret;
+
+ sdma_disable_channel(sdmac);
+@@ -730,12 +786,19 @@
+ sdmac->event_mask[1] = 0;
+ sdmac->shp_addr = 0;
+ sdmac->per_addr = 0;
++ sdmac->data_addr1 = 0;
++ sdmac->data_addr2 = 0;
+
+ if (sdmac->event_id0) {
+ if (sdmac->event_id0 >= sdmac->sdma->num_events)
+ return -EINVAL;
+ sdma_event_enable(sdmac, sdmac->event_id0);
+ }
++ if (sdmac->event_id1) {
++ if (sdmac->event_id1 >= sdmac->sdma->num_events)
++ return -EINVAL;
++ sdma_event_enable(sdmac, sdmac->event_id1);
++ }
+
+ switch (sdmac->peripheral_type) {
+ case IMX_DMATYPE_DSP:
+@@ -755,19 +818,75 @@
+ (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
+ /* Handle multiple event channels differently */
+ if (sdmac->event_id1) {
+- sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
+- if (sdmac->event_id1 > 31)
+- __set_bit(31, &sdmac->watermark_level);
+- sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
+- if (sdmac->event_id0 > 31)
+- __set_bit(30, &sdmac->watermark_level);
++ if (sdmac->event_id0 > 31) {
++ sdmac->event_mask[0] |= 0;
++ __set_bit(28, &sdmac->watermark_level);
++ sdmac->event_mask[1] |=
++ BIT(sdmac->event_id0 % 32);
++ } else {
++ sdmac->event_mask[1] |= 0;
++ sdmac->event_mask[0] |=
++ BIT(sdmac->event_id0 % 32);
++ }
++ if (sdmac->event_id1 > 31) {
++ sdmac->event_mask[0] |= 0;
++ __set_bit(29, &sdmac->watermark_level);
++ sdmac->event_mask[1] |=
++ BIT(sdmac->event_id1 % 32);
++ } else {
++ sdmac->event_mask[1] |= 0;
++ sdmac->event_mask[0] |=
++ BIT(sdmac->event_id1 % 32);
++ }
++ /* BIT 11:
++ * 1 : Source on SPBA
++ * 0 : Source on AIPS
++ */
++ __set_bit(11, &sdmac->watermark_level);
++ /* BIT 12:
++ * 1 : Destination on SPBA
++ * 0 : Destination on AIPS
++ */
++ __set_bit(12, &sdmac->watermark_level);
++ __set_bit(31, &sdmac->watermark_level);
++ /* BIT 31:
++ * 1 : Amount of samples to be transferred is
++ * unknown and script will keep on transferring
++ * samples as long as both events are detected
++ * and script must be manually stopped by the
++ * application.
++ * 0 : The amount of samples to be is equal to
++ * the count field of mode word
++ * */
++ __set_bit(25, &sdmac->watermark_level);
++ __clear_bit(24, &sdmac->watermark_level);
+ } else {
+- __set_bit(sdmac->event_id0, sdmac->event_mask);
++ if (sdmac->event_id0 > 31) {
++ sdmac->event_mask[0] = 0;
++ sdmac->event_mask[1] |=
++ BIT(sdmac->event_id0 % 32);
++ } else {
++ sdmac->event_mask[0] |=
++ BIT(sdmac->event_id0 % 32);
++ sdmac->event_mask[1] = 0;
++ }
+ }
+ /* Watermark Level */
+ sdmac->watermark_level |= sdmac->watermark_level;
+ /* Address */
+- sdmac->shp_addr = sdmac->per_address;
++ if (sdmac->direction == DMA_DEV_TO_DEV) {
++ sdmac->shp_addr = sdmac->per_address2;
++ sdmac->per_addr = sdmac->per_address;
++ } else if (sdmac->direction == DMA_TRANS_NONE) {
++ if (sdmac->peripheral_type != IMX_DMATYPE_HDMI ||
++ !data->data_addr1 || !data->data_addr2)
++ return -EINVAL;
++ sdmac->data_addr1 = *(u32 *)data->data_addr1;
++ sdmac->data_addr2 = *(u32 *)data->data_addr2;
++ sdmac->watermark_level = 0;
++ } else {
++ sdmac->shp_addr = sdmac->per_address;
++ }
+ } else {
+ sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
+ }
+@@ -799,10 +918,15 @@
+ int channel = sdmac->channel;
+ int ret = -EBUSY;
+
+- sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
++ sdmac->bd_iram = true;
++ sdmac->bd = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, &sdmac->bd_phys);
+ if (!sdmac->bd) {
+- ret = -ENOMEM;
+- goto out;
++ sdmac->bd_iram = false;
++ sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
++ if (!sdmac->bd) {
++ ret = -ENOMEM;
++ goto out;
++ }
+ }
+
+ memset(sdmac->bd, 0, PAGE_SIZE);
+@@ -863,7 +987,8 @@
+ }
+
+ sdmac->peripheral_type = data->peripheral_type;
+- sdmac->event_id0 = data->dma_request;
++ sdmac->event_id0 = data->dma_request0;
++ sdmac->event_id1 = data->dma_request1;
+
+ clk_enable(sdmac->sdma->clk_ipg);
+ clk_enable(sdmac->sdma->clk_ahb);
+@@ -881,6 +1006,9 @@
+ /* txd.flags will be overwritten in prep funcs */
+ sdmac->desc.flags = DMA_CTRL_ACK;
+
++ /* Set SDMA channel mode to unvalid to avoid misconfig */
++ sdmac->mode = SDMA_MODE_INVALID;
++
+ return 0;
+ }
+
+@@ -901,7 +1029,10 @@
+
+ sdma_set_channel_priority(sdmac, 0);
+
+- dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
++ if (sdmac->bd_iram)
++ gen_pool_free(sdma->iram_pool, (unsigned long)sdmac->bd, PAGE_SIZE);
++ else
++ dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
+
+ clk_disable(sdma->clk_ipg);
+ clk_disable(sdma->clk_ahb);
+@@ -922,7 +1053,7 @@
+ return NULL;
+ sdmac->status = DMA_IN_PROGRESS;
+
+- sdmac->flags = 0;
++ sdmac->mode = SDMA_MODE_NORMAL;
+
+ sdmac->buf_tail = 0;
+
+@@ -1015,9 +1146,9 @@
+ {
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct sdma_engine *sdma = sdmac->sdma;
+- int num_periods = buf_len / period_len;
+ int channel = sdmac->channel;
+ int ret, i = 0, buf = 0;
++ int num_periods;
+
+ dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
+
+@@ -1028,12 +1159,33 @@
+
+ sdmac->buf_tail = 0;
+
+- sdmac->flags |= IMX_DMA_SG_LOOP;
+ sdmac->direction = direction;
++
++ switch (sdmac->direction) {
++ case DMA_DEV_TO_DEV:
++ sdmac->mode = SDMA_MODE_P2P;
++ break;
++ case DMA_TRANS_NONE:
++ sdmac->mode = SDMA_MODE_NO_BD;
++ break;
++ case DMA_MEM_TO_DEV:
++ case DMA_DEV_TO_MEM:
++ sdmac->mode = SDMA_MODE_LOOP;
++ break;
++ default:
++ dev_err(sdma->dev, "invalid SDMA direction %d\n", direction);
++ return NULL;
++ }
++
+ ret = sdma_load_context(sdmac);
+ if (ret)
+ goto err_out;
+
++ if (period_len)
++ num_periods = buf_len / period_len;
++ else
++ return &sdmac->desc;
++
+ if (num_periods > NUM_BD) {
+ dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
+ channel, num_periods, NUM_BD);
+@@ -1098,18 +1250,31 @@
+ sdma_disable_channel(sdmac);
+ return 0;
+ case DMA_SLAVE_CONFIG:
+- if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
++ if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
++ sdmac->per_address = dmaengine_cfg->src_addr;
++ sdmac->per_address2 = dmaengine_cfg->dst_addr;
++ sdmac->watermark_level = 0;
++ sdmac->watermark_level |=
++ dmaengine_cfg->src_maxburst;
++ sdmac->watermark_level |=
++ dmaengine_cfg->dst_maxburst << 16;
++ sdmac->word_size = dmaengine_cfg->dst_addr_width;
++ } else if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
+ sdmac->per_address = dmaengine_cfg->src_addr;
+ sdmac->watermark_level = dmaengine_cfg->src_maxburst *
+ dmaengine_cfg->src_addr_width;
+ sdmac->word_size = dmaengine_cfg->src_addr_width;
+- } else {
++ } else if (dmaengine_cfg->direction == DMA_MEM_TO_DEV) {
+ sdmac->per_address = dmaengine_cfg->dst_addr;
+ sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
+ dmaengine_cfg->dst_addr_width;
+ sdmac->word_size = dmaengine_cfg->dst_addr_width;
+ }
+ sdmac->direction = dmaengine_cfg->direction;
++ if (dmaengine_cfg->dma_request0)
++ sdmac->event_id0 = dmaengine_cfg->dma_request0;
++ if (dmaengine_cfg->dma_request1)
++ sdmac->event_id1 = dmaengine_cfg->dma_request1;
+ return sdma_config_channel(sdmac);
+ default:
+ return -ENOSYS;
+@@ -1142,7 +1307,7 @@
+ sdma_enable_channel(sdma, sdmac->channel);
+ }
+
+-#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
++#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 38
+
+ static void sdma_add_scripts(struct sdma_engine *sdma,
+ const struct sdma_script_start_addrs *addr)
+@@ -1214,7 +1379,7 @@
+
+ static int __init sdma_init(struct sdma_engine *sdma)
+ {
+- int i, ret;
++ int i, ret, ccbsize;
+ dma_addr_t ccb_phys;
+
+ switch (sdma->devtype) {
+@@ -1236,14 +1401,17 @@
+ /* Be sure SDMA has not started yet */
+ writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
+
+- sdma->channel_control = dma_alloc_coherent(NULL,
+- MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
+- sizeof(struct sdma_context_data),
+- &ccb_phys, GFP_KERNEL);
++ ccbsize = MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)
++ + sizeof(struct sdma_context_data);
+
++ sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, ccbsize, &ccb_phys);
+ if (!sdma->channel_control) {
+- ret = -ENOMEM;
+- goto err_dma_alloc;
++ sdma->channel_control = dma_alloc_coherent(NULL, ccbsize,
++ &ccb_phys, GFP_KERNEL);
++ if (!sdma->channel_control) {
++ ret = -ENOMEM;
++ goto err_dma_alloc;
++ }
+ }
+
+ sdma->context = (void *)sdma->channel_control +
+@@ -1296,6 +1464,36 @@
+ return ret;
+ }
+
++static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
++{
++ struct imx_dma_data *data = fn_param;
++
++ if (!imx_dma_is_general_purpose(chan))
++ return false;
++
++ chan->private = data;
++
++ return true;
++}
++
++static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
++ struct of_dma *ofdma)
++{
++ struct sdma_engine *sdma = ofdma->of_dma_data;
++ dma_cap_mask_t mask = sdma->dma_device.cap_mask;
++ struct imx_dma_data data;
++
++ if (dma_spec->args_count != 3)
++ return NULL;
++
++ data.dma_request0 = dma_spec->args[0];
++ data.peripheral_type = dma_spec->args[1];
++ data.priority = dma_spec->args[2];
++ data.dma_request1 = 0;
++
++ return dma_request_channel(mask, sdma_filter_fn, &data);
++}
++
+ static int __init sdma_probe(struct platform_device *pdev)
+ {
+ const struct of_device_id *of_id =
+@@ -1397,6 +1595,11 @@
+ &sdma->dma_device.channels);
+ }
+
++ if (np)
++ sdma->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!sdma->iram_pool)
++ dev_warn(&pdev->dev, "no iram assigned, using external mem\n");
++
+ ret = sdma_init(sdma);
+ if (ret)
+ goto err_init;
+@@ -1443,10 +1646,20 @@
+ goto err_init;
+ }
+
++ if (np) {
++ ret = of_dma_controller_register(np, sdma_xlate, sdma);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register controller\n");
++ goto err_register;
++ }
++ }
++
+ dev_info(sdma->dev, "initialized\n");
+
+ return 0;
+
++err_register:
++ dma_async_device_unregister(&sdma->dma_device);
+ err_init:
+ kfree(sdma->script_addrs);
+ err_alloc:
+diff -Nur linux-3.10.30.orig/drivers/dma/Kconfig linux-linaro-stable-mx6/drivers/dma/Kconfig
+--- linux-3.10.30.orig/drivers/dma/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/dma/Kconfig 2014-05-15 20:33:46.877933716 +0200
+@@ -152,6 +152,19 @@
+ To avoid bloating the irq_desc[] array we allocate a sufficient
+ number of IRQ slots and map them dynamically to specific sources.
+
++config MXC_PXP_V2
++ bool "MXC PxP V2 support"
++ depends on ARM
++ select DMA_ENGINE
++ help
++ Support the PxP (Pixel Pipeline) on i.MX6 DualLite and i.MX6 SoloLite.
++ If unsure, select N.
++
++config MXC_PXP_CLIENT_DEVICE
++ bool "MXC PxP Client Device"
++ default y
++ depends on MXC_PXP_V2
++
+ config TXX9_DMAC
+ tristate "Toshiba TXx9 SoC DMA support"
+ depends on MACH_TX49XX || MACH_TX39XX
+diff -Nur linux-3.10.30.orig/drivers/dma/Makefile linux-linaro-stable-mx6/drivers/dma/Makefile
+--- linux-3.10.30.orig/drivers/dma/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/dma/Makefile 2014-05-15 20:33:46.877933716 +0200
+@@ -18,6 +18,7 @@
+ obj-$(CONFIG_DW_DMAC) += dw_dmac.o
+ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
+ obj-$(CONFIG_MX3_IPU) += ipu/
++obj-$(CONFIG_MXC_PXP_V2) += pxp/
+ obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
+ obj-$(CONFIG_SH_DMAE_BASE) += sh/
+ obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
+diff -Nur linux-3.10.30.orig/drivers/dma/pxp/Makefile linux-linaro-stable-mx6/drivers/dma/pxp/Makefile
+--- linux-3.10.30.orig/drivers/dma/pxp/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/dma/pxp/Makefile 2014-05-15 20:33:46.917934005 +0200
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_MXC_PXP_V2) += pxp_dma_v2.o
++obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o
+diff -Nur linux-3.10.30.orig/drivers/dma/pxp/pxp_device.c linux-linaro-stable-mx6/drivers/dma/pxp/pxp_device.c
+--- linux-3.10.30.orig/drivers/dma/pxp/pxp_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/dma/pxp/pxp_device.c 2014-05-15 20:33:46.917934005 +0200
+@@ -0,0 +1,489 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#include <linux/interrupt.h>
++#include <linux/miscdevice.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/slab.h>
++#include <linux/uaccess.h>
++#include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/pxp_dma.h>
++#include <linux/atomic.h>
++#include <linux/platform_data/dma-imx.h>
++
++static atomic_t open_count = ATOMIC_INIT(0);
++
++static DEFINE_SPINLOCK(pxp_mem_lock);
++static DEFINE_SPINLOCK(pxp_chan_lock);
++static LIST_HEAD(head);
++static LIST_HEAD(list);
++static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL];
++
++struct pxp_chan_handle {
++ int chan_id;
++ int hist_status;
++};
++
++/* To track the allocated memory buffer */
++struct memalloc_record {
++ struct list_head list;
++ struct pxp_mem_desc mem;
++};
++
++struct pxp_chan_info {
++ int chan_id;
++ struct dma_chan *dma_chan;
++ struct list_head list;
++};
++
++static int pxp_alloc_dma_buffer(struct pxp_mem_desc *mem)
++{
++ mem->cpu_addr = (unsigned long)
++ dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size),
++ (dma_addr_t *) (&mem->phys_addr),
++ GFP_DMA | GFP_KERNEL);
++ pr_debug("[ALLOC] mem alloc phys_addr = 0x%x\n", mem->phys_addr);
++ if ((void *)(mem->cpu_addr) == NULL) {
++ printk(KERN_ERR "Physical memory allocation error!\n");
++ return -1;
++ }
++ return 0;
++}
++
++static void pxp_free_dma_buffer(struct pxp_mem_desc *mem)
++{
++ if (mem->cpu_addr != 0) {
++ dma_free_coherent(0, PAGE_ALIGN(mem->size),
++ (void *)mem->cpu_addr, mem->phys_addr);
++ }
++}
++
++static int pxp_free_buffers(void)
++{
++ struct memalloc_record *rec, *n;
++ struct pxp_mem_desc mem;
++
++ list_for_each_entry_safe(rec, n, &head, list) {
++ mem = rec->mem;
++ if (mem.cpu_addr != 0) {
++ pxp_free_dma_buffer(&mem);
++ pr_debug("[FREE] freed paddr=0x%08X\n", mem.phys_addr);
++ /* delete from list */
++ list_del(&rec->list);
++ kfree(rec);
++ }
++ }
++
++ return 0;
++}
++
++/* Callback function triggered after PxP receives an EOF interrupt */
++static void pxp_dma_done(void *arg)
++{
++ struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
++ struct dma_chan *chan = tx_desc->txd.chan;
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ int chan_id = pxp_chan->dma_chan.chan_id;
++
++ pr_debug("DMA Done ISR, chan_id %d\n", chan_id);
++
++ irq_info[chan_id].irq_pending++;
++ irq_info[chan_id].hist_status = tx_desc->hist_status;
++
++ wake_up_interruptible(&(irq_info[chan_id].waitq));
++}
++
++static int pxp_ioc_config_chan(unsigned long arg)
++{
++ struct scatterlist sg[3];
++ struct pxp_tx_desc *desc;
++ struct dma_async_tx_descriptor *txd;
++ struct pxp_chan_info *info;
++ struct pxp_config_data pxp_conf;
++ dma_cookie_t cookie;
++ int chan_id;
++ int i, length, ret;
++
++ ret = copy_from_user(&pxp_conf,
++ (struct pxp_config_data *)arg,
++ sizeof(struct pxp_config_data));
++ if (ret)
++ return -EFAULT;
++
++ chan_id = pxp_conf.chan_id;
++ if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
++ return -ENODEV;
++
++ init_waitqueue_head(&(irq_info[chan_id].waitq));
++
++ /* find the channel */
++ spin_lock(&pxp_chan_lock);
++ list_for_each_entry(info, &list, list) {
++ if (info->dma_chan->chan_id == chan_id)
++ break;
++ }
++ spin_unlock(&pxp_chan_lock);
++
++ sg_init_table(sg, 3);
++
++ txd =
++ info->dma_chan->device->device_prep_slave_sg(info->dma_chan,
++ sg, 3,
++ DMA_TO_DEVICE,
++ DMA_PREP_INTERRUPT,
++ NULL);
++ if (!txd) {
++ pr_err("Error preparing a DMA transaction descriptor.\n");
++ return -EIO;
++ }
++
++ txd->callback_param = txd;
++ txd->callback = pxp_dma_done;
++
++ desc = to_tx_desc(txd);
++
++ length = desc->len;
++ for (i = 0; i < length; i++) {
++ if (i == 0) { /* S0 */
++ memcpy(&desc->proc_data,
++ &pxp_conf.proc_data,
++ sizeof(struct pxp_proc_data));
++ memcpy(&desc->layer_param.s0_param,
++ &pxp_conf.s0_param,
++ sizeof(struct pxp_layer_param));
++ } else if (i == 1) { /* Output */
++ memcpy(&desc->layer_param.out_param,
++ &pxp_conf.out_param,
++ sizeof(struct pxp_layer_param));
++ } else {
++ /* OverLay */
++ memcpy(&desc->layer_param.ol_param,
++ &pxp_conf.ol_param,
++ sizeof(struct pxp_layer_param));
++ }
++
++ desc = desc->next;
++ }
++
++ cookie = txd->tx_submit(txd);
++ if (cookie < 0) {
++ pr_err("Error tx_submit\n");
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int pxp_device_open(struct inode *inode, struct file *filp)
++{
++ atomic_inc(&open_count);
++
++ return 0;
++}
++
++static int pxp_device_release(struct inode *inode, struct file *filp)
++{
++ if (atomic_dec_and_test(&open_count))
++ pxp_free_buffers();
++
++ return 0;
++}
++
++static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ struct memalloc_record *rec, *n;
++ int request_size, found;
++
++ request_size = vma->vm_end - vma->vm_start;
++ found = 0;
++
++ pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n",
++ (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff),
++ request_size);
++
++ spin_lock(&pxp_mem_lock);
++ list_for_each_entry_safe(rec, n, &head, list) {
++ if (rec->mem.phys_addr == (vma->vm_pgoff << PAGE_SHIFT) &&
++ (rec->mem.size <= request_size)) {
++ found = 1;
++ break;
++ }
++ }
++ spin_unlock(&pxp_mem_lock);
++
++ if (found == 0)
++ return -ENOMEM;
++
++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++
++ return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ request_size, vma->vm_page_prot) ? -EAGAIN : 0;
++}
++
++static bool chan_filter(struct dma_chan *chan, void *arg)
++{
++ if (imx_dma_is_pxp(chan))
++ return true;
++ else
++ return false;
++}
++
++static long pxp_device_ioctl(struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ int ret = 0;
++
++ switch (cmd) {
++ case PXP_IOC_GET_CHAN:
++ {
++ struct pxp_chan_info *info;
++ dma_cap_mask_t mask;
++
++ pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__);
++ info = kzalloc(sizeof(*info), GFP_KERNEL);
++ if (!info) {
++ pr_err("%d: alloc err\n", __LINE__);
++ return -ENOMEM;
++ }
++
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_PRIVATE, mask);
++ info->dma_chan =
++ dma_request_channel(mask, chan_filter, NULL);
++ if (!info->dma_chan) {
++ pr_err("Unsccessfully received channel!\n");
++ kfree(info);
++ return -EBUSY;
++ }
++ pr_debug("Successfully received channel."
++ "chan_id %d\n", info->dma_chan->chan_id);
++
++ spin_lock(&pxp_chan_lock);
++ list_add_tail(&info->list, &list);
++ spin_unlock(&pxp_chan_lock);
++
++ if (put_user
++ (info->dma_chan->chan_id, (u32 __user *) arg))
++ return -EFAULT;
++
++ break;
++ }
++ case PXP_IOC_PUT_CHAN:
++ {
++ int chan_id;
++ struct pxp_chan_info *info;
++
++ if (get_user(chan_id, (u32 __user *) arg))
++ return -EFAULT;
++
++ if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
++ return -ENODEV;
++
++ spin_lock(&pxp_chan_lock);
++ list_for_each_entry(info, &list, list) {
++ if (info->dma_chan->chan_id == chan_id)
++ break;
++ }
++ spin_unlock(&pxp_chan_lock);
++
++ pr_debug("%d release chan_id %d\n", __LINE__,
++ info->dma_chan->chan_id);
++ /* REVISIT */
++ dma_release_channel(info->dma_chan);
++ spin_lock(&pxp_chan_lock);
++ list_del_init(&info->list);
++ spin_unlock(&pxp_chan_lock);
++ kfree(info);
++
++ break;
++ }
++ case PXP_IOC_CONFIG_CHAN:
++ {
++
++ int ret;
++
++ ret = pxp_ioc_config_chan(arg);
++ if (ret)
++ return ret;
++
++ break;
++ }
++ case PXP_IOC_START_CHAN:
++ {
++ struct pxp_chan_info *info;
++ int chan_id;
++
++ if (get_user(chan_id, (u32 __user *) arg))
++ return -EFAULT;
++
++ /* find the channel */
++ spin_lock(&pxp_chan_lock);
++ list_for_each_entry(info, &list, list) {
++ if (info->dma_chan->chan_id == chan_id)
++ break;
++ }
++ spin_unlock(&pxp_chan_lock);
++
++ dma_async_issue_pending(info->dma_chan);
++
++ break;
++ }
++ case PXP_IOC_GET_PHYMEM:
++ {
++ struct memalloc_record *rec;
++
++ rec = kzalloc(sizeof(*rec), GFP_KERNEL);
++ if (!rec)
++ return -ENOMEM;
++
++ ret = copy_from_user(&(rec->mem),
++ (struct pxp_mem_desc *)arg,
++ sizeof(struct pxp_mem_desc));
++ if (ret) {
++ kfree(rec);
++ return -EFAULT;
++ }
++
++ pr_debug("[ALLOC] mem alloc size = 0x%x\n",
++ rec->mem.size);
++
++ ret = pxp_alloc_dma_buffer(&(rec->mem));
++ if (ret == -1) {
++ kfree(rec);
++ printk(KERN_ERR
++ "Physical memory allocation error!\n");
++ break;
++ }
++ ret = copy_to_user((void __user *)arg, &(rec->mem),
++ sizeof(struct pxp_mem_desc));
++ if (ret) {
++ kfree(rec);
++ ret = -EFAULT;
++ break;
++ }
++
++ spin_lock(&pxp_mem_lock);
++ list_add(&rec->list, &head);
++ spin_unlock(&pxp_mem_lock);
++
++ break;
++ }
++ case PXP_IOC_PUT_PHYMEM:
++ {
++ struct memalloc_record *rec, *n;
++ struct pxp_mem_desc pxp_mem;
++
++ ret = copy_from_user(&pxp_mem,
++ (struct pxp_mem_desc *)arg,
++ sizeof(struct pxp_mem_desc));
++ if (ret)
++ return -EACCES;
++
++ pr_debug("[FREE] mem freed cpu_addr = 0x%x\n",
++ pxp_mem.cpu_addr);
++ if ((void *)pxp_mem.cpu_addr != NULL)
++ pxp_free_dma_buffer(&pxp_mem);
++
++ spin_lock(&pxp_mem_lock);
++ list_for_each_entry_safe(rec, n, &head, list) {
++ if (rec->mem.cpu_addr == pxp_mem.cpu_addr) {
++ /* delete from list */
++ list_del(&rec->list);
++ kfree(rec);
++ break;
++ }
++ }
++ spin_unlock(&pxp_mem_lock);
++
++ break;
++ }
++ case PXP_IOC_WAIT4CMPLT:
++ {
++ struct pxp_chan_handle chan_handle;
++ int ret, chan_id;
++
++ ret = copy_from_user(&chan_handle,
++ (struct pxp_chan_handle *)arg,
++ sizeof(struct pxp_chan_handle));
++ if (ret)
++ return -EFAULT;
++
++ chan_id = chan_handle.chan_id;
++ if (chan_id < 0 || chan_id >= NR_PXP_VIRT_CHANNEL)
++ return -ENODEV;
++
++ ret = wait_event_interruptible
++ (irq_info[chan_id].waitq,
++ (irq_info[chan_id].irq_pending != 0));
++ if (ret < 0) {
++ printk(KERN_WARNING
++ "pxp interrupt received.\n");
++ return -ERESTARTSYS;
++ } else
++ irq_info[chan_id].irq_pending--;
++
++ chan_handle.hist_status = irq_info[chan_id].hist_status;
++ ret = copy_to_user((struct pxp_chan_handle *)arg,
++ &chan_handle,
++ sizeof(struct pxp_chan_handle));
++ if (ret)
++ return -EFAULT;
++ break;
++ }
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++static const struct file_operations pxp_device_fops = {
++ .open = pxp_device_open,
++ .release = pxp_device_release,
++ .unlocked_ioctl = pxp_device_ioctl,
++ .mmap = pxp_device_mmap,
++};
++
++static struct miscdevice pxp_device_miscdev = {
++ .minor = MISC_DYNAMIC_MINOR,
++ .name = "pxp_device",
++ .fops = &pxp_device_fops,
++};
++
++int register_pxp_device(void)
++{
++ int ret;
++
++ ret = misc_register(&pxp_device_miscdev);
++ if (ret)
++ return ret;
++
++ pr_debug("PxP_Device registered Successfully\n");
++ return 0;
++}
++
++void unregister_pxp_device(void)
++{
++ misc_deregister(&pxp_device_miscdev);
++}
+diff -Nur linux-3.10.30.orig/drivers/dma/pxp/pxp_dma_v2.c linux-linaro-stable-mx6/drivers/dma/pxp/pxp_dma_v2.c
+--- linux-3.10.30.orig/drivers/dma/pxp/pxp_dma_v2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/dma/pxp/pxp_dma_v2.c 2014-05-15 20:33:46.917934005 +0200
+@@ -0,0 +1,1936 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * Based on STMP378X PxP driver
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++#include <linux/busfreq-imx6.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++#include <linux/timer.h>
++#include <linux/clk.h>
++#include <linux/workqueue.h>
++#include <linux/sched.h>
++#include <linux/of.h>
++
++#include "regs-pxp_v2.h"
++
++#define PXP_DOWNSCALE_THRESHOLD 0x4000
++
++static LIST_HEAD(head);
++static int timeout_in_ms = 600;
++static unsigned int block_size;
++struct mutex hard_lock;
++
++struct pxp_dma {
++ struct dma_device dma;
++};
++
++struct pxps {
++ struct platform_device *pdev;
++ struct clk *clk;
++ void __iomem *base;
++ int irq; /* PXP IRQ to the CPU */
++
++ spinlock_t lock;
++ struct mutex clk_mutex;
++ int clk_stat;
++#define CLK_STAT_OFF 0
++#define CLK_STAT_ON 1
++ int pxp_ongoing;
++ int lut_state;
++
++ struct device *dev;
++ struct pxp_dma pxp_dma;
++ struct pxp_channel channel[NR_PXP_VIRT_CHANNEL];
++ struct work_struct work;
++
++ /* describes most recent processing configuration */
++ struct pxp_config_data pxp_conf_state;
++
++ /* to turn clock off when pxp is inactive */
++ struct timer_list clk_timer;
++};
++
++#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma)
++#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd)
++#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan)
++#define to_pxp(id) container_of(id, struct pxps, pxp_dma)
++
++#define PXP_DEF_BUFS 2
++#define PXP_MIN_PIX 8
++
++static uint32_t pxp_s0_formats[] = {
++ PXP_PIX_FMT_RGB32,
++ PXP_PIX_FMT_RGB565,
++ PXP_PIX_FMT_RGB555,
++ PXP_PIX_FMT_YUV420P,
++ PXP_PIX_FMT_YUV422P,
++};
++
++/*
++ * PXP common functions
++ */
++static void dump_pxp_reg(struct pxps *pxp)
++{
++ dev_dbg(pxp->dev, "PXP_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CTRL));
++ dev_dbg(pxp->dev, "PXP_STAT 0x%x",
++ __raw_readl(pxp->base + HW_PXP_STAT));
++ dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_CTRL));
++ dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_BUF));
++ dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_BUF2));
++ dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_PITCH));
++ dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_LRC));
++ dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC));
++ dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC));
++ dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC));
++ dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC));
++ dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_CTRL));
++ dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_BUF));
++ dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_UBUF));
++ dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_VBUF));
++ dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_PITCH));
++ dev_dbg(pxp->dev, "PXP_PS_BACKGROUND 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND));
++ dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_SCALE));
++ dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_OFFSET));
++ dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW));
++ dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH));
++ dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_CTRL));
++ dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_BUF));
++ dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_PITCH));
++ dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW));
++ dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH));
++ dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC1_COEF0));
++ dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC1_COEF1));
++ dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC1_COEF2));
++ dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_CTRL));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF0));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF1));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF2));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF3));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF4));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF5));
++ dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_LUT_CTRL));
++ dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x",
++ __raw_readl(pxp->base + HW_PXP_LUT_ADDR));
++ dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x",
++ __raw_readl(pxp->base + HW_PXP_LUT_DATA));
++ dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x",
++ __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM));
++ dev_dbg(pxp->dev, "PXP_CFA 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CFA));
++ dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST_CTRL));
++ dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST2_PARAM));
++ dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST4_PARAM));
++ dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0));
++ dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1));
++ dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0));
++ dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1));
++ dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2));
++ dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3));
++ dev_dbg(pxp->dev, "PXP_POWER 0x%x",
++ __raw_readl(pxp->base + HW_PXP_POWER));
++ dev_dbg(pxp->dev, "PXP_NEXT 0x%x",
++ __raw_readl(pxp->base + HW_PXP_NEXT));
++ dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_DEBUGCTRL));
++ dev_dbg(pxp->dev, "PXP_DEBUG 0x%x",
++ __raw_readl(pxp->base + HW_PXP_DEBUG));
++ dev_dbg(pxp->dev, "PXP_VERSION 0x%x",
++ __raw_readl(pxp->base + HW_PXP_VERSION));
++}
++
++static bool is_yuv(u32 pix_fmt)
++{
++ if ((pix_fmt == PXP_PIX_FMT_YUYV) |
++ (pix_fmt == PXP_PIX_FMT_UYVY) |
++ (pix_fmt == PXP_PIX_FMT_YVYU) |
++ (pix_fmt == PXP_PIX_FMT_VYUY) |
++ (pix_fmt == PXP_PIX_FMT_Y41P) |
++ (pix_fmt == PXP_PIX_FMT_YUV444) |
++ (pix_fmt == PXP_PIX_FMT_NV12) |
++ (pix_fmt == PXP_PIX_FMT_NV16) |
++ (pix_fmt == PXP_PIX_FMT_NV61) |
++ (pix_fmt == PXP_PIX_FMT_GREY) |
++ (pix_fmt == PXP_PIX_FMT_GY04) |
++ (pix_fmt == PXP_PIX_FMT_YVU410P) |
++ (pix_fmt == PXP_PIX_FMT_YUV410P) |
++ (pix_fmt == PXP_PIX_FMT_YVU420P) |
++ (pix_fmt == PXP_PIX_FMT_YUV420P) |
++ (pix_fmt == PXP_PIX_FMT_YUV420P2) |
++ (pix_fmt == PXP_PIX_FMT_YVU422P) |
++ (pix_fmt == PXP_PIX_FMT_YUV422P)) {
++ return true;
++ } else {
++ return false;
++ }
++}
++
++static void pxp_set_ctrl(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ u32 ctrl;
++ u32 fmt_ctrl;
++ int need_swap = 0; /* to support YUYV and YVYU formats */
++
++ /* Configure S0 input format */
++ switch (pxp_conf->s0_param.pixel_fmt) {
++ case PXP_PIX_FMT_RGB32:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888;
++ break;
++ case PXP_PIX_FMT_RGB565:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565;
++ break;
++ case PXP_PIX_FMT_RGB555:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555;
++ break;
++ case PXP_PIX_FMT_YUV420P:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420;
++ break;
++ case PXP_PIX_FMT_YVU420P:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420;
++ break;
++ case PXP_PIX_FMT_GREY:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8;
++ break;
++ case PXP_PIX_FMT_GY04:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4;
++ break;
++ case PXP_PIX_FMT_YUV422P:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422;
++ break;
++ case PXP_PIX_FMT_UYVY:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
++ break;
++ case PXP_PIX_FMT_YUYV:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
++ need_swap = 1;
++ break;
++ case PXP_PIX_FMT_VYUY:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
++ break;
++ case PXP_PIX_FMT_YVYU:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
++ need_swap = 1;
++ break;
++ case PXP_PIX_FMT_NV12:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420;
++ break;
++ case PXP_PIX_FMT_NV21:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420;
++ break;
++ case PXP_PIX_FMT_NV16:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422;
++ break;
++ case PXP_PIX_FMT_NV61:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422;
++ break;
++ default:
++ fmt_ctrl = 0;
++ }
++
++ ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap);
++ __raw_writel(ctrl, pxp->base + HW_PXP_PS_CTRL_SET);
++
++ /* Configure output format based on out_channel format */
++ switch (pxp_conf->out_param.pixel_fmt) {
++ case PXP_PIX_FMT_RGB32:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888;
++ break;
++ case PXP_PIX_FMT_BGRA32:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888;
++ break;
++ case PXP_PIX_FMT_RGB24:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P;
++ break;
++ case PXP_PIX_FMT_RGB565:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565;
++ break;
++ case PXP_PIX_FMT_RGB555:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555;
++ break;
++ case PXP_PIX_FMT_GREY:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8;
++ break;
++ case PXP_PIX_FMT_GY04:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4;
++ break;
++ case PXP_PIX_FMT_UYVY:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422;
++ break;
++ case PXP_PIX_FMT_VYUY:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422;
++ break;
++ case PXP_PIX_FMT_NV12:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
++ break;
++ case PXP_PIX_FMT_NV21:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420;
++ break;
++ case PXP_PIX_FMT_NV16:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
++ break;
++ case PXP_PIX_FMT_NV61:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422;
++ break;
++ default:
++ fmt_ctrl = 0;
++ }
++
++ ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl);
++ __raw_writel(ctrl, pxp->base + HW_PXP_OUT_CTRL);
++
++ ctrl = 0;
++ if (proc_data->scaling)
++ ;
++ if (proc_data->vflip)
++ ctrl |= BM_PXP_CTRL_VFLIP;
++ if (proc_data->hflip)
++ ctrl |= BM_PXP_CTRL_HFLIP;
++ if (proc_data->rotate) {
++ ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90);
++ if (proc_data->rot_pos)
++ ctrl |= BM_PXP_CTRL_ROT_POS;
++ }
++
++ /* In default, the block size is set to 8x8
++ * But block size can be set to 16x16 due to
++ * blocksize variable modification
++ */
++ ctrl |= block_size << 23;
++
++ __raw_writel(ctrl, pxp->base + HW_PXP_CTRL);
++}
++
++static int pxp_start(struct pxps *pxp)
++{
++ __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET);
++ __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET);
++ dump_pxp_reg(pxp);
++
++ return 0;
++}
++
++static void pxp_set_outbuf(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *out_params = &pxp_conf->out_param;
++
++ __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUT_BUF);
++
++ __raw_writel(BF_PXP_OUT_LRC_X(out_params->width - 1) |
++ BF_PXP_OUT_LRC_Y(out_params->height - 1),
++ pxp->base + HW_PXP_OUT_LRC);
++
++ if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24) {
++ __raw_writel(out_params->stride * 3,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_BGRA32 ||
++ out_params->pixel_fmt == PXP_PIX_FMT_RGB32) {
++ __raw_writel(out_params->stride << 2,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_RGB565) {
++ __raw_writel(out_params->stride << 1,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_UYVY ||
++ (out_params->pixel_fmt == PXP_PIX_FMT_VYUY)) {
++ __raw_writel(out_params->stride << 1,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_GREY ||
++ out_params->pixel_fmt == PXP_PIX_FMT_NV12 ||
++ out_params->pixel_fmt == PXP_PIX_FMT_NV21 ||
++ out_params->pixel_fmt == PXP_PIX_FMT_NV16 ||
++ out_params->pixel_fmt == PXP_PIX_FMT_NV61) {
++ __raw_writel(out_params->stride,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_GY04) {
++ __raw_writel(out_params->stride >> 1,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else {
++ __raw_writel(0, pxp->base + HW_PXP_OUT_PITCH);
++ }
++
++ /* set global alpha if necessary */
++ if (out_params->global_alpha_enable) {
++ __raw_writel(out_params->global_alpha << 24,
++ pxp->base + HW_PXP_OUT_CTRL_SET);
++ __raw_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT,
++ pxp->base + HW_PXP_OUT_CTRL_SET);
++ }
++}
++
++static void pxp_set_s0colorkey(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
++
++ /* Low and high are set equal. V4L does not allow a chromakey range */
++ if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) {
++ /* disable color key */
++ __raw_writel(0xFFFFFF, pxp->base + HW_PXP_PS_CLRKEYLOW);
++ __raw_writel(0, pxp->base + HW_PXP_PS_CLRKEYHIGH);
++ } else {
++ __raw_writel(s0_params->color_key,
++ pxp->base + HW_PXP_PS_CLRKEYLOW);
++ __raw_writel(s0_params->color_key,
++ pxp->base + HW_PXP_PS_CLRKEYHIGH);
++ }
++}
++
++static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no];
++
++ /* Low and high are set equal. V4L does not allow a chromakey range */
++ if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) {
++ __raw_writel(ol_params->color_key,
++ pxp->base + HW_PXP_AS_CLRKEYLOW);
++ __raw_writel(ol_params->color_key,
++ pxp->base + HW_PXP_AS_CLRKEYHIGH);
++ } else {
++ /* disable color key */
++ __raw_writel(0xFFFFFF, pxp->base + HW_PXP_AS_CLRKEYLOW);
++ __raw_writel(0, pxp->base + HW_PXP_AS_CLRKEYHIGH);
++ }
++}
++
++static void pxp_set_oln(int layer_no, struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
++ dma_addr_t phys_addr = olparams_data->paddr;
++ u32 pitch = olparams_data->stride ? olparams_data->stride :
++ olparams_data->width;
++
++ __raw_writel(phys_addr, pxp->base + HW_PXP_AS_BUF);
++
++ /* Fixme */
++ if (olparams_data->width == 0 && olparams_data->height == 0) {
++ __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC);
++ __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC);
++ } else {
++ __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_ULC);
++ if (pxp_conf->proc_data.rotate == 90 ||
++ pxp_conf->proc_data.rotate == 270) {
++ if (pxp_conf->proc_data.rot_pos == 1) {
++ __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->height - 1) |
++ BF_PXP_OUT_AS_LRC_Y(olparams_data->width - 1),
++ pxp->base + HW_PXP_OUT_AS_LRC);
++ } else {
++ __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width - 1) |
++ BF_PXP_OUT_AS_LRC_Y(olparams_data->height - 1),
++ pxp->base + HW_PXP_OUT_AS_LRC);
++ }
++ } else {
++ __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width - 1) |
++ BF_PXP_OUT_AS_LRC_Y(olparams_data->height - 1),
++ pxp->base + HW_PXP_OUT_AS_LRC);
++ }
++ }
++
++ if ((olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) |
++ (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB32)) {
++ __raw_writel(pitch << 2,
++ pxp->base + HW_PXP_AS_PITCH);
++ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) {
++ __raw_writel(pitch << 1,
++ pxp->base + HW_PXP_AS_PITCH);
++ } else {
++ __raw_writel(0, pxp->base + HW_PXP_AS_PITCH);
++ }
++}
++
++static void pxp_set_olparam(int layer_no, struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
++ u32 olparam;
++
++ olparam = BF_PXP_AS_CTRL_ALPHA(olparams_data->global_alpha);
++ if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB32) {
++ olparam |=
++ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB888);
++ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) {
++ olparam |=
++ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__ARGB8888);
++ if (!olparams_data->combine_enable) {
++ olparam |=
++ BF_PXP_AS_CTRL_ALPHA_CTRL
++ (BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs);
++ olparam |= 0x3 << 16;
++ }
++ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) {
++ olparam |=
++ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB565);
++ }
++ if (olparams_data->global_alpha_enable) {
++ if (olparams_data->global_override) {
++ olparam |=
++ BF_PXP_AS_CTRL_ALPHA_CTRL
++ (BV_PXP_AS_CTRL_ALPHA_CTRL__Override);
++ } else {
++ olparam |=
++ BF_PXP_AS_CTRL_ALPHA_CTRL
++ (BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply);
++ }
++ if (olparams_data->alpha_invert)
++ olparam |= BM_PXP_AS_CTRL_ALPHA_INVERT;
++ }
++ if (olparams_data->color_key_enable)
++ olparam |= BM_PXP_AS_CTRL_ENABLE_COLORKEY;
++
++ __raw_writel(olparam, pxp->base + HW_PXP_AS_CTRL);
++}
++
++static void pxp_set_s0param(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ u32 s0param;
++
++ /* contains the coordinate for the PS in the OUTPUT buffer. */
++ if ((pxp_conf->s0_param).width == 0 &&
++ (pxp_conf->s0_param).height == 0) {
++ __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_PS_ULC);
++ __raw_writel(0x0, pxp->base + HW_PXP_OUT_PS_LRC);
++ } else {
++ s0param = BF_PXP_OUT_PS_ULC_X(proc_data->drect.left);
++ s0param |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.top);
++ __raw_writel(s0param, pxp->base + HW_PXP_OUT_PS_ULC);
++ s0param = BF_PXP_OUT_PS_LRC_X(proc_data->drect.left +
++ proc_data->drect.width - 1);
++ s0param |= BF_PXP_OUT_PS_LRC_Y(proc_data->drect.top +
++ proc_data->drect.height - 1);
++ __raw_writel(s0param, pxp->base + HW_PXP_OUT_PS_LRC);
++ }
++}
++
++/* crop behavior is re-designed in h/w. */
++static void pxp_set_s0crop(struct pxps *pxp)
++{
++ /*
++ * place-holder, it's implemented in other functions in this driver.
++ * Refer to "Clipping source images" section in RM for detail.
++ */
++}
++
++static int pxp_set_scaling(struct pxps *pxp)
++{
++ int ret = 0;
++ u32 xscale, yscale, s0scale;
++ u32 decx, decy, xdec = 0, ydec = 0;
++ struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data;
++
++ if (((proc_data->srect.width == proc_data->drect.width) &&
++ (proc_data->srect.height == proc_data->drect.height)) ||
++ ((proc_data->srect.width == 0) && (proc_data->srect.height == 0))) {
++ proc_data->scaling = 0;
++ __raw_writel(0x10001000, pxp->base + HW_PXP_PS_SCALE);
++ __raw_writel(0, pxp->base + HW_PXP_PS_CTRL);
++ goto out;
++ }
++
++ proc_data->scaling = 1;
++ decx = proc_data->srect.width / proc_data->drect.width;
++ decy = proc_data->srect.height / proc_data->drect.height;
++ if (decx > 0) {
++ if (decx >= 2 && decx < 4) {
++ decx = 2;
++ xdec = 1;
++ } else if (decx >= 4 && decx < 8) {
++ decx = 4;
++ xdec = 2;
++ } else if (decx >= 8) {
++ decx = 8;
++ xdec = 3;
++ }
++ xscale = proc_data->srect.width * 0x1000 /
++ (proc_data->drect.width * decx);
++ } else
++ xscale = proc_data->srect.width * 0x1000 /
++ proc_data->drect.width;
++ if (decy > 0) {
++ if (decy >= 2 && decy < 4) {
++ decy = 2;
++ ydec = 1;
++ } else if (decy >= 4 && decy < 8) {
++ decy = 4;
++ ydec = 2;
++ } else if (decy >= 8) {
++ decy = 8;
++ ydec = 3;
++ }
++ yscale = proc_data->srect.height * 0x1000 /
++ (proc_data->drect.height * decy);
++ } else
++ yscale = proc_data->srect.height * 0x1000 /
++ proc_data->drect.height;
++
++ __raw_writel((xdec << 10) | (ydec << 8), pxp->base + HW_PXP_PS_CTRL);
++
++ if (xscale > PXP_DOWNSCALE_THRESHOLD)
++ xscale = PXP_DOWNSCALE_THRESHOLD;
++ if (yscale > PXP_DOWNSCALE_THRESHOLD)
++ yscale = PXP_DOWNSCALE_THRESHOLD;
++ s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
++ BF_PXP_PS_SCALE_XSCALE(xscale);
++ __raw_writel(s0scale, pxp->base + HW_PXP_PS_SCALE);
++
++out:
++ pxp_set_ctrl(pxp);
++
++ return ret;
++}
++
++static void pxp_set_bg(struct pxps *pxp)
++{
++ __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor,
++ pxp->base + HW_PXP_PS_BACKGROUND);
++}
++
++static void pxp_set_lut(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ int lut_op = pxp_conf->proc_data.lut_transform;
++ u32 reg_val;
++ int i;
++ bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false;
++ u8 *cmap = pxp_conf->proc_data.lut_map;
++ u32 entry_src;
++ u32 pix_val;
++ u8 entry[4];
++
++ /*
++ * If LUT already configured as needed, return...
++ * Unless CMAP is needed and it has been updated.
++ */
++ if ((pxp->lut_state == lut_op) &&
++ !(use_cmap && pxp_conf->proc_data.lut_map_updated))
++ return;
++
++ if (lut_op == PXP_LUT_NONE) {
++ __raw_writel(BM_PXP_LUT_CTRL_BYPASS,
++ pxp->base + HW_PXP_LUT_CTRL);
++ } else if (((lut_op & PXP_LUT_INVERT) != 0)
++ && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) {
++ /* Fill out LUT table with inverted monochromized values */
++
++ /* clear bypass bit, set lookup mode & out mode */
++ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
++ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
++ BF_PXP_LUT_CTRL_OUT_MODE
++ (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
++ pxp->base + HW_PXP_LUT_CTRL);
++
++ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
++ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
++
++ /* LUT address pointer auto-increments after each data write */
++ for (pix_val = 0; pix_val < 256; pix_val += 4) {
++ for (i = 0; i < 4; i++) {
++ entry_src = use_cmap ?
++ cmap[pix_val + i] : pix_val + i;
++ entry[i] = (entry_src < 0x80) ? 0xFF : 0x00;
++ }
++ reg_val = (entry[3] << 24) | (entry[2] << 16) |
++ (entry[1] << 8) | entry[0];
++ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
++ }
++ } else if ((lut_op & PXP_LUT_INVERT) != 0) {
++ /* Fill out LUT table with 8-bit inverted values */
++
++ /* clear bypass bit, set lookup mode & out mode */
++ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
++ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
++ BF_PXP_LUT_CTRL_OUT_MODE
++ (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
++ pxp->base + HW_PXP_LUT_CTRL);
++
++ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
++ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
++
++ /* LUT address pointer auto-increments after each data write */
++ for (pix_val = 0; pix_val < 256; pix_val += 4) {
++ for (i = 0; i < 4; i++) {
++ entry_src = use_cmap ?
++ cmap[pix_val + i] : pix_val + i;
++ entry[i] = ~entry_src & 0xFF;
++ }
++ reg_val = (entry[3] << 24) | (entry[2] << 16) |
++ (entry[1] << 8) | entry[0];
++ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
++ }
++ } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) {
++ /* Fill out LUT table with 8-bit monochromized values */
++
++ /* clear bypass bit, set lookup mode & out mode */
++ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
++ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
++ BF_PXP_LUT_CTRL_OUT_MODE
++ (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
++ pxp->base + HW_PXP_LUT_CTRL);
++
++ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
++ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
++
++ /* LUT address pointer auto-increments after each data write */
++ for (pix_val = 0; pix_val < 256; pix_val += 4) {
++ for (i = 0; i < 4; i++) {
++ entry_src = use_cmap ?
++ cmap[pix_val + i] : pix_val + i;
++ entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF;
++ }
++ reg_val = (entry[3] << 24) | (entry[2] << 16) |
++ (entry[1] << 8) | entry[0];
++ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
++ }
++ } else if (use_cmap) {
++ /* Fill out LUT table using colormap values */
++
++ /* clear bypass bit, set lookup mode & out mode */
++ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
++ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
++ BF_PXP_LUT_CTRL_OUT_MODE
++ (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
++ pxp->base + HW_PXP_LUT_CTRL);
++
++ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
++ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
++
++ /* LUT address pointer auto-increments after each data write */
++ for (pix_val = 0; pix_val < 256; pix_val += 4) {
++ for (i = 0; i < 4; i++)
++ entry[i] = cmap[pix_val + i];
++ reg_val = (entry[3] << 24) | (entry[2] << 16) |
++ (entry[1] << 8) | entry[0];
++ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
++ }
++ }
++
++ pxp->lut_state = lut_op;
++}
++
++static void pxp_set_csc(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
++ struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0];
++ struct pxp_layer_param *out_params = &pxp_conf->out_param;
++
++ bool input_is_YUV = is_yuv(s0_params->pixel_fmt);
++ bool output_is_YUV = is_yuv(out_params->pixel_fmt);
++
++ if (input_is_YUV && output_is_YUV) {
++ /*
++ * Input = YUV, Output = YUV
++ * No CSC unless we need to do combining
++ */
++ if (ol_params->combine_enable) {
++ /* Must convert to RGB for combining with RGB overlay */
++
++ /* CSC1 - YUV->RGB */
++ __raw_writel(0x04030000, pxp->base + HW_PXP_CSC1_COEF0);
++ __raw_writel(0x01230208, pxp->base + HW_PXP_CSC1_COEF1);
++ __raw_writel(0x076b079c, pxp->base + HW_PXP_CSC1_COEF2);
++
++ /* CSC2 - RGB->YUV */
++ __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL);
++ __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0);
++ __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1);
++ __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2);
++ __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3);
++ __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4);
++ __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5);
++ } else {
++ /* Input & Output both YUV, so bypass both CSCs */
++
++ /* CSC1 - Bypass */
++ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
++
++ /* CSC2 - Bypass */
++ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
++ }
++ } else if (input_is_YUV && !output_is_YUV) {
++ /*
++ * Input = YUV, Output = RGB
++ * Use CSC1 to convert to RGB
++ */
++
++ /* CSC1 - YUV->RGB */
++ __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSC1_COEF0);
++ __raw_writel(0x01980204, pxp->base + HW_PXP_CSC1_COEF1);
++ __raw_writel(0x0730079c, pxp->base + HW_PXP_CSC1_COEF2);
++
++ /* CSC2 - Bypass */
++ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
++ } else if (!input_is_YUV && output_is_YUV) {
++ /*
++ * Input = RGB, Output = YUV
++ * Use CSC2 to convert to YUV
++ */
++
++ /* CSC1 - Bypass */
++ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
++
++ /* CSC2 - RGB->YUV */
++ __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL);
++ __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0);
++ __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1);
++ __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2);
++ __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3);
++ __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4);
++ __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5);
++ } else {
++ /*
++ * Input = RGB, Output = RGB
++ * Input & Output both RGB, so bypass both CSCs
++ */
++
++ /* CSC1 - Bypass */
++ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
++
++ /* CSC2 - Bypass */
++ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
++ }
++
++ /* YCrCb colorspace */
++ /* Not sure when we use this...no YCrCb formats are defined for PxP */
++ /*
++ __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR);
++ __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR);
++ __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR);
++ */
++
++}
++
++static void pxp_set_s0buf(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ dma_addr_t Y, U, V;
++ dma_addr_t Y1, U1, V1;
++ u32 offset, bpp = 1;
++ u32 pitch = s0_params->stride ? s0_params->stride :
++ s0_params->width;
++
++ Y = s0_params->paddr;
++
++ if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB565)
++ bpp = 2;
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB32)
++ bpp = 4;
++ offset = (proc_data->srect.top * s0_params->width +
++ proc_data->srect.left) * bpp;
++ /* clipping or cropping */
++ Y1 = Y + offset;
++ __raw_writel(Y1, pxp->base + HW_PXP_PS_BUF);
++ if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)) {
++ /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */
++ int s = 2;
++ if (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)
++ s = 1;
++
++ offset = proc_data->srect.top * s0_params->width / 4 +
++ proc_data->srect.left / 2;
++ U = Y + (s0_params->width * s0_params->height);
++ U1 = U + offset;
++ V = U + ((s0_params->width * s0_params->height) >> s);
++ V1 = V + offset;
++ __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF);
++ __raw_writel(V1, pxp->base + HW_PXP_PS_VBUF);
++ } else if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV12) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_NV21) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_NV16) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) {
++ int s = 2;
++ if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV16) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_NV61))
++ s = 1;
++
++ offset = (proc_data->srect.top * s0_params->width +
++ proc_data->srect.left) / s;
++ U = Y + (s0_params->width * s0_params->height);
++ U1 = U + offset;
++
++ __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF);
++ }
++
++ /* TODO: only support RGB565, Y8, Y4, YUV420 */
++ if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_NV12 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_NV21 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_NV16 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_NV61 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) {
++ __raw_writel(pitch, pxp->base + HW_PXP_PS_PITCH);
++ }
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04)
++ __raw_writel(pitch >> 1,
++ pxp->base + HW_PXP_PS_PITCH);
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB32)
++ __raw_writel(pitch << 2,
++ pxp->base + HW_PXP_PS_PITCH);
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_UYVY ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YUYV ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_VYUY ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YVYU)
++ __raw_writel(pitch << 1,
++ pxp->base + HW_PXP_PS_PITCH);
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB565)
++ __raw_writel(pitch << 1,
++ pxp->base + HW_PXP_PS_PITCH);
++ else
++ __raw_writel(0, pxp->base + HW_PXP_PS_PITCH);
++}
++
++/**
++ * pxp_config() - configure PxP for a processing task
++ * @pxps: PXP context.
++ * @pxp_chan: PXP channel.
++ * @return: 0 on success or negative error code on failure.
++ */
++static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan)
++{
++ struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state;
++ int ol_nr;
++ int i;
++
++ /* Configure PxP regs */
++ pxp_set_ctrl(pxp);
++ pxp_set_s0param(pxp);
++ pxp_set_s0crop(pxp);
++ pxp_set_scaling(pxp);
++ ol_nr = pxp_conf_data->layer_nr - 2;
++ while (ol_nr > 0) {
++ i = pxp_conf_data->layer_nr - 2 - ol_nr;
++ pxp_set_oln(i, pxp);
++ pxp_set_olparam(i, pxp);
++ /* only the color key in higher overlay will take effect. */
++ pxp_set_olcolorkey(i, pxp);
++ ol_nr--;
++ }
++ pxp_set_s0colorkey(pxp);
++ pxp_set_csc(pxp);
++ pxp_set_bg(pxp);
++ pxp_set_lut(pxp);
++
++ pxp_set_s0buf(pxp);
++ pxp_set_outbuf(pxp);
++
++ return 0;
++}
++
++static void pxp_clk_enable(struct pxps *pxp)
++{
++ mutex_lock(&pxp->clk_mutex);
++
++ if (pxp->clk_stat == CLK_STAT_ON) {
++ mutex_unlock(&pxp->clk_mutex);
++ return;
++ }
++
++ pm_runtime_get_sync(pxp->dev);
++
++ clk_prepare_enable(pxp->clk);
++ pxp->clk_stat = CLK_STAT_ON;
++
++ mutex_unlock(&pxp->clk_mutex);
++}
++
++static void pxp_clk_disable(struct pxps *pxp)
++{
++ unsigned long flags;
++
++ mutex_lock(&pxp->clk_mutex);
++
++ if (pxp->clk_stat == CLK_STAT_OFF) {
++ mutex_unlock(&pxp->clk_mutex);
++ return;
++ }
++
++ spin_lock_irqsave(&pxp->lock, flags);
++ if ((pxp->pxp_ongoing == 0) && list_empty(&head)) {
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ clk_disable_unprepare(pxp->clk);
++ pxp->clk_stat = CLK_STAT_OFF;
++ } else
++ spin_unlock_irqrestore(&pxp->lock, flags);
++
++ pm_runtime_put_sync_suspend(pxp->dev);
++
++ mutex_unlock(&pxp->clk_mutex);
++}
++
++static inline void clkoff_callback(struct work_struct *w)
++{
++ struct pxps *pxp = container_of(w, struct pxps, work);
++
++ pxp_clk_disable(pxp);
++}
++
++static void pxp_clkoff_timer(unsigned long arg)
++{
++ struct pxps *pxp = (struct pxps *)arg;
++
++ if ((pxp->pxp_ongoing == 0) && list_empty(&head))
++ schedule_work(&pxp->work);
++ else
++ mod_timer(&pxp->clk_timer,
++ jiffies + msecs_to_jiffies(timeout_in_ms));
++}
++
++static struct pxp_tx_desc *pxpdma_first_active(struct pxp_channel *pxp_chan)
++{
++ return list_entry(pxp_chan->active_list.next, struct pxp_tx_desc, list);
++}
++
++static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan)
++{
++ return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list);
++}
++
++/* called with pxp_chan->lock held */
++static void __pxpdma_dostart(struct pxp_channel *pxp_chan)
++{
++ struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device);
++ struct pxps *pxp = to_pxp(pxp_dma);
++ struct pxp_tx_desc *desc;
++ struct pxp_tx_desc *child;
++ int i = 0;
++
++ /* so far we presume only one transaction on active_list */
++ /* S0 */
++ desc = pxpdma_first_active(pxp_chan);
++ memcpy(&pxp->pxp_conf_state.s0_param,
++ &desc->layer_param.s0_param, sizeof(struct pxp_layer_param));
++ memcpy(&pxp->pxp_conf_state.proc_data,
++ &desc->proc_data, sizeof(struct pxp_proc_data));
++
++ /* Save PxP configuration */
++ list_for_each_entry(child, &desc->tx_list, list) {
++ if (i == 0) { /* Output */
++ memcpy(&pxp->pxp_conf_state.out_param,
++ &child->layer_param.out_param,
++ sizeof(struct pxp_layer_param));
++ } else { /* Overlay */
++ memcpy(&pxp->pxp_conf_state.ol_param[i - 1],
++ &child->layer_param.ol_param,
++ sizeof(struct pxp_layer_param));
++ }
++
++ i++;
++ }
++ pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__,
++ pxp->pxp_conf_state.s0_param.width,
++ pxp->pxp_conf_state.s0_param.height,
++ pxp->pxp_conf_state.s0_param.paddr);
++ pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__,
++ pxp->pxp_conf_state.out_param.width,
++ pxp->pxp_conf_state.out_param.height,
++ pxp->pxp_conf_state.out_param.paddr);
++}
++
++static void pxpdma_dostart_work(struct pxps *pxp)
++{
++ struct pxp_channel *pxp_chan = NULL;
++ unsigned long flags, flags1;
++
++ spin_lock_irqsave(&pxp->lock, flags);
++ if (list_empty(&head)) {
++ pxp->pxp_ongoing = 0;
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ return;
++ }
++
++ pxp_chan = list_entry(head.next, struct pxp_channel, list);
++
++ spin_lock_irqsave(&pxp_chan->lock, flags1);
++ if (!list_empty(&pxp_chan->active_list)) {
++ struct pxp_tx_desc *desc;
++ /* REVISIT */
++ desc = pxpdma_first_active(pxp_chan);
++ __pxpdma_dostart(pxp_chan);
++ }
++ spin_unlock_irqrestore(&pxp_chan->lock, flags1);
++
++ /* Configure PxP */
++ pxp_config(pxp, pxp_chan);
++
++ pxp_start(pxp);
++
++ spin_unlock_irqrestore(&pxp->lock, flags);
++}
++
++static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct list_head *list)
++{
++ struct pxp_tx_desc *desc = NULL;
++ do {
++ desc = pxpdma_first_queued(pxp_chan);
++ list_move_tail(&desc->list, list);
++ } while (!list_empty(&pxp_chan->queue));
++}
++
++static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx)
++{
++ struct pxp_tx_desc *desc = to_tx_desc(tx);
++ struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan);
++ dma_cookie_t cookie;
++ unsigned long flags;
++
++ dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n");
++
++ mutex_lock(&pxp_chan->chan_mutex);
++
++ cookie = pxp_chan->dma_chan.cookie;
++
++ if (++cookie < 0)
++ cookie = 1;
++
++ /* from dmaengine.h: "last cookie value returned to client" */
++ pxp_chan->dma_chan.cookie = cookie;
++ tx->cookie = cookie;
++
++ /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */
++ spin_lock_irqsave(&pxp_chan->lock, flags);
++
++ /* Here we add the tx descriptor to our PxP task queue. */
++ list_add_tail(&desc->list, &pxp_chan->queue);
++
++ spin_unlock_irqrestore(&pxp_chan->lock, flags);
++
++ dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n");
++
++ mutex_unlock(&pxp_chan->chan_mutex);
++ return cookie;
++}
++
++/* Called with pxp_chan->chan_mutex held */
++static int pxp_desc_alloc(struct pxp_channel *pxp_chan, int n)
++{
++ struct pxp_tx_desc *desc = vmalloc(n * sizeof(struct pxp_tx_desc));
++
++ if (!desc)
++ return -ENOMEM;
++
++ pxp_chan->n_tx_desc = n;
++ pxp_chan->desc = desc;
++ INIT_LIST_HEAD(&pxp_chan->active_list);
++ INIT_LIST_HEAD(&pxp_chan->queue);
++ INIT_LIST_HEAD(&pxp_chan->free_list);
++
++ while (n--) {
++ struct dma_async_tx_descriptor *txd = &desc->txd;
++
++ memset(txd, 0, sizeof(*txd));
++ INIT_LIST_HEAD(&desc->tx_list);
++ dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan);
++ txd->tx_submit = pxp_tx_submit;
++
++ list_add(&desc->list, &pxp_chan->free_list);
++
++ desc++;
++ }
++
++ return 0;
++}
++
++/**
++ * pxp_init_channel() - initialize a PXP channel.
++ * @pxp_dma: PXP DMA context.
++ * @pchan: pointer to the channel object.
++ * @return 0 on success or negative error code on failure.
++ */
++static int pxp_init_channel(struct pxp_dma *pxp_dma,
++ struct pxp_channel *pxp_chan)
++{
++ unsigned long flags;
++ struct pxps *pxp = to_pxp(pxp_dma);
++ int ret = 0, n_desc = 0;
++
++ /*
++ * We are using _virtual_ channel here.
++ * Each channel contains all parameters of corresponding layers
++ * for one transaction; each layer is represented as one descriptor
++ * (i.e., pxp_tx_desc) here.
++ */
++
++ spin_lock_irqsave(&pxp->lock, flags);
++
++ /* max desc nr: S0+OL+OUT = 1+8+1 */
++ n_desc = 16;
++
++ spin_unlock_irqrestore(&pxp->lock, flags);
++
++ if (n_desc && !pxp_chan->desc)
++ ret = pxp_desc_alloc(pxp_chan, n_desc);
++
++ return ret;
++}
++
++/**
++ * pxp_uninit_channel() - uninitialize a PXP channel.
++ * @pxp_dma: PXP DMA context.
++ * @pchan: pointer to the channel object.
++ * @return 0 on success or negative error code on failure.
++ */
++static int pxp_uninit_channel(struct pxp_dma *pxp_dma,
++ struct pxp_channel *pxp_chan)
++{
++ int ret = 0;
++
++ if (pxp_chan->desc)
++ vfree(pxp_chan->desc);
++
++ pxp_chan->desc = NULL;
++
++ return ret;
++}
++
++static irqreturn_t pxp_irq(int irq, void *dev_id)
++{
++ struct pxps *pxp = dev_id;
++ struct pxp_channel *pxp_chan;
++ struct pxp_tx_desc *desc;
++ dma_async_tx_callback callback;
++ void *callback_param;
++ unsigned long flags;
++ u32 hist_status;
++
++ dump_pxp_reg(pxp);
++
++ hist_status =
++ __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS;
++
++ __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR);
++
++ spin_lock_irqsave(&pxp->lock, flags);
++
++ if (list_empty(&head)) {
++ pxp->pxp_ongoing = 0;
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ return IRQ_NONE;
++ }
++
++ pxp_chan = list_entry(head.next, struct pxp_channel, list);
++ list_del_init(&pxp_chan->list);
++
++ if (list_empty(&pxp_chan->active_list)) {
++ pr_debug("PXP_IRQ pxp_chan->active_list empty. chan_id %d\n",
++ pxp_chan->dma_chan.chan_id);
++ pxp->pxp_ongoing = 0;
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ return IRQ_NONE;
++ }
++
++ /* Get descriptor and call callback */
++ desc = pxpdma_first_active(pxp_chan);
++
++ pxp_chan->completed = desc->txd.cookie;
++
++ callback = desc->txd.callback;
++ callback_param = desc->txd.callback_param;
++
++ /* Send histogram status back to caller */
++ desc->hist_status = hist_status;
++
++ if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
++ callback(callback_param);
++
++ pxp_chan->status = PXP_CHANNEL_INITIALIZED;
++
++ list_splice_init(&desc->tx_list, &pxp_chan->free_list);
++ list_move(&desc->list, &pxp_chan->free_list);
++
++ mutex_unlock(&hard_lock);
++ pxp->pxp_ongoing = 0;
++ mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms));
++
++ spin_unlock_irqrestore(&pxp->lock, flags);
++
++ return IRQ_HANDLED;
++}
++
++/* called with pxp_chan->lock held */
++static struct pxp_tx_desc *pxpdma_desc_get(struct pxp_channel *pxp_chan)
++{
++ struct pxp_tx_desc *desc, *_desc;
++ struct pxp_tx_desc *ret = NULL;
++
++ list_for_each_entry_safe(desc, _desc, &pxp_chan->free_list, list) {
++ list_del_init(&desc->list);
++ ret = desc;
++ break;
++ }
++
++ return ret;
++}
++
++/* called with pxp_chan->lock held */
++static void pxpdma_desc_put(struct pxp_channel *pxp_chan,
++ struct pxp_tx_desc *desc)
++{
++ if (desc) {
++ struct device *dev = &pxp_chan->dma_chan.dev->device;
++ struct pxp_tx_desc *child;
++
++ list_for_each_entry(child, &desc->tx_list, list)
++ dev_info(dev, "moving child desc %p to freelist\n", child);
++ list_splice_init(&desc->tx_list, &pxp_chan->free_list);
++ dev_info(dev, "moving desc %p to freelist\n", desc);
++ list_add(&desc->list, &pxp_chan->free_list);
++ }
++}
++
++/* Allocate and initialise a transfer descriptor. */
++static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan,
++ struct scatterlist
++ *sgl,
++ unsigned int sg_len,
++ enum
++ dma_transfer_direction
++ direction,
++ unsigned long tx_flags,
++ void *context)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
++ struct pxps *pxp = to_pxp(pxp_dma);
++ struct pxp_tx_desc *desc = NULL;
++ struct pxp_tx_desc *first = NULL, *prev = NULL;
++ struct scatterlist *sg;
++ unsigned long flags;
++ dma_addr_t phys_addr;
++ int i;
++
++ if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) {
++ dev_err(chan->device->dev, "Invalid DMA direction %d!\n",
++ direction);
++ return NULL;
++ }
++
++ if (unlikely(sg_len < 2))
++ return NULL;
++
++ spin_lock_irqsave(&pxp_chan->lock, flags);
++ for_each_sg(sgl, sg, sg_len, i) {
++ desc = pxpdma_desc_get(pxp_chan);
++ if (!desc) {
++ pxpdma_desc_put(pxp_chan, first);
++ dev_err(chan->device->dev, "Can't get DMA desc.\n");
++ spin_unlock_irqrestore(&pxp_chan->lock, flags);
++ return NULL;
++ }
++
++ phys_addr = sg_dma_address(sg);
++
++ if (!first) {
++ first = desc;
++
++ desc->layer_param.s0_param.paddr = phys_addr;
++ } else {
++ list_add_tail(&desc->list, &first->tx_list);
++ prev->next = desc;
++ desc->next = NULL;
++
++ if (i == 1)
++ desc->layer_param.out_param.paddr = phys_addr;
++ else
++ desc->layer_param.ol_param.paddr = phys_addr;
++ }
++
++ prev = desc;
++ }
++ spin_unlock_irqrestore(&pxp_chan->lock, flags);
++
++ pxp->pxp_conf_state.layer_nr = sg_len;
++ first->txd.flags = tx_flags;
++ first->len = sg_len;
++ pr_debug("%s:%d first %p, first->len %d, flags %08x\n",
++ __func__, __LINE__, first, first->len, first->txd.flags);
++
++ return &first->txd;
++}
++
++static void pxp_issue_pending(struct dma_chan *chan)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
++ struct pxps *pxp = to_pxp(pxp_dma);
++ unsigned long flags0, flags;
++
++ spin_lock_irqsave(&pxp->lock, flags0);
++ spin_lock_irqsave(&pxp_chan->lock, flags);
++
++ if (!list_empty(&pxp_chan->queue)) {
++ pxpdma_dequeue(pxp_chan, &pxp_chan->active_list);
++ pxp_chan->status = PXP_CHANNEL_READY;
++ list_add_tail(&pxp_chan->list, &head);
++ } else {
++ spin_unlock_irqrestore(&pxp_chan->lock, flags);
++ spin_unlock_irqrestore(&pxp->lock, flags0);
++ return;
++ }
++ spin_unlock_irqrestore(&pxp_chan->lock, flags);
++ spin_unlock_irqrestore(&pxp->lock, flags0);
++
++ pxp_clk_enable(pxp);
++ mutex_lock(&hard_lock);
++
++ spin_lock_irqsave(&pxp->lock, flags);
++ pxp->pxp_ongoing = 1;
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ pxpdma_dostart_work(pxp);
++}
++
++static void __pxp_terminate_all(struct dma_chan *chan)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ unsigned long flags;
++
++ /* pchan->queue is modified in ISR, have to spinlock */
++ spin_lock_irqsave(&pxp_chan->lock, flags);
++ list_splice_init(&pxp_chan->queue, &pxp_chan->free_list);
++ list_splice_init(&pxp_chan->active_list, &pxp_chan->free_list);
++
++ spin_unlock_irqrestore(&pxp_chan->lock, flags);
++
++ pxp_chan->status = PXP_CHANNEL_INITIALIZED;
++}
++
++static int pxp_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
++ unsigned long arg)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++
++ /* Only supports DMA_TERMINATE_ALL */
++ if (cmd != DMA_TERMINATE_ALL)
++ return -ENXIO;
++
++ mutex_lock(&pxp_chan->chan_mutex);
++ __pxp_terminate_all(chan);
++ mutex_unlock(&pxp_chan->chan_mutex);
++
++ return 0;
++}
++
++static int pxp_alloc_chan_resources(struct dma_chan *chan)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
++ int ret;
++
++ /* dmaengine.c now guarantees to only offer free channels */
++ BUG_ON(chan->client_count > 1);
++ WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE);
++
++ chan->cookie = 1;
++ pxp_chan->completed = -ENXIO;
++
++ pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id);
++ ret = pxp_init_channel(pxp_dma, pxp_chan);
++ if (ret < 0)
++ goto err_chan;
++
++ pxp_chan->status = PXP_CHANNEL_INITIALIZED;
++
++ dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
++ chan->chan_id, pxp_chan->eof_irq);
++
++ return ret;
++
++err_chan:
++ return ret;
++}
++
++static void pxp_free_chan_resources(struct dma_chan *chan)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
++
++ mutex_lock(&pxp_chan->chan_mutex);
++
++ __pxp_terminate_all(chan);
++
++ pxp_chan->status = PXP_CHANNEL_FREE;
++
++ pxp_uninit_channel(pxp_dma, pxp_chan);
++
++ mutex_unlock(&pxp_chan->chan_mutex);
++}
++
++static enum dma_status pxp_tx_status(struct dma_chan *chan,
++ dma_cookie_t cookie,
++ struct dma_tx_state *txstate)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++
++ if (cookie != chan->cookie)
++ return DMA_ERROR;
++
++ if (txstate) {
++ txstate->last = pxp_chan->completed;
++ txstate->used = chan->cookie;
++ txstate->residue = 0;
++ }
++ return DMA_SUCCESS;
++}
++
++static int pxp_hw_init(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ u32 reg_val;
++
++ /* Pull PxP out of reset */
++ __raw_writel(0, pxp->base + HW_PXP_CTRL);
++
++ /* Config defaults */
++
++ /* Initialize non-channel-specific PxP parameters */
++ proc_data->drect.left = proc_data->srect.left = 0;
++ proc_data->drect.top = proc_data->srect.top = 0;
++ proc_data->drect.width = proc_data->srect.width = 0;
++ proc_data->drect.height = proc_data->srect.height = 0;
++ proc_data->scaling = 0;
++ proc_data->hflip = 0;
++ proc_data->vflip = 0;
++ proc_data->rotate = 0;
++ proc_data->bgcolor = 0;
++
++ /* Initialize S0 channel parameters */
++ pxp_conf->s0_param.pixel_fmt = pxp_s0_formats[0];
++ pxp_conf->s0_param.width = 0;
++ pxp_conf->s0_param.height = 0;
++ pxp_conf->s0_param.color_key = -1;
++ pxp_conf->s0_param.color_key_enable = false;
++
++ /* Initialize OL channel parameters */
++ pxp_conf->ol_param[0].combine_enable = false;
++ pxp_conf->ol_param[0].width = 0;
++ pxp_conf->ol_param[0].height = 0;
++ pxp_conf->ol_param[0].pixel_fmt = PXP_PIX_FMT_RGB565;
++ pxp_conf->ol_param[0].color_key_enable = false;
++ pxp_conf->ol_param[0].color_key = -1;
++ pxp_conf->ol_param[0].global_alpha_enable = false;
++ pxp_conf->ol_param[0].global_alpha = 0;
++ pxp_conf->ol_param[0].local_alpha_enable = false;
++
++ /* Initialize Output channel parameters */
++ pxp_conf->out_param.width = 0;
++ pxp_conf->out_param.height = 0;
++ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++
++ proc_data->overlay_state = 0;
++
++ /* Write default h/w config */
++ pxp_set_ctrl(pxp);
++ pxp_set_s0param(pxp);
++ pxp_set_s0crop(pxp);
++ /*
++ * simply program the ULC to a higher value than the LRC
++ * to avoid any AS pixels to show up in the output buffer.
++ */
++ __raw_writel(0xFFFFFFFF, pxp->base + HW_PXP_OUT_AS_ULC);
++ pxp_set_olparam(0, pxp);
++ pxp_set_olcolorkey(0, pxp);
++
++ pxp_set_s0colorkey(pxp);
++ pxp_set_csc(pxp);
++ pxp_set_bg(pxp);
++ pxp_set_lut(pxp);
++
++ /* One-time histogram configuration */
++ reg_val =
++ BF_PXP_HIST_CTRL_PANEL_MODE(BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST_CTRL);
++
++ reg_val = BF_PXP_HIST2_PARAM_VALUE0(0x00) |
++ BF_PXP_HIST2_PARAM_VALUE1(0x00F);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST2_PARAM);
++
++ reg_val = BF_PXP_HIST4_PARAM_VALUE0(0x00) |
++ BF_PXP_HIST4_PARAM_VALUE1(0x05) |
++ BF_PXP_HIST4_PARAM_VALUE2(0x0A) | BF_PXP_HIST4_PARAM_VALUE3(0x0F);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST4_PARAM);
++
++ reg_val = BF_PXP_HIST8_PARAM0_VALUE0(0x00) |
++ BF_PXP_HIST8_PARAM0_VALUE1(0x02) |
++ BF_PXP_HIST8_PARAM0_VALUE2(0x04) | BF_PXP_HIST8_PARAM0_VALUE3(0x06);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM0);
++ reg_val = BF_PXP_HIST8_PARAM1_VALUE4(0x09) |
++ BF_PXP_HIST8_PARAM1_VALUE5(0x0B) |
++ BF_PXP_HIST8_PARAM1_VALUE6(0x0D) | BF_PXP_HIST8_PARAM1_VALUE7(0x0F);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST8_PARAM1);
++
++ reg_val = BF_PXP_HIST16_PARAM0_VALUE0(0x00) |
++ BF_PXP_HIST16_PARAM0_VALUE1(0x01) |
++ BF_PXP_HIST16_PARAM0_VALUE2(0x02) |
++ BF_PXP_HIST16_PARAM0_VALUE3(0x03);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM0);
++ reg_val = BF_PXP_HIST16_PARAM1_VALUE4(0x04) |
++ BF_PXP_HIST16_PARAM1_VALUE5(0x05) |
++ BF_PXP_HIST16_PARAM1_VALUE6(0x06) |
++ BF_PXP_HIST16_PARAM1_VALUE7(0x07);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM1);
++ reg_val = BF_PXP_HIST16_PARAM2_VALUE8(0x08) |
++ BF_PXP_HIST16_PARAM2_VALUE9(0x09) |
++ BF_PXP_HIST16_PARAM2_VALUE10(0x0A) |
++ BF_PXP_HIST16_PARAM2_VALUE11(0x0B);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM2);
++ reg_val = BF_PXP_HIST16_PARAM3_VALUE12(0x0C) |
++ BF_PXP_HIST16_PARAM3_VALUE13(0x0D) |
++ BF_PXP_HIST16_PARAM3_VALUE14(0x0E) |
++ BF_PXP_HIST16_PARAM3_VALUE15(0x0F);
++ __raw_writel(reg_val, pxp->base + HW_PXP_HIST16_PARAM3);
++
++ return 0;
++}
++
++static int pxp_dma_init(struct pxps *pxp)
++{
++ struct pxp_dma *pxp_dma = &pxp->pxp_dma;
++ struct dma_device *dma = &pxp_dma->dma;
++ int i;
++
++ dma_cap_set(DMA_SLAVE, dma->cap_mask);
++ dma_cap_set(DMA_PRIVATE, dma->cap_mask);
++
++ /* Compulsory common fields */
++ dma->dev = pxp->dev;
++ dma->device_alloc_chan_resources = pxp_alloc_chan_resources;
++ dma->device_free_chan_resources = pxp_free_chan_resources;
++ dma->device_tx_status = pxp_tx_status;
++ dma->device_issue_pending = pxp_issue_pending;
++
++ /* Compulsory for DMA_SLAVE fields */
++ dma->device_prep_slave_sg = pxp_prep_slave_sg;
++ dma->device_control = pxp_control;
++
++ /* Initialize PxP Channels */
++ INIT_LIST_HEAD(&dma->channels);
++ for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) {
++ struct pxp_channel *pxp_chan = pxp->channel + i;
++ struct dma_chan *dma_chan = &pxp_chan->dma_chan;
++
++ spin_lock_init(&pxp_chan->lock);
++ mutex_init(&pxp_chan->chan_mutex);
++
++ /* Only one EOF IRQ for PxP, shared by all channels */
++ pxp_chan->eof_irq = pxp->irq;
++ pxp_chan->status = PXP_CHANNEL_FREE;
++ pxp_chan->completed = -ENXIO;
++ snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name),
++ "PXP EOF %d", i);
++
++ dma_chan->device = &pxp_dma->dma;
++ dma_chan->cookie = 1;
++ dma_chan->chan_id = i;
++ list_add_tail(&dma_chan->device_node, &dma->channels);
++ }
++
++ return dma_async_device_register(&pxp_dma->dma);
++}
++
++static ssize_t clk_off_timeout_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "%d\n", timeout_in_ms);
++}
++
++static ssize_t clk_off_timeout_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ int val;
++ if (sscanf(buf, "%d", &val) > 0) {
++ timeout_in_ms = val;
++ return count;
++ }
++ return -EINVAL;
++}
++
++static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show,
++ clk_off_timeout_store);
++
++static ssize_t block_size_show(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ return sprintf(buf, "%d\n", block_size);
++}
++
++static ssize_t block_size_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ char **last = NULL;
++
++ block_size = simple_strtoul(buf, last, 0);
++ if (block_size > 1)
++ block_size = 1;
++
++ return count;
++}
++static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO,
++ block_size_show, block_size_store);
++
++static const struct of_device_id imx_pxpdma_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-pxp-dma", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids);
++
++static int pxp_probe(struct platform_device *pdev)
++{
++ struct pxps *pxp;
++ struct resource *res;
++ int irq;
++ int err = 0;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ irq = platform_get_irq(pdev, 0);
++ if (!res || irq < 0) {
++ err = -ENODEV;
++ goto exit;
++ }
++
++ pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL);
++ if (!pxp) {
++ dev_err(&pdev->dev, "failed to allocate control object\n");
++ err = -ENOMEM;
++ goto exit;
++ }
++
++ pxp->dev = &pdev->dev;
++
++ platform_set_drvdata(pdev, pxp);
++ pxp->irq = irq;
++
++ pxp->pxp_ongoing = 0;
++ pxp->lut_state = 0;
++
++ spin_lock_init(&pxp->lock);
++ mutex_init(&pxp->clk_mutex);
++ mutex_init(&hard_lock);
++
++ pxp->base = devm_request_and_ioremap(&pdev->dev, res);
++ if (pxp->base == NULL) {
++ dev_err(&pdev->dev, "Couldn't ioremap regs\n");
++ err = -ENODEV;
++ goto exit;
++ }
++
++ pxp->pdev = pdev;
++
++ pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi");
++ clk_prepare_enable(pxp->clk);
++
++ err = pxp_hw_init(pxp);
++ clk_disable_unprepare(pxp->clk);
++ if (err) {
++ dev_err(&pdev->dev, "failed to initialize hardware\n");
++ goto exit;
++ }
++
++ err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0,
++ "pxp-dmaengine", pxp);
++ if (err)
++ goto exit;
++ /* Initialize DMA engine */
++ err = pxp_dma_init(pxp);
++ if (err < 0)
++ goto exit;
++
++ if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) {
++ dev_err(&pdev->dev,
++ "Unable to create file from clk_off_timeout\n");
++ goto exit;
++ }
++
++ device_create_file(&pdev->dev, &dev_attr_block_size);
++ dump_pxp_reg(pxp);
++
++ INIT_WORK(&pxp->work, clkoff_callback);
++ init_timer(&pxp->clk_timer);
++ pxp->clk_timer.function = pxp_clkoff_timer;
++ pxp->clk_timer.data = (unsigned long)pxp;
++
++ register_pxp_device();
++
++ pm_runtime_enable(pxp->dev);
++
++exit:
++ if (err)
++ dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n");
++ return err;
++}
++
++static int pxp_remove(struct platform_device *pdev)
++{
++ struct pxps *pxp = platform_get_drvdata(pdev);
++
++ unregister_pxp_device();
++ cancel_work_sync(&pxp->work);
++ del_timer_sync(&pxp->clk_timer);
++ clk_disable_unprepare(pxp->clk);
++ device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout);
++ device_remove_file(&pdev->dev, &dev_attr_block_size);
++ dma_async_device_unregister(&(pxp->pxp_dma.dma));
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int pxp_suspend(struct device *dev)
++{
++ struct pxps *pxp = dev_get_drvdata(dev);
++
++ pxp_clk_enable(pxp);
++ while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE)
++ ;
++
++ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL);
++ pxp_clk_disable(pxp);
++
++ return 0;
++}
++
++static int pxp_resume(struct device *dev)
++{
++ struct pxps *pxp = dev_get_drvdata(dev);
++
++ pxp_clk_enable(pxp);
++ /* Pull PxP out of reset */
++ __raw_writel(0, pxp->base + HW_PXP_CTRL);
++ pxp_clk_disable(pxp);
++
++ return 0;
++}
++#else
++#define pxp_suspend NULL
++#define pxp_resume NULL
++#endif
++
++#ifdef CONFIG_PM_RUNTIME
++static int pxp_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "pxp busfreq high release.\n");
++
++ return 0;
++}
++
++static int pxp_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "pxp busfreq high request.\n");
++
++ return 0;
++}
++#else
++#define pxp_runtime_suspend NULL
++#define pxp_runtime_resume NULL
++#endif
++
++static const struct dev_pm_ops pxp_pm_ops = {
++ SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume)
++};
++
++static struct platform_driver pxp_driver = {
++ .driver = {
++ .name = "imx-pxp",
++ .of_match_table = of_match_ptr(imx_pxpdma_dt_ids),
++ .pm = &pxp_pm_ops,
++ },
++ .probe = pxp_probe,
++ .remove = pxp_remove,
++};
++
++module_platform_driver(pxp_driver);
++
++
++MODULE_DESCRIPTION("i.MX PxP driver");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/dma/pxp/regs-pxp_v2.h linux-linaro-stable-mx6/drivers/dma/pxp/regs-pxp_v2.h
+--- linux-3.10.30.orig/drivers/dma/pxp/regs-pxp_v2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/dma/pxp/regs-pxp_v2.h 2014-05-15 20:33:46.917934005 +0200
+@@ -0,0 +1,1152 @@
++/*
++ * Freescale PXP Register Definitions
++ *
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * This file is created by xml file. Don't Edit it.
++ *
++ * Xml Revision: 1.29
++ * Template revision: 1.3
++ */
++
++#ifndef __ARCH_ARM___PXP_H
++#define __ARCH_ARM___PXP_H
++
++#define HW_PXP_CTRL (0x00000000)
++#define HW_PXP_CTRL_SET (0x00000004)
++#define HW_PXP_CTRL_CLR (0x00000008)
++#define HW_PXP_CTRL_TOG (0x0000000c)
++
++#define BM_PXP_CTRL_SFTRST 0x80000000
++#define BM_PXP_CTRL_CLKGATE 0x40000000
++#define BM_PXP_CTRL_RSVD4 0x20000000
++#define BM_PXP_CTRL_EN_REPEAT 0x10000000
++#define BP_PXP_CTRL_RSVD3 26
++#define BM_PXP_CTRL_RSVD3 0x0C000000
++#define BF_PXP_CTRL_RSVD3(v) \
++ (((v) << 26) & BM_PXP_CTRL_RSVD3)
++#define BP_PXP_CTRL_INTERLACED_INPUT 24
++#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000
++#define BF_PXP_CTRL_INTERLACED_INPUT(v) \
++ (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT)
++#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0
++#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2
++#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3
++#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000
++#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0
++#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1
++#define BM_PXP_CTRL_ROT_POS 0x00400000
++#define BM_PXP_CTRL_IN_PLACE 0x00200000
++#define BP_PXP_CTRL_RSVD1 12
++#define BM_PXP_CTRL_RSVD1 0x001FF000
++#define BF_PXP_CTRL_RSVD1(v) \
++ (((v) << 12) & BM_PXP_CTRL_RSVD1)
++#define BM_PXP_CTRL_VFLIP 0x00000800
++#define BM_PXP_CTRL_HFLIP 0x00000400
++#define BP_PXP_CTRL_ROTATE 8
++#define BM_PXP_CTRL_ROTATE 0x00000300
++#define BF_PXP_CTRL_ROTATE(v) \
++ (((v) << 8) & BM_PXP_CTRL_ROTATE)
++#define BV_PXP_CTRL_ROTATE__ROT_0 0x0
++#define BV_PXP_CTRL_ROTATE__ROT_90 0x1
++#define BV_PXP_CTRL_ROTATE__ROT_180 0x2
++#define BV_PXP_CTRL_ROTATE__ROT_270 0x3
++#define BP_PXP_CTRL_RSVD0 5
++#define BM_PXP_CTRL_RSVD0 0x000000E0
++#define BF_PXP_CTRL_RSVD0(v) \
++ (((v) << 5) & BM_PXP_CTRL_RSVD0)
++#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000010
++#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008
++#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004
++#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
++#define BM_PXP_CTRL_ENABLE 0x00000001
++
++#define HW_PXP_STAT (0x00000010)
++#define HW_PXP_STAT_SET (0x00000014)
++#define HW_PXP_STAT_CLR (0x00000018)
++#define HW_PXP_STAT_TOG (0x0000001c)
++
++#define BP_PXP_STAT_BLOCKX 24
++#define BM_PXP_STAT_BLOCKX 0xFF000000
++#define BF_PXP_STAT_BLOCKX(v) \
++ (((v) << 24) & BM_PXP_STAT_BLOCKX)
++#define BP_PXP_STAT_BLOCKY 16
++#define BM_PXP_STAT_BLOCKY 0x00FF0000
++#define BF_PXP_STAT_BLOCKY(v) \
++ (((v) << 16) & BM_PXP_STAT_BLOCKY)
++#define BP_PXP_STAT_RSVD2 9
++#define BM_PXP_STAT_RSVD2 0x0000FE00
++#define BF_PXP_STAT_RSVD2(v) \
++ (((v) << 9) & BM_PXP_STAT_RSVD2)
++#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100
++#define BP_PXP_STAT_AXI_ERROR_ID 4
++#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0
++#define BF_PXP_STAT_AXI_ERROR_ID(v) \
++ (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID)
++#define BM_PXP_STAT_NEXT_IRQ 0x00000008
++#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004
++#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002
++#define BM_PXP_STAT_IRQ 0x00000001
++
++#define HW_PXP_OUT_CTRL (0x00000020)
++#define HW_PXP_OUT_CTRL_SET (0x00000024)
++#define HW_PXP_OUT_CTRL_CLR (0x00000028)
++#define HW_PXP_OUT_CTRL_TOG (0x0000002c)
++
++#define BP_PXP_OUT_CTRL_ALPHA 24
++#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000
++#define BF_PXP_OUT_CTRL_ALPHA(v) \
++ (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA)
++#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000
++#define BP_PXP_OUT_CTRL_RSVD1 10
++#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00
++#define BF_PXP_OUT_CTRL_RSVD1(v) \
++ (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1)
++#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8
++#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300
++#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \
++ (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT)
++#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
++#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1
++#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2
++#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3
++#define BP_PXP_OUT_CTRL_RSVD0 5
++#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0
++#define BF_PXP_OUT_CTRL_RSVD0(v) \
++ (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0)
++#define BP_PXP_OUT_CTRL_FORMAT 0
++#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F
++#define BF_PXP_OUT_CTRL_FORMAT(v) \
++ (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
++#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0
++#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4
++#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5
++#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8
++#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9
++#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC
++#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD
++#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE
++#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10
++#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12
++#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13
++#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14
++#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15
++#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18
++#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19
++#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A
++#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B
++
++#define HW_PXP_OUT_BUF (0x00000030)
++
++#define BP_PXP_OUT_BUF_ADDR 0
++#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF
++#define BF_PXP_OUT_BUF_ADDR(v) (v)
++
++#define HW_PXP_OUT_BUF2 (0x00000040)
++
++#define BP_PXP_OUT_BUF2_ADDR 0
++#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF
++#define BF_PXP_OUT_BUF2_ADDR(v) (v)
++
++#define HW_PXP_OUT_PITCH (0x00000050)
++
++#define BP_PXP_OUT_PITCH_RSVD 16
++#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000
++#define BF_PXP_OUT_PITCH_RSVD(v) \
++ (((v) << 16) & BM_PXP_OUT_PITCH_RSVD)
++#define BP_PXP_OUT_PITCH_PITCH 0
++#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF
++#define BF_PXP_OUT_PITCH_PITCH(v) \
++ (((v) << 0) & BM_PXP_OUT_PITCH_PITCH)
++
++#define HW_PXP_OUT_LRC (0x00000060)
++
++#define BP_PXP_OUT_LRC_RSVD1 30
++#define BM_PXP_OUT_LRC_RSVD1 0xC0000000
++#define BF_PXP_OUT_LRC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_LRC_RSVD1)
++#define BP_PXP_OUT_LRC_X 16
++#define BM_PXP_OUT_LRC_X 0x3FFF0000
++#define BF_PXP_OUT_LRC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_LRC_X)
++#define BP_PXP_OUT_LRC_RSVD0 14
++#define BM_PXP_OUT_LRC_RSVD0 0x0000C000
++#define BF_PXP_OUT_LRC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_LRC_RSVD0)
++#define BP_PXP_OUT_LRC_Y 0
++#define BM_PXP_OUT_LRC_Y 0x00003FFF
++#define BF_PXP_OUT_LRC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_LRC_Y)
++
++#define HW_PXP_OUT_PS_ULC (0x00000070)
++
++#define BP_PXP_OUT_PS_ULC_RSVD1 30
++#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000
++#define BF_PXP_OUT_PS_ULC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1)
++#define BP_PXP_OUT_PS_ULC_X 16
++#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000
++#define BF_PXP_OUT_PS_ULC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_PS_ULC_X)
++#define BP_PXP_OUT_PS_ULC_RSVD0 14
++#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000
++#define BF_PXP_OUT_PS_ULC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0)
++#define BP_PXP_OUT_PS_ULC_Y 0
++#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF
++#define BF_PXP_OUT_PS_ULC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_PS_ULC_Y)
++
++#define HW_PXP_OUT_PS_LRC (0x00000080)
++
++#define BP_PXP_OUT_PS_LRC_RSVD1 30
++#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000
++#define BF_PXP_OUT_PS_LRC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1)
++#define BP_PXP_OUT_PS_LRC_X 16
++#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000
++#define BF_PXP_OUT_PS_LRC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_PS_LRC_X)
++#define BP_PXP_OUT_PS_LRC_RSVD0 14
++#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000
++#define BF_PXP_OUT_PS_LRC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0)
++#define BP_PXP_OUT_PS_LRC_Y 0
++#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF
++#define BF_PXP_OUT_PS_LRC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_PS_LRC_Y)
++
++#define HW_PXP_OUT_AS_ULC (0x00000090)
++
++#define BP_PXP_OUT_AS_ULC_RSVD1 30
++#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000
++#define BF_PXP_OUT_AS_ULC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1)
++#define BP_PXP_OUT_AS_ULC_X 16
++#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000
++#define BF_PXP_OUT_AS_ULC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_AS_ULC_X)
++#define BP_PXP_OUT_AS_ULC_RSVD0 14
++#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000
++#define BF_PXP_OUT_AS_ULC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0)
++#define BP_PXP_OUT_AS_ULC_Y 0
++#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF
++#define BF_PXP_OUT_AS_ULC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_AS_ULC_Y)
++
++#define HW_PXP_OUT_AS_LRC (0x000000a0)
++
++#define BP_PXP_OUT_AS_LRC_RSVD1 30
++#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000
++#define BF_PXP_OUT_AS_LRC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1)
++#define BP_PXP_OUT_AS_LRC_X 16
++#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000
++#define BF_PXP_OUT_AS_LRC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_AS_LRC_X)
++#define BP_PXP_OUT_AS_LRC_RSVD0 14
++#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000
++#define BF_PXP_OUT_AS_LRC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0)
++#define BP_PXP_OUT_AS_LRC_Y 0
++#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF
++#define BF_PXP_OUT_AS_LRC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_AS_LRC_Y)
++
++#define HW_PXP_PS_CTRL (0x000000b0)
++#define HW_PXP_PS_CTRL_SET (0x000000b4)
++#define HW_PXP_PS_CTRL_CLR (0x000000b8)
++#define HW_PXP_PS_CTRL_TOG (0x000000bc)
++
++#define BP_PXP_PS_CTRL_RSVD1 12
++#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000
++#define BF_PXP_PS_CTRL_RSVD1(v) \
++ (((v) << 12) & BM_PXP_PS_CTRL_RSVD1)
++#define BP_PXP_PS_CTRL_DECX 10
++#define BM_PXP_PS_CTRL_DECX 0x00000C00
++#define BF_PXP_PS_CTRL_DECX(v) \
++ (((v) << 10) & BM_PXP_PS_CTRL_DECX)
++#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0
++#define BV_PXP_PS_CTRL_DECX__DECX2 0x1
++#define BV_PXP_PS_CTRL_DECX__DECX4 0x2
++#define BV_PXP_PS_CTRL_DECX__DECX8 0x3
++#define BP_PXP_PS_CTRL_DECY 8
++#define BM_PXP_PS_CTRL_DECY 0x00000300
++#define BF_PXP_PS_CTRL_DECY(v) \
++ (((v) << 8) & BM_PXP_PS_CTRL_DECY)
++#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0
++#define BV_PXP_PS_CTRL_DECY__DECY2 0x1
++#define BV_PXP_PS_CTRL_DECY__DECY4 0x2
++#define BV_PXP_PS_CTRL_DECY__DECY8 0x3
++#define BP_PXP_PS_CTRL_SWAP 5
++#define BM_PXP_PS_CTRL_SWAP 0x000000E0
++#define BF_PXP_PS_CTRL_SWAP(v) \
++ (((v) << 5) & BM_PXP_PS_CTRL_SWAP)
++#define BP_PXP_PS_CTRL_FORMAT 0
++#define BM_PXP_PS_CTRL_FORMAT 0x0000001F
++#define BF_PXP_PS_CTRL_FORMAT(v) \
++ (((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
++#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4
++#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC
++#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD
++#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE
++#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10
++#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12
++#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13
++#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14
++#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15
++#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18
++#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19
++#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A
++#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B
++#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E
++#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F
++
++#define HW_PXP_PS_BUF (0x000000c0)
++
++#define BP_PXP_PS_BUF_ADDR 0
++#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF
++#define BF_PXP_PS_BUF_ADDR(v) (v)
++
++#define HW_PXP_PS_UBUF (0x000000d0)
++
++#define BP_PXP_PS_UBUF_ADDR 0
++#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF
++#define BF_PXP_PS_UBUF_ADDR(v) (v)
++
++#define HW_PXP_PS_VBUF (0x000000e0)
++
++#define BP_PXP_PS_VBUF_ADDR 0
++#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF
++#define BF_PXP_PS_VBUF_ADDR(v) (v)
++
++#define HW_PXP_PS_PITCH (0x000000f0)
++
++#define BP_PXP_PS_PITCH_RSVD 16
++#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000
++#define BF_PXP_PS_PITCH_RSVD(v) \
++ (((v) << 16) & BM_PXP_PS_PITCH_RSVD)
++#define BP_PXP_PS_PITCH_PITCH 0
++#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF
++#define BF_PXP_PS_PITCH_PITCH(v) \
++ (((v) << 0) & BM_PXP_PS_PITCH_PITCH)
++
++#define HW_PXP_PS_BACKGROUND (0x00000100)
++
++#define BP_PXP_PS_BACKGROUND_RSVD 24
++#define BM_PXP_PS_BACKGROUND_RSVD 0xFF000000
++#define BF_PXP_PS_BACKGROUND_RSVD(v) \
++ (((v) << 24) & BM_PXP_PS_BACKGROUND_RSVD)
++#define BP_PXP_PS_BACKGROUND_COLOR 0
++#define BM_PXP_PS_BACKGROUND_COLOR 0x00FFFFFF
++#define BF_PXP_PS_BACKGROUND_COLOR(v) \
++ (((v) << 0) & BM_PXP_PS_BACKGROUND_COLOR)
++
++#define HW_PXP_PS_SCALE (0x00000110)
++
++#define BM_PXP_PS_SCALE_RSVD2 0x80000000
++#define BP_PXP_PS_SCALE_YSCALE 16
++#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000
++#define BF_PXP_PS_SCALE_YSCALE(v) \
++ (((v) << 16) & BM_PXP_PS_SCALE_YSCALE)
++#define BM_PXP_PS_SCALE_RSVD1 0x00008000
++#define BP_PXP_PS_SCALE_XSCALE 0
++#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF
++#define BF_PXP_PS_SCALE_XSCALE(v) \
++ (((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
++
++#define HW_PXP_PS_OFFSET (0x00000120)
++
++#define BP_PXP_PS_OFFSET_RSVD2 28
++#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000
++#define BF_PXP_PS_OFFSET_RSVD2(v) \
++ (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2)
++#define BP_PXP_PS_OFFSET_YOFFSET 16
++#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000
++#define BF_PXP_PS_OFFSET_YOFFSET(v) \
++ (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET)
++#define BP_PXP_PS_OFFSET_RSVD1 12
++#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000
++#define BF_PXP_PS_OFFSET_RSVD1(v) \
++ (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1)
++#define BP_PXP_PS_OFFSET_XOFFSET 0
++#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF
++#define BF_PXP_PS_OFFSET_XOFFSET(v) \
++ (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET)
++
++#define HW_PXP_PS_CLRKEYLOW (0x00000130)
++
++#define BP_PXP_PS_CLRKEYLOW_RSVD1 24
++#define BM_PXP_PS_CLRKEYLOW_RSVD1 0xFF000000
++#define BF_PXP_PS_CLRKEYLOW_RSVD1(v) \
++ (((v) << 24) & BM_PXP_PS_CLRKEYLOW_RSVD1)
++#define BP_PXP_PS_CLRKEYLOW_PIXEL 0
++#define BM_PXP_PS_CLRKEYLOW_PIXEL 0x00FFFFFF
++#define BF_PXP_PS_CLRKEYLOW_PIXEL(v) \
++ (((v) << 0) & BM_PXP_PS_CLRKEYLOW_PIXEL)
++
++#define HW_PXP_PS_CLRKEYHIGH (0x00000140)
++
++#define BP_PXP_PS_CLRKEYHIGH_RSVD1 24
++#define BM_PXP_PS_CLRKEYHIGH_RSVD1 0xFF000000
++#define BF_PXP_PS_CLRKEYHIGH_RSVD1(v) \
++ (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_RSVD1)
++#define BP_PXP_PS_CLRKEYHIGH_PIXEL 0
++#define BM_PXP_PS_CLRKEYHIGH_PIXEL 0x00FFFFFF
++#define BF_PXP_PS_CLRKEYHIGH_PIXEL(v) \
++ (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_PIXEL)
++
++#define HW_PXP_AS_CTRL (0x00000150)
++
++#define BP_PXP_AS_CTRL_RSVD1 21
++#define BM_PXP_AS_CTRL_RSVD1 0xFFE00000
++#define BF_PXP_AS_CTRL_RSVD1(v) \
++ (((v) << 21) & BM_PXP_AS_CTRL_RSVD1)
++#define BM_PXP_AS_CTRL_ALPHA_INVERT 0x00100000
++#define BP_PXP_AS_CTRL_ROP 16
++#define BM_PXP_AS_CTRL_ROP 0x000F0000
++#define BF_PXP_AS_CTRL_ROP(v) \
++ (((v) << 16) & BM_PXP_AS_CTRL_ROP)
++#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0
++#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1
++#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2
++#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3
++#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4
++#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5
++#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6
++#define BV_PXP_AS_CTRL_ROP__NOT 0x7
++#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8
++#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9
++#define BV_PXP_AS_CTRL_ROP__XORAS 0xA
++#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB
++#define BP_PXP_AS_CTRL_ALPHA 8
++#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00
++#define BF_PXP_AS_CTRL_ALPHA(v) \
++ (((v) << 8) & BM_PXP_AS_CTRL_ALPHA)
++#define BP_PXP_AS_CTRL_FORMAT 4
++#define BM_PXP_AS_CTRL_FORMAT 0x000000F0
++#define BF_PXP_AS_CTRL_FORMAT(v) \
++ (((v) << 4) & BM_PXP_AS_CTRL_FORMAT)
++#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0
++#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4
++#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8
++#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9
++#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC
++#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD
++#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE
++#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008
++#define BP_PXP_AS_CTRL_ALPHA_CTRL 1
++#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006
++#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \
++ (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL)
++#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0
++#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1
++#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2
++#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3
++#define BM_PXP_AS_CTRL_RSVD0 0x00000001
++
++#define HW_PXP_AS_BUF (0x00000160)
++
++#define BP_PXP_AS_BUF_ADDR 0
++#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF
++#define BF_PXP_AS_BUF_ADDR(v) (v)
++
++#define HW_PXP_AS_PITCH (0x00000170)
++
++#define BP_PXP_AS_PITCH_RSVD 16
++#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000
++#define BF_PXP_AS_PITCH_RSVD(v) \
++ (((v) << 16) & BM_PXP_AS_PITCH_RSVD)
++#define BP_PXP_AS_PITCH_PITCH 0
++#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF
++#define BF_PXP_AS_PITCH_PITCH(v) \
++ (((v) << 0) & BM_PXP_AS_PITCH_PITCH)
++
++#define HW_PXP_AS_CLRKEYLOW (0x00000180)
++
++#define BP_PXP_AS_CLRKEYLOW_RSVD1 24
++#define BM_PXP_AS_CLRKEYLOW_RSVD1 0xFF000000
++#define BF_PXP_AS_CLRKEYLOW_RSVD1(v) \
++ (((v) << 24) & BM_PXP_AS_CLRKEYLOW_RSVD1)
++#define BP_PXP_AS_CLRKEYLOW_PIXEL 0
++#define BM_PXP_AS_CLRKEYLOW_PIXEL 0x00FFFFFF
++#define BF_PXP_AS_CLRKEYLOW_PIXEL(v) \
++ (((v) << 0) & BM_PXP_AS_CLRKEYLOW_PIXEL)
++
++#define HW_PXP_AS_CLRKEYHIGH (0x00000190)
++
++#define BP_PXP_AS_CLRKEYHIGH_RSVD1 24
++#define BM_PXP_AS_CLRKEYHIGH_RSVD1 0xFF000000
++#define BF_PXP_AS_CLRKEYHIGH_RSVD1(v) \
++ (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_RSVD1)
++#define BP_PXP_AS_CLRKEYHIGH_PIXEL 0
++#define BM_PXP_AS_CLRKEYHIGH_PIXEL 0x00FFFFFF
++#define BF_PXP_AS_CLRKEYHIGH_PIXEL(v) \
++ (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_PIXEL)
++
++#define HW_PXP_CSC1_COEF0 (0x000001a0)
++
++#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000
++#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000
++#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000
++#define BP_PXP_CSC1_COEF0_C0 18
++#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000
++#define BF_PXP_CSC1_COEF0_C0(v) \
++ (((v) << 18) & BM_PXP_CSC1_COEF0_C0)
++#define BP_PXP_CSC1_COEF0_UV_OFFSET 9
++#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00
++#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \
++ (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET)
++#define BP_PXP_CSC1_COEF0_Y_OFFSET 0
++#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF
++#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \
++ (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET)
++
++#define HW_PXP_CSC1_COEF1 (0x000001b0)
++
++#define BP_PXP_CSC1_COEF1_RSVD1 27
++#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000
++#define BF_PXP_CSC1_COEF1_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1)
++#define BP_PXP_CSC1_COEF1_C1 16
++#define BM_PXP_CSC1_COEF1_C1 0x07FF0000
++#define BF_PXP_CSC1_COEF1_C1(v) \
++ (((v) << 16) & BM_PXP_CSC1_COEF1_C1)
++#define BP_PXP_CSC1_COEF1_RSVD0 11
++#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800
++#define BF_PXP_CSC1_COEF1_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0)
++#define BP_PXP_CSC1_COEF1_C4 0
++#define BM_PXP_CSC1_COEF1_C4 0x000007FF
++#define BF_PXP_CSC1_COEF1_C4(v) \
++ (((v) << 0) & BM_PXP_CSC1_COEF1_C4)
++
++#define HW_PXP_CSC1_COEF2 (0x000001c0)
++
++#define BP_PXP_CSC1_COEF2_RSVD1 27
++#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000
++#define BF_PXP_CSC1_COEF2_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1)
++#define BP_PXP_CSC1_COEF2_C2 16
++#define BM_PXP_CSC1_COEF2_C2 0x07FF0000
++#define BF_PXP_CSC1_COEF2_C2(v) \
++ (((v) << 16) & BM_PXP_CSC1_COEF2_C2)
++#define BP_PXP_CSC1_COEF2_RSVD0 11
++#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800
++#define BF_PXP_CSC1_COEF2_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0)
++#define BP_PXP_CSC1_COEF2_C3 0
++#define BM_PXP_CSC1_COEF2_C3 0x000007FF
++#define BF_PXP_CSC1_COEF2_C3(v) \
++ (((v) << 0) & BM_PXP_CSC1_COEF2_C3)
++
++#define HW_PXP_CSC2_CTRL (0x000001d0)
++
++#define BP_PXP_CSC2_CTRL_RSVD 3
++#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8
++#define BF_PXP_CSC2_CTRL_RSVD(v) \
++ (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD)
++#define BP_PXP_CSC2_CTRL_CSC_MODE 1
++#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006
++#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \
++ (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE)
++#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0
++#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1
++#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2
++#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3
++#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001
++
++#define HW_PXP_CSC2_COEF0 (0x000001e0)
++
++#define BP_PXP_CSC2_COEF0_RSVD1 27
++#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000
++#define BF_PXP_CSC2_COEF0_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1)
++#define BP_PXP_CSC2_COEF0_A2 16
++#define BM_PXP_CSC2_COEF0_A2 0x07FF0000
++#define BF_PXP_CSC2_COEF0_A2(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF0_A2)
++#define BP_PXP_CSC2_COEF0_RSVD0 11
++#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF0_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0)
++#define BP_PXP_CSC2_COEF0_A1 0
++#define BM_PXP_CSC2_COEF0_A1 0x000007FF
++#define BF_PXP_CSC2_COEF0_A1(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF0_A1)
++
++#define HW_PXP_CSC2_COEF1 (0x000001f0)
++
++#define BP_PXP_CSC2_COEF1_RSVD1 27
++#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000
++#define BF_PXP_CSC2_COEF1_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1)
++#define BP_PXP_CSC2_COEF1_B1 16
++#define BM_PXP_CSC2_COEF1_B1 0x07FF0000
++#define BF_PXP_CSC2_COEF1_B1(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF1_B1)
++#define BP_PXP_CSC2_COEF1_RSVD0 11
++#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF1_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0)
++#define BP_PXP_CSC2_COEF1_A3 0
++#define BM_PXP_CSC2_COEF1_A3 0x000007FF
++#define BF_PXP_CSC2_COEF1_A3(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF1_A3)
++
++#define HW_PXP_CSC2_COEF2 (0x00000200)
++
++#define BP_PXP_CSC2_COEF2_RSVD1 27
++#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000
++#define BF_PXP_CSC2_COEF2_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1)
++#define BP_PXP_CSC2_COEF2_B3 16
++#define BM_PXP_CSC2_COEF2_B3 0x07FF0000
++#define BF_PXP_CSC2_COEF2_B3(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF2_B3)
++#define BP_PXP_CSC2_COEF2_RSVD0 11
++#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF2_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0)
++#define BP_PXP_CSC2_COEF2_B2 0
++#define BM_PXP_CSC2_COEF2_B2 0x000007FF
++#define BF_PXP_CSC2_COEF2_B2(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF2_B2)
++
++#define HW_PXP_CSC2_COEF3 (0x00000210)
++
++#define BP_PXP_CSC2_COEF3_RSVD1 27
++#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000
++#define BF_PXP_CSC2_COEF3_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1)
++#define BP_PXP_CSC2_COEF3_C2 16
++#define BM_PXP_CSC2_COEF3_C2 0x07FF0000
++#define BF_PXP_CSC2_COEF3_C2(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF3_C2)
++#define BP_PXP_CSC2_COEF3_RSVD0 11
++#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF3_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0)
++#define BP_PXP_CSC2_COEF3_C1 0
++#define BM_PXP_CSC2_COEF3_C1 0x000007FF
++#define BF_PXP_CSC2_COEF3_C1(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF3_C1)
++
++#define HW_PXP_CSC2_COEF4 (0x00000220)
++
++#define BP_PXP_CSC2_COEF4_RSVD1 25
++#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000
++#define BF_PXP_CSC2_COEF4_RSVD1(v) \
++ (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1)
++#define BP_PXP_CSC2_COEF4_D1 16
++#define BM_PXP_CSC2_COEF4_D1 0x01FF0000
++#define BF_PXP_CSC2_COEF4_D1(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF4_D1)
++#define BP_PXP_CSC2_COEF4_RSVD0 11
++#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF4_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0)
++#define BP_PXP_CSC2_COEF4_C3 0
++#define BM_PXP_CSC2_COEF4_C3 0x000007FF
++#define BF_PXP_CSC2_COEF4_C3(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF4_C3)
++
++#define HW_PXP_CSC2_COEF5 (0x00000230)
++
++#define BP_PXP_CSC2_COEF5_RSVD1 25
++#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000
++#define BF_PXP_CSC2_COEF5_RSVD1(v) \
++ (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1)
++#define BP_PXP_CSC2_COEF5_D3 16
++#define BM_PXP_CSC2_COEF5_D3 0x01FF0000
++#define BF_PXP_CSC2_COEF5_D3(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF5_D3)
++#define BP_PXP_CSC2_COEF5_RSVD0 9
++#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00
++#define BF_PXP_CSC2_COEF5_RSVD0(v) \
++ (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0)
++#define BP_PXP_CSC2_COEF5_D2 0
++#define BM_PXP_CSC2_COEF5_D2 0x000001FF
++#define BF_PXP_CSC2_COEF5_D2(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF5_D2)
++
++#define HW_PXP_LUT_CTRL (0x00000240)
++
++#define BM_PXP_LUT_CTRL_BYPASS 0x80000000
++#define BP_PXP_LUT_CTRL_RSVD3 26
++#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000
++#define BF_PXP_LUT_CTRL_RSVD3(v) \
++ (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3)
++#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24
++#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000
++#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \
++ (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE)
++#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0
++#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1
++#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2
++#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3
++#define BP_PXP_LUT_CTRL_RSVD2 18
++#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000
++#define BF_PXP_LUT_CTRL_RSVD2(v) \
++ (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2)
++#define BP_PXP_LUT_CTRL_OUT_MODE 16
++#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000
++#define BF_PXP_LUT_CTRL_OUT_MODE(v) \
++ (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE)
++#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0
++#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1
++#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2
++#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3
++#define BP_PXP_LUT_CTRL_RSVD1 11
++#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800
++#define BF_PXP_LUT_CTRL_RSVD1(v) \
++ (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1)
++#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400
++#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200
++#define BM_PXP_LUT_CTRL_INVALID 0x00000100
++#define BP_PXP_LUT_CTRL_RSVD0 1
++#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE
++#define BF_PXP_LUT_CTRL_RSVD0(v) \
++ (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0)
++#define BM_PXP_LUT_CTRL_DMA_START 0x00000001
++
++#define HW_PXP_LUT_ADDR (0x00000250)
++
++#define BM_PXP_LUT_ADDR_RSVD2 0x80000000
++#define BP_PXP_LUT_ADDR_NUM_BYTES 16
++#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000
++#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \
++ (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES)
++#define BP_PXP_LUT_ADDR_RSVD1 14
++#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000
++#define BF_PXP_LUT_ADDR_RSVD1(v) \
++ (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1)
++#define BP_PXP_LUT_ADDR_ADDR 0
++#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF
++#define BF_PXP_LUT_ADDR_ADDR(v) \
++ (((v) << 0) & BM_PXP_LUT_ADDR_ADDR)
++
++#define HW_PXP_LUT_DATA (0x00000260)
++
++#define BP_PXP_LUT_DATA_DATA 0
++#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF
++#define BF_PXP_LUT_DATA_DATA(v) (v)
++
++#define HW_PXP_LUT_EXTMEM (0x00000270)
++
++#define BP_PXP_LUT_EXTMEM_ADDR 0
++#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF
++#define BF_PXP_LUT_EXTMEM_ADDR(v) (v)
++
++#define HW_PXP_CFA (0x00000280)
++
++#define BP_PXP_CFA_DATA 0
++#define BM_PXP_CFA_DATA 0xFFFFFFFF
++#define BF_PXP_CFA_DATA(v) (v)
++
++#define HW_PXP_HIST_CTRL (0x00000290)
++
++#define BP_PXP_HIST_CTRL_RSVD 6
++#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0
++#define BF_PXP_HIST_CTRL_RSVD(v) \
++ (((v) << 6) & BM_PXP_HIST_CTRL_RSVD)
++#define BP_PXP_HIST_CTRL_PANEL_MODE 4
++#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030
++#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \
++ (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE)
++#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0
++#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1
++#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2
++#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3
++#define BP_PXP_HIST_CTRL_STATUS 0
++#define BM_PXP_HIST_CTRL_STATUS 0x0000000F
++#define BF_PXP_HIST_CTRL_STATUS(v) \
++ (((v) << 0) & BM_PXP_HIST_CTRL_STATUS)
++
++#define HW_PXP_HIST2_PARAM (0x000002a0)
++
++#define BP_PXP_HIST2_PARAM_RSVD 16
++#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000
++#define BF_PXP_HIST2_PARAM_RSVD(v) \
++ (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD)
++#define BP_PXP_HIST2_PARAM_RSVD1 13
++#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000
++#define BF_PXP_HIST2_PARAM_RSVD1(v) \
++ (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1)
++#define BP_PXP_HIST2_PARAM_VALUE1 8
++#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00
++#define BF_PXP_HIST2_PARAM_VALUE1(v) \
++ (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1)
++#define BP_PXP_HIST2_PARAM_RSVD0 5
++#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0
++#define BF_PXP_HIST2_PARAM_RSVD0(v) \
++ (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0)
++#define BP_PXP_HIST2_PARAM_VALUE0 0
++#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F
++#define BF_PXP_HIST2_PARAM_VALUE0(v) \
++ (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0)
++
++#define HW_PXP_HIST4_PARAM (0x000002b0)
++
++#define BP_PXP_HIST4_PARAM_RSVD3 29
++#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000
++#define BF_PXP_HIST4_PARAM_RSVD3(v) \
++ (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3)
++#define BP_PXP_HIST4_PARAM_VALUE3 24
++#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000
++#define BF_PXP_HIST4_PARAM_VALUE3(v) \
++ (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3)
++#define BP_PXP_HIST4_PARAM_RSVD2 21
++#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000
++#define BF_PXP_HIST4_PARAM_RSVD2(v) \
++ (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2)
++#define BP_PXP_HIST4_PARAM_VALUE2 16
++#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000
++#define BF_PXP_HIST4_PARAM_VALUE2(v) \
++ (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2)
++#define BP_PXP_HIST4_PARAM_RSVD1 13
++#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000
++#define BF_PXP_HIST4_PARAM_RSVD1(v) \
++ (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1)
++#define BP_PXP_HIST4_PARAM_VALUE1 8
++#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00
++#define BF_PXP_HIST4_PARAM_VALUE1(v) \
++ (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1)
++#define BP_PXP_HIST4_PARAM_RSVD0 5
++#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0
++#define BF_PXP_HIST4_PARAM_RSVD0(v) \
++ (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0)
++#define BP_PXP_HIST4_PARAM_VALUE0 0
++#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F
++#define BF_PXP_HIST4_PARAM_VALUE0(v) \
++ (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0)
++
++#define HW_PXP_HIST8_PARAM0 (0x000002c0)
++
++#define BP_PXP_HIST8_PARAM0_RSVD3 29
++#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000
++#define BF_PXP_HIST8_PARAM0_RSVD3(v) \
++ (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3)
++#define BP_PXP_HIST8_PARAM0_VALUE3 24
++#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000
++#define BF_PXP_HIST8_PARAM0_VALUE3(v) \
++ (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3)
++#define BP_PXP_HIST8_PARAM0_RSVD2 21
++#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000
++#define BF_PXP_HIST8_PARAM0_RSVD2(v) \
++ (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2)
++#define BP_PXP_HIST8_PARAM0_VALUE2 16
++#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000
++#define BF_PXP_HIST8_PARAM0_VALUE2(v) \
++ (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2)
++#define BP_PXP_HIST8_PARAM0_RSVD1 13
++#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000
++#define BF_PXP_HIST8_PARAM0_RSVD1(v) \
++ (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1)
++#define BP_PXP_HIST8_PARAM0_VALUE1 8
++#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00
++#define BF_PXP_HIST8_PARAM0_VALUE1(v) \
++ (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1)
++#define BP_PXP_HIST8_PARAM0_RSVD0 5
++#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0
++#define BF_PXP_HIST8_PARAM0_RSVD0(v) \
++ (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0)
++#define BP_PXP_HIST8_PARAM0_VALUE0 0
++#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F
++#define BF_PXP_HIST8_PARAM0_VALUE0(v) \
++ (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0)
++
++#define HW_PXP_HIST8_PARAM1 (0x000002d0)
++
++#define BP_PXP_HIST8_PARAM1_RSVD7 29
++#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000
++#define BF_PXP_HIST8_PARAM1_RSVD7(v) \
++ (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7)
++#define BP_PXP_HIST8_PARAM1_VALUE7 24
++#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000
++#define BF_PXP_HIST8_PARAM1_VALUE7(v) \
++ (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7)
++#define BP_PXP_HIST8_PARAM1_RSVD6 21
++#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000
++#define BF_PXP_HIST8_PARAM1_RSVD6(v) \
++ (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6)
++#define BP_PXP_HIST8_PARAM1_VALUE6 16
++#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000
++#define BF_PXP_HIST8_PARAM1_VALUE6(v) \
++ (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6)
++#define BP_PXP_HIST8_PARAM1_RSVD5 13
++#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000
++#define BF_PXP_HIST8_PARAM1_RSVD5(v) \
++ (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5)
++#define BP_PXP_HIST8_PARAM1_VALUE5 8
++#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00
++#define BF_PXP_HIST8_PARAM1_VALUE5(v) \
++ (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5)
++#define BP_PXP_HIST8_PARAM1_RSVD4 5
++#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0
++#define BF_PXP_HIST8_PARAM1_RSVD4(v) \
++ (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4)
++#define BP_PXP_HIST8_PARAM1_VALUE4 0
++#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F
++#define BF_PXP_HIST8_PARAM1_VALUE4(v) \
++ (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4)
++
++#define HW_PXP_HIST16_PARAM0 (0x000002e0)
++
++#define BP_PXP_HIST16_PARAM0_RSVD3 29
++#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000
++#define BF_PXP_HIST16_PARAM0_RSVD3(v) \
++ (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3)
++#define BP_PXP_HIST16_PARAM0_VALUE3 24
++#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000
++#define BF_PXP_HIST16_PARAM0_VALUE3(v) \
++ (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3)
++#define BP_PXP_HIST16_PARAM0_RSVD2 21
++#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000
++#define BF_PXP_HIST16_PARAM0_RSVD2(v) \
++ (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2)
++#define BP_PXP_HIST16_PARAM0_VALUE2 16
++#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000
++#define BF_PXP_HIST16_PARAM0_VALUE2(v) \
++ (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2)
++#define BP_PXP_HIST16_PARAM0_RSVD1 13
++#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000
++#define BF_PXP_HIST16_PARAM0_RSVD1(v) \
++ (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1)
++#define BP_PXP_HIST16_PARAM0_VALUE1 8
++#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00
++#define BF_PXP_HIST16_PARAM0_VALUE1(v) \
++ (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1)
++#define BP_PXP_HIST16_PARAM0_RSVD0 5
++#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0
++#define BF_PXP_HIST16_PARAM0_RSVD0(v) \
++ (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0)
++#define BP_PXP_HIST16_PARAM0_VALUE0 0
++#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F
++#define BF_PXP_HIST16_PARAM0_VALUE0(v) \
++ (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0)
++
++#define HW_PXP_HIST16_PARAM1 (0x000002f0)
++
++#define BP_PXP_HIST16_PARAM1_RSVD7 29
++#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000
++#define BF_PXP_HIST16_PARAM1_RSVD7(v) \
++ (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7)
++#define BP_PXP_HIST16_PARAM1_VALUE7 24
++#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000
++#define BF_PXP_HIST16_PARAM1_VALUE7(v) \
++ (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7)
++#define BP_PXP_HIST16_PARAM1_RSVD6 21
++#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000
++#define BF_PXP_HIST16_PARAM1_RSVD6(v) \
++ (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6)
++#define BP_PXP_HIST16_PARAM1_VALUE6 16
++#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000
++#define BF_PXP_HIST16_PARAM1_VALUE6(v) \
++ (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6)
++#define BP_PXP_HIST16_PARAM1_RSVD5 13
++#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000
++#define BF_PXP_HIST16_PARAM1_RSVD5(v) \
++ (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5)
++#define BP_PXP_HIST16_PARAM1_VALUE5 8
++#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00
++#define BF_PXP_HIST16_PARAM1_VALUE5(v) \
++ (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5)
++#define BP_PXP_HIST16_PARAM1_RSVD4 5
++#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0
++#define BF_PXP_HIST16_PARAM1_RSVD4(v) \
++ (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4)
++#define BP_PXP_HIST16_PARAM1_VALUE4 0
++#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F
++#define BF_PXP_HIST16_PARAM1_VALUE4(v) \
++ (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4)
++
++#define HW_PXP_HIST16_PARAM2 (0x00000300)
++
++#define BP_PXP_HIST16_PARAM2_RSVD11 29
++#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000
++#define BF_PXP_HIST16_PARAM2_RSVD11(v) \
++ (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11)
++#define BP_PXP_HIST16_PARAM2_VALUE11 24
++#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000
++#define BF_PXP_HIST16_PARAM2_VALUE11(v) \
++ (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11)
++#define BP_PXP_HIST16_PARAM2_RSVD10 21
++#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000
++#define BF_PXP_HIST16_PARAM2_RSVD10(v) \
++ (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10)
++#define BP_PXP_HIST16_PARAM2_VALUE10 16
++#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000
++#define BF_PXP_HIST16_PARAM2_VALUE10(v) \
++ (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10)
++#define BP_PXP_HIST16_PARAM2_RSVD9 13
++#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000
++#define BF_PXP_HIST16_PARAM2_RSVD9(v) \
++ (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9)
++#define BP_PXP_HIST16_PARAM2_VALUE9 8
++#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00
++#define BF_PXP_HIST16_PARAM2_VALUE9(v) \
++ (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9)
++#define BP_PXP_HIST16_PARAM2_RSVD8 5
++#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0
++#define BF_PXP_HIST16_PARAM2_RSVD8(v) \
++ (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8)
++#define BP_PXP_HIST16_PARAM2_VALUE8 0
++#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F
++#define BF_PXP_HIST16_PARAM2_VALUE8(v) \
++ (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8)
++
++#define HW_PXP_HIST16_PARAM3 (0x00000310)
++
++#define BP_PXP_HIST16_PARAM3_RSVD15 29
++#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000
++#define BF_PXP_HIST16_PARAM3_RSVD15(v) \
++ (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15)
++#define BP_PXP_HIST16_PARAM3_VALUE15 24
++#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000
++#define BF_PXP_HIST16_PARAM3_VALUE15(v) \
++ (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15)
++#define BP_PXP_HIST16_PARAM3_RSVD14 21
++#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000
++#define BF_PXP_HIST16_PARAM3_RSVD14(v) \
++ (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14)
++#define BP_PXP_HIST16_PARAM3_VALUE14 16
++#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000
++#define BF_PXP_HIST16_PARAM3_VALUE14(v) \
++ (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14)
++#define BP_PXP_HIST16_PARAM3_RSVD13 13
++#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000
++#define BF_PXP_HIST16_PARAM3_RSVD13(v) \
++ (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13)
++#define BP_PXP_HIST16_PARAM3_VALUE13 8
++#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00
++#define BF_PXP_HIST16_PARAM3_VALUE13(v) \
++ (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13)
++#define BP_PXP_HIST16_PARAM3_RSVD12 5
++#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0
++#define BF_PXP_HIST16_PARAM3_RSVD12(v) \
++ (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12)
++#define BP_PXP_HIST16_PARAM3_VALUE12 0
++#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F
++#define BF_PXP_HIST16_PARAM3_VALUE12(v) \
++ (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12)
++
++#define HW_PXP_POWER (0x00000320)
++
++#define BP_PXP_POWER_CTRL 12
++#define BM_PXP_POWER_CTRL 0xFFFFF000
++#define BF_PXP_POWER_CTRL(v) \
++ (((v) << 12) & BM_PXP_POWER_CTRL)
++#define BP_PXP_POWER_ROT_MEM_LP_STATE 9
++#define BM_PXP_POWER_ROT_MEM_LP_STATE 0x00000E00
++#define BF_PXP_POWER_ROT_MEM_LP_STATE(v) \
++ (((v) << 9) & BM_PXP_POWER_ROT_MEM_LP_STATE)
++#define BV_PXP_POWER_ROT_MEM_LP_STATE__NONE 0x0
++#define BV_PXP_POWER_ROT_MEM_LP_STATE__LS 0x1
++#define BV_PXP_POWER_ROT_MEM_LP_STATE__DS 0x2
++#define BV_PXP_POWER_ROT_MEM_LP_STATE__SD 0x4
++#define BP_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 6
++#define BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 0x000001C0
++#define BF_PXP_POWER_LUT_LP_STATE_WAY1_BANKN(v) \
++ (((v) << 6) & BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN)
++#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__NONE 0x0
++#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__LS 0x1
++#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__DS 0x2
++#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__SD 0x4
++#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 3
++#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 0x00000038
++#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANKN(v) \
++ (((v) << 3) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN)
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__NONE 0x0
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__LS 0x1
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__DS 0x2
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__SD 0x4
++#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0
++#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0x00000007
++#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANK0(v) \
++ (((v) << 0) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0)
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__NONE 0x0
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__LS 0x1
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__DS 0x2
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__SD 0x4
++
++#define HW_PXP_NEXT (0x00000400)
++
++#define BP_PXP_NEXT_POINTER 2
++#define BM_PXP_NEXT_POINTER 0xFFFFFFFC
++#define BF_PXP_NEXT_POINTER(v) \
++ (((v) << 2) & BM_PXP_NEXT_POINTER)
++#define BM_PXP_NEXT_RSVD 0x00000002
++#define BM_PXP_NEXT_ENABLED 0x00000001
++
++#define HW_PXP_DEBUGCTRL (0x00000410)
++
++#define BP_PXP_DEBUGCTRL_RSVD 12
++#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000
++#define BF_PXP_DEBUGCTRL_RSVD(v) \
++ (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD)
++#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8
++#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00
++#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \
++ (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT)
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8
++#define BP_PXP_DEBUGCTRL_SELECT 0
++#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
++#define BF_PXP_DEBUGCTRL_SELECT(v) \
++ (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
++#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0
++#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1
++#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2
++#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3
++#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4
++#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5
++#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6
++#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7
++#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8
++#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14
++
++#define HW_PXP_DEBUG (0x00000420)
++
++#define BP_PXP_DEBUG_DATA 0
++#define BM_PXP_DEBUG_DATA 0xFFFFFFFF
++#define BF_PXP_DEBUG_DATA(v) (v)
++
++#define HW_PXP_VERSION (0x00000430)
++
++#define BP_PXP_VERSION_MAJOR 24
++#define BM_PXP_VERSION_MAJOR 0xFF000000
++#define BF_PXP_VERSION_MAJOR(v) \
++ (((v) << 24) & BM_PXP_VERSION_MAJOR)
++#define BP_PXP_VERSION_MINOR 16
++#define BM_PXP_VERSION_MINOR 0x00FF0000
++#define BF_PXP_VERSION_MINOR(v) \
++ (((v) << 16) & BM_PXP_VERSION_MINOR)
++#define BP_PXP_VERSION_STEP 0
++#define BM_PXP_VERSION_STEP 0x0000FFFF
++#define BF_PXP_VERSION_STEP(v) \
++ (((v) << 0) & BM_PXP_VERSION_STEP)
++#endif /* __ARCH_ARM___PXP_H */
+diff -Nur linux-3.10.30.orig/drivers/extcon/extcon-adc-jack.c linux-linaro-stable-mx6/drivers/extcon/extcon-adc-jack.c
+--- linux-3.10.30.orig/drivers/extcon/extcon-adc-jack.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/extcon/extcon-adc-jack.c 2014-05-15 20:33:46.949934235 +0200
+@@ -87,7 +87,8 @@
+ {
+ struct adc_jack_data *data = _data;
+
+- schedule_delayed_work(&data->handler, data->handling_delay);
++ queue_delayed_work(system_power_efficient_wq,
++ &data->handler, data->handling_delay);
+ return IRQ_HANDLED;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/extcon/extcon-gpio.c linux-linaro-stable-mx6/drivers/extcon/extcon-gpio.c
+--- linux-3.10.30.orig/drivers/extcon/extcon-gpio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/extcon/extcon-gpio.c 2014-05-15 20:33:46.949934235 +0200
+@@ -56,7 +56,7 @@
+ {
+ struct gpio_extcon_data *extcon_data = dev_id;
+
+- schedule_delayed_work(&extcon_data->work,
++ queue_delayed_work(system_power_efficient_wq, &extcon_data->work,
+ extcon_data->debounce_jiffies);
+ return IRQ_HANDLED;
+ }
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_annotate.c linux-linaro-stable-mx6/drivers/gator/gator_annotate.c
+--- linux-3.10.30.orig/drivers/gator/gator_annotate.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_annotate.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,186 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/slab.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <asm/uaccess.h>
++#include <asm/current.h>
++#include <linux/spinlock.h>
++
++static DEFINE_SPINLOCK(annotate_lock);
++static bool collect_annotations = false;
++
++static int annotate_copy(struct file *file, char const __user *buf, size_t count)
++{
++ int cpu = 0;
++ int write = per_cpu(gator_buffer_write, cpu)[ANNOTATE_BUF];
++
++ if (file == NULL) {
++ // copy from kernel
++ memcpy(&per_cpu(gator_buffer, cpu)[ANNOTATE_BUF][write], buf, count);
++ } else {
++ // copy from user space
++ if (copy_from_user(&per_cpu(gator_buffer, cpu)[ANNOTATE_BUF][write], buf, count) != 0)
++ return -1;
++ }
++ per_cpu(gator_buffer_write, cpu)[ANNOTATE_BUF] = (write + count) & gator_buffer_mask[ANNOTATE_BUF];
++
++ return 0;
++}
++
++static ssize_t annotate_write(struct file *file, char const __user *buf, size_t count_orig, loff_t *offset)
++{
++ int pid, cpu, header_size, available, contiguous, length1, length2, size, count = count_orig & 0x7fffffff;
++ bool interrupt_context;
++
++ if (*offset) {
++ return -EINVAL;
++ }
++
++ interrupt_context = in_interrupt();
++ // Annotations are not supported in interrupt context, but may work if you comment out the the next four lines of code.
++ // By doing so, annotations in interrupt context can result in deadlocks and lost data.
++ if (interrupt_context) {
++ printk(KERN_WARNING "gator: Annotations are not supported in interrupt context. Edit gator_annotate.c in the gator driver to enable annotations in interrupt context.\n");
++ return -EINVAL;
++ }
++
++ retry:
++ // synchronize between cores and with collect_annotations
++ spin_lock(&annotate_lock);
++
++ if (!collect_annotations) {
++ // Not collecting annotations, tell the caller everything was written
++ size = count_orig;
++ goto annotate_write_out;
++ }
++
++ // Annotation only uses a single per-cpu buffer as the data must be in order to the engine
++ cpu = 0;
++
++ if (current == NULL) {
++ pid = 0;
++ } else {
++ pid = current->pid;
++ }
++
++ // determine total size of the payload
++ header_size = MAXSIZE_PACK32 * 3 + MAXSIZE_PACK64;
++ available = buffer_bytes_available(cpu, ANNOTATE_BUF) - header_size;
++ size = count < available ? count : available;
++
++ if (size <= 0) {
++ // Buffer is full, wait until space is available
++ spin_unlock(&annotate_lock);
++
++ // Drop the annotation as blocking is not allowed in interrupt context
++ if (interrupt_context) {
++ return -EINVAL;
++ }
++
++ wait_event_interruptible(gator_annotate_wait, buffer_bytes_available(cpu, ANNOTATE_BUF) > header_size || !collect_annotations);
++
++ // Check to see if a signal is pending
++ if (signal_pending(current)) {
++ return -EINTR;
++ }
++
++ goto retry;
++ }
++
++ // synchronize shared variables annotateBuf and annotatePos
++ if (per_cpu(gator_buffer, cpu)[ANNOTATE_BUF]) {
++ u64 time = gator_get_time();
++ gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, get_physical_cpu());
++ gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, pid);
++ gator_buffer_write_packed_int64(cpu, ANNOTATE_BUF, time);
++ gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, size);
++
++ // determine the sizes to capture, length1 + length2 will equal size
++ contiguous = contiguous_space_available(cpu, ANNOTATE_BUF);
++ if (size < contiguous) {
++ length1 = size;
++ length2 = 0;
++ } else {
++ length1 = contiguous;
++ length2 = size - contiguous;
++ }
++
++ if (annotate_copy(file, buf, length1) != 0) {
++ size = -EINVAL;
++ goto annotate_write_out;
++ }
++
++ if (length2 > 0 && annotate_copy(file, &buf[length1], length2) != 0) {
++ size = -EINVAL;
++ goto annotate_write_out;
++ }
++
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, ANNOTATE_BUF, time);
++ }
++
++annotate_write_out:
++ spin_unlock(&annotate_lock);
++
++ // return the number of bytes written
++ return size;
++}
++
++#include "gator_annotate_kernel.c"
++
++static int annotate_release(struct inode *inode, struct file *file)
++{
++ int cpu = 0;
++
++ // synchronize between cores
++ spin_lock(&annotate_lock);
++
++ if (per_cpu(gator_buffer, cpu)[ANNOTATE_BUF] && buffer_check_space(cpu, ANNOTATE_BUF, MAXSIZE_PACK64 + 3 * MAXSIZE_PACK32)) {
++ uint32_t pid = current->pid;
++ gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, get_physical_cpu());
++ gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, pid);
++ gator_buffer_write_packed_int64(cpu, ANNOTATE_BUF, 0); // time
++ gator_buffer_write_packed_int(cpu, ANNOTATE_BUF, 0); // size
++ }
++
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, ANNOTATE_BUF, gator_get_time());
++
++ spin_unlock(&annotate_lock);
++
++ return 0;
++}
++
++static const struct file_operations annotate_fops = {
++ .write = annotate_write,
++ .release = annotate_release
++};
++
++static int gator_annotate_create_files(struct super_block *sb, struct dentry *root)
++{
++ return gatorfs_create_file_perm(sb, root, "annotate", &annotate_fops, 0666);
++}
++
++static int gator_annotate_start(void)
++{
++ collect_annotations = true;
++ return 0;
++}
++
++static void gator_annotate_stop(void)
++{
++ // the spinlock here will ensure that when this function exits, we are not in the middle of an annotation
++ spin_lock(&annotate_lock);
++ collect_annotations = false;
++ wake_up(&gator_annotate_wait);
++ spin_unlock(&annotate_lock);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_annotate_kernel.c linux-linaro-stable-mx6/drivers/gator/gator_annotate_kernel.c
+--- linux-3.10.30.orig/drivers/gator/gator_annotate_kernel.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_annotate_kernel.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,200 @@
++/**
++ * Copyright (C) ARM Limited 2012-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#define ESCAPE_CODE 0x1c
++#define STRING_ANNOTATION 0x06
++#define NAME_CHANNEL_ANNOTATION 0x07
++#define NAME_GROUP_ANNOTATION 0x08
++#define VISUAL_ANNOTATION 0x04
++#define MARKER_ANNOTATION 0x05
++
++static void kannotate_write(const char *ptr, unsigned int size)
++{
++ int retval;
++ int pos = 0;
++ loff_t offset = 0;
++ while (pos < size) {
++ retval = annotate_write(NULL, &ptr[pos], size - pos, &offset);
++ if (retval < 0) {
++ printk(KERN_WARNING "gator: kannotate_write failed with return value %d\n", retval);
++ return;
++ }
++ pos += retval;
++ }
++}
++
++static void marshal_u16(char *buf, u16 val) {
++ buf[0] = val & 0xff;
++ buf[1] = (val >> 8) & 0xff;
++}
++
++static void marshal_u32(char *buf, u32 val) {
++ buf[0] = val & 0xff;
++ buf[1] = (val >> 8) & 0xff;
++ buf[2] = (val >> 16) & 0xff;
++ buf[3] = (val >> 24) & 0xff;
++}
++
++void gator_annotate_channel(int channel, const char *str)
++{
++ const u16 str_size = strlen(str) & 0xffff;
++ char header[8];
++ header[0] = ESCAPE_CODE;
++ header[1] = STRING_ANNOTATION;
++ marshal_u32(header + 2, channel);
++ marshal_u16(header + 6, str_size);
++ kannotate_write(header, sizeof(header));
++ kannotate_write(str, str_size);
++}
++
++EXPORT_SYMBOL(gator_annotate_channel);
++
++void gator_annotate(const char *str)
++{
++ gator_annotate_channel(0, str);
++}
++
++EXPORT_SYMBOL(gator_annotate);
++
++void gator_annotate_channel_color(int channel, int color, const char *str)
++{
++ const u16 str_size = (strlen(str) + 4) & 0xffff;
++ char header[12];
++ header[0] = ESCAPE_CODE;
++ header[1] = STRING_ANNOTATION;
++ marshal_u32(header + 2, channel);
++ marshal_u16(header + 6, str_size);
++ marshal_u32(header + 8, color);
++ kannotate_write(header, sizeof(header));
++ kannotate_write(str, str_size - 4);
++}
++
++EXPORT_SYMBOL(gator_annotate_channel_color);
++
++void gator_annotate_color(int color, const char *str)
++{
++ gator_annotate_channel_color(0, color, str);
++}
++
++EXPORT_SYMBOL(gator_annotate_color);
++
++void gator_annotate_channel_end(int channel)
++{
++ char header[8];
++ header[0] = ESCAPE_CODE;
++ header[1] = STRING_ANNOTATION;
++ marshal_u32(header + 2, channel);
++ marshal_u16(header + 6, 0);
++ kannotate_write(header, sizeof(header));
++}
++
++EXPORT_SYMBOL(gator_annotate_channel_end);
++
++void gator_annotate_end(void)
++{
++ gator_annotate_channel_end(0);
++}
++
++EXPORT_SYMBOL(gator_annotate_end);
++
++void gator_annotate_name_channel(int channel, int group, const char* str)
++{
++ const u16 str_size = strlen(str) & 0xffff;
++ char header[12];
++ header[0] = ESCAPE_CODE;
++ header[1] = NAME_CHANNEL_ANNOTATION;
++ marshal_u32(header + 2, channel);
++ marshal_u32(header + 6, group);
++ marshal_u16(header + 10, str_size);
++ kannotate_write(header, sizeof(header));
++ kannotate_write(str, str_size);
++}
++
++EXPORT_SYMBOL(gator_annotate_name_channel);
++
++void gator_annotate_name_group(int group, const char* str)
++{
++ const u16 str_size = strlen(str) & 0xffff;
++ char header[8];
++ header[0] = ESCAPE_CODE;
++ header[1] = NAME_GROUP_ANNOTATION;
++ marshal_u32(header + 2, group);
++ marshal_u16(header + 6, str_size);
++ kannotate_write(header, sizeof(header));
++ kannotate_write(str, str_size);
++}
++
++EXPORT_SYMBOL(gator_annotate_name_group);
++
++void gator_annotate_visual(const char *data, unsigned int length, const char *str)
++{
++ const u16 str_size = strlen(str) & 0xffff;
++ char header[4];
++ char header_length[4];
++ header[0] = ESCAPE_CODE;
++ header[1] = VISUAL_ANNOTATION;
++ marshal_u16(header + 2, str_size);
++ marshal_u32(header_length, length);
++ kannotate_write(header, sizeof(header));
++ kannotate_write(str, str_size);
++ kannotate_write(header_length, sizeof(header_length));
++ kannotate_write(data, length);
++}
++
++EXPORT_SYMBOL(gator_annotate_visual);
++
++void gator_annotate_marker(void)
++{
++ char header[4];
++ header[0] = ESCAPE_CODE;
++ header[1] = MARKER_ANNOTATION;
++ marshal_u16(header + 2, 0);
++ kannotate_write(header, sizeof(header));
++}
++
++EXPORT_SYMBOL(gator_annotate_marker);
++
++void gator_annotate_marker_str(const char *str)
++{
++ const u16 str_size = strlen(str) & 0xffff;
++ char header[4];
++ header[0] = ESCAPE_CODE;
++ header[1] = MARKER_ANNOTATION;
++ marshal_u16(header + 2, str_size);
++ kannotate_write(header, sizeof(header));
++ kannotate_write(str, str_size);
++}
++
++EXPORT_SYMBOL(gator_annotate_marker_str);
++
++void gator_annotate_marker_color(int color)
++{
++ char header[8];
++ header[0] = ESCAPE_CODE;
++ header[1] = MARKER_ANNOTATION;
++ marshal_u16(header + 2, 4);
++ marshal_u32(header + 4, color);
++ kannotate_write(header, sizeof(header));
++}
++
++EXPORT_SYMBOL(gator_annotate_marker_color);
++
++void gator_annotate_marker_color_str(int color, const char *str)
++{
++ const u16 str_size = (strlen(str) + 4) & 0xffff;
++ char header[8];
++ header[0] = ESCAPE_CODE;
++ header[1] = MARKER_ANNOTATION;
++ marshal_u16(header + 2, str_size);
++ marshal_u32(header + 4, color);
++ kannotate_write(header, sizeof(header));
++ kannotate_write(str, str_size - 4);
++}
++
++EXPORT_SYMBOL(gator_annotate_marker_color_str);
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_backtrace.c linux-linaro-stable-mx6/drivers/gator/gator_backtrace.c
+--- linux-3.10.30.orig/drivers/gator/gator_backtrace.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_backtrace.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,168 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++/*
++ * EABI backtrace stores {fp,lr} on the stack.
++ */
++struct stack_frame_eabi {
++ union {
++ struct {
++ unsigned long fp;
++ // May be the fp in the case of a leaf function or clang
++ unsigned long lr;
++ // If lr is really the fp, lr2 is the corresponding lr
++ unsigned long lr2;
++ };
++ // Used to read 32 bit fp/lr from a 64 bit kernel
++ struct {
++ u32 fp_32;
++ // same as lr above
++ u32 lr_32;
++ // same as lr2 above
++ u32 lr2_32;
++ };
++ };
++};
++
++static void arm_backtrace_eabi(int cpu, struct pt_regs *const regs, unsigned int depth)
++{
++#if defined(__arm__) || defined(__aarch64__)
++ struct stack_frame_eabi *curr;
++ struct stack_frame_eabi bufcurr;
++#if defined(__arm__)
++ const bool is_compat = false;
++ unsigned long fp = regs->ARM_fp;
++ unsigned long sp = regs->ARM_sp;
++ unsigned long lr = regs->ARM_lr;
++ const int gcc_frame_offset = sizeof(unsigned long);
++#else
++ // Is userspace aarch32 (32 bit)
++ const bool is_compat = compat_user_mode(regs);
++ unsigned long fp = (is_compat ? regs->regs[11] : regs->regs[29]);
++ unsigned long sp = (is_compat ? regs->compat_sp : regs->sp);
++ unsigned long lr = (is_compat ? regs->compat_lr : regs->regs[30]);
++ const int gcc_frame_offset = (is_compat ? sizeof(u32) : 0);
++#endif
++ // clang frame offset is always zero
++ int is_user_mode = user_mode(regs);
++
++ // pc (current function) has already been added
++
++ if (!is_user_mode) {
++ return;
++ }
++
++ // Add the lr (parent function)
++ // entry preamble may not have executed
++ gator_add_trace(cpu, lr);
++
++ // check fp is valid
++ if (fp == 0 || fp < sp) {
++ return;
++ }
++
++ // Get the current stack frame
++ curr = (struct stack_frame_eabi *)(fp - gcc_frame_offset);
++ if ((unsigned long)curr & 3) {
++ return;
++ }
++
++ while (depth-- && curr) {
++ if (!access_ok(VERIFY_READ, curr, sizeof(struct stack_frame_eabi)) ||
++ __copy_from_user_inatomic(&bufcurr, curr, sizeof(struct stack_frame_eabi))) {
++ return;
++ }
++
++ fp = (is_compat ? bufcurr.fp_32 : bufcurr.fp);
++ lr = (is_compat ? bufcurr.lr_32 : bufcurr.lr);
++
++#define calc_next(reg) ((reg) - gcc_frame_offset)
++ // Returns true if reg is a valid fp
++#define validate_next(reg, curr) \
++ ((reg) != 0 && (calc_next(reg) & 3) == 0 && (unsigned long)(curr) < calc_next(reg))
++
++ // Try lr from the stack as the fp because gcc leaf functions do not push lr
++ // If gcc_frame_offset is non-zero, the lr will also be the clang fp
++ // This assumes code is at a lower address than the stack
++ if (validate_next(lr, curr)) {
++ fp = lr;
++ lr = (is_compat ? bufcurr.lr2_32 : bufcurr.lr2);
++ }
++
++ gator_add_trace(cpu, lr);
++
++ if (!validate_next(fp, curr)) {
++ return;
++ }
++
++ // Move to the next stack frame
++ curr = (struct stack_frame_eabi *)calc_next(fp);
++ }
++#endif
++}
++
++#if defined(__arm__) || defined(__aarch64__)
++static int report_trace(struct stackframe *frame, void *d)
++{
++ unsigned int *depth = d, cookie = NO_COOKIE;
++ unsigned long addr = frame->pc;
++
++ if (*depth) {
++#if defined(MODULE)
++ unsigned int cpu = get_physical_cpu();
++ struct module *mod = __module_address(addr);
++ if (mod) {
++ cookie = get_cookie(cpu, current, mod->name, false);
++ addr = addr - (unsigned long)mod->module_core;
++ }
++#endif
++ marshal_backtrace(addr & ~1, cookie);
++ (*depth)--;
++ }
++
++ return *depth == 0;
++}
++#endif
++
++// Uncomment the following line to enable kernel stack unwinding within gator, note it can also be defined from the Makefile
++// #define GATOR_KERNEL_STACK_UNWINDING
++
++#if (defined(__arm__) || defined(__aarch64__)) && !defined(GATOR_KERNEL_STACK_UNWINDING)
++// Disabled by default
++MODULE_PARM_DESC(kernel_stack_unwinding, "Allow kernel stack unwinding.");
++bool kernel_stack_unwinding = 0;
++module_param(kernel_stack_unwinding, bool, 0644);
++#endif
++
++static void kernel_backtrace(int cpu, struct pt_regs *const regs)
++{
++#if defined(__arm__) || defined(__aarch64__)
++#ifdef GATOR_KERNEL_STACK_UNWINDING
++ int depth = gator_backtrace_depth;
++#else
++ int depth = (kernel_stack_unwinding ? gator_backtrace_depth : 1);
++#endif
++ struct stackframe frame;
++ if (depth == 0)
++ depth = 1;
++#if defined(__arm__)
++ frame.fp = regs->ARM_fp;
++ frame.sp = regs->ARM_sp;
++ frame.lr = regs->ARM_lr;
++ frame.pc = regs->ARM_pc;
++#else
++ frame.fp = regs->regs[29];
++ frame.sp = regs->sp;
++ frame.pc = regs->pc;
++#endif
++ walk_stackframe(&frame, report_trace, &depth);
++#else
++ marshal_backtrace(PC_REG & ~1, NO_COOKIE);
++#endif
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_cookies.c linux-linaro-stable-mx6/drivers/gator/gator_cookies.c
+--- linux-3.10.30.orig/drivers/gator/gator_cookies.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_cookies.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,433 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#define COOKIEMAP_ENTRIES 1024 /* must be power of 2 */
++#define TRANSLATE_BUFFER_SIZE 512 // must be a power of 2 - 512/4 = 128 entries
++#define TRANSLATE_TEXT_SIZE 256
++#define MAX_COLLISIONS 2
++
++static uint32_t *gator_crc32_table;
++static unsigned int translate_buffer_mask;
++
++struct cookie_args {
++ struct task_struct *task;
++ const char *text;
++};
++
++static DEFINE_PER_CPU(char *, translate_text);
++static DEFINE_PER_CPU(uint32_t, cookie_next_key);
++static DEFINE_PER_CPU(uint64_t *, cookie_keys);
++static DEFINE_PER_CPU(uint32_t *, cookie_values);
++static DEFINE_PER_CPU(int, translate_buffer_read);
++static DEFINE_PER_CPU(int, translate_buffer_write);
++static DEFINE_PER_CPU(struct cookie_args *, translate_buffer);
++
++static uint32_t get_cookie(int cpu, struct task_struct *task, const char *text, bool from_wq);
++static void wq_cookie_handler(struct work_struct *unused);
++DECLARE_WORK(cookie_work, wq_cookie_handler);
++static struct timer_list app_process_wake_up_timer;
++static void app_process_wake_up_handler(unsigned long unused_data);
++
++static uint32_t cookiemap_code(uint64_t value64)
++{
++ uint32_t value = (uint32_t)((value64 >> 32) + value64);
++ uint32_t cookiecode = (value >> 24) & 0xff;
++ cookiecode = cookiecode * 31 + ((value >> 16) & 0xff);
++ cookiecode = cookiecode * 31 + ((value >> 8) & 0xff);
++ cookiecode = cookiecode * 31 + ((value >> 0) & 0xff);
++ cookiecode &= (COOKIEMAP_ENTRIES - 1);
++ return cookiecode * MAX_COLLISIONS;
++}
++
++static uint32_t gator_chksum_crc32(const char *data)
++{
++ register unsigned long crc;
++ const unsigned char *block = data;
++ int i, length = strlen(data);
++
++ crc = 0xFFFFFFFF;
++ for (i = 0; i < length; i++) {
++ crc = ((crc >> 8) & 0x00FFFFFF) ^ gator_crc32_table[(crc ^ *block++) & 0xFF];
++ }
++
++ return (crc ^ 0xFFFFFFFF);
++}
++
++/*
++ * Exists
++ * Pre: [0][1][v][3]..[n-1]
++ * Post: [v][0][1][3]..[n-1]
++ */
++static uint32_t cookiemap_exists(uint64_t key)
++{
++ unsigned long x, flags, retval = 0;
++ int cpu = get_physical_cpu();
++ uint32_t cookiecode = cookiemap_code(key);
++ uint64_t *keys = &(per_cpu(cookie_keys, cpu)[cookiecode]);
++ uint32_t *values = &(per_cpu(cookie_values, cpu)[cookiecode]);
++
++ // Can be called from interrupt handler or from work queue
++ local_irq_save(flags);
++ for (x = 0; x < MAX_COLLISIONS; x++) {
++ if (keys[x] == key) {
++ uint32_t value = values[x];
++ for (; x > 0; x--) {
++ keys[x] = keys[x - 1];
++ values[x] = values[x - 1];
++ }
++ keys[0] = key;
++ values[0] = value;
++ retval = value;
++ break;
++ }
++ }
++ local_irq_restore(flags);
++
++ return retval;
++}
++
++/*
++ * Add
++ * Pre: [0][1][2][3]..[n-1]
++ * Post: [v][0][1][2]..[n-2]
++ */
++static void cookiemap_add(uint64_t key, uint32_t value)
++{
++ int cpu = get_physical_cpu();
++ int cookiecode = cookiemap_code(key);
++ uint64_t *keys = &(per_cpu(cookie_keys, cpu)[cookiecode]);
++ uint32_t *values = &(per_cpu(cookie_values, cpu)[cookiecode]);
++ int x;
++
++ for (x = MAX_COLLISIONS - 1; x > 0; x--) {
++ keys[x] = keys[x - 1];
++ values[x] = values[x - 1];
++ }
++ keys[0] = key;
++ values[0] = value;
++}
++
++#ifndef CONFIG_PREEMPT_RT_FULL
++static void translate_buffer_write_args(int cpu, struct task_struct *task, const char *text)
++{
++ unsigned long flags;
++ int write;
++ int next_write;
++ struct cookie_args *args;
++
++ local_irq_save(flags);
++
++ write = per_cpu(translate_buffer_write, cpu);
++ next_write = (write + 1) & translate_buffer_mask;
++
++ // At least one entry must always remain available as when read == write, the queue is empty not full
++ if (next_write != per_cpu(translate_buffer_read, cpu)) {
++ args = &per_cpu(translate_buffer, cpu)[write];
++ args->task = task;
++ args->text = text;
++ get_task_struct(task);
++ per_cpu(translate_buffer_write, cpu) = next_write;
++ }
++
++ local_irq_restore(flags);
++}
++#endif
++
++static void translate_buffer_read_args(int cpu, struct cookie_args *args)
++{
++ unsigned long flags;
++ int read;
++
++ local_irq_save(flags);
++
++ read = per_cpu(translate_buffer_read, cpu);
++ *args = per_cpu(translate_buffer, cpu)[read];
++ per_cpu(translate_buffer_read, cpu) = (read + 1) & translate_buffer_mask;
++
++ local_irq_restore(flags);
++}
++
++static void wq_cookie_handler(struct work_struct *unused)
++{
++ struct cookie_args args;
++ int cpu = get_physical_cpu(), cookie;
++
++ mutex_lock(&start_mutex);
++
++ if (gator_started != 0) {
++ while (per_cpu(translate_buffer_read, cpu) != per_cpu(translate_buffer_write, cpu)) {
++ translate_buffer_read_args(cpu, &args);
++ cookie = get_cookie(cpu, args.task, args.text, true);
++ marshal_link(cookie, args.task->tgid, args.task->pid);
++ put_task_struct(args.task);
++ }
++ }
++
++ mutex_unlock(&start_mutex);
++}
++
++static void app_process_wake_up_handler(unsigned long unused_data)
++{
++ // had to delay scheduling work as attempting to schedule work during the context switch is illegal in kernel versions 3.5 and greater
++ schedule_work(&cookie_work);
++}
++
++// Retrieve full name from proc/pid/cmdline for java processes on Android
++static int translate_app_process(const char **text, int cpu, struct task_struct *task, bool from_wq)
++{
++ void *maddr;
++ unsigned int len;
++ unsigned long addr;
++ struct mm_struct *mm;
++ struct page *page = NULL;
++ struct vm_area_struct *page_vma;
++ int bytes, offset, retval = 0;
++ char *buf = per_cpu(translate_text, cpu);
++
++#ifndef CONFIG_PREEMPT_RT_FULL
++ // Push work into a work queue if in atomic context as the kernel functions below might sleep
++ // Rely on the in_interrupt variable rather than in_irq() or in_interrupt() kernel functions, as the value of these functions seems
++ // inconsistent during a context switch between android/linux versions
++ if (!from_wq) {
++ // Check if already in buffer
++ int pos = per_cpu(translate_buffer_read, cpu);
++ while (pos != per_cpu(translate_buffer_write, cpu)) {
++ if (per_cpu(translate_buffer, cpu)[pos].task == task)
++ goto out;
++ pos = (pos + 1) & translate_buffer_mask;
++ }
++
++ translate_buffer_write_args(cpu, task, *text);
++
++ // Not safe to call in RT-Preempt full in schedule switch context
++ mod_timer(&app_process_wake_up_timer, jiffies + 1);
++ goto out;
++ }
++#endif
++
++ mm = get_task_mm(task);
++ if (!mm)
++ goto out;
++ if (!mm->arg_end)
++ goto outmm;
++ addr = mm->arg_start;
++ len = mm->arg_end - mm->arg_start;
++
++ if (len > TRANSLATE_TEXT_SIZE)
++ len = TRANSLATE_TEXT_SIZE;
++
++ down_read(&mm->mmap_sem);
++ while (len) {
++ if (get_user_pages(task, mm, addr, 1, 0, 1, &page, &page_vma) <= 0)
++ goto outsem;
++
++ maddr = kmap(page);
++ offset = addr & (PAGE_SIZE - 1);
++ bytes = len;
++ if (bytes > PAGE_SIZE - offset)
++ bytes = PAGE_SIZE - offset;
++
++ copy_from_user_page(page_vma, page, addr, buf, maddr + offset, bytes);
++
++ kunmap(page); // release page allocated by get_user_pages()
++ page_cache_release(page);
++
++ len -= bytes;
++ buf += bytes;
++ addr += bytes;
++
++ *text = per_cpu(translate_text, cpu);
++ retval = 1;
++ }
++
++ // On app_process startup, /proc/pid/cmdline is initially "zygote" then "<pre-initialized>" but changes after an initial startup period
++ if (strcmp(*text, "zygote") == 0 || strcmp(*text, "<pre-initialized>") == 0)
++ retval = 0;
++
++outsem:
++ up_read(&mm->mmap_sem);
++outmm:
++ mmput(mm);
++out:
++ return retval;
++}
++
++static uint32_t get_cookie(int cpu, struct task_struct *task, const char *text, bool from_wq)
++{
++ unsigned long flags, cookie;
++ uint64_t key;
++
++ key = gator_chksum_crc32(text);
++ key = (key << 32) | (uint32_t)task->tgid;
++
++ cookie = cookiemap_exists(key);
++ if (cookie) {
++ return cookie;
++ }
++
++ if (strcmp(text, "app_process") == 0) {
++ if (!translate_app_process(&text, cpu, task, from_wq))
++ return UNRESOLVED_COOKIE;
++ }
++
++ // Can be called from interrupt handler or from work queue or from scheduler trace
++ local_irq_save(flags);
++
++ cookie = UNRESOLVED_COOKIE;
++ if (marshal_cookie_header(text)) {
++ cookie = per_cpu(cookie_next_key, cpu) += nr_cpu_ids;
++ cookiemap_add(key, cookie);
++ marshal_cookie(cookie, text);
++ }
++
++ local_irq_restore(flags);
++
++ return cookie;
++}
++
++static int get_exec_cookie(int cpu, struct task_struct *task)
++{
++ struct mm_struct *mm = task->mm;
++ const char *text;
++
++ // kernel threads have no address space
++ if (!mm)
++ return NO_COOKIE;
++
++ if (task && task->mm && task->mm->exe_file) {
++ text = task->mm->exe_file->f_path.dentry->d_name.name;
++ return get_cookie(cpu, task, text, false);
++ }
++
++ return UNRESOLVED_COOKIE;
++}
++
++static unsigned long get_address_cookie(int cpu, struct task_struct *task, unsigned long addr, off_t *offset)
++{
++ unsigned long cookie = NO_COOKIE;
++ struct mm_struct *mm = task->mm;
++ struct vm_area_struct *vma;
++ const char *text;
++
++ if (!mm)
++ return cookie;
++
++ for (vma = find_vma(mm, addr); vma; vma = vma->vm_next) {
++ if (addr < vma->vm_start || addr >= vma->vm_end)
++ continue;
++
++ if (vma->vm_file) {
++ text = vma->vm_file->f_path.dentry->d_name.name;
++ cookie = get_cookie(cpu, task, text, false);
++ *offset = (vma->vm_pgoff << PAGE_SHIFT) + addr - vma->vm_start;
++ } else {
++ /* must be an anonymous map */
++ *offset = addr;
++ }
++
++ break;
++ }
++
++ if (!vma)
++ cookie = UNRESOLVED_COOKIE;
++
++ return cookie;
++}
++
++static int cookies_initialize(void)
++{
++ uint32_t crc, poly;
++ int i, j, cpu, size, err = 0;
++
++ translate_buffer_mask = TRANSLATE_BUFFER_SIZE / sizeof(per_cpu(translate_buffer, 0)[0]) - 1;
++
++ for_each_present_cpu(cpu) {
++ per_cpu(cookie_next_key, cpu) = nr_cpu_ids + cpu;
++
++ size = COOKIEMAP_ENTRIES * MAX_COLLISIONS * sizeof(uint64_t);
++ per_cpu(cookie_keys, cpu) = (uint64_t *)kmalloc(size, GFP_KERNEL);
++ if (!per_cpu(cookie_keys, cpu)) {
++ err = -ENOMEM;
++ goto cookie_setup_error;
++ }
++ memset(per_cpu(cookie_keys, cpu), 0, size);
++
++ size = COOKIEMAP_ENTRIES * MAX_COLLISIONS * sizeof(uint32_t);
++ per_cpu(cookie_values, cpu) = (uint32_t *)kmalloc(size, GFP_KERNEL);
++ if (!per_cpu(cookie_values, cpu)) {
++ err = -ENOMEM;
++ goto cookie_setup_error;
++ }
++ memset(per_cpu(cookie_values, cpu), 0, size);
++
++ per_cpu(translate_buffer, cpu) = (struct cookie_args *)kmalloc(TRANSLATE_BUFFER_SIZE, GFP_KERNEL);
++ if (!per_cpu(translate_buffer, cpu)) {
++ err = -ENOMEM;
++ goto cookie_setup_error;
++ }
++
++ per_cpu(translate_buffer_write, cpu) = 0;
++ per_cpu(translate_buffer_read, cpu) = 0;
++
++ per_cpu(translate_text, cpu) = (char *)kmalloc(TRANSLATE_TEXT_SIZE, GFP_KERNEL);
++ if (!per_cpu(translate_text, cpu)) {
++ err = -ENOMEM;
++ goto cookie_setup_error;
++ }
++ }
++
++ // build CRC32 table
++ poly = 0x04c11db7;
++ gator_crc32_table = (uint32_t *)kmalloc(256 * sizeof(uint32_t), GFP_KERNEL);
++ if (!gator_crc32_table) {
++ err = -ENOMEM;
++ goto cookie_setup_error;
++ }
++ for (i = 0; i < 256; i++) {
++ crc = i;
++ for (j = 8; j > 0; j--) {
++ if (crc & 1) {
++ crc = (crc >> 1) ^ poly;
++ } else {
++ crc >>= 1;
++ }
++ }
++ gator_crc32_table[i] = crc;
++ }
++
++ setup_timer(&app_process_wake_up_timer, app_process_wake_up_handler, 0);
++
++cookie_setup_error:
++ return err;
++}
++
++static void cookies_release(void)
++{
++ int cpu;
++
++ for_each_present_cpu(cpu) {
++ kfree(per_cpu(cookie_keys, cpu));
++ per_cpu(cookie_keys, cpu) = NULL;
++
++ kfree(per_cpu(cookie_values, cpu));
++ per_cpu(cookie_values, cpu) = NULL;
++
++ kfree(per_cpu(translate_buffer, cpu));
++ per_cpu(translate_buffer, cpu) = NULL;
++ per_cpu(translate_buffer_read, cpu) = 0;
++ per_cpu(translate_buffer_write, cpu) = 0;
++
++ kfree(per_cpu(translate_text, cpu));
++ per_cpu(translate_text, cpu) = NULL;
++ }
++
++ del_timer_sync(&app_process_wake_up_timer);
++ kfree(gator_crc32_table);
++ gator_crc32_table = NULL;
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_armv6.c linux-linaro-stable-mx6/drivers/gator/gator_events_armv6.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_armv6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_armv6.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,237 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "gator.h"
++
++// gator_events_perf_pmu.c is used if perf is supported
++#if GATOR_NO_PERF_SUPPORT
++
++static const char *pmnc_name;
++
++/*
++ * Per-CPU PMCR
++ */
++#define PMCR_E (1 << 0) /* Enable */
++#define PMCR_P (1 << 1) /* Count reset */
++#define PMCR_C (1 << 2) /* Cycle counter reset */
++#define PMCR_OFL_PMN0 (1 << 8) /* Count reg 0 overflow */
++#define PMCR_OFL_PMN1 (1 << 9) /* Count reg 1 overflow */
++#define PMCR_OFL_CCNT (1 << 10) /* Cycle counter overflow */
++
++#define PMN0 0
++#define PMN1 1
++#define CCNT 2
++#define CNTMAX (CCNT+1)
++
++static int pmnc_counters = 0;
++static unsigned long pmnc_enabled[CNTMAX];
++static unsigned long pmnc_event[CNTMAX];
++static unsigned long pmnc_key[CNTMAX];
++
++static DEFINE_PER_CPU(int[CNTMAX * 2], perfCnt);
++
++static inline void armv6_pmnc_write(u32 val)
++{
++ /* upper 4bits and 7, 11 are write-as-0 */
++ val &= 0x0ffff77f;
++ asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r" (val));
++}
++
++static inline u32 armv6_pmnc_read(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r" (val));
++ return val;
++}
++
++static void armv6_pmnc_reset_counter(unsigned int cnt)
++{
++ u32 val = 0;
++ switch (cnt) {
++ case CCNT:
++ asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r" (val));
++ break;
++ case PMN0:
++ asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r" (val));
++ break;
++ case PMN1:
++ asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r" (val));
++ break;
++ }
++}
++
++int gator_events_armv6_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++ int i;
++
++ pmnc_counters = 3;
++
++ for (i = PMN0; i <= CCNT; i++) {
++ char buf[40];
++ if (i == CCNT) {
++ snprintf(buf, sizeof buf, "ARM_%s_ccnt", pmnc_name);
++ } else {
++ snprintf(buf, sizeof buf, "ARM_%s_cnt%d", pmnc_name, i);
++ }
++ dir = gatorfs_mkdir(sb, root, buf);
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &pmnc_enabled[i]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &pmnc_key[i]);
++ if (i != CCNT) {
++ gatorfs_create_ulong(sb, dir, "event", &pmnc_event[i]);
++ }
++ }
++
++ return 0;
++}
++
++static int gator_events_armv6_online(int **buffer, bool migrate)
++{
++ unsigned int cnt, len = 0, cpu = smp_processor_id();
++ u32 pmnc;
++
++ if (armv6_pmnc_read() & PMCR_E) {
++ armv6_pmnc_write(armv6_pmnc_read() & ~PMCR_E);
++ }
++
++ /* initialize PMNC, reset overflow, D bit, C bit and P bit. */
++ armv6_pmnc_write(PMCR_OFL_PMN0 | PMCR_OFL_PMN1 | PMCR_OFL_CCNT |
++ PMCR_C | PMCR_P);
++
++ /* configure control register */
++ for (pmnc = 0, cnt = PMN0; cnt <= CCNT; cnt++) {
++ unsigned long event;
++
++ if (!pmnc_enabled[cnt])
++ continue;
++
++ event = pmnc_event[cnt] & 255;
++
++ // Set event (if destined for PMNx counters)
++ if (cnt == PMN0) {
++ pmnc |= event << 20;
++ } else if (cnt == PMN1) {
++ pmnc |= event << 12;
++ }
++
++ // Reset counter
++ armv6_pmnc_reset_counter(cnt);
++ }
++ armv6_pmnc_write(pmnc | PMCR_E);
++
++ // return zero values, no need to read as the counters were just reset
++ for (cnt = PMN0; cnt <= CCNT; cnt++) {
++ if (pmnc_enabled[cnt]) {
++ per_cpu(perfCnt, cpu)[len++] = pmnc_key[cnt];
++ per_cpu(perfCnt, cpu)[len++] = 0;
++ }
++ }
++
++ if (buffer)
++ *buffer = per_cpu(perfCnt, cpu);
++
++ return len;
++}
++
++static int gator_events_armv6_offline(int **buffer, bool migrate)
++{
++ unsigned int cnt;
++
++ armv6_pmnc_write(armv6_pmnc_read() & ~PMCR_E);
++ for (cnt = PMN0; cnt <= CCNT; cnt++) {
++ armv6_pmnc_reset_counter(cnt);
++ }
++
++ return 0;
++}
++
++static void gator_events_armv6_stop(void)
++{
++ unsigned int cnt;
++
++ for (cnt = PMN0; cnt <= CCNT; cnt++) {
++ pmnc_enabled[cnt] = 0;
++ pmnc_event[cnt] = 0;
++ }
++}
++
++static int gator_events_armv6_read(int **buffer)
++{
++ int cnt, len = 0;
++ int cpu = smp_processor_id();
++
++ // a context switch may occur before the online hotplug event, thus need to check that the pmu is enabled
++ if (!(armv6_pmnc_read() & PMCR_E)) {
++ return 0;
++ }
++
++ for (cnt = PMN0; cnt <= CCNT; cnt++) {
++ if (pmnc_enabled[cnt]) {
++ u32 value = 0;
++ switch (cnt) {
++ case CCNT:
++ asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r" (value));
++ break;
++ case PMN0:
++ asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r" (value));
++ break;
++ case PMN1:
++ asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r" (value));
++ break;
++ }
++ armv6_pmnc_reset_counter(cnt);
++
++ per_cpu(perfCnt, cpu)[len++] = pmnc_key[cnt];
++ per_cpu(perfCnt, cpu)[len++] = value;
++ }
++ }
++
++ if (buffer)
++ *buffer = per_cpu(perfCnt, cpu);
++
++ return len;
++}
++
++static struct gator_interface gator_events_armv6_interface = {
++ .create_files = gator_events_armv6_create_files,
++ .stop = gator_events_armv6_stop,
++ .online = gator_events_armv6_online,
++ .offline = gator_events_armv6_offline,
++ .read = gator_events_armv6_read,
++};
++
++int gator_events_armv6_init(void)
++{
++ unsigned int cnt;
++
++ switch (gator_cpuid()) {
++ case ARM1136:
++ case ARM1156:
++ case ARM1176:
++ pmnc_name = "ARM11";
++ break;
++ case ARM11MPCORE:
++ pmnc_name = "ARM11MPCore";
++ break;
++ default:
++ return -1;
++ }
++
++ for (cnt = PMN0; cnt <= CCNT; cnt++) {
++ pmnc_enabled[cnt] = 0;
++ pmnc_event[cnt] = 0;
++ pmnc_key[cnt] = gator_events_get_key();
++ }
++
++ return gator_events_install(&gator_events_armv6_interface);
++}
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_armv7.c linux-linaro-stable-mx6/drivers/gator/gator_events_armv7.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_armv7.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_armv7.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,312 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/* Disabling interrupts
++ * Many of the functions below disable interrupts via local_irq_save(). This disabling of interrupts is done to prevent any race conditions
++ * between multiple entities (e.g. hrtimer interrupts and event based interrupts) calling the same functions. As accessing the pmu involves
++ * several steps (disable, select, read, enable), these steps must be performed atomically. Normal synchronization routines cannot be used
++ * as these functions are being called from interrupt context.
++ */
++
++#include "gator.h"
++
++// gator_events_perf_pmu.c is used if perf is supported
++#if GATOR_NO_PERF_SUPPORT
++
++// Per-CPU PMNC: config reg
++#define PMNC_E (1 << 0) /* Enable all counters */
++#define PMNC_P (1 << 1) /* Reset all counters */
++#define PMNC_C (1 << 2) /* Cycle counter reset */
++#define PMNC_MASK 0x3f /* Mask for writable bits */
++
++// ccnt reg
++#define CCNT_REG (1 << 31)
++
++#define CCNT 0
++#define CNT0 1
++#define CNTMAX (6+1)
++
++static const char *pmnc_name;
++static int pmnc_counters;
++
++static unsigned long pmnc_enabled[CNTMAX];
++static unsigned long pmnc_event[CNTMAX];
++static unsigned long pmnc_key[CNTMAX];
++
++static DEFINE_PER_CPU(int[CNTMAX * 2], perfCnt);
++
++inline void armv7_pmnc_write(u32 val)
++{
++ val &= PMNC_MASK;
++ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
++}
++
++inline u32 armv7_pmnc_read(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
++ return val;
++}
++
++inline u32 armv7_ccnt_read(u32 reset_value)
++{
++ unsigned long flags;
++ u32 newval = -reset_value;
++ u32 den = CCNT_REG;
++ u32 val;
++
++ local_irq_save(flags);
++ asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (den)); // disable
++ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); // read
++ asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (newval)); // new value
++ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (den)); // enable
++ local_irq_restore(flags);
++
++ return val;
++}
++
++inline u32 armv7_cntn_read(unsigned int cnt, u32 reset_value)
++{
++ unsigned long flags;
++ u32 newval = -reset_value;
++ u32 sel = (cnt - CNT0);
++ u32 den = 1 << sel;
++ u32 oldval;
++
++ local_irq_save(flags);
++ asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (den)); // disable
++ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (sel)); // select
++ asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (oldval)); // read
++ asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (newval)); // new value
++ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (den)); // enable
++ local_irq_restore(flags);
++
++ return oldval;
++}
++
++static inline void armv7_pmnc_disable_interrupt(unsigned int cnt)
++{
++ u32 val = cnt ? (1 << (cnt - CNT0)) : (1 << 31);
++ asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
++}
++
++inline u32 armv7_pmnc_reset_interrupt(void)
++{
++ // Get and reset overflow status flags
++ u32 flags;
++ asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (flags));
++ flags &= 0x8000003f;
++ asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (flags));
++ return flags;
++}
++
++static inline u32 armv7_pmnc_enable_counter(unsigned int cnt)
++{
++ u32 val = cnt ? (1 << (cnt - CNT0)) : CCNT_REG;
++ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
++ return cnt;
++}
++
++static inline u32 armv7_pmnc_disable_counter(unsigned int cnt)
++{
++ u32 val = cnt ? (1 << (cnt - CNT0)) : CCNT_REG;
++ asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
++ return cnt;
++}
++
++static inline int armv7_pmnc_select_counter(unsigned int cnt)
++{
++ u32 val = (cnt - CNT0);
++ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
++ return cnt;
++}
++
++static inline void armv7_pmnc_write_evtsel(unsigned int cnt, u32 val)
++{
++ if (armv7_pmnc_select_counter(cnt) == cnt) {
++ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
++ }
++}
++
++static int gator_events_armv7_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++ int i;
++
++ for (i = 0; i < pmnc_counters; i++) {
++ char buf[40];
++ if (i == 0) {
++ snprintf(buf, sizeof buf, "ARM_%s_ccnt", pmnc_name);
++ } else {
++ snprintf(buf, sizeof buf, "ARM_%s_cnt%d", pmnc_name, i - 1);
++ }
++ dir = gatorfs_mkdir(sb, root, buf);
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &pmnc_enabled[i]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &pmnc_key[i]);
++ if (i > 0) {
++ gatorfs_create_ulong(sb, dir, "event", &pmnc_event[i]);
++ }
++ }
++
++ return 0;
++}
++
++static int gator_events_armv7_online(int **buffer, bool migrate)
++{
++ unsigned int cnt, len = 0, cpu = smp_processor_id();
++
++ if (armv7_pmnc_read() & PMNC_E) {
++ armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E);
++ }
++
++ // Initialize & Reset PMNC: C bit and P bit
++ armv7_pmnc_write(PMNC_P | PMNC_C);
++
++ // Reset overflow flags
++ armv7_pmnc_reset_interrupt();
++
++ for (cnt = CCNT; cnt < CNTMAX; cnt++) {
++ unsigned long event;
++
++ if (!pmnc_enabled[cnt])
++ continue;
++
++ // Disable counter
++ armv7_pmnc_disable_counter(cnt);
++
++ event = pmnc_event[cnt] & 255;
++
++ // Set event (if destined for PMNx counters), we don't need to set the event if it's a cycle count
++ if (cnt != CCNT)
++ armv7_pmnc_write_evtsel(cnt, event);
++
++ armv7_pmnc_disable_interrupt(cnt);
++
++ // Reset counter
++ cnt ? armv7_cntn_read(cnt, 0) : armv7_ccnt_read(0);
++
++ // Enable counter
++ armv7_pmnc_enable_counter(cnt);
++ }
++
++ // enable
++ armv7_pmnc_write(armv7_pmnc_read() | PMNC_E);
++
++ // return zero values, no need to read as the counters were just reset
++ for (cnt = 0; cnt < pmnc_counters; cnt++) {
++ if (pmnc_enabled[cnt]) {
++ per_cpu(perfCnt, cpu)[len++] = pmnc_key[cnt];
++ per_cpu(perfCnt, cpu)[len++] = 0;
++ }
++ }
++
++ if (buffer)
++ *buffer = per_cpu(perfCnt, cpu);
++
++ return len;
++}
++
++static int gator_events_armv7_offline(int **buffer, bool migrate)
++{
++ // disable all counters, including PMCCNTR; overflow IRQs will not be signaled
++ armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E);
++
++ return 0;
++}
++
++static void gator_events_armv7_stop(void)
++{
++ unsigned int cnt;
++
++ for (cnt = CCNT; cnt < CNTMAX; cnt++) {
++ pmnc_enabled[cnt] = 0;
++ pmnc_event[cnt] = 0;
++ }
++}
++
++static int gator_events_armv7_read(int **buffer)
++{
++ int cnt, len = 0;
++ int cpu = smp_processor_id();
++
++ // a context switch may occur before the online hotplug event, thus need to check that the pmu is enabled
++ if (!(armv7_pmnc_read() & PMNC_E)) {
++ return 0;
++ }
++
++ for (cnt = 0; cnt < pmnc_counters; cnt++) {
++ if (pmnc_enabled[cnt]) {
++ int value;
++ if (cnt == CCNT) {
++ value = armv7_ccnt_read(0);
++ } else {
++ value = armv7_cntn_read(cnt, 0);
++ }
++ per_cpu(perfCnt, cpu)[len++] = pmnc_key[cnt];
++ per_cpu(perfCnt, cpu)[len++] = value;
++ }
++ }
++
++ if (buffer)
++ *buffer = per_cpu(perfCnt, cpu);
++
++ return len;
++}
++
++static struct gator_interface gator_events_armv7_interface = {
++ .create_files = gator_events_armv7_create_files,
++ .stop = gator_events_armv7_stop,
++ .online = gator_events_armv7_online,
++ .offline = gator_events_armv7_offline,
++ .read = gator_events_armv7_read,
++};
++
++int gator_events_armv7_init(void)
++{
++ unsigned int cnt;
++
++ switch (gator_cpuid()) {
++ case CORTEX_A5:
++ pmnc_name = "Cortex-A5";
++ pmnc_counters = 2;
++ break;
++ case CORTEX_A7:
++ pmnc_name = "Cortex-A7";
++ pmnc_counters = 4;
++ break;
++ case CORTEX_A8:
++ pmnc_name = "Cortex-A8";
++ pmnc_counters = 4;
++ break;
++ case CORTEX_A9:
++ pmnc_name = "Cortex-A9";
++ pmnc_counters = 6;
++ break;
++ case CORTEX_A15:
++ pmnc_name = "Cortex-A15";
++ pmnc_counters = 6;
++ break;
++ default:
++ return -1;
++ }
++
++ pmnc_counters++; // CNT[n] + CCNT
++
++ for (cnt = CCNT; cnt < CNTMAX; cnt++) {
++ pmnc_enabled[cnt] = 0;
++ pmnc_event[cnt] = 0;
++ pmnc_key[cnt] = gator_events_get_key();
++ }
++
++ return gator_events_install(&gator_events_armv7_interface);
++}
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_block.c linux-linaro-stable-mx6/drivers/gator/gator_events_block.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_block.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_block.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,153 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include "gator.h"
++#include <trace/events/block.h>
++
++#define BLOCK_RQ_WR 0
++#define BLOCK_RQ_RD 1
++
++#define BLOCK_TOTAL (BLOCK_RQ_RD+1)
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)
++#define EVENTWRITE REQ_RW
++#else
++#define EVENTWRITE REQ_WRITE
++#endif
++
++static ulong block_rq_wr_enabled;
++static ulong block_rq_rd_enabled;
++static ulong block_rq_wr_key;
++static ulong block_rq_rd_key;
++static atomic_t blockCnt[BLOCK_TOTAL];
++static int blockGet[BLOCK_TOTAL * 4];
++
++GATOR_DEFINE_PROBE(block_rq_complete, TP_PROTO(struct request_queue *q, struct request *rq))
++{
++ int write, size;
++
++ if (!rq)
++ return;
++
++ write = rq->cmd_flags & EVENTWRITE;
++ size = rq->resid_len;
++
++ if (!size)
++ return;
++
++ if (write) {
++ if (block_rq_wr_enabled) {
++ atomic_add(size, &blockCnt[BLOCK_RQ_WR]);
++ }
++ } else {
++ if (block_rq_rd_enabled) {
++ atomic_add(size, &blockCnt[BLOCK_RQ_RD]);
++ }
++ }
++}
++
++static int gator_events_block_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++
++ /* block_complete_wr */
++ dir = gatorfs_mkdir(sb, root, "Linux_block_rq_wr");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &block_rq_wr_enabled);
++ gatorfs_create_ro_ulong(sb, dir, "key", &block_rq_wr_key);
++
++ /* block_complete_rd */
++ dir = gatorfs_mkdir(sb, root, "Linux_block_rq_rd");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &block_rq_rd_enabled);
++ gatorfs_create_ro_ulong(sb, dir, "key", &block_rq_rd_key);
++
++ return 0;
++}
++
++static int gator_events_block_start(void)
++{
++ // register tracepoints
++ if (block_rq_wr_enabled || block_rq_rd_enabled)
++ if (GATOR_REGISTER_TRACE(block_rq_complete))
++ goto fail_block_rq_exit;
++ pr_debug("gator: registered block event tracepoints\n");
++
++ return 0;
++
++ // unregister tracepoints on error
++fail_block_rq_exit:
++ pr_err("gator: block event tracepoints failed to activate, please verify that tracepoints are enabled in the linux kernel\n");
++
++ return -1;
++}
++
++static void gator_events_block_stop(void)
++{
++ if (block_rq_wr_enabled || block_rq_rd_enabled)
++ GATOR_UNREGISTER_TRACE(block_rq_complete);
++ pr_debug("gator: unregistered block event tracepoints\n");
++
++ block_rq_wr_enabled = 0;
++ block_rq_rd_enabled = 0;
++}
++
++static int gator_events_block_read(int **buffer)
++{
++ int len, value, data = 0;
++
++ if (!on_primary_core()) {
++ return 0;
++ }
++
++ len = 0;
++ if (block_rq_wr_enabled && (value = atomic_read(&blockCnt[BLOCK_RQ_WR])) > 0) {
++ atomic_sub(value, &blockCnt[BLOCK_RQ_WR]);
++ blockGet[len++] = block_rq_wr_key;
++ blockGet[len++] = 0; // indicates to Streamline that value bytes were written now, not since the last message
++ blockGet[len++] = block_rq_wr_key;
++ blockGet[len++] = value;
++ data += value;
++ }
++ if (block_rq_rd_enabled && (value = atomic_read(&blockCnt[BLOCK_RQ_RD])) > 0) {
++ atomic_sub(value, &blockCnt[BLOCK_RQ_RD]);
++ blockGet[len++] = block_rq_rd_key;
++ blockGet[len++] = 0; // indicates to Streamline that value bytes were read now, not since the last message
++ blockGet[len++] = block_rq_rd_key;
++ blockGet[len++] = value;
++ data += value;
++ }
++
++ if (buffer)
++ *buffer = blockGet;
++
++ return len;
++}
++
++static struct gator_interface gator_events_block_interface = {
++ .create_files = gator_events_block_create_files,
++ .start = gator_events_block_start,
++ .stop = gator_events_block_stop,
++ .read = gator_events_block_read,
++};
++
++int gator_events_block_init(void)
++{
++ block_rq_wr_enabled = 0;
++ block_rq_rd_enabled = 0;
++
++ block_rq_wr_key = gator_events_get_key();
++ block_rq_rd_key = gator_events_get_key();
++
++ return gator_events_install(&gator_events_block_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_ccn-504.c linux-linaro-stable-mx6/drivers/gator/gator_events_ccn-504.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_ccn-504.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_ccn-504.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,346 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/io.h>
++#include <linux/module.h>
++
++#include "gator.h"
++
++#define NUM_REGIONS 256
++#define REGION_SIZE (64*1024)
++#define REGION_DEBUG 1
++#define REGION_XP 64
++#define NUM_XPS 11
++
++// DT (Debug) region
++#define PMEVCNTSR0 0x0150
++#define PMCCNTRSR 0x0190
++#define PMCR 0x01A8
++#define PMSR 0x01B0
++#define PMSR_REQ 0x01B8
++#define PMSR_CLR 0x01C0
++
++// XP region
++#define DT_CONFIG 0x0300
++#define DT_CONTROL 0x0370
++
++// Multiple
++#define PMU_EVENT_SEL 0x0600
++#define OLY_ID 0xFF00
++
++#define CCNT 4
++#define CNTMAX (CCNT + 1)
++
++#define get_pmu_event_id(event) (((event) >> 0) & 0xFF)
++#define get_node_type(event) (((event) >> 8) & 0xFF)
++#define get_region(event) (((event) >> 16) & 0xFF)
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)
++
++// From kernel/params.c
++#define STANDARD_PARAM_DEF(name, type, format, tmptype, strtolfn) \
++ int param_set_##name(const char *val, struct kernel_param *kp) \
++ { \
++ tmptype l; \
++ int ret; \
++ \
++ if (!val) return -EINVAL; \
++ ret = strtolfn(val, 0, &l); \
++ if (ret == -EINVAL || ((type)l != l)) \
++ return -EINVAL; \
++ *((type *)kp->arg) = l; \
++ return 0; \
++ } \
++ int param_get_##name(char *buffer, struct kernel_param *kp) \
++ { \
++ return sprintf(buffer, format, *((type *)kp->arg)); \
++ }
++
++#else
++
++// From kernel/params.c
++#define STANDARD_PARAM_DEF(name, type, format, tmptype, strtolfn) \
++ int param_set_##name(const char *val, const struct kernel_param *kp) \
++ { \
++ tmptype l; \
++ int ret; \
++ \
++ ret = strtolfn(val, 0, &l); \
++ if (ret < 0 || ((type)l != l)) \
++ return ret < 0 ? ret : -EINVAL; \
++ *((type *)kp->arg) = l; \
++ return 0; \
++ } \
++ int param_get_##name(char *buffer, const struct kernel_param *kp) \
++ { \
++ return scnprintf(buffer, PAGE_SIZE, format, \
++ *((type *)kp->arg)); \
++ } \
++ struct kernel_param_ops param_ops_##name = { \
++ .set = param_set_##name, \
++ .get = param_get_##name, \
++ }; \
++ EXPORT_SYMBOL(param_set_##name); \
++ EXPORT_SYMBOL(param_get_##name); \
++ EXPORT_SYMBOL(param_ops_##name)
++
++#endif
++
++STANDARD_PARAM_DEF(u64, u64, "%llu", u64, strict_strtoull);
++
++// From include/linux/moduleparam.h
++#define param_check_u64(name, p) __param_check(name, p, u64)
++
++MODULE_PARM_DESC(ccn504_addr, "CCN-504 physical base address");
++static u64 ccn504_addr = 0;
++module_param(ccn504_addr, u64, 0444);
++
++static void __iomem *gator_events_ccn504_base;
++static bool gator_events_ccn504_global_enabled;
++static unsigned long gator_events_ccn504_enabled[CNTMAX];
++static unsigned long gator_events_ccn504_event[CNTMAX];
++static unsigned long gator_events_ccn504_key[CNTMAX];
++static int gator_events_ccn504_buffer[2*CNTMAX];
++static int gator_events_ccn504_prev[CNTMAX];
++
++static void gator_events_ccn504_create_shutdown(void)
++{
++ if (gator_events_ccn504_base != NULL) {
++ iounmap(gator_events_ccn504_base);
++ }
++}
++
++static int gator_events_ccn504_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++ int i;
++ char buf[32];
++
++ for (i = 0; i < CNTMAX; ++i) {
++ if (i == CCNT) {
++ snprintf(buf, sizeof(buf), "CCN-504_ccnt");
++ } else {
++ snprintf(buf, sizeof(buf), "CCN-504_cnt%i", i);
++ }
++ dir = gatorfs_mkdir(sb, root, buf);
++ if (!dir) {
++ return -1;
++ }
++
++ gatorfs_create_ulong(sb, dir, "enabled", &gator_events_ccn504_enabled[i]);
++ if (i != CCNT) {
++ gatorfs_create_ulong(sb, dir, "event", &gator_events_ccn504_event[i]);
++ }
++ gatorfs_create_ro_ulong(sb, dir, "key", &gator_events_ccn504_key[i]);
++ }
++
++ return 0;
++}
++
++static void gator_events_ccn504_set_dt_config(int xp_node_id, int event_num, int value)
++{
++ u32 dt_config;
++
++ dt_config = readl(gator_events_ccn504_base + (REGION_XP + xp_node_id)*REGION_SIZE + DT_CONFIG);
++ dt_config |= (value + event_num) << (4*event_num);
++ writel(dt_config, gator_events_ccn504_base + (REGION_XP + xp_node_id)*REGION_SIZE + DT_CONFIG);
++}
++
++static int gator_events_ccn504_start(void)
++{
++ int i;
++
++ gator_events_ccn504_global_enabled = 0;
++ for (i = 0; i < CNTMAX; ++i) {
++ if (gator_events_ccn504_enabled[i]) {
++ gator_events_ccn504_global_enabled = 1;
++ break;
++ }
++ }
++
++ if (!gator_events_ccn504_global_enabled) {
++ return 0;
++ }
++
++ memset(&gator_events_ccn504_prev, 0x80, sizeof(gator_events_ccn504_prev));
++
++ // Disable INTREQ on overflow
++ // [6] ovfl_intr_en = 0
++ // perhaps set to 1?
++ // [5] cntr_rst = 0
++ // No register paring
++ // [4:1] cntcfg = 0
++ // Enable PMU features
++ // [0] pmu_en = 1
++ writel(0x1, gator_events_ccn504_base + REGION_DEBUG*REGION_SIZE + PMCR);
++
++ // Configure the XPs
++ for (i = 0; i < NUM_XPS; ++i) {
++ int dt_control;
++
++ // Pass on all events
++ writel(0, gator_events_ccn504_base + (REGION_XP + i)*REGION_SIZE + DT_CONFIG);
++
++ // Enable PMU capability
++ // [0] dt_enable = 1
++ dt_control = readl(gator_events_ccn504_base + (REGION_XP + i)*REGION_SIZE + DT_CONTROL);
++ dt_control |= 0x1;
++ writel(dt_control, gator_events_ccn504_base + (REGION_XP + i)*REGION_SIZE + DT_CONTROL);
++ }
++
++ // Assume no other pmu_event_sel registers are set
++
++ // cycle counter does not need to be enabled
++ for (i = 0; i < CCNT; ++i) {
++ int pmu_event_id;
++ int node_type;
++ int region;
++ u32 pmu_event_sel;
++ u32 oly_id_whole;
++ u32 oly_id;
++ u32 node_id;
++
++ if (!gator_events_ccn504_enabled[i]) {
++ continue;
++ }
++
++ pmu_event_id = get_pmu_event_id(gator_events_ccn504_event[i]);
++ node_type = get_node_type(gator_events_ccn504_event[i]);
++ region = get_region(gator_events_ccn504_event[i]);
++
++ // Verify the node_type
++ oly_id_whole = readl(gator_events_ccn504_base + region*REGION_SIZE + OLY_ID);
++ oly_id = oly_id_whole & 0x1F;
++ node_id = (oly_id_whole >> 8) & 0x7F;
++ if ((oly_id != node_type) ||
++ ((node_type == 0x16) && ((oly_id != 0x14) && (oly_id != 0x15) && (oly_id != 0x16) && (oly_id != 0x18) && (oly_id != 0x19) && (oly_id != 0x1A)))) {
++ printk(KERN_ERR "gator: oly_id is 0x%x expected 0x%x\n", oly_id, node_type);
++ return -1;
++ }
++
++ // Set the control register
++ pmu_event_sel = readl(gator_events_ccn504_base + region*REGION_SIZE + PMU_EVENT_SEL);
++ switch (node_type) {
++ case 0x08: // XP
++ pmu_event_sel |= pmu_event_id << (7*i);
++ gator_events_ccn504_set_dt_config(node_id, i, 0x4);
++ break;
++ case 0x04: // HN-F
++ case 0x16: // RN-I
++ case 0x10: // SBAS
++ pmu_event_sel |= pmu_event_id << (4*i);
++ gator_events_ccn504_set_dt_config(node_id/2, i, (node_id & 1) == 0 ? 0x8 : 0xC);
++ break;
++ }
++ writel(pmu_event_sel, gator_events_ccn504_base + region*REGION_SIZE + PMU_EVENT_SEL);
++ }
++
++ return 0;
++}
++
++static void gator_events_ccn504_stop(void)
++{
++ int i;
++
++ if (!gator_events_ccn504_global_enabled) {
++ return;
++ }
++
++ // cycle counter does not need to be disabled
++ for (i = 0; i < CCNT; ++i) {
++ int region;
++
++ if (!gator_events_ccn504_enabled[i]) {
++ continue;
++ }
++
++ region = get_region(gator_events_ccn504_event[i]);
++
++ writel(0, gator_events_ccn504_base + region*REGION_SIZE + PMU_EVENT_SEL);
++ }
++
++ // Clear dt_config
++ for (i = 0; i < NUM_XPS; ++i) {
++ writel(0, gator_events_ccn504_base + (REGION_XP + i)*REGION_SIZE + DT_CONFIG);
++ }
++}
++
++static int gator_events_ccn504_read(int **buffer)
++{
++ int i;
++ int len = 0;
++ int value;
++
++ if (!on_primary_core() || !gator_events_ccn504_global_enabled) {
++ return 0;
++ }
++
++ // Verify the pmsr register is zero
++ while (readl(gator_events_ccn504_base + REGION_DEBUG*REGION_SIZE + PMSR) != 0);
++
++ // Request a PMU snapshot
++ writel(1, gator_events_ccn504_base + REGION_DEBUG*REGION_SIZE + PMSR_REQ);
++
++ // Wait for the snapshot
++ while (readl(gator_events_ccn504_base + REGION_DEBUG*REGION_SIZE + PMSR) == 0);
++
++ // Read the shadow registers
++ for (i = 0; i < CNTMAX; ++i) {
++ if (!gator_events_ccn504_enabled[i]) {
++ continue;
++ }
++
++ value = readl(gator_events_ccn504_base + REGION_DEBUG*REGION_SIZE + (i == CCNT ? PMCCNTRSR : PMEVCNTSR0 + 8*i));
++ if (gator_events_ccn504_prev[i] != 0x80808080) {
++ gator_events_ccn504_buffer[len++] = gator_events_ccn504_key[i];
++ gator_events_ccn504_buffer[len++] = value - gator_events_ccn504_prev[i];
++ }
++ gator_events_ccn504_prev[i] = value;
++
++ // Are the counters registers cleared when read? Is that what the cntr_rst bit on the pmcr register does?
++ }
++
++ // Clear the PMU snapshot status
++ writel(1, gator_events_ccn504_base + REGION_DEBUG*REGION_SIZE + PMSR_CLR);
++
++ if (buffer)
++ *buffer = gator_events_ccn504_buffer;
++
++ return len;
++}
++
++static struct gator_interface gator_events_ccn504_interface = {
++ .shutdown = gator_events_ccn504_create_shutdown,
++ .create_files = gator_events_ccn504_create_files,
++ .start = gator_events_ccn504_start,
++ .stop = gator_events_ccn504_stop,
++ .read = gator_events_ccn504_read,
++};
++
++int gator_events_ccn504_init(void)
++{
++ int i;
++
++ if (ccn504_addr == 0) {
++ return -1;
++ }
++
++ gator_events_ccn504_base = ioremap(ccn504_addr, NUM_REGIONS*REGION_SIZE);
++ if (gator_events_ccn504_base == NULL) {
++ printk(KERN_ERR "gator: ioremap returned NULL\n");
++ return -1;
++ }
++
++ for (i = 0; i < CNTMAX; ++i) {
++ gator_events_ccn504_enabled[i] = 0;
++ gator_events_ccn504_event[i] = 0;
++ gator_events_ccn504_key[i] = gator_events_get_key();
++ }
++
++ return gator_events_install(&gator_events_ccn504_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_irq.c linux-linaro-stable-mx6/drivers/gator/gator_events_irq.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_irq.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_irq.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,165 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include "gator.h"
++#include <trace/events/irq.h>
++
++#define HARDIRQ 0
++#define SOFTIRQ 1
++#define TOTALIRQ (SOFTIRQ+1)
++
++static ulong hardirq_enabled;
++static ulong softirq_enabled;
++static ulong hardirq_key;
++static ulong softirq_key;
++static DEFINE_PER_CPU(atomic_t[TOTALIRQ], irqCnt);
++static DEFINE_PER_CPU(int[TOTALIRQ * 2], irqGet);
++
++GATOR_DEFINE_PROBE(irq_handler_exit,
++ TP_PROTO(int irq, struct irqaction *action, int ret))
++{
++ atomic_inc(&per_cpu(irqCnt, get_physical_cpu())[HARDIRQ]);
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37)
++GATOR_DEFINE_PROBE(softirq_exit, TP_PROTO(struct softirq_action *h, struct softirq_action *vec))
++#else
++GATOR_DEFINE_PROBE(softirq_exit, TP_PROTO(unsigned int vec_nr))
++#endif
++{
++ atomic_inc(&per_cpu(irqCnt, get_physical_cpu())[SOFTIRQ]);
++}
++
++static int gator_events_irq_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++
++ /* irq */
++ dir = gatorfs_mkdir(sb, root, "Linux_irq_irq");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &hardirq_enabled);
++ gatorfs_create_ro_ulong(sb, dir, "key", &hardirq_key);
++
++ /* soft irq */
++ dir = gatorfs_mkdir(sb, root, "Linux_irq_softirq");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &softirq_enabled);
++ gatorfs_create_ro_ulong(sb, dir, "key", &softirq_key);
++
++ return 0;
++}
++
++static int gator_events_irq_online(int **buffer, bool migrate)
++{
++ int len = 0, cpu = get_physical_cpu();
++
++ // synchronization with the irq_exit functions is not necessary as the values are being reset
++ if (hardirq_enabled) {
++ atomic_set(&per_cpu(irqCnt, cpu)[HARDIRQ], 0);
++ per_cpu(irqGet, cpu)[len++] = hardirq_key;
++ per_cpu(irqGet, cpu)[len++] = 0;
++ }
++
++ if (softirq_enabled) {
++ atomic_set(&per_cpu(irqCnt, cpu)[SOFTIRQ], 0);
++ per_cpu(irqGet, cpu)[len++] = softirq_key;
++ per_cpu(irqGet, cpu)[len++] = 0;
++ }
++
++ if (buffer)
++ *buffer = per_cpu(irqGet, cpu);
++
++ return len;
++}
++
++static int gator_events_irq_start(void)
++{
++ // register tracepoints
++ if (hardirq_enabled)
++ if (GATOR_REGISTER_TRACE(irq_handler_exit))
++ goto fail_hardirq_exit;
++ if (softirq_enabled)
++ if (GATOR_REGISTER_TRACE(softirq_exit))
++ goto fail_softirq_exit;
++ pr_debug("gator: registered irq tracepoints\n");
++
++ return 0;
++
++ // unregister tracepoints on error
++fail_softirq_exit:
++ if (hardirq_enabled)
++ GATOR_UNREGISTER_TRACE(irq_handler_exit);
++fail_hardirq_exit:
++ pr_err("gator: irq tracepoints failed to activate, please verify that tracepoints are enabled in the linux kernel\n");
++
++ return -1;
++}
++
++static void gator_events_irq_stop(void)
++{
++ if (hardirq_enabled)
++ GATOR_UNREGISTER_TRACE(irq_handler_exit);
++ if (softirq_enabled)
++ GATOR_UNREGISTER_TRACE(softirq_exit);
++ pr_debug("gator: unregistered irq tracepoints\n");
++
++ hardirq_enabled = 0;
++ softirq_enabled = 0;
++}
++
++static int gator_events_irq_read(int **buffer)
++{
++ int len, value;
++ int cpu = get_physical_cpu();
++
++ len = 0;
++ if (hardirq_enabled) {
++ value = atomic_read(&per_cpu(irqCnt, cpu)[HARDIRQ]);
++ atomic_sub(value, &per_cpu(irqCnt, cpu)[HARDIRQ]);
++
++ per_cpu(irqGet, cpu)[len++] = hardirq_key;
++ per_cpu(irqGet, cpu)[len++] = value;
++ }
++
++ if (softirq_enabled) {
++ value = atomic_read(&per_cpu(irqCnt, cpu)[SOFTIRQ]);
++ atomic_sub(value, &per_cpu(irqCnt, cpu)[SOFTIRQ]);
++
++ per_cpu(irqGet, cpu)[len++] = softirq_key;
++ per_cpu(irqGet, cpu)[len++] = value;
++ }
++
++ if (buffer)
++ *buffer = per_cpu(irqGet, cpu);
++
++ return len;
++}
++
++static struct gator_interface gator_events_irq_interface = {
++ .create_files = gator_events_irq_create_files,
++ .online = gator_events_irq_online,
++ .start = gator_events_irq_start,
++ .stop = gator_events_irq_stop,
++ .read = gator_events_irq_read,
++};
++
++int gator_events_irq_init(void)
++{
++ hardirq_key = gator_events_get_key();
++ softirq_key = gator_events_get_key();
++
++ hardirq_enabled = 0;
++ softirq_enabled = 0;
++
++ return gator_events_install(&gator_events_irq_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_l2c-310.c linux-linaro-stable-mx6/drivers/gator/gator_events_l2c-310.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_l2c-310.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_l2c-310.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,208 @@
++/**
++ * l2c310 (L2 Cache Controller) event counters for gator
++ *
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#if defined(CONFIG_OF)
++#include <linux/of.h>
++#include <linux/of_address.h>
++#endif
++#include <asm/hardware/cache-l2x0.h>
++
++#include "gator.h"
++
++#define L2C310_COUNTERS_NUM 2
++
++static struct {
++ unsigned long enabled;
++ unsigned long event;
++ unsigned long key;
++} l2c310_counters[L2C310_COUNTERS_NUM];
++
++static int l2c310_buffer[L2C310_COUNTERS_NUM * 2];
++
++static void __iomem *l2c310_base;
++
++static void gator_events_l2c310_reset_counters(void)
++{
++ u32 val = readl(l2c310_base + L2X0_EVENT_CNT_CTRL);
++
++ val |= ((1 << L2C310_COUNTERS_NUM) - 1) << 1;
++
++ writel(val, l2c310_base + L2X0_EVENT_CNT_CTRL);
++}
++
++static int gator_events_l2c310_create_files(struct super_block *sb,
++ struct dentry *root)
++{
++ int i;
++
++ for (i = 0; i < L2C310_COUNTERS_NUM; i++) {
++ char buf[16];
++ struct dentry *dir;
++
++ snprintf(buf, sizeof(buf), "L2C-310_cnt%d", i);
++ dir = gatorfs_mkdir(sb, root, buf);
++ if (WARN_ON(!dir))
++ return -1;
++ gatorfs_create_ulong(sb, dir, "enabled",
++ &l2c310_counters[i].enabled);
++ gatorfs_create_ulong(sb, dir, "event",
++ &l2c310_counters[i].event);
++ gatorfs_create_ro_ulong(sb, dir, "key",
++ &l2c310_counters[i].key);
++ }
++
++ return 0;
++}
++
++static int gator_events_l2c310_start(void)
++{
++ static const unsigned long l2x0_event_cntx_cfg[L2C310_COUNTERS_NUM] = {
++ L2X0_EVENT_CNT0_CFG,
++ L2X0_EVENT_CNT1_CFG,
++ };
++ int i;
++
++ /* Counter event sources */
++ for (i = 0; i < L2C310_COUNTERS_NUM; i++)
++ writel((l2c310_counters[i].event & 0xf) << 2,
++ l2c310_base + l2x0_event_cntx_cfg[i]);
++
++ gator_events_l2c310_reset_counters();
++
++ /* Event counter enable */
++ writel(1, l2c310_base + L2X0_EVENT_CNT_CTRL);
++
++ return 0;
++}
++
++static void gator_events_l2c310_stop(void)
++{
++ /* Event counter disable */
++ writel(0, l2c310_base + L2X0_EVENT_CNT_CTRL);
++}
++
++static int gator_events_l2c310_read(int **buffer)
++{
++ static const unsigned long l2x0_event_cntx_val[L2C310_COUNTERS_NUM] = {
++ L2X0_EVENT_CNT0_VAL,
++ L2X0_EVENT_CNT1_VAL,
++ };
++ int i;
++ int len = 0;
++
++ if (!on_primary_core())
++ return 0;
++
++ for (i = 0; i < L2C310_COUNTERS_NUM; i++) {
++ if (l2c310_counters[i].enabled) {
++ l2c310_buffer[len++] = l2c310_counters[i].key;
++ l2c310_buffer[len++] = readl(l2c310_base +
++ l2x0_event_cntx_val[i]);
++ }
++ }
++
++ /* l2c310 counters are saturating, not wrapping in case of overflow */
++ gator_events_l2c310_reset_counters();
++
++ if (buffer)
++ *buffer = l2c310_buffer;
++
++ return len;
++}
++
++static struct gator_interface gator_events_l2c310_interface = {
++ .create_files = gator_events_l2c310_create_files,
++ .start = gator_events_l2c310_start,
++ .stop = gator_events_l2c310_stop,
++ .read = gator_events_l2c310_read,
++};
++
++#define L2C310_ADDR_PROBE (~0)
++
++MODULE_PARM_DESC(l2c310_addr, "L2C310 physical base address (0 to disable)");
++static unsigned long l2c310_addr = L2C310_ADDR_PROBE;
++module_param(l2c310_addr, ulong, 0444);
++
++static void __iomem *gator_events_l2c310_probe(void)
++{
++ phys_addr_t variants[] = {
++#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_S5PV310)
++ 0x10502000,
++#endif
++#if defined(CONFIG_ARCH_OMAP4)
++ 0x48242000,
++#endif
++#if defined(CONFIG_ARCH_TEGRA)
++ 0x50043000,
++#endif
++#if defined(CONFIG_ARCH_U8500)
++ 0xa0412000,
++#endif
++#if defined(CONFIG_ARCH_VEXPRESS)
++ 0x1e00a000, // A9x4 core tile (HBI-0191)
++ 0x2c0f0000, // New memory map tiles
++#endif
++ };
++ int i;
++ void __iomem *base;
++#if defined(CONFIG_OF)
++ struct device_node *node = of_find_all_nodes(NULL);
++
++ if (node) {
++ of_node_put(node);
++
++ node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
++ base = of_iomap(node, 0);
++ of_node_put(node);
++
++ return base;
++ }
++#endif
++
++ for (i = 0; i < ARRAY_SIZE(variants); i++) {
++ base = ioremap(variants[i], SZ_4K);
++ if (base) {
++ u32 cache_id = readl(base + L2X0_CACHE_ID);
++
++ if ((cache_id & 0xff0003c0) == 0x410000c0)
++ return base;
++
++ iounmap(base);
++ }
++ }
++
++ return NULL;
++}
++
++int gator_events_l2c310_init(void)
++{
++ int i;
++
++ if (gator_cpuid() != CORTEX_A5 && gator_cpuid() != CORTEX_A9)
++ return -1;
++
++ if (l2c310_addr == L2C310_ADDR_PROBE)
++ l2c310_base = gator_events_l2c310_probe();
++ else if (l2c310_addr)
++ l2c310_base = ioremap(l2c310_addr, SZ_4K);
++
++ if (!l2c310_base)
++ return -1;
++
++ for (i = 0; i < L2C310_COUNTERS_NUM; i++) {
++ l2c310_counters[i].enabled = 0;
++ l2c310_counters[i].key = gator_events_get_key();
++ }
++
++ return gator_events_install(&gator_events_l2c310_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_mali_4xx.c linux-linaro-stable-mx6/drivers/gator/gator_events_mali_4xx.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_mali_4xx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_mali_4xx.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,723 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "gator.h"
++
++#include <linux/module.h>
++#include <linux/time.h>
++#include <linux/math64.h>
++
++#include "linux/mali_linux_trace.h"
++
++#include "gator_events_mali_common.h"
++#include "gator_events_mali_4xx.h"
++
++/*
++ * There are (currently) four different variants of the comms between gator and Mali:
++ * 1 (deprecated): No software counter support
++ * 2 (deprecated): Tracepoint called for each separate s/w counter value as it appears
++ * 3 (default): Single tracepoint for all s/w counters in a bundle.
++ * Interface style 3 is the default if no other is specified. 1 and 2 will be eliminated when
++ * existing Mali DDKs are upgraded.
++ * 4. As above, but for the Utgard (Mali-450) driver.
++ */
++
++#if !defined(GATOR_MALI_INTERFACE_STYLE)
++#define GATOR_MALI_INTERFACE_STYLE (3)
++#endif
++
++#if GATOR_MALI_INTERFACE_STYLE < 4
++#include "mali/mali_mjollnir_profiling_gator_api.h"
++#else
++#include "mali/mali_utgard_profiling_gator_api.h"
++#endif
++
++/*
++ * Check that the MALI_SUPPORT define is set to one of the allowable device codes.
++ */
++#if (MALI_SUPPORT != MALI_4xx)
++#error MALI_SUPPORT set to an invalid device code: expecting MALI_4xx
++#endif
++
++/* gatorfs variables for counter enable state,
++ * the event the counter should count and the
++ * 'key' (a unique id set by gatord and returned
++ * by gator.ko)
++ */
++static unsigned long counter_enabled[NUMBER_OF_EVENTS];
++static unsigned long counter_event[NUMBER_OF_EVENTS];
++static unsigned long counter_key[NUMBER_OF_EVENTS];
++
++/* The data we have recorded */
++static u32 counter_data[NUMBER_OF_EVENTS];
++/* The address to sample (or 0 if samples are sent to us) */
++static u32 *counter_address[NUMBER_OF_EVENTS];
++
++/* An array used to return the data we recorded
++ * as key,value pairs hence the *2
++ */
++static unsigned long counter_dump[NUMBER_OF_EVENTS * 2];
++static unsigned long counter_prev[NUMBER_OF_EVENTS];
++
++/* Note whether tracepoints have been registered */
++static int trace_registered;
++
++/*
++ * These numbers define the actual numbers of each block type that exist in the system. Initially
++ * these are set to the maxima defined above; if the driver is capable of being queried (newer
++ * drivers only) then the values may be revised.
++ */
++static unsigned int n_vp_cores = MAX_NUM_VP_CORES;
++static unsigned int n_l2_cores = MAX_NUM_L2_CACHE_CORES;
++static unsigned int n_fp_cores = MAX_NUM_FP_CORES;
++
++/**
++ * Calculate the difference and handle the overflow.
++ */
++static u32 get_difference(u32 start, u32 end)
++{
++ if (start - end >= 0) {
++ return start - end;
++ }
++
++ // Mali counters are unsigned 32 bit values that wrap.
++ return (4294967295u - end) + start;
++}
++
++/**
++ * Returns non-zero if the given counter ID is an activity counter.
++ */
++static inline int is_activity_counter(unsigned int event_id)
++{
++ return (event_id >= FIRST_ACTIVITY_EVENT &&
++ event_id <= LAST_ACTIVITY_EVENT);
++}
++
++/**
++ * Returns non-zero if the given counter ID is a hardware counter.
++ */
++static inline int is_hw_counter(unsigned int event_id)
++{
++ return (event_id >= FIRST_HW_COUNTER && event_id <= LAST_HW_COUNTER);
++}
++
++/*
++ * These are provided for utgard compatibility.
++ */
++typedef void _mali_profiling_get_mali_version_type(struct _mali_profiling_mali_version *values);
++typedef u32 _mali_profiling_get_l2_counters_type(_mali_profiling_l2_counter_values *values);
++
++#if GATOR_MALI_INTERFACE_STYLE == 2
++/**
++ * Returns non-zero if the given counter ID is a software counter.
++ */
++static inline int is_sw_counter(unsigned int event_id)
++{
++ return (event_id >= FIRST_SW_COUNTER && event_id <= LAST_SW_COUNTER);
++}
++#endif
++
++#if GATOR_MALI_INTERFACE_STYLE == 2
++/*
++ * The Mali DDK uses s64 types to contain software counter values, but gator
++ * can only use a maximum of 32 bits. This function scales a software counter
++ * to an appropriate range.
++ */
++static u32 scale_sw_counter_value(unsigned int event_id, signed long long value)
++{
++ u32 scaled_value;
++
++ switch (event_id) {
++ case COUNTER_GLES_UPLOAD_TEXTURE_TIME:
++ case COUNTER_GLES_UPLOAD_VBO_TIME:
++ scaled_value = (u32)div_s64(value, 1000000);
++ break;
++ default:
++ scaled_value = (u32)value;
++ break;
++ }
++
++ return scaled_value;
++}
++#endif
++
++/* Probe for continuously sampled counter */
++#if 0 //WE_DONT_CURRENTLY_USE_THIS_SO_SUPPRESS_WARNING
++GATOR_DEFINE_PROBE(mali_sample_address, TP_PROTO(unsigned int event_id, u32 *addr))
++{
++ /* Turning on too many pr_debug statements in frequently called functions
++ * can cause stability and/or performance problems
++ */
++ //pr_debug("gator: mali_sample_address %d %d\n", event_id, addr);
++ if (event_id >= ACTIVITY_VP && event_id <= COUNTER_FP3_C1) {
++ counter_address[event_id] = addr;
++ }
++}
++#endif
++
++/* Probe for hardware counter events */
++GATOR_DEFINE_PROBE(mali_hw_counter, TP_PROTO(unsigned int event_id, unsigned int value))
++{
++ /* Turning on too many pr_debug statements in frequently called functions
++ * can cause stability and/or performance problems
++ */
++ //pr_debug("gator: mali_hw_counter %d %d\n", event_id, value);
++ if (is_hw_counter(event_id)) {
++ counter_data[event_id] = value;
++ }
++}
++
++#if GATOR_MALI_INTERFACE_STYLE == 2
++GATOR_DEFINE_PROBE(mali_sw_counter, TP_PROTO(unsigned int event_id, signed long long value))
++{
++ if (is_sw_counter(event_id)) {
++ counter_data[event_id] = scale_sw_counter_value(event_id, value);
++ }
++}
++#endif /* GATOR_MALI_INTERFACE_STYLE == 2 */
++
++#if GATOR_MALI_INTERFACE_STYLE >= 3
++GATOR_DEFINE_PROBE(mali_sw_counters, TP_PROTO(pid_t pid, pid_t tid, void *surface_id, unsigned int *counters))
++{
++ u32 i;
++
++ /* Copy over the values for those counters which are enabled. */
++ for (i = FIRST_SW_COUNTER; i <= LAST_SW_COUNTER; i++) {
++ if (counter_enabled[i]) {
++ counter_data[i] = (u32)(counters[i - FIRST_SW_COUNTER]);
++ }
++ }
++}
++#endif /* GATOR_MALI_INTERFACE_STYLE >= 3 */
++
++/**
++ * Create a single filesystem entry for a specified event.
++ * @param sb the superblock
++ * @param root Filesystem root
++ * @param name The name of the entry to create
++ * @param event The ID of the event
++ * @param create_event_item boolean indicating whether to create an 'event' filesystem entry. True to create.
++ *
++ * @return 0 if ok, non-zero if the create failed.
++ */
++static int create_fs_entry(struct super_block *sb, struct dentry *root, const char *name, int event, int create_event_item)
++{
++ struct dentry *dir;
++
++ dir = gatorfs_mkdir(sb, root, name);
++
++ if (!dir) {
++ return -1;
++ }
++
++ if (create_event_item) {
++ gatorfs_create_ulong(sb, dir, "event", &counter_event[event]);
++ }
++
++ gatorfs_create_ulong(sb, dir, "enabled", &counter_enabled[event]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &counter_key[event]);
++
++ return 0;
++}
++
++#if GATOR_MALI_INTERFACE_STYLE > 3
++/*
++ * Read the version info structure if available
++ */
++static void initialise_version_info(void)
++{
++ _mali_profiling_get_mali_version_type *mali_profiling_get_mali_version_symbol;
++
++ mali_profiling_get_mali_version_symbol = symbol_get(_mali_profiling_get_mali_version);
++
++ if (mali_profiling_get_mali_version_symbol) {
++ struct _mali_profiling_mali_version version_info;
++
++ pr_debug("gator: mali online _mali_profiling_get_mali_version symbol @ %p\n",
++ mali_profiling_get_mali_version_symbol);
++
++ /*
++ * Revise the number of each different core type using information derived from the DDK.
++ */
++ mali_profiling_get_mali_version_symbol(&version_info);
++
++ n_fp_cores = version_info.num_of_fp_cores;
++ n_vp_cores = version_info.num_of_vp_cores;
++ n_l2_cores = version_info.num_of_l2_cores;
++
++ /* Release the function - we're done with it. */
++ symbol_put(_mali_profiling_get_mali_version);
++ } else {
++ printk("gator: mali online _mali_profiling_get_mali_version symbol not found\n");
++ }
++}
++#endif
++
++static int create_files(struct super_block *sb, struct dentry *root)
++{
++ int event;
++ const char *mali_name = gator_mali_get_mali_name();
++
++ char buf[40];
++ int core_id;
++ int counter_number;
++
++ pr_debug("gator: Initialising counters with style = %d\n", GATOR_MALI_INTERFACE_STYLE);
++
++#if GATOR_MALI_INTERFACE_STYLE > 3
++ /*
++ * Initialise first: this sets up the number of cores available (on compatible DDK versions).
++ * Ideally this would not need guarding but other parts of the code depend on the interface style being set
++ * correctly; if it is not then the system can enter an inconsistent state.
++ */
++ initialise_version_info();
++#endif
++
++ /* Vertex processor counters */
++ for (core_id = 0; core_id < n_vp_cores; core_id++) {
++ int activity_counter_id = ACTIVITY_VP_0;
++ snprintf(buf, sizeof buf, "ARM_%s_VP_%d_active", mali_name, core_id);
++ if (create_fs_entry(sb, root, buf, activity_counter_id, 0) != 0) {
++ return -1;
++ }
++
++ for (counter_number = 0; counter_number < 2; counter_number++) {
++ int counter_id = COUNTER_VP_0_C0 + (2 * core_id) + counter_number;
++
++ snprintf(buf, sizeof buf, "ARM_%s_VP_%d_cnt%d", mali_name, core_id, counter_number);
++ if (create_fs_entry(sb, root, buf, counter_id, 1) != 0) {
++ return -1;
++ }
++ }
++ }
++
++ /* Fragment processors' counters */
++ for (core_id = 0; core_id < n_fp_cores; core_id++) {
++ int activity_counter_id = ACTIVITY_FP_0 + core_id;
++
++ snprintf(buf, sizeof buf, "ARM_%s_FP_%d_active", mali_name, core_id);
++ if (create_fs_entry(sb, root, buf, activity_counter_id, 0) != 0) {
++ return -1;
++ }
++
++ for (counter_number = 0; counter_number < 2; counter_number++) {
++ int counter_id = COUNTER_FP_0_C0 + (2 * core_id) + counter_number;
++
++ snprintf(buf, sizeof buf, "ARM_%s_FP_%d_cnt%d", mali_name, core_id, counter_number);
++ if (create_fs_entry(sb, root, buf, counter_id, 1) != 0) {
++ return -1;
++ }
++ }
++ }
++
++ /* L2 Cache counters */
++ for (core_id = 0; core_id < n_l2_cores; core_id++) {
++ for (counter_number = 0; counter_number < 2; counter_number++) {
++ int counter_id = COUNTER_L2_0_C0 + (2 * core_id) + counter_number;
++
++ snprintf(buf, sizeof buf, "ARM_%s_L2_%d_cnt%d", mali_name, core_id, counter_number);
++ if (create_fs_entry(sb, root, buf, counter_id, 1) != 0) {
++ return -1;
++ }
++ }
++ }
++
++ /* Now set up the software counter entries */
++ for (event = FIRST_SW_COUNTER; event <= LAST_SW_COUNTER; event++) {
++ snprintf(buf, sizeof(buf), "ARM_%s_SW_%d", mali_name, event - FIRST_SW_COUNTER);
++
++ if (create_fs_entry(sb, root, buf, event, 0) != 0) {
++ return -1;
++ }
++ }
++
++ /* Now set up the special counter entries */
++ snprintf(buf, sizeof(buf), "ARM_%s_Filmstrip_cnt0", mali_name);
++ if (create_fs_entry(sb, root, buf, COUNTER_FILMSTRIP, 1) != 0) {
++ return -1;
++ }
++
++#ifdef DVFS_REPORTED_BY_DDK
++ snprintf(buf, sizeof(buf), "ARM_%s_Frequency", mali_name);
++ if (create_fs_entry(sb, root, buf, COUNTER_FREQUENCY, 1) != 0) {
++ return -1;
++ }
++
++ snprintf(buf, sizeof(buf), "ARM_%s_Voltage", mali_name);
++ if (create_fs_entry(sb, root, buf, COUNTER_VOLTAGE, 1) != 0) {
++ return -1;
++ }
++#endif
++
++ return 0;
++}
++
++/*
++ * Local store for the get_counters entry point into the DDK.
++ * This is stored here since it is used very regularly.
++ */
++static mali_profiling_get_counters_type *mali_get_counters = NULL;
++static _mali_profiling_get_l2_counters_type *mali_get_l2_counters = NULL;
++
++/*
++ * Examine list of counters between two index limits and determine if any one is enabled.
++ * Returns 1 if any counter is enabled, 0 if none is.
++ */
++static int is_any_counter_enabled(unsigned int first_counter, unsigned int last_counter)
++{
++ unsigned int i;
++
++ for (i = first_counter; i <= last_counter; i++) {
++ if (counter_enabled[i]) {
++ return 1; /* At least one counter is enabled */
++ }
++ }
++
++ return 0; /* No s/w counters enabled */
++}
++
++static void init_counters(unsigned int from_counter, unsigned int to_counter)
++{
++ unsigned int counter_id;
++
++ /* If a Mali driver is present and exporting the appropriate symbol
++ * then we can request the HW counters (of which there are only 2)
++ * be configured to count the desired events
++ */
++ mali_profiling_set_event_type *mali_set_hw_event;
++
++ mali_set_hw_event = symbol_get(_mali_profiling_set_event);
++
++ if (mali_set_hw_event) {
++ pr_debug("gator: mali online _mali_profiling_set_event symbol @ %p\n", mali_set_hw_event);
++
++ for (counter_id = from_counter; counter_id <= to_counter; counter_id++) {
++ if (counter_enabled[counter_id]) {
++ mali_set_hw_event(counter_id, counter_event[counter_id]);
++ } else {
++ mali_set_hw_event(counter_id, 0xFFFFFFFF);
++ }
++ }
++
++ symbol_put(_mali_profiling_set_event);
++ } else {
++ printk("gator: mali online _mali_profiling_set_event symbol not found\n");
++ }
++}
++
++static void mali_counter_initialize(void)
++{
++ int i;
++ int core_id;
++
++ mali_profiling_control_type *mali_control;
++
++ init_counters(COUNTER_L2_0_C0, COUNTER_L2_0_C0 + (2 * n_l2_cores) - 1);
++ init_counters(COUNTER_VP_0_C0, COUNTER_VP_0_C0 + (2 * n_vp_cores) - 1);
++ init_counters(COUNTER_FP_0_C0, COUNTER_FP_0_C0 + (2 * n_fp_cores) - 1);
++
++ /* Generic control interface for Mali DDK. */
++ mali_control = symbol_get(_mali_profiling_control);
++ if (mali_control) {
++ /* The event attribute in the XML file keeps the actual frame rate. */
++ unsigned int rate = counter_event[COUNTER_FILMSTRIP] & 0xff;
++ unsigned int resize_factor = (counter_event[COUNTER_FILMSTRIP] >> 8) & 0xff;
++
++ pr_debug("gator: mali online _mali_profiling_control symbol @ %p\n", mali_control);
++
++ mali_control(SW_COUNTER_ENABLE, (is_any_counter_enabled(FIRST_SW_COUNTER, LAST_SW_COUNTER) ? 1 : 0));
++ mali_control(FBDUMP_CONTROL_ENABLE, (counter_enabled[COUNTER_FILMSTRIP] ? 1 : 0));
++ mali_control(FBDUMP_CONTROL_RATE, rate);
++ mali_control(FBDUMP_CONTROL_RESIZE_FACTOR, resize_factor);
++
++ pr_debug("gator: sent mali_control enabled=%d, rate=%d\n", (counter_enabled[COUNTER_FILMSTRIP] ? 1 : 0), rate);
++
++ symbol_put(_mali_profiling_control);
++ } else {
++ printk("gator: mali online _mali_profiling_control symbol not found\n");
++ }
++
++ mali_get_counters = symbol_get(_mali_profiling_get_counters);
++ if (mali_get_counters) {
++ pr_debug("gator: mali online _mali_profiling_get_counters symbol @ %p\n", mali_get_counters);
++
++ } else {
++ pr_debug("gator WARNING: mali _mali_profiling_get_counters symbol not defined");
++ }
++
++ mali_get_l2_counters = symbol_get(_mali_profiling_get_l2_counters);
++ if (mali_get_l2_counters) {
++ pr_debug("gator: mali online _mali_profiling_get_l2_counters symbol @ %p\n", mali_get_l2_counters);
++
++ } else {
++ pr_debug("gator WARNING: mali _mali_profiling_get_l2_counters symbol not defined");
++ }
++
++ if (!mali_get_counters && !mali_get_l2_counters) {
++ pr_debug("gator: WARNING: no L2 counters available");
++ n_l2_cores = 0;
++ }
++
++ for (core_id = 0; core_id < n_l2_cores; core_id++) {
++ int counter_id = COUNTER_L2_0_C0 + (2 * core_id);
++ counter_prev[counter_id] = 0;
++ counter_prev[counter_id + 1] = 0;
++ }
++
++ /* Clear counters in the start */
++ for (i = 0; i < NUMBER_OF_EVENTS; i++) {
++ counter_data[i] = 0;
++ }
++}
++
++static void mali_counter_deinitialize(void)
++{
++ mali_profiling_set_event_type *mali_set_hw_event;
++ mali_profiling_control_type *mali_control;
++
++ mali_set_hw_event = symbol_get(_mali_profiling_set_event);
++
++ if (mali_set_hw_event) {
++ int i;
++
++ pr_debug("gator: mali offline _mali_profiling_set_event symbol @ %p\n", mali_set_hw_event);
++ for (i = FIRST_HW_COUNTER; i <= LAST_HW_COUNTER; i++) {
++ mali_set_hw_event(i, 0xFFFFFFFF);
++ }
++
++ symbol_put(_mali_profiling_set_event);
++ } else {
++ printk("gator: mali offline _mali_profiling_set_event symbol not found\n");
++ }
++
++ /* Generic control interface for Mali DDK. */
++ mali_control = symbol_get(_mali_profiling_control);
++
++ if (mali_control) {
++ pr_debug("gator: mali offline _mali_profiling_control symbol @ %p\n", mali_control);
++
++ /* Reset the DDK state - disable counter collection */
++ mali_control(SW_COUNTER_ENABLE, 0);
++
++ mali_control(FBDUMP_CONTROL_ENABLE, 0);
++
++ symbol_put(_mali_profiling_control);
++ } else {
++ printk("gator: mali offline _mali_profiling_control symbol not found\n");
++ }
++
++ if (mali_get_counters) {
++ symbol_put(_mali_profiling_get_counters);
++ }
++
++ if (mali_get_l2_counters) {
++ symbol_put(_mali_profiling_get_l2_counters);
++ }
++}
++
++static int start(void)
++{
++ // register tracepoints
++ if (GATOR_REGISTER_TRACE(mali_hw_counter)) {
++ printk("gator: mali_hw_counter tracepoint failed to activate\n");
++ return -1;
++ }
++
++#if GATOR_MALI_INTERFACE_STYLE == 1
++ /* None. */
++#elif GATOR_MALI_INTERFACE_STYLE == 2
++ /* For patched Mali driver. */
++ if (GATOR_REGISTER_TRACE(mali_sw_counter)) {
++ printk("gator: mali_sw_counter tracepoint failed to activate\n");
++ return -1;
++ }
++#elif GATOR_MALI_INTERFACE_STYLE >= 3
++ /* For Mali drivers with built-in support. */
++ if (GATOR_REGISTER_TRACE(mali_sw_counters)) {
++ printk("gator: mali_sw_counters tracepoint failed to activate\n");
++ return -1;
++ }
++#else
++#error Unknown GATOR_MALI_INTERFACE_STYLE option.
++#endif
++
++ trace_registered = 1;
++
++ mali_counter_initialize();
++ return 0;
++}
++
++static void stop(void)
++{
++ unsigned int cnt;
++
++ pr_debug("gator: mali stop\n");
++
++ if (trace_registered) {
++ GATOR_UNREGISTER_TRACE(mali_hw_counter);
++
++#if GATOR_MALI_INTERFACE_STYLE == 1
++ /* None. */
++#elif GATOR_MALI_INTERFACE_STYLE == 2
++ /* For patched Mali driver. */
++ GATOR_UNREGISTER_TRACE(mali_sw_counter);
++#elif GATOR_MALI_INTERFACE_STYLE >= 3
++ /* For Mali drivers with built-in support. */
++ GATOR_UNREGISTER_TRACE(mali_sw_counters);
++#else
++#error Unknown GATOR_MALI_INTERFACE_STYLE option.
++#endif
++
++ pr_debug("gator: mali timeline tracepoint deactivated\n");
++
++ trace_registered = 0;
++ }
++
++ for (cnt = 0; cnt < NUMBER_OF_EVENTS; cnt++) {
++ counter_enabled[cnt] = 0;
++ counter_event[cnt] = 0;
++ counter_address[cnt] = NULL;
++ }
++
++ mali_counter_deinitialize();
++}
++
++static void dump_counters(unsigned int from_counter, unsigned int to_counter, unsigned int *len)
++{
++ unsigned int counter_id;
++
++ for (counter_id = from_counter; counter_id <= to_counter; counter_id++) {
++ if (counter_enabled[counter_id]) {
++ counter_dump[(*len)++] = counter_key[counter_id];
++ counter_dump[(*len)++] = counter_data[counter_id];
++
++ counter_data[counter_id] = 0;
++ }
++ }
++}
++
++static int read(int **buffer)
++{
++ int len = 0;
++
++ if (!on_primary_core())
++ return 0;
++
++ // Read the L2 C0 and C1 here.
++ if (n_l2_cores > 0 && is_any_counter_enabled(COUNTER_L2_0_C0, COUNTER_L2_0_C0 + (2 * n_l2_cores))) {
++ unsigned int unavailable_l2_caches = 0;
++ _mali_profiling_l2_counter_values cache_values;
++ unsigned int cache_id;
++ struct _mali_profiling_core_counters *per_core;
++
++ /* Poke the driver to get the counter values - older style; only one L2 cache */
++ if (mali_get_l2_counters) {
++ unavailable_l2_caches = mali_get_l2_counters(&cache_values);
++ } else if (mali_get_counters) {
++ per_core = &cache_values.cores[0];
++ mali_get_counters(&per_core->source0, &per_core->value0, &per_core->source1, &per_core->value1);
++ } else {
++ /* This should never happen, as n_l2_caches is only set > 0 if one of the above functions is found. */
++ }
++
++ /* Fill in the two cache counter values for each cache block. */
++ for (cache_id = 0; cache_id < n_l2_cores; cache_id++) {
++ unsigned int counter_id_0 = COUNTER_L2_0_C0 + (2 * cache_id);
++ unsigned int counter_id_1 = counter_id_0 + 1;
++
++ if ((1 << cache_id) & unavailable_l2_caches) {
++ continue; /* This cache is unavailable (powered-off, possibly). */
++ }
++
++ per_core = &cache_values.cores[cache_id];
++
++ if (counter_enabled[counter_id_0]) {
++ // Calculate and save src0's counter val0
++ counter_dump[len++] = counter_key[counter_id_0];
++ counter_dump[len++] = get_difference(per_core->value0, counter_prev[counter_id_0]);
++ }
++
++ if (counter_enabled[counter_id_1]) {
++ // Calculate and save src1's counter val1
++ counter_dump[len++] = counter_key[counter_id_1];
++ counter_dump[len++] = get_difference(per_core->value1, counter_prev[counter_id_1]);
++ }
++
++ // Save the previous values for the counters.
++ counter_prev[counter_id_0] = per_core->value0;
++ counter_prev[counter_id_1] = per_core->value1;
++ }
++ }
++
++ /* Process other (non-timeline) counters. */
++ dump_counters(COUNTER_VP_0_C0, COUNTER_VP_0_C0 + (2 * n_vp_cores) - 1, &len);
++ dump_counters(COUNTER_FP_0_C0, COUNTER_FP_0_C0 + (2 * n_fp_cores) - 1, &len);
++
++ dump_counters(FIRST_SW_COUNTER, LAST_SW_COUNTER, &len);
++
++#ifdef DVFS_REPORTED_BY_DDK
++ {
++ int cnt;
++ /*
++ * Add in the voltage and frequency counters if enabled. Note that, since these are
++ * actually passed as events, the counter value should not be cleared.
++ */
++ cnt = COUNTER_FREQUENCY;
++ if (counter_enabled[cnt]) {
++ counter_dump[len++] = counter_key[cnt];
++ counter_dump[len++] = counter_data[cnt];
++ }
++
++ cnt = COUNTER_VOLTAGE;
++ if (counter_enabled[cnt]) {
++ counter_dump[len++] = counter_key[cnt];
++ counter_dump[len++] = counter_data[cnt];
++ }
++ }
++#endif
++
++ if (buffer) {
++ *buffer = (int *)counter_dump;
++ }
++
++ return len;
++}
++
++static struct gator_interface gator_events_mali_interface = {
++ .create_files = create_files,
++ .start = start,
++ .stop = stop,
++ .read = read,
++};
++
++extern void gator_events_mali_log_dvfs_event(unsigned int frequency_mhz, unsigned int voltage_mv)
++{
++#ifdef DVFS_REPORTED_BY_DDK
++ counter_data[COUNTER_FREQUENCY] = frequency_mhz;
++ counter_data[COUNTER_VOLTAGE] = voltage_mv;
++#endif
++}
++
++int gator_events_mali_init(void)
++{
++ unsigned int cnt;
++
++ pr_debug("gator: mali init\n");
++
++ for (cnt = 0; cnt < NUMBER_OF_EVENTS; cnt++) {
++ counter_enabled[cnt] = 0;
++ counter_event[cnt] = 0;
++ counter_key[cnt] = gator_events_get_key();
++ counter_address[cnt] = NULL;
++ counter_data[cnt] = 0;
++ }
++
++ trace_registered = 0;
++
++ return gator_events_install(&gator_events_mali_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_mali_4xx.h linux-linaro-stable-mx6/drivers/gator/gator_events_mali_4xx.h
+--- linux-3.10.30.orig/drivers/gator/gator_events_mali_4xx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_mali_4xx.h 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,18 @@
++/**
++ * Copyright (C) ARM Limited 2011-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++/*
++ * Header contains common definitions for the Mali-4xx processors.
++ */
++#if !defined(GATOR_EVENTS_MALI_4xx_H)
++#define GATOR_EVENTS_MALI_4xx_H
++
++extern void gator_events_mali_log_dvfs_event(unsigned int d0, unsigned int d1);
++
++#endif /* GATOR_EVENTS_MALI_4xx_H */
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_mali_common.c linux-linaro-stable-mx6/drivers/gator/gator_events_mali_common.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_mali_common.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_mali_common.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,81 @@
++/**
++ * Copyright (C) ARM Limited 2012-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++#include "gator_events_mali_common.h"
++
++static u32 gator_mali_get_id(void)
++{
++ return MALI_SUPPORT;
++}
++
++extern const char *gator_mali_get_mali_name(void)
++{
++ u32 id = gator_mali_get_id();
++
++ switch (id) {
++ case MALI_T6xx:
++ return "Mali-T6xx";
++ case MALI_4xx:
++ return "Mali-4xx";
++ default:
++ pr_debug("gator: Mali-T6xx: unknown Mali ID (%d)\n", id);
++ return "Mali-Unknown";
++ }
++}
++
++extern int gator_mali_create_file_system(const char *mali_name, const char *event_name, struct super_block *sb, struct dentry *root, mali_counter *counter, unsigned long *event)
++{
++ int err;
++ char buf[255];
++ struct dentry *dir;
++
++ /* If the counter name is empty ignore it */
++ if (strlen(event_name) != 0) {
++ /* Set up the filesystem entry for this event. */
++ snprintf(buf, sizeof(buf), "ARM_%s_%s", mali_name, event_name);
++
++ dir = gatorfs_mkdir(sb, root, buf);
++
++ if (dir == NULL) {
++ pr_debug("gator: Mali-T6xx: error creating file system for: %s (%s)", event_name, buf);
++ return -1;
++ }
++
++ err = gatorfs_create_ulong(sb, dir, "enabled", &counter->enabled);
++ if (err != 0) {
++ pr_debug("gator: Mali-T6xx: error calling gatorfs_create_ulong for: %s (%s)", event_name, buf);
++ return -1;
++ }
++ err = gatorfs_create_ro_ulong(sb, dir, "key", &counter->key);
++ if (err != 0) {
++ pr_debug("gator: Mali-T6xx: error calling gatorfs_create_ro_ulong for: %s (%s)", event_name, buf);
++ return -1;
++ }
++ if (event != NULL) {
++ err = gatorfs_create_ulong(sb, dir, "event", event);
++ if (err != 0) {
++ pr_debug("gator: Mali-T6xx: error calling gatorfs_create_ro_ulong for: %s (%s)", event_name, buf);
++ return -1;
++ }
++ }
++ }
++
++ return 0;
++}
++
++extern void gator_mali_initialise_counters(mali_counter counters[], unsigned int n_counters)
++{
++ unsigned int cnt;
++
++ for (cnt = 0; cnt < n_counters; cnt++) {
++ mali_counter *counter = &counters[cnt];
++
++ counter->key = gator_events_get_key();
++ counter->enabled = 0;
++ }
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_mali_common.h linux-linaro-stable-mx6/drivers/gator/gator_events_mali_common.h
+--- linux-3.10.30.orig/drivers/gator/gator_events_mali_common.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_mali_common.h 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,86 @@
++/**
++ * Copyright (C) ARM Limited 2012-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#if !defined(GATOR_EVENTS_MALI_COMMON_H)
++#define GATOR_EVENTS_MALI_COMMON_H
++
++#include "gator.h"
++
++#include <linux/module.h>
++#include <linux/time.h>
++#include <linux/math64.h>
++#include <linux/slab.h>
++#include <asm/io.h>
++
++/* Device codes for each known GPU */
++#define MALI_4xx (0x0b07)
++#define MALI_T6xx (0x0056)
++
++/* Ensure that MALI_SUPPORT has been defined to something. */
++#ifndef MALI_SUPPORT
++#error MALI_SUPPORT not defined!
++#endif
++
++/* Values for the supported activity event types */
++#define ACTIVITY_START (1)
++#define ACTIVITY_STOP (2)
++
++/*
++ * Runtime state information for a counter.
++ */
++typedef struct {
++ unsigned long key; /* 'key' (a unique id set by gatord and returned by gator.ko) */
++ unsigned long enabled; /* counter enable state */
++} mali_counter;
++
++/*
++ * Mali-4xx
++ */
++typedef int mali_profiling_set_event_type(unsigned int, int);
++typedef void mali_profiling_control_type(unsigned int, unsigned int);
++typedef void mali_profiling_get_counters_type(unsigned int *, unsigned int *, unsigned int *, unsigned int *);
++
++/*
++ * Driver entry points for functions called directly by gator.
++ */
++extern int _mali_profiling_set_event(unsigned int, int);
++extern void _mali_profiling_control(unsigned int, unsigned int);
++extern void _mali_profiling_get_counters(unsigned int *, unsigned int *, unsigned int *, unsigned int *);
++
++/**
++ * Returns a name which identifies the GPU type (eg Mali-4xx, Mali-T6xx).
++ *
++ * @return The name as a constant string.
++ */
++extern const char *gator_mali_get_mali_name(void);
++
++/**
++ * Creates a filesystem entry under /dev/gator relating to the specified event name and key, and
++ * associate the key/enable values with this entry point.
++ *
++ * @param mali_name A name related to the type of GPU, obtained from a call to gator_mali_get_mali_name()
++ * @param event_name The name of the event.
++ * @param sb Linux super block
++ * @param root Directory under which the entry will be created.
++ * @param counter_key Ptr to location which will be associated with the counter key.
++ * @param counter_enabled Ptr to location which will be associated with the counter enable state.
++ *
++ * @return 0 if entry point was created, non-zero if not.
++ */
++extern int gator_mali_create_file_system(const char *mali_name, const char *event_name, struct super_block *sb, struct dentry *root, mali_counter *counter, unsigned long *event);
++
++/**
++ * Initializes the counter array.
++ *
++ * @param keys The array of counters
++ * @param n_counters The number of entries in each of the arrays.
++ */
++extern void gator_mali_initialise_counters(mali_counter counters[], unsigned int n_counters);
++
++#endif /* GATOR_EVENTS_MALI_COMMON_H */
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_mali_t6xx.c linux-linaro-stable-mx6/drivers/gator/gator_events_mali_t6xx.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_mali_t6xx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_mali_t6xx.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,560 @@
++/**
++ * Copyright (C) ARM Limited 2011-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include "gator.h"
++
++#include <linux/module.h>
++#include <linux/time.h>
++#include <linux/math64.h>
++#include <linux/slab.h>
++#include <asm/io.h>
++
++#include "linux/mali_linux_trace.h"
++
++#include "gator_events_mali_common.h"
++
++/*
++ * Check that the MALI_SUPPORT define is set to one of the allowable device codes.
++ */
++#if (MALI_SUPPORT != MALI_T6xx)
++#error MALI_SUPPORT set to an invalid device code: expecting MALI_T6xx
++#endif
++
++/* Counters for Mali-T6xx:
++ *
++ * - Timeline events
++ * They are tracepoints, but instead of reporting a number they report a START/STOP event.
++ * They are reported in Streamline as number of microseconds while that particular counter was active.
++ *
++ * - SW counters
++ * They are tracepoints reporting a particular number.
++ * They are accumulated in sw_counter_data array until they are passed to Streamline, then they are zeroed.
++ *
++ * - Accumulators
++ * They are the same as software counters but their value is not zeroed.
++ */
++
++/* Timeline (start/stop) activity */
++static const char *timeline_event_names[] = {
++ "PM_SHADER_0",
++ "PM_SHADER_1",
++ "PM_SHADER_2",
++ "PM_SHADER_3",
++ "PM_SHADER_4",
++ "PM_SHADER_5",
++ "PM_SHADER_6",
++ "PM_SHADER_7",
++ "PM_TILER_0",
++ "PM_L2_0",
++ "PM_L2_1",
++ "MMU_AS_0",
++ "MMU_AS_1",
++ "MMU_AS_2",
++ "MMU_AS_3"
++};
++
++enum {
++ PM_SHADER_0 = 0,
++ PM_SHADER_1,
++ PM_SHADER_2,
++ PM_SHADER_3,
++ PM_SHADER_4,
++ PM_SHADER_5,
++ PM_SHADER_6,
++ PM_SHADER_7,
++ PM_TILER_0,
++ PM_L2_0,
++ PM_L2_1,
++ MMU_AS_0,
++ MMU_AS_1,
++ MMU_AS_2,
++ MMU_AS_3
++};
++/* The number of shader blocks in the enum above */
++#define NUM_PM_SHADER (8)
++
++/* Software Counters */
++static const char *software_counter_names[] = {
++ "MMU_PAGE_FAULT_0",
++ "MMU_PAGE_FAULT_1",
++ "MMU_PAGE_FAULT_2",
++ "MMU_PAGE_FAULT_3"
++};
++
++enum {
++ MMU_PAGE_FAULT_0 = 0,
++ MMU_PAGE_FAULT_1,
++ MMU_PAGE_FAULT_2,
++ MMU_PAGE_FAULT_3
++};
++
++/* Software Counters */
++static const char *accumulators_names[] = {
++ "TOTAL_ALLOC_PAGES"
++};
++
++enum {
++ TOTAL_ALLOC_PAGES = 0
++};
++
++#define FIRST_TIMELINE_EVENT (0)
++#define NUMBER_OF_TIMELINE_EVENTS (sizeof(timeline_event_names) / sizeof(timeline_event_names[0]))
++#define FIRST_SOFTWARE_COUNTER (FIRST_TIMELINE_EVENT + NUMBER_OF_TIMELINE_EVENTS)
++#define NUMBER_OF_SOFTWARE_COUNTERS (sizeof(software_counter_names) / sizeof(software_counter_names[0]))
++#define FIRST_ACCUMULATOR (FIRST_SOFTWARE_COUNTER + NUMBER_OF_SOFTWARE_COUNTERS)
++#define NUMBER_OF_ACCUMULATORS (sizeof(accumulators_names) / sizeof(accumulators_names[0]))
++#define FILMSTRIP (NUMBER_OF_TIMELINE_EVENTS + NUMBER_OF_SOFTWARE_COUNTERS + NUMBER_OF_ACCUMULATORS)
++#define NUMBER_OF_EVENTS (NUMBER_OF_TIMELINE_EVENTS + NUMBER_OF_SOFTWARE_COUNTERS + NUMBER_OF_ACCUMULATORS + 1)
++
++/*
++ * gatorfs variables for counter enable state
++ */
++static mali_counter counters[NUMBER_OF_EVENTS];
++static unsigned long filmstrip_event;
++
++/* An array used to return the data we recorded
++ * as key,value pairs hence the *2
++ */
++static unsigned long counter_dump[NUMBER_OF_EVENTS * 2];
++
++/*
++ * Array holding counter start times (in ns) for each counter. A zero here
++ * indicates that the activity monitored by this counter is not running.
++ */
++static struct timespec timeline_event_starttime[NUMBER_OF_TIMELINE_EVENTS];
++
++/* The data we have recorded */
++static unsigned int timeline_data[NUMBER_OF_TIMELINE_EVENTS];
++static unsigned int sw_counter_data[NUMBER_OF_SOFTWARE_COUNTERS];
++static unsigned int accumulators_data[NUMBER_OF_ACCUMULATORS];
++
++/* Hold the previous timestamp, used to calculate the sample interval. */
++static struct timespec prev_timestamp;
++
++/**
++ * Returns the timespan (in microseconds) between the two specified timestamps.
++ *
++ * @param start Ptr to the start timestamp
++ * @param end Ptr to the end timestamp
++ *
++ * @return Number of microseconds between the two timestamps (can be negative if start follows end).
++ */
++static inline long get_duration_us(const struct timespec *start, const struct timespec *end)
++{
++ long event_duration_us = (end->tv_nsec - start->tv_nsec) / 1000;
++ event_duration_us += (end->tv_sec - start->tv_sec) * 1000000;
++
++ return event_duration_us;
++}
++
++static void record_timeline_event(unsigned int timeline_index, unsigned int type)
++{
++ struct timespec event_timestamp;
++ struct timespec *event_start = &timeline_event_starttime[timeline_index];
++
++ switch (type) {
++ case ACTIVITY_START:
++ /* Get the event time... */
++ getnstimeofday(&event_timestamp);
++
++ /* Remember the start time if the activity is not already started */
++ if (event_start->tv_sec == 0) {
++ *event_start = event_timestamp; /* Structure copy */
++ }
++ break;
++
++ case ACTIVITY_STOP:
++ /* if the counter was started... */
++ if (event_start->tv_sec != 0) {
++ /* Get the event time... */
++ getnstimeofday(&event_timestamp);
++
++ /* Accumulate the duration in us */
++ timeline_data[timeline_index] += get_duration_us(event_start, &event_timestamp);
++
++ /* Reset the start time to indicate the activity is stopped. */
++ event_start->tv_sec = 0;
++ }
++ break;
++
++ default:
++ /* Other activity events are ignored. */
++ break;
++ }
++}
++
++/*
++ * Documentation about the following tracepoints is in mali_linux_trace.h
++ */
++
++GATOR_DEFINE_PROBE(mali_pm_status, TP_PROTO(unsigned int event_id, unsigned long long value))
++{
++#define SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */
++#define TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */
++#define L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
++#define BIT_AT(value, pos) ((value >> pos) & 1)
++
++ static unsigned long long previous_shader_bitmask = 0;
++ static unsigned long long previous_tiler_bitmask = 0;
++ static unsigned long long previous_l2_bitmask = 0;
++
++ switch (event_id) {
++ case SHADER_PRESENT_LO:
++ {
++ unsigned long long changed_bitmask = previous_shader_bitmask ^ value;
++ int pos;
++
++ for (pos = 0; pos < NUM_PM_SHADER; ++pos) {
++ if (BIT_AT(changed_bitmask, pos)) {
++ record_timeline_event(PM_SHADER_0 + pos, BIT_AT(value, pos) ? ACTIVITY_START : ACTIVITY_STOP);
++ }
++ }
++
++ previous_shader_bitmask = value;
++ break;
++ }
++
++ case TILER_PRESENT_LO:
++ {
++ unsigned long long changed = previous_tiler_bitmask ^ value;
++
++ if (BIT_AT(changed, 0)) {
++ record_timeline_event(PM_TILER_0, BIT_AT(value, 0) ? ACTIVITY_START : ACTIVITY_STOP);
++ }
++
++ previous_tiler_bitmask = value;
++ break;
++ }
++
++ case L2_PRESENT_LO:
++ {
++ unsigned long long changed = previous_l2_bitmask ^ value;
++
++ if (BIT_AT(changed, 0)) {
++ record_timeline_event(PM_L2_0, BIT_AT(value, 0) ? ACTIVITY_START : ACTIVITY_STOP);
++ }
++ if (BIT_AT(changed, 4)) {
++ record_timeline_event(PM_L2_1, BIT_AT(value, 4) ? ACTIVITY_START : ACTIVITY_STOP);
++ }
++
++ previous_l2_bitmask = value;
++ break;
++ }
++
++ default:
++ /* No other blocks are supported at present */
++ break;
++ }
++
++#undef SHADER_PRESENT_LO
++#undef TILER_PRESENT_LO
++#undef L2_PRESENT_LO
++#undef BIT_AT
++}
++
++GATOR_DEFINE_PROBE(mali_page_fault_insert_pages, TP_PROTO(int event_id, unsigned long value))
++{
++ /* We add to the previous since we may receive many tracepoints in one sample period */
++ sw_counter_data[MMU_PAGE_FAULT_0 + event_id] += value;
++}
++
++GATOR_DEFINE_PROBE(mali_mmu_as_in_use, TP_PROTO(int event_id))
++{
++ record_timeline_event(MMU_AS_0 + event_id, ACTIVITY_START);
++}
++
++GATOR_DEFINE_PROBE(mali_mmu_as_released, TP_PROTO(int event_id))
++{
++ record_timeline_event(MMU_AS_0 + event_id, ACTIVITY_STOP);
++}
++
++GATOR_DEFINE_PROBE(mali_total_alloc_pages_change, TP_PROTO(long long int event_id))
++{
++ accumulators_data[TOTAL_ALLOC_PAGES] = event_id;
++}
++
++static int create_files(struct super_block *sb, struct dentry *root)
++{
++ int event;
++ /*
++ * Create the filesystem for all events
++ */
++ int counter_index = 0;
++ const char *mali_name = gator_mali_get_mali_name();
++ mali_profiling_control_type *mali_control;
++
++ for (event = FIRST_TIMELINE_EVENT; event < FIRST_TIMELINE_EVENT + NUMBER_OF_TIMELINE_EVENTS; event++) {
++ if (gator_mali_create_file_system(mali_name, timeline_event_names[counter_index], sb, root, &counters[event], NULL) != 0) {
++ return -1;
++ }
++ counter_index++;
++ }
++ counter_index = 0;
++ for (event = FIRST_SOFTWARE_COUNTER; event < FIRST_SOFTWARE_COUNTER + NUMBER_OF_SOFTWARE_COUNTERS; event++) {
++ if (gator_mali_create_file_system(mali_name, software_counter_names[counter_index], sb, root, &counters[event], NULL) != 0) {
++ return -1;
++ }
++ counter_index++;
++ }
++ counter_index = 0;
++ for (event = FIRST_ACCUMULATOR; event < FIRST_ACCUMULATOR + NUMBER_OF_ACCUMULATORS; event++) {
++ if (gator_mali_create_file_system(mali_name, accumulators_names[counter_index], sb, root, &counters[event], NULL) != 0) {
++ return -1;
++ }
++ counter_index++;
++ }
++
++ mali_control = symbol_get(_mali_profiling_control);
++ if (mali_control) {
++ if (gator_mali_create_file_system(mali_name, "Filmstrip_cnt0", sb, root, &counters[FILMSTRIP], &filmstrip_event) != 0) {
++ return -1;
++ }
++ symbol_put(_mali_profiling_control);
++ }
++
++ return 0;
++}
++
++static int register_tracepoints(void)
++{
++ if (GATOR_REGISTER_TRACE(mali_pm_status)) {
++ pr_debug("gator: Mali-T6xx: mali_pm_status tracepoint failed to activate\n");
++ return 0;
++ }
++
++ if (GATOR_REGISTER_TRACE(mali_page_fault_insert_pages)) {
++ pr_debug("gator: Mali-T6xx: mali_page_fault_insert_pages tracepoint failed to activate\n");
++ return 0;
++ }
++
++ if (GATOR_REGISTER_TRACE(mali_mmu_as_in_use)) {
++ pr_debug("gator: Mali-T6xx: mali_mmu_as_in_use tracepoint failed to activate\n");
++ return 0;
++ }
++
++ if (GATOR_REGISTER_TRACE(mali_mmu_as_released)) {
++ pr_debug("gator: Mali-T6xx: mali_mmu_as_released tracepoint failed to activate\n");
++ return 0;
++ }
++
++ if (GATOR_REGISTER_TRACE(mali_total_alloc_pages_change)) {
++ pr_debug("gator: Mali-T6xx: mali_total_alloc_pages_change tracepoint failed to activate\n");
++ return 0;
++ }
++
++ pr_debug("gator: Mali-T6xx: start\n");
++ pr_debug("gator: Mali-T6xx: mali_pm_status probe is at %p\n", &probe_mali_pm_status);
++ pr_debug("gator: Mali-T6xx: mali_page_fault_insert_pages probe is at %p\n", &probe_mali_page_fault_insert_pages);
++ pr_debug("gator: Mali-T6xx: mali_mmu_as_in_use probe is at %p\n", &probe_mali_mmu_as_in_use);
++ pr_debug("gator: Mali-T6xx: mali_mmu_as_released probe is at %p\n", &probe_mali_mmu_as_released);
++ pr_debug("gator: Mali-T6xx: mali_total_alloc_pages_change probe is at %p\n", &probe_mali_total_alloc_pages_change);
++
++ return 1;
++}
++
++static int start(void)
++{
++ unsigned int cnt;
++ mali_profiling_control_type *mali_control;
++
++ /* Clean all data for the next capture */
++ for (cnt = 0; cnt < NUMBER_OF_TIMELINE_EVENTS; cnt++) {
++ timeline_event_starttime[cnt].tv_sec = timeline_event_starttime[cnt].tv_nsec = 0;
++ timeline_data[cnt] = 0;
++ }
++
++ for (cnt = 0; cnt < NUMBER_OF_SOFTWARE_COUNTERS; cnt++) {
++ sw_counter_data[cnt] = 0;
++ }
++
++ for (cnt = 0; cnt < NUMBER_OF_ACCUMULATORS; cnt++) {
++ accumulators_data[cnt] = 0;
++ }
++
++ /* Register tracepoints */
++ if (register_tracepoints() == 0) {
++ return -1;
++ }
++
++ /* Generic control interface for Mali DDK. */
++ mali_control = symbol_get(_mali_profiling_control);
++ if (mali_control) {
++ /* The event attribute in the XML file keeps the actual frame rate. */
++ unsigned int enabled = counters[FILMSTRIP].enabled ? 1 : 0;
++ unsigned int rate = filmstrip_event & 0xff;
++ unsigned int resize_factor = (filmstrip_event >> 8) & 0xff;
++
++ pr_debug("gator: mali online _mali_profiling_control symbol @ %p\n", mali_control);
++
++#define FBDUMP_CONTROL_ENABLE (1)
++#define FBDUMP_CONTROL_RATE (2)
++#define FBDUMP_CONTROL_RESIZE_FACTOR (4)
++ mali_control(FBDUMP_CONTROL_ENABLE, enabled);
++ mali_control(FBDUMP_CONTROL_RATE, rate);
++ mali_control(FBDUMP_CONTROL_RESIZE_FACTOR, resize_factor);
++
++ pr_debug("gator: sent mali_control enabled=%d, rate=%d, resize_factor=%d\n", enabled, rate, resize_factor);
++
++ symbol_put(_mali_profiling_control);
++ } else {
++ printk("gator: mali online _mali_profiling_control symbol not found\n");
++ }
++
++ /*
++ * Set the first timestamp for calculating the sample interval. The first interval could be quite long,
++ * since it will be the time between 'start' and the first 'read'.
++ * This means that timeline values will be divided by a big number for the first sample.
++ */
++ getnstimeofday(&prev_timestamp);
++
++ return 0;
++}
++
++static void stop(void)
++{
++ mali_profiling_control_type *mali_control;
++
++ pr_debug("gator: Mali-T6xx: stop\n");
++
++ /*
++ * It is safe to unregister traces even if they were not successfully
++ * registered, so no need to check.
++ */
++ GATOR_UNREGISTER_TRACE(mali_pm_status);
++ pr_debug("gator: Mali-T6xx: mali_pm_status tracepoint deactivated\n");
++
++ GATOR_UNREGISTER_TRACE(mali_page_fault_insert_pages);
++ pr_debug("gator: Mali-T6xx: mali_page_fault_insert_pages tracepoint deactivated\n");
++
++ GATOR_UNREGISTER_TRACE(mali_mmu_as_in_use);
++ pr_debug("gator: Mali-T6xx: mali_mmu_as_in_use tracepoint deactivated\n");
++
++ GATOR_UNREGISTER_TRACE(mali_mmu_as_released);
++ pr_debug("gator: Mali-T6xx: mali_mmu_as_released tracepoint deactivated\n");
++
++ GATOR_UNREGISTER_TRACE(mali_total_alloc_pages_change);
++ pr_debug("gator: Mali-T6xx: mali_total_alloc_pages_change tracepoint deactivated\n");
++
++ /* Generic control interface for Mali DDK. */
++ mali_control = symbol_get(_mali_profiling_control);
++ if (mali_control) {
++ pr_debug("gator: mali offline _mali_profiling_control symbol @ %p\n", mali_control);
++
++ mali_control(FBDUMP_CONTROL_ENABLE, 0);
++
++ symbol_put(_mali_profiling_control);
++ } else {
++ printk("gator: mali offline _mali_profiling_control symbol not found\n");
++ }
++}
++
++static int read(int **buffer)
++{
++ int cnt;
++ int len = 0;
++ long sample_interval_us = 0;
++ struct timespec read_timestamp;
++
++ if (!on_primary_core()) {
++ return 0;
++ }
++
++ /* Get the start of this sample period. */
++ getnstimeofday(&read_timestamp);
++
++ /*
++ * Calculate the sample interval if the previous sample time is valid.
++ * We use tv_sec since it will not be 0.
++ */
++ if (prev_timestamp.tv_sec != 0) {
++ sample_interval_us = get_duration_us(&prev_timestamp, &read_timestamp);
++ }
++
++ /* Structure copy. Update the previous timestamp. */
++ prev_timestamp = read_timestamp;
++
++ /*
++ * Report the timeline counters (ACTIVITY_START/STOP)
++ */
++ for (cnt = FIRST_TIMELINE_EVENT; cnt < (FIRST_TIMELINE_EVENT + NUMBER_OF_TIMELINE_EVENTS); cnt++) {
++ mali_counter *counter = &counters[cnt];
++ if (counter->enabled) {
++ const int index = cnt - FIRST_TIMELINE_EVENT;
++ unsigned int value;
++
++ /* If the activity is still running, reset its start time to the start of this sample period
++ * to correct the count. Add the time up to the end of the sample onto the count. */
++ if (timeline_event_starttime[index].tv_sec != 0) {
++ const long event_duration = get_duration_us(&timeline_event_starttime[index], &read_timestamp);
++ timeline_data[index] += event_duration;
++ timeline_event_starttime[index] = read_timestamp; /* Activity is still running. */
++ }
++
++ if (sample_interval_us != 0) {
++ /* Convert the counter to a percent-of-sample value */
++ value = (timeline_data[index] * 100) / sample_interval_us;
++ } else {
++ pr_debug("gator: Mali-T6xx: setting value to zero\n");
++ value = 0;
++ }
++
++ /* Clear the counter value ready for the next sample. */
++ timeline_data[index] = 0;
++
++ counter_dump[len++] = counter->key;
++ counter_dump[len++] = value;
++ }
++ }
++
++ /* Report the software counters */
++ for (cnt = FIRST_SOFTWARE_COUNTER; cnt < (FIRST_SOFTWARE_COUNTER + NUMBER_OF_SOFTWARE_COUNTERS); cnt++) {
++ const mali_counter *counter = &counters[cnt];
++ if (counter->enabled) {
++ const int index = cnt - FIRST_SOFTWARE_COUNTER;
++ counter_dump[len++] = counter->key;
++ counter_dump[len++] = sw_counter_data[index];
++ /* Set the value to zero for the next time */
++ sw_counter_data[index] = 0;
++ }
++ }
++
++ /* Report the accumulators */
++ for (cnt = FIRST_ACCUMULATOR; cnt < (FIRST_ACCUMULATOR + NUMBER_OF_ACCUMULATORS); cnt++) {
++ const mali_counter *counter = &counters[cnt];
++ if (counter->enabled) {
++ const int index = cnt - FIRST_ACCUMULATOR;
++ counter_dump[len++] = counter->key;
++ counter_dump[len++] = accumulators_data[index];
++ /* Do not zero the accumulator */
++ }
++ }
++
++ /* Update the buffer */
++ if (buffer) {
++ *buffer = (int *)counter_dump;
++ }
++
++ return len;
++}
++
++static struct gator_interface gator_events_mali_t6xx_interface = {
++ .create_files = create_files,
++ .start = start,
++ .stop = stop,
++ .read = read
++};
++
++extern int gator_events_mali_t6xx_init(void)
++{
++ pr_debug("gator: Mali-T6xx: sw_counters init\n");
++
++ gator_mali_initialise_counters(counters, NUMBER_OF_EVENTS);
++
++ return gator_events_install(&gator_events_mali_t6xx_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_mali_t6xx_hw.c linux-linaro-stable-mx6/drivers/gator/gator_events_mali_t6xx_hw.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_mali_t6xx_hw.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_mali_t6xx_hw.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,784 @@
++/**
++ * Copyright (C) ARM Limited 2012-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include "gator.h"
++
++#include <linux/module.h>
++#include <linux/time.h>
++#include <linux/math64.h>
++#include <linux/slab.h>
++#include <asm/io.h>
++
++/* Mali T6xx DDK includes */
++#include "linux/mali_linux_trace.h"
++#include "kbase/src/common/mali_kbase.h"
++#include "kbase/src/linux/mali_kbase_mem_linux.h"
++
++#include "gator_events_mali_common.h"
++
++/* If API version is not specified then assume API version 1. */
++#ifndef MALI_DDK_GATOR_API_VERSION
++#define MALI_DDK_GATOR_API_VERSION 1
++#endif
++
++#if (MALI_DDK_GATOR_API_VERSION != 1) && (MALI_DDK_GATOR_API_VERSION != 2)
++#error MALI_DDK_GATOR_API_VERSION is invalid (must be 1 for r1/r2 DDK, or 2 for r3 DDK).
++#endif
++
++/*
++ * Mali-T6xx
++ */
++typedef struct kbase_device *kbase_find_device_type(int);
++typedef kbase_context *kbase_create_context_type(kbase_device *);
++typedef void kbase_destroy_context_type(kbase_context *);
++
++#if MALI_DDK_GATOR_API_VERSION == 1
++typedef void *kbase_va_alloc_type(kbase_context *, u32);
++typedef void kbase_va_free_type(kbase_context *, void *);
++#elif MALI_DDK_GATOR_API_VERSION == 2
++typedef void *kbase_va_alloc_type(kbase_context *, u32, kbase_hwc_dma_mapping * handle);
++typedef void kbase_va_free_type(kbase_context *, kbase_hwc_dma_mapping * handle);
++#endif
++
++typedef mali_error kbase_instr_hwcnt_enable_type(kbase_context *, kbase_uk_hwcnt_setup *);
++typedef mali_error kbase_instr_hwcnt_disable_type(kbase_context *);
++typedef mali_error kbase_instr_hwcnt_clear_type(kbase_context *);
++typedef mali_error kbase_instr_hwcnt_dump_irq_type(kbase_context *);
++typedef mali_bool kbase_instr_hwcnt_dump_complete_type(kbase_context *, mali_bool *);
++
++static kbase_find_device_type *kbase_find_device_symbol;
++static kbase_create_context_type *kbase_create_context_symbol;
++static kbase_va_alloc_type *kbase_va_alloc_symbol;
++static kbase_instr_hwcnt_enable_type *kbase_instr_hwcnt_enable_symbol;
++static kbase_instr_hwcnt_clear_type *kbase_instr_hwcnt_clear_symbol;
++static kbase_instr_hwcnt_dump_irq_type *kbase_instr_hwcnt_dump_irq_symbol;
++static kbase_instr_hwcnt_dump_complete_type *kbase_instr_hwcnt_dump_complete_symbol;
++static kbase_instr_hwcnt_disable_type *kbase_instr_hwcnt_disable_symbol;
++static kbase_va_free_type *kbase_va_free_symbol;
++static kbase_destroy_context_type *kbase_destroy_context_symbol;
++
++static long shader_present_low = 0;
++
++/** The interval between reads, in ns.
++ *
++ * Earlier we introduced
++ * a 'hold off for 1ms after last read' to resolve MIDBASE-2178 and MALINE-724.
++ * However, the 1ms hold off is too long if no context switches occur as there is a race
++ * between this value and the tick of the read clock in gator which is also 1ms. If we 'miss' the
++ * current read, the counter values are effectively 'spread' over 2ms and the values seen are half
++ * what they should be (since Streamline averages over sample time). In the presence of context switches
++ * this spread can vary and markedly affect the counters. Currently there is no 'proper' solution to
++ * this, but empirically we have found that reducing the minimum read interval to 950us causes the
++ * counts to be much more stable.
++ */
++static const int READ_INTERVAL_NSEC = 950000;
++
++#if GATOR_TEST
++#include "gator_events_mali_t6xx_hw_test.c"
++#endif
++
++/* Blocks for HW counters */
++enum {
++ JM_BLOCK = 0,
++ TILER_BLOCK,
++ SHADER_BLOCK,
++ MMU_BLOCK
++};
++
++/* Counters for Mali-T6xx:
++ *
++ * - HW counters, 4 blocks
++ * For HW counters we need strings to create /dev/gator/events files.
++ * Enums are not needed because the position of the HW name in the array is the same
++ * of the corresponding value in the received block of memory.
++ * HW counters are requested by calculating a bitmask, passed then to the driver.
++ * Every millisecond a HW counters dump is requested, and if the previous has been completed they are read.
++ */
++
++/* Hardware Counters */
++static const char *const hardware_counter_names[] = {
++ /* Job Manager */
++ "",
++ "",
++ "",
++ "",
++ "MESSAGES_SENT",
++ "MESSAGES_RECEIVED",
++ "GPU_ACTIVE", /* 6 */
++ "IRQ_ACTIVE",
++ "JS0_JOBS",
++ "JS0_TASKS",
++ "JS0_ACTIVE",
++ "",
++ "JS0_WAIT_READ",
++ "JS0_WAIT_ISSUE",
++ "JS0_WAIT_DEPEND",
++ "JS0_WAIT_FINISH",
++ "JS1_JOBS",
++ "JS1_TASKS",
++ "JS1_ACTIVE",
++ "",
++ "JS1_WAIT_READ",
++ "JS1_WAIT_ISSUE",
++ "JS1_WAIT_DEPEND",
++ "JS1_WAIT_FINISH",
++ "JS2_JOBS",
++ "JS2_TASKS",
++ "JS2_ACTIVE",
++ "",
++ "JS2_WAIT_READ",
++ "JS2_WAIT_ISSUE",
++ "JS2_WAIT_DEPEND",
++ "JS2_WAIT_FINISH",
++ "JS3_JOBS",
++ "JS3_TASKS",
++ "JS3_ACTIVE",
++ "",
++ "JS3_WAIT_READ",
++ "JS3_WAIT_ISSUE",
++ "JS3_WAIT_DEPEND",
++ "JS3_WAIT_FINISH",
++ "JS4_JOBS",
++ "JS4_TASKS",
++ "JS4_ACTIVE",
++ "",
++ "JS4_WAIT_READ",
++ "JS4_WAIT_ISSUE",
++ "JS4_WAIT_DEPEND",
++ "JS4_WAIT_FINISH",
++ "JS5_JOBS",
++ "JS5_TASKS",
++ "JS5_ACTIVE",
++ "",
++ "JS5_WAIT_READ",
++ "JS5_WAIT_ISSUE",
++ "JS5_WAIT_DEPEND",
++ "JS5_WAIT_FINISH",
++ "JS6_JOBS",
++ "JS6_TASKS",
++ "JS6_ACTIVE",
++ "",
++ "JS6_WAIT_READ",
++ "JS6_WAIT_ISSUE",
++ "JS6_WAIT_DEPEND",
++ "JS6_WAIT_FINISH",
++
++ /*Tiler */
++ "",
++ "",
++ "",
++ "JOBS_PROCESSED",
++ "TRIANGLES",
++ "QUADS",
++ "POLYGONS",
++ "POINTS",
++ "LINES",
++ "VCACHE_HIT",
++ "VCACHE_MISS",
++ "FRONT_FACING",
++ "BACK_FACING",
++ "PRIM_VISIBLE",
++ "PRIM_CULLED",
++ "PRIM_CLIPPED",
++ "LEVEL0",
++ "LEVEL1",
++ "LEVEL2",
++ "LEVEL3",
++ "LEVEL4",
++ "LEVEL5",
++ "LEVEL6",
++ "LEVEL7",
++ "COMMAND_1",
++ "COMMAND_2",
++ "COMMAND_3",
++ "COMMAND_4",
++ "COMMAND_4_7",
++ "COMMAND_8_15",
++ "COMMAND_16_63",
++ "COMMAND_64",
++ "COMPRESS_IN",
++ "COMPRESS_OUT",
++ "COMPRESS_FLUSH",
++ "TIMESTAMPS",
++ "PCACHE_HIT",
++ "PCACHE_MISS",
++ "PCACHE_LINE",
++ "PCACHE_STALL",
++ "WRBUF_HIT",
++ "WRBUF_MISS",
++ "WRBUF_LINE",
++ "WRBUF_PARTIAL",
++ "WRBUF_STALL",
++ "ACTIVE",
++ "LOADING_DESC",
++ "INDEX_WAIT",
++ "INDEX_RANGE_WAIT",
++ "VERTEX_WAIT",
++ "PCACHE_WAIT",
++ "WRBUF_WAIT",
++ "BUS_READ",
++ "BUS_WRITE",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "UTLB_STALL",
++ "UTLB_REPLAY_MISS",
++ "UTLB_REPLAY_FULL",
++ "UTLB_NEW_MISS",
++ "UTLB_HIT",
++
++ /* Shader Core */
++ "",
++ "",
++ "",
++ "SHADER_CORE_ACTIVE",
++ "FRAG_ACTIVE",
++ "FRAG_PRIMATIVES",
++ "FRAG_PRIMATIVES_DROPPED",
++ "FRAG_CYCLE_DESC",
++ "FRAG_CYCLES_PLR",
++ "FRAG_CYCLES_VERT",
++ "FRAG_CYCLES_TRISETUP",
++ "FRAG_CYCLES_RAST",
++ "FRAG_THREADS",
++ "FRAG_DUMMY_THREADS",
++ "FRAG_QUADS_RAST",
++ "FRAG_QUADS_EZS_TEST",
++ "FRAG_QUADS_EZS_KILLED",
++ "FRAG_QUADS_LZS_TEST",
++ "FRAG_QUADS_LZS_KILLED",
++ "FRAG_CYCLE_NO_TILE",
++ "FRAG_NUM_TILES",
++ "FRAG_TRANS_ELIM",
++ "COMPUTE_ACTIVE",
++ "COMPUTE_TASKS",
++ "COMPUTE_THREADS",
++ "COMPUTE_CYCLES_DESC",
++ "TRIPIPE_ACTIVE",
++ "ARITH_WORDS",
++ "ARITH_CYCLES_REG",
++ "ARITH_CYCLES_L0",
++ "ARITH_FRAG_DEPEND",
++ "LS_WORDS",
++ "LS_ISSUES",
++ "LS_RESTARTS",
++ "LS_REISSUES_MISS",
++ "LS_REISSUES_VD",
++ "LS_REISSUE_ATTRIB_MISS",
++ "LS_NO_WB",
++ "TEX_WORDS",
++ "TEX_BUBBLES",
++ "TEX_WORDS_L0",
++ "TEX_WORDS_DESC",
++ "TEX_THREADS",
++ "TEX_RECIRC_FMISS",
++ "TEX_RECIRC_DESC",
++ "TEX_RECIRC_MULTI",
++ "TEX_RECIRC_PMISS",
++ "TEX_RECIRC_CONF",
++ "LSC_READ_HITS",
++ "LSC_READ_MISSES",
++ "LSC_WRITE_HITS",
++ "LSC_WRITE_MISSES",
++ "LSC_ATOMIC_HITS",
++ "LSC_ATOMIC_MISSES",
++ "LSC_LINE_FETCHES",
++ "LSC_DIRTY_LINE",
++ "LSC_SNOOPS",
++ "AXI_TLB_STALL",
++ "AXI_TLB_MIESS",
++ "AXI_TLB_TRANSACTION",
++ "LS_TLB_MISS",
++ "LS_TLB_HIT",
++ "AXI_BEATS_READ",
++ "AXI_BEATS_WRITTEN",
++
++ /*L2 and MMU */
++ "",
++ "",
++ "",
++ "",
++ "MMU_HIT",
++ "MMU_NEW_MISS",
++ "MMU_REPLAY_FULL",
++ "MMU_REPLAY_MISS",
++ "MMU_TABLE_WALK",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "UTLB_HIT",
++ "UTLB_NEW_MISS",
++ "UTLB_REPLAY_FULL",
++ "UTLB_REPLAY_MISS",
++ "UTLB_STALL",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "",
++ "L2_WRITE_BEATS",
++ "L2_READ_BEATS",
++ "L2_ANY_LOOKUP",
++ "L2_READ_LOOKUP",
++ "L2_SREAD_LOOKUP",
++ "L2_READ_REPLAY",
++ "L2_READ_SNOOP",
++ "L2_READ_HIT",
++ "L2_CLEAN_MISS",
++ "L2_WRITE_LOOKUP",
++ "L2_SWRITE_LOOKUP",
++ "L2_WRITE_REPLAY",
++ "L2_WRITE_SNOOP",
++ "L2_WRITE_HIT",
++ "L2_EXT_READ_FULL",
++ "L2_EXT_READ_HALF",
++ "L2_EXT_WRITE_FULL",
++ "L2_EXT_WRITE_HALF",
++ "L2_EXT_READ",
++ "L2_EXT_READ_LINE",
++ "L2_EXT_WRITE",
++ "L2_EXT_WRITE_LINE",
++ "L2_EXT_WRITE_SMALL",
++ "L2_EXT_BARRIER",
++ "L2_EXT_AR_STALL",
++ "L2_EXT_R_BUF_FULL",
++ "L2_EXT_RD_BUF_FULL",
++ "L2_EXT_R_RAW",
++ "L2_EXT_W_STALL",
++ "L2_EXT_W_BUF_FULL",
++ "L2_EXT_R_W_HAZARD",
++ "L2_TAG_HAZARD",
++ "L2_SNOOP_FULL",
++ "L2_REPLAY_FULL"
++};
++
++#define NUMBER_OF_HARDWARE_COUNTERS (sizeof(hardware_counter_names) / sizeof(hardware_counter_names[0]))
++
++#define GET_HW_BLOCK(c) (((c) >> 6) & 0x3)
++#define GET_COUNTER_OFFSET(c) ((c) & 0x3f)
++
++/* Memory to dump hardware counters into */
++static void *kernel_dump_buffer;
++
++#if MALI_DDK_GATOR_API_VERSION == 2
++/* DMA state used to manage lifetime of the buffer */
++kbase_hwc_dma_mapping kernel_dump_buffer_handle;
++#endif
++
++/* kbase context and device */
++static kbase_context *kbcontext = NULL;
++static struct kbase_device *kbdevice = NULL;
++
++/*
++ * The following function has no external prototype in older DDK revisions. When the DDK
++ * is updated then this should be removed.
++ */
++struct kbase_device *kbase_find_device(int minor);
++
++static volatile bool kbase_device_busy = false;
++static unsigned int num_hardware_counters_enabled;
++
++/*
++ * gatorfs variables for counter enable state
++ */
++static mali_counter counters[NUMBER_OF_HARDWARE_COUNTERS];
++
++/* An array used to return the data we recorded
++ * as key,value pairs hence the *2
++ */
++static unsigned long counter_dump[NUMBER_OF_HARDWARE_COUNTERS * 2];
++
++#define SYMBOL_GET(FUNCTION, ERROR_COUNT) \
++ if(FUNCTION ## _symbol) \
++ { \
++ printk("gator: mali " #FUNCTION " symbol was already registered\n"); \
++ (ERROR_COUNT)++; \
++ } \
++ else \
++ { \
++ FUNCTION ## _symbol = symbol_get(FUNCTION); \
++ if(! FUNCTION ## _symbol) \
++ { \
++ printk("gator: mali online " #FUNCTION " symbol not found\n"); \
++ (ERROR_COUNT)++; \
++ } \
++ }
++
++#define SYMBOL_CLEANUP(FUNCTION) \
++ if(FUNCTION ## _symbol) \
++ { \
++ symbol_put(FUNCTION); \
++ FUNCTION ## _symbol = NULL; \
++ }
++
++/**
++ * Execute symbol_get for all the Mali symbols and check for success.
++ * @return the number of symbols not loaded.
++ */
++static int init_symbols(void)
++{
++ int error_count = 0;
++ SYMBOL_GET(kbase_find_device, error_count);
++ SYMBOL_GET(kbase_create_context, error_count);
++ SYMBOL_GET(kbase_va_alloc, error_count);
++ SYMBOL_GET(kbase_instr_hwcnt_enable, error_count);
++ SYMBOL_GET(kbase_instr_hwcnt_clear, error_count);
++ SYMBOL_GET(kbase_instr_hwcnt_dump_irq, error_count);
++ SYMBOL_GET(kbase_instr_hwcnt_dump_complete, error_count);
++ SYMBOL_GET(kbase_instr_hwcnt_disable, error_count);
++ SYMBOL_GET(kbase_va_free, error_count);
++ SYMBOL_GET(kbase_destroy_context, error_count);
++
++ return error_count;
++}
++
++/**
++ * Execute symbol_put for all the registered Mali symbols.
++ */
++static void clean_symbols(void)
++{
++ SYMBOL_CLEANUP(kbase_find_device);
++ SYMBOL_CLEANUP(kbase_create_context);
++ SYMBOL_CLEANUP(kbase_va_alloc);
++ SYMBOL_CLEANUP(kbase_instr_hwcnt_enable);
++ SYMBOL_CLEANUP(kbase_instr_hwcnt_clear);
++ SYMBOL_CLEANUP(kbase_instr_hwcnt_dump_irq);
++ SYMBOL_CLEANUP(kbase_instr_hwcnt_dump_complete);
++ SYMBOL_CLEANUP(kbase_instr_hwcnt_disable);
++ SYMBOL_CLEANUP(kbase_va_free);
++ SYMBOL_CLEANUP(kbase_destroy_context);
++}
++
++/**
++ * Determines whether a read should take place
++ * @param current_time The current time, obtained from getnstimeofday()
++ * @param prev_time_s The number of seconds at the previous read attempt.
++ * @param next_read_time_ns The time (in ns) when the next read should be allowed.
++ *
++ * Note that this function has been separated out here to allow it to be tested.
++ */
++static int is_read_scheduled(const struct timespec *current_time, u32 *prev_time_s, s32 *next_read_time_ns)
++{
++ /* If the current ns count rolls over a second, roll the next read time too. */
++ if (current_time->tv_sec != *prev_time_s) {
++ *next_read_time_ns = *next_read_time_ns - NSEC_PER_SEC;
++ }
++
++ /* Abort the read if the next read time has not arrived. */
++ if (current_time->tv_nsec < *next_read_time_ns) {
++ return 0;
++ }
++
++ /* Set the next read some fixed time after this one, and update the read timestamp. */
++ *next_read_time_ns = current_time->tv_nsec + READ_INTERVAL_NSEC;
++
++ *prev_time_s = current_time->tv_sec;
++ return 1;
++}
++
++static int start(void)
++{
++ kbase_uk_hwcnt_setup setup;
++ mali_error err;
++ int cnt;
++ u16 bitmask[] = { 0, 0, 0, 0 };
++ unsigned long long shadersPresent = 0;
++
++ /* Setup HW counters */
++ num_hardware_counters_enabled = 0;
++
++ if (NUMBER_OF_HARDWARE_COUNTERS != 256) {
++ pr_debug("Unexpected number of hardware counters defined: expecting 256, got %d\n", NUMBER_OF_HARDWARE_COUNTERS);
++ }
++
++ /* Calculate enable bitmasks based on counters_enabled array */
++ for (cnt = 0; cnt < NUMBER_OF_HARDWARE_COUNTERS; cnt++) {
++ const mali_counter *counter = &counters[cnt];
++ if (counter->enabled) {
++ int block = GET_HW_BLOCK(cnt);
++ int enable_bit = GET_COUNTER_OFFSET(cnt) / 4;
++ bitmask[block] |= (1 << enable_bit);
++ pr_debug("gator: Mali-T6xx: hardware counter %s selected [%d]\n", hardware_counter_names[cnt], cnt);
++ num_hardware_counters_enabled++;
++ }
++ }
++
++ /* Create a kbase context for HW counters */
++ if (num_hardware_counters_enabled > 0) {
++ if (init_symbols() > 0) {
++ clean_symbols();
++ /* No Mali driver code entrypoints found - not a fault. */
++ return 0;
++ }
++
++ kbdevice = kbase_find_device_symbol(-1);
++
++ /* If we already got a context, fail */
++ if (kbcontext) {
++ pr_debug("gator: Mali-T6xx: error context already present\n");
++ goto out;
++ }
++
++ /* kbcontext will only be valid after all the Mali symbols are loaded successfully */
++ kbcontext = kbase_create_context_symbol(kbdevice);
++ if (!kbcontext) {
++ pr_debug("gator: Mali-T6xx: error creating kbase context\n");
++ goto out;
++ }
++
++
++ /* See if we can get the number of shader cores */
++ shadersPresent = kbdevice->shader_present_bitmap;
++ shader_present_low = (unsigned long)shadersPresent;
++
++ /*
++ * The amount of memory needed to store the dump (bytes)
++ * DUMP_SIZE = number of core groups
++ * * number of blocks (always 8 for midgard)
++ * * number of counters per block (always 64 for midgard)
++ * * number of bytes per counter (always 4 in midgard)
++ * For a Mali-T6xx with a single core group = 1 * 8 * 64 * 4 = 2048
++ * For a Mali-T6xx with a dual core group = 2 * 8 * 64 * 4 = 4096
++ */
++#if MALI_DDK_GATOR_API_VERSION == 1
++ kernel_dump_buffer = kbase_va_alloc_symbol(kbcontext, 4096);
++#elif MALI_DDK_GATOR_API_VERSION == 2
++ kernel_dump_buffer = kbase_va_alloc_symbol(kbcontext, 4096, &kernel_dump_buffer_handle);
++#endif
++ if (!kernel_dump_buffer) {
++ pr_debug("gator: Mali-T6xx: error trying to allocate va\n");
++ goto destroy_context;
++ }
++
++ setup.dump_buffer = (uintptr_t)kernel_dump_buffer;
++ setup.jm_bm = bitmask[JM_BLOCK];
++ setup.tiler_bm = bitmask[TILER_BLOCK];
++ setup.shader_bm = bitmask[SHADER_BLOCK];
++ setup.mmu_l2_bm = bitmask[MMU_BLOCK];
++ /* These counters do not exist on Mali-T60x */
++ setup.l3_cache_bm = 0;
++
++ /* Use kbase API to enable hardware counters and provide dump buffer */
++ err = kbase_instr_hwcnt_enable_symbol(kbcontext, &setup);
++ if (err != MALI_ERROR_NONE) {
++ pr_debug("gator: Mali-T6xx: can't setup hardware counters\n");
++ goto free_buffer;
++ }
++ pr_debug("gator: Mali-T6xx: hardware counters enabled\n");
++ kbase_instr_hwcnt_clear_symbol(kbcontext);
++ pr_debug("gator: Mali-T6xx: hardware counters cleared \n");
++
++ kbase_device_busy = false;
++ }
++
++ return 0;
++
++free_buffer:
++#if MALI_DDK_GATOR_API_VERSION == 1
++ kbase_va_free_symbol(kbcontext, kernel_dump_buffer);
++#elif MALI_DDK_GATOR_API_VERSION == 2
++ kbase_va_free_symbol(kbcontext, &kernel_dump_buffer_handle);
++#endif
++
++destroy_context:
++ kbase_destroy_context_symbol(kbcontext);
++
++out:
++ clean_symbols();
++ return -1;
++}
++
++static void stop(void)
++{
++ unsigned int cnt;
++ kbase_context *temp_kbcontext;
++
++ pr_debug("gator: Mali-T6xx: stop\n");
++
++ /* Set all counters as disabled */
++ for (cnt = 0; cnt < NUMBER_OF_HARDWARE_COUNTERS; cnt++) {
++ counters[cnt].enabled = 0;
++ }
++
++ /* Destroy the context for HW counters */
++ if (num_hardware_counters_enabled > 0 && kbcontext != NULL) {
++ /*
++ * Set the global variable to NULL before destroying it, because
++ * other function will check this before using it.
++ */
++ temp_kbcontext = kbcontext;
++ kbcontext = NULL;
++
++ kbase_instr_hwcnt_disable_symbol(temp_kbcontext);
++
++#if MALI_DDK_GATOR_API_VERSION == 1
++ kbase_va_free_symbol(temp_kbcontext, kernel_dump_buffer);
++#elif MALI_DDK_GATOR_API_VERSION == 2
++ kbase_va_free_symbol(temp_kbcontext, &kernel_dump_buffer_handle);
++#endif
++
++ kbase_destroy_context_symbol(temp_kbcontext);
++
++ pr_debug("gator: Mali-T6xx: hardware counters stopped\n");
++
++ clean_symbols();
++ }
++}
++
++static int read(int **buffer)
++{
++ int cnt;
++ int len = 0;
++ u32 value = 0;
++ mali_bool success;
++
++ struct timespec current_time;
++ static u32 prev_time_s = 0;
++ static s32 next_read_time_ns = 0;
++
++ if (!on_primary_core()) {
++ return 0;
++ }
++
++ getnstimeofday(&current_time);
++
++ /*
++ * Discard reads unless a respectable time has passed. This reduces the load on the GPU without sacrificing
++ * accuracy on the Streamline display.
++ */
++ if (!is_read_scheduled(&current_time, &prev_time_s, &next_read_time_ns)) {
++ return 0;
++ }
++
++ /*
++ * Report the HW counters
++ * Only process hardware counters if at least one of the hardware counters is enabled.
++ */
++ if (num_hardware_counters_enabled > 0) {
++ const unsigned int vithar_blocks[] = {
++ 0x700, /* VITHAR_JOB_MANAGER, Block 0 */
++ 0x400, /* VITHAR_TILER, Block 1 */
++ 0x000, /* VITHAR_SHADER_CORE, Block 2 */
++ 0x500 /* VITHAR_MEMORY_SYSTEM, Block 3 */
++ };
++
++ if (!kbcontext) {
++ return -1;
++ }
++
++ /* Mali symbols can be called safely since a kbcontext is valid */
++ if (kbase_instr_hwcnt_dump_complete_symbol(kbcontext, &success) == MALI_TRUE) {
++ kbase_device_busy = false;
++
++ if (success == MALI_TRUE) {
++ /* Cycle through hardware counters and accumulate totals */
++ for (cnt = 0; cnt < NUMBER_OF_HARDWARE_COUNTERS; cnt++) {
++ const mali_counter *counter = &counters[cnt];
++ if (counter->enabled) {
++ const int block = GET_HW_BLOCK(cnt);
++ const int counter_offset = GET_COUNTER_OFFSET(cnt);
++
++ const char* block_base_address = (char*)kernel_dump_buffer + vithar_blocks[block];
++
++ /* If counter belongs to shader block need to take into account all cores */
++ if (block == SHADER_BLOCK) {
++ int i = 0;
++ int shader_core_count = 0;
++ value = 0;
++
++ for (i = 0; i < 4; i++) {
++ if ((shader_present_low >> i) & 1) {
++ value += *((u32*) (block_base_address + (0x100 * i)) + counter_offset);
++ shader_core_count++;
++ }
++ }
++
++ for (i = 0; i < 4; i++) {
++ if((shader_present_low >> (i+4)) & 1) {
++ value += *((u32*)(block_base_address + (0x100 * i) + 0x800) + counter_offset);
++ shader_core_count++;
++ }
++ }
++
++ /* Need to total by number of cores to produce an average */
++ if (shader_core_count != 0) {
++ value /= shader_core_count;
++ }
++ } else {
++ value = *((u32*)block_base_address + counter_offset);
++ }
++
++ counter_dump[len++] = counter->key;
++ counter_dump[len++] = value;
++ }
++ }
++ }
++ }
++
++ if (!kbase_device_busy) {
++ kbase_device_busy = true;
++ kbase_instr_hwcnt_dump_irq_symbol(kbcontext);
++ }
++ }
++
++ /* Update the buffer */
++ if (buffer) {
++ *buffer = (int *)counter_dump;
++ }
++
++ return len;
++}
++
++static int create_files(struct super_block *sb, struct dentry *root)
++{
++ unsigned int event;
++ /*
++ * Create the filesystem for all events
++ */
++ int counter_index = 0;
++ const char *mali_name = gator_mali_get_mali_name();
++
++ for (event = 0; event < NUMBER_OF_HARDWARE_COUNTERS; event++) {
++ if (gator_mali_create_file_system(mali_name, hardware_counter_names[counter_index], sb, root, &counters[event], NULL) != 0)
++ return -1;
++ counter_index++;
++ }
++
++ return 0;
++}
++
++static struct gator_interface gator_events_mali_t6xx_interface = {
++ .create_files = create_files,
++ .start = start,
++ .stop = stop,
++ .read = read
++};
++
++int gator_events_mali_t6xx_hw_init(void)
++{
++ pr_debug("gator: Mali-T6xx: sw_counters init\n");
++
++#if GATOR_TEST
++ test_all_is_read_scheduled();
++#endif
++
++ gator_mali_initialise_counters(counters, NUMBER_OF_HARDWARE_COUNTERS);
++
++ return gator_events_install(&gator_events_mali_t6xx_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_mali_t6xx_hw_test.c linux-linaro-stable-mx6/drivers/gator/gator_events_mali_t6xx_hw_test.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_mali_t6xx_hw_test.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_mali_t6xx_hw_test.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,55 @@
++/**
++ * Copyright (C) ARM Limited 2012-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++/**
++ * Test functions for mali_t600_hw code.
++ */
++
++static int is_read_scheduled(const struct timespec *current_time, u32 *prev_time_s, s32 *next_read_time_ns);
++
++static int test_is_read_scheduled(u32 s, u32 ns, u32 prev_s, s32 next_ns, int expected_result, s32 expected_next_ns)
++{
++ struct timespec current_time;
++ u32 prev_time_s = prev_s;
++ s32 next_read_time_ns = next_ns;
++
++ current_time.tv_sec = s;
++ current_time.tv_nsec = ns;
++
++ if (is_read_scheduled(&current_time, &prev_time_s, &next_read_time_ns) != expected_result) {
++ printk("Failed do_read(%u, %u, %u, %d): expected %d\n", s, ns, prev_s, next_ns, expected_result);
++ return 0;
++ }
++
++ if (next_read_time_ns != expected_next_ns) {
++ printk("Failed: next_read_ns expected=%d, actual=%d\n", expected_next_ns, next_read_time_ns);
++ return 0;
++ }
++
++ return 1;
++}
++
++static void test_all_is_read_scheduled(void)
++{
++ const int HIGHEST_NS = 999999999;
++ int n_tests_passed = 0;
++
++ printk("gator: running tests on %s\n", __FILE__);
++
++ n_tests_passed += test_is_read_scheduled(0, 0, 0, 0, 1, READ_INTERVAL_NSEC); /* Null time */
++ n_tests_passed += test_is_read_scheduled(100, 1000, 0, 0, 1, READ_INTERVAL_NSEC + 1000); /* Initial values */
++
++ n_tests_passed += test_is_read_scheduled(100, HIGHEST_NS, 100, HIGHEST_NS + 500, 0, HIGHEST_NS + 500);
++ n_tests_passed += test_is_read_scheduled(101, 0001, 100, HIGHEST_NS + 500, 0, HIGHEST_NS + 500 - NSEC_PER_SEC);
++ n_tests_passed += test_is_read_scheduled(101, 600, 100, HIGHEST_NS + 500 - NSEC_PER_SEC, 1, 600 + READ_INTERVAL_NSEC);
++
++ n_tests_passed += test_is_read_scheduled(101, 600, 100, HIGHEST_NS + 500, 1, 600 + READ_INTERVAL_NSEC);
++
++ printk("gator: %d tests passed\n", n_tests_passed);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_meminfo.c linux-linaro-stable-mx6/drivers/gator/gator_events_meminfo.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_meminfo.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_meminfo.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,387 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include "gator.h"
++
++#include <linux/hardirq.h>
++#include <linux/kthread.h>
++#include <linux/sched.h>
++#include <linux/semaphore.h>
++#include <linux/workqueue.h>
++#include <trace/events/kmem.h>
++
++enum {
++ MEMINFO_MEMFREE,
++ MEMINFO_MEMUSED,
++ MEMINFO_BUFFERRAM,
++ MEMINFO_TOTAL,
++};
++
++enum {
++ PROC_SIZE,
++ PROC_SHARE,
++ PROC_TEXT,
++ PROC_DATA,
++ PROC_COUNT,
++};
++
++static const char * const meminfo_names[] = {
++ "Linux_meminfo_memfree",
++ "Linux_meminfo_memused",
++ "Linux_meminfo_bufferram",
++};
++
++static const char * const proc_names[] = {
++ "Linux_proc_statm_size",
++ "Linux_proc_statm_share",
++ "Linux_proc_statm_text",
++ "Linux_proc_statm_data",
++};
++
++static bool meminfo_global_enabled;
++static ulong meminfo_enabled[MEMINFO_TOTAL];
++static ulong meminfo_keys[MEMINFO_TOTAL];
++static long long meminfo_buffer[2 * (MEMINFO_TOTAL + 2)];
++static int meminfo_length = 0;
++static bool new_data_avail;
++
++static bool proc_global_enabled;
++static ulong proc_enabled[PROC_COUNT];
++static ulong proc_keys[PROC_COUNT];
++static DEFINE_PER_CPU(long long, proc_buffer[2 * (PROC_COUNT + 3)]);
++
++static int gator_meminfo_func(void *data);
++static bool gator_meminfo_run;
++// Initialize semaphore unlocked to initialize memory values
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)
++static DECLARE_MUTEX(gator_meminfo_sem);
++#else
++static DEFINE_SEMAPHORE(gator_meminfo_sem);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
++GATOR_DEFINE_PROBE(mm_page_free_direct, TP_PROTO(struct page *page, unsigned int order))
++#else
++GATOR_DEFINE_PROBE(mm_page_free, TP_PROTO(struct page *page, unsigned int order))
++#endif
++{
++ up(&gator_meminfo_sem);
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
++GATOR_DEFINE_PROBE(mm_pagevec_free, TP_PROTO(struct page *page, int cold))
++#else
++GATOR_DEFINE_PROBE(mm_page_free_batched, TP_PROTO(struct page *page, int cold))
++#endif
++{
++ up(&gator_meminfo_sem);
++}
++
++GATOR_DEFINE_PROBE(mm_page_alloc, TP_PROTO(struct page *page, unsigned int order, gfp_t gfp_flags, int migratetype))
++{
++ up(&gator_meminfo_sem);
++}
++
++static int gator_events_meminfo_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++ int i;
++
++ for (i = 0; i < MEMINFO_TOTAL; i++) {
++ dir = gatorfs_mkdir(sb, root, meminfo_names[i]);
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &meminfo_enabled[i]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &meminfo_keys[i]);
++ }
++
++ for (i = 0; i < PROC_COUNT; ++i) {
++ dir = gatorfs_mkdir(sb, root, proc_names[i]);
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &proc_enabled[i]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &proc_keys[i]);
++ }
++
++ return 0;
++}
++
++static int gator_events_meminfo_start(void)
++{
++ int i;
++
++ new_data_avail = false;
++ meminfo_global_enabled = 0;
++ for (i = 0; i < MEMINFO_TOTAL; i++) {
++ if (meminfo_enabled[i]) {
++ meminfo_global_enabled = 1;
++ break;
++ }
++ }
++
++ proc_global_enabled = 0;
++ for (i = 0; i < PROC_COUNT; ++i) {
++ if (proc_enabled[i]) {
++ proc_global_enabled = 1;
++ break;
++ }
++ }
++ if (meminfo_enabled[MEMINFO_MEMUSED]) {
++ proc_global_enabled = 1;
++ }
++
++ if (meminfo_global_enabled == 0)
++ return 0;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
++ if (GATOR_REGISTER_TRACE(mm_page_free_direct))
++#else
++ if (GATOR_REGISTER_TRACE(mm_page_free))
++#endif
++ goto mm_page_free_exit;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
++ if (GATOR_REGISTER_TRACE(mm_pagevec_free))
++#else
++ if (GATOR_REGISTER_TRACE(mm_page_free_batched))
++#endif
++ goto mm_page_free_batched_exit;
++ if (GATOR_REGISTER_TRACE(mm_page_alloc))
++ goto mm_page_alloc_exit;
++
++ // Start worker thread
++ gator_meminfo_run = true;
++ // Since the mutex starts unlocked, memory values will be initialized
++ if (IS_ERR(kthread_run(gator_meminfo_func, NULL, "gator_meminfo")))
++ goto kthread_run_exit;
++
++ return 0;
++
++kthread_run_exit:
++ GATOR_UNREGISTER_TRACE(mm_page_alloc);
++mm_page_alloc_exit:
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
++ GATOR_UNREGISTER_TRACE(mm_pagevec_free);
++#else
++ GATOR_UNREGISTER_TRACE(mm_page_free_batched);
++#endif
++mm_page_free_batched_exit:
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
++ GATOR_UNREGISTER_TRACE(mm_page_free_direct);
++#else
++ GATOR_UNREGISTER_TRACE(mm_page_free);
++#endif
++mm_page_free_exit:
++ return -1;
++}
++
++static void gator_events_meminfo_stop(void)
++{
++ if (meminfo_global_enabled) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
++ GATOR_UNREGISTER_TRACE(mm_page_free_direct);
++ GATOR_UNREGISTER_TRACE(mm_pagevec_free);
++#else
++ GATOR_UNREGISTER_TRACE(mm_page_free);
++ GATOR_UNREGISTER_TRACE(mm_page_free_batched);
++#endif
++ GATOR_UNREGISTER_TRACE(mm_page_alloc);
++
++ // Stop worker thread
++ gator_meminfo_run = false;
++ up(&gator_meminfo_sem);
++ }
++}
++
++// Must be run in process context as the kernel function si_meminfo() can sleep
++static int gator_meminfo_func(void *data)
++{
++ struct sysinfo info;
++ int i, len;
++ unsigned long long value;
++
++ for (;;) {
++ if (down_killable(&gator_meminfo_sem)) {
++ break;
++ }
++
++ // Eat up any pending events
++ while (!down_trylock(&gator_meminfo_sem));
++
++ if (!gator_meminfo_run) {
++ break;
++ }
++
++ meminfo_length = len = 0;
++
++ si_meminfo(&info);
++ for (i = 0; i < MEMINFO_TOTAL; i++) {
++ if (meminfo_enabled[i]) {
++ switch (i) {
++ case MEMINFO_MEMFREE:
++ value = info.freeram * PAGE_SIZE;
++ break;
++ case MEMINFO_MEMUSED:
++ // pid -1 means system wide
++ meminfo_buffer[len++] = 1;
++ meminfo_buffer[len++] = -1;
++ // Emit value
++ meminfo_buffer[len++] = meminfo_keys[MEMINFO_MEMUSED];
++ meminfo_buffer[len++] = (info.totalram - info.freeram) * PAGE_SIZE;
++ // Clear pid
++ meminfo_buffer[len++] = 1;
++ meminfo_buffer[len++] = 0;
++ continue;
++ case MEMINFO_BUFFERRAM:
++ value = info.bufferram * PAGE_SIZE;
++ break;
++ default:
++ value = 0;
++ break;
++ }
++ meminfo_buffer[len++] = meminfo_keys[i];
++ meminfo_buffer[len++] = value;
++ }
++ }
++
++ meminfo_length = len;
++ new_data_avail = true;
++ }
++
++ return 0;
++}
++
++static int gator_events_meminfo_read(long long **buffer)
++{
++ if (!on_primary_core() || !meminfo_global_enabled)
++ return 0;
++
++ if (!new_data_avail)
++ return 0;
++
++ new_data_avail = false;
++
++ if (buffer)
++ *buffer = meminfo_buffer;
++
++ return meminfo_length;
++}
++
++static int gator_events_meminfo_read_proc(long long **buffer, struct task_struct *task)
++{
++ struct mm_struct *mm;
++ u64 share = 0;
++ int i;
++ long long value;
++ int len = 0;
++ int cpu = get_physical_cpu();
++ long long *buf = per_cpu(proc_buffer, cpu);
++
++ if (!proc_global_enabled) {
++ return 0;
++ }
++
++ // Collect the memory stats of the process instead of the thread
++ if (task->group_leader != NULL) {
++ task = task->group_leader;
++ }
++
++ // get_task_mm/mmput is not needed in this context because the task and it's mm are required as part of the sched_switch
++ mm = task->mm;
++ if (mm == NULL) {
++ return 0;
++ }
++
++ // Derived from task_statm in fs/proc/task_mmu.c
++ if (meminfo_enabled[MEMINFO_MEMUSED] || proc_enabled[PROC_SHARE]) {
++ share = get_mm_counter(mm,
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 32)
++ file_rss
++#else
++ MM_FILEPAGES
++#endif
++ );
++ }
++
++ // key of 1 indicates a pid
++ buf[len++] = 1;
++ buf[len++] = task->pid;
++
++ for (i = 0; i < PROC_COUNT; ++i) {
++ if (proc_enabled[i]) {
++ switch (i) {
++ case PROC_SIZE:
++ value = mm->total_vm;
++ break;
++ case PROC_SHARE:
++ value = share;
++ break;
++ case PROC_TEXT:
++ value = (PAGE_ALIGN(mm->end_code) - (mm->start_code & PAGE_MASK)) >> PAGE_SHIFT;
++ break;
++ case PROC_DATA:
++ value = mm->total_vm - mm->shared_vm;
++ break;
++ }
++
++ buf[len++] = proc_keys[i];
++ buf[len++] = value * PAGE_SIZE;
++ }
++ }
++
++ if (meminfo_enabled[MEMINFO_MEMUSED]) {
++ value = share + get_mm_counter(mm,
++#if LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 32)
++ anon_rss
++#else
++ MM_ANONPAGES
++#endif
++ );
++ // Send resident for this pid
++ buf[len++] = meminfo_keys[MEMINFO_MEMUSED];
++ buf[len++] = value * PAGE_SIZE;
++ }
++
++ // Clear pid
++ buf[len++] = 1;
++ buf[len++] = 0;
++
++ if (buffer)
++ *buffer = buf;
++
++ return len;
++}
++
++static struct gator_interface gator_events_meminfo_interface = {
++ .create_files = gator_events_meminfo_create_files,
++ .start = gator_events_meminfo_start,
++ .stop = gator_events_meminfo_stop,
++ .read64 = gator_events_meminfo_read,
++ .read_proc = gator_events_meminfo_read_proc,
++};
++
++int gator_events_meminfo_init(void)
++{
++ int i;
++
++ meminfo_global_enabled = 0;
++ for (i = 0; i < MEMINFO_TOTAL; i++) {
++ meminfo_enabled[i] = 0;
++ meminfo_keys[i] = gator_events_get_key();
++ }
++
++ proc_global_enabled = 0;
++ for (i = 0; i < PROC_COUNT; ++i) {
++ proc_enabled[i] = 0;
++ proc_keys[i] = gator_events_get_key();
++ }
++
++ return gator_events_install(&gator_events_meminfo_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_mmapped.c linux-linaro-stable-mx6/drivers/gator/gator_events_mmapped.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_mmapped.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_mmapped.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,209 @@
++/*
++ * Example events provider
++ *
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Similar entries to those below must be present in the events.xml file.
++ * To add them to the events.xml, create an events-mmap.xml with the
++ * following contents and rebuild gatord:
++ *
++ * <counter_set name="mmapped_cnt" count="3"/>
++ * <category name="mmapped" counter_set="mmapped_cnt" per_cpu="no">
++ * <event event="0x0" title="Simulated1" name="Sine" display="maximum" average_selection="yes" description="Sort-of-sine"/>
++ * <event event="0x1" title="Simulated2" name="Triangle" display="maximum" average_selection="yes" description="Triangular wave"/>
++ * <event event="0x2" title="Simulated3" name="PWM" display="maximum" average_selection="yes" description="PWM Signal"/>
++ * </category>
++ *
++ * When adding custom events, be sure do the following
++ * - add any needed .c files to the gator driver Makefile
++ * - call gator_events_install in the events init function
++ * - add the init function to GATOR_EVENTS_LIST in gator_main.c
++ * - add a new events-*.xml file to the gator daemon and rebuild
++ */
++
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ratelimit.h>
++
++#include "gator.h"
++
++#define MMAPPED_COUNTERS_NUM 3
++
++static int mmapped_global_enabled;
++
++static struct {
++ unsigned long enabled;
++ unsigned long event;
++ unsigned long key;
++} mmapped_counters[MMAPPED_COUNTERS_NUM];
++
++static int mmapped_buffer[MMAPPED_COUNTERS_NUM * 2];
++
++static s64 prev_time;
++
++/* Adds mmapped_cntX directories and enabled, event, and key files to /dev/gator/events */
++static int gator_events_mmapped_create_files(struct super_block *sb,
++ struct dentry *root)
++{
++ int i;
++
++ for (i = 0; i < MMAPPED_COUNTERS_NUM; i++) {
++ char buf[16];
++ struct dentry *dir;
++
++ snprintf(buf, sizeof(buf), "mmapped_cnt%d", i);
++ dir = gatorfs_mkdir(sb, root, buf);
++ if (WARN_ON(!dir))
++ return -1;
++ gatorfs_create_ulong(sb, dir, "enabled",
++ &mmapped_counters[i].enabled);
++ gatorfs_create_ulong(sb, dir, "event",
++ &mmapped_counters[i].event);
++ gatorfs_create_ro_ulong(sb, dir, "key",
++ &mmapped_counters[i].key);
++ }
++
++ return 0;
++}
++
++static int gator_events_mmapped_start(void)
++{
++ int i;
++ struct timespec ts;
++
++ getnstimeofday(&ts);
++ prev_time = timespec_to_ns(&ts);
++
++ mmapped_global_enabled = 0;
++ for (i = 0; i < MMAPPED_COUNTERS_NUM; i++) {
++ if (mmapped_counters[i].enabled) {
++ mmapped_global_enabled = 1;
++ break;
++ }
++ }
++
++ return 0;
++}
++
++static void gator_events_mmapped_stop(void)
++{
++}
++
++/* This function "simulates" counters, generating values of fancy
++ * functions like sine or triangle... */
++static int mmapped_simulate(int counter, int delta_in_us)
++{
++ int result = 0;
++
++ switch (counter) {
++ case 0: /* sort-of-sine */
++ {
++ static int t = 0;
++ int x;
++
++ t += delta_in_us;
++ if (t > 2048000)
++ t = 0;
++
++ if (t % 1024000 < 512000)
++ x = 512000 - (t % 512000);
++ else
++ x = t % 512000;
++
++ result = 32 * x / 512000;
++ result = result * result;
++
++ if (t < 1024000)
++ result = 1922 - result;
++ }
++ break;
++ case 1: /* triangle */
++ {
++ static int v, d = 1;
++
++ v = v + d * delta_in_us;
++ if (v < 0) {
++ v = 0;
++ d = 1;
++ } else if (v > 1000000) {
++ v = 1000000;
++ d = -1;
++ }
++
++ result = v;
++ }
++ break;
++ case 2: /* PWM signal */
++ {
++ static int dc, x, t = 0;
++
++ t += delta_in_us;
++ if (t > 1000000)
++ t = 0;
++ if (x / 1000000 != (x + delta_in_us) / 1000000)
++ dc = (dc + 100000) % 1000000;
++ x += delta_in_us;
++
++ result = t < dc ? 0 : 10;
++ }
++ break;
++ }
++
++ return result;
++}
++
++static int gator_events_mmapped_read(int **buffer)
++{
++ int i;
++ int len = 0;
++ int delta_in_us;
++ struct timespec ts;
++ s64 time;
++
++ /* System wide counters - read from one core only */
++ if (!on_primary_core() || !mmapped_global_enabled)
++ return 0;
++
++ getnstimeofday(&ts);
++ time = timespec_to_ns(&ts);
++ delta_in_us = (int)(time - prev_time) / 1000;
++ prev_time = time;
++
++ for (i = 0; i < MMAPPED_COUNTERS_NUM; i++) {
++ if (mmapped_counters[i].enabled) {
++ mmapped_buffer[len++] = mmapped_counters[i].key;
++ mmapped_buffer[len++] =
++ mmapped_simulate(mmapped_counters[i].event,
++ delta_in_us);
++ }
++ }
++
++ if (buffer)
++ *buffer = mmapped_buffer;
++
++ return len;
++}
++
++static struct gator_interface gator_events_mmapped_interface = {
++ .create_files = gator_events_mmapped_create_files,
++ .start = gator_events_mmapped_start,
++ .stop = gator_events_mmapped_stop,
++ .read = gator_events_mmapped_read,
++};
++
++/* Must not be static! */
++int __init gator_events_mmapped_init(void)
++{
++ int i;
++
++ for (i = 0; i < MMAPPED_COUNTERS_NUM; i++) {
++ mmapped_counters[i].enabled = 0;
++ mmapped_counters[i].key = gator_events_get_key();
++ }
++
++ return gator_events_install(&gator_events_mmapped_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_net.c linux-linaro-stable-mx6/drivers/gator/gator_events_net.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_net.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_net.c 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,172 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include "gator.h"
++#include <linux/netdevice.h>
++#include <linux/hardirq.h>
++
++#define NETRX 0
++#define NETTX 1
++#define TOTALNET 2
++
++static ulong netrx_enabled;
++static ulong nettx_enabled;
++static ulong netrx_key;
++static ulong nettx_key;
++static int rx_total, tx_total;
++static ulong netPrev[TOTALNET];
++static int netGet[TOTALNET * 4];
++
++static struct timer_list net_wake_up_timer;
++
++// Must be run in process context as the kernel function dev_get_stats() can sleep
++static void get_network_stats(struct work_struct *wsptr)
++{
++ int rx = 0, tx = 0;
++ struct net_device *dev;
++
++ for_each_netdev(&init_net, dev) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)
++ const struct net_device_stats *stats = dev_get_stats(dev);
++#else
++ struct rtnl_link_stats64 temp;
++ const struct rtnl_link_stats64 *stats = dev_get_stats(dev, &temp);
++#endif
++ rx += stats->rx_bytes;
++ tx += stats->tx_bytes;
++ }
++ rx_total = rx;
++ tx_total = tx;
++}
++
++DECLARE_WORK(wq_get_stats, get_network_stats);
++
++static void net_wake_up_handler(unsigned long unused_data)
++{
++ // had to delay scheduling work as attempting to schedule work during the context switch is illegal in kernel versions 3.5 and greater
++ schedule_work(&wq_get_stats);
++}
++
++static void calculate_delta(int *rx, int *tx)
++{
++ int rx_calc, tx_calc;
++
++ rx_calc = (int)(rx_total - netPrev[NETRX]);
++ if (rx_calc < 0)
++ rx_calc = 0;
++ netPrev[NETRX] += rx_calc;
++
++ tx_calc = (int)(tx_total - netPrev[NETTX]);
++ if (tx_calc < 0)
++ tx_calc = 0;
++ netPrev[NETTX] += tx_calc;
++
++ *rx = rx_calc;
++ *tx = tx_calc;
++}
++
++static int gator_events_net_create_files(struct super_block *sb, struct dentry *root)
++{
++ // Network counters are not currently supported in RT-Preempt full because mod_timer is used
++#ifndef CONFIG_PREEMPT_RT_FULL
++ struct dentry *dir;
++
++ dir = gatorfs_mkdir(sb, root, "Linux_net_rx");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &netrx_enabled);
++ gatorfs_create_ro_ulong(sb, dir, "key", &netrx_key);
++
++ dir = gatorfs_mkdir(sb, root, "Linux_net_tx");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &nettx_enabled);
++ gatorfs_create_ro_ulong(sb, dir, "key", &nettx_key);
++#endif
++
++ return 0;
++}
++
++static int gator_events_net_start(void)
++{
++ get_network_stats(0);
++ netPrev[NETRX] = rx_total;
++ netPrev[NETTX] = tx_total;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36)
++ setup_timer(&net_wake_up_timer, net_wake_up_handler, 0);
++#else
++ setup_deferrable_timer_on_stack(&net_wake_up_timer, net_wake_up_handler, 0);
++#endif
++ return 0;
++}
++
++static void gator_events_net_stop(void)
++{
++ del_timer_sync(&net_wake_up_timer);
++ netrx_enabled = 0;
++ nettx_enabled = 0;
++}
++
++static int gator_events_net_read(int **buffer)
++{
++ int len, rx_delta, tx_delta;
++ static int last_rx_delta = 0, last_tx_delta = 0;
++
++ if (!on_primary_core())
++ return 0;
++
++ if (!netrx_enabled && !nettx_enabled)
++ return 0;
++
++ mod_timer(&net_wake_up_timer, jiffies + 1);
++
++ calculate_delta(&rx_delta, &tx_delta);
++
++ len = 0;
++ if (netrx_enabled && last_rx_delta != rx_delta) {
++ last_rx_delta = rx_delta;
++ netGet[len++] = netrx_key;
++ netGet[len++] = 0; // indicates to Streamline that rx_delta bytes were transmitted now, not since the last message
++ netGet[len++] = netrx_key;
++ netGet[len++] = rx_delta;
++ }
++
++ if (nettx_enabled && last_tx_delta != tx_delta) {
++ last_tx_delta = tx_delta;
++ netGet[len++] = nettx_key;
++ netGet[len++] = 0; // indicates to Streamline that tx_delta bytes were transmitted now, not since the last message
++ netGet[len++] = nettx_key;
++ netGet[len++] = tx_delta;
++ }
++
++ if (buffer)
++ *buffer = netGet;
++
++ return len;
++}
++
++static struct gator_interface gator_events_net_interface = {
++ .create_files = gator_events_net_create_files,
++ .start = gator_events_net_start,
++ .stop = gator_events_net_stop,
++ .read = gator_events_net_read,
++};
++
++int gator_events_net_init(void)
++{
++ netrx_key = gator_events_get_key();
++ nettx_key = gator_events_get_key();
++
++ netrx_enabled = 0;
++ nettx_enabled = 0;
++
++ return gator_events_install(&gator_events_net_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_perf_pmu.c linux-linaro-stable-mx6/drivers/gator/gator_events_perf_pmu.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_perf_pmu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_perf_pmu.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,587 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "gator.h"
++
++// gator_events_armvX.c is used for Linux 2.6.x
++#if GATOR_PERF_PMU_SUPPORT
++
++#include <linux/io.h>
++#ifdef CONFIG_OF
++#include <linux/of_address.h>
++#endif
++#include <linux/perf_event.h>
++#include <linux/slab.h>
++
++extern bool event_based_sampling;
++
++// Maximum number of per-core counters - currently reserves enough space for two full hardware PMUs for big.LITTLE
++#define CNTMAX 16
++#define CCI_400 4
++// Maximum number of uncore counters
++// + 1 for the cci-400 cycles counter
++#define UCCNT (CCI_400 + 1)
++
++// Default to 0 if unable to probe the revision which was the previous behavior
++#define DEFAULT_CCI_REVISION 0
++
++// A gator_attr is needed for every counter
++struct gator_attr {
++ // Set once in gator_events_perf_pmu_*_init - the name of the event in the gatorfs
++ char name[40];
++ // Exposed in gatorfs - set by gatord to enable this counter
++ unsigned long enabled;
++ // Set once in gator_events_perf_pmu_*_init - the perf type to use, see perf_type_id in the perf_event.h header file.
++ unsigned long type;
++ // Exposed in gatorfs - set by gatord to select the event to collect
++ unsigned long event;
++ // Exposed in gatorfs - set by gatord with the sample period to use and enable EBS for this counter
++ unsigned long count;
++ // Exposed as read only in gatorfs - set once in __attr_init as the key to use in the APC data
++ unsigned long key;
++};
++
++// Per-core counter attributes
++static struct gator_attr attrs[CNTMAX];
++// Number of initialized per-core counters
++static int attr_count;
++// Uncore counter attributes
++static struct gator_attr uc_attrs[UCCNT];
++// Number of initialized uncore counters
++static int uc_attr_count;
++
++struct gator_event {
++ int curr;
++ int prev;
++ int prev_delta;
++ bool zero;
++ struct perf_event *pevent;
++ struct perf_event_attr *pevent_attr;
++};
++
++static DEFINE_PER_CPU(struct gator_event[CNTMAX], events);
++static struct gator_event uc_events[UCCNT];
++static DEFINE_PER_CPU(int[(CNTMAX + UCCNT)*2], perf_cnt);
++
++static void gator_events_perf_pmu_stop(void);
++
++static int __create_files(struct super_block *sb, struct dentry *root, struct gator_attr *const attr)
++{
++ struct dentry *dir;
++
++ if (attr->name[0] == '\0') {
++ return 0;
++ }
++ dir = gatorfs_mkdir(sb, root, attr->name);
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &attr->enabled);
++ gatorfs_create_ulong(sb, dir, "count", &attr->count);
++ gatorfs_create_ro_ulong(sb, dir, "key", &attr->key);
++ gatorfs_create_ulong(sb, dir, "event", &attr->event);
++
++ return 0;
++}
++
++static int gator_events_perf_pmu_create_files(struct super_block *sb, struct dentry *root)
++{
++ int cnt;
++
++ for (cnt = 0; cnt < attr_count; cnt++) {
++ if (__create_files(sb, root, &attrs[cnt]) != 0) {
++ return -1;
++ }
++ }
++
++ for (cnt = 0; cnt < uc_attr_count; cnt++) {
++ if (__create_files(sb, root, &uc_attrs[cnt]) != 0) {
++ return -1;
++ }
++ }
++
++ return 0;
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
++static void ebs_overflow_handler(struct perf_event *event, int unused, struct perf_sample_data *data, struct pt_regs *regs)
++#else
++static void ebs_overflow_handler(struct perf_event *event, struct perf_sample_data *data, struct pt_regs *regs)
++#endif
++{
++ gator_backtrace_handler(regs);
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
++static void dummy_handler(struct perf_event *event, int unused, struct perf_sample_data *data, struct pt_regs *regs)
++#else
++static void dummy_handler(struct perf_event *event, struct perf_sample_data *data, struct pt_regs *regs)
++#endif
++{
++// Required as perf_event_create_kernel_counter() requires an overflow handler, even though all we do is poll
++}
++
++static int gator_events_perf_pmu_read(int **buffer);
++
++static int gator_events_perf_pmu_online(int **buffer, bool migrate)
++{
++ return gator_events_perf_pmu_read(buffer);
++}
++
++static void __online_dispatch(int cpu, bool migrate, struct gator_attr *const attr, struct gator_event *const event)
++{
++ perf_overflow_handler_t handler;
++
++ event->zero = true;
++
++ if (event->pevent != NULL || event->pevent_attr == 0 || migrate) {
++ return;
++ }
++
++ if (attr->count > 0) {
++ handler = ebs_overflow_handler;
++ } else {
++ handler = dummy_handler;
++ }
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
++ event->pevent = perf_event_create_kernel_counter(event->pevent_attr, cpu, 0, handler);
++#else
++ event->pevent = perf_event_create_kernel_counter(event->pevent_attr, cpu, 0, handler, 0);
++#endif
++ if (IS_ERR(event->pevent)) {
++ pr_debug("gator: unable to online a counter on cpu %d\n", cpu);
++ event->pevent = NULL;
++ return;
++ }
++
++ if (event->pevent->state != PERF_EVENT_STATE_ACTIVE) {
++ pr_debug("gator: inactive counter on cpu %d\n", cpu);
++ perf_event_release_kernel(event->pevent);
++ event->pevent = NULL;
++ return;
++ }
++}
++
++static void gator_events_perf_pmu_online_dispatch(int cpu, bool migrate)
++{
++ int cnt;
++
++ cpu = pcpu_to_lcpu(cpu);
++
++ for (cnt = 0; cnt < attr_count; cnt++) {
++ __online_dispatch(cpu, migrate, &attrs[cnt], &per_cpu(events, cpu)[cnt]);
++ }
++
++ if (cpu == 0) {
++ for (cnt = 0; cnt < uc_attr_count; cnt++) {
++ __online_dispatch(cpu, migrate, &uc_attrs[cnt], &uc_events[cnt]);
++ }
++ }
++}
++
++static void __offline_dispatch(int cpu, struct gator_event *const event)
++{
++ struct perf_event *pe = NULL;
++
++ if (event->pevent) {
++ pe = event->pevent;
++ event->pevent = NULL;
++ }
++
++ if (pe) {
++ perf_event_release_kernel(pe);
++ }
++}
++
++static void gator_events_perf_pmu_offline_dispatch(int cpu, bool migrate)
++{
++ int cnt;
++
++ if (migrate) {
++ return;
++ }
++ cpu = pcpu_to_lcpu(cpu);
++
++ for (cnt = 0; cnt < attr_count; cnt++) {
++ __offline_dispatch(cpu, &per_cpu(events, cpu)[cnt]);
++ }
++
++ if (cpu == 0) {
++ for (cnt = 0; cnt < uc_attr_count; cnt++) {
++ __offline_dispatch(cpu, &uc_events[cnt]);
++ }
++ }
++}
++
++static int __check_ebs(struct gator_attr *const attr)
++{
++ if (attr->count > 0) {
++ if (!event_based_sampling) {
++ event_based_sampling = true;
++ } else {
++ printk(KERN_WARNING "gator: Only one ebs counter is allowed\n");
++ return -1;
++ }
++ }
++
++ return 0;
++}
++
++static int __start(struct gator_attr *const attr, struct gator_event *const event)
++{
++ u32 size = sizeof(struct perf_event_attr);
++
++ event->pevent = NULL;
++ if (!attr->enabled) { // Skip disabled counters
++ return 0;
++ }
++
++ event->prev = 0;
++ event->curr = 0;
++ event->prev_delta = 0;
++ event->pevent_attr = kmalloc(size, GFP_KERNEL);
++ if (!event->pevent_attr) {
++ gator_events_perf_pmu_stop();
++ return -1;
++ }
++
++ memset(event->pevent_attr, 0, size);
++ event->pevent_attr->type = attr->type;
++ event->pevent_attr->size = size;
++ event->pevent_attr->config = attr->event;
++ event->pevent_attr->sample_period = attr->count;
++ event->pevent_attr->pinned = 1;
++
++ return 0;
++}
++
++static int gator_events_perf_pmu_start(void)
++{
++ int cnt, cpu;
++
++ event_based_sampling = false;
++ for (cnt = 0; cnt < attr_count; cnt++) {
++ if (__check_ebs(&attrs[cnt]) != 0) {
++ return -1;
++ }
++ }
++
++ for (cnt = 0; cnt < uc_attr_count; cnt++) {
++ if (__check_ebs(&uc_attrs[cnt]) != 0) {
++ return -1;
++ }
++ }
++
++ for_each_present_cpu(cpu) {
++ for (cnt = 0; cnt < attr_count; cnt++) {
++ if (__start(&attrs[cnt], &per_cpu(events, cpu)[cnt]) != 0) {
++ return -1;
++ }
++ }
++ }
++
++ for (cnt = 0; cnt < uc_attr_count; cnt++) {
++ if (__start(&uc_attrs[cnt], &uc_events[cnt]) != 0) {
++ return -1;
++ }
++ }
++
++ return 0;
++}
++
++static void __event_stop(struct gator_event *const event)
++{
++ if (event->pevent_attr) {
++ kfree(event->pevent_attr);
++ event->pevent_attr = NULL;
++ }
++}
++
++static void __attr_stop(struct gator_attr *const attr)
++{
++ attr->enabled = 0;
++ attr->event = 0;
++ attr->count = 0;
++}
++
++static void gator_events_perf_pmu_stop(void)
++{
++ unsigned int cnt, cpu;
++
++ for_each_present_cpu(cpu) {
++ for (cnt = 0; cnt < attr_count; cnt++) {
++ __event_stop(&per_cpu(events, cpu)[cnt]);
++ }
++ }
++
++ for (cnt = 0; cnt < uc_attr_count; cnt++) {
++ __event_stop(&uc_events[cnt]);
++ }
++
++ for (cnt = 0; cnt < attr_count; cnt++) {
++ __attr_stop(&attrs[cnt]);
++ }
++
++ for (cnt = 0; cnt < uc_attr_count; cnt++) {
++ __attr_stop(&uc_attrs[cnt]);
++ }
++}
++
++static void __read(int *const len, int cpu, struct gator_attr *const attr, struct gator_event *const event)
++{
++ int delta;
++
++ struct perf_event *const ev = event->pevent;
++ if (ev != NULL && ev->state == PERF_EVENT_STATE_ACTIVE) {
++ /* After creating the perf counter in __online_dispatch, there
++ * is a race condition between gator_events_perf_pmu_online and
++ * gator_events_perf_pmu_read. So have
++ * gator_events_perf_pmu_online call gator_events_perf_pmu_read
++ * and in __read check to see if it's the first call after
++ * __online_dispatch and if so, run the online code.
++ */
++ if (event->zero) {
++ ev->pmu->read(ev);
++ event->prev = event->curr = local64_read(&ev->count);
++ event->prev_delta = 0;
++ per_cpu(perf_cnt, cpu)[(*len)++] = attr->key;
++ per_cpu(perf_cnt, cpu)[(*len)++] = 0;
++ event->zero = false;
++ } else {
++ ev->pmu->read(ev);
++ event->curr = local64_read(&ev->count);
++ delta = event->curr - event->prev;
++ if (delta != 0 || delta != event->prev_delta) {
++ event->prev_delta = delta;
++ event->prev = event->curr;
++ per_cpu(perf_cnt, cpu)[(*len)++] = attr->key;
++ if (delta < 0) {
++ delta *= -1;
++ }
++ per_cpu(perf_cnt, cpu)[(*len)++] = delta;
++ }
++ }
++ }
++}
++
++static int gator_events_perf_pmu_read(int **buffer)
++{
++ int cnt, len = 0;
++ const int cpu = get_logical_cpu();
++
++ for (cnt = 0; cnt < attr_count; cnt++) {
++ __read(&len, cpu, &attrs[cnt], &per_cpu(events, cpu)[cnt]);
++ }
++
++ if (cpu == 0) {
++ for (cnt = 0; cnt < uc_attr_count; cnt++) {
++ __read(&len, cpu, &uc_attrs[cnt], &uc_events[cnt]);
++ }
++ }
++
++ if (buffer) {
++ *buffer = per_cpu(perf_cnt, cpu);
++ }
++
++ return len;
++}
++
++static struct gator_interface gator_events_perf_pmu_interface = {
++ .create_files = gator_events_perf_pmu_create_files,
++ .start = gator_events_perf_pmu_start,
++ .stop = gator_events_perf_pmu_stop,
++ .online = gator_events_perf_pmu_online,
++ .online_dispatch = gator_events_perf_pmu_online_dispatch,
++ .offline_dispatch = gator_events_perf_pmu_offline_dispatch,
++ .read = gator_events_perf_pmu_read,
++};
++
++static void __attr_init(struct gator_attr *const attr)
++{
++ attr->name[0] = '\0';
++ attr->enabled = 0;
++ attr->type = 0;
++ attr->event = 0;
++ attr->count = 0;
++ attr->key = gator_events_get_key();
++}
++
++#ifdef CONFIG_OF
++
++static const struct of_device_id arm_cci_matches[] = {
++ {.compatible = "arm,cci-400" },
++ {},
++};
++
++static int probe_cci_revision(void)
++{
++ struct device_node *np;
++ struct resource res;
++ void __iomem *cci_ctrl_base;
++ int rev;
++ int ret = DEFAULT_CCI_REVISION;
++
++ np = of_find_matching_node(NULL, arm_cci_matches);
++ if (!np) {
++ return ret;
++ }
++
++ if (of_address_to_resource(np, 0, &res)) {
++ goto node_put;
++ }
++
++ cci_ctrl_base = ioremap(res.start, resource_size(&res));
++
++ rev = (readl_relaxed(cci_ctrl_base + 0xfe8) >> 4) & 0xf;
++
++ if (rev <= 4) {
++ ret = 0;
++ } else if (rev <= 6) {
++ ret = 1;
++ }
++
++ iounmap(cci_ctrl_base);
++
++ node_put:
++ of_node_put(np);
++
++ return ret;
++}
++
++#else
++
++static int probe_cci_revision(void)
++{
++ return DEFAULT_CCI_REVISION;
++}
++
++#endif
++
++static void gator_events_perf_pmu_cci_init(const int type)
++{
++ int cnt;
++ const char *cci_name;
++
++ switch (probe_cci_revision()) {
++ case 0:
++ cci_name = "cci-400";
++ break;
++ case 1:
++ cci_name = "cci-400-r1";
++ break;
++ default:
++ pr_debug("gator: unrecognized cci-400 revision\n");
++ return;
++ }
++
++ snprintf(uc_attrs[uc_attr_count].name, sizeof(uc_attrs[uc_attr_count].name), "%s_ccnt", cci_name);
++ uc_attrs[uc_attr_count].type = type;
++ ++uc_attr_count;
++
++ for (cnt = 0; cnt < CCI_400; ++cnt, ++uc_attr_count) {
++ struct gator_attr *const attr = &uc_attrs[uc_attr_count];
++ snprintf(attr->name, sizeof(attr->name), "%s_cnt%d", cci_name, cnt);
++ attr->type = type;
++ }
++}
++
++static void gator_events_perf_pmu_cpu_init(const struct gator_cpu *const gator_cpu, const int type)
++{
++ int cnt;
++
++ snprintf(attrs[attr_count].name, sizeof(attrs[attr_count].name), "%s_ccnt", gator_cpu->pmnc_name);
++ attrs[attr_count].type = type;
++ ++attr_count;
++
++ for (cnt = 0; cnt < gator_cpu->pmnc_counters; ++cnt, ++attr_count) {
++ struct gator_attr *const attr = &attrs[attr_count];
++ snprintf(attr->name, sizeof(attr->name), "%s_cnt%d", gator_cpu->pmnc_name, cnt);
++ attr->type = type;
++ }
++}
++
++int gator_events_perf_pmu_init(void)
++{
++ struct perf_event_attr pea;
++ struct perf_event *pe;
++ const struct gator_cpu *gator_cpu;
++ int type;
++ int cpu;
++ int cnt;
++ bool found_cpu = false;
++
++ for (cnt = 0; cnt < CNTMAX; cnt++) {
++ __attr_init(&attrs[cnt]);
++ }
++ for (cnt = 0; cnt < UCCNT; cnt++) {
++ __attr_init(&uc_attrs[cnt]);
++ }
++
++ memset(&pea, 0, sizeof(pea));
++ pea.size = sizeof(pea);
++ pea.config = 0xFF;
++ attr_count = 0;
++ uc_attr_count = 0;
++ for (type = PERF_TYPE_MAX; type < 0x20; ++type) {
++ pea.type = type;
++
++ // A particular PMU may work on some but not all cores, so try on each core
++ pe = NULL;
++ for_each_present_cpu(cpu) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
++ pe = perf_event_create_kernel_counter(&pea, cpu, 0, dummy_handler);
++#else
++ pe = perf_event_create_kernel_counter(&pea, cpu, 0, dummy_handler, 0);
++#endif
++ if (!IS_ERR(pe)) {
++ break;
++ }
++ }
++ // Assume that valid PMUs are contiguous
++ if (IS_ERR(pe)) {
++ break;
++ }
++
++ if (pe->pmu != NULL && type == pe->pmu->type) {
++ if (strcmp("CCI", pe->pmu->name) == 0 || strcmp("CCI_400", pe->pmu->name) == 0) {
++ gator_events_perf_pmu_cci_init(type);
++ } else if ((gator_cpu = gator_find_cpu_by_pmu_name(pe->pmu->name)) != NULL) {
++ found_cpu = true;
++ gator_events_perf_pmu_cpu_init(gator_cpu, type);
++ }
++ // Initialize gator_attrs for dynamic PMUs here
++ }
++
++ perf_event_release_kernel(pe);
++ }
++
++ if (!found_cpu) {
++ const struct gator_cpu *const gator_cpu = gator_find_cpu_by_cpuid(gator_cpuid());
++ if (gator_cpu == NULL) {
++ return -1;
++ }
++ gator_events_perf_pmu_cpu_init(gator_cpu, PERF_TYPE_RAW);
++ }
++
++ // Initialize gator_attrs for non-dynamic PMUs here
++
++ if (attr_count > CNTMAX) {
++ printk(KERN_ERR "gator: Too many perf counters\n");
++ return -1;
++ }
++
++ if (uc_attr_count > UCCNT) {
++ printk(KERN_ERR "gator: Too many perf uncore counters\n");
++ return -1;
++ }
++
++ return gator_events_install(&gator_events_perf_pmu_interface);
++}
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_sched.c linux-linaro-stable-mx6/drivers/gator/gator_events_sched.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_sched.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_sched.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,113 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include "gator.h"
++#include <trace/events/sched.h>
++
++#define SCHED_SWITCH 0
++#define SCHED_TOTAL (SCHED_SWITCH+1)
++
++static ulong sched_switch_enabled;
++static ulong sched_switch_key;
++static DEFINE_PER_CPU(int[SCHED_TOTAL], schedCnt);
++static DEFINE_PER_CPU(int[SCHED_TOTAL * 2], schedGet);
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
++GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct rq *rq, struct task_struct *prev, struct task_struct *next))
++#else
++GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct task_struct *prev, struct task_struct *next))
++#endif
++{
++ unsigned long flags;
++
++ // disable interrupts to synchronize with gator_events_sched_read()
++ // spinlocks not needed since percpu buffers are used
++ local_irq_save(flags);
++ per_cpu(schedCnt, get_physical_cpu())[SCHED_SWITCH]++;
++ local_irq_restore(flags);
++}
++
++static int gator_events_sched_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++
++ /* switch */
++ dir = gatorfs_mkdir(sb, root, "Linux_sched_switch");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &sched_switch_enabled);
++ gatorfs_create_ro_ulong(sb, dir, "key", &sched_switch_key);
++
++ return 0;
++}
++
++static int gator_events_sched_start(void)
++{
++ // register tracepoints
++ if (sched_switch_enabled)
++ if (GATOR_REGISTER_TRACE(sched_switch))
++ goto sched_switch_exit;
++ pr_debug("gator: registered scheduler event tracepoints\n");
++
++ return 0;
++
++ // unregister tracepoints on error
++sched_switch_exit:
++ pr_err("gator: scheduler event tracepoints failed to activate, please verify that tracepoints are enabled in the linux kernel\n");
++
++ return -1;
++}
++
++static void gator_events_sched_stop(void)
++{
++ if (sched_switch_enabled)
++ GATOR_UNREGISTER_TRACE(sched_switch);
++ pr_debug("gator: unregistered scheduler event tracepoints\n");
++
++ sched_switch_enabled = 0;
++}
++
++static int gator_events_sched_read(int **buffer)
++{
++ unsigned long flags;
++ int len, value;
++ int cpu = get_physical_cpu();
++
++ len = 0;
++ if (sched_switch_enabled) {
++ local_irq_save(flags);
++ value = per_cpu(schedCnt, cpu)[SCHED_SWITCH];
++ per_cpu(schedCnt, cpu)[SCHED_SWITCH] = 0;
++ local_irq_restore(flags);
++ per_cpu(schedGet, cpu)[len++] = sched_switch_key;
++ per_cpu(schedGet, cpu)[len++] = value;
++ }
++
++ if (buffer)
++ *buffer = per_cpu(schedGet, cpu);
++
++ return len;
++}
++
++static struct gator_interface gator_events_sched_interface = {
++ .create_files = gator_events_sched_create_files,
++ .start = gator_events_sched_start,
++ .stop = gator_events_sched_stop,
++ .read = gator_events_sched_read,
++};
++
++int gator_events_sched_init(void)
++{
++ sched_switch_enabled = 0;
++
++ sched_switch_key = gator_events_get_key();
++
++ return gator_events_install(&gator_events_sched_interface);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_events_scorpion.c linux-linaro-stable-mx6/drivers/gator/gator_events_scorpion.c
+--- linux-3.10.30.orig/drivers/gator/gator_events_scorpion.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_events_scorpion.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,669 @@
++/**
++ * Copyright (C) ARM Limited 2011-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "gator.h"
++
++// gator_events_perf_pmu.c is used if perf is supported
++#if GATOR_NO_PERF_SUPPORT
++
++static const char *pmnc_name;
++static int pmnc_counters;
++
++// Per-CPU PMNC: config reg
++#define PMNC_E (1 << 0) /* Enable all counters */
++#define PMNC_P (1 << 1) /* Reset all counters */
++#define PMNC_C (1 << 2) /* Cycle counter reset */
++#define PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
++#define PMNC_X (1 << 4) /* Export to ETM */
++#define PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug */
++#define PMNC_MASK 0x3f /* Mask for writable bits */
++
++// ccnt reg
++#define CCNT_REG (1 << 31)
++
++#define CCNT 0
++#define CNT0 1
++#define CNTMAX (4+1)
++
++static unsigned long pmnc_enabled[CNTMAX];
++static unsigned long pmnc_event[CNTMAX];
++static unsigned long pmnc_key[CNTMAX];
++
++static DEFINE_PER_CPU(int[CNTMAX * 2], perfCnt);
++
++enum scorpion_perf_types {
++ SCORPION_ICACHE_EXPL_INV = 0x4c,
++ SCORPION_ICACHE_MISS = 0x4d,
++ SCORPION_ICACHE_ACCESS = 0x4e,
++ SCORPION_ICACHE_CACHEREQ_L2 = 0x4f,
++ SCORPION_ICACHE_NOCACHE_L2 = 0x50,
++ SCORPION_HIQUP_NOPED = 0x51,
++ SCORPION_DATA_ABORT = 0x52,
++ SCORPION_IRQ = 0x53,
++ SCORPION_FIQ = 0x54,
++ SCORPION_ALL_EXCPT = 0x55,
++ SCORPION_UNDEF = 0x56,
++ SCORPION_SVC = 0x57,
++ SCORPION_SMC = 0x58,
++ SCORPION_PREFETCH_ABORT = 0x59,
++ SCORPION_INDEX_CHECK = 0x5a,
++ SCORPION_NULL_CHECK = 0x5b,
++ SCORPION_EXPL_ICIALLU = 0x5c,
++ SCORPION_IMPL_ICIALLU = 0x5d,
++ SCORPION_NONICIALLU_BTAC_INV = 0x5e,
++ SCORPION_ICIMVAU_IMPL_ICIALLU = 0x5f,
++ SCORPION_SPIPE_ONLY_CYCLES = 0x60,
++ SCORPION_XPIPE_ONLY_CYCLES = 0x61,
++ SCORPION_DUAL_CYCLES = 0x62,
++ SCORPION_DISPATCH_ANY_CYCLES = 0x63,
++ SCORPION_FIFO_FULLBLK_CMT = 0x64,
++ SCORPION_FAIL_COND_INST = 0x65,
++ SCORPION_PASS_COND_INST = 0x66,
++ SCORPION_ALLOW_VU_CLK = 0x67,
++ SCORPION_VU_IDLE = 0x68,
++ SCORPION_ALLOW_L2_CLK = 0x69,
++ SCORPION_L2_IDLE = 0x6a,
++ SCORPION_DTLB_IMPL_INV_SCTLR_DACR = 0x6b,
++ SCORPION_DTLB_EXPL_INV = 0x6c,
++ SCORPION_DTLB_MISS = 0x6d,
++ SCORPION_DTLB_ACCESS = 0x6e,
++ SCORPION_ITLB_MISS = 0x6f,
++ SCORPION_ITLB_IMPL_INV = 0x70,
++ SCORPION_ITLB_EXPL_INV = 0x71,
++ SCORPION_UTLB_D_MISS = 0x72,
++ SCORPION_UTLB_D_ACCESS = 0x73,
++ SCORPION_UTLB_I_MISS = 0x74,
++ SCORPION_UTLB_I_ACCESS = 0x75,
++ SCORPION_UTLB_INV_ASID = 0x76,
++ SCORPION_UTLB_INV_MVA = 0x77,
++ SCORPION_UTLB_INV_ALL = 0x78,
++ SCORPION_S2_HOLD_RDQ_UNAVAIL = 0x79,
++ SCORPION_S2_HOLD = 0x7a,
++ SCORPION_S2_HOLD_DEV_OP = 0x7b,
++ SCORPION_S2_HOLD_ORDER = 0x7c,
++ SCORPION_S2_HOLD_BARRIER = 0x7d,
++ SCORPION_VIU_DUAL_CYCLE = 0x7e,
++ SCORPION_VIU_SINGLE_CYCLE = 0x7f,
++ SCORPION_VX_PIPE_WAR_STALL_CYCLES = 0x80,
++ SCORPION_VX_PIPE_WAW_STALL_CYCLES = 0x81,
++ SCORPION_VX_PIPE_RAW_STALL_CYCLES = 0x82,
++ SCORPION_VX_PIPE_LOAD_USE_STALL = 0x83,
++ SCORPION_VS_PIPE_WAR_STALL_CYCLES = 0x84,
++ SCORPION_VS_PIPE_WAW_STALL_CYCLES = 0x85,
++ SCORPION_VS_PIPE_RAW_STALL_CYCLES = 0x86,
++ SCORPION_EXCEPTIONS_INV_OPERATION = 0x87,
++ SCORPION_EXCEPTIONS_DIV_BY_ZERO = 0x88,
++ SCORPION_COND_INST_FAIL_VX_PIPE = 0x89,
++ SCORPION_COND_INST_FAIL_VS_PIPE = 0x8a,
++ SCORPION_EXCEPTIONS_OVERFLOW = 0x8b,
++ SCORPION_EXCEPTIONS_UNDERFLOW = 0x8c,
++ SCORPION_EXCEPTIONS_DENORM = 0x8d,
++#ifdef CONFIG_ARCH_MSM_SCORPIONMP
++ SCORPIONMP_NUM_BARRIERS = 0x8e,
++ SCORPIONMP_BARRIER_CYCLES = 0x8f,
++#else
++ SCORPION_BANK_AB_HIT = 0x8e,
++ SCORPION_BANK_AB_ACCESS = 0x8f,
++ SCORPION_BANK_CD_HIT = 0x90,
++ SCORPION_BANK_CD_ACCESS = 0x91,
++ SCORPION_BANK_AB_DSIDE_HIT = 0x92,
++ SCORPION_BANK_AB_DSIDE_ACCESS = 0x93,
++ SCORPION_BANK_CD_DSIDE_HIT = 0x94,
++ SCORPION_BANK_CD_DSIDE_ACCESS = 0x95,
++ SCORPION_BANK_AB_ISIDE_HIT = 0x96,
++ SCORPION_BANK_AB_ISIDE_ACCESS = 0x97,
++ SCORPION_BANK_CD_ISIDE_HIT = 0x98,
++ SCORPION_BANK_CD_ISIDE_ACCESS = 0x99,
++ SCORPION_ISIDE_RD_WAIT = 0x9a,
++ SCORPION_DSIDE_RD_WAIT = 0x9b,
++ SCORPION_BANK_BYPASS_WRITE = 0x9c,
++ SCORPION_BANK_AB_NON_CASTOUT = 0x9d,
++ SCORPION_BANK_AB_L2_CASTOUT = 0x9e,
++ SCORPION_BANK_CD_NON_CASTOUT = 0x9f,
++ SCORPION_BANK_CD_L2_CASTOUT = 0xa0,
++#endif
++ MSM_MAX_EVT
++};
++
++struct scorp_evt {
++ u32 evt_type;
++ u32 val;
++ u8 grp;
++ u32 evt_type_act;
++};
++
++static const struct scorp_evt sc_evt[] = {
++ {SCORPION_ICACHE_EXPL_INV, 0x80000500, 0, 0x4d},
++ {SCORPION_ICACHE_MISS, 0x80050000, 0, 0x4e},
++ {SCORPION_ICACHE_ACCESS, 0x85000000, 0, 0x4f},
++ {SCORPION_ICACHE_CACHEREQ_L2, 0x86000000, 0, 0x4f},
++ {SCORPION_ICACHE_NOCACHE_L2, 0x87000000, 0, 0x4f},
++ {SCORPION_HIQUP_NOPED, 0x80080000, 0, 0x4e},
++ {SCORPION_DATA_ABORT, 0x8000000a, 0, 0x4c},
++ {SCORPION_IRQ, 0x80000a00, 0, 0x4d},
++ {SCORPION_FIQ, 0x800a0000, 0, 0x4e},
++ {SCORPION_ALL_EXCPT, 0x8a000000, 0, 0x4f},
++ {SCORPION_UNDEF, 0x8000000b, 0, 0x4c},
++ {SCORPION_SVC, 0x80000b00, 0, 0x4d},
++ {SCORPION_SMC, 0x800b0000, 0, 0x4e},
++ {SCORPION_PREFETCH_ABORT, 0x8b000000, 0, 0x4f},
++ {SCORPION_INDEX_CHECK, 0x8000000c, 0, 0x4c},
++ {SCORPION_NULL_CHECK, 0x80000c00, 0, 0x4d},
++ {SCORPION_EXPL_ICIALLU, 0x8000000d, 0, 0x4c},
++ {SCORPION_IMPL_ICIALLU, 0x80000d00, 0, 0x4d},
++ {SCORPION_NONICIALLU_BTAC_INV, 0x800d0000, 0, 0x4e},
++ {SCORPION_ICIMVAU_IMPL_ICIALLU, 0x8d000000, 0, 0x4f},
++
++ {SCORPION_SPIPE_ONLY_CYCLES, 0x80000600, 1, 0x51},
++ {SCORPION_XPIPE_ONLY_CYCLES, 0x80060000, 1, 0x52},
++ {SCORPION_DUAL_CYCLES, 0x86000000, 1, 0x53},
++ {SCORPION_DISPATCH_ANY_CYCLES, 0x89000000, 1, 0x53},
++ {SCORPION_FIFO_FULLBLK_CMT, 0x8000000d, 1, 0x50},
++ {SCORPION_FAIL_COND_INST, 0x800d0000, 1, 0x52},
++ {SCORPION_PASS_COND_INST, 0x8d000000, 1, 0x53},
++ {SCORPION_ALLOW_VU_CLK, 0x8000000e, 1, 0x50},
++ {SCORPION_VU_IDLE, 0x80000e00, 1, 0x51},
++ {SCORPION_ALLOW_L2_CLK, 0x800e0000, 1, 0x52},
++ {SCORPION_L2_IDLE, 0x8e000000, 1, 0x53},
++
++ {SCORPION_DTLB_IMPL_INV_SCTLR_DACR, 0x80000001, 2, 0x54},
++ {SCORPION_DTLB_EXPL_INV, 0x80000100, 2, 0x55},
++ {SCORPION_DTLB_MISS, 0x80010000, 2, 0x56},
++ {SCORPION_DTLB_ACCESS, 0x81000000, 2, 0x57},
++ {SCORPION_ITLB_MISS, 0x80000200, 2, 0x55},
++ {SCORPION_ITLB_IMPL_INV, 0x80020000, 2, 0x56},
++ {SCORPION_ITLB_EXPL_INV, 0x82000000, 2, 0x57},
++ {SCORPION_UTLB_D_MISS, 0x80000003, 2, 0x54},
++ {SCORPION_UTLB_D_ACCESS, 0x80000300, 2, 0x55},
++ {SCORPION_UTLB_I_MISS, 0x80030000, 2, 0x56},
++ {SCORPION_UTLB_I_ACCESS, 0x83000000, 2, 0x57},
++ {SCORPION_UTLB_INV_ASID, 0x80000400, 2, 0x55},
++ {SCORPION_UTLB_INV_MVA, 0x80040000, 2, 0x56},
++ {SCORPION_UTLB_INV_ALL, 0x84000000, 2, 0x57},
++ {SCORPION_S2_HOLD_RDQ_UNAVAIL, 0x80000800, 2, 0x55},
++ {SCORPION_S2_HOLD, 0x88000000, 2, 0x57},
++ {SCORPION_S2_HOLD_DEV_OP, 0x80000900, 2, 0x55},
++ {SCORPION_S2_HOLD_ORDER, 0x80090000, 2, 0x56},
++ {SCORPION_S2_HOLD_BARRIER, 0x89000000, 2, 0x57},
++
++ {SCORPION_VIU_DUAL_CYCLE, 0x80000001, 4, 0x5c},
++ {SCORPION_VIU_SINGLE_CYCLE, 0x80000100, 4, 0x5d},
++ {SCORPION_VX_PIPE_WAR_STALL_CYCLES, 0x80000005, 4, 0x5c},
++ {SCORPION_VX_PIPE_WAW_STALL_CYCLES, 0x80000500, 4, 0x5d},
++ {SCORPION_VX_PIPE_RAW_STALL_CYCLES, 0x80050000, 4, 0x5e},
++ {SCORPION_VX_PIPE_LOAD_USE_STALL, 0x80000007, 4, 0x5c},
++ {SCORPION_VS_PIPE_WAR_STALL_CYCLES, 0x80000008, 4, 0x5c},
++ {SCORPION_VS_PIPE_WAW_STALL_CYCLES, 0x80000800, 4, 0x5d},
++ {SCORPION_VS_PIPE_RAW_STALL_CYCLES, 0x80080000, 4, 0x5e},
++ {SCORPION_EXCEPTIONS_INV_OPERATION, 0x8000000b, 4, 0x5c},
++ {SCORPION_EXCEPTIONS_DIV_BY_ZERO, 0x80000b00, 4, 0x5d},
++ {SCORPION_COND_INST_FAIL_VX_PIPE, 0x800b0000, 4, 0x5e},
++ {SCORPION_COND_INST_FAIL_VS_PIPE, 0x8b000000, 4, 0x5f},
++ {SCORPION_EXCEPTIONS_OVERFLOW, 0x8000000c, 4, 0x5c},
++ {SCORPION_EXCEPTIONS_UNDERFLOW, 0x80000c00, 4, 0x5d},
++ {SCORPION_EXCEPTIONS_DENORM, 0x8c000000, 4, 0x5f},
++
++#ifdef CONFIG_ARCH_MSM_SCORPIONMP
++ {SCORPIONMP_NUM_BARRIERS, 0x80000e00, 3, 0x59},
++ {SCORPIONMP_BARRIER_CYCLES, 0x800e0000, 3, 0x5a},
++#else
++ {SCORPION_BANK_AB_HIT, 0x80000001, 3, 0x58},
++ {SCORPION_BANK_AB_ACCESS, 0x80000100, 3, 0x59},
++ {SCORPION_BANK_CD_HIT, 0x80010000, 3, 0x5a},
++ {SCORPION_BANK_CD_ACCESS, 0x81000000, 3, 0x5b},
++ {SCORPION_BANK_AB_DSIDE_HIT, 0x80000002, 3, 0x58},
++ {SCORPION_BANK_AB_DSIDE_ACCESS, 0x80000200, 3, 0x59},
++ {SCORPION_BANK_CD_DSIDE_HIT, 0x80020000, 3, 0x5a},
++ {SCORPION_BANK_CD_DSIDE_ACCESS, 0x82000000, 3, 0x5b},
++ {SCORPION_BANK_AB_ISIDE_HIT, 0x80000003, 3, 0x58},
++ {SCORPION_BANK_AB_ISIDE_ACCESS, 0x80000300, 3, 0x59},
++ {SCORPION_BANK_CD_ISIDE_HIT, 0x80030000, 3, 0x5a},
++ {SCORPION_BANK_CD_ISIDE_ACCESS, 0x83000000, 3, 0x5b},
++ {SCORPION_ISIDE_RD_WAIT, 0x80000009, 3, 0x58},
++ {SCORPION_DSIDE_RD_WAIT, 0x80090000, 3, 0x5a},
++ {SCORPION_BANK_BYPASS_WRITE, 0x8000000a, 3, 0x58},
++ {SCORPION_BANK_AB_NON_CASTOUT, 0x8000000c, 3, 0x58},
++ {SCORPION_BANK_AB_L2_CASTOUT, 0x80000c00, 3, 0x59},
++ {SCORPION_BANK_CD_NON_CASTOUT, 0x800c0000, 3, 0x5a},
++ {SCORPION_BANK_CD_L2_CASTOUT, 0x8c000000, 3, 0x5b},
++#endif
++};
++
++static inline void scorpion_pmnc_write(u32 val)
++{
++ val &= PMNC_MASK;
++ asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
++}
++
++static inline u32 scorpion_pmnc_read(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
++ return val;
++}
++
++static inline u32 scorpion_ccnt_read(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
++ return val;
++}
++
++static inline u32 scorpion_cntn_read(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
++ return val;
++}
++
++static inline u32 scorpion_pmnc_enable_counter(unsigned int cnt)
++{
++ u32 val;
++
++ if (cnt >= CNTMAX) {
++ pr_err("gator: CPU%u enabling wrong PMNC counter %d\n", smp_processor_id(), cnt);
++ return -1;
++ }
++
++ if (cnt == CCNT)
++ val = CCNT_REG;
++ else
++ val = (1 << (cnt - CNT0));
++
++ asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
++
++ return cnt;
++}
++
++static inline u32 scorpion_pmnc_disable_counter(unsigned int cnt)
++{
++ u32 val;
++
++ if (cnt >= CNTMAX) {
++ pr_err("gator: CPU%u disabling wrong PMNC counter %d\n", smp_processor_id(), cnt);
++ return -1;
++ }
++
++ if (cnt == CCNT)
++ val = CCNT_REG;
++ else
++ val = (1 << (cnt - CNT0));
++
++ asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
++
++ return cnt;
++}
++
++static inline int scorpion_pmnc_select_counter(unsigned int cnt)
++{
++ u32 val;
++
++ if ((cnt == CCNT) || (cnt >= CNTMAX)) {
++ pr_err("gator: CPU%u selecting wrong PMNC counter %d\n", smp_processor_id(), cnt);
++ return -1;
++ }
++
++ val = (cnt - CNT0);
++ asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
++
++ return cnt;
++}
++
++static u32 scorpion_read_lpm0(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val));
++ return val;
++}
++
++static void scorpion_write_lpm0(u32 val)
++{
++ asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val));
++}
++
++static u32 scorpion_read_lpm1(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
++ return val;
++}
++
++static void scorpion_write_lpm1(u32 val)
++{
++ asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val));
++}
++
++static u32 scorpion_read_lpm2(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val));
++ return val;
++}
++
++static void scorpion_write_lpm2(u32 val)
++{
++ asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val));
++}
++
++static u32 scorpion_read_l2lpm(void)
++{
++ u32 val;
++ asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val));
++ return val;
++}
++
++static void scorpion_write_l2lpm(u32 val)
++{
++ asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val));
++}
++
++static u32 scorpion_read_vlpm(void)
++{
++ u32 val;
++ asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val));
++ return val;
++}
++
++static void scorpion_write_vlpm(u32 val)
++{
++ asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val));
++}
++
++struct scorpion_access_funcs {
++ u32(*read)(void);
++ void (*write)(u32);
++};
++
++struct scorpion_access_funcs scor_func[] = {
++ {scorpion_read_lpm0, scorpion_write_lpm0},
++ {scorpion_read_lpm1, scorpion_write_lpm1},
++ {scorpion_read_lpm2, scorpion_write_lpm2},
++ {scorpion_read_l2lpm, scorpion_write_l2lpm},
++ {scorpion_read_vlpm, scorpion_write_vlpm},
++};
++
++u32 venum_orig_val;
++u32 fp_orig_val;
++
++static void scorpion_pre_vlpm(void)
++{
++ u32 venum_new_val;
++ u32 fp_new_val;
++
++ /* CPACR Enable CP10 access */
++ asm volatile("mrc p15, 0, %0, c1, c0, 2" : "=r" (venum_orig_val));
++ venum_new_val = venum_orig_val | 0x00300000;
++ asm volatile("mcr p15, 0, %0, c1, c0, 2" : : "r" (venum_new_val));
++ /* Enable FPEXC */
++ asm volatile("mrc p10, 7, %0, c8, c0, 0" : "=r" (fp_orig_val));
++ fp_new_val = fp_orig_val | 0x40000000;
++ asm volatile("mcr p10, 7, %0, c8, c0, 0" : : "r" (fp_new_val));
++}
++
++static void scorpion_post_vlpm(void)
++{
++ /* Restore FPEXC */
++ asm volatile("mcr p10, 7, %0, c8, c0, 0" : : "r" (fp_orig_val));
++ /* Restore CPACR */
++ asm volatile("mcr p15, 0, %0, c1, c0, 2" : : "r" (venum_orig_val));
++}
++
++#define COLMN0MASK 0x000000ff
++#define COLMN1MASK 0x0000ff00
++#define COLMN2MASK 0x00ff0000
++static u32 scorpion_get_columnmask(u32 setval)
++{
++ if (setval & COLMN0MASK)
++ return 0xffffff00;
++ else if (setval & COLMN1MASK)
++ return 0xffff00ff;
++ else if (setval & COLMN2MASK)
++ return 0xff00ffff;
++ else
++ return 0x80ffffff;
++}
++
++static void scorpion_evt_setup(u32 gr, u32 setval)
++{
++ u32 val;
++ if (gr == 4)
++ scorpion_pre_vlpm();
++ val = scorpion_get_columnmask(setval) & scor_func[gr].read();
++ val = val | setval;
++ scor_func[gr].write(val);
++ if (gr == 4)
++ scorpion_post_vlpm();
++}
++
++static int get_scorpion_evtinfo(unsigned int evt_type, struct scorp_evt *evtinfo)
++{
++ u32 idx;
++ if ((evt_type < 0x4c) || (evt_type >= MSM_MAX_EVT))
++ return 0;
++ idx = evt_type - 0x4c;
++ if (sc_evt[idx].evt_type == evt_type) {
++ evtinfo->val = sc_evt[idx].val;
++ evtinfo->grp = sc_evt[idx].grp;
++ evtinfo->evt_type_act = sc_evt[idx].evt_type_act;
++ return 1;
++ }
++ return 0;
++}
++
++static inline void scorpion_pmnc_write_evtsel(unsigned int cnt, u32 val)
++{
++ if (scorpion_pmnc_select_counter(cnt) == cnt) {
++ if (val < 0x40) {
++ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
++ } else {
++ u32 zero = 0;
++ struct scorp_evt evtinfo;
++ // extract evtinfo.grp and evtinfo.tevt_type_act from val
++ if (get_scorpion_evtinfo(val, &evtinfo) == 0)
++ return;
++ asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (evtinfo.evt_type_act));
++ asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (zero));
++ scorpion_evt_setup(evtinfo.grp, val);
++ }
++ }
++}
++
++static void scorpion_pmnc_reset_counter(unsigned int cnt)
++{
++ u32 val = 0;
++
++ if (cnt == CCNT) {
++ scorpion_pmnc_disable_counter(cnt);
++
++ asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
++
++ if (pmnc_enabled[cnt] != 0)
++ scorpion_pmnc_enable_counter(cnt);
++
++ } else if (cnt >= CNTMAX) {
++ pr_err("gator: CPU%u resetting wrong PMNC counter %d\n", smp_processor_id(), cnt);
++ } else {
++ scorpion_pmnc_disable_counter(cnt);
++
++ if (scorpion_pmnc_select_counter(cnt) == cnt)
++ asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (val));
++
++ if (pmnc_enabled[cnt] != 0)
++ scorpion_pmnc_enable_counter(cnt);
++ }
++}
++
++static int gator_events_scorpion_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++ int i;
++
++ for (i = 0; i < pmnc_counters; i++) {
++ char buf[40];
++ if (i == 0) {
++ snprintf(buf, sizeof buf, "%s_ccnt", pmnc_name);
++ } else {
++ snprintf(buf, sizeof buf, "%s_cnt%d", pmnc_name, i - 1);
++ }
++ dir = gatorfs_mkdir(sb, root, buf);
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &pmnc_enabled[i]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &pmnc_key[i]);
++ if (i > 0) {
++ gatorfs_create_ulong(sb, dir, "event", &pmnc_event[i]);
++ }
++ }
++
++ return 0;
++}
++
++static int gator_events_scorpion_online(int **buffer, bool migrate)
++{
++ unsigned int cnt, len = 0, cpu = smp_processor_id();
++
++ if (scorpion_pmnc_read() & PMNC_E) {
++ scorpion_pmnc_write(scorpion_pmnc_read() & ~PMNC_E);
++ }
++
++ /* Initialize & Reset PMNC: C bit and P bit */
++ scorpion_pmnc_write(PMNC_P | PMNC_C);
++
++ for (cnt = CCNT; cnt < CNTMAX; cnt++) {
++ unsigned long event;
++
++ if (!pmnc_enabled[cnt])
++ continue;
++
++ // disable counter
++ scorpion_pmnc_disable_counter(cnt);
++
++ event = pmnc_event[cnt] & 255;
++
++ // Set event (if destined for PMNx counters), We don't need to set the event if it's a cycle count
++ if (cnt != CCNT)
++ scorpion_pmnc_write_evtsel(cnt, event);
++
++ // reset counter
++ scorpion_pmnc_reset_counter(cnt);
++
++ // Enable counter, do not enable interrupt for this counter
++ scorpion_pmnc_enable_counter(cnt);
++ }
++
++ // enable
++ scorpion_pmnc_write(scorpion_pmnc_read() | PMNC_E);
++
++ // read the counters and toss the invalid data, return zero instead
++ for (cnt = 0; cnt < pmnc_counters; cnt++) {
++ if (pmnc_enabled[cnt]) {
++ if (cnt == CCNT) {
++ scorpion_ccnt_read();
++ } else if (scorpion_pmnc_select_counter(cnt) == cnt) {
++ scorpion_cntn_read();
++ }
++ scorpion_pmnc_reset_counter(cnt);
++
++ per_cpu(perfCnt, cpu)[len++] = pmnc_key[cnt];
++ per_cpu(perfCnt, cpu)[len++] = 0;
++ }
++ }
++
++ if (buffer)
++ *buffer = per_cpu(perfCnt, cpu);
++
++ return len;
++}
++
++static int gator_events_scorpion_offline(int **buffer, bool migrate)
++{
++ scorpion_pmnc_write(scorpion_pmnc_read() & ~PMNC_E);
++ return 0;
++}
++
++static void gator_events_scorpion_stop(void)
++{
++ unsigned int cnt;
++
++ for (cnt = CCNT; cnt < CNTMAX; cnt++) {
++ pmnc_enabled[cnt] = 0;
++ pmnc_event[cnt] = 0;
++ }
++}
++
++static int gator_events_scorpion_read(int **buffer)
++{
++ int cnt, len = 0;
++ int cpu = smp_processor_id();
++
++ // a context switch may occur before the online hotplug event, thus need to check that the pmu is enabled
++ if (!(scorpion_pmnc_read() & PMNC_E)) {
++ return 0;
++ }
++
++ for (cnt = 0; cnt < pmnc_counters; cnt++) {
++ if (pmnc_enabled[cnt]) {
++ int value;
++ if (cnt == CCNT) {
++ value = scorpion_ccnt_read();
++ } else if (scorpion_pmnc_select_counter(cnt) == cnt) {
++ value = scorpion_cntn_read();
++ } else {
++ value = 0;
++ }
++ scorpion_pmnc_reset_counter(cnt);
++
++ per_cpu(perfCnt, cpu)[len++] = pmnc_key[cnt];
++ per_cpu(perfCnt, cpu)[len++] = value;
++ }
++ }
++
++ if (buffer)
++ *buffer = per_cpu(perfCnt, cpu);
++
++ return len;
++}
++
++static struct gator_interface gator_events_scorpion_interface = {
++ .create_files = gator_events_scorpion_create_files,
++ .stop = gator_events_scorpion_stop,
++ .online = gator_events_scorpion_online,
++ .offline = gator_events_scorpion_offline,
++ .read = gator_events_scorpion_read,
++};
++
++int gator_events_scorpion_init(void)
++{
++ unsigned int cnt;
++
++ switch (gator_cpuid()) {
++ case SCORPION:
++ pmnc_name = "Scorpion";
++ pmnc_counters = 4;
++ break;
++ case SCORPIONMP:
++ pmnc_name = "ScorpionMP";
++ pmnc_counters = 4;
++ break;
++ default:
++ return -1;
++ }
++
++ pmnc_counters++; // CNT[n] + CCNT
++
++ for (cnt = CCNT; cnt < CNTMAX; cnt++) {
++ pmnc_enabled[cnt] = 0;
++ pmnc_event[cnt] = 0;
++ pmnc_key[cnt] = gator_events_get_key();
++ }
++
++ return gator_events_install(&gator_events_scorpion_interface);
++}
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_fs.c linux-linaro-stable-mx6/drivers/gator/gator_fs.c
+--- linux-3.10.30.orig/drivers/gator/gator_fs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_fs.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,382 @@
++/**
++ * @file gatorfs.c
++ *
++ * @remark Copyright 2002 OProfile authors
++ * @remark Read the file COPYING
++ *
++ * @author John Levon
++ *
++ * A simple filesystem for configuration and
++ * access of oprofile.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/pagemap.h>
++#include <asm/uaccess.h>
++
++#define gatorfs_MAGIC 0x24051020
++#define TMPBUFSIZE 50
++DEFINE_SPINLOCK(gatorfs_lock);
++
++static struct inode *gatorfs_get_inode(struct super_block *sb, int mode)
++{
++ struct inode *inode = new_inode(sb);
++
++ if (inode) {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)
++ inode->i_ino = get_next_ino();
++#endif
++ inode->i_mode = mode;
++ inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME;
++ }
++ return inode;
++}
++
++static const struct super_operations s_ops = {
++ .statfs = simple_statfs,
++ .drop_inode = generic_delete_inode,
++};
++
++ssize_t gatorfs_str_to_user(char const *str, char __user *buf, size_t count, loff_t *offset)
++{
++ return simple_read_from_buffer(buf, count, offset, str, strlen(str));
++}
++
++ssize_t gatorfs_ulong_to_user(unsigned long val, char __user *buf, size_t count, loff_t *offset)
++{
++ char tmpbuf[TMPBUFSIZE];
++ size_t maxlen = snprintf(tmpbuf, TMPBUFSIZE, "%lu\n", val);
++ if (maxlen > TMPBUFSIZE)
++ maxlen = TMPBUFSIZE;
++ return simple_read_from_buffer(buf, count, offset, tmpbuf, maxlen);
++}
++
++ssize_t gatorfs_u64_to_user(u64 val, char __user *buf, size_t count, loff_t *offset)
++{
++ char tmpbuf[TMPBUFSIZE];
++ size_t maxlen = snprintf(tmpbuf, TMPBUFSIZE, "%llu\n", val);
++ if (maxlen > TMPBUFSIZE)
++ maxlen = TMPBUFSIZE;
++ return simple_read_from_buffer(buf, count, offset, tmpbuf, maxlen);
++}
++
++int gatorfs_ulong_from_user(unsigned long *val, char const __user *buf, size_t count)
++{
++ char tmpbuf[TMPBUFSIZE];
++ unsigned long flags;
++
++ if (!count)
++ return 0;
++
++ if (count > TMPBUFSIZE - 1)
++ return -EINVAL;
++
++ memset(tmpbuf, 0x0, TMPBUFSIZE);
++
++ if (copy_from_user(tmpbuf, buf, count))
++ return -EFAULT;
++
++ spin_lock_irqsave(&gatorfs_lock, flags);
++ *val = simple_strtoul(tmpbuf, NULL, 0);
++ spin_unlock_irqrestore(&gatorfs_lock, flags);
++ return 0;
++}
++
++int gatorfs_u64_from_user(u64 *val, char const __user *buf, size_t count)
++{
++ char tmpbuf[TMPBUFSIZE];
++ unsigned long flags;
++
++ if (!count)
++ return 0;
++
++ if (count > TMPBUFSIZE - 1)
++ return -EINVAL;
++
++ memset(tmpbuf, 0x0, TMPBUFSIZE);
++
++ if (copy_from_user(tmpbuf, buf, count))
++ return -EFAULT;
++
++ spin_lock_irqsave(&gatorfs_lock, flags);
++ *val = simple_strtoull(tmpbuf, NULL, 0);
++ spin_unlock_irqrestore(&gatorfs_lock, flags);
++ return 0;
++}
++
++static ssize_t ulong_read_file(struct file *file, char __user *buf, size_t count, loff_t *offset)
++{
++ unsigned long *val = file->private_data;
++ return gatorfs_ulong_to_user(*val, buf, count, offset);
++}
++
++static ssize_t u64_read_file(struct file *file, char __user *buf, size_t count, loff_t *offset)
++{
++ u64 *val = file->private_data;
++ return gatorfs_u64_to_user(*val, buf, count, offset);
++}
++
++static ssize_t ulong_write_file(struct file *file, char const __user *buf, size_t count, loff_t *offset)
++{
++ unsigned long *value = file->private_data;
++ int retval;
++
++ if (*offset)
++ return -EINVAL;
++
++ retval = gatorfs_ulong_from_user(value, buf, count);
++
++ if (retval)
++ return retval;
++ return count;
++}
++
++static ssize_t u64_write_file(struct file *file, char const __user *buf, size_t count, loff_t *offset)
++{
++ u64 *value = file->private_data;
++ int retval;
++
++ if (*offset)
++ return -EINVAL;
++
++ retval = gatorfs_u64_from_user(value, buf, count);
++
++ if (retval)
++ return retval;
++ return count;
++}
++
++static int default_open(struct inode *inode, struct file *filp)
++{
++ if (inode->i_private)
++ filp->private_data = inode->i_private;
++ return 0;
++}
++
++static const struct file_operations ulong_fops = {
++ .read = ulong_read_file,
++ .write = ulong_write_file,
++ .open = default_open,
++};
++
++static const struct file_operations u64_fops = {
++ .read = u64_read_file,
++ .write = u64_write_file,
++ .open = default_open,
++};
++
++static const struct file_operations ulong_ro_fops = {
++ .read = ulong_read_file,
++ .open = default_open,
++};
++
++static const struct file_operations u64_ro_fops = {
++ .read = u64_read_file,
++ .open = default_open,
++};
++
++static struct dentry *__gatorfs_create_file(struct super_block *sb,
++ struct dentry *root,
++ char const *name,
++ const struct file_operations *fops,
++ int perm)
++{
++ struct dentry *dentry;
++ struct inode *inode;
++
++ dentry = d_alloc_name(root, name);
++ if (!dentry)
++ return NULL;
++ inode = gatorfs_get_inode(sb, S_IFREG | perm);
++ if (!inode) {
++ dput(dentry);
++ return NULL;
++ }
++ inode->i_fop = fops;
++ d_add(dentry, inode);
++ return dentry;
++}
++
++int gatorfs_create_ulong(struct super_block *sb, struct dentry *root,
++ char const *name, unsigned long *val)
++{
++ struct dentry *d = __gatorfs_create_file(sb, root, name,
++ &ulong_fops, 0644);
++ if (!d)
++ return -EFAULT;
++
++ d->d_inode->i_private = val;
++ return 0;
++}
++
++int gatorfs_create_u64(struct super_block *sb, struct dentry *root,
++ char const *name, u64 *val)
++{
++ struct dentry *d = __gatorfs_create_file(sb, root, name,
++ &u64_fops, 0644);
++ if (!d)
++ return -EFAULT;
++
++ d->d_inode->i_private = val;
++ return 0;
++}
++
++int gatorfs_create_ro_ulong(struct super_block *sb, struct dentry *root,
++ char const *name, unsigned long *val)
++{
++ struct dentry *d = __gatorfs_create_file(sb, root, name,
++ &ulong_ro_fops, 0444);
++ if (!d)
++ return -EFAULT;
++
++ d->d_inode->i_private = val;
++ return 0;
++}
++
++int gatorfs_create_ro_u64(struct super_block *sb, struct dentry *root,
++ char const *name, u64 * val)
++{
++ struct dentry *d =
++ __gatorfs_create_file(sb, root, name, &u64_ro_fops, 0444);
++ if (!d)
++ return -EFAULT;
++
++ d->d_inode->i_private = val;
++ return 0;
++}
++
++static ssize_t atomic_read_file(struct file *file, char __user *buf, size_t count, loff_t *offset)
++{
++ atomic_t *val = file->private_data;
++ return gatorfs_ulong_to_user(atomic_read(val), buf, count, offset);
++}
++
++static const struct file_operations atomic_ro_fops = {
++ .read = atomic_read_file,
++ .open = default_open,
++};
++
++int gatorfs_create_ro_atomic(struct super_block *sb, struct dentry *root,
++ char const *name, atomic_t *val)
++{
++ struct dentry *d = __gatorfs_create_file(sb, root, name,
++ &atomic_ro_fops, 0444);
++ if (!d)
++ return -EFAULT;
++
++ d->d_inode->i_private = val;
++ return 0;
++}
++
++int gatorfs_create_file(struct super_block *sb, struct dentry *root,
++ char const *name, const struct file_operations *fops)
++{
++ if (!__gatorfs_create_file(sb, root, name, fops, 0644))
++ return -EFAULT;
++ return 0;
++}
++
++int gatorfs_create_file_perm(struct super_block *sb, struct dentry *root,
++ char const *name,
++ const struct file_operations *fops, int perm)
++{
++ if (!__gatorfs_create_file(sb, root, name, fops, perm))
++ return -EFAULT;
++ return 0;
++}
++
++struct dentry *gatorfs_mkdir(struct super_block *sb,
++ struct dentry *root, char const *name)
++{
++ struct dentry *dentry;
++ struct inode *inode;
++
++ dentry = d_alloc_name(root, name);
++ if (!dentry)
++ return NULL;
++ inode = gatorfs_get_inode(sb, S_IFDIR | 0755);
++ if (!inode) {
++ dput(dentry);
++ return NULL;
++ }
++ inode->i_op = &simple_dir_inode_operations;
++ inode->i_fop = &simple_dir_operations;
++ d_add(dentry, inode);
++ return dentry;
++}
++
++static int gatorfs_fill_super(struct super_block *sb, void *data, int silent)
++{
++ struct inode *root_inode;
++ struct dentry *root_dentry;
++
++ sb->s_blocksize = PAGE_CACHE_SIZE;
++ sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
++ sb->s_magic = gatorfs_MAGIC;
++ sb->s_op = &s_ops;
++ sb->s_time_gran = 1;
++
++ root_inode = gatorfs_get_inode(sb, S_IFDIR | 0755);
++ if (!root_inode)
++ return -ENOMEM;
++ root_inode->i_op = &simple_dir_inode_operations;
++ root_inode->i_fop = &simple_dir_operations;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)
++ root_dentry = d_alloc_root(root_inode);
++#else
++ root_dentry = d_make_root(root_inode);
++#endif
++
++ if (!root_dentry) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)
++ iput(root_inode);
++#endif
++ return -ENOMEM;
++ }
++
++ sb->s_root = root_dentry;
++
++ gator_op_create_files(sb, root_dentry);
++
++ return 0;
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++static int gatorfs_get_sb(struct file_system_type *fs_type,
++ int flags, const char *dev_name, void *data,
++ struct vfsmount *mnt)
++{
++ return get_sb_single(fs_type, flags, data, gatorfs_fill_super, mnt);
++}
++#else
++static struct dentry *gatorfs_mount(struct file_system_type *fs_type,
++ int flags, const char *dev_name, void *data)
++{
++ return mount_nodev(fs_type, flags, data, gatorfs_fill_super);
++}
++#endif
++
++static struct file_system_type gatorfs_type = {
++ .owner = THIS_MODULE,
++ .name = "gatorfs",
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39)
++ .get_sb = gatorfs_get_sb,
++#else
++ .mount = gatorfs_mount,
++#endif
++
++ .kill_sb = kill_litter_super,
++};
++
++int __init gatorfs_register(void)
++{
++ return register_filesystem(&gatorfs_type);
++}
++
++void gatorfs_unregister(void)
++{
++ unregister_filesystem(&gatorfs_type);
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator.h linux-linaro-stable-mx6/drivers/gator/gator.h
+--- linux-3.10.30.orig/drivers/gator/gator.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator.h 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,142 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef GATOR_H_
++#define GATOR_H_
++
++#include <linux/version.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/list.h>
++
++#define GATOR_PERF_SUPPORT LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
++#define GATOR_PERF_PMU_SUPPORT GATOR_PERF_SUPPORT && defined(CONFIG_PERF_EVENTS) && (!(defined(__arm__) || defined(__aarch64__)) || defined(CONFIG_HW_PERF_EVENTS))
++#define GATOR_NO_PERF_SUPPORT (!(GATOR_PERF_SUPPORT))
++#define GATOR_CPU_FREQ_SUPPORT (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) && defined(CONFIG_CPU_FREQ)
++#define GATOR_IKS_SUPPORT defined(CONFIG_BL_SWITCHER)
++
++// cpu ids
++#define ARM1136 0xb36
++#define ARM1156 0xb56
++#define ARM1176 0xb76
++#define ARM11MPCORE 0xb02
++#define CORTEX_A5 0xc05
++#define CORTEX_A7 0xc07
++#define CORTEX_A8 0xc08
++#define CORTEX_A9 0xc09
++#define CORTEX_A12 0xc0d
++#define CORTEX_A15 0xc0f
++#define SCORPION 0x00f
++#define SCORPIONMP 0x02d
++#define KRAITSIM 0x049
++#define KRAIT 0x04d
++#define KRAIT_S4_PRO 0x06f
++#define CORTEX_A53 0xd03
++#define CORTEX_A57 0xd07
++#define AARCH64 0xd0f
++#define OTHER 0xfff
++
++#define MAXSIZE_CORE_NAME 32
++
++struct gator_cpu {
++ const int cpuid;
++ // Human readable name
++ const char core_name[MAXSIZE_CORE_NAME];
++ // Perf PMU name
++ const char * const pmu_name;
++ // gatorfs event name
++ const char * const pmnc_name;
++ // compatible from Documentation/devicetree/bindings/arm/cpus.txt
++ const char * const dt_name;
++ const int pmnc_counters;
++};
++
++const struct gator_cpu *gator_find_cpu_by_cpuid(const u32 cpuid);
++const struct gator_cpu *gator_find_cpu_by_pmu_name(const char *const name);
++
++/******************************************************************************
++ * Filesystem
++ ******************************************************************************/
++int gatorfs_create_file_perm(struct super_block *sb, struct dentry *root,
++ char const *name,
++ const struct file_operations *fops, int perm);
++
++struct dentry *gatorfs_mkdir(struct super_block *sb, struct dentry *root,
++ char const *name);
++
++int gatorfs_create_ulong(struct super_block *sb, struct dentry *root,
++ char const *name, unsigned long *val);
++
++int gatorfs_create_ro_ulong(struct super_block *sb, struct dentry *root,
++ char const *name, unsigned long *val);
++
++void gator_op_create_files(struct super_block *sb, struct dentry *root);
++
++/******************************************************************************
++ * Tracepoints
++ ******************************************************************************/
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 32)
++# error Kernels prior to 2.6.32 not supported
++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
++# define GATOR_DEFINE_PROBE(probe_name, proto) \
++ static void probe_##probe_name(PARAMS(proto))
++# define GATOR_REGISTER_TRACE(probe_name) \
++ register_trace_##probe_name(probe_##probe_name)
++# define GATOR_UNREGISTER_TRACE(probe_name) \
++ unregister_trace_##probe_name(probe_##probe_name)
++#else
++# define GATOR_DEFINE_PROBE(probe_name, proto) \
++ static void probe_##probe_name(void *data, PARAMS(proto))
++# define GATOR_REGISTER_TRACE(probe_name) \
++ register_trace_##probe_name(probe_##probe_name, NULL)
++# define GATOR_UNREGISTER_TRACE(probe_name) \
++ unregister_trace_##probe_name(probe_##probe_name, NULL)
++#endif
++
++/******************************************************************************
++ * Events
++ ******************************************************************************/
++struct gator_interface {
++ void (*shutdown)(void); // Complementary function to init
++ int (*create_files)(struct super_block *sb, struct dentry *root);
++ int (*start)(void);
++ void (*stop)(void); // Complementary function to start
++ int (*online)(int **buffer, bool migrate);
++ int (*offline)(int **buffer, bool migrate);
++ void (*online_dispatch)(int cpu, bool migrate); // called in process context but may not be running on core 'cpu'
++ void (*offline_dispatch)(int cpu, bool migrate); // called in process context but may not be running on core 'cpu'
++ int (*read)(int **buffer);
++ int (*read64)(long long **buffer);
++ int (*read_proc)(long long **buffer, struct task_struct *);
++ struct list_head list;
++};
++
++int gator_events_install(struct gator_interface *interface);
++int gator_events_get_key(void);
++u32 gator_cpuid(void);
++
++void gator_backtrace_handler(struct pt_regs *const regs);
++
++#if !GATOR_IKS_SUPPORT
++
++#define get_physical_cpu() smp_processor_id()
++#define lcpu_to_pcpu(lcpu) lcpu
++#define pcpu_to_lcpu(pcpu) pcpu
++
++#else
++
++#define get_physical_cpu() lcpu_to_pcpu(get_logical_cpu())
++int lcpu_to_pcpu(const int lcpu);
++int pcpu_to_lcpu(const int pcpu);
++
++#endif
++
++#define get_logical_cpu() smp_processor_id()
++#define on_primary_core() (get_logical_cpu() == 0)
++
++#endif // GATOR_H_
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_hrtimer_gator.c linux-linaro-stable-mx6/drivers/gator/gator_hrtimer_gator.c
+--- linux-3.10.30.orig/drivers/gator/gator_hrtimer_gator.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_hrtimer_gator.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,86 @@
++/**
++ * Copyright (C) ARM Limited 2011-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++// gator_hrtimer_perf.c is used if perf is supported
++// update, gator_hrtimer_gator.c always used until issues resolved with perf hrtimers
++#if 1
++
++void (*callback)(void);
++DEFINE_PER_CPU(struct hrtimer, percpu_hrtimer);
++DEFINE_PER_CPU(ktime_t, hrtimer_expire);
++DEFINE_PER_CPU(int, hrtimer_is_active);
++static ktime_t profiling_interval;
++static void gator_hrtimer_online(void);
++static void gator_hrtimer_offline(void);
++
++static enum hrtimer_restart gator_hrtimer_notify(struct hrtimer *hrtimer)
++{
++ int cpu = get_logical_cpu();
++ hrtimer_forward(hrtimer, per_cpu(hrtimer_expire, cpu), profiling_interval);
++ per_cpu(hrtimer_expire, cpu) = ktime_add(per_cpu(hrtimer_expire, cpu), profiling_interval);
++ (*callback)();
++ return HRTIMER_RESTART;
++}
++
++static void gator_hrtimer_online(void)
++{
++ int cpu = get_logical_cpu();
++ struct hrtimer *hrtimer = &per_cpu(percpu_hrtimer, cpu);
++
++ if (per_cpu(hrtimer_is_active, cpu) || profiling_interval.tv64 == 0)
++ return;
++
++ per_cpu(hrtimer_is_active, cpu) = 1;
++ hrtimer_init(hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
++ hrtimer->function = gator_hrtimer_notify;
++#ifdef CONFIG_PREEMPT_RT_BASE
++ hrtimer->irqsafe = 1;
++#endif
++ per_cpu(hrtimer_expire, cpu) = ktime_add(hrtimer->base->get_time(), profiling_interval);
++ hrtimer_start(hrtimer, per_cpu(hrtimer_expire, cpu), HRTIMER_MODE_ABS_PINNED);
++}
++
++static void gator_hrtimer_offline(void)
++{
++ int cpu = get_logical_cpu();
++ struct hrtimer *hrtimer = &per_cpu(percpu_hrtimer, cpu);
++
++ if (!per_cpu(hrtimer_is_active, cpu))
++ return;
++
++ per_cpu(hrtimer_is_active, cpu) = 0;
++ hrtimer_cancel(hrtimer);
++}
++
++static int gator_hrtimer_init(int interval, void (*func)(void))
++{
++ int cpu;
++
++ (callback) = (func);
++
++ for_each_present_cpu(cpu) {
++ per_cpu(hrtimer_is_active, cpu) = 0;
++ }
++
++ // calculate profiling interval
++ if (interval > 0) {
++ profiling_interval = ns_to_ktime(1000000000UL / interval);
++ } else {
++ profiling_interval.tv64 = 0;
++ }
++
++ return 0;
++}
++
++static void gator_hrtimer_shutdown(void)
++{
++ /* empty */
++}
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_hrtimer_perf.c linux-linaro-stable-mx6/drivers/gator/gator_hrtimer_perf.c
+--- linux-3.10.30.orig/drivers/gator/gator_hrtimer_perf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_hrtimer_perf.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,113 @@
++/**
++ * Copyright (C) ARM Limited 2011-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++// gator_hrtimer_gator.c is used if perf is not supported
++// update, gator_hrtimer_gator.c always used until issues resolved with perf hrtimers
++#if 0
++
++// Note: perf Cortex support added in 2.6.35 and PERF_COUNT_SW_CPU_CLOCK/hrtimer broken on 2.6.35 and 2.6.36
++// not relevant as this code is not active until 3.0.0, but wanted to document the issue
++
++void (*callback)(void);
++static int profiling_interval;
++static DEFINE_PER_CPU(struct perf_event *, perf_hrtimer);
++static DEFINE_PER_CPU(struct perf_event_attr *, perf_hrtimer_attr);
++
++static void gator_hrtimer_shutdown(void);
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
++static void hrtimer_overflow_handler(struct perf_event *event, int unused, struct perf_sample_data *data, struct pt_regs *regs)
++#else
++static void hrtimer_overflow_handler(struct perf_event *event, struct perf_sample_data *data, struct pt_regs *regs)
++#endif
++{
++ (*callback)();
++}
++
++static int gator_online_single_hrtimer(int cpu)
++{
++ if (per_cpu(perf_hrtimer, cpu) != 0 || per_cpu(perf_hrtimer_attr, cpu) == 0)
++ return 0;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0)
++ per_cpu(perf_hrtimer, cpu) = perf_event_create_kernel_counter(per_cpu(perf_hrtimer_attr, cpu), cpu, 0, hrtimer_overflow_handler);
++#else
++ per_cpu(perf_hrtimer, cpu) = perf_event_create_kernel_counter(per_cpu(perf_hrtimer_attr, cpu), cpu, 0, hrtimer_overflow_handler, 0);
++#endif
++ if (IS_ERR(per_cpu(perf_hrtimer, cpu))) {
++ per_cpu(perf_hrtimer, cpu) = NULL;
++ return -1;
++ }
++
++ if (per_cpu(perf_hrtimer, cpu)->state != PERF_EVENT_STATE_ACTIVE) {
++ perf_event_release_kernel(per_cpu(perf_hrtimer, cpu));
++ per_cpu(perf_hrtimer, cpu) = NULL;
++ return -1;
++ }
++
++ return 0;
++}
++
++static void gator_hrtimer_online(int cpu)
++{
++ if (gator_online_single_hrtimer(cpu) < 0) {
++ pr_debug("gator: unable to online the hrtimer on cpu%d\n", cpu);
++ }
++}
++
++static void gator_hrtimer_offline(int cpu)
++{
++ if (per_cpu(perf_hrtimer, cpu)) {
++ perf_event_release_kernel(per_cpu(perf_hrtimer, cpu));
++ per_cpu(perf_hrtimer, cpu) = NULL;
++ }
++}
++
++static int gator_hrtimer_init(int interval, void (*func)(void))
++{
++ u32 size = sizeof(struct perf_event_attr);
++ int cpu;
++
++ callback = func;
++
++ // calculate profiling interval
++ profiling_interval = 1000000000 / interval;
++
++ for_each_present_cpu(cpu) {
++ per_cpu(perf_hrtimer, cpu) = 0;
++ per_cpu(perf_hrtimer_attr, cpu) = kmalloc(size, GFP_KERNEL);
++ if (per_cpu(perf_hrtimer_attr, cpu) == 0) {
++ gator_hrtimer_shutdown();
++ return -1;
++ }
++
++ memset(per_cpu(perf_hrtimer_attr, cpu), 0, size);
++ per_cpu(perf_hrtimer_attr, cpu)->type = PERF_TYPE_SOFTWARE;
++ per_cpu(perf_hrtimer_attr, cpu)->size = size;
++ per_cpu(perf_hrtimer_attr, cpu)->config = PERF_COUNT_SW_CPU_CLOCK;
++ per_cpu(perf_hrtimer_attr, cpu)->sample_period = profiling_interval;
++ per_cpu(perf_hrtimer_attr, cpu)->pinned = 1;
++ }
++
++ return 0;
++}
++
++static void gator_hrtimer_shutdown(void)
++{
++ int cpu;
++
++ for_each_present_cpu(cpu) {
++ if (per_cpu(perf_hrtimer_attr, cpu)) {
++ kfree(per_cpu(perf_hrtimer_attr, cpu));
++ per_cpu(perf_hrtimer_attr, cpu) = NULL;
++ }
++ }
++}
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_iks.c linux-linaro-stable-mx6/drivers/gator/gator_iks.c
+--- linux-3.10.30.orig/drivers/gator/gator_iks.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_iks.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,197 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#if GATOR_IKS_SUPPORT
++
++#include <linux/of.h>
++#include <asm/bL_switcher.h>
++#include <asm/smp_plat.h>
++#include <trace/events/power_cpu_migrate.h>
++
++static bool map_cpuids;
++static int mpidr_cpuids[NR_CPUS];
++static const struct gator_cpu * mpidr_cpus[NR_CPUS];
++static int __lcpu_to_pcpu[NR_CPUS];
++
++static const struct gator_cpu *gator_find_cpu_by_dt_name(const char *const name)
++{
++ int i;
++
++ for (i = 0; gator_cpus[i].cpuid != 0; ++i) {
++ const struct gator_cpu *const gator_cpu = &gator_cpus[i];
++ if (gator_cpu->dt_name != NULL && strcmp(gator_cpu->dt_name, name) == 0) {
++ return gator_cpu;
++ }
++ }
++
++ return NULL;
++}
++
++static void calc_first_cluster_size(void)
++{
++ int len;
++ const u32 *val;
++ const char *compatible;
++ struct device_node *cn = NULL;
++ int mpidr_cpuids_count = 0;
++
++ // Zero is a valid cpuid, so initialize the array to 0xff's
++ memset(&mpidr_cpuids, 0xff, sizeof(mpidr_cpuids));
++ memset(&mpidr_cpus, 0, sizeof(mpidr_cpus));
++
++ while ((cn = of_find_node_by_type(cn, "cpu"))) {
++ BUG_ON(mpidr_cpuids_count >= NR_CPUS);
++
++ val = of_get_property(cn, "reg", &len);
++ if (!val || len != 4) {
++ pr_err("%s missing reg property\n", cn->full_name);
++ continue;
++ }
++ compatible = of_get_property(cn, "compatible", NULL);
++ if (compatible == NULL) {
++ pr_err("%s missing compatible property\n", cn->full_name);
++ continue;
++ }
++
++ mpidr_cpuids[mpidr_cpuids_count] = be32_to_cpup(val);
++ mpidr_cpus[mpidr_cpuids_count] = gator_find_cpu_by_dt_name(compatible);
++ ++mpidr_cpuids_count;
++ }
++
++ map_cpuids = (mpidr_cpuids_count == nr_cpu_ids);
++}
++
++static int linearize_mpidr(int mpidr)
++{
++ int i;
++ for (i = 0; i < nr_cpu_ids; ++i) {
++ if (mpidr_cpuids[i] == mpidr) {
++ return i;
++ }
++ }
++
++ BUG();
++}
++
++int lcpu_to_pcpu(const int lcpu)
++{
++ int pcpu;
++
++ if (!map_cpuids)
++ return lcpu;
++
++ BUG_ON(lcpu >= nr_cpu_ids || lcpu < 0);
++ pcpu = __lcpu_to_pcpu[lcpu];
++ BUG_ON(pcpu >= nr_cpu_ids || pcpu < 0);
++ return pcpu;
++}
++
++int pcpu_to_lcpu(const int pcpu)
++{
++ int lcpu;
++
++ if (!map_cpuids)
++ return pcpu;
++
++ BUG_ON(pcpu >= nr_cpu_ids || pcpu < 0);
++ for (lcpu = 0; lcpu < nr_cpu_ids; ++lcpu) {
++ if (__lcpu_to_pcpu[lcpu] == pcpu) {
++ BUG_ON(lcpu >= nr_cpu_ids || lcpu < 0);
++ return lcpu;
++ }
++ }
++ BUG();
++}
++
++static void gator_update_cpu_mapping(u32 cpu_hwid)
++{
++ int lcpu = smp_processor_id();
++ int pcpu = linearize_mpidr(cpu_hwid & MPIDR_HWID_BITMASK);
++ BUG_ON(lcpu >= nr_cpu_ids || lcpu < 0);
++ BUG_ON(pcpu >= nr_cpu_ids || pcpu < 0);
++ __lcpu_to_pcpu[lcpu] = pcpu;
++}
++
++GATOR_DEFINE_PROBE(cpu_migrate_begin, TP_PROTO(u64 timestamp, u32 cpu_hwid))
++{
++ const int cpu = get_physical_cpu();
++
++ gator_timer_offline((void *)1);
++ gator_timer_offline_dispatch(cpu, true);
++}
++
++GATOR_DEFINE_PROBE(cpu_migrate_finish, TP_PROTO(u64 timestamp, u32 cpu_hwid))
++{
++ int cpu;
++
++ gator_update_cpu_mapping(cpu_hwid);
++
++ // get_physical_cpu must be called after gator_update_cpu_mapping
++ cpu = get_physical_cpu();
++ gator_timer_online_dispatch(cpu, true);
++ gator_timer_online((void *)1);
++}
++
++GATOR_DEFINE_PROBE(cpu_migrate_current, TP_PROTO(u64 timestamp, u32 cpu_hwid))
++{
++ gator_update_cpu_mapping(cpu_hwid);
++}
++
++static void gator_send_iks_core_names(void)
++{
++ int cpu;
++ // Send the cpu names
++ preempt_disable();
++ for (cpu = 0; cpu < nr_cpu_ids; ++cpu) {
++ if (mpidr_cpus[cpu] != NULL) {
++ gator_send_core_name(cpu, mpidr_cpus[cpu]->cpuid, mpidr_cpus[cpu]);
++ }
++ }
++ preempt_enable();
++}
++
++static int gator_migrate_start(void)
++{
++ int retval = 0;
++
++ if (!map_cpuids)
++ return retval;
++
++ if (retval == 0)
++ retval = GATOR_REGISTER_TRACE(cpu_migrate_begin);
++ if (retval == 0)
++ retval = GATOR_REGISTER_TRACE(cpu_migrate_finish);
++ if (retval == 0)
++ retval = GATOR_REGISTER_TRACE(cpu_migrate_current);
++ if (retval == 0) {
++ // Initialize the logical to physical cpu mapping
++ memset(&__lcpu_to_pcpu, 0xff, sizeof(__lcpu_to_pcpu));
++ bL_switcher_trace_trigger();
++ }
++ return retval;
++}
++
++static void gator_migrate_stop(void)
++{
++ if (!map_cpuids)
++ return;
++
++ GATOR_UNREGISTER_TRACE(cpu_migrate_current);
++ GATOR_UNREGISTER_TRACE(cpu_migrate_finish);
++ GATOR_UNREGISTER_TRACE(cpu_migrate_begin);
++}
++
++#else
++
++#define calc_first_cluster_size()
++#define gator_send_iks_core_names()
++#define gator_migrate_start() 0
++#define gator_migrate_stop()
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_main.c linux-linaro-stable-mx6/drivers/gator/gator_main.c
+--- linux-3.10.30.orig/drivers/gator/gator_main.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_main.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,1532 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++// This version must match the gator daemon version
++#define PROTOCOL_VERSION 17
++static unsigned long gator_protocol_version = PROTOCOL_VERSION;
++
++#include <linux/slab.h>
++#include <linux/cpu.h>
++#include <linux/sched.h>
++#include <linux/irq.h>
++#include <linux/vmalloc.h>
++#include <linux/hardirq.h>
++#include <linux/highmem.h>
++#include <linux/pagemap.h>
++#include <linux/suspend.h>
++#include <linux/module.h>
++#include <linux/perf_event.h>
++#include <linux/utsname.h>
++#include <linux/kthread.h>
++#include <asm/stacktrace.h>
++#include <asm/uaccess.h>
++
++#include "gator.h"
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 32)
++#error kernels prior to 2.6.32 are not supported
++#endif
++
++#if defined(MODULE) && !defined(CONFIG_MODULES)
++#error Cannot build a module against a kernel that does not support modules. To resolve, either rebuild the kernel to support modules or build gator as part of the kernel.
++#endif
++
++#if !defined(CONFIG_GENERIC_TRACER) && !defined(CONFIG_TRACING)
++#error gator requires the kernel to have CONFIG_GENERIC_TRACER or CONFIG_TRACING defined
++#endif
++
++#ifndef CONFIG_PROFILING
++#error gator requires the kernel to have CONFIG_PROFILING defined
++#endif
++
++#ifndef CONFIG_HIGH_RES_TIMERS
++#error gator requires the kernel to have CONFIG_HIGH_RES_TIMERS defined to support PC sampling
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 12, 0) && defined(__arm__) && defined(CONFIG_SMP) && !defined(CONFIG_LOCAL_TIMERS)
++#error gator requires the kernel to have CONFIG_LOCAL_TIMERS defined on SMP systems
++#endif
++
++#if (GATOR_PERF_SUPPORT) && (!(GATOR_PERF_PMU_SUPPORT))
++#ifndef CONFIG_PERF_EVENTS
++#warning gator requires the kernel to have CONFIG_PERF_EVENTS defined to support pmu hardware counters
++#elif !defined CONFIG_HW_PERF_EVENTS
++#warning gator requires the kernel to have CONFIG_HW_PERF_EVENTS defined to support pmu hardware counters
++#endif
++#endif
++
++/******************************************************************************
++ * DEFINES
++ ******************************************************************************/
++#define SUMMARY_BUFFER_SIZE (1*1024)
++#define BACKTRACE_BUFFER_SIZE (128*1024)
++#define NAME_BUFFER_SIZE (64*1024)
++#define COUNTER_BUFFER_SIZE (64*1024) // counters have the core as part of the data and the core value in the frame header may be discarded
++#define BLOCK_COUNTER_BUFFER_SIZE (128*1024)
++#define ANNOTATE_BUFFER_SIZE (128*1024) // annotate counters have the core as part of the data and the core value in the frame header may be discarded
++#define SCHED_TRACE_BUFFER_SIZE (128*1024)
++#define GPU_TRACE_BUFFER_SIZE (64*1024) // gpu trace counters have the core as part of the data and the core value in the frame header may be discarded
++#define IDLE_BUFFER_SIZE (32*1024) // idle counters have the core as part of the data and the core value in the frame header may be discarded
++
++#define NO_COOKIE 0U
++#define UNRESOLVED_COOKIE ~0U
++
++#define FRAME_SUMMARY 1
++#define FRAME_BACKTRACE 2
++#define FRAME_NAME 3
++#define FRAME_COUNTER 4
++#define FRAME_BLOCK_COUNTER 5
++#define FRAME_ANNOTATE 6
++#define FRAME_SCHED_TRACE 7
++#define FRAME_GPU_TRACE 8
++#define FRAME_IDLE 9
++
++#define MESSAGE_END_BACKTRACE 1
++
++#define MESSAGE_COOKIE 1
++#define MESSAGE_THREAD_NAME 2
++#define HRTIMER_CORE_NAME 3
++#define MESSAGE_LINK 4
++
++#define MESSAGE_GPU_START 1
++#define MESSAGE_GPU_STOP 2
++
++#define MESSAGE_SCHED_SWITCH 1
++#define MESSAGE_SCHED_EXIT 2
++#define MESSAGE_SCHED_START 3
++
++#define MESSAGE_IDLE_ENTER 1
++#define MESSAGE_IDLE_EXIT 2
++
++#define MAXSIZE_PACK32 5
++#define MAXSIZE_PACK64 10
++
++#define FRAME_HEADER_SIZE 3
++
++#if defined(__arm__)
++#define PC_REG regs->ARM_pc
++#elif defined(__aarch64__)
++#define PC_REG regs->pc
++#else
++#define PC_REG regs->ip
++#endif
++
++enum {
++ SUMMARY_BUF,
++ BACKTRACE_BUF,
++ NAME_BUF,
++ COUNTER_BUF,
++ BLOCK_COUNTER_BUF,
++ ANNOTATE_BUF,
++ SCHED_TRACE_BUF,
++ GPU_TRACE_BUF,
++ IDLE_BUF,
++ NUM_GATOR_BUFS
++};
++
++/******************************************************************************
++ * Globals
++ ******************************************************************************/
++static unsigned long gator_cpu_cores;
++// Size of the largest buffer. Effectively constant, set in gator_op_create_files
++static unsigned long userspace_buffer_size;
++static unsigned long gator_backtrace_depth;
++// How often to commit the buffers for live in nanoseconds
++static u64 gator_live_rate;
++
++static unsigned long gator_started;
++static u64 gator_monotonic_started;
++static u64 gator_hibernate_time;
++static unsigned long gator_buffer_opened;
++static unsigned long gator_timer_count;
++static unsigned long gator_response_type;
++static DEFINE_MUTEX(start_mutex);
++static DEFINE_MUTEX(gator_buffer_mutex);
++
++bool event_based_sampling;
++
++static DECLARE_WAIT_QUEUE_HEAD(gator_buffer_wait);
++static DECLARE_WAIT_QUEUE_HEAD(gator_annotate_wait);
++static struct timer_list gator_buffer_wake_up_timer;
++static bool gator_buffer_wake_stop;
++static struct task_struct *gator_buffer_wake_thread;
++static LIST_HEAD(gator_events);
++
++static DEFINE_PER_CPU(u64, last_timestamp);
++
++static bool printed_monotonic_warning;
++
++static bool sent_core_name[NR_CPUS];
++
++/******************************************************************************
++ * Prototypes
++ ******************************************************************************/
++static void buffer_check(int cpu, int buftype, u64 time);
++static void gator_commit_buffer(int cpu, int buftype, u64 time);
++static int buffer_bytes_available(int cpu, int buftype);
++static bool buffer_check_space(int cpu, int buftype, int bytes);
++static int contiguous_space_available(int cpu, int bufytpe);
++static void gator_buffer_write_packed_int(int cpu, int buftype, int x);
++static void gator_buffer_write_packed_int64(int cpu, int buftype, long long x);
++static void gator_buffer_write_bytes(int cpu, int buftype, const char *x, int len);
++static void gator_buffer_write_string(int cpu, int buftype, const char *x);
++static void gator_add_trace(int cpu, unsigned long address);
++static void gator_add_sample(int cpu, struct pt_regs *const regs, u64 time);
++static u64 gator_get_time(void);
++
++// Size of the buffer, must be a power of 2. Effectively constant, set in gator_op_setup.
++static uint32_t gator_buffer_size[NUM_GATOR_BUFS];
++// gator_buffer_size - 1, bitwise and with pos to get offset into the array. Effectively constant, set in gator_op_setup.
++static uint32_t gator_buffer_mask[NUM_GATOR_BUFS];
++// Read position in the buffer. Initialized to zero in gator_op_setup and incremented after bytes are read by userspace in userspace_buffer_read
++static DEFINE_PER_CPU(int[NUM_GATOR_BUFS], gator_buffer_read);
++// Write position in the buffer. Initialized to zero in gator_op_setup and incremented after bytes are written to the buffer
++static DEFINE_PER_CPU(int[NUM_GATOR_BUFS], gator_buffer_write);
++// Commit position in the buffer. Initialized to zero in gator_op_setup and incremented after a frame is ready to be read by userspace
++static DEFINE_PER_CPU(int[NUM_GATOR_BUFS], gator_buffer_commit);
++// If set to false, decreases the number of bytes returned by buffer_bytes_available. Set in buffer_check_space if no space is remaining. Initialized to true in gator_op_setup
++// This means that if we run out of space, continue to report that no space is available until bytes are read by userspace
++static DEFINE_PER_CPU(int[NUM_GATOR_BUFS], buffer_space_available);
++// The buffer. Allocated in gator_op_setup
++static DEFINE_PER_CPU(char *[NUM_GATOR_BUFS], gator_buffer);
++// The time after which the buffer should be committed for live display
++static DEFINE_PER_CPU(u64, gator_buffer_commit_time);
++
++// List of all gator events - new events must be added to this list
++#define GATOR_EVENTS_LIST \
++ GATOR_EVENT(gator_events_armv6_init) \
++ GATOR_EVENT(gator_events_armv7_init) \
++ GATOR_EVENT(gator_events_block_init) \
++ GATOR_EVENT(gator_events_ccn504_init) \
++ GATOR_EVENT(gator_events_irq_init) \
++ GATOR_EVENT(gator_events_l2c310_init) \
++ GATOR_EVENT(gator_events_mali_init) \
++ GATOR_EVENT(gator_events_mali_t6xx_hw_init) \
++ GATOR_EVENT(gator_events_mali_t6xx_init) \
++ GATOR_EVENT(gator_events_meminfo_init) \
++ GATOR_EVENT(gator_events_mmapped_init) \
++ GATOR_EVENT(gator_events_net_init) \
++ GATOR_EVENT(gator_events_perf_pmu_init) \
++ GATOR_EVENT(gator_events_sched_init) \
++ GATOR_EVENT(gator_events_scorpion_init) \
++
++#define GATOR_EVENT(EVENT_INIT) __weak int EVENT_INIT(void);
++GATOR_EVENTS_LIST
++#undef GATOR_EVENT
++
++static int (*gator_events_list[])(void) = {
++#define GATOR_EVENT(EVENT_INIT) EVENT_INIT,
++GATOR_EVENTS_LIST
++#undef GATOR_EVENT
++};
++
++/******************************************************************************
++ * Application Includes
++ ******************************************************************************/
++#include "gator_marshaling.c"
++#include "gator_hrtimer_perf.c"
++#include "gator_hrtimer_gator.c"
++#include "gator_cookies.c"
++#include "gator_annotate.c"
++#include "gator_trace_sched.c"
++#include "gator_trace_power.c"
++#include "gator_trace_gpu.c"
++#include "gator_backtrace.c"
++#include "gator_fs.c"
++#include "gator_pack.c"
++
++/******************************************************************************
++ * Misc
++ ******************************************************************************/
++
++const struct gator_cpu gator_cpus[] = {
++ {
++ .cpuid = ARM1136,
++ .core_name = "ARM1136",
++ .pmnc_name = "ARM_ARM11",
++ .dt_name = "arm,arm1136",
++ .pmnc_counters = 3,
++ },
++ {
++ .cpuid = ARM1156,
++ .core_name = "ARM1156",
++ .pmnc_name = "ARM_ARM11",
++ .dt_name = "arm,arm1156",
++ .pmnc_counters = 3,
++ },
++ {
++ .cpuid = ARM1176,
++ .core_name = "ARM1176",
++ .pmnc_name = "ARM_ARM11",
++ .dt_name = "arm,arm1176",
++ .pmnc_counters = 3,
++ },
++ {
++ .cpuid = ARM11MPCORE,
++ .core_name = "ARM11MPCore",
++ .pmnc_name = "ARM_ARM11MPCore",
++ .dt_name = "arm,arm11mpcore",
++ .pmnc_counters = 3,
++ },
++ {
++ .cpuid = CORTEX_A5,
++ .core_name = "Cortex-A5",
++ .pmu_name = "ARMv7_Cortex_A5",
++ .pmnc_name = "ARM_Cortex-A5",
++ .dt_name = "arm,cortex-a5",
++ .pmnc_counters = 2,
++ },
++ {
++ .cpuid = CORTEX_A7,
++ .core_name = "Cortex-A7",
++ .pmu_name = "ARMv7_Cortex_A7",
++ .pmnc_name = "ARM_Cortex-A7",
++ .dt_name = "arm,cortex-a7",
++ .pmnc_counters = 4,
++ },
++ {
++ .cpuid = CORTEX_A8,
++ .core_name = "Cortex-A8",
++ .pmu_name = "ARMv7_Cortex_A8",
++ .pmnc_name = "ARM_Cortex-A8",
++ .dt_name = "arm,cortex-a8",
++ .pmnc_counters = 4,
++ },
++ {
++ .cpuid = CORTEX_A9,
++ .core_name = "Cortex-A9",
++ .pmu_name = "ARMv7_Cortex_A9",
++ .pmnc_name = "ARM_Cortex-A9",
++ .dt_name = "arm,cortex-a9",
++ .pmnc_counters = 6,
++ },
++ {
++ .cpuid = CORTEX_A12,
++ .core_name = "Cortex-A12",
++ .pmu_name = "ARMv7_Cortex_A12",
++ .pmnc_name = "ARM_Cortex-A12",
++ .dt_name = "arm,cortex-a12",
++ .pmnc_counters = 6,
++ },
++ {
++ .cpuid = CORTEX_A15,
++ .core_name = "Cortex-A15",
++ .pmu_name = "ARMv7_Cortex_A15",
++ .pmnc_name = "ARM_Cortex-A15",
++ .dt_name = "arm,cortex-a15",
++ .pmnc_counters = 6,
++ },
++ {
++ .cpuid = SCORPION,
++ .core_name = "Scorpion",
++ .pmnc_name = "Scorpion",
++ .pmnc_counters = 4,
++ },
++ {
++ .cpuid = SCORPIONMP,
++ .core_name = "ScorpionMP",
++ .pmnc_name = "ScorpionMP",
++ .pmnc_counters = 4,
++ },
++ {
++ .cpuid = KRAITSIM,
++ .core_name = "KraitSIM",
++ .pmnc_name = "Krait",
++ .pmnc_counters = 4,
++ },
++ {
++ .cpuid = KRAIT,
++ .core_name = "Krait",
++ .pmnc_name = "Krait",
++ .pmnc_counters = 4,
++ },
++ {
++ .cpuid = KRAIT_S4_PRO,
++ .core_name = "Krait S4 Pro",
++ .pmnc_name = "Krait",
++ .pmnc_counters = 4,
++ },
++ {
++ .cpuid = CORTEX_A53,
++ .core_name = "Cortex-A53",
++ .pmnc_name = "ARM_Cortex-A53",
++ .dt_name = "arm,cortex-a53",
++ .pmnc_counters = 6,
++ },
++ {
++ .cpuid = CORTEX_A57,
++ .core_name = "Cortex-A57",
++ .pmnc_name = "ARM_Cortex-A57",
++ .dt_name = "arm,cortex-a57",
++ .pmnc_counters = 6,
++ },
++ {
++ .cpuid = AARCH64,
++ .core_name = "AArch64",
++ .pmnc_name = "ARM_AArch64",
++ .pmnc_counters = 6,
++ },
++ {
++ .cpuid = OTHER,
++ .core_name = "Other",
++ .pmnc_name = "Other",
++ .pmnc_counters = 6,
++ },
++ {}
++};
++
++const struct gator_cpu *gator_find_cpu_by_cpuid(const u32 cpuid)
++{
++ int i;
++
++ for (i = 0; gator_cpus[i].cpuid != 0; ++i) {
++ const struct gator_cpu *const gator_cpu = &gator_cpus[i];
++ if (gator_cpu->cpuid == cpuid) {
++ return gator_cpu;
++ }
++ }
++
++ return NULL;
++}
++
++const struct gator_cpu *gator_find_cpu_by_pmu_name(const char *const name)
++{
++ int i;
++
++ for (i = 0; gator_cpus[i].cpuid != 0; ++i) {
++ const struct gator_cpu *const gator_cpu = &gator_cpus[i];
++ if (gator_cpu->pmu_name != NULL && strcmp(gator_cpu->pmu_name, name) == 0) {
++ return gator_cpu;
++ }
++ }
++
++ return NULL;
++}
++
++u32 gator_cpuid(void)
++{
++#if defined(__arm__) || defined(__aarch64__)
++ u32 val;
++#if !defined(__aarch64__)
++ asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (val));
++#else
++ asm volatile("mrs %0, midr_el1" : "=r" (val));
++#endif
++ return (val >> 4) & 0xfff;
++#else
++ return OTHER;
++#endif
++}
++
++static void gator_buffer_wake_up(unsigned long data)
++{
++ wake_up(&gator_buffer_wait);
++}
++
++static int gator_buffer_wake_func(void *data)
++{
++ while (!gator_buffer_wake_stop) {
++ set_current_state(TASK_INTERRUPTIBLE);
++ schedule();
++ if (gator_buffer_wake_stop) {
++ break;
++ }
++
++ gator_buffer_wake_up(0);
++ }
++
++ return 0;
++}
++
++/******************************************************************************
++ * Commit interface
++ ******************************************************************************/
++static bool buffer_commit_ready(int *cpu, int *buftype)
++{
++ int cpu_x, x;
++ for_each_present_cpu(cpu_x) {
++ for (x = 0; x < NUM_GATOR_BUFS; x++)
++ if (per_cpu(gator_buffer_commit, cpu_x)[x] != per_cpu(gator_buffer_read, cpu_x)[x]) {
++ *cpu = cpu_x;
++ *buftype = x;
++ return true;
++ }
++ }
++ *cpu = -1;
++ *buftype = -1;
++ return false;
++}
++
++/******************************************************************************
++ * Buffer management
++ ******************************************************************************/
++static int buffer_bytes_available(int cpu, int buftype)
++{
++ int remaining, filled;
++
++ filled = per_cpu(gator_buffer_write, cpu)[buftype] - per_cpu(gator_buffer_read, cpu)[buftype];
++ if (filled < 0) {
++ filled += gator_buffer_size[buftype];
++ }
++
++ remaining = gator_buffer_size[buftype] - filled;
++
++ if (per_cpu(buffer_space_available, cpu)[buftype]) {
++ // Give some extra room; also allows space to insert the overflow error packet
++ remaining -= 200;
++ } else {
++ // Hysteresis, prevents multiple overflow messages
++ remaining -= 2000;
++ }
++
++ return remaining;
++}
++
++static int contiguous_space_available(int cpu, int buftype)
++{
++ int remaining = buffer_bytes_available(cpu, buftype);
++ int contiguous = gator_buffer_size[buftype] - per_cpu(gator_buffer_write, cpu)[buftype];
++ if (remaining < contiguous)
++ return remaining;
++ else
++ return contiguous;
++}
++
++static bool buffer_check_space(int cpu, int buftype, int bytes)
++{
++ int remaining = buffer_bytes_available(cpu, buftype);
++
++ if (remaining < bytes) {
++ per_cpu(buffer_space_available, cpu)[buftype] = false;
++ } else {
++ per_cpu(buffer_space_available, cpu)[buftype] = true;
++ }
++
++ return per_cpu(buffer_space_available, cpu)[buftype];
++}
++
++static void gator_buffer_write_bytes(int cpu, int buftype, const char *x, int len)
++{
++ int i;
++ u32 write = per_cpu(gator_buffer_write, cpu)[buftype];
++ u32 mask = gator_buffer_mask[buftype];
++ char *buffer = per_cpu(gator_buffer, cpu)[buftype];
++
++ for (i = 0; i < len; i++) {
++ buffer[write] = x[i];
++ write = (write + 1) & mask;
++ }
++
++ per_cpu(gator_buffer_write, cpu)[buftype] = write;
++}
++
++static void gator_buffer_write_string(int cpu, int buftype, const char *x)
++{
++ int len = strlen(x);
++ gator_buffer_write_packed_int(cpu, buftype, len);
++ gator_buffer_write_bytes(cpu, buftype, x, len);
++}
++
++static void gator_commit_buffer(int cpu, int buftype, u64 time)
++{
++ int type_length, commit, length, byte;
++
++ if (!per_cpu(gator_buffer, cpu)[buftype])
++ return;
++
++ // post-populate the length, which does not include the response type length nor the length itself, i.e. only the length of the payload
++ type_length = gator_response_type ? 1 : 0;
++ commit = per_cpu(gator_buffer_commit, cpu)[buftype];
++ length = per_cpu(gator_buffer_write, cpu)[buftype] - commit;
++ if (length < 0) {
++ length += gator_buffer_size[buftype];
++ }
++ length = length - type_length - sizeof(s32);
++
++ if (length <= FRAME_HEADER_SIZE) {
++ // Nothing to write, only the frame header is present
++ return;
++ }
++
++ for (byte = 0; byte < sizeof(s32); byte++) {
++ per_cpu(gator_buffer, cpu)[buftype][(commit + type_length + byte) & gator_buffer_mask[buftype]] = (length >> byte * 8) & 0xFF;
++ }
++
++ per_cpu(gator_buffer_commit, cpu)[buftype] = per_cpu(gator_buffer_write, cpu)[buftype];
++
++ if (gator_live_rate > 0) {
++ while (time > per_cpu(gator_buffer_commit_time, cpu)) {
++ per_cpu(gator_buffer_commit_time, cpu) += gator_live_rate;
++ }
++ }
++
++ marshal_frame(cpu, buftype);
++
++ // had to delay scheduling work as attempting to schedule work during the context switch is illegal in kernel versions 3.5 and greater
++ if (per_cpu(in_scheduler_context, cpu)) {
++#ifndef CONFIG_PREEMPT_RT_FULL
++ // mod_timer can not be used in interrupt context in RT-Preempt full
++ mod_timer(&gator_buffer_wake_up_timer, jiffies + 1);
++#endif
++ } else {
++ wake_up_process(gator_buffer_wake_thread);
++ }
++}
++
++static void buffer_check(int cpu, int buftype, u64 time)
++{
++ int filled = per_cpu(gator_buffer_write, cpu)[buftype] - per_cpu(gator_buffer_commit, cpu)[buftype];
++ if (filled < 0) {
++ filled += gator_buffer_size[buftype];
++ }
++ if (filled >= ((gator_buffer_size[buftype] * 3) / 4)) {
++ gator_commit_buffer(cpu, buftype, time);
++ }
++}
++
++static void gator_add_trace(int cpu, unsigned long address)
++{
++ off_t offset = 0;
++ unsigned long cookie = get_address_cookie(cpu, current, address & ~1, &offset);
++
++ if (cookie == NO_COOKIE || cookie == UNRESOLVED_COOKIE) {
++ offset = address;
++ }
++
++ marshal_backtrace(offset & ~1, cookie);
++}
++
++static void gator_add_sample(int cpu, struct pt_regs *const regs, u64 time)
++{
++ bool inKernel;
++ unsigned long exec_cookie;
++
++ if (!regs)
++ return;
++
++ inKernel = !user_mode(regs);
++ exec_cookie = get_exec_cookie(cpu, current);
++
++ if (!marshal_backtrace_header(exec_cookie, current->tgid, current->pid, inKernel, time))
++ return;
++
++ if (inKernel) {
++ kernel_backtrace(cpu, regs);
++ } else {
++ // Cookie+PC
++ gator_add_trace(cpu, PC_REG);
++
++ // Backtrace
++ if (gator_backtrace_depth)
++ arm_backtrace_eabi(cpu, regs, gator_backtrace_depth);
++ }
++
++ marshal_backtrace_footer(time);
++}
++
++/******************************************************************************
++ * hrtimer interrupt processing
++ ******************************************************************************/
++static void gator_timer_interrupt(void)
++{
++ struct pt_regs *const regs = get_irq_regs();
++ gator_backtrace_handler(regs);
++}
++
++void gator_backtrace_handler(struct pt_regs *const regs)
++{
++ u64 time = gator_get_time();
++ int cpu = get_physical_cpu();
++
++ // Output backtrace
++ gator_add_sample(cpu, regs, time);
++
++ // Collect counters
++ if (!per_cpu(collecting, cpu)) {
++ collect_counters(time, NULL);
++ }
++
++ // No buffer flushing occurs during sched switch for RT-Preempt full. The block counter frame will be flushed by collect_counters, but the sched buffer needs to be explicitly flushed
++#ifdef CONFIG_PREEMPT_RT_FULL
++ buffer_check(cpu, SCHED_TRACE_BUF, time);
++#endif
++}
++
++static int gator_running;
++
++// This function runs in interrupt context and on the appropriate core
++static void gator_timer_offline(void *migrate)
++{
++ struct gator_interface *gi;
++ int i, len, cpu = get_physical_cpu();
++ int *buffer;
++ u64 time;
++
++ gator_trace_sched_offline();
++ gator_trace_power_offline();
++
++ if (!migrate) {
++ gator_hrtimer_offline();
++ }
++
++ // Offline any events and output counters
++ time = gator_get_time();
++ if (marshal_event_header(time)) {
++ list_for_each_entry(gi, &gator_events, list) {
++ if (gi->offline) {
++ len = gi->offline(&buffer, migrate);
++ marshal_event(len, buffer);
++ }
++ }
++ // Only check after writing all counters so that time and corresponding counters appear in the same frame
++ buffer_check(cpu, BLOCK_COUNTER_BUF, time);
++ }
++
++ // Flush all buffers on this core
++ for (i = 0; i < NUM_GATOR_BUFS; i++)
++ gator_commit_buffer(cpu, i, time);
++}
++
++// This function runs in interrupt context and may be running on a core other than core 'cpu'
++static void gator_timer_offline_dispatch(int cpu, bool migrate)
++{
++ struct gator_interface *gi;
++
++ list_for_each_entry(gi, &gator_events, list) {
++ if (gi->offline_dispatch) {
++ gi->offline_dispatch(cpu, migrate);
++ }
++ }
++}
++
++static void gator_timer_stop(void)
++{
++ int cpu;
++
++ if (gator_running) {
++ on_each_cpu(gator_timer_offline, NULL, 1);
++ for_each_online_cpu(cpu) {
++ gator_timer_offline_dispatch(lcpu_to_pcpu(cpu), false);
++ }
++
++ gator_running = 0;
++ gator_hrtimer_shutdown();
++ }
++}
++
++#if defined(__arm__) || defined(__aarch64__)
++static void gator_send_core_name(int cpu, const u32 cpuid, const struct gator_cpu *const gator_cpu) {
++ const char *core_name = NULL;
++ char core_name_buf[32];
++
++ if (!sent_core_name[cpu]) {
++ if (gator_cpu != NULL) {
++ core_name = gator_cpu->core_name;
++ } else {
++ snprintf(core_name_buf, sizeof(core_name_buf), "Unknown (0x%.3x)", cpuid);
++ core_name = core_name_buf;
++ }
++
++ marshal_core_name(cpu, cpuid, core_name);
++ sent_core_name[cpu] = true;
++ }
++}
++#endif
++
++// This function runs in interrupt context and on the appropriate core
++static void gator_timer_online(void *migrate)
++{
++ struct gator_interface *gi;
++ int len, cpu = get_physical_cpu();
++ int *buffer;
++ u64 time;
++
++ gator_trace_power_online();
++
++ // online any events and output counters
++ time = gator_get_time();
++ if (marshal_event_header(time)) {
++ list_for_each_entry(gi, &gator_events, list) {
++ if (gi->online) {
++ len = gi->online(&buffer, migrate);
++ marshal_event(len, buffer);
++ }
++ }
++ // Only check after writing all counters so that time and corresponding counters appear in the same frame
++ buffer_check(cpu, BLOCK_COUNTER_BUF, time);
++ }
++
++ if (!migrate) {
++ gator_hrtimer_online();
++ }
++
++#if defined(__arm__) || defined(__aarch64__)
++ if (!sent_core_name[cpu]) {
++ const u32 cpuid = gator_cpuid();
++ gator_send_core_name(cpu, cpuid, gator_find_cpu_by_cpuid(cpuid));
++ }
++#endif
++}
++
++// This function runs in interrupt context and may be running on a core other than core 'cpu'
++static void gator_timer_online_dispatch(int cpu, bool migrate)
++{
++ struct gator_interface *gi;
++
++ list_for_each_entry(gi, &gator_events, list) {
++ if (gi->online_dispatch) {
++ gi->online_dispatch(cpu, migrate);
++ }
++ }
++}
++
++#include "gator_iks.c"
++
++int gator_timer_start(unsigned long sample_rate)
++{
++ int cpu;
++
++ if (gator_running) {
++ pr_notice("gator: already running\n");
++ return 0;
++ }
++
++ gator_running = 1;
++
++ // event based sampling trumps hr timer based sampling
++ if (event_based_sampling) {
++ sample_rate = 0;
++ }
++
++ if (gator_hrtimer_init(sample_rate, gator_timer_interrupt) == -1)
++ return -1;
++
++ gator_send_iks_core_names();
++ for_each_online_cpu(cpu) {
++ gator_timer_online_dispatch(lcpu_to_pcpu(cpu), false);
++ }
++ on_each_cpu(gator_timer_online, NULL, 1);
++
++ return 0;
++}
++
++static u64 gator_get_time(void)
++{
++ struct timespec ts;
++ u64 timestamp;
++ u64 prev_timestamp;
++ u64 delta;
++ int cpu = smp_processor_id();
++
++ // Match clock_gettime(CLOCK_MONOTONIC_RAW, &ts) from userspace
++ getrawmonotonic(&ts);
++ timestamp = timespec_to_ns(&ts);
++
++ // getrawmonotonic is not monotonic on all systems. Detect and attempt to correct these cases.
++ // up to 0.5ms delta has been seen on some systems, which can skew Streamline data when viewing at high resolution.
++ // This doesn't work well with interrupts, but that it's OK - the real concern is to catch big jumps in time
++ prev_timestamp = per_cpu(last_timestamp, cpu);
++ if (prev_timestamp <= timestamp) {
++ per_cpu(last_timestamp, cpu) = timestamp;
++ } else {
++ delta = prev_timestamp - timestamp;
++ // Log the error once
++ if (!printed_monotonic_warning && delta > 500000) {
++ printk(KERN_ERR "%s: getrawmonotonic is not monotonic cpu: %i delta: %lli\nSkew in Streamline data may be present at the fine zoom levels\n", __FUNCTION__, cpu, delta);
++ printed_monotonic_warning = true;
++ }
++ timestamp = prev_timestamp;
++ }
++
++ return timestamp - gator_monotonic_started;
++}
++
++/******************************************************************************
++ * cpu hotplug and pm notifiers
++ ******************************************************************************/
++static int __cpuinit gator_hotcpu_notify(struct notifier_block *self, unsigned long action, void *hcpu)
++{
++ int cpu = lcpu_to_pcpu((long)hcpu);
++
++ switch (action) {
++ case CPU_DOWN_PREPARE:
++ case CPU_DOWN_PREPARE_FROZEN:
++ smp_call_function_single(cpu, gator_timer_offline, NULL, 1);
++ gator_timer_offline_dispatch(cpu, false);
++ break;
++ case CPU_ONLINE:
++ case CPU_ONLINE_FROZEN:
++ gator_timer_online_dispatch(cpu, false);
++ smp_call_function_single(cpu, gator_timer_online, NULL, 1);
++ break;
++ }
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block __refdata gator_hotcpu_notifier = {
++ .notifier_call = gator_hotcpu_notify,
++};
++
++// n.b. calling "on_each_cpu" only runs on those that are online
++// Registered linux events are not disabled, so their counters will continue to collect
++static int gator_pm_notify(struct notifier_block *nb, unsigned long event, void *dummy)
++{
++ int cpu;
++ struct timespec ts;
++
++ switch (event) {
++ case PM_HIBERNATION_PREPARE:
++ case PM_SUSPEND_PREPARE:
++ unregister_hotcpu_notifier(&gator_hotcpu_notifier);
++ unregister_scheduler_tracepoints();
++ on_each_cpu(gator_timer_offline, NULL, 1);
++ for_each_online_cpu(cpu) {
++ gator_timer_offline_dispatch(lcpu_to_pcpu(cpu), false);
++ }
++
++ // Record the wallclock hibernate time
++ getnstimeofday(&ts);
++ gator_hibernate_time = timespec_to_ns(&ts) - gator_get_time();
++ break;
++ case PM_POST_HIBERNATION:
++ case PM_POST_SUSPEND:
++ // Adjust gator_monotonic_started for the time spent sleeping, as gator_get_time does not account for it
++ if (gator_hibernate_time > 0) {
++ getnstimeofday(&ts);
++ gator_monotonic_started += gator_hibernate_time + gator_get_time() - timespec_to_ns(&ts);
++ gator_hibernate_time = 0;
++ }
++
++ for_each_online_cpu(cpu) {
++ gator_timer_online_dispatch(lcpu_to_pcpu(cpu), false);
++ }
++ on_each_cpu(gator_timer_online, NULL, 1);
++ register_scheduler_tracepoints();
++ register_hotcpu_notifier(&gator_hotcpu_notifier);
++ break;
++ }
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block gator_pm_notifier = {
++ .notifier_call = gator_pm_notify,
++};
++
++static int gator_notifier_start(void)
++{
++ int retval;
++ retval = register_hotcpu_notifier(&gator_hotcpu_notifier);
++ if (retval == 0)
++ retval = register_pm_notifier(&gator_pm_notifier);
++ return retval;
++}
++
++static void gator_notifier_stop(void)
++{
++ unregister_pm_notifier(&gator_pm_notifier);
++ unregister_hotcpu_notifier(&gator_hotcpu_notifier);
++}
++
++/******************************************************************************
++ * Main
++ ******************************************************************************/
++static void gator_summary(void)
++{
++ u64 timestamp, uptime;
++ struct timespec ts;
++ char uname_buf[512];
++ void (*m2b)(struct timespec *ts);
++ unsigned long flags;
++
++ snprintf(uname_buf, sizeof(uname_buf), "%s %s %s %s %s GNU/Linux", utsname()->sysname, utsname()->nodename, utsname()->release, utsname()->version, utsname()->machine);
++
++ getnstimeofday(&ts);
++ timestamp = timespec_to_ns(&ts);
++
++ do_posix_clock_monotonic_gettime(&ts);
++ // monotonic_to_bootbased is not defined for some versions of Android
++ m2b = symbol_get(monotonic_to_bootbased);
++ if (m2b) {
++ m2b(&ts);
++ }
++ uptime = timespec_to_ns(&ts);
++
++ // Disable interrupts as gator_get_time calls smp_processor_id to verify time is monotonic
++ local_irq_save(flags);
++ // Set monotonic_started to zero as gator_get_time is uptime minus monotonic_started
++ gator_monotonic_started = 0;
++ gator_monotonic_started = gator_get_time();
++ local_irq_restore(flags);
++
++ marshal_summary(timestamp, uptime, gator_monotonic_started, uname_buf);
++}
++
++int gator_events_install(struct gator_interface *interface)
++{
++ list_add_tail(&interface->list, &gator_events);
++
++ return 0;
++}
++
++int gator_events_get_key(void)
++{
++ // key 0 is reserved as a timestamp
++ // key 1 is reserved as the marker for thread specific counters
++ // Odd keys are assigned by the driver, even keys by the daemon
++ static int key = 3;
++
++ const int ret = key;
++ key += 2;
++ return ret;
++}
++
++static int gator_init(void)
++{
++ int i;
++
++ calc_first_cluster_size();
++
++ // events sources
++ for (i = 0; i < ARRAY_SIZE(gator_events_list); i++)
++ if (gator_events_list[i])
++ gator_events_list[i]();
++
++ gator_trace_sched_init();
++ gator_trace_power_init();
++
++ return 0;
++}
++
++static void gator_exit(void)
++{
++ struct gator_interface *gi;
++
++ list_for_each_entry(gi, &gator_events, list)
++ if (gi->shutdown)
++ gi->shutdown();
++}
++
++static int gator_start(void)
++{
++ unsigned long cpu, i;
++ struct gator_interface *gi;
++
++ gator_buffer_wake_stop = false;
++ if (IS_ERR(gator_buffer_wake_thread = kthread_run(gator_buffer_wake_func, NULL, "gator_bwake"))) {
++ goto bwake_failure;
++ }
++
++ if (gator_migrate_start())
++ goto migrate_failure;
++
++ // Initialize the buffer with the frame type and core
++ for_each_present_cpu(cpu) {
++ for (i = 0; i < NUM_GATOR_BUFS; i++) {
++ marshal_frame(cpu, i);
++ }
++ per_cpu(last_timestamp, cpu) = 0;
++ }
++ printed_monotonic_warning = false;
++
++ // Capture the start time
++ gator_summary();
++
++ // start all events
++ list_for_each_entry(gi, &gator_events, list) {
++ if (gi->start && gi->start() != 0) {
++ struct list_head *ptr = gi->list.prev;
++
++ while (ptr != &gator_events) {
++ gi = list_entry(ptr, struct gator_interface, list);
++
++ if (gi->stop)
++ gi->stop();
++
++ ptr = ptr->prev;
++ }
++ goto events_failure;
++ }
++ }
++
++ // cookies shall be initialized before trace_sched_start() and gator_timer_start()
++ if (cookies_initialize())
++ goto cookies_failure;
++ if (gator_annotate_start())
++ goto annotate_failure;
++ if (gator_trace_sched_start())
++ goto sched_failure;
++ if (gator_trace_power_start())
++ goto power_failure;
++ if (gator_trace_gpu_start())
++ goto gpu_failure;
++ if (gator_timer_start(gator_timer_count))
++ goto timer_failure;
++ if (gator_notifier_start())
++ goto notifier_failure;
++
++ return 0;
++
++notifier_failure:
++ gator_timer_stop();
++timer_failure:
++ gator_trace_gpu_stop();
++gpu_failure:
++ gator_trace_power_stop();
++power_failure:
++ gator_trace_sched_stop();
++sched_failure:
++ gator_annotate_stop();
++annotate_failure:
++ cookies_release();
++cookies_failure:
++ // stop all events
++ list_for_each_entry(gi, &gator_events, list)
++ if (gi->stop)
++ gi->stop();
++events_failure:
++ gator_migrate_stop();
++migrate_failure:
++ gator_buffer_wake_stop = true;
++ wake_up_process(gator_buffer_wake_thread);
++bwake_failure:
++
++ return -1;
++}
++
++static void gator_stop(void)
++{
++ struct gator_interface *gi;
++
++ gator_annotate_stop();
++ gator_trace_sched_stop();
++ gator_trace_power_stop();
++ gator_trace_gpu_stop();
++
++ // stop all interrupt callback reads before tearing down other interfaces
++ gator_notifier_stop(); // should be called before gator_timer_stop to avoid re-enabling the hrtimer after it has been offlined
++ gator_timer_stop();
++
++ // stop all events
++ list_for_each_entry(gi, &gator_events, list)
++ if (gi->stop)
++ gi->stop();
++
++ gator_migrate_stop();
++
++ gator_buffer_wake_stop = true;
++ wake_up_process(gator_buffer_wake_thread);
++}
++
++/******************************************************************************
++ * Filesystem
++ ******************************************************************************/
++/* fopen("buffer") */
++static int gator_op_setup(void)
++{
++ int err = 0;
++ int cpu, i;
++
++ mutex_lock(&start_mutex);
++
++ gator_buffer_size[SUMMARY_BUF] = SUMMARY_BUFFER_SIZE;
++ gator_buffer_mask[SUMMARY_BUF] = SUMMARY_BUFFER_SIZE - 1;
++
++ gator_buffer_size[BACKTRACE_BUF] = BACKTRACE_BUFFER_SIZE;
++ gator_buffer_mask[BACKTRACE_BUF] = BACKTRACE_BUFFER_SIZE - 1;
++
++ gator_buffer_size[NAME_BUF] = NAME_BUFFER_SIZE;
++ gator_buffer_mask[NAME_BUF] = NAME_BUFFER_SIZE - 1;
++
++ gator_buffer_size[COUNTER_BUF] = COUNTER_BUFFER_SIZE;
++ gator_buffer_mask[COUNTER_BUF] = COUNTER_BUFFER_SIZE - 1;
++
++ gator_buffer_size[BLOCK_COUNTER_BUF] = BLOCK_COUNTER_BUFFER_SIZE;
++ gator_buffer_mask[BLOCK_COUNTER_BUF] = BLOCK_COUNTER_BUFFER_SIZE - 1;
++
++ gator_buffer_size[ANNOTATE_BUF] = ANNOTATE_BUFFER_SIZE;
++ gator_buffer_mask[ANNOTATE_BUF] = ANNOTATE_BUFFER_SIZE - 1;
++
++ gator_buffer_size[SCHED_TRACE_BUF] = SCHED_TRACE_BUFFER_SIZE;
++ gator_buffer_mask[SCHED_TRACE_BUF] = SCHED_TRACE_BUFFER_SIZE - 1;
++
++ gator_buffer_size[GPU_TRACE_BUF] = GPU_TRACE_BUFFER_SIZE;
++ gator_buffer_mask[GPU_TRACE_BUF] = GPU_TRACE_BUFFER_SIZE - 1;
++
++ gator_buffer_size[IDLE_BUF] = IDLE_BUFFER_SIZE;
++ gator_buffer_mask[IDLE_BUF] = IDLE_BUFFER_SIZE - 1;
++
++ // Initialize percpu per buffer variables
++ for (i = 0; i < NUM_GATOR_BUFS; i++) {
++ // Verify buffers are a power of 2
++ if (gator_buffer_size[i] & (gator_buffer_size[i] - 1)) {
++ err = -ENOEXEC;
++ goto setup_error;
++ }
++
++ for_each_present_cpu(cpu) {
++ per_cpu(gator_buffer_read, cpu)[i] = 0;
++ per_cpu(gator_buffer_write, cpu)[i] = 0;
++ per_cpu(gator_buffer_commit, cpu)[i] = 0;
++ per_cpu(buffer_space_available, cpu)[i] = true;
++ per_cpu(gator_buffer_commit_time, cpu) = gator_live_rate;
++
++ // Annotation is a special case that only uses a single buffer
++ if (cpu > 0 && i == ANNOTATE_BUF) {
++ per_cpu(gator_buffer, cpu)[i] = NULL;
++ continue;
++ }
++
++ per_cpu(gator_buffer, cpu)[i] = vmalloc(gator_buffer_size[i]);
++ if (!per_cpu(gator_buffer, cpu)[i]) {
++ err = -ENOMEM;
++ goto setup_error;
++ }
++ }
++ }
++
++setup_error:
++ mutex_unlock(&start_mutex);
++ return err;
++}
++
++/* Actually start profiling (echo 1>/dev/gator/enable) */
++static int gator_op_start(void)
++{
++ int err = 0;
++
++ mutex_lock(&start_mutex);
++
++ if (gator_started || gator_start())
++ err = -EINVAL;
++ else
++ gator_started = 1;
++
++ mutex_unlock(&start_mutex);
++
++ return err;
++}
++
++/* echo 0>/dev/gator/enable */
++static void gator_op_stop(void)
++{
++ mutex_lock(&start_mutex);
++
++ if (gator_started) {
++ gator_stop();
++
++ mutex_lock(&gator_buffer_mutex);
++
++ gator_started = 0;
++ gator_monotonic_started = 0;
++ cookies_release();
++ wake_up(&gator_buffer_wait);
++
++ mutex_unlock(&gator_buffer_mutex);
++ }
++
++ mutex_unlock(&start_mutex);
++}
++
++static void gator_shutdown(void)
++{
++ int cpu, i;
++
++ mutex_lock(&start_mutex);
++
++ for_each_present_cpu(cpu) {
++ mutex_lock(&gator_buffer_mutex);
++ for (i = 0; i < NUM_GATOR_BUFS; i++) {
++ vfree(per_cpu(gator_buffer, cpu)[i]);
++ per_cpu(gator_buffer, cpu)[i] = NULL;
++ per_cpu(gator_buffer_read, cpu)[i] = 0;
++ per_cpu(gator_buffer_write, cpu)[i] = 0;
++ per_cpu(gator_buffer_commit, cpu)[i] = 0;
++ per_cpu(buffer_space_available, cpu)[i] = true;
++ per_cpu(gator_buffer_commit_time, cpu) = 0;
++ }
++ mutex_unlock(&gator_buffer_mutex);
++ }
++
++ memset(&sent_core_name, 0, sizeof(sent_core_name));
++
++ mutex_unlock(&start_mutex);
++}
++
++static int gator_set_backtrace(unsigned long val)
++{
++ int err = 0;
++
++ mutex_lock(&start_mutex);
++
++ if (gator_started)
++ err = -EBUSY;
++ else
++ gator_backtrace_depth = val;
++
++ mutex_unlock(&start_mutex);
++
++ return err;
++}
++
++static ssize_t enable_read(struct file *file, char __user *buf, size_t count, loff_t *offset)
++{
++ return gatorfs_ulong_to_user(gator_started, buf, count, offset);
++}
++
++static ssize_t enable_write(struct file *file, char const __user *buf, size_t count, loff_t *offset)
++{
++ unsigned long val;
++ int retval;
++
++ if (*offset)
++ return -EINVAL;
++
++ retval = gatorfs_ulong_from_user(&val, buf, count);
++ if (retval)
++ return retval;
++
++ if (val)
++ retval = gator_op_start();
++ else
++ gator_op_stop();
++
++ if (retval)
++ return retval;
++ return count;
++}
++
++static const struct file_operations enable_fops = {
++ .read = enable_read,
++ .write = enable_write,
++};
++
++static int userspace_buffer_open(struct inode *inode, struct file *file)
++{
++ int err = -EPERM;
++
++ if (!capable(CAP_SYS_ADMIN))
++ return -EPERM;
++
++ if (test_and_set_bit_lock(0, &gator_buffer_opened))
++ return -EBUSY;
++
++ if ((err = gator_op_setup()))
++ goto fail;
++
++ /* NB: the actual start happens from userspace
++ * echo 1 >/dev/gator/enable
++ */
++
++ return 0;
++
++fail:
++ __clear_bit_unlock(0, &gator_buffer_opened);
++ return err;
++}
++
++static int userspace_buffer_release(struct inode *inode, struct file *file)
++{
++ gator_op_stop();
++ gator_shutdown();
++ __clear_bit_unlock(0, &gator_buffer_opened);
++ return 0;
++}
++
++static ssize_t userspace_buffer_read(struct file *file, char __user *buf, size_t count, loff_t *offset)
++{
++ int commit, length1, length2, read;
++ char *buffer1;
++ char *buffer2;
++ int cpu, buftype;
++ int written = 0;
++
++ // ensure there is enough space for a whole frame
++ if (count < userspace_buffer_size || *offset) {
++ return -EINVAL;
++ }
++
++ // sleep until the condition is true or a signal is received
++ // the condition is checked each time gator_buffer_wait is woken up
++ wait_event_interruptible(gator_buffer_wait, buffer_commit_ready(&cpu, &buftype) || !gator_started);
++
++ if (signal_pending(current)) {
++ return -EINTR;
++ }
++
++ if (buftype == -1 || cpu == -1) {
++ return 0;
++ }
++
++ mutex_lock(&gator_buffer_mutex);
++
++ do {
++ read = per_cpu(gator_buffer_read, cpu)[buftype];
++ commit = per_cpu(gator_buffer_commit, cpu)[buftype];
++
++ // May happen if the buffer is freed during pending reads.
++ if (!per_cpu(gator_buffer, cpu)[buftype]) {
++ break;
++ }
++
++ // determine the size of two halves
++ length1 = commit - read;
++ length2 = 0;
++ buffer1 = &(per_cpu(gator_buffer, cpu)[buftype][read]);
++ buffer2 = &(per_cpu(gator_buffer, cpu)[buftype][0]);
++ if (length1 < 0) {
++ length1 = gator_buffer_size[buftype] - read;
++ length2 = commit;
++ }
++
++ if (length1 + length2 > count - written) {
++ break;
++ }
++
++ // start, middle or end
++ if (length1 > 0 && copy_to_user(&buf[written], buffer1, length1)) {
++ break;
++ }
++
++ // possible wrap around
++ if (length2 > 0 && copy_to_user(&buf[written + length1], buffer2, length2)) {
++ break;
++ }
++
++ per_cpu(gator_buffer_read, cpu)[buftype] = commit;
++ written += length1 + length2;
++
++ // Wake up annotate_write if more space is available
++ if (buftype == ANNOTATE_BUF) {
++ wake_up(&gator_annotate_wait);
++ }
++ } while (buffer_commit_ready(&cpu, &buftype));
++
++ mutex_unlock(&gator_buffer_mutex);
++
++ // kick just in case we've lost an SMP event
++ wake_up(&gator_buffer_wait);
++
++ return written > 0 ? written : -EFAULT;
++}
++
++const struct file_operations gator_event_buffer_fops = {
++ .open = userspace_buffer_open,
++ .release = userspace_buffer_release,
++ .read = userspace_buffer_read,
++};
++
++static ssize_t depth_read(struct file *file, char __user *buf, size_t count, loff_t *offset)
++{
++ return gatorfs_ulong_to_user(gator_backtrace_depth, buf, count, offset);
++}
++
++static ssize_t depth_write(struct file *file, char const __user *buf, size_t count, loff_t *offset)
++{
++ unsigned long val;
++ int retval;
++
++ if (*offset)
++ return -EINVAL;
++
++ retval = gatorfs_ulong_from_user(&val, buf, count);
++ if (retval)
++ return retval;
++
++ retval = gator_set_backtrace(val);
++
++ if (retval)
++ return retval;
++ return count;
++}
++
++static const struct file_operations depth_fops = {
++ .read = depth_read,
++ .write = depth_write
++};
++
++void gator_op_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++ struct gator_interface *gi;
++ int cpu;
++
++ /* reinitialize default values */
++ gator_cpu_cores = 0;
++ for_each_present_cpu(cpu) {
++ gator_cpu_cores++;
++ }
++ userspace_buffer_size = BACKTRACE_BUFFER_SIZE;
++ gator_response_type = 1;
++ gator_live_rate = 0;
++
++ gatorfs_create_file(sb, root, "enable", &enable_fops);
++ gatorfs_create_file(sb, root, "buffer", &gator_event_buffer_fops);
++ gatorfs_create_file(sb, root, "backtrace_depth", &depth_fops);
++ gatorfs_create_ro_ulong(sb, root, "cpu_cores", &gator_cpu_cores);
++ gatorfs_create_ro_ulong(sb, root, "buffer_size", &userspace_buffer_size);
++ gatorfs_create_ulong(sb, root, "tick", &gator_timer_count);
++ gatorfs_create_ulong(sb, root, "response_type", &gator_response_type);
++ gatorfs_create_ro_ulong(sb, root, "version", &gator_protocol_version);
++ gatorfs_create_ro_u64(sb, root, "started", &gator_monotonic_started);
++ gatorfs_create_u64(sb, root, "live_rate", &gator_live_rate);
++
++ // Annotate interface
++ gator_annotate_create_files(sb, root);
++
++ // Linux Events
++ dir = gatorfs_mkdir(sb, root, "events");
++ list_for_each_entry(gi, &gator_events, list)
++ if (gi->create_files)
++ gi->create_files(sb, dir);
++
++ // Sched Events
++ sched_trace_create_files(sb, dir);
++
++ // Power interface
++ gator_trace_power_create_files(sb, dir);
++}
++
++/******************************************************************************
++ * Module
++ ******************************************************************************/
++static int __init gator_module_init(void)
++{
++ if (gatorfs_register()) {
++ return -1;
++ }
++
++ if (gator_init()) {
++ gatorfs_unregister();
++ return -1;
++ }
++
++ setup_timer(&gator_buffer_wake_up_timer, gator_buffer_wake_up, 0);
++
++ return 0;
++}
++
++static void __exit gator_module_exit(void)
++{
++ del_timer_sync(&gator_buffer_wake_up_timer);
++ tracepoint_synchronize_unregister();
++ gator_exit();
++ gatorfs_unregister();
++}
++
++module_init(gator_module_init);
++module_exit(gator_module_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("ARM Ltd");
++MODULE_DESCRIPTION("Gator system profiler");
++#define STRIFY2(ARG) #ARG
++#define STRIFY(ARG) STRIFY2(ARG)
++MODULE_VERSION(STRIFY(PROTOCOL_VERSION));
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_marshaling.c linux-linaro-stable-mx6/drivers/gator/gator_marshaling.c
+--- linux-3.10.30.orig/drivers/gator/gator_marshaling.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_marshaling.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,432 @@
++/**
++ * Copyright (C) ARM Limited 2012-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#define NEWLINE_CANARY \
++ /* Unix */ \
++ "1\n" \
++ /* Windows */ \
++ "2\r\n" \
++ /* Mac OS */ \
++ "3\r" \
++ /* RISC OS */ \
++ "4\n\r" \
++ /* Add another character so the length isn't 0x0a bytes */ \
++ "5"
++
++#ifdef MALI_SUPPORT
++#include "gator_events_mali_common.h"
++#endif
++
++static void marshal_summary(long long timestamp, long long uptime, long long monotonic_delta, const char * uname)
++{
++ unsigned long flags;
++ int cpu = 0;
++
++ local_irq_save(flags);
++ gator_buffer_write_string(cpu, SUMMARY_BUF, NEWLINE_CANARY);
++ gator_buffer_write_packed_int64(cpu, SUMMARY_BUF, timestamp);
++ gator_buffer_write_packed_int64(cpu, SUMMARY_BUF, uptime);
++ gator_buffer_write_packed_int64(cpu, SUMMARY_BUF, monotonic_delta);
++ gator_buffer_write_string(cpu, SUMMARY_BUF, "uname");
++ gator_buffer_write_string(cpu, SUMMARY_BUF, uname);
++#if GATOR_IKS_SUPPORT
++ gator_buffer_write_string(cpu, SUMMARY_BUF, "iks");
++ gator_buffer_write_string(cpu, SUMMARY_BUF, "");
++#endif
++ // Let Streamline know which GPU is used so that it can label the GPU Activity appropriately. This is a temporary fix, to be improved in a future release.
++#ifdef MALI_SUPPORT
++ gator_buffer_write_string(cpu, SUMMARY_BUF, "mali_type");
++#if (MALI_SUPPORT == MALI_4xx)
++ gator_buffer_write_string(cpu, SUMMARY_BUF, "4xx");
++#elif (MALI_SUPPORT == MALI_T6xx)
++ gator_buffer_write_string(cpu, SUMMARY_BUF, "6xx");
++#else
++ gator_buffer_write_string(cpu, SUMMARY_BUF, "unknown");
++#endif
++#endif
++ gator_buffer_write_string(cpu, SUMMARY_BUF, "");
++ // Commit the buffer now so it can be one of the first frames read by Streamline
++ gator_commit_buffer(cpu, SUMMARY_BUF, gator_get_time());
++ local_irq_restore(flags);
++}
++
++static bool marshal_cookie_header(const char *text)
++{
++ int cpu = get_physical_cpu();
++ return buffer_check_space(cpu, NAME_BUF, strlen(text) + 3 * MAXSIZE_PACK32);
++}
++
++static void marshal_cookie(int cookie, const char *text)
++{
++ int cpu = get_physical_cpu();
++ // buffer_check_space already called by marshal_cookie_header
++ gator_buffer_write_packed_int(cpu, NAME_BUF, MESSAGE_COOKIE);
++ gator_buffer_write_packed_int(cpu, NAME_BUF, cookie);
++ gator_buffer_write_string(cpu, NAME_BUF, text);
++ buffer_check(cpu, NAME_BUF, gator_get_time());
++}
++
++static void marshal_thread_name(int pid, char *name)
++{
++ unsigned long flags, cpu;
++ u64 time;
++ local_irq_save(flags);
++ cpu = get_physical_cpu();
++ time = gator_get_time();
++ if (buffer_check_space(cpu, NAME_BUF, TASK_COMM_LEN + 3 * MAXSIZE_PACK32 + MAXSIZE_PACK64)) {
++ gator_buffer_write_packed_int(cpu, NAME_BUF, MESSAGE_THREAD_NAME);
++ gator_buffer_write_packed_int64(cpu, NAME_BUF, time);
++ gator_buffer_write_packed_int(cpu, NAME_BUF, pid);
++ gator_buffer_write_string(cpu, NAME_BUF, name);
++ }
++ buffer_check(cpu, NAME_BUF, time);
++ local_irq_restore(flags);
++}
++
++static void marshal_link(int cookie, int tgid, int pid)
++{
++ unsigned long cpu = get_physical_cpu(), flags;
++ u64 time;
++
++ local_irq_save(flags);
++ time = gator_get_time();
++ if (buffer_check_space(cpu, NAME_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) {
++ gator_buffer_write_packed_int(cpu, NAME_BUF, MESSAGE_LINK);
++ gator_buffer_write_packed_int64(cpu, NAME_BUF, time);
++ gator_buffer_write_packed_int(cpu, NAME_BUF, cookie);
++ gator_buffer_write_packed_int(cpu, NAME_BUF, tgid);
++ gator_buffer_write_packed_int(cpu, NAME_BUF, pid);
++ }
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, NAME_BUF, time);
++ local_irq_restore(flags);
++}
++
++static bool marshal_backtrace_header(int exec_cookie, int tgid, int pid, int inKernel, u64 time)
++{
++ int cpu = get_physical_cpu();
++ if (!buffer_check_space(cpu, BACKTRACE_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32 + gator_backtrace_depth * 2 * MAXSIZE_PACK32)) {
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, BACKTRACE_BUF, time);
++
++ return false;
++ }
++
++ gator_buffer_write_packed_int64(cpu, BACKTRACE_BUF, time);
++ gator_buffer_write_packed_int(cpu, BACKTRACE_BUF, exec_cookie);
++ gator_buffer_write_packed_int(cpu, BACKTRACE_BUF, tgid);
++ gator_buffer_write_packed_int(cpu, BACKTRACE_BUF, pid);
++ gator_buffer_write_packed_int(cpu, BACKTRACE_BUF, inKernel);
++
++ return true;
++}
++
++static void marshal_backtrace(unsigned long address, int cookie)
++{
++ int cpu = get_physical_cpu();
++ gator_buffer_write_packed_int(cpu, BACKTRACE_BUF, cookie);
++ gator_buffer_write_packed_int64(cpu, BACKTRACE_BUF, address);
++}
++
++static void marshal_backtrace_footer(u64 time)
++{
++ int cpu = get_physical_cpu();
++ gator_buffer_write_packed_int(cpu, BACKTRACE_BUF, MESSAGE_END_BACKTRACE);
++
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, BACKTRACE_BUF, time);
++}
++
++static bool marshal_event_header(u64 time)
++{
++ unsigned long flags, cpu = get_physical_cpu();
++ bool retval = false;
++
++ local_irq_save(flags);
++ if (buffer_check_space(cpu, BLOCK_COUNTER_BUF, MAXSIZE_PACK32 + MAXSIZE_PACK64)) {
++ gator_buffer_write_packed_int(cpu, BLOCK_COUNTER_BUF, 0); // key of zero indicates a timestamp
++ gator_buffer_write_packed_int64(cpu, BLOCK_COUNTER_BUF, time);
++ retval = true;
++ }
++ local_irq_restore(flags);
++
++ return retval;
++}
++
++static void marshal_event(int len, int *buffer)
++{
++ unsigned long i, flags, cpu = get_physical_cpu();
++
++ if (len <= 0)
++ return;
++
++ // length must be even since all data is a (key, value) pair
++ if (len & 0x1) {
++ pr_err("gator: invalid counter data detected and discarded");
++ return;
++ }
++
++ // events must be written in key,value pairs
++ local_irq_save(flags);
++ for (i = 0; i < len; i += 2) {
++ if (!buffer_check_space(cpu, BLOCK_COUNTER_BUF, 2 * MAXSIZE_PACK32)) {
++ break;
++ }
++ gator_buffer_write_packed_int(cpu, BLOCK_COUNTER_BUF, buffer[i]);
++ gator_buffer_write_packed_int(cpu, BLOCK_COUNTER_BUF, buffer[i + 1]);
++ }
++ local_irq_restore(flags);
++}
++
++static void marshal_event64(int len, long long *buffer64)
++{
++ unsigned long i, flags, cpu = get_physical_cpu();
++
++ if (len <= 0)
++ return;
++
++ // length must be even since all data is a (key, value) pair
++ if (len & 0x1) {
++ pr_err("gator: invalid counter data detected and discarded");
++ return;
++ }
++
++ // events must be written in key,value pairs
++ local_irq_save(flags);
++ for (i = 0; i < len; i += 2) {
++ if (!buffer_check_space(cpu, BLOCK_COUNTER_BUF, 2 * MAXSIZE_PACK64)) {
++ break;
++ }
++ gator_buffer_write_packed_int64(cpu, BLOCK_COUNTER_BUF, buffer64[i]);
++ gator_buffer_write_packed_int64(cpu, BLOCK_COUNTER_BUF, buffer64[i + 1]);
++ }
++ local_irq_restore(flags);
++}
++
++#if GATOR_CPU_FREQ_SUPPORT
++static void marshal_event_single(int core, int key, int value)
++{
++ unsigned long flags, cpu;
++ u64 time;
++
++ local_irq_save(flags);
++ cpu = get_physical_cpu();
++ time = gator_get_time();
++ if (buffer_check_space(cpu, COUNTER_BUF, MAXSIZE_PACK64 + 3 * MAXSIZE_PACK32)) {
++ gator_buffer_write_packed_int64(cpu, COUNTER_BUF, time);
++ gator_buffer_write_packed_int(cpu, COUNTER_BUF, core);
++ gator_buffer_write_packed_int(cpu, COUNTER_BUF, key);
++ gator_buffer_write_packed_int(cpu, COUNTER_BUF, value);
++ }
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, COUNTER_BUF, time);
++ local_irq_restore(flags);
++}
++#endif
++
++static void marshal_sched_gpu_start(int unit, int core, int tgid, int pid)
++{
++ unsigned long cpu = get_physical_cpu(), flags;
++ u64 time;
++
++ if (!per_cpu(gator_buffer, cpu)[GPU_TRACE_BUF])
++ return;
++
++ local_irq_save(flags);
++ time = gator_get_time();
++ if (buffer_check_space(cpu, GPU_TRACE_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) {
++ gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, MESSAGE_GPU_START);
++ gator_buffer_write_packed_int64(cpu, GPU_TRACE_BUF, time);
++ gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, unit);
++ gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, core);
++ gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, tgid);
++ gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, pid);
++ }
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, GPU_TRACE_BUF, time);
++ local_irq_restore(flags);
++}
++
++static void marshal_sched_gpu_stop(int unit, int core)
++{
++ unsigned long cpu = get_physical_cpu(), flags;
++ u64 time;
++
++ if (!per_cpu(gator_buffer, cpu)[GPU_TRACE_BUF])
++ return;
++
++ local_irq_save(flags);
++ time = gator_get_time();
++ if (buffer_check_space(cpu, GPU_TRACE_BUF, MAXSIZE_PACK64 + 3 * MAXSIZE_PACK32)) {
++ gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, MESSAGE_GPU_STOP);
++ gator_buffer_write_packed_int64(cpu, GPU_TRACE_BUF, time);
++ gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, unit);
++ gator_buffer_write_packed_int(cpu, GPU_TRACE_BUF, core);
++ }
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, GPU_TRACE_BUF, time);
++ local_irq_restore(flags);
++}
++
++static void marshal_sched_trace_start(int tgid, int pid, int cookie)
++{
++ unsigned long cpu = get_physical_cpu(), flags;
++ u64 time;
++
++ if (!per_cpu(gator_buffer, cpu)[SCHED_TRACE_BUF])
++ return;
++
++ local_irq_save(flags);
++ time = gator_get_time();
++ if (buffer_check_space(cpu, SCHED_TRACE_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) {
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, MESSAGE_SCHED_START);
++ gator_buffer_write_packed_int64(cpu, SCHED_TRACE_BUF, time);
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, tgid);
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, pid);
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, cookie);
++ }
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, SCHED_TRACE_BUF, time);
++ local_irq_restore(flags);
++}
++
++static void marshal_sched_trace_switch(int tgid, int pid, int cookie, int state)
++{
++ unsigned long cpu = get_physical_cpu(), flags;
++ u64 time;
++
++ if (!per_cpu(gator_buffer, cpu)[SCHED_TRACE_BUF])
++ return;
++
++ local_irq_save(flags);
++ time = gator_get_time();
++ if (buffer_check_space(cpu, SCHED_TRACE_BUF, MAXSIZE_PACK64 + 5 * MAXSIZE_PACK32)) {
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, MESSAGE_SCHED_SWITCH);
++ gator_buffer_write_packed_int64(cpu, SCHED_TRACE_BUF, time);
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, tgid);
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, pid);
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, cookie);
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, state);
++ }
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, SCHED_TRACE_BUF, time);
++ local_irq_restore(flags);
++}
++
++static void marshal_sched_trace_exit(int tgid, int pid)
++{
++ unsigned long cpu = get_physical_cpu(), flags;
++ u64 time;
++
++ if (!per_cpu(gator_buffer, cpu)[SCHED_TRACE_BUF])
++ return;
++
++ local_irq_save(flags);
++ time = gator_get_time();
++ if (buffer_check_space(cpu, SCHED_TRACE_BUF, MAXSIZE_PACK64 + 2 * MAXSIZE_PACK32)) {
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, MESSAGE_SCHED_EXIT);
++ gator_buffer_write_packed_int64(cpu, SCHED_TRACE_BUF, time);
++ gator_buffer_write_packed_int(cpu, SCHED_TRACE_BUF, pid);
++ }
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, SCHED_TRACE_BUF, time);
++ local_irq_restore(flags);
++}
++
++#if GATOR_CPU_FREQ_SUPPORT
++static void marshal_idle(int core, int state)
++{
++ unsigned long flags, cpu;
++ u64 time;
++
++ local_irq_save(flags);
++ cpu = get_physical_cpu();
++ time = gator_get_time();
++ if (buffer_check_space(cpu, IDLE_BUF, MAXSIZE_PACK64 + 2 * MAXSIZE_PACK32)) {
++ gator_buffer_write_packed_int(cpu, IDLE_BUF, state);
++ gator_buffer_write_packed_int64(cpu, IDLE_BUF, time);
++ gator_buffer_write_packed_int(cpu, IDLE_BUF, core);
++ }
++ // Check and commit; commit is set to occur once buffer is 3/4 full
++ buffer_check(cpu, IDLE_BUF, time);
++ local_irq_restore(flags);
++}
++#endif
++
++static void marshal_frame(int cpu, int buftype)
++{
++ int frame;
++
++ if (!per_cpu(gator_buffer, cpu)[buftype]) {
++ return;
++ }
++
++ switch (buftype) {
++ case SUMMARY_BUF:
++ frame = FRAME_SUMMARY;
++ break;
++ case BACKTRACE_BUF:
++ frame = FRAME_BACKTRACE;
++ break;
++ case NAME_BUF:
++ frame = FRAME_NAME;
++ break;
++ case COUNTER_BUF:
++ frame = FRAME_COUNTER;
++ break;
++ case BLOCK_COUNTER_BUF:
++ frame = FRAME_BLOCK_COUNTER;
++ break;
++ case ANNOTATE_BUF:
++ frame = FRAME_ANNOTATE;
++ break;
++ case SCHED_TRACE_BUF:
++ frame = FRAME_SCHED_TRACE;
++ break;
++ case GPU_TRACE_BUF:
++ frame = FRAME_GPU_TRACE;
++ break;
++ case IDLE_BUF:
++ frame = FRAME_IDLE;
++ break;
++ default:
++ frame = -1;
++ break;
++ }
++
++ // add response type
++ if (gator_response_type > 0) {
++ gator_buffer_write_packed_int(cpu, buftype, gator_response_type);
++ }
++
++ // leave space for 4-byte unpacked length
++ per_cpu(gator_buffer_write, cpu)[buftype] = (per_cpu(gator_buffer_write, cpu)[buftype] + sizeof(s32)) & gator_buffer_mask[buftype];
++
++ // add frame type and core number
++ gator_buffer_write_packed_int(cpu, buftype, frame);
++ gator_buffer_write_packed_int(cpu, buftype, cpu);
++}
++
++#if defined(__arm__) || defined(__aarch64__)
++static void marshal_core_name(const int core, const int cpuid, const char *name)
++{
++ int cpu = get_physical_cpu();
++ unsigned long flags;
++ local_irq_save(flags);
++ if (buffer_check_space(cpu, NAME_BUF, MAXSIZE_PACK32 + MAXSIZE_CORE_NAME)) {
++ gator_buffer_write_packed_int(cpu, NAME_BUF, HRTIMER_CORE_NAME);
++ gator_buffer_write_packed_int(cpu, NAME_BUF, core);
++ gator_buffer_write_packed_int(cpu, NAME_BUF, cpuid);
++ gator_buffer_write_string(cpu, NAME_BUF, name);
++ }
++ // Commit core names now so that they can show up in live
++ gator_commit_buffer(cpu, NAME_BUF, gator_get_time());
++ local_irq_restore(flags);
++}
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_pack.c linux-linaro-stable-mx6/drivers/gator/gator_pack.c
+--- linux-3.10.30.orig/drivers/gator/gator_pack.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_pack.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,58 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++static void gator_buffer_write_packed_int(int cpu, int buftype, int x)
++{
++ uint32_t write = per_cpu(gator_buffer_write, cpu)[buftype];
++ uint32_t mask = gator_buffer_mask[buftype];
++ char *buffer = per_cpu(gator_buffer, cpu)[buftype];
++ int packedBytes = 0;
++ int more = true;
++ while (more) {
++ // low order 7 bits of x
++ char b = x & 0x7f;
++ x >>= 7;
++
++ if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
++ more = false;
++ } else {
++ b |= 0x80;
++ }
++
++ buffer[(write + packedBytes) & mask] = b;
++ packedBytes++;
++ }
++
++ per_cpu(gator_buffer_write, cpu)[buftype] = (write + packedBytes) & mask;
++}
++
++static void gator_buffer_write_packed_int64(int cpu, int buftype, long long x)
++{
++ uint32_t write = per_cpu(gator_buffer_write, cpu)[buftype];
++ uint32_t mask = gator_buffer_mask[buftype];
++ char *buffer = per_cpu(gator_buffer, cpu)[buftype];
++ int packedBytes = 0;
++ int more = true;
++ while (more) {
++ // low order 7 bits of x
++ char b = x & 0x7f;
++ x >>= 7;
++
++ if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
++ more = false;
++ } else {
++ b |= 0x80;
++ }
++
++ buffer[(write + packedBytes) & mask] = b;
++ packedBytes++;
++ }
++
++ per_cpu(gator_buffer_write, cpu)[buftype] = (write + packedBytes) & mask;
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_trace_gpu.c linux-linaro-stable-mx6/drivers/gator/gator_trace_gpu.c
+--- linux-3.10.30.orig/drivers/gator/gator_trace_gpu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_trace_gpu.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,294 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "gator.h"
++
++#include <linux/slab.h>
++#include <linux/module.h>
++#include <linux/time.h>
++#include <linux/math64.h>
++
++#ifdef MALI_SUPPORT
++#include "linux/mali_linux_trace.h"
++#endif
++#include "gator_trace_gpu.h"
++
++/*
++ * Taken from MALI_PROFILING_EVENT_TYPE_* items in Mali DDK.
++ */
++#define EVENT_TYPE_SINGLE 0
++#define EVENT_TYPE_START 1
++#define EVENT_TYPE_STOP 2
++#define EVENT_TYPE_SUSPEND 3
++#define EVENT_TYPE_RESUME 4
++
++/* Note whether tracepoints have been registered */
++static int mali_timeline_trace_registered;
++static int mali_job_slots_trace_registered;
++static int gpu_trace_registered;
++
++enum {
++ GPU_UNIT_NONE = 0,
++ GPU_UNIT_VP,
++ GPU_UNIT_FP,
++ GPU_UNIT_CL,
++ NUMBER_OF_GPU_UNITS
++};
++
++#define MALI_4xx (0x0b07)
++#define MALI_T6xx (0x0056)
++
++struct mali_gpu_job {
++ int count;
++ int last_tgid;
++ int last_pid;
++ int last_job_id;
++};
++
++#define NUMBER_OF_GPU_CORES 16
++static struct mali_gpu_job mali_gpu_jobs[NUMBER_OF_GPU_UNITS][NUMBER_OF_GPU_CORES];
++static DEFINE_SPINLOCK(mali_gpu_jobs_lock);
++
++/* Only one event should be running on a unit and core at a time (ie, a start
++ * event can only be followed by a stop and vice versa), but because the kernel
++ * only knows when a job is enqueued and not started, it is possible for a
++ * start1, start2, stop1, stop2. Change it back into start1, stop1, start2,
++ * stop2 by queueing up start2 and releasing it when stop1 is received.
++ */
++static void mali_gpu_enqueue(int unit, int core, int tgid, int pid, int job_id)
++{
++ int count;
++
++ spin_lock(&mali_gpu_jobs_lock);
++ count = mali_gpu_jobs[unit][core].count;
++ BUG_ON(count < 0);
++ ++mali_gpu_jobs[unit][core].count;
++ if (count) {
++ mali_gpu_jobs[unit][core].last_tgid = tgid;
++ mali_gpu_jobs[unit][core].last_pid = pid;
++ mali_gpu_jobs[unit][core].last_job_id = job_id;
++ }
++ spin_unlock(&mali_gpu_jobs_lock);
++
++ if (!count) {
++ marshal_sched_gpu_start(unit, core, tgid, pid/*, job_id*/);
++ }
++}
++
++static void mali_gpu_stop(int unit, int core)
++{
++ int count;
++ int last_tgid = 0;
++ int last_pid = 0;
++ //int last_job_id = 0;
++
++ spin_lock(&mali_gpu_jobs_lock);
++ if (mali_gpu_jobs[unit][core].count == 0) {
++ spin_unlock(&mali_gpu_jobs_lock);
++ return;
++ }
++ --mali_gpu_jobs[unit][core].count;
++ count = mali_gpu_jobs[unit][core].count;
++ if (count) {
++ last_tgid = mali_gpu_jobs[unit][core].last_tgid;
++ last_pid = mali_gpu_jobs[unit][core].last_pid;
++ //last_job_id = mali_gpu_jobs[unit][core].last_job_id;
++ }
++ spin_unlock(&mali_gpu_jobs_lock);
++
++ marshal_sched_gpu_stop(unit, core);
++ if (count) {
++ marshal_sched_gpu_start(unit, core, last_tgid, last_pid/*, last_job_id*/);
++ }
++}
++
++#if defined(MALI_SUPPORT) && (MALI_SUPPORT != MALI_T6xx)
++#include "gator_events_mali_4xx.h"
++
++/*
++ * Taken from MALI_PROFILING_EVENT_CHANNEL_* in Mali DDK.
++ */
++enum {
++ EVENT_CHANNEL_SOFTWARE = 0,
++ EVENT_CHANNEL_VP0 = 1,
++ EVENT_CHANNEL_FP0 = 5,
++ EVENT_CHANNEL_FP1,
++ EVENT_CHANNEL_FP2,
++ EVENT_CHANNEL_FP3,
++ EVENT_CHANNEL_FP4,
++ EVENT_CHANNEL_FP5,
++ EVENT_CHANNEL_FP6,
++ EVENT_CHANNEL_FP7,
++ EVENT_CHANNEL_GPU = 21
++};
++
++/**
++ * These events are applicable when the type MALI_PROFILING_EVENT_TYPE_SINGLE is used from the GPU channel
++ */
++enum {
++ EVENT_REASON_SINGLE_GPU_NONE = 0,
++ EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE = 1,
++};
++
++GATOR_DEFINE_PROBE(mali_timeline_event, TP_PROTO(unsigned int event_id, unsigned int d0, unsigned int d1, unsigned int d2, unsigned int d3, unsigned int d4))
++{
++ unsigned int component, state;
++
++ // do as much work as possible before disabling interrupts
++ component = (event_id >> 16) & 0xFF; // component is an 8-bit field
++ state = (event_id >> 24) & 0xF; // state is a 4-bit field
++
++ switch (state) {
++ case EVENT_TYPE_START:
++ if (component == EVENT_CHANNEL_VP0) {
++ /* tgid = d0; pid = d1; */
++ mali_gpu_enqueue(GPU_UNIT_VP, 0, d0, d1, 0);
++ } else if (component >= EVENT_CHANNEL_FP0 && component <= EVENT_CHANNEL_FP7) {
++ /* tgid = d0; pid = d1; */
++ mali_gpu_enqueue(GPU_UNIT_FP, component - EVENT_CHANNEL_FP0, d0, d1, 0);
++ }
++ break;
++
++ case EVENT_TYPE_STOP:
++ if (component == EVENT_CHANNEL_VP0) {
++ mali_gpu_stop(GPU_UNIT_VP, 0);
++ } else if (component >= EVENT_CHANNEL_FP0 && component <= EVENT_CHANNEL_FP7) {
++ mali_gpu_stop(GPU_UNIT_FP, component - EVENT_CHANNEL_FP0);
++ }
++ break;
++
++ case EVENT_TYPE_SINGLE:
++ if (component == EVENT_CHANNEL_GPU) {
++ unsigned int reason = (event_id & 0xffff);
++
++ if (reason == EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE) {
++ gator_events_mali_log_dvfs_event(d0, d1);
++ }
++ }
++ break;
++
++ default:
++ break;
++ }
++}
++#endif
++
++#if defined(MALI_SUPPORT) && (MALI_SUPPORT == MALI_T6xx)
++#if defined(MALI_JOB_SLOTS_EVENT_CHANGED)
++GATOR_DEFINE_PROBE(mali_job_slots_event, TP_PROTO(unsigned int event_id, unsigned int tgid, unsigned int pid, unsigned char job_id))
++#else
++GATOR_DEFINE_PROBE(mali_job_slots_event, TP_PROTO(unsigned int event_id, unsigned int tgid, unsigned int pid))
++#endif
++{
++ unsigned int component, state, unit;
++#if !defined(MALI_JOB_SLOTS_EVENT_CHANGED)
++ unsigned char job_id = 0;
++#endif
++
++ component = (event_id >> 16) & 0xFF; // component is an 8-bit field
++ state = (event_id >> 24) & 0xF; // state is a 4-bit field
++
++ switch (component) {
++ case 0:
++ unit = GPU_UNIT_FP;
++ break;
++ case 1:
++ unit = GPU_UNIT_VP;
++ break;
++ case 2:
++ unit = GPU_UNIT_CL;
++ break;
++ default:
++ unit = GPU_UNIT_NONE;
++ }
++
++ if (unit != GPU_UNIT_NONE) {
++ switch (state) {
++ case EVENT_TYPE_START:
++ mali_gpu_enqueue(unit, 0, tgid, (pid != 0 ? pid : tgid), job_id);
++ break;
++ case EVENT_TYPE_STOP:
++ mali_gpu_stop(unit, 0);
++ break;
++ default:
++ /*
++ * Some jobs can be soft-stopped, so ensure that this terminates the activity trace.
++ */
++ mali_gpu_stop(unit, 0);
++ }
++ }
++}
++#endif
++
++GATOR_DEFINE_PROBE(gpu_activity_start, TP_PROTO(int gpu_unit, int gpu_core, struct task_struct *p))
++{
++ mali_gpu_enqueue(gpu_unit, gpu_core, (int)p->tgid, (int)p->pid, 0);
++}
++
++GATOR_DEFINE_PROBE(gpu_activity_stop, TP_PROTO(int gpu_unit, int gpu_core))
++{
++ mali_gpu_stop(gpu_unit, gpu_core);
++}
++
++int gator_trace_gpu_start(void)
++{
++ /*
++ * Returns nonzero for installation failed
++ * Absence of gpu trace points is not an error
++ */
++
++ memset(&mali_gpu_jobs, 0, sizeof(mali_gpu_jobs));
++ gpu_trace_registered = mali_timeline_trace_registered = mali_job_slots_trace_registered = 0;
++
++#if defined(MALI_SUPPORT) && (MALI_SUPPORT != MALI_T6xx)
++ if (!GATOR_REGISTER_TRACE(mali_timeline_event)) {
++ mali_timeline_trace_registered = 1;
++ }
++#endif
++
++#if defined(MALI_SUPPORT) && (MALI_SUPPORT == MALI_T6xx)
++ if (!GATOR_REGISTER_TRACE(mali_job_slots_event)) {
++ mali_job_slots_trace_registered = 1;
++ }
++#endif
++
++ if (!mali_timeline_trace_registered) {
++ if (GATOR_REGISTER_TRACE(gpu_activity_start)) {
++ return 0;
++ }
++ if (GATOR_REGISTER_TRACE(gpu_activity_stop)) {
++ GATOR_UNREGISTER_TRACE(gpu_activity_start);
++ return 0;
++ }
++ gpu_trace_registered = 1;
++ }
++
++ return 0;
++}
++
++void gator_trace_gpu_stop(void)
++{
++#if defined(MALI_SUPPORT) && (MALI_SUPPORT != MALI_T6xx)
++ if (mali_timeline_trace_registered) {
++ GATOR_UNREGISTER_TRACE(mali_timeline_event);
++ }
++#endif
++
++#if defined(MALI_SUPPORT) && (MALI_SUPPORT == MALI_T6xx)
++ if (mali_job_slots_trace_registered) {
++ GATOR_UNREGISTER_TRACE(mali_job_slots_event);
++ }
++#endif
++
++ if (gpu_trace_registered) {
++ GATOR_UNREGISTER_TRACE(gpu_activity_stop);
++ GATOR_UNREGISTER_TRACE(gpu_activity_start);
++ }
++
++ gpu_trace_registered = mali_timeline_trace_registered = mali_job_slots_trace_registered = 0;
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_trace_gpu.h linux-linaro-stable-mx6/drivers/gator/gator_trace_gpu.h
+--- linux-3.10.30.orig/drivers/gator/gator_trace_gpu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_trace_gpu.h 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,79 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#undef TRACE_GPU
++#define TRACE_GPU gpu
++
++#if !defined(_TRACE_GPU_H)
++#define _TRACE_GPU_H
++
++#include <linux/tracepoint.h>
++
++/*
++ * UNIT - the GPU processor type
++ * 1 = Vertex Processor
++ * 2 = Fragment Processor
++ *
++ * CORE - the GPU processor core number
++ * this is not the CPU core number
++ */
++
++/*
++ * Tracepoint for calling GPU unit start activity on core
++ */
++TRACE_EVENT(gpu_activity_start,
++
++ TP_PROTO(int gpu_unit, int gpu_core, struct task_struct *p),
++
++ TP_ARGS(gpu_unit, gpu_core, p),
++
++ TP_STRUCT__entry(
++ __field(int, gpu_unit)
++ __field(int, gpu_core)
++ __array(char, comm, TASK_COMM_LEN)
++ __field(pid_t, pid)
++ ),
++
++ TP_fast_assign(
++ __entry->gpu_unit = gpu_unit;
++ __entry->gpu_core = gpu_core;
++ memcpy(__entry->comm, p->comm, TASK_COMM_LEN);
++ __entry->pid = p->pid;
++ ),
++
++ TP_printk("unit=%d core=%d comm=%s pid=%d",
++ __entry->gpu_unit, __entry->gpu_core, __entry->comm,
++ __entry->pid)
++ );
++
++/*
++ * Tracepoint for calling GPU unit stop activity on core
++ */
++TRACE_EVENT(gpu_activity_stop,
++
++ TP_PROTO(int gpu_unit, int gpu_core),
++
++ TP_ARGS(gpu_unit, gpu_core),
++
++ TP_STRUCT__entry(
++ __field(int, gpu_unit)
++ __field(int, gpu_core)
++ ),
++
++ TP_fast_assign(
++ __entry->gpu_unit = gpu_unit;
++ __entry->gpu_core = gpu_core;
++ ),
++
++ TP_printk("unit=%d core=%d", __entry->gpu_unit, __entry->gpu_core)
++ );
++
++#endif /* _TRACE_GPU_H */
++
++/* This part must be outside protection */
++#include <trace/define_trace.h>
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_trace_power.c linux-linaro-stable-mx6/drivers/gator/gator_trace_power.c
+--- linux-3.10.30.orig/drivers/gator/gator_trace_power.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_trace_power.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,203 @@
++/**
++ * Copyright (C) ARM Limited 2011-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/cpufreq.h>
++#include <trace/events/power.h>
++
++#if defined(__arm__)
++
++#include <asm/mach-types.h>
++
++#define implements_wfi() (!machine_is_omap3_beagle())
++
++#else
++
++#define implements_wfi() false
++
++#endif
++
++// cpu_frequency and cpu_idle trace points were introduced in Linux kernel v2.6.38
++// the now deprecated power_frequency trace point was available prior to 2.6.38, but only for x86
++#if GATOR_CPU_FREQ_SUPPORT
++enum {
++ POWER_CPU_FREQ,
++ POWER_CPU_IDLE,
++ POWER_TOTAL
++};
++
++static DEFINE_PER_CPU(ulong, idle_prev_state);
++static ulong power_cpu_enabled[POWER_TOTAL];
++static ulong power_cpu_key[POWER_TOTAL];
++
++static int gator_trace_power_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++ int cpu;
++ bool found_nonzero_freq = false;
++
++ // Even if CONFIG_CPU_FREQ is defined, it still may not be used. Check
++ // for non-zero values from cpufreq_quick_get
++ for_each_online_cpu(cpu) {
++ if (cpufreq_quick_get(cpu) > 0) {
++ found_nonzero_freq = true;
++ break;
++ }
++ }
++
++ if (found_nonzero_freq) {
++ // cpu_frequency
++ dir = gatorfs_mkdir(sb, root, "Linux_power_cpu_freq");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &power_cpu_enabled[POWER_CPU_FREQ]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &power_cpu_key[POWER_CPU_FREQ]);
++ }
++
++ // cpu_idle
++ dir = gatorfs_mkdir(sb, root, "Linux_power_cpu_idle");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &power_cpu_enabled[POWER_CPU_IDLE]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &power_cpu_key[POWER_CPU_IDLE]);
++
++ return 0;
++}
++
++// 'cpu' may not equal smp_processor_id(), i.e. may not be running on the core that is having the freq/idle state change
++GATOR_DEFINE_PROBE(cpu_frequency, TP_PROTO(unsigned int frequency, unsigned int cpu))
++{
++ cpu = lcpu_to_pcpu(cpu);
++ marshal_event_single(cpu, power_cpu_key[POWER_CPU_FREQ], frequency * 1000);
++}
++
++GATOR_DEFINE_PROBE(cpu_idle, TP_PROTO(unsigned int state, unsigned int cpu))
++{
++ cpu = lcpu_to_pcpu(cpu);
++
++ if (state == per_cpu(idle_prev_state, cpu)) {
++ return;
++ }
++
++ if (implements_wfi()) {
++ if (state == PWR_EVENT_EXIT) {
++ // transition from wfi to non-wfi
++ marshal_idle(cpu, MESSAGE_IDLE_EXIT);
++ } else {
++ // transition from non-wfi to wfi
++ marshal_idle(cpu, MESSAGE_IDLE_ENTER);
++ }
++ }
++
++ per_cpu(idle_prev_state, cpu) = state;
++
++ if (power_cpu_enabled[POWER_CPU_IDLE]) {
++ // Increment state so that no negative numbers are sent
++ marshal_event_single(cpu, power_cpu_key[POWER_CPU_IDLE], state + 1);
++ }
++}
++
++static void gator_trace_power_online(void)
++{
++ int pcpu = get_physical_cpu();
++ int lcpu = get_logical_cpu();
++ if (power_cpu_enabled[POWER_CPU_FREQ]) {
++ marshal_event_single(pcpu, power_cpu_key[POWER_CPU_FREQ], cpufreq_quick_get(lcpu) * 1000);
++ }
++}
++
++static void gator_trace_power_offline(void)
++{
++ // Set frequency to zero on an offline
++ int cpu = get_physical_cpu();
++ if (power_cpu_enabled[POWER_CPU_FREQ]) {
++ marshal_event_single(cpu, power_cpu_key[POWER_CPU_FREQ], 0);
++ }
++}
++
++static int gator_trace_power_start(void)
++{
++ int cpu;
++
++ // register tracepoints
++ if (power_cpu_enabled[POWER_CPU_FREQ])
++ if (GATOR_REGISTER_TRACE(cpu_frequency))
++ goto fail_cpu_frequency_exit;
++
++ // Always register for cpu:idle for detecting WFI, independent of power_cpu_enabled[POWER_CPU_IDLE]
++ if (GATOR_REGISTER_TRACE(cpu_idle))
++ goto fail_cpu_idle_exit;
++ pr_debug("gator: registered power event tracepoints\n");
++
++ for_each_present_cpu(cpu) {
++ per_cpu(idle_prev_state, cpu) = 0;
++ }
++
++ return 0;
++
++ // unregister tracepoints on error
++fail_cpu_idle_exit:
++ if (power_cpu_enabled[POWER_CPU_FREQ])
++ GATOR_UNREGISTER_TRACE(cpu_frequency);
++fail_cpu_frequency_exit:
++ pr_err("gator: power event tracepoints failed to activate, please verify that tracepoints are enabled in the linux kernel\n");
++
++ return -1;
++}
++
++static void gator_trace_power_stop(void)
++{
++ int i;
++
++ if (power_cpu_enabled[POWER_CPU_FREQ])
++ GATOR_UNREGISTER_TRACE(cpu_frequency);
++ GATOR_UNREGISTER_TRACE(cpu_idle);
++ pr_debug("gator: unregistered power event tracepoints\n");
++
++ for (i = 0; i < POWER_TOTAL; i++) {
++ power_cpu_enabled[i] = 0;
++ }
++}
++
++void gator_trace_power_init(void)
++{
++ int i;
++ for (i = 0; i < POWER_TOTAL; i++) {
++ power_cpu_enabled[i] = 0;
++ power_cpu_key[i] = gator_events_get_key();
++ }
++}
++#else
++static int gator_trace_power_create_files(struct super_block *sb, struct dentry *root)
++{
++ return 0;
++}
++
++static void gator_trace_power_online(void)
++{
++}
++
++static void gator_trace_power_offline(void)
++{
++}
++
++static int gator_trace_power_start(void)
++{
++ return 0;
++}
++
++static void gator_trace_power_stop(void)
++{
++}
++
++void gator_trace_power_init(void)
++{
++}
++#endif
+diff -Nur linux-3.10.30.orig/drivers/gator/gator_trace_sched.c linux-linaro-stable-mx6/drivers/gator/gator_trace_sched.c
+--- linux-3.10.30.orig/drivers/gator/gator_trace_sched.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/gator_trace_sched.c 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,270 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <trace/events/sched.h>
++#include "gator.h"
++
++#define TASK_MAP_ENTRIES 1024 /* must be power of 2 */
++#define TASK_MAX_COLLISIONS 2
++
++enum {
++ STATE_WAIT_ON_OTHER = 0,
++ STATE_CONTENTION,
++ STATE_WAIT_ON_IO,
++ CPU_WAIT_TOTAL
++};
++
++static DEFINE_PER_CPU(uint64_t *, taskname_keys);
++static DEFINE_PER_CPU(int, collecting);
++static DEFINE_PER_CPU(bool, in_scheduler_context);
++
++// this array is never read as the cpu wait charts are derived counters
++// the files are needed, nonetheless, to show that these counters are available
++static ulong cpu_wait_enabled[CPU_WAIT_TOTAL];
++static ulong sched_cpu_key[CPU_WAIT_TOTAL];
++
++static int sched_trace_create_files(struct super_block *sb, struct dentry *root)
++{
++ struct dentry *dir;
++
++ // CPU Wait - Contention
++ dir = gatorfs_mkdir(sb, root, "Linux_cpu_wait_contention");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &cpu_wait_enabled[STATE_CONTENTION]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &sched_cpu_key[STATE_CONTENTION]);
++
++ // CPU Wait - I/O
++ dir = gatorfs_mkdir(sb, root, "Linux_cpu_wait_io");
++ if (!dir) {
++ return -1;
++ }
++ gatorfs_create_ulong(sb, dir, "enabled", &cpu_wait_enabled[STATE_WAIT_ON_IO]);
++ gatorfs_create_ro_ulong(sb, dir, "key", &sched_cpu_key[STATE_WAIT_ON_IO]);
++
++ return 0;
++}
++
++void emit_pid_name(struct task_struct *task)
++{
++ bool found = false;
++ char taskcomm[TASK_COMM_LEN + 3];
++ unsigned long x, cpu = get_physical_cpu();
++ uint64_t *keys = &(per_cpu(taskname_keys, cpu)[(task->pid & 0xFF) * TASK_MAX_COLLISIONS]);
++ uint64_t value;
++
++ value = gator_chksum_crc32(task->comm);
++ value = (value << 32) | (uint32_t)task->pid;
++
++ // determine if the thread name was emitted already
++ for (x = 0; x < TASK_MAX_COLLISIONS; x++) {
++ if (keys[x] == value) {
++ found = true;
++ break;
++ }
++ }
++
++ if (!found) {
++ // shift values, new value always in front
++ uint64_t oldv, newv = value;
++ for (x = 0; x < TASK_MAX_COLLISIONS; x++) {
++ oldv = keys[x];
++ keys[x] = newv;
++ newv = oldv;
++ }
++
++ // emit pid names, cannot use get_task_comm, as it's not exported on all kernel versions
++ if (strlcpy(taskcomm, task->comm, TASK_COMM_LEN) == TASK_COMM_LEN - 1) {
++ // append ellipses if task->comm has length of TASK_COMM_LEN - 1
++ strcat(taskcomm, "...");
++ }
++
++ marshal_thread_name(task->pid, taskcomm);
++ }
++}
++
++static void collect_counters(u64 time, struct task_struct *task)
++{
++ int *buffer, len, cpu = get_physical_cpu();
++ long long *buffer64;
++ struct gator_interface *gi;
++
++ if (marshal_event_header(time)) {
++ list_for_each_entry(gi, &gator_events, list) {
++ if (gi->read) {
++ len = gi->read(&buffer);
++ marshal_event(len, buffer);
++ } else if (gi->read64) {
++ len = gi->read64(&buffer64);
++ marshal_event64(len, buffer64);
++ }
++ if (gi->read_proc && task != NULL) {
++ len = gi->read_proc(&buffer64, task);
++ marshal_event64(len, buffer64);
++ }
++ }
++ // Only check after writing all counters so that time and corresponding counters appear in the same frame
++ buffer_check(cpu, BLOCK_COUNTER_BUF, time);
++
++ // Commit buffers on timeout
++ if (gator_live_rate > 0 && time >= per_cpu(gator_buffer_commit_time, cpu)) {
++ static const int buftypes[] = { NAME_BUF, COUNTER_BUF, BLOCK_COUNTER_BUF, SCHED_TRACE_BUF };
++ unsigned long flags;
++ int i;
++
++ local_irq_save(flags);
++ for (i = 0; i < ARRAY_SIZE(buftypes); ++i) {
++ gator_commit_buffer(cpu, buftypes[i], time);
++ }
++ local_irq_restore(flags);
++
++ // Try to preemptively flush the annotate buffer to reduce the chance of the buffer being full
++ if (on_primary_core() && spin_trylock(&annotate_lock)) {
++ gator_commit_buffer(0, ANNOTATE_BUF, time);
++ spin_unlock(&annotate_lock);
++ }
++ }
++ }
++}
++
++// special case used during a suspend of the system
++static void trace_sched_insert_idle(void)
++{
++ marshal_sched_trace_switch(0, 0, 0, 0);
++}
++
++GATOR_DEFINE_PROBE(sched_process_fork, TP_PROTO(struct task_struct *parent, struct task_struct *child))
++{
++ int cookie;
++ int cpu = get_physical_cpu();
++
++ cookie = get_exec_cookie(cpu, child);
++ emit_pid_name(child);
++
++ marshal_sched_trace_start(child->tgid, child->pid, cookie);
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
++GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct rq *rq, struct task_struct *prev, struct task_struct *next))
++#else
++GATOR_DEFINE_PROBE(sched_switch, TP_PROTO(struct task_struct *prev, struct task_struct *next))
++#endif
++{
++ int cookie;
++ int state;
++ int cpu = get_physical_cpu();
++
++ per_cpu(in_scheduler_context, cpu) = true;
++
++ // do as much work as possible before disabling interrupts
++ cookie = get_exec_cookie(cpu, next);
++ emit_pid_name(next);
++ if (prev->state == TASK_RUNNING) {
++ state = STATE_CONTENTION;
++ } else if (prev->in_iowait) {
++ state = STATE_WAIT_ON_IO;
++ } else {
++ state = STATE_WAIT_ON_OTHER;
++ }
++
++ per_cpu(collecting, cpu) = 1;
++ collect_counters(gator_get_time(), prev);
++ per_cpu(collecting, cpu) = 0;
++
++ marshal_sched_trace_switch(next->tgid, next->pid, cookie, state);
++
++ per_cpu(in_scheduler_context, cpu) = false;
++}
++
++GATOR_DEFINE_PROBE(sched_process_free, TP_PROTO(struct task_struct *p))
++{
++ marshal_sched_trace_exit(p->tgid, p->pid);
++}
++
++static void do_nothing(void *info)
++{
++ // Intentionally do nothing
++ (void)info;
++}
++
++static int register_scheduler_tracepoints(void)
++{
++ // register tracepoints
++ if (GATOR_REGISTER_TRACE(sched_process_fork))
++ goto fail_sched_process_fork;
++ if (GATOR_REGISTER_TRACE(sched_switch))
++ goto fail_sched_switch;
++ if (GATOR_REGISTER_TRACE(sched_process_free))
++ goto fail_sched_process_free;
++ pr_debug("gator: registered tracepoints\n");
++
++ // Now that the scheduler tracepoint is registered, force a context switch
++ // on all cpus to capture what is currently running.
++ on_each_cpu(do_nothing, NULL, 0);
++
++ return 0;
++
++ // unregister tracepoints on error
++fail_sched_process_free:
++ GATOR_UNREGISTER_TRACE(sched_switch);
++fail_sched_switch:
++ GATOR_UNREGISTER_TRACE(sched_process_fork);
++fail_sched_process_fork:
++ pr_err("gator: tracepoints failed to activate, please verify that tracepoints are enabled in the linux kernel\n");
++
++ return -1;
++}
++
++int gator_trace_sched_start(void)
++{
++ int cpu, size;
++
++ for_each_present_cpu(cpu) {
++ size = TASK_MAP_ENTRIES * TASK_MAX_COLLISIONS * sizeof(uint64_t);
++ per_cpu(taskname_keys, cpu) = (uint64_t *)kmalloc(size, GFP_KERNEL);
++ if (!per_cpu(taskname_keys, cpu))
++ return -1;
++ memset(per_cpu(taskname_keys, cpu), 0, size);
++ }
++
++ return register_scheduler_tracepoints();
++}
++
++void gator_trace_sched_offline(void)
++{
++ trace_sched_insert_idle();
++}
++
++static void unregister_scheduler_tracepoints(void)
++{
++ GATOR_UNREGISTER_TRACE(sched_process_fork);
++ GATOR_UNREGISTER_TRACE(sched_switch);
++ GATOR_UNREGISTER_TRACE(sched_process_free);
++ pr_debug("gator: unregistered tracepoints\n");
++}
++
++void gator_trace_sched_stop(void)
++{
++ int cpu;
++ unregister_scheduler_tracepoints();
++
++ for_each_present_cpu(cpu) {
++ kfree(per_cpu(taskname_keys, cpu));
++ }
++}
++
++void gator_trace_sched_init(void)
++{
++ int i;
++ for (i = 0; i < CPU_WAIT_TOTAL; i++) {
++ cpu_wait_enabled[i] = 0;
++ sched_cpu_key[i] = gator_events_get_key();
++ }
++}
+diff -Nur linux-3.10.30.orig/drivers/gator/Kconfig linux-linaro-stable-mx6/drivers/gator/Kconfig
+--- linux-3.10.30.orig/drivers/gator/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/Kconfig 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,33 @@
++config GATOR
++ tristate "Gator module for ARM's Streamline Performance Analyzer"
++ default m if (ARM || ARM64)
++ depends on PROFILING
++ depends on HIGH_RES_TIMERS
++ depends on LOCAL_TIMERS || !(ARM && SMP)
++ select TRACING
++
++config GATOR_WITH_MALI_SUPPORT
++ bool
++
++choice
++ prompt "Enable Mali GPU support in Gator"
++ depends on GATOR
++ optional
++
++config GATOR_MALI_400MP
++ bool "Mali-400MP"
++ select GATOR_WITH_MALI_SUPPORT
++
++config GATOR_MALI_T6XX
++ bool "Mali-T604 or Mali-T658"
++ select GATOR_WITH_MALI_SUPPORT
++
++endchoice
++
++config GATOR_MALI_PATH
++ string "Path to Mali driver"
++ depends on GATOR_WITH_MALI_SUPPORT
++ default "drivers/gpu/arm/mali400mp"
++ help
++ The gator code adds this to its include path so it can get the Mali
++ trace headers with: #include "linux/mali_linux_trace.h"
+diff -Nur linux-3.10.30.orig/drivers/gator/LICENSE linux-linaro-stable-mx6/drivers/gator/LICENSE
+--- linux-3.10.30.orig/drivers/gator/LICENSE 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/LICENSE 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,339 @@
++ GNU GENERAL PUBLIC LICENSE
++ Version 2, June 1991
++
++ Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
++ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
++ Everyone is permitted to copy and distribute verbatim copies
++ of this license document, but changing it is not allowed.
++
++ Preamble
++
++ The licenses for most software are designed to take away your
++freedom to share and change it. By contrast, the GNU General Public
++License is intended to guarantee your freedom to share and change free
++software--to make sure the software is free for all its users. This
++General Public License applies to most of the Free Software
++Foundation's software and to any other program whose authors commit to
++using it. (Some other Free Software Foundation software is covered by
++the GNU Lesser General Public License instead.) You can apply it to
++your programs, too.
++
++ When we speak of free software, we are referring to freedom, not
++price. Our General Public Licenses are designed to make sure that you
++have the freedom to distribute copies of free software (and charge for
++this service if you wish), that you receive source code or can get it
++if you want it, that you can change the software or use pieces of it
++in new free programs; and that you know you can do these things.
++
++ To protect your rights, we need to make restrictions that forbid
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++
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++consider it more useful to permit linking proprietary applications with the
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++Public License instead of this License.
+diff -Nur linux-3.10.30.orig/drivers/gator/Makefile linux-linaro-stable-mx6/drivers/gator/Makefile
+--- linux-3.10.30.orig/drivers/gator/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/Makefile 2014-05-15 20:33:46.961934322 +0200
+@@ -0,0 +1,76 @@
++ifneq ($(KERNELRELEASE),)
++
++# Uncomment the following line to enable kernel stack unwinding within gator, or update gator_backtrace.c
++# EXTRA_CFLAGS += -DGATOR_KERNEL_STACK_UNWINDING
++
++CONFIG_GATOR ?= m
++obj-$(CONFIG_GATOR) := gator.o
++
++gator-y := gator_main.o \
++ gator_events_irq.o \
++ gator_events_sched.o \
++ gator_events_net.o \
++ gator_events_block.o \
++ gator_events_meminfo.o \
++ gator_events_perf_pmu.o \
++ gator_events_mmapped.o \
++
++# Convert the old GATOR_WITH_MALI_SUPPORT to the new kernel flags
++ifneq ($(GATOR_WITH_MALI_SUPPORT),)
++ CONFIG_GATOR_WITH_MALI_SUPPORT := y
++ ifeq ($(GATOR_WITH_MALI_SUPPORT),MALI_T6xx)
++ CONFIG_GATOR_MALI_4XXMP := n
++ CONFIG_GATOR_MALI_T6XX := y
++ else
++ CONFIG_GATOR_MALI_4XXMP := y
++ CONFIG_GATOR_MALI_T6XX := n
++ endif
++ EXTRA_CFLAGS += -DMALI_SUPPORT=$(GATOR_WITH_MALI_SUPPORT)
++ ifneq ($(GATOR_MALI_INTERFACE_STYLE),)
++ EXTRA_CFLAGS += -DGATOR_MALI_INTERFACE_STYLE=$(GATOR_MALI_INTERFACE_STYLE)
++ endif
++endif
++
++ifeq ($(CONFIG_GATOR_WITH_MALI_SUPPORT),y)
++ ifeq ($(CONFIG_GATOR_MALI_T6XX),y)
++ gator-y += gator_events_mali_t6xx.o \
++ gator_events_mali_t6xx_hw.o
++ include $(src)/mali_t6xx.mk
++ else
++ gator-y += gator_events_mali_4xx.o
++ endif
++ gator-y += gator_events_mali_common.o
++
++ ifneq ($(CONFIG_GATOR_MALI_PATH),)
++ ccflags-y += -I$(CONFIG_GATOR_MALI_PATH)
++ endif
++ ccflags-$(CONFIG_GATOR_MALI_4XXMP) += -DMALI_SUPPORT=MALI_4xx
++ ccflags-$(CONFIG_GATOR_MALI_T6XX) += -DMALI_SUPPORT=MALI_T6xx
++endif
++
++# GATOR_TEST controls whether to include (=1) or exclude (=0) test code.
++GATOR_TEST ?= 0
++EXTRA_CFLAGS += -DGATOR_TEST=$(GATOR_TEST)
++
++gator-$(CONFIG_ARM) += gator_events_armv6.o \
++ gator_events_armv7.o \
++ gator_events_ccn-504.o \
++ gator_events_l2c-310.o \
++ gator_events_scorpion.o
++
++gator-$(CONFIG_ARM64) += gator_events_ccn-504.o
++
++else
++
++all:
++ @echo
++ @echo "usage:"
++ @echo " make -C <kernel_build_dir> M=\`pwd\` ARCH=arm CROSS_COMPILE=<...> modules"
++ @echo
++ $(error)
++
++clean:
++ rm -f *.o .*.cmd modules.order Module.symvers gator.ko gator.mod.c
++ rm -rf .tmp_versions
++
++endif
+diff -Nur linux-3.10.30.orig/drivers/gator/mali/mali_mjollnir_profiling_gator_api.h linux-linaro-stable-mx6/drivers/gator/mali/mali_mjollnir_profiling_gator_api.h
+--- linux-3.10.30.orig/drivers/gator/mali/mali_mjollnir_profiling_gator_api.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/mali/mali_mjollnir_profiling_gator_api.h 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,163 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __MALI_MJOLLNIR_PROFILING_GATOR_API_H__
++#define __MALI_MJOLLNIR_PROFILING_GATOR_API_H__
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++
++/*
++ * The number of processor cores. Update to suit your hardware implementation.
++ */
++#define MAX_NUM_FP_CORES (4)
++#define MAX_NUM_VP_CORES (1)
++#define MAX_NUM_L2_CACHE_CORES (1)
++
++enum counters
++{
++ /* Timeline activity */
++ ACTIVITY_VP_0 = 0,
++ ACTIVITY_FP_0,
++ ACTIVITY_FP_1,
++ ACTIVITY_FP_2,
++ ACTIVITY_FP_3,
++
++ /* L2 cache counters */
++ COUNTER_L2_0_C0,
++ COUNTER_L2_0_C1,
++
++ /* Vertex processor counters */
++ COUNTER_VP_0_C0,
++ COUNTER_VP_0_C1,
++
++ /* Fragment processor counters */
++ COUNTER_FP_0_C0,
++ COUNTER_FP_0_C1,
++ COUNTER_FP_1_C0,
++ COUNTER_FP_1_C1,
++ COUNTER_FP_2_C0,
++ COUNTER_FP_2_C1,
++ COUNTER_FP_3_C0,
++ COUNTER_FP_3_C1,
++
++ /* EGL Software Counters */
++ COUNTER_EGL_BLIT_TIME,
++
++ /* GLES Software Counters */
++ COUNTER_GLES_DRAW_ELEMENTS_CALLS,
++ COUNTER_GLES_DRAW_ELEMENTS_NUM_INDICES,
++ COUNTER_GLES_DRAW_ELEMENTS_NUM_TRANSFORMED,
++ COUNTER_GLES_DRAW_ARRAYS_CALLS,
++ COUNTER_GLES_DRAW_ARRAYS_NUM_TRANSFORMED,
++ COUNTER_GLES_DRAW_POINTS,
++ COUNTER_GLES_DRAW_LINES,
++ COUNTER_GLES_DRAW_LINE_LOOP,
++ COUNTER_GLES_DRAW_LINE_STRIP,
++ COUNTER_GLES_DRAW_TRIANGLES,
++ COUNTER_GLES_DRAW_TRIANGLE_STRIP,
++ COUNTER_GLES_DRAW_TRIANGLE_FAN,
++ COUNTER_GLES_NON_VBO_DATA_COPY_TIME,
++ COUNTER_GLES_UNIFORM_BYTES_COPIED_TO_MALI,
++ COUNTER_GLES_UPLOAD_TEXTURE_TIME,
++ COUNTER_GLES_UPLOAD_VBO_TIME,
++ COUNTER_GLES_NUM_FLUSHES,
++ COUNTER_GLES_NUM_VSHADERS_GENERATED,
++ COUNTER_GLES_NUM_FSHADERS_GENERATED,
++ COUNTER_GLES_VSHADER_GEN_TIME,
++ COUNTER_GLES_FSHADER_GEN_TIME,
++ COUNTER_GLES_INPUT_TRIANGLES,
++ COUNTER_GLES_VXCACHE_HIT,
++ COUNTER_GLES_VXCACHE_MISS,
++ COUNTER_GLES_VXCACHE_COLLISION,
++ COUNTER_GLES_CULLED_TRIANGLES,
++ COUNTER_GLES_CULLED_LINES,
++ COUNTER_GLES_BACKFACE_TRIANGLES,
++ COUNTER_GLES_GBCLIP_TRIANGLES,
++ COUNTER_GLES_GBCLIP_LINES,
++ COUNTER_GLES_TRIANGLES_DRAWN,
++ COUNTER_GLES_DRAWCALL_TIME,
++ COUNTER_GLES_TRIANGLES_COUNT,
++ COUNTER_GLES_INDEPENDENT_TRIANGLES_COUNT,
++ COUNTER_GLES_STRIP_TRIANGLES_COUNT,
++ COUNTER_GLES_FAN_TRIANGLES_COUNT,
++ COUNTER_GLES_LINES_COUNT,
++ COUNTER_GLES_INDEPENDENT_LINES_COUNT,
++ COUNTER_GLES_STRIP_LINES_COUNT,
++ COUNTER_GLES_LOOP_LINES_COUNT,
++
++ COUNTER_FILMSTRIP,
++ COUNTER_FREQUENCY,
++ COUNTER_VOLTAGE,
++
++ NUMBER_OF_EVENTS
++};
++
++#define FIRST_ACTIVITY_EVENT ACTIVITY_VP_0
++#define LAST_ACTIVITY_EVENT ACTIVITY_FP_3
++
++#define FIRST_HW_COUNTER COUNTER_L2_0_C0
++#define LAST_HW_COUNTER COUNTER_FP_3_C1
++
++#define FIRST_SW_COUNTER COUNTER_EGL_BLIT_TIME
++#define LAST_SW_COUNTER COUNTER_GLES_LOOP_LINES_COUNT
++
++/* Signifies that the system is able to report voltage and frequency numbers. */
++#define DVFS_REPORTED_BY_DDK 1
++
++/**
++ * Structure to pass performance counter data of a Mali core
++ */
++typedef struct _mali_profiling_core_counters
++{
++ u32 source0;
++ u32 value0;
++ u32 source1;
++ u32 value1;
++} _mali_profiling_core_counters;
++
++/*
++ * For compatibility with utgard.
++ */
++typedef struct _mali_profiling_l2_counter_values
++{
++ struct _mali_profiling_core_counters cores[MAX_NUM_L2_CACHE_CORES];
++} _mali_profiling_l2_counter_values;
++
++typedef struct _mali_profiling_mali_version
++{
++ u32 mali_product_id;
++ u32 mali_version_major;
++ u32 mali_version_minor;
++ u32 num_of_l2_cores;
++ u32 num_of_fp_cores;
++ u32 num_of_vp_cores;
++} _mali_profiling_mali_version;
++
++extern void _mali_profiling_get_mali_version(struct _mali_profiling_mali_version *values);
++extern u32 _mali_profiling_get_l2_counters(_mali_profiling_l2_counter_values *values);
++
++/*
++ * List of possible actions allowing DDK to be controlled by Streamline.
++ * The following numbers are used by DDK to control the frame buffer dumping.
++ */
++#define FBDUMP_CONTROL_ENABLE (1)
++#define FBDUMP_CONTROL_RATE (2)
++#define SW_COUNTER_ENABLE (3)
++#define FBDUMP_CONTROL_RESIZE_FACTOR (4)
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __MALI_MJOLLNIR_PROFILING_GATOR_API_H__ */
+diff -Nur linux-3.10.30.orig/drivers/gator/mali/mali_utgard_profiling_gator_api.h linux-linaro-stable-mx6/drivers/gator/mali/mali_utgard_profiling_gator_api.h
+--- linux-3.10.30.orig/drivers/gator/mali/mali_utgard_profiling_gator_api.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/mali/mali_utgard_profiling_gator_api.h 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,201 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __MALI_UTGARD_PROFILING_GATOR_API_H__
++#define __MALI_UTGARD_PROFILING_GATOR_API_H__
++
++#ifdef __cplusplus
++extern "C"
++{
++#endif
++
++#define MALI_PROFILING_API_VERSION 4
++
++#define MAX_NUM_L2_CACHE_CORES 3
++#define MAX_NUM_FP_CORES 8
++#define MAX_NUM_VP_CORES 1
++
++/** The list of events supported by the Mali DDK. */
++typedef enum
++{
++ /* Vertex processor activity */
++ ACTIVITY_VP_0 = 0,
++
++ /* Fragment processor activity */
++ ACTIVITY_FP_0, /* 1 */
++ ACTIVITY_FP_1,
++ ACTIVITY_FP_2,
++ ACTIVITY_FP_3,
++ ACTIVITY_FP_4,
++ ACTIVITY_FP_5,
++ ACTIVITY_FP_6,
++ ACTIVITY_FP_7,
++
++ /* L2 cache counters */
++ COUNTER_L2_0_C0,
++ COUNTER_L2_0_C1,
++ COUNTER_L2_1_C0,
++ COUNTER_L2_1_C1,
++ COUNTER_L2_2_C0,
++ COUNTER_L2_2_C1,
++
++ /* Vertex processor counters */
++ COUNTER_VP_0_C0, /*15*/
++ COUNTER_VP_0_C1,
++
++ /* Fragment processor counters */
++ COUNTER_FP_0_C0,
++ COUNTER_FP_0_C1,
++ COUNTER_FP_1_C0,
++ COUNTER_FP_1_C1,
++ COUNTER_FP_2_C0,
++ COUNTER_FP_2_C1,
++ COUNTER_FP_3_C0,
++ COUNTER_FP_3_C1,
++ COUNTER_FP_4_C0,
++ COUNTER_FP_4_C1,
++ COUNTER_FP_5_C0,
++ COUNTER_FP_5_C1,
++ COUNTER_FP_6_C0,
++ COUNTER_FP_6_C1,
++ COUNTER_FP_7_C0,
++ COUNTER_FP_7_C1, /* 32 */
++
++ /*
++ * If more hardware counters are added, the _mali_osk_hw_counter_table
++ * below should also be updated.
++ */
++
++ /* EGL software counters */
++ COUNTER_EGL_BLIT_TIME,
++
++ /* GLES software counters */
++ COUNTER_GLES_DRAW_ELEMENTS_CALLS,
++ COUNTER_GLES_DRAW_ELEMENTS_NUM_INDICES,
++ COUNTER_GLES_DRAW_ELEMENTS_NUM_TRANSFORMED,
++ COUNTER_GLES_DRAW_ARRAYS_CALLS,
++ COUNTER_GLES_DRAW_ARRAYS_NUM_TRANSFORMED,
++ COUNTER_GLES_DRAW_POINTS,
++ COUNTER_GLES_DRAW_LINES,
++ COUNTER_GLES_DRAW_LINE_LOOP,
++ COUNTER_GLES_DRAW_LINE_STRIP,
++ COUNTER_GLES_DRAW_TRIANGLES,
++ COUNTER_GLES_DRAW_TRIANGLE_STRIP,
++ COUNTER_GLES_DRAW_TRIANGLE_FAN,
++ COUNTER_GLES_NON_VBO_DATA_COPY_TIME,
++ COUNTER_GLES_UNIFORM_BYTES_COPIED_TO_MALI,
++ COUNTER_GLES_UPLOAD_TEXTURE_TIME,
++ COUNTER_GLES_UPLOAD_VBO_TIME,
++ COUNTER_GLES_NUM_FLUSHES,
++ COUNTER_GLES_NUM_VSHADERS_GENERATED,
++ COUNTER_GLES_NUM_FSHADERS_GENERATED,
++ COUNTER_GLES_VSHADER_GEN_TIME,
++ COUNTER_GLES_FSHADER_GEN_TIME,
++ COUNTER_GLES_INPUT_TRIANGLES,
++ COUNTER_GLES_VXCACHE_HIT,
++ COUNTER_GLES_VXCACHE_MISS,
++ COUNTER_GLES_VXCACHE_COLLISION,
++ COUNTER_GLES_CULLED_TRIANGLES,
++ COUNTER_GLES_CULLED_LINES,
++ COUNTER_GLES_BACKFACE_TRIANGLES,
++ COUNTER_GLES_GBCLIP_TRIANGLES,
++ COUNTER_GLES_GBCLIP_LINES,
++ COUNTER_GLES_TRIANGLES_DRAWN,
++ COUNTER_GLES_DRAWCALL_TIME,
++ COUNTER_GLES_TRIANGLES_COUNT,
++ COUNTER_GLES_INDEPENDENT_TRIANGLES_COUNT,
++ COUNTER_GLES_STRIP_TRIANGLES_COUNT,
++ COUNTER_GLES_FAN_TRIANGLES_COUNT,
++ COUNTER_GLES_LINES_COUNT,
++ COUNTER_GLES_INDEPENDENT_LINES_COUNT,
++ COUNTER_GLES_STRIP_LINES_COUNT,
++ COUNTER_GLES_LOOP_LINES_COUNT,
++
++ /* Framebuffer capture pseudo-counter */
++ COUNTER_FILMSTRIP,
++
++ NUMBER_OF_EVENTS
++} _mali_osk_counter_id;
++
++#define FIRST_ACTIVITY_EVENT ACTIVITY_VP_0
++#define LAST_ACTIVITY_EVENT ACTIVITY_FP_7
++
++#define FIRST_HW_COUNTER COUNTER_L2_0_C0
++#define LAST_HW_COUNTER COUNTER_FP_7_C1
++
++#define FIRST_SW_COUNTER COUNTER_EGL_BLIT_TIME
++#define LAST_SW_COUNTER COUNTER_GLES_LOOP_LINES_COUNT
++
++#define FIRST_SPECIAL_COUNTER COUNTER_FILMSTRIP
++#define LAST_SPECIAL_COUNTER COUNTER_FILMSTRIP
++
++/**
++ * Structure to pass performance counter data of a Mali core
++ */
++typedef struct _mali_profiling_core_counters
++{
++ u32 source0;
++ u32 value0;
++ u32 source1;
++ u32 value1;
++} _mali_profiling_core_counters;
++
++/**
++ * Structure to pass performance counter data of Mali L2 cache cores
++ */
++typedef struct _mali_profiling_l2_counter_values
++{
++ struct _mali_profiling_core_counters cores[MAX_NUM_L2_CACHE_CORES];
++} _mali_profiling_l2_counter_values;
++
++/**
++ * Structure to pass data defining Mali instance in use:
++ *
++ * mali_product_id - Mali product id
++ * mali_version_major - Mali version major number
++ * mali_version_minor - Mali version minor number
++ * num_of_l2_cores - number of L2 cache cores
++ * num_of_fp_cores - number of fragment processor cores
++ * num_of_vp_cores - number of vertex processor cores
++ */
++typedef struct _mali_profiling_mali_version
++{
++ u32 mali_product_id;
++ u32 mali_version_major;
++ u32 mali_version_minor;
++ u32 num_of_l2_cores;
++ u32 num_of_fp_cores;
++ u32 num_of_vp_cores;
++} _mali_profiling_mali_version;
++
++/*
++ * List of possible actions to be controlled by Streamline.
++ * The following numbers are used by gator to control the frame buffer dumping and s/w counter reporting.
++ * We cannot use the enums in mali_uk_types.h because they are unknown inside gator.
++ */
++#define FBDUMP_CONTROL_ENABLE (1)
++#define FBDUMP_CONTROL_RATE (2)
++#define SW_COUNTER_ENABLE (3)
++#define FBDUMP_CONTROL_RESIZE_FACTOR (4)
++
++void _mali_profiling_control(u32 action, u32 value);
++
++u32 _mali_profiling_get_l2_counters(_mali_profiling_l2_counter_values *values);
++
++int _mali_profiling_set_event(u32 counter_id, s32 event_id);
++
++u32 _mali_profiling_get_api_version(void);
++
++void _mali_profiling_get_mali_version(struct _mali_profiling_mali_version *values);
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __MALI_UTGARD_PROFILING_GATOR_API_H__ */
+diff -Nur linux-3.10.30.orig/drivers/gator/mali_t6xx.mk linux-linaro-stable-mx6/drivers/gator/mali_t6xx.mk
+--- linux-3.10.30.orig/drivers/gator/mali_t6xx.mk 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gator/mali_t6xx.mk 2014-05-15 20:33:46.965934351 +0200
+@@ -0,0 +1,26 @@
++# Defines for Mali-T6xx driver
++EXTRA_CFLAGS += -DMALI_USE_UMP=1 \
++ -DMALI_LICENSE_IS_GPL=1 \
++ -DMALI_BASE_TRACK_MEMLEAK=0 \
++ -DMALI_DEBUG=0 \
++ -DMALI_ERROR_INJECT_ON=0 \
++ -DMALI_CUSTOMER_RELEASE=1 \
++ -DMALI_UNIT_TEST=0 \
++ -DMALI_BACKEND_KERNEL=1 \
++ -DMALI_NO_MALI=0
++
++DDK_DIR ?= .
++KBASE_DIR = $(DDK_DIR)/drivers/gpu/arm/t6xx/kbase
++OSK_DIR = $(DDK_DIR)/drivers/gpu/arm/t6xx/kbase/osk
++UMP_DIR = $(DDK_DIR)/include/linux
++
++# Include directories in the DDK
++EXTRA_CFLAGS += -I$(KBASE_DIR)/ \
++ -I$(KBASE_DIR)/.. \
++ -I$(OSK_DIR)/.. \
++ -I$(UMP_DIR)/.. \
++ -I$(DDK_DIR)/include \
++ -I$(KBASE_DIR)/osk/src/linux/include \
++ -I$(KBASE_DIR)/platform_dummy \
++ -I$(KBASE_DIR)/src
++
+diff -Nur linux-3.10.30.orig/drivers/gpio/devres.c linux-linaro-stable-mx6/drivers/gpio/devres.c
+--- linux-3.10.30.orig/drivers/gpio/devres.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpio/devres.c 2014-05-15 20:33:46.981934466 +0200
+@@ -19,6 +19,89 @@
+ #include <linux/device.h>
+ #include <linux/gfp.h>
+
++static void devm_gpiod_release(struct device *dev, void *res)
++{
++ struct gpio_desc **desc = res;
++
++ gpiod_put(*desc);
++}
++
++static int devm_gpiod_match(struct device *dev, void *res, void *data)
++{
++ struct gpio_desc **this = res, **gpio = data;
++
++ return *this == *gpio;
++}
++
++/**
++ * devm_gpiod_get - Resource-managed gpiod_get()
++ * @dev: GPIO consumer
++ * @con_id: function within the GPIO consumer
++ *
++ * Managed gpiod_get(). GPIO descriptors returned from this function are
++ * automatically disposed on driver detach. See gpiod_get() for detailed
++ * information about behavior and return values.
++ */
++struct gpio_desc *__must_check devm_gpiod_get(struct device *dev,
++ const char *con_id)
++{
++ return devm_gpiod_get_index(dev, con_id, 0);
++}
++EXPORT_SYMBOL(devm_gpiod_get);
++
++/**
++ * devm_gpiod_get_index - Resource-managed gpiod_get_index()
++ * @dev: GPIO consumer
++ * @con_id: function within the GPIO consumer
++ * @idx: index of the GPIO to obtain in the consumer
++ *
++ * Managed gpiod_get_index(). GPIO descriptors returned from this function are
++ * automatically disposed on driver detach. See gpiod_get_index() for detailed
++ * information about behavior and return values.
++ */
++struct gpio_desc *__must_check devm_gpiod_get_index(struct device *dev,
++ const char *con_id,
++ unsigned int idx)
++{
++ struct gpio_desc **dr;
++ struct gpio_desc *desc;
++
++ dr = devres_alloc(devm_gpiod_release, sizeof(struct gpiod_desc *),
++ GFP_KERNEL);
++ if (!dr)
++ return ERR_PTR(-ENOMEM);
++
++ desc = gpiod_get_index(dev, con_id, idx);
++ if (IS_ERR(desc)) {
++ devres_free(dr);
++ return desc;
++ }
++
++ *dr = desc;
++ devres_add(dev, dr);
++
++ return desc;
++}
++EXPORT_SYMBOL(devm_gpiod_get_index);
++
++/**
++ * devm_gpiod_put - Resource-managed gpiod_put()
++ * @desc: GPIO descriptor to dispose of
++ *
++ * Dispose of a GPIO descriptor obtained with devm_gpiod_get() or
++ * devm_gpiod_get_index(). Normally this function will not be called as the GPIO
++ * will be disposed of by the resource management code.
++ */
++void devm_gpiod_put(struct device *dev, struct gpio_desc *desc)
++{
++ WARN_ON(devres_release(dev, devm_gpiod_release, devm_gpiod_match,
++ &desc));
++}
++EXPORT_SYMBOL(devm_gpiod_put);
++
++
++
++
+ static void devm_gpio_release(struct device *dev, void *res)
+ {
+ unsigned *gpio = res;
+diff -Nur linux-3.10.30.orig/drivers/gpio/gpiolib.c linux-linaro-stable-mx6/drivers/gpio/gpiolib.c
+--- linux-3.10.30.orig/drivers/gpio/gpiolib.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpio/gpiolib.c 2014-05-15 20:33:47.001934610 +0200
+@@ -12,20 +12,16 @@
+ #include <linux/of_gpio.h>
+ #include <linux/idr.h>
+ #include <linux/slab.h>
++#include <linux/gpio/driver.h>
+
+ #define CREATE_TRACE_POINTS
+ #include <trace/events/gpio.h>
+
+-/* Optional implementation infrastructure for GPIO interfaces.
++/* Implementation infrastructure for GPIO interfaces.
+ *
+- * Platforms may want to use this if they tend to use very many GPIOs
+- * that aren't part of a System-On-Chip core; or across I2C/SPI/etc.
+- *
+- * When kernel footprint or instruction count is an issue, simpler
+- * implementations may be preferred. The GPIO programming interface
+- * allows for inlining speed-critical get/set operations for common
+- * cases, so that access to SOC-integrated GPIOs can sometimes cost
+- * only an instruction or two per bit.
++ * The GPIO programming interface allows for inlining speed-critical
++ * get/set operations for common cases, so that access to SOC-integrated
++ * GPIOs can sometimes cost only an instruction or two per bit.
+ */
+
+
+@@ -57,9 +53,10 @@
+ #define FLAG_SYSFS 3 /* exported via /sys/class/gpio/control */
+ #define FLAG_TRIG_FALL 4 /* trigger on falling edge */
+ #define FLAG_TRIG_RISE 5 /* trigger on rising edge */
+-#define FLAG_ACTIVE_LOW 6 /* sysfs value has active low */
++#define FLAG_ACTIVE_LOW 6 /* value has active low */
+ #define FLAG_OPEN_DRAIN 7 /* Gpio is open drain type */
+ #define FLAG_OPEN_SOURCE 8 /* Gpio is open source type */
++#define FLAG_USED_AS_IRQ 9 /* GPIO is connected to an IRQ */
+
+ #define ID_SHIFT 16 /* add new flags before this one */
+
+@@ -74,34 +71,50 @@
+
+ #define GPIO_OFFSET_VALID(chip, offset) (offset >= 0 && offset < chip->ngpio)
+
++static DEFINE_MUTEX(gpio_lookup_lock);
++static LIST_HEAD(gpio_lookup_list);
+ static LIST_HEAD(gpio_chips);
+
+ #ifdef CONFIG_GPIO_SYSFS
+ static DEFINE_IDR(dirent_idr);
+ #endif
+
+-/*
+- * Internal gpiod_* API using descriptors instead of the integer namespace.
+- * Most of this should eventually go public.
+- */
+ static int gpiod_request(struct gpio_desc *desc, const char *label);
+ static void gpiod_free(struct gpio_desc *desc);
+-static int gpiod_direction_input(struct gpio_desc *desc);
+-static int gpiod_direction_output(struct gpio_desc *desc, int value);
+-static int gpiod_get_direction(const struct gpio_desc *desc);
+-static int gpiod_set_debounce(struct gpio_desc *desc, unsigned debounce);
+-static int gpiod_get_value_cansleep(const struct gpio_desc *desc);
+-static void gpiod_set_value_cansleep(struct gpio_desc *desc, int value);
+-static int gpiod_get_value(const struct gpio_desc *desc);
+-static void gpiod_set_value(struct gpio_desc *desc, int value);
+-static int gpiod_cansleep(const struct gpio_desc *desc);
+-static int gpiod_to_irq(const struct gpio_desc *desc);
+-static int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
+-static int gpiod_export_link(struct device *dev, const char *name,
+- struct gpio_desc *desc);
+-static int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value);
+-static void gpiod_unexport(struct gpio_desc *desc);
+
++#ifdef CONFIG_DEBUG_FS
++#define gpiod_emerg(desc, fmt, ...) \
++ pr_emerg("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label, \
++ ##__VA_ARGS__)
++#define gpiod_crit(desc, fmt, ...) \
++ pr_crit("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label, \
++ ##__VA_ARGS__)
++#define gpiod_err(desc, fmt, ...) \
++ pr_err("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label, \
++ ##__VA_ARGS__)
++#define gpiod_warn(desc, fmt, ...) \
++ pr_warn("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label, \
++ ##__VA_ARGS__)
++#define gpiod_info(desc, fmt, ...) \
++ pr_info("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label, \
++ ##__VA_ARGS__)
++#define gpiod_dbg(desc, fmt, ...) \
++ pr_debug("gpio-%d (%s): " fmt, desc_to_gpio(desc), desc->label, \
++ ##__VA_ARGS__)
++#else
++#define gpiod_emerg(desc, fmt, ...) \
++ pr_emerg("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
++#define gpiod_crit(desc, fmt, ...) \
++ pr_crit("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
++#define gpiod_err(desc, fmt, ...) \
++ pr_err("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
++#define gpiod_warn(desc, fmt, ...) \
++ pr_warn("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
++#define gpiod_info(desc, fmt, ...) \
++ pr_info("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
++#define gpiod_dbg(desc, fmt, ...) \
++ pr_debug("gpio-%d: " fmt, desc_to_gpio(desc), ##__VA_ARGS__)
++#endif
+
+ static inline void desc_set_label(struct gpio_desc *d, const char *label)
+ {
+@@ -121,23 +134,36 @@
+ /**
+ * Convert a GPIO number to its descriptor
+ */
+-static struct gpio_desc *gpio_to_desc(unsigned gpio)
++struct gpio_desc *gpio_to_desc(unsigned gpio)
+ {
+ if (WARN(!gpio_is_valid(gpio), "invalid GPIO %d\n", gpio))
+ return NULL;
+ else
+ return &gpio_desc[gpio];
+ }
++EXPORT_SYMBOL_GPL(gpio_to_desc);
++
++/**
++ * Convert an offset on a certain chip to a corresponding descriptor
++ */
++static struct gpio_desc *gpiochip_offset_to_desc(struct gpio_chip *chip,
++ unsigned int offset)
++{
++ unsigned int gpio = chip->base + offset;
++
++ return gpio_to_desc(gpio);
++}
+
+ /**
+ * Convert a GPIO descriptor to the integer namespace.
+ * This should disappear in the future but is needed since we still
+ * use GPIO numbers for error messages and sysfs nodes
+ */
+-static int desc_to_gpio(const struct gpio_desc *desc)
++int desc_to_gpio(const struct gpio_desc *desc)
+ {
+- return desc->chip->base + gpio_chip_hwgpio(desc);
++ return desc - &gpio_desc[0];
+ }
++EXPORT_SYMBOL_GPL(desc_to_gpio);
+
+
+ /* Warn when drivers omit gpio_request() calls -- legal but ill-advised
+@@ -172,16 +198,15 @@
+ return 0;
+ }
+
+-static struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
++/**
++ * gpiod_to_chip - Return the GPIO chip to which a GPIO descriptor belongs
++ * @desc: descriptor to return the chip of
++ */
++struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
+ {
+ return desc ? desc->chip : NULL;
+ }
+-
+-/* caller holds gpio_lock *OR* gpio is marked as requested */
+-struct gpio_chip *gpio_to_chip(unsigned gpio)
+-{
+- return gpiod_to_chip(gpio_to_desc(gpio));
+-}
++EXPORT_SYMBOL_GPL(gpiod_to_chip);
+
+ /* dynamic allocation of GPIOs, e.g. on a hotplugged device */
+ static int gpiochip_find_base(int ngpio)
+@@ -207,8 +232,15 @@
+ }
+ }
+
+-/* caller ensures gpio is valid and requested, chip->get_direction may sleep */
+-static int gpiod_get_direction(const struct gpio_desc *desc)
++/**
++ * gpiod_get_direction - return the current direction of a GPIO
++ * @desc: GPIO to get the direction of
++ *
++ * Return GPIOF_DIR_IN or GPIOF_DIR_OUT, or an error code in case of error.
++ *
++ * This function may sleep if gpiod_cansleep() is true.
++ */
++int gpiod_get_direction(const struct gpio_desc *desc)
+ {
+ struct gpio_chip *chip;
+ unsigned offset;
+@@ -234,6 +266,7 @@
+ }
+ return status;
+ }
++EXPORT_SYMBOL_GPL(gpiod_get_direction);
+
+ #ifdef CONFIG_GPIO_SYSFS
+
+@@ -318,17 +351,10 @@
+
+ mutex_lock(&sysfs_lock);
+
+- if (!test_bit(FLAG_EXPORT, &desc->flags)) {
++ if (!test_bit(FLAG_EXPORT, &desc->flags))
+ status = -EIO;
+- } else {
+- int value;
+-
+- value = !!gpiod_get_value_cansleep(desc);
+- if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
+- value = !value;
+-
+- status = sprintf(buf, "%d\n", value);
+- }
++ else
++ status = sprintf(buf, "%d\n", gpiod_get_value_cansleep(desc));
+
+ mutex_unlock(&sysfs_lock);
+ return status;
+@@ -349,11 +375,9 @@
+ else {
+ long value;
+
+- status = strict_strtol(buf, 0, &value);
++ status = kstrtol(buf, 0, &value);
+ if (status == 0) {
+- if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
+- value = !value;
+- gpiod_set_value_cansleep(desc, value != 0);
++ gpiod_set_value_cansleep(desc, value);
+ status = size;
+ }
+ }
+@@ -395,6 +419,7 @@
+ desc->flags &= ~GPIO_TRIGGER_MASK;
+
+ if (!gpio_flags) {
++ gpiod_unlock_as_irq(desc);
+ ret = 0;
+ goto free_id;
+ }
+@@ -433,6 +458,12 @@
+ if (ret < 0)
+ goto free_id;
+
++ ret = gpiod_lock_as_irq(desc);
++ if (ret < 0) {
++ gpiod_warn(desc, "failed to flag the GPIO for IRQ\n");
++ goto free_id;
++ }
++
+ desc->flags |= gpio_flags;
+ return 0;
+
+@@ -570,7 +601,7 @@
+ } else {
+ long value;
+
+- status = strict_strtol(buf, 0, &value);
++ status = kstrtol(buf, 0, &value);
+ if (status == 0)
+ status = sysfs_set_active_low(desc, dev, value != 0);
+ }
+@@ -652,7 +683,7 @@
+ struct gpio_desc *desc;
+ int status;
+
+- status = strict_strtol(buf, 0, &gpio);
++ status = kstrtol(buf, 0, &gpio);
+ if (status < 0)
+ goto done;
+
+@@ -694,7 +725,7 @@
+ struct gpio_desc *desc;
+ int status;
+
+- status = strict_strtol(buf, 0, &gpio);
++ status = kstrtol(buf, 0, &gpio);
+ if (status < 0)
+ goto done;
+
+@@ -736,7 +767,7 @@
+
+
+ /**
+- * gpio_export - export a GPIO through sysfs
++ * gpiod_export - export a GPIO through sysfs
+ * @gpio: gpio to make available, already requested
+ * @direction_may_change: true if userspace may change gpio direction
+ * Context: arch_initcall or later
+@@ -750,7 +781,7 @@
+ *
+ * Returns zero on success, else an error.
+ */
+-static int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+ {
+ unsigned long flags;
+ int status;
+@@ -828,12 +859,7 @@
+ status);
+ return status;
+ }
+-
+-int gpio_export(unsigned gpio, bool direction_may_change)
+-{
+- return gpiod_export(gpio_to_desc(gpio), direction_may_change);
+-}
+-EXPORT_SYMBOL_GPL(gpio_export);
++EXPORT_SYMBOL_GPL(gpiod_export);
+
+ static int match_export(struct device *dev, const void *data)
+ {
+@@ -841,7 +867,7 @@
+ }
+
+ /**
+- * gpio_export_link - create a sysfs link to an exported GPIO node
++ * gpiod_export_link - create a sysfs link to an exported GPIO node
+ * @dev: device under which to create symlink
+ * @name: name of the symlink
+ * @gpio: gpio to create symlink to, already exported
+@@ -851,8 +877,8 @@
+ *
+ * Returns zero on success, else an error.
+ */
+-static int gpiod_export_link(struct device *dev, const char *name,
+- struct gpio_desc *desc)
++int gpiod_export_link(struct device *dev, const char *name,
++ struct gpio_desc *desc)
+ {
+ int status = -EINVAL;
+
+@@ -883,15 +909,10 @@
+
+ return status;
+ }
+-
+-int gpio_export_link(struct device *dev, const char *name, unsigned gpio)
+-{
+- return gpiod_export_link(dev, name, gpio_to_desc(gpio));
+-}
+-EXPORT_SYMBOL_GPL(gpio_export_link);
++EXPORT_SYMBOL_GPL(gpiod_export_link);
+
+ /**
+- * gpio_sysfs_set_active_low - set the polarity of gpio sysfs value
++ * gpiod_sysfs_set_active_low - set the polarity of gpio sysfs value
+ * @gpio: gpio to change
+ * @value: non-zero to use active low, i.e. inverted values
+ *
+@@ -902,7 +923,7 @@
+ *
+ * Returns zero on success, else an error.
+ */
+-static int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value)
++int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value)
+ {
+ struct device *dev = NULL;
+ int status = -EINVAL;
+@@ -933,20 +954,15 @@
+
+ return status;
+ }
+-
+-int gpio_sysfs_set_active_low(unsigned gpio, int value)
+-{
+- return gpiod_sysfs_set_active_low(gpio_to_desc(gpio), value);
+-}
+-EXPORT_SYMBOL_GPL(gpio_sysfs_set_active_low);
++EXPORT_SYMBOL_GPL(gpiod_sysfs_set_active_low);
+
+ /**
+- * gpio_unexport - reverse effect of gpio_export()
++ * gpiod_unexport - reverse effect of gpio_export()
+ * @gpio: gpio to make unavailable
+ *
+ * This is implicit on gpio_free().
+ */
+-static void gpiod_unexport(struct gpio_desc *desc)
++void gpiod_unexport(struct gpio_desc *desc)
+ {
+ int status = 0;
+ struct device *dev = NULL;
+@@ -979,12 +995,7 @@
+ pr_debug("%s: gpio%d status %d\n", __func__, desc_to_gpio(desc),
+ status);
+ }
+-
+-void gpio_unexport(unsigned gpio)
+-{
+- gpiod_unexport(gpio_to_desc(gpio));
+-}
+-EXPORT_SYMBOL_GPL(gpio_unexport);
++EXPORT_SYMBOL_GPL(gpiod_unexport);
+
+ static int gpiochip_export(struct gpio_chip *chip)
+ {
+@@ -1091,27 +1102,6 @@
+ {
+ }
+
+-static inline int gpiod_export(struct gpio_desc *desc,
+- bool direction_may_change)
+-{
+- return -ENOSYS;
+-}
+-
+-static inline int gpiod_export_link(struct device *dev, const char *name,
+- struct gpio_desc *desc)
+-{
+- return -ENOSYS;
+-}
+-
+-static inline int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value)
+-{
+- return -ENOSYS;
+-}
+-
+-static inline void gpiod_unexport(struct gpio_desc *desc)
+-{
+-}
+-
+ #endif /* CONFIG_GPIO_SYSFS */
+
+ /*
+@@ -1214,15 +1204,14 @@
+ }
+ }
+
++ spin_unlock_irqrestore(&gpio_lock, flags);
++
+ #ifdef CONFIG_PINCTRL
+ INIT_LIST_HEAD(&chip->pin_ranges);
+ #endif
+
+ of_gpiochip_add(chip);
+
+-unlock:
+- spin_unlock_irqrestore(&gpio_lock, flags);
+-
+ if (status)
+ goto fail;
+
+@@ -1235,6 +1224,9 @@
+ chip->label ? : "generic");
+
+ return 0;
++
++unlock:
++ spin_unlock_irqrestore(&gpio_lock, flags);
+ fail:
+ /* failures here can mean systems won't boot... */
+ pr_err("gpiochip_add: gpios %d..%d (%s) failed to register\n",
+@@ -1315,6 +1307,18 @@
+ }
+ EXPORT_SYMBOL_GPL(gpiochip_find);
+
++static int gpiochip_match_name(struct gpio_chip *chip, void *data)
++{
++ const char *name = data;
++
++ return !strcmp(chip->label, name);
++}
++
++static struct gpio_chip *find_chip_by_name(const char *name)
++{
++ return gpiochip_find((void *)name, gpiochip_match_name);
++}
++
+ #ifdef CONFIG_PINCTRL
+
+ /**
+@@ -1621,23 +1625,37 @@
+ * rely on gpio_request() having been called beforehand.
+ */
+
+-static int gpiod_direction_input(struct gpio_desc *desc)
++/**
++ * gpiod_direction_input - set the GPIO direction to input
++ * @desc: GPIO to set to input
++ *
++ * Set the direction of the passed GPIO to input, such as gpiod_get_value() can
++ * be called safely on it.
++ *
++ * Return 0 in case of success, else an error code.
++ */
++int gpiod_direction_input(struct gpio_desc *desc)
+ {
+ unsigned long flags;
+ struct gpio_chip *chip;
+ int status = -EINVAL;
+ int offset;
+
+- if (!desc) {
++ if (!desc || !desc->chip) {
+ pr_warn("%s: invalid GPIO\n", __func__);
+ return -EINVAL;
+ }
+
++ chip = desc->chip;
++ if (!chip->get || !chip->direction_input) {
++ gpiod_warn(desc,
++ "%s: missing get() or direction_input() operations\n",
++ __func__);
++ return -EIO;
++ }
++
+ spin_lock_irqsave(&gpio_lock, flags);
+
+- chip = desc->chip;
+- if (!chip || !chip->get || !chip->direction_input)
+- goto fail;
+ status = gpio_ensure_requested(desc);
+ if (status < 0)
+ goto fail;
+@@ -1652,8 +1670,7 @@
+ if (status) {
+ status = chip->request(chip, offset);
+ if (status < 0) {
+- pr_debug("GPIO-%d: chip request fail, %d\n",
+- desc_to_gpio(desc), status);
++ gpiod_dbg(desc, "chip request fail, %d\n", status);
+ /* and it's not available to anyone else ...
+ * gpio_request() is the fully clean solution.
+ */
+@@ -1671,29 +1688,41 @@
+ fail:
+ spin_unlock_irqrestore(&gpio_lock, flags);
+ if (status)
+- pr_debug("%s: gpio-%d status %d\n", __func__,
+- desc_to_gpio(desc), status);
++ gpiod_dbg(desc, "%s status %d\n", __func__, status);
+ return status;
+ }
++EXPORT_SYMBOL_GPL(gpiod_direction_input);
+
+-int gpio_direction_input(unsigned gpio)
+-{
+- return gpiod_direction_input(gpio_to_desc(gpio));
+-}
+-EXPORT_SYMBOL_GPL(gpio_direction_input);
+-
+-static int gpiod_direction_output(struct gpio_desc *desc, int value)
++/**
++ * gpiod_direction_output - set the GPIO direction to input
++ * @desc: GPIO to set to output
++ * @value: initial output value of the GPIO
++ *
++ * Set the direction of the passed GPIO to output, such as gpiod_set_value() can
++ * be called safely on it. The initial value of the output must be specified.
++ *
++ * Return 0 in case of success, else an error code.
++ */
++int gpiod_direction_output(struct gpio_desc *desc, int value)
+ {
+ unsigned long flags;
+ struct gpio_chip *chip;
+ int status = -EINVAL;
+ int offset;
+
+- if (!desc) {
++ if (!desc || !desc->chip) {
+ pr_warn("%s: invalid GPIO\n", __func__);
+ return -EINVAL;
+ }
+
++ /* GPIOs used for IRQs shall not be set as output */
++ if (test_bit(FLAG_USED_AS_IRQ, &desc->flags)) {
++ gpiod_err(desc,
++ "%s: tried to set a GPIO tied to an IRQ as output\n",
++ __func__);
++ return -EIO;
++ }
++
+ /* Open drain pin should not be driven to 1 */
+ if (value && test_bit(FLAG_OPEN_DRAIN, &desc->flags))
+ return gpiod_direction_input(desc);
+@@ -1702,11 +1731,16 @@
+ if (!value && test_bit(FLAG_OPEN_SOURCE, &desc->flags))
+ return gpiod_direction_input(desc);
+
++ chip = desc->chip;
++ if (!chip->set || !chip->direction_output) {
++ gpiod_warn(desc,
++ "%s: missing set() or direction_output() operations\n",
++ __func__);
++ return -EIO;
++ }
++
+ spin_lock_irqsave(&gpio_lock, flags);
+
+- chip = desc->chip;
+- if (!chip || !chip->set || !chip->direction_output)
+- goto fail;
+ status = gpio_ensure_requested(desc);
+ if (status < 0)
+ goto fail;
+@@ -1721,8 +1755,7 @@
+ if (status) {
+ status = chip->request(chip, offset);
+ if (status < 0) {
+- pr_debug("GPIO-%d: chip request fail, %d\n",
+- desc_to_gpio(desc), status);
++ gpiod_dbg(desc, "chip request fail, %d\n", status);
+ /* and it's not available to anyone else ...
+ * gpio_request() is the fully clean solution.
+ */
+@@ -1740,39 +1773,40 @@
+ fail:
+ spin_unlock_irqrestore(&gpio_lock, flags);
+ if (status)
+- pr_debug("%s: gpio-%d status %d\n", __func__,
+- desc_to_gpio(desc), status);
++ gpiod_dbg(desc, "%s: gpio status %d\n", __func__, status);
+ return status;
+ }
+-
+-int gpio_direction_output(unsigned gpio, int value)
+-{
+- return gpiod_direction_output(gpio_to_desc(gpio), value);
+-}
+-EXPORT_SYMBOL_GPL(gpio_direction_output);
++EXPORT_SYMBOL_GPL(gpiod_direction_output);
+
+ /**
+- * gpio_set_debounce - sets @debounce time for a @gpio
++ * gpiod_set_debounce - sets @debounce time for a @gpio
+ * @gpio: the gpio to set debounce time
+ * @debounce: debounce time is microseconds
++ *
++ * returns -ENOTSUPP if the controller does not support setting
++ * debounce.
+ */
+-static int gpiod_set_debounce(struct gpio_desc *desc, unsigned debounce)
++int gpiod_set_debounce(struct gpio_desc *desc, unsigned debounce)
+ {
+ unsigned long flags;
+ struct gpio_chip *chip;
+ int status = -EINVAL;
+ int offset;
+
+- if (!desc) {
++ if (!desc || !desc->chip) {
+ pr_warn("%s: invalid GPIO\n", __func__);
+ return -EINVAL;
+ }
+
+- spin_lock_irqsave(&gpio_lock, flags);
+-
+ chip = desc->chip;
+- if (!chip || !chip->set || !chip->set_debounce)
+- goto fail;
++ if (!chip->set || !chip->set_debounce) {
++ gpiod_dbg(desc,
++ "%s: missing set() or set_debounce() operations\n",
++ __func__);
++ return -ENOTSUPP;
++ }
++
++ spin_lock_irqsave(&gpio_lock, flags);
+
+ status = gpio_ensure_requested(desc);
+ if (status < 0)
+@@ -1790,17 +1824,23 @@
+ fail:
+ spin_unlock_irqrestore(&gpio_lock, flags);
+ if (status)
+- pr_debug("%s: gpio-%d status %d\n", __func__,
+- desc_to_gpio(desc), status);
++ gpiod_dbg(desc, "%s: status %d\n", __func__, status);
+
+ return status;
+ }
++EXPORT_SYMBOL_GPL(gpiod_set_debounce);
+
+-int gpio_set_debounce(unsigned gpio, unsigned debounce)
++/**
++ * gpiod_is_active_low - test whether a GPIO is active-low or not
++ * @desc: the gpio descriptor to test
++ *
++ * Returns 1 if the GPIO is active-low, 0 otherwise.
++ */
++int gpiod_is_active_low(const struct gpio_desc *desc)
+ {
+- return gpiod_set_debounce(gpio_to_desc(gpio), debounce);
++ return test_bit(FLAG_ACTIVE_LOW, &desc->flags);
+ }
+-EXPORT_SYMBOL_GPL(gpio_set_debounce);
++EXPORT_SYMBOL_GPL(gpiod_is_active_low);
+
+ /* I/O calls are only valid after configuration completed; the relevant
+ * "is this a valid GPIO" error checks should already have been done.
+@@ -1824,42 +1864,68 @@
+ * that the GPIO was actually requested.
+ */
+
+-/**
+- * __gpio_get_value() - return a gpio's value
+- * @gpio: gpio whose value will be returned
+- * Context: any
+- *
+- * This is used directly or indirectly to implement gpio_get_value().
+- * It returns the zero or nonzero value provided by the associated
+- * gpio_chip.get() method; or zero if no such method is provided.
+- */
+-static int gpiod_get_value(const struct gpio_desc *desc)
++static int _gpiod_get_raw_value(const struct gpio_desc *desc)
+ {
+ struct gpio_chip *chip;
+ int value;
+ int offset;
+
+- if (!desc)
+- return 0;
+ chip = desc->chip;
+ offset = gpio_chip_hwgpio(desc);
+- /* Should be using gpio_get_value_cansleep() */
+- WARN_ON(chip->can_sleep);
+ value = chip->get ? chip->get(chip, offset) : 0;
+ trace_gpio_value(desc_to_gpio(desc), 1, value);
+ return value;
+ }
+
+-int __gpio_get_value(unsigned gpio)
++/**
++ * gpiod_get_raw_value() - return a gpio's raw value
++ * @desc: gpio whose value will be returned
++ *
++ * Return the GPIO's raw value, i.e. the value of the physical line disregarding
++ * its ACTIVE_LOW status.
++ *
++ * This function should be called from contexts where we cannot sleep, and will
++ * complain if the GPIO chip functions potentially sleep.
++ */
++int gpiod_get_raw_value(const struct gpio_desc *desc)
+ {
+- return gpiod_get_value(gpio_to_desc(gpio));
++ if (!desc)
++ return 0;
++ /* Should be using gpio_get_value_cansleep() */
++ WARN_ON(desc->chip->can_sleep);
++ return _gpiod_get_raw_value(desc);
++}
++EXPORT_SYMBOL_GPL(gpiod_get_raw_value);
++
++/**
++ * gpiod_get_value() - return a gpio's value
++ * @desc: gpio whose value will be returned
++ *
++ * Return the GPIO's logical value, i.e. taking the ACTIVE_LOW status into
++ * account.
++ *
++ * This function should be called from contexts where we cannot sleep, and will
++ * complain if the GPIO chip functions potentially sleep.
++ */
++int gpiod_get_value(const struct gpio_desc *desc)
++{
++ int value;
++ if (!desc)
++ return 0;
++ /* Should be using gpio_get_value_cansleep() */
++ WARN_ON(desc->chip->can_sleep);
++
++ value = _gpiod_get_raw_value(desc);
++ if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
++ value = !value;
++
++ return value;
+ }
+-EXPORT_SYMBOL_GPL(__gpio_get_value);
++EXPORT_SYMBOL_GPL(gpiod_get_value);
+
+ /*
+ * _gpio_set_open_drain_value() - Set the open drain gpio's value.
+- * @gpio: Gpio whose state need to be set.
+- * @chip: Gpio chip.
++ * @desc: gpio descriptor whose state need to be set.
+ * @value: Non-zero for setting it HIGH otherise it will set to LOW.
+ */
+ static void _gpio_set_open_drain_value(struct gpio_desc *desc, int value)
+@@ -1879,14 +1945,14 @@
+ }
+ trace_gpio_direction(desc_to_gpio(desc), value, err);
+ if (err < 0)
+- pr_err("%s: Error in set_value for open drain gpio%d err %d\n",
+- __func__, desc_to_gpio(desc), err);
++ gpiod_err(desc,
++ "%s: Error in set_value for open drain err %d\n",
++ __func__, err);
+ }
+
+ /*
+- * _gpio_set_open_source() - Set the open source gpio's value.
+- * @gpio: Gpio whose state need to be set.
+- * @chip: Gpio chip.
++ * _gpio_set_open_source_value() - Set the open source gpio's value.
++ * @desc: gpio descriptor whose state need to be set.
+ * @value: Non-zero for setting it HIGH otherise it will set to LOW.
+ */
+ static void _gpio_set_open_source_value(struct gpio_desc *desc, int value)
+@@ -1906,28 +1972,16 @@
+ }
+ trace_gpio_direction(desc_to_gpio(desc), !value, err);
+ if (err < 0)
+- pr_err("%s: Error in set_value for open source gpio%d err %d\n",
+- __func__, desc_to_gpio(desc), err);
++ gpiod_err(desc,
++ "%s: Error in set_value for open source err %d\n",
++ __func__, err);
+ }
+
+-/**
+- * __gpio_set_value() - assign a gpio's value
+- * @gpio: gpio whose value will be assigned
+- * @value: value to assign
+- * Context: any
+- *
+- * This is used directly or indirectly to implement gpio_set_value().
+- * It invokes the associated gpio_chip.set() method.
+- */
+-static void gpiod_set_value(struct gpio_desc *desc, int value)
++static void _gpiod_set_raw_value(struct gpio_desc *desc, int value)
+ {
+ struct gpio_chip *chip;
+
+- if (!desc)
+- return;
+ chip = desc->chip;
+- /* Should be using gpio_set_value_cansleep() */
+- WARN_ON(chip->can_sleep);
+ trace_gpio_value(desc_to_gpio(desc), 0, value);
+ if (test_bit(FLAG_OPEN_DRAIN, &desc->flags))
+ _gpio_set_open_drain_value(desc, value);
+@@ -1937,44 +1991,71 @@
+ chip->set(chip, gpio_chip_hwgpio(desc), value);
+ }
+
+-void __gpio_set_value(unsigned gpio, int value)
++/**
++ * gpiod_set_raw_value() - assign a gpio's raw value
++ * @desc: gpio whose value will be assigned
++ * @value: value to assign
++ *
++ * Set the raw value of the GPIO, i.e. the value of its physical line without
++ * regard for its ACTIVE_LOW status.
++ *
++ * This function should be called from contexts where we cannot sleep, and will
++ * complain if the GPIO chip functions potentially sleep.
++ */
++void gpiod_set_raw_value(struct gpio_desc *desc, int value)
+ {
+- return gpiod_set_value(gpio_to_desc(gpio), value);
++ if (!desc)
++ return;
++ /* Should be using gpio_set_value_cansleep() */
++ WARN_ON(desc->chip->can_sleep);
++ _gpiod_set_raw_value(desc, value);
+ }
+-EXPORT_SYMBOL_GPL(__gpio_set_value);
++EXPORT_SYMBOL_GPL(gpiod_set_raw_value);
+
+ /**
+- * __gpio_cansleep() - report whether gpio value access will sleep
+- * @gpio: gpio in question
+- * Context: any
++ * gpiod_set_value() - assign a gpio's value
++ * @desc: gpio whose value will be assigned
++ * @value: value to assign
++ *
++ * Set the logical value of the GPIO, i.e. taking its ACTIVE_LOW status into
++ * account
+ *
+- * This is used directly or indirectly to implement gpio_cansleep(). It
+- * returns nonzero if access reading or writing the GPIO value can sleep.
++ * This function should be called from contexts where we cannot sleep, and will
++ * complain if the GPIO chip functions potentially sleep.
+ */
+-static int gpiod_cansleep(const struct gpio_desc *desc)
++void gpiod_set_value(struct gpio_desc *desc, int value)
+ {
+ if (!desc)
+- return 0;
+- /* only call this on GPIOs that are valid! */
+- return desc->chip->can_sleep;
++ return;
++ /* Should be using gpio_set_value_cansleep() */
++ WARN_ON(desc->chip->can_sleep);
++ if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
++ value = !value;
++ _gpiod_set_raw_value(desc, value);
+ }
++EXPORT_SYMBOL_GPL(gpiod_set_value);
+
+-int __gpio_cansleep(unsigned gpio)
++/**
++ * gpiod_cansleep() - report whether gpio value access may sleep
++ * @desc: gpio to check
++ *
++ */
++int gpiod_cansleep(const struct gpio_desc *desc)
+ {
+- return gpiod_cansleep(gpio_to_desc(gpio));
++ if (!desc)
++ return 0;
++ return desc->chip->can_sleep;
+ }
+-EXPORT_SYMBOL_GPL(__gpio_cansleep);
++EXPORT_SYMBOL_GPL(gpiod_cansleep);
+
+ /**
+- * __gpio_to_irq() - return the IRQ corresponding to a GPIO
+- * @gpio: gpio whose IRQ will be returned (already requested)
+- * Context: any
++ * gpiod_to_irq() - return the IRQ corresponding to a GPIO
++ * @desc: gpio whose IRQ will be returned (already requested)
+ *
+- * This is used directly or indirectly to implement gpio_to_irq().
+- * It returns the number of the IRQ signaled by this (input) GPIO,
+- * or a negative errno.
++ * Return the IRQ corresponding to the passed GPIO, or an error code in case of
++ * error.
+ */
+-static int gpiod_to_irq(const struct gpio_desc *desc)
++int gpiod_to_irq(const struct gpio_desc *desc)
+ {
+ struct gpio_chip *chip;
+ int offset;
+@@ -1985,62 +2066,336 @@
+ offset = gpio_chip_hwgpio(desc);
+ return chip->to_irq ? chip->to_irq(chip, offset) : -ENXIO;
+ }
++EXPORT_SYMBOL_GPL(gpiod_to_irq);
+
+-int __gpio_to_irq(unsigned gpio)
++/**
++ * gpiod_lock_as_irq() - lock a GPIO to be used as IRQ
++ * @gpio: the GPIO line to lock as used for IRQ
++ *
++ * This is used directly by GPIO drivers that want to lock down
++ * a certain GPIO line to be used as IRQs, for example in the
++ * .to_irq() callback of their gpio_chip, or in the .irq_enable()
++ * of its irq_chip implementation if the GPIO is known from that
++ * code.
++ */
++int gpiod_lock_as_irq(struct gpio_desc *desc)
+ {
+- return gpiod_to_irq(gpio_to_desc(gpio));
++ if (!desc)
++ return -EINVAL;
++
++ if (test_bit(FLAG_IS_OUT, &desc->flags)) {
++ gpiod_err(desc,
++ "%s: tried to flag a GPIO set as output for IRQ\n",
++ __func__);
++ return -EIO;
++ }
++
++ set_bit(FLAG_USED_AS_IRQ, &desc->flags);
++ return 0;
+ }
+-EXPORT_SYMBOL_GPL(__gpio_to_irq);
++EXPORT_SYMBOL_GPL(gpiod_lock_as_irq);
+
++int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset)
++{
++ return gpiod_lock_as_irq(gpiochip_offset_to_desc(chip, offset));
++}
++EXPORT_SYMBOL_GPL(gpio_lock_as_irq);
+
+-/* There's no value in making it easy to inline GPIO calls that may sleep.
+- * Common examples include ones connected to I2C or SPI chips.
++/**
++ * gpiod_unlock_as_irq() - unlock a GPIO used as IRQ
++ * @gpio: the GPIO line to unlock from IRQ usage
++ *
++ * This is used directly by GPIO drivers that want to indicate
++ * that a certain GPIO is no longer used exclusively for IRQ.
+ */
++void gpiod_unlock_as_irq(struct gpio_desc *desc)
++{
++ if (!desc)
++ return;
+
+-static int gpiod_get_value_cansleep(const struct gpio_desc *desc)
++ clear_bit(FLAG_USED_AS_IRQ, &desc->flags);
++}
++EXPORT_SYMBOL_GPL(gpiod_unlock_as_irq);
++
++void gpio_unlock_as_irq(struct gpio_chip *chip, unsigned int offset)
++{
++ return gpiod_unlock_as_irq(gpiochip_offset_to_desc(chip, offset));
++}
++EXPORT_SYMBOL_GPL(gpio_unlock_as_irq);
++
++/**
++ * gpiod_get_raw_value_cansleep() - return a gpio's raw value
++ * @desc: gpio whose value will be returned
++ *
++ * Return the GPIO's raw value, i.e. the value of the physical line disregarding
++ * its ACTIVE_LOW status.
++ *
++ * This function is to be called from contexts that can sleep.
++ */
++int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)
++{
++ might_sleep_if(extra_checks);
++ if (!desc)
++ return 0;
++ return _gpiod_get_raw_value(desc);
++}
++EXPORT_SYMBOL_GPL(gpiod_get_raw_value_cansleep);
++
++/**
++ * gpiod_get_value_cansleep() - return a gpio's value
++ * @desc: gpio whose value will be returned
++ *
++ * Return the GPIO's logical value, i.e. taking the ACTIVE_LOW status into
++ * account.
++ *
++ * This function is to be called from contexts that can sleep.
++ */
++int gpiod_get_value_cansleep(const struct gpio_desc *desc)
+ {
+- struct gpio_chip *chip;
+ int value;
+- int offset;
+
+ might_sleep_if(extra_checks);
+ if (!desc)
+ return 0;
+- chip = desc->chip;
+- offset = gpio_chip_hwgpio(desc);
+- value = chip->get ? chip->get(chip, offset) : 0;
+- trace_gpio_value(desc_to_gpio(desc), 1, value);
++
++ value = _gpiod_get_raw_value(desc);
++ if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
++ value = !value;
++
+ return value;
+ }
++EXPORT_SYMBOL_GPL(gpiod_get_value_cansleep);
+
+-int gpio_get_value_cansleep(unsigned gpio)
++/**
++ * gpiod_set_raw_value_cansleep() - assign a gpio's raw value
++ * @desc: gpio whose value will be assigned
++ * @value: value to assign
++ *
++ * Set the raw value of the GPIO, i.e. the value of its physical line without
++ * regard for its ACTIVE_LOW status.
++ *
++ * This function is to be called from contexts that can sleep.
++ */
++void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value)
+ {
+- return gpiod_get_value_cansleep(gpio_to_desc(gpio));
++ might_sleep_if(extra_checks);
++ if (!desc)
++ return;
++ _gpiod_set_raw_value(desc, value);
+ }
+-EXPORT_SYMBOL_GPL(gpio_get_value_cansleep);
++EXPORT_SYMBOL_GPL(gpiod_set_raw_value_cansleep);
+
+-static void gpiod_set_value_cansleep(struct gpio_desc *desc, int value)
++/**
++ * gpiod_set_value_cansleep() - assign a gpio's value
++ * @desc: gpio whose value will be assigned
++ * @value: value to assign
++ *
++ * Set the logical value of the GPIO, i.e. taking its ACTIVE_LOW status into
++ * account
++ *
++ * This function is to be called from contexts that can sleep.
++ */
++void gpiod_set_value_cansleep(struct gpio_desc *desc, int value)
+ {
+- struct gpio_chip *chip;
+-
+ might_sleep_if(extra_checks);
+ if (!desc)
+ return;
+- chip = desc->chip;
+- trace_gpio_value(desc_to_gpio(desc), 0, value);
+- if (test_bit(FLAG_OPEN_DRAIN, &desc->flags))
+- _gpio_set_open_drain_value(desc, value);
+- else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags))
+- _gpio_set_open_source_value(desc, value);
++
++ if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
++ value = !value;
++ _gpiod_set_raw_value(desc, value);
++}
++EXPORT_SYMBOL_GPL(gpiod_set_value_cansleep);
++
++/**
++ * gpiod_add_table() - register GPIO device consumers
++ * @table: array of consumers to register
++ * @num: number of consumers in table
++ */
++void gpiod_add_table(struct gpiod_lookup *table, size_t size)
++{
++ mutex_lock(&gpio_lookup_lock);
++
++ while (size--) {
++ list_add_tail(&table->list, &gpio_lookup_list);
++ table++;
++ }
++
++ mutex_unlock(&gpio_lookup_lock);
++}
++
++#ifdef CONFIG_OF
++static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
++ unsigned int idx,
++ enum gpio_lookup_flags *flags)
++{
++ char prop_name[32]; /* 32 is max size of property name */
++ enum of_gpio_flags of_flags;
++ struct gpio_desc *desc;
++
++ if (con_id)
++ snprintf(prop_name, 32, "%s-gpios", con_id);
+ else
+- chip->set(chip, gpio_chip_hwgpio(desc), value);
++ snprintf(prop_name, 32, "gpios");
++
++ desc = of_get_named_gpiod_flags(dev->of_node, prop_name, idx,
++ &of_flags);
++
++ if (IS_ERR(desc))
++ return desc;
++
++ if (of_flags & OF_GPIO_ACTIVE_LOW)
++ *flags |= GPIO_ACTIVE_LOW;
++
++ return desc;
++}
++#else
++static struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id,
++ unsigned int idx, unsigned long *flags)
++{
++ return ERR_PTR(-ENODEV);
++}
++#endif
++
++static struct gpio_desc *gpiod_find(struct device *dev, const char *con_id,
++ unsigned int idx,
++ enum gpio_lookup_flags *flags)
++{
++ const char *dev_id = dev ? dev_name(dev) : NULL;
++ struct gpio_desc *desc = ERR_PTR(-ENODEV);
++ unsigned int match, best = 0;
++ struct gpiod_lookup *p;
++
++ mutex_lock(&gpio_lookup_lock);
++
++ list_for_each_entry(p, &gpio_lookup_list, list) {
++ match = 0;
++
++ if (p->dev_id) {
++ if (!dev_id || strcmp(p->dev_id, dev_id))
++ continue;
++
++ match += 2;
++ }
++
++ if (p->con_id) {
++ if (!con_id || strcmp(p->con_id, con_id))
++ continue;
++
++ match += 1;
++ }
++
++ if (p->idx != idx)
++ continue;
++
++ if (match > best) {
++ struct gpio_chip *chip;
++
++ chip = find_chip_by_name(p->chip_label);
++
++ if (!chip) {
++ dev_warn(dev, "cannot find GPIO chip %s\n",
++ p->chip_label);
++ continue;
++ }
++
++ if (chip->ngpio >= p->chip_hwnum) {
++ dev_warn(dev, "GPIO chip %s has %d GPIOs\n",
++ chip->label, chip->ngpio);
++ continue;
++ }
++
++ desc = gpio_to_desc(chip->base + p->chip_hwnum);
++ *flags = p->flags;
++
++ if (match != 3)
++ best = match;
++ else
++ break;
++ }
++ }
++
++ mutex_unlock(&gpio_lookup_lock);
++
++ return desc;
++}
++
++/**
++ * gpio_get - obtain a GPIO for a given GPIO function
++ * @dev: GPIO consumer
++ * @con_id: function within the GPIO consumer
++ *
++ * Return the GPIO descriptor corresponding to the function con_id of device
++ * dev, or an IS_ERR() condition if an error occured.
++ */
++struct gpio_desc *__must_check gpiod_get(struct device *dev, const char *con_id)
++{
++ return gpiod_get_index(dev, con_id, 0);
++}
++EXPORT_SYMBOL_GPL(gpiod_get);
++
++/**
++ * gpiod_get_index - obtain a GPIO from a multi-index GPIO function
++ * @dev: GPIO consumer
++ * @con_id: function within the GPIO consumer
++ * @idx: index of the GPIO to obtain in the consumer
++ *
++ * This variant of gpiod_get() allows to access GPIOs other than the first
++ * defined one for functions that define several GPIOs.
++ *
++ * Return a valid GPIO descriptor, or an IS_ERR() condition in case of error.
++ */
++struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
++ const char *con_id,
++ unsigned int idx)
++{
++ struct gpio_desc *desc;
++ int status;
++ enum gpio_lookup_flags flags = 0;
++
++ dev_dbg(dev, "GPIO lookup for consumer %s\n", con_id);
++
++ /* Using device tree? */
++ if (IS_ENABLED(CONFIG_OF) && dev && dev->of_node) {
++ dev_dbg(dev, "using device tree for GPIO lookup\n");
++ desc = of_find_gpio(dev, con_id, idx, &flags);
++ } else {
++ dev_dbg(dev, "using lookup tables for GPIO lookup");
++ desc = gpiod_find(dev, con_id, idx, &flags);
++ }
++
++ if (IS_ERR(desc)) {
++ dev_warn(dev, "lookup for GPIO %s failed\n", con_id);
++ return desc;
++ }
++
++ status = gpiod_request(desc, con_id);
++
++ if (status < 0)
++ return ERR_PTR(status);
++
++ if (flags & GPIO_ACTIVE_LOW)
++ set_bit(FLAG_ACTIVE_LOW, &desc->flags);
++ if (flags & GPIO_OPEN_DRAIN)
++ set_bit(FLAG_OPEN_DRAIN, &desc->flags);
++ if (flags & GPIO_OPEN_SOURCE)
++ set_bit(FLAG_OPEN_SOURCE, &desc->flags);
++
++ return desc;
+ }
++EXPORT_SYMBOL_GPL(gpiod_get_index);
+
+-void gpio_set_value_cansleep(unsigned gpio, int value)
++/**
++ * gpiod_put - dispose of a GPIO descriptor
++ * @desc: GPIO descriptor to dispose of
++ *
++ * No descriptor can be used after gpiod_put() has been called on it.
++ */
++void gpiod_put(struct gpio_desc *desc)
+ {
+- return gpiod_set_value_cansleep(gpio_to_desc(gpio), value);
++ gpiod_free(desc);
+ }
+-EXPORT_SYMBOL_GPL(gpio_set_value_cansleep);
++EXPORT_SYMBOL_GPL(gpiod_put);
+
+ #ifdef CONFIG_DEBUG_FS
+
+@@ -2050,6 +2405,7 @@
+ unsigned gpio = chip->base;
+ struct gpio_desc *gdesc = &chip->desc[0];
+ int is_out;
++ int is_irq;
+
+ for (i = 0; i < chip->ngpio; i++, gpio++, gdesc++) {
+ if (!test_bit(FLAG_REQUESTED, &gdesc->flags))
+@@ -2057,12 +2413,14 @@
+
+ gpiod_get_direction(gdesc);
+ is_out = test_bit(FLAG_IS_OUT, &gdesc->flags);
+- seq_printf(s, " gpio-%-3d (%-20.20s) %s %s",
++ is_irq = test_bit(FLAG_USED_AS_IRQ, &gdesc->flags);
++ seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s",
+ gpio, gdesc->label,
+ is_out ? "out" : "in ",
+ chip->get
+ ? (chip->get(chip, i) ? "hi" : "lo")
+- : "? ");
++ : "? ",
++ is_irq ? "IRQ" : " ");
+ seq_printf(s, "\n");
+ }
+ }
+diff -Nur linux-3.10.30.orig/drivers/gpio/gpiolib-of.c linux-linaro-stable-mx6/drivers/gpio/gpiolib-of.c
+--- linux-3.10.30.orig/drivers/gpio/gpiolib-of.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpio/gpiolib-of.c 2014-05-15 20:33:47.001934610 +0200
+@@ -15,19 +15,21 @@
+ #include <linux/errno.h>
+ #include <linux/module.h>
+ #include <linux/io.h>
+-#include <linux/gpio.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_gpio.h>
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/slab.h>
+
++struct gpio_desc;
++
+ /* Private data structure for of_gpiochip_find_and_xlate */
+ struct gg_data {
+ enum of_gpio_flags *flags;
+ struct of_phandle_args gpiospec;
+
+- int out_gpio;
++ struct gpio_desc *out_gpio;
+ };
+
+ /* Private function for resolving node pointer to gpio_chip */
+@@ -45,28 +47,31 @@
+ if (ret < 0)
+ return false;
+
+- gg_data->out_gpio = ret + gc->base;
++ gg_data->out_gpio = gpio_to_desc(ret + gc->base);
+ return true;
+ }
+
+ /**
+- * of_get_named_gpio_flags() - Get a GPIO number and flags to use with GPIO API
++ * of_get_named_gpiod_flags() - Get a GPIO descriptor and flags for GPIO API
+ * @np: device node to get GPIO from
+ * @propname: property name containing gpio specifier(s)
+ * @index: index of the GPIO
+ * @flags: a flags pointer to fill in
+ *
+- * Returns GPIO number to use with Linux generic GPIO API, or one of the errno
++ * Returns GPIO descriptor to use with Linux GPIO API, or one of the errno
+ * value on the error condition. If @flags is not NULL the function also fills
+ * in flags for the GPIO.
+ */
+-int of_get_named_gpio_flags(struct device_node *np, const char *propname,
+- int index, enum of_gpio_flags *flags)
++struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np,
++ const char *propname, int index, enum of_gpio_flags *flags)
+ {
+ /* Return -EPROBE_DEFER to support probe() functions to be called
+ * later when the GPIO actually becomes available
+ */
+- struct gg_data gg_data = { .flags = flags, .out_gpio = -EPROBE_DEFER };
++ struct gg_data gg_data = {
++ .flags = flags,
++ .out_gpio = ERR_PTR(-EPROBE_DEFER)
++ };
+ int ret;
+
+ /* .of_xlate might decide to not fill in the flags, so clear it. */
+@@ -76,17 +81,19 @@
+ ret = of_parse_phandle_with_args(np, propname, "#gpio-cells", index,
+ &gg_data.gpiospec);
+ if (ret) {
+- pr_debug("%s: can't parse gpios property\n", __func__);
+- return ret;
++ pr_debug("%s: can't parse gpios property of node '%s[%d]'\n",
++ __func__, np->full_name, index);
++ return ERR_PTR(ret);
+ }
+
+ gpiochip_find(&gg_data, of_gpiochip_find_and_xlate);
+
+ of_node_put(gg_data.gpiospec.np);
+- pr_debug("%s exited with status %d\n", __func__, gg_data.out_gpio);
++ pr_debug("%s exited with status %d\n", __func__,
++ PTR_RET(gg_data.out_gpio));
+ return gg_data.out_gpio;
+ }
+-EXPORT_SYMBOL(of_get_named_gpio_flags);
++EXPORT_SYMBOL(of_get_named_gpiod_flags);
+
+ /**
+ * of_gpio_simple_xlate - translate gpio_spec to the GPIO number and flags
+@@ -194,8 +201,8 @@
+ return;
+
+ for (;; index++) {
+- ret = of_parse_phandle_with_args(np, "gpio-ranges",
+- "#gpio-range-cells", index, &pinspec);
++ ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
++ index, &pinspec);
+ if (ret)
+ break;
+
+diff -Nur linux-3.10.30.orig/drivers/gpio/gpio-mxc.c linux-linaro-stable-mx6/drivers/gpio/gpio-mxc.c
+--- linux-3.10.30.orig/drivers/gpio/gpio-mxc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpio/gpio-mxc.c 2014-05-15 20:33:46.985934494 +0200
+@@ -405,34 +405,19 @@
+
+ mxc_gpio_get_hw(pdev);
+
+- port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
++ port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!iores) {
+- err = -ENODEV;
+- goto out_kfree;
+- }
+-
+- if (!request_mem_region(iores->start, resource_size(iores),
+- pdev->name)) {
+- err = -EBUSY;
+- goto out_kfree;
+- }
+-
+- port->base = ioremap(iores->start, resource_size(iores));
+- if (!port->base) {
+- err = -ENOMEM;
+- goto out_release_mem;
+- }
++ port->base = devm_ioremap_resource(&pdev->dev, iores);
++ if (IS_ERR(port->base))
++ return PTR_ERR(port->base);
+
+ port->irq_high = platform_get_irq(pdev, 1);
+ port->irq = platform_get_irq(pdev, 0);
+- if (port->irq < 0) {
+- err = -EINVAL;
+- goto out_iounmap;
+- }
++ if (port->irq < 0)
++ return -EINVAL;
+
+ /* disable the interrupt and clear the status */
+ writel(0, port->base + GPIO_IMR);
+@@ -462,7 +447,7 @@
+ port->base + GPIO_DR, NULL,
+ port->base + GPIO_GDIR, NULL, 0);
+ if (err)
+- goto out_iounmap;
++ goto out_bgio;
+
+ port->bgc.gc.to_irq = mxc_gpio_to_irq;
+ port->bgc.gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
+@@ -498,12 +483,7 @@
+ WARN_ON(gpiochip_remove(&port->bgc.gc) < 0);
+ out_bgpio_remove:
+ bgpio_remove(&port->bgc);
+-out_iounmap:
+- iounmap(port->base);
+-out_release_mem:
+- release_mem_region(iores->start, resource_size(iores));
+-out_kfree:
+- kfree(port);
++out_bgio:
+ dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
+ return err;
+ }
+diff -Nur linux-3.10.30.orig/drivers/gpio/gpio-pca953x.c linux-linaro-stable-mx6/drivers/gpio/gpio-pca953x.c
+--- linux-3.10.30.orig/drivers/gpio/gpio-pca953x.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpio/gpio-pca953x.c 2014-05-15 20:33:46.985934494 +0200
+@@ -19,6 +19,7 @@
+ #include <linux/irqdomain.h>
+ #include <linux/i2c.h>
+ #include <linux/i2c/pca953x.h>
++#include <linux/reset.h>
+ #include <linux/slab.h>
+ #ifdef CONFIG_OF_GPIO
+ #include <linux/of_platform.h>
+@@ -752,6 +753,10 @@
+
+ mutex_init(&chip->i2c_lock);
+
++ ret = device_reset(&client->dev);
++ if (ret == -ENODEV)
++ return -EPROBE_DEFER;
++
+ /* initialize cached registers from their original values.
+ * we can't share this chip with another i2c master.
+ */
+diff -Nur linux-3.10.30.orig/drivers/gpu/drm/drm_crtc_helper.c linux-linaro-stable-mx6/drivers/gpu/drm/drm_crtc_helper.c
+--- linux-3.10.30.orig/drivers/gpu/drm/drm_crtc_helper.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpu/drm/drm_crtc_helper.c 2014-05-15 20:33:47.029934812 +0200
+@@ -308,6 +308,29 @@
+ EXPORT_SYMBOL(drm_helper_disable_unused_functions);
+
+ /**
++ * drm_helper_crtc_possible_mask - find the mask of a registered CRTC
++ * @crtc: crtc to find mask for
++ *
++ * Given a registered CRTC, return the mask bit of that CRTC for an
++ * encoder's possible_crtcs field.
++ */
++uint32_t drm_helper_crtc_possible_mask(struct drm_crtc *crtc)
++{
++ struct drm_device *dev = crtc->dev;
++ struct drm_crtc *tmp;
++ uint32_t crtc_mask = 1;
++
++ list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
++ if (tmp == crtc)
++ return crtc_mask;
++ crtc_mask <<= 1;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(drm_helper_crtc_possible_mask);
++
++/**
+ * drm_encoder_crtc_ok - can a given crtc drive a given encoder?
+ * @encoder: encoder to test
+ * @crtc: crtc to test
+@@ -317,23 +340,13 @@
+ static bool drm_encoder_crtc_ok(struct drm_encoder *encoder,
+ struct drm_crtc *crtc)
+ {
+- struct drm_device *dev;
+- struct drm_crtc *tmp;
+- int crtc_mask = 1;
++ uint32_t crtc_mask;
+
+ WARN(!crtc, "checking null crtc?\n");
+
+- dev = crtc->dev;
+-
+- list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
+- if (tmp == crtc)
+- break;
+- crtc_mask <<= 1;
+- }
++ crtc_mask = drm_helper_crtc_possible_mask(crtc);
+
+- if (encoder->possible_crtcs & crtc_mask)
+- return true;
+- return false;
++ return !!(encoder->possible_crtcs & crtc_mask);
+ }
+
+ /*
+diff -Nur linux-3.10.30.orig/drivers/gpu/drm/Kconfig linux-linaro-stable-mx6/drivers/gpu/drm/Kconfig
+--- linux-3.10.30.orig/drivers/gpu/drm/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpu/drm/Kconfig 2014-05-15 20:33:47.001934610 +0200
+@@ -199,6 +199,13 @@
+ Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
+ chipset. If M is selected the module will be called savage.
+
++config DRM_VIVANTE
++ tristate "Vivante GCCore"
++ depends on DRM
++ help
++ Choose this option if you have a Vivante graphics card.
++ If M is selected, the module will be called vivante.
++
+ source "drivers/gpu/drm/exynos/Kconfig"
+
+ source "drivers/gpu/drm/vmwgfx/Kconfig"
+diff -Nur linux-3.10.30.orig/drivers/gpu/drm/Makefile linux-linaro-stable-mx6/drivers/gpu/drm/Makefile
+--- linux-3.10.30.orig/drivers/gpu/drm/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpu/drm/Makefile 2014-05-15 20:33:47.001934610 +0200
+@@ -1,3 +1,24 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2013 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
+ #
+ # Makefile for the drm device driver. This driver provides support for the
+ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
+@@ -29,8 +50,8 @@
+ CFLAGS_drm_trace_points.o := -I$(src)
+
+ obj-$(CONFIG_DRM) += drm.o
+-obj-$(CONFIG_DRM_USB) += drm_usb.o
+ obj-$(CONFIG_DRM_TTM) += ttm/
++obj-$(CONFIG_DRM_VIVANTE) += vivante/
+ obj-$(CONFIG_DRM_TDFX) += tdfx/
+ obj-$(CONFIG_DRM_R128) += r128/
+ obj-$(CONFIG_DRM_RADEON)+= radeon/
+diff -Nur linux-3.10.30.orig/drivers/gpu/drm/vivante/Makefile linux-linaro-stable-mx6/drivers/gpu/drm/vivante/Makefile
+--- linux-3.10.30.orig/drivers/gpu/drm/vivante/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpu/drm/vivante/Makefile 2014-05-15 20:33:54.229986710 +0200
+@@ -0,0 +1,29 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2013 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++#
++# Makefile for the drm device driver. This driver provides support for the
++# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
++
++ccflags-y := -Iinclude/drm
++vivante-y := vivante_drv.o
++
++obj-$(CONFIG_DRM_VIVANTE) += vivante.o
+diff -Nur linux-3.10.30.orig/drivers/gpu/drm/vivante/vivante_drv.c linux-linaro-stable-mx6/drivers/gpu/drm/vivante/vivante_drv.c
+--- linux-3.10.30.orig/drivers/gpu/drm/vivante/vivante_drv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpu/drm/vivante/vivante_drv.c 2014-05-15 20:33:54.229986710 +0200
+@@ -0,0 +1,111 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/* vivante_drv.c -- vivante driver -*- linux-c -*-
++ *
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Rickard E. (Rik) Faith <faith@valinux.com>
++ * Daryll Strauss <daryll@valinux.com>
++ * Gareth Hughes <gareth@valinux.com>
++ */
++
++#include <linux/version.h>
++#include <linux/module.h>
++
++#include "drmP.h"
++#include "vivante_drv.h"
++
++#include "drm_pciids.h"
++
++static char platformdevicename[] = "Vivante GCCore";
++static struct platform_device *pplatformdev;
++
++static const struct file_operations viv_driver_fops = {
++ .owner = THIS_MODULE,
++ .open = drm_open,
++ .release = drm_release,
++ .unlocked_ioctl = drm_ioctl,
++ .mmap = drm_mmap,
++ .poll = drm_poll,
++ .fasync = drm_fasync,
++ .llseek = noop_llseek,
++};
++
++static struct drm_driver driver = {
++ .driver_features = DRIVER_USE_MTRR,
++ .fops = &viv_driver_fops,
++ .name = DRIVER_NAME,
++ .desc = DRIVER_DESC,
++ .date = DRIVER_DATE,
++ .major = DRIVER_MAJOR,
++ .minor = DRIVER_MINOR,
++ .patchlevel = DRIVER_PATCHLEVEL,
++};
++
++static int __init vivante_init(void)
++{
++ int retcode;
++
++ pplatformdev = platform_device_register_simple(platformdevicename,
++ -1, NULL, 0);
++ if (pplatformdev == NULL)
++ printk(KERN_ERR"Platform device is null\n");
++
++ retcode = drm_platform_init(&driver, pplatformdev);
++
++ return retcode;
++}
++
++static void __exit vivante_exit(void)
++{
++ if (pplatformdev) {
++ drm_platform_exit(&driver, pplatformdev);
++ platform_device_unregister(pplatformdev);
++ pplatformdev = NULL;
++ }
++}
++
++module_init(vivante_init);
++module_exit(vivante_exit);
++
++MODULE_AUTHOR(DRIVER_AUTHOR);
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_LICENSE("GPL and additional rights");
+diff -Nur linux-3.10.30.orig/drivers/gpu/drm/vivante/vivante_drv.h linux-linaro-stable-mx6/drivers/gpu/drm/vivante/vivante_drv.h
+--- linux-3.10.30.orig/drivers/gpu/drm/vivante/vivante_drv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/gpu/drm/vivante/vivante_drv.h 2014-05-15 20:33:54.229986710 +0200
+@@ -0,0 +1,66 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/* vivante_drv.h -- Vivante DRM template customization -*- linux-c -*-
++ * Created: Wed Feb 14 12:32:32 2012 by John Zhao
++ */
++/*
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Gareth Hughes <gareth@valinux.com>
++ */
++
++#ifndef __VIVANTE_DRV_H__
++#define __VIVANTE_DRV_H__
++
++/* General customization:
++ */
++
++#define DRIVER_AUTHOR "Vivante Inc."
++
++#define DRIVER_NAME "vivante"
++#define DRIVER_DESC "Vivante GCCore"
++#define DRIVER_DATE "20120216"
++
++#define DRIVER_MAJOR 1
++#define DRIVER_MINOR 0
++#define DRIVER_PATCHLEVEL 0
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/hwmon/Kconfig linux-linaro-stable-mx6/drivers/hwmon/Kconfig
+--- linux-3.10.30.orig/drivers/hwmon/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/hwmon/Kconfig 2014-05-15 20:33:54.425988123 +0200
+@@ -867,6 +867,15 @@
+ This driver can also be built as a module. If so, the module
+ will be called max1668.
+
++config SENSORS_MAX17135
++ tristate "Maxim MAX17135 EPD temperature sensor"
++ depends on I2C
++ help
++ If you say yes here you get support for MAX17135 PMIC sensor.
++
++ This driver can also be built as a module. If so, the module
++ will be called max17135_sensor.
++
+ config SENSORS_MAX197
+ tristate "Maxim MAX197 and compatibles"
+ help
+@@ -1556,4 +1565,18 @@
+
+ endif # ACPI
+
++config SENSORS_MAG3110
++ tristate "Freescale MAG3110 e-compass sensor"
++ depends on I2C && SYSFS
++ help
++ If you say yes here you get support for the Freescale MAG3110
++ e-compass sensor.
++ This driver can also be built as a module. If so, the module
++ will be called mag3110.
++
++config MXC_MMA8451
++ tristate "MMA8451 device driver"
++ depends on I2C
++ default y
++
+ endif # HWMON
+diff -Nur linux-3.10.30.orig/drivers/hwmon/mag3110.c linux-linaro-stable-mx6/drivers/hwmon/mag3110.c
+--- linux-3.10.30.orig/drivers/hwmon/mag3110.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/hwmon/mag3110.c 2014-05-15 20:33:54.505988699 +0200
+@@ -0,0 +1,611 @@
++/*
++ *
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/i2c.h>
++#include <linux/irq.h>
++#include <linux/platform_device.h>
++#include <linux/input-polldev.h>
++#include <linux/hwmon.h>
++#include <linux/input.h>
++#include <linux/wait.h>
++#include <linux/workqueue.h>
++#include <linux/of.h>
++#include <linux/regulator/consumer.h>
++
++#define MAG3110_DRV_NAME "mag3110"
++#define MAG3110_ID 0xC4
++#define MAG3110_XYZ_DATA_LEN 6
++#define MAG3110_STATUS_ZYXDR 0x08
++
++#define MAG3110_AC_MASK (0x01)
++#define MAG3110_AC_OFFSET 0
++#define MAG3110_DR_MODE_MASK (0x7 << 5)
++#define MAG3110_DR_MODE_OFFSET 5
++#define MAG3110_IRQ_USED 0
++
++#define POLL_INTERVAL_MAX 500
++#define POLL_INTERVAL 100
++#define INT_TIMEOUT 1000
++#define DEFAULT_POSITION 2
++/* register enum for mag3110 registers */
++enum {
++ MAG3110_DR_STATUS = 0x00,
++ MAG3110_OUT_X_MSB,
++ MAG3110_OUT_X_LSB,
++ MAG3110_OUT_Y_MSB,
++ MAG3110_OUT_Y_LSB,
++ MAG3110_OUT_Z_MSB,
++ MAG3110_OUT_Z_LSB,
++ MAG3110_WHO_AM_I,
++
++ MAG3110_OFF_X_MSB,
++ MAG3110_OFF_X_LSB,
++ MAG3110_OFF_Y_MSB,
++ MAG3110_OFF_Y_LSB,
++ MAG3110_OFF_Z_MSB,
++ MAG3110_OFF_Z_LSB,
++
++ MAG3110_DIE_TEMP,
++
++ MAG3110_CTRL_REG1 = 0x10,
++ MAG3110_CTRL_REG2,
++};
++enum {
++ MAG_STANDBY,
++ MAG_ACTIVED
++};
++struct mag3110_data {
++ struct i2c_client *client;
++ struct input_polled_dev *poll_dev;
++ struct device *hwmon_dev;
++ wait_queue_head_t waitq;
++ bool data_ready;
++ u8 ctl_reg1;
++ int active;
++ int position;
++};
++static short MAGHAL[8][3][3] = {
++ { {0, 1, 0}, {-1, 0, 0}, {0, 0, 1} },
++ { {1, 0, 0}, {0, 1, 0}, {0, 0, 1} },
++ { {0, -1, 0}, {1, 0, 0}, {0, 0, 1} },
++ { {-1, 0, 0}, {0, -1, 0}, {0, 0, 1} },
++
++ { {0, 1, 0}, {1, 0, 0}, {0, 0, -1} },
++ { {1, 0, 0}, {0, -1, 0}, {0, 0, -1} },
++ { {0, -1, 0}, {-1, 0, 0}, {0, 0, -1} },
++ { {-1, 0, 0}, {0, 1, 0}, {0, 0, -1} },
++};
++
++static struct mag3110_data *mag3110_pdata;
++/*!
++ * This function do one mag3110 register read.
++ */
++static DEFINE_MUTEX(mag3110_lock);
++static int mag3110_adjust_position(short *x, short *y, short *z)
++{
++ short rawdata[3], data[3];
++ int i, j;
++ int position = mag3110_pdata->position;
++ if (position < 0 || position > 7)
++ position = 0;
++ rawdata[0] = *x;
++ rawdata[1] = *y;
++ rawdata[2] = *z;
++ for (i = 0; i < 3; i++) {
++ data[i] = 0;
++ for (j = 0; j < 3; j++)
++ data[i] += rawdata[j] * MAGHAL[position][i][j];
++ }
++ *x = data[0];
++ *y = data[1];
++ *z = data[2];
++ return 0;
++}
++
++static int mag3110_read_reg(struct i2c_client *client, u8 reg)
++{
++ return i2c_smbus_read_byte_data(client, reg);
++}
++
++/*!
++ * This function do one mag3110 register write.
++ */
++static int mag3110_write_reg(struct i2c_client *client, u8 reg, char value)
++{
++ int ret;
++
++ ret = i2c_smbus_write_byte_data(client, reg, value);
++ if (ret < 0)
++ dev_err(&client->dev, "i2c write failed\n");
++ return ret;
++}
++
++/*!
++ * This function do multiple mag3110 registers read.
++ */
++static int mag3110_read_block_data(struct i2c_client *client, u8 reg,
++ int count, u8 *addr)
++{
++ if (i2c_smbus_read_i2c_block_data(client, reg, count, addr) < count) {
++ dev_err(&client->dev, "i2c block read failed\n");
++ return -1;
++ }
++
++ return count;
++}
++
++/*
++ * Initialization function
++ */
++static int mag3110_init_client(struct i2c_client *client)
++{
++ int val, ret;
++
++ /* enable automatic resets */
++ val = 0x80;
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG2, val);
++
++ /* set default data rate to 10HZ */
++ val = mag3110_read_reg(client, MAG3110_CTRL_REG1);
++ val |= (0x0 << MAG3110_DR_MODE_OFFSET);
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, val);
++
++ return ret;
++}
++
++/***************************************************************
++*
++* read sensor data from mag3110
++*
++***************************************************************/
++static int mag3110_read_data(short *x, short *y, short *z)
++{
++ struct mag3110_data *data;
++ int retry = 3;
++ u8 tmp_data[MAG3110_XYZ_DATA_LEN];
++ int result;
++ if (!mag3110_pdata || mag3110_pdata->active == MAG_STANDBY)
++ return -EINVAL;
++
++ data = mag3110_pdata;
++#if MAG3110_IRQ_USED
++ if (!wait_event_interruptible_timeout
++ (data->waitq, data->data_ready != 0,
++ msecs_to_jiffies(INT_TIMEOUT))) {
++ dev_dbg(&data->client->dev, "interrupt not received\n");
++ return -ETIME;
++ }
++#else
++ do {
++ msleep(1);
++ result = i2c_smbus_read_byte_data(data->client,
++ MAG3110_DR_STATUS);
++ retry--;
++ } while (!(result & MAG3110_STATUS_ZYXDR) && retry > 0);
++ /* Clear data_ready flag after data is read out */
++ if (retry == 0)
++ return -EINVAL;
++#endif
++
++ data->data_ready = 0;
++
++ if (mag3110_read_block_data(data->client,
++ MAG3110_OUT_X_MSB, MAG3110_XYZ_DATA_LEN,
++ tmp_data) < 0)
++ return -1;
++
++ *x = ((tmp_data[0] << 8) & 0xff00) | tmp_data[1];
++ *y = ((tmp_data[2] << 8) & 0xff00) | tmp_data[3];
++ *z = ((tmp_data[4] << 8) & 0xff00) | tmp_data[5];
++
++ return 0;
++}
++
++static void report_abs(void)
++{
++ struct input_dev *idev;
++ short x, y, z;
++
++ mutex_lock(&mag3110_lock);
++ if (mag3110_read_data(&x, &y, &z) != 0)
++ goto out;
++ mag3110_adjust_position(&x, &y, &z);
++ idev = mag3110_pdata->poll_dev->input;
++ input_report_abs(idev, ABS_X, x);
++ input_report_abs(idev, ABS_Y, y);
++ input_report_abs(idev, ABS_Z, z);
++ input_sync(idev);
++out:
++ mutex_unlock(&mag3110_lock);
++}
++
++static void mag3110_dev_poll(struct input_polled_dev *dev)
++{
++ report_abs();
++}
++
++#if MAG3110_IRQ_USED
++static irqreturn_t mag3110_irq_handler(int irq, void *dev_id)
++{
++ mag3110_pdata->data_ready = 1;
++ wake_up_interruptible(&mag3110_pdata->waitq);
++
++ return IRQ_HANDLED;
++}
++#endif
++static ssize_t mag3110_enable_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client;
++ int val;
++ mutex_lock(&mag3110_lock);
++ client = mag3110_pdata->client;
++ val = mag3110_read_reg(client, MAG3110_CTRL_REG1) & MAG3110_AC_MASK;
++
++ mutex_unlock(&mag3110_lock);
++ return sprintf(buf, "%d\n", val);
++}
++
++static ssize_t mag3110_enable_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client;
++ int reg, ret;
++ long enable;
++ u8 tmp_data[MAG3110_XYZ_DATA_LEN];
++
++ ret = strict_strtol(buf, 10, &enable);
++ if (ret) {
++ dev_err(dev, "string to long error\n");
++ return ret;
++ }
++
++ mutex_lock(&mag3110_lock);
++ client = mag3110_pdata->client;
++ reg = mag3110_read_reg(client, MAG3110_CTRL_REG1);
++ if (enable && mag3110_pdata->active == MAG_STANDBY) {
++ reg |= MAG3110_AC_MASK;
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, reg);
++ if (!ret)
++ mag3110_pdata->active = MAG_ACTIVED;
++ } else if (!enable && mag3110_pdata->active == MAG_ACTIVED) {
++ reg &= ~MAG3110_AC_MASK;
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, reg);
++ if (!ret)
++ mag3110_pdata->active = MAG_STANDBY;
++ }
++
++ if (mag3110_pdata->active == MAG_ACTIVED) {
++ msleep(100);
++ /* Read out MSB data to clear interrupt flag automatically */
++ mag3110_read_block_data(client, MAG3110_OUT_X_MSB,
++ MAG3110_XYZ_DATA_LEN, tmp_data);
++ }
++ mutex_unlock(&mag3110_lock);
++ return count;
++}
++
++static DEVICE_ATTR(enable, S_IWUSR | S_IRUGO,
++ mag3110_enable_show, mag3110_enable_store);
++
++static ssize_t mag3110_dr_mode_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client;
++ int val;
++
++ client = mag3110_pdata->client;
++ val = (mag3110_read_reg(client, MAG3110_CTRL_REG1)
++ & MAG3110_DR_MODE_MASK) >> MAG3110_DR_MODE_OFFSET;
++
++ return sprintf(buf, "%d\n", val);
++}
++
++static ssize_t mag3110_dr_mode_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client;
++ int reg, ret;
++ unsigned long val;
++
++ /* This must be done when mag3110 is disabled */
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > 7))
++ return -EINVAL;
++
++ client = mag3110_pdata->client;
++ reg = mag3110_read_reg(client, MAG3110_CTRL_REG1) &
++ ~MAG3110_DR_MODE_MASK;
++ reg |= (val << MAG3110_DR_MODE_OFFSET);
++ /* MAG3110_CTRL_REG1 bit 5-7: data rate mode */
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, reg);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(dr_mode, S_IWUSR | S_IRUGO,
++ mag3110_dr_mode_show, mag3110_dr_mode_store);
++
++static ssize_t mag3110_position_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ int val;
++ mutex_lock(&mag3110_lock);
++ val = mag3110_pdata->position;
++ mutex_unlock(&mag3110_lock);
++ return sprintf(buf, "%d\n", val);
++}
++
++static ssize_t mag3110_position_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ long position;
++ int ret;
++ ret = strict_strtol(buf, 10, &position);
++ if (ret) {
++ dev_err(dev, "string to long error\n");
++ return ret;
++ }
++
++ mutex_lock(&mag3110_lock);
++ mag3110_pdata->position = (int)position;
++ mutex_unlock(&mag3110_lock);
++ return count;
++}
++
++static DEVICE_ATTR(position, S_IWUSR | S_IRUGO,
++ mag3110_position_show, mag3110_position_store);
++
++static struct attribute *mag3110_attributes[] = {
++ &dev_attr_enable.attr,
++ &dev_attr_dr_mode.attr,
++ &dev_attr_position.attr,
++ NULL
++};
++
++static const struct attribute_group mag3110_attr_group = {
++ .attrs = mag3110_attributes,
++};
++
++static int mag3110_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct i2c_adapter *adapter;
++ struct input_dev *idev;
++ struct mag3110_data *data;
++ int ret = 0;
++ struct regulator *vdd, *vdd_io;
++ u32 pos = 0;
++ struct device_node *of_node = client->dev.of_node;
++ vdd = NULL;
++ vdd_io = NULL;
++
++ vdd = devm_regulator_get(&client->dev, "vdd");
++ if (!IS_ERR(vdd)) {
++ ret = regulator_enable(vdd);
++ if (ret) {
++ dev_err(&client->dev, "vdd set voltage error\n");
++ return ret;
++ }
++ }
++
++ vdd_io = devm_regulator_get(&client->dev, "vddio");
++ if (!IS_ERR(vdd_io)) {
++ ret = regulator_enable(vdd_io);
++ if (ret) {
++ dev_err(&client->dev, "vddio set voltage error\n");
++ return ret;
++ }
++ }
++
++ adapter = to_i2c_adapter(client->dev.parent);
++ if (!i2c_check_functionality(adapter,
++ I2C_FUNC_SMBUS_BYTE |
++ I2C_FUNC_SMBUS_BYTE_DATA |
++ I2C_FUNC_SMBUS_I2C_BLOCK))
++ return -EIO;
++
++ dev_info(&client->dev, "check mag3110 chip ID\n");
++ ret = mag3110_read_reg(client, MAG3110_WHO_AM_I);
++
++ if (MAG3110_ID != ret) {
++ dev_err(&client->dev,
++ "read chip ID 0x%x is not equal to 0x%x!\n", ret,
++ MAG3110_ID);
++ return -EINVAL;
++ }
++ data = kzalloc(sizeof(struct mag3110_data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++ data->client = client;
++ i2c_set_clientdata(client, data);
++ /* Init queue */
++ init_waitqueue_head(&data->waitq);
++
++ data->hwmon_dev = hwmon_device_register(&client->dev);
++ if (IS_ERR(data->hwmon_dev)) {
++ dev_err(&client->dev, "hwmon register failed!\n");
++ ret = PTR_ERR(data->hwmon_dev);
++ goto error_rm_dev_sysfs;
++ }
++
++ /*input poll device register */
++ data->poll_dev = input_allocate_polled_device();
++ if (!data->poll_dev) {
++ dev_err(&client->dev, "alloc poll device failed!\n");
++ ret = -ENOMEM;
++ goto error_rm_hwmon_dev;
++ }
++ data->poll_dev->poll = mag3110_dev_poll;
++ data->poll_dev->poll_interval = POLL_INTERVAL;
++ data->poll_dev->poll_interval_max = POLL_INTERVAL_MAX;
++ idev = data->poll_dev->input;
++ idev->name = MAG3110_DRV_NAME;
++ idev->id.bustype = BUS_I2C;
++ idev->evbit[0] = BIT_MASK(EV_ABS);
++ input_set_abs_params(idev, ABS_X, -15000, 15000, 0, 0);
++ input_set_abs_params(idev, ABS_Y, -15000, 15000, 0, 0);
++ input_set_abs_params(idev, ABS_Z, -15000, 15000, 0, 0);
++ ret = input_register_polled_device(data->poll_dev);
++ if (ret) {
++ dev_err(&client->dev, "register poll device failed!\n");
++ goto error_free_poll_dev;
++ }
++
++ /*create device group in sysfs as user interface */
++ ret = sysfs_create_group(&idev->dev.kobj, &mag3110_attr_group);
++ if (ret) {
++ dev_err(&client->dev, "create device file failed!\n");
++ ret = -EINVAL;
++ goto error_rm_poll_dev;
++ }
++ /* set irq type to edge rising */
++#if MAG3110_IRQ_USED
++ ret = request_irq(client->irq, mag3110_irq_handler,
++ IRQF_TRIGGER_RISING, client->dev.driver->name, idev);
++ if (ret < 0) {
++ dev_err(&client->dev, "failed to register irq %d!\n",
++ client->irq);
++ goto error_rm_dev_sysfs;
++ }
++#endif
++ /* Initialize mag3110 chip */
++ mag3110_init_client(client);
++ mag3110_pdata = data;
++ mag3110_pdata->active = MAG_STANDBY;
++ ret = of_property_read_u32(of_node, "position", &pos);
++ if (ret)
++ pos = DEFAULT_POSITION;
++ mag3110_pdata->position = (int)pos;
++ dev_info(&client->dev, "mag3110 is probed\n");
++ return 0;
++error_rm_dev_sysfs:
++ sysfs_remove_group(&client->dev.kobj, &mag3110_attr_group);
++error_rm_poll_dev:
++ input_unregister_polled_device(data->poll_dev);
++error_free_poll_dev:
++ input_free_polled_device(data->poll_dev);
++error_rm_hwmon_dev:
++ hwmon_device_unregister(data->hwmon_dev);
++
++ kfree(data);
++ mag3110_pdata = NULL;
++
++ return ret;
++}
++
++static int mag3110_remove(struct i2c_client *client)
++{
++ struct mag3110_data *data;
++ int ret;
++
++ data = i2c_get_clientdata(client);
++
++ data->ctl_reg1 = mag3110_read_reg(client, MAG3110_CTRL_REG1);
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1,
++ data->ctl_reg1 & ~MAG3110_AC_MASK);
++
++ free_irq(client->irq, data);
++ input_unregister_polled_device(data->poll_dev);
++ input_free_polled_device(data->poll_dev);
++ hwmon_device_unregister(data->hwmon_dev);
++ sysfs_remove_group(&client->dev.kobj, &mag3110_attr_group);
++ kfree(data);
++ mag3110_pdata = NULL;
++
++ return ret;
++}
++
++#ifdef CONFIG_PM
++static int mag3110_suspend(struct i2c_client *client, pm_message_t mesg)
++{
++ int ret = 0;
++ struct mag3110_data *data = i2c_get_clientdata(client);
++ if (data->active == MAG_ACTIVED) {
++ data->ctl_reg1 = mag3110_read_reg(client, MAG3110_CTRL_REG1);
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1,
++ data->ctl_reg1 & ~MAG3110_AC_MASK);
++ }
++ return ret;
++}
++
++static int mag3110_resume(struct i2c_client *client)
++{
++ int ret = 0;
++ u8 tmp_data[MAG3110_XYZ_DATA_LEN];
++ struct mag3110_data *data = i2c_get_clientdata(client);
++ if (data->active == MAG_ACTIVED) {
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1,
++ data->ctl_reg1);
++
++ if (data->ctl_reg1 & MAG3110_AC_MASK) {
++ /* Read out MSB data to clear interrupt
++ flag automatically */
++ mag3110_read_block_data(client, MAG3110_OUT_X_MSB,
++ MAG3110_XYZ_DATA_LEN, tmp_data);
++ }
++ }
++ return ret;
++}
++
++#else
++#define mag3110_suspend NULL
++#define mag3110_resume NULL
++#endif /* CONFIG_PM */
++
++static const struct i2c_device_id mag3110_id[] = {
++ {MAG3110_DRV_NAME, 0},
++ {}
++};
++
++MODULE_DEVICE_TABLE(i2c, mag3110_id);
++static struct i2c_driver mag3110_driver = {
++ .driver = {.name = MAG3110_DRV_NAME,
++ .owner = THIS_MODULE,},
++ .suspend = mag3110_suspend,
++ .resume = mag3110_resume,
++ .probe = mag3110_probe,
++ .remove = mag3110_remove,
++ .id_table = mag3110_id,
++};
++
++static int __init mag3110_init(void)
++{
++ return i2c_add_driver(&mag3110_driver);
++}
++
++static void __exit mag3110_exit(void)
++{
++ i2c_del_driver(&mag3110_driver);
++}
++
++module_init(mag3110_init);
++module_exit(mag3110_exit);
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Freescale mag3110 3-axis magnetometer driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/hwmon/Makefile linux-linaro-stable-mx6/drivers/hwmon/Makefile
+--- linux-3.10.30.orig/drivers/hwmon/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/hwmon/Makefile 2014-05-15 20:33:54.425988123 +0200
+@@ -101,6 +101,7 @@
+ obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
+ obj-$(CONFIG_SENSORS_MAX1619) += max1619.o
+ obj-$(CONFIG_SENSORS_MAX1668) += max1668.o
++obj-$(CONFIG_SENSORS_MAX17135) += max17135-hwmon.o
+ obj-$(CONFIG_SENSORS_MAX197) += max197.o
+ obj-$(CONFIG_SENSORS_MAX6639) += max6639.o
+ obj-$(CONFIG_SENSORS_MAX6642) += max6642.o
+@@ -140,6 +141,8 @@
+ obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o
+ obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o
+ obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o
++obj-$(CONFIG_SENSORS_MAG3110) += mag3110.o
++obj-$(CONFIG_MXC_MMA8451) += mxc_mma8451.o
+
+ obj-$(CONFIG_PMBUS) += pmbus/
+
+diff -Nur linux-3.10.30.orig/drivers/hwmon/max17135-hwmon.c linux-linaro-stable-mx6/drivers/hwmon/max17135-hwmon.c
+--- linux-3.10.30.orig/drivers/hwmon/max17135-hwmon.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/hwmon/max17135-hwmon.c 2014-05-15 20:33:54.505988699 +0200
+@@ -0,0 +1,176 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * max17135.c
++ *
++ * Based on the MAX1619 driver.
++ * Copyright (C) 2003-2004 Alexey Fisher <fishor@mail.ru>
++ * Jean Delvare <khali@linux-fr.org>
++ *
++ * The MAX17135 is a sensor chip made by Maxim.
++ * It reports up to two temperatures (its own plus up to
++ * one external one).
++ */
++
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/jiffies.h>
++#include <linux/hwmon.h>
++#include <linux/hwmon-sysfs.h>
++#include <linux/err.h>
++#include <linux/sysfs.h>
++#include <linux/platform_device.h>
++#include <linux/mfd/max17135.h>
++
++/*
++ * Conversions
++ */
++static int temp_from_reg(int val)
++{
++ return val >> 8;
++}
++
++/*
++ * Functions declaration
++ */
++static int max17135_sensor_probe(struct platform_device *pdev);
++static int max17135_sensor_remove(struct platform_device *pdev);
++
++static const struct platform_device_id max17135_sns_id[] = {
++ { "max17135-sns", 0},
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(platform, max17135_sns_id);
++
++/*
++ * Driver data (common to all clients)
++ */
++static struct platform_driver max17135_sensor_driver = {
++ .probe = max17135_sensor_probe,
++ .remove = max17135_sensor_remove,
++ .id_table = max17135_sns_id,
++ .driver = {
++ .name = "max17135_sensor",
++ },
++};
++
++/*
++ * Client data (each client gets its own)
++ */
++struct max17135_data {
++ struct device *hwmon_dev;
++};
++
++/*
++ * Sysfs stuff
++ */
++static ssize_t show_temp_input1(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ unsigned int reg_val;
++ max17135_reg_read(REG_MAX17135_INT_TEMP, &reg_val);
++ return snprintf(buf, PAGE_SIZE, "%d\n", temp_from_reg(reg_val));
++}
++
++static ssize_t show_temp_input2(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ unsigned int reg_val;
++ max17135_reg_read(REG_MAX17135_EXT_TEMP, &reg_val);
++ return snprintf(buf, PAGE_SIZE, "%d\n", temp_from_reg(reg_val));
++}
++
++static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp_input1, NULL);
++static DEVICE_ATTR(temp2_input, S_IRUGO, show_temp_input2, NULL);
++
++static struct attribute *max17135_attributes[] = {
++ &dev_attr_temp1_input.attr,
++ &dev_attr_temp2_input.attr,
++ NULL
++};
++
++static const struct attribute_group max17135_group = {
++ .attrs = max17135_attributes,
++};
++
++/*
++ * Real code
++ */
++static int max17135_sensor_probe(struct platform_device *pdev)
++{
++ struct max17135_data *data;
++ int err;
++
++ data = kzalloc(sizeof(struct max17135_data), GFP_KERNEL);
++ if (!data) {
++ err = -ENOMEM;
++ goto exit;
++ }
++
++ /* Register sysfs hooks */
++ err = sysfs_create_group(&pdev->dev.kobj, &max17135_group);
++ if (err)
++ goto exit_free;
++
++ data->hwmon_dev = hwmon_device_register(&pdev->dev);
++ if (IS_ERR(data->hwmon_dev)) {
++ err = PTR_ERR(data->hwmon_dev);
++ goto exit_remove_files;
++ }
++
++ platform_set_drvdata(pdev, data);
++
++ return 0;
++
++exit_remove_files:
++ sysfs_remove_group(&pdev->dev.kobj, &max17135_group);
++exit_free:
++ kfree(data);
++exit:
++ return err;
++}
++
++static int max17135_sensor_remove(struct platform_device *pdev)
++{
++ struct max17135_data *data = platform_get_drvdata(pdev);
++
++ hwmon_device_unregister(data->hwmon_dev);
++ sysfs_remove_group(&pdev->dev.kobj, &max17135_group);
++
++ kfree(data);
++ return 0;
++}
++
++static int __init sensors_max17135_init(void)
++{
++ return platform_driver_register(&max17135_sensor_driver);
++}
++module_init(sensors_max17135_init);
++
++static void __exit sensors_max17135_exit(void)
++{
++ platform_driver_unregister(&max17135_sensor_driver);
++}
++module_exit(sensors_max17135_exit);
++
++MODULE_DESCRIPTION("MAX17135 sensor driver");
++MODULE_LICENSE("GPL");
++
+diff -Nur linux-3.10.30.orig/drivers/hwmon/mxc_mma8451.c linux-linaro-stable-mx6/drivers/hwmon/mxc_mma8451.c
+--- linux-3.10.30.orig/drivers/hwmon/mxc_mma8451.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/hwmon/mxc_mma8451.c 2014-05-15 20:33:54.509988729 +0200
+@@ -0,0 +1,538 @@
++/*
++ * mma8451.c - Linux kernel modules for 3-Axis Orientation/Motion
++ * Detection Sensor
++ *
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/pm.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/hwmon-sysfs.h>
++#include <linux/err.h>
++#include <linux/hwmon.h>
++#include <linux/input-polldev.h>
++#include <linux/of.h>
++#include <linux/regulator/consumer.h>
++
++#define MMA8451_I2C_ADDR 0x1C
++#define MMA8451_ID 0x1A
++#define MMA8452_ID 0x2A
++#define MMA8453_ID 0x3A
++
++#define POLL_INTERVAL_MIN 1
++#define POLL_INTERVAL_MAX 500
++#define POLL_INTERVAL 100 /* msecs */
++#define INPUT_FUZZ 32
++#define INPUT_FLAT 32
++#define MODE_CHANGE_DELAY_MS 100
++
++#define MMA8451_STATUS_ZYXDR 0x08
++#define MMA8451_BUF_SIZE 7
++#define DEFAULT_POSITION 0
++
++/* register enum for mma8451 registers */
++enum {
++ MMA8451_STATUS = 0x00,
++ MMA8451_OUT_X_MSB,
++ MMA8451_OUT_X_LSB,
++ MMA8451_OUT_Y_MSB,
++ MMA8451_OUT_Y_LSB,
++ MMA8451_OUT_Z_MSB,
++ MMA8451_OUT_Z_LSB,
++
++ MMA8451_F_SETUP = 0x09,
++ MMA8451_TRIG_CFG,
++ MMA8451_SYSMOD,
++ MMA8451_INT_SOURCE,
++ MMA8451_WHO_AM_I,
++ MMA8451_XYZ_DATA_CFG,
++ MMA8451_HP_FILTER_CUTOFF,
++
++ MMA8451_PL_STATUS,
++ MMA8451_PL_CFG,
++ MMA8451_PL_COUNT,
++ MMA8451_PL_BF_ZCOMP,
++ MMA8451_P_L_THS_REG,
++
++ MMA8451_FF_MT_CFG,
++ MMA8451_FF_MT_SRC,
++ MMA8451_FF_MT_THS,
++ MMA8451_FF_MT_COUNT,
++
++ MMA8451_TRANSIENT_CFG = 0x1D,
++ MMA8451_TRANSIENT_SRC,
++ MMA8451_TRANSIENT_THS,
++ MMA8451_TRANSIENT_COUNT,
++
++ MMA8451_PULSE_CFG,
++ MMA8451_PULSE_SRC,
++ MMA8451_PULSE_THSX,
++ MMA8451_PULSE_THSY,
++ MMA8451_PULSE_THSZ,
++ MMA8451_PULSE_TMLT,
++ MMA8451_PULSE_LTCY,
++ MMA8451_PULSE_WIND,
++
++ MMA8451_ASLP_COUNT,
++ MMA8451_CTRL_REG1,
++ MMA8451_CTRL_REG2,
++ MMA8451_CTRL_REG3,
++ MMA8451_CTRL_REG4,
++ MMA8451_CTRL_REG5,
++
++ MMA8451_OFF_X,
++ MMA8451_OFF_Y,
++ MMA8451_OFF_Z,
++
++ MMA8451_REG_END,
++};
++
++/* The sensitivity is represented in counts/g. In 2g mode the
++sensitivity is 1024 counts/g. In 4g mode the sensitivity is 512
++counts/g and in 8g mode the sensitivity is 256 counts/g.
++ */
++enum {
++ MODE_2G = 0,
++ MODE_4G,
++ MODE_8G,
++};
++
++enum {
++ MMA_STANDBY = 0,
++ MMA_ACTIVED,
++};
++
++/* mma8451 status */
++struct mma8451_status {
++ u8 mode;
++ u8 ctl_reg1;
++ int active;
++ int position;
++};
++
++static struct mma8451_status mma_status;
++static struct input_polled_dev *mma8451_idev;
++static struct device *hwmon_dev;
++static struct i2c_client *mma8451_i2c_client;
++
++static int senstive_mode = MODE_2G;
++static int ACCHAL[8][3][3] = {
++ { {0, -1, 0}, {1, 0, 0}, {0, 0, 1} },
++ { {-1, 0, 0}, {0, -1, 0}, {0, 0, 1} },
++ { {0, 1, 0}, {-1, 0, 0}, {0, 0, 1} },
++ { {1, 0, 0}, {0, 1, 0}, {0, 0, 1} },
++
++ { {0, -1, 0}, {-1, 0, 0}, {0, 0, -1} },
++ { {-1, 0, 0}, {0, 1, 0}, {0, 0, -1} },
++ { {0, 1, 0}, {1, 0, 0}, {0, 0, -1} },
++ { {1, 0, 0}, {0, -1, 0}, {0, 0, -1} },
++};
++
++static DEFINE_MUTEX(mma8451_lock);
++static int mma8451_adjust_position(short *x, short *y, short *z)
++{
++ short rawdata[3], data[3];
++ int i, j;
++ int position = mma_status.position;
++ if (position < 0 || position > 7)
++ position = 0;
++ rawdata[0] = *x;
++ rawdata[1] = *y;
++ rawdata[2] = *z;
++ for (i = 0; i < 3; i++) {
++ data[i] = 0;
++ for (j = 0; j < 3; j++)
++ data[i] += rawdata[j] * ACCHAL[position][i][j];
++ }
++ *x = data[0];
++ *y = data[1];
++ *z = data[2];
++ return 0;
++}
++
++static int mma8451_change_mode(struct i2c_client *client, int mode)
++{
++ int result;
++
++ mma_status.ctl_reg1 = 0;
++ result = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, 0);
++ if (result < 0)
++ goto out;
++
++ mma_status.mode = mode;
++ result = i2c_smbus_write_byte_data(client, MMA8451_XYZ_DATA_CFG,
++ mma_status.mode);
++ if (result < 0)
++ goto out;
++ mma_status.active = MMA_STANDBY;
++ mdelay(MODE_CHANGE_DELAY_MS);
++
++ return 0;
++out:
++ dev_err(&client->dev, "error when init mma8451:(%d)", result);
++ return result;
++}
++
++static int mma8451_read_data(short *x, short *y, short *z)
++{
++ u8 tmp_data[MMA8451_BUF_SIZE];
++ int ret;
++
++ ret = i2c_smbus_read_i2c_block_data(mma8451_i2c_client,
++ MMA8451_OUT_X_MSB, 7, tmp_data);
++ if (ret < MMA8451_BUF_SIZE) {
++ dev_err(&mma8451_i2c_client->dev, "i2c block read failed\n");
++ return -EIO;
++ }
++
++ *x = ((tmp_data[0] << 8) & 0xff00) | tmp_data[1];
++ *y = ((tmp_data[2] << 8) & 0xff00) | tmp_data[3];
++ *z = ((tmp_data[4] << 8) & 0xff00) | tmp_data[5];
++ return 0;
++}
++
++static void report_abs(void)
++{
++ short x, y, z;
++ int result;
++ int retry = 3;
++
++ mutex_lock(&mma8451_lock);
++ if (mma_status.active == MMA_STANDBY)
++ goto out;
++ /* wait for the data ready */
++ do {
++ result = i2c_smbus_read_byte_data(mma8451_i2c_client,
++ MMA8451_STATUS);
++ retry--;
++ msleep(1);
++ } while (!(result & MMA8451_STATUS_ZYXDR) && retry > 0);
++ if (retry == 0)
++ goto out;
++ if (mma8451_read_data(&x, &y, &z) != 0)
++ goto out;
++ mma8451_adjust_position(&x, &y, &z);
++ input_report_abs(mma8451_idev->input, ABS_X, x);
++ input_report_abs(mma8451_idev->input, ABS_Y, y);
++ input_report_abs(mma8451_idev->input, ABS_Z, z);
++ input_sync(mma8451_idev->input);
++out:
++ mutex_unlock(&mma8451_lock);
++}
++
++static void mma8451_dev_poll(struct input_polled_dev *dev)
++{
++ report_abs();
++}
++
++static ssize_t mma8451_enable_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client;
++ u8 val;
++ int enable;
++
++ mutex_lock(&mma8451_lock);
++ client = mma8451_i2c_client;
++ val = i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1);
++ if ((val & 0x01) && mma_status.active == MMA_ACTIVED)
++ enable = 1;
++ else
++ enable = 0;
++ mutex_unlock(&mma8451_lock);
++ return sprintf(buf, "%d\n", enable);
++}
++
++static ssize_t mma8451_enable_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client;
++ int ret;
++ unsigned long enable;
++ u8 val = 0;
++
++ ret = strict_strtoul(buf, 10, &enable);
++ if (ret) {
++ dev_err(dev, "string transform error\n");
++ return ret;
++ }
++
++ mutex_lock(&mma8451_lock);
++ client = mma8451_i2c_client;
++ enable = (enable > 0) ? 1 : 0;
++ if (enable && mma_status.active == MMA_STANDBY) {
++ val = i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1);
++ ret =
++ i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1,
++ val | 0x01);
++ if (!ret)
++ mma_status.active = MMA_ACTIVED;
++
++ } else if (enable == 0 && mma_status.active == MMA_ACTIVED) {
++ val = i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1);
++ ret =
++ i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1,
++ val & 0xFE);
++ if (!ret)
++ mma_status.active = MMA_STANDBY;
++
++ }
++ mutex_unlock(&mma8451_lock);
++ return count;
++}
++
++static ssize_t mma8451_position_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ int position = 0;
++ mutex_lock(&mma8451_lock);
++ position = mma_status.position;
++ mutex_unlock(&mma8451_lock);
++ return sprintf(buf, "%d\n", position);
++}
++
++static ssize_t mma8451_position_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ unsigned long position;
++ int ret;
++ ret = strict_strtoul(buf, 10, &position);
++ if (ret) {
++ dev_err(dev, "string transform error\n");
++ return ret;
++ }
++
++ mutex_lock(&mma8451_lock);
++ mma_status.position = (int)position;
++ mutex_unlock(&mma8451_lock);
++ return count;
++}
++
++static DEVICE_ATTR(enable, S_IWUSR | S_IRUGO,
++ mma8451_enable_show, mma8451_enable_store);
++static DEVICE_ATTR(position, S_IWUSR | S_IRUGO,
++ mma8451_position_show, mma8451_position_store);
++
++static struct attribute *mma8451_attributes[] = {
++ &dev_attr_enable.attr,
++ &dev_attr_position.attr,
++ NULL
++};
++
++static const struct attribute_group mma8451_attr_group = {
++ .attrs = mma8451_attributes,
++};
++
++static int mma8451_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ int result, client_id;
++ struct input_dev *idev;
++ struct i2c_adapter *adapter;
++ u32 pos;
++ struct device_node *of_node = client->dev.of_node;
++ struct regulator *vdd, *vdd_io;
++
++ mma8451_i2c_client = client;
++
++ vdd = devm_regulator_get(&client->dev, "vdd");
++ if (!IS_ERR(vdd)) {
++ result = regulator_enable(vdd);
++ if (result) {
++ dev_err(&client->dev, "vdd set voltage error\n");
++ return result;
++ }
++ }
++
++ vdd_io = devm_regulator_get(&client->dev, "vddio");
++ if (!IS_ERR(vdd_io)) {
++ result = regulator_enable(vdd_io);
++ if (result) {
++ dev_err(&client->dev, "vddio set voltage error\n");
++ return result;
++ }
++ }
++
++ adapter = to_i2c_adapter(client->dev.parent);
++ result = i2c_check_functionality(adapter,
++ I2C_FUNC_SMBUS_BYTE |
++ I2C_FUNC_SMBUS_BYTE_DATA);
++ if (!result)
++ goto err_out;
++
++ client_id = i2c_smbus_read_byte_data(client, MMA8451_WHO_AM_I);
++ if (client_id != MMA8451_ID && client_id != MMA8452_ID
++ && client_id != MMA8453_ID) {
++ dev_err(&client->dev,
++ "read chip ID 0x%x is not equal to 0x%x or 0x%x!\n",
++ result, MMA8451_ID, MMA8452_ID);
++ result = -EINVAL;
++ goto err_out;
++ }
++
++ /* Initialize the MMA8451 chip */
++ result = mma8451_change_mode(client, senstive_mode);
++ if (result) {
++ dev_err(&client->dev,
++ "error when init mma8451 chip:(%d)\n", result);
++ goto err_out;
++ }
++
++ hwmon_dev = hwmon_device_register(&client->dev);
++ if (!hwmon_dev) {
++ result = -ENOMEM;
++ dev_err(&client->dev, "error when register hwmon device\n");
++ goto err_out;
++ }
++
++ mma8451_idev = input_allocate_polled_device();
++ if (!mma8451_idev) {
++ result = -ENOMEM;
++ dev_err(&client->dev, "alloc poll device failed!\n");
++ goto err_alloc_poll_device;
++ }
++ mma8451_idev->poll = mma8451_dev_poll;
++ mma8451_idev->poll_interval = POLL_INTERVAL;
++ mma8451_idev->poll_interval_min = POLL_INTERVAL_MIN;
++ mma8451_idev->poll_interval_max = POLL_INTERVAL_MAX;
++ idev = mma8451_idev->input;
++ idev->name = "mma845x";
++ idev->id.bustype = BUS_I2C;
++ idev->evbit[0] = BIT_MASK(EV_ABS);
++
++ input_set_abs_params(idev, ABS_X, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++ input_set_abs_params(idev, ABS_Y, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++ input_set_abs_params(idev, ABS_Z, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++
++ result = input_register_polled_device(mma8451_idev);
++ if (result) {
++ dev_err(&client->dev, "register poll device failed!\n");
++ goto err_register_polled_device;
++ }
++ result = sysfs_create_group(&idev->dev.kobj, &mma8451_attr_group);
++ if (result) {
++ dev_err(&client->dev, "create device file failed!\n");
++ result = -EINVAL;
++ goto err_register_polled_device;
++ }
++
++ result = of_property_read_u32(of_node, "position", &pos);
++ if (result)
++ pos = DEFAULT_POSITION;
++ mma_status.position = (int)pos;
++
++ return 0;
++err_register_polled_device:
++ input_free_polled_device(mma8451_idev);
++err_alloc_poll_device:
++ hwmon_device_unregister(&client->dev);
++err_out:
++ return result;
++}
++
++static int mma8451_stop_chip(struct i2c_client *client)
++{
++ int ret = 0;
++ if (mma_status.active == MMA_ACTIVED) {
++ mma_status.ctl_reg1 = i2c_smbus_read_byte_data(client,
++ MMA8451_CTRL_REG1);
++ ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1,
++ mma_status.ctl_reg1 & 0xFE);
++ }
++ return ret;
++}
++
++static int mma8451_remove(struct i2c_client *client)
++{
++ int ret;
++ ret = mma8451_stop_chip(client);
++ hwmon_device_unregister(hwmon_dev);
++
++ return ret;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int mma8451_suspend(struct device *dev)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++
++ return mma8451_stop_chip(client);
++}
++
++static int mma8451_resume(struct device *dev)
++{
++ int ret = 0;
++ struct i2c_client *client = to_i2c_client(dev);
++ if (mma_status.active == MMA_ACTIVED)
++ ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1,
++ mma_status.ctl_reg1);
++ return ret;
++
++}
++#endif
++
++static const struct i2c_device_id mma8451_id[] = {
++ {"mma8451", 0},
++};
++
++MODULE_DEVICE_TABLE(i2c, mma8451_id);
++
++static SIMPLE_DEV_PM_OPS(mma8451_pm_ops, mma8451_suspend, mma8451_resume);
++static struct i2c_driver mma8451_driver = {
++ .driver = {
++ .name = "mma8451",
++ .owner = THIS_MODULE,
++ .pm = &mma8451_pm_ops,
++ },
++ .probe = mma8451_probe,
++ .remove = mma8451_remove,
++ .id_table = mma8451_id,
++};
++
++static int __init mma8451_init(void)
++{
++ /* register driver */
++ int res;
++
++ res = i2c_add_driver(&mma8451_driver);
++ if (res < 0) {
++ printk(KERN_INFO "add mma8451 i2c driver failed\n");
++ return -ENODEV;
++ }
++ return res;
++}
++
++static void __exit mma8451_exit(void)
++{
++ i2c_del_driver(&mma8451_driver);
++}
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MMA8451 3-Axis Orientation/Motion Detection Sensor driver");
++MODULE_LICENSE("GPL");
++
++module_init(mma8451_init);
++module_exit(mma8451_exit);
+diff -Nur linux-3.10.30.orig/drivers/i2c/busses/i2c-davinci.c linux-linaro-stable-mx6/drivers/i2c/busses/i2c-davinci.c
+--- linux-3.10.30.orig/drivers/i2c/busses/i2c-davinci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/i2c/busses/i2c-davinci.c 2014-05-15 20:33:54.569989161 +0200
+@@ -646,13 +646,6 @@
+ struct resource *mem, *irq;
+ int r;
+
+- /* NOTE: driver uses the static register mapping */
+- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!mem) {
+- dev_err(&pdev->dev, "no mem resource?\n");
+- return -ENODEV;
+- }
+-
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!irq) {
+ dev_err(&pdev->dev, "no irq resource?\n");
+@@ -697,6 +690,7 @@
+ return -ENODEV;
+ clk_prepare_enable(dev->clk);
+
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dev->base = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(dev->base)) {
+ r = PTR_ERR(dev->base);
+diff -Nur linux-3.10.30.orig/drivers/i2c/busses/i2c-designware-platdrv.c linux-linaro-stable-mx6/drivers/i2c/busses/i2c-designware-platdrv.c
+--- linux-3.10.30.orig/drivers/i2c/busses/i2c-designware-platdrv.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/i2c/busses/i2c-designware-platdrv.c 2014-05-15 20:33:54.569989161 +0200
+@@ -87,13 +87,6 @@
+ struct resource *mem;
+ int irq, r;
+
+- /* NOTE: driver uses the static register mapping */
+- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!mem) {
+- dev_err(&pdev->dev, "no mem resource?\n");
+- return -EINVAL;
+- }
+-
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "no irq resource?\n");
+@@ -104,6 +97,7 @@
+ if (!dev)
+ return -ENOMEM;
+
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dev->base = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(dev->base))
+ return PTR_ERR(dev->base);
+diff -Nur linux-3.10.30.orig/drivers/i2c/busses/i2c-imx.c linux-linaro-stable-mx6/drivers/i2c/busses/i2c-imx.c
+--- linux-3.10.30.orig/drivers/i2c/busses/i2c-imx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/i2c/busses/i2c-imx.c 2014-05-15 20:33:54.581989248 +0200
+@@ -51,7 +51,6 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/of_i2c.h>
+-#include <linux/pinctrl/consumer.h>
+ #include <linux/platform_data/i2c-imx.h>
+
+ /** Defines ********************************************************************
+@@ -97,7 +96,7 @@
+ * Duplicated divider values removed from list
+ */
+
+-static u16 __initdata i2c_clk_div[50][2] = {
++static u16 i2c_clk_div[50][2] = {
+ { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
+ { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
+ { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
+@@ -128,6 +127,9 @@
+ int stopped;
+ unsigned int ifdr; /* IMX_I2C_IFDR */
+ enum imx_i2c_type devtype;
++
++ unsigned int cur_clk;
++ unsigned int bitrate;
+ };
+
+ static struct platform_device_id imx_i2c_devtype[] = {
+@@ -148,6 +150,7 @@
+ { .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], },
+ { /* sentinel */ }
+ };
++MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
+
+ static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
+ {
+@@ -205,6 +208,49 @@
+ return 0;
+ }
+
++static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
++{
++ unsigned int i2c_clk_rate;
++ unsigned int div;
++ int i;
++
++ /* Divider value calculation */
++ i2c_clk_rate = clk_get_rate(i2c_imx->clk);
++ if (i2c_imx->cur_clk == i2c_clk_rate)
++ return;
++ else
++ i2c_imx->cur_clk = i2c_clk_rate;
++
++ div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
++ if (div < i2c_clk_div[0][0])
++ i = 0;
++ else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
++ i = ARRAY_SIZE(i2c_clk_div) - 1;
++ else
++ for (i = 0; i2c_clk_div[i][0] < div; i++)
++ ;
++
++ /* Store divider value */
++ i2c_imx->ifdr = i2c_clk_div[i][1];
++
++ /*
++ * There dummy delay is calculated.
++ * It should be about one I2C clock period long.
++ * This delay is used in I2C bus disable function
++ * to fix chip hardware bug.
++ */
++ i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
++ + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
++
++ /* dev_dbg() can't be used, because adapter is not yet registered */
++#ifdef CONFIG_I2C_DEBUG_BUS
++ dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
++ __func__, i2c_clk_rate, div);
++ dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
++ __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
++#endif
++}
++
+ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
+ {
+ unsigned int temp = 0;
+@@ -212,6 +258,7 @@
+
+ dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
+
++ i2c_imx_set_clk(i2c_imx);
+ clk_prepare_enable(i2c_imx->clk);
+ writeb(i2c_imx->ifdr, i2c_imx->base + IMX_I2C_IFDR);
+ /* Enable I2C controller */
+@@ -264,44 +311,6 @@
+ clk_disable_unprepare(i2c_imx->clk);
+ }
+
+-static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
+- unsigned int rate)
+-{
+- unsigned int i2c_clk_rate;
+- unsigned int div;
+- int i;
+-
+- /* Divider value calculation */
+- i2c_clk_rate = clk_get_rate(i2c_imx->clk);
+- div = (i2c_clk_rate + rate - 1) / rate;
+- if (div < i2c_clk_div[0][0])
+- i = 0;
+- else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
+- i = ARRAY_SIZE(i2c_clk_div) - 1;
+- else
+- for (i = 0; i2c_clk_div[i][0] < div; i++);
+-
+- /* Store divider value */
+- i2c_imx->ifdr = i2c_clk_div[i][1];
+-
+- /*
+- * There dummy delay is calculated.
+- * It should be about one I2C clock period long.
+- * This delay is used in I2C bus disable function
+- * to fix chip hardware bug.
+- */
+- i2c_imx->disable_delay = (500000U * i2c_clk_div[i][0]
+- + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
+-
+- /* dev_dbg() can't be used, because adapter is not yet registered */
+-#ifdef CONFIG_I2C_DEBUG_BUS
+- dev_dbg(&i2c_imx->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
+- __func__, i2c_clk_rate, div);
+- dev_dbg(&i2c_imx->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
+- __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
+-#endif
+-}
+-
+ static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
+ {
+ struct imx_i2c_struct *i2c_imx = dev_id;
+@@ -493,24 +502,18 @@
+ struct imx_i2c_struct *i2c_imx;
+ struct resource *res;
+ struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
+- struct pinctrl *pinctrl;
+ void __iomem *base;
+ int irq, ret;
+- u32 bitrate;
+
+ dev_dbg(&pdev->dev, "<%s>\n", __func__);
+
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!res) {
+- dev_err(&pdev->dev, "can't get device resources\n");
+- return -ENOENT;
+- }
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "can't get irq number\n");
+ return -ENOENT;
+ }
+
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+@@ -535,12 +538,6 @@
+ i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
+ i2c_imx->base = base;
+
+- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+- if (IS_ERR(pinctrl)) {
+- dev_err(&pdev->dev, "can't get/select pinctrl\n");
+- return PTR_ERR(pinctrl);
+- }
+-
+ /* Get I2C clock */
+ i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(i2c_imx->clk)) {
+@@ -548,6 +545,11 @@
+ return PTR_ERR(i2c_imx->clk);
+ }
+
++ ret = clk_prepare_enable(i2c_imx->clk);
++ if (ret) {
++ dev_err(&pdev->dev, "can't enable I2C clock\n");
++ return ret;
++ }
+ /* Request IRQ */
+ ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
+ pdev->name, i2c_imx);
+@@ -563,12 +565,12 @@
+ i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
+
+ /* Set up clock divider */
+- bitrate = IMX_I2C_BIT_RATE;
++ i2c_imx->bitrate = IMX_I2C_BIT_RATE;
+ ret = of_property_read_u32(pdev->dev.of_node,
+- "clock-frequency", &bitrate);
++ "clock-frequency", &i2c_imx->bitrate);
+ if (ret < 0 && pdata && pdata->bitrate)
+- bitrate = pdata->bitrate;
+- i2c_imx_set_clk(i2c_imx, bitrate);
++ i2c_imx->bitrate = pdata->bitrate;
++ i2c_imx_set_clk(i2c_imx);
+
+ /* Set up chip registers to defaults */
+ writeb(0, i2c_imx->base + IMX_I2C_I2CR);
+@@ -585,6 +587,7 @@
+
+ /* Set up platform driver data */
+ platform_set_drvdata(pdev, i2c_imx);
++ clk_disable_unprepare(i2c_imx->clk);
+
+ dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
+ dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
+diff -Nur linux-3.10.30.orig/drivers/i2c/busses/i2c-omap.c linux-linaro-stable-mx6/drivers/i2c/busses/i2c-omap.c
+--- linux-3.10.30.orig/drivers/i2c/busses/i2c-omap.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/i2c/busses/i2c-omap.c 2014-05-15 20:33:54.581989248 +0200
+@@ -1087,13 +1087,6 @@
+ u32 rev;
+ u16 minor, major, scheme;
+
+- /* NOTE: driver uses the static register mapping */
+- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!mem) {
+- dev_err(&pdev->dev, "no mem resource?\n");
+- return -ENODEV;
+- }
+-
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "no irq resource?\n");
+@@ -1106,6 +1099,7 @@
+ return -ENOMEM;
+ }
+
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ dev->base = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(dev->base))
+ return PTR_ERR(dev->base);
+diff -Nur linux-3.10.30.orig/drivers/i2c/busses/i2c-rcar.c linux-linaro-stable-mx6/drivers/i2c/busses/i2c-rcar.c
+--- linux-3.10.30.orig/drivers/i2c/busses/i2c-rcar.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/i2c/busses/i2c-rcar.c 2014-05-15 20:33:54.585989276 +0200
+@@ -623,12 +623,6 @@
+ u32 bus_speed;
+ int ret;
+
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!res) {
+- dev_err(dev, "no mmio resources\n");
+- return -ENODEV;
+- }
+-
+ priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(dev, "no mem for private data\n");
+@@ -642,6 +636,7 @@
+ if (ret < 0)
+ return ret;
+
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->io = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->io))
+ return PTR_ERR(priv->io);
+diff -Nur linux-3.10.30.orig/drivers/input/keyboard/gpio_keys.c linux-linaro-stable-mx6/drivers/input/keyboard/gpio_keys.c
+--- linux-3.10.30.orig/drivers/input/keyboard/gpio_keys.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/keyboard/gpio_keys.c 2014-05-15 20:33:55.033992505 +0200
+@@ -3,6 +3,7 @@
+ *
+ * Copyright 2005 Phil Blundell
+ * Copyright 2010, 2011 David Jander <david@protonic.nl>
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -472,6 +473,8 @@
+
+ isr = gpio_keys_gpio_isr;
+ irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
++ if (bdata->button->wakeup)
++ irqflags |= IRQF_NO_SUSPEND;
+
+ } else {
+ if (!button->irq) {
+diff -Nur linux-3.10.30.orig/drivers/input/keyboard/imx_keypad.c linux-linaro-stable-mx6/drivers/input/keyboard/imx_keypad.c
+--- linux-3.10.30.orig/drivers/input/keyboard/imx_keypad.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/keyboard/imx_keypad.c 2014-05-15 20:33:55.033992505 +0200
+@@ -1,6 +1,7 @@
+ /*
+ * Driver for the IMX keypad port.
+ * Copyright (C) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -553,6 +554,8 @@
+
+ if (device_may_wakeup(&pdev->dev))
+ enable_irq_wake(kbd->irq);
++ else
++ pinctrl_pm_select_sleep_state(dev);
+
+ return 0;
+ }
+@@ -566,6 +569,8 @@
+
+ if (device_may_wakeup(&pdev->dev))
+ disable_irq_wake(kbd->irq);
++ else
++ pinctrl_pm_select_default_state(dev);
+
+ mutex_lock(&input_dev->mutex);
+
+diff -Nur linux-3.10.30.orig/drivers/input/misc/isl29023.c linux-linaro-stable-mx6/drivers/input/misc/isl29023.c
+--- linux-3.10.30.orig/drivers/input/misc/isl29023.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/misc/isl29023.c 2014-05-15 20:33:55.061992707 +0200
+@@ -0,0 +1,1029 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/regulator/consumer.h>
++#include <linux/isl29023.h>
++
++#define ISL29023_DRV_NAME "isl29023"
++#define DRIVER_VERSION "1.0"
++
++#define ISL29023_COMMAND1 0x00
++#define ISL29023_MODE_SHIFT (5)
++#define ISL29023_MODE_MASK (0x7 << ISL29023_MODE_SHIFT)
++#define ISL29023_INT_FLAG_SHIFT (2)
++#define ISL29023_INT_FLAG_MASK (0x1 << ISL29023_INT_FLAG_SHIFT)
++#define ISL29023_INT_PERSISTS_SHIFT (0)
++#define ISL29023_INT_PERSISTS_MASK (0x3 << ISL29023_INT_PERSISTS_SHIFT)
++
++#define ISL29023_COMMAND2 0x01
++#define ISL29023_RES_SHIFT (2)
++#define ISL29023_RES_MASK (0x3 << ISL29023_RES_SHIFT)
++#define ISL29023_RANGE_SHIFT (0)
++#define ISL29023_RANGE_MASK (0x3 << ISL29023_RANGE_SHIFT)
++
++#define ISL29023_REG_LSB_SENSOR 0x02
++#define ISL29023_REG_MSB_SENSOR 0x03
++#define ISL29023_REG_IRQ_TH_LO_LSB 0x04
++#define ISL29023_REG_IRQ_TH_LO_MSB 0x05
++#define ISL29023_REG_IRQ_TH_HI_LSB 0x06
++#define ISL29023_REG_IRQ_TH_HI_MSB 0x07
++
++#define ISL29023_NUM_CACHABLE_REGS 8
++#define DEF_RANGE 2
++#define DEFAULT_REGISTOR_VAL 499
++
++struct isl29023_data {
++ struct i2c_client *client;
++ struct mutex lock;
++ struct input_dev *input;
++ struct work_struct work;
++ struct workqueue_struct *workqueue;
++ char phys[32];
++ u8 reg_cache[ISL29023_NUM_CACHABLE_REGS];
++ u8 mode_before_suspend;
++ u8 mode_before_interrupt;
++ u16 rext;
++};
++
++static int gain_range[] = {
++ 1000, 4000, 16000, 64000
++};
++
++/*
++ * register access helpers
++ */
++static int __isl29023_read_reg(struct i2c_client *client,
++ u32 reg, u8 mask, u8 shift)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ return (data->reg_cache[reg] & mask) >> shift;
++}
++
++static int __isl29023_write_reg(struct i2c_client *client,
++ u32 reg, u8 mask, u8 shift, u8 val)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int ret = 0;
++ u8 tmp;
++
++ if (reg >= ISL29023_NUM_CACHABLE_REGS)
++ return -EINVAL;
++
++ mutex_lock(&data->lock);
++
++ tmp = data->reg_cache[reg];
++ tmp &= ~mask;
++ tmp |= val << shift;
++
++ ret = i2c_smbus_write_byte_data(client, reg, tmp);
++ if (!ret)
++ data->reg_cache[reg] = tmp;
++
++ mutex_unlock(&data->lock);
++ return ret;
++}
++
++/*
++ * internally used functions
++ */
++
++/* interrupt persists */
++static int isl29023_get_int_persists(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND1,
++ ISL29023_INT_PERSISTS_MASK, ISL29023_INT_PERSISTS_SHIFT);
++}
++
++static int isl29023_set_int_persists(struct i2c_client *client,
++ int int_persists)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND1,
++ ISL29023_INT_PERSISTS_MASK, ISL29023_INT_PERSISTS_SHIFT,
++ int_persists);
++}
++
++/* interrupt flag */
++static int isl29023_get_int_flag(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND1,
++ ISL29023_INT_FLAG_MASK, ISL29023_INT_FLAG_SHIFT);
++}
++
++static int isl29023_set_int_flag(struct i2c_client *client, int flag)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND1,
++ ISL29023_INT_FLAG_MASK, ISL29023_INT_FLAG_SHIFT, flag);
++}
++
++/* interrupt lt */
++static int isl29023_get_int_lt(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, lt;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_LO_LSB);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_LO_MSB);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ lt = ((msb << 8) | lsb);
++
++ return lt;
++}
++
++static int isl29023_set_int_lt(struct i2c_client *client, int lt)
++{
++ int ret = 0;
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ mutex_lock(&data->lock);
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_LO_LSB,
++ lt & 0xff);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_LO_MSB,
++ (lt >> 8) & 0xff);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ data->reg_cache[ISL29023_REG_IRQ_TH_LO_MSB] = (lt >> 8) & 0xff;
++ data->reg_cache[ISL29023_REG_IRQ_TH_LO_LSB] = lt & 0xff;
++ mutex_unlock(&data->lock);
++
++ return ret;
++}
++
++/* interrupt ht */
++static int isl29023_get_int_ht(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, ht;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_HI_LSB);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_HI_MSB);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ ht = ((msb << 8) | lsb);
++
++ return ht;
++}
++
++static int isl29023_set_int_ht(struct i2c_client *client, int ht)
++{
++ int ret = 0;
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ mutex_lock(&data->lock);
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_HI_LSB,
++ ht & 0xff);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_HI_MSB,
++ (ht >> 8) & 0xff);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ data->reg_cache[ISL29023_REG_IRQ_TH_HI_MSB] = (ht >> 8) & 0xff;
++ data->reg_cache[ISL29023_REG_IRQ_TH_HI_LSB] = ht & 0xff;
++ mutex_unlock(&data->lock);
++
++ return ret;
++}
++
++/* range */
++static int isl29023_get_range(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND2,
++ ISL29023_RANGE_MASK, ISL29023_RANGE_SHIFT);
++}
++
++static int isl29023_set_range(struct i2c_client *client, int range)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND2,
++ ISL29023_RANGE_MASK, ISL29023_RANGE_SHIFT, range);
++}
++
++/* resolution */
++static int isl29023_get_resolution(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND2,
++ ISL29023_RES_MASK, ISL29023_RES_SHIFT);
++}
++
++static int isl29023_set_resolution(struct i2c_client *client, int res)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND2,
++ ISL29023_RES_MASK, ISL29023_RES_SHIFT, res);
++}
++
++/* mode */
++static int isl29023_get_mode(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND1,
++ ISL29023_MODE_MASK, ISL29023_MODE_SHIFT);
++}
++
++static int isl29023_set_mode(struct i2c_client *client, int mode)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND1,
++ ISL29023_MODE_MASK, ISL29023_MODE_SHIFT, mode);
++}
++
++/* power_state */
++static int isl29023_set_power_state(struct i2c_client *client, int state)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND1,
++ ISL29023_MODE_MASK, ISL29023_MODE_SHIFT,
++ state ?
++ ISL29023_ALS_ONCE_MODE : ISL29023_PD_MODE);
++}
++
++static int isl29023_get_power_state(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ u8 cmdreg = data->reg_cache[ISL29023_COMMAND1];
++
++ if (cmdreg & ISL29023_MODE_MASK)
++ return 1;
++ else
++ return 0;
++}
++
++static int isl29023_get_adc_value(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, range, bitdepth;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_LSB_SENSOR);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_MSB_SENSOR);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ return (((msb << 8) | lsb) * ((gain_range[range] * 499) / data->rext))
++ >> bitdepth;
++}
++
++static int isl29023_get_int_lt_value(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, range, bitdepth;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_LO_LSB);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_LO_MSB);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ return (((msb << 8) | lsb) * ((gain_range[range] * 499) / data->rext))
++ >> bitdepth;
++}
++
++static int isl29023_get_int_ht_value(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, range, bitdepth;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_HI_LSB);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_HI_MSB);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ return (((msb << 8) | lsb) * ((gain_range[range] * 499) / data->rext))
++ >> bitdepth;
++}
++
++/*
++ * sysfs layer
++ */
++
++/* interrupt persists */
++static ssize_t isl29023_show_int_persists(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_int_persists(client));
++}
++
++static ssize_t isl29023_store_int_persists(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) ||
++ (val > ISL29023_INT_PERSISTS_16))
++ return -EINVAL;
++
++ ret = isl29023_set_int_persists(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(int_persists, S_IWUSR | S_IRUGO,
++ isl29023_show_int_persists, isl29023_store_int_persists);
++
++/* interrupt flag */
++static ssize_t isl29023_show_int_flag(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_int_flag(client));
++}
++
++static ssize_t isl29023_store_int_flag(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > 1))
++ return -EINVAL;
++
++ ret = isl29023_set_int_flag(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(int_flag, S_IWUSR | S_IRUGO,
++ isl29023_show_int_flag, isl29023_store_int_flag);
++
++/* interrupt lt */
++static ssize_t isl29023_show_int_lt(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_int_lt(client));
++}
++
++static ssize_t isl29023_store_int_lt(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 16, &val) < 0) || (val > 0xffff))
++ return -EINVAL;
++
++ ret = isl29023_set_int_lt(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(int_lt, S_IWUSR | S_IRUGO,
++ isl29023_show_int_lt, isl29023_store_int_lt);
++
++/* interrupt ht */
++static ssize_t isl29023_show_int_ht(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_int_ht(client));
++}
++
++static ssize_t isl29023_store_int_ht(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 16, &val) < 0) || (val > 0xffff))
++ return -EINVAL;
++
++ ret = isl29023_set_int_ht(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(int_ht, S_IWUSR | S_IRUGO,
++ isl29023_show_int_ht, isl29023_store_int_ht);
++
++/* range */
++static ssize_t isl29023_show_range(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_range(client));
++}
++
++static ssize_t isl29023_store_range(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > ISL29023_RANGE_64K))
++ return -EINVAL;
++
++ ret = isl29023_set_range(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(range, S_IWUSR | S_IRUGO,
++ isl29023_show_range, isl29023_store_range);
++
++
++/* resolution */
++static ssize_t isl29023_show_resolution(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%d\n", isl29023_get_resolution(client));
++}
++
++static ssize_t isl29023_store_resolution(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > ISL29023_RES_4))
++ return -EINVAL;
++
++ ret = isl29023_set_resolution(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(resolution, S_IWUSR | S_IRUGO,
++ isl29023_show_resolution, isl29023_store_resolution);
++
++/* mode */
++static ssize_t isl29023_show_mode(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%d\n", isl29023_get_mode(client));
++}
++
++static ssize_t isl29023_store_mode(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) ||
++ (val > ISL29023_IR_CONT_MODE))
++ return -EINVAL;
++
++ ret = isl29023_set_mode(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(mode, S_IWUSR | S_IRUGO,
++ isl29023_show_mode, isl29023_store_mode);
++
++
++/* power state */
++static ssize_t isl29023_show_power_state(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%d\n", isl29023_get_power_state(client));
++}
++
++static ssize_t isl29023_store_power_state(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > 1))
++ return -EINVAL;
++
++ ret = isl29023_set_power_state(client, val);
++ return ret ? ret : count;
++}
++
++static DEVICE_ATTR(power_state, S_IWUSR | S_IRUGO,
++ isl29023_show_power_state, isl29023_store_power_state);
++
++/* lux */
++static ssize_t isl29023_show_lux(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++
++ /* No LUX data if not operational */
++ if (!isl29023_get_power_state(client))
++ return -EBUSY;
++
++ return sprintf(buf, "%d\n", isl29023_get_adc_value(client));
++}
++
++static DEVICE_ATTR(lux, S_IRUGO, isl29023_show_lux, NULL);
++
++/* lux interrupt low threshold */
++static ssize_t isl29023_show_int_lt_lux(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++
++ /* No LUX data if not operational */
++ if (isl29023_get_mode(client) != ISL29023_ALS_ONCE_MODE &&
++ isl29023_get_mode(client) != ISL29023_ALS_CONT_MODE)
++ return -EIO;
++
++ return sprintf(buf, "%d\n", isl29023_get_int_lt_value(client));
++}
++
++static ssize_t isl29023_store_int_lt_lux(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ unsigned long val, lux_data;
++ int range, bitdepth, ret;
++ u8 lsb, msb;
++
++ if ((strict_strtoul(buf, 10, &val) < 0))
++ return -EINVAL;
++
++ /* No LUX data if not operational */
++ if (isl29023_get_mode(client) != ISL29023_ALS_ONCE_MODE &&
++ isl29023_get_mode(client) != ISL29023_ALS_CONT_MODE)
++ return -EIO;
++
++ if (val > (gain_range[isl29023_get_range(client)]*499/data->rext))
++ return -EINVAL;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ lux_data = ((unsigned long)(val << bitdepth)) /
++ ((gain_range[range] * 499) / data->rext);
++ lux_data &= 0xffff;
++
++ msb = lux_data >> 8;
++ lsb = lux_data & 0xff;
++
++ mutex_lock(&data->lock);
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_LO_LSB,
++ lsb);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_LO_MSB,
++ msb);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ data->reg_cache[ISL29023_REG_IRQ_TH_LO_MSB] = msb;
++ data->reg_cache[ISL29023_REG_IRQ_TH_LO_LSB] = lsb;
++ mutex_unlock(&data->lock);
++
++ return count;
++}
++
++static DEVICE_ATTR(int_lt_lux, S_IWUSR | S_IRUGO,
++ isl29023_show_int_lt_lux, isl29023_store_int_lt_lux);
++
++/* lux interrupt high threshold */
++static ssize_t isl29023_show_int_ht_lux(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++
++ /* No LUX data if not operational */
++ if (isl29023_get_mode(client) != ISL29023_ALS_ONCE_MODE &&
++ isl29023_get_mode(client) != ISL29023_ALS_CONT_MODE)
++ return -EIO;
++
++ return sprintf(buf, "%d\n", isl29023_get_int_ht_value(client));
++}
++
++static ssize_t isl29023_store_int_ht_lux(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ unsigned long val, lux_data;
++ int range, bitdepth, ret;
++ u8 lsb, msb;
++
++ if ((strict_strtoul(buf, 10, &val) < 0))
++ return -EINVAL;
++
++ /* No LUX data if not operational */
++ if (isl29023_get_mode(client) != ISL29023_ALS_ONCE_MODE &&
++ isl29023_get_mode(client) != ISL29023_ALS_CONT_MODE)
++ return -EIO;
++
++ if (val > (gain_range[isl29023_get_range(client)]*499/data->rext))
++ return -EINVAL;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ lux_data = ((unsigned long)(val << bitdepth)) /
++ ((gain_range[range] * 499) / data->rext);
++ lux_data &= 0xffff;
++
++ msb = lux_data >> 8;
++ lsb = lux_data & 0xff;
++
++ mutex_lock(&data->lock);
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_HI_LSB,
++ lsb);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_HI_MSB,
++ msb);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ data->reg_cache[ISL29023_REG_IRQ_TH_HI_MSB] = msb;
++ data->reg_cache[ISL29023_REG_IRQ_TH_HI_LSB] = lsb;
++ mutex_unlock(&data->lock);
++
++ return count;
++}
++
++static DEVICE_ATTR(int_ht_lux, S_IWUSR | S_IRUGO,
++ isl29023_show_int_ht_lux, isl29023_store_int_ht_lux);
++
++static struct attribute *isl29023_attributes[] = {
++ &dev_attr_int_persists.attr,
++ &dev_attr_range.attr,
++ &dev_attr_resolution.attr,
++ &dev_attr_mode.attr,
++ &dev_attr_power_state.attr,
++ &dev_attr_lux.attr,
++ &dev_attr_int_lt_lux.attr,
++ &dev_attr_int_ht_lux.attr,
++ &dev_attr_int_lt.attr,
++ &dev_attr_int_ht.attr,
++ &dev_attr_int_flag.attr,
++ NULL
++};
++
++static const struct attribute_group isl29023_attr_group = {
++ .attrs = isl29023_attributes,
++};
++
++static int isl29023_init_client(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int i;
++
++ /* read all the registers once to fill the cache.
++ * if one of the reads fails, we consider the init failed */
++ for (i = 0; i < ARRAY_SIZE(data->reg_cache); i++) {
++ int v = i2c_smbus_read_byte_data(client, i);
++ if (v < 0)
++ return -ENODEV;
++
++ data->reg_cache[i] = v;
++ }
++
++ /* set defaults */
++ isl29023_set_int_persists(client, ISL29023_INT_PERSISTS_8);
++ isl29023_set_int_ht(client, 0xffff);
++ isl29023_set_int_lt(client, 0x0);
++ isl29023_set_range(client, ISL29023_RANGE_16K);
++ isl29023_set_resolution(client, ISL29023_RES_16);
++ isl29023_set_mode(client, ISL29023_ALS_ONCE_MODE);
++ isl29023_set_int_flag(client, 0);
++ isl29023_set_power_state(client, 0);
++
++ return 0;
++}
++
++static void isl29023_work(struct work_struct *work)
++{
++ struct isl29023_data *data =
++ container_of(work, struct isl29023_data, work);
++ struct i2c_client *client = data->client;
++ int lux;
++
++ /* Clear interrupt flag */
++ isl29023_set_int_flag(client, 0);
++
++ data->mode_before_interrupt = isl29023_get_mode(client);
++ lux = isl29023_get_adc_value(client);
++
++ /* To clear the interrpt status */
++ isl29023_set_power_state(client, ISL29023_PD_MODE);
++ isl29023_set_mode(client, data->mode_before_interrupt);
++
++ msleep(100);
++
++ input_report_abs(data->input, ABS_MISC, lux);
++ input_sync(data->input);
++}
++
++static irqreturn_t isl29023_irq_handler(int irq, void *handle)
++{
++ struct isl29023_data *data = handle;
++ queue_work(data->workqueue, &data->work);
++ return IRQ_HANDLED;
++}
++
++/*
++ * I2C layer
++ */
++
++static int isl29023_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
++ struct isl29023_data *data;
++ struct input_dev *input_dev;
++ int err = 0;
++ struct regulator *vdd = NULL;
++ u32 rext = 0;
++ struct device_node *of_node = client->dev.of_node;
++
++ vdd = devm_regulator_get(&client->dev, "vdd");
++ if (!IS_ERR(vdd)) {
++ err = regulator_enable(vdd);
++ if (err) {
++ dev_err(&client->dev, "vdd set voltage error\n");
++ return err;
++ }
++ }
++
++ err = of_property_read_u32(of_node, "rext", &rext);
++ if (err)
++ rext = DEFAULT_REGISTOR_VAL;
++
++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE))
++ return -EIO;
++
++ data = kzalloc(sizeof(struct isl29023_data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ data->client = client;
++ data->rext = (u16)rext;
++ snprintf(data->phys, sizeof(data->phys),
++ "%s", dev_name(&client->dev));
++ i2c_set_clientdata(client, data);
++ mutex_init(&data->lock);
++
++ /* initialize the ISL29023 chip */
++ err = isl29023_init_client(client);
++ if (err)
++ goto exit_kfree;
++
++ /* register sysfs hooks */
++ err = sysfs_create_group(&client->dev.kobj, &isl29023_attr_group);
++ if (err)
++ goto exit_kfree;
++
++ input_dev = input_allocate_device();
++ if (!input_dev) {
++ err = -ENOMEM;
++ goto exit_kfree;
++ }
++
++ data->input = input_dev;
++ input_dev->name = "isl29023 light sensor";
++ input_dev->id.bustype = BUS_I2C;
++ input_dev->phys = data->phys;
++
++ __set_bit(EV_ABS, input_dev->evbit);
++ input_set_abs_params(input_dev, ABS_MISC, 0,
++ gain_range[DEF_RANGE]*499/data->rext, 0, 0);
++
++ err = input_register_device(input_dev);
++ if (err)
++ goto exit_free_input;
++
++ /* set irq type to edge falling */
++ irq_set_irq_type(client->irq, IRQF_TRIGGER_FALLING);
++ err = request_irq(client->irq, isl29023_irq_handler, 0,
++ client->dev.driver->name, data);
++ if (err < 0) {
++ dev_err(&client->dev, "failed to register irq %d!\n",
++ client->irq);
++ goto exit_free_input;
++ }
++
++ data->workqueue = create_singlethread_workqueue("isl29023");
++ INIT_WORK(&data->work, isl29023_work);
++ if (data->workqueue == NULL) {
++ dev_err(&client->dev, "couldn't create workqueue\n");
++ err = -ENOMEM;
++ goto exit_free_interrupt;
++ }
++
++ dev_info(&client->dev, "driver version %s enabled\n", DRIVER_VERSION);
++ return 0;
++
++exit_free_interrupt:
++ free_irq(client->irq, data);
++exit_free_input:
++ input_free_device(input_dev);
++exit_kfree:
++ kfree(data);
++ return err;
++}
++
++static int isl29023_remove(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ cancel_work_sync(&data->work);
++ destroy_workqueue(data->workqueue);
++ free_irq(client->irq, data);
++ input_unregister_device(data->input);
++ input_free_device(data->input);
++ sysfs_remove_group(&client->dev.kobj, &isl29023_attr_group);
++ isl29023_set_power_state(client, 0);
++ kfree(i2c_get_clientdata(client));
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int isl29023_suspend(struct i2c_client *client, pm_message_t mesg)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ data->mode_before_suspend = isl29023_get_mode(client);
++ return isl29023_set_power_state(client, ISL29023_PD_MODE);
++}
++
++static int isl29023_resume(struct i2c_client *client)
++{
++ int i;
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ /* restore registers from cache */
++ for (i = 0; i < ARRAY_SIZE(data->reg_cache); i++)
++ if (i2c_smbus_write_byte_data(client, i, data->reg_cache[i]))
++ return -EIO;
++
++ return isl29023_set_mode(client, data->mode_before_suspend);
++}
++
++#else
++#define isl29023_suspend NULL
++#define isl29023_resume NULL
++#endif /* CONFIG_PM */
++
++static const struct i2c_device_id isl29023_id[] = {
++ { ISL29023_DRV_NAME, 0 },
++ {}
++};
++MODULE_DEVICE_TABLE(i2c, isl29023_id);
++
++static struct i2c_driver isl29023_driver = {
++ .driver = {
++ .name = ISL29023_DRV_NAME,
++ .owner = THIS_MODULE,
++ },
++ .suspend = isl29023_suspend,
++ .resume = isl29023_resume,
++ .probe = isl29023_probe,
++ .remove = isl29023_remove,
++ .id_table = isl29023_id,
++};
++
++static int __init isl29023_init(void)
++{
++ return i2c_add_driver(&isl29023_driver);
++}
++
++static void __exit isl29023_exit(void)
++{
++ i2c_del_driver(&isl29023_driver);
++}
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("ISL29023 ambient light sensor driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION(DRIVER_VERSION);
++
++module_init(isl29023_init);
++module_exit(isl29023_exit);
+diff -Nur linux-3.10.30.orig/drivers/input/misc/Kconfig linux-linaro-stable-mx6/drivers/input/misc/Kconfig
+--- linux-3.10.30.orig/drivers/input/misc/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/misc/Kconfig 2014-05-15 20:33:55.061992707 +0200
+@@ -637,4 +637,14 @@
+ To compile this driver as a module, choose M here: the
+ module will be called xen-kbdfront.
+
++config INPUT_ISL29023
++ tristate "Intersil ISL29023 ambient light sensor"
++ depends on I2C && SYSFS
++ help
++ If you say yes here you get support for the Intersil ISL29023
++ ambient light sensor.
++
++ This driver can also be built as a module. If so, the module
++ will be called isl29023.
++
+ endif
+diff -Nur linux-3.10.30.orig/drivers/input/misc/Makefile linux-linaro-stable-mx6/drivers/input/misc/Makefile
+--- linux-3.10.30.orig/drivers/input/misc/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/misc/Makefile 2014-05-15 20:33:55.061992707 +0200
+@@ -60,3 +60,4 @@
+ obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o
+ obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND) += xen-kbdfront.o
+ obj-$(CONFIG_INPUT_YEALINK) += yealink.o
++obj-$(CONFIG_INPUT_ISL29023) += isl29023.o
+diff -Nur linux-3.10.30.orig/drivers/input/misc/mma8450.c linux-linaro-stable-mx6/drivers/input/misc/mma8450.c
+--- linux-3.10.30.orig/drivers/input/misc/mma8450.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/misc/mma8450.c 2014-05-15 20:33:55.065992735 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Driver for Freescale's 3-Axis Accelerometer MMA8450
+ *
+- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+@@ -51,6 +51,8 @@
+
+ #define MMA8450_CTRL_REG1 0x38
+ #define MMA8450_CTRL_REG2 0x39
++#define MMA8450_ID 0xC6
++#define MMA8450_WHO_AM_I 0x0F
+
+ /* mma8450 status */
+ struct mma8450 {
+@@ -172,7 +174,25 @@
+ {
+ struct input_polled_dev *idev;
+ struct mma8450 *m;
+- int err;
++ int err, client_id;
++ struct i2c_adapter *adapter = NULL;
++
++ adapter = to_i2c_adapter(c->dev.parent);
++ err = i2c_check_functionality(adapter,
++ I2C_FUNC_SMBUS_BYTE |
++ I2C_FUNC_SMBUS_BYTE_DATA);
++ if (!err)
++ goto err_out;
++
++ client_id = i2c_smbus_read_byte_data(c, MMA8450_WHO_AM_I);
++
++ if (MMA8450_ID != client_id) {
++ dev_err(&c->dev,
++ "read chip ID 0x%x is not equal to 0x%x!\n", client_id,
++ MMA8450_ID);
++ err = -EINVAL;
++ goto err_out;
++ }
+
+ m = kzalloc(sizeof(struct mma8450), GFP_KERNEL);
+ idev = input_allocate_polled_device();
+@@ -209,6 +229,7 @@
+ err_free_mem:
+ input_free_polled_device(idev);
+ kfree(m);
++err_out:
+ return err;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/input/touchscreen/egalax_ts.c linux-linaro-stable-mx6/drivers/input/touchscreen/egalax_ts.c
+--- linux-3.10.30.orig/drivers/input/touchscreen/egalax_ts.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/touchscreen/egalax_ts.c 2014-05-15 20:33:55.141993284 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Driver for EETI eGalax Multiple Touch Controller
+ *
+- * Copyright (C) 2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * based on max11801_ts.c
+ *
+@@ -35,7 +35,7 @@
+ * which can only report one point at a given time.
+ * This driver will ignore events in this mode.
+ */
+-#define REPORT_MODE_MOUSE 0x1
++#define REPORT_MODE_SINGLE 0x1
+ /*
+ * Vendor Mode: this mode is used to transfer some vendor specific
+ * messages.
+@@ -47,6 +47,8 @@
+
+ #define MAX_SUPPORT_POINTS 5
+
++#define EVENT_MODE 0
++#define EVENT_STATUS 1
+ #define EVENT_VALID_OFFSET 7
+ #define EVENT_VALID_MASK (0x1 << EVENT_VALID_OFFSET)
+ #define EVENT_ID_OFFSET 2
+@@ -56,13 +58,21 @@
+
+ #define MAX_I2C_DATA_LEN 10
+
+-#define EGALAX_MAX_X 32760
+-#define EGALAX_MAX_Y 32760
++#define EGALAX_MAX_X 32767
++#define EGALAX_MAX_Y 32767
+ #define EGALAX_MAX_TRIES 100
+
++struct egalax_pointer {
++ bool valid;
++ bool status;
++ u16 x;
++ u16 y;
++};
++
+ struct egalax_ts {
+ struct i2c_client *client;
+ struct input_dev *input_dev;
++ struct egalax_pointer events[MAX_SUPPORT_POINTS];
+ };
+
+ static irqreturn_t egalax_ts_interrupt(int irq, void *dev_id)
+@@ -70,8 +80,9 @@
+ struct egalax_ts *ts = dev_id;
+ struct input_dev *input_dev = ts->input_dev;
+ struct i2c_client *client = ts->client;
++ struct egalax_pointer *events = ts->events;
+ u8 buf[MAX_I2C_DATA_LEN];
+- int id, ret, x, y, z;
++ int i, id, ret, x, y;
+ int tries = 0;
+ bool down, valid;
+ u8 state;
+@@ -83,15 +94,38 @@
+ if (ret < 0)
+ return IRQ_HANDLED;
+
+- if (buf[0] != REPORT_MODE_MTTOUCH) {
+- /* ignore mouse events and vendor events */
++ dev_dbg(&client->dev, "recv ret:%d", ret);
++ for (i = 0; i < MAX_I2C_DATA_LEN; i++)
++ dev_dbg(&client->dev, " %x ", buf[i]);
++
++ if (buf[0] != REPORT_MODE_VENDOR
++ && buf[0] != REPORT_MODE_SINGLE
++ && buf[0] != REPORT_MODE_MTTOUCH) {
++ /* invalid point */
++ return IRQ_HANDLED;
++ }
++
++ if (buf[0] == REPORT_MODE_VENDOR) {
++ dev_dbg(&client->dev, "vendor message, ignored\n");
+ return IRQ_HANDLED;
+ }
+
+ state = buf[1];
+ x = (buf[3] << 8) | buf[2];
+ y = (buf[5] << 8) | buf[4];
+- z = (buf[7] << 8) | buf[6];
++
++ /* Currently, the panel Freescale using on SMD board _NOT_
++ * support single pointer mode. All event are going to
++ * multiple pointer mode. Add single pointer mode according
++ * to EETI eGalax I2C programming manual.
++ */
++ if (buf[0] == REPORT_MODE_SINGLE) {
++ input_report_abs(input_dev, ABS_X, x);
++ input_report_abs(input_dev, ABS_Y, y);
++ input_report_key(input_dev, BTN_TOUCH, !!state);
++ input_sync(input_dev);
++ return IRQ_HANDLED;
++ }
+
+ valid = state & EVENT_VALID_MASK;
+ id = (state & EVENT_ID_MASK) >> EVENT_ID_OFFSET;
+@@ -102,19 +136,50 @@
+ return IRQ_HANDLED;
+ }
+
+- input_mt_slot(input_dev, id);
+- input_mt_report_slot_state(input_dev, MT_TOOL_FINGER, down);
+-
+- dev_dbg(&client->dev, "%s id:%d x:%d y:%d z:%d",
+- down ? "down" : "up", id, x, y, z);
+-
+ if (down) {
+- input_report_abs(input_dev, ABS_MT_POSITION_X, x);
+- input_report_abs(input_dev, ABS_MT_POSITION_Y, y);
+- input_report_abs(input_dev, ABS_MT_PRESSURE, z);
++ events[id].valid = valid;
++ events[id].status = down;
++ events[id].x = x;
++ events[id].y = y;
++
++#ifdef CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH
++ input_report_abs(input_dev, ABS_X, x);
++ input_report_abs(input_dev, ABS_Y, y);
++ input_event(ts->input_dev, EV_KEY, BTN_TOUCH, 1);
++ input_report_abs(input_dev, ABS_PRESSURE, 1);
++#endif
++ } else {
++ dev_dbg(&client->dev, "release id:%d\n", id);
++ events[id].valid = 0;
++ events[id].status = 0;
++#ifdef CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH
++ input_report_key(input_dev, BTN_TOUCH, 0);
++ input_report_abs(input_dev, ABS_PRESSURE, 0);
++#else
++ input_report_abs(input_dev, ABS_MT_TRACKING_ID, id);
++ input_event(input_dev, EV_ABS, ABS_MT_TOUCH_MAJOR, 0);
++ input_mt_sync(input_dev);
++#endif
+ }
+
+- input_mt_report_pointer_emulation(input_dev, true);
++#ifndef CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH
++ /* report all pointers */
++ for (i = 0; i < MAX_SUPPORT_POINTS; i++) {
++ if (!events[i].valid)
++ continue;
++ dev_dbg(&client->dev, "report id:%d valid:%d x:%d y:%d",
++ i, valid, x, y);
++ input_report_abs(input_dev,
++ ABS_MT_TRACKING_ID, i);
++ input_report_abs(input_dev,
++ ABS_MT_TOUCH_MAJOR, 1);
++ input_report_abs(input_dev,
++ ABS_MT_POSITION_X, events[i].x);
++ input_report_abs(input_dev,
++ ABS_MT_POSITION_Y, events[i].y);
++ input_mt_sync(input_dev);
++ }
++#endif
+ input_sync(input_dev);
+
+ return IRQ_HANDLED;
+@@ -203,22 +268,34 @@
+ goto err_free_dev;
+ }
+
+- input_dev->name = "EETI eGalax Touch Screen";
++ input_dev->name = "eGalax Touch Screen";
++ input_dev->phys = "I2C",
+ input_dev->id.bustype = BUS_I2C;
++ input_dev->id.vendor = 0x0EEF;
++ input_dev->id.product = 0x0020;
++ input_dev->id.version = 0x0001;
+ input_dev->dev.parent = &client->dev;
+
+ __set_bit(EV_ABS, input_dev->evbit);
+ __set_bit(EV_KEY, input_dev->evbit);
+ __set_bit(BTN_TOUCH, input_dev->keybit);
+-
++ __set_bit(ABS_X, input_dev->absbit);
++ __set_bit(ABS_Y, input_dev->absbit);
++ __set_bit(ABS_PRESSURE, input_dev->absbit);
+ input_set_abs_params(input_dev, ABS_X, 0, EGALAX_MAX_X, 0, 0);
+ input_set_abs_params(input_dev, ABS_Y, 0, EGALAX_MAX_Y, 0, 0);
+- input_set_abs_params(input_dev,
+- ABS_MT_POSITION_X, 0, EGALAX_MAX_X, 0, 0);
+- input_set_abs_params(input_dev,
+- ABS_MT_POSITION_Y, 0, EGALAX_MAX_Y, 0, 0);
+- input_mt_init_slots(input_dev, MAX_SUPPORT_POINTS, 0);
++ input_set_abs_params(input_dev, ABS_PRESSURE, 0, 1, 0, 0);
+
++#ifndef CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH
++ input_set_abs_params(input_dev, ABS_MT_POSITION_X,
++ 0, EGALAX_MAX_X, 0, 0);
++ input_set_abs_params(input_dev, ABS_MT_POSITION_Y,
++ 0, EGALAX_MAX_Y, 0, 0);
++ input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
++ input_set_abs_params(input_dev, ABS_MT_WIDTH_MAJOR, 0, 255, 0, 0);
++ input_set_abs_params(input_dev, ABS_MT_TRACKING_ID, 0,
++ MAX_SUPPORT_POINTS, 0, 0);
++#endif
+ input_set_drvdata(input_dev, ts);
+
+ error = request_threaded_irq(client->irq, NULL, egalax_ts_interrupt,
+diff -Nur linux-3.10.30.orig/drivers/input/touchscreen/elan_ts.c linux-linaro-stable-mx6/drivers/input/touchscreen/elan_ts.c
+--- linux-3.10.30.orig/drivers/input/touchscreen/elan_ts.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/touchscreen/elan_ts.c 2014-05-15 20:33:55.141993284 +0200
+@@ -0,0 +1,472 @@
++/*
++ * Copyright (C) 2007-2008 HTC Corporation.
++ *
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This driver is adapted from elan8232_i2c.c written by Shan-Fu Chiou
++ * <sfchiou@gmail.com> and Jay Tu <jay_tu@htc.com>.
++ * This driver is also adapted from the ELAN Touch Screen driver
++ * written by Stanley Zeng <stanley.zeng@emc.com.tw>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/input.h>
++#include <linux/device.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/jiffies.h>
++#include <linux/interrupt.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/hrtimer.h>
++#include <linux/of_gpio.h>
++#include <linux/regulator/consumer.h>
++#include <linux/gpio.h>
++
++static const char ELAN_TS_NAME[] = "elan-touch";
++
++#define ELAN_TS_X_MAX 1088
++#define ELAN_TS_Y_MAX 768
++#define ELAN_USER_X_MAX 800
++#define ELAN_USER_Y_MAX 600
++#define IDX_PACKET_SIZE 8
++
++enum {
++ hello_packet = 0x55,
++ idx_coordinate_packet = 0x5a,
++};
++
++enum {
++ idx_finger_state = 7,
++};
++
++static struct workqueue_struct *elan_wq;
++
++static struct elan_data {
++ int intr_gpio;
++ int use_irq;
++ struct hrtimer timer;
++ struct work_struct work;
++ struct i2c_client *client;
++ struct input_dev *input;
++ wait_queue_head_t wait;
++} elan_touch_data;
++
++/*--------------------------------------------------------------*/
++static int elan_touch_detect_int_level(void)
++{
++ int v;
++ v = gpio_get_value(elan_touch_data.intr_gpio);
++
++ return v;
++}
++
++static int __elan_touch_poll(struct i2c_client *client)
++{
++ int status = 0, retry = 20;
++
++ do {
++ status = elan_touch_detect_int_level();
++ retry--;
++ mdelay(20);
++ } while (status == 1 && retry > 0);
++
++ return (status == 0 ? 0 : -ETIMEDOUT);
++}
++
++static int elan_touch_poll(struct i2c_client *client)
++{
++ return __elan_touch_poll(client);
++}
++
++static int __hello_packet_handler(struct i2c_client *client)
++{
++ int rc;
++ uint8_t buf_recv[4] = { 0 };
++
++ rc = elan_touch_poll(client);
++
++ if (rc < 0)
++ return -EINVAL;
++
++ rc = i2c_master_recv(client, buf_recv, 4);
++
++ if (rc != 4) {
++ return rc;
++ } else {
++ int i;
++ pr_info("hello packet: [0x%02x 0x%02x 0x%02x 0x%02x]\n",
++ buf_recv[0], buf_recv[1], buf_recv[2], buf_recv[3]);
++
++ for (i = 0; i < 4; i++)
++ if (buf_recv[i] != hello_packet)
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static inline int elan_touch_parse_xy(uint8_t *data, uint16_t *x,
++ uint16_t *y)
++{
++ *x = (data[0] & 0xf0);
++ *x <<= 4;
++ *x |= data[1];
++ if (*x >= ELAN_TS_X_MAX)
++ *x = ELAN_TS_X_MAX;
++ *x = ((((ELAN_TS_X_MAX -
++ *x) * 1000) / ELAN_TS_X_MAX) * ELAN_USER_X_MAX) / 1000;
++
++ *y = (data[0] & 0x0f);
++ *y <<= 8;
++ *y |= data[2];
++ if (*y >= ELAN_TS_Y_MAX)
++ *y = ELAN_TS_Y_MAX;
++ *y = ((((ELAN_TS_Y_MAX -
++ *y) * 1000) / ELAN_TS_Y_MAX) * ELAN_USER_Y_MAX) / 1000;
++
++ return 0;
++}
++
++/* __elan_touch_init -- hand shaking with touch panel
++ *
++ * 1.recv hello packet
++ */
++static int __elan_touch_init(struct i2c_client *client)
++{
++ int rc;
++ rc = __hello_packet_handler(client);
++ if (rc < 0)
++ goto hand_shake_failed;
++
++hand_shake_failed:
++ return rc;
++}
++
++static int elan_touch_recv_data(struct i2c_client *client, uint8_t * buf)
++{
++ int rc, bytes_to_recv = IDX_PACKET_SIZE;
++
++ if (buf == NULL)
++ return -EINVAL;
++
++ memset(buf, 0, bytes_to_recv);
++ rc = i2c_master_recv(client, buf, bytes_to_recv);
++ if (rc != bytes_to_recv)
++ return -EINVAL;
++
++ return rc;
++}
++
++static void elan_touch_report_data(struct i2c_client *client, uint8_t * buf)
++{
++ switch (buf[0]) {
++ case idx_coordinate_packet:
++ {
++ uint16_t x1, x2, y1, y2;
++ uint8_t finger_stat;
++
++ finger_stat = (buf[idx_finger_state] & 0x06) >> 1;
++
++ if (finger_stat == 0) {
++ input_report_key(elan_touch_data.input, BTN_TOUCH, 0);
++ input_report_key(elan_touch_data.input, BTN_2, 0);
++ } else if (finger_stat == 1) {
++ elan_touch_parse_xy(&buf[1], &x1, &y1);
++ input_report_abs(elan_touch_data.input, ABS_X, x1);
++ input_report_abs(elan_touch_data.input, ABS_Y, y1);
++ input_report_key(elan_touch_data.input, BTN_TOUCH, 1);
++ input_report_key(elan_touch_data.input, BTN_2, 0);
++ } else if (finger_stat == 2) {
++ elan_touch_parse_xy(&buf[1], &x1, &y1);
++ input_report_abs(elan_touch_data.input, ABS_X, x1);
++ input_report_abs(elan_touch_data.input, ABS_Y, y1);
++ input_report_key(elan_touch_data.input, BTN_TOUCH, 1);
++ elan_touch_parse_xy(&buf[4], &x2, &y2);
++ input_report_abs(elan_touch_data.input, ABS_HAT0X, x2);
++ input_report_abs(elan_touch_data.input, ABS_HAT0Y, y2);
++ input_report_key(elan_touch_data.input, BTN_2, 1);
++ }
++ input_sync(elan_touch_data.input);
++ break;
++ }
++
++ default:
++ break;
++ }
++}
++
++static void elan_touch_work_func(struct work_struct *work)
++{
++ int rc;
++ uint8_t buf[IDX_PACKET_SIZE] = { 0 };
++ struct i2c_client *client = elan_touch_data.client;
++
++ if (elan_touch_detect_int_level())
++ return;
++
++ rc = elan_touch_recv_data(client, buf);
++ if (rc < 0)
++ return;
++
++ elan_touch_report_data(client, buf);
++}
++
++static irqreturn_t elan_touch_ts_interrupt(int irq, void *dev_id)
++{
++ queue_work(elan_wq, &elan_touch_data.work);
++
++ return IRQ_HANDLED;
++}
++
++static enum hrtimer_restart elan_touch_timer_func(struct hrtimer *timer)
++{
++ queue_work(elan_wq, &elan_touch_data.work);
++ hrtimer_start(&elan_touch_data.timer, ktime_set(0, 12500000),
++ HRTIMER_MODE_REL);
++
++ return HRTIMER_NORESTART;
++}
++
++static int elan_touch_register_interrupt(struct i2c_client *client)
++{
++ int err = 0;
++
++ if (client->irq) {
++ elan_touch_data.use_irq = 1;
++ err =
++ request_irq(client->irq, elan_touch_ts_interrupt,
++ IRQF_TRIGGER_FALLING, ELAN_TS_NAME,
++ &elan_touch_data);
++
++ if (err < 0) {
++ pr_info("%s(%s): Can't allocate irq %d\n", __FILE__,
++ __func__, client->irq);
++ elan_touch_data.use_irq = 0;
++ }
++ }
++
++ if (!elan_touch_data.use_irq) {
++ hrtimer_init(&elan_touch_data.timer, CLOCK_MONOTONIC,
++ HRTIMER_MODE_REL);
++ elan_touch_data.timer.function = elan_touch_timer_func;
++ hrtimer_start(&elan_touch_data.timer, ktime_set(1, 0),
++ HRTIMER_MODE_REL);
++ }
++
++ pr_info("elan ts starts in %s mode.\n",
++ elan_touch_data.use_irq == 1 ? "interrupt" : "polling");
++
++ return 0;
++}
++
++static int elan_touch_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct device_node *np = client->dev.of_node;
++ int gpio_elan_cs, gpio_elan_rst, err = 0;
++
++ if (!np)
++ return -ENODEV;
++
++ elan_touch_data.intr_gpio = of_get_named_gpio(np, "gpio_intr", 0);
++ if (!gpio_is_valid(elan_touch_data.intr_gpio))
++ return -ENODEV;
++
++ err = devm_gpio_request_one(&client->dev, elan_touch_data.intr_gpio,
++ GPIOF_IN, "gpio_elan_intr");
++ if (err < 0) {
++ dev_err(&client->dev,
++ "request gpio failed: %d\n", err);
++ return err;
++ }
++
++ /* elan touch init */
++ gpio_elan_cs = of_get_named_gpio(np, "gpio_elan_cs", 0);
++ if (!gpio_is_valid(gpio_elan_cs))
++ return -ENODEV;
++
++ err = devm_gpio_request_one(&client->dev, gpio_elan_cs,
++ GPIOF_OUT_INIT_HIGH, "gpio_elan_cs");
++ if (err < 0) {
++ dev_err(&client->dev,
++ "request gpio failed: %d\n", err);
++ return err;
++ }
++ gpio_set_value(gpio_elan_cs, 0);
++
++ gpio_elan_rst = of_get_named_gpio(np, "gpio_elan_rst", 0);
++ if (!gpio_is_valid(gpio_elan_rst))
++ return -ENODEV;
++
++ err = devm_gpio_request_one(&client->dev, gpio_elan_rst,
++ GPIOF_OUT_INIT_HIGH, "gpio_elan_rst");
++ if (err < 0) {
++ dev_err(&client->dev,
++ "request gpio failed: %d\n", err);
++ return err;
++ }
++ gpio_set_value(gpio_elan_rst, 0);
++ msleep(10);
++ gpio_set_value(gpio_elan_rst, 1);
++
++ gpio_set_value(gpio_elan_cs, 1);
++ msleep(100);
++
++ elan_wq = create_singlethread_workqueue("elan_wq");
++ if (!elan_wq) {
++ err = -ENOMEM;
++ goto fail;
++ }
++
++ elan_touch_data.client = client;
++ strlcpy(client->name, ELAN_TS_NAME, I2C_NAME_SIZE);
++
++ INIT_WORK(&elan_touch_data.work, elan_touch_work_func);
++
++ elan_touch_data.input = input_allocate_device();
++ if (elan_touch_data.input == NULL) {
++ err = -ENOMEM;
++ goto fail;
++ }
++
++ err = __elan_touch_init(client);
++ if (err < 0) {
++ dev_err(&client->dev, "elan - Read Hello Packet Failed\n");
++ goto fail;
++ }
++
++ elan_touch_data.input->name = ELAN_TS_NAME;
++ elan_touch_data.input->id.bustype = BUS_I2C;
++
++ set_bit(EV_SYN, elan_touch_data.input->evbit);
++
++ set_bit(EV_KEY, elan_touch_data.input->evbit);
++ set_bit(BTN_TOUCH, elan_touch_data.input->keybit);
++ set_bit(BTN_2, elan_touch_data.input->keybit);
++
++ set_bit(EV_ABS, elan_touch_data.input->evbit);
++ set_bit(ABS_X, elan_touch_data.input->absbit);
++ set_bit(ABS_Y, elan_touch_data.input->absbit);
++ set_bit(ABS_HAT0X, elan_touch_data.input->absbit);
++ set_bit(ABS_HAT0Y, elan_touch_data.input->absbit);
++
++ input_set_abs_params(elan_touch_data.input, ABS_X, 0, ELAN_USER_X_MAX,
++ 0, 0);
++ input_set_abs_params(elan_touch_data.input, ABS_Y, 0, ELAN_USER_Y_MAX,
++ 0, 0);
++ input_set_abs_params(elan_touch_data.input, ABS_HAT0X, 0,
++ ELAN_USER_X_MAX, 0, 0);
++ input_set_abs_params(elan_touch_data.input, ABS_HAT0Y, 0,
++ ELAN_USER_Y_MAX, 0, 0);
++
++ err = input_register_device(elan_touch_data.input);
++ if (err < 0)
++ goto fail;
++
++ elan_touch_register_interrupt(elan_touch_data.client);
++
++ return 0;
++
++fail:
++ input_free_device(elan_touch_data.input);
++ if (elan_wq)
++ destroy_workqueue(elan_wq);
++ return err;
++}
++
++static int elan_touch_remove(struct i2c_client *client)
++{
++ if (elan_wq)
++ destroy_workqueue(elan_wq);
++
++ input_unregister_device(elan_touch_data.input);
++
++ if (elan_touch_data.use_irq)
++ free_irq(client->irq, client);
++ else
++ hrtimer_cancel(&elan_touch_data.timer);
++ return 0;
++}
++
++/* -------------------------------------------------------------------- */
++static const struct i2c_device_id elan_touch_id[] = {
++ {"elan-touch", 0},
++ {}
++};
++
++static const struct of_device_id elan_dt_ids[] = {
++ {
++ .compatible = "elan,elan-touch",
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(of, elan_dt_ids);
++
++static int elan_suspend(struct device *dev)
++{
++ return 0;
++}
++
++static int elan_resume(struct device *dev)
++{
++ uint8_t buf[IDX_PACKET_SIZE] = { 0 };
++
++ if (0 == elan_touch_detect_int_level()) {
++ dev_dbg(dev, "Got touch during suspend period.\n");
++ /*
++ * if touch screen during suspend, recv and drop the
++ * data, then touch interrupt pin will return high after
++ * receving data.
++ */
++ elan_touch_recv_data(elan_touch_data.client, buf);
++ }
++
++ return 0;
++}
++
++static const struct dev_pm_ops elan_dev_pm_ops = {
++ .suspend = elan_suspend,
++ .resume = elan_resume,
++};
++
++static struct i2c_driver elan_touch_driver = {
++ .probe = elan_touch_probe,
++ .remove = elan_touch_remove,
++ .id_table = elan_touch_id,
++ .driver = {
++ .name = "elan-touch",
++ .owner = THIS_MODULE,
++ .of_match_table = elan_dt_ids,
++#ifdef CONFIG_PM
++ .pm = &elan_dev_pm_ops,
++#endif
++ },
++};
++
++static int __init elan_touch_init(void)
++{
++ return i2c_add_driver(&elan_touch_driver);
++}
++
++static void __exit elan_touch_exit(void)
++{
++ i2c_del_driver(&elan_touch_driver);
++}
++
++module_init(elan_touch_init);
++module_exit(elan_touch_exit);
++
++MODULE_AUTHOR("Stanley Zeng <stanley.zeng@emc.com.tw>");
++MODULE_DESCRIPTION("ELAN Touch Screen driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/input/touchscreen/Kconfig linux-linaro-stable-mx6/drivers/input/touchscreen/Kconfig
+--- linux-3.10.30.orig/drivers/input/touchscreen/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/touchscreen/Kconfig 2014-05-15 20:33:55.129993197 +0200
+@@ -235,6 +235,27 @@
+ To compile this driver as a module, choose M here: the
+ module will be called egalax_ts.
+
++config TOUCHSCREEN_EGALAX_SINGLE_TOUCH
++ bool "EETI eGalax touchscreen as single-touch"
++ default N
++ depends on TOUCHSCREEN_EGALAX
++ help
++ If you say yes here you get single-touch touchscreen support
++ on the eGalax I2C controller.
++ If you say "no", you'll get the normal multi-touch
++
++config TOUCHSCREEN_ELAN
++ tristate "ELAN touchscreen input driver"
++ depends on I2C
++ help
++ Say Y here if you have an I2C ELAN touchscreen
++ attached.
++
++ If unsure, say N.
++
++ To compile this driver as a module, choose M here: the
++ module will be called elan-touch.
++
+ config TOUCHSCREEN_FUJITSU
+ tristate "Fujitsu serial touchscreen"
+ select SERIO
+diff -Nur linux-3.10.30.orig/drivers/input/touchscreen/Makefile linux-linaro-stable-mx6/drivers/input/touchscreen/Makefile
+--- linux-3.10.30.orig/drivers/input/touchscreen/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/touchscreen/Makefile 2014-05-15 20:33:55.129993197 +0200
+@@ -27,6 +27,7 @@
+ obj-$(CONFIG_TOUCHSCREEN_HAMPSHIRE) += hampshire.o
+ obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o
+ obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o
++obj-$(CONFIG_TOUCHSCREEN_ELAN) += elan_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o
+ obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o
+diff -Nur linux-3.10.30.orig/drivers/input/touchscreen/max11801_ts.c linux-linaro-stable-mx6/drivers/input/touchscreen/max11801_ts.c
+--- linux-3.10.30.orig/drivers/input/touchscreen/max11801_ts.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/input/touchscreen/max11801_ts.c 2014-05-15 20:33:55.145993312 +0200
+@@ -2,7 +2,7 @@
+ * Driver for MAXI MAX11801 - A Resistive touch screen controller with
+ * i2c interface
+ *
+- * Copyright (C) 2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ * Author: Zhang Jiejing <jiejing.zhang@freescale.com>
+ *
+ * Based on mcs5000_ts.c
+@@ -39,6 +39,10 @@
+ #include <linux/input.h>
+ #include <linux/slab.h>
+ #include <linux/bitops.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
+
+ /* Register Address define */
+ #define GENERNAL_STATUS_REG 0x00
+@@ -54,13 +58,30 @@
+ #define AUX_MESURE_CONF_REG 0x0a
+ #define OP_MODE_CONF_REG 0x0b
+
++#define Panel_Setup_X (0x69 << 1)
++#define Panel_Setup_Y (0x6b << 1)
++
++#define XY_combined_measurement (0x70 << 1)
++#define X_measurement (0x78 << 1)
++#define Y_measurement (0x7a << 1)
++#define AUX_measurement (0x76 << 1)
++
+ /* FIFO is found only in max11800 and max11801 */
+ #define FIFO_RD_CMD (0x50 << 1)
+ #define MAX11801_FIFO_INT (1 << 2)
+ #define MAX11801_FIFO_OVERFLOW (1 << 3)
++#define MAX11801_EDGE_INT (1 << 1)
++
++#define FIFO_RD_X_MSB (0x52 << 1)
++#define FIFO_RD_X_LSB (0x53 << 1)
++#define FIFO_RD_Y_MSB (0x54 << 1)
++#define FIFO_RD_Y_LSB (0x55 << 1)
++#define FIFO_RD_AUX_MSB (0x5a << 1)
++#define FIFO_RD_AUX_LSB (0x5b << 1)
+
+ #define XY_BUFSIZE 4
+ #define XY_BUF_OFFSET 4
++#define AUX_BUFSIZE 2
+
+ #define MAX11801_MAX_X 0xfff
+ #define MAX11801_MAX_Y 0xfff
+@@ -85,6 +106,64 @@
+ struct input_dev *input_dev;
+ };
+
++static struct i2c_client *max11801_client;
++static unsigned int max11801_workmode;
++static u8 aux_buf[AUX_BUFSIZE];
++
++static int max11801_dcm_write_command(struct i2c_client *client, int command)
++{
++ return i2c_smbus_write_byte(client, command);
++}
++
++static u32 max11801_dcm_sample_aux(struct i2c_client *client)
++{
++ int ret;
++ int aux = 0;
++ u32 sample_data;
++
++ /* AUX_measurement */
++ max11801_dcm_write_command(client, AUX_measurement);
++ mdelay(5);
++ ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_AUX_MSB,
++ 1, &aux_buf[0]);
++ if (ret < 1) {
++ dev_err(&client->dev, "FIFO_RD_AUX_MSB read fails\n");
++ return ret;
++ }
++ mdelay(5);
++ ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_AUX_LSB,
++ 1, &aux_buf[1]);
++ if (ret < 1) {
++ dev_err(&client->dev, "FIFO_RD_AUX_LSB read fails\n");
++ return ret;
++ }
++
++ aux = (aux_buf[0] << 4) + (aux_buf[1] >> 4);
++ /*
++ * voltage = (9170*aux)/7371;
++ * voltage is (26.2*3150*aux)/(16.2*0xFFF)
++ * V(aux)=3150*sample/0xFFF,V(battery)=212*V(aux)/81
++ * sample_data = (14840*aux)/7371-1541;
++ */
++ sample_data = (14840 * aux) / 7371;
++
++ return sample_data;
++}
++
++u32 max11801_read_adc(void)
++{
++ u32 adc_data;
++
++ if (!max11801_client) {
++ pr_err("FAIL max11801_client not initialize\n");
++ return -1;
++ }
++ adc_data = max11801_dcm_sample_aux(max11801_client);
++
++ return adc_data;
++}
++EXPORT_SYMBOL_GPL(max11801_read_adc);
++
+ static u8 read_register(struct i2c_client *client, int addr)
+ {
+ /* XXX: The chip ignores LSB of register address */
+@@ -105,29 +184,62 @@
+ u8 buf[XY_BUFSIZE];
+ int x = -1;
+ int y = -1;
++ u8 command = FIFO_RD_X_MSB;
+
+ status = read_register(data->client, GENERNAL_STATUS_REG);
+-
+- if (status & (MAX11801_FIFO_INT | MAX11801_FIFO_OVERFLOW)) {
++ if ((!max11801_workmode && (status & (MAX11801_FIFO_INT |
++ MAX11801_FIFO_OVERFLOW))) || (max11801_workmode && (status &
++ MAX11801_EDGE_INT))) {
+ status = read_register(data->client, GENERNAL_STATUS_REG);
++ if (!max11801_workmode) {
++ /* ACM mode */
++ ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_CMD,
++ XY_BUFSIZE, buf);
++ /*
++ * We should get 4 bytes buffer that contains X,Y
++ * and event tag
++ */
++ if (ret < XY_BUFSIZE)
++ goto out;
++ } else {
++ /* DCM mode */
++ /* X = panel setup */
++ max11801_dcm_write_command(client, Panel_Setup_X);
++ /* X_measurement */
++ max11801_dcm_write_command(client, X_measurement);
++ for (i = 0; i < 2; i++) {
++ ret = i2c_smbus_read_i2c_block_data(client,
++ command, 1, &buf[i]);
++ if (ret < 1)
++ goto out;
++
++ command = FIFO_RD_X_LSB;
++ }
++
++ /* Y = panel setup */
++ max11801_dcm_write_command(client, Panel_Setup_Y);
++ /* Y_measurement */
++ max11801_dcm_write_command(client, Y_measurement);
++ command = FIFO_RD_Y_MSB;
++ for (i = 2; i < XY_BUFSIZE; i++) {
++ ret = i2c_smbus_read_i2c_block_data(client,
++ command, 1, &buf[i]);
++ if (ret < 1)
++ goto out;
+
+- ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_CMD,
+- XY_BUFSIZE, buf);
+-
+- /*
+- * We should get 4 bytes buffer that contains X,Y
+- * and event tag
+- */
+- if (ret < XY_BUFSIZE)
+- goto out;
++ command = FIFO_RD_Y_LSB;
++ }
++ }
+
+ for (i = 0; i < XY_BUFSIZE; i += XY_BUFSIZE / 2) {
+- if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_X_TAG)
++ if ((buf[i + 1] & MEASURE_TAG_MASK) ==
++ MEASURE_X_TAG)
+ x = (buf[i] << XY_BUF_OFFSET) +
+- (buf[i + 1] >> XY_BUF_OFFSET);
+- else if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_Y_TAG)
++ (buf[i + 1] >> XY_BUF_OFFSET);
++ else if ((buf[i + 1] & MEASURE_TAG_MASK) ==
++ MEASURE_Y_TAG)
+ y = (buf[i] << XY_BUF_OFFSET) +
+- (buf[i + 1] >> XY_BUF_OFFSET);
++ (buf[i + 1] >> XY_BUF_OFFSET);
+ }
+
+ if ((buf[1] & EVENT_TAG_MASK) != (buf[3] & EVENT_TAG_MASK))
+@@ -138,18 +250,17 @@
+ /* fall through */
+ case EVENT_MIDDLE:
+ input_report_abs(data->input_dev, ABS_X, x);
++ y = MAX11801_MAX_Y - y; /* Calibration */
+ input_report_abs(data->input_dev, ABS_Y, y);
+ input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1);
+ input_sync(data->input_dev);
+ break;
+-
+ case EVENT_RELEASE:
+ input_event(data->input_dev, EV_KEY, BTN_TOUCH, 0);
+ input_sync(data->input_dev);
+ break;
+-
+ case EVENT_FIFO_END:
+- break;
++ break;
+ }
+ }
+ out:
+@@ -160,18 +271,37 @@
+ {
+ struct i2c_client *client = data->client;
+
+- /* Average X,Y, take 16 samples, average eight media sample */
++ max11801_client = client;
++ /* Average X,Y, take 16 samples average eight media sample */
+ max11801_write_reg(client, MESURE_AVER_CONF_REG, 0xff);
+ /* X,Y panel setup time set to 20us */
+ max11801_write_reg(client, PANEL_SETUPTIME_CONF_REG, 0x11);
+- /* Rough pullup time (2uS), Fine pullup time (10us) */
++ /* Rough pullup time (2uS), Fine pullup time (10us) */
+ max11801_write_reg(client, TOUCH_DETECT_PULLUP_CONF_REG, 0x10);
+- /* Auto mode init period = 5ms , scan period = 5ms*/
++ /* Auto mode init period = 5ms, scan period = 5ms */
+ max11801_write_reg(client, AUTO_MODE_TIME_CONF_REG, 0xaa);
+ /* Aperture X,Y set to +- 4LSB */
+ max11801_write_reg(client, APERTURE_CONF_REG, 0x33);
+- /* Enable Power, enable Automode, enable Aperture, enable Average X,Y */
+- max11801_write_reg(client, OP_MODE_CONF_REG, 0x36);
++ /*
++ * Enable Power, enable Automode, enable Aperture,
++ * enable Average X,Y
++ */
++ if (!max11801_workmode)
++ max11801_write_reg(client, OP_MODE_CONF_REG, 0x36);
++ else {
++ max11801_write_reg(client, OP_MODE_CONF_REG, 0x16);
++ /*
++ * Delay initial=1ms, Sampling time 2us
++ * Averaging sample depth 2
++ * samples, Resolution 12bit
++ */
++ max11801_write_reg(client, AUX_MESURE_CONF_REG, 0x76);
++ /*
++ * Use edge interrupt with
++ * direct conversion mode
++ */
++ max11801_write_reg(client, GENERNAL_CONF_REG, 0xf3);
++ }
+ }
+
+ static int max11801_ts_probe(struct i2c_client *client,
+@@ -180,6 +310,7 @@
+ struct max11801_data *data;
+ struct input_dev *input_dev;
+ int error;
++ struct device_node *of_node = client->dev.of_node;
+
+ data = kzalloc(sizeof(struct max11801_data), GFP_KERNEL);
+ input_dev = input_allocate_device();
+@@ -203,11 +334,14 @@
+ input_set_abs_params(input_dev, ABS_Y, 0, MAX11801_MAX_Y, 0, 0);
+ input_set_drvdata(input_dev, data);
+
++ if (of_property_read_u32(of_node, "work-mode", &max11801_workmode))
++ max11801_workmode = *(int *)(client->dev).platform_data;
++
+ max11801_ts_phy_init(data);
+
+ error = request_threaded_irq(client->irq, NULL, max11801_ts_interrupt,
+- IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+- "max11801_ts", data);
++ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
++ "max11801_ts", data);
+ if (error) {
+ dev_err(&client->dev, "Failed to register interrupt\n");
+ goto err_free_mem;
+@@ -245,10 +379,17 @@
+ };
+ MODULE_DEVICE_TABLE(i2c, max11801_ts_id);
+
++static const struct of_device_id max11801_ts_dt_ids[] = {
++ { .compatible = "maxim,max11801", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, max11801_ts_dt_ids);
++
+ static struct i2c_driver max11801_ts_driver = {
+ .driver = {
+ .name = "max11801_ts",
+ .owner = THIS_MODULE,
++ .of_match_table = max11801_ts_dt_ids,
+ },
+ .id_table = max11801_ts_id,
+ .probe = max11801_ts_probe,
+diff -Nur linux-3.10.30.orig/drivers/irqchip/irq-gic.c linux-linaro-stable-mx6/drivers/irqchip/irq-gic.c
+--- linux-3.10.30.orig/drivers/irqchip/irq-gic.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/irqchip/irq-gic.c 2014-05-15 20:33:55.245994033 +0200
+@@ -41,6 +41,7 @@
+ #include <linux/slab.h>
+ #include <linux/irqchip/chained_irq.h>
+ #include <linux/irqchip/arm-gic.h>
++#include <trace/events/arm-ipi.h>
+
+ #include <asm/irq.h>
+ #include <asm/exception.h>
+@@ -253,10 +254,9 @@
+ if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
+ return -EINVAL;
+
++ raw_spin_lock(&irq_controller_lock);
+ mask = 0xff << shift;
+ bit = gic_cpu_map[cpu] << shift;
+-
+- raw_spin_lock(&irq_controller_lock);
+ val = readl_relaxed(reg) & ~mask;
+ writel_relaxed(val | bit, reg);
+ raw_spin_unlock(&irq_controller_lock);
+@@ -453,6 +453,12 @@
+ writel_relaxed(1, base + GIC_CPU_CTRL);
+ }
+
++void gic_cpu_if_down(void)
++{
++ void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
++ writel_relaxed(0, cpu_base + GIC_CPU_CTRL);
++}
++
+ #ifdef CONFIG_CPU_PM
+ /*
+ * Saves the GIC distributor registers during suspend or idle. Must be called
+@@ -646,11 +652,15 @@
+ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
+ {
+ int cpu;
+- unsigned long map = 0;
++ unsigned long flags, map = 0;
++
++ raw_spin_lock_irqsave(&irq_controller_lock, flags);
+
+ /* Convert our logical CPU mask into a physical one. */
+- for_each_cpu(cpu, mask)
++ for_each_cpu(cpu, mask) {
++ trace_arm_ipi_send(irq, cpu);
+ map |= gic_cpu_map[cpu];
++ }
+
+ /*
+ * Ensure that stores to Normal memory are visible to the
+@@ -660,7 +670,143 @@
+
+ /* this always happens on GIC0 */
+ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
++
++ raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
++}
++#endif
++
++#ifdef CONFIG_BL_SWITCHER
++/*
++ * gic_send_sgi - send a SGI directly to given CPU interface number
++ *
++ * cpu_id: the ID for the destination CPU interface
++ * irq: the IPI number to send a SGI for
++ */
++void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
++{
++ BUG_ON(cpu_id >= NR_GIC_CPU_IF);
++ cpu_id = 1 << cpu_id;
++ /* this always happens on GIC0 */
++ writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
++}
++
++/*
++ * gic_get_cpu_id - get the CPU interface ID for the specified CPU
++ *
++ * @cpu: the logical CPU number to get the GIC ID for.
++ *
++ * Return the CPU interface ID for the given logical CPU number,
++ * or -1 if the CPU number is too large or the interface ID is
++ * unknown (more than one bit set).
++ */
++int gic_get_cpu_id(unsigned int cpu)
++{
++ unsigned int cpu_bit;
++
++ if (cpu >= NR_GIC_CPU_IF)
++ return -1;
++ cpu_bit = gic_cpu_map[cpu];
++ if (cpu_bit & (cpu_bit - 1))
++ return -1;
++ return __ffs(cpu_bit);
++}
++
++/*
++ * gic_migrate_target - migrate IRQs to another PU interface
++ *
++ * @new_cpu_id: the CPU target ID to migrate IRQs to
++ *
++ * Migrate all peripheral interrupts with a target matching the current CPU
++ * to the interface corresponding to @new_cpu_id. The CPU interface mapping
++ * is also updated. Targets to other CPU interfaces are unchanged.
++ * This must be called with IRQs locally disabled.
++ */
++void gic_migrate_target(unsigned int new_cpu_id)
++{
++ unsigned int old_cpu_id, gic_irqs, gic_nr = 0;
++ void __iomem *dist_base;
++ int i, ror_val, cpu = smp_processor_id();
++ u32 val, old_mask, active_mask;
++
++ if (gic_nr >= MAX_GIC_NR)
++ BUG();
++
++ dist_base = gic_data_dist_base(&gic_data[gic_nr]);
++ if (!dist_base)
++ return;
++ gic_irqs = gic_data[gic_nr].gic_irqs;
++
++ old_cpu_id = __ffs(gic_cpu_map[cpu]);
++ old_mask = 0x01010101 << old_cpu_id;
++ ror_val = (old_cpu_id - new_cpu_id) & 31;
++
++ raw_spin_lock(&irq_controller_lock);
++
++ gic_cpu_map[cpu] = 1 << new_cpu_id;
++
++ for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
++ val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
++ active_mask = val & old_mask;
++ if (active_mask) {
++ val &= ~active_mask;
++ val |= ror32(active_mask, ror_val);
++ writel_relaxed(val, dist_base + GIC_DIST_TARGET + i * 4);
++ }
++ }
++
++ raw_spin_unlock(&irq_controller_lock);
++
++ /*
++ * Now let's migrate and clear any potential SGIs that might be
++ * pending for us (old_cpu_id). Since GIC_DIST_SGI_PENDING_SET
++ * is a banked register, we can only forward the SGI using
++ * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
++ * doesn't use that information anyway.
++ *
++ * For the same reason we do not adjust SGI source information
++ * for previously sent SGIs by us to other CPUs either.
++ */
++ for (i = 0; i < 16; i += 4) {
++ int j;
++ val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
++ if (!val)
++ continue;
++ writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
++ for (j = i; j < i + 4; j++) {
++ if (val & 0xff)
++ writel_relaxed((1 << (new_cpu_id + 16)) | j,
++ dist_base + GIC_DIST_SOFTINT);
++ val >>= 8;
++ }
++ }
+ }
++
++/*
++ * gic_get_sgir_physaddr - get the physical address for the SGI register
++ *
++ * REturn the physical address of the SGI register to be used
++ * by some early assembly code when the kernel is not yet available.
++ */
++static unsigned long gic_dist_physaddr;
++
++unsigned long gic_get_sgir_physaddr(void)
++{
++ if (!gic_dist_physaddr)
++ return 0;
++ return gic_dist_physaddr + GIC_DIST_SOFTINT;
++}
++
++void __init gic_init_physaddr(struct device_node *node)
++{
++ struct resource res;
++ if (of_address_to_resource(node, 0, &res) == 0) {
++ gic_dist_physaddr = res.start;
++ pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
++ }
++}
++
++#else
++#define gic_init_physaddr(node) do { } while(0)
+ #endif
+
+ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
+@@ -844,6 +990,8 @@
+ percpu_offset = 0;
+
+ gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
++ if (!gic_cnt)
++ gic_init_physaddr(node);
+
+ if (parent) {
+ irq = irq_of_parse_and_map(node, 0);
+diff -Nur linux-3.10.30.orig/drivers/Kconfig linux-linaro-stable-mx6/drivers/Kconfig
+--- linux-3.10.30.orig/drivers/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/Kconfig 2014-05-15 20:33:44.917919586 +0200
+@@ -98,6 +98,8 @@
+
+ source "drivers/memstick/Kconfig"
+
++source "drivers/mxc/Kconfig"
++
+ source "drivers/leds/Kconfig"
+
+ source "drivers/accessibility/Kconfig"
+@@ -166,4 +168,6 @@
+
+ source "drivers/reset/Kconfig"
+
++source "drivers/gator/Kconfig"
++
+ endmenu
+diff -Nur linux-3.10.30.orig/drivers/leds/leds-pwm.c linux-linaro-stable-mx6/drivers/leds/leds-pwm.c
+--- linux-3.10.30.orig/drivers/leds/leds-pwm.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/leds/leds-pwm.c 2014-05-15 20:33:55.805998069 +0200
+@@ -67,8 +67,13 @@
+ container_of(led_cdev, struct led_pwm_data, cdev);
+ unsigned int max = led_dat->cdev.max_brightness;
+ unsigned int period = led_dat->period;
++ int duty;
+
+- led_dat->duty = brightness * period / max;
++ duty = brightness * period / max;
++ if (led_dat->active_low)
++ duty = period - duty;
++
++ led_dat->duty = duty;
+
+ if (led_dat->can_sleep)
+ schedule_work(&led_dat->work);
+@@ -102,6 +107,10 @@
+ for_each_child_of_node(node, child) {
+ struct led_pwm_data *led_dat = &priv->leds[priv->num_leds];
+
++ led_dat->cdev.brightness_set = led_pwm_set;
++ led_dat->cdev.brightness = LED_OFF;
++ led_dat->cdev.flags |= LED_CORE_SUSPENDRESUME;
++
+ led_dat->cdev.name = of_get_property(child, "label",
+ NULL) ? : child->name;
+
+@@ -118,10 +127,9 @@
+ "linux,default-trigger", NULL);
+ of_property_read_u32(child, "max-brightness",
+ &led_dat->cdev.max_brightness);
+-
+- led_dat->cdev.brightness_set = led_pwm_set;
+- led_dat->cdev.brightness = LED_OFF;
+- led_dat->cdev.flags |= LED_CORE_SUSPENDRESUME;
++ of_property_read_u32(child, "default-brightness",
++ &led_dat->cdev.brightness);
++ led_dat->active_low = of_property_read_bool(child, "active-low");
+
+ led_dat->can_sleep = pwm_can_sleep(led_dat->pwm);
+ if (led_dat->can_sleep)
+diff -Nur linux-3.10.30.orig/drivers/Makefile linux-linaro-stable-mx6/drivers/Makefile
+--- linux-3.10.30.orig/drivers/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/Makefile 2014-05-15 20:33:44.917919586 +0200
+@@ -109,6 +109,7 @@
+ obj-$(CONFIG_CPU_FREQ) += cpufreq/
+ obj-$(CONFIG_CPU_IDLE) += cpuidle/
+ obj-y += mmc/
++obj-$(CONFIG_ARCH_MXC) += mxc/
+ obj-$(CONFIG_MEMSTICK) += memstick/
+ obj-y += leds/
+ obj-$(CONFIG_INFINIBAND) += infiniband/
+@@ -152,3 +153,5 @@
+ obj-$(CONFIG_VME_BUS) += vme/
+ obj-$(CONFIG_IPACK_BUS) += ipack/
+ obj-$(CONFIG_NTB) += ntb/
++
++obj-$(CONFIG_GATOR) += gator/
+diff -Nur linux-3.10.30.orig/drivers/media/platform/Kconfig linux-linaro-stable-mx6/drivers/media/platform/Kconfig
+--- linux-3.10.30.orig/drivers/media/platform/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/Kconfig 2014-05-15 20:33:56.994006630 +0200
+@@ -121,6 +121,21 @@
+ To compile this driver as a module, choose M here: the module
+ will be called s3c-camif.
+
++config VIDEO_MXC_OUTPUT
++ tristate "MXC Video For Linux Video Output"
++ depends on VIDEO_DEV && ARCH_MXC && FB_MXC
++ select VIDEOBUF_DMA_CONTIG
++ ---help---
++ This is the video4linux2 output driver based on MXC module.
++
++config VIDEO_MXC_CAPTURE
++ tristate "MXC Video For Linux Video Capture"
++ depends on VIDEO_V4L2 && VIDEO_V4L2_INT_DEVICE
++ ---help---
++ This is the video4linux2 capture driver based on i.MX video-in module.
++
++source "drivers/media/platform/mxc/capture/Kconfig"
++source "drivers/media/platform/mxc/output/Kconfig"
+ source "drivers/media/platform/soc_camera/Kconfig"
+ source "drivers/media/platform/exynos4-is/Kconfig"
+ source "drivers/media/platform/s5p-tv/Kconfig"
+diff -Nur linux-3.10.30.orig/drivers/media/platform/Makefile linux-linaro-stable-mx6/drivers/media/platform/Makefile
+--- linux-3.10.30.orig/drivers/media/platform/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/Makefile 2014-05-15 20:33:56.994006630 +0200
+@@ -50,4 +50,7 @@
+
+ obj-$(CONFIG_ARCH_OMAP) += omap/
+
++obj-$(CONFIG_VIDEO_MXC_CAPTURE) += mxc/capture/
++obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mxc/output/
++
+ ccflags-y += -I$(srctree)/drivers/media/i2c
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/adv7180.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/adv7180.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/adv7180.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/adv7180.c 2014-05-15 20:33:57.110007467 +0200
+@@ -0,0 +1,1344 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file adv7180.c
++ *
++ * @brief Analog Device ADV7180 video decoder functions
++ *
++ * @ingroup Camera
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-chip-ident.h>
++#include <media/v4l2-int-device.h>
++#include "mxc_v4l2_capture.h"
++
++#define ADV7180_VOLTAGE_ANALOG 1800000
++#define ADV7180_VOLTAGE_DIGITAL_CORE 1800000
++#define ADV7180_VOLTAGE_DIGITAL_IO 3300000
++#define ADV7180_VOLTAGE_PLL 1800000
++
++static struct regulator *dvddio_regulator;
++static struct regulator *dvdd_regulator;
++static struct regulator *avdd_regulator;
++static struct regulator *pvdd_regulator;
++static int pwn_gpio;
++
++static int adv7180_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *id);
++static int adv7180_detach(struct i2c_client *client);
++
++static const struct i2c_device_id adv7180_id[] = {
++ {"adv7180", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, adv7180_id);
++
++static struct i2c_driver adv7180_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "adv7180",
++ },
++ .probe = adv7180_probe,
++ .remove = adv7180_detach,
++ .id_table = adv7180_id,
++};
++
++/*!
++ * Maintains the information on the current state of the sensor.
++ */
++struct sensor {
++ struct sensor_data sen;
++ v4l2_std_id std_id;
++} adv7180_data;
++
++
++/*! List of input video formats supported. The video formats is corresponding
++ * with v4l2 id in video_fmt_t
++ */
++typedef enum {
++ ADV7180_NTSC = 0, /*!< Locked on (M) NTSC video signal. */
++ ADV7180_PAL, /*!< (B, G, H, I, N)PAL video signal. */
++ ADV7180_NOT_LOCKED, /*!< Not locked on a signal. */
++} video_fmt_idx;
++
++/*! Number of video standards supported (including 'not locked' signal). */
++#define ADV7180_STD_MAX (ADV7180_PAL + 1)
++
++/*! Video format structure. */
++typedef struct {
++ int v4l2_id; /*!< Video for linux ID. */
++ char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */
++ u16 raw_width; /*!< Raw width. */
++ u16 raw_height; /*!< Raw height. */
++ u16 active_width; /*!< Active width. */
++ u16 active_height; /*!< Active height. */
++} video_fmt_t;
++
++/*! Description of video formats supported.
++ *
++ * PAL: raw=720x625, active=720x576.
++ * NTSC: raw=720x525, active=720x480.
++ */
++static video_fmt_t video_fmts[] = {
++ { /*! NTSC */
++ .v4l2_id = V4L2_STD_NTSC,
++ .name = "NTSC",
++ .raw_width = 720, /* SENS_FRM_WIDTH */
++ .raw_height = 525, /* SENS_FRM_HEIGHT */
++ .active_width = 720, /* ACT_FRM_WIDTH plus 1 */
++ .active_height = 480, /* ACT_FRM_WIDTH plus 1 */
++ },
++ { /*! (B, G, H, I, N) PAL */
++ .v4l2_id = V4L2_STD_PAL,
++ .name = "PAL",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ },
++ { /*! Unlocked standard */
++ .v4l2_id = V4L2_STD_ALL,
++ .name = "Autodetect",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ },
++};
++
++/*!* Standard index of ADV7180. */
++static video_fmt_idx video_idx = ADV7180_PAL;
++
++/*! @brief This mutex is used to provide mutual exclusion.
++ *
++ * Create a mutex that can be used to provide mutually exclusive
++ * read/write access to the globally accessible data structures
++ * and variables that were defined above.
++ */
++static DEFINE_MUTEX(mutex);
++
++#define IF_NAME "adv7180"
++#define ADV7180_INPUT_CTL 0x00 /* Input Control */
++#define ADV7180_STATUS_1 0x10 /* Status #1 */
++#define ADV7180_BRIGHTNESS 0x0a /* Brightness */
++#define ADV7180_IDENT 0x11 /* IDENT */
++#define ADV7180_VSYNC_FIELD_CTL_1 0x31 /* VSYNC Field Control #1 */
++#define ADV7180_MANUAL_WIN_CTL 0x3d /* Manual Window Control */
++#define ADV7180_SD_SATURATION_CB 0xe3 /* SD Saturation Cb */
++#define ADV7180_SD_SATURATION_CR 0xe4 /* SD Saturation Cr */
++#define ADV7180_PWR_MNG 0x0f /* Power Management */
++
++/* supported controls */
++/* This hasn't been fully implemented yet.
++ * This is how it should work, though. */
++static struct v4l2_queryctrl adv7180_qctrl[] = {
++ {
++ .id = V4L2_CID_BRIGHTNESS,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ .name = "Brightness",
++ .minimum = 0, /* check this value */
++ .maximum = 255, /* check this value */
++ .step = 1, /* check this value */
++ .default_value = 127, /* check this value */
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_SATURATION,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ .name = "Saturation",
++ .minimum = 0, /* check this value */
++ .maximum = 255, /* check this value */
++ .step = 0x1, /* check this value */
++ .default_value = 127, /* check this value */
++ .flags = 0,
++ }
++};
++
++static inline void adv7180_power_down(int enable)
++{
++ gpio_set_value_cansleep(pwn_gpio, !enable);
++ msleep(2);
++}
++
++static int adv7180_regulator_enable(struct device *dev)
++{
++ int ret = 0;
++
++ dvddio_regulator = devm_regulator_get(dev, "DOVDD");
++
++ if (!IS_ERR(dvddio_regulator)) {
++ regulator_set_voltage(dvddio_regulator,
++ ADV7180_VOLTAGE_DIGITAL_IO,
++ ADV7180_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(dvddio_regulator);
++ if (ret) {
++ dev_err(dev, "set io voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set io voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get io voltage\n");
++ }
++
++ dvdd_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(dvdd_regulator)) {
++ regulator_set_voltage(dvdd_regulator,
++ ADV7180_VOLTAGE_DIGITAL_CORE,
++ ADV7180_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(dvdd_regulator);
++ if (ret) {
++ dev_err(dev, "set core voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set core voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get core voltage\n");
++ }
++
++ avdd_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(avdd_regulator)) {
++ regulator_set_voltage(avdd_regulator,
++ ADV7180_VOLTAGE_ANALOG,
++ ADV7180_VOLTAGE_ANALOG);
++ ret = regulator_enable(avdd_regulator);
++ if (ret) {
++ dev_err(dev, "set analog voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set analog voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get analog voltage\n");
++ }
++
++ pvdd_regulator = devm_regulator_get(dev, "PVDD");
++ if (!IS_ERR(pvdd_regulator)) {
++ regulator_set_voltage(pvdd_regulator,
++ ADV7180_VOLTAGE_PLL,
++ ADV7180_VOLTAGE_PLL);
++ ret = regulator_enable(pvdd_regulator);
++ if (ret) {
++ dev_err(dev, "set pll voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set pll voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get pll voltage\n");
++ }
++
++ return ret;
++}
++
++
++/***********************************************************************
++ * I2C transfert.
++ ***********************************************************************/
++
++/*! Read one register from a ADV7180 i2c slave device.
++ *
++ * @param *reg register in the device we wish to access.
++ *
++ * @return 0 if success, an error code otherwise.
++ */
++static inline int adv7180_read(u8 reg)
++{
++ int val;
++
++ val = i2c_smbus_read_byte_data(adv7180_data.sen.i2c_client, reg);
++ if (val < 0) {
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "%s:read reg error: reg=%2x\n", __func__, reg);
++ return -1;
++ }
++ return val;
++}
++
++/*! Write one register of a ADV7180 i2c slave device.
++ *
++ * @param *reg register in the device we wish to access.
++ *
++ * @return 0 if success, an error code otherwise.
++ */
++static int adv7180_write_reg(u8 reg, u8 val)
++{
++ s32 ret;
++
++ ret = i2c_smbus_write_byte_data(adv7180_data.sen.i2c_client, reg, val);
++ if (ret < 0) {
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
++ reg, val);
++ return -1;
++ }
++ return 0;
++}
++
++/***********************************************************************
++ * mxc_v4l2_capture interface.
++ ***********************************************************************/
++
++/*!
++ * Return attributes of current video standard.
++ * Since this device autodetects the current standard, this function also
++ * sets the values that need to be changed if the standard changes.
++ * There is no set std equivalent function.
++ *
++ * @return None.
++ */
++static void adv7180_get_std(v4l2_std_id *std)
++{
++ int tmp;
++ int idx;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180_get_std\n");
++
++ /* Read the AD_RESULT to get the detect output video standard */
++ tmp = adv7180_read(ADV7180_STATUS_1) & 0x70;
++
++ mutex_lock(&mutex);
++ if (tmp == 0x40) {
++ /* PAL */
++ *std = V4L2_STD_PAL;
++ idx = ADV7180_PAL;
++ } else if (tmp == 0) {
++ /*NTSC*/
++ *std = V4L2_STD_NTSC;
++ idx = ADV7180_NTSC;
++ } else {
++ *std = V4L2_STD_ALL;
++ idx = ADV7180_NOT_LOCKED;
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "Got invalid video standard!\n");
++ }
++ mutex_unlock(&mutex);
++
++ /* This assumes autodetect which this device uses. */
++ if (*std != adv7180_data.std_id) {
++ video_idx = idx;
++ adv7180_data.std_id = *std;
++ adv7180_data.sen.pix.width = video_fmts[video_idx].raw_width;
++ adv7180_data.sen.pix.height = video_fmts[video_idx].raw_height;
++ }
++}
++
++/***********************************************************************
++ * IOCTL Functions from v4l2_int_ioctl_desc.
++ ***********************************************************************/
++
++/*!
++ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num
++ * s: pointer to standard V4L2 device structure
++ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure
++ *
++ * Gets slave interface parameters.
++ * Calculates the required xclk value to support the requested
++ * clock parameters in p. This value is returned in the p
++ * parameter.
++ *
++ * vidioc_int_g_ifparm returns platform-specific information about the
++ * interface settings used by the sensor.
++ *
++ * Called on open.
++ */
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_g_ifparm\n");
++
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ /* Initialize structure to 0s then set any non-0 values. */
++ memset(p, 0, sizeof(*p));
++ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.nobt_hs_inv = 1;
++ p->u.bt656.bt_sync_correct = 1;
++
++ /* ADV7180 has a dedicated clock so no clock settings needed. */
++
++ return 0;
++}
++
++/*!
++ * Sets the camera power.
++ *
++ * s pointer to the camera device
++ * on if 1, power is to be turned on. 0 means power is to be turned off
++ *
++ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num
++ * @s: pointer to standard V4L2 device structure
++ * @on: power state to which device is to be set
++ *
++ * Sets devices power state to requrested state, if possible.
++ * This is called on open, close, suspend and resume.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor *sensor = s->priv;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_s_power\n");
++
++ if (on && !sensor->sen.on) {
++ if (adv7180_write_reg(ADV7180_PWR_MNG, 0x04) != 0)
++ return -EIO;
++
++ /*
++ * FIXME:Additional 400ms to wait the chip to be stable?
++ * This is a workaround for preview scrolling issue.
++ */
++ msleep(400);
++ } else if (!on && sensor->sen.on) {
++ if (adv7180_write_reg(ADV7180_PWR_MNG, 0x24) != 0)
++ return -EIO;
++ }
++
++ sensor->sen.on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_g_parm\n");
++
++ switch (a->type) {
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->sen.streamcap.capability;
++ cparm->timeperframe = sensor->sen.streamcap.timeperframe;
++ cparm->capturemode = sensor->sen.streamcap.capturemode;
++ break;
++
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ break;
++
++ default:
++ pr_debug("ioctl_g_parm:type is unknown %d\n", a->type);
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ *
++ * This driver cannot change these settings.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_s_parm\n");
++
++ switch (a->type) {
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor *sensor = s->priv;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_g_fmt_cap\n");
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" Returning size of %dx%d\n",
++ sensor->sen.pix.width, sensor->sen.pix.height);
++ f->fmt.pix = sensor->sen.pix;
++ break;
++
++ case V4L2_BUF_TYPE_PRIVATE: {
++ v4l2_std_id std;
++ adv7180_get_std(&std);
++ f->fmt.pix.pixelformat = (u32)std;
++ }
++ break;
++
++ default:
++ f->fmt.pix = sensor->sen.pix;
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control information
++ * from the video_control[] array. Otherwise, returns -EINVAL if the
++ * control is not supported.
++ */
++static int ioctl_queryctrl(struct v4l2_int_device *s,
++ struct v4l2_queryctrl *qc)
++{
++ int i;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_queryctrl\n");
++
++ for (i = 0; i < ARRAY_SIZE(adv7180_qctrl); i++)
++ if (qc->id && qc->id == adv7180_qctrl[i].id) {
++ memcpy(qc, &(adv7180_qctrl[i]),
++ sizeof(*qc));
++ return 0;
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++ int sat = 0;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_g_ctrl\n");
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_BRIGHTNESS\n");
++ adv7180_data.sen.brightness = adv7180_read(ADV7180_BRIGHTNESS);
++ vc->value = adv7180_data.sen.brightness;
++ break;
++ case V4L2_CID_CONTRAST:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_CONTRAST\n");
++ vc->value = adv7180_data.sen.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_SATURATION\n");
++ sat = adv7180_read(ADV7180_SD_SATURATION_CB);
++ adv7180_data.sen.saturation = sat;
++ vc->value = adv7180_data.sen.saturation;
++ break;
++ case V4L2_CID_HUE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_HUE\n");
++ vc->value = adv7180_data.sen.hue;
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_AUTO_WHITE_BALANCE\n");
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_DO_WHITE_BALANCE\n");
++ break;
++ case V4L2_CID_RED_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_RED_BALANCE\n");
++ vc->value = adv7180_data.sen.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_BLUE_BALANCE\n");
++ vc->value = adv7180_data.sen.blue;
++ break;
++ case V4L2_CID_GAMMA:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_GAMMA\n");
++ break;
++ case V4L2_CID_EXPOSURE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_EXPOSURE\n");
++ vc->value = adv7180_data.sen.ae_mode;
++ break;
++ case V4L2_CID_AUTOGAIN:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_AUTOGAIN\n");
++ break;
++ case V4L2_CID_GAIN:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_GAIN\n");
++ break;
++ case V4L2_CID_HFLIP:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_HFLIP\n");
++ break;
++ case V4L2_CID_VFLIP:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_VFLIP\n");
++ break;
++ default:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " Default case\n");
++ vc->value = 0;
++ ret = -EPERM;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++ u8 tmp;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_s_ctrl\n");
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_BRIGHTNESS\n");
++ tmp = vc->value;
++ adv7180_write_reg(ADV7180_BRIGHTNESS, tmp);
++ adv7180_data.sen.brightness = vc->value;
++ break;
++ case V4L2_CID_CONTRAST:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_CONTRAST\n");
++ break;
++ case V4L2_CID_SATURATION:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_SATURATION\n");
++ tmp = vc->value;
++ adv7180_write_reg(ADV7180_SD_SATURATION_CB, tmp);
++ adv7180_write_reg(ADV7180_SD_SATURATION_CR, tmp);
++ adv7180_data.sen.saturation = vc->value;
++ break;
++ case V4L2_CID_HUE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_HUE\n");
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_AUTO_WHITE_BALANCE\n");
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_DO_WHITE_BALANCE\n");
++ break;
++ case V4L2_CID_RED_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_RED_BALANCE\n");
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_BLUE_BALANCE\n");
++ break;
++ case V4L2_CID_GAMMA:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_GAMMA\n");
++ break;
++ case V4L2_CID_EXPOSURE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_EXPOSURE\n");
++ break;
++ case V4L2_CID_AUTOGAIN:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_AUTOGAIN\n");
++ break;
++ case V4L2_CID_GAIN:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_GAIN\n");
++ break;
++ case V4L2_CID_HFLIP:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_HFLIP\n");
++ break;
++ case V4L2_CID_VFLIP:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_VFLIP\n");
++ break;
++ default:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " Default case\n");
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index >= 1)
++ return -EINVAL;
++
++ fsize->discrete.width = video_fmts[video_idx].active_width;
++ fsize->discrete.height = video_fmts[video_idx].active_height;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
++ "adv7180_decoder");
++ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_ADV7180;
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_init\n");
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_dev_init\n");
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module.
++ */
++static struct v4l2_int_ioctl_desc adv7180_ioctl_desc[] = {
++
++ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init},
++
++ /*!
++ * Delinitialise the dev. at slave detach.
++ * The complement of ioctl_dev_init.
++ */
++/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */
++
++ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power},
++ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm},
++/* {vidioc_int_g_needs_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
++/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
++ {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init},
++
++ /*!
++ * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
++ */
++/* {vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */
++
++ /*!
++ * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type.
++ * This ioctl is used to negotiate the image capture size and
++ * pixel format without actually making it take effect.
++ */
++/* {vidioc_int_try_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
++
++ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap},
++
++ /*!
++ * If the requested format is supported, configures the HW to use that
++ * format, returns error code if format not supported or HW can't be
++ * correctly configured.
++ */
++/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */
++
++ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm},
++ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm},
++ {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl},
++ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl},
++ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl},
++ {vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
++ {vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *)ioctl_g_chip_ident},
++};
++
++static struct v4l2_int_slave adv7180_slave = {
++ .ioctls = adv7180_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(adv7180_ioctl_desc),
++};
++
++static struct v4l2_int_device adv7180_int_device = {
++ .module = THIS_MODULE,
++ .name = "adv7180",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &adv7180_slave,
++ },
++};
++
++
++/***********************************************************************
++ * I2C client and driver.
++ ***********************************************************************/
++
++/*! ADV7180 Reset function.
++ *
++ * @return None.
++ */
++static void adv7180_hard_reset(bool cvbs)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "In adv7180:adv7180_hard_reset\n");
++
++ if (cvbs) {
++ /* Set CVBS input on AIN1 */
++ adv7180_write_reg(ADV7180_INPUT_CTL, 0x00);
++ } else {
++ /*
++ * Set YPbPr input on AIN1,4,5 and normal
++ * operations(autodection of all stds).
++ */
++ adv7180_write_reg(ADV7180_INPUT_CTL, 0x09);
++ }
++
++ /* Datasheet recommends */
++ adv7180_write_reg(0x01, 0xc8);
++ adv7180_write_reg(0x02, 0x04);
++ adv7180_write_reg(0x03, 0x00);
++ adv7180_write_reg(0x04, 0x45);
++ adv7180_write_reg(0x05, 0x00);
++ adv7180_write_reg(0x06, 0x02);
++ adv7180_write_reg(0x07, 0x7F);
++ adv7180_write_reg(0x08, 0x80);
++ adv7180_write_reg(0x0A, 0x00);
++ adv7180_write_reg(0x0B, 0x00);
++ adv7180_write_reg(0x0C, 0x36);
++ adv7180_write_reg(0x0D, 0x7C);
++ adv7180_write_reg(0x0E, 0x00);
++ adv7180_write_reg(0x0F, 0x00);
++ adv7180_write_reg(0x13, 0x00);
++ adv7180_write_reg(0x14, 0x12);
++ adv7180_write_reg(0x15, 0x00);
++ adv7180_write_reg(0x16, 0x00);
++ adv7180_write_reg(0x17, 0x01);
++ adv7180_write_reg(0x18, 0x93);
++ adv7180_write_reg(0xF1, 0x19);
++ adv7180_write_reg(0x1A, 0x00);
++ adv7180_write_reg(0x1B, 0x00);
++ adv7180_write_reg(0x1C, 0x00);
++ adv7180_write_reg(0x1D, 0x40);
++ adv7180_write_reg(0x1E, 0x00);
++ adv7180_write_reg(0x1F, 0x00);
++ adv7180_write_reg(0x20, 0x00);
++ adv7180_write_reg(0x21, 0x00);
++ adv7180_write_reg(0x22, 0x00);
++ adv7180_write_reg(0x23, 0xC0);
++ adv7180_write_reg(0x24, 0x00);
++ adv7180_write_reg(0x25, 0x00);
++ adv7180_write_reg(0x26, 0x00);
++ adv7180_write_reg(0x27, 0x58);
++ adv7180_write_reg(0x28, 0x00);
++ adv7180_write_reg(0x29, 0x00);
++ adv7180_write_reg(0x2A, 0x00);
++ adv7180_write_reg(0x2B, 0xE1);
++ adv7180_write_reg(0x2C, 0xAE);
++ adv7180_write_reg(0x2D, 0xF4);
++ adv7180_write_reg(0x2E, 0x00);
++ adv7180_write_reg(0x2F, 0xF0);
++ adv7180_write_reg(0x30, 0x00);
++ adv7180_write_reg(0x31, 0x12);
++ adv7180_write_reg(0x32, 0x41);
++ adv7180_write_reg(0x33, 0x84);
++ adv7180_write_reg(0x34, 0x00);
++ adv7180_write_reg(0x35, 0x02);
++ adv7180_write_reg(0x36, 0x00);
++ adv7180_write_reg(0x37, 0x01);
++ adv7180_write_reg(0x38, 0x80);
++ adv7180_write_reg(0x39, 0xC0);
++ adv7180_write_reg(0x3A, 0x10);
++ adv7180_write_reg(0x3B, 0x05);
++ adv7180_write_reg(0x3C, 0x58);
++ adv7180_write_reg(0x3D, 0xB2);
++ adv7180_write_reg(0x3E, 0x64);
++ adv7180_write_reg(0x3F, 0xE4);
++ adv7180_write_reg(0x40, 0x90);
++ adv7180_write_reg(0x41, 0x01);
++ adv7180_write_reg(0x42, 0x7E);
++ adv7180_write_reg(0x43, 0xA4);
++ adv7180_write_reg(0x44, 0xFF);
++ adv7180_write_reg(0x45, 0xB6);
++ adv7180_write_reg(0x46, 0x12);
++ adv7180_write_reg(0x48, 0x00);
++ adv7180_write_reg(0x49, 0x00);
++ adv7180_write_reg(0x4A, 0x00);
++ adv7180_write_reg(0x4B, 0x00);
++ adv7180_write_reg(0x4C, 0x00);
++ adv7180_write_reg(0x4D, 0xEF);
++ adv7180_write_reg(0x4E, 0x08);
++ adv7180_write_reg(0x4F, 0x08);
++ adv7180_write_reg(0x50, 0x08);
++ adv7180_write_reg(0x51, 0x24);
++ adv7180_write_reg(0x52, 0x0B);
++ adv7180_write_reg(0x53, 0x4E);
++ adv7180_write_reg(0x54, 0x80);
++ adv7180_write_reg(0x55, 0x00);
++ adv7180_write_reg(0x56, 0x10);
++ adv7180_write_reg(0x57, 0x00);
++ adv7180_write_reg(0x58, 0x00);
++ adv7180_write_reg(0x59, 0x00);
++ adv7180_write_reg(0x5A, 0x00);
++ adv7180_write_reg(0x5B, 0x00);
++ adv7180_write_reg(0x5C, 0x00);
++ adv7180_write_reg(0x5D, 0x00);
++ adv7180_write_reg(0x5E, 0x00);
++ adv7180_write_reg(0x5F, 0x00);
++ adv7180_write_reg(0x60, 0x00);
++ adv7180_write_reg(0x61, 0x00);
++ adv7180_write_reg(0x62, 0x20);
++ adv7180_write_reg(0x63, 0x00);
++ adv7180_write_reg(0x64, 0x00);
++ adv7180_write_reg(0x65, 0x00);
++ adv7180_write_reg(0x66, 0x00);
++ adv7180_write_reg(0x67, 0x03);
++ adv7180_write_reg(0x68, 0x01);
++ adv7180_write_reg(0x69, 0x00);
++ adv7180_write_reg(0x6A, 0x00);
++ adv7180_write_reg(0x6B, 0xC0);
++ adv7180_write_reg(0x6C, 0x00);
++ adv7180_write_reg(0x6D, 0x00);
++ adv7180_write_reg(0x6E, 0x00);
++ adv7180_write_reg(0x6F, 0x00);
++ adv7180_write_reg(0x70, 0x00);
++ adv7180_write_reg(0x71, 0x00);
++ adv7180_write_reg(0x72, 0x00);
++ adv7180_write_reg(0x73, 0x10);
++ adv7180_write_reg(0x74, 0x04);
++ adv7180_write_reg(0x75, 0x01);
++ adv7180_write_reg(0x76, 0x00);
++ adv7180_write_reg(0x77, 0x3F);
++ adv7180_write_reg(0x78, 0xFF);
++ adv7180_write_reg(0x79, 0xFF);
++ adv7180_write_reg(0x7A, 0xFF);
++ adv7180_write_reg(0x7B, 0x1E);
++ adv7180_write_reg(0x7C, 0xC0);
++ adv7180_write_reg(0x7D, 0x00);
++ adv7180_write_reg(0x7E, 0x00);
++ adv7180_write_reg(0x7F, 0x00);
++ adv7180_write_reg(0x80, 0x00);
++ adv7180_write_reg(0x81, 0xC0);
++ adv7180_write_reg(0x82, 0x04);
++ adv7180_write_reg(0x83, 0x00);
++ adv7180_write_reg(0x84, 0x0C);
++ adv7180_write_reg(0x85, 0x02);
++ adv7180_write_reg(0x86, 0x03);
++ adv7180_write_reg(0x87, 0x63);
++ adv7180_write_reg(0x88, 0x5A);
++ adv7180_write_reg(0x89, 0x08);
++ adv7180_write_reg(0x8A, 0x10);
++ adv7180_write_reg(0x8B, 0x00);
++ adv7180_write_reg(0x8C, 0x40);
++ adv7180_write_reg(0x8D, 0x00);
++ adv7180_write_reg(0x8E, 0x40);
++ adv7180_write_reg(0x8F, 0x00);
++ adv7180_write_reg(0x90, 0x00);
++ adv7180_write_reg(0x91, 0x50);
++ adv7180_write_reg(0x92, 0x00);
++ adv7180_write_reg(0x93, 0x00);
++ adv7180_write_reg(0x94, 0x00);
++ adv7180_write_reg(0x95, 0x00);
++ adv7180_write_reg(0x96, 0x00);
++ adv7180_write_reg(0x97, 0xF0);
++ adv7180_write_reg(0x98, 0x00);
++ adv7180_write_reg(0x99, 0x00);
++ adv7180_write_reg(0x9A, 0x00);
++ adv7180_write_reg(0x9B, 0x00);
++ adv7180_write_reg(0x9C, 0x00);
++ adv7180_write_reg(0x9D, 0x00);
++ adv7180_write_reg(0x9E, 0x00);
++ adv7180_write_reg(0x9F, 0x00);
++ adv7180_write_reg(0xA0, 0x00);
++ adv7180_write_reg(0xA1, 0x00);
++ adv7180_write_reg(0xA2, 0x00);
++ adv7180_write_reg(0xA3, 0x00);
++ adv7180_write_reg(0xA4, 0x00);
++ adv7180_write_reg(0xA5, 0x00);
++ adv7180_write_reg(0xA6, 0x00);
++ adv7180_write_reg(0xA7, 0x00);
++ adv7180_write_reg(0xA8, 0x00);
++ adv7180_write_reg(0xA9, 0x00);
++ adv7180_write_reg(0xAA, 0x00);
++ adv7180_write_reg(0xAB, 0x00);
++ adv7180_write_reg(0xAC, 0x00);
++ adv7180_write_reg(0xAD, 0x00);
++ adv7180_write_reg(0xAE, 0x60);
++ adv7180_write_reg(0xAF, 0x00);
++ adv7180_write_reg(0xB0, 0x00);
++ adv7180_write_reg(0xB1, 0x60);
++ adv7180_write_reg(0xB2, 0x1C);
++ adv7180_write_reg(0xB3, 0x54);
++ adv7180_write_reg(0xB4, 0x00);
++ adv7180_write_reg(0xB5, 0x00);
++ adv7180_write_reg(0xB6, 0x00);
++ adv7180_write_reg(0xB7, 0x13);
++ adv7180_write_reg(0xB8, 0x03);
++ adv7180_write_reg(0xB9, 0x33);
++ adv7180_write_reg(0xBF, 0x02);
++ adv7180_write_reg(0xC0, 0x00);
++ adv7180_write_reg(0xC1, 0x00);
++ adv7180_write_reg(0xC2, 0x00);
++ adv7180_write_reg(0xC3, 0x00);
++ adv7180_write_reg(0xC4, 0x00);
++ adv7180_write_reg(0xC5, 0x81);
++ adv7180_write_reg(0xC6, 0x00);
++ adv7180_write_reg(0xC7, 0x00);
++ adv7180_write_reg(0xC8, 0x00);
++ adv7180_write_reg(0xC9, 0x04);
++ adv7180_write_reg(0xCC, 0x69);
++ adv7180_write_reg(0xCD, 0x00);
++ adv7180_write_reg(0xCE, 0x01);
++ adv7180_write_reg(0xCF, 0xB4);
++ adv7180_write_reg(0xD0, 0x00);
++ adv7180_write_reg(0xD1, 0x10);
++ adv7180_write_reg(0xD2, 0xFF);
++ adv7180_write_reg(0xD3, 0xFF);
++ adv7180_write_reg(0xD4, 0x7F);
++ adv7180_write_reg(0xD5, 0x7F);
++ adv7180_write_reg(0xD6, 0x3E);
++ adv7180_write_reg(0xD7, 0x08);
++ adv7180_write_reg(0xD8, 0x3C);
++ adv7180_write_reg(0xD9, 0x08);
++ adv7180_write_reg(0xDA, 0x3C);
++ adv7180_write_reg(0xDB, 0x9B);
++ adv7180_write_reg(0xDC, 0xAC);
++ adv7180_write_reg(0xDD, 0x4C);
++ adv7180_write_reg(0xDE, 0x00);
++ adv7180_write_reg(0xDF, 0x00);
++ adv7180_write_reg(0xE0, 0x14);
++ adv7180_write_reg(0xE1, 0x80);
++ adv7180_write_reg(0xE2, 0x80);
++ adv7180_write_reg(0xE3, 0x80);
++ adv7180_write_reg(0xE4, 0x80);
++ adv7180_write_reg(0xE5, 0x25);
++ adv7180_write_reg(0xE6, 0x44);
++ adv7180_write_reg(0xE7, 0x63);
++ adv7180_write_reg(0xE8, 0x65);
++ adv7180_write_reg(0xE9, 0x14);
++ adv7180_write_reg(0xEA, 0x63);
++ adv7180_write_reg(0xEB, 0x55);
++ adv7180_write_reg(0xEC, 0x55);
++ adv7180_write_reg(0xEE, 0x00);
++ adv7180_write_reg(0xEF, 0x4A);
++ adv7180_write_reg(0xF0, 0x44);
++ adv7180_write_reg(0xF1, 0x0C);
++ adv7180_write_reg(0xF2, 0x32);
++ adv7180_write_reg(0xF3, 0x00);
++ adv7180_write_reg(0xF4, 0x3F);
++ adv7180_write_reg(0xF5, 0xE0);
++ adv7180_write_reg(0xF6, 0x69);
++ adv7180_write_reg(0xF7, 0x10);
++ adv7180_write_reg(0xF8, 0x00);
++ adv7180_write_reg(0xF9, 0x03);
++ adv7180_write_reg(0xFA, 0xFA);
++ adv7180_write_reg(0xFB, 0x40);
++}
++
++/*! ADV7180 I2C attach function.
++ *
++ * @param *adapter struct i2c_adapter *.
++ *
++ * @return Error code indicating success or failure.
++ */
++
++/*!
++ * ADV7180 I2C probe function.
++ * Function set in i2c_driver struct.
++ * Called by insmod.
++ *
++ * @param *adapter I2C adapter descriptor.
++ *
++ * @return Error code indicating success or failure.
++ */
++static int adv7180_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ int rev_id;
++ int ret = 0;
++ u32 cvbs = true;
++ struct pinctrl *pinctrl;
++ struct device *dev = &client->dev;
++
++ printk(KERN_ERR"DBG sensor data is at %p\n", &adv7180_data);
++
++ /* ov5640 pinctrl */
++ pinctrl = devm_pinctrl_get_select_default(dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(dev, "setup pinctrl failed\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_err(dev, "no sensor pwdn pin available\n");
++ return -ENODEV;
++ }
++ ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "adv7180_pwdn");
++ if (ret < 0) {
++ dev_err(dev, "no power pin available!\n");
++ return ret;
++ }
++
++ adv7180_regulator_enable(dev);
++
++ adv7180_power_down(0);
++
++ msleep(1);
++
++ /* Set initial values for the sensor struct. */
++ memset(&adv7180_data, 0, sizeof(adv7180_data));
++ adv7180_data.sen.i2c_client = client;
++ adv7180_data.sen.streamcap.timeperframe.denominator = 30;
++ adv7180_data.sen.streamcap.timeperframe.numerator = 1;
++ adv7180_data.std_id = V4L2_STD_ALL;
++ video_idx = ADV7180_NOT_LOCKED;
++ adv7180_data.sen.pix.width = video_fmts[video_idx].raw_width;
++ adv7180_data.sen.pix.height = video_fmts[video_idx].raw_height;
++ adv7180_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */
++ adv7180_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */
++ adv7180_data.sen.on = true;
++
++ adv7180_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(adv7180_data.sen.sensor_clk)) {
++ dev_err(dev, "get mclk failed\n");
++ return PTR_ERR(adv7180_data.sen.sensor_clk);
++ }
++
++ ret = of_property_read_u32(dev->of_node, "mclk",
++ &adv7180_data.sen.mclk);
++ if (ret) {
++ dev_err(dev, "mclk frequency is invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(
++ dev->of_node, "mclk_source",
++ (u32 *) &(adv7180_data.sen.mclk_source));
++ if (ret) {
++ dev_err(dev, "mclk_source invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(dev->of_node, "csi_id",
++ &(adv7180_data.sen.csi));
++ if (ret) {
++ dev_err(dev, "csi_id invalid\n");
++ return ret;
++ }
++
++ clk_prepare_enable(adv7180_data.sen.sensor_clk);
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "%s:adv7180 probe i2c address is 0x%02X\n",
++ __func__, adv7180_data.sen.i2c_client->addr);
++
++ /*! Read the revision ID of the tvin chip */
++ rev_id = adv7180_read(ADV7180_IDENT);
++ dev_dbg(dev,
++ "%s:Analog Device adv7%2X0 detected!\n", __func__,
++ rev_id);
++
++ ret = of_property_read_u32(dev->of_node, "cvbs", &(cvbs));
++ if (ret) {
++ dev_err(dev, "cvbs setting is not found\n");
++ cvbs = true;
++ }
++
++ /*! ADV7180 initialization. */
++ adv7180_hard_reset(cvbs);
++
++ pr_debug(" type is %d (expect %d)\n",
++ adv7180_int_device.type, v4l2_int_type_slave);
++ pr_debug(" num ioctls is %d\n",
++ adv7180_int_device.u.slave->num_ioctls);
++
++ /* This function attaches this structure to the /dev/video0 device.
++ * The pointer in priv points to the adv7180_data structure here.*/
++ adv7180_int_device.priv = &adv7180_data;
++ ret = v4l2_int_device_register(&adv7180_int_device);
++
++ clk_disable_unprepare(adv7180_data.sen.sensor_clk);
++
++ return ret;
++}
++
++/*!
++ * ADV7180 I2C detach function.
++ * Called on rmmod.
++ *
++ * @param *client struct i2c_client*.
++ *
++ * @return Error code indicating success or failure.
++ */
++static int adv7180_detach(struct i2c_client *client)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "%s:Removing %s video decoder @ 0x%02X from adapter %s\n",
++ __func__, IF_NAME, client->addr << 1, client->adapter->name);
++
++ /* Power down via i2c */
++ adv7180_write_reg(ADV7180_PWR_MNG, 0x24);
++
++ if (dvddio_regulator)
++ regulator_disable(dvddio_regulator);
++
++ if (dvdd_regulator)
++ regulator_disable(dvdd_regulator);
++
++ if (avdd_regulator)
++ regulator_disable(avdd_regulator);
++
++ if (pvdd_regulator)
++ regulator_disable(pvdd_regulator);
++
++ v4l2_int_device_unregister(&adv7180_int_device);
++
++ return 0;
++}
++
++/*!
++ * ADV7180 init function.
++ * Called on insmod.
++ *
++ * @return Error code indicating success or failure.
++ */
++static __init int adv7180_init(void)
++{
++ u8 err = 0;
++
++ pr_debug("In adv7180_init\n");
++
++ /* Tells the i2c driver what functions to call for this driver. */
++ err = i2c_add_driver(&adv7180_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d\n",
++ __func__, err);
++
++ return err;
++}
++
++/*!
++ * ADV7180 cleanup function.
++ * Called on rmmod.
++ *
++ * @return Error code indicating success or failure.
++ */
++static void __exit adv7180_clean(void)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180_clean\n");
++ i2c_del_driver(&adv7180_i2c_driver);
++}
++
++module_init(adv7180_init);
++module_exit(adv7180_clean);
++
++MODULE_AUTHOR("Freescale Semiconductor");
++MODULE_DESCRIPTION("Anolog Device ADV7180 video decoder driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/csi_v4l2_capture.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/csi_v4l2_capture.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/csi_v4l2_capture.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/csi_v4l2_capture.c 2014-05-15 20:33:57.110007467 +0200
+@@ -0,0 +1,2047 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file drivers/media/video/mxc/capture/csi_v4l2_capture.c
++ * This file is derived from mxc_v4l2_capture.c
++ *
++ * @brief Video For Linux 2 capture driver
++ *
++ * @ingroup MXC_V4L2_CAPTURE
++ */
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/semaphore.h>
++#include <linux/pagemap.h>
++#include <linux/vmalloc.h>
++#include <linux/types.h>
++#include <linux/fb.h>
++#include <linux/mxcfb.h>
++#include <linux/dma-mapping.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-int-device.h>
++#include <media/v4l2-chip-ident.h>
++#include "mxc_v4l2_capture.h"
++#include "fsl_csi.h"
++
++static int video_nr = -1;
++static cam_data *g_cam;
++static int req_buf_number;
++
++static int csi_v4l2_master_attach(struct v4l2_int_device *slave);
++static void csi_v4l2_master_detach(struct v4l2_int_device *slave);
++static u8 camera_power(cam_data *cam, bool cameraOn);
++struct v4l2_crop crop_current;
++struct v4l2_window win_current;
++
++/*! Information about this driver. */
++static struct v4l2_int_master csi_v4l2_master = {
++ .attach = csi_v4l2_master_attach,
++ .detach = csi_v4l2_master_detach,
++};
++
++static struct v4l2_int_device csi_v4l2_int_device = {
++ .module = THIS_MODULE,
++ .name = "csi_v4l2_cap",
++ .type = v4l2_int_type_master,
++ .u = {
++ .master = &csi_v4l2_master,
++ },
++};
++
++static struct v4l2_queryctrl pxp_controls[] = {
++ {
++ .id = V4L2_CID_HFLIP,
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ .name = "Horizontal Flip",
++ .minimum = 0,
++ .maximum = 1,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_VFLIP,
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ .name = "Vertical Flip",
++ .minimum = 0,
++ .maximum = 1,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ .name = "Rotation",
++ .minimum = 0,
++ .maximum = 270,
++ .step = 90,
++ .default_value = 0,
++ .flags = 0,
++ },
++};
++
++/* Callback function triggered after PxP receives an EOF interrupt */
++static void pxp_dma_done(void *arg)
++{
++ struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
++ struct dma_chan *chan = tx_desc->txd.chan;
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ cam_data *cam = pxp_chan->client;
++
++ /* This call will signal wait_for_completion_timeout() */
++ complete(&cam->pxp_tx_cmpl);
++}
++
++static bool chan_filter(struct dma_chan *chan, void *arg)
++{
++ if (imx_dma_is_pxp(chan))
++ return true;
++ else
++ return false;
++}
++
++/* Function to request PXP DMA channel */
++static int pxp_chan_init(cam_data *cam)
++{
++ dma_cap_mask_t mask;
++ struct dma_chan *chan;
++
++ /* Request a free channel */
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_PRIVATE, mask);
++ chan = dma_request_channel(mask, chan_filter, NULL);
++ if (!chan) {
++ pr_err("Unsuccessfully request channel!\n");
++ return -EBUSY;
++ }
++
++ cam->pxp_chan = to_pxp_channel(chan);
++ cam->pxp_chan->client = cam;
++
++ init_completion(&cam->pxp_tx_cmpl);
++
++ return 0;
++}
++
++/*
++ * Function to call PxP DMA driver and send our new V4L2 buffer
++ * through the PxP.
++ * Note: This is a blocking call, so upon return the PxP tx should be complete.
++ */
++static int pxp_process_update(cam_data *cam)
++{
++ dma_cookie_t cookie;
++ struct scatterlist *sg = cam->sg;
++ struct dma_chan *dma_chan;
++ struct pxp_tx_desc *desc;
++ struct dma_async_tx_descriptor *txd;
++ struct pxp_config_data *pxp_conf = &cam->pxp_conf;
++ struct pxp_proc_data *proc_data = &cam->pxp_conf.proc_data;
++ int i, ret;
++ int length;
++
++ pr_debug("Starting PxP Send Buffer\n");
++
++ /* First, check to see that we have acquired a PxP Channel object */
++ if (cam->pxp_chan == NULL) {
++ /*
++ * PxP Channel has not yet been created and initialized,
++ * so let's go ahead and try
++ */
++ ret = pxp_chan_init(cam);
++ if (ret) {
++ /*
++ * PxP channel init failed, and we can't use the
++ * PxP until the PxP DMA driver has loaded, so we abort
++ */
++ pr_err("PxP chan init failed\n");
++ return -ENODEV;
++ }
++ }
++
++ /*
++ * Init completion, so that we can be properly informed of
++ * the completion of the PxP task when it is done.
++ */
++ init_completion(&cam->pxp_tx_cmpl);
++
++ dma_chan = &cam->pxp_chan->dma_chan;
++
++ txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2,
++ DMA_TO_DEVICE,
++ DMA_PREP_INTERRUPT,
++ NULL);
++ if (!txd) {
++ pr_err("Error preparing a DMA transaction descriptor.\n");
++ return -EIO;
++ }
++
++ txd->callback_param = txd;
++ txd->callback = pxp_dma_done;
++
++ /*
++ * Configure PxP for processing of new v4l2 buf
++ */
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_UYVY;
++ pxp_conf->s0_param.color_key = -1;
++ pxp_conf->s0_param.color_key_enable = false;
++ pxp_conf->s0_param.width = cam->v2f.fmt.pix.width;
++ pxp_conf->s0_param.height = cam->v2f.fmt.pix.height;
++
++ pxp_conf->ol_param[0].combine_enable = false;
++
++ proc_data->srect.top = 0;
++ proc_data->srect.left = 0;
++ proc_data->srect.width = pxp_conf->s0_param.width;
++ proc_data->srect.height = pxp_conf->s0_param.height;
++
++ if (crop_current.c.top != 0)
++ proc_data->srect.top = crop_current.c.top;
++ if (crop_current.c.left != 0)
++ proc_data->srect.left = crop_current.c.left;
++ if (crop_current.c.width != 0)
++ proc_data->srect.width = crop_current.c.width;
++ if (crop_current.c.height != 0)
++ proc_data->srect.height = crop_current.c.height;
++
++ proc_data->drect.left = 0;
++ proc_data->drect.top = 0;
++ proc_data->drect.width = proc_data->srect.width;
++ proc_data->drect.height = proc_data->srect.height;
++
++ if (win_current.w.left != 0)
++ proc_data->drect.left = win_current.w.left;
++ if (win_current.w.top != 0)
++ proc_data->drect.top = win_current.w.top;
++ if (win_current.w.width != 0)
++ proc_data->drect.width = win_current.w.width;
++ if (win_current.w.height != 0)
++ proc_data->drect.height = win_current.w.height;
++
++ pr_debug("srect l: %d, t: %d, w: %d, h: %d; "
++ "drect l: %d, t: %d, w: %d, h: %d\n",
++ proc_data->srect.left, proc_data->srect.top,
++ proc_data->srect.width, proc_data->srect.height,
++ proc_data->drect.left, proc_data->drect.top,
++ proc_data->drect.width, proc_data->drect.height);
++
++ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++ pxp_conf->out_param.width = proc_data->drect.width;
++ pxp_conf->out_param.height = proc_data->drect.height;
++
++ if (cam->rotation % 180)
++ pxp_conf->out_param.stride = pxp_conf->out_param.height;
++ else
++ pxp_conf->out_param.stride = pxp_conf->out_param.width;
++
++ desc = to_tx_desc(txd);
++ length = desc->len;
++ for (i = 0; i < length; i++) {
++ if (i == 0) {/* S0 */
++ memcpy(&desc->proc_data, proc_data,
++ sizeof(struct pxp_proc_data));
++ pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]);
++ memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param,
++ sizeof(struct pxp_layer_param));
++ } else if (i == 1) {
++ pxp_conf->out_param.paddr = sg_dma_address(&sg[1]);
++ memcpy(&desc->layer_param.out_param,
++ &pxp_conf->out_param,
++ sizeof(struct pxp_layer_param));
++ }
++
++ desc = desc->next;
++ }
++
++ /* Submitting our TX starts the PxP processing task */
++ cookie = txd->tx_submit(txd);
++ if (cookie < 0) {
++ pr_err("Error sending FB through PxP\n");
++ return -EIO;
++ }
++
++ cam->txd = txd;
++
++ /* trigger PxP */
++ dma_async_issue_pending(dma_chan);
++
++ return 0;
++}
++
++static int pxp_complete_update(cam_data *cam)
++{
++ int ret;
++ /*
++ * Wait for completion event, which will be set
++ * through our TX callback function.
++ */
++ ret = wait_for_completion_timeout(&cam->pxp_tx_cmpl, HZ / 10);
++ if (ret <= 0) {
++ pr_warning("PxP operation failed due to %s\n",
++ ret < 0 ? "user interrupt" : "timeout");
++ dma_release_channel(&cam->pxp_chan->dma_chan);
++ cam->pxp_chan = NULL;
++ return ret ? : -ETIMEDOUT;
++ }
++
++ dma_release_channel(&cam->pxp_chan->dma_chan);
++ cam->pxp_chan = NULL;
++
++ pr_debug("TX completed\n");
++
++ return 0;
++}
++
++/*!
++ * Camera V4l2 callback function.
++ *
++ * @param mask u32
++ * @param dev void device structure
++ *
++ * @return none
++ */
++static void camera_callback(u32 mask, void *dev)
++{
++ struct mxc_v4l_frame *done_frame;
++ struct mxc_v4l_frame *ready_frame;
++ cam_data *cam;
++
++ cam = (cam_data *) dev;
++ if (cam == NULL)
++ return;
++
++ spin_lock(&cam->queue_int_lock);
++ spin_lock(&cam->dqueue_int_lock);
++ if (!list_empty(&cam->working_q)) {
++ done_frame = list_entry(cam->working_q.next,
++ struct mxc_v4l_frame, queue);
++
++ if (done_frame->csi_buf_num != cam->ping_pong_csi)
++ goto next;
++
++ if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
++ done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE;
++ done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
++
++ /* Added to the done queue */
++ list_del(cam->working_q.next);
++ list_add_tail(&done_frame->queue, &cam->done_q);
++ cam->enc_counter++;
++ wake_up_interruptible(&cam->enc_queue);
++ } else {
++ pr_err("ERROR: v4l2 capture: %s: "
++ "buffer not queued\n", __func__);
++ }
++ }
++
++next:
++ if (!list_empty(&cam->ready_q)) {
++ ready_frame = list_entry(cam->ready_q.next,
++ struct mxc_v4l_frame, queue);
++ list_del(cam->ready_q.next);
++ list_add_tail(&ready_frame->queue, &cam->working_q);
++
++ __raw_writel(ready_frame->paddress,
++ cam->ping_pong_csi == 1 ? CSI_CSIDMASA_FB1 :
++ CSI_CSIDMASA_FB2);
++ ready_frame->csi_buf_num = cam->ping_pong_csi;
++ } else {
++ __raw_writel(cam->dummy_frame.paddress,
++ cam->ping_pong_csi == 1 ? CSI_CSIDMASA_FB1 :
++ CSI_CSIDMASA_FB2);
++ }
++ spin_unlock(&cam->dqueue_int_lock);
++ spin_unlock(&cam->queue_int_lock);
++
++ return;
++}
++
++/*!
++ * Make csi ready for capture image.
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 success
++ */
++static int csi_cap_image(cam_data *cam)
++{
++ unsigned int value;
++
++ value = __raw_readl(CSI_CSICR3);
++ __raw_writel(value | BIT_FRMCNT_RST, CSI_CSICR3);
++ value = __raw_readl(CSI_CSISR);
++ __raw_writel(value, CSI_CSISR);
++
++ return 0;
++}
++
++/***************************************************************************
++ * Functions for handling Frame buffers.
++ **************************************************************************/
++
++/*!
++ * Free frame buffers
++ *
++ * @param cam Structure cam_data *
++ *
++ * @return status 0 success.
++ */
++static int csi_free_frame_buf(cam_data *cam)
++{
++ int i;
++
++ pr_debug("MVC: In %s\n", __func__);
++
++ for (i = 0; i < FRAME_NUM; i++) {
++ if (cam->frame[i].vaddress != 0) {
++ dma_free_coherent(0, cam->frame[i].buffer.length,
++ cam->frame[i].vaddress,
++ cam->frame[i].paddress);
++ cam->frame[i].vaddress = 0;
++ }
++ }
++
++ if (cam->dummy_frame.vaddress != 0) {
++ dma_free_coherent(0, cam->dummy_frame.buffer.length,
++ cam->dummy_frame.vaddress,
++ cam->dummy_frame.paddress);
++ cam->dummy_frame.vaddress = 0;
++ }
++
++ return 0;
++}
++
++/*!
++ * Allocate frame buffers
++ *
++ * @param cam Structure cam_data *
++ * @param count int number of buffer need to allocated
++ *
++ * @return status -0 Successfully allocated a buffer, -ENOBUFS failed.
++ */
++static int csi_allocate_frame_buf(cam_data *cam, int count)
++{
++ int i;
++
++ pr_debug("In MVC:%s- size=%d\n",
++ __func__, cam->v2f.fmt.pix.sizeimage);
++ for (i = 0; i < count; i++) {
++ cam->frame[i].vaddress = dma_alloc_coherent(0, PAGE_ALIGN
++ (cam->v2f.fmt.
++ pix.sizeimage),
++ &cam->frame[i].
++ paddress,
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->frame[i].vaddress == 0) {
++ pr_err("ERROR: v4l2 capture: "
++ "%s failed.\n", __func__);
++ csi_free_frame_buf(cam);
++ return -ENOBUFS;
++ }
++ cam->frame[i].buffer.index = i;
++ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++ cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cam->frame[i].buffer.length = cam->v2f.fmt.pix.sizeimage;
++ cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP;
++ cam->frame[i].buffer.m.offset = cam->frame[i].paddress;
++ cam->frame[i].index = i;
++ cam->frame[i].csi_buf_num = 0;
++ }
++
++ return 0;
++}
++
++/*!
++ * Free frame buffers status
++ *
++ * @param cam Structure cam_data *
++ *
++ * @return none
++ */
++static void csi_free_frames(cam_data *cam)
++{
++ int i;
++
++ pr_debug("In MVC: %s\n", __func__);
++
++ for (i = 0; i < FRAME_NUM; i++)
++ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++
++ cam->enc_counter = 0;
++ INIT_LIST_HEAD(&cam->ready_q);
++ INIT_LIST_HEAD(&cam->working_q);
++ INIT_LIST_HEAD(&cam->done_q);
++
++ return;
++}
++
++/*!
++ * Return the buffer status
++ *
++ * @param cam Structure cam_data *
++ * @param buf Structure v4l2_buffer *
++ *
++ * @return status 0 success, EINVAL failed.
++ */
++static int csi_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf)
++{
++ pr_debug("In MVC: %s\n", __func__);
++
++ if (buf->index < 0 || buf->index >= FRAME_NUM) {
++ pr_err("ERROR: v4l2 capture: %s buffers "
++ "not allocated\n", __func__);
++ return -EINVAL;
++ }
++
++ memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf));
++
++ return 0;
++}
++
++static int csi_v4l2_release_bufs(cam_data *cam)
++{
++ pr_debug("In MVC:csi_v4l2_release_bufs\n");
++ return 0;
++}
++
++static int csi_v4l2_prepare_bufs(cam_data *cam, struct v4l2_buffer *buf)
++{
++ pr_debug("In MVC:csi_v4l2_prepare_bufs\n");
++
++ if (buf->index < 0 || buf->index >= FRAME_NUM || buf->length <
++ cam->v2f.fmt.pix.sizeimage) {
++ pr_err("ERROR: v4l2 capture: csi_v4l2_prepare_bufs buffers "
++ "not allocated,index=%d, length=%d\n", buf->index,
++ buf->length);
++ return -EINVAL;
++ }
++
++ cam->frame[buf->index].buffer.index = buf->index;
++ cam->frame[buf->index].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++ cam->frame[buf->index].buffer.length = buf->length;
++ cam->frame[buf->index].buffer.m.offset = cam->frame[buf->index].paddress
++ = buf->m.offset;
++ cam->frame[buf->index].buffer.type = buf->type;
++ cam->frame[buf->index].buffer.memory = V4L2_MEMORY_USERPTR;
++ cam->frame[buf->index].index = buf->index;
++
++ return 0;
++}
++
++/*!
++ * Indicates whether the palette is supported.
++ *
++ * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_UYVY or V4L2_PIX_FMT_YUV420
++ *
++ * @return 0 if failed
++ */
++static inline int valid_mode(u32 palette)
++{
++ return (palette == V4L2_PIX_FMT_RGB565) ||
++ (palette == V4L2_PIX_FMT_YUYV) ||
++ (palette == V4L2_PIX_FMT_UYVY) || (palette == V4L2_PIX_FMT_YUV420);
++}
++
++/*!
++ * Start stream I/O
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int csi_streamon(cam_data *cam)
++{
++ struct mxc_v4l_frame *frame;
++ unsigned long flags;
++ unsigned long val;
++ int timeout, timeout2;
++
++ pr_debug("In MVC: %s\n", __func__);
++
++ if (NULL == cam) {
++ pr_err("ERROR: v4l2 capture: %s cam parameter is NULL\n",
++ __func__);
++ return -1;
++ }
++ cam->dummy_frame.vaddress = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->dummy_frame.paddress,
++ GFP_DMA | GFP_KERNEL);
++ if (cam->dummy_frame.vaddress == 0) {
++ pr_err("ERROR: v4l2 capture: Allocate dummy frame "
++ "failed.\n");
++ return -ENOBUFS;
++ }
++ cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE;
++ cam->dummy_frame.buffer.length = cam->v2f.fmt.pix.sizeimage;
++ cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
++
++ spin_lock_irqsave(&cam->queue_int_lock, flags);
++ /* move the frame from readyq to workingq */
++ if (list_empty(&cam->ready_q)) {
++ pr_err("ERROR: v4l2 capture: %s: "
++ "ready_q queue empty\n", __func__);
++ spin_unlock_irqrestore(&cam->queue_int_lock, flags);
++ return -1;
++ }
++ frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->ready_q.next);
++ list_add_tail(&frame->queue, &cam->working_q);
++ __raw_writel(frame->paddress, CSI_CSIDMASA_FB1);
++ frame->csi_buf_num = 1;
++
++ if (list_empty(&cam->ready_q)) {
++ pr_err("ERROR: v4l2 capture: %s: "
++ "ready_q queue empty\n", __func__);
++ spin_unlock_irqrestore(&cam->queue_int_lock, flags);
++ return -1;
++ }
++ frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->ready_q.next);
++ list_add_tail(&frame->queue, &cam->working_q);
++ __raw_writel(frame->paddress, CSI_CSIDMASA_FB2);
++ frame->csi_buf_num = 2;
++ spin_unlock_irqrestore(&cam->queue_int_lock, flags);
++
++ cam->capture_pid = current->pid;
++ cam->capture_on = true;
++ csi_cap_image(cam);
++
++ local_irq_save(flags);
++ for (timeout = 1000000; timeout > 0; timeout--) {
++ if (__raw_readl(CSI_CSISR) & BIT_SOF_INT) {
++ val = __raw_readl(CSI_CSICR3);
++ __raw_writel(val | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
++ for (timeout2 = 1000000; timeout2 > 0; timeout2--) {
++ if (__raw_readl(CSI_CSICR3) &
++ BIT_DMA_REFLASH_RFF)
++ cpu_relax();
++ else
++ break;
++ }
++ if (timeout2 <= 0) {
++ pr_err("timeout when wait for reflash done.\n");
++ local_irq_restore(flags);
++ return -ETIME;
++ }
++
++ csi_dmareq_rff_enable();
++ csi_enable_int(1);
++ break;
++ } else
++ cpu_relax();
++ }
++ if (timeout <= 0) {
++ pr_err("timeout when wait for SOF\n");
++ local_irq_restore(flags);
++ return -ETIME;
++ }
++ local_irq_restore(flags);
++
++ return 0;
++}
++
++/*!
++ * Stop stream I/O
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int csi_streamoff(cam_data *cam)
++{
++ pr_debug("In MVC: %s\n", __func__);
++
++ if (cam->capture_on == false)
++ return 0;
++
++ csi_dmareq_rff_disable();
++ csi_disable_int();
++ cam->capture_on = false;
++
++ /* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */
++ __raw_writel(0, CSI_CSIDMASA_FB1);
++ __raw_writel(0, CSI_CSIDMASA_FB2);
++
++ csi_free_frames(cam);
++ csi_free_frame_buf(cam);
++
++ return 0;
++}
++
++/*!
++ * start the viewfinder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int start_preview(cam_data *cam)
++{
++ unsigned long fb_addr = (unsigned long)cam->v4l2_fb.base;
++
++ __raw_writel(fb_addr, CSI_CSIDMASA_FB1);
++ __raw_writel(fb_addr, CSI_CSIDMASA_FB2);
++ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
++
++ csi_enable_int(0);
++
++ return 0;
++}
++
++/*!
++ * shut down the viewfinder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int stop_preview(cam_data *cam)
++{
++ csi_disable_int();
++
++ /* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */
++ __raw_writel(0, CSI_CSIDMASA_FB1);
++ __raw_writel(0, CSI_CSIDMASA_FB2);
++ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
++
++ return 0;
++}
++
++/***************************************************************************
++ * VIDIOC Functions.
++ **************************************************************************/
++
++/*!
++ *
++ * @param cam structure cam_data *
++ *
++ * @param f structure v4l2_format *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int csi_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f)
++{
++ int retval = 0;
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ f->fmt.pix = cam->v2f.fmt.pix;
++ break;
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
++ f->fmt.win = cam->win;
++ break;
++ default:
++ pr_debug(" type is invalid\n");
++ retval = -EINVAL;
++ }
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++
++ return retval;
++}
++
++/*!
++ * V4L2 - csi_v4l2_s_fmt function
++ *
++ * @param cam structure cam_data *
++ *
++ * @param f structure v4l2_format *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int csi_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f)
++{
++ int retval = 0;
++ int size = 0;
++ int bytesperline = 0;
++ int *width, *height;
++
++ pr_debug("In MVC: %s\n", __func__);
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ if (!valid_mode(f->fmt.pix.pixelformat)) {
++ pr_err("ERROR: v4l2 capture: %s: format "
++ "not supported\n", __func__);
++ return -EINVAL;
++ }
++
++ /* Handle case where size requested is larger than cuurent
++ * camera setting. */
++ if ((f->fmt.pix.width > cam->crop_bounds.width)
++ || (f->fmt.pix.height > cam->crop_bounds.height)) {
++ /* Need the logic here, calling vidioc_s_param if
++ * camera can change. */
++ pr_debug("csi_v4l2_s_fmt size changed\n");
++ }
++ if (cam->rotation % 180) {
++ height = &f->fmt.pix.width;
++ width = &f->fmt.pix.height;
++ } else {
++ width = &f->fmt.pix.width;
++ height = &f->fmt.pix.height;
++ }
++
++ if ((cam->crop_bounds.width / *width > 8) ||
++ ((cam->crop_bounds.width / *width == 8) &&
++ (cam->crop_bounds.width % *width))) {
++ *width = cam->crop_bounds.width / 8;
++ if (*width % 8)
++ *width += 8 - *width % 8;
++ pr_err("ERROR: v4l2 capture: width exceeds limit "
++ "resize to %d.\n", *width);
++ }
++
++ if ((cam->crop_bounds.height / *height > 8) ||
++ ((cam->crop_bounds.height / *height == 8) &&
++ (cam->crop_bounds.height % *height))) {
++ *height = cam->crop_bounds.height / 8;
++ if (*height % 8)
++ *height += 8 - *height % 8;
++ pr_err("ERROR: v4l2 capture: height exceeds limit "
++ "resize to %d.\n", *height);
++ }
++
++ switch (f->fmt.pix.pixelformat) {
++ case V4L2_PIX_FMT_RGB565:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ csi_init_format(V4L2_PIX_FMT_UYVY);
++ csi_set_16bit_imagpara(f->fmt.pix.width,
++ f->fmt.pix.height);
++ bytesperline = f->fmt.pix.width * 2;
++ break;
++ case V4L2_PIX_FMT_UYVY:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ csi_init_format(f->fmt.pix.pixelformat);
++ csi_set_16bit_imagpara(f->fmt.pix.width,
++ f->fmt.pix.height);
++ bytesperline = f->fmt.pix.width * 2;
++ break;
++ case V4L2_PIX_FMT_YUYV:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ csi_init_format(f->fmt.pix.pixelformat);
++ csi_set_16bit_imagpara(f->fmt.pix.width,
++ f->fmt.pix.height);
++ bytesperline = f->fmt.pix.width * 2;
++ break;
++ case V4L2_PIX_FMT_YUV420:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
++ csi_set_12bit_imagpara(f->fmt.pix.width,
++ f->fmt.pix.height);
++ bytesperline = f->fmt.pix.width;
++ break;
++ case V4L2_PIX_FMT_YUV422P:
++ case V4L2_PIX_FMT_RGB24:
++ case V4L2_PIX_FMT_BGR24:
++ case V4L2_PIX_FMT_BGR32:
++ case V4L2_PIX_FMT_RGB32:
++ case V4L2_PIX_FMT_NV12:
++ default:
++ pr_debug(" case not supported\n");
++ break;
++ }
++
++ if (f->fmt.pix.bytesperline < bytesperline)
++ f->fmt.pix.bytesperline = bytesperline;
++ else
++ bytesperline = f->fmt.pix.bytesperline;
++
++ if (f->fmt.pix.sizeimage < size)
++ f->fmt.pix.sizeimage = size;
++ else
++ size = f->fmt.pix.sizeimage;
++
++ cam->v2f.fmt.pix = f->fmt.pix;
++
++ if (cam->v2f.fmt.pix.priv != 0) {
++ if (copy_from_user(&cam->offset,
++ (void *)cam->v2f.fmt.pix.priv,
++ sizeof(cam->offset))) {
++ retval = -EFAULT;
++ break;
++ }
++ }
++ break;
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
++ cam->win = f->fmt.win;
++ win_current = f->fmt.win;
++ size = win_current.w.width * win_current.w.height * 2;
++ if (cam->v2f.fmt.pix.sizeimage < size)
++ cam->v2f.fmt.pix.sizeimage = size;
++
++ break;
++ default:
++ retval = -EINVAL;
++ }
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++
++ return retval;
++}
++
++/*!
++ * V4L2 - csi_v4l2_s_param function
++ * Allows setting of capturemode and frame rate.
++ *
++ * @param cam structure cam_data *
++ * @param parm structure v4l2_streamparm *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int csi_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
++{
++ struct v4l2_ifparm ifparm;
++ struct v4l2_format cam_fmt;
++ struct v4l2_streamparm currentparm;
++ int err = 0;
++
++ pr_debug("In %s\n", __func__);
++
++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ pr_err(KERN_ERR "%s invalid type\n", __func__);
++ return -EINVAL;
++ }
++
++ /* Stop the viewfinder */
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++
++ /* First check that this device can support the changes requested. */
++ err = vidioc_int_g_parm(cam->sensor, &currentparm);
++ if (err) {
++ pr_err("%s: vidioc_int_g_parm returned an error %d\n",
++ __func__, err);
++ goto exit;
++ }
++
++ pr_debug(" Current capabilities are %x\n",
++ currentparm.parm.capture.capability);
++ pr_debug(" Current capturemode is %d change to %d\n",
++ currentparm.parm.capture.capturemode,
++ parm->parm.capture.capturemode);
++ pr_debug(" Current framerate is %d change to %d\n",
++ currentparm.parm.capture.timeperframe.denominator,
++ parm->parm.capture.timeperframe.denominator);
++
++ err = vidioc_int_s_parm(cam->sensor, parm);
++ if (err) {
++ pr_err("%s: vidioc_int_s_parm returned an error %d\n",
++ __func__, err);
++ goto exit;
++ }
++
++ vidioc_int_g_ifparm(cam->sensor, &ifparm);
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++ pr_debug(" g_fmt_cap returns widthxheight of input as %d x %d\n",
++ cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
++
++ cam->crop_bounds.top = cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = cam_fmt.fmt.pix.width;
++ cam->crop_bounds.height = cam_fmt.fmt.pix.height;
++ cam->crop_current.width = cam->crop_bounds.width;
++ cam->crop_current.height = cam->crop_bounds.height;
++
++exit:
++ return err;
++}
++
++static int pxp_set_cstate(cam_data *cam, struct v4l2_control *vc)
++{
++ struct pxp_proc_data *proc_data = &cam->pxp_conf.proc_data;
++
++ if (vc->id == V4L2_CID_HFLIP) {
++ proc_data->hflip = vc->value;
++ } else if (vc->id == V4L2_CID_VFLIP) {
++ proc_data->vflip = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE) {
++ if (vc->value % 90)
++ return -ERANGE;
++ proc_data->rotate = vc->value;
++ cam->rotation = vc->value;
++ }
++
++ return 0;
++}
++
++static int pxp_get_cstate(cam_data *cam, struct v4l2_control *vc)
++{
++ struct pxp_proc_data *proc_data = &cam->pxp_conf.proc_data;
++
++ if (vc->id == V4L2_CID_HFLIP)
++ vc->value = proc_data->hflip;
++ else if (vc->id == V4L2_CID_VFLIP)
++ vc->value = proc_data->vflip;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE)
++ vc->value = proc_data->rotate;
++
++ return 0;
++}
++
++
++/*!
++ * Dequeue one V4L capture buffer
++ *
++ * @param cam structure cam_data *
++ * @param buf structure v4l2_buffer *
++ *
++ * @return status 0 success, EINVAL invalid frame number
++ * ETIME timeout, ERESTARTSYS interrupted by user
++ */
++static int csi_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf)
++{
++ int retval = 0;
++ struct mxc_v4l_frame *frame;
++ unsigned long lock_flags;
++
++ if (!wait_event_interruptible_timeout(cam->enc_queue,
++ cam->enc_counter != 0, 10 * HZ)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout "
++ "enc_counter %x\n", cam->enc_counter);
++ return -ETIME;
++ } else if (signal_pending(current)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() "
++ "interrupt received\n");
++ return -ERESTARTSYS;
++ }
++
++ if (down_interruptible(&cam->busy_lock))
++ return -EBUSY;
++
++ spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags);
++
++ if (list_empty(&cam->done_q)) {
++ spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags);
++ up(&cam->busy_lock);
++ return -EINVAL;
++ }
++
++ cam->enc_counter--;
++
++ frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->done_q.next);
++
++ if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) {
++ frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE;
++ } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
++ "Buffer not filled.\n");
++ frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
++ retval = -EINVAL;
++ } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
++ "Buffer not queued.\n");
++ retval = -EINVAL;
++ }
++
++ spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags);
++
++ buf->bytesused = cam->v2f.fmt.pix.sizeimage;
++ buf->index = frame->index;
++ buf->flags = frame->buffer.flags;
++ buf->m = cam->frame[frame->index].buffer.m;
++
++ /*
++ * Note:
++ * If want to do preview on LCD, use PxP CSC to convert from UYVY
++ * to RGB565; but for encoding, usually we don't use RGB format.
++ */
++ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) {
++ sg_dma_address(&cam->sg[0]) = buf->m.offset;
++ sg_dma_address(&cam->sg[1]) =
++ cam->frame[req_buf_number].paddress;
++ retval = pxp_process_update(cam);
++ if (retval) {
++ pr_err("Unable to submit PxP update task.\n");
++ return retval;
++ }
++ pxp_complete_update(cam);
++ if (cam->frame[buf->index].vaddress)
++ memcpy(cam->frame[buf->index].vaddress,
++ cam->frame[req_buf_number].vaddress,
++ cam->v2f.fmt.pix.sizeimage);
++ }
++ up(&cam->busy_lock);
++
++ return retval;
++}
++
++/*!
++ * V4L interface - open function
++ *
++ * @param file structure file *
++ *
++ * @return status 0 success, ENODEV invalid device instance,
++ * ENODEV timeout, ERESTARTSYS interrupted by user
++ */
++static int csi_v4l_open(struct file *file)
++{
++ struct v4l2_ifparm ifparm;
++ struct v4l2_format cam_fmt;
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++ struct sensor_data *sensor;
++ int err = 0;
++
++ pr_debug(" device name is %s\n", dev->name);
++
++ if (!cam) {
++ pr_err("%s: Internal error, cam_data not found!\n", __func__);
++ return -EBADF;
++ }
++
++ if (!cam->sensor) {
++ pr_err("%s: Internal error, camera is not found!\n", __func__);
++ return -EBADF;
++ }
++
++ sensor = cam->sensor->priv;
++ if (!sensor) {
++ pr_err("%s: Internal error, sensor_data is not found!\n", __func__);
++ return -EBADF;
++ }
++
++ down(&cam->busy_lock);
++ err = 0;
++ if (signal_pending(current))
++ goto oops;
++
++ if (cam->open_count++ == 0) {
++ wait_event_interruptible(cam->power_queue,
++ cam->low_power == false);
++
++ cam->enc_counter = 0;
++ INIT_LIST_HEAD(&cam->ready_q);
++ INIT_LIST_HEAD(&cam->working_q);
++ INIT_LIST_HEAD(&cam->done_q);
++
++ vidioc_int_g_ifparm(cam->sensor, &ifparm);
++
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ clk_prepare_enable(sensor->sensor_clk);
++ vidioc_int_s_power(cam->sensor, 1);
++ vidioc_int_init(cam->sensor);
++ vidioc_int_dev_init(cam->sensor);
++ }
++
++ file->private_data = dev;
++
++oops:
++ up(&cam->busy_lock);
++ return err;
++}
++
++/*!
++ * V4L interface - close function
++ *
++ * @param file struct file *
++ *
++ * @return 0 success
++ */
++static int csi_v4l_close(struct file *file)
++{
++ struct video_device *dev = video_devdata(file);
++ int err = 0;
++ cam_data *cam = video_get_drvdata(dev);
++ struct sensor_data *sensor;
++
++ pr_debug("In MVC:%s\n", __func__);
++
++ if (!cam) {
++ pr_err("%s: Internal error, cam_data not found!\n", __func__);
++ return -EBADF;
++ }
++
++ if (!cam->sensor) {
++ pr_err("%s: Internal error, camera is not found!\n", __func__);
++ return -EBADF;
++ }
++
++ sensor = cam->sensor->priv;
++ if (!sensor) {
++ pr_err("%s: Internal error, sensor_data is not found!\n", __func__);
++ return -EBADF;
++ }
++
++ /* for the case somebody hit the ctrl C */
++ if (cam->overlay_pid == current->pid) {
++ err = stop_preview(cam);
++ cam->overlay_on = false;
++ }
++
++ if (--cam->open_count == 0) {
++ wait_event_interruptible(cam->power_queue,
++ cam->low_power == false);
++ file->private_data = NULL;
++ vidioc_int_s_power(cam->sensor, 0);
++ clk_disable_unprepare(sensor->sensor_clk);
++ }
++
++ return err;
++}
++
++/*
++ * V4L interface - read function
++ *
++ * @param file struct file *
++ * @param read buf char *
++ * @param count size_t
++ * @param ppos structure loff_t *
++ *
++ * @return bytes read
++ */
++static ssize_t csi_v4l_read(struct file *file, char *buf, size_t count,
++ loff_t *ppos)
++{
++ int err = 0;
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++
++ if (down_interruptible(&cam->busy_lock))
++ return -EINTR;
++
++ /* Stop the viewfinder */
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ if (cam->still_buf_vaddr == NULL) {
++ cam->still_buf_vaddr = dma_alloc_coherent(0,
++ PAGE_ALIGN
++ (cam->v2f.fmt.
++ pix.sizeimage),
++ &cam->
++ still_buf[0],
++ GFP_DMA | GFP_KERNEL);
++ if (cam->still_buf_vaddr == NULL) {
++ pr_err("alloc dma memory failed\n");
++ return -ENOMEM;
++ }
++ cam->still_counter = 0;
++ __raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB2);
++ __raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB1);
++ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF,
++ CSI_CSICR3);
++ __raw_writel(__raw_readl(CSI_CSISR), CSI_CSISR);
++ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST,
++ CSI_CSICR3);
++ csi_enable_int(1);
++ }
++
++ wait_event_interruptible(cam->still_queue, cam->still_counter);
++ csi_disable_int();
++ err = copy_to_user(buf, cam->still_buf_vaddr,
++ cam->v2f.fmt.pix.sizeimage);
++
++ if (cam->still_buf_vaddr != NULL) {
++ dma_free_coherent(0, PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ cam->still_buf_vaddr, cam->still_buf[0]);
++ cam->still_buf[0] = 0;
++ cam->still_buf_vaddr = NULL;
++ }
++
++ if (cam->overlay_on == true)
++ start_preview(cam);
++
++ up(&cam->busy_lock);
++ if (err < 0)
++ return err;
++
++ return cam->v2f.fmt.pix.sizeimage - err;
++}
++
++/*!
++ * V4L interface - ioctl function
++ *
++ * @param file struct file*
++ *
++ * @param ioctlnr unsigned int
++ *
++ * @param arg void*
++ *
++ * @return 0 success, ENODEV for invalid device instance,
++ * -1 for other errors.
++ */
++static long csi_v4l_do_ioctl(struct file *file,
++ unsigned int ioctlnr, void *arg)
++{
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++ int retval = 0;
++ unsigned long lock_flags;
++
++ pr_debug("In MVC: %s, %x\n", __func__, ioctlnr);
++ wait_event_interruptible(cam->power_queue, cam->low_power == false);
++ /* make this _really_ smp-safe */
++ if (ioctlnr != VIDIOC_DQBUF)
++ if (down_interruptible(&cam->busy_lock))
++ return -EBUSY;
++
++ switch (ioctlnr) {
++ /*!
++ * V4l2 VIDIOC_G_FMT ioctl
++ */
++ case VIDIOC_G_FMT:{
++ struct v4l2_format *gf = arg;
++ pr_debug(" case VIDIOC_G_FMT\n");
++ retval = csi_v4l2_g_fmt(cam, gf);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_FMT ioctl
++ */
++ case VIDIOC_S_FMT:{
++ struct v4l2_format *sf = arg;
++ pr_debug(" case VIDIOC_S_FMT\n");
++ retval = csi_v4l2_s_fmt(cam, sf);
++ vidioc_int_s_fmt_cap(cam->sensor, sf);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_OVERLAY ioctl
++ */
++ case VIDIOC_OVERLAY:{
++ int *on = arg;
++ pr_debug(" case VIDIOC_OVERLAY\n");
++ if (*on) {
++ cam->overlay_on = true;
++ cam->overlay_pid = current->pid;
++ start_preview(cam);
++ }
++ if (!*on) {
++ stop_preview(cam);
++ cam->overlay_on = false;
++ }
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_FBUF ioctl
++ */
++ case VIDIOC_G_FBUF:{
++ struct v4l2_framebuffer *fb = arg;
++ *fb = cam->v4l2_fb;
++ fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_FBUF ioctl
++ */
++ case VIDIOC_S_FBUF:{
++ struct v4l2_framebuffer *fb = arg;
++ cam->v4l2_fb = *fb;
++ break;
++ }
++
++ case VIDIOC_G_PARM:{
++ struct v4l2_streamparm *parm = arg;
++ pr_debug(" case VIDIOC_G_PARM\n");
++ vidioc_int_g_parm(cam->sensor, parm);
++ break;
++ }
++
++ case VIDIOC_S_PARM:{
++ struct v4l2_streamparm *parm = arg;
++ pr_debug(" case VIDIOC_S_PARM\n");
++ retval = csi_v4l2_s_param(cam, parm);
++ break;
++ }
++
++ case VIDIOC_QUERYCAP:{
++ struct v4l2_capability *cap = arg;
++ pr_debug(" case VIDIOC_QUERYCAP\n");
++ strcpy(cap->driver, "csi_v4l2");
++ cap->version = KERNEL_VERSION(0, 1, 11);
++ cap->capabilities = V4L2_CAP_VIDEO_OVERLAY |
++ V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
++ V4L2_CAP_VIDEO_OUTPUT_OVERLAY | V4L2_CAP_READWRITE;
++ cap->card[0] = '\0';
++ cap->bus_info[0] = '\0';
++ break;
++ }
++
++ case VIDIOC_CROPCAP:
++ {
++ struct v4l2_cropcap *cap = arg;
++
++ if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
++ retval = -EINVAL;
++ break;
++ }
++ cap->bounds = cam->crop_bounds;
++ cap->defrect = cam->crop_defrect;
++ break;
++ }
++ case VIDIOC_S_CROP:
++ {
++ struct v4l2_crop *crop = arg;
++ struct v4l2_rect *b = &cam->crop_bounds;
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ retval = -EINVAL;
++ break;
++ }
++
++ crop->c.top = (crop->c.top < b->top) ? b->top
++ : crop->c.top;
++ if (crop->c.top > b->top + b->height)
++ crop->c.top = b->top + b->height - 1;
++ if (crop->c.height > b->top + b->height - crop->c.top)
++ crop->c.height =
++ b->top + b->height - crop->c.top;
++
++ crop->c.left = (crop->c.left < b->left) ? b->left
++ : crop->c.left;
++ if (crop->c.left > b->left + b->width)
++ crop->c.left = b->left + b->width - 1;
++ if (crop->c.width > b->left - crop->c.left + b->width)
++ crop->c.width =
++ b->left - crop->c.left + b->width;
++
++ crop->c.width -= crop->c.width % 8;
++ crop->c.height -= crop->c.height % 8;
++
++ crop_current.c = crop->c;
++
++ break;
++ }
++ case VIDIOC_G_CROP:
++ {
++ struct v4l2_crop *crop = arg;
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ retval = -EINVAL;
++ break;
++ }
++ crop->c = crop_current.c;
++
++ break;
++
++ }
++ case VIDIOC_REQBUFS: {
++ struct v4l2_requestbuffers *req = arg;
++ pr_debug(" case VIDIOC_REQBUFS\n");
++
++ if (req->count > FRAME_NUM) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
++ "not enough buffers\n");
++ req->count = FRAME_NUM;
++ }
++
++ if (req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
++ "wrong buffer type\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ csi_streamoff(cam);
++ if (req->memory & V4L2_MEMORY_MMAP) {
++ csi_free_frame_buf(cam);
++ retval = csi_allocate_frame_buf(cam, req->count + 1);
++ req_buf_number = req->count;
++ }
++ break;
++ }
++
++ case VIDIOC_QUERYBUF: {
++ struct v4l2_buffer *buf = arg;
++ int index = buf->index;
++ pr_debug(" case VIDIOC_QUERYBUF\n");
++
++ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ retval = -EINVAL;
++ break;
++ }
++
++ if (buf->memory & V4L2_MEMORY_MMAP) {
++ memset(buf, 0, sizeof(buf));
++ buf->index = index;
++ }
++
++ down(&cam->param_lock);
++ if (buf->memory & V4L2_MEMORY_USERPTR) {
++ csi_v4l2_release_bufs(cam);
++ retval = csi_v4l2_prepare_bufs(cam, buf);
++ }
++ if (buf->memory & V4L2_MEMORY_MMAP)
++ retval = csi_v4l2_buffer_status(cam, buf);
++ up(&cam->param_lock);
++ break;
++ }
++
++ case VIDIOC_QBUF: {
++ struct v4l2_buffer *buf = arg;
++ int index = buf->index;
++ pr_debug(" case VIDIOC_QBUF\n");
++
++ spin_lock_irqsave(&cam->queue_int_lock, lock_flags);
++ cam->frame[index].buffer.m.offset = buf->m.offset;
++ if ((cam->frame[index].buffer.flags & 0x7) ==
++ V4L2_BUF_FLAG_MAPPED) {
++ cam->frame[index].buffer.flags |= V4L2_BUF_FLAG_QUEUED;
++ list_add_tail(&cam->frame[index].queue, &cam->ready_q);
++ } else if (cam->frame[index].buffer.flags &
++ V4L2_BUF_FLAG_QUEUED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
++ "buffer already queued\n");
++ retval = -EINVAL;
++ } else if (cam->frame[index].buffer.
++ flags & V4L2_BUF_FLAG_DONE) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
++ "overwrite done buffer.\n");
++ cam->frame[index].buffer.flags &=
++ ~V4L2_BUF_FLAG_DONE;
++ cam->frame[index].buffer.flags |=
++ V4L2_BUF_FLAG_QUEUED;
++ retval = -EINVAL;
++ }
++ buf->flags = cam->frame[index].buffer.flags;
++ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
++
++ break;
++ }
++
++ case VIDIOC_DQBUF: {
++ struct v4l2_buffer *buf = arg;
++ pr_debug(" case VIDIOC_DQBUF\n");
++
++ retval = csi_v4l_dqueue(cam, buf);
++
++ break;
++ }
++
++ case VIDIOC_STREAMON: {
++ pr_debug(" case VIDIOC_STREAMON\n");
++ retval = csi_streamon(cam);
++ break;
++ }
++
++ case VIDIOC_STREAMOFF: {
++ pr_debug(" case VIDIOC_STREAMOFF\n");
++ retval = csi_streamoff(cam);
++ break;
++ }
++ case VIDIOC_ENUM_FMT: {
++ struct v4l2_fmtdesc *fmt = arg;
++ if (cam->sensor)
++ retval = vidioc_int_enum_fmt_cap(cam->sensor, fmt);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_ENUM_FRAMESIZES: {
++ struct v4l2_frmsizeenum *fsize = arg;
++ if (cam->sensor)
++ retval = vidioc_int_enum_framesizes(cam->sensor, fsize);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_ENUM_FRAMEINTERVALS: {
++ struct v4l2_frmivalenum *fival = arg;
++ if (cam->sensor)
++ retval = vidioc_int_enum_frameintervals(cam->sensor,
++ fival);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_DBG_G_CHIP_IDENT: {
++ struct v4l2_dbg_chip_ident *p = arg;
++ p->ident = V4L2_IDENT_NONE;
++ p->revision = 0;
++ if (cam->sensor)
++ retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++
++ case VIDIOC_S_CTRL:
++ {
++ struct v4l2_control *vc = arg;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (vc->id == pxp_controls[i].id) {
++ if (vc->value < pxp_controls[i].minimum ||
++ vc->value > pxp_controls[i].maximum) {
++ retval = -ERANGE;
++ break;
++ }
++ retval = pxp_set_cstate(cam, vc);
++ break;
++ }
++
++ if (i >= ARRAY_SIZE(pxp_controls))
++ retval = -EINVAL;
++ break;
++
++ }
++ case VIDIOC_G_CTRL:
++ {
++ struct v4l2_control *vc = arg;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (vc->id == pxp_controls[i].id) {
++ retval = pxp_get_cstate(cam, vc);
++ break;
++ }
++
++ if (i >= ARRAY_SIZE(pxp_controls))
++ retval = -EINVAL;
++ break;
++ }
++ case VIDIOC_QUERYCTRL:
++ {
++ struct v4l2_queryctrl *qc = arg;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (qc->id && qc->id == pxp_controls[i].id) {
++ memcpy(qc, &(pxp_controls[i]), sizeof(*qc));
++ break;
++ }
++
++ if (i >= ARRAY_SIZE(pxp_controls))
++ retval = -EINVAL;
++ break;
++ }
++ case VIDIOC_G_STD:
++ case VIDIOC_G_OUTPUT:
++ case VIDIOC_S_OUTPUT:
++ case VIDIOC_ENUMSTD:
++ case VIDIOC_S_STD:
++ case VIDIOC_TRY_FMT:
++ case VIDIOC_ENUMINPUT:
++ case VIDIOC_G_INPUT:
++ case VIDIOC_S_INPUT:
++ case VIDIOC_G_TUNER:
++ case VIDIOC_S_TUNER:
++ case VIDIOC_G_FREQUENCY:
++ case VIDIOC_S_FREQUENCY:
++ case VIDIOC_ENUMOUTPUT:
++ default:
++ pr_debug(" case not supported\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ if (ioctlnr != VIDIOC_DQBUF)
++ up(&cam->busy_lock);
++ return retval;
++}
++
++/*
++ * V4L interface - ioctl function
++ *
++ * @return None
++ */
++static long csi_v4l_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ return video_usercopy(file, cmd, arg, csi_v4l_do_ioctl);
++}
++
++/*!
++ * V4L interface - mmap function
++ *
++ * @param file structure file *
++ *
++ * @param vma structure vm_area_struct *
++ *
++ * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error
++ */
++static int csi_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ struct video_device *dev = video_devdata(file);
++ unsigned long size;
++ int res = 0;
++ cam_data *cam = video_get_drvdata(dev);
++
++ pr_debug("%s\n", __func__);
++ pr_debug("\npgoff=0x%lx, start=0x%lx, end=0x%lx\n",
++ vma->vm_pgoff, vma->vm_start, vma->vm_end);
++
++ /* make this _really_ smp-safe */
++ if (down_interruptible(&cam->busy_lock))
++ return -EINTR;
++
++ size = vma->vm_end - vma->vm_start;
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start,
++ vma->vm_pgoff, size, vma->vm_page_prot)) {
++ pr_err("ERROR: v4l2 capture: %s : "
++ "remap_pfn_range failed\n", __func__);
++ res = -ENOBUFS;
++ goto csi_mmap_exit;
++ }
++
++ vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */
++
++csi_mmap_exit:
++ up(&cam->busy_lock);
++ return res;
++}
++
++/*!
++ * This structure defines the functions to be called in this driver.
++ */
++static struct v4l2_file_operations csi_v4l_fops = {
++ .owner = THIS_MODULE,
++ .open = csi_v4l_open,
++ .release = csi_v4l_close,
++ .read = csi_v4l_read,
++ .ioctl = csi_v4l_ioctl,
++ .mmap = csi_mmap,
++};
++
++static struct video_device csi_v4l_template = {
++ .name = "Mx25 Camera",
++ .fops = &csi_v4l_fops,
++ .release = video_device_release,
++};
++
++/*!
++ * initialize cam_data structure
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static void init_camera_struct(cam_data *cam)
++{
++ struct pxp_proc_data *proc_data = &cam->pxp_conf.proc_data;
++ pr_debug("In MVC: %s\n", __func__);
++
++ proc_data->hflip = 0;
++ proc_data->vflip = 0;
++ proc_data->rotate = 0;
++ proc_data->bgcolor = 0;
++
++ /* Default everything to 0 */
++ memset(cam, 0, sizeof(cam_data));
++
++ sema_init(&cam->param_lock, 1);
++ sema_init(&cam->busy_lock, 1);
++
++ cam->video_dev = video_device_alloc();
++ if (cam->video_dev == NULL)
++ return;
++
++ *(cam->video_dev) = csi_v4l_template;
++
++ video_set_drvdata(cam->video_dev, cam);
++ cam->video_dev->minor = -1;
++
++ init_waitqueue_head(&cam->enc_queue);
++ init_waitqueue_head(&cam->still_queue);
++
++ cam->streamparm.parm.capture.capturemode = 0;
++
++ cam->standard.index = 0;
++ cam->standard.id = V4L2_STD_UNKNOWN;
++ cam->standard.frameperiod.denominator = 30;
++ cam->standard.frameperiod.numerator = 1;
++ cam->standard.framelines = 480;
++ cam->standard_autodetect = true;
++ cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod;
++ cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
++ cam->overlay_on = false;
++ cam->capture_on = false;
++ cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY;
++
++ cam->v2f.fmt.pix.sizeimage = 480 * 640 * 2;
++ cam->v2f.fmt.pix.bytesperline = 640 * 2;
++ cam->v2f.fmt.pix.width = 640;
++ cam->v2f.fmt.pix.height = 480;
++ cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_UYVY;
++ cam->win.w.width = 160;
++ cam->win.w.height = 160;
++ cam->win.w.left = 0;
++ cam->win.w.top = 0;
++ cam->still_counter = 0;
++ /* setup cropping */
++ cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = 640;
++ cam->crop_bounds.top = 0;
++ cam->crop_bounds.height = 480;
++ cam->crop_current = cam->crop_defrect = cam->crop_bounds;
++
++ cam->enc_callback = camera_callback;
++ csi_start_callback(cam);
++ init_waitqueue_head(&cam->power_queue);
++ spin_lock_init(&cam->queue_int_lock);
++ spin_lock_init(&cam->dqueue_int_lock);
++}
++
++/*!
++ * camera_power function
++ * Turns Sensor power On/Off
++ *
++ * @param cam cam data struct
++ * @param cameraOn true to turn camera on, false to turn off power.
++ *
++ * @return status
++ */
++static u8 camera_power(cam_data *cam, bool cameraOn)
++{
++ pr_debug("In MVC: %s on=%d\n", __func__, cameraOn);
++
++ if (cameraOn == true) {
++ vidioc_int_s_power(cam->sensor, 1);
++ } else {
++ vidioc_int_s_power(cam->sensor, 0);
++ }
++ return 0;
++}
++
++static const struct of_device_id imx_csi_v4l2_dt_ids[] = {
++ { .compatible = "fsl,imx6sl-csi-v4l2", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_csi_v4l2_dt_ids);
++
++static int csi_v4l2_probe(struct platform_device *pdev)
++{
++ struct scatterlist *sg;
++ u8 err = 0;
++
++ /* Create g_cam and initialize it. */
++ g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL);
++ if (g_cam == NULL) {
++ pr_err("ERROR: v4l2 capture: failed to register camera\n");
++ err = -ENOMEM;
++ goto out;
++ }
++ memset(&crop_current, 0, sizeof(crop_current));
++ memset(&win_current, 0, sizeof(win_current));
++ init_camera_struct(g_cam);
++ platform_set_drvdata(pdev, (void *)g_cam);
++
++ /* Set up the v4l2 device and register it */
++ csi_v4l2_int_device.priv = g_cam;
++ /* This function contains a bug that won't let this be rmmod'd. */
++ v4l2_int_device_register(&csi_v4l2_int_device);
++
++ /* register v4l video device */
++ if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr)
++ == -1) {
++ kfree(g_cam);
++ g_cam = NULL;
++ pr_err("ERROR: v4l2 capture: video_register_device failed\n");
++ err = -ENODEV;
++ goto out;
++ }
++ pr_debug(" Video device registered: %s #%d\n",
++ g_cam->video_dev->name, g_cam->video_dev->minor);
++
++ g_cam->pxp_chan = NULL;
++ /* Initialize Scatter-gather list containing 2 buffer addresses. */
++ sg = g_cam->sg;
++ sg_init_table(sg, 2);
++
++out:
++ return err;
++}
++
++static int csi_v4l2_remove(struct platform_device *pdev)
++{
++ if (g_cam->open_count) {
++ pr_err("ERROR: v4l2 capture:camera open "
++ "-- setting ops to NULL\n");
++ } else {
++ pr_info("V4L2 freeing image input device\n");
++ v4l2_int_device_unregister(&csi_v4l2_int_device);
++ csi_stop_callback(g_cam);
++ video_unregister_device(g_cam->video_dev);
++ platform_set_drvdata(pdev, NULL);
++
++ kfree(g_cam);
++ g_cam = NULL;
++ }
++
++ return 0;
++}
++
++/*!
++ * This function is called to put the sensor in a low power state.
++ * Refer to the document driver-model/driver.txt in the kernel source tree
++ * for more information.
++ *
++ * @param pdev the device structure used to give information on which I2C
++ * to suspend
++ * @param state the power state the device is entering
++ *
++ * @return The function returns 0 on success and -1 on failure.
++ */
++static int csi_v4l2_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ cam_data *cam = platform_get_drvdata(pdev);
++
++ pr_debug("In MVC: %s\n", __func__);
++
++ if (cam == NULL)
++ return -1;
++
++ cam->low_power = true;
++
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ if (cam->capture_on == true || cam->overlay_on == true)
++ camera_power(cam, false);
++
++ return 0;
++}
++
++/*!
++ * This function is called to bring the sensor back from a low power state.
++ * Refer to the document driver-model/driver.txt in the kernel source tree
++ * for more information.
++ *
++ * @param pdev the device structure
++ *
++ * @return The function returns 0 on success and -1 on failure
++ */
++static int csi_v4l2_resume(struct platform_device *pdev)
++{
++ cam_data *cam = platform_get_drvdata(pdev);
++
++ pr_debug("In MVC: %s\n", __func__);
++
++ if (cam == NULL)
++ return -1;
++
++ cam->low_power = false;
++ wake_up_interruptible(&cam->power_queue);
++ if (cam->capture_on == true || cam->overlay_on == true)
++ camera_power(cam, true);
++
++ if (cam->overlay_on == true)
++ start_preview(cam);
++
++ return 0;
++}
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver csi_v4l2_driver = {
++ .driver = {
++ .name = "csi_v4l2",
++ .of_match_table = of_match_ptr(imx_csi_v4l2_dt_ids),
++ },
++ .probe = csi_v4l2_probe,
++ .remove = csi_v4l2_remove,
++#ifdef CONFIG_PM
++ .suspend = csi_v4l2_suspend,
++ .resume = csi_v4l2_resume,
++#endif
++ .shutdown = NULL,
++};
++
++/*!
++ * Initializes the camera driver.
++ */
++static int csi_v4l2_master_attach(struct v4l2_int_device *slave)
++{
++ cam_data *cam = slave->u.slave->master->priv;
++ struct v4l2_format cam_fmt;
++
++ pr_debug("In MVC: %s\n", __func__);
++ pr_debug(" slave.name = %s\n", slave->name);
++ pr_debug(" master.name = %s\n", slave->u.slave->master->name);
++
++ cam->sensor = slave;
++ if (slave == NULL) {
++ pr_err("ERROR: v4l2 capture: slave parameter not valid.\n");
++ return -1;
++ }
++
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++
++ /* Used to detect TV in (type 1) vs. camera (type 0) */
++ cam->device_type = cam_fmt.fmt.pix.priv;
++
++ cam->crop_bounds.top = cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = cam_fmt.fmt.pix.width;
++ cam->crop_bounds.height = cam_fmt.fmt.pix.height;
++
++ /* This also is the max crop size for this device. */
++ cam->crop_defrect.top = cam->crop_defrect.left = 0;
++ cam->crop_defrect.width = cam_fmt.fmt.pix.width;
++ cam->crop_defrect.height = cam_fmt.fmt.pix.height;
++
++ /* At this point, this is also the current image size. */
++ cam->crop_current.top = cam->crop_current.left = 0;
++ cam->crop_current.width = cam_fmt.fmt.pix.width;
++ cam->crop_current.height = cam_fmt.fmt.pix.height;
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++
++ return 0;
++}
++
++/*!
++ * Disconnects the camera driver.
++ */
++static void csi_v4l2_master_detach(struct v4l2_int_device *slave)
++{
++ pr_debug("In MVC: %s\n", __func__);
++
++ vidioc_int_dev_exit(slave);
++}
++
++module_platform_driver(csi_v4l2_driver);
++
++module_param(video_nr, int, 0444);
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("V4L2 capture driver for Mx25 based cameras");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("video");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/fsl_csi.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/fsl_csi.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/fsl_csi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/fsl_csi.c 2014-05-15 20:33:57.110007467 +0200
+@@ -0,0 +1,302 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file fsl_csi.c, this file is derived from mx27_csi.c
++ *
++ * @brief mx25 CMOS Sensor interface functions
++ *
++ * @ingroup CSI
++ */
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/spinlock.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/of.h>
++#include <linux/sched.h>
++
++#include "mxc_v4l2_capture.h"
++#include "fsl_csi.h"
++
++void __iomem *csi_regbase;
++EXPORT_SYMBOL(csi_regbase);
++static int irq_nr;
++static csi_irq_callback_t g_callback;
++static void *g_callback_data;
++
++static irqreturn_t csi_irq_handler(int irq, void *data)
++{
++ cam_data *cam = (cam_data *) data;
++ unsigned long status = __raw_readl(CSI_CSISR);
++
++ __raw_writel(status, CSI_CSISR);
++
++ if (status & BIT_HRESP_ERR_INT)
++ pr_warning("Hresponse error is detected.\n");
++
++ if (status & BIT_DMA_TSF_DONE_FB1) {
++ if (cam->capture_on) {
++ spin_lock(&cam->queue_int_lock);
++ cam->ping_pong_csi = 1;
++ spin_unlock(&cam->queue_int_lock);
++ cam->enc_callback(0, cam);
++ } else {
++ cam->still_counter++;
++ wake_up_interruptible(&cam->still_queue);
++ }
++ }
++
++ if (status & BIT_DMA_TSF_DONE_FB2) {
++ if (cam->capture_on) {
++ spin_lock(&cam->queue_int_lock);
++ cam->ping_pong_csi = 2;
++ spin_unlock(&cam->queue_int_lock);
++ cam->enc_callback(0, cam);
++ } else {
++ cam->still_counter++;
++ wake_up_interruptible(&cam->still_queue);
++ }
++ }
++
++ if (g_callback)
++ g_callback(g_callback_data, status);
++
++ pr_debug("CSI status = 0x%08lX\n", status);
++
++ return IRQ_HANDLED;
++}
++
++static void csihw_reset_frame_count(void)
++{
++ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3);
++}
++
++static void csihw_reset(void)
++{
++ csihw_reset_frame_count();
++ __raw_writel(CSICR1_RESET_VAL, CSI_CSICR1);
++ __raw_writel(CSICR2_RESET_VAL, CSI_CSICR2);
++ __raw_writel(CSICR3_RESET_VAL, CSI_CSICR3);
++}
++
++/*!
++ * csi_init_interface
++ * Init csi interface
++ */
++void csi_init_interface(void)
++{
++ unsigned int val = 0;
++ unsigned int imag_para;
++
++ val |= BIT_SOF_POL;
++ val |= BIT_REDGE;
++ val |= BIT_GCLK_MODE;
++ val |= BIT_HSYNC_POL;
++ val |= BIT_PACK_DIR;
++ val |= BIT_FCC;
++ val |= BIT_SWAP16_EN;
++ val |= 1 << SHIFT_MCLKDIV;
++ val |= BIT_MCLKEN;
++ __raw_writel(val, CSI_CSICR1);
++
++ imag_para = (640 << 16) | 960;
++ __raw_writel(imag_para, CSI_CSIIMAG_PARA);
++
++ val = 0x1010;
++ val |= BIT_DMA_REFLASH_RFF;
++ __raw_writel(val, CSI_CSICR3);
++}
++EXPORT_SYMBOL(csi_init_interface);
++
++void csi_init_format(int fmt)
++{
++ unsigned int val;
++
++ val = __raw_readl(CSI_CSICR1);
++ if (fmt == V4L2_PIX_FMT_YUYV) {
++ val &= ~BIT_PACK_DIR;
++ val &= ~BIT_SWAP16_EN;
++ } else if (fmt == V4L2_PIX_FMT_UYVY) {
++ val |= BIT_PACK_DIR;
++ val |= BIT_SWAP16_EN;
++ } else
++ pr_warning("unsupported format, old format remains.\n");
++
++ __raw_writel(val, CSI_CSICR1);
++}
++EXPORT_SYMBOL(csi_init_format);
++
++/*!
++ * csi_read_mclk_flag
++ *
++ * @return gcsi_mclk_source
++ */
++int csi_read_mclk_flag(void)
++{
++ return 0;
++}
++EXPORT_SYMBOL(csi_read_mclk_flag);
++
++void csi_start_callback(void *data)
++{
++ cam_data *cam = (cam_data *) data;
++
++ if (request_irq(irq_nr, csi_irq_handler, 0, "csi", cam) < 0)
++ pr_debug("CSI error: irq request fail\n");
++
++}
++EXPORT_SYMBOL(csi_start_callback);
++
++void csi_stop_callback(void *data)
++{
++ cam_data *cam = (cam_data *) data;
++
++ free_irq(irq_nr, cam);
++}
++EXPORT_SYMBOL(csi_stop_callback);
++
++void csi_enable_int(int arg)
++{
++ unsigned long cr1 = __raw_readl(CSI_CSICR1);
++
++ cr1 |= BIT_SOF_INTEN;
++ if (arg == 1) {
++ /* still capture needs DMA intterrupt */
++ cr1 |= BIT_FB1_DMA_DONE_INTEN;
++ cr1 |= BIT_FB2_DMA_DONE_INTEN;
++ }
++ __raw_writel(cr1, CSI_CSICR1);
++}
++EXPORT_SYMBOL(csi_enable_int);
++
++void csi_disable_int(void)
++{
++ unsigned long cr1 = __raw_readl(CSI_CSICR1);
++
++ cr1 &= ~BIT_SOF_INTEN;
++ cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
++ cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
++ __raw_writel(cr1, CSI_CSICR1);
++}
++EXPORT_SYMBOL(csi_disable_int);
++
++void csi_set_16bit_imagpara(int width, int height)
++{
++ int imag_para = 0;
++ unsigned long cr3 = __raw_readl(CSI_CSICR3);
++
++ imag_para = (width << 16) | (height * 2);
++ __raw_writel(imag_para, CSI_CSIIMAG_PARA);
++
++ /* reflash the embeded DMA controller */
++ __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
++}
++EXPORT_SYMBOL(csi_set_16bit_imagpara);
++
++void csi_set_12bit_imagpara(int width, int height)
++{
++ int imag_para = 0;
++ unsigned long cr3 = __raw_readl(CSI_CSICR3);
++
++ imag_para = (width << 16) | (height * 3 / 2);
++ __raw_writel(imag_para, CSI_CSIIMAG_PARA);
++
++ /* reflash the embeded DMA controller */
++ __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3);
++}
++EXPORT_SYMBOL(csi_set_12bit_imagpara);
++
++void csi_dmareq_rff_enable(void)
++{
++ unsigned long cr3 = __raw_readl(CSI_CSICR3);
++
++ cr3 |= BIT_DMA_REQ_EN_RFF;
++ cr3 |= BIT_HRESP_ERR_EN;
++ __raw_writel(cr3, CSI_CSICR3);
++}
++EXPORT_SYMBOL(csi_dmareq_rff_enable);
++
++void csi_dmareq_rff_disable(void)
++{
++ unsigned long cr3 = __raw_readl(CSI_CSICR3);
++
++ cr3 &= ~BIT_DMA_REQ_EN_RFF;
++ cr3 &= ~BIT_HRESP_ERR_EN;
++ __raw_writel(cr3, CSI_CSICR3);
++}
++EXPORT_SYMBOL(csi_dmareq_rff_disable);
++
++static const struct of_device_id fsl_csi_dt_ids[] = {
++ { .compatible = "fsl,imx6sl-csi", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, fsl_csi_dt_ids);
++
++static int csi_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++ struct resource *res;
++
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "No csi irq found.\n");
++ ret = -ENODEV;
++ goto err;
++ }
++ irq_nr = res->start;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "No csi base address found.\n");
++ ret = -ENODEV;
++ goto err;
++ }
++ csi_regbase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
++ if (!csi_regbase) {
++ dev_err(&pdev->dev, "ioremap failed with csi base\n");
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ csihw_reset();
++ csi_init_interface();
++ csi_dmareq_rff_disable();
++
++err:
++ return ret;
++}
++
++static int csi_remove(struct platform_device *pdev)
++{
++ return 0;
++}
++
++static struct platform_driver csi_driver = {
++ .driver = {
++ .name = "fsl_csi",
++ .of_match_table = of_match_ptr(fsl_csi_dt_ids),
++ },
++ .probe = csi_probe,
++ .remove = csi_remove,
++};
++
++module_platform_driver(csi_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("fsl CSI driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/fsl_csi.h linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/fsl_csi.h
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/fsl_csi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/fsl_csi.h 2014-05-15 20:33:57.110007467 +0200
+@@ -0,0 +1,198 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file fsl_csi.h
++ *
++ * @brief mx25 CMOS Sensor interface functions
++ *
++ * @ingroup CSI
++ */
++
++#ifndef MX25_CSI_H
++#define MX25_CSI_H
++
++#include <linux/io.h>
++
++/* reset values */
++#define CSICR1_RESET_VAL 0x40000800
++#define CSICR2_RESET_VAL 0x0
++#define CSICR3_RESET_VAL 0x0
++
++/* csi control reg 1 */
++#define BIT_SWAP16_EN (0x1 << 31)
++#define BIT_EXT_VSYNC (0x1 << 30)
++#define BIT_EOF_INT_EN (0x1 << 29)
++#define BIT_PRP_IF_EN (0x1 << 28)
++#define BIT_CCIR_MODE (0x1 << 27)
++#define BIT_COF_INT_EN (0x1 << 26)
++#define BIT_SF_OR_INTEN (0x1 << 25)
++#define BIT_RF_OR_INTEN (0x1 << 24)
++#define BIT_SFF_DMA_DONE_INTEN (0x1 << 22)
++#define BIT_STATFF_INTEN (0x1 << 21)
++#define BIT_FB2_DMA_DONE_INTEN (0x1 << 20)
++#define BIT_FB1_DMA_DONE_INTEN (0x1 << 19)
++#define BIT_RXFF_INTEN (0x1 << 18)
++#define BIT_SOF_POL (0x1 << 17)
++#define BIT_SOF_INTEN (0x1 << 16)
++#define BIT_MCLKDIV (0xF << 12)
++#define BIT_HSYNC_POL (0x1 << 11)
++#define BIT_CCIR_EN (0x1 << 10)
++#define BIT_MCLKEN (0x1 << 9)
++#define BIT_FCC (0x1 << 8)
++#define BIT_PACK_DIR (0x1 << 7)
++#define BIT_CLR_STATFIFO (0x1 << 6)
++#define BIT_CLR_RXFIFO (0x1 << 5)
++#define BIT_GCLK_MODE (0x1 << 4)
++#define BIT_INV_DATA (0x1 << 3)
++#define BIT_INV_PCLK (0x1 << 2)
++#define BIT_REDGE (0x1 << 1)
++#define BIT_PIXEL_BIT (0x1 << 0)
++
++#define SHIFT_MCLKDIV 12
++
++/* control reg 3 */
++#define BIT_FRMCNT (0xFFFF << 16)
++#define BIT_FRMCNT_RST (0x1 << 15)
++#define BIT_DMA_REFLASH_RFF (0x1 << 14)
++#define BIT_DMA_REFLASH_SFF (0x1 << 13)
++#define BIT_DMA_REQ_EN_RFF (0x1 << 12)
++#define BIT_DMA_REQ_EN_SFF (0x1 << 11)
++#define BIT_STATFF_LEVEL (0x7 << 8)
++#define BIT_HRESP_ERR_EN (0x1 << 7)
++#define BIT_RXFF_LEVEL (0x7 << 4)
++#define BIT_TWO_8BIT_SENSOR (0x1 << 3)
++#define BIT_ZERO_PACK_EN (0x1 << 2)
++#define BIT_ECC_INT_EN (0x1 << 1)
++#define BIT_ECC_AUTO_EN (0x1 << 0)
++
++#define SHIFT_FRMCNT 16
++
++/* csi status reg */
++#define BIT_SFF_OR_INT (0x1 << 25)
++#define BIT_RFF_OR_INT (0x1 << 24)
++#define BIT_DMA_TSF_DONE_SFF (0x1 << 22)
++#define BIT_STATFF_INT (0x1 << 21)
++#define BIT_DMA_TSF_DONE_FB2 (0x1 << 20)
++#define BIT_DMA_TSF_DONE_FB1 (0x1 << 19)
++#define BIT_RXFF_INT (0x1 << 18)
++#define BIT_EOF_INT (0x1 << 17)
++#define BIT_SOF_INT (0x1 << 16)
++#define BIT_F2_INT (0x1 << 15)
++#define BIT_F1_INT (0x1 << 14)
++#define BIT_COF_INT (0x1 << 13)
++#define BIT_HRESP_ERR_INT (0x1 << 7)
++#define BIT_ECC_INT (0x1 << 1)
++#define BIT_DRDY (0x1 << 0)
++
++#define CSI_MCLK_VF 1
++#define CSI_MCLK_ENC 2
++#define CSI_MCLK_RAW 4
++#define CSI_MCLK_I2C 8
++#endif
++
++extern void __iomem *csi_regbase;
++#define CSI_CSICR1 (csi_regbase)
++#define CSI_CSICR2 (csi_regbase + 0x4)
++#define CSI_CSICR3 (csi_regbase + 0x8)
++#define CSI_STATFIFO (csi_regbase + 0xC)
++#define CSI_CSIRXFIFO (csi_regbase + 0x10)
++#define CSI_CSIRXCNT (csi_regbase + 0x14)
++#define CSI_CSISR (csi_regbase + 0x18)
++
++#define CSI_CSIDBG (csi_regbase + 0x1C)
++#define CSI_CSIDMASA_STATFIFO (csi_regbase + 0x20)
++#define CSI_CSIDMATS_STATFIFO (csi_regbase + 0x24)
++#define CSI_CSIDMASA_FB1 (csi_regbase + 0x28)
++#define CSI_CSIDMASA_FB2 (csi_regbase + 0x2C)
++#define CSI_CSIFBUF_PARA (csi_regbase + 0x30)
++#define CSI_CSIIMAG_PARA (csi_regbase + 0x34)
++
++static inline void csi_clear_status(unsigned long status)
++{
++ __raw_writel(status, CSI_CSISR);
++}
++
++struct csi_signal_cfg_t {
++ unsigned data_width:3;
++ unsigned clk_mode:2;
++ unsigned ext_vsync:1;
++ unsigned Vsync_pol:1;
++ unsigned Hsync_pol:1;
++ unsigned pixclk_pol:1;
++ unsigned data_pol:1;
++ unsigned sens_clksrc:1;
++};
++
++struct csi_config_t {
++ /* control reg 1 */
++ unsigned int swap16_en:1;
++ unsigned int ext_vsync:1;
++ unsigned int eof_int_en:1;
++ unsigned int prp_if_en:1;
++ unsigned int ccir_mode:1;
++ unsigned int cof_int_en:1;
++ unsigned int sf_or_inten:1;
++ unsigned int rf_or_inten:1;
++ unsigned int sff_dma_done_inten:1;
++ unsigned int statff_inten:1;
++ unsigned int fb2_dma_done_inten:1;
++ unsigned int fb1_dma_done_inten:1;
++ unsigned int rxff_inten:1;
++ unsigned int sof_pol:1;
++ unsigned int sof_inten:1;
++ unsigned int mclkdiv:4;
++ unsigned int hsync_pol:1;
++ unsigned int ccir_en:1;
++ unsigned int mclken:1;
++ unsigned int fcc:1;
++ unsigned int pack_dir:1;
++ unsigned int gclk_mode:1;
++ unsigned int inv_data:1;
++ unsigned int inv_pclk:1;
++ unsigned int redge:1;
++ unsigned int pixel_bit:1;
++
++ /* control reg 3 */
++ unsigned int frmcnt:16;
++ unsigned int frame_reset:1;
++ unsigned int dma_reflash_rff:1;
++ unsigned int dma_reflash_sff:1;
++ unsigned int dma_req_en_rff:1;
++ unsigned int dma_req_en_sff:1;
++ unsigned int statff_level:3;
++ unsigned int hresp_err_en:1;
++ unsigned int rxff_level:3;
++ unsigned int two_8bit_sensor:1;
++ unsigned int zero_pack_en:1;
++ unsigned int ecc_int_en:1;
++ unsigned int ecc_auto_en:1;
++ /* fifo counter */
++ unsigned int rxcnt;
++};
++
++typedef void (*csi_irq_callback_t) (void *data, unsigned long status);
++
++void csi_init_interface(void);
++void csi_init_format(int fmt);
++void csi_set_16bit_imagpara(int width, int height);
++void csi_set_12bit_imagpara(int width, int height);
++int csi_read_mclk_flag(void);
++void csi_start_callback(void *data);
++void csi_stop_callback(void *data);
++void csi_enable_int(int arg);
++void csi_disable_int(void);
++void csi_mclk_enable(void);
++void csi_mclk_disable(void);
++void csi_dmareq_rff_enable(void);
++void csi_dmareq_rff_disable(void);
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c 2014-05-15 20:33:57.110007467 +0200
+@@ -0,0 +1,554 @@
++
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_bg_overlay_sdc_bg.c
++ *
++ * @brief IPU Use case for PRP-VF back-ground
++ *
++ * @ingroup IPU
++ */
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/fb.h>
++#include <linux/ipu.h>
++#include <linux/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++static int csi_buffer_num;
++static u32 bpp, csi_mem_bufsize = 3;
++static u32 out_format;
++static struct ipu_soc *disp_ipu;
++static u32 offset;
++
++static void csi_buf_work_func(struct work_struct *work)
++{
++ int err = 0;
++ cam_data *cam =
++ container_of(work, struct _cam_data, csi_work_struct);
++
++ struct ipu_task task;
++ memset(&task, 0, sizeof(task));
++
++ if (csi_buffer_num)
++ task.input.paddr = cam->vf_bufs[0];
++ else
++ task.input.paddr = cam->vf_bufs[1];
++ task.input.width = cam->crop_current.width;
++ task.input.height = cam->crop_current.height;
++ task.input.format = IPU_PIX_FMT_UYVY;
++
++ task.output.paddr = offset;
++ task.output.width = cam->overlay_fb->var.xres;
++ task.output.height = cam->overlay_fb->var.yres;
++ task.output.format = out_format;
++ task.output.rotate = cam->rotation;
++ task.output.crop.pos.x = cam->win.w.left;
++ task.output.crop.pos.y = cam->win.w.top;
++ if (cam->win.w.width > 1024 || cam->win.w.height > 1024) {
++ task.output.crop.w = cam->overlay_fb->var.xres;
++ task.output.crop.h = cam->overlay_fb->var.yres;
++ } else {
++ task.output.crop.w = cam->win.w.width;
++ task.output.crop.h = cam->win.w.height;
++ }
++again:
++ err = ipu_check_task(&task);
++ if (err != IPU_CHECK_OK) {
++ if (err > IPU_CHECK_ERR_MIN) {
++ if (err == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) {
++ task.input.crop.w -= 8;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) {
++ task.input.crop.h -= 8;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
++ task.output.width -= 8;
++ task.output.crop.w = task.output.width;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
++ task.output.height -= 8;
++ task.output.crop.h = task.output.height;
++ goto again;
++ }
++ printk(KERN_ERR "check ipu taks fail\n");
++ return;
++ }
++ printk(KERN_ERR "check ipu taks fail\n");
++ return;
++ }
++ err = ipu_queue_task(&task);
++ if (err < 0)
++ printk(KERN_ERR "queue ipu task error\n");
++}
++
++static void get_disp_ipu(cam_data *cam)
++{
++ if (cam->output > 2)
++ disp_ipu = ipu_get_soc(1); /* using DISP4 */
++ else
++ disp_ipu = ipu_get_soc(0);
++}
++
++
++/*!
++ * csi ENC callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t csi_enc_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, csi_buffer_num);
++ schedule_work(&cam->csi_work_struct);
++ csi_buffer_num = (csi_buffer_num == 0) ? 1 : 0;
++ return IRQ_HANDLED;
++}
++
++static int csi_enc_setup(cam_data *cam)
++{
++ ipu_channel_params_t params;
++ u32 pixel_fmt;
++ int err = 0, sensor_protocol = 0;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ if (!cam) {
++ printk(KERN_ERR "cam private is NULL\n");
++ return -ENXIO;
++ }
++
++ memset(&params, 0, sizeof(ipu_channel_params_t));
++ params.csi_mem.csi = cam->csi;
++
++ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi);
++ switch (sensor_protocol) {
++ case IPU_CSI_CLK_MODE_GATED_CLK:
++ case IPU_CSI_CLK_MODE_NONGATED_CLK:
++ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
++ params.csi_mem.interlaced = false;
++ break;
++ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
++ params.csi_mem.interlaced = true;
++ break;
++ default:
++ printk(KERN_ERR "sensor protocol unsupported\n");
++ return -EINVAL;
++ }
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id) {
++ params.csi_mem.mipi_en = true;
++ params.csi_mem.mipi_vc =
++ mipi_csi2_get_virtual_channel(mipi_csi2_info);
++ params.csi_mem.mipi_id =
++ mipi_csi2_get_datatype(mipi_csi2_info);
++
++ mipi_csi2_pixelclk_enable(mipi_csi2_info);
++ } else {
++ params.csi_mem.mipi_en = false;
++ params.csi_mem.mipi_vc = 0;
++ params.csi_mem.mipi_id = 0;
++ }
++ } else {
++ params.csi_mem.mipi_en = false;
++ params.csi_mem.mipi_vc = 0;
++ params.csi_mem.mipi_id = 0;
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ }
++ csi_mem_bufsize =
++ cam->crop_current.width * cam->crop_current.height * 2;
++ cam->vf_bufs_size[0] = PAGE_ALIGN(csi_mem_bufsize);
++ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[0],
++ (dma_addr_t *) &
++ cam->vf_bufs[0],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[0] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_2;
++ }
++ cam->vf_bufs_size[1] = PAGE_ALIGN(csi_mem_bufsize);
++ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[1],
++ (dma_addr_t *) &
++ cam->vf_bufs[1],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[1] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_1;
++ }
++ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]);
++
++ err = ipu_init_channel(cam->ipu, CSI_MEM, &params);
++ if (err != 0) {
++ printk(KERN_ERR "ipu_init_channel %d\n", err);
++ goto out_1;
++ }
++
++ pixel_fmt = IPU_PIX_FMT_UYVY;
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ pixel_fmt, cam->crop_current.width,
++ cam->crop_current.height,
++ cam->crop_current.width, IPU_ROTATE_NONE,
++ cam->vf_bufs[0], cam->vf_bufs[1], 0,
++ cam->offset.u_offset, cam->offset.u_offset);
++ if (err != 0) {
++ printk(KERN_ERR "CSI_MEM output buffer\n");
++ goto out_1;
++ }
++ err = ipu_enable_channel(cam->ipu, CSI_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
++ goto out_1;
++ }
++
++ csi_buffer_num = 0;
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0);
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 1);
++ return err;
++out_1:
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++out_2:
++ return err;
++}
++
++/*!
++ * Enable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_enabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
++ csi_enc_callback, 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering CSI0_OUT_EOF irq\n");
++ return err;
++ }
++
++ INIT_WORK(&cam->csi_work_struct, csi_buf_work_func);
++
++ err = csi_enc_setup(cam);
++ if (err != 0) {
++ printk(KERN_ERR "csi_enc_setup %d\n", err);
++ goto out1;
++ }
++
++ return err;
++out1:
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++ return err;
++}
++
++/*!
++ * bg_overlay_start - start the overlay task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int bg_overlay_start(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (!cam) {
++ printk(KERN_ERR "private is NULL\n");
++ return -EIO;
++ }
++
++ if (cam->overlay_active == true) {
++ pr_debug("already start.\n");
++ return 0;
++ }
++
++ get_disp_ipu(cam);
++
++ out_format = cam->v4l2_fb.fmt.pixelformat;
++ if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) {
++ bpp = 3, csi_mem_bufsize = 3;
++ pr_info("BGR24\n");
++ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) {
++ bpp = 2, csi_mem_bufsize = 2;
++ pr_info("RGB565\n");
++ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) {
++ bpp = 4, csi_mem_bufsize = 4;
++ pr_info("BGR32\n");
++ } else {
++ printk(KERN_ERR
++ "unsupported fix format from the framebuffer.\n");
++ return -EINVAL;
++ }
++
++ offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top +
++ csi_mem_bufsize * cam->win.w.left;
++
++ if (cam->v4l2_fb.base == 0)
++ printk(KERN_ERR "invalid frame buffer address.\n");
++ else
++ offset += (u32) cam->v4l2_fb.base;
++
++ csi_mem_bufsize = cam->win.w.width * cam->win.w.height
++ * csi_mem_bufsize;
++
++ err = csi_enc_enabling_tasks(cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error csi enc enable fail\n");
++ return err;
++ }
++
++ cam->overlay_active = true;
++ return err;
++}
++
++/*!
++ * bg_overlay_stop - stop the overlay task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int bg_overlay_stop(void *private)
++{
++ int err = 0;
++ cam_data *cam = (cam_data *) private;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ if (cam->overlay_active == false)
++ return 0;
++
++ err = ipu_disable_channel(cam->ipu, CSI_MEM, true);
++
++ ipu_uninit_channel(cam->ipu, CSI_MEM);
++
++ csi_buffer_num = 0;
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id)
++ mipi_csi2_pixelclk_disable(mipi_csi2_info);
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ flush_work(&cam->csi_work_struct);
++ cancel_work_sync(&cam->csi_work_struct);
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[0],
++ cam->rot_vf_bufs_vaddr[0],
++ cam->rot_vf_bufs[0]);
++ cam->rot_vf_bufs_vaddr[0] = NULL;
++ cam->rot_vf_bufs[0] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[1],
++ cam->rot_vf_bufs_vaddr[1],
++ cam->rot_vf_bufs[1]);
++ cam->rot_vf_bufs_vaddr[1] = NULL;
++ cam->rot_vf_bufs[1] = 0;
++ }
++
++ cam->overlay_active = false;
++ return err;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int bg_overlay_enable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ return ipu_enable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int bg_overlay_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++
++ return ipu_disable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * function to select bg as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int bg_overlay_sdc_select(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->vf_start_sdc = bg_overlay_start;
++ cam->vf_stop_sdc = bg_overlay_stop;
++ cam->vf_enable_csi = bg_overlay_enable_csi;
++ cam->vf_disable_csi = bg_overlay_disable_csi;
++ cam->overlay_active = false;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(bg_overlay_sdc_select);
++
++/*!
++ * function to de-select bg as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int bg_overlay_sdc_deselect(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->vf_start_sdc = NULL;
++ cam->vf_stop_sdc = NULL;
++ cam->vf_enable_csi = NULL;
++ cam->vf_disable_csi = NULL;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(bg_overlay_sdc_deselect);
++
++/*!
++ * Init background overlay task.
++ *
++ * @return Error code indicating success or failure
++ */
++__init int bg_overlay_sdc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit background overlay task.
++ *
++ * @return Error code indicating success or failure
++ */
++void __exit bg_overlay_sdc_exit(void)
++{
++}
++
++module_init(bg_overlay_sdc_init);
++module_exit(bg_overlay_sdc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_csi_enc.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_csi_enc.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_csi_enc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_csi_enc.c 2014-05-15 20:33:57.134007639 +0200
+@@ -0,0 +1,426 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_csi_enc.c
++ *
++ * @brief CSI Use case for video capture
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/dma-mapping.h>
++#include <linux/ipu.h>
++#include <linux/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++#ifdef CAMERA_DBG
++ #define CAMERA_TRACE(x) (printk)x
++#else
++ #define CAMERA_TRACE(x)
++#endif
++
++/*
++ * Function definitions
++ */
++
++/*!
++ * csi ENC callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t csi_enc_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ if (cam->enc_callback == NULL)
++ return IRQ_HANDLED;
++
++ cam->enc_callback(irq, dev_id);
++ return IRQ_HANDLED;
++}
++
++/*!
++ * CSI ENC enable channel setup function
++ *
++ * @param cam struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_setup(cam_data *cam)
++{
++ ipu_channel_params_t params;
++ u32 pixel_fmt;
++ int err = 0, sensor_protocol = 0;
++ dma_addr_t dummy = cam->dummy_frame.buffer.m.offset;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ CAMERA_TRACE("In csi_enc_setup\n");
++ if (!cam) {
++ printk(KERN_ERR "cam private is NULL\n");
++ return -ENXIO;
++ }
++
++ memset(&params, 0, sizeof(ipu_channel_params_t));
++ params.csi_mem.csi = cam->csi;
++
++ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi);
++ switch (sensor_protocol) {
++ case IPU_CSI_CLK_MODE_GATED_CLK:
++ case IPU_CSI_CLK_MODE_NONGATED_CLK:
++ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
++ params.csi_mem.interlaced = false;
++ break;
++ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
++ params.csi_mem.interlaced = true;
++ break;
++ default:
++ printk(KERN_ERR "sensor protocol unsupported\n");
++ return -EINVAL;
++ }
++
++ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
++ pixel_fmt = IPU_PIX_FMT_YUV420P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420)
++ pixel_fmt = IPU_PIX_FMT_YVU420P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P)
++ pixel_fmt = IPU_PIX_FMT_YUV422P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY)
++ pixel_fmt = IPU_PIX_FMT_UYVY;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
++ pixel_fmt = IPU_PIX_FMT_YUYV;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)
++ pixel_fmt = IPU_PIX_FMT_NV12;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24)
++ pixel_fmt = IPU_PIX_FMT_BGR24;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24)
++ pixel_fmt = IPU_PIX_FMT_RGB24;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565)
++ pixel_fmt = IPU_PIX_FMT_RGB565;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32)
++ pixel_fmt = IPU_PIX_FMT_BGR32;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32)
++ pixel_fmt = IPU_PIX_FMT_RGB32;
++ else {
++ printk(KERN_ERR "format not supported\n");
++ return -EINVAL;
++ }
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id) {
++ params.csi_mem.mipi_en = true;
++ params.csi_mem.mipi_vc =
++ mipi_csi2_get_virtual_channel(mipi_csi2_info);
++ params.csi_mem.mipi_id =
++ mipi_csi2_get_datatype(mipi_csi2_info);
++
++ mipi_csi2_pixelclk_enable(mipi_csi2_info);
++ } else {
++ params.csi_mem.mipi_en = false;
++ params.csi_mem.mipi_vc = 0;
++ params.csi_mem.mipi_id = 0;
++ }
++ } else {
++ params.csi_mem.mipi_en = false;
++ params.csi_mem.mipi_vc = 0;
++ params.csi_mem.mipi_id = 0;
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ err = ipu_init_channel(cam->ipu, CSI_MEM, &params);
++ if (err != 0) {
++ printk(KERN_ERR "ipu_init_channel %d\n", err);
++ return err;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ pixel_fmt, cam->v2f.fmt.pix.width,
++ cam->v2f.fmt.pix.height,
++ cam->v2f.fmt.pix.bytesperline,
++ IPU_ROTATE_NONE,
++ dummy, dummy, 0,
++ cam->offset.u_offset,
++ cam->offset.v_offset);
++ if (err != 0) {
++ printk(KERN_ERR "CSI_MEM output buffer\n");
++ return err;
++ }
++ err = ipu_enable_channel(cam->ipu, CSI_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
++ return err;
++ }
++
++ return err;
++}
++
++/*!
++ * function to update physical buffer address for encorder IDMA channel
++ *
++ * @param eba physical buffer address for encorder IDMA channel
++ * @param buffer_num int buffer 0 or buffer 1
++ *
++ * @return status
++ */
++static int csi_enc_eba_update(struct ipu_soc *ipu, dma_addr_t eba,
++ int *buffer_num)
++{
++ int err = 0;
++
++ pr_debug("eba %x\n", eba);
++ err = ipu_update_channel_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num, eba);
++ if (err != 0) {
++ ipu_clear_buffer_ready(ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num);
++
++ err = ipu_update_channel_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num, eba);
++ if (err != 0) {
++ pr_err("ERROR: v4l2 capture: fail to update "
++ "buf%d\n", *buffer_num);
++ return err;
++ }
++ }
++
++ ipu_select_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER, *buffer_num);
++
++ *buffer_num = (*buffer_num == 0) ? 1 : 0;
++
++ return 0;
++}
++
++/*!
++ * Enable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_enabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++ CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n");
++
++ cam->dummy_frame.vaddress = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->dummy_frame.paddress,
++ GFP_DMA | GFP_KERNEL);
++ if (cam->dummy_frame.vaddress == 0) {
++ pr_err("ERROR: v4l2 capture: Allocate dummy frame "
++ "failed.\n");
++ return -ENOBUFS;
++ }
++ cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE;
++ cam->dummy_frame.buffer.length =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
++ csi_enc_callback, 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering rot irq\n");
++ return err;
++ }
++
++ err = csi_enc_setup(cam);
++ if (err != 0) {
++ printk(KERN_ERR "csi_enc_setup %d\n", err);
++ return err;
++ }
++
++ return err;
++}
++
++/*!
++ * Disable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++static int csi_enc_disabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ err = ipu_disable_channel(cam->ipu, CSI_MEM, true);
++
++ ipu_uninit_channel(cam->ipu, CSI_MEM);
++
++ if (cam->dummy_frame.vaddress != 0) {
++ dma_free_coherent(0, cam->dummy_frame.buffer.length,
++ cam->dummy_frame.vaddress,
++ cam->dummy_frame.paddress);
++ cam->dummy_frame.vaddress = 0;
++ }
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id)
++ mipi_csi2_pixelclk_disable(mipi_csi2_info);
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ return err;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_enable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ return ipu_enable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++
++ return ipu_disable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * function to select CSI ENC as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++int csi_enc_select(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (cam) {
++ cam->enc_update_eba = csi_enc_eba_update;
++ cam->enc_enable = csi_enc_enabling_tasks;
++ cam->enc_disable = csi_enc_disabling_tasks;
++ cam->enc_enable_csi = csi_enc_enable_csi;
++ cam->enc_disable_csi = csi_enc_disable_csi;
++ } else {
++ err = -EIO;
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(csi_enc_select);
++
++/*!
++ * function to de-select CSI ENC as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++int csi_enc_deselect(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (cam) {
++ cam->enc_update_eba = NULL;
++ cam->enc_enable = NULL;
++ cam->enc_disable = NULL;
++ cam->enc_enable_csi = NULL;
++ cam->enc_disable_csi = NULL;
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(csi_enc_deselect);
++
++/*!
++ * Init the Encorder channels
++ *
++ * @return Error code indicating success or failure
++ */
++__init int csi_enc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit the Encorder channels
++ *
++ */
++void __exit csi_enc_exit(void)
++{
++}
++
++module_init(csi_enc_init);
++module_exit(csi_enc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("CSI ENC Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c 2014-05-15 20:33:57.134007639 +0200
+@@ -0,0 +1,642 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++/* * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_foreground_sdc.c
++ *
++ * @brief IPU Use case for PRP-VF
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/console.h>
++#include <linux/ipu.h>
++#include <linux/mxcfb.h>
++#include <linux/mipi_csi2.h>
++
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++#ifdef CAMERA_DBG
++ #define CAMERA_TRACE(x) (printk)x
++#else
++ #define CAMERA_TRACE(x)
++#endif
++
++static int csi_buffer_num, buffer_num;
++static u32 csi_mem_bufsize;
++static struct ipu_soc *disp_ipu;
++static struct fb_info *fbi;
++static struct fb_var_screeninfo fbvar;
++static u32 vf_out_format;
++static void csi_buf_work_func(struct work_struct *work)
++{
++ int err = 0;
++ cam_data *cam =
++ container_of(work, struct _cam_data, csi_work_struct);
++
++ struct ipu_task task;
++ memset(&task, 0, sizeof(task));
++
++ if (csi_buffer_num)
++ task.input.paddr = cam->vf_bufs[0];
++ else
++ task.input.paddr = cam->vf_bufs[1];
++ task.input.width = cam->crop_current.width;
++ task.input.height = cam->crop_current.height;
++ task.input.format = IPU_PIX_FMT_NV12;
++
++ if (buffer_num == 0)
++ task.output.paddr = fbi->fix.smem_start +
++ (fbi->fix.line_length * fbvar.yres);
++ else
++ task.output.paddr = fbi->fix.smem_start;
++ task.output.width = cam->win.w.width;
++ task.output.height = cam->win.w.height;
++ task.output.format = vf_out_format;
++ task.output.rotate = cam->rotation;
++again:
++ err = ipu_check_task(&task);
++ if (err != IPU_CHECK_OK) {
++ if (err > IPU_CHECK_ERR_MIN) {
++ if (err == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) {
++ task.input.crop.w -= 8;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) {
++ task.input.crop.h -= 8;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
++ task.output.width -= 8;
++ task.output.crop.w = task.output.width;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
++ task.output.height -= 8;
++ task.output.crop.h = task.output.height;
++ goto again;
++ }
++ printk(KERN_ERR "check ipu taks fail\n");
++ return;
++ }
++ printk(KERN_ERR "check ipu taks fail\n");
++ return;
++ }
++ err = ipu_queue_task(&task);
++ if (err < 0)
++ printk(KERN_ERR "queue ipu task error\n");
++ ipu_select_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER, buffer_num);
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++}
++
++static void get_disp_ipu(cam_data *cam)
++{
++ if (cam->output > 2)
++ disp_ipu = ipu_get_soc(1); /* using DISP4 */
++ else
++ disp_ipu = ipu_get_soc(0);
++}
++
++/*!
++ * csi ENC callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t csi_enc_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, csi_buffer_num);
++ if ((cam->crop_current.width != cam->win.w.width) ||
++ (cam->crop_current.height != cam->win.w.height) ||
++ (vf_out_format != IPU_PIX_FMT_NV12) ||
++ (cam->rotation >= IPU_ROTATE_VERT_FLIP))
++ schedule_work(&cam->csi_work_struct);
++ csi_buffer_num = (csi_buffer_num == 0) ? 1 : 0;
++ return IRQ_HANDLED;
++}
++
++static int csi_enc_setup(cam_data *cam)
++{
++ ipu_channel_params_t params;
++ int err = 0, sensor_protocol = 0;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ CAMERA_TRACE("In csi_enc_setup\n");
++ if (!cam) {
++ printk(KERN_ERR "cam private is NULL\n");
++ return -ENXIO;
++ }
++
++ memset(&params, 0, sizeof(ipu_channel_params_t));
++ params.csi_mem.csi = cam->csi;
++
++ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi);
++ switch (sensor_protocol) {
++ case IPU_CSI_CLK_MODE_GATED_CLK:
++ case IPU_CSI_CLK_MODE_NONGATED_CLK:
++ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
++ params.csi_mem.interlaced = false;
++ break;
++ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
++ params.csi_mem.interlaced = true;
++ break;
++ default:
++ printk(KERN_ERR "sensor protocol unsupported\n");
++ return -EINVAL;
++ }
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id) {
++ params.csi_mem.mipi_en = true;
++ params.csi_mem.mipi_vc =
++ mipi_csi2_get_virtual_channel(mipi_csi2_info);
++ params.csi_mem.mipi_id =
++ mipi_csi2_get_datatype(mipi_csi2_info);
++
++ mipi_csi2_pixelclk_enable(mipi_csi2_info);
++ } else {
++ params.csi_mem.mipi_en = false;
++ params.csi_mem.mipi_vc = 0;
++ params.csi_mem.mipi_id = 0;
++ }
++ } else {
++ params.csi_mem.mipi_en = false;
++ params.csi_mem.mipi_vc = 0;
++ params.csi_mem.mipi_id = 0;
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ }
++ csi_mem_bufsize = cam->crop_current.width *
++ cam->crop_current.height * 3/2;
++ cam->vf_bufs_size[0] = PAGE_ALIGN(csi_mem_bufsize);
++ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[0],
++ (dma_addr_t *) &
++ cam->vf_bufs[0],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[0] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_2;
++ }
++ cam->vf_bufs_size[1] = PAGE_ALIGN(csi_mem_bufsize);
++ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[1],
++ (dma_addr_t *) &
++ cam->vf_bufs[1],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[1] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_1;
++ }
++ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]);
++
++ err = ipu_init_channel(cam->ipu, CSI_MEM, &params);
++ if (err != 0) {
++ printk(KERN_ERR "ipu_init_channel %d\n", err);
++ goto out_1;
++ }
++
++ if ((cam->crop_current.width == cam->win.w.width) &&
++ (cam->crop_current.height == cam->win.w.height) &&
++ (vf_out_format == IPU_PIX_FMT_NV12) &&
++ (cam->rotation < IPU_ROTATE_VERT_FLIP)) {
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM,
++ IPU_OUTPUT_BUFFER,
++ IPU_PIX_FMT_NV12,
++ cam->crop_current.width,
++ cam->crop_current.height,
++ cam->crop_current.width, IPU_ROTATE_NONE,
++ fbi->fix.smem_start +
++ (fbi->fix.line_length * fbvar.yres),
++ fbi->fix.smem_start, 0,
++ cam->offset.u_offset, cam->offset.u_offset);
++ } else {
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM,
++ IPU_OUTPUT_BUFFER,
++ IPU_PIX_FMT_NV12,
++ cam->crop_current.width,
++ cam->crop_current.height,
++ cam->crop_current.width, IPU_ROTATE_NONE,
++ cam->vf_bufs[0], cam->vf_bufs[1], 0,
++ cam->offset.u_offset, cam->offset.u_offset);
++ }
++ if (err != 0) {
++ printk(KERN_ERR "CSI_MEM output buffer\n");
++ goto out_1;
++ }
++ err = ipu_enable_channel(cam->ipu, CSI_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
++ goto out_1;
++ }
++
++ csi_buffer_num = 0;
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0);
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 1);
++ return err;
++out_1:
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++out_2:
++ return err;
++}
++
++/*!
++ * Enable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_enabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++ CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n");
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
++ csi_enc_callback, 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering CSI0_OUT_EOF irq\n");
++ return err;
++ }
++
++ INIT_WORK(&cam->csi_work_struct, csi_buf_work_func);
++
++ err = csi_enc_setup(cam);
++ if (err != 0) {
++ printk(KERN_ERR "csi_enc_setup %d\n", err);
++ goto out1;
++ }
++
++ return err;
++out1:
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++ return err;
++}
++
++/*
++ * Function definitions
++ */
++
++/*!
++ * foreground_start - start the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int foreground_start(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0, i = 0, screen_size;
++ char *base;
++
++ if (!cam) {
++ printk(KERN_ERR "private is NULL\n");
++ return -EIO;
++ }
++
++ if (cam->overlay_active == true) {
++ pr_debug("already started.\n");
++ return 0;
++ }
++
++ get_disp_ipu(cam);
++
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) ||
++ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++
++ if (fbi == NULL) {
++ printk(KERN_ERR "DISP FG fb not found\n");
++ return -EPERM;
++ }
++
++ fbvar = fbi->var;
++
++ /* Store the overlay frame buffer's original std */
++ cam->fb_origin_std = fbvar.nonstd;
++
++ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) {
++ /* Use DP to do CSC so that we can get better performance */
++ vf_out_format = IPU_PIX_FMT_NV12;
++ fbvar.nonstd = vf_out_format;
++ } else {
++ vf_out_format = IPU_PIX_FMT_RGB565;
++ fbvar.nonstd = 0;
++ }
++
++ fbvar.bits_per_pixel = 16;
++ fbvar.xres = fbvar.xres_virtual = cam->win.w.width;
++ fbvar.yres = cam->win.w.height;
++ fbvar.yres_virtual = cam->win.w.height * 2;
++ fbvar.yoffset = 0;
++ fbvar.vmode &= ~FB_VMODE_YWRAP;
++ fbvar.accel_flags = FB_ACCEL_DOUBLE_FLAG;
++ fbvar.activate |= FB_ACTIVATE_FORCE;
++ fb_set_var(fbi, &fbvar);
++
++ ipu_disp_set_window_pos(disp_ipu, MEM_FG_SYNC, cam->win.w.left,
++ cam->win.w.top);
++
++ /* Fill black color for framebuffer */
++ base = (char *) fbi->screen_base;
++ screen_size = fbi->var.xres * fbi->var.yres;
++ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) {
++ memset(base, 0, screen_size);
++ base += screen_size;
++ for (i = 0; i < screen_size / 2; i++, base++)
++ *base = 0x80;
++ } else {
++ for (i = 0; i < screen_size * 2; i++, base++)
++ *base = 0x00;
++ }
++
++ console_lock();
++ fb_blank(fbi, FB_BLANK_UNBLANK);
++ console_unlock();
++
++ /* correct display ch buffer address */
++ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER,
++ 0, fbi->fix.smem_start +
++ (fbi->fix.line_length * fbvar.yres));
++ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER,
++ 1, fbi->fix.smem_start);
++
++ err = csi_enc_enabling_tasks(cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error csi enc enable fail\n");
++ return err;
++ }
++
++ cam->overlay_active = true;
++ return err;
++
++}
++
++/*!
++ * foreground_stop - stop the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int foreground_stop(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0, i = 0;
++ struct fb_info *fbi = NULL;
++ struct fb_var_screeninfo fbvar;
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ if (cam->overlay_active == false)
++ return 0;
++
++ err = ipu_disable_channel(cam->ipu, CSI_MEM, true);
++
++ ipu_uninit_channel(cam->ipu, CSI_MEM);
++
++ csi_buffer_num = 0;
++ buffer_num = 0;
++
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) ||
++ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++
++ if (fbi == NULL) {
++ printk(KERN_ERR "DISP FG fb not found\n");
++ return -EPERM;
++ }
++
++ console_lock();
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ console_unlock();
++
++ /* Set the overlay frame buffer std to what it is used to be */
++ fbvar = fbi->var;
++ fbvar.accel_flags = FB_ACCEL_TRIPLE_FLAG;
++ fbvar.nonstd = cam->fb_origin_std;
++ fbvar.activate |= FB_ACTIVATE_FORCE;
++ fb_set_var(fbi, &fbvar);
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id)
++ mipi_csi2_pixelclk_disable(mipi_csi2_info);
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ flush_work(&cam->csi_work_struct);
++ cancel_work_sync(&cam->csi_work_struct);
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++
++ cam->overlay_active = false;
++ return err;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int foreground_enable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ return ipu_enable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int foreground_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++
++ return ipu_disable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * function to select foreground as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int foreground_sdc_select(void *private)
++{
++ cam_data *cam;
++ int err = 0;
++ if (private) {
++ cam = (cam_data *) private;
++ cam->vf_start_sdc = foreground_start;
++ cam->vf_stop_sdc = foreground_stop;
++ cam->vf_enable_csi = foreground_enable_csi;
++ cam->vf_disable_csi = foreground_disable_csi;
++ cam->overlay_active = false;
++ } else
++ err = -EIO;
++
++ return err;
++}
++EXPORT_SYMBOL(foreground_sdc_select);
++
++/*!
++ * function to de-select foreground as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return int
++ */
++int foreground_sdc_deselect(void *private)
++{
++ cam_data *cam;
++
++ if (private) {
++ cam = (cam_data *) private;
++ cam->vf_start_sdc = NULL;
++ cam->vf_stop_sdc = NULL;
++ cam->vf_enable_csi = NULL;
++ cam->vf_disable_csi = NULL;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(foreground_sdc_deselect);
++
++/*!
++ * Init viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++__init int foreground_sdc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++void __exit foreground_sdc_exit(void)
++{
++}
++
++module_init(foreground_sdc_init);
++module_exit(foreground_sdc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP VF SDC Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_prp_enc.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_prp_enc.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_prp_enc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_prp_enc.c 2014-05-15 20:33:57.134007639 +0200
+@@ -0,0 +1,603 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_prp_enc.c
++ *
++ * @brief IPU Use case for PRP-ENC
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/ipu.h>
++#include <linux/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++#ifdef CAMERA_DBG
++ #define CAMERA_TRACE(x) (printk)x
++#else
++ #define CAMERA_TRACE(x)
++#endif
++
++static ipu_rotate_mode_t grotation = IPU_ROTATE_NONE;
++
++/*
++ * Function definitions
++ */
++
++/*!
++ * IPU ENC callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prp_enc_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ if (cam->enc_callback == NULL)
++ return IRQ_HANDLED;
++
++ cam->enc_callback(irq, dev_id);
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * PrpENC enable channel setup function
++ *
++ * @param cam struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_enc_setup(cam_data *cam)
++{
++ ipu_channel_params_t enc;
++ int err = 0;
++ dma_addr_t dummy = cam->dummy_frame.buffer.m.offset;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ CAMERA_TRACE("In prp_enc_setup\n");
++ if (!cam) {
++ printk(KERN_ERR "cam private is NULL\n");
++ return -ENXIO;
++ }
++ memset(&enc, 0, sizeof(ipu_channel_params_t));
++
++ ipu_csi_get_window_size(cam->ipu, &enc.csi_prp_enc_mem.in_width,
++ &enc.csi_prp_enc_mem.in_height, cam->csi);
++
++ enc.csi_prp_enc_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
++ enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.width;
++ enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.height;
++ enc.csi_prp_enc_mem.csi = cam->csi;
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.height;
++ enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.width;
++ }
++
++ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV420P;
++ pr_info("YUV420\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YVU420P;
++ pr_info("YVU420\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV422P;
++ pr_info("YUV422P\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUYV;
++ pr_info("YUYV\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_UYVY;
++ pr_info("UYVY\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_NV12;
++ pr_info("NV12\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR24;
++ pr_info("BGR24\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB24;
++ pr_info("RGB24\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB565;
++ pr_info("RGB565\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR32;
++ pr_info("BGR32\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB32;
++ pr_info("RGB32\n");
++ } else {
++ printk(KERN_ERR "format not supported\n");
++ return -EINVAL;
++ }
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id) {
++ enc.csi_prp_enc_mem.mipi_en = true;
++ enc.csi_prp_enc_mem.mipi_vc =
++ mipi_csi2_get_virtual_channel(mipi_csi2_info);
++ enc.csi_prp_enc_mem.mipi_id =
++ mipi_csi2_get_datatype(mipi_csi2_info);
++
++ mipi_csi2_pixelclk_enable(mipi_csi2_info);
++ } else {
++ enc.csi_prp_enc_mem.mipi_en = false;
++ enc.csi_prp_enc_mem.mipi_vc = 0;
++ enc.csi_prp_enc_mem.mipi_id = 0;
++ }
++ } else {
++ enc.csi_prp_enc_mem.mipi_en = false;
++ enc.csi_prp_enc_mem.mipi_vc = 0;
++ enc.csi_prp_enc_mem.mipi_id = 0;
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ err = ipu_init_channel(cam->ipu, CSI_PRP_ENC_MEM, &enc);
++ if (err != 0) {
++ printk(KERN_ERR "ipu_init_channel %d\n", err);
++ return err;
++ }
++
++ grotation = cam->rotation;
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ if (cam->rot_enc_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[0],
++ cam->rot_enc_bufs_vaddr[0],
++ cam->rot_enc_bufs[0]);
++ }
++ if (cam->rot_enc_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[1],
++ cam->rot_enc_bufs_vaddr[1],
++ cam->rot_enc_bufs[1]);
++ }
++ cam->rot_enc_buf_size[0] =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ cam->rot_enc_bufs_vaddr[0] =
++ (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[0],
++ &cam->rot_enc_bufs[0],
++ GFP_DMA | GFP_KERNEL);
++ if (!cam->rot_enc_bufs_vaddr[0]) {
++ printk(KERN_ERR "alloc enc_bufs0\n");
++ return -ENOMEM;
++ }
++ cam->rot_enc_buf_size[1] =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ cam->rot_enc_bufs_vaddr[1] =
++ (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[1],
++ &cam->rot_enc_bufs[1],
++ GFP_DMA | GFP_KERNEL);
++ if (!cam->rot_enc_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[0],
++ cam->rot_enc_bufs_vaddr[0],
++ cam->rot_enc_bufs[0]);
++ cam->rot_enc_bufs_vaddr[0] = NULL;
++ cam->rot_enc_bufs[0] = 0;
++ printk(KERN_ERR "alloc enc_bufs1\n");
++ return -ENOMEM;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ enc.csi_prp_enc_mem.out_pixel_fmt,
++ enc.csi_prp_enc_mem.out_width,
++ enc.csi_prp_enc_mem.out_height,
++ enc.csi_prp_enc_mem.out_width,
++ IPU_ROTATE_NONE,
++ cam->rot_enc_bufs[0],
++ cam->rot_enc_bufs[1], 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "CSI_PRP_ENC_MEM err\n");
++ return err;
++ }
++
++ err = ipu_init_channel(cam->ipu, MEM_ROT_ENC_MEM, NULL);
++ if (err != 0) {
++ printk(KERN_ERR "MEM_ROT_ENC_MEM channel err\n");
++ return err;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_ENC_MEM,
++ IPU_INPUT_BUFFER,
++ enc.csi_prp_enc_mem.out_pixel_fmt,
++ enc.csi_prp_enc_mem.out_width,
++ enc.csi_prp_enc_mem.out_height,
++ enc.csi_prp_enc_mem.out_width,
++ cam->rotation,
++ cam->rot_enc_bufs[0],
++ cam->rot_enc_bufs[1], 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "MEM_ROT_ENC_MEM input buffer\n");
++ return err;
++ }
++
++ err =
++ ipu_init_channel_buffer(cam->ipu, MEM_ROT_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ enc.csi_prp_enc_mem.out_pixel_fmt,
++ enc.csi_prp_enc_mem.out_height,
++ enc.csi_prp_enc_mem.out_width,
++ cam->v2f.fmt.pix.bytesperline /
++ bytes_per_pixel(enc.csi_prp_enc_mem.
++ out_pixel_fmt),
++ IPU_ROTATE_NONE,
++ dummy, dummy, 0,
++ cam->offset.u_offset,
++ cam->offset.v_offset);
++ if (err != 0) {
++ printk(KERN_ERR "MEM_ROT_ENC_MEM output buffer\n");
++ return err;
++ }
++
++ err = ipu_link_channels(cam->ipu,
++ CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM);
++ if (err < 0) {
++ printk(KERN_ERR
++ "link CSI_PRP_ENC_MEM-MEM_ROT_ENC_MEM\n");
++ return err;
++ }
++
++ err = ipu_enable_channel(cam->ipu, CSI_PRP_ENC_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n");
++ return err;
++ }
++ err = ipu_enable_channel(cam->ipu, MEM_ROT_ENC_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel MEM_ROT_ENC_MEM\n");
++ return err;
++ }
++
++ ipu_select_buffer(cam->ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ ipu_select_buffer(cam->ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER, 1);
++ } else {
++ err =
++ ipu_init_channel_buffer(cam->ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ enc.csi_prp_enc_mem.out_pixel_fmt,
++ enc.csi_prp_enc_mem.out_width,
++ enc.csi_prp_enc_mem.out_height,
++ cam->v2f.fmt.pix.bytesperline /
++ bytes_per_pixel(enc.csi_prp_enc_mem.
++ out_pixel_fmt),
++ cam->rotation,
++ dummy, dummy, 0,
++ cam->offset.u_offset,
++ cam->offset.v_offset);
++ if (err != 0) {
++ printk(KERN_ERR "CSI_PRP_ENC_MEM output buffer\n");
++ return err;
++ }
++ err = ipu_enable_channel(cam->ipu, CSI_PRP_ENC_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n");
++ return err;
++ }
++ }
++
++ return err;
++}
++
++/*!
++ * function to update physical buffer address for encorder IDMA channel
++ *
++ * @param eba physical buffer address for encorder IDMA channel
++ * @param buffer_num int buffer 0 or buffer 1
++ *
++ * @return status
++ */
++static int prp_enc_eba_update(struct ipu_soc *ipu, dma_addr_t eba,
++ int *buffer_num)
++{
++ int err = 0;
++
++ pr_debug("eba %x\n", eba);
++ if (grotation >= IPU_ROTATE_90_RIGHT) {
++ err = ipu_update_channel_buffer(ipu, MEM_ROT_ENC_MEM,
++ IPU_OUTPUT_BUFFER, *buffer_num,
++ eba);
++ } else {
++ err = ipu_update_channel_buffer(ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER, *buffer_num,
++ eba);
++ }
++ if (err != 0) {
++ if (grotation >= IPU_ROTATE_90_RIGHT) {
++ ipu_clear_buffer_ready(ipu, MEM_ROT_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ *buffer_num);
++ err = ipu_update_channel_buffer(ipu, MEM_ROT_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ *buffer_num,
++ eba);
++ } else {
++ ipu_clear_buffer_ready(ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ *buffer_num);
++ err = ipu_update_channel_buffer(ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ *buffer_num,
++ eba);
++ }
++
++ if (err != 0) {
++ pr_err("ERROR: v4l2 capture: fail to update "
++ "buf%d\n", *buffer_num);
++ return err;
++ }
++ }
++
++ if (grotation >= IPU_ROTATE_90_RIGHT) {
++ ipu_select_buffer(ipu, MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num);
++ } else {
++ ipu_select_buffer(ipu, CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num);
++ }
++
++ *buffer_num = (*buffer_num == 0) ? 1 : 0;
++ return 0;
++}
++
++/*!
++ * Enable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_enc_enabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++ CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n");
++
++ cam->dummy_frame.vaddress = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->dummy_frame.paddress,
++ GFP_DMA | GFP_KERNEL);
++ if (cam->dummy_frame.vaddress == 0) {
++ pr_err("ERROR: v4l2 capture: Allocate dummy frame "
++ "failed.\n");
++ return -ENOBUFS;
++ }
++ cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE;
++ cam->dummy_frame.buffer.length =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
++
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF,
++ prp_enc_callback, 0, "Mxc Camera", cam);
++ } else {
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF,
++ prp_enc_callback, 0, "Mxc Camera", cam);
++ }
++ if (err != 0) {
++ printk(KERN_ERR "Error registering rot irq\n");
++ return err;
++ }
++
++ err = prp_enc_setup(cam);
++ if (err != 0) {
++ printk(KERN_ERR "prp_enc_setup %d\n", err);
++ return err;
++ }
++
++ return err;
++}
++
++/*!
++ * Disable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++static int prp_enc_disabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF, cam);
++ ipu_unlink_channels(cam->ipu, CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM);
++ }
++
++ err = ipu_disable_channel(cam->ipu, CSI_PRP_ENC_MEM, true);
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT)
++ err |= ipu_disable_channel(cam->ipu, MEM_ROT_ENC_MEM, true);
++
++ ipu_uninit_channel(cam->ipu, CSI_PRP_ENC_MEM);
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT)
++ ipu_uninit_channel(cam->ipu, MEM_ROT_ENC_MEM);
++
++ if (cam->dummy_frame.vaddress != 0) {
++ dma_free_coherent(0, cam->dummy_frame.buffer.length,
++ cam->dummy_frame.vaddress,
++ cam->dummy_frame.paddress);
++ cam->dummy_frame.vaddress = 0;
++ }
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id)
++ mipi_csi2_pixelclk_disable(mipi_csi2_info);
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ return err;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_enc_enable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ return ipu_enable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_enc_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ if (cam->rotation < IPU_ROTATE_90_RIGHT)
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF, cam);
++
++ return ipu_disable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * function to select PRP-ENC as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++int prp_enc_select(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (cam) {
++ cam->enc_update_eba = prp_enc_eba_update;
++ cam->enc_enable = prp_enc_enabling_tasks;
++ cam->enc_disable = prp_enc_disabling_tasks;
++ cam->enc_enable_csi = prp_enc_enable_csi;
++ cam->enc_disable_csi = prp_enc_disable_csi;
++ } else {
++ err = -EIO;
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(prp_enc_select);
++
++/*!
++ * function to de-select PRP-ENC as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++int prp_enc_deselect(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (cam) {
++ cam->enc_update_eba = NULL;
++ cam->enc_enable = NULL;
++ cam->enc_disable = NULL;
++ cam->enc_enable_csi = NULL;
++ cam->enc_disable_csi = NULL;
++ if (cam->rot_enc_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[0],
++ cam->rot_enc_bufs_vaddr[0],
++ cam->rot_enc_bufs[0]);
++ cam->rot_enc_bufs_vaddr[0] = NULL;
++ cam->rot_enc_bufs[0] = 0;
++ }
++ if (cam->rot_enc_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[1],
++ cam->rot_enc_bufs_vaddr[1],
++ cam->rot_enc_bufs[1]);
++ cam->rot_enc_bufs_vaddr[1] = NULL;
++ cam->rot_enc_bufs[1] = 0;
++ }
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(prp_enc_deselect);
++
++/*!
++ * Init the Encorder channels
++ *
++ * @return Error code indicating success or failure
++ */
++__init int prp_enc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit the Encorder channels
++ *
++ */
++void __exit prp_enc_exit(void)
++{
++}
++
++module_init(prp_enc_init);
++module_exit(prp_enc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP ENC Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_prp_sw.h linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_prp_sw.h
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_prp_sw.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_prp_sw.h 2014-05-15 20:33:57.134007639 +0200
+@@ -0,0 +1,43 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_prp_sw.h
++ *
++ * @brief This file contains the IPU PRP use case driver header.
++ *
++ * @ingroup IPU
++ */
++
++#ifndef _INCLUDE_IPU__PRP_SW_H_
++#define _INCLUDE_IPU__PRP_SW_H_
++
++int csi_enc_select(void *private);
++int csi_enc_deselect(void *private);
++int prp_enc_select(void *private);
++int prp_enc_deselect(void *private);
++#ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++int prp_vf_sdc_select(void *private);
++int prp_vf_sdc_deselect(void *private);
++int prp_vf_sdc_select_bg(void *private);
++int prp_vf_sdc_deselect_bg(void *private);
++#else
++int foreground_sdc_select(void *private);
++int foreground_sdc_deselect(void *private);
++int bg_overlay_sdc_select(void *private);
++int bg_overlay_sdc_deselect(void *private);
++#endif
++int prp_still_select(void *private);
++int prp_still_deselect(void *private);
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c 2014-05-15 20:33:57.138007668 +0200
+@@ -0,0 +1,529 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_prp_vf_sdc_bg.c
++ *
++ * @brief IPU Use case for PRP-VF back-ground
++ *
++ * @ingroup IPU
++ */
++#include <linux/dma-mapping.h>
++#include <linux/fb.h>
++#include <linux/ipu.h>
++#include <linux/module.h>
++#include <mach/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++static int buffer_num;
++static int buffer_ready;
++static struct ipu_soc *disp_ipu;
++
++static void get_disp_ipu(cam_data *cam)
++{
++ if (cam->output > 2)
++ disp_ipu = ipu_get_soc(1); /* using DISP4 */
++ else
++ disp_ipu = ipu_get_soc(0);
++}
++
++/*
++ * Function definitions
++ */
++
++/*!
++ * SDC V-Sync callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prpvf_sdc_vsync_callback(int irq, void *dev_id)
++{
++ cam_data *cam = dev_id;
++ if (buffer_ready > 0) {
++ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ buffer_ready--;
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * VF EOF callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prpvf_vf_eof_callback(int irq, void *dev_id)
++{
++ cam_data *cam = dev_id;
++ pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num);
++
++ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_INPUT_BUFFER, buffer_num);
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, buffer_num);
++ buffer_ready++;
++ return IRQ_HANDLED;
++}
++
++/*!
++ * prpvf_start - start the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int prpvf_start(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ ipu_channel_params_t vf;
++ u32 format;
++ u32 offset;
++ u32 bpp, size = 3;
++ int err = 0;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ if (!cam) {
++ printk(KERN_ERR "private is NULL\n");
++ return -EIO;
++ }
++
++ if (cam->overlay_active == true) {
++ pr_debug("already start.\n");
++ return 0;
++ }
++
++ get_disp_ipu(cam);
++
++ format = cam->v4l2_fb.fmt.pixelformat;
++ if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) {
++ bpp = 3, size = 3;
++ pr_info("BGR24\n");
++ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) {
++ bpp = 2, size = 2;
++ pr_info("RGB565\n");
++ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) {
++ bpp = 4, size = 4;
++ pr_info("BGR32\n");
++ } else {
++ printk(KERN_ERR
++ "unsupported fix format from the framebuffer.\n");
++ return -EINVAL;
++ }
++
++ offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top +
++ size * cam->win.w.left;
++
++ if (cam->v4l2_fb.base == 0)
++ printk(KERN_ERR "invalid frame buffer address.\n");
++ else
++ offset += (u32) cam->v4l2_fb.base;
++
++ memset(&vf, 0, sizeof(ipu_channel_params_t));
++ ipu_csi_get_window_size(cam->ipu, &vf.csi_prp_vf_mem.in_width,
++ &vf.csi_prp_vf_mem.in_height, cam->csi);
++ vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
++ vf.csi_prp_vf_mem.out_width = cam->win.w.width;
++ vf.csi_prp_vf_mem.out_height = cam->win.w.height;
++ vf.csi_prp_vf_mem.csi = cam->csi;
++ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
++ vf.csi_prp_vf_mem.out_width = cam->win.w.height;
++ vf.csi_prp_vf_mem.out_height = cam->win.w.width;
++ }
++ vf.csi_prp_vf_mem.out_pixel_fmt = format;
++ size = cam->win.w.width * cam->win.w.height * size;
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id) {
++ vf.csi_prp_vf_mem.mipi_en = true;
++ vf.csi_prp_vf_mem.mipi_vc =
++ mipi_csi2_get_virtual_channel(mipi_csi2_info);
++ vf.csi_prp_vf_mem.mipi_id =
++ mipi_csi2_get_datatype(mipi_csi2_info);
++
++ mipi_csi2_pixelclk_enable(mipi_csi2_info);
++ } else {
++ vf.csi_prp_vf_mem.mipi_en = false;
++ vf.csi_prp_vf_mem.mipi_vc = 0;
++ vf.csi_prp_vf_mem.mipi_id = 0;
++ }
++ } else {
++ vf.csi_prp_vf_mem.mipi_en = false;
++ vf.csi_prp_vf_mem.mipi_vc = 0;
++ vf.csi_prp_vf_mem.mipi_id = 0;
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ err = ipu_init_channel(cam->ipu, CSI_PRP_VF_MEM, &vf);
++ if (err != 0)
++ goto out_4;
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
++ }
++ cam->vf_bufs_size[0] = PAGE_ALIGN(size);
++ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[0],
++ &cam->vf_bufs[0],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[0] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_3;
++ }
++ cam->vf_bufs_size[1] = PAGE_ALIGN(size);
++ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[1],
++ &cam->vf_bufs[1],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[1] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_3;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ format, vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ IPU_ROTATE_NONE,
++ cam->vf_bufs[0],
++ cam->vf_bufs[1],
++ 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n");
++ goto out_3;
++ }
++ err = ipu_init_channel(cam->ipu, MEM_ROT_VF_MEM, NULL);
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n");
++ goto out_3;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_INPUT_BUFFER,
++ format, vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ cam->vf_rotation,
++ cam->vf_bufs[0],
++ cam->vf_bufs[1],
++ 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n");
++ goto out_2;
++ }
++
++ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ format,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ cam->overlay_fb->var.xres * bpp,
++ IPU_ROTATE_NONE,
++ offset, 0, 0, 0, 0);
++
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
++ goto out_2;
++ }
++ } else {
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ format,
++ vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ cam->overlay_fb->var.xres * bpp,
++ IPU_ROTATE_NONE,
++ offset, 0, 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
++ goto out_2;
++ }
++ }
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF,
++ prpvf_vf_eof_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR
++ "Error registering IPU_IRQ_PRP_VF_OUT_EOF irq.\n");
++ goto out_2;
++ }
++
++ ipu_clear_irq(disp_ipu, IPU_IRQ_BG_SF_END);
++ err = ipu_request_irq(disp_ipu, IPU_IRQ_BG_SF_END,
++ prpvf_sdc_vsync_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering IPU_IRQ_BG_SF_END irq.\n");
++ goto out_1;
++ }
++
++ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM);
++ ipu_enable_channel(cam->ipu, MEM_ROT_VF_MEM);
++
++ buffer_num = 0;
++ buffer_ready = 0;
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0);
++
++ cam->overlay_active = true;
++ return err;
++
++out_1:
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, NULL);
++out_2:
++ ipu_uninit_channel(cam->ipu, MEM_ROT_VF_MEM);
++out_3:
++ ipu_uninit_channel(cam->ipu, CSI_PRP_VF_MEM);
++out_4:
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[0],
++ cam->rot_vf_bufs_vaddr[0],
++ cam->rot_vf_bufs[0]);
++ cam->rot_vf_bufs_vaddr[0] = NULL;
++ cam->rot_vf_bufs[0] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[1],
++ cam->rot_vf_bufs_vaddr[1],
++ cam->rot_vf_bufs[1]);
++ cam->rot_vf_bufs_vaddr[1] = NULL;
++ cam->rot_vf_bufs[1] = 0;
++ }
++ return err;
++}
++
++/*!
++ * prpvf_stop - stop the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int prpvf_stop(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ if (cam->overlay_active == false)
++ return 0;
++
++ ipu_free_irq(disp_ipu, IPU_IRQ_BG_SF_END, cam);
++
++ ipu_disable_channel(cam->ipu, CSI_PRP_VF_MEM, true);
++ ipu_disable_channel(cam->ipu, MEM_ROT_VF_MEM, true);
++ ipu_uninit_channel(cam->ipu, CSI_PRP_VF_MEM);
++ ipu_uninit_channel(cam->ipu, MEM_ROT_VF_MEM);
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id)
++ mipi_csi2_pixelclk_disable(mipi_csi2_info);
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[0],
++ cam->rot_vf_bufs_vaddr[0],
++ cam->rot_vf_bufs[0]);
++ cam->rot_vf_bufs_vaddr[0] = NULL;
++ cam->rot_vf_bufs[0] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[1],
++ cam->rot_vf_bufs_vaddr[1],
++ cam->rot_vf_bufs[1]);
++ cam->rot_vf_bufs_vaddr[1] = NULL;
++ cam->rot_vf_bufs[1] = 0;
++ }
++
++ buffer_num = 0;
++ buffer_ready = 0;
++ cam->overlay_active = false;
++ return 0;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_vf_enable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ return ipu_enable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_vf_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, cam);
++
++ return ipu_disable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * function to select PRP-VF as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int prp_vf_sdc_select_bg(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->vf_start_sdc = prpvf_start;
++ cam->vf_stop_sdc = prpvf_stop;
++ cam->vf_enable_csi = prp_vf_enable_csi;
++ cam->vf_disable_csi = prp_vf_disable_csi;
++ cam->overlay_active = false;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(prp_vf_sdc_select_bg);
++
++/*!
++ * function to de-select PRP-VF as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int prp_vf_sdc_deselect_bg(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->vf_start_sdc = NULL;
++ cam->vf_stop_sdc = NULL;
++ cam->vf_enable_csi = NULL;
++ cam->vf_disable_csi = NULL;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(prp_vf_sdc_deselect_bg);
++
++/*!
++ * Init viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++__init int prp_vf_sdc_init_bg(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++void __exit prp_vf_sdc_exit_bg(void)
++{
++}
++
++module_init(prp_vf_sdc_init_bg);
++module_exit(prp_vf_sdc_exit_bg);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c 2014-05-15 20:33:57.138007668 +0200
+@@ -0,0 +1,590 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++/* * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_prp_vf_sdc.c
++ *
++ * @brief IPU Use case for PRP-VF
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/console.h>
++#include <linux/ipu.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <mach/hardware.h>
++#include <mach/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++static int buffer_num;
++static struct ipu_soc *disp_ipu;
++
++static void get_disp_ipu(cam_data *cam)
++{
++ if (cam->output > 2)
++ disp_ipu = ipu_get_soc(1); /* using DISP4 */
++ else
++ disp_ipu = ipu_get_soc(0);
++}
++
++static irqreturn_t prpvf_rot_eof_callback(int irq, void *dev_id)
++{
++ cam_data *cam = dev_id;
++ pr_debug("buffer_num %d\n", buffer_num);
++
++ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
++ ipu_select_buffer(disp_ipu, MEM_FG_SYNC,
++ IPU_INPUT_BUFFER, buffer_num);
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER, buffer_num);
++ } else {
++ ipu_select_buffer(disp_ipu, MEM_FG_SYNC,
++ IPU_INPUT_BUFFER, buffer_num);
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, buffer_num);
++ }
++ return IRQ_HANDLED;
++}
++/*
++ * Function definitions
++ */
++
++/*!
++ * prpvf_start - start the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int prpvf_start(void *private)
++{
++ struct fb_var_screeninfo fbvar;
++ struct fb_info *fbi = NULL;
++ cam_data *cam = (cam_data *) private;
++ ipu_channel_params_t vf;
++ u32 vf_out_format = 0;
++ u32 size = 2, temp = 0;
++ int err = 0, i = 0;
++ short *tmp, color;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ if (!cam) {
++ printk(KERN_ERR "private is NULL\n");
++ return -EIO;
++ }
++
++ if (cam->overlay_active == true) {
++ pr_debug("already started.\n");
++ return 0;
++ }
++
++ get_disp_ipu(cam);
++
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) ||
++ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++
++ if (fbi == NULL) {
++ printk(KERN_ERR "DISP FG fb not found\n");
++ return -EPERM;
++ }
++
++ fbvar = fbi->var;
++
++ /* Store the overlay frame buffer's original std */
++ cam->fb_origin_std = fbvar.nonstd;
++
++ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) {
++ /* Use DP to do CSC so that we can get better performance */
++ vf_out_format = IPU_PIX_FMT_UYVY;
++ fbvar.nonstd = vf_out_format;
++ color = 0x80;
++ } else {
++ vf_out_format = IPU_PIX_FMT_RGB565;
++ fbvar.nonstd = 0;
++ color = 0x0;
++ }
++
++ fbvar.bits_per_pixel = 16;
++ fbvar.xres = fbvar.xres_virtual = cam->win.w.width;
++ fbvar.yres = cam->win.w.height;
++ fbvar.yres_virtual = cam->win.w.height * 2;
++ fbvar.yoffset = 0;
++ fbvar.accel_flags = FB_ACCEL_DOUBLE_FLAG;
++ fbvar.activate |= FB_ACTIVATE_FORCE;
++ fb_set_var(fbi, &fbvar);
++
++ ipu_disp_set_window_pos(disp_ipu, MEM_FG_SYNC, cam->win.w.left,
++ cam->win.w.top);
++
++ /* Fill black color for framebuffer */
++ tmp = (short *) fbi->screen_base;
++ for (i = 0; i < (fbi->fix.line_length * fbi->var.yres)/2;
++ i++, tmp++)
++ *tmp = color;
++
++ console_lock();
++ fb_blank(fbi, FB_BLANK_UNBLANK);
++ console_unlock();
++
++ /* correct display ch buffer address */
++ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER,
++ 0, fbi->fix.smem_start +
++ (fbi->fix.line_length * fbvar.yres));
++ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER,
++ 1, fbi->fix.smem_start);
++
++ memset(&vf, 0, sizeof(ipu_channel_params_t));
++ ipu_csi_get_window_size(cam->ipu, &vf.csi_prp_vf_mem.in_width,
++ &vf.csi_prp_vf_mem.in_height, cam->csi);
++ vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
++ vf.csi_prp_vf_mem.out_width = cam->win.w.width;
++ vf.csi_prp_vf_mem.out_height = cam->win.w.height;
++ vf.csi_prp_vf_mem.csi = cam->csi;
++ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
++ vf.csi_prp_vf_mem.out_width = cam->win.w.height;
++ vf.csi_prp_vf_mem.out_height = cam->win.w.width;
++ }
++ vf.csi_prp_vf_mem.out_pixel_fmt = vf_out_format;
++ size = cam->win.w.width * cam->win.w.height * size;
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id) {
++ vf.csi_prp_vf_mem.mipi_en = true;
++ vf.csi_prp_vf_mem.mipi_vc =
++ mipi_csi2_get_virtual_channel(mipi_csi2_info);
++ vf.csi_prp_vf_mem.mipi_id =
++ mipi_csi2_get_datatype(mipi_csi2_info);
++
++ mipi_csi2_pixelclk_enable(mipi_csi2_info);
++ } else {
++ vf.csi_prp_vf_mem.mipi_en = false;
++ vf.csi_prp_vf_mem.mipi_vc = 0;
++ vf.csi_prp_vf_mem.mipi_id = 0;
++ }
++ } else {
++ vf.csi_prp_vf_mem.mipi_en = false;
++ vf.csi_prp_vf_mem.mipi_vc = 0;
++ vf.csi_prp_vf_mem.mipi_id = 0;
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ err = ipu_init_channel(cam->ipu, CSI_PRP_VF_MEM, &vf);
++ if (err != 0)
++ goto out_5;
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ }
++ cam->vf_bufs_size[0] = PAGE_ALIGN(size);
++ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[0],
++ (dma_addr_t *) &
++ cam->vf_bufs[0],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[0] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_4;
++ }
++ cam->vf_bufs_size[1] = PAGE_ALIGN(size);
++ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[1],
++ (dma_addr_t *) &
++ cam->vf_bufs[1],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[1] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_3;
++ }
++ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]);
++
++ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
++ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ vf_out_format,
++ vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ IPU_ROTATE_NONE,
++ cam->vf_bufs[0], cam->vf_bufs[1],
++ 0, 0, 0);
++ if (err != 0)
++ goto out_3;
++
++ err = ipu_init_channel(cam->ipu, MEM_ROT_VF_MEM, NULL);
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM channel\n");
++ goto out_3;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_INPUT_BUFFER,
++ vf_out_format,
++ vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ cam->vf_rotation,
++ cam->vf_bufs[0],
++ cam->vf_bufs[1],
++ 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n");
++ goto out_2;
++ }
++
++ if (cam->vf_rotation < IPU_ROTATE_90_RIGHT) {
++ temp = vf.csi_prp_vf_mem.out_width;
++ vf.csi_prp_vf_mem.out_width =
++ vf.csi_prp_vf_mem.out_height;
++ vf.csi_prp_vf_mem.out_height = temp;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ vf_out_format,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ IPU_ROTATE_NONE,
++ fbi->fix.smem_start +
++ (fbi->fix.line_length *
++ fbi->var.yres),
++ fbi->fix.smem_start, 0, 0, 0);
++
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
++ goto out_2;
++ }
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF,
++ prpvf_rot_eof_callback,
++ 0, "Mxc Camera", cam);
++ if (err < 0) {
++ printk(KERN_ERR "Error request irq:IPU_IRQ_PRP_VF_ROT_OUT_EOF\n");
++ goto out_2;
++ }
++
++ err = ipu_link_channels(cam->ipu,
++ CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
++ if (err < 0) {
++ printk(KERN_ERR
++ "Error link CSI_PRP_VF_MEM-MEM_ROT_VF_MEM\n");
++ goto out_1;
++ }
++
++ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM);
++ ipu_enable_channel(cam->ipu, MEM_ROT_VF_MEM);
++
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, 1);
++ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ } else {
++ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ vf_out_format, cam->win.w.width,
++ cam->win.w.height,
++ cam->win.w.width,
++ cam->vf_rotation,
++ fbi->fix.smem_start +
++ (fbi->fix.line_length *
++ fbi->var.yres),
++ fbi->fix.smem_start, 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n");
++ goto out_4;
++ }
++ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF,
++ prpvf_rot_eof_callback,
++ 0, "Mxc Camera", cam);
++ if (err < 0) {
++ printk(KERN_ERR "Error request irq:IPU_IRQ_PRP_VF_OUT_EOF\n");
++ goto out_4;
++ }
++
++ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM);
++
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ }
++
++ cam->overlay_active = true;
++ return err;
++
++out_1:
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, NULL);
++out_2:
++ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP)
++ ipu_uninit_channel(cam->ipu, MEM_ROT_VF_MEM);
++out_3:
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++out_4:
++ ipu_uninit_channel(cam->ipu, CSI_PRP_VF_MEM);
++out_5:
++ return err;
++}
++
++/*!
++ * prpvf_stop - stop the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int prpvf_stop(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0, i = 0;
++ struct fb_info *fbi = NULL;
++ struct fb_var_screeninfo fbvar;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++
++ if (cam->overlay_active == false)
++ return 0;
++
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) ||
++ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++
++ if (fbi == NULL) {
++ printk(KERN_ERR "DISP FG fb not found\n");
++ return -EPERM;
++ }
++
++ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
++ ipu_unlink_channels(cam->ipu, CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF, cam);
++ }
++ buffer_num = 0;
++
++ ipu_disable_channel(cam->ipu, CSI_PRP_VF_MEM, true);
++
++ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
++ ipu_disable_channel(cam->ipu, MEM_ROT_VF_MEM, true);
++ ipu_uninit_channel(cam->ipu, MEM_ROT_VF_MEM);
++ }
++ ipu_uninit_channel(cam->ipu, CSI_PRP_VF_MEM);
++
++ console_lock();
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ console_unlock();
++
++ /* Set the overlay frame buffer std to what it is used to be */
++ fbvar = fbi->var;
++ fbvar.accel_flags = FB_ACCEL_TRIPLE_FLAG;
++ fbvar.nonstd = cam->fb_origin_std;
++ fbvar.activate |= FB_ACTIVATE_FORCE;
++ fb_set_var(fbi, &fbvar);
++
++#ifdef CONFIG_MXC_MIPI_CSI2
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (mipi_csi2_info) {
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ ipu_id = mipi_csi2_get_bind_ipu(mipi_csi2_info);
++ csi_id = mipi_csi2_get_bind_csi(mipi_csi2_info);
++
++ if (cam->ipu == ipu_get_soc(ipu_id)
++ && cam->csi == csi_id)
++ mipi_csi2_pixelclk_disable(mipi_csi2_info);
++ }
++ } else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++#endif
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++
++ cam->overlay_active = false;
++ return err;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_vf_enable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ return ipu_enable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_vf_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ if (cam->vf_rotation < IPU_ROTATE_VERT_FLIP)
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, cam);
++
++ return ipu_disable_csi(cam->ipu, cam->csi);
++}
++
++/*!
++ * function to select PRP-VF as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int prp_vf_sdc_select(void *private)
++{
++ cam_data *cam;
++ int err = 0;
++ if (private) {
++ cam = (cam_data *) private;
++ cam->vf_start_sdc = prpvf_start;
++ cam->vf_stop_sdc = prpvf_stop;
++ cam->vf_enable_csi = prp_vf_enable_csi;
++ cam->vf_disable_csi = prp_vf_disable_csi;
++ cam->overlay_active = false;
++ } else
++ err = -EIO;
++
++ return err;
++}
++EXPORT_SYMBOL(prp_vf_sdc_select);
++
++/*!
++ * function to de-select PRP-VF as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return int
++ */
++int prp_vf_sdc_deselect(void *private)
++{
++ cam_data *cam;
++
++ if (private) {
++ cam = (cam_data *) private;
++ cam->vf_start_sdc = NULL;
++ cam->vf_stop_sdc = NULL;
++ cam->vf_enable_csi = NULL;
++ cam->vf_disable_csi = NULL;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(prp_vf_sdc_deselect);
++
++/*!
++ * Init viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++__init int prp_vf_sdc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++void __exit prp_vf_sdc_exit(void)
++{
++}
++
++module_init(prp_vf_sdc_init);
++module_exit(prp_vf_sdc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP VF SDC Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_still.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_still.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ipu_still.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ipu_still.c 2014-05-15 20:33:57.138007668 +0200
+@@ -0,0 +1,268 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_still.c
++ *
++ * @brief IPU Use case for still image capture
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/module.h>
++#include <linux/semaphore.h>
++#include <linux/sched.h>
++#include <linux/ipu.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++static int callback_eof_flag;
++#ifndef CONFIG_MXC_IPU_V1
++static int buffer_num;
++#endif
++
++#ifdef CONFIG_MXC_IPU_V1
++static int callback_flag;
++/*
++ * Function definitions
++ */
++/*!
++ * CSI EOF callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prp_csi_eof_callback(int irq, void *dev_id)
++{
++ cam_data *cam = devid;
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ callback_flag%2 ? 1 : 0);
++ if (callback_flag == 0)
++ ipu_enable_channel(cam->ipu, CSI_MEM);
++
++ callback_flag++;
++ return IRQ_HANDLED;
++}
++#endif
++
++/*!
++ * CSI callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prp_still_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ callback_eof_flag++;
++ if (callback_eof_flag < 5) {
++#ifndef CONFIG_MXC_IPU_V1
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++ ipu_select_buffer(cam->ipu, CSI_MEM,
++ IPU_OUTPUT_BUFFER, buffer_num);
++#endif
++ } else {
++ cam->still_counter++;
++ wake_up_interruptible(&cam->still_queue);
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * start csi->mem task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_still_start(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ u32 pixel_fmt;
++ int err;
++ ipu_channel_params_t params;
++
++ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
++ pixel_fmt = IPU_PIX_FMT_YUV420P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)
++ pixel_fmt = IPU_PIX_FMT_NV12;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P)
++ pixel_fmt = IPU_PIX_FMT_YUV422P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY)
++ pixel_fmt = IPU_PIX_FMT_UYVY;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
++ pixel_fmt = IPU_PIX_FMT_YUYV;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24)
++ pixel_fmt = IPU_PIX_FMT_BGR24;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24)
++ pixel_fmt = IPU_PIX_FMT_RGB24;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565)
++ pixel_fmt = IPU_PIX_FMT_RGB565;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32)
++ pixel_fmt = IPU_PIX_FMT_BGR32;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32)
++ pixel_fmt = IPU_PIX_FMT_RGB32;
++ else {
++ printk(KERN_ERR "format not supported\n");
++ return -EINVAL;
++ }
++
++ memset(&params, 0, sizeof(params));
++ err = ipu_init_channel(cam->ipu, CSI_MEM, &params);
++ if (err != 0)
++ return err;
++
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ pixel_fmt, cam->v2f.fmt.pix.width,
++ cam->v2f.fmt.pix.height,
++ cam->v2f.fmt.pix.width, IPU_ROTATE_NONE,
++ cam->still_buf[0], cam->still_buf[1], 0,
++ 0, 0);
++ if (err != 0)
++ return err;
++
++#ifdef CONFIG_MXC_IPU_V1
++ ipu_clear_irq(IPU_IRQ_SENSOR_OUT_EOF);
++ err = ipu_request_irq(IPU_IRQ_SENSOR_OUT_EOF, prp_still_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering irq.\n");
++ return err;
++ }
++ callback_flag = 0;
++ callback_eof_flag = 0;
++ ipu_clear_irq(IPU_IRQ_SENSOR_EOF);
++ err = ipu_request_irq(IPU_IRQ_SENSOR_EOF, prp_csi_eof_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error IPU_IRQ_SENSOR_EOF\n");
++ return err;
++ }
++#else
++ callback_eof_flag = 0;
++ buffer_num = 0;
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
++ prp_still_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering irq.\n");
++ return err;
++ }
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0);
++ ipu_enable_channel(cam->ipu, CSI_MEM);
++ ipu_enable_csi(cam->ipu, cam->csi);
++#endif
++
++ return err;
++}
++
++/*!
++ * stop csi->mem encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_still_stop(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++#ifdef CONFIG_MXC_IPU_V1
++ ipu_free_irq(IPU_IRQ_SENSOR_EOF, NULL);
++ ipu_free_irq(IPU_IRQ_SENSOR_OUT_EOF, cam);
++#else
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++#endif
++
++ ipu_disable_csi(cam->ipu, cam->csi);
++ ipu_disable_channel(cam->ipu, CSI_MEM, true);
++ ipu_uninit_channel(cam->ipu, CSI_MEM);
++
++ return err;
++}
++
++/*!
++ * function to select CSI_MEM as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++int prp_still_select(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->csi_start = prp_still_start;
++ cam->csi_stop = prp_still_stop;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(prp_still_select);
++
++/*!
++ * function to de-select CSI_MEM as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++int prp_still_deselect(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ err = prp_still_stop(cam);
++
++ if (cam) {
++ cam->csi_start = NULL;
++ cam->csi_stop = NULL;
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(prp_still_deselect);
++
++/*!
++ * Init the Encorder channels
++ *
++ * @return Error code indicating success or failure
++ */
++__init int prp_still_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit the Encorder channels
++ *
++ */
++void __exit prp_still_exit(void)
++{
++}
++
++module_init(prp_still_init);
++module_exit(prp_still_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP STILL IMAGE Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/Kconfig linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/Kconfig
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/Kconfig 2014-05-15 20:33:57.110007467 +0200
+@@ -0,0 +1,86 @@
++if VIDEO_MXC_CAPTURE
++
++menu "MXC Camera/V4L2 PRP Features support"
++config VIDEO_MXC_IPU_CAMERA
++ bool
++ depends on VIDEO_MXC_CAPTURE && MXC_IPU
++ default y
++
++config VIDEO_MXC_CSI_CAMERA
++ tristate "CSI camera support"
++ depends on VIDEO_MXC_CAPTURE && VIDEO_V4L2
++ ---help---
++ This is the video4linux2 capture driver based on CSI module.
++
++config MXC_CAMERA_OV5640
++ tristate "OmniVision ov5640 camera support"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ ---help---
++ If you plan to use the ov5640 Camera with your MXC system, say Y here.
++
++config MXC_CAMERA_OV5642
++ tristate "OmniVision ov5642 camera support"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ ---help---
++ If you plan to use the ov5642 Camera with your MXC system, say Y here.
++
++config MXC_CAMERA_OV5640_MIPI
++ tristate "OmniVision ov5640 camera support using mipi"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ ---help---
++ If you plan to use the ov5640 Camera with mipi interface in your MXC system, say Y here.
++
++config MXC_TVIN_ADV7180
++ tristate "Analog Device adv7180 TV Decoder Input support"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ ---help---
++ If you plan to use the adv7180 video decoder with your MXC system, say Y here.
++
++choice
++ prompt "Select Overlay Rounting"
++ default MXC_IPU_DEVICE_QUEUE_SDC
++ depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_SYNC_PANEL
++
++config MXC_IPU_DEVICE_QUEUE_SDC
++ tristate "Queue ipu device for overlay library"
++ depends on VIDEO_MXC_IPU_CAMERA
++ ---help---
++ Use case CSI->MEM->IPU DEVICE->SDC:
++ Images from sensor will be frist recieved in memory,then
++ queue to ipu device for processing if needed, and displaying
++ it on synchronous display with SDC use case.
++
++config MXC_IPU_PRP_VF_SDC
++ bool "Pre-Processor VF SDC library"
++ depends on VIDEO_MXC_IPU_CAMERA
++ ---help---
++ Use case PRP_VF_SDC:
++ Preprocessing image from smart sensor for viewfinder and
++ displaying it on synchronous display with SDC use case.
++ If SDC BG is selected, Rotation will not be supported.
++ CSI -> IC (PRP VF) -> MEM
++ MEM -> IC (ROT) -> MEM
++ MEM -> SDC (FG/BG)
++
++endchoice
++
++config MXC_IPU_PRP_ENC
++ tristate "Pre-processor Encoder library"
++ depends on VIDEO_MXC_IPU_CAMERA
++ default y
++ ---help---
++ Use case PRP_ENC:
++ Preprocessing image from smart sensor for encoder.
++ CSI -> IC (PRP ENC) -> MEM
++
++config MXC_IPU_CSI_ENC
++ tristate "IPU CSI Encoder library"
++ depends on VIDEO_MXC_IPU_CAMERA
++ default y
++ ---help---
++ Use case IPU_CSI_ENC:
++ Get raw image with CSI from smart sensor for encoder.
++ CSI -> MEM
++endmenu
++
++endif
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/Makefile linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/Makefile
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/Makefile 2014-05-15 20:33:57.110007467 +0200
+@@ -0,0 +1,21 @@
++obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += fsl_csi.o csi_v4l2_capture.o
++
++ifeq ($(CONFIG_VIDEO_MXC_IPU_CAMERA),y)
++ obj-$(CONFIG_VIDEO_MXC_CAPTURE) += mxc_v4l2_capture.o
++ obj-$(CONFIG_MXC_IPU_PRP_VF_SDC) += ipu_prp_vf_sdc.o ipu_prp_vf_sdc_bg.o
++ obj-$(CONFIG_MXC_IPU_DEVICE_QUEUE_SDC) += ipu_fg_overlay_sdc.o ipu_bg_overlay_sdc.o
++ obj-$(CONFIG_MXC_IPU_PRP_ENC) += ipu_prp_enc.o ipu_still.o
++ obj-$(CONFIG_MXC_IPU_CSI_ENC) += ipu_csi_enc.o ipu_still.o
++endif
++
++ov5640_camera-objs := ov5640.o
++obj-$(CONFIG_MXC_CAMERA_OV5640) += ov5640_camera.o
++
++ov5642_camera-objs := ov5642.o
++obj-$(CONFIG_MXC_CAMERA_OV5642) += ov5642_camera.o
++
++ov5640_camera_mipi-objs := ov5640_mipi.o
++obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI) += ov5640_camera_mipi.o
++
++adv7180_tvin-objs := adv7180.o
++obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c 2014-05-15 20:33:57.138007668 +0200
+@@ -0,0 +1,3109 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file drivers/media/video/mxc/capture/mxc_v4l2_capture.c
++ *
++ * @brief Mxc Video For Linux 2 driver
++ *
++ * @ingroup MXC_V4L2_CAPTURE
++ */
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/semaphore.h>
++#include <linux/pagemap.h>
++#include <linux/vmalloc.h>
++#include <linux/types.h>
++#include <linux/fb.h>
++#include <linux/dma-mapping.h>
++#include <linux/delay.h>
++#include <linux/mxcfb.h>
++#include <linux/of_device.h>
++#include <media/v4l2-chip-ident.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-int-device.h>
++#include <linux/fsl_devices.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++#define init_MUTEX(sem) sema_init(sem, 1)
++
++static struct platform_device_id imx_v4l2_devtype[] = {
++ {
++ .name = "v4l2-capture-imx5",
++ .driver_data = IMX5_V4L2,
++ }, {
++ .name = "v4l2-capture-imx6",
++ .driver_data = IMX6_V4L2,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_v4l2_devtype);
++
++static const struct of_device_id mxc_v4l2_dt_ids[] = {
++ {
++ .compatible = "fsl,imx6q-v4l2-capture",
++ .data = &imx_v4l2_devtype[IMX6_V4L2],
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(of, mxc_v4l2_dt_ids);
++
++static int video_nr = -1;
++
++/*! This data is used for the output to the display. */
++#define MXC_V4L2_CAPTURE_NUM_OUTPUTS 6
++#define MXC_V4L2_CAPTURE_NUM_INPUTS 2
++static struct v4l2_output mxc_capture_outputs[MXC_V4L2_CAPTURE_NUM_OUTPUTS] = {
++ {
++ .index = 0,
++ .name = "DISP3 BG",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 1,
++ .name = "DISP3 BG - DI1",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 2,
++ .name = "DISP3 FG",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 3,
++ .name = "DISP4 BG",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 4,
++ .name = "DISP4 BG - DI1",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 5,
++ .name = "DISP4 FG",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++};
++
++static struct v4l2_input mxc_capture_inputs[MXC_V4L2_CAPTURE_NUM_INPUTS] = {
++ {
++ .index = 0,
++ .name = "CSI IC MEM",
++ .type = V4L2_INPUT_TYPE_CAMERA,
++ .audioset = 0,
++ .tuner = 0,
++ .std = V4L2_STD_UNKNOWN,
++ .status = 0,
++ },
++ {
++ .index = 1,
++ .name = "CSI MEM",
++ .type = V4L2_INPUT_TYPE_CAMERA,
++ .audioset = 0,
++ .tuner = 0,
++ .std = V4L2_STD_UNKNOWN,
++ .status = V4L2_IN_ST_NO_POWER,
++ },
++};
++
++/*! List of TV input video formats supported. The video formats is corresponding
++ * to the v4l2_id in video_fmt_t.
++ * Currently, only PAL and NTSC is supported. Needs to be expanded in the
++ * future.
++ */
++typedef enum {
++ TV_NTSC = 0, /*!< Locked on (M) NTSC video signal. */
++ TV_PAL, /*!< (B, G, H, I, N)PAL video signal. */
++ TV_NOT_LOCKED, /*!< Not locked on a signal. */
++} video_fmt_idx;
++
++/*! Number of video standards supported (including 'not locked' signal). */
++#define TV_STD_MAX (TV_NOT_LOCKED + 1)
++
++/*! Video format structure. */
++typedef struct {
++ int v4l2_id; /*!< Video for linux ID. */
++ char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */
++ u16 raw_width; /*!< Raw width. */
++ u16 raw_height; /*!< Raw height. */
++ u16 active_width; /*!< Active width. */
++ u16 active_height; /*!< Active height. */
++ u16 active_top; /*!< Active top. */
++ u16 active_left; /*!< Active left. */
++} video_fmt_t;
++
++/*!
++ * Description of video formats supported.
++ *
++ * PAL: raw=720x625, active=720x576.
++ * NTSC: raw=720x525, active=720x480.
++ */
++static video_fmt_t video_fmts[] = {
++ { /*! NTSC */
++ .v4l2_id = V4L2_STD_NTSC,
++ .name = "NTSC",
++ .raw_width = 720, /* SENS_FRM_WIDTH */
++ .raw_height = 525, /* SENS_FRM_HEIGHT */
++ .active_width = 720, /* ACT_FRM_WIDTH */
++ .active_height = 480, /* ACT_FRM_HEIGHT */
++ .active_top = 13,
++ .active_left = 0,
++ },
++ { /*! (B, G, H, I, N) PAL */
++ .v4l2_id = V4L2_STD_PAL,
++ .name = "PAL",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ .active_top = 0,
++ .active_left = 0,
++ },
++ { /*! Unlocked standard */
++ .v4l2_id = V4L2_STD_ALL,
++ .name = "Autodetect",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ .active_top = 0,
++ .active_left = 0,
++ },
++};
++
++/*!* Standard index of TV. */
++static video_fmt_idx video_index = TV_NOT_LOCKED;
++
++static int mxc_v4l2_master_attach(struct v4l2_int_device *slave);
++static void mxc_v4l2_master_detach(struct v4l2_int_device *slave);
++static int start_preview(cam_data *cam);
++static int stop_preview(cam_data *cam);
++
++/*! Information about this driver. */
++static struct v4l2_int_master mxc_v4l2_master = {
++ .attach = mxc_v4l2_master_attach,
++ .detach = mxc_v4l2_master_detach,
++};
++
++/***************************************************************************
++ * Functions for handling Frame buffers.
++ **************************************************************************/
++
++/*!
++ * Free frame buffers
++ *
++ * @param cam Structure cam_data *
++ *
++ * @return status 0 success.
++ */
++static int mxc_free_frame_buf(cam_data *cam)
++{
++ int i;
++
++ pr_debug("MVC: In mxc_free_frame_buf\n");
++
++ for (i = 0; i < FRAME_NUM; i++) {
++ if (cam->frame[i].vaddress != 0) {
++ dma_free_coherent(0, cam->frame[i].buffer.length,
++ cam->frame[i].vaddress,
++ cam->frame[i].paddress);
++ cam->frame[i].vaddress = 0;
++ }
++ }
++
++ return 0;
++}
++
++/*!
++ * Allocate frame buffers
++ *
++ * @param cam Structure cam_data*
++ * @param count int number of buffer need to allocated
++ *
++ * @return status -0 Successfully allocated a buffer, -ENOBUFS failed.
++ */
++static int mxc_allocate_frame_buf(cam_data *cam, int count)
++{
++ int i;
++
++ pr_debug("In MVC:mxc_allocate_frame_buf - size=%d\n",
++ cam->v2f.fmt.pix.sizeimage);
++
++ for (i = 0; i < count; i++) {
++ cam->frame[i].vaddress =
++ dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->frame[i].paddress,
++ GFP_DMA | GFP_KERNEL);
++ if (cam->frame[i].vaddress == 0) {
++ pr_err("ERROR: v4l2 capture: "
++ "mxc_allocate_frame_buf failed.\n");
++ mxc_free_frame_buf(cam);
++ return -ENOBUFS;
++ }
++ cam->frame[i].buffer.index = i;
++ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++ cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cam->frame[i].buffer.length =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP;
++ cam->frame[i].buffer.m.offset = cam->frame[i].paddress;
++ cam->frame[i].index = i;
++ }
++
++ return 0;
++}
++
++/*!
++ * Free frame buffers status
++ *
++ * @param cam Structure cam_data *
++ *
++ * @return none
++ */
++static void mxc_free_frames(cam_data *cam)
++{
++ int i;
++
++ pr_debug("In MVC:mxc_free_frames\n");
++
++ for (i = 0; i < FRAME_NUM; i++)
++ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++
++ cam->enc_counter = 0;
++ INIT_LIST_HEAD(&cam->ready_q);
++ INIT_LIST_HEAD(&cam->working_q);
++ INIT_LIST_HEAD(&cam->done_q);
++}
++
++/*!
++ * Return the buffer status
++ *
++ * @param cam Structure cam_data *
++ * @param buf Structure v4l2_buffer *
++ *
++ * @return status 0 success, EINVAL failed.
++ */
++static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf)
++{
++ pr_debug("In MVC:mxc_v4l2_buffer_status\n");
++
++ if (buf->index < 0 || buf->index >= FRAME_NUM) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l2_buffer_status buffers "
++ "not allocated\n");
++ return -EINVAL;
++ }
++
++ memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf));
++ return 0;
++}
++
++static int mxc_v4l2_release_bufs(cam_data *cam)
++{
++ pr_debug("In MVC:mxc_v4l2_release_bufs\n");
++ return 0;
++}
++
++static int mxc_v4l2_prepare_bufs(cam_data *cam, struct v4l2_buffer *buf)
++{
++ pr_debug("In MVC:mxc_v4l2_prepare_bufs\n");
++
++ if (buf->index < 0 || buf->index >= FRAME_NUM || buf->length <
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l2_prepare_bufs buffers "
++ "not allocated,index=%d, length=%d\n", buf->index,
++ buf->length);
++ return -EINVAL;
++ }
++
++ cam->frame[buf->index].buffer.index = buf->index;
++ cam->frame[buf->index].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++ cam->frame[buf->index].buffer.length = buf->length;
++ cam->frame[buf->index].buffer.m.offset = cam->frame[buf->index].paddress
++ = buf->m.offset;
++ cam->frame[buf->index].buffer.type = buf->type;
++ cam->frame[buf->index].buffer.memory = V4L2_MEMORY_USERPTR;
++ cam->frame[buf->index].index = buf->index;
++
++ return 0;
++}
++
++/***************************************************************************
++ * Functions for handling the video stream.
++ **************************************************************************/
++
++/*!
++ * Indicates whether the palette is supported.
++ *
++ * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
++ *
++ * @return 0 if failed
++ */
++static inline int valid_mode(u32 palette)
++{
++ return ((palette == V4L2_PIX_FMT_RGB565) ||
++ (palette == V4L2_PIX_FMT_BGR24) ||
++ (palette == V4L2_PIX_FMT_RGB24) ||
++ (palette == V4L2_PIX_FMT_BGR32) ||
++ (palette == V4L2_PIX_FMT_RGB32) ||
++ (palette == V4L2_PIX_FMT_YUV422P) ||
++ (palette == V4L2_PIX_FMT_UYVY) ||
++ (palette == V4L2_PIX_FMT_YUYV) ||
++ (palette == V4L2_PIX_FMT_YUV420) ||
++ (palette == V4L2_PIX_FMT_YVU420) ||
++ (palette == V4L2_PIX_FMT_NV12));
++}
++
++/*!
++ * Start the encoder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int mxc_streamon(cam_data *cam)
++{
++ struct mxc_v4l_frame *frame;
++ unsigned long lock_flags;
++ int err = 0;
++
++ pr_debug("In MVC:mxc_streamon\n");
++
++ if (NULL == cam) {
++ pr_err("ERROR! cam parameter is NULL\n");
++ return -1;
++ }
++
++ if (cam->capture_on) {
++ pr_err("ERROR: v4l2 capture: Capture stream has been turned "
++ " on\n");
++ return -1;
++ }
++
++ if (list_empty(&cam->ready_q)) {
++ pr_err("ERROR: v4l2 capture: mxc_streamon buffer has not been "
++ "queued yet\n");
++ return -EINVAL;
++ }
++ if (cam->enc_update_eba &&
++ cam->ready_q.prev == cam->ready_q.next) {
++ pr_err("ERROR: v4l2 capture: mxc_streamon buffer need "
++ "ping pong at least two buffers\n");
++ return -EINVAL;
++ }
++
++ cam->capture_pid = current->pid;
++
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ if (cam->enc_enable) {
++ err = cam->enc_enable(cam);
++ if (err != 0)
++ return err;
++ }
++
++ spin_lock_irqsave(&cam->queue_int_lock, lock_flags);
++ cam->ping_pong_csi = 0;
++ cam->local_buf_num = 0;
++ if (cam->enc_update_eba) {
++ frame =
++ list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->ready_q.next);
++ list_add_tail(&frame->queue, &cam->working_q);
++ frame->ipu_buf_num = cam->ping_pong_csi;
++ err = cam->enc_update_eba(cam->ipu, frame->buffer.m.offset,
++ &cam->ping_pong_csi);
++
++ frame =
++ list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->ready_q.next);
++ list_add_tail(&frame->queue, &cam->working_q);
++ frame->ipu_buf_num = cam->ping_pong_csi;
++ err |= cam->enc_update_eba(cam->ipu, frame->buffer.m.offset,
++ &cam->ping_pong_csi);
++ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
++ } else {
++ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
++ return -EINVAL;
++ }
++
++ if (cam->overlay_on == true)
++ start_preview(cam);
++
++ if (cam->enc_enable_csi) {
++ err = cam->enc_enable_csi(cam);
++ if (err != 0)
++ return err;
++ }
++
++ cam->capture_on = true;
++
++ return err;
++}
++
++/*!
++ * Shut down the encoder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int mxc_streamoff(cam_data *cam)
++{
++ int err = 0;
++
++ pr_debug("In MVC:mxc_streamoff\n");
++
++ if (cam->capture_on == false)
++ return 0;
++
++ /* For both CSI--MEM and CSI--IC--MEM
++ * 1. wait for idmac eof
++ * 2. disable csi first
++ * 3. disable idmac
++ * 4. disable smfc (CSI--MEM channel)
++ */
++ if (mxc_capture_inputs[cam->current_input].name != NULL) {
++ if (cam->enc_disable_csi) {
++ err = cam->enc_disable_csi(cam);
++ if (err != 0)
++ return err;
++ }
++ if (cam->enc_disable) {
++ err = cam->enc_disable(cam);
++ if (err != 0)
++ return err;
++ }
++ }
++
++ mxc_free_frames(cam);
++ mxc_capture_inputs[cam->current_input].status |= V4L2_IN_ST_NO_POWER;
++ cam->capture_on = false;
++ return err;
++}
++
++/*!
++ * Valid and adjust the overlay window size, position
++ *
++ * @param cam structure cam_data *
++ * @param win struct v4l2_window *
++ *
++ * @return 0
++ */
++static int verify_preview(cam_data *cam, struct v4l2_window *win)
++{
++ int i = 0, width_bound = 0, height_bound = 0;
++ int *width, *height;
++ unsigned int ipu_ch = CHAN_NONE;
++ struct fb_info *bg_fbi = NULL, *fbi = NULL;
++ bool foregound_fb = false;
++ mm_segment_t old_fs;
++
++ pr_debug("In MVC: verify_preview\n");
++
++ do {
++ fbi = (struct fb_info *)registered_fb[i];
++ if (fbi == NULL) {
++ pr_err("ERROR: verify_preview frame buffer NULL.\n");
++ return -1;
++ }
++
++ /* Which DI supports 2 layers? */
++ if (((strncmp(fbi->fix.id, "DISP3 BG", 8) == 0) &&
++ (cam->output < 3)) ||
++ ((strncmp(fbi->fix.id, "DISP4 BG", 8) == 0) &&
++ (cam->output >= 3))) {
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN,
++ (unsigned long)&ipu_ch);
++ set_fs(old_fs);
++ }
++ if (ipu_ch == MEM_BG_SYNC) {
++ bg_fbi = fbi;
++ pr_debug("Found background frame buffer.\n");
++ }
++ }
++
++ /* Found the frame buffer to preview on. */
++ if (strcmp(fbi->fix.id,
++ mxc_capture_outputs[cam->output].name) == 0) {
++ if (((strcmp(fbi->fix.id, "DISP3 FG") == 0) &&
++ (cam->output < 3)) ||
++ ((strcmp(fbi->fix.id, "DISP4 FG") == 0) &&
++ (cam->output >= 3)))
++ foregound_fb = true;
++
++ cam->overlay_fb = fbi;
++ break;
++ }
++ } while (++i < FB_MAX);
++
++ if (foregound_fb) {
++ width_bound = bg_fbi->var.xres;
++ height_bound = bg_fbi->var.yres;
++
++ if (win->w.width + win->w.left > bg_fbi->var.xres ||
++ win->w.height + win->w.top > bg_fbi->var.yres) {
++ pr_err("ERROR: FG window position exceeds.\n");
++ return -1;
++ }
++ } else {
++ /* 4 bytes alignment for BG */
++ width_bound = cam->overlay_fb->var.xres;
++ height_bound = cam->overlay_fb->var.yres;
++
++ if (cam->overlay_fb->var.bits_per_pixel == 24)
++ win->w.left -= win->w.left % 4;
++ else if (cam->overlay_fb->var.bits_per_pixel == 16)
++ win->w.left -= win->w.left % 2;
++
++ if (win->w.width + win->w.left > cam->overlay_fb->var.xres)
++ win->w.width = cam->overlay_fb->var.xres - win->w.left;
++ if (win->w.height + win->w.top > cam->overlay_fb->var.yres)
++ win->w.height = cam->overlay_fb->var.yres - win->w.top;
++ }
++
++ /* stride line limitation */
++ win->w.height -= win->w.height % 8;
++ win->w.width -= win->w.width % 8;
++
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ height = &win->w.width;
++ width = &win->w.height;
++ } else {
++ width = &win->w.width;
++ height = &win->w.height;
++ }
++
++ if (*width == 0 || *height == 0) {
++ pr_err("ERROR: v4l2 capture: width or height"
++ " too small.\n");
++ return -EINVAL;
++ }
++
++ if ((cam->crop_bounds.width / *width > 8) ||
++ ((cam->crop_bounds.width / *width == 8) &&
++ (cam->crop_bounds.width % *width))) {
++ *width = cam->crop_bounds.width / 8;
++ if (*width % 8)
++ *width += 8 - *width % 8;
++ if (*width + win->w.left > width_bound) {
++ pr_err("ERROR: v4l2 capture: width exceeds "
++ "resize limit.\n");
++ return -1;
++ }
++ pr_err("ERROR: v4l2 capture: width exceeds limit. "
++ "Resize to %d.\n",
++ *width);
++ }
++
++ if ((cam->crop_bounds.height / *height > 8) ||
++ ((cam->crop_bounds.height / *height == 8) &&
++ (cam->crop_bounds.height % *height))) {
++ *height = cam->crop_bounds.height / 8;
++ if (*height % 8)
++ *height += 8 - *height % 8;
++ if (*height + win->w.top > height_bound) {
++ pr_err("ERROR: v4l2 capture: height exceeds "
++ "resize limit.\n");
++ return -1;
++ }
++ pr_err("ERROR: v4l2 capture: height exceeds limit "
++ "resize to %d.\n",
++ *height);
++ }
++
++ return 0;
++}
++
++/*!
++ * start the viewfinder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int start_preview(cam_data *cam)
++{
++ int err = 0;
++
++ pr_debug("MVC: start_preview\n");
++
++ if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY)
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ err = prp_vf_sdc_select(cam);
++ #else
++ err = foreground_sdc_select(cam);
++ #endif
++ else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY)
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ err = prp_vf_sdc_select_bg(cam);
++ #else
++ err = bg_overlay_sdc_select(cam);
++ #endif
++ if (err != 0)
++ return err;
++
++ if (cam->vf_start_sdc) {
++ err = cam->vf_start_sdc(cam);
++ if (err != 0)
++ return err;
++ }
++
++ if (cam->vf_enable_csi)
++ err = cam->vf_enable_csi(cam);
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ return err;
++}
++
++/*!
++ * shut down the viewfinder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int stop_preview(cam_data *cam)
++{
++ int err = 0;
++
++ if (cam->vf_disable_csi) {
++ err = cam->vf_disable_csi(cam);
++ if (err != 0)
++ return err;
++ }
++
++ if (cam->vf_stop_sdc) {
++ err = cam->vf_stop_sdc(cam);
++ if (err != 0)
++ return err;
++ }
++
++ if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY)
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ err = prp_vf_sdc_deselect(cam);
++ #else
++ err = foreground_sdc_deselect(cam);
++ #endif
++ else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY)
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ err = prp_vf_sdc_deselect_bg(cam);
++ #else
++ err = bg_overlay_sdc_deselect(cam);
++ #endif
++
++ return err;
++}
++
++/***************************************************************************
++ * VIDIOC Functions.
++ **************************************************************************/
++
++/*!
++ * V4L2 - mxc_v4l2_g_fmt function
++ *
++ * @param cam structure cam_data *
++ *
++ * @param f structure v4l2_format *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f)
++{
++ int retval = 0;
++
++ pr_debug("In MVC: mxc_v4l2_g_fmt type=%d\n", f->type);
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ f->fmt.pix = cam->v2f.fmt.pix;
++ break;
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
++ f->fmt.win = cam->win;
++ break;
++ default:
++ pr_debug(" type is invalid\n");
++ retval = -EINVAL;
++ }
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ return retval;
++}
++
++/*!
++ * V4L2 - mxc_v4l2_s_fmt function
++ *
++ * @param cam structure cam_data *
++ *
++ * @param f structure v4l2_format *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f)
++{
++ int retval = 0;
++ int size = 0;
++ int bytesperline = 0;
++ int *width, *height;
++
++ pr_debug("In MVC: mxc_v4l2_s_fmt\n");
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ if (!valid_mode(f->fmt.pix.pixelformat)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l2_s_fmt: format "
++ "not supported\n");
++ return -EINVAL;
++ }
++
++ /*
++ * Force the capture window resolution to be crop bounds
++ * for CSI MEM input mode.
++ */
++ if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI MEM") == 0) {
++ f->fmt.pix.width = cam->crop_current.width;
++ f->fmt.pix.height = cam->crop_current.height;
++ }
++
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ height = &f->fmt.pix.width;
++ width = &f->fmt.pix.height;
++ } else {
++ width = &f->fmt.pix.width;
++ height = &f->fmt.pix.height;
++ }
++
++ /* stride line limitation */
++ *width -= *width % 8;
++ *height -= *height % 8;
++
++ if (*width == 0 || *height == 0) {
++ pr_err("ERROR: v4l2 capture: width or height"
++ " too small.\n");
++ return -EINVAL;
++ }
++
++ if ((cam->crop_current.width / *width > 8) ||
++ ((cam->crop_current.width / *width == 8) &&
++ (cam->crop_current.width % *width))) {
++ *width = cam->crop_current.width / 8;
++ if (*width % 8)
++ *width += 8 - *width % 8;
++ pr_err("ERROR: v4l2 capture: width exceeds limit "
++ "resize to %d.\n",
++ *width);
++ }
++
++ if ((cam->crop_current.height / *height > 8) ||
++ ((cam->crop_current.height / *height == 8) &&
++ (cam->crop_current.height % *height))) {
++ *height = cam->crop_current.height / 8;
++ if (*height % 8)
++ *height += 8 - *height % 8;
++ pr_err("ERROR: v4l2 capture: height exceeds limit "
++ "resize to %d.\n",
++ *height);
++ }
++
++ switch (f->fmt.pix.pixelformat) {
++ case V4L2_PIX_FMT_RGB565:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ bytesperline = f->fmt.pix.width * 2;
++ break;
++ case V4L2_PIX_FMT_BGR24:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3;
++ bytesperline = f->fmt.pix.width * 3;
++ break;
++ case V4L2_PIX_FMT_RGB24:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3;
++ bytesperline = f->fmt.pix.width * 3;
++ break;
++ case V4L2_PIX_FMT_BGR32:
++ size = f->fmt.pix.width * f->fmt.pix.height * 4;
++ bytesperline = f->fmt.pix.width * 4;
++ break;
++ case V4L2_PIX_FMT_RGB32:
++ size = f->fmt.pix.width * f->fmt.pix.height * 4;
++ bytesperline = f->fmt.pix.width * 4;
++ break;
++ case V4L2_PIX_FMT_YUV422P:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ bytesperline = f->fmt.pix.width;
++ break;
++ case V4L2_PIX_FMT_UYVY:
++ case V4L2_PIX_FMT_YUYV:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ bytesperline = f->fmt.pix.width * 2;
++ break;
++ case V4L2_PIX_FMT_YUV420:
++ case V4L2_PIX_FMT_YVU420:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
++ bytesperline = f->fmt.pix.width;
++ break;
++ case V4L2_PIX_FMT_NV12:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
++ bytesperline = f->fmt.pix.width;
++ break;
++ default:
++ break;
++ }
++
++ if (f->fmt.pix.bytesperline < bytesperline)
++ f->fmt.pix.bytesperline = bytesperline;
++ else
++ bytesperline = f->fmt.pix.bytesperline;
++
++ if (f->fmt.pix.sizeimage < size)
++ f->fmt.pix.sizeimage = size;
++ else
++ size = f->fmt.pix.sizeimage;
++
++ cam->v2f.fmt.pix = f->fmt.pix;
++
++ if (cam->v2f.fmt.pix.priv != 0) {
++ if (copy_from_user(&cam->offset,
++ (void *)cam->v2f.fmt.pix.priv,
++ sizeof(cam->offset))) {
++ retval = -EFAULT;
++ break;
++ }
++ }
++ break;
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
++ retval = verify_preview(cam, &f->fmt.win);
++ cam->win = f->fmt.win;
++ break;
++ default:
++ retval = -EINVAL;
++ }
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ return retval;
++}
++
++/*!
++ * get control param
++ *
++ * @param cam structure cam_data *
++ *
++ * @param c structure v4l2_control *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
++{
++ int status = 0;
++
++ pr_debug("In MVC:mxc_v4l2_g_ctrl\n");
++
++ /* probably don't need to store the values that can be retrieved,
++ * locally, but they are for now. */
++ switch (c->id) {
++ case V4L2_CID_HFLIP:
++ /* This is handled in the ipu. */
++ if (cam->rotation == IPU_ROTATE_HORIZ_FLIP)
++ c->value = 1;
++ break;
++ case V4L2_CID_VFLIP:
++ /* This is handled in the ipu. */
++ if (cam->rotation == IPU_ROTATE_VERT_FLIP)
++ c->value = 1;
++ break;
++ case V4L2_CID_MXC_ROT:
++ /* This is handled in the ipu. */
++ c->value = cam->rotation;
++ break;
++ case V4L2_CID_BRIGHTNESS:
++ if (cam->sensor) {
++ c->value = cam->bright;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->bright = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_HUE:
++ if (cam->sensor) {
++ c->value = cam->hue;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->hue = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_CONTRAST:
++ if (cam->sensor) {
++ c->value = cam->contrast;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->contrast = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_SATURATION:
++ if (cam->sensor) {
++ c->value = cam->saturation;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->saturation = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_RED_BALANCE:
++ if (cam->sensor) {
++ c->value = cam->red;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->red = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ if (cam->sensor) {
++ c->value = cam->blue;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->blue = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_BLACK_LEVEL:
++ if (cam->sensor) {
++ c->value = cam->ae_mode;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->ae_mode = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ default:
++ pr_err("ERROR: v4l2 capture: unsupported ioctrl!\n");
++ }
++
++ return status;
++}
++
++/*!
++ * V4L2 - set_control function
++ * V4L2_CID_PRIVATE_BASE is the extention for IPU preprocessing.
++ * 0 for normal operation
++ * 1 for vertical flip
++ * 2 for horizontal flip
++ * 3 for horizontal and vertical flip
++ * 4 for 90 degree rotation
++ * @param cam structure cam_data *
++ *
++ * @param c structure v4l2_control *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
++{
++ int i, ret = 0;
++ int tmp_rotation = IPU_ROTATE_NONE;
++ struct sensor_data *sensor_data;
++
++ pr_debug("In MVC:mxc_v4l2_s_ctrl\n");
++
++ switch (c->id) {
++ case V4L2_CID_HFLIP:
++ /* This is done by the IPU */
++ if (c->value == 1) {
++ if ((cam->rotation != IPU_ROTATE_VERT_FLIP) &&
++ (cam->rotation != IPU_ROTATE_180))
++ cam->rotation = IPU_ROTATE_HORIZ_FLIP;
++ else
++ cam->rotation = IPU_ROTATE_180;
++ } else {
++ if (cam->rotation == IPU_ROTATE_HORIZ_FLIP)
++ cam->rotation = IPU_ROTATE_NONE;
++ if (cam->rotation == IPU_ROTATE_180)
++ cam->rotation = IPU_ROTATE_VERT_FLIP;
++ }
++ break;
++ case V4L2_CID_VFLIP:
++ /* This is done by the IPU */
++ if (c->value == 1) {
++ if ((cam->rotation != IPU_ROTATE_HORIZ_FLIP) &&
++ (cam->rotation != IPU_ROTATE_180))
++ cam->rotation = IPU_ROTATE_VERT_FLIP;
++ else
++ cam->rotation = IPU_ROTATE_180;
++ } else {
++ if (cam->rotation == IPU_ROTATE_VERT_FLIP)
++ cam->rotation = IPU_ROTATE_NONE;
++ if (cam->rotation == IPU_ROTATE_180)
++ cam->rotation = IPU_ROTATE_HORIZ_FLIP;
++ }
++ break;
++ case V4L2_CID_MXC_ROT:
++ case V4L2_CID_MXC_VF_ROT:
++ /* This is done by the IPU */
++ switch (c->value) {
++ case V4L2_MXC_ROTATE_NONE:
++ tmp_rotation = IPU_ROTATE_NONE;
++ break;
++ case V4L2_MXC_ROTATE_VERT_FLIP:
++ tmp_rotation = IPU_ROTATE_VERT_FLIP;
++ break;
++ case V4L2_MXC_ROTATE_HORIZ_FLIP:
++ tmp_rotation = IPU_ROTATE_HORIZ_FLIP;
++ break;
++ case V4L2_MXC_ROTATE_180:
++ tmp_rotation = IPU_ROTATE_180;
++ break;
++ case V4L2_MXC_ROTATE_90_RIGHT:
++ tmp_rotation = IPU_ROTATE_90_RIGHT;
++ break;
++ case V4L2_MXC_ROTATE_90_RIGHT_VFLIP:
++ tmp_rotation = IPU_ROTATE_90_RIGHT_VFLIP;
++ break;
++ case V4L2_MXC_ROTATE_90_RIGHT_HFLIP:
++ tmp_rotation = IPU_ROTATE_90_RIGHT_HFLIP;
++ break;
++ case V4L2_MXC_ROTATE_90_LEFT:
++ tmp_rotation = IPU_ROTATE_90_LEFT;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ if (c->id == V4L2_CID_MXC_VF_ROT)
++ cam->vf_rotation = tmp_rotation;
++ else
++ cam->rotation = tmp_rotation;
++ #else
++ cam->rotation = tmp_rotation;
++ #endif
++
++ break;
++ case V4L2_CID_HUE:
++ if (cam->sensor) {
++ cam->hue = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_CONTRAST:
++ if (cam->sensor) {
++ cam->contrast = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_BRIGHTNESS:
++ if (cam->sensor) {
++ cam->bright = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_SATURATION:
++ if (cam->sensor) {
++ cam->saturation = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_RED_BALANCE:
++ if (cam->sensor) {
++ cam->red = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ if (cam->sensor) {
++ cam->blue = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_EXPOSURE:
++ if (cam->sensor) {
++ cam->ae_mode = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_MXC_FLASH:
++#ifdef CONFIG_MXC_IPU_V1
++ ipu_csi_flash_strobe(true);
++#endif
++ break;
++ case V4L2_CID_MXC_SWITCH_CAM:
++ if (cam->sensor == cam->all_sensors[c->value])
++ break;
++
++ /* power down other cameraes before enable new one */
++ for (i = 0; i < cam->sensor_index; i++) {
++ if (i != c->value) {
++ vidioc_int_dev_exit(cam->all_sensors[i]);
++ vidioc_int_s_power(cam->all_sensors[i], 0);
++ if (cam->mclk_on[cam->mclk_source]) {
++ ipu_csi_enable_mclk_if(cam->ipu,
++ CSI_MCLK_I2C,
++ cam->mclk_source,
++ false, false);
++ cam->mclk_on[cam->mclk_source] =
++ false;
++ }
++ }
++ }
++ sensor_data = cam->all_sensors[c->value]->priv;
++ if (sensor_data->io_init)
++ sensor_data->io_init();
++ cam->sensor = cam->all_sensors[c->value];
++ cam->mclk_source = sensor_data->mclk_source;
++ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C,
++ cam->mclk_source, true, true);
++ cam->mclk_on[cam->mclk_source] = true;
++ vidioc_int_s_power(cam->sensor, 1);
++ vidioc_int_dev_init(cam->sensor);
++ break;
++ default:
++ pr_debug(" default case\n");
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * V4L2 - mxc_v4l2_s_param function
++ * Allows setting of capturemode and frame rate.
++ *
++ * @param cam structure cam_data *
++ * @param parm structure v4l2_streamparm *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
++{
++ struct v4l2_ifparm ifparm;
++ struct v4l2_format cam_fmt;
++ struct v4l2_streamparm currentparm;
++ ipu_csi_signal_cfg_t csi_param;
++ u32 current_fps, parm_fps;
++ int err = 0;
++
++ pr_debug("In mxc_v4l2_s_param\n");
++
++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n");
++ return -EINVAL;
++ }
++
++ /* Stop the viewfinder */
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++
++ /* First check that this device can support the changes requested. */
++ err = vidioc_int_g_parm(cam->sensor, &currentparm);
++ if (err) {
++ pr_err("%s: vidioc_int_g_parm returned an error %d\n",
++ __func__, err);
++ goto exit;
++ }
++
++ current_fps = currentparm.parm.capture.timeperframe.denominator
++ / currentparm.parm.capture.timeperframe.numerator;
++ parm_fps = parm->parm.capture.timeperframe.denominator
++ / parm->parm.capture.timeperframe.numerator;
++
++ pr_debug(" Current capabilities are %x\n",
++ currentparm.parm.capture.capability);
++ pr_debug(" Current capturemode is %d change to %d\n",
++ currentparm.parm.capture.capturemode,
++ parm->parm.capture.capturemode);
++ pr_debug(" Current framerate is %d change to %d\n",
++ current_fps, parm_fps);
++
++ /* This will change any camera settings needed. */
++ err = vidioc_int_s_parm(cam->sensor, parm);
++ if (err) {
++ pr_err("%s: vidioc_int_s_parm returned an error %d\n",
++ __func__, err);
++ goto exit;
++ }
++
++ /* If resolution changed, need to re-program the CSI */
++ /* Get new values. */
++ vidioc_int_g_ifparm(cam->sensor, &ifparm);
++
++ csi_param.data_width = 0;
++ csi_param.clk_mode = 0;
++ csi_param.ext_vsync = 0;
++ csi_param.Vsync_pol = 0;
++ csi_param.Hsync_pol = 0;
++ csi_param.pixclk_pol = 0;
++ csi_param.data_pol = 0;
++ csi_param.sens_clksrc = 0;
++ csi_param.pack_tight = 0;
++ csi_param.force_eof = 0;
++ csi_param.data_en_pol = 0;
++ csi_param.data_fmt = 0;
++ csi_param.csi = cam->csi;
++ csi_param.mclk = 0;
++
++ /*This may not work on other platforms. Check when adding a new one.*/
++ /*The mclk clock was never set correclty in the ipu register*/
++ /*for now we are going to use this mclk as pixel clock*/
++ /*to set csi0_data_dest register.*/
++ /*This is a workaround which should be fixed*/
++ pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);
++ if (ifparm.u.bt656.clock_curr == 0) {
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
++ /*protocol bt656 use 27Mhz pixel clock */
++ csi_param.mclk = 27000000;
++ } else {
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
++ }
++
++ csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;
++
++ if (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT) {
++ csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
++ } else if (ifparm.u.bt656.mode
++ == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) {
++ csi_param.data_width = IPU_CSI_DATA_WIDTH_10;
++ } else {
++ csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
++ }
++
++ csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv;
++ csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv;
++ csi_param.ext_vsync = ifparm.u.bt656.bt_sync_correct;
++
++ /* if the capturemode changed, the size bounds will have changed. */
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++ pr_debug(" g_fmt_cap returns widthxheight of input as %d x %d\n",
++ cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
++
++ csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat;
++
++ cam->crop_bounds.top = cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = cam_fmt.fmt.pix.width;
++ cam->crop_bounds.height = cam_fmt.fmt.pix.height;
++
++ /*
++ * Set the default current cropped resolution to be the same with
++ * the cropping boundary(except for tvin module).
++ */
++ if (cam->device_type != 1) {
++ cam->crop_current.width = cam->crop_bounds.width;
++ cam->crop_current.height = cam->crop_bounds.height;
++ }
++
++ /* This essentially loses the data at the left and bottom of the image
++ * giving a digital zoom image, if crop_current is less than the full
++ * size of the image. */
++ ipu_csi_set_window_size(cam->ipu, cam->crop_current.width,
++ cam->crop_current.height, cam->csi);
++ ipu_csi_set_window_pos(cam->ipu, cam->crop_current.left,
++ cam->crop_current.top,
++ cam->csi);
++ ipu_csi_init_interface(cam->ipu, cam->crop_bounds.width,
++ cam->crop_bounds.height,
++ cam_fmt.fmt.pix.pixelformat, csi_param);
++
++
++exit:
++ if (cam->overlay_on == true)
++ start_preview(cam);
++
++ return err;
++}
++
++/*!
++ * V4L2 - mxc_v4l2_s_std function
++ *
++ * Sets the TV standard to be used.
++ *
++ * @param cam structure cam_data *
++ * @param parm structure v4l2_streamparm *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_s_std(cam_data *cam, v4l2_std_id e)
++{
++ printk(KERN_ERR "In mxc_v4l2_s_std %Lx\n", e);
++ if (e == V4L2_STD_PAL) {
++ pr_debug(" Setting standard to PAL %Lx\n", V4L2_STD_PAL);
++ cam->standard.id = V4L2_STD_PAL;
++ video_index = TV_PAL;
++ } else if (e == V4L2_STD_NTSC) {
++ pr_debug(" Setting standard to NTSC %Lx\n",
++ V4L2_STD_NTSC);
++ /* Get rid of the white dot line in NTSC signal input */
++ cam->standard.id = V4L2_STD_NTSC;
++ video_index = TV_NTSC;
++ } else {
++ cam->standard.id = V4L2_STD_ALL;
++ video_index = TV_NOT_LOCKED;
++ pr_err("ERROR: unrecognized std! %Lx (PAL=%Lx, NTSC=%Lx\n",
++ e, V4L2_STD_PAL, V4L2_STD_NTSC);
++ }
++
++ cam->standard.index = video_index;
++ strcpy(cam->standard.name, video_fmts[video_index].name);
++ cam->crop_bounds.width = video_fmts[video_index].raw_width;
++ cam->crop_bounds.height = video_fmts[video_index].raw_height;
++ cam->crop_current.width = video_fmts[video_index].active_width;
++ cam->crop_current.height = video_fmts[video_index].active_height;
++ cam->crop_current.top = video_fmts[video_index].active_top;
++ cam->crop_current.left = video_fmts[video_index].active_left;
++
++ return 0;
++}
++
++/*!
++ * V4L2 - mxc_v4l2_g_std function
++ *
++ * Gets the TV standard from the TV input device.
++ *
++ * @param cam structure cam_data *
++ *
++ * @param e structure v4l2_streamparm *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_g_std(cam_data *cam, v4l2_std_id *e)
++{
++ struct v4l2_format tv_fmt;
++
++ pr_debug("In mxc_v4l2_g_std\n");
++
++ if (cam->device_type == 1) {
++ /* Use this function to get what the TV-In device detects the
++ * format to be. pixelformat is used to return the std value
++ * since the interface has no vidioc_g_std.*/
++ tv_fmt.type = V4L2_BUF_TYPE_PRIVATE;
++ vidioc_int_g_fmt_cap(cam->sensor, &tv_fmt);
++
++ /* If the TV-in automatically detects the standard, then if it
++ * changes, the settings need to change. */
++ if (cam->standard_autodetect) {
++ if (cam->standard.id != tv_fmt.fmt.pix.pixelformat) {
++ pr_debug("MVC: mxc_v4l2_g_std: "
++ "Changing standard\n");
++ mxc_v4l2_s_std(cam, tv_fmt.fmt.pix.pixelformat);
++ }
++ }
++
++ *e = tv_fmt.fmt.pix.pixelformat;
++ }
++
++ return 0;
++}
++
++/*!
++ * Dequeue one V4L capture buffer
++ *
++ * @param cam structure cam_data *
++ * @param buf structure v4l2_buffer *
++ *
++ * @return status 0 success, EINVAL invalid frame number,
++ * ETIME timeout, ERESTARTSYS interrupted by user
++ */
++static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf)
++{
++ int retval = 0;
++ struct mxc_v4l_frame *frame;
++ unsigned long lock_flags;
++
++ pr_debug("In MVC:mxc_v4l_dqueue\n");
++
++ if (!wait_event_interruptible_timeout(cam->enc_queue,
++ cam->enc_counter != 0, 10 * HZ)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout "
++ "enc_counter %x\n",
++ cam->enc_counter);
++ return -ETIME;
++ } else if (signal_pending(current)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() "
++ "interrupt received\n");
++ return -ERESTARTSYS;
++ }
++
++ if (down_interruptible(&cam->busy_lock))
++ return -EBUSY;
++
++ spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags);
++ cam->enc_counter--;
++
++ frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->done_q.next);
++ if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) {
++ frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE;
++ } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
++ "Buffer not filled.\n");
++ frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
++ retval = -EINVAL;
++ } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
++ "Buffer not queued.\n");
++ retval = -EINVAL;
++ }
++
++ cam->frame[frame->index].buffer.field = cam->device_type ?
++ V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
++
++ buf->bytesused = cam->v2f.fmt.pix.sizeimage;
++ buf->index = frame->index;
++ buf->flags = frame->buffer.flags;
++ buf->m = cam->frame[frame->index].buffer.m;
++ buf->timestamp = cam->frame[frame->index].buffer.timestamp;
++ buf->field = cam->frame[frame->index].buffer.field;
++ spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags);
++
++ up(&cam->busy_lock);
++ return retval;
++}
++
++/*!
++ * V4L interface - open function
++ *
++ * @param file structure file *
++ *
++ * @return status 0 success, ENODEV invalid device instance,
++ * ENODEV timeout, ERESTARTSYS interrupted by user
++ */
++static int mxc_v4l_open(struct file *file)
++{
++ struct v4l2_ifparm ifparm;
++ struct v4l2_format cam_fmt;
++ ipu_csi_signal_cfg_t csi_param;
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++ int err = 0;
++ struct sensor_data *sensor;
++
++ pr_debug("\nIn MVC: mxc_v4l_open\n");
++ pr_debug(" device name is %s\n", dev->name);
++
++ if (!cam) {
++ pr_err("ERROR: v4l2 capture: Internal error, "
++ "cam_data not found!\n");
++ return -EBADF;
++ }
++
++ if (cam->sensor == NULL ||
++ cam->sensor->type != v4l2_int_type_slave) {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ return -EAGAIN;
++ }
++
++ sensor = cam->sensor->priv;
++ if (!sensor) {
++ pr_err("%s: Internal error, sensor_data is not found!\n", __func__);
++ return -EBADF;
++ }
++
++ down(&cam->busy_lock);
++ err = 0;
++ if (signal_pending(current))
++ goto oops;
++
++ if (cam->open_count++ == 0) {
++ wait_event_interruptible(cam->power_queue,
++ cam->low_power == false);
++
++ if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
++ err = csi_enc_select(cam);
++#endif
++ } else if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI IC MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
++ err = prp_enc_select(cam);
++#endif
++ }
++
++ cam->enc_counter = 0;
++ INIT_LIST_HEAD(&cam->ready_q);
++ INIT_LIST_HEAD(&cam->working_q);
++ INIT_LIST_HEAD(&cam->done_q);
++
++ vidioc_int_g_ifparm(cam->sensor, &ifparm);
++
++ csi_param.sens_clksrc = 0;
++
++ csi_param.clk_mode = 0;
++ csi_param.data_pol = 0;
++ csi_param.ext_vsync = 0;
++
++ csi_param.pack_tight = 0;
++ csi_param.force_eof = 0;
++ csi_param.data_en_pol = 0;
++
++ csi_param.mclk = ifparm.u.bt656.clock_curr;
++
++ csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;
++
++ if (ifparm.u.bt656.mode
++ == V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT)
++ csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
++ else if (ifparm.u.bt656.mode
++ == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT)
++ csi_param.data_width = IPU_CSI_DATA_WIDTH_10;
++ else
++ csi_param.data_width = IPU_CSI_DATA_WIDTH_8;
++
++
++ csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv;
++ csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv;
++
++ csi_param.csi = cam->csi;
++
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++
++ /* Reset the sizes. Needed to prevent carryover of last
++ * operation.*/
++ cam->crop_bounds.top = cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = cam_fmt.fmt.pix.width;
++ cam->crop_bounds.height = cam_fmt.fmt.pix.height;
++
++ /* This also is the max crop size for this device. */
++ cam->crop_defrect.top = cam->crop_defrect.left = 0;
++ cam->crop_defrect.width = cam_fmt.fmt.pix.width;
++ cam->crop_defrect.height = cam_fmt.fmt.pix.height;
++
++ /* At this point, this is also the current image size. */
++ cam->crop_current.top = cam->crop_current.left = 0;
++ cam->crop_current.width = cam_fmt.fmt.pix.width;
++ cam->crop_current.height = cam_fmt.fmt.pix.height;
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ csi_param.data_fmt = cam_fmt.fmt.pix.pixelformat;
++ pr_debug("On Open: Input to ipu size is %d x %d\n",
++ cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
++ ipu_csi_set_window_size(cam->ipu, cam->crop_current.width,
++ cam->crop_current.height,
++ cam->csi);
++ ipu_csi_set_window_pos(cam->ipu, cam->crop_current.left,
++ cam->crop_current.top,
++ cam->csi);
++ ipu_csi_init_interface(cam->ipu, cam->crop_bounds.width,
++ cam->crop_bounds.height,
++ cam_fmt.fmt.pix.pixelformat,
++ csi_param);
++ clk_prepare_enable(sensor->sensor_clk);
++ vidioc_int_s_power(cam->sensor, 1);
++ vidioc_int_init(cam->sensor);
++ vidioc_int_dev_init(cam->sensor);
++ }
++
++ file->private_data = dev;
++
++oops:
++ up(&cam->busy_lock);
++ return err;
++}
++
++/*!
++ * V4L interface - close function
++ *
++ * @param file struct file *
++ *
++ * @return 0 success
++ */
++static int mxc_v4l_close(struct file *file)
++{
++ struct video_device *dev = video_devdata(file);
++ int err = 0;
++ cam_data *cam = video_get_drvdata(dev);
++ struct sensor_data *sensor;
++ pr_debug("In MVC:mxc_v4l_close\n");
++
++ if (!cam) {
++ pr_err("ERROR: v4l2 capture: Internal error, "
++ "cam_data not found!\n");
++ return -EBADF;
++ }
++
++ if (!cam->sensor) {
++ pr_err("%s: Internal error, camera is not found!\n", __func__);
++ return -EBADF;
++ }
++
++ sensor = cam->sensor->priv;
++ if (!sensor) {
++ pr_err("%s: Internal error, sensor_data is not found!\n", __func__);
++ return -EBADF;
++ }
++
++ down(&cam->busy_lock);
++
++ /* for the case somebody hit the ctrl C */
++ if (cam->overlay_pid == current->pid && cam->overlay_on) {
++ err = stop_preview(cam);
++ cam->overlay_on = false;
++ }
++ if (cam->capture_pid == current->pid) {
++ err |= mxc_streamoff(cam);
++ wake_up_interruptible(&cam->enc_queue);
++ }
++
++ if (--cam->open_count == 0) {
++ vidioc_int_s_power(cam->sensor, 0);
++ clk_disable_unprepare(sensor->sensor_clk);
++ wait_event_interruptible(cam->power_queue,
++ cam->low_power == false);
++ pr_debug("mxc_v4l_close: release resource\n");
++
++ if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
++ err |= csi_enc_deselect(cam);
++#endif
++ } else if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI IC MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
++ err |= prp_enc_deselect(cam);
++#endif
++ }
++
++ mxc_free_frame_buf(cam);
++ file->private_data = NULL;
++
++ /* capture off */
++ wake_up_interruptible(&cam->enc_queue);
++ mxc_free_frames(cam);
++ cam->enc_counter++;
++ }
++
++ up(&cam->busy_lock);
++
++ return err;
++}
++
++#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC) || \
++ defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) || \
++ defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
++/*
++ * V4L interface - read function
++ *
++ * @param file struct file *
++ * @param read buf char *
++ * @param count size_t
++ * @param ppos structure loff_t *
++ *
++ * @return bytes read
++ */
++static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count,
++ loff_t *ppos)
++{
++ int err = 0;
++ u8 *v_address[2];
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++
++ if (down_interruptible(&cam->busy_lock))
++ return -EINTR;
++
++ /* Stop the viewfinder */
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ v_address[0] = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->still_buf[0],
++ GFP_DMA | GFP_KERNEL);
++
++ v_address[1] = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->still_buf[1],
++ GFP_DMA | GFP_KERNEL);
++
++ if (!v_address[0] || !v_address[1]) {
++ err = -ENOBUFS;
++ goto exit0;
++ }
++
++ err = prp_still_select(cam);
++ if (err != 0) {
++ err = -EIO;
++ goto exit0;
++ }
++
++ cam->still_counter = 0;
++ err = cam->csi_start(cam);
++ if (err != 0) {
++ err = -EIO;
++ goto exit1;
++ }
++
++ if (!wait_event_interruptible_timeout(cam->still_queue,
++ cam->still_counter != 0,
++ 10 * HZ)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l_read timeout counter %x\n",
++ cam->still_counter);
++ err = -ETIME;
++ goto exit1;
++ }
++ err = copy_to_user(buf, v_address[1], cam->v2f.fmt.pix.sizeimage);
++
++exit1:
++ prp_still_deselect(cam);
++
++exit0:
++ if (v_address[0] != 0)
++ dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[0],
++ cam->still_buf[0]);
++ if (v_address[1] != 0)
++ dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[1],
++ cam->still_buf[1]);
++
++ cam->still_buf[0] = cam->still_buf[1] = 0;
++
++ if (cam->overlay_on == true)
++ start_preview(cam);
++
++ up(&cam->busy_lock);
++ if (err < 0)
++ return err;
++
++ return cam->v2f.fmt.pix.sizeimage - err;
++}
++#endif
++
++/*!
++ * V4L interface - ioctl function
++ *
++ * @param file struct file*
++ *
++ * @param ioctlnr unsigned int
++ *
++ * @param arg void*
++ *
++ * @return 0 success, ENODEV for invalid device instance,
++ * -1 for other errors.
++ */
++static long mxc_v4l_do_ioctl(struct file *file,
++ unsigned int ioctlnr, void *arg)
++{
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++ int retval = 0;
++ unsigned long lock_flags;
++
++ pr_debug("In MVC: mxc_v4l_do_ioctl %x\n", ioctlnr);
++ wait_event_interruptible(cam->power_queue, cam->low_power == false);
++ /* make this _really_ smp-safe */
++ if (ioctlnr != VIDIOC_DQBUF)
++ if (down_interruptible(&cam->busy_lock))
++ return -EBUSY;
++
++ switch (ioctlnr) {
++ /*!
++ * V4l2 VIDIOC_QUERYCAP ioctl
++ */
++ case VIDIOC_QUERYCAP: {
++ struct v4l2_capability *cap = arg;
++ pr_debug(" case VIDIOC_QUERYCAP\n");
++ strcpy(cap->driver, "mxc_v4l2");
++ cap->version = KERNEL_VERSION(0, 1, 11);
++ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
++ V4L2_CAP_VIDEO_OVERLAY |
++ V4L2_CAP_STREAMING |
++ V4L2_CAP_READWRITE;
++ cap->card[0] = '\0';
++ cap->bus_info[0] = '\0';
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_FMT ioctl
++ */
++ case VIDIOC_G_FMT: {
++ struct v4l2_format *gf = arg;
++ pr_debug(" case VIDIOC_G_FMT\n");
++ retval = mxc_v4l2_g_fmt(cam, gf);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_FMT ioctl
++ */
++ case VIDIOC_S_FMT: {
++ struct v4l2_format *sf = arg;
++ pr_debug(" case VIDIOC_S_FMT\n");
++ retval = mxc_v4l2_s_fmt(cam, sf);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_REQBUFS ioctl
++ */
++ case VIDIOC_REQBUFS: {
++ struct v4l2_requestbuffers *req = arg;
++ pr_debug(" case VIDIOC_REQBUFS\n");
++
++ if (req->count > FRAME_NUM) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
++ "not enough buffers\n");
++ req->count = FRAME_NUM;
++ }
++
++ if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
++ "wrong buffer type\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ mxc_streamoff(cam);
++ if (req->memory & V4L2_MEMORY_MMAP) {
++ mxc_free_frame_buf(cam);
++ retval = mxc_allocate_frame_buf(cam, req->count);
++ }
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_QUERYBUF ioctl
++ */
++ case VIDIOC_QUERYBUF: {
++ struct v4l2_buffer *buf = arg;
++ int index = buf->index;
++ pr_debug(" case VIDIOC_QUERYBUF\n");
++
++ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ pr_err("ERROR: v4l2 capture: "
++ "VIDIOC_QUERYBUFS: "
++ "wrong buffer type\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ if (buf->memory & V4L2_MEMORY_MMAP) {
++ memset(buf, 0, sizeof(buf));
++ buf->index = index;
++ }
++
++ down(&cam->param_lock);
++ if (buf->memory & V4L2_MEMORY_USERPTR) {
++ mxc_v4l2_release_bufs(cam);
++ retval = mxc_v4l2_prepare_bufs(cam, buf);
++ }
++
++ if (buf->memory & V4L2_MEMORY_MMAP)
++ retval = mxc_v4l2_buffer_status(cam, buf);
++ up(&cam->param_lock);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_QBUF ioctl
++ */
++ case VIDIOC_QBUF: {
++ struct v4l2_buffer *buf = arg;
++ int index = buf->index;
++ pr_debug(" case VIDIOC_QBUF\n");
++
++ spin_lock_irqsave(&cam->queue_int_lock, lock_flags);
++ if ((cam->frame[index].buffer.flags & 0x7) ==
++ V4L2_BUF_FLAG_MAPPED) {
++ cam->frame[index].buffer.flags |=
++ V4L2_BUF_FLAG_QUEUED;
++ list_add_tail(&cam->frame[index].queue,
++ &cam->ready_q);
++ } else if (cam->frame[index].buffer.
++ flags & V4L2_BUF_FLAG_QUEUED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
++ "buffer already queued\n");
++ retval = -EINVAL;
++ } else if (cam->frame[index].buffer.
++ flags & V4L2_BUF_FLAG_DONE) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
++ "overwrite done buffer.\n");
++ cam->frame[index].buffer.flags &=
++ ~V4L2_BUF_FLAG_DONE;
++ cam->frame[index].buffer.flags |=
++ V4L2_BUF_FLAG_QUEUED;
++ retval = -EINVAL;
++ }
++
++ buf->flags = cam->frame[index].buffer.flags;
++ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_DQBUF ioctl
++ */
++ case VIDIOC_DQBUF: {
++ struct v4l2_buffer *buf = arg;
++ pr_debug(" case VIDIOC_DQBUF\n");
++
++ if ((cam->enc_counter == 0) &&
++ (file->f_flags & O_NONBLOCK)) {
++ retval = -EAGAIN;
++ break;
++ }
++
++ retval = mxc_v4l_dqueue(cam, buf);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_STREAMON ioctl
++ */
++ case VIDIOC_STREAMON: {
++ pr_debug(" case VIDIOC_STREAMON\n");
++ retval = mxc_streamon(cam);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_STREAMOFF ioctl
++ */
++ case VIDIOC_STREAMOFF: {
++ pr_debug(" case VIDIOC_STREAMOFF\n");
++ retval = mxc_streamoff(cam);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_CTRL ioctl
++ */
++ case VIDIOC_G_CTRL: {
++ pr_debug(" case VIDIOC_G_CTRL\n");
++ retval = mxc_v4l2_g_ctrl(cam, arg);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_CTRL ioctl
++ */
++ case VIDIOC_S_CTRL: {
++ pr_debug(" case VIDIOC_S_CTRL\n");
++ retval = mxc_v4l2_s_ctrl(cam, arg);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_CROPCAP ioctl
++ */
++ case VIDIOC_CROPCAP: {
++ struct v4l2_cropcap *cap = arg;
++ pr_debug(" case VIDIOC_CROPCAP\n");
++ if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
++ retval = -EINVAL;
++ break;
++ }
++ cap->bounds = cam->crop_bounds;
++ cap->defrect = cam->crop_defrect;
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_CROP ioctl
++ */
++ case VIDIOC_G_CROP: {
++ struct v4l2_crop *crop = arg;
++ pr_debug(" case VIDIOC_G_CROP\n");
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
++ retval = -EINVAL;
++ break;
++ }
++ crop->c = cam->crop_current;
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_CROP ioctl
++ */
++ case VIDIOC_S_CROP: {
++ struct v4l2_crop *crop = arg;
++ struct v4l2_rect *b = &cam->crop_bounds;
++ pr_debug(" case VIDIOC_S_CROP\n");
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
++ retval = -EINVAL;
++ break;
++ }
++
++ crop->c.top = (crop->c.top < b->top) ? b->top
++ : crop->c.top;
++ if (crop->c.top > b->top + b->height)
++ crop->c.top = b->top + b->height - 1;
++ if (crop->c.height > b->top + b->height - crop->c.top)
++ crop->c.height =
++ b->top + b->height - crop->c.top;
++
++ crop->c.left = (crop->c.left < b->left) ? b->left
++ : crop->c.left;
++ if (crop->c.left > b->left + b->width)
++ crop->c.left = b->left + b->width - 1;
++ if (crop->c.width > b->left - crop->c.left + b->width)
++ crop->c.width =
++ b->left - crop->c.left + b->width;
++
++ crop->c.width -= crop->c.width % 8;
++ crop->c.left -= crop->c.left % 4;
++ cam->crop_current = crop->c;
++
++ pr_debug(" Cropping Input to ipu size %d x %d\n",
++ cam->crop_current.width,
++ cam->crop_current.height);
++ ipu_csi_set_window_size(cam->ipu, cam->crop_current.width,
++ cam->crop_current.height,
++ cam->csi);
++ ipu_csi_set_window_pos(cam->ipu, cam->crop_current.left,
++ cam->crop_current.top,
++ cam->csi);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_OVERLAY ioctl
++ */
++ case VIDIOC_OVERLAY: {
++ int *on = arg;
++ pr_debug(" VIDIOC_OVERLAY on=%d\n", *on);
++ if (*on) {
++ cam->overlay_on = true;
++ cam->overlay_pid = current->pid;
++ retval = start_preview(cam);
++ }
++ if (!*on) {
++ retval = stop_preview(cam);
++ cam->overlay_on = false;
++ }
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_FBUF ioctl
++ */
++ case VIDIOC_G_FBUF: {
++ struct v4l2_framebuffer *fb = arg;
++ pr_debug(" case VIDIOC_G_FBUF\n");
++ *fb = cam->v4l2_fb;
++ fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_FBUF ioctl
++ */
++ case VIDIOC_S_FBUF: {
++ struct v4l2_framebuffer *fb = arg;
++ pr_debug(" case VIDIOC_S_FBUF\n");
++ cam->v4l2_fb = *fb;
++ break;
++ }
++
++ case VIDIOC_G_PARM: {
++ struct v4l2_streamparm *parm = arg;
++ pr_debug(" case VIDIOC_G_PARM\n");
++ if (cam->sensor)
++ retval = vidioc_int_g_parm(cam->sensor, parm);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++
++ case VIDIOC_S_PARM: {
++ struct v4l2_streamparm *parm = arg;
++ pr_debug(" case VIDIOC_S_PARM\n");
++ if (cam->sensor)
++ retval = mxc_v4l2_s_param(cam, parm);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++
++ /* linux v4l2 bug, kernel c0485619 user c0405619 */
++ case VIDIOC_ENUMSTD: {
++ struct v4l2_standard *e = arg;
++ pr_debug(" case VIDIOC_ENUMSTD\n");
++ *e = cam->standard;
++ break;
++ }
++
++ case VIDIOC_G_STD: {
++ v4l2_std_id *e = arg;
++ pr_debug(" case VIDIOC_G_STD\n");
++ if (cam->sensor)
++ retval = mxc_v4l2_g_std(cam, e);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++
++ case VIDIOC_S_STD: {
++ v4l2_std_id *e = arg;
++ pr_debug(" case VIDIOC_S_STD\n");
++ retval = mxc_v4l2_s_std(cam, *e);
++
++ break;
++ }
++
++ case VIDIOC_ENUMOUTPUT: {
++ struct v4l2_output *output = arg;
++ pr_debug(" case VIDIOC_ENUMOUTPUT\n");
++ if (output->index >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) {
++ retval = -EINVAL;
++ break;
++ }
++ *output = mxc_capture_outputs[output->index];
++
++ break;
++ }
++ case VIDIOC_G_OUTPUT: {
++ int *p_output_num = arg;
++ pr_debug(" case VIDIOC_G_OUTPUT\n");
++ *p_output_num = cam->output;
++ break;
++ }
++
++ case VIDIOC_S_OUTPUT: {
++ int *p_output_num = arg;
++ pr_debug(" case VIDIOC_S_OUTPUT\n");
++ if (*p_output_num >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) {
++ retval = -EINVAL;
++ break;
++ }
++ cam->output = *p_output_num;
++ break;
++ }
++
++ case VIDIOC_ENUMINPUT: {
++ struct v4l2_input *input = arg;
++ pr_debug(" case VIDIOC_ENUMINPUT\n");
++ if (input->index >= MXC_V4L2_CAPTURE_NUM_INPUTS) {
++ retval = -EINVAL;
++ break;
++ }
++ *input = mxc_capture_inputs[input->index];
++ break;
++ }
++
++ case VIDIOC_G_INPUT: {
++ int *index = arg;
++ pr_debug(" case VIDIOC_G_INPUT\n");
++ *index = cam->current_input;
++ break;
++ }
++
++ case VIDIOC_S_INPUT: {
++ int *index = arg;
++ pr_debug(" case VIDIOC_S_INPUT\n");
++ if (*index >= MXC_V4L2_CAPTURE_NUM_INPUTS) {
++ retval = -EINVAL;
++ break;
++ }
++
++ if (*index == cam->current_input)
++ break;
++
++ if ((mxc_capture_inputs[cam->current_input].status &
++ V4L2_IN_ST_NO_POWER) == 0) {
++ retval = mxc_streamoff(cam);
++ if (retval)
++ break;
++ mxc_capture_inputs[cam->current_input].status |=
++ V4L2_IN_ST_NO_POWER;
++ }
++
++ if (strcmp(mxc_capture_inputs[*index].name, "CSI MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
++ retval = csi_enc_select(cam);
++ if (retval)
++ break;
++#endif
++ } else if (strcmp(mxc_capture_inputs[*index].name,
++ "CSI IC MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
++ retval = prp_enc_select(cam);
++ if (retval)
++ break;
++#endif
++ }
++
++ mxc_capture_inputs[*index].status &= ~V4L2_IN_ST_NO_POWER;
++ cam->current_input = *index;
++ break;
++ }
++ case VIDIOC_ENUM_FMT: {
++ struct v4l2_fmtdesc *f = arg;
++ if (cam->sensor)
++ retval = vidioc_int_enum_fmt_cap(cam->sensor, f);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_ENUM_FRAMESIZES: {
++ struct v4l2_frmsizeenum *fsize = arg;
++ if (cam->sensor)
++ retval = vidioc_int_enum_framesizes(cam->sensor, fsize);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_DBG_G_CHIP_IDENT: {
++ struct v4l2_dbg_chip_ident *p = arg;
++ p->ident = V4L2_IDENT_NONE;
++ p->revision = 0;
++ if (cam->sensor)
++ retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_TRY_FMT:
++ case VIDIOC_QUERYCTRL:
++ case VIDIOC_G_TUNER:
++ case VIDIOC_S_TUNER:
++ case VIDIOC_G_FREQUENCY:
++ case VIDIOC_S_FREQUENCY:
++ default:
++ pr_debug(" case default or not supported\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ if (ioctlnr != VIDIOC_DQBUF)
++ up(&cam->busy_lock);
++ return retval;
++}
++
++/*
++ * V4L interface - ioctl function
++ *
++ * @return None
++ */
++static long mxc_v4l_ioctl(struct file *file, unsigned int cmd,
++ unsigned long arg)
++{
++ pr_debug("In MVC:mxc_v4l_ioctl\n");
++ return video_usercopy(file, cmd, arg, mxc_v4l_do_ioctl);
++}
++
++/*!
++ * V4L interface - mmap function
++ *
++ * @param file structure file *
++ *
++ * @param vma structure vm_area_struct *
++ *
++ * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error
++ */
++static int mxc_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ struct video_device *dev = video_devdata(file);
++ unsigned long size;
++ int res = 0;
++ cam_data *cam = video_get_drvdata(dev);
++
++ pr_debug("In MVC:mxc_mmap\n");
++ pr_debug(" pgoff=0x%lx, start=0x%lx, end=0x%lx\n",
++ vma->vm_pgoff, vma->vm_start, vma->vm_end);
++
++ /* make this _really_ smp-safe */
++ if (down_interruptible(&cam->busy_lock))
++ return -EINTR;
++
++ size = vma->vm_end - vma->vm_start;
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start,
++ vma->vm_pgoff, size, vma->vm_page_prot)) {
++ pr_err("ERROR: v4l2 capture: mxc_mmap: "
++ "remap_pfn_range failed\n");
++ res = -ENOBUFS;
++ goto mxc_mmap_exit;
++ }
++
++ vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */
++
++mxc_mmap_exit:
++ up(&cam->busy_lock);
++ return res;
++}
++
++/*!
++ * V4L interface - poll function
++ *
++ * @param file structure file *
++ *
++ * @param wait structure poll_table_struct *
++ *
++ * @return status POLLIN | POLLRDNORM
++ */
++static unsigned int mxc_poll(struct file *file, struct poll_table_struct *wait)
++{
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++ wait_queue_head_t *queue = NULL;
++ int res = POLLIN | POLLRDNORM;
++
++ pr_debug("In MVC:mxc_poll\n");
++
++ if (down_interruptible(&cam->busy_lock))
++ return -EINTR;
++
++ queue = &cam->enc_queue;
++ poll_wait(file, queue, wait);
++
++ up(&cam->busy_lock);
++
++ return res;
++}
++
++/*!
++ * This structure defines the functions to be called in this driver.
++ */
++static struct v4l2_file_operations mxc_v4l_fops = {
++ .owner = THIS_MODULE,
++ .open = mxc_v4l_open,
++ .release = mxc_v4l_close,
++ .read = mxc_v4l_read,
++ .ioctl = mxc_v4l_ioctl,
++ .mmap = mxc_mmap,
++ .poll = mxc_poll,
++};
++
++static struct video_device mxc_v4l_template = {
++ .name = "Mxc Camera",
++ .fops = &mxc_v4l_fops,
++ .release = video_device_release,
++};
++
++/*!
++ * This function can be used to release any platform data on closing.
++ */
++static void camera_platform_release(struct device *device)
++{
++}
++
++/*!
++ * Camera V4l2 callback function.
++ *
++ * @param mask u32
++ *
++ * @param dev void device structure
++ *
++ * @return status
++ */
++static void camera_callback(u32 mask, void *dev)
++{
++ struct mxc_v4l_frame *done_frame;
++ struct mxc_v4l_frame *ready_frame;
++ struct timeval cur_time;
++
++ cam_data *cam = (cam_data *) dev;
++ if (cam == NULL)
++ return;
++
++ pr_debug("In MVC:camera_callback\n");
++
++ spin_lock(&cam->queue_int_lock);
++ spin_lock(&cam->dqueue_int_lock);
++ if (!list_empty(&cam->working_q)) {
++ do_gettimeofday(&cur_time);
++
++ done_frame = list_entry(cam->working_q.next,
++ struct mxc_v4l_frame,
++ queue);
++
++ if (done_frame->ipu_buf_num != cam->local_buf_num)
++ goto next;
++
++ /*
++ * Set the current time to done frame buffer's
++ * timestamp. Users can use this information to judge
++ * the frame's usage.
++ */
++ done_frame->buffer.timestamp = cur_time;
++
++ if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
++ done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE;
++ done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
++
++ /* Added to the done queue */
++ list_del(cam->working_q.next);
++ list_add_tail(&done_frame->queue, &cam->done_q);
++
++ /* Wake up the queue */
++ cam->enc_counter++;
++ wake_up_interruptible(&cam->enc_queue);
++ } else
++ pr_err("ERROR: v4l2 capture: camera_callback: "
++ "buffer not queued\n");
++ }
++
++next:
++ if (!list_empty(&cam->ready_q)) {
++ ready_frame = list_entry(cam->ready_q.next,
++ struct mxc_v4l_frame,
++ queue);
++ if (cam->enc_update_eba)
++ if (cam->enc_update_eba(cam->ipu,
++ ready_frame->buffer.m.offset,
++ &cam->ping_pong_csi) == 0) {
++ list_del(cam->ready_q.next);
++ list_add_tail(&ready_frame->queue,
++ &cam->working_q);
++ ready_frame->ipu_buf_num = cam->local_buf_num;
++ }
++ } else {
++ if (cam->enc_update_eba)
++ cam->enc_update_eba(
++ cam->ipu, cam->dummy_frame.buffer.m.offset,
++ &cam->ping_pong_csi);
++ }
++
++ cam->local_buf_num = (cam->local_buf_num == 0) ? 1 : 0;
++ spin_unlock(&cam->dqueue_int_lock);
++ spin_unlock(&cam->queue_int_lock);
++
++ return;
++}
++
++/*!
++ * initialize cam_data structure
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
++{
++ const struct of_device_id *of_id =
++ of_match_device(mxc_v4l2_dt_ids, &pdev->dev);
++ struct device_node *np = pdev->dev.of_node;
++ int ipu_id, csi_id, mclk_source;
++ int ret = 0;
++
++ pr_debug("In MVC: init_camera_struct\n");
++
++ ret = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (ret) {
++ dev_err(&pdev->dev, "ipu_id missing or invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "csi_id", &csi_id);
++ if (ret) {
++ dev_err(&pdev->dev, "csi_id missing or invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "mclk_source", &mclk_source);
++ if (ret) {
++ dev_err(&pdev->dev, "sensor mclk missing or invalid\n");
++ return ret;
++ }
++
++ /* Default everything to 0 */
++ memset(cam, 0, sizeof(cam_data));
++
++ /* get devtype to distinguish if the cpu is imx5 or imx6
++ * IMX5_V4L2 specify the cpu is imx5
++ * IMX6_V4L2 specify the cpu is imx6q or imx6sdl
++ */
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ cam->devtype = pdev->id_entry->driver_data;
++
++ cam->ipu = ipu_get_soc(ipu_id);
++ if (cam->ipu == NULL) {
++ pr_err("ERROR: v4l2 capture: failed to get ipu\n");
++ return -EINVAL;
++ } else if (cam->ipu == ERR_PTR(-ENODEV)) {
++ pr_err("ERROR: v4l2 capture: get invalid ipu\n");
++ return -ENODEV;
++ }
++
++ init_MUTEX(&cam->param_lock);
++ init_MUTEX(&cam->busy_lock);
++
++ cam->video_dev = video_device_alloc();
++ if (cam->video_dev == NULL)
++ return -ENODEV;
++
++ *(cam->video_dev) = mxc_v4l_template;
++
++ video_set_drvdata(cam->video_dev, cam);
++ dev_set_drvdata(&pdev->dev, (void *)cam);
++ cam->video_dev->minor = -1;
++
++ init_waitqueue_head(&cam->enc_queue);
++ init_waitqueue_head(&cam->still_queue);
++
++ /* setup cropping */
++ cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = 640;
++ cam->crop_bounds.top = 0;
++ cam->crop_bounds.height = 480;
++ cam->crop_current = cam->crop_defrect = cam->crop_bounds;
++ ipu_csi_set_window_size(cam->ipu, cam->crop_current.width,
++ cam->crop_current.height, cam->csi);
++ ipu_csi_set_window_pos(cam->ipu, cam->crop_current.left,
++ cam->crop_current.top, cam->csi);
++ cam->streamparm.parm.capture.capturemode = 0;
++
++ cam->standard.index = 0;
++ cam->standard.id = V4L2_STD_UNKNOWN;
++ cam->standard.frameperiod.denominator = 30;
++ cam->standard.frameperiod.numerator = 1;
++ cam->standard.framelines = 480;
++ cam->standard_autodetect = true;
++ cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod;
++ cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
++ cam->overlay_on = false;
++ cam->capture_on = false;
++ cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY;
++
++ cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2;
++ cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2;
++ cam->v2f.fmt.pix.width = 288;
++ cam->v2f.fmt.pix.height = 352;
++ cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
++ cam->win.w.width = 160;
++ cam->win.w.height = 160;
++ cam->win.w.left = 0;
++ cam->win.w.top = 0;
++
++ cam->ipu_id = ipu_id;
++ cam->csi = csi_id;
++ cam->mclk_source = mclk_source;
++ cam->mclk_on[cam->mclk_source] = false;
++
++ cam->enc_callback = camera_callback;
++ init_waitqueue_head(&cam->power_queue);
++ spin_lock_init(&cam->queue_int_lock);
++ spin_lock_init(&cam->dqueue_int_lock);
++
++ cam->self = kmalloc(sizeof(struct v4l2_int_device), GFP_KERNEL);
++ cam->self->module = THIS_MODULE;
++ sprintf(cam->self->name, "mxc_v4l2_cap%d", cam->csi);
++ cam->self->type = v4l2_int_type_master;
++ cam->self->u.master = &mxc_v4l2_master;
++
++ return 0;
++}
++
++static ssize_t show_streaming(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct video_device *video_dev = container_of(dev,
++ struct video_device, dev);
++ cam_data *cam = video_get_drvdata(video_dev);
++
++ if (cam->capture_on)
++ return sprintf(buf, "stream on\n");
++ else
++ return sprintf(buf, "stream off\n");
++}
++static DEVICE_ATTR(fsl_v4l2_capture_property, S_IRUGO, show_streaming, NULL);
++
++static ssize_t show_overlay(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct video_device *video_dev = container_of(dev,
++ struct video_device, dev);
++ cam_data *cam = video_get_drvdata(video_dev);
++
++ if (cam->overlay_on)
++ return sprintf(buf, "overlay on\n");
++ else
++ return sprintf(buf, "overlay off\n");
++}
++static DEVICE_ATTR(fsl_v4l2_overlay_property, S_IRUGO, show_overlay, NULL);
++
++static ssize_t show_csi(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct video_device *video_dev = container_of(dev,
++ struct video_device, dev);
++ cam_data *cam = video_get_drvdata(video_dev);
++
++ return sprintf(buf, "ipu%d_csi%d\n", cam->ipu_id, cam->csi);
++}
++static DEVICE_ATTR(fsl_csi_property, S_IRUGO, show_csi, NULL);
++
++/*!
++ * This function is called to probe the devices if registered.
++ *
++ * @param pdev the device structure used to give information on which device
++ * to probe
++ *
++ * @return The function returns 0 on success and -1 on failure.
++ */
++static int mxc_v4l2_probe(struct platform_device *pdev)
++{
++ /* Create cam and initialize it. */
++ cam_data *cam = kmalloc(sizeof(cam_data), GFP_KERNEL);
++ if (cam == NULL) {
++ pr_err("ERROR: v4l2 capture: failed to register camera\n");
++ return -1;
++ }
++
++ init_camera_struct(cam, pdev);
++ pdev->dev.release = camera_platform_release;
++
++ /* Set up the v4l2 device and register it*/
++ cam->self->priv = cam;
++ v4l2_int_device_register(cam->self);
++
++ /* register v4l video device */
++ if (video_register_device(cam->video_dev, VFL_TYPE_GRABBER, video_nr)
++ == -1) {
++ kfree(cam);
++ cam = NULL;
++ pr_err("ERROR: v4l2 capture: video_register_device failed\n");
++ return -1;
++ }
++ pr_debug(" Video device registered: %s #%d\n",
++ cam->video_dev->name, cam->video_dev->minor);
++
++ if (device_create_file(&cam->video_dev->dev,
++ &dev_attr_fsl_v4l2_capture_property))
++ dev_err(&pdev->dev, "Error on creating sysfs file"
++ " for capture\n");
++
++ if (device_create_file(&cam->video_dev->dev,
++ &dev_attr_fsl_v4l2_overlay_property))
++ dev_err(&pdev->dev, "Error on creating sysfs file"
++ " for overlay\n");
++
++ if (device_create_file(&cam->video_dev->dev,
++ &dev_attr_fsl_csi_property))
++ dev_err(&pdev->dev, "Error on creating sysfs file"
++ " for csi number\n");
++
++ return 0;
++}
++
++/*!
++ * This function is called to remove the devices when device unregistered.
++ *
++ * @param pdev the device structure used to give information on which device
++ * to remove
++ *
++ * @return The function returns 0 on success and -1 on failure.
++ */
++static int mxc_v4l2_remove(struct platform_device *pdev)
++{
++ cam_data *cam = (cam_data *)platform_get_drvdata(pdev);
++ if (cam->open_count) {
++ pr_err("ERROR: v4l2 capture:camera open "
++ "-- setting ops to NULL\n");
++ return -EBUSY;
++ } else {
++ device_remove_file(&cam->video_dev->dev,
++ &dev_attr_fsl_v4l2_capture_property);
++ device_remove_file(&cam->video_dev->dev,
++ &dev_attr_fsl_v4l2_overlay_property);
++ device_remove_file(&cam->video_dev->dev,
++ &dev_attr_fsl_csi_property);
++
++ pr_info("V4L2 freeing image input device\n");
++ v4l2_int_device_unregister(cam->self);
++ video_unregister_device(cam->video_dev);
++
++ mxc_free_frame_buf(cam);
++ kfree(cam);
++ }
++
++ pr_info("V4L2 unregistering video\n");
++ return 0;
++}
++
++/*!
++ * This function is called to put the sensor in a low power state.
++ * Refer to the document driver-model/driver.txt in the kernel source tree
++ * for more information.
++ *
++ * @param pdev the device structure used to give information on which I2C
++ * to suspend
++ * @param state the power state the device is entering
++ *
++ * @return The function returns 0 on success and -1 on failure.
++ */
++static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ cam_data *cam = platform_get_drvdata(pdev);
++
++ pr_debug("In MVC:mxc_v4l2_suspend\n");
++
++ if (cam == NULL)
++ return -1;
++
++ down(&cam->busy_lock);
++
++ cam->low_power = true;
++
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++ if ((cam->capture_on == true) && cam->enc_disable)
++ cam->enc_disable(cam);
++
++ if (cam->sensor && cam->open_count) {
++ if (cam->mclk_on[cam->mclk_source]) {
++ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C,
++ cam->mclk_source,
++ false, false);
++ cam->mclk_on[cam->mclk_source] = false;
++ }
++ vidioc_int_s_power(cam->sensor, 0);
++ }
++
++ up(&cam->busy_lock);
++
++ return 0;
++}
++
++/*!
++ * This function is called to bring the sensor back from a low power state.
++ * Refer to the document driver-model/driver.txt in the kernel source tree
++ * for more information.
++ *
++ * @param pdev the device structure
++ *
++ * @return The function returns 0 on success and -1 on failure
++ */
++static int mxc_v4l2_resume(struct platform_device *pdev)
++{
++ cam_data *cam = platform_get_drvdata(pdev);
++
++ pr_debug("In MVC:mxc_v4l2_resume\n");
++
++ if (cam == NULL)
++ return -1;
++
++ down(&cam->busy_lock);
++
++ cam->low_power = false;
++ wake_up_interruptible(&cam->power_queue);
++
++ if (cam->sensor && cam->open_count) {
++ vidioc_int_s_power(cam->sensor, 1);
++
++ if (!cam->mclk_on[cam->mclk_source]) {
++ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C,
++ cam->mclk_source,
++ true, true);
++ cam->mclk_on[cam->mclk_source] = true;
++ }
++ }
++
++ if (cam->overlay_on == true)
++ start_preview(cam);
++ if (cam->capture_on == true)
++ mxc_streamon(cam);
++
++ up(&cam->busy_lock);
++
++ return 0;
++}
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxc_v4l2_driver = {
++ .driver = {
++ .name = "mxc_v4l2_capture",
++ .owner = THIS_MODULE,
++ .of_match_table = mxc_v4l2_dt_ids,
++ },
++ .id_table = imx_v4l2_devtype,
++ .probe = mxc_v4l2_probe,
++ .remove = mxc_v4l2_remove,
++ .suspend = mxc_v4l2_suspend,
++ .resume = mxc_v4l2_resume,
++ .shutdown = NULL,
++};
++
++/*!
++ * Initializes the camera driver.
++ */
++static int mxc_v4l2_master_attach(struct v4l2_int_device *slave)
++{
++ cam_data *cam = slave->u.slave->master->priv;
++ struct v4l2_format cam_fmt;
++ int i;
++ struct sensor_data *sdata = slave->priv;
++
++ pr_debug("In MVC: mxc_v4l2_master_attach\n");
++ pr_debug(" slave.name = %s\n", slave->name);
++ pr_debug(" master.name = %s\n", slave->u.slave->master->name);
++
++ if (slave == NULL) {
++ pr_err("ERROR: v4l2 capture: slave parameter not valid.\n");
++ return -1;
++ }
++
++ if (sdata->csi != cam->csi) {
++ pr_debug("%s: csi doesn't match\n", __func__);
++ return -1;
++ }
++
++ cam->sensor = slave;
++
++ if (cam->sensor_index < MXC_SENSOR_NUM) {
++ cam->all_sensors[cam->sensor_index] = slave;
++ cam->sensor_index++;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave number exceeds the maximum.\n");
++ return -1;
++ }
++
++ for (i = 0; i < cam->sensor_index; i++) {
++ vidioc_int_dev_exit(cam->all_sensors[i]);
++ vidioc_int_s_power(cam->all_sensors[i], 0);
++ }
++
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++
++ /* Used to detect TV in (type 1) vs. camera (type 0)*/
++ cam->device_type = cam_fmt.fmt.pix.priv;
++
++ /* Set the input size to the ipu for this device */
++ cam->crop_bounds.top = cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = cam_fmt.fmt.pix.width;
++ cam->crop_bounds.height = cam_fmt.fmt.pix.height;
++
++ /* This also is the max crop size for this device. */
++ cam->crop_defrect.top = cam->crop_defrect.left = 0;
++ cam->crop_defrect.width = cam_fmt.fmt.pix.width;
++ cam->crop_defrect.height = cam_fmt.fmt.pix.height;
++
++ /* At this point, this is also the current image size. */
++ cam->crop_current.top = cam->crop_current.left = 0;
++ cam->crop_current.width = cam_fmt.fmt.pix.width;
++ cam->crop_current.height = cam_fmt.fmt.pix.height;
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ return 0;
++}
++
++/*!
++ * Disconnects the camera driver.
++ */
++static void mxc_v4l2_master_detach(struct v4l2_int_device *slave)
++{
++ unsigned int i;
++ cam_data *cam = slave->u.slave->master->priv;
++
++ pr_debug("In MVC:mxc_v4l2_master_detach\n");
++
++ if (cam->sensor_index > 1) {
++ for (i = 0; i < cam->sensor_index; i++) {
++ if (cam->all_sensors[i] != slave)
++ continue;
++ /* Move all the sensors behind this
++ * sensor one step forward
++ */
++ for (; i <= MXC_SENSOR_NUM - 2; i++)
++ cam->all_sensors[i] = cam->all_sensors[i+1];
++ break;
++ }
++ /* Point current sensor to the last one */
++ cam->sensor = cam->all_sensors[cam->sensor_index - 2];
++ } else
++ cam->sensor = NULL;
++
++ cam->sensor_index--;
++ vidioc_int_dev_exit(slave);
++}
++
++/*!
++ * Entry point for the V4L2
++ *
++ * @return Error code indicating success or failure
++ */
++static __init int camera_init(void)
++{
++ u8 err = 0;
++
++ pr_debug("In MVC:camera_init\n");
++
++ /* Register the device driver structure. */
++ err = platform_driver_register(&mxc_v4l2_driver);
++ if (err != 0) {
++ pr_err("ERROR: v4l2 capture:camera_init: "
++ "platform_driver_register failed.\n");
++ return err;
++ }
++
++ return err;
++}
++
++/*!
++ * Exit and cleanup for the V4L2
++ */
++static void __exit camera_exit(void)
++{
++ pr_debug("In MVC: camera_exit\n");
++
++ platform_driver_unregister(&mxc_v4l2_driver);
++}
++
++module_init(camera_init);
++module_exit(camera_exit);
++
++module_param(video_nr, int, 0444);
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("V4L2 capture driver for Mxc based cameras");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("video");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h 2014-05-15 20:33:57.138007668 +0200
+@@ -0,0 +1,260 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup MXC_V4L2_CAPTURE MXC V4L2 Video Capture Driver
++ */
++/*!
++ * @file mxc_v4l2_capture.h
++ *
++ * @brief mxc V4L2 capture device API Header file
++ *
++ * It include all the defines for frame operations, also three structure defines
++ * use case ops structure, common v4l2 driver structure and frame structure.
++ *
++ * @ingroup MXC_V4L2_CAPTURE
++ */
++#ifndef __MXC_V4L2_CAPTURE_H__
++#define __MXC_V4L2_CAPTURE_H__
++
++#include <linux/uaccess.h>
++#include <linux/list.h>
++#include <linux/mxc_v4l2.h>
++#include <linux/completion.h>
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++#include <linux/ipu-v3.h>
++#include <linux/platform_data/dma-imx.h>
++
++#include <media/v4l2-dev.h>
++#include <media/v4l2-int-device.h>
++
++
++#define FRAME_NUM 10
++#define MXC_SENSOR_NUM 2
++
++enum imx_v4l2_devtype {
++ IMX5_V4L2,
++ IMX6_V4L2,
++};
++
++/*!
++ * v4l2 frame structure.
++ */
++struct mxc_v4l_frame {
++ u32 paddress;
++ void *vaddress;
++ int count;
++ int width;
++ int height;
++
++ struct v4l2_buffer buffer;
++ struct list_head queue;
++ int index;
++ union {
++ int ipu_buf_num;
++ int csi_buf_num;
++ };
++};
++
++/* Only for old version. Will go away soon. */
++typedef struct {
++ u8 clk_mode;
++ u8 ext_vsync;
++ u8 Vsync_pol;
++ u8 Hsync_pol;
++ u8 pixclk_pol;
++ u8 data_pol;
++ u8 data_width;
++ u8 pack_tight;
++ u8 force_eof;
++ u8 data_en_pol;
++ u16 width;
++ u16 height;
++ u32 pixel_fmt;
++ u32 mclk;
++ u16 active_width;
++ u16 active_height;
++} sensor_interface;
++
++/* Sensor control function */
++/* Only for old version. Will go away soon. */
++struct camera_sensor {
++ void (*set_color) (int bright, int saturation, int red, int green,
++ int blue);
++ void (*get_color) (int *bright, int *saturation, int *red, int *green,
++ int *blue);
++ void (*set_ae_mode) (int ae_mode);
++ void (*get_ae_mode) (int *ae_mode);
++ sensor_interface *(*config) (int *frame_rate, int high_quality);
++ sensor_interface *(*reset) (void);
++ void (*get_std) (v4l2_std_id *std);
++ void (*set_std) (v4l2_std_id std);
++ unsigned int csi;
++};
++
++/*!
++ * common v4l2 driver structure.
++ */
++typedef struct _cam_data {
++ struct video_device *video_dev;
++ int device_type;
++
++ /* semaphore guard against SMP multithreading */
++ struct semaphore busy_lock;
++
++ int open_count;
++
++ /* params lock for this camera */
++ struct semaphore param_lock;
++
++ /* Encoder */
++ struct list_head ready_q;
++ struct list_head done_q;
++ struct list_head working_q;
++ int ping_pong_csi;
++ spinlock_t queue_int_lock;
++ spinlock_t dqueue_int_lock;
++ struct mxc_v4l_frame frame[FRAME_NUM];
++ struct mxc_v4l_frame dummy_frame;
++ wait_queue_head_t enc_queue;
++ int enc_counter;
++ dma_addr_t rot_enc_bufs[2];
++ void *rot_enc_bufs_vaddr[2];
++ int rot_enc_buf_size[2];
++ enum v4l2_buf_type type;
++
++ /* still image capture */
++ wait_queue_head_t still_queue;
++ int still_counter;
++ dma_addr_t still_buf[2];
++ void *still_buf_vaddr;
++
++ /* overlay */
++ struct v4l2_window win;
++ struct v4l2_framebuffer v4l2_fb;
++ dma_addr_t vf_bufs[2];
++ void *vf_bufs_vaddr[2];
++ int vf_bufs_size[2];
++ dma_addr_t rot_vf_bufs[2];
++ void *rot_vf_bufs_vaddr[2];
++ int rot_vf_buf_size[2];
++ bool overlay_active;
++ int output;
++ struct fb_info *overlay_fb;
++ int fb_origin_std;
++ struct work_struct csi_work_struct;
++
++ /* v4l2 format */
++ struct v4l2_format v2f;
++ int rotation; /* for IPUv1 and IPUv3, this means encoder rotation */
++ int vf_rotation; /* viewfinder rotation only for IPUv1 and IPUv3 */
++ struct v4l2_mxc_offset offset;
++
++ /* V4l2 control bit */
++ int bright;
++ int hue;
++ int contrast;
++ int saturation;
++ int red;
++ int green;
++ int blue;
++ int ae_mode;
++
++ /* standard */
++ struct v4l2_streamparm streamparm;
++ struct v4l2_standard standard;
++ bool standard_autodetect;
++
++ /* crop */
++ struct v4l2_rect crop_bounds;
++ struct v4l2_rect crop_defrect;
++ struct v4l2_rect crop_current;
++
++ int (*enc_update_eba) (struct ipu_soc *ipu, dma_addr_t eba,
++ int *bufferNum);
++ int (*enc_enable) (void *private);
++ int (*enc_disable) (void *private);
++ int (*enc_enable_csi) (void *private);
++ int (*enc_disable_csi) (void *private);
++ void (*enc_callback) (u32 mask, void *dev);
++ int (*vf_start_adc) (void *private);
++ int (*vf_stop_adc) (void *private);
++ int (*vf_start_sdc) (void *private);
++ int (*vf_stop_sdc) (void *private);
++ int (*vf_enable_csi) (void *private);
++ int (*vf_disable_csi) (void *private);
++ int (*csi_start) (void *private);
++ int (*csi_stop) (void *private);
++
++ /* misc status flag */
++ bool overlay_on;
++ bool capture_on;
++ int overlay_pid;
++ int capture_pid;
++ bool low_power;
++ wait_queue_head_t power_queue;
++ unsigned int ipu_id;
++ unsigned int csi;
++ u8 mclk_source;
++ bool mclk_on[2]; /* two mclk sources at most now */
++ int current_input;
++
++ int local_buf_num;
++
++ /* camera sensor interface */
++ struct camera_sensor *cam_sensor; /* old version */
++ struct v4l2_int_device *all_sensors[MXC_SENSOR_NUM];
++ struct v4l2_int_device *sensor;
++ struct v4l2_int_device *self;
++ int sensor_index;
++ void *ipu;
++ enum imx_v4l2_devtype devtype;
++
++ /* v4l2 buf elements related to PxP DMA */
++ struct completion pxp_tx_cmpl;
++ struct pxp_channel *pxp_chan;
++ struct pxp_config_data pxp_conf;
++ struct dma_async_tx_descriptor *txd;
++ dma_cookie_t cookie;
++ struct scatterlist sg[2];
++} cam_data;
++
++struct sensor_data {
++ const struct ov5642_platform_data *platform_data;
++ struct v4l2_int_device *v4l2_int_device;
++ struct i2c_client *i2c_client;
++ struct v4l2_pix_format pix;
++ struct v4l2_captureparm streamcap;
++ bool on;
++
++ /* control settings */
++ int brightness;
++ int hue;
++ int contrast;
++ int saturation;
++ int red;
++ int green;
++ int blue;
++ int ae_mode;
++
++ u32 mclk;
++ u8 mclk_source;
++ struct clk *sensor_clk;
++ int csi;
++
++ void (*io_init)(void);
++};
++
++void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi);
++#endif /* __MXC_V4L2_CAPTURE_H__ */
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ov5640.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ov5640.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ov5640.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ov5640.c 2014-05-15 20:33:57.138007668 +0200
+@@ -0,0 +1,1951 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-chip-ident.h>
++#include <media/v4l2-int-device.h>
++#include "mxc_v4l2_capture.h"
++
++#define OV5640_VOLTAGE_ANALOG 2800000
++#define OV5640_VOLTAGE_DIGITAL_CORE 1500000
++#define OV5640_VOLTAGE_DIGITAL_IO 1800000
++
++#define MIN_FPS 15
++#define MAX_FPS 30
++#define DEFAULT_FPS 30
++
++#define OV5640_XCLK_MIN 6000000
++#define OV5640_XCLK_MAX 24000000
++
++#define OV5640_CHIP_ID_HIGH_BYTE 0x300A
++#define OV5640_CHIP_ID_LOW_BYTE 0x300B
++
++enum ov5640_mode {
++ ov5640_mode_MIN = 0,
++ ov5640_mode_VGA_640_480 = 0,
++ ov5640_mode_QVGA_320_240 = 1,
++ ov5640_mode_NTSC_720_480 = 2,
++ ov5640_mode_PAL_720_576 = 3,
++ ov5640_mode_720P_1280_720 = 4,
++ ov5640_mode_1080P_1920_1080 = 5,
++ ov5640_mode_QSXGA_2592_1944 = 6,
++ ov5640_mode_QCIF_176_144 = 7,
++ ov5640_mode_XGA_1024_768 = 8,
++ ov5640_mode_MAX = 8
++};
++
++enum ov5640_frame_rate {
++ ov5640_15_fps,
++ ov5640_30_fps
++};
++
++static int ov5640_framerates[] = {
++ [ov5640_15_fps] = 15,
++ [ov5640_30_fps] = 30,
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u8 u8Val;
++ u8 u8Mask;
++ u32 u32Delay_ms;
++};
++
++struct ov5640_mode_info {
++ enum ov5640_mode mode;
++ u32 width;
++ u32 height;
++ struct reg_value *init_data_ptr;
++ u32 init_data_size;
++};
++
++/*!
++ * Maintains the information on the current state of the sesor.
++ */
++static struct sensor_data ov5640_data;
++static int pwn_gpio, rst_gpio;
++static int prev_sysclk;
++static int AE_Target = 52, night_mode;
++static int prev_HTS;
++static int AE_high, AE_low;
++
++static struct reg_value ov5640_global_init_setting[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0},
++ {0x3034, 0x1a, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0},
++ {0x3630, 0x36, 0, 0}, {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0},
++ {0x3633, 0x12, 0, 0}, {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0},
++ {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0},
++ {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0},
++ {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0},
++ {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0},
++ {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0},
++ {0x3a13, 0x43, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3635, 0x13, 0, 0}, {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0},
++ {0x3622, 0x01, 0, 0}, {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0},
++ {0x3c05, 0x98, 0, 0}, {0x3c06, 0x00, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3c08, 0x00, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0},
++ {0x3c0b, 0x40, 0, 0}, {0x3810, 0x00, 0, 0}, {0x3811, 0x10, 0, 0},
++ {0x3812, 0x00, 0, 0}, {0x3708, 0x64, 0, 0}, {0x4001, 0x02, 0, 0},
++ {0x4005, 0x1a, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3004, 0xff, 0, 0},
++ {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x440e, 0x00, 0, 0}, {0x5000, 0xa7, 0, 0},
++ {0x3008, 0x02, 0, 0},
++};
++
++static struct reg_value ov5640_init_setting_30fps_VGA[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0},
++ {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0},
++ {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x36, 0, 0},
++ {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
++ {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
++ {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
++ {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
++ {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
++ {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
++ {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
++ {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
++ {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
++ {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5000, 0xa7, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0xf2, 0, 0},
++ {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, {0x5187, 0x09, 0, 0},
++ {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0}, {0x518a, 0x54, 0, 0},
++ {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x50, 0, 0},
++ {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x6c, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x09, 0, 0},
++ {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0}, {0x5381, 0x1e, 0, 0},
++ {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0}, {0x5384, 0x0a, 0, 0},
++ {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, {0x5387, 0x7c, 0, 0},
++ {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, {0x538a, 0x01, 0, 0},
++ {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, {0x5301, 0x30, 0, 0},
++ {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, {0x5304, 0x08, 0, 0},
++ {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, {0x5307, 0x16, 0, 0},
++ {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, {0x530b, 0x04, 0, 0},
++ {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, {0x5481, 0x08, 0, 0},
++ {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, {0x5484, 0x51, 0, 0},
++ {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, {0x5487, 0x7d, 0, 0},
++ {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, {0x548a, 0x9a, 0, 0},
++ {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, {0x548d, 0xcd, 0, 0},
++ {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, {0x5490, 0x1d, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x10, 0, 0},
++ {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, {0x558b, 0xf8, 0, 0},
++ {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0}, {0x5802, 0x0f, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0}, {0x5805, 0x26, 0, 0},
++ {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, {0x5808, 0x05, 0, 0},
++ {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, {0x580b, 0x0d, 0, 0},
++ {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0}, {0x580e, 0x00, 0, 0},
++ {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, {0x5811, 0x09, 0, 0},
++ {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x00, 0, 0},
++ {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0}, {0x5817, 0x08, 0, 0},
++ {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0}, {0x581a, 0x05, 0, 0},
++ {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0}, {0x581d, 0x0e, 0, 0},
++ {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0}, {0x5820, 0x11, 0, 0},
++ {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, {0x5823, 0x28, 0, 0},
++ {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0}, {0x5829, 0x26, 0, 0},
++ {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0}, {0x582c, 0x24, 0, 0},
++ {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0}, {0x582f, 0x22, 0, 0},
++ {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0}, {0x5832, 0x24, 0, 0},
++ {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0}, {0x5835, 0x22, 0, 0},
++ {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0}, {0x5838, 0x44, 0, 0},
++ {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0}, {0x583b, 0x28, 0, 0},
++ {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0}, {0x5025, 0x00, 0, 0},
++ {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0},
++ {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0},
++ {0x3008, 0x02, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_VGA_640_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_VGA_640_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0},
++ {0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0},
++ {0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_PAL_720_576[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_PAL_720_576[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_720P_1280_720[] = {
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0},
++ {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0},
++ {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
++ {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_720P_1280_720[] = {
++ {0x3035, 0x41, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0},
++ {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0},
++ {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
++ {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0},
++ {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0},
++ {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++
++static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = {
++ {0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0},
++ {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0xee, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x05, 0, 0},
++ {0x3807, 0xc3, 0, 0}, {0x3808, 0x07, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, {0x380c, 0x0b, 0, 0},
++ {0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0},
++ {0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0},
++ {0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0},
++ {0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = {
++ {0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0},
++ {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9f, 0, 0}, {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0},
++ {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0},
++ {0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0},
++ {0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0},
++ {0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0},
++ {0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = {
++ {
++ {ov5640_mode_VGA_640_480, 640, 480,
++ ov5640_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, 320, 240,
++ ov5640_setting_15fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, 720, 480,
++ ov5640_setting_15fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, 720, 576,
++ ov5640_setting_15fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, 1280, 720,
++ ov5640_setting_15fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, 1920, 1080,
++ ov5640_setting_15fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)},
++ {ov5640_mode_QSXGA_2592_1944, 2592, 1944,
++ ov5640_setting_15fps_QSXGA_2592_1944,
++ ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)},
++ {ov5640_mode_QCIF_176_144, 176, 144,
++ ov5640_setting_15fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, 1024, 768,
++ ov5640_setting_15fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)},
++ },
++ {
++ {ov5640_mode_VGA_640_480, 640, 480,
++ ov5640_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, 320, 240,
++ ov5640_setting_30fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, 720, 480,
++ ov5640_setting_30fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, 720, 576,
++ ov5640_setting_30fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, 1280, 720,
++ ov5640_setting_30fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, 0, 0, NULL, 0},
++ {ov5640_mode_QSXGA_2592_1944, 0, 0, NULL, 0},
++ {ov5640_mode_QCIF_176_144, 176, 144,
++ ov5640_setting_30fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, 1024, 768,
++ ov5640_setting_30fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)},
++ },
++};
++
++static struct regulator *io_regulator;
++static struct regulator *core_regulator;
++static struct regulator *analog_regulator;
++
++static int ov5640_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int ov5640_remove(struct i2c_client *client);
++
++static s32 ov5640_read_reg(u16 reg, u8 *val);
++static s32 ov5640_write_reg(u16 reg, u8 val);
++
++static const struct i2c_device_id ov5640_id[] = {
++ {"ov5640", 0},
++ {"ov564x", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, ov5640_id);
++
++static struct i2c_driver ov5640_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ov5640",
++ },
++ .probe = ov5640_probe,
++ .remove = ov5640_remove,
++ .id_table = ov5640_id,
++};
++
++static inline void ov5640_power_down(int enable)
++{
++ gpio_set_value(pwn_gpio, enable);
++
++ msleep(2);
++}
++
++static inline void ov5640_reset(void)
++{
++ /* camera reset */
++ gpio_set_value(rst_gpio, 1);
++
++ /* camera power down */
++ gpio_set_value(pwn_gpio, 1);
++ msleep(5);
++ gpio_set_value(pwn_gpio, 0);
++ msleep(5);
++ gpio_set_value(rst_gpio, 0);
++ msleep(1);
++ gpio_set_value(rst_gpio, 1);
++ msleep(5);
++ gpio_set_value(pwn_gpio, 1);
++}
++
++static int ov5640_regulator_enable(struct device *dev)
++{
++ int ret = 0;
++
++ io_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(io_regulator)) {
++ regulator_set_voltage(io_regulator,
++ OV5640_VOLTAGE_DIGITAL_IO,
++ OV5640_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(io_regulator);
++ if (ret) {
++ dev_err(dev, "set io voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set io voltage ok\n");
++ }
++ } else {
++ io_regulator = NULL;
++ dev_warn(dev, "cannot get io voltage\n");
++ }
++
++ core_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(core_regulator)) {
++ regulator_set_voltage(core_regulator,
++ OV5640_VOLTAGE_DIGITAL_CORE,
++ OV5640_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(core_regulator);
++ if (ret) {
++ dev_err(dev, "set core voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set core voltage ok\n");
++ }
++ } else {
++ core_regulator = NULL;
++ dev_warn(dev, "cannot get core voltage\n");
++ }
++
++ analog_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(analog_regulator)) {
++ regulator_set_voltage(analog_regulator,
++ OV5640_VOLTAGE_ANALOG,
++ OV5640_VOLTAGE_ANALOG);
++ ret = regulator_enable(analog_regulator);
++ if (ret) {
++ dev_err(dev, "set analog voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set analog voltage ok\n");
++ }
++ } else {
++ analog_regulator = NULL;
++ dev_warn(dev, "cannot get analog voltage\n");
++ }
++
++ return ret;
++}
++
++static s32 ov5640_write_reg(u16 reg, u8 val)
++{
++ u8 au8Buf[3] = {0};
++
++ au8Buf[0] = reg >> 8;
++ au8Buf[1] = reg & 0xff;
++ au8Buf[2] = val;
++
++ if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, val);
++ return -1;
++ }
++
++ return 0;
++}
++
++static s32 ov5640_read_reg(u16 reg, u8 *val)
++{
++ u8 au8RegBuf[2] = {0};
++ u8 u8RdVal = 0;
++
++ au8RegBuf[0] = reg >> 8;
++ au8RegBuf[1] = reg & 0xff;
++
++ if (2 != i2c_master_send(ov5640_data.i2c_client, au8RegBuf, 2)) {
++ pr_err("%s:write reg error:reg=%x\n",
++ __func__, reg);
++ return -1;
++ }
++
++ if (1 != i2c_master_recv(ov5640_data.i2c_client, &u8RdVal, 1)) {
++ pr_err("%s:read reg error:reg=%x,val=%x\n",
++ __func__, reg, u8RdVal);
++ return -1;
++ }
++
++ *val = u8RdVal;
++
++ return u8RdVal;
++}
++
++static void ov5640_soft_reset(void)
++{
++ /* sysclk from pad */
++ ov5640_write_reg(0x3103, 0x11);
++
++ /* software reset */
++ ov5640_write_reg(0x3008, 0x82);
++
++ /* delay at least 5ms */
++ msleep(10);
++}
++
++/* set sensor driver capability
++ * 0x302c[7:6] - strength
++ 00 - 1x
++ 01 - 2x
++ 10 - 3x
++ 11 - 4x
++ */
++static int ov5640_driver_capability(int strength)
++{
++ u8 temp = 0;
++
++ if (strength > 4 || strength < 1) {
++ pr_err("The valid driver capability of ov5640 is 1x~4x\n");
++ return -EINVAL;
++ }
++
++ ov5640_read_reg(0x302c, &temp);
++
++ temp &= ~0xc0; /* clear [7:6] */
++ temp |= ((strength - 1) << 6); /* set [7:6] */
++
++ ov5640_write_reg(0x302c, temp);
++
++ return 0;
++}
++
++/* calculate sysclk */
++static int ov5640_get_sysclk(void)
++{
++ int xvclk = ov5640_data.mclk / 10000;
++ int sysclk;
++ int temp1, temp2;
++ int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv;
++ int sclk_rdiv_map[] = {1, 2, 4, 8};
++ u8 regval = 0;
++
++ temp1 = ov5640_read_reg(0x3034, &regval);
++ temp2 = temp1 & 0x0f;
++ if (temp2 == 8 || temp2 == 10) {
++ Bit_div2x = temp2 / 2;
++ } else {
++ pr_err("ov5640: unsupported bit mode %d\n", temp2);
++ return -1;
++ }
++
++ temp1 = ov5640_read_reg(0x3035, &regval);
++ SysDiv = temp1 >> 4;
++ if (SysDiv == 0)
++ SysDiv = 16;
++
++ temp1 = ov5640_read_reg(0x3036, &regval);
++ Multiplier = temp1;
++ temp1 = ov5640_read_reg(0x3037, &regval);
++ PreDiv = temp1 & 0x0f;
++ Pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
++
++ temp1 = ov5640_read_reg(0x3108, &regval);
++ temp2 = temp1 & 0x03;
++
++ sclk_rdiv = sclk_rdiv_map[temp2];
++ VCO = xvclk * Multiplier / PreDiv;
++ sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv;
++
++ return sysclk;
++}
++
++/* read HTS from register settings */
++static int ov5640_get_HTS(void)
++{
++ int HTS;
++ u8 temp = 0;
++
++ HTS = ov5640_read_reg(0x380c, &temp);
++ HTS = (HTS<<8) + ov5640_read_reg(0x380d, &temp);
++ return HTS;
++}
++
++/* read VTS from register settings */
++static int ov5640_get_VTS(void)
++{
++ int VTS;
++ u8 temp = 0;
++
++ VTS = ov5640_read_reg(0x380e, &temp);
++ VTS = (VTS<<8) + ov5640_read_reg(0x380f, &temp);
++
++ return VTS;
++}
++
++/* write VTS to registers */
++static int ov5640_set_VTS(int VTS)
++{
++ int temp;
++
++ temp = VTS & 0xff;
++ ov5640_write_reg(0x380f, temp);
++
++ temp = VTS>>8;
++ ov5640_write_reg(0x380e, temp);
++ return 0;
++}
++
++/* read shutter, in number of line period */
++static int ov5640_get_shutter(void)
++{
++ int shutter;
++ u8 regval;
++
++ shutter = (ov5640_read_reg(0x03500, &regval) & 0x0f);
++
++ shutter = (shutter<<8) + ov5640_read_reg(0x3501, &regval);
++ shutter = (shutter<<4) + (ov5640_read_reg(0x3502, &regval)>>4);
++
++ return shutter;
++}
++
++/* write shutter, in number of line period */
++static int ov5640_set_shutter(int shutter)
++{
++ int temp;
++
++ shutter = shutter & 0xffff;
++ temp = shutter & 0x0f;
++ temp = temp<<4;
++ ov5640_write_reg(0x3502, temp);
++
++ temp = shutter & 0xfff;
++ temp = temp>>4;
++ ov5640_write_reg(0x3501, temp);
++
++ temp = shutter>>12;
++ ov5640_write_reg(0x3500, temp);
++
++ return 0;
++}
++
++/* read gain, 16 = 1x */
++static int ov5640_get_gain16(void)
++{
++ int gain16;
++ u8 regval;
++
++ gain16 = ov5640_read_reg(0x350a, &regval) & 0x03;
++ gain16 = (gain16<<8) + ov5640_read_reg(0x350b, &regval);
++
++ return gain16;
++}
++
++/* write gain, 16 = 1x */
++static int ov5640_set_gain16(int gain16)
++{
++ int temp;
++
++ gain16 = gain16 & 0x3ff;
++ temp = gain16 & 0xff;
++
++ ov5640_write_reg(0x350b, temp);
++ temp = gain16>>8;
++
++ ov5640_write_reg(0x350a, temp);
++ return 0;
++}
++
++/* get banding filter value */
++static int ov5640_get_light_freq(void)
++{
++ int temp, temp1, light_frequency;
++ u8 regval;
++
++ temp = ov5640_read_reg(0x3c01, &regval);
++ if (temp & 0x80) {
++ /* manual */
++ temp1 = ov5640_read_reg(0x3c00, &regval);
++ if (temp1 & 0x04) {
++ /* 50Hz */
++ light_frequency = 50;
++ } else {
++ /* 60Hz */
++ light_frequency = 60;
++ }
++ } else {
++ /* auto */
++ temp1 = ov5640_read_reg(0x3c0c, &regval);
++ if (temp1 & 0x01) {
++ /* 50Hz */
++ light_frequency = 50;
++ } else {
++ /* 60Hz */
++ light_frequency = 60;
++ }
++ }
++
++ return light_frequency;
++}
++
++static void ov5640_set_bandingfilter(void)
++{
++ int prev_VTS;
++ int band_step60, max_band60, band_step50, max_band50;
++
++ /* read preview PCLK */
++ prev_sysclk = ov5640_get_sysclk();
++
++ /* read preview HTS */
++ prev_HTS = ov5640_get_HTS();
++
++ /* read preview VTS */
++ prev_VTS = ov5640_get_VTS();
++
++ /* calculate banding filter */
++ /* 60Hz */
++ band_step60 = prev_sysclk * 100/prev_HTS * 100/120;
++ ov5640_write_reg(0x3a0a, (band_step60 >> 8));
++ ov5640_write_reg(0x3a0b, (band_step60 & 0xff));
++
++ max_band60 = (int)((prev_VTS-4)/band_step60);
++ ov5640_write_reg(0x3a0d, max_band60);
++
++ /* 50Hz */
++ band_step50 = prev_sysclk * 100/prev_HTS;
++ ov5640_write_reg(0x3a08, (band_step50 >> 8));
++ ov5640_write_reg(0x3a09, (band_step50 & 0xff));
++
++ max_band50 = (int)((prev_VTS-4)/band_step50);
++ ov5640_write_reg(0x3a0e, max_band50);
++}
++
++/* stable in high */
++static int ov5640_set_AE_target(int target)
++{
++ int fast_high, fast_low;
++
++ AE_low = target * 23 / 25; /* 0.92 */
++ AE_high = target * 27 / 25; /* 1.08 */
++ fast_high = AE_high << 1;
++
++ if (fast_high > 255)
++ fast_high = 255;
++ fast_low = AE_low >> 1;
++
++ ov5640_write_reg(0x3a0f, AE_high);
++ ov5640_write_reg(0x3a10, AE_low);
++ ov5640_write_reg(0x3a1b, AE_high);
++ ov5640_write_reg(0x3a1e, AE_low);
++ ov5640_write_reg(0x3a11, fast_high);
++ ov5640_write_reg(0x3a1f, fast_low);
++
++ return 0;
++}
++
++/* enable = 0 to turn off night mode
++ enable = 1 to turn on night mode */
++static int ov5640_set_night_mode(int enable)
++{
++ u8 mode;
++
++ ov5640_read_reg(0x3a00, &mode);
++
++ if (enable) {
++ /* night mode on */
++ mode |= 0x04;
++ ov5640_write_reg(0x3a00, mode);
++ } else {
++ /* night mode off */
++ mode &= 0xfb;
++ ov5640_write_reg(0x3a00, mode);
++ }
++
++ return 0;
++}
++
++/* enable = 0 to turn off AEC/AGC
++ enable = 1 to turn on AEC/AGC */
++void ov5640_turn_on_AE_AG(int enable)
++{
++ u8 ae_ag_ctrl;
++
++ ov5640_read_reg(0x3503, &ae_ag_ctrl);
++ if (enable) {
++ /* turn on auto AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl & ~(0x03);
++ } else {
++ /* turn off AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl | 0x03;
++ }
++ ov5640_write_reg(0x3503, ae_ag_ctrl);
++}
++
++/* download ov5640 settings to sensor through i2c */
++static int ov5640_download_firmware(struct reg_value *pModeSetting, s32 ArySize)
++{
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int i, retval = 0;
++
++ for (i = 0; i < ArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5640_read_reg(RegAddr, &RegVal);
++ if (retval < 0)
++ goto err;
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5640_write_reg(RegAddr, Val);
++ if (retval < 0)
++ goto err;
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++static int ov5640_init_mode(void)
++{
++ struct reg_value *pModeSetting = NULL;
++ int ArySize = 0, retval = 0;
++
++ ov5640_soft_reset();
++
++ pModeSetting = ov5640_global_init_setting;
++ ArySize = ARRAY_SIZE(ov5640_global_init_setting);
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ pModeSetting = ov5640_init_setting_30fps_VGA;
++ ArySize = ARRAY_SIZE(ov5640_init_setting_30fps_VGA);
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* change driver capability to 2x according to validation board.
++ * if the image is not stable, please increase the driver strength.
++ */
++ ov5640_driver_capability(2);
++ ov5640_set_bandingfilter();
++ ov5640_set_AE_target(AE_Target);
++ ov5640_set_night_mode(night_mode);
++
++ /* skip 9 vysnc: start capture at 10th vsync */
++ msleep(300);
++
++ /* turn off night mode */
++ night_mode = 0;
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++err:
++ return retval;
++}
++
++/* change to or back to subsampling mode set the mode directly
++ * image size below 1280 * 960 is subsampling mode */
++static int ov5640_change_mode_direct(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) {
++ pr_err("Wrong ov5640 mode detected!\n");
++ return -1;
++ }
++
++ pModeSetting = ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width = ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height = ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* set ov5640 to subsampling mode */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++
++ /* turn on AE AG for subsampling mode, in case the firmware didn't */
++ ov5640_turn_on_AE_AG(1);
++
++ /* calculate banding filter */
++ ov5640_set_bandingfilter();
++
++ /* set AE target */
++ ov5640_set_AE_target(AE_Target);
++
++ /* update night mode setting */
++ ov5640_set_night_mode(night_mode);
++
++ /* skip 9 vysnc: start capture at 10th vsync */
++ if (mode == ov5640_mode_XGA_1024_768 && frame_rate == ov5640_30_fps) {
++ pr_warning("ov5640: actual frame rate of XGA is 22.5fps\n");
++ /* 1/22.5 * 9*/
++ msleep(400);
++ return retval;
++ }
++
++ if (frame_rate == ov5640_15_fps) {
++ /* 1/15 * 9*/
++ msleep(600);
++ } else if (frame_rate == ov5640_30_fps) {
++ /* 1/30 * 9*/
++ msleep(300);
++ }
++
++ return retval;
++}
++
++/* change to scaling mode go through exposure calucation
++ * image size above 1280 * 960 is scaling mode */
++static int ov5640_change_mode_exposure_calc(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ int prev_shutter, prev_gain16, average;
++ int cap_shutter, cap_gain16;
++ int cap_sysclk, cap_HTS, cap_VTS;
++ int light_freq, cap_bandfilt, cap_maxband;
++ long cap_gain16_shutter;
++ u8 temp;
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width =
++ ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height =
++ ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* read preview shutter */
++ prev_shutter = ov5640_get_shutter();
++
++ /* read preview gain */
++ prev_gain16 = ov5640_get_gain16();
++
++ /* get average */
++ average = ov5640_read_reg(0x56a1, &temp);
++
++ /* turn off night mode for capture */
++ ov5640_set_night_mode(0);
++
++ /* turn off overlay */
++ ov5640_write_reg(0x3022, 0x06);
++
++ /* Write capture setting */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* turn off AE AG when capture image. */
++ ov5640_turn_on_AE_AG(0);
++
++ /* read capture VTS */
++ cap_VTS = ov5640_get_VTS();
++ cap_HTS = ov5640_get_HTS();
++ cap_sysclk = ov5640_get_sysclk();
++
++ /* calculate capture banding filter */
++ light_freq = ov5640_get_light_freq();
++ if (light_freq == 60) {
++ /* 60Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120;
++ } else {
++ /* 50Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS;
++ }
++ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt);
++ /* calculate capture shutter/gain16 */
++ if (average > AE_low && average < AE_high) {
++ /* in stable range */
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk *
++ prev_HTS/cap_HTS * AE_Target / average;
++ } else {
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk *
++ prev_HTS/cap_HTS;
++ }
++
++ /* gain to shutter */
++ if (cap_gain16_shutter < (cap_bandfilt * 16)) {
++ /* shutter < 1/100 */
++ cap_shutter = cap_gain16_shutter/16;
++ if (cap_shutter < 1)
++ cap_shutter = 1;
++ cap_gain16 = cap_gain16_shutter/cap_shutter;
++ if (cap_gain16 < 16)
++ cap_gain16 = 16;
++ } else {
++ if (cap_gain16_shutter > (cap_bandfilt*cap_maxband*16)) {
++ /* exposure reach max */
++ cap_shutter = cap_bandfilt*cap_maxband;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ } else {
++ /* 1/100 < cap_shutter =< max, cap_shutter = n/100 */
++ cap_shutter =
++ ((int)(cap_gain16_shutter/16/cap_bandfilt))
++ * cap_bandfilt;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ }
++ }
++
++ /* write capture gain */
++ ov5640_set_gain16(cap_gain16);
++
++ /* write capture shutter */
++ if (cap_shutter > (cap_VTS - 4)) {
++ cap_VTS = cap_shutter + 4;
++ ov5640_set_VTS(cap_VTS);
++ }
++
++ ov5640_set_shutter(cap_shutter);
++
++ /* skip 2 vysnc: start capture at 3rd vsync
++ * frame rate of QSXGA and 1080P is 7.5fps: 1/7.5 * 2
++ */
++ pr_warning("ov5640: the actual frame rate of %s is 7.5fps\n",
++ mode == ov5640_mode_1080P_1920_1080 ? "1080P" : "QSXGA");
++ msleep(267);
++err:
++ return retval;
++}
++
++static int ov5640_change_mode(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ int retval = 0;
++
++ if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) {
++ pr_err("Wrong ov5640 mode detected!\n");
++ return -1;
++ }
++
++ if (mode == ov5640_mode_1080P_1920_1080 ||
++ mode == ov5640_mode_QSXGA_2592_1944) {
++ /* change to scaling mode go through exposure calucation
++ * image size above 1280 * 960 is scaling mode */
++ retval = ov5640_change_mode_exposure_calc(frame_rate, mode);
++ } else {
++ /* change back to subsampling modem download firmware directly
++ * image size below 1280 * 960 is subsampling mode */
++ retval = ov5640_change_mode_direct(frame_rate, mode);
++ }
++
++ return retval;
++}
++
++/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
++
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ memset(p, 0, sizeof(*p));
++ p->u.bt656.clock_curr = ov5640_data.mclk;
++ pr_debug(" clock_curr=mclk=%d\n", ov5640_data.mclk);
++ p->if_type = V4L2_IF_TYPE_BT656;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.clock_min = OV5640_XCLK_MIN;
++ p->u.bt656.clock_max = OV5640_XCLK_MAX;
++ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor_data *sensor = s->priv;
++
++ if (on && !sensor->on) {
++ if (io_regulator)
++ if (regulator_enable(io_regulator) != 0)
++ return -EIO;
++ if (core_regulator)
++ if (regulator_enable(core_regulator) != 0)
++ return -EIO;
++ if (analog_regulator)
++ if (regulator_enable(analog_regulator) != 0)
++ return -EIO;
++ /* Make sure power on */
++ ov5640_power_down(0);
++ } else if (!on && sensor->on) {
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++ if (core_regulator)
++ regulator_disable(core_regulator);
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ ov5640_power_down(1);
++}
++
++ sensor->on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5640_frame_rate frame_rate;
++ int ret = 0;
++
++ /* Make sure power on */
++ ov5640_power_down(0);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ return -EINVAL;
++ }
++
++ ret = ov5640_change_mode(frame_rate,
++ a->parm.capture.capturemode);
++ if (ret < 0)
++ return ret;
++
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.capturemode = a->parm.capture.capturemode;
++
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor_data *sensor = s->priv;
++
++ f->fmt.pix = sensor->pix;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ vc->value = ov5640_data.brightness;
++ break;
++ case V4L2_CID_HUE:
++ vc->value = ov5640_data.hue;
++ break;
++ case V4L2_CID_CONTRAST:
++ vc->value = ov5640_data.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ vc->value = ov5640_data.saturation;
++ break;
++ case V4L2_CID_RED_BALANCE:
++ vc->value = ov5640_data.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ vc->value = ov5640_data.blue;
++ break;
++ case V4L2_CID_EXPOSURE:
++ vc->value = ov5640_data.ae_mode;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++
++ pr_debug("In ov5640:ioctl_s_ctrl %d\n",
++ vc->id);
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ break;
++ case V4L2_CID_CONTRAST:
++ break;
++ case V4L2_CID_SATURATION:
++ break;
++ case V4L2_CID_HUE:
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_RED_BALANCE:
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ break;
++ case V4L2_CID_GAMMA:
++ break;
++ case V4L2_CID_EXPOSURE:
++ break;
++ case V4L2_CID_AUTOGAIN:
++ break;
++ case V4L2_CID_GAIN:
++ break;
++ case V4L2_CID_HFLIP:
++ break;
++ case V4L2_CID_VFLIP:
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fsize->pixel_format = ov5640_data.pix.pixelformat;
++ fsize->discrete.width =
++ max(ov5640_mode_info_data[0][fsize->index].width,
++ ov5640_mode_info_data[1][fsize->index].width);
++ fsize->discrete.height =
++ max(ov5640_mode_info_data[0][fsize->index].height,
++ ov5640_mode_info_data[1][fsize->index].height);
++ return 0;
++}
++
++/*!
++ * ioctl_enum_frameintervals - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMEINTERVALS ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_frameintervals(struct v4l2_int_device *s,
++ struct v4l2_frmivalenum *fival)
++{
++ int i, j, count;
++
++ if (fival->index < 0 || fival->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ if (fival->width == 0 || fival->height == 0 ||
++ fival->pixel_format == 0) {
++ pr_warning("Please assign pixelformat, width and height.\n");
++ return -EINVAL;
++ }
++
++ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++ fival->discrete.numerator = 1;
++
++ count = 0;
++ for (i = 0; i < ARRAY_SIZE(ov5640_mode_info_data); i++) {
++ for (j = 0; j < (ov5640_mode_MAX + 1); j++) {
++ if (fival->pixel_format == ov5640_data.pix.pixelformat
++ && fival->width == ov5640_mode_info_data[i][j].width
++ && fival->height == ov5640_mode_info_data[i][j].height
++ && ov5640_mode_info_data[i][j].init_data_ptr != NULL) {
++ count++;
++ }
++ if (fival->index == (count - 1)) {
++ fival->discrete.denominator =
++ ov5640_framerates[i];
++ return 0;
++ }
++ }
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov5640_camera");
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
++ * @s: pointer to standard V4L2 device structure
++ * @fmt: pointer to standard V4L2 fmt description structure
++ *
++ * Return 0.
++ */
++static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fmt->pixelformat = ov5640_data.pix.pixelformat;
++
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ struct sensor_data *sensor = s->priv;
++ u32 tgt_xclk; /* target xclk */
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5640_frame_rate frame_rate;
++ int ret;
++
++ ov5640_data.on = true;
++
++ /* mclk */
++ tgt_xclk = ov5640_data.mclk;
++ tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX);
++ tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN);
++ ov5640_data.mclk = tgt_xclk;
++
++ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000);
++ clk_set_rate(ov5640_data.sensor_clk, ov5640_data.mclk);
++
++ /* Default camera frame rate is set in probe */
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else
++ return -EINVAL; /* Only support 15fps or 30fps now. */
++
++ ret = ov5640_init_mode();
++ return ret;
++}
++
++/*!
++ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Delinitialise the device when slave detaches to the master.
++ */
++static int ioctl_dev_exit(struct v4l2_int_device *s)
++{
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module and links them to the
++ * enumeration.
++ */
++static struct v4l2_int_ioctl_desc ov5640_ioctl_desc[] = {
++ { vidioc_int_dev_init_num,
++ (v4l2_int_ioctl_func *)ioctl_dev_init },
++ { vidioc_int_dev_exit_num,
++ ioctl_dev_exit},
++ { vidioc_int_s_power_num,
++ (v4l2_int_ioctl_func *)ioctl_s_power },
++ { vidioc_int_g_ifparm_num,
++ (v4l2_int_ioctl_func *)ioctl_g_ifparm },
++ { vidioc_int_init_num,
++ (v4l2_int_ioctl_func *)ioctl_init },
++ { vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap },
++ { vidioc_int_g_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_g_fmt_cap },
++ { vidioc_int_g_parm_num,
++ (v4l2_int_ioctl_func *)ioctl_g_parm },
++ { vidioc_int_s_parm_num,
++ (v4l2_int_ioctl_func *)ioctl_s_parm },
++ { vidioc_int_g_ctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_g_ctrl },
++ { vidioc_int_s_ctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_s_ctrl },
++ { vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_framesizes },
++ { vidioc_int_enum_frameintervals_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_frameintervals },
++ { vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *)ioctl_g_chip_ident },
++};
++
++static struct v4l2_int_slave ov5640_slave = {
++ .ioctls = ov5640_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(ov5640_ioctl_desc),
++};
++
++static struct v4l2_int_device ov5640_int_device = {
++ .module = THIS_MODULE,
++ .name = "ov5640",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &ov5640_slave,
++ },
++};
++
++/*!
++ * ov5640 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct pinctrl *pinctrl;
++ struct device *dev = &client->dev;
++ int retval;
++ u8 chip_id_high, chip_id_low;
++
++ /* ov5640 pinctrl */
++ pinctrl = devm_pinctrl_get_select_default(dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(dev, "setup pinctrl failed\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_err(dev, "no sensor pwdn pin available\n");
++ return -ENODEV;
++ }
++ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_pwdn");
++ if (retval < 0)
++ return retval;
++
++ /* request reset pin */
++ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
++ if (!gpio_is_valid(rst_gpio)) {
++ dev_err(dev, "no sensor reset pin available\n");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_reset");
++ if (retval < 0)
++ return retval;
++
++ /* Set initial values for the sensor struct. */
++ memset(&ov5640_data, 0, sizeof(ov5640_data));
++ ov5640_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(ov5640_data.sensor_clk)) {
++ dev_err(dev, "get mclk failed\n");
++ return PTR_ERR(ov5640_data.sensor_clk);
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ &ov5640_data.mclk);
++ if (retval) {
++ dev_err(dev, "mclk frequency is invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(ov5640_data.mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(ov5640_data.csi));
++ if (retval) {
++ dev_err(dev, "csi_id invalid\n");
++ return retval;
++ }
++
++ clk_prepare_enable(ov5640_data.sensor_clk);
++
++ ov5640_data.io_init = ov5640_reset;
++ ov5640_data.i2c_client = client;
++ ov5640_data.pix.pixelformat = V4L2_PIX_FMT_YUYV;
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++ ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ ov5640_data.streamcap.capturemode = 0;
++ ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
++ ov5640_data.streamcap.timeperframe.numerator = 1;
++
++ ov5640_regulator_enable(&client->dev);
++
++ ov5640_reset();
++
++ ov5640_power_down(0);
++
++ retval = ov5640_read_reg(OV5640_CHIP_ID_HIGH_BYTE, &chip_id_high);
++ if (retval < 0 || chip_id_high != 0x56) {
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ pr_warning("camera ov5640 is not found\n");
++ return -ENODEV;
++ }
++ retval = ov5640_read_reg(OV5640_CHIP_ID_LOW_BYTE, &chip_id_low);
++ if (retval < 0 || chip_id_low != 0x40) {
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ pr_warning("camera ov5640 is not found\n");
++ return -ENODEV;
++ }
++
++ ov5640_power_down(1);
++
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++
++ ov5640_int_device.priv = &ov5640_data;
++ retval = v4l2_int_device_register(&ov5640_int_device);
++
++ pr_info("camera ov5640 is found\n");
++ return retval;
++}
++
++/*!
++ * ov5640 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_remove(struct i2c_client *client)
++{
++ v4l2_int_device_unregister(&ov5640_int_device);
++
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++
++ if (core_regulator)
++ regulator_disable(core_regulator);
++
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ return 0;
++}
++
++module_i2c_driver(ov5640_i2c_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("OV5640 Camera Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ov5640_mipi.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ov5640_mipi.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ov5640_mipi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ov5640_mipi.c 2014-05-15 20:33:57.138007668 +0200
+@@ -0,0 +1,2104 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/of_device.h>
++#include <linux/i2c.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/fsl_devices.h>
++#include <linux/mipi_csi2.h>
++#include <media/v4l2-chip-ident.h>
++#include <media/v4l2-int-device.h>
++#include "mxc_v4l2_capture.h"
++
++#define OV5640_VOLTAGE_ANALOG 2800000
++#define OV5640_VOLTAGE_DIGITAL_CORE 1500000
++#define OV5640_VOLTAGE_DIGITAL_IO 1800000
++
++#define MIN_FPS 15
++#define MAX_FPS 30
++#define DEFAULT_FPS 30
++
++#define OV5640_XCLK_MIN 6000000
++#define OV5640_XCLK_MAX 24000000
++
++#define OV5640_CHIP_ID_HIGH_BYTE 0x300A
++#define OV5640_CHIP_ID_LOW_BYTE 0x300B
++
++enum ov5640_mode {
++ ov5640_mode_MIN = 0,
++ ov5640_mode_VGA_640_480 = 0,
++ ov5640_mode_QVGA_320_240 = 1,
++ ov5640_mode_NTSC_720_480 = 2,
++ ov5640_mode_PAL_720_576 = 3,
++ ov5640_mode_720P_1280_720 = 4,
++ ov5640_mode_1080P_1920_1080 = 5,
++ ov5640_mode_QSXGA_2592_1944 = 6,
++ ov5640_mode_QCIF_176_144 = 7,
++ ov5640_mode_XGA_1024_768 = 8,
++ ov5640_mode_MAX = 8,
++ ov5640_mode_INIT = 0xff, /*only for sensor init*/
++};
++
++enum ov5640_frame_rate {
++ ov5640_15_fps,
++ ov5640_30_fps
++};
++
++/* image size under 1280 * 960 are SUBSAMPLING
++ * image size upper 1280 * 960 are SCALING
++ */
++enum ov5640_downsize_mode {
++ SUBSAMPLING,
++ SCALING,
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u8 u8Val;
++ u8 u8Mask;
++ u32 u32Delay_ms;
++};
++
++struct ov5640_mode_info {
++ enum ov5640_mode mode;
++ enum ov5640_downsize_mode dn_mode;
++ u32 width;
++ u32 height;
++ struct reg_value *init_data_ptr;
++ u32 init_data_size;
++};
++
++/*!
++ * Maintains the information on the current state of the sesor.
++ */
++static struct sensor_data ov5640_data;
++static int pwn_gpio, rst_gpio;
++
++static struct reg_value ov5640_init_setting_30fps_VGA[] = {
++
++ {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0},
++ {0x3103, 0x03, 0, 0}, {0x3017, 0x00, 0, 0}, {0x3018, 0x00, 0, 0},
++ {0x3034, 0x18, 0, 0}, {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0},
++ {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x36, 0, 0},
++ {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
++ {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
++ {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
++ {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
++ {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
++ {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
++ {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
++ {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
++ {0x3c01, 0xa4, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
++ {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x300e, 0x45, 0, 0}, {0x302e, 0x08, 0, 0}, {0x4300, 0x3f, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x4837, 0x0a, 0, 0}, {0x4800, 0x04, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0},
++ {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0},
++ {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0},
++ {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0},
++ {0x518a, 0x54, 0, 0}, {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0},
++ {0x518d, 0x50, 0, 0}, {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0},
++ {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0},
++ {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0},
++ {0x5199, 0x6c, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0},
++ {0x519c, 0x09, 0, 0}, {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0},
++ {0x5381, 0x1e, 0, 0}, {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0},
++ {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0},
++ {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0},
++ {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0},
++ {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0},
++ {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0},
++ {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0},
++ {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0},
++ {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0},
++ {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0},
++ {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0},
++ {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0},
++ {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0},
++ {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0},
++ {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0},
++ {0x5802, 0x0f, 0, 0}, {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0},
++ {0x5805, 0x26, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0},
++ {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0},
++ {0x580b, 0x0d, 0, 0}, {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0},
++ {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0},
++ {0x5811, 0x09, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0},
++ {0x5814, 0x00, 0, 0}, {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0},
++ {0x5817, 0x08, 0, 0}, {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0},
++ {0x581a, 0x05, 0, 0}, {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0},
++ {0x581d, 0x0e, 0, 0}, {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0},
++ {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0},
++ {0x5823, 0x28, 0, 0}, {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0},
++ {0x5826, 0x08, 0, 0}, {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0},
++ {0x5829, 0x26, 0, 0}, {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0},
++ {0x582c, 0x24, 0, 0}, {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0},
++ {0x582f, 0x22, 0, 0}, {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0},
++ {0x5832, 0x24, 0, 0}, {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0},
++ {0x5835, 0x22, 0, 0}, {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0},
++ {0x5838, 0x44, 0, 0}, {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0},
++ {0x583b, 0x28, 0, 0}, {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0},
++ {0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0},
++ {0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0},
++ {0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300},
++};
++
++static struct reg_value ov5640_setting_30fps_VGA_640_480[] = {
++
++ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x04, 0, 0}, {0x380f, 0x38, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_VGA_640_480[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = {
++
++ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x04, 0, 0}, {0x380f, 0x38, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0},
++ {0x380b, 0x00, 0, 0}, {0x3035, 0x12, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3808, 0x04, 0, 0},
++ {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = {
++ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = {
++ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = {
++ {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_PAL_720_576[] = {
++ {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_PAL_720_576[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_720P_1280_720[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0},
++ {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
++ {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
++ {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, {0x4005, 0x1a, 0, 0},
++ {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_720P_1280_720[] = {
++ {0x3035, 0x41, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0},
++ {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
++ {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
++ {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0},
++ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
++ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0},
++ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
++ {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
++ {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, {0x3808, 0x07, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0},
++ {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, {0x380e, 0x04, 0, 0},
++ {0x380f, 0x60, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
++ {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
++ {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
++ {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
++ {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0},
++ {0x3503, 0, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0},
++ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
++ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0},
++ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x54, 0, 1}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
++ {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
++ {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, {0x3808, 0x07, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0},
++ {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, {0x380e, 0x04, 0, 0},
++ {0x380f, 0x60, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
++ {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
++ {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
++ {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
++ {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = {
++ {0x4202, 0x0f, 0, 0}, /* stream off the sensor */
++ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, /*disable flip*/
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0},
++ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
++ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0},
++ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70},
++ {0x4202, 0x00, 0, 0}, /* stream on the sensor */
++};
++
++static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = {
++ {
++ {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480,
++ ov5640_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240,
++ ov5640_setting_15fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480,
++ ov5640_setting_15fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576,
++ ov5640_setting_15fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720,
++ ov5640_setting_15fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, SCALING, 1920, 1080,
++ ov5640_setting_15fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)},
++ {ov5640_mode_QSXGA_2592_1944, SCALING, 2592, 1944,
++ ov5640_setting_15fps_QSXGA_2592_1944,
++ ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)},
++ {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144,
++ ov5640_setting_15fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768,
++ ov5640_setting_15fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)},
++ },
++ {
++ {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480,
++ ov5640_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240,
++ ov5640_setting_30fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480,
++ ov5640_setting_30fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576,
++ ov5640_setting_30fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720,
++ ov5640_setting_30fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, SCALING, 1920, 1080,
++ ov5640_setting_30fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5640_setting_30fps_1080P_1920_1080)},
++ {ov5640_mode_QSXGA_2592_1944, -1, 0, 0, NULL, 0},
++ {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144,
++ ov5640_setting_30fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768,
++ ov5640_setting_30fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)},
++ },
++};
++
++static struct regulator *io_regulator;
++static struct regulator *core_regulator;
++static struct regulator *analog_regulator;
++static struct regulator *gpo_regulator;
++
++static int ov5640_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int ov5640_remove(struct i2c_client *client);
++
++static s32 ov5640_read_reg(u16 reg, u8 *val);
++static s32 ov5640_write_reg(u16 reg, u8 val);
++
++static const struct i2c_device_id ov5640_id[] = {
++ {"ov5640_mipi", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, ov5640_id);
++
++static struct i2c_driver ov5640_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ov5640_mipi",
++ },
++ .probe = ov5640_probe,
++ .remove = ov5640_remove,
++ .id_table = ov5640_id,
++};
++
++static void ov5640_standby(s32 enable)
++{
++ if (enable)
++ gpio_set_value(pwn_gpio, 1);
++ else
++ gpio_set_value(pwn_gpio, 0);
++
++ msleep(2);
++}
++
++static void ov5640_reset(void)
++{
++ /* camera reset */
++ gpio_set_value(rst_gpio, 1);
++
++ /* camera power dowmn */
++ gpio_set_value(pwn_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, 0);
++ msleep(5);
++
++ gpio_set_value(rst_gpio, 0);
++ msleep(1);
++
++ gpio_set_value(rst_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, 1);
++}
++
++static int ov5640_power_on(struct device *dev)
++{
++ int ret = 0;
++
++ io_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(io_regulator)) {
++ regulator_set_voltage(io_regulator,
++ OV5640_VOLTAGE_DIGITAL_IO,
++ OV5640_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(io_regulator);
++ if (ret) {
++ pr_err("%s:io set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:io set voltage ok\n", __func__);
++ }
++ } else {
++ pr_err("%s: cannot get io voltage error\n", __func__);
++ io_regulator = NULL;
++ }
++
++ core_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(core_regulator)) {
++ regulator_set_voltage(core_regulator,
++ OV5640_VOLTAGE_DIGITAL_CORE,
++ OV5640_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(core_regulator);
++ if (ret) {
++ pr_err("%s:core set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:core set voltage ok\n", __func__);
++ }
++ } else {
++ core_regulator = NULL;
++ pr_err("%s: cannot get core voltage error\n", __func__);
++ }
++
++ analog_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(analog_regulator)) {
++ regulator_set_voltage(analog_regulator,
++ OV5640_VOLTAGE_ANALOG,
++ OV5640_VOLTAGE_ANALOG);
++ ret = regulator_enable(analog_regulator);
++ if (ret) {
++ pr_err("%s:analog set voltage error\n",
++ __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:analog set voltage ok\n", __func__);
++ }
++ } else {
++ analog_regulator = NULL;
++ pr_err("%s: cannot get analog voltage error\n", __func__);
++ }
++
++ return ret;
++}
++
++static s32 ov5640_write_reg(u16 reg, u8 val)
++{
++ u8 au8Buf[3] = {0};
++
++ au8Buf[0] = reg >> 8;
++ au8Buf[1] = reg & 0xff;
++ au8Buf[2] = val;
++
++ if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, val);
++ return -1;
++ }
++
++ return 0;
++}
++
++static s32 ov5640_read_reg(u16 reg, u8 *val)
++{
++ u8 au8RegBuf[2] = {0};
++ u8 u8RdVal = 0;
++
++ au8RegBuf[0] = reg >> 8;
++ au8RegBuf[1] = reg & 0xff;
++
++ if (2 != i2c_master_send(ov5640_data.i2c_client, au8RegBuf, 2)) {
++ pr_err("%s:write reg error:reg=%x\n",
++ __func__, reg);
++ return -1;
++ }
++
++ if (1 != i2c_master_recv(ov5640_data.i2c_client, &u8RdVal, 1)) {
++ pr_err("%s:read reg error:reg=%x,val=%x\n",
++ __func__, reg, u8RdVal);
++ return -1;
++ }
++
++ *val = u8RdVal;
++
++ return u8RdVal;
++}
++
++static int prev_sysclk, prev_HTS;
++static int AE_low, AE_high, AE_Target = 52;
++
++void OV5640_stream_on(void)
++{
++ ov5640_write_reg(0x4202, 0x00);
++}
++
++void OV5640_stream_off(void)
++{
++ ov5640_write_reg(0x4202, 0x0f);
++}
++
++
++int OV5640_get_sysclk(void)
++{
++ /* calculate sysclk */
++ int xvclk = ov5640_data.mclk / 10000;
++ int temp1, temp2;
++ int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv;
++ int Bit_div2x = 1, sclk_rdiv, sysclk;
++ u8 temp;
++
++ int sclk_rdiv_map[] = {1, 2, 4, 8};
++
++ temp1 = ov5640_read_reg(0x3034, &temp);
++ temp2 = temp1 & 0x0f;
++ if (temp2 == 8 || temp2 == 10)
++ Bit_div2x = temp2 / 2;
++
++ temp1 = ov5640_read_reg(0x3035, &temp);
++ SysDiv = temp1>>4;
++ if (SysDiv == 0)
++ SysDiv = 16;
++
++ temp1 = ov5640_read_reg(0x3036, &temp);
++ Multiplier = temp1;
++
++ temp1 = ov5640_read_reg(0x3037, &temp);
++ PreDiv = temp1 & 0x0f;
++ Pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
++
++ temp1 = ov5640_read_reg(0x3108, &temp);
++ temp2 = temp1 & 0x03;
++ sclk_rdiv = sclk_rdiv_map[temp2];
++
++ VCO = xvclk * Multiplier / PreDiv;
++
++ sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv;
++
++ return sysclk;
++}
++
++void OV5640_set_night_mode(void)
++{
++ /* read HTS from register settings */
++ u8 mode;
++
++ ov5640_read_reg(0x3a00, &mode);
++ mode &= 0xfb;
++ ov5640_write_reg(0x3a00, mode);
++}
++
++int OV5640_get_HTS(void)
++{
++ /* read HTS from register settings */
++ int HTS;
++ u8 temp;
++
++ HTS = ov5640_read_reg(0x380c, &temp);
++ HTS = (HTS<<8) + ov5640_read_reg(0x380d, &temp);
++
++ return HTS;
++}
++
++int OV5640_get_VTS(void)
++{
++ /* read VTS from register settings */
++ int VTS;
++ u8 temp;
++
++ /* total vertical size[15:8] high byte */
++ VTS = ov5640_read_reg(0x380e, &temp);
++
++ VTS = (VTS<<8) + ov5640_read_reg(0x380f, &temp);
++
++ return VTS;
++}
++
++int OV5640_set_VTS(int VTS)
++{
++ /* write VTS to registers */
++ int temp;
++
++ temp = VTS & 0xff;
++ ov5640_write_reg(0x380f, temp);
++
++ temp = VTS>>8;
++ ov5640_write_reg(0x380e, temp);
++
++ return 0;
++}
++
++int OV5640_get_shutter(void)
++{
++ /* read shutter, in number of line period */
++ int shutter;
++ u8 temp;
++
++ shutter = (ov5640_read_reg(0x03500, &temp) & 0x0f);
++ shutter = (shutter<<8) + ov5640_read_reg(0x3501, &temp);
++ shutter = (shutter<<4) + (ov5640_read_reg(0x3502, &temp)>>4);
++
++ return shutter;
++}
++
++int OV5640_set_shutter(int shutter)
++{
++ /* write shutter, in number of line period */
++ int temp;
++
++ shutter = shutter & 0xffff;
++
++ temp = shutter & 0x0f;
++ temp = temp<<4;
++ ov5640_write_reg(0x3502, temp);
++
++ temp = shutter & 0xfff;
++ temp = temp>>4;
++ ov5640_write_reg(0x3501, temp);
++
++ temp = shutter>>12;
++ ov5640_write_reg(0x3500, temp);
++
++ return 0;
++}
++
++int OV5640_get_gain16(void)
++{
++ /* read gain, 16 = 1x */
++ int gain16;
++ u8 temp;
++
++ gain16 = ov5640_read_reg(0x350a, &temp) & 0x03;
++ gain16 = (gain16<<8) + ov5640_read_reg(0x350b, &temp);
++
++ return gain16;
++}
++
++int OV5640_set_gain16(int gain16)
++{
++ /* write gain, 16 = 1x */
++ u8 temp;
++ gain16 = gain16 & 0x3ff;
++
++ temp = gain16 & 0xff;
++ ov5640_write_reg(0x350b, temp);
++
++ temp = gain16>>8;
++ ov5640_write_reg(0x350a, temp);
++
++ return 0;
++}
++
++int OV5640_get_light_freq(void)
++{
++ /* get banding filter value */
++ int temp, temp1, light_freq = 0;
++ u8 tmp;
++
++ temp = ov5640_read_reg(0x3c01, &tmp);
++
++ if (temp & 0x80) {
++ /* manual */
++ temp1 = ov5640_read_reg(0x3c00, &tmp);
++ if (temp1 & 0x04) {
++ /* 50Hz */
++ light_freq = 50;
++ } else {
++ /* 60Hz */
++ light_freq = 60;
++ }
++ } else {
++ /* auto */
++ temp1 = ov5640_read_reg(0x3c0c, &tmp);
++ if (temp1 & 0x01) {
++ /* 50Hz */
++ light_freq = 50;
++ } else {
++ /* 60Hz */
++ }
++ }
++ return light_freq;
++}
++
++void OV5640_set_bandingfilter(void)
++{
++ int prev_VTS;
++ int band_step60, max_band60, band_step50, max_band50;
++
++ /* read preview PCLK */
++ prev_sysclk = OV5640_get_sysclk();
++ /* read preview HTS */
++ prev_HTS = OV5640_get_HTS();
++
++ /* read preview VTS */
++ prev_VTS = OV5640_get_VTS();
++
++ /* calculate banding filter */
++ /* 60Hz */
++ band_step60 = prev_sysclk * 100/prev_HTS * 100/120;
++ ov5640_write_reg(0x3a0a, (band_step60 >> 8));
++ ov5640_write_reg(0x3a0b, (band_step60 & 0xff));
++
++ max_band60 = (int)((prev_VTS-4)/band_step60);
++ ov5640_write_reg(0x3a0d, max_band60);
++
++ /* 50Hz */
++ band_step50 = prev_sysclk * 100/prev_HTS;
++ ov5640_write_reg(0x3a08, (band_step50 >> 8));
++ ov5640_write_reg(0x3a09, (band_step50 & 0xff));
++
++ max_band50 = (int)((prev_VTS-4)/band_step50);
++ ov5640_write_reg(0x3a0e, max_band50);
++}
++
++int OV5640_set_AE_target(int target)
++{
++ /* stable in high */
++ int fast_high, fast_low;
++ AE_low = target * 23 / 25; /* 0.92 */
++ AE_high = target * 27 / 25; /* 1.08 */
++
++ fast_high = AE_high<<1;
++ if (fast_high > 255)
++ fast_high = 255;
++
++ fast_low = AE_low >> 1;
++
++ ov5640_write_reg(0x3a0f, AE_high);
++ ov5640_write_reg(0x3a10, AE_low);
++ ov5640_write_reg(0x3a1b, AE_high);
++ ov5640_write_reg(0x3a1e, AE_low);
++ ov5640_write_reg(0x3a11, fast_high);
++ ov5640_write_reg(0x3a1f, fast_low);
++
++ return 0;
++}
++
++void OV5640_turn_on_AE_AG(int enable)
++{
++ u8 ae_ag_ctrl;
++
++ ov5640_read_reg(0x3503, &ae_ag_ctrl);
++ if (enable) {
++ /* turn on auto AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl & ~(0x03);
++ } else {
++ /* turn off AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl | 0x03;
++ }
++ ov5640_write_reg(0x3503, ae_ag_ctrl);
++}
++
++bool binning_on(void)
++{
++ u8 temp;
++ ov5640_read_reg(0x3821, &temp);
++ temp &= 0xfe;
++ if (temp)
++ return true;
++ else
++ return false;
++}
++
++static void ov5640_set_virtual_channel(int channel)
++{
++ u8 channel_id;
++
++ ov5640_read_reg(0x4814, &channel_id);
++ channel_id &= ~(3 << 6);
++ ov5640_write_reg(0x4814, channel_id | (channel << 6));
++}
++
++/* download ov5640 settings to sensor through i2c */
++static int ov5640_download_firmware(struct reg_value *pModeSetting, s32 ArySize)
++{
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int i, retval = 0;
++
++ for (i = 0; i < ArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5640_read_reg(RegAddr, &RegVal);
++ if (retval < 0)
++ goto err;
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5640_write_reg(RegAddr, Val);
++ if (retval < 0)
++ goto err;
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++/* sensor changes between scaling and subsampling
++ * go through exposure calcualtion
++ */
++static int ov5640_change_mode_exposure_calc(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ u8 average;
++ int prev_shutter, prev_gain16;
++ int cap_shutter, cap_gain16;
++ int cap_sysclk, cap_HTS, cap_VTS;
++ int light_freq, cap_bandfilt, cap_maxband;
++ long cap_gain16_shutter;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width =
++ ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height =
++ ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* auto focus */
++ /* OV5640_auto_focus();//if no af function, just skip it */
++
++ /* turn off AE/AG */
++ OV5640_turn_on_AE_AG(0);
++
++ /* read preview shutter */
++ prev_shutter = OV5640_get_shutter();
++ if ((binning_on()) && (mode != ov5640_mode_720P_1280_720)
++ && (mode != ov5640_mode_1080P_1920_1080))
++ prev_shutter *= 2;
++
++ /* read preview gain */
++ prev_gain16 = OV5640_get_gain16();
++
++ /* get average */
++ ov5640_read_reg(0x56a1, &average);
++
++ /* turn off night mode for capture */
++ OV5640_set_night_mode();
++
++ /* turn off overlay */
++ /* ov5640_write_reg(0x3022, 0x06);//if no af function, just skip it */
++
++ OV5640_stream_off();
++
++ /* Write capture setting */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* read capture VTS */
++ cap_VTS = OV5640_get_VTS();
++ cap_HTS = OV5640_get_HTS();
++ cap_sysclk = OV5640_get_sysclk();
++
++ /* calculate capture banding filter */
++ light_freq = OV5640_get_light_freq();
++ if (light_freq == 60) {
++ /* 60Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120;
++ } else {
++ /* 50Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS;
++ }
++ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt);
++
++ /* calculate capture shutter/gain16 */
++ if (average > AE_low && average < AE_high) {
++ /* in stable range */
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk
++ * prev_HTS/cap_HTS * AE_Target / average;
++ } else {
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk
++ * prev_HTS/cap_HTS;
++ }
++
++ /* gain to shutter */
++ if (cap_gain16_shutter < (cap_bandfilt * 16)) {
++ /* shutter < 1/100 */
++ cap_shutter = cap_gain16_shutter/16;
++ if (cap_shutter < 1)
++ cap_shutter = 1;
++
++ cap_gain16 = cap_gain16_shutter/cap_shutter;
++ if (cap_gain16 < 16)
++ cap_gain16 = 16;
++ } else {
++ if (cap_gain16_shutter >
++ (cap_bandfilt * cap_maxband * 16)) {
++ /* exposure reach max */
++ cap_shutter = cap_bandfilt * cap_maxband;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ } else {
++ /* 1/100 < (cap_shutter = n/100) =< max */
++ cap_shutter =
++ ((int) (cap_gain16_shutter/16 / cap_bandfilt))
++ *cap_bandfilt;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ }
++ }
++
++ /* write capture gain */
++ OV5640_set_gain16(cap_gain16);
++
++ /* write capture shutter */
++ if (cap_shutter > (cap_VTS - 4)) {
++ cap_VTS = cap_shutter + 4;
++ OV5640_set_VTS(cap_VTS);
++ }
++ OV5640_set_shutter(cap_shutter);
++
++ OV5640_stream_on();
++
++err:
++ return retval;
++}
++
++/* if sensor changes inside scaling or subsampling
++ * change mode directly
++ * */
++static int ov5640_change_mode_direct(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width =
++ ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height =
++ ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* turn off AE/AG */
++ OV5640_turn_on_AE_AG(0);
++
++ OV5640_stream_off();
++
++ /* Write capture setting */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ OV5640_stream_on();
++
++ OV5640_turn_on_AE_AG(1);
++
++err:
++ return retval;
++}
++
++static int ov5640_init_mode(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode, enum ov5640_mode orig_mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++ void *mipi_csi2_info;
++ u32 mipi_reg, msec_wait4stable = 0;
++ enum ov5640_downsize_mode dn_mode, orig_dn_mode;
++
++ if ((mode > ov5640_mode_MAX || mode < ov5640_mode_MIN)
++ && (mode != ov5640_mode_INIT)) {
++ pr_err("Wrong ov5640 mode detected!\n");
++ return -1;
++ }
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* initial mipi dphy */
++ if (!mipi_csi2_info) {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -1;
++ }
++
++ if (!mipi_csi2_get_status(mipi_csi2_info))
++ mipi_csi2_enable(mipi_csi2_info);
++
++ if (!mipi_csi2_get_status(mipi_csi2_info)) {
++ pr_err("Can not enable mipi csi2 driver!\n");
++ return -1;
++ }
++
++ mipi_csi2_set_lanes(mipi_csi2_info);
++
++ /*Only reset MIPI CSI2 HW at sensor initialize*/
++ if (mode == ov5640_mode_INIT)
++ mipi_csi2_reset(mipi_csi2_info);
++
++ if (ov5640_data.pix.pixelformat == V4L2_PIX_FMT_UYVY)
++ mipi_csi2_set_datatype(mipi_csi2_info, MIPI_DT_YUV422);
++ else if (ov5640_data.pix.pixelformat == V4L2_PIX_FMT_RGB565)
++ mipi_csi2_set_datatype(mipi_csi2_info, MIPI_DT_RGB565);
++ else
++ pr_err("currently this sensor format can not be supported!\n");
++
++ dn_mode = ov5640_mode_info_data[frame_rate][mode].dn_mode;
++ orig_dn_mode = ov5640_mode_info_data[frame_rate][orig_mode].dn_mode;
++ if (mode == ov5640_mode_INIT) {
++ pModeSetting = ov5640_init_setting_30fps_VGA;
++ ArySize = ARRAY_SIZE(ov5640_init_setting_30fps_VGA);
++
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ pModeSetting = ov5640_setting_30fps_VGA_640_480;
++ ArySize = ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480);
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ } else if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) ||
++ (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) {
++ /* change between subsampling and scaling
++ * go through exposure calucation */
++ retval = ov5640_change_mode_exposure_calc(frame_rate, mode);
++ } else {
++ /* change inside subsampling or scaling
++ * download firmware directly */
++ retval = ov5640_change_mode_direct(frame_rate, mode);
++ }
++
++ if (retval < 0)
++ goto err;
++
++ OV5640_set_AE_target(AE_Target);
++ OV5640_get_light_freq();
++ OV5640_set_bandingfilter();
++ ov5640_set_virtual_channel(ov5640_data.csi);
++
++ /* add delay to wait for sensor stable */
++ if (mode == ov5640_mode_QSXGA_2592_1944) {
++ /* dump the first two frames: 1/7.5*2
++ * the frame rate of QSXGA is 7.5fps */
++ msec_wait4stable = 267;
++ } else if (frame_rate == ov5640_15_fps) {
++ /* dump the first nine frames: 1/15*9 */
++ msec_wait4stable = 600;
++ } else if (frame_rate == ov5640_30_fps) {
++ /* dump the first nine frames: 1/30*9 */
++ msec_wait4stable = 300;
++ }
++ msleep(msec_wait4stable);
++
++ if (mipi_csi2_info) {
++ unsigned int i;
++
++ i = 0;
++
++ /* wait for mipi sensor ready */
++ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
++ while ((mipi_reg == 0x200) && (i < 10)) {
++ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
++ i++;
++ msleep(10);
++ }
++
++ if (i >= 10) {
++ pr_err("mipi csi2 can not receive sensor clk!\n");
++ return -1;
++ }
++
++ i = 0;
++
++ /* wait for mipi stable */
++ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
++ while ((mipi_reg != 0x0) && (i < 10)) {
++ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
++ i++;
++ msleep(10);
++ }
++
++ if (i >= 10) {
++ pr_err("mipi csi2 can not reveive data correctly!\n");
++ return -1;
++ }
++ }
++err:
++ return retval;
++}
++
++/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
++
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ memset(p, 0, sizeof(*p));
++ p->u.bt656.clock_curr = ov5640_data.mclk;
++ pr_debug(" clock_curr=mclk=%d\n", ov5640_data.mclk);
++ p->if_type = V4L2_IF_TYPE_BT656;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.clock_min = OV5640_XCLK_MIN;
++ p->u.bt656.clock_max = OV5640_XCLK_MAX;
++ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor_data *sensor = s->priv;
++
++ if (on && !sensor->on) {
++ if (io_regulator)
++ if (regulator_enable(io_regulator) != 0)
++ return -EIO;
++ if (core_regulator)
++ if (regulator_enable(core_regulator) != 0)
++ return -EIO;
++ if (gpo_regulator)
++ if (regulator_enable(gpo_regulator) != 0)
++ return -EIO;
++ if (analog_regulator)
++ if (regulator_enable(analog_regulator) != 0)
++ return -EIO;
++ /* Make sure power on */
++ ov5640_standby(0);
++ } else if (!on && sensor->on) {
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++ if (core_regulator)
++ regulator_disable(core_regulator);
++ if (io_regulator)
++ regulator_disable(io_regulator);
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ ov5640_standby(1);
++ }
++
++ sensor->on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5640_frame_rate frame_rate;
++ enum ov5640_mode orig_mode;
++ int ret = 0;
++
++ /* Make sure power on */
++ ov5640_standby(0);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ return -EINVAL;
++ }
++
++ orig_mode = sensor->streamcap.capturemode;
++ ret = ov5640_init_mode(frame_rate,
++ (u32)a->parm.capture.capturemode, orig_mode);
++ if (ret < 0)
++ return ret;
++
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.capturemode =
++ (u32)a->parm.capture.capturemode;
++
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor_data *sensor = s->priv;
++
++ f->fmt.pix = sensor->pix;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ vc->value = ov5640_data.brightness;
++ break;
++ case V4L2_CID_HUE:
++ vc->value = ov5640_data.hue;
++ break;
++ case V4L2_CID_CONTRAST:
++ vc->value = ov5640_data.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ vc->value = ov5640_data.saturation;
++ break;
++ case V4L2_CID_RED_BALANCE:
++ vc->value = ov5640_data.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ vc->value = ov5640_data.blue;
++ break;
++ case V4L2_CID_EXPOSURE:
++ vc->value = ov5640_data.ae_mode;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++
++ pr_debug("In ov5640:ioctl_s_ctrl %d\n",
++ vc->id);
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ break;
++ case V4L2_CID_CONTRAST:
++ break;
++ case V4L2_CID_SATURATION:
++ break;
++ case V4L2_CID_HUE:
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_RED_BALANCE:
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ break;
++ case V4L2_CID_GAMMA:
++ break;
++ case V4L2_CID_EXPOSURE:
++ break;
++ case V4L2_CID_AUTOGAIN:
++ break;
++ case V4L2_CID_GAIN:
++ break;
++ case V4L2_CID_HFLIP:
++ break;
++ case V4L2_CID_VFLIP:
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fsize->pixel_format = ov5640_data.pix.pixelformat;
++ fsize->discrete.width =
++ max(ov5640_mode_info_data[0][fsize->index].width,
++ ov5640_mode_info_data[1][fsize->index].width);
++ fsize->discrete.height =
++ max(ov5640_mode_info_data[0][fsize->index].height,
++ ov5640_mode_info_data[1][fsize->index].height);
++ return 0;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
++ "ov5640_mipi_camera");
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
++ * @s: pointer to standard V4L2 device structure
++ * @fmt: pointer to standard V4L2 fmt description structure
++ *
++ * Return 0.
++ */
++static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fmt->pixelformat = ov5640_data.pix.pixelformat;
++
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ struct sensor_data *sensor = s->priv;
++ u32 tgt_xclk; /* target xclk */
++ u32 tgt_fps; /* target frames per secound */
++ int ret;
++ enum ov5640_frame_rate frame_rate;
++ void *mipi_csi2_info;
++
++ ov5640_data.on = true;
++
++ /* mclk */
++ tgt_xclk = ov5640_data.mclk;
++ tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX);
++ tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN);
++ ov5640_data.mclk = tgt_xclk;
++
++ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000);
++
++ /* Default camera frame rate is set in probe */
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else
++ return -EINVAL; /* Only support 15fps or 30fps now. */
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* enable mipi csi2 */
++ if (mipi_csi2_info)
++ mipi_csi2_enable(mipi_csi2_info);
++ else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++
++ ret = ov5640_init_mode(frame_rate, ov5640_mode_INIT, ov5640_mode_INIT);
++
++ return ret;
++}
++
++/*!
++ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Delinitialise the device when slave detaches to the master.
++ */
++static int ioctl_dev_exit(struct v4l2_int_device *s)
++{
++ void *mipi_csi2_info;
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* disable mipi csi2 */
++ if (mipi_csi2_info)
++ if (mipi_csi2_get_status(mipi_csi2_info))
++ mipi_csi2_disable(mipi_csi2_info);
++
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module and links them to the
++ * enumeration.
++ */
++static struct v4l2_int_ioctl_desc ov5640_ioctl_desc[] = {
++ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *) ioctl_dev_init},
++ {vidioc_int_dev_exit_num, ioctl_dev_exit},
++ {vidioc_int_s_power_num, (v4l2_int_ioctl_func *) ioctl_s_power},
++ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *) ioctl_g_ifparm},
++/* {vidioc_int_g_needs_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
++/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
++ {vidioc_int_init_num, (v4l2_int_ioctl_func *) ioctl_init},
++ {vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap},
++/* {vidioc_int_try_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
++ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap},
++/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_s_fmt_cap}, */
++ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm},
++ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm},
++/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */
++ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl},
++ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl},
++ {vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
++ {vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *) ioctl_g_chip_ident},
++};
++
++static struct v4l2_int_slave ov5640_slave = {
++ .ioctls = ov5640_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(ov5640_ioctl_desc),
++};
++
++static struct v4l2_int_device ov5640_int_device = {
++ .module = THIS_MODULE,
++ .name = "ov5640",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &ov5640_slave,
++ },
++};
++
++/*!
++ * ov5640 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct device *dev = &client->dev;
++ int retval;
++ u8 chip_id_high, chip_id_low;
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_warn(dev, "no sensor pwdn pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_mipi_pwdn");
++ if (retval < 0)
++ return retval;
++
++ /* request reset pin */
++ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
++ if (!gpio_is_valid(rst_gpio)) {
++ dev_warn(dev, "no sensor reset pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_mipi_reset");
++ if (retval < 0)
++ return retval;
++
++ /* Set initial values for the sensor struct. */
++ memset(&ov5640_data, 0, sizeof(ov5640_data));
++ ov5640_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(ov5640_data.sensor_clk)) {
++ /* assuming clock enabled by default */
++ ov5640_data.sensor_clk = NULL;
++ dev_err(dev, "clock-frequency missing or invalid\n");
++ return PTR_ERR(ov5640_data.sensor_clk);
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ &(ov5640_data.mclk));
++ if (retval) {
++ dev_err(dev, "mclk missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(ov5640_data.mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(ov5640_data.csi));
++ if (retval) {
++ dev_err(dev, "csi id missing or invalid\n");
++ return retval;
++ }
++
++ clk_prepare_enable(ov5640_data.sensor_clk);
++
++ ov5640_data.io_init = ov5640_reset;
++ ov5640_data.i2c_client = client;
++ ov5640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY;
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++ ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ ov5640_data.streamcap.capturemode = 0;
++ ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
++ ov5640_data.streamcap.timeperframe.numerator = 1;
++
++ ov5640_power_on(dev);
++
++ ov5640_reset();
++
++ ov5640_standby(0);
++
++ retval = ov5640_read_reg(OV5640_CHIP_ID_HIGH_BYTE, &chip_id_high);
++ if (retval < 0 || chip_id_high != 0x56) {
++ pr_warning("camera ov5640_mipi is not found\n");
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ return -ENODEV;
++ }
++ retval = ov5640_read_reg(OV5640_CHIP_ID_LOW_BYTE, &chip_id_low);
++ if (retval < 0 || chip_id_low != 0x40) {
++ pr_warning("camera ov5640_mipi is not found\n");
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ return -ENODEV;
++ }
++
++ ov5640_standby(1);
++
++ ov5640_int_device.priv = &ov5640_data;
++ retval = v4l2_int_device_register(&ov5640_int_device);
++
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++
++ pr_info("camera ov5640_mipi is found\n");
++ return retval;
++}
++
++/*!
++ * ov5640 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_remove(struct i2c_client *client)
++{
++ v4l2_int_device_unregister(&ov5640_int_device);
++
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++
++ if (core_regulator)
++ regulator_disable(core_regulator);
++
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ return 0;
++}
++
++/*!
++ * ov5640 init function
++ * Called by insmod ov5640_camera.ko.
++ *
++ * @return Error code indicating success or failure
++ */
++static __init int ov5640_init(void)
++{
++ u8 err;
++
++ err = i2c_add_driver(&ov5640_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d\n",
++ __func__, err);
++
++ return err;
++}
++
++/*!
++ * OV5640 cleanup function
++ * Called on rmmod ov5640_camera.ko
++ *
++ * @return Error code indicating success or failure
++ */
++static void __exit ov5640_clean(void)
++{
++ i2c_del_driver(&ov5640_i2c_driver);
++}
++
++module_init(ov5640_init);
++module_exit(ov5640_clean);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("OV5640 MIPI Camera Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/capture/ov5642.c linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ov5642.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/capture/ov5642.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/capture/ov5642.c 2014-05-15 20:33:57.138007668 +0200
+@@ -0,0 +1,4252 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/of_device.h>
++#include <linux/i2c.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/fsl_devices.h>
++#include <media/v4l2-chip-ident.h>
++#include <media/v4l2-int-device.h>
++#include "mxc_v4l2_capture.h"
++
++#define OV5642_VOLTAGE_ANALOG 2800000
++#define OV5642_VOLTAGE_DIGITAL_CORE 1500000
++#define OV5642_VOLTAGE_DIGITAL_IO 1800000
++
++#define MIN_FPS 15
++#define MAX_FPS 30
++#define DEFAULT_FPS 30
++
++#define OV5642_XCLK_MIN 6000000
++#define OV5642_XCLK_MAX 24000000
++
++#define OV5642_CHIP_ID_HIGH_BYTE 0x300A
++#define OV5642_CHIP_ID_LOW_BYTE 0x300B
++
++enum ov5642_mode {
++ ov5642_mode_MIN = 0,
++ ov5642_mode_VGA_640_480 = 0,
++ ov5642_mode_QVGA_320_240 = 1,
++ ov5642_mode_NTSC_720_480 = 2,
++ ov5642_mode_PAL_720_576 = 3,
++ ov5642_mode_720P_1280_720 = 4,
++ ov5642_mode_1080P_1920_1080 = 5,
++ ov5642_mode_QSXGA_2592_1944 = 6,
++ ov5642_mode_QCIF_176_144 = 7,
++ ov5642_mode_XGA_1024_768 = 8,
++ ov5642_mode_MAX = 8
++};
++
++enum ov5642_frame_rate {
++ ov5642_15_fps,
++ ov5642_30_fps
++};
++
++static int ov5642_framerates[] = {
++ [ov5642_15_fps] = 15,
++ [ov5642_30_fps] = 30,
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u8 u8Val;
++ u8 u8Mask;
++ u32 u32Delay_ms;
++};
++
++struct ov5642_mode_info {
++ enum ov5642_mode mode;
++ u32 width;
++ u32 height;
++ struct reg_value *init_data_ptr;
++ u32 init_data_size;
++};
++
++/*!
++ * Maintains the information on the current state of the sesor.
++ */
++static struct sensor_data ov5642_data;
++static int pwn_gpio, rst_gpio;
++
++static struct reg_value ov5642_rot_none_VGA[] = {
++ {0x3818, 0xc1, 0x00, 0x00}, {0x3621, 0x87, 0x00, 0x00},
++};
++
++static struct reg_value ov5642_rot_vert_flip_VGA[] = {
++ {0x3818, 0x20, 0xbf, 0x00}, {0x3621, 0x20, 0xff, 0x00},
++};
++
++static struct reg_value ov5642_rot_horiz_flip_VGA[] = {
++ {0x3818, 0x81, 0x00, 0x01}, {0x3621, 0xa7, 0x00, 0x00},
++};
++
++static struct reg_value ov5642_rot_180_VGA[] = {
++ {0x3818, 0x60, 0xff, 0x00}, {0x3621, 0x00, 0xdf, 0x00},
++};
++
++
++static struct reg_value ov5642_rot_none_FULL[] = {
++ {0x3818, 0xc0, 0x00, 0x00}, {0x3621, 0x09, 0x00, 0x00},
++};
++
++static struct reg_value ov5642_rot_vert_flip_FULL[] = {
++ {0x3818, 0x20, 0xbf, 0x01}, {0x3621, 0x20, 0xff, 0x00},
++};
++
++static struct reg_value ov5642_rot_horiz_flip_FULL[] = {
++ {0x3818, 0x80, 0x00, 0x01}, {0x3621, 0x29, 0x00, 0x00},
++};
++
++static struct reg_value ov5642_rot_180_FULL[] = {
++ {0x3818, 0x60, 0xff, 0x00}, {0x3621, 0x00, 0xdf, 0x00},
++};
++
++
++static struct reg_value ov5642_initial_setting[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c00, 0x04, 0, 0}, {0x3c01, 0x80, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0},
++ {0x5182, 0x00, 0, 0}, {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5001, 0xff, 0, 0}, {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0},
++ {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0},
++ {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0},
++ {0x350b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x0b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 300},
++};
++
++static struct reg_value ov5642_setting_15fps_QCIF_176_144[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0x90, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_QCIF_176_144[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x10, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0x90, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_QSXGA_2592_1944[] = {
++ {0x3503, 0x07, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0},
++ {0x3002, 0x00, 0, 0}, {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0},
++ {0x3005, 0xff, 0, 0}, {0x3006, 0xff, 0, 0}, {0x3007, 0x3f, 0, 0},
++ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3818, 0xc0, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3602, 0xe4, 0, 0}, {0x3612, 0xac, 0, 0}, {0x3613, 0x44, 0, 0},
++ {0x3622, 0x60, 0, 0}, {0x3623, 0x22, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3705, 0xda, 0, 0}, {0x370a, 0x80, 0, 0}, {0x3801, 0x95, 0, 0},
++ {0x3803, 0x0e, 0, 0}, {0x3804, 0x0a, 0, 0}, {0x3805, 0x20, 0, 0},
++ {0x3806, 0x07, 0, 0}, {0x3807, 0x98, 0, 0}, {0x3808, 0x0a, 0, 0},
++ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3815, 0x44, 0, 0},
++ {0x3824, 0x11, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0},
++ {0x3a00, 0x78, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0},
++ {0x5682, 0x0a, 0, 0}, {0x5683, 0x20, 0, 0}, {0x5686, 0x07, 0, 0},
++ {0x5687, 0x98, 0, 0}, {0x5001, 0xff, 0, 0}, {0x589b, 0x00, 0, 0},
++ {0x589a, 0xc0, 0, 0}, {0x4407, 0x04, 0, 0}, {0x3008, 0x02, 0, 0},
++ {0x460b, 0x37, 0, 0}, {0x460c, 0x22, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x471c, 0xd0, 0, 0}, {0x3815, 0x01, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3819, 0x80, 0, 0},
++ {0x5002, 0xe0, 0, 0}, {0x530a, 0x01, 0, 0}, {0x530d, 0x10, 0, 0},
++ {0x530c, 0x04, 0, 0}, {0x5312, 0x20, 0, 0}, {0x5282, 0x01, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x3012, 0x00, 0, 0},
++};
++
++
++static struct reg_value ov5642_setting_VGA_2_QVGA[] = {
++ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0xf0, 0, 0}, {0x3815, 0x04, 0, 0},
++};
++
++static struct reg_value ov5642_setting_QSXGA_2_VGA[] = {
++ {0x3503, 0x00, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0},
++ {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0},
++ {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x3818, 0xc1, 0, 0}, {0x3621, 0x87, 0, 0},
++ {0x350c, 0x03, 0, 0}, {0x350d, 0xe8, 0, 0}, {0x3602, 0xfc, 0, 0},
++ {0x3612, 0xff, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3622, 0x60, 0, 0},
++ {0x3623, 0x01, 0, 0}, {0x3604, 0x48, 0, 0}, {0x3705, 0xdb, 0, 0},
++ {0x370a, 0x81, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x3806, 0x03, 0, 0},
++ {0x3807, 0xc0, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3810, 0x40, 0, 0}, {0x3815, 0x04, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3825, 0xb4, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0},
++ {0x5001, 0xff, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x4407, 0x0c, 0, 0}, {0x3008, 0x02, 0, 0}, {0x460b, 0x37, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x471d, 0x05, 0, 0}, {0x4713, 0x02, 0, 0},
++ {0x471c, 0xd0, 0, 0}, {0x3815, 0x04, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x3002, 0x5c, 0, 0}, {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0},
++ {0x530a, 0x01, 0, 0}, {0x530d, 0x0c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x5312, 0x40, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x3012, 0x02, 0, 0}, {0x3010, 0x00, 0, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_VGA_640_480[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_VGA_640_480[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++
++static struct reg_value ov5642_setting_30fps_XGA_1024_768[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0},
++ {0x380b, 0x00, 0, 0}, {0x3815, 0x02, 0, 0}, {0x302c, 0x60, 0x60, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_XGA_1024_768[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0},
++ {0x380b, 0x00, 0, 0}, {0x3815, 0x02, 0, 0}, {0x302c, 0x60, 0x60, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_QVGA_320_240[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3808, 0x01, 0, 0},
++ {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_NTSC_720_480[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x3c, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0x58, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0x58, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x302c, 0x60, 0x60, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_PAL_720_576[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xd8, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x3c, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x04, 0, 0}, {0x3805, 0xb0, 0, 0}, {0x5682, 0x04, 0, 0},
++ {0x5683, 0xb0, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0x58, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0x58, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x302c, 0x60, 0x60, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_720P_1280_720[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0},
++ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0},
++ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0},
++ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0},
++ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0},
++ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0},
++ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0},
++ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0},
++ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0},
++ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0},
++ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0},
++ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0},
++ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0},
++ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0},
++ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0},
++ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x350c, 0x02, 0, 0}, {0x350d, 0xe4, 0, 0}, {0x3621, 0xc9, 0, 0},
++ {0x370a, 0x81, 0, 0}, {0x3803, 0x08, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x3806, 0x02, 0, 0}, {0x3807, 0xd0, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x08, 0, 0}, {0x380d, 0x72, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0xc0, 0, 0},
++ {0x3818, 0xc9, 0, 0}, {0x381c, 0x10, 0, 0}, {0x381d, 0xa0, 0, 0},
++ {0x381e, 0x05, 0, 0}, {0x381f, 0xb0, 0, 0}, {0x3820, 0x00, 0, 0},
++ {0x3821, 0x00, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3a08, 0x1b, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x17, 0, 0}, {0x3a0b, 0x20, 0, 0},
++ {0x3a0d, 0x02, 0, 0}, {0x3a0e, 0x01, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, {0x5686, 0x02, 0, 0},
++ {0x5687, 0xcc, 0, 0}, {0x5001, 0x7f, 0, 0}, {0x589b, 0x06, 0, 0},
++ {0x589a, 0xc5, 0, 0}, {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0},
++ {0x501f, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0},
++ {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0}, {0x3010, 0x30, 0, 0},
++ {0x3a08, 0x06, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x05, 0, 0},
++ {0x3a0b, 0x50, 0, 0}, {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x07, 0, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_720P_1280_720[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0},
++ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0},
++ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0},
++ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0},
++ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0},
++ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0},
++ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0},
++ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0},
++ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0},
++ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0},
++ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0},
++ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0},
++ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0},
++ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0},
++ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0},
++ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x350c, 0x02, 0, 0}, {0x350d, 0xe4, 0, 0}, {0x3621, 0xc9, 0, 0},
++ {0x370a, 0x81, 0, 0}, {0x3803, 0x08, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x3806, 0x02, 0, 0}, {0x3807, 0xd0, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x08, 0, 0}, {0x380d, 0x72, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0xc0, 0, 0},
++ {0x3818, 0xc9, 0, 0}, {0x381c, 0x10, 0, 0}, {0x381d, 0xa0, 0, 0},
++ {0x381e, 0x05, 0, 0}, {0x381f, 0xb0, 0, 0}, {0x3820, 0x00, 0, 0},
++ {0x3821, 0x00, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3a08, 0x1b, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x17, 0, 0}, {0x3a0b, 0x20, 0, 0},
++ {0x3a0d, 0x02, 0, 0}, {0x3a0e, 0x01, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, {0x5686, 0x02, 0, 0},
++ {0x5687, 0xcc, 0, 0}, {0x5001, 0x7f, 0, 0}, {0x589b, 0x06, 0, 0},
++ {0x589a, 0xc5, 0, 0}, {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0},
++ {0x501f, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0},
++ {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_1080P_1920_1080[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0},
++ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0},
++ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0},
++ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0},
++ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0},
++ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0},
++ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0},
++ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0},
++ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0},
++ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0},
++ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0},
++ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0},
++ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0},
++ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0},
++ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0},
++ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x07, 0, 0},
++ {0x350c, 0x04, 0, 0}, {0x350d, 0x58, 0, 0}, {0x3801, 0x8a, 0, 0},
++ {0x3803, 0x0a, 0, 0}, {0x3804, 0x07, 0, 0}, {0x3805, 0x80, 0, 0},
++ {0x3806, 0x04, 0, 0}, {0x3807, 0x39, 0, 0}, {0x3808, 0x07, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0},
++ {0x380c, 0x09, 0, 0}, {0x380d, 0xd6, 0, 0}, {0x380e, 0x04, 0, 0},
++ {0x380f, 0x58, 0, 0}, {0x381c, 0x11, 0, 0}, {0x381d, 0xba, 0, 0},
++ {0x381e, 0x04, 0, 0}, {0x381f, 0x48, 0, 0}, {0x3820, 0x04, 0, 0},
++ {0x3821, 0x18, 0, 0}, {0x3a08, 0x14, 0, 0}, {0x3a09, 0xe0, 0, 0},
++ {0x3a0a, 0x11, 0, 0}, {0x3a0b, 0x60, 0, 0}, {0x3a0d, 0x04, 0, 0},
++ {0x3a0e, 0x03, 0, 0}, {0x5682, 0x07, 0, 0}, {0x5683, 0x60, 0, 0},
++ {0x5686, 0x04, 0, 0}, {0x5687, 0x1c, 0, 0}, {0x5001, 0x7f, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0}, {0x501f, 0x00, 0, 0},
++ {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3819, 0x80, 0, 0},
++ {0x5002, 0xe0, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_QVGA_320_240[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0xf0, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_NTSC_720_480[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3824, 0x11, 0, 0}, {0x3825, 0xb4, 0, 0}, {0x3826, 0x00, 0, 0},
++ {0x3827, 0x3d, 0, 0}, {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0xd0, 0, 0}, {0x380A, 0x01, 0, 0}, {0x380B, 0xe0, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x3806, 0x03, 0, 0},
++ {0x3807, 0x55, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0x55, 0, 0},
++ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_PAL_720_576[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3824, 0x11, 0, 0}, {0x3825, 0xdc, 0, 0}, {0x3826, 0x00, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0xd0, 0, 0}, {0x380A, 0x02, 0, 0}, {0x380B, 0x40, 0, 0},
++ {0x3804, 0x04, 0, 0}, {0x3805, 0xb0, 0, 0}, {0x3806, 0x03, 0, 0},
++ {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0xc0, 0, 0},
++ {0x5682, 0x04, 0, 0}, {0x5683, 0xb0, 0, 0},
++};
++
++static struct ov5642_mode_info ov5642_mode_info_data[2][ov5642_mode_MAX + 1] = {
++ {
++ {ov5642_mode_VGA_640_480, 640, 480,
++ ov5642_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5642_setting_15fps_VGA_640_480)},
++ {ov5642_mode_QVGA_320_240, 320, 240,
++ ov5642_setting_15fps_QVGA_320_240,
++ ARRAY_SIZE(ov5642_setting_15fps_QVGA_320_240)},
++ {ov5642_mode_NTSC_720_480, 720, 480,
++ ov5642_setting_15fps_NTSC_720_480,
++ ARRAY_SIZE(ov5642_setting_15fps_NTSC_720_480)},
++ {ov5642_mode_PAL_720_576, 720, 576,
++ ov5642_setting_15fps_PAL_720_576,
++ ARRAY_SIZE(ov5642_setting_15fps_PAL_720_576)},
++ {ov5642_mode_720P_1280_720, 1280, 720,
++ ov5642_setting_15fps_720P_1280_720,
++ ARRAY_SIZE(ov5642_setting_15fps_720P_1280_720)},
++ {ov5642_mode_1080P_1920_1080, 1920, 1080,
++ ov5642_setting_15fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5642_setting_15fps_1080P_1920_1080)},
++ {ov5642_mode_QSXGA_2592_1944, 2592, 1944,
++ ov5642_setting_15fps_QSXGA_2592_1944,
++ ARRAY_SIZE(ov5642_setting_15fps_QSXGA_2592_1944)},
++ {ov5642_mode_QCIF_176_144, 176, 144,
++ ov5642_setting_15fps_QCIF_176_144,
++ ARRAY_SIZE(ov5642_setting_15fps_QCIF_176_144)},
++ {ov5642_mode_XGA_1024_768, 1024, 768,
++ ov5642_setting_15fps_XGA_1024_768,
++ ARRAY_SIZE(ov5642_setting_15fps_XGA_1024_768)},
++ },
++ {
++ {ov5642_mode_VGA_640_480, 640, 480,
++ ov5642_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5642_setting_30fps_VGA_640_480)},
++ {ov5642_mode_QVGA_320_240, 320, 240,
++ ov5642_setting_30fps_QVGA_320_240,
++ ARRAY_SIZE(ov5642_setting_30fps_QVGA_320_240)},
++ {ov5642_mode_NTSC_720_480, 720, 480,
++ ov5642_setting_30fps_NTSC_720_480,
++ ARRAY_SIZE(ov5642_setting_30fps_NTSC_720_480)},
++ {ov5642_mode_PAL_720_576, 720, 576,
++ ov5642_setting_30fps_PAL_720_576,
++ ARRAY_SIZE(ov5642_setting_30fps_PAL_720_576)},
++ {ov5642_mode_720P_1280_720, 1280, 720,
++ ov5642_setting_30fps_720P_1280_720,
++ ARRAY_SIZE(ov5642_setting_30fps_720P_1280_720)},
++ {ov5642_mode_1080P_1920_1080, 0, 0, NULL, 0},
++ {ov5642_mode_QSXGA_2592_1944, 0, 0, NULL, 0},
++ {ov5642_mode_QCIF_176_144, 176, 144,
++ ov5642_setting_30fps_QCIF_176_144,
++ ARRAY_SIZE(ov5642_setting_30fps_QCIF_176_144)},
++ {ov5642_mode_XGA_1024_768, 1024, 768,
++ ov5642_setting_30fps_XGA_1024_768,
++ ARRAY_SIZE(ov5642_setting_30fps_XGA_1024_768)},
++ },
++};
++
++static struct regulator *io_regulator;
++static struct regulator *core_regulator;
++static struct regulator *analog_regulator;
++static struct regulator *gpo_regulator;
++
++static int ov5642_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int ov5642_remove(struct i2c_client *client);
++
++static s32 ov5642_read_reg(u16 reg, u8 *val);
++static s32 ov5642_write_reg(u16 reg, u8 val);
++
++static const struct i2c_device_id ov5642_id[] = {
++ {"ov5642", 0},
++ {"ov564x", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, ov5642_id);
++
++static struct i2c_driver ov5642_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ov5642",
++ },
++ .probe = ov5642_probe,
++ .remove = ov5642_remove,
++ .id_table = ov5642_id,
++};
++
++static void ov5642_standby(s32 enable)
++{
++ if (enable)
++ gpio_set_value(pwn_gpio, 1);
++ else
++ gpio_set_value(pwn_gpio, 0);
++
++ msleep(2);
++}
++
++static void ov5642_reset(void)
++{
++ /* camera reset */
++ gpio_set_value(rst_gpio, 1);
++
++ /* camera power down */
++ gpio_set_value(pwn_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, 0);
++ msleep(5);
++
++ gpio_set_value(rst_gpio, 0);
++ msleep(1);
++
++ gpio_set_value(rst_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, 1);
++}
++
++static int ov5642_power_on(struct device *dev)
++{
++ int ret = 0;
++
++ io_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(io_regulator)) {
++ regulator_set_voltage(io_regulator,
++ OV5642_VOLTAGE_DIGITAL_IO,
++ OV5642_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(io_regulator);
++ if (ret) {
++ pr_err("%s:io set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:io set voltage ok\n", __func__);
++ }
++ } else {
++ pr_err("%s: cannot get io voltage error\n", __func__);
++ io_regulator = NULL;
++ }
++
++ core_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(core_regulator)) {
++ regulator_set_voltage(core_regulator,
++ OV5642_VOLTAGE_DIGITAL_CORE,
++ OV5642_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(core_regulator);
++ if (ret) {
++ pr_err("%s:core set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:core set voltage ok\n", __func__);
++ }
++ } else {
++ core_regulator = NULL;
++ pr_err("%s: cannot get core voltage error\n", __func__);
++ }
++
++ analog_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(analog_regulator)) {
++ regulator_set_voltage(analog_regulator,
++ OV5642_VOLTAGE_ANALOG,
++ OV5642_VOLTAGE_ANALOG);
++ ret = regulator_enable(analog_regulator);
++ if (ret) {
++ pr_err("%s:analog set voltage error\n",
++ __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:analog set voltage ok\n", __func__);
++ }
++ } else {
++ analog_regulator = NULL;
++ pr_err("%s: cannot get analog voltage error\n", __func__);
++ }
++
++ return ret;
++}
++
++static s32 ov5642_write_reg(u16 reg, u8 val)
++{
++ u8 au8Buf[3] = {0};
++
++ au8Buf[0] = reg >> 8;
++ au8Buf[1] = reg & 0xff;
++ au8Buf[2] = val;
++
++ if (i2c_master_send(ov5642_data.i2c_client, au8Buf, 3) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, val);
++ return -1;
++ }
++
++ return 0;
++}
++
++static s32 ov5642_read_reg(u16 reg, u8 *val)
++{
++ u8 au8RegBuf[2] = {0};
++ u8 u8RdVal = 0;
++
++ au8RegBuf[0] = reg >> 8;
++ au8RegBuf[1] = reg & 0xff;
++
++ if (2 != i2c_master_send(ov5642_data.i2c_client, au8RegBuf, 2)) {
++ pr_err("%s:write reg error:reg=%x\n",
++ __func__, reg);
++ return -1;
++ }
++
++ if (1 != i2c_master_recv(ov5642_data.i2c_client, &u8RdVal, 1)) {
++ pr_err("%s:read reg error:reg=%x,val=%x\n",
++ __func__, reg, u8RdVal);
++ return -1;
++ }
++
++ *val = u8RdVal;
++
++ return u8RdVal;
++}
++
++static int ov5642_set_rot_mode(struct reg_value *rot_mode)
++{
++ s32 i = 0;
++ s32 iModeSettingArySize = 2;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++ for (i = 0; i < iModeSettingArySize; ++i, ++rot_mode) {
++ Delay_ms = rot_mode->u32Delay_ms;
++ RegAddr = rot_mode->u16RegAddr;
++ Val = rot_mode->u8Val;
++ Mask = rot_mode->u8Mask;
++
++ if (Mask) {
++ retval = ov5642_read_reg(RegAddr, &RegVal);
++ if (retval < 0) {
++ pr_err("%s, read reg 0x%x failed\n",
++ __func__, RegAddr);
++ goto err;
++ }
++
++ Val |= RegVal;
++ Val &= Mask;
++ }
++
++ retval = ov5642_write_reg(RegAddr, Val);
++ if (retval < 0) {
++ pr_err("%s, write reg 0x%x failed\n",
++ __func__, RegAddr);
++ goto err;
++ }
++
++ if (Delay_ms)
++ mdelay(Delay_ms);
++ }
++err:
++ return retval;
++}
++static int ov5642_init_mode(enum ov5642_frame_rate frame_rate,
++ enum ov5642_mode mode);
++static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
++ enum ov5642_mode mode);
++static int ov5642_change_mode(enum ov5642_frame_rate new_frame_rate,
++ enum ov5642_frame_rate old_frame_rate,
++ enum ov5642_mode new_mode,
++ enum ov5642_mode orig_mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 i = 0;
++ s32 iModeSettingArySize = 0;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++
++ if (new_mode > ov5642_mode_MAX || new_mode < ov5642_mode_MIN) {
++ pr_err("Wrong ov5642 mode detected!\n");
++ return -1;
++ }
++
++ if ((new_frame_rate == old_frame_rate) &&
++ (new_mode == ov5642_mode_VGA_640_480) &&
++ (orig_mode == ov5642_mode_QSXGA_2592_1944)) {
++ pModeSetting = ov5642_setting_QSXGA_2_VGA;
++ iModeSettingArySize = ARRAY_SIZE(ov5642_setting_QSXGA_2_VGA);
++ ov5642_data.pix.width = 640;
++ ov5642_data.pix.height = 480;
++ } else if ((new_frame_rate == old_frame_rate) &&
++ (new_mode == ov5642_mode_QVGA_320_240) &&
++ (orig_mode == ov5642_mode_VGA_640_480)) {
++ pModeSetting = ov5642_setting_VGA_2_QVGA;
++ iModeSettingArySize = ARRAY_SIZE(ov5642_setting_VGA_2_QVGA);
++ ov5642_data.pix.width = 320;
++ ov5642_data.pix.height = 240;
++ } else {
++ retval = ov5642_write_snapshot_para(new_frame_rate, new_mode);
++ goto err;
++ }
++
++ if (ov5642_data.pix.width == 0 || ov5642_data.pix.height == 0 ||
++ pModeSetting == NULL || iModeSettingArySize == 0)
++ return -EINVAL;
++
++ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5642_read_reg(RegAddr, &RegVal);
++ if (retval < 0) {
++ pr_err("read reg error addr=0x%x", RegAddr);
++ goto err;
++ }
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5642_write_reg(RegAddr, Val);
++ if (retval < 0) {
++ pr_err("write reg error addr=0x%x", RegAddr);
++ goto err;
++ }
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++static int ov5642_init_mode(enum ov5642_frame_rate frame_rate,
++ enum ov5642_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 i = 0;
++ s32 iModeSettingArySize = 0;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++
++ if (mode > ov5642_mode_MAX || mode < ov5642_mode_MIN) {
++ pr_err("Wrong ov5642 mode detected!\n");
++ return -1;
++ }
++
++ pModeSetting = ov5642_mode_info_data[frame_rate][mode].init_data_ptr;
++ iModeSettingArySize =
++ ov5642_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5642_data.pix.width = ov5642_mode_info_data[frame_rate][mode].width;
++ ov5642_data.pix.height = ov5642_mode_info_data[frame_rate][mode].height;
++
++ if (ov5642_data.pix.width == 0 || ov5642_data.pix.height == 0 ||
++ pModeSetting == NULL || iModeSettingArySize == 0)
++ return -EINVAL;
++
++ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5642_read_reg(RegAddr, &RegVal);
++ if (retval < 0) {
++ pr_err("read reg error addr=0x%x", RegAddr);
++ goto err;
++ }
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5642_write_reg(RegAddr, Val);
++ if (retval < 0) {
++ pr_err("write reg error addr=0x%x", RegAddr);
++ goto err;
++ }
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
++ enum ov5642_mode mode)
++{
++ int ret = 0;
++ bool m_60Hz = false;
++ u16 cap_frame_rate = 50;
++ u16 g_prev_frame_rate = 225;
++
++ u8 ev_low, ev_mid, ev_high;
++ u8 ret_l, ret_m, ret_h, gain, lines_10ms;
++ u16 ulcap_ev, icap_gain, prev_maxlines;
++ u32 ulcap_ev_gain, cap_maxlines, g_prev_ev;
++
++ ov5642_write_reg(0x3503, 0x07);
++
++ ret_h = ret_m = ret_l = 0;
++ g_prev_ev = 0;
++ ov5642_read_reg(0x3500, &ret_h);
++ ov5642_read_reg(0x3501, &ret_m);
++ ov5642_read_reg(0x3502, &ret_l);
++ g_prev_ev = (ret_h << 12) + (ret_m << 4) + (ret_l >> 4);
++
++ ret_h = ret_m = ret_l = 0;
++ prev_maxlines = 0;
++ ov5642_read_reg(0x380e, &ret_h);
++ ov5642_read_reg(0x380f, &ret_l);
++ prev_maxlines = (ret_h << 8) + ret_l;
++ /*Read back AGC Gain for preview*/
++ gain = 0;
++ ov5642_read_reg(0x350b, &gain);
++
++ ret = ov5642_init_mode(frame_rate, mode);
++ if (ret < 0)
++ return ret;
++
++ ret_h = ret_m = ret_l = 0;
++ ov5642_read_reg(0x380e, &ret_h);
++ ov5642_read_reg(0x380f, &ret_l);
++ cap_maxlines = (ret_h << 8) + ret_l;
++ if (m_60Hz == true)
++ lines_10ms = cap_frame_rate * cap_maxlines/12000;
++ else
++ lines_10ms = cap_frame_rate * cap_maxlines/10000;
++
++ if (prev_maxlines == 0)
++ prev_maxlines = 1;
++
++ ulcap_ev = (g_prev_ev*(cap_frame_rate)*(cap_maxlines))/
++ (((prev_maxlines)*(g_prev_frame_rate)));
++ icap_gain = (gain & 0x0f) + 16;
++ if (gain & 0x10)
++ icap_gain = icap_gain << 1;
++
++ if (gain & 0x20)
++ icap_gain = icap_gain << 1;
++
++ if (gain & 0x40)
++ icap_gain = icap_gain << 1;
++
++ if (gain & 0x80)
++ icap_gain = icap_gain << 1;
++
++ ulcap_ev_gain = 2 * ulcap_ev * icap_gain;
++
++ if (ulcap_ev_gain < cap_maxlines*16) {
++ ulcap_ev = ulcap_ev_gain/16;
++ if (ulcap_ev > lines_10ms) {
++ ulcap_ev /= lines_10ms;
++ ulcap_ev *= lines_10ms;
++ }
++ } else
++ ulcap_ev = cap_maxlines;
++
++ if (ulcap_ev == 0)
++ ulcap_ev = 1;
++
++ icap_gain = (ulcap_ev_gain*2/ulcap_ev + 1)/2;
++ ev_low = ((unsigned char)ulcap_ev)<<4;
++ ev_mid = (unsigned char)(ulcap_ev >> 4) & 0xff;
++ ev_high = (unsigned char)(ulcap_ev >> 12);
++
++ gain = 0;
++ if (icap_gain > 31) {
++ gain |= 0x10;
++ icap_gain = icap_gain >> 1;
++ }
++ if (icap_gain > 31) {
++ gain |= 0x20;
++ icap_gain = icap_gain >> 1;
++ }
++ if (icap_gain > 31) {
++ gain |= 0x40;
++ icap_gain = icap_gain >> 1;
++ }
++ if (icap_gain > 31) {
++ gain |= 0x80;
++ icap_gain = icap_gain >> 1;
++ }
++ if (icap_gain > 16)
++ gain |= ((icap_gain - 16) & 0x0f);
++
++ if (gain == 0x10)
++ gain = 0x11;
++
++ ov5642_write_reg(0x350b, gain);
++ ov5642_write_reg(0x3502, ev_low);
++ ov5642_write_reg(0x3501, ev_mid);
++ ov5642_write_reg(0x3500, ev_high);
++ msleep(500);
++
++ return ret ;
++}
++
++
++/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
++
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ memset(p, 0, sizeof(*p));
++ p->u.bt656.clock_curr = ov5642_data.mclk;
++ pr_debug(" clock_curr=mclk=%d\n", ov5642_data.mclk);
++ p->if_type = V4L2_IF_TYPE_BT656;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.clock_min = OV5642_XCLK_MIN;
++ p->u.bt656.clock_max = OV5642_XCLK_MAX;
++ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor_data *sensor = s->priv;
++
++ if (on && !sensor->on) {
++ if (io_regulator)
++ if (regulator_enable(io_regulator) != 0)
++ return -EIO;
++ if (core_regulator)
++ if (regulator_enable(core_regulator) != 0)
++ return -EIO;
++ if (gpo_regulator)
++ if (regulator_enable(gpo_regulator) != 0)
++ return -EIO;
++ if (analog_regulator)
++ if (regulator_enable(analog_regulator) != 0)
++ return -EIO;
++ /* Make sure power on */
++ ov5642_standby(0);
++ } else if (!on && sensor->on) {
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++ if (core_regulator)
++ regulator_disable(core_regulator);
++ if (io_regulator)
++ regulator_disable(io_regulator);
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ ov5642_standby(1);
++ }
++
++ sensor->on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps, old_fps; /* target frames per secound */
++ enum ov5642_frame_rate new_frame_rate, old_frame_rate;
++ int ret = 0;
++
++ /* Make sure power on */
++ ov5642_standby(0);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 15)
++ new_frame_rate = ov5642_15_fps;
++ else if (tgt_fps == 30)
++ new_frame_rate = ov5642_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ return -EINVAL;
++ }
++
++ if (sensor->streamcap.timeperframe.numerator != 0)
++ old_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++ else
++ old_fps = 30;
++
++ if (old_fps == 15)
++ old_frame_rate = ov5642_15_fps;
++ else if (old_fps == 30)
++ old_frame_rate = ov5642_30_fps;
++ else {
++ pr_warning(" No valid frame rate set!\n");
++ old_frame_rate = ov5642_30_fps;
++ }
++
++ ret = ov5642_change_mode(new_frame_rate, old_frame_rate,
++ a->parm.capture.capturemode,
++ sensor->streamcap.capturemode);
++ if (ret < 0)
++ return ret;
++
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.capturemode =
++ (u32)a->parm.capture.capturemode;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor_data *sensor = s->priv;
++
++ f->fmt.pix = sensor->pix;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ vc->value = ov5642_data.brightness;
++ break;
++ case V4L2_CID_HUE:
++ vc->value = ov5642_data.hue;
++ break;
++ case V4L2_CID_CONTRAST:
++ vc->value = ov5642_data.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ vc->value = ov5642_data.saturation;
++ break;
++ case V4L2_CID_RED_BALANCE:
++ vc->value = ov5642_data.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ vc->value = ov5642_data.blue;
++ break;
++ case V4L2_CID_EXPOSURE:
++ vc->value = ov5642_data.ae_mode;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++ struct sensor_data *sensor = s->priv;
++ __u32 captureMode = sensor->streamcap.capturemode;
++ struct reg_value *rot_mode = NULL;
++
++ pr_debug("In ov5642:ioctl_s_ctrl %d\n",
++ vc->id);
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ break;
++ case V4L2_CID_CONTRAST:
++ break;
++ case V4L2_CID_SATURATION:
++ break;
++ case V4L2_CID_HUE:
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_RED_BALANCE:
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ break;
++ case V4L2_CID_GAMMA:
++ break;
++ case V4L2_CID_EXPOSURE:
++ break;
++ case V4L2_CID_AUTOGAIN:
++ break;
++ case V4L2_CID_GAIN:
++ break;
++ case V4L2_CID_HFLIP:
++ break;
++ case V4L2_CID_VFLIP:
++ break;
++ case V4L2_CID_MXC_ROT:
++ case V4L2_CID_MXC_VF_ROT:
++ switch (vc->value) {
++ case V4L2_MXC_ROTATE_NONE:
++ if (captureMode == ov5642_mode_QSXGA_2592_1944)
++ rot_mode = ov5642_rot_none_FULL;
++ else
++ rot_mode = ov5642_rot_none_VGA;
++
++ if (ov5642_set_rot_mode(rot_mode))
++ retval = -EPERM;
++ break;
++ case V4L2_MXC_ROTATE_VERT_FLIP:
++ if (captureMode == ov5642_mode_QSXGA_2592_1944)
++ rot_mode = ov5642_rot_vert_flip_FULL;
++ else
++ rot_mode = ov5642_rot_vert_flip_VGA ;
++
++ if (ov5642_set_rot_mode(rot_mode))
++ retval = -EPERM;
++ break;
++ case V4L2_MXC_ROTATE_HORIZ_FLIP:
++ if (captureMode == ov5642_mode_QSXGA_2592_1944)
++ rot_mode = ov5642_rot_horiz_flip_FULL;
++ else
++ rot_mode = ov5642_rot_horiz_flip_VGA;
++
++ if (ov5642_set_rot_mode(rot_mode))
++ retval = -EPERM;
++ break;
++ case V4L2_MXC_ROTATE_180:
++ if (captureMode == ov5642_mode_QSXGA_2592_1944)
++ rot_mode = ov5642_rot_180_FULL;
++ else
++ rot_mode = ov5642_rot_180_VGA;
++
++ if (ov5642_set_rot_mode(rot_mode))
++ retval = -EPERM;
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index > ov5642_mode_MAX)
++ return -EINVAL;
++
++ fsize->pixel_format = ov5642_data.pix.pixelformat;
++ fsize->discrete.width =
++ max(ov5642_mode_info_data[0][fsize->index].width,
++ ov5642_mode_info_data[1][fsize->index].width);
++ fsize->discrete.height =
++ max(ov5642_mode_info_data[0][fsize->index].height,
++ ov5642_mode_info_data[1][fsize->index].height);
++ return 0;
++}
++
++/*!
++ * ioctl_enum_frameintervals - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMEINTERVALS ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_frameintervals(struct v4l2_int_device *s,
++ struct v4l2_frmivalenum *fival)
++{
++ int i, j, count;
++
++ if (fival->index < 0 || fival->index > ov5642_mode_MAX)
++ return -EINVAL;
++
++ if (fival->pixel_format == 0 || fival->width == 0 ||
++ fival->height == 0) {
++ pr_warning("Please assign pixelformat, width and height.\n");
++ return -EINVAL;
++ }
++
++ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++ fival->discrete.numerator = 1;
++
++ count = 0;
++ for (i = 0; i < ARRAY_SIZE(ov5642_mode_info_data); i++) {
++ for (j = 0; j < (ov5642_mode_MAX + 1); j++) {
++ if (fival->pixel_format == ov5642_data.pix.pixelformat
++ && fival->width == ov5642_mode_info_data[i][j].width
++ && fival->height == ov5642_mode_info_data[i][j].height
++ && ov5642_mode_info_data[i][j].init_data_ptr != NULL) {
++ count++;
++ }
++ if (fival->index == (count - 1)) {
++ fival->discrete.denominator =
++ ov5642_framerates[i];
++ return 0;
++ }
++ }
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov5642_camera");
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
++ * @s: pointer to standard V4L2 device structure
++ * @fmt: pointer to standard V4L2 fmt description structure
++ *
++ * Return 0.
++ */
++static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index > 0) /* only 1 pixelformat support so far */
++ return -EINVAL;
++
++ fmt->pixelformat = ov5642_data.pix.pixelformat;
++
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 i = 0;
++ s32 iModeSettingArySize = 0;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++
++ struct sensor_data *sensor = s->priv;
++ u32 tgt_xclk; /* target xclk */
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5642_frame_rate frame_rate;
++
++ ov5642_data.on = true;
++
++ /* mclk */
++ tgt_xclk = ov5642_data.mclk;
++ tgt_xclk = min(tgt_xclk, (u32)OV5642_XCLK_MAX);
++ tgt_xclk = max(tgt_xclk, (u32)OV5642_XCLK_MIN);
++ ov5642_data.mclk = tgt_xclk;
++
++ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000);
++
++ /* Default camera frame rate is set in probe */
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5642_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5642_30_fps;
++ else
++ return -EINVAL; /* Only support 15fps or 30fps now. */
++
++ pModeSetting = ov5642_initial_setting;
++ iModeSettingArySize = ARRAY_SIZE(ov5642_initial_setting);
++
++ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++ if (Mask) {
++ retval = ov5642_read_reg(RegAddr, &RegVal);
++ if (retval < 0)
++ goto err;
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5642_write_reg(RegAddr, Val);
++ if (retval < 0)
++ goto err;
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++/*!
++ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Delinitialise the device when slave detaches to the master.
++ */
++static int ioctl_dev_exit(struct v4l2_int_device *s)
++{
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module and links them to the
++ * enumeration.
++ */
++static struct v4l2_int_ioctl_desc ov5642_ioctl_desc[] = {
++ { vidioc_int_dev_init_num,
++ (v4l2_int_ioctl_func *)ioctl_dev_init },
++ { vidioc_int_dev_exit_num, ioctl_dev_exit},
++ { vidioc_int_s_power_num,
++ (v4l2_int_ioctl_func *)ioctl_s_power },
++ { vidioc_int_g_ifparm_num,
++ (v4l2_int_ioctl_func *)ioctl_g_ifparm },
++/* { vidioc_int_g_needs_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_g_needs_reset }, */
++/* { vidioc_int_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_reset }, */
++ { vidioc_int_init_num,
++ (v4l2_int_ioctl_func *)ioctl_init },
++ { vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap },
++/* { vidioc_int_try_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap }, */
++ { vidioc_int_g_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_g_fmt_cap },
++/* { vidioc_int_s_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_s_fmt_cap }, */
++ { vidioc_int_g_parm_num,
++ (v4l2_int_ioctl_func *)ioctl_g_parm },
++ { vidioc_int_s_parm_num,
++ (v4l2_int_ioctl_func *)ioctl_s_parm },
++/* { vidioc_int_queryctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_queryctrl }, */
++ { vidioc_int_g_ctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_g_ctrl },
++ { vidioc_int_s_ctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_s_ctrl },
++ { vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_framesizes },
++ { vidioc_int_enum_frameintervals_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_frameintervals },
++ { vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *)ioctl_g_chip_ident },
++};
++
++static struct v4l2_int_slave ov5642_slave = {
++ .ioctls = ov5642_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(ov5642_ioctl_desc),
++};
++
++static struct v4l2_int_device ov5642_int_device = {
++ .module = THIS_MODULE,
++ .name = "ov5642",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &ov5642_slave,
++ },
++};
++
++/*!
++ * ov5642 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++static int ov5642_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct pinctrl *pinctrl;
++ struct device *dev = &client->dev;
++ int retval;
++ u8 chip_id_high, chip_id_low;
++
++ /* ov5642 pinctrl */
++ pinctrl = devm_pinctrl_get_select_default(dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(dev, "ov5642 setup pinctrl failed!");
++ return PTR_ERR(pinctrl);
++ }
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_warn(dev, "no sensor pwdn pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5642_pwdn");
++ if (retval < 0)
++ return retval;
++
++ /* request reset pin */
++ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
++ if (!gpio_is_valid(rst_gpio)) {
++ dev_warn(dev, "no sensor reset pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5642_reset");
++ if (retval < 0)
++ return retval;
++
++ /* Set initial values for the sensor struct. */
++ memset(&ov5642_data, 0, sizeof(ov5642_data));
++ ov5642_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(ov5642_data.sensor_clk)) {
++ /* assuming clock enabled by default */
++ ov5642_data.sensor_clk = NULL;
++ dev_err(dev, "clock-frequency missing or invalid\n");
++ return PTR_ERR(ov5642_data.sensor_clk);
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ (u32 *) &(ov5642_data.mclk));
++ if (retval) {
++ dev_err(dev, "mclk missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(ov5642_data.mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(ov5642_data.csi));
++ if (retval) {
++ dev_err(dev, "csi_id missing or invalid\n");
++ return retval;
++ }
++
++ clk_prepare_enable(ov5642_data.sensor_clk);
++
++ ov5642_data.io_init = ov5642_reset;
++ ov5642_data.i2c_client = client;
++ ov5642_data.pix.pixelformat = V4L2_PIX_FMT_YUYV;
++ ov5642_data.pix.width = 640;
++ ov5642_data.pix.height = 480;
++ ov5642_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ ov5642_data.streamcap.capturemode = 0;
++ ov5642_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
++ ov5642_data.streamcap.timeperframe.numerator = 1;
++
++ ov5642_power_on(&client->dev);
++
++ ov5642_reset();
++
++ ov5642_standby(0);
++
++ retval = ov5642_read_reg(OV5642_CHIP_ID_HIGH_BYTE, &chip_id_high);
++ if (retval < 0 || chip_id_high != 0x56) {
++ pr_warning("camera ov5642 is not found\n");
++ clk_disable_unprepare(ov5642_data.sensor_clk);
++ return -ENODEV;
++ }
++ retval = ov5642_read_reg(OV5642_CHIP_ID_LOW_BYTE, &chip_id_low);
++ if (retval < 0 || chip_id_low != 0x42) {
++ pr_warning("camera ov5642 is not found\n");
++ clk_disable_unprepare(ov5642_data.sensor_clk);
++ return -ENODEV;
++ }
++
++ ov5642_standby(1);
++
++ ov5642_int_device.priv = &ov5642_data;
++ retval = v4l2_int_device_register(&ov5642_int_device);
++
++ clk_disable_unprepare(ov5642_data.sensor_clk);
++
++ pr_info("camera ov5642 is found\n");
++ return retval;
++}
++
++/*!
++ * ov5642 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int ov5642_remove(struct i2c_client *client)
++{
++ v4l2_int_device_unregister(&ov5642_int_device);
++
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++
++ if (core_regulator)
++ regulator_disable(core_regulator);
++
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ return 0;
++}
++
++/*!
++ * ov5642 init function
++ * Called by insmod ov5642_camera.ko.
++ *
++ * @return Error code indicating success or failure
++ */
++static __init int ov5642_init(void)
++{
++ u8 err;
++
++ err = i2c_add_driver(&ov5642_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d\n",
++ __func__, err);
++
++ return err;
++}
++
++/*!
++ * OV5642 cleanup function
++ * Called on rmmod ov5642_camera.ko
++ *
++ * @return Error code indicating success or failure
++ */
++static void __exit ov5642_clean(void)
++{
++ i2c_del_driver(&ov5642_i2c_driver);
++}
++
++module_init(ov5642_init);
++module_exit(ov5642_clean);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("OV5642 Camera Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/output/Kconfig linux-linaro-stable-mx6/drivers/media/platform/mxc/output/Kconfig
+--- linux-3.10.30.orig/drivers/media/platform/mxc/output/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/output/Kconfig 2014-05-15 20:33:57.142007696 +0200
+@@ -0,0 +1,16 @@
++config VIDEO_MXC_IPU_OUTPUT
++ tristate "IPU v4l2 output support"
++ depends on VIDEO_MXC_OUTPUT && MXC_IPU
++ ---help---
++ This is the video4linux2 driver for IPU post processing video output.
++
++config VIDEO_MXC_PXP_V4L2
++ tristate "MXC PxP V4L2 driver"
++ depends on VIDEO_DEV && VIDEO_V4L2
++ select VIDEOBUF_DMA_CONTIG
++ ---help---
++ This is a video4linux driver for the Freescale PxP
++ (Pixel Pipeline). This module supports output overlay of
++ the MXC framebuffer on a video stream.
++
++ To compile this driver as a module, choose M here.
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/output/Makefile linux-linaro-stable-mx6/drivers/media/platform/mxc/output/Makefile
+--- linux-3.10.30.orig/drivers/media/platform/mxc/output/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/output/Makefile 2014-05-15 20:33:57.142007696 +0200
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_VIDEO_MXC_IPU_OUTPUT) += mxc_vout.o
++obj-$(CONFIG_VIDEO_MXC_PXP_V4L2) += mxc_pxp_v4l2.o
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c linux-linaro-stable-mx6/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c 2014-05-15 20:33:57.142007696 +0200
+@@ -0,0 +1,1263 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * Based on STMP378X PxP driver
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/vmalloc.h>
++#include <linux/videodev2.h>
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++#include <linux/delay.h>
++#include <linux/console.h>
++#include <linux/mxcfb.h>
++
++#include <media/videobuf-dma-contig.h>
++#include <media/v4l2-common.h>
++#include <media/v4l2-dev.h>
++#include <media/v4l2-ioctl.h>
++
++#include "mxc_pxp_v4l2.h"
++
++#define PXP_DRIVER_NAME "pxp-v4l2"
++#define PXP_DRIVER_MAJOR 2
++#define PXP_DRIVER_MINOR 0
++
++#define PXP_DEF_BUFS 2
++#define PXP_MIN_PIX 8
++
++#define V4L2_OUTPUT_TYPE_INTERNAL 4
++
++static int video_nr = -1; /* -1 ==> auto assign */
++static struct pxp_data_format pxp_s0_formats[] = {
++ {
++ .name = "24-bit RGB",
++ .bpp = 4,
++ .fourcc = V4L2_PIX_FMT_RGB24,
++ .colorspace = V4L2_COLORSPACE_SRGB,
++ }, {
++ .name = "16-bit RGB 5:6:5",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_RGB565,
++ .colorspace = V4L2_COLORSPACE_SRGB,
++ }, {
++ .name = "16-bit RGB 5:5:5",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_RGB555,
++ .colorspace = V4L2_COLORSPACE_SRGB,
++ }, {
++ .name = "YUV 4:2:0 Planar",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_YUV420,
++ .colorspace = V4L2_COLORSPACE_JPEG,
++ }, {
++ .name = "YUV 4:2:2 Planar",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_YUV422P,
++ .colorspace = V4L2_COLORSPACE_JPEG,
++ }, {
++ .name = "UYVY",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_UYVY,
++ .colorspace = V4L2_COLORSPACE_JPEG,
++ },
++};
++
++static unsigned int v4l2_fmt_to_pxp_fmt(u32 v4l2_pix_fmt)
++{
++ u32 pxp_fmt = 0;
++
++ if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB24)
++ pxp_fmt = PXP_PIX_FMT_RGB24;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB565)
++ pxp_fmt = PXP_PIX_FMT_RGB565;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555)
++ pxp_fmt = PXP_PIX_FMT_RGB555;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555)
++ pxp_fmt = PXP_PIX_FMT_RGB555;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV420)
++ pxp_fmt = PXP_PIX_FMT_YUV420P;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV422P)
++ pxp_fmt = PXP_PIX_FMT_YUV422P;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_UYVY)
++ pxp_fmt = PXP_PIX_FMT_UYVY;
++
++ return pxp_fmt;
++}
++struct v4l2_queryctrl pxp_controls[] = {
++ {
++ .id = V4L2_CID_HFLIP,
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ .name = "Horizontal Flip",
++ .minimum = 0,
++ .maximum = 1,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_VFLIP,
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ .name = "Vertical Flip",
++ .minimum = 0,
++ .maximum = 1,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ .name = "Rotation",
++ .minimum = 0,
++ .maximum = 270,
++ .step = 90,
++ .default_value = 0,
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE + 1,
++ .name = "Background Color",
++ .minimum = 0,
++ .maximum = 0xFFFFFF,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE + 2,
++ .name = "Set S0 Chromakey",
++ .minimum = -1,
++ .maximum = 0xFFFFFF,
++ .step = 1,
++ .default_value = -1,
++ .flags = 0,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE + 3,
++ .name = "YUV Colorspace",
++ .minimum = 0,
++ .maximum = 1,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ },
++};
++
++/* callback function */
++static void video_dma_done(void *arg)
++{
++ struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
++ struct dma_chan *chan = tx_desc->txd.chan;
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxps *pxp = pxp_chan->client;
++ struct videobuf_buffer *vb;
++
++ dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
++ tx_desc->txd.cookie,
++ pxp->active ? sg_dma_address(&pxp->active->sg[0]) : 0);
++
++ spin_lock(&pxp->lock);
++ if (pxp->active) {
++ vb = &pxp->active->vb;
++
++ list_del_init(&vb->queue);
++ vb->state = VIDEOBUF_DONE;
++ do_gettimeofday(&vb->ts);
++ vb->field_count++;
++ wake_up(&vb->done);
++ }
++
++ if (list_empty(&pxp->outq)) {
++ pxp->active = NULL;
++ spin_unlock(&pxp->lock);
++
++ return;
++ }
++
++ pxp->active = list_entry(pxp->outq.next,
++ struct pxp_buffer, vb.queue);
++ pxp->active->vb.state = VIDEOBUF_ACTIVE;
++ spin_unlock(&pxp->lock);
++}
++
++static int acquire_dma_channel(struct pxps *pxp)
++{
++ dma_cap_mask_t mask;
++ struct dma_chan *chan;
++ struct pxp_channel **pchan = &pxp->pxp_channel[0];
++
++ if (*pchan) {
++ struct videobuf_buffer *vb, *_vb;
++ dma_release_channel(&(*pchan)->dma_chan);
++ *pchan = NULL;
++ pxp->active = NULL;
++ list_for_each_entry_safe(vb, _vb, &pxp->outq, queue) {
++ list_del_init(&vb->queue);
++ vb->state = VIDEOBUF_ERROR;
++ wake_up(&vb->done);
++ }
++ }
++
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_PRIVATE, mask);
++ chan = dma_request_channel(mask, NULL, NULL);
++ if (!chan)
++ return -EBUSY;
++
++ *pchan = to_pxp_channel(chan);
++ (*pchan)->client = pxp;
++
++ return 0;
++}
++
++static int _get_fbinfo(struct fb_info **fbi)
++{
++ int i;
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (strcmp(idstr, "mxs") == 0) {
++ *fbi = registered_fb[i];
++ return 0;
++ }
++ }
++
++ return -ENODEV;
++}
++
++static int pxp_set_fbinfo(struct pxps *pxp)
++{
++ struct v4l2_framebuffer *fb = &pxp->fb;
++ int err;
++
++ err = _get_fbinfo(&pxp->fbi);
++ if (err)
++ return err;
++
++ fb->fmt.width = pxp->fbi->var.xres;
++ fb->fmt.height = pxp->fbi->var.yres;
++ pxp->pxp_conf.out_param.stride = pxp->fbi->var.xres;
++ if (pxp->fbi->var.bits_per_pixel == 16)
++ fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565;
++ else
++ fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24;
++
++ fb->base = (void *)pxp->fbi->fix.smem_start;
++
++ return 0;
++}
++
++static int _get_cur_fb_blank(struct pxps *pxp)
++{
++ struct fb_info *fbi;
++ mm_segment_t old_fs;
++ int err = 0;
++
++ err = _get_fbinfo(&fbi);
++ if (err)
++ return err;
++
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ err = fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_BLANK,
++ (unsigned int)(&pxp->fb_blank));
++ set_fs(old_fs);
++ }
++
++ return err;
++}
++
++static int pxp_show_buf(struct pxps *pxp, bool toshow)
++{
++ struct fb_info *fbi = pxp->fbi;
++ int ret;
++
++ console_lock();
++ fbi->fix.smem_start = toshow ?
++ pxp->outb_phys : (unsigned long)pxp->fb.base;
++ ret = fb_pan_display(fbi, &fbi->var);
++ console_unlock();
++
++ return ret;
++}
++
++static int set_fb_blank(int blank)
++{
++ struct fb_info *fbi;
++ int err = 0;
++
++ err = _get_fbinfo(&fbi);
++ if (err)
++ return err;
++
++ console_lock();
++ fb_blank(fbi, blank);
++ console_unlock();
++
++ return err;
++}
++
++static int pxp_set_cstate(struct pxps *pxp, struct v4l2_control *vc)
++{
++
++ if (vc->id == V4L2_CID_HFLIP) {
++ pxp->pxp_conf.proc_data.hflip = vc->value;
++ } else if (vc->id == V4L2_CID_VFLIP) {
++ pxp->pxp_conf.proc_data.vflip = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE) {
++ if (vc->value % 90)
++ return -ERANGE;
++ pxp->pxp_conf.proc_data.rotate = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) {
++ pxp->pxp_conf.proc_data.bgcolor = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) {
++ pxp->pxp_conf.s0_param.color_key = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) {
++ pxp->pxp_conf.proc_data.yuv = vc->value;
++ }
++
++ return 0;
++}
++
++static int pxp_get_cstate(struct pxps *pxp, struct v4l2_control *vc)
++{
++ if (vc->id == V4L2_CID_HFLIP)
++ vc->value = pxp->pxp_conf.proc_data.hflip;
++ else if (vc->id == V4L2_CID_VFLIP)
++ vc->value = pxp->pxp_conf.proc_data.vflip;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE)
++ vc->value = pxp->pxp_conf.proc_data.rotate;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE + 1)
++ vc->value = pxp->pxp_conf.proc_data.bgcolor;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE + 2)
++ vc->value = pxp->pxp_conf.s0_param.color_key;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE + 3)
++ vc->value = pxp->pxp_conf.proc_data.yuv;
++
++ return 0;
++}
++
++static int pxp_enumoutput(struct file *file, void *fh,
++ struct v4l2_output *o)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ if ((o->index < 0) || (o->index > 1))
++ return -EINVAL;
++
++ memset(o, 0, sizeof(struct v4l2_output));
++ if (o->index == 0) {
++ strcpy(o->name, "PxP Display Output");
++ pxp->output = 0;
++ } else {
++ strcpy(o->name, "PxP Virtual Output");
++ pxp->output = 1;
++ }
++ o->type = V4L2_OUTPUT_TYPE_INTERNAL;
++ o->std = 0;
++ o->reserved[0] = pxp->outb_phys;
++
++ return 0;
++}
++
++static int pxp_g_output(struct file *file, void *fh,
++ unsigned int *i)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ *i = pxp->output;
++
++ return 0;
++}
++
++static int pxp_s_output(struct file *file, void *fh,
++ unsigned int i)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_pix_format *fmt = &pxp->fb.fmt;
++ int bpp;
++
++ if ((i < 0) || (i > 1))
++ return -EINVAL;
++
++ if (pxp->outb)
++ return 0;
++
++ /* Output buffer is same format as fbdev */
++ if (fmt->pixelformat == V4L2_PIX_FMT_RGB24)
++ bpp = 4;
++ else
++ bpp = 2;
++
++ pxp->outb_size = fmt->width * fmt->height * bpp;
++ pxp->outb = kmalloc(fmt->width * fmt->height * bpp,
++ GFP_KERNEL | GFP_DMA);
++ if (pxp->outb == NULL) {
++ dev_err(&pxp->pdev->dev, "No enough memory!\n");
++ return -ENOMEM;
++ }
++ pxp->outb_phys = virt_to_phys(pxp->outb);
++ dma_map_single(NULL, pxp->outb,
++ fmt->width * fmt->height * bpp, DMA_TO_DEVICE);
++
++ pxp->pxp_conf.out_param.width = fmt->width;
++ pxp->pxp_conf.out_param.height = fmt->height;
++ if (fmt->pixelformat == V4L2_PIX_FMT_RGB24)
++ pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB24;
++ else
++ pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++
++ return 0;
++}
++
++static int pxp_enum_fmt_video_output(struct file *file, void *fh,
++ struct v4l2_fmtdesc *fmt)
++{
++ enum v4l2_buf_type type = fmt->type;
++ int index = fmt->index;
++
++ if ((fmt->index < 0) || (fmt->index >= ARRAY_SIZE(pxp_s0_formats)))
++ return -EINVAL;
++
++ memset(fmt, 0, sizeof(struct v4l2_fmtdesc));
++ fmt->index = index;
++ fmt->type = type;
++ fmt->pixelformat = pxp_s0_formats[index].fourcc;
++ strcpy(fmt->description, pxp_s0_formats[index].name);
++
++ return 0;
++}
++
++static int pxp_g_fmt_video_output(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct v4l2_pix_format *pf = &f->fmt.pix;
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct pxp_data_format *fmt = pxp->s0_fmt;
++
++ pf->width = pxp->pxp_conf.s0_param.width;
++ pf->height = pxp->pxp_conf.s0_param.height;
++ pf->pixelformat = fmt->fourcc;
++ pf->field = V4L2_FIELD_NONE;
++ pf->bytesperline = fmt->bpp * pf->width;
++ pf->sizeimage = pf->bytesperline * pf->height;
++ pf->colorspace = fmt->colorspace;
++ pf->priv = 0;
++
++ return 0;
++}
++
++static struct pxp_data_format *pxp_get_format(struct v4l2_format *f)
++{
++ struct pxp_data_format *fmt;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pxp_s0_formats); i++) {
++ fmt = &pxp_s0_formats[i];
++ if (fmt->fourcc == f->fmt.pix.pixelformat)
++ break;
++ }
++
++ if (i == ARRAY_SIZE(pxp_s0_formats))
++ return NULL;
++
++ return &pxp_s0_formats[i];
++}
++
++static int pxp_try_fmt_video_output(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ int w = f->fmt.pix.width;
++ int h = f->fmt.pix.height;
++ struct pxp_data_format *fmt = pxp_get_format(f);
++
++ if (!fmt)
++ return -EINVAL;
++
++ w = min(w, 2040);
++ w = max(w, 8);
++ h = min(h, 2040);
++ h = max(h, 8);
++ f->fmt.pix.field = V4L2_FIELD_NONE;
++ f->fmt.pix.width = w;
++ f->fmt.pix.height = h;
++ f->fmt.pix.pixelformat = fmt->fourcc;
++
++ return 0;
++}
++
++static int pxp_s_fmt_video_output(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_pix_format *pf = &f->fmt.pix;
++ int ret;
++
++ ret = acquire_dma_channel(pxp);
++ if (ret < 0)
++ return ret;
++
++ ret = pxp_try_fmt_video_output(file, fh, f);
++ if (ret == 0) {
++ pxp->s0_fmt = pxp_get_format(f);
++ pxp->pxp_conf.s0_param.pixel_fmt =
++ v4l2_fmt_to_pxp_fmt(pxp->s0_fmt->fourcc);
++ pxp->pxp_conf.s0_param.width = pf->width;
++ pxp->pxp_conf.s0_param.height = pf->height;
++ }
++
++
++ return ret;
++}
++
++static int pxp_g_fmt_output_overlay(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_window *wf = &f->fmt.win;
++
++ memset(wf, 0, sizeof(struct v4l2_window));
++ wf->chromakey = pxp->s1_chromakey;
++ wf->global_alpha = pxp->global_alpha;
++ wf->field = V4L2_FIELD_NONE;
++ wf->clips = NULL;
++ wf->clipcount = 0;
++ wf->bitmap = NULL;
++ wf->w.left = pxp->pxp_conf.proc_data.srect.left;
++ wf->w.top = pxp->pxp_conf.proc_data.srect.top;
++ wf->w.width = pxp->pxp_conf.proc_data.srect.width;
++ wf->w.height = pxp->pxp_conf.proc_data.srect.height;
++
++ return 0;
++}
++
++static int pxp_try_fmt_output_overlay(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_window *wf = &f->fmt.win;
++ struct v4l2_rect srect;
++ u32 s1_chromakey = wf->chromakey;
++ u8 global_alpha = wf->global_alpha;
++
++ memcpy(&srect, &(wf->w), sizeof(struct v4l2_rect));
++
++ pxp_g_fmt_output_overlay(file, fh, f);
++
++ wf->chromakey = s1_chromakey;
++ wf->global_alpha = global_alpha;
++
++ /* Constrain parameters to the input buffer */
++ wf->w.left = srect.left;
++ wf->w.top = srect.top;
++ wf->w.width = min(srect.width,
++ ((__s32)pxp->pxp_conf.s0_param.width - wf->w.left));
++ wf->w.height = min(srect.height,
++ ((__s32)pxp->pxp_conf.s0_param.height - wf->w.top));
++
++ return 0;
++}
++
++static int pxp_s_fmt_output_overlay(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_window *wf = &f->fmt.win;
++ int ret = pxp_try_fmt_output_overlay(file, fh, f);
++
++ if (ret == 0) {
++ pxp->global_alpha = wf->global_alpha;
++ pxp->s1_chromakey = wf->chromakey;
++ pxp->pxp_conf.proc_data.srect.left = wf->w.left;
++ pxp->pxp_conf.proc_data.srect.top = wf->w.top;
++ pxp->pxp_conf.proc_data.srect.width = wf->w.width;
++ pxp->pxp_conf.proc_data.srect.height = wf->w.height;
++ pxp->pxp_conf.ol_param[0].global_alpha = pxp->global_alpha;
++ pxp->pxp_conf.ol_param[0].color_key = pxp->s1_chromakey;
++ pxp->pxp_conf.ol_param[0].color_key_enable =
++ pxp->s1_chromakey_state;
++ }
++
++ return ret;
++}
++
++static int pxp_reqbufs(struct file *file, void *priv,
++ struct v4l2_requestbuffers *r)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ return videobuf_reqbufs(&pxp->s0_vbq, r);
++}
++
++static int pxp_querybuf(struct file *file, void *priv,
++ struct v4l2_buffer *b)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ return videobuf_querybuf(&pxp->s0_vbq, b);
++}
++
++static int pxp_qbuf(struct file *file, void *priv,
++ struct v4l2_buffer *b)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ return videobuf_qbuf(&pxp->s0_vbq, b);
++}
++
++static int pxp_dqbuf(struct file *file, void *priv,
++ struct v4l2_buffer *b)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ return videobuf_dqbuf(&pxp->s0_vbq, b, file->f_flags & O_NONBLOCK);
++}
++
++static int pxp_streamon(struct file *file, void *priv,
++ enum v4l2_buf_type t)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int ret = 0;
++
++ if (t != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ _get_cur_fb_blank(pxp);
++ set_fb_blank(FB_BLANK_UNBLANK);
++
++ ret = videobuf_streamon(&pxp->s0_vbq);
++
++ if (!ret && (pxp->output == 0))
++ pxp_show_buf(pxp, true);
++
++ return ret;
++}
++
++static int pxp_streamoff(struct file *file, void *priv,
++ enum v4l2_buf_type t)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int ret = 0;
++
++ if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT))
++ return -EINVAL;
++
++ ret = videobuf_streamoff(&pxp->s0_vbq);
++
++ if (!ret)
++ pxp_show_buf(pxp, false);
++
++ if (pxp->fb_blank)
++ set_fb_blank(FB_BLANK_POWERDOWN);
++
++ return ret;
++}
++
++static int pxp_buf_setup(struct videobuf_queue *q,
++ unsigned int *count, unsigned *size)
++{
++ struct pxps *pxp = q->priv_data;
++
++ *size = pxp->pxp_conf.s0_param.width *
++ pxp->pxp_conf.s0_param.height * pxp->s0_fmt->bpp;
++
++ if (0 == *count)
++ *count = PXP_DEF_BUFS;
++
++ return 0;
++}
++
++static void pxp_buf_free(struct videobuf_queue *q, struct pxp_buffer *buf)
++{
++ struct videobuf_buffer *vb = &buf->vb;
++ struct dma_async_tx_descriptor *txd = buf->txd;
++
++ BUG_ON(in_interrupt());
++
++ pr_debug("%s (vb=0x%p) 0x%08lx %d\n", __func__,
++ vb, vb->baddr, vb->bsize);
++
++ /*
++ * This waits until this buffer is out of danger, i.e., until it is no
++ * longer in STATE_QUEUED or STATE_ACTIVE
++ */
++ videobuf_waiton(q, vb, 0, 0);
++ if (txd)
++ async_tx_ack(txd);
++
++ videobuf_dma_contig_free(q, vb);
++ buf->txd = NULL;
++
++ vb->state = VIDEOBUF_NEEDS_INIT;
++}
++
++static int pxp_buf_prepare(struct videobuf_queue *q,
++ struct videobuf_buffer *vb,
++ enum v4l2_field field)
++{
++ struct pxps *pxp = q->priv_data;
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb);
++ struct pxp_tx_desc *desc;
++ int ret = 0;
++ int i, length;
++
++ vb->width = pxp->pxp_conf.s0_param.width;
++ vb->height = pxp->pxp_conf.s0_param.height;
++ vb->size = vb->width * vb->height * pxp->s0_fmt->bpp;
++ vb->field = V4L2_FIELD_NONE;
++ if (vb->state != VIDEOBUF_NEEDS_INIT)
++ pxp_buf_free(q, buf);
++
++ if (vb->state == VIDEOBUF_NEEDS_INIT) {
++ struct pxp_channel *pchan = pxp->pxp_channel[0];
++ struct scatterlist *sg = &buf->sg[0];
++
++ /* This actually (allocates and) maps buffers */
++ ret = videobuf_iolock(q, vb, NULL);
++ if (ret) {
++ pr_err("fail to call videobuf_iolock, ret = %d\n", ret);
++ goto fail;
++ }
++
++ /*
++ * sg[0] for input(S0)
++ * Sg[1] for output
++ */
++ sg_init_table(sg, 3);
++
++ buf->txd = pchan->dma_chan.device->device_prep_slave_sg(
++ &pchan->dma_chan, sg, 3, DMA_FROM_DEVICE,
++ DMA_PREP_INTERRUPT, NULL);
++ if (!buf->txd) {
++ ret = -EIO;
++ goto fail;
++ }
++
++ buf->txd->callback_param = buf->txd;
++ buf->txd->callback = video_dma_done;
++
++ desc = to_tx_desc(buf->txd);
++ length = desc->len;
++ for (i = 0; i < length; i++) {
++ if (i == 0) {/* S0 */
++ memcpy(&desc->proc_data, proc_data,
++ sizeof(struct pxp_proc_data));
++ pxp_conf->s0_param.paddr =
++ videobuf_to_dma_contig(vb);
++ memcpy(&desc->layer_param.s0_param,
++ &pxp_conf->s0_param,
++ sizeof(struct pxp_layer_param));
++ } else if (i == 1) { /* Output */
++ if (proc_data->rotate % 180) {
++ pxp_conf->out_param.width =
++ pxp->fb.fmt.height;
++ pxp_conf->out_param.height =
++ pxp->fb.fmt.width;
++ } else {
++ pxp_conf->out_param.width =
++ pxp->fb.fmt.width;
++ pxp_conf->out_param.height =
++ pxp->fb.fmt.height;
++ }
++
++ pxp_conf->out_param.paddr = pxp->outb_phys;
++ memcpy(&desc->layer_param.out_param,
++ &pxp_conf->out_param,
++ sizeof(struct pxp_layer_param));
++ } else if (pxp_conf->ol_param[0].combine_enable) {
++ /* Overlay */
++ pxp_conf->ol_param[0].paddr =
++ (dma_addr_t)pxp->fb.base;
++ pxp_conf->ol_param[0].width = pxp->fb.fmt.width;
++ pxp_conf->ol_param[0].height =
++ pxp->fb.fmt.height;
++ pxp_conf->ol_param[0].pixel_fmt =
++ pxp_conf->out_param.pixel_fmt;
++ memcpy(&desc->layer_param.ol_param,
++ &pxp_conf->ol_param[0],
++ sizeof(struct pxp_layer_param));
++ }
++
++ desc = desc->next;
++ }
++
++ vb->state = VIDEOBUF_PREPARED;
++ }
++
++ return 0;
++
++fail:
++ pxp_buf_free(q, buf);
++ return ret;
++}
++
++
++static void pxp_buf_queue(struct videobuf_queue *q,
++ struct videobuf_buffer *vb)
++{
++ struct pxps *pxp = q->priv_data;
++ struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb);
++ struct dma_async_tx_descriptor *txd = buf->txd;
++ struct pxp_channel *pchan = pxp->pxp_channel[0];
++ dma_cookie_t cookie;
++
++ BUG_ON(!irqs_disabled());
++
++ list_add_tail(&vb->queue, &pxp->outq);
++
++ if (!pxp->active) {
++ pxp->active = buf;
++ vb->state = VIDEOBUF_ACTIVE;
++ } else {
++ vb->state = VIDEOBUF_QUEUED;
++ }
++
++ spin_unlock_irq(&pxp->lock);
++
++ cookie = txd->tx_submit(txd);
++ dev_dbg(&pxp->pdev->dev, "Submitted cookie %d DMA 0x%08x\n",
++ cookie, sg_dma_address(&buf->sg[0]));
++ mdelay(5);
++ /* trigger ePxP */
++ dma_async_issue_pending(&pchan->dma_chan);
++
++ spin_lock_irq(&pxp->lock);
++
++ if (cookie >= 0)
++ return;
++
++ /* Submit error */
++ pr_err("%s: Submit error\n", __func__);
++ vb->state = VIDEOBUF_PREPARED;
++
++ list_del_init(&vb->queue);
++
++ if (pxp->active == buf)
++ pxp->active = NULL;
++}
++
++static void pxp_buf_release(struct videobuf_queue *q,
++ struct videobuf_buffer *vb)
++{
++ struct pxps *pxp = q->priv_data;
++ struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb);
++ unsigned long flags;
++
++ spin_lock_irqsave(&pxp->lock, flags);
++ if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) &&
++ !list_empty(&vb->queue)) {
++ vb->state = VIDEOBUF_ERROR;
++
++ list_del_init(&vb->queue);
++ if (pxp->active == buf)
++ pxp->active = NULL;
++ }
++ spin_unlock_irqrestore(&pxp->lock, flags);
++
++ pxp_buf_free(q, buf);
++}
++
++static struct videobuf_queue_ops pxp_vbq_ops = {
++ .buf_setup = pxp_buf_setup,
++ .buf_prepare = pxp_buf_prepare,
++ .buf_queue = pxp_buf_queue,
++ .buf_release = pxp_buf_release,
++};
++
++static int pxp_querycap(struct file *file, void *fh,
++ struct v4l2_capability *cap)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ memset(cap, 0, sizeof(*cap));
++ strcpy(cap->driver, "pxp");
++ strcpy(cap->card, "pxp");
++ strlcpy(cap->bus_info, dev_name(&pxp->pdev->dev),
++ sizeof(cap->bus_info));
++
++ cap->version = (PXP_DRIVER_MAJOR << 8) + PXP_DRIVER_MINOR;
++
++ cap->capabilities = V4L2_CAP_VIDEO_OUTPUT |
++ V4L2_CAP_VIDEO_OUTPUT_OVERLAY |
++ V4L2_CAP_STREAMING;
++
++ return 0;
++}
++
++static int pxp_g_fbuf(struct file *file, void *priv,
++ struct v4l2_framebuffer *fb)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ memset(fb, 0, sizeof(*fb));
++
++ fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY |
++ V4L2_FBUF_CAP_CHROMAKEY |
++ V4L2_FBUF_CAP_LOCAL_ALPHA |
++ V4L2_FBUF_CAP_GLOBAL_ALPHA;
++
++ if (pxp->global_alpha_state)
++ fb->flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA;
++ if (pxp->s1_chromakey_state)
++ fb->flags |= V4L2_FBUF_FLAG_CHROMAKEY;
++
++ return 0;
++}
++
++static int pxp_s_fbuf(struct file *file, void *priv,
++ const struct v4l2_framebuffer *fb)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ pxp->overlay_state =
++ (fb->flags & V4L2_FBUF_FLAG_OVERLAY) != 0;
++ pxp->global_alpha_state =
++ (fb->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) != 0;
++ pxp->s1_chromakey_state =
++ (fb->flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0;
++
++ pxp->pxp_conf.ol_param[0].combine_enable = pxp->overlay_state;
++ pxp->pxp_conf.ol_param[0].global_alpha_enable = pxp->global_alpha_state;
++
++ return 0;
++}
++
++static int pxp_g_crop(struct file *file, void *fh,
++ struct v4l2_crop *c)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
++ return -EINVAL;
++
++ c->c.left = pxp->pxp_conf.proc_data.drect.left;
++ c->c.top = pxp->pxp_conf.proc_data.drect.top;
++ c->c.width = pxp->pxp_conf.proc_data.drect.width;
++ c->c.height = pxp->pxp_conf.proc_data.drect.height;
++
++ return 0;
++}
++
++static int pxp_s_crop(struct file *file, void *fh,
++ const struct v4l2_crop *c)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int l = c->c.left;
++ int t = c->c.top;
++ int w = c->c.width;
++ int h = c->c.height;
++ int fbw = pxp->fb.fmt.width;
++ int fbh = pxp->fb.fmt.height;
++
++ if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
++ return -EINVAL;
++
++ /* Constrain parameters to FB limits */
++ w = min(w, fbw);
++ w = max(w, PXP_MIN_PIX);
++ h = min(h, fbh);
++ h = max(h, PXP_MIN_PIX);
++ if ((l + w) > fbw)
++ l = 0;
++ if ((t + h) > fbh)
++ t = 0;
++
++ /* Round up values to PxP pixel block */
++ l = roundup(l, PXP_MIN_PIX);
++ t = roundup(t, PXP_MIN_PIX);
++ w = roundup(w, PXP_MIN_PIX);
++ h = roundup(h, PXP_MIN_PIX);
++
++ pxp->pxp_conf.proc_data.drect.left = l;
++ pxp->pxp_conf.proc_data.drect.top = t;
++ pxp->pxp_conf.proc_data.drect.width = w;
++ pxp->pxp_conf.proc_data.drect.height = h;
++
++ return 0;
++}
++
++static int pxp_queryctrl(struct file *file, void *priv,
++ struct v4l2_queryctrl *qc)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (qc->id && qc->id == pxp_controls[i].id) {
++ memcpy(qc, &(pxp_controls[i]), sizeof(*qc));
++ return 0;
++ }
++
++ return -EINVAL;
++}
++
++static int pxp_g_ctrl(struct file *file, void *priv,
++ struct v4l2_control *vc)
++{
++ int i;
++
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (vc->id == pxp_controls[i].id)
++ return pxp_get_cstate(pxp, vc);
++
++ return -EINVAL;
++}
++
++static int pxp_s_ctrl(struct file *file, void *priv,
++ struct v4l2_control *vc)
++{
++ int i;
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (vc->id == pxp_controls[i].id) {
++ if (vc->value < pxp_controls[i].minimum ||
++ vc->value > pxp_controls[i].maximum)
++ return -ERANGE;
++ return pxp_set_cstate(pxp, vc);
++ }
++
++ return -EINVAL;
++}
++
++void pxp_release(struct video_device *vfd)
++{
++ struct pxps *pxp = video_get_drvdata(vfd);
++
++ spin_lock(&pxp->lock);
++ video_device_release(vfd);
++ spin_unlock(&pxp->lock);
++}
++
++static int pxp_open(struct file *file)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int ret = 0;
++
++ mutex_lock(&pxp->mutex);
++ pxp->users++;
++
++ if (pxp->users > 1) {
++ pxp->users--;
++ ret = -EBUSY;
++ goto out;
++ }
++out:
++ mutex_unlock(&pxp->mutex);
++ if (ret)
++ return ret;
++
++ ret = pxp_set_fbinfo(pxp);
++ if (ret) {
++ dev_err(&pxp->pdev->dev, "failed to call pxp_set_fbinfo\n");
++ return ret;
++ }
++
++ videobuf_queue_dma_contig_init(&pxp->s0_vbq,
++ &pxp_vbq_ops,
++ &pxp->pdev->dev,
++ &pxp->lock,
++ V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ V4L2_FIELD_NONE,
++ sizeof(struct pxp_buffer),
++ pxp,
++ NULL);
++ dev_dbg(&pxp->pdev->dev, "call pxp_open\n");
++
++ return 0;
++}
++
++static int pxp_close(struct file *file)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ videobuf_stop(&pxp->s0_vbq);
++ videobuf_mmap_free(&pxp->s0_vbq);
++ pxp->active = NULL;
++ kfree(pxp->outb);
++ pxp->outb = NULL;
++
++ mutex_lock(&pxp->mutex);
++ pxp->users--;
++ mutex_unlock(&pxp->mutex);
++
++ return 0;
++}
++
++static int pxp_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int ret;
++
++ ret = videobuf_mmap_mapper(&pxp->s0_vbq, vma);
++
++ return ret;
++}
++
++static const struct v4l2_file_operations pxp_fops = {
++ .owner = THIS_MODULE,
++ .open = pxp_open,
++ .release = pxp_close,
++ .unlocked_ioctl = video_ioctl2,
++ .mmap = pxp_mmap,
++};
++
++static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
++ .vidioc_querycap = pxp_querycap,
++
++ .vidioc_reqbufs = pxp_reqbufs,
++ .vidioc_querybuf = pxp_querybuf,
++ .vidioc_qbuf = pxp_qbuf,
++ .vidioc_dqbuf = pxp_dqbuf,
++
++ .vidioc_streamon = pxp_streamon,
++ .vidioc_streamoff = pxp_streamoff,
++
++ .vidioc_enum_output = pxp_enumoutput,
++ .vidioc_g_output = pxp_g_output,
++ .vidioc_s_output = pxp_s_output,
++
++ .vidioc_enum_fmt_vid_out = pxp_enum_fmt_video_output,
++ .vidioc_try_fmt_vid_out = pxp_try_fmt_video_output,
++ .vidioc_g_fmt_vid_out = pxp_g_fmt_video_output,
++ .vidioc_s_fmt_vid_out = pxp_s_fmt_video_output,
++
++ .vidioc_try_fmt_vid_out_overlay = pxp_try_fmt_output_overlay,
++ .vidioc_g_fmt_vid_out_overlay = pxp_g_fmt_output_overlay,
++ .vidioc_s_fmt_vid_out_overlay = pxp_s_fmt_output_overlay,
++
++ .vidioc_g_fbuf = pxp_g_fbuf,
++ .vidioc_s_fbuf = pxp_s_fbuf,
++
++ .vidioc_g_crop = pxp_g_crop,
++ .vidioc_s_crop = pxp_s_crop,
++
++ .vidioc_queryctrl = pxp_queryctrl,
++ .vidioc_g_ctrl = pxp_g_ctrl,
++ .vidioc_s_ctrl = pxp_s_ctrl,
++};
++
++static const struct video_device pxp_template = {
++ .name = "PxP",
++ .vfl_type = V4L2_CAP_VIDEO_OUTPUT |
++ V4L2_CAP_VIDEO_OVERLAY |
++ V4L2_CAP_STREAMING,
++ .vfl_dir = VFL_DIR_TX,
++ .fops = &pxp_fops,
++ .release = pxp_release,
++ .minor = -1,
++ .ioctl_ops = &pxp_ioctl_ops,
++};
++
++static const struct of_device_id imx_pxpv4l2_dt_ids[] = {
++ { .compatible = "fsl,imx6sl-pxp-v4l2", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_pxpv4l2_dt_ids);
++
++static int pxp_probe(struct platform_device *pdev)
++{
++ struct pxps *pxp;
++ int err = 0;
++
++ pxp = kzalloc(sizeof(*pxp), GFP_KERNEL);
++ if (!pxp) {
++ dev_err(&pdev->dev, "failed to allocate control object\n");
++ err = -ENOMEM;
++ goto exit;
++ }
++
++ dev_set_drvdata(&pdev->dev, pxp);
++
++ INIT_LIST_HEAD(&pxp->outq);
++ spin_lock_init(&pxp->lock);
++ mutex_init(&pxp->mutex);
++
++ pxp->pdev = pdev;
++
++ pxp->vdev = video_device_alloc();
++ if (!pxp->vdev) {
++ dev_err(&pdev->dev, "video_device_alloc() failed\n");
++ err = -ENOMEM;
++ goto freeirq;
++ }
++
++ memcpy(pxp->vdev, &pxp_template, sizeof(pxp_template));
++ video_set_drvdata(pxp->vdev, pxp);
++
++ err = video_register_device(pxp->vdev, VFL_TYPE_GRABBER, video_nr);
++ if (err) {
++ dev_err(&pdev->dev, "failed to register video device\n");
++ goto freevdev;
++ }
++
++ dev_info(&pdev->dev, "initialized\n");
++
++exit:
++ return err;
++
++freevdev:
++ video_device_release(pxp->vdev);
++
++freeirq:
++ kfree(pxp);
++
++ return err;
++}
++
++static int pxp_remove(struct platform_device *pdev)
++{
++ struct pxps *pxp = platform_get_drvdata(pdev);
++
++ video_unregister_device(pxp->vdev);
++ video_device_release(pxp->vdev);
++
++ kfree(pxp);
++
++ return 0;
++}
++
++static struct platform_driver pxp_driver = {
++ .driver = {
++ .name = PXP_DRIVER_NAME,
++ .of_match_table = of_match_ptr(imx_pxpv4l2_dt_ids),
++ },
++ .probe = pxp_probe,
++ .remove = pxp_remove,
++};
++
++module_platform_driver(pxp_driver);
++
++module_param(video_nr, int, 0444);
++MODULE_DESCRIPTION("MXC PxP V4L2 driver");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/output/mxc_pxp_v4l2.h linux-linaro-stable-mx6/drivers/media/platform/mxc/output/mxc_pxp_v4l2.h
+--- linux-3.10.30.orig/drivers/media/platform/mxc/output/mxc_pxp_v4l2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/output/mxc_pxp_v4l2.h 2014-05-15 20:33:57.142007696 +0200
+@@ -0,0 +1,83 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * Based on STMP378X PxP driver
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++#ifndef _MXC_PXP_V4L2_H
++#define _MXC_PXP_V4L2_H
++
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++
++struct pxp_buffer {
++ /* Must be first! */
++ struct videobuf_buffer vb;
++
++ /* One descriptor per scatterlist (per frame) */
++ struct dma_async_tx_descriptor *txd;
++
++ struct scatterlist sg[3];
++};
++
++struct pxps {
++ struct platform_device *pdev;
++
++ spinlock_t lock;
++ struct mutex mutex;
++ int users;
++
++ struct video_device *vdev;
++
++ struct videobuf_queue s0_vbq;
++ struct pxp_buffer *active;
++ struct list_head outq;
++ struct pxp_channel *pxp_channel[1]; /* We need 1 channel */
++ struct pxp_config_data pxp_conf;
++
++ int output;
++ u32 *outb;
++ dma_addr_t outb_phys;
++ u32 outb_size;
++
++ /* Current S0 configuration */
++ struct pxp_data_format *s0_fmt;
++
++ struct fb_info *fbi;
++ struct v4l2_framebuffer fb;
++
++ /* Output overlay support */
++ int overlay_state;
++ int global_alpha_state;
++ u8 global_alpha;
++ int s1_chromakey_state;
++ u32 s1_chromakey;
++
++ int fb_blank;
++};
++
++struct pxp_data_format {
++ char *name;
++ unsigned int bpp;
++ u32 fourcc;
++ enum v4l2_colorspace colorspace;
++};
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/media/platform/mxc/output/mxc_vout.c linux-linaro-stable-mx6/drivers/media/platform/mxc/output/mxc_vout.c
+--- linux-3.10.30.orig/drivers/media/platform/mxc/output/mxc_vout.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/platform/mxc/output/mxc_vout.c 2014-05-15 20:33:57.142007696 +0200
+@@ -0,0 +1,2265 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/console.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/mxc_v4l2.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/types.h>
++#include <linux/videodev2.h>
++#include <linux/vmalloc.h>
++
++#include <media/videobuf-dma-contig.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++
++#define UYVY_BLACK (0x00800080)
++#define RGB_BLACK (0x0)
++#define UV_BLACK (0x80)
++#define Y_BLACK (0x0)
++
++#define MAX_FB_NUM 6
++#define FB_BUFS 3
++#define VDOA_FB_BUFS (FB_BUFS - 1)
++#define VALID_HEIGHT_1080P (1080)
++#define FRAME_HEIGHT_1080P (1088)
++#define FRAME_WIDTH_1080P (1920)
++#define CHECK_TILED_1080P_DISPLAY(vout) \
++ ((((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12) || \
++ ((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12F)) &&\
++ ((vout)->task.input.width == FRAME_WIDTH_1080P) && \
++ ((vout)->task.input.height == FRAME_HEIGHT_1080P) && \
++ ((vout)->task.input.crop.w == FRAME_WIDTH_1080P) && \
++ (((vout)->task.input.crop.h == FRAME_HEIGHT_1080P) || \
++ ((vout)->task.input.crop.h == VALID_HEIGHT_1080P)) && \
++ ((vout)->task.output.width == FRAME_WIDTH_1080P) && \
++ ((vout)->task.output.height == VALID_HEIGHT_1080P) && \
++ ((vout)->task.output.crop.w == FRAME_WIDTH_1080P) && \
++ ((vout)->task.output.crop.h == VALID_HEIGHT_1080P))
++#define CHECK_TILED_1080P_STREAM(vout) \
++ ((((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12) || \
++ ((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12F)) &&\
++ ((vout)->task.input.width == FRAME_WIDTH_1080P) && \
++ ((vout)->task.input.crop.w == FRAME_WIDTH_1080P) && \
++ ((vout)->task.input.height == FRAME_HEIGHT_1080P) && \
++ ((vout)->task.input.crop.h == FRAME_HEIGHT_1080P))
++#define IS_PLANAR_PIXEL_FORMAT(format) \
++ (format == IPU_PIX_FMT_NV12 || \
++ format == IPU_PIX_FMT_YUV420P2 || \
++ format == IPU_PIX_FMT_YUV420P || \
++ format == IPU_PIX_FMT_YVU420P || \
++ format == IPU_PIX_FMT_YUV422P || \
++ format == IPU_PIX_FMT_YVU422P || \
++ format == IPU_PIX_FMT_YUV444P)
++
++#define NSEC_PER_FRAME_30FPS (33333333)
++
++struct mxc_vout_fb {
++ char *name;
++ int ipu_id;
++ struct v4l2_rect crop_bounds;
++ unsigned int disp_fmt;
++ bool disp_support_csc;
++ bool disp_support_windows;
++};
++
++struct dma_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ size_t size;
++};
++
++struct mxc_vout_output {
++ int open_cnt;
++ struct fb_info *fbi;
++ unsigned long fb_smem_start;
++ unsigned long fb_smem_len;
++ struct video_device *vfd;
++ struct mutex mutex;
++ struct mutex task_lock;
++ enum v4l2_buf_type type;
++
++ struct videobuf_queue vbq;
++ spinlock_t vbq_lock;
++
++ struct list_head queue_list;
++ struct list_head active_list;
++
++ struct v4l2_rect crop_bounds;
++ unsigned int disp_fmt;
++ struct mxcfb_pos win_pos;
++ bool disp_support_windows;
++ bool disp_support_csc;
++
++ bool fmt_init;
++ bool release;
++ bool linear_bypass_pp;
++ bool vdoa_1080p;
++ bool tiled_bypass_pp;
++ struct v4l2_rect in_rect;
++ struct ipu_task task;
++ struct ipu_task vdoa_task;
++ struct dma_mem vdoa_work;
++ struct dma_mem vdoa_output[VDOA_FB_BUFS];
++
++ bool timer_stop;
++ struct hrtimer timer;
++ struct workqueue_struct *v4l_wq;
++ struct work_struct disp_work;
++ unsigned long frame_count;
++ unsigned long vdi_frame_cnt;
++ ktime_t start_ktime;
++
++ int ctrl_rotate;
++ int ctrl_vflip;
++ int ctrl_hflip;
++
++ dma_addr_t disp_bufs[FB_BUFS];
++
++ struct videobuf_buffer *pre1_vb;
++ struct videobuf_buffer *pre2_vb;
++};
++
++struct mxc_vout_dev {
++ struct device *dev;
++ struct v4l2_device v4l2_dev;
++ struct mxc_vout_output *out[MAX_FB_NUM];
++ int out_num;
++};
++
++/* Driver Configuration macros */
++#define VOUT_NAME "mxc_vout"
++
++/* Variables configurable through module params*/
++static int debug;
++static int vdi_rate_double;
++static int video_nr = 16;
++
++/* Module parameters */
++module_param(video_nr, int, S_IRUGO);
++MODULE_PARM_DESC(video_nr, "video device numbers");
++module_param(debug, int, 0600);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++module_param(vdi_rate_double, int, 0600);
++MODULE_PARM_DESC(vdi_rate_double, "vdi frame rate double on/off");
++
++static const struct v4l2_fmtdesc mxc_formats[] = {
++ {
++ .description = "RGB565",
++ .pixelformat = V4L2_PIX_FMT_RGB565,
++ },
++ {
++ .description = "BGR24",
++ .pixelformat = V4L2_PIX_FMT_BGR24,
++ },
++ {
++ .description = "RGB24",
++ .pixelformat = V4L2_PIX_FMT_RGB24,
++ },
++ {
++ .description = "RGB32",
++ .pixelformat = V4L2_PIX_FMT_RGB32,
++ },
++ {
++ .description = "BGR32",
++ .pixelformat = V4L2_PIX_FMT_BGR32,
++ },
++ {
++ .description = "NV12",
++ .pixelformat = V4L2_PIX_FMT_NV12,
++ },
++ {
++ .description = "UYVY",
++ .pixelformat = V4L2_PIX_FMT_UYVY,
++ },
++ {
++ .description = "YUYV",
++ .pixelformat = V4L2_PIX_FMT_YUYV,
++ },
++ {
++ .description = "YUV422 planar",
++ .pixelformat = V4L2_PIX_FMT_YUV422P,
++ },
++ {
++ .description = "YUV444",
++ .pixelformat = V4L2_PIX_FMT_YUV444,
++ },
++ {
++ .description = "YUV420",
++ .pixelformat = V4L2_PIX_FMT_YUV420,
++ },
++ {
++ .description = "YVU420",
++ .pixelformat = V4L2_PIX_FMT_YVU420,
++ },
++ {
++ .description = "TILED NV12P",
++ .pixelformat = IPU_PIX_FMT_TILED_NV12,
++ },
++ {
++ .description = "TILED NV12F",
++ .pixelformat = IPU_PIX_FMT_TILED_NV12F,
++ },
++ {
++ .description = "YUV444 planar",
++ .pixelformat = IPU_PIX_FMT_YUV444P,
++ },
++};
++
++#define NUM_MXC_VOUT_FORMATS (ARRAY_SIZE(mxc_formats))
++
++#define DEF_INPUT_WIDTH 320
++#define DEF_INPUT_HEIGHT 240
++
++static int mxc_vidioc_streamoff(struct file *file, void *fh,
++ enum v4l2_buf_type i);
++
++static struct mxc_vout_fb g_fb_setting[MAX_FB_NUM];
++static int config_disp_output(struct mxc_vout_output *vout);
++static void release_disp_output(struct mxc_vout_output *vout);
++
++static unsigned int get_frame_size(struct mxc_vout_output *vout)
++{
++ unsigned int size;
++
++ if (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format)
++ size = TILED_NV12_FRAME_SIZE(vout->task.input.width,
++ vout->task.input.height);
++ else if (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format) {
++ size = TILED_NV12_FRAME_SIZE(vout->task.input.width,
++ vout->task.input.height/2);
++ size *= 2;
++ } else
++ size = vout->task.input.width * vout->task.input.height *
++ fmt_to_bpp(vout->task.input.format)/8;
++
++ return size;
++}
++
++static void free_dma_buf(struct mxc_vout_output *vout, struct dma_mem *buf)
++{
++ dma_free_coherent(vout->vbq.dev, buf->size, buf->vaddr, buf->paddr);
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "free dma size:0x%x, paddr:0x%x\n",
++ buf->size, buf->paddr);
++ memset(buf, 0, sizeof(*buf));
++}
++
++static int alloc_dma_buf(struct mxc_vout_output *vout, struct dma_mem *buf)
++{
++
++ buf->vaddr = dma_alloc_coherent(vout->vbq.dev, buf->size, &buf->paddr,
++ GFP_DMA | GFP_KERNEL);
++ if (!buf->vaddr) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "cannot get dma buf size:0x%x\n", buf->size);
++ return -ENOMEM;
++ }
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "alloc dma buf size:0x%x, paddr:0x%x\n", buf->size, buf->paddr);
++ return 0;
++}
++
++static ipu_channel_t get_ipu_channel(struct fb_info *fbi)
++{
++ ipu_channel_t ipu_ch = CHAN_NONE;
++ mm_segment_t old_fs;
++
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN,
++ (unsigned long)&ipu_ch);
++ set_fs(old_fs);
++ }
++
++ return ipu_ch;
++}
++
++static unsigned int get_ipu_fmt(struct fb_info *fbi)
++{
++ mm_segment_t old_fs;
++ unsigned int fb_fmt;
++
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_DIFMT,
++ (unsigned long)&fb_fmt);
++ set_fs(old_fs);
++ }
++
++ return fb_fmt;
++}
++
++static void update_display_setting(void)
++{
++ int i;
++ struct fb_info *fbi;
++ struct v4l2_rect bg_crop_bounds[2];
++
++ for (i = 0; i < num_registered_fb; i++) {
++ fbi = registered_fb[i];
++
++ memset(&g_fb_setting[i], 0, sizeof(struct mxc_vout_fb));
++
++ if (!strncmp(fbi->fix.id, "DISP3", 5))
++ g_fb_setting[i].ipu_id = 0;
++ else
++ g_fb_setting[i].ipu_id = 1;
++
++ g_fb_setting[i].name = fbi->fix.id;
++ g_fb_setting[i].crop_bounds.left = 0;
++ g_fb_setting[i].crop_bounds.top = 0;
++ g_fb_setting[i].crop_bounds.width = fbi->var.xres;
++ g_fb_setting[i].crop_bounds.height = fbi->var.yres;
++ g_fb_setting[i].disp_fmt = get_ipu_fmt(fbi);
++
++ if (get_ipu_channel(fbi) == MEM_BG_SYNC) {
++ bg_crop_bounds[g_fb_setting[i].ipu_id] =
++ g_fb_setting[i].crop_bounds;
++ g_fb_setting[i].disp_support_csc = true;
++ } else if (get_ipu_channel(fbi) == MEM_FG_SYNC) {
++ g_fb_setting[i].disp_support_csc = true;
++ g_fb_setting[i].disp_support_windows = true;
++ }
++ }
++
++ for (i = 0; i < num_registered_fb; i++) {
++ fbi = registered_fb[i];
++
++ if (get_ipu_channel(fbi) == MEM_FG_SYNC)
++ g_fb_setting[i].crop_bounds =
++ bg_crop_bounds[g_fb_setting[i].ipu_id];
++ }
++}
++
++/* called after g_fb_setting filled by update_display_setting */
++static int update_setting_from_fbi(struct mxc_vout_output *vout,
++ struct fb_info *fbi)
++{
++ int i;
++ bool found = false;
++
++ for (i = 0; i < MAX_FB_NUM; i++) {
++ if (g_fb_setting[i].name) {
++ if (!strcmp(fbi->fix.id, g_fb_setting[i].name)) {
++ vout->crop_bounds = g_fb_setting[i].crop_bounds;
++ vout->disp_fmt = g_fb_setting[i].disp_fmt;
++ vout->disp_support_csc =
++ g_fb_setting[i].disp_support_csc;
++ vout->disp_support_windows =
++ g_fb_setting[i].disp_support_windows;
++ found = true;
++ break;
++ }
++ }
++ }
++
++ if (!found) {
++ v4l2_err(vout->vfd->v4l2_dev, "can not find output\n");
++ return -EINVAL;
++ }
++ strlcpy(vout->vfd->name, fbi->fix.id, sizeof(vout->vfd->name));
++
++ memset(&vout->task, 0, sizeof(struct ipu_task));
++
++ vout->task.input.width = DEF_INPUT_WIDTH;
++ vout->task.input.height = DEF_INPUT_HEIGHT;
++ vout->task.input.crop.pos.x = 0;
++ vout->task.input.crop.pos.y = 0;
++ vout->task.input.crop.w = DEF_INPUT_WIDTH;
++ vout->task.input.crop.h = DEF_INPUT_HEIGHT;
++
++ vout->task.output.width = vout->crop_bounds.width;
++ vout->task.output.height = vout->crop_bounds.height;
++ vout->task.output.crop.pos.x = 0;
++ vout->task.output.crop.pos.y = 0;
++ vout->task.output.crop.w = vout->crop_bounds.width;
++ vout->task.output.crop.h = vout->crop_bounds.height;
++ if (colorspaceofpixel(vout->disp_fmt) == YUV_CS)
++ vout->task.output.format = IPU_PIX_FMT_UYVY;
++ else
++ vout->task.output.format = IPU_PIX_FMT_RGB565;
++
++ return 0;
++}
++
++static inline unsigned long get_jiffies(struct timeval *t)
++{
++ struct timeval cur;
++
++ if (t->tv_usec >= 1000000) {
++ t->tv_sec += t->tv_usec / 1000000;
++ t->tv_usec = t->tv_usec % 1000000;
++ }
++
++ do_gettimeofday(&cur);
++ if ((t->tv_sec < cur.tv_sec)
++ || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec)))
++ return jiffies;
++
++ if (t->tv_usec < cur.tv_usec) {
++ cur.tv_sec = t->tv_sec - cur.tv_sec - 1;
++ cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec;
++ } else {
++ cur.tv_sec = t->tv_sec - cur.tv_sec;
++ cur.tv_usec = t->tv_usec - cur.tv_usec;
++ }
++
++ return jiffies + timeval_to_jiffies(&cur);
++}
++
++static bool deinterlace_3_field(struct mxc_vout_output *vout)
++{
++ return (vout->task.input.deinterlace.enable &&
++ (vout->task.input.deinterlace.motion != HIGH_MOTION));
++}
++
++static int set_field_fmt(struct mxc_vout_output *vout, enum v4l2_field field)
++{
++ struct ipu_deinterlace *deinterlace = &vout->task.input.deinterlace;
++
++ switch (field) {
++ /* Images are in progressive format, not interlaced */
++ case V4L2_FIELD_NONE:
++ case V4L2_FIELD_ANY:
++ deinterlace->enable = false;
++ deinterlace->field_fmt = 0;
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "Progressive frame.\n");
++ break;
++ case V4L2_FIELD_INTERLACED_TB:
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "Enable deinterlace TB.\n");
++ deinterlace->enable = true;
++ deinterlace->field_fmt = IPU_DEINTERLACE_FIELD_TOP;
++ break;
++ case V4L2_FIELD_INTERLACED_BT:
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "Enable deinterlace BT.\n");
++ deinterlace->enable = true;
++ deinterlace->field_fmt = IPU_DEINTERLACE_FIELD_BOTTOM;
++ break;
++ default:
++ v4l2_err(vout->vfd->v4l2_dev,
++ "field format:%d not supported yet!\n", field);
++ return -EINVAL;
++ }
++
++ if (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format) {
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "tiled fmt enable deinterlace.\n");
++ deinterlace->enable = true;
++ }
++
++ if (deinterlace->enable && vdi_rate_double)
++ deinterlace->field_fmt |= IPU_DEINTERLACE_RATE_EN;
++
++ return 0;
++}
++
++static bool is_pp_bypass(struct mxc_vout_output *vout)
++{
++ if ((IPU_PIX_FMT_TILED_NV12 == vout->task.input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format))
++ return false;
++ if ((vout->task.input.width == vout->task.output.width) &&
++ (vout->task.input.height == vout->task.output.height) &&
++ (vout->task.input.crop.w == vout->task.output.crop.w) &&
++ (vout->task.input.crop.h == vout->task.output.crop.h) &&
++ (vout->task.output.rotate < IPU_ROTATE_HORIZ_FLIP) &&
++ !vout->task.input.deinterlace.enable) {
++ if (vout->disp_support_csc)
++ return true;
++ else if (!need_csc(vout->task.input.format, vout->disp_fmt))
++ return true;
++ /*
++ * input crop show to full output which can show based on
++ * xres_virtual/yres_virtual
++ */
++ } else if ((vout->task.input.crop.w == vout->task.output.crop.w) &&
++ (vout->task.output.crop.w == vout->task.output.width) &&
++ (vout->task.input.crop.h == vout->task.output.crop.h) &&
++ (vout->task.output.crop.h ==
++ vout->task.output.height) &&
++ (vout->task.output.rotate < IPU_ROTATE_HORIZ_FLIP) &&
++ !vout->task.input.deinterlace.enable) {
++ if (vout->disp_support_csc)
++ return true;
++ else if (!need_csc(vout->task.input.format, vout->disp_fmt))
++ return true;
++ }
++ return false;
++}
++
++static void setup_buf_timer(struct mxc_vout_output *vout,
++ struct videobuf_buffer *vb)
++{
++ ktime_t expiry_time, now;
++
++ /* if timestamp is 0, then default to 30fps */
++ if ((vb->ts.tv_sec == 0) && (vb->ts.tv_usec == 0))
++ expiry_time = ktime_add_ns(vout->start_ktime,
++ NSEC_PER_FRAME_30FPS * vout->frame_count);
++ else
++ expiry_time = timeval_to_ktime(vb->ts);
++
++ now = hrtimer_cb_get_time(&vout->timer);
++ if ((now.tv64 > expiry_time.tv64)) {
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "warning: timer timeout already expired.\n");
++ expiry_time = now;
++ }
++
++ hrtimer_start(&vout->timer, expiry_time, HRTIMER_MODE_ABS);
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "timer handler next "
++ "schedule: %lldnsecs\n", expiry_time.tv64);
++}
++
++static int show_buf(struct mxc_vout_output *vout, int idx,
++ struct ipu_pos *ipos)
++{
++ struct fb_info *fbi = vout->fbi;
++ struct fb_var_screeninfo var;
++ int ret;
++ u32 fb_base = 0;
++
++ memcpy(&var, &fbi->var, sizeof(var));
++
++ if (vout->linear_bypass_pp || vout->tiled_bypass_pp) {
++ /*
++ * crack fb base
++ * NOTE: should not do other fb operation during v4l2
++ */
++ console_lock();
++ fb_base = fbi->fix.smem_start;
++ fbi->fix.smem_start = vout->task.output.paddr;
++ fbi->var.yoffset = ipos->y + 1;
++ var.xoffset = ipos->x;
++ var.yoffset = ipos->y;
++ var.vmode |= FB_VMODE_YWRAP;
++ ret = fb_pan_display(fbi, &var);
++ fbi->fix.smem_start = fb_base;
++ console_unlock();
++ } else {
++ console_lock();
++ var.yoffset = idx * fbi->var.yres;
++ var.vmode &= ~FB_VMODE_YWRAP;
++ ret = fb_pan_display(fbi, &var);
++ console_unlock();
++ }
++
++ return ret;
++}
++
++static void disp_work_func(struct work_struct *work)
++{
++ struct mxc_vout_output *vout =
++ container_of(work, struct mxc_vout_output, disp_work);
++ struct videobuf_queue *q = &vout->vbq;
++ struct videobuf_buffer *vb, *vb_next = NULL;
++ unsigned long flags = 0;
++ struct ipu_pos ipos;
++ int ret = 0;
++ u32 in_fmt = 0;
++ u32 vdi_cnt = 0;
++ u32 vdi_frame;
++ u32 index = 0;
++ u32 ocrop_h = 0;
++ u32 o_height = 0;
++ u32 tiled_interlaced = 0;
++ bool tiled_fmt = false;
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work begin one frame\n");
++
++ spin_lock_irqsave(q->irqlock, flags);
++
++ if (list_empty(&vout->active_list)) {
++ v4l2_warn(vout->vfd->v4l2_dev,
++ "no entry in active_list, should not be here\n");
++ spin_unlock_irqrestore(q->irqlock, flags);
++ return;
++ }
++
++ vb = list_first_entry(&vout->active_list,
++ struct videobuf_buffer, queue);
++ ret = set_field_fmt(vout, vb->field);
++ if (ret < 0) {
++ spin_unlock_irqrestore(q->irqlock, flags);
++ return;
++ }
++ if (deinterlace_3_field(vout)) {
++ if (list_is_singular(&vout->active_list)) {
++ if (list_empty(&vout->queue_list)) {
++ vout->timer_stop = true;
++ spin_unlock_irqrestore(q->irqlock, flags);
++ v4l2_warn(vout->vfd->v4l2_dev,
++ "no enough entry for 3 fields "
++ "deinterlacer\n");
++ return;
++ }
++
++ /*
++ * We need to use the next vb even if it is
++ * not on the active list.
++ */
++ vb_next = list_first_entry(&vout->queue_list,
++ struct videobuf_buffer, queue);
++ } else
++ vb_next = list_first_entry(vout->active_list.next,
++ struct videobuf_buffer, queue);
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "cur field_fmt:%d, next field_fmt:%d.\n",
++ vb->field, vb_next->field);
++ /* repeat the last field during field format changing */
++ if ((vb->field != vb_next->field) &&
++ (vb_next->field != V4L2_FIELD_NONE))
++ vb_next = vb;
++ }
++
++ spin_unlock_irqrestore(q->irqlock, flags);
++
++vdi_frame_rate_double:
++ mutex_lock(&vout->task_lock);
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "v4l2 frame_cnt:%ld, vb_field:%d, fmt:%d\n",
++ vout->frame_count, vb->field,
++ vout->task.input.deinterlace.field_fmt);
++ if (vb->memory == V4L2_MEMORY_USERPTR)
++ vout->task.input.paddr = vb->baddr;
++ else
++ vout->task.input.paddr = videobuf_to_dma_contig(vb);
++
++ if (vout->task.input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN)
++ index = vout->vdi_frame_cnt % FB_BUFS;
++ else
++ index = vout->frame_count % FB_BUFS;
++ if (vout->linear_bypass_pp) {
++ vout->task.output.paddr = vout->task.input.paddr;
++ ipos.x = vout->task.input.crop.pos.x;
++ ipos.y = vout->task.input.crop.pos.y;
++ } else {
++ if (deinterlace_3_field(vout)) {
++ if (vb->memory == V4L2_MEMORY_USERPTR)
++ vout->task.input.paddr_n = vb_next->baddr;
++ else
++ vout->task.input.paddr_n =
++ videobuf_to_dma_contig(vb_next);
++ }
++ vout->task.output.paddr = vout->disp_bufs[index];
++ if (vout->vdoa_1080p) {
++ o_height = vout->task.output.height;
++ ocrop_h = vout->task.output.crop.h;
++ vout->task.output.height = FRAME_HEIGHT_1080P;
++ vout->task.output.crop.h = FRAME_HEIGHT_1080P;
++ }
++ tiled_fmt =
++ (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format);
++ if (vout->tiled_bypass_pp) {
++ ipos.x = vout->task.input.crop.pos.x;
++ ipos.y = vout->task.input.crop.pos.y;
++ } else if (tiled_fmt) {
++ vout->vdoa_task.input.paddr = vout->task.input.paddr;
++ if (deinterlace_3_field(vout))
++ vout->vdoa_task.input.paddr_n =
++ vout->task.input.paddr_n;
++ vout->vdoa_task.output.paddr = vout->vdoa_work.paddr;
++ ret = ipu_queue_task(&vout->vdoa_task);
++ if (ret < 0) {
++ mutex_unlock(&vout->task_lock);
++ goto err;
++ }
++ vout->task.input.paddr = vout->vdoa_task.output.paddr;
++ in_fmt = vout->task.input.format;
++ vout->task.input.format = vout->vdoa_task.output.format;
++ if (vout->task.input.deinterlace.enable) {
++ tiled_interlaced = 1;
++ vout->task.input.deinterlace.enable = 0;
++ }
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "tiled queue task\n");
++ }
++ ret = ipu_queue_task(&vout->task);
++ if ((!vout->tiled_bypass_pp) && tiled_fmt)
++ vout->task.input.format = in_fmt;
++ if (tiled_interlaced)
++ vout->task.input.deinterlace.enable = 1;
++ if (ret < 0) {
++ mutex_unlock(&vout->task_lock);
++ goto err;
++ }
++ if (vout->vdoa_1080p) {
++ vout->task.output.crop.h = ocrop_h;
++ vout->task.output.height = o_height;
++ }
++ }
++
++ mutex_unlock(&vout->task_lock);
++
++ ret = show_buf(vout, index, &ipos);
++ if (ret < 0)
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "show buf with ret %d\n", ret);
++
++ if (vout->task.input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN) {
++ vdi_frame = vout->task.input.deinterlace.field_fmt
++ & IPU_DEINTERLACE_RATE_FRAME1;
++ if (vdi_frame)
++ vout->task.input.deinterlace.field_fmt &=
++ ~IPU_DEINTERLACE_RATE_FRAME1;
++ else
++ vout->task.input.deinterlace.field_fmt |=
++ IPU_DEINTERLACE_RATE_FRAME1;
++ vout->vdi_frame_cnt++;
++ vdi_cnt++;
++ if (vdi_cnt < IPU_DEINTERLACE_MAX_FRAME)
++ goto vdi_frame_rate_double;
++ }
++ spin_lock_irqsave(q->irqlock, flags);
++
++ list_del(&vb->queue);
++
++ /*
++ * The videobuf before the last one has been shown. Set
++ * VIDEOBUF_DONE state here to avoid tearing issue in ic bypass
++ * case, which makes sure a buffer being shown will not be
++ * dequeued to be overwritten. It also brings side-effect that
++ * the last 2 buffers can not be dequeued correctly, apps need
++ * to take care of it.
++ */
++ if (vout->pre2_vb) {
++ vout->pre2_vb->state = VIDEOBUF_DONE;
++ wake_up_interruptible(&vout->pre2_vb->done);
++ vout->pre2_vb = NULL;
++ }
++
++ if (vout->linear_bypass_pp) {
++ vout->pre2_vb = vout->pre1_vb;
++ vout->pre1_vb = vb;
++ } else {
++ if (vout->pre1_vb) {
++ vout->pre1_vb->state = VIDEOBUF_DONE;
++ wake_up_interruptible(&vout->pre1_vb->done);
++ vout->pre1_vb = NULL;
++ }
++ vb->state = VIDEOBUF_DONE;
++ wake_up_interruptible(&vb->done);
++ }
++
++ vout->frame_count++;
++
++ /* pick next queue buf to setup timer */
++ if (list_empty(&vout->queue_list))
++ vout->timer_stop = true;
++ else {
++ vb = list_first_entry(&vout->queue_list,
++ struct videobuf_buffer, queue);
++ setup_buf_timer(vout, vb);
++ }
++
++ spin_unlock_irqrestore(q->irqlock, flags);
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work finish one frame\n");
++
++ return;
++err:
++ v4l2_err(vout->vfd->v4l2_dev, "display work fail ret = %d\n", ret);
++ vout->timer_stop = true;
++ vb->state = VIDEOBUF_ERROR;
++ return;
++}
++
++static enum hrtimer_restart mxc_vout_timer_handler(struct hrtimer *timer)
++{
++ struct mxc_vout_output *vout = container_of(timer,
++ struct mxc_vout_output,
++ timer);
++ struct videobuf_queue *q = &vout->vbq;
++ struct videobuf_buffer *vb;
++ unsigned long flags = 0;
++
++ spin_lock_irqsave(q->irqlock, flags);
++
++ /*
++ * put first queued entry into active, if previous entry did not
++ * finish, setup current entry's timer again.
++ */
++ if (list_empty(&vout->queue_list)) {
++ spin_unlock_irqrestore(q->irqlock, flags);
++ return HRTIMER_NORESTART;
++ }
++
++ /* move videobuf from queued list to active list */
++ vb = list_first_entry(&vout->queue_list,
++ struct videobuf_buffer, queue);
++ list_del(&vb->queue);
++ list_add_tail(&vb->queue, &vout->active_list);
++
++ if (queue_work(vout->v4l_wq, &vout->disp_work) == 0) {
++ v4l2_warn(vout->vfd->v4l2_dev,
++ "disp work was in queue already, queue buf again next time\n");
++ list_del(&vb->queue);
++ list_add(&vb->queue, &vout->queue_list);
++ spin_unlock_irqrestore(q->irqlock, flags);
++ return HRTIMER_NORESTART;
++ }
++
++ vb->state = VIDEOBUF_ACTIVE;
++
++ spin_unlock_irqrestore(q->irqlock, flags);
++
++ return HRTIMER_NORESTART;
++}
++
++/* Video buffer call backs */
++
++/*
++ * Buffer setup function is called by videobuf layer when REQBUF ioctl is
++ * called. This is used to setup buffers and return size and count of
++ * buffers allocated. After the call to this buffer, videobuf layer will
++ * setup buffer queue depending on the size and count of buffers
++ */
++static int mxc_vout_buffer_setup(struct videobuf_queue *q, unsigned int *count,
++ unsigned int *size)
++{
++ struct mxc_vout_output *vout = q->priv_data;
++ unsigned int frame_size;
++
++ if (!vout)
++ return -EINVAL;
++
++ if (V4L2_BUF_TYPE_VIDEO_OUTPUT != q->type)
++ return -EINVAL;
++
++ frame_size = get_frame_size(vout);
++ *size = PAGE_ALIGN(frame_size);
++
++ return 0;
++}
++
++/*
++ * This function will be called when VIDIOC_QBUF ioctl is called.
++ * It prepare buffers before give out for the display. This function
++ * converts user space virtual address into physical address if userptr memory
++ * exchange mechanism is used.
++ */
++static int mxc_vout_buffer_prepare(struct videobuf_queue *q,
++ struct videobuf_buffer *vb,
++ enum v4l2_field field)
++{
++ vb->state = VIDEOBUF_PREPARED;
++ return 0;
++}
++
++/*
++ * Buffer queue funtion will be called from the videobuf layer when _QBUF
++ * ioctl is called. It is used to enqueue buffer, which is ready to be
++ * displayed.
++ * This function is protected by q->irqlock.
++ */
++static void mxc_vout_buffer_queue(struct videobuf_queue *q,
++ struct videobuf_buffer *vb)
++{
++ struct mxc_vout_output *vout = q->priv_data;
++ struct videobuf_buffer *active_vb;
++
++ list_add_tail(&vb->queue, &vout->queue_list);
++ vb->state = VIDEOBUF_QUEUED;
++
++ if (vout->timer_stop) {
++ if (deinterlace_3_field(vout) &&
++ !list_empty(&vout->active_list)) {
++ active_vb = list_first_entry(&vout->active_list,
++ struct videobuf_buffer, queue);
++ setup_buf_timer(vout, active_vb);
++ } else {
++ setup_buf_timer(vout, vb);
++ }
++ vout->timer_stop = false;
++ }
++}
++
++/*
++ * Buffer release function is called from videobuf layer to release buffer
++ * which are already allocated
++ */
++static void mxc_vout_buffer_release(struct videobuf_queue *q,
++ struct videobuf_buffer *vb)
++{
++ vb->state = VIDEOBUF_NEEDS_INIT;
++}
++
++static int mxc_vout_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ int ret;
++ struct mxc_vout_output *vout = file->private_data;
++
++ if (!vout)
++ return -ENODEV;
++
++ ret = videobuf_mmap_mapper(&vout->vbq, vma);
++ if (ret < 0)
++ v4l2_err(vout->vfd->v4l2_dev,
++ "offset invalid [offset=0x%lx]\n",
++ (vma->vm_pgoff << PAGE_SHIFT));
++
++ return ret;
++}
++
++static int mxc_vout_release(struct file *file)
++{
++ unsigned int ret = 0;
++ struct videobuf_queue *q;
++ struct mxc_vout_output *vout = file->private_data;
++
++ if (!vout)
++ return 0;
++
++ if (--vout->open_cnt == 0) {
++ q = &vout->vbq;
++ if (q->streaming)
++ mxc_vidioc_streamoff(file, vout, vout->type);
++ else {
++ release_disp_output(vout);
++ videobuf_queue_cancel(q);
++ }
++ destroy_workqueue(vout->v4l_wq);
++ ret = videobuf_mmap_free(q);
++ }
++
++ return ret;
++}
++
++static int mxc_vout_open(struct file *file)
++{
++ struct mxc_vout_output *vout = NULL;
++ int ret = 0;
++
++ vout = video_drvdata(file);
++
++ if (vout == NULL)
++ return -ENODEV;
++
++ if (vout->open_cnt++ == 0) {
++ vout->ctrl_rotate = 0;
++ vout->ctrl_vflip = 0;
++ vout->ctrl_hflip = 0;
++ update_display_setting();
++ ret = update_setting_from_fbi(vout, vout->fbi);
++ if (ret < 0)
++ goto err;
++
++ vout->v4l_wq = create_singlethread_workqueue("v4l2q");
++ if (!vout->v4l_wq) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "Could not create work queue\n");
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ INIT_WORK(&vout->disp_work, disp_work_func);
++
++ INIT_LIST_HEAD(&vout->queue_list);
++ INIT_LIST_HEAD(&vout->active_list);
++
++ vout->fmt_init = false;
++ vout->frame_count = 0;
++ vout->vdi_frame_cnt = 0;
++
++ vout->win_pos.x = 0;
++ vout->win_pos.y = 0;
++ vout->release = true;
++ }
++
++ file->private_data = vout;
++
++err:
++ return ret;
++}
++
++/*
++ * V4L2 ioctls
++ */
++static int mxc_vidioc_querycap(struct file *file, void *fh,
++ struct v4l2_capability *cap)
++{
++ struct mxc_vout_output *vout = fh;
++
++ strlcpy(cap->driver, VOUT_NAME, sizeof(cap->driver));
++ strlcpy(cap->card, vout->vfd->name, sizeof(cap->card));
++ cap->bus_info[0] = '\0';
++ cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT;
++
++ return 0;
++}
++
++static int mxc_vidioc_enum_fmt_vid_out(struct file *file, void *fh,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index >= NUM_MXC_VOUT_FORMATS)
++ return -EINVAL;
++
++ strlcpy(fmt->description, mxc_formats[fmt->index].description,
++ sizeof(fmt->description));
++ fmt->pixelformat = mxc_formats[fmt->index].pixelformat;
++
++ return 0;
++}
++
++static int mxc_vidioc_g_fmt_vid_out(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct mxc_vout_output *vout = fh;
++ struct v4l2_rect rect;
++
++ f->fmt.pix.width = vout->task.input.width;
++ f->fmt.pix.height = vout->task.input.height;
++ f->fmt.pix.pixelformat = vout->task.input.format;
++ f->fmt.pix.sizeimage = get_frame_size(vout);
++
++ if (f->fmt.pix.priv) {
++ rect.left = vout->task.input.crop.pos.x;
++ rect.top = vout->task.input.crop.pos.y;
++ rect.width = vout->task.input.crop.w;
++ rect.height = vout->task.input.crop.h;
++ if (copy_to_user((void __user *)f->fmt.pix.priv,
++ &rect, sizeof(rect)))
++ return -EFAULT;
++ }
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "frame_size:0x%x, pix_fmt:0x%x\n",
++ f->fmt.pix.sizeimage,
++ vout->task.input.format);
++
++ return 0;
++}
++
++static inline int ipu_try_task(struct mxc_vout_output *vout)
++{
++ int ret;
++ struct ipu_task *task = &vout->task;
++
++again:
++ ret = ipu_check_task(task);
++ if (ret != IPU_CHECK_OK) {
++ if (ret > IPU_CHECK_ERR_MIN) {
++ if (ret == IPU_CHECK_ERR_SPLIT_INPUTW_OVER ||
++ ret == IPU_CHECK_ERR_W_DOWNSIZE_OVER) {
++ task->input.crop.w -= 8;
++ goto again;
++ }
++ if (ret == IPU_CHECK_ERR_SPLIT_INPUTH_OVER ||
++ ret == IPU_CHECK_ERR_H_DOWNSIZE_OVER) {
++ task->input.crop.h -= 8;
++ goto again;
++ }
++ if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
++ if (vout->disp_support_windows) {
++ task->output.width -= 8;
++ task->output.crop.w =
++ task->output.width;
++ } else
++ task->output.crop.w -= 8;
++ goto again;
++ }
++ if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
++ if (vout->disp_support_windows) {
++ task->output.height -= 8;
++ task->output.crop.h =
++ task->output.height;
++ } else
++ task->output.crop.h -= 8;
++ goto again;
++ }
++ ret = -EINVAL;
++ }
++ } else
++ ret = 0;
++
++ return ret;
++}
++
++static inline int vdoaipu_try_task(struct mxc_vout_output *vout)
++{
++ int ret;
++ int is_1080p_stream;
++ size_t size;
++ struct ipu_task *ipu_task = &vout->task;
++ struct ipu_crop *icrop = &ipu_task->input.crop;
++ struct ipu_task *vdoa_task = &vout->vdoa_task;
++ u32 deinterlace = 0;
++ u32 in_fmt;
++
++ if (vout->task.input.deinterlace.enable)
++ deinterlace = 1;
++
++ memset(vdoa_task, 0, sizeof(*vdoa_task));
++ vdoa_task->output.format = IPU_PIX_FMT_NV12;
++ memcpy(&vdoa_task->input, &ipu_task->input,
++ sizeof(ipu_task->input));
++ if ((icrop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (icrop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN)) {
++ vdoa_task->input.crop.w =
++ ALIGN(icrop->w, IPU_PIX_FMT_TILED_NV12_MBALIGN);
++ vdoa_task->input.crop.h =
++ ALIGN(icrop->h, IPU_PIX_FMT_TILED_NV12_MBALIGN);
++ }
++ vdoa_task->output.width = vdoa_task->input.crop.w;
++ vdoa_task->output.height = vdoa_task->input.crop.h;
++ vdoa_task->output.crop.w = vdoa_task->input.crop.w;
++ vdoa_task->output.crop.h = vdoa_task->input.crop.h;
++
++ size = PAGE_ALIGN(vdoa_task->input.crop.w *
++ vdoa_task->input.crop.h *
++ fmt_to_bpp(vdoa_task->output.format)/8);
++ if (size > vout->vdoa_work.size) {
++ if (vout->vdoa_work.vaddr)
++ free_dma_buf(vout, &vout->vdoa_work);
++ vout->vdoa_work.size = size;
++ ret = alloc_dma_buf(vout, &vout->vdoa_work);
++ if (ret < 0)
++ return ret;
++ }
++ ret = ipu_check_task(vdoa_task);
++ if (ret != IPU_CHECK_OK)
++ return -EINVAL;
++
++ is_1080p_stream = CHECK_TILED_1080P_STREAM(vout);
++ if (is_1080p_stream)
++ ipu_task->input.crop.h = VALID_HEIGHT_1080P;
++ in_fmt = ipu_task->input.format;
++ ipu_task->input.format = vdoa_task->output.format;
++ ipu_task->input.height = vdoa_task->output.height;
++ ipu_task->input.width = vdoa_task->output.width;
++ if (deinterlace)
++ ipu_task->input.deinterlace.enable = 0;
++ ret = ipu_try_task(vout);
++ if (deinterlace)
++ ipu_task->input.deinterlace.enable = 1;
++ ipu_task->input.format = in_fmt;
++
++ return ret;
++}
++
++static int mxc_vout_try_task(struct mxc_vout_output *vout)
++{
++ int ret = 0;
++ struct ipu_output *output = &vout->task.output;
++ struct ipu_input *input = &vout->task.input;
++ struct ipu_crop *crop = &input->crop;
++ u32 o_height = 0;
++ u32 ocrop_h = 0;
++ bool tiled_fmt = false;
++ bool tiled_need_pp = false;
++
++ vout->vdoa_1080p = CHECK_TILED_1080P_DISPLAY(vout);
++ if (vout->vdoa_1080p) {
++ input->crop.h = FRAME_HEIGHT_1080P;
++ o_height = output->height;
++ ocrop_h = output->crop.h;
++ output->height = FRAME_HEIGHT_1080P;
++ output->crop.h = FRAME_HEIGHT_1080P;
++ }
++
++ if ((IPU_PIX_FMT_TILED_NV12 == input->format) ||
++ (IPU_PIX_FMT_TILED_NV12F == input->format)) {
++ if ((input->width % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (input->height % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (crop->pos.x % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (crop->pos.y % IPU_PIX_FMT_TILED_NV12_MBALIGN)) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "ERR: tiled fmt needs 16 pixel align.\n");
++ return -EINVAL;
++ }
++ if ((crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ tiled_need_pp = true;
++ } else {
++ crop->w -= crop->w % 8;
++ crop->h -= crop->h % 8;
++ }
++ /* assume task.output already set by S_CROP */
++ vout->linear_bypass_pp = is_pp_bypass(vout);
++ if (vout->linear_bypass_pp) {
++ v4l2_info(vout->vfd->v4l2_dev, "Bypass IC.\n");
++ output->format = input->format;
++ } else {
++ /* if need CSC, choose IPU-DP or IPU_IC do it */
++ if (vout->disp_support_csc) {
++ if (colorspaceofpixel(input->format) == YUV_CS)
++ output->format = IPU_PIX_FMT_UYVY;
++ else
++ output->format = IPU_PIX_FMT_RGB565;
++ } else {
++ if (colorspaceofpixel(vout->disp_fmt) == YUV_CS)
++ output->format = IPU_PIX_FMT_UYVY;
++ else
++ output->format = IPU_PIX_FMT_RGB565;
++ }
++
++ vout->tiled_bypass_pp = false;
++ if ((IPU_PIX_FMT_TILED_NV12 == input->format) ||
++ (IPU_PIX_FMT_TILED_NV12F == input->format)) {
++ /* check resize/rotate/flip, or csc task */
++ if (!(tiled_need_pp ||
++ (IPU_ROTATE_NONE != output->rotate) ||
++ (input->crop.w != output->crop.w) ||
++ (input->crop.h != output->crop.h) ||
++ (!vout->disp_support_csc &&
++ (colorspaceofpixel(vout->disp_fmt) == RGB_CS)))
++ ) {
++ /* IC bypass */
++ output->format = IPU_PIX_FMT_NV12;
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "tiled bypass pp\n");
++ vout->tiled_bypass_pp = true;
++ }
++ tiled_fmt = true;
++ }
++
++ if ((!vout->tiled_bypass_pp) && tiled_fmt)
++ ret = vdoaipu_try_task(vout);
++ else
++ ret = ipu_try_task(vout);
++ }
++
++ if (vout->vdoa_1080p) {
++ output->height = o_height;
++ output->crop.h = ocrop_h;
++ }
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "icrop.w:%u, icrop.h:%u, iw:%u, ih:%u,"
++ "ocrop.w:%u, ocrop.h:%u, ow:%u, oh:%u\n",
++ input->crop.w, input->crop.h,
++ input->width, input->height,
++ output->crop.w, output->crop.h,
++ output->width, output->height);
++ return ret;
++}
++
++static int mxc_vout_try_format(struct mxc_vout_output *vout,
++ struct v4l2_format *f)
++{
++ int ret = 0;
++ struct v4l2_rect rect;
++
++ if ((f->fmt.pix.field != V4L2_FIELD_NONE) &&
++ (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format)) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "progressive tiled fmt should used V4L2_FIELD_NONE!\n");
++ return -EINVAL;
++ }
++
++ if (f->fmt.pix.priv && copy_from_user(&rect,
++ (void __user *)f->fmt.pix.priv, sizeof(rect)))
++ return -EFAULT;
++
++ vout->task.input.width = f->fmt.pix.width;
++ vout->task.input.height = f->fmt.pix.height;
++ vout->task.input.format = f->fmt.pix.pixelformat;
++
++ ret = set_field_fmt(vout, f->fmt.pix.field);
++ if (ret < 0)
++ return ret;
++
++ if (f->fmt.pix.priv) {
++ vout->task.input.crop.pos.x = rect.left;
++ vout->task.input.crop.pos.y = rect.top;
++ vout->task.input.crop.w = rect.width;
++ vout->task.input.crop.h = rect.height;
++ } else {
++ vout->task.input.crop.pos.x = 0;
++ vout->task.input.crop.pos.y = 0;
++ vout->task.input.crop.w = f->fmt.pix.width;
++ vout->task.input.crop.h = f->fmt.pix.height;
++ }
++ memcpy(&vout->in_rect, &vout->task.input.crop, sizeof(vout->in_rect));
++
++ ret = mxc_vout_try_task(vout);
++ if (!ret) {
++ if (f->fmt.pix.priv) {
++ rect.width = vout->task.input.crop.w;
++ rect.height = vout->task.input.crop.h;
++ if (copy_to_user((void __user *)f->fmt.pix.priv,
++ &rect, sizeof(rect)))
++ ret = -EFAULT;
++ } else {
++ f->fmt.pix.width = vout->task.input.crop.w;
++ f->fmt.pix.height = vout->task.input.crop.h;
++ }
++ }
++
++ return ret;
++}
++
++static bool mxc_vout_need_fb_reconfig(struct mxc_vout_output *vout,
++ struct mxc_vout_output *pre_vout)
++{
++ if (!vout->vbq.streaming)
++ return false;
++
++ if (vout->tiled_bypass_pp)
++ return true;
++
++ if (vout->linear_bypass_pp != pre_vout->linear_bypass_pp)
++ return true;
++
++ /* cropped output resolution or format are changed */
++ if (vout->task.output.format != pre_vout->task.output.format ||
++ vout->task.output.crop.w != pre_vout->task.output.crop.w ||
++ vout->task.output.crop.h != pre_vout->task.output.crop.h)
++ return true;
++
++ /* overlay: window position or resolution are changed */
++ if (vout->disp_support_windows &&
++ (vout->win_pos.x != pre_vout->win_pos.x ||
++ vout->win_pos.y != pre_vout->win_pos.y ||
++ vout->task.output.width != pre_vout->task.output.width ||
++ vout->task.output.height != pre_vout->task.output.height))
++ return true;
++
++ /* background: cropped position is changed */
++ if (!vout->disp_support_windows &&
++ (vout->task.output.crop.pos.x !=
++ pre_vout->task.output.crop.pos.x ||
++ vout->task.output.crop.pos.y !=
++ pre_vout->task.output.crop.pos.y))
++ return true;
++
++ return false;
++}
++
++static int mxc_vidioc_s_fmt_vid_out(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct mxc_vout_output *vout = fh;
++ int ret = 0;
++
++ if (vout->vbq.streaming)
++ return -EBUSY;
++
++ mutex_lock(&vout->task_lock);
++ ret = mxc_vout_try_format(vout, f);
++ if (ret >= 0)
++ vout->fmt_init = true;
++ mutex_unlock(&vout->task_lock);
++
++ return ret;
++}
++
++static int mxc_vidioc_cropcap(struct file *file, void *fh,
++ struct v4l2_cropcap *cropcap)
++{
++ struct mxc_vout_output *vout = fh;
++
++ if (cropcap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ cropcap->bounds = vout->crop_bounds;
++ cropcap->defrect = vout->crop_bounds;
++
++ return 0;
++}
++
++static int mxc_vidioc_g_crop(struct file *file, void *fh,
++ struct v4l2_crop *crop)
++{
++ struct mxc_vout_output *vout = fh;
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ if (vout->disp_support_windows) {
++ crop->c.left = vout->win_pos.x;
++ crop->c.top = vout->win_pos.y;
++ crop->c.width = vout->task.output.width;
++ crop->c.height = vout->task.output.height;
++ } else {
++ if (vout->task.output.crop.w && vout->task.output.crop.h) {
++ crop->c.left = vout->task.output.crop.pos.x;
++ crop->c.top = vout->task.output.crop.pos.y;
++ crop->c.width = vout->task.output.crop.w;
++ crop->c.height = vout->task.output.crop.h;
++ } else {
++ crop->c.left = 0;
++ crop->c.top = 0;
++ crop->c.width = vout->task.output.width;
++ crop->c.height = vout->task.output.height;
++ }
++ }
++
++ return 0;
++}
++
++static int mxc_vidioc_s_crop(struct file *file, void *fh,
++ const struct v4l2_crop *crop)
++{
++ struct mxc_vout_output *vout = fh, *pre_vout;
++ struct v4l2_rect *b = &vout->crop_bounds;
++ struct v4l2_crop fix_up_crop;
++ int ret = 0;
++
++ memcpy(&fix_up_crop, crop, sizeof(*crop));
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ if (crop->c.width < 0 || crop->c.height < 0)
++ return -EINVAL;
++
++ if (crop->c.width == 0)
++ fix_up_crop.c.width = b->width - b->left;
++ if (crop->c.height == 0)
++ fix_up_crop.c.height = b->height - b->top;
++
++ if (crop->c.top < b->top)
++ fix_up_crop.c.top = b->top;
++ if (crop->c.top >= b->top + b->height)
++ fix_up_crop.c.top = b->top + b->height - 1;
++ if (crop->c.height > b->top - crop->c.top + b->height)
++ fix_up_crop.c.height =
++ b->top - fix_up_crop.c.top + b->height;
++
++ if (crop->c.left < b->left)
++ fix_up_crop.c.left = b->left;
++ if (crop->c.left >= b->left + b->width)
++ fix_up_crop.c.left = b->left + b->width - 1;
++ if (crop->c.width > b->left - crop->c.left + b->width)
++ fix_up_crop.c.width =
++ b->left - fix_up_crop.c.left + b->width;
++
++ /* stride line limitation */
++ fix_up_crop.c.height -= fix_up_crop.c.height % 8;
++ fix_up_crop.c.width -= fix_up_crop.c.width % 8;
++ if ((fix_up_crop.c.width <= 0) || (fix_up_crop.c.height <= 0) ||
++ ((fix_up_crop.c.left + fix_up_crop.c.width) >
++ (b->left + b->width)) ||
++ ((fix_up_crop.c.top + fix_up_crop.c.height) >
++ (b->top + b->height))) {
++ v4l2_err(vout->vfd->v4l2_dev, "s_crop err: %d, %d, %d, %d",
++ fix_up_crop.c.left, fix_up_crop.c.top,
++ fix_up_crop.c.width, fix_up_crop.c.height);
++ return -EINVAL;
++ }
++
++ /* the same setting, return */
++ if (vout->disp_support_windows) {
++ if ((vout->win_pos.x == fix_up_crop.c.left) &&
++ (vout->win_pos.y == fix_up_crop.c.top) &&
++ (vout->task.output.crop.w == fix_up_crop.c.width) &&
++ (vout->task.output.crop.h == fix_up_crop.c.height))
++ return 0;
++ } else {
++ if ((vout->task.output.crop.pos.x == fix_up_crop.c.left) &&
++ (vout->task.output.crop.pos.y == fix_up_crop.c.top) &&
++ (vout->task.output.crop.w == fix_up_crop.c.width) &&
++ (vout->task.output.crop.h == fix_up_crop.c.height))
++ return 0;
++ }
++
++ pre_vout = vmalloc(sizeof(*pre_vout));
++ if (!pre_vout)
++ return -ENOMEM;
++
++ /* wait current work finish */
++ if (vout->vbq.streaming)
++ flush_workqueue(vout->v4l_wq);
++
++ mutex_lock(&vout->task_lock);
++
++ memcpy(pre_vout, vout, sizeof(*vout));
++
++ if (vout->disp_support_windows) {
++ vout->task.output.crop.pos.x = 0;
++ vout->task.output.crop.pos.y = 0;
++ vout->win_pos.x = fix_up_crop.c.left;
++ vout->win_pos.y = fix_up_crop.c.top;
++ vout->task.output.width = fix_up_crop.c.width;
++ vout->task.output.height = fix_up_crop.c.height;
++ } else {
++ vout->task.output.crop.pos.x = fix_up_crop.c.left;
++ vout->task.output.crop.pos.y = fix_up_crop.c.top;
++ }
++
++ vout->task.output.crop.w = fix_up_crop.c.width;
++ vout->task.output.crop.h = fix_up_crop.c.height;
++
++ /*
++ * must S_CROP before S_FMT, for fist time S_CROP, will not check
++ * ipu task, it will check in S_FMT, after S_FMT, S_CROP should
++ * check ipu task too.
++ */
++ if (vout->fmt_init) {
++ memcpy(&vout->task.input.crop, &vout->in_rect,
++ sizeof(vout->in_rect));
++ ret = mxc_vout_try_task(vout);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "vout check task failed\n");
++ memcpy(vout, pre_vout, sizeof(*vout));
++ goto done;
++ }
++
++ if (mxc_vout_need_fb_reconfig(vout, pre_vout)) {
++ ret = config_disp_output(vout);
++ if (ret < 0)
++ v4l2_err(vout->vfd->v4l2_dev,
++ "Config display output failed\n");
++ }
++ }
++
++done:
++ vfree(pre_vout);
++ mutex_unlock(&vout->task_lock);
++
++ return ret;
++}
++
++static int mxc_vidioc_queryctrl(struct file *file, void *fh,
++ struct v4l2_queryctrl *ctrl)
++{
++ int ret = 0;
++
++ switch (ctrl->id) {
++ case V4L2_CID_ROTATE:
++ ret = v4l2_ctrl_query_fill(ctrl, 0, 270, 90, 0);
++ break;
++ case V4L2_CID_VFLIP:
++ ret = v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0);
++ break;
++ case V4L2_CID_HFLIP:
++ ret = v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0);
++ break;
++ case V4L2_CID_MXC_MOTION:
++ ret = v4l2_ctrl_query_fill(ctrl, 0, 2, 1, 0);
++ break;
++ default:
++ ctrl->name[0] = '\0';
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++static int mxc_vidioc_g_ctrl(struct file *file, void *fh,
++ struct v4l2_control *ctrl)
++{
++ int ret = 0;
++ struct mxc_vout_output *vout = fh;
++
++ switch (ctrl->id) {
++ case V4L2_CID_ROTATE:
++ ctrl->value = vout->ctrl_rotate;
++ break;
++ case V4L2_CID_VFLIP:
++ ctrl->value = vout->ctrl_vflip;
++ break;
++ case V4L2_CID_HFLIP:
++ ctrl->value = vout->ctrl_hflip;
++ break;
++ case V4L2_CID_MXC_MOTION:
++ if (vout->task.input.deinterlace.enable)
++ ctrl->value = vout->task.input.deinterlace.motion;
++ else
++ ctrl->value = 0;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++static void setup_task_rotation(struct mxc_vout_output *vout)
++{
++ if (vout->ctrl_rotate == 0) {
++ if (vout->ctrl_vflip && vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_180;
++ else if (vout->ctrl_vflip)
++ vout->task.output.rotate = IPU_ROTATE_VERT_FLIP;
++ else if (vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_HORIZ_FLIP;
++ else
++ vout->task.output.rotate = IPU_ROTATE_NONE;
++ } else if (vout->ctrl_rotate == 90) {
++ if (vout->ctrl_vflip && vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_90_LEFT;
++ else if (vout->ctrl_vflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_VFLIP;
++ else if (vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_HFLIP;
++ else
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT;
++ } else if (vout->ctrl_rotate == 180) {
++ if (vout->ctrl_vflip && vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_NONE;
++ else if (vout->ctrl_vflip)
++ vout->task.output.rotate = IPU_ROTATE_HORIZ_FLIP;
++ else if (vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_VERT_FLIP;
++ else
++ vout->task.output.rotate = IPU_ROTATE_180;
++ } else if (vout->ctrl_rotate == 270) {
++ if (vout->ctrl_vflip && vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT;
++ else if (vout->ctrl_vflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_HFLIP;
++ else if (vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_VFLIP;
++ else
++ vout->task.output.rotate = IPU_ROTATE_90_LEFT;
++ }
++}
++
++static int mxc_vidioc_s_ctrl(struct file *file, void *fh,
++ struct v4l2_control *ctrl)
++{
++ int ret = 0;
++ struct mxc_vout_output *vout = fh, *pre_vout;
++
++ pre_vout = vmalloc(sizeof(*pre_vout));
++ if (!pre_vout)
++ return -ENOMEM;
++
++ /* wait current work finish */
++ if (vout->vbq.streaming)
++ flush_workqueue(vout->v4l_wq);
++
++ mutex_lock(&vout->task_lock);
++
++ memcpy(pre_vout, vout, sizeof(*vout));
++
++ switch (ctrl->id) {
++ case V4L2_CID_ROTATE:
++ {
++ vout->ctrl_rotate = (ctrl->value/90) * 90;
++ if (vout->ctrl_rotate > 270)
++ vout->ctrl_rotate = 270;
++ setup_task_rotation(vout);
++ break;
++ }
++ case V4L2_CID_VFLIP:
++ {
++ vout->ctrl_vflip = ctrl->value;
++ setup_task_rotation(vout);
++ break;
++ }
++ case V4L2_CID_HFLIP:
++ {
++ vout->ctrl_hflip = ctrl->value;
++ setup_task_rotation(vout);
++ break;
++ }
++ case V4L2_CID_MXC_MOTION:
++ {
++ vout->task.input.deinterlace.motion = ctrl->value;
++ break;
++ }
++ default:
++ ret = -EINVAL;
++ goto done;
++ }
++
++ if (vout->fmt_init) {
++ memcpy(&vout->task.input.crop, &vout->in_rect,
++ sizeof(vout->in_rect));
++ ret = mxc_vout_try_task(vout);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "vout check task failed\n");
++ memcpy(vout, pre_vout, sizeof(*vout));
++ goto done;
++ }
++
++ if (mxc_vout_need_fb_reconfig(vout, pre_vout)) {
++ ret = config_disp_output(vout);
++ if (ret < 0)
++ v4l2_err(vout->vfd->v4l2_dev,
++ "Config display output failed\n");
++ }
++ }
++
++done:
++ vfree(pre_vout);
++ mutex_unlock(&vout->task_lock);
++
++ return ret;
++}
++
++static int mxc_vidioc_reqbufs(struct file *file, void *fh,
++ struct v4l2_requestbuffers *req)
++{
++ int ret = 0;
++ struct mxc_vout_output *vout = fh;
++ struct videobuf_queue *q = &vout->vbq;
++
++ if (req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ /* should not be here after streaming, videobuf_reqbufs will control */
++ mutex_lock(&vout->task_lock);
++
++ ret = videobuf_reqbufs(q, req);
++
++ mutex_unlock(&vout->task_lock);
++ return ret;
++}
++
++static int mxc_vidioc_querybuf(struct file *file, void *fh,
++ struct v4l2_buffer *b)
++{
++ int ret;
++ struct mxc_vout_output *vout = fh;
++
++ ret = videobuf_querybuf(&vout->vbq, b);
++ if (!ret) {
++ /* return physical address */
++ struct videobuf_buffer *vb = vout->vbq.bufs[b->index];
++ if (b->flags & V4L2_BUF_FLAG_MAPPED)
++ b->m.offset = videobuf_to_dma_contig(vb);
++ }
++
++ return ret;
++}
++
++static int mxc_vidioc_qbuf(struct file *file, void *fh,
++ struct v4l2_buffer *buffer)
++{
++ struct mxc_vout_output *vout = fh;
++
++ return videobuf_qbuf(&vout->vbq, buffer);
++}
++
++static int mxc_vidioc_dqbuf(struct file *file, void *fh, struct v4l2_buffer *b)
++{
++ struct mxc_vout_output *vout = fh;
++
++ if (!vout->vbq.streaming)
++ return -EINVAL;
++
++ if (file->f_flags & O_NONBLOCK)
++ return videobuf_dqbuf(&vout->vbq, (struct v4l2_buffer *)b, 1);
++ else
++ return videobuf_dqbuf(&vout->vbq, (struct v4l2_buffer *)b, 0);
++}
++
++static int set_window_position(struct mxc_vout_output *vout,
++ struct mxcfb_pos *pos)
++{
++ struct fb_info *fbi = vout->fbi;
++ mm_segment_t old_fs;
++ int ret = 0;
++
++ if (vout->disp_support_windows) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ ret = fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS,
++ (unsigned long)pos);
++ set_fs(old_fs);
++ }
++
++ return ret;
++}
++
++static int config_disp_output(struct mxc_vout_output *vout)
++{
++ struct dma_mem *buf = NULL;
++ struct fb_info *fbi = vout->fbi;
++ struct fb_var_screeninfo var;
++ struct mxcfb_pos pos;
++ int i, fb_num, ret;
++ u32 fb_base;
++ u32 size;
++ u32 display_buf_size;
++ u32 *pixel = NULL;
++ u32 color;
++ int j;
++
++ memcpy(&var, &fbi->var, sizeof(var));
++ fb_base = fbi->fix.smem_start;
++
++ var.xres = vout->task.output.width;
++ var.yres = vout->task.output.height;
++ if (vout->linear_bypass_pp || vout->tiled_bypass_pp) {
++ fb_num = 1;
++ /* input crop */
++ if (vout->task.input.width > vout->task.output.width)
++ var.xres_virtual = vout->task.input.width;
++ else
++ var.xres_virtual = var.xres;
++ if (vout->task.input.height > vout->task.output.height)
++ var.yres_virtual = vout->task.input.height;
++ else
++ var.yres_virtual = var.yres;
++ var.rotate = vout->task.output.rotate;
++ var.vmode |= FB_VMODE_YWRAP;
++ } else {
++ fb_num = FB_BUFS;
++ var.xres_virtual = var.xres;
++ var.yres_virtual = fb_num * var.yres;
++ var.vmode &= ~FB_VMODE_YWRAP;
++ }
++ var.bits_per_pixel = fmt_to_bpp(vout->task.output.format);
++ var.nonstd = vout->task.output.format;
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "set display fb to %d %d\n",
++ var.xres, var.yres);
++
++ /*
++ * To setup the overlay fb from scratch without
++ * the last time overlay fb position or resolution's
++ * impact, we take the following steps:
++ * - blank fb
++ * - set fb position to the starting point
++ * - reconfigure fb
++ * - set fb position to a specific point
++ * - unblank fb
++ * This procedure applies to non-overlay fbs as well.
++ */
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ pos.x = 0;
++ pos.y = 0;
++ ret = set_window_position(vout, &pos);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev, "failed to set fb position "
++ "to starting point\n");
++ return ret;
++ }
++
++ /* Init display channel through fb API */
++ var.yoffset = 0;
++ var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ ret = fb_set_var(fbi, &var);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "ERR:%s fb_set_var ret:%d\n", __func__, ret);
++ return ret;
++ }
++
++ ret = set_window_position(vout, &vout->win_pos);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev, "failed to set fb position\n");
++ return ret;
++ }
++
++ if (vout->linear_bypass_pp || vout->tiled_bypass_pp)
++ display_buf_size = fbi->fix.line_length * fbi->var.yres_virtual;
++ else
++ display_buf_size = fbi->fix.line_length * fbi->var.yres;
++ for (i = 0; i < fb_num; i++)
++ vout->disp_bufs[i] = fbi->fix.smem_start + i * display_buf_size;
++ if (vout->tiled_bypass_pp) {
++ size = PAGE_ALIGN(vout->task.input.crop.w *
++ vout->task.input.crop.h *
++ fmt_to_bpp(vout->task.output.format)/8);
++ if (size > vout->vdoa_output[0].size) {
++ for (i = 0; i < VDOA_FB_BUFS; i++) {
++ buf = &vout->vdoa_output[i];
++ if (buf->vaddr)
++ free_dma_buf(vout, buf);
++ buf->size = size;
++ ret = alloc_dma_buf(vout, buf);
++ if (ret < 0)
++ goto err;
++ }
++ }
++ for (i = fb_num; i < (fb_num + VDOA_FB_BUFS); i++)
++ vout->disp_bufs[i] =
++ vout->vdoa_output[i - fb_num].paddr;
++ }
++ vout->fb_smem_len = fbi->fix.smem_len;
++ vout->fb_smem_start = fbi->fix.smem_start;
++ if (fb_base != fbi->fix.smem_start) {
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "realloc fb mem size:0x%x@0x%lx,old paddr @0x%x\n",
++ fbi->fix.smem_len, fbi->fix.smem_start, fb_base);
++ }
++
++ /* fill black when video config changed */
++ color = colorspaceofpixel(vout->task.output.format) == YUV_CS ?
++ UYVY_BLACK : RGB_BLACK;
++ if (IS_PLANAR_PIXEL_FORMAT(vout->task.output.format)) {
++ size = display_buf_size * 8 /
++ fmt_to_bpp(vout->task.output.format);
++ memset(fbi->screen_base, Y_BLACK, size);
++ memset(fbi->screen_base + size, UV_BLACK,
++ display_buf_size - size);
++ } else {
++ pixel = (u32 *)fbi->screen_base;
++ for (i = 0; i < (display_buf_size >> 2); i++)
++ *pixel++ = color;
++ }
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ ret = fb_blank(fbi, FB_BLANK_UNBLANK);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ vout->release = false;
++
++ return ret;
++err:
++ for (j = i - 1; j >= 0; j--) {
++ buf = &vout->vdoa_output[j];
++ if (buf->vaddr)
++ free_dma_buf(vout, buf);
++ }
++ return ret;
++}
++
++static inline void wait_for_vsync(struct mxc_vout_output *vout)
++{
++ struct fb_info *fbi = vout->fbi;
++ mm_segment_t old_fs;
++
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC,
++ (unsigned long)NULL);
++ set_fs(old_fs);
++ }
++
++ return;
++}
++
++static void release_disp_output(struct mxc_vout_output *vout)
++{
++ struct fb_info *fbi = vout->fbi;
++ struct mxcfb_pos pos;
++
++ if (vout->release)
++ return;
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ /* restore pos to 0,0 avoid fb pan display hang? */
++ pos.x = 0;
++ pos.y = 0;
++ set_window_position(vout, &pos);
++
++ if (get_ipu_channel(fbi) == MEM_BG_SYNC) {
++ console_lock();
++ fbi->fix.smem_start = vout->disp_bufs[0];
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_blank(fbi, FB_BLANK_UNBLANK);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ }
++
++ vout->release = true;
++}
++
++static int mxc_vidioc_streamon(struct file *file, void *fh,
++ enum v4l2_buf_type i)
++{
++ struct mxc_vout_output *vout = fh;
++ struct videobuf_queue *q = &vout->vbq;
++ int ret;
++
++ if (q->streaming) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "video output already run\n");
++ ret = -EBUSY;
++ goto done;
++ }
++
++ if (deinterlace_3_field(vout) && list_is_singular(&q->stream)) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "deinterlacing: need queue 2 frame before streamon\n");
++ ret = -EINVAL;
++ goto done;
++ }
++
++ ret = config_disp_output(vout);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "Config display output failed\n");
++ goto done;
++ }
++
++ hrtimer_init(&vout->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS);
++ vout->timer.function = mxc_vout_timer_handler;
++ vout->timer_stop = true;
++
++ vout->start_ktime = hrtimer_cb_get_time(&vout->timer);
++
++ vout->pre1_vb = NULL;
++ vout->pre2_vb = NULL;
++
++ ret = videobuf_streamon(q);
++done:
++ return ret;
++}
++
++static int mxc_vidioc_streamoff(struct file *file, void *fh,
++ enum v4l2_buf_type i)
++{
++ struct mxc_vout_output *vout = fh;
++ struct videobuf_queue *q = &vout->vbq;
++ int ret = 0;
++
++ if (q->streaming) {
++ flush_workqueue(vout->v4l_wq);
++
++ hrtimer_cancel(&vout->timer);
++
++ /*
++ * Wait for 2 vsyncs to make sure
++ * frames are drained on triple
++ * buffer.
++ */
++ wait_for_vsync(vout);
++ wait_for_vsync(vout);
++
++ release_disp_output(vout);
++
++ ret = videobuf_streamoff(&vout->vbq);
++ }
++ INIT_LIST_HEAD(&vout->queue_list);
++ INIT_LIST_HEAD(&vout->active_list);
++
++ return ret;
++}
++
++static const struct v4l2_ioctl_ops mxc_vout_ioctl_ops = {
++ .vidioc_querycap = mxc_vidioc_querycap,
++ .vidioc_enum_fmt_vid_out = mxc_vidioc_enum_fmt_vid_out,
++ .vidioc_g_fmt_vid_out = mxc_vidioc_g_fmt_vid_out,
++ .vidioc_s_fmt_vid_out = mxc_vidioc_s_fmt_vid_out,
++ .vidioc_cropcap = mxc_vidioc_cropcap,
++ .vidioc_g_crop = mxc_vidioc_g_crop,
++ .vidioc_s_crop = mxc_vidioc_s_crop,
++ .vidioc_queryctrl = mxc_vidioc_queryctrl,
++ .vidioc_g_ctrl = mxc_vidioc_g_ctrl,
++ .vidioc_s_ctrl = mxc_vidioc_s_ctrl,
++ .vidioc_reqbufs = mxc_vidioc_reqbufs,
++ .vidioc_querybuf = mxc_vidioc_querybuf,
++ .vidioc_qbuf = mxc_vidioc_qbuf,
++ .vidioc_dqbuf = mxc_vidioc_dqbuf,
++ .vidioc_streamon = mxc_vidioc_streamon,
++ .vidioc_streamoff = mxc_vidioc_streamoff,
++};
++
++static const struct v4l2_file_operations mxc_vout_fops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = video_ioctl2,
++ .mmap = mxc_vout_mmap,
++ .open = mxc_vout_open,
++ .release = mxc_vout_release,
++};
++
++static struct video_device mxc_vout_template = {
++ .name = "MXC Video Output",
++ .fops = &mxc_vout_fops,
++ .ioctl_ops = &mxc_vout_ioctl_ops,
++ .release = video_device_release,
++};
++
++static struct videobuf_queue_ops mxc_vout_vbq_ops = {
++ .buf_setup = mxc_vout_buffer_setup,
++ .buf_prepare = mxc_vout_buffer_prepare,
++ .buf_release = mxc_vout_buffer_release,
++ .buf_queue = mxc_vout_buffer_queue,
++};
++
++static void mxc_vout_free_output(struct mxc_vout_dev *dev)
++{
++ int i;
++ int j;
++ struct mxc_vout_output *vout;
++ struct video_device *vfd;
++
++ for (i = 0; i < dev->out_num; i++) {
++ vout = dev->out[i];
++ vfd = vout->vfd;
++ if (vout->vdoa_work.vaddr)
++ free_dma_buf(vout, &vout->vdoa_work);
++ for (j = 0; j < VDOA_FB_BUFS; j++) {
++ if (vout->vdoa_output[j].vaddr)
++ free_dma_buf(vout, &vout->vdoa_output[j]);
++ }
++ if (vfd) {
++ if (!video_is_registered(vfd))
++ video_device_release(vfd);
++ else
++ video_unregister_device(vfd);
++ }
++ kfree(vout);
++ }
++}
++
++static int mxc_vout_setup_output(struct mxc_vout_dev *dev)
++{
++ struct videobuf_queue *q;
++ struct fb_info *fbi;
++ struct mxc_vout_output *vout;
++ int i, ret = 0;
++
++ update_display_setting();
++
++ /* all output/overlay based on fb */
++ for (i = 0; i < num_registered_fb; i++) {
++ fbi = registered_fb[i];
++
++ vout = kzalloc(sizeof(struct mxc_vout_output), GFP_KERNEL);
++ if (!vout) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ dev->out[dev->out_num] = vout;
++ dev->out_num++;
++
++ vout->fbi = fbi;
++ vout->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++ vout->vfd = video_device_alloc();
++ if (!vout->vfd) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ *vout->vfd = mxc_vout_template;
++ vout->vfd->debug = debug;
++ vout->vfd->v4l2_dev = &dev->v4l2_dev;
++ vout->vfd->lock = &vout->mutex;
++ vout->vfd->vfl_dir = VFL_DIR_TX;
++
++ mutex_init(&vout->mutex);
++ mutex_init(&vout->task_lock);
++
++ strlcpy(vout->vfd->name, fbi->fix.id, sizeof(vout->vfd->name));
++
++ video_set_drvdata(vout->vfd, vout);
++
++ if (video_register_device(vout->vfd,
++ VFL_TYPE_GRABBER, video_nr + i) < 0) {
++ ret = -ENODEV;
++ break;
++ }
++
++ q = &vout->vbq;
++ q->dev = dev->dev;
++ spin_lock_init(&vout->vbq_lock);
++ videobuf_queue_dma_contig_init(q, &mxc_vout_vbq_ops, q->dev,
++ &vout->vbq_lock, vout->type, V4L2_FIELD_NONE,
++ sizeof(struct videobuf_buffer), vout, NULL);
++
++ v4l2_info(vout->vfd->v4l2_dev, "V4L2 device registered as %s\n",
++ video_device_node_name(vout->vfd));
++
++ }
++
++ return ret;
++}
++
++static int mxc_vout_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct mxc_vout_dev *dev;
++
++ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++ if (!dev)
++ return -ENOMEM;
++
++ dev->dev = &pdev->dev;
++ dev->dev->dma_mask = kmalloc(sizeof(*dev->dev->dma_mask), GFP_KERNEL);
++ *dev->dev->dma_mask = DMA_BIT_MASK(32);
++ dev->dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ ret = v4l2_device_register(dev->dev, &dev->v4l2_dev);
++ if (ret) {
++ dev_err(dev->dev, "v4l2_device_register failed\n");
++ goto free_dev;
++ }
++
++ ret = mxc_vout_setup_output(dev);
++ if (ret < 0)
++ goto rel_vdev;
++
++ return 0;
++
++rel_vdev:
++ mxc_vout_free_output(dev);
++ v4l2_device_unregister(&dev->v4l2_dev);
++free_dev:
++ kfree(dev);
++ return ret;
++}
++
++static int mxc_vout_remove(struct platform_device *pdev)
++{
++ struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
++ struct mxc_vout_dev *dev = container_of(v4l2_dev, struct
++ mxc_vout_dev, v4l2_dev);
++
++ mxc_vout_free_output(dev);
++ v4l2_device_unregister(v4l2_dev);
++ kfree(dev);
++ return 0;
++}
++
++static const struct of_device_id mxc_v4l2_dt_ids[] = {
++ { .compatible = "fsl,mxc_v4l2_output", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_vout_driver = {
++ .driver = {
++ .name = "mxc_v4l2_output",
++ .of_match_table = mxc_v4l2_dt_ids,
++ },
++ .probe = mxc_vout_probe,
++ .remove = mxc_vout_remove,
++};
++
++static int __init mxc_vout_init(void)
++{
++ if (platform_driver_register(&mxc_vout_driver) != 0) {
++ printk(KERN_ERR VOUT_NAME ":Could not register Video driver\n");
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static void mxc_vout_cleanup(void)
++{
++ platform_driver_unregister(&mxc_vout_driver);
++}
++
++module_init(mxc_vout_init);
++module_exit(mxc_vout_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("V4L2-driver for MXC video output");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/media/v4l2-core/videobuf-dma-contig.c linux-linaro-stable-mx6/drivers/media/v4l2-core/videobuf-dma-contig.c
+--- linux-3.10.30.orig/drivers/media/v4l2-core/videobuf-dma-contig.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/media/v4l2-core/videobuf-dma-contig.c 2014-05-15 20:33:57.950013520 +0200
+@@ -307,7 +307,7 @@
+ size = vma->vm_end - vma->vm_start;
+ size = (size < mem->size) ? size : mem->size;
+
+- vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+ retval = remap_pfn_range(vma, vma->vm_start,
+ mem->dma_handle >> PAGE_SHIFT,
+ size, vma->vm_page_prot);
+diff -Nur linux-3.10.30.orig/drivers/mfd/Kconfig linux-linaro-stable-mx6/drivers/mfd/Kconfig
+--- linux-3.10.30.orig/drivers/mfd/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/Kconfig 2014-05-15 20:33:58.030014096 +0200
+@@ -139,6 +139,13 @@
+ This driver can be built as a module. If built as a module it will be
+ called "da9055"
+
++config MFD_MXC_HDMI
++ tristate "Freescale HDMI Core"
++ select MFD_CORE
++ help
++ This is the core driver for the Freescale i.MX6 on-chip HDMI.
++ This MFD driver connects with the video and audio drivers for HDMI.
++
+ config MFD_MC13783
+ tristate
+
+@@ -277,6 +284,13 @@
+ select individual components like voltage regulators, RTC and
+ battery-charger under the corresponding menus.
+
++config MFD_MAX17135
++ tristate "Maxim MAX17135 EPD PMIC core"
++ depends on I2C
++ help
++ This is the MAX17135 PMIC support. It includes
++ core support for communication with the MAX17135 chip.
++
+ config MFD_MAX77686
+ bool "Maxim Semiconductor MAX77686 PMIC Support"
+ depends on I2C=y && GENERIC_HARDIRQS
+@@ -1144,7 +1158,16 @@
+ endmenu
+
+ config VEXPRESS_CONFIG
+- bool
++ bool "ARM Versatile Express platform infrastructure"
++ depends on ARM || ARM64
+ help
+ Platform configuration infrastructure for the ARM Ltd.
+ Versatile Express.
++
++config VEXPRESS_SPC
++ bool "Versatile Express SPC driver support"
++ depends on ARM
++ depends on VEXPRESS_CONFIG
++ help
++ Serial Power Controller driver for ARM Ltd. test chips.
++
+diff -Nur linux-3.10.30.orig/drivers/mfd/Makefile linux-linaro-stable-mx6/drivers/mfd/Makefile
+--- linux-3.10.30.orig/drivers/mfd/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/Makefile 2014-05-15 20:33:58.030014096 +0200
+@@ -104,6 +104,7 @@
+ da9055-objs := da9055-core.o da9055-i2c.o
+ obj-$(CONFIG_MFD_DA9055) += da9055.o
+
++obj-$(CONFIG_MFD_MAX17135) += max17135-core.o
+ obj-$(CONFIG_MFD_MAX77686) += max77686.o max77686-irq.o
+ obj-$(CONFIG_MFD_MAX77693) += max77693.o max77693-irq.o
+ obj-$(CONFIG_MFD_MAX8907) += max8907.o
+@@ -153,5 +154,7 @@
+ obj-$(CONFIG_MFD_SYSCON) += syscon.o
+ obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o
+ obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o vexpress-sysreg.o
++obj-$(CONFIG_VEXPRESS_SPC) += vexpress-spc.o
+ obj-$(CONFIG_MFD_RETU) += retu-mfd.o
+ obj-$(CONFIG_MFD_AS3711) += as3711.o
++obj-$(CONFIG_MFD_MXC_HDMI) += mxc-hdmi-core.o
+diff -Nur linux-3.10.30.orig/drivers/mfd/max17135-core.c linux-linaro-stable-mx6/drivers/mfd/max17135-core.c
+--- linux-3.10.30.orig/drivers/mfd/max17135-core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/max17135-core.c 2014-05-15 20:33:58.050014240 +0200
+@@ -0,0 +1,295 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++/*!
++ * @file pmic/core/max17135.c
++ * @brief This file contains MAX17135 specific PMIC code. This implementaion
++ * may differ for each PMIC chip.
++ *
++ * @ingroup PMIC_CORE
++ */
++
++/*
++ * Includes
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/uaccess.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <linux/pmic_status.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/max17135.h>
++#include <asm/mach-types.h>
++
++static int max17135_detect(struct i2c_client *client,
++ struct i2c_board_info *info);
++struct i2c_client *max17135_client;
++static struct regulator *gpio_regulator;
++
++static struct mfd_cell max17135_devs[] = {
++ { .name = "max17135-pmic", },
++ { .name = "max17135-sns", },
++};
++
++static const unsigned short normal_i2c[] = {0x48, I2C_CLIENT_END};
++
++int max17135_reg_read(int reg_num, unsigned int *reg_val)
++{
++ int result;
++
++ if (max17135_client == NULL)
++ return PMIC_ERROR;
++
++ if ((reg_num == REG_MAX17135_EXT_TEMP) ||
++ (reg_num == REG_MAX17135_INT_TEMP)) {
++ result = i2c_smbus_read_word_data(max17135_client, reg_num);
++ if (result < 0) {
++ dev_err(&max17135_client->dev,
++ "Unable to read MAX17135 register via I2C\n");
++ return PMIC_ERROR;
++ }
++ /* Swap bytes for dword read */
++ result = (result >> 8) | ((result & 0xFF) << 8);
++ } else {
++ result = i2c_smbus_read_byte_data(max17135_client, reg_num);
++ if (result < 0) {
++ dev_err(&max17135_client->dev,
++ "Unable to read MAX17135 register via I2C\n");
++ return PMIC_ERROR;
++ }
++ }
++
++ *reg_val = result;
++ return PMIC_SUCCESS;
++}
++
++int max17135_reg_write(int reg_num, const unsigned int reg_val)
++{
++ int result;
++
++ if (max17135_client == NULL)
++ return PMIC_ERROR;
++
++ result = i2c_smbus_write_byte_data(max17135_client, reg_num, reg_val);
++ if (result < 0) {
++ dev_err(&max17135_client->dev,
++ "Unable to write MAX17135 register via I2C\n");
++ return PMIC_ERROR;
++ }
++
++ return PMIC_SUCCESS;
++}
++
++#ifdef CONFIG_OF
++static struct max17135_platform_data *max17135_i2c_parse_dt_pdata(
++ struct device *dev)
++{
++ struct max17135_platform_data *pdata;
++
++ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
++ if (!pdata) {
++ dev_err(dev, "could not allocate memory for pdata\n");
++ return ERR_PTR(-ENOMEM);
++ }
++
++ return pdata;
++}
++#else
++static struct max17135_platform_data *max17135_i2c_parse_dt_pdata(
++ struct device *dev)
++{
++ return NULL;
++}
++#endif /* !CONFIG_OF */
++
++static int max17135_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct max17135 *max17135;
++ struct max17135_platform_data *pdata = client->dev.platform_data;
++ struct device_node *np = client->dev.of_node;
++ int ret = 0;
++
++ if (!np)
++ return -ENODEV;
++
++ gpio_regulator = devm_regulator_get(&client->dev, "SENSOR");
++ if (!IS_ERR(gpio_regulator)) {
++ ret = regulator_enable(gpio_regulator);
++ if (ret) {
++ dev_err(&client->dev, "gpio set voltage error\n");
++ return ret;
++ }
++ }
++
++ /* Create the PMIC data structure */
++ max17135 = kzalloc(sizeof(struct max17135), GFP_KERNEL);
++ if (max17135 == NULL) {
++ kfree(client);
++ return -ENOMEM;
++ }
++
++ /* Initialize the PMIC data structure */
++ i2c_set_clientdata(client, max17135);
++ max17135->dev = &client->dev;
++ max17135->i2c_client = client;
++
++ max17135_client = client;
++ ret = max17135_detect(client, NULL);
++ if (ret)
++ goto err1;
++
++ mfd_add_devices(max17135->dev, -1, max17135_devs,
++ ARRAY_SIZE(max17135_devs),
++ NULL, 0, NULL);
++
++ if (max17135->dev->of_node) {
++ pdata = max17135_i2c_parse_dt_pdata(max17135->dev);
++ if (IS_ERR(pdata)) {
++ ret = PTR_ERR(pdata);
++ goto err2;
++ }
++
++ }
++ max17135->pdata = pdata;
++
++ dev_info(&client->dev, "PMIC MAX17135 for eInk display\n");
++
++ return ret;
++err2:
++ mfd_remove_devices(max17135->dev);
++err1:
++ kfree(max17135);
++
++ return ret;
++}
++
++
++static int max17135_remove(struct i2c_client *i2c)
++{
++ struct max17135 *max17135 = i2c_get_clientdata(i2c);
++
++ mfd_remove_devices(max17135->dev);
++ return 0;
++}
++
++static int max17135_suspend(struct i2c_client *client, pm_message_t state)
++{
++ return 0;
++}
++
++static int max17135_resume(struct i2c_client *client)
++{
++ return 0;
++}
++
++/* Return 0 if detection is successful, -ENODEV otherwise */
++static int max17135_detect(struct i2c_client *client,
++ struct i2c_board_info *info)
++{
++ struct i2c_adapter *adapter = client->adapter;
++ u8 chip_rev, chip_id;
++
++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
++ return -ENODEV;
++
++ /* detection */
++ if (i2c_smbus_read_byte_data(client,
++ REG_MAX17135_PRODUCT_REV) != 0) {
++ dev_err(&adapter->dev,
++ "Max17135 PMIC not found!\n");
++ return -ENODEV;
++ }
++
++ /* identification */
++ chip_rev = i2c_smbus_read_byte_data(client,
++ REG_MAX17135_PRODUCT_REV);
++ chip_id = i2c_smbus_read_byte_data(client,
++ REG_MAX17135_PRODUCT_ID);
++
++ if (chip_rev != 0x00 || chip_id != 0x4D) { /* identification failed */
++ dev_info(&adapter->dev,
++ "Unsupported chip (man_id=0x%02X, "
++ "chip_id=0x%02X).\n", chip_rev, chip_id);
++ return -ENODEV;
++ }
++
++ if (info)
++ strlcpy(info->type, "max17135_sensor", I2C_NAME_SIZE);
++
++ return 0;
++}
++
++static const struct i2c_device_id max17135_id[] = {
++ { "max17135", 0 },
++ { }
++};
++MODULE_DEVICE_TABLE(i2c, max17135_id);
++
++static const struct of_device_id max17135_dt_ids[] = {
++ {
++ .compatible = "maxim,max17135",
++ .data = (void *) &max17135_id[0],
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(of, max17135_dt_ids);
++
++
++static struct i2c_driver max17135_driver = {
++ .driver = {
++ .name = "max17135",
++ .owner = THIS_MODULE,
++ .of_match_table = max17135_dt_ids,
++ },
++ .probe = max17135_probe,
++ .remove = max17135_remove,
++ .suspend = max17135_suspend,
++ .resume = max17135_resume,
++ .id_table = max17135_id,
++ .detect = max17135_detect,
++ .address_list = &normal_i2c[0],
++};
++
++static int __init max17135_init(void)
++{
++ return i2c_add_driver(&max17135_driver);
++}
++
++static void __exit max17135_exit(void)
++{
++ i2c_del_driver(&max17135_driver);
++}
++
++/*
++ * Module entry points
++ */
++subsys_initcall(max17135_init);
++module_exit(max17135_exit);
+diff -Nur linux-3.10.30.orig/drivers/mfd/mxc-hdmi-core.c linux-linaro-stable-mx6/drivers/mfd/mxc-hdmi-core.c
+--- linux-3.10.30.orig/drivers/mfd/mxc-hdmi-core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/mxc-hdmi-core.c 2014-05-15 20:33:58.050014240 +0200
+@@ -0,0 +1,775 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/spinlock.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <asm/mach-types.h>
++
++#include <video/mxc_hdmi.h>
++#include <linux/ipu-v3.h>
++#include <video/mxc_edid.h>
++#include "../mxc/ipu3/ipu_prv.h"
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/of_device.h>
++#include <linux/mod_devicetable.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++
++struct mxc_hdmi_data {
++ struct platform_device *pdev;
++ unsigned long __iomem *reg_base;
++ unsigned long reg_phys_base;
++ struct device *dev;
++};
++
++static void __iomem *hdmi_base;
++static struct clk *isfr_clk;
++static struct clk *iahb_clk;
++static spinlock_t irq_spinlock;
++static spinlock_t edid_spinlock;
++static unsigned int sample_rate;
++static unsigned long pixel_clk_rate;
++static struct clk *pixel_clk;
++static int hdmi_ratio;
++int mxc_hdmi_ipu_id;
++int mxc_hdmi_disp_id;
++static struct mxc_edid_cfg hdmi_core_edid_cfg;
++static int hdmi_core_init;
++static unsigned int hdmi_dma_running;
++static struct snd_pcm_substream *hdmi_audio_stream_playback;
++static unsigned int hdmi_cable_state;
++static unsigned int hdmi_blank_state;
++static spinlock_t hdmi_audio_lock, hdmi_blank_state_lock, hdmi_cable_state_lock;
++
++unsigned int hdmi_set_cable_state(unsigned int state)
++{
++ unsigned long flags;
++ struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags);
++ hdmi_cable_state = state;
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
++
++ if (check_hdmi_state() && substream)
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
++ return 0;
++}
++EXPORT_SYMBOL(hdmi_set_cable_state);
++
++unsigned int hdmi_set_blank_state(unsigned int state)
++{
++ unsigned long flags;
++ struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
++
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags);
++ hdmi_blank_state = state;
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
++
++ if (check_hdmi_state() && substream)
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
++
++ return 0;
++}
++EXPORT_SYMBOL(hdmi_set_blank_state);
++
++static void hdmi_audio_abort_stream(struct snd_pcm_substream *substream)
++{
++ unsigned long flags;
++
++ snd_pcm_stream_lock_irqsave(substream, flags);
++
++ if (snd_pcm_running(substream))
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_STOP);
++
++ snd_pcm_stream_unlock_irqrestore(substream, flags);
++}
++
++int mxc_hdmi_abort_stream(void)
++{
++ unsigned long flags;
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ if (hdmi_audio_stream_playback)
++ hdmi_audio_abort_stream(hdmi_audio_stream_playback);
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_hdmi_abort_stream);
++
++int check_hdmi_state(void)
++{
++ unsigned long flags1, flags2;
++ unsigned int ret;
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags1);
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags2);
++
++ ret = hdmi_cable_state && hdmi_blank_state;
++
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags2);
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags1);
++
++ return ret;
++}
++EXPORT_SYMBOL(check_hdmi_state);
++
++int mxc_hdmi_register_audio(struct snd_pcm_substream *substream)
++{
++ unsigned long flags, flags1;
++ int ret = 0;
++
++ snd_pcm_stream_lock_irqsave(substream, flags);
++
++ if (substream && check_hdmi_state()) {
++ spin_lock_irqsave(&hdmi_audio_lock, flags1);
++ if (hdmi_audio_stream_playback) {
++ pr_err("%s unconsist hdmi auido stream!\n", __func__);
++ ret = -EINVAL;
++ }
++ hdmi_audio_stream_playback = substream;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags1);
++ } else
++ ret = -EINVAL;
++
++ snd_pcm_stream_unlock_irqrestore(substream, flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(mxc_hdmi_register_audio);
++
++void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ hdmi_audio_stream_playback = NULL;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++}
++EXPORT_SYMBOL(mxc_hdmi_unregister_audio);
++
++u8 hdmi_readb(unsigned int reg)
++{
++ u8 value;
++
++ value = __raw_readb(hdmi_base + reg);
++
++ return value;
++}
++EXPORT_SYMBOL(hdmi_readb);
++
++#ifdef DEBUG
++static bool overflow_lo;
++static bool overflow_hi;
++
++bool hdmi_check_overflow(void)
++{
++ u8 val, lo, hi;
++
++ val = hdmi_readb(HDMI_IH_FC_STAT2);
++ lo = (val & HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW) != 0;
++ hi = (val & HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW) != 0;
++
++ if ((lo != overflow_lo) || (hi != overflow_hi)) {
++ pr_debug("%s LowPriority=%d HighPriority=%d <=======================\n",
++ __func__, lo, hi);
++ overflow_lo = lo;
++ overflow_hi = hi;
++ return true;
++ }
++ return false;
++}
++#else
++bool hdmi_check_overflow(void)
++{
++ return false;
++}
++#endif
++EXPORT_SYMBOL(hdmi_check_overflow);
++
++void hdmi_writeb(u8 value, unsigned int reg)
++{
++ hdmi_check_overflow();
++ __raw_writeb(value, hdmi_base + reg);
++ hdmi_check_overflow();
++}
++EXPORT_SYMBOL(hdmi_writeb);
++
++void hdmi_mask_writeb(u8 data, unsigned int reg, u8 shift, u8 mask)
++{
++ u8 value = hdmi_readb(reg) & ~mask;
++ value |= (data << shift) & mask;
++ hdmi_writeb(value, reg);
++}
++EXPORT_SYMBOL(hdmi_mask_writeb);
++
++unsigned int hdmi_read4(unsigned int reg)
++{
++ /* read a four byte address from registers */
++ return (hdmi_readb(reg + 3) << 24) |
++ (hdmi_readb(reg + 2) << 16) |
++ (hdmi_readb(reg + 1) << 8) |
++ hdmi_readb(reg);
++}
++EXPORT_SYMBOL(hdmi_read4);
++
++void hdmi_write4(unsigned int value, unsigned int reg)
++{
++ /* write a four byte address to hdmi regs */
++ hdmi_writeb(value & 0xff, reg);
++ hdmi_writeb((value >> 8) & 0xff, reg + 1);
++ hdmi_writeb((value >> 16) & 0xff, reg + 2);
++ hdmi_writeb((value >> 24) & 0xff, reg + 3);
++}
++EXPORT_SYMBOL(hdmi_write4);
++
++static void initialize_hdmi_ih_mutes(void)
++{
++ u8 ih_mute;
++
++ /*
++ * Boot up defaults are:
++ * HDMI_IH_MUTE = 0x03 (disabled)
++ * HDMI_IH_MUTE_* = 0x00 (enabled)
++ */
++
++ /* Disable top level interrupt bits in HDMI block */
++ ih_mute = hdmi_readb(HDMI_IH_MUTE) |
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
++
++ hdmi_writeb(ih_mute, HDMI_IH_MUTE);
++
++ /* by default mask all interrupts */
++ hdmi_writeb(0xff, HDMI_VP_MASK);
++ hdmi_writeb(0xff, HDMI_FC_MASK0);
++ hdmi_writeb(0xff, HDMI_FC_MASK1);
++ hdmi_writeb(0xff, HDMI_FC_MASK2);
++ hdmi_writeb(0xff, HDMI_PHY_MASK0);
++ hdmi_writeb(0xff, HDMI_PHY_I2CM_INT_ADDR);
++ hdmi_writeb(0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
++ hdmi_writeb(0xff, HDMI_AUD_INT);
++ hdmi_writeb(0xff, HDMI_AUD_SPDIFINT);
++ hdmi_writeb(0xff, HDMI_AUD_HBR_MASK);
++ hdmi_writeb(0xff, HDMI_GP_MASK);
++ hdmi_writeb(0xff, HDMI_A_APIINTMSK);
++ hdmi_writeb(0xff, HDMI_CEC_MASK);
++ hdmi_writeb(0xff, HDMI_I2CM_INT);
++ hdmi_writeb(0xff, HDMI_I2CM_CTLINT);
++
++ /* Disable interrupts in the IH_MUTE_* registers */
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT1);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT2);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AS_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_PHY_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_I2CM_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_VP_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++
++ /* Enable top level interrupt bits in HDMI block */
++ ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
++ hdmi_writeb(ih_mute, HDMI_IH_MUTE);
++}
++
++static void hdmi_set_clock_regenerator_n(unsigned int value)
++{
++ u8 val;
++
++ if (!hdmi_dma_running) {
++ hdmi_writeb(value & 0xff, HDMI_AUD_N1);
++ hdmi_writeb(0, HDMI_AUD_N2);
++ hdmi_writeb(0, HDMI_AUD_N3);
++ }
++
++ hdmi_writeb(value & 0xff, HDMI_AUD_N1);
++ hdmi_writeb((value >> 8) & 0xff, HDMI_AUD_N2);
++ hdmi_writeb((value >> 16) & 0x0f, HDMI_AUD_N3);
++
++ /* nshift factor = 0 */
++ val = hdmi_readb(HDMI_AUD_CTS3);
++ val &= ~HDMI_AUD_CTS3_N_SHIFT_MASK;
++ hdmi_writeb(val, HDMI_AUD_CTS3);
++}
++
++static void hdmi_set_clock_regenerator_cts(unsigned int cts)
++{
++ u8 val;
++
++ if (!hdmi_dma_running) {
++ hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
++ hdmi_writeb(0, HDMI_AUD_CTS2);
++ hdmi_writeb(0, HDMI_AUD_CTS3);
++ }
++
++ /* Must be set/cleared first */
++ val = hdmi_readb(HDMI_AUD_CTS3);
++ val &= ~HDMI_AUD_CTS3_CTS_MANUAL;
++ hdmi_writeb(val, HDMI_AUD_CTS3);
++
++ hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
++ hdmi_writeb((cts >> 8) & 0xff, HDMI_AUD_CTS2);
++ hdmi_writeb(((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
++ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
++}
++
++static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
++ unsigned int ratio)
++{
++ unsigned int n = (128 * freq) / 1000;
++
++ switch (freq) {
++ case 32000:
++ if (pixel_clk == 25174000)
++ n = (ratio == 150) ? 9152 : 4576;
++ else if (pixel_clk == 27020000)
++ n = (ratio == 150) ? 8192 : 4096;
++ else if (pixel_clk == 74170000 || pixel_clk == 148350000)
++ n = 11648;
++ else if (pixel_clk == 297000000)
++ n = (ratio == 150) ? 6144 : 3072;
++ else
++ n = 4096;
++ break;
++
++ case 44100:
++ if (pixel_clk == 25174000)
++ n = 7007;
++ else if (pixel_clk == 74170000)
++ n = 17836;
++ else if (pixel_clk == 148350000)
++ n = (ratio == 150) ? 17836 : 8918;
++ else if (pixel_clk == 297000000)
++ n = (ratio == 150) ? 9408 : 4704;
++ else
++ n = 6272;
++ break;
++
++ case 48000:
++ if (pixel_clk == 25174000)
++ n = (ratio == 150) ? 9152 : 6864;
++ else if (pixel_clk == 27020000)
++ n = (ratio == 150) ? 8192 : 6144;
++ else if (pixel_clk == 74170000)
++ n = 11648;
++ else if (pixel_clk == 148350000)
++ n = (ratio == 150) ? 11648 : 5824;
++ else if (pixel_clk == 297000000)
++ n = (ratio == 150) ? 10240 : 5120;
++ else
++ n = 6144;
++ break;
++
++ case 88200:
++ n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
++ break;
++
++ case 96000:
++ n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
++ break;
++
++ case 176400:
++ n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
++ break;
++
++ case 192000:
++ n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
++ break;
++
++ default:
++ break;
++ }
++
++ return n;
++}
++
++static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
++ unsigned int ratio)
++{
++ unsigned int cts = 0;
++ switch (freq) {
++ case 32000:
++ if (pixel_clk == 297000000) {
++ cts = 222750;
++ break;
++ } else if (pixel_clk == 25174000) {
++ cts = 28125;
++ break;
++ }
++ case 48000:
++ case 96000:
++ case 192000:
++ switch (pixel_clk) {
++ case 25200000:
++ case 27000000:
++ case 54000000:
++ case 74250000:
++ case 148500000:
++ cts = pixel_clk / 1000;
++ break;
++ case 297000000:
++ cts = 247500;
++ break;
++ case 25174000:
++ cts = 28125l;
++ break;
++ /*
++ * All other TMDS clocks are not supported by
++ * DWC_hdmi_tx. The TMDS clocks divided or
++ * multiplied by 1,001 coefficients are not
++ * supported.
++ */
++ default:
++ break;
++ }
++ break;
++ case 44100:
++ case 88200:
++ case 176400:
++ switch (pixel_clk) {
++ case 25200000:
++ cts = 28000;
++ break;
++ case 25174000:
++ cts = 31250;
++ break;
++ case 27000000:
++ cts = 30000;
++ break;
++ case 54000000:
++ cts = 60000;
++ break;
++ case 74250000:
++ cts = 82500;
++ break;
++ case 148500000:
++ cts = 165000;
++ break;
++ case 297000000:
++ cts = 247500;
++ break;
++ default:
++ break;
++ }
++ break;
++ default:
++ break;
++ }
++ if (ratio == 100)
++ return cts;
++ else
++ return (cts * ratio) / 100;
++}
++
++static void hdmi_set_clk_regenerator(void)
++{
++ unsigned int clk_n, clk_cts;
++
++ clk_n = hdmi_compute_n(sample_rate, pixel_clk_rate, hdmi_ratio);
++ clk_cts = hdmi_compute_cts(sample_rate, pixel_clk_rate, hdmi_ratio);
++
++ if (clk_cts == 0) {
++ pr_debug("%s: pixel clock not supported: %d\n",
++ __func__, (int)pixel_clk_rate);
++ return;
++ }
++
++ pr_debug("%s: samplerate=%d ratio=%d pixelclk=%d N=%d cts=%d\n",
++ __func__, sample_rate, hdmi_ratio, (int)pixel_clk_rate,
++ clk_n, clk_cts);
++
++ hdmi_set_clock_regenerator_cts(clk_cts);
++ hdmi_set_clock_regenerator_n(clk_n);
++}
++
++static int hdmi_core_get_of_property(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++ int ipu_id, disp_id;
++
++ err = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "disp_id", &disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
++ return err;
++ }
++
++ mxc_hdmi_ipu_id = ipu_id;
++ mxc_hdmi_disp_id = disp_id;
++
++ return err;
++}
++
++/* Need to run this before phy is enabled the first time to prevent
++ * overflow condition in HDMI_IH_FC_STAT2 */
++void hdmi_init_clk_regenerator(void)
++{
++ if (pixel_clk_rate == 0) {
++ pixel_clk_rate = 74250000;
++ hdmi_set_clk_regenerator();
++ }
++}
++EXPORT_SYMBOL(hdmi_init_clk_regenerator);
++
++void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock)
++{
++
++ /* Translate pixel clock in ps (pico seconds) to Hz */
++ pixel_clk_rate = PICOS2KHZ(pixclock) * 1000UL;
++ hdmi_set_clk_regenerator();
++}
++EXPORT_SYMBOL(hdmi_clk_regenerator_update_pixel_clock);
++
++void hdmi_set_dma_mode(unsigned int dma_running)
++{
++ hdmi_dma_running = dma_running;
++ hdmi_set_clk_regenerator();
++}
++EXPORT_SYMBOL(hdmi_set_dma_mode);
++
++void hdmi_set_sample_rate(unsigned int rate)
++{
++ sample_rate = rate;
++}
++EXPORT_SYMBOL(hdmi_set_sample_rate);
++
++void hdmi_set_edid_cfg(struct mxc_edid_cfg *cfg)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&edid_spinlock, flags);
++ memcpy(&hdmi_core_edid_cfg, cfg, sizeof(struct mxc_edid_cfg));
++ spin_unlock_irqrestore(&edid_spinlock, flags);
++}
++EXPORT_SYMBOL(hdmi_set_edid_cfg);
++
++void hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&edid_spinlock, flags);
++ memcpy(cfg, &hdmi_core_edid_cfg, sizeof(struct mxc_edid_cfg));
++ spin_unlock_irqrestore(&edid_spinlock, flags);
++}
++EXPORT_SYMBOL(hdmi_get_edid_cfg);
++
++void hdmi_set_registered(int registered)
++{
++ hdmi_core_init = registered;
++}
++EXPORT_SYMBOL(hdmi_set_registered);
++
++int hdmi_get_registered(void)
++{
++ return hdmi_core_init;
++}
++EXPORT_SYMBOL(hdmi_get_registered);
++
++static int mxc_hdmi_core_probe(struct platform_device *pdev)
++{
++ struct mxc_hdmi_data *hdmi_data;
++ struct resource *res;
++ unsigned long flags;
++ int ret = 0;
++
++#ifdef DEBUG
++ overflow_lo = false;
++ overflow_hi = false;
++#endif
++
++ hdmi_core_init = 0;
++ hdmi_dma_running = 0;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENOENT;
++
++ ret = hdmi_core_get_of_property(pdev);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get hdmi of property fail\n");
++ return -ENOENT;
++ }
++
++ hdmi_data = devm_kzalloc(&pdev->dev, sizeof(struct mxc_hdmi_data), GFP_KERNEL);
++ if (!hdmi_data) {
++ dev_err(&pdev->dev, "Couldn't allocate mxc hdmi mfd device\n");
++ return -ENOMEM;
++ }
++ hdmi_data->pdev = pdev;
++
++ pixel_clk = NULL;
++ sample_rate = 48000;
++ pixel_clk_rate = 0;
++ hdmi_ratio = 100;
++
++ spin_lock_init(&irq_spinlock);
++ spin_lock_init(&edid_spinlock);
++
++
++ spin_lock_init(&hdmi_cable_state_lock);
++ spin_lock_init(&hdmi_blank_state_lock);
++ spin_lock_init(&hdmi_audio_lock);
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags);
++ hdmi_cable_state = 0;
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
++
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags);
++ hdmi_blank_state = 0;
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
++
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ hdmi_audio_stream_playback = NULL;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++
++ isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr");
++ if (IS_ERR(isfr_clk)) {
++ ret = PTR_ERR(isfr_clk);
++ dev_err(&hdmi_data->pdev->dev,
++ "Unable to get HDMI isfr clk: %d\n", ret);
++ goto eclkg;
++ }
++
++ ret = clk_prepare_enable(isfr_clk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
++ goto eclke;
++ }
++
++ pr_debug("%s isfr_clk:%d\n", __func__,
++ (int)clk_get_rate(isfr_clk));
++
++ iahb_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_iahb");
++ if (IS_ERR(iahb_clk)) {
++ ret = PTR_ERR(iahb_clk);
++ dev_err(&hdmi_data->pdev->dev,
++ "Unable to get HDMI iahb clk: %d\n", ret);
++ goto eclkg2;
++ }
++
++ ret = clk_prepare_enable(iahb_clk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
++ goto eclke2;
++ }
++
++ hdmi_data->reg_phys_base = res->start;
++ if (!request_mem_region(res->start, resource_size(res),
++ dev_name(&pdev->dev))) {
++ dev_err(&pdev->dev, "request_mem_region failed\n");
++ ret = -EBUSY;
++ goto emem;
++ }
++
++ hdmi_data->reg_base = ioremap(res->start, resource_size(res));
++ if (!hdmi_data->reg_base) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto eirq;
++ }
++ hdmi_base = hdmi_data->reg_base;
++
++ pr_debug("\n%s hdmi hw base = 0x%08x\n\n", __func__, (int)res->start);
++
++ initialize_hdmi_ih_mutes();
++
++ /* Disable HDMI clocks until video/audio sub-drivers are initialized */
++ clk_disable_unprepare(isfr_clk);
++ clk_disable_unprepare(iahb_clk);
++
++ /* Replace platform data coming in with a local struct */
++ platform_set_drvdata(pdev, hdmi_data);
++
++ return ret;
++
++eirq:
++ release_mem_region(res->start, resource_size(res));
++emem:
++ clk_disable_unprepare(iahb_clk);
++eclke2:
++ clk_put(iahb_clk);
++eclkg2:
++ clk_disable_unprepare(isfr_clk);
++eclke:
++ clk_put(isfr_clk);
++eclkg:
++ return ret;
++}
++
++
++static int __exit mxc_hdmi_core_remove(struct platform_device *pdev)
++{
++ struct mxc_hdmi_data *hdmi_data = platform_get_drvdata(pdev);
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ iounmap(hdmi_data->reg_base);
++ release_mem_region(res->start, resource_size(res));
++
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx6q-hdmi-core", },
++ { .compatible = "fsl,imx6dl-hdmi-core", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_hdmi_core_driver = {
++ .driver = {
++ .name = "mxc_hdmi_core",
++ .of_match_table = imx_hdmi_dt_ids,
++ .owner = THIS_MODULE,
++ },
++ .remove = __exit_p(mxc_hdmi_core_remove),
++};
++
++static int __init mxc_hdmi_core_init(void)
++{
++ return platform_driver_probe(&mxc_hdmi_core_driver,
++ mxc_hdmi_core_probe);
++}
++
++static void __exit mxc_hdmi_core_exit(void)
++{
++ platform_driver_unregister(&mxc_hdmi_core_driver);
++}
++
++subsys_initcall(mxc_hdmi_core_init);
++module_exit(mxc_hdmi_core_exit);
++
++MODULE_DESCRIPTION("Core driver for Freescale i.Mx on-chip HDMI");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mfd/si476x-cmd.c linux-linaro-stable-mx6/drivers/mfd/si476x-cmd.c
+--- linux-3.10.30.orig/drivers/mfd/si476x-cmd.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/si476x-cmd.c 2014-05-15 20:33:58.066014355 +0200
+@@ -303,13 +303,13 @@
+ * possible racing conditions when working in polling mode */
+ atomic_set(&core->cts, 0);
+
+- /* if (unlikely(command == CMD_POWER_DOWN) */
+- if (!wait_event_timeout(core->command,
+- atomic_read(&core->cts),
+- usecs_to_jiffies(usecs) + 1))
+- dev_warn(&core->client->dev,
+- "(%s) [CMD 0x%02x] Answer timeout.\n",
+- __func__, command);
++ if (!(command == CMD_POWER_DOWN))
++ if (!wait_event_timeout(core->command,
++ atomic_read(&core->cts),
++ usecs_to_jiffies(usecs) + 1))
++ dev_warn(&core->client->dev,
++ "(%s) [CMD 0x%02x] Answer timeout.\n",
++ __func__, command);
+
+ /*
+ When working in polling mode, for some reason the tuner will
+diff -Nur linux-3.10.30.orig/drivers/mfd/si476x-i2c.c linux-linaro-stable-mx6/drivers/mfd/si476x-i2c.c
+--- linux-3.10.30.orig/drivers/mfd/si476x-i2c.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/si476x-i2c.c 2014-05-15 20:33:58.066014355 +0200
+@@ -303,7 +303,7 @@
+ */
+ udelay(100);
+
+- err = si476x_core_start(core, false);
++ err = si476x_core_start(core, true);
+ if (err < 0)
+ goto disable_regulators;
+
+@@ -312,7 +312,7 @@
+
+ case SI476X_POWER_DOWN:
+ core->power_state = next_state;
+- err = si476x_core_stop(core, false);
++ err = si476x_core_stop(core, true);
+ if (err < 0)
+ core->power_state = SI476X_POWER_INCONSISTENT;
+ disable_regulators:
+@@ -740,8 +740,15 @@
+ memcpy(&core->pinmux, &pdata->pinmux,
+ sizeof(struct si476x_pinmux));
+ } else {
+- dev_err(&client->dev, "No platform data provided\n");
+- return -EINVAL;
++ dev_warn(&client->dev, "Using default platform data.\n");
++ core->power_up_parameters.xcload = 0x28;
++ core->power_up_parameters.func = SI476X_FUNC_FM_RECEIVER;
++ core->power_up_parameters.freq = SI476X_FREQ_37P209375_MHZ;
++ core->diversity_mode = SI476X_PHDIV_DISABLED;
++ core->pinmux.dclk = SI476X_DCLK_DAUDIO;
++ core->pinmux.dfs = SI476X_DFS_DAUDIO;
++ core->pinmux.dout = SI476X_DOUT_I2S_OUTPUT;
++ core->pinmux.xout = SI476X_XOUT_TRISTATE;
+ }
+
+ core->supplies[0].supply = "vd";
+@@ -799,6 +806,10 @@
+
+ core->chip_id = id->driver_data;
+
++ /* Power down si476x first */
++ core->power_state = SI476X_POWER_UP_FULL;
++ si476x_core_set_power_state(core, SI476X_POWER_DOWN);
++
+ rval = si476x_core_get_revision_info(core);
+ if (rval < 0) {
+ rval = -ENODEV;
+diff -Nur linux-3.10.30.orig/drivers/mfd/si476x-prop.c linux-linaro-stable-mx6/drivers/mfd/si476x-prop.c
+--- linux-3.10.30.orig/drivers/mfd/si476x-prop.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/si476x-prop.c 2014-05-15 20:33:58.066014355 +0200
+@@ -217,15 +217,36 @@
+ return 0;
+ }
+
++static bool si476x_core_regmap_volatile_register(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case SI476X_PROP_DIGITAL_IO_OUTPUT_SAMPLE_RATE:
++ case SI476X_PROP_DIGITAL_IO_OUTPUT_FORMAT:
++ return false;
++ default:
++ return true;
++ }
++
++ return true;
++}
++
++/* These two register is used by the codec, so add reg_default here */
++static struct reg_default si476x_core_reg[] = {
++ { 0x202, 0xBB80 },
++ { 0x203, 0x1700 },
++};
+
+ static const struct regmap_config si476x_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 16,
+
+ .max_register = 0x4003,
++ .reg_defaults = si476x_core_reg,
++ .num_reg_defaults = ARRAY_SIZE(si476x_core_reg),
+
+ .writeable_reg = si476x_core_regmap_writable_register,
+ .readable_reg = si476x_core_regmap_readable_register,
++ .volatile_reg = si476x_core_regmap_volatile_register,
+
+ .reg_read = si476x_core_regmap_read,
+ .reg_write = si476x_core_regmap_write,
+diff -Nur linux-3.10.30.orig/drivers/mfd/vexpress-config.c linux-linaro-stable-mx6/drivers/mfd/vexpress-config.c
+--- linux-3.10.30.orig/drivers/mfd/vexpress-config.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/vexpress-config.c 2014-05-15 20:33:58.090014528 +0200
+@@ -86,29 +86,13 @@
+ }
+ EXPORT_SYMBOL(vexpress_config_bridge_unregister);
+
+-
+-struct vexpress_config_func {
+- struct vexpress_config_bridge *bridge;
+- void *func;
+-};
+-
+-struct vexpress_config_func *__vexpress_config_func_get(struct device *dev,
+- struct device_node *node)
++static struct vexpress_config_bridge *
++ vexpress_config_bridge_find(struct device_node *node)
+ {
+- struct device_node *bridge_node;
+- struct vexpress_config_func *func;
+ int i;
++ struct vexpress_config_bridge *res = NULL;
++ struct device_node *bridge_node = of_node_get(node);
+
+- if (WARN_ON(dev && node && dev->of_node != node))
+- return NULL;
+- if (dev && !node)
+- node = dev->of_node;
+-
+- func = kzalloc(sizeof(*func), GFP_KERNEL);
+- if (!func)
+- return NULL;
+-
+- bridge_node = of_node_get(node);
+ while (bridge_node) {
+ const __be32 *prop = of_get_property(bridge_node,
+ "arm,vexpress,config-bridge", NULL);
+@@ -129,13 +113,46 @@
+
+ if (test_bit(i, vexpress_config_bridges_map) &&
+ bridge->node == bridge_node) {
+- func->bridge = bridge;
+- func->func = bridge->info->func_get(dev, node);
++ res = bridge;
+ break;
+ }
+ }
+ mutex_unlock(&vexpress_config_bridges_mutex);
+
++ return res;
++}
++
++
++struct vexpress_config_func {
++ struct vexpress_config_bridge *bridge;
++ void *func;
++};
++
++struct vexpress_config_func *__vexpress_config_func_get(
++ struct vexpress_config_bridge *bridge,
++ struct device *dev,
++ struct device_node *node,
++ const char *id)
++{
++ struct vexpress_config_func *func;
++
++ if (WARN_ON(dev && node && dev->of_node != node))
++ return NULL;
++ if (dev && !node)
++ node = dev->of_node;
++
++ if (!bridge)
++ bridge = vexpress_config_bridge_find(node);
++ if (!bridge)
++ return NULL;
++
++ func = kzalloc(sizeof(*func), GFP_KERNEL);
++ if (!func)
++ return NULL;
++
++ func->bridge = bridge;
++ func->func = bridge->info->func_get(dev, node, id);
++
+ if (!func->func) {
+ of_node_put(node);
+ kfree(func);
+diff -Nur linux-3.10.30.orig/drivers/mfd/vexpress-spc.c linux-linaro-stable-mx6/drivers/mfd/vexpress-spc.c
+--- linux-3.10.30.orig/drivers/mfd/vexpress-spc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/vexpress-spc.c 2014-05-15 20:33:58.090014528 +0200
+@@ -0,0 +1,633 @@
++/*
++ * Versatile Express Serial Power Controller (SPC) support
++ *
++ * Copyright (C) 2013 ARM Ltd.
++ *
++ * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
++ * Achin Gupta <achin.gupta@arm.com>
++ * Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/slab.h>
++#include <linux/vexpress.h>
++
++#include <asm/cacheflush.h>
++
++#define SCC_CFGREG19 0x120
++#define SCC_CFGREG20 0x124
++#define A15_CONF 0x400
++#define A7_CONF 0x500
++#define SYS_INFO 0x700
++#define PERF_LVL_A15 0xB00
++#define PERF_REQ_A15 0xB04
++#define PERF_LVL_A7 0xB08
++#define PERF_REQ_A7 0xB0c
++#define SYS_CFGCTRL 0xB10
++#define SYS_CFGCTRL_REQ 0xB14
++#define PWC_STATUS 0xB18
++#define PWC_FLAG 0xB1c
++#define WAKE_INT_MASK 0xB24
++#define WAKE_INT_RAW 0xB28
++#define WAKE_INT_STAT 0xB2c
++#define A15_PWRDN_EN 0xB30
++#define A7_PWRDN_EN 0xB34
++#define A7_PWRDNACK 0xB54
++#define A15_BX_ADDR0 0xB68
++#define SYS_CFG_WDATA 0xB70
++#define SYS_CFG_RDATA 0xB74
++#define A7_BX_ADDR0 0xB78
++
++#define GBL_WAKEUP_INT_MSK (0x3 << 10)
++
++#define CLKF_SHIFT 16
++#define CLKF_MASK 0x1FFF
++#define CLKR_SHIFT 0
++#define CLKR_MASK 0x3F
++#define CLKOD_SHIFT 8
++#define CLKOD_MASK 0xF
++
++#define OPP_FUNCTION 6
++#define OPP_BASE_DEVICE 0x300
++#define OPP_A15_OFFSET 0x4
++#define OPP_A7_OFFSET 0xc
++
++#define SYS_CFGCTRL_START (1 << 31)
++#define SYS_CFGCTRL_WRITE (1 << 30)
++#define SYS_CFGCTRL_FUNC(n) (((n) & 0x3f) << 20)
++#define SYS_CFGCTRL_DEVICE(n) (((n) & 0xfff) << 0)
++
++#define MAX_OPPS 8
++#define MAX_CLUSTERS 2
++
++enum {
++ A15_OPP_TYPE = 0,
++ A7_OPP_TYPE = 1,
++ SYS_CFGCTRL_TYPE = 2,
++ INVALID_TYPE
++};
++
++#define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
++#define STAT_ERR(type) ((1 << 1) << (type << 2))
++#define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type))
++
++struct vexpress_spc_drvdata {
++ void __iomem *baseaddr;
++ u32 a15_clusid;
++ int irq;
++ u32 cur_req_type;
++ u32 freqs[MAX_CLUSTERS][MAX_OPPS];
++ int freqs_cnt[MAX_CLUSTERS];
++};
++
++enum spc_func_type {
++ CONFIG_FUNC = 0,
++ PERF_FUNC = 1,
++};
++
++struct vexpress_spc_func {
++ enum spc_func_type type;
++ u32 function;
++ u32 device;
++};
++
++static struct vexpress_spc_drvdata *info;
++static u32 *vexpress_spc_config_data;
++static struct vexpress_config_bridge *vexpress_spc_config_bridge;
++static struct vexpress_config_func *opp_func, *perf_func;
++
++static int vexpress_spc_load_result = -EAGAIN;
++
++static bool vexpress_spc_initialized(void)
++{
++ return vexpress_spc_load_result == 0;
++}
++
++/**
++ * vexpress_spc_write_resume_reg() - set the jump address used for warm boot
++ *
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
++ * @addr: physical resume address
++ */
++void vexpress_spc_write_resume_reg(u32 cluster, u32 cpu, u32 addr)
++{
++ void __iomem *baseaddr;
++
++ if (WARN_ON_ONCE(cluster >= MAX_CLUSTERS))
++ return;
++
++ if (cluster != info->a15_clusid)
++ baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
++ else
++ baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
++
++ writel_relaxed(addr, baseaddr);
++}
++
++/**
++ * vexpress_spc_get_nb_cpus() - get number of cpus in a cluster
++ *
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ *
++ * Return: number of cpus in the cluster
++ * -EINVAL if cluster number invalid
++ */
++int vexpress_spc_get_nb_cpus(u32 cluster)
++{
++ u32 val;
++
++ if (WARN_ON_ONCE(cluster >= MAX_CLUSTERS))
++ return -EINVAL;
++
++ val = readl_relaxed(info->baseaddr + SYS_INFO);
++ val = (cluster != info->a15_clusid) ? (val >> 20) : (val >> 16);
++ return val & 0xf;
++}
++EXPORT_SYMBOL_GPL(vexpress_spc_get_nb_cpus);
++
++/**
++ * vexpress_spc_get_performance - get current performance level of cluster
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ * @freq: pointer to the performance level to be assigned
++ *
++ * Return: 0 on success
++ * < 0 on read error
++ */
++int vexpress_spc_get_performance(u32 cluster, u32 *freq)
++{
++ u32 perf_cfg_reg;
++ int perf, ret;
++
++ if (!vexpress_spc_initialized() || (cluster >= MAX_CLUSTERS))
++ return -EINVAL;
++
++ perf_cfg_reg = cluster != info->a15_clusid ? PERF_LVL_A7 : PERF_LVL_A15;
++ ret = vexpress_config_read(perf_func, perf_cfg_reg, &perf);
++
++ if (!ret)
++ *freq = info->freqs[cluster][perf];
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(vexpress_spc_get_performance);
++
++/**
++ * vexpress_spc_get_perf_index - get performance level corresponding to
++ * a frequency
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ * @freq: frequency to be looked-up
++ *
++ * Return: perf level index on success
++ * -EINVAL on error
++ */
++static int vexpress_spc_find_perf_index(u32 cluster, u32 freq)
++{
++ int idx;
++
++ for (idx = 0; idx < info->freqs_cnt[cluster]; idx++)
++ if (info->freqs[cluster][idx] == freq)
++ break;
++ return (idx == info->freqs_cnt[cluster]) ? -EINVAL : idx;
++}
++
++/**
++ * vexpress_spc_set_performance - set current performance level of cluster
++ *
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ * @freq: performance level to be programmed
++ *
++ * Returns: 0 on success
++ * < 0 on write error
++ */
++int vexpress_spc_set_performance(u32 cluster, u32 freq)
++{
++ int ret, perf, offset;
++
++ if (!vexpress_spc_initialized() || (cluster >= MAX_CLUSTERS))
++ return -EINVAL;
++
++ offset = (cluster != info->a15_clusid) ? PERF_LVL_A7 : PERF_LVL_A15;
++
++ perf = vexpress_spc_find_perf_index(cluster, freq);
++
++ if (perf < 0 || perf >= MAX_OPPS)
++ return -EINVAL;
++
++ ret = vexpress_config_write(perf_func, offset, perf);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(vexpress_spc_set_performance);
++
++static void vexpress_spc_set_wake_intr(u32 mask)
++{
++ writel_relaxed(mask & VEXPRESS_SPC_WAKE_INTR_MASK,
++ info->baseaddr + WAKE_INT_MASK);
++}
++
++static inline void reg_bitmask(u32 *reg, u32 mask, bool set)
++{
++ if (set)
++ *reg |= mask;
++ else
++ *reg &= ~mask;
++}
++
++/**
++ * vexpress_spc_set_global_wakeup_intr()
++ *
++ * Function to set/clear global wakeup IRQs. Not protected by locking since
++ * it might be used in code paths where normal cacheable locks are not
++ * working. Locking must be provided by the caller to ensure atomicity.
++ *
++ * @set: if true, global wake-up IRQs are set, if false they are cleared
++ */
++void vexpress_spc_set_global_wakeup_intr(bool set)
++{
++ u32 wake_int_mask_reg = 0;
++
++ wake_int_mask_reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
++ reg_bitmask(&wake_int_mask_reg, GBL_WAKEUP_INT_MSK, set);
++ vexpress_spc_set_wake_intr(wake_int_mask_reg);
++}
++
++/**
++ * vexpress_spc_set_cpu_wakeup_irq()
++ *
++ * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
++ * it might be used in code paths where normal cacheable locks are not
++ * working. Locking must be provided by the caller to ensure atomicity.
++ *
++ * @cpu: mpidr[7:0] bitfield describing cpu affinity level
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ * @set: if true, wake-up IRQs are set, if false they are cleared
++ */
++void vexpress_spc_set_cpu_wakeup_irq(u32 cpu, u32 cluster, bool set)
++{
++ u32 mask = 0;
++ u32 wake_int_mask_reg = 0;
++
++ mask = 1 << cpu;
++ if (info->a15_clusid != cluster)
++ mask <<= 4;
++
++ wake_int_mask_reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
++ reg_bitmask(&wake_int_mask_reg, mask, set);
++ vexpress_spc_set_wake_intr(wake_int_mask_reg);
++}
++
++/**
++ * vexpress_spc_powerdown_enable()
++ *
++ * Function to enable/disable cluster powerdown. Not protected by locking
++ * since it might be used in code paths where normal cacheable locks are not
++ * working. Locking must be provided by the caller to ensure atomicity.
++ *
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ * @enable: if true enables powerdown, if false disables it
++ */
++void vexpress_spc_powerdown_enable(u32 cluster, bool enable)
++{
++ u32 pwdrn_reg = 0;
++
++ if (cluster >= MAX_CLUSTERS)
++ return;
++ pwdrn_reg = cluster != info->a15_clusid ? A7_PWRDN_EN : A15_PWRDN_EN;
++ writel_relaxed(enable, info->baseaddr + pwdrn_reg);
++}
++
++irqreturn_t vexpress_spc_irq_handler(int irq, void *data)
++{
++ int ret;
++ u32 status = readl_relaxed(info->baseaddr + PWC_STATUS);
++
++ if (!(status & RESPONSE_MASK(info->cur_req_type)))
++ return IRQ_NONE;
++
++ if ((status == STAT_COMPLETE(SYS_CFGCTRL_TYPE))
++ && vexpress_spc_config_data) {
++ *vexpress_spc_config_data =
++ readl_relaxed(info->baseaddr + SYS_CFG_RDATA);
++ vexpress_spc_config_data = NULL;
++ }
++
++ ret = STAT_COMPLETE(info->cur_req_type) ? 0 : -EIO;
++ info->cur_req_type = INVALID_TYPE;
++ vexpress_config_complete(vexpress_spc_config_bridge, ret);
++ return IRQ_HANDLED;
++}
++
++/**
++ * Based on the firmware documentation, this is always fixed to 20
++ * All the 4 OSC: A15 PLL0/1, A7 PLL0/1 must be programmed same
++ * values for both control and value registers.
++ * This function uses A15 PLL 0 registers to compute multiple factor
++ * F out = F in * (CLKF + 1) / ((CLKOD + 1) * (CLKR + 1))
++ */
++static inline int __get_mult_factor(void)
++{
++ int i_div, o_div, f_div;
++ u32 tmp;
++
++ tmp = readl(info->baseaddr + SCC_CFGREG19);
++ f_div = (tmp >> CLKF_SHIFT) & CLKF_MASK;
++
++ tmp = readl(info->baseaddr + SCC_CFGREG20);
++ o_div = (tmp >> CLKOD_SHIFT) & CLKOD_MASK;
++ i_div = (tmp >> CLKR_SHIFT) & CLKR_MASK;
++
++ return (f_div + 1) / ((o_div + 1) * (i_div + 1));
++}
++
++/**
++ * vexpress_spc_populate_opps() - initialize opp tables from microcontroller
++ *
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ *
++ * Return: 0 on success
++ * < 0 on error
++ */
++static int vexpress_spc_populate_opps(u32 cluster)
++{
++ u32 data = 0, ret, i, offset;
++ int mult_fact = __get_mult_factor();
++
++ if (WARN_ON_ONCE(cluster >= MAX_CLUSTERS))
++ return -EINVAL;
++
++ offset = cluster != info->a15_clusid ? OPP_A7_OFFSET : OPP_A15_OFFSET;
++ for (i = 0; i < MAX_OPPS; i++) {
++ ret = vexpress_config_read(opp_func, i + offset, &data);
++ if (!ret)
++ info->freqs[cluster][i] = (data & 0xFFFFF) * mult_fact;
++ else
++ break;
++ }
++
++ info->freqs_cnt[cluster] = i;
++ return ret;
++}
++
++/**
++ * vexpress_spc_get_freq_table() - Retrieve a pointer to the frequency
++ * table for a given cluster
++ *
++ * @cluster: mpidr[15:8] bitfield describing cluster affinity level
++ * @fptr: pointer to be initialized
++ * Return: operating points count on success
++ * -EINVAL on pointer error
++ */
++int vexpress_spc_get_freq_table(u32 cluster, u32 **fptr)
++{
++ if (WARN_ON_ONCE(!fptr || cluster >= MAX_CLUSTERS))
++ return -EINVAL;
++ *fptr = info->freqs[cluster];
++ return info->freqs_cnt[cluster];
++}
++EXPORT_SYMBOL_GPL(vexpress_spc_get_freq_table);
++
++static void *vexpress_spc_func_get(struct device *dev,
++ struct device_node *node, const char *id)
++{
++ struct vexpress_spc_func *spc_func;
++ u32 func_device[2];
++ int err = 0;
++
++ spc_func = kzalloc(sizeof(*spc_func), GFP_KERNEL);
++ if (!spc_func)
++ return NULL;
++
++ if (strcmp(id, "opp") == 0) {
++ spc_func->type = CONFIG_FUNC;
++ spc_func->function = OPP_FUNCTION;
++ spc_func->device = OPP_BASE_DEVICE;
++ } else if (strcmp(id, "perf") == 0) {
++ spc_func->type = PERF_FUNC;
++ } else if (node) {
++ of_node_get(node);
++ err = of_property_read_u32_array(node,
++ "arm,vexpress-sysreg,func", func_device,
++ ARRAY_SIZE(func_device));
++ of_node_put(node);
++ spc_func->type = CONFIG_FUNC;
++ spc_func->function = func_device[0];
++ spc_func->device = func_device[1];
++ }
++
++ if (WARN_ON(err)) {
++ kfree(spc_func);
++ return NULL;
++ }
++
++ pr_debug("func 0x%p = 0x%x, %d %d\n", spc_func,
++ spc_func->function,
++ spc_func->device,
++ spc_func->type);
++
++ return spc_func;
++}
++
++static void vexpress_spc_func_put(void *func)
++{
++ kfree(func);
++}
++
++static int vexpress_spc_func_exec(void *func, int offset, bool write,
++ u32 *data)
++{
++ struct vexpress_spc_func *spc_func = func;
++ u32 command;
++
++ if (!data)
++ return -EINVAL;
++ /*
++ * Setting and retrieval of operating points is not part of
++ * DCC config interface. It was made to go through the same
++ * code path so that requests to the M3 can be serialized
++ * properly with config reads/writes through the common
++ * vexpress config interface
++ */
++ switch (spc_func->type) {
++ case PERF_FUNC:
++ if (write) {
++ info->cur_req_type = (offset == PERF_LVL_A15) ?
++ A15_OPP_TYPE : A7_OPP_TYPE;
++ writel_relaxed(*data, info->baseaddr + offset);
++ return VEXPRESS_CONFIG_STATUS_WAIT;
++ } else {
++ *data = readl_relaxed(info->baseaddr + offset);
++ return VEXPRESS_CONFIG_STATUS_DONE;
++ }
++ case CONFIG_FUNC:
++ info->cur_req_type = SYS_CFGCTRL_TYPE;
++
++ command = SYS_CFGCTRL_START;
++ command |= write ? SYS_CFGCTRL_WRITE : 0;
++ command |= SYS_CFGCTRL_FUNC(spc_func->function);
++ command |= SYS_CFGCTRL_DEVICE(spc_func->device + offset);
++
++ pr_debug("command %x\n", command);
++
++ if (!write)
++ vexpress_spc_config_data = data;
++ else
++ writel_relaxed(*data, info->baseaddr + SYS_CFG_WDATA);
++ writel_relaxed(command, info->baseaddr + SYS_CFGCTRL);
++
++ return VEXPRESS_CONFIG_STATUS_WAIT;
++ default:
++ return -EINVAL;
++ }
++}
++
++struct vexpress_config_bridge_info vexpress_spc_config_bridge_info = {
++ .name = "vexpress-spc",
++ .func_get = vexpress_spc_func_get,
++ .func_put = vexpress_spc_func_put,
++ .func_exec = vexpress_spc_func_exec,
++};
++
++static const struct of_device_id vexpress_spc_ids[] __initconst = {
++ { .compatible = "arm,vexpress-spc,v2p-ca15_a7" },
++ { .compatible = "arm,vexpress-spc" },
++ {},
++};
++
++static int __init vexpress_spc_init(void)
++{
++ int ret;
++ struct device_node *node = of_find_matching_node(NULL,
++ vexpress_spc_ids);
++
++ if (!node)
++ return -ENODEV;
++
++ info = kzalloc(sizeof(*info), GFP_KERNEL);
++ if (!info) {
++ pr_err("%s: unable to allocate mem\n", __func__);
++ return -ENOMEM;
++ }
++ info->cur_req_type = INVALID_TYPE;
++
++ info->baseaddr = of_iomap(node, 0);
++ if (WARN_ON(!info->baseaddr)) {
++ ret = -ENXIO;
++ goto mem_free;
++ }
++
++ info->irq = irq_of_parse_and_map(node, 0);
++
++ if (WARN_ON(!info->irq)) {
++ ret = -ENXIO;
++ goto unmap;
++ }
++
++ readl_relaxed(info->baseaddr + PWC_STATUS);
++
++ ret = request_irq(info->irq, vexpress_spc_irq_handler,
++ IRQF_DISABLED | IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
++ "arm-spc", info);
++
++ if (ret) {
++ pr_err("IRQ %d request failed\n", info->irq);
++ ret = -ENODEV;
++ goto unmap;
++ }
++
++ info->a15_clusid = readl_relaxed(info->baseaddr + A15_CONF) & 0xf;
++
++ vexpress_spc_config_bridge = vexpress_config_bridge_register(
++ node, &vexpress_spc_config_bridge_info);
++
++ if (WARN_ON(!vexpress_spc_config_bridge)) {
++ ret = -ENODEV;
++ goto unmap;
++ }
++
++ opp_func = vexpress_config_func_get(vexpress_spc_config_bridge, "opp");
++ perf_func =
++ vexpress_config_func_get(vexpress_spc_config_bridge, "perf");
++
++ if (!opp_func || !perf_func) {
++ ret = -ENODEV;
++ goto unmap;
++ }
++
++ if (vexpress_spc_populate_opps(0) || vexpress_spc_populate_opps(1)) {
++ if (info->irq)
++ free_irq(info->irq, info);
++ pr_err("failed to build OPP table\n");
++ ret = -ENODEV;
++ goto unmap;
++ }
++ /*
++ * Multi-cluster systems may need this data when non-coherent, during
++ * cluster power-up/power-down. Make sure it reaches main memory:
++ */
++ sync_cache_w(info);
++ sync_cache_w(&info);
++ pr_info("vexpress-spc loaded at %p\n", info->baseaddr);
++ return 0;
++
++unmap:
++ iounmap(info->baseaddr);
++
++mem_free:
++ kfree(info);
++ return ret;
++}
++
++static bool __init __vexpress_spc_check_loaded(void);
++/*
++ * Pointer spc_check_loaded is swapped after init hence it is safe
++ * to initialize it to a function in the __init section
++ */
++static bool (*spc_check_loaded)(void) __refdata = &__vexpress_spc_check_loaded;
++
++static bool __init __vexpress_spc_check_loaded(void)
++{
++ if (vexpress_spc_load_result == -EAGAIN)
++ vexpress_spc_load_result = vexpress_spc_init();
++ spc_check_loaded = &vexpress_spc_initialized;
++ return vexpress_spc_initialized();
++}
++
++/*
++ * Function exported to manage early_initcall ordering.
++ * SPC code is needed very early in the boot process
++ * to bring CPUs out of reset and initialize power
++ * management back-end. After boot swap pointers to
++ * make the functionality check available to loadable
++ * modules, when early boot init functions have been
++ * already freed from kernel address space.
++ */
++bool vexpress_spc_check_loaded(void)
++{
++ return spc_check_loaded();
++}
++EXPORT_SYMBOL_GPL(vexpress_spc_check_loaded);
++
++static int __init vexpress_spc_early_init(void)
++{
++ __vexpress_spc_check_loaded();
++ return vexpress_spc_load_result;
++}
++early_initcall(vexpress_spc_early_init);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Serial Power Controller (SPC) support");
+diff -Nur linux-3.10.30.orig/drivers/mfd/vexpress-sysreg.c linux-linaro-stable-mx6/drivers/mfd/vexpress-sysreg.c
+--- linux-3.10.30.orig/drivers/mfd/vexpress-sysreg.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mfd/vexpress-sysreg.c 2014-05-15 20:33:58.090014528 +0200
+@@ -165,7 +165,7 @@
+ static int vexpress_sysreg_config_tries;
+
+ static void *vexpress_sysreg_config_func_get(struct device *dev,
+- struct device_node *node)
++ struct device_node *node, const char *id)
+ {
+ struct vexpress_sysreg_config_func *config_func;
+ u32 site;
+@@ -351,6 +351,8 @@
+ }
+
+
++#ifdef CONFIG_GPIOLIB
++
+ #define VEXPRESS_SYSREG_GPIO(_name, _reg, _value) \
+ [VEXPRESS_GPIO_##_name] = { \
+ .reg = _reg, \
+@@ -445,6 +447,8 @@
+ .leds = vexpress_sysreg_leds,
+ };
+
++#endif
++
+
+ static ssize_t vexpress_sysreg_sys_id_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+@@ -480,6 +484,9 @@
+ setup_timer(&vexpress_sysreg_config_timer,
+ vexpress_sysreg_config_complete, 0);
+
++ vexpress_sysreg_dev = &pdev->dev;
++
++#ifdef CONFIG_GPIOLIB
+ vexpress_sysreg_gpio_chip.dev = &pdev->dev;
+ err = gpiochip_add(&vexpress_sysreg_gpio_chip);
+ if (err) {
+@@ -490,11 +497,10 @@
+ return err;
+ }
+
+- vexpress_sysreg_dev = &pdev->dev;
+-
+ platform_device_register_data(vexpress_sysreg_dev, "leds-gpio",
+ PLATFORM_DEVID_AUTO, &vexpress_sysreg_leds_pdata,
+ sizeof(vexpress_sysreg_leds_pdata));
++#endif
+
+ device_create_file(vexpress_sysreg_dev, &dev_attr_sys_id);
+
+diff -Nur linux-3.10.30.orig/drivers/misc/sram.c linux-linaro-stable-mx6/drivers/misc/sram.c
+--- linux-3.10.30.orig/drivers/misc/sram.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/misc/sram.c 2014-05-15 20:33:58.166015076 +0200
+@@ -29,7 +29,7 @@
+ #include <linux/spinlock.h>
+ #include <linux/genalloc.h>
+
+-#define SRAM_GRANULARITY 32
++#define SRAM_GRANULARITY 4096
+
+ struct sram_dev {
+ struct gen_pool *pool;
+diff -Nur linux-3.10.30.orig/drivers/mmc/card/block.c linux-linaro-stable-mx6/drivers/mmc/card/block.c
+--- linux-3.10.30.orig/drivers/mmc/card/block.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/card/block.c 2014-05-15 20:33:58.202015335 +0200
+@@ -58,6 +58,8 @@
+ #define INAND_CMD38_ARG_SECTRIM1 0x81
+ #define INAND_CMD38_ARG_SECTRIM2 0x88
+ #define MMC_BLK_TIMEOUT_MS (10 * 60 * 1000) /* 10 minute timeout */
++#define MMC_SANITIZE_REQ_TIMEOUT 240000
++#define MMC_EXTRACT_INDEX_FROM_ARG(x) ((x & 0x00FF0000) >> 16)
+
+ #define mmc_req_rel_wr(req) (((req->cmd_flags & REQ_FUA) || \
+ (req->cmd_flags & REQ_META)) && \
+@@ -408,6 +410,35 @@
+ return err;
+ }
+
++static int ioctl_do_sanitize(struct mmc_card *card)
++{
++ int err;
++
++ if (!(mmc_can_sanitize(card) &&
++ (card->host->caps2 & MMC_CAP2_SANITIZE))) {
++ pr_warn("%s: %s - SANITIZE is not supported\n",
++ mmc_hostname(card->host), __func__);
++ err = -EOPNOTSUPP;
++ goto out;
++ }
++
++ pr_debug("%s: %s - SANITIZE IN PROGRESS...\n",
++ mmc_hostname(card->host), __func__);
++
++ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
++ EXT_CSD_SANITIZE_START, 1,
++ MMC_SANITIZE_REQ_TIMEOUT);
++
++ if (err)
++ pr_err("%s: %s - EXT_CSD_SANITIZE_START failed. err=%d\n",
++ mmc_hostname(card->host), __func__, err);
++
++ pr_debug("%s: %s - SANITIZE COMPLETED\n", mmc_hostname(card->host),
++ __func__);
++out:
++ return err;
++}
++
+ static int mmc_blk_ioctl_cmd(struct block_device *bdev,
+ struct mmc_ioc_cmd __user *ic_ptr)
+ {
+@@ -510,6 +541,16 @@
+ goto cmd_rel_host;
+ }
+
++ if (MMC_EXTRACT_INDEX_FROM_ARG(cmd.arg) == EXT_CSD_SANITIZE_START) {
++ err = ioctl_do_sanitize(card);
++
++ if (err)
++ pr_err("%s: ioctl_do_sanitize() failed. err = %d",
++ __func__, err);
++
++ goto cmd_rel_host;
++ }
++
+ mmc_wait_for_req(card->host, &mrq);
+
+ if (cmd.error) {
+@@ -956,10 +997,10 @@
+ {
+ struct mmc_blk_data *md = mq->data;
+ struct mmc_card *card = md->queue.card;
+- unsigned int from, nr, arg, trim_arg, erase_arg;
++ unsigned int from, nr, arg;
+ int err = 0, type = MMC_BLK_SECDISCARD;
+
+- if (!(mmc_can_secure_erase_trim(card) || mmc_can_sanitize(card))) {
++ if (!(mmc_can_secure_erase_trim(card))) {
+ err = -EOPNOTSUPP;
+ goto out;
+ }
+@@ -967,23 +1008,11 @@
+ from = blk_rq_pos(req);
+ nr = blk_rq_sectors(req);
+
+- /* The sanitize operation is supported at v4.5 only */
+- if (mmc_can_sanitize(card)) {
+- erase_arg = MMC_ERASE_ARG;
+- trim_arg = MMC_TRIM_ARG;
+- } else {
+- erase_arg = MMC_SECURE_ERASE_ARG;
+- trim_arg = MMC_SECURE_TRIM1_ARG;
+- }
++ if (mmc_can_trim(card) && !mmc_erase_group_aligned(card, from, nr))
++ arg = MMC_SECURE_TRIM1_ARG;
++ else
++ arg = MMC_SECURE_ERASE_ARG;
+
+- if (mmc_erase_group_aligned(card, from, nr))
+- arg = erase_arg;
+- else if (mmc_can_trim(card))
+- arg = trim_arg;
+- else {
+- err = -EINVAL;
+- goto out;
+- }
+ retry:
+ if (card->quirks & MMC_QUIRK_INAND_CMD38) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+@@ -1019,9 +1048,6 @@
+ goto out;
+ }
+
+- if (mmc_can_sanitize(card))
+- err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+- EXT_CSD_SANITIZE_START, 1, 0);
+ out_retry:
+ if (err && !mmc_blk_reset(md, card->host, type))
+ goto retry;
+diff -Nur linux-3.10.30.orig/drivers/mmc/card/queue.c linux-linaro-stable-mx6/drivers/mmc/card/queue.c
+--- linux-3.10.30.orig/drivers/mmc/card/queue.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/card/queue.c 2014-05-15 20:33:58.202015335 +0200
+@@ -173,7 +173,7 @@
+ /* granularity must not be greater than max. discard */
+ if (card->pref_erase > max_discard)
+ q->limits.discard_granularity = 0;
+- if (mmc_can_secure_erase_trim(card) || mmc_can_sanitize(card))
++ if (mmc_can_secure_erase_trim(card))
+ queue_flag_set_unlocked(QUEUE_FLAG_SECDISCARD, q);
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/mmc/core/core.c linux-linaro-stable-mx6/drivers/mmc/core/core.c
+--- linux-3.10.30.orig/drivers/mmc/core/core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/core/core.c 2014-05-15 20:33:58.218015451 +0200
+@@ -13,11 +13,13 @@
+ #include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
++#include <linux/clk.h>
+ #include <linux/completion.h>
+ #include <linux/device.h>
+ #include <linux/delay.h>
+ #include <linux/pagemap.h>
+ #include <linux/err.h>
++#include <linux/gpio.h>
+ #include <linux/leds.h>
+ #include <linux/scatterlist.h>
+ #include <linux/log2.h>
+@@ -402,6 +404,7 @@
+ context_info->is_done_rcv = false;
+ context_info->is_new_req = false;
+ cmd = mrq->cmd;
++
+ if (!cmd->error || !cmd->retries ||
+ mmc_card_removed(host->card)) {
+ err = host->areq->err_check(host->card,
+@@ -436,6 +439,24 @@
+ wait_for_completion(&mrq->completion);
+
+ cmd = mrq->cmd;
++
++ /*
++ * If host has timed out waiting for the sanitize
++ * to complete, card might be still in programming state
++ * so let's try to bring the card out of programming
++ * state.
++ */
++ if (cmd->sanitize_busy && cmd->error == -ETIMEDOUT) {
++ if (!mmc_interrupt_hpi(host->card)) {
++ pr_warning("%s: %s: Interrupted sanitize\n",
++ mmc_hostname(host), __func__);
++ cmd->error = 0;
++ break;
++ } else {
++ pr_err("%s: %s: Failed to interrupt sanitize\n",
++ mmc_hostname(host), __func__);
++ }
++ }
+ if (!cmd->error || !cmd->retries ||
+ mmc_card_removed(host->card))
+ break;
+@@ -1448,6 +1469,43 @@
+ mmc_host_clk_release(host);
+ }
+
++static void mmc_card_power_up(struct mmc_host *host)
++{
++ int i;
++ struct gpio_desc **gds = host->card_reset_gpios;
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ if (gds[i]) {
++ dev_dbg(host->parent, "Asserting reset line %d", i);
++ gpiod_set_value(gds[i], 1);
++ }
++ }
++
++ if (host->card_regulator) {
++ dev_dbg(host->parent, "Enabling external regulator");
++ if (regulator_enable(host->card_regulator))
++ dev_err(host->parent, "Failed to enable external regulator");
++ }
++
++ if (host->card_clk) {
++ dev_dbg(host->parent, "Enabling external clock");
++ clk_prepare_enable(host->card_clk);
++ }
++
++ /* 2ms delay to let clocks and power settle */
++ mmc_delay(20);
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ if (gds[i]) {
++ dev_dbg(host->parent, "Deasserting reset line %d", i);
++ gpiod_set_value(gds[i], 0);
++ }
++ }
++
++ /* 2ms delay to after reset release */
++ mmc_delay(20);
++}
++
+ /*
+ * Apply power to the MMC stack. This is a two-stage process.
+ * First, we enable power to the card without the clock running.
+@@ -1466,6 +1524,9 @@
+ if (host->ios.power_mode == MMC_POWER_ON)
+ return;
+
++ /* Power up the card/module first, if needed */
++ mmc_card_power_up(host);
++
+ mmc_host_clk_hold(host);
+
+ /* If ocr is set, we use it */
+diff -Nur linux-3.10.30.orig/drivers/mmc/core/host.c linux-linaro-stable-mx6/drivers/mmc/core/host.c
+--- linux-3.10.30.orig/drivers/mmc/core/host.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/core/host.c 2014-05-15 20:33:58.218015451 +0200
+@@ -12,14 +12,18 @@
+ * MMC host class device management
+ */
+
++#include <linux/kernel.h>
++#include <linux/clk.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/idr.h>
+ #include <linux/of.h>
+ #include <linux/of_gpio.h>
+ #include <linux/pagemap.h>
+ #include <linux/export.h>
+ #include <linux/leds.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+ #include <linux/suspend.h>
+
+@@ -306,7 +310,7 @@
+ * parse the properties and set respective generic mmc-host flags and
+ * parameters.
+ */
+-void mmc_of_parse(struct mmc_host *host)
++int mmc_of_parse(struct mmc_host *host)
+ {
+ struct device_node *np;
+ u32 bus_width;
+@@ -315,7 +319,7 @@
+ int len, ret, gpio;
+
+ if (!host->parent || !host->parent->of_node)
+- return;
++ return 0;
+
+ np = host->parent->of_node;
+
+@@ -338,6 +342,7 @@
+ default:
+ dev_err(host->parent,
+ "Invalid \"bus-width\" value %ud!\n", bus_width);
++ return -EINVAL;
+ }
+
+ /* f_max is obtained from the optional "max-frequency" property */
+@@ -367,18 +372,22 @@
+ host->caps |= MMC_CAP_NEEDS_POLL;
+
+ gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags);
++ if (gpio == -EPROBE_DEFER)
++ return gpio;
+ if (gpio_is_valid(gpio)) {
+ if (!(flags & OF_GPIO_ACTIVE_LOW))
+ gpio_inv_cd = true;
+
+- ret = mmc_gpio_request_cd(host, gpio);
+- if (ret < 0)
++ ret = mmc_gpio_request_cd(host, gpio, 0);
++ if (ret < 0) {
+ dev_err(host->parent,
+ "Failed to request CD GPIO #%d: %d!\n",
+ gpio, ret);
+- else
++ return ret;
++ } else {
+ dev_info(host->parent, "Got CD GPIO #%d.\n",
+ gpio);
++ }
+ }
+
+ if (explicit_inv_cd ^ gpio_inv_cd)
+@@ -389,14 +398,23 @@
+ explicit_inv_wp = of_property_read_bool(np, "wp-inverted");
+
+ gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, &flags);
++ if (gpio == -EPROBE_DEFER) {
++ ret = -EPROBE_DEFER;
++ goto out;
++ }
+ if (gpio_is_valid(gpio)) {
+ if (!(flags & OF_GPIO_ACTIVE_LOW))
+ gpio_inv_wp = true;
+
+ ret = mmc_gpio_request_ro(host, gpio);
+- if (ret < 0)
++ if (ret < 0) {
+ dev_err(host->parent,
+ "Failed to request WP GPIO: %d!\n", ret);
++ goto out;
++ } else {
++ dev_info(host->parent, "Got WP GPIO #%d.\n",
++ gpio);
++ }
+ }
+ if (explicit_inv_wp ^ gpio_inv_wp)
+ host->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
+@@ -413,10 +431,76 @@
+ host->pm_caps |= MMC_PM_KEEP_POWER;
+ if (of_find_property(np, "enable-sdio-wakeup", &len))
+ host->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
++
++ return 0;
++
++out:
++ mmc_gpio_free_cd(host);
++ return ret;
+ }
+
+ EXPORT_SYMBOL(mmc_of_parse);
+
++static int mmc_of_parse_child(struct mmc_host *host)
++{
++ struct device_node *np;
++ struct clk *clk;
++ int i;
++
++ if (!host->parent || !host->parent->of_node)
++ return 0;
++
++ np = host->parent->of_node;
++
++ host->card_regulator = regulator_get(host->parent, "card-external-vcc");
++ if (IS_ERR(host->card_regulator)) {
++ if (PTR_ERR(host->card_regulator) == -EPROBE_DEFER)
++ return PTR_ERR(host->card_regulator);
++ host->card_regulator = NULL;
++ }
++
++ /* Parse card power/reset/clock control */
++ if (of_find_property(np, "card-reset-gpios", NULL)) {
++ struct gpio_desc *gpd;
++ int level = 0;
++
++ /*
++ * If the regulator is enabled, then we can hold the
++ * card in reset with an active high resets. Otherwise,
++ * hold the resets low.
++ */
++ if (host->card_regulator && regulator_is_enabled(host->card_regulator))
++ level = 1;
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ gpd = devm_gpiod_get_index(host->parent, "card-reset", i);
++ if (IS_ERR(gpd)) {
++ if (PTR_ERR(gpd) == -EPROBE_DEFER)
++ return PTR_ERR(gpd);
++ break;
++ }
++ gpiod_direction_output(gpd, gpiod_is_active_low(gpd) | level);
++ host->card_reset_gpios[i] = gpd;
++ }
++
++ gpd = devm_gpiod_get_index(host->parent, "card-reset", ARRAY_SIZE(host->card_reset_gpios));
++ if (!IS_ERR(gpd)) {
++ dev_warn(host->parent, "More reset gpios than we can handle");
++ gpiod_put(gpd);
++ }
++ }
++
++ clk = of_clk_get_by_name(np, "card_ext_clock");
++ if (IS_ERR(clk)) {
++ if (PTR_ERR(clk) == -EPROBE_DEFER)
++ return PTR_ERR(clk);
++ clk = NULL;
++ }
++ host->card_clk = clk;
++
++ return 0;
++}
++
+ /**
+ * mmc_alloc_host - initialise the per-host structure.
+ * @extra: sizeof private data structure
+@@ -496,6 +580,10 @@
+ {
+ int err;
+
++ err = mmc_of_parse_child(host);
++ if (err)
++ return err;
++
+ WARN_ON((host->caps & MMC_CAP_SDIO_IRQ) &&
+ !host->ops->enable_sdio_irq);
+
+diff -Nur linux-3.10.30.orig/drivers/mmc/core/mmc.c linux-linaro-stable-mx6/drivers/mmc/core/mmc.c
+--- linux-3.10.30.orig/drivers/mmc/core/mmc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/core/mmc.c 2014-05-15 20:33:58.218015451 +0200
+@@ -316,6 +316,11 @@
+ mmc_card_set_blockaddr(card);
+ }
+
++ card->ext_csd.boot_info = ext_csd[EXT_CSD_BOOT_INFO];
++ card->ext_csd.boot_config = ext_csd[EXT_CSD_PART_CONFIG];
++ card->ext_csd.boot_size = ext_csd[EXT_CSD_BOOT_MULT];
++ card->ext_csd.boot_bus_width = ext_csd[EXT_CSD_BOOT_BUS_WIDTH];
++
+ card->ext_csd.raw_card_type = ext_csd[EXT_CSD_CARD_TYPE];
+ mmc_select_card_type(card);
+
+@@ -616,6 +621,372 @@
+ return err;
+ }
+
++static ssize_t mmc_boot_info_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ char *boot_partition[8] = {
++ "Device not boot enabled",
++ "Boot partition 1 enabled",
++ "Boot partition 2 enabled",
++ "Reserved",
++ "Reserved",
++ "Reserved",
++ "Reserved",
++ "User area enabled for boot"};
++
++ char *bus_width[4] = {
++ "x1 (sdr) or x4 (ddr) bus width in boot operation mode",
++ "x4 (sdr/ddr) bus width in boot operation mode",
++ "x8 (sdr/ddr) bus width in boot operation mode",
++ "Reserved"};
++
++ char *boot_mode[4] = {
++ "Use single data rate + backward compatible timings in boot operation",
++ "Use single data rate + high speed timings in boot operation mode",
++ "Use dual data rate in boot operation",
++ "Reserved"};
++
++ int partition;
++ int width;
++ int mode;
++ int err;
++ u8 *ext_csd = NULL;
++ struct mmc_card *card = container_of(dev, struct mmc_card, dev);
++
++ /* read it again because user may change it */
++ mmc_claim_host(card->host);
++ err = mmc_get_ext_csd(card, &ext_csd);
++ mmc_release_host(card->host);
++ if (err || !ext_csd) {
++ pr_err("%s: failed to get ext_csd, err=%d\n",
++ mmc_hostname(card->host),
++ err);
++ return err;
++ }
++
++ mmc_read_ext_csd(card, ext_csd);
++ mmc_free_ext_csd(ext_csd);
++
++ partition = (card->ext_csd.boot_config >> 3) & 0x7;
++ width = card->ext_csd.boot_bus_width & 0x3;
++ mode = (card->ext_csd.boot_bus_width >> 3) & 0x3;
++
++ return sprintf(buf,
++ "boot_info:0x%02x;\n"
++ " ALT_BOOT_MODE:%x - %s\n"
++ " DDR_BOOT_MODE:%x - %s\n"
++ " HS_BOOTMODE:%x - %s\n"
++ "boot_size:%04dKB\n"
++ "boot_partition:0x%02x;\n"
++ " BOOT_ACK:%x - %s\n"
++ " BOOT_PARTITION-ENABLE: %x - %s\n"
++ "boot_bus:0x%02x\n"
++ " BOOT_MODE:%x - %s\n"
++ " RESET_BOOT_BUS_WIDTH:%x - %s\n"
++ " BOOT_BUS_WIDTH:%x - %s\n",
++
++ card->ext_csd.boot_info,
++ !!(card->ext_csd.boot_info & 0x1),
++ (card->ext_csd.boot_info & 0x1) ?
++ "Supports alternate boot method" :
++ "Does not support alternate boot method",
++ !!(card->ext_csd.boot_info & 0x2),
++ (card->ext_csd.boot_info & 0x2) ?
++ "Supports alternate dual data rate during boot" :
++ "Does not support dual data rate during boot",
++ !!(card->ext_csd.boot_info & 0x4),
++ (card->ext_csd.boot_info & 0x4) ?
++ "Supports high speed timing during boot" :
++ "Does not support high speed timing during boot",
++
++ card->ext_csd.boot_size * 128,
++
++ card->ext_csd.boot_config,
++ !!(card->ext_csd.boot_config & 0x40),
++ (card->ext_csd.boot_config & 0x40) ?
++ "Boot acknowledge sent during boot operation" :
++ "No boot acknowledge sent",
++ partition,
++ boot_partition[partition],
++
++ card->ext_csd.boot_bus_width,
++ mode,
++ boot_mode[mode],
++ !!(card->ext_csd.boot_bus_width & 0x4),
++ (card->ext_csd.boot_bus_width & 0x4) ?
++ "Retain boot bus width and boot mode after boot operation" :
++ "Reset bus width to x1, single data rate and backward"
++ "compatible timings after boot operation",
++ width,
++ bus_width[width]);
++}
++
++/* set up boot partitions */
++static ssize_t
++setup_boot_partitions(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ int err, busy = 0;
++ u32 part;
++ u8 *ext_csd, boot_config;
++ struct mmc_command cmd;
++ struct mmc_card *card = container_of(dev, struct mmc_card, dev);
++
++ BUG_ON(!card);
++
++ sscanf(buf, "%d\n", &part);
++
++ if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
++ pr_err("%s: invalid mmc version" \
++ " mmc version is below version 4!)\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ /* it's a normal SD/MMC but user request to configure boot partition */
++ if (card->ext_csd.boot_size <= 0) {
++ pr_err("%s: fail to send SWITCH command to card " \
++ "to update boot_config of the EXT_CSD!\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ /*
++ * partition must be -
++ * 0 - user area
++ * 1 - boot partition 1
++ * 2 - boot partition 2
++ * DO NOT switch the partitions that used to be accessed
++ * in OS layer HERE
++ */
++ if (part & EXT_CSD_BOOT_PARTITION_ACCESS_MASK) {
++ pr_err("%s: DO NOT switch the partitions that used to be\n" \
++ " accessed in OS layer HERE. please following the\n" \
++ " guidance of Documentation/mmc/mmc-dev-parts.txt.\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ ext_csd = kmalloc(512, GFP_KERNEL);
++ if (!ext_csd) {
++ pr_err("%s: could not allocate a buffer to " \
++ "receive the ext_csd.\n", mmc_hostname(card->host));
++ return -ENOMEM;
++ }
++
++ mmc_claim_host(card->host);
++ err = mmc_send_ext_csd(card, ext_csd);
++ if (err) {
++ pr_err("%s: unable to read EXT_CSD.\n",
++ mmc_hostname(card->host));
++ goto err_rtn;
++ }
++
++ /* enable the boot partition in boot mode */
++ /* boot enable be -
++ * 0x00 - disable boot enable.
++ * 0x08 - boot partition 1 is enabled for boot.
++ * 0x10 - boot partition 2 is enabled for boot.
++ * 0x38 - User area is enabled for boot.
++ */
++ switch (part & EXT_CSD_BOOT_PARTITION_ENABLE_MASK) {
++ case 0:
++ boot_config = (ext_csd[EXT_CSD_PART_CONFIG]
++ & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK
++ & ~EXT_CSD_BOOT_ACK_ENABLE);
++ break;
++ case EXT_CSD_BOOT_PARTITION_PART1:
++ boot_config = ((ext_csd[EXT_CSD_PART_CONFIG]
++ & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK)
++ | EXT_CSD_BOOT_PARTITION_PART1
++ | EXT_CSD_BOOT_ACK_ENABLE);
++ break;
++ case EXT_CSD_BOOT_PARTITION_PART2:
++ boot_config = ((ext_csd[EXT_CSD_PART_CONFIG]
++ & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK)
++ | EXT_CSD_BOOT_PARTITION_PART2
++ | EXT_CSD_BOOT_ACK_ENABLE);
++ break;
++ case EXT_CSD_BOOT_PARTITION_ENABLE_MASK:
++ boot_config = ((ext_csd[EXT_CSD_PART_CONFIG]
++ | EXT_CSD_BOOT_PARTITION_ENABLE_MASK)
++ & ~EXT_CSD_BOOT_ACK_ENABLE);
++ break;
++ default:
++ pr_err("%s: wrong boot config parameter" \
++ " 00 (disable boot), 08 (enable boot1)," \
++ "16 (enable boot2), 56 (User area)\n",
++ mmc_hostname(card->host));
++ err = -EINVAL;
++ goto err_rtn;
++ }
++
++ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
++ EXT_CSD_PART_CONFIG, boot_config, card->ext_csd.part_time);
++ if (err) {
++ pr_err("%s: fail to send SWITCH command to card " \
++ "to update boot_config of the EXT_CSD!\n",
++ mmc_hostname(card->host));
++ goto err_rtn;
++ }
++
++ /* waiting for the card to finish the busy state */
++ do {
++ memset(&cmd, 0, sizeof(struct mmc_command));
++
++ cmd.opcode = MMC_SEND_STATUS;
++ cmd.arg = card->rca << 16;
++ cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
++
++ err = mmc_wait_for_cmd(card->host, &cmd, 0);
++ if (err || busy > 100) {
++ pr_err("%s: failed to wait for" \
++ "the busy state to end.\n",
++ mmc_hostname(card->host));
++ break;
++ }
++
++ if (!busy && !(cmd.resp[0] & R1_READY_FOR_DATA)) {
++ pr_info("%s: card is in busy state" \
++ "pls wait for busy state to end.\n",
++ mmc_hostname(card->host));
++ }
++ busy++;
++ } while (!(cmd.resp[0] & R1_READY_FOR_DATA));
++
++ /* Now check whether it works */
++ err = mmc_send_ext_csd(card, ext_csd);
++ if (err) {
++ pr_err("%s: %d unable to re-read EXT_CSD.\n",
++ mmc_hostname(card->host), err);
++ goto err_rtn;
++ }
++
++ card->ext_csd.boot_config = ext_csd[EXT_CSD_PART_CONFIG];
++
++err_rtn:
++ mmc_release_host(card->host);
++ kfree(ext_csd);
++ if (err)
++ return err;
++ else
++ return count;
++}
++
++/* configure the boot bus */
++static ssize_t
++setup_boot_bus(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ int err, busy = 0;
++ u32 boot_bus, new_bus;
++ u8 *ext_csd;
++ struct mmc_command cmd;
++ struct mmc_card *card = container_of(dev, struct mmc_card, dev);
++
++ BUG_ON(!card);
++
++ sscanf(buf, "%d\n", &boot_bus);
++
++ if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
++ pr_err("%s: invalid mmc version" \
++ " mmc version is below version 4!)\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ /* it's a normal SD/MMC but user request to configure boot bus */
++ if (card->ext_csd.boot_size <= 0) {
++ pr_err("%s: this is a normal SD/MMC card" \
++ " but you request to configure boot bus !\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ ext_csd = kmalloc(512, GFP_KERNEL);
++ if (!ext_csd) {
++ pr_err("%s: could not allocate a buffer to " \
++ "receive the ext_csd.\n", mmc_hostname(card->host));
++ return -ENOMEM;
++ }
++
++ mmc_claim_host(card->host);
++ err = mmc_send_ext_csd(card, ext_csd);
++ if (err) {
++ pr_err("%s: unable to read EXT_CSD.\n",
++ mmc_hostname(card->host));
++ goto err_rtn;
++ }
++
++ /* Configure the boot bus width when boot partition is enabled */
++ if (((boot_bus & EXT_CSD_BOOT_BUS_WIDTH_MODE_MASK) >> 3) > 2
++ || (boot_bus & EXT_CSD_BOOT_BUS_WIDTH_WIDTH_MASK) > 2
++ || (boot_bus & ~EXT_CSD_BOOT_BUS_WIDTH_MASK) > 0) {
++ pr_err("%s: Invalid inputs!\n",
++ mmc_hostname(card->host));
++ err = -EINVAL;
++ goto err_rtn;
++ }
++
++ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
++ EXT_CSD_BOOT_BUS_WIDTH, boot_bus, card->ext_csd.part_time);
++ if (err) {
++ pr_err("%s: fail to send SWITCH command to card " \
++ "to update boot_config of the EXT_CSD!\n",
++ mmc_hostname(card->host));
++ goto err_rtn;
++ }
++
++ /* waiting for the card to finish the busy state */
++ do {
++ memset(&cmd, 0, sizeof(struct mmc_command));
++
++ cmd.opcode = MMC_SEND_STATUS;
++ cmd.arg = card->rca << 16;
++ cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
++
++ err = mmc_wait_for_cmd(card->host, &cmd, 0);
++ if (err || busy > 100) {
++ pr_err("%s: failed to wait for" \
++ "the busy state to end.\n",
++ mmc_hostname(card->host));
++ break;
++ }
++
++ if (!busy && !(cmd.resp[0] & R1_READY_FOR_DATA)) {
++ pr_info("%s: card is in busy state" \
++ "pls wait for busy state to end.\n",
++ mmc_hostname(card->host));
++ }
++ busy++;
++ } while (!(cmd.resp[0] & R1_READY_FOR_DATA));
++
++ /* Now check whether it works */
++ err = mmc_send_ext_csd(card, ext_csd);
++ if (err) {
++ pr_err("%s: %d unable to re-read EXT_CSD.\n",
++ mmc_hostname(card->host), err);
++ goto err_rtn;
++ }
++
++ new_bus = ext_csd[EXT_CSD_BOOT_BUS_WIDTH];
++ if (boot_bus != new_bus) {
++ pr_err("%s: after SWITCH, current boot bus mode %d" \
++ " is not same as requested bus mode %d!\n",
++ mmc_hostname(card->host), new_bus, boot_bus);
++ goto err_rtn;
++ }
++ card->ext_csd.boot_bus_width = ext_csd[EXT_CSD_BOOT_BUS_WIDTH];
++
++err_rtn:
++ mmc_release_host(card->host);
++ mmc_free_ext_csd(ext_csd);
++ if (err)
++ return err;
++ else
++ return count;
++}
++
+ MMC_DEV_ATTR(cid, "%08x%08x%08x%08x\n", card->raw_cid[0], card->raw_cid[1],
+ card->raw_cid[2], card->raw_cid[3]);
+ MMC_DEV_ATTR(csd, "%08x%08x%08x%08x\n", card->raw_csd[0], card->raw_csd[1],
+@@ -635,6 +1006,9 @@
+ MMC_DEV_ATTR(enhanced_area_size, "%u\n", card->ext_csd.enhanced_area_size);
+ MMC_DEV_ATTR(raw_rpmb_size_mult, "%#x\n", card->ext_csd.raw_rpmb_size_mult);
+ MMC_DEV_ATTR(rel_sectors, "%#x\n", card->ext_csd.rel_sectors);
++DEVICE_ATTR(boot_info, S_IRUGO, mmc_boot_info_show, NULL);
++DEVICE_ATTR(boot_config, S_IWUGO, NULL, setup_boot_partitions);
++DEVICE_ATTR(boot_bus_config, S_IWUGO, NULL, setup_boot_bus);
+
+ static struct attribute *mmc_std_attrs[] = {
+ &dev_attr_cid.attr,
+@@ -653,6 +1027,9 @@
+ &dev_attr_enhanced_area_size.attr,
+ &dev_attr_raw_rpmb_size_mult.attr,
+ &dev_attr_rel_sectors.attr,
++ &dev_attr_boot_info.attr,
++ &dev_attr_boot_config.attr,
++ &dev_attr_boot_bus_config.attr,
+ NULL,
+ };
+
+@@ -1087,14 +1464,10 @@
+ */
+ if (mmc_card_highspeed(card)) {
+ if ((card->ext_csd.card_type & EXT_CSD_CARD_TYPE_DDR_1_8V)
+- && ((host->caps & (MMC_CAP_1_8V_DDR |
+- MMC_CAP_UHS_DDR50))
+- == (MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50)))
++ && (host->caps & MMC_CAP_1_8V_DDR))
+ ddr = MMC_1_8V_DDR_MODE;
+ else if ((card->ext_csd.card_type & EXT_CSD_CARD_TYPE_DDR_1_2V)
+- && ((host->caps & (MMC_CAP_1_2V_DDR |
+- MMC_CAP_UHS_DDR50))
+- == (MMC_CAP_1_2V_DDR | MMC_CAP_UHS_DDR50)))
++ && (host->caps & MMC_CAP_1_2V_DDR))
+ ddr = MMC_1_2V_DDR_MODE;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/mmc/core/mmc_ops.c linux-linaro-stable-mx6/drivers/mmc/core/mmc_ops.c
+--- linux-3.10.30.orig/drivers/mmc/core/mmc_ops.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/core/mmc_ops.c 2014-05-15 20:33:58.218015451 +0200
+@@ -431,6 +431,8 @@
+
+
+ cmd.cmd_timeout_ms = timeout_ms;
++ if (index == EXT_CSD_SANITIZE_START)
++ cmd.sanitize_busy = true;
+
+ err = mmc_wait_for_cmd(card->host, &cmd, MMC_CMD_RETRIES);
+ if (err)
+@@ -440,6 +442,12 @@
+ if (!use_busy_signal)
+ return 0;
+
++ /*
++ * WORKAROUND: for Sandisk eMMC cards, it might need certain delay
++ * before sending CMD13 after CMD6
++ */
++ mdelay(1);
++
+ /* Must check status to be sure of no errors */
+ timeout = jiffies + msecs_to_jiffies(MMC_OPS_TIMEOUT_MS);
+ do {
+diff -Nur linux-3.10.30.orig/drivers/mmc/core/sd.c linux-linaro-stable-mx6/drivers/mmc/core/sd.c
+--- linux-3.10.30.orig/drivers/mmc/core/sd.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/core/sd.c 2014-05-15 20:33:58.218015451 +0200
+@@ -215,7 +215,7 @@
+ static int mmc_read_ssr(struct mmc_card *card)
+ {
+ unsigned int au, es, et, eo;
+- int err, i;
++ int err, i, max_au;
+ u32 *ssr;
+
+ if (!(card->csd.cmdclass & CCC_APP_SPEC)) {
+@@ -239,12 +239,15 @@
+ for (i = 0; i < 16; i++)
+ ssr[i] = be32_to_cpu(ssr[i]);
+
++ /* SD3.0 increases max AU size to 64MB (0xF) from 4MB (0x9) */
++ max_au = card->scr.sda_spec3 ? 0xF : 0x9;
++
+ /*
+ * UNSTUFF_BITS only works with four u32s so we have to offset the
+ * bitfield positions accordingly.
+ */
+ au = UNSTUFF_BITS(ssr, 428 - 384, 4);
+- if (au > 0 && au <= 9) {
++ if (au > 0 && au <= max_au) {
+ card->ssr.au = 1 << (au + 4);
+ es = UNSTUFF_BITS(ssr, 408 - 384, 16);
+ et = UNSTUFF_BITS(ssr, 402 - 384, 6);
+@@ -646,8 +649,13 @@
+ if (err)
+ goto out;
+
+- /* SPI mode doesn't define CMD19 */
+- if (!mmc_host_is_spi(card->host) && card->host->ops->execute_tuning) {
++ /*
++ * SPI mode doesn't define CMD19 and tuning is only valid for SDR50 and
++ * SDR104 mode SD-cards. Note that tuning is mandatory for SDR104.
++ */
++ if (!mmc_host_is_spi(card->host) && card->host->ops->execute_tuning &&
++ (card->sd_bus_speed == UHS_SDR50_BUS_SPEED ||
++ card->sd_bus_speed == UHS_SDR104_BUS_SPEED)) {
+ mmc_host_clk_hold(card->host);
+ err = card->host->ops->execute_tuning(card->host,
+ MMC_SEND_TUNING_BLOCK);
+diff -Nur linux-3.10.30.orig/drivers/mmc/core/sdio.c linux-linaro-stable-mx6/drivers/mmc/core/sdio.c
+--- linux-3.10.30.orig/drivers/mmc/core/sdio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/core/sdio.c 2014-05-15 20:33:58.218015451 +0200
+@@ -563,10 +563,18 @@
+ if (err)
+ goto out;
+
+- /* Initialize and start re-tuning timer */
+- if (!mmc_host_is_spi(card->host) && card->host->ops->execute_tuning)
++ /*
++ * SPI mode doesn't define CMD19 and tuning is only valid for SDR50 and
++ * SDR104 mode SD-cards. Note that tuning is mandatory for SDR104.
++ */
++ if (!mmc_host_is_spi(card->host) && card->host->ops->execute_tuning &&
++ ((card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR50) ||
++ (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104))) {
++ mmc_host_clk_hold(card->host);
+ err = card->host->ops->execute_tuning(card->host,
+ MMC_SEND_TUNING_BLOCK);
++ mmc_host_clk_release(card->host);
++ }
+
+ out:
+
+diff -Nur linux-3.10.30.orig/drivers/mmc/core/sdio_irq.c linux-linaro-stable-mx6/drivers/mmc/core/sdio_irq.c
+--- linux-3.10.30.orig/drivers/mmc/core/sdio_irq.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/core/sdio_irq.c 2014-05-15 20:33:58.218015451 +0200
+@@ -79,6 +79,15 @@
+ return ret;
+ }
+
++void sdio_run_irqs(struct mmc_host *host)
++{
++ mmc_claim_host(host);
++ host->sdio_irq_pending = true;
++ process_sdio_pending_irqs(host);
++ mmc_release_host(host);
++}
++EXPORT_SYMBOL_GPL(sdio_run_irqs);
++
+ static int sdio_irq_thread(void *_host)
+ {
+ struct mmc_host *host = _host;
+@@ -178,14 +187,20 @@
+ WARN_ON(!host->claimed);
+
+ if (!host->sdio_irqs++) {
+- atomic_set(&host->sdio_irq_thread_abort, 0);
+- host->sdio_irq_thread =
+- kthread_run(sdio_irq_thread, host, "ksdioirqd/%s",
+- mmc_hostname(host));
+- if (IS_ERR(host->sdio_irq_thread)) {
+- int err = PTR_ERR(host->sdio_irq_thread);
+- host->sdio_irqs--;
+- return err;
++ if (!(host->caps2 & MMC_CAP2_SDIO_NOTHREAD)) {
++ atomic_set(&host->sdio_irq_thread_abort, 0);
++ host->sdio_irq_thread =
++ kthread_run(sdio_irq_thread, host,
++ "ksdioirqd/%s", mmc_hostname(host));
++ if (IS_ERR(host->sdio_irq_thread)) {
++ int err = PTR_ERR(host->sdio_irq_thread);
++ host->sdio_irqs--;
++ return err;
++ }
++ } else {
++ mmc_host_clk_hold(host);
++ host->ops->enable_sdio_irq(host, 1);
++ mmc_host_clk_release(host);
+ }
+ }
+
+@@ -200,8 +215,14 @@
+ BUG_ON(host->sdio_irqs < 1);
+
+ if (!--host->sdio_irqs) {
+- atomic_set(&host->sdio_irq_thread_abort, 1);
+- kthread_stop(host->sdio_irq_thread);
++ if (!(host->caps2 & MMC_CAP2_SDIO_NOTHREAD)) {
++ atomic_set(&host->sdio_irq_thread_abort, 1);
++ kthread_stop(host->sdio_irq_thread);
++ } else {
++ mmc_host_clk_hold(host);
++ host->ops->enable_sdio_irq(host, 0);
++ mmc_host_clk_release(host);
++ }
+ }
+
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/mmc/core/slot-gpio.c linux-linaro-stable-mx6/drivers/mmc/core/slot-gpio.c
+--- linux-3.10.30.orig/drivers/mmc/core/slot-gpio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/core/slot-gpio.c 2014-05-15 20:33:58.218015451 +0200
+@@ -135,6 +135,7 @@
+ * mmc_gpio_request_cd - request a gpio for card-detection
+ * @host: mmc host
+ * @gpio: gpio number requested
++ * @debounce: debounce time in microseconds
+ *
+ * As devm_* managed functions are used in mmc_gpio_request_cd(), client
+ * drivers do not need to explicitly call mmc_gpio_free_cd() for freeing up,
+@@ -143,9 +144,14 @@
+ * switching for card-detection, they are responsible for calling
+ * mmc_gpio_request_cd() and mmc_gpio_free_cd() as a pair on their own.
+ *
++ * If GPIO debouncing is desired, set the debounce parameter to a non-zero
++ * value. The caller is responsible for ensuring that the GPIO driver associated
++ * with the GPIO supports debouncing, otherwise an error will be returned.
++ *
+ * Returns zero on success, else an error.
+ */
+-int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio)
++int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio,
++ unsigned int debounce)
+ {
+ struct mmc_gpio *ctx;
+ int irq = gpio_to_irq(gpio);
+@@ -167,6 +173,12 @@
+ */
+ return ret;
+
++ if (debounce) {
++ ret = gpio_set_debounce(gpio, debounce);
++ if (ret < 0)
++ return ret;
++ }
++
+ /*
+ * Even if gpio_to_irq() returns a valid IRQ number, the platform might
+ * still prefer to poll, e.g., because that IRQ number is already used
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/dw_mmc.c linux-linaro-stable-mx6/drivers/mmc/host/dw_mmc.c
+--- linux-3.10.30.orig/drivers/mmc/host/dw_mmc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/dw_mmc.c 2014-05-15 20:33:58.222015480 +0200
+@@ -1902,6 +1902,8 @@
+ if (!mmc)
+ return -ENOMEM;
+
++ mmc_of_parse(mmc);
++
+ slot = mmc_priv(mmc);
+ slot->id = id;
+ slot->mmc = mmc;
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/jz4740_mmc.c linux-linaro-stable-mx6/drivers/mmc/host/jz4740_mmc.c
+--- linux-3.10.30.orig/drivers/mmc/host/jz4740_mmc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/jz4740_mmc.c 2014-05-15 20:33:58.222015480 +0200
+@@ -14,6 +14,7 @@
+ */
+
+ #include <linux/mmc/host.h>
++#include <linux/mmc/slot-gpio.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+@@ -650,35 +651,6 @@
+ }
+ }
+
+-static int jz4740_mmc_get_ro(struct mmc_host *mmc)
+-{
+- struct jz4740_mmc_host *host = mmc_priv(mmc);
+- if (!gpio_is_valid(host->pdata->gpio_read_only))
+- return -ENOSYS;
+-
+- return gpio_get_value(host->pdata->gpio_read_only) ^
+- host->pdata->read_only_active_low;
+-}
+-
+-static int jz4740_mmc_get_cd(struct mmc_host *mmc)
+-{
+- struct jz4740_mmc_host *host = mmc_priv(mmc);
+- if (!gpio_is_valid(host->pdata->gpio_card_detect))
+- return -ENOSYS;
+-
+- return gpio_get_value(host->pdata->gpio_card_detect) ^
+- host->pdata->card_detect_active_low;
+-}
+-
+-static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid)
+-{
+- struct jz4740_mmc_host *host = devid;
+-
+- mmc_detect_change(host->mmc, HZ / 2);
+-
+- return IRQ_HANDLED;
+-}
+-
+ static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+ {
+ struct jz4740_mmc_host *host = mmc_priv(mmc);
+@@ -688,8 +660,8 @@
+ static const struct mmc_host_ops jz4740_mmc_ops = {
+ .request = jz4740_mmc_request,
+ .set_ios = jz4740_mmc_set_ios,
+- .get_ro = jz4740_mmc_get_ro,
+- .get_cd = jz4740_mmc_get_cd,
++ .get_ro = mmc_gpio_get_ro,
++ .get_cd = mmc_gpio_get_cd,
+ .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
+ };
+
+@@ -724,58 +696,34 @@
+ return 0;
+ }
+
+-static int jz4740_mmc_request_gpios(struct platform_device *pdev)
++static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
++ struct platform_device *pdev)
+ {
+- int ret;
+ struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
++ int ret = 0;
+
+ if (!pdata)
+ return 0;
+
+- ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect,
+- "MMC detect change", false, 0);
+- if (ret)
+- goto err;
+-
+- ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only,
+- "MMC read only", false, 0);
+- if (ret)
+- goto err_free_gpio_card_detect;
++ if (!pdata->card_detect_active_low)
++ mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
++ if (!pdata->read_only_active_low)
++ mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
+
+- ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
+- "MMC read only", true, pdata->power_active_low);
+- if (ret)
+- goto err_free_gpio_read_only;
+-
+- return 0;
+-
+-err_free_gpio_read_only:
+- if (gpio_is_valid(pdata->gpio_read_only))
+- gpio_free(pdata->gpio_read_only);
+-err_free_gpio_card_detect:
+- if (gpio_is_valid(pdata->gpio_card_detect))
+- gpio_free(pdata->gpio_card_detect);
+-err:
+- return ret;
+-}
+-
+-static int jz4740_mmc_request_cd_irq(struct platform_device *pdev,
+- struct jz4740_mmc_host *host)
+-{
+- struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data;
+-
+- if (!gpio_is_valid(pdata->gpio_card_detect))
+- return 0;
++ if (gpio_is_valid(pdata->gpio_card_detect)) {
++ ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0);
++ if (ret)
++ return ret;
++ }
+
+- host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect);
+- if (host->card_detect_irq < 0) {
+- dev_warn(&pdev->dev, "Failed to get card detect irq\n");
+- return 0;
++ if (gpio_is_valid(pdata->gpio_read_only)) {
++ ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only);
++ if (ret)
++ return ret;
+ }
+
+- return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq,
+- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+- "MMC card detect", host);
++ return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
++ "MMC read only", true, pdata->power_active_low);
+ }
+
+ static void jz4740_mmc_free_gpios(struct platform_device *pdev)
+@@ -787,10 +735,6 @@
+
+ if (gpio_is_valid(pdata->gpio_power))
+ gpio_free(pdata->gpio_power);
+- if (gpio_is_valid(pdata->gpio_read_only))
+- gpio_free(pdata->gpio_read_only);
+- if (gpio_is_valid(pdata->gpio_card_detect))
+- gpio_free(pdata->gpio_card_detect);
+ }
+
+ static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host)
+@@ -862,7 +806,7 @@
+ goto err_iounmap;
+ }
+
+- ret = jz4740_mmc_request_gpios(pdev);
++ ret = jz4740_mmc_request_gpios(mmc, pdev);
+ if (ret)
+ goto err_gpio_bulk_free;
+
+@@ -885,17 +829,11 @@
+ spin_lock_init(&host->lock);
+ host->irq_mask = 0xffff;
+
+- ret = jz4740_mmc_request_cd_irq(pdev, host);
+- if (ret) {
+- dev_err(&pdev->dev, "Failed to request card detect irq\n");
+- goto err_free_gpios;
+- }
+-
+ ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
+ dev_name(&pdev->dev), host);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
+- goto err_free_card_detect_irq;
++ goto err_free_gpios;
+ }
+
+ jz4740_mmc_reset(host);
+@@ -918,9 +856,6 @@
+
+ err_free_irq:
+ free_irq(host->irq, host);
+-err_free_card_detect_irq:
+- if (host->card_detect_irq >= 0)
+- free_irq(host->card_detect_irq, host);
+ err_free_gpios:
+ jz4740_mmc_free_gpios(pdev);
+ err_gpio_bulk_free:
+@@ -949,8 +884,6 @@
+ mmc_remove_host(host->mmc);
+
+ free_irq(host->irq, host);
+- if (host->card_detect_irq >= 0)
+- free_irq(host->card_detect_irq, host);
+
+ jz4740_mmc_free_gpios(pdev);
+ jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host));
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/mvsdio.c linux-linaro-stable-mx6/drivers/mmc/host/mvsdio.c
+--- linux-3.10.30.orig/drivers/mmc/host/mvsdio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/mvsdio.c 2014-05-15 20:33:58.238015595 +0200
+@@ -35,7 +35,7 @@
+
+ #define DRIVER_NAME "mvsdio"
+
+-static int maxfreq = MVSD_CLOCKRATE_MAX;
++static int maxfreq;
+ static int nodma;
+
+ struct mvsd_host {
+@@ -685,7 +685,6 @@
+ const struct mbus_dram_target_info *dram;
+ struct resource *r;
+ int ret, irq;
+- int gpio_card_detect, gpio_write_protect;
+ struct pinctrl *pinctrl;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -718,6 +717,20 @@
+ if (!IS_ERR(host->clk))
+ clk_prepare_enable(host->clk);
+
++ mmc->ops = &mvsd_ops;
++
++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
++
++ mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
++ mmc->f_max = MVSD_CLOCKRATE_MAX;
++
++ mmc->max_blk_size = 2048;
++ mmc->max_blk_count = 65535;
++
++ mmc->max_segs = 1;
++ mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
++ mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
++
+ if (np) {
+ if (IS_ERR(host->clk)) {
+ dev_err(&pdev->dev, "DT platforms must have a clock associated\n");
+@@ -726,35 +739,39 @@
+ }
+
+ host->base_clock = clk_get_rate(host->clk) / 2;
+- gpio_card_detect = of_get_named_gpio(np, "cd-gpios", 0);
+- gpio_write_protect = of_get_named_gpio(np, "wp-gpios", 0);
++ ret = mmc_of_parse(mmc);
++ if (ret < 0)
++ goto out;
+ } else {
+ const struct mvsdio_platform_data *mvsd_data;
++
+ mvsd_data = pdev->dev.platform_data;
+ if (!mvsd_data) {
+ ret = -ENXIO;
+ goto out;
+ }
++ mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
++ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
+ host->base_clock = mvsd_data->clock / 2;
+- gpio_card_detect = mvsd_data->gpio_card_detect ? : -EINVAL;
+- gpio_write_protect = mvsd_data->gpio_write_protect ? : -EINVAL;
+- }
+-
+- mmc->ops = &mvsd_ops;
+-
+- mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+- mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
+- MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
+-
+- mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
+- mmc->f_max = maxfreq;
++ /* GPIO 0 regarded as invalid for backward compatibility */
++ if (mvsd_data->gpio_card_detect &&
++ gpio_is_valid(mvsd_data->gpio_card_detect)) {
++ ret = mmc_gpio_request_cd(mmc,
++ mvsd_data->gpio_card_detect,
++ 0);
++ if (ret)
++ goto out;
++ } else {
++ mmc->caps |= MMC_CAP_NEEDS_POLL;
++ }
+
+- mmc->max_blk_size = 2048;
+- mmc->max_blk_count = 65535;
++ if (mvsd_data->gpio_write_protect &&
++ gpio_is_valid(mvsd_data->gpio_write_protect))
++ mmc_gpio_request_ro(mmc, mvsd_data->gpio_write_protect);
++ }
+
+- mmc->max_segs = 1;
+- mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
+- mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
++ if (maxfreq)
++ mmc->f_max = maxfreq;
+
+ spin_lock_init(&host->lock);
+
+@@ -777,15 +794,6 @@
+ goto out;
+ }
+
+- if (gpio_is_valid(gpio_card_detect)) {
+- ret = mmc_gpio_request_cd(mmc, gpio_card_detect);
+- if (ret)
+- goto out;
+- } else
+- mmc->caps |= MMC_CAP_NEEDS_POLL;
+-
+- mmc_gpio_request_ro(mmc, gpio_write_protect);
+-
+ setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
+ platform_set_drvdata(pdev, mmc);
+ ret = mmc_add_host(mmc);
+@@ -793,10 +801,10 @@
+ goto out;
+
+ if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
+- dev_notice(&pdev->dev, "using GPIO %d for card detection\n",
+- gpio_card_detect);
++ dev_notice(&pdev->dev, "using GPIO for card detection\n");
+ else
+- dev_notice(&pdev->dev, "lacking card detect (fall back to polling)\n");
++ dev_notice(&pdev->dev,
++ "lacking card detect (fall back to polling)\n");
+ return 0;
+
+ out:
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-bcm2835.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-bcm2835.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-bcm2835.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-bcm2835.c 2014-05-15 20:33:58.242015624 +0200
+@@ -131,8 +131,12 @@
+ .read_l = bcm2835_sdhci_readl,
+ .read_w = bcm2835_sdhci_readw,
+ .read_b = bcm2835_sdhci_readb,
++ .set_clock = sdhci_set_clock,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .get_min_clock = bcm2835_sdhci_get_min_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci.c 2014-05-15 20:33:58.246015652 +0200
+@@ -44,12 +44,13 @@
+
+ #define MAX_TUNING_LOOP 40
+
++#define ADMA_SIZE ((128 * 2 + 1) * 4)
++
+ static unsigned int debug_quirks = 0;
+ static unsigned int debug_quirks2;
+
+ static void sdhci_finish_data(struct sdhci_host *);
+
+-static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
+ static void sdhci_finish_command(struct sdhci_host *);
+ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
+ static void sdhci_tuning_timer(unsigned long data);
+@@ -58,6 +59,8 @@
+ #ifdef CONFIG_PM_RUNTIME
+ static int sdhci_runtime_pm_get(struct sdhci_host *host);
+ static int sdhci_runtime_pm_put(struct sdhci_host *host);
++static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
++static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
+ #else
+ static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
+ {
+@@ -67,6 +70,12 @@
+ {
+ return 0;
+ }
++static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
++{
++}
++static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
++{
++}
+ #endif
+
+ static void sdhci_dumpregs(struct sdhci_host *host)
+@@ -124,43 +133,26 @@
+ * *
+ \*****************************************************************************/
+
+-static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
+-{
+- u32 ier;
+-
+- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+- ier &= ~clear;
+- ier |= set;
+- sdhci_writel(host, ier, SDHCI_INT_ENABLE);
+- sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
+-}
+-
+-static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
+-{
+- sdhci_clear_set_irqs(host, 0, irqs);
+-}
+-
+-static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
+-{
+- sdhci_clear_set_irqs(host, irqs, 0);
+-}
+-
+ static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
+ {
+- u32 present, irqs;
++ u32 present;
+
+ if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
+ (host->mmc->caps & MMC_CAP_NONREMOVABLE))
+ return;
+
+- present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
+- SDHCI_CARD_PRESENT;
+- irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
++ if (enable) {
++ present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
++ SDHCI_CARD_PRESENT;
+
+- if (enable)
+- sdhci_unmask_irqs(host, irqs);
+- else
+- sdhci_mask_irqs(host, irqs);
++ host->ier |= present ? SDHCI_INT_CARD_REMOVE :
++ SDHCI_INT_CARD_INSERT;
++ } else {
++ host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
++ }
++
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
+
+ static void sdhci_enable_card_detection(struct sdhci_host *host)
+@@ -173,27 +165,18 @@
+ sdhci_set_card_detection(host, false);
+ }
+
+-static void sdhci_reset(struct sdhci_host *host, u8 mask)
++void sdhci_reset(struct sdhci_host *host, u8 mask)
+ {
+ unsigned long timeout;
+- u32 uninitialized_var(ier);
+-
+- if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
+- if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
+- SDHCI_CARD_PRESENT))
+- return;
+- }
+-
+- if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
+- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+-
+- if (host->ops->platform_reset_enter)
+- host->ops->platform_reset_enter(host, mask);
+
+ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+
+- if (mask & SDHCI_RESET_ALL)
++ if (mask & SDHCI_RESET_ALL) {
+ host->clock = 0;
++ /* Reset-all turns off SD Bus Power */
++ if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
++ sdhci_runtime_pm_bus_off(host);
++ }
+
+ /* Wait max 100 ms */
+ timeout = 100;
+@@ -209,12 +192,18 @@
+ timeout--;
+ mdelay(1);
+ }
++}
++EXPORT_SYMBOL_GPL(sdhci_reset);
+
+- if (host->ops->platform_reset_exit)
+- host->ops->platform_reset_exit(host, mask);
++static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
++{
++ if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
++ if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
++ SDHCI_CARD_PRESENT))
++ return;
++ }
+
+- if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
+- sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
++ host->ops->reset(host, mask);
+
+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+ if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
+@@ -227,15 +216,18 @@
+ static void sdhci_init(struct sdhci_host *host, int soft)
+ {
+ if (soft)
+- sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
+ else
+- sdhci_reset(host, SDHCI_RESET_ALL);
++ sdhci_do_reset(host, SDHCI_RESET_ALL);
+
+- sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
+- SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
+- SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
+- SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
+- SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
++ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
++ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
++ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
++ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
++ SDHCI_INT_RESPONSE;
++
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+
+ if (soft) {
+ /* force clock reconfiguration */
+@@ -491,11 +483,6 @@
+ else
+ direction = DMA_TO_DEVICE;
+
+- /*
+- * The ADMA descriptor table is mapped further down as we
+- * need to fill it with data first.
+- */
+-
+ host->align_addr = dma_map_single(mmc_dev(host->mmc),
+ host->align_buffer, 128 * 4, direction);
+ if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
+@@ -556,7 +543,7 @@
+ * If this triggers then we have a calculation bug
+ * somewhere. :/
+ */
+- WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
++ WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
+ }
+
+ if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
+@@ -584,17 +571,8 @@
+ host->align_addr, 128 * 4, direction);
+ }
+
+- host->adma_addr = dma_map_single(mmc_dev(host->mmc),
+- host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
+- if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
+- goto unmap_entries;
+- BUG_ON(host->adma_addr & 0x3);
+-
+ return 0;
+
+-unmap_entries:
+- dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+- data->sg_len, direction);
+ unmap_align:
+ dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
+ 128 * 4, direction);
+@@ -612,19 +590,25 @@
+ u8 *align;
+ char *buffer;
+ unsigned long flags;
++ bool has_unaligned;
+
+ if (data->flags & MMC_DATA_READ)
+ direction = DMA_FROM_DEVICE;
+ else
+ direction = DMA_TO_DEVICE;
+
+- dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
+- (128 * 2 + 1) * 4, DMA_TO_DEVICE);
+-
+ dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
+ 128 * 4, direction);
+
+- if (data->flags & MMC_DATA_READ) {
++ /* Do a quick scan of the SG list for any unaligned mappings */
++ has_unaligned = false;
++ for_each_sg(data->sg, sg, host->sg_count, i)
++ if (sg_dma_address(sg) & 3) {
++ has_unaligned = true;
++ break;
++ }
++
++ if (has_unaligned && data->flags & MMC_DATA_READ) {
+ dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
+ data->sg_len, direction);
+
+@@ -710,9 +694,12 @@
+ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
+
+ if (host->flags & SDHCI_REQ_USE_DMA)
+- sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
++ host->ier = (host->ier & ~pio_irqs) | dma_irqs;
+ else
+- sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
++ host->ier = (host->ier & ~dma_irqs) | pio_irqs;
++
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
+
+ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
+@@ -887,8 +874,13 @@
+ u16 mode;
+ struct mmc_data *data = cmd->data;
+
+- if (data == NULL)
++ if (data == NULL) {
++ /* clear Auto CMD settings for no data CMDs */
++ mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
++ sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
++ SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
+ return;
++ }
+
+ WARN_ON(!host->data);
+
+@@ -960,8 +952,8 @@
+ * upon error conditions.
+ */
+ if (data->error) {
+- sdhci_reset(host, SDHCI_RESET_CMD);
+- sdhci_reset(host, SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD);
++ sdhci_do_reset(host, SDHCI_RESET_DATA);
+ }
+
+ sdhci_send_command(host, data->stop);
+@@ -969,7 +961,7 @@
+ tasklet_schedule(&host->finish_tasklet);
+ }
+
+-static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
++void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
+ {
+ int flags;
+ u32 mask;
+@@ -1041,6 +1033,7 @@
+
+ sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
+ }
++EXPORT_SYMBOL_GPL(sdhci_send_command);
+
+ static void sdhci_finish_command(struct sdhci_host *host)
+ {
+@@ -1085,24 +1078,23 @@
+
+ static u16 sdhci_get_preset_value(struct sdhci_host *host)
+ {
+- u16 ctrl, preset = 0;
+-
+- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
++ u16 preset = 0;
+
+- switch (ctrl & SDHCI_CTRL_UHS_MASK) {
+- case SDHCI_CTRL_UHS_SDR12:
++ switch (host->timing) {
++ case MMC_TIMING_UHS_SDR12:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
+ break;
+- case SDHCI_CTRL_UHS_SDR25:
++ case MMC_TIMING_UHS_SDR25:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
+ break;
+- case SDHCI_CTRL_UHS_SDR50:
++ case MMC_TIMING_UHS_SDR50:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
+ break;
+- case SDHCI_CTRL_UHS_SDR104:
++ case MMC_TIMING_UHS_SDR104:
++ case MMC_TIMING_MMC_HS200:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
+ break;
+- case SDHCI_CTRL_UHS_DDR50:
++ case MMC_TIMING_UHS_DDR50:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
+ break;
+ default:
+@@ -1114,28 +1106,19 @@
+ return preset;
+ }
+
+-static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
++void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+ {
+ int div = 0; /* Initialized for compiler warning */
+ int real_div = div, clk_mul = 1;
+ u16 clk = 0;
+ unsigned long timeout;
+
+- if (clock && clock == host->clock)
+- return;
+-
+ host->mmc->actual_clock = 0;
+
+- if (host->ops->set_clock) {
+- host->ops->set_clock(host, clock);
+- if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
+- return;
+- }
+-
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+- goto out;
++ return;
+
+ if (host->version >= SDHCI_SPEC_300) {
+ if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
+@@ -1225,19 +1208,8 @@
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+-
+-out:
+- host->clock = clock;
+-}
+-
+-static inline void sdhci_update_clock(struct sdhci_host *host)
+-{
+- unsigned int clock;
+-
+- clock = host->clock;
+- host->clock = 0;
+- sdhci_set_clock(host, clock);
+ }
++EXPORT_SYMBOL_GPL(sdhci_set_clock);
+
+ static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
+ {
+@@ -1268,6 +1240,8 @@
+
+ if (pwr == 0) {
+ sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
++ if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
++ sdhci_runtime_pm_bus_off(host);
+ return 0;
+ }
+
+@@ -1289,6 +1263,9 @@
+
+ sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
++ if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
++ sdhci_runtime_pm_bus_on(host);
++
+ /*
+ * Some controllers need an extra 10ms delay of 10ms before they
+ * can apply clock after applying power
+@@ -1393,6 +1370,49 @@
+ spin_unlock_irqrestore(&host->lock, flags);
+ }
+
++void sdhci_set_bus_width(struct sdhci_host *host, int width)
++{
++ u8 ctrl;
++
++ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
++ if (width == MMC_BUS_WIDTH_8) {
++ ctrl &= ~SDHCI_CTRL_4BITBUS;
++ if (host->version >= SDHCI_SPEC_300)
++ ctrl |= SDHCI_CTRL_8BITBUS;
++ } else {
++ if (host->version >= SDHCI_SPEC_300)
++ ctrl &= ~SDHCI_CTRL_8BITBUS;
++ if (width == MMC_BUS_WIDTH_4)
++ ctrl |= SDHCI_CTRL_4BITBUS;
++ else
++ ctrl &= ~SDHCI_CTRL_4BITBUS;
++ }
++ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
++}
++EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
++
++void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
++{
++ u16 ctrl_2;
++
++ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
++ /* Select Bus Speed Mode for host */
++ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
++ if ((timing == MMC_TIMING_MMC_HS200) ||
++ (timing == MMC_TIMING_UHS_SDR104))
++ ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
++ else if (timing == MMC_TIMING_UHS_SDR12)
++ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
++ else if (timing == MMC_TIMING_UHS_SDR25)
++ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
++ else if (timing == MMC_TIMING_UHS_SDR50)
++ ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
++ else if (timing == MMC_TIMING_UHS_DDR50)
++ ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
++ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
++}
++EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
++
+ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
+ {
+ unsigned long flags;
+@@ -1418,10 +1438,14 @@
+ }
+
+ if (host->version >= SDHCI_SPEC_300 &&
+- (ios->power_mode == MMC_POWER_UP))
++ (ios->power_mode == MMC_POWER_UP) &&
++ !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
+ sdhci_enable_preset_value(host, false);
+
+- sdhci_set_clock(host, ios->clock);
++ if (!ios->clock || ios->clock != host->clock) {
++ host->ops->set_clock(host, ios->clock);
++ host->clock = ios->clock;
++ }
+
+ if (ios->power_mode == MMC_POWER_OFF)
+ vdd_bit = sdhci_set_power(host, -1);
+@@ -1437,29 +1461,7 @@
+ if (host->ops->platform_send_init_74_clocks)
+ host->ops->platform_send_init_74_clocks(host, ios->power_mode);
+
+- /*
+- * If your platform has 8-bit width support but is not a v3 controller,
+- * or if it requires special setup code, you should implement that in
+- * platform_bus_width().
+- */
+- if (host->ops->platform_bus_width) {
+- host->ops->platform_bus_width(host, ios->bus_width);
+- } else {
+- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+- if (ios->bus_width == MMC_BUS_WIDTH_8) {
+- ctrl &= ~SDHCI_CTRL_4BITBUS;
+- if (host->version >= SDHCI_SPEC_300)
+- ctrl |= SDHCI_CTRL_8BITBUS;
+- } else {
+- if (host->version >= SDHCI_SPEC_300)
+- ctrl &= ~SDHCI_CTRL_8BITBUS;
+- if (ios->bus_width == MMC_BUS_WIDTH_4)
+- ctrl |= SDHCI_CTRL_4BITBUS;
+- else
+- ctrl &= ~SDHCI_CTRL_4BITBUS;
+- }
+- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+- }
++ host->ops->set_bus_width(host, ios->bus_width);
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+
+@@ -1496,6 +1498,7 @@
+
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+ } else {
++ int timeout;
+ /*
+ * According to SDHC Spec v3.00, if the Preset Value
+ * Enable in the Host Control 2 register is set, we
+@@ -1510,36 +1513,23 @@
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+- /* Re-enable SD Clock */
+- sdhci_update_clock(host);
++ /* Wait max 5 ms */
++ timeout = 10;
++ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
++ & SDHCI_CLOCK_INT_STABLE)) {
++ if (timeout == 0) {
++ pr_err("%s: Internal clock never "
++ "stabilised.\n", mmc_hostname(host->mmc));
++ sdhci_dumpregs(host);
++ return;
++ }
++ timeout--;
++ mdelay(1);
++ }
+ }
+
+-
+- /* Reset SD Clock Enable */
+- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+- clk &= ~SDHCI_CLOCK_CARD_EN;
+- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+-
+- if (host->ops->set_uhs_signaling)
+- host->ops->set_uhs_signaling(host, ios->timing);
+- else {
+- ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+- /* Select Bus Speed Mode for host */
+- ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+- if (ios->timing == MMC_TIMING_MMC_HS200)
+- ctrl_2 |= SDHCI_CTRL_HS_SDR200;
+- else if (ios->timing == MMC_TIMING_UHS_SDR12)
+- ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+- else if (ios->timing == MMC_TIMING_UHS_SDR25)
+- ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+- else if (ios->timing == MMC_TIMING_UHS_SDR50)
+- ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+- else if (ios->timing == MMC_TIMING_UHS_SDR104)
+- ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+- else if (ios->timing == MMC_TIMING_UHS_DDR50)
+- ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+- sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+- }
++ host->ops->set_uhs_signaling(host, ios->timing);
++ host->timing = ios->timing;
+
+ if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
+ ((ios->timing == MMC_TIMING_UHS_SDR12) ||
+@@ -1556,7 +1546,7 @@
+ }
+
+ /* Re-enable SD Clock */
+- sdhci_update_clock(host);
++ host->ops->set_clock(host, host->clock);
+ } else
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+@@ -1566,7 +1556,7 @@
+ * it on each ios seems to solve the problem.
+ */
+ if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
+- sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+ mmiowb();
+ spin_unlock_irqrestore(&host->lock, flags);
+@@ -1675,24 +1665,16 @@
+
+ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
+ {
+- if (host->flags & SDHCI_DEVICE_DEAD)
+- goto out;
+-
+- if (enable)
+- host->flags |= SDHCI_SDIO_IRQ_ENABLED;
+- else
+- host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
+-
+- /* SDIO IRQ will be enabled as appropriate in runtime resume */
+- if (host->runtime_suspended)
+- goto out;
++ if (!(host->flags & SDHCI_DEVICE_DEAD)) {
++ if (enable)
++ host->ier |= SDHCI_INT_CARD_INT;
++ else
++ host->ier &= ~SDHCI_INT_CARD_INT;
+
+- if (enable)
+- sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
+- else
+- sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
+-out:
+- mmiowb();
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
++ mmiowb();
++ }
+ }
+
+ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+@@ -1700,9 +1682,19 @@
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
++ sdhci_runtime_pm_get(host);
++
+ spin_lock_irqsave(&host->lock, flags);
++
++ if (enable)
++ host->flags |= SDHCI_SDIO_IRQ_ENABLED;
++ else
++ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
++
+ sdhci_enable_sdio_irq_nolock(host, enable);
+ spin_unlock_irqrestore(&host->lock, flags);
++
++ sdhci_runtime_pm_put(host);
+ }
+
+ static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
+@@ -1764,9 +1756,6 @@
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+- /* Wait for 5ms */
+- usleep_range(5000, 5500);
+-
+ /* 1.8V regulator output should be stable within 5 ms */
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (ctrl & SDHCI_CTRL_VDD_180)
+@@ -1821,22 +1810,16 @@
+
+ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+ {
+- struct sdhci_host *host;
++ struct sdhci_host *host = mmc_priv(mmc);
+ u16 ctrl;
+- u32 ier;
+ int tuning_loop_counter = MAX_TUNING_LOOP;
+ unsigned long timeout;
+ int err = 0;
+- bool requires_tuning_nonuhs = false;
+-
+- host = mmc_priv(mmc);
+
+ sdhci_runtime_pm_get(host);
+ disable_irq(host->irq);
+ spin_lock(&host->lock);
+
+- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+-
+ /*
+ * The Host Controller needs tuning only in case of SDR104 mode
+ * and for SDR50 mode when Use Tuning for SDR50 is set in the
+@@ -1844,21 +1827,34 @@
+ * If the Host Controller supports the HS200 mode then the
+ * tuning function has to be executed.
+ */
+- if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
+- (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
+- host->flags & SDHCI_HS200_NEEDS_TUNING))
+- requires_tuning_nonuhs = true;
+-
+- if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
+- requires_tuning_nonuhs)
+- ctrl |= SDHCI_CTRL_EXEC_TUNING;
+- else {
++ switch (host->timing) {
++ case MMC_TIMING_MMC_HS200:
++ case MMC_TIMING_UHS_SDR104:
++ break;
++
++ case MMC_TIMING_UHS_SDR50:
++ if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
++ host->flags & SDHCI_SDR104_NEEDS_TUNING)
++ break;
++ /* FALLTHROUGH */
++
++ default:
+ spin_unlock(&host->lock);
+ enable_irq(host->irq);
+ sdhci_runtime_pm_put(host);
+ return 0;
+ }
+
++ if (host->ops->platform_execute_tuning) {
++ spin_unlock(&host->lock);
++ enable_irq(host->irq);
++ err = host->ops->platform_execute_tuning(host, opcode);
++ sdhci_runtime_pm_put(host);
++ return err;
++ }
++
++ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
++ ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ /*
+@@ -1871,8 +1867,8 @@
+ * to make sure we don't hit a controller bug, we _only_
+ * enable Buffer Read Ready interrupt here.
+ */
+- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+- sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
++ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
++ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+
+ /*
+ * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
+@@ -1965,6 +1961,7 @@
+ if (!tuning_loop_counter || !timeout) {
+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
++ err = -EIO;
+ } else {
+ if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+ pr_info(DRIVER_NAME ": Tuning procedure"
+@@ -2007,7 +2004,8 @@
+ if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
+ err = 0;
+
+- sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ spin_unlock(&host->lock);
+ enable_irq(host->irq);
+ sdhci_runtime_pm_put(host);
+@@ -2049,15 +2047,14 @@
+ spin_lock_irqsave(&host->lock, flags);
+
+ /* Check host->mrq first in case we are runtime suspended */
+- if (host->mrq &&
+- !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
++ if (host->mrq && !sdhci_do_get_cd(host)) {
+ pr_err("%s: Card removed during transfer!\n",
+ mmc_hostname(host->mmc));
+ pr_err("%s: Resetting controller.\n",
+ mmc_hostname(host->mmc));
+
+- sdhci_reset(host, SDHCI_RESET_CMD);
+- sdhci_reset(host, SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD);
++ sdhci_do_reset(host, SDHCI_RESET_DATA);
+
+ host->mrq->cmd->error = -ENOMEDIUM;
+ tasklet_schedule(&host->finish_tasklet);
+@@ -2085,15 +2082,6 @@
+ * *
+ \*****************************************************************************/
+
+-static void sdhci_tasklet_card(unsigned long param)
+-{
+- struct sdhci_host *host = (struct sdhci_host*)param;
+-
+- sdhci_card_event(host->mmc);
+-
+- mmc_detect_change(host->mmc, msecs_to_jiffies(200));
+-}
+-
+ static void sdhci_tasklet_finish(unsigned long param)
+ {
+ struct sdhci_host *host;
+@@ -2130,12 +2118,12 @@
+ /* Some controllers need this kick or reset won't work here */
+ if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
+ /* This is to force an update */
+- sdhci_update_clock(host);
++ host->ops->set_clock(host, host->clock);
+
+ /* Spec says we should do both at the same time, but Ricoh
+ controllers do not like that. */
+- sdhci_reset(host, SDHCI_RESET_CMD);
+- sdhci_reset(host, SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD);
++ sdhci_do_reset(host, SDHCI_RESET_DATA);
+ }
+
+ host->mrq = NULL;
+@@ -2385,14 +2373,14 @@
+
+ static irqreturn_t sdhci_irq(int irq, void *dev_id)
+ {
+- irqreturn_t result;
++ irqreturn_t result = IRQ_NONE;
+ struct sdhci_host *host = dev_id;
+- u32 intmask, unexpected = 0;
+- int cardint = 0, max_loops = 16;
++ u32 intmask, mask, unexpected = 0;
++ int max_loops = 16;
+
+ spin_lock(&host->lock);
+
+- if (host->runtime_suspended) {
++ if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
+ spin_unlock(&host->lock);
+ pr_warning("%s: got irq while runtime suspended\n",
+ mmc_hostname(host->mmc));
+@@ -2400,80 +2388,81 @@
+ }
+
+ intmask = sdhci_readl(host, SDHCI_INT_STATUS);
+-
+ if (!intmask || intmask == 0xffffffff) {
+ result = IRQ_NONE;
+ goto out;
+ }
+
+-again:
+- DBG("*** %s got interrupt: 0x%08x\n",
+- mmc_hostname(host->mmc), intmask);
+-
+- if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
+- u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
+- SDHCI_CARD_PRESENT;
+-
+- /*
+- * There is a observation on i.mx esdhc. INSERT bit will be
+- * immediately set again when it gets cleared, if a card is
+- * inserted. We have to mask the irq to prevent interrupt
+- * storm which will freeze the system. And the REMOVE gets
+- * the same situation.
+- *
+- * More testing are needed here to ensure it works for other
+- * platforms though.
+- */
+- sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
+- SDHCI_INT_CARD_REMOVE);
+- sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
+- SDHCI_INT_CARD_INSERT);
+-
+- sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
+- SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
+- intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
+- tasklet_schedule(&host->card_tasklet);
+- }
++ do {
++ /* Clear selected interrupts. */
++ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
++ SDHCI_INT_BUS_POWER);
++ sdhci_writel(host, mask, SDHCI_INT_STATUS);
++
++ DBG("*** %s got interrupt: 0x%08x\n",
++ mmc_hostname(host->mmc), intmask);
++
++ if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
++ u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
++ SDHCI_CARD_PRESENT;
+
+- if (intmask & SDHCI_INT_CMD_MASK) {
+- sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
+- SDHCI_INT_STATUS);
+- sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
+- }
++ /*
++ * There is a observation on i.mx esdhc. INSERT
++ * bit will be immediately set again when it gets
++ * cleared, if a card is inserted. We have to mask
++ * the irq to prevent interrupt storm which will
++ * freeze the system. And the REMOVE gets the
++ * same situation.
++ *
++ * More testing are needed here to ensure it works
++ * for other platforms though.
++ */
++ host->ier &= ~(SDHCI_INT_CARD_INSERT |
++ SDHCI_INT_CARD_REMOVE);
++ host->ier |= present ? SDHCI_INT_CARD_REMOVE :
++ SDHCI_INT_CARD_INSERT;
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+
+- if (intmask & SDHCI_INT_DATA_MASK) {
+- sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
+- SDHCI_INT_STATUS);
+- sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
+- }
++ sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
++ SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
+
+- intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
++ host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
++ SDHCI_INT_CARD_REMOVE);
++ result = IRQ_WAKE_THREAD;
++ }
+
+- intmask &= ~SDHCI_INT_ERROR;
++ if (intmask & SDHCI_INT_CMD_MASK)
++ sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
+
+- if (intmask & SDHCI_INT_BUS_POWER) {
+- pr_err("%s: Card is consuming too much power!\n",
+- mmc_hostname(host->mmc));
+- sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
+- }
++ if (intmask & SDHCI_INT_DATA_MASK)
++ sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
+
+- intmask &= ~SDHCI_INT_BUS_POWER;
++ if (intmask & SDHCI_INT_BUS_POWER)
++ pr_err("%s: Card is consuming too much power!\n",
++ mmc_hostname(host->mmc));
+
+- if (intmask & SDHCI_INT_CARD_INT)
+- cardint = 1;
++ if (intmask & SDHCI_INT_CARD_INT) {
++ sdhci_enable_sdio_irq_nolock(host, false);
++ host->thread_isr |= SDHCI_INT_CARD_INT;
++ result = IRQ_WAKE_THREAD;
++ }
+
+- intmask &= ~SDHCI_INT_CARD_INT;
++ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
++ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
++ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
++ SDHCI_INT_CARD_INT);
+
+- if (intmask) {
+- unexpected |= intmask;
+- sdhci_writel(host, intmask, SDHCI_INT_STATUS);
+- }
++ if (intmask) {
++ unexpected |= intmask;
++ sdhci_writel(host, intmask, SDHCI_INT_STATUS);
++ }
+
+- result = IRQ_HANDLED;
++ if (result == IRQ_NONE)
++ result = IRQ_HANDLED;
+
+- intmask = sdhci_readl(host, SDHCI_INT_STATUS);
+- if (intmask && --max_loops)
+- goto again;
++ intmask = sdhci_readl(host, SDHCI_INT_STATUS);
++ } while (intmask && --max_loops);
+ out:
+ spin_unlock(&host->lock);
+
+@@ -2482,15 +2471,38 @@
+ mmc_hostname(host->mmc), unexpected);
+ sdhci_dumpregs(host);
+ }
+- /*
+- * We have to delay this as it calls back into the driver.
+- */
+- if (cardint)
+- mmc_signal_sdio_irq(host->mmc);
+
+ return result;
+ }
+
++static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
++{
++ struct sdhci_host *host = dev_id;
++ unsigned long flags;
++ u32 isr;
++
++ spin_lock_irqsave(&host->lock, flags);
++ isr = host->thread_isr;
++ host->thread_isr = 0;
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
++ sdhci_card_event(host->mmc);
++ mmc_detect_change(host->mmc, msecs_to_jiffies(200));
++ }
++
++ if (isr & SDHCI_INT_CARD_INT) {
++ sdio_run_irqs(host->mmc);
++
++ spin_lock_irqsave(&host->lock, flags);
++ if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
++ sdhci_enable_sdio_irq_nolock(host, true);
++ spin_unlock_irqrestore(&host->lock, flags);
++ }
++
++ return isr ? IRQ_HANDLED : IRQ_NONE;
++}
++
+ /*****************************************************************************\
+ * *
+ * Suspend/resume *
+@@ -2529,9 +2541,6 @@
+ {
+ int ret;
+
+- if (host->ops->platform_suspend)
+- host->ops->platform_suspend(host);
+-
+ sdhci_disable_card_detection(host);
+
+ /* Disable tuning since we are suspending */
+@@ -2554,7 +2563,9 @@
+ }
+
+ if (!device_may_wakeup(mmc_dev(host->mmc))) {
+- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
++ host->ier = 0;
++ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
++ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+ } else {
+ sdhci_enable_irq_wakeups(host);
+@@ -2575,8 +2586,9 @@
+ }
+
+ if (!device_may_wakeup(mmc_dev(host->mmc))) {
+- ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
+- mmc_hostname(host->mmc), host);
++ ret = request_threaded_irq(host->irq, sdhci_irq,
++ sdhci_thread_irq, IRQF_SHARED,
++ mmc_hostname(host->mmc), host);
+ if (ret)
+ return ret;
+ } else {
+@@ -2599,9 +2611,6 @@
+ ret = mmc_resume_host(host->mmc);
+ sdhci_enable_card_detection(host);
+
+- if (host->ops->platform_resume)
+- host->ops->platform_resume(host);
+-
+ /* Set the re-tuning expiration flag */
+ if (host->flags & SDHCI_USING_RETUNING_TIMER)
+ host->flags |= SDHCI_NEEDS_RETUNING;
+@@ -2625,6 +2634,22 @@
+ return pm_runtime_put_autosuspend(host->mmc->parent);
+ }
+
++static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
++{
++ if (host->runtime_suspended || host->bus_on)
++ return;
++ host->bus_on = true;
++ pm_runtime_get_noresume(host->mmc->parent);
++}
++
++static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
++{
++ if (host->runtime_suspended || !host->bus_on)
++ return;
++ host->bus_on = false;
++ pm_runtime_put_noidle(host->mmc->parent);
++}
++
+ int sdhci_runtime_suspend_host(struct sdhci_host *host)
+ {
+ unsigned long flags;
+@@ -2637,10 +2662,12 @@
+ }
+
+ spin_lock_irqsave(&host->lock, flags);
+- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
++ host->ier &= SDHCI_INT_CARD_INT;
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+- synchronize_irq(host->irq);
++ synchronize_hardirq(host->irq);
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->runtime_suspended = true;
+@@ -2684,7 +2711,7 @@
+ host->runtime_suspended = false;
+
+ /* Enable SDIO IRQ */
+- if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
++ if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
+ sdhci_enable_sdio_irq_nolock(host, true);
+
+ /* Enable Card Detection */
+@@ -2743,7 +2770,7 @@
+ if (debug_quirks2)
+ host->quirks2 = debug_quirks2;
+
+- sdhci_reset(host, SDHCI_RESET_ALL);
++ sdhci_do_reset(host, SDHCI_RESET_ALL);
+
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ host->version = (host->version & SDHCI_SPEC_VER_MASK)
+@@ -2803,15 +2830,29 @@
+ * (128) and potentially one alignment transfer for
+ * each of those entries.
+ */
+- host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
++ host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
++ ADMA_SIZE, &host->adma_addr,
++ GFP_KERNEL);
+ host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
+ if (!host->adma_desc || !host->align_buffer) {
+- kfree(host->adma_desc);
++ dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
++ host->adma_desc, host->adma_addr);
+ kfree(host->align_buffer);
+ pr_warning("%s: Unable to allocate ADMA "
+ "buffers. Falling back to standard DMA.\n",
+ mmc_hostname(mmc));
+ host->flags &= ~SDHCI_USE_ADMA;
++ host->adma_desc = NULL;
++ host->align_buffer = NULL;
++ } else if (host->adma_addr & 3) {
++ pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
++ mmc_hostname(mmc));
++ host->flags &= ~SDHCI_USE_ADMA;
++ dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
++ host->adma_desc, host->adma_addr);
++ kfree(host->align_buffer);
++ host->adma_desc = NULL;
++ host->align_buffer = NULL;
+ }
+ }
+
+@@ -2893,9 +2934,22 @@
+ if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
+ host->timeout_clk = mmc->f_max / 1000;
+
+- mmc->max_discard_to = (1 << 27) / host->timeout_clk;
++ if (host->quirks2 & SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER) {
++ if (host->ops->get_max_timeout_counter) {
++ mmc->max_discard_to =
++ host->ops->get_max_timeout_counter(host)
++ / host->timeout_clk;
++ } else {
++ pr_err("%s: Hardware doesn't specify max timeout "
++ "counter\n", mmc_hostname(mmc));
++ return -ENODEV;
++ }
++ } else {
++ mmc->max_discard_to = (1 << 27) / host->timeout_clk;
++ }
+
+ mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
++ mmc->caps2 |= MMC_CAP2_SDIO_NOTHREAD;
+
+ if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
+ host->flags |= SDHCI_AUTO_CMD12;
+@@ -2962,9 +3016,13 @@
+ mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
+
+ /* SDR104 supports also implies SDR50 support */
+- if (caps[1] & SDHCI_SUPPORT_SDR104)
++ if (caps[1] & SDHCI_SUPPORT_SDR104) {
+ mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
+- else if (caps[1] & SDHCI_SUPPORT_SDR50)
++ /* SD3.0: SDR104 is supported so (for eMMC) the caps2
++ * field can be promoted to support HS200.
++ */
++ mmc->caps2 |= MMC_CAP2_HS200;
++ } else if (caps[1] & SDHCI_SUPPORT_SDR50)
+ mmc->caps |= MMC_CAP_UHS_SDR50;
+
+ if (caps[1] & SDHCI_SUPPORT_DDR50)
+@@ -2974,9 +3032,9 @@
+ if (caps[1] & SDHCI_USE_SDR50_TUNING)
+ host->flags |= SDHCI_SDR50_NEEDS_TUNING;
+
+- /* Does the host need tuning for HS200? */
++ /* Does the host need tuning for SDR104 / HS200? */
+ if (mmc->caps2 & MMC_CAP2_HS200)
+- host->flags |= SDHCI_HS200_NEEDS_TUNING;
++ host->flags |= SDHCI_SDR104_NEEDS_TUNING;
+
+ /* Driver Type(s) (A, C, D) supported by the host */
+ if (caps[1] & SDHCI_DRIVER_TYPE_A)
+@@ -3158,8 +3216,6 @@
+ /*
+ * Init tasklets.
+ */
+- tasklet_init(&host->card_tasklet,
+- sdhci_tasklet_card, (unsigned long)host);
+ tasklet_init(&host->finish_tasklet,
+ sdhci_tasklet_finish, (unsigned long)host);
+
+@@ -3174,16 +3230,16 @@
+ host->tuning_timer.function = sdhci_tuning_timer;
+ }
+
+- ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
+- mmc_hostname(mmc), host);
++ sdhci_init(host, 0);
++
++ ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
++ IRQF_SHARED, mmc_hostname(mmc), host);
+ if (ret) {
+ pr_err("%s: Failed to request IRQ %d: %d\n",
+ mmc_hostname(mmc), host->irq, ret);
+ goto untasklet;
+ }
+
+- sdhci_init(host, 0);
+-
+ #ifdef CONFIG_MMC_DEBUG
+ sdhci_dumpregs(host);
+ #endif
+@@ -3219,12 +3275,12 @@
+
+ #ifdef SDHCI_USE_LEDS_CLASS
+ reset:
+- sdhci_reset(host, SDHCI_RESET_ALL);
+- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
++ sdhci_do_reset(host, SDHCI_RESET_ALL);
++ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
++ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+ #endif
+ untasklet:
+- tasklet_kill(&host->card_tasklet);
+ tasklet_kill(&host->finish_tasklet);
+
+ return ret;
+@@ -3261,14 +3317,14 @@
+ #endif
+
+ if (!dead)
+- sdhci_reset(host, SDHCI_RESET_ALL);
++ sdhci_do_reset(host, SDHCI_RESET_ALL);
+
+- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
++ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
++ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+
+ del_timer_sync(&host->timer);
+
+- tasklet_kill(&host->card_tasklet);
+ tasklet_kill(&host->finish_tasklet);
+
+ if (host->vmmc) {
+@@ -3281,7 +3337,9 @@
+ regulator_put(host->vqmmc);
+ }
+
+- kfree(host->adma_desc);
++ if (host->adma_desc)
++ dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
++ host->adma_desc, host->adma_addr);
+ kfree(host->align_buffer);
+
+ host->adma_desc = NULL;
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-cns3xxx.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-cns3xxx.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-cns3xxx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-cns3xxx.c 2014-05-15 20:33:58.242015624 +0200
+@@ -30,13 +30,12 @@
+ u16 clk;
+ unsigned long timeout;
+
+- if (clock == host->clock)
+- return;
++ host->mmc->actual_clock = 0;
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+- goto out;
++ return;
+
+ while (host->max_clk / div > clock) {
+ /*
+@@ -75,13 +74,14 @@
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+-out:
+- host->clock = clock;
+ }
+
+ static const struct sdhci_ops sdhci_cns3xxx_ops = {
+ .get_max_clock = sdhci_cns3xxx_get_max_clk,
+ .set_clock = sdhci_cns3xxx_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
+@@ -90,8 +90,7 @@
+ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
+ SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+- SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
+- SDHCI_QUIRK_NONSTANDARD_CLOCK,
++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
+ };
+
+ static int sdhci_cns3xxx_probe(struct platform_device *pdev)
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-dove.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-dove.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-dove.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-dove.c 2014-05-15 20:33:58.242015624 +0200
+@@ -86,6 +86,10 @@
+ static const struct sdhci_ops sdhci_dove_ops = {
+ .read_w = sdhci_dove_readw,
+ .read_l = sdhci_dove_readl,
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_dove_pdata = {
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-esdhc.h linux-linaro-stable-mx6/drivers/mmc/host/sdhci-esdhc.h
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-esdhc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-esdhc.h 2014-05-15 20:33:58.242015624 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Freescale eSDHC controller driver generics for OF and pltfm.
+ *
+- * Copyright (c) 2007 Freescale Semiconductor, Inc.
++ * Copyright 2007-2013 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ * Copyright (c) 2010 Pengutronix e.K.
+ * Author: Wolfram Sang <w.sang@pengutronix.de>
+@@ -20,12 +20,11 @@
+
+ #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
+ SDHCI_QUIRK_NO_BUSY_IRQ | \
+- SDHCI_QUIRK_NONSTANDARD_CLOCK | \
+ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
+- SDHCI_QUIRK_PIO_NEEDS_DELAY | \
+- SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
++ SDHCI_QUIRK_PIO_NEEDS_DELAY)
+
+ #define ESDHC_SYSTEM_CONTROL 0x2c
++#define ESDHC_SYS_CTRL_RSTA (1 << 24)
+ #define ESDHC_CLOCK_MASK 0x0000fff0
+ #define ESDHC_PREDIV_SHIFT 8
+ #define ESDHC_DIVIDER_SHIFT 4
+@@ -36,6 +35,13 @@
+ /* pltfm-specific */
+ #define ESDHC_HOST_CONTROL_LE 0x20
+
++/*
++ * P2020 interpretation of the SDHCI_HOST_CONTROL register
++ */
++#define ESDHC_CTRL_4BITBUS (0x1 << 1)
++#define ESDHC_CTRL_8BITBUS (0x2 << 1)
++#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
++
+ /* OF-specific */
+ #define ESDHC_DMA_SYSCTL 0x40c
+ #define ESDHC_DMA_SNOOP 0x00000040
+@@ -48,8 +54,10 @@
+ int div = 1;
+ u32 temp;
+
++ host->mmc->actual_clock = 0;
++
+ if (clock == 0)
+- goto out;
++ return;
+
+ temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
+ temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
+@@ -74,8 +82,6 @@
+ | (pre_div << ESDHC_PREDIV_SHIFT));
+ sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
+ mdelay(1);
+-out:
+- host->clock = clock;
+ }
+
+ #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-esdhc-imx.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-esdhc-imx.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-esdhc-imx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-esdhc-imx.c 2014-05-15 20:33:58.242015624 +0200
+@@ -11,6 +11,7 @@
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
++#include <linux/busfreq-imx6.h>
+ #include <linux/io.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
+@@ -27,6 +28,7 @@
+ #include <linux/of_gpio.h>
+ #include <linux/pinctrl/consumer.h>
+ #include <linux/platform_data/mmc-esdhc-imx.h>
++#include <linux/pm_runtime.h>
+ #include "sdhci-pltfm.h"
+ #include "sdhci-esdhc.h"
+
+@@ -34,11 +36,41 @@
+ /* VENDOR SPEC register */
+ #define ESDHC_VENDOR_SPEC 0xc0
+ #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
++#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
++#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
+ #define ESDHC_WTMK_LVL 0x44
+ #define ESDHC_MIX_CTRL 0x48
++#define ESDHC_MIX_CTRL_DDREN (1 << 3)
+ #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
++#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
++#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
++#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
+ /* Bits 3 and 6 are not SDHCI standard definitions */
+ #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
++/* Tuning bits */
++#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
++
++/* dll control register */
++#define ESDHC_DLL_CTRL 0x60
++#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
++#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
++
++/* tune control register */
++#define ESDHC_TUNE_CTRL_STATUS 0x68
++#define ESDHC_TUNE_CTRL_STEP 1
++#define ESDHC_TUNE_CTRL_MIN 0
++#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
++
++#define ESDHC_TUNING_CTRL 0xcc
++#define ESDHC_STD_TUNING_EN (1 << 24)
++/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
++#define ESDHC_TUNING_START_TAP 0x1
++
++#define ESDHC_TUNING_BLOCK_PATTERN_LEN 64
++
++/* pinctrl state */
++#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
++#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
+
+ /*
+ * Our interpretation of the SDHCI_HOST_CONTROL register
+@@ -66,21 +98,62 @@
+ * As a result, the TC flag is not asserted and SW received timeout
+ * exeception. Bit1 of Vendor Spec registor is used to fix it.
+ */
+-#define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1)
++#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
++/*
++ * The flag enables the workaround for ESDHC errata ENGcm07207 which
++ * affects i.MX25 and i.MX35.
++ */
++#define ESDHC_FLAG_ENGCM07207 BIT(2)
++/*
++ * The flag tells that the ESDHC controller is an USDHC block that is
++ * integrated on the i.MX6 series.
++ */
++#define ESDHC_FLAG_USDHC BIT(3)
++/* The IP supports manual tuning process */
++#define ESDHC_FLAG_MAN_TUNING BIT(4)
++/* The IP supports standard tuning process */
++#define ESDHC_FLAG_STD_TUNING BIT(5)
++/* The IP has SDHCI_CAPABILITIES_1 register */
++#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
++/* The IP has errata ERR004536 */
++#define ESDHC_FLAG_ERR004536 BIT(7)
++
++struct esdhc_soc_data {
++ u32 flags;
++};
++
++static struct esdhc_soc_data esdhc_imx25_data = {
++ .flags = ESDHC_FLAG_ENGCM07207,
++};
++
++static struct esdhc_soc_data esdhc_imx35_data = {
++ .flags = ESDHC_FLAG_ENGCM07207,
++};
++
++static struct esdhc_soc_data esdhc_imx51_data = {
++ .flags = 0,
++};
++
++static struct esdhc_soc_data esdhc_imx53_data = {
++ .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
++};
+
+-enum imx_esdhc_type {
+- IMX25_ESDHC,
+- IMX35_ESDHC,
+- IMX51_ESDHC,
+- IMX53_ESDHC,
+- IMX6Q_USDHC,
++static struct esdhc_soc_data usdhc_imx6q_data = {
++ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
++};
++
++static struct esdhc_soc_data usdhc_imx6sl_data = {
++ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
++ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536,
+ };
+
+ struct pltfm_imx_data {
+- int flags;
+ u32 scratchpad;
+- enum imx_esdhc_type devtype;
+ struct pinctrl *pinctrl;
++ struct pinctrl_state *pins_default;
++ struct pinctrl_state *pins_100mhz;
++ struct pinctrl_state *pins_200mhz;
++ const struct esdhc_soc_data *socdata;
+ struct esdhc_platform_data boarddata;
+ struct clk *clk_ipg;
+ struct clk *clk_ahb;
+@@ -90,25 +163,19 @@
+ MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
+ WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
+ } multiblock_status;
+-
++ u32 is_ddr;
+ };
+
+ static struct platform_device_id imx_esdhc_devtype[] = {
+ {
+ .name = "sdhci-esdhc-imx25",
+- .driver_data = IMX25_ESDHC,
++ .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
+ }, {
+ .name = "sdhci-esdhc-imx35",
+- .driver_data = IMX35_ESDHC,
++ .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
+ }, {
+ .name = "sdhci-esdhc-imx51",
+- .driver_data = IMX51_ESDHC,
+- }, {
+- .name = "sdhci-esdhc-imx53",
+- .driver_data = IMX53_ESDHC,
+- }, {
+- .name = "sdhci-usdhc-imx6q",
+- .driver_data = IMX6Q_USDHC,
++ .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
+ }, {
+ /* sentinel */
+ }
+@@ -116,38 +183,34 @@
+ MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
+
+ static const struct of_device_id imx_esdhc_dt_ids[] = {
+- { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
+- { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
+- { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
+- { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
+- { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
++ { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
++ { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
++ { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
++ { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
++ { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
++ { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
+
+ static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
+ {
+- return data->devtype == IMX25_ESDHC;
+-}
+-
+-static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
+-{
+- return data->devtype == IMX35_ESDHC;
++ return data->socdata == &esdhc_imx25_data;
+ }
+
+-static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
++static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
+ {
+- return data->devtype == IMX51_ESDHC;
++ return data->socdata == &esdhc_imx53_data;
+ }
+
+-static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
++static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
+ {
+- return data->devtype == IMX53_ESDHC;
++ return data->socdata == &usdhc_imx6q_data;
+ }
+
+-static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
++static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
+ {
+- return data->devtype == IMX6Q_USDHC;
++ return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
+ }
+
+ static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
+@@ -164,7 +227,21 @@
+ struct pltfm_imx_data *imx_data = pltfm_host->priv;
+ u32 val = readl(host->ioaddr + reg);
+
++ if (unlikely(reg == SDHCI_PRESENT_STATE)) {
++ u32 fsl_prss = val;
++ /* save the least 20 bits */
++ val = fsl_prss & 0x000FFFFF;
++ /* move dat[0-3] bits */
++ val |= (fsl_prss & 0x0F000000) >> 4;
++ /* move cmd line bit */
++ val |= (fsl_prss & 0x00800000) << 1;
++ }
++
+ if (unlikely(reg == SDHCI_CAPABILITIES)) {
++ /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
++ if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
++ val &= 0xffff0000;
++
+ /* In FSL esdhc IC module, only bit20 is used to indicate the
+ * ADMA2 capability of esdhc, but this bit is messed up on
+ * some SOCs (e.g. on MX25, MX35 this bit is set, but they
+@@ -178,6 +255,25 @@
+ }
+ }
+
++ if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
++ if (esdhc_is_usdhc(imx_data)) {
++ if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
++ val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
++ else
++ /* imx6q/dl does not have cap_1 register, fake one */
++ val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
++ | SDHCI_SUPPORT_SDR50
++ | SDHCI_USE_SDR50_TUNING;
++ }
++ }
++
++ if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
++ val = 0;
++ val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
++ val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
++ val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
++ }
++
+ if (unlikely(reg == SDHCI_INT_STATUS)) {
+ if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
+ val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
+@@ -224,7 +320,7 @@
+ }
+ }
+
+- if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
++ if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
+ && (reg == SDHCI_INT_STATUS)
+ && (val & SDHCI_INT_DATA_END))) {
+ u32 v;
+@@ -256,10 +352,12 @@
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_imx_data *imx_data = pltfm_host->priv;
++ u16 ret = 0;
++ u32 val;
+
+ if (unlikely(reg == SDHCI_HOST_VERSION)) {
+ reg ^= 2;
+- if (is_imx6q_usdhc(imx_data)) {
++ if (esdhc_is_usdhc(imx_data)) {
+ /*
+ * The usdhc register returns a wrong host version.
+ * Correct it here.
+@@ -268,6 +366,45 @@
+ }
+ }
+
++ if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
++ val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
++ if (val & ESDHC_VENDOR_SPEC_VSELECT)
++ ret |= SDHCI_CTRL_VDD_180;
++
++ if (esdhc_is_usdhc(imx_data)) {
++ if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
++ val = readl(host->ioaddr + ESDHC_MIX_CTRL);
++ else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
++ /* the std tuning bits is in ACMD12_ERR for imx6sl */
++ val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
++ }
++
++ if (val & ESDHC_MIX_CTRL_EXE_TUNE)
++ ret |= SDHCI_CTRL_EXEC_TUNING;
++ if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
++ ret |= SDHCI_CTRL_TUNED_CLK;
++
++ ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
++
++ return ret;
++ }
++
++ if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
++ if (esdhc_is_usdhc(imx_data)) {
++ u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
++ ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
++ /* Swap AC23 bit */
++ if (m & ESDHC_MIX_CTRL_AC23EN) {
++ ret &= ~ESDHC_MIX_CTRL_AC23EN;
++ ret |= SDHCI_TRNS_AUTO_CMD23;
++ }
++ } else {
++ ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
++ }
++
++ return ret;
++ }
++
+ return readw(host->ioaddr + reg);
+ }
+
+@@ -275,10 +412,54 @@
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_imx_data *imx_data = pltfm_host->priv;
++ u32 new_val = 0;
+
+ switch (reg) {
++ case SDHCI_CLOCK_CONTROL:
++ new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
++ if (val & SDHCI_CLOCK_CARD_EN)
++ new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
++ else
++ new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
++ writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
++ return;
++ case SDHCI_HOST_CONTROL2:
++ new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
++ if (val & SDHCI_CTRL_VDD_180)
++ new_val |= ESDHC_VENDOR_SPEC_VSELECT;
++ else
++ new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
++ writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
++ if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
++ new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
++ if (val & SDHCI_CTRL_TUNED_CLK)
++ new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
++ else
++ new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
++ writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
++ } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
++ u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
++ u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
++ if (val & SDHCI_CTRL_TUNED_CLK) {
++ v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
++ } else {
++ v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
++ m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
++ }
++
++ if (val & SDHCI_CTRL_EXEC_TUNING) {
++ v |= ESDHC_MIX_CTRL_EXE_TUNE;
++ m |= ESDHC_MIX_CTRL_FBCLK_SEL;
++ } else {
++ v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
++ }
++
++ writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
++ writel(m, host->ioaddr + ESDHC_MIX_CTRL);
++ }
++ return;
+ case SDHCI_TRANSFER_MODE:
+- if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
++ if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
+ && (host->cmd->opcode == SD_IO_RW_EXTENDED)
+ && (host->cmd->data->blocks > 1)
+ && (host->cmd->data->flags & MMC_DATA_READ)) {
+@@ -288,7 +469,7 @@
+ writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
+ }
+
+- if (is_imx6q_usdhc(imx_data)) {
++ if (esdhc_is_usdhc(imx_data)) {
+ u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
+ /* Swap AC23 bit */
+ if (val & SDHCI_TRNS_AUTO_CMD23) {
+@@ -310,10 +491,10 @@
+ val |= SDHCI_CMD_ABORTCMD;
+
+ if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
+- (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
++ (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
+ imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
+
+- if (is_imx6q_usdhc(imx_data))
++ if (esdhc_is_usdhc(imx_data))
+ writel(val << 16,
+ host->ioaddr + SDHCI_TRANSFER_MODE);
+ else
+@@ -379,8 +560,13 @@
+ * The reset on usdhc fails to clear MIX_CTRL register.
+ * Do it manually here.
+ */
+- if (is_imx6q_usdhc(imx_data))
+- writel(0, host->ioaddr + ESDHC_MIX_CTRL);
++ if (esdhc_is_usdhc(imx_data)) {
++ /* the tuning bits should be kept during reset */
++ new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
++ writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
++ host->ioaddr + ESDHC_MIX_CTRL);
++ imx_data->is_ddr = 0;
++ }
+ }
+ }
+
+@@ -391,6 +577,65 @@
+ return clk_get_rate(pltfm_host->clk) / 256 / 16;
+ }
+
++static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
++ unsigned int clock)
++{
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++ struct pltfm_imx_data *imx_data = pltfm_host->priv;
++ int pre_div = 2;
++ int div = 1;
++ u32 temp, val;
++
++ if (clock == 0) {
++ host->mmc->actual_clock = 0;
++
++ if (esdhc_is_usdhc(imx_data)) {
++ val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
++ writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
++ host->ioaddr + ESDHC_VENDOR_SPEC);
++ }
++ return;
++ }
++
++ if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
++ pre_div = 1;
++
++ temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
++ temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
++ | ESDHC_CLOCK_MASK);
++ sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
++
++ while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
++ pre_div *= 2;
++
++ while (host->max_clk / pre_div / div > clock && div < 16)
++ div++;
++
++ host->mmc->actual_clock = host->max_clk / pre_div / div;
++ dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
++ clock, host->mmc->actual_clock);
++
++ if (imx_data->is_ddr)
++ pre_div >>= 2;
++ else
++ pre_div >>= 1;
++ div--;
++
++ temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
++ temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
++ | (div << ESDHC_DIVIDER_SHIFT)
++ | (pre_div << ESDHC_PREDIV_SHIFT));
++ sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
++
++ if (esdhc_is_usdhc(imx_data)) {
++ val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
++ writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
++ host->ioaddr + ESDHC_VENDOR_SPEC);
++ }
++
++ mdelay(1);
++}
++
+ static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+@@ -410,7 +655,7 @@
+ return -ENOSYS;
+ }
+
+-static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
++static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u32 ctrl;
+
+@@ -428,21 +673,258 @@
+
+ esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
+ SDHCI_HOST_CONTROL);
++}
++
++static void esdhc_full_reset(struct sdhci_host *host, u32 rst_bits)
++{
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++ struct pltfm_imx_data *imx_data = pltfm_host->priv;
++ u32 timeout;
++ u32 reg;
++
++ reg = readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
++ reg |= rst_bits;
++ writel(reg, host->ioaddr + ESDHC_SYSTEM_CONTROL);
++
++ /* Wait for max 100ms */
++ timeout = 100;
++
++ /* hw clears the bit when it's done */
++ while (readl(host->ioaddr + ESDHC_SYSTEM_CONTROL) & rst_bits) {
++ if (timeout == 0) {
++ dev_err(mmc_dev(host->mmc),
++ "Reset never completes!\n");
++ return;
++ }
++ timeout--;
++ mdelay(1);
++ }
++
++ /*
++ * The RSTA, reset all, on usdhc will not clear following regs:
++ * > SDHCI_MIX_CTRL
++ * > SDHCI_TUNE_CTRL_STATUS
++ *
++ * Do it manually here.
++ */
++ if ((rst_bits & ESDHC_SYS_CTRL_RSTA) && is_imx6q_usdhc(imx_data)) {
++ writel(0, host->ioaddr + ESDHC_MIX_CTRL);
++ writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
++ /* FIXME: delay for clear tuning status or some cards may not work */
++ mdelay(1);
++ }
++}
++
++static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
++{
++ u32 reg;
++
++ /* reset controller before tuning or it may fail on some cards */
++ esdhc_full_reset(host, ESDHC_SYS_CTRL_RSTA);
++
++ reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
++ reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
++ ESDHC_MIX_CTRL_FBCLK_SEL;
++ writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
++ writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
++ dev_dbg(mmc_dev(host->mmc),
++ "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
++ val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
++}
++
++static void esdhc_request_done(struct mmc_request *mrq)
++{
++ complete(&mrq->completion);
++}
++
++static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode,
++ struct scatterlist *sg)
++{
++ struct mmc_command cmd = {0};
++ struct mmc_request mrq = {0};
++ struct mmc_data data = {0};
++
++ cmd.opcode = opcode;
++ cmd.arg = 0;
++ cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
++
++ data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
++ data.blocks = 1;
++ data.flags = MMC_DATA_READ;
++ data.sg = sg;
++ data.sg_len = 1;
++
++ mrq.cmd = &cmd;
++ mrq.cmd->mrq = &mrq;
++ mrq.data = &data;
++ mrq.data->mrq = &mrq;
++ mrq.cmd->data = mrq.data;
++
++ mrq.done = esdhc_request_done;
++ init_completion(&(mrq.completion));
++
++ spin_lock_irq(&host->lock);
++ host->mrq = &mrq;
++
++ sdhci_send_command(host, mrq.cmd);
++
++ spin_unlock_irq(&host->lock);
++
++ wait_for_completion(&mrq.completion);
++
++ if (cmd.error)
++ return cmd.error;
++ if (data.error)
++ return data.error;
+
+ return 0;
+ }
+
+-static const struct sdhci_ops sdhci_esdhc_ops = {
++static void esdhc_post_tuning(struct sdhci_host *host)
++{
++ u32 reg;
++
++ reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
++ reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
++ writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
++}
++
++static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
++{
++ struct scatterlist sg;
++ char *tuning_pattern;
++ int min, max, avg, ret;
++
++ tuning_pattern = kmalloc(ESDHC_TUNING_BLOCK_PATTERN_LEN, GFP_KERNEL);
++ if (!tuning_pattern)
++ return -ENOMEM;
++
++ sg_init_one(&sg, tuning_pattern, ESDHC_TUNING_BLOCK_PATTERN_LEN);
++
++ /* find the mininum delay first which can pass tuning */
++ min = ESDHC_TUNE_CTRL_MIN;
++ while (min < ESDHC_TUNE_CTRL_MAX) {
++ esdhc_prepare_tuning(host, min);
++ if (!esdhc_send_tuning_cmd(host, opcode, &sg))
++ break;
++ min += ESDHC_TUNE_CTRL_STEP;
++ }
++
++ /* find the maxinum delay which can not pass tuning */
++ max = min + ESDHC_TUNE_CTRL_STEP;
++ while (max < ESDHC_TUNE_CTRL_MAX) {
++ esdhc_prepare_tuning(host, max);
++ if (esdhc_send_tuning_cmd(host, opcode, &sg)) {
++ max -= ESDHC_TUNE_CTRL_STEP;
++ break;
++ }
++ max += ESDHC_TUNE_CTRL_STEP;
++ }
++
++ /* use average delay to get the best timing */
++ avg = (min + max) / 2;
++ esdhc_prepare_tuning(host, avg);
++ ret = esdhc_send_tuning_cmd(host, opcode, &sg);
++ esdhc_post_tuning(host);
++
++ kfree(tuning_pattern);
++
++ dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
++ ret ? "failed" : "passed", avg, ret);
++
++ return ret;
++}
++
++static int esdhc_change_pinstate(struct sdhci_host *host,
++ unsigned int uhs)
++{
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++ struct pltfm_imx_data *imx_data = pltfm_host->priv;
++ struct pinctrl_state *pinctrl;
++
++ dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
++
++ if (IS_ERR(imx_data->pinctrl) ||
++ IS_ERR(imx_data->pins_default) ||
++ IS_ERR(imx_data->pins_100mhz) ||
++ IS_ERR(imx_data->pins_200mhz))
++ return -EINVAL;
++
++ switch (uhs) {
++ case MMC_TIMING_UHS_SDR50:
++ pinctrl = imx_data->pins_100mhz;
++ break;
++ case MMC_TIMING_UHS_SDR104:
++ case MMC_TIMING_MMC_HS200:
++ pinctrl = imx_data->pins_200mhz;
++ break;
++ default:
++ /* back to default state for other legacy timing */
++ pinctrl = imx_data->pins_default;
++ }
++
++ return pinctrl_select_state(imx_data->pinctrl, pinctrl);
++}
++
++static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
++{
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++ struct pltfm_imx_data *imx_data = pltfm_host->priv;
++ struct esdhc_platform_data *boarddata = &imx_data->boarddata;
++
++ switch (timing) {
++ case MMC_TIMING_UHS_SDR12:
++ case MMC_TIMING_UHS_SDR25:
++ case MMC_TIMING_UHS_SDR50:
++ case MMC_TIMING_UHS_SDR104:
++ case MMC_TIMING_MMC_HS200:
++ break;
++ case MMC_TIMING_UHS_DDR50:
++ writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
++ ESDHC_MIX_CTRL_DDREN,
++ host->ioaddr + ESDHC_MIX_CTRL);
++ imx_data->is_ddr = 1;
++ if (boarddata->delay_line) {
++ u32 v;
++ v = boarddata->delay_line <<
++ ESDHC_DLL_OVERRIDE_VAL_SHIFT |
++ (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
++ if (is_imx53_esdhc(imx_data))
++ v <<= 1;
++ writel(v, host->ioaddr + ESDHC_DLL_CTRL);
++ }
++ break;
++ }
++
++ return esdhc_change_pinstate(host, timing);
++}
++
++static unsigned int esdhc_get_max_timeout_counter(struct sdhci_host *host)
++{
++ return 1 << 28;
++}
++
++static void esdhc_reset(struct sdhci_host *host, u8 mask)
++{
++ sdhci_reset(host, mask);
++
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
++}
++
++static struct sdhci_ops sdhci_esdhc_ops = {
+ .read_l = esdhc_readl_le,
+ .read_w = esdhc_readw_le,
+ .write_l = esdhc_writel_le,
+ .write_w = esdhc_writew_le,
+ .write_b = esdhc_writeb_le,
+- .set_clock = esdhc_set_clock,
++ .set_clock = esdhc_pltfm_set_clock,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .get_min_clock = esdhc_pltfm_get_min_clock,
+ .get_ro = esdhc_pltfm_get_ro,
+- .platform_bus_width = esdhc_pltfm_bus_width,
++ .set_bus_width = esdhc_pltfm_set_bus_width,
++ .set_uhs_signaling = esdhc_set_uhs_signaling,
++ .reset = esdhc_reset,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
+@@ -482,6 +964,14 @@
+
+ of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
+
++ if (of_find_property(np, "no-1-8-v", NULL))
++ boarddata->support_vsel = false;
++ else
++ boarddata->support_vsel = true;
++
++ if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
++ boarddata->delay_line = 0;
++
+ return 0;
+ }
+ #else
+@@ -515,9 +1005,8 @@
+ goto free_sdhci;
+ }
+
+- if (of_id)
+- pdev->id_entry = of_id->data;
+- imx_data->devtype = pdev->id_entry->driver_data;
++ imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
++ pdev->id_entry->driver_data;
+ pltfm_host->priv = imx_data;
+
+ imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+@@ -540,32 +1029,63 @@
+
+ pltfm_host->clk = imx_data->clk_per;
+
++ request_bus_freq(BUS_FREQ_HIGH);
++
+ clk_prepare_enable(imx_data->clk_per);
+ clk_prepare_enable(imx_data->clk_ipg);
+ clk_prepare_enable(imx_data->clk_ahb);
+
+- imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR(imx_data->pinctrl)) {
+ err = PTR_ERR(imx_data->pinctrl);
+ goto disable_clk;
+ }
+
++ imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
++ PINCTRL_STATE_DEFAULT);
++ if (IS_ERR(imx_data->pins_default)) {
++ err = PTR_ERR(imx_data->pins_default);
++ dev_err(mmc_dev(host->mmc), "could not get default state\n");
++ goto disable_clk;
++ }
++
+ host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+
+- if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
++ if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
+ /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
+ host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
+ | SDHCI_QUIRK_BROKEN_ADMA;
+
+- if (is_imx53_esdhc(imx_data))
+- imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
+-
+ /*
+ * The imx6q ROM code will change the default watermark level setting
+ * to something insane. Change it back here.
+ */
+- if (is_imx6q_usdhc(imx_data))
++ if (esdhc_is_usdhc(imx_data)) {
+ writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
++ host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
++ SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER;
++ host->mmc->caps |= MMC_CAP_1_8V_DDR;
++
++ /*
++ * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
++ * TO1.1, it's harmless for MX6SL
++ */
++ writel(readl(host->ioaddr + 0x6c) | BIT(7), host->ioaddr + 0x6c);
++ sdhci_esdhc_ops.get_max_timeout_counter =
++ esdhc_get_max_timeout_counter;
++ }
++
++ if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
++ sdhci_esdhc_ops.platform_execute_tuning =
++ esdhc_executing_tuning;
++
++ if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
++ writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
++ ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
++ host->ioaddr + ESDHC_TUNING_CTRL);
++
++ if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
++ host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
+ boarddata = &imx_data->boarddata;
+ if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
+@@ -592,7 +1112,7 @@
+ /* card_detect */
+ switch (boarddata->cd_type) {
+ case ESDHC_CD_GPIO:
+- err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio);
++ err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
+ if (err) {
+ dev_err(mmc_dev(host->mmc),
+ "failed to request card-detect gpio!\n");
+@@ -606,7 +1126,7 @@
+ break;
+
+ case ESDHC_CD_PERMANENT:
+- host->mmc->caps = MMC_CAP_NONREMOVABLE;
++ host->mmc->caps |= MMC_CAP_NONREMOVABLE;
+ break;
+
+ case ESDHC_CD_NONE:
+@@ -626,16 +1146,40 @@
+ break;
+ }
+
++ /* sdr50 and sdr104 needs work on 1.8v signal voltage */
++ if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
++ imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
++ ESDHC_PINCTRL_STATE_100MHZ);
++ imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
++ ESDHC_PINCTRL_STATE_200MHZ);
++ if (IS_ERR(imx_data->pins_100mhz) ||
++ IS_ERR(imx_data->pins_200mhz)) {
++ dev_warn(mmc_dev(host->mmc),
++ "could not get ultra high speed state, work on normal mode\n");
++ /* fall back to not support uhs by specify no 1.8v quirk */
++ host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
++ }
++ } else {
++ host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
++ }
++
+ err = sdhci_add_host(host);
+ if (err)
+ goto disable_clk;
+
++ pm_runtime_set_active(&pdev->dev);
++ pm_runtime_enable(&pdev->dev);
++ pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
++ pm_runtime_use_autosuspend(&pdev->dev);
++ pm_suspend_ignore_children(&pdev->dev, 1);
++
+ return 0;
+
+ disable_clk:
+ clk_disable_unprepare(imx_data->clk_per);
+ clk_disable_unprepare(imx_data->clk_ipg);
+ clk_disable_unprepare(imx_data->clk_ahb);
++ release_bus_freq(BUS_FREQ_HIGH);
+ free_sdhci:
+ sdhci_pltfm_free(pdev);
+ return err;
+@@ -644,27 +1188,69 @@
+ static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
+ {
+ struct sdhci_host *host = platform_get_drvdata(pdev);
+- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+- struct pltfm_imx_data *imx_data = pltfm_host->priv;
+ int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
+
+ sdhci_remove_host(host, dead);
+
+- clk_disable_unprepare(imx_data->clk_per);
+- clk_disable_unprepare(imx_data->clk_ipg);
+- clk_disable_unprepare(imx_data->clk_ahb);
++ pm_runtime_dont_use_autosuspend(&pdev->dev);
++ pm_runtime_disable(&pdev->dev);
+
+ sdhci_pltfm_free(pdev);
+
+ return 0;
+ }
+
++#ifdef CONFIG_PM_RUNTIME
++static int sdhci_esdhc_runtime_suspend(struct device *dev)
++{
++ struct sdhci_host *host = dev_get_drvdata(dev);
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++ struct pltfm_imx_data *imx_data = pltfm_host->priv;
++ int ret;
++
++ ret = sdhci_runtime_suspend_host(host);
++
++ if (!sdhci_sdio_irq_enabled(host)) {
++ clk_disable_unprepare(imx_data->clk_per);
++ clk_disable_unprepare(imx_data->clk_ipg);
++ }
++ clk_disable_unprepare(imx_data->clk_ahb);
++
++ release_bus_freq(BUS_FREQ_HIGH);
++
++ return ret;
++}
++
++static int sdhci_esdhc_runtime_resume(struct device *dev)
++{
++ struct sdhci_host *host = dev_get_drvdata(dev);
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++ struct pltfm_imx_data *imx_data = pltfm_host->priv;
++
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ if (!sdhci_sdio_irq_enabled(host)) {
++ clk_prepare_enable(imx_data->clk_per);
++ clk_prepare_enable(imx_data->clk_ipg);
++ }
++ clk_prepare_enable(imx_data->clk_ahb);
++
++ return sdhci_runtime_resume_host(host);
++}
++#endif
++
++static const struct dev_pm_ops sdhci_esdhc_pmops = {
++ SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_pltfm_resume)
++ SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
++ sdhci_esdhc_runtime_resume, NULL)
++};
++
+ static struct platform_driver sdhci_esdhc_imx_driver = {
+ .driver = {
+ .name = "sdhci-esdhc-imx",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_esdhc_dt_ids,
+- .pm = SDHCI_PLTFM_PMOPS,
++ .pm = &sdhci_esdhc_pmops,
+ },
+ .id_table = imx_esdhc_devtype,
+ .probe = sdhci_esdhc_imx_probe,
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci.h linux-linaro-stable-mx6/drivers/mmc/host/sdhci.h
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci.h 2014-05-15 20:33:58.246015652 +0200
+@@ -281,17 +281,15 @@
+ unsigned int (*get_max_clock)(struct sdhci_host *host);
+ unsigned int (*get_min_clock)(struct sdhci_host *host);
+ unsigned int (*get_timeout_clock)(struct sdhci_host *host);
+- int (*platform_bus_width)(struct sdhci_host *host,
+- int width);
++ unsigned int (*get_max_timeout_counter)(struct sdhci_host *host);
++ void (*set_bus_width)(struct sdhci_host *host, int width);
+ void (*platform_send_init_74_clocks)(struct sdhci_host *host,
+ u8 power_mode);
+ unsigned int (*get_ro)(struct sdhci_host *host);
+- void (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
+- void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
++ void (*reset)(struct sdhci_host *host, u8 mask);
++ int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
+ int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
+ void (*hw_reset)(struct sdhci_host *host);
+- void (*platform_suspend)(struct sdhci_host *host);
+- void (*platform_resume)(struct sdhci_host *host);
+ void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
+ void (*platform_init)(struct sdhci_host *host);
+ };
+@@ -392,6 +390,18 @@
+ extern void sdhci_card_detect(struct sdhci_host *host);
+ extern int sdhci_add_host(struct sdhci_host *host);
+ extern void sdhci_remove_host(struct sdhci_host *host, int dead);
++extern void sdhci_send_command(struct sdhci_host *host,
++ struct mmc_command *cmd);
++
++static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
++{
++ return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
++}
++
++void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
++void sdhci_set_bus_width(struct sdhci_host *host, int width);
++void sdhci_reset(struct sdhci_host *host, u8 mask);
++void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
+
+ #ifdef CONFIG_PM
+ extern int sdhci_suspend_host(struct sdhci_host *host);
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-of-esdhc.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-of-esdhc.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-of-esdhc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-of-esdhc.c 2014-05-15 20:33:58.242015624 +0200
+@@ -13,6 +13,7 @@
+ * your option) any later version.
+ */
+
++#include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
+ #include <linux/delay.h>
+@@ -203,20 +204,6 @@
+ esdhc_set_clock(host, clock);
+ }
+
+-#ifdef CONFIG_PM
+-static u32 esdhc_proctl;
+-static void esdhc_of_suspend(struct sdhci_host *host)
+-{
+- esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
+-}
+-
+-static void esdhc_of_resume(struct sdhci_host *host)
+-{
+- esdhc_of_enable_dma(host);
+- sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
+-}
+-#endif
+-
+ static void esdhc_of_platform_init(struct sdhci_host *host)
+ {
+ u32 vvn;
+@@ -230,6 +217,28 @@
+ host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
+ }
+
++static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
++{
++ u32 ctrl;
++
++ switch (width) {
++ case MMC_BUS_WIDTH_8:
++ ctrl = ESDHC_CTRL_8BITBUS;
++ break;
++
++ case MMC_BUS_WIDTH_4:
++ ctrl = ESDHC_CTRL_4BITBUS;
++ break;
++
++ default:
++ ctrl = 0;
++ break;
++ }
++
++ clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL,
++ ESDHC_CTRL_BUSWIDTH_MASK, ctrl);
++}
++
+ static const struct sdhci_ops sdhci_esdhc_ops = {
+ .read_l = esdhc_readl,
+ .read_w = esdhc_readw,
+@@ -242,13 +251,47 @@
+ .get_max_clock = esdhc_of_get_max_clock,
+ .get_min_clock = esdhc_of_get_min_clock,
+ .platform_init = esdhc_of_platform_init,
+-#ifdef CONFIG_PM
+- .platform_suspend = esdhc_of_suspend,
+- .platform_resume = esdhc_of_resume,
+-#endif
+ .adma_workaround = esdhci_of_adma_workaround,
++ .set_bus_width = esdhc_pltfm_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
++#ifdef CONFIG_PM
++
++static u32 esdhc_proctl;
++static int esdhc_of_suspend(struct device *dev)
++{
++ struct sdhci_host *host = dev_get_drvdata(dev);
++
++ esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
++
++ return sdhci_suspend_host(host);
++}
++
++static void esdhc_of_resume(device *dev)
++{
++ struct sdhci_host *host = dev_get_drvdata(dev);
++ int ret = sdhci_resume_host(host);
++
++ if (ret == 0) {
++ /* Isn't this already done by sdhci_resume_host() ? --rmk */
++ esdhc_of_enable_dma(host);
++ sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
++ }
++
++ return ret;
++}
++
++static const struct dev_pm_ops esdhc_pmops = {
++ .suspend = esdhci_of_suspend,
++ .resume = esdhci_of_resume,
++};
++#define ESDHC_PMOPS (&esdhc_pmops)
++#else
++#define ESDHC_PMOPS NULL
++#endif
++
+ static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
+ /*
+ * card detection could be handled via GPIO
+@@ -262,7 +305,23 @@
+
+ static int sdhci_esdhc_probe(struct platform_device *pdev)
+ {
+- return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
++ struct sdhci_host *host;
++ int ret;
++
++ host = sdhci_pltfm_init(pdev, &sdhci_esdhc_pdata);
++ if (IS_ERR(host))
++ return PTR_ERR(host);
++
++ sdhci_get_of_property(pdev);
++
++ /* call to generic mmc_of_parse to support additional capabilities */
++ mmc_of_parse(host->mmc);
++
++ ret = sdhci_add_host(host);
++ if (ret)
++ sdhci_pltfm_free(pdev);
++
++ return ret;
+ }
+
+ static int sdhci_esdhc_remove(struct platform_device *pdev)
+@@ -283,7 +342,7 @@
+ .name = "sdhci-esdhc",
+ .owner = THIS_MODULE,
+ .of_match_table = sdhci_esdhc_of_match,
+- .pm = SDHCI_PLTFM_PMOPS,
++ .pm = ESDHC_PMOPS,
+ },
+ .probe = sdhci_esdhc_probe,
+ .remove = sdhci_esdhc_remove,
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-of-hlwd.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-of-hlwd.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-of-hlwd.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-of-hlwd.c 2014-05-15 20:33:58.242015624 +0200
+@@ -58,6 +58,10 @@
+ .write_l = sdhci_hlwd_writel,
+ .write_w = sdhci_hlwd_writew,
+ .write_b = sdhci_hlwd_writeb,
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_hlwd_pdata = {
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-pci.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pci.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-pci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pci.c 2014-05-15 20:33:58.242015624 +0200
+@@ -989,7 +989,7 @@
+ return 0;
+ }
+
+-static int sdhci_pci_bus_width(struct sdhci_host *host, int width)
++static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u8 ctrl;
+
+@@ -1010,8 +1010,6 @@
+ }
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+-
+- return 0;
+ }
+
+ static void sdhci_pci_hw_reset(struct sdhci_host *host)
+@@ -1030,8 +1028,11 @@
+ }
+
+ static const struct sdhci_ops sdhci_pci_ops = {
++ .set_clock = sdhci_set_clock,
+ .enable_dma = sdhci_pci_enable_dma,
+- .platform_bus_width = sdhci_pci_bus_width,
++ .set_bus_width = sdhci_pci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ .hw_reset = sdhci_pci_hw_reset,
+ };
+
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-pltfm.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pltfm.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-pltfm.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pltfm.c 2014-05-15 20:33:58.242015624 +0200
+@@ -45,6 +45,10 @@
+ EXPORT_SYMBOL_GPL(sdhci_pltfm_clk_get_max_clock);
+
+ static const struct sdhci_ops sdhci_pltfm_ops = {
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ #ifdef CONFIG_OF
+@@ -234,19 +238,21 @@
+ EXPORT_SYMBOL_GPL(sdhci_pltfm_unregister);
+
+ #ifdef CONFIG_PM
+-static int sdhci_pltfm_suspend(struct device *dev)
++int sdhci_pltfm_suspend(struct device *dev)
+ {
+ struct sdhci_host *host = dev_get_drvdata(dev);
+
+ return sdhci_suspend_host(host);
+ }
++EXPORT_SYMBOL_GPL(sdhci_pltfm_suspend);
+
+-static int sdhci_pltfm_resume(struct device *dev)
++int sdhci_pltfm_resume(struct device *dev)
+ {
+ struct sdhci_host *host = dev_get_drvdata(dev);
+
+ return sdhci_resume_host(host);
+ }
++EXPORT_SYMBOL_GPL(sdhci_pltfm_resume);
+
+ const struct dev_pm_ops sdhci_pltfm_pmops = {
+ .suspend = sdhci_pltfm_suspend,
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-pltfm.h linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pltfm.h
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-pltfm.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pltfm.h 2014-05-15 20:33:58.242015624 +0200
+@@ -101,6 +101,8 @@
+ extern unsigned int sdhci_pltfm_clk_get_max_clock(struct sdhci_host *host);
+
+ #ifdef CONFIG_PM
++extern int sdhci_pltfm_suspend(struct device *dev);
++extern int sdhci_pltfm_resume(struct device *dev);
+ extern const struct dev_pm_ops sdhci_pltfm_pmops;
+ #define SDHCI_PLTFM_PMOPS (&sdhci_pltfm_pmops)
+ #else
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-pxav2.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pxav2.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-pxav2.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pxav2.c 2014-05-15 20:33:58.242015624 +0200
+@@ -51,11 +51,13 @@
+ #define MMC_CARD 0x1000
+ #define MMC_WIDTH 0x0100
+
+-static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
++static void pxav2_reset(struct sdhci_host *host, u8 mask)
+ {
+ struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
++ sdhci_reset(host, mask);
++
+ if (mask == SDHCI_RESET_ALL) {
+ u16 tmp = 0;
+
+@@ -88,7 +90,7 @@
+ }
+ }
+
+-static int pxav2_mmc_set_width(struct sdhci_host *host, int width)
++static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u8 ctrl;
+ u16 tmp;
+@@ -107,14 +109,14 @@
+ }
+ writew(tmp, host->ioaddr + SD_CE_ATA_2);
+ writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
+-
+- return 0;
+ }
+
+ static const struct sdhci_ops pxav2_sdhci_ops = {
++ .set_clock = sdhci_set_clock,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+- .platform_reset_exit = pxav2_set_private_registers,
+- .platform_bus_width = pxav2_mmc_set_width,
++ .set_bus_width = pxav2_mmc_set_bus_width,
++ .reset = pxav2_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ #ifdef CONFIG_OF
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-pxav3.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pxav3.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-pxav3.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-pxav3.c 2014-05-15 20:33:58.242015624 +0200
+@@ -57,11 +57,13 @@
+ #define SDCE_MISC_INT (1<<2)
+ #define SDCE_MISC_INT_EN (1<<1)
+
+-static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
++static void pxav3_reset(struct sdhci_host *host, u8 mask)
+ {
+ struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
++ sdhci_reset(host, mask);
++
+ if (mask == SDHCI_RESET_ALL) {
+ /*
+ * tune timing of read data/command when crc error happen
+@@ -168,10 +170,13 @@
+ }
+
+ static const struct sdhci_ops pxav3_sdhci_ops = {
+- .platform_reset_exit = pxav3_set_private_registers,
++ .set_clock = sdhci_set_clock,
+ .set_uhs_signaling = pxav3_set_uhs_signaling,
+ .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = pxav3_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
+@@ -276,7 +281,8 @@
+ host->mmc->pm_caps |= pdata->pm_caps;
+
+ if (gpio_is_valid(pdata->ext_cd_gpio)) {
+- ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio);
++ ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
++ 0);
+ if (ret) {
+ dev_err(mmc_dev(host->mmc),
+ "failed to allocate card detect gpio\n");
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-s3c.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-s3c.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-s3c.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-s3c.c 2014-05-15 20:33:58.246015652 +0200
+@@ -57,6 +57,8 @@
+
+ struct clk *clk_io;
+ struct clk *clk_bus[MAX_BUS_CLK];
++
++ bool no_divider;
+ };
+
+ /**
+@@ -69,6 +71,7 @@
+ */
+ struct sdhci_s3c_drv_data {
+ unsigned int sdhci_quirks;
++ bool no_divider;
+ };
+
+ static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
+@@ -153,7 +156,7 @@
+ * If controller uses a non-standard clock division, find the best clock
+ * speed possible with selected clock source and skip the division.
+ */
+- if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
++ if (ourhost->no_divider) {
+ rate = clk_round_rate(clksrc, wanted);
+ return wanted - rate;
+ }
+@@ -188,9 +191,13 @@
+ int src;
+ u32 ctrl;
+
++ host->mmc->actual_clock = 0;
++
+ /* don't bother if the clock is going off. */
+- if (clock == 0)
++ if (clock == 0) {
++ sdhci_set_clock(host, clock);
+ return;
++ }
+
+ for (src = 0; src < MAX_BUS_CLK; src++) {
+ delta = sdhci_s3c_consider_clock(ourhost, src, clock);
+@@ -240,6 +247,8 @@
+ if (clock < 25 * 1000000)
+ ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
+ writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
++
++ sdhci_set_clock(host, clock);
+ }
+
+ /**
+@@ -296,6 +305,8 @@
+ unsigned long timeout;
+ u16 clk = 0;
+
++ host->mmc->actual_clock = 0;
++
+ /* don't bother if the clock is going off */
+ if (clock == 0)
+ return;
+@@ -304,8 +315,6 @@
+
+ clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
+
+- host->clock = clock;
+-
+ clk = SDHCI_CLOCK_INT_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+@@ -327,14 +336,14 @@
+ }
+
+ /**
+- * sdhci_s3c_platform_bus_width - support 8bit buswidth
++ * sdhci_s3c_set_bus_width - support 8bit buswidth
+ * @host: The SDHCI host being queried
+ * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
+ *
+ * We have 8-bit width support but is not a v3 controller.
+ * So we add platform_bus_width() and support 8bit width.
+ */
+-static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width)
++static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u8 ctrl;
+
+@@ -356,15 +365,15 @@
+ }
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+-
+- return 0;
+ }
+
+ static struct sdhci_ops sdhci_s3c_ops = {
+ .get_max_clock = sdhci_s3c_get_max_clk,
+ .set_clock = sdhci_s3c_set_clock,
+ .get_min_clock = sdhci_s3c_get_min_clock,
+- .platform_bus_width = sdhci_s3c_platform_bus_width,
++ .set_bus_width = sdhci_s3c_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
+@@ -613,8 +622,10 @@
+ /* Setup quirks for the controller */
+ host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
+ host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+- if (drv_data)
++ if (drv_data) {
+ host->quirks |= drv_data->sdhci_quirks;
++ sc->no_divider = drv_data->no_divider;
++ }
+
+ #ifndef CONFIG_MMC_SDHCI_S3C_DMA
+
+@@ -663,7 +674,7 @@
+ * If controller does not have internal clock divider,
+ * we can use overriding functions instead of default.
+ */
+- if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
++ if (sc->no_divider) {
+ sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
+ sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
+ sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
+@@ -810,7 +821,7 @@
+
+ #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+ static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
+- .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
++ .no_divider = true,
+ };
+ #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
+ #else
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-sirf.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-sirf.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-sirf.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-sirf.c 2014-05-15 20:33:58.246015652 +0200
+@@ -29,7 +29,11 @@
+ }
+
+ static struct sdhci_ops sdhci_sirf_ops = {
++ .set_clock = sdhci_set_clock,
+ .get_max_clock = sdhci_sirf_get_max_clk,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static struct sdhci_pltfm_data sdhci_sirf_pdata = {
+@@ -97,7 +101,7 @@
+ * gets setup in sdhci_add_host() and we oops.
+ */
+ if (gpio_is_valid(priv->gpio_cd)) {
+- ret = mmc_gpio_request_cd(host->mmc, priv->gpio_cd);
++ ret = mmc_gpio_request_cd(host->mmc, priv->gpio_cd, 0);
+ if (ret) {
+ dev_err(&pdev->dev, "card detect irq request failed: %d\n",
+ ret);
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-spear.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-spear.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-spear.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-spear.c 2014-05-15 20:33:58.246015652 +0200
+@@ -37,7 +37,10 @@
+
+ /* sdhci ops */
+ static const struct sdhci_ops sdhci_pltfm_ops = {
+- /* Nothing to do for now. */
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ /* gpio card detection interrupt handler */
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sdhci-tegra.c linux-linaro-stable-mx6/drivers/mmc/host/sdhci-tegra.c
+--- linux-3.10.30.orig/drivers/mmc/host/sdhci-tegra.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sdhci-tegra.c 2014-05-15 20:33:58.246015652 +0200
+@@ -48,19 +48,6 @@
+ int power_gpio;
+ };
+
+-static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
+-{
+- u32 val;
+-
+- if (unlikely(reg == SDHCI_PRESENT_STATE)) {
+- /* Use wp_gpio here instead? */
+- val = readl(host->ioaddr + reg);
+- return val | SDHCI_WRITE_PROTECT;
+- }
+-
+- return readl(host->ioaddr + reg);
+-}
+-
+ static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+@@ -108,12 +95,14 @@
+ return mmc_gpio_get_ro(host->mmc);
+ }
+
+-static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask)
++static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_tegra *tegra_host = pltfm_host->priv;
+ const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
+
++ sdhci_reset(host, mask);
++
+ if (!(mask & SDHCI_RESET_ALL))
+ return;
+
+@@ -127,7 +116,7 @@
+ }
+ }
+
+-static int tegra_sdhci_buswidth(struct sdhci_host *host, int bus_width)
++static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
+ {
+ u32 ctrl;
+
+@@ -144,16 +133,16 @@
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ }
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+- return 0;
+ }
+
+ static const struct sdhci_ops tegra_sdhci_ops = {
+ .get_ro = tegra_sdhci_get_ro,
+- .read_l = tegra_sdhci_readl,
+ .read_w = tegra_sdhci_readw,
+ .write_l = tegra_sdhci_writel,
+- .platform_bus_width = tegra_sdhci_buswidth,
+- .platform_reset_exit = tegra_sdhci_reset_exit,
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = tegra_sdhci_set_bus_width,
++ .reset = tegra_sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/sh_mmcif.c linux-linaro-stable-mx6/drivers/mmc/host/sh_mmcif.c
+--- linux-3.10.30.orig/drivers/mmc/host/sh_mmcif.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/sh_mmcif.c 2014-05-15 20:33:58.246015652 +0200
+@@ -1431,7 +1431,7 @@
+ }
+
+ if (pd && pd->use_cd_gpio) {
+- ret = mmc_gpio_request_cd(mmc, pd->cd_gpio);
++ ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0);
+ if (ret < 0)
+ goto erqcd;
+ }
+diff -Nur linux-3.10.30.orig/drivers/mmc/host/tmio_mmc_pio.c linux-linaro-stable-mx6/drivers/mmc/host/tmio_mmc_pio.c
+--- linux-3.10.30.orig/drivers/mmc/host/tmio_mmc_pio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mmc/host/tmio_mmc_pio.c 2014-05-15 20:33:58.258015739 +0200
+@@ -1091,7 +1091,7 @@
+ dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
+
+ if (pdata->flags & TMIO_MMC_USE_GPIO_CD) {
+- ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio);
++ ret = mmc_gpio_request_cd(mmc, pdata->cd_gpio, 0);
+ if (ret < 0) {
+ tmio_mmc_host_remove(_host);
+ return ret;
+diff -Nur linux-3.10.30.orig/drivers/mtd/chips/cfi_cmdset_0002.c linux-linaro-stable-mx6/drivers/mtd/chips/cfi_cmdset_0002.c
+--- linux-3.10.30.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/chips/cfi_cmdset_0002.c 2014-05-15 20:33:58.262015767 +0200
+@@ -1058,17 +1058,13 @@
+
+ #define UDELAY(map, chip, adr, usec) \
+ do { \
+- mutex_unlock(&chip->mutex); \
+ cfi_udelay(usec); \
+- mutex_lock(&chip->mutex); \
+ } while (0)
+
+ #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
+ do { \
+- mutex_unlock(&chip->mutex); \
+ INVALIDATE_CACHED_RANGE(map, adr, len); \
+ cfi_udelay(usec); \
+- mutex_lock(&chip->mutex); \
+ } while (0)
+
+ #endif
+diff -Nur linux-3.10.30.orig/drivers/mtd/inftlcore.c linux-linaro-stable-mx6/drivers/mtd/inftlcore.c
+--- linux-3.10.30.orig/drivers/mtd/inftlcore.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/inftlcore.c 2014-05-15 20:33:58.362016488 +0200
+@@ -50,7 +50,7 @@
+ struct INFTLrecord *inftl;
+ unsigned long temp;
+
+- if (mtd->type != MTD_NANDFLASH || mtd->size > UINT_MAX)
++ if (!mtd_type_is_nand(mtd) || mtd->size > UINT_MAX)
+ return;
+ /* OK, this is moderately ugly. But probably safe. Alternatives? */
+ if (memcmp(mtd->name, "DiskOnChip", 10))
+diff -Nur linux-3.10.30.orig/drivers/mtd/mtdcore.c linux-linaro-stable-mx6/drivers/mtd/mtdcore.c
+--- linux-3.10.30.orig/drivers/mtd/mtdcore.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/mtdcore.c 2014-05-15 20:33:58.398016748 +0200
+@@ -157,6 +157,9 @@
+ case MTD_UBIVOLUME:
+ type = "ubi";
+ break;
++ case MTD_MLCNANDFLASH:
++ type = "mlc-nand";
++ break;
+ default:
+ type = "unknown";
+ }
+@@ -285,6 +288,16 @@
+ mtd_bitflip_threshold_show,
+ mtd_bitflip_threshold_store);
+
++static ssize_t mtd_ecc_step_size_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mtd_info *mtd = dev_get_drvdata(dev);
++
++ return snprintf(buf, PAGE_SIZE, "%u\n", mtd->ecc_step_size);
++
++}
++static DEVICE_ATTR(ecc_step_size, S_IRUGO, mtd_ecc_step_size_show, NULL);
++
+ static struct attribute *mtd_attrs[] = {
+ &dev_attr_type.attr,
+ &dev_attr_flags.attr,
+@@ -296,6 +309,7 @@
+ &dev_attr_numeraseregions.attr,
+ &dev_attr_name.attr,
+ &dev_attr_ecc_strength.attr,
++ &dev_attr_ecc_step_size.attr,
+ &dev_attr_bitflip_threshold.attr,
+ NULL,
+ };
+diff -Nur linux-3.10.30.orig/drivers/mtd/mtdpart.c linux-linaro-stable-mx6/drivers/mtd/mtdpart.c
+--- linux-3.10.30.orig/drivers/mtd/mtdpart.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/mtdpart.c 2014-05-15 20:33:58.398016748 +0200
+@@ -516,6 +516,7 @@
+ }
+
+ slave->mtd.ecclayout = master->ecclayout;
++ slave->mtd.ecc_step_size = master->ecc_step_size;
+ slave->mtd.ecc_strength = master->ecc_strength;
+ slave->mtd.bitflip_threshold = master->bitflip_threshold;
+
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/denali.c linux-linaro-stable-mx6/drivers/mtd/nand/denali.c
+--- linux-3.10.30.orig/drivers/mtd/nand/denali.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/denali.c 2014-05-15 20:33:58.402016777 +0200
+@@ -1520,7 +1520,7 @@
+ * so just let controller do 15bit ECC for MLC and 8bit ECC for
+ * SLC if possible.
+ * */
+- if (denali->nand.cellinfo & 0xc &&
++ if (!nand_is_slc(&denali->nand) &&
+ (denali->mtd.oobsize > (denali->bbtskipbytes +
+ ECC_15BITS * (denali->mtd.writesize /
+ ECC_SECTOR_SIZE)))) {
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/docg4.c linux-linaro-stable-mx6/drivers/mtd/nand/docg4.c
+--- linux-3.10.30.orig/drivers/mtd/nand/docg4.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/docg4.c 2014-05-15 20:33:58.406016805 +0200
+@@ -1093,7 +1093,6 @@
+ struct nand_chip *nand = mtd->priv;
+ struct docg4_priv *doc = nand->priv;
+ struct nand_bbt_descr *bbtd = nand->badblock_pattern;
+- int block = (int)(ofs >> nand->bbt_erase_shift);
+ int page = (int)(ofs >> nand->page_shift);
+ uint32_t g4_addr = mtd_to_docg4_address(page, 0);
+
+@@ -1108,9 +1107,6 @@
+ if (buf == NULL)
+ return -ENOMEM;
+
+- /* update bbt in memory */
+- nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2);
+-
+ /* write bit-wise negation of pattern to oob buffer */
+ memset(nand->oob_poi, 0xff, mtd->oobsize);
+ for (i = 0; i < bbtd->len; i++)
+@@ -1120,8 +1116,6 @@
+ write_page_prologue(mtd, g4_addr);
+ docg4_write_page(mtd, nand, buf, 1);
+ ret = pageprog(mtd);
+- if (!ret)
+- mtd->ecc_stats.badblocks++;
+
+ kfree(buf);
+
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/fsl_elbc_nand.c linux-linaro-stable-mx6/drivers/mtd/nand/fsl_elbc_nand.c
+--- linux-3.10.30.orig/drivers/mtd/nand/fsl_elbc_nand.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/fsl_elbc_nand.c 2014-05-15 20:33:58.406016805 +0200
+@@ -650,8 +650,6 @@
+ chip->page_shift);
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n",
+ chip->phys_erase_shift);
+- dev_dbg(priv->dev, "fsl_elbc_init: nand->ecclayout = %p\n",
+- chip->ecclayout);
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n",
+ chip->ecc.mode);
+ dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n",
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/fsl_ifc_nand.c linux-linaro-stable-mx6/drivers/mtd/nand/fsl_ifc_nand.c
+--- linux-3.10.30.orig/drivers/mtd/nand/fsl_ifc_nand.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/fsl_ifc_nand.c 2014-05-15 20:33:58.422016921 +0200
+@@ -718,8 +718,6 @@
+ chip->page_shift);
+ dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
+ chip->phys_erase_shift);
+- dev_dbg(priv->dev, "%s: nand->ecclayout = %p\n", __func__,
+- chip->ecclayout);
+ dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
+ chip->ecc.mode);
+ dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/gpmi-nand/gpmi-lib.c linux-linaro-stable-mx6/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+--- linux-3.10.30.orig/drivers/mtd/nand/gpmi-nand/gpmi-lib.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/gpmi-nand/gpmi-lib.c 2014-05-15 20:33:58.426016950 +0200
+@@ -20,6 +20,7 @@
+ */
+ #include <linux/delay.h>
+ #include <linux/clk.h>
++#include <linux/slab.h>
+
+ #include "gpmi-nand.h"
+ #include "gpmi-regs.h"
+@@ -187,6 +188,12 @@
+ /* Select BCH ECC. */
+ writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
+
++ /*
++ * Decouple the chip select from dma channel. We use dma0 for all
++ * the chips.
++ */
++ writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
++
+ gpmi_disable_clk(this);
+ return 0;
+ err_out:
+@@ -201,30 +208,41 @@
+ u32 reg;
+ int i;
+
+- pr_err("Show GPMI registers :\n");
++ dev_err(this->dev, "Show GPMI registers :\n");
+ for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
+ reg = readl(r->gpmi_regs + i * 0x10);
+- pr_err("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
++ dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
+ }
+
+ /* start to print out the BCH info */
+- pr_err("Show BCH registers :\n");
++ dev_err(this->dev, "Show BCH registers :\n");
+ for (i = 0; i <= HW_BCH_VERSION / 0x10 + 1; i++) {
+ reg = readl(r->bch_regs + i * 0x10);
+- pr_err("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
++ dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
+ }
+- pr_err("BCH Geometry :\n");
+- pr_err("GF length : %u\n", geo->gf_len);
+- pr_err("ECC Strength : %u\n", geo->ecc_strength);
+- pr_err("Page Size in Bytes : %u\n", geo->page_size);
+- pr_err("Metadata Size in Bytes : %u\n", geo->metadata_size);
+- pr_err("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size);
+- pr_err("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
+- pr_err("Payload Size in Bytes : %u\n", geo->payload_size);
+- pr_err("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size);
+- pr_err("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
+- pr_err("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
+- pr_err("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
++ dev_err(this->dev, "BCH Geometry :\n"
++ "GF length : %u\n"
++ "ECC Strength : %u\n"
++ "Page Size in Bytes : %u\n"
++ "Metadata Size in Bytes : %u\n"
++ "ECC Chunk Size in Bytes: %u\n"
++ "ECC Chunk Count : %u\n"
++ "Payload Size in Bytes : %u\n"
++ "Auxiliary Size in Bytes: %u\n"
++ "Auxiliary Status Offset: %u\n"
++ "Block Mark Byte Offset : %u\n"
++ "Block Mark Bit Offset : %u\n",
++ geo->gf_len,
++ geo->ecc_strength,
++ geo->page_size,
++ geo->metadata_size,
++ geo->ecc_chunk_size,
++ geo->ecc_chunk_count,
++ geo->payload_size,
++ geo->auxiliary_size,
++ geo->auxiliary_status_offset,
++ geo->block_mark_byte_offset,
++ geo->block_mark_bit_offset);
+ }
+
+ /* Configures the geometry for BCH. */
+@@ -259,8 +277,8 @@
+ * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
+ * On the other hand, the MX28 needs the reset, because one case has been
+ * seen where the BCH produced ECC errors constantly after 10000
+- * consecutive reboots. The latter case has not been seen on the MX23 yet,
+- * still we don't know if it could happen there as well.
++ * consecutive reboots. The latter case has not been seen on the MX23
++ * yet, still we don't know if it could happen there as well.
+ */
+ ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
+ if (ret)
+@@ -347,7 +365,7 @@
+ improved_timing_is_available =
+ (target.tREA_in_ns >= 0) &&
+ (target.tRLOH_in_ns >= 0) &&
+- (target.tRHOH_in_ns >= 0) ;
++ (target.tRHOH_in_ns >= 0);
+
+ /* Inspect the clock. */
+ nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
+@@ -905,10 +923,14 @@
+ struct resources *r = &this->resources;
+ struct nand_chip *nand = &this->nand;
+ struct mtd_info *mtd = &this->mtd;
+- uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
++ uint8_t *feature;
+ unsigned long rate;
+ int ret;
+
++ feature = kzalloc(ONFI_SUBFEATURE_PARAM_LEN, GFP_KERNEL);
++ if (!feature)
++ return -ENOMEM;
++
+ nand->select_chip(mtd, 0);
+
+ /* [1] send SET FEATURE commond to NAND */
+@@ -936,11 +958,13 @@
+
+ this->flags |= GPMI_ASYNC_EDO_ENABLED;
+ this->timing_mode = mode;
++ kfree(feature);
+ dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode);
+ return 0;
+
+ err_out:
+ nand->select_chip(mtd, -1);
++ kfree(feature);
+ dev_err(this->dev, "mode:%d ,failed in set feature.\n", mode);
+ return -EINVAL;
+ }
+@@ -980,7 +1004,7 @@
+ /* Enable the clock. */
+ ret = gpmi_enable_clk(this);
+ if (ret) {
+- pr_err("We failed in enable the clk\n");
++ dev_err(this->dev, "We failed in enable the clk\n");
+ goto err_out;
+ }
+
+@@ -997,7 +1021,7 @@
+ /* [1] Set HW_GPMI_TIMING0 */
+ reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
+ BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
+- BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
++ BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles);
+
+ writel(reg, gpmi_regs + HW_GPMI_TIMING0);
+
+@@ -1073,11 +1097,18 @@
+ mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
+ reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
+ } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6Q(this)) {
++ /*
++ * In the imx6, all the ready/busy pins are bound
++ * together. So we only need to check chip 0.
++ */
++ if (GPMI_IS_MX6Q(this))
++ chip = 0;
++
+ /* MX28 shares the same R/B register as MX6Q. */
+ mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
+ reg = readl(r->gpmi_regs + HW_GPMI_STAT);
+ } else
+- pr_err("unknow arch.\n");
++ dev_err(this->dev, "unknow arch.\n");
+ return reg & mask;
+ }
+
+@@ -1108,10 +1139,8 @@
+ desc = dmaengine_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
+- if (!desc) {
+- pr_err("step 1 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
+
+ /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
+ sgl = &this->cmd_sgl;
+@@ -1121,11 +1150,8 @@
+ desc = dmaengine_prep_slave_sg(channel,
+ sgl, 1, DMA_MEM_TO_DEV,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+-
+- if (!desc) {
+- pr_err("step 2 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
+
+ /* [3] submit the DMA */
+ set_dma_type(this, DMA_FOR_COMMAND);
+@@ -1154,20 +1180,17 @@
+ pio[1] = 0;
+ desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
+- if (!desc) {
+- pr_err("step 1 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
+
+ /* [2] send DMA request */
+ prepare_data_dma(this, DMA_TO_DEVICE);
+ desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
+ 1, DMA_MEM_TO_DEV,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+- if (!desc) {
+- pr_err("step 2 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
++
+ /* [3] submit the DMA */
+ set_dma_type(this, DMA_FOR_WRITE_DATA);
+ return start_dma_without_bch_irq(this, desc);
+@@ -1191,20 +1214,16 @@
+ desc = dmaengine_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
+- if (!desc) {
+- pr_err("step 1 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
+
+ /* [2] : send DMA request */
+ prepare_data_dma(this, DMA_FROM_DEVICE);
+ desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
+ 1, DMA_DEV_TO_MEM,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+- if (!desc) {
+- pr_err("step 2 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
+
+ /* [3] : submit the DMA */
+ set_dma_type(this, DMA_FOR_READ_DATA);
+@@ -1249,10 +1268,9 @@
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_TRANS_NONE,
+ DMA_CTRL_ACK);
+- if (!desc) {
+- pr_err("step 2 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
++
+ set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
+ return start_dma_with_bch_irq(this, desc);
+ }
+@@ -1284,10 +1302,8 @@
+ desc = dmaengine_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2,
+ DMA_TRANS_NONE, 0);
+- if (!desc) {
+- pr_err("step 1 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
+
+ /* [2] Enable the BCH block and read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+@@ -1314,10 +1330,8 @@
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_TRANS_NONE,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+- if (!desc) {
+- pr_err("step 2 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
+
+ /* [3] Disable the BCH block */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+@@ -1335,10 +1349,8 @@
+ (struct scatterlist *)pio, 3,
+ DMA_TRANS_NONE,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+- if (!desc) {
+- pr_err("step 3 error\n");
+- return -1;
+- }
++ if (!desc)
++ return -EINVAL;
+
+ /* [4] submit the DMA */
+ set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/gpmi-nand/gpmi-nand.c linux-linaro-stable-mx6/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+--- linux-3.10.30.orig/drivers/mtd/nand/gpmi-nand/gpmi-nand.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/gpmi-nand/gpmi-nand.c 2014-05-15 20:33:58.426016950 +0200
+@@ -18,15 +18,11 @@
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+ #include <linux/clk.h>
+ #include <linux/slab.h>
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/mtd/partitions.h>
+-#include <linux/pinctrl/consumer.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/of_mtd.h>
+@@ -46,7 +42,10 @@
+ .pattern = scan_ff_pattern
+ };
+
+-/* We will use all the (page + OOB). */
++/*
++ * We may change the layout if we can get the ECC info from the datasheet,
++ * else we will use all the (page + OOB).
++ */
+ static struct nand_ecclayout gpmi_hw_ecclayout = {
+ .eccbytes = 0,
+ .eccpos = { 0, },
+@@ -112,7 +111,131 @@
+ return true;
+ }
+
+-int common_nfc_set_geometry(struct gpmi_nand_data *this)
++/*
++ * If we can get the ECC information from the nand chip, we do not
++ * need to calculate them ourselves.
++ *
++ * We may have available oob space in this case.
++ */
++static bool set_geometry_by_ecc_info(struct gpmi_nand_data *this)
++{
++ struct bch_geometry *geo = &this->bch_geometry;
++ struct mtd_info *mtd = &this->mtd;
++ struct nand_chip *chip = mtd->priv;
++ struct nand_oobfree *of = gpmi_hw_ecclayout.oobfree;
++ unsigned int block_mark_bit_offset;
++
++ if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
++ return false;
++
++ switch (chip->ecc_step_ds) {
++ case SZ_512:
++ geo->gf_len = 13;
++ break;
++ case SZ_1K:
++ geo->gf_len = 14;
++ break;
++ default:
++ dev_err(this->dev,
++ "unsupported nand chip. ecc bits : %d, ecc size : %d\n",
++ chip->ecc_strength_ds, chip->ecc_step_ds);
++ return false;
++ }
++ geo->ecc_chunk_size = chip->ecc_step_ds;
++ geo->ecc_strength = round_up(chip->ecc_strength_ds, 2);
++ if (!gpmi_check_ecc(this))
++ return false;
++
++ /* Keep the C >= O */
++ if (geo->ecc_chunk_size < mtd->oobsize) {
++ dev_err(this->dev,
++ "unsupported nand chip. ecc size: %d, oob size : %d\n",
++ chip->ecc_step_ds, mtd->oobsize);
++ return false;
++ }
++
++ /* The default value, see comment in the legacy_set_geometry(). */
++ geo->metadata_size = 10;
++
++ geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
++
++ /*
++ * Now, the NAND chip with 2K page(data chunk is 512byte) shows below:
++ *
++ * | P |
++ * |<----------------------------------------------------->|
++ * | |
++ * | (Block Mark) |
++ * | P' | | | |
++ * |<-------------------------------------------->| D | | O' |
++ * | |<---->| |<--->|
++ * V V V V V
++ * +---+----------+-+----------+-+----------+-+----------+-+-----+
++ * | M | data |E| data |E| data |E| data |E| |
++ * +---+----------+-+----------+-+----------+-+----------+-+-----+
++ * ^ ^
++ * | O |
++ * |<------------>|
++ * | |
++ *
++ * P : the page size for BCH module.
++ * E : The ECC strength.
++ * G : the length of Galois Field.
++ * N : The chunk count of per page.
++ * M : the metasize of per page.
++ * C : the ecc chunk size, aka the "data" above.
++ * P': the nand chip's page size.
++ * O : the nand chip's oob size.
++ * O': the free oob.
++ *
++ * The formula for P is :
++ *
++ * E * G * N
++ * P = ------------ + P' + M
++ * 8
++ *
++ * The position of block mark moves forward in the ECC-based view
++ * of page, and the delta is:
++ *
++ * E * G * (N - 1)
++ * D = (---------------- + M)
++ * 8
++ *
++ * Please see the comment in legacy_set_geometry().
++ * With the condition C >= O , we still can get same result.
++ * So the bit position of the physical block mark within the ECC-based
++ * view of the page is :
++ * (P' - D) * 8
++ */
++ geo->page_size = mtd->writesize + geo->metadata_size +
++ (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8;
++
++ /* The available oob size we have. */
++ if (geo->page_size < mtd->writesize + mtd->oobsize) {
++ of->offset = geo->page_size - mtd->writesize;
++ of->length = mtd->oobsize - of->offset;
++ }
++
++ geo->payload_size = mtd->writesize;
++
++ geo->auxiliary_status_offset = ALIGN(geo->metadata_size, 4);
++ geo->auxiliary_size = ALIGN(geo->metadata_size, 4)
++ + ALIGN(geo->ecc_chunk_count, 4);
++
++ if (!this->swap_block_mark)
++ return true;
++
++ /* For bit swap. */
++ block_mark_bit_offset = mtd->writesize * 8 -
++ (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
++ + geo->metadata_size * 8);
++
++ geo->block_mark_byte_offset = block_mark_bit_offset / 8;
++ geo->block_mark_bit_offset = block_mark_bit_offset % 8;
++ return true;
++}
++
++static int legacy_set_geometry(struct gpmi_nand_data *this)
+ {
+ struct bch_geometry *geo = &this->bch_geometry;
+ struct mtd_info *mtd = &this->mtd;
+@@ -224,11 +347,18 @@
+ return 0;
+ }
+
+-struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
++int common_nfc_set_geometry(struct gpmi_nand_data *this)
+ {
+- int chipnr = this->current_chip;
++ if (of_property_read_bool(this->dev->of_node, "fsl,use-minimum-ecc")
++ && set_geometry_by_ecc_info(this))
++ return 0;
++ return legacy_set_geometry(this);
++}
+
+- return this->dma_chans[chipnr];
++struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
++{
++ /* We use the DMA channel 0 to access all the nand chips. */
++ return this->dma_chans[0];
+ }
+
+ /* Can we use the upper's buffer directly for DMA? */
+@@ -252,7 +382,7 @@
+
+ ret = dma_map_sg(this->dev, sgl, 1, dr);
+ if (ret == 0)
+- pr_err("DMA mapping failed.\n");
++ dev_err(this->dev, "DMA mapping failed.\n");
+
+ this->direct_dma_map_ok = false;
+ }
+@@ -286,7 +416,7 @@
+ break;
+
+ default:
+- pr_err("in wrong DMA operation.\n");
++ dev_err(this->dev, "in wrong DMA operation.\n");
+ }
+
+ complete(dma_c);
+@@ -308,7 +438,8 @@
+ /* Wait for the interrupt from the DMA block. */
+ err = wait_for_completion_timeout(dma_c, msecs_to_jiffies(1000));
+ if (!err) {
+- pr_err("DMA timeout, last DMA :%d\n", this->last_dma_type);
++ dev_err(this->dev, "DMA timeout, last DMA :%d\n",
++ this->last_dma_type);
+ gpmi_dump_info(this);
+ return -ETIMEDOUT;
+ }
+@@ -337,7 +468,8 @@
+ /* Wait for the interrupt from the BCH block. */
+ err = wait_for_completion_timeout(bch_c, msecs_to_jiffies(1000));
+ if (!err) {
+- pr_err("BCH timeout, last DMA :%d\n", this->last_dma_type);
++ dev_err(this->dev, "BCH timeout, last DMA :%d\n",
++ this->last_dma_type);
+ gpmi_dump_info(this);
+ return -ETIMEDOUT;
+ }
+@@ -353,70 +485,38 @@
+ void __iomem *p;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
+- if (!r) {
+- pr_err("Can't get resource for %s\n", res_name);
+- return -ENXIO;
+- }
+-
+- p = ioremap(r->start, resource_size(r));
+- if (!p) {
+- pr_err("Can't remap %s\n", res_name);
+- return -ENOMEM;
+- }
++ p = devm_ioremap_resource(&pdev->dev, r);
++ if (IS_ERR(p))
++ return PTR_ERR(p);
+
+ if (!strcmp(res_name, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME))
+ res->gpmi_regs = p;
+ else if (!strcmp(res_name, GPMI_NAND_BCH_REGS_ADDR_RES_NAME))
+ res->bch_regs = p;
+ else
+- pr_err("unknown resource name : %s\n", res_name);
++ dev_err(this->dev, "unknown resource name : %s\n", res_name);
+
+ return 0;
+ }
+
+-static void release_register_block(struct gpmi_nand_data *this)
+-{
+- struct resources *res = &this->resources;
+- if (res->gpmi_regs)
+- iounmap(res->gpmi_regs);
+- if (res->bch_regs)
+- iounmap(res->bch_regs);
+- res->gpmi_regs = NULL;
+- res->bch_regs = NULL;
+-}
+-
+ static int acquire_bch_irq(struct gpmi_nand_data *this, irq_handler_t irq_h)
+ {
+ struct platform_device *pdev = this->pdev;
+- struct resources *res = &this->resources;
+ const char *res_name = GPMI_NAND_BCH_INTERRUPT_RES_NAME;
+ struct resource *r;
+ int err;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
+ if (!r) {
+- pr_err("Can't get resource for %s\n", res_name);
+- return -ENXIO;
+- }
+-
+- err = request_irq(r->start, irq_h, 0, res_name, this);
+- if (err) {
+- pr_err("Can't own %s\n", res_name);
+- return err;
++ dev_err(this->dev, "Can't get resource for %s\n", res_name);
++ return -ENODEV;
+ }
+
+- res->bch_low_interrupt = r->start;
+- res->bch_high_interrupt = r->end;
+- return 0;
+-}
+-
+-static void release_bch_irq(struct gpmi_nand_data *this)
+-{
+- struct resources *res = &this->resources;
+- int i = res->bch_low_interrupt;
++ err = devm_request_irq(this->dev, r->start, irq_h, 0, res_name, this);
++ if (err)
++ dev_err(this->dev, "error requesting BCH IRQ\n");
+
+- for (; i <= res->bch_high_interrupt; i++)
+- free_irq(i, this);
++ return err;
+ }
+
+ static void release_dma_channels(struct gpmi_nand_data *this)
+@@ -437,7 +537,7 @@
+ /* request dma channel */
+ dma_chan = dma_request_slave_channel(&pdev->dev, "rx-tx");
+ if (!dma_chan) {
+- pr_err("Failed to request DMA channel.\n");
++ dev_err(this->dev, "Failed to request DMA channel.\n");
+ goto acquire_err;
+ }
+
+@@ -449,21 +549,6 @@
+ return -EINVAL;
+ }
+
+-static void gpmi_put_clks(struct gpmi_nand_data *this)
+-{
+- struct resources *r = &this->resources;
+- struct clk *clk;
+- int i;
+-
+- for (i = 0; i < GPMI_CLK_MAX; i++) {
+- clk = r->clock[i];
+- if (clk) {
+- clk_put(clk);
+- r->clock[i] = NULL;
+- }
+- }
+-}
+-
+ static char *extra_clks_for_mx6q[GPMI_CLK_MAX] = {
+ "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch",
+ };
+@@ -473,12 +558,14 @@
+ struct resources *r = &this->resources;
+ char **extra_clks = NULL;
+ struct clk *clk;
+- int i;
++ int err, i;
+
+ /* The main clock is stored in the first. */
+- r->clock[0] = clk_get(this->dev, "gpmi_io");
+- if (IS_ERR(r->clock[0]))
++ r->clock[0] = devm_clk_get(this->dev, "gpmi_io");
++ if (IS_ERR(r->clock[0])) {
++ err = PTR_ERR(r->clock[0]);
+ goto err_clock;
++ }
+
+ /* Get extra clocks */
+ if (GPMI_IS_MX6Q(this))
+@@ -490,9 +577,11 @@
+ if (extra_clks[i - 1] == NULL)
+ break;
+
+- clk = clk_get(this->dev, extra_clks[i - 1]);
+- if (IS_ERR(clk))
++ clk = devm_clk_get(this->dev, extra_clks[i - 1]);
++ if (IS_ERR(clk)) {
++ err = PTR_ERR(clk);
+ goto err_clock;
++ }
+
+ r->clock[i] = clk;
+ }
+@@ -510,13 +599,11 @@
+
+ err_clock:
+ dev_dbg(this->dev, "failed in finding the clocks.\n");
+- gpmi_put_clks(this);
+- return -ENOMEM;
++ return err;
+ }
+
+ static int acquire_resources(struct gpmi_nand_data *this)
+ {
+- struct pinctrl *pinctrl;
+ int ret;
+
+ ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME);
+@@ -533,13 +620,7 @@
+
+ ret = acquire_dma_channels(this);
+ if (ret)
+- goto exit_dma_channels;
+-
+- pinctrl = devm_pinctrl_get_select_default(&this->pdev->dev);
+- if (IS_ERR(pinctrl)) {
+- ret = PTR_ERR(pinctrl);
+- goto exit_pin;
+- }
++ goto exit_regs;
+
+ ret = gpmi_get_clks(this);
+ if (ret)
+@@ -547,20 +628,13 @@
+ return 0;
+
+ exit_clock:
+-exit_pin:
+ release_dma_channels(this);
+-exit_dma_channels:
+- release_bch_irq(this);
+ exit_regs:
+- release_register_block(this);
+ return ret;
+ }
+
+ static void release_resources(struct gpmi_nand_data *this)
+ {
+- gpmi_put_clks(this);
+- release_register_block(this);
+- release_bch_irq(this);
+ release_dma_channels(this);
+ }
+
+@@ -606,8 +680,7 @@
+ length, DMA_FROM_DEVICE);
+ if (dma_mapping_error(dev, dest_phys)) {
+ if (alt_size < length) {
+- pr_err("%s, Alternate buffer is too small\n",
+- __func__);
++ dev_err(dev, "Alternate buffer is too small\n");
+ return -ENOMEM;
+ }
+ goto map_failed;
+@@ -657,8 +730,7 @@
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, source_phys)) {
+ if (alt_size < length) {
+- pr_err("%s, Alternate buffer is too small\n",
+- __func__);
++ dev_err(dev, "Alternate buffer is too small\n");
+ return -ENOMEM;
+ }
+ goto map_failed;
+@@ -746,7 +818,6 @@
+
+ error_alloc:
+ gpmi_free_dma_buffer(this);
+- pr_err("Error allocating DMA buffers!\n");
+ return -ENOMEM;
+ }
+
+@@ -778,7 +849,8 @@
+
+ ret = gpmi_send_command(this);
+ if (ret)
+- pr_err("Chip: %u, Error %d\n", this->current_chip, ret);
++ dev_err(this->dev, "Chip: %u, Error %d\n",
++ this->current_chip, ret);
+
+ this->command_length = 0;
+ }
+@@ -809,7 +881,7 @@
+ struct nand_chip *chip = mtd->priv;
+ struct gpmi_nand_data *this = chip->priv;
+
+- pr_debug("len is %d\n", len);
++ dev_dbg(this->dev, "len is %d\n", len);
+ this->upper_buf = buf;
+ this->upper_len = len;
+
+@@ -821,7 +893,7 @@
+ struct nand_chip *chip = mtd->priv;
+ struct gpmi_nand_data *this = chip->priv;
+
+- pr_debug("len is %d\n", len);
++ dev_dbg(this->dev, "len is %d\n", len);
+ this->upper_buf = (uint8_t *)buf;
+ this->upper_len = len;
+
+@@ -900,13 +972,13 @@
+ unsigned int max_bitflips = 0;
+ int ret;
+
+- pr_debug("page number is : %d\n", page);
++ dev_dbg(this->dev, "page number is : %d\n", page);
+ ret = read_page_prepare(this, buf, mtd->writesize,
+ this->payload_virt, this->payload_phys,
+ nfc_geo->payload_size,
+ &payload_virt, &payload_phys);
+ if (ret) {
+- pr_err("Inadequate DMA buffer\n");
++ dev_err(this->dev, "Inadequate DMA buffer\n");
+ ret = -ENOMEM;
+ return ret;
+ }
+@@ -920,7 +992,7 @@
+ nfc_geo->payload_size,
+ payload_virt, payload_phys);
+ if (ret) {
+- pr_err("Error in ECC-based read: %d\n", ret);
++ dev_err(this->dev, "Error in ECC-based read: %d\n", ret);
+ return ret;
+ }
+
+@@ -976,7 +1048,7 @@
+ dma_addr_t auxiliary_phys;
+ int ret;
+
+- pr_debug("ecc write page.\n");
++ dev_dbg(this->dev, "ecc write page.\n");
+ if (this->swap_block_mark) {
+ /*
+ * If control arrives here, we're doing block mark swapping.
+@@ -1006,7 +1078,7 @@
+ nfc_geo->payload_size,
+ &payload_virt, &payload_phys);
+ if (ret) {
+- pr_err("Inadequate payload DMA buffer\n");
++ dev_err(this->dev, "Inadequate payload DMA buffer\n");
+ return 0;
+ }
+
+@@ -1016,7 +1088,7 @@
+ nfc_geo->auxiliary_size,
+ &auxiliary_virt, &auxiliary_phys);
+ if (ret) {
+- pr_err("Inadequate auxiliary DMA buffer\n");
++ dev_err(this->dev, "Inadequate auxiliary DMA buffer\n");
+ goto exit_auxiliary;
+ }
+ }
+@@ -1024,7 +1096,7 @@
+ /* Ask the NFC. */
+ ret = gpmi_send_page(this, payload_phys, auxiliary_phys);
+ if (ret)
+- pr_err("Error in ECC-based write: %d\n", ret);
++ dev_err(this->dev, "Error in ECC-based write: %d\n", ret);
+
+ if (!this->swap_block_mark) {
+ send_page_end(this, chip->oob_poi, mtd->oobsize,
+@@ -1114,7 +1186,7 @@
+ {
+ struct gpmi_nand_data *this = chip->priv;
+
+- pr_debug("page number is %d\n", page);
++ dev_dbg(this->dev, "page number is %d\n", page);
+ /* clear the OOB buffer */
+ memset(chip->oob_poi, ~0, mtd->oobsize);
+
+@@ -1139,57 +1211,53 @@
+ static int
+ gpmi_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
+ {
+- /*
+- * The BCH will use all the (page + oob).
+- * Our gpmi_hw_ecclayout can only prohibit the JFFS2 to write the oob.
+- * But it can not stop some ioctls such MEMWRITEOOB which uses
+- * MTD_OPS_PLACE_OOB. So We have to implement this function to prohibit
+- * these ioctls too.
+- */
+- return -EPERM;
++ struct nand_oobfree *of = mtd->ecclayout->oobfree;
++ int status = 0;
++
++ /* Do we have available oob area? */
++ if (!of->length)
++ return -EPERM;
++
++ if (!nand_is_slc(chip))
++ return -EPERM;
++
++ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize + of->offset, page);
++ chip->write_buf(mtd, chip->oob_poi + of->offset, of->length);
++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
++
++ status = chip->waitfunc(mtd, chip);
++ return status & NAND_STATUS_FAIL ? -EIO : 0;
+ }
+
+ static int gpmi_block_markbad(struct mtd_info *mtd, loff_t ofs)
+ {
+ struct nand_chip *chip = mtd->priv;
+ struct gpmi_nand_data *this = chip->priv;
+- int block, ret = 0;
++ int ret = 0;
+ uint8_t *block_mark;
+ int column, page, status, chipnr;
+
+- /* Get block number */
+- block = (int)(ofs >> chip->bbt_erase_shift);
+- if (chip->bbt)
+- chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
+-
+- /* Do we have a flash based bad block table ? */
+- if (chip->bbt_options & NAND_BBT_USE_FLASH)
+- ret = nand_update_bbt(mtd, ofs);
+- else {
+- chipnr = (int)(ofs >> chip->chip_shift);
+- chip->select_chip(mtd, chipnr);
++ chipnr = (int)(ofs >> chip->chip_shift);
++ chip->select_chip(mtd, chipnr);
+
+- column = this->swap_block_mark ? mtd->writesize : 0;
++ column = this->swap_block_mark ? mtd->writesize : 0;
+
+- /* Write the block mark. */
+- block_mark = this->data_buffer_dma;
+- block_mark[0] = 0; /* bad block marker */
++ /* Write the block mark. */
++ block_mark = this->data_buffer_dma;
++ block_mark[0] = 0; /* bad block marker */
+
+- /* Shift to get page */
+- page = (int)(ofs >> chip->page_shift);
++ /* Shift to get page */
++ page = (int)(ofs >> chip->page_shift);
+
+- chip->cmdfunc(mtd, NAND_CMD_SEQIN, column, page);
+- chip->write_buf(mtd, block_mark, 1);
+- chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
++ chip->cmdfunc(mtd, NAND_CMD_SEQIN, column, page);
++ chip->write_buf(mtd, block_mark, 1);
++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+- status = chip->waitfunc(mtd, chip);
+- if (status & NAND_STATUS_FAIL)
+- ret = -EIO;
++ status = chip->waitfunc(mtd, chip);
++ if (status & NAND_STATUS_FAIL)
++ ret = -EIO;
+
+- chip->select_chip(mtd, -1);
+- }
+- if (!ret)
+- mtd->ecc_stats.badblocks++;
++ chip->select_chip(mtd, -1);
+
+ return ret;
+ }
+@@ -1331,7 +1399,6 @@
+
+ /* Write the NCB fingerprint into the page buffer. */
+ memset(buffer, ~0, mtd->writesize);
+- memset(chip->oob_poi, ~0, mtd->oobsize);
+ memcpy(buffer + 12, fingerprint, strlen(fingerprint));
+
+ /* Loop through the first search area, writing NCB fingerprints. */
+@@ -1446,7 +1513,7 @@
+ /* Set up the NFC geometry which is used by BCH. */
+ ret = bch_set_geometry(this);
+ if (ret) {
+- pr_err("Error setting BCH geometry : %d\n", ret);
++ dev_err(this->dev, "Error setting BCH geometry : %d\n", ret);
+ return ret;
+ }
+
+@@ -1454,40 +1521,37 @@
+ return gpmi_alloc_dma_buffer(this);
+ }
+
+-static int gpmi_pre_bbt_scan(struct gpmi_nand_data *this)
++static void gpmi_nand_exit(struct gpmi_nand_data *this)
++{
++ nand_release(&this->mtd);
++ gpmi_free_dma_buffer(this);
++}
++
++static int gpmi_init_last(struct gpmi_nand_data *this)
+ {
++ struct mtd_info *mtd = &this->mtd;
++ struct nand_chip *chip = mtd->priv;
++ struct nand_ecc_ctrl *ecc = &chip->ecc;
++ struct bch_geometry *bch_geo = &this->bch_geometry;
+ int ret;
+
+ /* Set up swap_block_mark, must be set before the gpmi_set_geometry() */
+- if (GPMI_IS_MX23(this))
+- this->swap_block_mark = false;
+- else
+- this->swap_block_mark = true;
++ this->swap_block_mark = !GPMI_IS_MX23(this);
+
+ /* Set up the medium geometry */
+ ret = gpmi_set_geometry(this);
+ if (ret)
+ return ret;
+
+- /* Adjust the ECC strength according to the chip. */
+- this->nand.ecc.strength = this->bch_geometry.ecc_strength;
+- this->mtd.ecc_strength = this->bch_geometry.ecc_strength;
+- this->mtd.bitflip_threshold = this->bch_geometry.ecc_strength;
+-
+- /* NAND boot init, depends on the gpmi_set_geometry(). */
+- return nand_boot_init(this);
+-}
+-
+-static int gpmi_scan_bbt(struct mtd_info *mtd)
+-{
+- struct nand_chip *chip = mtd->priv;
+- struct gpmi_nand_data *this = chip->priv;
+- int ret;
+-
+- /* Prepare for the BBT scan. */
+- ret = gpmi_pre_bbt_scan(this);
+- if (ret)
+- return ret;
++ /* Init the nand_ecc_ctrl{} */
++ ecc->read_page = gpmi_ecc_read_page;
++ ecc->write_page = gpmi_ecc_write_page;
++ ecc->read_oob = gpmi_ecc_read_oob;
++ ecc->write_oob = gpmi_ecc_write_oob;
++ ecc->mode = NAND_ECC_HW;
++ ecc->size = bch_geo->ecc_chunk_size;
++ ecc->strength = bch_geo->ecc_strength;
++ ecc->layout = &gpmi_hw_ecclayout;
+
+ /*
+ * Can we enable the extra features? such as EDO or Sync mode.
+@@ -1497,17 +1561,10 @@
+ */
+ gpmi_extra_init(this);
+
+- /* use the default BBT implementation */
+- return nand_default_bbt(mtd);
+-}
+-
+-static void gpmi_nfc_exit(struct gpmi_nand_data *this)
+-{
+- nand_release(&this->mtd);
+- gpmi_free_dma_buffer(this);
++ return 0;
+ }
+
+-static int gpmi_nfc_init(struct gpmi_nand_data *this)
++static int gpmi_nand_init(struct gpmi_nand_data *this)
+ {
+ struct mtd_info *mtd = &this->mtd;
+ struct nand_chip *chip = &this->nand;
+@@ -1530,33 +1587,39 @@
+ chip->read_byte = gpmi_read_byte;
+ chip->read_buf = gpmi_read_buf;
+ chip->write_buf = gpmi_write_buf;
+- chip->ecc.read_page = gpmi_ecc_read_page;
+- chip->ecc.write_page = gpmi_ecc_write_page;
+- chip->ecc.read_oob = gpmi_ecc_read_oob;
+- chip->ecc.write_oob = gpmi_ecc_write_oob;
+- chip->scan_bbt = gpmi_scan_bbt;
+ chip->badblock_pattern = &gpmi_bbt_descr;
+ chip->block_markbad = gpmi_block_markbad;
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
+- chip->ecc.mode = NAND_ECC_HW;
+- chip->ecc.size = 1;
+- chip->ecc.strength = 8;
+- chip->ecc.layout = &gpmi_hw_ecclayout;
+ if (of_get_nand_on_flash_bbt(this->dev->of_node))
+ chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
+
+- /* Allocate a temporary DMA buffer for reading ID in the nand_scan() */
++ /*
++ * Allocate a temporary DMA buffer for reading ID in the
++ * nand_scan_ident().
++ */
+ this->bch_geometry.payload_size = 1024;
+ this->bch_geometry.auxiliary_size = 128;
+ ret = gpmi_alloc_dma_buffer(this);
+ if (ret)
+ goto err_out;
+
+- ret = nand_scan(mtd, 1);
+- if (ret) {
+- pr_err("Chip scan failed\n");
++ ret = nand_scan_ident(mtd, GPMI_IS_MX6Q(this) ? 2 : 1, NULL);
++ if (ret)
++ goto err_out;
++
++ ret = gpmi_init_last(this);
++ if (ret)
+ goto err_out;
+- }
++
++ chip->options |= NAND_SKIP_BBTSCAN;
++ ret = nand_scan_tail(mtd);
++ if (ret)
++ goto err_out;
++
++ ret = nand_boot_init(this);
++ if (ret)
++ goto err_out;
++ chip->scan_bbt(mtd);
+
+ ppdata.of_node = this->pdev->dev.of_node;
+ ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
+@@ -1565,7 +1628,7 @@
+ return 0;
+
+ err_out:
+- gpmi_nfc_exit(this);
++ gpmi_nand_exit(this);
+ return ret;
+ }
+
+@@ -1573,19 +1636,19 @@
+ { .name = "imx23-gpmi-nand", .driver_data = IS_MX23, },
+ { .name = "imx28-gpmi-nand", .driver_data = IS_MX28, },
+ { .name = "imx6q-gpmi-nand", .driver_data = IS_MX6Q, },
+- {},
++ {}
+ };
+
+ static const struct of_device_id gpmi_nand_id_table[] = {
+ {
+ .compatible = "fsl,imx23-gpmi-nand",
+- .data = (void *)&gpmi_ids[IS_MX23]
++ .data = (void *)&gpmi_ids[IS_MX23],
+ }, {
+ .compatible = "fsl,imx28-gpmi-nand",
+- .data = (void *)&gpmi_ids[IS_MX28]
++ .data = (void *)&gpmi_ids[IS_MX28],
+ }, {
+ .compatible = "fsl,imx6q-gpmi-nand",
+- .data = (void *)&gpmi_ids[IS_MX6Q]
++ .data = (void *)&gpmi_ids[IS_MX6Q],
+ }, {}
+ };
+ MODULE_DEVICE_TABLE(of, gpmi_nand_id_table);
+@@ -1600,15 +1663,13 @@
+ if (of_id) {
+ pdev->id_entry = of_id->data;
+ } else {
+- pr_err("Failed to find the right device id.\n");
+- return -ENOMEM;
++ dev_err(&pdev->dev, "Failed to find the right device id.\n");
++ return -ENODEV;
+ }
+
+- this = kzalloc(sizeof(*this), GFP_KERNEL);
+- if (!this) {
+- pr_err("Failed to allocate per-device memory\n");
++ this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
++ if (!this)
+ return -ENOMEM;
+- }
+
+ platform_set_drvdata(pdev, this);
+ this->pdev = pdev;
+@@ -1622,7 +1683,7 @@
+ if (ret)
+ goto exit_nfc_init;
+
+- ret = gpmi_nfc_init(this);
++ ret = gpmi_nand_init(this);
+ if (ret)
+ goto exit_nfc_init;
+
+@@ -1633,9 +1694,7 @@
+ exit_nfc_init:
+ release_resources(this);
+ exit_acquire_resources:
+- platform_set_drvdata(pdev, NULL);
+ dev_err(this->dev, "driver registration failed: %d\n", ret);
+- kfree(this);
+
+ return ret;
+ }
+@@ -1644,10 +1703,8 @@
+ {
+ struct gpmi_nand_data *this = platform_get_drvdata(pdev);
+
+- gpmi_nfc_exit(this);
++ gpmi_nand_exit(this);
+ release_resources(this);
+- platform_set_drvdata(pdev, NULL);
+- kfree(this);
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/gpmi-nand/gpmi-nand.h linux-linaro-stable-mx6/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+--- linux-3.10.30.orig/drivers/mtd/nand/gpmi-nand/gpmi-nand.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/gpmi-nand/gpmi-nand.h 2014-05-15 20:33:58.426016950 +0200
+@@ -26,8 +26,6 @@
+ struct resources {
+ void __iomem *gpmi_regs;
+ void __iomem *bch_regs;
+- unsigned int bch_low_interrupt;
+- unsigned int bch_high_interrupt;
+ unsigned int dma_low_channel;
+ unsigned int dma_high_channel;
+ struct clk *clock[GPMI_CLK_MAX];
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/gpmi-nand/gpmi-regs.h linux-linaro-stable-mx6/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
+--- linux-3.10.30.orig/drivers/mtd/nand/gpmi-nand/gpmi-regs.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/gpmi-nand/gpmi-regs.h 2014-05-15 20:33:58.426016950 +0200
+@@ -108,6 +108,9 @@
+ #define HW_GPMI_CTRL1_CLR 0x00000068
+ #define HW_GPMI_CTRL1_TOG 0x0000006c
+
++#define BP_GPMI_CTRL1_DECOUPLE_CS 24
++#define BM_GPMI_CTRL1_DECOUPLE_CS (1 << BP_GPMI_CTRL1_DECOUPLE_CS)
++
+ #define BP_GPMI_CTRL1_WRN_DLY_SEL 22
+ #define BM_GPMI_CTRL1_WRN_DLY_SEL (0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL)
+ #define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/nand_base.c linux-linaro-stable-mx6/drivers/mtd/nand/nand_base.c
+--- linux-3.10.30.orig/drivers/mtd/nand/nand_base.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/nand_base.c 2014-05-15 20:33:58.430016978 +0200
+@@ -108,13 +108,13 @@
+ int ret = 0;
+
+ /* Start address must align on block boundary */
+- if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
++ if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
+ pr_debug("%s: unaligned address\n", __func__);
+ ret = -EINVAL;
+ }
+
+ /* Length must align on block boundary */
+- if (len & ((1 << chip->phys_erase_shift) - 1)) {
++ if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
+ pr_debug("%s: length not block aligned\n", __func__);
+ ret = -EINVAL;
+ }
+@@ -211,11 +211,9 @@
+ */
+ static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+ {
+- int i;
+ struct nand_chip *chip = mtd->priv;
+
+- for (i = 0; i < len; i++)
+- writeb(buf[i], chip->IO_ADDR_W);
++ iowrite8_rep(chip->IO_ADDR_W, buf, len);
+ }
+
+ /**
+@@ -228,11 +226,9 @@
+ */
+ static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+ {
+- int i;
+ struct nand_chip *chip = mtd->priv;
+
+- for (i = 0; i < len; i++)
+- buf[i] = readb(chip->IO_ADDR_R);
++ ioread8_rep(chip->IO_ADDR_R, buf, len);
+ }
+
+ /**
+@@ -245,14 +241,10 @@
+ */
+ static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
+ {
+- int i;
+ struct nand_chip *chip = mtd->priv;
+ u16 *p = (u16 *) buf;
+- len >>= 1;
+-
+- for (i = 0; i < len; i++)
+- writew(p[i], chip->IO_ADDR_W);
+
++ iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
+ }
+
+ /**
+@@ -265,13 +257,10 @@
+ */
+ static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
+ {
+- int i;
+ struct nand_chip *chip = mtd->priv;
+ u16 *p = (u16 *) buf;
+- len >>= 1;
+
+- for (i = 0; i < len; i++)
+- p[i] = readw(chip->IO_ADDR_R);
++ ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
+ }
+
+ /**
+@@ -335,80 +324,88 @@
+ }
+
+ /**
+- * nand_default_block_markbad - [DEFAULT] mark a block bad
++ * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
+ * @mtd: MTD device structure
+ * @ofs: offset from device start
+ *
+ * This is the default implementation, which can be overridden by a hardware
+- * specific driver. We try operations in the following order, according to our
+- * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
++ * specific driver. It provides the details for writing a bad block marker to a
++ * block.
++ */
++static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
++{
++ struct nand_chip *chip = mtd->priv;
++ struct mtd_oob_ops ops;
++ uint8_t buf[2] = { 0, 0 };
++ int ret = 0, res, i = 0;
++
++ ops.datbuf = NULL;
++ ops.oobbuf = buf;
++ ops.ooboffs = chip->badblockpos;
++ if (chip->options & NAND_BUSWIDTH_16) {
++ ops.ooboffs &= ~0x01;
++ ops.len = ops.ooblen = 2;
++ } else {
++ ops.len = ops.ooblen = 1;
++ }
++ ops.mode = MTD_OPS_PLACE_OOB;
++
++ /* Write to first/last page(s) if necessary */
++ if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
++ ofs += mtd->erasesize - mtd->writesize;
++ do {
++ res = nand_do_write_oob(mtd, ofs, &ops);
++ if (!ret)
++ ret = res;
++
++ i++;
++ ofs += mtd->writesize;
++ } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
++
++ return ret;
++}
++
++/**
++ * nand_block_markbad_lowlevel - mark a block bad
++ * @mtd: MTD device structure
++ * @ofs: offset from device start
++ *
++ * This function performs the generic NAND bad block marking steps (i.e., bad
++ * block table(s) and/or marker(s)). We only allow the hardware driver to
++ * specify how to write bad block markers to OOB (chip->block_markbad).
++ *
++ * We try operations in the following order:
+ * (1) erase the affected block, to allow OOB marker to be written cleanly
+- * (2) update in-memory BBT
+- * (3) write bad block marker to OOB area of affected block
+- * (4) update flash-based BBT
+- * Note that we retain the first error encountered in (3) or (4), finish the
++ * (2) write bad block marker to OOB area of affected block (unless flag
++ * NAND_BBT_NO_OOB_BBM is present)
++ * (3) update the BBT
++ * Note that we retain the first error encountered in (2) or (3), finish the
+ * procedures, and dump the error in the end.
+ */
+-static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
++static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
+ {
+ struct nand_chip *chip = mtd->priv;
+- uint8_t buf[2] = { 0, 0 };
+- int block, res, ret = 0, i = 0;
+- int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
++ int res, ret = 0;
+
+- if (write_oob) {
++ if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
+ struct erase_info einfo;
+
+ /* Attempt erase before marking OOB */
+ memset(&einfo, 0, sizeof(einfo));
+ einfo.mtd = mtd;
+ einfo.addr = ofs;
+- einfo.len = 1 << chip->phys_erase_shift;
++ einfo.len = 1ULL << chip->phys_erase_shift;
+ nand_erase_nand(mtd, &einfo, 0);
+- }
+-
+- /* Get block number */
+- block = (int)(ofs >> chip->bbt_erase_shift);
+- /* Mark block bad in memory-based BBT */
+- if (chip->bbt)
+- chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
+-
+- /* Write bad block marker to OOB */
+- if (write_oob) {
+- struct mtd_oob_ops ops;
+- loff_t wr_ofs = ofs;
+
++ /* Write bad block marker to OOB */
+ nand_get_device(mtd, FL_WRITING);
+-
+- ops.datbuf = NULL;
+- ops.oobbuf = buf;
+- ops.ooboffs = chip->badblockpos;
+- if (chip->options & NAND_BUSWIDTH_16) {
+- ops.ooboffs &= ~0x01;
+- ops.len = ops.ooblen = 2;
+- } else {
+- ops.len = ops.ooblen = 1;
+- }
+- ops.mode = MTD_OPS_PLACE_OOB;
+-
+- /* Write to first/last page(s) if necessary */
+- if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
+- wr_ofs += mtd->erasesize - mtd->writesize;
+- do {
+- res = nand_do_write_oob(mtd, wr_ofs, &ops);
+- if (!ret)
+- ret = res;
+-
+- i++;
+- wr_ofs += mtd->writesize;
+- } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
+-
++ ret = chip->block_markbad(mtd, ofs);
+ nand_release_device(mtd);
+ }
+
+- /* Update flash-based bad block table */
+- if (chip->bbt_options & NAND_BBT_USE_FLASH) {
+- res = nand_update_bbt(mtd, ofs);
++ /* Mark block bad in BBT */
++ if (chip->bbt) {
++ res = nand_markbad_bbt(mtd, ofs);
+ if (!ret)
+ ret = res;
+ }
+@@ -1983,13 +1980,14 @@
+ * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
+ * @mtd: mtd info structure
+ * @chip: nand chip info structure
+- * @column: column address of subpage within the page
++ * @offset: column address of subpage within the page
+ * @data_len: data length
++ * @buf: data buffer
+ * @oob_required: must write chip->oob_poi to OOB
+ */
+ static int nand_write_subpage_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, uint32_t offset,
+- uint32_t data_len, const uint8_t *data_buf,
++ uint32_t data_len, const uint8_t *buf,
+ int oob_required)
+ {
+ uint8_t *oob_buf = chip->oob_poi;
+@@ -2008,20 +2006,20 @@
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+
+ /* write data (untouched subpages already masked by 0xFF) */
+- chip->write_buf(mtd, data_buf, ecc_size);
++ chip->write_buf(mtd, buf, ecc_size);
+
+ /* mask ECC of un-touched subpages by padding 0xFF */
+ if ((step < start_step) || (step > end_step))
+ memset(ecc_calc, 0xff, ecc_bytes);
+ else
+- chip->ecc.calculate(mtd, data_buf, ecc_calc);
++ chip->ecc.calculate(mtd, buf, ecc_calc);
+
+ /* mask OOB of un-touched subpages by padding 0xFF */
+ /* if oob_required, preserve OOB metadata of written subpage */
+ if (!oob_required || (step < start_step) || (step > end_step))
+ memset(oob_buf, 0xff, oob_bytes);
+
+- data_buf += ecc_size;
++ buf += ecc_size;
+ ecc_calc += ecc_bytes;
+ oob_buf += oob_bytes;
+ }
+@@ -2633,7 +2631,7 @@
+ }
+
+ /* Increment page address and decrement length */
+- len -= (1 << chip->phys_erase_shift);
++ len -= (1ULL << chip->phys_erase_shift);
+ page += pages_per_block;
+
+ /* Check, if we cross a chip boundary */
+@@ -2694,7 +2692,6 @@
+ */
+ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
+ {
+- struct nand_chip *chip = mtd->priv;
+ int ret;
+
+ ret = nand_block_isbad(mtd, ofs);
+@@ -2705,7 +2702,7 @@
+ return ret;
+ }
+
+- return chip->block_markbad(mtd, ofs);
++ return nand_block_markbad_lowlevel(mtd, ofs);
+ }
+
+ /**
+@@ -2720,7 +2717,9 @@
+ {
+ int status;
+
+- if (!chip->onfi_version)
++ if (!chip->onfi_version ||
++ !(le16_to_cpu(chip->onfi_params.opt_cmd)
++ & ONFI_OPT_CMD_SET_GET_FEATURES))
+ return -EINVAL;
+
+ chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
+@@ -2741,7 +2740,9 @@
+ static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
+ int addr, uint8_t *subfeature_param)
+ {
+- if (!chip->onfi_version)
++ if (!chip->onfi_version ||
++ !(le16_to_cpu(chip->onfi_params.opt_cmd)
++ & ONFI_OPT_CMD_SET_GET_FEATURES))
+ return -EINVAL;
+
+ /* clear the sub feature parameters */
+@@ -2794,6 +2795,12 @@
+ if (!chip->select_chip)
+ chip->select_chip = nand_select_chip;
+
++ /* set for ONFI nand */
++ if (!chip->onfi_set_features)
++ chip->onfi_set_features = nand_onfi_set_features;
++ if (!chip->onfi_get_features)
++ chip->onfi_get_features = nand_onfi_get_features;
++
+ /* If called twice, pointers that depend on busw may need to be reset */
+ if (!chip->read_byte || chip->read_byte == nand_read_byte)
+ chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
+@@ -2848,6 +2855,77 @@
+ return crc;
+ }
+
++/* Parse the Extended Parameter Page. */
++static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
++ struct nand_chip *chip, struct nand_onfi_params *p)
++{
++ struct onfi_ext_param_page *ep;
++ struct onfi_ext_section *s;
++ struct onfi_ext_ecc_info *ecc;
++ uint8_t *cursor;
++ int ret = -EINVAL;
++ int len;
++ int i;
++
++ len = le16_to_cpu(p->ext_param_page_length) * 16;
++ ep = kmalloc(len, GFP_KERNEL);
++ if (!ep)
++ return -ENOMEM;
++
++ /* Send our own NAND_CMD_PARAM. */
++ chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
++
++ /* Use the Change Read Column command to skip the ONFI param pages. */
++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
++ sizeof(*p) * p->num_of_param_pages , -1);
++
++ /* Read out the Extended Parameter Page. */
++ chip->read_buf(mtd, (uint8_t *)ep, len);
++ if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
++ != le16_to_cpu(ep->crc))) {
++ pr_debug("fail in the CRC.\n");
++ goto ext_out;
++ }
++
++ /*
++ * Check the signature.
++ * Do not strictly follow the ONFI spec, maybe changed in future.
++ */
++ if (strncmp(ep->sig, "EPPS", 4)) {
++ pr_debug("The signature is invalid.\n");
++ goto ext_out;
++ }
++
++ /* find the ECC section. */
++ cursor = (uint8_t *)(ep + 1);
++ for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
++ s = ep->sections + i;
++ if (s->type == ONFI_SECTION_TYPE_2)
++ break;
++ cursor += s->length * 16;
++ }
++ if (i == ONFI_EXT_SECTION_MAX) {
++ pr_debug("We can not find the ECC section.\n");
++ goto ext_out;
++ }
++
++ /* get the info we want. */
++ ecc = (struct onfi_ext_ecc_info *)cursor;
++
++ if (!ecc->codeword_size) {
++ pr_debug("Invalid codeword size\n");
++ goto ext_out;
++ }
++
++ chip->ecc_strength_ds = ecc->ecc_bits;
++ chip->ecc_step_ds = 1 << ecc->codeword_size;
++ ret = 0;
++
++ext_out:
++ kfree(ep);
++ return ret;
++}
++
+ /*
+ * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
+ */
+@@ -2858,29 +2936,34 @@
+ int i;
+ int val;
+
+- /* ONFI need to be probed in 8 bits mode, and 16 bits should be selected with NAND_BUSWIDTH_AUTO */
+- if (chip->options & NAND_BUSWIDTH_16) {
+- pr_err("Trying ONFI probe in 16 bits mode, aborting !\n");
+- return 0;
+- }
+ /* Try ONFI for unknown chip or LP */
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+ if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
+ chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
+ return 0;
+
++ /*
++ * ONFI must be probed in 8-bit mode or with NAND_BUSWIDTH_AUTO, not
++ * with NAND_BUSWIDTH_16
++ */
++ if (chip->options & NAND_BUSWIDTH_16) {
++ pr_err("ONFI cannot be probed in 16-bit mode; aborting\n");
++ return 0;
++ }
++
+ chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+ for (i = 0; i < 3; i++) {
+ chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
+ if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
+ le16_to_cpu(p->crc)) {
+- pr_info("ONFI param page %d valid\n", i);
+ break;
+ }
+ }
+
+- if (i == 3)
++ if (i == 3) {
++ pr_err("Could not find valid ONFI parameter page; aborting\n");
+ return 0;
++ }
+
+ /* Check version */
+ val = le16_to_cpu(p->revision);
+@@ -2920,11 +3003,35 @@
+ /* See erasesize comment */
+ chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
+ chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
+- *busw = 0;
+- if (le16_to_cpu(p->features) & 1)
++ chip->bits_per_cell = p->bits_per_cell;
++
++ if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
+ *busw = NAND_BUSWIDTH_16;
++ else
++ *busw = 0;
++
++ if (p->ecc_bits != 0xff) {
++ chip->ecc_strength_ds = p->ecc_bits;
++ chip->ecc_step_ds = 512;
++ } else if (chip->onfi_version >= 21 &&
++ (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
++
++ /*
++ * The nand_flash_detect_ext_param_page() uses the
++ * Change Read Column command which maybe not supported
++ * by the chip->cmdfunc. So try to update the chip->cmdfunc
++ * now. We do not replace user supplied command function.
++ */
++ if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
++ chip->cmdfunc = nand_command_lp;
++
++ /* The Extended Parameter Page is supported since ONFI 2.1. */
++ if (nand_flash_detect_ext_param_page(mtd, chip, p))
++ pr_warn("Failed to detect ONFI extended param page\n");
++ } else {
++ pr_warn("Could not retrieve ONFI ECC requirements\n");
++ }
+
+- pr_info("ONFI flash detected\n");
+ return 1;
+ }
+
+@@ -2987,6 +3094,16 @@
+ return arrlen;
+ }
+
++/* Extract the bits of per cell from the 3rd byte of the extended ID */
++static int nand_get_bits_per_cell(u8 cellinfo)
++{
++ int bits;
++
++ bits = cellinfo & NAND_CI_CELLTYPE_MSK;
++ bits >>= NAND_CI_CELLTYPE_SHIFT;
++ return bits + 1;
++}
++
+ /*
+ * Many new NAND share similar device ID codes, which represent the size of the
+ * chip. The rest of the parameters must be decoded according to generic or
+@@ -2997,7 +3114,7 @@
+ {
+ int extid, id_len;
+ /* The 3rd id byte holds MLC / multichip data */
+- chip->cellinfo = id_data[2];
++ chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
+ /* The 4th id byte is the important one */
+ extid = id_data[3];
+
+@@ -3013,8 +3130,7 @@
+ * ID to decide what to do.
+ */
+ if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
+- (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+- id_data[5] != 0x00) {
++ !nand_is_slc(chip) && id_data[5] != 0x00) {
+ /* Calc pagesize */
+ mtd->writesize = 2048 << (extid & 0x03);
+ extid >>= 2;
+@@ -3046,7 +3162,7 @@
+ (((extid >> 1) & 0x04) | (extid & 0x03));
+ *busw = 0;
+ } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
+- (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
++ !nand_is_slc(chip)) {
+ unsigned int tmp;
+
+ /* Calc pagesize */
+@@ -3099,6 +3215,22 @@
+ extid >>= 2;
+ /* Get buswidth information */
+ *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
++
++ /*
++ * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
++ * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
++ * follows:
++ * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
++ * 110b -> 24nm
++ * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
++ */
++ if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
++ nand_is_slc(chip) &&
++ (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
++ !(id_data[4] & 0x80) /* !BENAND */) {
++ mtd->oobsize = 32 * mtd->writesize >> 9;
++ }
++
+ }
+ }
+
+@@ -3118,6 +3250,9 @@
+ mtd->oobsize = mtd->writesize / 32;
+ *busw = type->options & NAND_BUSWIDTH_16;
+
++ /* All legacy ID NAND are small-page, SLC */
++ chip->bits_per_cell = 1;
++
+ /*
+ * Check for Spansion/AMD ID + repeating 5th, 6th byte since
+ * some Spansion chips have erasesize that conflicts with size
+@@ -3154,11 +3289,11 @@
+ * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
+ * AMD/Spansion, and Macronix. All others scan only the first page.
+ */
+- if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
++ if (!nand_is_slc(chip) &&
+ (maf_id == NAND_MFR_SAMSUNG ||
+ maf_id == NAND_MFR_HYNIX))
+ chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
+- else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
++ else if ((nand_is_slc(chip) &&
+ (maf_id == NAND_MFR_SAMSUNG ||
+ maf_id == NAND_MFR_HYNIX ||
+ maf_id == NAND_MFR_TOSHIBA ||
+@@ -3182,9 +3317,11 @@
+ mtd->erasesize = type->erasesize;
+ mtd->oobsize = type->oobsize;
+
+- chip->cellinfo = id_data[2];
++ chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
+ chip->chipsize = (uint64_t)type->chipsize << 20;
+ chip->options |= type->options;
++ chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
++ chip->ecc_step_ds = NAND_ECC_STEP(type);
+
+ *busw = type->options & NAND_BUSWIDTH_16;
+
+@@ -3335,11 +3472,13 @@
+ if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
+ chip->cmdfunc = nand_command_lp;
+
+- pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
+- " %dMiB, page size: %d, OOB size: %d\n",
++ pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s)\n",
+ *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
+- chip->onfi_version ? chip->onfi_params.model : type->name,
+- (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
++ chip->onfi_version ? chip->onfi_params.model : type->name);
++
++ pr_info("NAND device: %dMiB, %s, page size: %d, OOB size: %d\n",
++ (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
++ mtd->writesize, mtd->oobsize);
+
+ return type;
+ }
+@@ -3419,6 +3558,7 @@
+ {
+ int i;
+ struct nand_chip *chip = mtd->priv;
++ struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+ /* New bad blocks should be marked in OOB, flash-based BBT, or both */
+ BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
+@@ -3435,19 +3575,19 @@
+ /*
+ * If no default placement scheme is given, select an appropriate one.
+ */
+- if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
++ if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
+ switch (mtd->oobsize) {
+ case 8:
+- chip->ecc.layout = &nand_oob_8;
++ ecc->layout = &nand_oob_8;
+ break;
+ case 16:
+- chip->ecc.layout = &nand_oob_16;
++ ecc->layout = &nand_oob_16;
+ break;
+ case 64:
+- chip->ecc.layout = &nand_oob_64;
++ ecc->layout = &nand_oob_64;
+ break;
+ case 128:
+- chip->ecc.layout = &nand_oob_128;
++ ecc->layout = &nand_oob_128;
+ break;
+ default:
+ pr_warn("No oob scheme defined for oobsize %d\n",
+@@ -3459,75 +3599,67 @@
+ if (!chip->write_page)
+ chip->write_page = nand_write_page;
+
+- /* set for ONFI nand */
+- if (!chip->onfi_set_features)
+- chip->onfi_set_features = nand_onfi_set_features;
+- if (!chip->onfi_get_features)
+- chip->onfi_get_features = nand_onfi_get_features;
+-
+ /*
+ * Check ECC mode, default to software if 3byte/512byte hardware ECC is
+ * selected and we have 256 byte pagesize fallback to software ECC
+ */
+
+- switch (chip->ecc.mode) {
++ switch (ecc->mode) {
+ case NAND_ECC_HW_OOB_FIRST:
+ /* Similar to NAND_ECC_HW, but a separate read_page handle */
+- if (!chip->ecc.calculate || !chip->ecc.correct ||
+- !chip->ecc.hwctl) {
++ if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
+ pr_warn("No ECC functions supplied; "
+ "hardware ECC not possible\n");
+ BUG();
+ }
+- if (!chip->ecc.read_page)
+- chip->ecc.read_page = nand_read_page_hwecc_oob_first;
++ if (!ecc->read_page)
++ ecc->read_page = nand_read_page_hwecc_oob_first;
+
+ case NAND_ECC_HW:
+ /* Use standard hwecc read page function? */
+- if (!chip->ecc.read_page)
+- chip->ecc.read_page = nand_read_page_hwecc;
+- if (!chip->ecc.write_page)
+- chip->ecc.write_page = nand_write_page_hwecc;
+- if (!chip->ecc.read_page_raw)
+- chip->ecc.read_page_raw = nand_read_page_raw;
+- if (!chip->ecc.write_page_raw)
+- chip->ecc.write_page_raw = nand_write_page_raw;
+- if (!chip->ecc.read_oob)
+- chip->ecc.read_oob = nand_read_oob_std;
+- if (!chip->ecc.write_oob)
+- chip->ecc.write_oob = nand_write_oob_std;
+- if (!chip->ecc.read_subpage)
+- chip->ecc.read_subpage = nand_read_subpage;
+- if (!chip->ecc.write_subpage)
+- chip->ecc.write_subpage = nand_write_subpage_hwecc;
++ if (!ecc->read_page)
++ ecc->read_page = nand_read_page_hwecc;
++ if (!ecc->write_page)
++ ecc->write_page = nand_write_page_hwecc;
++ if (!ecc->read_page_raw)
++ ecc->read_page_raw = nand_read_page_raw;
++ if (!ecc->write_page_raw)
++ ecc->write_page_raw = nand_write_page_raw;
++ if (!ecc->read_oob)
++ ecc->read_oob = nand_read_oob_std;
++ if (!ecc->write_oob)
++ ecc->write_oob = nand_write_oob_std;
++ if (!ecc->read_subpage)
++ ecc->read_subpage = nand_read_subpage;
++ if (!ecc->write_subpage)
++ ecc->write_subpage = nand_write_subpage_hwecc;
+
+ case NAND_ECC_HW_SYNDROME:
+- if ((!chip->ecc.calculate || !chip->ecc.correct ||
+- !chip->ecc.hwctl) &&
+- (!chip->ecc.read_page ||
+- chip->ecc.read_page == nand_read_page_hwecc ||
+- !chip->ecc.write_page ||
+- chip->ecc.write_page == nand_write_page_hwecc)) {
++ if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
++ (!ecc->read_page ||
++ ecc->read_page == nand_read_page_hwecc ||
++ !ecc->write_page ||
++ ecc->write_page == nand_write_page_hwecc)) {
+ pr_warn("No ECC functions supplied; "
+ "hardware ECC not possible\n");
+ BUG();
+ }
+ /* Use standard syndrome read/write page function? */
+- if (!chip->ecc.read_page)
+- chip->ecc.read_page = nand_read_page_syndrome;
+- if (!chip->ecc.write_page)
+- chip->ecc.write_page = nand_write_page_syndrome;
+- if (!chip->ecc.read_page_raw)
+- chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
+- if (!chip->ecc.write_page_raw)
+- chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
+- if (!chip->ecc.read_oob)
+- chip->ecc.read_oob = nand_read_oob_syndrome;
+- if (!chip->ecc.write_oob)
+- chip->ecc.write_oob = nand_write_oob_syndrome;
++ if (!ecc->read_page)
++ ecc->read_page = nand_read_page_syndrome;
++ if (!ecc->write_page)
++ ecc->write_page = nand_write_page_syndrome;
++ if (!ecc->read_page_raw)
++ ecc->read_page_raw = nand_read_page_raw_syndrome;
++ if (!ecc->write_page_raw)
++ ecc->write_page_raw = nand_write_page_raw_syndrome;
++ if (!ecc->read_oob)
++ ecc->read_oob = nand_read_oob_syndrome;
++ if (!ecc->write_oob)
++ ecc->write_oob = nand_write_oob_syndrome;
+
+- if (mtd->writesize >= chip->ecc.size) {
+- if (!chip->ecc.strength) {
++ if (mtd->writesize >= ecc->size) {
++ if (!ecc->strength) {
+ pr_warn("Driver must set ecc.strength when using hardware ECC\n");
+ BUG();
+ }
+@@ -3535,23 +3667,23 @@
+ }
+ pr_warn("%d byte HW ECC not possible on "
+ "%d byte page size, fallback to SW ECC\n",
+- chip->ecc.size, mtd->writesize);
+- chip->ecc.mode = NAND_ECC_SOFT;
++ ecc->size, mtd->writesize);
++ ecc->mode = NAND_ECC_SOFT;
+
+ case NAND_ECC_SOFT:
+- chip->ecc.calculate = nand_calculate_ecc;
+- chip->ecc.correct = nand_correct_data;
+- chip->ecc.read_page = nand_read_page_swecc;
+- chip->ecc.read_subpage = nand_read_subpage;
+- chip->ecc.write_page = nand_write_page_swecc;
+- chip->ecc.read_page_raw = nand_read_page_raw;
+- chip->ecc.write_page_raw = nand_write_page_raw;
+- chip->ecc.read_oob = nand_read_oob_std;
+- chip->ecc.write_oob = nand_write_oob_std;
+- if (!chip->ecc.size)
+- chip->ecc.size = 256;
+- chip->ecc.bytes = 3;
+- chip->ecc.strength = 1;
++ ecc->calculate = nand_calculate_ecc;
++ ecc->correct = nand_correct_data;
++ ecc->read_page = nand_read_page_swecc;
++ ecc->read_subpage = nand_read_subpage;
++ ecc->write_page = nand_write_page_swecc;
++ ecc->read_page_raw = nand_read_page_raw;
++ ecc->write_page_raw = nand_write_page_raw;
++ ecc->read_oob = nand_read_oob_std;
++ ecc->write_oob = nand_write_oob_std;
++ if (!ecc->size)
++ ecc->size = 256;
++ ecc->bytes = 3;
++ ecc->strength = 1;
+ break;
+
+ case NAND_ECC_SOFT_BCH:
+@@ -3559,88 +3691,83 @@
+ pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
+ BUG();
+ }
+- chip->ecc.calculate = nand_bch_calculate_ecc;
+- chip->ecc.correct = nand_bch_correct_data;
+- chip->ecc.read_page = nand_read_page_swecc;
+- chip->ecc.read_subpage = nand_read_subpage;
+- chip->ecc.write_page = nand_write_page_swecc;
+- chip->ecc.read_page_raw = nand_read_page_raw;
+- chip->ecc.write_page_raw = nand_write_page_raw;
+- chip->ecc.read_oob = nand_read_oob_std;
+- chip->ecc.write_oob = nand_write_oob_std;
++ ecc->calculate = nand_bch_calculate_ecc;
++ ecc->correct = nand_bch_correct_data;
++ ecc->read_page = nand_read_page_swecc;
++ ecc->read_subpage = nand_read_subpage;
++ ecc->write_page = nand_write_page_swecc;
++ ecc->read_page_raw = nand_read_page_raw;
++ ecc->write_page_raw = nand_write_page_raw;
++ ecc->read_oob = nand_read_oob_std;
++ ecc->write_oob = nand_write_oob_std;
+ /*
+ * Board driver should supply ecc.size and ecc.bytes values to
+ * select how many bits are correctable; see nand_bch_init()
+ * for details. Otherwise, default to 4 bits for large page
+ * devices.
+ */
+- if (!chip->ecc.size && (mtd->oobsize >= 64)) {
+- chip->ecc.size = 512;
+- chip->ecc.bytes = 7;
+- }
+- chip->ecc.priv = nand_bch_init(mtd,
+- chip->ecc.size,
+- chip->ecc.bytes,
+- &chip->ecc.layout);
+- if (!chip->ecc.priv) {
++ if (!ecc->size && (mtd->oobsize >= 64)) {
++ ecc->size = 512;
++ ecc->bytes = 7;
++ }
++ ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
++ &ecc->layout);
++ if (!ecc->priv) {
+ pr_warn("BCH ECC initialization failed!\n");
+ BUG();
+ }
+- chip->ecc.strength =
+- chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
++ ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
+ break;
+
+ case NAND_ECC_NONE:
+ pr_warn("NAND_ECC_NONE selected by board driver. "
+ "This is not recommended!\n");
+- chip->ecc.read_page = nand_read_page_raw;
+- chip->ecc.write_page = nand_write_page_raw;
+- chip->ecc.read_oob = nand_read_oob_std;
+- chip->ecc.read_page_raw = nand_read_page_raw;
+- chip->ecc.write_page_raw = nand_write_page_raw;
+- chip->ecc.write_oob = nand_write_oob_std;
+- chip->ecc.size = mtd->writesize;
+- chip->ecc.bytes = 0;
+- chip->ecc.strength = 0;
++ ecc->read_page = nand_read_page_raw;
++ ecc->write_page = nand_write_page_raw;
++ ecc->read_oob = nand_read_oob_std;
++ ecc->read_page_raw = nand_read_page_raw;
++ ecc->write_page_raw = nand_write_page_raw;
++ ecc->write_oob = nand_write_oob_std;
++ ecc->size = mtd->writesize;
++ ecc->bytes = 0;
++ ecc->strength = 0;
+ break;
+
+ default:
+- pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
++ pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
+ BUG();
+ }
+
+ /* For many systems, the standard OOB write also works for raw */
+- if (!chip->ecc.read_oob_raw)
+- chip->ecc.read_oob_raw = chip->ecc.read_oob;
+- if (!chip->ecc.write_oob_raw)
+- chip->ecc.write_oob_raw = chip->ecc.write_oob;
++ if (!ecc->read_oob_raw)
++ ecc->read_oob_raw = ecc->read_oob;
++ if (!ecc->write_oob_raw)
++ ecc->write_oob_raw = ecc->write_oob;
+
+ /*
+ * The number of bytes available for a client to place data into
+ * the out of band area.
+ */
+- chip->ecc.layout->oobavail = 0;
+- for (i = 0; chip->ecc.layout->oobfree[i].length
+- && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
+- chip->ecc.layout->oobavail +=
+- chip->ecc.layout->oobfree[i].length;
+- mtd->oobavail = chip->ecc.layout->oobavail;
++ ecc->layout->oobavail = 0;
++ for (i = 0; ecc->layout->oobfree[i].length
++ && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
++ ecc->layout->oobavail += ecc->layout->oobfree[i].length;
++ mtd->oobavail = ecc->layout->oobavail;
+
+ /*
+ * Set the number of read / write steps for one page depending on ECC
+ * mode.
+ */
+- chip->ecc.steps = mtd->writesize / chip->ecc.size;
+- if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
++ ecc->steps = mtd->writesize / ecc->size;
++ if (ecc->steps * ecc->size != mtd->writesize) {
+ pr_warn("Invalid ECC parameters\n");
+ BUG();
+ }
+- chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
++ ecc->total = ecc->steps * ecc->bytes;
+
+ /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
+- if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
+- !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
+- switch (chip->ecc.steps) {
++ if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
++ switch (ecc->steps) {
+ case 2:
+ mtd->subpage_sft = 1;
+ break;
+@@ -3660,11 +3787,11 @@
+ chip->pagebuf = -1;
+
+ /* Large page NAND with SOFT_ECC should support subpage reads */
+- if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
++ if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
+ chip->options |= NAND_SUBPAGE_READ;
+
+ /* Fill in remaining MTD driver data */
+- mtd->type = MTD_NANDFLASH;
++ mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
+ mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
+ MTD_CAP_NANDFLASH;
+ mtd->_erase = nand_erase;
+@@ -3685,8 +3812,9 @@
+ mtd->writebufsize = mtd->writesize;
+
+ /* propagate ecc info to mtd_info */
+- mtd->ecclayout = chip->ecc.layout;
+- mtd->ecc_strength = chip->ecc.strength;
++ mtd->ecclayout = ecc->layout;
++ mtd->ecc_strength = ecc->strength;
++ mtd->ecc_step_size = ecc->size;
+ /*
+ * Initialize bitflip_threshold to its default prior scan_bbt() call.
+ * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/nand_bbt.c linux-linaro-stable-mx6/drivers/mtd/nand/nand_bbt.c
+--- linux-3.10.30.orig/drivers/mtd/nand/nand_bbt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/nand_bbt.c 2014-05-15 20:33:58.430016978 +0200
+@@ -71,6 +71,30 @@
+ #include <linux/export.h>
+ #include <linux/string.h>
+
++#define BBT_BLOCK_GOOD 0x00
++#define BBT_BLOCK_WORN 0x01
++#define BBT_BLOCK_RESERVED 0x02
++#define BBT_BLOCK_FACTORY_BAD 0x03
++
++#define BBT_ENTRY_MASK 0x03
++#define BBT_ENTRY_SHIFT 2
++
++static int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
++
++static inline uint8_t bbt_get_entry(struct nand_chip *chip, int block)
++{
++ uint8_t entry = chip->bbt[block >> BBT_ENTRY_SHIFT];
++ entry >>= (block & BBT_ENTRY_MASK) * 2;
++ return entry & BBT_ENTRY_MASK;
++}
++
++static inline void bbt_mark_entry(struct nand_chip *chip, int block,
++ uint8_t mark)
++{
++ uint8_t msk = (mark & BBT_ENTRY_MASK) << ((block & BBT_ENTRY_MASK) * 2);
++ chip->bbt[block >> BBT_ENTRY_SHIFT] |= msk;
++}
++
+ static int check_pattern_no_oob(uint8_t *buf, struct nand_bbt_descr *td)
+ {
+ if (memcmp(buf, td->pattern, td->len))
+@@ -86,33 +110,17 @@
+ * @td: search pattern descriptor
+ *
+ * Check for a pattern at the given place. Used to search bad block tables and
+- * good / bad block identifiers. If the SCAN_EMPTY option is set then check, if
+- * all bytes except the pattern area contain 0xff.
++ * good / bad block identifiers.
+ */
+ static int check_pattern(uint8_t *buf, int len, int paglen, struct nand_bbt_descr *td)
+ {
+- int end = 0;
+- uint8_t *p = buf;
+-
+ if (td->options & NAND_BBT_NO_OOB)
+ return check_pattern_no_oob(buf, td);
+
+- end = paglen + td->offs;
+- if (td->options & NAND_BBT_SCANEMPTY)
+- if (memchr_inv(p, 0xff, end))
+- return -1;
+- p += end;
+-
+ /* Compare the pattern */
+- if (memcmp(p, td->pattern, td->len))
++ if (memcmp(buf + paglen + td->offs, td->pattern, td->len))
+ return -1;
+
+- if (td->options & NAND_BBT_SCANEMPTY) {
+- p += td->len;
+- end += td->len;
+- if (memchr_inv(p, 0xff, len - end))
+- return -1;
+- }
+ return 0;
+ }
+
+@@ -159,7 +167,7 @@
+ * @page: the starting page
+ * @num: the number of bbt descriptors to read
+ * @td: the bbt describtion table
+- * @offs: offset in the memory table
++ * @offs: block number offset in the table
+ *
+ * Read the bad block table starting from page.
+ */
+@@ -209,14 +217,16 @@
+ /* Analyse data */
+ for (i = 0; i < len; i++) {
+ uint8_t dat = buf[i];
+- for (j = 0; j < 8; j += bits, act += 2) {
++ for (j = 0; j < 8; j += bits, act++) {
+ uint8_t tmp = (dat >> j) & msk;
+ if (tmp == msk)
+ continue;
+ if (reserved_block_code && (tmp == reserved_block_code)) {
+ pr_info("nand_read_bbt: reserved block at 0x%012llx\n",
+- (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
+- this->bbt[offs + (act >> 3)] |= 0x2 << (act & 0x06);
++ (loff_t)(offs + act) <<
++ this->bbt_erase_shift);
++ bbt_mark_entry(this, offs + act,
++ BBT_BLOCK_RESERVED);
+ mtd->ecc_stats.bbtblocks++;
+ continue;
+ }
+@@ -225,12 +235,15 @@
+ * move this message to pr_debug.
+ */
+ pr_info("nand_read_bbt: bad block at 0x%012llx\n",
+- (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift);
++ (loff_t)(offs + act) <<
++ this->bbt_erase_shift);
+ /* Factory marked bad or worn out? */
+ if (tmp == 0)
+- this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06);
++ bbt_mark_entry(this, offs + act,
++ BBT_BLOCK_FACTORY_BAD);
+ else
+- this->bbt[offs + (act >> 3)] |= 0x1 << (act & 0x06);
++ bbt_mark_entry(this, offs + act,
++ BBT_BLOCK_WORN);
+ mtd->ecc_stats.badblocks++;
+ }
+ }
+@@ -265,7 +278,7 @@
+ td, offs);
+ if (res)
+ return res;
+- offs += this->chipsize >> (this->bbt_erase_shift + 2);
++ offs += this->chipsize >> this->bbt_erase_shift;
+ }
+ } else {
+ res = read_bbt(mtd, buf, td->pages[0],
+@@ -399,25 +412,6 @@
+ }
+ }
+
+-/* Scan a given block full */
+-static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd,
+- loff_t offs, uint8_t *buf, size_t readlen,
+- int scanlen, int numpages)
+-{
+- int ret, j;
+-
+- ret = scan_read_oob(mtd, buf, offs, readlen);
+- /* Ignore ECC errors when checking for BBM */
+- if (ret && !mtd_is_bitflip_or_eccerr(ret))
+- return ret;
+-
+- for (j = 0; j < numpages; j++, buf += scanlen) {
+- if (check_pattern(buf, scanlen, mtd->writesize, bd))
+- return 1;
+- }
+- return 0;
+-}
+-
+ /* Scan a given block partially */
+ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
+ loff_t offs, uint8_t *buf, int numpages)
+@@ -464,36 +458,19 @@
+ struct nand_bbt_descr *bd, int chip)
+ {
+ struct nand_chip *this = mtd->priv;
+- int i, numblocks, numpages, scanlen;
++ int i, numblocks, numpages;
+ int startblock;
+ loff_t from;
+- size_t readlen;
+
+ pr_info("Scanning device for bad blocks\n");
+
+- if (bd->options & NAND_BBT_SCANALLPAGES)
+- numpages = 1 << (this->bbt_erase_shift - this->page_shift);
+- else if (bd->options & NAND_BBT_SCAN2NDPAGE)
++ if (bd->options & NAND_BBT_SCAN2NDPAGE)
+ numpages = 2;
+ else
+ numpages = 1;
+
+- if (!(bd->options & NAND_BBT_SCANEMPTY)) {
+- /* We need only read few bytes from the OOB area */
+- scanlen = 0;
+- readlen = bd->len;
+- } else {
+- /* Full page content should be read */
+- scanlen = mtd->writesize + mtd->oobsize;
+- readlen = numpages * mtd->writesize;
+- }
+-
+ if (chip == -1) {
+- /*
+- * Note that numblocks is 2 * (real numblocks) here, see i+=2
+- * below as it makes shifting and masking less painful
+- */
+- numblocks = mtd->size >> (this->bbt_erase_shift - 1);
++ numblocks = mtd->size >> this->bbt_erase_shift;
+ startblock = 0;
+ from = 0;
+ } else {
+@@ -502,37 +479,31 @@
+ chip + 1, this->numchips);
+ return -EINVAL;
+ }
+- numblocks = this->chipsize >> (this->bbt_erase_shift - 1);
++ numblocks = this->chipsize >> this->bbt_erase_shift;
+ startblock = chip * numblocks;
+ numblocks += startblock;
+- from = (loff_t)startblock << (this->bbt_erase_shift - 1);
++ from = (loff_t)startblock << this->bbt_erase_shift;
+ }
+
+ if (this->bbt_options & NAND_BBT_SCANLASTPAGE)
+ from += mtd->erasesize - (mtd->writesize * numpages);
+
+- for (i = startblock; i < numblocks;) {
++ for (i = startblock; i < numblocks; i++) {
+ int ret;
+
+ BUG_ON(bd->options & NAND_BBT_NO_OOB);
+
+- if (bd->options & NAND_BBT_SCANALLPAGES)
+- ret = scan_block_full(mtd, bd, from, buf, readlen,
+- scanlen, numpages);
+- else
+- ret = scan_block_fast(mtd, bd, from, buf, numpages);
+-
++ ret = scan_block_fast(mtd, bd, from, buf, numpages);
+ if (ret < 0)
+ return ret;
+
+ if (ret) {
+- this->bbt[i >> 3] |= 0x03 << (i & 0x6);
++ bbt_mark_entry(this, i, BBT_BLOCK_FACTORY_BAD);
+ pr_warn("Bad eraseblock %d at 0x%012llx\n",
+- i >> 1, (unsigned long long)from);
++ i, (unsigned long long)from);
+ mtd->ecc_stats.badblocks++;
+ }
+
+- i += 2;
+ from += (1 << this->bbt_erase_shift);
+ }
+ return 0;
+@@ -655,9 +626,9 @@
+ {
+ struct nand_chip *this = mtd->priv;
+ struct erase_info einfo;
+- int i, j, res, chip = 0;
++ int i, res, chip = 0;
+ int bits, startblock, dir, page, offs, numblocks, sft, sftmsk;
+- int nrchips, bbtoffs, pageoffs, ooboffs;
++ int nrchips, pageoffs, ooboffs;
+ uint8_t msk[4];
+ uint8_t rcode = td->reserved_block_code;
+ size_t retlen, len = 0;
+@@ -713,10 +684,9 @@
+ for (i = 0; i < td->maxblocks; i++) {
+ int block = startblock + dir * i;
+ /* Check, if the block is bad */
+- switch ((this->bbt[block >> 2] >>
+- (2 * (block & 0x03))) & 0x03) {
+- case 0x01:
+- case 0x03:
++ switch (bbt_get_entry(this, block)) {
++ case BBT_BLOCK_WORN:
++ case BBT_BLOCK_FACTORY_BAD:
+ continue;
+ }
+ page = block <<
+@@ -748,8 +718,6 @@
+ default: return -EINVAL;
+ }
+
+- bbtoffs = chip * (numblocks >> 2);
+-
+ to = ((loff_t)page) << this->page_shift;
+
+ /* Must we save the block contents? */
+@@ -814,16 +782,12 @@
+ buf[ooboffs + td->veroffs] = td->version[chip];
+
+ /* Walk through the memory table */
+- for (i = 0; i < numblocks;) {
++ for (i = 0; i < numblocks; i++) {
+ uint8_t dat;
+- dat = this->bbt[bbtoffs + (i >> 2)];
+- for (j = 0; j < 4; j++, i++) {
+- int sftcnt = (i << (3 - sft)) & sftmsk;
+- /* Do not store the reserved bbt blocks! */
+- buf[offs + (i >> sft)] &=
+- ~(msk[dat & 0x03] << sftcnt);
+- dat >>= 2;
+- }
++ int sftcnt = (i << (3 - sft)) & sftmsk;
++ dat = bbt_get_entry(this, chip * numblocks + i);
++ /* Do not store the reserved bbt blocks! */
++ buf[offs + (i >> sft)] &= ~(msk[dat] << sftcnt);
+ }
+
+ memset(&einfo, 0, sizeof(einfo));
+@@ -865,7 +829,6 @@
+ {
+ struct nand_chip *this = mtd->priv;
+
+- bd->options &= ~NAND_BBT_SCANEMPTY;
+ return create_bbt(mtd, this->buffers->databuf, bd, -1);
+ }
+
+@@ -1009,7 +972,7 @@
+ {
+ struct nand_chip *this = mtd->priv;
+ int i, j, chips, block, nrblocks, update;
+- uint8_t oldval, newval;
++ uint8_t oldval;
+
+ /* Do we have a bbt per chip? */
+ if (td->options & NAND_BBT_PERCHIP) {
+@@ -1026,12 +989,12 @@
+ if (td->pages[i] == -1)
+ continue;
+ block = td->pages[i] >> (this->bbt_erase_shift - this->page_shift);
+- block <<= 1;
+- oldval = this->bbt[(block >> 3)];
+- newval = oldval | (0x2 << (block & 0x06));
+- this->bbt[(block >> 3)] = newval;
+- if ((oldval != newval) && td->reserved_block_code)
+- nand_update_bbt(mtd, (loff_t)block << (this->bbt_erase_shift - 1));
++ oldval = bbt_get_entry(this, block);
++ bbt_mark_entry(this, block, BBT_BLOCK_RESERVED);
++ if ((oldval != BBT_BLOCK_RESERVED) &&
++ td->reserved_block_code)
++ nand_update_bbt(mtd, (loff_t)block <<
++ this->bbt_erase_shift);
+ continue;
+ }
+ update = 0;
+@@ -1039,14 +1002,12 @@
+ block = ((i + 1) * nrblocks) - td->maxblocks;
+ else
+ block = i * nrblocks;
+- block <<= 1;
+ for (j = 0; j < td->maxblocks; j++) {
+- oldval = this->bbt[(block >> 3)];
+- newval = oldval | (0x2 << (block & 0x06));
+- this->bbt[(block >> 3)] = newval;
+- if (oldval != newval)
++ oldval = bbt_get_entry(this, block);
++ bbt_mark_entry(this, block, BBT_BLOCK_RESERVED);
++ if (oldval != BBT_BLOCK_RESERVED)
+ update = 1;
+- block += 2;
++ block++;
+ }
+ /*
+ * If we want reserved blocks to be recorded to flash, and some
+@@ -1054,7 +1015,8 @@
+ * bbts. This should only happen once.
+ */
+ if (update && td->reserved_block_code)
+- nand_update_bbt(mtd, (loff_t)(block - 2) << (this->bbt_erase_shift - 1));
++ nand_update_bbt(mtd, (loff_t)(block - 1) <<
++ this->bbt_erase_shift);
+ }
+ }
+
+@@ -1180,13 +1142,13 @@
+ }
+
+ /**
+- * nand_update_bbt - [NAND Interface] update bad block table(s)
++ * nand_update_bbt - update bad block table(s)
+ * @mtd: MTD device structure
+ * @offs: the offset of the newly marked block
+ *
+ * The function updates the bad block table(s).
+ */
+-int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
++static int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
+ {
+ struct nand_chip *this = mtd->priv;
+ int len, res = 0;
+@@ -1356,28 +1318,46 @@
+ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
+ {
+ struct nand_chip *this = mtd->priv;
+- int block;
+- uint8_t res;
++ int block, res;
+
+- /* Get block number * 2 */
+- block = (int)(offs >> (this->bbt_erase_shift - 1));
+- res = (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
++ block = (int)(offs >> this->bbt_erase_shift);
++ res = bbt_get_entry(this, block);
+
+ pr_debug("nand_isbad_bbt(): bbt info for offs 0x%08x: "
+ "(block %d) 0x%02x\n",
+- (unsigned int)offs, block >> 1, res);
++ (unsigned int)offs, block, res);
+
+- switch ((int)res) {
+- case 0x00:
++ switch (res) {
++ case BBT_BLOCK_GOOD:
+ return 0;
+- case 0x01:
++ case BBT_BLOCK_WORN:
+ return 1;
+- case 0x02:
++ case BBT_BLOCK_RESERVED:
+ return allowbbt ? 0 : 1;
+ }
+ return 1;
+ }
+
++/**
++ * nand_markbad_bbt - [NAND Interface] Mark a block bad in the BBT
++ * @mtd: MTD device structure
++ * @offs: offset of the bad block
++ */
++int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
++{
++ struct nand_chip *this = mtd->priv;
++ int block, ret = 0;
++
++ block = (int)(offs >> this->bbt_erase_shift);
++
++ /* Mark bad block in memory */
++ bbt_mark_entry(this, block, BBT_BLOCK_WORN);
++
++ /* Update flash-based bad block table */
++ if (this->bbt_options & NAND_BBT_USE_FLASH)
++ ret = nand_update_bbt(mtd, offs);
++
++ return ret;
++}
++
+ EXPORT_SYMBOL(nand_scan_bbt);
+-EXPORT_SYMBOL(nand_default_bbt);
+-EXPORT_SYMBOL_GPL(nand_update_bbt);
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/nand_ids.c linux-linaro-stable-mx6/drivers/mtd/nand/nand_ids.c
+--- linux-3.10.30.orig/drivers/mtd/nand/nand_ids.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/nand_ids.c 2014-05-15 20:33:58.430016978 +0200
+@@ -33,16 +33,16 @@
+ */
+ {"TC58NVG2S0F 4G 3.3V 8-bit",
+ { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
+- SZ_4K, SZ_512, SZ_256K, 0, 8, 224},
++ SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
+ {"TC58NVG3S0F 8G 3.3V 8-bit",
+ { .id = {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} },
+- SZ_4K, SZ_1K, SZ_256K, 0, 8, 232},
++ SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
+ {"TC58NVG5D2 32G 3.3V 8-bit",
+ { .id = {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0x09, 0x00} },
+- SZ_8K, SZ_4K, SZ_1M, 0, 8, 640},
++ SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
+ {"TC58NVG6D2 64G 3.3V 8-bit",
+ { .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
+- SZ_8K, SZ_8K, SZ_2M, 0, 8, 640},
++ SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
+
+ LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
+ LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/omap2.c linux-linaro-stable-mx6/drivers/mtd/nand/omap2.c
+--- linux-3.10.30.orig/drivers/mtd/nand/omap2.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/omap2.c 2014-05-15 20:33:58.430016978 +0200
+@@ -154,7 +154,7 @@
+ */
+ static uint8_t scan_ff_pattern[] = { 0xff };
+ static struct nand_bbt_descr bb_descrip_flashbased = {
+- .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
++ .options = NAND_BBT_SCANALLPAGES,
+ .offs = 0,
+ .len = 1,
+ .pattern = scan_ff_pattern,
+diff -Nur linux-3.10.30.orig/drivers/mtd/nand/sm_common.c linux-linaro-stable-mx6/drivers/mtd/nand/sm_common.c
+--- linux-3.10.30.orig/drivers/mtd/nand/sm_common.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nand/sm_common.c 2014-05-15 20:33:58.434017007 +0200
+@@ -42,7 +42,7 @@
+ {
+ struct mtd_oob_ops ops;
+ struct sm_oob oob;
+- int ret, error = 0;
++ int ret;
+
+ memset(&oob, -1, SM_OOB_SIZE);
+ oob.block_status = 0x0F;
+@@ -61,11 +61,10 @@
+ printk(KERN_NOTICE
+ "sm_common: can't mark sector at %i as bad\n",
+ (int)ofs);
+- error = -EIO;
+- } else
+- mtd->ecc_stats.badblocks++;
++ return -EIO;
++ }
+
+- return error;
++ return 0;
+ }
+
+ static struct nand_flash_dev nand_smartmedia_flash_ids[] = {
+diff -Nur linux-3.10.30.orig/drivers/mtd/nftlcore.c linux-linaro-stable-mx6/drivers/mtd/nftlcore.c
+--- linux-3.10.30.orig/drivers/mtd/nftlcore.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/nftlcore.c 2014-05-15 20:33:58.502017497 +0200
+@@ -50,7 +50,7 @@
+ struct NFTLrecord *nftl;
+ unsigned long temp;
+
+- if (mtd->type != MTD_NANDFLASH || mtd->size > UINT_MAX)
++ if (!mtd_type_is_nand(mtd) || mtd->size > UINT_MAX)
+ return;
+ /* OK, this is moderately ugly. But probably safe. Alternatives? */
+ if (memcmp(mtd->name, "DiskOnChip", 10))
+diff -Nur linux-3.10.30.orig/drivers/mtd/onenand/onenand_bbt.c linux-linaro-stable-mx6/drivers/mtd/onenand/onenand_bbt.c
+--- linux-3.10.30.orig/drivers/mtd/onenand/onenand_bbt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/onenand/onenand_bbt.c 2014-05-15 20:33:58.538017757 +0200
+@@ -133,7 +133,6 @@
+ {
+ struct onenand_chip *this = mtd->priv;
+
+- bd->options &= ~NAND_BBT_SCANEMPTY;
+ return create_bbt(mtd, this->page_buf, bd, -1);
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/mtd/ssfdc.c linux-linaro-stable-mx6/drivers/mtd/ssfdc.c
+--- linux-3.10.30.orig/drivers/mtd/ssfdc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/ssfdc.c 2014-05-15 20:33:58.538017757 +0200
+@@ -290,7 +290,7 @@
+ int cis_sector;
+
+ /* Check for small page NAND flash */
+- if (mtd->type != MTD_NANDFLASH || mtd->oobsize != OOB_SIZE ||
++ if (!mtd_type_is_nand(mtd) || mtd->oobsize != OOB_SIZE ||
+ mtd->size > UINT_MAX)
+ return;
+
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/Makefile linux-linaro-stable-mx6/drivers/mtd/tests/Makefile
+--- linux-3.10.30.orig/drivers/mtd/tests/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/Makefile 2014-05-15 20:33:58.542017785 +0200
+@@ -7,3 +7,12 @@
+ obj-$(CONFIG_MTD_TESTS) += mtd_torturetest.o
+ obj-$(CONFIG_MTD_TESTS) += mtd_nandecctest.o
+ obj-$(CONFIG_MTD_TESTS) += mtd_nandbiterrs.o
++
++mtd_oobtest-objs := oobtest.o mtd_test.o
++mtd_pagetest-objs := pagetest.o mtd_test.o
++mtd_readtest-objs := readtest.o mtd_test.o
++mtd_speedtest-objs := speedtest.o mtd_test.o
++mtd_stresstest-objs := stresstest.o mtd_test.o
++mtd_subpagetest-objs := subpagetest.o mtd_test.o
++mtd_torturetest-objs := torturetest.o mtd_test.o
++mtd_nandbiterrs-objs := nandbiterrs.o mtd_test.o
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_nandbiterrs.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_nandbiterrs.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_nandbiterrs.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_nandbiterrs.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,461 +0,0 @@
+-/*
+- * Copyright © 2012 NetCommWireless
+- * Iwo Mergler <Iwo.Mergler@netcommwireless.com.au>
+- *
+- * Test for multi-bit error recovery on a NAND page This mostly tests the
+- * ECC controller / driver.
+- *
+- * There are two test modes:
+- *
+- * 0 - artificially inserting bit errors until the ECC fails
+- * This is the default method and fairly quick. It should
+- * be independent of the quality of the FLASH.
+- *
+- * 1 - re-writing the same pattern repeatedly until the ECC fails.
+- * This method relies on the physics of NAND FLASH to eventually
+- * generate '0' bits if '1' has been written sufficient times.
+- * Depending on the NAND, the first bit errors will appear after
+- * 1000 or more writes and then will usually snowball, reaching the
+- * limits of the ECC quickly.
+- *
+- * The test stops after 10000 cycles, should your FLASH be
+- * exceptionally good and not generate bit errors before that. Try
+- * a different page in that case.
+- *
+- * Please note that neither of these tests will significantly 'use up' any
+- * FLASH endurance. Only a maximum of two erase operations will be performed.
+- *
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; see the file COPYING. If not, write to the Free Software
+- * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/err.h>
+-#include <linux/mtd/nand.h>
+-#include <linux/slab.h>
+-
+-static int dev;
+-module_param(dev, int, S_IRUGO);
+-MODULE_PARM_DESC(dev, "MTD device number to use");
+-
+-static unsigned page_offset;
+-module_param(page_offset, uint, S_IRUGO);
+-MODULE_PARM_DESC(page_offset, "Page number relative to dev start");
+-
+-static unsigned seed;
+-module_param(seed, uint, S_IRUGO);
+-MODULE_PARM_DESC(seed, "Random seed");
+-
+-static int mode;
+-module_param(mode, int, S_IRUGO);
+-MODULE_PARM_DESC(mode, "0=incremental errors, 1=overwrite test");
+-
+-static unsigned max_overwrite = 10000;
+-
+-static loff_t offset; /* Offset of the page we're using. */
+-static unsigned eraseblock; /* Eraseblock number for our page. */
+-
+-/* We assume that the ECC can correct up to a certain number
+- * of biterrors per subpage. */
+-static unsigned subsize; /* Size of subpages */
+-static unsigned subcount; /* Number of subpages per page */
+-
+-static struct mtd_info *mtd; /* MTD device */
+-
+-static uint8_t *wbuffer; /* One page write / compare buffer */
+-static uint8_t *rbuffer; /* One page read buffer */
+-
+-/* 'random' bytes from known offsets */
+-static uint8_t hash(unsigned offset)
+-{
+- unsigned v = offset;
+- unsigned char c;
+- v ^= 0x7f7edfd3;
+- v = v ^ (v >> 3);
+- v = v ^ (v >> 5);
+- v = v ^ (v >> 13);
+- c = v & 0xFF;
+- /* Reverse bits of result. */
+- c = (c & 0x0F) << 4 | (c & 0xF0) >> 4;
+- c = (c & 0x33) << 2 | (c & 0xCC) >> 2;
+- c = (c & 0x55) << 1 | (c & 0xAA) >> 1;
+- return c;
+-}
+-
+-static int erase_block(void)
+-{
+- int err;
+- struct erase_info ei;
+- loff_t addr = eraseblock * mtd->erasesize;
+-
+- pr_info("erase_block\n");
+-
+- memset(&ei, 0, sizeof(struct erase_info));
+- ei.mtd = mtd;
+- ei.addr = addr;
+- ei.len = mtd->erasesize;
+-
+- err = mtd_erase(mtd, &ei);
+- if (err || ei.state == MTD_ERASE_FAILED) {
+- pr_err("error %d while erasing\n", err);
+- if (!err)
+- err = -EIO;
+- return err;
+- }
+-
+- return 0;
+-}
+-
+-/* Writes wbuffer to page */
+-static int write_page(int log)
+-{
+- int err = 0;
+- size_t written;
+-
+- if (log)
+- pr_info("write_page\n");
+-
+- err = mtd_write(mtd, offset, mtd->writesize, &written, wbuffer);
+- if (err || written != mtd->writesize) {
+- pr_err("error: write failed at %#llx\n", (long long)offset);
+- if (!err)
+- err = -EIO;
+- }
+-
+- return err;
+-}
+-
+-/* Re-writes the data area while leaving the OOB alone. */
+-static int rewrite_page(int log)
+-{
+- int err = 0;
+- struct mtd_oob_ops ops;
+-
+- if (log)
+- pr_info("rewrite page\n");
+-
+- ops.mode = MTD_OPS_RAW; /* No ECC */
+- ops.len = mtd->writesize;
+- ops.retlen = 0;
+- ops.ooblen = 0;
+- ops.oobretlen = 0;
+- ops.ooboffs = 0;
+- ops.datbuf = wbuffer;
+- ops.oobbuf = NULL;
+-
+- err = mtd_write_oob(mtd, offset, &ops);
+- if (err || ops.retlen != mtd->writesize) {
+- pr_err("error: write_oob failed (%d)\n", err);
+- if (!err)
+- err = -EIO;
+- }
+-
+- return err;
+-}
+-
+-/* Reads page into rbuffer. Returns number of corrected bit errors (>=0)
+- * or error (<0) */
+-static int read_page(int log)
+-{
+- int err = 0;
+- size_t read;
+- struct mtd_ecc_stats oldstats;
+-
+- if (log)
+- pr_info("read_page\n");
+-
+- /* Saving last mtd stats */
+- memcpy(&oldstats, &mtd->ecc_stats, sizeof(oldstats));
+-
+- err = mtd_read(mtd, offset, mtd->writesize, &read, rbuffer);
+- if (err == -EUCLEAN)
+- err = mtd->ecc_stats.corrected - oldstats.corrected;
+-
+- if (err < 0 || read != mtd->writesize) {
+- pr_err("error: read failed at %#llx\n", (long long)offset);
+- if (err >= 0)
+- err = -EIO;
+- }
+-
+- return err;
+-}
+-
+-/* Verifies rbuffer against random sequence */
+-static int verify_page(int log)
+-{
+- unsigned i, errs = 0;
+-
+- if (log)
+- pr_info("verify_page\n");
+-
+- for (i = 0; i < mtd->writesize; i++) {
+- if (rbuffer[i] != hash(i+seed)) {
+- pr_err("Error: page offset %u, expected %02x, got %02x\n",
+- i, hash(i+seed), rbuffer[i]);
+- errs++;
+- }
+- }
+-
+- if (errs)
+- return -EIO;
+- else
+- return 0;
+-}
+-
+-#define CBIT(v, n) ((v) & (1 << (n)))
+-#define BCLR(v, n) ((v) = (v) & ~(1 << (n)))
+-
+-/* Finds the first '1' bit in wbuffer starting at offset 'byte'
+- * and sets it to '0'. */
+-static int insert_biterror(unsigned byte)
+-{
+- int bit;
+-
+- while (byte < mtd->writesize) {
+- for (bit = 7; bit >= 0; bit--) {
+- if (CBIT(wbuffer[byte], bit)) {
+- BCLR(wbuffer[byte], bit);
+- pr_info("Inserted biterror @ %u/%u\n", byte, bit);
+- return 0;
+- }
+- }
+- byte++;
+- }
+- pr_err("biterror: Failed to find a '1' bit\n");
+- return -EIO;
+-}
+-
+-/* Writes 'random' data to page and then introduces deliberate bit
+- * errors into the page, while verifying each step. */
+-static int incremental_errors_test(void)
+-{
+- int err = 0;
+- unsigned i;
+- unsigned errs_per_subpage = 0;
+-
+- pr_info("incremental biterrors test\n");
+-
+- for (i = 0; i < mtd->writesize; i++)
+- wbuffer[i] = hash(i+seed);
+-
+- err = write_page(1);
+- if (err)
+- goto exit;
+-
+- while (1) {
+-
+- err = rewrite_page(1);
+- if (err)
+- goto exit;
+-
+- err = read_page(1);
+- if (err > 0)
+- pr_info("Read reported %d corrected bit errors\n", err);
+- if (err < 0) {
+- pr_err("After %d biterrors per subpage, read reported error %d\n",
+- errs_per_subpage, err);
+- err = 0;
+- goto exit;
+- }
+-
+- err = verify_page(1);
+- if (err) {
+- pr_err("ECC failure, read data is incorrect despite read success\n");
+- goto exit;
+- }
+-
+- pr_info("Successfully corrected %d bit errors per subpage\n",
+- errs_per_subpage);
+-
+- for (i = 0; i < subcount; i++) {
+- err = insert_biterror(i * subsize);
+- if (err < 0)
+- goto exit;
+- }
+- errs_per_subpage++;
+- }
+-
+-exit:
+- return err;
+-}
+-
+-
+-/* Writes 'random' data to page and then re-writes that same data repeatedly.
+- This eventually develops bit errors (bits written as '1' will slowly become
+- '0'), which are corrected as far as the ECC is capable of. */
+-static int overwrite_test(void)
+-{
+- int err = 0;
+- unsigned i;
+- unsigned max_corrected = 0;
+- unsigned opno = 0;
+- /* We don't expect more than this many correctable bit errors per
+- * page. */
+- #define MAXBITS 512
+- static unsigned bitstats[MAXBITS]; /* bit error histogram. */
+-
+- memset(bitstats, 0, sizeof(bitstats));
+-
+- pr_info("overwrite biterrors test\n");
+-
+- for (i = 0; i < mtd->writesize; i++)
+- wbuffer[i] = hash(i+seed);
+-
+- err = write_page(1);
+- if (err)
+- goto exit;
+-
+- while (opno < max_overwrite) {
+-
+- err = rewrite_page(0);
+- if (err)
+- break;
+-
+- err = read_page(0);
+- if (err >= 0) {
+- if (err >= MAXBITS) {
+- pr_info("Implausible number of bit errors corrected\n");
+- err = -EIO;
+- break;
+- }
+- bitstats[err]++;
+- if (err > max_corrected) {
+- max_corrected = err;
+- pr_info("Read reported %d corrected bit errors\n",
+- err);
+- }
+- } else { /* err < 0 */
+- pr_info("Read reported error %d\n", err);
+- err = 0;
+- break;
+- }
+-
+- err = verify_page(0);
+- if (err) {
+- bitstats[max_corrected] = opno;
+- pr_info("ECC failure, read data is incorrect despite read success\n");
+- break;
+- }
+-
+- opno++;
+- }
+-
+- /* At this point bitstats[0] contains the number of ops with no bit
+- * errors, bitstats[1] the number of ops with 1 bit error, etc. */
+- pr_info("Bit error histogram (%d operations total):\n", opno);
+- for (i = 0; i < max_corrected; i++)
+- pr_info("Page reads with %3d corrected bit errors: %d\n",
+- i, bitstats[i]);
+-
+-exit:
+- return err;
+-}
+-
+-static int __init mtd_nandbiterrs_init(void)
+-{
+- int err = 0;
+-
+- printk("\n");
+- printk(KERN_INFO "==================================================\n");
+- pr_info("MTD device: %d\n", dev);
+-
+- mtd = get_mtd_device(NULL, dev);
+- if (IS_ERR(mtd)) {
+- err = PTR_ERR(mtd);
+- pr_err("error: cannot get MTD device\n");
+- goto exit_mtddev;
+- }
+-
+- if (mtd->type != MTD_NANDFLASH) {
+- pr_info("this test requires NAND flash\n");
+- err = -ENODEV;
+- goto exit_nand;
+- }
+-
+- pr_info("MTD device size %llu, eraseblock=%u, page=%u, oob=%u\n",
+- (unsigned long long)mtd->size, mtd->erasesize,
+- mtd->writesize, mtd->oobsize);
+-
+- subsize = mtd->writesize >> mtd->subpage_sft;
+- subcount = mtd->writesize / subsize;
+-
+- pr_info("Device uses %d subpages of %d bytes\n", subcount, subsize);
+-
+- offset = page_offset * mtd->writesize;
+- eraseblock = mtd_div_by_eb(offset, mtd);
+-
+- pr_info("Using page=%u, offset=%llu, eraseblock=%u\n",
+- page_offset, offset, eraseblock);
+-
+- wbuffer = kmalloc(mtd->writesize, GFP_KERNEL);
+- if (!wbuffer) {
+- err = -ENOMEM;
+- goto exit_wbuffer;
+- }
+-
+- rbuffer = kmalloc(mtd->writesize, GFP_KERNEL);
+- if (!rbuffer) {
+- err = -ENOMEM;
+- goto exit_rbuffer;
+- }
+-
+- err = erase_block();
+- if (err)
+- goto exit_error;
+-
+- if (mode == 0)
+- err = incremental_errors_test();
+- else
+- err = overwrite_test();
+-
+- if (err)
+- goto exit_error;
+-
+- /* We leave the block un-erased in case of test failure. */
+- err = erase_block();
+- if (err)
+- goto exit_error;
+-
+- err = -EIO;
+- pr_info("finished successfully.\n");
+- printk(KERN_INFO "==================================================\n");
+-
+-exit_error:
+- kfree(rbuffer);
+-exit_rbuffer:
+- kfree(wbuffer);
+-exit_wbuffer:
+- /* Nothing */
+-exit_nand:
+- put_mtd_device(mtd);
+-exit_mtddev:
+- return err;
+-}
+-
+-static void __exit mtd_nandbiterrs_exit(void)
+-{
+- return;
+-}
+-
+-module_init(mtd_nandbiterrs_init);
+-module_exit(mtd_nandbiterrs_exit);
+-
+-MODULE_DESCRIPTION("NAND bit error recovery test");
+-MODULE_AUTHOR("Iwo Mergler");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_oobtest.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_oobtest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_oobtest.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_oobtest.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,720 +0,0 @@
+-/*
+- * Copyright (C) 2006-2008 Nokia Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; see the file COPYING. If not, write to the Free Software
+- * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- *
+- * Test OOB read and write on MTD device.
+- *
+- * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <asm/div64.h>
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/err.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/slab.h>
+-#include <linux/sched.h>
+-#include <linux/random.h>
+-
+-static int dev = -EINVAL;
+-module_param(dev, int, S_IRUGO);
+-MODULE_PARM_DESC(dev, "MTD device number to use");
+-
+-static struct mtd_info *mtd;
+-static unsigned char *readbuf;
+-static unsigned char *writebuf;
+-static unsigned char *bbt;
+-
+-static int ebcnt;
+-static int pgcnt;
+-static int errcnt;
+-static int use_offset;
+-static int use_len;
+-static int use_len_max;
+-static int vary_offset;
+-static struct rnd_state rnd_state;
+-
+-static int erase_eraseblock(int ebnum)
+-{
+- int err;
+- struct erase_info ei;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- memset(&ei, 0, sizeof(struct erase_info));
+- ei.mtd = mtd;
+- ei.addr = addr;
+- ei.len = mtd->erasesize;
+-
+- err = mtd_erase(mtd, &ei);
+- if (err) {
+- pr_err("error %d while erasing EB %d\n", err, ebnum);
+- return err;
+- }
+-
+- if (ei.state == MTD_ERASE_FAILED) {
+- pr_err("some erase error occurred at EB %d\n", ebnum);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-static int erase_whole_device(void)
+-{
+- int err;
+- unsigned int i;
+-
+- pr_info("erasing whole device\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = erase_eraseblock(i);
+- if (err)
+- return err;
+- cond_resched();
+- }
+- pr_info("erased %u eraseblocks\n", i);
+- return 0;
+-}
+-
+-static void do_vary_offset(void)
+-{
+- use_len -= 1;
+- if (use_len < 1) {
+- use_offset += 1;
+- if (use_offset >= use_len_max)
+- use_offset = 0;
+- use_len = use_len_max - use_offset;
+- }
+-}
+-
+-static int write_eraseblock(int ebnum)
+-{
+- int i;
+- struct mtd_oob_ops ops;
+- int err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- for (i = 0; i < pgcnt; ++i, addr += mtd->writesize) {
+- prandom_bytes_state(&rnd_state, writebuf, use_len);
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = use_len;
+- ops.oobretlen = 0;
+- ops.ooboffs = use_offset;
+- ops.datbuf = NULL;
+- ops.oobbuf = writebuf;
+- err = mtd_write_oob(mtd, addr, &ops);
+- if (err || ops.oobretlen != use_len) {
+- pr_err("error: writeoob failed at %#llx\n",
+- (long long)addr);
+- pr_err("error: use_len %d, use_offset %d\n",
+- use_len, use_offset);
+- errcnt += 1;
+- return err ? err : -1;
+- }
+- if (vary_offset)
+- do_vary_offset();
+- }
+-
+- return err;
+-}
+-
+-static int write_whole_device(void)
+-{
+- int err;
+- unsigned int i;
+-
+- pr_info("writing OOBs of whole device\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = write_eraseblock(i);
+- if (err)
+- return err;
+- if (i % 256 == 0)
+- pr_info("written up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("written %u eraseblocks\n", i);
+- return 0;
+-}
+-
+-static int verify_eraseblock(int ebnum)
+-{
+- int i;
+- struct mtd_oob_ops ops;
+- int err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- for (i = 0; i < pgcnt; ++i, addr += mtd->writesize) {
+- prandom_bytes_state(&rnd_state, writebuf, use_len);
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = use_len;
+- ops.oobretlen = 0;
+- ops.ooboffs = use_offset;
+- ops.datbuf = NULL;
+- ops.oobbuf = readbuf;
+- err = mtd_read_oob(mtd, addr, &ops);
+- if (err || ops.oobretlen != use_len) {
+- pr_err("error: readoob failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- return err ? err : -1;
+- }
+- if (memcmp(readbuf, writebuf, use_len)) {
+- pr_err("error: verify failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- if (errcnt > 1000) {
+- pr_err("error: too many errors\n");
+- return -1;
+- }
+- }
+- if (use_offset != 0 || use_len < mtd->ecclayout->oobavail) {
+- int k;
+-
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = mtd->ecclayout->oobavail;
+- ops.oobretlen = 0;
+- ops.ooboffs = 0;
+- ops.datbuf = NULL;
+- ops.oobbuf = readbuf;
+- err = mtd_read_oob(mtd, addr, &ops);
+- if (err || ops.oobretlen != mtd->ecclayout->oobavail) {
+- pr_err("error: readoob failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- return err ? err : -1;
+- }
+- if (memcmp(readbuf + use_offset, writebuf, use_len)) {
+- pr_err("error: verify failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- if (errcnt > 1000) {
+- pr_err("error: too many errors\n");
+- return -1;
+- }
+- }
+- for (k = 0; k < use_offset; ++k)
+- if (readbuf[k] != 0xff) {
+- pr_err("error: verify 0xff "
+- "failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- if (errcnt > 1000) {
+- pr_err("error: too "
+- "many errors\n");
+- return -1;
+- }
+- }
+- for (k = use_offset + use_len;
+- k < mtd->ecclayout->oobavail; ++k)
+- if (readbuf[k] != 0xff) {
+- pr_err("error: verify 0xff "
+- "failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- if (errcnt > 1000) {
+- pr_err("error: too "
+- "many errors\n");
+- return -1;
+- }
+- }
+- }
+- if (vary_offset)
+- do_vary_offset();
+- }
+- return err;
+-}
+-
+-static int verify_eraseblock_in_one_go(int ebnum)
+-{
+- struct mtd_oob_ops ops;
+- int err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+- size_t len = mtd->ecclayout->oobavail * pgcnt;
+-
+- prandom_bytes_state(&rnd_state, writebuf, len);
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = len;
+- ops.oobretlen = 0;
+- ops.ooboffs = 0;
+- ops.datbuf = NULL;
+- ops.oobbuf = readbuf;
+- err = mtd_read_oob(mtd, addr, &ops);
+- if (err || ops.oobretlen != len) {
+- pr_err("error: readoob failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- return err ? err : -1;
+- }
+- if (memcmp(readbuf, writebuf, len)) {
+- pr_err("error: verify failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- if (errcnt > 1000) {
+- pr_err("error: too many errors\n");
+- return -1;
+- }
+- }
+-
+- return err;
+-}
+-
+-static int verify_all_eraseblocks(void)
+-{
+- int err;
+- unsigned int i;
+-
+- pr_info("verifying all eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = verify_eraseblock(i);
+- if (err)
+- return err;
+- if (i % 256 == 0)
+- pr_info("verified up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("verified %u eraseblocks\n", i);
+- return 0;
+-}
+-
+-static int is_block_bad(int ebnum)
+-{
+- int ret;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- ret = mtd_block_isbad(mtd, addr);
+- if (ret)
+- pr_info("block %d is bad\n", ebnum);
+- return ret;
+-}
+-
+-static int scan_for_bad_eraseblocks(void)
+-{
+- int i, bad = 0;
+-
+- bbt = kmalloc(ebcnt, GFP_KERNEL);
+- if (!bbt) {
+- pr_err("error: cannot allocate memory\n");
+- return -ENOMEM;
+- }
+-
+- pr_info("scanning for bad eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- bbt[i] = is_block_bad(i) ? 1 : 0;
+- if (bbt[i])
+- bad += 1;
+- cond_resched();
+- }
+- pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
+- return 0;
+-}
+-
+-static int __init mtd_oobtest_init(void)
+-{
+- int err = 0;
+- unsigned int i;
+- uint64_t tmp;
+- struct mtd_oob_ops ops;
+- loff_t addr = 0, addr0;
+-
+- printk(KERN_INFO "\n");
+- printk(KERN_INFO "=================================================\n");
+-
+- if (dev < 0) {
+- pr_info("Please specify a valid mtd-device via module parameter\n");
+- pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
+- return -EINVAL;
+- }
+-
+- pr_info("MTD device: %d\n", dev);
+-
+- mtd = get_mtd_device(NULL, dev);
+- if (IS_ERR(mtd)) {
+- err = PTR_ERR(mtd);
+- pr_err("error: cannot get MTD device\n");
+- return err;
+- }
+-
+- if (mtd->type != MTD_NANDFLASH) {
+- pr_info("this test requires NAND flash\n");
+- goto out;
+- }
+-
+- tmp = mtd->size;
+- do_div(tmp, mtd->erasesize);
+- ebcnt = tmp;
+- pgcnt = mtd->erasesize / mtd->writesize;
+-
+- pr_info("MTD device size %llu, eraseblock size %u, "
+- "page size %u, count of eraseblocks %u, pages per "
+- "eraseblock %u, OOB size %u\n",
+- (unsigned long long)mtd->size, mtd->erasesize,
+- mtd->writesize, ebcnt, pgcnt, mtd->oobsize);
+-
+- err = -ENOMEM;
+- readbuf = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!readbuf) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+- writebuf = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!writebuf) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+-
+- err = scan_for_bad_eraseblocks();
+- if (err)
+- goto out;
+-
+- use_offset = 0;
+- use_len = mtd->ecclayout->oobavail;
+- use_len_max = mtd->ecclayout->oobavail;
+- vary_offset = 0;
+-
+- /* First test: write all OOB, read it back and verify */
+- pr_info("test 1 of 5\n");
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- prandom_seed_state(&rnd_state, 1);
+- err = write_whole_device();
+- if (err)
+- goto out;
+-
+- prandom_seed_state(&rnd_state, 1);
+- err = verify_all_eraseblocks();
+- if (err)
+- goto out;
+-
+- /*
+- * Second test: write all OOB, a block at a time, read it back and
+- * verify.
+- */
+- pr_info("test 2 of 5\n");
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- prandom_seed_state(&rnd_state, 3);
+- err = write_whole_device();
+- if (err)
+- goto out;
+-
+- /* Check all eraseblocks */
+- prandom_seed_state(&rnd_state, 3);
+- pr_info("verifying all eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = verify_eraseblock_in_one_go(i);
+- if (err)
+- goto out;
+- if (i % 256 == 0)
+- pr_info("verified up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("verified %u eraseblocks\n", i);
+-
+- /*
+- * Third test: write OOB at varying offsets and lengths, read it back
+- * and verify.
+- */
+- pr_info("test 3 of 5\n");
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- /* Write all eraseblocks */
+- use_offset = 0;
+- use_len = mtd->ecclayout->oobavail;
+- use_len_max = mtd->ecclayout->oobavail;
+- vary_offset = 1;
+- prandom_seed_state(&rnd_state, 5);
+-
+- err = write_whole_device();
+- if (err)
+- goto out;
+-
+- /* Check all eraseblocks */
+- use_offset = 0;
+- use_len = mtd->ecclayout->oobavail;
+- use_len_max = mtd->ecclayout->oobavail;
+- vary_offset = 1;
+- prandom_seed_state(&rnd_state, 5);
+- err = verify_all_eraseblocks();
+- if (err)
+- goto out;
+-
+- use_offset = 0;
+- use_len = mtd->ecclayout->oobavail;
+- use_len_max = mtd->ecclayout->oobavail;
+- vary_offset = 0;
+-
+- /* Fourth test: try to write off end of device */
+- pr_info("test 4 of 5\n");
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- addr0 = 0;
+- for (i = 0; i < ebcnt && bbt[i]; ++i)
+- addr0 += mtd->erasesize;
+-
+- /* Attempt to write off end of OOB */
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = 1;
+- ops.oobretlen = 0;
+- ops.ooboffs = mtd->ecclayout->oobavail;
+- ops.datbuf = NULL;
+- ops.oobbuf = writebuf;
+- pr_info("attempting to start write past end of OOB\n");
+- pr_info("an error is expected...\n");
+- err = mtd_write_oob(mtd, addr0, &ops);
+- if (err) {
+- pr_info("error occurred as expected\n");
+- err = 0;
+- } else {
+- pr_err("error: can write past end of OOB\n");
+- errcnt += 1;
+- }
+-
+- /* Attempt to read off end of OOB */
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = 1;
+- ops.oobretlen = 0;
+- ops.ooboffs = mtd->ecclayout->oobavail;
+- ops.datbuf = NULL;
+- ops.oobbuf = readbuf;
+- pr_info("attempting to start read past end of OOB\n");
+- pr_info("an error is expected...\n");
+- err = mtd_read_oob(mtd, addr0, &ops);
+- if (err) {
+- pr_info("error occurred as expected\n");
+- err = 0;
+- } else {
+- pr_err("error: can read past end of OOB\n");
+- errcnt += 1;
+- }
+-
+- if (bbt[ebcnt - 1])
+- pr_info("skipping end of device tests because last "
+- "block is bad\n");
+- else {
+- /* Attempt to write off end of device */
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = mtd->ecclayout->oobavail + 1;
+- ops.oobretlen = 0;
+- ops.ooboffs = 0;
+- ops.datbuf = NULL;
+- ops.oobbuf = writebuf;
+- pr_info("attempting to write past end of device\n");
+- pr_info("an error is expected...\n");
+- err = mtd_write_oob(mtd, mtd->size - mtd->writesize, &ops);
+- if (err) {
+- pr_info("error occurred as expected\n");
+- err = 0;
+- } else {
+- pr_err("error: wrote past end of device\n");
+- errcnt += 1;
+- }
+-
+- /* Attempt to read off end of device */
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = mtd->ecclayout->oobavail + 1;
+- ops.oobretlen = 0;
+- ops.ooboffs = 0;
+- ops.datbuf = NULL;
+- ops.oobbuf = readbuf;
+- pr_info("attempting to read past end of device\n");
+- pr_info("an error is expected...\n");
+- err = mtd_read_oob(mtd, mtd->size - mtd->writesize, &ops);
+- if (err) {
+- pr_info("error occurred as expected\n");
+- err = 0;
+- } else {
+- pr_err("error: read past end of device\n");
+- errcnt += 1;
+- }
+-
+- err = erase_eraseblock(ebcnt - 1);
+- if (err)
+- goto out;
+-
+- /* Attempt to write off end of device */
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = mtd->ecclayout->oobavail;
+- ops.oobretlen = 0;
+- ops.ooboffs = 1;
+- ops.datbuf = NULL;
+- ops.oobbuf = writebuf;
+- pr_info("attempting to write past end of device\n");
+- pr_info("an error is expected...\n");
+- err = mtd_write_oob(mtd, mtd->size - mtd->writesize, &ops);
+- if (err) {
+- pr_info("error occurred as expected\n");
+- err = 0;
+- } else {
+- pr_err("error: wrote past end of device\n");
+- errcnt += 1;
+- }
+-
+- /* Attempt to read off end of device */
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = mtd->ecclayout->oobavail;
+- ops.oobretlen = 0;
+- ops.ooboffs = 1;
+- ops.datbuf = NULL;
+- ops.oobbuf = readbuf;
+- pr_info("attempting to read past end of device\n");
+- pr_info("an error is expected...\n");
+- err = mtd_read_oob(mtd, mtd->size - mtd->writesize, &ops);
+- if (err) {
+- pr_info("error occurred as expected\n");
+- err = 0;
+- } else {
+- pr_err("error: read past end of device\n");
+- errcnt += 1;
+- }
+- }
+-
+- /* Fifth test: write / read across block boundaries */
+- pr_info("test 5 of 5\n");
+-
+- /* Erase all eraseblocks */
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- /* Write all eraseblocks */
+- prandom_seed_state(&rnd_state, 11);
+- pr_info("writing OOBs of whole device\n");
+- for (i = 0; i < ebcnt - 1; ++i) {
+- int cnt = 2;
+- int pg;
+- size_t sz = mtd->ecclayout->oobavail;
+- if (bbt[i] || bbt[i + 1])
+- continue;
+- addr = (i + 1) * mtd->erasesize - mtd->writesize;
+- for (pg = 0; pg < cnt; ++pg) {
+- prandom_bytes_state(&rnd_state, writebuf, sz);
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = sz;
+- ops.oobretlen = 0;
+- ops.ooboffs = 0;
+- ops.datbuf = NULL;
+- ops.oobbuf = writebuf;
+- err = mtd_write_oob(mtd, addr, &ops);
+- if (err)
+- goto out;
+- if (i % 256 == 0)
+- pr_info("written up to eraseblock %u\n", i);
+- cond_resched();
+- addr += mtd->writesize;
+- }
+- }
+- pr_info("written %u eraseblocks\n", i);
+-
+- /* Check all eraseblocks */
+- prandom_seed_state(&rnd_state, 11);
+- pr_info("verifying all eraseblocks\n");
+- for (i = 0; i < ebcnt - 1; ++i) {
+- if (bbt[i] || bbt[i + 1])
+- continue;
+- prandom_bytes_state(&rnd_state, writebuf,
+- mtd->ecclayout->oobavail * 2);
+- addr = (i + 1) * mtd->erasesize - mtd->writesize;
+- ops.mode = MTD_OPS_AUTO_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = mtd->ecclayout->oobavail * 2;
+- ops.oobretlen = 0;
+- ops.ooboffs = 0;
+- ops.datbuf = NULL;
+- ops.oobbuf = readbuf;
+- err = mtd_read_oob(mtd, addr, &ops);
+- if (err)
+- goto out;
+- if (memcmp(readbuf, writebuf, mtd->ecclayout->oobavail * 2)) {
+- pr_err("error: verify failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- if (errcnt > 1000) {
+- pr_err("error: too many errors\n");
+- goto out;
+- }
+- }
+- if (i % 256 == 0)
+- pr_info("verified up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("verified %u eraseblocks\n", i);
+-
+- pr_info("finished with %d errors\n", errcnt);
+-out:
+- kfree(bbt);
+- kfree(writebuf);
+- kfree(readbuf);
+- put_mtd_device(mtd);
+- if (err)
+- pr_info("error %d occurred\n", err);
+- printk(KERN_INFO "=================================================\n");
+- return err;
+-}
+-module_init(mtd_oobtest_init);
+-
+-static void __exit mtd_oobtest_exit(void)
+-{
+- return;
+-}
+-module_exit(mtd_oobtest_exit);
+-
+-MODULE_DESCRIPTION("Out-of-band test module");
+-MODULE_AUTHOR("Adrian Hunter");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_pagetest.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_pagetest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_pagetest.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_pagetest.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,615 +0,0 @@
+-/*
+- * Copyright (C) 2006-2008 Nokia Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; see the file COPYING. If not, write to the Free Software
+- * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- *
+- * Test page read and write on MTD device.
+- *
+- * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <asm/div64.h>
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/err.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/slab.h>
+-#include <linux/sched.h>
+-#include <linux/random.h>
+-
+-static int dev = -EINVAL;
+-module_param(dev, int, S_IRUGO);
+-MODULE_PARM_DESC(dev, "MTD device number to use");
+-
+-static struct mtd_info *mtd;
+-static unsigned char *twopages;
+-static unsigned char *writebuf;
+-static unsigned char *boundary;
+-static unsigned char *bbt;
+-
+-static int pgsize;
+-static int bufsize;
+-static int ebcnt;
+-static int pgcnt;
+-static int errcnt;
+-static struct rnd_state rnd_state;
+-
+-static int erase_eraseblock(int ebnum)
+-{
+- int err;
+- struct erase_info ei;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- memset(&ei, 0, sizeof(struct erase_info));
+- ei.mtd = mtd;
+- ei.addr = addr;
+- ei.len = mtd->erasesize;
+-
+- err = mtd_erase(mtd, &ei);
+- if (err) {
+- pr_err("error %d while erasing EB %d\n", err, ebnum);
+- return err;
+- }
+-
+- if (ei.state == MTD_ERASE_FAILED) {
+- pr_err("some erase error occurred at EB %d\n",
+- ebnum);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-static int write_eraseblock(int ebnum)
+-{
+- int err = 0;
+- size_t written;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- prandom_bytes_state(&rnd_state, writebuf, mtd->erasesize);
+- cond_resched();
+- err = mtd_write(mtd, addr, mtd->erasesize, &written, writebuf);
+- if (err || written != mtd->erasesize)
+- pr_err("error: write failed at %#llx\n",
+- (long long)addr);
+-
+- return err;
+-}
+-
+-static int verify_eraseblock(int ebnum)
+-{
+- uint32_t j;
+- size_t read;
+- int err = 0, i;
+- loff_t addr0, addrn;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- addr0 = 0;
+- for (i = 0; i < ebcnt && bbt[i]; ++i)
+- addr0 += mtd->erasesize;
+-
+- addrn = mtd->size;
+- for (i = 0; i < ebcnt && bbt[ebcnt - i - 1]; ++i)
+- addrn -= mtd->erasesize;
+-
+- prandom_bytes_state(&rnd_state, writebuf, mtd->erasesize);
+- for (j = 0; j < pgcnt - 1; ++j, addr += pgsize) {
+- /* Do a read to set the internal dataRAMs to different data */
+- err = mtd_read(mtd, addr0, bufsize, &read, twopages);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != bufsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr0);
+- return err;
+- }
+- err = mtd_read(mtd, addrn - bufsize, bufsize, &read, twopages);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != bufsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)(addrn - bufsize));
+- return err;
+- }
+- memset(twopages, 0, bufsize);
+- err = mtd_read(mtd, addr, bufsize, &read, twopages);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != bufsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- break;
+- }
+- if (memcmp(twopages, writebuf + (j * pgsize), bufsize)) {
+- pr_err("error: verify failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- }
+- }
+- /* Check boundary between eraseblocks */
+- if (addr <= addrn - pgsize - pgsize && !bbt[ebnum + 1]) {
+- struct rnd_state old_state = rnd_state;
+-
+- /* Do a read to set the internal dataRAMs to different data */
+- err = mtd_read(mtd, addr0, bufsize, &read, twopages);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != bufsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr0);
+- return err;
+- }
+- err = mtd_read(mtd, addrn - bufsize, bufsize, &read, twopages);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != bufsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)(addrn - bufsize));
+- return err;
+- }
+- memset(twopages, 0, bufsize);
+- err = mtd_read(mtd, addr, bufsize, &read, twopages);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != bufsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- return err;
+- }
+- memcpy(boundary, writebuf + mtd->erasesize - pgsize, pgsize);
+- prandom_bytes_state(&rnd_state, boundary + pgsize, pgsize);
+- if (memcmp(twopages, boundary, bufsize)) {
+- pr_err("error: verify failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- }
+- rnd_state = old_state;
+- }
+- return err;
+-}
+-
+-static int crosstest(void)
+-{
+- size_t read;
+- int err = 0, i;
+- loff_t addr, addr0, addrn;
+- unsigned char *pp1, *pp2, *pp3, *pp4;
+-
+- pr_info("crosstest\n");
+- pp1 = kmalloc(pgsize * 4, GFP_KERNEL);
+- if (!pp1) {
+- pr_err("error: cannot allocate memory\n");
+- return -ENOMEM;
+- }
+- pp2 = pp1 + pgsize;
+- pp3 = pp2 + pgsize;
+- pp4 = pp3 + pgsize;
+- memset(pp1, 0, pgsize * 4);
+-
+- addr0 = 0;
+- for (i = 0; i < ebcnt && bbt[i]; ++i)
+- addr0 += mtd->erasesize;
+-
+- addrn = mtd->size;
+- for (i = 0; i < ebcnt && bbt[ebcnt - i - 1]; ++i)
+- addrn -= mtd->erasesize;
+-
+- /* Read 2nd-to-last page to pp1 */
+- addr = addrn - pgsize - pgsize;
+- err = mtd_read(mtd, addr, pgsize, &read, pp1);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- kfree(pp1);
+- return err;
+- }
+-
+- /* Read 3rd-to-last page to pp1 */
+- addr = addrn - pgsize - pgsize - pgsize;
+- err = mtd_read(mtd, addr, pgsize, &read, pp1);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- kfree(pp1);
+- return err;
+- }
+-
+- /* Read first page to pp2 */
+- addr = addr0;
+- pr_info("reading page at %#llx\n", (long long)addr);
+- err = mtd_read(mtd, addr, pgsize, &read, pp2);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- kfree(pp1);
+- return err;
+- }
+-
+- /* Read last page to pp3 */
+- addr = addrn - pgsize;
+- pr_info("reading page at %#llx\n", (long long)addr);
+- err = mtd_read(mtd, addr, pgsize, &read, pp3);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- kfree(pp1);
+- return err;
+- }
+-
+- /* Read first page again to pp4 */
+- addr = addr0;
+- pr_info("reading page at %#llx\n", (long long)addr);
+- err = mtd_read(mtd, addr, pgsize, &read, pp4);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- kfree(pp1);
+- return err;
+- }
+-
+- /* pp2 and pp4 should be the same */
+- pr_info("verifying pages read at %#llx match\n",
+- (long long)addr0);
+- if (memcmp(pp2, pp4, pgsize)) {
+- pr_err("verify failed!\n");
+- errcnt += 1;
+- } else if (!err)
+- pr_info("crosstest ok\n");
+- kfree(pp1);
+- return err;
+-}
+-
+-static int erasecrosstest(void)
+-{
+- size_t read, written;
+- int err = 0, i, ebnum, ebnum2;
+- loff_t addr0;
+- char *readbuf = twopages;
+-
+- pr_info("erasecrosstest\n");
+-
+- ebnum = 0;
+- addr0 = 0;
+- for (i = 0; i < ebcnt && bbt[i]; ++i) {
+- addr0 += mtd->erasesize;
+- ebnum += 1;
+- }
+-
+- ebnum2 = ebcnt - 1;
+- while (ebnum2 && bbt[ebnum2])
+- ebnum2 -= 1;
+-
+- pr_info("erasing block %d\n", ebnum);
+- err = erase_eraseblock(ebnum);
+- if (err)
+- return err;
+-
+- pr_info("writing 1st page of block %d\n", ebnum);
+- prandom_bytes_state(&rnd_state, writebuf, pgsize);
+- strcpy(writebuf, "There is no data like this!");
+- err = mtd_write(mtd, addr0, pgsize, &written, writebuf);
+- if (err || written != pgsize) {
+- pr_info("error: write failed at %#llx\n",
+- (long long)addr0);
+- return err ? err : -1;
+- }
+-
+- pr_info("reading 1st page of block %d\n", ebnum);
+- memset(readbuf, 0, pgsize);
+- err = mtd_read(mtd, addr0, pgsize, &read, readbuf);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr0);
+- return err ? err : -1;
+- }
+-
+- pr_info("verifying 1st page of block %d\n", ebnum);
+- if (memcmp(writebuf, readbuf, pgsize)) {
+- pr_err("verify failed!\n");
+- errcnt += 1;
+- return -1;
+- }
+-
+- pr_info("erasing block %d\n", ebnum);
+- err = erase_eraseblock(ebnum);
+- if (err)
+- return err;
+-
+- pr_info("writing 1st page of block %d\n", ebnum);
+- prandom_bytes_state(&rnd_state, writebuf, pgsize);
+- strcpy(writebuf, "There is no data like this!");
+- err = mtd_write(mtd, addr0, pgsize, &written, writebuf);
+- if (err || written != pgsize) {
+- pr_err("error: write failed at %#llx\n",
+- (long long)addr0);
+- return err ? err : -1;
+- }
+-
+- pr_info("erasing block %d\n", ebnum2);
+- err = erase_eraseblock(ebnum2);
+- if (err)
+- return err;
+-
+- pr_info("reading 1st page of block %d\n", ebnum);
+- memset(readbuf, 0, pgsize);
+- err = mtd_read(mtd, addr0, pgsize, &read, readbuf);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr0);
+- return err ? err : -1;
+- }
+-
+- pr_info("verifying 1st page of block %d\n", ebnum);
+- if (memcmp(writebuf, readbuf, pgsize)) {
+- pr_err("verify failed!\n");
+- errcnt += 1;
+- return -1;
+- }
+-
+- if (!err)
+- pr_info("erasecrosstest ok\n");
+- return err;
+-}
+-
+-static int erasetest(void)
+-{
+- size_t read, written;
+- int err = 0, i, ebnum, ok = 1;
+- loff_t addr0;
+-
+- pr_info("erasetest\n");
+-
+- ebnum = 0;
+- addr0 = 0;
+- for (i = 0; i < ebcnt && bbt[i]; ++i) {
+- addr0 += mtd->erasesize;
+- ebnum += 1;
+- }
+-
+- pr_info("erasing block %d\n", ebnum);
+- err = erase_eraseblock(ebnum);
+- if (err)
+- return err;
+-
+- pr_info("writing 1st page of block %d\n", ebnum);
+- prandom_bytes_state(&rnd_state, writebuf, pgsize);
+- err = mtd_write(mtd, addr0, pgsize, &written, writebuf);
+- if (err || written != pgsize) {
+- pr_err("error: write failed at %#llx\n",
+- (long long)addr0);
+- return err ? err : -1;
+- }
+-
+- pr_info("erasing block %d\n", ebnum);
+- err = erase_eraseblock(ebnum);
+- if (err)
+- return err;
+-
+- pr_info("reading 1st page of block %d\n", ebnum);
+- err = mtd_read(mtd, addr0, pgsize, &read, twopages);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr0);
+- return err ? err : -1;
+- }
+-
+- pr_info("verifying 1st page of block %d is all 0xff\n",
+- ebnum);
+- for (i = 0; i < pgsize; ++i)
+- if (twopages[i] != 0xff) {
+- pr_err("verifying all 0xff failed at %d\n",
+- i);
+- errcnt += 1;
+- ok = 0;
+- break;
+- }
+-
+- if (ok && !err)
+- pr_info("erasetest ok\n");
+-
+- return err;
+-}
+-
+-static int is_block_bad(int ebnum)
+-{
+- loff_t addr = ebnum * mtd->erasesize;
+- int ret;
+-
+- ret = mtd_block_isbad(mtd, addr);
+- if (ret)
+- pr_info("block %d is bad\n", ebnum);
+- return ret;
+-}
+-
+-static int scan_for_bad_eraseblocks(void)
+-{
+- int i, bad = 0;
+-
+- bbt = kzalloc(ebcnt, GFP_KERNEL);
+- if (!bbt) {
+- pr_err("error: cannot allocate memory\n");
+- return -ENOMEM;
+- }
+-
+- pr_info("scanning for bad eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- bbt[i] = is_block_bad(i) ? 1 : 0;
+- if (bbt[i])
+- bad += 1;
+- cond_resched();
+- }
+- pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
+- return 0;
+-}
+-
+-static int __init mtd_pagetest_init(void)
+-{
+- int err = 0;
+- uint64_t tmp;
+- uint32_t i;
+-
+- printk(KERN_INFO "\n");
+- printk(KERN_INFO "=================================================\n");
+-
+- if (dev < 0) {
+- pr_info("Please specify a valid mtd-device via module parameter\n");
+- pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
+- return -EINVAL;
+- }
+-
+- pr_info("MTD device: %d\n", dev);
+-
+- mtd = get_mtd_device(NULL, dev);
+- if (IS_ERR(mtd)) {
+- err = PTR_ERR(mtd);
+- pr_err("error: cannot get MTD device\n");
+- return err;
+- }
+-
+- if (mtd->type != MTD_NANDFLASH) {
+- pr_info("this test requires NAND flash\n");
+- goto out;
+- }
+-
+- tmp = mtd->size;
+- do_div(tmp, mtd->erasesize);
+- ebcnt = tmp;
+- pgcnt = mtd->erasesize / mtd->writesize;
+- pgsize = mtd->writesize;
+-
+- pr_info("MTD device size %llu, eraseblock size %u, "
+- "page size %u, count of eraseblocks %u, pages per "
+- "eraseblock %u, OOB size %u\n",
+- (unsigned long long)mtd->size, mtd->erasesize,
+- pgsize, ebcnt, pgcnt, mtd->oobsize);
+-
+- err = -ENOMEM;
+- bufsize = pgsize * 2;
+- writebuf = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!writebuf) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+- twopages = kmalloc(bufsize, GFP_KERNEL);
+- if (!twopages) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+- boundary = kmalloc(bufsize, GFP_KERNEL);
+- if (!boundary) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+-
+- err = scan_for_bad_eraseblocks();
+- if (err)
+- goto out;
+-
+- /* Erase all eraseblocks */
+- pr_info("erasing whole device\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = erase_eraseblock(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- pr_info("erased %u eraseblocks\n", i);
+-
+- /* Write all eraseblocks */
+- prandom_seed_state(&rnd_state, 1);
+- pr_info("writing whole device\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = write_eraseblock(i);
+- if (err)
+- goto out;
+- if (i % 256 == 0)
+- pr_info("written up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("written %u eraseblocks\n", i);
+-
+- /* Check all eraseblocks */
+- prandom_seed_state(&rnd_state, 1);
+- pr_info("verifying all eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = verify_eraseblock(i);
+- if (err)
+- goto out;
+- if (i % 256 == 0)
+- pr_info("verified up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("verified %u eraseblocks\n", i);
+-
+- err = crosstest();
+- if (err)
+- goto out;
+-
+- err = erasecrosstest();
+- if (err)
+- goto out;
+-
+- err = erasetest();
+- if (err)
+- goto out;
+-
+- pr_info("finished with %d errors\n", errcnt);
+-out:
+-
+- kfree(bbt);
+- kfree(boundary);
+- kfree(twopages);
+- kfree(writebuf);
+- put_mtd_device(mtd);
+- if (err)
+- pr_info("error %d occurred\n", err);
+- printk(KERN_INFO "=================================================\n");
+- return err;
+-}
+-module_init(mtd_pagetest_init);
+-
+-static void __exit mtd_pagetest_exit(void)
+-{
+- return;
+-}
+-module_exit(mtd_pagetest_exit);
+-
+-MODULE_DESCRIPTION("NAND page test");
+-MODULE_AUTHOR("Adrian Hunter");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_readtest.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_readtest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_readtest.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_readtest.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,263 +0,0 @@
+-/*
+- * Copyright (C) 2006-2008 Nokia Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; see the file COPYING. If not, write to the Free Software
+- * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- *
+- * Check MTD device read.
+- *
+- * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/err.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/slab.h>
+-#include <linux/sched.h>
+-
+-static int dev = -EINVAL;
+-module_param(dev, int, S_IRUGO);
+-MODULE_PARM_DESC(dev, "MTD device number to use");
+-
+-static struct mtd_info *mtd;
+-static unsigned char *iobuf;
+-static unsigned char *iobuf1;
+-static unsigned char *bbt;
+-
+-static int pgsize;
+-static int ebcnt;
+-static int pgcnt;
+-
+-static int read_eraseblock_by_page(int ebnum)
+-{
+- size_t read;
+- int i, ret, err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+- void *buf = iobuf;
+- void *oobbuf = iobuf1;
+-
+- for (i = 0; i < pgcnt; i++) {
+- memset(buf, 0 , pgsize);
+- ret = mtd_read(mtd, addr, pgsize, &read, buf);
+- if (ret == -EUCLEAN)
+- ret = 0;
+- if (ret || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- if (!err)
+- err = ret;
+- if (!err)
+- err = -EINVAL;
+- }
+- if (mtd->oobsize) {
+- struct mtd_oob_ops ops;
+-
+- ops.mode = MTD_OPS_PLACE_OOB;
+- ops.len = 0;
+- ops.retlen = 0;
+- ops.ooblen = mtd->oobsize;
+- ops.oobretlen = 0;
+- ops.ooboffs = 0;
+- ops.datbuf = NULL;
+- ops.oobbuf = oobbuf;
+- ret = mtd_read_oob(mtd, addr, &ops);
+- if ((ret && !mtd_is_bitflip(ret)) ||
+- ops.oobretlen != mtd->oobsize) {
+- pr_err("error: read oob failed at "
+- "%#llx\n", (long long)addr);
+- if (!err)
+- err = ret;
+- if (!err)
+- err = -EINVAL;
+- }
+- oobbuf += mtd->oobsize;
+- }
+- addr += pgsize;
+- buf += pgsize;
+- }
+-
+- return err;
+-}
+-
+-static void dump_eraseblock(int ebnum)
+-{
+- int i, j, n;
+- char line[128];
+- int pg, oob;
+-
+- pr_info("dumping eraseblock %d\n", ebnum);
+- n = mtd->erasesize;
+- for (i = 0; i < n;) {
+- char *p = line;
+-
+- p += sprintf(p, "%05x: ", i);
+- for (j = 0; j < 32 && i < n; j++, i++)
+- p += sprintf(p, "%02x", (unsigned int)iobuf[i]);
+- printk(KERN_CRIT "%s\n", line);
+- cond_resched();
+- }
+- if (!mtd->oobsize)
+- return;
+- pr_info("dumping oob from eraseblock %d\n", ebnum);
+- n = mtd->oobsize;
+- for (pg = 0, i = 0; pg < pgcnt; pg++)
+- for (oob = 0; oob < n;) {
+- char *p = line;
+-
+- p += sprintf(p, "%05x: ", i);
+- for (j = 0; j < 32 && oob < n; j++, oob++, i++)
+- p += sprintf(p, "%02x",
+- (unsigned int)iobuf1[i]);
+- printk(KERN_CRIT "%s\n", line);
+- cond_resched();
+- }
+-}
+-
+-static int is_block_bad(int ebnum)
+-{
+- loff_t addr = ebnum * mtd->erasesize;
+- int ret;
+-
+- ret = mtd_block_isbad(mtd, addr);
+- if (ret)
+- pr_info("block %d is bad\n", ebnum);
+- return ret;
+-}
+-
+-static int scan_for_bad_eraseblocks(void)
+-{
+- int i, bad = 0;
+-
+- bbt = kzalloc(ebcnt, GFP_KERNEL);
+- if (!bbt) {
+- pr_err("error: cannot allocate memory\n");
+- return -ENOMEM;
+- }
+-
+- if (!mtd_can_have_bb(mtd))
+- return 0;
+-
+- pr_info("scanning for bad eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- bbt[i] = is_block_bad(i) ? 1 : 0;
+- if (bbt[i])
+- bad += 1;
+- cond_resched();
+- }
+- pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
+- return 0;
+-}
+-
+-static int __init mtd_readtest_init(void)
+-{
+- uint64_t tmp;
+- int err, i;
+-
+- printk(KERN_INFO "\n");
+- printk(KERN_INFO "=================================================\n");
+-
+- if (dev < 0) {
+- pr_info("Please specify a valid mtd-device via module parameter\n");
+- return -EINVAL;
+- }
+-
+- pr_info("MTD device: %d\n", dev);
+-
+- mtd = get_mtd_device(NULL, dev);
+- if (IS_ERR(mtd)) {
+- err = PTR_ERR(mtd);
+- pr_err("error: Cannot get MTD device\n");
+- return err;
+- }
+-
+- if (mtd->writesize == 1) {
+- pr_info("not NAND flash, assume page size is 512 "
+- "bytes.\n");
+- pgsize = 512;
+- } else
+- pgsize = mtd->writesize;
+-
+- tmp = mtd->size;
+- do_div(tmp, mtd->erasesize);
+- ebcnt = tmp;
+- pgcnt = mtd->erasesize / pgsize;
+-
+- pr_info("MTD device size %llu, eraseblock size %u, "
+- "page size %u, count of eraseblocks %u, pages per "
+- "eraseblock %u, OOB size %u\n",
+- (unsigned long long)mtd->size, mtd->erasesize,
+- pgsize, ebcnt, pgcnt, mtd->oobsize);
+-
+- err = -ENOMEM;
+- iobuf = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!iobuf) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+- iobuf1 = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!iobuf1) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+-
+- err = scan_for_bad_eraseblocks();
+- if (err)
+- goto out;
+-
+- /* Read all eraseblocks 1 page at a time */
+- pr_info("testing page read\n");
+- for (i = 0; i < ebcnt; ++i) {
+- int ret;
+-
+- if (bbt[i])
+- continue;
+- ret = read_eraseblock_by_page(i);
+- if (ret) {
+- dump_eraseblock(i);
+- if (!err)
+- err = ret;
+- }
+- cond_resched();
+- }
+-
+- if (err)
+- pr_info("finished with errors\n");
+- else
+- pr_info("finished\n");
+-
+-out:
+-
+- kfree(iobuf);
+- kfree(iobuf1);
+- kfree(bbt);
+- put_mtd_device(mtd);
+- if (err)
+- pr_info("error %d occurred\n", err);
+- printk(KERN_INFO "=================================================\n");
+- return err;
+-}
+-module_init(mtd_readtest_init);
+-
+-static void __exit mtd_readtest_exit(void)
+-{
+- return;
+-}
+-module_exit(mtd_readtest_exit);
+-
+-MODULE_DESCRIPTION("Read test module");
+-MODULE_AUTHOR("Adrian Hunter");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_speedtest.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_speedtest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_speedtest.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_speedtest.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,560 +0,0 @@
+-/*
+- * Copyright (C) 2007 Nokia Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; see the file COPYING. If not, write to the Free Software
+- * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- *
+- * Test read and write speed of a MTD device.
+- *
+- * Author: Adrian Hunter <adrian.hunter@nokia.com>
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/err.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/slab.h>
+-#include <linux/sched.h>
+-#include <linux/random.h>
+-
+-static int dev = -EINVAL;
+-module_param(dev, int, S_IRUGO);
+-MODULE_PARM_DESC(dev, "MTD device number to use");
+-
+-static int count;
+-module_param(count, int, S_IRUGO);
+-MODULE_PARM_DESC(count, "Maximum number of eraseblocks to use "
+- "(0 means use all)");
+-
+-static struct mtd_info *mtd;
+-static unsigned char *iobuf;
+-static unsigned char *bbt;
+-
+-static int pgsize;
+-static int ebcnt;
+-static int pgcnt;
+-static int goodebcnt;
+-static struct timeval start, finish;
+-
+-
+-static int erase_eraseblock(int ebnum)
+-{
+- int err;
+- struct erase_info ei;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- memset(&ei, 0, sizeof(struct erase_info));
+- ei.mtd = mtd;
+- ei.addr = addr;
+- ei.len = mtd->erasesize;
+-
+- err = mtd_erase(mtd, &ei);
+- if (err) {
+- pr_err("error %d while erasing EB %d\n", err, ebnum);
+- return err;
+- }
+-
+- if (ei.state == MTD_ERASE_FAILED) {
+- pr_err("some erase error occurred at EB %d\n",
+- ebnum);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-static int multiblock_erase(int ebnum, int blocks)
+-{
+- int err;
+- struct erase_info ei;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- memset(&ei, 0, sizeof(struct erase_info));
+- ei.mtd = mtd;
+- ei.addr = addr;
+- ei.len = mtd->erasesize * blocks;
+-
+- err = mtd_erase(mtd, &ei);
+- if (err) {
+- pr_err("error %d while erasing EB %d, blocks %d\n",
+- err, ebnum, blocks);
+- return err;
+- }
+-
+- if (ei.state == MTD_ERASE_FAILED) {
+- pr_err("some erase error occurred at EB %d,"
+- "blocks %d\n", ebnum, blocks);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-static int erase_whole_device(void)
+-{
+- int err;
+- unsigned int i;
+-
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = erase_eraseblock(i);
+- if (err)
+- return err;
+- cond_resched();
+- }
+- return 0;
+-}
+-
+-static int write_eraseblock(int ebnum)
+-{
+- size_t written;
+- int err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- err = mtd_write(mtd, addr, mtd->erasesize, &written, iobuf);
+- if (err || written != mtd->erasesize) {
+- pr_err("error: write failed at %#llx\n", addr);
+- if (!err)
+- err = -EINVAL;
+- }
+-
+- return err;
+-}
+-
+-static int write_eraseblock_by_page(int ebnum)
+-{
+- size_t written;
+- int i, err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+- void *buf = iobuf;
+-
+- for (i = 0; i < pgcnt; i++) {
+- err = mtd_write(mtd, addr, pgsize, &written, buf);
+- if (err || written != pgsize) {
+- pr_err("error: write failed at %#llx\n",
+- addr);
+- if (!err)
+- err = -EINVAL;
+- break;
+- }
+- addr += pgsize;
+- buf += pgsize;
+- }
+-
+- return err;
+-}
+-
+-static int write_eraseblock_by_2pages(int ebnum)
+-{
+- size_t written, sz = pgsize * 2;
+- int i, n = pgcnt / 2, err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+- void *buf = iobuf;
+-
+- for (i = 0; i < n; i++) {
+- err = mtd_write(mtd, addr, sz, &written, buf);
+- if (err || written != sz) {
+- pr_err("error: write failed at %#llx\n",
+- addr);
+- if (!err)
+- err = -EINVAL;
+- return err;
+- }
+- addr += sz;
+- buf += sz;
+- }
+- if (pgcnt % 2) {
+- err = mtd_write(mtd, addr, pgsize, &written, buf);
+- if (err || written != pgsize) {
+- pr_err("error: write failed at %#llx\n",
+- addr);
+- if (!err)
+- err = -EINVAL;
+- }
+- }
+-
+- return err;
+-}
+-
+-static int read_eraseblock(int ebnum)
+-{
+- size_t read;
+- int err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- err = mtd_read(mtd, addr, mtd->erasesize, &read, iobuf);
+- /* Ignore corrected ECC errors */
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != mtd->erasesize) {
+- pr_err("error: read failed at %#llx\n", addr);
+- if (!err)
+- err = -EINVAL;
+- }
+-
+- return err;
+-}
+-
+-static int read_eraseblock_by_page(int ebnum)
+-{
+- size_t read;
+- int i, err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+- void *buf = iobuf;
+-
+- for (i = 0; i < pgcnt; i++) {
+- err = mtd_read(mtd, addr, pgsize, &read, buf);
+- /* Ignore corrected ECC errors */
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- addr);
+- if (!err)
+- err = -EINVAL;
+- break;
+- }
+- addr += pgsize;
+- buf += pgsize;
+- }
+-
+- return err;
+-}
+-
+-static int read_eraseblock_by_2pages(int ebnum)
+-{
+- size_t read, sz = pgsize * 2;
+- int i, n = pgcnt / 2, err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+- void *buf = iobuf;
+-
+- for (i = 0; i < n; i++) {
+- err = mtd_read(mtd, addr, sz, &read, buf);
+- /* Ignore corrected ECC errors */
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != sz) {
+- pr_err("error: read failed at %#llx\n",
+- addr);
+- if (!err)
+- err = -EINVAL;
+- return err;
+- }
+- addr += sz;
+- buf += sz;
+- }
+- if (pgcnt % 2) {
+- err = mtd_read(mtd, addr, pgsize, &read, buf);
+- /* Ignore corrected ECC errors */
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (err || read != pgsize) {
+- pr_err("error: read failed at %#llx\n",
+- addr);
+- if (!err)
+- err = -EINVAL;
+- }
+- }
+-
+- return err;
+-}
+-
+-static int is_block_bad(int ebnum)
+-{
+- loff_t addr = ebnum * mtd->erasesize;
+- int ret;
+-
+- ret = mtd_block_isbad(mtd, addr);
+- if (ret)
+- pr_info("block %d is bad\n", ebnum);
+- return ret;
+-}
+-
+-static inline void start_timing(void)
+-{
+- do_gettimeofday(&start);
+-}
+-
+-static inline void stop_timing(void)
+-{
+- do_gettimeofday(&finish);
+-}
+-
+-static long calc_speed(void)
+-{
+- uint64_t k;
+- long ms;
+-
+- ms = (finish.tv_sec - start.tv_sec) * 1000 +
+- (finish.tv_usec - start.tv_usec) / 1000;
+- if (ms == 0)
+- return 0;
+- k = goodebcnt * (mtd->erasesize / 1024) * 1000;
+- do_div(k, ms);
+- return k;
+-}
+-
+-static int scan_for_bad_eraseblocks(void)
+-{
+- int i, bad = 0;
+-
+- bbt = kzalloc(ebcnt, GFP_KERNEL);
+- if (!bbt) {
+- pr_err("error: cannot allocate memory\n");
+- return -ENOMEM;
+- }
+-
+- if (!mtd_can_have_bb(mtd))
+- goto out;
+-
+- pr_info("scanning for bad eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- bbt[i] = is_block_bad(i) ? 1 : 0;
+- if (bbt[i])
+- bad += 1;
+- cond_resched();
+- }
+- pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
+-out:
+- goodebcnt = ebcnt - bad;
+- return 0;
+-}
+-
+-static int __init mtd_speedtest_init(void)
+-{
+- int err, i, blocks, j, k;
+- long speed;
+- uint64_t tmp;
+-
+- printk(KERN_INFO "\n");
+- printk(KERN_INFO "=================================================\n");
+-
+- if (dev < 0) {
+- pr_info("Please specify a valid mtd-device via module parameter\n");
+- pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
+- return -EINVAL;
+- }
+-
+- if (count)
+- pr_info("MTD device: %d count: %d\n", dev, count);
+- else
+- pr_info("MTD device: %d\n", dev);
+-
+- mtd = get_mtd_device(NULL, dev);
+- if (IS_ERR(mtd)) {
+- err = PTR_ERR(mtd);
+- pr_err("error: cannot get MTD device\n");
+- return err;
+- }
+-
+- if (mtd->writesize == 1) {
+- pr_info("not NAND flash, assume page size is 512 "
+- "bytes.\n");
+- pgsize = 512;
+- } else
+- pgsize = mtd->writesize;
+-
+- tmp = mtd->size;
+- do_div(tmp, mtd->erasesize);
+- ebcnt = tmp;
+- pgcnt = mtd->erasesize / pgsize;
+-
+- pr_info("MTD device size %llu, eraseblock size %u, "
+- "page size %u, count of eraseblocks %u, pages per "
+- "eraseblock %u, OOB size %u\n",
+- (unsigned long long)mtd->size, mtd->erasesize,
+- pgsize, ebcnt, pgcnt, mtd->oobsize);
+-
+- if (count > 0 && count < ebcnt)
+- ebcnt = count;
+-
+- err = -ENOMEM;
+- iobuf = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!iobuf) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+-
+- prandom_bytes(iobuf, mtd->erasesize);
+-
+- err = scan_for_bad_eraseblocks();
+- if (err)
+- goto out;
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- /* Write all eraseblocks, 1 eraseblock at a time */
+- pr_info("testing eraseblock write speed\n");
+- start_timing();
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = write_eraseblock(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- stop_timing();
+- speed = calc_speed();
+- pr_info("eraseblock write speed is %ld KiB/s\n", speed);
+-
+- /* Read all eraseblocks, 1 eraseblock at a time */
+- pr_info("testing eraseblock read speed\n");
+- start_timing();
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = read_eraseblock(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- stop_timing();
+- speed = calc_speed();
+- pr_info("eraseblock read speed is %ld KiB/s\n", speed);
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- /* Write all eraseblocks, 1 page at a time */
+- pr_info("testing page write speed\n");
+- start_timing();
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = write_eraseblock_by_page(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- stop_timing();
+- speed = calc_speed();
+- pr_info("page write speed is %ld KiB/s\n", speed);
+-
+- /* Read all eraseblocks, 1 page at a time */
+- pr_info("testing page read speed\n");
+- start_timing();
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = read_eraseblock_by_page(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- stop_timing();
+- speed = calc_speed();
+- pr_info("page read speed is %ld KiB/s\n", speed);
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- /* Write all eraseblocks, 2 pages at a time */
+- pr_info("testing 2 page write speed\n");
+- start_timing();
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = write_eraseblock_by_2pages(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- stop_timing();
+- speed = calc_speed();
+- pr_info("2 page write speed is %ld KiB/s\n", speed);
+-
+- /* Read all eraseblocks, 2 pages at a time */
+- pr_info("testing 2 page read speed\n");
+- start_timing();
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = read_eraseblock_by_2pages(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- stop_timing();
+- speed = calc_speed();
+- pr_info("2 page read speed is %ld KiB/s\n", speed);
+-
+- /* Erase all eraseblocks */
+- pr_info("Testing erase speed\n");
+- start_timing();
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = erase_eraseblock(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- stop_timing();
+- speed = calc_speed();
+- pr_info("erase speed is %ld KiB/s\n", speed);
+-
+- /* Multi-block erase all eraseblocks */
+- for (k = 1; k < 7; k++) {
+- blocks = 1 << k;
+- pr_info("Testing %dx multi-block erase speed\n",
+- blocks);
+- start_timing();
+- for (i = 0; i < ebcnt; ) {
+- for (j = 0; j < blocks && (i + j) < ebcnt; j++)
+- if (bbt[i + j])
+- break;
+- if (j < 1) {
+- i++;
+- continue;
+- }
+- err = multiblock_erase(i, j);
+- if (err)
+- goto out;
+- cond_resched();
+- i += j;
+- }
+- stop_timing();
+- speed = calc_speed();
+- pr_info("%dx multi-block erase speed is %ld KiB/s\n",
+- blocks, speed);
+- }
+- pr_info("finished\n");
+-out:
+- kfree(iobuf);
+- kfree(bbt);
+- put_mtd_device(mtd);
+- if (err)
+- pr_info("error %d occurred\n", err);
+- printk(KERN_INFO "=================================================\n");
+- return err;
+-}
+-module_init(mtd_speedtest_init);
+-
+-static void __exit mtd_speedtest_exit(void)
+-{
+- return;
+-}
+-module_exit(mtd_speedtest_exit);
+-
+-MODULE_DESCRIPTION("Speed test module");
+-MODULE_AUTHOR("Adrian Hunter");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_stresstest.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_stresstest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_stresstest.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_stresstest.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,325 +0,0 @@
+-/*
+- * Copyright (C) 2006-2008 Nokia Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; see the file COPYING. If not, write to the Free Software
+- * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- *
+- * Test random reads, writes and erases on MTD device.
+- *
+- * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/err.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/slab.h>
+-#include <linux/sched.h>
+-#include <linux/vmalloc.h>
+-#include <linux/random.h>
+-
+-static int dev = -EINVAL;
+-module_param(dev, int, S_IRUGO);
+-MODULE_PARM_DESC(dev, "MTD device number to use");
+-
+-static int count = 10000;
+-module_param(count, int, S_IRUGO);
+-MODULE_PARM_DESC(count, "Number of operations to do (default is 10000)");
+-
+-static struct mtd_info *mtd;
+-static unsigned char *writebuf;
+-static unsigned char *readbuf;
+-static unsigned char *bbt;
+-static int *offsets;
+-
+-static int pgsize;
+-static int bufsize;
+-static int ebcnt;
+-static int pgcnt;
+-
+-static int rand_eb(void)
+-{
+- unsigned int eb;
+-
+-again:
+- eb = prandom_u32();
+- /* Read or write up 2 eraseblocks at a time - hence 'ebcnt - 1' */
+- eb %= (ebcnt - 1);
+- if (bbt[eb])
+- goto again;
+- return eb;
+-}
+-
+-static int rand_offs(void)
+-{
+- unsigned int offs;
+-
+- offs = prandom_u32();
+- offs %= bufsize;
+- return offs;
+-}
+-
+-static int rand_len(int offs)
+-{
+- unsigned int len;
+-
+- len = prandom_u32();
+- len %= (bufsize - offs);
+- return len;
+-}
+-
+-static int erase_eraseblock(int ebnum)
+-{
+- int err;
+- struct erase_info ei;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- memset(&ei, 0, sizeof(struct erase_info));
+- ei.mtd = mtd;
+- ei.addr = addr;
+- ei.len = mtd->erasesize;
+-
+- err = mtd_erase(mtd, &ei);
+- if (unlikely(err)) {
+- pr_err("error %d while erasing EB %d\n", err, ebnum);
+- return err;
+- }
+-
+- if (unlikely(ei.state == MTD_ERASE_FAILED)) {
+- pr_err("some erase error occurred at EB %d\n",
+- ebnum);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-static int is_block_bad(int ebnum)
+-{
+- loff_t addr = ebnum * mtd->erasesize;
+- int ret;
+-
+- ret = mtd_block_isbad(mtd, addr);
+- if (ret)
+- pr_info("block %d is bad\n", ebnum);
+- return ret;
+-}
+-
+-static int do_read(void)
+-{
+- size_t read;
+- int eb = rand_eb();
+- int offs = rand_offs();
+- int len = rand_len(offs), err;
+- loff_t addr;
+-
+- if (bbt[eb + 1]) {
+- if (offs >= mtd->erasesize)
+- offs -= mtd->erasesize;
+- if (offs + len > mtd->erasesize)
+- len = mtd->erasesize - offs;
+- }
+- addr = eb * mtd->erasesize + offs;
+- err = mtd_read(mtd, addr, len, &read, readbuf);
+- if (mtd_is_bitflip(err))
+- err = 0;
+- if (unlikely(err || read != len)) {
+- pr_err("error: read failed at 0x%llx\n",
+- (long long)addr);
+- if (!err)
+- err = -EINVAL;
+- return err;
+- }
+- return 0;
+-}
+-
+-static int do_write(void)
+-{
+- int eb = rand_eb(), offs, err, len;
+- size_t written;
+- loff_t addr;
+-
+- offs = offsets[eb];
+- if (offs >= mtd->erasesize) {
+- err = erase_eraseblock(eb);
+- if (err)
+- return err;
+- offs = offsets[eb] = 0;
+- }
+- len = rand_len(offs);
+- len = ((len + pgsize - 1) / pgsize) * pgsize;
+- if (offs + len > mtd->erasesize) {
+- if (bbt[eb + 1])
+- len = mtd->erasesize - offs;
+- else {
+- err = erase_eraseblock(eb + 1);
+- if (err)
+- return err;
+- offsets[eb + 1] = 0;
+- }
+- }
+- addr = eb * mtd->erasesize + offs;
+- err = mtd_write(mtd, addr, len, &written, writebuf);
+- if (unlikely(err || written != len)) {
+- pr_err("error: write failed at 0x%llx\n",
+- (long long)addr);
+- if (!err)
+- err = -EINVAL;
+- return err;
+- }
+- offs += len;
+- while (offs > mtd->erasesize) {
+- offsets[eb++] = mtd->erasesize;
+- offs -= mtd->erasesize;
+- }
+- offsets[eb] = offs;
+- return 0;
+-}
+-
+-static int do_operation(void)
+-{
+- if (prandom_u32() & 1)
+- return do_read();
+- else
+- return do_write();
+-}
+-
+-static int scan_for_bad_eraseblocks(void)
+-{
+- int i, bad = 0;
+-
+- bbt = kzalloc(ebcnt, GFP_KERNEL);
+- if (!bbt) {
+- pr_err("error: cannot allocate memory\n");
+- return -ENOMEM;
+- }
+-
+- if (!mtd_can_have_bb(mtd))
+- return 0;
+-
+- pr_info("scanning for bad eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- bbt[i] = is_block_bad(i) ? 1 : 0;
+- if (bbt[i])
+- bad += 1;
+- cond_resched();
+- }
+- pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
+- return 0;
+-}
+-
+-static int __init mtd_stresstest_init(void)
+-{
+- int err;
+- int i, op;
+- uint64_t tmp;
+-
+- printk(KERN_INFO "\n");
+- printk(KERN_INFO "=================================================\n");
+-
+- if (dev < 0) {
+- pr_info("Please specify a valid mtd-device via module parameter\n");
+- pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
+- return -EINVAL;
+- }
+-
+- pr_info("MTD device: %d\n", dev);
+-
+- mtd = get_mtd_device(NULL, dev);
+- if (IS_ERR(mtd)) {
+- err = PTR_ERR(mtd);
+- pr_err("error: cannot get MTD device\n");
+- return err;
+- }
+-
+- if (mtd->writesize == 1) {
+- pr_info("not NAND flash, assume page size is 512 "
+- "bytes.\n");
+- pgsize = 512;
+- } else
+- pgsize = mtd->writesize;
+-
+- tmp = mtd->size;
+- do_div(tmp, mtd->erasesize);
+- ebcnt = tmp;
+- pgcnt = mtd->erasesize / pgsize;
+-
+- pr_info("MTD device size %llu, eraseblock size %u, "
+- "page size %u, count of eraseblocks %u, pages per "
+- "eraseblock %u, OOB size %u\n",
+- (unsigned long long)mtd->size, mtd->erasesize,
+- pgsize, ebcnt, pgcnt, mtd->oobsize);
+-
+- if (ebcnt < 2) {
+- pr_err("error: need at least 2 eraseblocks\n");
+- err = -ENOSPC;
+- goto out_put_mtd;
+- }
+-
+- /* Read or write up 2 eraseblocks at a time */
+- bufsize = mtd->erasesize * 2;
+-
+- err = -ENOMEM;
+- readbuf = vmalloc(bufsize);
+- writebuf = vmalloc(bufsize);
+- offsets = kmalloc(ebcnt * sizeof(int), GFP_KERNEL);
+- if (!readbuf || !writebuf || !offsets) {
+- pr_err("error: cannot allocate memory\n");
+- goto out;
+- }
+- for (i = 0; i < ebcnt; i++)
+- offsets[i] = mtd->erasesize;
+- prandom_bytes(writebuf, bufsize);
+-
+- err = scan_for_bad_eraseblocks();
+- if (err)
+- goto out;
+-
+- /* Do operations */
+- pr_info("doing operations\n");
+- for (op = 0; op < count; op++) {
+- if ((op & 1023) == 0)
+- pr_info("%d operations done\n", op);
+- err = do_operation();
+- if (err)
+- goto out;
+- cond_resched();
+- }
+- pr_info("finished, %d operations done\n", op);
+-
+-out:
+- kfree(offsets);
+- kfree(bbt);
+- vfree(writebuf);
+- vfree(readbuf);
+-out_put_mtd:
+- put_mtd_device(mtd);
+- if (err)
+- pr_info("error %d occurred\n", err);
+- printk(KERN_INFO "=================================================\n");
+- return err;
+-}
+-module_init(mtd_stresstest_init);
+-
+-static void __exit mtd_stresstest_exit(void)
+-{
+- return;
+-}
+-module_exit(mtd_stresstest_exit);
+-
+-MODULE_DESCRIPTION("Stress test module");
+-MODULE_AUTHOR("Adrian Hunter");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_subpagetest.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_subpagetest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_subpagetest.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_subpagetest.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,510 +0,0 @@
+-/*
+- * Copyright (C) 2006-2007 Nokia Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; see the file COPYING. If not, write to the Free Software
+- * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- *
+- * Test sub-page read and write on MTD device.
+- * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
+- *
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/err.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/slab.h>
+-#include <linux/sched.h>
+-#include <linux/random.h>
+-
+-static int dev = -EINVAL;
+-module_param(dev, int, S_IRUGO);
+-MODULE_PARM_DESC(dev, "MTD device number to use");
+-
+-static struct mtd_info *mtd;
+-static unsigned char *writebuf;
+-static unsigned char *readbuf;
+-static unsigned char *bbt;
+-
+-static int subpgsize;
+-static int bufsize;
+-static int ebcnt;
+-static int pgcnt;
+-static int errcnt;
+-static struct rnd_state rnd_state;
+-
+-static inline void clear_data(unsigned char *buf, size_t len)
+-{
+- memset(buf, 0, len);
+-}
+-
+-static int erase_eraseblock(int ebnum)
+-{
+- int err;
+- struct erase_info ei;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- memset(&ei, 0, sizeof(struct erase_info));
+- ei.mtd = mtd;
+- ei.addr = addr;
+- ei.len = mtd->erasesize;
+-
+- err = mtd_erase(mtd, &ei);
+- if (err) {
+- pr_err("error %d while erasing EB %d\n", err, ebnum);
+- return err;
+- }
+-
+- if (ei.state == MTD_ERASE_FAILED) {
+- pr_err("some erase error occurred at EB %d\n",
+- ebnum);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-static int erase_whole_device(void)
+-{
+- int err;
+- unsigned int i;
+-
+- pr_info("erasing whole device\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = erase_eraseblock(i);
+- if (err)
+- return err;
+- cond_resched();
+- }
+- pr_info("erased %u eraseblocks\n", i);
+- return 0;
+-}
+-
+-static int write_eraseblock(int ebnum)
+-{
+- size_t written;
+- int err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- prandom_bytes_state(&rnd_state, writebuf, subpgsize);
+- err = mtd_write(mtd, addr, subpgsize, &written, writebuf);
+- if (unlikely(err || written != subpgsize)) {
+- pr_err("error: write failed at %#llx\n",
+- (long long)addr);
+- if (written != subpgsize) {
+- pr_err(" write size: %#x\n", subpgsize);
+- pr_err(" written: %#zx\n", written);
+- }
+- return err ? err : -1;
+- }
+-
+- addr += subpgsize;
+-
+- prandom_bytes_state(&rnd_state, writebuf, subpgsize);
+- err = mtd_write(mtd, addr, subpgsize, &written, writebuf);
+- if (unlikely(err || written != subpgsize)) {
+- pr_err("error: write failed at %#llx\n",
+- (long long)addr);
+- if (written != subpgsize) {
+- pr_err(" write size: %#x\n", subpgsize);
+- pr_err(" written: %#zx\n", written);
+- }
+- return err ? err : -1;
+- }
+-
+- return err;
+-}
+-
+-static int write_eraseblock2(int ebnum)
+-{
+- size_t written;
+- int err = 0, k;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- for (k = 1; k < 33; ++k) {
+- if (addr + (subpgsize * k) > (ebnum + 1) * mtd->erasesize)
+- break;
+- prandom_bytes_state(&rnd_state, writebuf, subpgsize * k);
+- err = mtd_write(mtd, addr, subpgsize * k, &written, writebuf);
+- if (unlikely(err || written != subpgsize * k)) {
+- pr_err("error: write failed at %#llx\n",
+- (long long)addr);
+- if (written != subpgsize) {
+- pr_err(" write size: %#x\n",
+- subpgsize * k);
+- pr_err(" written: %#08zx\n",
+- written);
+- }
+- return err ? err : -1;
+- }
+- addr += subpgsize * k;
+- }
+-
+- return err;
+-}
+-
+-static void print_subpage(unsigned char *p)
+-{
+- int i, j;
+-
+- for (i = 0; i < subpgsize; ) {
+- for (j = 0; i < subpgsize && j < 32; ++i, ++j)
+- printk("%02x", *p++);
+- printk("\n");
+- }
+-}
+-
+-static int verify_eraseblock(int ebnum)
+-{
+- size_t read;
+- int err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- prandom_bytes_state(&rnd_state, writebuf, subpgsize);
+- clear_data(readbuf, subpgsize);
+- err = mtd_read(mtd, addr, subpgsize, &read, readbuf);
+- if (unlikely(err || read != subpgsize)) {
+- if (mtd_is_bitflip(err) && read == subpgsize) {
+- pr_info("ECC correction at %#llx\n",
+- (long long)addr);
+- err = 0;
+- } else {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- return err ? err : -1;
+- }
+- }
+- if (unlikely(memcmp(readbuf, writebuf, subpgsize))) {
+- pr_err("error: verify failed at %#llx\n",
+- (long long)addr);
+- pr_info("------------- written----------------\n");
+- print_subpage(writebuf);
+- pr_info("------------- read ------------------\n");
+- print_subpage(readbuf);
+- pr_info("-------------------------------------\n");
+- errcnt += 1;
+- }
+-
+- addr += subpgsize;
+-
+- prandom_bytes_state(&rnd_state, writebuf, subpgsize);
+- clear_data(readbuf, subpgsize);
+- err = mtd_read(mtd, addr, subpgsize, &read, readbuf);
+- if (unlikely(err || read != subpgsize)) {
+- if (mtd_is_bitflip(err) && read == subpgsize) {
+- pr_info("ECC correction at %#llx\n",
+- (long long)addr);
+- err = 0;
+- } else {
+- pr_err("error: read failed at %#llx\n",
+- (long long)addr);
+- return err ? err : -1;
+- }
+- }
+- if (unlikely(memcmp(readbuf, writebuf, subpgsize))) {
+- pr_info("error: verify failed at %#llx\n",
+- (long long)addr);
+- pr_info("------------- written----------------\n");
+- print_subpage(writebuf);
+- pr_info("------------- read ------------------\n");
+- print_subpage(readbuf);
+- pr_info("-------------------------------------\n");
+- errcnt += 1;
+- }
+-
+- return err;
+-}
+-
+-static int verify_eraseblock2(int ebnum)
+-{
+- size_t read;
+- int err = 0, k;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- for (k = 1; k < 33; ++k) {
+- if (addr + (subpgsize * k) > (ebnum + 1) * mtd->erasesize)
+- break;
+- prandom_bytes_state(&rnd_state, writebuf, subpgsize * k);
+- clear_data(readbuf, subpgsize * k);
+- err = mtd_read(mtd, addr, subpgsize * k, &read, readbuf);
+- if (unlikely(err || read != subpgsize * k)) {
+- if (mtd_is_bitflip(err) && read == subpgsize * k) {
+- pr_info("ECC correction at %#llx\n",
+- (long long)addr);
+- err = 0;
+- } else {
+- pr_err("error: read failed at "
+- "%#llx\n", (long long)addr);
+- return err ? err : -1;
+- }
+- }
+- if (unlikely(memcmp(readbuf, writebuf, subpgsize * k))) {
+- pr_err("error: verify failed at %#llx\n",
+- (long long)addr);
+- errcnt += 1;
+- }
+- addr += subpgsize * k;
+- }
+-
+- return err;
+-}
+-
+-static int verify_eraseblock_ff(int ebnum)
+-{
+- uint32_t j;
+- size_t read;
+- int err = 0;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- memset(writebuf, 0xff, subpgsize);
+- for (j = 0; j < mtd->erasesize / subpgsize; ++j) {
+- clear_data(readbuf, subpgsize);
+- err = mtd_read(mtd, addr, subpgsize, &read, readbuf);
+- if (unlikely(err || read != subpgsize)) {
+- if (mtd_is_bitflip(err) && read == subpgsize) {
+- pr_info("ECC correction at %#llx\n",
+- (long long)addr);
+- err = 0;
+- } else {
+- pr_err("error: read failed at "
+- "%#llx\n", (long long)addr);
+- return err ? err : -1;
+- }
+- }
+- if (unlikely(memcmp(readbuf, writebuf, subpgsize))) {
+- pr_err("error: verify 0xff failed at "
+- "%#llx\n", (long long)addr);
+- errcnt += 1;
+- }
+- addr += subpgsize;
+- }
+-
+- return err;
+-}
+-
+-static int verify_all_eraseblocks_ff(void)
+-{
+- int err;
+- unsigned int i;
+-
+- pr_info("verifying all eraseblocks for 0xff\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = verify_eraseblock_ff(i);
+- if (err)
+- return err;
+- if (i % 256 == 0)
+- pr_info("verified up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("verified %u eraseblocks\n", i);
+- return 0;
+-}
+-
+-static int is_block_bad(int ebnum)
+-{
+- loff_t addr = ebnum * mtd->erasesize;
+- int ret;
+-
+- ret = mtd_block_isbad(mtd, addr);
+- if (ret)
+- pr_info("block %d is bad\n", ebnum);
+- return ret;
+-}
+-
+-static int scan_for_bad_eraseblocks(void)
+-{
+- int i, bad = 0;
+-
+- bbt = kzalloc(ebcnt, GFP_KERNEL);
+- if (!bbt) {
+- pr_err("error: cannot allocate memory\n");
+- return -ENOMEM;
+- }
+-
+- pr_info("scanning for bad eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- bbt[i] = is_block_bad(i) ? 1 : 0;
+- if (bbt[i])
+- bad += 1;
+- cond_resched();
+- }
+- pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
+- return 0;
+-}
+-
+-static int __init mtd_subpagetest_init(void)
+-{
+- int err = 0;
+- uint32_t i;
+- uint64_t tmp;
+-
+- printk(KERN_INFO "\n");
+- printk(KERN_INFO "=================================================\n");
+-
+- if (dev < 0) {
+- pr_info("Please specify a valid mtd-device via module parameter\n");
+- pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
+- return -EINVAL;
+- }
+-
+- pr_info("MTD device: %d\n", dev);
+-
+- mtd = get_mtd_device(NULL, dev);
+- if (IS_ERR(mtd)) {
+- err = PTR_ERR(mtd);
+- pr_err("error: cannot get MTD device\n");
+- return err;
+- }
+-
+- if (mtd->type != MTD_NANDFLASH) {
+- pr_info("this test requires NAND flash\n");
+- goto out;
+- }
+-
+- subpgsize = mtd->writesize >> mtd->subpage_sft;
+- tmp = mtd->size;
+- do_div(tmp, mtd->erasesize);
+- ebcnt = tmp;
+- pgcnt = mtd->erasesize / mtd->writesize;
+-
+- pr_info("MTD device size %llu, eraseblock size %u, "
+- "page size %u, subpage size %u, count of eraseblocks %u, "
+- "pages per eraseblock %u, OOB size %u\n",
+- (unsigned long long)mtd->size, mtd->erasesize,
+- mtd->writesize, subpgsize, ebcnt, pgcnt, mtd->oobsize);
+-
+- err = -ENOMEM;
+- bufsize = subpgsize * 32;
+- writebuf = kmalloc(bufsize, GFP_KERNEL);
+- if (!writebuf) {
+- pr_info("error: cannot allocate memory\n");
+- goto out;
+- }
+- readbuf = kmalloc(bufsize, GFP_KERNEL);
+- if (!readbuf) {
+- pr_info("error: cannot allocate memory\n");
+- goto out;
+- }
+-
+- err = scan_for_bad_eraseblocks();
+- if (err)
+- goto out;
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- pr_info("writing whole device\n");
+- prandom_seed_state(&rnd_state, 1);
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = write_eraseblock(i);
+- if (unlikely(err))
+- goto out;
+- if (i % 256 == 0)
+- pr_info("written up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("written %u eraseblocks\n", i);
+-
+- prandom_seed_state(&rnd_state, 1);
+- pr_info("verifying all eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = verify_eraseblock(i);
+- if (unlikely(err))
+- goto out;
+- if (i % 256 == 0)
+- pr_info("verified up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("verified %u eraseblocks\n", i);
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- err = verify_all_eraseblocks_ff();
+- if (err)
+- goto out;
+-
+- /* Write all eraseblocks */
+- prandom_seed_state(&rnd_state, 3);
+- pr_info("writing whole device\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = write_eraseblock2(i);
+- if (unlikely(err))
+- goto out;
+- if (i % 256 == 0)
+- pr_info("written up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("written %u eraseblocks\n", i);
+-
+- /* Check all eraseblocks */
+- prandom_seed_state(&rnd_state, 3);
+- pr_info("verifying all eraseblocks\n");
+- for (i = 0; i < ebcnt; ++i) {
+- if (bbt[i])
+- continue;
+- err = verify_eraseblock2(i);
+- if (unlikely(err))
+- goto out;
+- if (i % 256 == 0)
+- pr_info("verified up to eraseblock %u\n", i);
+- cond_resched();
+- }
+- pr_info("verified %u eraseblocks\n", i);
+-
+- err = erase_whole_device();
+- if (err)
+- goto out;
+-
+- err = verify_all_eraseblocks_ff();
+- if (err)
+- goto out;
+-
+- pr_info("finished with %d errors\n", errcnt);
+-
+-out:
+- kfree(bbt);
+- kfree(readbuf);
+- kfree(writebuf);
+- put_mtd_device(mtd);
+- if (err)
+- pr_info("error %d occurred\n", err);
+- printk(KERN_INFO "=================================================\n");
+- return err;
+-}
+-module_init(mtd_subpagetest_init);
+-
+-static void __exit mtd_subpagetest_exit(void)
+-{
+- return;
+-}
+-module_exit(mtd_subpagetest_exit);
+-
+-MODULE_DESCRIPTION("Subpage test module");
+-MODULE_AUTHOR("Adrian Hunter");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_test.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_test.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_test.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_test.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,110 @@
++#define pr_fmt(fmt) "mtd_test: " fmt
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/sched.h>
++#include <linux/printk.h>
++
++#include "mtd_test.h"
++
++int mtdtest_erase_eraseblock(struct mtd_info *mtd, unsigned int ebnum)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize;
++
++ err = mtd_erase(mtd, &ei);
++ if (err) {
++ pr_info("error %d while erasing EB %d\n", err, ebnum);
++ return err;
++ }
++
++ if (ei.state == MTD_ERASE_FAILED) {
++ pr_info("some erase error occurred at EB %d\n", ebnum);
++ return -EIO;
++ }
++ return 0;
++}
++
++static int is_block_bad(struct mtd_info *mtd, unsigned int ebnum)
++{
++ int ret;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ ret = mtd_block_isbad(mtd, addr);
++ if (ret)
++ pr_info("block %d is bad\n", ebnum);
++
++ return ret;
++}
++
++int mtdtest_scan_for_bad_eraseblocks(struct mtd_info *mtd, unsigned char *bbt,
++ unsigned int eb, int ebcnt)
++{
++ int i, bad = 0;
++
++ if (!mtd_can_have_bb(mtd))
++ return 0;
++
++ pr_info("scanning for bad eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ bbt[i] = is_block_bad(mtd, eb + i) ? 1 : 0;
++ if (bbt[i])
++ bad += 1;
++ cond_resched();
++ }
++ pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
++
++ return 0;
++}
++
++int mtdtest_erase_good_eraseblocks(struct mtd_info *mtd, unsigned char *bbt,
++ unsigned int eb, int ebcnt)
++{
++ int err;
++ unsigned int i;
++
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = mtdtest_erase_eraseblock(mtd, eb + i);
++ if (err)
++ return err;
++ cond_resched();
++ }
++
++ return 0;
++}
++
++int mtdtest_read(struct mtd_info *mtd, loff_t addr, size_t size, void *buf)
++{
++ size_t read;
++ int err;
++
++ err = mtd_read(mtd, addr, size, &read, buf);
++ /* Ignore corrected ECC errors */
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (!err && read != size)
++ err = -EIO;
++
++ return err;
++}
++
++int mtdtest_write(struct mtd_info *mtd, loff_t addr, size_t size,
++ const void *buf)
++{
++ size_t written;
++ int err;
++
++ err = mtd_write(mtd, addr, size, &written, buf);
++ if (!err && written != size)
++ err = -EIO;
++
++ return err;
++}
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_test.h linux-linaro-stable-mx6/drivers/mtd/tests/mtd_test.h
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_test.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_test.h 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,11 @@
++#include <linux/mtd/mtd.h>
++
++int mtdtest_erase_eraseblock(struct mtd_info *mtd, unsigned int ebnum);
++int mtdtest_scan_for_bad_eraseblocks(struct mtd_info *mtd, unsigned char *bbt,
++ unsigned int eb, int ebcnt);
++int mtdtest_erase_good_eraseblocks(struct mtd_info *mtd, unsigned char *bbt,
++ unsigned int eb, int ebcnt);
++
++int mtdtest_read(struct mtd_info *mtd, loff_t addr, size_t size, void *buf);
++int mtdtest_write(struct mtd_info *mtd, loff_t addr, size_t size,
++ const void *buf);
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/mtd_torturetest.c linux-linaro-stable-mx6/drivers/mtd/tests/mtd_torturetest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/mtd_torturetest.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/mtd_torturetest.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,535 +0,0 @@
+-/*
+- * Copyright (C) 2006-2008 Artem Bityutskiy
+- * Copyright (C) 2006-2008 Jarkko Lavinen
+- * Copyright (C) 2006-2008 Adrian Hunter
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License version 2 as published by
+- * the Free Software Foundation.
+- *
+- * This program is distributed in the hope that it will be useful, but WITHOUT
+- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+- * more details.
+- *
+- * You should have received a copy of the GNU General Public License along with
+- * this program; see the file COPYING. If not, write to the Free Software
+- * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+- *
+- * Authors: Artem Bityutskiy, Jarkko Lavinen, Adria Hunter
+- *
+- * WARNING: this test program may kill your flash and your device. Do not
+- * use it unless you know what you do. Authors are not responsible for any
+- * damage caused by this program.
+- */
+-
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-#include <linux/init.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/err.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/slab.h>
+-#include <linux/sched.h>
+-
+-#define RETRIES 3
+-
+-static int eb = 8;
+-module_param(eb, int, S_IRUGO);
+-MODULE_PARM_DESC(eb, "eraseblock number within the selected MTD device");
+-
+-static int ebcnt = 32;
+-module_param(ebcnt, int, S_IRUGO);
+-MODULE_PARM_DESC(ebcnt, "number of consecutive eraseblocks to torture");
+-
+-static int pgcnt;
+-module_param(pgcnt, int, S_IRUGO);
+-MODULE_PARM_DESC(pgcnt, "number of pages per eraseblock to torture (0 => all)");
+-
+-static int dev = -EINVAL;
+-module_param(dev, int, S_IRUGO);
+-MODULE_PARM_DESC(dev, "MTD device number to use");
+-
+-static int gran = 512;
+-module_param(gran, int, S_IRUGO);
+-MODULE_PARM_DESC(gran, "how often the status information should be printed");
+-
+-static int check = 1;
+-module_param(check, int, S_IRUGO);
+-MODULE_PARM_DESC(check, "if the written data should be checked");
+-
+-static unsigned int cycles_count;
+-module_param(cycles_count, uint, S_IRUGO);
+-MODULE_PARM_DESC(cycles_count, "how many erase cycles to do "
+- "(infinite by default)");
+-
+-static struct mtd_info *mtd;
+-
+-/* This buffer contains 0x555555...0xAAAAAA... pattern */
+-static unsigned char *patt_5A5;
+-/* This buffer contains 0xAAAAAA...0x555555... pattern */
+-static unsigned char *patt_A5A;
+-/* This buffer contains all 0xFF bytes */
+-static unsigned char *patt_FF;
+-/* This a temporary buffer is use when checking data */
+-static unsigned char *check_buf;
+-/* How many erase cycles were done */
+-static unsigned int erase_cycles;
+-
+-static int pgsize;
+-static struct timeval start, finish;
+-
+-static void report_corrupt(unsigned char *read, unsigned char *written);
+-
+-static inline void start_timing(void)
+-{
+- do_gettimeofday(&start);
+-}
+-
+-static inline void stop_timing(void)
+-{
+- do_gettimeofday(&finish);
+-}
+-
+-/*
+- * Erase eraseblock number @ebnum.
+- */
+-static inline int erase_eraseblock(int ebnum)
+-{
+- int err;
+- struct erase_info ei;
+- loff_t addr = ebnum * mtd->erasesize;
+-
+- memset(&ei, 0, sizeof(struct erase_info));
+- ei.mtd = mtd;
+- ei.addr = addr;
+- ei.len = mtd->erasesize;
+-
+- err = mtd_erase(mtd, &ei);
+- if (err) {
+- pr_err("error %d while erasing EB %d\n", err, ebnum);
+- return err;
+- }
+-
+- if (ei.state == MTD_ERASE_FAILED) {
+- pr_err("some erase error occurred at EB %d\n",
+- ebnum);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-/*
+- * Check that the contents of eraseblock number @enbum is equivalent to the
+- * @buf buffer.
+- */
+-static inline int check_eraseblock(int ebnum, unsigned char *buf)
+-{
+- int err, retries = 0;
+- size_t read;
+- loff_t addr = ebnum * mtd->erasesize;
+- size_t len = mtd->erasesize;
+-
+- if (pgcnt) {
+- addr = (ebnum + 1) * mtd->erasesize - pgcnt * pgsize;
+- len = pgcnt * pgsize;
+- }
+-
+-retry:
+- err = mtd_read(mtd, addr, len, &read, check_buf);
+- if (mtd_is_bitflip(err))
+- pr_err("single bit flip occurred at EB %d "
+- "MTD reported that it was fixed.\n", ebnum);
+- else if (err) {
+- pr_err("error %d while reading EB %d, "
+- "read %zd\n", err, ebnum, read);
+- return err;
+- }
+-
+- if (read != len) {
+- pr_err("failed to read %zd bytes from EB %d, "
+- "read only %zd, but no error reported\n",
+- len, ebnum, read);
+- return -EIO;
+- }
+-
+- if (memcmp(buf, check_buf, len)) {
+- pr_err("read wrong data from EB %d\n", ebnum);
+- report_corrupt(check_buf, buf);
+-
+- if (retries++ < RETRIES) {
+- /* Try read again */
+- yield();
+- pr_info("re-try reading data from EB %d\n",
+- ebnum);
+- goto retry;
+- } else {
+- pr_info("retried %d times, still errors, "
+- "give-up\n", RETRIES);
+- return -EINVAL;
+- }
+- }
+-
+- if (retries != 0)
+- pr_info("only attempt number %d was OK (!!!)\n",
+- retries);
+-
+- return 0;
+-}
+-
+-static inline int write_pattern(int ebnum, void *buf)
+-{
+- int err;
+- size_t written;
+- loff_t addr = ebnum * mtd->erasesize;
+- size_t len = mtd->erasesize;
+-
+- if (pgcnt) {
+- addr = (ebnum + 1) * mtd->erasesize - pgcnt * pgsize;
+- len = pgcnt * pgsize;
+- }
+- err = mtd_write(mtd, addr, len, &written, buf);
+- if (err) {
+- pr_err("error %d while writing EB %d, written %zd"
+- " bytes\n", err, ebnum, written);
+- return err;
+- }
+- if (written != len) {
+- pr_info("written only %zd bytes of %zd, but no error"
+- " reported\n", written, len);
+- return -EIO;
+- }
+-
+- return 0;
+-}
+-
+-static int __init tort_init(void)
+-{
+- int err = 0, i, infinite = !cycles_count;
+- int *bad_ebs;
+-
+- printk(KERN_INFO "\n");
+- printk(KERN_INFO "=================================================\n");
+- pr_info("Warning: this program is trying to wear out your "
+- "flash, stop it if this is not wanted.\n");
+-
+- if (dev < 0) {
+- pr_info("Please specify a valid mtd-device via module parameter\n");
+- pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
+- return -EINVAL;
+- }
+-
+- pr_info("MTD device: %d\n", dev);
+- pr_info("torture %d eraseblocks (%d-%d) of mtd%d\n",
+- ebcnt, eb, eb + ebcnt - 1, dev);
+- if (pgcnt)
+- pr_info("torturing just %d pages per eraseblock\n",
+- pgcnt);
+- pr_info("write verify %s\n", check ? "enabled" : "disabled");
+-
+- mtd = get_mtd_device(NULL, dev);
+- if (IS_ERR(mtd)) {
+- err = PTR_ERR(mtd);
+- pr_err("error: cannot get MTD device\n");
+- return err;
+- }
+-
+- if (mtd->writesize == 1) {
+- pr_info("not NAND flash, assume page size is 512 "
+- "bytes.\n");
+- pgsize = 512;
+- } else
+- pgsize = mtd->writesize;
+-
+- if (pgcnt && (pgcnt > mtd->erasesize / pgsize || pgcnt < 0)) {
+- pr_err("error: invalid pgcnt value %d\n", pgcnt);
+- goto out_mtd;
+- }
+-
+- err = -ENOMEM;
+- patt_5A5 = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!patt_5A5)
+- goto out_mtd;
+-
+- patt_A5A = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!patt_A5A)
+- goto out_patt_5A5;
+-
+- patt_FF = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!patt_FF)
+- goto out_patt_A5A;
+-
+- check_buf = kmalloc(mtd->erasesize, GFP_KERNEL);
+- if (!check_buf)
+- goto out_patt_FF;
+-
+- bad_ebs = kcalloc(ebcnt, sizeof(*bad_ebs), GFP_KERNEL);
+- if (!bad_ebs)
+- goto out_check_buf;
+-
+- err = 0;
+-
+- /* Initialize patterns */
+- memset(patt_FF, 0xFF, mtd->erasesize);
+- for (i = 0; i < mtd->erasesize / pgsize; i++) {
+- if (!(i & 1)) {
+- memset(patt_5A5 + i * pgsize, 0x55, pgsize);
+- memset(patt_A5A + i * pgsize, 0xAA, pgsize);
+- } else {
+- memset(patt_5A5 + i * pgsize, 0xAA, pgsize);
+- memset(patt_A5A + i * pgsize, 0x55, pgsize);
+- }
+- }
+-
+- /*
+- * Check if there is a bad eraseblock among those we are going to test.
+- */
+- if (mtd_can_have_bb(mtd)) {
+- for (i = eb; i < eb + ebcnt; i++) {
+- err = mtd_block_isbad(mtd, (loff_t)i * mtd->erasesize);
+-
+- if (err < 0) {
+- pr_info("block_isbad() returned %d "
+- "for EB %d\n", err, i);
+- goto out;
+- }
+-
+- if (err) {
+- pr_err("EB %d is bad. Skip it.\n", i);
+- bad_ebs[i - eb] = 1;
+- }
+- }
+- }
+-
+- start_timing();
+- while (1) {
+- int i;
+- void *patt;
+-
+- /* Erase all eraseblocks */
+- for (i = eb; i < eb + ebcnt; i++) {
+- if (bad_ebs[i - eb])
+- continue;
+- err = erase_eraseblock(i);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+-
+- /* Check if the eraseblocks contain only 0xFF bytes */
+- if (check) {
+- for (i = eb; i < eb + ebcnt; i++) {
+- if (bad_ebs[i - eb])
+- continue;
+- err = check_eraseblock(i, patt_FF);
+- if (err) {
+- pr_info("verify failed"
+- " for 0xFF... pattern\n");
+- goto out;
+- }
+- cond_resched();
+- }
+- }
+-
+- /* Write the pattern */
+- for (i = eb; i < eb + ebcnt; i++) {
+- if (bad_ebs[i - eb])
+- continue;
+- if ((eb + erase_cycles) & 1)
+- patt = patt_5A5;
+- else
+- patt = patt_A5A;
+- err = write_pattern(i, patt);
+- if (err)
+- goto out;
+- cond_resched();
+- }
+-
+- /* Verify what we wrote */
+- if (check) {
+- for (i = eb; i < eb + ebcnt; i++) {
+- if (bad_ebs[i - eb])
+- continue;
+- if ((eb + erase_cycles) & 1)
+- patt = patt_5A5;
+- else
+- patt = patt_A5A;
+- err = check_eraseblock(i, patt);
+- if (err) {
+- pr_info("verify failed for %s"
+- " pattern\n",
+- ((eb + erase_cycles) & 1) ?
+- "0x55AA55..." : "0xAA55AA...");
+- goto out;
+- }
+- cond_resched();
+- }
+- }
+-
+- erase_cycles += 1;
+-
+- if (erase_cycles % gran == 0) {
+- long ms;
+-
+- stop_timing();
+- ms = (finish.tv_sec - start.tv_sec) * 1000 +
+- (finish.tv_usec - start.tv_usec) / 1000;
+- pr_info("%08u erase cycles done, took %lu "
+- "milliseconds (%lu seconds)\n",
+- erase_cycles, ms, ms / 1000);
+- start_timing();
+- }
+-
+- if (!infinite && --cycles_count == 0)
+- break;
+- }
+-out:
+-
+- pr_info("finished after %u erase cycles\n",
+- erase_cycles);
+- kfree(bad_ebs);
+-out_check_buf:
+- kfree(check_buf);
+-out_patt_FF:
+- kfree(patt_FF);
+-out_patt_A5A:
+- kfree(patt_A5A);
+-out_patt_5A5:
+- kfree(patt_5A5);
+-out_mtd:
+- put_mtd_device(mtd);
+- if (err)
+- pr_info("error %d occurred during torturing\n", err);
+- printk(KERN_INFO "=================================================\n");
+- return err;
+-}
+-module_init(tort_init);
+-
+-static void __exit tort_exit(void)
+-{
+- return;
+-}
+-module_exit(tort_exit);
+-
+-static int countdiffs(unsigned char *buf, unsigned char *check_buf,
+- unsigned offset, unsigned len, unsigned *bytesp,
+- unsigned *bitsp);
+-static void print_bufs(unsigned char *read, unsigned char *written, int start,
+- int len);
+-
+-/*
+- * Report the detailed information about how the read EB differs from what was
+- * written.
+- */
+-static void report_corrupt(unsigned char *read, unsigned char *written)
+-{
+- int i;
+- int bytes, bits, pages, first;
+- int offset, len;
+- size_t check_len = mtd->erasesize;
+-
+- if (pgcnt)
+- check_len = pgcnt * pgsize;
+-
+- bytes = bits = pages = 0;
+- for (i = 0; i < check_len; i += pgsize)
+- if (countdiffs(written, read, i, pgsize, &bytes,
+- &bits) >= 0)
+- pages++;
+-
+- pr_info("verify fails on %d pages, %d bytes/%d bits\n",
+- pages, bytes, bits);
+- pr_info("The following is a list of all differences between"
+- " what was read from flash and what was expected\n");
+-
+- for (i = 0; i < check_len; i += pgsize) {
+- cond_resched();
+- bytes = bits = 0;
+- first = countdiffs(written, read, i, pgsize, &bytes,
+- &bits);
+- if (first < 0)
+- continue;
+-
+- printk("-------------------------------------------------------"
+- "----------------------------------\n");
+-
+- pr_info("Page %zd has %d bytes/%d bits failing verify,"
+- " starting at offset 0x%x\n",
+- (mtd->erasesize - check_len + i) / pgsize,
+- bytes, bits, first);
+-
+- offset = first & ~0x7;
+- len = ((first + bytes) | 0x7) + 1 - offset;
+-
+- print_bufs(read, written, offset, len);
+- }
+-}
+-
+-static void print_bufs(unsigned char *read, unsigned char *written, int start,
+- int len)
+-{
+- int i = 0, j1, j2;
+- char *diff;
+-
+- printk("Offset Read Written\n");
+- while (i < len) {
+- printk("0x%08x: ", start + i);
+- diff = " ";
+- for (j1 = 0; j1 < 8 && i + j1 < len; j1++) {
+- printk(" %02x", read[start + i + j1]);
+- if (read[start + i + j1] != written[start + i + j1])
+- diff = "***";
+- }
+-
+- while (j1 < 8) {
+- printk(" ");
+- j1 += 1;
+- }
+-
+- printk(" %s ", diff);
+-
+- for (j2 = 0; j2 < 8 && i + j2 < len; j2++)
+- printk(" %02x", written[start + i + j2]);
+- printk("\n");
+- i += 8;
+- }
+-}
+-
+-/*
+- * Count the number of differing bytes and bits and return the first differing
+- * offset.
+- */
+-static int countdiffs(unsigned char *buf, unsigned char *check_buf,
+- unsigned offset, unsigned len, unsigned *bytesp,
+- unsigned *bitsp)
+-{
+- unsigned i, bit;
+- int first = -1;
+-
+- for (i = offset; i < offset + len; i++)
+- if (buf[i] != check_buf[i]) {
+- first = i;
+- break;
+- }
+-
+- while (i < offset + len) {
+- if (buf[i] != check_buf[i]) {
+- (*bytesp)++;
+- bit = 1;
+- while (bit < 256) {
+- if ((buf[i] & bit) != (check_buf[i] & bit))
+- (*bitsp)++;
+- bit <<= 1;
+- }
+- }
+- i++;
+- }
+-
+- return first;
+-}
+-
+-MODULE_DESCRIPTION("Eraseblock torturing module");
+-MODULE_AUTHOR("Artem Bityutskiy, Jarkko Lavinen, Adrian Hunter");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/nandbiterrs.c linux-linaro-stable-mx6/drivers/mtd/tests/nandbiterrs.c
+--- linux-3.10.30.orig/drivers/mtd/tests/nandbiterrs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/nandbiterrs.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,461 @@
++/*
++ * Copyright © 2012 NetCommWireless
++ * Iwo Mergler <Iwo.Mergler@netcommwireless.com.au>
++ *
++ * Test for multi-bit error recovery on a NAND page This mostly tests the
++ * ECC controller / driver.
++ *
++ * There are two test modes:
++ *
++ * 0 - artificially inserting bit errors until the ECC fails
++ * This is the default method and fairly quick. It should
++ * be independent of the quality of the FLASH.
++ *
++ * 1 - re-writing the same pattern repeatedly until the ECC fails.
++ * This method relies on the physics of NAND FLASH to eventually
++ * generate '0' bits if '1' has been written sufficient times.
++ * Depending on the NAND, the first bit errors will appear after
++ * 1000 or more writes and then will usually snowball, reaching the
++ * limits of the ECC quickly.
++ *
++ * The test stops after 10000 cycles, should your FLASH be
++ * exceptionally good and not generate bit errors before that. Try
++ * a different page in that case.
++ *
++ * Please note that neither of these tests will significantly 'use up' any
++ * FLASH endurance. Only a maximum of two erase operations will be performed.
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; see the file COPYING. If not, write to the Free Software
++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/mtd/mtd.h>
++#include <linux/err.h>
++#include <linux/mtd/nand.h>
++#include <linux/slab.h>
++
++static int dev;
++module_param(dev, int, S_IRUGO);
++MODULE_PARM_DESC(dev, "MTD device number to use");
++
++static unsigned page_offset;
++module_param(page_offset, uint, S_IRUGO);
++MODULE_PARM_DESC(page_offset, "Page number relative to dev start");
++
++static unsigned seed;
++module_param(seed, uint, S_IRUGO);
++MODULE_PARM_DESC(seed, "Random seed");
++
++static int mode;
++module_param(mode, int, S_IRUGO);
++MODULE_PARM_DESC(mode, "0=incremental errors, 1=overwrite test");
++
++static unsigned max_overwrite = 10000;
++
++static loff_t offset; /* Offset of the page we're using. */
++static unsigned eraseblock; /* Eraseblock number for our page. */
++
++/* We assume that the ECC can correct up to a certain number
++ * of biterrors per subpage. */
++static unsigned subsize; /* Size of subpages */
++static unsigned subcount; /* Number of subpages per page */
++
++static struct mtd_info *mtd; /* MTD device */
++
++static uint8_t *wbuffer; /* One page write / compare buffer */
++static uint8_t *rbuffer; /* One page read buffer */
++
++/* 'random' bytes from known offsets */
++static uint8_t hash(unsigned offset)
++{
++ unsigned v = offset;
++ unsigned char c;
++ v ^= 0x7f7edfd3;
++ v = v ^ (v >> 3);
++ v = v ^ (v >> 5);
++ v = v ^ (v >> 13);
++ c = v & 0xFF;
++ /* Reverse bits of result. */
++ c = (c & 0x0F) << 4 | (c & 0xF0) >> 4;
++ c = (c & 0x33) << 2 | (c & 0xCC) >> 2;
++ c = (c & 0x55) << 1 | (c & 0xAA) >> 1;
++ return c;
++}
++
++static int erase_block(void)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = eraseblock * mtd->erasesize;
++
++ pr_info("erase_block\n");
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize;
++
++ err = mtd_erase(mtd, &ei);
++ if (err || ei.state == MTD_ERASE_FAILED) {
++ pr_err("error %d while erasing\n", err);
++ if (!err)
++ err = -EIO;
++ return err;
++ }
++
++ return 0;
++}
++
++/* Writes wbuffer to page */
++static int write_page(int log)
++{
++ int err = 0;
++ size_t written;
++
++ if (log)
++ pr_info("write_page\n");
++
++ err = mtd_write(mtd, offset, mtd->writesize, &written, wbuffer);
++ if (err || written != mtd->writesize) {
++ pr_err("error: write failed at %#llx\n", (long long)offset);
++ if (!err)
++ err = -EIO;
++ }
++
++ return err;
++}
++
++/* Re-writes the data area while leaving the OOB alone. */
++static int rewrite_page(int log)
++{
++ int err = 0;
++ struct mtd_oob_ops ops;
++
++ if (log)
++ pr_info("rewrite page\n");
++
++ ops.mode = MTD_OPS_RAW; /* No ECC */
++ ops.len = mtd->writesize;
++ ops.retlen = 0;
++ ops.ooblen = 0;
++ ops.oobretlen = 0;
++ ops.ooboffs = 0;
++ ops.datbuf = wbuffer;
++ ops.oobbuf = NULL;
++
++ err = mtd_write_oob(mtd, offset, &ops);
++ if (err || ops.retlen != mtd->writesize) {
++ pr_err("error: write_oob failed (%d)\n", err);
++ if (!err)
++ err = -EIO;
++ }
++
++ return err;
++}
++
++/* Reads page into rbuffer. Returns number of corrected bit errors (>=0)
++ * or error (<0) */
++static int read_page(int log)
++{
++ int err = 0;
++ size_t read;
++ struct mtd_ecc_stats oldstats;
++
++ if (log)
++ pr_info("read_page\n");
++
++ /* Saving last mtd stats */
++ memcpy(&oldstats, &mtd->ecc_stats, sizeof(oldstats));
++
++ err = mtd_read(mtd, offset, mtd->writesize, &read, rbuffer);
++ if (err == -EUCLEAN)
++ err = mtd->ecc_stats.corrected - oldstats.corrected;
++
++ if (err < 0 || read != mtd->writesize) {
++ pr_err("error: read failed at %#llx\n", (long long)offset);
++ if (err >= 0)
++ err = -EIO;
++ }
++
++ return err;
++}
++
++/* Verifies rbuffer against random sequence */
++static int verify_page(int log)
++{
++ unsigned i, errs = 0;
++
++ if (log)
++ pr_info("verify_page\n");
++
++ for (i = 0; i < mtd->writesize; i++) {
++ if (rbuffer[i] != hash(i+seed)) {
++ pr_err("Error: page offset %u, expected %02x, got %02x\n",
++ i, hash(i+seed), rbuffer[i]);
++ errs++;
++ }
++ }
++
++ if (errs)
++ return -EIO;
++ else
++ return 0;
++}
++
++#define CBIT(v, n) ((v) & (1 << (n)))
++#define BCLR(v, n) ((v) = (v) & ~(1 << (n)))
++
++/* Finds the first '1' bit in wbuffer starting at offset 'byte'
++ * and sets it to '0'. */
++static int insert_biterror(unsigned byte)
++{
++ int bit;
++
++ while (byte < mtd->writesize) {
++ for (bit = 7; bit >= 0; bit--) {
++ if (CBIT(wbuffer[byte], bit)) {
++ BCLR(wbuffer[byte], bit);
++ pr_info("Inserted biterror @ %u/%u\n", byte, bit);
++ return 0;
++ }
++ }
++ byte++;
++ }
++ pr_err("biterror: Failed to find a '1' bit\n");
++ return -EIO;
++}
++
++/* Writes 'random' data to page and then introduces deliberate bit
++ * errors into the page, while verifying each step. */
++static int incremental_errors_test(void)
++{
++ int err = 0;
++ unsigned i;
++ unsigned errs_per_subpage = 0;
++
++ pr_info("incremental biterrors test\n");
++
++ for (i = 0; i < mtd->writesize; i++)
++ wbuffer[i] = hash(i+seed);
++
++ err = write_page(1);
++ if (err)
++ goto exit;
++
++ while (1) {
++
++ err = rewrite_page(1);
++ if (err)
++ goto exit;
++
++ err = read_page(1);
++ if (err > 0)
++ pr_info("Read reported %d corrected bit errors\n", err);
++ if (err < 0) {
++ pr_err("After %d biterrors per subpage, read reported error %d\n",
++ errs_per_subpage, err);
++ err = 0;
++ goto exit;
++ }
++
++ err = verify_page(1);
++ if (err) {
++ pr_err("ECC failure, read data is incorrect despite read success\n");
++ goto exit;
++ }
++
++ pr_info("Successfully corrected %d bit errors per subpage\n",
++ errs_per_subpage);
++
++ for (i = 0; i < subcount; i++) {
++ err = insert_biterror(i * subsize);
++ if (err < 0)
++ goto exit;
++ }
++ errs_per_subpage++;
++ }
++
++exit:
++ return err;
++}
++
++
++/* Writes 'random' data to page and then re-writes that same data repeatedly.
++ This eventually develops bit errors (bits written as '1' will slowly become
++ '0'), which are corrected as far as the ECC is capable of. */
++static int overwrite_test(void)
++{
++ int err = 0;
++ unsigned i;
++ unsigned max_corrected = 0;
++ unsigned opno = 0;
++ /* We don't expect more than this many correctable bit errors per
++ * page. */
++ #define MAXBITS 512
++ static unsigned bitstats[MAXBITS]; /* bit error histogram. */
++
++ memset(bitstats, 0, sizeof(bitstats));
++
++ pr_info("overwrite biterrors test\n");
++
++ for (i = 0; i < mtd->writesize; i++)
++ wbuffer[i] = hash(i+seed);
++
++ err = write_page(1);
++ if (err)
++ goto exit;
++
++ while (opno < max_overwrite) {
++
++ err = rewrite_page(0);
++ if (err)
++ break;
++
++ err = read_page(0);
++ if (err >= 0) {
++ if (err >= MAXBITS) {
++ pr_info("Implausible number of bit errors corrected\n");
++ err = -EIO;
++ break;
++ }
++ bitstats[err]++;
++ if (err > max_corrected) {
++ max_corrected = err;
++ pr_info("Read reported %d corrected bit errors\n",
++ err);
++ }
++ } else { /* err < 0 */
++ pr_info("Read reported error %d\n", err);
++ err = 0;
++ break;
++ }
++
++ err = verify_page(0);
++ if (err) {
++ bitstats[max_corrected] = opno;
++ pr_info("ECC failure, read data is incorrect despite read success\n");
++ break;
++ }
++
++ opno++;
++ }
++
++ /* At this point bitstats[0] contains the number of ops with no bit
++ * errors, bitstats[1] the number of ops with 1 bit error, etc. */
++ pr_info("Bit error histogram (%d operations total):\n", opno);
++ for (i = 0; i < max_corrected; i++)
++ pr_info("Page reads with %3d corrected bit errors: %d\n",
++ i, bitstats[i]);
++
++exit:
++ return err;
++}
++
++static int __init mtd_nandbiterrs_init(void)
++{
++ int err = 0;
++
++ printk("\n");
++ printk(KERN_INFO "==================================================\n");
++ pr_info("MTD device: %d\n", dev);
++
++ mtd = get_mtd_device(NULL, dev);
++ if (IS_ERR(mtd)) {
++ err = PTR_ERR(mtd);
++ pr_err("error: cannot get MTD device\n");
++ goto exit_mtddev;
++ }
++
++ if (!mtd_type_is_nand(mtd)) {
++ pr_info("this test requires NAND flash\n");
++ err = -ENODEV;
++ goto exit_nand;
++ }
++
++ pr_info("MTD device size %llu, eraseblock=%u, page=%u, oob=%u\n",
++ (unsigned long long)mtd->size, mtd->erasesize,
++ mtd->writesize, mtd->oobsize);
++
++ subsize = mtd->writesize >> mtd->subpage_sft;
++ subcount = mtd->writesize / subsize;
++
++ pr_info("Device uses %d subpages of %d bytes\n", subcount, subsize);
++
++ offset = page_offset * mtd->writesize;
++ eraseblock = mtd_div_by_eb(offset, mtd);
++
++ pr_info("Using page=%u, offset=%llu, eraseblock=%u\n",
++ page_offset, offset, eraseblock);
++
++ wbuffer = kmalloc(mtd->writesize, GFP_KERNEL);
++ if (!wbuffer) {
++ err = -ENOMEM;
++ goto exit_wbuffer;
++ }
++
++ rbuffer = kmalloc(mtd->writesize, GFP_KERNEL);
++ if (!rbuffer) {
++ err = -ENOMEM;
++ goto exit_rbuffer;
++ }
++
++ err = erase_block();
++ if (err)
++ goto exit_error;
++
++ if (mode == 0)
++ err = incremental_errors_test();
++ else
++ err = overwrite_test();
++
++ if (err)
++ goto exit_error;
++
++ /* We leave the block un-erased in case of test failure. */
++ err = erase_block();
++ if (err)
++ goto exit_error;
++
++ err = -EIO;
++ pr_info("finished successfully.\n");
++ printk(KERN_INFO "==================================================\n");
++
++exit_error:
++ kfree(rbuffer);
++exit_rbuffer:
++ kfree(wbuffer);
++exit_wbuffer:
++ /* Nothing */
++exit_nand:
++ put_mtd_device(mtd);
++exit_mtddev:
++ return err;
++}
++
++static void __exit mtd_nandbiterrs_exit(void)
++{
++ return;
++}
++
++module_init(mtd_nandbiterrs_init);
++module_exit(mtd_nandbiterrs_exit);
++
++MODULE_DESCRIPTION("NAND bit error recovery test");
++MODULE_AUTHOR("Iwo Mergler");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/oobtest.c linux-linaro-stable-mx6/drivers/mtd/tests/oobtest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/oobtest.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/oobtest.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,714 @@
++/*
++ * Copyright (C) 2006-2008 Nokia Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; see the file COPYING. If not, write to the Free Software
++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Test OOB read and write on MTD device.
++ *
++ * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <asm/div64.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <linux/slab.h>
++#include <linux/sched.h>
++#include <linux/random.h>
++
++static int dev = -EINVAL;
++module_param(dev, int, S_IRUGO);
++MODULE_PARM_DESC(dev, "MTD device number to use");
++
++static struct mtd_info *mtd;
++static unsigned char *readbuf;
++static unsigned char *writebuf;
++static unsigned char *bbt;
++
++static int ebcnt;
++static int pgcnt;
++static int errcnt;
++static int use_offset;
++static int use_len;
++static int use_len_max;
++static int vary_offset;
++static struct rnd_state rnd_state;
++
++static int erase_eraseblock(int ebnum)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize;
++
++ err = mtd_erase(mtd, &ei);
++ if (err) {
++ pr_err("error %d while erasing EB %d\n", err, ebnum);
++ return err;
++ }
++
++ if (ei.state == MTD_ERASE_FAILED) {
++ pr_err("some erase error occurred at EB %d\n", ebnum);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int erase_whole_device(void)
++{
++ int err;
++ unsigned int i;
++
++ pr_info("erasing whole device\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = erase_eraseblock(i);
++ if (err)
++ return err;
++ cond_resched();
++ }
++ pr_info("erased %u eraseblocks\n", i);
++ return 0;
++}
++
++static void do_vary_offset(void)
++{
++ use_len -= 1;
++ if (use_len < 1) {
++ use_offset += 1;
++ if (use_offset >= use_len_max)
++ use_offset = 0;
++ use_len = use_len_max - use_offset;
++ }
++}
++
++static int write_eraseblock(int ebnum)
++{
++ int i;
++ struct mtd_oob_ops ops;
++ int err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ for (i = 0; i < pgcnt; ++i, addr += mtd->writesize) {
++ prandom_bytes_state(&rnd_state, writebuf, use_len);
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = use_len;
++ ops.oobretlen = 0;
++ ops.ooboffs = use_offset;
++ ops.datbuf = NULL;
++ ops.oobbuf = writebuf;
++ err = mtd_write_oob(mtd, addr, &ops);
++ if (err || ops.oobretlen != use_len) {
++ pr_err("error: writeoob failed at %#llx\n",
++ (long long)addr);
++ pr_err("error: use_len %d, use_offset %d\n",
++ use_len, use_offset);
++ errcnt += 1;
++ return err ? err : -1;
++ }
++ if (vary_offset)
++ do_vary_offset();
++ }
++
++ return err;
++}
++
++static int write_whole_device(void)
++{
++ int err;
++ unsigned int i;
++
++ pr_info("writing OOBs of whole device\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = write_eraseblock(i);
++ if (err)
++ return err;
++ if (i % 256 == 0)
++ pr_info("written up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("written %u eraseblocks\n", i);
++ return 0;
++}
++
++static int verify_eraseblock(int ebnum)
++{
++ int i;
++ struct mtd_oob_ops ops;
++ int err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ for (i = 0; i < pgcnt; ++i, addr += mtd->writesize) {
++ prandom_bytes_state(&rnd_state, writebuf, use_len);
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = use_len;
++ ops.oobretlen = 0;
++ ops.ooboffs = use_offset;
++ ops.datbuf = NULL;
++ ops.oobbuf = readbuf;
++ err = mtd_read_oob(mtd, addr, &ops);
++ if (err || ops.oobretlen != use_len) {
++ pr_err("error: readoob failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ return err ? err : -1;
++ }
++ if (memcmp(readbuf, writebuf, use_len)) {
++ pr_err("error: verify failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ if (errcnt > 1000) {
++ pr_err("error: too many errors\n");
++ return -1;
++ }
++ }
++ if (use_offset != 0 || use_len < mtd->ecclayout->oobavail) {
++ int k;
++
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = mtd->ecclayout->oobavail;
++ ops.oobretlen = 0;
++ ops.ooboffs = 0;
++ ops.datbuf = NULL;
++ ops.oobbuf = readbuf;
++ err = mtd_read_oob(mtd, addr, &ops);
++ if (err || ops.oobretlen != mtd->ecclayout->oobavail) {
++ pr_err("error: readoob failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ return err ? err : -1;
++ }
++ if (memcmp(readbuf + use_offset, writebuf, use_len)) {
++ pr_err("error: verify failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ if (errcnt > 1000) {
++ pr_err("error: too many errors\n");
++ return -1;
++ }
++ }
++ for (k = 0; k < use_offset; ++k)
++ if (readbuf[k] != 0xff) {
++ pr_err("error: verify 0xff "
++ "failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ if (errcnt > 1000) {
++ pr_err("error: too "
++ "many errors\n");
++ return -1;
++ }
++ }
++ for (k = use_offset + use_len;
++ k < mtd->ecclayout->oobavail; ++k)
++ if (readbuf[k] != 0xff) {
++ pr_err("error: verify 0xff "
++ "failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ if (errcnt > 1000) {
++ pr_err("error: too "
++ "many errors\n");
++ return -1;
++ }
++ }
++ }
++ if (vary_offset)
++ do_vary_offset();
++ }
++ return err;
++}
++
++static int verify_eraseblock_in_one_go(int ebnum)
++{
++ struct mtd_oob_ops ops;
++ int err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++ size_t len = mtd->ecclayout->oobavail * pgcnt;
++
++ prandom_bytes_state(&rnd_state, writebuf, len);
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = len;
++ ops.oobretlen = 0;
++ ops.ooboffs = 0;
++ ops.datbuf = NULL;
++ ops.oobbuf = readbuf;
++ err = mtd_read_oob(mtd, addr, &ops);
++ if (err || ops.oobretlen != len) {
++ pr_err("error: readoob failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ return err ? err : -1;
++ }
++ if (memcmp(readbuf, writebuf, len)) {
++ pr_err("error: verify failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ if (errcnt > 1000) {
++ pr_err("error: too many errors\n");
++ return -1;
++ }
++ }
++
++ return err;
++}
++
++static int verify_all_eraseblocks(void)
++{
++ int err;
++ unsigned int i;
++
++ pr_info("verifying all eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = verify_eraseblock(i);
++ if (err)
++ return err;
++ if (i % 256 == 0)
++ pr_info("verified up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("verified %u eraseblocks\n", i);
++ return 0;
++}
++
++static int is_block_bad(int ebnum)
++{
++ int ret;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ ret = mtd_block_isbad(mtd, addr);
++ if (ret)
++ pr_info("block %d is bad\n", ebnum);
++ return ret;
++}
++
++static int scan_for_bad_eraseblocks(void)
++{
++ int i, bad = 0;
++
++ bbt = kmalloc(ebcnt, GFP_KERNEL);
++ if (!bbt)
++ return -ENOMEM;
++
++ pr_info("scanning for bad eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ bbt[i] = is_block_bad(i) ? 1 : 0;
++ if (bbt[i])
++ bad += 1;
++ cond_resched();
++ }
++ pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
++ return 0;
++}
++
++static int __init mtd_oobtest_init(void)
++{
++ int err = 0;
++ unsigned int i;
++ uint64_t tmp;
++ struct mtd_oob_ops ops;
++ loff_t addr = 0, addr0;
++
++ printk(KERN_INFO "\n");
++ printk(KERN_INFO "=================================================\n");
++
++ if (dev < 0) {
++ pr_info("Please specify a valid mtd-device via module parameter\n");
++ pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
++ return -EINVAL;
++ }
++
++ pr_info("MTD device: %d\n", dev);
++
++ mtd = get_mtd_device(NULL, dev);
++ if (IS_ERR(mtd)) {
++ err = PTR_ERR(mtd);
++ pr_err("error: cannot get MTD device\n");
++ return err;
++ }
++
++ if (!mtd_type_is_nand(mtd)) {
++ pr_info("this test requires NAND flash\n");
++ goto out;
++ }
++
++ tmp = mtd->size;
++ do_div(tmp, mtd->erasesize);
++ ebcnt = tmp;
++ pgcnt = mtd->erasesize / mtd->writesize;
++
++ pr_info("MTD device size %llu, eraseblock size %u, "
++ "page size %u, count of eraseblocks %u, pages per "
++ "eraseblock %u, OOB size %u\n",
++ (unsigned long long)mtd->size, mtd->erasesize,
++ mtd->writesize, ebcnt, pgcnt, mtd->oobsize);
++
++ err = -ENOMEM;
++ readbuf = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!readbuf)
++ goto out;
++ writebuf = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!writebuf)
++ goto out;
++
++ err = scan_for_bad_eraseblocks();
++ if (err)
++ goto out;
++
++ use_offset = 0;
++ use_len = mtd->ecclayout->oobavail;
++ use_len_max = mtd->ecclayout->oobavail;
++ vary_offset = 0;
++
++ /* First test: write all OOB, read it back and verify */
++ pr_info("test 1 of 5\n");
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ prandom_seed_state(&rnd_state, 1);
++ err = write_whole_device();
++ if (err)
++ goto out;
++
++ prandom_seed_state(&rnd_state, 1);
++ err = verify_all_eraseblocks();
++ if (err)
++ goto out;
++
++ /*
++ * Second test: write all OOB, a block at a time, read it back and
++ * verify.
++ */
++ pr_info("test 2 of 5\n");
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ prandom_seed_state(&rnd_state, 3);
++ err = write_whole_device();
++ if (err)
++ goto out;
++
++ /* Check all eraseblocks */
++ prandom_seed_state(&rnd_state, 3);
++ pr_info("verifying all eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = verify_eraseblock_in_one_go(i);
++ if (err)
++ goto out;
++ if (i % 256 == 0)
++ pr_info("verified up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("verified %u eraseblocks\n", i);
++
++ /*
++ * Third test: write OOB at varying offsets and lengths, read it back
++ * and verify.
++ */
++ pr_info("test 3 of 5\n");
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ /* Write all eraseblocks */
++ use_offset = 0;
++ use_len = mtd->ecclayout->oobavail;
++ use_len_max = mtd->ecclayout->oobavail;
++ vary_offset = 1;
++ prandom_seed_state(&rnd_state, 5);
++
++ err = write_whole_device();
++ if (err)
++ goto out;
++
++ /* Check all eraseblocks */
++ use_offset = 0;
++ use_len = mtd->ecclayout->oobavail;
++ use_len_max = mtd->ecclayout->oobavail;
++ vary_offset = 1;
++ prandom_seed_state(&rnd_state, 5);
++ err = verify_all_eraseblocks();
++ if (err)
++ goto out;
++
++ use_offset = 0;
++ use_len = mtd->ecclayout->oobavail;
++ use_len_max = mtd->ecclayout->oobavail;
++ vary_offset = 0;
++
++ /* Fourth test: try to write off end of device */
++ pr_info("test 4 of 5\n");
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ addr0 = 0;
++ for (i = 0; i < ebcnt && bbt[i]; ++i)
++ addr0 += mtd->erasesize;
++
++ /* Attempt to write off end of OOB */
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = 1;
++ ops.oobretlen = 0;
++ ops.ooboffs = mtd->ecclayout->oobavail;
++ ops.datbuf = NULL;
++ ops.oobbuf = writebuf;
++ pr_info("attempting to start write past end of OOB\n");
++ pr_info("an error is expected...\n");
++ err = mtd_write_oob(mtd, addr0, &ops);
++ if (err) {
++ pr_info("error occurred as expected\n");
++ err = 0;
++ } else {
++ pr_err("error: can write past end of OOB\n");
++ errcnt += 1;
++ }
++
++ /* Attempt to read off end of OOB */
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = 1;
++ ops.oobretlen = 0;
++ ops.ooboffs = mtd->ecclayout->oobavail;
++ ops.datbuf = NULL;
++ ops.oobbuf = readbuf;
++ pr_info("attempting to start read past end of OOB\n");
++ pr_info("an error is expected...\n");
++ err = mtd_read_oob(mtd, addr0, &ops);
++ if (err) {
++ pr_info("error occurred as expected\n");
++ err = 0;
++ } else {
++ pr_err("error: can read past end of OOB\n");
++ errcnt += 1;
++ }
++
++ if (bbt[ebcnt - 1])
++ pr_info("skipping end of device tests because last "
++ "block is bad\n");
++ else {
++ /* Attempt to write off end of device */
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = mtd->ecclayout->oobavail + 1;
++ ops.oobretlen = 0;
++ ops.ooboffs = 0;
++ ops.datbuf = NULL;
++ ops.oobbuf = writebuf;
++ pr_info("attempting to write past end of device\n");
++ pr_info("an error is expected...\n");
++ err = mtd_write_oob(mtd, mtd->size - mtd->writesize, &ops);
++ if (err) {
++ pr_info("error occurred as expected\n");
++ err = 0;
++ } else {
++ pr_err("error: wrote past end of device\n");
++ errcnt += 1;
++ }
++
++ /* Attempt to read off end of device */
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = mtd->ecclayout->oobavail + 1;
++ ops.oobretlen = 0;
++ ops.ooboffs = 0;
++ ops.datbuf = NULL;
++ ops.oobbuf = readbuf;
++ pr_info("attempting to read past end of device\n");
++ pr_info("an error is expected...\n");
++ err = mtd_read_oob(mtd, mtd->size - mtd->writesize, &ops);
++ if (err) {
++ pr_info("error occurred as expected\n");
++ err = 0;
++ } else {
++ pr_err("error: read past end of device\n");
++ errcnt += 1;
++ }
++
++ err = erase_eraseblock(ebcnt - 1);
++ if (err)
++ goto out;
++
++ /* Attempt to write off end of device */
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = mtd->ecclayout->oobavail;
++ ops.oobretlen = 0;
++ ops.ooboffs = 1;
++ ops.datbuf = NULL;
++ ops.oobbuf = writebuf;
++ pr_info("attempting to write past end of device\n");
++ pr_info("an error is expected...\n");
++ err = mtd_write_oob(mtd, mtd->size - mtd->writesize, &ops);
++ if (err) {
++ pr_info("error occurred as expected\n");
++ err = 0;
++ } else {
++ pr_err("error: wrote past end of device\n");
++ errcnt += 1;
++ }
++
++ /* Attempt to read off end of device */
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = mtd->ecclayout->oobavail;
++ ops.oobretlen = 0;
++ ops.ooboffs = 1;
++ ops.datbuf = NULL;
++ ops.oobbuf = readbuf;
++ pr_info("attempting to read past end of device\n");
++ pr_info("an error is expected...\n");
++ err = mtd_read_oob(mtd, mtd->size - mtd->writesize, &ops);
++ if (err) {
++ pr_info("error occurred as expected\n");
++ err = 0;
++ } else {
++ pr_err("error: read past end of device\n");
++ errcnt += 1;
++ }
++ }
++
++ /* Fifth test: write / read across block boundaries */
++ pr_info("test 5 of 5\n");
++
++ /* Erase all eraseblocks */
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ /* Write all eraseblocks */
++ prandom_seed_state(&rnd_state, 11);
++ pr_info("writing OOBs of whole device\n");
++ for (i = 0; i < ebcnt - 1; ++i) {
++ int cnt = 2;
++ int pg;
++ size_t sz = mtd->ecclayout->oobavail;
++ if (bbt[i] || bbt[i + 1])
++ continue;
++ addr = (i + 1) * mtd->erasesize - mtd->writesize;
++ for (pg = 0; pg < cnt; ++pg) {
++ prandom_bytes_state(&rnd_state, writebuf, sz);
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = sz;
++ ops.oobretlen = 0;
++ ops.ooboffs = 0;
++ ops.datbuf = NULL;
++ ops.oobbuf = writebuf;
++ err = mtd_write_oob(mtd, addr, &ops);
++ if (err)
++ goto out;
++ if (i % 256 == 0)
++ pr_info("written up to eraseblock %u\n", i);
++ cond_resched();
++ addr += mtd->writesize;
++ }
++ }
++ pr_info("written %u eraseblocks\n", i);
++
++ /* Check all eraseblocks */
++ prandom_seed_state(&rnd_state, 11);
++ pr_info("verifying all eraseblocks\n");
++ for (i = 0; i < ebcnt - 1; ++i) {
++ if (bbt[i] || bbt[i + 1])
++ continue;
++ prandom_bytes_state(&rnd_state, writebuf,
++ mtd->ecclayout->oobavail * 2);
++ addr = (i + 1) * mtd->erasesize - mtd->writesize;
++ ops.mode = MTD_OPS_AUTO_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = mtd->ecclayout->oobavail * 2;
++ ops.oobretlen = 0;
++ ops.ooboffs = 0;
++ ops.datbuf = NULL;
++ ops.oobbuf = readbuf;
++ err = mtd_read_oob(mtd, addr, &ops);
++ if (err)
++ goto out;
++ if (memcmp(readbuf, writebuf, mtd->ecclayout->oobavail * 2)) {
++ pr_err("error: verify failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ if (errcnt > 1000) {
++ pr_err("error: too many errors\n");
++ goto out;
++ }
++ }
++ if (i % 256 == 0)
++ pr_info("verified up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("verified %u eraseblocks\n", i);
++
++ pr_info("finished with %d errors\n", errcnt);
++out:
++ kfree(bbt);
++ kfree(writebuf);
++ kfree(readbuf);
++ put_mtd_device(mtd);
++ if (err)
++ pr_info("error %d occurred\n", err);
++ printk(KERN_INFO "=================================================\n");
++ return err;
++}
++module_init(mtd_oobtest_init);
++
++static void __exit mtd_oobtest_exit(void)
++{
++ return;
++}
++module_exit(mtd_oobtest_exit);
++
++MODULE_DESCRIPTION("Out-of-band test module");
++MODULE_AUTHOR("Adrian Hunter");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/pagetest.c linux-linaro-stable-mx6/drivers/mtd/tests/pagetest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/pagetest.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/pagetest.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,605 @@
++/*
++ * Copyright (C) 2006-2008 Nokia Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; see the file COPYING. If not, write to the Free Software
++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Test page read and write on MTD device.
++ *
++ * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <asm/div64.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <linux/slab.h>
++#include <linux/sched.h>
++#include <linux/random.h>
++
++static int dev = -EINVAL;
++module_param(dev, int, S_IRUGO);
++MODULE_PARM_DESC(dev, "MTD device number to use");
++
++static struct mtd_info *mtd;
++static unsigned char *twopages;
++static unsigned char *writebuf;
++static unsigned char *boundary;
++static unsigned char *bbt;
++
++static int pgsize;
++static int bufsize;
++static int ebcnt;
++static int pgcnt;
++static int errcnt;
++static struct rnd_state rnd_state;
++
++static int erase_eraseblock(int ebnum)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize;
++
++ err = mtd_erase(mtd, &ei);
++ if (err) {
++ pr_err("error %d while erasing EB %d\n", err, ebnum);
++ return err;
++ }
++
++ if (ei.state == MTD_ERASE_FAILED) {
++ pr_err("some erase error occurred at EB %d\n",
++ ebnum);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int write_eraseblock(int ebnum)
++{
++ int err = 0;
++ size_t written;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ prandom_bytes_state(&rnd_state, writebuf, mtd->erasesize);
++ cond_resched();
++ err = mtd_write(mtd, addr, mtd->erasesize, &written, writebuf);
++ if (err || written != mtd->erasesize)
++ pr_err("error: write failed at %#llx\n",
++ (long long)addr);
++
++ return err;
++}
++
++static int verify_eraseblock(int ebnum)
++{
++ uint32_t j;
++ size_t read;
++ int err = 0, i;
++ loff_t addr0, addrn;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ addr0 = 0;
++ for (i = 0; i < ebcnt && bbt[i]; ++i)
++ addr0 += mtd->erasesize;
++
++ addrn = mtd->size;
++ for (i = 0; i < ebcnt && bbt[ebcnt - i - 1]; ++i)
++ addrn -= mtd->erasesize;
++
++ prandom_bytes_state(&rnd_state, writebuf, mtd->erasesize);
++ for (j = 0; j < pgcnt - 1; ++j, addr += pgsize) {
++ /* Do a read to set the internal dataRAMs to different data */
++ err = mtd_read(mtd, addr0, bufsize, &read, twopages);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != bufsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr0);
++ return err;
++ }
++ err = mtd_read(mtd, addrn - bufsize, bufsize, &read, twopages);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != bufsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)(addrn - bufsize));
++ return err;
++ }
++ memset(twopages, 0, bufsize);
++ err = mtd_read(mtd, addr, bufsize, &read, twopages);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != bufsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ break;
++ }
++ if (memcmp(twopages, writebuf + (j * pgsize), bufsize)) {
++ pr_err("error: verify failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ }
++ }
++ /* Check boundary between eraseblocks */
++ if (addr <= addrn - pgsize - pgsize && !bbt[ebnum + 1]) {
++ struct rnd_state old_state = rnd_state;
++
++ /* Do a read to set the internal dataRAMs to different data */
++ err = mtd_read(mtd, addr0, bufsize, &read, twopages);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != bufsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr0);
++ return err;
++ }
++ err = mtd_read(mtd, addrn - bufsize, bufsize, &read, twopages);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != bufsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)(addrn - bufsize));
++ return err;
++ }
++ memset(twopages, 0, bufsize);
++ err = mtd_read(mtd, addr, bufsize, &read, twopages);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != bufsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ return err;
++ }
++ memcpy(boundary, writebuf + mtd->erasesize - pgsize, pgsize);
++ prandom_bytes_state(&rnd_state, boundary + pgsize, pgsize);
++ if (memcmp(twopages, boundary, bufsize)) {
++ pr_err("error: verify failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ }
++ rnd_state = old_state;
++ }
++ return err;
++}
++
++static int crosstest(void)
++{
++ size_t read;
++ int err = 0, i;
++ loff_t addr, addr0, addrn;
++ unsigned char *pp1, *pp2, *pp3, *pp4;
++
++ pr_info("crosstest\n");
++ pp1 = kmalloc(pgsize * 4, GFP_KERNEL);
++ if (!pp1)
++ return -ENOMEM;
++ pp2 = pp1 + pgsize;
++ pp3 = pp2 + pgsize;
++ pp4 = pp3 + pgsize;
++ memset(pp1, 0, pgsize * 4);
++
++ addr0 = 0;
++ for (i = 0; i < ebcnt && bbt[i]; ++i)
++ addr0 += mtd->erasesize;
++
++ addrn = mtd->size;
++ for (i = 0; i < ebcnt && bbt[ebcnt - i - 1]; ++i)
++ addrn -= mtd->erasesize;
++
++ /* Read 2nd-to-last page to pp1 */
++ addr = addrn - pgsize - pgsize;
++ err = mtd_read(mtd, addr, pgsize, &read, pp1);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ kfree(pp1);
++ return err;
++ }
++
++ /* Read 3rd-to-last page to pp1 */
++ addr = addrn - pgsize - pgsize - pgsize;
++ err = mtd_read(mtd, addr, pgsize, &read, pp1);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ kfree(pp1);
++ return err;
++ }
++
++ /* Read first page to pp2 */
++ addr = addr0;
++ pr_info("reading page at %#llx\n", (long long)addr);
++ err = mtd_read(mtd, addr, pgsize, &read, pp2);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ kfree(pp1);
++ return err;
++ }
++
++ /* Read last page to pp3 */
++ addr = addrn - pgsize;
++ pr_info("reading page at %#llx\n", (long long)addr);
++ err = mtd_read(mtd, addr, pgsize, &read, pp3);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ kfree(pp1);
++ return err;
++ }
++
++ /* Read first page again to pp4 */
++ addr = addr0;
++ pr_info("reading page at %#llx\n", (long long)addr);
++ err = mtd_read(mtd, addr, pgsize, &read, pp4);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ kfree(pp1);
++ return err;
++ }
++
++ /* pp2 and pp4 should be the same */
++ pr_info("verifying pages read at %#llx match\n",
++ (long long)addr0);
++ if (memcmp(pp2, pp4, pgsize)) {
++ pr_err("verify failed!\n");
++ errcnt += 1;
++ } else if (!err)
++ pr_info("crosstest ok\n");
++ kfree(pp1);
++ return err;
++}
++
++static int erasecrosstest(void)
++{
++ size_t read, written;
++ int err = 0, i, ebnum, ebnum2;
++ loff_t addr0;
++ char *readbuf = twopages;
++
++ pr_info("erasecrosstest\n");
++
++ ebnum = 0;
++ addr0 = 0;
++ for (i = 0; i < ebcnt && bbt[i]; ++i) {
++ addr0 += mtd->erasesize;
++ ebnum += 1;
++ }
++
++ ebnum2 = ebcnt - 1;
++ while (ebnum2 && bbt[ebnum2])
++ ebnum2 -= 1;
++
++ pr_info("erasing block %d\n", ebnum);
++ err = erase_eraseblock(ebnum);
++ if (err)
++ return err;
++
++ pr_info("writing 1st page of block %d\n", ebnum);
++ prandom_bytes_state(&rnd_state, writebuf, pgsize);
++ strcpy(writebuf, "There is no data like this!");
++ err = mtd_write(mtd, addr0, pgsize, &written, writebuf);
++ if (err || written != pgsize) {
++ pr_info("error: write failed at %#llx\n",
++ (long long)addr0);
++ return err ? err : -1;
++ }
++
++ pr_info("reading 1st page of block %d\n", ebnum);
++ memset(readbuf, 0, pgsize);
++ err = mtd_read(mtd, addr0, pgsize, &read, readbuf);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr0);
++ return err ? err : -1;
++ }
++
++ pr_info("verifying 1st page of block %d\n", ebnum);
++ if (memcmp(writebuf, readbuf, pgsize)) {
++ pr_err("verify failed!\n");
++ errcnt += 1;
++ return -1;
++ }
++
++ pr_info("erasing block %d\n", ebnum);
++ err = erase_eraseblock(ebnum);
++ if (err)
++ return err;
++
++ pr_info("writing 1st page of block %d\n", ebnum);
++ prandom_bytes_state(&rnd_state, writebuf, pgsize);
++ strcpy(writebuf, "There is no data like this!");
++ err = mtd_write(mtd, addr0, pgsize, &written, writebuf);
++ if (err || written != pgsize) {
++ pr_err("error: write failed at %#llx\n",
++ (long long)addr0);
++ return err ? err : -1;
++ }
++
++ pr_info("erasing block %d\n", ebnum2);
++ err = erase_eraseblock(ebnum2);
++ if (err)
++ return err;
++
++ pr_info("reading 1st page of block %d\n", ebnum);
++ memset(readbuf, 0, pgsize);
++ err = mtd_read(mtd, addr0, pgsize, &read, readbuf);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr0);
++ return err ? err : -1;
++ }
++
++ pr_info("verifying 1st page of block %d\n", ebnum);
++ if (memcmp(writebuf, readbuf, pgsize)) {
++ pr_err("verify failed!\n");
++ errcnt += 1;
++ return -1;
++ }
++
++ if (!err)
++ pr_info("erasecrosstest ok\n");
++ return err;
++}
++
++static int erasetest(void)
++{
++ size_t read, written;
++ int err = 0, i, ebnum, ok = 1;
++ loff_t addr0;
++
++ pr_info("erasetest\n");
++
++ ebnum = 0;
++ addr0 = 0;
++ for (i = 0; i < ebcnt && bbt[i]; ++i) {
++ addr0 += mtd->erasesize;
++ ebnum += 1;
++ }
++
++ pr_info("erasing block %d\n", ebnum);
++ err = erase_eraseblock(ebnum);
++ if (err)
++ return err;
++
++ pr_info("writing 1st page of block %d\n", ebnum);
++ prandom_bytes_state(&rnd_state, writebuf, pgsize);
++ err = mtd_write(mtd, addr0, pgsize, &written, writebuf);
++ if (err || written != pgsize) {
++ pr_err("error: write failed at %#llx\n",
++ (long long)addr0);
++ return err ? err : -1;
++ }
++
++ pr_info("erasing block %d\n", ebnum);
++ err = erase_eraseblock(ebnum);
++ if (err)
++ return err;
++
++ pr_info("reading 1st page of block %d\n", ebnum);
++ err = mtd_read(mtd, addr0, pgsize, &read, twopages);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr0);
++ return err ? err : -1;
++ }
++
++ pr_info("verifying 1st page of block %d is all 0xff\n",
++ ebnum);
++ for (i = 0; i < pgsize; ++i)
++ if (twopages[i] != 0xff) {
++ pr_err("verifying all 0xff failed at %d\n",
++ i);
++ errcnt += 1;
++ ok = 0;
++ break;
++ }
++
++ if (ok && !err)
++ pr_info("erasetest ok\n");
++
++ return err;
++}
++
++static int is_block_bad(int ebnum)
++{
++ loff_t addr = ebnum * mtd->erasesize;
++ int ret;
++
++ ret = mtd_block_isbad(mtd, addr);
++ if (ret)
++ pr_info("block %d is bad\n", ebnum);
++ return ret;
++}
++
++static int scan_for_bad_eraseblocks(void)
++{
++ int i, bad = 0;
++
++ bbt = kzalloc(ebcnt, GFP_KERNEL);
++ if (!bbt)
++ return -ENOMEM;
++
++ pr_info("scanning for bad eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ bbt[i] = is_block_bad(i) ? 1 : 0;
++ if (bbt[i])
++ bad += 1;
++ cond_resched();
++ }
++ pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
++ return 0;
++}
++
++static int __init mtd_pagetest_init(void)
++{
++ int err = 0;
++ uint64_t tmp;
++ uint32_t i;
++
++ printk(KERN_INFO "\n");
++ printk(KERN_INFO "=================================================\n");
++
++ if (dev < 0) {
++ pr_info("Please specify a valid mtd-device via module parameter\n");
++ pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
++ return -EINVAL;
++ }
++
++ pr_info("MTD device: %d\n", dev);
++
++ mtd = get_mtd_device(NULL, dev);
++ if (IS_ERR(mtd)) {
++ err = PTR_ERR(mtd);
++ pr_err("error: cannot get MTD device\n");
++ return err;
++ }
++
++ if (!mtd_type_is_nand(mtd)) {
++ pr_info("this test requires NAND flash\n");
++ goto out;
++ }
++
++ tmp = mtd->size;
++ do_div(tmp, mtd->erasesize);
++ ebcnt = tmp;
++ pgcnt = mtd->erasesize / mtd->writesize;
++ pgsize = mtd->writesize;
++
++ pr_info("MTD device size %llu, eraseblock size %u, "
++ "page size %u, count of eraseblocks %u, pages per "
++ "eraseblock %u, OOB size %u\n",
++ (unsigned long long)mtd->size, mtd->erasesize,
++ pgsize, ebcnt, pgcnt, mtd->oobsize);
++
++ err = -ENOMEM;
++ bufsize = pgsize * 2;
++ writebuf = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!writebuf)
++ goto out;
++ twopages = kmalloc(bufsize, GFP_KERNEL);
++ if (!twopages)
++ goto out;
++ boundary = kmalloc(bufsize, GFP_KERNEL);
++ if (!boundary)
++ goto out;
++
++ err = scan_for_bad_eraseblocks();
++ if (err)
++ goto out;
++
++ /* Erase all eraseblocks */
++ pr_info("erasing whole device\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = erase_eraseblock(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ pr_info("erased %u eraseblocks\n", i);
++
++ /* Write all eraseblocks */
++ prandom_seed_state(&rnd_state, 1);
++ pr_info("writing whole device\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = write_eraseblock(i);
++ if (err)
++ goto out;
++ if (i % 256 == 0)
++ pr_info("written up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("written %u eraseblocks\n", i);
++
++ /* Check all eraseblocks */
++ prandom_seed_state(&rnd_state, 1);
++ pr_info("verifying all eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = verify_eraseblock(i);
++ if (err)
++ goto out;
++ if (i % 256 == 0)
++ pr_info("verified up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("verified %u eraseblocks\n", i);
++
++ err = crosstest();
++ if (err)
++ goto out;
++
++ err = erasecrosstest();
++ if (err)
++ goto out;
++
++ err = erasetest();
++ if (err)
++ goto out;
++
++ pr_info("finished with %d errors\n", errcnt);
++out:
++
++ kfree(bbt);
++ kfree(boundary);
++ kfree(twopages);
++ kfree(writebuf);
++ put_mtd_device(mtd);
++ if (err)
++ pr_info("error %d occurred\n", err);
++ printk(KERN_INFO "=================================================\n");
++ return err;
++}
++module_init(mtd_pagetest_init);
++
++static void __exit mtd_pagetest_exit(void)
++{
++ return;
++}
++module_exit(mtd_pagetest_exit);
++
++MODULE_DESCRIPTION("NAND page test");
++MODULE_AUTHOR("Adrian Hunter");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/readtest.c linux-linaro-stable-mx6/drivers/mtd/tests/readtest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/readtest.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/readtest.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,257 @@
++/*
++ * Copyright (C) 2006-2008 Nokia Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; see the file COPYING. If not, write to the Free Software
++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Check MTD device read.
++ *
++ * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <linux/slab.h>
++#include <linux/sched.h>
++
++static int dev = -EINVAL;
++module_param(dev, int, S_IRUGO);
++MODULE_PARM_DESC(dev, "MTD device number to use");
++
++static struct mtd_info *mtd;
++static unsigned char *iobuf;
++static unsigned char *iobuf1;
++static unsigned char *bbt;
++
++static int pgsize;
++static int ebcnt;
++static int pgcnt;
++
++static int read_eraseblock_by_page(int ebnum)
++{
++ size_t read;
++ int i, ret, err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++ void *buf = iobuf;
++ void *oobbuf = iobuf1;
++
++ for (i = 0; i < pgcnt; i++) {
++ memset(buf, 0 , pgsize);
++ ret = mtd_read(mtd, addr, pgsize, &read, buf);
++ if (ret == -EUCLEAN)
++ ret = 0;
++ if (ret || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ if (!err)
++ err = ret;
++ if (!err)
++ err = -EINVAL;
++ }
++ if (mtd->oobsize) {
++ struct mtd_oob_ops ops;
++
++ ops.mode = MTD_OPS_PLACE_OOB;
++ ops.len = 0;
++ ops.retlen = 0;
++ ops.ooblen = mtd->oobsize;
++ ops.oobretlen = 0;
++ ops.ooboffs = 0;
++ ops.datbuf = NULL;
++ ops.oobbuf = oobbuf;
++ ret = mtd_read_oob(mtd, addr, &ops);
++ if ((ret && !mtd_is_bitflip(ret)) ||
++ ops.oobretlen != mtd->oobsize) {
++ pr_err("error: read oob failed at "
++ "%#llx\n", (long long)addr);
++ if (!err)
++ err = ret;
++ if (!err)
++ err = -EINVAL;
++ }
++ oobbuf += mtd->oobsize;
++ }
++ addr += pgsize;
++ buf += pgsize;
++ }
++
++ return err;
++}
++
++static void dump_eraseblock(int ebnum)
++{
++ int i, j, n;
++ char line[128];
++ int pg, oob;
++
++ pr_info("dumping eraseblock %d\n", ebnum);
++ n = mtd->erasesize;
++ for (i = 0; i < n;) {
++ char *p = line;
++
++ p += sprintf(p, "%05x: ", i);
++ for (j = 0; j < 32 && i < n; j++, i++)
++ p += sprintf(p, "%02x", (unsigned int)iobuf[i]);
++ printk(KERN_CRIT "%s\n", line);
++ cond_resched();
++ }
++ if (!mtd->oobsize)
++ return;
++ pr_info("dumping oob from eraseblock %d\n", ebnum);
++ n = mtd->oobsize;
++ for (pg = 0, i = 0; pg < pgcnt; pg++)
++ for (oob = 0; oob < n;) {
++ char *p = line;
++
++ p += sprintf(p, "%05x: ", i);
++ for (j = 0; j < 32 && oob < n; j++, oob++, i++)
++ p += sprintf(p, "%02x",
++ (unsigned int)iobuf1[i]);
++ printk(KERN_CRIT "%s\n", line);
++ cond_resched();
++ }
++}
++
++static int is_block_bad(int ebnum)
++{
++ loff_t addr = ebnum * mtd->erasesize;
++ int ret;
++
++ ret = mtd_block_isbad(mtd, addr);
++ if (ret)
++ pr_info("block %d is bad\n", ebnum);
++ return ret;
++}
++
++static int scan_for_bad_eraseblocks(void)
++{
++ int i, bad = 0;
++
++ bbt = kzalloc(ebcnt, GFP_KERNEL);
++ if (!bbt)
++ return -ENOMEM;
++
++ if (!mtd_can_have_bb(mtd))
++ return 0;
++
++ pr_info("scanning for bad eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ bbt[i] = is_block_bad(i) ? 1 : 0;
++ if (bbt[i])
++ bad += 1;
++ cond_resched();
++ }
++ pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
++ return 0;
++}
++
++static int __init mtd_readtest_init(void)
++{
++ uint64_t tmp;
++ int err, i;
++
++ printk(KERN_INFO "\n");
++ printk(KERN_INFO "=================================================\n");
++
++ if (dev < 0) {
++ pr_info("Please specify a valid mtd-device via module parameter\n");
++ return -EINVAL;
++ }
++
++ pr_info("MTD device: %d\n", dev);
++
++ mtd = get_mtd_device(NULL, dev);
++ if (IS_ERR(mtd)) {
++ err = PTR_ERR(mtd);
++ pr_err("error: Cannot get MTD device\n");
++ return err;
++ }
++
++ if (mtd->writesize == 1) {
++ pr_info("not NAND flash, assume page size is 512 "
++ "bytes.\n");
++ pgsize = 512;
++ } else
++ pgsize = mtd->writesize;
++
++ tmp = mtd->size;
++ do_div(tmp, mtd->erasesize);
++ ebcnt = tmp;
++ pgcnt = mtd->erasesize / pgsize;
++
++ pr_info("MTD device size %llu, eraseblock size %u, "
++ "page size %u, count of eraseblocks %u, pages per "
++ "eraseblock %u, OOB size %u\n",
++ (unsigned long long)mtd->size, mtd->erasesize,
++ pgsize, ebcnt, pgcnt, mtd->oobsize);
++
++ err = -ENOMEM;
++ iobuf = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!iobuf)
++ goto out;
++ iobuf1 = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!iobuf1)
++ goto out;
++
++ err = scan_for_bad_eraseblocks();
++ if (err)
++ goto out;
++
++ /* Read all eraseblocks 1 page at a time */
++ pr_info("testing page read\n");
++ for (i = 0; i < ebcnt; ++i) {
++ int ret;
++
++ if (bbt[i])
++ continue;
++ ret = read_eraseblock_by_page(i);
++ if (ret) {
++ dump_eraseblock(i);
++ if (!err)
++ err = ret;
++ }
++ cond_resched();
++ }
++
++ if (err)
++ pr_info("finished with errors\n");
++ else
++ pr_info("finished\n");
++
++out:
++
++ kfree(iobuf);
++ kfree(iobuf1);
++ kfree(bbt);
++ put_mtd_device(mtd);
++ if (err)
++ pr_info("error %d occurred\n", err);
++ printk(KERN_INFO "=================================================\n");
++ return err;
++}
++module_init(mtd_readtest_init);
++
++static void __exit mtd_readtest_exit(void)
++{
++ return;
++}
++module_exit(mtd_readtest_exit);
++
++MODULE_DESCRIPTION("Read test module");
++MODULE_AUTHOR("Adrian Hunter");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/speedtest.c linux-linaro-stable-mx6/drivers/mtd/tests/speedtest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/speedtest.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/speedtest.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,556 @@
++/*
++ * Copyright (C) 2007 Nokia Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; see the file COPYING. If not, write to the Free Software
++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Test read and write speed of a MTD device.
++ *
++ * Author: Adrian Hunter <adrian.hunter@nokia.com>
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <linux/slab.h>
++#include <linux/sched.h>
++#include <linux/random.h>
++
++static int dev = -EINVAL;
++module_param(dev, int, S_IRUGO);
++MODULE_PARM_DESC(dev, "MTD device number to use");
++
++static int count;
++module_param(count, int, S_IRUGO);
++MODULE_PARM_DESC(count, "Maximum number of eraseblocks to use "
++ "(0 means use all)");
++
++static struct mtd_info *mtd;
++static unsigned char *iobuf;
++static unsigned char *bbt;
++
++static int pgsize;
++static int ebcnt;
++static int pgcnt;
++static int goodebcnt;
++static struct timeval start, finish;
++
++
++static int erase_eraseblock(int ebnum)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize;
++
++ err = mtd_erase(mtd, &ei);
++ if (err) {
++ pr_err("error %d while erasing EB %d\n", err, ebnum);
++ return err;
++ }
++
++ if (ei.state == MTD_ERASE_FAILED) {
++ pr_err("some erase error occurred at EB %d\n",
++ ebnum);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int multiblock_erase(int ebnum, int blocks)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize * blocks;
++
++ err = mtd_erase(mtd, &ei);
++ if (err) {
++ pr_err("error %d while erasing EB %d, blocks %d\n",
++ err, ebnum, blocks);
++ return err;
++ }
++
++ if (ei.state == MTD_ERASE_FAILED) {
++ pr_err("some erase error occurred at EB %d,"
++ "blocks %d\n", ebnum, blocks);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int erase_whole_device(void)
++{
++ int err;
++ unsigned int i;
++
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = erase_eraseblock(i);
++ if (err)
++ return err;
++ cond_resched();
++ }
++ return 0;
++}
++
++static int write_eraseblock(int ebnum)
++{
++ size_t written;
++ int err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ err = mtd_write(mtd, addr, mtd->erasesize, &written, iobuf);
++ if (err || written != mtd->erasesize) {
++ pr_err("error: write failed at %#llx\n", addr);
++ if (!err)
++ err = -EINVAL;
++ }
++
++ return err;
++}
++
++static int write_eraseblock_by_page(int ebnum)
++{
++ size_t written;
++ int i, err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++ void *buf = iobuf;
++
++ for (i = 0; i < pgcnt; i++) {
++ err = mtd_write(mtd, addr, pgsize, &written, buf);
++ if (err || written != pgsize) {
++ pr_err("error: write failed at %#llx\n",
++ addr);
++ if (!err)
++ err = -EINVAL;
++ break;
++ }
++ addr += pgsize;
++ buf += pgsize;
++ }
++
++ return err;
++}
++
++static int write_eraseblock_by_2pages(int ebnum)
++{
++ size_t written, sz = pgsize * 2;
++ int i, n = pgcnt / 2, err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++ void *buf = iobuf;
++
++ for (i = 0; i < n; i++) {
++ err = mtd_write(mtd, addr, sz, &written, buf);
++ if (err || written != sz) {
++ pr_err("error: write failed at %#llx\n",
++ addr);
++ if (!err)
++ err = -EINVAL;
++ return err;
++ }
++ addr += sz;
++ buf += sz;
++ }
++ if (pgcnt % 2) {
++ err = mtd_write(mtd, addr, pgsize, &written, buf);
++ if (err || written != pgsize) {
++ pr_err("error: write failed at %#llx\n",
++ addr);
++ if (!err)
++ err = -EINVAL;
++ }
++ }
++
++ return err;
++}
++
++static int read_eraseblock(int ebnum)
++{
++ size_t read;
++ int err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ err = mtd_read(mtd, addr, mtd->erasesize, &read, iobuf);
++ /* Ignore corrected ECC errors */
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != mtd->erasesize) {
++ pr_err("error: read failed at %#llx\n", addr);
++ if (!err)
++ err = -EINVAL;
++ }
++
++ return err;
++}
++
++static int read_eraseblock_by_page(int ebnum)
++{
++ size_t read;
++ int i, err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++ void *buf = iobuf;
++
++ for (i = 0; i < pgcnt; i++) {
++ err = mtd_read(mtd, addr, pgsize, &read, buf);
++ /* Ignore corrected ECC errors */
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ addr);
++ if (!err)
++ err = -EINVAL;
++ break;
++ }
++ addr += pgsize;
++ buf += pgsize;
++ }
++
++ return err;
++}
++
++static int read_eraseblock_by_2pages(int ebnum)
++{
++ size_t read, sz = pgsize * 2;
++ int i, n = pgcnt / 2, err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++ void *buf = iobuf;
++
++ for (i = 0; i < n; i++) {
++ err = mtd_read(mtd, addr, sz, &read, buf);
++ /* Ignore corrected ECC errors */
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != sz) {
++ pr_err("error: read failed at %#llx\n",
++ addr);
++ if (!err)
++ err = -EINVAL;
++ return err;
++ }
++ addr += sz;
++ buf += sz;
++ }
++ if (pgcnt % 2) {
++ err = mtd_read(mtd, addr, pgsize, &read, buf);
++ /* Ignore corrected ECC errors */
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (err || read != pgsize) {
++ pr_err("error: read failed at %#llx\n",
++ addr);
++ if (!err)
++ err = -EINVAL;
++ }
++ }
++
++ return err;
++}
++
++static int is_block_bad(int ebnum)
++{
++ loff_t addr = ebnum * mtd->erasesize;
++ int ret;
++
++ ret = mtd_block_isbad(mtd, addr);
++ if (ret)
++ pr_info("block %d is bad\n", ebnum);
++ return ret;
++}
++
++static inline void start_timing(void)
++{
++ do_gettimeofday(&start);
++}
++
++static inline void stop_timing(void)
++{
++ do_gettimeofday(&finish);
++}
++
++static long calc_speed(void)
++{
++ uint64_t k;
++ long ms;
++
++ ms = (finish.tv_sec - start.tv_sec) * 1000 +
++ (finish.tv_usec - start.tv_usec) / 1000;
++ if (ms == 0)
++ return 0;
++ k = goodebcnt * (mtd->erasesize / 1024) * 1000;
++ do_div(k, ms);
++ return k;
++}
++
++static int scan_for_bad_eraseblocks(void)
++{
++ int i, bad = 0;
++
++ bbt = kzalloc(ebcnt, GFP_KERNEL);
++ if (!bbt)
++ return -ENOMEM;
++
++ if (!mtd_can_have_bb(mtd))
++ goto out;
++
++ pr_info("scanning for bad eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ bbt[i] = is_block_bad(i) ? 1 : 0;
++ if (bbt[i])
++ bad += 1;
++ cond_resched();
++ }
++ pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
++out:
++ goodebcnt = ebcnt - bad;
++ return 0;
++}
++
++static int __init mtd_speedtest_init(void)
++{
++ int err, i, blocks, j, k;
++ long speed;
++ uint64_t tmp;
++
++ printk(KERN_INFO "\n");
++ printk(KERN_INFO "=================================================\n");
++
++ if (dev < 0) {
++ pr_info("Please specify a valid mtd-device via module parameter\n");
++ pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
++ return -EINVAL;
++ }
++
++ if (count)
++ pr_info("MTD device: %d count: %d\n", dev, count);
++ else
++ pr_info("MTD device: %d\n", dev);
++
++ mtd = get_mtd_device(NULL, dev);
++ if (IS_ERR(mtd)) {
++ err = PTR_ERR(mtd);
++ pr_err("error: cannot get MTD device\n");
++ return err;
++ }
++
++ if (mtd->writesize == 1) {
++ pr_info("not NAND flash, assume page size is 512 "
++ "bytes.\n");
++ pgsize = 512;
++ } else
++ pgsize = mtd->writesize;
++
++ tmp = mtd->size;
++ do_div(tmp, mtd->erasesize);
++ ebcnt = tmp;
++ pgcnt = mtd->erasesize / pgsize;
++
++ pr_info("MTD device size %llu, eraseblock size %u, "
++ "page size %u, count of eraseblocks %u, pages per "
++ "eraseblock %u, OOB size %u\n",
++ (unsigned long long)mtd->size, mtd->erasesize,
++ pgsize, ebcnt, pgcnt, mtd->oobsize);
++
++ if (count > 0 && count < ebcnt)
++ ebcnt = count;
++
++ err = -ENOMEM;
++ iobuf = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!iobuf)
++ goto out;
++
++ prandom_bytes(iobuf, mtd->erasesize);
++
++ err = scan_for_bad_eraseblocks();
++ if (err)
++ goto out;
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ /* Write all eraseblocks, 1 eraseblock at a time */
++ pr_info("testing eraseblock write speed\n");
++ start_timing();
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = write_eraseblock(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ stop_timing();
++ speed = calc_speed();
++ pr_info("eraseblock write speed is %ld KiB/s\n", speed);
++
++ /* Read all eraseblocks, 1 eraseblock at a time */
++ pr_info("testing eraseblock read speed\n");
++ start_timing();
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = read_eraseblock(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ stop_timing();
++ speed = calc_speed();
++ pr_info("eraseblock read speed is %ld KiB/s\n", speed);
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ /* Write all eraseblocks, 1 page at a time */
++ pr_info("testing page write speed\n");
++ start_timing();
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = write_eraseblock_by_page(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ stop_timing();
++ speed = calc_speed();
++ pr_info("page write speed is %ld KiB/s\n", speed);
++
++ /* Read all eraseblocks, 1 page at a time */
++ pr_info("testing page read speed\n");
++ start_timing();
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = read_eraseblock_by_page(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ stop_timing();
++ speed = calc_speed();
++ pr_info("page read speed is %ld KiB/s\n", speed);
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ /* Write all eraseblocks, 2 pages at a time */
++ pr_info("testing 2 page write speed\n");
++ start_timing();
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = write_eraseblock_by_2pages(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ stop_timing();
++ speed = calc_speed();
++ pr_info("2 page write speed is %ld KiB/s\n", speed);
++
++ /* Read all eraseblocks, 2 pages at a time */
++ pr_info("testing 2 page read speed\n");
++ start_timing();
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = read_eraseblock_by_2pages(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ stop_timing();
++ speed = calc_speed();
++ pr_info("2 page read speed is %ld KiB/s\n", speed);
++
++ /* Erase all eraseblocks */
++ pr_info("Testing erase speed\n");
++ start_timing();
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = erase_eraseblock(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ stop_timing();
++ speed = calc_speed();
++ pr_info("erase speed is %ld KiB/s\n", speed);
++
++ /* Multi-block erase all eraseblocks */
++ for (k = 1; k < 7; k++) {
++ blocks = 1 << k;
++ pr_info("Testing %dx multi-block erase speed\n",
++ blocks);
++ start_timing();
++ for (i = 0; i < ebcnt; ) {
++ for (j = 0; j < blocks && (i + j) < ebcnt; j++)
++ if (bbt[i + j])
++ break;
++ if (j < 1) {
++ i++;
++ continue;
++ }
++ err = multiblock_erase(i, j);
++ if (err)
++ goto out;
++ cond_resched();
++ i += j;
++ }
++ stop_timing();
++ speed = calc_speed();
++ pr_info("%dx multi-block erase speed is %ld KiB/s\n",
++ blocks, speed);
++ }
++ pr_info("finished\n");
++out:
++ kfree(iobuf);
++ kfree(bbt);
++ put_mtd_device(mtd);
++ if (err)
++ pr_info("error %d occurred\n", err);
++ printk(KERN_INFO "=================================================\n");
++ return err;
++}
++module_init(mtd_speedtest_init);
++
++static void __exit mtd_speedtest_exit(void)
++{
++ return;
++}
++module_exit(mtd_speedtest_exit);
++
++MODULE_DESCRIPTION("Speed test module");
++MODULE_AUTHOR("Adrian Hunter");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/stresstest.c linux-linaro-stable-mx6/drivers/mtd/tests/stresstest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/stresstest.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/stresstest.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,321 @@
++/*
++ * Copyright (C) 2006-2008 Nokia Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; see the file COPYING. If not, write to the Free Software
++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Test random reads, writes and erases on MTD device.
++ *
++ * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <linux/slab.h>
++#include <linux/sched.h>
++#include <linux/vmalloc.h>
++#include <linux/random.h>
++
++static int dev = -EINVAL;
++module_param(dev, int, S_IRUGO);
++MODULE_PARM_DESC(dev, "MTD device number to use");
++
++static int count = 10000;
++module_param(count, int, S_IRUGO);
++MODULE_PARM_DESC(count, "Number of operations to do (default is 10000)");
++
++static struct mtd_info *mtd;
++static unsigned char *writebuf;
++static unsigned char *readbuf;
++static unsigned char *bbt;
++static int *offsets;
++
++static int pgsize;
++static int bufsize;
++static int ebcnt;
++static int pgcnt;
++
++static int rand_eb(void)
++{
++ unsigned int eb;
++
++again:
++ eb = prandom_u32();
++ /* Read or write up 2 eraseblocks at a time - hence 'ebcnt - 1' */
++ eb %= (ebcnt - 1);
++ if (bbt[eb])
++ goto again;
++ return eb;
++}
++
++static int rand_offs(void)
++{
++ unsigned int offs;
++
++ offs = prandom_u32();
++ offs %= bufsize;
++ return offs;
++}
++
++static int rand_len(int offs)
++{
++ unsigned int len;
++
++ len = prandom_u32();
++ len %= (bufsize - offs);
++ return len;
++}
++
++static int erase_eraseblock(int ebnum)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize;
++
++ err = mtd_erase(mtd, &ei);
++ if (unlikely(err)) {
++ pr_err("error %d while erasing EB %d\n", err, ebnum);
++ return err;
++ }
++
++ if (unlikely(ei.state == MTD_ERASE_FAILED)) {
++ pr_err("some erase error occurred at EB %d\n",
++ ebnum);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int is_block_bad(int ebnum)
++{
++ loff_t addr = ebnum * mtd->erasesize;
++ int ret;
++
++ ret = mtd_block_isbad(mtd, addr);
++ if (ret)
++ pr_info("block %d is bad\n", ebnum);
++ return ret;
++}
++
++static int do_read(void)
++{
++ size_t read;
++ int eb = rand_eb();
++ int offs = rand_offs();
++ int len = rand_len(offs), err;
++ loff_t addr;
++
++ if (bbt[eb + 1]) {
++ if (offs >= mtd->erasesize)
++ offs -= mtd->erasesize;
++ if (offs + len > mtd->erasesize)
++ len = mtd->erasesize - offs;
++ }
++ addr = eb * mtd->erasesize + offs;
++ err = mtd_read(mtd, addr, len, &read, readbuf);
++ if (mtd_is_bitflip(err))
++ err = 0;
++ if (unlikely(err || read != len)) {
++ pr_err("error: read failed at 0x%llx\n",
++ (long long)addr);
++ if (!err)
++ err = -EINVAL;
++ return err;
++ }
++ return 0;
++}
++
++static int do_write(void)
++{
++ int eb = rand_eb(), offs, err, len;
++ size_t written;
++ loff_t addr;
++
++ offs = offsets[eb];
++ if (offs >= mtd->erasesize) {
++ err = erase_eraseblock(eb);
++ if (err)
++ return err;
++ offs = offsets[eb] = 0;
++ }
++ len = rand_len(offs);
++ len = ((len + pgsize - 1) / pgsize) * pgsize;
++ if (offs + len > mtd->erasesize) {
++ if (bbt[eb + 1])
++ len = mtd->erasesize - offs;
++ else {
++ err = erase_eraseblock(eb + 1);
++ if (err)
++ return err;
++ offsets[eb + 1] = 0;
++ }
++ }
++ addr = eb * mtd->erasesize + offs;
++ err = mtd_write(mtd, addr, len, &written, writebuf);
++ if (unlikely(err || written != len)) {
++ pr_err("error: write failed at 0x%llx\n",
++ (long long)addr);
++ if (!err)
++ err = -EINVAL;
++ return err;
++ }
++ offs += len;
++ while (offs > mtd->erasesize) {
++ offsets[eb++] = mtd->erasesize;
++ offs -= mtd->erasesize;
++ }
++ offsets[eb] = offs;
++ return 0;
++}
++
++static int do_operation(void)
++{
++ if (prandom_u32() & 1)
++ return do_read();
++ else
++ return do_write();
++}
++
++static int scan_for_bad_eraseblocks(void)
++{
++ int i, bad = 0;
++
++ bbt = kzalloc(ebcnt, GFP_KERNEL);
++ if (!bbt)
++ return -ENOMEM;
++
++ if (!mtd_can_have_bb(mtd))
++ return 0;
++
++ pr_info("scanning for bad eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ bbt[i] = is_block_bad(i) ? 1 : 0;
++ if (bbt[i])
++ bad += 1;
++ cond_resched();
++ }
++ pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
++ return 0;
++}
++
++static int __init mtd_stresstest_init(void)
++{
++ int err;
++ int i, op;
++ uint64_t tmp;
++
++ printk(KERN_INFO "\n");
++ printk(KERN_INFO "=================================================\n");
++
++ if (dev < 0) {
++ pr_info("Please specify a valid mtd-device via module parameter\n");
++ pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
++ return -EINVAL;
++ }
++
++ pr_info("MTD device: %d\n", dev);
++
++ mtd = get_mtd_device(NULL, dev);
++ if (IS_ERR(mtd)) {
++ err = PTR_ERR(mtd);
++ pr_err("error: cannot get MTD device\n");
++ return err;
++ }
++
++ if (mtd->writesize == 1) {
++ pr_info("not NAND flash, assume page size is 512 "
++ "bytes.\n");
++ pgsize = 512;
++ } else
++ pgsize = mtd->writesize;
++
++ tmp = mtd->size;
++ do_div(tmp, mtd->erasesize);
++ ebcnt = tmp;
++ pgcnt = mtd->erasesize / pgsize;
++
++ pr_info("MTD device size %llu, eraseblock size %u, "
++ "page size %u, count of eraseblocks %u, pages per "
++ "eraseblock %u, OOB size %u\n",
++ (unsigned long long)mtd->size, mtd->erasesize,
++ pgsize, ebcnt, pgcnt, mtd->oobsize);
++
++ if (ebcnt < 2) {
++ pr_err("error: need at least 2 eraseblocks\n");
++ err = -ENOSPC;
++ goto out_put_mtd;
++ }
++
++ /* Read or write up 2 eraseblocks at a time */
++ bufsize = mtd->erasesize * 2;
++
++ err = -ENOMEM;
++ readbuf = vmalloc(bufsize);
++ writebuf = vmalloc(bufsize);
++ offsets = kmalloc(ebcnt * sizeof(int), GFP_KERNEL);
++ if (!readbuf || !writebuf || !offsets)
++ goto out;
++ for (i = 0; i < ebcnt; i++)
++ offsets[i] = mtd->erasesize;
++ prandom_bytes(writebuf, bufsize);
++
++ err = scan_for_bad_eraseblocks();
++ if (err)
++ goto out;
++
++ /* Do operations */
++ pr_info("doing operations\n");
++ for (op = 0; op < count; op++) {
++ if ((op & 1023) == 0)
++ pr_info("%d operations done\n", op);
++ err = do_operation();
++ if (err)
++ goto out;
++ cond_resched();
++ }
++ pr_info("finished, %d operations done\n", op);
++
++out:
++ kfree(offsets);
++ kfree(bbt);
++ vfree(writebuf);
++ vfree(readbuf);
++out_put_mtd:
++ put_mtd_device(mtd);
++ if (err)
++ pr_info("error %d occurred\n", err);
++ printk(KERN_INFO "=================================================\n");
++ return err;
++}
++module_init(mtd_stresstest_init);
++
++static void __exit mtd_stresstest_exit(void)
++{
++ return;
++}
++module_exit(mtd_stresstest_exit);
++
++MODULE_DESCRIPTION("Stress test module");
++MODULE_AUTHOR("Adrian Hunter");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/subpagetest.c linux-linaro-stable-mx6/drivers/mtd/tests/subpagetest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/subpagetest.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/subpagetest.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,504 @@
++/*
++ * Copyright (C) 2006-2007 Nokia Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; see the file COPYING. If not, write to the Free Software
++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Test sub-page read and write on MTD device.
++ * Author: Adrian Hunter <ext-adrian.hunter@nokia.com>
++ *
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <linux/slab.h>
++#include <linux/sched.h>
++#include <linux/random.h>
++
++static int dev = -EINVAL;
++module_param(dev, int, S_IRUGO);
++MODULE_PARM_DESC(dev, "MTD device number to use");
++
++static struct mtd_info *mtd;
++static unsigned char *writebuf;
++static unsigned char *readbuf;
++static unsigned char *bbt;
++
++static int subpgsize;
++static int bufsize;
++static int ebcnt;
++static int pgcnt;
++static int errcnt;
++static struct rnd_state rnd_state;
++
++static inline void clear_data(unsigned char *buf, size_t len)
++{
++ memset(buf, 0, len);
++}
++
++static int erase_eraseblock(int ebnum)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize;
++
++ err = mtd_erase(mtd, &ei);
++ if (err) {
++ pr_err("error %d while erasing EB %d\n", err, ebnum);
++ return err;
++ }
++
++ if (ei.state == MTD_ERASE_FAILED) {
++ pr_err("some erase error occurred at EB %d\n",
++ ebnum);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int erase_whole_device(void)
++{
++ int err;
++ unsigned int i;
++
++ pr_info("erasing whole device\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = erase_eraseblock(i);
++ if (err)
++ return err;
++ cond_resched();
++ }
++ pr_info("erased %u eraseblocks\n", i);
++ return 0;
++}
++
++static int write_eraseblock(int ebnum)
++{
++ size_t written;
++ int err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ prandom_bytes_state(&rnd_state, writebuf, subpgsize);
++ err = mtd_write(mtd, addr, subpgsize, &written, writebuf);
++ if (unlikely(err || written != subpgsize)) {
++ pr_err("error: write failed at %#llx\n",
++ (long long)addr);
++ if (written != subpgsize) {
++ pr_err(" write size: %#x\n", subpgsize);
++ pr_err(" written: %#zx\n", written);
++ }
++ return err ? err : -1;
++ }
++
++ addr += subpgsize;
++
++ prandom_bytes_state(&rnd_state, writebuf, subpgsize);
++ err = mtd_write(mtd, addr, subpgsize, &written, writebuf);
++ if (unlikely(err || written != subpgsize)) {
++ pr_err("error: write failed at %#llx\n",
++ (long long)addr);
++ if (written != subpgsize) {
++ pr_err(" write size: %#x\n", subpgsize);
++ pr_err(" written: %#zx\n", written);
++ }
++ return err ? err : -1;
++ }
++
++ return err;
++}
++
++static int write_eraseblock2(int ebnum)
++{
++ size_t written;
++ int err = 0, k;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ for (k = 1; k < 33; ++k) {
++ if (addr + (subpgsize * k) > (ebnum + 1) * mtd->erasesize)
++ break;
++ prandom_bytes_state(&rnd_state, writebuf, subpgsize * k);
++ err = mtd_write(mtd, addr, subpgsize * k, &written, writebuf);
++ if (unlikely(err || written != subpgsize * k)) {
++ pr_err("error: write failed at %#llx\n",
++ (long long)addr);
++ if (written != subpgsize) {
++ pr_err(" write size: %#x\n",
++ subpgsize * k);
++ pr_err(" written: %#08zx\n",
++ written);
++ }
++ return err ? err : -1;
++ }
++ addr += subpgsize * k;
++ }
++
++ return err;
++}
++
++static void print_subpage(unsigned char *p)
++{
++ int i, j;
++
++ for (i = 0; i < subpgsize; ) {
++ for (j = 0; i < subpgsize && j < 32; ++i, ++j)
++ printk("%02x", *p++);
++ printk("\n");
++ }
++}
++
++static int verify_eraseblock(int ebnum)
++{
++ size_t read;
++ int err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ prandom_bytes_state(&rnd_state, writebuf, subpgsize);
++ clear_data(readbuf, subpgsize);
++ err = mtd_read(mtd, addr, subpgsize, &read, readbuf);
++ if (unlikely(err || read != subpgsize)) {
++ if (mtd_is_bitflip(err) && read == subpgsize) {
++ pr_info("ECC correction at %#llx\n",
++ (long long)addr);
++ err = 0;
++ } else {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ return err ? err : -1;
++ }
++ }
++ if (unlikely(memcmp(readbuf, writebuf, subpgsize))) {
++ pr_err("error: verify failed at %#llx\n",
++ (long long)addr);
++ pr_info("------------- written----------------\n");
++ print_subpage(writebuf);
++ pr_info("------------- read ------------------\n");
++ print_subpage(readbuf);
++ pr_info("-------------------------------------\n");
++ errcnt += 1;
++ }
++
++ addr += subpgsize;
++
++ prandom_bytes_state(&rnd_state, writebuf, subpgsize);
++ clear_data(readbuf, subpgsize);
++ err = mtd_read(mtd, addr, subpgsize, &read, readbuf);
++ if (unlikely(err || read != subpgsize)) {
++ if (mtd_is_bitflip(err) && read == subpgsize) {
++ pr_info("ECC correction at %#llx\n",
++ (long long)addr);
++ err = 0;
++ } else {
++ pr_err("error: read failed at %#llx\n",
++ (long long)addr);
++ return err ? err : -1;
++ }
++ }
++ if (unlikely(memcmp(readbuf, writebuf, subpgsize))) {
++ pr_info("error: verify failed at %#llx\n",
++ (long long)addr);
++ pr_info("------------- written----------------\n");
++ print_subpage(writebuf);
++ pr_info("------------- read ------------------\n");
++ print_subpage(readbuf);
++ pr_info("-------------------------------------\n");
++ errcnt += 1;
++ }
++
++ return err;
++}
++
++static int verify_eraseblock2(int ebnum)
++{
++ size_t read;
++ int err = 0, k;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ for (k = 1; k < 33; ++k) {
++ if (addr + (subpgsize * k) > (ebnum + 1) * mtd->erasesize)
++ break;
++ prandom_bytes_state(&rnd_state, writebuf, subpgsize * k);
++ clear_data(readbuf, subpgsize * k);
++ err = mtd_read(mtd, addr, subpgsize * k, &read, readbuf);
++ if (unlikely(err || read != subpgsize * k)) {
++ if (mtd_is_bitflip(err) && read == subpgsize * k) {
++ pr_info("ECC correction at %#llx\n",
++ (long long)addr);
++ err = 0;
++ } else {
++ pr_err("error: read failed at "
++ "%#llx\n", (long long)addr);
++ return err ? err : -1;
++ }
++ }
++ if (unlikely(memcmp(readbuf, writebuf, subpgsize * k))) {
++ pr_err("error: verify failed at %#llx\n",
++ (long long)addr);
++ errcnt += 1;
++ }
++ addr += subpgsize * k;
++ }
++
++ return err;
++}
++
++static int verify_eraseblock_ff(int ebnum)
++{
++ uint32_t j;
++ size_t read;
++ int err = 0;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(writebuf, 0xff, subpgsize);
++ for (j = 0; j < mtd->erasesize / subpgsize; ++j) {
++ clear_data(readbuf, subpgsize);
++ err = mtd_read(mtd, addr, subpgsize, &read, readbuf);
++ if (unlikely(err || read != subpgsize)) {
++ if (mtd_is_bitflip(err) && read == subpgsize) {
++ pr_info("ECC correction at %#llx\n",
++ (long long)addr);
++ err = 0;
++ } else {
++ pr_err("error: read failed at "
++ "%#llx\n", (long long)addr);
++ return err ? err : -1;
++ }
++ }
++ if (unlikely(memcmp(readbuf, writebuf, subpgsize))) {
++ pr_err("error: verify 0xff failed at "
++ "%#llx\n", (long long)addr);
++ errcnt += 1;
++ }
++ addr += subpgsize;
++ }
++
++ return err;
++}
++
++static int verify_all_eraseblocks_ff(void)
++{
++ int err;
++ unsigned int i;
++
++ pr_info("verifying all eraseblocks for 0xff\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = verify_eraseblock_ff(i);
++ if (err)
++ return err;
++ if (i % 256 == 0)
++ pr_info("verified up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("verified %u eraseblocks\n", i);
++ return 0;
++}
++
++static int is_block_bad(int ebnum)
++{
++ loff_t addr = ebnum * mtd->erasesize;
++ int ret;
++
++ ret = mtd_block_isbad(mtd, addr);
++ if (ret)
++ pr_info("block %d is bad\n", ebnum);
++ return ret;
++}
++
++static int scan_for_bad_eraseblocks(void)
++{
++ int i, bad = 0;
++
++ bbt = kzalloc(ebcnt, GFP_KERNEL);
++ if (!bbt)
++ return -ENOMEM;
++
++ pr_info("scanning for bad eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ bbt[i] = is_block_bad(i) ? 1 : 0;
++ if (bbt[i])
++ bad += 1;
++ cond_resched();
++ }
++ pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
++ return 0;
++}
++
++static int __init mtd_subpagetest_init(void)
++{
++ int err = 0;
++ uint32_t i;
++ uint64_t tmp;
++
++ printk(KERN_INFO "\n");
++ printk(KERN_INFO "=================================================\n");
++
++ if (dev < 0) {
++ pr_info("Please specify a valid mtd-device via module parameter\n");
++ pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
++ return -EINVAL;
++ }
++
++ pr_info("MTD device: %d\n", dev);
++
++ mtd = get_mtd_device(NULL, dev);
++ if (IS_ERR(mtd)) {
++ err = PTR_ERR(mtd);
++ pr_err("error: cannot get MTD device\n");
++ return err;
++ }
++
++ if (!mtd_type_is_nand(mtd)) {
++ pr_info("this test requires NAND flash\n");
++ goto out;
++ }
++
++ subpgsize = mtd->writesize >> mtd->subpage_sft;
++ tmp = mtd->size;
++ do_div(tmp, mtd->erasesize);
++ ebcnt = tmp;
++ pgcnt = mtd->erasesize / mtd->writesize;
++
++ pr_info("MTD device size %llu, eraseblock size %u, "
++ "page size %u, subpage size %u, count of eraseblocks %u, "
++ "pages per eraseblock %u, OOB size %u\n",
++ (unsigned long long)mtd->size, mtd->erasesize,
++ mtd->writesize, subpgsize, ebcnt, pgcnt, mtd->oobsize);
++
++ err = -ENOMEM;
++ bufsize = subpgsize * 32;
++ writebuf = kmalloc(bufsize, GFP_KERNEL);
++ if (!writebuf)
++ goto out;
++ readbuf = kmalloc(bufsize, GFP_KERNEL);
++ if (!readbuf)
++ goto out;
++
++ err = scan_for_bad_eraseblocks();
++ if (err)
++ goto out;
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ pr_info("writing whole device\n");
++ prandom_seed_state(&rnd_state, 1);
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = write_eraseblock(i);
++ if (unlikely(err))
++ goto out;
++ if (i % 256 == 0)
++ pr_info("written up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("written %u eraseblocks\n", i);
++
++ prandom_seed_state(&rnd_state, 1);
++ pr_info("verifying all eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = verify_eraseblock(i);
++ if (unlikely(err))
++ goto out;
++ if (i % 256 == 0)
++ pr_info("verified up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("verified %u eraseblocks\n", i);
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ err = verify_all_eraseblocks_ff();
++ if (err)
++ goto out;
++
++ /* Write all eraseblocks */
++ prandom_seed_state(&rnd_state, 3);
++ pr_info("writing whole device\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = write_eraseblock2(i);
++ if (unlikely(err))
++ goto out;
++ if (i % 256 == 0)
++ pr_info("written up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("written %u eraseblocks\n", i);
++
++ /* Check all eraseblocks */
++ prandom_seed_state(&rnd_state, 3);
++ pr_info("verifying all eraseblocks\n");
++ for (i = 0; i < ebcnt; ++i) {
++ if (bbt[i])
++ continue;
++ err = verify_eraseblock2(i);
++ if (unlikely(err))
++ goto out;
++ if (i % 256 == 0)
++ pr_info("verified up to eraseblock %u\n", i);
++ cond_resched();
++ }
++ pr_info("verified %u eraseblocks\n", i);
++
++ err = erase_whole_device();
++ if (err)
++ goto out;
++
++ err = verify_all_eraseblocks_ff();
++ if (err)
++ goto out;
++
++ pr_info("finished with %d errors\n", errcnt);
++
++out:
++ kfree(bbt);
++ kfree(readbuf);
++ kfree(writebuf);
++ put_mtd_device(mtd);
++ if (err)
++ pr_info("error %d occurred\n", err);
++ printk(KERN_INFO "=================================================\n");
++ return err;
++}
++module_init(mtd_subpagetest_init);
++
++static void __exit mtd_subpagetest_exit(void)
++{
++ return;
++}
++module_exit(mtd_subpagetest_exit);
++
++MODULE_DESCRIPTION("Subpage test module");
++MODULE_AUTHOR("Adrian Hunter");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/tests/torturetest.c linux-linaro-stable-mx6/drivers/mtd/tests/torturetest.c
+--- linux-3.10.30.orig/drivers/mtd/tests/torturetest.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/tests/torturetest.c 2014-05-15 20:33:58.542017785 +0200
+@@ -0,0 +1,535 @@
++/*
++ * Copyright (C) 2006-2008 Artem Bityutskiy
++ * Copyright (C) 2006-2008 Jarkko Lavinen
++ * Copyright (C) 2006-2008 Adrian Hunter
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published by
++ * the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License along with
++ * this program; see the file COPYING. If not, write to the Free Software
++ * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
++ *
++ * Authors: Artem Bityutskiy, Jarkko Lavinen, Adria Hunter
++ *
++ * WARNING: this test program may kill your flash and your device. Do not
++ * use it unless you know what you do. Authors are not responsible for any
++ * damage caused by this program.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/err.h>
++#include <linux/mtd/mtd.h>
++#include <linux/slab.h>
++#include <linux/sched.h>
++
++#define RETRIES 3
++
++static int eb = 8;
++module_param(eb, int, S_IRUGO);
++MODULE_PARM_DESC(eb, "eraseblock number within the selected MTD device");
++
++static int ebcnt = 32;
++module_param(ebcnt, int, S_IRUGO);
++MODULE_PARM_DESC(ebcnt, "number of consecutive eraseblocks to torture");
++
++static int pgcnt;
++module_param(pgcnt, int, S_IRUGO);
++MODULE_PARM_DESC(pgcnt, "number of pages per eraseblock to torture (0 => all)");
++
++static int dev = -EINVAL;
++module_param(dev, int, S_IRUGO);
++MODULE_PARM_DESC(dev, "MTD device number to use");
++
++static int gran = 512;
++module_param(gran, int, S_IRUGO);
++MODULE_PARM_DESC(gran, "how often the status information should be printed");
++
++static int check = 1;
++module_param(check, int, S_IRUGO);
++MODULE_PARM_DESC(check, "if the written data should be checked");
++
++static unsigned int cycles_count;
++module_param(cycles_count, uint, S_IRUGO);
++MODULE_PARM_DESC(cycles_count, "how many erase cycles to do "
++ "(infinite by default)");
++
++static struct mtd_info *mtd;
++
++/* This buffer contains 0x555555...0xAAAAAA... pattern */
++static unsigned char *patt_5A5;
++/* This buffer contains 0xAAAAAA...0x555555... pattern */
++static unsigned char *patt_A5A;
++/* This buffer contains all 0xFF bytes */
++static unsigned char *patt_FF;
++/* This a temporary buffer is use when checking data */
++static unsigned char *check_buf;
++/* How many erase cycles were done */
++static unsigned int erase_cycles;
++
++static int pgsize;
++static struct timeval start, finish;
++
++static void report_corrupt(unsigned char *read, unsigned char *written);
++
++static inline void start_timing(void)
++{
++ do_gettimeofday(&start);
++}
++
++static inline void stop_timing(void)
++{
++ do_gettimeofday(&finish);
++}
++
++/*
++ * Erase eraseblock number @ebnum.
++ */
++static inline int erase_eraseblock(int ebnum)
++{
++ int err;
++ struct erase_info ei;
++ loff_t addr = ebnum * mtd->erasesize;
++
++ memset(&ei, 0, sizeof(struct erase_info));
++ ei.mtd = mtd;
++ ei.addr = addr;
++ ei.len = mtd->erasesize;
++
++ err = mtd_erase(mtd, &ei);
++ if (err) {
++ pr_err("error %d while erasing EB %d\n", err, ebnum);
++ return err;
++ }
++
++ if (ei.state == MTD_ERASE_FAILED) {
++ pr_err("some erase error occurred at EB %d\n",
++ ebnum);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++/*
++ * Check that the contents of eraseblock number @enbum is equivalent to the
++ * @buf buffer.
++ */
++static inline int check_eraseblock(int ebnum, unsigned char *buf)
++{
++ int err, retries = 0;
++ size_t read;
++ loff_t addr = ebnum * mtd->erasesize;
++ size_t len = mtd->erasesize;
++
++ if (pgcnt) {
++ addr = (ebnum + 1) * mtd->erasesize - pgcnt * pgsize;
++ len = pgcnt * pgsize;
++ }
++
++retry:
++ err = mtd_read(mtd, addr, len, &read, check_buf);
++ if (mtd_is_bitflip(err))
++ pr_err("single bit flip occurred at EB %d "
++ "MTD reported that it was fixed.\n", ebnum);
++ else if (err) {
++ pr_err("error %d while reading EB %d, "
++ "read %zd\n", err, ebnum, read);
++ return err;
++ }
++
++ if (read != len) {
++ pr_err("failed to read %zd bytes from EB %d, "
++ "read only %zd, but no error reported\n",
++ len, ebnum, read);
++ return -EIO;
++ }
++
++ if (memcmp(buf, check_buf, len)) {
++ pr_err("read wrong data from EB %d\n", ebnum);
++ report_corrupt(check_buf, buf);
++
++ if (retries++ < RETRIES) {
++ /* Try read again */
++ yield();
++ pr_info("re-try reading data from EB %d\n",
++ ebnum);
++ goto retry;
++ } else {
++ pr_info("retried %d times, still errors, "
++ "give-up\n", RETRIES);
++ return -EINVAL;
++ }
++ }
++
++ if (retries != 0)
++ pr_info("only attempt number %d was OK (!!!)\n",
++ retries);
++
++ return 0;
++}
++
++static inline int write_pattern(int ebnum, void *buf)
++{
++ int err;
++ size_t written;
++ loff_t addr = ebnum * mtd->erasesize;
++ size_t len = mtd->erasesize;
++
++ if (pgcnt) {
++ addr = (ebnum + 1) * mtd->erasesize - pgcnt * pgsize;
++ len = pgcnt * pgsize;
++ }
++ err = mtd_write(mtd, addr, len, &written, buf);
++ if (err) {
++ pr_err("error %d while writing EB %d, written %zd"
++ " bytes\n", err, ebnum, written);
++ return err;
++ }
++ if (written != len) {
++ pr_info("written only %zd bytes of %zd, but no error"
++ " reported\n", written, len);
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static int __init tort_init(void)
++{
++ int err = 0, i, infinite = !cycles_count;
++ int *bad_ebs;
++
++ printk(KERN_INFO "\n");
++ printk(KERN_INFO "=================================================\n");
++ pr_info("Warning: this program is trying to wear out your "
++ "flash, stop it if this is not wanted.\n");
++
++ if (dev < 0) {
++ pr_info("Please specify a valid mtd-device via module parameter\n");
++ pr_crit("CAREFUL: This test wipes all data on the specified MTD device!\n");
++ return -EINVAL;
++ }
++
++ pr_info("MTD device: %d\n", dev);
++ pr_info("torture %d eraseblocks (%d-%d) of mtd%d\n",
++ ebcnt, eb, eb + ebcnt - 1, dev);
++ if (pgcnt)
++ pr_info("torturing just %d pages per eraseblock\n",
++ pgcnt);
++ pr_info("write verify %s\n", check ? "enabled" : "disabled");
++
++ mtd = get_mtd_device(NULL, dev);
++ if (IS_ERR(mtd)) {
++ err = PTR_ERR(mtd);
++ pr_err("error: cannot get MTD device\n");
++ return err;
++ }
++
++ if (mtd->writesize == 1) {
++ pr_info("not NAND flash, assume page size is 512 "
++ "bytes.\n");
++ pgsize = 512;
++ } else
++ pgsize = mtd->writesize;
++
++ if (pgcnt && (pgcnt > mtd->erasesize / pgsize || pgcnt < 0)) {
++ pr_err("error: invalid pgcnt value %d\n", pgcnt);
++ goto out_mtd;
++ }
++
++ err = -ENOMEM;
++ patt_5A5 = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!patt_5A5)
++ goto out_mtd;
++
++ patt_A5A = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!patt_A5A)
++ goto out_patt_5A5;
++
++ patt_FF = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!patt_FF)
++ goto out_patt_A5A;
++
++ check_buf = kmalloc(mtd->erasesize, GFP_KERNEL);
++ if (!check_buf)
++ goto out_patt_FF;
++
++ bad_ebs = kcalloc(ebcnt, sizeof(*bad_ebs), GFP_KERNEL);
++ if (!bad_ebs)
++ goto out_check_buf;
++
++ err = 0;
++
++ /* Initialize patterns */
++ memset(patt_FF, 0xFF, mtd->erasesize);
++ for (i = 0; i < mtd->erasesize / pgsize; i++) {
++ if (!(i & 1)) {
++ memset(patt_5A5 + i * pgsize, 0x55, pgsize);
++ memset(patt_A5A + i * pgsize, 0xAA, pgsize);
++ } else {
++ memset(patt_5A5 + i * pgsize, 0xAA, pgsize);
++ memset(patt_A5A + i * pgsize, 0x55, pgsize);
++ }
++ }
++
++ /*
++ * Check if there is a bad eraseblock among those we are going to test.
++ */
++ if (mtd_can_have_bb(mtd)) {
++ for (i = eb; i < eb + ebcnt; i++) {
++ err = mtd_block_isbad(mtd, (loff_t)i * mtd->erasesize);
++
++ if (err < 0) {
++ pr_info("block_isbad() returned %d "
++ "for EB %d\n", err, i);
++ goto out;
++ }
++
++ if (err) {
++ pr_err("EB %d is bad. Skip it.\n", i);
++ bad_ebs[i - eb] = 1;
++ }
++ }
++ }
++
++ start_timing();
++ while (1) {
++ int i;
++ void *patt;
++
++ /* Erase all eraseblocks */
++ for (i = eb; i < eb + ebcnt; i++) {
++ if (bad_ebs[i - eb])
++ continue;
++ err = erase_eraseblock(i);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++
++ /* Check if the eraseblocks contain only 0xFF bytes */
++ if (check) {
++ for (i = eb; i < eb + ebcnt; i++) {
++ if (bad_ebs[i - eb])
++ continue;
++ err = check_eraseblock(i, patt_FF);
++ if (err) {
++ pr_info("verify failed"
++ " for 0xFF... pattern\n");
++ goto out;
++ }
++ cond_resched();
++ }
++ }
++
++ /* Write the pattern */
++ for (i = eb; i < eb + ebcnt; i++) {
++ if (bad_ebs[i - eb])
++ continue;
++ if ((eb + erase_cycles) & 1)
++ patt = patt_5A5;
++ else
++ patt = patt_A5A;
++ err = write_pattern(i, patt);
++ if (err)
++ goto out;
++ cond_resched();
++ }
++
++ /* Verify what we wrote */
++ if (check) {
++ for (i = eb; i < eb + ebcnt; i++) {
++ if (bad_ebs[i - eb])
++ continue;
++ if ((eb + erase_cycles) & 1)
++ patt = patt_5A5;
++ else
++ patt = patt_A5A;
++ err = check_eraseblock(i, patt);
++ if (err) {
++ pr_info("verify failed for %s"
++ " pattern\n",
++ ((eb + erase_cycles) & 1) ?
++ "0x55AA55..." : "0xAA55AA...");
++ goto out;
++ }
++ cond_resched();
++ }
++ }
++
++ erase_cycles += 1;
++
++ if (erase_cycles % gran == 0) {
++ long ms;
++
++ stop_timing();
++ ms = (finish.tv_sec - start.tv_sec) * 1000 +
++ (finish.tv_usec - start.tv_usec) / 1000;
++ pr_info("%08u erase cycles done, took %lu "
++ "milliseconds (%lu seconds)\n",
++ erase_cycles, ms, ms / 1000);
++ start_timing();
++ }
++
++ if (!infinite && --cycles_count == 0)
++ break;
++ }
++out:
++
++ pr_info("finished after %u erase cycles\n",
++ erase_cycles);
++ kfree(bad_ebs);
++out_check_buf:
++ kfree(check_buf);
++out_patt_FF:
++ kfree(patt_FF);
++out_patt_A5A:
++ kfree(patt_A5A);
++out_patt_5A5:
++ kfree(patt_5A5);
++out_mtd:
++ put_mtd_device(mtd);
++ if (err)
++ pr_info("error %d occurred during torturing\n", err);
++ printk(KERN_INFO "=================================================\n");
++ return err;
++}
++module_init(tort_init);
++
++static void __exit tort_exit(void)
++{
++ return;
++}
++module_exit(tort_exit);
++
++static int countdiffs(unsigned char *buf, unsigned char *check_buf,
++ unsigned offset, unsigned len, unsigned *bytesp,
++ unsigned *bitsp);
++static void print_bufs(unsigned char *read, unsigned char *written, int start,
++ int len);
++
++/*
++ * Report the detailed information about how the read EB differs from what was
++ * written.
++ */
++static void report_corrupt(unsigned char *read, unsigned char *written)
++{
++ int i;
++ int bytes, bits, pages, first;
++ int offset, len;
++ size_t check_len = mtd->erasesize;
++
++ if (pgcnt)
++ check_len = pgcnt * pgsize;
++
++ bytes = bits = pages = 0;
++ for (i = 0; i < check_len; i += pgsize)
++ if (countdiffs(written, read, i, pgsize, &bytes,
++ &bits) >= 0)
++ pages++;
++
++ pr_info("verify fails on %d pages, %d bytes/%d bits\n",
++ pages, bytes, bits);
++ pr_info("The following is a list of all differences between"
++ " what was read from flash and what was expected\n");
++
++ for (i = 0; i < check_len; i += pgsize) {
++ cond_resched();
++ bytes = bits = 0;
++ first = countdiffs(written, read, i, pgsize, &bytes,
++ &bits);
++ if (first < 0)
++ continue;
++
++ printk("-------------------------------------------------------"
++ "----------------------------------\n");
++
++ pr_info("Page %zd has %d bytes/%d bits failing verify,"
++ " starting at offset 0x%x\n",
++ (mtd->erasesize - check_len + i) / pgsize,
++ bytes, bits, first);
++
++ offset = first & ~0x7;
++ len = ((first + bytes) | 0x7) + 1 - offset;
++
++ print_bufs(read, written, offset, len);
++ }
++}
++
++static void print_bufs(unsigned char *read, unsigned char *written, int start,
++ int len)
++{
++ int i = 0, j1, j2;
++ char *diff;
++
++ printk("Offset Read Written\n");
++ while (i < len) {
++ printk("0x%08x: ", start + i);
++ diff = " ";
++ for (j1 = 0; j1 < 8 && i + j1 < len; j1++) {
++ printk(" %02x", read[start + i + j1]);
++ if (read[start + i + j1] != written[start + i + j1])
++ diff = "***";
++ }
++
++ while (j1 < 8) {
++ printk(" ");
++ j1 += 1;
++ }
++
++ printk(" %s ", diff);
++
++ for (j2 = 0; j2 < 8 && i + j2 < len; j2++)
++ printk(" %02x", written[start + i + j2]);
++ printk("\n");
++ i += 8;
++ }
++}
++
++/*
++ * Count the number of differing bytes and bits and return the first differing
++ * offset.
++ */
++static int countdiffs(unsigned char *buf, unsigned char *check_buf,
++ unsigned offset, unsigned len, unsigned *bytesp,
++ unsigned *bitsp)
++{
++ unsigned i, bit;
++ int first = -1;
++
++ for (i = offset; i < offset + len; i++)
++ if (buf[i] != check_buf[i]) {
++ first = i;
++ break;
++ }
++
++ while (i < offset + len) {
++ if (buf[i] != check_buf[i]) {
++ (*bytesp)++;
++ bit = 1;
++ while (bit < 256) {
++ if ((buf[i] & bit) != (check_buf[i] & bit))
++ (*bitsp)++;
++ bit <<= 1;
++ }
++ }
++ i++;
++ }
++
++ return first;
++}
++
++MODULE_DESCRIPTION("Eraseblock torturing module");
++MODULE_AUTHOR("Artem Bityutskiy, Jarkko Lavinen, Adrian Hunter");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mtd/ubi/build.c linux-linaro-stable-mx6/drivers/mtd/ubi/build.c
+--- linux-3.10.30.orig/drivers/mtd/ubi/build.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mtd/ubi/build.c 2014-05-15 20:33:58.542017785 +0200
+@@ -638,7 +638,7 @@
+ dbg_gen("sizeof(struct ubi_ainf_peb) %zu", sizeof(struct ubi_ainf_peb));
+ dbg_gen("sizeof(struct ubi_wl_entry) %zu", sizeof(struct ubi_wl_entry));
+
+- if (ubi->mtd->numeraseregions != 0) {
++ if (ubi->mtd->numeraseregions > 1) {
+ /*
+ * Some flashes have several erase regions. Different regions
+ * may have different eraseblock size and other
+diff -Nur linux-3.10.30.orig/drivers/mxc/asrc/Kconfig linux-linaro-stable-mx6/drivers/mxc/asrc/Kconfig
+--- linux-3.10.30.orig/drivers/mxc/asrc/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/asrc/Kconfig 2014-05-15 20:33:58.586018102 +0200
+@@ -0,0 +1,14 @@
++#
++# ASRC configuration
++#
++
++menu "MXC Asynchronous Sample Rate Converter support"
++
++config MXC_ASRC
++ tristate "ASRC support"
++ depends on SOC_IMX35 || SOC_IMX53 || SOC_IMX6Q
++ select SND_SOC_FSL_ASRC
++ ---help---
++ Say Y to get the ASRC service.
++
++endmenu
+diff -Nur linux-3.10.30.orig/drivers/mxc/asrc/Makefile linux-linaro-stable-mx6/drivers/mxc/asrc/Makefile
+--- linux-3.10.30.orig/drivers/mxc/asrc/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/asrc/Makefile 2014-05-15 20:33:58.586018102 +0200
+@@ -0,0 +1,4 @@
++#
++# Makefile for the kernel Asynchronous Sample Rate Converter driver
++#
++obj-$(CONFIG_MXC_ASRC) += mxc_asrc.o
+diff -Nur linux-3.10.30.orig/drivers/mxc/asrc/mxc_asrc.c linux-linaro-stable-mx6/drivers/mxc/asrc/mxc_asrc.c
+--- linux-3.10.30.orig/drivers/mxc/asrc/mxc_asrc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/asrc/mxc_asrc.c 2014-05-15 20:33:58.586018102 +0200
+@@ -0,0 +1,1957 @@
++/*
++ * Freescale Asynchronous Sample Rate Converter (ASRC) driver
++ *
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/clk.h>
++#include <linux/slab.h>
++#include <linux/delay.h>
++#include <linux/sched.h>
++#include <linux/regmap.h>
++#include <linux/module.h>
++#include <linux/proc_fs.h>
++#include <linux/pagemap.h>
++#include <linux/interrupt.h>
++#include <linux/miscdevice.h>
++#include <linux/dma-mapping.h>
++#include <linux/of_platform.h>
++#include <linux/platform_data/dma-imx.h>
++
++#include <linux/mxc_asrc.h>
++
++#define ASRC_PROC_PATH "driver/asrc"
++
++#define ASRC_RATIO_DECIMAL_DEPTH 26
++
++#define pair_err(fmt, ...) \
++ dev_err(asrc->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
++
++#define pair_dbg(fmt, ...) \
++ dev_dbg(asrc->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
++
++DEFINE_SPINLOCK(data_lock);
++DEFINE_SPINLOCK(pair_lock);
++
++/* Sample rates are aligned with that defined in pcm.h file */
++static const unsigned char asrc_process_table[][8][2] = {
++ /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
++ {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
++ {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
++ {{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
++ {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
++ {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
++ {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
++ {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
++};
++
++static struct asrc_data *asrc;
++
++/*
++ * The following tables map the relationship between asrc_inclk/asrc_outclk in
++ * mxc_asrc.h and the registers of ASRCSR
++ */
++static unsigned char input_clk_map_v1[] = {
++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
++};
++
++static unsigned char output_clk_map_v1[] = {
++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
++};
++
++/* V2 uses the same map for input and output */
++static unsigned char input_clk_map_v2[] = {
++/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
++ 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
++};
++
++static unsigned char output_clk_map_v2[] = {
++/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
++ 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
++};
++
++static unsigned char *input_clk_map, *output_clk_map;
++
++enum mxc_asrc_type {
++ IMX35_ASRC,
++ IMX53_ASRC,
++};
++
++static const struct platform_device_id mxc_asrc_devtype[] = {
++ {
++ .name = "imx35-asrc",
++ .driver_data = IMX35_ASRC,
++ }, {
++ .name = "imx53-asrc",
++ .driver_data = IMX53_ASRC,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, mxc_asrc_devtype);
++
++static const struct of_device_id fsl_asrc_ids[] = {
++ {
++ .compatible = "fsl,imx35-asrc",
++ .data = &mxc_asrc_devtype[IMX35_ASRC],
++ }, {
++ .compatible = "fsl,imx53-asrc",
++ .data = &mxc_asrc_devtype[IMX53_ASRC],
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
++
++
++#ifdef DEBUG
++u32 asrc_reg[] = {
++ REG_ASRCTR,
++ REG_ASRIER,
++ REG_ASRCNCR,
++ REG_ASRCFG,
++ REG_ASRCSR,
++ REG_ASRCDR1,
++ REG_ASRCDR2,
++ REG_ASRSTR,
++ REG_ASRRA,
++ REG_ASRRB,
++ REG_ASRRC,
++ REG_ASRPM1,
++ REG_ASRPM2,
++ REG_ASRPM3,
++ REG_ASRPM4,
++ REG_ASRPM5,
++ REG_ASRTFR1,
++ REG_ASRCCR,
++ REG_ASRIDRHA,
++ REG_ASRIDRLA,
++ REG_ASRIDRHB,
++ REG_ASRIDRLB,
++ REG_ASRIDRHC,
++ REG_ASRIDRLC,
++ REG_ASR76K,
++ REG_ASR56K,
++ REG_ASRMCRA,
++ REG_ASRFSTA,
++ REG_ASRMCRB,
++ REG_ASRFSTB,
++ REG_ASRMCRC,
++ REG_ASRFSTC,
++ REG_ASRMCR1A,
++ REG_ASRMCR1B,
++ REG_ASRMCR1C,
++};
++
++static void dump_regs(void)
++{
++ u32 reg, val;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(asrc_reg); i++) {
++ reg = asrc_reg[i];
++ regmap_read(asrc->regmap, reg, &val);
++ dev_dbg(asrc->dev, "REG addr=0x%x val=0x%x\n", reg, val);
++ }
++}
++#else
++static void dump_regs(void) {}
++#endif
++
++/* Only used for Ideal Ratio mode */
++static int asrc_set_clock_ratio(enum asrc_pair_index index,
++ int inrate, int outrate)
++{
++ unsigned long val = 0;
++ int integ, i;
++
++ if (outrate == 0) {
++ dev_err(asrc->dev, "wrong output sample rate: %d\n", outrate);
++ return -EINVAL;
++ }
++
++ /* Formula: r = (1 << ASRC_RATIO_DECIMAL_DEPTH) / outrate * inrate; */
++ for (integ = 0; inrate >= outrate; integ++)
++ inrate -= outrate;
++
++ val |= (integ << ASRC_RATIO_DECIMAL_DEPTH);
++
++ for (i = 1; i <= ASRC_RATIO_DECIMAL_DEPTH; i++) {
++ if ((inrate * 2) >= outrate) {
++ val |= (1 << (ASRC_RATIO_DECIMAL_DEPTH - i));
++ inrate = inrate * 2 - outrate;
++ } else
++ inrate = inrate << 1;
++
++ if (inrate == 0)
++ break;
++ }
++
++ regmap_write(asrc->regmap, REG_ASRIDRL(index), val);
++ regmap_write(asrc->regmap, REG_ASRIDRH(index), (val >> 24));
++
++ return 0;
++}
++
++/* Corresponding to asrc_process_table */
++static int supported_input_rate[] = {
++ 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
++ 96000, 176400, 192000,
++};
++
++static int supported_output_rate[] = {
++ 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
++};
++
++static int asrc_set_process_configuration(enum asrc_pair_index index,
++ int inrate, int outrate)
++{
++ int in, out;
++
++ for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++) {
++ if (inrate == supported_input_rate[in])
++ break;
++ }
++
++ if (in == ARRAY_SIZE(supported_input_rate)) {
++ dev_err(asrc->dev, "unsupported input sample rate: %d\n", in);
++ return -EINVAL;
++ }
++
++ for (out = 0; out < ARRAY_SIZE(supported_output_rate); out++) {
++ if (outrate == supported_output_rate[out])
++ break;
++ }
++
++ if (out == ARRAY_SIZE(supported_output_rate)) {
++ dev_err(asrc->dev, "unsupported output sample rate: %d\n", out);
++ return -EINVAL;
++ }
++
++ regmap_update_bits(asrc->regmap, REG_ASRCFG,
++ ASRCFG_PREMODx_MASK(index) | ASRCFG_POSTMODx_MASK(index),
++ ASRCFG_PREMOD(index, asrc_process_table[in][out][0]) |
++ ASRCFG_POSTMOD(index, asrc_process_table[in][out][1]));
++
++ return 0;
++}
++
++static int asrc_get_asrck_clock_divider(int samplerate)
++{
++ unsigned int prescaler, divider, ratio, ra, i;
++ unsigned long bitclk;
++
++ if (samplerate == 0) {
++ dev_err(asrc->dev, "invalid sample rate: %d\n", samplerate);
++ return -EINVAL;
++ }
++
++ bitclk = clk_get_rate(asrc->asrc_clk);
++
++ ra = bitclk / samplerate;
++ ratio = ra;
++
++ /* Calculate the prescaler */
++ for (i = 0; ratio > 8; i++)
++ ratio >>= 1;
++
++ prescaler = i;
++
++ /* Calculate the divider */
++ divider = i ? (((ra + (1 << (i - 1)) - 1) >> i) - 1) : (ra - 1);
++
++ /* The totally divider is (2 ^ prescaler) * divider */
++ return (divider << ASRCDRx_AxCPx_WIDTH) + prescaler;
++}
++
++int asrc_req_pair(int chn_num, enum asrc_pair_index *index)
++{
++ int imax = 0, busy = 0, i, ret = 0;
++ unsigned long lock_flags;
++ struct asrc_pair *pair;
++
++ spin_lock_irqsave(&data_lock, lock_flags);
++
++ for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
++ pair = &asrc->asrc_pair[i];
++ if (chn_num > pair->chn_max) {
++ imax++;
++ continue;
++ } else if (pair->active) {
++ busy++;
++ continue;
++ }
++ /* Save the current qualified pair */
++ *index = i;
++
++ /* Check if this pair is a perfect one */
++ if (chn_num == pair->chn_max)
++ break;
++ }
++
++ if (imax == ASRC_PAIR_MAX_NUM) {
++ dev_err(asrc->dev, "no pair could afford required channel number\n");
++ ret = -EINVAL;
++ } else if (busy == ASRC_PAIR_MAX_NUM) {
++ dev_err(asrc->dev, "all pairs are busy now\n");
++ ret = -EBUSY;
++ } else if (busy + imax >= ASRC_PAIR_MAX_NUM) {
++ dev_err(asrc->dev, "all affordable pairs are busy now\n");
++ ret = -EBUSY;
++ } else {
++ pair = &asrc->asrc_pair[*index];
++ pair->chn_num = chn_num;
++ pair->active = 1;
++ }
++
++ spin_unlock_irqrestore(&data_lock, lock_flags);
++
++ if (!ret) {
++ clk_enable(asrc->asrc_clk);
++ clk_prepare_enable(asrc->dma_clk);
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL(asrc_req_pair);
++
++void asrc_release_pair(enum asrc_pair_index index)
++{
++ struct asrc_pair *pair = &asrc->asrc_pair[index];
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&data_lock, lock_flags);
++
++ pair->active = 0;
++ pair->overload_error = 0;
++
++ spin_unlock_irqrestore(&data_lock, lock_flags);
++
++ /* Disable PAIR */
++ regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEx_MASK(index), 0);
++}
++EXPORT_SYMBOL(asrc_release_pair);
++
++int asrc_config_pair(struct asrc_config *config)
++{
++ u32 inrate = config->input_sample_rate, indiv;
++ u32 outrate = config->output_sample_rate, outdiv;
++ int ret, channels, index = config->pair;
++ unsigned long lock_flags;
++
++ /* Set the channel number */
++ spin_lock_irqsave(&data_lock, lock_flags);
++ asrc->asrc_pair[index].chn_num = config->channel_num;
++ spin_unlock_irqrestore(&data_lock, lock_flags);
++
++ if (asrc->channel_bits > 3)
++ channels = config->channel_num;
++ else
++ channels = (config->channel_num + 1) / 2;
++
++ /* Update channel number of current pair */
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(index, asrc->channel_bits),
++ ASRCNCR_ANCx_set(index, channels, asrc->channel_bits));
++
++ /* Set the clock source */
++ regmap_update_bits(asrc->regmap, REG_ASRCSR,
++ ASRCSR_AICSx_MASK(index) | ASRCSR_AOCSx_MASK(index),
++ ASRCSR_AICS(index, input_clk_map[config->inclk]) |
++ ASRCSR_AOCS(index, output_clk_map[config->outclk]));
++
++ /* Default setting: Automatic selection for processing mode */
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_ATSx_MASK(index), ASRCTR_ATS(index));
++ regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_USRx_MASK(index), 0);
++
++ /* Default Input Clock Divider Setting */
++ switch (config->inclk & ASRCSR_AxCSx_MASK) {
++ case INCLK_SPDIF_RX:
++ indiv = ASRC_PRESCALER_SPDIF_RX;
++ break;
++ case INCLK_SPDIF_TX:
++ indiv = ASRC_PRESCALER_SPDIF_TX;
++ break;
++ case INCLK_ASRCK1_CLK:
++ indiv = asrc_get_asrck_clock_divider(inrate);
++ break;
++ default:
++ switch (config->input_word_width) {
++ case ASRC_WIDTH_16_BIT:
++ indiv = ASRC_PRESCALER_I2S_16BIT;
++ break;
++ case ASRC_WIDTH_24_BIT:
++ indiv = ASRC_PRESCALER_I2S_24BIT;
++ break;
++ default:
++ pair_err("unsupported input word width %d\n",
++ config->input_word_width);
++ return -EINVAL;
++ }
++ break;
++ }
++
++ /* Default Output Clock Divider Setting */
++ switch (config->outclk & ASRCSR_AxCSx_MASK) {
++ case OUTCLK_SPDIF_RX:
++ outdiv = ASRC_PRESCALER_SPDIF_RX;
++ break;
++ case OUTCLK_SPDIF_TX:
++ outdiv = ASRC_PRESCALER_SPDIF_TX;
++ break;
++ case OUTCLK_ASRCK1_CLK:
++ if ((config->inclk & ASRCSR_AxCSx_MASK) == INCLK_NONE)
++ outdiv = ASRC_PRESCALER_IDEAL_RATIO;
++ else
++ outdiv = asrc_get_asrck_clock_divider(outrate);
++ break;
++ default:
++ switch (config->output_word_width) {
++ case ASRC_WIDTH_16_BIT:
++ outdiv = ASRC_PRESCALER_I2S_16BIT;
++ break;
++ case ASRC_WIDTH_24_BIT:
++ outdiv = ASRC_PRESCALER_I2S_24BIT;
++ break;
++ default:
++ pair_err("unsupported output word width %d\n",
++ config->input_word_width);
++ return -EINVAL;
++ }
++ break;
++ }
++
++ /* indiv and outdiv'd include prescaler's value, so add its MASK too */
++ regmap_update_bits(asrc->regmap, REG_ASRCDR(index),
++ ASRCDRx_AOCPx_MASK(index) | ASRCDRx_AICPx_MASK(index) |
++ ASRCDRx_AOCDx_MASK(index) | ASRCDRx_AICDx_MASK(index),
++ ASRCDRx_AOCP(index, outdiv) | ASRCDRx_AICP(index, indiv));
++
++ /* Check whether ideal ratio is a must */
++ switch (config->inclk & ASRCSR_AxCSx_MASK) {
++ case INCLK_NONE:
++ /* Clear ASTSx bit to use ideal ratio */
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_ATSx_MASK(index), 0);
++
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_IDRx_MASK(index) | ASRCTR_USRx_MASK(index),
++ ASRCTR_IDR(index) | ASRCTR_USR(index));
++
++ ret = asrc_set_clock_ratio(index, inrate, outrate);
++ if (ret)
++ return ret;
++
++ ret = asrc_set_process_configuration(index, inrate, outrate);
++ if (ret)
++ return ret;
++
++ break;
++ case INCLK_ASRCK1_CLK:
++ /* This case and default are both remained for v1 */
++ if (inrate == 44100 || inrate == 88200) {
++ pair_err("unsupported sample rate %d by selected clock\n",
++ inrate);
++ return -EINVAL;
++ }
++ break;
++ default:
++ if ((config->outclk & ASRCSR_AxCSx_MASK) != OUTCLK_ASRCK1_CLK)
++ break;
++
++ if (outrate == 44100 || outrate == 88200) {
++ pair_err("unsupported sample rate %d by selected clock\n",
++ outrate);
++ return -EINVAL;
++ }
++ break;
++ }
++
++ /* Config input and output wordwidth */
++ if (config->output_word_width == ASRC_WIDTH_8_BIT) {
++ pair_err("unsupported wordwidth for output: 8bit\n");
++ pair_err("output only support: 16bit or 24bit\n");
++ return -EINVAL;
++ }
++
++ regmap_update_bits(asrc->regmap, REG_ASRMCR1(index),
++ ASRMCR1x_OW16_MASK | ASRMCR1x_IWD_MASK,
++ ASRMCR1x_OW16(config->output_word_width) |
++ ASRMCR1x_IWD(config->input_word_width));
++
++ /* Enable BUFFER STALL */
++ regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
++ ASRMCRx_BUFSTALLx_MASK, ASRMCRx_BUFSTALLx);
++
++ /* Set Threshold for input and output FIFO */
++ return asrc_set_watermark(index, ASRC_INPUTFIFO_THRESHOLD,
++ ASRC_INPUTFIFO_THRESHOLD);
++}
++EXPORT_SYMBOL(asrc_config_pair);
++
++int asrc_set_watermark(enum asrc_pair_index index, u32 in_wm, u32 out_wm)
++{
++ if (in_wm > ASRC_FIFO_THRESHOLD_MAX || out_wm > ASRC_FIFO_THRESHOLD_MAX) {
++ pair_err("invalid watermark!\n");
++ return -EINVAL;
++ }
++
++ return regmap_update_bits(asrc->regmap, REG_ASRMCR(index),
++ ASRMCRx_EXTTHRSHx_MASK | ASRMCRx_INFIFO_THRESHOLD_MASK |
++ ASRMCRx_OUTFIFO_THRESHOLD_MASK,
++ ASRMCRx_EXTTHRSHx | ASRMCRx_INFIFO_THRESHOLD(in_wm) |
++ ASRMCRx_OUTFIFO_THRESHOLD(out_wm));
++}
++EXPORT_SYMBOL(asrc_set_watermark);
++
++void asrc_start_conv(enum asrc_pair_index index)
++{
++ int reg, retry, channels, i;
++
++ regmap_update_bits(asrc->regmap, REG_ASRCTR,
++ ASRCTR_ASRCEx_MASK(index), ASRCTR_ASRCE(index));
++
++ /* Wait for status of initialization */
++ for (retry = 10, reg = 0; !reg && retry; --retry) {
++ udelay(5);
++ regmap_read(asrc->regmap, REG_ASRCFG, &reg);
++ reg &= ASRCFG_INIRQx_MASK(index);
++ }
++
++ /* Set the input fifo to ASRC STALL level */
++ regmap_read(asrc->regmap, REG_ASRCNCR, &reg);
++ channels = ASRCNCR_ANCx_get(index, reg, asrc->channel_bits);
++ for (i = 0; i < channels * 4; i++)
++ regmap_write(asrc->regmap, REG_ASRDI(index), 0);
++
++ /* Overload Interrupt Enable */
++ regmap_write(asrc->regmap, REG_ASRIER, ASRIER_AOLIE);
++}
++EXPORT_SYMBOL(asrc_start_conv);
++
++void asrc_stop_conv(enum asrc_pair_index index)
++{
++ regmap_update_bits(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEx_MASK(index), 0);
++}
++EXPORT_SYMBOL(asrc_stop_conv);
++
++void asrc_finish_conv(enum asrc_pair_index index)
++{
++ clk_disable_unprepare(asrc->dma_clk);
++ clk_disable(asrc->asrc_clk);
++}
++EXPORT_SYMBOL(asrc_finish_conv);
++
++#define SET_OVERLOAD_ERR(index, err, msg) \
++ do { \
++ asrc->asrc_pair[index].overload_error |= err; \
++ pair_dbg(msg); \
++ } while (0)
++
++static irqreturn_t asrc_isr(int irq, void *dev_id)
++{
++ enum asrc_pair_index index;
++ u32 status;
++
++ regmap_read(asrc->regmap, REG_ASRSTR, &status);
++
++ for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
++ if (asrc->asrc_pair[index].active == 0)
++ continue;
++ if (status & ASRSTR_ATQOL)
++ SET_OVERLOAD_ERR(index, ASRC_TASK_Q_OVERLOAD,
++ "Task Queue FIFO overload");
++ if (status & ASRSTR_AOOL(index))
++ SET_OVERLOAD_ERR(index, ASRC_OUTPUT_TASK_OVERLOAD,
++ "Output Task Overload");
++ if (status & ASRSTR_AIOL(index))
++ SET_OVERLOAD_ERR(index, ASRC_INPUT_TASK_OVERLOAD,
++ "Input Task Overload");
++ if (status & ASRSTR_AODO(index))
++ SET_OVERLOAD_ERR(index, ASRC_OUTPUT_BUFFER_OVERFLOW,
++ "Output Data Buffer has overflowed");
++ if (status & ASRSTR_AIDU(index))
++ SET_OVERLOAD_ERR(index, ASRC_INPUT_BUFFER_UNDERRUN,
++ "Input Data Buffer has underflowed");
++ }
++
++ /* Clean overload error */
++ regmap_write(asrc->regmap, REG_ASRSTR, ASRSTR_AOLE);
++
++ return IRQ_HANDLED;
++}
++
++void asrc_get_status(struct asrc_status_flags *flags)
++{
++ enum asrc_pair_index index = flags->index;
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&data_lock, lock_flags);
++
++ flags->overload_error = asrc->asrc_pair[index].overload_error;
++
++ spin_unlock_irqrestore(&data_lock, lock_flags);
++}
++EXPORT_SYMBOL(asrc_get_status);
++
++u32 asrc_get_per_addr(enum asrc_pair_index index, bool in)
++{
++ return asrc->paddr + (in ? REG_ASRDI(index) : REG_ASRDO(index));
++}
++EXPORT_SYMBOL(asrc_get_per_addr);
++
++static int mxc_init_asrc(void)
++{
++ /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
++ regmap_write(asrc->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
++
++ /* Disable interrupt by default */
++ regmap_write(asrc->regmap, REG_ASRIER, 0x0);
++
++ /* Default 2: 6: 2 channel assignment */
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_A, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_A, 2, asrc->channel_bits));
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_B, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_B, 6, asrc->channel_bits));
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_C, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_C, 2, asrc->channel_bits));
++
++ /* Parameter Registers recommended settings */
++ regmap_write(asrc->regmap, REG_ASRPM1, 0x7fffff);
++ regmap_write(asrc->regmap, REG_ASRPM2, 0x255555);
++ regmap_write(asrc->regmap, REG_ASRPM3, 0xff7280);
++ regmap_write(asrc->regmap, REG_ASRPM4, 0xff7280);
++ regmap_write(asrc->regmap, REG_ASRPM5, 0xff7280);
++
++ /* Base address for task queue FIFO. Set to 0x7C */
++ regmap_update_bits(asrc->regmap, REG_ASRTFR1,
++ ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
++
++ /* Set the processing clock for 76KHz, 133M */
++ regmap_write(asrc->regmap, REG_ASR76K, 0x06D6);
++
++ /* Set the processing clock for 56KHz, 133M */
++ return regmap_write(asrc->regmap, REG_ASR56K, 0x0947);
++}
++
++#define ASRC_xPUT_DMA_CALLBACK(in) \
++ ((in) ? asrc_input_dma_callback : asrc_output_dma_callback)
++
++static void asrc_input_dma_callback(void *data)
++{
++ struct asrc_pair_params *params = (struct asrc_pair_params *)data;
++
++ dma_unmap_sg(NULL, params->input_sg, params->input_sg_nodes,
++ DMA_MEM_TO_DEV);
++
++ complete(&params->input_complete);
++
++ schedule_work(&params->task_output_work);
++}
++
++static void asrc_output_dma_callback(void *data)
++{
++ struct asrc_pair_params *params = (struct asrc_pair_params *)data;
++
++ dma_unmap_sg(NULL, params->output_sg, params->output_sg_nodes,
++ DMA_DEV_TO_MEM);
++
++ complete(&params->output_complete);
++}
++
++static unsigned int asrc_get_output_FIFO_size(enum asrc_pair_index index)
++{
++ u32 val;
++
++ regmap_read(asrc->regmap, REG_ASRFST(index), &val);
++
++ val &= ASRFSTx_OUTPUT_FIFO_MASK;
++
++ return val >> ASRFSTx_OUTPUT_FIFO_SHIFT;
++}
++
++static u32 asrc_read_one_from_output_FIFO(enum asrc_pair_index index)
++{
++ u32 val;
++
++ regmap_read(asrc->regmap, REG_ASRDO(index), &val);
++
++ return val;
++}
++
++static void asrc_read_output_FIFO(struct asrc_pair_params *params)
++{
++ u32 *reg24 = params->output_last_period.dma_vaddr;
++ u16 *reg16 = params->output_last_period.dma_vaddr;
++ enum asrc_pair_index index = params->index;
++ u32 i, j, reg, size, t_size;
++ bool bit24 = false;
++
++ if (params->output_word_width == ASRC_WIDTH_24_BIT)
++ bit24 = true;
++
++ t_size = 0;
++ do {
++ size = asrc_get_output_FIFO_size(index);
++ for (i = 0; i < size; i++) {
++ for (j = 0; j < params->channel_nums; j++) {
++ reg = asrc_read_one_from_output_FIFO(index);
++ if (bit24) {
++ *(reg24) = reg;
++ reg24++;
++ } else {
++ *(reg16) = (u16)reg;
++ reg16++;
++ }
++ }
++ }
++ t_size += size;
++ } while (size);
++
++ if (t_size > params->last_period_sample)
++ t_size = params->last_period_sample;
++
++ params->output_last_period.length = t_size * params->channel_nums * 2;
++ if (bit24)
++ params->output_last_period.length *= 2;
++}
++
++static void asrc_output_task_worker(struct work_struct *w)
++{
++ struct asrc_pair_params *params =
++ container_of(w, struct asrc_pair_params, task_output_work);
++ enum asrc_pair_index index = params->index;
++ unsigned long lock_flags;
++
++ if (!wait_for_completion_interruptible_timeout(&params->output_complete, HZ / 10)) {
++ pair_err("output dma task timeout\n");
++ return;
++ }
++
++ init_completion(&params->output_complete);
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ if (!params->pair_hold) {
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++ return;
++ }
++ asrc_read_output_FIFO(params);
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++
++ complete(&params->lastperiod_complete);
++}
++
++static void mxc_free_dma_buf(struct asrc_pair_params *params)
++{
++ if (params->input_dma_total.dma_vaddr != NULL) {
++ kfree(params->input_dma_total.dma_vaddr);
++ params->input_dma_total.dma_vaddr = NULL;
++ }
++
++ if (params->output_dma_total.dma_vaddr != NULL) {
++ kfree(params->output_dma_total.dma_vaddr);
++ params->output_dma_total.dma_vaddr = NULL;
++ }
++
++ if (params->output_last_period.dma_vaddr) {
++ dma_free_coherent(asrc->dev, 1024 * params->last_period_sample,
++ params->output_last_period.dma_vaddr,
++ params->output_last_period.dma_paddr);
++ params->output_last_period.dma_vaddr = NULL;
++ }
++}
++
++static int mxc_allocate_dma_buf(struct asrc_pair_params *params)
++{
++ struct dma_block *input_a, *output_a, *last_period;
++ enum asrc_pair_index index = params->index;
++
++ input_a = &params->input_dma_total;
++ output_a = &params->output_dma_total;
++ last_period = &params->output_last_period;
++
++ input_a->dma_vaddr = kzalloc(input_a->length, GFP_KERNEL);
++ if (!input_a->dma_vaddr) {
++ pair_err("failed to allocate input dma buffer\n");
++ goto exit;
++ }
++ input_a->dma_paddr = virt_to_dma(NULL, input_a->dma_vaddr);
++
++ output_a->dma_vaddr = kzalloc(output_a->length, GFP_KERNEL);
++ if (!output_a->dma_vaddr) {
++ pair_err("failed to allocate output dma buffer\n");
++ goto exit;
++ }
++ output_a->dma_paddr = virt_to_dma(NULL, output_a->dma_vaddr);
++
++ last_period->dma_vaddr = dma_alloc_coherent(asrc->dev,
++ 1024 * params->last_period_sample,
++ &last_period->dma_paddr, GFP_KERNEL);
++ if (!last_period->dma_vaddr) {
++ pair_err("failed to allocate last period buffer\n");
++ goto exit;
++ }
++
++ return 0;
++
++exit:
++ mxc_free_dma_buf(params);
++
++ return -ENOBUFS;
++}
++
++static struct dma_chan *imx_asrc_get_dma_channel(enum asrc_pair_index index, bool in)
++{
++ char name[4];
++
++ sprintf(name, "%cx%c", in ? 'r' : 't', index + 'a');
++
++ return dma_request_slave_channel(asrc->dev, name);
++}
++
++static int imx_asrc_dma_config(struct asrc_pair_params *params,
++ struct dma_chan *chan, u32 dma_addr,
++ void *buf_addr, u32 buf_len, bool in,
++ enum asrc_word_width word_width)
++{
++ enum asrc_pair_index index = params->index;
++ struct dma_async_tx_descriptor *desc;
++ struct dma_slave_config slave_config;
++ enum dma_slave_buswidth buswidth;
++ struct scatterlist *sg;
++ unsigned int sg_nent, i;
++ int ret;
++
++ if (in) {
++ sg = params->input_sg;
++ sg_nent = params->input_sg_nodes;
++ desc = params->desc_in;
++ } else {
++ sg = params->output_sg;
++ sg_nent = params->output_sg_nodes;
++ desc = params->desc_out;
++ }
++
++ switch (word_width) {
++ case ASRC_WIDTH_16_BIT:
++ buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++ break;
++ case ASRC_WIDTH_24_BIT:
++ buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ break;
++ default:
++ pair_err("invalid word width\n");
++ return -EINVAL;
++ }
++
++ slave_config.dma_request0 = 0;
++ slave_config.dma_request1 = 0;
++
++ if (in) {
++ slave_config.direction = DMA_MEM_TO_DEV;
++ slave_config.dst_addr = dma_addr;
++ slave_config.dst_addr_width = buswidth;
++ slave_config.dst_maxburst =
++ params->input_wm * params->channel_nums / buswidth;
++ } else {
++ slave_config.direction = DMA_DEV_TO_MEM;
++ slave_config.src_addr = dma_addr;
++ slave_config.src_addr_width = buswidth;
++ slave_config.src_maxburst =
++ params->output_wm * params->channel_nums / buswidth;
++ }
++ ret = dmaengine_slave_config(chan, &slave_config);
++ if (ret) {
++ pair_err("failed to config dmaengine for %sput task: %d\n",
++ in ? "in" : "out", ret);
++ return -EINVAL;
++ }
++
++ sg_init_table(sg, sg_nent);
++ switch (sg_nent) {
++ case 1:
++ sg_init_one(sg, buf_addr, buf_len);
++ break;
++ case 2:
++ case 3:
++ case 4:
++ for (i = 0; i < (sg_nent - 1); i++)
++ sg_set_buf(&sg[i], buf_addr + i * ASRC_MAX_BUFFER_SIZE,
++ ASRC_MAX_BUFFER_SIZE);
++
++ sg_set_buf(&sg[i], buf_addr + i * ASRC_MAX_BUFFER_SIZE,
++ buf_len - ASRC_MAX_BUFFER_SIZE * i);
++ break;
++ default:
++ pair_err("invalid input DMA nodes number: %d\n", sg_nent);
++ return -EINVAL;
++ }
++
++ ret = dma_map_sg(NULL, sg, sg_nent, slave_config.direction);
++ if (ret != sg_nent) {
++ pair_err("failed to map dma sg for %sput task\n",
++ in ? "in" : "out");
++ return -EINVAL;
++ }
++
++ desc = dmaengine_prep_slave_sg(chan, sg, sg_nent,
++ slave_config.direction, DMA_PREP_INTERRUPT);
++ if (!desc) {
++ pair_err("failed to prepare slave sg for %sput task\n",
++ in ? "in" : "out");
++ return -EINVAL;
++ }
++
++ if (in) {
++ params->desc_in = desc;
++ params->desc_in->callback = asrc_input_dma_callback;
++ } else {
++ params->desc_out = desc;
++ params->desc_out->callback = asrc_output_dma_callback;
++ }
++
++ desc->callback = ASRC_xPUT_DMA_CALLBACK(in);
++ desc->callback_param = params;
++
++ return 0;
++}
++
++static int mxc_asrc_prepare_io_buffer(struct asrc_pair_params *params,
++ struct asrc_convert_buffer *pbuf, bool in)
++{
++ enum asrc_pair_index index = params->index;
++ struct dma_chan *dma_channel;
++ enum asrc_word_width width;
++ unsigned int *dma_len, *sg_nodes, buf_len, wm;
++ void __user *buf_vaddr;
++ void *dma_vaddr;
++ u32 word_size, fifo_addr;
++
++ if (in) {
++ dma_channel = params->input_dma_channel;
++ dma_vaddr = params->input_dma_total.dma_vaddr;
++ dma_len = &params->input_dma_total.length;
++ width = params->input_word_width;
++ sg_nodes = &params->input_sg_nodes;
++ wm = params->input_wm;
++ buf_vaddr = (void __user *)pbuf->input_buffer_vaddr;
++ buf_len = pbuf->input_buffer_length;
++ } else {
++ dma_channel = params->output_dma_channel;
++ dma_vaddr = params->output_dma_total.dma_vaddr;
++ dma_len = &params->output_dma_total.length;
++ width = params->output_word_width;
++ sg_nodes = &params->output_sg_nodes;
++ wm = params->last_period_sample;
++ buf_vaddr = (void __user *)pbuf->output_buffer_vaddr;
++ buf_len = pbuf->output_buffer_length;
++ }
++
++ switch (width) {
++ case ASRC_WIDTH_24_BIT:
++ word_size = 4;
++ break;
++ case ASRC_WIDTH_16_BIT:
++ case ASRC_WIDTH_8_BIT:
++ word_size = 2;
++ break;
++ default:
++ pair_err("invalid %sput word size!\n", in ? "in" : "out");
++ return -EINVAL;
++ }
++
++ if (buf_len < word_size * params->channel_nums * wm) {
++ pair_err("%sput buffer size[%d] is too small!\n",
++ in ? "in" : "out", buf_len);
++ return -EINVAL;
++ }
++
++ /* Copy origin data into input buffer */
++ if (in && copy_from_user(dma_vaddr, buf_vaddr, buf_len))
++ return -EFAULT;
++
++ *dma_len = buf_len;
++ if (!in)
++ *dma_len -= wm * word_size * params->channel_nums;
++
++ *sg_nodes = *dma_len / ASRC_MAX_BUFFER_SIZE + 1;
++
++ fifo_addr = asrc_get_per_addr(params->index, in);
++
++ return imx_asrc_dma_config(params, dma_channel, fifo_addr, dma_vaddr,
++ *dma_len, in, width);
++}
++
++static int mxc_asrc_prepare_buffer(struct asrc_pair_params *params,
++ struct asrc_convert_buffer *pbuf)
++{
++ enum asrc_pair_index index = params->index;
++ int ret;
++
++ ret = mxc_asrc_prepare_io_buffer(params, pbuf, true);
++ if (ret) {
++ pair_err("failed to prepare input buffer: %d\n", ret);
++ return ret;
++ }
++
++ ret = mxc_asrc_prepare_io_buffer(params, pbuf, false);
++ if (ret) {
++ pair_err("failed to prepare output buffer: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++int mxc_asrc_process_io_buffer(struct asrc_pair_params *params,
++ struct asrc_convert_buffer *pbuf, bool in)
++{
++ void *last_vaddr = params->output_last_period.dma_vaddr;
++ unsigned int *last_len = &params->output_last_period.length;
++ enum asrc_pair_index index = params->index;
++ unsigned int dma_len, *buf_len;
++ struct completion *complete;
++ void __user *buf_vaddr;
++ void *dma_vaddr;
++
++ if (in) {
++ dma_vaddr = params->input_dma_total.dma_vaddr;
++ dma_len = params->input_dma_total.length;
++ buf_len = &pbuf->input_buffer_length;
++ complete = &params->input_complete;
++ buf_vaddr = (void __user *)pbuf->input_buffer_vaddr;
++ } else {
++ dma_vaddr = params->output_dma_total.dma_vaddr;
++ dma_len = params->output_dma_total.length;
++ buf_len = &pbuf->output_buffer_length;
++ complete = &params->lastperiod_complete;
++ buf_vaddr = (void __user *)pbuf->output_buffer_vaddr;
++ }
++
++ if (!wait_for_completion_interruptible_timeout(complete, 10 * HZ)) {
++ pair_err("%s task timeout\n", in ? "input dma" : "last period");
++ return -ETIME;
++ } else if (signal_pending(current)) {
++ pair_err("%sput task forcibly aborted\n", in ? "in" : "out");
++ return -ERESTARTSYS;
++ }
++
++ init_completion(complete);
++
++ *buf_len = dma_len;
++
++ /* Only output need return data to user space */
++ if (!in) {
++ if (copy_to_user(buf_vaddr, dma_vaddr, dma_len))
++ return -EFAULT;
++
++ *buf_len += *last_len;
++
++ if (copy_to_user(buf_vaddr + dma_len, last_vaddr, *last_len))
++ return -EFAULT;
++ }
++
++ return 0;
++}
++
++int mxc_asrc_process_buffer(struct asrc_pair_params *params,
++ struct asrc_convert_buffer *pbuf)
++{
++ enum asrc_pair_index index = params->index;
++ int ret;
++
++ ret = mxc_asrc_process_io_buffer(params, pbuf, true);
++ if (ret) {
++ pair_err("failed to process input buffer: %d\n", ret);
++ return ret;
++ }
++
++ ret = mxc_asrc_process_io_buffer(params, pbuf, false);
++ if (ret) {
++ pair_err("failed to process output buffer: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++#ifdef ASRC_POLLING_WITHOUT_DMA
++static void asrc_write_one_to_input_FIFO(enum asrc_pair_index index, u32 val)
++{
++ regmap_write(asrc->regmap, REG_ASRDI(index), val);
++}
++
++/* THIS FUNCTION ONLY EXISTS FOR DEBUGGING AND ONLY SUPPORTS TWO CHANNELS */
++static void asrc_polling_debug(struct asrc_pair_params *params)
++{
++ enum asrc_pair_index index = params->index;
++ u32 *in24 = params->input_dma_total.dma_vaddr;
++ u32 dma_len = params->input_dma_total.length / (params->channel_nums * 4);
++ u32 size, i, j, t_size, reg;
++ u32 *reg24 = params->output_dma_total.dma_vaddr;
++
++ t_size = 0;
++
++ for (i = 0; i < dma_len; ) {
++ for (j = 0; j < 2; j++) {
++ asrc_write_one_to_input_FIFO(index, *in24);
++ in24++;
++ asrc_write_one_to_input_FIFO(index, *in24);
++ in24++;
++ i++;
++ }
++ udelay(50);
++ udelay(50 * params->output_sample_rate / params->input_sample_rate);
++
++ size = asrc_get_output_FIFO_size(index);
++ for (j = 0; j < size; j++) {
++ reg = asrc_read_one_from_output_FIFO(index);
++ *(reg24) = reg;
++ reg24++;
++ reg = asrc_read_one_from_output_FIFO(index);
++ *(reg24) = reg;
++ reg24++;
++ }
++ t_size += size;
++ }
++
++ mdelay(1);
++ size = asrc_get_output_FIFO_size(index);
++ for (j = 0; j < size; j++) {
++ reg = asrc_read_one_from_output_FIFO(index);
++ *(reg24) = reg;
++ reg24++;
++ reg = asrc_read_one_from_output_FIFO(index);
++ *(reg24) = reg;
++ reg24++;
++ }
++ t_size += size;
++
++ params->output_dma_total.length = t_size * params->channel_nums * 4;
++ params->output_last_period.length = 0;
++
++ dma_unmap_sg(NULL, params->input_sg, params->input_sg_nodes,
++ DMA_MEM_TO_DEV);
++ dma_unmap_sg(NULL, params->output_sg, params->output_sg_nodes,
++ DMA_DEV_TO_MEM);
++
++ complete(&params->input_complete);
++ complete(&params->lastperiod_complete);
++}
++#else
++static void mxc_asrc_submit_dma(struct asrc_pair_params *params)
++{
++ enum asrc_pair_index index = params->index;
++ u32 size = asrc_get_output_FIFO_size(params->index);
++ int i, j;
++
++ /* Read all data in OUTPUT FIFO */
++ while (size) {
++ for (j = 0; j < size; j++)
++ for (i = 0; i < params->channel_nums; i++)
++ asrc_read_one_from_output_FIFO(index);
++ /* Fetch the data every 100us */
++ udelay(100);
++
++ size = asrc_get_output_FIFO_size(index);
++ }
++
++ /* Submit dma request */
++ dmaengine_submit(params->desc_in);
++ dma_async_issue_pending(params->desc_in->chan);
++
++ dmaengine_submit(params->desc_out);
++ dma_async_issue_pending(params->desc_out->chan);
++
++ /*
++ * Clear dma request during the stall state of ASRC:
++ * During STALL state, the remaining in input fifo would never be
++ * smaller than the input threshold while the output fifo would not
++ * be bigger than output one. Thus the dma request would be cleared.
++ */
++ asrc_set_watermark(index, ASRC_FIFO_THRESHOLD_MIN, ASRC_FIFO_THRESHOLD_MAX);
++
++ /* Update the real input threshold to raise dma request */
++ asrc_set_watermark(index, params->input_wm, params->output_wm);
++}
++#endif
++
++static long asrc_ioctl_req_pair(struct asrc_pair_params *params,
++ void __user *user)
++{
++ struct asrc_req req;
++ long ret;
++
++ ret = copy_from_user(&req, user, sizeof(req));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get req from user space: %ld\n", ret);
++ return ret;
++ }
++
++ ret = asrc_req_pair(req.chn_num, &req.index);
++ if (ret) {
++ dev_err(asrc->dev, "failed to request pair: %ld\n", ret);
++ return ret;
++ }
++
++ params->pair_hold = 1;
++ params->index = req.index;
++ params->channel_nums = req.chn_num;
++
++ ret = copy_to_user(user, &req, sizeof(req));
++ if (ret) {
++ dev_err(asrc->dev, "failed to send req to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl_config_pair(struct asrc_pair_params *params,
++ void __user *user)
++{
++ struct asrc_config config;
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&config, user, sizeof(config));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get config from user space: %ld\n", ret);
++ return ret;
++ }
++
++ index = config.pair;
++
++ ret = asrc_config_pair(&config);
++ if (ret) {
++ pair_err("failed to config pair: %ld\n", ret);
++ return ret;
++ }
++
++ params->input_wm = 4;
++ params->output_wm = 2;
++
++ ret = asrc_set_watermark(index, params->input_wm, params->output_wm);
++ if (ret)
++ return ret;
++
++ params->output_buffer_size = config.dma_buffer_size;
++ params->input_buffer_size = config.dma_buffer_size;
++ if (config.buffer_num > ASRC_DMA_BUFFER_NUM)
++ params->buffer_num = ASRC_DMA_BUFFER_NUM;
++ else
++ params->buffer_num = config.buffer_num;
++
++ params->input_dma_total.length = ASRC_DMA_BUFFER_SIZE;
++ params->output_dma_total.length = ASRC_DMA_BUFFER_SIZE;
++
++ params->input_word_width = config.input_word_width;
++ params->output_word_width = config.output_word_width;
++
++ params->input_sample_rate = config.input_sample_rate;
++ params->output_sample_rate = config.output_sample_rate;
++
++ params->last_period_sample = ASRC_OUTPUT_LAST_SAMPLE_DEFAULT;
++
++ ret = mxc_allocate_dma_buf(params);
++ if (ret) {
++ pair_err("failed to allocate dma buffer: %ld\n", ret);
++ return ret;
++ }
++
++ /* Request DMA channel for both input and output */
++ params->input_dma_channel = imx_asrc_get_dma_channel(index, true);
++ if (params->input_dma_channel == NULL) {
++ pair_err("failed to request input task dma channel\n");
++ return -EBUSY;
++ }
++
++ params->output_dma_channel = imx_asrc_get_dma_channel(index, false);
++ if (params->output_dma_channel == NULL) {
++ pair_err("failed to request output task dma channel\n");
++ return -EBUSY;
++ }
++
++ init_completion(&params->input_complete);
++ init_completion(&params->output_complete);
++ init_completion(&params->lastperiod_complete);
++
++ /* Add work struct to receive last period of output data */
++ INIT_WORK(&params->task_output_work, asrc_output_task_worker);
++
++ ret = copy_to_user(user, &config, sizeof(config));
++ if (ret) {
++ pair_err("failed to send config to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl_release_pair(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index;
++ unsigned long lock_flags;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ /* index might be not valid due to some application failure. */
++ if (index < 0)
++ return -EINVAL;
++
++ params->asrc_active = 0;
++
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ params->pair_hold = 0;
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++
++ if (params->input_dma_channel)
++ dma_release_channel(params->input_dma_channel);
++ if (params->output_dma_channel)
++ dma_release_channel(params->output_dma_channel);
++ mxc_free_dma_buf(params);
++ asrc_release_pair(index);
++ asrc_finish_conv(index);
++
++ return 0;
++}
++
++static long asrc_ioctl_convert(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index = params->index;
++ struct asrc_convert_buffer buf;
++ long ret;
++
++ ret = copy_from_user(&buf, user, sizeof(buf));
++ if (ret) {
++ pair_err("failed to get buf from user space: %ld\n", ret);
++ return ret;
++ }
++
++ ret = mxc_asrc_prepare_buffer(params, &buf);
++ if (ret) {
++ pair_err("failed to prepare buffer: %ld\n", ret);
++ return ret;
++ }
++
++#ifdef ASRC_POLLING_WITHOUT_DMA
++ asrc_polling_debug(params);
++#else
++ mxc_asrc_submit_dma(params);
++#endif
++
++ ret = mxc_asrc_process_buffer(params, &buf);
++ if (ret) {
++ pair_err("failed to process buffer: %ld\n", ret);
++ return ret;
++ }
++
++ ret = copy_to_user(user, &buf, sizeof(buf));
++ if (ret) {
++ pair_err("failed to send buf to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl_start_conv(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ params->asrc_active = 1;
++ asrc_start_conv(index);
++
++ return 0;
++}
++
++static long asrc_ioctl_stop_conv(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ dev_err(asrc->dev, "failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ dmaengine_terminate_all(params->input_dma_channel);
++ dmaengine_terminate_all(params->output_dma_channel);
++
++ asrc_stop_conv(index);
++ params->asrc_active = 0;
++
++ return 0;
++}
++
++static long asrc_ioctl_status(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index = params->index;
++ struct asrc_status_flags flags;
++ long ret;
++
++ ret = copy_from_user(&flags, user, sizeof(flags));
++ if (ret) {
++ pair_err("failed to get flags from user space: %ld\n", ret);
++ return ret;
++ }
++
++ asrc_get_status(&flags);
++
++ ret = copy_to_user(user, &flags, sizeof(flags));
++ if (ret) {
++ pair_err("failed to send flags to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl_flush(struct asrc_pair_params *params,
++ void __user *user)
++{
++ enum asrc_pair_index index = params->index;
++ init_completion(&params->input_complete);
++ init_completion(&params->output_complete);
++ init_completion(&params->lastperiod_complete);
++
++ /* Release DMA and request again */
++ dma_release_channel(params->input_dma_channel);
++ dma_release_channel(params->output_dma_channel);
++
++ params->input_dma_channel = imx_asrc_get_dma_channel(index, true);
++ if (params->input_dma_channel == NULL) {
++ pair_err("failed to request input task dma channel\n");
++ return -EBUSY;
++ }
++
++ params->output_dma_channel = imx_asrc_get_dma_channel(index, false);
++ if (params->output_dma_channel == NULL) {
++ pair_err("failed to request output task dma channel\n");
++ return -EBUSY;
++ }
++
++ return 0;
++}
++
++static long asrc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ struct asrc_pair_params *params = file->private_data;
++ void __user *user = (void __user *)arg;
++ long ret = 0;
++
++ switch (cmd) {
++ case ASRC_REQ_PAIR:
++ ret = asrc_ioctl_req_pair(params, user);
++ break;
++ case ASRC_CONFIG_PAIR:
++ ret = asrc_ioctl_config_pair(params, user);
++ break;
++ case ASRC_RELEASE_PAIR:
++ ret = asrc_ioctl_release_pair(params, user);
++ break;
++ case ASRC_CONVERT:
++ ret = asrc_ioctl_convert(params, user);
++ break;
++ case ASRC_START_CONV:
++ ret = asrc_ioctl_start_conv(params, user);
++ dump_regs();
++ break;
++ case ASRC_STOP_CONV:
++ ret = asrc_ioctl_stop_conv(params, user);
++ break;
++ case ASRC_STATUS:
++ ret = asrc_ioctl_status(params, user);
++ break;
++ case ASRC_FLUSH:
++ ret = asrc_ioctl_flush(params, user);
++ break;
++ default:
++ dev_err(asrc->dev, "invalid ioctl cmd!\n");
++ break;
++ }
++
++ return ret;
++}
++
++static int mxc_asrc_open(struct inode *inode, struct file *file)
++{
++ struct asrc_pair_params *params;
++ int ret = 0;
++
++ ret = signal_pending(current);
++ if (ret) {
++ dev_err(asrc->dev, "current process has a signal pending\n");
++ return ret;
++ }
++
++ params = kzalloc(sizeof(struct asrc_pair_params), GFP_KERNEL);
++ if (params == NULL) {
++ dev_err(asrc->dev, "failed to allocate pair_params\n");
++ return -ENOBUFS;
++ }
++
++ file->private_data = params;
++
++ return ret;
++}
++
++static int mxc_asrc_close(struct inode *inode, struct file *file)
++{
++ struct asrc_pair_params *params;
++ unsigned long lock_flags;
++
++ params = file->private_data;
++
++ if (!params)
++ return 0;
++
++ if (params->asrc_active) {
++ params->asrc_active = 0;
++
++ dmaengine_terminate_all(params->input_dma_channel);
++ dmaengine_terminate_all(params->output_dma_channel);
++
++ asrc_stop_conv(params->index);
++
++ complete(&params->input_complete);
++ complete(&params->output_complete);
++ complete(&params->lastperiod_complete);
++ }
++
++ if (params->pair_hold) {
++ spin_lock_irqsave(&pair_lock, lock_flags);
++ params->pair_hold = 0;
++ spin_unlock_irqrestore(&pair_lock, lock_flags);
++
++ if (params->input_dma_channel)
++ dma_release_channel(params->input_dma_channel);
++ if (params->output_dma_channel)
++ dma_release_channel(params->output_dma_channel);
++
++ mxc_free_dma_buf(params);
++
++ asrc_release_pair(params->index);
++ asrc_finish_conv(params->index);
++ }
++
++ kfree(params);
++ file->private_data = NULL;
++
++ return 0;
++}
++
++static int mxc_asrc_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ unsigned long size = vma->vm_end - vma->vm_start;
++ int ret;
++
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ size, vma->vm_page_prot);
++ if (ret) {
++ dev_err(asrc->dev, "failed to memory map!\n");
++ return ret;
++ }
++
++ vma->vm_flags &= ~VM_IO;
++
++ return ret;
++}
++
++static const struct file_operations asrc_fops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = asrc_ioctl,
++ .mmap = mxc_asrc_mmap,
++ .open = mxc_asrc_open,
++ .release = mxc_asrc_close,
++};
++
++static struct miscdevice asrc_miscdev = {
++ .name = "mxc_asrc",
++ .fops = &asrc_fops,
++ .minor = MISC_DYNAMIC_MINOR,
++};
++
++static int asrc_read_proc_attr(struct file *file, char __user *buf,
++ size_t count, loff_t *off)
++{
++ char tmpbuf[80];
++ int len = 0;
++ u32 reg;
++
++ if (*off)
++ return 0;
++
++ regmap_read(asrc->regmap, REG_ASRCNCR, &reg);
++
++ len += sprintf(tmpbuf, "ANCA: %d\nANCB: %d\nANCC: %d\n",
++ ASRCNCR_ANCx_get(ASRC_PAIR_A, reg, asrc->channel_bits),
++ ASRCNCR_ANCx_get(ASRC_PAIR_B, reg, asrc->channel_bits),
++ ASRCNCR_ANCx_get(ASRC_PAIR_C, reg, asrc->channel_bits));
++
++ if (len > count)
++ return 0;
++
++ if (copy_to_user(buf, &tmpbuf, len))
++ return -EFAULT;
++
++ *off += len;
++
++ return len;
++}
++
++#define ASRC_MAX_PROC_BUFFER_SIZE 63
++
++static int asrc_write_proc_attr(struct file *file, const char __user *buffer,
++ size_t count, loff_t *data)
++{
++ char buf[ASRC_MAX_PROC_BUFFER_SIZE];
++ int na, nb, nc;
++ int total;
++
++ if (count > ASRC_MAX_PROC_BUFFER_SIZE) {
++ dev_err(asrc->dev, "proc write: the input string was too long\n");
++ return -EINVAL;
++ }
++
++ if (copy_from_user(buf, buffer, count)) {
++ dev_err(asrc->dev, "proc write: failed to copy buffer from user\n");
++ return -EFAULT;
++ }
++
++ sscanf(buf, "ANCA: %d\nANCB: %d\nANCC: %d", &na, &nb, &nc);
++
++ total = asrc->channel_bits > 3 ? 10 : 5;
++
++ if (na + nb + nc > total) {
++ dev_err(asrc->dev, "don't surpass %d for total\n", total);
++ return -EINVAL;
++ } else if (na % 2 != 0 || nb % 2 != 0 || nc % 2 != 0) {
++ dev_err(asrc->dev, "please set an even number for each pair\n");
++ return -EINVAL;
++ } else if (na < 0 || nb < 0 || nc < 0) {
++ dev_err(asrc->dev, "please set an positive number for each pair\n");
++ return -EINVAL;
++ }
++
++
++ asrc->asrc_pair[ASRC_PAIR_A].chn_max = na;
++ asrc->asrc_pair[ASRC_PAIR_B].chn_max = nb;
++ asrc->asrc_pair[ASRC_PAIR_C].chn_max = nc;
++
++ /* Update channel number settings */
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_A, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_A, na, asrc->channel_bits));
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_B, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_B, nb, asrc->channel_bits));
++ regmap_update_bits(asrc->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCx_MASK(ASRC_PAIR_C, asrc->channel_bits),
++ ASRCNCR_ANCx_set(ASRC_PAIR_C, nc, asrc->channel_bits));
++
++ return count;
++}
++
++static const struct file_operations asrc_proc_fops = {
++ .read = asrc_read_proc_attr,
++ .write = asrc_write_proc_attr,
++};
++
++static void asrc_proc_create(void)
++{
++ struct proc_dir_entry *proc_attr;
++
++ asrc->proc_asrc = proc_mkdir(ASRC_PROC_PATH, NULL);
++ if (!asrc->proc_asrc) {
++ dev_err(asrc->dev, "failed to create proc entry %s\n", ASRC_PROC_PATH);
++ return;
++ }
++
++ proc_attr = proc_create("ChSettings", S_IFREG | S_IRUGO | S_IWUSR,
++ asrc->proc_asrc, &asrc_proc_fops);
++ if (!proc_attr) {
++ remove_proc_entry(ASRC_PROC_PATH, NULL);
++ dev_err(asrc->dev, "failed to create proc attribute entry\n");
++ }
++}
++
++static void asrc_proc_remove(void)
++{
++ remove_proc_entry("ChSettings", asrc->proc_asrc);
++ remove_proc_entry(ASRC_PROC_PATH, NULL);
++}
++
++
++static bool asrc_readable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ASRCTR:
++ case REG_ASRIER:
++ case REG_ASRCNCR:
++ case REG_ASRCFG:
++ case REG_ASRCSR:
++ case REG_ASRCDR1:
++ case REG_ASRCDR2:
++ case REG_ASRSTR:
++ case REG_ASRPM1:
++ case REG_ASRPM2:
++ case REG_ASRPM3:
++ case REG_ASRPM4:
++ case REG_ASRPM5:
++ case REG_ASRTFR1:
++ case REG_ASRCCR:
++ case REG_ASRDOA:
++ case REG_ASRDOB:
++ case REG_ASRDOC:
++ case REG_ASRIDRHA:
++ case REG_ASRIDRLA:
++ case REG_ASRIDRHB:
++ case REG_ASRIDRLB:
++ case REG_ASRIDRHC:
++ case REG_ASRIDRLC:
++ case REG_ASR76K:
++ case REG_ASR56K:
++ case REG_ASRMCRA:
++ case REG_ASRFSTA:
++ case REG_ASRMCRB:
++ case REG_ASRFSTB:
++ case REG_ASRMCRC:
++ case REG_ASRFSTC:
++ case REG_ASRMCR1A:
++ case REG_ASRMCR1B:
++ case REG_ASRMCR1C:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool asrc_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ASRCTR:
++ case REG_ASRIER:
++ case REG_ASRCNCR:
++ case REG_ASRCFG:
++ case REG_ASRCSR:
++ case REG_ASRCDR1:
++ case REG_ASRCDR2:
++ case REG_ASRSTR:
++ case REG_ASRPM1:
++ case REG_ASRPM2:
++ case REG_ASRPM3:
++ case REG_ASRPM4:
++ case REG_ASRPM5:
++ case REG_ASRTFR1:
++ case REG_ASRCCR:
++ case REG_ASRDIA:
++ case REG_ASRDIB:
++ case REG_ASRDIC:
++ case REG_ASRIDRHA:
++ case REG_ASRIDRLA:
++ case REG_ASRIDRHB:
++ case REG_ASRIDRLB:
++ case REG_ASRIDRHC:
++ case REG_ASRIDRLC:
++ case REG_ASR76K:
++ case REG_ASR56K:
++ case REG_ASRMCRA:
++ case REG_ASRMCRB:
++ case REG_ASRMCRC:
++ case REG_ASRMCR1A:
++ case REG_ASRMCR1B:
++ case REG_ASRMCR1C:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static struct regmap_config asrc_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++
++ .max_register = REG_ASRMCR1C,
++ .readable_reg = asrc_readable_reg,
++ .writeable_reg = asrc_writeable_reg,
++};
++
++static int mxc_asrc_probe(struct platform_device *pdev)
++{
++ const struct of_device_id *of_id = of_match_device(fsl_asrc_ids, &pdev->dev);
++ struct device_node *np = pdev->dev.of_node;
++ enum mxc_asrc_type devtype;
++ struct resource *res;
++ void __iomem *regs;
++ int ret;
++
++ /* Check if the device is existed */
++ if (!np)
++ return -ENODEV;
++
++ asrc = devm_kzalloc(&pdev->dev, sizeof(struct asrc_data), GFP_KERNEL);
++ if (!asrc)
++ return -ENOMEM;
++
++ if (of_id) {
++ const struct platform_device_id *id_entry = of_id->data;
++ devtype = id_entry->driver_data;
++ } else {
++ devtype = pdev->id_entry->driver_data;
++ }
++
++ asrc->dev = &pdev->dev;
++ asrc->dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ asrc->asrc_pair[ASRC_PAIR_A].chn_max = 2;
++ asrc->asrc_pair[ASRC_PAIR_B].chn_max = 6;
++ asrc->asrc_pair[ASRC_PAIR_C].chn_max = 2;
++ asrc->asrc_pair[ASRC_PAIR_A].overload_error = 0;
++ asrc->asrc_pair[ASRC_PAIR_B].overload_error = 0;
++ asrc->asrc_pair[ASRC_PAIR_C].overload_error = 0;
++
++ /* Map the address */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (IS_ERR(res)) {
++ dev_err(&pdev->dev, "could not determine device resources\n");
++ return PTR_ERR(res);
++ }
++
++ regs = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(regs)) {
++ dev_err(&pdev->dev, "could not map device resources\n");
++ return PTR_ERR(regs);
++ }
++ asrc->paddr = res->start;
++
++ /* Register regmap and let it prepare core clock */
++ asrc->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
++ "core", regs, &asrc_regmap_config);
++ if (IS_ERR(asrc->regmap)) {
++ dev_err(&pdev->dev, "regmap init failed\n");
++ return PTR_ERR(asrc->regmap);
++ }
++
++ asrc->irq = platform_get_irq(pdev, 0);
++ if (asrc->irq == NO_IRQ) {
++ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
++ return asrc->irq;
++ }
++
++ ret = devm_request_irq(&pdev->dev, asrc->irq, asrc_isr, 0, np->name, NULL);
++ if (ret) {
++ dev_err(&pdev->dev, "could not claim irq %u: %d\n", asrc->irq, ret);
++ return ret;
++ }
++
++ asrc->asrc_clk = devm_clk_get(&pdev->dev, "core");
++ if (IS_ERR(asrc->asrc_clk)) {
++ dev_err(&pdev->dev, "failed to get core clock\n");
++ return PTR_ERR(asrc->asrc_clk);
++ }
++
++ asrc->dma_clk = devm_clk_get(&pdev->dev, "dma");
++ if (IS_ERR(asrc->dma_clk)) {
++ dev_err(&pdev->dev, "failed to get dma script clock\n");
++ return PTR_ERR(asrc->dma_clk);
++ }
++
++ switch (devtype) {
++ case IMX35_ASRC:
++ asrc->channel_bits = 3;
++ input_clk_map = input_clk_map_v1;
++ output_clk_map = output_clk_map_v1;
++ break;
++ case IMX53_ASRC:
++ asrc->channel_bits = 4;
++ input_clk_map = input_clk_map_v2;
++ output_clk_map = output_clk_map_v2;
++ break;
++ default:
++ dev_err(&pdev->dev, "unsupported device type\n");
++ return -EINVAL;
++ }
++
++ ret = misc_register(&asrc_miscdev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register char device %d\n", ret);
++ return ret;
++ }
++
++ asrc_proc_create();
++
++ ret = mxc_init_asrc();
++ if (ret) {
++ dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
++ goto err_misc;
++ }
++
++ dev_info(&pdev->dev, "mxc_asrc registered\n");
++
++ return ret;
++
++err_misc:
++ misc_deregister(&asrc_miscdev);
++
++ return ret;
++}
++
++static int mxc_asrc_remove(struct platform_device *pdev)
++{
++ asrc_proc_remove();
++ misc_deregister(&asrc_miscdev);
++
++ return 0;
++}
++
++static struct platform_driver mxc_asrc_driver = {
++ .driver = {
++ .name = "mxc_asrc",
++ .of_match_table = fsl_asrc_ids,
++ },
++ .probe = mxc_asrc_probe,
++ .remove = mxc_asrc_remove,
++};
++
++module_platform_driver(mxc_asrc_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Asynchronous Sample Rate Converter");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:mxc_asrc");
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.c 2014-05-15 20:33:58.590018132 +0200
+@@ -0,0 +1,932 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_InitializeInfo
++**
++** Initialize architecture dependent command buffer information.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ /* Reset interrupts. */
++ Command->info.feBufferInt = -1;
++ Command->info.tsOverflowInt = -1;
++
++ /* Set command buffer attributes. */
++ Command->info.addressAlignment = 64;
++ Command->info.commandAlignment = 8;
++
++ /* Determine command alignment address mask. */
++ Command->info.addressMask = ((((gctUINT32) (Command->info.addressAlignment - 1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0 ) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Query the number of bytes needed by the STATE command. */
++ gcmkERR_BREAK(gckVGCOMMAND_StateCommand(
++ Command, 0x0, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.stateCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RESTART command. */
++ gcmkERR_BREAK(gckVGCOMMAND_RestartCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.restartCommandSize
++ ));
++
++ /* Query the number of bytes needed by the FETCH command. */
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.fetchCommandSize
++ ));
++
++ /* Query the number of bytes needed by the CALL command. */
++ gcmkERR_BREAK(gckVGCOMMAND_CallCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.callCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RETURN command. */
++ gcmkERR_BREAK(gckVGCOMMAND_ReturnCommand(
++ Command, gcvNULL,
++ &Command->info.returnCommandSize
++ ));
++
++ /* Query the number of bytes needed by the EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, gcvNULL, gcvBLOCK_PIXEL, -1,
++ &Command->info.eventCommandSize
++ ));
++
++ /* Query the number of bytes needed by the END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command, gcvNULL, -1,
++ &Command->info.endCommandSize
++ ));
++
++ /* Determine the tail reserve size. */
++ Command->info.staticTailSize = gcmMAX(
++ Command->info.fetchCommandSize,
++ gcmMAX(
++ Command->info.returnCommandSize,
++ Command->info.endCommandSize
++ )
++ );
++
++ /* Determine the maximum tail size. */
++ Command->info.dynamicTailSize
++ = Command->info.staticTailSize
++ + Command->info.eventCommandSize * gcvBLOCK_COUNT;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_StateCommand
++**
++** Append a STATE command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctUINT32 Pipe
++** Harwdare destination pipe.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** STATE command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 Address
++** Starting register address of the state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT32 Count
++** Number of states in state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the STATE command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the STATE command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Count,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Pipe=0x%x Logical=0x%x Address=0x%x Count=0x%x Bytes = 0x%x",
++ Command, Pipe, Logical, Address, Count, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) ((gctUINT32) (Pipe) & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LOAD_STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_RestartCommand
++**
++** Form a RESTART command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RESTART command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this RESTART
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this RESTART command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RESTART command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RESTART command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++ gctUINT32 beginEndMark;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Determine Begin/End flag. */
++ beginEndMark = (FetchCount > 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)));
++
++ /* Append RESTART. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x9 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)))
++ | beginEndMark;
++
++ buffer[1]
++ = FetchAddress;
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RESTART command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_FetchCommand
++**
++** Form a FETCH command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** FETCH command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this FETCH
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this FETCH command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the FETCH command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the FETCH command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append FETCH. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x5 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the FETCH command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LINK. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_CallCommand
++**
++** Append a CALL command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** CALL command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this CALL
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this CALL command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the CALL command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the CALL command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append CALL. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x6 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the CALL command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_ReturnCommand
++**
++** Append a RETURN command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RETURN command at or gcvNULL to query the size of the command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RETURN command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RETURN command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Bytes = 0x%x",
++ Command, Logical, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append RETURN. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x7 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RETURN command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EventCommand
++**
++** Form an EVENT command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** EVENT command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gceBLOCK Block
++** Block that will generate the interrupt.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Block=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, Block, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ typedef struct _gcsEVENTSTATES
++ {
++ /* Chips before VG21 use these values. */
++ gctUINT eventFromFE;
++ gctUINT eventFromPE;
++
++ /* VG21 chips and later use SOURCE field. */
++ gctUINT eventSource;
++ }
++ gcsEVENTSTATES;
++
++ static gcsEVENTSTATES states[] =
++ {
++ /* gcvBLOCK_COMMAND */
++ {
++ (gctUINT)~0,
++ (gctUINT)~0,
++ (gctUINT)~0
++ },
++
++ /* gcvBLOCK_TESSELLATOR */
++ {
++ 0x0,
++ 0x1,
++ 0x10
++ },
++
++ /* gcvBLOCK_TESSELLATOR2 */
++ {
++ 0x0,
++ 0x1,
++ 0x12
++ },
++
++ /* gcvBLOCK_TESSELLATOR3 */
++ {
++ 0x0,
++ 0x1,
++ 0x14
++ },
++
++ /* gcvBLOCK_RASTER */
++ {
++ 0x0,
++ 0x1,
++ 0x07,
++ },
++
++ /* gcvBLOCK_VG */
++ {
++ 0x0,
++ 0x1,
++ 0x0F
++ },
++
++ /* gcvBLOCK_VG2 */
++ {
++ 0x0,
++ 0x1,
++ 0x11
++ },
++
++ /* gcvBLOCK_VG3 */
++ {
++ 0x0,
++ 0x1,
++ 0x13
++ },
++
++ /* gcvBLOCK_PIXEL */
++ {
++ 0x0,
++ 0x1,
++ 0x07
++ },
++ };
++
++ /* Verify block ID. */
++ gcmkVERIFY_ARGUMENT(gcmIS_VALID_INDEX(Block, states));
++
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++
++ /* Determine chip version. */
++ if (Command->vg21)
++ {
++ /* Get the event source for the block. */
++ gctUINT eventSource = states[Block].eventSource;
++
++ /* Supported? */
++ if (eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) ((gctUINT32) (eventSource) & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++ else
++ {
++ /* Get the event source for the block. */
++ gctUINT eventFromFE = states[Block].eventFromFE;
++ gctUINT eventFromPE = states[Block].eventFromPE;
++
++ /* Supported? */
++ if (eventFromFE == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (eventFromFE) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (eventFromPE) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Make sure the events are directly supported for the block. */
++ if (states[Block].eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine event source. */
++ if (Block == gcvBLOCK_COMMAND)
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++ else
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EndCommand
++**
++** Form an END command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** END command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append END. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR memory;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ memory = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ memory[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ memory[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Append END. */
++ memory[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 16;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_command_vg.h 2014-05-15 20:33:58.590018132 +0200
+@@ -0,0 +1,319 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_command_vg_h_
++#define __gc_hal_kernel_hardware_command_vg_h_
++
++/******************************************************************************\
++******************* Task and Interrupt Management Structures. ******************
++\******************************************************************************/
++
++/* Task storage header. */
++typedef struct _gcsTASK_STORAGE * gcsTASK_STORAGE_PTR;
++typedef struct _gcsTASK_STORAGE
++{
++ /* Next allocated storage buffer. */
++ gcsTASK_STORAGE_PTR next;
++}
++gcsTASK_STORAGE;
++
++/* Task container header. */
++typedef struct _gcsTASK_CONTAINER * gcsTASK_CONTAINER_PTR;
++typedef struct _gcsTASK_CONTAINER
++{
++ /* The number of tasks left to be processed in the container. */
++ gctINT referenceCount;
++
++ /* Size of the buffer. */
++ gctUINT size;
++
++ /* Link to the previous and the next allocated containers. */
++ gcsTASK_CONTAINER_PTR allocPrev;
++ gcsTASK_CONTAINER_PTR allocNext;
++
++ /* Link to the previous and the next containers in the free list. */
++ gcsTASK_CONTAINER_PTR freePrev;
++ gcsTASK_CONTAINER_PTR freeNext;
++}
++gcsTASK_CONTAINER;
++
++/* Kernel space task master table entry. */
++typedef struct _gcsBLOCK_TASK_ENTRY * gcsBLOCK_TASK_ENTRY_PTR;
++typedef struct _gcsBLOCK_TASK_ENTRY
++{
++ /* Pointer to the current task container for the block. */
++ gcsTASK_CONTAINER_PTR container;
++
++ /* Pointer to the current task data within the container. */
++ gcsTASK_HEADER_PTR task;
++
++ /* Pointer to the last link task within the container. */
++ gcsTASK_LINK_PTR link;
++
++ /* Number of interrupts allocated for this block. */
++ gctUINT interruptCount;
++
++ /* The index of the current interrupt. */
++ gctUINT interruptIndex;
++
++ /* Interrupt semaphore. */
++ gctSEMAPHORE interruptSemaphore;
++
++ /* Interrupt value array. */
++ gctINT32 interruptArray[32];
++}
++gcsBLOCK_TASK_ENTRY;
++
++
++/******************************************************************************\
++********************* Command Queue Management Structures. *********************
++\******************************************************************************/
++
++/* Command queue kernel element pointer. */
++typedef struct _gcsKERNEL_CMDQUEUE * gcsKERNEL_CMDQUEUE_PTR;
++
++/* Command queue object handler function type. */
++typedef gceSTATUS (* gctOBJECT_HANDLER) (
++ gckVGKERNEL Kernel,
++ gcsKERNEL_CMDQUEUE_PTR Entry
++ );
++
++/* Command queue kernel element. */
++typedef struct _gcsKERNEL_CMDQUEUE
++{
++ /* The number of buffers in the queue. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Pointer to the object handler function. */
++ gctOBJECT_HANDLER handler;
++}
++gcsKERNEL_CMDQUEUE;
++
++/* Command queue header. */
++typedef struct _gcsKERNEL_QUEUE_HEADER * gcsKERNEL_QUEUE_HEADER_PTR;
++typedef struct _gcsKERNEL_QUEUE_HEADER
++{
++ /* The size of the buffer in bytes. */
++ gctUINT size;
++
++ /* The number of pending entries to be processed. */
++ volatile gctUINT pending;
++
++ /* The current command queue entry. */
++ gcsKERNEL_CMDQUEUE_PTR currentEntry;
++
++ /* Next buffer. */
++ gcsKERNEL_QUEUE_HEADER_PTR next;
++}
++gcsKERNEL_QUEUE_HEADER;
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++/* gckVGCOMMAND object. */
++struct _gckVGCOMMAND
++{
++ /***************************************************************************
++ ** Object data and pointers.
++ */
++
++ gcsOBJECT object;
++ gckVGKERNEL kernel;
++ gckOS os;
++ gckVGHARDWARE hardware;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++
++ /***************************************************************************
++ ** Enable command queue dumping.
++ */
++
++ gctBOOL enableDumping;
++
++
++ /***************************************************************************
++ ** Bus Error interrupt.
++ */
++
++ gctINT32 busErrorInt;
++
++
++ /***************************************************************************
++ ** Command buffer information.
++ */
++
++ gcsCOMMAND_BUFFER_INFO info;
++
++
++ /***************************************************************************
++ ** Synchronization objects.
++ */
++
++ gctPOINTER queueMutex;
++ gctPOINTER taskMutex;
++ gctPOINTER commitMutex;
++
++
++ /***************************************************************************
++ ** Task management.
++ */
++
++ /* The head of the storage buffer linked list. */
++ gcsTASK_STORAGE_PTR taskStorage;
++
++ /* Allocation size. */
++ gctUINT taskStorageGranularity;
++ gctUINT taskStorageUsable;
++
++ /* The free container list. */
++ gcsTASK_CONTAINER_PTR taskFreeHead;
++ gcsTASK_CONTAINER_PTR taskFreeTail;
++
++ /* Task table */
++ gcsBLOCK_TASK_ENTRY taskTable[gcvBLOCK_COUNT];
++
++
++ /***************************************************************************
++ ** Command queue.
++ */
++
++ /* Pointer to the allocated queue memory. */
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++
++ /* Pointer to the current available queue from which new queue entries
++ will be allocated. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* If different from queueHead, points to the command queue which is
++ currently being executed by the hardware. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++
++ /* Points to the queue to merge the tail with when the tail is processed. */
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++
++ /* Queue overflow counter. */
++ gctUINT queueOverflow;
++
++
++ /***************************************************************************
++ ** Context.
++ */
++
++ /* Context counter used for unique ID. */
++ gctUINT64 contextCounter;
++
++ /* Current context ID. */
++ gctUINT64 currentContext;
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++ gctINT32 powerStallInt;
++ gcsCMDBUFFER_PTR powerStallBuffer;
++ gctSIGNAL powerStallSignal;
++
++};
++
++/******************************************************************************\
++************************ gckVGCOMMAND Object Internal API. ***********************
++\******************************************************************************/
++
++/* Initialize architecture dependent command buffer information. */
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ );
++
++/* Form a STATE command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Count,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form a RESTART command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form a FETCH command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form a CALL command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form a RETURN command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form an EVENT command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Form an END command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++#endif /* __gc_hal_kernel_hardware_command_h_ */
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c 2014-05-15 20:33:58.590018132 +0200
+@@ -0,0 +1,2110 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++ gcvPOWER_FLAG_NOP = 1 << 11,
++}
++gcePOWER_FLAGS;
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_ResetGPU(
++ IN gckOS Os
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ /* Read register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00104,
++ 0x00000000));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32 * ChipFeatures,
++ OUT gctUINT32 * ChipMinorFeatures,
++ OUT gctUINT32 * ChipMinorFeatures2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 chipIdentity;
++
++ do
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG, 0x00018, &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ *ChipModel = gcv500;
++ *ChipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00020,
++ (gctUINT32 *) ChipModel));
++
++ /* Read CHIP_REV register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00024,
++ ChipRevision));
++ }
++
++ /* Read chip feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x0001C, ChipFeatures
++ ));
++
++ /* Read chip minor feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00034, ChipMinorFeatures
++ ));
++
++ /* Read chip minor feature register #2. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00074, ChipMinorFeatures2
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_VERBOSE,
++ "ChipModel=0x%08X\n"
++ "ChipRevision=0x%08X\n"
++ "ChipFeatures=0x%08X\n"
++ "ChipMinorFeatures=0x%08X\n"
++ "ChipMinorFeatures2=0x%08X\n",
++ *ChipModel,
++ *ChipRevision,
++ *ChipFeatures,
++ *ChipMinorFeatures,
++ *ChipMinorFeatures2
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_VGPowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckVGHARDWARE hardware = (gckVGHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++/******************************************************************************\
++****************************** gckVGHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Construct
++**
++** Construct a new gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** OUTPUT:
++**
++** gckVGHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckVGHARDWARE
++** object.
++*/
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ )
++{
++ gckVGHARDWARE hardware = gcvNULL;
++ gceSTATUS status;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x ", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ status = _ResetGPU(Os);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++ /* Identify the hardware. */
++ gcmkERR_BREAK(_IdentifyHardware(Os,
++ &chipModel, &chipRevision,
++ &chipFeatures, &chipMinorFeatures, &chipMinorFeatures2
++ ));
++
++ /* Allocate the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckVGHARDWARE), (gctPOINTER *) &hardware
++ ));
++
++ /* Initialize the gckVGHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++
++ /* Set chip identity. */
++ hardware->chipModel = chipModel;
++ hardware->chipRevision = chipRevision;
++ hardware->chipFeatures = chipFeatures;
++ hardware->chipMinorFeatures = chipMinorFeatures;
++ hardware->chipMinorFeatures2 = chipMinorFeatures2;
++
++ hardware->powerMutex = gcvNULL;
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->chipPowerStateGlobal = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++
++ hardware->powerOffTime = 0;
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _VGPowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ /* Determine whether FE 2.0 is present. */
++ hardware->fe20 = ((((gctUINT32) (hardware->chipFeatures)) >> (0 ? 28:28) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))));
++
++ /* Determine whether VG 2.0 is present. */
++ hardware->vg20 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 13:13) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))));
++
++ /* Determine whether VG 2.1 is present. */
++ hardware->vg21 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++
++ /* Set default event mask. */
++ hardware->eventMask = 0xFFFFFFFF;
++
++ gcmkERR_BREAK(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++
++ /* Set fast clear to auto. */
++ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(hardware, -1));
++
++ gcmkERR_BREAK(gckOS_CreateMutex(Os, &hardware->powerMutex));
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Return pointer to the gckVGHARDWARE object. */
++ *Hardware = hardware;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ if (hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ if (hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Free(Os, hardware));
++ }
++
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvFALSE, gcvFALSE));
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Destroy
++**
++** Destroy an gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ if (Hardware->powerMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(
++ Hardware->os, Hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ if (Hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++ }
++
++ /* Free the object. */
++ status = gckOS_Free(Hardware->os, Hardware);
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x InternalSize=0x%x InternalBaseAddress=0x%x InternalAlignment=0x%x"
++ "ExternalSize=0x%x ExternalBaseAddress=0x%x ExternalAlignment=0x%x HorizontalTileSize=0x%x VerticalTileSize=0x%x",
++ Hardware, InternalSize, InternalBaseAddress, InternalAlignment,
++ ExternalSize, ExternalBaseAddress, ExternalAlignment, HorizontalTileSize, VerticalTileSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gceCHIPMODEL * ChipModel
++** If 'ChipModel' is not gcvNULL, the variable it points to will
++** receive the model of the chip.
++**
++** gctUINT32 * ChipRevision
++** If 'ChipRevision' is not gcvNULL, the variable it points to will
++** receive the revision of the chip.
++**
++** gctUINT32 * ChipFeatures
++** If 'ChipFeatures' is not gcvNULL, the variable it points to will
++** receive the feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures
++** If 'ChipMinorFeatures' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures2
++** If 'ChipMinorFeatures2' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures2
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x ChipModel=0x%x ChipRevision=0x%x ChipFeatures = 0x%x ChipMinorFeatures = 0x%x ChipMinorFeatures2 = 0x%x",
++ Hardware, ChipModel, ChipRevision, ChipFeatures, ChipMinorFeatures, ChipMinorFeatures2);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Return chip model. */
++ if (ChipModel != gcvNULL)
++ {
++ *ChipModel = Hardware->chipModel;
++ }
++
++ /* Return revision number. */
++ if (ChipRevision != gcvNULL)
++ {
++ *ChipRevision = Hardware->chipRevision;
++ }
++
++ /* Return feature set. */
++ if (ChipFeatures != gcvNULL)
++ {
++ gctUINT32 features = Hardware->chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 since it did not have this *\
++ \* bit. */
++ if ((Hardware->chipModel == gcv500)
++ && (Hardware->chipRevision == 0)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ /* Mark 2D pipe as available for GC300 since it did not have this *\
++ \* bit. */
++ if (Hardware->chipModel == gcv300)
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ *ChipFeatures = features;
++ }
++
++ /* Return minor feature set. */
++ if (ChipMinorFeatures != gcvNULL)
++ {
++ *ChipMinorFeatures = Hardware->chipMinorFeatures;
++ }
++
++ /* Return minor feature set #2. */
++ if (ChipMinorFeatures2 != gcvNULL)
++ {
++ *ChipMinorFeatures2 = Hardware->chipMinorFeatures2;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertFormat
++**
++** Convert an API format to hardware parameters.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gceSURF_FORMAT Format
++** API format to convert.
++**
++** OUTPUT:
++**
++** gctUINT32 * BitsPerPixel
++** Pointer to a variable that will hold the number of bits per pixel.
++**
++** gctUINT32 * BytesPerTile
++** Pointer to a variable that will hold the number of bytes per tile.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ )
++{
++ gctUINT32 bitsPerPixel;
++ gctUINT32 bytesPerTile;
++
++ gcmkHEADER_ARG("Hardware=0x%x Format=0x%x BitsPerPixel=0x%x BytesPerTile = 0x%x",
++ Hardware, Format, BitsPerPixel, BytesPerTile);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Dispatch on format. */
++ switch (Format)
++ {
++ case gcvSURF_A1:
++ case gcvSURF_L1:
++ /* 1-bpp format. */
++ bitsPerPixel = 1;
++ bytesPerTile = (1 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_A4:
++ /* 4-bpp format. */
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_INDEX8:
++ case gcvSURF_A8:
++ case gcvSURF_L8:
++ /* 8-bpp format. */
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_YV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_NV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ /* 4444 variations. */
++ case gcvSURF_X4R4G4B4:
++ case gcvSURF_A4R4G4B4:
++ case gcvSURF_R4G4B4X4:
++ case gcvSURF_R4G4B4A4:
++ case gcvSURF_B4G4R4X4:
++ case gcvSURF_B4G4R4A4:
++ case gcvSURF_X4B4G4R4:
++ case gcvSURF_A4B4G4R4:
++
++ /* 1555 variations. */
++ case gcvSURF_X1R5G5B5:
++ case gcvSURF_A1R5G5B5:
++ case gcvSURF_R5G5B5X1:
++ case gcvSURF_R5G5B5A1:
++ case gcvSURF_X1B5G5R5:
++ case gcvSURF_A1B5G5R5:
++ case gcvSURF_B5G5R5X1:
++ case gcvSURF_B5G5R5A1:
++
++ /* 565 variations. */
++ case gcvSURF_R5G6B5:
++ case gcvSURF_B5G6R5:
++
++ case gcvSURF_A8L8:
++ case gcvSURF_YUY2:
++ case gcvSURF_UYVY:
++ case gcvSURF_D16:
++ /* 16-bpp format. */
++ bitsPerPixel = 16;
++ bytesPerTile = (16 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_X8R8G8B8:
++ case gcvSURF_A8R8G8B8:
++ case gcvSURF_X8B8G8R8:
++ case gcvSURF_A8B8G8R8:
++ case gcvSURF_R8G8B8X8:
++ case gcvSURF_R8G8B8A8:
++ case gcvSURF_B8G8R8X8:
++ case gcvSURF_B8G8R8A8:
++ case gcvSURF_D32:
++ /* 32-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_D24S8:
++ /* 24-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT1:
++ case gcvSURF_ETC1:
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT2:
++ case gcvSURF_DXT3:
++ case gcvSURF_DXT4:
++ case gcvSURF_DXT5:
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ default:
++ /* Invalid format. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Set the result. */
++ if (BitsPerPixel != gcvNULL)
++ {
++ * BitsPerPixel = bitsPerPixel;
++ }
++
++ if (BytesPerTile != gcvNULL)
++ {
++ * BytesPerTile = bytesPerTile;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Pool=0x%x Offset = 0x%x",
++ Hardware, Address, Pool, Offset);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 1:0)) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x2:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = ((((gctUINT32) (Address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address of the command buffer.
++**
++** gctSIZE_T Count
++** Number of command-sized data units to be executed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Count
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Count=0x%x",
++ Hardware, Address, Count);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ /* Enable all events. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00014,
++ Hardware->eventMask
++ ));
++
++ if (Hardware->fe20)
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00500,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00504,
++ Count
++ ));
++ }
++ else
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00654,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00658,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_AlignToTile
++**
++** Align the specified width and height to tile boundaries.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gceSURF_TYPE Type
++** Type of alignment.
++**
++** gctUINT32 * Width
++** Pointer to the width to be aligned. If 'Width' is gcvNULL, no width
++** will be aligned.
++**
++** gctUINT32 * Height
++** Pointer to the height to be aligned. If 'Height' is gcvNULL, no height
++** will be aligned.
++**
++** OUTPUT:
++**
++** gctUINT32 * Width
++** Pointer to a variable that will receive the aligned width.
++**
++** gctUINT32 * Height
++** Pointer to a variable that will receive the aligned height.
++*/
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32 * Width,
++ IN OUT gctUINT32 * Height
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Type=0x%x Width=0x%x Height=0x%x",
++ Hardware, Type, Width, Height);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Width != gcvNULL)
++ {
++ /* Align the width. */
++ *Width = gcmALIGN(*Width, (Type == gcvSURF_TEXTURE) ? 4 : 16);
++ }
++
++ if (Height != gcvNULL)
++ {
++ /* Special case for VG images. */
++ if ((*Height == 0) && (Type == gcvSURF_IMAGE))
++ {
++ *Height = 4;
++ }
++ else
++ {
++ /* Align the height. */
++ *Height = gcmALIGN(*Height, 4);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Address=0x%x",
++ Hardware, Logical, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ /* Convert logical address into a physical address. */
++ gcmkERR_BREAK(gckOS_GetPhysicalAddress(
++ Hardware->os, Logical, &address
++ ));
++
++ /* Return hardware specific address. */
++ *Address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x SystemSize=0x%x SystemBaseAddress=0x%x",
++ Hardware, SystemSize, SystemBaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = (gctSIZE_T)(1 << 31);
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x",
++ Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ do
++ {
++ /* Convert the logical address into an hardware address. */
++ gcmkERR_BREAK(gckVGHARDWARE_ConvertLogical(Hardware, Logical, &address) );
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00400,
++ gcmkFIXADDRESS(address)) );
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00404,
++ gcmkFIXADDRESS(address)) );
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00408,
++ gcmkFIXADDRESS(address)) );
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x0040C,
++ gcmkFIXADDRESS(address)) );
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00410,
++ gcmkFIXADDRESS(address)) );
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++ gctUINT32_PTR buffer;
++
++ /* Create a shortcut to the command buffer object. */
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &commandBuffer, (gctPOINTER *) &buffer
++ ));
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Hardware=0x%x Index=0x%x Offset=0x%x Address=0x%x",
++ Hardware, Index, Offset, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ address = (Index << 12) | Offset;
++
++ /* Set virtual type. */
++ address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Set the result. */
++ *Address = address;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x Data=0x%x", Hardware, Data);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ /* Read register and return. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, Data);
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ )
++{
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ if (!(((((gctUINT32) (Hardware->chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ return gcvSTATUS_OK;
++ }
++
++ do
++ {
++ if (Enable == -1)
++ {
++ Enable = (Hardware->chipModel > gcv500) ||
++ ((Hardware->chipModel == gcv500) && (Hardware->chipRevision >= 3));
++ }
++
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ &debug));
++
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++#ifdef AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION)));
++#endif
++
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ debug));
++
++ Hardware->allowFastClear = Enable;
++
++ status = gcvFALSE;
++ }
++ while (gcvFALSE);
++
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x IDs=0x%x", Hardware, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IDs != gcvNULL);
++
++ /* Read AQIntrAcknowledge register. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00010,
++ IDs);
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS _CommandStall(
++ gckVGHARDWARE Hardware)
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gctUINT32_PTR buffer;
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &command->powerStallBuffer,
++ (gctPOINTER *) &buffer
++ ));
++
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ command, buffer, gcvBLOCK_PIXEL,
++ command->powerStallInt, gcvNULL));
++
++ gcmkERR_BREAK(gckVGCOMMAND_Execute(
++ command,
++ command->powerStallBuffer
++ ));
++
++ /* Wait the signal. */
++ gcmkERR_BREAK(gckOS_WaitSignal(
++ command->os,
++ command->powerStallSignal,
++ gcdGPU_TIMEOUT));
++
++
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag/*, clock*/;
++
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL commitMutex = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++
++ gctBOOL broadcast = gcvFALSE;
++ gctUINT32 process, thread;
++ gctBOOL global = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_NOP,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_NOP,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d",
++ State);
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->powerManagement == gcvFALSE)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ /* Acquire the power mutex. */
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 0);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State == gcvPOWER_IDLE)
++ {
++ /* gcvPOWER_IDLE_BROADCAST is from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ /*clock = clocks[State];*/
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* internal power control */
++ if (!global)
++ {
++ if (Hardware->chipPowerStateGlobal == gcvPOWER_OFF)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os,
++ command->commitMutex,
++ gcvINFINITE
++ ));
++
++ commitMutex = gcvTRUE;
++
++ gcmkONERROR(_CommandStall(Hardware));
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++
++ acquired = gcvTRUE;
++ }
++
++ if (flag & gcvPOWER_FLAG_STOP)
++ {
++ }
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++ /* Only process this when hardware is enabled. */
++ if (Hardware->clockState && Hardware->powerState)
++ {
++ }
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++ gcmkONERROR(gckVGHARDWARE_SetMMU(Hardware, Hardware->kernel->mmu->pageTableLogical));
++
++ /* Force the command queue to reload the next context. */
++ command->currentContext = 0;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ gcvCORE_VG,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++ if (flag & gcvPOWER_FLAG_START)
++ {
++ }
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++ if (global)
++ {
++ /* Save the new power state. */
++ Hardware->chipPowerStateGlobal = State;
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ /* Reset power off time */
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++
++ if (State == gcvPOWER_IDLE)
++ {
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagement = PowerManagement;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ *IsIdle = gcvTRUE;
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, &idle));
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 8:8)) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 10:10)) & ((gctUINT32) ((((1 ? 10:10) - (0 ? 10:10) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 10:10) - (0 ? 10:10) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ *IsIdle = gcvFALSE;
++ }
++
++ else
++ {
++ *IsIdle = gcvTRUE;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.h 2014-05-15 20:33:58.590018132 +0200
+@@ -0,0 +1,75 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_vg_h_
++#define __gc_hal_kernel_hardware_vg_h_
++
++/* gckHARDWARE object. */
++struct _gckVGHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckKERNEL object. */
++ gckVGKERNEL kernel;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Chip characteristics. */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++ gctBOOL allowFastClear;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++ /* Event mask. */
++ gctUINT32 eventMask;
++
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gceCHIPPOWERSTATE chipPowerStateGlobal;
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++ gctPOINTER pageTableDirty;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++ gctBOOL powerManagement;
++};
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c 2014-05-15 20:33:58.590018132 +0200
+@@ -0,0 +1,1735 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_context.h"
++#include "gc_hal_kernel_buffer.h"
++
++/******************************************************************************\
++******************************** Debugging Macro *******************************
++\******************************************************************************/
++
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++
++/******************************************************************************\
++************************** Context State Buffer Helpers ************************
++\******************************************************************************/
++
++#define _STATE(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT(reg, count) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT_OFFSET(reg, offset, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + offset, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_MIRROR_COUNT(reg, mirror, count) \
++ _StateMirror(\
++ Context, \
++ reg ## _Address >> 2, \
++ count, \
++ mirror ## _Address >> 2 \
++ )
++
++#define _STATE_HINT(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_HINT_BLOCK(reg, block, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + (block << reg ## _BLK), \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_X(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvTRUE, gcvFALSE \
++ )
++
++#define _CLOSE_RANGE() \
++ _TerminateStateBlock(Context, index)
++
++#define _ENABLE(reg, field) \
++ do \
++ { \
++ if (gcmVERIFYFIELDVALUE(data, reg, MASK_ ## field, ENABLED)) \
++ { \
++ enable |= gcmFIELDMASK(reg, field); \
++ } \
++ } \
++ while (gcvFALSE)
++
++#define _BLOCK_COUNT(reg) \
++ ((reg ## _Count) >> (reg ## _BLK))
++
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++#define gcdSTATE_MASK \
++ (((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 | 0xC0FFEE & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))))
++
++#if !defined(VIVANTE_NO_3D)
++static gctSIZE_T
++_TerminateStateBlock(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index
++ )
++{
++ gctUINT32_PTR buffer;
++ gctSIZE_T align;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ /* Flush the current state block; make sure no pairing with the states
++ to follow happens. */
++ if (align && (buffer != gcvNULL))
++ {
++ buffer[Index] = 0xDEADDEAD;
++ }
++
++ /* Reset last address. */
++ Context->lastAddress = ~0U;
++
++ /* Return alignment requirement. */
++ return align;
++}
++#endif
++
++
++static gctSIZE_T
++_FlushPipe(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Flush the current pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ /* Flushing 3D pipe takes 6 slots. */
++ return 6;
++}
++
++#if !defined(VIVANTE_NO_3D)
++static gctSIZE_T
++_SemaphoreStall(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ /* Semaphore/stall takes 4 slots. */
++ return 4;
++}
++#endif
++
++static gctSIZE_T
++_SwitchPipe(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer
++ = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++ }
++
++ return 2;
++}
++
++#if !defined(VIVANTE_NO_3D)
++static gctSIZE_T
++_State(
++ IN gckCONTEXT Context,
++ IN gctSIZE_T Index,
++ IN gctUINT32 Address,
++ IN gctUINT32 Value,
++ IN gctSIZE_T Size,
++ IN gctBOOL FixedPoint,
++ IN gctBOOL Hinted
++ )
++{
++ gctUINT32_PTR buffer;
++ gctSIZE_T align, i;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ if ((buffer == gcvNULL) && (Address + Size > Context->stateCount))
++ {
++ /* Determine maximum state. */
++ Context->stateCount = Address + Size;
++ }
++
++ /* Do we need a new entry? */
++ if ((Address != Context->lastAddress) || (FixedPoint != Context->lastFixed))
++ {
++ if (buffer != gcvNULL)
++ {
++ if (align)
++ {
++ /* Add filler. */
++ buffer[Index++] = 0xDEADDEAD;
++ }
++
++ /* LoadState(Address, Count). */
++ gcmkASSERT((Index & 1) == 0);
++
++ if (FixedPoint)
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++ else
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ /* Walk all the states. */
++ for (i = 0; i < Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + 1 + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = Index + 1 + i;
++
++#if gcdSECURE_USER
++ /* Save hint. */
++ if (Context->hint != gcvNULL)
++ {
++ Context->hint[Address + i] = Hinted;
++ }
++#endif
++ }
++ }
++
++ /* Save information for this LoadState. */
++ Context->lastIndex = Index;
++ Context->lastAddress = Address + Size;
++ Context->lastSize = Size;
++ Context->lastFixed = FixedPoint;
++
++ /* Return size for load state. */
++ return align + 1 + Size;
++ }
++
++ /* Append this state to the previous one. */
++ if (buffer != gcvNULL)
++ {
++ /* Update last load state. */
++ buffer[Context->lastIndex] =
++ ((((gctUINT32) (buffer[Context->lastIndex])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Context->lastSize + Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Walk all the states. */
++ for (i = 0; i < Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = Index + i;
++
++#if gcdSECURE_USER
++ /* Save hint. */
++ if (Context->hint != gcvNULL)
++ {
++ Context->hint[Address + i] = Hinted;
++ }
++#endif
++ }
++ }
++
++ /* Update last address and size. */
++ Context->lastAddress += Size;
++ Context->lastSize += Size;
++
++ /* Return number of slots required. */
++ return Size;
++}
++
++static gctSIZE_T
++_StateMirror(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Size,
++ IN gctUINT32 AddressMirror
++ )
++{
++ gctSIZE_T i;
++
++ /* Process when buffer is set. */
++ if (Context->buffer != gcvNULL)
++ {
++ /* Walk all states. */
++ for (i = 0; i < Size; i++)
++ {
++ /* Copy the mapping address. */
++ Context->map[Address + i].index =
++ Context->map[AddressMirror + i].index;
++ }
++ }
++
++ /* Return the number of required maps. */
++ return Size;
++}
++#endif
++
++static gceSTATUS
++_InitializeContextBuffer(
++ IN gckCONTEXT Context
++ )
++{
++ gctUINT32_PTR buffer;
++ gctSIZE_T index;
++
++#if !defined(VIVANTE_NO_3D)
++ gctUINT i;
++ gctUINT vertexUniforms, fragmentUniforms;
++ gctUINT fe2vsCount;
++ gctBOOL halti0;
++#endif
++
++ /* Reset the buffer index. */
++ index = 0;
++
++ /* Reset the last state address. */
++ Context->lastAddress = ~0U;
++
++ /* Get the buffer pointer. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++
++ /**************************************************************************/
++ /* Build 2D states. *******************************************************/
++
++
++#if !defined(VIVANTE_NO_3D)
++ /**************************************************************************/
++ /* Build 3D states. *******************************************************/
++ halti0 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) );
++
++ /* Query shader support. */
++ gcmkVERIFY_OK(gckHARDWARE_QueryShaderCaps(
++ Context->hardware, &vertexUniforms, &fragmentUniforms, gcvNULL));
++
++ /* Store the 3D entry index. */
++ Context->entryOffset3D = index * gcmSIZEOF(gctUINT32);
++
++ /* Flush 2D pipe. */
++ index += _FlushPipe(Context, index, gcvPIPE_2D);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Current context pointer. */
++#if gcdDEBUG
++ index += _State(Context, index, 0x03850 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++
++ index += _FlushPipe(Context, index, gcvPIPE_3D);
++
++ /* Global states. */
++ index += _State(Context, index, 0x03814 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03818 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0381C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03820 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03828 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0382C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03834 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0384C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Front End states. */
++ fe2vsCount = 12;
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) ))
++ {
++ fe2vsCount = 16;
++ }
++ index += _State(Context, index, 0x00600 >> 2, 0x00000000, fe2vsCount, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x00644 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00648 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0064C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00650 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00680 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x006A0 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0067C >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x006C0 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00700 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00740 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00780 >> 2, 0x3F800000, 16, gcvFALSE, gcvFALSE);
++
++ /* Vertex Shader states. */
++ index += _State(Context, index, 0x00800 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00804 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00808 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0080C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00810 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00820 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00830 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ if (Context->hardware->identity.instructionCount <= 256)
++ {
++ index += _State(Context, index, 0x04000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x05000 >> 2, 0x00000000, vertexUniforms * 4, gcvFALSE, gcvFALSE);
++
++ /* Primitive Assembly states. */
++ index += _State(Context, index, 0x00A00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A08 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A0C >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A10 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A1C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A28 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A2C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A30 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A40 >> 2, 0x00000000, 10, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A34 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A38 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A3C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A80 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A84 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A8C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Setup states. */
++ index += _State(Context, index, 0x00C00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C08 >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C0C >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C10 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C1C >> 2, 0x42000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C20 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C24 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++
++ /* Raster states. */
++ index += _State(Context, index, 0x00E00 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E10 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E04 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E40 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E08 >> 2, 0x00000031, 1, gcvFALSE, gcvFALSE);
++
++ /* Pixel Shader states. */
++ index += _State(Context, index, 0x01000 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01004 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0100C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01010 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01018 >> 2, 0x01000000, 1, gcvFALSE, gcvFALSE);
++ if (Context->hardware->identity.instructionCount <= 256)
++ {
++ index += _State(Context, index, 0x06000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x07000 >> 2, 0x00000000, fragmentUniforms * 4, gcvFALSE, gcvFALSE);
++
++ /* Texture states. */
++ index += _State(Context, index, 0x02000 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02040 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02080 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x020C0 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02100 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02140 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02180 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x021C0 >> 2, 0x00321000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02200 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02240 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x02400 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02440 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02480 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x024C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02500 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02540 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02580 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x025C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02600 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02640 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02680 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x026C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02700 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02740 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ))
++ {
++ gctUINT texBlockCount;
++
++ /* New texture block. */
++ index += _State(Context, index, 0x10000 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10080 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10100 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10180 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10200 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10280 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ for (i = 0; i < 256 / 16; i += 1)
++ {
++ index += _State(Context, index, (0x02C00 >> 2) + i * 16, 0x00000000, 14, gcvFALSE, gcvFALSE);
++ }
++ index += _State(Context, index, 0x10300 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10380 >> 2, 0x00321000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10400 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10480 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 15:15)) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) ))
++ {
++ index += _State(Context, index, 0x12000 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x12400 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ }
++
++ if ((Context->hardware->identity.chipModel == gcv2000)
++ && (Context->hardware->identity.chipRevision == 0x5108))
++ {
++ texBlockCount = 12;
++ }
++ else
++ {
++ texBlockCount = ((512) >> (4));
++ }
++ for (i = 0; i < texBlockCount; i += 1)
++ {
++ index += _State(Context, index, (0x10800 >> 2) + (i << 4), 0x00000000, 14, gcvFALSE, gcvTRUE);
++ }
++ }
++
++ /* YUV. */
++ index += _State(Context, index, 0x01678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0167C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01680 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01684 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01688 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0168C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01690 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01694 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01698 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0169C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* Thread walker states. */
++ index += _State(Context, index, 0x00900 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00904 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00908 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0090C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00910 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00914 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00918 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0091C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00924 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if (Context->hardware->identity.instructionCount > 1024)
++ {
++ /* New Shader instruction memory. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00860 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x20000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++ }
++ else if (Context->hardware->identity.instructionCount > 256)
++ {
++ /* New Shader instruction memory. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* VX instruction memory. */
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x0C000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ _StateMirror(Context, 0x08000 >> 2, Context->hardware->identity.instructionCount << 2 , 0x0C000 >> 2);
++ }
++
++ /* Store the index of the "XD" entry. */
++ Context->entryOffsetXDFrom3D = index * gcmSIZEOF(gctUINT32);
++
++
++ /* Pixel Engine states. */
++ index += _State(Context, index, 0x01400 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01404 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01408 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0140C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01414 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01418 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0141C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01420 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01424 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01428 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0142C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01434 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01454 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01458 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0145C >> 2, 0x00000010, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A8 >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014AC >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A4 >> 2, 0x000E400C, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01580 >> 2, 0x00000000, 3, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Composition states. */
++ index += _State(Context, index, 0x03008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (Context->hardware->identity.pixelPipes == 1)
++ {
++ index += _State(Context, index, 0x01460 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01430 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01410 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ }
++ else
++ {
++ index += _State(Context, index, (0x01460 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ for (i = 0; i < 2; i++)
++ {
++ index += _State(Context, index, (0x01500 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++ }
++
++ if (Context->hardware->identity.pixelPipes > 1 || halti0)
++ {
++ index += _State(Context, index, (0x01480 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ /* Resolve states. */
++ index += _State(Context, index, 0x01604 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01608 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0160C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01610 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01614 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01620 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01630 >> 2, 0x00000000, 2, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01640 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0163C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if (Context->hardware->identity.pixelPipes > 1)
++ {
++ index += _State(Context, index, (0x016C0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, (0x016E0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01700 >> 2, 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvFALSE);
++ }
++
++ /* Tile status. */
++ index += _State(Context, index, 0x01654 >> 2, 0x00200000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x01658 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0165C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01660 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01664 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01668 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0166C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A4 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x016AC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01720 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01740 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01760 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* Semaphore/stall. */
++ index += _SemaphoreStall(Context, index);
++#endif
++
++ /**************************************************************************/
++ /* Link to another address. ***********************************************/
++
++ Context->linkIndex3D = index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++ /* Store the end of the context buffer. */
++ Context->bufferSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /**************************************************************************/
++ /* Pipe switch for the case where neither 2D nor 3D are used. *************/
++
++ /* Store the 3D entry index. */
++ Context->entryOffsetXDFrom2D = index * gcmSIZEOF(gctUINT32);
++
++ /* Flush 2D pipe. */
++ index += _FlushPipe(Context, index, gcvPIPE_2D);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Store the location of the link. */
++ Context->linkIndexXD = index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++
++ /**************************************************************************/
++ /* Save size for buffer. **************************************************/
++
++ Context->totalSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_DestroyContext(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ if (Context != gcvNULL)
++ {
++ gcsCONTEXT_PTR bufferHead;
++
++ /* Free context buffers. */
++ for (bufferHead = Context->buffer; Context->buffer != gcvNULL;)
++ {
++ /* Get a shortcut to the current buffer. */
++ gcsCONTEXT_PTR buffer = Context->buffer;
++
++ /* Get the next buffer. */
++ gcsCONTEXT_PTR next = buffer->next;
++
++ /* Last item? */
++ if (next == bufferHead)
++ {
++ next = gcvNULL;
++ }
++
++ /* Destroy the signal. */
++ if (buffer->signal != gcvNULL)
++ {
++ gcmkONERROR(gckOS_DestroySignal(
++ Context->os, buffer->signal
++ ));
++
++ buffer->signal = gcvNULL;
++ }
++
++ /* Free state delta map. */
++ if (buffer->logical != gcvNULL)
++ {
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gcmkONERROR(gckEVENT_DestroyVirtualCommandBuffer(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++
++#else
++ gcmkONERROR(gckEVENT_FreeContiguousMemory(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++#endif
++
++ buffer->logical = gcvNULL;
++ }
++
++ /* Free context buffer. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, buffer));
++
++ /* Remove from the list. */
++ Context->buffer = next;
++ }
++
++#if gcdSECURE_USER
++ /* Free the hint array. */
++ if (Context->hint != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->hint));
++ }
++#endif
++ /* Free record array copy. */
++ if (Context->recordArray != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArray));
++ }
++
++ /* Free the state mapping. */
++ if (Context->map != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->map));
++ }
++
++ /* Mark the gckCONTEXT object as unknown. */
++ Context->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCONTEXT object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context));
++ }
++
++OnError:
++ return status;
++}
++
++
++/******************************************************************************\
++**************************** Context Management API ****************************
++\******************************************************************************/
++
++/******************************************************************************\
++**
++** gckCONTEXT_Construct
++**
++** Construct a new gckCONTEXT object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gckHARDWARE Hardware
++** Pointer to gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable thet will receive the gckCONTEXT object
++** pointer.
++*/
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ )
++{
++ gceSTATUS status;
++ gckCONTEXT context = gcvNULL;
++ gctSIZE_T allocationSize;
++ gctUINT i;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%08X Hardware=0x%08X", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++
++
++ /**************************************************************************/
++ /* Allocate and initialize basic fields of gckCONTEXT. ********************/
++
++ /* The context object size. */
++ allocationSize = gcmSIZEOF(struct _gckCONTEXT);
++
++ /* Allocate the object. */
++ gcmkONERROR(gckOS_Allocate(
++ Os, allocationSize, &pointer
++ ));
++
++ context = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(context, allocationSize));
++
++ /* Initialize the gckCONTEXT object. */
++ context->object.type = gcvOBJ_CONTEXT;
++ context->os = Os;
++ context->hardware = Hardware;
++
++
++#if defined(VIVANTE_NO_3D)
++ context->entryPipe = gcvPIPE_2D;
++ context->exitPipe = gcvPIPE_2D;
++#elif gcdCMD_NO_2D_CONTEXT
++ context->entryPipe = gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#else
++ context->entryPipe
++ = (((((gctUINT32) (context->hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) )
++ ? gcvPIPE_2D
++ : gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#endif
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Hardware,
++ &context->alignment,
++ &context->reservedHead,
++ &context->reservedTail
++ ));
++
++ /* Mark the context as dirty to force loading of the entire state table
++ the first time. */
++ context->dirty = gcvTRUE;
++
++
++ /**************************************************************************/
++ /* Get the size of the context buffer. ************************************/
++
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++
++ /**************************************************************************/
++ /* Compute the size of the record array. **********************************/
++
++ context->recordArraySize
++ = gcmSIZEOF(gcsSTATE_DELTA_RECORD) * context->stateCount;
++
++
++ if (context->stateCount > 0)
++ {
++ /**************************************************************************/
++ /* Allocate and reset the state mapping table. ****************************/
++
++ /* Allocate the state mapping table. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsSTATE_MAP) * context->stateCount,
++ &pointer
++ ));
++
++ context->map = pointer;
++
++ /* Zero the state mapping table. */
++ gcmkONERROR(gckOS_ZeroMemory(
++ context->map, gcmSIZEOF(gcsSTATE_MAP) * context->stateCount
++ ));
++
++
++ /**************************************************************************/
++ /* Allocate the hint array. ***********************************************/
++
++#if gcdSECURE_USER
++ /* Allocate hints. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gctBOOL) * context->stateCount,
++ &pointer
++ ));
++
++ context->hint = pointer;
++#endif
++ }
++
++ /**************************************************************************/
++ /* Allocate the context and state delta buffers. **************************/
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i += 1)
++ {
++ /* Allocate a context buffer. */
++ gcsCONTEXT_PTR buffer;
++
++ /* Allocate the context buffer structure. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsCONTEXT),
++ &pointer
++ ));
++
++ buffer = pointer;
++
++ /* Reset the context buffer structure. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ buffer, gcmSIZEOF(gcsCONTEXT)
++ ));
++
++ /* Append to the list. */
++ if (context->buffer == gcvNULL)
++ {
++ buffer->next = buffer;
++ context->buffer = buffer;
++ }
++ else
++ {
++ buffer->next = context->buffer->next;
++ context->buffer->next = buffer;
++ }
++
++ /* Set the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ buffer->num = i;
++#endif
++
++ /* Create the busy signal. */
++ gcmkONERROR(gckOS_CreateSignal(
++ Os, gcvFALSE, &buffer->signal
++ ));
++
++ /* Set the signal, buffer is currently not busy. */
++ gcmkONERROR(gckOS_Signal(
++ Os, buffer->signal, gcvTRUE
++ ));
++
++ /* Create a new physical context buffer. */
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gcmkONERROR(gckKERNEL_AllocateVirtualCommandBuffer(
++ context->hardware->kernel,
++ gcvFALSE,
++ &context->totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++
++#else
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Os,
++ gcvFALSE,
++ &context->totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++#endif
++
++ buffer->logical = pointer;
++
++ /* Set gckEVENT object pointer. */
++ buffer->eventObj = Hardware->kernel->eventObj;
++
++ /* Set the pointers to the LINK commands. */
++ if (context->linkIndex2D != 0)
++ {
++ buffer->link2D = &buffer->logical[context->linkIndex2D];
++ }
++
++ if (context->linkIndex3D != 0)
++ {
++ buffer->link3D = &buffer->logical[context->linkIndex3D];
++ }
++
++ if (context->linkIndexXD != 0)
++ {
++ gctPOINTER xdLink;
++ gctUINT8_PTR xdEntryLogical;
++ gctSIZE_T xdEntrySize;
++ gctSIZE_T linkBytes;
++
++ /* Determine LINK parameters. */
++ xdLink
++ = &buffer->logical[context->linkIndexXD];
++
++ xdEntryLogical
++ = (gctUINT8_PTR) buffer->logical
++ + context->entryOffsetXDFrom3D;
++
++ xdEntrySize
++ = context->bufferSize
++ - context->entryOffsetXDFrom3D;
++
++ /* Query LINK size. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware, gcvNULL, gcvNULL, 0, &linkBytes
++ ));
++
++ /* Generate a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware,
++ xdLink,
++ xdEntryLogical,
++ xdEntrySize,
++ &linkBytes
++ ));
++ }
++ }
++
++
++ /**************************************************************************/
++ /* Initialize the context buffers. ****************************************/
++
++ /* Initialize the current context buffer. */
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++ /* Make all created contexts equal. */
++ {
++ gcsCONTEXT_PTR currContext, tempContext;
++
++ /* Set the current context buffer. */
++ currContext = context->buffer;
++
++ /* Get the next context buffer. */
++ tempContext = currContext->next;
++
++ /* Loop through all buffers. */
++ while (tempContext != currContext)
++ {
++ if (tempContext == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ /* Copy the current context. */
++ gckOS_MemCopy(
++ tempContext->logical,
++ currContext->logical,
++ context->totalSize
++ );
++
++ /* Get the next context buffer. */
++ tempContext = tempContext->next;
++ }
++ }
++
++ /* Return pointer to the gckCONTEXT object. */
++ *Context = context;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%08X", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back on error. */
++ gcmkVERIFY_OK(_DestroyContext(context));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/******************************************************************************\
++**
++** gckCONTEXT_Destroy
++**
++** Destroy a gckCONTEXT object.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Context=0x%08X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Destroy the context and all related objects. */
++ status = _DestroyContext(Context);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/******************************************************************************\
++**
++** gckCONTEXT_Update
++**
++** Merge all pending state delta buffers into the current context buffer.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ )
++{
++#ifndef VIVANTE_NO_3D
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSTATE_DELTA _stateDelta;
++ gckKERNEL kernel;
++ gcsCONTEXT_PTR buffer;
++ gcsSTATE_MAP_PTR map;
++ gctBOOL needCopy = gcvFALSE;
++ gcsSTATE_DELTA_PTR nDelta;
++ gcsSTATE_DELTA_PTR uDelta = gcvNULL;
++ gcsSTATE_DELTA_PTR kDelta = gcvNULL;
++ gcsSTATE_DELTA_RECORD_PTR record;
++ gcsSTATE_DELTA_RECORD_PTR recordArray = gcvNULL;
++ gctUINT elementCount;
++ gctUINT address;
++ gctUINT32 mask;
++ gctUINT32 data;
++ gctUINT index;
++ gctUINT i, j;
++
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++
++ gcmkHEADER_ARG(
++ "Context=0x%08X ProcessID=%d StateDelta=0x%08X",
++ Context, ProcessID, StateDelta
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Get a shortcut to the kernel object. */
++ kernel = Context->hardware->kernel;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Context->os, ProcessID, &needCopy));
++
++ /* Allocate the copy buffer for the user record array. */
++ if (needCopy && (Context->recordArray == gcvNULL))
++ {
++ /* Allocate the buffer. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ Context->recordArraySize,
++ (gctPOINTER *) &Context->recordArray
++ ));
++ }
++
++ /* Get the current context buffer. */
++ buffer = Context->buffer;
++
++ /* Wait until the context buffer becomes available; this will
++ also reset the signal and mark the buffer as busy. */
++ gcmkONERROR(gckOS_WaitSignal(
++ Context->os, buffer->signal, gcvINFINITE
++ ));
++
++#if gcdSECURE_USER
++ /* Get the cache form the database. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(kernel, ProcessID, &cache));
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE) && 1 && !defined(VIVANTE_NO_3D)
++ /* Update current context token. */
++ buffer->logical[Context->map[0x0E14].index]
++ = gcmPTR2INT(Context);
++#endif
++
++ /* Are there any pending deltas? */
++ if (buffer->deltaCount != 0)
++ {
++ /* Get the state map. */
++ map = Context->map;
++
++ /* Get the first delta item. */
++ uDelta = buffer->delta;
++
++ /* Reset the vertex stream count. */
++ elementCount = 0;
++
++ /* Merge all pending deltas. */
++ for (i = 0; i < buffer->deltaCount; i += 1)
++ {
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ Context->recordArray,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++
++ /* Merge all pending states. */
++ for (j = 0; j < kDelta->recordCount; j += 1)
++ {
++ if (j >= Context->stateCount)
++ {
++ break;
++ }
++
++ /* Get the current state record. */
++ record = &recordArray[j];
++
++ /* Get the state address. */
++ address = record->address;
++
++ /* Make sure the state is a part of the mapping table. */
++ if (address >= Context->stateCount)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): State 0x%04X is not mapped.\n",
++ __FUNCTION__, __LINE__,
++ address
++ );
++
++ continue;
++ }
++
++ /* Get the state index. */
++ index = map[address].index;
++
++ /* Skip the state if not mapped. */
++ if (index == 0)
++ {
++#if gcdDEBUG
++ if ((address != 0x0594)
++ && (address != 0x0E00)
++ && (address != 0x0E03)
++ )
++ {
++#endif
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): State 0x%04X is not mapped.\n",
++ __FUNCTION__, __LINE__,
++ address
++ );
++#if gcdDEBUG
++ }
++#endif
++ continue;
++ }
++
++ /* Get the data mask. */
++ mask = record->mask;
++
++ /* Masked states that are being completly reset or regular states. */
++ if ((mask == 0) || (mask == ~0U))
++ {
++ /* Get the new data value. */
++ data = record->data;
++
++ /* Process special states. */
++ if (address == 0x0595)
++ {
++ /* Force auto-disable to be disabled. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13)));
++ }
++
++#if gcdSECURE_USER
++ /* Do we need to convert the logical address? */
++ if (Context->hint[address])
++ {
++ /* Map handle into physical address. */
++ gcmkONERROR(gckKERNEL_MapLogicalToPhysical(
++ kernel, cache, (gctPOINTER) &data
++ ));
++ }
++#endif
++
++ /* Set new data. */
++ buffer->logical[index] = data;
++ }
++
++ /* Masked states that are being set partially. */
++ else
++ {
++ buffer->logical[index]
++ = (~mask & buffer->logical[index])
++ | (mask & record->data);
++ }
++ }
++
++ /* Get the element count. */
++ if (kDelta->elementCount != 0)
++ {
++ elementCount = kDelta->elementCount;
++ }
++
++ /* Dereference delta. */
++ kDelta->refCount -= 1;
++ gcmkASSERT(kDelta->refCount >= 0);
++
++ /* Get the next state delta. */
++ nDelta = gcmUINT64_TO_PTR(kDelta->next);
++
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Update the user delta pointer. */
++ uDelta = nDelta;
++ }
++
++ /* Hardware disables all input streams when the stream 0 is programmed,
++ it then reenables those streams that were explicitely programmed by
++ the software. Because of this we cannot program the entire array of
++ values, otherwise we'll get all streams reenabled, but rather program
++ only those that are actully needed by the software. */
++ if (elementCount != 0)
++ {
++ gctUINT base;
++ gctUINT nopCount;
++ gctUINT32_PTR nop;
++ gctUINT fe2vsCount = 12;
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) ))
++ {
++ fe2vsCount = 16;
++ }
++
++ /* Determine the base index of the vertex stream array. */
++ base = map[0x0180].index;
++
++ /* Set the proper state count. */
++ buffer->logical[base - 1]
++ = ((((gctUINT32) (buffer->logical[base - 1])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (elementCount ) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine the number of NOP commands. */
++ nopCount
++ = (fe2vsCount / 2)
++ - (elementCount / 2);
++
++ /* Determine the location of the first NOP. */
++ nop = &buffer->logical[base + (elementCount | 1)];
++
++ /* Fill the unused space with NOPs. */
++ for (i = 0; i < nopCount; i += 1)
++ {
++ if (nop >= buffer->logical + Context->totalSize)
++ {
++ break;
++ }
++
++ /* Generate a NOP command. */
++ *nop = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ /* Advance. */
++ nop += 2;
++ }
++ }
++
++ /* Reset pending deltas. */
++ buffer->deltaCount = 0;
++ buffer->delta = gcvNULL;
++ }
++
++ /* Set state delta user pointer. */
++ uDelta = StateDelta;
++
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* State delta cannot be attached to anything yet. */
++ if (kDelta->refCount != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): kDelta->refCount = %d (has to be 0).\n",
++ __FUNCTION__, __LINE__,
++ kDelta->refCount
++ );
++ }
++
++ /* Attach to all contexts. */
++ buffer = Context->buffer;
++
++ do
++ {
++ /* Attach to the context if nothing is attached yet. If a delta
++ is allready attached, all we need to do is to increment
++ the number of deltas in the context. */
++ if (buffer->delta == gcvNULL)
++ {
++ buffer->delta = uDelta;
++ }
++
++ /* Update reference count. */
++ kDelta->refCount += 1;
++
++ /* Update counters. */
++ buffer->deltaCount += 1;
++
++ /* Get the next context buffer. */
++ buffer = buffer->next;
++
++ if (buffer == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++ }
++ while (Context->buffer != buffer);
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Schedule an event to mark the context buffer as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ buffer->eventObj, buffer->signal, gcvKERNEL_PIXEL
++ ));
++
++ /* Advance to the next context buffer. */
++ Context->buffer = buffer->next;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Get access to the state records. */
++ if (kDelta != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++ }
++
++ /* Close access to the current state delta. */
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.h 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,157 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_context_h_
++#define __gc_hal_kernel_context_h_
++
++#include "gc_hal_kernel_buffer.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Maps state locations within the context buffer. */
++typedef struct _gcsSTATE_MAP * gcsSTATE_MAP_PTR;
++typedef struct _gcsSTATE_MAP
++{
++ /* Index of the state in the context buffer. */
++ gctUINT index;
++
++ /* State mask. */
++ gctUINT32 mask;
++}
++gcsSTATE_MAP;
++
++/* Context buffer. */
++typedef struct _gcsCONTEXT * gcsCONTEXT_PTR;
++typedef struct _gcsCONTEXT
++{
++ /* For debugging: the number of context buffer in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Context busy signal. */
++ gctSIGNAL signal;
++
++ /* Physical address of the context buffer. */
++ gctPHYS_ADDR physical;
++
++ /* Logical address of the context buffer. */
++ gctUINT32_PTR logical;
++
++ /* Pointer to the LINK commands. */
++ gctPOINTER link2D;
++ gctPOINTER link3D;
++
++ /* The number of pending state deltas. */
++ gctUINT deltaCount;
++
++ /* Pointer to the first delta to be applied. */
++ gcsSTATE_DELTA_PTR delta;
++
++ /* Next context buffer. */
++ gcsCONTEXT_PTR next;
++}
++gcsCONTEXT;
++
++/* gckCONTEXT structure that hold the current context. */
++struct _gckCONTEXT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Command buffer alignment. */
++ gctSIZE_T alignment;
++ gctSIZE_T reservedHead;
++ gctSIZE_T reservedTail;
++
++ /* Context buffer metrics. */
++ gctSIZE_T stateCount;
++ gctSIZE_T totalSize;
++ gctSIZE_T bufferSize;
++ gctUINT32 linkIndex2D;
++ gctUINT32 linkIndex3D;
++ gctUINT32 linkIndexXD;
++ gctUINT32 entryOffset3D;
++ gctUINT32 entryOffsetXDFrom2D;
++ gctUINT32 entryOffsetXDFrom3D;
++
++ /* Dirty flags. */
++ gctBOOL dirty;
++ gctBOOL dirty2D;
++ gctBOOL dirty3D;
++ gcsCONTEXT_PTR dirtyBuffer;
++
++ /* State mapping. */
++ gcsSTATE_MAP_PTR map;
++
++ /* List of context buffers. */
++ gcsCONTEXT_PTR buffer;
++
++ /* A copy of the user record array. */
++ gctUINT recordArraySize;
++ gcsSTATE_DELTA_RECORD_PTR recordArray;
++
++ /* Requested pipe select for context. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Variables used for building state buffer. */
++ gctUINT32 lastAddress;
++ gctSIZE_T lastSize;
++ gctUINT32 lastIndex;
++ gctBOOL lastFixed;
++
++ /* Hint array. */
++#if gcdSECURE_USER
++ gctBOOL_PTR hint;
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ gcsPROFILER_COUNTERS latestProfiler;
++ gcsPROFILER_COUNTERS histroyProfiler;
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++#endif
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_context_h_ */
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,7247 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#if VIVANTE_PROFILER_CONTEXT
++#include "gc_hal_kernel_context.h"
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++typedef struct _gcsiDEBUG_REGISTERS * gcsiDEBUG_REGISTERS_PTR;
++typedef struct _gcsiDEBUG_REGISTERS
++{
++ gctSTRING module;
++ gctUINT index;
++ gctUINT shift;
++ gctUINT data;
++ gctUINT count;
++ gctUINT32 signature;
++}
++gcsiDEBUG_REGISTERS;
++
++extern int gpu3DMinClock;
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gceSTATUS status;
++
++ gctUINT32 chipIdentity;
++
++ gctUINT32 streamCount = 0;
++ gctUINT32 registerMax = 0;
++ gctUINT32 threadCount = 0;
++ gctUINT32 shaderCoreCount = 0;
++ gctUINT32 vertexCacheSize = 0;
++ gctUINT32 vertexOutputBufferSize = 0;
++ gctUINT32 pixelPipes = 0;
++ gctUINT32 instructionCount = 0;
++ gctUINT32 numConstants = 0;
++ gctUINT32 bufferSize = 0;
++ gctUINT32 varyingsCount = 0;
++ gctBOOL useHZ;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /***************************************************************************
++ ** Get chip ID and revision.
++ */
++
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00018,
++ &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ Identity->chipModel = gcv500;
++ Identity->chipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00020,
++ (gctUINT32_PTR) &Identity->chipModel));
++
++ /* !!!! HACK ALERT !!!! */
++ /* Because people change device IDs without letting software know
++ ** about it - here is the hack to make it all look the same. Only
++ ** for GC400 family. Next time - TELL ME!!! */
++ if (((Identity->chipModel & 0xFF00) == 0x0400)
++ && (Identity->chipModel != 0x0420))
++ {
++ Identity->chipModel = (gceCHIPMODEL) (Identity->chipModel & 0x0400);
++ }
++
++ /* Read CHIP_REV register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00024,
++ &Identity->chipRevision));
++
++ if ((Identity->chipModel == gcv300)
++ && (Identity->chipRevision == 0x2201)
++ )
++ {
++ gctUINT32 chipDate;
++ gctUINT32 chipTime;
++
++ /* Read date and time registers. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00028,
++ &chipDate));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0002C,
++ &chipTime));
++
++ if ((chipDate == 0x20080814) && (chipTime == 0x12051100))
++ {
++ /* This IP has an ECO; put the correct revision in it. */
++ Identity->chipRevision = 0x1051;
++ }
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipModel=%X",
++ Identity->chipModel);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipRevision=%X",
++ Identity->chipRevision);
++
++
++ /***************************************************************************
++ ** Get chip features.
++ */
++
++ /* Read chip feature register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0001C,
++ &Identity->chipFeatures));
++
++#ifndef VIVANTE_NO_3D
++ /* Disable fast clear on GC700. */
++ if (Identity->chipModel == gcv700)
++ {
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++#endif
++
++ if (((Identity->chipModel == gcv500) && (Identity->chipRevision < 2))
++ || ((Identity->chipModel == gcv300) && (Identity->chipRevision < 0x2000))
++ )
++ {
++ /* GC500 rev 1.x and GC300 rev < 2.0 doesn't have these registers. */
++ Identity->chipMinorFeatures = 0;
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ }
++ else
++ {
++ /* Read chip minor feature register #0. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00034,
++ &Identity->chipMinorFeatures));
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))))
++ )
++ {
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00074,
++ &Identity->chipMinorFeatures1));
++
++ /* Read chip minor featuress register #2. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00084,
++ &Identity->chipMinorFeatures2));
++
++ /*Identity->chipMinorFeatures2 &= ~(0x1 << 3);*/
++
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00088,
++ &Identity->chipMinorFeatures3));
++
++ /*The BG2 chip has no compression supertiled, and the bit of GCMinorFeature3BugFixes15 is n/a*/
++ if(Identity->chipModel == gcv1000 && Identity->chipRevision == 0x5036)
++ {
++ Identity->chipMinorFeatures3
++ = ((((gctUINT32) (Identity->chipMinorFeatures3)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ Identity->chipMinorFeatures3
++ = ((((gctUINT32) (Identity->chipMinorFeatures3)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27)));
++ }
++
++ /* Read chip minor featuress register #4. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00094,
++ &Identity->chipMinorFeatures4));
++ }
++ else
++ {
++ /* Chip doesn't has minor features register #1 or 2 or 3 or 4. */
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ }
++ }
++
++ /* Get the Supertile layout in the hardware. */
++ if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))))
++ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))))
++ {
++ Identity->superTileMode = 2;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))))
++ {
++ Identity->superTileMode = 1;
++ }
++ else
++ {
++ Identity->superTileMode = 0;
++ }
++
++ /* Exception for GC1000, revision 5035 & GC800, revision 4612 */
++ if (((Identity->chipModel == gcv1000) && ((Identity->chipRevision == 0x5035)
++ || (Identity->chipRevision == 0x5036)
++ || (Identity->chipRevision == 0x5037)))
++ || ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4612))
++ || ((Identity->chipModel == gcv860) && (Identity->chipRevision == 0x4647)))
++ {
++ Identity->superTileMode = 1;
++ }
++
++ if (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5245)
++ {
++ useHZ = ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))))
++ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))));
++ }
++ else
++ {
++ useHZ = gcvFALSE;
++ }
++
++ if (useHZ)
++ {
++ /* Disable EZ. */
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++ }
++
++ /* Disable HZ when EZ is present for older chips. */
++ else if (!((((gctUINT32) (Identity->chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))))
++ {
++ /* Disable HIERARCHICAL_Z. */
++ Identity->chipMinorFeatures
++ = ((((gctUINT32) (Identity->chipMinorFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27)));
++ }
++
++ /* Disable rectangle primitive when chip is gc880_5_1_0_rc6*/
++ if ((Identity->chipModel == gcv880) && (Identity->chipRevision == 0x5106))
++ {
++ /* Disable rectangle primitive. */
++ Identity->chipMinorFeatures2
++ = ((((gctUINT32) (Identity->chipMinorFeatures2)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++
++ if ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4605))
++ {
++ /* Correct feature bit: RTL does not have such feature. */
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipFeatures=0x%08X",
++ Identity->chipFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures=0x%08X",
++ Identity->chipMinorFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures1=0x%08X",
++ Identity->chipMinorFeatures1);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures2=0x%08X",
++ Identity->chipMinorFeatures2);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures3=0x%08X",
++ Identity->chipMinorFeatures3);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures4=0x%08X",
++ Identity->chipMinorFeatures4);
++
++ /***************************************************************************
++ ** Get chip specs.
++ */
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ gctUINT32 specs, specs2, specs3;
++
++ /* Read gcChipSpecs register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00048,
++ &specs));
++
++ /* Extract the fields. */
++ streamCount = (((((gctUINT32) (specs)) >> (0 ? 3:0)) & ((gctUINT32) ((((1 ? 3:0) - (0 ? 3:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:0) - (0 ? 3:0) + 1)))))) );
++ registerMax = (((((gctUINT32) (specs)) >> (0 ? 7:4)) & ((gctUINT32) ((((1 ? 7:4) - (0 ? 7:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:4) - (0 ? 7:4) + 1)))))) );
++ threadCount = (((((gctUINT32) (specs)) >> (0 ? 11:8)) & ((gctUINT32) ((((1 ? 11:8) - (0 ? 11:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:8) - (0 ? 11:8) + 1)))))) );
++ shaderCoreCount = (((((gctUINT32) (specs)) >> (0 ? 24:20)) & ((gctUINT32) ((((1 ? 24:20) - (0 ? 24:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:20) - (0 ? 24:20) + 1)))))) );
++ vertexCacheSize = (((((gctUINT32) (specs)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) );
++ vertexOutputBufferSize = (((((gctUINT32) (specs)) >> (0 ? 31:28)) & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1)))))) );
++ pixelPipes = (((((gctUINT32) (specs)) >> (0 ? 27:25)) & ((gctUINT32) ((((1 ? 27:25) - (0 ? 27:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:25) - (0 ? 27:25) + 1)))))) );
++
++ /* Read gcChipSpecs2 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00080,
++ &specs2));
++
++ instructionCount = (((((gctUINT32) (specs2)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) );
++ numConstants = (((((gctUINT32) (specs2)) >> (0 ? 31:16)) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1)))))) );
++ bufferSize = (((((gctUINT32) (specs2)) >> (0 ? 7:0)) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1)))))) );
++
++ /* Read gcChipSpecs3 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0008C,
++ &specs3));
++
++ varyingsCount = (((((gctUINT32) (specs3)) >> (0 ? 8:4)) & ((gctUINT32) ((((1 ? 8:4) - (0 ? 8:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:4) - (0 ? 8:4) + 1)))))) );
++ }
++
++ /* Get the number of pixel pipes. */
++ Identity->pixelPipes = gcmMAX(pixelPipes, 1);
++
++ /* Get the stream count. */
++ Identity->streamCount = (streamCount != 0)
++ ? streamCount
++ : (Identity->chipModel >= gcv1000) ? 4 : 1;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: streamCount=%u%s",
++ Identity->streamCount,
++ (streamCount == 0) ? " (default)" : "");
++
++ /* Get the vertex output buffer size. */
++ Identity->vertexOutputBufferSize = (vertexOutputBufferSize != 0)
++ ? 1 << vertexOutputBufferSize
++ : (Identity->chipModel == gcv400)
++ ? (Identity->chipRevision < 0x4000) ? 512
++ : (Identity->chipRevision < 0x4200) ? 256
++ : 128
++ : (Identity->chipModel == gcv530)
++ ? (Identity->chipRevision < 0x4200) ? 512
++ : 128
++ : 512;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexOutputBufferSize=%u%s",
++ Identity->vertexOutputBufferSize,
++ (vertexOutputBufferSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of threads. */
++ Identity->threadCount = (threadCount != 0)
++ ? 1 << threadCount
++ : (Identity->chipModel == gcv400) ? 64
++ : (Identity->chipModel == gcv500) ? 128
++ : (Identity->chipModel == gcv530) ? 128
++ : 256;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: threadCount=%u%s",
++ Identity->threadCount,
++ (threadCount == 0) ? " (default)" : "");
++
++ /* Get the number of shader cores. */
++ Identity->shaderCoreCount = (shaderCoreCount != 0)
++ ? shaderCoreCount
++ : (Identity->chipModel >= gcv1000) ? 2
++ : 1;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: shaderCoreCount=%u%s",
++ Identity->shaderCoreCount,
++ (shaderCoreCount == 0) ? " (default)" : "");
++
++ /* Get the vertex cache size. */
++ Identity->vertexCacheSize = (vertexCacheSize != 0)
++ ? vertexCacheSize
++ : 8;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexCacheSize=%u%s",
++ Identity->vertexCacheSize,
++ (vertexCacheSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of temporary registers. */
++ Identity->registerMax = (registerMax != 0)
++ /* Maximum of registerMax/4 registers are accessible to 1 shader */
++ ? 1 << registerMax
++ : (Identity->chipModel == gcv400) ? 32
++ : 64;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: registerMax=%u%s",
++ Identity->registerMax,
++ (registerMax == 0) ? " (default)" : "");
++
++ /* Get the instruction count. */
++ Identity->instructionCount = (instructionCount == 0) ? 256
++ : (instructionCount == 1) ? 1024
++ : (instructionCount == 2) ? 2048
++ : (instructionCount == 0xFF) ? 512
++ : 256;
++
++ if (Identity->instructionCount == 256)
++ {
++ if ((Identity->chipModel == gcv2000 && Identity->chipRevision == 0x5108)
++ || Identity->chipModel == gcv880)
++ {
++ Identity->instructionCount = 512;
++ }
++ }
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))))
++ {
++ Identity->instructionCount = 512;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: instructionCount=%u%s",
++ Identity->instructionCount,
++ (instructionCount == 0) ? " (default)" : "");
++
++ /* Get the number of constants. */
++ Identity->numConstants = (numConstants == 0) ? 168 : numConstants;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: numConstants=%u%s",
++ Identity->numConstants,
++ (numConstants == 0) ? " (default)" : "");
++
++ /* Get the buffer size. */
++ Identity->bufferSize = bufferSize;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: bufferSize=%u%s",
++ Identity->bufferSize,
++ (bufferSize == 0) ? " (default)" : "");
++
++
++ if (varyingsCount != 0)
++ {
++ /* Bug 4480. */
++ /*Identity->varyingsCount = varyingsCount;*/
++ Identity->varyingsCount = 12;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures1)) >> (0 ? 23:23) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))))
++ {
++ Identity->varyingsCount = 12;
++ }
++ else
++ {
++ Identity->varyingsCount = 8;
++ }
++
++ /* For some cores, it consumes two varying for position, so the max varying vectors should minus one. */
++ if ((Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5222) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5208) ||
++ ((Identity->chipModel == gcv2100 || Identity->chipModel == gcv2000) && Identity->chipRevision == 0x5108) ||
++ (Identity->chipModel == gcv880 && (Identity->chipRevision == 0x5107 || Identity->chipRevision == 0x5106)))
++ {
++ Identity->varyingsCount -= 1;
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_PowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckHARDWARE hardware = (gckHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++static gceSTATUS
++_VerifyDMA(
++ IN gckOS Os,
++ IN gceCORE Core,
++ gctUINT32_PTR Address1,
++ gctUINT32_PTR Address2,
++ gctUINT32_PTR State1,
++ gctUINT32_PTR State2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State1));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address1));
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State2));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address2));
++
++ if (*Address1 != *Address2)
++ {
++ break;
++ }
++
++ if (*State1 != *State2)
++ {
++ break;
++ }
++ }
++
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_DumpDebugRegisters(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gcsiDEBUG_REGISTERS_PTR Descriptor
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 select;
++ gctUINT32 data = 0;
++ gctUINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Descriptor=0x%X", Os, Descriptor);
++
++ gcmkPRINT_N(4, " %s debug registers:\n", Descriptor->module);
++
++ for (i = 0; i < Descriptor->count; i += 1)
++ {
++ select = i << Descriptor->shift;
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ gcmkPRINT_N(12, " [0x%02X] 0x%08X\n", i, data);
++ }
++
++ select = 0xF << Descriptor->shift;
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ if (data == Descriptor->signature)
++ {
++ break;
++ }
++ }
++
++ if (i == 500)
++ {
++ gcmkPRINT_N(4, " failed to obtain the signature (read 0x%08X).\n", data);
++ }
++ else
++ {
++ gcmkPRINT_N(8, " signature = 0x%08X (%d read attempt(s))\n", data, i + 1);
++ }
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IsGPUPresent(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++#if 0
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++#endif
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ control));
++
++#if 0
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Hardware->os,
++ Hardware->core,
++ &identity));
++
++ /* Check if these are the same values as saved before. */
++ if ((Hardware->identity.chipModel != identity.chipModel)
++ || (Hardware->identity.chipRevision != identity.chipRevision)
++ || (Hardware->identity.chipFeatures != identity.chipFeatures)
++ || (Hardware->identity.chipMinorFeatures != identity.chipMinorFeatures)
++ || (Hardware->identity.chipMinorFeatures1 != identity.chipMinorFeatures1)
++ || (Hardware->identity.chipMinorFeatures2 != identity.chipMinorFeatures2)
++ )
++ {
++ gcmkPRINT("[galcore]: GPU is not present.");
++ gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING);
++ }
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++_FlushCache(
++ gckHARDWARE Hardware,
++ gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes, requested;
++ gctPOINTER buffer;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(Command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(Command, requested));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++/******************************************************************************\
++****************************** gckHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckHARDWARE_Construct
++**
++** Construct a new gckHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** OUTPUT:
++**
++** gckHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckHARDWARE
++** object.
++*/
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware = gcvNULL;
++ gctUINT16 data = 0xff00;
++ gctUINT32 axi_ot;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ /* Enable the GPU. */
++ gcmkONERROR(gckOS_SetGPUPower(Os, Core, gcvTRUE, gcvTRUE));
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Allocate the gckHARDWARE object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckHARDWARE),
++ &pointer));
++
++ hardware = (gckHARDWARE) pointer;
++
++ /* Initialize the gckHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++ hardware->core = Core;
++
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Os, Core, &hardware->identity));
++
++ /* Determine the hardware type */
++ switch (hardware->identity.chipModel)
++ {
++ case gcv350:
++ case gcv355:
++ hardware->type = gcvHARDWARE_VG;
++ break;
++
++ case gcv300:
++ case gcv320:
++ case gcv420:
++ hardware->type = gcvHARDWARE_2D;
++ /*set outstanding limit*/
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x10;
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00414, axi_ot));
++ break;
++
++ default:
++ hardware->type = gcvHARDWARE_3D;
++ if(hardware->identity.chipModel == gcv880)
++ {
++ /*set outstanding limit*/
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x10;
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00414, axi_ot));
++ }
++
++ if ((((((gctUINT32) (hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ))
++ {
++ hardware->type = (gceHARDWARE_TYPE) (hardware->type | gcvHARDWARE_2D);
++ }
++ }
++
++ hardware->powerBaseAddress
++ = ((hardware->identity.chipModel == gcv300)
++ && (hardware->identity.chipRevision < 0x2000))
++ ? 0x0100
++ : 0x0000;
++
++ /* _ResetGPU need powerBaseAddress. */
++ status = _ResetGPU(hardware, Os, Core);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++ hardware->powerMutex = gcvNULL;
++
++ hardware->mmuVersion
++ = (((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 28:28)) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) );
++
++ /* Determine whether bug fixes #1 are present. */
++ hardware->extraEventStates = ((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))));
++
++ /* Check if big endian */
++ hardware->bigEndian = (*(gctUINT8 *)&data == 0xff);
++
++ /* Initialize the fast clear. */
++ gcmkONERROR(gckHARDWARE_SetFastClear(hardware, -1, -1));
++
++#if !gcdENABLE_128B_MERGE
++
++ if (((((gctUINT32) (hardware->identity.chipMinorFeatures2)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ /* 128B merge is turned on by default. Disable it. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00558, 0));
++ }
++
++#endif
++
++ /* Set power state to ON. */
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++ hardware->lastWaitLink = ~0U;
++ hardware->globalSemaphore = gcvNULL;
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ hardware->powerOnFscaleVal = 64;
++#endif
++
++ gcmkONERROR(gckOS_CreateMutex(Os, &hardware->powerMutex));
++ gcmkONERROR(gckOS_CreateSemaphore(Os, &hardware->globalSemaphore));
++ hardware->startIsr = gcvNULL;
++ hardware->stopIsr = gcvNULL;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _PowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++
++#if gcdLINK_QUEUE_SIZE
++ hardware->linkQueue.front = 0;
++ hardware->linkQueue.rear = 0;
++ hardware->linkQueue.count = 0;
++#endif
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Disable profiler by default */
++ hardware->gpuProfiler = gcvFALSE;
++
++ /* Return pointer to the gckHARDWARE object. */
++ *Hardware = hardware;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Hardware=0x%x", *Hardware);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, Core, gcvFALSE, gcvFALSE));
++
++ if (hardware->globalSemaphore != gcvNULL)
++ {
++ /* Destroy the global semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Os,
++ hardware->globalSemaphore));
++ }
++
++ if (hardware->powerMutex != gcvNULL)
++ {
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ if (hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, hardware));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Destroy
++**
++** Destroy an gckHARDWARE object.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Destroy the power semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Hardware->os, Hardware->powerMutex));
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Hardware->os, Hardware));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_GetType
++**
++** Get the hardware type.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gceHARDWARE_TYPE * Type
++** Pointer to a variable that receives the type of hardware object.
++*/
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ gcmkVERIFY_ARGUMENT(Type != gcvNULL);
++
++ *Type = Hardware->type;
++
++ gcmkFOOTER_ARG("*Type=%d", *Type);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_InitializeHardware
++**
++** Initialize the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++ gctUINT32 chipRev;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the chip revision register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00024,
++ &chipRev));
++
++ if (chipRev != Hardware->identity.chipRevision)
++ {
++ /* Chip is not there! */
++ gcmkONERROR(gcvSTATUS_CONTEXT_LOSSED);
++ }
++
++ /* Disable isolate GPU bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)))));
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ /* Enable debug register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ /* Reset memory counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ ~0U));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++
++ /* Get the system's physical base address. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Program the base addesses. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0041C,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00418,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00428,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00420,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00424,
++ baseAddress));
++
++#if !VIVANTE_PROFILER
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ /* Enable clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ if ((Hardware->identity.chipRevision == 0x4301)
++ || (Hardware->identity.chipRevision == 0x4302)
++ )
++ {
++ /* Disable stall module level clock gating for 4.3.0.1 and 4.3.0.2
++ ** revisions. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++
++#ifndef VIVANTE_NO_3D
++ /* Disable PE clock gating on revs < 5.0 when HZ is present without a
++ ** bug fix. */
++ if ((Hardware->identity.chipRevision < 0x5000)
++ && ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))))
++ && ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))))
++ )
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable PE clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++#endif
++ }
++#endif
++
++ /* Special workaround for this core
++ ** Make sure pulse eater kicks in only when SH is idle */
++ if (Hardware->identity.chipModel == gcv4000 &&
++ Hardware->identity.chipRevision == 0x5208)
++ {
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)))));
++ }
++
++ if ((gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) == gcvFALSE)
++ || (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) && (Hardware->identity.chipRevision < 0x5422))
++ )
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15)));
++
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++ /* Special workaround for this core
++ ** Make sure FE and TX are on different buses */
++ if ((Hardware->identity.chipModel == gcv2000)
++ && (Hardware->identity.chipRevision == 0x5108))
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ &data));
++
++ /* Set FE bus to one, TX bus to zero */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ data));
++ }
++
++ /* Test if MMU is initialized. */
++ if ((Hardware->kernel != gcvNULL)
++ && (Hardware->kernel->mmu != gcvNULL)
++ )
++ {
++ /* Reset MMU. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(Hardware,
++ Hardware->kernel->mmu->pageTableLogical));
++ }
++ }
++
++ if (Hardware->identity.chipModel >= gcv400
++ && Hardware->identity.chipModel != gcv420
++ && (((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 15:15) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) != gcvTRUE)
++ )
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable PA clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++#if gcdHZ_L2_DISALBE
++ /* Disable HZ-L2. */
++ if (((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) == gcvTRUE ||
++ ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) == gcvTRUE)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++#endif
++
++ /* Limit 2D outstanding request. */
++ if(Hardware->identity.chipModel == gcv880)
++ {
++ gctUINT32 axi_ot;
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x10;
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00414, axi_ot));
++ }
++
++ if ((Hardware->identity.chipModel == gcv320)
++ && ((Hardware->identity.chipRevision == 0x5007)
++ || (Hardware->identity.chipRevision == 0x5220)))
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0002C,
++ &data));
++ if (data != 33956864)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (Hardware->identity.chipRevision == 0x5220 ? 8 : (Hardware->identity.chipRevision == 0x5007 ? 16 : 0)) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++ }
++
++ /* Update GPU AXI cache atttribute. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00008,
++ 0x00002200));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*InternalSize=%lu *InternalBaseAddress=0x%08x "
++ "*InternalAlignment=0x%08x *ExternalSize=%lu "
++ "*ExternalBaseAddress=0x%08x *ExtenalAlignment=0x%08x "
++ "*HorizontalTileSize=%u *VerticalTileSize=%u",
++ gcmOPT_VALUE(InternalSize),
++ gcmOPT_VALUE(InternalBaseAddress),
++ gcmOPT_VALUE(InternalAlignment),
++ gcmOPT_VALUE(ExternalSize),
++ gcmOPT_VALUE(ExternalBaseAddress),
++ gcmOPT_VALUE(ExternalAlignment),
++ gcmOPT_VALUE(HorizontalTileSize),
++ gcmOPT_VALUE(VerticalTileSize));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++** Pointer to the identity structure.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gctUINT32 features;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Identity != gcvNULL);
++
++ /* Return chip model and revision. */
++ Identity->chipModel = Hardware->identity.chipModel;
++ Identity->chipRevision = Hardware->identity.chipRevision;
++
++ /* Return feature set. */
++ features = Hardware->identity.chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* Override fast clear by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ if ((((((gctUINT32) (features)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ))
++ {
++ /* Override compression by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (Hardware->allowCompression) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 through GC500.2 and GC300,
++ ** since they did not have this bit. */
++ if (((Hardware->identity.chipModel == gcv500) && (Hardware->identity.chipRevision <= 2))
++ || (Hardware->identity.chipModel == gcv300)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ Identity->chipFeatures = features;
++
++ /* Return minor features. */
++ Identity->chipMinorFeatures = Hardware->identity.chipMinorFeatures;
++ Identity->chipMinorFeatures1 = Hardware->identity.chipMinorFeatures1;
++ Identity->chipMinorFeatures2 = Hardware->identity.chipMinorFeatures2;
++ Identity->chipMinorFeatures3 = Hardware->identity.chipMinorFeatures3;
++ Identity->chipMinorFeatures4 = Hardware->identity.chipMinorFeatures4;
++
++ /* Return chip specs. */
++ Identity->streamCount = Hardware->identity.streamCount;
++ Identity->registerMax = Hardware->identity.registerMax;
++ Identity->threadCount = Hardware->identity.threadCount;
++ Identity->shaderCoreCount = Hardware->identity.shaderCoreCount;
++ Identity->vertexCacheSize = Hardware->identity.vertexCacheSize;
++ Identity->vertexOutputBufferSize = Hardware->identity.vertexOutputBufferSize;
++ Identity->pixelPipes = Hardware->identity.pixelPipes;
++ Identity->instructionCount = Hardware->identity.instructionCount;
++ Identity->numConstants = Hardware->identity.numConstants;
++ Identity->bufferSize = Hardware->identity.bufferSize;
++ Identity->varyingsCount = Hardware->identity.varyingsCount;
++ Identity->superTileMode = Hardware->identity.superTileMode;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Addres=0x%08x", Hardware, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ if (Hardware->mmuVersion == 0)
++ {
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 31:31)) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x1:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = (((((gctUINT32) (Address)) >> (0 ? 30:0)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1)))))) );
++ }
++ else
++ {
++ *Pool = gcvPOOL_SYSTEM;
++ *Offset = Address;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Pool=%d *Offset=0x%08x", *Pool, *Offset);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of command buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes for the prefetch unit (until after the first LINK).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++#ifdef __QNXNTO__
++ IN gctPOINTER Physical,
++ IN gctBOOL PhysicalAddresses,
++#endif
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0, control;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Bytes=%lu",
++ Hardware, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++#ifdef __QNXNTO__
++ if (PhysicalAddresses && (Hardware->mmuVersion == 0))
++ {
++ /* Convert physical into hardware specific address. */
++ gcmkONERROR(
++ gckHARDWARE_ConvertPhysical(Hardware, Physical, &address));
++ }
++ else
++ {
++#endif
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(
++ gckHARDWARE_ConvertLogical(Hardware, Logical, &address));
++#ifdef __QNXNTO__
++ }
++#endif
++
++ /* Enable all events. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00014, ~0U));
++
++ /* Write address register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00654, address));
++
++ /* Build control register. */
++ control = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) ((Bytes + 7) >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ /* Set big endian */
++ if (Hardware->bigEndian)
++ {
++ control |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20)));
++ }
++
++ /* Write control register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00658, control));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Started command buffer @ 0x%08x",
++ address);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_WaitLink
++**
++** Append a WAIT/LINK command sequence at the specified location in the command
++** queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** WAIT/LINK command sequence at or gcvNULL just to query the size of the
++** WAIT/LINK command sequence.
++**
++** gctUINT32 Offset
++** Offset into command buffer required for alignment.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the WAIT/LINK command
++** sequence. If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** by the WAIT/LINK command sequence. If 'Bytes' is gcvNULL, nothing will
++** be returned.
++**
++** gctUINT32 * WaitOffset
++** Pointer to a variable that will receive the offset of the WAIT command
++** from the specified logcial pointer.
++** If 'WaitOffset' is gcvNULL nothing will be returned.
++**
++** gctSIZE_T * WaitSize
++** Pointer to a variable that will receive the number of bytes used by
++** the WAIT command. If 'LinkSize' is gcvNULL nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctSIZE_T * WaitSize
++ )
++{
++ static const gctUINT waitCount = 200;
++
++ gceSTATUS status;
++ gctUINT32 address;
++ gctUINT32_PTR logical;
++ gctSIZE_T bytes;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x *Bytes=%lu",
++ Hardware, Logical, Offset, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical != gcvNULL) || (Bytes != gcvNULL));
++
++ /* Compute number of bytes required. */
++#if gcd6000_SUPPORT
++ bytes = gcmALIGN(Offset + 96, 8) - Offset;
++#else
++ bytes = gcmALIGN(Offset + 16, 8) - Offset;
++#endif
++
++ /* Cast the input pointer. */
++ logical = (gctUINT32_PTR) Logical;
++
++ if (logical != gcvNULL)
++ {
++ /* Not enough space? */
++ if (*Bytes < bytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, &address));
++
++ /* Store the WAIT/LINK address. */
++ Hardware->lastWaitLink = address;
++
++ /* Append WAIT(count). */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (waitCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++#if gcd6000_SUPPORT
++ /* Send FE-PE sempahore token. */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Send FE-PE stall token. */
++ logical[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ logical[5]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /*************************************************************/
++ /* Enable chip ID 0. */
++ logical[6] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | (1 << 0);
++
++ /* Send semaphore from FE to ChipID 1. */
++ logical[8] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[9] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x0F & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24)));
++
++ /* Send semaphore from FE to ChipID 1. */
++ logical[10] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ logical[11] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x0F & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24)));
++
++ /*************************************************************/
++ /* Enable chip ID 1. */
++ logical[12] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | (1 << 1);
++
++ /* Send semaphore from FE to ChipID 1. */
++ logical[14] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[15] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x0F & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24)));
++
++ /* Wait for semaphore from ChipID 0. */
++ logical[16] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ logical[17] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x0F & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:24) - (0 ? 27:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:24) - (0 ? 27:24) + 1))))))) << (0 ? 27:24)));
++
++ /*************************************************************/
++ /* Enable all chips. */
++ logical[18] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | (0xFFFF);
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[20]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[21]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Append LINK(2, address). */
++ logical[22]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[23] = address;
++#else
++ /* Append LINK(2, address). */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3] = address;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, waitCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: LINK 0x%08x, #%lu",
++ address + 8, address, bytes
++ );
++#endif
++
++ if (WaitOffset != gcvNULL)
++ {
++ /* Return the offset pointer to WAIT command. */
++ *WaitOffset = 0;
++ }
++
++ if (WaitSize != gcvNULL)
++ {
++ /* Return number of bytes used by the WAIT command. */
++ *WaitSize = 8;
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the WAIT/LINK command
++ ** sequence. */
++ *Bytes = bytes;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *WaitOffset=0x%x *WaitSize=%lu",
++ gcmOPT_VALUE(Bytes), gcmOPT_VALUE(WaitOffset),
++ gcmOPT_VALUE(WaitSize));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_End
++**
++** Append an END command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** END command at or gcvNULL just to query the size of the END command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append END. */
++ logical[0] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: END", Logical);
++
++ /* Make sure the CPU writes out the data to memory. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Nop
++**
++** Append a NOP command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** NOP command at or gcvNULL just to query the size of the NOP command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the NOP command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the NOP command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append NOP. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: NOP", Logical);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the NOP command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Wait
++**
++** Append a WAIT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** WAIT command at or gcvNULL just to query the size of the WAIT command.
++**
++** gctUINT32 Count
++** Number of cycles to wait.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the WAIT command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the NOP command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Wait(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Count,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32_PTR logical;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Count=%u *Bytes=%lu",
++ Hardware, Logical, Count, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ /* Cast the input pointer. */
++ logical = (gctUINT32_PTR) Logical;
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append WAIT. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ {
++ gctUINT32 address;
++
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Hardware, logical, &address
++ ));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, Count
++ );
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the WAIT command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Event
++**
++** Append an EVENT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the EVENT command at or gcvNULL just to query the size of the EVENT
++** command.
++**
++** gctUINT8 Event
++** Event ID to program.
++**
++** gceKERNEL_WHERE FromWhere
++** Location of the pipe to send the event.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the EVENT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT size;
++ gctUINT32 destination = 0;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Event=%u FromWhere=%d *Bytes=%lu",
++ Hardware, Logical, Event, FromWhere, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++ gcmkVERIFY_ARGUMENT(Event < 32);
++
++ /* Determine the size of the command. */
++
++ size = (Hardware->extraEventStates && (FromWhere == gcvKERNEL_PIXEL))
++ ? gcmALIGN(8 + (1 + 5) * 4, 8) /* EVENT + 5 STATES */
++ : 8;
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < size)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ switch (FromWhere)
++ {
++ case gcvKERNEL_COMMAND:
++ /* From command processor. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ break;
++
++ case gcvKERNEL_PIXEL:
++ /* From pixel engine. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Append EVENT(Event, destiantion). */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1] = ((((gctUINT32) (destination)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (Event) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++
++ /* Make sure the event ID gets written out before GPU can access it. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ {
++ gctUINT32 phys;
++ gckOS_GetPhysicalAddress(Hardware->os, Logical, &phys);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: EVENT %d", phys, Event);
++ }
++#endif
++
++ /* Append the extra states. These are needed for the chips that do not
++ ** support back-to-back events due to the async interface. The extra
++ ** states add the necessary delay to ensure that event IDs do not
++ ** collide. */
++ if (size > 8)
++ {
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0100) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++ logical[3] = 0;
++ logical[4] = 0;
++ logical[5] = 0;
++ logical[6] = 0;
++ logical[7] = 0;
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT command. */
++ *Bytes = size;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_PipeSelect
++**
++** Append a PIPESELECT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the PIPESELECT command at or gcvNULL just to query the size of the
++** PIPESELECT command.
++**
++** gcePIPE_SELECT Pipe
++** Pipe value to select.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the PIPESELECT command.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the PIPESELECT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Pipe=%d *Bytes=%lu",
++ Hardware, Logical, Pipe, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ /* Append a PipeSelect. */
++ if (Logical != gcvNULL)
++ {
++ gctUINT32 flush, stall;
++
++ if (*Bytes < 32)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ flush = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++
++ stall = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1]
++ = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical, flush);
++
++ /* LoadState(AQSempahore, 1), stall. */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3]
++ = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: SEMAPHORE 0x%x", logical + 2, stall);
++
++ /* Stall, stall. */
++ logical[4] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ logical[5] = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: STALL 0x%x", logical + 4, stall);
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ logical[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[7] = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: PIPE %d", logical + 6, Pipe);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the PIPESELECT command. */
++ *Bytes = 32;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Link
++**
++** Append a LINK command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the LINK command at or gcvNULL just to query the size of the LINK
++** command.
++**
++** gctPOINTER FetchAddress
++** Logical address of destination of LINK.
++**
++** gctSIZE_T FetchSize
++** Number of bytes in destination of LINK.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the LINK command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the LINK command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER FetchAddress,
++ IN gctSIZE_T FetchSize,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gctUINT32 address;
++ gctUINT32 link;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x FetchAddress=0x%x FetchSize=%lu "
++ "*Bytes=%lu",
++ Hardware, Logical, FetchAddress, FetchSize,
++ gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Convert logical address to hardware address. */
++ gcmkONERROR(
++ gckHARDWARE_ConvertLogical(Hardware, FetchAddress, &address));
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical + 1, address));
++
++ /* Make sure the address got written before the LINK command. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++ /* Compute number of 64-byte aligned bytes to fetch. */
++ bytes = gcmALIGN(address + FetchSize, 8) - address;
++
++ /* Append LINK(bytes / 8), FetchAddress. */
++ link = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical, link));
++
++ /* Memory barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical));
++
++#if gcdLINK_QUEUE_SIZE && gcdVIRTUAL_COMMAND_BUFFER
++ if (address >= 0x80000000)
++ {
++ gckLINKQUEUE_Enqueue(&Hardware->linkQueue, address, address + bytes);
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_UpdateQueueTail
++**
++** Update the tail of the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the start of the command queue.
++**
++** gctUINT32 Offset
++** Offset into the command queue of the tail (last command).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x",
++ Hardware, Logical, Offset);
++
++ /* Verify the hardware. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Force a barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++
++ /* Notify gckKERNEL object of change. */
++ gcmkONERROR(
++ gckKERNEL_Notify(Hardware->kernel,
++ gcvNOTIFY_COMMAND_QUEUE,
++ gcvFALSE));
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ status = gckKERNEL_GetGPUAddress(Hardware->kernel, Logical, Address);
++
++ if (status == gcvSTATUS_INVALID_ADDRESS)
++#endif
++ {
++ /* Convert logical address into a physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, Logical, &address));
++
++ /* For old MMU, get GPU address according to baseAddress. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Subtract base address to get a GPU address. */
++ gcmkASSERT(address >= baseAddress);
++ address -= baseAddress;
++ }
++
++ /* Return hardware specific address. */
++ *Address = (Hardware->mmuVersion == 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (address) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)))
++ : address;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_ConvertPhysical
++**
++** Convert a physical address into a hardware specific address.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPHYS_ADDR Physical
++** Physical address to convert.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ConvertPhysical(
++ IN gckHARDWARE Hardware,
++ IN gctPHYS_ADDR Physical,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Physical=0x%x", Hardware, Physical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ address = gcmPTR2INT(Physical);
++
++ /* For old MMU, get GPU address according to baseAddress. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkVERIFY_OK(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Subtract base address to get a GPU address. */
++ gcmkASSERT(address >= baseAddress);
++ address -= baseAddress;
++ }
++
++ /* Return hardware specific address. */
++ *Address = (Hardware->mmuVersion == 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (address) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)))
++ : address;
++
++ /* Return the status. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Interrupt
++**
++** Process an interrupt.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL InterruptValid
++** If gcvTRUE, this function will read the interrupt acknowledge
++** register, stores the data, and return whether or not the interrupt
++** is ours or not. If gcvFALSE, this functions will read the interrupt
++** acknowledge register and combine it with any stored value to handle
++** the event notifications.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL InterruptValid
++ )
++{
++ gckEVENT eventObj;
++ gctUINT32 data;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x InterruptValid=%d", Hardware, InterruptValid);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Extract gckEVENT object. */
++ eventObj = Hardware->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ if (InterruptValid)
++ {
++ /* Read AQIntrAcknowledge register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00010,
++ &data));
++
++ if (data == 0)
++ {
++ /* Not our interrupt. */
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ }
++ else
++ {
++ /* Inform gckEVENT of the interrupt. */
++ status = gckEVENT_Interrupt(eventObj, data);
++ }
++ }
++ else
++ {
++ /* Handle events. */
++ status = gckEVENT_Notify(eventObj, 0);
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryCommandBuffer
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Alignment
++** Pointer to a variable receiving the alignment for each command.
++**
++** gctSIZE_T * ReservedHead
++** Pointer to a variable receiving the number of reserved bytes at the
++** head of each command buffer.
++**
++** gctSIZE_T * ReservedTail
++** Pointer to a variable receiving the number of bytes reserved at the
++** tail of each command buffer.
++*/
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * Alignment,
++ OUT gctSIZE_T * ReservedHead,
++ OUT gctSIZE_T * ReservedTail
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Alignment != gcvNULL)
++ {
++ /* Align every 8 bytes. */
++ *Alignment = 8;
++ }
++
++ if (ReservedHead != gcvNULL)
++ {
++ /* Reserve space for SelectPipe(). */
++ *ReservedHead = 32;
++ }
++
++ if (ReservedTail != gcvNULL)
++ {
++ /* Reserve space for Link(). */
++ *ReservedTail = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Alignment=%lu *ReservedHead=%lu *ReservedTail=%lu",
++ gcmOPT_VALUE(Alignment), gcmOPT_VALUE(ReservedHead),
++ gcmOPT_VALUE(ReservedTail));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = 1U << 31;
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*SystemSize=%lu *SystemBaseAddress=%lu",
++ gcmOPT_VALUE(SystemSize), gcmOPT_VALUE(SystemBaseAddress));
++ return gcvSTATUS_OK;
++}
++
++#ifndef VIVANTE_NO_3D
++/*******************************************************************************
++**
++** gckHARDWARE_QueryShaderCaps
++**
++** Query the shader capabilities.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT * VertexUniforms
++** Pointer to a variable receiving the number of uniforms in the vertex
++** shader.
++**
++** gctUINT * FragmentUniforms
++** Pointer to a variable receiving the number of uniforms in the
++** fragment shader.
++**
++** gctUINT * Varyings
++** Pointer to a variable receiving the maimum number of varyings.
++*/
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctUINT * Varyings
++ )
++{
++ gctUINT32 vsConstMax;
++ gctUINT32 psConstMax;
++
++ gcmkHEADER_ARG("Hardware=0x%x VertexUniforms=0x%x "
++ "FragmentUniforms=0x%x Varyings=0x%x",
++ Hardware, VertexUniforms,
++ FragmentUniforms, Varyings);
++
++ if ((Hardware->identity.chipModel == gcv2000)
++ && (Hardware->identity.chipRevision == 0x5118))
++ {
++ vsConstMax = 256;
++ psConstMax = 64;
++ }
++ else if (Hardware->identity.numConstants > 256)
++ {
++ vsConstMax = 256;
++ psConstMax = 256;
++ }
++ else if (Hardware->identity.numConstants == 256)
++ {
++ vsConstMax = 256;
++ psConstMax = 256;
++ }
++ else
++ {
++ vsConstMax = 168;
++ psConstMax = 64;
++ }
++
++ if (VertexUniforms != gcvNULL)
++ {
++ *VertexUniforms = vsConstMax;
++ }
++
++ if (FragmentUniforms != gcvNULL)
++ {
++ *FragmentUniforms = psConstMax;
++ }
++
++ if (Varyings != gcvNULL)
++ {
++ /* Return the shader varyings count. */
++ *Varyings = Hardware->identity.varyingsCount;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert the logical address into an hardware address. */
++ gcmkONERROR(
++ gckHARDWARE_ConvertLogical(Hardware, Logical, &address));
++
++ /* Also get the base address - we need a real physical address. */
++ gcmkONERROR(
++ gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Setting page table to 0x%08X",
++ address + baseAddress);
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00400,
++ address + baseAddress));
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00410,
++ address + baseAddress));
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00404,
++ address + baseAddress));
++
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00408,
++ address + baseAddress));
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0040C,
++ address + baseAddress));
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return status;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command;
++ gctUINT32_PTR buffer;
++ gctSIZE_T bufferSize;
++ gctBOOL commitEntered = gcvFALSE;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 flushSize;
++ gctUINT32 count;
++ gctUINT32 physical;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Hardware->kernel->command;
++
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvFALSE));
++ commitEntered = gcvTRUE;
++
++ /* Flush the memory controller. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, 8, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ gcmkONERROR(gckCOMMAND_Execute(command, 8));
++ }
++ else
++ {
++ flushSize = 16 * 4;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, flushSize, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ count = (bufferSize - flushSize + 7) >> 3;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(command->os, buffer, &physical));
++
++ /* Flush cache. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[3]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[5]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[7]
++ = physical + 8 * gcmSIZEOF(gctUINT32);
++
++ /* Flush MMU cache. */
++ buffer[8]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[9]
++ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[10]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[11]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[12]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[13]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[14]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[15]
++ = physical + flushSize;
++
++ gcmkONERROR(gckCOMMAND_Execute(command, flushSize));
++ }
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvFALSE));
++ commitEntered = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Hardware->kernel->command,
++ gcvFALSE));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetMMUv2
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_SetMMUv2(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Enable,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++ gctUINT32 config, address;
++ gckCOMMAND command;
++ gctUINT32_PTR buffer;
++ gctSIZE_T bufferSize;
++ gctBOOL commitEntered = gcvFALSE;
++ gctPOINTER pointer = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL config2D;
++ gctSIZE_T configSize;
++
++ gcmkHEADER_ARG("Hardware=0x%x Enable=%d", Hardware, Enable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ config2D = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_2D);
++
++ configSize = 4 * 4;
++
++ if (config2D)
++ {
++ configSize +=
++ /* Pipe Select. */
++ 4 * 4
++ /* Configure MMU States. */
++ + 4 * 4;
++ }
++
++ /* Convert logical address into physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, MtlbAddress, &config));
++
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, SafeAddress, &address));
++
++ if (address & 0x3F)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ switch (Mode)
++ {
++ case gcvMMU_MODE_1K:
++ if (config & 0x3FF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ case gcvMMU_MODE_4K:
++ if (config & 0xFFF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Hardware->kernel->command;
++
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, FromPower));
++ commitEntered = gcvTRUE;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, configSize, &pointer, &bufferSize
++ ));
++
++ buffer = pointer;
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1] = config;
++
++ buffer[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[3] = address;
++
++ if (config2D)
++ {
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ buffer[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[5] = 0x1;
++
++ buffer[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[7] = config;
++
++ buffer[8]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[9] = address;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ buffer[10]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[11] = 0x0;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Setup MMU: config=%08x, Safe Address=%08x\n.", config, address);
++
++ gcmkONERROR(gckCOMMAND_Execute(command, configSize));
++
++ if (FromPower == gcvFALSE)
++ {
++ /* Acquire global semaphore to suspend power management until MMU
++ ** is enabled. And acquired it before gckCOMMAND_ExitCommit to
++ ** make sure GPU keeps ON. */
++ gcmkONERROR(
++ gckOS_AcquireSemaphore(Hardware->os, Hardware->globalSemaphore));
++
++ acquired = gcvTRUE;
++ }
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, FromPower));
++ commitEntered = gcvFALSE;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "call gckCOMMAND_Stall to make sure the config is done.\n ");
++
++ gcmkONERROR(gckCOMMAND_Stall(command, FromPower));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Enable MMU through GCREG_MMU_CONTROL.");
++
++ /* Enable MMU. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0018C,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Enable) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))));
++
++ if (FromPower == gcvFALSE)
++ {
++ /* Relase global semaphore. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseSemaphore(Hardware->os, Hardware->globalSemaphore));
++
++ acquired = gcvFALSE;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "call gckCOMMAND_Stall to check MMU available.\n");
++
++ gcmkONERROR(gckCOMMAND_Stall(command, FromPower));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "The MMU is available.\n");
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return status;
++
++OnError:
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Hardware->kernel->command,
++ FromPower));
++ }
++
++ if (acquired)
++ {
++ gcmkVERIFY_OK(
++ gckOS_ReleaseSemaphore(Hardware->os, Hardware->globalSemaphore));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Index=%u Offset=%u", Hardware, Index, Offset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ *Address = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (Offset | (Index << 12)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle = 0;
++ gctINT retry, poll, pollCount;
++
++ gcmkHEADER_ARG("Hardware=0x%x Wait=%d", Hardware, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++
++ /* If we have to wait, try 100 polls per millisecond. */
++ pollCount = Wait ? 100 : 1;
++
++ /* At most, try for 1 second. */
++ for (retry = 0; retry < 1000; ++retry)
++ {
++ /* If we have to wait, try 100 polls per millisecond. */
++ for (poll = pollCount; poll > 0; --poll)
++ {
++ /* Read register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++ /* See if we have to wait for FE idle. */
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* FE is idle. */
++ break;
++ }
++ }
++
++ /* Check if we need to wait for FE and FE is busy. */
++ if (Wait && !(((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* Wait a little. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "%s: Waiting for idle: 0x%08X",
++ __FUNCTION__, idle);
++
++ gcmkVERIFY_OK(gckOS_Delay(Hardware->os, 1));
++ }
++ else
++ {
++ break;
++ }
++ }
++
++ /* Return idle to caller. */
++ *Data = idle;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32 pipe;
++ gctUINT32 flush = 0;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++ gctBOOL fcFlushStall;
++ gctUINT32 reserveBytes = 8;
++
++ gcmkHEADER_ARG("Hardware=0x%x Flush=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Flush, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get current pipe. */
++ pipe = Hardware->kernel->command->pipeSelect;
++
++ fcFlushStall
++ = ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 31:31) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))))
++ && (Flush == gcvFLUSH_ALL)
++ ;
++
++ if (fcFlushStall)
++ {
++ reserveBytes += 8;
++ }
++
++ /* Flush 3D color cache. */
++ if ((Flush & gcvFLUSH_COLOR) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ /* Flush 3D depth cache. */
++ if ((Flush & gcvFLUSH_DEPTH) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Flush 3D texture cache. */
++ if ((Flush & gcvFLUSH_TEXTURE) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++
++ /* Flush 2D cache. */
++ if ((Flush & gcvFLUSH_2D) && (pipe == 0x1))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ }
++
++ /* See if there is a valid flush. */
++ if (flush == 0)
++ {
++ if (Bytes != gcvNULL)
++ {
++ /* No bytes required. */
++ *Bytes = 0;
++ }
++ }
++
++ else
++ {
++ /* Copy to command queue. */
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < reserveBytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append LOAD_STATE to AQFlush. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1] = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical, flush);
++
++ if (fcFlushStall)
++ {
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[3] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical + 3, logical[3]);
++ }
++
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* bytes required. */
++ *Bytes = reserveBytes;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ )
++{
++#ifndef VIVANTE_NO_3D
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Enable=%d Compression=%d",
++ Hardware, Enable, Compression);
++
++ /* Only process if fast clear is available. */
++ if ((((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ if (Enable == -1)
++ {
++ /* Determine automatic value for fast clear. */
++ Enable = ((Hardware->identity.chipModel != gcv500)
++ || (Hardware->identity.chipRevision >= 3)
++ ) ? 1 : 0;
++ }
++
++ if (Compression == -1)
++ {
++ /* Determine automatic value for compression. */
++ Compression = Enable
++ & (((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) );
++ }
++
++ /* Read AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &debug));
++
++ /* Set fast clear bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++ if (
++ ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) ||
++ (Hardware->identity.chipModel >= gcv4000))
++ {
++ /* Set compression bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21))) | (((gctUINT32) ((gctUINT32) (Compression == 0) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21)));
++ }
++
++ /* Write back AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ debug));
++
++ /* Store fast clear and comprersison flags. */
++ Hardware->allowFastClear = Enable;
++ Hardware->allowCompression = Compression;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "FastClear=%d Compression=%d", Enable, Compression);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++}
++gcePOWER_FLAGS;
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++static gctCONST_STRING
++_PowerEnum(gceCHIPPOWERSTATE State)
++{
++ const gctCONST_STRING states[] =
++ {
++ gcmSTRING(gcvPOWER_ON),
++ gcmSTRING(gcvPOWER_OFF),
++ gcmSTRING(gcvPOWER_IDLE),
++ gcmSTRING(gcvPOWER_SUSPEND),
++ gcmSTRING(gcvPOWER_SUSPEND_ATPOWERON),
++ gcmSTRING(gcvPOWER_OFF_ATPOWERON),
++ gcmSTRING(gcvPOWER_IDLE_BROADCAST),
++ gcmSTRING(gcvPOWER_SUSPEND_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_RECOVERY),
++ gcmSTRING(gcvPOWER_ON_AUTO)
++ };
++
++ if ((State >= gcvPOWER_ON) && (State <= gcvPOWER_ON_AUTO))
++ {
++ return states[State - gcvPOWER_ON];
++ }
++
++ return "unknown";
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag, clock;
++ gctPOINTER buffer;
++ gctSIZE_T bytes, requested;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL broadcast = gcvFALSE;
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++ gctUINT32 process, thread;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL commandStarted = gcvFALSE;
++ gctBOOL isrStarted = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++ gctBOOL global = gcvFALSE;
++ gctBOOL globalAcquired = gcvFALSE;
++ gctBOOL configMmu = gcvFALSE;
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_RELEASE,
++ /* OFF */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ /* Clocks. */
++ static const gctUINT clocks[4] =
++ {
++ /* gcvPOWER_ON */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (64) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_OFF */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_IDLE */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_SUSPEND */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d(%s)",
++ State, _PowerEnum(State));
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->powerManagement == gcvFALSE)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ /* Before we grab locks see if this is actually a needed change */
++ if (State == Hardware->chipPowerState)
++ return gcvSTATUS_OK;
++
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 0);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Called from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ clock = clocks[State];
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if (State == gcvPOWER_ON)
++ {
++ clock = ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (Hardware->powerOnFscaleVal) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)));
++ }
++#endif
++
++ if (State == gcvPOWER_SUSPEND && Hardware->chipPowerState == gcvPOWER_OFF && broadcast)
++ {
++#if gcdPOWER_SUSNPEND_WHEN_IDLE
++ /* Do nothing */
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++#else
++ /* Clock should be on when switch power from off to suspend */
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) ;
++#endif
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE or SUSPEND. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Power Off GPU[%d] at %u [supposed to be at %u]",
++ Hardware->core, currentTime, Hardware->powerOffTime);
++ }
++
++ if (State == gcvPOWER_ON || State == gcvPOWER_OFF)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* If this is an internal power management, we have to check if we can grab
++ ** the global power semaphore. If we cannot, we have to wait until the
++ ** external world changes power management. */
++ if (!global)
++ {
++ /* Try to acquire the global semaphore. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Called from thread routine which should NEVER sleep.*/
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Release the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Releasing the power mutex.");
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ /* Wait for the semaphore. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Waiting for global semaphore.");
++ gcmkONERROR(gckOS_AcquireSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvTRUE;
++
++ /* Acquire the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Reacquiring the power mutex.");
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ mutexAcquired = gcvTRUE;
++
++ /* chipPowerState may be changed by external world during the time
++ ** we give up powerMutex, so updating flag now is necessary. */
++ flag = flags[Hardware->chipPowerState][State];
++
++ if (flag == 0)
++ {
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Error. */
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore again. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ else
++ {
++ if (State == gcvPOWER_OFF || State == gcvPOWER_SUSPEND || State == gcvPOWER_IDLE)
++ {
++ /* Acquire the global semaphore if it has not been acquired. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_OK)
++ {
++ globalAcquired = gcvTRUE;
++ }
++ else if (status != gcvSTATUS_TIMEOUT)
++ {
++ /* Other errors. */
++ gcmkONERROR(status);
++ }
++ /* Ignore gcvSTATUS_TIMEOUT and leave globalAcquired as gcvFALSE.
++ ** gcvSTATUS_TIMEOUT means global semaphore has already
++ ** been acquired before this operation, so even if we fail,
++ ** we should not release it in our error handling. It should be
++ ** released by the next successful global gcvPOWER_ON. */
++ }
++
++ /* Global power management can't be aborted, so sync with
++ ** proceeding last commit. */
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ for (;;)
++ {
++ /* Check if GPU is present and awake. */
++ status = _IsGPUPresent(Hardware);
++
++ /* Check if the GPU is not responding. */
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Turn off the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvFALSE, gcvFALSE));
++
++ Hardware->clockState = gcvFALSE;
++ Hardware->powerState = gcvFALSE;
++
++ /* Wait a little. */
++ gckOS_Delay(os, 1);
++
++ /* Turn on the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ /* We need to initialize the hardware and start the command
++ * processor. */
++ flag |= gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_START;
++ }
++ else
++ {
++ /* Test for error. */
++ gcmkONERROR(status);
++
++ /* Break out of loop. */
++ break;
++ }
++ }
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ gctBOOL idle;
++ gctINT32 atomValue;
++
++ /* For global operation, all pending commits have already been
++ ** blocked by globalSemaphore or powerSemaphore.*/
++ if (!global)
++ {
++ /* Check commit atom. */
++ gcmkONERROR(gckOS_AtomGet(os, command->atomCommit, &atomValue));
++
++ if (atomValue > 0)
++ {
++ /* Commits are pending - abort power management. */
++ status = broadcast ? gcvSTATUS_CHIP_NOT_READY
++ : gcvSTATUS_MORE_DATA;
++ goto OnError;
++ }
++ }
++
++ if (broadcast)
++ {
++ /* Check for idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Hardware, &idle));
++
++ if (!idle)
++ {
++ status = gcvSTATUS_CHIP_NOT_READY;
++ goto OnError;
++ }
++ }
++
++ else
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvTRUE));
++ commitEntered = gcvTRUE;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(command, requested));
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ commitEntered = gcvFALSE;
++
++ /* Wait to finish all commands. */
++ gcmkONERROR(gckCOMMAND_Stall(command, gcvTRUE));
++ }
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++ }
++
++ if (flag & gcvPOWER_FLAG_STOP)
++ {
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ /* Stop the Isr. */
++ if (Hardware->stopIsr)
++ {
++ gcmkONERROR(Hardware->stopIsr(Hardware->isrContext, Hardware->core));
++ }
++ }
++
++ /* Flush Cache before Power Off. */
++ if (flag & gcvPOWER_FLAG_POWER_OFF)
++ {
++ if (Hardware->clockState == gcvFALSE)
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ gcvTRUE,
++ gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++
++ if (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE)
++ {
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clocks[0]));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clocks[0])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++ }
++
++ gcmkONERROR(gckCOMMAND_Start(command));
++
++ gcmkONERROR(_FlushCache(Hardware, command));
++
++ gckOS_Delay(gcvNULL, 1);
++
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ flag |= gcvPOWER_FLAG_CLOCK_OFF;
++ }
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++ /* Only process this when hardware is enabled. */
++ if (Hardware->clockState && Hardware->powerState
++ /* Don't touch clock control if dynamic frequency scaling is available. */
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE
++ )
++ {
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ if (Hardware->identity.chipModel == gcv4000
++ && Hardware->identity.chipRevision == 0x5208)
++ {
++ clock &= ~2U;
++ }
++ }
++
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++ /* Initialize hardware. */
++ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(Hardware,
++ Hardware->allowFastClear,
++ Hardware->allowCompression));
++
++ /* Force the command queue to reload the next context. */
++ command->currContext = gcvNULL;
++
++ /* Need to config mmu after command start. */
++ configMmu = gcvTRUE;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++ if (flag & gcvPOWER_FLAG_START)
++ {
++ /* Start the command processor. */
++ gcmkONERROR(gckCOMMAND_Start(command));
++ commandStarted = gcvTRUE;
++
++ if (Hardware->startIsr)
++ {
++ /* Start the Isr. */
++ gcmkONERROR(Hardware->startIsr(Hardware->isrContext, Hardware->core));
++ isrStarted = gcvTRUE;
++ }
++
++ /* Set NEW MMU. */
++ if (Hardware->mmuVersion != 0 && configMmu)
++ {
++ gcmkONERROR(
++ gckHARDWARE_SetMMUv2(
++ Hardware,
++ gcvTRUE,
++ Hardware->kernel->mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Hardware->kernel->mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ gcvTRUE
++ ));
++ }
++ }
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++
++ if (global)
++ {
++ /* Verify global semaphore has been acquired already before
++ ** we release it.
++ ** If it was acquired, gckOS_TryAcquireSemaphore will return
++ ** gcvSTATUS_TIMEOUT and we release it. Otherwise, global
++ ** semaphore will be acquried now, but it still is released
++ ** immediately. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status != gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++#if gcdDVFS
++ if (State == gcvPOWER_ON && Hardware->kernel->dvfs)
++ {
++ gckDVFS_Start(Hardware->kernel->dvfs);
++ }
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commandStarted)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Stop(command, gcvFALSE));
++ }
++
++ if (isrStarted)
++ {
++ gcmkVERIFY_OK(Hardware->stopIsr(Hardware->isrContext, Hardware->core));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ }
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (globalAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagement = PowerManagement;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetGpuProfiler
++**
++** Configure GPU profiler function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL GpuProfiler
++** GOU Profiler State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->gpuProfiler = GpuProfiler;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ )
++{
++ gceSTATUS status;
++ gctUINT32 clock;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x FscaleValue=%d", Hardware, FscaleValue);
++
++ gcmkVERIFY_ARGUMENT(FscaleValue > 0 && FscaleValue <= 64);
++
++ gcmkONERROR(
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ Hardware->powerOnFscaleVal = FscaleValue;
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (FscaleValue) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ /* Restore all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ )
++{
++ *FscaleValue = Hardware->powerOnFscaleVal;
++ if ((gpu3DMinClock > 0) && (gpu3DMinClock <= 64) && (Hardware->core == gcvCORE_MAJOR))
++ *MinFscaleValue = gpu3DMinClock;
++ else
++ *MinFscaleValue = 1;
++ *MaxFscaleValue = 64;
++
++ return gcvSTATUS_OK;
++}
++
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle, address;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ *IsIdle = gcvTRUE;
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ *IsIdle = gcvFALSE;
++ }
++
++ else
++ {
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00664,
++ &address));
++
++ /* Test if address is inside the last WAIT/LINK sequence. */
++ if ((address >= Hardware->lastWaitLink)
++ && (address <= Hardware->lastWaitLink + 16)
++ )
++ {
++ /* FE is in last WAIT/LINK and the pipe is idle. */
++ *IsIdle = gcvTRUE;
++ }
++ else
++ {
++ /* FE is not in WAIT/LINK yet. */
++ *IsIdle = gcvFALSE;
++ }
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** Handy macros that will help in reading those debug registers.
++*/
++
++#define gcmkREAD_DEBUG_REGISTER(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &profiler->data))
++
++#define gcmkREAD_DEBUG_REGISTER_N(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &data))
++
++#define gcmkRESET_DEBUG_REGISTER(control, block) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 15))); \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 0)))
++
++/*******************************************************************************
++**
++** gckHARDWARE_ProfileEngine2D
++**
++** Read the profile registers available in the 2D engine and sets them in the
++** profile. The function will also reset the pixelsRendered counter every time.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** OPTIONAL gcs2D_PROFILE_PTR Profile
++** Pointer to a gcs2D_Profile structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ )
++{
++ gceSTATUS status;
++ gcs2D_PROFILE_PTR profiler = Profile;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Profile != gcvNULL)
++ {
++ /* Read the cycle count. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &Profile->cycleCount));
++
++ /* Read pixels rendered by 2D engine. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &profiler->pixelsRendered));
++
++ /* Reset counter. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++ gctUINT i, clock;
++ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn;
++ gctUINT32 totalRead, totalWrite;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ if(Reset){
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++ }
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));}
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));}
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));}
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));}
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));}
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));}
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ if(Reset){ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));}
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++#define gcmkUPDATE_PROFILE_DATA(data) \
++ profilerHistroy->data += profiler->data
++
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = Hardware->kernel->command;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os, command->mutexContextSeq, gcvINFINITE
++ ));
++
++ /* Read the counters. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ profiler, &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++
++ if (Reset)
++ {
++ /* Reset counters. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os, command->mutexContextSeq
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = &Context->latestProfiler;
++ gcsPROFILER_COUNTERS * profilerHistroy = &Context->histroyProfiler;
++ gctUINT i, clock;
++ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn;
++ gctUINT32 totalRead, totalWrite;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 temp;
++ gctBOOL needResetShader = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x Context=0x%x", Hardware, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ chipModel = Hardware->identity.chipModel;
++ chipRevision = Hardware->identity.chipRevision;
++ if (chipModel == gcv2000 || (chipModel == gcv2100 && chipRevision == 0x5118))
++ {
++ needResetShader = gcvTRUE;
++ }
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuTotalCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuIdleCyclesCounter);
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++ gcmkUPDATE_PROFILE_DATA(gpuTotalRead64BytesPerFrame);
++ gcmkUPDATE_PROFILE_DATA(gpuTotalWrite64BytesPerFrame);
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_depth_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_depth_pipe);
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++
++
++
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->ps_inst_counter;
++ profiler->ps_inst_counter -= Context->prevPSInstCount;
++ Context->prevPSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(ps_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_pixel_counter;
++ profiler->rendered_pixel_counter -= Context->prevPSPixelCount;
++ Context->prevPSPixelCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_pixel_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vs_inst_counter;
++ profiler->vs_inst_counter -= Context->prevVSInstCount;
++ Context->prevVSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vs_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_vertice_counter;
++ profiler->rendered_vertice_counter -= Context->prevVSVertexCount;
++ Context->prevVSVertexCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_vertice_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_branch_inst_counter;
++ profiler->vtx_branch_inst_counter -= Context->prevVSBranchInstCount;
++ Context->prevVSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_texld_inst_counter;
++ profiler->vtx_texld_inst_counter -= Context->prevVSTexInstCount;
++ Context->prevVSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_branch_inst_counter;
++ profiler->pxl_branch_inst_counter -= Context->prevPSBranchInstCount;
++ Context->prevPSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_texld_inst_counter;
++ profiler->pxl_texld_inst_counter -= Context->prevPSTexInstCount;
++ Context->prevPSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_vtx_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_output_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_depth_clipped_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_trivial_rejected_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_culled_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_triangle_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_lines_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_pixel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_quad_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_quad_count_after_early_z);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_primitive_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_pipe_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_prefetch_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_bilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_trilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_discarded_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_in_8B_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_hit_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_IP);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_write_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_read_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_data_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ Hardware->powerBaseAddress +
++ 0x00104,
++ 0x00000000));
++
++ control = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++
++ /* Disable pulse-eater. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++ gctUINT32 process, thread;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->identity.chipRevision < 0x4600)
++ {
++ /* Not supported - we need the isolation bit. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ status = gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread))
++ {
++ /* No way to recovery from a error in power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ mutexAcquired = gcvTRUE;
++ }
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(
++ gckOS_AcquireSemaphore(Hardware->os, command->powerSemaphore));
++ acquired = gcvTRUE;
++ }
++
++ if ((Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_IDLE)
++ )
++ {
++ /* Stop the command processor. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvTRUE));
++ }
++
++ /* Stop isr, we will start it again when power on GPU. */
++ if (Hardware->stopIsr)
++ {
++ gcmkONERROR(Hardware->stopIsr(Hardware->isrContext, Hardware->core));
++ }
++
++ /* Hardware reset. */
++ status = gckOS_ResetGPU(Hardware->os, Hardware->core);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Soft reset. */
++ gcmkONERROR(_ResetGPU(Hardware, Hardware->os, Hardware->core));
++ }
++
++ /* Force an OFF to ON power switch. */
++ Hardware->chipPowerState = gcvPOWER_OFF;
++
++ gcmkONERROR(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the power management semaphore. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseSemaphore(Hardware->os, command->powerSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++ }
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Test if we have a new Memory Controller. */
++ if (((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))))
++ {
++ /* No base address required. */
++ *BaseAddress = 0;
++ }
++ else
++ {
++ /* Get the base address from the OS. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, BaseAddress));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ )
++{
++ gctBOOL need = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x State=0x%08x", Hardware, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(NeedBase != gcvNULL);
++
++ /* Make sure this is a load state. */
++ if (((((gctUINT32) (State)) >> (0 ? 31:27) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))))
++ {
++#ifndef VIVANTE_NO_3D
++ /* Get the state address. */
++ switch ((((((gctUINT32) (State)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) ))
++ {
++ case 0x0596:
++ case 0x0597:
++ case 0x0599:
++ case 0x059A:
++ case 0x05A9:
++ /* These states need a TRUE physical address. */
++ need = gcvTRUE;
++ break;
++ }
++#else
++ /* 2D addresses don't need a base address. */
++#endif
++ }
++
++ /* Return the flag. */
++ *NeedBase = need;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedBase=%d", *NeedBase);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Hardware=0x%x, StartIsr=0x%x, StopIsr=0x%x, Context=0x%x",
++ Hardware, StartIsr, StopIsr, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (StartIsr == gcvNULL ||
++ StopIsr == gcvNULL ||
++ Context == gcvNULL)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ Hardware->startIsr = StartIsr;
++ Hardware->stopIsr = StopIsr;
++ Hardware->isrContext = Context;
++
++ /* Success. */
++ gcmkFOOTER();
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Compose
++**
++** Start a composition.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ )
++{
++#ifndef VIVANTE_NO_3D
++ gceSTATUS status;
++ gctUINT32_PTR triggerState;
++
++ gcmkHEADER_ARG("Hardware=0x%x Physical=0x%x Logical=0x%x"
++ " Offset=%d Size=%d EventID=%d",
++ Hardware, Physical, Logical, Offset, Size, EventID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(((Size + 8) & 63) == 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Program the trigger state. */
++ triggerState = (gctUINT32_PTR) ((gctUINT8_PTR) Logical + Offset + Size);
++ triggerState[0] = 0x0C03;
++ triggerState[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16))) | (((gctUINT32) ((gctUINT32) (EventID) & ((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16)))
++ ;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Hardware->os, ProcessID, gcvNULL,
++ Physical, Logical, Offset + Size
++ ));
++#endif
++
++ /* Start composition. */
++ gcmkONERROR(gckOS_WriteRegisterEx(
++ Hardware->os, Hardware->core, 0x00554,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ /* Return the status. */
++ return gcvSTATUS_NOT_SUPPORTED;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_IsFeatureAvailable
++**
++** Verifies whether the specified feature is available in hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gceFEATURE Feature
++** Feature to be verified.
++*/
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ )
++{
++ gctBOOL available;
++
++ gcmkHEADER_ARG("Hardware=0x%x Feature=%d", Hardware, Feature);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Only features needed by common kernel logic added here. */
++ switch (Feature)
++ {
++ case gcvFEATURE_END_EVENT:
++ /*available = gcmVERIFYFIELDVALUE(Hardware->identity.chipMinorFeatures2,
++ GC_MINOR_FEATURES2, END_EVENT, AVAILABLE
++ );*/
++ available = gcvFALSE;
++ break;
++ case gcvFEATURE_MC20:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))));
++ break;
++ case gcvFEATURE_DYNAMIC_FREQUENCY_SCALING:
++ /* This feature doesn't apply for 2D cores. */
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 14:14) & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))))
++ && ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_2D:
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_3D:
++#ifndef VIVANTE_NO_3D
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++#else
++ available = gcvFALSE;
++#endif
++ break;
++
++ case gcvFEATURE_HALTI2:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
++ break;
++
++ default:
++ gcmkFATAL("Invalid feature has been requested.");
++ available = gcvFALSE;
++ }
++
++ /* Return result. */
++ gcmkFOOTER_ARG("%d", available ? gcvSTATUS_TRUE : gcvSTATUS_OK);
++ return available ? gcvSTATUS_TRUE : gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpMMUException
++**
++** Dump the MMU debug info on an MMU exception.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ )
++{
++#if !gcdPOWER_SUSNPEND_WHEN_IDLE && !gcdPOWEROFF_TIMEOUT
++ gctUINT32 mmu, mmuStatus, address, i;
++#if gcdDEBUG
++ gctUINT32 mtlb, stlb, offset;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkPRINT("GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ Hardware->core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** MMU ERROR DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00188,
++ &mmuStatus));
++
++ gcmkPRINT(" MMU status = 0x%08X\n", mmuStatus);
++
++ for (i = 0; i < 4; i += 1)
++ {
++ mmu = mmuStatus & 0xF;
++ mmuStatus >>= 4;
++
++ if (mmu == 0)
++ {
++ continue;
++ }
++
++ switch (mmu)
++ {
++ case 1:
++ gcmkPRINT(" MMU%d: slave not present\n", i);
++ break;
++
++ case 2:
++ gcmkPRINT(" MMU%d: page not present\n", i);
++ break;
++
++ case 3:
++ gcmkPRINT(" MMU%d: write violation\n", i);
++ break;
++
++ default:
++ gcmkPRINT(" MMU%d: unknown state\n", i);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00190 + i * 4,
++ &address));
++
++ mtlb = (address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ stlb = (address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++ offset = address & gcdMMU_OFFSET_4K_MASK;
++
++ gcmkPRINT(" MMU%d: exception address = 0x%08X\n", i, address);
++
++ gcmkPRINT(" MTLB entry = %d\n", mtlb);
++
++ gcmkPRINT(" STLB entry = %d\n", stlb);
++
++ gcmkPRINT(" Offset = 0x%08X (%d)\n", offset, offset);
++
++ gckMMU_DumpPageTableEntry(Hardware->kernel->mmu, address);
++
++ }
++
++ gcmkFOOTER_NO();
++#else
++ /* If clock could be off automatically, we can't read mmu debug
++ ** register here; build driver with gcdPOWER_SUSPEND_WHEN_IDLE = 0
++ ** and gcdPOWEROFF_TIMEOUT = 0 to make it safe to read mmu register. */
++ gcmkPRINT("[galcore] %s(%d): MMU Exception!", __FUNCTION__, __LINE__);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpGPUState
++**
++** Dump the GPU debug registers.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ )
++{
++ static gctCONST_STRING _cmdState[] =
++ {
++ "PAR_IDLE_ST", "PAR_DEC_ST", "PAR_ADR0_ST", "PAR_LOAD0_ST",
++ "PAR_ADR1_ST", "PAR_LOAD1_ST", "PAR_3DADR_ST", "PAR_3DCMD_ST",
++ "PAR_3DCNTL_ST", "PAR_3DIDXCNTL_ST", "PAR_INITREQDMA_ST",
++ "PAR_DRAWIDX_ST", "PAR_DRAW_ST", "PAR_2DRECT0_ST", "PAR_2DRECT1_ST",
++ "PAR_2DDATA0_ST", "PAR_2DDATA1_ST", "PAR_WAITFIFO_ST", "PAR_WAIT_ST",
++ "PAR_LINK_ST", "PAR_END_ST", "PAR_STALL_ST"
++ };
++
++ static gctCONST_STRING _cmdDmaState[] =
++ {
++ "CMD_IDLE_ST", "CMD_START_ST", "CMD_REQ_ST", "CMD_END_ST"
++ };
++
++ static gctCONST_STRING _cmdFetState[] =
++ {
++ "FET_IDLE_ST", "FET_RAMVALID_ST", "FET_VALID_ST"
++ };
++
++ static gctCONST_STRING _reqDmaState[] =
++ {
++ "REQ_IDLE_ST", "REQ_WAITIDX_ST", "REQ_CAL_ST"
++ };
++
++ static gctCONST_STRING _calState[] =
++ {
++ "CAL_IDLE_ST", "CAL_LDADR_ST", "CAL_IDXCALC_ST"
++ };
++
++ static gctCONST_STRING _veReqState[] =
++ {
++ "VER_IDLE_ST", "VER_CKCACHE_ST", "VER_MISS_ST"
++ };
++
++ static gcsiDEBUG_REGISTERS _dbgRegs[] =
++ {
++ { "RA", 0x474, 16, 0x448, 16, 0x12344321 },
++ { "TX", 0x474, 24, 0x44C, 16, 0x12211221 },
++ { "FE", 0x470, 0, 0x450, 16, 0xBABEF00D },
++ { "PE", 0x470, 16, 0x454, 16, 0xBABEF00D },
++ { "DE", 0x470, 8, 0x458, 16, 0xBABEF00D },
++ { "SH", 0x470, 24, 0x45C, 16, 0xDEADBEEF },
++ { "PA", 0x474, 0, 0x460, 16, 0x0000AAAA },
++ { "SE", 0x474, 8, 0x464, 16, 0x5E5E5E5E },
++ { "MC", 0x478, 0, 0x468, 16, 0x12345678 },
++ { "HI", 0x478, 8, 0x46C, 16, 0xAAAAAAAA }
++ };
++
++ static gctUINT32 _otherRegs[] =
++ {
++ 0x040, 0x044, 0x04C, 0x050, 0x054, 0x058, 0x05C, 0x060,
++ 0x43c, 0x440, 0x444, 0x414,
++ };
++
++ gceSTATUS status;
++ gckKERNEL kernel;
++ gctUINT32 idle, axi;
++ gctUINT32 dmaAddress1, dmaAddress2;
++ gctUINT32 dmaState1, dmaState2;
++ gctUINT32 dmaLow, dmaHigh;
++ gctUINT32 cmdState, cmdDmaState, cmdFetState;
++ gctUINT32 dmaReqState, calState, veReqState;
++ gctUINT i;
++ gctUINT pipe, pixelPipes;
++ gctUINT32 control, oldControl;
++ gckOS os = Hardware->os;
++ gceCORE core = Hardware->core;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ kernel = Hardware->kernel;
++
++ gcmkPRINT_N(12, "GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ pixelPipes = Hardware->identity.pixelPipes
++ ? Hardware->identity.pixelPipes
++ : 1;
++
++ /* Reset register values. */
++ idle = axi =
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 =
++ dmaLow = dmaHigh = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkONERROR(_VerifyDMA(
++ os, core, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++ cmdState = dmaState2 & 0x1F;
++ cmdDmaState = (dmaState2 >> 8) & 0x03;
++ cmdFetState = (dmaState2 >> 10) & 0x03;
++ dmaReqState = (dmaState2 >> 12) & 0x03;
++ calState = (dmaState2 >> 14) & 0x03;
++ veReqState = (dmaState2 >> 16) & 0x03;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x004, &idle));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x00C, &axi));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x668, &dmaLow));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x66C, &dmaHigh));
++
++ gcmkPRINT_N(0, "**************************\n");
++ gcmkPRINT_N(0, "*** GPU STATE DUMP ***\n");
++ gcmkPRINT_N(0, "**************************\n");
++
++ gcmkPRINT_N(4, " axi = 0x%08X\n", axi);
++
++ gcmkPRINT_N(4, " idle = 0x%08X\n", idle);
++ if ((idle & 0x00000001) == 0) gcmkPRINT_N(0, " FE not idle\n");
++ if ((idle & 0x00000002) == 0) gcmkPRINT_N(0, " DE not idle\n");
++ if ((idle & 0x00000004) == 0) gcmkPRINT_N(0, " PE not idle\n");
++ if ((idle & 0x00000008) == 0) gcmkPRINT_N(0, " SH not idle\n");
++ if ((idle & 0x00000010) == 0) gcmkPRINT_N(0, " PA not idle\n");
++ if ((idle & 0x00000020) == 0) gcmkPRINT_N(0, " SE not idle\n");
++ if ((idle & 0x00000040) == 0) gcmkPRINT_N(0, " RA not idle\n");
++ if ((idle & 0x00000080) == 0) gcmkPRINT_N(0, " TX not idle\n");
++ if ((idle & 0x00000100) == 0) gcmkPRINT_N(0, " VG not idle\n");
++ if ((idle & 0x00000200) == 0) gcmkPRINT_N(0, " IM not idle\n");
++ if ((idle & 0x00000400) == 0) gcmkPRINT_N(0, " FP not idle\n");
++ if ((idle & 0x00000800) == 0) gcmkPRINT_N(0, " TS not idle\n");
++ if ((idle & 0x80000000) != 0) gcmkPRINT_N(0, " AXI low power mode\n");
++
++ if (
++ (dmaAddress1 == dmaAddress2)
++ && (dmaState1 == dmaState2)
++ )
++ {
++ gcmkPRINT_N(0, " DMA appears to be stuck at this address:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ }
++ else
++ {
++ if (dmaAddress1 == dmaAddress2)
++ {
++ gcmkPRINT_N(0, " DMA address is constant, but state is changing:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState2);
++ }
++ else
++ {
++ gcmkPRINT_N(0, " DMA is running; known addresses are:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress2);
++ }
++ }
++ gcmkPRINT_N(4, " dmaLow = 0x%08X\n", dmaLow);
++ gcmkPRINT_N(4, " dmaHigh = 0x%08X\n", dmaHigh);
++ gcmkPRINT_N(4, " dmaState = 0x%08X\n", dmaState2);
++ gcmkPRINT_N(8, " command state = %d (%s)\n", cmdState, _cmdState [cmdState]);
++ gcmkPRINT_N(8, " command DMA state = %d (%s)\n", cmdDmaState, _cmdDmaState[cmdDmaState]);
++ gcmkPRINT_N(8, " command fetch state = %d (%s)\n", cmdFetState, _cmdFetState[cmdFetState]);
++ gcmkPRINT_N(8, " DMA request state = %d (%s)\n", dmaReqState, _reqDmaState[dmaReqState]);
++ gcmkPRINT_N(8, " cal state = %d (%s)\n", calState, _calState [calState]);
++ gcmkPRINT_N(8, " VE request state = %d (%s)\n", veReqState, _veReqState [veReqState]);
++
++ /* Record control. */
++ gckOS_ReadRegisterEx(os, core, 0x0, &oldControl);
++
++ for (pipe = 0; pipe < pixelPipes; pipe++)
++ {
++ gcmkPRINT_N(4, " Debug registers of pipe[%d]:\n", pipe);
++
++ /* Switch pipe. */
++ gckOS_ReadRegisterEx(os, core, 0x0, &control);
++ control &= ~(0xF << 20);
++ control |= (pipe << 20);
++ gckOS_WriteRegisterEx(os, core, 0x0, control);
++
++ for (i = 0; i < gcmCOUNTOF(_dbgRegs); i += 1)
++ {
++ gcmkONERROR(_DumpDebugRegisters(os, core, &_dbgRegs[i]));
++ }
++
++ gcmkPRINT_N(0, " Other Registers:\n");
++ for (i = 0; i < gcmCOUNTOF(_otherRegs); i += 1)
++ {
++ gctUINT32 read;
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, _otherRegs[i], &read));
++ gcmkPRINT_N(12, " [0x%04X] 0x%08X\n", _otherRegs[i], read);
++ }
++ }
++
++ if (kernel->hardware->identity.chipFeatures & (1 << 4))
++ {
++ gctUINT32 read0, read1, write;
++
++ read0 = read1 = write = 0;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x43C, &read0));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x440, &read1));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x444, &write));
++
++ gcmkPRINT_N(4, " read0 = 0x%08X\n", read0);
++ gcmkPRINT_N(4, " read1 = 0x%08X\n", read1);
++ gcmkPRINT_N(4, " write = 0x%08X\n", write);
++ }
++
++ /* Restore control. */
++ gckOS_WriteRegisterEx(os, core, 0x0, oldControl);
++
++ /* dump stack. */
++ gckOS_DumpCallStack(os);
++
++OnError:
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++
++#if gcdFRAME_DB
++static gceSTATUS
++gckHARDWARE_ReadPerformanceRegister(
++ IN gckHARDWARE Hardware,
++ IN gctUINT PerformanceAddress,
++ IN gctUINT IndexAddress,
++ IN gctUINT IndexShift,
++ IN gctUINT Index,
++ OUT gctUINT32_PTR Value
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x PerformanceAddress=0x%x IndexAddress=0x%x "
++ "IndexShift=%u Index=%u",
++ Hardware, PerformanceAddress, IndexAddress, IndexShift,
++ Index);
++
++ /* Write the index. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ IndexAddress,
++ Index << IndexShift));
++
++ /* Read the register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ PerformanceAddress,
++ Value));
++
++ /* Test for reset. */
++ if (Index == 15)
++ {
++ /* Index another register to get out of reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, IndexAddress, 0));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=0x%x", *Value);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ )
++{
++ gceSTATUS status;
++ gctUINT i, clock;
++ gcsHAL_FRAME_INFO info;
++#if gcdFRAME_DB_RESET
++ gctUINT reset;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Get profile tick. */
++ gcmkONERROR(gckOS_GetProfileTick(&info.ticks));
++
++ /* Read SH counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 4,
++ &info.shaderCycles));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 9,
++ &info.vsInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 12,
++ &info.vsTextureCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 7,
++ &info.psInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 14,
++ &info.psTextureCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read PA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 3,
++ &info.vertexCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 4,
++ &info.primitiveCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 7,
++ &info.rejectedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 8,
++ &info.culledPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 6,
++ &info.clippedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 5,
++ &info.outPrimitives));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 15,
++ &reset));
++#endif
++
++ /* Read RA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 3,
++ &info.inPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 11,
++ &info.culledQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 1,
++ &info.totalQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 2,
++ &info.quadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 0,
++ &info.totalPixelCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Read TX counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 0,
++ &info.bilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 1,
++ &info.trilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 8,
++ &info.txHitCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 9,
++ &info.txMissCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 6,
++ &info.txBytes8));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* Read cycle registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &info.cycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &info.idleCycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &info.mcCycles[i]));
++
++ /* Read bandwidth registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0005C,
++ &info.readRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &info.readBytes8[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00050,
++ &info.writeRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &info.writeBytes8[i]));
++
++ /* Read PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 0,
++ &info.colorKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 2,
++ &info.colorDrawn[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 1,
++ &info.depthKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 3,
++ &info.depthDrawn[i]));
++ }
++
++ /* Zero out remaning reserved counters. */
++ for (; i < 8; ++i)
++ {
++ info.readBytes8[i] = 0;
++ info.writeBytes8[i] = 0;
++ info.cycles[i] = 0;
++ info.idleCycles[i] = 0;
++ info.mcCycles[i] = 0;
++ info.readRequests[i] = 0;
++ info.writeRequests[i] = 0;
++ info.colorKilled[i] = 0;
++ info.colorDrawn[i] = 0;
++ info.depthKilled[i] = 0;
++ info.depthDrawn[i] = 0;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Reset cycle and bandwidth counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 1));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ 0));
++
++#if gcdFRAME_DB_RESET
++ /* Reset PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Copy to user. */
++ gcmkONERROR(gckOS_CopyToUserData(Hardware->os,
++ &info,
++ FrameInfo,
++ gcmSIZEOF(info)));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++#if gcdDVFS
++#define READ_FROM_EATER1 0
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ )
++{
++ gctUINT32 debug1;
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Load != gcvNULL);
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00110,
++ Load));
++#if READ_FROM_EATER1
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00134,
++ Load));
++#endif
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00114,
++ &debug1));
++
++ /* Patch result of 0x110 with result of 0x114. */
++ if ((debug1 & 0xFF) == 1)
++ {
++ *Load &= ~0xFF;
++ *Load |= 1;
++ }
++
++ if (((debug1 & 0xFF00) >> 8) == 1)
++ {
++ *Load &= ~(0xFF << 8);
++ *Load |= 1 << 8;
++ }
++
++ if (((debug1 & 0xFF0000) >> 16) == 1)
++ {
++ *Load &= ~(0xFF << 16);
++ *Load |= 1 << 16;
++ }
++
++ if (((debug1 & 0xFF000000) >> 24) == 1)
++ {
++ *Load &= ~(0xFF << 24);
++ *Load |= 1 << 24;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 Frequency
++ )
++{
++ gceSTATUS status;
++ gctUINT32 period;
++ gctUINT32 eater;
++
++#if READ_FROM_EATER1
++ gctUINT32 period1;
++ gctUINT32 eater1;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%X Frequency=%d", Hardware, Frequency);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ period = 0;
++
++ while((64 << period) < (gcdDVFS_ANAYLSE_WINDOW * Frequency * 1000) )
++ {
++ period++;
++ }
++
++#if READ_FROM_EATER1
++ /*
++ * Peroid = F * 1000 * 1000 / (60 * 16 * 1024);
++ */
++ period1 = Frequency * 6250 / 6114;
++#endif
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ /* Get current configure. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &eater));
++
++ /* Change peroid. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (eater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (period) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))));
++
++#if READ_FROM_EATER1
++ /* Config eater1. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ &eater1));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ ((((gctUINT32) (eater1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16))) | (((gctUINT32) ((gctUINT32) (period1) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16)))));
++#endif
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 data;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "DVFS Configure=0x%X",
++ data);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ data));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.h 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,136 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_h_
++#define __gc_hal_kernel_hardware_h_
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_hardware_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* gckHARDWARE object. */
++struct _gckHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gctKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Pointer to gctOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Chip characteristics. */
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++ gctBOOL allowFastClear;
++ gctBOOL allowCompression;
++ gctUINT32 powerBaseAddress;
++ gctBOOL extraEventStates;
++
++ /* Big endian */
++ gctBOOL bigEndian;
++
++ /* Chip status */
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gctUINT32 lastWaitLink;
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER globalSemaphore;
++
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++
++ gctUINT32 mmuVersion;
++
++ /* Type */
++ gceHARDWARE_TYPE type;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++ gctPOINTER pageTableDirty;
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ /* FSCALE_VAL when gcvPOWER_ON. */
++ gctUINT32 powerOnFscaleVal;
++#endif
++
++#if gcdLINK_QUEUE_SIZE
++ struct _gckLINKQUEUE linkQueue;
++#endif
++
++ gctBOOL powerManagement;
++ gctBOOL gpuProfiler;
++};
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ );
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ );
++
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ );
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/config linux-linaro-stable-mx6/drivers/mxc/gpu-viv/config
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/config 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/config 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,38 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2013 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++ARCH_TYPE ?= arm
++SDK_DIR ?= $(AQROOT)/build/sdk
++USE_3D_VG ?= 1
++FORCE_ALL_VIDEO_MEMORY_CACHED ?= 0
++NONPAGED_MEMORY_CACHEABLE ?= 0
++NONPAGED_MEMORY_BUFFERABLE ?= 1
++CACHE_FUNCTION_UNIMPLEMENTED ?= 0
++VIVANTE_ENABLE_VG ?= 0
++NO_USER_DIRECT_ACCESS_FROM_KERNEL ?= 1
++VIVANTE_NO_3D ?= 0
++ENABLE_OUTER_CACHE_PATCH ?= 1
++USE_BANK_ALIGNMENT ?= 1
++BANK_BIT_START ?= 13
++BANK_BIT_END ?= 15
++BANK_CHANNEL_BIT ?= 12
++ENABLE_GPU_CLOCK_BY_DRIVER = 1
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,3881 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++/*******************************************************************************
++***** Version Signature *******************************************************/
++
++#define _gcmTXT2STR(t) #t
++#define gcmTXT2STR(t) _gcmTXT2STR(t)
++const char * _VERSION = "\n\0$VERSION$"
++ gcmTXT2STR(gcvVERSION_MAJOR) "."
++ gcmTXT2STR(gcvVERSION_MINOR) "."
++ gcmTXT2STR(gcvVERSION_PATCH) ":"
++ gcmTXT2STR(gcvVERSION_BUILD) "$\n";
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++#define gcmDEFINE2TEXT(d) #d
++gctCONST_STRING _DispatchText[] =
++{
++ gcmDEFINE2TEXT(gcvHAL_QUERY_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_CHIP_IDENTITY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_NON_PAGED_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_NON_PAGED_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_CONTIGUOUS_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_MAP_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNMAP_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_MAP_USER_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNMAP_USER_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_LOCK_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNLOCK_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_EVENT_COMMIT),
++ gcmDEFINE2TEXT(gcvHAL_USER_SIGNAL),
++ gcmDEFINE2TEXT(gcvHAL_SIGNAL),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_DATA),
++ gcmDEFINE2TEXT(gcvHAL_COMMIT),
++ gcmDEFINE2TEXT(gcvHAL_STALL),
++ gcmDEFINE2TEXT(gcvHAL_READ_REGISTER),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_REGISTER),
++ gcmDEFINE2TEXT(gcvHAL_GET_PROFILE_SETTING),
++ gcmDEFINE2TEXT(gcvHAL_SET_PROFILE_SETTING),
++ gcmDEFINE2TEXT(gcvHAL_READ_ALL_PROFILE_REGISTERS),
++#if VIVANTE_PROFILER_PERDRAW
++ gcmDEFINE2TEXT(gcvHAL_READ_PROFILER_REGISTER_SETTING),
++#endif
++ gcmDEFINE2TEXT(gcvHAL_PROFILE_REGISTERS_2D),
++ gcmDEFINE2TEXT(gcvHAL_SET_POWER_MANAGEMENT_STATE),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_POWER_MANAGEMENT_STATE),
++ gcmDEFINE2TEXT(gcvHAL_GET_BASE_ADDRESS),
++ gcmDEFINE2TEXT(gcvHAL_SET_IDLE),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_KERNEL_SETTINGS),
++ gcmDEFINE2TEXT(gcvHAL_RESET),
++ gcmDEFINE2TEXT(gcvHAL_MAP_PHYSICAL),
++ gcmDEFINE2TEXT(gcvHAL_DEBUG),
++ gcmDEFINE2TEXT(gcvHAL_CACHE),
++ gcmDEFINE2TEXT(gcvHAL_TIMESTAMP),
++ gcmDEFINE2TEXT(gcvHAL_DATABASE),
++ gcmDEFINE2TEXT(gcvHAL_VERSION),
++ gcmDEFINE2TEXT(gcvHAL_CHIP_INFO),
++ gcmDEFINE2TEXT(gcvHAL_ATTACH),
++ gcmDEFINE2TEXT(gcvHAL_DETACH)
++};
++#endif
++
++#if gcdENABLE_RECOVERY
++void
++_ResetFinishFunction(
++ gctPOINTER Data
++ )
++{
++ gckKERNEL kernel = (gckKERNEL)Data;
++
++ gckOS_AtomSet(kernel->os, kernel->resetAtom, 0);
++}
++#endif
++
++/*******************************************************************************
++**
++** gckKERNEL_Construct
++**
++** Construct a new gckKERNEL object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** IN gctPOINTER Context
++** Pointer to a driver defined context.
++**
++** IN gckDB SharedDB,
++** Pointer to a shared DB.
++**
++** OUTPUT:
++**
++** gckKERNEL * Kernel
++** Pointer to a variable that will hold the pointer to the gckKERNEL
++** object.
++*/
++
++gceSTATUS
++gckKERNEL_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Context,
++ IN gckDB SharedDB,
++ OUT gckKERNEL * Kernel
++ )
++{
++ gckKERNEL kernel = gcvNULL;
++ gceSTATUS status;
++ gctSIZE_T i;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++
++ /* Allocate the gckKERNEL object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckKERNEL),
++ &pointer));
++
++ kernel = pointer;
++
++ /* Zero the object pointers. */
++ kernel->hardware = gcvNULL;
++ kernel->command = gcvNULL;
++ kernel->eventObj = gcvNULL;
++ kernel->mmu = gcvNULL;
++#if gcdDVFS
++ kernel->dvfs = gcvNULL;
++#endif
++
++ /* Initialize the gckKERNEL object. */
++ kernel->object.type = gcvOBJ_KERNEL;
++ kernel->os = Os;
++ kernel->core = Core;
++
++
++ if (SharedDB == gcvNULL)
++ {
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckDB),
++ &pointer));
++
++ kernel->db = pointer;
++ kernel->dbCreated = gcvTRUE;
++ kernel->db->freeDatabase = gcvNULL;
++ kernel->db->freeRecord = gcvNULL;
++ kernel->db->dbMutex = gcvNULL;
++ kernel->db->lastDatabase = gcvNULL;
++ kernel->db->idleTime = 0;
++ kernel->db->lastIdle = 0;
++ kernel->db->lastSlowdown = 0;
++
++ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i)
++ {
++ kernel->db->db[i] = gcvNULL;
++ }
++
++ /* Construct a database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->dbMutex));
++
++ /* Construct a id-pointer database. */
++ gcmkONERROR(gckKERNEL_CreateIntegerDatabase(kernel, &kernel->db->pointerDatabase));
++
++ /* Construct a id-pointer database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->pointerDatabaseMutex));
++ }
++ else
++ {
++ kernel->db = SharedDB;
++ kernel->dbCreated = gcvFALSE;
++ }
++
++ for (i = 0; i < gcmCOUNTOF(kernel->timers); ++i)
++ {
++ kernel->timers[i].startTime = 0;
++ kernel->timers[i].stopTime = 0;
++ }
++
++ kernel->timeOut = gcdGPU_TIMEOUT;
++
++ /* Save context. */
++ kernel->context = Context;
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ kernel->virtualBufferHead =
++ kernel->virtualBufferTail = gcvNULL;
++
++ gcmkONERROR(
++ gckOS_CreateMutex(Os, (gctPOINTER)&kernel->virtualBufferLock));
++#endif
++
++ /* Construct atom holding number of clients. */
++ kernel->atomClients = gcvNULL;
++ gcmkONERROR(gckOS_AtomConstruct(Os, &kernel->atomClients));
++
++#if gcdENABLE_VG
++ kernel->vg = gcvNULL;
++
++ if (Core == gcvCORE_VG)
++ {
++ /* Construct the gckMMU object. */
++ gcmkONERROR(
++ gckVGKERNEL_Construct(Os, Context, kernel, &kernel->vg));
++ }
++ else
++#endif
++ {
++ /* Construct the gckHARDWARE object. */
++ gcmkONERROR(
++ gckHARDWARE_Construct(Os, kernel->core, &kernel->hardware));
++
++ /* Set pointer to gckKERNEL object in gckHARDWARE object. */
++ kernel->hardware->kernel = kernel;
++
++ /* Initialize the hardware. */
++ gcmkONERROR(
++ gckHARDWARE_InitializeHardware(kernel->hardware));
++
++ /* Construct the gckCOMMAND object. */
++ gcmkONERROR(
++ gckCOMMAND_Construct(kernel, &kernel->command));
++
++ /* Construct the gckEVENT object. */
++ gcmkONERROR(
++ gckEVENT_Construct(kernel, &kernel->eventObj));
++
++ /* Construct the gckMMU object. */
++ gcmkONERROR(
++ gckMMU_Construct(kernel, gcdMMU_SIZE, &kernel->mmu));
++
++#if gcdENABLE_RECOVERY
++ gcmkONERROR(
++ gckOS_AtomConstruct(Os, &kernel->resetAtom));
++
++ gcmkVERIFY_OK(
++ gckOS_CreateTimer(Os,
++ (gctTIMERFUNCTION)_ResetFinishFunction,
++ (gctPOINTER)kernel,
++ &kernel->resetFlagClearTimer));
++ kernel->resetTimeStamp = 0;
++#endif
++
++#if gcdDVFS
++ if (gckHARDWARE_IsFeatureAvailable(kernel->hardware,
++ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING))
++ {
++ gcmkONERROR(gckDVFS_Construct(kernel->hardware, &kernel->dvfs));
++ gcmkONERROR(gckDVFS_Start(kernel->dvfs));
++ }
++#endif
++ }
++
++ spin_lock_init(&kernel->irq_lock);
++
++#if VIVANTE_PROFILER
++ /* Initialize profile setting */
++ kernel->profileEnable = gcvFALSE;
++ kernel->profileCleanRegister = gcvTRUE;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gcmkONERROR(gckOS_CreateSyncTimeline(Os, &kernel->timeline));
++#endif
++
++ /* Return pointer to the gckKERNEL object. */
++ *Kernel = kernel;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (kernel != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Core != gcvCORE_VG)
++#endif
++ {
++ if (kernel->eventObj != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckEVENT_Destroy(kernel->eventObj));
++ }
++
++ if (kernel->command != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Destroy(kernel->command));
++ }
++
++ if (kernel->hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(kernel->hardware->os,
++ kernel->hardware->core,
++ gcvFALSE,
++ gcvFALSE));
++ gcmkVERIFY_OK(gckHARDWARE_Destroy(kernel->hardware));
++ }
++ }
++
++ if (kernel->atomClients != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, kernel->atomClients));
++ }
++
++#if gcdENABLE_RECOVERY
++ if (kernel->resetAtom != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, kernel->resetAtom));
++ }
++
++ if (kernel->resetFlagClearTimer)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, kernel->resetFlagClearTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, kernel->resetFlagClearTimer));
++ }
++#endif
++
++ if (kernel->dbCreated && kernel->db != gcvNULL)
++ {
++ if (kernel->db->dbMutex != gcvNULL)
++ {
++ /* Destroy the database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->db->dbMutex));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel->db));
++ }
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ if (kernel->virtualBufferLock != gcvNULL)
++ {
++ /* Destroy the virtual command buffer mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->virtualBufferLock));
++ }
++#endif
++
++#if gcdDVFS
++ if (kernel->dvfs)
++ {
++ gcmkVERIFY_OK(gckDVFS_Stop(kernel->dvfs));
++ gcmkVERIFY_OK(gckDVFS_Destroy(kernel->dvfs));
++ }
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ if (kernel->timeline)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Os, kernel->timeline));
++ }
++#endif
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel));
++ }
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Destroy
++**
++** Destroy an gckKERNEL object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Destroy(
++ IN gckKERNEL Kernel
++ )
++{
++ gctSIZE_T i;
++ gcsDATABASE_PTR database, databaseNext;
++ gcsDATABASE_RECORD_PTR record, recordNext;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->debugMutex));
++#endif
++
++ /* Destroy the database. */
++ if (Kernel->dbCreated)
++ {
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ if (Kernel->db->db[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckKERNEL_DestroyProcessDB(Kernel, Kernel->db->db[i]->processID));
++ }
++ }
++
++ /* Free all databases. */
++ for (database = Kernel->db->freeDatabase;
++ database != gcvNULL;
++ database = databaseNext)
++ {
++ databaseNext = database->next;
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, database));
++ }
++
++ if (Kernel->db->lastDatabase != gcvNULL)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel->db->lastDatabase));
++ }
++
++ /* Free all database records. */
++ for (record = Kernel->db->freeRecord; record != gcvNULL; record = recordNext)
++ {
++ recordNext = record->next;
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record));
++ }
++
++ /* Destroy the database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->dbMutex));
++
++
++ /* Destroy id-pointer database. */
++ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Kernel->db->pointerDatabase));
++
++ /* Destroy id-pointer database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++#if gcdENABLE_VG
++ if (Kernel->vg)
++ {
++ gcmkVERIFY_OK(gckVGKERNEL_Destroy(Kernel->vg));
++ }
++ else
++#endif
++ {
++ /* Destroy the gckMMU object. */
++ gcmkVERIFY_OK(gckMMU_Destroy(Kernel->mmu));
++
++ /* Destroy the gckCOMMNAND object. */
++ gcmkVERIFY_OK(gckCOMMAND_Destroy(Kernel->command));
++
++ /* Destroy the gckEVENT object. */
++ gcmkVERIFY_OK(gckEVENT_Destroy(Kernel->eventObj));
++
++ /* Destroy the gckHARDWARE object. */
++ gcmkVERIFY_OK(gckHARDWARE_Destroy(Kernel->hardware));
++
++#if gcdENABLE_RECOVERY
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Kernel->resetAtom));
++
++ if (Kernel->resetFlagClearTimer)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Kernel->os, Kernel->resetFlagClearTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Kernel->os, Kernel->resetFlagClearTimer));
++ }
++#endif
++ }
++
++ /* Detsroy the client atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Kernel->atomClients));
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->virtualBufferLock));
++#endif
++
++#if gcdDVFS
++ if (Kernel->dvfs)
++ {
++ gcmkVERIFY_OK(gckDVFS_Stop(Kernel->dvfs));
++ gcmkVERIFY_OK(gckDVFS_Destroy(Kernel->dvfs));
++ }
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Kernel->os, Kernel->timeline));
++#endif
++
++ /* Mark the gckKERNEL object as unknown. */
++ Kernel->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckKERNEL object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/oom.h>
++#include <linux/sched.h>
++#include <linux/notifier.h>
++
++extern struct task_struct *lowmem_deathpending;
++static unsigned long lowmem_deathpending_timeout;
++
++static int force_contiguous_lowmem_shrink(IN gckKERNEL Kernel)
++{
++ struct task_struct *p;
++ struct task_struct *selected = NULL;
++ int tasksize;
++ int ret = -1;
++ int min_adj = 0;
++ int selected_tasksize = 0;
++ int selected_oom_adj;
++ /*
++ * If we already have a death outstanding, then
++ * bail out right away; indicating to vmscan
++ * that we have nothing further to offer on
++ * this pass.
++ *
++ */
++ if (lowmem_deathpending &&
++ time_before_eq(jiffies, lowmem_deathpending_timeout))
++ return 0;
++ selected_oom_adj = min_adj;
++
++ read_lock(&tasklist_lock);
++ for_each_process(p) {
++ struct mm_struct *mm;
++ struct signal_struct *sig;
++ gcuDATABASE_INFO info;
++ int oom_adj;
++
++ task_lock(p);
++ mm = p->mm;
++ sig = p->signal;
++ if (!mm || !sig) {
++ task_unlock(p);
++ continue;
++ }
++ oom_adj = sig->oom_adj;
++ if (oom_adj < min_adj) {
++ task_unlock(p);
++ continue;
++ }
++
++ tasksize = 0;
++ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_VIDEO_MEMORY, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_CONTIGUOUS, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++
++ task_unlock(p);
++
++ if (tasksize <= 0)
++ continue;
++
++ gckOS_Print("<gpu> pid %d (%s), adj %d, size %d \n", p->pid, p->comm, oom_adj, tasksize);
++
++ if (selected) {
++ if (oom_adj < selected_oom_adj)
++ continue;
++ if (oom_adj == selected_oom_adj &&
++ tasksize <= selected_tasksize)
++ continue;
++ }
++ selected = p;
++ selected_tasksize = tasksize;
++ selected_oom_adj = oom_adj;
++ }
++ if (selected) {
++ gckOS_Print("<gpu> send sigkill to %d (%s), adj %d, size %d\n",
++ selected->pid, selected->comm,
++ selected_oom_adj, selected_tasksize);
++ lowmem_deathpending = selected;
++ lowmem_deathpending_timeout = jiffies + HZ;
++ force_sig(SIGKILL, selected);
++ ret = 0;
++ }
++ read_unlock(&tasklist_lock);
++ return ret;
++}
++
++#endif
++
++/*******************************************************************************
++**
++** _AllocateMemory
++**
++** Private function to walk all required memory pools to allocate the requested
++** amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++static gceSTATUS
++_AllocateMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gcePOOL pool;
++ gceSTATUS status;
++ gckVIDMEM videoMemory;
++ gctINT loopCount;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctBOOL tileStatusInVirtual;
++ gctBOOL forceContiguous = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x *Pool=%d Bytes=%lu Alignment=%lu Type=%d",
++ Kernel, *Pool, Bytes, Alignment, Type);
++
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes != 0);
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++_AllocateMemory_Retry:
++#endif
++ /* Get initial pool. */
++ switch (pool = *Pool)
++ {
++ case gcvPOOL_DEFAULT_FORCE_CONTIGUOUS:
++ forceContiguous = gcvTRUE;
++ case gcvPOOL_DEFAULT:
++ case gcvPOOL_LOCAL:
++ pool = gcvPOOL_LOCAL_INTERNAL;
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_UNIFIED:
++ pool = gcvPOOL_SYSTEM;
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_CONTIGUOUS:
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_DEFAULT_FORCE_CONTIGUOUS_CACHEABLE:
++ pool = gcvPOOL_CONTIGUOUS;
++ loopCount = 1;
++ forceContiguous = gcvTRUE;
++ break;
++
++ default:
++ loopCount = 1;
++ break;
++ }
++
++ while (loopCount-- > 0)
++ {
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ /* Create a gcuVIDMEM_NODE for virtual memory. */
++ gcmkONERROR(
++ gckVIDMEM_ConstructVirtual(Kernel, gcvFALSE, Bytes, &node));
++
++ /* Success. */
++ break;
++ }
++
++ else
++ if (pool == gcvPOOL_CONTIGUOUS)
++ {
++#if gcdCONTIGUOUS_SIZE_LIMIT
++ if (Bytes > gcdCONTIGUOUS_SIZE_LIMIT && forceContiguous == gcvFALSE)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ }
++ else
++#endif
++ {
++ /* Create a gcuVIDMEM_NODE from contiguous memory. */
++ status = gckVIDMEM_ConstructVirtual(Kernel, gcvTRUE, Bytes, &node);
++ }
++
++ if (gcmIS_SUCCESS(status) || forceContiguous == gcvTRUE)
++ {
++ /* Memory allocated. */
++ if(node && forceContiguous == gcvTRUE)
++ {
++ gctUINT32 physAddr=0;
++ gctUINT32 baseAddress = 0;
++
++ gckOS_LockPages(Kernel->os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ gcvFALSE,
++ &node->Virtual.logical,
++ &node->Virtual.pageCount);
++
++ /* Convert logical address into a physical address. */
++ gckOS_GetPhysicalAddress(Kernel->os, node->Virtual.logical, &physAddr);
++
++ gckOS_UnlockPages(Kernel->os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ node->Virtual.logical);
++
++ gckOS_GetBaseAddress(Kernel->os, &baseAddress);
++
++ gcmkASSERT(physAddr >= baseAddress);
++
++ /* Subtract baseAddress to get a GPU address used for programming. */
++ physAddr -= baseAddress;
++
++ if((physAddr & 0x80000000) || ((physAddr + Bytes) & 0x80000000))
++ {
++ gckOS_Print("gpu virtual memory 0x%x cannot be allocated for external use !\n", physAddr);
++
++ gckVIDMEM_Free(node);
++
++ node = gcvNULL;
++ }
++ }
++
++ break;
++ }
++ }
++
++ else
++ {
++ /* Get pointer to gckVIDMEM object for pool. */
++#if gcdUSE_VIDMEM_PER_PID
++ gctUINT32 pid;
++ gckOS_GetProcessID(&pid);
++
++ status = gckKERNEL_GetVideoMemoryPoolPid(Kernel, pool, pid, &videoMemory);
++ if (status == gcvSTATUS_NOT_FOUND)
++ {
++ /* Create VidMem pool for this process. */
++ status = gckKERNEL_CreateVideoMemoryPoolPid(Kernel, pool, pid, &videoMemory);
++ }
++#else
++ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory);
++#endif
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Allocate memory. */
++ status = gckVIDMEM_AllocateLinear(videoMemory,
++ Bytes,
++ Alignment,
++ Type,
++ &node);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Memory allocated. */
++ node->VidMem.pool = pool;
++ break;
++ }
++ }
++ }
++
++ if (pool == gcvPOOL_LOCAL_INTERNAL)
++ {
++ /* Advance to external memory. */
++ pool = gcvPOOL_LOCAL_EXTERNAL;
++ }
++
++ else
++ if (pool == gcvPOOL_LOCAL_EXTERNAL)
++ {
++ /* Advance to contiguous system memory. */
++ pool = gcvPOOL_SYSTEM;
++ }
++
++ else
++ if (pool == gcvPOOL_SYSTEM)
++ {
++ /* Advance to contiguous memory. */
++ pool = gcvPOOL_CONTIGUOUS;
++ }
++
++ else
++ if (pool == gcvPOOL_CONTIGUOUS)
++ {
++ tileStatusInVirtual =
++ gckHARDWARE_IsFeatureAvailable(Kernel->hardware,
++ gcvFEATURE_MC20);
++
++ if (Type == gcvSURF_TILE_STATUS && tileStatusInVirtual != gcvTRUE)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Advance to virtual memory. */
++ pool = gcvPOOL_VIRTUAL;
++ }
++
++ else
++ {
++ /* Out of pools. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++ if(forceContiguous == gcvTRUE)
++ {
++ if(force_contiguous_lowmem_shrink(Kernel) == 0)
++ {
++ /* Sleep 1 millisecond. */
++ gckOS_Delay(gcvNULL, 1);
++ goto _AllocateMemory_Retry;
++ }
++ }
++#endif
++ /* Nothing allocated. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Return node and pool used for allocation. */
++ *Node = node;
++ *Pool = pool;
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Pool=%d *Node=0x%x", *Pool, *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Dispatch
++**
++** Dispatch a command received from the user HAL layer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL FromUser
++** whether the call is from the user space.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++
++gceSTATUS
++gckKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctSIZE_T bytes;
++ gcuVIDMEM_NODE_PTR node;
++ gctBOOL locked = gcvFALSE;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctPOINTER logical = gcvNULL;
++ gctPOINTER info = gcvNULL;
++ gckCONTEXT context = gcvNULL;
++ gctUINT32 address;
++ gctUINT32 processID;
++ gckKERNEL kernel = Kernel;
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++ gctBOOL asynchronous;
++ gctPOINTER paddr = gcvNULL;
++#if !USE_NEW_LINUX_SIGNAL
++ gctSIGNAL signal;
++#endif
++
++ gcmkHEADER_ARG("Kernel=0x%x FromUser=%d Interface=0x%x",
++ Kernel, FromUser, Interface);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "Dispatching command %d (%s)",
++ Interface->command, _DispatchText[Interface->command]);
++#endif
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gckOS_AcquireMutex(Kernel->os, Kernel->debugMutex, gcvINFINITE);
++#endif
++
++ /* Get the current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Kernel, processID, &cache));
++#endif
++
++ /* Dispatch on command. */
++ switch (Interface->command)
++ {
++ case gcvHAL_GET_BASE_ADDRESS:
++ /* Get base address. */
++ gcmkONERROR(
++ gckOS_GetBaseAddress(Kernel->os,
++ &Interface->u.GetBaseAddress.baseAddress));
++ break;
++
++ case gcvHAL_QUERY_VIDEO_MEMORY:
++ /* Query video memory size. */
++ gcmkONERROR(gckKERNEL_QueryVideoMemory(Kernel, Interface));
++ break;
++
++ case gcvHAL_QUERY_CHIP_IDENTITY:
++ /* Query chip identity. */
++ gcmkONERROR(
++ gckHARDWARE_QueryChipIdentity(
++ Kernel->hardware,
++ &Interface->u.QueryChipIdentity));
++ break;
++
++ case gcvHAL_MAP_MEMORY:
++ physical = gcmINT2PTR(Interface->u.MapMemory.physical);
++
++ /* Map memory. */
++ gcmkONERROR(
++ gckKERNEL_MapMemory(Kernel,
++ physical,
++ (gctSIZE_T) Interface->u.MapMemory.bytes,
++ &logical));
++
++ Interface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_MAP_MEMORY,
++ logical,
++ physical,
++ (gctSIZE_T) Interface->u.MapMemory.bytes));
++ break;
++
++ case gcvHAL_UNMAP_MEMORY:
++ physical = gcmINT2PTR(Interface->u.UnmapMemory.physical);
++
++ /* Unmap memory. */
++ gcmkONERROR(
++ gckKERNEL_UnmapMemory(Kernel,
++ physical,
++ (gctSIZE_T) Interface->u.UnmapMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical)));
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_MAP_MEMORY,
++ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical)));
++ break;
++
++ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY:
++ bytes = (gctSIZE_T) Interface->u.AllocateNonPagedMemory.bytes;
++
++ /* Allocate non-paged memory. */
++ gcmkONERROR(
++ gckOS_AllocateNonPagedMemory(
++ Kernel->os,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateNonPagedMemory.bytes = bytes;
++ Interface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_NON_PAGED,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateNonPagedMemory.physical),
++ bytes));
++
++ break;
++
++ case gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER:
++#if gcdVIRTUAL_COMMAND_BUFFER
++ bytes = (gctSIZE_T) Interface->u.AllocateVirtualCommandBuffer.bytes;
++
++ gcmkONERROR(
++ gckKERNEL_AllocateVirtualCommandBuffer(
++ Kernel,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateVirtualCommandBuffer.bytes = bytes;
++ Interface->u.AllocateVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateVirtualCommandBuffer.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_COMMAND_BUFFER,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateVirtualCommandBuffer.physical),
++ bytes));
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ physical = gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical);
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ /* Free non-paged memory. */
++ gcmkONERROR(
++ gckOS_FreeNonPagedMemory(Kernel->os,
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ physical,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_NON_PAGED,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical),
++ Interface->u.FreeNonPagedMemory.bytes));
++#endif
++
++ gcmRELEASE_NAME(Interface->u.FreeNonPagedMemory.physical);
++
++ break;
++
++ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY:
++ bytes = (gctSIZE_T) Interface->u.AllocateContiguousMemory.bytes;
++
++ /* Allocate contiguous memory. */
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Kernel->os,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateContiguousMemory.bytes = bytes;
++ Interface->u.AllocateContiguousMemory.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateContiguousMemory.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.AllocateContiguousMemory.logical),
++ &Interface->u.AllocateContiguousMemory.address));
++
++ gcmkVERIFY_OK(gckKERNEL_AddProcessDB(
++ Kernel,
++ processID, gcvDB_CONTIGUOUS,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateContiguousMemory.physical),
++ bytes));
++
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ physical = gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical);
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical)));
++
++ /* Free contiguous memory. */
++ gcmkONERROR(
++ gckOS_FreeContiguous(Kernel->os,
++ physical,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_CONTIGUOUS,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical),
++ Interface->u.FreeContiguousMemory.bytes));
++#endif
++
++ gcmRELEASE_NAME(Interface->u.FreeContiguousMemory.physical);
++
++ break;
++
++ case gcvHAL_ALLOCATE_VIDEO_MEMORY:
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++
++ break;
++
++ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY:
++ /* Allocate memory. */
++ gcmkONERROR(
++ _AllocateMemory(Kernel,
++ &Interface->u.AllocateLinearVideoMemory.pool,
++ Interface->u.AllocateLinearVideoMemory.bytes,
++ Interface->u.AllocateLinearVideoMemory.alignment,
++ Interface->u.AllocateLinearVideoMemory.type,
++ &node));
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ bytes = node->VidMem.bytes;
++ }
++ else
++ {
++ bytes = node->Virtual.bytes;
++ }
++
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ node,
++ gcvNULL,
++ bytes));
++
++ /* Get the node. */
++ Interface->u.AllocateLinearVideoMemory.node = gcmPTR_TO_UINT64(node);
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(Interface->u.FreeVideoMemory.node);
++#ifdef __QNXNTO__
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM
++ && node->VidMem.logical != gcvNULL)
++ {
++ gcmkONERROR(
++ gckKERNEL_UnmapVideoMemory(Kernel,
++ node->VidMem.logical,
++ processID,
++ node->VidMem.bytes));
++ node->VidMem.logical = gcvNULL;
++ }
++#endif
++ /* Free video memory. */
++ gcmkONERROR(
++ gckVIDMEM_Free(node));
++
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ node));
++
++ break;
++
++ case gcvHAL_LOCK_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(Interface->u.LockVideoMemory.node);
++
++ /* Lock video memory. */
++ gcmkONERROR(
++ gckVIDMEM_Lock(Kernel,
++ node,
++ Interface->u.LockVideoMemory.cacheable,
++ &Interface->u.LockVideoMemory.address));
++
++ locked = gcvTRUE;
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Map video memory address into user space. */
++#ifdef __QNXNTO__
++ if (node->VidMem.logical == gcvNULL)
++ {
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemory(Kernel,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ processID,
++ node->VidMem.bytes,
++ &node->VidMem.logical));
++ }
++ gcmkASSERT(node->VidMem.logical != gcvNULL);
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->VidMem.logical);
++#else
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemory(Kernel,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ &logical));
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(logical);
++#endif
++ }
++ else
++ {
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->Virtual.logical);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++
++#if gcdSECURE_USER
++ /* Return logical address as physical address. */
++ Interface->u.LockVideoMemory.address =
++ Interface->u.LockVideoMemory.memory;
++#endif
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_LOCKED,
++ node,
++ gcvNULL,
++ 0));
++
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ /* Unlock video memory. */
++ node = gcmUINT64_TO_PTR(Interface->u.UnlockVideoMemory.node);
++
++#if gcdSECURE_USER
++ /* Save node information before it disappears. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ logical = gcvNULL;
++ bytes = 0;
++ }
++ else
++ {
++ logical = node->Virtual.logical;
++ bytes = node->Virtual.bytes;
++ }
++#endif
++
++ /* Unlock video memory. */
++ gcmkONERROR(
++ gckVIDMEM_Unlock(Kernel,
++ node,
++ Interface->u.UnlockVideoMemory.type,
++ &Interface->u.UnlockVideoMemory.asynchroneous));
++
++#if gcdSECURE_USER
++ /* Flush the translation cache for virtual surfaces. */
++ if (logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(Kernel,
++ cache,
++ logical,
++ bytes));
++ }
++#endif
++ if (Interface->u.UnlockVideoMemory.asynchroneous == gcvFALSE)
++ {
++ /* There isn't a event to unlock this node, remove record now */
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_LOCKED,
++ node));
++ }
++ break;
++
++ case gcvHAL_EVENT_COMMIT:
++ /* Commit an event queue. */
++ gcmkONERROR(
++ gckEVENT_Commit(Kernel->eventObj,
++ gcmUINT64_TO_PTR(Interface->u.Event.queue)));
++ break;
++
++ case gcvHAL_COMMIT:
++ /* Commit a command and context buffer. */
++ gcmkONERROR(
++ gckCOMMAND_Commit(Kernel->command,
++ Interface->u.Commit.context ?
++ gcmNAME_TO_PTR(Interface->u.Commit.context) : gcvNULL,
++ gcmUINT64_TO_PTR(Interface->u.Commit.commandBuffer),
++ gcmUINT64_TO_PTR(Interface->u.Commit.delta),
++ gcmUINT64_TO_PTR(Interface->u.Commit.queue),
++ processID));
++ break;
++
++ case gcvHAL_STALL:
++ /* Stall the command queue. */
++ gcmkONERROR(gckCOMMAND_Stall(Kernel->command, gcvFALSE));
++ break;
++
++ case gcvHAL_MAP_USER_MEMORY:
++ /* Map user memory to DMA. */
++ gcmkONERROR(
++ gckOS_MapUserMemory(Kernel->os,
++ Kernel->core,
++ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory),
++ Interface->u.MapUserMemory.physical,
++ (gctSIZE_T) Interface->u.MapUserMemory.size,
++ &info,
++ &Interface->u.MapUserMemory.address));
++
++ Interface->u.MapUserMemory.info = gcmPTR_TO_NAME(info);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Interface->u.MapUserMemory.info),
++ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory),
++ (gctSIZE_T) Interface->u.MapUserMemory.size));
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ address = Interface->u.UnmapUserMemory.address;
++ info = gcmNAME_TO_PTR(Interface->u.UnmapUserMemory.info);
++
++ /* Unmap user memory. */
++ gcmkONERROR(
++ gckOS_UnmapUserMemory(Kernel->os,
++ Kernel->core,
++ gcmUINT64_TO_PTR(Interface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) Interface->u.UnmapUserMemory.size,
++ info,
++ address));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.UnmapUserMemory.memory),
++ Interface->u.UnmapUserMemory.size));
++#endif
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Interface->u.UnmapUserMemory.info)));
++
++ gcmRELEASE_NAME(Interface->u.UnmapUserMemory.info);
++
++ break;
++
++#if !USE_NEW_LINUX_SIGNAL
++ case gcvHAL_USER_SIGNAL:
++ /* Dispatch depends on the user signal subcommands. */
++ switch(Interface->u.UserSignal.command)
++ {
++ case gcvUSER_SIGNAL_CREATE:
++ /* Create a signal used in the user space. */
++ gcmkONERROR(
++ gckOS_CreateUserSignal(Kernel->os,
++ Interface->u.UserSignal.manualReset,
++ &Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_DESTROY:
++ /* Destroy the signal. */
++ gcmkONERROR(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++ break;
++
++ case gcvUSER_SIGNAL_SIGNAL:
++ /* Signal the signal. */
++ gcmkONERROR(
++ gckOS_SignalUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.state));
++ break;
++
++ case gcvUSER_SIGNAL_WAIT:
++#if gcdGPU_TIMEOUT
++ if (Interface->u.UserSignal.wait == gcvINFINITE)
++ {
++ gckHARDWARE hardware;
++ gctUINT32 timer = 0;
++
++ for(;;)
++ {
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ gcdGPU_ADVANCETIMER);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(
++ gckOS_SignalQueryHardware(Kernel->os,
++ (gctSIGNAL)(gctUINTPTR_T)Interface->u.UserSignal.id,
++ &hardware));
++
++ if (hardware)
++ {
++ /* This signal is bound to a hardware,
++ ** so the timeout is limited by gcdGPU_TIMEOUT.
++ */
++ timer += gcdGPU_ADVANCETIMER;
++ }
++
++ if (timer >= gcdGPU_TIMEOUT)
++ {
++ gcmkONERROR(
++ gckOS_Broadcast(Kernel->os,
++ hardware,
++ gcvBROADCAST_GPU_STUCK));
++
++ timer = 0;
++
++ /* If a few process try to reset GPU, only one
++ ** of them can do the real reset, other processes
++ ** still need to wait for this signal is triggered,
++ ** which menas reset is finished.
++ */
++ continue;
++ }
++ }
++ else
++ {
++ /* Bail out on other error. */
++ gcmkONERROR(status);
++
++ /* Wait for signal successfully. */
++ break;
++ }
++ }
++ }
++ else
++#endif
++ {
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.wait);
++ }
++
++ break;
++
++ case gcvUSER_SIGNAL_MAP:
++ gcmkONERROR(
++ gckOS_MapSignal(Kernel->os,
++ (gctSIGNAL)(gctUINTPTR_T)Interface->u.UserSignal.id,
++ (gctHANDLE)(gctUINTPTR_T)processID,
++ &signal));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_UNMAP:
++ /* Destroy the signal. */
++ gcmkONERROR(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++ break;
++
++ default:
++ /* Invalid user signal command. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ break;
++#endif
++
++ case gcvHAL_SET_POWER_MANAGEMENT_STATE:
++ /* Set the power management state. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(
++ Kernel->hardware,
++ Interface->u.SetPowerManagement.state));
++ break;
++
++ case gcvHAL_QUERY_POWER_MANAGEMENT_STATE:
++ /* Chip is not idle. */
++ Interface->u.QueryPowerManagement.isIdle = gcvFALSE;
++
++ /* Query the power management state. */
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(
++ Kernel->hardware,
++ &Interface->u.QueryPowerManagement.state));
++
++ /* Query the idle state. */
++ gcmkONERROR(
++ gckHARDWARE_QueryIdle(Kernel->hardware,
++ &Interface->u.QueryPowerManagement.isIdle));
++ break;
++
++ case gcvHAL_READ_REGISTER:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++
++ gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE);
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ /* Read a register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(
++ Kernel->os,
++ Kernel->core,
++ Interface->u.ReadRegisterData.address,
++ &Interface->u.ReadRegisterData.data));
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ }
++#else
++ /* No access from user land to read registers. */
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_WRITE_REGISTER:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++
++ gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE);
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ /* Write a register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Kernel->os,
++ Kernel->core,
++ Interface->u.WriteRegisterData.address,
++ Interface->u.WriteRegisterData.data));
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ Interface->u.WriteRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ }
++#else
++ /* No access from user land to write registers. */
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_READ_ALL_PROFILE_REGISTERS:
++#if VIVANTE_PROFILER && VIVANTE_PROFILER_CONTEXT
++ /* Read profile data according to the context. */
++ gcmkONERROR(
++ gckHARDWARE_QueryContextProfile(
++ Kernel->hardware,
++ Kernel->profileCleanRegister,
++ gcmNAME_TO_PTR(Interface->u.RegisterProfileData.context),
++ &Interface->u.RegisterProfileData.counters));
++#elif VIVANTE_PROFILER
++ /* Read all 3D profile registers. */
++ gcmkONERROR(
++ gckHARDWARE_QueryProfileRegisters(
++ Kernel->hardware,
++ Kernel->profileCleanRegister,
++ &Interface->u.RegisterProfileData.counters));
++#else
++ status = gcvSTATUS_OK;
++#endif
++ break;
++
++ case gcvHAL_PROFILE_REGISTERS_2D:
++#if VIVANTE_PROFILER
++ /* Read all 2D profile registers. */
++ gcmkONERROR(
++ gckHARDWARE_ProfileEngine2D(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.RegisterProfileData2D.hwProfile2D)));
++#else
++ status = gcvSTATUS_OK;
++#endif
++ break;
++
++ case gcvHAL_GET_PROFILE_SETTING:
++#if VIVANTE_PROFILER
++ /* Get profile setting */
++ Interface->u.GetProfileSetting.enable = Kernel->profileEnable;
++#endif
++
++ status = gcvSTATUS_OK;
++ break;
++ case gcvHAL_SET_PROFILE_SETTING:
++#if VIVANTE_PROFILER
++ /* Set profile setting */
++ if(Kernel->hardware->gpuProfiler)
++ Kernel->profileEnable = Interface->u.SetProfileSetting.enable;
++ else
++ {
++ status = gcvSTATUS_NOT_SUPPORTED;
++ break;
++ }
++#endif
++
++ status = gcvSTATUS_OK;
++ break;
++
++#if VIVANTE_PROFILER_PERDRAW
++ case gcvHAL_READ_PROFILER_REGISTER_SETTING:
++ #if VIVANTE_PROFILER
++ Kernel->profileCleanRegister = Interface->u.SetProfilerRegisterClear.bclear;
++ #endif
++ status = gcvSTATUS_OK;
++ break;
++#endif
++
++ case gcvHAL_QUERY_KERNEL_SETTINGS:
++ /* Get kernel settings. */
++ gcmkONERROR(
++ gckKERNEL_QuerySettings(Kernel,
++ &Interface->u.QueryKernelSettings.settings));
++ break;
++
++ case gcvHAL_RESET:
++ /* Reset the hardware. */
++ gckKERNEL_Recovery(Kernel);
++ break;
++
++ case gcvHAL_DEBUG:
++ /* Set debug level and zones. */
++ if (Interface->u.Debug.set)
++ {
++ gckOS_SetDebugLevel(Interface->u.Debug.level);
++ gckOS_SetDebugZones(Interface->u.Debug.zones,
++ Interface->u.Debug.enable);
++ }
++
++ if (Interface->u.Debug.message[0] != '\0')
++ {
++ /* Print a message to the debugger. */
++ if (Interface->u.Debug.type == gcvMESSAGE_TEXT)
++ {
++ gckOS_CopyPrint(Interface->u.Debug.message);
++ }
++ else
++ {
++ gckOS_DumpBuffer(Kernel->os,
++ Interface->u.Debug.message,
++ Interface->u.Debug.messageSize,
++ gceDUMP_BUFFER_FROM_USER,
++ gcvTRUE);
++ }
++ }
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_DUMP_GPU_STATE:
++ /* Dump GPU state */
++ {
++ gceCHIPPOWERSTATE power;
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ Interface->u.ReadRegisterData.data = 1;
++ gcmkVERIFY_OK(
++ gckHARDWARE_DumpGPUState(Kernel->hardware));
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gcmkVERIFY_OK(
++ gckCOMMAND_DumpExecutingBuffer(Kernel->command));
++#endif
++ }
++ else
++ {
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ }
++ break;
++
++ case gcvHAL_DUMP_EVENT:
++ /* Dump GPU event */
++ gcmkVERIFY_OK(gckEVENT_Dump(Kernel->eventObj));
++
++ /* Dump Process DB. */
++ gcmkVERIFY_OK(gckKERNEL_DumpProcessDB(Kernel));
++ break;
++
++ case gcvHAL_CACHE:
++ node = gcmUINT64_TO_PTR(Interface->u.Cache.node);
++ if (node == gcvNULL)
++ {
++ /* FIXME Surface wrap some memory which is not allocated by us,
++ ** So we don't have physical address to handle outer cache, ignore it*/
++ status = gcvSTATUS_OK;
++ break;
++ }
++ else if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Video memory has no physical handles. */
++ physical = gcvNULL;
++ }
++ else
++ {
++ /* Grab physical handle. */
++ physical = node->Virtual.physical;
++ }
++
++ logical = gcmUINT64_TO_PTR(Interface->u.Cache.logical);
++ bytes = (gctSIZE_T) Interface->u.Cache.bytes;
++ switch(Interface->u.Cache.operation)
++ {
++ case gcvCACHE_FLUSH:
++ /* Clean and invalidate the cache. */
++ status = gckOS_CacheFlush(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++ case gcvCACHE_CLEAN:
++ /* Clean the cache. */
++ status = gckOS_CacheClean(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++ case gcvCACHE_INVALIDATE:
++ /* Invalidate the cache. */
++ status = gckOS_CacheInvalidate(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++
++ case gcvCACHE_MEMORY_BARRIER:
++ status = gckOS_MemoryBarrier(Kernel->os,
++ logical);
++ break;
++ default:
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ /* Check for invalid timer. */
++ if ((Interface->u.TimeStamp.timer >= gcmCOUNTOF(Kernel->timers))
++ || (Interface->u.TimeStamp.request != 2))
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Return timer results and reset timer. */
++ {
++ gcsTIMER_PTR timer = &(Kernel->timers[Interface->u.TimeStamp.timer]);
++ gctUINT64 timeDelta = 0;
++
++ if (timer->stopTime < timer->startTime )
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW);
++ }
++
++ timeDelta = timer->stopTime - timer->startTime;
++
++ /* Check truncation overflow. */
++ Interface->u.TimeStamp.timeDelta = (gctINT32) timeDelta;
++ /*bit0~bit30 is available*/
++ if (timeDelta>>31)
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW);
++ }
++
++ status = gcvSTATUS_OK;
++ }
++ break;
++
++ case gcvHAL_DATABASE:
++ /* Query video memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_VIDEO_MEMORY,
++ &Interface->u.Database.vidMem));
++
++ /* Query non-paged memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_NON_PAGED,
++ &Interface->u.Database.nonPaged));
++
++ /* Query contiguous memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_CONTIGUOUS,
++ &Interface->u.Database.contiguous));
++
++ /* Query GPU idle time. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_IDLE,
++ &Interface->u.Database.gpuIdle));
++ break;
++
++ case gcvHAL_VERSION:
++ Interface->u.Version.major = gcvVERSION_MAJOR;
++ Interface->u.Version.minor = gcvVERSION_MINOR;
++ Interface->u.Version.patch = gcvVERSION_PATCH;
++ Interface->u.Version.build = gcvVERSION_BUILD;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "KERNEL version %d.%d.%d build %u %s %s",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH,
++ gcvVERSION_BUILD, gcvVERSION_DATE, gcvVERSION_TIME);
++#endif
++ break;
++
++ case gcvHAL_CHIP_INFO:
++ /* Only if not support multi-core */
++ Interface->u.ChipInfo.count = 1;
++ Interface->u.ChipInfo.types[0] = Kernel->hardware->type;
++ break;
++
++ case gcvHAL_ATTACH:
++ /* Attach user process. */
++ gcmkONERROR(
++ gckCOMMAND_Attach(Kernel->command,
++ &context,
++ &bytes,
++ processID));
++
++ Interface->u.Attach.stateCount = bytes;
++ Interface->u.Attach.context = gcmPTR_TO_NAME(context);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_CONTEXT,
++ gcmINT2PTR(Interface->u.Attach.context),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvHAL_DETACH:
++ /* Detach user process. */
++ gcmkONERROR(
++ gckCOMMAND_Detach(Kernel->command,
++ gcmNAME_TO_PTR(Interface->u.Detach.context)));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_CONTEXT,
++ gcmINT2PTR(Interface->u.Detach.context)));
++
++ gcmRELEASE_NAME(Interface->u.Detach.context);
++ break;
++
++ case gcvHAL_COMPOSE:
++ Interface->u.Compose.physical = gcmPTR_TO_UINT64(gcmNAME_TO_PTR(Interface->u.Compose.physical));
++ /* Start composition. */
++ gcmkONERROR(
++ gckEVENT_Compose(Kernel->eventObj,
++ &Interface->u.Compose));
++ break;
++
++ case gcvHAL_SET_TIMEOUT:
++ /* set timeOut value from user */
++ gckKERNEL_SetTimeOut(Kernel, Interface->u.SetTimeOut.timeOut);
++ break;
++
++#if gcdFRAME_DB
++ case gcvHAL_GET_FRAME_INFO:
++ gcmkONERROR(gckHARDWARE_GetFrameInfo(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.GetFrameInfo.frameInfo)));
++ break;
++#endif
++
++ case gcvHAL_GET_SHARED_INFO:
++ if (Interface->u.GetSharedInfo.data == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ else
++ {
++ gctUINT32 pid = Interface->u.GetSharedInfo.pid;
++ gctUINT32 dataId = Interface->u.GetSharedInfo.dataId;
++ gctSIZE_T bytes = Interface->u.GetSharedInfo.bytes;
++ gctPOINTER data = Interface->u.GetSharedInfo.data;
++ gcsDATABASE_RECORD record;
++
++ /* Find record. */
++ gcmkONERROR(
++ gckKERNEL_FindProcessDB(Kernel,
++ pid,
++ 0,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId),
++ &record));
++
++ /* Check memory size. */
++ if (bytes < record.bytes)
++ {
++ /* Insufficient memory to hold shared data. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Copy to user. */
++ status = gckOS_CopyToUserData(Kernel->os,
++ record.physical,
++ data,
++ record.bytes);
++
++ /*
++ * Remove from process db.
++ * Every time when shared info is taken, the record is erased in
++ * kernel side.
++ */
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ pid,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId)));
++ /* Free existed data. */
++ gcmkVERIFY_OK(
++ gckOS_FreeMemory(Kernel->os, record.physical));
++ }
++ break;
++
++ case gcvHAL_SET_SHARED_INFO:
++ {
++ gctUINT32 dataId = Interface->u.SetSharedInfo.dataId;
++ gctPOINTER data = Interface->u.SetSharedInfo.data;
++ gctUINT32 bytes = Interface->u.SetSharedInfo.bytes;
++ gctPOINTER memory = gcvNULL;
++ gcsDATABASE_RECORD record;
++
++ if (gcmIS_SUCCESS(gckKERNEL_FindProcessDB(Kernel,
++ processID,
++ 0,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId),
++ &record)))
++ {
++ /* Find a record with the same id. */
++ if (bytes != record.bytes)
++ {
++ /* Remove from process db. */
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId)));
++
++ /* Free existed data. */
++ gcmkVERIFY_OK(
++ gckOS_FreeMemory(Kernel->os, record.physical));
++ }
++ else
++ {
++ /* Re-use allocated memory. */
++ memory = record.physical;
++ }
++ }
++
++ if ((data == gcvNULL) || (bytes == 0))
++ {
++ /* Nothing to record. */
++ break;
++ }
++
++ if (bytes > 1024)
++ {
++ /* Limite data size. */
++ gcmkONERROR(gcvSTATUS_TOO_COMPLEX);
++ }
++
++ if (memory == gcvNULL)
++ {
++ /* Allocate memory for holding shared data. */
++ gcmkONERROR(
++ gckOS_AllocateMemory(Kernel->os, bytes, &memory));
++
++ /* Add to process db. */
++ status = gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHARED_INFO,
++ gcmINT2PTR(dataId),
++ memory,
++ bytes);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Failed to add process db. Free allocated memory. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Kernel->os, memory));
++ break;
++ }
++ }
++
++ /* Copy shared data to kernel memory. */
++ gcmkONERROR(
++ gckOS_CopyFromUserData(Kernel->os,
++ memory,
++ data,
++ bytes));
++ }
++ break;
++
++ case gcvHAL_SET_FSCALE_VALUE:
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ status = gckHARDWARE_SetFscaleValue(Kernel->hardware,
++ Interface->u.SetFscaleValue.value);
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++ case gcvHAL_GET_FSCALE_VALUE:
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ status = gckHARDWARE_GetFscaleValue(Kernel->hardware,
++ &Interface->u.GetFscaleValue.value,
++ &Interface->u.GetFscaleValue.minValue,
++ &Interface->u.GetFscaleValue.maxValue);
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_QUERY_RESET_TIME_STAMP:
++#if gcdENABLE_RECOVERY
++ Interface->u.QueryResetTimeStamp.timeStamp = Kernel->resetTimeStamp;
++#else
++ Interface->u.QueryResetTimeStamp.timeStamp = 0;
++#endif
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvHAL_SYNC_POINT:
++ {
++ gctSYNC_POINT syncPoint;
++
++ switch (Interface->u.SyncPoint.command)
++ {
++ case gcvSYNC_POINT_CREATE:
++ gcmkONERROR(gckOS_CreateSyncPoint(Kernel->os, &syncPoint));
++
++ Interface->u.SyncPoint.syncPoint = gcmPTR_TO_UINT64(syncPoint);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SYNC_POINT,
++ syncPoint,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSYNC_POINT_DESTROY:
++ syncPoint = gcmUINT64_TO_PTR(Interface->u.SyncPoint.syncPoint);
++
++ gcmkONERROR(gckOS_DestroySyncPoint(Kernel->os, syncPoint));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_SYNC_POINT,
++ syncPoint));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ break;
++ }
++ }
++ break;
++
++ case gcvHAL_CREATE_NATIVE_FENCE:
++ {
++ gctINT fenceFD;
++ gctSYNC_POINT syncPoint =
++ gcmUINT64_TO_PTR(Interface->u.CreateNativeFence.syncPoint);
++
++ gcmkONERROR(
++ gckOS_CreateNativeFence(Kernel->os,
++ Kernel->timeline,
++ syncPoint,
++ &fenceFD));
++
++ Interface->u.CreateNativeFence.fenceFD = fenceFD;
++ }
++ break;
++#endif
++
++ default:
++ /* Invalid command. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++OnError:
++ /* Save status. */
++ Interface->status = status;
++
++ if (gcmIS_ERROR(status))
++ {
++ if (locked)
++ {
++ /* Roll back the lock. */
++ gcmkVERIFY_OK(
++ gckVIDMEM_Unlock(Kernel,
++ gcmUINT64_TO_PTR(Interface->u.LockVideoMemory.node),
++ gcvSURF_TYPE_UNKNOWN,
++ &asynchronous));
++
++ if (gcvTRUE == asynchronous)
++ {
++ /* Bottom Half */
++ gcmkVERIFY_OK(
++ gckVIDMEM_Unlock(Kernel,
++ gcmUINT64_TO_PTR(Interface->u.LockVideoMemory.node),
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL));
++ }
++ }
++ }
++
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gckOS_ReleaseMutex(Kernel->os, Kernel->debugMutex);
++#endif
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AttachProcess
++**
++** Attach or detach a process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL Attach
++** gcvTRUE if a new process gets attached or gcFALSE when a process
++** gets detatched.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AttachProcess(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Kernel=0x%x Attach=%d", Kernel, Attach);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckKERNEL_AttachProcessEx(Kernel, Attach, processID));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AttachProcessEx
++**
++** Attach or detach a process with the given PID. Can be paired with gckKERNEL_AttachProcess
++** provided the programmer is aware of the consequences.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL Attach
++** gcvTRUE if a new process gets attached or gcFALSE when a process
++** gets detatched.
++**
++** gctUINT32 PID
++** PID of the process to attach or detach.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AttachProcessEx(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach,
++ IN gctUINT32 PID
++ )
++{
++ gceSTATUS status;
++ gctINT32 old;
++
++ gcmkHEADER_ARG("Kernel=0x%x Attach=%d PID=%d", Kernel, Attach, PID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (Attach)
++ {
++ /* Increment the number of clients attached. */
++ gcmkONERROR(
++ gckOS_AtomIncrement(Kernel->os, Kernel->atomClients, &old));
++
++ if (old == 0)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ gcmkONERROR(gckOS_Broadcast(Kernel->os,
++ Kernel->hardware,
++ gcvBROADCAST_FIRST_PROCESS));
++ }
++ }
++
++ if (Kernel->dbCreated)
++ {
++ /* Create the process database. */
++ gcmkONERROR(gckKERNEL_CreateProcessDB(Kernel, PID));
++ }
++ }
++ else
++ {
++ if (Kernel->dbCreated)
++ {
++ /* Clean up the process database. */
++ gcmkONERROR(gckKERNEL_DestroyProcessDB(Kernel, PID));
++
++ /* Save the last know process ID. */
++ Kernel->db->lastProcessID = PID;
++ }
++
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ status = gckEVENT_Submit(Kernel->eventObj, gcvTRUE, gcvFALSE);
++
++ if (status == gcvSTATUS_INTERRUPTED && Kernel->eventObj->submitTimer)
++ {
++ gcmkONERROR(gckOS_StartTimer(Kernel->os,
++ Kernel->eventObj->submitTimer,
++ 1));
++ }
++ else
++ {
++ gcmkONERROR(status);
++ }
++ }
++
++ /* Decrement the number of clients attached. */
++ gcmkONERROR(
++ gckOS_AtomDecrement(Kernel->os, Kernel->atomClients, &old));
++
++ if (old == 1)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ /* Last client detached, switch to SUSPEND power state. */
++ gcmkONERROR(gckOS_Broadcast(Kernel->os,
++ Kernel->hardware,
++ gcvBROADCAST_LAST_PROCESS));
++ }
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(~0U);
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++gceSTATUS
++gckKERNEL_MapLogicalToPhysical(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN OUT gctPOINTER * Data
++ )
++{
++ gceSTATUS status;
++ static gctBOOL baseAddressValid = gcvFALSE;
++ static gctUINT32 baseAddress;
++ gctBOOL needBase;
++ gcskLOGICAL_CACHE_PTR slot;
++
++ gcmkHEADER_ARG("Kernel=0x%x Cache=0x%x *Data=0x%x",
++ Kernel, Cache, gcmOPT_POINTER(Data));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (!baseAddressValid)
++ {
++ /* Get base address. */
++ gcmkONERROR(gckHARDWARE_GetBaseAddress(Kernel->hardware, &baseAddress));
++
++ baseAddressValid = gcvTRUE;
++ }
++
++ /* Does this state load need a base address? */
++ gcmkONERROR(gckHARDWARE_NeedBaseAddress(Kernel->hardware,
++ ((gctUINT32_PTR) Data)[-1],
++ &needBase));
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LRU
++ {
++ gcskLOGICAL_CACHE_PTR next;
++ gctINT i;
++
++ /* Walk all used cache slots. */
++ for (i = 1, slot = Cache->cache[0].next, next = gcvNULL;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->next
++ )
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++ }
++
++ /* See if we had a miss. */
++ if (next == gcvNULL)
++ {
++ /* Use the tail of the cache. */
++ slot = Cache->cache[0].prev;
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++
++ /* Move slot to head of list. */
++ if (slot != Cache->cache[0].next)
++ {
++ /* Unlink. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Move to head of chain. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ {
++ gctINT i;
++ gcskLOGICAL_CACHE_PTR next = gcvNULL;
++ gcskLOGICAL_CACHE_PTR oldestSlot = gcvNULL;
++ slot = gcvNULL;
++
++ if (Cache->cacheIndex != gcvNULL)
++ {
++ /* Walk the cache forwards. */
++ for (i = 1, slot = Cache->cacheIndex;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->next)
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++
++ /* Determine age of this slot. */
++ if ((oldestSlot == gcvNULL)
++ || (oldestSlot->stamp > slot->stamp)
++ )
++ {
++ oldestSlot = slot;
++ }
++ }
++
++ if (next == gcvNULL)
++ {
++ /* Walk the cache backwards. */
++ for (slot = Cache->cacheIndex->prev;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->prev)
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++
++ /* Determine age of this slot. */
++ if ((oldestSlot == gcvNULL)
++ || (oldestSlot->stamp > slot->stamp)
++ )
++ {
++ oldestSlot = slot;
++ }
++ }
++ }
++ }
++
++ /* See if we had a miss. */
++ if (next == gcvNULL)
++ {
++ if (Cache->cacheFree != 0)
++ {
++ slot = &Cache->cache[Cache->cacheFree];
++ gcmkASSERT(slot->logical == gcvNULL);
++
++ ++ Cache->cacheFree;
++ if (Cache->cacheFree >= gcmCOUNTOF(Cache->cache))
++ {
++ Cache->cacheFree = 0;
++ }
++ }
++ else
++ {
++ /* Use the oldest cache slot. */
++ gcmkASSERT(oldestSlot != gcvNULL);
++ slot = oldestSlot;
++
++ /* Unlink from the chain. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append to the end. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++
++ /* Save time stamp. */
++ slot->stamp = ++ Cache->cacheStamp;
++
++ /* Save current slot for next lookup. */
++ Cache->cacheIndex = slot;
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ {
++ gctINT i;
++ gctUINT32 data = gcmPTR2INT(*Data);
++ gctUINT32 key, index;
++ gcskLOGICAL_CACHE_PTR hash;
++
++ /* Generate a hash key. */
++ key = (data >> 24) + (data >> 16) + (data >> 8) + data;
++ index = key % gcmCOUNTOF(Cache->hash);
++
++ /* Get the hash entry. */
++ hash = &Cache->hash[index];
++
++ for (slot = hash->nextHash, i = 0;
++ (slot != gcvNULL) && (i < gcdSECURE_CACHE_SLOTS);
++ slot = slot->nextHash, ++i
++ )
++ {
++ if (slot->logical == (*Data))
++ {
++ break;
++ }
++ }
++
++ if (slot == gcvNULL)
++ {
++ /* Grab from the tail of the cache. */
++ slot = Cache->cache[0].prev;
++
++ /* Unlink slot from any hash table it is part of. */
++ if (slot->prevHash != gcvNULL)
++ {
++ slot->prevHash->nextHash = slot->nextHash;
++ }
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot->prevHash;
++ }
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++
++ if (hash->nextHash != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "Hash Collision: logical=0x%x key=0x%08x",
++ *Data, key);
++ }
++
++ /* Insert the slot at the head of the hash list. */
++ slot->nextHash = hash->nextHash;
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot;
++ }
++ slot->prevHash = hash;
++ hash->nextHash = slot;
++ }
++
++ /* Move slot to head of list. */
++ if (slot != Cache->cache[0].next)
++ {
++ /* Unlink. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Move to head of chain. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_TABLE
++ {
++ gctUINT32 index = (gcmPTR2INT(*Data) % gcdSECURE_CACHE_SLOTS) + 1;
++
++ /* Get cache slot. */
++ slot = &Cache->cache[index];
++
++ /* Check for cache miss. */
++ if (slot->logical != *Data)
++ {
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++ }
++#endif
++
++ /* Return DMA address. */
++ *Data = gcmINT2PTR(slot->dma + (needBase ? baseAddress : 0));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FlushTranslationCache(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gctINT i;
++ gcskLOGICAL_CACHE_PTR slot;
++ gctUINT8_PTR ptr;
++
++ gcmkHEADER_ARG("Kernel=0x%x Cache=0x%x Logical=0x%x Bytes=%lu",
++ Kernel, Cache, Logical, Bytes);
++
++ /* Do we need to flush the entire cache? */
++ if (Logical == gcvNULL)
++ {
++ /* Clear all cache slots. */
++ for (i = 1; i <= gcdSECURE_CACHE_SLOTS; ++i)
++ {
++ Cache->cache[i].logical = gcvNULL;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ Cache->cache[i].nextHash = gcvNULL;
++ Cache->cache[i].prevHash = gcvNULL;
++#endif
++}
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Zero the hash table. */
++ for (i = 0; i < gcmCOUNTOF(Cache->hash); ++i)
++ {
++ Cache->hash[i].nextHash = gcvNULL;
++ }
++#endif
++
++ /* Reset the cache functionality. */
++ Cache->cacheIndex = gcvNULL;
++ Cache->cacheFree = 1;
++ Cache->cacheStamp = 0;
++ }
++
++ else
++ {
++ gctUINT8_PTR low = (gctUINT8_PTR) Logical;
++ gctUINT8_PTR high = low + Bytes;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LRU
++ gcskLOGICAL_CACHE_PTR next;
++
++ /* Walk all used cache slots. */
++ for (i = 1, slot = Cache->cache[0].next;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = next
++ )
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Unlink slot. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append slot to tail of cache. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ gcskLOGICAL_CACHE_PTR next;
++
++ for (i = 1, slot = Cache->cache[0].next;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = next)
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Test if this slot is the current slot. */
++ if (slot == Cache->cacheIndex)
++ {
++ /* Move to next or previous slot. */
++ Cache->cacheIndex = (slot->next->logical != gcvNULL)
++ ? slot->next
++ : (slot->prev->logical != gcvNULL)
++ ? slot->prev
++ : gcvNULL;
++ }
++
++ /* Unlink slot from cache. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Insert slot to head of cache. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ slot->stamp = 0;
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ gctINT j;
++ gcskLOGICAL_CACHE_PTR hash, next;
++
++ /* Walk all hash tables. */
++ for (i = 0, hash = Cache->hash;
++ i < gcmCOUNTOF(Cache->hash);
++ ++i, ++hash)
++ {
++ /* Walk all slots in the hash. */
++ for (j = 0, slot = hash->nextHash;
++ (j < gcdSECURE_CACHE_SLOTS) && (slot != gcvNULL);
++ ++j, slot = next)
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Unlink slot from hash table. */
++ if (slot->prevHash == hash)
++ {
++ hash->nextHash = slot->nextHash;
++ }
++ else
++ {
++ slot->prevHash->nextHash = slot->nextHash;
++ }
++
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot->prevHash;
++ }
++
++ /* Unlink slot from cache. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append slot to tail of cache. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ slot->prevHash = gcvNULL;
++ slot->nextHash = gcvNULL;
++ }
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_TABLE
++ gctUINT32 index;
++
++ /* Loop while inside the range. */
++ for (i = 1; (low < high) && (i <= gcdSECURE_CACHE_SLOTS); ++i)
++ {
++ /* Get index into cache for this range. */
++ index = (gcmPTR2INT(low) % gcdSECURE_CACHE_SLOTS) + 1;
++ slot = &Cache->cache[index];
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Remove entry from cache. */
++ slot->logical = gcvNULL;
++ }
++
++ /* Next block. */
++ low += gcdSECURE_CACHE_SLOTS;
++ }
++#endif
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckKERNEL_Recovery
++**
++** Try to recover the GPU from a fatal error.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Recovery(
++ IN gckKERNEL Kernel
++ )
++{
++#if gcdENABLE_RECOVERY
++#define gcdEVENT_MASK 0x3FFFFFFF
++ gceSTATUS status;
++ gckEVENT eventObj;
++ gckHARDWARE hardware;
++#if gcdSECURE_USER
++ gctUINT32 processID;
++ gcskSECURE_CACHE_PTR cache;
++#endif
++ gctUINT32 oldValue;
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Grab gckEVENT object. */
++ eventObj = Kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ /* Grab gckHARDWARE object. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++#if gcdSECURE_USER
++ /* Flush the secure mapping cache. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Kernel, processID, &cache));
++ gcmkONERROR(gckKERNEL_FlushTranslationCache(Kernel, cache, gcvNULL, 0));
++#endif
++
++ gcmkONERROR(
++ gckOS_AtomicExchange(Kernel->os, Kernel->resetAtom, 1, &oldValue));
++
++ if (oldValue)
++ {
++ /* Some one else will recovery GPU. */
++ return gcvSTATUS_OK;
++ }
++
++ gcmkPRINT("[galcore]: GPU[%d] hang, automatic recovery.", Kernel->core);
++
++ /* Start a timer to clear reset flag, before timer is expired,
++ ** other recovery request is ignored. */
++ gcmkVERIFY_OK(
++ gckOS_StartTimer(Kernel->os,
++ Kernel->resetFlagClearTimer,
++ gcdGPU_TIMEOUT - 500));
++
++
++ /* Try issuing a soft reset for the GPU. */
++ status = gckHARDWARE_Reset(hardware);
++ if (status == gcvSTATUS_NOT_SUPPORTED)
++ {
++ /* Switch to OFF power. The next submit should return the GPU to ON
++ ** state. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(hardware,
++ gcvPOWER_OFF_RECOVERY));
++ }
++ else
++ {
++ /* Bail out on reset error. */
++ gcmkONERROR(status);
++ }
++
++ /* Handle all outstanding events now. */
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending, gcdEVENT_MASK));
++#else
++ eventObj->pending = gcdEVENT_MASK;
++#endif
++ gcmkONERROR(gckEVENT_Notify(eventObj, 1));
++
++ /* Again in case more events got submitted. */
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending, gcdEVENT_MASK));
++#else
++ eventObj->pending = gcdEVENT_MASK;
++#endif
++ gcmkONERROR(gckEVENT_Notify(eventObj, 2));
++
++ Kernel->resetTimeStamp++;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_OpenUserData
++**
++** Get access to the user data.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL NeedCopy
++** The flag indicating whether or not the data should be copied.
++**
++** gctPOINTER StaticStorage
++** Pointer to the kernel storage where the data is to be copied if
++** NeedCopy is gcvTRUE.
++**
++** gctPOINTER UserPointer
++** User pointer to the data.
++**
++** gctSIZE_T Size
++** Size of the data.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to the kernel pointer that will be pointing to the data.
++*/
++gceSTATUS
++gckKERNEL_OpenUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctPOINTER StaticStorage,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG(
++ "Kernel=0x%08X NeedCopy=%d StaticStorage=0x%08X "
++ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X",
++ Kernel, NeedCopy, StaticStorage, UserPointer, Size, KernelPointer
++ );
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(!NeedCopy || (StaticStorage != gcvNULL));
++ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ if (NeedCopy)
++ {
++ /* Copy the user data to the static storage. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Kernel->os, StaticStorage, UserPointer, Size
++ ));
++
++ /* Set the kernel pointer. */
++ * KernelPointer = StaticStorage;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Map the user pointer. */
++ gcmkONERROR(gckOS_MapUserPointer(
++ Kernel->os, UserPointer, Size, &pointer
++ ));
++
++ /* Set the kernel pointer. */
++ * KernelPointer = pointer;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_CloseUserData
++**
++** Release resources associated with the user data connection opened by
++** gckKERNEL_OpenUserData.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL NeedCopy
++** The flag indicating whether or not the data should be copied.
++**
++** gctBOOL FlushData
++** If gcvTRUE, the data is written back to the user.
++**
++** gctPOINTER UserPointer
++** User pointer to the data.
++**
++** gctSIZE_T Size
++** Size of the data.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Kernel pointer to the data.
++*/
++gceSTATUS
++gckKERNEL_CloseUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctBOOL FlushData,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG(
++ "Kernel=0x%08X NeedCopy=%d FlushData=%d "
++ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X",
++ Kernel, NeedCopy, FlushData, UserPointer, Size, KernelPointer
++ );
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Get a shortcut to the kernel pointer. */
++ pointer = * KernelPointer;
++
++ if (pointer != gcvNULL)
++ {
++ if (NeedCopy)
++ {
++ if (FlushData)
++ {
++ gcmkONERROR(gckOS_CopyToUserData(
++ Kernel->os, * KernelPointer, UserPointer, Size
++ ));
++ }
++ }
++ else
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Kernel->os,
++ UserPointer,
++ Size,
++ * KernelPointer
++ ));
++ }
++
++ /* Reset the kernel pointer. */
++ * KernelPointer = gcvNULL;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++void
++gckKERNEL_SetTimeOut(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 timeOut
++ )
++{
++ gcmkHEADER_ARG("Kernel=0x%x timeOut=%d", Kernel, timeOut);
++#if gcdGPU_TIMEOUT
++ Kernel->timeOut = timeOut;
++#endif
++ gcmkFOOTER_NO();
++}
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++gceSTATUS
++gckKERNEL_AllocateVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckOS os = Kernel->os;
++ gceSTATUS status;
++ gctPOINTER logical;
++ gctSIZE_T pageCount;
++ gctSIZE_T bytes = *Bytes;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gcmkONERROR(gckOS_Allocate(os,
++ sizeof(gckVIRTUAL_COMMAND_BUFFER),
++ (gctPOINTER)&buffer));
++
++ gcmkONERROR(gckOS_ZeroMemory(buffer, sizeof(gckVIRTUAL_COMMAND_BUFFER)));
++
++ gcmkONERROR(gckOS_AllocatePagedMemoryEx(os,
++ gcvFALSE,
++ bytes,
++ &buffer->physical));
++
++ if (InUserSpace)
++ {
++ gcmkONERROR(gckOS_LockPages(os,
++ buffer->physical,
++ bytes,
++ gcvFALSE,
++ &logical,
++ &pageCount));
++
++ *Logical =
++ buffer->userLogical = logical;
++ }
++ else
++ {
++ gcmkONERROR(
++ gckOS_CreateKernelVirtualMapping(buffer->physical,
++ &pageCount,
++ &logical));
++ *Logical =
++ buffer->kernelLogical = logical;
++ }
++
++ buffer->pageCount = pageCount;
++ buffer->kernel = Kernel;
++
++ gcmkONERROR(gckOS_GetProcessID(&buffer->pid));
++
++ gcmkONERROR(gckMMU_AllocatePages(Kernel->mmu,
++ pageCount,
++ &buffer->pageTable,
++ &buffer->gpuAddress));
++
++ gcmkONERROR(gckOS_MapPagesEx(os,
++ Kernel->core,
++ buffer->physical,
++ pageCount,
++ buffer->pageTable));
++
++ gcmkONERROR(gckMMU_Flush(Kernel->mmu));
++
++ *Physical = buffer;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "gpuAddress = %x pageCount = %d kernelLogical = %x userLogical=%x",
++ buffer->gpuAddress, buffer->pageCount,
++ buffer->kernelLogical, buffer->userLogical);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ if (Kernel->virtualBufferHead == gcvNULL)
++ {
++ Kernel->virtualBufferHead =
++ Kernel->virtualBufferTail = buffer;
++ }
++ else
++ {
++ buffer->prev = Kernel->virtualBufferTail;
++ Kernel->virtualBufferTail->next = buffer;
++ Kernel->virtualBufferTail = buffer;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Kernel->virtualBufferLock));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (buffer->gpuAddress)
++ {
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(Kernel->mmu, buffer->pageTable, buffer->pageCount));
++ }
++
++ if (buffer->userLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_UnlockPages(os, buffer->physical, bytes, buffer->userLogical));
++ }
++
++ if (buffer->kernelLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(buffer->kernelLogical));
++ }
++
++ if (buffer->physical)
++ {
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, bytes));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(os, buffer));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_DestroyVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ )
++{
++ gckOS os;
++ gckKERNEL kernel;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)Physical;
++
++ gcmkHEADER();
++ gcmkVERIFY_ARGUMENT(buffer != gcvNULL);
++
++ kernel = buffer->kernel;
++ os = kernel->os;
++
++ if (buffer->userLogical)
++ {
++ gcmkVERIFY_OK(gckOS_UnlockPages(os, buffer->physical, Bytes, Logical));
++ }
++ else
++ {
++ gcmkVERIFY_OK(gckOS_DestroyKernelVirtualMapping(Logical));
++ }
++
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(kernel->mmu, buffer->pageTable, buffer->pageCount));
++
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, Bytes));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, kernel->virtualBufferLock, gcvINFINITE));
++
++ if (buffer == kernel->virtualBufferHead)
++ {
++ if ((kernel->virtualBufferHead = buffer->next) == gcvNULL)
++ {
++ kernel->virtualBufferTail = gcvNULL;
++ }
++ }
++ else
++ {
++ buffer->prev->next = buffer->next;
++
++ if (buffer == kernel->virtualBufferTail)
++ {
++ kernel->virtualBufferTail = buffer->prev;
++ }
++ else
++ {
++ buffer->next->prev = buffer->prev;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, kernel->virtualBufferLock));
++
++ gcmkVERIFY_OK(gckOS_Free(os, buffer));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_GetGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctPOINTER start;
++ gctINT pid;
++
++ gcmkHEADER_ARG("Logical = %x", Logical);
++
++ gckOS_GetProcessID(&pid);
++
++ status = gcvSTATUS_INVALID_ADDRESS;
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ /* Walk all command buffer. */
++ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next)
++ {
++ if (buffer->userLogical)
++ {
++ start = buffer->userLogical;
++ }
++ else
++ {
++ start = buffer->kernelLogical;
++ }
++
++ if (Logical >= start
++ && (Logical < (start + buffer->pageCount * 4096))
++ && pid == buffer->pid
++ )
++ {
++ * Address = buffer->gpuAddress + (Logical - start);
++ status = gcvSTATUS_OK;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock));
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GpuAddress,
++ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer
++ )
++{
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctUINT32 start;
++ gceSTATUS status = gcvSTATUS_NOT_SUPPORTED;
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ /* Walk all command buffers. */
++ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next)
++ {
++ start = (gctUINT32)buffer->gpuAddress;
++
++ if (GpuAddress >= start && GpuAddress < (start + buffer->pageCount * 4096))
++ {
++ /* Find a range matched. */
++ *Buffer = buffer;
++ status = gcvSTATUS_OK;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock));
++
++ return status;
++}
++#endif
++
++#if gcdLINK_QUEUE_SIZE
++static void
++gckLINKQUEUE_Dequeue(
++ IN gckLINKQUEUE LinkQueue
++ )
++{
++ gcmkASSERT(LinkQueue->count == gcdLINK_QUEUE_SIZE);
++
++ LinkQueue->count--;
++ LinkQueue->front = (LinkQueue->front + 1) % gcdLINK_QUEUE_SIZE;
++}
++
++void
++gckLINKQUEUE_Enqueue(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 start,
++ IN gctUINT32 end
++ )
++{
++ if (LinkQueue->count == gcdLINK_QUEUE_SIZE)
++ {
++ gckLINKQUEUE_Dequeue(LinkQueue);
++ }
++
++ gcmkASSERT(LinkQueue->count < gcdLINK_QUEUE_SIZE);
++
++ LinkQueue->count++;
++
++ LinkQueue->data[LinkQueue->rear].start = start;
++ LinkQueue->data[LinkQueue->rear].end = end;
++
++ gcmkVERIFY_OK(
++ gckOS_GetProcessID(&LinkQueue->data[LinkQueue->rear].pid));
++
++ LinkQueue->rear = (LinkQueue->rear + 1) % gcdLINK_QUEUE_SIZE;
++}
++
++void
++gckLINKQUEUE_GetData(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 Index,
++ OUT gckLINKDATA * Data
++ )
++{
++ gcmkASSERT(Index >= 0 && Index < gcdLINK_QUEUE_SIZE);
++
++ *Data = &LinkQueue->data[(Index + LinkQueue->front) % gcdLINK_QUEUE_SIZE];
++}
++#endif
++
++/******************************************************************************\
++*************************** Pointer - ID translation ***************************
++\******************************************************************************/
++#define gcdID_TABLE_LENGTH 1024
++typedef struct _gcsINTEGERDB * gckINTEGERDB;
++typedef struct _gcsINTEGERDB
++{
++ gckOS os;
++ gctPOINTER* table;
++ gctPOINTER mutex;
++ gctUINT32 tableLen;
++ gctUINT32 currentID;
++ gctUINT32 unused;
++}
++gcsINTEGERDB;
++
++gceSTATUS
++gckKERNEL_CreateIntegerDatabase(
++ IN gckKERNEL Kernel,
++ OUT gctPOINTER * Database
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Database != gcvNULL);
++
++ /* Allocate a database. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os, gcmSIZEOF(gcsINTEGERDB), (gctPOINTER *)&database));
++
++ gckOS_ZeroMemory(database, gcmSIZEOF(gcsINTEGERDB));
++
++ /* Allocate a pointer table. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH, (gctPOINTER *)&database->table));
++
++ gckOS_ZeroMemory(database->table, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH);
++
++ /* Allocate a database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Kernel->os, &database->mutex));
++
++ /* Initialize. */
++ database->currentID = 0;
++ database->unused = gcdID_TABLE_LENGTH;
++ database->os = Kernel->os;
++ database->tableLen = gcdID_TABLE_LENGTH;
++
++ *Database = database;
++
++ gcmkFOOTER_ARG("*Database=0x%08X", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Rollback. */
++ if (database)
++ {
++ if (database->table)
++ {
++ gcmkOS_SAFE_FREE(Kernel->os, database->table);
++ }
++
++ gcmkOS_SAFE_FREE(Kernel->os, database);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_DestroyIntegerDatabase(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Database
++ )
++{
++ gckINTEGERDB database = Database;
++
++ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Database != gcvNULL);
++
++ /* Destroy pointer table. */
++ gcmkOS_SAFE_FREE(Kernel->os, database->table);
++
++ /* Destroy database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, database->mutex));
++
++ /* Destroy database. */
++ gcmkOS_SAFE_FREE(Kernel->os, database);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_AllocateIntegerId(
++ IN gctPOINTER Database,
++ IN gctPOINTER Pointer,
++ OUT gctUINT32 * Id
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gctUINT32 i, unused, currentID, tableLen;
++ gctPOINTER * table;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Pointer=0x%08X", Database, Pointer);
++
++ gcmkVERIFY_ARGUMENT(Id != gcvNULL);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (database->unused < 1)
++ {
++ /* Extend table. */
++ gcmkONERROR(
++ gckOS_Allocate(os,
++ gcmSIZEOF(gctPOINTER) * (database->tableLen + gcdID_TABLE_LENGTH),
++ (gctPOINTER *)&table));
++
++ gckOS_ZeroMemory(table + database->tableLen,
++ gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH);
++
++ /* Copy data from old table. */
++ gckOS_MemCopy(table,
++ database->table,
++ database->tableLen * gcmSIZEOF(gctPOINTER));
++
++ gcmkOS_SAFE_FREE(os, database->table);
++
++ /* Update databse with new allocated table. */
++ database->table = table;
++ database->currentID = database->tableLen;
++ database->tableLen += gcdID_TABLE_LENGTH;
++ database->unused += gcdID_TABLE_LENGTH;
++ }
++
++ table = database->table;
++ currentID = database->currentID;
++ tableLen = database->tableLen;
++ unused = database->unused;
++
++ /* Connect id with pointer. */
++ table[currentID] = Pointer;
++
++ *Id = currentID + 1;
++
++ /* Update the currentID. */
++ if (--unused > 0)
++ {
++ for (i = 0; i < tableLen; i++)
++ {
++ if (++currentID >= tableLen)
++ {
++ /* Wrap to the begin. */
++ currentID = 0;
++ }
++
++ if (table[currentID] == gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ database->table = table;
++ database->currentID = currentID;
++ database->tableLen = tableLen;
++ database->unused = unused;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_ARG("*Id=%d", *Id);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FreeIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (!(Id > 0 && Id <= database->tableLen))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ Id -= 1;
++
++ database->table[Id] = gcvNULL;
++
++ if (database->unused++ == 0)
++ {
++ database->currentID = Id;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * Pointer
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gctPOINTER pointer;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (!(Id > 0 && Id <= database->tableLen))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ Id -= 1;
++
++ pointer = database->table[Id];
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ if (pointer)
++ {
++ *Pointer = pointer;
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ gcmkFOOTER_ARG("*Pointer=0x%08X", *Pointer);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++gctUINT32
++gckKERNEL_AllocateNameFromPointer(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Pointer
++ )
++{
++ gceSTATUS status;
++ gctUINT32 name;
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Pointer=0x%X", Kernel, Pointer);
++
++ gcmkONERROR(
++ gckKERNEL_AllocateIntegerId(database, Pointer, &name));
++
++ gcmkFOOTER_ARG("name=%d", name);
++ return name;
++
++OnError:
++ gcmkFOOTER();
++ return 0;
++}
++
++gctPOINTER
++gckKERNEL_QueryPointerFromName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ )
++{
++ gceSTATUS status;
++ gctPOINTER pointer = gcvNULL;
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=%d", Kernel, Name);
++
++ /* Lookup in database to get pointer. */
++ gcmkONERROR(gckKERNEL_QueryIntegerId(database, Name, &pointer));
++
++ gcmkFOOTER_ARG("pointer=0x%X", pointer);
++ return pointer;
++
++OnError:
++ gcmkFOOTER();
++ return gcvNULL;
++}
++
++gceSTATUS
++gckKERNEL_DeleteName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ )
++{
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=0x%X", Kernel, Name);
++
++ /* Free name if exists. */
++ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(database, Name));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++/*******************************************************************************
++***** Test Code ****************************************************************
++*******************************************************************************/
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,3042 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include "gc_hal_kernel_context.h"
++
++#ifdef __QNXNTO__
++#include <sys/slog.h>
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** _NewQueue
++**
++** Allocate a new command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** OUTPUT:
++**
++** gckCOMMAND Command
++** gckCOMMAND object has been updated with a new command queue.
++*/
++static gceSTATUS
++_NewQueue(
++ IN OUT gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctINT currentIndex, newIndex;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Switch to the next command buffer. */
++ currentIndex = Command->index;
++ newIndex = (currentIndex + 1) % gcdCOMMAND_QUEUES;
++
++ /* Wait for availability. */
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.waitsignal]");
++#endif
++
++ gcmkONERROR(gckOS_WaitSignal(
++ Command->os,
++ Command->queues[newIndex].signal,
++ gcvINFINITE
++ ));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ if (newIndex < currentIndex)
++ {
++ Command->wrapCount += 1;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 2 * 4,
++ "%s(%d): queue array wrapped around.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 3 * 4,
++ "%s(%d): total queue wrap arounds %d.\n",
++ __FUNCTION__, __LINE__, Command->wrapCount
++ );
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 3 * 4,
++ "%s(%d): switched to queue %d.\n",
++ __FUNCTION__, __LINE__, newIndex
++ );
++#endif
++
++ /* Update gckCOMMAND object with new command queue. */
++ Command->index = newIndex;
++ Command->newQueue = gcvTRUE;
++ Command->logical = Command->queues[newIndex].logical;
++ Command->offset = 0;
++
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(
++ Command->os,
++ Command->logical,
++ (gctUINT32 *) &Command->physical
++ ));
++
++ if (currentIndex != -1)
++ {
++ /* Mark the command queue as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ Command->kernel->eventObj,
++ Command->queues[currentIndex].signal,
++ gcvKERNEL_COMMAND
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("Command->index=%d", Command->index);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IncrementCommitAtom(
++ IN gckCOMMAND Command,
++ IN gctBOOL Increment
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctINT32 atomValue;
++ gctBOOL powerAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Grab the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, hardware->powerMutex, gcvINFINITE
++ ));
++ powerAcquired = gcvTRUE;
++
++ /* Increment the commit atom. */
++ if (Increment)
++ {
++ gcmkONERROR(gckOS_AtomIncrement(
++ Command->os, Command->atomCommit, &atomValue
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AtomDecrement(
++ Command->os, Command->atomCommit, &atomValue
++ ));
++ }
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(
++ Command->os, hardware->powerMutex
++ ));
++ powerAcquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (powerAcquired)
++ {
++ /* Release the power mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ Command->os, hardware->powerMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++static gceSTATUS
++_ProcessHints(
++ IN gckCOMMAND Command,
++ IN gctUINT32 ProcessID,
++ IN gcoCMDBUF CommandBuffer
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gckKERNEL kernel;
++ gctBOOL needCopy = gcvFALSE;
++ gcskSECURE_CACHE_PTR cache;
++ gctUINT8_PTR commandBufferLogical;
++ gctUINT8_PTR hintedData;
++ gctUINT32_PTR hintArray;
++ gctUINT i, hintCount;
++
++ gcmkHEADER_ARG(
++ "Command=0x%08X ProcessID=%d CommandBuffer=0x%08X",
++ Command, ProcessID, CommandBuffer
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Reset state array pointer. */
++ hintArray = gcvNULL;
++
++ /* Get the kernel object. */
++ kernel = Command->kernel;
++
++ /* Get the cache form the database. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(kernel, ProcessID, &cache));
++
++ /* Determine the start of the command buffer. */
++ commandBufferLogical
++ = (gctUINT8_PTR) CommandBuffer->logical
++ + CommandBuffer->startOffset;
++
++ /* Determine the number of records in the state array. */
++ hintCount = CommandBuffer->hintArrayTail - CommandBuffer->hintArray;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy));
++
++ /* Get access to the state array. */
++ if (needCopy)
++ {
++ gctUINT copySize;
++
++ if (Command->hintArrayAllocated &&
++ (Command->hintArraySize < CommandBuffer->hintArraySize))
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Command->os, gcmUINT64_TO_PTR(Command->hintArray)));
++ Command->hintArraySize = gcvFALSE;
++ }
++
++ if (!Command->hintArrayAllocated)
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkONERROR(gckOS_Allocate(
++ Command->os,
++ CommandBuffer->hintArraySize,
++ &pointer
++ ));
++
++ Command->hintArray = gcmPTR_TO_UINT64(pointer);
++ Command->hintArrayAllocated = gcvTRUE;
++ Command->hintArraySize = CommandBuffer->hintArraySize;
++ }
++
++ hintArray = gcmUINT64_TO_PTR(Command->hintArray);
++ copySize = hintCount * gcmSIZEOF(gctUINT32);
++
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os,
++ hintArray,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ copySize
++ ));
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ CommandBuffer->hintArraySize,
++ &pointer
++ ));
++
++ hintArray = pointer;
++ }
++
++ /* Scan through the buffer. */
++ for (i = 0; i < hintCount; i += 1)
++ {
++ /* Determine the location of the hinted data. */
++ hintedData = commandBufferLogical + hintArray[i];
++
++ /* Map handle into physical address. */
++ gcmkONERROR(gckKERNEL_MapLogicalToPhysical(
++ kernel, cache, (gctPOINTER) hintedData
++ ));
++ }
++
++OnError:
++ /* Get access to the state array. */
++ if (!needCopy && (hintArray != gcvNULL))
++ {
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ CommandBuffer->hintArraySize,
++ hintArray
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_FlushMMU(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 oldValue;
++ gckHARDWARE hardware = Command->kernel->hardware;
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ hardware->pageTableDirty,
++ 0,
++ &oldValue));
++
++ if (oldValue)
++ {
++ /* Page Table is upated, flush mmu before commit. */
++ gcmkONERROR(gckHARDWARE_FlushMMU(hardware));
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++static void
++_DumpBuffer(
++ IN gctPOINTER Buffer,
++ IN gctUINT32 GpuAddress,
++ IN gctSIZE_T Size
++ )
++{
++ gctINT i, line, left;
++ gctUINT32_PTR data = Buffer;
++
++ line = Size / 32;
++ left = Size % 32;
++
++
++ for (i = 0; i < line; i++)
++ {
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]);
++ data += 8;
++ GpuAddress += 8 * 4;
++ }
++
++ switch(left)
++ {
++ case 28:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6]);
++ break;
++ case 24:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5]);
++ break;
++ case 20:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4]);
++ break;
++ case 16:
++ gcmkPRINT("%X : %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3]);
++ break;
++ case 12:
++ gcmkPRINT("%X : %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2]);
++ break;
++ case 8:
++ gcmkPRINT("%X : %08X %08X ",
++ GpuAddress, data[0], data[1]);
++ break;
++ case 4:
++ gcmkPRINT("%X : %08X ",
++ GpuAddress, data[0]);
++ break;
++ default:
++ break;
++ }
++}
++
++static void
++_DumpKernelCommandBuffer(
++ IN gckCOMMAND Command
++)
++{
++ gctINT i;
++ gctUINT32 physical;
++ gctPOINTER entry;
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ entry = Command->queues[i].logical;
++
++ gckOS_GetPhysicalAddress(Command->os, entry, &physical);
++
++ gcmkPRINT("Kernel command buffer %d\n", i);
++
++ _DumpBuffer(entry, physical, Command->pageSize);
++ }
++}
++#endif
++
++/******************************************************************************\
++****************************** gckCOMMAND API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckCOMMAND_Construct
++**
++** Construct a new gckCOMMAND object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gckCOMMAND * Command
++** Pointer to a variable that will hold the pointer to the gckCOMMAND
++** object.
++*/
++gceSTATUS
++gckCOMMAND_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckCOMMAND * Command
++ )
++{
++ gckOS os;
++ gckCOMMAND command = gcvNULL;
++ gceSTATUS status;
++ gctINT i;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Command != gcvNULL);
++
++ /* Extract the gckOS object. */
++ os = Kernel->os;
++
++ /* Allocate the gckCOMMAND structure. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckCOMMAND), &pointer));
++ command = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(command, gcmSIZEOF(struct _gckCOMMAND)));
++
++ /* Initialize the gckCOMMAND object.*/
++ command->object.type = gcvOBJ_COMMAND;
++ command->kernel = Kernel;
++ command->os = os;
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Kernel->hardware,
++ &command->alignment,
++ &command->reservedHead,
++ &command->reservedTail
++ ));
++
++ /* Create the command queue mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexQueue));
++
++ /* Create the context switching mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContext));
++
++#if VIVANTE_PROFILER_CONTEXT
++ /* Create the context switching mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContextSeq));
++#endif
++
++ /* Create the power management semaphore. */
++ gcmkONERROR(gckOS_CreateSemaphore(os, &command->powerSemaphore));
++
++ /* Create the commit atom. */
++ gcmkONERROR(gckOS_AtomConstruct(os, &command->atomCommit));
++
++ /* Get the page size from teh OS. */
++ gcmkONERROR(gckOS_GetPageSize(os, &command->pageSize));
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&command->kernelProcessID));
++
++ /* Set hardware to pipe 0. */
++ command->pipeSelect = gcvPIPE_INVALID;
++
++ /* Pre-allocate the command queues. */
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ os,
++ gcvFALSE,
++ &command->pageSize,
++ &command->queues[i].physical,
++ &command->queues[i].logical
++ ));
++
++ gcmkONERROR(gckOS_CreateSignal(
++ os, gcvFALSE, &command->queues[i].signal
++ ));
++
++ gcmkONERROR(gckOS_Signal(
++ os, command->queues[i].signal, gcvTRUE
++ ));
++ }
++
++ /* No command queue in use yet. */
++ command->index = -1;
++ command->logical = gcvNULL;
++ command->newQueue = gcvFALSE;
++
++ /* Command is not yet running. */
++ command->running = gcvFALSE;
++
++ /* Command queue is idle. */
++ command->idle = gcvTRUE;
++
++ /* Commit stamp is zero. */
++ command->commitStamp = 0;
++
++ /* END event signal not created. */
++ command->endEventSignal = gcvNULL;
++
++ /* Return pointer to the gckCOMMAND object. */
++ *Command = command;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Command=0x%x", *Command);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (command != gcvNULL)
++ {
++ if (command->atomCommit != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, command->atomCommit));
++ }
++
++ if (command->powerSemaphore != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(os, command->powerSemaphore));
++ }
++
++ if (command->mutexContext != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContext));
++ }
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (command->mutexContextSeq != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContextSeq));
++ }
++#endif
++
++ if (command->mutexQueue != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexQueue));
++ }
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ if (command->queues[i].signal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ os, command->queues[i].signal
++ ));
++ }
++
++ if (command->queues[i].logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ os,
++ command->pageSize,
++ command->queues[i].physical,
++ command->queues[i].logical
++ ));
++ }
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, command));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Destroy
++**
++** Destroy an gckCOMMAND object.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Destroy(
++ IN gckCOMMAND Command
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Stop the command queue. */
++ gcmkVERIFY_OK(gckCOMMAND_Stop(Command, gcvFALSE));
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ gcmkASSERT(Command->queues[i].signal != gcvNULL);
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, Command->queues[i].signal
++ ));
++
++ gcmkASSERT(Command->queues[i].logical != gcvNULL);
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ Command->os,
++ Command->pageSize,
++ Command->queues[i].physical,
++ Command->queues[i].logical
++ ));
++ }
++
++ /* END event signal. */
++ if (Command->endEventSignal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, Command->endEventSignal
++ ));
++ }
++
++ /* Delete the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContext));
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (Command->mutexContextSeq != gcvNULL)
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContextSeq));
++#endif
++
++ /* Delete the command queue mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexQueue));
++
++ /* Destroy the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Command->os, Command->powerSemaphore));
++
++ /* Destroy the commit atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Command->os, Command->atomCommit));
++
++#if gcdSECURE_USER
++ /* Free state array. */
++ if (Command->hintArrayAllocated)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Command->os, gcmUINT64_TO_PTR(Command->hintArray)));
++ Command->hintArrayAllocated = gcvFALSE;
++ }
++#endif
++
++ /* Mark object as unknown. */
++ Command->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCOMMAND object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Command->os, Command));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_EnterCommit
++**
++** Acquire command queue synchronization objects.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_EnterCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctBOOL atomIncremented = gcvFALSE;
++ gctBOOL semaAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (!FromPower)
++ {
++ /* Increment COMMIT atom to let power management know that a commit is
++ ** in progress. */
++ gcmkONERROR(_IncrementCommitAtom(Command, gcvTRUE));
++ atomIncremented = gcvTRUE;
++
++ /* Notify the system the GPU has a commit. */
++ gcmkONERROR(gckOS_Broadcast(Command->os,
++ hardware,
++ gcvBROADCAST_GPU_COMMIT));
++
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(Command->os,
++ Command->powerSemaphore));
++ semaAcquired = gcvTRUE;
++ }
++
++ /* Grab the conmmand queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Command->os,
++ Command->mutexQueue,
++ gcvINFINITE));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (semaAcquired)
++ {
++ /* Release the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore
++ ));
++ }
++
++ if (atomIncremented)
++ {
++ /* Decrement the commit atom. */
++ gcmkVERIFY_OK(_IncrementCommitAtom(
++ Command, gcvFALSE
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_ExitCommit
++**
++** Release command queue synchronization objects.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_ExitCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexQueue));
++
++ if (!FromPower)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(Command->os,
++ Command->powerSemaphore));
++
++ /* Decrement the commit atom. */
++ gcmkONERROR(_IncrementCommitAtom(Command, gcvFALSE));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Start
++**
++** Start up the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to start.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Start(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctUINT32 waitOffset;
++ gctSIZE_T waitLinkBytes;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->running)
++ {
++ /* Command queue already running. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract the gckHARDWARE object. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (Command->logical == gcvNULL)
++ {
++ /* Start at beginning of a new queue. */
++ gcmkONERROR(_NewQueue(Command));
++ }
++
++ /* Start at beginning of page. */
++ Command->offset = 0;
++
++ /* Set abvailable number of bytes for WAIT/LINK command sequence. */
++ waitLinkBytes = Command->pageSize;
++
++ /* Append WAIT/LINK. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ Command->logical,
++ 0,
++ &waitLinkBytes,
++ &waitOffset,
++ &Command->waitSize
++ ));
++
++ Command->waitLogical = (gctUINT8_PTR) Command->logical + waitOffset;
++ Command->waitPhysical = (gctUINT8_PTR) Command->physical + waitOffset;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ Command->physical,
++ Command->logical,
++ waitLinkBytes
++ ));
++#endif
++
++ /* Adjust offset. */
++ Command->offset = waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Enable command processor. */
++#ifdef __QNXNTO__
++ gcmkONERROR(gckHARDWARE_Execute(
++ hardware,
++ Command->logical,
++ Command->physical,
++ gcvTRUE,
++ waitLinkBytes
++ ));
++#else
++ gcmkONERROR(gckHARDWARE_Execute(
++ hardware,
++ Command->logical,
++ waitLinkBytes
++ ));
++#endif
++
++ /* Command queue is running. */
++ Command->running = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Stop
++**
++** Stop the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to stop.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Stop(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromRecovery
++ )
++{
++ gckHARDWARE hardware;
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (!Command->running)
++ {
++ /* Command queue is not running. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract the gckHARDWARE object. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (gckHARDWARE_IsFeatureAvailable(hardware,
++ gcvFEATURE_END_EVENT) == gcvSTATUS_TRUE)
++ {
++ /* Allocate the signal. */
++ if (Command->endEventSignal == gcvNULL)
++ {
++ gcmkONERROR(gckOS_CreateSignal(Command->os,
++ gcvTRUE,
++ &Command->endEventSignal));
++ }
++
++ /* Append the END EVENT command to trigger the signal. */
++ gcmkONERROR(gckEVENT_Stop(Command->kernel->eventObj,
++ Command->kernelProcessID,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->endEventSignal,
++ &Command->waitSize));
++ }
++ else
++ {
++ /* Replace last WAIT with END. */
++ gcmkONERROR(gckHARDWARE_End(
++ hardware, Command->waitLogical, &Command->waitSize
++ ));
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(Command->kernel->hardware,
++ Command->logical,
++ Command->offset));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the END. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ /* Wait for idle. */
++ gcmkONERROR(gckHARDWARE_GetIdle(hardware, !FromRecovery, &idle));
++ }
++
++ /* Command queue is no longer running. */
++ Command->running = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Commit
++**
++** Commit a command buffer to the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gckCONTEXT Context
++** Pointer to a gckCONTEXT object.
++**
++** gcoCMDBUF CommandBuffer
++** Pointer to a gcoCMDBUF object.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL contextAcquired = gcvFALSE;
++ gckHARDWARE hardware;
++ gctBOOL needCopy = gcvFALSE;
++ gcsQUEUE_PTR eventRecord = gcvNULL;
++ gcsQUEUE _eventRecord;
++ gcsQUEUE_PTR nextEventRecord;
++ gctBOOL commandBufferMapped = gcvFALSE;
++ gcoCMDBUF commandBufferObject = gcvNULL;
++
++#if !gcdNULL_DRIVER
++ gcsCONTEXT_PTR contextBuffer;
++ struct _gcoCMDBUF _commandBufferObject;
++ gctPHYS_ADDR commandBufferPhysical;
++ gctUINT8_PTR commandBufferLogical;
++ gctUINT8_PTR commandBufferLink;
++ gctUINT commandBufferSize;
++ gctSIZE_T nopBytes;
++ gctSIZE_T pipeBytes;
++ gctSIZE_T linkBytes;
++ gctSIZE_T bytes;
++ gctUINT32 offset;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR entryPhysical;
++#endif
++ gctPOINTER entryLogical;
++ gctSIZE_T entryBytes;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR exitPhysical;
++#endif
++ gctPOINTER exitLogical;
++ gctSIZE_T exitBytes;
++ gctPHYS_ADDR waitLinkPhysical;
++ gctPOINTER waitLinkLogical;
++ gctSIZE_T waitLinkBytes;
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitOffset;
++ gctSIZE_T waitSize;
++
++#if gcdDUMP_COMMAND
++ gctPOINTER contextDumpLogical = gcvNULL;
++ gctSIZE_T contextDumpBytes = 0;
++ gctPOINTER bufferDumpLogical = gcvNULL;
++ gctSIZE_T bufferDumpBytes = 0;
++# endif
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ gctBOOL sequenceAcquired = gcvFALSE;
++#endif
++
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG(
++ "Command=0x%x CommandBuffer=0x%x ProcessID=%d",
++ Command, CommandBuffer, ProcessID
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->kernel->core == gcvCORE_2D)
++ {
++ /* There is no context for 2D. */
++ Context = gcvNULL;
++ }
++
++ gcmkONERROR(_FlushMMU(Command));
++
++#if VIVANTE_PROFILER_CONTEXT
++ if((Command->kernel->hardware->gpuProfiler) && (Command->kernel->profileEnable))
++ {
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContextSeq, gcvINFINITE
++ ));
++ sequenceAcquired = gcvTRUE;
++ }
++#endif
++
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(Command, gcvFALSE));
++ commitEntered = gcvTRUE;
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ contextAcquired = gcvTRUE;
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy));
++
++#if gcdNULL_DRIVER
++ /* Context switch required? */
++ if ((Context != gcvNULL) && (Command->currContext != Context))
++ {
++ /* Yes, merge in the deltas. */
++ gckCONTEXT_Update(Context, ProcessID, StateDelta);
++
++ /* Update the current context. */
++ Command->currContext = Context;
++ }
++#else
++ if (needCopy)
++ {
++ commandBufferObject = &_commandBufferObject;
++
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os,
++ commandBufferObject,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF)
++ ));
++
++ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER);
++ }
++ else
++ {
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ &pointer
++ ));
++
++ commandBufferObject = pointer;
++
++ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER);
++ commandBufferMapped = gcvTRUE;
++ }
++
++ /* Query the size of NOP command. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware, gcvNULL, &nopBytes
++ ));
++
++ /* Query the size of pipe select command sequence. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ hardware, gcvNULL, gcvPIPE_3D, &pipeBytes
++ ));
++
++ /* Query the size of LINK command. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware, gcvNULL, gcvNULL, 0, &linkBytes
++ ));
++
++ /* Compute the command buffer entry and the size. */
++ commandBufferLogical
++ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical)
++ + commandBufferObject->startOffset;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Command->os,
++ commandBufferLogical,
++ (gctUINT32_PTR)&commandBufferPhysical
++ ));
++
++ commandBufferSize
++ = commandBufferObject->offset
++ + Command->reservedTail
++ - commandBufferObject->startOffset;
++
++ /* Get the current offset. */
++ offset = Command->offset;
++
++ /* Compute number of bytes left in current kernel command queue. */
++ bytes = Command->pageSize - offset;
++
++ /* Query the size of WAIT/LINK command sequence. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ gcvNULL,
++ offset,
++ &waitLinkBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Is there enough space in the current command queue? */
++ if (bytes < waitLinkBytes)
++ {
++ /* No, create a new one. */
++ gcmkONERROR(_NewQueue(Command));
++
++ /* Get the new current offset. */
++ offset = Command->offset;
++
++ /* Recompute the number of bytes in the new kernel command queue. */
++ bytes = Command->pageSize - offset;
++ gcmkASSERT(bytes >= waitLinkBytes);
++ }
++
++ /* Compute the location if WAIT/LINK command sequence. */
++ waitLinkPhysical = (gctUINT8_PTR) Command->physical + offset;
++ waitLinkLogical = (gctUINT8_PTR) Command->logical + offset;
++
++ /* Context switch required? */
++ if (Context == gcvNULL)
++ {
++ /* See if we have to switch pipes for the command buffer. */
++ if (commandBufferObject->entryPipe == Command->pipeSelect)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the entry command buffer pipes
++ ** are different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset;
++#endif
++ entryLogical = commandBufferLogical + offset;
++ entryBytes = commandBufferSize - offset;
++ }
++ else if (Command->currContext != Context)
++ {
++ /* Temporary disable context length oprimization. */
++ Context->dirty = gcvTRUE;
++
++ /* Get the current context buffer. */
++ contextBuffer = Context->buffer;
++
++ /* Yes, merge in the deltas. */
++ gcmkONERROR(gckCONTEXT_Update(Context, ProcessID, StateDelta));
++
++ /* Determine context entry and exit points. */
++ if (0)
++ {
++ /* Reset 2D dirty flag. */
++ Context->dirty2D = gcvFALSE;
++
++ if (Context->dirty || commandBufferObject->using3D)
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 2D and 3D are used.
++ */
++
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryBytes = Context->bufferSize - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryBytes = Context->bufferSize;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Ensure the NOP between 2D and 3D is in place so that the
++ execution falls through from 2D to 3D. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ contextBuffer->link2D,
++ &nopBytes
++ ));
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++
++ /* Mark context as not dirty. */
++ Context->dirty = gcvFALSE;
++ }
++ else
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 2D only command buffer.
++ */
++
++ /* Mark 3D as dirty. */
++ Context->dirty3D = gcvTRUE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryBytes = Context->entryOffset3D - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryBytes = Context->entryOffset3D;
++ }
++
++ /* Store the current context buffer. */
++ Context->dirtyBuffer = contextBuffer;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_2D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* 3D is not used, generate a LINK from the end of 2D part of
++ the context buffer to the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link2D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++
++ /* Not using 2D. */
++ else
++ {
++ /* Mark 2D as dirty. */
++ Context->dirty2D = gcvTRUE;
++
++ /* Store the current context buffer. */
++ Context->dirtyBuffer = contextBuffer;
++
++ if (Context->dirty || commandBufferObject->using3D)
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 3D only command buffer.
++ */
++
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Determine context buffer entry offset. */
++ offset = (Command->pipeSelect == gcvPIPE_3D)
++
++ /* Skip pipe switching sequence. */
++ ? Context->entryOffset3D + pipeBytes
++
++ /* Do not skip pipe switching sequence. */
++ : Context->entryOffset3D;
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset;
++ entryBytes = Context->bufferSize - offset;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: "XD" command buffer - neither 2D nor 3D.
++ */
++
++ /* Mark 3D as dirty. */
++ Context->dirty3D = gcvTRUE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_3D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical
++ = (gctUINT8_PTR) contextBuffer->physical
++ + Context->entryOffsetXDFrom3D;
++#endif
++ entryLogical
++ = (gctUINT8_PTR) contextBuffer->logical
++ + Context->entryOffsetXDFrom3D;
++
++ entryBytes
++ = Context->bufferSize
++ - Context->entryOffsetXDFrom3D;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical
++ = (gctUINT8_PTR) contextBuffer->physical
++ + Context->entryOffsetXDFrom2D;
++#endif
++ entryLogical
++ = (gctUINT8_PTR) contextBuffer->logical
++ + Context->entryOffsetXDFrom2D;
++
++ entryBytes
++ = Context->totalSize
++ - Context->entryOffsetXDFrom2D;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the context buffer cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ entryPhysical,
++ entryLogical,
++ entryBytes
++ ));
++#endif
++
++ /* Update the current context. */
++ Command->currContext = Context;
++
++#if gcdDUMP_COMMAND
++ contextDumpLogical = entryLogical;
++ contextDumpBytes = entryBytes;
++#endif
++ }
++
++ /* Same context. */
++ else
++ {
++ /* Determine context entry and exit points. */
++ if (commandBufferObject->using2D && Context->dirty2D)
++ {
++ /* Reset 2D dirty flag. */
++ Context->dirty2D = gcvFALSE;
++
++ /* Get the "dirty" context buffer. */
++ contextBuffer = Context->dirtyBuffer;
++
++ if (commandBufferObject->using3D && Context->dirty3D)
++ {
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryBytes = Context->bufferSize - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryBytes = Context->bufferSize;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Ensure the NOP between 2D and 3D is in place so that the
++ execution falls through from 2D to 3D. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ contextBuffer->link2D,
++ &nopBytes
++ ));
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryBytes = Context->entryOffset3D - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryBytes = Context->entryOffset3D;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_2D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* 3D is not used, generate a LINK from the end of 2D part of
++ the context buffer to the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link2D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++ else
++ {
++ if (commandBufferObject->using3D && Context->dirty3D)
++ {
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Get the "dirty" context buffer. */
++ contextBuffer = Context->dirtyBuffer;
++
++ /* Determine context buffer entry offset. */
++ offset = (Command->pipeSelect == gcvPIPE_3D)
++
++ /* Skip pipe switching sequence. */
++ ? Context->entryOffset3D + pipeBytes
++
++ /* Do not skip pipe switching sequence. */
++ : Context->entryOffset3D;
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset;
++ entryBytes = Context->bufferSize - offset;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferLogical + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /* See if we have to switch pipes for the command buffer. */
++ if (commandBufferObject->entryPipe == Command->pipeSelect)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the entry command buffer pipes
++ ** are different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset;
++#endif
++ entryLogical = commandBufferLogical + offset;
++ entryBytes = commandBufferSize - offset;
++ }
++ }
++ }
++
++#if gcdDUMP_COMMAND
++ bufferDumpLogical = commandBufferLogical + offset;
++ bufferDumpBytes = commandBufferSize - offset;
++#endif
++
++#if gcdSECURE_USER
++ /* Process user hints. */
++ gcmkONERROR(_ProcessHints(Command, ProcessID, commandBufferObject));
++#endif
++
++ /* Determine the location to jump to for the command buffer being
++ ** scheduled. */
++ if (Command->newQueue)
++ {
++ /* New command queue, jump to the beginning of it. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ exitPhysical = Command->physical;
++#endif
++ exitLogical = Command->logical;
++ exitBytes = Command->offset + waitLinkBytes;
++ }
++ else
++ {
++ /* Still within the preexisting command queue, jump to the new
++ WAIT/LINK command sequence. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ exitPhysical = waitLinkPhysical;
++#endif
++ exitLogical = waitLinkLogical;
++ exitBytes = waitLinkBytes;
++ }
++
++ /* Add a new WAIT/LINK command sequence. When the command buffer which is
++ currently being scheduled is fully executed by the GPU, the FE will
++ jump to this WAIT/LINK sequence. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ waitLinkLogical,
++ offset,
++ &waitLinkBytes,
++ &waitOffset,
++ &waitSize
++ ));
++
++ /* Compute the location if WAIT command. */
++ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset;
++ waitLogical = (gctUINT8_PTR) waitLinkLogical + waitOffset;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the command queue cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ exitPhysical,
++ exitLogical,
++ exitBytes
++ ));
++#endif
++
++ /* Determine the location of the LINK command in the command buffer. */
++ commandBufferLink
++ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical)
++ + commandBufferObject->offset;
++
++ /* Generate a LINK from the end of the command buffer being scheduled
++ back to the kernel command queue. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ commandBufferLink,
++ exitLogical,
++ exitBytes,
++ &linkBytes
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the command buffer cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ ProcessID,
++ gcvNULL,
++ commandBufferPhysical,
++ commandBufferLogical,
++ commandBufferSize
++ ));
++#endif
++
++ /* Generate a LINK from the previous WAIT/LINK command sequence to the
++ entry determined above (either the context or the command buffer).
++ This LINK replaces the WAIT instruction from the previous WAIT/LINK
++ pair, therefore we use WAIT metrics for generation of this LINK.
++ This action will execute the entire sequence. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ Command->waitLogical,
++ entryLogical,
++ entryBytes,
++ &Command->waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ Command->waitLogical,
++ Command->waitSize,
++ gceDUMP_BUFFER_LINK,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ contextDumpLogical,
++ contextDumpBytes,
++ gceDUMP_BUFFER_CONTEXT,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ bufferDumpLogical,
++ bufferDumpBytes,
++ gceDUMP_BUFFER_USER,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ waitLinkLogical,
++ waitLinkBytes,
++ gceDUMP_BUFFER_WAITLINK,
++ gcvFALSE
++ );
++
++ /* Update the current pipe. */
++ Command->pipeSelect = commandBufferObject->exitPipe;
++
++ /* Update command queue offset. */
++ Command->offset += waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Update address of last WAIT. */
++ Command->waitPhysical = waitPhysical;
++ Command->waitLogical = waitLogical;
++ Command->waitSize = waitSize;
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ hardware, Command->logical, Command->offset
++ ));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.commit]");
++#endif
++#endif /* gcdNULL_DRIVER */
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ contextAcquired = gcvFALSE;
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(Command, gcvFALSE));
++ commitEntered = gcvFALSE;
++
++#if VIVANTE_PROFILER_CONTEXT
++ if(sequenceAcquired)
++ {
++ gcmkONERROR(gckCOMMAND_Stall(Command, gcvTRUE));
++ if (Command->currContext)
++ {
++ gcmkONERROR(gckHARDWARE_UpdateContextProfile(
++ hardware,
++ Command->currContext));
++ }
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
++ sequenceAcquired = gcvFALSE;
++ }
++#endif
++
++ /* Loop while there are records in the queue. */
++ while (EventQueue != gcvNULL)
++ {
++ if (needCopy)
++ {
++ /* Point to stack record. */
++ eventRecord = &_eventRecord;
++
++ /* Copy the data from the client. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os, eventRecord, EventQueue, gcmSIZEOF(gcsQUEUE)
++ ));
++ }
++ else
++ {
++ /* Map record into kernel memory. */
++ gcmkONERROR(gckOS_MapUserPointer(Command->os,
++ EventQueue,
++ gcmSIZEOF(gcsQUEUE),
++ &pointer));
++
++ eventRecord = pointer;
++ }
++
++ /* Append event record to event queue. */
++ gcmkONERROR(gckEVENT_AddList(
++ Command->kernel->eventObj, &eventRecord->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE
++ ));
++
++ /* Next record in the queue. */
++ nextEventRecord = gcmUINT64_TO_PTR(eventRecord->next);
++
++ if (!needCopy)
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os, EventQueue, gcmSIZEOF(gcsQUEUE), (gctPOINTER *) eventRecord
++ ));
++
++ eventRecord = gcvNULL;
++ }
++
++ EventQueue = nextEventRecord;
++ }
++
++ if (Command->kernel->eventObj->queueHead == gcvNULL
++ && Command->kernel->hardware->powerManagement == gcvTRUE
++ )
++ {
++ /* Commit done event by which work thread knows all jobs done. */
++ gcmkVERIFY_OK(
++ gckEVENT_CommitDone(Command->kernel->eventObj, gcvKERNEL_PIXEL));
++ }
++
++ /* Submit events. */
++ status = gckEVENT_Submit(Command->kernel->eventObj, gcvTRUE, gcvFALSE);
++
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkTRACE(
++ gcvLEVEL_INFO,
++ "%s(%d): Intterupted in gckEVENT_Submit",
++ __FUNCTION__, __LINE__
++ );
++ status = gcvSTATUS_OK;
++ }
++ else
++ {
++ gcmkONERROR(status);
++ }
++
++ /* Unmap the command buffer pointer. */
++ if (commandBufferMapped)
++ {
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ commandBufferObject
++ ));
++
++ commandBufferMapped = gcvFALSE;
++ }
++
++ /* Return status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if ((eventRecord != gcvNULL) && !needCopy)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ EventQueue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) eventRecord
++ ));
++ }
++
++ if (contextAcquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Command, gcvFALSE));
++ }
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (sequenceAcquired)
++ {
++ /* Release the context sequence mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
++ }
++#endif
++
++ /* Unmap the command buffer pointer. */
++ if (commandBufferMapped)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ commandBufferObject
++ ));
++ }
++
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Reserve
++**
++** Reserve space in the command queue. Also acquire the command queue mutex.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctSIZE_T RequestedBytes
++** Number of bytes previously reserved.
++**
++** OUTPUT:
++**
++** gctPOINTER * Buffer
++** Pointer to a variable that will receive the address of the reserved
++** space.
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable that will receive the number of bytes
++** available in the command queue.
++*/
++gceSTATUS
++gckCOMMAND_Reserve(
++ IN gckCOMMAND Command,
++ IN gctSIZE_T RequestedBytes,
++ OUT gctPOINTER * Buffer,
++ OUT gctSIZE_T * BufferSize
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gctSIZE_T requiredBytes;
++ gctUINT32 requestedAligned;
++
++ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Compute aligned number of reuested bytes. */
++ requestedAligned = gcmALIGN(RequestedBytes, Command->alignment);
++
++ /* Another WAIT/LINK command sequence will have to be appended after
++ the requested area being reserved. Compute the number of bytes
++ required for WAIT/LINK at the location after the reserved area. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ Command->kernel->hardware,
++ gcvNULL,
++ Command->offset + requestedAligned,
++ &requiredBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Compute total number of bytes required. */
++ requiredBytes += requestedAligned;
++
++ /* Compute number of bytes available in command queue. */
++ bytes = Command->pageSize - Command->offset;
++
++ /* Is there enough space in the current command queue? */
++ if (bytes < requiredBytes)
++ {
++ /* Create a new command queue. */
++ gcmkONERROR(_NewQueue(Command));
++
++ /* Recompute the number of bytes in the new kernel command queue. */
++ bytes = Command->pageSize - Command->offset;
++
++ /* Still not enough space? */
++ if (bytes < requiredBytes)
++ {
++ /* Rare case, not enough room in command queue. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++ }
++
++ /* Return pointer to empty slot command queue. */
++ *Buffer = (gctUINT8 *) Command->logical + Command->offset;
++
++ /* Return number of bytes left in command queue. */
++ *BufferSize = bytes;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Buffer=0x%x *BufferSize=%lu", *Buffer, *BufferSize);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Execute
++**
++** Execute a previously reserved command queue by appending a WAIT/LINK command
++** sequence after it and modifying the last WAIT into a LINK command. The
++** command FIFO mutex will be released whether this function succeeds or not.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctSIZE_T RequestedBytes
++** Number of bytes previously reserved.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Execute(
++ IN gckCOMMAND Command,
++ IN gctSIZE_T RequestedBytes
++ )
++{
++ gceSTATUS status;
++
++ gctPHYS_ADDR waitLinkPhysical;
++ gctUINT8_PTR waitLinkLogical;
++ gctUINT32 waitLinkOffset;
++ gctSIZE_T waitLinkBytes;
++
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitOffset;
++ gctSIZE_T waitBytes;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR execPhysical;
++#endif
++ gctPOINTER execLogical;
++ gctSIZE_T execBytes;
++
++ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Compute offset for WAIT/LINK. */
++ waitLinkOffset = Command->offset + RequestedBytes;
++
++ /* Compute number of bytes left in command queue. */
++ waitLinkBytes = Command->pageSize - waitLinkOffset;
++
++ /* Compute the location if WAIT/LINK command sequence. */
++ waitLinkPhysical = (gctUINT8_PTR) Command->physical + waitLinkOffset;
++ waitLinkLogical = (gctUINT8_PTR) Command->logical + waitLinkOffset;
++
++ /* Append WAIT/LINK in command queue. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ Command->kernel->hardware,
++ waitLinkLogical,
++ waitLinkOffset,
++ &waitLinkBytes,
++ &waitOffset,
++ &waitBytes
++ ));
++
++ /* Compute the location if WAIT command. */
++ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset;
++ waitLogical = waitLinkLogical + waitOffset;
++
++ /* Determine the location to jump to for the command buffer being
++ ** scheduled. */
++ if (Command->newQueue)
++ {
++ /* New command queue, jump to the beginning of it. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ execPhysical = Command->physical;
++#endif
++ execLogical = Command->logical;
++ execBytes = waitLinkOffset + waitLinkBytes;
++ }
++ else
++ {
++ /* Still within the preexisting command queue, jump directly to the
++ reserved area. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ execPhysical = (gctUINT8 *) Command->physical + Command->offset;
++#endif
++ execLogical = (gctUINT8 *) Command->logical + Command->offset;
++ execBytes = RequestedBytes + waitLinkBytes;
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ execPhysical,
++ execLogical,
++ execBytes
++ ));
++#endif
++
++ /* Convert the last WAIT into a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Command->kernel->hardware,
++ Command->waitLogical,
++ execLogical,
++ execBytes,
++ &Command->waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ Command->waitLogical,
++ Command->waitSize,
++ gceDUMP_BUFFER_LINK,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ execLogical,
++ execBytes,
++ gceDUMP_BUFFER_KERNEL,
++ gcvFALSE
++ );
++
++ /* Update the pointer to the last WAIT. */
++ Command->waitPhysical = waitPhysical;
++ Command->waitLogical = waitLogical;
++ Command->waitSize = waitBytes;
++
++ /* Update the command queue. */
++ Command->offset += RequestedBytes + waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ Command->kernel->hardware, Command->logical, Command->offset
++ ));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.execute]");
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Stall
++**
++** The calling thread will be suspended until the command queue has been
++** completed.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++#if gcdNULL_DRIVER
++ /* Do nothing with infinite hardware. */
++ return gcvSTATUS_OK;
++#else
++ gckOS os;
++ gckHARDWARE hardware;
++ gckEVENT eventObject;
++ gceSTATUS status;
++ gctSIGNAL signal = gcvNULL;
++ gctUINT timer = 0;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Extract the gckOS object pointer. */
++ os = Command->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckHARDWARE object pointer. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Extract the gckEVENT object pointer. */
++ eventObject = Command->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObject, gcvOBJ_EVENT);
++
++ /* Allocate the signal. */
++ gcmkONERROR(gckOS_CreateSignal(os, gcvTRUE, &signal));
++
++ /* Append the EVENT command to trigger the signal. */
++ gcmkONERROR(gckEVENT_Signal(eventObject, signal, gcvKERNEL_PIXEL));
++
++ /* Submit the event queue. */
++ gcmkONERROR(gckEVENT_Submit(eventObject, gcvTRUE, FromPower));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.stall]");
++#endif
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ /* Error. */
++ goto OnError;
++ }
++
++ do
++ {
++ /* Wait for the signal. */
++ status = gckOS_WaitSignal(os, signal, gcdGPU_ADVANCETIMER);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT32 idle;
++
++ /* Read idle register. */
++ gcmkVERIFY_OK(gckHARDWARE_GetIdle(
++ hardware, gcvFALSE, &idle
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): idle=%08x",
++ __FUNCTION__, __LINE__, idle
++ );
++
++ gcmkONERROR(gckOS_MemoryBarrier(os, gcvNULL));
++
++#ifdef __QNXNTO__
++ gctUINT32 reg_cmdbuf_fetch;
++ gctUINT32 reg_intr;
++
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(
++ Command->kernel->hardware->os, Command->kernel->core, 0x0664, &reg_cmdbuf_fetch
++ ));
++
++ if (idle == 0x7FFFFFFE)
++ {
++ /*
++ * GPU is idle so there should not be pending interrupts.
++ * Just double check.
++ *
++ * Note that reading interrupt register clears it.
++ * That's why we don't read it in all cases.
++ */
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(
++ Command->kernel->hardware->os, Command->kernel->core, 0x10, &reg_intr
++ ));
++
++ slogf(
++ _SLOG_SETCODE(1, 0),
++ _SLOG_CRITICAL,
++ "GALcore: Stall timeout (idle = 0x%X, command buffer fetch = 0x%X, interrupt = 0x%X)",
++ idle, reg_cmdbuf_fetch, reg_intr
++ );
++ }
++ else
++ {
++ slogf(
++ _SLOG_SETCODE(1, 0),
++ _SLOG_CRITICAL,
++ "GALcore: Stall timeout (idle = 0x%X, command buffer fetch = 0x%X)",
++ idle, reg_cmdbuf_fetch
++ );
++ }
++#endif
++#endif
++ /* Advance timer. */
++ timer += gcdGPU_ADVANCETIMER;
++ }
++ else if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkONERROR(gcvSTATUS_INTERRUPTED);
++ }
++
++ }
++ while (gcmIS_ERROR(status)
++#if gcdGPU_TIMEOUT
++ && (timer < Command->kernel->timeOut)
++#endif
++ );
++
++ /* Bail out on timeout. */
++ if (gcmIS_ERROR(status))
++ {
++ /* Broadcast the stuck GPU. */
++ gcmkONERROR(gckOS_Broadcast(
++ os, hardware, gcvBROADCAST_GPU_STUCK
++ ));
++ }
++
++ /* Delete the signal. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (signal != gcvNULL)
++ {
++ /* Free the signal. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Attach
++**
++** Attach user process.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable that will receive a pointer to a new
++** gckCONTEXT object.
++**
++** gctSIZE_T * StateCount
++** Pointer to a variable that will receive the number of states
++** in the context buffer.
++*/
++gceSTATUS
++gckCOMMAND_Attach(
++ IN gckCOMMAND Command,
++ OUT gckCONTEXT * Context,
++ OUT gctSIZE_T * StateCount,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ acquired = gcvTRUE;
++
++ /* Construct a gckCONTEXT object. */
++ gcmkONERROR(gckCONTEXT_Construct(
++ Command->os,
++ Command->kernel->hardware,
++ ProcessID,
++ Context
++ ));
++
++ /* Return the number of states in the context. */
++ * StateCount = (* Context)->stateCount;
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%x", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release mutex. */
++ if (acquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Detach
++**
++** Detach user process.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gckCONTEXT Context
++** Pointer to a gckCONTEXT object to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Detach(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x Context=0x%x", Command, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ acquired = gcvTRUE;
++
++ /* Construct a gckCONTEXT object. */
++ gcmkONERROR(gckCONTEXT_Destroy(Context));
++
++ if (Command->currContext == Context)
++ {
++ /* Detach from gckCOMMAND object if the destoryed context is current context. */
++ Command->currContext = gcvNULL;
++ }
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release mutex. */
++ if (acquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++/*******************************************************************************
++**
++** gckCOMMAND_DumpExecutingBuffer
++**
++** Dump the command buffer which GPU is executing.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_DumpExecutingBuffer(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctUINT32 gpuAddress;
++ gctSIZE_T pageCount;
++ gctPOINTER entry;
++ gckOS os = Command->os;
++ gckKERNEL kernel = Command->kernel;
++#if gcdLINK_QUEUE_SIZE
++ gctINT pid;
++ gctINT i, rear;
++ gctUINT32 start, end;
++ gctUINT32 dumpFront, dumpRear;
++ gckLINKQUEUE queue = &kernel->hardware->linkQueue;
++ gckLINKQUEUE queueMirror;
++ gctUINT32 bytes;
++ gckLINKDATA linkData;
++#endif
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("**** COMMAND BUF DUMP ****\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(os, kernel->core, 0x664, &gpuAddress));
++
++ gcmkPRINT("DMA Address 0x%08X", gpuAddress);
++
++#if gcdLINK_QUEUE_SIZE
++ /* Duplicate queue because it will be changed.*/
++ gcmkONERROR(gckOS_AllocateMemory(os,
++ sizeof(struct _gckLINKQUEUE),
++ (gctPOINTER *)&queueMirror));
++
++ gcmkONERROR(gckOS_MemCopy(queueMirror,
++ queue,
++ sizeof(struct _gckLINKQUEUE)));
++
++ /* If kernel command buffer link to a context buffer, then link to a user command
++ ** buffer, the second link will be in queue first, so we must fix this.
++ ** In Queue: C1 U1 U2 C2 U3 U4 U5 C3
++ ** Real: C1 X1 U1 C2 U2 U3 U4 C3 U5
++ ** Command buffer X1 which is after C1 is out of queue, so C1 is meaningless.
++ */
++ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, i, &linkData);
++
++ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Can't find it in virtual command buffer list, ignore it. */
++ continue;
++ }
++
++ if (buffer->kernelLogical)
++ {
++ /* It is a context buffer. */
++ if (i == 0)
++ {
++ /* The real command buffer is out, so clear this slot. */
++ linkData->start = 0;
++ linkData->end = 0;
++ linkData->pid = 0;
++ }
++ else
++ {
++ /* switch context buffer and command buffer. */
++ struct _gckLINKDATA tmp = *linkData;
++ gckLINKDATA linkDataPrevious;
++
++ gckLINKQUEUE_GetData(queueMirror, i - 1, &linkDataPrevious);
++ *linkData = *linkDataPrevious;
++ *linkDataPrevious = tmp;
++ }
++ }
++ }
++
++ /* Clear search result. */
++ dumpFront = dumpRear = gcvINFINITE;
++
++ gcmkPRINT("Link Stack:");
++
++ /* Search stuck address in link queue from rear. */
++ rear = gcdLINK_QUEUE_SIZE - 1;
++ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, rear, &linkData);
++
++ start = linkData->start;
++ end = linkData->end;
++ pid = linkData->pid;
++
++ if (gpuAddress >= start && gpuAddress < end)
++ {
++ /* Find latest matched command buffer. */
++ gcmkPRINT(" %d, [%08X - %08X]", pid, start, end);
++
++ /* Initiliaze dump information. */
++ dumpFront = dumpRear = rear;
++ }
++
++ /* Advance to previous one. */
++ rear--;
++
++ if (dumpFront != gcvINFINITE)
++ {
++ break;
++ }
++ }
++
++ if (dumpFront == gcvINFINITE)
++ {
++ /* Can't find matched record in link queue, dump kernel command buffer. */
++ _DumpKernelCommandBuffer(Command);
++
++ /* Free local copy. */
++ gcmkOS_SAFE_FREE(os, queueMirror);
++ return gcvSTATUS_OK;
++ }
++
++ /* Search the last context buffer linked. */
++ while (rear >= 0)
++ {
++ gckLINKQUEUE_GetData(queueMirror, rear, &linkData);
++
++ gcmkPRINT(" %d, [%08X - %08X]",
++ linkData->pid,
++ linkData->start,
++ linkData->end);
++
++ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer);
++
++ if (gcmIS_SUCCESS(status) && buffer->kernelLogical)
++ {
++ /* Find a context buffer. */
++ dumpFront = rear;
++ break;
++ }
++
++ rear--;
++ }
++
++ /* Dump from last context buffer to last command buffer where hang happens. */
++ for (i = dumpFront; i <= dumpRear; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, i, &linkData);
++
++ /* Get gpu address of this command buffer. */
++ gpuAddress = linkData->start;
++ bytes = linkData->end - gpuAddress;
++
++ /* Get the whole buffer. */
++ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkPRINT("Buffer [%08X - %08X] is lost",
++ linkData->start,
++ linkData->end);
++ continue;
++ }
++
++ /* Get kernel logical for dump. */
++ if (buffer->kernelLogical)
++ {
++ /* Get kernel logical directly if it is a context buffer. */
++ entry = buffer->kernelLogical;
++ gcmkPRINT("Context Buffer:");
++ }
++ else
++ {
++ /* Make it accessiable by kernel if it is a user command buffer. */
++ gcmkVERIFY_OK(
++ gckOS_CreateKernelVirtualMapping(buffer->physical,
++ &pageCount,
++ &entry));
++ gcmkPRINT("User Command Buffer:");
++ }
++
++ /* Dump from the entry. */
++ _DumpBuffer(entry + (gpuAddress - buffer->gpuAddress), gpuAddress, bytes);
++
++ /* Release kernel logical address if neccessary. */
++ if (!buffer->kernelLogical)
++ {
++ gcmkVERIFY_OK(gckOS_DestroyKernelVirtualMapping(entry));
++ }
++ }
++
++ /* Free local copy. */
++ gcmkOS_SAFE_FREE(os, queueMirror);
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++#else
++ /* Without link queue information, we don't know the entry of last command
++ ** buffer, just dump the page where GPU stuck. */
++ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CreateKernelVirtualMapping(buffer->physical, &pageCount, &entry));
++
++ if (entry)
++ {
++ gctUINT32 offset = gpuAddress - buffer->gpuAddress;
++ gctPOINTER entryDump = entry;
++
++ /* Dump one pages. */
++ gctUINT32 bytes = 4096;
++
++ /* Align to page. */
++ offset &= 0xfffff000;
++
++ /* Kernel address of page where stall point stay. */
++ entryDump += offset;
++
++ /* Align to page. */
++ gpuAddress &= 0xfffff000;
++
++ gcmkPRINT("User Command Buffer:\n");
++ _DumpBuffer(entryDump, gpuAddress, bytes);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(entry));
++ }
++ else
++ {
++ _DumpKernelCommandBuffer(Command);
++ }
++
++ return gcvSTATUS_OK;
++#endif
++}
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,3677 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++*********************************** Debugging **********************************
++\******************************************************************************/
++
++#define gcvDISABLE_TIMEOUT 1
++#define gcvDUMP_COMMAND_BUFFER 0
++#define gcvDUMP_COMMAND_LINES 0
++
++
++#if gcvDEBUG || defined(EMULATOR) || gcvDISABLE_TIMEOUT
++# define gcvQUEUE_TIMEOUT ~0
++#else
++# define gcvQUEUE_TIMEOUT 10
++#endif
++
++
++/******************************************************************************\
++********************************** Definitions *********************************
++\******************************************************************************/
++
++/* Minimum buffer size. */
++#define gcvMINUMUM_BUFFER \
++ gcmSIZEOF(gcsKERNEL_QUEUE_HEADER) + \
++ gcmSIZEOF(gcsKERNEL_CMDQUEUE) * 2
++
++#define gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \
++ static gceSTATUS \
++ _EventHandler_##Block##_##Number( \
++ IN gckVGKERNEL Kernel \
++ )
++
++#define gcmDEFINE_INTERRUPT_HANDLER(Block, Number) \
++ gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \
++ { \
++ return _EventHandler_Block( \
++ Kernel, \
++ &Kernel->command->taskTable[gcvBLOCK_##Block], \
++ gcvFALSE \
++ ); \
++ }
++
++#define gcmDEFINE_INTERRUPT_HANDLER_ENTRY(Block, Number) \
++ { gcvBLOCK_##Block, _EventHandler_##Block##_##Number }
++
++/* Block interrupt handling table entry. */
++typedef struct _gcsBLOCK_INTERRUPT_HANDLER * gcsBLOCK_INTERRUPT_HANDLER_PTR;
++typedef struct _gcsBLOCK_INTERRUPT_HANDLER
++{
++ gceBLOCK block;
++ gctINTERRUPT_HANDLER handler;
++}
++gcsBLOCK_INTERRUPT_HANDLER;
++
++/* Queue control functions. */
++typedef struct _gcsQUEUE_UPDATE_CONTROL * gcsQUEUE_UPDATE_CONTROL_PTR;
++typedef struct _gcsQUEUE_UPDATE_CONTROL
++{
++ gctOBJECT_HANDLER execute;
++ gctOBJECT_HANDLER update;
++ gctOBJECT_HANDLER lastExecute;
++ gctOBJECT_HANDLER lastUpdate;
++}
++gcsQUEUE_UPDATE_CONTROL;
++
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_FlushMMU(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 oldValue;
++ gckVGHARDWARE hardware = Command->hardware;
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ hardware->pageTableDirty,
++ 0,
++ &oldValue));
++
++ if (oldValue)
++ {
++ /* Page Table is upated, flush mmu before commit. */
++ gcmkONERROR(gckVGHARDWARE_FlushMMU(hardware));
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_WaitForIdle(
++ IN gckVGCOMMAND Command,
++ IN gcsKERNEL_QUEUE_HEADER_PTR Queue
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 idle;
++ gctUINT timeout = 0;
++
++ /* Loop while not idle. */
++ while (Queue->pending)
++ {
++ /* Did we reach the timeout limit? */
++ if (timeout == gcvQUEUE_TIMEOUT)
++ {
++ /* Hardware is probably dead... */
++ return gcvSTATUS_TIMEOUT;
++ }
++
++ /* Sleep for 100ms. */
++ gcmkERR_BREAK(gckOS_Delay(Command->os, 100));
++
++ /* Not the first loop? */
++ if (timeout > 0)
++ {
++ /* Read IDLE register. */
++ gcmkVERIFY_OK(gckVGHARDWARE_GetIdle(Command->hardware, &idle));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_COMMAND,
++ "%s: timeout, IDLE=%08X\n",
++ __FUNCTION__, idle
++ );
++ }
++
++ /* Increment the timeout counter. */
++ timeout += 1;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gctINT32
++_GetNextInterrupt(
++ IN gckVGCOMMAND Command,
++ IN gceBLOCK Block
++ )
++{
++ gctUINT index;
++ gcsBLOCK_TASK_ENTRY_PTR entry;
++ gctINT32 interrupt;
++
++ /* Get the block entry. */
++ entry = &Command->taskTable[Block];
++
++ /* Make sure we have initialized interrupts. */
++ gcmkASSERT(entry->interruptCount > 0);
++
++ /* Decrement the interrupt usage semaphore. */
++ gcmkVERIFY_OK(gckOS_DecrementSemaphore(
++ Command->os, entry->interruptSemaphore
++ ));
++
++ /* Get the value index. */
++ index = entry->interruptIndex;
++
++ /* Get the interrupt value. */
++ interrupt = entry->interruptArray[index];
++
++ /* Must be a valid value. */
++ gcmkASSERT((interrupt >= 0) && (interrupt <= 31));
++
++ /* Advance the index to the next value. */
++ index += 1;
++
++ /* Set the new index. */
++ entry->interruptIndex = (index == entry->interruptCount)
++ ? 0
++ : index;
++
++ /* Return interrupt value. */
++ return interrupt;
++}
++
++
++/******************************************************************************\
++***************************** Task Storage Management **************************
++\******************************************************************************/
++
++/* Minimum task buffer size. */
++#define gcvMIN_TASK_BUFFER \
++( \
++ gcmSIZEOF(gcsTASK_CONTAINER) + 128 \
++)
++
++/* Free list terminator. */
++#define gcvFREE_TASK_TERMINATOR \
++( \
++ (gcsTASK_CONTAINER_PTR) gcmINT2PTR(~0) \
++)
++
++
++/*----------------------------------------------------------------------------*/
++/*------------------- Allocated Task Buffer List Management ------------------*/
++
++static void
++_InsertTaskBuffer(
++ IN gcsTASK_CONTAINER_PTR AddAfter,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR addBefore;
++
++ /* Cannot add before the first buffer. */
++ gcmkASSERT(AddAfter != gcvNULL);
++
++ /* Create a shortcut to the next buffer. */
++ addBefore = AddAfter->allocNext;
++
++ /* Initialize the links. */
++ Buffer->allocPrev = AddAfter;
++ Buffer->allocNext = addBefore;
++
++ /* Link to the previous buffer. */
++ AddAfter->allocNext = Buffer;
++
++ /* Link to the next buffer. */
++ if (addBefore != gcvNULL)
++ {
++ addBefore->allocPrev = Buffer;
++ }
++}
++
++static void
++_RemoveTaskBuffer(
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR prev;
++ gcsTASK_CONTAINER_PTR next;
++
++ /* Cannot remove the first buffer. */
++ gcmkASSERT(Buffer->allocPrev != gcvNULL);
++
++ /* Create shortcuts to the previous and next buffers. */
++ prev = Buffer->allocPrev;
++ next = Buffer->allocNext;
++
++ /* Tail buffer? */
++ if (next == gcvNULL)
++ {
++ /* Remove from the list. */
++ prev->allocNext = gcvNULL;
++ }
++
++ /* Buffer from the middle. */
++ else
++ {
++ prev->allocNext = next;
++ next->allocPrev = prev;
++ }
++}
++
++
++/*----------------------------------------------------------------------------*/
++/*--------------------- Free Task Buffer List Management ---------------------*/
++
++static void
++_AppendToFreeList(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ /* Cannot be a part of the free list already. */
++ gcmkASSERT(Buffer->freePrev == gcvNULL);
++ gcmkASSERT(Buffer->freeNext == gcvNULL);
++
++ /* First buffer to add? */
++ if (Command->taskFreeHead == gcvNULL)
++ {
++ /* Terminate the links. */
++ Buffer->freePrev = gcvFREE_TASK_TERMINATOR;
++ Buffer->freeNext = gcvFREE_TASK_TERMINATOR;
++
++ /* Initialize the list pointer. */
++ Command->taskFreeHead = Command->taskFreeTail = Buffer;
++ }
++
++ /* Not the first, add after the tail. */
++ else
++ {
++ /* Initialize the new tail buffer. */
++ Buffer->freePrev = Command->taskFreeTail;
++ Buffer->freeNext = gcvFREE_TASK_TERMINATOR;
++
++ /* Add after the tail. */
++ Command->taskFreeTail->freeNext = Buffer;
++ Command->taskFreeTail = Buffer;
++ }
++}
++
++static void
++_RemoveFromFreeList(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ /* Has to be a part of the free list. */
++ gcmkASSERT(Buffer->freePrev != gcvNULL);
++ gcmkASSERT(Buffer->freeNext != gcvNULL);
++
++ /* Head buffer? */
++ if (Buffer->freePrev == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Tail buffer as well? */
++ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Reset the list pointer. */
++ Command->taskFreeHead = Command->taskFreeTail = gcvNULL;
++ }
++
++ /* No, just the head. */
++ else
++ {
++ /* Update the head. */
++ Command->taskFreeHead = Buffer->freeNext;
++
++ /* Terminate the next buffer. */
++ Command->taskFreeHead->freePrev = gcvFREE_TASK_TERMINATOR;
++ }
++ }
++
++ /* Not the head. */
++ else
++ {
++ /* Tail buffer? */
++ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Update the tail. */
++ Command->taskFreeTail = Buffer->freePrev;
++
++ /* Terminate the previous buffer. */
++ Command->taskFreeTail->freeNext = gcvFREE_TASK_TERMINATOR;
++ }
++
++ /* A buffer in the middle. */
++ else
++ {
++ /* Remove the buffer from the list. */
++ Buffer->freePrev->freeNext = Buffer->freeNext;
++ Buffer->freeNext->freePrev = Buffer->freePrev;
++ }
++ }
++
++ /* Reset free list pointers. */
++ Buffer->freePrev = gcvNULL;
++ Buffer->freeNext = gcvNULL;
++}
++
++
++/*----------------------------------------------------------------------------*/
++/*-------------------------- Task Buffer Allocation --------------------------*/
++
++static void
++_SplitTaskBuffer(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer,
++ IN gctUINT Size
++ )
++{
++ /* Determine the size of the new buffer. */
++ gctINT splitBufferSize = Buffer->size - Size;
++ gcmkASSERT(splitBufferSize >= 0);
++
++ /* Is the split buffer big enough to become a separate buffer? */
++ if (splitBufferSize >= gcvMIN_TASK_BUFFER)
++ {
++ /* Place the new path data. */
++ gcsTASK_CONTAINER_PTR splitBuffer = (gcsTASK_CONTAINER_PTR)
++ (
++ (gctUINT8_PTR) Buffer + Size
++ );
++
++ /* Set the trimmed buffer size. */
++ Buffer->size = Size;
++
++ /* Initialize the split buffer. */
++ splitBuffer->referenceCount = 0;
++ splitBuffer->size = splitBufferSize;
++ splitBuffer->freePrev = gcvNULL;
++ splitBuffer->freeNext = gcvNULL;
++
++ /* Link in. */
++ _InsertTaskBuffer(Buffer, splitBuffer);
++ _AppendToFreeList(Command, splitBuffer);
++ }
++}
++
++static gceSTATUS
++_AllocateTaskContainer(
++ IN gckVGCOMMAND Command,
++ IN gctUINT Size,
++ OUT gcsTASK_CONTAINER_PTR * Buffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x Size=0x%x, Buffer ==0x%x", Command, Size, Buffer);
++
++ /* Verify arguments. */
++ gcmkVERIFY_ARGUMENT(Buffer != gcvNULL);
++
++ do
++ {
++ gcsTASK_STORAGE_PTR storage;
++ gcsTASK_CONTAINER_PTR buffer;
++
++ /* Adjust the size. */
++ Size += gcmSIZEOF(gcsTASK_CONTAINER);
++
++ /* Adjust the allocation size if not big enough. */
++ if (Size > Command->taskStorageUsable)
++ {
++ Command->taskStorageGranularity
++ = gcmALIGN(Size + gcmSIZEOF(gcsTASK_STORAGE), 1024);
++
++ Command->taskStorageUsable
++ = Command->taskStorageGranularity - gcmSIZEOF(gcsTASK_STORAGE);
++ }
++
++ /* Is there a free buffer available? */
++ else if (Command->taskFreeHead != gcvNULL)
++ {
++ /* Set the initial free buffer. */
++ gcsTASK_CONTAINER_PTR buffer = Command->taskFreeHead;
++
++ do
++ {
++ /* Is the buffer big enough? */
++ if (buffer->size >= Size)
++ {
++ /* Remove the buffer from the free list. */
++ _RemoveFromFreeList(Command, buffer);
++
++ /* Split the buffer. */
++ _SplitTaskBuffer(Command, buffer, Size);
++
++ /* Set the result. */
++ * Buffer = buffer;
++
++ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++
++ /* Get the next free buffer. */
++ buffer = buffer->freeNext;
++ }
++ while (buffer != gcvFREE_TASK_TERMINATOR);
++ }
++
++ /* Allocate a container. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Command->os,
++ Command->taskStorageGranularity,
++ (gctPOINTER *) &storage
++ ));
++
++ /* Link in the storage buffer. */
++ storage->next = Command->taskStorage;
++ Command->taskStorage = storage;
++
++ /* Place the task buffer. */
++ buffer = (gcsTASK_CONTAINER_PTR) (storage + 1);
++
++ /* Determine the size of the buffer. */
++ buffer->size
++ = Command->taskStorageGranularity
++ - gcmSIZEOF(gcsTASK_STORAGE);
++
++ /* Initialize the task buffer. */
++ buffer->referenceCount = 0;
++ buffer->allocPrev = gcvNULL;
++ buffer->allocNext = gcvNULL;
++ buffer->freePrev = gcvNULL;
++ buffer->freeNext = gcvNULL;
++
++ /* Split the buffer. */
++ _SplitTaskBuffer(Command, buffer, Size);
++
++ /* Set the result. */
++ * Buffer = buffer;
++
++ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++static void
++_FreeTaskContainer(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR prev;
++ gcsTASK_CONTAINER_PTR next;
++ gcsTASK_CONTAINER_PTR merged;
++
++ gctSIZE_T mergedSize;
++
++ /* Verify arguments. */
++ gcmkASSERT(Buffer != gcvNULL);
++ gcmkASSERT(Buffer->freePrev == gcvNULL);
++ gcmkASSERT(Buffer->freeNext == gcvNULL);
++
++ /* Get shortcuts to the previous and next path data buffers. */
++ prev = Buffer->allocPrev;
++ next = Buffer->allocNext;
++
++ /* Is the previous path data buffer already free? */
++ if (prev && prev->freeNext)
++ {
++ /* The previous path data buffer is the one that remains. */
++ merged = prev;
++
++ /* Is the next path data buffer already free? */
++ if (next && next->freeNext)
++ {
++ /* Merge all three path data buffers into the previous. */
++ mergedSize = prev->size + Buffer->size + next->size;
++
++ /* Remove the next path data buffer. */
++ _RemoveFromFreeList(Command, next);
++ _RemoveTaskBuffer(next);
++ }
++ else
++ {
++ /* Merge the current path data buffer into the previous. */
++ mergedSize = prev->size + Buffer->size;
++ }
++
++ /* Delete the current path data buffer. */
++ _RemoveTaskBuffer(Buffer);
++
++ /* Set new size. */
++ merged->size = mergedSize;
++ }
++ else
++ {
++ /* The current path data buffer is the one that remains. */
++ merged = Buffer;
++
++ /* Is the next buffer already free? */
++ if (next && next->freeNext)
++ {
++ /* Merge the next into the current. */
++ mergedSize = Buffer->size + next->size;
++
++ /* Remove the next buffer. */
++ _RemoveFromFreeList(Command, next);
++ _RemoveTaskBuffer(next);
++
++ /* Set new size. */
++ merged->size = mergedSize;
++ }
++
++ /* Add the current buffer into the free list. */
++ _AppendToFreeList(Command, merged);
++ }
++}
++
++gceSTATUS
++_RemoveRecordFromProcesDB(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_HEADER_PTR Task
++ )
++{
++ gcsTASK_PTR task = (gcsTASK_PTR)((gctUINT8_PTR)Task - sizeof(gcsTASK));
++ gcsTASK_FREE_VIDEO_MEMORY_PTR freeVideoMemory;
++ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR unlockVideoMemory;
++ gctINT pid;
++ gctUINT32 size;
++
++ /* Get the total size of all tasks. */
++ size = task->size;
++
++ gcmkVERIFY_OK(gckOS_GetProcessID((gctUINT32_PTR)&pid));
++
++ do
++ {
++ switch (Task->id)
++ {
++ case gcvTASK_FREE_VIDEO_MEMORY:
++ freeVideoMemory = (gcsTASK_FREE_VIDEO_MEMORY_PTR)Task;
++
++ /* Remove record from process db. */
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Command->kernel->kernel,
++ pid,
++ gcvDB_VIDEO_MEMORY,
++ gcmUINT64_TO_PTR(freeVideoMemory->node)));
++
++ /* Advance to next task. */
++ size -= sizeof(gcsTASK_FREE_VIDEO_MEMORY);
++ Task = (gcsTASK_HEADER_PTR)(freeVideoMemory + 1);
++
++ break;
++ case gcvTASK_UNLOCK_VIDEO_MEMORY:
++ unlockVideoMemory = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR)Task;
++
++ /* Remove record from process db. */
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Command->kernel->kernel,
++ pid,
++ gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmUINT64_TO_PTR(unlockVideoMemory->node)));
++
++ /* Advance to next task. */
++ size -= sizeof(gcsTASK_UNLOCK_VIDEO_MEMORY);
++ Task = (gcsTASK_HEADER_PTR)(unlockVideoMemory + 1);
++
++ break;
++ default:
++ /* Skip the whole task. */
++ size = 0;
++ break;
++ }
++ }
++ while(size);
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++********************************* Task Scheduling ******************************
++\******************************************************************************/
++
++static gceSTATUS
++_ScheduleTasks(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable,
++ IN gctUINT8_PTR PreviousEnd
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gctINT block;
++ gcsTASK_CONTAINER_PTR container;
++ gcsTASK_MASTER_ENTRY_PTR userTaskEntry;
++ gcsBLOCK_TASK_ENTRY_PTR kernelTaskEntry;
++ gcsTASK_PTR userTask;
++ gctUINT8_PTR kernelTask;
++ gctINT32 interrupt;
++ gctUINT8_PTR eventCommand;
++
++ /* Nothing to schedule? */
++ if (TaskTable->size == 0)
++ {
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->taskMutex,
++ gcvINFINITE
++ ));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ do
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " number of tasks scheduled = %d\n"
++ " size of event data in bytes = %d\n",
++ TaskTable->count,
++ TaskTable->size
++ );
++
++ /* Allocate task buffer. */
++ gcmkERR_BREAK(_AllocateTaskContainer(
++ Command,
++ TaskTable->size,
++ &container
++ ));
++
++ /* Determine the task data pointer. */
++ kernelTask = (gctUINT8_PTR) (container + 1);
++
++ /* Initialize the reference count. */
++ container->referenceCount = TaskTable->count;
++
++ /* Process tasks. */
++ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1)
++ {
++ /* Get the current user table entry. */
++ userTaskEntry = &TaskTable->table[block];
++
++ /* Are there tasks scheduled? */
++ if (userTaskEntry->head == gcvNULL)
++ {
++ /* No, skip to the next block. */
++ continue;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " processing tasks for block %d\n",
++ block
++ );
++
++ /* Get the current kernel table entry. */
++ kernelTaskEntry = &Command->taskTable[block];
++
++ /* Are there tasks for the current block scheduled? */
++ if (kernelTaskEntry->container == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " first task container for the block added\n",
++ block
++ );
++
++ /* Nothing yet, set the container buffer pointer. */
++ kernelTaskEntry->container = container;
++ kernelTaskEntry->task = (gcsTASK_HEADER_PTR) kernelTask;
++ }
++
++ /* Yes, append to the end. */
++ else
++ {
++ kernelTaskEntry->link->cotainer = container;
++ kernelTaskEntry->link->task = (gcsTASK_HEADER_PTR) kernelTask;
++ }
++
++ /* Set initial task. */
++ userTask = userTaskEntry->head;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " copying user tasks over to the kernel\n"
++ );
++
++ /* Copy tasks. */
++ do
++ {
++ gcsTASK_HEADER_PTR taskHeader = (gcsTASK_HEADER_PTR) (userTask + 1);
++
++ gcmkVERIFY_OK(_RemoveRecordFromProcesDB(Command, taskHeader));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " task ID = %d, size = %d\n",
++ ((gcsTASK_HEADER_PTR) (userTask + 1))->id,
++ userTask->size
++ );
++
++#ifdef __QNXNTO__
++ if (taskHeader->id == gcvTASK_SIGNAL)
++ {
++ ((gcsTASK_SIGNAL_PTR)taskHeader)->coid = TaskTable->coid;
++ ((gcsTASK_SIGNAL_PTR)taskHeader)->rcvid = TaskTable->rcvid;
++ }
++#endif /* __QNXNTO__ */
++ /* Copy the task data. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ kernelTask, taskHeader, userTask->size
++ ));
++
++ /* Advance to the next task. */
++ kernelTask += userTask->size;
++ userTask = userTask->next;
++ }
++ while (userTask != gcvNULL);
++
++ /* Update link pointer in the header. */
++ kernelTaskEntry->link = (gcsTASK_LINK_PTR) kernelTask;
++
++ /* Initialize link task. */
++ kernelTaskEntry->link->id = gcvTASK_LINK;
++ kernelTaskEntry->link->cotainer = gcvNULL;
++ kernelTaskEntry->link->task = gcvNULL;
++
++ /* Advance the task data pointer. */
++ kernelTask += gcmSIZEOF(gcsTASK_LINK);
++ }
++ }
++ while (gcvFALSE);
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->taskMutex
++ ));
++
++ /* Assign interrupts to the blocks. */
++ eventCommand = PreviousEnd;
++
++ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1)
++ {
++ /* Get the current user table entry. */
++ userTaskEntry = &TaskTable->table[block];
++
++ /* Are there tasks scheduled? */
++ if (userTaskEntry->head == gcvNULL)
++ {
++ /* No, skip to the next block. */
++ continue;
++ }
++
++ /* Get the interrupt number. */
++ interrupt = _GetNextInterrupt(Command, block);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): block = %d interrupt = %d\n",
++ __FUNCTION__, __LINE__,
++ block, interrupt
++ );
++
++ /* Determine the command position. */
++ eventCommand -= Command->info.eventCommandSize;
++
++ /* Append an EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, eventCommand, block, interrupt, gcvNULL
++ ));
++ }
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++******************************** Memory Management *****************************
++\******************************************************************************/
++
++static gceSTATUS
++_HardwareToKernel(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM memory;
++ gctUINT32 offset;
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY
++ gctUINT32 nodePhysical;
++#endif
++ status = gcvSTATUS_OK;
++ /* Assume a non-virtual node and get the pool manager object. */
++ memory = Node->VidMem.memory;
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY
++ nodePhysical = memory->baseAddress
++ + Node->VidMem.offset
++ + Node->VidMem.alignment;
++
++ if (Node->VidMem.kernelVirtual == gcvNULL)
++ {
++ status = gckOS_MapPhysical(Os,
++ nodePhysical,
++ Node->VidMem.bytes,
++ (gctPOINTER *)&Node->VidMem.kernelVirtual);
++
++ if (gcmkIS_ERROR(status))
++ {
++ return status;
++ }
++ }
++
++ offset = Address - nodePhysical;
++ *KernelPointer = (gctPOINTER)((gctUINT8_PTR)Node->VidMem.kernelVirtual + offset);
++#else
++ /* Determine the header offset within the pool it is allocated in. */
++ offset = Address - memory->baseAddress;
++
++ /* Translate the offset into the kernel side pointer. */
++ status = gckOS_GetKernelLogicalEx(
++ Os,
++ gcvCORE_VG,
++ offset,
++ KernelPointer
++ );
++#endif
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_ConvertUserCommandBufferPointer(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR UserCommandBuffer,
++ OUT gcsCMDBUFFER_PTR * KernelCommandBuffer
++ )
++{
++ gceSTATUS status, last;
++ gcsCMDBUFFER_PTR mappedUserCommandBuffer = gcvNULL;
++
++ do
++ {
++ gctUINT32 headerAddress;
++
++ /* Map the command buffer structure into the kernel space. */
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ UserCommandBuffer,
++ gcmSIZEOF(gcsCMDBUFFER),
++ (gctPOINTER *) &mappedUserCommandBuffer
++ ));
++
++ /* Determine the address of the header. */
++ headerAddress
++ = mappedUserCommandBuffer->address
++ - mappedUserCommandBuffer->bufferOffset;
++
++ /* Translate the logical address to the kernel space. */
++ gcmkERR_BREAK(_HardwareToKernel(
++ Command->os,
++ gcmUINT64_TO_PTR(mappedUserCommandBuffer->node),
++ headerAddress,
++ (gctPOINTER *) KernelCommandBuffer
++ ));
++ }
++ while (gcvFALSE);
++
++ /* Unmap the user command buffer. */
++ if (mappedUserCommandBuffer != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_UnmapUserPointer(
++ Command->os,
++ UserCommandBuffer,
++ gcmSIZEOF(gcsCMDBUFFER),
++ mappedUserCommandBuffer
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_AllocateLinear(
++ IN gckVGCOMMAND Command,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ OUT gcuVIDMEM_NODE_PTR * Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ gceSTATUS status, last;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctUINT32 address = (gctUINT32)~0;
++
++ do
++ {
++ gcePOOL pool;
++ gctPOINTER logical;
++
++ /* Allocate from the system pool. */
++ pool = gcvPOOL_SYSTEM;
++
++ /* Allocate memory. */
++ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory(
++ Command->kernel->kernel, &pool,
++ Size, Alignment,
++ gcvSURF_TYPE_UNKNOWN,
++ &node
++ ));
++
++ /* Do not accept virtual pools for now because we don't handle the
++ kernel pointer translation at the moment. */
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ /* Lock the command buffer. */
++ gcmkERR_BREAK(gckVIDMEM_Lock(
++ Command->kernel->kernel,
++ node,
++ gcvFALSE,
++ &address
++ ));
++
++ /* Translate the logical address to the kernel space. */
++ gcmkERR_BREAK(_HardwareToKernel(
++ Command->os,
++ node,
++ address,
++ &logical
++ ));
++
++ /* Set return values. */
++ * Node = node;
++ * Address = address;
++ * Logical = logical;
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Unlock the command buffer. */
++ if (address != ~0)
++ {
++ gcmkCHECK_STATUS(gckVIDMEM_Unlock(
++ Command->kernel->kernel, node, gcvSURF_TYPE_UNKNOWN, gcvNULL
++ ));
++ }
++
++ /* Free the command buffer. */
++ gcmkCHECK_STATUS(gckVIDMEM_Free(
++ node
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_FreeLinear(
++ IN gckVGKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Unlock the linear buffer. */
++ gcmkERR_BREAK(gckVIDMEM_Unlock(Kernel->kernel, Node, gcvSURF_TYPE_UNKNOWN, gcvNULL));
++
++ /* Free the linear buffer. */
++ gcmkERR_BREAK(gckVIDMEM_Free(Node));
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++_AllocateCommandBuffer(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer
++ )
++{
++ gceSTATUS status, last;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++
++ do
++ {
++ gctUINT alignedHeaderSize;
++ gctUINT requestedSize;
++ gctUINT allocationSize;
++ gctUINT32 address = 0;
++ gcsCMDBUFFER_PTR commandBuffer;
++ gctUINT8_PTR endCommand;
++
++ /* Determine the aligned header size. */
++ alignedHeaderSize
++ = gcmALIGN(gcmSIZEOF(gcsCMDBUFFER), Command->info.addressAlignment);
++
++ /* Align the requested size. */
++ requestedSize
++ = gcmALIGN(Size, Command->info.commandAlignment);
++
++ /* Determine the size of the buffer to allocate. */
++ allocationSize
++ = alignedHeaderSize
++ + requestedSize
++ + Command->info.staticTailSize;
++
++ /* Allocate the command buffer. */
++ gcmkERR_BREAK(_AllocateLinear(
++ Command,
++ allocationSize,
++ Command->info.addressAlignment,
++ &node,
++ &address,
++ (gctPOINTER *) &commandBuffer
++ ));
++
++ /* Initialize the structure. */
++ commandBuffer->completion = gcvVACANT_BUFFER;
++ commandBuffer->node = gcmPTR_TO_UINT64(node);
++ commandBuffer->address = address + alignedHeaderSize;
++ commandBuffer->bufferOffset = alignedHeaderSize;
++ commandBuffer->size = requestedSize;
++ commandBuffer->offset = requestedSize;
++ commandBuffer->nextAllocated = gcvNULL;
++ commandBuffer->nextSubBuffer = gcvNULL;
++
++ /* Determine the data count. */
++ commandBuffer->dataCount
++ = (requestedSize + Command->info.staticTailSize)
++ / Command->info.commandAlignment;
++
++ /* Determine the location of the END command. */
++ endCommand
++ = (gctUINT8_PTR) commandBuffer
++ + alignedHeaderSize
++ + requestedSize;
++
++ /* Append an END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command,
++ endCommand,
++ Command->info.feBufferInt,
++ gcvNULL
++ ));
++
++ /* Set the return pointer. */
++ * CommandBuffer = commandBuffer;
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Free the command buffer. */
++ gcmkCHECK_STATUS(_FreeLinear(Command->kernel, node));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_FreeCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ /* Free the buffer. */
++ status = _FreeLinear(Kernel, gcmUINT64_TO_PTR(CommandBuffer->node));
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++****************************** TS Overflow Handler *****************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_TSOverflow(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): **** TS OVERFLOW ENCOUNTERED ****\n",
++ __FUNCTION__, __LINE__
++ );
++
++ return gcvSTATUS_OK;
++}
++
++
++/******************************************************************************\
++****************************** Bus Error Handler *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_BusError(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): **** BUS ERROR ENCOUNTERED ****\n",
++ __FUNCTION__, __LINE__
++ );
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++****************************** Power Stall Handler *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_PowerStall(
++ IN gckVGKERNEL Kernel
++ )
++{
++ /* Signal. */
++ return gckOS_Signal(
++ Kernel->os,
++ Kernel->command->powerStallSignal,
++ gcvTRUE);
++}
++
++/******************************************************************************\
++******************************** Task Routines *********************************
++\******************************************************************************/
++
++typedef gceSTATUS (* gctTASKROUTINE) (
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskLink(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskCluster(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskIncrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskDecrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskSignal(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskLockdown(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskUnlockVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskFreeVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskFreeContiguousMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskUnmapUserMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gctTASKROUTINE _taskRoutine[] =
++{
++ _TaskLink, /* gcvTASK_LINK */
++ _TaskCluster, /* gcvTASK_CLUSTER */
++ _TaskIncrement, /* gcvTASK_INCREMENT */
++ _TaskDecrement, /* gcvTASK_DECREMENT */
++ _TaskSignal, /* gcvTASK_SIGNAL */
++ _TaskLockdown, /* gcvTASK_LOCKDOWN */
++ _TaskUnlockVideoMemory, /* gcvTASK_UNLOCK_VIDEO_MEMORY */
++ _TaskFreeVideoMemory, /* gcvTASK_FREE_VIDEO_MEMORY */
++ _TaskFreeContiguousMemory, /* gcvTASK_FREE_CONTIGUOUS_MEMORY */
++ _TaskUnmapUserMemory, /* gcvTASK_UNMAP_USER_MEMORY */
++};
++
++static gceSTATUS
++_TaskLink(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ /* Cast the task pointer. */
++ gcsTASK_LINK_PTR task = (gcsTASK_LINK_PTR) TaskHeader->task;
++
++ /* Save the pointer to the container. */
++ gcsTASK_CONTAINER_PTR container = TaskHeader->container;
++
++ /* No more tasks in the list? */
++ if (task->task == gcvNULL)
++ {
++ /* Reset the entry. */
++ TaskHeader->container = gcvNULL;
++ TaskHeader->task = gcvNULL;
++ TaskHeader->link = gcvNULL;
++ }
++ else
++ {
++ /* Update the entry. */
++ TaskHeader->container = task->cotainer;
++ TaskHeader->task = task->task;
++ }
++
++ /* Decrement the task buffer reference. */
++ gcmkASSERT(container->referenceCount >= 0);
++ if (container->referenceCount == 0)
++ {
++ /* Free the container. */
++ _FreeTaskContainer(Command, container);
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_TaskCluster(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ /* Cast the task pointer. */
++ gcsTASK_CLUSTER_PTR cluster = (gcsTASK_CLUSTER_PTR) TaskHeader->task;
++
++ /* Get the number of tasks. */
++ gctUINT taskCount = cluster->taskCount;
++
++ /* Advance to the next task. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (cluster + 1);
++
++ /* Perform all tasks in the cluster. */
++ while (taskCount)
++ {
++ /* Perform the current task. */
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ Command,
++ TaskHeader
++ ));
++
++ /* Update the task count. */
++ taskCount -= 1;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskIncrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_INCREMENT_PTR task = (gcsTASK_INCREMENT_PTR) TaskHeader->task;
++
++ /* Convert physical into logical address. */
++ gctUINT32_PTR logical;
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->address,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &logical
++ ));
++
++ /* Increment data. */
++ (* logical) += 1;
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(gckOS_UnmapPhysical(
++ Command->os,
++ logical,
++ gcmSIZEOF(gctUINT32)
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskDecrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_DECREMENT_PTR task = (gcsTASK_DECREMENT_PTR) TaskHeader->task;
++
++ /* Convert physical into logical address. */
++ gctUINT32_PTR logical;
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->address,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &logical
++ ));
++
++ /* Decrement data. */
++ (* logical) -= 1;
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(gckOS_UnmapPhysical(
++ Command->os,
++ logical,
++ gcmSIZEOF(gctUINT32)
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskSignal(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_SIGNAL_PTR task = (gcsTASK_SIGNAL_PTR) TaskHeader->task;
++
++
++ /* Map the signal into kernel space. */
++#ifdef __QNXNTO__
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, task->signal, task->rcvid, task->coid
++ ));
++#else
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, task->signal, task->process
++ ));
++#endif /* __QNXNTO__ */
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskLockdown(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++ gctUINT32_PTR userCounter = gcvNULL;
++ gctUINT32_PTR kernelCounter = gcvNULL;
++ gctSIGNAL signal = gcvNULL;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_LOCKDOWN_PTR task = (gcsTASK_LOCKDOWN_PTR) TaskHeader->task;
++
++ /* Convert physical addresses into logical. */
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->userCounter,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &userCounter
++ ));
++
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->kernelCounter,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &kernelCounter
++ ));
++
++ /* Update the kernel counter. */
++ (* kernelCounter) += 1;
++
++ /* Are the counters equal? */
++ if ((* userCounter) == (* kernelCounter))
++ {
++ /* Map the signal into kernel space. */
++ gcmkERR_BREAK(gckOS_MapSignal(
++ Command->os, task->signal, task->process, &signal
++ ));
++
++ if (signal == gcvNULL)
++ {
++ /* Signal. */
++ gcmkERR_BREAK(gckOS_Signal(
++ Command->os, task->signal, gcvTRUE
++ ));
++ }
++ else
++ {
++ /* Signal. */
++ gcmkERR_BREAK(gckOS_Signal(
++ Command->os, signal, gcvTRUE
++ ));
++ }
++ }
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Destroy the mapped signal. */
++ if (signal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, signal
++ ));
++ }
++
++ /* Unmap the physical memory. */
++ if (kernelCounter != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapPhysical(
++ Command->os,
++ kernelCounter,
++ gcmSIZEOF(gctUINT32)
++ ));
++ }
++
++ if (userCounter != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapPhysical(
++ Command->os,
++ userCounter,
++ gcmSIZEOF(gctUINT32)
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskUnlockVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR task
++ = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR) TaskHeader->task;
++
++ /* Unlock video memory. */
++ gcmkERR_BREAK(gckVIDMEM_Unlock(
++ Command->kernel->kernel,
++ gcmUINT64_TO_PTR(task->node),
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskFreeVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_FREE_VIDEO_MEMORY_PTR task
++ = (gcsTASK_FREE_VIDEO_MEMORY_PTR) TaskHeader->task;
++
++ /* Free video memory. */
++ gcmkERR_BREAK(gckVIDMEM_Free(gcmUINT64_TO_PTR(task->node)));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskFreeContiguousMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR task
++ = (gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR) TaskHeader->task;
++
++ /* Free contiguous memory. */
++ gcmkERR_BREAK(gckOS_FreeContiguous(
++ Command->os, task->physical, task->logical, task->bytes
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskUnmapUserMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_UNMAP_USER_MEMORY_PTR task
++ = (gcsTASK_UNMAP_USER_MEMORY_PTR) TaskHeader->task;
++
++ /* Unmap the user memory. */
++ gcmkERR_BREAK(gckOS_UnmapUserMemory(
++ Command->os, gcvCORE_VG, task->memory, task->size, task->info, task->address
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++/******************************************************************************\
++************ Hardware Block Interrupt Handlers For Scheduled Events ************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_Block(
++ IN gckVGKERNEL Kernel,
++ IN gcsBLOCK_TASK_ENTRY_PTR TaskHeader,
++ IN gctBOOL ProcessAll
++ )
++{
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Kernel=0x%x TaskHeader=0x%x ProcessAll=0x%x", Kernel, TaskHeader, ProcessAll);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ do
++ {
++ gckVGCOMMAND command;
++
++ /* Get the command buffer object. */
++ command = Kernel->command;
++
++ /* Increment the interrupt usage semaphore. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ command->os, TaskHeader->interruptSemaphore
++ ));
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ command->os,
++ command->taskMutex,
++ gcvINFINITE
++ ));
++
++ /* Verify inputs. */
++ gcmkASSERT(TaskHeader != gcvNULL);
++ gcmkASSERT(TaskHeader->container != gcvNULL);
++ gcmkASSERT(TaskHeader->task != gcvNULL);
++ gcmkASSERT(TaskHeader->link != gcvNULL);
++
++ /* Process tasks. */
++ do
++ {
++ /* Process the current task. */
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ command,
++ TaskHeader
++ ));
++
++ /* Is the next task is LINK? */
++ if (TaskHeader->task->id == gcvTASK_LINK)
++ {
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ command,
++ TaskHeader
++ ));
++
++ /* Done. */
++ break;
++ }
++ }
++ while (ProcessAll);
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ command->os,
++ command->taskMutex
++ ));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gcmDECLARE_INTERRUPT_HANDLER(COMMAND, 0)
++{
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Kernel=0x%x ", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++
++ do
++ {
++ gckVGCOMMAND command;
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++ gcsKERNEL_CMDQUEUE_PTR entry;
++ gctUINT entryCount;
++
++ /* Get the command buffer object. */
++ command = Kernel->command;
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ command->os,
++ command->queueMutex,
++ gcvINFINITE
++ ));
++
++ /* Get the current queue. */
++ queueTail = command->queueTail;
++
++ /* Get the current queue entry. */
++ entry = queueTail->currentEntry;
++
++ /* Get the number of entries in the queue. */
++ entryCount = queueTail->pending;
++
++ /* Process all entries. */
++ while (gcvTRUE)
++ {
++ /* Call post-execution function. */
++ status = entry->handler(Kernel, entry);
++
++ /* Failed? */
++ if (gcmkIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR,
++ gcvZONE_COMMAND,
++ "[%s] line %d: post action failed.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Executed the next buffer? */
++ if (status == gcvSTATUS_EXECUTED)
++ {
++ /* Update the queue. */
++ queueTail->pending = entryCount;
++ queueTail->currentEntry = entry;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++
++ /* Break out of the loop. */
++ break;
++ }
++
++ /* Advance to the next entry. */
++ entry += 1;
++ entryCount -= 1;
++
++ /* Last entry? */
++ if (entryCount == 0)
++ {
++ /* Reset the queue to idle. */
++ queueTail->pending = 0;
++
++ /* Get a shortcut to the queue to merge with. */
++ mergeQueue = command->mergeQueue;
++
++ /* Merge the queues if necessary. */
++ if (mergeQueue != queueTail)
++ {
++ gcmkASSERT(mergeQueue < queueTail);
++ gcmkASSERT(mergeQueue->next == queueTail);
++
++ mergeQueue->size
++ += gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ + queueTail->size;
++
++ mergeQueue->next = queueTail->next;
++ }
++
++ /* Advance to the next queue. */
++ queueTail = queueTail->next;
++
++ /* Did it wrap around? */
++ if (command->queue == queueTail)
++ {
++ /* Reset merge queue. */
++ command->mergeQueue = queueTail;
++ }
++
++ /* Set new queue. */
++ command->queueTail = queueTail;
++
++ /* Is the next queue scheduled? */
++ if (queueTail->pending > 0)
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* The first entry must be a command buffer. */
++ commandBuffer = queueTail->currentEntry->commandBuffer;
++
++ /* Start the command processor. */
++ status = gckVGHARDWARE_Execute(
++ command->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Failed? */
++ if (gcmkIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR,
++ gcvZONE_COMMAND,
++ "[%s] line %d: failed to start the next queue.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ }
++ else
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(
++ Kernel->command->hardware, gcvPOWER_IDLE_BROADCAST
++ );
++ }
++
++ /* Break out of the loop. */
++ break;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ command->os,
++ command->queueMutex
++ ));
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/* Define standard block interrupt handlers. */
++gcmDEFINE_INTERRUPT_HANDLER(TESSELLATOR, 0)
++gcmDEFINE_INTERRUPT_HANDLER(VG, 0)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 0)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 1)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 2)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 3)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 4)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 5)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 6)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 7)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 8)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 9)
++
++/* The entries in the array are arranged by event priority. */
++static gcsBLOCK_INTERRUPT_HANDLER _blockHandlers[] =
++{
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(TESSELLATOR, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(VG, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 1),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 2),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 3),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 4),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 5),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 6),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 7),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 8),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 9),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(COMMAND, 0),
++};
++
++
++/******************************************************************************\
++************************* Static Command Buffer Handlers ***********************
++\******************************************************************************/
++
++static gceSTATUS
++_UpdateStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_ExecuteStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Cast the command buffer header. */
++ commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateStaticCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UpdateLastStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++#if gcvDEBUG || gcdFORCE_MESSAGES
++ /* Get the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Validate the command buffer. */
++ gcmkASSERT(commandBuffer->completion != gcvNULL);
++ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER);
++
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): processing all tasks scheduled for FE.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Perform scheduled tasks. */
++ return _EventHandler_Block(
++ Kernel,
++ &Kernel->command->taskTable[gcvBLOCK_COMMAND],
++ gcvTRUE
++ );
++}
++
++static gceSTATUS
++_ExecuteLastStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateLastStaticCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++************************* Dynamic Command Buffer Handlers **********************
++\******************************************************************************/
++
++static gceSTATUS
++_UpdateDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_ExecuteDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateDynamicCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UpdateLastDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++#if gcvDEBUG || gcdFORCE_MESSAGES
++ /* Get the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Validate the command buffer. */
++ gcmkASSERT(commandBuffer->completion != gcvNULL);
++ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER);
++
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): processing all tasks scheduled for FE.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Perform scheduled tasks. */
++ return _EventHandler_Block(
++ Kernel,
++ &Kernel->command->taskTable[gcvBLOCK_COMMAND],
++ gcvTRUE
++ );
++}
++
++static gceSTATUS
++_ExecuteLastDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateLastDynamicCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++********************************* Other Handlers *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_FreeKernelCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ /* Free the command buffer. */
++ status = _FreeCommandBuffer(Kernel, Entry->commandBuffer);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++******************************* Queue Management *******************************
++\******************************************************************************/
++
++#if gcvDUMP_COMMAND_BUFFER
++static void
++_DumpCommandQueue(
++ IN gckVGCOMMAND Command,
++ IN gcsKERNEL_QUEUE_HEADER_PTR QueueHeader,
++ IN gctUINT EntryCount
++ )
++{
++ gcsKERNEL_CMDQUEUE_PTR entry;
++ gctUINT queueIndex;
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ static gctUINT arrayCount = 0;
++#endif
++
++ /* Is dumpinng enabled? */
++ if (!Commad->enableDumping)
++ {
++ return;
++ }
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ "COMMAND QUEUE DUMP: %d entries\n", EntryCount
++ );
++#endif
++
++ /* Get the pointer to the first entry. */
++ entry = QueueHeader->currentEntry;
++
++ /* Iterate through the queue. */
++ for (queueIndex = 0; queueIndex < EntryCount; queueIndex += 1)
++ {
++ gcsCMDBUFFER_PTR buffer;
++ gctUINT bufferCount;
++ gctUINT bufferIndex;
++ gctUINT i, count;
++ gctUINT size;
++ gctUINT32_PTR data;
++
++#if gcvDUMP_COMMAND_LINES
++ gctUINT lineNumber;
++#endif
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ "ENTRY %d\n", queueIndex
++ );
++#endif
++
++ /* Reset the count. */
++ bufferCount = 0;
++
++ /* Set the initial buffer. */
++ buffer = entry->commandBuffer;
++
++ /* Loop through all subbuffers. */
++ while (buffer)
++ {
++ /* Update the count. */
++ bufferCount += 1;
++
++ /* Advance to the next subbuffer. */
++ buffer = buffer->nextSubBuffer;
++ }
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ if (bufferCount > 1)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER SET: %d buffers.\n",
++ bufferCount
++ );
++ }
++#endif
++
++ /* Reset the buffer index. */
++ bufferIndex = 0;
++
++ /* Set the initial buffer. */
++ buffer = entry->commandBuffer;
++
++ /* Loop through all subbuffers. */
++ while (buffer)
++ {
++ /* Determine the size of the buffer. */
++ size = buffer->dataCount * Command->info.commandAlignment;
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ /* A single buffer? */
++ if (bufferCount == 1)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER: count=%d (0x%X), size=%d bytes @ %08X.\n",
++ buffer->dataCount,
++ buffer->dataCount,
++ size,
++ buffer->address
++ );
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER %d: count=%d (0x%X), size=%d bytes @ %08X\n",
++ bufferIndex,
++ buffer->dataCount,
++ buffer->dataCount,
++ size,
++ buffer->address
++ );
++ }
++#endif
++
++ /* Determine the number of double words to print. */
++ count = size / 4;
++
++ /* Determine the buffer location. */
++ data = (gctUINT32_PTR)
++ (
++ (gctUINT8_PTR) buffer + buffer->bufferOffset
++ );
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "unsigned int _" gcvCOMMAND_BUFFER_NAME "_%d[] =\n",
++ arrayCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "{\n"
++ );
++
++ arrayCount += 1;
++#endif
++
++#if gcvDUMP_COMMAND_LINES
++ /* Reset the line number. */
++ lineNumber = 0;
++#endif
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ count -= 2;
++#endif
++
++ for (i = 0; i < count; i += 1)
++ {
++ if ((i % 8) == 0)
++ {
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\t");
++#else
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " ");
++#endif
++ }
++
++#if gcvDUMP_COMMAND_LINES
++ if (lineNumber == gcvDUMP_COMMAND_LINES)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " . . . . . . . . .\n");
++ break;
++ }
++#endif
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "0x%08X", data[i]);
++
++ if (i + 1 == count)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\n");
++
++#if gcvDUMP_COMMAND_LINES
++ lineNumber += 1;
++#endif
++ }
++ else
++ {
++ if (((i + 1) % 8) == 0)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ",\n");
++
++#if gcvDUMP_COMMAND_LINES
++ lineNumber += 1;
++#endif
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ", ");
++ }
++ }
++ }
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "};\n\n"
++ );
++#endif
++
++ /* Advance to the next subbuffer. */
++ buffer = buffer->nextSubBuffer;
++ bufferIndex += 1;
++ }
++
++ /* Advance to the next entry. */
++ entry += 1;
++ }
++}
++#endif
++
++static gceSTATUS
++_LockCurrentQueue(
++ IN gckVGCOMMAND Command,
++ OUT gcsKERNEL_CMDQUEUE_PTR * Entries,
++ OUT gctUINT_PTR EntryCount
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* Get a shortcut to the head of the queue. */
++ queueHead = Command->queueHead;
++
++ /* Is the head buffer still being worked on? */
++ if (queueHead->pending)
++ {
++ /* Increment overflow count. */
++ Command->queueOverflow += 1;
++
++ /* Wait until the head becomes idle. */
++ gcmkERR_BREAK(_WaitForIdle(Command, queueHead));
++ }
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->queueMutex,
++ gcvINFINITE
++ ));
++
++ /* Determine the first queue entry. */
++ queueHead->currentEntry = (gcsKERNEL_CMDQUEUE_PTR)
++ (
++ (gctUINT8_PTR) queueHead + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ );
++
++ /* Set the pointer to the first entry. */
++ * Entries = queueHead->currentEntry;
++
++ /* Determine the number of available entries. */
++ * EntryCount = queueHead->size / gcmSIZEOF(gcsKERNEL_CMDQUEUE);
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UnlockCurrentQueue(
++ IN gckVGCOMMAND Command,
++ IN gctUINT EntryCount
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++#if !gcdENABLE_INFINITE_SPEED_HW
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++ gcsKERNEL_QUEUE_HEADER_PTR queueNext;
++ gctUINT queueSize;
++ gctUINT newSize;
++ gctUINT unusedSize;
++
++ /* Get shortcut to the head and to the tail of the queue. */
++ queueTail = Command->queueTail;
++ queueHead = Command->queueHead;
++
++ /* Dump the command buffer. */
++#if gcvDUMP_COMMAND_BUFFER
++ _DumpCommandQueue(Command, queueHead, EntryCount);
++#endif
++
++ /* Get a shortcut to the current queue size. */
++ queueSize = queueHead->size;
++
++ /* Determine the new queue size. */
++ newSize = EntryCount * gcmSIZEOF(gcsKERNEL_CMDQUEUE);
++ gcmkASSERT(newSize <= queueSize);
++
++ /* Determine the size of the unused area. */
++ unusedSize = queueSize - newSize;
++
++ /* Is the unused area big enough to become a buffer? */
++ if (unusedSize >= gcvMINUMUM_BUFFER)
++ {
++ gcsKERNEL_QUEUE_HEADER_PTR nextHead;
++
++ /* Place the new header. */
++ nextHead = (gcsKERNEL_QUEUE_HEADER_PTR)
++ (
++ (gctUINT8_PTR) queueHead
++ + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ + newSize
++ );
++
++ /* Initialize the buffer. */
++ nextHead->size = unusedSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER);
++ nextHead->pending = 0;
++
++ /* Link the buffer in. */
++ nextHead->next = queueHead->next;
++ queueHead->next = nextHead;
++ queueNext = nextHead;
++
++ /* Update the size of the current buffer. */
++ queueHead->size = newSize;
++ }
++
++ /* Not big enough. */
++ else
++ {
++ /* Determine the next queue. */
++ queueNext = queueHead->next;
++ }
++
++ /* Mark the buffer as busy. */
++ queueHead->pending = EntryCount;
++
++ /* Advance to the next buffer. */
++ Command->queueHead = queueNext;
++
++ /* Start the command processor if the queue was empty. */
++ if (queueTail == queueHead)
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* The first entry must be a command buffer. */
++ commandBuffer = queueTail->currentEntry->commandBuffer;
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Command->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++ }
++
++ /* The queue was not empty. */
++ else
++ {
++ /* Advance the merge buffer if needed. */
++ if (queueHead == Command->mergeQueue)
++ {
++ Command->mergeQueue = queueNext;
++ }
++ }
++#endif
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->queueMutex
++ ));
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API Code *****************************
++\******************************************************************************/
++gceSTATUS
++gckVGCOMMAND_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT TaskGranularity,
++ IN gctUINT QueueSize,
++ OUT gckVGCOMMAND * Command
++ )
++{
++ gceSTATUS status, last;
++ gckVGCOMMAND command = gcvNULL;
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++ gctUINT i, j;
++
++ gcmkHEADER_ARG("Kernel=0x%x TaskGranularity=0x%x QueueSize=0x%x Command=0x%x",
++ Kernel, TaskGranularity, QueueSize, Command);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(QueueSize >= gcvMINUMUM_BUFFER);
++ gcmkVERIFY_ARGUMENT(Command != gcvNULL);
++
++ do
++ {
++ /***********************************************************************
++ ** Generic object initialization.
++ */
++
++ /* Allocate the gckVGCOMMAND structure. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(struct _gckVGCOMMAND),
++ (gctPOINTER *) &command
++ ));
++
++ /* Initialize the object. */
++ command->object.type = gcvOBJ_COMMAND;
++
++ /* Set the object pointers. */
++ command->kernel = Kernel;
++ command->os = Kernel->os;
++ command->hardware = Kernel->hardware;
++
++ /* Reset pointers. */
++ command->queue = gcvNULL;
++ command->queueMutex = gcvNULL;
++ command->taskMutex = gcvNULL;
++ command->commitMutex = gcvNULL;
++
++ command->powerStallBuffer = gcvNULL;
++ command->powerStallSignal = gcvNULL;
++ command->powerSemaphore = gcvNULL;
++
++ /* Reset context states. */
++ command->contextCounter = 0;
++ command->currentContext = 0;
++
++ /* Enable command buffer dumping. */
++ command->enableDumping = gcvTRUE;
++
++ /* Set features. */
++ command->fe20 = Kernel->hardware->fe20;
++ command->vg20 = Kernel->hardware->vg20;
++ command->vg21 = Kernel->hardware->vg21;
++
++ /* Reset task table .*/
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ command->taskTable, gcmSIZEOF(command->taskTable)
++ ));
++
++ /* Query command buffer attributes. */
++ gcmkERR_BREAK(gckVGCOMMAND_InitializeInfo(command));
++
++ /* Create the control mutexes. */
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->queueMutex));
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->taskMutex));
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->commitMutex));
++
++ /* Create the power management semaphore. */
++ gcmkERR_BREAK(gckOS_CreateSemaphore(Kernel->os,
++ &command->powerSemaphore));
++
++ gcmkERR_BREAK(gckOS_CreateSignal(Kernel->os,
++ gcvFALSE, &command->powerStallSignal));
++
++ /***********************************************************************
++ ** Command queue initialization.
++ */
++
++ /* Allocate the command queue. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ QueueSize,
++ (gctPOINTER *) &command->queue
++ ));
++
++ /* Initialize the command queue. */
++ queue = command->queue;
++
++ queue->size = QueueSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER);
++ queue->pending = 0;
++ queue->next = queue;
++
++ command->queueHead =
++ command->queueTail =
++ command->mergeQueue = command->queue;
++
++ command->queueOverflow = 0;
++
++
++ /***********************************************************************
++ ** Enable TS overflow interrupt.
++ */
++
++ command->info.tsOverflowInt = 0;
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->info.tsOverflowInt,
++ _EventHandler_TSOverflow
++ ));
++
++ /* Mask out the interrupt. */
++ Kernel->hardware->eventMask &= ~(1 << command->info.tsOverflowInt);
++
++
++ /***********************************************************************
++ ** Enable Bus Error interrupt.
++ */
++
++ /* Hardwired to bit 31. */
++ command->busErrorInt = 31;
++
++ /* Enable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->busErrorInt,
++ _EventHandler_BusError
++ ));
++
++
++ command->powerStallInt = 30;
++ /* Enable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->powerStallInt,
++ _EventHandler_PowerStall
++ ));
++
++ /***********************************************************************
++ ** Task management initialization.
++ */
++
++ command->taskStorage = gcvNULL;
++ command->taskStorageGranularity = TaskGranularity;
++ command->taskStorageUsable = TaskGranularity - gcmSIZEOF(gcsTASK_STORAGE);
++
++ command->taskFreeHead = gcvNULL;
++ command->taskFreeTail = gcvNULL;
++
++ /* Enable block handlers. */
++ for (i = 0; i < gcmCOUNTOF(_blockHandlers); i += 1)
++ {
++ /* Get the target hardware block. */
++ gceBLOCK block = _blockHandlers[i].block;
++
++ /* Get the interrupt array entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[block];
++
++ /* Determine the interrupt value index. */
++ gctUINT index = entry->interruptCount;
++
++ /* Create the block semaphore. */
++ if (entry->interruptSemaphore == gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_CreateSemaphoreVG(
++ command->os, &entry->interruptSemaphore
++ ));
++ }
++
++ /* Enable auto-detection. */
++ entry->interruptArray[index] = -1;
++
++ /* Enable interrupt for the block. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &entry->interruptArray[index],
++ _blockHandlers[i].handler
++ ));
++
++ /* Update the number of registered interrupts. */
++ entry->interruptCount += 1;
++
++ /* Inrement the semaphore to allow the usage of the registered
++ interrupt. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ command->os, entry->interruptSemaphore
++ ));
++
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Get the FE interrupt. */
++ command->info.feBufferInt
++ = command->taskTable[gcvBLOCK_COMMAND].interruptArray[0];
++
++ /* Return gckVGCOMMAND object pointer. */
++ *Command = command;
++
++ gcmkFOOTER_ARG("*Command=0x%x",*Command);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (command != gcvNULL)
++ {
++ /* Disable block handlers. */
++ for (i = 0; i < gcvBLOCK_COUNT; i += 1)
++ {
++ /* Get the task table entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[i];
++
++ /* Destroy the semaphore. */
++ if (entry->interruptSemaphore != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DestroySemaphore(
++ command->os, entry->interruptSemaphore
++ ));
++ }
++
++ /* Disable all enabled interrupts. */
++ for (j = 0; j < entry->interruptCount; j += 1)
++ {
++ /* Must be a valid value. */
++ gcmkASSERT(entry->interruptArray[j] >= 0);
++ gcmkASSERT(entry->interruptArray[j] <= 31);
++
++ /* Disable the interrupt. */
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ entry->interruptArray[j]
++ ));
++ }
++ }
++
++ /* Disable the bus error interrupt. */
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ command->busErrorInt
++ ));
++
++ /* Disable TS overflow interrupt. */
++ if (command->info.tsOverflowInt != -1)
++ {
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ command->info.tsOverflowInt
++ ));
++ }
++
++ /* Delete the commit mutex. */
++ if (command->commitMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->commitMutex
++ ));
++ }
++
++ /* Delete the command queue mutex. */
++ if (command->taskMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->taskMutex
++ ));
++ }
++
++ /* Delete the command queue mutex. */
++ if (command->queueMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->queueMutex
++ ));
++ }
++
++ /* Delete the command queue. */
++ if (command->queue != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_Free(
++ Kernel->os, command->queue
++ ));
++ }
++
++ if (command->powerSemaphore != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(
++ Kernel->os, command->powerSemaphore));
++ }
++
++ if (command->powerStallSignal != gcvNULL)
++ {
++ /* Create the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Kernel->os,
++ command->powerStallSignal));
++ }
++
++ /* Free the gckVGCOMMAND structure. */
++ gcmkCHECK_STATUS(gckOS_Free(
++ Kernel->os, command
++ ));
++ }
++
++ gcmkFOOTER();
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Destroy(
++ OUT gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ gctUINT i;
++ gcsTASK_STORAGE_PTR nextStorage;
++
++ if (Command->queueHead != gcvNULL)
++ {
++ /* Wait until the head becomes idle. */
++ gcmkERR_BREAK(_WaitForIdle(Command, Command->queueHead));
++ }
++
++ /* Disable block handlers. */
++ for (i = 0; i < gcvBLOCK_COUNT; i += 1)
++ {
++ /* Get the interrupt array entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &Command->taskTable[i];
++
++ /* Determine the index of the last interrupt in the array. */
++ gctINT index = entry->interruptCount - 1;
++
++ /* Destroy the semaphore. */
++ if (entry->interruptSemaphore != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Command->os, entry->interruptSemaphore
++ ));
++ }
++
++ /* Disable all enabled interrupts. */
++ while (index >= 0)
++ {
++ /* Must be a valid value. */
++ gcmkASSERT(entry->interruptArray[index] >= 0);
++ gcmkASSERT(entry->interruptArray[index] <= 31);
++
++ /* Disable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ entry->interruptArray[index]
++ ));
++
++ /* Update to the next interrupt. */
++ index -= 1;
++ entry->interruptCount -= 1;
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Disable the bus error interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ Command->busErrorInt
++ ));
++
++ /* Disable TS overflow interrupt. */
++ if (Command->info.tsOverflowInt != -1)
++ {
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ Command->info.tsOverflowInt
++ ));
++
++ Command->info.tsOverflowInt = -1;
++ }
++
++ /* Delete the commit mutex. */
++ if (Command->commitMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->commitMutex
++ ));
++
++ Command->commitMutex = gcvNULL;
++ }
++
++ /* Delete the command queue mutex. */
++ if (Command->taskMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->taskMutex
++ ));
++
++ Command->taskMutex = gcvNULL;
++ }
++
++ /* Delete the command queue mutex. */
++ if (Command->queueMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->queueMutex
++ ));
++
++ Command->queueMutex = gcvNULL;
++ }
++
++ if (Command->powerSemaphore != gcvNULL)
++ {
++ /* Destroy the power management semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Command->os, Command->powerSemaphore));
++ }
++
++ if (Command->powerStallSignal != gcvNULL)
++ {
++ /* Create the power management semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySignal(
++ Command->os,
++ Command->powerStallSignal));
++ }
++
++ if (Command->queue != gcvNULL)
++ {
++ /* Delete the command queue. */
++ gcmkERR_BREAK(gckOS_Free(
++ Command->os, Command->queue
++ ));
++ }
++
++ /* Destroy all allocated buffers. */
++ while (Command->taskStorage)
++ {
++ /* Copy the buffer pointer. */
++ nextStorage = Command->taskStorage->next;
++
++ /* Free the current container. */
++ gcmkERR_BREAK(gckOS_Free(
++ Command->os, Command->taskStorage
++ ));
++
++ /* Advance to the next one. */
++ Command->taskStorage = nextStorage;
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Mark the object as unknown. */
++ Command->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGCOMMAND structure. */
++ gcmkERR_BREAK(gckOS_Free(Command->os, Command));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Restore the object type if failed. */
++ Command->object.type = gcvOBJ_COMMAND;
++
++ gcmkFOOTER();
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_QueryCommandBuffer(
++ IN gckVGCOMMAND Command,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Information=0x%x", Command, Information);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Information != gcvNULL);
++
++ /* Copy the information. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ Information, &Command->info, sizeof(gcsCOMMAND_BUFFER_INFO)
++ ));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGCOMMAND_Allocate(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer,
++ OUT gctPOINTER * Data
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x Size=0x%x CommandBuffer=0x%x Data=0x%x",
++ Command, Size, CommandBuffer, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ do
++ {
++ /* Allocate the buffer. */
++ gcmkERR_BREAK(_AllocateCommandBuffer(Command, Size, CommandBuffer));
++
++ /* Determine the data pointer. */
++ * Data = (gctUINT8_PTR) (*CommandBuffer) + (* CommandBuffer)->bufferOffset;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Free(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x",
++ Command, CommandBuffer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL);
++
++ /* Free command buffer. */
++ status = _FreeCommandBuffer(Command->kernel, CommandBuffer);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Execute(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x",
++ Command, CommandBuffer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL);
++
++ do
++ {
++ gctUINT queueLength;
++ gcsKERNEL_CMDQUEUE_PTR kernelEntry;
++
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_LockCurrentQueue(
++ Command, &kernelEntry, &queueLength
++ ));
++
++ /* Set the buffer. */
++ kernelEntry->commandBuffer = CommandBuffer;
++ kernelEntry->handler = _FreeKernelCommandBuffer;
++
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_UnlockCurrentQueue(
++ Command, 1
++ ));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Commit(
++ IN gckVGCOMMAND Command,
++ IN gcsVGCONTEXT_PTR Context,
++ IN gcsVGCMDQUEUE_PTR Queue,
++ IN gctUINT EntryCount,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable
++ )
++{
++ /*
++ The first buffer is executed through a direct gckVGHARDWARE_Execute call,
++ therefore only an update is needed after the execution is over. All
++ consequent buffers need to be executed upon the first update call from
++ the FE interrupt handler.
++ */
++
++ static gcsQUEUE_UPDATE_CONTROL _dynamicBuffer[] =
++ {
++ {
++ _UpdateDynamicCommandBuffer,
++ _UpdateDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer
++ },
++ {
++ _ExecuteDynamicCommandBuffer,
++ _UpdateDynamicCommandBuffer,
++ _ExecuteLastDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer
++ }
++ };
++
++ static gcsQUEUE_UPDATE_CONTROL _staticBuffer[] =
++ {
++ {
++ _UpdateStaticCommandBuffer,
++ _UpdateStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer
++ },
++ {
++ _ExecuteStaticCommandBuffer,
++ _UpdateStaticCommandBuffer,
++ _ExecuteLastStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer
++ }
++ };
++
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Command=0x%x Context=0x%x Queue=0x%x EntryCount=0x%x TaskTable=0x%x",
++ Command, Context, Queue, EntryCount, TaskTable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++ gcmkVERIFY_ARGUMENT(EntryCount > 1);
++
++#ifdef __QNXNTO__
++ TaskTable->coid = Context->coid;
++ TaskTable->rcvid = Context->rcvid;
++#endif /* __QNXNTO__ */
++
++ do
++ {
++ gctBOOL haveFETasks;
++ gctUINT queueSize;
++ gcsVGCMDQUEUE_PTR mappedQueue;
++ gcsVGCMDQUEUE_PTR userEntry;
++ gcsKERNEL_CMDQUEUE_PTR kernelEntry;
++ gcsQUEUE_UPDATE_CONTROL_PTR queueControl;
++ gctUINT currentLength;
++ gctUINT queueLength;
++ gctUINT entriesQueued;
++ gctUINT8_PTR previousEnd;
++ gctBOOL previousDynamic;
++ gctBOOL previousExecuted;
++ gctUINT controlIndex;
++
++ gcmkERR_BREAK(gckVGHARDWARE_SetPowerManagementState(
++ Command->hardware, gcvPOWER_ON_AUTO
++ ));
++
++ /* Acquire the power semaphore. */
++ gcmkERR_BREAK(gckOS_AcquireSemaphore(
++ Command->os, Command->powerSemaphore
++ ));
++
++ /* Acquire the mutex. */
++ status = gckOS_AcquireMutex(
++ Command->os,
++ Command->commitMutex,
++ gcvINFINITE
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore));
++ break;
++ }
++
++ gcmkERR_BREAK(_FlushMMU(Command));
++
++ do
++ {
++ /* Assign a context ID if not yet assigned. */
++ if (Context->id == 0)
++ {
++ /* Assign the next context number. */
++ Context->id = ++ Command->contextCounter;
++
++ /* See if we overflowed. */
++ if (Command->contextCounter == 0)
++ {
++ /* We actually did overflow, wow... */
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ break;
++ }
++ }
++
++ /* The first entry in the queue is always the context buffer.
++ Verify whether the user context is the same as the current
++ context and if that's the case, skip the first entry. */
++ if (Context->id == Command->currentContext)
++ {
++ /* Same context as before, skip the first entry. */
++ EntryCount -= 1;
++ Queue += 1;
++
++ /* Set the signal to avoid user waiting. */
++#ifdef __QNXNTO__
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, Context->signal, Context->rcvid, Context->coid
++ ));
++#else
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, Context->signal, Context->process
++ ));
++
++#endif /* __QNXNTO__ */
++
++ }
++ else
++ {
++ /* Different user context - keep the first entry.
++ Set the user context as the current one. */
++ Command->currentContext = Context->id;
++ }
++
++ /* Reset pointers. */
++ queueControl = gcvNULL;
++ previousEnd = gcvNULL;
++
++ /* Determine whether there are FE tasks to be performed. */
++ haveFETasks = (TaskTable->table[gcvBLOCK_COMMAND].head != gcvNULL);
++
++ /* Determine the size of the queue. */
++ queueSize = EntryCount * gcmSIZEOF(gcsVGCMDQUEUE);
++
++ /* Map the command queue into the kernel space. */
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ Queue,
++ queueSize,
++ (gctPOINTER *) &mappedQueue
++ ));
++
++ /* Set the first entry. */
++ userEntry = mappedQueue;
++
++ /* Process the command queue. */
++ while (EntryCount)
++ {
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_LockCurrentQueue(
++ Command, &kernelEntry, &queueLength
++ ));
++
++ /* Determine the number of entries to process. */
++ currentLength = (queueLength < EntryCount)
++ ? queueLength
++ : EntryCount;
++
++ /* Update the number of the entries left to process. */
++ EntryCount -= currentLength;
++
++ /* Reset previous flags. */
++ previousDynamic = gcvFALSE;
++ previousExecuted = gcvFALSE;
++
++ /* Set the initial control index. */
++ controlIndex = 0;
++
++ /* Process entries. */
++ for (entriesQueued = 0; entriesQueued < currentLength; entriesQueued += 1)
++ {
++ /* Get the kernel pointer to the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = gcvNULL;
++ gcmkERR_BREAK(_ConvertUserCommandBufferPointer(
++ Command,
++ userEntry->commandBuffer,
++ &commandBuffer
++ ));
++
++ /* Is it a dynamic command buffer? */
++ if (userEntry->dynamic)
++ {
++ /* Select dynamic buffer control functions. */
++ queueControl = &_dynamicBuffer[controlIndex];
++ }
++
++ /* No, a static command buffer. */
++ else
++ {
++ /* Select static buffer control functions. */
++ queueControl = &_staticBuffer[controlIndex];
++ }
++
++ /* Set the command buffer pointer to the entry. */
++ kernelEntry->commandBuffer = commandBuffer;
++
++ /* If the previous entry was a dynamic command buffer,
++ link it to the current. */
++ if (previousDynamic)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command,
++ previousEnd,
++ commandBuffer->address,
++ commandBuffer->dataCount,
++ gcvNULL
++ ));
++
++ /* The buffer will be auto-executed, only need to
++ update it after it has been executed. */
++ kernelEntry->handler = queueControl->update;
++
++ /* The buffer is only being updated. */
++ previousExecuted = gcvFALSE;
++ }
++ else
++ {
++ /* Set the buffer up for execution. */
++ kernelEntry->handler = queueControl->execute;
++
++ /* The buffer is being updated. */
++ previousExecuted = gcvTRUE;
++ }
++
++ /* The current buffer's END command becomes the last END. */
++ previousEnd
++ = ((gctUINT8_PTR) commandBuffer)
++ + commandBuffer->bufferOffset
++ + commandBuffer->dataCount * Command->info.commandAlignment
++ - Command->info.staticTailSize;
++
++ /* Update the last entry info. */
++ previousDynamic = userEntry->dynamic;
++
++ /* Advance entries. */
++ userEntry += 1;
++ kernelEntry += 1;
++
++ /* Update the control index. */
++ controlIndex = 1;
++ }
++
++ /* If the previous entry was a dynamic command buffer,
++ terminate it with an END. */
++ if (previousDynamic)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command,
++ previousEnd,
++ Command->info.feBufferInt,
++ gcvNULL
++ ));
++ }
++
++ /* Last buffer? */
++ if (EntryCount == 0)
++ {
++ /* Modify the last command buffer's routines to handle
++ tasks if any.*/
++ if (haveFETasks)
++ {
++ if (previousExecuted)
++ {
++ kernelEntry[-1].handler = queueControl->lastExecute;
++ }
++ else
++ {
++ kernelEntry[-1].handler = queueControl->lastUpdate;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->queueMutex
++ ));
++ /* Schedule tasks. */
++ gcmkERR_BREAK(_ScheduleTasks(Command, TaskTable, previousEnd));
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->queueMutex,
++ gcvINFINITE
++ ));
++ }
++
++ /* Unkock and schedule the current queue for execution. */
++ gcmkERR_BREAK(_UnlockCurrentQueue(
++ Command, currentLength
++ ));
++ }
++
++
++ /* Unmap the user command buffer. */
++ gcmkERR_BREAK(gckOS_UnmapUserPointer(
++ Command->os,
++ Queue,
++ queueSize,
++ mappedQueue
++ ));
++ }
++ while (gcvFALSE);
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ Command->os,
++ Command->commitMutex
++ ));
++
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,1548 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_DATABASE
++
++/*******************************************************************************
++***** Private fuctions ********************************************************/
++
++#define _GetSlot(database, x) \
++ (gctUINT32)(((gcmPTR_TO_UINT64(x) >> 7) % gcmCOUNTOF(database->list)))
++
++/*******************************************************************************
++** gckKERNEL_NewDatabase
++**
++** Create a new database structure and insert it to the head of the hash list.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID that identifies the database.
++**
++** OUTPUT:
++**
++** gcsDATABASE_PTR * Database
++** Pointer to a variable receiving the database structure pointer on
++** success.
++*/
++static gceSTATUS
++gckKERNEL_NewDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcsDATABASE_PTR * Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctBOOL acquired = gcvFALSE;
++ gctSIZE_T slot;
++ gcsDATABASE_PTR existingDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Compute the hash for the database. */
++ slot = ProcessID % gcmCOUNTOF(Kernel->db->db);
++
++ /* Walk the hash list. */
++ for (existingDatabase = Kernel->db->db[slot];
++ existingDatabase != gcvNULL;
++ existingDatabase = existingDatabase->next)
++ {
++ if (existingDatabase->processID == ProcessID)
++ {
++ /* One process can't be added twice. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++ }
++
++ if (Kernel->db->freeDatabase != gcvNULL)
++ {
++ /* Allocate a database from the free list. */
++ database = Kernel->db->freeDatabase;
++ Kernel->db->freeDatabase = database->next;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Allocate a new database from the heap. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os,
++ gcmSIZEOF(gcsDATABASE),
++ &pointer));
++
++ database = pointer;
++ }
++
++ /* Insert the database into the hash. */
++ database->next = Kernel->db->db[slot];
++ Kernel->db->db[slot] = database;
++
++ /* Save the hash slot. */
++ database->slot = slot;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the database. */
++ *Database = database;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Database=0x%x", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindDatabase
++**
++** Find a database identified by a process ID and move it to the head of the
++** hash list.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID that identifies the database.
++**
++** gctBOOL LastProcessID
++** gcvTRUE if searching for the last known process ID. gcvFALSE if
++** we need to search for the process ID specified by the ProcessID
++** argument.
++**
++** OUTPUT:
++**
++** gcsDATABASE_PTR * Database
++** Pointer to a variable receiving the database structure pointer on
++** success.
++*/
++static gceSTATUS
++gckKERNEL_FindDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ OUT gcsDATABASE_PTR * Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database, previous;
++ gctSIZE_T slot;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d LastProcessID=%d",
++ Kernel, ProcessID, LastProcessID);
++
++ /* Compute the hash for the database. */
++ slot = ProcessID % gcmCOUNTOF(Kernel->db->db);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Check whether we are getting the last known database. */
++ if (LastProcessID)
++ {
++ /* Use last database. */
++ database = Kernel->db->lastDatabase;
++
++ if (database == gcvNULL)
++ {
++ /* Database not found. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++ }
++ else
++ {
++ /* Walk the hash list. */
++ for (previous = gcvNULL, database = Kernel->db->db[slot];
++ database != gcvNULL;
++ database = database->next)
++ {
++ if (database->processID == ProcessID)
++ {
++ /* Found it! */
++ break;
++ }
++
++ previous = database;
++ }
++
++ if (database == gcvNULL)
++ {
++ /* Database not found. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (previous != gcvNULL)
++ {
++ /* Move database to the head of the hash list. */
++ previous->next = database->next;
++ database->next = Kernel->db->db[slot];
++ Kernel->db->db[slot] = database;
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the database. */
++ *Database = database;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Database=0x%x", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DeleteDatabase
++**
++** Remove a database from the hash list and delete its structure.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to the database structure to remove.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++static gceSTATUS
++gckKERNEL_DeleteDatabase(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Check slot value. */
++ gcmkVERIFY_ARGUMENT(Database->slot < gcmCOUNTOF(Kernel->db->db));
++
++ if (Database->slot < gcmCOUNTOF(Kernel->db->db))
++ {
++ /* Check if database if the head of the hash list. */
++ if (Kernel->db->db[Database->slot] == Database)
++ {
++ /* Remove the database from the hash list. */
++ Kernel->db->db[Database->slot] = Database->next;
++ }
++ else
++ {
++ /* Walk the has list to find the database. */
++ for (database = Kernel->db->db[Database->slot];
++ database != gcvNULL;
++ database = database->next
++ )
++ {
++ /* Check if the next list entry is this database. */
++ if (database->next == Database)
++ {
++ /* Remove the database from the hash list. */
++ database->next = Database->next;
++ break;
++ }
++ }
++
++ if (database == gcvNULL)
++ {
++ /* Ouch! Something got corrupted. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++ }
++ }
++
++ if (Kernel->db->lastDatabase != gcvNULL)
++ {
++ /* Insert database to the free list. */
++ Kernel->db->lastDatabase->next = Kernel->db->freeDatabase;
++ Kernel->db->freeDatabase = Kernel->db->lastDatabase;
++ }
++
++ /* Keep database as the last database. */
++ Kernel->db->lastDatabase = Database;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_NewRecord
++**
++** Create a new database record structure and insert it to the head of the
++** database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** OUTPUT:
++**
++** gcsDATABASE_RECORD_PTR * Record
++** Pointer to a variable receiving the database record structure
++** pointer on success.
++*/
++static gceSTATUS
++gckKERNEL_NewRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gctUINT32 Slot,
++ OUT gcsDATABASE_RECORD_PTR * Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (Kernel->db->freeRecord != gcvNULL)
++ {
++ /* Allocate the record from the free list. */
++ record = Kernel->db->freeRecord;
++ Kernel->db->freeRecord = record->next;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Allocate the record from the heap. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os,
++ gcmSIZEOF(gcsDATABASE_RECORD),
++ &pointer));
++
++ record = pointer;
++ }
++
++ /* Insert the record in the database. */
++ record->next = Database->list[Slot];
++ Database->list[Slot] = record;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the record. */
++ *Record = record;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Record=0x%x", *Record);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++ if (record != gcvNULL)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DeleteRecord
++**
++** Remove a database record from the database and delete its structure.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to remove.
++**
++** gctPOINTER Data
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gctSIZE_T_PTR Bytes
++** Pointer to a variable that receives the size of the record deleted.
++** Can be gcvNULL if the size is not required.
++*/
++static gceSTATUS
++gckKERNEL_DeleteRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Data,
++ OUT gctSIZE_T_PTR Bytes OPTIONAL
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record, previous;
++ gctUINT32 slot = _GetSlot(Database, Data);
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x",
++ Kernel, Database, Type, Data);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++
++ /* Scan the database for this record. */
++ for (record = Database->list[slot], previous = gcvNULL;
++ record != gcvNULL;
++ record = record->next
++ )
++ {
++ if ((record->type == Type)
++ && (record->data == Data)
++ )
++ {
++ /* Found it! */
++ break;
++ }
++
++ previous = record;
++ }
++
++ if (record == gcvNULL)
++ {
++ /* Ouch! This record is not found? */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return size of record. */
++ *Bytes = record->bytes;
++ }
++
++ /* Remove record from database. */
++ if (previous == gcvNULL)
++ {
++ Database->list[slot] = record->next;
++ }
++ else
++ {
++ previous->next = record->next;
++ }
++
++ /* Insert record in free list. */
++ record->next = Kernel->db->freeRecord;
++ Kernel->db->freeRecord = record;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindRecord
++**
++** Find a database record from the database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to remove.
++**
++** gctPOINTER Data
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gctSIZE_T_PTR Bytes
++** Pointer to a variable that receives the size of the record deleted.
++** Can be gcvNULL if the size is not required.
++*/
++static gceSTATUS
++gckKERNEL_FindRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Data,
++ OUT gcsDATABASE_RECORD_PTR Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record;
++ gctUINT32 slot = _GetSlot(Database, Data);
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x",
++ Kernel, Database, Type, Data);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Scan the database for this record. */
++ for (record = Database->list[slot];
++ record != gcvNULL;
++ record = record->next
++ )
++ {
++ if ((record->type == Type)
++ && (record->data == Data)
++ )
++ {
++ /* Found it! */
++ break;
++ }
++ }
++
++ if (record == gcvNULL)
++ {
++ /* Ouch! This record is not found? */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (Record != gcvNULL)
++ {
++ /* Return information of record. */
++ gcmkONERROR(
++ gckOS_MemCopy(Record, record, sizeof(gcsDATABASE_RECORD)));
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("Record=0x%x", Record);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++
++/*******************************************************************************
++***** Public API **************************************************************/
++
++/*******************************************************************************
++** gckKERNEL_CreateProcessDB
++**
++** Create a new process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_CreateProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database = gcvNULL;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Create a new database. */
++ gcmkONERROR(gckKERNEL_NewDatabase(Kernel, ProcessID, &database));
++
++ /* Initialize the database. */
++ database->processID = ProcessID;
++ database->vidMem.bytes = 0;
++ database->vidMem.maxBytes = 0;
++ database->vidMem.totalBytes = 0;
++ database->nonPaged.bytes = 0;
++ database->nonPaged.maxBytes = 0;
++ database->nonPaged.totalBytes = 0;
++ database->contiguous.bytes = 0;
++ database->contiguous.maxBytes = 0;
++ database->contiguous.totalBytes = 0;
++ database->mapMemory.bytes = 0;
++ database->mapMemory.maxBytes = 0;
++ database->mapMemory.totalBytes = 0;
++ database->mapUserMemory.bytes = 0;
++ database->mapUserMemory.maxBytes = 0;
++ database->mapUserMemory.totalBytes = 0;
++
++ for (i = 0; i < gcmCOUNTOF(database->list); i++)
++ {
++ database->list[i] = gcvNULL;
++ }
++
++#if gcdSECURE_USER
++ {
++ gctINT slot;
++ gcskSECURE_CACHE * cache = &database->cache;
++
++ /* Setup the linked list of cache nodes. */
++ for (slot = 1; slot <= gcdSECURE_CACHE_SLOTS; ++slot)
++ {
++ cache->cache[slot].logical = gcvNULL;
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ cache->cache[slot].prev = &cache->cache[slot - 1];
++ cache->cache[slot].next = &cache->cache[slot + 1];
++# endif
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ cache->cache[slot].nextHash = gcvNULL;
++ cache->cache[slot].prevHash = gcvNULL;
++# endif
++ }
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ /* Setup the head and tail of the cache. */
++ cache->cache[0].next = &cache->cache[1];
++ cache->cache[0].prev = &cache->cache[gcdSECURE_CACHE_SLOTS];
++ cache->cache[0].logical = gcvNULL;
++
++ /* Fix up the head and tail pointers. */
++ cache->cache[0].next->prev = &cache->cache[0];
++ cache->cache[0].prev->next = &cache->cache[0];
++# endif
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Zero out the hash table. */
++ for (slot = 0; slot < gcmCOUNTOF(cache->hash); ++slot)
++ {
++ cache->hash[slot].logical = gcvNULL;
++ cache->hash[slot].nextHash = gcvNULL;
++ }
++# endif
++
++ /* Initialize cache index. */
++ cache->cacheIndex = gcvNULL;
++ cache->cacheFree = 1;
++ cache->cacheStamp = 0;
++ }
++#endif
++
++ /* Reset idle timer. */
++ Kernel->db->lastIdle = 0;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AddProcessDB
++**
++** Add a record to a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to add.
++**
++** gctPOINTER Pointer
++** Data of the record to add.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the record to add.
++**
++** gctSIZE_T Size
++** Size of the record to add.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AddProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_RECORD_PTR record = gcvNULL;
++ gcsDATABASE_COUNTERS * count;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x "
++ "Physical=0x%x Size=%lu",
++ Kernel, ProcessID, Type, Pointer, Physical, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Special case the idle record. */
++ if (Type == gcvDB_IDLE)
++ {
++ gctUINT64 time;
++
++ /* Get the current profile time. */
++ gcmkONERROR(gckOS_GetProfileTick(&time));
++
++ if ((ProcessID == 0) && (Kernel->db->lastIdle != 0))
++ {
++ /* Out of idle, adjust time it was idle. */
++ Kernel->db->idleTime += time - Kernel->db->lastIdle;
++ Kernel->db->lastIdle = 0;
++ }
++ else if (ProcessID == 1)
++ {
++ /* Save current idle time. */
++ Kernel->db->lastIdle = time;
++ }
++
++#if gcdDYNAMIC_SPEED
++ {
++ /* Test for first call. */
++ if (Kernel->db->lastSlowdown == 0)
++ {
++ /* Save milliseconds. */
++ Kernel->db->lastSlowdown = time;
++ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime;
++ }
++ else
++ {
++ /* Compute ellapsed time in milliseconds. */
++ gctUINT delta = gckOS_ProfileToMS(time - Kernel->db->lastSlowdown);
++
++ /* Test for end of period. */
++ if (delta >= gcdDYNAMIC_SPEED)
++ {
++ /* Compute number of idle milliseconds. */
++ gctUINT idle = gckOS_ProfileToMS(
++ Kernel->db->idleTime - Kernel->db->lastSlowdownIdle);
++
++ /* Broadcast to slow down the GPU. */
++ gcmkONERROR(gckOS_BroadcastCalibrateSpeed(Kernel->os,
++ Kernel->hardware,
++ idle,
++ delta));
++
++ /* Save current time. */
++ Kernel->db->lastSlowdown = time;
++ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime;
++ }
++ }
++ }
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Create a new record in the database. */
++ gcmkONERROR(gckKERNEL_NewRecord(Kernel, database, _GetSlot(database, Pointer), &record));
++
++ /* Initialize the record. */
++ record->kernel = Kernel;
++ record->type = Type;
++ record->data = Pointer;
++ record->physical = Physical;
++ record->bytes = Size;
++
++ /* Get pointer to counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ count = &database->vidMem;
++ break;
++
++ case gcvDB_NON_PAGED:
++ count = &database->nonPaged;
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ count = &database->contiguous;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ count = &database->mapMemory;
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ count = &database->mapUserMemory;
++ break;
++
++ default:
++ count = gcvNULL;
++ break;
++ }
++
++ if (count != gcvNULL)
++ {
++ /* Adjust counters. */
++ count->totalBytes += Size;
++ count->bytes += Size;
++
++ if (count->bytes > count->maxBytes)
++ {
++ count->maxBytes = count->bytes;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_RemoveProcessDB
++**
++** Remove a record from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to remove.
++**
++** gctPOINTER Pointer
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_RemoveProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctSIZE_T bytes = 0;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x",
++ Kernel, ProcessID, Type, Pointer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Delete the record. */
++ gcmkONERROR(
++ gckKERNEL_DeleteRecord(Kernel, database, Type, Pointer, &bytes));
++
++ /* Update counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ database->vidMem.bytes -= bytes;
++ break;
++
++ case gcvDB_NON_PAGED:
++ database->nonPaged.bytes -= bytes;
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ database->contiguous.bytes -= bytes;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ database->mapMemory.bytes -= bytes;
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ database->mapUserMemory.bytes -= bytes;
++ break;
++
++ default:
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindProcessDB
++**
++** Find a record from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to remove.
++**
++** gctPOINTER Pointer
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gcsDATABASE_RECORD_PTR Record
++** Copy of record.
++*/
++gceSTATUS
++gckKERNEL_FindProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 ThreadID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ OUT gcsDATABASE_RECORD_PTR Record
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x",
++ Kernel, ProcessID, ThreadID, Type, Pointer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Find the record. */
++ gcmkONERROR(
++ gckKERNEL_FindRecord(Kernel, database, Type, Pointer, Record));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DestroyProcessDB
++**
++** Destroy a process database. If the database contains any records, the data
++** inside those records will be deleted as well. This aids in the cleanup if
++** a process has died unexpectedly or has memory leaks.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_DestroyProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_RECORD_PTR record, next;
++ gctBOOL asynchronous;
++ gctPHYS_ADDR physical;
++ gcuVIDMEM_NODE_PTR node;
++ gckKERNEL kernel = Kernel;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): VidMem: total=%lu max=%lu",
++ ProcessID, database->vidMem.totalBytes,
++ database->vidMem.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): NonPaged: total=%lu max=%lu",
++ ProcessID, database->nonPaged.totalBytes,
++ database->nonPaged.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Contiguous: total=%lu max=%lu",
++ ProcessID, database->contiguous.totalBytes,
++ database->contiguous.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Idle time=%llu",
++ ProcessID, Kernel->db->idleTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Map: total=%lu max=%lu",
++ ProcessID, database->mapMemory.totalBytes,
++ database->mapMemory.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Map: total=%lu max=%lu",
++ ProcessID, database->mapUserMemory.totalBytes,
++ database->mapUserMemory.maxBytes);
++
++ if (database->list != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "Process %d has entries in its database:",
++ ProcessID);
++ }
++
++ for(i = 0; i < gcmCOUNTOF(database->list); i++)
++ {
++
++ /* Walk all records. */
++ for (record = database->list[i]; record != gcvNULL; record = next)
++ {
++ /* Next next record. */
++ next = record->next;
++
++ /* Dispatch on record type. */
++ switch (record->type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ /* Free the video memory. */
++ status = gckVIDMEM_Free(gcmUINT64_TO_PTR(record->data));
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: VIDEO_MEMORY 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_NON_PAGED:
++ physical = gcmNAME_TO_PTR(record->physical);
++ /* Unmap user logical memory first. */
++ status = gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ record->bytes,
++ record->data);
++
++ /* Free the non paged memory. */
++ status = gckOS_FreeNonPagedMemory(Kernel->os,
++ record->bytes,
++ physical,
++ record->data);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: NON_PAGED 0x%x, bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ case gcvDB_COMMAND_BUFFER:
++ /* Free the command buffer. */
++ status = gckEVENT_DestroyVirtualCommandBuffer(record->kernel->eventObj,
++ record->bytes,
++ gcmNAME_TO_PTR(record->physical),
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: COMMAND_BUFFER 0x%x, bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++#endif
++
++ case gcvDB_CONTIGUOUS:
++ physical = gcmNAME_TO_PTR(record->physical);
++ /* Unmap user logical memory first. */
++ status = gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ record->bytes,
++ record->data);
++
++ /* Free the contiguous memory. */
++ status = gckEVENT_FreeContiguousMemory(Kernel->eventObj,
++ record->bytes,
++ physical,
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: CONTIGUOUS 0x%x bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++ case gcvDB_SIGNAL:
++#if USE_NEW_LINUX_SIGNAL
++ status = gcvSTATUS_NOT_SUPPORTED;
++#else
++ /* Free the user signal. */
++ status = gckOS_DestroyUserSignal(Kernel->os,
++ gcmPTR2INT(record->data));
++#endif /* USE_NEW_LINUX_SIGNAL */
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SIGNAL %d (status=%d)",
++ (gctINT)(gctUINTPTR_T)record->data, status);
++ break;
++
++ case gcvDB_VIDEO_MEMORY_LOCKED:
++ node = gcmUINT64_TO_PTR(record->data);
++ /* Unlock what we still locked */
++ status = gckVIDMEM_Unlock(record->kernel,
++ node,
++ gcvSURF_TYPE_UNKNOWN,
++ &asynchronous);
++
++ if (gcmIS_SUCCESS(status) && (gcvTRUE == asynchronous))
++ {
++ /* TODO: we maybe need to schedule a event here */
++ status = gckVIDMEM_Unlock(record->kernel,
++ node,
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL);
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: VIDEO_MEMORY_LOCKED 0x%x (status=%d)",
++ node, status);
++ break;
++
++ case gcvDB_CONTEXT:
++ /* TODO: Free the context */
++ status = gckCOMMAND_Detach(Kernel->command, gcmNAME_TO_PTR(record->data));
++ gcmRELEASE_NAME(record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: CONTEXT 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ /* Unmap memory. */
++ status = gckKERNEL_UnmapMemory(Kernel,
++ record->physical,
++ record->bytes,
++ record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: MAP MEMORY %d (status=%d)",
++ gcmPTR2INT(record->data), status);
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ /* TODO: Unmap user memory. */
++ status = gckOS_UnmapUserMemory(Kernel->os,
++ Kernel->core,
++ record->physical,
++ record->bytes,
++ gcmNAME_TO_PTR(record->data),
++ 0);
++ gcmRELEASE_NAME(record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: MAP USER MEMORY %d (status=%d)",
++ gcmPTR2INT(record->data), status);
++ break;
++
++ case gcvDB_SHARED_INFO:
++ status = gckOS_FreeMemory(Kernel->os, record->physical);
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvDB_SYNC_POINT:
++ /* Free the user signal. */
++ status = gckOS_DestroySyncPoint(Kernel->os,
++ (gctSYNC_POINT) record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SYNC POINT %d (status=%d)",
++ (gctINT)(gctUINTPTR_T)record->data, status);
++ break;
++#endif
++
++ default:
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DATABASE,
++ "DB: Correcupted record=0x%08x type=%d",
++ record, record->type);
++ break;
++ }
++
++ /* Delete the record. */
++ gcmkONERROR(gckKERNEL_DeleteRecord(Kernel,
++ database,
++ record->type,
++ record->data,
++ gcvNULL));
++ }
++
++ }
++
++ /* Delete the database. */
++ gcmkONERROR(gckKERNEL_DeleteDatabase(Kernel, database));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_QueryProcessDB
++**
++** Query a process database for the current usage of a particular record type.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gctBOOL LastProcessID
++** gcvTRUE if searching for the last known process ID. gcvFALSE if
++** we need to search for the process ID specified by the ProcessID
++** argument.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to query.
++**
++** OUTPUT:
++**
++** gcuDATABASE_INFO * Info
++** Pointer to a variable that receives the requested information.
++*/
++gceSTATUS
++gckKERNEL_QueryProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ IN gceDATABASE_TYPE Type,
++ OUT gcuDATABASE_INFO * Info
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Info=0x%x",
++ Kernel, ProcessID, Type, Info);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(
++ gckKERNEL_FindDatabase(Kernel, ProcessID, LastProcessID, &database));
++
++ /* Get pointer to counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMem,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_NON_PAGED:
++ gckOS_MemCopy(&Info->counters,
++ &database->nonPaged,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ gckOS_MemCopy(&Info->counters,
++ &database->contiguous,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_IDLE:
++ Info->time = Kernel->db->idleTime;
++ Kernel->db->idleTime = 0;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->mapMemory,
++ gcmSIZEOF(database->mapMemory));
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->mapUserMemory,
++ gcmSIZEOF(database->mapUserMemory));
++ break;
++
++ default:
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++/*******************************************************************************
++** gckKERNEL_GetProcessDBCache
++**
++** Get teh secure cache from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** gcskSECURE_CACHE_PTR * Cache
++** Pointer to a variable that receives the secure cache pointer.
++*/
++gceSTATUS
++gckKERNEL_GetProcessDBCache(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcskSECURE_CACHE_PTR * Cache
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Cache != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Return the pointer to the cache. */
++ *Cache = &database->cache;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Cache=0x%x", *Cache);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckKERNEL_DumpProcessDB(
++ IN gckKERNEL Kernel
++ )
++{
++ gcsDATABASE_PTR database;
++ gctINT i, pid;
++ gctUINT8 name[24];
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** PROCESS DB DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkPRINT_N(8, "%-8s%s\n", "PID", "NAME");
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ for (database = Kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ pid = database->processID;
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name)));
++
++ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name));
++
++ gcmkPRINT_N(8, "%-8d%s\n", pid, name);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,2559 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include <gc_hal_kernel_debug.h>
++
++/******************************************************************************\
++******************************** Debug Variables *******************************
++\******************************************************************************/
++
++static gceSTATUS _lastError = gcvSTATUS_OK;
++static gctUINT32 _debugLevel = gcvLEVEL_ERROR;
++/*
++_debugZones config value
++Please Reference define in gc_hal_base.h
++*/
++static gctUINT32 _debugZones = gcvZONE_NONE;
++
++/******************************************************************************\
++********************************* Debug Switches *******************************
++\******************************************************************************/
++
++/*
++ gcdBUFFERED_OUTPUT
++
++ When set to non-zero, all output is collected into a buffer with the
++ specified size. Once the buffer gets full, the debug buffer will be
++ printed to the console. gcdBUFFERED_SIZE determines the size of the buffer.
++*/
++#define gcdBUFFERED_OUTPUT 0
++
++/*
++ gcdBUFFERED_SIZE
++
++ When set to non-zero, all output is collected into a buffer with the
++ specified size. Once the buffer gets full, the debug buffer will be
++ printed to the console.
++*/
++#define gcdBUFFERED_SIZE (1024 * 1024 * 2)
++
++/*
++ gcdDMA_BUFFER_COUNT
++
++ If greater then zero, the debugger will attempt to find the command buffer
++ where DMA is currently executing and then print this buffer and
++ (gcdDMA_BUFFER_COUNT - 1) buffers before the current one. If set to zero
++ or the current buffer is not found, all buffers are printed.
++*/
++#define gcdDMA_BUFFER_COUNT 0
++
++/*
++ gcdTHREAD_BUFFERS
++
++ When greater then one, will accumulate messages from the specified number
++ of threads in separate output buffers.
++*/
++#define gcdTHREAD_BUFFERS 1
++
++/*
++ gcdENABLE_OVERFLOW
++
++ When set to non-zero, and the output buffer gets full, instead of being
++ printed, it will be allowed to overflow removing the oldest messages.
++*/
++#define gcdENABLE_OVERFLOW 1
++
++/*
++ gcdSHOW_LINE_NUMBER
++
++ When enabledm each print statement will be preceeded with the current
++ line number.
++*/
++#define gcdSHOW_LINE_NUMBER 0
++
++/*
++ gcdSHOW_PROCESS_ID
++
++ When enabledm each print statement will be preceeded with the current
++ process ID.
++*/
++#define gcdSHOW_PROCESS_ID 0
++
++/*
++ gcdSHOW_THREAD_ID
++
++ When enabledm each print statement will be preceeded with the current
++ thread ID.
++*/
++#define gcdSHOW_THREAD_ID 0
++
++/*
++ gcdSHOW_TIME
++
++ When enabled each print statement will be preceeded with the current
++ high-resolution time.
++*/
++#define gcdSHOW_TIME 0
++
++
++/******************************************************************************\
++****************************** Miscellaneous Macros ****************************
++\******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmDBGASSERT(Expression, Format, Value) \
++ if (!(Expression)) \
++ { \
++ _DirectPrint( \
++ "*** gcmDBGASSERT ***************************\n" \
++ " function : %s\n" \
++ " line : %d\n" \
++ " expression : " #Expression "\n" \
++ " actual value : " Format "\n", \
++ __FUNCTION__, __LINE__, Value \
++ ); \
++ }
++#else
++# define gcmDBGASSERT(Expression, Format, Value)
++#endif
++
++#define gcmPTRALIGNMENT(Pointer, Alignemnt) \
++( \
++ gcmALIGN(gcmPTR2INT(Pointer), Alignemnt) - gcmPTR2INT(Pointer) \
++)
++
++#if gcdALIGNBYSIZE
++# define gcmISALIGNED(Offset, Alignment) \
++ (((Offset) & ((Alignment) - 1)) == 0)
++
++# define gcmkALIGNPTR(Type, Pointer, Alignment) \
++ Pointer = (Type) gcmINT2PTR(gcmALIGN(gcmPTR2INT(Pointer), Alignment))
++#else
++# define gcmISALIGNED(Offset, Alignment) \
++ gcvTRUE
++
++# define gcmkALIGNPTR(Type, Pointer, Alignment)
++#endif
++
++#define gcmALIGNSIZE(Offset, Size) \
++ ((Size - Offset) + Size)
++
++#define gcdHAVEPREFIX \
++( \
++ gcdSHOW_TIME \
++ || gcdSHOW_LINE_NUMBER \
++ || gcdSHOW_PROCESS_ID \
++ || gcdSHOW_THREAD_ID \
++)
++
++#if gcdHAVEPREFIX
++
++# define gcdOFFSET 0
++
++#if gcdSHOW_TIME
++#if gcmISALIGNED(gcdOFFSET, 8)
++# define gcdTIMESIZE gcmSIZEOF(gctUINT64)
++# elif gcdOFFSET == 4
++# define gcdTIMESIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64))
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 8
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64)
++# define gcdTIMEFORMAT "0x%016llX"
++# else
++# define gcdTIMEFORMAT ", 0x%016llX"
++# endif
++# else
++# define gcdTIMESIZE 0
++# define gcdTIMEFORMAT
++# endif
++
++#if gcdSHOW_LINE_NUMBER
++#if gcmISALIGNED(gcdOFFSET, 8)
++# define gcdNUMSIZE gcmSIZEOF(gctUINT64)
++# elif gcdOFFSET == 4
++# define gcdNUMSIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64))
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 8
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64)
++# define gcdNUMFORMAT "%8llu"
++# else
++# define gcdNUMFORMAT ", %8llu"
++# endif
++# else
++# define gcdNUMSIZE 0
++# define gcdNUMFORMAT
++# endif
++
++#if gcdSHOW_PROCESS_ID
++#if gcmISALIGNED(gcdOFFSET, 4)
++# define gcdPIDSIZE gcmSIZEOF(gctUINT32)
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 4
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdPIDFORMAT "pid=%5d"
++# else
++# define gcdPIDFORMAT ", pid=%5d"
++# endif
++# else
++# define gcdPIDSIZE 0
++# define gcdPIDFORMAT
++# endif
++
++#if gcdSHOW_THREAD_ID
++#if gcmISALIGNED(gcdOFFSET, 4)
++# define gcdTIDSIZE gcmSIZEOF(gctUINT32)
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 4
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdTIDFORMAT "tid=%5d"
++# else
++# define gcdTIDFORMAT ", tid=%5d"
++# endif
++# else
++# define gcdTIDSIZE 0
++# define gcdTIDFORMAT
++# endif
++
++# define gcdPREFIX_SIZE \
++ ( \
++ gcdTIMESIZE \
++ + gcdNUMSIZE \
++ + gcdPIDSIZE \
++ + gcdTIDSIZE \
++ )
++
++ static const char * _prefixFormat =
++ "["
++ gcdTIMEFORMAT
++ gcdNUMFORMAT
++ gcdPIDFORMAT
++ gcdTIDFORMAT
++ "] ";
++
++#else
++
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdPREFIX_SIZE 0
++
++#endif
++
++/* Assumed largest variable argument leader size. */
++#define gcdVARARG_LEADER gcmSIZEOF(gctUINT64)
++
++/* Alignnments. */
++#if gcdALIGNBYSIZE
++# define gcdPREFIX_ALIGNMENT gcdPREFIX_LEADER
++# define gcdVARARG_ALIGNMENT gcdVARARG_LEADER
++#else
++# define gcdPREFIX_ALIGNMENT 0
++# define gcdVARARG_ALIGNMENT 0
++#endif
++
++#if gcdBUFFERED_OUTPUT
++# define gcdOUTPUTPREFIX _AppendPrefix
++# define gcdOUTPUTSTRING _AppendString
++# define gcdOUTPUTCOPY _AppendCopy
++# define gcdOUTPUTBUFFER _AppendBuffer
++#else
++# define gcdOUTPUTPREFIX _PrintPrefix
++# define gcdOUTPUTSTRING _PrintString
++# define gcdOUTPUTCOPY _PrintString
++# define gcdOUTPUTBUFFER _PrintBuffer
++#endif
++
++/******************************************************************************\
++****************************** Private Structures ******************************
++\******************************************************************************/
++
++typedef enum _gceBUFITEM
++{
++ gceBUFITEM_NONE,
++ gcvBUFITEM_PREFIX,
++ gcvBUFITEM_STRING,
++ gcvBUFITEM_COPY,
++ gcvBUFITEM_BUFFER
++}
++gceBUFITEM;
++
++/* Common item head/buffer terminator. */
++typedef struct _gcsBUFITEM_HEAD * gcsBUFITEM_HEAD_PTR;
++typedef struct _gcsBUFITEM_HEAD
++{
++ gceBUFITEM type;
++}
++gcsBUFITEM_HEAD;
++
++/* String prefix (for ex. [ 1,tid=0x019A]) */
++typedef struct _gcsBUFITEM_PREFIX * gcsBUFITEM_PREFIX_PTR;
++typedef struct _gcsBUFITEM_PREFIX
++{
++ gceBUFITEM type;
++#if gcdHAVEPREFIX
++ gctPOINTER prefixData;
++#endif
++}
++gcsBUFITEM_PREFIX;
++
++/* Buffered string. */
++typedef struct _gcsBUFITEM_STRING * gcsBUFITEM_STRING_PTR;
++typedef struct _gcsBUFITEM_STRING
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gctCONST_STRING message;
++ gctPOINTER messageData;
++ gctUINT messageDataSize;
++}
++gcsBUFITEM_STRING;
++
++/* Buffered string (copy of the string is included with the record). */
++typedef struct _gcsBUFITEM_COPY * gcsBUFITEM_COPY_PTR;
++typedef struct _gcsBUFITEM_COPY
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gctPOINTER messageData;
++ gctUINT messageDataSize;
++}
++gcsBUFITEM_COPY;
++
++/* Memory buffer. */
++typedef struct _gcsBUFITEM_BUFFER * gcsBUFITEM_BUFFER_PTR;
++typedef struct _gcsBUFITEM_BUFFER
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gceDUMP_BUFFER bufferType;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ gctUINT32 dmaAddress;
++#endif
++
++ gctUINT dataSize;
++ gctUINT32 address;
++#if gcdHAVEPREFIX
++ gctPOINTER prefixData;
++#endif
++}
++gcsBUFITEM_BUFFER;
++
++typedef struct _gcsBUFFERED_OUTPUT * gcsBUFFERED_OUTPUT_PTR;
++typedef struct _gcsBUFFERED_OUTPUT
++{
++#if gcdTHREAD_BUFFERS > 1
++ gctUINT32 threadID;
++#endif
++
++#if gcdSHOW_LINE_NUMBER
++ gctUINT64 lineNumber;
++#endif
++
++ gctINT indent;
++
++#if gcdBUFFERED_OUTPUT
++ gctINT start;
++ gctINT index;
++ gctINT count;
++ gctUINT8 buffer[gcdBUFFERED_SIZE];
++#endif
++
++ gcsBUFFERED_OUTPUT_PTR prev;
++ gcsBUFFERED_OUTPUT_PTR next;
++}
++gcsBUFFERED_OUTPUT;
++
++typedef gctUINT (* gcfPRINTSTRING) (
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ );
++
++typedef gctINT (* gcfGETITEMSIZE) (
++ IN gcsBUFITEM_HEAD_PTR Item
++ );
++
++/******************************************************************************\
++******************************* Private Variables ******************************
++\******************************************************************************/
++
++static gcsBUFFERED_OUTPUT _outputBuffer[gcdTHREAD_BUFFERS];
++static gcsBUFFERED_OUTPUT_PTR _outputBufferHead = gcvNULL;
++static gcsBUFFERED_OUTPUT_PTR _outputBufferTail = gcvNULL;
++
++/******************************************************************************\
++****************************** Item Size Functions *****************************
++\******************************************************************************/
++
++#if gcdBUFFERED_OUTPUT
++static gctINT
++_GetTerminatorItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ return gcmSIZEOF(gcsBUFITEM_HEAD);
++}
++
++static gctINT
++_GetPrefixItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_PREFIX_PTR item = (gcsBUFITEM_PREFIX_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++ return vlen + gcdPREFIX_SIZE;
++#else
++ return gcmSIZEOF(gcsBUFITEM_PREFIX);
++#endif
++}
++
++static gctINT
++_GetStringItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_STRING_PTR item = (gcsBUFITEM_STRING_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++ return vlen + item->messageDataSize;
++}
++
++static gctINT
++_GetCopyItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_COPY_PTR item = (gcsBUFITEM_COPY_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++ return vlen + item->messageDataSize;
++}
++
++static gctINT
++_GetBufferItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++ return vlen + gcdPREFIX_SIZE + item->dataSize;
++#else
++ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item;
++ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize;
++#endif
++}
++
++static gcfGETITEMSIZE _itemSize[] =
++{
++ _GetTerminatorItemSize,
++ _GetPrefixItemSize,
++ _GetStringItemSize,
++ _GetCopyItemSize,
++ _GetBufferItemSize
++};
++#endif
++
++/******************************************************************************\
++******************************* Printing Functions *****************************
++\******************************************************************************/
++
++#if gcdDEBUG || gcdBUFFERED_OUTPUT
++static void
++_DirectPrint(
++ gctCONST_STRING Message,
++ ...
++ )
++{
++ gctINT len;
++ char buffer[768];
++ gctARGUMENTS arguments;
++
++ gcmkARGUMENTS_START(arguments, Message);
++ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), Message, arguments);
++ gcmkARGUMENTS_END(arguments);
++
++ buffer[len] = '\0';
++ gcmkOUTPUT_STRING(buffer);
++}
++#endif
++
++static int
++_AppendIndent(
++ IN gctINT Indent,
++ IN char * Buffer,
++ IN int BufferSize
++ )
++{
++ gctINT i;
++
++ gctINT len = 0;
++ gctINT indent = Indent % 40;
++
++ for (i = 0; i < indent; i += 1)
++ {
++ Buffer[len++] = ' ';
++ }
++
++ if (indent != Indent)
++ {
++ len += gcmkSPRINTF(
++ Buffer + len, BufferSize - len, " <%d> ", Indent
++ );
++
++ Buffer[len] = '\0';
++ }
++
++ return len;
++}
++
++#if gcdHAVEPREFIX
++static void
++_PrintPrefix(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ char buffer[768];
++ gctINT len;
++
++ /* Format the string. */
++ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, Data);
++ buffer[len] = '\0';
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++}
++#endif
++
++static void
++_PrintString(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ char buffer[768];
++ gctINT len;
++
++ /* Append the indent string. */
++ len = _AppendIndent(Indent, buffer, gcmSIZEOF(buffer));
++
++ /* Format the string. */
++ len += gcmkVSPRINTF(buffer + len, gcmSIZEOF(buffer) - len, Message, Data);
++ buffer[len] = '\0';
++
++ /* Add end-of-line if missing. */
++ if (buffer[len - 1] != '\n')
++ {
++ buffer[len++] = '\n';
++ buffer[len] = '\0';
++ }
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++}
++
++static void
++_PrintBuffer(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctPOINTER PrefixData,
++ IN gctPOINTER Data,
++ IN gctUINT Address,
++ IN gctUINT DataSize,
++ IN gceDUMP_BUFFER Type,
++ IN gctUINT32 DmaAddress
++ )
++{
++ static gctCONST_STRING _titleString[] =
++ {
++ "CONTEXT BUFFER",
++ "USER COMMAND BUFFER",
++ "KERNEL COMMAND BUFFER",
++ "LINK BUFFER",
++ "WAIT LINK BUFFER",
++ ""
++ };
++
++ static const gctINT COLUMN_COUNT = 8;
++
++ gctUINT i, count, column, address;
++ gctUINT32_PTR data;
++ gctCHAR buffer[768];
++ gctUINT indent, len;
++ gctBOOL command;
++
++ /* Append space for the prefix. */
++#if gcdHAVEPREFIX
++ indent = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, PrefixData);
++ buffer[indent] = '\0';
++#else
++ indent = 0;
++#endif
++
++ /* Append the indent string. */
++ indent += _AppendIndent(
++ Indent, buffer + indent, gcmSIZEOF(buffer) - indent
++ );
++
++ switch (Type)
++ {
++ case gceDUMP_BUFFER_CONTEXT:
++ case gceDUMP_BUFFER_USER:
++ case gceDUMP_BUFFER_KERNEL:
++ case gceDUMP_BUFFER_LINK:
++ case gceDUMP_BUFFER_WAITLINK:
++ /* Form and print the title string. */
++ gcmkSPRINTF2(
++ buffer + indent, gcmSIZEOF(buffer) - indent,
++ "%s%s\n", _titleString[Type],
++ ((DmaAddress >= Address) && (DmaAddress < Address + DataSize))
++ ? " (CURRENT)" : ""
++ );
++
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Terminate the string. */
++ buffer[indent] = '\0';
++
++ /* This is a command buffer. */
++ command = gcvTRUE;
++ break;
++
++ case gceDUMP_BUFFER_FROM_USER:
++ /* This is not a command buffer. */
++ command = gcvFALSE;
++
++ /* No title. */
++ break;
++
++ default:
++ gcmDBGASSERT(gcvFALSE, "%s", "invalid buffer type");
++
++ /* This is not a command buffer. */
++ command = gcvFALSE;
++ }
++
++ /* Overwrite the prefix with spaces. */
++ for (i = 0; i < indent; i += 1)
++ {
++ buffer[i] = ' ';
++ }
++
++ /* Form and print the opening string. */
++ if (command)
++ {
++ gcmkSPRINTF2(
++ buffer + indent, gcmSIZEOF(buffer) - indent,
++ "@[kernel.command %08X %08X\n", Address, DataSize
++ );
++
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Terminate the string. */
++ buffer[indent] = '\0';
++ }
++
++ /* Get initial address. */
++ address = Address;
++
++ /* Cast the data pointer. */
++ data = (gctUINT32_PTR) Data;
++
++ /* Compute the number of double words. */
++ count = DataSize / gcmSIZEOF(gctUINT32);
++
++ /* Print the buffer. */
++ for (i = 0, len = indent, column = 0; i < count; i += 1)
++ {
++ /* Append the address. */
++ if (column == 0)
++ {
++ len += gcmkSPRINTF(
++ buffer + len, gcmSIZEOF(buffer) - len, "0x%08X:", address
++ );
++ }
++
++ /* Append the data value. */
++ len += gcmkSPRINTF2(
++ buffer + len, gcmSIZEOF(buffer) - len, "%c%08X",
++ (address == DmaAddress)? '>' : ' ', data[i]
++ );
++
++ buffer[len] = '\0';
++
++ /* Update the address. */
++ address += gcmSIZEOF(gctUINT32);
++
++ /* Advance column count. */
++ column += 1;
++
++ /* End of line? */
++ if ((column % COLUMN_COUNT) == 0)
++ {
++ /* Append EOL. */
++ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n");
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Reset. */
++ len = indent;
++ column = 0;
++ }
++ }
++
++ /* Print the last partial string. */
++ if (column != 0)
++ {
++ /* Append EOL. */
++ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n");
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++ }
++
++ /* Form and print the opening string. */
++ if (command)
++ {
++ buffer[indent] = '\0';
++ gcmkSTRCAT(buffer, gcmSIZEOF(buffer), "] -- command\n");
++ gcmkOUTPUT_STRING(buffer);
++ }
++}
++
++#if gcdBUFFERED_OUTPUT
++static gctUINT
++_PrintNone(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ /* Return the size of the node. */
++ return gcmSIZEOF(gcsBUFITEM_HEAD);
++}
++
++static gctUINT
++_PrintPrefixWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_PREFIX_PTR item;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_PREFIX_PTR) Item;
++
++ /* Print the message. */
++ _PrintPrefix(OutputBuffer, item->prefixData);
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + gcdPREFIX_SIZE;
++#else
++ return gcmSIZEOF(gcsBUFITEM_PREFIX);
++#endif
++}
++
++static gctUINT
++_PrintStringWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_STRING_PTR item;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_STRING_PTR) Item;
++
++ /* Print the message. */
++ _PrintString(
++ OutputBuffer,
++ item->indent, item->message, item->messageDataSize, item->messageData
++ );
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + item->messageDataSize;
++}
++
++static gctUINT
++_PrintCopyWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_COPY_PTR item;
++ gctCONST_STRING message;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_COPY_PTR) Item;
++
++ /* Determine the string pointer. */
++ message = (gctCONST_STRING) (item + 1);
++
++ /* Print the message. */
++ _PrintString(
++ OutputBuffer,
++ item->indent, message, item->messageDataSize, item->messageData
++ );
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + item->messageDataSize;
++}
++
++static gctUINT
++_PrintBufferWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gctUINT32 dmaAddress;
++ gcsBUFITEM_BUFFER_PTR item;
++ gctPOINTER data;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_BUFFER_PTR) Item;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ dmaAddress = item->dmaAddress;
++#else
++ dmaAddress = 0xFFFFFFFF;
++#endif
++
++ if (dmaAddress != 0)
++ {
++ /* Compute the data address. */
++ data = ((gctUINT8_PTR) item->prefixData) + gcdPREFIX_SIZE;
++
++ /* Print buffer. */
++ _PrintBuffer(
++ OutputBuffer,
++ item->indent, item->prefixData,
++ data, item->address, item->dataSize,
++ item->bufferType, dmaAddress
++ );
++ }
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + gcdPREFIX_SIZE + item->dataSize;
++#else
++ gctUINT32 dmaAddress;
++ gcsBUFITEM_BUFFER_PTR item;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_BUFFER_PTR) Item;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ dmaAddress = item->dmaAddress;
++#else
++ dmaAddress = 0xFFFFFFFF;
++#endif
++
++ if (dmaAddress != 0)
++ {
++ /* Print buffer. */
++ _PrintBuffer(
++ OutputBuffer,
++ item->indent, gcvNULL,
++ item + 1, item->address, item->dataSize,
++ item->bufferType, dmaAddress
++ );
++ }
++
++ /* Return the size of the node. */
++ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize;
++#endif
++}
++
++static gcfPRINTSTRING _printArray[] =
++{
++ _PrintNone,
++ _PrintPrefixWrapper,
++ _PrintStringWrapper,
++ _PrintCopyWrapper,
++ _PrintBufferWrapper
++};
++#endif
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++#if gcdBUFFERED_OUTPUT
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++static gcsBUFITEM_BUFFER_PTR
++_FindCurrentDMABuffer(
++ gctUINT32 DmaAddress
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++ gcsBUFITEM_BUFFER_PTR dmaCurrent;
++
++ /* Reset the current buffer. */
++ dmaCurrent = gcvNULL;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item;
++
++ if ((DmaAddress >= buffer->address) &&
++ (DmaAddress < buffer->address + buffer->dataSize))
++ {
++ dmaCurrent = buffer;
++ }
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++
++ /* Return result. */
++ return dmaCurrent;
++}
++
++static void
++_EnableAllDMABuffers(
++ void
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item;
++
++ /* Enable the buffer. */
++ buffer->dmaAddress = ~0U;
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++}
++
++static void
++_EnableDMABuffers(
++ gctUINT32 DmaAddress,
++ gcsBUFITEM_BUFFER_PTR CurrentDMABuffer
++ )
++{
++ gctINT i, skip, index;
++ gcsBUFITEM_HEAD_PTR item;
++ gcsBUFITEM_BUFFER_PTR buffers[gcdDMA_BUFFER_COUNT];
++
++ /* Reset buffer pointers. */
++ gckOS_ZeroMemory(buffers, gcmSIZEOF(buffers));
++
++ /* Set the current buffer index. */
++ index = -1;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items until the current DMA buffer is found. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ /* Advance the index. */
++ index = (index + 1) % gcdDMA_BUFFER_COUNT;
++
++ /* Add to the buffer array. */
++ buffers[index] = (gcsBUFITEM_BUFFER_PTR) item;
++
++ /* Stop if this is the current DMA buffer. */
++ if ((gcsBUFITEM_BUFFER_PTR) item == CurrentDMABuffer)
++ {
++ break;
++ }
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++
++ /* Enable the found buffers. */
++ gcmDBGASSERT(index != -1, "%d", index);
++
++ for (i = 0; i < gcdDMA_BUFFER_COUNT; i += 1)
++ {
++ if (buffers[index] == gcvNULL)
++ {
++ break;
++ }
++
++ buffers[index]->dmaAddress = DmaAddress;
++
++ index -= 1;
++
++ if (index == -1)
++ {
++ index = gcdDMA_BUFFER_COUNT - 1;
++ }
++ }
++}
++#endif
++
++static void
++_Flush(
++ gctUINT32 DmaAddress
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++
++ gcsBUFFERED_OUTPUT_PTR outputBuffer = _outputBufferHead;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ if ((outputBuffer != gcvNULL) && (outputBuffer->count != 0))
++ {
++ /* Find the current DMA buffer. */
++ gcsBUFITEM_BUFFER_PTR dmaCurrent = _FindCurrentDMABuffer(DmaAddress);
++
++ /* Was the current buffer found? */
++ if (dmaCurrent == gcvNULL)
++ {
++ /* No, print all buffers. */
++ _EnableAllDMABuffers();
++ }
++ else
++ {
++ /* Yes, enable only specified number of buffers. */
++ _EnableDMABuffers(DmaAddress, dmaCurrent);
++ }
++ }
++#endif
++
++ while (outputBuffer != gcvNULL)
++ {
++ if (outputBuffer->count != 0)
++ {
++ _DirectPrint("********************************************************************************\n");
++ _DirectPrint("FLUSHING DEBUG OUTPUT BUFFER (%d elements).\n", outputBuffer->count);
++ _DirectPrint("********************************************************************************\n");
++
++ item = (gcsBUFITEM_HEAD_PTR) &outputBuffer->buffer[outputBuffer->start];
++
++ for (i = 0; i < outputBuffer->count; i += 1)
++ {
++ skip = (* _printArray[item->type]) (outputBuffer, item);
++
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) outputBuffer->buffer;
++ }
++ }
++
++ outputBuffer->start = 0;
++ outputBuffer->index = 0;
++ outputBuffer->count = 0;
++ }
++
++ outputBuffer = outputBuffer->next;
++ }
++}
++
++static gcsBUFITEM_HEAD_PTR
++_AllocateItem(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Size
++ )
++{
++ gctINT skip;
++ gcsBUFITEM_HEAD_PTR item, next;
++
++#if gcdENABLE_OVERFLOW
++ if (
++ (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ ||
++ (
++ (OutputBuffer->index < OutputBuffer->start) &&
++ (OutputBuffer->index + Size >= OutputBuffer->start)
++ )
++ )
++ {
++ if (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ {
++ if (OutputBuffer->index < OutputBuffer->start)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start];
++
++ while (item->type != gceBUFITEM_NONE)
++ {
++ skip = (* _itemSize[item->type]) (item);
++
++ OutputBuffer->start += skip;
++ OutputBuffer->count -= 1;
++
++ item->type = gceBUFITEM_NONE;
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++ }
++
++ OutputBuffer->start = 0;
++ }
++
++ OutputBuffer->index = 0;
++ }
++
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start];
++
++ while (OutputBuffer->start - OutputBuffer->index <= Size)
++ {
++ skip = (* _itemSize[item->type]) (item);
++
++ OutputBuffer->start += skip;
++ OutputBuffer->count -= 1;
++
++ item->type = gceBUFITEM_NONE;
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ if (item->type == gceBUFITEM_NONE)
++ {
++ OutputBuffer->start = 0;
++ break;
++ }
++ }
++ }
++#else
++ if (OutputBuffer->index + Size > gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ {
++ _DirectPrint("\nMessage buffer full; forcing message flush.\n\n");
++ _Flush(~0U);
++ }
++#endif
++
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->index];
++
++ OutputBuffer->index += Size;
++ OutputBuffer->count += 1;
++
++ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + Size);
++ next->type = gceBUFITEM_NONE;
++
++ return item;
++}
++
++#if gcdALIGNBYSIZE
++static void
++_FreeExtraSpace(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Item,
++ IN gctINT ItemSize,
++ IN gctINT FreeSize
++ )
++{
++ gcsBUFITEM_HEAD_PTR next;
++
++ OutputBuffer->index -= FreeSize;
++
++ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) Item + ItemSize);
++ next->type = gceBUFITEM_NONE;
++}
++#endif
++
++#if gcdHAVEPREFIX
++static void
++_AppendPrefix(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR prefixData;
++ gcsBUFITEM_PREFIX_PTR item;
++ gctINT allocSize;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_PREFIX)
++ + gcdPREFIX_SIZE
++ + gcdPREFIX_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_PREFIX_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial prefix data pointer. */
++ prefixData = (gctUINT8_PTR) (item + 1);
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT);
++ prefixData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_PREFIX;
++ item->prefixData = prefixData;
++
++ /* Copy argument value. */
++ memcpy(prefixData, Data, gcdPREFIX_SIZE);
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size = gcmSIZEOF(gcsBUFITEM_PREFIX) + gcdPREFIX_SIZE + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++#endif
++
++static void
++_AppendString(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR messageData;
++ gcsBUFITEM_STRING_PTR item;
++ gctINT allocSize;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_STRING)
++ + ArgumentSize
++ + gcdVARARG_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_STRING_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial message data pointer. */
++ messageData = (gctUINT8_PTR) (item + 1);
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT);
++ messageData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_STRING;
++ item->indent = Indent;
++ item->message = Message;
++ item->messageData = messageData;
++ item->messageDataSize = ArgumentSize;
++
++ /* Copy argument value. */
++ if (ArgumentSize != 0)
++ {
++ memcpy(messageData, Data, ArgumentSize);
++ }
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size = gcmSIZEOF(gcsBUFITEM_STRING) + ArgumentSize + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++
++static void
++_AppendCopy(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR messageData;
++ gcsBUFITEM_COPY_PTR item;
++ gctINT allocSize;
++ gctINT messageLength;
++ gctCONST_STRING message;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ /* Get the length of the string. */
++ messageLength = strlen(Message) + 1;
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_COPY)
++ + messageLength
++ + ArgumentSize
++ + gcdVARARG_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_COPY_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Determine the message placement. */
++ message = (gctCONST_STRING) (item + 1);
++
++ /* Compute the initial message data pointer. */
++ messageData = (gctUINT8_PTR) message + messageLength;
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ if (ArgumentSize == 0)
++ {
++ alignment = 0;
++ }
++ else
++ {
++ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT);
++ messageData += alignment;
++ }
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_COPY;
++ item->indent = Indent;
++ item->messageData = messageData;
++ item->messageDataSize = ArgumentSize;
++
++ /* Copy the message. */
++ memcpy((gctPOINTER) message, Message, messageLength);
++
++ /* Copy argument value. */
++ if (ArgumentSize != 0)
++ {
++ memcpy(messageData, Data, ArgumentSize);
++ }
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size
++ = gcmSIZEOF(gcsBUFITEM_COPY)
++ + messageLength
++ + ArgumentSize
++ + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++
++static void
++_AppendBuffer(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctPOINTER PrefixData,
++ IN gctPOINTER Data,
++ IN gctUINT Address,
++ IN gctUINT DataSize,
++ IN gceDUMP_BUFFER Type,
++ IN gctUINT32 DmaAddress
++ )
++{
++#if gcdHAVEPREFIX
++ gctUINT8_PTR prefixData;
++ gcsBUFITEM_BUFFER_PTR item;
++ gctINT allocSize;
++ gctPOINTER data;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ gcmDBGASSERT(DataSize != 0, "%d", DataSize);
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_BUFFER)
++ + gcdPREFIX_SIZE
++ + gcdPREFIX_ALIGNMENT
++ + DataSize;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial prefix data pointer. */
++ prefixData = (gctUINT8_PTR) (item + 1);
++
++#if gcdALIGNBYSIZE
++ /* Align the data pointer as necessary. */
++ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT);
++ prefixData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_BUFFER;
++ item->indent = Indent;
++ item->bufferType = Type;
++ item->dataSize = DataSize;
++ item->address = Address;
++ item->prefixData = prefixData;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ item->dmaAddress = DmaAddress;
++#endif
++
++ /* Copy prefix data. */
++ memcpy(prefixData, PrefixData, gcdPREFIX_SIZE);
++
++ /* Compute the data pointer. */
++ data = prefixData + gcdPREFIX_SIZE;
++
++ /* Copy argument value. */
++ memcpy(data, Data, DataSize);
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size
++ = gcmSIZEOF(gcsBUFITEM_BUFFER)
++ + gcdPREFIX_SIZE
++ + alignment
++ + DataSize;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++#else
++ gcsBUFITEM_BUFFER_PTR item;
++ gctINT size;
++
++ gcmDBGASSERT(DataSize != 0, "%d", DataSize);
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ size = gcmSIZEOF(gcsBUFITEM_BUFFER) + DataSize;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, size);
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_BUFFER;
++ item->indent = Indent;
++ item->dataSize = DataSize;
++ item->address = Address;
++
++ /* Copy argument value. */
++ memcpy(item + 1, Data, DataSize);
++#endif
++}
++#endif
++
++static gcmINLINE void
++_InitBuffers(
++ void
++ )
++{
++ int i;
++
++ if (_outputBufferHead == gcvNULL)
++ {
++ for (i = 0; i < gcdTHREAD_BUFFERS; i += 1)
++ {
++ if (_outputBufferTail == gcvNULL)
++ {
++ _outputBufferHead = &_outputBuffer[i];
++ }
++ else
++ {
++ _outputBufferTail->next = &_outputBuffer[i];
++ }
++
++#if gcdTHREAD_BUFFERS > 1
++ _outputBuffer[i].threadID = ~0U;
++#endif
++
++ _outputBuffer[i].prev = _outputBufferTail;
++ _outputBuffer[i].next = gcvNULL;
++
++ _outputBufferTail = &_outputBuffer[i];
++ }
++ }
++}
++
++static gcmINLINE gcsBUFFERED_OUTPUT_PTR
++_GetOutputBuffer(
++ void
++ )
++{
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++
++#if gcdTHREAD_BUFFERS > 1
++ /* Get the current thread ID. */
++ gctUINT32 ThreadID = gcmkGETTHREADID();
++
++ /* Locate the output buffer for the thread. */
++ outputBuffer = _outputBufferHead;
++
++ while (outputBuffer != gcvNULL)
++ {
++ if (outputBuffer->threadID == ThreadID)
++ {
++ break;
++ }
++
++ outputBuffer = outputBuffer->next;
++ }
++
++ /* No matching buffer found? */
++ if (outputBuffer == gcvNULL)
++ {
++ /* Get the tail for the buffer. */
++ outputBuffer = _outputBufferTail;
++
++ /* Move it to the head. */
++ _outputBufferTail = _outputBufferTail->prev;
++ _outputBufferTail->next = gcvNULL;
++
++ outputBuffer->prev = gcvNULL;
++ outputBuffer->next = _outputBufferHead;
++
++ _outputBufferHead->prev = outputBuffer;
++ _outputBufferHead = outputBuffer;
++
++ /* Reset the buffer. */
++ outputBuffer->threadID = ThreadID;
++#if gcdBUFFERED_OUTPUT
++ outputBuffer->start = 0;
++ outputBuffer->index = 0;
++ outputBuffer->count = 0;
++#endif
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber = 0;
++#endif
++ }
++#else
++ outputBuffer = _outputBufferHead;
++#endif
++
++ return outputBuffer;
++}
++
++static gcmINLINE int _GetArgumentSize(
++ IN gctCONST_STRING Message
++ )
++{
++ int i, count;
++
++ gcmDBGASSERT(Message != gcvNULL, "%p", Message);
++
++ for (i = 0, count = 0; Message[i]; i += 1)
++ {
++ if (Message[i] == '%')
++ {
++ count += 1;
++ }
++ }
++
++ return count * gcmSIZEOF(gctUINT32);
++}
++
++#if gcdHAVEPREFIX
++static void
++_InitPrefixData(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR data = (gctUINT8_PTR) Data;
++
++#if gcdSHOW_TIME
++ {
++ gctUINT64 time;
++ gckOS_GetProfileTick(&time);
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64));
++ * ((gctUINT64_PTR) data) = time;
++ data += gcmSIZEOF(gctUINT64);
++ }
++#endif
++
++#if gcdSHOW_LINE_NUMBER
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64));
++ * ((gctUINT64_PTR) data) = OutputBuffer->lineNumber;
++ data += gcmSIZEOF(gctUINT64);
++ }
++#endif
++
++#if gcdSHOW_PROCESS_ID
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32));
++ * ((gctUINT32_PTR) data) = gcmkGETPROCESSID();
++ data += gcmSIZEOF(gctUINT32);
++ }
++#endif
++
++#if gcdSHOW_THREAD_ID
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32));
++ * ((gctUINT32_PTR) data) = gcmkGETTHREADID();
++ }
++#endif
++}
++#endif
++
++static void
++_Print(
++ IN gctUINT ArgumentSize,
++ IN gctBOOL CopyMessage,
++ IN gctCONST_STRING Message,
++ IN gctARGUMENTS Arguments
++ )
++{
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++ gcmkDECLARE_LOCK(lockHandle);
++
++ gcmkLOCKSECTION(lockHandle);
++
++ /* Initialize output buffer list. */
++ _InitBuffers();
++
++ /* Locate the proper output buffer. */
++ outputBuffer = _GetOutputBuffer();
++
++ /* Update the line number. */
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber += 1;
++#endif
++
++ /* Print prefix. */
++#if gcdHAVEPREFIX
++ {
++ gctUINT8_PTR alignedPrefixData;
++ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT];
++
++ /* Compute aligned pointer. */
++ alignedPrefixData = prefixData;
++ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT);
++
++ /* Initialize the prefix data. */
++ _InitPrefixData(outputBuffer, alignedPrefixData);
++
++ /* Print the prefix. */
++ gcdOUTPUTPREFIX(outputBuffer, alignedPrefixData);
++ }
++#endif
++
++ /* Form the indent string. */
++ if (strncmp(Message, "--", 2) == 0)
++ {
++ outputBuffer->indent -= 2;
++ }
++
++ /* Print the message. */
++ if (CopyMessage)
++ {
++ gcdOUTPUTCOPY(
++ outputBuffer, outputBuffer->indent,
++ Message, ArgumentSize, * (gctPOINTER *) &Arguments
++ );
++ }
++ else
++ {
++ gcdOUTPUTSTRING(
++ outputBuffer, outputBuffer->indent,
++ Message, ArgumentSize, * (gctPOINTER *) &Arguments
++ );
++ }
++
++ /* Check increasing indent. */
++ if (strncmp(Message, "++", 2) == 0)
++ {
++ outputBuffer->indent += 2;
++ }
++
++ gcmkUNLOCKSECTION(lockHandle);
++}
++
++
++/******************************************************************************\
++********************************* Debug Macros *********************************
++\******************************************************************************/
++
++#ifdef __QNXNTO__
++
++extern volatile unsigned g_nQnxInIsrs;
++
++#define gcmDEBUGPRINT(ArgumentSize, CopyMessage, Message) \
++{ \
++ if (atomic_add_value(&g_nQnxInIsrs, 1) == 0) \
++ { \
++ gctARGUMENTS __arguments__; \
++ gcmkARGUMENTS_START(__arguments__, Message); \
++ _Print(ArgumentSize, CopyMessage, Message, __arguments__); \
++ gcmkARGUMENTS_END(__arguments__); \
++ } \
++ atomic_sub(&g_nQnxInIsrs, 1); \
++}
++
++#else
++
++#define gcmDEBUGPRINT(ArgumentSize, CopyMessage, Message) \
++{ \
++ gctARGUMENTS __arguments__; \
++ gcmkARGUMENTS_START(__arguments__, Message); \
++ _Print(ArgumentSize, CopyMessage, Message, __arguments__); \
++ gcmkARGUMENTS_END(__arguments__); \
++}
++
++#endif
++
++/******************************************************************************\
++********************************** Debug Code **********************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_Print
++**
++** Send a message to the debugger.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_PrintN
++**
++** Send a message to the debugger.
++**
++** INPUT:
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_PrintN(
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyPrint
++**
++** Send a message to the debugger. If in buffered output mode, the entire
++** message will be copied into the buffer instead of using the pointer to
++** the string.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_CopyPrint(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvTRUE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DumpBuffer
++**
++** Print the contents of the specified buffer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Buffer
++** Pointer to the buffer to print.
++**
++** gctUINT Size
++** Size of the buffer.
++**
++** gceDUMP_BUFFER Type
++** Buffer type.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DumpBuffer(
++ IN gckOS Os,
++ IN gctPOINTER Buffer,
++ IN gctUINT Size,
++ IN gceDUMP_BUFFER Type,
++ IN gctBOOL CopyMessage
++ )
++{
++ gctUINT32 address;
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++ static gctBOOL userLocked;
++ gctCHAR *buffer = (gctCHAR*)Buffer;
++
++ gcmkDECLARE_LOCK(lockHandle);
++
++ /* Request lock when not coming from user,
++ or coming from user and not yet locked
++ and message is starting with @[. */
++ if (Type == gceDUMP_BUFFER_FROM_USER)
++ {
++ if ((Size > 2)
++ && (buffer[0] == '@')
++ && (buffer[1] == '['))
++ {
++ /* Beginning of a user dump. */
++ gcmkLOCKSECTION(lockHandle);
++ userLocked = gcvTRUE;
++ }
++ /* Else, let it pass through. */
++ }
++ else
++ {
++ gcmkLOCKSECTION(lockHandle);
++ userLocked = gcvFALSE;
++ }
++
++ if (Buffer != gcvNULL)
++ {
++ /* Initialize output buffer list. */
++ _InitBuffers();
++
++ /* Locate the proper output buffer. */
++ outputBuffer = _GetOutputBuffer();
++
++ /* Update the line number. */
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber += 1;
++#endif
++
++ /* Get the physical address of the buffer. */
++ if (Type != gceDUMP_BUFFER_FROM_USER)
++ {
++ gcmkVERIFY_OK(gckOS_GetPhysicalAddress(Os, Buffer, &address));
++ }
++ else
++ {
++ address = 0;
++ }
++
++#if gcdHAVEPREFIX
++ {
++ gctUINT8_PTR alignedPrefixData;
++ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT];
++
++ /* Compute aligned pointer. */
++ alignedPrefixData = prefixData;
++ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT);
++
++ /* Initialize the prefix data. */
++ _InitPrefixData(outputBuffer, alignedPrefixData);
++
++ /* Print/schedule the buffer. */
++ gcdOUTPUTBUFFER(
++ outputBuffer, outputBuffer->indent,
++ alignedPrefixData, Buffer, address, Size, Type, 0
++ );
++ }
++#else
++ /* Print/schedule the buffer. */
++ if (Type == gceDUMP_BUFFER_FROM_USER)
++ {
++ gcdOUTPUTSTRING(
++ outputBuffer, outputBuffer->indent,
++ Buffer, 0, gcvNULL
++ );
++ }
++ else
++ {
++ gcdOUTPUTBUFFER(
++ outputBuffer, outputBuffer->indent,
++ gcvNULL, Buffer, address, Size, Type, 0
++ );
++ }
++#endif
++ }
++
++ /* Unlock when not coming from user,
++ or coming from user and not yet locked. */
++ if (userLocked)
++ {
++ if ((Size > 4)
++ && (buffer[0] == ']')
++ && (buffer[1] == ' ')
++ && (buffer[2] == '-')
++ && (buffer[3] == '-'))
++ {
++ /* End of a user dump. */
++ gcmkUNLOCKSECTION(lockHandle);
++ userLocked = gcvFALSE;
++ }
++ /* Else, let it pass through, don't unlock. */
++ }
++ else
++ {
++ gcmkUNLOCKSECTION(lockHandle);
++ }
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTrace
++**
++** Send a leveled message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level of message.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if (Level > _debugLevel)
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceN
++**
++** Send a leveled message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level of message.
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceN(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if (Level > _debugLevel)
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceZone
++**
++** Send a leveled and zoned message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level for message.
++**
++** gctUINT32 Zone
++** Debug zone for message.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if ((Level > _debugLevel) || !(Zone & _debugZones))
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceZoneN
++**
++** Send a leveled and zoned message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level for message.
++**
++** gctUINT32 Zone
++** Debug zone for message.
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceZoneN(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if ((Level > _debugLevel) || !(Zone & _debugZones))
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugBreak
++**
++** Break into the debugger.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_DebugBreak(
++ void
++ )
++{
++ gckOS_DebugTrace(gcvLEVEL_ERROR, "%s(%d)", __FUNCTION__, __LINE__);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugFatal
++**
++** Send a message to the debugger and break into the debugger.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmkPRINT_VERSION();
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++
++ /* Break into the debugger. */
++ gckOS_DebugBreak();
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugLevel
++**
++** Set the debug level.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** New debug level.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugLevel(
++ IN gctUINT32 Level
++ )
++{
++ _debugLevel = Level;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugZone
++**
++** Set the debug zone.
++**
++** INPUT:
++**
++** gctUINT32 Zone
++** New debug zone.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_SetDebugZone(
++ IN gctUINT32 Zone
++ )
++{
++ _debugZones = Zone;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugLevelZone
++**
++** Set the debug level and zone.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** New debug level.
++**
++** gctUINT32 Zone
++** New debug zone.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ )
++{
++ _debugLevel = Level;
++ _debugZones = Zone;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugZones
++**
++** Enable or disable debug zones.
++**
++** INPUT:
++**
++** gctUINT32 Zones
++** Debug zones to enable or disable.
++**
++** gctBOOL Enable
++** Set to gcvTRUE to enable the zones (or the Zones with the current
++** zones) or gcvFALSE to disable the specified Zones.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ )
++{
++ if (Enable)
++ {
++ /* Enable the zones. */
++ _debugZones |= Zones;
++ }
++ else
++ {
++ /* Disable the zones. */
++ _debugZones &= ~Zones;
++ }
++}
++
++/*******************************************************************************
++**
++** gckOS_Verify
++**
++** Called to verify the result of a function call.
++**
++** INPUT:
++**
++** gceSTATUS Status
++** Function call result.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_Verify(
++ IN gceSTATUS Status
++ )
++{
++ _lastError = Status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugFlush
++**
++** Force messages to be flushed out.
++**
++** INPUT:
++**
++** gctCONST_STRING CallerName
++** Name of the caller function.
++**
++** gctUINT LineNumber
++** Line number of the caller.
++**
++** gctUINT32 DmaAddress
++** The current DMA address or ~0U to ignore.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugFlush(
++ gctCONST_STRING CallerName,
++ gctUINT LineNumber,
++ gctUINT32 DmaAddress
++ )
++{
++#if gcdBUFFERED_OUTPUT
++ _DirectPrint("\nFlush requested by %s(%d).\n\n", CallerName, LineNumber);
++ _Flush(DmaAddress);
++#endif
++}
++gctCONST_STRING
++gckOS_DebugStatus2Name(
++ gceSTATUS status
++ )
++{
++ switch (status)
++ {
++ case gcvSTATUS_OK:
++ return "gcvSTATUS_OK";
++ case gcvSTATUS_TRUE:
++ return "gcvSTATUS_TRUE";
++ case gcvSTATUS_NO_MORE_DATA:
++ return "gcvSTATUS_NO_MORE_DATA";
++ case gcvSTATUS_CACHED:
++ return "gcvSTATUS_CACHED";
++ case gcvSTATUS_MIPMAP_TOO_LARGE:
++ return "gcvSTATUS_MIPMAP_TOO_LARGE";
++ case gcvSTATUS_NAME_NOT_FOUND:
++ return "gcvSTATUS_NAME_NOT_FOUND";
++ case gcvSTATUS_NOT_OUR_INTERRUPT:
++ return "gcvSTATUS_NOT_OUR_INTERRUPT";
++ case gcvSTATUS_MISMATCH:
++ return "gcvSTATUS_MISMATCH";
++ case gcvSTATUS_MIPMAP_TOO_SMALL:
++ return "gcvSTATUS_MIPMAP_TOO_SMALL";
++ case gcvSTATUS_LARGER:
++ return "gcvSTATUS_LARGER";
++ case gcvSTATUS_SMALLER:
++ return "gcvSTATUS_SMALLER";
++ case gcvSTATUS_CHIP_NOT_READY:
++ return "gcvSTATUS_CHIP_NOT_READY";
++ case gcvSTATUS_NEED_CONVERSION:
++ return "gcvSTATUS_NEED_CONVERSION";
++ case gcvSTATUS_SKIP:
++ return "gcvSTATUS_SKIP";
++ case gcvSTATUS_DATA_TOO_LARGE:
++ return "gcvSTATUS_DATA_TOO_LARGE";
++ case gcvSTATUS_INVALID_CONFIG:
++ return "gcvSTATUS_INVALID_CONFIG";
++ case gcvSTATUS_CHANGED:
++ return "gcvSTATUS_CHANGED";
++ case gcvSTATUS_NOT_SUPPORT_DITHER:
++ return "gcvSTATUS_NOT_SUPPORT_DITHER";
++
++ case gcvSTATUS_INVALID_ARGUMENT:
++ return "gcvSTATUS_INVALID_ARGUMENT";
++ case gcvSTATUS_INVALID_OBJECT:
++ return "gcvSTATUS_INVALID_OBJECT";
++ case gcvSTATUS_OUT_OF_MEMORY:
++ return "gcvSTATUS_OUT_OF_MEMORY";
++ case gcvSTATUS_MEMORY_LOCKED:
++ return "gcvSTATUS_MEMORY_LOCKED";
++ case gcvSTATUS_MEMORY_UNLOCKED:
++ return "gcvSTATUS_MEMORY_UNLOCKED";
++ case gcvSTATUS_HEAP_CORRUPTED:
++ return "gcvSTATUS_HEAP_CORRUPTED";
++ case gcvSTATUS_GENERIC_IO:
++ return "gcvSTATUS_GENERIC_IO";
++ case gcvSTATUS_INVALID_ADDRESS:
++ return "gcvSTATUS_INVALID_ADDRESS";
++ case gcvSTATUS_CONTEXT_LOSSED:
++ return "gcvSTATUS_CONTEXT_LOSSED";
++ case gcvSTATUS_TOO_COMPLEX:
++ return "gcvSTATUS_TOO_COMPLEX";
++ case gcvSTATUS_BUFFER_TOO_SMALL:
++ return "gcvSTATUS_BUFFER_TOO_SMALL";
++ case gcvSTATUS_INTERFACE_ERROR:
++ return "gcvSTATUS_INTERFACE_ERROR";
++ case gcvSTATUS_NOT_SUPPORTED:
++ return "gcvSTATUS_NOT_SUPPORTED";
++ case gcvSTATUS_MORE_DATA:
++ return "gcvSTATUS_MORE_DATA";
++ case gcvSTATUS_TIMEOUT:
++ return "gcvSTATUS_TIMEOUT";
++ case gcvSTATUS_OUT_OF_RESOURCES:
++ return "gcvSTATUS_OUT_OF_RESOURCES";
++ case gcvSTATUS_INVALID_DATA:
++ return "gcvSTATUS_INVALID_DATA";
++ case gcvSTATUS_INVALID_MIPMAP:
++ return "gcvSTATUS_INVALID_MIPMAP";
++ case gcvSTATUS_NOT_FOUND:
++ return "gcvSTATUS_NOT_FOUND";
++ case gcvSTATUS_NOT_ALIGNED:
++ return "gcvSTATUS_NOT_ALIGNED";
++ case gcvSTATUS_INVALID_REQUEST:
++ return "gcvSTATUS_INVALID_REQUEST";
++ case gcvSTATUS_GPU_NOT_RESPONDING:
++ return "gcvSTATUS_GPU_NOT_RESPONDING";
++ case gcvSTATUS_TIMER_OVERFLOW:
++ return "gcvSTATUS_TIMER_OVERFLOW";
++ case gcvSTATUS_VERSION_MISMATCH:
++ return "gcvSTATUS_VERSION_MISMATCH";
++ case gcvSTATUS_LOCKED:
++ return "gcvSTATUS_LOCKED";
++
++ /* Linker errors. */
++ case gcvSTATUS_GLOBAL_TYPE_MISMATCH:
++ return "gcvSTATUS_GLOBAL_TYPE_MISMATCH";
++ case gcvSTATUS_TOO_MANY_ATTRIBUTES:
++ return "gcvSTATUS_TOO_MANY_ATTRIBUTES";
++ case gcvSTATUS_TOO_MANY_UNIFORMS:
++ return "gcvSTATUS_TOO_MANY_UNIFORMS";
++ case gcvSTATUS_TOO_MANY_VARYINGS:
++ return "gcvSTATUS_TOO_MANY_VARYINGS";
++ case gcvSTATUS_UNDECLARED_VARYING:
++ return "gcvSTATUS_UNDECLARED_VARYING";
++ case gcvSTATUS_VARYING_TYPE_MISMATCH:
++ return "gcvSTATUS_VARYING_TYPE_MISMATCH";
++ case gcvSTATUS_MISSING_MAIN:
++ return "gcvSTATUS_MISSING_MAIN";
++ case gcvSTATUS_NAME_MISMATCH:
++ return "gcvSTATUS_NAME_MISMATCH";
++ case gcvSTATUS_INVALID_INDEX:
++ return "gcvSTATUS_INVALID_INDEX";
++ default:
++ return "nil";
++ }
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,2888 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include "gc_hal_kernel_buffer.h"
++
++#ifdef __QNXNTO__
++#include <atomic.h>
++#include "gc_hal_kernel_qnx.h"
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_EVENT
++
++#define gcdEVENT_ALLOCATION_COUNT (4096 / gcmSIZEOF(gcsHAL_INTERFACE))
++#define gcdEVENT_MIN_THRESHOLD 4
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++
++static gceSTATUS
++gckEVENT_AllocateQueue(
++ IN gckEVENT Event,
++ OUT gcsEVENT_QUEUE_PTR * Queue
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++
++ /* Do we have free queues? */
++ if (Event->freeList == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Move one free queue from the free list. */
++ * Queue = Event->freeList;
++ Event->freeList = Event->freeList->next;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Queue=0x%x", gcmOPT_POINTER(Queue));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckEVENT_FreeQueue(
++ IN gckEVENT Event,
++ OUT gcsEVENT_QUEUE_PTR Queue
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++
++ /* Move one free queue from the free list. */
++ Queue->next = Event->freeList;
++ Event->freeList = Queue;
++
++ /* Success. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckEVENT_FreeRecord(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->freeEventMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Push the record on the free list. */
++ Record->next = Event->freeEventList;
++ Event->freeEventList = Record;
++ Event->freeEventCount += 1;
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++gckEVENT_IsEmpty(
++ IN gckEVENT Event,
++ OUT gctBOOL_PTR IsEmpty
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T i;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(IsEmpty != gcvNULL);
++
++ /* Assume the event queue is empty. */
++ *IsEmpty = gcvTRUE;
++
++ /* Try acquiring the mutex. */
++ status = gckOS_AcquireMutex(Event->os, Event->eventQueueMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Timeout - queue is no longer empty. */
++ *IsEmpty = gcvFALSE;
++ }
++ else
++ {
++ /* Bail out on error. */
++ gcmkONERROR(status);
++
++ /* Walk the event queue. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ /* Check whether this event is in use. */
++ if (Event->queues[i].head != gcvNULL)
++ {
++ /* The event is in use, hence the queue is not empty. */
++ *IsEmpty = gcvFALSE;
++ break;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*IsEmpty=%d", gcmOPT_VALUE(IsEmpty));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_TryToIdleGPU(
++ IN gckEVENT Event
++)
++{
++ gceSTATUS status;
++ gctBOOL empty = gcvFALSE, idle = gcvFALSE;
++ gctUINT32 process, thread;
++ gctBOOL powerLocked = gcvFALSE;
++ gckHARDWARE hardware;
++
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Grab gckHARDWARE object. */
++ hardware = Event->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++
++ /* Check whether the event queue is empty. */
++ gcmkONERROR(gckEVENT_IsEmpty(Event, &empty));
++
++ if (empty)
++ {
++ status = gckOS_AcquireMutex(hardware->os, hardware->powerMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ /* Just return to prevent deadlock. */
++ if ((hardware->powerProcess != process)
++ || (hardware->powerThread != thread))
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ powerLocked = gcvTRUE;
++ }
++
++ /* Query whether the hardware is idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Event->kernel->hardware, &idle));
++
++ if (powerLocked)
++ {
++ gcmkONERROR(gckOS_ReleaseMutex(hardware->os, hardware->powerMutex));
++ powerLocked = gcvFALSE;
++ }
++
++ if (idle)
++ {
++ /* Inform the system of idle GPU. */
++ gcmkONERROR(gckOS_Broadcast(Event->os,
++ Event->kernel->hardware,
++ gcvBROADCAST_GPU_IDLE));
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (powerLocked)
++ {
++ gcmkONERROR(gckOS_ReleaseMutex(hardware->os, hardware->powerMutex));
++ powerLocked = gcvFALSE;
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++__RemoveRecordFromProcessDB(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record
++ )
++{
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ while (Record != gcvNULL)
++ {
++ if (Record->info.command == gcvHAL_SIGNAL)
++ {
++ /* TODO: Find a better place to bind signal to hardware.*/
++ gcmkVERIFY_OK(gckOS_SignalSetHardware(Event->os,
++ gcmUINT64_TO_PTR(Record->info.u.Signal.signal),
++ Event->kernel->hardware));
++ }
++
++ if (Record->fromKernel)
++ {
++ /* No need to check db if event is from kernel. */
++ Record = Record->next;
++ continue;
++ }
++
++ switch (Record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_NON_PAGED,
++ gcmUINT64_TO_PTR(Record->info.u.FreeNonPagedMemory.logical)));
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_CONTIGUOUS,
++ gcmUINT64_TO_PTR(Record->info.u.FreeContiguousMemory.logical)));
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY,
++ gcmUINT64_TO_PTR(Record->info.u.FreeVideoMemory.node)));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmUINT64_TO_PTR(Record->info.u.UnlockVideoMemory.node)));
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Record->info.u.UnmapUserMemory.info)));
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_COMMAND_BUFFER,
++ gcmUINT64_TO_PTR(Record->info.u.FreeVirtualCommandBuffer.logical)));
++ break;
++
++ default:
++ break;
++ }
++
++ Record = Record->next;
++ }
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_SubmitTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckEVENT event = (gckEVENT)Data;
++ gcmkVERIFY_OK(gckEVENT_Submit(event, gcvTRUE, gcvFALSE));
++}
++
++/******************************************************************************\
++******************************* gckEVENT API Code *******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckEVENT_Construct
++**
++** Construct a new gckEVENT object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gckEVENT * Event
++** Pointer to a variable that receives the gckEVENT object pointer.
++*/
++gceSTATUS
++gckEVENT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckEVENT * Event
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gckEVENT eventObj = gcvNULL;
++ int i;
++ gcsEVENT_PTR record;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Event != gcvNULL);
++
++ /* Extract the pointer to the gckOS object. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate the gckEVENT object. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckEVENT), &pointer));
++
++ eventObj = pointer;
++
++ /* Reset the object. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(eventObj, gcmSIZEOF(struct _gckEVENT)));
++
++ /* Initialize the gckEVENT object. */
++ eventObj->object.type = gcvOBJ_EVENT;
++ eventObj->kernel = Kernel;
++ eventObj->os = os;
++
++ /* Create the mutexes. */
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventQueueMutex));
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->freeEventMutex));
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventListMutex));
++
++ /* Create a bunch of event reccords. */
++ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1)
++ {
++ /* Allocate an event record. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsEVENT), &pointer));
++
++ record = pointer;
++
++ /* Push it on the free list. */
++ record->next = eventObj->freeEventList;
++ eventObj->freeEventList = record;
++ eventObj->freeEventCount += 1;
++ }
++
++ /* Initialize the free list of event queues. */
++ for (i = 0; i < gcdREPO_LIST_COUNT; i += 1)
++ {
++ eventObj->repoList[i].next = eventObj->freeList;
++ eventObj->freeList = &eventObj->repoList[i];
++ }
++
++ /* Construct the atom. */
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->freeAtom));
++ gcmkONERROR(gckOS_AtomSet(os,
++ eventObj->freeAtom,
++ gcmCOUNTOF(eventObj->queues)));
++
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->pending));
++#endif
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(os,
++ _SubmitTimerFunction,
++ (gctPOINTER)eventObj,
++ &eventObj->submitTimer));
++
++ /* Return pointer to the gckEVENT object. */
++ *Event = eventObj;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Event=0x%x", *Event);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (eventObj != gcvNULL)
++ {
++ if (eventObj->eventQueueMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventQueueMutex));
++ }
++
++ if (eventObj->freeEventMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->freeEventMutex));
++ }
++
++ if (eventObj->eventListMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventListMutex));
++ }
++
++ while (eventObj->freeEventList != gcvNULL)
++ {
++ record = eventObj->freeEventList;
++ eventObj->freeEventList = record->next;
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, record));
++ }
++
++ if (eventObj->freeAtom != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->freeAtom));
++ }
++
++#if gcdSMP
++ if (eventObj->pending != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->pending));
++ }
++#endif
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, eventObj));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Destroy
++**
++** Destroy an gckEVENT object.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Destroy(
++ IN gckEVENT Event
++ )
++{
++ gcsEVENT_PTR record;
++ gcsEVENT_QUEUE_PTR queue;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ if (Event->submitTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Event->os, Event->submitTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Event->os, Event->submitTimer));
++ }
++
++ /* Delete the queue mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventQueueMutex));
++
++ /* Free all free events. */
++ while (Event->freeEventList != gcvNULL)
++ {
++ record = Event->freeEventList;
++ Event->freeEventList = record->next;
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record));
++ }
++
++ /* Delete the free mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->freeEventMutex));
++
++ /* Free all pending queues. */
++ while (Event->queueHead != gcvNULL)
++ {
++ /* Get the current queue. */
++ queue = Event->queueHead;
++
++ /* Free all pending events. */
++ while (queue->head != gcvNULL)
++ {
++ record = queue->head;
++ queue->head = record->next;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_WARNING, gcvZONE_EVENT,
++ gcmSIZEOF(record) + gcmSIZEOF(queue->source),
++ "Event record 0x%x is still pending for %d.",
++ record, queue->source
++ );
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record));
++ }
++
++ /* Remove the top queue from the list. */
++ if (Event->queueHead == Event->queueTail)
++ {
++ Event->queueHead =
++ Event->queueTail = gcvNULL;
++ }
++ else
++ {
++ Event->queueHead = Event->queueHead->next;
++ }
++
++ /* Free the queue. */
++ gcmkVERIFY_OK(gckEVENT_FreeQueue(Event, queue));
++ }
++
++ /* Delete the list mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventListMutex));
++
++ /* Delete the atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->freeAtom));
++
++#if gcdSMP
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->pending));
++#endif
++
++ /* Mark the gckEVENT object as unknown. */
++ Event->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckEVENT object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, Event));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_GetEvent
++**
++** Reserve the next available hardware event.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL Wait
++** Set to gcvTRUE to force the function to wait if no events are
++** immediately available.
++**
++** gceKERNEL_WHERE Source
++** Source of the event.
++**
++** OUTPUT:
++**
++** gctUINT8 * EventID
++** Reserved event ID.
++*/
++static gceSTATUS
++gckEVENT_GetEvent(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ OUT gctUINT8 * EventID,
++ IN gcsEVENT_PTR Head,
++ IN gceKERNEL_WHERE Source
++ )
++{
++ gctINT i, id;
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctINT32 free;
++
++#if gcdGPU_TIMEOUT
++ gctUINT32 timer = 0;
++#endif
++
++ gcmkHEADER_ARG("Event=0x%x Head=%p Source=%d", Event, Head, Source);
++
++ while (gcvTRUE)
++ {
++ /* Grab the queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Walk through all events. */
++ id = Event->lastID;
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ gctINT nextID = gckMATH_ModuloInt((id + 1),
++ gcmCOUNTOF(Event->queues));
++
++ if (Event->queues[id].head == gcvNULL)
++ {
++ *EventID = (gctUINT8) id;
++
++ Event->lastID = (gctUINT8) nextID;
++
++ /* Save time stamp of event. */
++ Event->queues[id].stamp = ++(Event->stamp);
++ Event->queues[id].head = Head;
++ Event->queues[id].source = Source;
++
++ gcmkONERROR(gckOS_AtomDecrement(Event->os,
++ Event->freeAtom,
++ &free));
++#if gcdDYNAMIC_SPEED
++ if (free <= gcdDYNAMIC_EVENT_THRESHOLD)
++ {
++ gcmkONERROR(gckOS_BroadcastHurry(
++ Event->os,
++ Event->kernel->hardware,
++ gcdDYNAMIC_EVENT_THRESHOLD - free));
++ }
++#endif
++
++ /* Release the queue mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os,
++ Event->eventQueueMutex));
++
++ /* Success. */
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(id),
++ "Using id=%d",
++ id
++ );
++
++ gcmkFOOTER_ARG("*EventID=%u", *EventID);
++ return gcvSTATUS_OK;
++ }
++
++ id = nextID;
++ }
++
++#if gcdDYNAMIC_SPEED
++ /* No free events, speed up the GPU right now! */
++ gcmkONERROR(gckOS_BroadcastHurry(Event->os,
++ Event->kernel->hardware,
++ gcdDYNAMIC_EVENT_THRESHOLD));
++#endif
++
++ /* Release the queue mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Fail if wait is not requested. */
++ if (!Wait)
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Delay a while. */
++ gcmkONERROR(gckOS_Delay(Event->os, 1));
++
++#if gcdGPU_TIMEOUT
++ /* Increment the wait timer. */
++ timer += 1;
++
++ if (timer == gcdGPU_TIMEOUT)
++ {
++ /* Try to call any outstanding events. */
++ gcmkONERROR(gckHARDWARE_Interrupt(Event->kernel->hardware,
++ gcvTRUE));
++ }
++ else if (timer > gcdGPU_TIMEOUT)
++ {
++ gcmkTRACE_N(
++ gcvLEVEL_ERROR,
++ gcmSIZEOF(gctCONST_STRING) + gcmSIZEOF(gctINT),
++ "%s(%d): no available events\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Bail out. */
++ gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING);
++ }
++#endif
++ }
++
++OnError:
++ if (acquired)
++ {
++ /* Release the queue mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_AllocateRecord
++**
++** Allocate a record for the new event.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL AllocateAllowed
++** State for allocation if out of free events.
++**
++** OUTPUT:
++**
++** gcsEVENT_PTR * Record
++** Allocated event record.
++*/
++gceSTATUS
++gckEVENT_AllocateRecord(
++ IN gckEVENT Event,
++ IN gctBOOL AllocateAllowed,
++ OUT gcsEVENT_PTR * Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctINT i;
++ gcsEVENT_PTR record;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Event=0x%x AllocateAllowed=%d", Event, AllocateAllowed);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->freeEventMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Test if we are below the allocation threshold. */
++ if ( (AllocateAllowed && (Event->freeEventCount < gcdEVENT_MIN_THRESHOLD)) ||
++ (Event->freeEventCount == 0) )
++ {
++ /* Allocate a bunch of records. */
++ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1)
++ {
++ /* Allocate an event record. */
++ gcmkONERROR(gckOS_Allocate(Event->os,
++ gcmSIZEOF(gcsEVENT),
++ &pointer));
++
++ record = pointer;
++
++ /* Push it on the free list. */
++ record->next = Event->freeEventList;
++ Event->freeEventList = record;
++ Event->freeEventCount += 1;
++ }
++ }
++
++ *Record = Event->freeEventList;
++ Event->freeEventList = Event->freeEventList->next;
++ Event->freeEventCount -= 1;
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Record=0x%x", gcmOPT_POINTER(Record));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_AddList
++**
++** Add a new event to the list of events.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsHAL_INTERFACE_PTR Interface
++** Pointer to the interface for the event to be added.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** gctBOOL AllocateAllowed
++** State for allocation if out of free events.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_AddList(
++ IN gckEVENT Event,
++ IN gcsHAL_INTERFACE_PTR Interface,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctBOOL AllocateAllowed,
++ IN gctBOOL FromKernel
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsEVENT_PTR record = gcvNULL;
++ gcsEVENT_QUEUE_PTR queue;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Interface=0x%x",
++ Event, Interface);
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, _GC_OBJ_ZONE,
++ "FromWhere=%d AllocateAllowed=%d",
++ FromWhere, AllocateAllowed);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ /* Verify the event command. */
++ gcmkASSERT
++ ( (Interface->command == gcvHAL_FREE_NON_PAGED_MEMORY)
++ || (Interface->command == gcvHAL_FREE_CONTIGUOUS_MEMORY)
++ || (Interface->command == gcvHAL_FREE_VIDEO_MEMORY)
++ || (Interface->command == gcvHAL_WRITE_DATA)
++ || (Interface->command == gcvHAL_UNLOCK_VIDEO_MEMORY)
++ || (Interface->command == gcvHAL_SIGNAL)
++ || (Interface->command == gcvHAL_UNMAP_USER_MEMORY)
++ || (Interface->command == gcvHAL_TIMESTAMP)
++ || (Interface->command == gcvHAL_COMMIT_DONE)
++ || (Interface->command == gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER)
++ || (Interface->command == gcvHAL_SYNC_POINT)
++ );
++
++ /* Validate the source. */
++ if ((FromWhere != gcvKERNEL_COMMAND) && (FromWhere != gcvKERNEL_PIXEL))
++ {
++ /* Invalid argument. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Allocate a free record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, AllocateAllowed, &record));
++
++ /* Termninate the record. */
++ record->next = gcvNULL;
++
++ /* Record the committer. */
++ record->fromKernel = FromKernel;
++
++ /* Copy the event interface into the record. */
++ gckOS_MemCopy(&record->info, Interface, gcmSIZEOF(record->info));
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&record->processID));
++
++#ifdef __QNXNTO__
++ record->kernel = Event->kernel;
++#endif
++
++ gcmkONERROR(__RemoveRecordFromProcessDB(Event, record));
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->eventListMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Do we need to allocate a new queue? */
++ if ((Event->queueTail == gcvNULL) || (Event->queueTail->source < FromWhere))
++ {
++ /* Allocate a new queue. */
++ gcmkONERROR(gckEVENT_AllocateQueue(Event, &queue));
++
++ /* Initialize the queue. */
++ queue->source = FromWhere;
++ queue->head = gcvNULL;
++ queue->next = gcvNULL;
++
++ /* Attach it to the list of allocated queues. */
++ if (Event->queueTail == gcvNULL)
++ {
++ Event->queueHead =
++ Event->queueTail = queue;
++ }
++ else
++ {
++ Event->queueTail->next = queue;
++ Event->queueTail = queue;
++ }
++ }
++ else
++ {
++ queue = Event->queueTail;
++ }
++
++ /* Attach the record to the queue. */
++ if (queue->head == gcvNULL)
++ {
++ queue->head = record;
++ queue->tail = record;
++ }
++ else
++ {
++ queue->tail->next = record;
++ queue->tail = record;
++ }
++
++ /* Unmap user space logical address.
++ * Linux kernel does not support unmap the memory of other process any more since 3.5.
++ * Let's unmap memory of self process before submit the event to gpu.
++ * */
++ switch(Interface->command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkONERROR(gckOS_UnmapUserLogical(
++ Event->os,
++ gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical),
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++ break;
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkONERROR(gckOS_UnmapUserLogical(
++ Event->os,
++ gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical)));
++ break;
++ default:
++ break;
++ }
++
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ }
++
++ if (record != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Unlock
++**
++** Schedule an event to unlock virtual memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union that specifies the virtual memory
++** to unlock.
++**
++** gceSURF_TYPE Type
++** Type of surface to unlock.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Unlock(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gceSURF_TYPE Type
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d Node=0x%x Type=%d",
++ Event, FromWhere, Node, Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Mark the event as an unlock. */
++ iface.command = gcvHAL_UNLOCK_VIDEO_MEMORY;
++ iface.u.UnlockVideoMemory.node = gcmPTR_TO_UINT64(Node);
++ iface.u.UnlockVideoMemory.type = Type;
++ iface.u.UnlockVideoMemory.asynchroneous = 0;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeVideoMemory
++**
++** Schedule an event to free video memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcuVIDMEM_NODE_PTR VideoMemory
++** Pointer to a gcuVIDMEM_NODE object to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_FreeVideoMemory(
++ IN gckEVENT Event,
++ IN gcuVIDMEM_NODE_PTR VideoMemory,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x VideoMemory=0x%x FromWhere=%d",
++ Event, VideoMemory, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(VideoMemory != gcvNULL);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_VIDEO_MEMORY;
++ iface.u.FreeVideoMemory.node = gcmPTR_TO_UINT64(VideoMemory);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeNonPagedMemory
++**
++** Schedule an event to free non-paged memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIZE_T Bytes
++** Number of bytes of non-paged memory to free.
++**
++** gctPHYS_ADDR Physical
++** Physical address of non-paged memory to free.
++**
++** gctPOINTER Logical
++** Logical address of non-paged memory to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++*/
++gceSTATUS
++gckEVENT_FreeNonPagedMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_NON_PAGED_MEMORY;
++ iface.u.FreeNonPagedMemory.bytes = Bytes;
++ iface.u.FreeNonPagedMemory.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeNonPagedMemory.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckEVENT_DestroyVirtualCommandBuffer(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER;
++ iface.u.FreeVirtualCommandBuffer.bytes = Bytes;
++ iface.u.FreeVirtualCommandBuffer.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeContigiuousMemory
++**
++** Schedule an event to free contiguous memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIZE_T Bytes
++** Number of bytes of contiguous memory to free.
++**
++** gctPHYS_ADDR Physical
++** Physical address of contiguous memory to free.
++**
++** gctPOINTER Logical
++** Logical address of contiguous memory to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++*/
++gceSTATUS
++gckEVENT_FreeContiguousMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_CONTIGUOUS_MEMORY;
++ iface.u.FreeContiguousMemory.bytes = Bytes;
++ iface.u.FreeContiguousMemory.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeContiguousMemory.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Signal
++**
++** Schedule an event to trigger a signal.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIGNAL Signal
++** Pointer to the signal to trigger.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Signal(
++ IN gckEVENT Event,
++ IN gctSIGNAL Signal,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x Signal=0x%x FromWhere=%d",
++ Event, Signal, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ /* Mark the event as a signal. */
++ iface.command = gcvHAL_SIGNAL;
++ iface.u.Signal.signal = gcmPTR_TO_UINT64(Signal);
++#ifdef __QNXNTO__
++ iface.u.Signal.coid = 0;
++ iface.u.Signal.rcvid = 0;
++#endif
++ iface.u.Signal.auxSignal = 0;
++ iface.u.Signal.process = 0;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_CommitDone
++**
++** Schedule an event to wake up work thread when commit is done by GPU.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_CommitDone(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d", Event, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ iface.command = gcvHAL_COMMIT_DONE;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++/*******************************************************************************
++**
++** gckEVENT_Submit
++**
++** Submit the current event queue to the GPU.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL Wait
++** Submit requires one vacant event; if Wait is set to not zero,
++** and there are no vacant events at this time, the function will
++** wait until an event becomes vacant so that submission of the
++** queue is successful.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++ gctUINT8 id = 0xFF;
++ gcsEVENT_QUEUE_PTR queue;
++ gctBOOL acquired = gcvFALSE;
++ gckCOMMAND command = gcvNULL;
++ gctBOOL commitEntered = gcvFALSE;
++#if !gcdNULL_DRIVER
++ gctSIZE_T bytes;
++ gctPOINTER buffer;
++#endif
++
++ gcmkHEADER_ARG("Event=0x%x Wait=%d", Event, Wait);
++
++ /* Get gckCOMMAND object. */
++ command = Event->kernel->command;
++
++ /* Are there event queues? */
++ if (Event->queueHead != gcvNULL)
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, FromPower));
++ commitEntered = gcvTRUE;
++
++ /* Process all queues. */
++ while (Event->queueHead != gcvNULL)
++ {
++ /* Acquire the list mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventListMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Get the current queue. */
++ queue = Event->queueHead;
++
++ /* Allocate an event ID. */
++ gcmkONERROR(gckEVENT_GetEvent(Event, Wait, &id, queue->head, queue->source));
++
++ /* Copy event list to event ID queue. */
++ Event->queues[id].head = queue->head;
++
++ /* Remove the top queue from the list. */
++ if (Event->queueHead == Event->queueTail)
++ {
++ Event->queueHead = gcvNULL;
++ Event->queueTail = gcvNULL;
++ }
++ else
++ {
++ Event->queueHead = Event->queueHead->next;
++ }
++
++ /* Free the queue. */
++ gcmkONERROR(gckEVENT_FreeQueue(Event, queue));
++
++ /* Release the list mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ acquired = gcvFALSE;
++
++#if gcdNULL_DRIVER
++ /* Notify immediately on infinite hardware. */
++ gcmkONERROR(gckEVENT_Interrupt(Event, 1 << id));
++
++ gcmkONERROR(gckEVENT_Notify(Event, 0));
++#else
++ /* Get the size of the hardware event. */
++ gcmkONERROR(gckHARDWARE_Event(Event->kernel->hardware,
++ gcvNULL,
++ id,
++ Event->queues[id].source,
++ &bytes));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command,
++ bytes,
++ &buffer,
++ &bytes));
++
++ /* Set the hardware event in the command queue. */
++ gcmkONERROR(gckHARDWARE_Event(Event->kernel->hardware,
++ buffer,
++ id,
++ Event->queues[id].source,
++ &bytes));
++
++ /* Execute the hardware event. */
++ gcmkONERROR(gckCOMMAND_Execute(command, bytes));
++#endif
++ }
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, FromPower));
++ commitEntered = gcvFALSE;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, FromPower));
++ }
++
++ if (acquired)
++ {
++ /* Need to unroll the mutex acquire. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ }
++
++ if (id != 0xFF)
++ {
++ /* Need to unroll the event allocation. */
++ Event->queues[id].head = gcvNULL;
++ }
++
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Broadcast GPU stuck. */
++ status = gckOS_Broadcast(Event->os,
++ Event->kernel->hardware,
++ gcvBROADCAST_GPU_STUCK);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Commit
++**
++** Commit an event queue from the user.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsQUEUE_PTR Queue
++** User event queue.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue
++ )
++{
++ gceSTATUS status;
++ gcsQUEUE_PTR record = gcvNULL, next;
++ gctUINT32 processID;
++ gctBOOL needCopy = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Queue=0x%x", Event, Queue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Get the current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Query if we need to copy the client data. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Event->os, processID, &needCopy));
++
++ /* Loop while there are records in the queue. */
++ while (Queue != gcvNULL)
++ {
++ gcsQUEUE queue;
++
++ if (needCopy)
++ {
++ /* Point to stack record. */
++ record = &queue;
++
++ /* Copy the data from the client. */
++ gcmkONERROR(gckOS_CopyFromUserData(Event->os,
++ record,
++ Queue,
++ gcmSIZEOF(gcsQUEUE)));
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Map record into kernel memory. */
++ gcmkONERROR(gckOS_MapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ &pointer));
++
++ record = pointer;
++ }
++
++ /* Append event record to event queue. */
++ gcmkONERROR(
++ gckEVENT_AddList(Event, &record->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE));
++
++ /* Next record in the queue. */
++ next = gcmUINT64_TO_PTR(record->next);
++
++ if (!needCopy)
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(
++ gckOS_UnmapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) record));
++ record = gcvNULL;
++ }
++
++ Queue = next;
++ }
++
++ /* Submit the event list. */
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE));
++
++ /* Success */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if ((record != gcvNULL) && !needCopy)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Compose
++**
++** Schedule a composition event and start a composition.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsHAL_COMPOSE_PTR Info
++** Pointer to the composition structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Compose(
++ IN gckEVENT Event,
++ IN gcsHAL_COMPOSE_PTR Info
++ )
++{
++ gceSTATUS status;
++ gcsEVENT_PTR headRecord;
++ gcsEVENT_PTR tailRecord;
++ gcsEVENT_PTR tempRecord;
++ gctUINT8 id = 0xFF;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Event=0x%x Info=0x%x", Event, Info);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ headRecord = tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->process;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->signal;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++
++ /* Allocate another record for user signal #1. */
++ if (gcmUINT64_TO_PTR(Info->userSignal1) != gcvNULL)
++ {
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ tailRecord->next = tempRecord;
++ tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->userProcess;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->userSignal1;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++ }
++
++ /* Allocate another record for user signal #2. */
++ if (gcmUINT64_TO_PTR(Info->userSignal2) != gcvNULL)
++ {
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ tailRecord->next = tempRecord;
++ tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->userProcess;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->userSignal2;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++ }
++
++ /* Allocate an event ID. */
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, headRecord, gcvKERNEL_PIXEL));
++
++ /* Start composition. */
++ gcmkONERROR(gckHARDWARE_Compose(
++ Event->kernel->hardware, processID,
++ gcmUINT64_TO_PTR(Info->physical), gcmUINT64_TO_PTR(Info->logical), Info->offset, Info->size, id
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Interrupt
++**
++** Called by the interrupt service routine to store the triggered interrupt
++** mask to be later processed by gckEVENT_Notify.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 Data
++** Mask for the 32 interrupts.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Interrupt(
++ IN gckEVENT Event,
++ IN gctUINT32 Data
++ )
++{
++ unsigned long flags;
++ gcmkHEADER_ARG("Event=0x%x Data=0x%x", Event, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Combine current interrupt status with pending flags. */
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ gckOS_AtomSetMask(Event->pending, Data);
++#elif defined(__QNXNTO__)
++ atomic_set(&Event->pending, Data);
++#else
++ Event->pending |= Data;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Notify
++**
++** Process all triggered interrupts.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Notify(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctINT i;
++ gcsEVENT_QUEUE * queue;
++ gctUINT mask = 0;
++ gctBOOL acquired = gcvFALSE;
++ gcuVIDMEM_NODE_PTR node;
++ gctPOINTER info;
++ gctSIGNAL signal;
++ gctUINT pending;
++ gckKERNEL kernel = Event->kernel;
++#if !gcdSMP
++ gctBOOL suspended = gcvFALSE;
++#endif
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gctINT eventNumber = 0;
++#endif
++ gctINT32 free;
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++ unsigned long flags;
++
++ gcmkHEADER_ARG("Event=0x%x IDs=0x%x", Event, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ gcmDEBUG_ONLY(
++ if (IDs != 0)
++ {
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Queue(%d): stamp=%llu source=%d",
++ i,
++ Event->queues[i].stamp,
++ Event->queues[i].source);
++ }
++ }
++ }
++ );
++
++ for (;;)
++ {
++ gcsEVENT_PTR record;
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ /* Get current interrupts. */
++ gckOS_AtomGet(Event->os, Event->pending, (gctINT32_PTR)&pending);
++#else
++ /* Get current interrupts. */
++ pending = Event->pending;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ if (pending == 0)
++ {
++ /* No more pending interrupts - done. */
++ break;
++ }
++
++ if (pending & 0x80000000)
++ {
++ gckOS_Print("!!!!!!!!!!!!! AXI BUS ERROR !!!!!!!!!!!!!\n");
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_EVENT, "AXI BUS ERROR");
++ pending &= 0x7FFFFFFF;
++ }
++
++ if (pending & 0x40000000)
++ {
++ gckHARDWARE_DumpMMUException(Event->kernel->hardware);
++
++ pending &= 0xBFFFFFFF;
++ }
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(pending),
++ "Pending interrupts 0x%x",
++ pending
++ );
++
++ queue = gcvNULL;
++
++ /* Grab the mutex queue. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmDEBUG_ONLY(
++ if (IDs == 0)
++ {
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Queue(%d): stamp=%llu source=%d",
++ i,
++ Event->queues[i].stamp,
++ Event->queues[i].source);
++ }
++ }
++ }
++ );
++
++ /* Find the oldest pending interrupt. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if ((Event->queues[i].head != gcvNULL)
++ && (pending & (1 << i))
++ )
++ {
++ if ((queue == gcvNULL)
++ || (Event->queues[i].stamp < queue->stamp)
++ )
++ {
++ queue = &Event->queues[i];
++ mask = 1 << i;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ eventNumber = i;
++#endif
++ }
++ }
++ }
++
++ if (queue == gcvNULL)
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(pending),
++ "Interrupts 0x%x are not pending.",
++ pending
++ );
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ /* Mark pending interrupts as handled. */
++ gckOS_AtomClearMask(Event->pending, pending);
++#elif defined(__QNXNTO__)
++ /* Mark pending interrupts as handled. */
++ atomic_clr((gctUINT32_PTR)&Event->pending, pending);
++#else
++ /* Mark pending interrupts as handled. */
++ Event->pending &= ~pending;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++ break;
++ }
++
++ /* Check whether there is a missed interrupt. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if ((Event->queues[i].head != gcvNULL)
++ && (Event->queues[i].stamp < queue->stamp)
++ && (Event->queues[i].source <= queue->source)
++ )
++ {
++ gcmkTRACE_N(
++ gcvLEVEL_ERROR,
++ gcmSIZEOF(i) + gcmSIZEOF(Event->queues[i].stamp),
++ "Event %d lost (stamp %llu)",
++ i, Event->queues[i].stamp
++ );
++
++ /* Use this event instead. */
++ queue = &Event->queues[i];
++ mask = 0;
++ }
++ }
++
++ if (mask != 0)
++ {
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(eventNumber),
++ "Processing interrupt %d",
++ eventNumber
++ );
++#endif
++ }
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ /* Mark pending interrupt as handled. */
++ gckOS_AtomClearMask(Event->pending, mask);
++#elif defined(__QNXNTO__)
++ /* Mark pending interrupt as handled. */
++ atomic_clr(&Event->pending, mask);
++#else
++ /* Mark pending interrupt as handled. */
++ Event->pending &= ~mask;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ /* We are in the notify loop. */
++ Event->inNotify = gcvTRUE;
++
++ /* We are in the notify loop. */
++ Event->inNotify = gcvTRUE;
++
++ /* Grab the event head. */
++ record = queue->head;
++
++ /* Now quickly clear its event list. */
++ queue->head = gcvNULL;
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Increase the number of free events. */
++ gcmkONERROR(gckOS_AtomIncrement(Event->os, Event->freeAtom, &free));
++
++ /* Walk all events for this interrupt. */
++ while (record != gcvNULL)
++ {
++ gcsEVENT_PTR recordNext;
++#ifndef __QNXNTO__
++ gctPOINTER logical;
++#endif
++#if gcdSECURE_USER
++ gctSIZE_T bytes;
++#endif
++
++ /* Grab next record. */
++ recordNext = record->next;
++
++#ifdef __QNXNTO__
++ /* Assign record->processID as the pid for this galcore thread.
++ * Used in OS calls like gckOS_UnlockMemory() which do not take a pid.
++ */
++ drv_thread_specific_key_assign(record->processID, 0, Event->kernel->core);
++#endif
++
++#if gcdSECURE_USER
++ /* Get the cache that belongs to this process. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Event->kernel,
++ record->processID,
++ &cache));
++#endif
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.command),
++ "Processing event type: %d",
++ record->info.command
++ );
++
++ switch (record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_NON_PAGED_MEMORY: 0x%x",
++ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical));
++
++ /* Free non-paged memory. */
++ status = gckOS_FreeNonPagedMemory(
++ Event->os,
++ (gctSIZE_T) record->info.u.FreeNonPagedMemory.bytes,
++ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeNonPagedMemory.logical));
++
++ if (gcmIS_SUCCESS(status))
++ {
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(record->record.u.FreeNonPagedMemory.logical),
++ (gctSIZE_T) record->record.u.FreeNonPagedMemory.bytes));
++#endif
++ }
++ gcmRELEASE_NAME(record->info.u.FreeNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_CONTIGUOUS_MEMORY: 0x%x",
++ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical));
++
++ /* Unmap the user memory. */
++ status = gckOS_FreeContiguous(
++ Event->os,
++ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeContiguousMemory.logical),
++ (gctSIZE_T) record->info.u.FreeContiguousMemory.bytes);
++
++ if (gcmIS_SUCCESS(status))
++ {
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(record->record.u.FreeContiguousMemory.logical),
++ (gctSIZE_T) record->record.u.FreeContiguousMemory.bytes));
++#endif
++ }
++ gcmRELEASE_NAME(record->info.u.FreeContiguousMemory.physical);
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(record->info.u.FreeVideoMemory.node);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_VIDEO_MEMORY: 0x%x",
++ node);
++#ifdef __QNXNTO__
++#if gcdUSE_VIDMEM_PER_PID
++ /* Check if the VidMem object still exists. */
++ if (gckKERNEL_GetVideoMemoryPoolPid(record->kernel,
++ gcvPOOL_SYSTEM,
++ record->processID,
++ gcvNULL) == gcvSTATUS_NOT_FOUND)
++ {
++ /*printf("Vidmem not found for process:%d\n", queue->processID);*/
++ status = gcvSTATUS_OK;
++ break;
++ }
++#else
++ if ((node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ && (node->VidMem.logical != gcvNULL)
++ )
++ {
++ gcmkERR_BREAK(
++ gckKERNEL_UnmapVideoMemory(record->kernel,
++ node->VidMem.logical,
++ record->processID,
++ node->VidMem.bytes));
++ node->VidMem.logical = gcvNULL;
++ }
++#endif
++#endif
++
++ /* Free video memory. */
++ status =
++ gckVIDMEM_Free(node);
++
++ break;
++
++ case gcvHAL_WRITE_DATA:
++#ifndef __QNXNTO__
++ /* Convert physical into logical address. */
++ gcmkERR_BREAK(
++ gckOS_MapPhysical(Event->os,
++ record->info.u.WriteData.address,
++ gcmSIZEOF(gctUINT32),
++ &logical));
++
++ /* Write data. */
++ gcmkERR_BREAK(
++ gckOS_WriteMemory(Event->os,
++ logical,
++ record->info.u.WriteData.data));
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(
++ gckOS_UnmapPhysical(Event->os,
++ logical,
++ gcmSIZEOF(gctUINT32)));
++#else
++ /* Write data. */
++ gcmkERR_BREAK(
++ gckOS_WriteMemory(Event->os,
++ (gctPOINTER)
++ record->info.u.WriteData.address,
++ record->info.u.WriteData.data));
++#endif
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(record->info.u.UnlockVideoMemory.node);
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_UNLOCK_VIDEO_MEMORY: 0x%x",
++ node);
++
++ /* Save node information before it disappears. */
++#if gcdSECURE_USER
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ logical = gcvNULL;
++ bytes = 0;
++ }
++ else
++ {
++ logical = node->Virtual.logical;
++ bytes = node->Virtual.bytes;
++ }
++#endif
++
++ /* Unlock. */
++ status = gckVIDMEM_Unlock(
++ Event->kernel,
++ node,
++ record->info.u.UnlockVideoMemory.type,
++ gcvNULL);
++
++#if gcdSECURE_USER
++ if (gcmIS_SUCCESS(status) && (logical != gcvNULL))
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ logical,
++ bytes));
++ }
++#endif
++ break;
++
++ case gcvHAL_SIGNAL:
++ signal = gcmUINT64_TO_PTR(record->info.u.Signal.signal);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_SIGNAL: 0x%x",
++ signal);
++
++#ifdef __QNXNTO__
++ if ((record->info.u.Signal.coid == 0)
++ && (record->info.u.Signal.rcvid == 0)
++ )
++ {
++ /* Kernel signal. */
++ gcmkERR_BREAK(
++ gckOS_Signal(Event->os,
++ signal,
++ gcvTRUE));
++ }
++ else
++ {
++ /* User signal. */
++ gcmkERR_BREAK(
++ gckOS_UserSignal(Event->os,
++ signal,
++ record->info.u.Signal.rcvid,
++ record->info.u.Signal.coid));
++ }
++#else
++ /* Set signal. */
++ if (gcmUINT64_TO_PTR(record->info.u.Signal.process) == gcvNULL)
++ {
++ /* Kernel signal. */
++ gcmkERR_BREAK(
++ gckOS_Signal(Event->os,
++ signal,
++ gcvTRUE));
++ }
++ else
++ {
++ /* User signal. */
++ gcmkERR_BREAK(
++ gckOS_UserSignal(Event->os,
++ signal,
++ gcmUINT64_TO_PTR(record->info.u.Signal.process)));
++ }
++
++ gcmkASSERT(record->info.u.Signal.auxSignal == 0);
++#endif
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ info = gcmNAME_TO_PTR(record->info.u.UnmapUserMemory.info);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_UNMAP_USER_MEMORY: 0x%x",
++ info);
++
++ /* Unmap the user memory. */
++ status = gckOS_UnmapUserMemory(
++ Event->os,
++ Event->kernel->core,
++ gcmUINT64_TO_PTR(record->info.u.UnmapUserMemory.memory),
++ (gctSIZE_T) record->info.u.UnmapUserMemory.size,
++ info,
++ record->info.u.UnmapUserMemory.address);
++
++#if gcdSECURE_USER
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(record->info.u.UnmapUserMemory.memory),
++ (gctSIZE_T) record->info.u.UnmapUserMemory.size));
++ }
++#endif
++ gcmRELEASE_NAME(record->info.u.UnmapUserMemory.info);
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_TIMESTAMP: %d %d",
++ record->info.u.TimeStamp.timer,
++ record->info.u.TimeStamp.request);
++
++ /* Process the timestamp. */
++ switch (record->info.u.TimeStamp.request)
++ {
++ case 0:
++ status = gckOS_GetTime(&Event->kernel->timers[
++ record->info.u.TimeStamp.timer].
++ stopTime);
++ break;
++
++ case 1:
++ status = gckOS_GetTime(&Event->kernel->timers[
++ record->info.u.TimeStamp.timer].
++ startTime);
++ break;
++
++ default:
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.u.TimeStamp.request),
++ "Invalid timestamp request: %d",
++ record->info.u.TimeStamp.request
++ );
++
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ break;
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkVERIFY_OK(
++ gckKERNEL_DestroyVirtualCommandBuffer(Event->kernel,
++ (gctSIZE_T) record->info.u.FreeVirtualCommandBuffer.bytes,
++ gcmNAME_TO_PTR(record->info.u.FreeVirtualCommandBuffer.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeVirtualCommandBuffer.logical)
++ ));
++ gcmRELEASE_NAME(record->info.u.FreeVirtualCommandBuffer.physical);
++ break;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvHAL_SYNC_POINT:
++ {
++ gctSYNC_POINT syncPoint;
++
++ syncPoint = gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint);
++ status = gckOS_SignalSyncPoint(Event->os, syncPoint);
++ }
++ break;
++#endif
++
++ case gcvHAL_COMMIT_DONE:
++ break;
++
++ default:
++ /* Invalid argument. */
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.command),
++ "Unknown event type: %d",
++ record->info.command
++ );
++
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ /* Make sure there are no errors generated. */
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_WARNING, gcvZONE_EVENT,
++ gcmSIZEOF(status),
++ "Event produced status: %d(%s)",
++ status, gckOS_DebugStatus2Name(status));
++ }
++
++ /* Free the event. */
++ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record));
++
++ /* Advance to next record. */
++ record = recordNext;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Handled interrupt 0x%x", mask);
++ }
++
++ if (IDs == 0)
++ {
++ gcmkONERROR(_TryToIdleGPU(Event));
++ }
++
++ /* We are out the notify loop. */
++ Event->inNotify = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++#if !gcdSMP
++ if (suspended)
++ {
++ /* Resume interrupts. */
++ gcmkVERIFY_OK(gckOS_ResumeInterruptEx(Event->os, Event->kernel->core));
++ }
++#endif
++
++ /* We are out the notify loop. */
++ Event->inNotify = gcvFALSE;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckEVENT_FreeProcess
++**
++** Free all events owned by a particular process ID.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 ProcessID
++** Process ID of the process to be freed up.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_FreeProcess(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID
++ )
++{
++ gctSIZE_T i;
++ gctBOOL acquired = gcvFALSE;
++ gcsEVENT_PTR record, next;
++ gceSTATUS status;
++ gcsEVENT_PTR deleteHead, deleteTail;
++
++ gcmkHEADER_ARG("Event=0x%x ProcessID=%d", Event, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Walk through all queues. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ /* Grab the event queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Grab the mutex head. */
++ record = Event->queues[i].head;
++ Event->queues[i].head = gcvNULL;
++ Event->queues[i].tail = gcvNULL;
++ deleteHead = gcvNULL;
++ deleteTail = gcvNULL;
++
++ while (record != gcvNULL)
++ {
++ next = record->next;
++ if (record->processID == ProcessID)
++ {
++ if (deleteHead == gcvNULL)
++ {
++ deleteHead = record;
++ }
++ else
++ {
++ deleteTail->next = record;
++ }
++
++ deleteTail = record;
++ }
++ else
++ {
++ if (Event->queues[i].head == gcvNULL)
++ {
++ Event->queues[i].head = record;
++ }
++ else
++ {
++ Event->queues[i].tail->next = record;
++ }
++
++ Event->queues[i].tail = record;
++ }
++
++ record->next = gcvNULL;
++ record = next;
++ }
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Loop through the entire list of events. */
++ for (record = deleteHead; record != gcvNULL; record = next)
++ {
++ /* Get the next event record. */
++ next = record->next;
++
++ /* Free the event record. */
++ gcmkONERROR(gckEVENT_FreeRecord(Event, record));
++ }
++ }
++ }
++
++ gcmkONERROR(_TryToIdleGPU(Event));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release the event queue mutex. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckEVENT_Stop
++**
++** Stop the hardware using the End event mechanism.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIGNAL Signal
++** Pointer to the signal to trigger.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Stop(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Logical,
++ IN gctSIGNAL Signal,
++ IN OUT gctSIZE_T * waitSize
++ )
++{
++ gceSTATUS status;
++ /* gctSIZE_T waitSize;*/
++ gcsEVENT_PTR record;
++ gctUINT8 id = 0xFF;
++
++ gcmkHEADER_ARG("Event=0x%x ProcessID=%u Handle=0x%x Logical=0x%x "
++ "Signal=0x%x",
++ Event, ProcessID, Handle, Logical, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Submit the current event queue. */
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE));
++
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &record));
++
++ /* Initialize the record. */
++ record->next = gcvNULL;
++ record->processID = ProcessID;
++ record->info.command = gcvHAL_SIGNAL;
++ record->info.u.Signal.signal = gcmPTR_TO_UINT64(Signal);
++#ifdef __QNXNTO__
++ record->info.u.Signal.coid = 0;
++ record->info.u.Signal.rcvid = 0;
++#endif
++ record->info.u.Signal.auxSignal = 0;
++ record->info.u.Signal.process = 0;
++
++
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, record, gcvKERNEL_PIXEL));
++
++ /* Replace last WAIT with END. */
++ gcmkONERROR(gckHARDWARE_End(
++ Event->kernel->hardware, Logical, waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the END. */
++ gcmkONERROR(gckOS_CacheClean(
++ Event->os,
++ ProcessID,
++ gcvNULL,
++ Handle,
++ Logical,
++ *waitSize
++ ));
++#endif
++
++ /* Wait for the signal. */
++ gcmkONERROR(gckOS_WaitSignal(Event->os, Signal, gcvINFINITE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_PrintRecord(
++ gcsEVENT_PTR record
++ )
++{
++ switch (record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_NON_PAGED_MEMORY");
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_CONTIGUOUS_MEMORY");
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_VIDEO_MEMORY");
++ break;
++
++ case gcvHAL_WRITE_DATA:
++ gcmkPRINT(" gcvHAL_WRITE_DATA");
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkPRINT(" gcvHAL_UNLOCK_VIDEO_MEMORY");
++ break;
++
++ case gcvHAL_SIGNAL:
++ gcmkPRINT(" gcvHAL_SIGNAL process=%d signal=0x%x",
++ record->info.u.Signal.process,
++ record->info.u.Signal.signal);
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ gcmkPRINT(" gcvHAL_UNMAP_USER_MEMORY");
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ gcmkPRINT(" gcvHAL_TIMESTAMP");
++ break;
++
++ case gcvHAL_COMMIT_DONE:
++ gcmkPRINT(" gcvHAL_COMMIT_DONE");
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkPRINT(" gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER logical=0x%08x",
++ record->info.u.FreeVirtualCommandBuffer.logical);
++ break;
++
++ default:
++ gcmkPRINT(" Illegal Event %d", record->info.command);
++ break;
++ }
++}
++
++/*******************************************************************************
++** gckEVENT_Dump
++**
++** Dump record in event queue when stuck happens.
++** No protection for the event queue.
++**/
++gceSTATUS
++gckEVENT_Dump(
++ IN gckEVENT Event
++ )
++{
++ gcsEVENT_QUEUE_PTR queueHead = Event->queueHead;
++ gcsEVENT_QUEUE_PTR queue;
++ gcsEVENT_PTR record = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** EVENT STATE DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++
++ gcmkPRINT(" Unsumbitted Event:");
++ while(queueHead)
++ {
++ queue = queueHead;
++ record = queueHead->head;
++
++ gcmkPRINT(" [%x]:", queue);
++ while(record)
++ {
++ _PrintRecord(record);
++ record = record->next;
++ }
++
++ if (queueHead == Event->queueTail)
++ {
++ queueHead = gcvNULL;
++ }
++ else
++ {
++ queueHead = queueHead->next;
++ }
++ }
++
++ gcmkPRINT(" Untriggered Event:");
++ for (i = 0; i < 30; i++)
++ {
++ queue = &Event->queues[i];
++ record = queue->head;
++
++ gcmkPRINT(" [%d]:", i);
++ while(record)
++ {
++ _PrintRecord(record);
++ record = record->next;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS gckEVENT_WaitEmpty(gckEVENT Event)
++{
++ gctBOOL isEmpty;
++
++ while (Event->inNotify || (gcmIS_SUCCESS(gckEVENT_IsEmpty(Event, &isEmpty)) && !isEmpty)) ;
++
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h 2014-05-15 20:33:58.594018160 +0200
+@@ -0,0 +1,999 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_h_
++#define __gc_hal_kernel_h_
++
++#include <linux/spinlock.h>
++
++#include "gc_hal.h"
++#include "gc_hal_kernel_hardware.h"
++#include "gc_hal_driver.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++/*******************************************************************************
++***** New MMU Defination *******************************************************/
++#define gcdMMU_MTLB_SHIFT 22
++#define gcdMMU_STLB_4K_SHIFT 12
++#define gcdMMU_STLB_64K_SHIFT 16
++
++#define gcdMMU_MTLB_BITS (32 - gcdMMU_MTLB_SHIFT)
++#define gcdMMU_PAGE_4K_BITS gcdMMU_STLB_4K_SHIFT
++#define gcdMMU_STLB_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_4K_BITS)
++#define gcdMMU_PAGE_64K_BITS gcdMMU_STLB_64K_SHIFT
++#define gcdMMU_STLB_64K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_64K_BITS)
++
++#define gcdMMU_MTLB_ENTRY_NUM (1 << gcdMMU_MTLB_BITS)
++#define gcdMMU_MTLB_SIZE (gcdMMU_MTLB_ENTRY_NUM << 2)
++#define gcdMMU_STLB_4K_ENTRY_NUM (1 << gcdMMU_STLB_4K_BITS)
++#define gcdMMU_STLB_4K_SIZE (gcdMMU_STLB_4K_ENTRY_NUM << 2)
++#define gcdMMU_PAGE_4K_SIZE (1 << gcdMMU_STLB_4K_SHIFT)
++#define gcdMMU_STLB_64K_ENTRY_NUM (1 << gcdMMU_STLB_64K_BITS)
++#define gcdMMU_STLB_64K_SIZE (gcdMMU_STLB_64K_ENTRY_NUM << 2)
++#define gcdMMU_PAGE_64K_SIZE (1 << gcdMMU_STLB_64K_SHIFT)
++
++#define gcdMMU_MTLB_MASK (~((1U << gcdMMU_MTLB_SHIFT)-1))
++#define gcdMMU_STLB_4K_MASK ((~0U << gcdMMU_STLB_4K_SHIFT) ^ gcdMMU_MTLB_MASK)
++#define gcdMMU_PAGE_4K_MASK (gcdMMU_PAGE_4K_SIZE - 1)
++#define gcdMMU_STLB_64K_MASK ((~((1U << gcdMMU_STLB_64K_SHIFT)-1)) ^ gcdMMU_MTLB_MASK)
++#define gcdMMU_PAGE_64K_MASK (gcdMMU_PAGE_64K_SIZE - 1)
++
++/* Page offset definitions. */
++#define gcdMMU_OFFSET_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_4K_BITS)
++#define gcdMMU_OFFSET_4K_MASK ((1U << gcdMMU_OFFSET_4K_BITS) - 1)
++#define gcdMMU_OFFSET_16K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_16K_BITS)
++#define gcdMMU_OFFSET_16K_MASK ((1U << gcdMMU_OFFSET_16K_BITS) - 1)
++
++/*******************************************************************************
++***** Process Secure Cache ****************************************************/
++
++#define gcdSECURE_CACHE_LRU 1
++#define gcdSECURE_CACHE_LINEAR 2
++#define gcdSECURE_CACHE_HASH 3
++#define gcdSECURE_CACHE_TABLE 4
++
++typedef struct _gcskLOGICAL_CACHE * gcskLOGICAL_CACHE_PTR;
++typedef struct _gcskLOGICAL_CACHE gcskLOGICAL_CACHE;
++struct _gcskLOGICAL_CACHE
++{
++ /* Logical address. */
++ gctPOINTER logical;
++
++ /* DMAable address. */
++ gctUINT32 dma;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Pointer to the previous and next hash tables. */
++ gcskLOGICAL_CACHE_PTR nextHash;
++ gcskLOGICAL_CACHE_PTR prevHash;
++#endif
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ /* Pointer to the previous and next slot. */
++ gcskLOGICAL_CACHE_PTR next;
++ gcskLOGICAL_CACHE_PTR prev;
++#endif
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ /* Time stamp. */
++ gctUINT64 stamp;
++#endif
++};
++
++typedef struct _gcskSECURE_CACHE * gcskSECURE_CACHE_PTR;
++typedef struct _gcskSECURE_CACHE
++{
++ /* Cache memory. */
++ gcskLOGICAL_CACHE cache[1 + gcdSECURE_CACHE_SLOTS];
++
++ /* Last known index for LINEAR mode. */
++ gcskLOGICAL_CACHE_PTR cacheIndex;
++
++ /* Current free slot for LINEAR mode. */
++ gctUINT32 cacheFree;
++
++ /* Time stamp for LINEAR mode. */
++ gctUINT64 cacheStamp;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Hash table for HASH mode. */
++ gcskLOGICAL_CACHE hash[256];
++#endif
++}
++gcskSECURE_CACHE;
++
++/*******************************************************************************
++***** Process Database Management *********************************************/
++
++typedef enum _gceDATABASE_TYPE
++{
++ gcvDB_VIDEO_MEMORY = 1, /* Video memory created. */
++ gcvDB_COMMAND_BUFFER, /* Command Buffer. */
++ gcvDB_NON_PAGED, /* Non paged memory. */
++ gcvDB_CONTIGUOUS, /* Contiguous memory. */
++ gcvDB_SIGNAL, /* Signal. */
++ gcvDB_VIDEO_MEMORY_LOCKED, /* Video memory locked. */
++ gcvDB_CONTEXT, /* Context */
++ gcvDB_IDLE, /* GPU idle. */
++ gcvDB_MAP_MEMORY, /* Map memory */
++ gcvDB_SHARED_INFO, /* Private data */
++ gcvDB_MAP_USER_MEMORY, /* Map user memory */
++ gcvDB_SYNC_POINT, /* Sync point. */
++}
++gceDATABASE_TYPE;
++
++typedef struct _gcsDATABASE_RECORD * gcsDATABASE_RECORD_PTR;
++typedef struct _gcsDATABASE_RECORD
++{
++ /* Pointer to kernel. */
++ gckKERNEL kernel;
++
++ /* Pointer to next database record. */
++ gcsDATABASE_RECORD_PTR next;
++
++ /* Type of record. */
++ gceDATABASE_TYPE type;
++
++ /* Data for record. */
++ gctPOINTER data;
++ gctPHYS_ADDR physical;
++ gctSIZE_T bytes;
++}
++gcsDATABASE_RECORD;
++
++typedef struct _gcsDATABASE * gcsDATABASE_PTR;
++typedef struct _gcsDATABASE
++{
++ /* Pointer to next entry is hash list. */
++ gcsDATABASE_PTR next;
++ gctSIZE_T slot;
++
++ /* Process ID. */
++ gctUINT32 processID;
++
++ /* Sizes to query. */
++ gcsDATABASE_COUNTERS vidMem;
++ gcsDATABASE_COUNTERS nonPaged;
++ gcsDATABASE_COUNTERS contiguous;
++ gcsDATABASE_COUNTERS mapUserMemory;
++ gcsDATABASE_COUNTERS mapMemory;
++
++ /* Idle time management. */
++ gctUINT64 lastIdle;
++ gctUINT64 idle;
++
++ /* Pointer to database. */
++ gcsDATABASE_RECORD_PTR list[48];
++
++#if gcdSECURE_USER
++ /* Secure cache. */
++ gcskSECURE_CACHE cache;
++#endif
++
++ gctPOINTER handleDatabase;
++ gctPOINTER handleDatabaseMutex;
++}
++gcsDATABASE;
++
++/* Create a process database that will contain all its allocations. */
++gceSTATUS
++gckKERNEL_CreateProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ );
++
++/* Add a record to the process database. */
++gceSTATUS
++gckKERNEL_AddProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Size
++ );
++
++/* Remove a record to the process database. */
++gceSTATUS
++gckKERNEL_RemoveProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer
++ );
++
++/* Destroy the process database. */
++gceSTATUS
++gckKERNEL_DestroyProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ );
++
++/* Find a record to the process database. */
++gceSTATUS
++gckKERNEL_FindProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 ThreadID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ OUT gcsDATABASE_RECORD_PTR Record
++ );
++
++/* Query the process database. */
++gceSTATUS
++gckKERNEL_QueryProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ IN gceDATABASE_TYPE Type,
++ OUT gcuDATABASE_INFO * Info
++ );
++
++/* Dump the process database. */
++gceSTATUS
++gckKERNEL_DumpProcessDB(
++ IN gckKERNEL Kernel
++ );
++
++/* ID database */
++gceSTATUS
++gckKERNEL_CreateIntegerDatabase(
++ IN gckKERNEL Kernel,
++ OUT gctPOINTER * Database
++ );
++
++gceSTATUS
++gckKERNEL_DestroyIntegerDatabase(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Database
++ );
++
++gceSTATUS
++gckKERNEL_AllocateIntegerId(
++ IN gctPOINTER Database,
++ IN gctPOINTER Pointer,
++ OUT gctUINT32 * Id
++ );
++
++gceSTATUS
++gckKERNEL_FreeIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id
++ );
++
++gceSTATUS
++gckKERNEL_QueryIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * Pointer
++ );
++
++gctUINT32
++gckKERNEL_AllocateNameFromPointer(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Pointer
++ );
++
++gctPOINTER
++gckKERNEL_QueryPointerFromName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ );
++
++gceSTATUS
++gckKERNEL_DeleteName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ );
++
++#if gcdSECURE_USER
++/* Get secure cache from the process database. */
++gceSTATUS
++gckKERNEL_GetProcessDBCache(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcskSECURE_CACHE_PTR * Cache
++ );
++#endif
++
++/*******************************************************************************
++********* Timer Management ****************************************************/
++typedef struct _gcsTIMER * gcsTIMER_PTR;
++typedef struct _gcsTIMER
++{
++ /* Start and Stop time holders. */
++ gctUINT64 startTime;
++ gctUINT64 stopTime;
++}
++gcsTIMER;
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++
++/* gckDB object. */
++struct _gckDB
++{
++ /* Database management. */
++ gcsDATABASE_PTR db[16];
++ gctPOINTER dbMutex;
++ gcsDATABASE_PTR freeDatabase;
++ gcsDATABASE_RECORD_PTR freeRecord;
++ gcsDATABASE_PTR lastDatabase;
++ gctUINT32 lastProcessID;
++ gctUINT64 lastIdle;
++ gctUINT64 idleTime;
++ gctUINT64 lastSlowdown;
++ gctUINT64 lastSlowdownIdle;
++ /* ID - Pointer database*/
++ gctPOINTER pointerDatabase;
++ gctPOINTER pointerDatabaseMutex;
++};
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++typedef struct _gckVIRTUAL_COMMAND_BUFFER * gckVIRTUAL_COMMAND_BUFFER_PTR;
++typedef struct _gckVIRTUAL_COMMAND_BUFFER
++{
++ gctPHYS_ADDR physical;
++ gctPOINTER userLogical;
++ gctPOINTER kernelLogical;
++ gctSIZE_T pageCount;
++ gctPOINTER pageTable;
++ gctUINT32 gpuAddress;
++ gctUINT pid;
++ gckVIRTUAL_COMMAND_BUFFER_PTR next;
++ gckVIRTUAL_COMMAND_BUFFER_PTR prev;
++ gckKERNEL kernel;
++}
++gckVIRTUAL_COMMAND_BUFFER;
++#endif
++
++/* gckKERNEL object. */
++struct _gckKERNEL
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Pointer to gckCOMMAND object. */
++ gckCOMMAND command;
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Pointer to context. */
++ gctPOINTER context;
++
++ /* Pointer to gckMMU object. */
++ gckMMU mmu;
++
++ /* Arom holding number of clients. */
++ gctPOINTER atomClients;
++
++#if VIVANTE_PROFILER
++ /* Enable profiling */
++ gctBOOL profileEnable;
++
++ /* Clear profile register or not*/
++ gctBOOL profileCleanRegister;
++
++#endif
++
++#ifdef QNX_SINGLE_THREADED_DEBUGGING
++ gctPOINTER debugMutex;
++#endif
++
++ /* Database management. */
++ gckDB db;
++ gctBOOL dbCreated;
++
++#if gcdENABLE_RECOVERY
++ gctPOINTER resetFlagClearTimer;
++ gctPOINTER resetAtom;
++ gctUINT64 resetTimeStamp;
++#endif
++
++ /* Pointer to gckEVENT object. */
++ gcsTIMER timers[8];
++ gctUINT32 timeOut;
++
++#if gcdENABLE_VG
++ gckVGKERNEL vg;
++#endif
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferHead;
++ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferTail;
++ gctPOINTER virtualBufferLock;
++#endif
++
++#if gcdDVFS
++ gckDVFS dvfs;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gctHANDLE timeline;
++#endif
++
++ spinlock_t irq_lock;
++};
++
++struct _FrequencyHistory
++{
++ gctUINT32 frequency;
++ gctUINT32 count;
++};
++
++/* gckDVFS object. */
++struct _gckDVFS
++{
++ gckOS os;
++ gckHARDWARE hardware;
++ gctPOINTER timer;
++ gctUINT32 pollingTime;
++ gctBOOL stop;
++ gctUINT32 totalConfig;
++ gctUINT32 loads[8];
++ gctUINT8 currentScale;
++ struct _FrequencyHistory frequencyHistory[16];
++};
++
++/* gckCOMMAND object. */
++struct _gckCOMMAND
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to required object. */
++ gckKERNEL kernel;
++ gckOS os;
++
++ /* Number of bytes per page. */
++ gctSIZE_T pageSize;
++
++ /* Current pipe select. */
++ gcePIPE_SELECT pipeSelect;
++
++ /* Command queue running flag. */
++ gctBOOL running;
++
++ /* Idle flag and commit stamp. */
++ gctBOOL idle;
++ gctUINT64 commitStamp;
++
++ /* Command queue mutex. */
++ gctPOINTER mutexQueue;
++
++ /* Context switching mutex. */
++ gctPOINTER mutexContext;
++
++#if VIVANTE_PROFILER_CONTEXT
++ /* Context sequence mutex. */
++ gctPOINTER mutexContextSeq;
++#endif
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++
++ /* Current command queue. */
++ struct _gcskCOMMAND_QUEUE
++ {
++ gctSIGNAL signal;
++ gctPHYS_ADDR physical;
++ gctPOINTER logical;
++ }
++ queues[gcdCOMMAND_QUEUES];
++
++ gctPHYS_ADDR physical;
++ gctPOINTER logical;
++ gctUINT32 offset;
++ gctINT index;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gctUINT wrapCount;
++#endif
++
++ /* The command queue is new. */
++ gctBOOL newQueue;
++
++ /* Context management. */
++ gckCONTEXT currContext;
++
++ /* Pointer to last WAIT command. */
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctSIZE_T waitSize;
++
++ /* Command buffer alignment. */
++ gctSIZE_T alignment;
++ gctSIZE_T reservedHead;
++ gctSIZE_T reservedTail;
++
++ /* Commit counter. */
++ gctPOINTER atomCommit;
++
++ /* Kernel process ID. */
++ gctUINT32 kernelProcessID;
++
++ /* End Event signal. */
++ gctSIGNAL endEventSignal;
++
++#if gcdSECURE_USER
++ /* Hint array copy buffer. */
++ gctBOOL hintArrayAllocated;
++ gctUINT hintArraySize;
++ gctUINT32_PTR hintArray;
++#endif
++};
++
++typedef struct _gcsEVENT * gcsEVENT_PTR;
++
++/* Structure holding one event to be processed. */
++typedef struct _gcsEVENT
++{
++ /* Pointer to next event in queue. */
++ gcsEVENT_PTR next;
++
++ /* Event information. */
++ gcsHAL_INTERFACE info;
++
++ /* Process ID owning the event. */
++ gctUINT32 processID;
++
++#ifdef __QNXNTO__
++ /* Kernel. */
++ gckKERNEL kernel;
++#endif
++
++ gctBOOL fromKernel;
++}
++gcsEVENT;
++
++/* Structure holding a list of events to be processed by an interrupt. */
++typedef struct _gcsEVENT_QUEUE * gcsEVENT_QUEUE_PTR;
++typedef struct _gcsEVENT_QUEUE
++{
++ /* Time stamp. */
++ gctUINT64 stamp;
++
++ /* Source of the event. */
++ gceKERNEL_WHERE source;
++
++ /* Pointer to head of event queue. */
++ gcsEVENT_PTR head;
++
++ /* Pointer to tail of event queue. */
++ gcsEVENT_PTR tail;
++
++ /* Next list of events. */
++ gcsEVENT_QUEUE_PTR next;
++}
++gcsEVENT_QUEUE;
++
++/*
++ gcdREPO_LIST_COUNT defines the maximum number of event queues with different
++ hardware module sources that may coexist at the same time. Only two sources
++ are supported - gcvKERNEL_COMMAND and gcvKERNEL_PIXEL. gcvKERNEL_COMMAND
++ source is used only for managing the kernel command queue and is only issued
++ when the current command queue gets full. Since we commit event queues every
++ time we commit command buffers, in the worst case we can have up to three
++ pending event queues:
++ - gcvKERNEL_PIXEL
++ - gcvKERNEL_COMMAND (queue overflow)
++ - gcvKERNEL_PIXEL
++*/
++#define gcdREPO_LIST_COUNT 3
++
++/* gckEVENT object. */
++struct _gckEVENT
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to required objects. */
++ gckOS os;
++ gckKERNEL kernel;
++
++ /* Time stamp. */
++ gctUINT64 stamp;
++ gctUINT64 lastCommitStamp;
++
++ /* Queue mutex. */
++ gctPOINTER eventQueueMutex;
++
++ /* Array of event queues. */
++ gcsEVENT_QUEUE queues[30];
++ gctUINT8 lastID;
++ gctPOINTER freeAtom;
++
++ /* Pending events. */
++#if gcdSMP
++ gctPOINTER pending;
++#else
++ volatile gctUINT pending;
++#endif
++
++ /* List of free event structures and its mutex. */
++ gcsEVENT_PTR freeEventList;
++ gctSIZE_T freeEventCount;
++ gctPOINTER freeEventMutex;
++
++ /* Event queues. */
++ gcsEVENT_QUEUE_PTR queueHead;
++ gcsEVENT_QUEUE_PTR queueTail;
++ gcsEVENT_QUEUE_PTR freeList;
++ gcsEVENT_QUEUE repoList[gcdREPO_LIST_COUNT];
++ gctPOINTER eventListMutex;
++
++ gctPOINTER submitTimer;
++
++ volatile gctBOOL inNotify;
++};
++
++/* Free all events belonging to a process. */
++gceSTATUS
++gckEVENT_FreeProcess(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID
++ );
++
++gceSTATUS
++gckEVENT_Stop(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Logical,
++ IN gctSIGNAL Signal,
++ IN OUT gctSIZE_T * waitSize
++ );
++
++gceSTATUS
++gckEVENT_WaitEmpty(
++ IN gckEVENT Event
++ );
++
++/* gcuVIDMEM_NODE structure. */
++typedef union _gcuVIDMEM_NODE
++{
++ /* Allocated from gckVIDMEM. */
++ struct _gcsVIDMEM_NODE_VIDMEM
++ {
++ /* Owner of this node. */
++ gckVIDMEM memory;
++
++ /* Dual-linked list of nodes. */
++ gcuVIDMEM_NODE_PTR next;
++ gcuVIDMEM_NODE_PTR prev;
++
++ /* Dual linked list of free nodes. */
++ gcuVIDMEM_NODE_PTR nextFree;
++ gcuVIDMEM_NODE_PTR prevFree;
++
++ /* Information for this node. */
++ gctUINT32 offset;
++ gctSIZE_T bytes;
++ gctUINT32 alignment;
++
++#ifdef __QNXNTO__
++ /* Client/server vaddr (mapped using mmap_join). */
++ gctPOINTER logical;
++#endif
++
++ /* Locked counter. */
++ gctINT32 locked;
++
++ /* Memory pool. */
++ gcePOOL pool;
++ gctUINT32 physical;
++
++ /* Process ID owning this memory. */
++ gctUINT32 processID;
++
++ /* Prevent compositor from freeing until client unlocks. */
++ gctBOOL freePending;
++
++ /* */
++ gcsVIDMEM_NODE_SHARED_INFO sharedInfo;
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ gctPOINTER kernelVirtual;
++#endif
++ }
++ VidMem;
++
++ /* Allocated from gckOS. */
++ struct _gcsVIDMEM_NODE_VIRTUAL
++ {
++ /* Pointer to gckKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Information for this node. */
++ /* Contiguously allocated? */
++ gctBOOL contiguous;
++ /* mdl record pointer... a kmalloc address. Process agnostic. */
++ gctPHYS_ADDR physical;
++ gctSIZE_T bytes;
++ /* do_mmap_pgoff address... mapped per-process. */
++ gctPOINTER logical;
++
++ /* Page table information. */
++ /* Used only when node is not contiguous */
++ gctSIZE_T pageCount;
++
++ /* Used only when node is not contiguous */
++ gctPOINTER pageTables[gcdMAX_GPU_COUNT];
++ /* Pointer to gckKERNEL object who lock this. */
++ gckKERNEL lockKernels[gcdMAX_GPU_COUNT];
++ /* Actual physical address */
++ gctUINT32 addresses[gcdMAX_GPU_COUNT];
++
++ /* Mutex. */
++ gctPOINTER mutex;
++
++ /* Locked counter. */
++ gctINT32 lockeds[gcdMAX_GPU_COUNT];
++
++#ifdef __QNXNTO__
++ /* Single linked list of nodes. */
++ gcuVIDMEM_NODE_PTR next;
++
++ /* Unlock pending flag. */
++ gctBOOL unlockPendings[gcdMAX_GPU_COUNT];
++
++ /* Free pending flag. */
++ gctBOOL freePending;
++#endif
++
++ /* Process ID owning this memory. */
++ gctUINT32 processID;
++
++ /* Owner process sets freed to true
++ * when it trys to free a locked
++ * node */
++ gctBOOL freed;
++
++ /* */
++ gcsVIDMEM_NODE_SHARED_INFO sharedInfo;
++ }
++ Virtual;
++}
++gcuVIDMEM_NODE;
++
++/* gckVIDMEM object. */
++struct _gckVIDMEM
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Information for this video memory heap. */
++ gctUINT32 baseAddress;
++ gctSIZE_T bytes;
++ gctSIZE_T freeBytes;
++
++ /* Mapping for each type of surface. */
++ gctINT mapping[gcvSURF_NUM_TYPES];
++
++ /* Sentinel nodes for up to 8 banks. */
++ gcuVIDMEM_NODE sentinel[8];
++
++ /* Allocation threshold. */
++ gctSIZE_T threshold;
++
++ /* The heap mutex. */
++ gctPOINTER mutex;
++
++#if gcdUSE_VIDMEM_PER_PID
++ /* The Pid this VidMem belongs to. */
++ gctUINT32 pid;
++
++ struct _gckVIDMEM* next;
++#endif
++};
++
++/* gckMMU object. */
++struct _gckMMU
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* The page table mutex. */
++ gctPOINTER pageTableMutex;
++
++ /* Page table information. */
++ gctSIZE_T pageTableSize;
++ gctPHYS_ADDR pageTablePhysical;
++ gctUINT32_PTR pageTableLogical;
++ gctUINT32 pageTableEntries;
++
++ /* Master TLB information. */
++ gctSIZE_T mtlbSize;
++ gctPHYS_ADDR mtlbPhysical;
++ gctUINT32_PTR mtlbLogical;
++ gctUINT32 mtlbEntries;
++
++ /* Free entries. */
++ gctUINT32 heapList;
++ gctBOOL freeNodes;
++
++ gctPOINTER staticSTLB;
++ gctBOOL enabled;
++
++ gctUINT32 dynamicMappingStart;
++
++#ifdef __QNXNTO__
++ /* Single linked list of all allocated nodes. */
++ gctPOINTER nodeMutex;
++ gcuVIDMEM_NODE_PTR nodeList;
++#endif
++};
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++gceSTATUS
++gckOS_CreateKernelVirtualMapping(
++ IN gctPHYS_ADDR Physical,
++ OUT gctSIZE_T * PageCount,
++ OUT gctPOINTER * Logical
++ );
++
++gceSTATUS
++gckOS_DestroyKernelVirtualMapping(
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckKERNEL_AllocateVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++gceSTATUS
++gckKERNEL_DestroyVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckKERNEL_GetGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++gceSTATUS
++gckKERNEL_QueryGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GpuAddress,
++ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer
++ );
++#endif
++
++gceSTATUS
++gckKERNEL_AttachProcess(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach
++ );
++
++gceSTATUS
++gckKERNEL_AttachProcessEx(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach,
++ IN gctUINT32 PID
++ );
++
++#if gcdSECURE_USER
++gceSTATUS
++gckKERNEL_MapLogicalToPhysical(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN OUT gctPOINTER * Data
++ );
++
++gceSTATUS
++gckKERNEL_FlushTranslationCache(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++#endif
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ );
++
++/******************************************************************************\
++******************************* gckCONTEXT Object *******************************
++\******************************************************************************/
++
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ );
++
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ );
++
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ );
++
++#if gcdLINK_QUEUE_SIZE
++void
++gckLINKQUEUE_Enqueue(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 start,
++ IN gctUINT32 end
++ );
++
++void
++gckLINKQUEUE_GetData(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 Index,
++ OUT gckLINKDATA * Data
++ );
++#endif
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,859 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/**
++** @file
++** gckHEAP object for kernel HAL layer. The heap implemented here is an arena-
++** based memory allocation. An arena-based memory heap allocates data quickly
++** from specified arenas and reduces memory fragmentation.
++**
++*/
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_HEAP
++
++/*******************************************************************************
++***** Structures ***************************************************************
++*******************************************************************************/
++
++#define gcdIN_USE ((gcskNODE_PTR) ~0)
++
++typedef struct _gcskNODE * gcskNODE_PTR;
++typedef struct _gcskNODE
++{
++ /* Number of byets in node. */
++ gctSIZE_T bytes;
++
++ /* Pointer to next free node, or gcvNULL to mark the node as freed, or
++ ** gcdIN_USE to mark the node as used. */
++ gcskNODE_PTR next;
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Time stamp of allocation. */
++ gctUINT64 timeStamp;
++#endif
++}
++gcskNODE;
++
++typedef struct _gcskHEAP * gcskHEAP_PTR;
++typedef struct _gcskHEAP
++{
++ /* Linked list. */
++ gcskHEAP_PTR next;
++ gcskHEAP_PTR prev;
++
++ /* Heap size. */
++ gctSIZE_T size;
++
++ /* Free list. */
++ gcskNODE_PTR freeList;
++}
++gcskHEAP;
++
++struct _gckHEAP
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to a gckOS object. */
++ gckOS os;
++
++ /* Locking mutex. */
++ gctPOINTER mutex;
++
++ /* Allocation parameters. */
++ gctSIZE_T allocationSize;
++
++ /* Heap list. */
++ gcskHEAP_PTR heap;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT64 timeStamp;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Profile information. */
++ gctUINT32 allocCount;
++ gctUINT64 allocBytes;
++ gctUINT64 allocBytesMax;
++ gctUINT64 allocBytesTotal;
++ gctUINT32 heapCount;
++ gctUINT32 heapCountMax;
++ gctUINT64 heapMemory;
++ gctUINT64 heapMemoryMax;
++#endif
++};
++
++/*******************************************************************************
++***** Static Support Functions *************************************************
++*******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++static gctSIZE_T
++_DumpHeap(
++ IN gcskHEAP_PTR Heap
++ )
++{
++ gctPOINTER p;
++ gctSIZE_T leaked = 0;
++
++ /* Start at first node. */
++ for (p = Heap + 1;;)
++ {
++ /* Convert the pointer. */
++ gcskNODE_PTR node = (gcskNODE_PTR) p;
++
++ /* Check if this is a used node. */
++ if (node->next == gcdIN_USE)
++ {
++ /* Print the leaking node. */
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_HEAP,
++ "Detected leaking: node=0x%x bytes=%lu timeStamp=%llu "
++ "(%08X %c%c%c%c)",
++ node, node->bytes, node->timeStamp,
++ ((gctUINT32_PTR) (node + 1))[0],
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[0]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[1]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[2]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[3]));
++
++ /* Add leaking byte count. */
++ leaked += node->bytes;
++ }
++
++ /* Test for end of heap. */
++ if (node->bytes == 0)
++ {
++ break;
++ }
++
++ else
++ {
++ /* Move to next node. */
++ p = (gctUINT8_PTR) node + node->bytes;
++ }
++ }
++
++ /* Return the number of leaked bytes. */
++ return leaked;
++}
++#endif
++
++static gceSTATUS
++_CompactKernelHeap(
++ IN gckHEAP Heap
++ )
++{
++ gcskHEAP_PTR heap, next;
++ gctPOINTER p;
++ gcskHEAP_PTR freeList = gcvNULL;
++
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ /* Walk all the heaps. */
++ for (heap = Heap->heap; heap != gcvNULL; heap = next)
++ {
++ gcskNODE_PTR lastFree = gcvNULL;
++
++ /* Zero out the free list. */
++ heap->freeList = gcvNULL;
++
++ /* Start at the first node. */
++ for (p = (gctUINT8_PTR) (heap + 1);;)
++ {
++ /* Convert the pointer. */
++ gcskNODE_PTR node = (gcskNODE_PTR) p;
++
++ gcmkASSERT(p <= (gctPOINTER) ((gctUINT8_PTR) (heap + 1) + heap->size));
++
++ /* Test if this node not used. */
++ if (node->next != gcdIN_USE)
++ {
++ /* Test if this is the end of the heap. */
++ if (node->bytes == 0)
++ {
++ break;
++ }
++
++ /* Test of this is the first free node. */
++ else if (lastFree == gcvNULL)
++ {
++ /* Initialzie the free list. */
++ heap->freeList = node;
++ lastFree = node;
++ }
++
++ else
++ {
++ /* Test if this free node is contiguous with the previous
++ ** free node. */
++ if ((gctUINT8_PTR) lastFree + lastFree->bytes == p)
++ {
++ /* Just increase the size of the previous free node. */
++ lastFree->bytes += node->bytes;
++ }
++ else
++ {
++ /* Add to linked list. */
++ lastFree->next = node;
++ lastFree = node;
++ }
++ }
++ }
++
++ /* Move to next node. */
++ p = (gctUINT8_PTR) node + node->bytes;
++ }
++
++ /* Mark the end of the chain. */
++ if (lastFree != gcvNULL)
++ {
++ lastFree->next = gcvNULL;
++ }
++
++ /* Get next heap. */
++ next = heap->next;
++
++ /* Check if the entire heap is free. */
++ if ((heap->freeList != gcvNULL)
++ && (heap->freeList->bytes == heap->size - gcmSIZEOF(gcskNODE))
++ )
++ {
++ /* Remove the heap from the linked list. */
++ if (heap->prev == gcvNULL)
++ {
++ Heap->heap = next;
++ }
++ else
++ {
++ heap->prev->next = next;
++ }
++
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap->prev;
++ }
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profiling. */
++ Heap->heapCount -= 1;
++ Heap->heapMemory -= heap->size + gcmSIZEOF(gcskHEAP);
++#endif
++
++ /* Add this heap to the list of heaps that need to be freed. */
++ heap->next = freeList;
++ freeList = heap;
++ }
++ }
++
++ if (freeList != gcvNULL)
++ {
++ /* Release the mutex, remove any chance for a dead lock. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Free all heaps in the free list. */
++ for (heap = freeList; heap != gcvNULL; heap = next)
++ {
++ /* Get pointer to the next heap. */
++ next = heap->next;
++
++ /* Free the heap. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HEAP,
++ "Freeing heap 0x%x (%lu bytes)",
++ heap, heap->size + gcmSIZEOF(gcskHEAP));
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, heap));
++ }
++
++ /* Acquire the mutex again. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++***** gckHEAP API Code *********************************************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckHEAP_Construct
++**
++** Construct a new gckHEAP object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctSIZE_T AllocationSize
++** Minimum size per arena.
++**
++** OUTPUT:
++**
++** gckHEAP * Heap
++** Pointer to a variable that will hold the pointer to the gckHEAP
++** object.
++*/
++gceSTATUS
++gckHEAP_Construct(
++ IN gckOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gckHEAP * Heap
++ )
++{
++ gceSTATUS status;
++ gckHEAP heap = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x AllocationSize=%lu", Os, AllocationSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Heap != gcvNULL);
++
++ /* Allocate the gckHEAP object. */
++ gcmkONERROR(gckOS_AllocateMemory(Os,
++ gcmSIZEOF(struct _gckHEAP),
++ &pointer));
++
++ heap = pointer;
++
++ /* Initialize the gckHEAP object. */
++ heap->object.type = gcvOBJ_HEAP;
++ heap->os = Os;
++ heap->allocationSize = AllocationSize;
++ heap->heap = gcvNULL;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ heap->timeStamp = 0;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Zero the counters. */
++ heap->allocCount = 0;
++ heap->allocBytes = 0;
++ heap->allocBytesMax = 0;
++ heap->allocBytesTotal = 0;
++ heap->heapCount = 0;
++ heap->heapCountMax = 0;
++ heap->heapMemory = 0;
++ heap->heapMemoryMax = 0;
++#endif
++
++ /* Create the mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &heap->mutex));
++
++ /* Return the pointer to the gckHEAP object. */
++ *Heap = heap;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Heap=0x%x", *Heap);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (heap != gcvNULL)
++ {
++ /* Free the heap structure. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Os, heap));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Destroy
++**
++** Destroy a gckHEAP object.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHEAP_Destroy(
++ IN gckHEAP Heap
++ )
++{
++ gcskHEAP_PTR heap;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctSIZE_T leaked = 0;
++#endif
++
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ for (heap = Heap->heap; heap != gcvNULL; heap = Heap->heap)
++ {
++ /* Unlink heap from linked list. */
++ Heap->heap = heap->next;
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Check for leaked memory. */
++ leaked += _DumpHeap(heap);
++#endif
++
++ /* Free the heap. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, heap));
++ }
++
++ /* Free the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Heap->os, Heap->mutex));
++
++ /* Free the heap structure. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, Heap));
++
++ /* Success. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gcmkFOOTER_ARG("leaked=%lu", leaked);
++#else
++ gcmkFOOTER_NO();
++#endif
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Allocate
++**
++** Allocate data from the heap.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object.
++**
++** IN gctSIZE_T Bytes
++** Number of byte to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the address of the allocated
++** memory.
++*/
++gceSTATUS
++gckHEAP_Allocate(
++ IN gckHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gctBOOL acquired = gcvFALSE;
++ gcskHEAP_PTR heap;
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gcskNODE_PTR node, used, prevFree = gcvNULL;
++ gctPOINTER memory = gcvNULL;
++
++ gcmkHEADER_ARG("Heap=0x%x Bytes=%lu", Heap, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Determine number of bytes required for a node. */
++ bytes = gcmALIGN(Bytes + gcmSIZEOF(gcskNODE), 8);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ /* Check if this allocation is bigger than the default allocation size. */
++ if (bytes > Heap->allocationSize - gcmSIZEOF(gcskHEAP) - gcmSIZEOF(gcskNODE))
++ {
++ /* Adjust allocation size. */
++ Heap->allocationSize = bytes * 2;
++ }
++
++ else if (Heap->heap != gcvNULL)
++ {
++ gctINT i;
++
++ /* 2 retries, since we might need to compact. */
++ for (i = 0; i < 2; ++i)
++ {
++ /* Walk all the heaps. */
++ for (heap = Heap->heap; heap != gcvNULL; heap = heap->next)
++ {
++ /* Check if this heap has enough bytes to hold the request. */
++ if (bytes <= heap->size - gcmSIZEOF(gcskNODE))
++ {
++ prevFree = gcvNULL;
++
++ /* Walk the chain of free nodes. */
++ for (node = heap->freeList;
++ node != gcvNULL;
++ node = node->next
++ )
++ {
++ gcmkASSERT(node->next != gcdIN_USE);
++
++ /* Check if this free node has enough bytes. */
++ if (node->bytes >= bytes)
++ {
++ /* Use the node. */
++ goto UseNode;
++ }
++
++ /* Save current free node for linked list management. */
++ prevFree = node;
++ }
++ }
++ }
++
++ if (i == 0)
++ {
++ /* Compact the heap. */
++ gcmkVERIFY_OK(_CompactKernelHeap(Heap));
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "===== KERNEL HEAP =====");
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of allocations : %12u",
++ Heap->allocCount);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of bytes allocated : %12llu",
++ Heap->allocBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum allocation size : %12llu",
++ Heap->allocBytesMax);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Total number of bytes allocated : %12llu",
++ Heap->allocBytesTotal);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of heaps : %12u",
++ Heap->heapCount);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Heap memory in bytes : %12llu",
++ Heap->heapMemory);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum number of heaps : %12u",
++ Heap->heapCountMax);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum heap memory in bytes : %12llu",
++ Heap->heapMemoryMax);
++#endif
++ }
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkONERROR(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ acquired = gcvFALSE;
++
++ /* Allocate a new heap. */
++ gcmkONERROR(
++ gckOS_AllocateMemory(Heap->os,
++ Heap->allocationSize,
++ &memory));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HEAP,
++ "Allocated heap 0x%x (%lu bytes)",
++ memory, Heap->allocationSize);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ /* Use the allocated memory as the heap. */
++ heap = (gcskHEAP_PTR) memory;
++
++ /* Insert this heap to the head of the chain. */
++ heap->next = Heap->heap;
++ heap->prev = gcvNULL;
++ heap->size = Heap->allocationSize - gcmSIZEOF(gcskHEAP);
++
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap;
++ }
++ Heap->heap = heap;
++
++ /* Mark the end of the heap. */
++ node = (gcskNODE_PTR) ( (gctUINT8_PTR) heap
++ + Heap->allocationSize
++ - gcmSIZEOF(gcskNODE)
++ );
++ node->bytes = 0;
++ node->next = gcvNULL;
++
++ /* Create a free list. */
++ node = (gcskNODE_PTR) (heap + 1);
++ heap->freeList = node;
++
++ /* Initialize the free list. */
++ node->bytes = heap->size - gcmSIZEOF(gcskNODE);
++ node->next = gcvNULL;
++
++ /* No previous free. */
++ prevFree = gcvNULL;
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profiling. */
++ Heap->heapCount += 1;
++ Heap->heapMemory += Heap->allocationSize;
++
++ if (Heap->heapCount > Heap->heapCountMax)
++ {
++ Heap->heapCountMax = Heap->heapCount;
++ }
++ if (Heap->heapMemory > Heap->heapMemoryMax)
++ {
++ Heap->heapMemoryMax = Heap->heapMemory;
++ }
++#endif
++
++UseNode:
++ /* Verify some stuff. */
++ gcmkASSERT(heap != gcvNULL);
++ gcmkASSERT(node != gcvNULL);
++ gcmkASSERT(node->bytes >= bytes);
++
++ if (heap->prev != gcvNULL)
++ {
++ /* Unlink the heap from the linked list. */
++ heap->prev->next = heap->next;
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap->prev;
++ }
++
++ /* Move the heap to the front of the list. */
++ heap->next = Heap->heap;
++ heap->prev = gcvNULL;
++ Heap->heap = heap;
++ heap->next->prev = heap;
++ }
++
++ /* Check if there is enough free space left after usage for another free
++ ** node. */
++ if (node->bytes - bytes >= gcmSIZEOF(gcskNODE))
++ {
++ /* Allocated used space from the back of the free list. */
++ used = (gcskNODE_PTR) ((gctUINT8_PTR) node + node->bytes - bytes);
++
++ /* Adjust the number of free bytes. */
++ node->bytes -= bytes;
++ gcmkASSERT(node->bytes >= gcmSIZEOF(gcskNODE));
++ }
++ else
++ {
++ /* Remove this free list from the chain. */
++ if (prevFree == gcvNULL)
++ {
++ heap->freeList = node->next;
++ }
++ else
++ {
++ prevFree->next = node->next;
++ }
++
++ /* Consume the entire free node. */
++ used = (gcskNODE_PTR) node;
++ bytes = node->bytes;
++ }
++
++ /* Mark node as used. */
++ used->bytes = bytes;
++ used->next = gcdIN_USE;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ used->timeStamp = ++Heap->timeStamp;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profile counters. */
++ Heap->allocCount += 1;
++ Heap->allocBytes += bytes;
++ Heap->allocBytesMax = gcmMAX(Heap->allocBytes, Heap->allocBytesMax);
++ Heap->allocBytesTotal += bytes;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Return pointer to memory. */
++ *Memory = used + 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%x", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++ }
++
++ if (memory != gcvNULL)
++ {
++ /* Free the heap memory. */
++ gckOS_FreeMemory(Heap->os, memory);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Free
++**
++** Free allocated memory from the heap.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object.
++**
++** IN gctPOINTER Memory
++** Pointer to memory to free.
++**
++** OUTPUT:
++**
++** NOTHING.
++*/
++gceSTATUS
++gckHEAP_Free(
++ IN gckHEAP Heap,
++ IN gctPOINTER Memory
++ )
++{
++ gcskNODE_PTR node;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Heap=0x%x Memory=0x%x", Heap, Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ /* Pointer to structure. */
++ node = (gcskNODE_PTR) Memory - 1;
++
++ /* Mark the node as freed. */
++ node->next = gcvNULL;
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profile counters. */
++ Heap->allocBytes -= node->bytes;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHEAP_ProfileStart(
++ IN gckHEAP Heap
++ )
++{
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++
++ /* Zero the counters. */
++ Heap->allocCount = 0;
++ Heap->allocBytes = 0;
++ Heap->allocBytesMax = 0;
++ Heap->allocBytesTotal = 0;
++ Heap->heapCount = 0;
++ Heap->heapCountMax = 0;
++ Heap->heapMemory = 0;
++ Heap->heapMemoryMax = 0;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHEAP_ProfileEnd(
++ IN gckHEAP Heap,
++ IN gctCONST_STRING Title
++ )
++{
++ gcmkHEADER_ARG("Heap=0x%x Title=0x%x", Heap, Title);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Title != gcvNULL);
++
++ gcmkPRINT("");
++ gcmkPRINT("=====[ HEAP - %s ]=====", Title);
++ gcmkPRINT("Number of allocations : %12u", Heap->allocCount);
++ gcmkPRINT("Number of bytes allocated : %12llu", Heap->allocBytes);
++ gcmkPRINT("Maximum allocation size : %12llu", Heap->allocBytesMax);
++ gcmkPRINT("Total number of bytes allocated : %12llu", Heap->allocBytesTotal);
++ gcmkPRINT("Number of heaps : %12u", Heap->heapCount);
++ gcmkPRINT("Heap memory in bytes : %12llu", Heap->heapMemory);
++ gcmkPRINT("Maximum number of heaps : %12u", Heap->heapCountMax);
++ gcmkPRINT("Maximum heap memory in bytes : %12llu", Heap->heapMemoryMax);
++ gcmkPRINT("==============================================");
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif /* VIVANTE_PROFILER */
++
++/*******************************************************************************
++***** Test Code ****************************************************************
++*******************************************************************************/
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,877 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++/* Interruot statistics will be accumulated if not zero. */
++#define gcmENABLE_INTERRUPT_STATISTICS 0
++
++#define _GC_OBJ_ZONE gcvZONE_INTERRUPT
++
++/* Object structure. */
++struct _gckVGINTERRUPT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* gckVGKERNEL pointer. */
++ gckVGKERNEL kernel;
++
++ /* gckOS pointer. */
++ gckOS os;
++
++ /* Interrupt handlers. */
++ gctINTERRUPT_HANDLER handlers[32];
++
++ /* Main interrupt handler thread. */
++ gctTHREAD handler;
++ gctBOOL terminate;
++
++ /* Interrupt FIFO. */
++ gctSEMAPHORE fifoValid;
++ gctUINT32 fifo[256];
++ gctUINT fifoItems;
++ gctUINT8 head;
++ gctUINT8 tail;
++
++ /* Interrupt statistics. */
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gctUINT maxFifoItems;
++ gctUINT fifoOverflow;
++ gctUINT maxSimultaneous;
++ gctUINT multipleCount;
++#endif
++};
++
++
++/*******************************************************************************
++**
++** _ProcessInterrupt
++**
++** The interrupt processor.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++static void
++_ProcessInterrupt(
++ gckVGINTERRUPT Interrupt,
++ gctUINT_PTR TriggeredCount
++ )
++#else
++static void
++_ProcessInterrupt(
++ gckVGINTERRUPT Interrupt
++ )
++#endif
++{
++ gceSTATUS status;
++ gctUINT32 triggered;
++ gctUINT i;
++
++ /* Advance to the next entry. */
++ Interrupt->tail += 1;
++ Interrupt->fifoItems -= 1;
++
++ /* Get the interrupt value. */
++ triggered = Interrupt->fifo[Interrupt->tail];
++ gcmkASSERT(triggered != 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: triggered=0x%08X\n",
++ __FUNCTION__,
++ triggered
++ );
++
++ /* Walk through all possible interrupts. */
++ for (i = 0; i < gcmSIZEOF(Interrupt->handlers); i += 1)
++ {
++ /* Test if interrupt happened. */
++ if ((triggered & 1) == 1)
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ if (TriggeredCount != gcvNULL)
++ {
++ (* TriggeredCount) += 1;
++ }
++#endif
++
++ /* Make sure we have valid handler. */
++ if (Interrupt->handlers[i] == gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s: Interrupt %d isn't registered.\n",
++ __FUNCTION__, i
++ );
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: interrupt=%d\n",
++ __FUNCTION__,
++ i
++ );
++
++ /* Call the handler. */
++ status = Interrupt->handlers[i] (Interrupt->kernel);
++
++ if (gcmkIS_ERROR(status))
++ {
++ /* Failed to signal the semaphore. */
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s: Error %d incrementing the semaphore #%d.\n",
++ __FUNCTION__, status, i
++ );
++ }
++ }
++ }
++
++ /* Next interrupt. */
++ triggered >>= 1;
++
++ /* No more interrupts to handle? */
++ if (triggered == 0)
++ {
++ break;
++ }
++ }
++}
++
++
++/*******************************************************************************
++**
++** _MainInterruptHandler
++**
++** The main interrupt thread serves the interrupt FIFO and calls registered
++** handlers for the interrupts that occured. The handlers are called in the
++** sequence interrupts occured with the exception when multiple interrupts
++** occured at the same time. In that case the handler calls are "sorted" by
++** the interrupt number therefore giving the interrupts with lower numbers
++** higher priority.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++static gctTHREADFUNCRESULT gctTHREADFUNCTYPE
++_MainInterruptHandler(
++ gctTHREADFUNCPARAMETER ThreadParameter
++ )
++{
++ gceSTATUS status;
++ gckVGINTERRUPT interrupt;
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gctUINT count;
++#endif
++
++ /* Cast the object. */
++ interrupt = (gckVGINTERRUPT) ThreadParameter;
++
++ /* Enter the loop. */
++ while (gcvTRUE)
++ {
++ /* Wait for an interrupt. */
++ status = gckOS_DecrementSemaphore(interrupt->os, interrupt->fifoValid);
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* System termination request? */
++ if (status == gcvSTATUS_TERMINATE)
++ {
++ break;
++ }
++
++ /* Driver is shutting down? */
++ if (interrupt->terminate)
++ {
++ break;
++ }
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ /* Reset triggered count. */
++ count = 0;
++
++ /* Process the interrupt. */
++ _ProcessInterrupt(interrupt, &count);
++
++ /* Update conters. */
++ if (count > interrupt->maxSimultaneous)
++ {
++ interrupt->maxSimultaneous = count;
++ }
++
++ if (count > 1)
++ {
++ interrupt->multipleCount += 1;
++ }
++#else
++ /* Process the interrupt. */
++ _ProcessInterrupt(interrupt);
++#endif
++ }
++
++ return 0;
++}
++
++
++/*******************************************************************************
++**
++** _StartInterruptHandler / _StopInterruptHandler
++**
++** Main interrupt handler routine control.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++static gceSTATUS
++_StartInterruptHandler(
++ gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status, last;
++
++ do
++ {
++ /* Objects must not be already created. */
++ gcmkASSERT(Interrupt->fifoValid == gcvNULL);
++ gcmkASSERT(Interrupt->handler == gcvNULL);
++
++ /* Reset the termination request. */
++ Interrupt->terminate = gcvFALSE;
++
++#if !gcdENABLE_INFINITE_SPEED_HW
++ /* Construct the fifo semaphore. */
++ gcmkERR_BREAK(gckOS_CreateSemaphoreVG(
++ Interrupt->os, &Interrupt->fifoValid
++ ));
++
++ /* Start the interrupt handler thread. */
++ gcmkERR_BREAK(gckOS_StartThread(
++ Interrupt->os,
++ _MainInterruptHandler,
++ Interrupt,
++ &Interrupt->handler
++ ));
++#endif
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (Interrupt->fifoValid != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DestroySemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ Interrupt->fifoValid = gcvNULL;
++ }
++
++ /* Return the status. */
++ return status;
++}
++
++static gceSTATUS
++_StopInterruptHandler(
++ gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Does the thread exist? */
++ if (Interrupt->handler == gcvNULL)
++ {
++ /* The semaphore must be NULL as well. */
++ gcmkASSERT(Interrupt->fifoValid == gcvNULL);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* The semaphore must exist as well. */
++ gcmkASSERT(Interrupt->fifoValid != gcvNULL);
++
++ /* Set the termination request. */
++ Interrupt->terminate = gcvTRUE;
++
++ /* Unlock the thread. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Wait until the thread quits. */
++ gcmkERR_BREAK(gckOS_StopThread(
++ Interrupt->os,
++ Interrupt->handler
++ ));
++
++ /* Destroy the semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Reset handles. */
++ Interrupt->handler = gcvNULL;
++ Interrupt->fifoValid = gcvNULL;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++
++/******************************************************************************\
++***************************** Interrupt Object API *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Construct
++**
++** Construct an interrupt object.
++**
++** INPUT:
++**
++** Kernel
++** Pointer to the gckVGKERNEL object.
++**
++** OUTPUT:
++**
++** Interrupt
++** Pointer to the new gckVGINTERRUPT object.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Construct(
++ IN gckVGKERNEL Kernel,
++ OUT gckVGINTERRUPT * Interrupt
++ )
++{
++ gceSTATUS status;
++ gckVGINTERRUPT interrupt = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x Interrupt=0x%x", Kernel, Interrupt);
++
++ /* Verify argeuments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interrupt != gcvNULL);
++
++ do
++ {
++ /* Allocate the gckVGINTERRUPT structure. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(struct _gckVGINTERRUPT),
++ (gctPOINTER *) &interrupt
++ ));
++
++ /* Reset the object data. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ interrupt, gcmSIZEOF(struct _gckVGINTERRUPT)
++ ));
++
++ /* Initialize the object. */
++ interrupt->object.type = gcvOBJ_INTERRUPT;
++
++ /* Initialize the object pointers. */
++ interrupt->kernel = Kernel;
++ interrupt->os = Kernel->os;
++
++ /* Initialize the current FIFO position. */
++ interrupt->head = (gctUINT8)~0;
++ interrupt->tail = (gctUINT8)~0;
++
++ /* Start the thread. */
++ gcmkERR_BREAK(_StartInterruptHandler(interrupt));
++
++ /* Return interrupt object. */
++ *Interrupt = interrupt;
++
++ gcmkFOOTER_ARG("*Interrup=0x%x", *Interrupt);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (interrupt != gcvNULL)
++ {
++ /* Free the gckVGINTERRUPT structure. */
++ gcmkVERIFY_OK(gckOS_Free(interrupt->os, interrupt));
++ }
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Destroy
++**
++** Destroy an interrupt object.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to the gckVGINTERRUPT object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Destroy(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ do
++ {
++ /* Stop the interrupt thread. */
++ gcmkERR_BREAK(_StopInterruptHandler(Interrupt));
++
++ /* Mark the object as unknown. */
++ Interrupt->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGINTERRUPT structure. */
++ gcmkERR_BREAK(gckOS_Free(Interrupt->os, Interrupt));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_DumpState
++**
++** Print the current state of the interrupt manager.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#if gcvDEBUG
++gceSTATUS
++gckVGINTERRUPT_DumpState(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ /* Print the header. */
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: INTERRUPT OBJECT STATUS\n",
++ __FUNCTION__
++ );
++
++ /* Print statistics. */
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Maximum number of FIFO items accumulated at a single time: %d\n",
++ Interrupt->maxFifoItems
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Interrupt FIFO overflow happened times: %d\n",
++ Interrupt->fifoOverflow
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Maximum number of interrupts simultaneously generated: %d\n",
++ Interrupt->maxSimultaneous
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Number of times when there were multiple interrupts generated: %d\n",
++ Interrupt->multipleCount
++ );
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " The current number of entries in the FIFO: %d\n",
++ Interrupt->fifoItems
++ );
++
++ /* Print the FIFO contents. */
++ if (Interrupt->fifoItems != 0)
++ {
++ gctUINT8 index;
++ gctUINT8 last;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " FIFO current contents:\n"
++ );
++
++ /* Get the current pointers. */
++ index = Interrupt->tail;
++ last = Interrupt->head;
++
++ while (index != last)
++ {
++ /* Advance to the next entry. */
++ index += 1;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " %d: 0x%08X\n",
++ index, Interrupt->fifo[index]
++ );
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Enable
++**
++** Enable the specified interrupt.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** Id
++** Pointer to the variable that holds the interrupt number to be
++** registered in range 0..31.
++** If the value is less then 0, gckVGINTERRUPT_Enable will attempt
++** to find an unused interrupt. If such interrupt is found, the number
++** will be assigned to the variable if the functuion call succeedes.
++**
++** Handler
++** Pointer to the handler to register for the interrupt.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Enable(
++ IN gckVGINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ )
++{
++ gceSTATUS status;
++ gctINT32 i;
++
++ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x Handler=0x%x", Interrupt, Id, Handler);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++ gcmkVERIFY_ARGUMENT(Id != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Handler != gcvNULL);
++
++ do
++ {
++ /* See if we need to allocate an ID. */
++ if (*Id < 0)
++ {
++ /* Find the first unused interrupt handler. */
++ for (i = 0; i < gcmCOUNTOF(Interrupt->handlers); ++i)
++ {
++ if (Interrupt->handlers[i] == gcvNULL)
++ {
++ break;
++ }
++ }
++
++ /* No unused innterrupts? */
++ if (i == gcmCOUNTOF(Interrupt->handlers))
++ {
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ break;
++ }
++
++ /* Update the interrupt ID. */
++ *Id = i;
++ }
++
++ /* Make sure the ID is in range. */
++ else if (*Id >= gcmCOUNTOF(Interrupt->handlers))
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ /* Set interrupt handler. */
++ Interrupt->handlers[*Id] = Handler;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Disable
++**
++** Disable the specified interrupt.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** Id
++** Interrupt number to be disabled in range 0..31.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Disable(
++ IN gckVGINTERRUPT Interrupt,
++ IN gctINT32 Id
++ )
++{
++ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x", Interrupt, Id);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++ gcmkVERIFY_ARGUMENT((Id >= 0) && (Id < gcmCOUNTOF(Interrupt->handlers)));
++
++ /* Reset interrupt handler. */
++ Interrupt->handlers[Id] = gcvNULL;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Enque
++**
++** Read the interrupt status register and put the value in the interrupt FIFO.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#ifndef __QNXNTO__
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt
++ )
++#else
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt,
++ OUT gckOS *Os,
++ OUT gctSEMAPHORE *Semaphore
++ )
++#endif
++{
++ gceSTATUS status;
++ gctUINT32 triggered;
++
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++#ifdef __QNXNTO__
++ *Os = gcvNULL;
++ *Semaphore = gcvNULL;
++#endif
++
++ do
++ {
++ /* Read interrupt status register. */
++ gcmkERR_BREAK(gckVGHARDWARE_ReadInterrupt(
++ Interrupt->kernel->hardware, &triggered
++ ));
++
++ /* Mask out TS overflow interrupt */
++ triggered &= 0xfffffffe;
++
++ /* No interrupts to process? */
++ if (triggered == 0)
++ {
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ break;
++ }
++
++ /* FIFO overflow? */
++ if (Interrupt->fifoItems == gcmCOUNTOF(Interrupt->fifo))
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ Interrupt->fifoOverflow += 1;
++#endif
++
++ /* OR the interrupt with the last value in the FIFO. */
++ Interrupt->fifo[Interrupt->head] |= triggered;
++
++ /* Success (kind of). */
++ status = gcvSTATUS_OK;
++ }
++ else
++ {
++ /* Advance to the next entry. */
++ Interrupt->head += 1;
++ Interrupt->fifoItems += 1;
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ if (Interrupt->fifoItems > Interrupt->maxFifoItems)
++ {
++ Interrupt->maxFifoItems = Interrupt->fifoItems;
++ }
++#endif
++
++ /* Set the new value. */
++ Interrupt->fifo[Interrupt->head] = triggered;
++
++#ifndef __QNXNTO__
++ /* Increment the FIFO semaphore. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++#else
++ *Os = Interrupt->os;
++ *Semaphore = Interrupt->fifoValid;
++#endif
++
++ /* Windows kills our threads prematurely when the application
++ exists. Verify here that the thread is still alive. */
++ status = gckOS_VerifyThread(Interrupt->os, Interrupt->handler);
++
++ /* Has the thread been prematurely terminated? */
++ if (status != gcvSTATUS_OK)
++ {
++ /* Process all accumulated interrupts. */
++ while (Interrupt->head != Interrupt->tail)
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ /* Process the interrupt. */
++ _ProcessInterrupt(Interrupt, gcvNULL);
++#else
++ /* Process the interrupt. */
++ _ProcessInterrupt(Interrupt);
++#endif
++ }
++
++ /* Set success. */
++ status = gcvSTATUS_OK;
++ }
++ }
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,1870 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_MMU
++
++typedef enum _gceMMU_TYPE
++{
++ gcvMMU_USED = (0 << 4),
++ gcvMMU_SINGLE = (1 << 4),
++ gcvMMU_FREE = (2 << 4),
++}
++gceMMU_TYPE;
++
++#define gcmENTRY_TYPE(x) (x & 0xF0)
++
++#define gcdMMU_TABLE_DUMP 0
++
++#define gcdUSE_MMU_EXCEPTION 0
++
++/*
++ gcdMMU_CLEAR_VALUE
++
++ The clear value for the entry of the old MMU.
++*/
++#ifndef gcdMMU_CLEAR_VALUE
++# define gcdMMU_CLEAR_VALUE 0x00000ABC
++#endif
++
++typedef struct _gcsMMU_STLB *gcsMMU_STLB_PTR;
++
++typedef struct _gcsMMU_STLB
++{
++ gctPHYS_ADDR physical;
++ gctUINT32_PTR logical;
++ gctSIZE_T size;
++ gctUINT32 physBase;
++ gctSIZE_T pageCount;
++ gctUINT32 mtlbIndex;
++ gctUINT32 mtlbEntryNum;
++ gcsMMU_STLB_PTR next;
++} gcsMMU_STLB;
++
++#if gcdSHARED_PAGETABLE
++typedef struct _gcsSharedPageTable * gcsSharedPageTable_PTR;
++typedef struct _gcsSharedPageTable
++{
++ /* Shared gckMMU object. */
++ gckMMU mmu;
++
++ /* Hardwares which use this shared pagetable. */
++ gckHARDWARE hardwares[gcdMAX_GPU_COUNT];
++
++ /* Number of cores use this shared pagetable. */
++ gctUINT32 reference;
++}
++gcsSharedPageTable;
++
++static gcsSharedPageTable_PTR sharedPageTable = gcvNULL;
++#endif
++
++#if gcdMIRROR_PAGETABLE
++typedef struct _gcsMirrorPageTable * gcsMirrorPageTable_PTR;
++typedef struct _gcsMirrorPageTable
++{
++ /* gckMMU objects. */
++ gckMMU mmus[gcdMAX_GPU_COUNT];
++
++ /* Hardwares which use this shared pagetable. */
++ gckHARDWARE hardwares[gcdMAX_GPU_COUNT];
++
++ /* Number of cores use this shared pagetable. */
++ gctUINT32 reference;
++}
++gcsMirrorPageTable;
++
++static gcsMirrorPageTable_PTR mirrorPageTable = gcvNULL;
++static gctPOINTER mirrorPageTableMutex = gcvNULL;
++#endif
++
++typedef struct _gcsDynamicSpaceNode * gcsDynamicSpaceNode_PTR;
++typedef struct _gcsDynamicSpaceNode
++{
++ gctUINT32 start;
++ gctINT32 entries;
++}
++gcsDynamicSpaceNode;
++
++static void
++_WritePageEntry(
++ IN gctUINT32_PTR PageEntry,
++ IN gctUINT32 EntryValue
++ )
++{
++ static gctUINT16 data = 0xff00;
++
++ if (*(gctUINT8 *)&data == 0xff)
++ {
++ *PageEntry = gcmSWAB32(EntryValue);
++ }
++ else
++ {
++ *PageEntry = EntryValue;
++ }
++}
++
++static gctUINT32
++_ReadPageEntry(
++ IN gctUINT32_PTR PageEntry
++ )
++{
++ static gctUINT16 data = 0xff00;
++ gctUINT32 entryValue;
++
++ if (*(gctUINT8 *)&data == 0xff)
++ {
++ entryValue = *PageEntry;
++ return gcmSWAB32(entryValue);
++ }
++ else
++ {
++ return *PageEntry;
++ }
++}
++
++static gceSTATUS
++_FillPageTable(
++ IN gctUINT32_PTR PageTable,
++ IN gctUINT32 PageCount,
++ IN gctUINT32 EntryValue
++)
++{
++ gctUINT i;
++
++ for (i = 0; i < PageCount; i++)
++ {
++ _WritePageEntry(PageTable + i, EntryValue);
++ }
++
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_Link(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 Next
++ )
++{
++ if (Index >= Mmu->pageTableEntries)
++ {
++ /* Just move heap pointer. */
++ Mmu->heapList = Next;
++ }
++ else
++ {
++ /* Address page table. */
++ gctUINT32_PTR pageTable = Mmu->pageTableLogical;
++
++ /* Dispatch on node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&pageTable[Index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Set single index. */
++ _WritePageEntry(&pageTable[Index], (Next << 8) | gcvMMU_SINGLE);
++ break;
++
++ case gcvMMU_FREE:
++ /* Set index. */
++ _WritePageEntry(&pageTable[Index + 1], Next);
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", Index);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_AddFree(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 Node,
++ IN gctUINT32 Count
++ )
++{
++ gctUINT32_PTR pageTable = Mmu->pageTableLogical;
++
++ if (Count == 1)
++ {
++ /* Initialize a single page node. */
++ _WritePageEntry(pageTable + Node, (~((1U<<8)-1)) | gcvMMU_SINGLE);
++ }
++ else
++ {
++ /* Initialize the node. */
++ _WritePageEntry(pageTable + Node + 0, (Count << 8) | gcvMMU_FREE);
++ _WritePageEntry(pageTable + Node + 1, ~0U);
++ }
++
++ /* Append the node. */
++ return _Link(Mmu, Index, Node);
++}
++
++static gceSTATUS
++_Collect(
++ IN gckMMU Mmu
++ )
++{
++ gctUINT32_PTR pageTable = Mmu->pageTableLogical;
++ gceSTATUS status;
++ gctUINT32 i, previous, start = 0, count = 0;
++
++ previous = Mmu->heapList = ~0U;
++ Mmu->freeNodes = gcvFALSE;
++
++ /* Walk the entire page table. */
++ for (i = 0; i < Mmu->pageTableEntries; ++i)
++ {
++ /* Dispatch based on type of page. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&pageTable[i])))
++ {
++ case gcvMMU_USED:
++ /* Used page, so close any open node. */
++ if (count > 0)
++ {
++ /* Add the node. */
++ gcmkONERROR(_AddFree(Mmu, previous, start, count));
++
++ /* Reset the node. */
++ previous = start;
++ count = 0;
++ }
++ break;
++
++ case gcvMMU_SINGLE:
++ /* Single free node. */
++ if (count++ == 0)
++ {
++ /* Start a new node. */
++ start = i;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ /* A free node. */
++ if (count == 0)
++ {
++ /* Start a new node. */
++ start = i;
++ }
++
++ /* Advance the count. */
++ count += _ReadPageEntry(&pageTable[i]) >> 8;
++
++ /* Advance the index into the page table. */
++ i += (_ReadPageEntry(&pageTable[i]) >> 8) - 1;
++ break;
++
++ default:
++ gcmkFATAL("MMU page table correcupted at index %u!", i);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++ }
++
++ /* See if we have an open node left. */
++ if (count > 0)
++ {
++ /* Add the node to the list. */
++ gcmkONERROR(_AddFree(Mmu, previous, start, count));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_MMU,
++ "Performed a garbage collection of the MMU heap.");
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the staus. */
++ return status;
++}
++
++static gctUINT32
++_SetPage(gctUINT32 PageAddress)
++{
++ return PageAddress
++ /* writable */
++ | (1 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0);
++}
++
++static gceSTATUS
++_FillFlatMapping(
++ IN gckMMU Mmu,
++ IN gctUINT32 PhysBase,
++ OUT gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gcsMMU_STLB_PTR head = gcvNULL, pre = gcvNULL;
++ gctUINT32 start = PhysBase & (~gcdMMU_PAGE_64K_MASK);
++ gctUINT32 end = (PhysBase + Size - 1) & (~gcdMMU_PAGE_64K_MASK);
++ gctUINT32 mStart = start >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 mEnd = end >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 sStart = (start & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++ gctUINT32 sEnd = (end & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ while (mStart <= mEnd)
++ {
++ gcmkASSERT(mStart < gcdMMU_MTLB_ENTRY_NUM);
++ if (*(Mmu->mtlbLogical + mStart) == 0)
++ {
++ gcsMMU_STLB_PTR stlb;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 last = (mStart == mEnd) ? sEnd : (gcdMMU_STLB_64K_ENTRY_NUM - 1);
++
++ gcmkONERROR(gckOS_Allocate(Mmu->os, sizeof(struct _gcsMMU_STLB), &pointer));
++ stlb = pointer;
++
++ stlb->mtlbEntryNum = 0;
++ stlb->next = gcvNULL;
++ stlb->physical = gcvNULL;
++ stlb->logical = gcvNULL;
++ stlb->size = gcdMMU_STLB_64K_SIZE;
++ stlb->pageCount = 0;
++
++ if (pre == gcvNULL)
++ {
++ pre = head = stlb;
++ }
++ else
++ {
++ gcmkASSERT(pre->next == gcvNULL);
++ pre->next = stlb;
++ pre = stlb;
++ }
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(Mmu->os,
++ gcvFALSE,
++ &stlb->size,
++ &stlb->physical,
++ (gctPOINTER)&stlb->logical));
++
++ gcmkONERROR(gckOS_ZeroMemory(stlb->logical, stlb->size));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Mmu->os,
++ stlb->logical,
++ &stlb->physBase));
++
++ if (stlb->physBase & (gcdMMU_STLB_64K_SIZE - 1))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ _WritePageEntry(Mmu->mtlbLogical + mStart,
++ stlb->physBase
++ /* 64KB page size */
++ | (1 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0)
++ );
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ mStart,
++ _ReadPageEntry(Mmu->mtlbLogical + mStart));
++#endif
++
++ stlb->mtlbIndex = mStart;
++ stlb->mtlbEntryNum = 1;
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): STLB: logical:%08x -> physical:%08x\n",
++ __FUNCTION__, __LINE__,
++ stlb->logical,
++ stlb->physBase);
++#endif
++
++ while (sStart <= last)
++ {
++ gcmkASSERT(!(start & gcdMMU_PAGE_64K_MASK));
++ _WritePageEntry(stlb->logical + sStart, _SetPage(start));
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert STLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ sStart,
++ _ReadPageEntry(stlb->logical + sStart));
++#endif
++ /* next page. */
++ start += gcdMMU_PAGE_64K_SIZE;
++ sStart++;
++ stlb->pageCount++;
++ }
++
++ sStart = 0;
++ ++mStart;
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ }
++
++ /* Insert the stlb into staticSTLB. */
++ if (Mmu->staticSTLB == gcvNULL)
++ {
++ Mmu->staticSTLB = head;
++ }
++ else
++ {
++ gcmkASSERT(pre == gcvNULL);
++ gcmkASSERT(pre->next == gcvNULL);
++ pre->next = Mmu->staticSTLB;
++ Mmu->staticSTLB = head;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Roll back. */
++ while (head != gcvNULL)
++ {
++ pre = head;
++ head = head->next;
++
++ if (pre->physical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ pre->physical,
++ pre->logical,
++ pre->size));
++ }
++
++ if (pre->mtlbEntryNum != 0)
++ {
++ gcmkASSERT(pre->mtlbEntryNum == 1);
++ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0);
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre));
++ }
++
++ if (mutex)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ return status;
++}
++
++static gceSTATUS
++_FindDynamicSpace(
++ IN gckMMU Mmu,
++ OUT gcsDynamicSpaceNode_PTR *Array,
++ OUT gctINT * Size
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPOINTER pointer = gcvNULL;
++ gcsDynamicSpaceNode_PTR array = gcvNULL;
++ gctINT size = 0;
++ gctINT i = 0, nodeStart = -1, nodeEntries = 0;
++
++ /* Allocate memory for the array. */
++ gcmkONERROR(gckOS_Allocate(Mmu->os,
++ gcmSIZEOF(*array) * (gcdMMU_MTLB_ENTRY_NUM / 2),
++ &pointer));
++
++ array = (gcsDynamicSpaceNode_PTR)pointer;
++
++ /* Loop all the entries. */
++ while (i < gcdMMU_MTLB_ENTRY_NUM)
++ {
++ if (!Mmu->mtlbLogical[i])
++ {
++ if (nodeStart < 0)
++ {
++ /* This is the first entry of the dynamic space. */
++ nodeStart = i;
++ nodeEntries = 1;
++ }
++ else
++ {
++ /* Other entries of the dynamic space. */
++ nodeEntries++;
++ }
++ }
++ else if (nodeStart >= 0)
++ {
++ /* Save the previous node. */
++ array[size].start = nodeStart;
++ array[size].entries = nodeEntries;
++ size++;
++
++ /* Reset the start. */
++ nodeStart = -1;
++ nodeEntries = 0;
++ }
++
++ i++;
++ }
++
++ /* Save the previous node. */
++ if (nodeStart >= 0)
++ {
++ array[size].start = nodeStart;
++ array[size].entries = nodeEntries;
++ size++;
++ }
++
++#if gcdMMU_TABLE_DUMP
++ for (i = 0; i < size; i++)
++ {
++ gckOS_Print("%s(%d): [%d]: start=%d, entries=%d.\n",
++ __FUNCTION__, __LINE__,
++ i,
++ array[i].start,
++ array[i].entries);
++ }
++#endif
++
++ *Array = array;
++ *Size = size;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (pointer != gcvNULL)
++ {
++ gckOS_Free(Mmu->os, pointer);
++ }
++
++ return status;
++}
++
++static gceSTATUS
++_SetupDynamicSpace(
++ IN gckMMU Mmu
++ )
++{
++ gceSTATUS status;
++ gcsDynamicSpaceNode_PTR nodeArray = gcvNULL;
++ gctINT i, nodeArraySize = 0;
++ gctUINT32 physical;
++ gctINT numEntries = 0;
++ gctUINT32_PTR pageTable;
++ gctBOOL acquired = gcvFALSE;
++
++ /* Find all the dynamic address space. */
++ gcmkONERROR(_FindDynamicSpace(Mmu, &nodeArray, &nodeArraySize));
++
++ /* TODO: We only use the largest one for now. */
++ for (i = 0; i < nodeArraySize; i++)
++ {
++ if (nodeArray[i].entries > numEntries)
++ {
++ Mmu->dynamicMappingStart = nodeArray[i].start;
++ numEntries = nodeArray[i].entries;
++ }
++ }
++
++ gckOS_Free(Mmu->os, (gctPOINTER)nodeArray);
++
++ Mmu->pageTableSize = numEntries * 4096;
++
++ Mmu->pageTableEntries = Mmu->pageTableSize / gcmSIZEOF(gctUINT32);
++
++ /* Construct Slave TLB. */
++ gcmkONERROR(gckOS_AllocateContiguous(Mmu->os,
++ gcvFALSE,
++ &Mmu->pageTableSize,
++ &Mmu->pageTablePhysical,
++ (gctPOINTER)&Mmu->pageTableLogical));
++
++#if gcdUSE_MMU_EXCEPTION
++ gcmkONERROR(_FillPageTable(Mmu->pageTableLogical,
++ Mmu->pageTableEntries,
++ /* Enable exception */
++ 1 << 1));
++#else
++ /* Invalidate all entries. */
++ gcmkONERROR(gckOS_ZeroMemory(Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++#endif
++
++ /* Initilization. */
++ pageTable = Mmu->pageTableLogical;
++ _WritePageEntry(pageTable, (Mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(pageTable + 1, ~0U);
++ Mmu->heapList = 0;
++ Mmu->freeNodes = gcvFALSE;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(Mmu->os,
++ Mmu->pageTableLogical,
++ &physical));
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Map to Master TLB. */
++ for (i = (gctINT)Mmu->dynamicMappingStart;
++ i < (gctINT)Mmu->dynamicMappingStart + numEntries;
++ i++)
++ {
++ _WritePageEntry(Mmu->mtlbLogical + i,
++ physical
++ /* 4KB page size */
++ | (0 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0)
++ );
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ i,
++ _ReadPageEntry(Mmu->mtlbLogical + i));
++#endif
++ physical += gcdMMU_STLB_4K_SIZE;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (Mmu->pageTableLogical)
++ {
++ /* Free the page table. */
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ (gctPOINTER) Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** _Construct
++**
++** Construct a new gckMMU object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSIZE_T MmuSize
++** Number of bytes for the page table.
++**
++** OUTPUT:
++**
++** gckMMU * Mmu
++** Pointer to a variable that receives the gckMMU object pointer.
++*/
++gceSTATUS
++_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ )
++{
++ gckOS os;
++ gckHARDWARE hardware;
++ gceSTATUS status;
++ gckMMU mmu = gcvNULL;
++ gctUINT32_PTR pageTable;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x MmuSize=%lu", Kernel, MmuSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(MmuSize > 0);
++ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Allocate memory for the gckMMU object. */
++ gcmkONERROR(gckOS_Allocate(os, sizeof(struct _gckMMU), &pointer));
++
++ mmu = pointer;
++
++ /* Initialize the gckMMU object. */
++ mmu->object.type = gcvOBJ_MMU;
++ mmu->os = os;
++ mmu->hardware = hardware;
++ mmu->pageTableMutex = gcvNULL;
++ mmu->pageTableLogical = gcvNULL;
++ mmu->mtlbLogical = gcvNULL;
++ mmu->staticSTLB = gcvNULL;
++ mmu->enabled = gcvFALSE;
++#ifdef __QNXNTO__
++ mmu->nodeList = gcvNULL;
++ mmu->nodeMutex = gcvNULL;
++#endif
++
++ /* Create the page table mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &mmu->pageTableMutex));
++
++#ifdef __QNXNTO__
++ /* Create the node list mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &mmu->nodeMutex));
++#endif
++
++ if (hardware->mmuVersion == 0)
++ {
++ mmu->pageTableSize = MmuSize;
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->pageTableSize,
++ &mmu->pageTablePhysical,
++ &pointer));
++
++ mmu->pageTableLogical = pointer;
++
++ /* Compute number of entries in page table. */
++ mmu->pageTableEntries = mmu->pageTableSize / sizeof(gctUINT32);
++
++ /* Mark all pages as free. */
++ pageTable = mmu->pageTableLogical;
++
++#if gcdMMU_CLEAR_VALUE
++ _FillPageTable(pageTable, mmu->pageTableEntries, gcdMMU_CLEAR_VALUE);
++#endif
++
++ _WritePageEntry(pageTable, (mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(pageTable + 1, ~0U);
++ mmu->heapList = 0;
++ mmu->freeNodes = gcvFALSE;
++
++ /* Set page table address. */
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(hardware, (gctPOINTER) mmu->pageTableLogical));
++ }
++ else
++ {
++ /* Allocate the 4K mode MTLB table. */
++ mmu->mtlbSize = gcdMMU_MTLB_SIZE + 64;
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->mtlbSize,
++ &mmu->mtlbPhysical,
++ &pointer));
++
++ mmu->mtlbLogical = pointer;
++
++ /* Invalid all the entries. */
++ gcmkONERROR(
++ gckOS_ZeroMemory(pointer, mmu->mtlbSize));
++ }
++
++ /* Return the gckMMU object pointer. */
++ *Mmu = mmu;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Mmu=0x%x", *Mmu);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (mmu != gcvNULL)
++ {
++ if (mmu->pageTableLogical != gcvNULL)
++ {
++ /* Free the page table. */
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(os,
++ mmu->pageTablePhysical,
++ (gctPOINTER) mmu->pageTableLogical,
++ mmu->pageTableSize));
++
++ }
++
++ if (mmu->mtlbLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(os,
++ mmu->mtlbPhysical,
++ (gctPOINTER) mmu->mtlbLogical,
++ mmu->mtlbSize));
++ }
++
++ if (mmu->pageTableMutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, mmu->pageTableMutex));
++ }
++
++#ifdef __QNXNTO__
++ if (mmu->nodeMutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, mmu->nodeMutex));
++ }
++#endif
++
++ /* Mark the gckMMU object as unknown. */
++ mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the allocates memory. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, mmu));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** _Destroy
++**
++** Destroy a gckMMU object.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++_Destroy(
++ IN gckMMU Mmu
++ )
++{
++#ifdef __QNXNTO__
++ gcuVIDMEM_NODE_PTR node, next;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++#ifdef __QNXNTO__
++ /* Free all associated virtual memory. */
++ for (node = Mmu->nodeList; node != gcvNULL; node = next)
++ {
++ next = node->Virtual.next;
++ gcmkVERIFY_OK(gckVIDMEM_Free(node));
++ }
++#endif
++
++ while (Mmu->staticSTLB != gcvNULL)
++ {
++ gcsMMU_STLB_PTR pre = Mmu->staticSTLB;
++ Mmu->staticSTLB = pre->next;
++
++ if (pre->physical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ pre->physical,
++ pre->logical,
++ pre->size));
++ }
++
++ if (pre->mtlbEntryNum != 0)
++ {
++ gcmkASSERT(pre->mtlbEntryNum == 1);
++ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0);
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): clean MTLB[%d]\n",
++ __FUNCTION__, __LINE__,
++ pre->mtlbIndex);
++#endif
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre));
++ }
++
++ if (Mmu->hardware->mmuVersion != 0)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->mtlbPhysical,
++ (gctPOINTER) Mmu->mtlbLogical,
++ Mmu->mtlbSize));
++ }
++
++ /* Free the page table. */
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ (gctPOINTER) Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++
++#ifdef __QNXNTO__
++ /* Delete the node list mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->nodeMutex));
++#endif
++
++ /* Delete the page table mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->pageTableMutex));
++
++ /* Mark the gckMMU object as unknown. */
++ Mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckMMU object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, Mmu));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckMMU_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ )
++{
++#if gcdSHARED_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG("Kernel=0x%08x", Kernel);
++
++ if (sharedPageTable == gcvNULL)
++ {
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof(struct _gcsSharedPageTable),
++ &pointer));
++ sharedPageTable = pointer;
++
++ gcmkONERROR(
++ gckOS_ZeroMemory(sharedPageTable,
++ sizeof(struct _gcsSharedPageTable)));
++
++ gcmkONERROR(_Construct(Kernel, MmuSize, &sharedPageTable->mmu));
++ }
++ else if (Kernel->hardware->mmuVersion == 0)
++ {
++ /* Set page table address. */
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(Kernel->hardware, (gctPOINTER) sharedPageTable->mmu->pageTableLogical));
++ }
++
++ *Mmu = sharedPageTable->mmu;
++
++ sharedPageTable->hardwares[sharedPageTable->reference] = Kernel->hardware;
++
++ sharedPageTable->reference++;
++
++ gcmkFOOTER_ARG("sharedPageTable->reference=%lu", sharedPageTable->reference);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (sharedPageTable)
++ {
++ if (sharedPageTable->mmu)
++ {
++ gcmkVERIFY_OK(gckMMU_Destroy(sharedPageTable->mmu));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, sharedPageTable));
++ }
++
++ gcmkFOOTER();
++ return status;
++#elif gcdMIRROR_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG("Kernel=0x%08x", Kernel);
++
++ if (mirrorPageTable == gcvNULL)
++ {
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof(struct _gcsMirrorPageTable),
++ &pointer));
++ mirrorPageTable = pointer;
++
++ gcmkONERROR(
++ gckOS_ZeroMemory(mirrorPageTable,
++ sizeof(struct _gcsMirrorPageTable)));
++
++ gcmkONERROR(
++ gckOS_CreateMutex(Kernel->os, &mirrorPageTableMutex));
++ }
++
++ gcmkONERROR(_Construct(Kernel, MmuSize, Mmu));
++
++ mirrorPageTable->mmus[mirrorPageTable->reference] = *Mmu;
++
++ mirrorPageTable->hardwares[mirrorPageTable->reference] = Kernel->hardware;
++
++ mirrorPageTable->reference++;
++
++ gcmkFOOTER_ARG("mirrorPageTable->reference=%lu", mirrorPageTable->reference);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mirrorPageTable && mirrorPageTable->reference == 0)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, mirrorPageTable));
++ }
++
++ gcmkFOOTER();
++ return status;
++#else
++ return _Construct(Kernel, MmuSize, Mmu);
++#endif
++}
++
++gceSTATUS
++gckMMU_Destroy(
++ IN gckMMU Mmu
++ )
++{
++#if gcdSHARED_PAGETABLE
++ sharedPageTable->reference--;
++
++ if (sharedPageTable->reference == 0)
++ {
++ if (sharedPageTable->mmu)
++ {
++ gcmkVERIFY_OK(_Destroy(Mmu));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, sharedPageTable));
++ }
++
++ return gcvSTATUS_OK;
++#elif gcdMIRROR_PAGETABLE
++ mirrorPageTable->reference--;
++
++ if (mirrorPageTable->reference == 0)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTable));
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTableMutex));
++ }
++
++ return _Destroy(Mmu);
++#else
++ return _Destroy(Mmu);
++#endif
++}
++
++/*******************************************************************************
++**
++** gckMMU_AllocatePages
++**
++** Allocate pages inside the page table.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** gctSIZE_T PageCount
++** Number of pages to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * PageTable
++** Pointer to a variable that receives the base address of the page
++** table.
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the hardware specific address.
++*/
++gceSTATUS
++_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gctUINT32 index = 0, previous = ~0U, left;
++ gctUINT32_PTR pageTable;
++ gctBOOL gotIt;
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageCount=%lu", Mmu, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++
++ if (PageCount > Mmu->pageTableEntries)
++ {
++ gcmkPRINT("[galcore]: %s(%d): Run out of free page entry.",
++ __FUNCTION__, __LINE__);
++
++ /* Not enough pages avaiable. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ /* Cast pointer to page table. */
++ for (pageTable = Mmu->pageTableLogical, gotIt = gcvFALSE; !gotIt;)
++ {
++ /* Walk the heap list. */
++ for (index = Mmu->heapList; !gotIt && (index < Mmu->pageTableEntries);)
++ {
++ /* Check the node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&pageTable[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Single odes are valid if we only need 1 page. */
++ if (PageCount == 1)
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ /* Move to next node. */
++ previous = index;
++ index = _ReadPageEntry(&pageTable[index]) >> 8;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ /* Test if the node has enough space. */
++ if (PageCount <= (_ReadPageEntry(&pageTable[index]) >> 8))
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ /* Move to next node. */
++ previous = index;
++ index = _ReadPageEntry(&pageTable[index + 1]);
++ }
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ /* Test if we are out of memory. */
++ if (index >= Mmu->pageTableEntries)
++ {
++ if (Mmu->freeNodes)
++ {
++ /* Time to move out the trash! */
++ gcmkONERROR(_Collect(Mmu));
++ }
++ else
++ {
++ gcmkPRINT("[galcore]: %s(%d): Run out of free page entry.",
++ __FUNCTION__, __LINE__);
++
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++ }
++
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&pageTable[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Unlink single node from free list. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&pageTable[index]) >> 8));
++ break;
++
++ case gcvMMU_FREE:
++ /* Check how many pages will be left. */
++ left = (_ReadPageEntry(&pageTable[index]) >> 8) - PageCount;
++ switch (left)
++ {
++ case 0:
++ /* The entire node is consumed, just unlink it. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&pageTable[index + 1])));
++ break;
++
++ case 1:
++ /* One page will remain. Convert the node to a single node and
++ ** advance the index. */
++ _WritePageEntry(&pageTable[index], (_ReadPageEntry(&pageTable[index + 1]) << 8) | gcvMMU_SINGLE);
++ index ++;
++ break;
++
++ default:
++ /* Enough pages remain for a new node. However, we will just adjust
++ ** the size of the current node and advance the index. */
++ _WritePageEntry(&pageTable[index], (left << 8) | gcvMMU_FREE);
++ index += left;
++ break;
++ }
++ break;
++ }
++
++ /* Mark node as used. */
++ gcmkONERROR(_FillPageTable(&pageTable[index], PageCount, gcvMMU_USED));
++
++ /* Return pointer to page table. */
++ *PageTable = &pageTable[index];
++
++ /* Build virtual address. */
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(
++ gckHARDWARE_BuildVirtualAddress(Mmu->hardware, index, 0, &address));
++ }
++ else
++ {
++ gctUINT32 masterOffset = index / gcdMMU_STLB_4K_ENTRY_NUM
++ + Mmu->dynamicMappingStart;
++ gctUINT32 slaveOffset = index % gcdMMU_STLB_4K_ENTRY_NUM;
++
++ address = (masterOffset << gcdMMU_MTLB_SHIFT)
++ | (slaveOffset << gcdMMU_STLB_4K_SHIFT);
++ }
++
++ if (Address != gcvNULL)
++ {
++ *Address = address;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*PageTable=0x%x *Address=%08x",
++ *PageTable, gcmOPT_VALUE(Address));
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (mutex)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckMMU_FreePages
++**
++** Free pages inside the page table.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** gctPOINTER PageTable
++** Base address of the page table to free.
++**
++** gctSIZE_T PageCount
++** Number of pages to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32_PTR pageTable;
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=%lu",
++ Mmu, PageTable, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ /* Convert the pointer. */
++ pageTable = (gctUINT32_PTR) PageTable;
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++#if gcdMMU_CLEAR_VALUE
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ _FillPageTable(pageTable, PageCount, gcdMMU_CLEAR_VALUE);
++ }
++#endif
++
++ if (PageCount == 1)
++ {
++ /* Single page node. */
++ _WritePageEntry(pageTable,
++ (~((1U<<8)-1)) | gcvMMU_SINGLE
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ | 1 << 1
++#endif
++ );
++ }
++ else
++ {
++ /* Mark the node as free. */
++ _WritePageEntry(pageTable,
++ (PageCount << 8) | gcvMMU_FREE
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ | 1 << 1
++#endif
++ );
++ _WritePageEntry(pageTable + 1, ~0U);
++
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ gcmkVERIFY_OK(_FillPageTable(pageTable + 2, PageCount - 2, 1 << 1));
++#endif
++ }
++
++ /* We have free nodes. */
++ Mmu->freeNodes = gcvTRUE;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pageTable;
++ gctUINT32 address;
++ gctINT i;
++ gckMMU mmu;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL allocated = gcvFALSE;
++
++ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE);
++ acquired = gcvTRUE;
++
++ /* Allocate page table for current MMU. */
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ if (Mmu == mirrorPageTable->mmus[i])
++ {
++ gcmkONERROR(_AllocatePages(Mmu, PageCount, PageTable, Address));
++ allocated = gcvTRUE;
++ }
++ }
++
++ /* Allocate page table for other MMUs. */
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (Mmu != mmu)
++ {
++ gcmkONERROR(_AllocatePages(mmu, PageCount, &pageTable, &address));
++ gcmkASSERT(address == *Address);
++ }
++ }
++
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++ acquired = gcvFALSE;
++
++ return gcvSTATUS_OK;
++OnError:
++
++ if (allocated)
++ {
++ /* Page tables for multiple GPU always keep the same. So it is impossible
++ * the fist one allocates successfully but others fail.
++ */
++ gcmkASSERT(0);
++ }
++
++ if (acquired)
++ {
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++ }
++
++ return status;
++#else
++ return _AllocatePages(Mmu, PageCount, PageTable, Address);
++#endif
++}
++
++gceSTATUS
++gckMMU_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gctINT i;
++ gctUINT32 offset;
++ gckMMU mmu;
++
++ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE);
++
++ gcmkVERIFY_OK(_FreePages(Mmu, PageTable, PageCount));
++
++ offset = (gctUINT32)PageTable - (gctUINT32)Mmu->pageTableLogical;
++
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (mmu != Mmu)
++ {
++ gcmkVERIFY_OK(_FreePages(mmu, mmu->pageTableLogical + offset/4, PageCount));
++ }
++ }
++
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++
++ return gcvSTATUS_OK;
++#else
++ return _FreePages(Mmu, PageTable, PageCount);
++#endif
++}
++
++gceSTATUS
++gckMMU_Enable(
++ IN gckMMU Mmu,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize
++ )
++{
++ gceSTATUS status;
++#if gcdSHARED_PAGETABLE
++ gckHARDWARE hardware;
++ gctINT i;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++#if gcdSHARED_PAGETABLE
++ if (Mmu->enabled)
++ {
++ gcmkFOOTER_ARG("Status=%d", gcvSTATUS_SKIP);
++ return gcvSTATUS_SKIP;
++ }
++#endif
++
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ /* Success. */
++ gcmkFOOTER_ARG("Status=%d", gcvSTATUS_SKIP);
++ return gcvSTATUS_SKIP;
++ }
++ else
++ {
++ if (PhysSize != 0)
++ {
++ gcmkONERROR(_FillFlatMapping(
++ Mmu,
++ PhysBaseAddr,
++ PhysSize
++ ));
++ }
++
++ gcmkONERROR(_SetupDynamicSpace(Mmu));
++
++#if gcdSHARED_PAGETABLE
++ for(i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ hardware = sharedPageTable->hardwares[i];
++ if (hardware != gcvNULL)
++ {
++ gcmkONERROR(
++ gckHARDWARE_SetMMUv2(
++ hardware,
++ gcvTRUE,
++ Mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ gcvFALSE
++ ));
++ }
++ }
++#else
++ gcmkONERROR(
++ gckHARDWARE_SetMMUv2(
++ Mmu->hardware,
++ gcvTRUE,
++ Mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ gcvFALSE
++ ));
++#endif
++
++ Mmu->enabled = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_SetPage(
++ IN gckMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gctUINT32_PTR pageEntry;
++ gctINT i;
++ gckMMU mmu;
++ gctUINT32 offset = (gctUINT32)PageEntry - (gctUINT32)Mmu->pageTableLogical;
++#endif
++
++ gctUINT32 data;
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL);
++ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF));
++
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ data = PageAddress;
++ }
++ else
++ {
++ data = _SetPage(PageAddress);
++ }
++
++ _WritePageEntry(PageEntry, data);
++
++#if gcdMIRROR_PAGETABLE
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (mmu != Mmu)
++ {
++ pageEntry = mmu->pageTableLogical + offset / 4;
++
++ if (mmu->hardware->mmuVersion == 0)
++ {
++ _WritePageEntry(pageEntry, PageAddress);
++ }
++ else
++ {
++ _WritePageEntry(pageEntry, _SetPage(PageAddress));
++ }
++ }
++
++ }
++#endif
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#ifdef __QNXNTO__
++gceSTATUS
++gckMMU_InsertNode(
++ IN gckMMU Mmu,
++ IN gcuVIDMEM_NODE_PTR Node)
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++
++ gcmkHEADER_ARG("Mmu=0x%x Node=0x%x", Mmu, Node);
++
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ Node->Virtual.next = Mmu->nodeList;
++ Mmu->nodeList = Node;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutex)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_RemoveNode(
++ IN gckMMU Mmu,
++ IN gcuVIDMEM_NODE_PTR Node)
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gcuVIDMEM_NODE_PTR *iter;
++
++ gcmkHEADER_ARG("Mmu=0x%x Node=0x%x", Mmu, Node);
++
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ for (iter = &Mmu->nodeList; *iter; iter = &(*iter)->Virtual.next)
++ {
++ if (*iter == Node)
++ {
++ *iter = Node->Virtual.next;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutex)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_FreeHandleMemory(
++ IN gckKERNEL Kernel,
++ IN gckMMU Mmu,
++ IN gctUINT32 Pid
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcuVIDMEM_NODE_PTR curr, next;
++
++ gcmkHEADER_ARG("Kernel=0x%x, Mmu=0x%x Pid=%u", Kernel, Mmu, Pid);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->nodeMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ for (curr = Mmu->nodeList; curr != gcvNULL; curr = next)
++ {
++ next = curr->Virtual.next;
++
++ if (curr->Virtual.processID == Pid)
++ {
++ while (curr->Virtual.unlockPendings[Kernel->core] == 0 && curr->Virtual.lockeds[Kernel->core] > 0)
++ {
++ gcmkONERROR(gckVIDMEM_Unlock(Kernel, curr, gcvSURF_TYPE_UNKNOWN, gcvNULL));
++ }
++
++ gcmkVERIFY_OK(gckVIDMEM_Free(curr));
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->nodeMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckMMU_Flush(
++ IN gckMMU Mmu
++ )
++{
++ gckHARDWARE hardware;
++#if gcdSHARED_PAGETABLE
++ gctINT i;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ continue;
++ }
++#endif
++ hardware = sharedPageTable->hardwares[i];
++ if (hardware)
++ {
++ /* Notify cores who use this page table. */
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++ }
++ }
++#elif gcdMIRROR_PAGETABLE
++ gctINT i;
++ for (i = 0; i < mirrorPageTable->reference; i++)
++ {
++ hardware = mirrorPageTable->hardwares[i];
++
++ /* Notify cores who use this page table. */
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++ }
++#else
++ hardware = Mmu->hardware;
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckMMU_DumpPageTableEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ )
++{
++ gctUINT32_PTR pageTable;
++ gctUINT32 index;
++ gctUINT32 mtlb, stlb;
++
++ gcmkHEADER_ARG("Mmu=0x%08X Address=0x%08X", Mmu, Address);
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkASSERT(Mmu->hardware->mmuVersion > 0);
++
++ mtlb = (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ stlb = (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++
++ if (Address >= 0x80000000)
++ {
++ pageTable = Mmu->pageTableLogical;
++
++ index = (mtlb - Mmu->dynamicMappingStart)
++ * gcdMMU_STLB_4K_ENTRY_NUM
++ + stlb;
++
++ gcmkPRINT(" Page table entry = 0x%08X", _ReadPageEntry(pageTable + index));
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************
++****************************** T E S T C O D E ******************************
++******************************************************************************/
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,522 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_MMU
++
++/*******************************************************************************
++**
++** gckVGMMU_Construct
++**
++** Construct a new gckVGMMU object.
++**
++** INPUT:
++**
++** gckVGKERNEL Kernel
++** Pointer to an gckVGKERNEL object.
++**
++** gctSIZE_T MmuSize
++** Number of bytes for the page table.
++**
++** OUTPUT:
++**
++** gckVGMMU * Mmu
++** Pointer to a variable that receives the gckVGMMU object pointer.
++*/
++gceSTATUS gckVGMMU_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckVGMMU * Mmu
++ )
++{
++ gckOS os;
++ gckVGHARDWARE hardware;
++ gceSTATUS status;
++ gckVGMMU mmu;
++ gctUINT32 * pageTable;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x MmuSize=0x%x Mmu=0x%x", Kernel, MmuSize, Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(MmuSize > 0);
++ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckVGHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Allocate memory for the gckVGMMU object. */
++ status = gckOS_Allocate(os, sizeof(struct _gckVGMMU), (gctPOINTER *) &mmu);
++
++ if (status < 0)
++ {
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not allocate gckVGMMU object.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Initialize the gckVGMMU object. */
++ mmu->object.type = gcvOBJ_MMU;
++ mmu->os = os;
++ mmu->hardware = hardware;
++
++ /* Create the mutex. */
++ status = gckOS_CreateMutex(os, &mmu->mutex);
++
++ if (status < 0)
++ {
++ /* Roll back. */
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ gcmkFOOTER();
++ /* Error. */
++ return status;
++ }
++
++ /* Allocate the page table. */
++ mmu->pageTableSize = MmuSize;
++ status = gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->pageTableSize,
++ &mmu->pageTablePhysical,
++ &mmu->pageTableLogical);
++
++ if (status < 0)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex));
++
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not allocate page table.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Compute number of entries in page table. */
++ mmu->entryCount = mmu->pageTableSize / sizeof(gctUINT32);
++ mmu->entry = 0;
++
++ /* Mark the entire page table as available. */
++ pageTable = (gctUINT32 *) mmu->pageTableLogical;
++ for (i = 0; i < mmu->entryCount; i++)
++ {
++ pageTable[i] = (gctUINT32)~0;
++ }
++
++ /* Set page table address. */
++ status = gckVGHARDWARE_SetMMU(hardware, mmu->pageTableLogical);
++
++ if (status < 0)
++ {
++ /* Free the page table. */
++ gcmkVERIFY_OK(gckOS_FreeContiguous(mmu->os,
++ mmu->pageTablePhysical,
++ mmu->pageTableLogical,
++ mmu->pageTableSize));
++
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex));
++
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not program page table.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Return the gckVGMMU object pointer. */
++ *Mmu = mmu;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): %u entries at %p.(0x%08X)\n",
++ __FUNCTION__, __LINE__,
++ mmu->entryCount,
++ mmu->pageTableLogical,
++ mmu->pageTablePhysical
++ );
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_Destroy
++**
++** Destroy a nAQMMU object.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGMMU_Destroy(
++ IN gckVGMMU Mmu
++ )
++{
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ /* Free the page table. */
++ gcmkVERIFY_OK(gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->mutex));
++
++ /* Mark the gckVGMMU object as unknown. */
++ Mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGMMU object. */
++ gcmkVERIFY_OK(gckOS_Free(Mmu->os, Mmu));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_AllocatePages
++**
++** Allocate pages inside the page table.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** gctSIZE_T PageCount
++** Number of pages to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * PageTable
++** Pointer to a variable that receives the base address of the page
++** table.
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the hardware specific address.
++*/
++gceSTATUS gckVGMMU_AllocatePages(
++ IN gckVGMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctUINT32 tail, index, i;
++ gctUINT32 * table;
++ gctBOOL allocated = gcvFALSE;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageCount=0x%x PageTable=0x%x Address=0x%x",
++ Mmu, PageCount, PageTable, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ if (PageCount > Mmu->entryCount)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): page table too small for %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ gcmkFOOTER_NO();
++ /* Not enough pages avaiable. */
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Grab the mutex. */
++ status = gckOS_AcquireMutex(Mmu->os, Mmu->mutex, gcvINFINITE);
++
++ if (status < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): could not acquire mutex.\n"
++ ,__FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ /* Error. */
++ return status;
++ }
++
++ /* Compute the tail for this allocation. */
++ tail = Mmu->entryCount - PageCount;
++
++ /* Walk all entries until we find enough slots. */
++ for (index = Mmu->entry; index <= tail;)
++ {
++ /* Access page table. */
++ table = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ /* See if all slots are available. */
++ for (i = 0; i < PageCount; i++, table++)
++ {
++ if (*table != ~0)
++ {
++ /* Start from next slot. */
++ index += i + 1;
++ break;
++ }
++ }
++
++ if (i == PageCount)
++ {
++ /* Bail out if we have enough page entries. */
++ allocated = gcvTRUE;
++ break;
++ }
++ }
++
++ if (!allocated)
++ {
++ if (status >= 0)
++ {
++ /* Walk all entries until we find enough slots. */
++ for (index = 0; index <= tail;)
++ {
++ /* Access page table. */
++ table = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ /* See if all slots are available. */
++ for (i = 0; i < PageCount; i++, table++)
++ {
++ if (*table != ~0)
++ {
++ /* Start from next slot. */
++ index += i + 1;
++ break;
++ }
++ }
++
++ if (i == PageCount)
++ {
++ /* Bail out if we have enough page entries. */
++ allocated = gcvTRUE;
++ break;
++ }
++ }
++ }
++ }
++
++ if (!allocated && (status >= 0))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): not enough free pages for %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ /* Not enough empty slots available. */
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ if (status >= 0)
++ {
++ /* Build virtual address. */
++ status = gckVGHARDWARE_BuildVirtualAddress(Mmu->hardware,
++ index,
++ 0,
++ Address);
++
++ if (status >= 0)
++ {
++ /* Update current entry into page table. */
++ Mmu->entry = index + PageCount;
++
++ /* Return pointer to page table. */
++ *PageTable = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): allocated %u pages at index %u (0x%08X) @ %p.\n",
++ __FUNCTION__, __LINE__,
++ PageCount,
++ index,
++ *Address,
++ *PageTable
++ );
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->mutex));
++ gcmkFOOTER();
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_FreePages
++**
++** Free pages inside the page table.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** gctPOINTER PageTable
++** Base address of the page table to free.
++**
++** gctSIZE_T PageCount
++** Number of pages to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGMMU_FreePages(
++ IN gckVGMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32 * table;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=0x%x",
++ Mmu, PageTable, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): freeing %u pages at index %u @ %p.\n",
++ __FUNCTION__, __LINE__,
++ PageCount,
++ ((gctUINT32 *) PageTable - (gctUINT32 *) Mmu->pageTableLogical),
++ PageTable
++ );
++
++ /* Convert pointer. */
++ table = (gctUINT32 *) PageTable;
++
++ /* Mark the page table entries as available. */
++ while (PageCount-- > 0)
++ {
++ *table++ = (gctUINT32)~0;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGMMU_SetPage(
++ IN gckVGMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ )
++{
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL);
++ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF));
++
++ *PageEntry = PageAddress;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGMMU_Flush(
++ IN gckVGMMU Mmu
++ )
++{
++ gckVGHARDWARE hardware;
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ hardware = Mmu->hardware;
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,347 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_POWER
++
++/******************************************************************************\
++************************ Dynamic Voltage Frequency Setting *********************
++\******************************************************************************/
++#if gcdDVFS
++static gctUINT32
++_GetLoadHistory(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Select,
++ IN gctUINT32 Index
++)
++{
++ return Dvfs->loads[Index];
++}
++
++static void
++_IncreaseScale(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Load,
++ OUT gctUINT8 *Scale
++ )
++{
++ if (Dvfs->currentScale < 32)
++ {
++ *Scale = Dvfs->currentScale + 8;
++ }
++ else
++ {
++ *Scale = Dvfs->currentScale + 8;
++ *Scale = gcmMIN(64, *Scale);
++ }
++}
++
++static void
++_RecordFrequencyHistory(
++ gckDVFS Dvfs,
++ gctUINT32 Frequency
++ )
++{
++ gctUINT32 i = 0;
++
++ struct _FrequencyHistory *history = Dvfs->frequencyHistory;
++
++ for (i = 0; i < 16; i++)
++ {
++ if (history->frequency == Frequency)
++ {
++ break;
++ }
++
++ if (history->frequency == 0)
++ {
++ history->frequency = Frequency;
++ break;
++ }
++
++ history++;
++ }
++
++ if (i < 16)
++ {
++ history->count++;
++ }
++}
++
++static gctUINT32
++_GetFrequencyHistory(
++ gckDVFS Dvfs,
++ gctUINT32 Frequency
++ )
++{
++ gctUINT32 i = 0;
++
++ struct _FrequencyHistory * history = Dvfs->frequencyHistory;
++
++ for (i = 0; i < 16; i++)
++ {
++ if (history->frequency == Frequency)
++ {
++ break;
++ }
++
++ history++;
++ }
++
++ if (i < 16)
++ {
++ return history->count;
++ }
++
++ return 0;
++}
++
++static void
++_Policy(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Load,
++ OUT gctUINT8 *Scale
++ )
++{
++ gctUINT8 load[4], nextLoad;
++ gctUINT8 scale;
++
++ /* Last 4 history. */
++ load[0] = (Load & 0xFF);
++ load[1] = (Load & 0xFF00) >> 8;
++ load[2] = (Load & 0xFF0000) >> 16;
++ load[3] = (Load & 0xFF000000) >> 24;
++
++ /* Determine target scale. */
++ if (load[0] > 54)
++ {
++ _IncreaseScale(Dvfs, Load, &scale);
++ }
++ else
++ {
++ nextLoad = (load[0] + load[1] + load[2] + load[3])/4;
++
++ scale = Dvfs->currentScale * (nextLoad) / 54;
++
++ scale = gcmMAX(1, scale);
++ scale = gcmMIN(64, scale);
++ }
++
++ Dvfs->totalConfig++;
++
++ Dvfs->loads[(load[0]-1)/8]++;
++
++ *Scale = scale;
++
++
++ if (Dvfs->totalConfig % 100 == 0)
++ {
++ gcmkPRINT("=======================================================");
++ gcmkPRINT("GPU Load: %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d",
++ 8, 16, 24, 32, 40, 48, 56, 64);
++ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d",
++ _GetLoadHistory(Dvfs,2, 0),
++ _GetLoadHistory(Dvfs,2, 1),
++ _GetLoadHistory(Dvfs,2, 2),
++ _GetLoadHistory(Dvfs,2, 3),
++ _GetLoadHistory(Dvfs,2, 4),
++ _GetLoadHistory(Dvfs,2, 5),
++ _GetLoadHistory(Dvfs,2, 6),
++ _GetLoadHistory(Dvfs,2, 7)
++ );
++
++ gcmkPRINT("Frequency(MHz) %-8d %-8d %-8d %-8d %-8d",
++ 58, 120, 240, 360, 480);
++ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d",
++ _GetFrequencyHistory(Dvfs, 58),
++ _GetFrequencyHistory(Dvfs,120),
++ _GetFrequencyHistory(Dvfs,240),
++ _GetFrequencyHistory(Dvfs,360),
++ _GetFrequencyHistory(Dvfs,480)
++ );
++ }
++}
++
++static void
++_TimerFunction(
++ gctPOINTER Data
++ )
++{
++ gceSTATUS status;
++ gckDVFS dvfs = (gckDVFS) Data;
++ gckHARDWARE hardware = dvfs->hardware;
++ gctUINT32 value;
++ gctUINT32 frequency;
++ gctUINT8 scale;
++ gctUINT32 t1, t2, consumed;
++
++ gckOS_GetTicks(&t1);
++
++ gcmkONERROR(gckHARDWARE_QueryLoad(hardware, &value));
++
++ /* determine target sacle. */
++ _Policy(dvfs, value, &scale);
++
++ /* Set frequency and voltage. */
++ gcmkONERROR(gckOS_SetGPUFrequency(hardware->os, hardware->core, scale));
++
++ /* Query real frequency. */
++ gcmkONERROR(
++ gckOS_QueryGPUFrequency(hardware->os,
++ hardware->core,
++ &frequency,
++ &dvfs->currentScale));
++
++ _RecordFrequencyHistory(dvfs, frequency);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_POWER,
++ "Current frequency = %d",
++ frequency);
++
++ /* Set period. */
++ gcmkONERROR(gckHARDWARE_SetDVFSPeroid(hardware, frequency));
++
++OnError:
++ /* Determine next querying time. */
++ gckOS_GetTicks(&t2);
++
++ consumed = gcmMIN(((long)t2 - (long)t1), 5);
++
++ if (dvfs->stop == gcvFALSE)
++ {
++ gcmkVERIFY_OK(gckOS_StartTimer(hardware->os,
++ dvfs->timer,
++ dvfs->pollingTime - consumed));
++ }
++
++ return;
++}
++
++gceSTATUS
++gckDVFS_Construct(
++ IN gckHARDWARE Hardware,
++ OUT gckDVFS * Dvfs
++ )
++{
++ gceSTATUS status;
++ gctPOINTER pointer;
++ gckDVFS dvfs = gcvNULL;
++ gckOS os = Hardware->os;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ /* Allocate a gckDVFS manager. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckDVFS), &pointer));
++
++ gckOS_ZeroMemory(pointer, gcmSIZEOF(struct _gckDVFS));
++
++ dvfs = pointer;
++
++ /* Initialization. */
++ dvfs->hardware = Hardware;
++ dvfs->pollingTime = gcdDVFS_POLLING_TIME;
++ dvfs->os = Hardware->os;
++ dvfs->currentScale = 64;
++
++ /* Create a polling timer. */
++ gcmkONERROR(gckOS_CreateTimer(os, _TimerFunction, pointer, &dvfs->timer));
++
++ /* Initialize frequency and voltage adjustment helper. */
++ gcmkONERROR(gckOS_PrepareGPUFrequency(os, Hardware->core));
++
++ /* Return result. */
++ *Dvfs = dvfs;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (dvfs)
++ {
++ if (dvfs->timer)
++ {
++ gcmkVERIFY_OK(gckOS_DestroyTimer(os, dvfs->timer));
++ }
++
++ gcmkOS_SAFE_FREE(os, dvfs);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckDVFS_Destroy(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ /* Deinitialize helper fuunction. */
++ gcmkVERIFY_OK(gckOS_FinishGPUFrequency(Dvfs->os, Dvfs->hardware->core));
++
++ /* DestroyTimer. */
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Dvfs->os, Dvfs->timer));
++
++ gcmkOS_SAFE_FREE(Dvfs->os, Dvfs);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDVFS_Start(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ gckHARDWARE_InitDVFS(Dvfs->hardware);
++
++ Dvfs->stop = gcvFALSE;
++
++ gckOS_StartTimer(Dvfs->os, Dvfs->timer, Dvfs->pollingTime);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDVFS_Stop(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ Dvfs->stop = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,29 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_precomp_h_
++#define __gc_hal_kernel_precomp_h_
++
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel.h"
++
++#endif /* __gc_hal_kernel_precomp_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,893 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#define ENABLE_VG_TRY_VIRTUAL_MEMORY 0
++
++#define _GC_OBJ_ZONE gcvZONE_VG
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_Construct
++**
++** Construct a new gckKERNEL object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN gctPOINTER Context
++** Pointer to a driver defined context.
++**
++** OUTPUT:
++**
++** gckKERNEL * Kernel
++** Pointer to a variable that will hold the pointer to the gckKERNEL
++** object.
++*/
++gceSTATUS gckVGKERNEL_Construct(
++ IN gckOS Os,
++ IN gctPOINTER Context,
++ IN gckKERNEL inKernel,
++ OUT gckVGKERNEL * Kernel
++ )
++{
++ gceSTATUS status;
++ gckVGKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++
++ do
++ {
++ /* Allocate the gckKERNEL object. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Os,
++ sizeof(struct _gckVGKERNEL),
++ (gctPOINTER *) &kernel
++ ));
++
++ /* Initialize the gckKERNEL object. */
++ kernel->object.type = gcvOBJ_KERNEL;
++ kernel->os = Os;
++ kernel->context = Context;
++ kernel->hardware = gcvNULL;
++ kernel->interrupt = gcvNULL;
++ kernel->command = gcvNULL;
++ kernel->mmu = gcvNULL;
++ kernel->kernel = inKernel;
++
++ /* Construct the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckVGHARDWARE_Construct(
++ Os, &kernel->hardware
++ ));
++
++ /* Set pointer to gckKERNEL object in gckVGHARDWARE object. */
++ kernel->hardware->kernel = kernel;
++
++ /* Construct the gckVGINTERRUPT object. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Construct(
++ kernel, &kernel->interrupt
++ ));
++
++ /* Construct the gckVGCOMMAND object. */
++ gcmkERR_BREAK(gckVGCOMMAND_Construct(
++ kernel, gcmKB2BYTES(8), gcmKB2BYTES(2), &kernel->command
++ ));
++
++ /* Construct the gckVGMMU object. */
++ gcmkERR_BREAK(gckVGMMU_Construct(
++ kernel, gcmKB2BYTES(32), &kernel->mmu
++ ));
++
++ /* Return pointer to the gckKERNEL object. */
++ *Kernel = kernel;
++
++ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (kernel != gcvNULL)
++ {
++ if (kernel->mmu != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGMMU_Destroy(kernel->mmu));
++ }
++
++ if (kernel->command != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGCOMMAND_Destroy(kernel->command));
++ }
++
++ if (kernel->interrupt != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGINTERRUPT_Destroy(kernel->interrupt));
++ }
++
++ if (kernel->hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGHARDWARE_Destroy(kernel->hardware));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(Os, kernel));
++ }
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Destroy
++**
++** Destroy an gckKERNEL object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGKERNEL_Destroy(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ do
++ {
++ /* Destroy the gckVGMMU object. */
++ if (Kernel->mmu != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGMMU_Destroy(Kernel->mmu));
++ Kernel->mmu = gcvNULL;
++ }
++
++ /* Destroy the gckVGCOMMAND object. */
++ if (Kernel->command != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_Destroy(Kernel->command));
++ Kernel->command = gcvNULL;
++ }
++
++ /* Destroy the gckVGINTERRUPT object. */
++ if (Kernel->interrupt != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGINTERRUPT_Destroy(Kernel->interrupt));
++ Kernel->interrupt = gcvNULL;
++ }
++
++ /* Destroy the gckVGHARDWARE object. */
++ if (Kernel->hardware != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGHARDWARE_Destroy(Kernel->hardware));
++ Kernel->hardware = gcvNULL;
++ }
++
++ /* Mark the gckKERNEL object as unknown. */
++ Kernel->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckKERNEL object. */
++ gcmkERR_BREAK(gckOS_Free(Kernel->os, Kernel));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_AllocateLinearMemory
++**
++** Function walks all required memory pools and allocates the requested
++** amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcePOOL * Pool
++** Pointer the desired memory pool.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** gctSIZE_T Alignment
++** Required buffer alignment.
++**
++** gceSURF_TYPE Type
++** Surface type.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to the actual pool where the memory was allocated.
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Allocated node.
++*/
++gceSTATUS
++gckKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gcePOOL pool;
++ gceSTATUS status;
++ gckVIDMEM videoMemory;
++
++ /* Get initial pool. */
++ switch (pool = *Pool)
++ {
++ case gcvPOOL_DEFAULT:
++ case gcvPOOL_LOCAL:
++ pool = gcvPOOL_LOCAL_INTERNAL;
++ break;
++
++ case gcvPOOL_UNIFIED:
++ pool = gcvPOOL_SYSTEM;
++ break;
++
++ default:
++ break;
++ }
++
++ do
++ {
++ /* Verify the number of bytes to allocate. */
++ if (Bytes == 0)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ /* Create a gcuVIDMEM_NODE for virtual memory. */
++ gcmkERR_BREAK(gckVIDMEM_ConstructVirtual(Kernel, gcvFALSE, Bytes, Node));
++
++ /* Success. */
++ break;
++ }
++
++ else
++ {
++ /* Get pointer to gckVIDMEM object for pool. */
++ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory);
++
++ if (status == gcvSTATUS_OK)
++ {
++ /* Allocate memory. */
++ status = gckVIDMEM_AllocateLinear(videoMemory,
++ Bytes,
++ Alignment,
++ Type,
++ Node);
++
++ if (status == gcvSTATUS_OK)
++ {
++ /* Memory allocated. */
++ break;
++ }
++ }
++ }
++
++ if (pool == gcvPOOL_LOCAL_INTERNAL)
++ {
++ /* Advance to external memory. */
++ pool = gcvPOOL_LOCAL_EXTERNAL;
++ }
++ else if (pool == gcvPOOL_LOCAL_EXTERNAL)
++ {
++ /* Advance to contiguous system memory. */
++ pool = gcvPOOL_SYSTEM;
++ }
++ else if (pool == gcvPOOL_SYSTEM)
++ {
++ /* Advance to virtual memory. */
++#if ENABLE_VG_TRY_VIRTUAL_MEMORY
++ pool = gcvPOOL_VIRTUAL;
++#else
++ /*VG non-contiguous memory support is not ready yet, disable it temporary*/
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++#endif
++ }
++ else
++ {
++ /* Out of pools. */
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++ }
++ /* Loop only for multiple selection pools. */
++ while ((*Pool == gcvPOOL_DEFAULT)
++ || (*Pool == gcvPOOL_LOCAL)
++ || (*Pool == gcvPOOL_UNIFIED)
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Return pool used for allocation. */
++ *Pool = pool;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Dispatch
++**
++** Dispatch a command received from the user HAL layer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS gckVGKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE * kernelInterface = Interface;
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 processID;
++ gckKERNEL kernel = Kernel;
++ gctPOINTER info = gcvNULL;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctPOINTER logical = gcvNULL;
++ gctSIZE_T bytes = 0;
++
++ gcmkHEADER_ARG("Kernel=0x%x Interface=0x%x ", Kernel, Interface);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Dispatch on command. */
++ switch (Interface->command)
++ {
++ case gcvHAL_QUERY_VIDEO_MEMORY:
++ /* Query video memory size. */
++ gcmkERR_BREAK(gckKERNEL_QueryVideoMemory(
++ Kernel, kernelInterface
++ ));
++ break;
++
++ case gcvHAL_QUERY_CHIP_IDENTITY:
++ /* Query chip identity. */
++ gcmkERR_BREAK(gckVGHARDWARE_QueryChipIdentity(
++ Kernel->vg->hardware,
++ &kernelInterface->u.QueryChipIdentity.chipModel,
++ &kernelInterface->u.QueryChipIdentity.chipRevision,
++ &kernelInterface->u.QueryChipIdentity.chipFeatures,
++ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures,
++ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures2
++ ));
++ break;
++
++ case gcvHAL_QUERY_COMMAND_BUFFER:
++ /* Query command buffer information. */
++ gcmkERR_BREAK(gckKERNEL_QueryCommandBuffer(
++ Kernel,
++ &kernelInterface->u.QueryCommandBuffer.information
++ ));
++ break;
++ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY:
++ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes;
++ /* Allocate non-paged memory. */
++ gcmkERR_BREAK(gckOS_AllocateContiguous(
++ Kernel->os,
++ gcvTRUE,
++ &bytes,
++ &physical,
++ &logical
++ ));
++
++ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes;
++ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++ break;
++
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical);
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkERR_BREAK(gckOS_UnmapUserLogical(
++ Kernel->os,
++ physical,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ /* Free non-paged memory. */
++ gcmkERR_BREAK(gckOS_FreeNonPagedMemory(
++ Kernel->os,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ physical,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY:
++ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes;
++ /* Allocate contiguous memory. */
++ gcmkERR_BREAK(gckOS_AllocateContiguous(
++ Kernel->os,
++ gcvTRUE,
++ &bytes,
++ &physical,
++ &logical
++ ));
++
++ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes;
++ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical);
++ /* Unmap user logical out of physical memory first. */
++ gcmkERR_BREAK(gckOS_UnmapUserLogical(
++ Kernel->os,
++ physical,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ /* Free contiguous memory. */
++ gcmkERR_BREAK(gckOS_FreeContiguous(
++ Kernel->os,
++ physical,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical),
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_VIDEO_MEMORY:
++ {
++ gctSIZE_T bytes;
++ gctUINT32 bitsPerPixel;
++ gctUINT32 bits;
++
++ /* Align width and height to tiles. */
++ gcmkERR_BREAK(gckVGHARDWARE_AlignToTile(
++ Kernel->vg->hardware,
++ kernelInterface->u.AllocateVideoMemory.type,
++ &kernelInterface->u.AllocateVideoMemory.width,
++ &kernelInterface->u.AllocateVideoMemory.height
++ ));
++
++ /* Convert format into bytes per pixel and bytes per tile. */
++ gcmkERR_BREAK(gckVGHARDWARE_ConvertFormat(
++ Kernel->vg->hardware,
++ kernelInterface->u.AllocateVideoMemory.format,
++ &bitsPerPixel,
++ gcvNULL
++ ));
++
++ /* Compute number of bits for the allocation. */
++ bits
++ = kernelInterface->u.AllocateVideoMemory.width
++ * kernelInterface->u.AllocateVideoMemory.height
++ * kernelInterface->u.AllocateVideoMemory.depth
++ * bitsPerPixel;
++
++ /* Compute number of bytes for the allocation. */
++ bytes = gcmALIGN(bits, 8) / 8;
++
++ /* Allocate memory. */
++ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory(
++ Kernel,
++ &kernelInterface->u.AllocateVideoMemory.pool,
++ bytes,
++ 64,
++ kernelInterface->u.AllocateVideoMemory.type,
++ &node
++ ));
++
++ kernelInterface->u.AllocateVideoMemory.node = gcmPTR_TO_UINT64(node);
++ }
++ break;
++
++ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY:
++ /* Allocate memory. */
++ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory(
++ Kernel,
++ &kernelInterface->u.AllocateLinearVideoMemory.pool,
++ kernelInterface->u.AllocateLinearVideoMemory.bytes,
++ kernelInterface->u.AllocateLinearVideoMemory.alignment,
++ kernelInterface->u.AllocateLinearVideoMemory.type,
++ &node
++ ));
++
++ gcmkERR_BREAK(gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ node,
++ gcvNULL,
++ kernelInterface->u.AllocateLinearVideoMemory.bytes
++ ));
++
++ kernelInterface->u.AllocateLinearVideoMemory.node = gcmPTR_TO_UINT64(node);
++ break;
++
++ case gcvHAL_FREE_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(Interface->u.FreeVideoMemory.node);
++#ifdef __QNXNTO__
++ /* Unmap the video memory */
++
++ if ((node->VidMem.memory->object.type == gcvOBJ_VIDMEM) &&
++ (node->VidMem.logical != gcvNULL))
++ {
++ gckKERNEL_UnmapVideoMemory(Kernel,
++ node->VidMem.logical,
++ processID,
++ node->VidMem.bytes);
++ node->VidMem.logical = gcvNULL;
++ }
++#endif /* __QNXNTO__ */
++
++ /* Free video memory. */
++ gcmkERR_BREAK(gckVIDMEM_Free(
++ node
++ ));
++
++ gcmkERR_BREAK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ node
++ ));
++
++ break;
++
++ case gcvHAL_MAP_MEMORY:
++ /* Map memory. */
++ gcmkERR_BREAK(gckKERNEL_MapMemory(
++ Kernel,
++ gcmINT2PTR(kernelInterface->u.MapMemory.physical),
++ (gctSIZE_T) kernelInterface->u.MapMemory.bytes,
++ &logical
++ ));
++ kernelInterface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical);
++ break;
++
++ case gcvHAL_UNMAP_MEMORY:
++ /* Unmap memory. */
++ gcmkERR_BREAK(gckKERNEL_UnmapMemory(
++ Kernel,
++ gcmINT2PTR(kernelInterface->u.MapMemory.physical),
++ (gctSIZE_T) kernelInterface->u.MapMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.MapMemory.logical)
++ ));
++ break;
++
++ case gcvHAL_MAP_USER_MEMORY:
++ /* Map user memory to DMA. */
++ gcmkERR_BREAK(gckOS_MapUserMemory(
++ Kernel->os,
++ gcvCORE_VG,
++ gcmUINT64_TO_PTR(kernelInterface->u.MapUserMemory.memory),
++ kernelInterface->u.MapUserMemory.physical,
++ (gctSIZE_T) kernelInterface->u.MapUserMemory.size,
++ &info,
++ &kernelInterface->u.MapUserMemory.address
++ ));
++
++ kernelInterface->u.MapUserMemory.info = gcmPTR_TO_NAME(info);
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ /* Unmap user memory. */
++ gcmkERR_BREAK(gckOS_UnmapUserMemory(
++ Kernel->os,
++ gcvCORE_VG,
++ gcmUINT64_TO_PTR(kernelInterface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) kernelInterface->u.UnmapUserMemory.size,
++ gcmNAME_TO_PTR(kernelInterface->u.UnmapUserMemory.info),
++ kernelInterface->u.UnmapUserMemory.address
++ ));
++ gcmRELEASE_NAME(kernelInterface->u.UnmapUserMemory.info);
++ break;
++ case gcvHAL_LOCK_VIDEO_MEMORY:
++ node = gcmUINT64_TO_PTR(Interface->u.LockVideoMemory.node);
++
++ /* Lock video memory. */
++ gcmkERR_BREAK(
++ gckVIDMEM_Lock(Kernel,
++ node,
++ gcvFALSE,
++ &Interface->u.LockVideoMemory.address));
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Map video memory address into user space. */
++#ifdef __QNXNTO__
++ if (node->VidMem.logical == gcvNULL)
++ {
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemory(Kernel,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ processID,
++ node->VidMem.bytes,
++ &node->VidMem.logical));
++ }
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->VidMem.logical);
++#else
++ gcmkERR_BREAK(
++ gckKERNEL_MapVideoMemoryEx(Kernel,
++ gcvCORE_VG,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ &logical));
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(logical);
++#endif
++ }
++ else
++ {
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->Virtual.logical);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++
++#if gcdSECURE_USER
++ /* Return logical address as physical address. */
++ Interface->u.LockVideoMemory.address =
++ (gctUINT32)(Interface->u.LockVideoMemory.memory);
++#endif
++ gcmkERR_BREAK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_LOCKED,
++ node,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ /* Unlock video memory. */
++ node = gcmUINT64_TO_PTR(Interface->u.UnlockVideoMemory.node);
++
++#if gcdSECURE_USER
++ /* Save node information before it disappears. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ logical = gcvNULL;
++ bytes = 0;
++ }
++ else
++ {
++ logical = node->Virtual.logical;
++ bytes = node->Virtual.bytes;
++ }
++#endif
++
++ /* Unlock video memory. */
++ gcmkERR_BREAK(
++ gckVIDMEM_Unlock(Kernel,
++ node,
++ Interface->u.UnlockVideoMemory.type,
++ &Interface->u.UnlockVideoMemory.asynchroneous));
++
++#if gcdSECURE_USER
++ /* Flush the translation cache for virtual surfaces. */
++ if (logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(Kernel,
++ cache,
++ logical,
++ bytes));
++ }
++#endif
++
++ if (Interface->u.UnlockVideoMemory.asynchroneous == gcvFALSE)
++ {
++ /* There isn't a event to unlock this node, remove record now */
++ gcmkERR_BREAK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY_LOCKED,
++ node));
++ }
++
++ break;
++ case gcvHAL_USER_SIGNAL:
++#if !USE_NEW_LINUX_SIGNAL
++ /* Dispatch depends on the user signal subcommands. */
++ switch(Interface->u.UserSignal.command)
++ {
++ case gcvUSER_SIGNAL_CREATE:
++ /* Create a signal used in the user space. */
++ gcmkERR_BREAK(
++ gckOS_CreateUserSignal(Kernel->os,
++ Interface->u.UserSignal.manualReset,
++ &Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_DESTROY:
++ /* Destroy the signal. */
++ gcmkERR_BREAK(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++ break;
++
++ case gcvUSER_SIGNAL_SIGNAL:
++ /* Signal the signal. */
++ gcmkERR_BREAK(
++ gckOS_SignalUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.state));
++ break;
++
++ case gcvUSER_SIGNAL_WAIT:
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.wait);
++ break;
++
++ default:
++ /* Invalid user signal command. */
++ gcmkERR_BREAK(gcvSTATUS_INVALID_ARGUMENT);
++ }
++#endif
++ break;
++
++ case gcvHAL_COMMIT:
++ /* Commit a command and context buffer. */
++ gcmkERR_BREAK(gckVGCOMMAND_Commit(
++ Kernel->vg->command,
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.context),
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.queue),
++ kernelInterface->u.VGCommit.entryCount,
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.taskTable)
++ ));
++ break;
++ case gcvHAL_VERSION:
++ kernelInterface->u.Version.major = gcvVERSION_MAJOR;
++ kernelInterface->u.Version.minor = gcvVERSION_MINOR;
++ kernelInterface->u.Version.patch = gcvVERSION_PATCH;
++ kernelInterface->u.Version.build = gcvVERSION_BUILD;
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_GET_BASE_ADDRESS:
++ /* Get base address. */
++ gcmkERR_BREAK(
++ gckOS_GetBaseAddress(Kernel->os,
++ &kernelInterface->u.GetBaseAddress.baseAddress));
++ break;
++ default:
++ /* Invalid command. */
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++OnError:
++ /* Save status. */
++ kernelInterface->status = status;
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_QueryCommandBuffer
++**
++** Query command buffer attributes.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsCOMMAND_BUFFER_INFO_PTR Information
++** Pointer to the information structure to receive buffer attributes.
++*/
++gceSTATUS
++gckKERNEL_QueryCommandBuffer(
++ IN gckKERNEL Kernel,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=0x%x *Pool=0x%x",
++ Kernel, Information);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get the information. */
++ status = gckVGCOMMAND_QueryCommandBuffer(Kernel->vg->command, Information);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h 2014-05-15 20:33:58.598018189 +0200
+@@ -0,0 +1,85 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_vg_h_
++#define __gc_hal_kernel_vg_h_
++
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel_hardware.h"
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++
++/* gckKERNEL object. */
++struct _gckVGKERNEL
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckVGHARDWARE hardware;
++
++ /* Pointer to gckINTERRUPT object. */
++ gckVGINTERRUPT interrupt;
++
++ /* Pointer to gckCOMMAND object. */
++ gckVGCOMMAND command;
++
++ /* Pointer to context. */
++ gctPOINTER context;
++
++ /* Pointer to gckMMU object. */
++ gckVGMMU mmu;
++
++ gckKERNEL kernel;
++};
++
++/* gckMMU object. */
++struct _gckVGMMU
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckVGHARDWARE hardware;
++
++ /* The page table mutex. */
++ gctPOINTER mutex;
++
++ /* Page table information. */
++ gctSIZE_T pageTableSize;
++ gctPHYS_ADDR pageTablePhysical;
++ gctPOINTER pageTableLogical;
++
++ /* Allocation index. */
++ gctUINT32 entryCount;
++ gctUINT32 entry;
++};
++
++#endif /* __gc_hal_kernel_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c 2014-05-15 20:33:58.606018247 +0200
+@@ -0,0 +1,2249 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_VIDMEM
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** _Split
++**
++** Split a node on the required byte boundary.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to the node to split.
++**
++** gctSIZE_T Bytes
++** Number of bytes to keep in the node.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gctBOOL
++** gcvTRUE if the node was split successfully, or gcvFALSE if there is an
++** error.
++**
++*/
++static gctBOOL
++_Split(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gctPOINTER pointer = gcvNULL;
++
++ /* Make sure the byte boundary makes sense. */
++ if ((Bytes <= 0) || (Bytes > Node->VidMem.bytes))
++ {
++ return gcvFALSE;
++ }
++
++ /* Allocate a new gcuVIDMEM_NODE object. */
++ if (gcmIS_ERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(gcuVIDMEM_NODE),
++ &pointer)))
++ {
++ /* Error. */
++ return gcvFALSE;
++ }
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE structure. */
++ node->VidMem.offset = Node->VidMem.offset + Bytes;
++ node->VidMem.bytes = Node->VidMem.bytes - Bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.locked = 0;
++ node->VidMem.memory = Node->VidMem.memory;
++ node->VidMem.pool = Node->VidMem.pool;
++ node->VidMem.physical = Node->VidMem.physical;
++#ifdef __QNXNTO__
++#if gcdUSE_VIDMEM_PER_PID
++ gcmkASSERT(Node->VidMem.physical != 0);
++ gcmkASSERT(Node->VidMem.logical != gcvNULL);
++ node->VidMem.processID = Node->VidMem.processID;
++ node->VidMem.physical = Node->VidMem.physical + Bytes;
++ node->VidMem.logical = Node->VidMem.logical + Bytes;
++#else
++ node->VidMem.processID = 0;
++ node->VidMem.logical = gcvNULL;
++#endif
++#endif
++
++ /* Insert node behind specified node. */
++ node->VidMem.next = Node->VidMem.next;
++ node->VidMem.prev = Node;
++ Node->VidMem.next = node->VidMem.next->VidMem.prev = node;
++
++ /* Insert free node behind specified node. */
++ node->VidMem.nextFree = Node->VidMem.nextFree;
++ node->VidMem.prevFree = Node;
++ Node->VidMem.nextFree = node->VidMem.nextFree->VidMem.prevFree = node;
++
++ /* Adjust size of specified node. */
++ Node->VidMem.bytes = Bytes;
++
++ /* Success. */
++ return gcvTRUE;
++}
++
++/*******************************************************************************
++**
++** _Merge
++**
++** Merge two adjacent nodes together.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to the first of the two nodes to merge.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++*/
++static gceSTATUS
++_Merge(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gceSTATUS status;
++
++ /* Save pointer to next node. */
++ node = Node->VidMem.next;
++#if gcdUSE_VIDMEM_PER_PID
++ /* Check if the nodes are adjacent physically. */
++ if ( ((Node->VidMem.physical + Node->VidMem.bytes) != node->VidMem.physical) ||
++ ((Node->VidMem.logical + Node->VidMem.bytes) != node->VidMem.logical) )
++ {
++ /* Can't merge. */
++ return gcvSTATUS_OK;
++ }
++#else
++
++ /* This is a good time to make sure the heap is not corrupted. */
++ if (Node->VidMem.offset + Node->VidMem.bytes != node->VidMem.offset)
++ {
++ /* Corrupted heap. */
++ gcmkASSERT(
++ Node->VidMem.offset + Node->VidMem.bytes == node->VidMem.offset);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++#endif
++
++ /* Adjust byte count. */
++ Node->VidMem.bytes += node->VidMem.bytes;
++
++ /* Unlink next node from linked list. */
++ Node->VidMem.next = node->VidMem.next;
++ Node->VidMem.nextFree = node->VidMem.nextFree;
++
++ Node->VidMem.next->VidMem.prev =
++ Node->VidMem.nextFree->VidMem.prevFree = Node;
++
++ /* Free next node. */
++ status = gcmkOS_SAFE_FREE(Os, node);
++ return status;
++}
++
++/******************************************************************************\
++******************************* gckVIDMEM API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVIDMEM_ConstructVirtual
++**
++** Construct a new gcuVIDMEM_NODE union for virtual memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSIZE_T Bytes
++** Number of byte to allocate.
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that receives the gcuVIDMEM_NODE union pointer.
++*/
++gceSTATUS
++gckVIDMEM_ConstructVirtual(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Contiguous,
++ IN gctSIZE_T Bytes,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("Kernel=0x%x Contiguous=%d Bytes=%lu", Kernel, Contiguous, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate an gcuVIDMEM_NODE union. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer));
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE union for virtual memory. */
++ node->Virtual.kernel = Kernel;
++ node->Virtual.contiguous = Contiguous;
++ node->Virtual.logical = gcvNULL;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ node->Virtual.lockeds[i] = 0;
++ node->Virtual.pageTables[i] = gcvNULL;
++ node->Virtual.lockKernels[i] = gcvNULL;
++ }
++
++ node->Virtual.mutex = gcvNULL;
++
++ gcmkONERROR(gckOS_GetProcessID(&node->Virtual.processID));
++
++#ifdef __QNXNTO__
++ node->Virtual.next = gcvNULL;
++ node->Virtual.freePending = gcvFALSE;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ node->Virtual.unlockPendings[i] = gcvFALSE;
++ }
++#endif
++
++ node->Virtual.freed = gcvFALSE;
++
++ gcmkONERROR(gckOS_ZeroMemory(&node->Virtual.sharedInfo, gcmSIZEOF(gcsVIDMEM_NODE_SHARED_INFO)));
++
++ /* Create the mutex. */
++ gcmkONERROR(
++ gckOS_CreateMutex(os, &node->Virtual.mutex));
++
++ /* Allocate the virtual memory. */
++ gcmkONERROR(
++ gckOS_AllocatePagedMemoryEx(os,
++ node->Virtual.contiguous,
++ node->Virtual.bytes = Bytes,
++ &node->Virtual.physical));
++
++#ifdef __QNXNTO__
++ /* Register. */
++#if gcdENABLE_VG
++ if (Kernel->core != gcvCORE_VG)
++#endif
++ {
++ gckMMU_InsertNode(Kernel->mmu, node);
++ }
++#endif
++
++ /* Return pointer to the gcuVIDMEM_NODE union. */
++ *Node = node;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Created virtual node 0x%x for %u bytes @ 0x%x",
++ node, Bytes, node->Virtual.physical);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ if (node->Virtual.mutex != gcvNULL)
++ {
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, node->Virtual.mutex));
++ }
++
++ /* Free the structure. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, node));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_DestroyVirtual
++**
++** Destroy an gcuVIDMEM_NODE union for virtual memory.
++**
++** INPUT:
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_DestroyVirtual(
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gckOS os;
++ gctINT i;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Node->Virtual.kernel, gcvOBJ_KERNEL);
++
++ /* Extact the gckOS object pointer. */
++ os = Node->Virtual.kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++#ifdef __QNXNTO__
++ /* Unregister. */
++#if gcdENABLE_VG
++ if (Node->Virtual.kernel->core != gcvCORE_VG)
++#endif
++ {
++ gcmkVERIFY_OK(
++ gckMMU_RemoveNode(Node->Virtual.kernel->mmu, Node));
++ }
++#endif
++
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, Node->Virtual.mutex));
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Node->Virtual.pageTables[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ /* Free the pages. */
++ gcmkVERIFY_OK(gckVGMMU_FreePages(Node->Virtual.lockKernels[i]->vg->mmu,
++ Node->Virtual.pageTables[i],
++ Node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ /* Free the pages. */
++ gcmkVERIFY_OK(gckMMU_FreePages(Node->Virtual.lockKernels[i]->mmu,
++ Node->Virtual.pageTables[i],
++ Node->Virtual.pageCount));
++ }
++ }
++ }
++
++ /* Delete the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, Node));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Construct
++**
++** Construct a new gckVIDMEM object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 BaseAddress
++** Base address for the video memory heap.
++**
++** gctSIZE_T Bytes
++** Number of bytes in the video memory heap.
++**
++** gctSIZE_T Threshold
++** Minimum number of bytes beyond am allocation before the node is
++** split. Can be used as a minimum alignment requirement.
++**
++** gctSIZE_T BankSize
++** Number of bytes per physical memory bank. Used by bank
++** optimization.
++**
++** OUTPUT:
++**
++** gckVIDMEM * Memory
++** Pointer to a variable that will hold the pointer to the gckVIDMEM
++** object.
++*/
++gceSTATUS
++gckVIDMEM_Construct(
++ IN gckOS Os,
++ IN gctUINT32 BaseAddress,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Threshold,
++ IN gctSIZE_T BankSize,
++ OUT gckVIDMEM * Memory
++ )
++{
++ gckVIDMEM memory = gcvNULL;
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node;
++ gctINT i, banks = 0;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x BaseAddress=%08x Bytes=%lu Threshold=%lu "
++ "BankSize=%lu",
++ Os, BaseAddress, Bytes, Threshold, BankSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Allocate the gckVIDMEM object. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct _gckVIDMEM), &pointer));
++
++ memory = pointer;
++
++ /* Initialize the gckVIDMEM object. */
++ memory->object.type = gcvOBJ_VIDMEM;
++ memory->os = Os;
++
++ /* Set video memory heap information. */
++ memory->baseAddress = BaseAddress;
++ memory->bytes = Bytes;
++ memory->freeBytes = Bytes;
++ memory->threshold = Threshold;
++ memory->mutex = gcvNULL;
++#if gcdUSE_VIDMEM_PER_PID
++ gcmkONERROR(gckOS_GetProcessID(&memory->pid));
++#endif
++
++ BaseAddress = 0;
++
++ /* Walk all possible banks. */
++ for (i = 0; i < gcmCOUNTOF(memory->sentinel); ++i)
++ {
++ gctSIZE_T bytes;
++
++ if (BankSize == 0)
++ {
++ /* Use all bytes for the first bank. */
++ bytes = Bytes;
++ }
++ else
++ {
++ /* Compute number of bytes for this bank. */
++ bytes = gcmALIGN(BaseAddress + 1, BankSize) - BaseAddress;
++
++ if (bytes > Bytes)
++ {
++ /* Make sure we don't exceed the total number of bytes. */
++ bytes = Bytes;
++ }
++ }
++
++ if (bytes == 0)
++ {
++ /* Mark heap is not used. */
++ memory->sentinel[i].VidMem.next =
++ memory->sentinel[i].VidMem.prev =
++ memory->sentinel[i].VidMem.nextFree =
++ memory->sentinel[i].VidMem.prevFree = gcvNULL;
++ continue;
++ }
++
++ /* Allocate one gcuVIDMEM_NODE union. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer));
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE union. */
++ node->VidMem.memory = memory;
++
++ node->VidMem.next =
++ node->VidMem.prev =
++ node->VidMem.nextFree =
++ node->VidMem.prevFree = &memory->sentinel[i];
++
++ node->VidMem.offset = BaseAddress;
++ node->VidMem.bytes = bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.physical = 0;
++ node->VidMem.pool = gcvPOOL_UNKNOWN;
++
++ node->VidMem.locked = 0;
++
++ gcmkONERROR(gckOS_ZeroMemory(&node->VidMem.sharedInfo, gcmSIZEOF(gcsVIDMEM_NODE_SHARED_INFO)));
++
++#ifdef __QNXNTO__
++#if gcdUSE_VIDMEM_PER_PID
++ node->VidMem.processID = memory->pid;
++ node->VidMem.physical = memory->baseAddress + BaseAddress;
++ gcmkONERROR(gckOS_GetLogicalAddressProcess(Os,
++ node->VidMem.processID,
++ node->VidMem.physical,
++ &node->VidMem.logical));
++#else
++ node->VidMem.processID = 0;
++ node->VidMem.logical = gcvNULL;
++#endif
++#endif
++
++ /* Initialize the linked list of nodes. */
++ memory->sentinel[i].VidMem.next =
++ memory->sentinel[i].VidMem.prev =
++ memory->sentinel[i].VidMem.nextFree =
++ memory->sentinel[i].VidMem.prevFree = node;
++
++ /* Mark sentinel. */
++ memory->sentinel[i].VidMem.bytes = 0;
++
++ /* Adjust address for next bank. */
++ BaseAddress += bytes;
++ Bytes -= bytes;
++ banks ++;
++ }
++
++ /* Assign all the bank mappings. */
++ memory->mapping[gcvSURF_RENDER_TARGET] = banks - 1;
++ memory->mapping[gcvSURF_BITMAP] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_DEPTH] = banks - 1;
++ memory->mapping[gcvSURF_HIERARCHICAL_DEPTH] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TEXTURE] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_VERTEX] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_INDEX] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TILE_STATUS] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TYPE_UNKNOWN] = 0;
++
++#if gcdENABLE_VG
++ memory->mapping[gcvSURF_IMAGE] = 0;
++ memory->mapping[gcvSURF_MASK] = 0;
++ memory->mapping[gcvSURF_SCISSOR] = 0;
++#endif
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] INDEX: bank %d",
++ memory->mapping[gcvSURF_INDEX]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] VERTEX: bank %d",
++ memory->mapping[gcvSURF_VERTEX]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] TEXTURE: bank %d",
++ memory->mapping[gcvSURF_TEXTURE]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] RENDER_TARGET: bank %d",
++ memory->mapping[gcvSURF_RENDER_TARGET]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] DEPTH: bank %d",
++ memory->mapping[gcvSURF_DEPTH]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] TILE_STATUS: bank %d",
++ memory->mapping[gcvSURF_TILE_STATUS]);
++
++ /* Allocate the mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &memory->mutex));
++
++ /* Return pointer to the gckVIDMEM object. */
++ *Memory = memory;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%x", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (memory != gcvNULL)
++ {
++ if (memory->mutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, memory->mutex));
++ }
++
++ for (i = 0; i < banks; ++i)
++ {
++ /* Free the heap. */
++ gcmkASSERT(memory->sentinel[i].VidMem.next != gcvNULL);
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory->sentinel[i].VidMem.next));
++ }
++
++ /* Free the object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Destroy
++**
++** Destroy an gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_Destroy(
++ IN gckVIDMEM Memory
++ )
++{
++ gcuVIDMEM_NODE_PTR node, next;
++ gctINT i;
++
++ gcmkHEADER_ARG("Memory=0x%x", Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++
++ /* Walk all sentinels. */
++ for (i = 0; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ /* Bail out of the heap is not used. */
++ if (Memory->sentinel[i].VidMem.next == gcvNULL)
++ {
++ break;
++ }
++
++ /* Walk all the nodes until we reach the sentinel. */
++ for (node = Memory->sentinel[i].VidMem.next;
++ node->VidMem.bytes != 0;
++ node = next)
++ {
++ /* Save pointer to the next node. */
++ next = node->VidMem.next;
++
++ /* Free the node. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, node));
++ }
++ }
++
++ /* Free the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Memory->os, Memory->mutex));
++
++ /* Mark the object as unknown. */
++ Memory->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVIDMEM object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, Memory));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Allocate
++**
++** Allocate rectangular memory from the gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object.
++**
++** gctUINT Width
++** Width of rectangle to allocate. Make sure the width is properly
++** aligned.
++**
++** gctUINT Height
++** Height of rectangle to allocate. Make sure the height is properly
++** aligned.
++**
++** gctUINT Depth
++** Depth of rectangle to allocate. This equals to the number of
++** rectangles to allocate contiguously (i.e., for cubic maps and volume
++** textures).
++**
++** gctUINT BytesPerPixel
++** Number of bytes per pixel.
++**
++** gctUINT32 Alignment
++** Byte alignment for allocation.
++**
++** gceSURF_TYPE Type
++** Type of surface to allocate (use by bank optimization).
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that will hold the allocated memory node.
++*/
++gceSTATUS
++gckVIDMEM_Allocate(
++ IN gckVIDMEM Memory,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT BytesPerPixel,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gctSIZE_T bytes;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Memory=0x%x Width=%u Height=%u Depth=%u BytesPerPixel=%u "
++ "Alignment=%u Type=%d",
++ Memory, Width, Height, Depth, BytesPerPixel, Alignment,
++ Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++ gcmkVERIFY_ARGUMENT(Width > 0);
++ gcmkVERIFY_ARGUMENT(Height > 0);
++ gcmkVERIFY_ARGUMENT(Depth > 0);
++ gcmkVERIFY_ARGUMENT(BytesPerPixel > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Compute linear size. */
++ bytes = Width * Height * Depth * BytesPerPixel;
++
++ /* Allocate through linear function. */
++ gcmkONERROR(
++ gckVIDMEM_AllocateLinear(Memory, bytes, Alignment, Type, Node));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_BANK_ALIGNMENT
++
++#if !gcdBANK_BIT_START
++#error gcdBANK_BIT_START not defined.
++#endif
++
++#if !gcdBANK_BIT_END
++#error gcdBANK_BIT_END not defined.
++#endif
++/*******************************************************************************
++** _GetSurfaceBankAlignment
++**
++** Return the required offset alignment required to the make BaseAddress
++** aligned properly.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gcoOS object.
++**
++** gceSURF_TYPE Type
++** Type of allocation.
++**
++** gctUINT32 BaseAddress
++** Base address of current video memory node.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR AlignmentOffset
++** Pointer to a variable that will hold the number of bytes to skip in
++** the current video memory node in order to make the alignment bank
++** aligned.
++*/
++static gceSTATUS
++_GetSurfaceBankAlignment(
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 BaseAddress,
++ OUT gctUINT32_PTR AlignmentOffset
++ )
++{
++ gctUINT32 bank;
++ /* To retrieve the bank. */
++ static const gctUINT32 bankMask = (0xFFFFFFFF << gcdBANK_BIT_START)
++ ^ (0xFFFFFFFF << (gcdBANK_BIT_END + 1));
++
++ /* To retrieve the bank and all the lower bytes. */
++ static const gctUINT32 byteMask = ~(0xFFFFFFFF << (gcdBANK_BIT_END + 1));
++
++ gcmkHEADER_ARG("Type=%d BaseAddress=0x%x ", Type, BaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(AlignmentOffset != gcvNULL);
++
++ switch (Type)
++ {
++ case gcvSURF_RENDER_TARGET:
++ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START);
++
++ /* Align to the first bank. */
++ *AlignmentOffset = (bank == 0) ?
++ 0 :
++ ((1 << (gcdBANK_BIT_END + 1)) + 0) - (BaseAddress & byteMask);
++ break;
++
++ case gcvSURF_DEPTH:
++ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START);
++
++ /* Align to the third bank. */
++ *AlignmentOffset = (bank == 2) ?
++ 0 :
++ ((1 << (gcdBANK_BIT_END + 1)) + (2 << gcdBANK_BIT_START)) - (BaseAddress & byteMask);
++
++ /* Add a channel offset at the channel bit. */
++ *AlignmentOffset += (1 << gcdBANK_CHANNEL_BIT);
++ break;
++
++ default:
++ /* no alignment needed. */
++ *AlignmentOffset = 0;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_ARG("*AlignmentOffset=%u", *AlignmentOffset);
++ return gcvSTATUS_OK;
++}
++#endif
++
++static gcuVIDMEM_NODE_PTR
++_FindNode(
++ IN gckVIDMEM Memory,
++ IN gctINT Bank,
++ IN gctSIZE_T Bytes,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Alignment
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 alignment;
++
++#if gcdENABLE_BANK_ALIGNMENT
++ gctUINT32 bankAlignment;
++ gceSTATUS status;
++#endif
++
++ if (Memory->sentinel[Bank].VidMem.nextFree == gcvNULL)
++ {
++ /* No free nodes left. */
++ return gcvNULL;
++ }
++
++#if gcdENABLE_BANK_ALIGNMENT
++ /* Walk all free nodes until we have one that is big enough or we have
++ ** reached the sentinel. */
++ for (node = Memory->sentinel[Bank].VidMem.nextFree;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.nextFree)
++ {
++ gcmkONERROR(_GetSurfaceBankAlignment(
++ Type,
++ node->VidMem.memory->baseAddress + node->VidMem.offset,
++ &bankAlignment));
++
++ bankAlignment = gcmALIGN(bankAlignment, *Alignment);
++
++ /* Compute number of bytes to skip for alignment. */
++ alignment = (*Alignment == 0)
++ ? 0
++ : (*Alignment - (node->VidMem.offset % *Alignment));
++
++ if (alignment == *Alignment)
++ {
++ /* Node is already aligned. */
++ alignment = 0;
++ }
++
++ if (node->VidMem.bytes >= Bytes + alignment + bankAlignment)
++ {
++ /* This node is big enough. */
++ *Alignment = alignment + bankAlignment;
++ return node;
++ }
++ }
++#endif
++
++ /* Walk all free nodes until we have one that is big enough or we have
++ reached the sentinel. */
++ for (node = Memory->sentinel[Bank].VidMem.nextFree;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.nextFree)
++ {
++
++ gctINT modulo = gckMATH_ModuloInt(node->VidMem.offset, *Alignment);
++
++ /* Compute number of bytes to skip for alignment. */
++ alignment = (*Alignment == 0) ? 0 : (*Alignment - modulo);
++
++ if (alignment == *Alignment)
++ {
++ /* Node is already aligned. */
++ alignment = 0;
++ }
++
++ if (node->VidMem.bytes >= Bytes + alignment)
++ {
++ /* This node is big enough. */
++ *Alignment = alignment;
++ return node;
++ }
++ }
++
++#if gcdENABLE_BANK_ALIGNMENT
++OnError:
++#endif
++ /* Not enough memory. */
++ return gcvNULL;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_AllocateLinear
++**
++** Allocate linear memory from the gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** gctUINT32 Alignment
++** Byte alignment for allocation.
++**
++** gceSURF_TYPE Type
++** Type of surface to allocate (use by bank optimization).
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that will hold the allocated memory node.
++*/
++gceSTATUS
++gckVIDMEM_AllocateLinear(
++ IN gckVIDMEM Memory,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 alignment;
++ gctINT bank, i;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Memory=0x%x Bytes=%lu Alignment=%u Type=%d",
++ Memory, Bytes, Alignment, Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Type < gcvSURF_NUM_TYPES);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Memory->os, Memory->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++#if !gcdUSE_VIDMEM_PER_PID
++
++ if (Bytes > Memory->freeBytes)
++ {
++ /* Not enough memory. */
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++#endif
++
++#if gcdSMALL_BLOCK_SIZE
++ if ((Memory->freeBytes < (Memory->bytes/gcdRATIO_FOR_SMALL_MEMORY))
++ && (Bytes >= gcdSMALL_BLOCK_SIZE)
++ )
++ {
++ /* The left memory is for small memory.*/
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++#endif
++
++ /* Find the default bank for this surface type. */
++ gcmkASSERT((gctINT) Type < gcmCOUNTOF(Memory->mapping));
++ bank = Memory->mapping[Type];
++ alignment = Alignment;
++
++#if gcdUSE_VIDMEM_PER_PID
++ if (Bytes <= Memory->freeBytes)
++ {
++#endif
++ /* Find a free node in the default bank. */
++ node = _FindNode(Memory, bank, Bytes, Type, &alignment);
++
++ /* Out of memory? */
++ if (node == gcvNULL)
++ {
++ /* Walk all lower banks. */
++ for (i = bank - 1; i >= 0; --i)
++ {
++ /* Find a free node inside the current bank. */
++ node = _FindNode(Memory, i, Bytes, Type, &alignment);
++ if (node != gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++ /* Walk all upper banks. */
++ for (i = bank + 1; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ if (Memory->sentinel[i].VidMem.nextFree == gcvNULL)
++ {
++ /* Abort when we reach unused banks. */
++ break;
++ }
++
++ /* Find a free node inside the current bank. */
++ node = _FindNode(Memory, i, Bytes, Type, &alignment);
++ if (node != gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++#if gcdUSE_VIDMEM_PER_PID
++ }
++#endif
++
++ if (node == gcvNULL)
++ {
++ /* Out of memory. */
++#if gcdUSE_VIDMEM_PER_PID
++ /* Allocate more memory from shared pool. */
++ gctSIZE_T bytes;
++ gctPHYS_ADDR physical_temp;
++ gctUINT32 physical;
++ gctPOINTER logical;
++
++ bytes = gcmALIGN(Bytes, gcdUSE_VIDMEM_PER_PID_SIZE);
++
++ gcmkONERROR(gckOS_AllocateContiguous(Memory->os,
++ gcvTRUE,
++ &bytes,
++ &physical_temp,
++ &logical));
++
++ /* physical address is returned as 0 for user space. workaround. */
++ if (physical_temp == gcvNULL)
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(Memory->os, logical, &physical));
++ }
++
++ /* Allocate one gcuVIDMEM_NODE union. */
++ gcmkONERROR(
++ gckOS_Allocate(Memory->os,
++ gcmSIZEOF(gcuVIDMEM_NODE),
++ (gctPOINTER *) &node));
++
++ /* Initialize gcuVIDMEM_NODE union. */
++ node->VidMem.memory = Memory;
++
++ node->VidMem.offset = 0;
++ node->VidMem.bytes = bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.physical = physical;
++ node->VidMem.pool = gcvPOOL_UNKNOWN;
++
++ node->VidMem.locked = 0;
++
++#ifdef __QNXNTO__
++ gcmkONERROR(gckOS_GetProcessID(&node->VidMem.processID));
++ node->VidMem.logical = logical;
++ gcmkASSERT(logical != gcvNULL);
++#endif
++
++ /* Insert node behind sentinel node. */
++ node->VidMem.next = Memory->sentinel[bank].VidMem.next;
++ node->VidMem.prev = &Memory->sentinel[bank];
++ Memory->sentinel[bank].VidMem.next = node->VidMem.next->VidMem.prev = node;
++
++ /* Insert free node behind sentinel node. */
++ node->VidMem.nextFree = Memory->sentinel[bank].VidMem.nextFree;
++ node->VidMem.prevFree = &Memory->sentinel[bank];
++ Memory->sentinel[bank].VidMem.nextFree = node->VidMem.nextFree->VidMem.prevFree = node;
++
++ Memory->freeBytes += bytes;
++#else
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++#endif
++ }
++
++ /* Do we have an alignment? */
++ if (alignment > 0)
++ {
++ /* Split the node so it is aligned. */
++ if (_Split(Memory->os, node, alignment))
++ {
++ /* Successful split, move to aligned node. */
++ node = node->VidMem.next;
++
++ /* Remove alignment. */
++ alignment = 0;
++ }
++ }
++
++ /* Do we have enough memory after the allocation to split it? */
++ if (node->VidMem.bytes - Bytes > Memory->threshold)
++ {
++ /* Adjust the node size. */
++ _Split(Memory->os, node, Bytes);
++ }
++
++ /* Remove the node from the free list. */
++ node->VidMem.prevFree->VidMem.nextFree = node->VidMem.nextFree;
++ node->VidMem.nextFree->VidMem.prevFree = node->VidMem.prevFree;
++ node->VidMem.nextFree =
++ node->VidMem.prevFree = gcvNULL;
++
++ /* Fill in the information. */
++ node->VidMem.alignment = alignment;
++ node->VidMem.memory = Memory;
++#ifdef __QNXNTO__
++#if !gcdUSE_VIDMEM_PER_PID
++ node->VidMem.logical = gcvNULL;
++ gcmkONERROR(gckOS_GetProcessID(&node->VidMem.processID));
++#else
++ gcmkASSERT(node->VidMem.logical != gcvNULL);
++#endif
++#endif
++
++ /* Adjust the number of free bytes. */
++ Memory->freeBytes -= node->VidMem.bytes;
++
++ node->VidMem.freePending = gcvFALSE;
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ node->VidMem.kernelVirtual = gcvNULL;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++
++ /* Return the pointer to the node. */
++ *Node = node;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Allocated %u bytes @ 0x%x [0x%08X]",
++ node->VidMem.bytes, node, node->VidMem.offset);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Free
++**
++** Free an allocated video memory node.
++**
++** INPUT:
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_Free(
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gceSTATUS status;
++ gckKERNEL kernel = gcvNULL;
++ gckVIDMEM memory = gcvNULL;
++ gcuVIDMEM_NODE_PTR node;
++ gctBOOL mutexAcquired = gcvFALSE;
++ gckOS os = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++ gctINT32 i, totalLocked;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ if ((Node == gcvNULL)
++ || (Node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /**************************** Video Memory ********************************/
++
++ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ if (Node->VidMem.locked > 0)
++ {
++ /* Client still has a lock, defer free op 'till when lock reaches 0. */
++ Node->VidMem.freePending = gcvTRUE;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Node 0x%x is locked (%d)... deferring free.",
++ Node, Node->VidMem.locked);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract pointer to gckVIDMEM object owning the node. */
++ memory = Node->VidMem.memory;
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(memory->os, memory->mutex, gcvINFINITE));
++
++ mutexAcquired = gcvTRUE;
++
++#ifdef __QNXNTO__
++#if !gcdUSE_VIDMEM_PER_PID
++ /* Reset. */
++ Node->VidMem.processID = 0;
++ Node->VidMem.logical = gcvNULL;
++#endif
++
++ /* Don't try to re-free an already freed node. */
++ if ((Node->VidMem.nextFree == gcvNULL)
++ && (Node->VidMem.prevFree == gcvNULL)
++ )
++#endif
++ {
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ if (Node->VidMem.kernelVirtual)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "%s(%d) Unmap %x from kernel space.",
++ __FUNCTION__, __LINE__,
++ Node->VidMem.kernelVirtual);
++
++ gcmkVERIFY_OK(
++ gckOS_UnmapPhysical(memory->os,
++ Node->VidMem.kernelVirtual,
++ Node->VidMem.bytes));
++
++ Node->VidMem.kernelVirtual = gcvNULL;
++ }
++#endif
++
++ /* Check if Node is already freed. */
++ if (Node->VidMem.nextFree)
++ {
++ /* Node is alread freed. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ /* Update the number of free bytes. */
++ memory->freeBytes += Node->VidMem.bytes;
++
++ /* Find the next free node. */
++ for (node = Node->VidMem.next;
++ node != gcvNULL && node->VidMem.nextFree == gcvNULL;
++ node = node->VidMem.next) ;
++
++ /* Insert this node in the free list. */
++ Node->VidMem.nextFree = node;
++ Node->VidMem.prevFree = node->VidMem.prevFree;
++
++ Node->VidMem.prevFree->VidMem.nextFree =
++ node->VidMem.prevFree = Node;
++
++ /* Is the next node a free node and not the sentinel? */
++ if ((Node->VidMem.next == Node->VidMem.nextFree)
++ && (Node->VidMem.next->VidMem.bytes != 0)
++ )
++ {
++ /* Merge this node with the next node. */
++ gcmkONERROR(_Merge(memory->os, node = Node));
++ gcmkASSERT(node->VidMem.nextFree != node);
++ gcmkASSERT(node->VidMem.prevFree != node);
++ }
++
++ /* Is the previous node a free node and not the sentinel? */
++ if ((Node->VidMem.prev == Node->VidMem.prevFree)
++ && (Node->VidMem.prev->VidMem.bytes != 0)
++ )
++ {
++ /* Merge this node with the previous node. */
++ gcmkONERROR(_Merge(memory->os, node = Node->VidMem.prev));
++ gcmkASSERT(node->VidMem.nextFree != node);
++ gcmkASSERT(node->VidMem.prevFree != node);
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(memory->os, memory->mutex));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Node 0x%x is freed.",
++ Node);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ /* Get gckKERNEL object. */
++ kernel = Node->Virtual.kernel;
++
++ /* Verify the gckKERNEL object pointer. */
++ gcmkVERIFY_OBJECT(kernel, gcvOBJ_KERNEL);
++
++ /* Get the gckOS object pointer. */
++ os = kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Grab the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(os, Node->Virtual.mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ for (i = 0, totalLocked = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ totalLocked += Node->Virtual.lockeds[i];
++ }
++
++ if (totalLocked > 0)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_VIDMEM,
++ "gckVIDMEM_Free: Virtual node 0x%x is locked (%d)",
++ Node, totalLocked);
++
++ /* Set Flag */
++ Node->Virtual.freed = gcvTRUE;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->Virtual.mutex));
++ }
++ else
++ {
++ /* Free the virtual memory. */
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(kernel->os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes));
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->Virtual.mutex));
++
++ /* Destroy the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gckVIDMEM_DestroyVirtual(Node));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutexAcquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ memory->os, memory->mutex
++ ));
++ }
++
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->Virtual.mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++
++#ifdef __QNXNTO__
++/*******************************************************************************
++**
++** gcoVIDMEM_FreeHandleMemory
++**
++** Free all allocated video memory nodes for a handle.
++**
++** INPUT:
++**
++** gcoVIDMEM Memory
++** Pointer to an gcoVIDMEM object..
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_FreeHandleMemory(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctUINT32 Pid
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gcuVIDMEM_NODE_PTR node;
++ gctINT i;
++ gctUINT32 nodeCount = 0, byteCount = 0;
++ gctBOOL again;
++
++ gcmkHEADER_ARG("Kernel=0x%x, Memory=0x%x Pid=0x%u", Kernel, Memory, Pid);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++
++ gcmkONERROR(gckOS_AcquireMutex(Memory->os, Memory->mutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ /* Walk all sentinels. */
++ for (i = 0; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ /* Bail out of the heap if it is not used. */
++ if (Memory->sentinel[i].VidMem.next == gcvNULL)
++ {
++ break;
++ }
++
++ do
++ {
++ again = gcvFALSE;
++
++ /* Walk all the nodes until we reach the sentinel. */
++ for (node = Memory->sentinel[i].VidMem.next;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.next)
++ {
++ /* Free the node if it was allocated by Handle. */
++ if (node->VidMem.processID == Pid)
++ {
++ /* Unlock video memory. */
++ while (node->VidMem.locked > 0)
++ {
++ gckVIDMEM_Unlock(Kernel, node, gcvSURF_TYPE_UNKNOWN, gcvNULL);
++ }
++
++ nodeCount++;
++ byteCount += node->VidMem.bytes;
++
++ /* Free video memory. */
++ gcmkVERIFY_OK(gckVIDMEM_Free(node));
++
++ /*
++ * Freeing may cause a merge which will invalidate our iteration.
++ * Don't be clever, just restart.
++ */
++ again = gcvTRUE;
++
++ break;
++ }
++#if gcdUSE_VIDMEM_PER_PID
++ else
++ {
++ gcmkASSERT(node->VidMem.processID == Pid);
++ }
++#endif
++ }
++ }
++ while (again);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutex)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** _NeedVirtualMapping
++**
++** Whether setup GPU page table for video node.
++**
++** INPUT:
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** gceCORE Core
++** Id of current GPU.
++**
++** OUTPUT:
++** gctBOOL * NeedMapping
++** A pointer hold the result whether Node should be mapping.
++*/
++static gceSTATUS
++_NeedVirtualMapping(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gcuVIDMEM_NODE_PTR Node,
++ OUT gctBOOL * NeedMapping
++)
++{
++ gceSTATUS status;
++ gctUINT32 phys;
++ gctUINT32 end;
++ gcePOOL pool;
++ gctUINT32 offset;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Node=0x%X", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(NeedMapping != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Core < gcdMAX_GPU_COUNT);
++
++ if (Node->Virtual.contiguous)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ *NeedMapping = gcvFALSE;
++ }
++ else
++#endif
++ {
++ /* Convert logical address into a physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, Node->Virtual.logical, &phys));
++
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++
++ gcmkASSERT(phys >= baseAddress);
++
++ /* Subtract baseAddress to get a GPU address used for programming. */
++ phys -= baseAddress;
++
++ /* If part of region is belong to gcvPOOL_VIRTUAL,
++ ** whole region has to be mapped. */
++ end = phys + Node->Virtual.bytes - 1;
++
++ gcmkONERROR(gckHARDWARE_SplitMemory(
++ Kernel->hardware, end, &pool, &offset
++ ));
++
++ *NeedMapping = (pool == gcvPOOL_VIRTUAL);
++ }
++ }
++ else
++ {
++ *NeedMapping = gcvTRUE;
++ }
++
++ gcmkFOOTER_ARG("*NeedMapping=%d", *NeedMapping);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Lock
++**
++** Lock a video memory node and return its hardware specific address.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable that will hold the hardware specific address.
++*/
++gceSTATUS
++gckVIDMEM_Lock(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctBOOL Cacheable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL locked = gcvFALSE;
++ gckOS os = gcvNULL;
++ gctBOOL needMapping;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ if ((Node == gcvNULL)
++ || (Node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /**************************** Video Memory ********************************/
++
++ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ if (Cacheable == gcvTRUE)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Increment the lock count. */
++ Node->VidMem.locked ++;
++
++ /* Return the physical address of the node. */
++#if !gcdUSE_VIDMEM_PER_PID
++ *Address = Node->VidMem.memory->baseAddress
++ + Node->VidMem.offset
++ + Node->VidMem.alignment;
++#else
++ *Address = Node->VidMem.physical;
++#endif
++
++ /* Get hardware specific address. */
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ if (Kernel->hardware->mmuVersion == 0)
++ {
++ /* Convert physical to GPU address for old mmu. */
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++ gcmkASSERT(*Address > baseAddress);
++ *Address -= baseAddress;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Locked node 0x%x (%d) @ 0x%08X",
++ Node,
++ Node->VidMem.locked,
++ *Address);
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ else
++ {
++ /* Verify the gckKERNEL object pointer. */
++ gcmkVERIFY_OBJECT(Node->Virtual.kernel, gcvOBJ_KERNEL);
++
++ /* Extract the gckOS object pointer. */
++ os = Node->Virtual.kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Node->Virtual.mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++#if gcdPAGED_MEMORY_CACHEABLE
++ /* Force video memory cacheable. */
++ Cacheable = gcvTRUE;
++#endif
++
++ gcmkONERROR(
++ gckOS_LockPages(os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes,
++ Cacheable,
++ &Node->Virtual.logical,
++ &Node->Virtual.pageCount));
++
++ /* Increment the lock count. */
++ if (Node->Virtual.lockeds[Kernel->core] ++ == 0)
++ {
++ /* Is this node pending for a final unlock? */
++#ifdef __QNXNTO__
++ if (!Node->Virtual.contiguous && Node->Virtual.unlockPendings[Kernel->core])
++ {
++ /* Make sure we have a page table. */
++ gcmkASSERT(Node->Virtual.pageTables[Kernel->core] != gcvNULL);
++
++ /* Remove pending unlock. */
++ Node->Virtual.unlockPendings[Kernel->core] = gcvFALSE;
++ }
++
++ /* First lock - create a page table. */
++ gcmkASSERT(Node->Virtual.pageTables[Kernel->core] == gcvNULL);
++
++ /* Make sure we mark our node as not flushed. */
++ Node->Virtual.unlockPendings[Kernel->core] = gcvFALSE;
++#endif
++
++ locked = gcvTRUE;
++
++ gcmkONERROR(_NeedVirtualMapping(Kernel, Kernel->core, Node, &needMapping));
++
++ if (needMapping == gcvFALSE)
++ {
++ /* Get hardware specific address. */
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ gcmkONERROR(gckVGHARDWARE_ConvertLogical(Kernel->vg->hardware,
++ Node->Virtual.logical,
++ &Node->Virtual.addresses[Kernel->core]));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Kernel->hardware,
++ Node->Virtual.logical,
++ &Node->Virtual.addresses[Kernel->core]));
++ }
++ }
++ else
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(
++ gckVGMMU_AllocatePages(Kernel->vg->mmu,
++ Node->Virtual.pageCount,
++ &Node->Virtual.pageTables[Kernel->core],
++ &Node->Virtual.addresses[Kernel->core]));
++ }
++ else
++#endif
++ {
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(
++ gckMMU_AllocatePages(Kernel->mmu,
++ Node->Virtual.pageCount,
++ &Node->Virtual.pageTables[Kernel->core],
++ &Node->Virtual.addresses[Kernel->core]));
++ }
++
++ Node->Virtual.lockKernels[Kernel->core] = Kernel;
++
++ /* Map the pages. */
++#ifdef __QNXNTO__
++ gcmkONERROR(
++ gckOS_MapPagesEx(os,
++ Kernel->core,
++ Node->Virtual.physical,
++ Node->Virtual.logical,
++ Node->Virtual.pageCount,
++ Node->Virtual.pageTables[Kernel->core]));
++#else
++ gcmkONERROR(
++ gckOS_MapPagesEx(os,
++ Kernel->core,
++ Node->Virtual.physical,
++ Node->Virtual.pageCount,
++ Node->Virtual.pageTables[Kernel->core]));
++#endif
++
++#if gcdENABLE_VG
++ if (Kernel->core == gcvCORE_VG)
++ {
++ gcmkONERROR(gckVGMMU_Flush(Kernel->vg->mmu));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckMMU_Flush(Kernel->mmu));
++ }
++ }
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Mapped virtual node 0x%x to 0x%08X",
++ Node,
++ Node->Virtual.addresses[Kernel->core]);
++ }
++
++ /* Return hardware address. */
++ *Address = Node->Virtual.addresses[Kernel->core];
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->Virtual.mutex));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (locked)
++ {
++ if (Node->Virtual.pageTables[Kernel->core] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ /* Free the pages from the MMU. */
++ gcmkVERIFY_OK(
++ gckVGMMU_FreePages(Kernel->vg->mmu,
++ Node->Virtual.pageTables[Kernel->core],
++ Node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ /* Free the pages from the MMU. */
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(Kernel->mmu,
++ Node->Virtual.pageTables[Kernel->core],
++ Node->Virtual.pageCount));
++ }
++ Node->Virtual.pageTables[Kernel->core] = gcvNULL;
++ Node->Virtual.lockKernels[Kernel->core] = gcvNULL;
++ }
++
++ /* Unlock the pages. */
++ gcmkVERIFY_OK(
++ gckOS_UnlockPages(os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes,
++ Node->Virtual.logical
++ ));
++
++ Node->Virtual.lockeds[Kernel->core]--;
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->Virtual.mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Unlock
++**
++** Unlock a video memory node.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a locked gcuVIDMEM_NODE union.
++**
++** gceSURF_TYPE Type
++** Type of surface to unlock.
++**
++** gctBOOL * Asynchroneous
++** Pointer to a variable specifying whether the surface should be
++** unlocked asynchroneously or not.
++**
++** OUTPUT:
++**
++** gctBOOL * Asynchroneous
++** Pointer to a variable receiving the number of bytes used in the
++** command buffer specified by 'Commands'. If gcvNULL, there is no
++** command buffer.
++*/
++gceSTATUS
++gckVIDMEM_Unlock(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gceSURF_TYPE Type,
++ IN OUT gctBOOL * Asynchroneous
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctPOINTER buffer;
++ gctSIZE_T requested, bufferSize;
++ gckCOMMAND command = gcvNULL;
++ gceKERNEL_FLUSH flush;
++ gckOS os = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL commitEntered = gcvFALSE;
++ gctINT32 i, totalLocked;
++
++ gcmkHEADER_ARG("Node=0x%x Type=%d *Asynchroneous=%d",
++ Node, Type, gcmOPT_VALUE(Asynchroneous));
++
++ /* Verify the arguments. */
++ if ((Node == gcvNULL)
++ || (Node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /**************************** Video Memory ********************************/
++
++ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ if (Node->VidMem.locked <= 0)
++ {
++ /* The surface was not locked. */
++ status = gcvSTATUS_MEMORY_UNLOCKED;
++ goto OnError;
++ }
++
++ /* Decrement the lock count. */
++ Node->VidMem.locked --;
++
++ if (Asynchroneous != gcvNULL)
++ {
++ /* No need for any events. */
++ *Asynchroneous = gcvFALSE;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Unlocked node 0x%x (%d)",
++ Node,
++ Node->VidMem.locked);
++
++#ifdef __QNXNTO__
++ /* Unmap the video memory */
++ if ((Node->VidMem.locked == 0) && (Node->VidMem.logical != gcvNULL))
++ {
++ if (Kernel->core == gcvCORE_VG)
++ {
++ gckKERNEL_UnmapVideoMemory(Kernel,
++ Node->VidMem.logical,
++ Node->VidMem.processID,
++ Node->VidMem.bytes);
++ Node->VidMem.logical = gcvNULL;
++ }
++ }
++#endif /* __QNXNTO__ */
++
++ if (Node->VidMem.freePending && (Node->VidMem.locked == 0))
++ {
++ /* Client has unlocked node previously attempted to be freed by compositor. Free now. */
++ Node->VidMem.freePending = gcvFALSE;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Deferred-freeing Node 0x%x.",
++ Node);
++ gcmkONERROR(gckVIDMEM_Free(Node));
++ }
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ else
++ {
++ /* Verify the gckHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ /* Get the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Grab the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(os, Node->Virtual.mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ if (Asynchroneous == gcvNULL)
++ {
++ if (Node->Virtual.lockeds[Kernel->core] == 0)
++ {
++ status = gcvSTATUS_MEMORY_UNLOCKED;
++ goto OnError;
++ }
++
++ /* Decrement lock count. */
++ -- Node->Virtual.lockeds[Kernel->core];
++
++ /* See if we can unlock the resources. */
++ if (Node->Virtual.lockeds[Kernel->core] == 0)
++ {
++ /* Free the page table. */
++ if (Node->Virtual.pageTables[Kernel->core] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ gcmkONERROR(
++ gckVGMMU_FreePages(Kernel->vg->mmu,
++ Node->Virtual.pageTables[Kernel->core],
++ Node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(
++ gckMMU_FreePages(Kernel->mmu,
++ Node->Virtual.pageTables[Kernel->core],
++ Node->Virtual.pageCount));
++ }
++ /* Mark page table as freed. */
++ Node->Virtual.pageTables[Kernel->core] = gcvNULL;
++ Node->Virtual.lockKernels[Kernel->core] = gcvNULL;
++ }
++
++#ifdef __QNXNTO__
++ /* Mark node as unlocked. */
++ Node->Virtual.unlockPendings[Kernel->core] = gcvFALSE;
++#endif
++ }
++
++ for (i = 0, totalLocked = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ totalLocked += Node->Virtual.lockeds[i];
++ }
++
++ if (totalLocked == 0)
++ {
++ /* Owner have already freed this node
++ ** and we are the last one to unlock, do
++ ** real free */
++ if (Node->Virtual.freed)
++ {
++ /* Free the virtual memory. */
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(Kernel->os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes));
++
++ /* Release mutex before node is destroyed */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->Virtual.mutex));
++
++ acquired = gcvFALSE;
++
++ /* Destroy the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gckVIDMEM_DestroyVirtual(Node));
++
++ /* Node has been destroyed, so we should not touch it any more */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Unmapped virtual node 0x%x from 0x%08X",
++ Node, Node->Virtual.addresses[Kernel->core]);
++
++ }
++
++ else
++ {
++ /* If we need to unlock a node from virtual memory we have to be
++ ** very carefull. If the node is still inside the caches we
++ ** might get a bus error later if the cache line needs to be
++ ** replaced. So - we have to flush the caches before we do
++ ** anything. */
++
++ /* gckCommand_EnterCommit() can't be called in interrupt handler because
++ ** of a dead lock situation:
++ ** process call Command_Commit(), and acquire Command->mutexQueue in
++ ** gckCOMMAND_EnterCommit(). Then it will wait for a signal which depends
++ ** on interrupt handler to generate, if interrupt handler enter
++ ** gckCommand_EnterCommit(), process will never get the signal. */
++
++ /* So, flush cache when we still in process context, and then ask caller to
++ ** schedule a event. */
++
++ gcmkONERROR(
++ gckOS_UnlockPages(os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes,
++ Node->Virtual.logical));
++
++ if (!Node->Virtual.contiguous
++ && (Node->Virtual.lockeds[Kernel->core] == 1)
++#if gcdENABLE_VG
++ && (Kernel->vg == gcvNULL)
++#endif
++ )
++ {
++ if (Type == gcvSURF_BITMAP)
++ {
++ /* Flush 2D cache. */
++ flush = gcvFLUSH_2D;
++ }
++ else if (Type == gcvSURF_RENDER_TARGET)
++ {
++ /* Flush color cache. */
++ flush = gcvFLUSH_COLOR;
++ }
++ else if (Type == gcvSURF_DEPTH)
++ {
++ /* Flush depth cache. */
++ flush = gcvFLUSH_DEPTH;
++ }
++ else
++ {
++ /* No flush required. */
++ flush = (gceKERNEL_FLUSH) 0;
++ }
++
++ gcmkONERROR(
++ gckHARDWARE_Flush(hardware, flush, gcvNULL, &requested));
++
++ if (requested != 0)
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvFALSE));
++ commitEntered = gcvTRUE;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, requested, &buffer, &bufferSize
++ ));
++
++ gcmkONERROR(gckHARDWARE_Flush(
++ hardware, flush, buffer, &bufferSize
++ ));
++
++ /* Mark node as pending. */
++#ifdef __QNXNTO__
++ Node->Virtual.unlockPendings[Kernel->core] = gcvTRUE;
++#endif
++
++ gcmkONERROR(gckCOMMAND_Execute(command, requested));
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvFALSE));
++ commitEntered = gcvFALSE;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Scheduled unlock for virtual node 0x%x",
++ Node);
++
++ /* Schedule the surface to be unlocked. */
++ *Asynchroneous = gcvTRUE;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->Virtual.mutex));
++
++ acquired = gcvFALSE;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Asynchroneous=%d", gcmOPT_VALUE(Asynchroneous));
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, gcvFALSE));
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->Virtual.mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h 2014-05-15 20:33:58.610018275 +0200
+@@ -0,0 +1,3896 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_base_h_
++#define __gc_hal_base_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#include "gc_hal_dump.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gckOS * gckOS;
++typedef struct _gcoHAL * gcoHAL;
++typedef struct _gcoOS * gcoOS;
++typedef struct _gco2D * gco2D;
++
++#ifndef VIVANTE_NO_3D
++typedef struct _gco3D * gco3D;
++#endif
++
++typedef struct _gcoSURF * gcoSURF;
++typedef struct _gcsSURF_INFO * gcsSURF_INFO_PTR;
++typedef struct _gcsSURF_NODE * gcsSURF_NODE_PTR;
++typedef struct _gcsSURF_FORMAT_INFO * gcsSURF_FORMAT_INFO_PTR;
++typedef struct _gcsPOINT * gcsPOINT_PTR;
++typedef struct _gcsSIZE * gcsSIZE_PTR;
++typedef struct _gcsRECT * gcsRECT_PTR;
++typedef struct _gcsBOUNDARY * gcsBOUNDARY_PTR;
++typedef struct _gcoDUMP * gcoDUMP;
++typedef struct _gcoHARDWARE * gcoHARDWARE;
++typedef union _gcuVIDMEM_NODE * gcuVIDMEM_NODE_PTR;
++
++typedef struct gcsATOM * gcsATOM_PTR;
++
++#if gcdENABLE_VG
++typedef struct _gcoVG * gcoVG;
++typedef struct _gcsCOMPLETION_SIGNAL * gcsCOMPLETION_SIGNAL_PTR;
++typedef struct _gcsCONTEXT_MAP * gcsCONTEXT_MAP_PTR;
++#else
++typedef void * gcoVG;
++#endif
++
++#if gcdSYNC
++typedef struct _gcoFENCE * gcoFENCE;
++typedef struct _gcsSYNC_CONTEXT * gcsSYNC_CONTEXT_PTR;
++#endif
++
++typedef struct _gcoOS_SymbolsList gcoOS_SymbolsList;
++
++/******************************************************************************\
++******************************* Process local storage *************************
++\******************************************************************************/
++typedef struct _gcsPLS * gcsPLS_PTR;
++
++typedef void (* gctPLS_DESTRUCTOR) (
++ gcsPLS_PTR
++ );
++
++typedef struct _gcsPLS
++{
++ /* Global objects. */
++ gcoOS os;
++ gcoHAL hal;
++
++ /* Internal memory pool. */
++ gctSIZE_T internalSize;
++ gctPHYS_ADDR internalPhysical;
++ gctPOINTER internalLogical;
++
++ /* External memory pool. */
++ gctSIZE_T externalSize;
++ gctPHYS_ADDR externalPhysical;
++ gctPOINTER externalLogical;
++
++ /* Contiguous memory pool. */
++ gctSIZE_T contiguousSize;
++ gctPHYS_ADDR contiguousPhysical;
++ gctPOINTER contiguousLogical;
++
++ /* EGL-specific process-wide objects. */
++ gctPOINTER eglDisplayInfo;
++ gctPOINTER eglSurfaceInfo;
++ gceSURF_FORMAT eglConfigFormat;
++
++ /* PorcessID of the constrcutor process */
++ gctUINT32 processID;
++#if gcdFORCE_GAL_LOAD_TWICE
++ /* ThreadID of the constrcutor process. */
++ gctSIZE_T threadID;
++ /* Flag for calling module destructor. */
++ gctBOOL exiting;
++#endif
++
++ /* Reference count for destructor. */
++ gcsATOM_PTR reference;
++ gctBOOL bKFS;
++#if gcdUSE_NPOT_PATCH
++ gctBOOL bNeedSupportNP2Texture;
++#endif
++
++ /* Destructor for eglDisplayInfo. */
++ gctPLS_DESTRUCTOR destructor;
++}
++gcsPLS;
++
++extern gcsPLS gcPLS;
++
++/******************************************************************************\
++******************************* Thread local storage *************************
++\******************************************************************************/
++
++typedef struct _gcsTLS * gcsTLS_PTR;
++
++typedef void (* gctTLS_DESTRUCTOR) (
++ gcsTLS_PTR
++ );
++
++typedef struct _gcsTLS
++{
++ gceHARDWARE_TYPE currentType;
++ gcoHARDWARE hardware;
++ /* Only for separated 3D and 2D */
++ gcoHARDWARE hardware2D;
++#if gcdENABLE_VG
++ gcoVGHARDWARE vg;
++ gcoVG engineVG;
++#endif /* gcdENABLE_VG */
++ gctPOINTER context;
++ gctTLS_DESTRUCTOR destructor;
++ gctBOOL ProcessExiting;
++
++#ifndef VIVANTE_NO_3D
++ gco3D engine3D;
++#endif
++#if gcdSYNC
++ gctBOOL fenceEnable;
++#endif
++ gco2D engine2D;
++ gctBOOL copied;
++
++#if gcdFORCE_GAL_LOAD_TWICE
++ /* libGAL.so handle */
++ gctHANDLE handle;
++#endif
++}
++gcsTLS;
++
++/******************************************************************************\
++********************************* Enumerations *********************************
++\******************************************************************************/
++
++typedef enum _gcePLS_VALUE
++{
++ gcePLS_VALUE_EGL_DISPLAY_INFO,
++ gcePLS_VALUE_EGL_SURFACE_INFO,
++ gcePLS_VALUE_EGL_CONFIG_FORMAT_INFO,
++ gcePLS_VALUE_EGL_DESTRUCTOR_INFO,
++}
++gcePLS_VALUE;
++
++/* Video memory pool type. */
++typedef enum _gcePOOL
++{
++ gcvPOOL_UNKNOWN = 0,
++ gcvPOOL_DEFAULT,
++ gcvPOOL_LOCAL,
++ gcvPOOL_LOCAL_INTERNAL,
++ gcvPOOL_LOCAL_EXTERNAL,
++ gcvPOOL_UNIFIED,
++ gcvPOOL_SYSTEM,
++ gcvPOOL_VIRTUAL,
++ gcvPOOL_USER,
++ gcvPOOL_CONTIGUOUS,
++ gcvPOOL_DEFAULT_FORCE_CONTIGUOUS,
++ gcvPOOL_DEFAULT_FORCE_CONTIGUOUS_CACHEABLE,
++
++ gcvPOOL_NUMBER_OF_POOLS
++}
++gcePOOL;
++
++#ifndef VIVANTE_NO_3D
++/* Blending functions. */
++typedef enum _gceBLEND_FUNCTION
++{
++ gcvBLEND_ZERO,
++ gcvBLEND_ONE,
++ gcvBLEND_SOURCE_COLOR,
++ gcvBLEND_INV_SOURCE_COLOR,
++ gcvBLEND_SOURCE_ALPHA,
++ gcvBLEND_INV_SOURCE_ALPHA,
++ gcvBLEND_TARGET_COLOR,
++ gcvBLEND_INV_TARGET_COLOR,
++ gcvBLEND_TARGET_ALPHA,
++ gcvBLEND_INV_TARGET_ALPHA,
++ gcvBLEND_SOURCE_ALPHA_SATURATE,
++ gcvBLEND_CONST_COLOR,
++ gcvBLEND_INV_CONST_COLOR,
++ gcvBLEND_CONST_ALPHA,
++ gcvBLEND_INV_CONST_ALPHA,
++}
++gceBLEND_FUNCTION;
++
++/* Blending modes. */
++typedef enum _gceBLEND_MODE
++{
++ gcvBLEND_ADD,
++ gcvBLEND_SUBTRACT,
++ gcvBLEND_REVERSE_SUBTRACT,
++ gcvBLEND_MIN,
++ gcvBLEND_MAX,
++}
++gceBLEND_MODE;
++
++/* API flags. */
++typedef enum _gceAPI
++{
++ gcvAPI_D3D = 0x1,
++ gcvAPI_OPENGL = 0x2,
++ gcvAPI_OPENVG = 0x3,
++ gcvAPI_OPENCL = 0x4,
++}
++gceAPI;
++
++/* Depth modes. */
++typedef enum _gceDEPTH_MODE
++{
++ gcvDEPTH_NONE,
++ gcvDEPTH_Z,
++ gcvDEPTH_W,
++}
++gceDEPTH_MODE;
++#endif /* VIVANTE_NO_3D */
++
++typedef enum _gceWHERE
++{
++ gcvWHERE_COMMAND,
++ gcvWHERE_RASTER,
++ gcvWHERE_PIXEL,
++}
++gceWHERE;
++
++typedef enum _gceHOW
++{
++ gcvHOW_SEMAPHORE = 0x1,
++ gcvHOW_STALL = 0x2,
++ gcvHOW_SEMAPHORE_STALL = 0x3,
++}
++gceHOW;
++
++typedef enum _gceSignalHandlerType
++{
++ gcvHANDLE_SIGFPE_WHEN_SIGNAL_CODE_IS_0 = 0x1,
++}
++gceSignalHandlerType;
++
++
++#if gcdENABLE_VG
++/* gcsHAL_Limits*/
++typedef struct _gcsHAL_LIMITS
++{
++ /* chip info */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 featureCount;
++ gctUINT32 *chipFeatures;
++
++ /* target caps */
++ gctUINT32 maxWidth;
++ gctUINT32 maxHeight;
++ gctUINT32 multiTargetCount;
++ gctUINT32 maxSamples;
++
++}gcsHAL_LIMITS;
++#endif
++
++/******************************************************************************\
++*********** Generic Memory Allocation Optimization Using Containers ************
++\******************************************************************************/
++
++/* Generic container definition. */
++typedef struct _gcsCONTAINER_LINK * gcsCONTAINER_LINK_PTR;
++typedef struct _gcsCONTAINER_LINK
++{
++ /* Points to the next container. */
++ gcsCONTAINER_LINK_PTR next;
++}
++gcsCONTAINER_LINK;
++
++typedef struct _gcsCONTAINER_RECORD * gcsCONTAINER_RECORD_PTR;
++typedef struct _gcsCONTAINER_RECORD
++{
++ gcsCONTAINER_RECORD_PTR prev;
++ gcsCONTAINER_RECORD_PTR next;
++}
++gcsCONTAINER_RECORD;
++
++typedef struct _gcsCONTAINER * gcsCONTAINER_PTR;
++typedef struct _gcsCONTAINER
++{
++ gctUINT containerSize;
++ gctUINT recordSize;
++ gctUINT recordCount;
++ gcsCONTAINER_LINK_PTR containers;
++ gcsCONTAINER_RECORD freeList;
++ gcsCONTAINER_RECORD allocList;
++}
++gcsCONTAINER;
++
++gceSTATUS
++gcsCONTAINER_Construct(
++ IN gcsCONTAINER_PTR Container,
++ gctUINT RecordsPerContainer,
++ gctUINT RecordSize
++ );
++
++gceSTATUS
++gcsCONTAINER_Destroy(
++ IN gcsCONTAINER_PTR Container
++ );
++
++gceSTATUS
++gcsCONTAINER_AllocateRecord(
++ IN gcsCONTAINER_PTR Container,
++ OUT gctPOINTER * Record
++ );
++
++gceSTATUS
++gcsCONTAINER_FreeRecord(
++ IN gcsCONTAINER_PTR Container,
++ IN gctPOINTER Record
++ );
++
++gceSTATUS
++gcsCONTAINER_FreeAll(
++ IN gcsCONTAINER_PTR Container
++ );
++
++/******************************************************************************\
++********************************* gcoHAL Object *********************************
++\******************************************************************************/
++
++/* Construct a new gcoHAL object. */
++gceSTATUS
++gcoHAL_Construct(
++ IN gctPOINTER Context,
++ IN gcoOS Os,
++ OUT gcoHAL * Hal
++ );
++
++/* Destroy an gcoHAL object. */
++gceSTATUS
++gcoHAL_Destroy(
++ IN gcoHAL Hal
++ );
++
++/* Get pointer to gco2D object. */
++gceSTATUS
++gcoHAL_Get2DEngine(
++ IN gcoHAL Hal,
++ OUT gco2D * Engine
++ );
++
++gceSTATUS
++gcoHAL_SetFscaleValue(
++ IN gctUINT FscaleValue
++ );
++
++gceSTATUS
++gcoHAL_GetFscaleValue(
++ OUT gctUINT * FscaleValue,
++ OUT gctUINT * MinFscaleValue,
++ OUT gctUINT * MaxFscaleValue
++ );
++
++gceSTATUS
++gcoHAL_SetBltNP2Texture(
++ gctBOOL enable
++ );
++
++#ifndef VIVANTE_NO_3D
++/* Get pointer to gco3D object. */
++gceSTATUS
++gcoHAL_Get3DEngine(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++
++gceSTATUS
++gcoHAL_Query3DEngine(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++
++gceSTATUS
++gcoHAL_Set3DEngine(
++ IN gcoHAL Hal,
++ IN gco3D Engine
++ );
++
++gceSTATUS
++gcoHAL_Get3DHardware(
++ IN gcoHAL Hal,
++ OUT gcoHARDWARE * Hardware
++ );
++
++gceSTATUS
++gcoHAL_Set3DHardware(
++ IN gcoHAL Hal,
++ IN gcoHARDWARE Hardware
++ );
++
++
++#endif /* VIVANTE_NO_3D */
++
++/* Verify whether the specified feature is available in hardware. */
++gceSTATUS
++gcoHAL_IsFeatureAvailable(
++ IN gcoHAL Hal,
++ IN gceFEATURE Feature
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gcoHAL_QueryChipIdentity(
++ IN gcoHAL Hal,
++ OUT gceCHIPMODEL* ChipModel,
++ OUT gctUINT32* ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures
++ );
++
++/* Query the minor features of the hardware. */
++gceSTATUS gcoHAL_QueryChipMinorFeatures(
++ IN gcoHAL Hal,
++ OUT gctUINT32* NumFeatures,
++ OUT gctUINT32* ChipMinorFeatures
++ );
++
++/* Query the amount of video memory. */
++gceSTATUS
++gcoHAL_QueryVideoMemory(
++ IN gcoHAL Hal,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Map video memory. */
++gceSTATUS
++gcoHAL_MapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap video memory. */
++gceSTATUS
++gcoHAL_UnmapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ IN gctPOINTER Logical
++ );
++
++/* Schedule an unmap of a buffer mapped through its physical address. */
++gceSTATUS
++gcoHAL_ScheduleUnmapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ IN gctPOINTER Logical
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoHAL_MapUserMemory(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR GPUAddress
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gcoHAL_UnmapUserMemory(
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 GPUAddress
++ );
++
++/* Schedule an unmap of a user buffer using event mechanism. */
++gceSTATUS
++gcoHAL_ScheduleUnmapUserMemory(
++ IN gcoHAL Hal,
++ IN gctPOINTER Info,
++ IN gctSIZE_T Size,
++ IN gctUINT32 Address,
++ IN gctPOINTER Memory
++ );
++
++/* Commit the current command buffer. */
++gceSTATUS
++gcoHAL_Commit(
++ IN gcoHAL Hal,
++ IN gctBOOL Stall
++ );
++
++/* Query the tile capabilities. */
++gceSTATUS
++gcoHAL_QueryTiled(
++ IN gcoHAL Hal,
++ OUT gctINT32 * TileWidth2D,
++ OUT gctINT32 * TileHeight2D,
++ OUT gctINT32 * TileWidth3D,
++ OUT gctINT32 * TileHeight3D
++ );
++
++gceSTATUS
++gcoHAL_Compact(
++ IN gcoHAL Hal
++ );
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gcoHAL_ProfileStart(
++ IN gcoHAL Hal
++ );
++
++gceSTATUS
++gcoHAL_ProfileEnd(
++ IN gcoHAL Hal,
++ IN gctCONST_STRING Title
++ );
++#endif
++
++/* Power Management */
++gceSTATUS
++gcoHAL_SetPowerManagementState(
++ IN gcoHAL Hal,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gcoHAL_QueryPowerManagementState(
++ IN gcoHAL Hal,
++ OUT gceCHIPPOWERSTATE *State
++ );
++
++/* Set the filter type for filter blit. */
++gceSTATUS
++gcoHAL_SetFilterType(
++ IN gcoHAL Hal,
++ IN gceFILTER_TYPE FilterType
++ );
++
++gceSTATUS
++gcoHAL_GetDump(
++ IN gcoHAL Hal,
++ OUT gcoDUMP * Dump
++ );
++
++/* Call the kernel HAL layer. */
++gceSTATUS
++gcoHAL_Call(
++ IN gcoHAL Hal,
++ IN OUT gcsHAL_INTERFACE_PTR Interface
++ );
++
++gceSTATUS
++gcoHAL_GetPatchID(
++ IN gcoHAL Hal,
++ OUT gcePATCH_ID * PatchID
++ );
++
++/* Schedule an event. */
++gceSTATUS
++gcoHAL_ScheduleEvent(
++ IN gcoHAL Hal,
++ IN OUT gcsHAL_INTERFACE_PTR Interface
++ );
++
++/* Destroy a surface. */
++gceSTATUS
++gcoHAL_DestroySurface(
++ IN gcoHAL Hal,
++ IN gcoSURF Surface
++ );
++
++/* Request a start/stop timestamp. */
++gceSTATUS
++gcoHAL_SetTimer(
++ IN gcoHAL Hal,
++ IN gctUINT32 Index,
++ IN gctBOOL Start
++ );
++
++/* Get Time delta from a Timer in microseconds. */
++gceSTATUS
++gcoHAL_GetTimerTime(
++ IN gcoHAL Hal,
++ IN gctUINT32 Timer,
++ OUT gctINT32_PTR TimeDelta
++ );
++
++/* set timeout value. */
++gceSTATUS
++gcoHAL_SetTimeOut(
++ IN gcoHAL Hal,
++ IN gctUINT32 timeOut
++ );
++
++gceSTATUS
++gcoHAL_SetHardwareType(
++ IN gcoHAL Hal,
++ IN gceHARDWARE_TYPE HardwardType
++ );
++
++gceSTATUS
++gcoHAL_GetHardwareType(
++ IN gcoHAL Hal,
++ OUT gceHARDWARE_TYPE * HardwardType
++ );
++
++gceSTATUS
++gcoHAL_QueryChipCount(
++ IN gcoHAL Hal,
++ OUT gctINT32 * Count
++ );
++
++gceSTATUS
++gcoHAL_QuerySeparated3D2D(
++ IN gcoHAL Hal
++ );
++
++gceSTATUS
++gcoHAL_QuerySpecialHint(
++ IN gceSPECIAL_HINT Hint
++ );
++
++gceSTATUS
++gcoHAL_SetSpecialHintData(
++ IN gcoHARDWARE Hardware
++ );
++
++/* Get pointer to gcoVG object. */
++gceSTATUS
++gcoHAL_GetVGEngine(
++ IN gcoHAL Hal,
++ OUT gcoVG * Engine
++ );
++
++#if gcdENABLE_VG
++gceSTATUS
++gcoHAL_QueryChipLimits(
++ IN gcoHAL Hal,
++ IN gctINT32 Chip,
++ OUT gcsHAL_LIMITS *Limits);
++
++gceSTATUS
++gcoHAL_QueryChipFeature(
++ IN gcoHAL Hal,
++ IN gctINT32 Chip,
++ IN gceFEATURE Feature);
++
++#endif
++/******************************************************************************\
++********************************** gcoOS Object *********************************
++\******************************************************************************/
++
++/* Get PLS value for given key */
++gctPOINTER
++gcoOS_GetPLSValue(
++ IN gcePLS_VALUE key
++ );
++
++/* Set PLS value of a given key */
++void
++gcoOS_SetPLSValue(
++ IN gcePLS_VALUE key,
++ OUT gctPOINTER value
++ );
++
++/* Get access to the thread local storage. */
++gceSTATUS
++gcoOS_GetTLS(
++ OUT gcsTLS_PTR * TLS
++ );
++
++ /* Copy the TLS from a source thread. */
++ gceSTATUS gcoOS_CopyTLS(IN gcsTLS_PTR Source);
++
++/* Destroy the objects associated with the current thread. */
++void
++gcoOS_FreeThreadData(
++ IN gctBOOL ProcessExiting
++ );
++
++/* Construct a new gcoOS object. */
++gceSTATUS
++gcoOS_Construct(
++ IN gctPOINTER Context,
++ OUT gcoOS * Os
++ );
++
++/* Destroy an gcoOS object. */
++gceSTATUS
++gcoOS_Destroy(
++ IN gcoOS Os
++ );
++
++/* Get the base address for the physical memory. */
++gceSTATUS
++gcoOS_GetBaseAddress(
++ IN gcoOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++/* Allocate memory from the heap. */
++gceSTATUS
++gcoOS_Allocate(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Get allocated memory size. */
++gceSTATUS
++gcoOS_GetMemorySize(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ OUT gctSIZE_T_PTR MemorySize
++ );
++
++/* Free allocated memory. */
++gceSTATUS
++gcoOS_Free(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoOS_AllocateMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoOS_FreeMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate contiguous memory. */
++gceSTATUS
++gcoOS_AllocateContiguous(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free contiguous memory. */
++gceSTATUS
++gcoOS_FreeContiguous(
++ IN gcoOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Allocate video memory. */
++gceSTATUS
++gcoOS_AllocateVideoMemory(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN gctBOOL InCacheable,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctUINT32 * Physical,
++ OUT gctPOINTER * Logical,
++ OUT gctPOINTER * Handle
++ );
++
++/* Free video memory. */
++gceSTATUS
++gcoOS_FreeVideoMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Handle
++ );
++
++gceSTATUS
++gcoSURF_GetBankOffsetBytes(
++ IN gcoSURF Surfce,
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 Stride,
++ IN gctUINT32_PTR Bytes
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoOS_MapUserMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoOS_MapUserMemoryEx(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gcoOS_UnmapUserMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ );
++
++/* Device I/O Control call to the kernel HAL layer. */
++gceSTATUS
++gcoOS_DeviceControl(
++ IN gcoOS Os,
++ IN gctUINT32 IoControlCode,
++ IN gctPOINTER InputBuffer,
++ IN gctSIZE_T InputBufferSize,
++ IN gctPOINTER OutputBuffer,
++ IN gctSIZE_T OutputBufferSize
++ );
++
++/* Allocate non paged memory. */
++gceSTATUS
++gcoOS_AllocateNonPagedMemory(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free non paged memory. */
++gceSTATUS
++gcoOS_FreeNonPagedMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++#define gcmOS_SAFE_FREE(os, mem) \
++ gcoOS_Free(os, mem); \
++ mem = gcvNULL
++
++#define gcmkOS_SAFE_FREE(os, mem) \
++ gckOS_Free(os, mem); \
++ mem = gcvNULL
++
++typedef enum _gceFILE_MODE
++{
++ gcvFILE_CREATE = 0,
++ gcvFILE_APPEND,
++ gcvFILE_READ,
++ gcvFILE_CREATETEXT,
++ gcvFILE_APPENDTEXT,
++ gcvFILE_READTEXT,
++}
++gceFILE_MODE;
++
++/* Open a file. */
++gceSTATUS
++gcoOS_Open(
++ IN gcoOS Os,
++ IN gctCONST_STRING FileName,
++ IN gceFILE_MODE Mode,
++ OUT gctFILE * File
++ );
++
++/* Close a file. */
++gceSTATUS
++gcoOS_Close(
++ IN gcoOS Os,
++ IN gctFILE File
++ );
++
++/* Read data from a file. */
++gceSTATUS
++gcoOS_Read(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctSIZE_T ByteCount,
++ IN gctPOINTER Data,
++ OUT gctSIZE_T * ByteRead
++ );
++
++/* Write data to a file. */
++gceSTATUS
++gcoOS_Write(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Flush data to a file. */
++gceSTATUS
++gcoOS_Flush(
++ IN gcoOS Os,
++ IN gctFILE File
++ );
++
++/* Close a file descriptor. */
++gceSTATUS
++gcoOS_CloseFD(
++ IN gcoOS Os,
++ IN gctINT FD
++ );
++
++/* Dup file descriptor to another. */
++gceSTATUS
++gcoOS_DupFD(
++ IN gcoOS Os,
++ IN gctINT FD,
++ OUT gctINT * FD2
++ );
++
++/* Create an endpoint for communication. */
++gceSTATUS
++gcoOS_Socket(
++ IN gcoOS Os,
++ IN gctINT Domain,
++ IN gctINT Type,
++ IN gctINT Protocol,
++ OUT gctINT *SockFd
++ );
++
++/* Close a socket. */
++gceSTATUS
++gcoOS_CloseSocket(
++ IN gcoOS Os,
++ IN gctINT SockFd
++ );
++
++/* Initiate a connection on a socket. */
++gceSTATUS
++gcoOS_Connect(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctCONST_POINTER HostName,
++ IN gctUINT Port);
++
++/* Shut down part of connection on a socket. */
++gceSTATUS
++gcoOS_Shutdown(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctINT How
++ );
++
++/* Send a message on a socket. */
++gceSTATUS
++gcoOS_Send(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data,
++ IN gctINT Flags
++ );
++
++/* Initiate a connection on a socket. */
++gceSTATUS
++gcoOS_WaitForSend(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctINT Seconds,
++ IN gctINT MicroSeconds);
++
++/* Get environment variable value. */
++gceSTATUS
++gcoOS_GetEnv(
++ IN gcoOS Os,
++ IN gctCONST_STRING VarName,
++ OUT gctSTRING * Value
++ );
++
++/* Set environment variable value. */
++gceSTATUS
++gcoOS_SetEnv(
++ IN gcoOS Os,
++ IN gctCONST_STRING VarName,
++ IN gctSTRING Value
++ );
++
++/* Get current working directory. */
++gceSTATUS
++gcoOS_GetCwd(
++ IN gcoOS Os,
++ IN gctINT SizeInBytes,
++ OUT gctSTRING Buffer
++ );
++
++/* Get file status info. */
++gceSTATUS
++gcoOS_Stat(
++ IN gcoOS Os,
++ IN gctCONST_STRING FileName,
++ OUT gctPOINTER Buffer
++ );
++
++typedef enum _gceFILE_WHENCE
++{
++ gcvFILE_SEEK_SET,
++ gcvFILE_SEEK_CUR,
++ gcvFILE_SEEK_END
++}
++gceFILE_WHENCE;
++
++/* Set the current position of a file. */
++gceSTATUS
++gcoOS_Seek(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctUINT32 Offset,
++ IN gceFILE_WHENCE Whence
++ );
++
++/* Set the current position of a file. */
++gceSTATUS
++gcoOS_SetPos(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctUINT32 Position
++ );
++
++/* Get the current position of a file. */
++gceSTATUS
++gcoOS_GetPos(
++ IN gcoOS Os,
++ IN gctFILE File,
++ OUT gctUINT32 * Position
++ );
++
++/* Same as strstr. */
++gceSTATUS
++gcoOS_StrStr(
++ IN gctCONST_STRING String,
++ IN gctCONST_STRING SubString,
++ OUT gctSTRING * Output
++ );
++
++/* Find the last occurance of a character inside a string. */
++gceSTATUS
++gcoOS_StrFindReverse(
++ IN gctCONST_STRING String,
++ IN gctINT8 Character,
++ OUT gctSTRING * Output
++ );
++
++gceSTATUS
++gcoOS_StrDup(
++ IN gcoOS Os,
++ IN gctCONST_STRING String,
++ OUT gctSTRING * Target
++ );
++
++/* Copy a string. */
++gceSTATUS
++gcoOS_StrCopySafe(
++ IN gctSTRING Destination,
++ IN gctSIZE_T DestinationSize,
++ IN gctCONST_STRING Source
++ );
++
++/* Append a string. */
++gceSTATUS
++gcoOS_StrCatSafe(
++ IN gctSTRING Destination,
++ IN gctSIZE_T DestinationSize,
++ IN gctCONST_STRING Source
++ );
++
++/* Compare two strings. */
++gceSTATUS
++gcoOS_StrCmp(
++ IN gctCONST_STRING String1,
++ IN gctCONST_STRING String2
++ );
++
++/* Compare characters of two strings. */
++gceSTATUS
++gcoOS_StrNCmp(
++ IN gctCONST_STRING String1,
++ IN gctCONST_STRING String2,
++ IN gctSIZE_T Count
++ );
++
++/* Convert string to float. */
++gceSTATUS
++gcoOS_StrToFloat(
++ IN gctCONST_STRING String,
++ OUT gctFLOAT * Float
++ );
++
++/* Convert hex string to integer. */
++gceSTATUS
++gcoOS_HexStrToInt(
++ IN gctCONST_STRING String,
++ OUT gctINT * Int
++ );
++
++/* Convert hex string to float. */
++gceSTATUS
++gcoOS_HexStrToFloat(
++ IN gctCONST_STRING String,
++ OUT gctFLOAT * Float
++ );
++
++/* Convert string to integer. */
++gceSTATUS
++gcoOS_StrToInt(
++ IN gctCONST_STRING String,
++ OUT gctINT * Int
++ );
++
++gceSTATUS
++gcoOS_MemCmp(
++ IN gctCONST_POINTER Memory1,
++ IN gctCONST_POINTER Memory2,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_PrintStrSafe(
++ OUT gctSTRING String,
++ IN gctSIZE_T StringSize,
++ IN OUT gctUINT * Offset,
++ IN gctCONST_STRING Format,
++ ...
++ );
++
++gceSTATUS
++gcoOS_LoadLibrary(
++ IN gcoOS Os,
++ IN gctCONST_STRING Library,
++ OUT gctHANDLE * Handle
++ );
++
++gceSTATUS
++gcoOS_FreeLibrary(
++ IN gcoOS Os,
++ IN gctHANDLE Handle
++ );
++
++gceSTATUS
++gcoOS_GetProcAddress(
++ IN gcoOS Os,
++ IN gctHANDLE Handle,
++ IN gctCONST_STRING Name,
++ OUT gctPOINTER * Function
++ );
++
++gceSTATUS
++gcoOS_Compact(
++ IN gcoOS Os
++ );
++
++gceSTATUS
++gcoOS_AddSignalHandler (
++ IN gceSignalHandlerType SignalHandlerType
++ );
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gcoOS_ProfileStart(
++ IN gcoOS Os
++ );
++
++gceSTATUS
++gcoOS_ProfileEnd(
++ IN gcoOS Os,
++ IN gctCONST_STRING Title
++ );
++
++gceSTATUS
++gcoOS_SetProfileSetting(
++ IN gcoOS Os,
++ IN gctBOOL Enable,
++ IN gctCONST_STRING FileName
++ );
++#endif
++
++gctBOOL
++gcoOS_IsNeededSupportNP2Texture(
++ IN gctCHAR* ProcName
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gcoOS_QueryVideoMemory(
++ IN gcoOS Os,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Detect if the process is the executable specified. */
++gceSTATUS
++gcoOS_DetectProcessByNamePid(
++ IN gctCONST_STRING Name,
++ IN gctHANDLE Pid
++ );
++
++/* Detect if the current process is the executable specified. */
++gceSTATUS
++gcoOS_DetectProcessByName(
++ IN gctCONST_STRING Name
++ );
++
++gceSTATUS
++gcoOS_DetectProcessByEncryptedName(
++ IN gctCONST_STRING Name
++ );
++
++#if defined(ANDROID)
++gceSTATUS
++gcoOS_DetectProgrameByEncryptedSymbols(
++ IN gcoOS_SymbolsList Symbols
++ );
++#endif
++
++/*----------------------------------------------------------------------------*/
++/*----- Atoms ----------------------------------------------------------------*/
++
++/* Construct an atom. */
++gceSTATUS
++gcoOS_AtomConstruct(
++ IN gcoOS Os,
++ OUT gcsATOM_PTR * Atom
++ );
++
++/* Destroy an atom. */
++gceSTATUS
++gcoOS_AtomDestroy(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom
++ );
++
++/* Increment an atom. */
++gceSTATUS
++gcoOS_AtomIncrement(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR OldValue
++ );
++
++/* Decrement an atom. */
++gceSTATUS
++gcoOS_AtomDecrement(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR OldValue
++ );
++
++gctHANDLE
++gcoOS_GetCurrentProcessID(
++ void
++ );
++
++gctHANDLE
++gcoOS_GetCurrentThreadID(
++ void
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Time -----------------------------------------------------------------*/
++
++/* Get the number of milliseconds since the system started. */
++gctUINT32
++gcoOS_GetTicks(
++ void
++ );
++
++/* Get time in microseconds. */
++gceSTATUS
++gcoOS_GetTime(
++ gctUINT64_PTR Time
++ );
++
++/* Get CPU usage in microseconds. */
++gceSTATUS
++gcoOS_GetCPUTime(
++ gctUINT64_PTR CPUTime
++ );
++
++/* Get memory usage. */
++gceSTATUS
++gcoOS_GetMemoryUsage(
++ gctUINT32_PTR MaxRSS,
++ gctUINT32_PTR IxRSS,
++ gctUINT32_PTR IdRSS,
++ gctUINT32_PTR IsRSS
++ );
++
++/* Delay a number of microseconds. */
++gceSTATUS
++gcoOS_Delay(
++ IN gcoOS Os,
++ IN gctUINT32 Delay
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Threads --------------------------------------------------------------*/
++
++#ifdef _WIN32
++/* Cannot include windows.h here becuase "near" and "far"
++ * which are used in gcsDEPTH_INFO, are defined to nothing in WinDef.h.
++ * So, use the real value of DWORD and WINAPI, instead.
++ * DWORD is unsigned long, and WINAPI is __stdcall.
++ * If these two are change in WinDef.h, the following two typdefs
++ * need to be changed, too.
++ */
++typedef unsigned long gctTHREAD_RETURN;
++typedef unsigned long (__stdcall * gcTHREAD_ROUTINE)(void * Argument);
++#else
++typedef void * gctTHREAD_RETURN;
++typedef void * (* gcTHREAD_ROUTINE)(void *);
++#endif
++
++/* Create a new thread. */
++gceSTATUS
++gcoOS_CreateThread(
++ IN gcoOS Os,
++ IN gcTHREAD_ROUTINE Worker,
++ IN gctPOINTER Argument,
++ OUT gctPOINTER * Thread
++ );
++
++/* Close a thread. */
++gceSTATUS
++gcoOS_CloseThread(
++ IN gcoOS Os,
++ IN gctPOINTER Thread
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Mutexes --------------------------------------------------------------*/
++
++/* Create a new mutex. */
++gceSTATUS
++gcoOS_CreateMutex(
++ IN gcoOS Os,
++ OUT gctPOINTER * Mutex
++ );
++
++/* Delete a mutex. */
++gceSTATUS
++gcoOS_DeleteMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Acquire a mutex. */
++gceSTATUS
++gcoOS_AcquireMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ );
++
++/* Release a mutex. */
++gceSTATUS
++gcoOS_ReleaseMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Signals --------------------------------------------------------------*/
++
++/* Create a signal. */
++gceSTATUS
++gcoOS_CreateSignal(
++ IN gcoOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ );
++
++/* Destroy a signal. */
++gceSTATUS
++gcoOS_DestroySignal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Signal a signal. */
++gceSTATUS
++gcoOS_Signal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ );
++
++/* Wait for a signal. */
++gceSTATUS
++gcoOS_WaitSignal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ );
++
++/* Map a signal from another process */
++gceSTATUS
++gcoOS_MapSignal(
++ IN gctSIGNAL RemoteSignal,
++ OUT gctSIGNAL * LocalSignal
++ );
++
++/* Unmap a signal mapped from another process */
++gceSTATUS
++gcoOS_UnmapSignal(
++ IN gctSIGNAL Signal
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Android Native Fence -------------------------------------------------*/
++
++/* Create sync point. */
++gceSTATUS
++gcoOS_CreateSyncPoint(
++ IN gcoOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ );
++
++/* Destroy sync point. */
++gceSTATUS
++gcoOS_DestroySyncPoint(
++ IN gcoOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++/* Create native fence. */
++gceSTATUS
++gcoOS_CreateNativeFence(
++ IN gcoOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ );
++
++/* Wait on native fence. */
++gceSTATUS
++gcoOS_WaitNativeFence(
++ IN gcoOS Os,
++ IN gctINT FenceFD,
++ IN gctUINT32 Timeout
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Memory Access and Cache ----------------------------------------------*/
++
++/* Write a register. */
++gceSTATUS
++gcoOS_WriteRegister(
++ IN gcoOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Read a register. */
++gceSTATUS
++gcoOS_ReadRegister(
++ IN gcoOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++gceSTATUS
++gcoOS_CacheClean(
++ IN gcoOS Os,
++ IN gctUINT64 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_CacheFlush(
++ IN gcoOS Os,
++ IN gctUINT64 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_CacheInvalidate(
++ IN gcoOS Os,
++ IN gctUINT64 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_MemoryBarrier(
++ IN gcoOS Os,
++ IN gctPOINTER Logical
++ );
++
++
++/*----------------------------------------------------------------------------*/
++/*----- Profile --------------------------------------------------------------*/
++
++gceSTATUS
++gckOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ );
++
++gceSTATUS
++gckOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ );
++
++gctUINT32
++gckOS_ProfileToMS(
++ IN gctUINT64 Ticks
++ );
++
++gceSTATUS
++gcoOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ );
++
++gceSTATUS
++gcoOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ );
++
++#define _gcmPROFILE_INIT(prefix, freq, start) \
++ do { \
++ prefix ## OS_QueryProfileTickRate(&(freq)); \
++ prefix ## OS_GetProfileTick(&(start)); \
++ } while (gcvFALSE)
++
++#define _gcmPROFILE_QUERY(prefix, start, ticks) \
++ do { \
++ prefix ## OS_GetProfileTick(&(ticks)); \
++ (ticks) = ((ticks) > (start)) ? ((ticks) - (start)) \
++ : (~0ull - (start) + (ticks) + 1); \
++ } while (gcvFALSE)
++
++#if gcdENABLE_PROFILING
++# define gcmkPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gck, freq, start)
++# define gcmkPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gck, start, ticks)
++# define gcmPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gco, freq, start)
++# define gcmPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gco, start, ticks)
++# define gcmPROFILE_ONLY(x) x
++# define gcmPROFILE_ELSE(x) do { } while (gcvFALSE)
++# define gcmPROFILE_DECLARE_ONLY(x) x
++# define gcmPROFILE_DECLARE_ELSE(x) typedef x
++#else
++# define gcmkPROFILE_INIT(start, freq) do { } while (gcvFALSE)
++# define gcmkPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
++# define gcmPROFILE_INIT(start, freq) do { } while (gcvFALSE)
++# define gcmPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
++# define gcmPROFILE_ONLY(x) do { } while (gcvFALSE)
++# define gcmPROFILE_ELSE(x) x
++# define gcmPROFILE_DECLARE_ONLY(x) do { } while (gcvFALSE)
++# define gcmPROFILE_DECLARE_ELSE(x) x
++#endif
++
++/*******************************************************************************
++** gcoMATH object
++*/
++
++#define gcdPI 3.14159265358979323846f
++
++/* Kernel. */
++gctINT
++gckMATH_ModuloInt(
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++/* User. */
++gctUINT32
++gcoMATH_Log2in5dot5(
++ IN gctINT X
++ );
++
++
++gctFLOAT
++gcoMATH_UIntAsFloat(
++ IN gctUINT32 X
++ );
++
++gctUINT32
++gcoMATH_FloatAsUInt(
++ IN gctFLOAT X
++ );
++
++gctBOOL
++gcoMATH_CompareEqualF(
++ IN gctFLOAT X,
++ IN gctFLOAT Y
++ );
++
++gctUINT16
++gcoMATH_UInt8AsFloat16(
++ IN gctUINT8 X
++ );
++
++/******************************************************************************\
++**************************** Coordinate Structures *****************************
++\******************************************************************************/
++
++typedef struct _gcsPOINT
++{
++ gctINT32 x;
++ gctINT32 y;
++}
++gcsPOINT;
++
++typedef struct _gcsSIZE
++{
++ gctINT32 width;
++ gctINT32 height;
++}
++gcsSIZE;
++
++typedef struct _gcsRECT
++{
++ gctINT32 left;
++ gctINT32 top;
++ gctINT32 right;
++ gctINT32 bottom;
++}
++gcsRECT;
++
++typedef union _gcsPIXEL
++{
++ struct
++ {
++ gctFLOAT r, g, b, a;
++ gctFLOAT d, s;
++ } pf;
++
++ struct
++ {
++ gctINT32 r, g, b, a;
++ gctINT32 d, s;
++ } pi;
++
++ struct
++ {
++ gctUINT32 r, g, b, a;
++ gctUINT32 d, s;
++ } pui;
++
++} gcsPIXEL;
++
++
++/******************************************************************************\
++********************************* gcoSURF Object ********************************
++\******************************************************************************/
++
++/*----------------------------------------------------------------------------*/
++/*------------------------------- gcoSURF Common ------------------------------*/
++
++/* Color format classes. */
++typedef enum _gceFORMAT_CLASS
++{
++ gcvFORMAT_CLASS_RGBA = 4500,
++ gcvFORMAT_CLASS_YUV,
++ gcvFORMAT_CLASS_INDEX,
++ gcvFORMAT_CLASS_LUMINANCE,
++ gcvFORMAT_CLASS_BUMP,
++ gcvFORMAT_CLASS_DEPTH,
++}
++gceFORMAT_CLASS;
++
++/* Special enums for width field in gcsFORMAT_COMPONENT. */
++typedef enum _gceCOMPONENT_CONTROL
++{
++ gcvCOMPONENT_NOTPRESENT = 0x00,
++ gcvCOMPONENT_DONTCARE = 0x80,
++ gcvCOMPONENT_WIDTHMASK = 0x7F,
++ gcvCOMPONENT_ODD = 0x80
++}
++gceCOMPONENT_CONTROL;
++
++/* Color format component parameters. */
++typedef struct _gcsFORMAT_COMPONENT
++{
++ gctUINT8 start;
++ gctUINT8 width;
++}
++gcsFORMAT_COMPONENT;
++
++/* RGBA color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_RGBA
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT red;
++ gcsFORMAT_COMPONENT green;
++ gcsFORMAT_COMPONENT blue;
++}
++gcsFORMAT_CLASS_TYPE_RGBA;
++
++/* YUV color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_YUV
++{
++ gcsFORMAT_COMPONENT y;
++ gcsFORMAT_COMPONENT u;
++ gcsFORMAT_COMPONENT v;
++}
++gcsFORMAT_CLASS_TYPE_YUV;
++
++/* Index color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_INDEX
++{
++ gcsFORMAT_COMPONENT value;
++}
++gcsFORMAT_CLASS_TYPE_INDEX;
++
++/* Luminance color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_LUMINANCE
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT value;
++}
++gcsFORMAT_CLASS_TYPE_LUMINANCE;
++
++/* Bump map color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_BUMP
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT l;
++ gcsFORMAT_COMPONENT v;
++ gcsFORMAT_COMPONENT u;
++ gcsFORMAT_COMPONENT q;
++ gcsFORMAT_COMPONENT w;
++}
++gcsFORMAT_CLASS_TYPE_BUMP;
++
++/* Depth and stencil format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_DEPTH
++{
++ gcsFORMAT_COMPONENT depth;
++ gcsFORMAT_COMPONENT stencil;
++}
++gcsFORMAT_CLASS_TYPE_DEPTH;
++
++/* Format parameters. */
++typedef struct _gcsSURF_FORMAT_INFO
++{
++ /* Format code and class. */
++ gceSURF_FORMAT format;
++ gceFORMAT_CLASS fmtClass;
++
++ /* The size of one pixel in bits. */
++ gctUINT8 bitsPerPixel;
++
++ /* Component swizzle. */
++ gceSURF_SWIZZLE swizzle;
++
++ /* Some formats have two neighbour pixels interleaved together. */
++ /* To describe such format, set the flag to 1 and add another */
++ /* like this one describing the odd pixel format. */
++ gctUINT8 interleaved;
++
++ /* Format components. */
++ union
++ {
++ gcsFORMAT_CLASS_TYPE_BUMP bump;
++ gcsFORMAT_CLASS_TYPE_RGBA rgba;
++ gcsFORMAT_CLASS_TYPE_YUV yuv;
++ gcsFORMAT_CLASS_TYPE_LUMINANCE lum;
++ gcsFORMAT_CLASS_TYPE_INDEX index;
++ gcsFORMAT_CLASS_TYPE_DEPTH depth;
++ } u;
++}
++gcsSURF_FORMAT_INFO;
++
++/* Frame buffer information. */
++typedef struct _gcsSURF_FRAMEBUFFER
++{
++ gctPOINTER logical;
++ gctUINT width, height;
++ gctINT stride;
++ gceSURF_FORMAT format;
++}
++gcsSURF_FRAMEBUFFER;
++
++typedef struct _gcsVIDMEM_NODE_SHARED_INFO
++{
++ gctBOOL tileStatusDisabled;
++ gcsPOINT SrcOrigin;
++ gcsPOINT DestOrigin;
++ gcsSIZE RectSize;
++ gctUINT32 clearValue;
++}
++gcsVIDMEM_NODE_SHARED_INFO;
++
++/* Generic pixel component descriptors. */
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XXX8;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XX8X;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_X8XX;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_8XXX;
++
++typedef enum _gceORIENTATION
++{
++ gcvORIENTATION_TOP_BOTTOM,
++ gcvORIENTATION_BOTTOM_TOP,
++}
++gceORIENTATION;
++
++
++/* Construct a new gcoSURF object. */
++gceSTATUS
++gcoSURF_Construct(
++ IN gcoHAL Hal,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gcePOOL Pool,
++ OUT gcoSURF * Surface
++ );
++
++/* Destroy an gcoSURF object. */
++gceSTATUS
++gcoSURF_Destroy(
++ IN gcoSURF Surface
++ );
++
++/* Map user-allocated surface. */
++gceSTATUS
++gcoSURF_MapUserSurface(
++ IN gcoSURF Surface,
++ IN gctUINT Alignment,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++/* Query vid mem node info. */
++gceSTATUS
++gcoSURF_QueryVidMemNode(
++ IN gcoSURF Surface,
++ OUT gctUINT64 * Node,
++ OUT gcePOOL * Pool,
++ OUT gctUINT_PTR Bytes
++ );
++
++/* Set the color type of the surface. */
++gceSTATUS
++gcoSURF_SetColorType(
++ IN gcoSURF Surface,
++ IN gceSURF_COLOR_TYPE ColorType
++ );
++
++/* Get the color type of the surface. */
++gceSTATUS
++gcoSURF_GetColorType(
++ IN gcoSURF Surface,
++ OUT gceSURF_COLOR_TYPE *ColorType
++ );
++
++/* Set the surface ration angle. */
++gceSTATUS
++gcoSURF_SetRotation(
++ IN gcoSURF Surface,
++ IN gceSURF_ROTATION Rotation
++ );
++
++gceSTATUS
++gcoSURF_SetPreRotation(
++ IN gcoSURF Surface,
++ IN gceSURF_ROTATION Rotation
++ );
++
++gceSTATUS
++gcoSURF_GetPreRotation(
++ IN gcoSURF Surface,
++ IN gceSURF_ROTATION *Rotation
++ );
++
++gceSTATUS
++gcoSURF_IsValid(
++ IN gcoSURF Surface
++ );
++
++#ifndef VIVANTE_NO_3D
++/* Verify and return the state of the tile status mechanism. */
++gceSTATUS
++gcoSURF_IsTileStatusSupported(
++ IN gcoSURF Surface
++ );
++
++/* Process tile status for the specified surface. */
++gceSTATUS
++gcoSURF_SetTileStatus(
++ IN gcoSURF Surface
++ );
++
++/* Enable tile status for the specified surface. */
++gceSTATUS
++gcoSURF_EnableTileStatus(
++ IN gcoSURF Surface
++ );
++
++/* Disable tile status for the specified surface. */
++gceSTATUS
++gcoSURF_DisableTileStatus(
++ IN gcoSURF Surface,
++ IN gctBOOL Decompress
++ );
++
++gceSTATUS
++gcoSURF_AlignResolveRect(
++ IN gcoSURF Surf,
++ IN gcsPOINT_PTR RectOrigin,
++ IN gcsPOINT_PTR RectSize,
++ OUT gcsPOINT_PTR AlignedOrigin,
++ OUT gcsPOINT_PTR AlignedSize
++ );
++#endif /* VIVANTE_NO_3D */
++
++/* Get surface size. */
++gceSTATUS
++gcoSURF_GetSize(
++ IN gcoSURF Surface,
++ OUT gctUINT * Width,
++ OUT gctUINT * Height,
++ OUT gctUINT * Depth
++ );
++
++/* Get surface aligned sizes. */
++gceSTATUS
++gcoSURF_GetAlignedSize(
++ IN gcoSURF Surface,
++ OUT gctUINT * Width,
++ OUT gctUINT * Height,
++ OUT gctINT * Stride
++ );
++
++/* Get alignments. */
++gceSTATUS
++gcoSURF_GetAlignment(
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT * AddressAlignment,
++ OUT gctUINT * XAlignment,
++ OUT gctUINT * YAlignment
++ );
++
++/* Get surface type and format. */
++gceSTATUS
++gcoSURF_GetFormat(
++ IN gcoSURF Surface,
++ OUT gceSURF_TYPE * Type,
++ OUT gceSURF_FORMAT * Format
++ );
++
++/* Get surface tiling. */
++gceSTATUS
++gcoSURF_GetTiling(
++ IN gcoSURF Surface,
++ OUT gceTILING * Tiling
++ );
++
++/* Lock the surface. */
++gceSTATUS
++gcoSURF_Lock(
++ IN gcoSURF Surface,
++ IN OUT gctUINT32 * Address,
++ IN OUT gctPOINTER * Memory
++ );
++
++/* Unlock the surface. */
++gceSTATUS
++gcoSURF_Unlock(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory
++ );
++
++/* Return pixel format parameters. */
++gceSTATUS
++gcoSURF_QueryFormat(
++ IN gceSURF_FORMAT Format,
++ OUT gcsSURF_FORMAT_INFO_PTR * Info
++ );
++
++/* Compute the color pixel mask. */
++gceSTATUS
++gcoSURF_ComputeColorMask(
++ IN gcsSURF_FORMAT_INFO_PTR Format,
++ OUT gctUINT32_PTR ColorMask
++ );
++
++/* Flush the surface. */
++gceSTATUS
++gcoSURF_Flush(
++ IN gcoSURF Surface
++ );
++
++/* Fill surface from it's tile status buffer. */
++gceSTATUS
++gcoSURF_FillFromTile(
++ IN gcoSURF Surface
++ );
++
++/* Check if surface needs a filler. */
++gceSTATUS gcoSURF_NeedFiller(IN gcoSURF Surface);
++
++/* Fill surface with a value. */
++gceSTATUS
++gcoSURF_Fill(
++ IN gcoSURF Surface,
++ IN gcsPOINT_PTR Origin,
++ IN gcsSIZE_PTR Size,
++ IN gctUINT32 Value,
++ IN gctUINT32 Mask
++ );
++
++/* Alpha blend two surfaces together. */
++gceSTATUS
++gcoSURF_Blend(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrig,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsSIZE_PTR Size,
++ IN gceSURF_BLEND_MODE Mode
++ );
++
++/* Create a new gcoSURF wrapper object. */
++gceSTATUS
++gcoSURF_ConstructWrapper(
++ IN gcoHAL Hal,
++ OUT gcoSURF * Surface
++ );
++
++/* Set the underlying buffer for the surface wrapper. */
++gceSTATUS
++gcoSURF_SetBuffer(
++ IN gcoSURF Surface,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Stride,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++/* Set the underlying video buffer for the surface wrapper. */
++gceSTATUS
++gcoSURF_SetVideoBuffer(
++ IN gcoSURF Surface,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Stride,
++ IN gctPOINTER *LogicalPlane1,
++ IN gctUINT32 *PhysicalPlane1
++ );
++
++/* Set the size of the surface in pixels and map the underlying buffer. */
++gceSTATUS
++gcoSURF_SetWindow(
++ IN gcoSURF Surface,
++ IN gctUINT X,
++ IN gctUINT Y,
++ IN gctUINT Width,
++ IN gctUINT Height
++ );
++
++/* Set width/height alignment of the surface directly and calculate stride/size. This is only for dri backend now. Please be careful before use. */
++gceSTATUS
++gcoSURF_SetAlignment(
++ IN gcoSURF Surface,
++ IN gctUINT Width,
++ IN gctUINT Height
++ );
++
++/* Increase reference count of the surface. */
++gceSTATUS
++gcoSURF_ReferenceSurface(
++ IN gcoSURF Surface
++ );
++
++/* Get surface reference count. */
++gceSTATUS
++gcoSURF_QueryReferenceCount(
++ IN gcoSURF Surface,
++ OUT gctINT32 * ReferenceCount
++ );
++
++/* Set surface orientation. */
++gceSTATUS
++gcoSURF_SetOrientation(
++ IN gcoSURF Surface,
++ IN gceORIENTATION Orientation
++ );
++
++/* Query surface orientation. */
++gceSTATUS
++gcoSURF_QueryOrientation(
++ IN gcoSURF Surface,
++ OUT gceORIENTATION * Orientation
++ );
++
++gceSTATUS
++gcoSURF_SetOffset(
++ IN gcoSURF Surface,
++ IN gctUINT Offset
++ );
++
++gceSTATUS
++gcoSURF_GetOffset(
++ IN gcoSURF Surface,
++ OUT gctUINT *Offset
++ );
++
++gceSTATUS
++gcoSURF_NODE_Cache(
++ IN gcsSURF_NODE_PTR Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Perform CPU cache operation on surface */
++gceSTATUS
++gcoSURF_CPUCacheOperation(
++ IN gcoSURF Surface,
++ IN gceCACHEOPERATION Operation
++ );
++
++
++gceSTATUS
++gcoSURF_SetLinearResolveAddress(
++ IN gcoSURF Surface,
++ IN gctUINT32 Address,
++ IN gctPOINTER Memory
++ );
++
++ gceSTATUS
++ gcoSURF_Swap(IN gcoSURF Surface1, IN gcoSURF Surface2);
++
++/******************************************************************************\
++********************************* gcoDUMP Object ********************************
++\******************************************************************************/
++
++/* Construct a new gcoDUMP object. */
++gceSTATUS
++gcoDUMP_Construct(
++ IN gcoOS Os,
++ IN gcoHAL Hal,
++ OUT gcoDUMP * Dump
++ );
++
++/* Destroy a gcoDUMP object. */
++gceSTATUS
++gcoDUMP_Destroy(
++ IN gcoDUMP Dump
++ );
++
++/* Enable/disable dumping. */
++gceSTATUS
++gcoDUMP_Control(
++ IN gcoDUMP Dump,
++ IN gctSTRING FileName
++ );
++
++gceSTATUS
++gcoDUMP_IsEnabled(
++ IN gcoDUMP Dump,
++ OUT gctBOOL * Enabled
++ );
++
++/* Add surface. */
++gceSTATUS
++gcoDUMP_AddSurface(
++ IN gcoDUMP Dump,
++ IN gctINT32 Width,
++ IN gctINT32 Height,
++ IN gceSURF_FORMAT PixelFormat,
++ IN gctUINT32 Address,
++ IN gctSIZE_T ByteCount
++ );
++
++/* Mark the beginning of a frame. */
++gceSTATUS
++gcoDUMP_FrameBegin(
++ IN gcoDUMP Dump
++ );
++
++/* Mark the end of a frame. */
++gceSTATUS
++gcoDUMP_FrameEnd(
++ IN gcoDUMP Dump
++ );
++
++/* Dump data. */
++gceSTATUS
++gcoDUMP_DumpData(
++ IN gcoDUMP Dump,
++ IN gceDUMP_TAG Type,
++ IN gctUINT32 Address,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Delete an address. */
++gceSTATUS
++gcoDUMP_Delete(
++ IN gcoDUMP Dump,
++ IN gctUINT32 Address
++ );
++
++/* Enable dump or not. */
++gceSTATUS
++gcoDUMP_SetDumpFlag(
++ IN gctBOOL DumpState
++ );
++
++/******************************************************************************\
++******************************* gcsRECT Structure ******************************
++\******************************************************************************/
++
++/* Initialize rectangle structure. */
++gceSTATUS
++gcsRECT_Set(
++ OUT gcsRECT_PTR Rect,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Return the width of the rectangle. */
++gceSTATUS
++gcsRECT_Width(
++ IN gcsRECT_PTR Rect,
++ OUT gctINT32 * Width
++ );
++
++/* Return the height of the rectangle. */
++gceSTATUS
++gcsRECT_Height(
++ IN gcsRECT_PTR Rect,
++ OUT gctINT32 * Height
++ );
++
++/* Ensure that top left corner is to the left and above the right bottom. */
++gceSTATUS
++gcsRECT_Normalize(
++ IN OUT gcsRECT_PTR Rect
++ );
++
++/* Compare two rectangles. */
++gceSTATUS
++gcsRECT_IsEqual(
++ IN gcsRECT_PTR Rect1,
++ IN gcsRECT_PTR Rect2,
++ OUT gctBOOL * Equal
++ );
++
++/* Compare the sizes of two rectangles. */
++gceSTATUS
++gcsRECT_IsOfEqualSize(
++ IN gcsRECT_PTR Rect1,
++ IN gcsRECT_PTR Rect2,
++ OUT gctBOOL * EqualSize
++ );
++
++gceSTATUS
++gcsRECT_RelativeRotation(
++ IN gceSURF_ROTATION Orientation,
++ IN OUT gceSURF_ROTATION *Relation);
++
++gceSTATUS
++
++gcsRECT_Rotate(
++
++ IN OUT gcsRECT_PTR Rect,
++
++ IN gceSURF_ROTATION Rotation,
++
++ IN gceSURF_ROTATION toRotation,
++
++ IN gctINT32 SurfaceWidth,
++
++ IN gctINT32 SurfaceHeight
++
++ );
++
++/******************************************************************************\
++**************************** gcsBOUNDARY Structure *****************************
++\******************************************************************************/
++
++typedef struct _gcsBOUNDARY
++{
++ gctINT x;
++ gctINT y;
++ gctINT width;
++ gctINT height;
++}
++gcsBOUNDARY;
++
++/******************************************************************************\
++********************************* gcoHEAP Object ********************************
++\******************************************************************************/
++
++typedef struct _gcoHEAP * gcoHEAP;
++
++/* Construct a new gcoHEAP object. */
++gceSTATUS
++gcoHEAP_Construct(
++ IN gcoOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gcoHEAP * Heap
++ );
++
++/* Destroy an gcoHEAP object. */
++gceSTATUS
++gcoHEAP_Destroy(
++ IN gcoHEAP Heap
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoHEAP_Allocate(
++ IN gcoHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcoHEAP_GetMemorySize(
++ IN gcoHEAP Heap,
++ IN gctPOINTER Memory,
++ OUT gctSIZE_T_PTR MemorySize
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoHEAP_Free(
++ IN gcoHEAP Heap,
++ IN gctPOINTER Node
++ );
++
++#if (VIVANTE_PROFILER || gcdDEBUG)
++/* Profile the heap. */
++gceSTATUS
++gcoHEAP_ProfileStart(
++ IN gcoHEAP Heap
++ );
++
++gceSTATUS
++gcoHEAP_ProfileEnd(
++ IN gcoHEAP Heap,
++ IN gctCONST_STRING Title
++ );
++#endif
++
++
++/******************************************************************************\
++******************************* Debugging Macros *******************************
++\******************************************************************************/
++
++void
++gcoOS_SetDebugLevel(
++ IN gctUINT32 Level
++ );
++
++void
++gcoOS_GetDebugLevel(
++ OUT gctUINT32_PTR DebugLevel
++ );
++
++void
++gcoOS_SetDebugZone(
++ IN gctUINT32 Zone
++ );
++
++void
++gcoOS_GetDebugZone(
++ IN gctUINT32 Zone,
++ OUT gctUINT32_PTR DebugZone
++ );
++
++void
++gcoOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ );
++
++void
++gcoOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ );
++
++void
++gcoOS_SetDebugFile(
++ IN gctCONST_STRING FileName
++ );
++
++gctFILE
++gcoOS_ReplaceDebugFile(
++ IN gctFILE fp
++ );
++
++/*******************************************************************************
++**
++** gcmFATAL
++**
++** Print a message to the debugger and execute a break point.
++**
++** ARGUMENTS:
++**
++** message Message.
++** ... Optional arguments.
++*/
++
++void
++gckOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_FATAL)
++# define gcmFATAL gcoOS_DebugFatal
++# define gcmkFATAL gckOS_DebugFatal
++#elif gcdHAS_ELLIPSES
++# define gcmFATAL(...)
++# define gcmkFATAL(...)
++#else
++ gcmINLINE static void
++ __dummy_fatal(
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmFATAL __dummy_fatal
++# define gcmkFATAL __dummy_fatal
++#endif
++
++#define gcmENUM2TEXT(e) case e: return #e
++
++/*******************************************************************************
++**
++** gcmTRACE
++**
++** Print a message to the debugfer if the correct level has been set. In
++** retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** level Level of message.
++** message Message.
++** ... Optional arguments.
++*/
++#define gcvLEVEL_NONE -1
++#define gcvLEVEL_ERROR 0
++#define gcvLEVEL_WARNING 1
++#define gcvLEVEL_INFO 2
++#define gcvLEVEL_VERBOSE 3
++
++void
++gckOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_DebugTraceN(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmTRACE gcoOS_DebugTrace
++# define gcmkTRACE gckOS_DebugTrace
++# define gcmkTRACE_N gckOS_DebugTraceN
++#elif gcdHAS_ELLIPSES
++# define gcmTRACE(...)
++# define gcmkTRACE(...)
++# define gcmkTRACE_N(...)
++#else
++ gcmINLINE static void
++ __dummy_trace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++ gcmINLINE static void
++ __dummy_trace_n(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++# define gcmTRACE __dummy_trace
++# define gcmkTRACE __dummy_trace
++# define gcmkTRACE_N __dummy_trace_n
++#endif
++
++/* Zones common for kernel and user. */
++#define gcvZONE_OS (1 << 0)
++#define gcvZONE_HARDWARE (1 << 1)
++#define gcvZONE_HEAP (1 << 2)
++#define gcvZONE_SIGNAL (1 << 27)
++
++/* Kernel zones. */
++#define gcvZONE_KERNEL (1 << 3)
++#define gcvZONE_VIDMEM (1 << 4)
++#define gcvZONE_COMMAND (1 << 5)
++#define gcvZONE_DRIVER (1 << 6)
++#define gcvZONE_CMODEL (1 << 7)
++#define gcvZONE_MMU (1 << 8)
++#define gcvZONE_EVENT (1 << 9)
++#define gcvZONE_DEVICE (1 << 10)
++#define gcvZONE_DATABASE (1 << 11)
++#define gcvZONE_INTERRUPT (1 << 12)
++#define gcvZONE_POWER (1 << 13)
++
++/* User zones. */
++#define gcvZONE_HAL (1 << 3)
++#define gcvZONE_BUFFER (1 << 4)
++#define gcvZONE_CONTEXT (1 << 5)
++#define gcvZONE_SURFACE (1 << 6)
++#define gcvZONE_INDEX (1 << 7)
++#define gcvZONE_STREAM (1 << 8)
++#define gcvZONE_TEXTURE (1 << 9)
++#define gcvZONE_2D (1 << 10)
++#define gcvZONE_3D (1 << 11)
++#define gcvZONE_COMPILER (1 << 12)
++#define gcvZONE_MEMORY (1 << 13)
++#define gcvZONE_STATE (1 << 14)
++#define gcvZONE_AUX (1 << 15)
++#define gcvZONE_VERTEX (1 << 16)
++#define gcvZONE_CL (1 << 17)
++#define gcvZONE_COMPOSITION (1 << 17)
++#define gcvZONE_VG (1 << 18)
++#define gcvZONE_IMAGE (1 << 19)
++#define gcvZONE_UTILITY (1 << 20)
++#define gcvZONE_PARAMETERS (1 << 21)
++
++/* API definitions. */
++#define gcvZONE_API_HAL (1 << 28)
++#define gcvZONE_API_EGL (2 << 28)
++#define gcvZONE_API_ES11 (3 << 28)
++#define gcvZONE_API_ES20 (4 << 28)
++#define gcvZONE_API_VG11 (5 << 28)
++#define gcvZONE_API_GL (6 << 28)
++#define gcvZONE_API_DFB (7 << 28)
++#define gcvZONE_API_GDI (8 << 28)
++#define gcvZONE_API_D3D (9 << 28)
++#define gcvZONE_API_ES30 (10 << 28)
++
++
++#define gcmZONE_GET_API(zone) ((zone) >> 28)
++/*Set gcdZONE_MASE like 0x0 | gcvZONE_API_EGL
++will enable print EGL module debug info*/
++#define gcdZONE_MASK 0x0FFFFFFF
++
++/* Handy zones. */
++#define gcvZONE_NONE 0
++#define gcvZONE_ALL 0x0FFFFFFF
++
++/*Dump API depth set 1 for API, 2 for API and API behavior*/
++#define gcvDUMP_API_DEPTH 1
++
++/*******************************************************************************
++**
++** gcmTRACE_ZONE
++**
++** Print a message to the debugger if the correct level and zone has been
++** set. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** Level Level of message.
++** Zone Zone of message.
++** Message Message.
++** ... Optional arguments.
++*/
++
++void
++gckOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_DebugTraceZoneN(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmTRACE_ZONE gcoOS_DebugTraceZone
++# define gcmkTRACE_ZONE gckOS_DebugTraceZone
++# define gcmkTRACE_ZONE_N gckOS_DebugTraceZoneN
++#elif gcdHAS_ELLIPSES
++# define gcmTRACE_ZONE(...)
++# define gcmkTRACE_ZONE(...)
++# define gcmkTRACE_ZONE_N(...)
++#else
++ gcmINLINE static void
++ __dummy_trace_zone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++ gcmINLINE static void
++ __dummy_trace_zone_n(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++# define gcmTRACE_ZONE __dummy_trace_zone
++# define gcmkTRACE_ZONE __dummy_trace_zone
++# define gcmkTRACE_ZONE_N __dummy_trace_zone_n
++#endif
++
++/*******************************************************************************
++**
++** gcmDEBUG_ONLY
++**
++** Execute a statement or function only in DEBUG mode.
++**
++** ARGUMENTS:
++**
++** f Statement or function to execute.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++# define gcmDEBUG_ONLY(f) f
++#else
++# define gcmDEBUG_ONLY(f)
++#endif
++
++/*******************************************************************************
++**
++** gcmSTACK_PUSH
++** gcmSTACK_POP
++** gcmSTACK_DUMP
++**
++** Push or pop a function with entry arguments on the trace stack.
++**
++** ARGUMENTS:
++**
++** Function Name of function.
++** Line Line number.
++** Text Optional text.
++** ... Optional arguments for text.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_STACK)
++ void
++ gcoOS_StackPush(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text,
++ ...
++ );
++ void
++ gcoOS_StackPop(
++ IN gctCONST_STRING Function
++ );
++ void
++ gcoOS_StackDump(
++ void
++ );
++# define gcmSTACK_PUSH gcoOS_StackPush
++# define gcmSTACK_POP gcoOS_StackPop
++# define gcmSTACK_DUMP gcoOS_StackDump
++#elif gcdHAS_ELLIPSES
++# define gcmSTACK_PUSH(...) do { } while (0)
++# define gcmSTACK_POP(Function) do { } while (0)
++# define gcmSTACK_DUMP() do { } while (0)
++#else
++ gcmINLINE static void
++ __dummy_stack_push(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text, ...
++ )
++ {
++ }
++# define gcmSTACK_PUSH __dummy_stack_push
++# define gcmSTACK_POP(Function) do { } while (0)
++# define gcmSTACK_DUMP() do { } while (0)
++#endif
++
++/******************************************************************************\
++******************************** Logging Macros ********************************
++\******************************************************************************/
++
++#define gcdHEADER_LEVEL gcvLEVEL_VERBOSE
++
++
++#if gcdENABLE_PROFILING
++void
++gcoOS_ProfileDB(
++ IN gctCONST_STRING Function,
++ IN OUT gctBOOL_PTR Initialized
++ );
++
++#define gcmHEADER() \
++ static gctBOOL __profile__initialized__ = gcvFALSE; \
++ gcmSTACK_PUSH(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__)
++#define gcmHEADER_ARG(...) \
++ static gctBOOL __profile__initialized__ = gcvFALSE; \
++ gcmSTACK_PUSH(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__)
++#define gcmFOOTER() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_NO() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_ARG(...) \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_KILL() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcoOS_ProfileDB(gcvNULL, gcvNULL)
++
++#else /* gcdENABLE_PROFILING */
++
++#if gcdHAS_ELLIPSES
++#define gcmHEADER() \
++ gctINT8 __user__ = 1; \
++ gctINT8_PTR __user_ptr__ = &__user__; \
++ gcmSTACK_PUSH(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d)", __FUNCTION__, __LINE__)
++#else
++ gcmINLINE static void
++ __dummy_header(void)
++ {
++ }
++# define gcmHEADER __dummy_header
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmHEADER_ARG(Text, ...) \
++ gctINT8 __user__ = 1; \
++ gctINT8_PTR __user_ptr__ = &__user__; \
++ gcmSTACK_PUSH(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__)
++#else
++ gcmINLINE static void
++ __dummy_header_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmHEADER_ARG __dummy_header_arg
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmFOOTER() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcmPROFILE_ONLY(gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d) [%llu,%llu]: status=%d(%s)", \
++ __FUNCTION__, __LINE__, \
++ __ticks__, __total__, \
++ status, gcoOS_DebugStatus2Name(status))); \
++ gcmPROFILE_ELSE(gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): status=%d(%s)", \
++ __FUNCTION__, __LINE__, \
++ status, gcoOS_DebugStatus2Name(status))); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer(void)
++ {
++ }
++# define gcmFOOTER __dummy_footer
++#endif
++
++#if gcdHAS_ELLIPSES
++#define gcmFOOTER_NO() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_no(void)
++ {
++ }
++# define gcmFOOTER_NO __dummy_footer_no
++#endif
++
++#if gcdHAS_ELLIPSES
++#define gcmFOOTER_KILL() \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_kill(void)
++ {
++ }
++# define gcmFOOTER_KILL __dummy_footer_kill
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmFOOTER_ARG(Text, ...) \
++ gcmSTACK_POP(__FUNCTION__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmFOOTER_ARG __dummy_footer_arg
++#endif
++
++#endif /* gcdENABLE_PROFILING */
++
++#if gcdHAS_ELLIPSES
++#define gcmkHEADER() \
++ gctINT8 __kernel__ = 1; \
++ gctINT8_PTR __kernel_ptr__ = &__kernel__; \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d)", __FUNCTION__, __LINE__)
++#else
++ gcmINLINE static void
++ __dummy_kheader(void)
++ {
++ }
++# define gcmkHEADER __dummy_kheader
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmkHEADER_ARG(Text, ...) \
++ gctINT8 __kernel__ = 1; \
++ gctINT8_PTR __kernel_ptr__ = &__kernel__; \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__)
++#else
++ gcmINLINE static void
++ __dummy_kheader_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmkHEADER_ARG __dummy_kheader_arg
++#endif
++
++#if gcdHAS_ELLIPSES
++#define gcmkFOOTER() \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): status=%d(%s)", \
++ __FUNCTION__, __LINE__, status, gckOS_DebugStatus2Name(status)); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter(void)
++ {
++ }
++# define gcmkFOOTER __dummy_kfooter
++#endif
++
++#if gcdHAS_ELLIPSES
++#define gcmkFOOTER_NO() \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter_no(void)
++ {
++ }
++# define gcmkFOOTER_NO __dummy_kfooter_no
++#endif
++
++#if gcdHAS_ELLIPSES
++# define gcmkFOOTER_ARG(Text, ...) \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): " Text, \
++ __FUNCTION__, __LINE__, __VA_ARGS__); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmkFOOTER_ARG __dummy_kfooter_arg
++#endif
++
++#define gcmOPT_VALUE(ptr) (((ptr) == gcvNULL) ? 0 : *(ptr))
++#define gcmOPT_VALUE_INDEX(ptr, index) (((ptr) == gcvNULL) ? 0 : ptr[index])
++#define gcmOPT_POINTER(ptr) (((ptr) == gcvNULL) ? gcvNULL : *(ptr))
++#define gcmOPT_STRING(ptr) (((ptr) == gcvNULL) ? "(nil)" : (ptr))
++
++void
++gckOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_PrintN(
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_CopyPrint(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#define gcmPRINT gcoOS_Print
++#define gcmkPRINT gckOS_Print
++#define gcmkPRINT_N gckOS_PrintN
++
++#if gcdPRINT_VERSION
++# define gcmPRINT_VERSION() do { \
++ _gcmPRINT_VERSION(gcm); \
++ gcmSTACK_DUMP(); \
++ } while (0)
++# define gcmkPRINT_VERSION() _gcmPRINT_VERSION(gcmk)
++# define _gcmPRINT_VERSION(prefix) \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ "Vivante HAL version %d.%d.%d build %d %s %s", \
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, \
++ gcvVERSION_BUILD, gcvVERSION_DATE, gcvVERSION_TIME )
++#else
++# define gcmPRINT_VERSION() do { gcmSTACK_DUMP(); } while (gcvFALSE)
++# define gcmkPRINT_VERSION() do { } while (gcvFALSE)
++#endif
++
++typedef enum _gceDUMP_BUFFER
++{
++ gceDUMP_BUFFER_CONTEXT,
++ gceDUMP_BUFFER_USER,
++ gceDUMP_BUFFER_KERNEL,
++ gceDUMP_BUFFER_LINK,
++ gceDUMP_BUFFER_WAITLINK,
++ gceDUMP_BUFFER_FROM_USER,
++}
++gceDUMP_BUFFER;
++
++void
++gckOS_DumpBuffer(
++ IN gckOS Os,
++ IN gctPOINTER Buffer,
++ IN gctUINT Size,
++ IN gceDUMP_BUFFER Type,
++ IN gctBOOL CopyMessage
++ );
++
++#define gcmkDUMPBUFFER gckOS_DumpBuffer
++
++#if gcdDUMP_COMMAND
++# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage) \
++ gcmkDUMPBUFFER(Os, Buffer, Size, Type, CopyMessage)
++#else
++# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage)
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++
++void
++gckOS_DebugFlush(
++ gctCONST_STRING CallerName,
++ gctUINT LineNumber,
++ gctUINT32 DmaAddress
++ );
++
++# define gcmkDEBUGFLUSH(DmaAddress) \
++ gckOS_DebugFlush(__FUNCTION__, __LINE__, DmaAddress)
++#else
++# define gcmkDEBUGFLUSH(DmaAddress)
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_FRAMERATE
++**
++** Print average frame rate
++**
++*/
++#if gcdDUMP_FRAMERATE
++ gceSTATUS
++ gcfDumpFrameRate(
++ void
++ );
++# define gcmDUMP_FRAMERATE gcfDumpFrameRate
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_FRAMERATE(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_frame_rate(
++ void
++ )
++ {
++ }
++# define gcmDUMP_FRAMERATE __dummy_dump_frame_rate
++#endif
++
++
++/*******************************************************************************
++**
++** gcmDUMP
++**
++** Print a dump message.
++**
++** ARGUMENTS:
++**
++** gctSTRING Message.
++**
++** ... Optional arguments.
++*/
++#if gcdDUMP
++ gceSTATUS
++ gcfDump(
++ IN gcoOS Os,
++ IN gctCONST_STRING String,
++ ...
++ );
++# define gcmDUMP gcfDump
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP(...)
++#else
++ gcmINLINE static void
++ __dummy_dump(
++ IN gcoOS Os,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmDUMP __dummy_dump
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_DATA
++**
++** Add data to the dump.
++**
++** ARGUMENTS:
++**
++** gctSTRING Tag
++** Tag for dump.
++**
++** gctPOINTER Logical
++** Logical address of buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes.
++*/
++
++#if gcdDUMP || gcdDUMP_COMMAND
++ gceSTATUS
++ gcfDumpData(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++# define gcmDUMP_DATA gcfDumpData
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_DATA(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_data(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++ {
++ }
++# define gcmDUMP_DATA __dummy_dump_data
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_BUFFER
++**
++** Print a buffer to the dump.
++**
++** ARGUMENTS:
++**
++** gctSTRING Tag
++** Tag for dump.
++**
++** gctUINT32 Physical
++** Physical address of buffer.
++**
++** gctPOINTER Logical
++** Logical address of buffer.
++**
++** gctUINT32 Offset
++** Offset into buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes.
++*/
++
++#if gcdDUMP || gcdDUMP_COMMAND
++gceSTATUS
++gcfDumpBuffer(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes
++ );
++# define gcmDUMP_BUFFER gcfDumpBuffer
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_BUFFER(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_buffer(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes
++ )
++ {
++ }
++# define gcmDUMP_BUFFER __dummy_dump_buffer
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API
++**
++** Print a dump message for a high level API prefixed by the function name.
++**
++** ARGUMENTS:
++**
++** gctSTRING Message.
++**
++** ... Optional arguments.
++*/
++gceSTATUS gcfDumpApi(IN gctCONST_STRING String, ...);
++#if gcdDUMP_API
++# define gcmDUMP_API gcfDumpApi
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_API(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api(
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmDUMP_API __dummy_dump_api
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_ARRAY
++**
++** Print an array of data.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to array.
++** gctUINT32 Size.
++*/
++gceSTATUS gcfDumpArray(IN gctCONST_POINTER Data, IN gctUINT32 Size);
++#if gcdDUMP_API
++# define gcmDUMP_API_ARRAY gcfDumpArray
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_API_ARRAY(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_array(
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 Size
++ )
++ {
++ }
++# define gcmDUMP_API_ARRAY __dummy_dump_api_array
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_ARRAY_TOKEN
++**
++** Print an array of data terminated by a token.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to array.
++** gctUINT32 Termination.
++*/
++gceSTATUS gcfDumpArrayToken(IN gctCONST_POINTER Data, IN gctUINT32 Termination);
++#if gcdDUMP_API
++# define gcmDUMP_API_ARRAY_TOKEN gcfDumpArrayToken
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_API_ARRAY_TOKEN(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_array_token(
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 Termination
++ )
++ {
++ }
++# define gcmDUMP_API_ARRAY_TOKEN __dummy_dump_api_array_token
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_DATA
++**
++** Print an array of bytes.
++**
++** ARGUMENTS:
++**
++** gctCONST_POINTER Pointer to array.
++** gctSIZE_T Size.
++*/
++gceSTATUS gcfDumpApiData(IN gctCONST_POINTER Data, IN gctSIZE_T Size);
++#if gcdDUMP_API
++# define gcmDUMP_API_DATA gcfDumpApiData
++#elif gcdHAS_ELLIPSES
++# define gcmDUMP_API_DATA(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_data(
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Size
++ )
++ {
++ }
++# define gcmDUMP_API_DATA __dummy_dump_api_data
++#endif
++
++/*******************************************************************************
++**
++** gcmTRACE_RELEASE
++**
++** Print a message to the shader debugger.
++**
++** ARGUMENTS:
++**
++** message Message.
++** ... Optional arguments.
++*/
++
++#define gcmTRACE_RELEASE gcoOS_DebugShaderTrace
++
++void
++gcoOS_DebugShaderTrace(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_SetDebugShaderFiles(
++ IN gctCONST_STRING VSFileName,
++ IN gctCONST_STRING FSFileName
++ );
++
++void
++gcoOS_SetDebugShaderFileType(
++ IN gctUINT32 ShaderType
++ );
++
++void
++gcoOS_EnableDebugBuffer(
++ IN gctBOOL Enable
++ );
++
++/*******************************************************************************
++**
++** gcmBREAK
++**
++** Break into the debugger. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** None.
++*/
++
++void
++gcoOS_DebugBreak(
++ void
++ );
++
++void
++gckOS_DebugBreak(
++ void
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_BREAK)
++# define gcmBREAK gcoOS_DebugBreak
++# define gcmkBREAK gckOS_DebugBreak
++#else
++# define gcmBREAK()
++# define gcmkBREAK()
++#endif
++
++/*******************************************************************************
++**
++** gcmASSERT
++**
++** Evaluate an expression and break into the debugger if the expression
++** evaluates to false. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** exp Expression to evaluate.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define _gcmASSERT(prefix, exp) \
++ do \
++ { \
++ if (!(exp)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ASSERT at %s(%d)", \
++ __FUNCTION__, __LINE__); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ "(%s)", #exp); \
++ prefix##BREAK(); \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmASSERT(exp) _gcmASSERT(gcm, exp)
++# define gcmkASSERT(exp) _gcmASSERT(gcmk, exp)
++#else
++# define gcmASSERT(exp)
++# define gcmkASSERT(exp)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY
++**
++** Verify if an expression returns true. If the expression does not
++** evaluates to true, an assertion will happen in debug mode.
++**
++** ARGUMENTS:
++**
++** exp Expression to evaluate.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define gcmVERIFY(exp) gcmASSERT(exp)
++# define gcmkVERIFY(exp) gcmkASSERT(exp)
++#else
++# define gcmVERIFY(exp) exp
++# define gcmkVERIFY(exp) exp
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY_OK
++**
++** Verify a fucntion returns gcvSTATUS_OK. If the function does not return
++** gcvSTATUS_OK, an assertion will happen in debug mode.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++
++void
++gcoOS_Verify(
++ IN gceSTATUS Status
++ );
++
++void
++gckOS_Verify(
++ IN gceSTATUS Status
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define gcmVERIFY_OK(func) \
++ do \
++ { \
++ gceSTATUS verifyStatus = func; \
++ gcoOS_Verify(verifyStatus); \
++ if (verifyStatus != gcvSTATUS_OK) \
++ { \
++ gcmTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmVERIFY_OK(%d): function returned %d", \
++ __LINE__, verifyStatus \
++ ); \
++ } \
++ gcmASSERT(verifyStatus == gcvSTATUS_OK); \
++ } \
++ while (gcvFALSE)
++# define gcmkVERIFY_OK(func) \
++ do \
++ { \
++ gceSTATUS verifyStatus = func; \
++ if (verifyStatus != gcvSTATUS_OK) \
++ { \
++ gcmkTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmkVERIFY_OK(%d): function returned %d", \
++ __LINE__, verifyStatus \
++ ); \
++ } \
++ gckOS_Verify(verifyStatus); \
++ gcmkASSERT(verifyStatus == gcvSTATUS_OK); \
++ } \
++ while (gcvFALSE)
++#else
++# define gcmVERIFY_OK(func) func
++# define gcmkVERIFY_OK(func) func
++#endif
++
++gctCONST_STRING
++gcoOS_DebugStatus2Name(
++ gceSTATUS status
++ );
++
++gctCONST_STRING
++gckOS_DebugStatus2Name(
++ gceSTATUS status
++ );
++
++/*******************************************************************************
++**
++** gcmERR_BREAK
++**
++** Executes a break statement on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmERR_BREAK(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++#define _gcmkERR_BREAK(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++#define gcmERR_BREAK(func) _gcmERR_BREAK(gcm, func)
++#define gcmkERR_BREAK(func) _gcmkERR_BREAK(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmERR_RETURN
++**
++** Executes a return on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmERR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ prefix##FOOTER(); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++#define _gcmkERR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ prefix##FOOTER(); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++#define gcmERR_RETURN(func) _gcmERR_RETURN(gcm, func)
++#define gcmkERR_RETURN(func) _gcmkERR_RETURN(gcmk, func)
++
++
++/*******************************************************************************
++**
++** gcmONERROR
++**
++** Jump to the error handler in case there is an error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmONERROR(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkONERROR(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmONERROR(func) _gcmONERROR(gcm, func)
++#define gcmkONERROR(func) _gcmkONERROR(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmVERIFY_LOCK
++**
++** Verifies whether the surface is locked.
++**
++** ARGUMENTS:
++**
++** surfaceInfo Pointer to the surface iniformational structure.
++*/
++#define gcmVERIFY_LOCK(surfaceInfo) \
++ if (!surfaceInfo->node.valid) \
++ { \
++ gcmONERROR(gcvSTATUS_MEMORY_UNLOCKED); \
++ } \
++
++/*******************************************************************************
++**
++** gcmVERIFY_NODE_LOCK
++**
++** Verifies whether the surface node is locked.
++**
++** ARGUMENTS:
++**
++** surfaceInfo Pointer to the surface iniformational structure.
++*/
++#define gcmVERIFY_NODE_LOCK(surfaceNode) \
++ if (!(surfaceNode)->valid) \
++ { \
++ status = gcvSTATUS_MEMORY_UNLOCKED; \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmBADOBJECT_BREAK
++**
++** Executes a break statement on bad object.
++**
++** ARGUMENTS:
++**
++** obj Object to test.
++** t Expected type of the object.
++*/
++#define gcmBADOBJECT_BREAK(obj, t) \
++ if ((obj == gcvNULL) \
++ || (((gcsOBJECT *)(obj))->type != t) \
++ ) \
++ { \
++ status = gcvSTATUS_INVALID_OBJECT; \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmCHECK_STATUS
++**
++** Executes a break statement on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmCHECK_STATUS(prefix, func) \
++ do \
++ { \
++ last = func; \
++ if (gcmIS_ERROR(last)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \
++ last, gcoOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \
++ status = last; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkCHECK_STATUS(prefix, func) \
++ do \
++ { \
++ last = func; \
++ if (gcmIS_ERROR(last)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \
++ last, gckOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \
++ status = last; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmCHECK_STATUS(func) _gcmCHECK_STATUS(gcm, func)
++#define gcmkCHECK_STATUS(func) _gcmkCHECK_STATUS(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmVERIFY_ARGUMENT
++**
++** Assert if an argument does not apply to the specified expression. If
++** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be
++** returned from the current function. In retail mode this macro does
++** nothing.
++**
++** ARGUMENTS:
++**
++** arg Argument to evaluate.
++*/
++# define _gcmVERIFY_ARGUMENT(prefix, arg) \
++ do \
++ { \
++ if (!(arg)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, #prefix "VERIFY_ARGUMENT failed:"); \
++ prefix##ASSERT(arg); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); \
++ return gcvSTATUS_INVALID_ARGUMENT; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg)
++# define gcmkVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcmk, arg)
++
++/*******************************************************************************
++**
++** gcmDEBUG_VERIFY_ARGUMENT
++**
++** Works just like gcmVERIFY_ARGUMENT, but is only valid in debug mode.
++** Use this to verify arguments inside non-public API functions.
++*/
++#if gcdDEBUG
++# define gcmDEBUG_VERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg)
++# define gcmkDEBUG_VERIFY_ARGUMENT(arg) _gcmkVERIFY_ARGUMENT(gcm, arg)
++#else
++# define gcmDEBUG_VERIFY_ARGUMENT(arg)
++# define gcmkDEBUG_VERIFY_ARGUMENT(arg)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY_ARGUMENT_RETURN
++**
++** Assert if an argument does not apply to the specified expression. If
++** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be
++** returned from the current function. In retail mode this macro does
++** nothing.
++**
++** ARGUMENTS:
++**
++** arg Argument to evaluate.
++*/
++# define _gcmVERIFY_ARGUMENT_RETURN(prefix, arg, value) \
++ do \
++ { \
++ if (!(arg)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "gcmVERIFY_ARGUMENT_RETURN failed:"); \
++ prefix##ASSERT(arg); \
++ prefix##FOOTER_ARG("value=%d", value); \
++ return value; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_ARGUMENT_RETURN(arg, value) \
++ _gcmVERIFY_ARGUMENT_RETURN(gcm, arg, value)
++# define gcmkVERIFY_ARGUMENT_RETURN(arg, value) \
++ _gcmVERIFY_ARGUMENT_RETURN(gcmk, arg, value)
++
++#define MAX_LOOP_COUNT 0x7FFFFFFF
++
++/******************************************************************************\
++****************************** User Debug Option ******************************
++\******************************************************************************/
++
++/* User option. */
++typedef enum _gceDEBUG_MSG
++{
++ gcvDEBUG_MSG_NONE,
++ gcvDEBUG_MSG_ERROR,
++ gcvDEBUG_MSG_WARNING
++}
++gceDEBUG_MSG;
++
++typedef struct _gcsUSER_DEBUG_OPTION
++{
++ gceDEBUG_MSG debugMsg;
++}
++gcsUSER_DEBUG_OPTION;
++
++gcsUSER_DEBUG_OPTION *
++gcGetUserDebugOption(
++ void
++ );
++
++struct _gcoOS_SymbolsList
++{
++ gcePATCH_ID patchId;
++ const char * symList[10];
++};
++
++#if gcdHAS_ELLIPSES
++#define gcmUSER_DEBUG_MSG(level, ...) \
++ do \
++ { \
++ if (level <= gcGetUserDebugOption()->debugMsg) \
++ { \
++ gcoOS_Print(__VA_ARGS__); \
++ } \
++ } while (gcvFALSE)
++
++#define gcmUSER_DEBUG_ERROR_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_ERROR, "Error: " __VA_ARGS__)
++#define gcmUSER_DEBUG_WARNING_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_WARNING, "Warring: " __VA_ARGS__)
++#else
++#define gcmUSER_DEBUG_MSG
++#define gcmUSER_DEBUG_ERROR_MSG
++#define gcmUSER_DEBUG_WARNING_MSG
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_base_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_compiler.h 2014-05-15 20:33:58.610018275 +0200
+@@ -0,0 +1,4278 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/*
++** Include file the defines the front- and back-end compilers, as well as the
++** objects they use.
++*/
++
++#ifndef __gc_hal_compiler_h_
++#define __gc_hal_compiler_h_
++
++#ifndef VIVANTE_NO_3D
++#include "gc_hal_types.h"
++#include "gc_hal_engine.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#ifndef GC_ENABLE_LOADTIME_OPT
++#define GC_ENABLE_LOADTIME_OPT 1
++#endif
++
++#define TEMP_OPT_CONSTANT_TEXLD_COORD 0
++
++#define TEMP_SHADER_PATCH 1
++
++#define TEMP_INLINE_ALL_EXPANSION 1
++/******************************* IR VERSION ******************/
++#define gcdSL_IR_VERSION gcmCC('\0','\0','\0','\1')
++
++/******************************************************************************\
++|******************************* SHADER LANGUAGE ******************************|
++\******************************************************************************/
++
++ /* allocator/deallocator function pointer */
++typedef gceSTATUS (*gctAllocatorFunc)(
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++typedef gceSTATUS (*gctDeallocatorFunc)(
++ IN gctPOINTER Memory
++ );
++
++typedef gctBOOL (*compareFunc) (
++ IN void * data,
++ IN void * key
++ );
++
++typedef struct _gcsListNode gcsListNode;
++struct _gcsListNode
++{
++ gcsListNode * next;
++ void * data;
++};
++
++typedef struct _gcsAllocator
++{
++ gctAllocatorFunc allocate;
++ gctDeallocatorFunc deallocate;
++} gcsAllocator;
++
++/* simple map structure */
++typedef struct _SimpleMap SimpleMap;
++struct _SimpleMap
++{
++ gctUINT32 key;
++ gctUINT32 val;
++ SimpleMap *next;
++ gcsAllocator *allocator;
++
++};
++
++/* SimpleMap Operations */
++/* return -1 if not found, otherwise return the mapped value */
++gctUINT32
++gcSimpleMap_Find(
++ IN SimpleMap *Map,
++ IN gctUINT32 Key
++ );
++
++gceSTATUS
++gcSimpleMap_Destory(
++ IN SimpleMap * Map,
++ IN gcsAllocator * Allocator
++ );
++
++/* Add a pair <Key, Val> to the Map head, the user should be aware that the
++ * map pointer is always changed when adding a new node :
++ *
++ * gcSimpleMap_AddNode(&theMap, key, val, allocator);
++ *
++ */
++gceSTATUS
++gcSimpleMap_AddNode(
++ IN SimpleMap ** Map,
++ IN gctUINT32 Key,
++ IN gctUINT32 Val,
++ IN gcsAllocator * Allocator
++ );
++
++/* gcsList data structure and related operations */
++typedef struct _gcsList
++{
++ gcsListNode *head;
++ gcsListNode *tail;
++ gctINT count;
++ gcsAllocator *allocator;
++} gcsList;
++
++/* List operations */
++void
++gcList_Init(
++ IN gcsList *list,
++ IN gcsAllocator *allocator
++ );
++
++gceSTATUS
++gcList_CreateNode(
++ IN void * Data,
++ IN gctAllocatorFunc Allocator,
++ OUT gcsListNode ** ListNode
++ );
++
++gceSTATUS
++gcList_Clean(
++ IN gcsList * List,
++ IN gctBOOL FreeData
++ );
++
++gcsListNode *
++gcList_FindNode(
++ IN gcsList * List,
++ IN void * Key,
++ IN compareFunc compare
++ );
++
++gceSTATUS
++gcList_AddNode(
++ IN gcsList * List,
++ IN void * Data
++ );
++
++gceSTATUS
++gcList_RemoveNode(
++ IN gcsList * List,
++ IN gcsListNode * Node
++ );
++
++/* link list structure for code list */
++typedef gcsList gcsCodeList;
++typedef gcsCodeList * gctCodeList;
++typedef gcsListNode gcsCodeListNode;
++
++/* Possible shader language opcodes. */
++typedef enum _gcSL_OPCODE
++{
++ gcSL_NOP, /* 0x00 */
++ gcSL_MOV, /* 0x01 */
++ gcSL_SAT, /* 0x02 */
++ gcSL_DP3, /* 0x03 */
++ gcSL_DP4, /* 0x04 */
++ gcSL_ABS, /* 0x05 */
++ gcSL_JMP, /* 0x06 */
++ gcSL_ADD, /* 0x07 */
++ gcSL_MUL, /* 0x08 */
++ gcSL_RCP, /* 0x09 */
++ gcSL_SUB, /* 0x0A */
++ gcSL_KILL, /* 0x0B */
++ gcSL_TEXLD, /* 0x0C */
++ gcSL_CALL, /* 0x0D */
++ gcSL_RET, /* 0x0E */
++ gcSL_NORM, /* 0x0F */
++ gcSL_MAX, /* 0x10 */
++ gcSL_MIN, /* 0x11 */
++ gcSL_POW, /* 0x12 */
++ gcSL_RSQ, /* 0x13 */
++ gcSL_LOG, /* 0x14 */
++ gcSL_FRAC, /* 0x15 */
++ gcSL_FLOOR, /* 0x16 */
++ gcSL_CEIL, /* 0x17 */
++ gcSL_CROSS, /* 0x18 */
++ gcSL_TEXLDP, /* 0x19 */
++ gcSL_TEXBIAS, /* 0x1A */
++ gcSL_TEXGRAD, /* 0x1B */
++ gcSL_TEXLOD, /* 0x1C */
++ gcSL_SIN, /* 0x1D */
++ gcSL_COS, /* 0x1E */
++ gcSL_TAN, /* 0x1F */
++ gcSL_EXP, /* 0x20 */
++ gcSL_SIGN, /* 0x21 */
++ gcSL_STEP, /* 0x22 */
++ gcSL_SQRT, /* 0x23 */
++ gcSL_ACOS, /* 0x24 */
++ gcSL_ASIN, /* 0x25 */
++ gcSL_ATAN, /* 0x26 */
++ gcSL_SET, /* 0x27 */
++ gcSL_DSX, /* 0x28 */
++ gcSL_DSY, /* 0x29 */
++ gcSL_FWIDTH, /* 0x2A */
++ gcSL_DIV, /* 0x2B */
++ gcSL_MOD, /* 0x2C */
++ gcSL_AND_BITWISE, /* 0x2D */
++ gcSL_OR_BITWISE, /* 0x2E */
++ gcSL_XOR_BITWISE, /* 0x2F */
++ gcSL_NOT_BITWISE, /* 0x30 */
++ gcSL_LSHIFT, /* 0x31 */
++ gcSL_RSHIFT, /* 0x32 */
++ gcSL_ROTATE, /* 0x33 */
++ gcSL_BITSEL, /* 0x34 */
++ gcSL_LEADZERO, /* 0x35 */
++ gcSL_LOAD, /* 0x36 */
++ gcSL_STORE, /* 0x37 */
++ gcSL_BARRIER, /* 0x38 */
++ gcSL_STORE1, /* 0x39 */
++ gcSL_ATOMADD, /* 0x3A */
++ gcSL_ATOMSUB, /* 0x3B */
++ gcSL_ATOMXCHG, /* 0x3C */
++ gcSL_ATOMCMPXCHG, /* 0x3D */
++ gcSL_ATOMMIN, /* 0x3E */
++ gcSL_ATOMMAX, /* 0x3F */
++ gcSL_ATOMOR, /* 0x40 */
++ gcSL_ATOMAND, /* 0x41 */
++ gcSL_ATOMXOR, /* 0x42 */
++ /*gcSL_UNUSED, 0x43 */
++ /*gcSL_UNUSED, 0x44 */
++ /*gcSL_UNUSED, 0x45 */
++ /*gcSL_UNUSED, 0x46 */
++ /*gcSL_UNUSED, 0x47 */
++ /*gcSL_UNUSED, 0x48 */
++ /*gcSL_UNUSED, 0x49 */
++ /*gcSL_UNUSED, 0x4A */
++ /*gcSL_UNUSED, 0x4B */
++ /*gcSL_UNUSED, 0x4C */
++ /*gcSL_UNUSED, 0x4D */
++ /*gcSL_UNUSED, 0x4E */
++ /*gcSL_UNUSED, 0x4F */
++ /*gcSL_UNUSED, 0x50 */
++ /*gcSL_UNUSED, 0x51 */
++ /*gcSL_UNUSED, 0x52 */
++ gcSL_ADDLO = 0x53, /* 0x53 */ /* Float only. */
++ gcSL_MULLO, /* 0x54 */ /* Float only. */
++ gcSL_CONV, /* 0x55 */
++ gcSL_GETEXP, /* 0x56 */
++ gcSL_GETMANT, /* 0x57 */
++ gcSL_MULHI, /* 0x58 */ /* Integer only. */
++ gcSL_CMP, /* 0x59 */
++ gcSL_I2F, /* 0x5A */
++ gcSL_F2I, /* 0x5B */
++ gcSL_ADDSAT, /* 0x5C */ /* Integer only. */
++ gcSL_SUBSAT, /* 0x5D */ /* Integer only. */
++ gcSL_MULSAT, /* 0x5E */ /* Integer only. */
++ gcSL_DP2, /* 0x5F */
++ gcSL_MAXOPCODE
++}
++gcSL_OPCODE;
++
++typedef enum _gcSL_FORMAT
++{
++ gcSL_FLOAT = 0, /* 0 */
++ gcSL_INTEGER = 1, /* 1 */
++ gcSL_INT32 = 1, /* 1 */
++ gcSL_BOOLEAN = 2, /* 2 */
++ gcSL_UINT32 = 3, /* 3 */
++ gcSL_INT8, /* 4 */
++ gcSL_UINT8, /* 5 */
++ gcSL_INT16, /* 6 */
++ gcSL_UINT16, /* 7 */
++ gcSL_INT64, /* 8 */ /* Reserved for future enhancement. */
++ gcSL_UINT64, /* 9 */ /* Reserved for future enhancement. */
++ gcSL_INT128, /* 10 */ /* Reserved for future enhancement. */
++ gcSL_UINT128, /* 11 */ /* Reserved for future enhancement. */
++ gcSL_FLOAT16, /* 12 */
++ gcSL_FLOAT64, /* 13 */ /* Reserved for future enhancement. */
++ gcSL_FLOAT128, /* 14 */ /* Reserved for future enhancement. */
++}
++gcSL_FORMAT;
++
++/* Destination write enable bits. */
++typedef enum _gcSL_ENABLE
++{
++ gcSL_ENABLE_NONE = 0x0, /* none is enabled, error/uninitialized state */
++ gcSL_ENABLE_X = 0x1,
++ gcSL_ENABLE_Y = 0x2,
++ gcSL_ENABLE_Z = 0x4,
++ gcSL_ENABLE_W = 0x8,
++ /* Combinations. */
++ gcSL_ENABLE_XY = gcSL_ENABLE_X | gcSL_ENABLE_Y,
++ gcSL_ENABLE_XYZ = gcSL_ENABLE_X | gcSL_ENABLE_Y | gcSL_ENABLE_Z,
++ gcSL_ENABLE_XYZW = gcSL_ENABLE_X | gcSL_ENABLE_Y | gcSL_ENABLE_Z | gcSL_ENABLE_W,
++ gcSL_ENABLE_XYW = gcSL_ENABLE_X | gcSL_ENABLE_Y | gcSL_ENABLE_W,
++ gcSL_ENABLE_XZ = gcSL_ENABLE_X | gcSL_ENABLE_Z,
++ gcSL_ENABLE_XZW = gcSL_ENABLE_X | gcSL_ENABLE_Z | gcSL_ENABLE_W,
++ gcSL_ENABLE_XW = gcSL_ENABLE_X | gcSL_ENABLE_W,
++ gcSL_ENABLE_YZ = gcSL_ENABLE_Y | gcSL_ENABLE_Z,
++ gcSL_ENABLE_YZW = gcSL_ENABLE_Y | gcSL_ENABLE_Z | gcSL_ENABLE_W,
++ gcSL_ENABLE_YW = gcSL_ENABLE_Y | gcSL_ENABLE_W,
++ gcSL_ENABLE_ZW = gcSL_ENABLE_Z | gcSL_ENABLE_W,
++}
++gcSL_ENABLE;
++
++/* Possible indices. */
++typedef enum _gcSL_INDEXED
++{
++ gcSL_NOT_INDEXED, /* 0 */
++ gcSL_INDEXED_X, /* 1 */
++ gcSL_INDEXED_Y, /* 2 */
++ gcSL_INDEXED_Z, /* 3 */
++ gcSL_INDEXED_W, /* 4 */
++}
++gcSL_INDEXED;
++
++/* Opcode conditions. */
++typedef enum _gcSL_CONDITION
++{
++ gcSL_ALWAYS, /* 0x0 */
++ gcSL_NOT_EQUAL, /* 0x1 */
++ gcSL_LESS_OR_EQUAL, /* 0x2 */
++ gcSL_LESS, /* 0x3 */
++ gcSL_EQUAL, /* 0x4 */
++ gcSL_GREATER, /* 0x5 */
++ gcSL_GREATER_OR_EQUAL, /* 0x6 */
++ gcSL_AND, /* 0x7 */
++ gcSL_OR, /* 0x8 */
++ gcSL_XOR, /* 0x9 */
++ gcSL_NOT_ZERO, /* 0xA */
++}
++gcSL_CONDITION;
++
++/* Possible source operand types. */
++typedef enum _gcSL_TYPE
++{
++ gcSL_NONE, /* 0x0 */
++ gcSL_TEMP, /* 0x1 */
++ gcSL_ATTRIBUTE, /* 0x2 */
++ gcSL_UNIFORM, /* 0x3 */
++ gcSL_SAMPLER, /* 0x4 */
++ gcSL_CONSTANT, /* 0x5 */
++ gcSL_OUTPUT, /* 0x6 */
++ gcSL_PHYSICAL, /* 0x7 */
++}
++gcSL_TYPE;
++
++/* Swizzle generator macro. */
++#define gcmSWIZZLE(Component1, Component2, Component3, Component4) \
++( \
++ (gcSL_SWIZZLE_ ## Component1 << 0) | \
++ (gcSL_SWIZZLE_ ## Component2 << 2) | \
++ (gcSL_SWIZZLE_ ## Component3 << 4) | \
++ (gcSL_SWIZZLE_ ## Component4 << 6) \
++)
++
++#define gcmExtractSwizzle(Swizzle, Index) \
++ ((gcSL_SWIZZLE) ((((Swizzle) >> (Index * 2)) & 0x3)))
++
++#define gcmComposeSwizzle(SwizzleX, SwizzleY, SwizzleZ, SwizzleW) \
++( \
++ ((SwizzleX) << 0) | \
++ ((SwizzleY) << 2) | \
++ ((SwizzleZ) << 4) | \
++ ((SwizzleW) << 6) \
++)
++
++/* Possible swizzle values. */
++typedef enum _gcSL_SWIZZLE
++{
++ gcSL_SWIZZLE_X, /* 0x0 */
++ gcSL_SWIZZLE_Y, /* 0x1 */
++ gcSL_SWIZZLE_Z, /* 0x2 */
++ gcSL_SWIZZLE_W, /* 0x3 */
++ /* Combinations. */
++ gcSL_SWIZZLE_XXXX = gcmSWIZZLE(X, X, X, X),
++ gcSL_SWIZZLE_YYYY = gcmSWIZZLE(Y, Y, Y, Y),
++ gcSL_SWIZZLE_ZZZZ = gcmSWIZZLE(Z, Z, Z, Z),
++ gcSL_SWIZZLE_WWWW = gcmSWIZZLE(W, W, W, W),
++ gcSL_SWIZZLE_XYYY = gcmSWIZZLE(X, Y, Y, Y),
++ gcSL_SWIZZLE_XZZZ = gcmSWIZZLE(X, Z, Z, Z),
++ gcSL_SWIZZLE_XWWW = gcmSWIZZLE(X, W, W, W),
++ gcSL_SWIZZLE_YZZZ = gcmSWIZZLE(Y, Z, Z, Z),
++ gcSL_SWIZZLE_YWWW = gcmSWIZZLE(Y, W, W, W),
++ gcSL_SWIZZLE_ZWWW = gcmSWIZZLE(Z, W, W, W),
++ gcSL_SWIZZLE_XYZZ = gcmSWIZZLE(X, Y, Z, Z),
++ gcSL_SWIZZLE_XYWW = gcmSWIZZLE(X, Y, W, W),
++ gcSL_SWIZZLE_XZWW = gcmSWIZZLE(X, Z, W, W),
++ gcSL_SWIZZLE_YZWW = gcmSWIZZLE(Y, Z, W, W),
++ gcSL_SWIZZLE_XXYZ = gcmSWIZZLE(X, X, Y, Z),
++ gcSL_SWIZZLE_XYZW = gcmSWIZZLE(X, Y, Z, W),
++ gcSL_SWIZZLE_XYXY = gcmSWIZZLE(X, Y, X, Y),
++ gcSL_SWIZZLE_YYZZ = gcmSWIZZLE(Y, Y, Z, Z),
++ gcSL_SWIZZLE_YYWW = gcmSWIZZLE(Y, Y, W, W),
++ gcSL_SWIZZLE_ZZZW = gcmSWIZZLE(Z, Z, Z, W),
++ gcSL_SWIZZLE_XZZW = gcmSWIZZLE(X, Z, Z, W),
++ gcSL_SWIZZLE_YYZW = gcmSWIZZLE(Y, Y, Z, W),
++
++ gcSL_SWIZZLE_INVALID = 0x7FFFFFFF
++}
++gcSL_SWIZZLE;
++
++typedef enum _gcSL_COMPONENT
++{
++ gcSL_COMPONENT_X, /* 0x0 */
++ gcSL_COMPONENT_Y, /* 0x1 */
++ gcSL_COMPONENT_Z, /* 0x2 */
++ gcSL_COMPONENT_W, /* 0x3 */
++ gcSL_COMPONENT_COUNT /* 0x4 */
++} gcSL_COMPONENT;
++
++#define gcmIsComponentEnabled(Enable, Component) (((Enable) & (1 << (Component))) != 0)
++
++/******************************************************************************\
++|*********************************** SHADERS **********************************|
++\******************************************************************************/
++
++/* Shader types. */
++typedef enum _gcSHADER_KIND {
++ gcSHADER_TYPE_UNKNOWN = 0,
++ gcSHADER_TYPE_VERTEX,
++ gcSHADER_TYPE_FRAGMENT,
++ gcSHADER_TYPE_CL,
++ gcSHADER_TYPE_PRECOMPILED,
++ gcSHADER_KIND_COUNT
++} gcSHADER_KIND;
++
++typedef enum _gcGL_DRIVER_VERSION {
++ gcGL_DRIVER_ES11, /* OpenGL ES 1.1 */
++ gcGL_DRIVER_ES20, /* OpenGL ES 2.0 */
++ gcGL_DRIVER_ES30 /* OpenGL ES 3.0 */
++} gcGL_DRIVER_VERSION;
++
++/* gcSHADER objects. */
++typedef struct _gcSHADER * gcSHADER;
++typedef struct _gcATTRIBUTE * gcATTRIBUTE;
++typedef struct _gcUNIFORM * gcUNIFORM;
++typedef struct _gcOUTPUT * gcOUTPUT;
++typedef struct _gcsFUNCTION * gcFUNCTION;
++typedef struct _gcsKERNEL_FUNCTION * gcKERNEL_FUNCTION;
++typedef struct _gcsHINT * gcsHINT_PTR;
++typedef struct _gcSHADER_PROFILER * gcSHADER_PROFILER;
++typedef struct _gcVARIABLE * gcVARIABLE;
++
++struct _gcsHINT
++{
++ /* Numbr of data transfers for Vertex Shader output. */
++ gctUINT32 vsOutputCount;
++
++ /* Flag whether the VS has point size or not. */
++ gctBOOL vsHasPointSize;
++
++#if gcdUSE_WCLIP_PATCH
++ /* Flag whether the VS gl_position.z depends on gl_position.w
++ it's a hint for wclipping */
++ gctBOOL vsPositionZDependsOnW;
++#endif
++
++ gctBOOL clipW;
++
++ /* Flag whether or not the shader has a KILL instruction. */
++ gctBOOL hasKill;
++
++ /* Element count. */
++ gctUINT32 elementCount;
++
++ /* Component count. */
++ gctUINT32 componentCount;
++
++ /* Number of data transfers for Fragment Shader input. */
++ gctUINT32 fsInputCount;
++
++ /* Maximum number of temporary registers used in FS. */
++ gctUINT32 fsMaxTemp;
++
++ /* Maximum number of temporary registers used in VS. */
++ gctUINT32 vsMaxTemp;
++
++ /* Balance minimum. */
++ gctUINT32 balanceMin;
++
++ /* Balance maximum. */
++ gctUINT32 balanceMax;
++
++ /* Auto-shift balancing. */
++ gctBOOL autoShift;
++
++ /* Flag whether the PS outputs the depth value or not. */
++ gctBOOL psHasFragDepthOut;
++
++ /* Flag whether the ThreadWalker is in PS. */
++ gctBOOL threadWalkerInPS;
++
++ /* HW reg number for position of VS */
++ gctUINT32 hwRegNoOfSIVPos;
++
++#if gcdALPHA_KILL_IN_SHADER
++ /* States to set when alpha kill is enabled. */
++ gctUINT32 killStateAddress;
++ gctUINT32 alphaKillStateValue;
++ gctUINT32 colorKillStateValue;
++
++ /* Shader instructiuon. */
++ gctUINT32 killInstructionAddress;
++ gctUINT32 alphaKillInstruction[3];
++ gctUINT32 colorKillInstruction[3];
++#endif
++
++#if TEMP_SHADER_PATCH
++ gctUINT32 pachedShaderIdentifier;
++#endif
++};
++
++#if TEMP_SHADER_PATCH
++#define INVALID_SHADER_IDENTIFIER 0xFFFFFFFF
++#endif
++
++/* gcSHADER_TYPE enumeration. */
++typedef enum _gcSHADER_TYPE
++{
++ gcSHADER_FLOAT_X1 = 0, /* 0x00 */
++ gcSHADER_FLOAT_X2, /* 0x01 */
++ gcSHADER_FLOAT_X3, /* 0x02 */
++ gcSHADER_FLOAT_X4, /* 0x03 */
++ gcSHADER_FLOAT_2X2, /* 0x04 */
++ gcSHADER_FLOAT_3X3, /* 0x05 */
++ gcSHADER_FLOAT_4X4, /* 0x06 */
++ gcSHADER_BOOLEAN_X1, /* 0x07 */
++ gcSHADER_BOOLEAN_X2, /* 0x08 */
++ gcSHADER_BOOLEAN_X3, /* 0x09 */
++ gcSHADER_BOOLEAN_X4, /* 0x0A */
++ gcSHADER_INTEGER_X1, /* 0x0B */
++ gcSHADER_INTEGER_X2, /* 0x0C */
++ gcSHADER_INTEGER_X3, /* 0x0D */
++ gcSHADER_INTEGER_X4, /* 0x0E */
++ gcSHADER_SAMPLER_1D, /* 0x0F */
++ gcSHADER_SAMPLER_2D, /* 0x10 */
++ gcSHADER_SAMPLER_3D, /* 0x11 */
++ gcSHADER_SAMPLER_CUBIC, /* 0x12 */
++ gcSHADER_FIXED_X1, /* 0x13 */
++ gcSHADER_FIXED_X2, /* 0x14 */
++ gcSHADER_FIXED_X3, /* 0x15 */
++ gcSHADER_FIXED_X4, /* 0x16 */
++ gcSHADER_IMAGE_2D, /* 0x17 */ /* For OCL. */
++ gcSHADER_IMAGE_3D, /* 0x18 */ /* For OCL. */
++ gcSHADER_SAMPLER, /* 0x19 */ /* For OCL. */
++ gcSHADER_FLOAT_2X3, /* 0x1A */
++ gcSHADER_FLOAT_2X4, /* 0x1B */
++ gcSHADER_FLOAT_3X2, /* 0x1C */
++ gcSHADER_FLOAT_3X4, /* 0x1D */
++ gcSHADER_FLOAT_4X2, /* 0x1E */
++ gcSHADER_FLOAT_4X3, /* 0x1F */
++ gcSHADER_ISAMPLER_2D, /* 0x20 */
++ gcSHADER_ISAMPLER_3D, /* 0x21 */
++ gcSHADER_ISAMPLER_CUBIC, /* 0x22 */
++ gcSHADER_USAMPLER_2D, /* 0x23 */
++ gcSHADER_USAMPLER_3D, /* 0x24 */
++ gcSHADER_USAMPLER_CUBIC, /* 0x25 */
++ gcSHADER_SAMPLER_EXTERNAL_OES, /* 0x26 */
++
++ gcSHADER_UINT_X1, /* 0x27 */
++ gcSHADER_UINT_X2, /* 0x28 */
++ gcSHADER_UINT_X3, /* 0x29 */
++ gcSHADER_UINT_X4, /* 0x2A */
++
++ gcSHADER_UNKONWN_TYPE, /* do not add type after this */
++ gcSHADER_TYPE_COUNT /* must to change gcvShaderTypeInfo at the
++ * same time if you add any new type! */}
++gcSHADER_TYPE;
++
++typedef enum _gcSHADER_TYPE_KIND
++{
++ gceTK_UNKOWN,
++ gceTK_FLOAT,
++ gceTK_INT,
++ gceTK_UINT,
++ gceTK_BOOL,
++ gceTK_FIXED,
++ gceTK_SAMPLER,
++ gceTK_IMAGE,
++ gceTK_OTHER
++} gcSHADER_TYPE_KIND;
++
++typedef struct _gcSHADER_TYPEINFO
++{
++ gcSHADER_TYPE type; /* e.g. gcSHADER_FLOAT_2X4 */
++ gctINT components; /* e.g. 4 components */
++ gctINT rows; /* e.g. 2 rows */
++ gcSHADER_TYPE componentType; /* e.g. gcSHADER_FLOAT_X4 */
++ gcSHADER_TYPE_KIND kind; /* e.g. gceTK_FLOAT */
++ gctCONST_STRING name; /* e.g. "FLOAT_2X4" */
++} gcSHADER_TYPEINFO;
++
++extern gcSHADER_TYPEINFO gcvShaderTypeInfo[];
++
++#define gcmType_Comonents(Type) (gcvShaderTypeInfo[Type].components)
++#define gcmType_Rows(Type) (gcvShaderTypeInfo[Type].rows)
++#define gcmType_ComonentType(Type) (gcvShaderTypeInfo[Type].componentType)
++#define gcmType_Kind(Type) (gcvShaderTypeInfo[Type].kind)
++#define gcmType_Name(Type) (gcvShaderTypeInfo[Type].name)
++
++#define gcmType_isMatrix(type) (gcmType_Rows(type) > 1)
++
++typedef enum _gcSHADER_VAR_CATEGORY
++{
++ gcSHADER_VAR_CATEGORY_NORMAL = 0, /* primitive type and its array */
++ gcSHADER_VAR_CATEGORY_STRUCT = 1 /* structure */
++}
++gcSHADER_VAR_CATEGORY;
++
++typedef enum _gceTYPE_QUALIFIER
++{
++ gcvTYPE_QUALIFIER_NONE = 0x0, /* unqualified */
++ gcvTYPE_QUALIFIER_VOLATILE = 0x1, /* volatile */
++}gceTYPE_QUALIFIER;
++
++typedef gctUINT16 gctTYPE_QUALIFIER;
++
++#if GC_ENABLE_LOADTIME_OPT
++typedef struct _gcSHADER_TYPE_INFO
++{
++ gcSHADER_TYPE type; /* eg. gcSHADER_FLOAT_2X3 is the type */
++ gctCONST_STRING name; /* the name of the type: "gcSHADER_FLOAT_2X3" */
++ gcSHADER_TYPE baseType; /* its base type is gcSHADER_FLOAT_2 */
++ gctINT components; /* it has 2 components */
++ gctINT rows; /* and 3 rows */
++ gctINT size; /* the size in byte */
++} gcSHADER_TYPE_INFO;
++
++extern gcSHADER_TYPE_INFO shader_type_info[];
++
++enum gceLTCDumpOption {
++ gceLTC_DUMP_UNIFORM = 0x0001,
++ gceLTC_DUMP_EVALUATION = 0x0002,
++ gceLTC_DUMP_EXPESSION = 0x0004,
++ gceLTC_DUMP_COLLECTING = 0x0008,
++};
++
++gctBOOL gcDumpOption(gctINT Opt);
++
++#endif /* GC_ENABLE_LOADTIME_OPT */
++
++#define IS_MATRIX_TYPE(type) \
++ (((type >= gcSHADER_FLOAT_2X2) && (type <= gcSHADER_FLOAT_4X4)) || \
++ ((type >= gcSHADER_FLOAT_2X3) && (type <= gcSHADER_FLOAT_4X3)))
++
++/* gcSHADER_PRECISION enumeration. */
++typedef enum _gcSHADER_PRECISION
++{
++ gcSHADER_PRECISION_DEFAULT, /* 0x00 */
++ gcSHADER_PRECISION_HIGH, /* 0x01 */
++ gcSHADER_PRECISION_MEDIUM, /* 0x02 */
++ gcSHADER_PRECISION_LOW, /* 0x03 */
++}
++gcSHADER_PRECISION;
++
++/* Shader flags. */
++typedef enum _gceSHADER_FLAGS
++{
++ gcvSHADER_NO_OPTIMIZATION = 0x00,
++ gcvSHADER_DEAD_CODE = 0x01,
++ gcvSHADER_RESOURCE_USAGE = 0x02,
++ gcvSHADER_OPTIMIZER = 0x04,
++ gcvSHADER_USE_GL_Z = 0x08,
++ /*
++ The GC family of GPU cores model GC860 and under require the Z
++ to be from 0 <= z <= w.
++ However, OpenGL specifies the Z to be from -w <= z <= w. So we
++ have to a conversion here:
++
++ z = (z + w) / 2.
++
++ So here we append two instructions to the vertex shader.
++ */
++ gcvSHADER_USE_GL_POSITION = 0x10,
++ gcvSHADER_USE_GL_FACE = 0x20,
++ gcvSHADER_USE_GL_POINT_COORD = 0x40,
++ gcvSHADER_LOADTIME_OPTIMIZER = 0x80,
++#if gcdALPHA_KILL_IN_SHADER
++ gcvSHADER_USE_ALPHA_KILL = 0x100,
++#endif
++
++#if gcdPRE_ROTATION && (ANDROID_SDK_VERSION >= 14)
++ gcvSHADER_VS_PRE_ROTATION = 0x200,
++#endif
++
++#if TEMP_INLINE_ALL_EXPANSION
++ gcvSHADER_INLINE_ALL_EXPANSION = 0x400,
++#endif
++}
++gceSHADER_FLAGS;
++
++gceSTATUS
++gcSHADER_CheckClipW(
++ IN gctCONST_STRING VertexSource,
++ IN gctCONST_STRING FragmentSource,
++ OUT gctBOOL * clipW);
++
++/*******************************************************************************
++** gcOptimizer Data Structures
++*******************************************************************************/
++typedef enum _gceSHADER_OPTIMIZATION
++{
++ /* No optimization. */
++ gcvOPTIMIZATION_NONE,
++
++ /* Flow graph construction. */
++ gcvOPTIMIZATION_CONSTRUCTION = 1 << 0,
++
++ /* Dead code elimination. */
++ gcvOPTIMIZATION_DEAD_CODE = 1 << 1,
++
++ /* Redundant move instruction elimination. */
++ gcvOPTIMIZATION_REDUNDANT_MOVE = 1 << 2,
++
++ /* Inline expansion. */
++ gcvOPTIMIZATION_INLINE_EXPANSION = 1 << 3,
++
++ /* Constant propagation. */
++ gcvOPTIMIZATION_CONSTANT_PROPAGATION = 1 << 4,
++
++ /* Redundant bounds/checking elimination. */
++ gcvOPTIMIZATION_REDUNDANT_CHECKING = 1 << 5,
++
++ /* Loop invariant movement. */
++ gcvOPTIMIZATION_LOOP_INVARIANT = 1 << 6,
++
++ /* Induction variable removal. */
++ gcvOPTIMIZATION_INDUCTION_VARIABLE = 1 << 7,
++
++ /* Common subexpression elimination. */
++ gcvOPTIMIZATION_COMMON_SUBEXPRESSION = 1 << 8,
++
++ /* Control flow/banch optimization. */
++ gcvOPTIMIZATION_CONTROL_FLOW = 1 << 9,
++
++ /* Vector component operation merge. */
++ gcvOPTIMIZATION_VECTOR_INSTRUCTION_MERGE = 1 << 10,
++
++ /* Algebra simplificaton. */
++ gcvOPTIMIZATION_ALGEBRAIC_SIMPLIFICATION = 1 << 11,
++
++ /* Pattern matching and replacing. */
++ gcvOPTIMIZATION_PATTERN_MATCHING = 1 << 12,
++
++ /* Interprocedural constant propagation. */
++ gcvOPTIMIZATION_IP_CONSTANT_PROPAGATION = 1 << 13,
++
++ /* Interprecedural register optimization. */
++ gcvOPTIMIZATION_IP_REGISTRATION = 1 << 14,
++
++ /* Optimization option number. */
++ gcvOPTIMIZATION_OPTION_NUMBER = 1 << 15,
++
++ /* Loadtime constant. */
++ gcvOPTIMIZATION_LOADTIME_CONSTANT = 1 << 16,
++
++ /* MAD instruction optimization. */
++ gcvOPTIMIZATION_MAD_INSTRUCTION = 1 << 17,
++
++ /* Special optimization for LOAD SW workaround. */
++ gcvOPTIMIZATION_LOAD_SW_WORKAROUND = 1 << 18,
++
++ /* move code into conditional block if possile */
++ gcvOPTIMIZATION_CONDITIONALIZE = 1 << 19,
++
++ /* expriemental: power optimization mode
++ 1. add extra dummy texld to tune performance
++ 2. insert NOP after high power instrucitons
++ 3. split high power vec3/vec4 instruciton to vec2/vec1 operation
++ 4. ...
++ */
++ gcvOPTIMIZATION_POWER_OPTIMIZATION = 1 << 20,
++
++ /* optimize varying packing */
++ gcvOPTIMIZATION_VARYINGPACKING = 1 << 22,
++
++#if TEMP_INLINE_ALL_EXPANSION
++ gcvOPTIMIZATION_INLINE_ALL_EXPANSION = 1 << 23,
++#endif
++
++ /* Full optimization. */
++ /* Note that gcvOPTIMIZATION_LOAD_SW_WORKAROUND is off. */
++ gcvOPTIMIZATION_FULL = 0x7FFFFFFF &
++ ~gcvOPTIMIZATION_LOAD_SW_WORKAROUND &
++ ~gcvOPTIMIZATION_INLINE_ALL_EXPANSION &
++ ~gcvOPTIMIZATION_POWER_OPTIMIZATION,
++
++ /* Optimization Unit Test flag. */
++ gcvOPTIMIZATION_UNIT_TEST = 1 << 31
++}
++gceSHADER_OPTIMIZATION;
++
++typedef enum _gceOPTIMIZATION_VaryingPaking
++{
++ gcvOPTIMIZATION_VARYINGPACKING_NONE = 0,
++ gcvOPTIMIZATION_VARYINGPACKING_NOSPLIT,
++ gcvOPTIMIZATION_VARYINGPACKING_SPLIT
++} gceOPTIMIZATION_VaryingPaking;
++
++typedef struct _gcOPTIMIZER_OPTION
++{
++ gceSHADER_OPTIMIZATION optFlags;
++
++ /* debug & dump options:
++
++ VC_OPTION=-DUMP:SRC:OPT|:OPTV|:CG|:CGV:|ALL|ALLV
++
++ SRC: dump shader source code
++ OPT: dump incoming and final IR
++ OPTV: dump result IR in each optimization phase
++ CG: dump generated machine code
++ CGV: dump BE tree and optimization detail
++
++ ALL = SRC|OPT|CG
++ ALLV = SRC|OPT|OPTV|CG|CGV
++ */
++ gctBOOL dumpShaderSource; /* dump shader source code */
++ gctBOOL dumpOptimizer; /* dump incoming and final IR */
++ gctBOOL dumpOptimizerVerbose; /* dump result IR in each optimization phase */
++ gctBOOL dumpBEGenertedCode; /* dump generated machine code */
++ gctBOOL dumpBEVerbose; /* dump BE tree and optimization detail */
++ gctBOOL dumpBEFinalIR; /* dump BE final IR */
++
++ /* Code generation */
++
++ /* Varying Packing:
++
++ VC_OPTION=-PACKVARYING:[0-2]|:T[-]m[,n]|:LshaderIdx,min,max
++
++ 0: turn off varying packing
++ 1: pack varyings, donot split any varying
++ 2: pack varyings, may split to make fully packed output
++
++ Tm: only packing shader pair which vertex shader id is m
++ Tm,n: only packing shader pair which vertex shader id
++ is in range of [m, n]
++ T-m: do not packing shader pair which vertex shader id is m
++ T-m,n: do not packing shader pair which vertex shader id
++ is in range of [m, n]
++
++ LshaderIdx,min,max : set load balance (min, max) for shaderIdx
++ if shaderIdx is -1, all shaders are impacted
++ newMin = origMin * (min/100.);
++ newMax = origMax * (max/100.);
++ */
++ gceOPTIMIZATION_VaryingPaking packVarying;
++ gctINT _triageStart;
++ gctINT _triageEnd;
++ gctINT _loadBalanceShaderIdx;
++ gctINT _loadBalanceMin;
++ gctINT _loadBalanceMax;
++
++ /* Do not generate immdeiate
++
++ VC_OPTION=-NOIMM
++
++ Force generate immediate even the machine model don't support it,
++ for testing purpose only
++
++ VC_OPTION=-FORCEIMM
++ */
++ gctBOOL noImmediate;
++ gctBOOL forceImmediate;
++
++ /* Power reduction mode options */
++ gctBOOL needPowerOptimization;
++
++ /* Patch TEXLD instruction by adding dummy texld
++ (can be used to tune GPU power usage):
++ for every TEXLD we seen, add n dummy TEXLD
++
++ it can be enabled by environment variable:
++
++ VC_OPTION=-PATCH_TEXLD:M:N
++
++ (for each M texld, add N dummy texld)
++ */
++ gctINT patchEveryTEXLDs;
++ gctINT patchDummyTEXLDs;
++
++ /* Insert NOP after high power consumption instructions
++
++ VC_OPTION="-INSERTNOP:MUL:MULLO:DP3:DP4:SEENTEXLD"
++ */
++ gctBOOL insertNOP;
++ gctBOOL insertNOPAfterMUL;
++ gctBOOL insertNOPAfterMULLO;
++ gctBOOL insertNOPAfterDP3;
++ gctBOOL insertNOPAfterDP4;
++ gctBOOL insertNOPOnlyWhenTexldSeen;
++
++ /* split MAD to MUL and ADD:
++
++ VC_OPTION=-SPLITMAD
++ */
++ gctBOOL splitMAD;
++
++ /* Convert vect3/vec4 operations to multiple vec2/vec1 operations
++
++ VC_OPTION=-SPLITVEC:MUL:MULLO:DP3:DP4
++ */
++ gctBOOL splitVec;
++ gctBOOL splitVec4MUL;
++ gctBOOL splitVec4MULLO;
++ gctBOOL splitVec4DP3;
++ gctBOOL splitVec4DP4;
++
++ /* turn/off features:
++
++ VC_OPTION=-F:n,[0|1]
++ Note: n must be decimal number
++ */
++ gctUINT featureBits;
++
++ /* inline level (default 2 at O1):
++
++ VC_OPTION=-INLINELEVEL:[0-3]
++ 0: no inline
++ 1: only inline the function only called once or small function
++ 2: inline functions be called less than 5 times or medium size function
++ 3: inline everything possible
++ */
++ gctUINT inlineLevel;
++} gcOPTIMIZER_OPTION;
++
++extern gcOPTIMIZER_OPTION theOptimizerOption;
++#define gcmGetOptimizerOption() gcGetOptimizerOption()
++
++#define gcmOPT_DUMP_SHADER_SRC() \
++ (gcmGetOptimizerOption()->dumpShaderSource != 0)
++#define gcmOPT_DUMP_OPTIMIZER() \
++ (gcmGetOptimizerOption()->dumpOptimizer != 0 || \
++ gcmOPT_DUMP_OPTIMIZER_VERBOSE() )
++#define gcmOPT_DUMP_OPTIMIZER_VERBOSE() \
++ (gcmGetOptimizerOption()->dumpOptimizerVerbose != 0)
++#define gcmOPT_DUMP_CODEGEN() \
++ (gcmGetOptimizerOption()->dumpBEGenertedCode != 0 || \
++ gcmOPT_DUMP_CODEGEN_VERBOSE() )
++#define gcmOPT_DUMP_CODEGEN_VERBOSE() \
++ (gcmGetOptimizerOption()->dumpBEVerbose != 0)
++#define gcmOPT_DUMP_FINAL_IR() \
++ (gcmGetOptimizerOption()->dumpBEFinalIR != 0)
++
++#define gcmOPT_SET_DUMP_SHADER_SRC(v) \
++ gcmGetOptimizerOption()->dumpShaderSource = (v)
++
++#define gcmOPT_PATCH_TEXLD() (gcmGetOptimizerOption()->patchDummyTEXLDs != 0)
++#define gcmOPT_INSERT_NOP() (gcmGetOptimizerOption()->insertNOP == gcvTRUE)
++#define gcmOPT_SPLITMAD() (gcmGetOptimizerOption()->splitMAD == gcvTRUE)
++#define gcmOPT_SPLITVEC() (gcmGetOptimizerOption()->splitVec == gcvTRUE)
++
++#define gcmOPT_NOIMMEDIATE() (gcmGetOptimizerOption()->noImmediate == gcvTRUE)
++#define gcmOPT_FORCEIMMEDIATE() (gcmGetOptimizerOption()->forceImmediate == gcvTRUE)
++
++#define gcmOPT_PACKVARYING() (gcmGetOptimizerOption()->packVarying)
++#define gcmOPT_PACKVARYING_triageStart() (gcmGetOptimizerOption()->_triageStart)
++#define gcmOPT_PACKVARYING_triageEnd() (gcmGetOptimizerOption()->_triageEnd)
++
++#define gcmOPT_INLINELEVEL() (gcmGetOptimizerOption()->inlineLevel)
++
++/* Setters */
++#define gcmOPT_SetPatchTexld(m,n) (gcmGetOptimizerOption()->patchEveryTEXLDs = (m),\
++ gcmGetOptimizerOption()->patchDummyTEXLDs = (n))
++#define gcmOPT_SetSplitVecMUL() (gcmGetOptimizerOption()->splitVec = gcvTRUE, \
++ gcmGetOptimizerOption()->splitVec4MUL = gcvTRUE)
++#define gcmOPT_SetSplitVecMULLO() (gcmGetOptimizerOption()->splitVec = gcvTRUE, \
++ gcmGetOptimizerOption()->splitVec4MULLO = gcvTRUE)
++#define gcmOPT_SetSplitVecDP3() (gcmGetOptimizerOption()->splitVec = gcvTRUE, \
++ gcmGetOptimizerOption()->splitVec4DP3 = gcvTRUE)
++#define gcmOPT_SetSplitVecDP4() (gcmGetOptimizerOption()->splitVec = gcvTRUE, \
++ gcmGetOptimizerOption()->splitVec4DP4 = gcvTRUE)
++
++#define gcmOPT_SetPackVarying(v) (gcmGetOptimizerOption()->packVarying = v)
++
++#define FB_LIVERANGE_FIX1 0x0001
++
++
++#define PredefinedDummySamplerId 8
++
++/* Function argument qualifier */
++typedef enum _gceINPUT_OUTPUT
++{
++ gcvFUNCTION_INPUT,
++ gcvFUNCTION_OUTPUT,
++ gcvFUNCTION_INOUT
++}
++gceINPUT_OUTPUT;
++
++/* Kernel function property flags. */
++typedef enum _gcePROPERTY_FLAGS
++{
++ gcvPROPERTY_REQD_WORK_GRP_SIZE = 0x01
++}
++gceKERNEL_FUNCTION_PROPERTY_FLAGS;
++
++/* Uniform flags. */
++typedef enum _gceUNIFORM_FLAGS
++{
++ gcvUNIFORM_KERNEL_ARG = 0x01,
++ gcvUNIFORM_KERNEL_ARG_LOCAL = 0x02,
++ gcvUNIFORM_KERNEL_ARG_SAMPLER = 0x04,
++ gcvUNIFORM_LOCAL_ADDRESS_SPACE = 0x08,
++ gcvUNIFORM_PRIVATE_ADDRESS_SPACE = 0x10,
++ gcvUNIFORM_CONSTANT_ADDRESS_SPACE = 0x20,
++ gcvUNIFORM_GLOBAL_SIZE = 0x40,
++ gcvUNIFORM_LOCAL_SIZE = 0x80,
++ gcvUNIFORM_NUM_GROUPS = 0x100,
++ gcvUNIFORM_GLOBAL_OFFSET = 0x200,
++ gcvUNIFORM_WORK_DIM = 0x400,
++ gcvUNIFORM_KERNEL_ARG_CONSTANT = 0x800,
++ gcvUNIFORM_KERNEL_ARG_LOCAL_MEM_SIZE = 0x1000,
++ gcvUNIFORM_KERNEL_ARG_PRIVATE = 0x2000,
++ gcvUNIFORM_LOADTIME_CONSTANT = 0x4000,
++ gcvUNIFORM_IS_ARRAY = 0x8000,
++}
++gceUNIFORM_FLAGS;
++
++#define gcdUNIFORM_KERNEL_ARG_MASK (gcvUNIFORM_KERNEL_ARG | \
++ gcvUNIFORM_KERNEL_ARG_LOCAL | \
++ gcvUNIFORM_KERNEL_ARG_SAMPLER | \
++ gcvUNIFORM_KERNEL_ARG_PRIVATE | \
++ gcvUNIFORM_KERNEL_ARG_CONSTANT)
++
++typedef enum _gceVARIABLE_UPDATE_FLAGS
++{
++ gcvVARIABLE_UPDATE_NOUPDATE = 0,
++ gcvVARIABLE_UPDATE_TEMPREG,
++ gcvVARIABLE_UPDATE_TYPE_QUALIFIER,
++}gceVARIABLE_UPDATE_FLAGS;
++
++typedef struct _gcMACHINE_INST
++{
++ gctUINT state0;
++ gctUINT state1;
++ gctUINT state2;
++ gctUINT state3;
++}gcMACHINE_INST, *gcMACHINE_INST_PTR;
++
++typedef struct _gcMACHINECODE
++{
++ gcMACHINE_INST_PTR pCode; /* machine code */
++ gctUINT instCount; /* 128-bit count */
++ gctUINT maxConstRegNo;
++ gctUINT maxTempRegNo;
++ gctUINT endPCOfMainRoutine;
++}gcMACHINECODE, *gcMACHINECODE_PTR;
++
++typedef enum NP2_ADDRESS_MODE
++{
++ NP2_ADDRESS_MODE_CLAMP = 0,
++ NP2_ADDRESS_MODE_REPEAT = 1,
++ NP2_ADDRESS_MODE_MIRROR = 2
++}NP2_ADDRESS_MODE;
++
++typedef struct _gcNPOT_PATCH_PARAM
++{
++ gctINT samplerSlot;
++ NP2_ADDRESS_MODE addressMode[3];
++ gctINT texDimension; /* 2 or 3 */
++}gcNPOT_PATCH_PARAM, *gcNPOT_PATCH_PARAM_PTR;
++
++typedef struct _gcZBIAS_PATCH_PARAM
++{
++ /* Driver uses this to program uniform that designating zbias */
++ gctINT uniformAddr;
++ gctINT channel;
++}gcZBIAS_PATCH_PARAM, *gcZBIAS_PATCH_PARAM_PTR;
++
++void
++gcGetOptionFromEnv(
++ IN OUT gcOPTIMIZER_OPTION * Option
++ );
++
++void
++gcSetOptimizerOption(
++ IN gceSHADER_FLAGS Flags
++ );
++
++gcOPTIMIZER_OPTION *
++gcGetOptimizerOption();
++
++/*******************************************************************************
++** gcSHADER_SetCompilerVersion
++**
++** Set the compiler version of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to gcSHADER object
++**
++** gctINT *Version
++** Pointer to a two word version
++*/
++gceSTATUS
++gcSHADER_SetCompilerVersion(
++ IN gcSHADER Shader,
++ IN gctUINT32 *Version
++ );
++
++/*******************************************************************************
++** gcSHADER_GetCompilerVersion
++**
++** Get the compiler version of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR *CompilerVersion.
++** Pointer to holder of returned compilerVersion pointer
++*/
++gceSTATUS
++gcSHADER_GetCompilerVersion(
++ IN gcSHADER Shader,
++ OUT gctUINT32_PTR *CompilerVersion
++ );
++
++/*******************************************************************************
++** gcSHADER_GetType
++**
++** Get the gcSHADER object's type.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctINT *Type.
++** Pointer to return shader type.
++*/
++gceSTATUS
++gcSHADER_GetType(
++ IN gcSHADER Shader,
++ OUT gctINT *Type
++ );
++
++gctUINT
++gcSHADER_NextId();
++/*******************************************************************************
++** gcSHADER_Construct
++********************************************************************************
++**
++** Construct a new gcSHADER object.
++**
++** INPUT:
++**
++** gcoOS Hal
++** Pointer to an gcoHAL object.
++**
++** gctINT ShaderType
++** Type of gcSHADER object to cerate. 'ShaderType' can be one of the
++** following:
++**
++** gcSHADER_TYPE_VERTEX Vertex shader.
++** gcSHADER_TYPE_FRAGMENT Fragment shader.
++**
++** OUTPUT:
++**
++** gcSHADER * Shader
++** Pointer to a variable receiving the gcSHADER object pointer.
++*/
++gceSTATUS
++gcSHADER_Construct(
++ IN gcoHAL Hal,
++ IN gctINT ShaderType,
++ OUT gcSHADER * Shader
++ );
++
++/*******************************************************************************
++** gcSHADER_Destroy
++********************************************************************************
++**
++** Destroy a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_Destroy(
++ IN gcSHADER Shader
++ );
++
++/*******************************************************************************
++** gcSHADER_Copy
++********************************************************************************
++**
++** Copy a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSHADER Source
++** Pointer to a gcSHADER object that will be copied.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_Copy(
++ IN gcSHADER Shader,
++ IN gcSHADER Source
++ );
++
++/*******************************************************************************
++** gcSHADER_LoadHeader
++**
++** Load a gcSHADER object from a binary buffer. The binary buffer is layed out
++** as follows:
++** // Six word header
++** // Signature, must be 'S','H','D','R'.
++** gctINT8 signature[4];
++** gctUINT32 binFileVersion;
++** gctUINT32 compilerVersion[2];
++** gctUINT32 gcSLVersion;
++** gctUINT32 binarySize;
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++** Shader type will be returned if type in shader object is not gcSHADER_TYPE_PRECOMPILED
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer containing the shader data to load.
++**
++** gctSIZE_T BufferSize
++** Number of bytes inside the binary buffer pointed to by 'Buffer'.
++**
++** OUTPUT:
++** nothing
++**
++*/
++gceSTATUS
++gcSHADER_LoadHeader(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN gctSIZE_T BufferSize,
++ OUT gctUINT32 * ShaderVersion
++ );
++
++/*******************************************************************************
++** gcSHADER_LoadKernel
++**
++** Load a kernel function given by name into gcSHADER object
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSTRING KernelName
++** Pointer to a kernel function name
++**
++** OUTPUT:
++** nothing
++**
++*/
++gceSTATUS
++gcSHADER_LoadKernel(
++ IN gcSHADER Shader,
++ IN gctSTRING KernelName
++ );
++
++/*******************************************************************************
++** gcSHADER_Load
++********************************************************************************
++**
++** Load a gcSHADER object from a binary buffer.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer containg the shader data to load.
++**
++** gctSIZE_T BufferSize
++** Number of bytes inside the binary buffer pointed to by 'Buffer'.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_Load(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN gctSIZE_T BufferSize
++ );
++
++/*******************************************************************************
++** gcSHADER_Save
++********************************************************************************
++**
++** Save a gcSHADER object to a binary buffer.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer to be used as storage for the gcSHADER
++** object. If 'Buffer' is gcvNULL, the gcSHADER object will not be saved,
++** but the number of bytes required to hold the binary output for the
++** gcSHADER object will be returned.
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable holding the number of bytes allocated in
++** 'Buffer'. Only valid if 'Buffer' is not gcvNULL.
++**
++** OUTPUT:
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable receiving the number of bytes required to hold
++** the binary form of the gcSHADER object.
++*/
++gceSTATUS
++gcSHADER_Save(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN OUT gctSIZE_T * BufferSize
++ );
++
++/*******************************************************************************
++** gcSHADER_LoadEx
++********************************************************************************
++**
++** Load a gcSHADER object from a binary buffer.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer containg the shader data to load.
++**
++** gctSIZE_T BufferSize
++** Number of bytes inside the binary buffer pointed to by 'Buffer'.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_LoadEx(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN gctSIZE_T BufferSize
++ );
++
++/*******************************************************************************
++** gcSHADER_SaveEx
++********************************************************************************
++**
++** Save a gcSHADER object to a binary buffer.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctPOINTER Buffer
++** Pointer to a binary buffer to be used as storage for the gcSHADER
++** object. If 'Buffer' is gcvNULL, the gcSHADER object will not be saved,
++** but the number of bytes required to hold the binary output for the
++** gcSHADER object will be returned.
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable holding the number of bytes allocated in
++** 'Buffer'. Only valid if 'Buffer' is not gcvNULL.
++**
++** OUTPUT:
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable receiving the number of bytes required to hold
++** the binary form of the gcSHADER object.
++*/
++gceSTATUS
++gcSHADER_SaveEx(
++ IN gcSHADER Shader,
++ IN gctPOINTER Buffer,
++ IN OUT gctSIZE_T * BufferSize
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateAttributes
++**
++** Reallocate an array of pointers to gcATTRIBUTE objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateAttributes(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++/*******************************************************************************
++** gcSHADER_AddAttribute
++********************************************************************************
++**
++** Add an attribute to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the attribute to add.
++**
++** gcSHADER_TYPE Type
++** Type of the attribute to add.
++**
++** gctSIZE_T Length
++** Array length of the attribute to add. 'Length' must be at least 1.
++**
++** gctBOOL IsTexture
++** gcvTRUE if the attribute is used as a texture coordinate, gcvFALSE if not.
++**
++** OUTPUT:
++**
++** gcATTRIBUTE * Attribute
++** Pointer to a variable receiving the gcATTRIBUTE object pointer.
++*/
++gceSTATUS
++gcSHADER_AddAttribute(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctBOOL IsTexture,
++ OUT gcATTRIBUTE * Attribute
++ );
++
++/*******************************************************************************
++** gcSHADER_GetAttributeCount
++********************************************************************************
++**
++** Get the number of attributes for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of attributes.
++*/
++gceSTATUS
++gcSHADER_GetAttributeCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_GetAttribute
++********************************************************************************
++**
++** Get the gcATTRIBUTE object poniter for an indexed attribute for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of the attribute to retrieve.
++**
++** OUTPUT:
++**
++** gcATTRIBUTE * Attribute
++** Pointer to a variable receiving the gcATTRIBUTE object pointer.
++*/
++gceSTATUS
++gcSHADER_GetAttribute(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcATTRIBUTE * Attribute
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateUniforms
++**
++** Reallocate an array of pointers to gcUNIFORM objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateUniforms(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++/*******************************************************************************
++** gcSHADER_AddUniform
++********************************************************************************
++**
++** Add an uniform to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the uniform to add.
++**
++** gcSHADER_TYPE Type
++** Type of the uniform to add.
++**
++** gctSIZE_T Length
++** Array length of the uniform to add. 'Length' must be at least 1.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++*/
++gceSTATUS
++gcSHADER_AddUniform(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ OUT gcUNIFORM * Uniform
++ );
++
++/*******************************************************************************
++** gcSHADER_AddPreRotationUniform
++********************************************************************************
++**
++** Add an uniform to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the uniform to add.
++**
++** gcSHADER_TYPE Type
++** Type of the uniform to add.
++**
++** gctSIZE_T Length
++** Array length of the uniform to add. 'Length' must be at least 1.
++**
++** gctINT col
++** Which uniform.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++*/
++gceSTATUS
++gcSHADER_AddPreRotationUniform(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctINT col,
++ OUT gcUNIFORM * Uniform
++ );
++
++/*******************************************************************************
++** gcSHADER_AddUniformEx
++********************************************************************************
++**
++** Add an uniform to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the uniform to add.
++**
++** gcSHADER_TYPE Type
++** Type of the uniform to add.
++**
++** gcSHADER_PRECISION precision
++** Precision of the uniform to add.
++**
++** gctSIZE_T Length
++** Array length of the uniform to add. 'Length' must be at least 1.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++*/
++gceSTATUS
++gcSHADER_AddUniformEx(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gcSHADER_PRECISION precision,
++ IN gctSIZE_T Length,
++ OUT gcUNIFORM * Uniform
++ );
++
++/*******************************************************************************
++** gcSHADER_AddUniformEx1
++********************************************************************************
++**
++** Add an uniform to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the uniform to add.
++**
++** gcSHADER_TYPE Type
++** Type of the uniform to add.
++**
++** gcSHADER_PRECISION precision
++** Precision of the uniform to add.
++**
++** gctSIZE_T Length
++** Array length of the uniform to add. 'Length' must be at least 1.
++**
++** gcSHADER_VAR_CATEGORY varCategory
++** Variable category, normal or struct.
++**
++** gctUINT16 numStructureElement
++** If struct, its element number.
++**
++** gctINT16 parent
++** If struct, parent index in gcSHADER.variables.
++**
++** gctINT16 prevSibling
++** If struct, previous sibling index in gcSHADER.variables.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++**
++** gctINT16* ThisUniformIndex
++** Returned value about uniform index in gcSHADER.
++*/
++gceSTATUS
++gcSHADER_AddUniformEx1(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gcSHADER_PRECISION precision,
++ IN gctSIZE_T Length,
++ IN gctINT IsArray,
++ IN gcSHADER_VAR_CATEGORY varCategory,
++ IN gctUINT16 numStructureElement,
++ IN gctINT16 parent,
++ IN gctINT16 prevSibling,
++ OUT gctINT16* ThisUniformIndex,
++ OUT gcUNIFORM * Uniform
++ );
++
++/*******************************************************************************
++** gcSHADER_GetUniformCount
++********************************************************************************
++**
++** Get the number of uniforms for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of uniforms.
++*/
++gceSTATUS
++gcSHADER_GetUniformCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_GetPreRotationUniform
++********************************************************************************
++**
++** Get the preRotate Uniform.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gcUNIFORM ** pUniform
++** Pointer to a preRotation uniforms array.
++*/
++gceSTATUS
++gcSHADER_GetPreRotationUniform(
++ IN gcSHADER Shader,
++ OUT gcUNIFORM ** pUniform
++ );
++
++/*******************************************************************************
++** gcSHADER_GetUniform
++********************************************************************************
++**
++** Get the gcUNIFORM object pointer for an indexed uniform for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of the uniform to retrieve.
++**
++** OUTPUT:
++**
++** gcUNIFORM * Uniform
++** Pointer to a variable receiving the gcUNIFORM object pointer.
++*/
++gceSTATUS
++gcSHADER_GetUniform(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcUNIFORM * Uniform
++ );
++
++
++/*******************************************************************************
++** gcSHADER_GetUniformIndexingRange
++********************************************************************************
++**
++** Get the gcUNIFORM object pointer for an indexed uniform for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctINT uniformIndex
++** Index of the start uniform.
++**
++** gctINT offset
++** Offset to indexing.
++**
++** OUTPUT:
++**
++** gctINT * LastUniformIndex
++** Pointer to index of last uniform in indexing range.
++**
++** gctINT * OffsetUniformIndex
++** Pointer to index of uniform that indexing at offset.
++**
++** gctINT * DeviationInOffsetUniform
++** Pointer to offset in uniform picked up.
++*/
++gceSTATUS
++gcSHADER_GetUniformIndexingRange(
++ IN gcSHADER Shader,
++ IN gctINT uniformIndex,
++ IN gctINT offset,
++ OUT gctINT * LastUniformIndex,
++ OUT gctINT * OffsetUniformIndex,
++ OUT gctINT * DeviationInOffsetUniform
++ );
++
++/*******************************************************************************
++** gcSHADER_GetKernelFucntion
++**
++** Get the gcKERNEL_FUNCTION object pointer for an indexed kernel function for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of kernel function to retreive the name for.
++**
++** OUTPUT:
++**
++** gcKERNEL_FUNCTION * KernelFunction
++** Pointer to a variable receiving the gcKERNEL_FUNCTION object pointer.
++*/
++gceSTATUS
++gcSHADER_GetKernelFunction(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcKERNEL_FUNCTION * KernelFunction
++ );
++
++gceSTATUS
++gcSHADER_GetKernelFunctionByName(
++ IN gcSHADER Shader,
++ IN gctSTRING KernelName,
++ OUT gcKERNEL_FUNCTION * KernelFunction
++ );
++/*******************************************************************************
++** gcSHADER_GetKernelFunctionCount
++**
++** Get the number of kernel functions for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of kernel functions.
++*/
++gceSTATUS
++gcSHADER_GetKernelFunctionCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateOutputs
++**
++** Reallocate an array of pointers to gcOUTPUT objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateOutputs(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOutput
++********************************************************************************
++**
++** Add an output to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the output to add.
++**
++** gcSHADER_TYPE Type
++** Type of the output to add.
++**
++** gctSIZE_T Length
++** Array length of the output to add. 'Length' must be at least 1.
++**
++** gctUINT16 TempRegister
++** Temporary register index that holds the output value.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOutput(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctUINT16 TempRegister
++ );
++
++gceSTATUS
++gcSHADER_AddOutputIndexed(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gctSIZE_T Index,
++ IN gctUINT16 TempIndex
++ );
++
++/*******************************************************************************
++** gcSHADER_GetOutputCount
++********************************************************************************
++**
++** Get the number of outputs for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of outputs.
++*/
++gceSTATUS
++gcSHADER_GetOutputCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_GetOutput
++********************************************************************************
++**
++** Get the gcOUTPUT object pointer for an indexed output for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of output to retrieve.
++**
++** OUTPUT:
++**
++** gcOUTPUT * Output
++** Pointer to a variable receiving the gcOUTPUT object pointer.
++*/
++gceSTATUS
++gcSHADER_GetOutput(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcOUTPUT * Output
++ );
++
++
++/*******************************************************************************
++** gcSHADER_GetOutputByName
++********************************************************************************
++**
++** Get the gcOUTPUT object pointer for this shader by output name.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSTRING name
++** Name of output to retrieve.
++**
++** gctSIZE_T nameLength
++** Length of name to retrieve
++**
++** OUTPUT:
++**
++** gcOUTPUT * Output
++** Pointer to a variable receiving the gcOUTPUT object pointer.
++*/
++gceSTATUS
++gcSHADER_GetOutputByName(
++ IN gcSHADER Shader,
++ IN gctSTRING name,
++ IN gctSIZE_T nameLength,
++ OUT gcOUTPUT * Output
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateVariables
++**
++** Reallocate an array of pointers to gcVARIABLE objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateVariables(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++/*******************************************************************************
++** gcSHADER_AddVariable
++********************************************************************************
++**
++** Add a variable to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the variable to add.
++**
++** gcSHADER_TYPE Type
++** Type of the variable to add.
++**
++** gctSIZE_T Length
++** Array length of the variable to add. 'Length' must be at least 1.
++**
++** gctUINT16 TempRegister
++** Temporary register index that holds the variable value.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddVariable(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctUINT16 TempRegister
++ );
++
++
++/*******************************************************************************
++** gcSHADER_AddVariableEx
++********************************************************************************
++**
++** Add a variable to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctCONST_STRING Name
++** Name of the variable to add.
++**
++** gcSHADER_TYPE Type
++** Type of the variable to add.
++**
++** gctSIZE_T Length
++** Array length of the variable to add. 'Length' must be at least 1.
++**
++** gctUINT16 TempRegister
++** Temporary register index that holds the variable value.
++**
++** gcSHADER_VAR_CATEGORY varCategory
++** Variable category, normal or struct.
++**
++** gctUINT16 numStructureElement
++** If struct, its element number.
++**
++** gctINT16 parent
++** If struct, parent index in gcSHADER.variables.
++**
++** gctINT16 prevSibling
++** If struct, previous sibling index in gcSHADER.variables.
++**
++** OUTPUT:
++**
++** gctINT16* ThisVarIndex
++** Returned value about variable index in gcSHADER.
++*/
++gceSTATUS
++gcSHADER_AddVariableEx(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ IN gctUINT16 TempRegister,
++ IN gcSHADER_VAR_CATEGORY varCategory,
++ IN gctUINT16 numStructureElement,
++ IN gctINT16 parent,
++ IN gctINT16 prevSibling,
++ OUT gctINT16* ThisVarIndex
++ );
++
++/*******************************************************************************
++** gcSHADER_UpdateVariable
++********************************************************************************
++**
++** Update a variable to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of variable to retrieve.
++**
++** gceVARIABLE_UPDATE_FLAGS flag
++** Flag which property of variable will be updated.
++**
++** gctUINT newValue
++** New value to update.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_UpdateVariable(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ IN gceVARIABLE_UPDATE_FLAGS flag,
++ IN gctUINT newValue
++ );
++
++/*******************************************************************************
++** gcSHADER_GetVariableCount
++********************************************************************************
++**
++** Get the number of variables for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Count
++** Pointer to a variable receiving the number of variables.
++*/
++gceSTATUS
++gcSHADER_GetVariableCount(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * Count
++ );
++
++/*******************************************************************************
++** gcSHADER_GetVariable
++********************************************************************************
++**
++** Get the gcVARIABLE object pointer for an indexed variable for this shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Index
++** Index of variable to retrieve.
++**
++** OUTPUT:
++**
++** gcVARIABLE * Variable
++** Pointer to a variable receiving the gcVARIABLE object pointer.
++*/
++gceSTATUS
++gcSHADER_GetVariable(
++ IN gcSHADER Shader,
++ IN gctUINT Index,
++ OUT gcVARIABLE * Variable
++ );
++
++/*******************************************************************************
++** gcSHADER_GetVariableIndexingRange
++********************************************************************************
++**
++** Get the gcVARIABLE indexing range.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcVARIABLE variable
++** Start variable.
++**
++** gctBOOL whole
++** Indicate whether maximum indexing range is queried
++**
++** OUTPUT:
++**
++** gctUINT *Start
++** Pointer to range start (temp register index).
++**
++** gctUINT *End
++** Pointer to range end (temp register index).
++*/
++gceSTATUS
++gcSHADER_GetVariableIndexingRange(
++ IN gcSHADER Shader,
++ IN gcVARIABLE variable,
++ IN gctBOOL whole,
++ OUT gctUINT *Start,
++ OUT gctUINT *End
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcode
++********************************************************************************
++**
++** Add an opcode to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gctUINT16 TempRegister
++** Temporary register index that acts as the target of the opcode.
++**
++** gctUINT8 Enable
++** Write enable bits for the temporary register that acts as the target
++** of the opcode.
++**
++** gcSL_FORMAT Format
++** Format of the temporary register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcode(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gctUINT16 TempRegister,
++ IN gctUINT8 Enable,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddOpcode2(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gctUINT16 TempRegister,
++ IN gctUINT8 Enable,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeIndexed
++********************************************************************************
++**
++** Add an opcode to a gcSHADER object that writes to an dynamically indexed
++** target.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gctUINT16 TempRegister
++** Temporary register index that acts as the target of the opcode.
++**
++** gctUINT8 Enable
++** Write enable bits for the temporary register that acts as the
++** target of the opcode.
++**
++** gcSL_INDEXED Mode
++** Location of the dynamic index inside the temporary register. Valid
++** values can be:
++**
++** gcSL_INDEXED_X - Use x component of the temporary register.
++** gcSL_INDEXED_Y - Use y component of the temporary register.
++** gcSL_INDEXED_Z - Use z component of the temporary register.
++** gcSL_INDEXED_W - Use w component of the temporary register.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** gcSL_FORMAT Format
++** Format of the temporary register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeIndexed(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gctUINT16 TempRegister,
++ IN gctUINT8 Enable,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeConditionIndexed
++**
++** Add an opcode to a gcSHADER object that writes to an dynamically indexed
++** target.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gcSL_CONDITION Condition
++** Condition to check.
++**
++** gctUINT16 TempRegister
++** Temporary register index that acts as the target of the opcode.
++**
++** gctUINT8 Enable
++** Write enable bits for the temporary register that acts as the
++** target of the opcode.
++**
++** gcSL_INDEXED Indexed
++** Location of the dynamic index inside the temporary register. Valid
++** values can be:
++**
++** gcSL_INDEXED_X - Use x component of the temporary register.
++** gcSL_INDEXED_Y - Use y component of the temporary register.
++** gcSL_INDEXED_Z - Use z component of the temporary register.
++** gcSL_INDEXED_W - Use w component of the temporary register.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeConditionIndexed(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gctUINT16 TempRegister,
++ IN gctUINT8 Enable,
++ IN gcSL_INDEXED Indexed,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeConditional
++********************************************************************************
++**
++** Add an conditional opcode to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gcSL_CONDITION Condition
++** Condition that needs to evaluate to gcvTRUE in order for the opcode to
++** execute.
++**
++** gctUINT Label
++** Target label if 'Condition' evaluates to gcvTRUE.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeConditional(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gctUINT Label
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeConditionalFormatted
++**
++** Add an conditional jump or call opcode to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gcSL_CONDITION Condition
++** Condition that needs to evaluate to gcvTRUE in order for the opcode to
++** execute.
++**
++** gcSL_FORMAT Format
++** Format of conditional operands
++**
++** gctUINT Label
++** Target label if 'Condition' evaluates to gcvTRUE.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeConditionalFormatted(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gcSL_FORMAT Format,
++ IN gctUINT Label
++ );
++
++/*******************************************************************************
++** gcSHADER_AddOpcodeConditionalFormattedEnable
++**
++** Add an conditional jump or call opcode to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_OPCODE Opcode
++** Opcode to add.
++**
++** gcSL_CONDITION Condition
++** Condition that needs to evaluate to gcvTRUE in order for the opcode to
++** execute.
++**
++** gcSL_FORMAT Format
++** Format of conditional operands
++**
++** gctUINT8 Enable
++** Write enable value for the target of the opcode.
++**
++** gctUINT Label
++** Target label if 'Condition' evaluates to gcvTRUE.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddOpcodeConditionalFormattedEnable(
++ IN gcSHADER Shader,
++ IN gcSL_OPCODE Opcode,
++ IN gcSL_CONDITION Condition,
++ IN gcSL_FORMAT Format,
++ IN gctUINT8 Enable,
++ IN gctUINT Label
++ );
++
++/*******************************************************************************
++** gcSHADER_AddLabel
++********************************************************************************
++**
++** Define a label at the current instruction of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT Label
++** Label to define.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddLabel(
++ IN gcSHADER Shader,
++ IN gctUINT Label
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSource
++********************************************************************************
++**
++** Add a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_TYPE Type
++** Type of the source operand.
++**
++** gctUINT16 SourceIndex
++** Index of the source operand.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gcSL_FORMAT Format
++** Format of the source operand.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSource(
++ IN gcSHADER Shader,
++ IN gcSL_TYPE Type,
++ IN gctUINT16 SourceIndex,
++ IN gctUINT8 Swizzle,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceIndexed
++********************************************************************************
++**
++** Add a dynamically indexed source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcSL_TYPE Type
++** Type of the source operand.
++**
++** gctUINT16 SourceIndex
++** Index of the source operand.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gcSL_INDEXED Mode
++** Addressing mode for the index.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** gcSL_FORMAT Format
++** Format of the source operand.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceIndexed(
++ IN gcSHADER Shader,
++ IN gcSL_TYPE Type,
++ IN gctUINT16 SourceIndex,
++ IN gctUINT8 Swizzle,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceAttribute
++********************************************************************************
++**
++** Add an attribute as a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gctINT Index
++** Static index into the attribute in case the attribute is a matrix
++** or array.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceAttribute(
++ IN gcSHADER Shader,
++ IN gcATTRIBUTE Attribute,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceAttributeIndexed
++********************************************************************************
++**
++** Add an indexed attribute as a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gctINT Index
++** Static index into the attribute in case the attribute is a matrix
++** or array.
++**
++** gcSL_INDEXED Mode
++** Addressing mode of the dynamic index.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceAttributeIndexed(
++ IN gcSHADER Shader,
++ IN gcATTRIBUTE Attribute,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceUniform
++********************************************************************************
++**
++** Add a uniform as a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gctINT Index
++** Static index into the uniform in case the uniform is a matrix or
++** array.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceUniform(
++ IN gcSHADER Shader,
++ IN gcUNIFORM Uniform,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceUniformIndexed
++********************************************************************************
++**
++** Add an indexed uniform as a source operand to a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctUINT8 Swizzle
++** x, y, z, and w swizzle values packed into one 8-bit value.
++**
++** gctINT Index
++** Static index into the uniform in case the uniform is a matrix or
++** array.
++**
++** gcSL_INDEXED Mode
++** Addressing mode of the dynamic index.
++**
++** gctUINT16 IndexRegister
++** Temporary register index that holds the dynamic index.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceUniformIndexed(
++ IN gcSHADER Shader,
++ IN gcUNIFORM Uniform,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister
++ );
++
++gceSTATUS
++gcSHADER_AddSourceSamplerIndexed(
++ IN gcSHADER Shader,
++ IN gctUINT8 Swizzle,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister
++ );
++
++gceSTATUS
++gcSHADER_AddSourceAttributeFormatted(
++ IN gcSHADER Shader,
++ IN gcATTRIBUTE Attribute,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddSourceAttributeIndexedFormatted(
++ IN gcSHADER Shader,
++ IN gcATTRIBUTE Attribute,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddSourceUniformFormatted(
++ IN gcSHADER Shader,
++ IN gcUNIFORM Uniform,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddSourceUniformIndexedFormatted(
++ IN gcSHADER Shader,
++ IN gcUNIFORM Uniform,
++ IN gctUINT8 Swizzle,
++ IN gctINT Index,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++gceSTATUS
++gcSHADER_AddSourceSamplerIndexedFormatted(
++ IN gcSHADER Shader,
++ IN gctUINT8 Swizzle,
++ IN gcSL_INDEXED Mode,
++ IN gctUINT16 IndexRegister,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceConstant
++********************************************************************************
++**
++** Add a constant floating point value as a source operand to a gcSHADER
++** object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctFLOAT Constant
++** Floating point constant.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceConstant(
++ IN gcSHADER Shader,
++ IN gctFLOAT Constant
++ );
++
++/*******************************************************************************
++** gcSHADER_AddSourceConstantFormatted
++********************************************************************************
++**
++** Add a constant value as a source operand to a gcSHADER
++** object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** void * Constant
++** Pointer to constant.
++**
++** gcSL_FORMAT Format
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_AddSourceConstantFormatted(
++ IN gcSHADER Shader,
++ IN void *Constant,
++ IN gcSL_FORMAT Format
++ );
++
++/*******************************************************************************
++** gcSHADER_Pack
++********************************************************************************
++**
++** Pack a dynamically created gcSHADER object by trimming the allocated arrays
++** and resolving all the labeling.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_Pack(
++ IN gcSHADER Shader
++ );
++
++/*******************************************************************************
++** gcSHADER_SetOptimizationOption
++********************************************************************************
++**
++** Set optimization option of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctUINT OptimizationOption
++** Optimization option. Can be one of the following:
++**
++** 0 - No optimization.
++** 1 - Full optimization.
++** Other value - For optimizer testing.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcSHADER_SetOptimizationOption(
++ IN gcSHADER Shader,
++ IN gctUINT OptimizationOption
++ );
++
++/*******************************************************************************
++** gcSHADER_ReallocateFunctions
++**
++** Reallocate an array of pointers to gcFUNCTION objects.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcSHADER_ReallocateFunctions(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcSHADER_AddFunction(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ OUT gcFUNCTION * Function
++ );
++
++gceSTATUS
++gcSHADER_ReallocateKernelFunctions(
++ IN gcSHADER Shader,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcSHADER_AddKernelFunction(
++ IN gcSHADER Shader,
++ IN gctCONST_STRING Name,
++ OUT gcKERNEL_FUNCTION * KernelFunction
++ );
++
++gceSTATUS
++gcSHADER_BeginFunction(
++ IN gcSHADER Shader,
++ IN gcFUNCTION Function
++ );
++
++gceSTATUS
++gcSHADER_EndFunction(
++ IN gcSHADER Shader,
++ IN gcFUNCTION Function
++ );
++
++gceSTATUS
++gcSHADER_BeginKernelFunction(
++ IN gcSHADER Shader,
++ IN gcKERNEL_FUNCTION KernelFunction
++ );
++
++gceSTATUS
++gcSHADER_EndKernelFunction(
++ IN gcSHADER Shader,
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctSIZE_T LocalMemorySize
++ );
++
++gceSTATUS
++gcSHADER_SetMaxKernelFunctionArgs(
++ IN gcSHADER Shader,
++ IN gctUINT32 MaxKernelFunctionArgs
++ );
++
++/*******************************************************************************
++** gcSHADER_SetConstantMemorySize
++**
++** Set the constant memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T ConstantMemorySize
++** Constant memory size in bytes
++**
++** gctCHAR *ConstantMemoryBuffer
++** Constant memory buffer
++*/
++gceSTATUS
++gcSHADER_SetConstantMemorySize(
++ IN gcSHADER Shader,
++ IN gctSIZE_T ConstantMemorySize,
++ IN gctCHAR * ConstantMemoryBuffer
++ );
++
++/*******************************************************************************
++** gcSHADER_GetConstantMemorySize
++**
++** Set the constant memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * ConstantMemorySize
++** Pointer to a variable receiving constant memory size in bytes
++**
++** gctCHAR **ConstantMemoryBuffer.
++** Pointer to a variable for returned shader constant memory buffer.
++*/
++gceSTATUS
++gcSHADER_GetConstantMemorySize(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * ConstantMemorySize,
++ OUT gctCHAR ** ConstantMemoryBuffer
++ );
++
++/*******************************************************************************
++** gcSHADER_SetPrivateMemorySize
++**
++** Set the private memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T PrivateMemorySize
++** Private memory size in bytes
++*/
++gceSTATUS
++gcSHADER_SetPrivateMemorySize(
++ IN gcSHADER Shader,
++ IN gctSIZE_T PrivateMemorySize
++ );
++
++/*******************************************************************************
++** gcSHADER_GetPrivateMemorySize
++**
++** Set the private memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * PrivateMemorySize
++** Pointer to a variable receiving private memory size in bytes
++*/
++gceSTATUS
++gcSHADER_GetPrivateMemorySize(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * PrivateMemorySize
++ );
++
++/*******************************************************************************
++** gcSHADER_SetLocalMemorySize
++**
++** Set the local memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** gctSIZE_T LocalMemorySize
++** Local memory size in bytes
++*/
++gceSTATUS
++gcSHADER_SetLocalMemorySize(
++ IN gcSHADER Shader,
++ IN gctSIZE_T LocalMemorySize
++ );
++
++/*******************************************************************************
++** gcSHADER_GetLocalMemorySize
++**
++** Set the local memory address space size of a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * LocalMemorySize
++** Pointer to a variable receiving lcoal memory size in bytes
++*/
++gceSTATUS
++gcSHADER_GetLocalMemorySize(
++ IN gcSHADER Shader,
++ OUT gctSIZE_T * LocalMemorySize
++ );
++
++
++/*******************************************************************************
++** gcSHADER_CheckValidity
++**
++** Check validity for a gcSHADER object.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object.
++**
++*/
++gceSTATUS
++gcSHADER_CheckValidity(
++ IN gcSHADER Shader
++ );
++
++#if gcdUSE_WCLIP_PATCH
++gceSTATUS
++gcATTRIBUTE_IsPosition(
++ IN gcATTRIBUTE Attribute,
++ OUT gctBOOL * IsPosition
++ );
++#endif
++
++/*******************************************************************************
++** gcATTRIBUTE_GetType
++********************************************************************************
++**
++** Get the type and array length of a gcATTRIBUTE object.
++**
++** INPUT:
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** OUTPUT:
++**
++** gcSHADER_TYPE * Type
++** Pointer to a variable receiving the type of the attribute. 'Type'
++** can be gcvNULL, in which case no type will be returned.
++**
++** gctSIZE_T * ArrayLength
++** Pointer to a variable receiving the length of the array if the
++** attribute was declared as an array. If the attribute was not
++** declared as an array, the array length will be 1. 'ArrayLength' can
++** be gcvNULL, in which case no array length will be returned.
++*/
++gceSTATUS
++gcATTRIBUTE_GetType(
++ IN gcATTRIBUTE Attribute,
++ OUT gcSHADER_TYPE * Type,
++ OUT gctSIZE_T * ArrayLength
++ );
++
++/*******************************************************************************
++** gcATTRIBUTE_GetName
++********************************************************************************
++**
++** Get the name of a gcATTRIBUTE object.
++**
++** INPUT:
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Length
++** Pointer to a variable receiving the length of the attribute name.
++** 'Length' can be gcvNULL, in which case no length will be returned.
++**
++** gctCONST_STRING * Name
++** Pointer to a variable receiving the pointer to the attribute name.
++** 'Name' can be gcvNULL, in which case no name will be returned.
++*/
++gceSTATUS
++gcATTRIBUTE_GetName(
++ IN gcATTRIBUTE Attribute,
++ OUT gctSIZE_T * Length,
++ OUT gctCONST_STRING * Name
++ );
++
++/*******************************************************************************
++** gcATTRIBUTE_IsEnabled
++********************************************************************************
++**
++** Query the enabled state of a gcATTRIBUTE object.
++**
++** INPUT:
++**
++** gcATTRIBUTE Attribute
++** Pointer to a gcATTRIBUTE object.
++**
++** OUTPUT:
++**
++** gctBOOL * Enabled
++** Pointer to a variable receiving the enabled state of the attribute.
++*/
++gceSTATUS
++gcATTRIBUTE_IsEnabled(
++ IN gcATTRIBUTE Attribute,
++ OUT gctBOOL * Enabled
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetType
++********************************************************************************
++**
++** Get the type and array length of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gcSHADER_TYPE * Type
++** Pointer to a variable receiving the type of the uniform. 'Type' can
++** be gcvNULL, in which case no type will be returned.
++**
++** gctSIZE_T * ArrayLength
++** Pointer to a variable receiving the length of the array if the
++** uniform was declared as an array. If the uniform was not declared
++** as an array, the array length will be 1. 'ArrayLength' can be gcvNULL,
++** in which case no array length will be returned.
++*/
++gceSTATUS
++gcUNIFORM_GetType(
++ IN gcUNIFORM Uniform,
++ OUT gcSHADER_TYPE * Type,
++ OUT gctSIZE_T * ArrayLength
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetTypeEx
++********************************************************************************
++**
++** Get the type and array length of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gcSHADER_TYPE * Type
++** Pointer to a variable receiving the type of the uniform. 'Type' can
++** be gcvNULL, in which case no type will be returned.
++**
++** gcSHADER_PRECISION * Precision
++** Pointer to a variable receiving the precision of the uniform. 'Precision' can
++** be gcvNULL, in which case no type will be returned.
++**
++** gctSIZE_T * ArrayLength
++** Pointer to a variable receiving the length of the array if the
++** uniform was declared as an array. If the uniform was not declared
++** as an array, the array length will be 1. 'ArrayLength' can be gcvNULL,
++** in which case no array length will be returned.
++*/
++gceSTATUS
++gcUNIFORM_GetTypeEx(
++ IN gcUNIFORM Uniform,
++ OUT gcSHADER_TYPE * Type,
++ OUT gcSHADER_PRECISION * Precision,
++ OUT gctSIZE_T * ArrayLength
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetFlags
++********************************************************************************
++**
++** Get the flags of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gceUNIFORM_FLAGS * Flags
++** Pointer to a variable receiving the flags of the uniform.
++**
++*/
++gceSTATUS
++gcUNIFORM_GetFlags(
++ IN gcUNIFORM Uniform,
++ OUT gceUNIFORM_FLAGS * Flags
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetFlags
++********************************************************************************
++**
++** Set the flags of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gceUNIFORM_FLAGS Flags
++** Flags of the uniform to be set.
++**
++** OUTPUT:
++** Nothing.
++**
++*/
++gceSTATUS
++gcUNIFORM_SetFlags(
++ IN gcUNIFORM Uniform,
++ IN gceUNIFORM_FLAGS Flags
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetName
++********************************************************************************
++**
++** Get the name of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Length
++** Pointer to a variable receiving the length of the uniform name.
++** 'Length' can be gcvNULL, in which case no length will be returned.
++**
++** gctCONST_STRING * Name
++** Pointer to a variable receiving the pointer to the uniform name.
++** 'Name' can be gcvNULL, in which case no name will be returned.
++*/
++gceSTATUS
++gcUNIFORM_GetName(
++ IN gcUNIFORM Uniform,
++ OUT gctSIZE_T * Length,
++ OUT gctCONST_STRING * Name
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetSampler
++********************************************************************************
++**
++** Get the physical sampler number for a sampler gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Sampler
++** Pointer to a variable receiving the physical sampler.
++*/
++gceSTATUS
++gcUNIFORM_GetSampler(
++ IN gcUNIFORM Uniform,
++ OUT gctUINT32 * Sampler
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetFormat
++**
++** Get the type and array length of a gcUNIFORM object.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** gcSL_FORMAT * Format
++** Pointer to a variable receiving the format of element of the uniform.
++** 'Type' can be gcvNULL, in which case no type will be returned.
++**
++** gctBOOL * IsPointer
++** Pointer to a variable receiving the state wheter the uniform is a pointer.
++** 'IsPointer' can be gcvNULL, in which case no array length will be returned.
++*/
++gceSTATUS
++gcUNIFORM_GetFormat(
++ IN gcUNIFORM Uniform,
++ OUT gcSL_FORMAT * Format,
++ OUT gctBOOL * IsPointer
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetFormat
++**
++** Set the format and isPointer of a uniform.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gcSL_FORMAT Format
++** Format of element of the uniform shaderType.
++**
++** gctBOOL IsPointer
++** Wheter the uniform is a pointer.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_SetFormat(
++ IN gcUNIFORM Uniform,
++ IN gcSL_FORMAT Format,
++ IN gctBOOL IsPointer
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetValue
++********************************************************************************
++**
++** Set the value of a uniform in integer.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctSIZE_T Count
++** Number of entries to program if the uniform has been declared as an
++** array.
++**
++** const gctINT * Value
++** Pointer to a buffer holding the integer values for the uniform.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_SetValue(
++ IN gcUNIFORM Uniform,
++ IN gctSIZE_T Count,
++ IN const gctINT * Value
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetValueX
++********************************************************************************
++**
++** Set the value of a uniform in fixed point.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctSIZE_T Count
++** Number of entries to program if the uniform has been declared as an
++** array.
++**
++** const gctFIXED_POINT * Value
++** Pointer to a buffer holding the fixed point values for the uniform.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_SetValueX(
++ IN gcUNIFORM Uniform,
++ IN gctSIZE_T Count,
++ IN gctFIXED_POINT * Value
++ );
++
++/*******************************************************************************
++** gcUNIFORM_SetValueF
++********************************************************************************
++**
++** Set the value of a uniform in floating point.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** gctSIZE_T Count
++** Number of entries to program if the uniform has been declared as an
++** array.
++**
++** const gctFLOAT * Value
++** Pointer to a buffer holding the floating point values for the
++** uniform.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_SetValueF(
++ IN gcUNIFORM Uniform,
++ IN gctSIZE_T Count,
++ IN const gctFLOAT * Value
++ );
++
++/*******************************************************************************
++** gcUNIFORM_ProgramF
++**
++** Set the value of a uniform in floating point.
++**
++** INPUT:
++**
++** gctUINT32 Address
++** Address of Uniform.
++**
++** gctSIZE_T Row/Col
++**
++** const gctFLOAT * Value
++** Pointer to a buffer holding the floating point values for the
++** uniform.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gcUNIFORM_ProgramF(
++ IN gctUINT32 Address,
++ IN gctSIZE_T Row,
++ IN gctSIZE_T Col,
++ IN const gctFLOAT * Value
++ );
++
++/*******************************************************************************
++** gcUNIFORM_GetModelViewProjMatrix
++********************************************************************************
++**
++** Get the value of uniform modelViewProjMatrix ID if present.
++**
++** INPUT:
++**
++** gcUNIFORM Uniform
++** Pointer to a gcUNIFORM object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gctUINT
++gcUNIFORM_GetModelViewProjMatrix(
++ IN gcUNIFORM Uniform
++ );
++
++/*******************************************************************************
++** gcOUTPUT_GetType
++********************************************************************************
++**
++** Get the type and array length of a gcOUTPUT object.
++**
++** INPUT:
++**
++** gcOUTPUT Output
++** Pointer to a gcOUTPUT object.
++**
++** OUTPUT:
++**
++** gcSHADER_TYPE * Type
++** Pointer to a variable receiving the type of the output. 'Type' can
++** be gcvNULL, in which case no type will be returned.
++**
++** gctSIZE_T * ArrayLength
++** Pointer to a variable receiving the length of the array if the
++** output was declared as an array. If the output was not declared
++** as an array, the array length will be 1. 'ArrayLength' can be gcvNULL,
++** in which case no array length will be returned.
++*/
++gceSTATUS
++gcOUTPUT_GetType(
++ IN gcOUTPUT Output,
++ OUT gcSHADER_TYPE * Type,
++ OUT gctSIZE_T * ArrayLength
++ );
++
++/*******************************************************************************
++** gcOUTPUT_GetIndex
++********************************************************************************
++**
++** Get the index of a gcOUTPUT object.
++**
++** INPUT:
++**
++** gcOUTPUT Output
++** Pointer to a gcOUTPUT object.
++**
++** OUTPUT:
++**
++** gctUINT * Index
++** Pointer to a variable receiving the temporary register index of the
++** output. 'Index' can be gcvNULL,. in which case no index will be
++** returned.
++*/
++gceSTATUS
++gcOUTPUT_GetIndex(
++ IN gcOUTPUT Output,
++ OUT gctUINT * Index
++ );
++
++/*******************************************************************************
++** gcOUTPUT_GetName
++********************************************************************************
++**
++** Get the name of a gcOUTPUT object.
++**
++** INPUT:
++**
++** gcOUTPUT Output
++** Pointer to a gcOUTPUT object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Length
++** Pointer to a variable receiving the length of the output name.
++** 'Length' can be gcvNULL, in which case no length will be returned.
++**
++** gctCONST_STRING * Name
++** Pointer to a variable receiving the pointer to the output name.
++** 'Name' can be gcvNULL, in which case no name will be returned.
++*/
++gceSTATUS
++gcOUTPUT_GetName(
++ IN gcOUTPUT Output,
++ OUT gctSIZE_T * Length,
++ OUT gctCONST_STRING * Name
++ );
++
++/*******************************************************************************
++*********************************************************** F U N C T I O N S **
++*******************************************************************************/
++
++/*******************************************************************************
++** gcFUNCTION_ReallocateArguments
++**
++** Reallocate an array of gcsFUNCTION_ARGUMENT objects.
++**
++** INPUT:
++**
++** gcFUNCTION Function
++** Pointer to a gcFUNCTION object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcFUNCTION_ReallocateArguments(
++ IN gcFUNCTION Function,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcFUNCTION_AddArgument(
++ IN gcFUNCTION Function,
++ IN gctUINT16 TempIndex,
++ IN gctUINT8 Enable,
++ IN gctUINT8 Qualifier
++ );
++
++gceSTATUS
++gcFUNCTION_GetArgument(
++ IN gcFUNCTION Function,
++ IN gctUINT16 Index,
++ OUT gctUINT16_PTR Temp,
++ OUT gctUINT8_PTR Enable,
++ OUT gctUINT8_PTR Swizzle
++ );
++
++gceSTATUS
++gcFUNCTION_GetLabel(
++ IN gcFUNCTION Function,
++ OUT gctUINT_PTR Label
++ );
++
++/*******************************************************************************
++************************* K E R N E L P R O P E R T Y F U N C T I O N S **
++*******************************************************************************/
++/*******************************************************************************/
++gceSTATUS
++gcKERNEL_FUNCTION_AddKernelFunctionProperties(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctINT propertyType,
++ IN gctSIZE_T propertySize,
++ IN gctINT * values
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetPropertyCount(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ OUT gctSIZE_T * Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetProperty(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctUINT Index,
++ OUT gctSIZE_T * propertySize,
++ OUT gctINT * propertyType,
++ OUT gctINT * propertyValues
++ );
++
++
++/*******************************************************************************
++*******************************I M A G E S A M P L E R F U N C T I O N S **
++*******************************************************************************/
++/*******************************************************************************
++** gcKERNEL_FUNCTION_ReallocateImageSamplers
++**
++** Reallocate an array of pointers to image sampler pair.
++**
++** INPUT:
++**
++** gcKERNEL_FUNCTION KernelFunction
++** Pointer to a gcKERNEL_FUNCTION object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcKERNEL_FUNCTION_ReallocateImageSamplers(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_AddImageSampler(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctUINT8 ImageNum,
++ IN gctBOOL IsConstantSamplerType,
++ IN gctUINT32 SamplerType
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetImageSamplerCount(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ OUT gctSIZE_T * Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetImageSampler(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctUINT Index,
++ OUT gctUINT8 *ImageNum,
++ OUT gctBOOL *IsConstantSamplerType,
++ OUT gctUINT32 *SamplerType
++ );
++
++/*******************************************************************************
++*********************************************K E R N E L F U N C T I O N S **
++*******************************************************************************/
++
++/*******************************************************************************
++** gcKERNEL_FUNCTION_ReallocateArguments
++**
++** Reallocate an array of gcsFUNCTION_ARGUMENT objects.
++**
++** INPUT:
++**
++** gcKERNEL_FUNCTION Function
++** Pointer to a gcKERNEL_FUNCTION object.
++**
++** gctSIZE_T Count
++** Array count to reallocate. 'Count' must be at least 1.
++*/
++gceSTATUS
++gcKERNEL_FUNCTION_ReallocateArguments(
++ IN gcKERNEL_FUNCTION Function,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_AddArgument(
++ IN gcKERNEL_FUNCTION Function,
++ IN gctUINT16 TempIndex,
++ IN gctUINT8 Enable,
++ IN gctUINT8 Qualifier
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetArgument(
++ IN gcKERNEL_FUNCTION Function,
++ IN gctUINT16 Index,
++ OUT gctUINT16_PTR Temp,
++ OUT gctUINT8_PTR Enable,
++ OUT gctUINT8_PTR Swizzle
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetLabel(
++ IN gcKERNEL_FUNCTION Function,
++ OUT gctUINT_PTR Label
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetName(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ OUT gctSIZE_T * Length,
++ OUT gctCONST_STRING * Name
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_ReallocateUniformArguments(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctSIZE_T Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_AddUniformArgument(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctCONST_STRING Name,
++ IN gcSHADER_TYPE Type,
++ IN gctSIZE_T Length,
++ OUT gcUNIFORM * UniformArgument
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetUniformArgumentCount(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ OUT gctSIZE_T * Count
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_GetUniformArgument(
++ IN gcKERNEL_FUNCTION KernelFunction,
++ IN gctUINT Index,
++ OUT gcUNIFORM * UniformArgument
++ );
++
++gceSTATUS
++gcKERNEL_FUNCTION_SetCodeEnd(
++ IN gcKERNEL_FUNCTION KernelFunction
++ );
++
++/*******************************************************************************
++** gcCompileShader
++********************************************************************************
++**
++** Compile a shader.
++**
++** INPUT:
++**
++** gcoOS Hal
++** Pointer to an gcoHAL object.
++**
++** gctINT ShaderType
++** Shader type to compile. Can be one of the following values:
++**
++** gcSHADER_TYPE_VERTEX
++** Compile a vertex shader.
++**
++** gcSHADER_TYPE_FRAGMENT
++** Compile a fragment shader.
++**
++** gctSIZE_T SourceSize
++** Size of the source buffer in bytes.
++**
++** gctCONST_STRING Source
++** Pointer to the buffer containing the shader source code.
++**
++** OUTPUT:
++**
++** gcSHADER * Binary
++** Pointer to a variable receiving the pointer to a gcSHADER object
++** containg the compiled shader code.
++**
++** gctSTRING * Log
++** Pointer to a variable receiving a string pointer containging the
++** compile log.
++*/
++gceSTATUS
++gcCompileShader(
++ IN gcoHAL Hal,
++ IN gctINT ShaderType,
++ IN gctSIZE_T SourceSize,
++ IN gctCONST_STRING Source,
++ OUT gcSHADER * Binary,
++ OUT gctSTRING * Log
++ );
++
++/*******************************************************************************
++** gcOptimizeShader
++********************************************************************************
++**
++** Optimize a shader.
++**
++** INPUT:
++**
++** gcSHADER Shader
++** Pointer to a gcSHADER object holding information about the compiled
++** shader.
++**
++** gctFILE LogFile
++** Pointer to an open FILE object.
++*/
++gceSTATUS
++gcOptimizeShader(
++ IN gcSHADER Shader,
++ IN gctFILE LogFile
++ );
++
++/*******************************************************************************
++** gcLinkShaders
++********************************************************************************
++**
++** Link two shaders and generate a harwdare specific state buffer by compiling
++** the compiler generated code through the resource allocator and code
++** generator.
++**
++** INPUT:
++**
++** gcSHADER VertexShader
++** Pointer to a gcSHADER object holding information about the compiled
++** vertex shader.
++**
++** gcSHADER FragmentShader
++** Pointer to a gcSHADER object holding information about the compiled
++** fragment shader.
++**
++** gceSHADER_FLAGS Flags
++** Compiler flags. Can be any of the following:
++**
++** gcvSHADER_DEAD_CODE - Dead code elimination.
++** gcvSHADER_RESOURCE_USAGE - Resource usage optimizaion.
++** gcvSHADER_OPTIMIZER - Full optimization.
++** gcvSHADER_USE_GL_Z - Use OpenGL ES Z coordinate.
++** gcvSHADER_USE_GL_POSITION - Use OpenGL ES gl_Position.
++** gcvSHADER_USE_GL_FACE - Use OpenGL ES gl_FaceForward.
++**
++** OUTPUT:
++**
++** gctSIZE_T * StateBufferSize
++** Pointer to a variable receicing the number of bytes in the buffer
++** returned in 'StateBuffer'.
++**
++** gctPOINTER * StateBuffer
++** Pointer to a variable receiving a buffer pointer that contains the
++** states required to download the shaders into the hardware.
++**
++** gcsHINT_PTR * Hints
++** Pointer to a variable receiving a gcsHINT structure pointer that
++** contains information required when loading the shader states.
++*/
++gceSTATUS
++gcLinkShaders(
++ IN gcSHADER VertexShader,
++ IN gcSHADER FragmentShader,
++ IN gceSHADER_FLAGS Flags,
++ OUT gctSIZE_T * StateBufferSize,
++ OUT gctPOINTER * StateBuffer,
++ OUT gcsHINT_PTR * Hints,
++ OUT gcMACHINECODE_PTR *ppVsMachineCode,
++ OUT gcMACHINECODE_PTR *ppFsMachineCode
++ );
++
++/*******************************************************************************
++** gcLoadShaders
++********************************************************************************
++**
++** Load a pre-compiled and pre-linked shader program into the hardware.
++**
++** INPUT:
++**
++** gcoHAL Hal
++** Pointer to a gcoHAL object.
++**
++** gctSIZE_T StateBufferSize
++** The number of bytes in the 'StateBuffer'.
++**
++** gctPOINTER StateBuffer
++** Pointer to the states that make up the shader program.
++**
++** gcsHINT_PTR Hints
++** Pointer to a gcsHINT structure that contains information required
++** when loading the shader states.
++*/
++gceSTATUS
++gcLoadShaders(
++ IN gcoHAL Hal,
++ IN gctSIZE_T StateBufferSize,
++ IN gctPOINTER StateBuffer,
++ IN gcsHINT_PTR Hints
++ );
++
++gceSTATUS
++gcRecompileShaders(
++ IN gcoHAL Hal,
++ IN gcMACHINECODE_PTR pVsMachineCode,
++ IN gcMACHINECODE_PTR pPsMachineCode,
++ /*Recompile variables*/
++ IN OUT gctPOINTER *ppRecompileStateBuffer,
++ IN OUT gctSIZE_T *pRecompileStateBufferSize,
++ IN OUT gcsHINT_PTR *ppRecompileHints,
++ /* natvie state*/
++ IN gctPOINTER pNativeStateBuffer,
++ IN gctSIZE_T nativeStateBufferSize,
++ IN gcsHINT_PTR pNativeHints,
++ /* npt info */
++ IN gctUINT32 Samplers,
++ IN gctUINT32 *SamplerWrapS,
++ IN gctUINT32 *SamplerWrapT
++ );
++
++gceSTATUS
++gcRecompileDepthBias(
++ IN gcoHAL Hal,
++ IN gcMACHINECODE_PTR pVsMachineCode,
++ /*Recompile variables*/
++ IN OUT gctPOINTER *ppRecompileStateBuffer,
++ IN OUT gctSIZE_T *pRecompileStateBufferSize,
++ IN OUT gcsHINT_PTR *ppRecompileHints,
++ /* natvie state*/
++ IN gctPOINTER pNativeStateBuffer,
++ IN gctSIZE_T nativeStateBufferSize,
++ IN gcsHINT_PTR pNativeHints,
++ OUT gctINT * uniformAddr,
++ OUT gctINT * uniformChannel
++ );
++
++/*******************************************************************************
++** gcSaveProgram
++********************************************************************************
++**
++** Save pre-compiled shaders and pre-linked programs to a binary file.
++**
++** INPUT:
++**
++** gcSHADER VertexShader
++** Pointer to vertex shader object.
++**
++** gcSHADER FragmentShader
++** Pointer to fragment shader object.
++**
++** gctSIZE_T ProgramBufferSize
++** Number of bytes in 'ProgramBuffer'.
++**
++** gctPOINTER ProgramBuffer
++** Pointer to buffer containing the program states.
++**
++** gcsHINT_PTR Hints
++** Pointer to HINTS structure for program states.
++**
++** OUTPUT:
++**
++** gctPOINTER * Binary
++** Pointer to a variable receiving the binary data to be saved.
++**
++** gctSIZE_T * BinarySize
++** Pointer to a variable receiving the number of bytes inside 'Binary'.
++*/
++gceSTATUS
++gcSaveProgram(
++ IN gcSHADER VertexShader,
++ IN gcSHADER FragmentShader,
++ IN gctSIZE_T ProgramBufferSize,
++ IN gctPOINTER ProgramBuffer,
++ IN gcsHINT_PTR Hints,
++ OUT gctPOINTER * Binary,
++ OUT gctSIZE_T * BinarySize
++ );
++
++/*******************************************************************************
++** gcLoadProgram
++********************************************************************************
++**
++** Load pre-compiled shaders and pre-linked programs from a binary file.
++**
++** INPUT:
++**
++** gctPOINTER Binary
++** Pointer to the binary data loaded.
++**
++** gctSIZE_T BinarySize
++** Number of bytes in 'Binary'.
++**
++** OUTPUT:
++**
++** gcSHADER VertexShader
++** Pointer to a vertex shader object.
++**
++** gcSHADER FragmentShader
++** Pointer to a fragment shader object.
++**
++** gctSIZE_T * ProgramBufferSize
++** Pointer to a variable receicing the number of bytes in the buffer
++** returned in 'ProgramBuffer'.
++**
++** gctPOINTER * ProgramBuffer
++** Pointer to a variable receiving a buffer pointer that contains the
++** states required to download the shaders into the hardware.
++**
++** gcsHINT_PTR * Hints
++** Pointer to a variable receiving a gcsHINT structure pointer that
++** contains information required when loading the shader states.
++*/
++gceSTATUS
++gcLoadProgram(
++ IN gctPOINTER Binary,
++ IN gctSIZE_T BinarySize,
++ OUT gcSHADER VertexShader,
++ OUT gcSHADER FragmentShader,
++ OUT gctSIZE_T * ProgramBufferSize,
++ OUT gctPOINTER * ProgramBuffer,
++ OUT gcsHINT_PTR * Hints
++ );
++
++/*******************************************************************************
++** gcCompileKernel
++********************************************************************************
++**
++** Compile a OpenCL kernel shader.
++**
++** INPUT:
++**
++** gcoOS Hal
++** Pointer to an gcoHAL object.
++**
++** gctSIZE_T SourceSize
++** Size of the source buffer in bytes.
++**
++** gctCONST_STRING Source
++** Pointer to the buffer containing the shader source code.
++**
++** OUTPUT:
++**
++** gcSHADER * Binary
++** Pointer to a variable receiving the pointer to a gcSHADER object
++** containg the compiled shader code.
++**
++** gctSTRING * Log
++** Pointer to a variable receiving a string pointer containging the
++** compile log.
++*/
++gceSTATUS
++gcCompileKernel(
++ IN gcoHAL Hal,
++ IN gctSIZE_T SourceSize,
++ IN gctCONST_STRING Source,
++ IN gctCONST_STRING Options,
++ OUT gcSHADER * Binary,
++ OUT gctSTRING * Log
++ );
++
++/*******************************************************************************
++** gcLinkKernel
++********************************************************************************
++**
++** Link OpenCL kernel and generate a harwdare specific state buffer by compiling
++** the compiler generated code through the resource allocator and code
++** generator.
++**
++** INPUT:
++**
++** gcSHADER Kernel
++** Pointer to a gcSHADER object holding information about the compiled
++** OpenCL kernel.
++**
++** gceSHADER_FLAGS Flags
++** Compiler flags. Can be any of the following:
++**
++** gcvSHADER_DEAD_CODE - Dead code elimination.
++** gcvSHADER_RESOURCE_USAGE - Resource usage optimizaion.
++** gcvSHADER_OPTIMIZER - Full optimization.
++** gcvSHADER_USE_GL_Z - Use OpenGL ES Z coordinate.
++** gcvSHADER_USE_GL_POSITION - Use OpenGL ES gl_Position.
++** gcvSHADER_USE_GL_FACE - Use OpenGL ES gl_FaceForward.
++**
++** OUTPUT:
++**
++** gctSIZE_T * StateBufferSize
++** Pointer to a variable receiving the number of bytes in the buffer
++** returned in 'StateBuffer'.
++**
++** gctPOINTER * StateBuffer
++** Pointer to a variable receiving a buffer pointer that contains the
++** states required to download the shaders into the hardware.
++**
++** gcsHINT_PTR * Hints
++** Pointer to a variable receiving a gcsHINT structure pointer that
++** contains information required when loading the shader states.
++*/
++gceSTATUS
++gcLinkKernel(
++ IN gcSHADER Kernel,
++ IN gceSHADER_FLAGS Flags,
++ OUT gctSIZE_T * StateBufferSize,
++ OUT gctPOINTER * StateBuffer,
++ OUT gcsHINT_PTR * Hints
++ );
++
++/*******************************************************************************
++** gcLoadKernel
++********************************************************************************
++**
++** Load a pre-compiled and pre-linked kernel program into the hardware.
++**
++** INPUT:
++**
++** gctSIZE_T StateBufferSize
++** The number of bytes in the 'StateBuffer'.
++**
++** gctPOINTER StateBuffer
++** Pointer to the states that make up the shader program.
++**
++** gcsHINT_PTR Hints
++** Pointer to a gcsHINT structure that contains information required
++** when loading the shader states.
++*/
++gceSTATUS
++gcLoadKernel(
++ IN gctSIZE_T StateBufferSize,
++ IN gctPOINTER StateBuffer,
++ IN gcsHINT_PTR Hints
++ );
++
++gceSTATUS
++gcInvokeThreadWalker(
++ IN gcsTHREAD_WALKER_INFO_PTR Info
++ );
++
++void
++gcTYPE_GetTypeInfo(
++ IN gcSHADER_TYPE Type,
++ OUT gctINT * Components,
++ OUT gctINT * Rows,
++ OUT gctCONST_STRING * Name
++ );
++
++gctBOOL
++gcOPT_doVaryingPackingForShader(
++ IN gcSHADER Shader
++ );
++
++gceSTATUS
++gcSHADER_PatchNPOTForMachineCode(
++ IN gcSHADER_KIND shaderType,
++ IN gcMACHINECODE_PTR pMachineCode,
++ IN gcNPOT_PATCH_PARAM_PTR pPatchParam,
++ IN gctUINT countOfPatchParam,
++ IN gctUINT hwSupportedInstCount,
++ OUT gctPOINTER* ppCmdBuffer,
++ OUT gctUINT32* pByteSizeOfCmdBuffer,
++ IN OUT gcsHINT_PTR pHints /* User needs copy original hints to this one, then passed this one in */
++ );
++
++gceSTATUS
++gcSHADER_PatchZBiasForMachineCodeVS(
++ IN gcMACHINECODE_PTR pMachineCode,
++ IN OUT gcZBIAS_PATCH_PARAM_PTR pPatchParam,
++ IN gctUINT hwSupportedInstCount,
++ OUT gctPOINTER* ppCmdBuffer,
++ OUT gctUINT32* pByteSizeOfCmdBuffer,
++ IN OUT gcsHINT_PTR pHints /* User needs copy original hints to this one, then passed this one in */
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* VIVANTE_NO_3D */
++#endif /* __gc_hal_compiler_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h 2014-05-15 20:33:58.610018275 +0200
+@@ -0,0 +1,1028 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_driver_h_
++#define __gc_hal_driver_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_driver_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* I/O Control Codes ******************************
++\******************************************************************************/
++
++#define gcvHAL_CLASS "galcore"
++#define IOCTL_GCHAL_INTERFACE 30000
++#define IOCTL_GCHAL_KERNEL_INTERFACE 30001
++#define IOCTL_GCHAL_TERMINATE 30002
++
++/******************************************************************************\
++********************************* Command Codes ********************************
++\******************************************************************************/
++
++typedef enum _gceHAL_COMMAND_CODES
++{
++ /* Generic query. */
++ gcvHAL_QUERY_VIDEO_MEMORY,
++ gcvHAL_QUERY_CHIP_IDENTITY,
++
++ /* Contiguous memory. */
++ gcvHAL_ALLOCATE_NON_PAGED_MEMORY,
++ gcvHAL_FREE_NON_PAGED_MEMORY,
++ gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY,
++ gcvHAL_FREE_CONTIGUOUS_MEMORY,
++
++ /* Video memory allocation. */
++ gcvHAL_ALLOCATE_VIDEO_MEMORY, /* Enforced alignment. */
++ gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY, /* No alignment. */
++ gcvHAL_FREE_VIDEO_MEMORY,
++
++ /* Physical-to-logical mapping. */
++ gcvHAL_MAP_MEMORY,
++ gcvHAL_UNMAP_MEMORY,
++
++ /* Logical-to-physical mapping. */
++ gcvHAL_MAP_USER_MEMORY,
++ gcvHAL_UNMAP_USER_MEMORY,
++
++ /* Surface lock/unlock. */
++ gcvHAL_LOCK_VIDEO_MEMORY,
++ gcvHAL_UNLOCK_VIDEO_MEMORY,
++
++ /* Event queue. */
++ gcvHAL_EVENT_COMMIT,
++
++ gcvHAL_USER_SIGNAL,
++ gcvHAL_SIGNAL,
++ gcvHAL_WRITE_DATA,
++
++ gcvHAL_COMMIT,
++ gcvHAL_STALL,
++
++ gcvHAL_READ_REGISTER,
++ gcvHAL_WRITE_REGISTER,
++
++ gcvHAL_GET_PROFILE_SETTING,
++ gcvHAL_SET_PROFILE_SETTING,
++
++ gcvHAL_READ_ALL_PROFILE_REGISTERS,
++ gcvHAL_PROFILE_REGISTERS_2D,
++#if VIVANTE_PROFILER_PERDRAW
++ gcvHAL_READ_PROFILER_REGISTER_SETTING,
++#endif
++
++ /* Power management. */
++ gcvHAL_SET_POWER_MANAGEMENT_STATE,
++ gcvHAL_QUERY_POWER_MANAGEMENT_STATE,
++
++ gcvHAL_GET_BASE_ADDRESS,
++
++ gcvHAL_SET_IDLE, /* reserved */
++
++ /* Queries. */
++ gcvHAL_QUERY_KERNEL_SETTINGS,
++
++ /* Reset. */
++ gcvHAL_RESET,
++
++ /* Map physical address into handle. */
++ gcvHAL_MAP_PHYSICAL,
++
++ /* Debugger stuff. */
++ gcvHAL_DEBUG,
++
++ /* Cache stuff. */
++ gcvHAL_CACHE,
++
++ /* TimeStamp */
++ gcvHAL_TIMESTAMP,
++
++ /* Database. */
++ gcvHAL_DATABASE,
++
++ /* Version. */
++ gcvHAL_VERSION,
++
++ /* Chip info */
++ gcvHAL_CHIP_INFO,
++
++ /* Process attaching/detaching. */
++ gcvHAL_ATTACH,
++ gcvHAL_DETACH,
++
++ /* Composition. */
++ gcvHAL_COMPOSE,
++
++ /* Set timeOut value */
++ gcvHAL_SET_TIMEOUT,
++
++ /* Frame database. */
++ gcvHAL_GET_FRAME_INFO,
++
++ /* Shared info for each process */
++ gcvHAL_GET_SHARED_INFO,
++ gcvHAL_SET_SHARED_INFO,
++ gcvHAL_QUERY_COMMAND_BUFFER,
++
++ gcvHAL_COMMIT_DONE,
++
++ /* GPU and event dump */
++ gcvHAL_DUMP_GPU_STATE,
++ gcvHAL_DUMP_EVENT,
++
++ /* Virtual command buffer. */
++ gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER,
++ gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER,
++
++ /* FSCALE_VAL. */
++ gcvHAL_SET_FSCALE_VALUE,
++ gcvHAL_GET_FSCALE_VALUE,
++
++ /* Reset time stamp. */
++ gcvHAL_QUERY_RESET_TIME_STAMP,
++
++ /* Sync point operations. */
++ gcvHAL_SYNC_POINT,
++
++ /* Create native fence and return its fd. */
++ gcvHAL_CREATE_NATIVE_FENCE,
++}
++gceHAL_COMMAND_CODES;
++
++/******************************************************************************\
++****************************** Interface Structure *****************************
++\******************************************************************************/
++
++#define gcdMAX_PROFILE_FILE_NAME 128
++
++/* Kernel settings. */
++typedef struct _gcsKERNEL_SETTINGS
++{
++ /* Used RealTime signal between kernel and user. */
++ gctINT signal;
++}
++gcsKERNEL_SETTINGS;
++
++
++/* gcvHAL_QUERY_CHIP_IDENTITY */
++typedef struct _gcsHAL_QUERY_CHIP_IDENTITY * gcsHAL_QUERY_CHIP_IDENTITY_PTR;
++typedef struct _gcsHAL_QUERY_CHIP_IDENTITY
++{
++
++ /* Chip model. */
++ gceCHIPMODEL chipModel;
++
++ /* Revision value.*/
++ gctUINT32 chipRevision;
++
++ /* Supported feature fields. */
++ gctUINT32 chipFeatures;
++
++ /* Supported minor feature fields. */
++ gctUINT32 chipMinorFeatures;
++
++ /* Supported minor feature 1 fields. */
++ gctUINT32 chipMinorFeatures1;
++
++ /* Supported minor feature 2 fields. */
++ gctUINT32 chipMinorFeatures2;
++
++ /* Supported minor feature 3 fields. */
++ gctUINT32 chipMinorFeatures3;
++
++ /* Supported minor feature 4 fields. */
++ gctUINT32 chipMinorFeatures4;
++
++ /* Number of streams supported. */
++ gctUINT32 streamCount;
++
++ /* Total number of temporary registers per thread. */
++ gctUINT32 registerMax;
++
++ /* Maximum number of threads. */
++ gctUINT32 threadCount;
++
++ /* Number of shader cores. */
++ gctUINT32 shaderCoreCount;
++
++ /* Size of the vertex cache. */
++ gctUINT32 vertexCacheSize;
++
++ /* Number of entries in the vertex output buffer. */
++ gctUINT32 vertexOutputBufferSize;
++
++ /* Number of pixel pipes. */
++ gctUINT32 pixelPipes;
++
++ /* Number of instructions. */
++ gctUINT32 instructionCount;
++
++ /* Number of constants. */
++ gctUINT32 numConstants;
++
++ /* Buffer size */
++ gctUINT32 bufferSize;
++
++ /* Number of varyings */
++ gctUINT32 varyingsCount;
++
++ /* Supertile layout style in hardware */
++ gctUINT32 superTileMode;
++}
++gcsHAL_QUERY_CHIP_IDENTITY;
++
++/* gcvHAL_COMPOSE. */
++typedef struct _gcsHAL_COMPOSE * gcsHAL_COMPOSE_PTR;
++typedef struct _gcsHAL_COMPOSE
++{
++ /* Composition state buffer. */
++ gctUINT64 physical;
++ gctUINT64 logical;
++ gctUINT offset;
++ gctUINT size;
++
++ /* Composition end signal. */
++ gctUINT64 process;
++ gctUINT64 signal;
++
++ /* User signals. */
++ gctUINT64 userProcess;
++ gctUINT64 userSignal1;
++ gctUINT64 userSignal2;
++
++#if defined(__QNXNTO__)
++ /* Client pulse side-channel connection ID. */
++ gctINT32 coid;
++
++ /* Set by server. */
++ gctINT32 rcvid;
++#endif
++}
++gcsHAL_COMPOSE;
++
++
++typedef struct _gcsHAL_INTERFACE
++{
++ /* Command code. */
++ gceHAL_COMMAND_CODES command;
++
++ /* Hardware type. */
++ gceHARDWARE_TYPE hardwareType;
++
++ /* Status value. */
++ gceSTATUS status;
++
++ /* Handle to this interface channel. */
++ gctUINT64 handle;
++
++ /* Pid of the client. */
++ gctUINT32 pid;
++
++ /* Union of command structures. */
++ union _u
++ {
++ /* gcvHAL_GET_BASE_ADDRESS */
++ struct _gcsHAL_GET_BASE_ADDRESS
++ {
++ /* Physical memory address of internal memory. */
++ OUT gctUINT32 baseAddress;
++ }
++ GetBaseAddress;
++
++ /* gcvHAL_QUERY_VIDEO_MEMORY */
++ struct _gcsHAL_QUERY_VIDEO_MEMORY
++ {
++ /* Physical memory address of internal memory. Just a name. */
++ OUT gctUINT32 internalPhysical;
++
++ /* Size in bytes of internal memory. */
++ OUT gctUINT64 internalSize;
++
++ /* Physical memory address of external memory. Just a name. */
++ OUT gctUINT32 externalPhysical;
++
++ /* Size in bytes of external memory.*/
++ OUT gctUINT64 externalSize;
++
++ /* Physical memory address of contiguous memory. Just a name. */
++ OUT gctUINT32 contiguousPhysical;
++
++ /* Size in bytes of contiguous memory.*/
++ OUT gctUINT64 contiguousSize;
++ }
++ QueryVideoMemory;
++
++ /* gcvHAL_QUERY_CHIP_IDENTITY */
++ gcsHAL_QUERY_CHIP_IDENTITY QueryChipIdentity;
++
++ /* gcvHAL_MAP_MEMORY */
++ struct _gcsHAL_MAP_MEMORY
++ {
++ /* Physical memory address to map. Just a name on Linux/Qnx. */
++ IN gctUINT32 physical;
++
++ /* Number of bytes in physical memory to map. */
++ IN gctUINT64 bytes;
++
++ /* Address of mapped memory. */
++ OUT gctUINT64 logical;
++ }
++ MapMemory;
++
++ /* gcvHAL_UNMAP_MEMORY */
++ struct _gcsHAL_UNMAP_MEMORY
++ {
++ /* Physical memory address to unmap. Just a name on Linux/Qnx. */
++ IN gctUINT32 physical;
++
++ /* Number of bytes in physical memory to unmap. */
++ IN gctUINT64 bytes;
++
++ /* Address of mapped memory to unmap. */
++ IN gctUINT64 logical;
++ }
++ UnmapMemory;
++
++ /* gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY */
++ struct _gcsHAL_ALLOCATE_LINEAR_VIDEO_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT bytes;
++
++ /* Buffer alignment. */
++ IN gctUINT alignment;
++
++ /* Type of allocation. */
++ IN gceSURF_TYPE type;
++
++ /* Memory pool to allocate from. */
++ IN OUT gcePOOL pool;
++
++ /* Allocated video memory in gcuVIDMEM_NODE. */
++ OUT gctUINT64 node;
++ }
++ AllocateLinearVideoMemory;
++
++ /* gcvHAL_ALLOCATE_VIDEO_MEMORY */
++ struct _gcsHAL_ALLOCATE_VIDEO_MEMORY
++ {
++ /* Width of rectangle to allocate. */
++ IN OUT gctUINT width;
++
++ /* Height of rectangle to allocate. */
++ IN OUT gctUINT height;
++
++ /* Depth of rectangle to allocate. */
++ IN gctUINT depth;
++
++ /* Format rectangle to allocate in gceSURF_FORMAT. */
++ IN gceSURF_FORMAT format;
++
++ /* Type of allocation. */
++ IN gceSURF_TYPE type;
++
++ /* Memory pool to allocate from. */
++ IN OUT gcePOOL pool;
++
++ /* Allocated video memory in gcuVIDMEM_NODE. */
++ OUT gctUINT64 node;
++ }
++ AllocateVideoMemory;
++
++ /* gcvHAL_FREE_VIDEO_MEMORY */
++ struct _gcsHAL_FREE_VIDEO_MEMORY
++ {
++ /* Allocated video memory in gcuVIDMEM_NODE. */
++ IN gctUINT64 node;
++
++#ifdef __QNXNTO__
++/* TODO: This is part of the unlock - why is it here? */
++ /* Mapped logical address to unmap in user space. */
++ OUT gctUINT64 memory;
++
++ /* Number of bytes to allocated. */
++ OUT gctUINT64 bytes;
++#endif
++ }
++ FreeVideoMemory;
++
++ /* gcvHAL_LOCK_VIDEO_MEMORY */
++ struct _gcsHAL_LOCK_VIDEO_MEMORY
++ {
++ /* Allocated video memory gcuVIDMEM_NODE gcuVIDMEM_NODE. */
++ IN gctUINT64 node;
++
++ /* Cache configuration. */
++ /* Only gcvPOOL_CONTIGUOUS and gcvPOOL_VIRUTAL
++ ** can be configured */
++ IN gctBOOL cacheable;
++
++ /* Hardware specific address. */
++ OUT gctUINT32 address;
++
++ /* Mapped logical address. */
++ OUT gctUINT64 memory;
++ }
++ LockVideoMemory;
++
++ /* gcvHAL_UNLOCK_VIDEO_MEMORY */
++ struct _gcsHAL_UNLOCK_VIDEO_MEMORY
++ {
++ /* Allocated video memory in gcuVIDMEM_NODE. */
++ IN gctUINT64 node;
++
++ /* Type of surface. */
++ IN gceSURF_TYPE type;
++
++ /* Flag to unlock surface asynchroneously. */
++ IN OUT gctBOOL asynchroneous;
++ }
++ UnlockVideoMemory;
++
++ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
++ struct _gcsHAL_ALLOCATE_NON_PAGED_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateNonPagedMemory;
++
++ /* gcvHAL_FREE_NON_PAGED_MEMORY */
++ struct _gcsHAL_FREE_NON_PAGED_MEMORY
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeNonPagedMemory;
++
++ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
++ struct _gcsHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateVirtualCommandBuffer;
++
++ /* gcvHAL_FREE_NON_PAGED_MEMORY */
++ struct _gcsHAL_FREE_VIRTUAL_COMMAND_BUFFER
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeVirtualCommandBuffer;
++
++ /* gcvHAL_EVENT_COMMIT. */
++ struct _gcsHAL_EVENT_COMMIT
++ {
++ /* Event queue in gcsQUEUE. */
++ IN gctUINT64 queue;
++ }
++ Event;
++
++ /* gcvHAL_COMMIT */
++ struct _gcsHAL_COMMIT
++ {
++ /* Context buffer object gckCONTEXT. */
++ IN gctUINT64 context;
++
++ /* Command buffer gcoCMDBUF. */
++ IN gctUINT64 commandBuffer;
++
++ /* State delta buffer in gcsSTATE_DELTA. */
++ gctUINT64 delta;
++
++ /* Event queue in gcsQUEUE. */
++ IN gctUINT64 queue;
++ }
++ Commit;
++
++ /* gcvHAL_MAP_USER_MEMORY */
++ struct _gcsHAL_MAP_USER_MEMORY
++ {
++ /* Base address of user memory to map. */
++ IN gctUINT64 memory;
++
++ /* Physical address of user memory to map. */
++ IN gctUINT32 physical;
++
++ /* Size of user memory in bytes to map. */
++ IN gctUINT64 size;
++
++ /* Info record required by gcvHAL_UNMAP_USER_MEMORY. Just a name. */
++ OUT gctUINT32 info;
++
++ /* Physical address of mapped memory. */
++ OUT gctUINT32 address;
++ }
++ MapUserMemory;
++
++ /* gcvHAL_UNMAP_USER_MEMORY */
++ struct _gcsHAL_UNMAP_USER_MEMORY
++ {
++ /* Base address of user memory to unmap. */
++ IN gctUINT64 memory;
++
++ /* Size of user memory in bytes to unmap. */
++ IN gctUINT64 size;
++
++ /* Info record returned by gcvHAL_MAP_USER_MEMORY. Just a name. */
++ IN gctUINT32 info;
++
++ /* Physical address of mapped memory as returned by
++ gcvHAL_MAP_USER_MEMORY. */
++ IN gctUINT32 address;
++ }
++ UnmapUserMemory;
++#if !USE_NEW_LINUX_SIGNAL
++ /* gcsHAL_USER_SIGNAL */
++ struct _gcsHAL_USER_SIGNAL
++ {
++ /* Command. */
++ gceUSER_SIGNAL_COMMAND_CODES command;
++
++ /* Signal ID. */
++ IN OUT gctINT id;
++
++ /* Reset mode. */
++ IN gctBOOL manualReset;
++
++ /* Wait timedout. */
++ IN gctUINT32 wait;
++
++ /* State. */
++ IN gctBOOL state;
++ }
++ UserSignal;
++#endif
++
++ /* gcvHAL_SIGNAL. */
++ struct _gcsHAL_SIGNAL
++ {
++ /* Signal handle to signal gctSIGNAL. */
++ IN gctUINT64 signal;
++
++ /* Reserved gctSIGNAL. */
++ IN gctUINT64 auxSignal;
++
++ /* Process owning the signal gctHANDLE. */
++ IN gctUINT64 process;
++
++#if defined(__QNXNTO__)
++ /* Client pulse side-channel connection ID. Set by client in gcoOS_CreateSignal. */
++ IN gctINT32 coid;
++
++ /* Set by server. */
++ IN gctINT32 rcvid;
++#endif
++ /* Event generated from where of pipeline */
++ IN gceKERNEL_WHERE fromWhere;
++ }
++ Signal;
++
++ /* gcvHAL_WRITE_DATA. */
++ struct _gcsHAL_WRITE_DATA
++ {
++ /* Address to write data to. */
++ IN gctUINT32 address;
++
++ /* Data to write. */
++ IN gctUINT32 data;
++ }
++ WriteData;
++
++ /* gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY */
++ struct _gcsHAL_ALLOCATE_CONTIGUOUS_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Hardware address of allocation. */
++ OUT gctUINT32 address;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateContiguousMemory;
++
++ /* gcvHAL_FREE_CONTIGUOUS_MEMORY */
++ struct _gcsHAL_FREE_CONTIGUOUS_MEMORY
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeContiguousMemory;
++
++ /* gcvHAL_READ_REGISTER */
++ struct _gcsHAL_READ_REGISTER
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ /* Data read. */
++ OUT gctUINT32 data;
++ }
++ ReadRegisterData;
++
++ /* gcvHAL_WRITE_REGISTER */
++ struct _gcsHAL_WRITE_REGISTER
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ /* Data read. */
++ IN gctUINT32 data;
++ }
++ WriteRegisterData;
++
++#if VIVANTE_PROFILER
++ /* gcvHAL_GET_PROFILE_SETTING */
++ struct _gcsHAL_GET_PROFILE_SETTING
++ {
++ /* Enable profiling */
++ OUT gctBOOL enable;
++
++ /* The profile file name */
++ OUT gctCHAR fileName[gcdMAX_PROFILE_FILE_NAME];
++ }
++ GetProfileSetting;
++
++ /* gcvHAL_SET_PROFILE_SETTING */
++ struct _gcsHAL_SET_PROFILE_SETTING
++ {
++ /* Enable profiling */
++ IN gctBOOL enable;
++
++ /* The profile file name */
++ IN gctCHAR fileName[gcdMAX_PROFILE_FILE_NAME];
++ }
++ SetProfileSetting;
++
++#if VIVANTE_PROFILER_PERDRAW
++ /* gcvHAL_READ_PROFILER_REGISTER_SETTING */
++ struct _gcsHAL_READ_PROFILER_REGISTER_SETTING
++ {
++ /*Should Clear Register*/
++ IN gctBOOL bclear;
++ }
++ SetProfilerRegisterClear;
++#endif
++
++ /* gcvHAL_READ_ALL_PROFILE_REGISTERS */
++ struct _gcsHAL_READ_ALL_PROFILE_REGISTERS
++ {
++#if VIVANTE_PROFILER_CONTEXT
++ /* Context buffer object gckCONTEXT. Just a name. */
++ IN gctUINT32 context;
++#endif
++ /* Data read. */
++ OUT gcsPROFILER_COUNTERS counters;
++ }
++ RegisterProfileData;
++
++ /* gcvHAL_PROFILE_REGISTERS_2D */
++ struct _gcsHAL_PROFILE_REGISTERS_2D
++ {
++ /* Data read in gcs2D_PROFILE. */
++ OUT gctUINT64 hwProfile2D;
++ }
++ RegisterProfileData2D;
++#endif
++ /* Power management. */
++ /* gcvHAL_SET_POWER_MANAGEMENT_STATE */
++ struct _gcsHAL_SET_POWER_MANAGEMENT
++ {
++ /* Data read. */
++ IN gceCHIPPOWERSTATE state;
++ }
++ SetPowerManagement;
++
++ /* gcvHAL_QUERY_POWER_MANAGEMENT_STATE */
++ struct _gcsHAL_QUERY_POWER_MANAGEMENT
++ {
++ /* Data read. */
++ OUT gceCHIPPOWERSTATE state;
++
++ /* Idle query. */
++ OUT gctBOOL isIdle;
++ }
++ QueryPowerManagement;
++
++ /* gcvHAL_QUERY_KERNEL_SETTINGS */
++ struct _gcsHAL_QUERY_KERNEL_SETTINGS
++ {
++ /* Settings.*/
++ OUT gcsKERNEL_SETTINGS settings;
++ }
++ QueryKernelSettings;
++
++ /* gcvHAL_MAP_PHYSICAL */
++ struct _gcsHAL_MAP_PHYSICAL
++ {
++ /* gcvTRUE to map, gcvFALSE to unmap. */
++ IN gctBOOL map;
++
++ /* Physical address. */
++ IN OUT gctUINT64 physical;
++ }
++ MapPhysical;
++
++ /* gcvHAL_DEBUG */
++ struct _gcsHAL_DEBUG
++ {
++ /* If gcvTRUE, set the debug information. */
++ IN gctBOOL set;
++ IN gctUINT32 level;
++ IN gctUINT32 zones;
++ IN gctBOOL enable;
++
++ IN gceDEBUG_MESSAGE_TYPE type;
++ IN gctUINT32 messageSize;
++
++ /* Message to print if not empty. */
++ IN gctCHAR message[80];
++ }
++ Debug;
++
++ /* gcvHAL_CACHE */
++ struct _gcsHAL_CACHE
++ {
++ IN gceCACHEOPERATION operation;
++ /* gctHANDLE */
++ IN gctUINT64 process;
++ IN gctUINT64 logical;
++ IN gctUINT64 bytes;
++ /* gcuVIDMEM_NODE_PTR */
++ IN gctUINT64 node;
++ }
++ Cache;
++
++ /* gcvHAL_TIMESTAMP */
++ struct _gcsHAL_TIMESTAMP
++ {
++ /* Timer select. */
++ IN gctUINT32 timer;
++
++ /* Timer request type (0-stop, 1-start, 2-send delta). */
++ IN gctUINT32 request;
++
++ /* Result of delta time in microseconds. */
++ OUT gctINT32 timeDelta;
++ }
++ TimeStamp;
++
++ /* gcvHAL_DATABASE */
++ struct _gcsHAL_DATABASE
++ {
++ /* Set to gcvTRUE if you want to query a particular process ID.
++ ** Set to gcvFALSE to query the last detached process. */
++ IN gctBOOL validProcessID;
++
++ /* Process ID to query. */
++ IN gctUINT32 processID;
++
++ /* Information. */
++ OUT gcuDATABASE_INFO vidMem;
++ OUT gcuDATABASE_INFO nonPaged;
++ OUT gcuDATABASE_INFO contiguous;
++ OUT gcuDATABASE_INFO gpuIdle;
++ }
++ Database;
++
++ /* gcvHAL_VERSION */
++ struct _gcsHAL_VERSION
++ {
++ /* Major version: N.n.n. */
++ OUT gctINT32 major;
++
++ /* Minor version: n.N.n. */
++ OUT gctINT32 minor;
++
++ /* Patch version: n.n.N. */
++ OUT gctINT32 patch;
++
++ /* Build version. */
++ OUT gctUINT32 build;
++ }
++ Version;
++
++ /* gcvHAL_CHIP_INFO */
++ struct _gcsHAL_CHIP_INFO
++ {
++ /* Chip count. */
++ OUT gctINT32 count;
++
++ /* Chip types. */
++ OUT gceHARDWARE_TYPE types[gcdCHIP_COUNT];
++ }
++ ChipInfo;
++
++ /* gcvHAL_ATTACH */
++ struct _gcsHAL_ATTACH
++ {
++ /* Context buffer object gckCONTEXT. Just a name. */
++ OUT gctUINT32 context;
++
++ /* Number of states in the buffer. */
++ OUT gctUINT64 stateCount;
++ }
++ Attach;
++
++ /* gcvHAL_DETACH */
++ struct _gcsHAL_DETACH
++ {
++ /* Context buffer object gckCONTEXT. Just a name. */
++ IN gctUINT32 context;
++ }
++ Detach;
++
++ /* gcvHAL_COMPOSE. */
++ gcsHAL_COMPOSE Compose;
++
++ /* gcvHAL_GET_FRAME_INFO. */
++ struct _gcsHAL_GET_FRAME_INFO
++ {
++ /* gcsHAL_FRAME_INFO* */
++ OUT gctUINT64 frameInfo;
++ }
++ GetFrameInfo;
++
++ /* gcvHAL_SET_TIME_OUT. */
++ struct _gcsHAL_SET_TIMEOUT
++ {
++ gctUINT32 timeOut;
++ }
++ SetTimeOut;
++
++#if gcdENABLE_VG
++ /* gcvHAL_COMMIT */
++ struct _gcsHAL_VGCOMMIT
++ {
++ /* Context buffer in gcsVGCONTEXT. */
++ IN gctUINT64 context;
++
++ /* Command queue in gcsVGCMDQUEUE. */
++ IN gctUINT64 queue;
++
++ /* Number of entries in the queue. */
++ IN gctUINT entryCount;
++
++ /* Task table in gcsTASK_MASTER_TABLE. */
++ IN gctUINT64 taskTable;
++ }
++ VGCommit;
++
++ /* gcvHAL_QUERY_COMMAND_BUFFER */
++ struct _gcsHAL_QUERY_COMMAND_BUFFER
++ {
++ /* Command buffer attributes. */
++ OUT gcsCOMMAND_BUFFER_INFO information;
++ }
++ QueryCommandBuffer;
++
++#endif
++
++ struct _gcsHAL_GET_SHARED_INFO
++ {
++ /* Process id. */
++ IN gctUINT32 pid;
++
++ /* Data id. */
++ IN gctUINT32 dataId;
++
++ /* Data size. */
++ IN gctSIZE_T bytes;
++
++ /* Pointer to save the shared data. */
++ OUT gctPOINTER data;
++ }
++ GetSharedInfo;
++
++ struct _gcsHAL_SET_SHARED_INFO
++ {
++ /* Data id. */
++ IN gctUINT32 dataId;
++
++ /* Data to be shared. */
++ IN gctPOINTER data;
++
++ /* Data size. */
++ IN gctSIZE_T bytes;
++ }
++ SetSharedInfo;
++
++ struct _gcsHAL_SET_FSCALE_VALUE
++ {
++ IN gctUINT value;
++ }
++ SetFscaleValue;
++
++ struct _gcsHAL_GET_FSCALE_VALUE
++ {
++ OUT gctUINT value;
++ OUT gctUINT minValue;
++ OUT gctUINT maxValue;
++ }
++ GetFscaleValue;
++
++ struct _gcsHAL_QUERY_RESET_TIME_STAMP
++ {
++ OUT gctUINT64 timeStamp;
++ }
++ QueryResetTimeStamp;
++
++ struct _gcsHAL_SYNC_POINT
++ {
++ /* Command. */
++ gceSYNC_POINT_COMMAND_CODES command;
++
++ /* Sync point. */
++ IN OUT gctUINT64 syncPoint;
++
++ /* From where. */
++ IN gceKERNEL_WHERE fromWhere;
++
++ /* Signaled state. */
++ OUT gctBOOL state;
++ }
++ SyncPoint;
++
++ struct _gcsHAL_CREATE_NATIVE_FENCE
++ {
++ /* Signal id to dup. */
++ IN gctUINT64 syncPoint;
++
++ /* Native fence file descriptor. */
++ OUT gctINT fenceFD;
++
++ }
++ CreateNativeFence;
++ }
++ u;
++}
++gcsHAL_INTERFACE;
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_driver_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h 2014-05-15 20:33:58.610018275 +0200
+@@ -0,0 +1,270 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_driver_vg_h_
++#define __gc_hal_driver_vg_h_
++
++
++
++#include "gc_hal_types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* I/O Control Codes ******************************
++\******************************************************************************/
++
++#define gcvHAL_CLASS "galcore"
++#define IOCTL_GCHAL_INTERFACE 30000
++
++/******************************************************************************\
++********************************* Command Codes ********************************
++\******************************************************************************/
++
++/******************************************************************************\
++********************* Command buffer information structure. ********************
++\******************************************************************************/
++
++typedef struct _gcsCOMMAND_BUFFER_INFO * gcsCOMMAND_BUFFER_INFO_PTR;
++typedef struct _gcsCOMMAND_BUFFER_INFO
++{
++ /* FE command buffer interrupt ID. */
++ gctINT32 feBufferInt;
++
++ /* TS overflow interrupt ID. */
++ gctINT32 tsOverflowInt;
++
++ /* Alignment and mask for the buffer address. */
++ gctUINT addressMask;
++ gctSIZE_T addressAlignment;
++
++ /* Alignment for each command. */
++ gctSIZE_T commandAlignment;
++
++ /* Number of bytes required by the STATE command. */
++ gctSIZE_T stateCommandSize;
++
++ /* Number of bytes required by the RESTART command. */
++ gctSIZE_T restartCommandSize;
++
++ /* Number of bytes required by the FETCH command. */
++ gctSIZE_T fetchCommandSize;
++
++ /* Number of bytes required by the CALL command. */
++ gctSIZE_T callCommandSize;
++
++ /* Number of bytes required by the RETURN command. */
++ gctSIZE_T returnCommandSize;
++
++ /* Number of bytes required by the EVENT command. */
++ gctSIZE_T eventCommandSize;
++
++ /* Number of bytes required by the END command. */
++ gctSIZE_T endCommandSize;
++
++ /* Number of bytes reserved at the tail of a static command buffer. */
++ gctSIZE_T staticTailSize;
++
++ /* Number of bytes reserved at the tail of a dynamic command buffer. */
++ gctSIZE_T dynamicTailSize;
++}
++gcsCOMMAND_BUFFER_INFO;
++
++/******************************************************************************\
++******************************** Task Structures *******************************
++\******************************************************************************/
++
++typedef enum _gceTASK
++{
++ gcvTASK_LINK,
++ gcvTASK_CLUSTER,
++ gcvTASK_INCREMENT,
++ gcvTASK_DECREMENT,
++ gcvTASK_SIGNAL,
++ gcvTASK_LOCKDOWN,
++ gcvTASK_UNLOCK_VIDEO_MEMORY,
++ gcvTASK_FREE_VIDEO_MEMORY,
++ gcvTASK_FREE_CONTIGUOUS_MEMORY,
++ gcvTASK_UNMAP_USER_MEMORY
++}
++gceTASK;
++
++typedef struct _gcsTASK_HEADER * gcsTASK_HEADER_PTR;
++typedef struct _gcsTASK_HEADER
++{
++ /* Task ID. */
++ IN gceTASK id;
++}
++gcsTASK_HEADER;
++
++typedef struct _gcsTASK_LINK * gcsTASK_LINK_PTR;
++typedef struct _gcsTASK_LINK
++{
++ /* Task ID (gcvTASK_LINK). */
++ IN gceTASK id;
++
++ /* Pointer to the next task container. */
++ IN gctPOINTER cotainer;
++
++ /* Pointer to the next task from the next task container. */
++ IN gcsTASK_HEADER_PTR task;
++}
++gcsTASK_LINK;
++
++typedef struct _gcsTASK_CLUSTER * gcsTASK_CLUSTER_PTR;
++typedef struct _gcsTASK_CLUSTER
++{
++ /* Task ID (gcvTASK_CLUSTER). */
++ IN gceTASK id;
++
++ /* Number of tasks in the cluster. */
++ IN gctUINT taskCount;
++}
++gcsTASK_CLUSTER;
++
++typedef struct _gcsTASK_INCREMENT * gcsTASK_INCREMENT_PTR;
++typedef struct _gcsTASK_INCREMENT
++{
++ /* Task ID (gcvTASK_INCREMENT). */
++ IN gceTASK id;
++
++ /* Address of the variable to increment. */
++ IN gctUINT32 address;
++}
++gcsTASK_INCREMENT;
++
++typedef struct _gcsTASK_DECREMENT * gcsTASK_DECREMENT_PTR;
++typedef struct _gcsTASK_DECREMENT
++{
++ /* Task ID (gcvTASK_DECREMENT). */
++ IN gceTASK id;
++
++ /* Address of the variable to decrement. */
++ IN gctUINT32 address;
++}
++gcsTASK_DECREMENT;
++
++typedef struct _gcsTASK_SIGNAL * gcsTASK_SIGNAL_PTR;
++typedef struct _gcsTASK_SIGNAL
++{
++ /* Task ID (gcvTASK_SIGNAL). */
++ IN gceTASK id;
++
++ /* Process owning the signal. */
++ IN gctHANDLE process;
++
++ /* Signal handle to signal. */
++ IN gctSIGNAL signal;
++
++#if defined(__QNXNTO__)
++ IN gctINT32 coid;
++ IN gctINT32 rcvid;
++#endif
++}
++gcsTASK_SIGNAL;
++
++typedef struct _gcsTASK_LOCKDOWN * gcsTASK_LOCKDOWN_PTR;
++typedef struct _gcsTASK_LOCKDOWN
++{
++ /* Task ID (gcvTASK_LOCKDOWN). */
++ IN gceTASK id;
++
++ /* Address of the user space counter. */
++ IN gctUINT32 userCounter;
++
++ /* Address of the kernel space counter. */
++ IN gctUINT32 kernelCounter;
++
++ /* Process owning the signal. */
++ IN gctHANDLE process;
++
++ /* Signal handle to signal. */
++ IN gctSIGNAL signal;
++}
++gcsTASK_LOCKDOWN;
++
++typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY * gcsTASK_UNLOCK_VIDEO_MEMORY_PTR;
++typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY
++{
++ /* Task ID (gcvTASK_UNLOCK_VIDEO_MEMORY). */
++ IN gceTASK id;
++
++ /* Allocated video memory. */
++ IN gctUINT64 node;
++}
++gcsTASK_UNLOCK_VIDEO_MEMORY;
++
++typedef struct _gcsTASK_FREE_VIDEO_MEMORY * gcsTASK_FREE_VIDEO_MEMORY_PTR;
++typedef struct _gcsTASK_FREE_VIDEO_MEMORY
++{
++ /* Task ID (gcvTASK_FREE_VIDEO_MEMORY). */
++ IN gceTASK id;
++
++ /* Allocated video memory. */
++ IN gctUINT64 node;
++}
++gcsTASK_FREE_VIDEO_MEMORY;
++
++typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY * gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR;
++typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY
++{
++ /* Task ID (gcvTASK_FREE_CONTIGUOUS_MEMORY). */
++ IN gceTASK id;
++
++ /* Number of bytes allocated. */
++ IN gctSIZE_T bytes;
++
++ /* Physical address of allocation. */
++ IN gctPHYS_ADDR physical;
++
++ /* Logical address of allocation. */
++ IN gctPOINTER logical;
++}
++gcsTASK_FREE_CONTIGUOUS_MEMORY;
++
++typedef struct _gcsTASK_UNMAP_USER_MEMORY * gcsTASK_UNMAP_USER_MEMORY_PTR;
++typedef struct _gcsTASK_UNMAP_USER_MEMORY
++{
++ /* Task ID (gcvTASK_UNMAP_USER_MEMORY). */
++ IN gceTASK id;
++
++ /* Base address of user memory to unmap. */
++ IN gctPOINTER memory;
++
++ /* Size of user memory in bytes to unmap. */
++ IN gctSIZE_T size;
++
++ /* Info record returned by gcvHAL_MAP_USER_MEMORY. */
++ IN gctPOINTER info;
++
++ /* Physical address of mapped memory as returned by
++ gcvHAL_MAP_USER_MEMORY. */
++ IN gctUINT32 address;
++}
++gcsTASK_UNMAP_USER_MEMORY;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_driver_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h 2014-05-15 20:33:58.610018275 +0200
+@@ -0,0 +1,88 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_dump_h_
++#define __gc_hal_dump_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++** FILE LAYOUT:
++**
++** gcsDUMP_FILE structure
++**
++** gcsDUMP_DATA frame
++** gcsDUMP_DATA or gcDUMP_DATA_SIZE records rendingring the frame
++** gctUINT8 data[length]
++*/
++
++#define gcvDUMP_FILE_SIGNATURE gcmCC('g','c','D','B')
++
++typedef struct _gcsDUMP_FILE
++{
++ gctUINT32 signature; /* File signature */
++ gctSIZE_T length; /* Length of file */
++ gctUINT32 frames; /* Number of frames in file */
++}
++gcsDUMP_FILE;
++
++typedef enum _gceDUMP_TAG
++{
++ gcvTAG_SURFACE = gcmCC('s','u','r','f'),
++ gcvTAG_FRAME = gcmCC('f','r','m',' '),
++ gcvTAG_COMMAND = gcmCC('c','m','d',' '),
++ gcvTAG_INDEX = gcmCC('i','n','d','x'),
++ gcvTAG_STREAM = gcmCC('s','t','r','m'),
++ gcvTAG_TEXTURE = gcmCC('t','e','x','t'),
++ gcvTAG_RENDER_TARGET = gcmCC('r','n','d','r'),
++ gcvTAG_DEPTH = gcmCC('z','b','u','f'),
++ gcvTAG_RESOLVE = gcmCC('r','s','l','v'),
++ gcvTAG_DELETE = gcmCC('d','e','l',' '),
++}
++gceDUMP_TAG;
++
++typedef struct _gcsDUMP_SURFACE
++{
++ gceDUMP_TAG type; /* Type of record. */
++ gctUINT32 address; /* Address of the surface. */
++ gctINT16 width; /* Width of surface. */
++ gctINT16 height; /* Height of surface. */
++ gceSURF_FORMAT format; /* Surface pixel format. */
++ gctSIZE_T length; /* Number of bytes inside the surface. */
++}
++gcsDUMP_SURFACE;
++
++typedef struct _gcsDUMP_DATA
++{
++ gceDUMP_TAG type; /* Type of record. */
++ gctSIZE_T length; /* Number of bytes of data. */
++ gctUINT32 address; /* Address for the data. */
++}
++gcsDUMP_DATA;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_dump_h_ */
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h 2014-05-15 20:33:58.610018275 +0200
+@@ -0,0 +1,617 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_eglplatform_h_
++#define __gc_hal_eglplatform_h_
++
++/* Include VDK types. */
++#include "gc_hal_types.h"
++#include "gc_hal_base.h"
++#include "gc_hal_eglplatform_type.h"
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#if defined(_WIN32) || defined(__VC32__) && !defined(__CYGWIN__) && !defined(__SCITECH_SNAP__)
++/* Win32 and Windows CE platforms. */
++#include <windows.h>
++typedef HDC HALNativeDisplayType;
++typedef HWND HALNativeWindowType;
++typedef HBITMAP HALNativePixmapType;
++
++typedef struct __BITFIELDINFO{
++ BITMAPINFO bmi;
++ RGBQUAD bmiColors[2];
++} BITFIELDINFO;
++
++#elif defined(LINUX) && defined(EGL_API_DFB) && !defined(__APPLE__)
++#include <directfb.h>
++typedef struct _DFBDisplay * HALNativeDisplayType;
++typedef IDirectFBWindow * HALNativeWindowType;
++typedef struct _DFBPixmap * HALNativePixmapType;
++
++#elif defined(LINUX) && defined(EGL_API_FB) && !defined(__APPLE__)
++
++#if defined(EGL_API_WL)
++/* Wayland platform. */
++#include "wayland-server.h"
++#include <wayland-egl.h>
++
++#define WL_EGL_NUM_BACKBUFFERS 2
++
++typedef struct _gcsWL_VIV_BUFFER
++{
++ struct wl_buffer wl_buffer;
++ gcoSURF surface;
++} gcsWL_VIV_BUFFER;
++
++typedef struct _gcsWL_EGL_DISPLAY
++{
++ struct wl_display* wl_display;
++ struct wl_viv* wl_viv;
++} gcsWL_EGL_DISPLAY;
++
++typedef struct _gcsWL_EGL_BUFFER_INFO
++{
++ gctINT32 width;
++ gctINT32 height;
++ gctINT32 stride;
++ gceSURF_FORMAT format;
++ gcuVIDMEM_NODE_PTR node;
++ gcePOOL pool;
++ gctUINT bytes;
++ gcoSURF surface;
++} gcsWL_EGL_BUFFER_INFO;
++
++typedef struct _gcsWL_EGL_BUFFER
++{
++ struct wl_buffer* wl_buffer;
++ gcsWL_EGL_BUFFER_INFO info;
++} gcsWL_EGL_BUFFER;
++
++typedef struct _gcsWL_EGL_WINDOW_INFO
++{
++ gctUINT width;
++ gctUINT height;
++ gceSURF_FORMAT format;
++ gctUINT bpp;
++} gcsWL_EGL_WINDOW_INFO;
++
++struct wl_egl_window
++{
++ gcsWL_EGL_BUFFER backbuffers[WL_EGL_NUM_BACKBUFFERS];
++ gcsWL_EGL_WINDOW_INFO info;
++ gctUINT current;
++ struct wl_surface* surface;
++ struct wl_callback* pending;
++};
++
++typedef void* HALNativeDisplayType;
++typedef void* HALNativeWindowType;
++typedef void* HALNativePixmapType;
++#else
++/* Linux platform for FBDEV. */
++typedef struct _FBDisplay * HALNativeDisplayType;
++typedef struct _FBWindow * HALNativeWindowType;
++typedef struct _FBPixmap * HALNativePixmapType;
++#endif
++#elif defined(__ANDROID__) || defined(ANDROID)
++
++struct egl_native_pixmap_t;
++
++#if ANDROID_SDK_VERSION >= 9
++ #include <android/native_window.h>
++
++ typedef struct ANativeWindow* HALNativeWindowType;
++ typedef struct egl_native_pixmap_t* HALNativePixmapType;
++ typedef void* HALNativeDisplayType;
++#else
++ struct android_native_window_t;
++ typedef struct android_native_window_t* HALNativeWindowType;
++ typedef struct egl_native_pixmap_t * HALNativePixmapType;
++ typedef void* HALNativeDisplayType;
++#endif
++
++#elif defined(LINUX) || defined(__APPLE__)
++/* X11 platform. */
++#include <X11/Xlib.h>
++#include <X11/Xutil.h>
++
++typedef Display * HALNativeDisplayType;
++typedef Window HALNativeWindowType;
++
++#ifdef CUSTOM_PIXMAP
++typedef void * HALNativePixmapType;
++#else
++typedef Pixmap HALNativePixmapType;
++#endif /* CUSTOM_PIXMAP */
++
++/* Rename some badly named X defines. */
++#ifdef Status
++# define XStatus int
++# undef Status
++#endif
++#ifdef Always
++# define XAlways 2
++# undef Always
++#endif
++#ifdef CurrentTime
++# undef CurrentTime
++# define XCurrentTime 0
++#endif
++
++#elif defined(__QNXNTO__)
++#include <screen/screen.h>
++
++/* VOID */
++typedef int HALNativeDisplayType;
++typedef screen_window_t HALNativeWindowType;
++typedef screen_pixmap_t HALNativePixmapType;
++
++#else
++
++#error "Platform not recognized"
++
++/* VOID */
++typedef void * HALNativeDisplayType;
++typedef void * HALNativeWindowType;
++typedef void * HALNativePixmapType;
++
++#endif
++
++/* define DUMMY according to the system */
++#if defined(EGL_API_WL)
++# define WL_DUMMY (31415926)
++# define EGL_DUMMY WL_DUMMY
++#elif defined(__ANDROID__) || defined(ANDROID)
++# define ANDROID_DUMMY (31415926)
++# define EGL_DUMMY ANDROID_DUMMY
++#else
++# define EGL_DUMMY (31415926)
++#endif
++
++/*******************************************************************************
++** Display. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_GetDisplay(
++ OUT HALNativeDisplayType * Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_GetDisplayByIndex(
++ IN gctINT DisplayIndex,
++ OUT HALNativeDisplayType * Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_GetDisplayInfo(
++ IN HALNativeDisplayType Display,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctSIZE_T * Physical,
++ OUT gctINT * Stride,
++ OUT gctINT * BitsPerPixel
++ );
++
++
++
++gceSTATUS
++gcoOS_GetDisplayInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetNextDisplayInfoExByIndex(
++ IN gctINT Index,
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetDisplayVirtual(
++ IN HALNativeDisplayType Display,
++ OUT gctINT * Width,
++ OUT gctINT * Height
++ );
++
++gceSTATUS
++gcoOS_GetDisplayBackbuffer(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctPOINTER * context,
++ OUT gcoSURF * surface,
++ OUT gctUINT * Offset,
++ OUT gctINT * X,
++ OUT gctINT * Y
++ );
++
++gceSTATUS
++gcoOS_SetDisplayVirtual(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT Offset,
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++gceSTATUS
++gcoOS_SetDisplayVirtualEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER Context,
++ IN gcoSURF Surface,
++ IN gctUINT Offset,
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++gceSTATUS
++gcoOS_SetSwapInterval(
++ IN HALNativeDisplayType Display,
++ IN gctINT Interval
++);
++
++gceSTATUS
++gcoOS_GetSwapInterval(
++ IN HALNativeDisplayType Display,
++ IN gctINT_PTR Min,
++ IN gctINT_PTR Max
++);
++
++gceSTATUS
++gcoOS_DisplayBufferRegions(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT NumRects,
++ IN gctINT_PTR Rects
++ );
++
++gceSTATUS
++gcoOS_DestroyDisplay(
++ IN HALNativeDisplayType Display
++ );
++
++gceSTATUS
++gcoOS_InitLocalDisplayInfo(
++ IN HALNativeDisplayType Display,
++ IN OUT gctPOINTER * localDisplay
++ );
++
++gceSTATUS
++gcoOS_DeinitLocalDisplayInfo(
++ IN HALNativeDisplayType Display,
++ IN OUT gctPOINTER * localDisplay
++ );
++
++gceSTATUS
++gcoOS_GetDisplayInfoEx2(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER localDisplay,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetDisplayBackbufferEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER localDisplay,
++ OUT gctPOINTER * context,
++ OUT gcoSURF * surface,
++ OUT gctUINT * Offset,
++ OUT gctINT * X,
++ OUT gctINT * Y
++ );
++
++gceSTATUS
++gcoOS_IsValidDisplay(
++ IN HALNativeDisplayType Display
++ );
++
++gceSTATUS
++gcoOS_GetNativeVisualId(
++ IN HALNativeDisplayType Display,
++ OUT gctINT* nativeVisualId
++ );
++
++gctBOOL
++gcoOS_SynchronousFlip(
++ IN HALNativeDisplayType Display
++ );
++
++/*******************************************************************************
++** Windows. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_CreateWindow(
++ IN HALNativeDisplayType Display,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gctINT Width,
++ IN gctINT Height,
++ OUT HALNativeWindowType * Window
++ );
++
++gceSTATUS
++gcoOS_GetWindowInfo(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctINT * X,
++ OUT gctINT * Y,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctUINT * Offset
++ );
++
++gceSTATUS
++gcoOS_DestroyWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_DrawImage(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits
++ );
++
++gceSTATUS
++gcoOS_GetImage(
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ OUT gctINT * BitsPerPixel,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_GetWindowInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctINT * X,
++ OUT gctINT * Y,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctUINT * Offset,
++ OUT gceSURF_FORMAT * Format
++ );
++
++gceSTATUS
++gcoOS_DrawImageEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits,
++ IN gceSURF_FORMAT Format
++ );
++
++/*******************************************************************************
++** Pixmaps. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_CreatePixmap(
++ IN HALNativeDisplayType Display,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ OUT HALNativePixmapType * Pixmap
++ );
++
++gceSTATUS
++gcoOS_GetPixmapInfo(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_DrawPixmap(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits
++ );
++
++gceSTATUS
++gcoOS_DestroyPixmap(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap
++ );
++
++gceSTATUS
++gcoOS_GetPixmapInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits,
++ OUT gceSURF_FORMAT * Format
++ );
++
++gceSTATUS
++gcoOS_CopyPixmapBits(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ IN gctUINT DstWidth,
++ IN gctUINT DstHeight,
++ IN gctINT DstStride,
++ IN gceSURF_FORMAT DstFormat,
++ OUT gctPOINTER DstBits
++ );
++
++/*******************************************************************************
++** OS relative. ****************************************************************
++*/
++gceSTATUS
++gcoOS_LoadEGLLibrary(
++ OUT gctHANDLE * Handle
++ );
++
++gceSTATUS
++gcoOS_FreeEGLLibrary(
++ IN gctHANDLE Handle
++ );
++
++gceSTATUS
++gcoOS_ShowWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_HideWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_SetWindowTitle(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctCONST_STRING Title
++ );
++
++gceSTATUS
++gcoOS_CapturePointer(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_GetEvent(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT halEvent * Event
++ );
++
++gceSTATUS
++gcoOS_CreateClientBuffer(
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT Format,
++ IN gctINT Type,
++ OUT gctPOINTER * ClientBuffer
++ );
++
++gceSTATUS
++gcoOS_GetClientBufferInfo(
++ IN gctPOINTER ClientBuffer,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_DestroyClientBuffer(
++ IN gctPOINTER ClientBuffer
++ );
++
++gceSTATUS
++gcoOS_DestroyContext(
++ IN gctPOINTER Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_CreateContext(
++ IN gctPOINTER LocalDisplay,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_MakeCurrent(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType DrawDrawable,
++ IN HALNativeWindowType ReadDrawable,
++ IN gctPOINTER Context,
++ IN gcoSURF ResolveTarget
++ );
++
++gceSTATUS
++gcoOS_CreateDrawable(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable
++ );
++
++gceSTATUS
++gcoOS_DestroyDrawable(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable
++ );
++gceSTATUS
++gcoOS_SwapBuffers(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable,
++ IN gcoSURF RenderTarget,
++ IN gcoSURF ResolveTarget,
++ IN gctPOINTER ResolveBits,
++ OUT gctUINT *Width,
++ OUT gctUINT *Height
++ );
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_eglplatform_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h 2014-05-15 20:33:58.634018448 +0200
+@@ -0,0 +1,286 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_eglplatform_type_h_
++#define __gc_hal_eglplatform_type_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*******************************************************************************
++** Events. *********************************************************************
++*/
++
++typedef enum _halEventType
++{
++ /* Keyboard event. */
++ HAL_KEYBOARD,
++
++ /* Mouse move event. */
++ HAL_POINTER,
++
++ /* Mouse button event. */
++ HAL_BUTTON,
++
++ /* Application close event. */
++ HAL_CLOSE,
++
++ /* Application window has been updated. */
++ HAL_WINDOW_UPDATE
++}
++halEventType;
++
++/* Scancodes for keyboard. */
++typedef enum _halKeys
++{
++ HAL_UNKNOWN = -1,
++
++ HAL_BACKSPACE = 0x08,
++ HAL_TAB,
++ HAL_ENTER = 0x0D,
++ HAL_ESCAPE = 0x1B,
++
++ HAL_SPACE = 0x20,
++ HAL_SINGLEQUOTE = 0x27,
++ HAL_PAD_ASTERISK = 0x2A,
++ HAL_COMMA = 0x2C,
++ HAL_HYPHEN,
++ HAL_PERIOD,
++ HAL_SLASH,
++ HAL_0,
++ HAL_1,
++ HAL_2,
++ HAL_3,
++ HAL_4,
++ HAL_5,
++ HAL_6,
++ HAL_7,
++ HAL_8,
++ HAL_9,
++ HAL_SEMICOLON = 0x3B,
++ HAL_EQUAL = 0x3D,
++ HAL_A = 0x41,
++ HAL_B,
++ HAL_C,
++ HAL_D,
++ HAL_E,
++ HAL_F,
++ HAL_G,
++ HAL_H,
++ HAL_I,
++ HAL_J,
++ HAL_K,
++ HAL_L,
++ HAL_M,
++ HAL_N,
++ HAL_O,
++ HAL_P,
++ HAL_Q,
++ HAL_R,
++ HAL_S,
++ HAL_T,
++ HAL_U,
++ HAL_V,
++ HAL_W,
++ HAL_X,
++ HAL_Y,
++ HAL_Z,
++ HAL_LBRACKET,
++ HAL_BACKSLASH,
++ HAL_RBRACKET,
++ HAL_BACKQUOTE = 0x60,
++
++ HAL_F1 = 0x80,
++ HAL_F2,
++ HAL_F3,
++ HAL_F4,
++ HAL_F5,
++ HAL_F6,
++ HAL_F7,
++ HAL_F8,
++ HAL_F9,
++ HAL_F10,
++ HAL_F11,
++ HAL_F12,
++
++ HAL_LCTRL,
++ HAL_RCTRL,
++ HAL_LSHIFT,
++ HAL_RSHIFT,
++ HAL_LALT,
++ HAL_RALT,
++ HAL_CAPSLOCK,
++ HAL_NUMLOCK,
++ HAL_SCROLLLOCK,
++ HAL_PAD_0,
++ HAL_PAD_1,
++ HAL_PAD_2,
++ HAL_PAD_3,
++ HAL_PAD_4,
++ HAL_PAD_5,
++ HAL_PAD_6,
++ HAL_PAD_7,
++ HAL_PAD_8,
++ HAL_PAD_9,
++ HAL_PAD_HYPHEN,
++ HAL_PAD_PLUS,
++ HAL_PAD_SLASH,
++ HAL_PAD_PERIOD,
++ HAL_PAD_ENTER,
++ HAL_SYSRQ,
++ HAL_PRNTSCRN,
++ HAL_BREAK,
++ HAL_UP,
++ HAL_LEFT,
++ HAL_RIGHT,
++ HAL_DOWN,
++ HAL_HOME,
++ HAL_END,
++ HAL_PGUP,
++ HAL_PGDN,
++ HAL_INSERT,
++ HAL_DELETE,
++ HAL_LWINDOW,
++ HAL_RWINDOW,
++ HAL_MENU,
++ HAL_POWER,
++ HAL_SLEEP,
++ HAL_WAKE
++}
++halKeys;
++
++/* Structure that defined keyboard mapping. */
++typedef struct _halKeyMap
++{
++ /* Normal key. */
++ halKeys normal;
++
++ /* Extended key. */
++ halKeys extended;
++}
++halKeyMap;
++
++/* Event structure. */
++typedef struct _halEvent
++{
++ /* Event type. */
++ halEventType type;
++
++ /* Event data union. */
++ union _halEventData
++ {
++ /* Event data for keyboard. */
++ struct _halKeyboard
++ {
++ /* Scancode. */
++ halKeys scancode;
++
++ /* ASCII characte of the key pressed. */
++ char key;
++
++ /* Flag whether the key was pressed (1) or released (0). */
++ char pressed;
++ }
++ keyboard;
++
++ /* Event data for pointer. */
++ struct _halPointer
++ {
++ /* Current pointer coordinate. */
++ int x;
++ int y;
++ }
++ pointer;
++
++ /* Event data for mouse buttons. */
++ struct _halButton
++ {
++ /* Left button state. */
++ int left;
++
++ /* Middle button state. */
++ int middle;
++
++ /* Right button state. */
++ int right;
++
++ /* Current pointer coordinate. */
++ int x;
++ int y;
++ }
++ button;
++ }
++ data;
++}
++halEvent;
++
++/* VFK_DISPLAY_INFO structure defining information returned by
++ vdkGetDisplayInfoEx. */
++typedef struct _halDISPLAY_INFO
++{
++ /* The size of the display in pixels. */
++ int width;
++ int height;
++
++ /* The stride of the dispay. -1 is returned if the stride is not known
++ ** for the specified display.*/
++ int stride;
++
++ /* The color depth of the display in bits per pixel. */
++ int bitsPerPixel;
++
++ /* The logical pointer to the display memory buffer. NULL is returned
++ ** if the pointer is not known for the specified display. */
++ void * logical;
++
++ /* The physical address of the display memory buffer. ~0 is returned
++ ** if the address is not known for the specified display. */
++ unsigned long physical;
++
++ int wrapFB; /* true if compositor, false otherwise. */
++
++#ifndef __QNXNTO__
++ /* 355_FB_MULTI_BUFFER */
++ int multiBuffer;
++ int backBufferY;
++#endif
++
++ /* The color info of the display. */
++ unsigned int alphaLength;
++ unsigned int alphaOffset;
++ unsigned int redLength;
++ unsigned int redOffset;
++ unsigned int greenLength;
++ unsigned int greenOffset;
++ unsigned int blueLength;
++ unsigned int blueOffset;
++
++ /* Display flip support. */
++ int flip;
++}
++halDISPLAY_INFO;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_eglplatform_type_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h 2014-05-15 20:33:58.634018448 +0200
+@@ -0,0 +1,2053 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_engine_h_
++#define __gc_hal_engine_h_
++
++#ifndef VIVANTE_NO_3D
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_engine_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gcoSTREAM * gcoSTREAM;
++typedef struct _gcoVERTEX * gcoVERTEX;
++typedef struct _gcoTEXTURE * gcoTEXTURE;
++typedef struct _gcoINDEX * gcoINDEX;
++typedef struct _gcsVERTEX_ATTRIBUTES * gcsVERTEX_ATTRIBUTES_PTR;
++typedef struct _gcoVERTEXARRAY * gcoVERTEXARRAY;
++
++#define gcdATTRIBUTE_COUNT 16
++
++/******************************************************************************\
++********************************* Enumerations *********************************
++\******************************************************************************/
++
++/* Shading format. */
++typedef enum _gceSHADING
++{
++ gcvSHADING_SMOOTH,
++ gcvSHADING_FLAT_D3D,
++ gcvSHADING_FLAT_OPENGL,
++}
++gceSHADING;
++
++/* Culling modes. */
++typedef enum _gceCULL
++{
++ gcvCULL_NONE,
++ gcvCULL_CCW,
++ gcvCULL_CW,
++}
++gceCULL;
++
++/* Fill modes. */
++typedef enum _gceFILL
++{
++ gcvFILL_POINT,
++ gcvFILL_WIRE_FRAME,
++ gcvFILL_SOLID,
++}
++gceFILL;
++
++/* Compare modes. */
++typedef enum _gceCOMPARE
++{
++ gcvCOMPARE_NEVER,
++ gcvCOMPARE_NOT_EQUAL,
++ gcvCOMPARE_LESS,
++ gcvCOMPARE_LESS_OR_EQUAL,
++ gcvCOMPARE_EQUAL,
++ gcvCOMPARE_GREATER,
++ gcvCOMPARE_GREATER_OR_EQUAL,
++ gcvCOMPARE_ALWAYS,
++ gcvCOMPARE_INVALID = -1
++}
++gceCOMPARE;
++
++/* Stencil modes. */
++typedef enum _gceSTENCIL_MODE
++{
++ gcvSTENCIL_NONE,
++ gcvSTENCIL_SINGLE_SIDED,
++ gcvSTENCIL_DOUBLE_SIDED,
++}
++gceSTENCIL_MODE;
++
++/* Stencil operations. */
++typedef enum _gceSTENCIL_OPERATION
++{
++ gcvSTENCIL_KEEP,
++ gcvSTENCIL_REPLACE,
++ gcvSTENCIL_ZERO,
++ gcvSTENCIL_INVERT,
++ gcvSTENCIL_INCREMENT,
++ gcvSTENCIL_DECREMENT,
++ gcvSTENCIL_INCREMENT_SATURATE,
++ gcvSTENCIL_DECREMENT_SATURATE,
++ gcvSTENCIL_OPERATION_INVALID = -1
++}
++gceSTENCIL_OPERATION;
++
++/* Stencil selection. */
++typedef enum _gceSTENCIL_WHERE
++{
++ gcvSTENCIL_FRONT,
++ gcvSTENCIL_BACK,
++}
++gceSTENCIL_WHERE;
++
++/* Texture addressing selection. */
++typedef enum _gceTEXTURE_WHICH
++{
++ gcvTEXTURE_S,
++ gcvTEXTURE_T,
++ gcvTEXTURE_R,
++}
++gceTEXTURE_WHICH;
++
++/* Texture addressing modes. */
++typedef enum _gceTEXTURE_ADDRESSING
++{
++ gcvTEXTURE_WRAP,
++ gcvTEXTURE_CLAMP,
++ gcvTEXTURE_BORDER,
++ gcvTEXTURE_MIRROR,
++ gcvTEXTURE_MIRROR_ONCE,
++}
++gceTEXTURE_ADDRESSING;
++
++/* Texture filters. */
++typedef enum _gceTEXTURE_FILTER
++{
++ gcvTEXTURE_NONE,
++ gcvTEXTURE_POINT,
++ gcvTEXTURE_LINEAR,
++ gcvTEXTURE_ANISOTROPIC,
++}
++gceTEXTURE_FILTER;
++
++/* Primitive types. */
++typedef enum _gcePRIMITIVE
++{
++ gcvPRIMITIVE_POINT_LIST,
++ gcvPRIMITIVE_LINE_LIST,
++ gcvPRIMITIVE_LINE_STRIP,
++ gcvPRIMITIVE_LINE_LOOP,
++ gcvPRIMITIVE_TRIANGLE_LIST,
++ gcvPRIMITIVE_TRIANGLE_STRIP,
++ gcvPRIMITIVE_TRIANGLE_FAN,
++ gcvPRIMITIVE_RECTANGLE,
++}
++gcePRIMITIVE;
++
++/* Index types. */
++typedef enum _gceINDEX_TYPE
++{
++ gcvINDEX_8,
++ gcvINDEX_16,
++ gcvINDEX_32,
++}
++gceINDEX_TYPE;
++
++/******************************************************************************\
++********************************* gcoHAL Object *********************************
++\******************************************************************************/
++
++/* Query the target capabilities. */
++gceSTATUS
++gcoHAL_QueryTargetCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MultiTargetCount,
++ OUT gctUINT * MaxSamples
++ );
++
++gceSTATUS
++gcoHAL_SetDepthOnly(
++ IN gcoHAL Hal,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoHAL_QueryShaderCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctUINT * Varyings
++ );
++
++gceSTATUS
++gcoHAL_QueryTextureCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MaxDepth,
++ OUT gctBOOL * Cubic,
++ OUT gctBOOL * NonPowerOfTwo,
++ OUT gctUINT * VertexSamplers,
++ OUT gctUINT * PixelSamplers
++ );
++
++gceSTATUS
++gcoHAL_QueryTextureMaxAniso(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxAnisoValue
++ );
++
++gceSTATUS
++gcoHAL_QueryStreamCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT32 * MaxAttributes,
++ OUT gctUINT32 * MaxStreamSize,
++ OUT gctUINT32 * NumberOfStreams,
++ OUT gctUINT32 * Alignment
++ );
++
++/******************************************************************************\
++********************************* gcoSURF Object ********************************
++\******************************************************************************/
++
++/*----------------------------------------------------------------------------*/
++/*--------------------------------- gcoSURF 3D --------------------------------*/
++
++/* Copy surface. */
++gceSTATUS
++gcoSURF_Copy(
++ IN gcoSURF Surface,
++ IN gcoSURF Source
++ );
++
++/* Clear surface. */
++gceSTATUS
++gcoSURF_Clear(
++ IN gcoSURF Surface,
++ IN gctUINT Flags
++ );
++
++/* Set number of samples for a gcoSURF object. */
++gceSTATUS
++gcoSURF_SetSamples(
++ IN gcoSURF Surface,
++ IN gctUINT Samples
++ );
++
++/* Get the number of samples per pixel. */
++gceSTATUS
++gcoSURF_GetSamples(
++ IN gcoSURF Surface,
++ OUT gctUINT_PTR Samples
++ );
++
++/* Clear rectangular surface. */
++gceSTATUS
++gcoSURF_ClearRect(
++ IN gcoSURF Surface,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctUINT Flags
++ );
++
++/* TO BE REMOVED */
++ gceSTATUS
++ depr_gcoSURF_Resolve(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 DestAddress,
++ IN gctPOINTER DestBits,
++ IN gctINT DestStride,
++ IN gceSURF_TYPE DestType,
++ IN gceSURF_FORMAT DestFormat,
++ IN gctUINT DestWidth,
++ IN gctUINT DestHeight
++ );
++
++ gceSTATUS
++ depr_gcoSURF_ResolveRect(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 DestAddress,
++ IN gctPOINTER DestBits,
++ IN gctINT DestStride,
++ IN gceSURF_TYPE DestType,
++ IN gceSURF_FORMAT DestFormat,
++ IN gctUINT DestWidth,
++ IN gctUINT DestHeight,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Resample surface. */
++gceSTATUS
++gcoSURF_Resample(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface
++ );
++
++/* Resolve surface. */
++gceSTATUS
++gcoSURF_Resolve(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface
++ );
++
++gceSTATUS
++gcoSURF_IsHWResolveable(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Resolve rectangular area of a surface. */
++gceSTATUS
++gcoSURF_ResolveRect(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Set surface resolvability. */
++gceSTATUS
++gcoSURF_SetResolvability(
++ IN gcoSURF Surface,
++ IN gctBOOL Resolvable
++ );
++
++gceSTATUS
++gcoSURF_IsRenderable(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSURF_IsFormatRenderableAsRT(
++ IN gcoSURF Surface
++ );
++
++#if gcdSYNC
++gceSTATUS
++gcoSURF_GetFence(
++ IN gcoSURF Surface
++ );
++gceSTATUS
++gcoSURF_WaitFence(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSTREAM_GetFence(
++ IN gcoSTREAM stream
++ );
++
++gceSTATUS
++gcoSTREAM_WaitFence(
++ IN gcoSTREAM stream
++ );
++
++gceSTATUS
++gcoINDEX_GetFence(
++ IN gcoINDEX index
++ );
++
++gceSTATUS
++gcoINDEX_WaitFence(
++ IN gcoINDEX index
++ );
++#endif
++
++/******************************************************************************\
++******************************** gcoINDEX Object *******************************
++\******************************************************************************/
++
++/* Construct a new gcoINDEX object. */
++gceSTATUS
++gcoINDEX_Construct(
++ IN gcoHAL Hal,
++ OUT gcoINDEX * Index
++ );
++
++/* Destroy a gcoINDEX object. */
++gceSTATUS
++gcoINDEX_Destroy(
++ IN gcoINDEX Index
++ );
++
++/* Lock index in memory. */
++gceSTATUS
++gcoINDEX_Lock(
++ IN gcoINDEX Index,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Unlock index that was previously locked with gcoINDEX_Lock. */
++gceSTATUS
++gcoINDEX_Unlock(
++ IN gcoINDEX Index
++ );
++
++/* Upload index data into the memory. */
++gceSTATUS
++gcoINDEX_Load(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE IndexType,
++ IN gctUINT32 IndexCount,
++ IN gctPOINTER IndexBuffer
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoINDEX_Bind(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoINDEX_BindOffset(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset
++ );
++
++/* Free existing index buffer. */
++gceSTATUS
++gcoINDEX_Free(
++ IN gcoINDEX Index
++ );
++
++/* Upload data into an index buffer. */
++gceSTATUS
++gcoINDEX_Upload(
++ IN gcoINDEX Index,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Bytes
++ );
++
++/* Upload data into an index buffer starting at an offset. */
++gceSTATUS
++gcoINDEX_UploadOffset(
++ IN gcoINDEX Index,
++ IN gctUINT32 Offset,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Bytes
++ );
++
++/*Merge index2 to index1 from 0, index2 must subset of inex1*/
++gceSTATUS
++gcoINDEX_Merge(
++ IN gcoINDEX Index1,
++ IN gcoINDEX Index2
++ );
++
++/*check if index buffer is enough for this draw*/
++gctBOOL
++gcoINDEX_CheckRange(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctINT Count,
++ IN gctUINT32 Indices
++ );
++
++/* Query the index capabilities. */
++gceSTATUS
++gcoINDEX_QueryCaps(
++ OUT gctBOOL * Index8,
++ OUT gctBOOL * Index16,
++ OUT gctBOOL * Index32,
++ OUT gctUINT * MaxIndex
++ );
++
++/* Determine the index range in the current index buffer. */
++gceSTATUS
++gcoINDEX_GetIndexRange(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Count,
++ OUT gctUINT32 * MinimumIndex,
++ OUT gctUINT32 * MaximumIndex
++ );
++
++/* Dynamic buffer management. */
++gceSTATUS
++gcoINDEX_SetDynamic(
++ IN gcoINDEX Index,
++ IN gctSIZE_T Bytes,
++ IN gctUINT Buffers
++ );
++
++gceSTATUS
++gcoINDEX_UploadDynamic(
++ IN gcoINDEX Index,
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Bytes
++ );
++
++/******************************************************************************\
++********************************** gco3D Object *********************************
++\******************************************************************************/
++
++/* Clear flags. */
++typedef enum _gceCLEAR
++{
++ gcvCLEAR_COLOR = 0x1,
++ gcvCLEAR_DEPTH = 0x2,
++ gcvCLEAR_STENCIL = 0x4,
++ gcvCLEAR_HZ = 0x8,
++ gcvCLEAR_HAS_VAA = 0x10,
++}
++gceCLEAR;
++
++/* Blending targets. */
++typedef enum _gceBLEND_UNIT
++{
++ gcvBLEND_SOURCE,
++ gcvBLEND_TARGET,
++}
++gceBLEND_UNIT;
++
++/* Construct a new gco3D object. */
++gceSTATUS
++gco3D_Construct(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++
++/* Destroy an gco3D object. */
++gceSTATUS
++gco3D_Destroy(
++ IN gco3D Engine
++ );
++
++/* Set 3D API type. */
++gceSTATUS
++gco3D_SetAPI(
++ IN gco3D Engine,
++ IN gceAPI ApiType
++ );
++
++/* Set render target. */
++gceSTATUS
++gco3D_SetTarget(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Unset render target. */
++gceSTATUS
++gco3D_UnsetTarget(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Set depth buffer. */
++gceSTATUS
++gco3D_SetDepth(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Unset depth buffer. */
++gceSTATUS
++gco3D_UnsetDepth(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Set viewport. */
++gceSTATUS
++gco3D_SetViewport(
++ IN gco3D Engine,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Set scissors. */
++gceSTATUS
++gco3D_SetScissors(
++ IN gco3D Engine,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Set clear color. */
++gceSTATUS
++gco3D_SetClearColor(
++ IN gco3D Engine,
++ IN gctUINT8 Red,
++ IN gctUINT8 Green,
++ IN gctUINT8 Blue,
++ IN gctUINT8 Alpha
++ );
++
++/* Set fixed point clear color. */
++gceSTATUS
++gco3D_SetClearColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++/* Set floating point clear color. */
++gceSTATUS
++gco3D_SetClearColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Set fixed point clear depth. */
++gceSTATUS
++gco3D_SetClearDepthX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Depth
++ );
++
++/* Set floating point clear depth. */
++gceSTATUS
++gco3D_SetClearDepthF(
++ IN gco3D Engine,
++ IN gctFLOAT Depth
++ );
++
++/* Set clear stencil. */
++gceSTATUS
++gco3D_SetClearStencil(
++ IN gco3D Engine,
++ IN gctUINT32 Stencil
++ );
++
++/* Clear a Rect sub-surface. */
++gceSTATUS
++gco3D_ClearRect(
++ IN gco3D Engine,
++ IN gctUINT32 Address,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom,
++ IN gctUINT32 Width,
++ IN gctUINT32 Height,
++ IN gctUINT32 Flags
++ );
++
++/* Clear surface. */
++gceSTATUS
++gco3D_Clear(
++ IN gco3D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT32 Width,
++ IN gctUINT32 Height,
++ IN gctUINT32 Flags
++ );
++
++
++/* Clear tile status. */
++gceSTATUS
++gco3D_ClearTileStatus(
++ IN gco3D Engine,
++ IN gcsSURF_INFO_PTR Surface,
++ IN gctUINT32 TileStatusAddress,
++ IN gctUINT32 Flags
++ );
++
++/* Set shading mode. */
++gceSTATUS
++gco3D_SetShading(
++ IN gco3D Engine,
++ IN gceSHADING Shading
++ );
++
++/* Set blending mode. */
++gceSTATUS
++gco3D_EnableBlending(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set blending function. */
++gceSTATUS
++gco3D_SetBlendFunction(
++ IN gco3D Engine,
++ IN gceBLEND_UNIT Unit,
++ IN gceBLEND_FUNCTION FunctionRGB,
++ IN gceBLEND_FUNCTION FunctionAlpha
++ );
++
++/* Set blending mode. */
++gceSTATUS
++gco3D_SetBlendMode(
++ IN gco3D Engine,
++ IN gceBLEND_MODE ModeRGB,
++ IN gceBLEND_MODE ModeAlpha
++ );
++
++/* Set blending color. */
++gceSTATUS
++gco3D_SetBlendColor(
++ IN gco3D Engine,
++ IN gctUINT Red,
++ IN gctUINT Green,
++ IN gctUINT Blue,
++ IN gctUINT Alpha
++ );
++
++/* Set fixed point blending color. */
++gceSTATUS
++gco3D_SetBlendColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++/* Set floating point blending color. */
++gceSTATUS
++gco3D_SetBlendColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Set culling mode. */
++gceSTATUS
++gco3D_SetCulling(
++ IN gco3D Engine,
++ IN gceCULL Mode
++ );
++
++/* Enable point size */
++gceSTATUS
++gco3D_SetPointSizeEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set point sprite */
++gceSTATUS
++gco3D_SetPointSprite(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set fill mode. */
++gceSTATUS
++gco3D_SetFill(
++ IN gco3D Engine,
++ IN gceFILL Mode
++ );
++
++/* Set depth compare mode. */
++gceSTATUS
++gco3D_SetDepthCompare(
++ IN gco3D Engine,
++ IN gceCOMPARE Compare
++ );
++
++/* Enable depth writing. */
++gceSTATUS
++gco3D_EnableDepthWrite(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set depth mode. */
++gceSTATUS
++gco3D_SetDepthMode(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode
++ );
++
++/* Set depth range. */
++gceSTATUS
++gco3D_SetDepthRangeX(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode,
++ IN gctFIXED_POINT Near,
++ IN gctFIXED_POINT Far
++ );
++
++/* Set depth range. */
++gceSTATUS
++gco3D_SetDepthRangeF(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode,
++ IN gctFLOAT Near,
++ IN gctFLOAT Far
++ );
++
++/* Set last pixel enable */
++gceSTATUS
++gco3D_SetLastPixelEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set depth Bias and Scale */
++gceSTATUS
++gco3D_SetDepthScaleBiasX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT DepthScale,
++ IN gctFIXED_POINT DepthBias
++ );
++
++gceSTATUS
++gco3D_SetDepthScaleBiasF(
++ IN gco3D Engine,
++ IN gctFLOAT DepthScale,
++ IN gctFLOAT DepthBias
++ );
++
++/* Set depth near and far clipping plane. */
++gceSTATUS
++gco3D_SetDepthPlaneF(
++ IN gco3D Engine,
++ IN gctFLOAT Near,
++ IN gctFLOAT Far
++ );
++
++/* Enable or disable dithering. */
++gceSTATUS
++gco3D_EnableDither(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set color write enable bits. */
++gceSTATUS
++gco3D_SetColorWrite(
++ IN gco3D Engine,
++ IN gctUINT8 Enable
++ );
++
++/* Enable or disable early depth. */
++gceSTATUS
++gco3D_SetEarlyDepth(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Enable or disable all early depth operations. */
++gceSTATUS
++gco3D_SetAllEarlyDepthModes(
++ IN gco3D Engine,
++ IN gctBOOL Disable
++ );
++
++/* Switch dynamic early mode */
++gceSTATUS
++gco3D_SwitchDynamicEarlyDepthMode(
++ IN gco3D Engine
++ );
++
++/* Set dynamic early mode */
++gceSTATUS
++gco3D_DisableDynamicEarlyDepthMode(
++ IN gco3D Engine,
++ IN gctBOOL Disable
++ );
++
++/* Enable or disable depth-only mode. */
++gceSTATUS
++gco3D_SetDepthOnly(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++typedef struct _gcsSTENCIL_INFO * gcsSTENCIL_INFO_PTR;
++typedef struct _gcsSTENCIL_INFO
++{
++ gceSTENCIL_MODE mode;
++
++ gctUINT8 maskFront;
++ gctUINT8 maskBack;
++ gctUINT8 writeMaskFront;
++ gctUINT8 writeMaskBack;
++
++ gctUINT8 referenceFront;
++
++ gceCOMPARE compareFront;
++ gceSTENCIL_OPERATION passFront;
++ gceSTENCIL_OPERATION failFront;
++ gceSTENCIL_OPERATION depthFailFront;
++
++ gctUINT8 referenceBack;
++ gceCOMPARE compareBack;
++ gceSTENCIL_OPERATION passBack;
++ gceSTENCIL_OPERATION failBack;
++ gceSTENCIL_OPERATION depthFailBack;
++}
++gcsSTENCIL_INFO;
++
++/* Set stencil mode. */
++gceSTATUS
++gco3D_SetStencilMode(
++ IN gco3D Engine,
++ IN gceSTENCIL_MODE Mode
++ );
++
++/* Set stencil mask. */
++gceSTATUS
++gco3D_SetStencilMask(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil back mask. */
++gceSTATUS
++gco3D_SetStencilMaskBack(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil write mask. */
++gceSTATUS
++gco3D_SetStencilWriteMask(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil back write mask. */
++gceSTATUS
++gco3D_SetStencilWriteMaskBack(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil reference. */
++gceSTATUS
++gco3D_SetStencilReference(
++ IN gco3D Engine,
++ IN gctUINT8 Reference,
++ IN gctBOOL Front
++ );
++
++/* Set stencil compare. */
++gceSTATUS
++gco3D_SetStencilCompare(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceCOMPARE Compare
++ );
++
++/* Set stencil operation on pass. */
++gceSTATUS
++gco3D_SetStencilPass(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set stencil operation on fail. */
++gceSTATUS
++gco3D_SetStencilFail(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set stencil operation on depth fail. */
++gceSTATUS
++gco3D_SetStencilDepthFail(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set all stencil states in one blow. */
++gceSTATUS
++gco3D_SetStencilAll(
++ IN gco3D Engine,
++ IN gcsSTENCIL_INFO_PTR Info
++ );
++
++typedef struct _gcsALPHA_INFO * gcsALPHA_INFO_PTR;
++typedef struct _gcsALPHA_INFO
++{
++ /* Alpha test states. */
++ gctBOOL test;
++ gceCOMPARE compare;
++ gctUINT8 reference;
++ gctFLOAT floatReference;
++
++ /* Alpha blending states. */
++ gctBOOL blend;
++
++ gceBLEND_FUNCTION srcFuncColor;
++ gceBLEND_FUNCTION srcFuncAlpha;
++ gceBLEND_FUNCTION trgFuncColor;
++ gceBLEND_FUNCTION trgFuncAlpha;
++
++ gceBLEND_MODE modeColor;
++ gceBLEND_MODE modeAlpha;
++
++ gctUINT32 color;
++}
++gcsALPHA_INFO;
++
++/* Enable or disable alpha test. */
++gceSTATUS
++gco3D_SetAlphaTest(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set alpha test compare. */
++gceSTATUS
++gco3D_SetAlphaCompare(
++ IN gco3D Engine,
++ IN gceCOMPARE Compare
++ );
++
++/* Set alpha test reference in unsigned integer. */
++gceSTATUS
++gco3D_SetAlphaReference(
++ IN gco3D Engine,
++ IN gctUINT8 Reference,
++ IN gctFLOAT FloatReference
++ );
++
++/* Set alpha test reference in fixed point. */
++gceSTATUS
++gco3D_SetAlphaReferenceX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Reference
++ );
++
++/* Set alpha test reference in floating point. */
++gceSTATUS
++gco3D_SetAlphaReferenceF(
++ IN gco3D Engine,
++ IN gctFLOAT Reference
++ );
++
++/* Enable/Disable anti-alias line. */
++gceSTATUS
++gco3D_SetAntiAliasLine(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set texture slot for anti-alias line. */
++gceSTATUS
++gco3D_SetAALineTexSlot(
++ IN gco3D Engine,
++ IN gctUINT TexSlot
++ );
++
++/* Set anti-alias line width scale. */
++gceSTATUS
++gco3D_SetAALineWidth(
++ IN gco3D Engine,
++ IN gctFLOAT Width
++ );
++
++/* Draw a number of primitives. */
++gceSTATUS
++gco3D_DrawPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT StartVertex,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++gceSTATUS
++gco3D_DrawPrimitivesCount(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT* StartVertex,
++ IN gctSIZE_T* VertexCount,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++
++/* Draw a number of primitives using offsets. */
++gceSTATUS
++gco3D_DrawPrimitivesOffset(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT32 StartOffset,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a number of indexed primitives. */
++gceSTATUS
++gco3D_DrawIndexedPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT BaseVertex,
++ IN gctINT StartIndex,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a number of indexed primitives using offsets. */
++gceSTATUS
++gco3D_DrawIndexedPrimitivesOffset(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT32 BaseOffset,
++ IN gctINT32 StartOffset,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Enable or disable anti-aliasing. */
++gceSTATUS
++gco3D_SetAntiAlias(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Write data into the command buffer. */
++gceSTATUS
++gco3D_WriteBuffer(
++ IN gco3D Engine,
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Aligned
++ );
++
++/* Send sempahore and stall until sempahore is signalled. */
++gceSTATUS
++gco3D_Semaphore(
++ IN gco3D Engine,
++ IN gceWHERE From,
++ IN gceWHERE To,
++ IN gceHOW How);
++
++/* Set the subpixels center. */
++gceSTATUS
++gco3D_SetCentroids(
++ IN gco3D Engine,
++ IN gctUINT32 Index,
++ IN gctPOINTER Centroids
++ );
++
++gceSTATUS
++gco3D_SetLogicOp(
++ IN gco3D Engine,
++ IN gctUINT8 Rop
++ );
++
++/* OCL thread walker information. */
++typedef struct _gcsTHREAD_WALKER_INFO * gcsTHREAD_WALKER_INFO_PTR;
++typedef struct _gcsTHREAD_WALKER_INFO
++{
++ gctUINT32 dimensions;
++ gctUINT32 traverseOrder;
++ gctUINT32 enableSwathX;
++ gctUINT32 enableSwathY;
++ gctUINT32 enableSwathZ;
++ gctUINT32 swathSizeX;
++ gctUINT32 swathSizeY;
++ gctUINT32 swathSizeZ;
++ gctUINT32 valueOrder;
++
++ gctUINT32 globalSizeX;
++ gctUINT32 globalOffsetX;
++ gctUINT32 globalSizeY;
++ gctUINT32 globalOffsetY;
++ gctUINT32 globalSizeZ;
++ gctUINT32 globalOffsetZ;
++
++ gctUINT32 workGroupSizeX;
++ gctUINT32 workGroupCountX;
++ gctUINT32 workGroupSizeY;
++ gctUINT32 workGroupCountY;
++ gctUINT32 workGroupSizeZ;
++ gctUINT32 workGroupCountZ;
++
++ gctUINT32 threadAllocation;
++}
++gcsTHREAD_WALKER_INFO;
++
++/* Start OCL thread walker. */
++gceSTATUS
++gco3D_InvokeThreadWalker(
++ IN gco3D Engine,
++ IN gcsTHREAD_WALKER_INFO_PTR Info
++ );
++
++/* Set w clip and w plane limit value. */
++gceSTATUS
++gco3D_SetWClipEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco3D_GetWClipEnable(
++ IN gco3D Engine,
++ OUT gctBOOL * Enable
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimitF(
++ IN gco3D Engine,
++ IN gctFLOAT Value
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimitX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Value
++ );
++
++
++gceSTATUS
++gco3D_SetWPlaneLimit(
++ IN gco3D Engine,
++ IN gctFLOAT Value
++ );
++
++/*----------------------------------------------------------------------------*/
++/*-------------------------- gco3D Fragment Processor ------------------------*/
++
++/* Set the fragment processor configuration. */
++gceSTATUS
++gco3D_SetFragmentConfiguration(
++ IN gco3D Engine,
++ IN gctBOOL ColorFromStream,
++ IN gctBOOL EnableFog,
++ IN gctBOOL EnableSmoothPoint,
++ IN gctUINT32 ClipPlanes
++ );
++
++/* Enable/disable texture stage operation. */
++gceSTATUS
++gco3D_EnableTextureStage(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL Enable
++ );
++
++/* Program the channel enable masks for the color texture function. */
++gceSTATUS
++gco3D_SetTextureColorMask(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL ColorEnabled,
++ IN gctBOOL AlphaEnabled
++ );
++
++/* Program the channel enable masks for the alpha texture function. */
++gceSTATUS
++gco3D_SetTextureAlphaMask(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL ColorEnabled,
++ IN gctBOOL AlphaEnabled
++ );
++
++/* Program the constant fragment color. */
++gceSTATUS
++gco3D_SetFragmentColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetFragmentColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Program the constant fog color. */
++gceSTATUS
++gco3D_SetFogColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetFogColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Program the constant texture color. */
++gceSTATUS
++gco3D_SetTetxureColorX(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetTetxureColorF(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Configure color texture function. */
++gceSTATUS
++gco3D_SetColorTextureFunction(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gceTEXTURE_FUNCTION Function,
++ IN gceTEXTURE_SOURCE Source0,
++ IN gceTEXTURE_CHANNEL Channel0,
++ IN gceTEXTURE_SOURCE Source1,
++ IN gceTEXTURE_CHANNEL Channel1,
++ IN gceTEXTURE_SOURCE Source2,
++ IN gceTEXTURE_CHANNEL Channel2,
++ IN gctINT Scale
++ );
++
++/* Configure alpha texture function. */
++gceSTATUS
++gco3D_SetAlphaTextureFunction(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gceTEXTURE_FUNCTION Function,
++ IN gceTEXTURE_SOURCE Source0,
++ IN gceTEXTURE_CHANNEL Channel0,
++ IN gceTEXTURE_SOURCE Source1,
++ IN gceTEXTURE_CHANNEL Channel1,
++ IN gceTEXTURE_SOURCE Source2,
++ IN gceTEXTURE_CHANNEL Channel2,
++ IN gctINT Scale
++ );
++
++/* Invoke OCL thread walker. */
++gceSTATUS
++gcoHARDWARE_InvokeThreadWalker(
++ IN gcsTHREAD_WALKER_INFO_PTR Info
++ );
++
++/******************************************************************************\
++******************************* gcoTEXTURE Object *******************************
++\******************************************************************************/
++
++/* Cube faces. */
++typedef enum _gceTEXTURE_FACE
++{
++ gcvFACE_NONE,
++ gcvFACE_POSITIVE_X,
++ gcvFACE_NEGATIVE_X,
++ gcvFACE_POSITIVE_Y,
++ gcvFACE_NEGATIVE_Y,
++ gcvFACE_POSITIVE_Z,
++ gcvFACE_NEGATIVE_Z,
++}
++gceTEXTURE_FACE;
++
++#if gcdFORCE_MIPMAP
++typedef enum
++{
++ gcvForceMipDisabled = 0,
++ gcvForceMipEnable = 1,
++ gcvForceMipGenerated = 2,
++ gcvForceMipNever = 3,
++}gceFORCE_MIPMAP;
++#endif
++
++typedef struct _gcsTEXTURE
++{
++ /* Addressing modes. */
++ gceTEXTURE_ADDRESSING s;
++ gceTEXTURE_ADDRESSING t;
++ gceTEXTURE_ADDRESSING r;
++
++ /* Border color. */
++ gctUINT8 border[4];
++
++ /* Filters. */
++ gceTEXTURE_FILTER minFilter;
++ gceTEXTURE_FILTER magFilter;
++ gceTEXTURE_FILTER mipFilter;
++ gctUINT anisoFilter;
++ gctBOOL forceTopLevel;
++ gctBOOL autoMipmap;
++#if gcdFORCE_MIPMAP
++ gceFORCE_MIPMAP forceMipmap;
++#endif
++ /* Level of detail. */
++ gctFIXED_POINT lodBias;
++ gctFIXED_POINT lodMin;
++ gctFIXED_POINT lodMax;
++}
++gcsTEXTURE, * gcsTEXTURE_PTR;
++
++/* Construct a new gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Construct(
++ IN gcoHAL Hal,
++ OUT gcoTEXTURE * Texture
++ );
++
++/* Construct a new sized gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_ConstructSized(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT Faces,
++ IN gctUINT MipMapCount,
++ IN gcePOOL Pool,
++ OUT gcoTEXTURE * Texture
++ );
++
++/* Destroy an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Destroy(
++ IN gcoTEXTURE Texture
++ );
++#if gcdFORCE_MIPMAP
++gceSTATUS
++gcoTEXTURE_DestroyForceMipmap(
++ IN gcoTEXTURE Texture
++ );
++
++gceSTATUS
++gcoTEXTURE_GetMipLevels(
++ IN gcoTEXTURE Texture,
++ OUT gctINT * levels
++ );
++#endif
++/* Replace a mipmap in gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_ReplaceMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Level,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctINT imageFormat,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Depth,
++ IN gctUINT Faces,
++ IN gcePOOL Pool
++ );
++
++/* Upload data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Upload(
++ IN gcoTEXTURE Texture,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctINT Stride,
++ IN gceSURF_FORMAT Format
++ );
++
++/* Upload data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadSub(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT X,
++ IN gctUINT Y,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctINT Stride,
++ IN gceSURF_FORMAT Format
++ );
++
++/* Upload YUV data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadYUV(
++ IN gcoTEXTURE Texture,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctPOINTER Memory[3],
++ IN gctINT Stride[3],
++ IN gceSURF_FORMAT Format
++ );
++
++/* Upload compressed data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadCompressed(
++ IN gcoTEXTURE Texture,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Bytes
++ );
++
++/* Upload compressed sub data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadCompressedSub(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT XOffset,
++ IN gctUINT YOffset,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Size
++ );
++
++/* GetImageFormat of texture. */
++gceSTATUS
++gcoTEXTURE_GetImageFormat(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ OUT gctINT * ImageFormat
++ );
++
++/* Get gcoSURF object for a mipmap level. */
++gceSTATUS
++gcoTEXTURE_GetMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ OUT gcoSURF * Surface
++ );
++
++/* Get gcoSURF object for a mipmap level and face offset. */
++gceSTATUS
++gcoTEXTURE_GetMipMapFace(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ OUT gcoSURF * Surface,
++ OUT gctUINT32_PTR Offset
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gctINT imageFormat,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT Faces,
++ IN gcePOOL Pool,
++ OUT gcoSURF * Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapFromClient(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapFromSurface(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_SetMaxLevel(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Levels
++ );
++
++gceSTATUS
++gcoTEXTURE_SetEndianHint(
++ IN gcoTEXTURE Texture,
++ IN gceENDIAN_HINT EndianHint
++ );
++
++gceSTATUS
++gcoTEXTURE_Disable(
++ IN gcoHAL Hal,
++ IN gctINT Sampler
++ );
++
++gceSTATUS
++gcoTEXTURE_Flush(
++ IN gcoTEXTURE Texture
++ );
++
++gceSTATUS
++gcoTEXTURE_QueryCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MaxDepth,
++ OUT gctBOOL * Cubic,
++ OUT gctBOOL * NonPowerOfTwo,
++ OUT gctUINT * VertexSamplers,
++ OUT gctUINT * PixelSamplers
++ );
++
++gceSTATUS
++gcoTEXTURE_GetTiling(
++ IN gcoTEXTURE Texture,
++ IN gctINT preferLevel,
++ OUT gceTILING * Tiling
++ );
++
++gceSTATUS
++gcoTEXTURE_GetClosestFormat(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT InFormat,
++ OUT gceSURF_FORMAT* OutFormat
++ );
++
++gceSTATUS
++gcoTEXTURE_RenderIntoMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_IsRenderable(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_IsRenderableEx(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_IsComplete(
++ IN gcoTEXTURE Texture,
++ IN gctINT MaxLevel
++ );
++
++gceSTATUS
++gcoTEXTURE_BindTexture(
++ IN gcoTEXTURE Texture,
++ IN gctINT Target,
++ IN gctINT Sampler,
++ IN gcsTEXTURE_PTR Info
++ );
++
++/******************************************************************************\
++******************************* gcoSTREAM Object ******************************
++\******************************************************************************/
++
++typedef enum _gceVERTEX_FORMAT
++{
++ gcvVERTEX_BYTE,
++ gcvVERTEX_UNSIGNED_BYTE,
++ gcvVERTEX_SHORT,
++ gcvVERTEX_UNSIGNED_SHORT,
++ gcvVERTEX_INT,
++ gcvVERTEX_UNSIGNED_INT,
++ gcvVERTEX_FIXED,
++ gcvVERTEX_HALF,
++ gcvVERTEX_FLOAT,
++ gcvVERTEX_UNSIGNED_INT_10_10_10_2,
++ gcvVERTEX_INT_10_10_10_2,
++}
++gceVERTEX_FORMAT;
++
++gceSTATUS
++gcoSTREAM_Construct(
++ IN gcoHAL Hal,
++ OUT gcoSTREAM * Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Destroy(
++ IN gcoSTREAM Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Upload(
++ IN gcoSTREAM Stream,
++ IN gctCONST_POINTER Buffer,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Dynamic
++ );
++
++gceSTATUS
++gcoSTREAM_SetStride(
++ IN gcoSTREAM Stream,
++ IN gctUINT32 Stride
++ );
++
++gceSTATUS
++gcoSTREAM_Lock(
++ IN gcoSTREAM Stream,
++ OUT gctPOINTER * Logical,
++ OUT gctUINT32 * Physical
++ );
++
++gceSTATUS
++gcoSTREAM_Unlock(
++ IN gcoSTREAM Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Reserve(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoSTREAM_Flush(
++ IN gcoSTREAM Stream
++ );
++
++/* Dynamic buffer API. */
++gceSTATUS
++gcoSTREAM_SetDynamic(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Bytes,
++ IN gctUINT Buffers
++ );
++
++typedef struct _gcsSTREAM_INFO
++{
++ gctUINT index;
++ gceVERTEX_FORMAT format;
++ gctBOOL normalized;
++ gctUINT components;
++ gctSIZE_T size;
++ gctCONST_POINTER data;
++ gctUINT stride;
++}
++gcsSTREAM_INFO, * gcsSTREAM_INFO_PTR;
++
++gceSTATUS
++gcoSTREAM_UploadDynamic(
++ IN gcoSTREAM Stream,
++ IN gctUINT VertexCount,
++ IN gctUINT InfoCount,
++ IN gcsSTREAM_INFO_PTR Info,
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoSTREAM_CPUCacheOperation(
++ IN gcoSTREAM Stream,
++ IN gceCACHEOPERATION Operation
++ );
++
++/******************************************************************************\
++******************************** gcoVERTEX Object ******************************
++\******************************************************************************/
++
++typedef struct _gcsVERTEX_ATTRIBUTES
++{
++ gceVERTEX_FORMAT format;
++ gctBOOL normalized;
++ gctUINT32 components;
++ gctSIZE_T size;
++ gctUINT32 stream;
++ gctUINT32 offset;
++ gctUINT32 stride;
++}
++gcsVERTEX_ATTRIBUTES;
++
++gceSTATUS
++gcoVERTEX_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVERTEX * Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_Destroy(
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_Reset(
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_EnableAttribute(
++ IN gcoVERTEX Vertex,
++ IN gctUINT32 Index,
++ IN gceVERTEX_FORMAT Format,
++ IN gctBOOL Normalized,
++ IN gctUINT32 Components,
++ IN gcoSTREAM Stream,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Stride
++ );
++
++gceSTATUS
++gcoVERTEX_DisableAttribute(
++ IN gcoVERTEX Vertex,
++ IN gctUINT32 Index
++ );
++
++gceSTATUS
++gcoVERTEX_Bind(
++ IN gcoVERTEX Vertex
++ );
++
++/*******************************************************************************
++***** gcoVERTEXARRAY Object ***************************************************/
++
++typedef struct _gcsVERTEXARRAY
++{
++ /* Enabled. */
++ gctBOOL enable;
++
++ /* Number of components. */
++ gctINT size;
++
++ /* Attribute format. */
++ gceVERTEX_FORMAT format;
++
++ /* Flag whether the attribute is normalized or not. */
++ gctBOOL normalized;
++
++ /* Stride of the component. */
++ gctUINT stride;
++
++ /* Pointer to the attribute data. */
++ gctCONST_POINTER pointer;
++
++ /* Stream object owning the attribute data. */
++ gcoSTREAM stream;
++
++ /* Generic values for attribute. */
++ gctFLOAT genericValue[4];
++
++ /* Generic size for attribute. */
++ gctINT genericSize;
++
++ /* Vertex shader linkage. */
++ gctUINT linkage;
++
++#if gcdUSE_WCLIP_PATCH
++ gctBOOL isPosition;
++#endif
++}
++gcsVERTEXARRAY,
++* gcsVERTEXARRAY_PTR;
++
++gceSTATUS
++gcoVERTEXARRAY_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVERTEXARRAY * Vertex
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Destroy(
++ IN gcoVERTEXARRAY Vertex
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Bind(
++ IN gcoVERTEXARRAY Vertex,
++ IN gctUINT32 EnableBits,
++ IN gcsVERTEXARRAY_PTR VertexArray,
++ IN gctUINT First,
++ IN gctSIZE_T Count,
++ IN gceINDEX_TYPE IndexType,
++ IN gcoINDEX IndexObject,
++ IN gctPOINTER IndexMemory,
++ IN OUT gcePRIMITIVE * PrimitiveType,
++#if gcdUSE_WCLIP_PATCH
++ IN OUT gctUINT * PrimitiveCount,
++ IN OUT gctFLOAT * wLimitRms,
++ IN OUT gctBOOL * wLimitDirty
++#else
++ IN OUT gctUINT * PrimitiveCount
++#endif
++ );
++
++gctUINT
++gcoVERTEXARRAY_GetMaxStream(
++ IN gcoVERTEXARRAY Vertex
++);
++
++gceSTATUS
++gcoVERTEXARRAY_SetMaxStream(
++ IN gcoVERTEXARRAY Vertex,
++ gctUINT maxStreams
++);
++/*******************************************************************************
++***** Composition *************************************************************/
++
++typedef enum _gceCOMPOSITION
++{
++ gcvCOMPOSE_CLEAR = 1,
++ gcvCOMPOSE_BLUR,
++ gcvCOMPOSE_DIM,
++ gcvCOMPOSE_LAYER
++}
++gceCOMPOSITION;
++
++typedef struct _gcsCOMPOSITION * gcsCOMPOSITION_PTR;
++typedef struct _gcsCOMPOSITION
++{
++ /* Structure size. */
++ gctUINT structSize;
++
++ /* Composition operation. */
++ gceCOMPOSITION operation;
++
++ /* Layer to be composed. */
++ gcoSURF layer;
++
++ /* Source and target coordinates. */
++ gcsRECT srcRect;
++ gcsRECT trgRect;
++
++ /* Target rectangle */
++ gcsPOINT v0;
++ gcsPOINT v1;
++ gcsPOINT v2;
++
++ /* Blending parameters. */
++ gctBOOL enableBlending;
++ gctBOOL premultiplied;
++ gctUINT8 alphaValue;
++
++ /* Clear color. */
++ gctFLOAT r;
++ gctFLOAT g;
++ gctFLOAT b;
++ gctFLOAT a;
++}
++gcsCOMPOSITION;
++
++gceSTATUS
++gco3D_ProbeComposition(
++ gctBOOL ResetIfEmpty
++ );
++
++gceSTATUS
++gco3D_CompositionBegin(
++ void
++ );
++
++gceSTATUS
++gco3D_ComposeLayer(
++ IN gcsCOMPOSITION_PTR Layer
++ );
++
++gceSTATUS
++gco3D_CompositionSignals(
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal1,
++ IN gctSIGNAL Signal2
++ );
++
++gceSTATUS
++gco3D_CompositionEnd(
++ IN gcoSURF Target,
++ IN gctBOOL Synchronous
++ );
++
++/* Frame Database */
++gceSTATUS
++gcoHAL_AddFrameDB(
++ void
++ );
++
++gceSTATUS
++gcoHAL_DumpFrameDB(
++ gctCONST_STRING Filename OPTIONAL
++ );
++
++gceSTATUS
++gcoHAL_GetSharedInfo(
++ IN gctUINT32 Pid,
++ IN gctUINT32 DataId,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER Data
++ );
++
++gceSTATUS
++gcoHAL_SetSharedInfo(
++ IN gctUINT32 DataId,
++ IN gctPOINTER Data,
++ IN gctSIZE_T Bytes
++ );
++
++#if VIVANTE_PROFILER_CONTEXT
++gceSTATUS
++gcoHARDWARE_GetContext(
++ IN gcoHARDWARE Hardware,
++ OUT gctUINT32 * Context
++ );
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* VIVANTE_NO_3D */
++#endif /* __gc_hal_engine_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,904 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_engine_vg_h_
++#define __gc_hal_engine_vg_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "gc_hal_types.h"
++
++/******************************************************************************\
++******************************** VG Enumerations *******************************
++\******************************************************************************/
++
++/**
++** @ingroup gcoVG
++**
++** @brief Tiling mode for painting and imagig.
++**
++** This enumeration defines the tiling modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 tile modes.
++*/
++typedef enum _gceTILE_MODE
++{
++ gcvTILE_FILL,
++ gcvTILE_PAD,
++ gcvTILE_REPEAT,
++ gcvTILE_REFLECT
++}
++gceTILE_MODE;
++
++/******************************************************************************/
++/** @ingroup gcoVG
++**
++** @brief The different paint modes.
++**
++** This enumeration lists the available paint modes.
++*/
++typedef enum _gcePAINT_TYPE
++{
++ /** Solid color. */
++ gcvPAINT_MODE_SOLID,
++
++ /** Linear gradient. */
++ gcvPAINT_MODE_LINEAR,
++
++ /** Radial gradient. */
++ gcvPAINT_MODE_RADIAL,
++
++ /** Pattern. */
++ gcvPAINT_MODE_PATTERN,
++
++ /** Mode count. */
++ gcvPAINT_MODE_COUNT
++}
++gcePAINT_TYPE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Types of path data supported by HAL.
++**
++** This enumeration defines the types of path data supported by the HAL.
++** This is in fact a one-to-one mapping of the OpenVG 1.1 path types.
++*/
++typedef enum _gcePATHTYPE
++{
++ gcePATHTYPE_UNKNOWN = -1,
++ gcePATHTYPE_INT8,
++ gcePATHTYPE_INT16,
++ gcePATHTYPE_INT32,
++ gcePATHTYPE_FLOAT
++}
++gcePATHTYPE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Supported path segment commands.
++**
++** This enumeration defines the path segment commands supported by the HAL.
++*/
++typedef enum _gceVGCMD
++{
++ gcvVGCMD_END, /* 0: GCCMD_TS_OPCODE_END */
++ gcvVGCMD_CLOSE, /* 1: GCCMD_TS_OPCODE_CLOSE */
++ gcvVGCMD_MOVE, /* 2: GCCMD_TS_OPCODE_MOVE */
++ gcvVGCMD_MOVE_REL, /* 3: GCCMD_TS_OPCODE_MOVE_REL */
++ gcvVGCMD_LINE, /* 4: GCCMD_TS_OPCODE_LINE */
++ gcvVGCMD_LINE_REL, /* 5: GCCMD_TS_OPCODE_LINE_REL */
++ gcvVGCMD_QUAD, /* 6: GCCMD_TS_OPCODE_QUADRATIC */
++ gcvVGCMD_QUAD_REL, /* 7: GCCMD_TS_OPCODE_QUADRATIC_REL */
++ gcvVGCMD_CUBIC, /* 8: GCCMD_TS_OPCODE_CUBIC */
++ gcvVGCMD_CUBIC_REL, /* 9: GCCMD_TS_OPCODE_CUBIC_REL */
++ gcvVGCMD_BREAK, /* 10: GCCMD_TS_OPCODE_BREAK */
++ gcvVGCMD_HLINE, /* 11: ******* R E S E R V E D *******/
++ gcvVGCMD_HLINE_REL, /* 12: ******* R E S E R V E D *******/
++ gcvVGCMD_VLINE, /* 13: ******* R E S E R V E D *******/
++ gcvVGCMD_VLINE_REL, /* 14: ******* R E S E R V E D *******/
++ gcvVGCMD_SQUAD, /* 15: ******* R E S E R V E D *******/
++ gcvVGCMD_SQUAD_REL, /* 16: ******* R E S E R V E D *******/
++ gcvVGCMD_SCUBIC, /* 17: ******* R E S E R V E D *******/
++ gcvVGCMD_SCUBIC_REL, /* 18: ******* R E S E R V E D *******/
++ gcvVGCMD_SCCWARC, /* 19: ******* R E S E R V E D *******/
++ gcvVGCMD_SCCWARC_REL, /* 20: ******* R E S E R V E D *******/
++ gcvVGCMD_SCWARC, /* 21: ******* R E S E R V E D *******/
++ gcvVGCMD_SCWARC_REL, /* 22: ******* R E S E R V E D *******/
++ gcvVGCMD_LCCWARC, /* 23: ******* R E S E R V E D *******/
++ gcvVGCMD_LCCWARC_REL, /* 24: ******* R E S E R V E D *******/
++ gcvVGCMD_LCWARC, /* 25: ******* R E S E R V E D *******/
++ gcvVGCMD_LCWARC_REL, /* 26: ******* R E S E R V E D *******/
++
++ /* The width of the command recognized by the hardware on bits. */
++ gcvVGCMD_WIDTH = 5,
++
++ /* Hardware command mask. */
++ gcvVGCMD_MASK = (1 << gcvVGCMD_WIDTH) - 1,
++
++ /* Command modifiers. */
++ gcvVGCMD_H_MOD = 1 << gcvVGCMD_WIDTH, /* = 32 */
++ gcvVGCMD_V_MOD = 2 << gcvVGCMD_WIDTH, /* = 64 */
++ gcvVGCMD_S_MOD = 3 << gcvVGCMD_WIDTH, /* = 96 */
++ gcvVGCMD_ARC_MOD = 4 << gcvVGCMD_WIDTH, /* = 128 */
++
++ /* Emulated LINE commands. */
++ gcvVGCMD_HLINE_EMUL = gcvVGCMD_H_MOD | gcvVGCMD_LINE, /* = 36 */
++ gcvVGCMD_HLINE_EMUL_REL = gcvVGCMD_H_MOD | gcvVGCMD_LINE_REL, /* = 37 */
++ gcvVGCMD_VLINE_EMUL = gcvVGCMD_V_MOD | gcvVGCMD_LINE, /* = 68 */
++ gcvVGCMD_VLINE_EMUL_REL = gcvVGCMD_V_MOD | gcvVGCMD_LINE_REL, /* = 69 */
++
++ /* Emulated SMOOTH commands. */
++ gcvVGCMD_SQUAD_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD, /* = 102 */
++ gcvVGCMD_SQUAD_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD_REL, /* = 103 */
++ gcvVGCMD_SCUBIC_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC, /* = 104 */
++ gcvVGCMD_SCUBIC_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC_REL, /* = 105 */
++
++ /* Emulation ARC commands. */
++ gcvVGCMD_ARC_LINE = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE, /* = 132 */
++ gcvVGCMD_ARC_LINE_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE_REL, /* = 133 */
++ gcvVGCMD_ARC_QUAD = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD, /* = 134 */
++ gcvVGCMD_ARC_QUAD_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD_REL /* = 135 */
++}
++gceVGCMD;
++typedef enum _gceVGCMD * gceVGCMD_PTR;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Blending modes supported by the HAL.
++**
++** This enumeration defines the blending modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 blending modes.
++*/
++typedef enum _gceVG_BLEND
++{
++ gcvVG_BLEND_SRC,
++ gcvVG_BLEND_SRC_OVER,
++ gcvVG_BLEND_DST_OVER,
++ gcvVG_BLEND_SRC_IN,
++ gcvVG_BLEND_DST_IN,
++ gcvVG_BLEND_MULTIPLY,
++ gcvVG_BLEND_SCREEN,
++ gcvVG_BLEND_DARKEN,
++ gcvVG_BLEND_LIGHTEN,
++ gcvVG_BLEND_ADDITIVE,
++ gcvVG_BLEND_SUBTRACT,
++ gcvVG_BLEND_FILTER
++}
++gceVG_BLEND;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Image modes supported by the HAL.
++**
++** This enumeration defines the image modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 image modes with the addition
++** of NO IMAGE.
++*/
++typedef enum _gceVG_IMAGE
++{
++ gcvVG_IMAGE_NONE,
++ gcvVG_IMAGE_NORMAL,
++ gcvVG_IMAGE_MULTIPLY,
++ gcvVG_IMAGE_STENCIL,
++ gcvVG_IMAGE_FILTER
++}
++gceVG_IMAGE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Filter mode patterns and imaging.
++**
++** This enumeration defines the filter modes supported by the HAL.
++*/
++typedef enum _gceIMAGE_FILTER
++{
++ gcvFILTER_POINT,
++ gcvFILTER_LINEAR,
++ gcvFILTER_BI_LINEAR
++}
++gceIMAGE_FILTER;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Primitive modes supported by the HAL.
++**
++** This enumeration defines the primitive modes supported by the HAL.
++*/
++typedef enum _gceVG_PRIMITIVE
++{
++ gcvVG_SCANLINE,
++ gcvVG_RECTANGLE,
++ gcvVG_TESSELLATED,
++ gcvVG_TESSELLATED_TILED
++}
++gceVG_PRIMITIVE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Rendering quality modes supported by the HAL.
++**
++** This enumeration defines the rendering quality modes supported by the HAL.
++*/
++typedef enum _gceRENDER_QUALITY
++{
++ gcvVG_NONANTIALIASED,
++ gcvVG_2X2_MSAA,
++ gcvVG_2X4_MSAA,
++ gcvVG_4X4_MSAA
++}
++gceRENDER_QUALITY;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Fill rules supported by the HAL.
++**
++** This enumeration defines the fill rules supported by the HAL.
++*/
++typedef enum _gceFILL_RULE
++{
++ gcvVG_EVEN_ODD,
++ gcvVG_NON_ZERO
++}
++gceFILL_RULE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Cap styles supported by the HAL.
++**
++** This enumeration defines the cap styles supported by the HAL.
++*/
++typedef enum _gceCAP_STYLE
++{
++ gcvCAP_BUTT,
++ gcvCAP_ROUND,
++ gcvCAP_SQUARE
++}
++gceCAP_STYLE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Join styles supported by the HAL.
++**
++** This enumeration defines the join styles supported by the HAL.
++*/
++typedef enum _gceJOIN_STYLE
++{
++ gcvJOIN_MITER,
++ gcvJOIN_ROUND,
++ gcvJOIN_BEVEL
++}
++gceJOIN_STYLE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Channel mask values.
++**
++** This enumeration defines the values for channel mask used in image
++** filtering.
++*/
++
++/* Base values for channel mask definitions. */
++#define gcvCHANNEL_X (0)
++#define gcvCHANNEL_R (1 << 0)
++#define gcvCHANNEL_G (1 << 1)
++#define gcvCHANNEL_B (1 << 2)
++#define gcvCHANNEL_A (1 << 3)
++
++typedef enum _gceCHANNEL
++{
++ gcvCHANNEL_XXXX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_XXXA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_XXBX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_XXBA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_XGXX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_XGXA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_XGBX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_XGBA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_RXXX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_RXXA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_RXBX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_RXBA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_RGXX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_RGXA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_RGBX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_RGBA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A),
++}
++gceCHANNEL;
++
++/******************************************************************************\
++******************************** VG Structures *******************************
++\******************************************************************************/
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the color ramp used by the gradient paints.
++**
++** The gcsCOLOR_RAMP structure defines the layout of one single color inside
++** a color ramp which is used by gradient paints.
++*/
++typedef struct _gcsCOLOR_RAMP
++{
++ /** Value for the color stop. */
++ gctFLOAT stop;
++
++ /** Red color channel value for the color stop. */
++ gctFLOAT red;
++
++ /** Green color channel value for the color stop. */
++ gctFLOAT green;
++
++ /** Blue color channel value for the color stop. */
++ gctFLOAT blue;
++
++ /** Alpha color channel value for the color stop. */
++ gctFLOAT alpha;
++}
++gcsCOLOR_RAMP, * gcsCOLOR_RAMP_PTR;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the color ramp used by the gradient paints in fixed form.
++**
++** The gcsCOLOR_RAMP structure defines the layout of one single color inside
++** a color ramp which is used by gradient paints.
++*/
++typedef struct _gcsFIXED_COLOR_RAMP
++{
++ /** Value for the color stop. */
++ gctFIXED_POINT stop;
++
++ /** Red color channel value for the color stop. */
++ gctFIXED_POINT red;
++
++ /** Green color channel value for the color stop. */
++ gctFIXED_POINT green;
++
++ /** Blue color channel value for the color stop. */
++ gctFIXED_POINT blue;
++
++ /** Alpha color channel value for the color stop. */
++ gctFIXED_POINT alpha;
++}
++gcsFIXED_COLOR_RAMP, * gcsFIXED_COLOR_RAMP_PTR;
++
++
++/**
++** @ingroup gcoVG
++**
++** @brief Rectangle structure used by the gcoVG object.
++**
++** This structure defines the layout of a rectangle. Make sure width and
++** height are larger than 0.
++*/
++typedef struct _gcsVG_RECT * gcsVG_RECT_PTR;
++typedef struct _gcsVG_RECT
++{
++ /** Left location of the rectangle. */
++ gctINT x;
++
++ /** Top location of the rectangle. */
++ gctINT y;
++
++ /** Width of the rectangle. */
++ gctINT width;
++
++ /** Height of the rectangle. */
++ gctINT height;
++}
++gcsVG_RECT;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Path command buffer attribute structure.
++**
++** The gcsPATH_BUFFER_INFO structure contains the specifics about
++** the layout of the path data command buffer.
++*/
++typedef struct _gcsPATH_BUFFER_INFO * gcsPATH_BUFFER_INFO_PTR;
++typedef struct _gcsPATH_BUFFER_INFO
++{
++ gctUINT reservedForHead;
++ gctUINT reservedForTail;
++}
++gcsPATH_BUFFER_INFO;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the path data container structure.
++**
++** The gcsPATH structure defines the layout of the path data container.
++*/
++typedef struct _gcsPATH_DATA * gcsPATH_DATA_PTR;
++typedef struct _gcsPATH_DATA
++{
++ /* Data container in command buffer format. */
++ gcsCMDBUFFER data;
++
++ /* Path data type. */
++ gcePATHTYPE dataType;
++}
++gcsPATH_DATA;
++
++
++/******************************************************************************\
++********************************* gcoHAL Object ********************************
++\******************************************************************************/
++
++/* Query path data storage attributes. */
++gceSTATUS
++gcoHAL_QueryPathStorage(
++ IN gcoHAL Hal,
++ OUT gcsPATH_BUFFER_INFO_PTR Information
++ );
++
++/* Associate a completion signal with the command buffer. */
++gceSTATUS
++gcoHAL_AssociateCompletion(
++ IN gcoHAL Hal,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Release the current command buffer completion signal. */
++gceSTATUS
++gcoHAL_DeassociateCompletion(
++ IN gcoHAL Hal,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Verify whether the command buffer is still in use. */
++gceSTATUS
++gcoHAL_CheckCompletion(
++ IN gcoHAL Hal,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Wait until the command buffer is no longer in use. */
++gceSTATUS
++gcoHAL_WaitCompletion(
++ IN gcoHAL Hal,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Flush the pixel cache. */
++gceSTATUS
++gcoHAL_Flush(
++ IN gcoHAL Hal
++ );
++
++/* Split a harwdare address into pool and offset. */
++gceSTATUS
++gcoHAL_SplitAddress(
++ IN gcoHAL Hal,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Combine pool and offset into a harwdare address. */
++gceSTATUS
++gcoHAL_CombineAddress(
++ IN gcoHAL Hal,
++ IN gcePOOL Pool,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Schedule to free linear video memory allocated. */
++gceSTATUS
++gcoHAL_ScheduleVideoMemory(
++ IN gcoHAL Hal,
++ IN gctUINT64 Node
++ );
++
++/* Free linear video memory allocated with gcoHAL_AllocateLinearVideoMemory. */
++gceSTATUS
++gcoHAL_FreeVideoMemory(
++ IN gcoHAL Hal,
++ IN gctUINT64 Node
++ );
++
++/* Query command buffer attributes. */
++gceSTATUS
++gcoHAL_QueryCommandBuffer(
++ IN gcoHAL Hal,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++/* Allocate and lock linear video memory. */
++gceSTATUS
++gcoHAL_AllocateLinearVideoMemory(
++ IN gcoHAL Hal,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ IN gcePOOL Pool,
++ OUT gctUINT64 * Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Align the specified size accordingly to the hardware requirements. */
++gceSTATUS
++gcoHAL_GetAlignedSurfaceSize(
++ IN gcoHAL Hal,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Width,
++ IN OUT gctUINT32_PTR Height
++ );
++
++gceSTATUS
++gcoHAL_ReserveTask(
++ IN gcoHAL Hal,
++ IN gceBLOCK Block,
++ IN gctUINT TaskCount,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++/******************************************************************************\
++********************************** gcoVG Object ********************************
++\******************************************************************************/
++
++/** @defgroup gcoVG gcoVG
++**
++** The gcoVG object abstracts the VG hardware pipe.
++*/
++
++gctBOOL
++gcoVG_IsMaskSupported(
++ IN gceSURF_FORMAT Format
++ );
++
++gctBOOL
++gcoVG_IsTargetSupported(
++ IN gceSURF_FORMAT Format
++ );
++
++gctBOOL
++gcoVG_IsImageSupported(
++ IN gceSURF_FORMAT Format
++ );
++
++gctUINT8 gcoVG_PackColorComponent(
++ gctFLOAT Value
++ );
++
++gceSTATUS
++gcoVG_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVG * Vg
++ );
++
++gceSTATUS
++gcoVG_Destroy(
++ IN gcoVG Vg
++ );
++
++gceSTATUS
++gcoVG_SetTarget(
++ IN gcoVG Vg,
++ IN gcoSURF Target
++ );
++
++gceSTATUS
++gcoVG_UnsetTarget(
++ IN gcoVG Vg,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoVG_SetUserToSurface(
++ IN gcoVG Vg,
++ IN gctFLOAT UserToSurface[9]
++ );
++
++gceSTATUS
++gcoVG_SetSurfaceToImage(
++ IN gcoVG Vg,
++ IN gctFLOAT SurfaceToImage[9]
++ );
++
++gceSTATUS
++gcoVG_EnableMask(
++ IN gcoVG Vg,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetMask(
++ IN gcoVG Vg,
++ IN gcoSURF Mask
++ );
++
++gceSTATUS
++gcoVG_UnsetMask(
++ IN gcoVG Vg,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoVG_FlushMask(
++ IN gcoVG Vg
++ );
++
++gceSTATUS
++gcoVG_EnableScissor(
++ IN gcoVG Vg,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetScissor(
++ IN gcoVG Vg,
++ IN gctSIZE_T RectangleCount,
++ IN gcsVG_RECT_PTR Rectangles
++ );
++
++gceSTATUS
++gcoVG_EnableColorTransform(
++ IN gcoVG Vg,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetColorTransform(
++ IN gcoVG Vg,
++ IN gctFLOAT ColorTransform[8]
++ );
++
++gceSTATUS
++gcoVG_SetTileFillColor(
++ IN gcoVG Vg,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++gceSTATUS
++gcoVG_SetSolidPaint(
++ IN gcoVG Vg,
++ IN gctUINT8 Red,
++ IN gctUINT8 Green,
++ IN gctUINT8 Blue,
++ IN gctUINT8 Alpha
++ );
++
++gceSTATUS
++gcoVG_SetLinearPaint(
++ IN gcoVG Vg,
++ IN gctFLOAT Constant,
++ IN gctFLOAT StepX,
++ IN gctFLOAT StepY
++ );
++
++gceSTATUS
++gcoVG_SetRadialPaint(
++ IN gcoVG Vg,
++ IN gctFLOAT LinConstant,
++ IN gctFLOAT LinStepX,
++ IN gctFLOAT LinStepY,
++ IN gctFLOAT RadConstant,
++ IN gctFLOAT RadStepX,
++ IN gctFLOAT RadStepY,
++ IN gctFLOAT RadStepXX,
++ IN gctFLOAT RadStepYY,
++ IN gctFLOAT RadStepXY
++ );
++
++gceSTATUS
++gcoVG_SetPatternPaint(
++ IN gcoVG Vg,
++ IN gctFLOAT UConstant,
++ IN gctFLOAT UStepX,
++ IN gctFLOAT UStepY,
++ IN gctFLOAT VConstant,
++ IN gctFLOAT VStepX,
++ IN gctFLOAT VStepY,
++ IN gctBOOL Linear
++ );
++
++gceSTATUS
++gcoVG_SetColorRamp(
++ IN gcoVG Vg,
++ IN gcoSURF ColorRamp,
++ IN gceTILE_MODE ColorRampSpreadMode
++ );
++
++gceSTATUS
++gcoVG_SetPattern(
++ IN gcoVG Vg,
++ IN gcoSURF Pattern,
++ IN gceTILE_MODE TileMode,
++ IN gceIMAGE_FILTER Filter
++ );
++
++gceSTATUS
++gcoVG_SetImageMode(
++ IN gcoVG Vg,
++ IN gceVG_IMAGE Mode
++ );
++
++gceSTATUS
++gcoVG_SetBlendMode(
++ IN gcoVG Vg,
++ IN gceVG_BLEND Mode
++ );
++
++gceSTATUS
++gcoVG_SetRenderingQuality(
++ IN gcoVG Vg,
++ IN gceRENDER_QUALITY Quality
++ );
++
++gceSTATUS
++gcoVG_SetFillRule(
++ IN gcoVG Vg,
++ IN gceFILL_RULE FillRule
++ );
++
++gceSTATUS
++gcoVG_FinalizePath(
++ IN gcoVG Vg,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++gceSTATUS
++gcoVG_Clear(
++ IN gcoVG Vg,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_DrawPath(
++ IN gcoVG Vg,
++ IN gcsPATH_DATA_PTR PathData,
++ IN gctFLOAT Scale,
++ IN gctFLOAT Bias,
++ IN gctBOOL SoftwareTesselation
++ );
++
++gceSTATUS
++gcoVG_DrawImage(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT SourceX,
++ IN gctINT SourceY,
++ IN gctINT TargetX,
++ IN gctINT TargetY,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctBOOL Mask
++ );
++
++gceSTATUS
++gcoVG_TesselateImage(
++ IN gcoVG Vg,
++ IN gcoSURF Image,
++ IN gcsVG_RECT_PTR Rectangle,
++ IN gceIMAGE_FILTER Filter,
++ IN gctBOOL Mask,
++ IN gctBOOL SoftwareTesselation
++ );
++
++gceSTATUS
++gcoVG_Blit(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gcsVG_RECT_PTR SrcRect,
++ IN gcsVG_RECT_PTR TrgRect,
++ IN gceIMAGE_FILTER Filter,
++ IN gceVG_BLEND Mode
++ );
++
++gceSTATUS
++gcoVG_ColorMatrix(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN const gctFLOAT * Matrix,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_SeparableConvolve(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctINT KernelWidth,
++ IN gctINT KernelHeight,
++ IN gctINT ShiftX,
++ IN gctINT ShiftY,
++ IN const gctINT16 * KernelX,
++ IN const gctINT16 * KernelY,
++ IN gctFLOAT Scale,
++ IN gctFLOAT Bias,
++ IN gceTILE_MODE TilingMode,
++ IN gctFLOAT_PTR FillColor,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_GaussianBlur(
++ IN gcoVG Vg,
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctFLOAT StdDeviationX,
++ IN gctFLOAT StdDeviationY,
++ IN gceTILE_MODE TilingMode,
++ IN gctFLOAT_PTR FillColor,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_EnableDither(
++ IN gcoVG Vg,
++ IN gctBOOL Enable
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_vg_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,962 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_enum_h_
++#define __gc_hal_enum_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Chip models. */
++typedef enum _gceCHIPMODEL
++{
++ gcv300 = 0x0300,
++ gcv320 = 0x0320,
++ gcv350 = 0x0350,
++ gcv355 = 0x0355,
++ gcv400 = 0x0400,
++ gcv410 = 0x0410,
++ gcv420 = 0x0420,
++ gcv450 = 0x0450,
++ gcv500 = 0x0500,
++ gcv530 = 0x0530,
++ gcv600 = 0x0600,
++ gcv700 = 0x0700,
++ gcv800 = 0x0800,
++ gcv860 = 0x0860,
++ gcv880 = 0x0880,
++ gcv1000 = 0x1000,
++ gcv2000 = 0x2000,
++ gcv2100 = 0x2100,
++ gcv4000 = 0x4000,
++}
++gceCHIPMODEL;
++
++/* Chip features. */
++typedef enum _gceFEATURE
++{
++ gcvFEATURE_PIPE_2D = 0,
++ gcvFEATURE_PIPE_3D,
++ gcvFEATURE_PIPE_VG,
++ gcvFEATURE_DC,
++ gcvFEATURE_HIGH_DYNAMIC_RANGE,
++ gcvFEATURE_MODULE_CG,
++ gcvFEATURE_MIN_AREA,
++ gcvFEATURE_BUFFER_INTERLEAVING,
++ gcvFEATURE_BYTE_WRITE_2D,
++ gcvFEATURE_ENDIANNESS_CONFIG,
++ gcvFEATURE_DUAL_RETURN_BUS,
++ gcvFEATURE_DEBUG_MODE,
++ gcvFEATURE_YUY2_RENDER_TARGET,
++ gcvFEATURE_FRAGMENT_PROCESSOR,
++ gcvFEATURE_2DPE20,
++ gcvFEATURE_FAST_CLEAR,
++ gcvFEATURE_YUV420_TILER,
++ gcvFEATURE_YUY2_AVERAGING,
++ gcvFEATURE_FLIP_Y,
++ gcvFEATURE_EARLY_Z,
++ gcvFEATURE_Z_COMPRESSION,
++ gcvFEATURE_MSAA,
++ gcvFEATURE_SPECIAL_ANTI_ALIASING,
++ gcvFEATURE_SPECIAL_MSAA_LOD,
++ gcvFEATURE_422_TEXTURE_COMPRESSION,
++ gcvFEATURE_DXT_TEXTURE_COMPRESSION,
++ gcvFEATURE_ETC1_TEXTURE_COMPRESSION,
++ gcvFEATURE_CORRECT_TEXTURE_CONVERTER,
++ gcvFEATURE_TEXTURE_8K,
++ gcvFEATURE_SCALER,
++ gcvFEATURE_YUV420_SCALER,
++ gcvFEATURE_SHADER_HAS_W,
++ gcvFEATURE_SHADER_HAS_SIGN,
++ gcvFEATURE_SHADER_HAS_FLOOR,
++ gcvFEATURE_SHADER_HAS_CEIL,
++ gcvFEATURE_SHADER_HAS_SQRT,
++ gcvFEATURE_SHADER_HAS_TRIG,
++ gcvFEATURE_VAA,
++ gcvFEATURE_HZ,
++ gcvFEATURE_CORRECT_STENCIL,
++ gcvFEATURE_VG20,
++ gcvFEATURE_VG_FILTER,
++ gcvFEATURE_VG21,
++ gcvFEATURE_VG_DOUBLE_BUFFER,
++ gcvFEATURE_MC20,
++ gcvFEATURE_SUPER_TILED,
++ gcvFEATURE_2D_FILTERBLIT_PLUS_ALPHABLEND,
++ gcvFEATURE_2D_DITHER,
++ gcvFEATURE_2D_A8_TARGET,
++ gcvFEATURE_2D_FILTERBLIT_FULLROTATION,
++ gcvFEATURE_2D_BITBLIT_FULLROTATION,
++ gcvFEATURE_WIDE_LINE,
++ gcvFEATURE_FC_FLUSH_STALL,
++ gcvFEATURE_FULL_DIRECTFB,
++ gcvFEATURE_HALF_FLOAT_PIPE,
++ gcvFEATURE_LINE_LOOP,
++ gcvFEATURE_2D_YUV_BLIT,
++ gcvFEATURE_2D_TILING,
++ gcvFEATURE_NON_POWER_OF_TWO,
++ gcvFEATURE_3D_TEXTURE,
++ gcvFEATURE_TEXTURE_ARRAY,
++ gcvFEATURE_TILE_FILLER,
++ gcvFEATURE_LOGIC_OP,
++ gcvFEATURE_COMPOSITION,
++ gcvFEATURE_MIXED_STREAMS,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT,
++ gcvFEATURE_END_EVENT,
++ gcvFEATURE_VERTEX_10_10_10_2,
++ gcvFEATURE_TEXTURE_10_10_10_2,
++ gcvFEATURE_TEXTURE_ANISOTROPIC_FILTERING,
++ gcvFEATURE_TEXTURE_FLOAT_HALF_FLOAT,
++ gcvFEATURE_2D_ROTATION_STALL_FIX,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX,
++ gcvFEATURE_BUG_FIXES10,
++ gcvFEATURE_2D_MINOR_TILING,
++ /* Supertiled compressed textures are supported. */
++ gcvFEATURE_TEX_COMPRRESSION_SUPERTILED,
++ gcvFEATURE_FAST_MSAA,
++ gcvFEATURE_BUG_FIXED_INDEXED_TRIANGLE_STRIP,
++ gcvFEATURE_TEXTURE_TILED_READ,
++ gcvFEATURE_DEPTH_BIAS_FIX,
++ gcvFEATURE_RECT_PRIMITIVE,
++ gcvFEATURE_BUG_FIXES11,
++ gcvFEATURE_SUPERTILED_TEXTURE,
++ gcvFEATURE_2D_NO_COLORBRUSH_INDEX8,
++ gcvFEATURE_RS_YUV_TARGET,
++ gcvFEATURE_2D_FC_SOURCE,
++ gcvFEATURE_PE_DITHER_FIX,
++ gcvFEATURE_2D_YUV_SEPARATE_STRIDE,
++ gcvFEATURE_FRUSTUM_CLIP_FIX,
++ gcvFEATURE_TEXTURE_LINEAR,
++ gcvFEATURE_TEXTURE_YUV_ASSEMBLER,
++ gcvFEATURE_SHADER_HAS_INSTRUCTION_CACHE,
++ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING,
++ gcvFEATURE_BUGFIX15,
++ gcvFEATURE_2D_GAMMA,
++ gcvFEATURE_2D_COLOR_SPACE_CONVERSION,
++ gcvFEATURE_2D_SUPER_TILE_VERSION,
++ gcvFEATURE_2D_MIRROR_EXTENSION,
++ gcvFEATURE_2D_SUPER_TILE_V1,
++ gcvFEATURE_2D_SUPER_TILE_V2,
++ gcvFEATURE_2D_SUPER_TILE_V3,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX2,
++ gcvFEATURE_ELEMENT_INDEX_UINT,
++ gcvFEATURE_2D_COMPRESSION,
++ gcvFEATURE_2D_OPF_YUV_OUTPUT,
++ gcvFEATURE_2D_MULTI_SRC_BLT_TO_UNIFIED_DST_RECT,
++ gcvFEATURE_2D_YUV_MODE,
++ gcvFEATURE_DECOMPRESS_Z16,
++ gcvFEATURE_LINEAR_RENDER_TARGET,
++ gcvFEATURE_BUG_FIXES8,
++ gcvFEATURE_HALTI2,
++}
++gceFEATURE;
++
++/* Chip Power Status. */
++typedef enum _gceCHIPPOWERSTATE
++{
++ gcvPOWER_ON = 0,
++ gcvPOWER_OFF,
++ gcvPOWER_IDLE,
++ gcvPOWER_SUSPEND,
++ gcvPOWER_SUSPEND_ATPOWERON,
++ gcvPOWER_OFF_ATPOWERON,
++ gcvPOWER_IDLE_BROADCAST,
++ gcvPOWER_SUSPEND_BROADCAST,
++ gcvPOWER_OFF_BROADCAST,
++ gcvPOWER_OFF_RECOVERY,
++ gcvPOWER_OFF_TIMEOUT,
++ gcvPOWER_ON_AUTO
++}
++gceCHIPPOWERSTATE;
++
++/* CPU cache operations */
++typedef enum _gceCACHEOPERATION
++{
++ gcvCACHE_CLEAN = 0x01,
++ gcvCACHE_INVALIDATE = 0x02,
++ gcvCACHE_FLUSH = gcvCACHE_CLEAN | gcvCACHE_INVALIDATE,
++ gcvCACHE_MEMORY_BARRIER = 0x04
++}
++gceCACHEOPERATION;
++
++/* Surface types. */
++typedef enum _gceSURF_TYPE
++{
++ gcvSURF_TYPE_UNKNOWN = 0,
++ gcvSURF_INDEX,
++ gcvSURF_VERTEX,
++ gcvSURF_TEXTURE,
++ gcvSURF_RENDER_TARGET,
++ gcvSURF_DEPTH,
++ gcvSURF_BITMAP,
++ gcvSURF_TILE_STATUS,
++ gcvSURF_IMAGE,
++ gcvSURF_MASK,
++ gcvSURF_SCISSOR,
++ gcvSURF_HIERARCHICAL_DEPTH,
++ gcvSURF_NUM_TYPES, /* Make sure this is the last one! */
++
++ /* Combinations. */
++ gcvSURF_NO_TILE_STATUS = 0x100,
++ gcvSURF_NO_VIDMEM = 0x200, /* Used to allocate surfaces with no underlying vidmem node.
++ In Android, vidmem node is allocated by another process. */
++ gcvSURF_CACHEABLE = 0x400, /* Used to allocate a cacheable surface */
++ gcvSURF_FLIP = 0x800, /* The Resolve Target the will been flip resolve from RT */
++ gcvSURF_TILE_STATUS_DIRTY = 0x1000, /* Init tile status to all dirty */
++
++ gcvSURF_LINEAR = 0x2000,
++
++ gcvSURF_TEXTURE_LINEAR = gcvSURF_TEXTURE
++ | gcvSURF_LINEAR,
++
++ gcvSURF_RENDER_TARGET_NO_TILE_STATUS = gcvSURF_RENDER_TARGET
++ | gcvSURF_NO_TILE_STATUS,
++
++ gcvSURF_RENDER_TARGET_TS_DIRTY = gcvSURF_RENDER_TARGET
++ | gcvSURF_TILE_STATUS_DIRTY,
++
++ gcvSURF_DEPTH_NO_TILE_STATUS = gcvSURF_DEPTH
++ | gcvSURF_NO_TILE_STATUS,
++
++ gcvSURF_DEPTH_TS_DIRTY = gcvSURF_DEPTH
++ | gcvSURF_TILE_STATUS_DIRTY,
++
++ /* Supported surface types with no vidmem node. */
++ gcvSURF_BITMAP_NO_VIDMEM = gcvSURF_BITMAP
++ | gcvSURF_NO_VIDMEM,
++
++ gcvSURF_TEXTURE_NO_VIDMEM = gcvSURF_TEXTURE
++ | gcvSURF_NO_VIDMEM,
++
++ /* Cacheable surface types with no vidmem node. */
++ gcvSURF_CACHEABLE_BITMAP_NO_VIDMEM = gcvSURF_BITMAP_NO_VIDMEM
++ | gcvSURF_CACHEABLE,
++
++ gcvSURF_CACHEABLE_BITMAP = gcvSURF_BITMAP
++ | gcvSURF_CACHEABLE,
++
++ gcvSURF_FLIP_BITMAP = gcvSURF_BITMAP
++ | gcvSURF_FLIP,
++}
++gceSURF_TYPE;
++
++typedef enum _gceSURF_USAGE
++{
++ gcvSURF_USAGE_UNKNOWN,
++ gcvSURF_USAGE_RESOLVE_AFTER_CPU,
++ gcvSURF_USAGE_RESOLVE_AFTER_3D
++}
++gceSURF_USAGE;
++
++typedef enum _gceSURF_COLOR_TYPE
++{
++ gcvSURF_COLOR_UNKNOWN = 0,
++ gcvSURF_COLOR_LINEAR = 0x01,
++ gcvSURF_COLOR_ALPHA_PRE = 0x02,
++}
++gceSURF_COLOR_TYPE;
++
++/* Rotation. */
++typedef enum _gceSURF_ROTATION
++{
++ gcvSURF_0_DEGREE = 0,
++ gcvSURF_90_DEGREE,
++ gcvSURF_180_DEGREE,
++ gcvSURF_270_DEGREE,
++ gcvSURF_FLIP_X,
++ gcvSURF_FLIP_Y,
++
++ gcvSURF_POST_FLIP_X = 0x40000000,
++ gcvSURF_POST_FLIP_Y = 0x80000000,
++}
++gceSURF_ROTATION;
++
++typedef enum _gceMIPMAP_IMAGE_FORMAT
++{
++ gcvUNKNOWN_MIPMAP_IMAGE_FORMAT = -2
++}
++gceMIPMAP_IMAGE_FORMAT;
++
++
++/* Surface formats. */
++typedef enum _gceSURF_FORMAT
++{
++ /* Unknown format. */
++ gcvSURF_UNKNOWN = 0,
++
++ /* Palettized formats. */
++ gcvSURF_INDEX1 = 100,
++ gcvSURF_INDEX4,
++ gcvSURF_INDEX8,
++
++ /* RGB formats. */
++ gcvSURF_A2R2G2B2 = 200,
++ gcvSURF_R3G3B2,
++ gcvSURF_A8R3G3B2,
++ gcvSURF_X4R4G4B4,
++ gcvSURF_A4R4G4B4,
++ gcvSURF_R4G4B4A4,
++ gcvSURF_X1R5G5B5,
++ gcvSURF_A1R5G5B5,
++ gcvSURF_R5G5B5A1,
++ gcvSURF_R5G6B5,
++ gcvSURF_R8G8B8,
++ gcvSURF_X8R8G8B8,
++ gcvSURF_A8R8G8B8,
++ gcvSURF_R8G8B8A8,
++ gcvSURF_G8R8G8B8,
++ gcvSURF_R8G8B8G8,
++ gcvSURF_X2R10G10B10,
++ gcvSURF_A2R10G10B10,
++ gcvSURF_X12R12G12B12,
++ gcvSURF_A12R12G12B12,
++ gcvSURF_X16R16G16B16,
++ gcvSURF_A16R16G16B16,
++ gcvSURF_A32R32G32B32,
++ gcvSURF_R8G8B8X8,
++ gcvSURF_R5G5B5X1,
++ gcvSURF_R4G4B4X4,
++
++ /* BGR formats. */
++ gcvSURF_A4B4G4R4 = 300,
++ gcvSURF_A1B5G5R5,
++ gcvSURF_B5G6R5,
++ gcvSURF_B8G8R8,
++ gcvSURF_B16G16R16,
++ gcvSURF_X8B8G8R8,
++ gcvSURF_A8B8G8R8,
++ gcvSURF_A2B10G10R10,
++ gcvSURF_X16B16G16R16,
++ gcvSURF_A16B16G16R16,
++ gcvSURF_B32G32R32,
++ gcvSURF_X32B32G32R32,
++ gcvSURF_A32B32G32R32,
++ gcvSURF_B4G4R4A4,
++ gcvSURF_B5G5R5A1,
++ gcvSURF_B8G8R8X8,
++ gcvSURF_B8G8R8A8,
++ gcvSURF_X4B4G4R4,
++ gcvSURF_X1B5G5R5,
++ gcvSURF_B4G4R4X4,
++ gcvSURF_B5G5R5X1,
++ gcvSURF_X2B10G10R10,
++
++ /* Compressed formats. */
++ gcvSURF_DXT1 = 400,
++ gcvSURF_DXT2,
++ gcvSURF_DXT3,
++ gcvSURF_DXT4,
++ gcvSURF_DXT5,
++ gcvSURF_CXV8U8,
++ gcvSURF_ETC1,
++ gcvSURF_R11_EAC,
++ gcvSURF_SIGNED_R11_EAC,
++ gcvSURF_RG11_EAC,
++ gcvSURF_SIGNED_RG11_EAC,
++ gcvSURF_RGB8_ETC2,
++ gcvSURF_SRGB8_ETC2,
++ gcvSURF_RGB8_PUNCHTHROUGH_ALPHA1_ETC2,
++ gcvSURF_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2,
++ gcvSURF_RGBA8_ETC2_EAC,
++ gcvSURF_SRGB8_ALPHA8_ETC2_EAC,
++
++ /* YUV formats. */
++ gcvSURF_YUY2 = 500,
++ gcvSURF_UYVY,
++ gcvSURF_YV12,
++ gcvSURF_I420,
++ gcvSURF_NV12,
++ gcvSURF_NV21,
++ gcvSURF_NV16,
++ gcvSURF_NV61,
++ gcvSURF_YVYU,
++ gcvSURF_VYUY,
++
++ /* Depth formats. */
++ gcvSURF_D16 = 600,
++ gcvSURF_D24S8,
++ gcvSURF_D32,
++ gcvSURF_D24X8,
++
++ /* Alpha formats. */
++ gcvSURF_A4 = 700,
++ gcvSURF_A8,
++ gcvSURF_A12,
++ gcvSURF_A16,
++ gcvSURF_A32,
++ gcvSURF_A1,
++
++ /* Luminance formats. */
++ gcvSURF_L4 = 800,
++ gcvSURF_L8,
++ gcvSURF_L12,
++ gcvSURF_L16,
++ gcvSURF_L32,
++ gcvSURF_L1,
++
++ /* Alpha/Luminance formats. */
++ gcvSURF_A4L4 = 900,
++ gcvSURF_A2L6,
++ gcvSURF_A8L8,
++ gcvSURF_A4L12,
++ gcvSURF_A12L12,
++ gcvSURF_A16L16,
++
++ /* Bump formats. */
++ gcvSURF_L6V5U5 = 1000,
++ gcvSURF_V8U8,
++ gcvSURF_X8L8V8U8,
++ gcvSURF_Q8W8V8U8,
++ gcvSURF_A2W10V10U10,
++ gcvSURF_V16U16,
++ gcvSURF_Q16W16V16U16,
++
++ /* R/RG/RA formats. */
++ gcvSURF_R8 = 1100,
++ gcvSURF_X8R8,
++ gcvSURF_G8R8,
++ gcvSURF_X8G8R8,
++ gcvSURF_A8R8,
++ gcvSURF_R16,
++ gcvSURF_X16R16,
++ gcvSURF_G16R16,
++ gcvSURF_X16G16R16,
++ gcvSURF_A16R16,
++ gcvSURF_R32,
++ gcvSURF_X32R32,
++ gcvSURF_G32R32,
++ gcvSURF_X32G32R32,
++ gcvSURF_A32R32,
++ gcvSURF_RG16,
++
++ /* Floating point formats. */
++ gcvSURF_R16F = 1200,
++ gcvSURF_X16R16F,
++ gcvSURF_G16R16F,
++ gcvSURF_X16G16R16F,
++ gcvSURF_B16G16R16F,
++ gcvSURF_X16B16G16R16F,
++ gcvSURF_A16B16G16R16F,
++ gcvSURF_R32F,
++ gcvSURF_X32R32F,
++ gcvSURF_G32R32F,
++ gcvSURF_X32G32R32F,
++ gcvSURF_B32G32R32F,
++ gcvSURF_X32B32G32R32F,
++ gcvSURF_A32B32G32R32F,
++ gcvSURF_A16F,
++ gcvSURF_L16F,
++ gcvSURF_A16L16F,
++ gcvSURF_A16R16F,
++ gcvSURF_A32F,
++ gcvSURF_L32F,
++ gcvSURF_A32L32F,
++ gcvSURF_A32R32F,
++
++}
++gceSURF_FORMAT;
++
++/* Pixel swizzle modes. */
++typedef enum _gceSURF_SWIZZLE
++{
++ gcvSURF_NOSWIZZLE = 0,
++ gcvSURF_ARGB,
++ gcvSURF_ABGR,
++ gcvSURF_RGBA,
++ gcvSURF_BGRA
++}
++gceSURF_SWIZZLE;
++
++/* Transparency modes. */
++typedef enum _gceSURF_TRANSPARENCY
++{
++ /* Valid only for PE 1.0 */
++ gcvSURF_OPAQUE = 0,
++ gcvSURF_SOURCE_MATCH,
++ gcvSURF_SOURCE_MASK,
++ gcvSURF_PATTERN_MASK,
++}
++gceSURF_TRANSPARENCY;
++
++/* Surface Alignment. */
++typedef enum _gceSURF_ALIGNMENT
++{
++ gcvSURF_FOUR = 0,
++ gcvSURF_SIXTEEN,
++ gcvSURF_SUPER_TILED,
++ gcvSURF_SPLIT_TILED,
++ gcvSURF_SPLIT_SUPER_TILED,
++}
++gceSURF_ALIGNMENT;
++
++
++/* Surface Addressing. */
++typedef enum _gceSURF_ADDRESSING
++{
++ gcvSURF_NO_STRIDE_TILED = 0,
++ gcvSURF_NO_STRIDE_LINEAR,
++ gcvSURF_STRIDE_TILED,
++ gcvSURF_STRIDE_LINEAR
++}
++gceSURF_ADDRESSING;
++
++/* Transparency modes. */
++typedef enum _gce2D_TRANSPARENCY
++{
++ /* Valid only for PE 2.0 */
++ gcv2D_OPAQUE = 0,
++ gcv2D_KEYED,
++ gcv2D_MASKED
++}
++gce2D_TRANSPARENCY;
++
++/* Mono packing modes. */
++typedef enum _gceSURF_MONOPACK
++{
++ gcvSURF_PACKED8 = 0,
++ gcvSURF_PACKED16,
++ gcvSURF_PACKED32,
++ gcvSURF_UNPACKED,
++}
++gceSURF_MONOPACK;
++
++/* Blending modes. */
++typedef enum _gceSURF_BLEND_MODE
++{
++ /* Porter-Duff blending modes. */
++ /* Fsrc Fdst */
++ gcvBLEND_CLEAR = 0, /* 0 0 */
++ gcvBLEND_SRC, /* 1 0 */
++ gcvBLEND_DST, /* 0 1 */
++ gcvBLEND_SRC_OVER_DST, /* 1 1 - Asrc */
++ gcvBLEND_DST_OVER_SRC, /* 1 - Adst 1 */
++ gcvBLEND_SRC_IN_DST, /* Adst 0 */
++ gcvBLEND_DST_IN_SRC, /* 0 Asrc */
++ gcvBLEND_SRC_OUT_DST, /* 1 - Adst 0 */
++ gcvBLEND_DST_OUT_SRC, /* 0 1 - Asrc */
++ gcvBLEND_SRC_ATOP_DST, /* Adst 1 - Asrc */
++ gcvBLEND_DST_ATOP_SRC, /* 1 - Adst Asrc */
++ gcvBLEND_SRC_XOR_DST, /* 1 - Adst 1 - Asrc */
++
++ /* Special blending modes. */
++ gcvBLEND_SET, /* DST = 1 */
++ gcvBLEND_SUB /* DST = DST * (1 - SRC) */
++}
++gceSURF_BLEND_MODE;
++
++/* Per-pixel alpha modes. */
++typedef enum _gceSURF_PIXEL_ALPHA_MODE
++{
++ gcvSURF_PIXEL_ALPHA_STRAIGHT = 0,
++ gcvSURF_PIXEL_ALPHA_INVERSED
++}
++gceSURF_PIXEL_ALPHA_MODE;
++
++/* Global alpha modes. */
++typedef enum _gceSURF_GLOBAL_ALPHA_MODE
++{
++ gcvSURF_GLOBAL_ALPHA_OFF = 0,
++ gcvSURF_GLOBAL_ALPHA_ON,
++ gcvSURF_GLOBAL_ALPHA_SCALE
++}
++gceSURF_GLOBAL_ALPHA_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gceSURF_PIXEL_COLOR_MODE
++{
++ gcvSURF_COLOR_STRAIGHT = 0,
++ gcvSURF_COLOR_MULTIPLY
++}
++gceSURF_PIXEL_COLOR_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gce2D_PIXEL_COLOR_MULTIPLY_MODE
++{
++ gcv2D_COLOR_MULTIPLY_DISABLE = 0,
++ gcv2D_COLOR_MULTIPLY_ENABLE
++}
++gce2D_PIXEL_COLOR_MULTIPLY_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gce2D_GLOBAL_COLOR_MULTIPLY_MODE
++{
++ gcv2D_GLOBAL_COLOR_MULTIPLY_DISABLE = 0,
++ gcv2D_GLOBAL_COLOR_MULTIPLY_ALPHA,
++ gcv2D_GLOBAL_COLOR_MULTIPLY_COLOR
++}
++gce2D_GLOBAL_COLOR_MULTIPLY_MODE;
++
++/* Alpha blending factor modes. */
++typedef enum _gceSURF_BLEND_FACTOR_MODE
++{
++ gcvSURF_BLEND_ZERO = 0,
++ gcvSURF_BLEND_ONE,
++ gcvSURF_BLEND_STRAIGHT,
++ gcvSURF_BLEND_INVERSED,
++ gcvSURF_BLEND_COLOR,
++ gcvSURF_BLEND_COLOR_INVERSED,
++ gcvSURF_BLEND_SRC_ALPHA_SATURATED,
++ gcvSURF_BLEND_STRAIGHT_NO_CROSS,
++ gcvSURF_BLEND_INVERSED_NO_CROSS,
++ gcvSURF_BLEND_COLOR_NO_CROSS,
++ gcvSURF_BLEND_COLOR_INVERSED_NO_CROSS,
++ gcvSURF_BLEND_SRC_ALPHA_SATURATED_CROSS
++}
++gceSURF_BLEND_FACTOR_MODE;
++
++/* Alpha blending porter duff rules. */
++typedef enum _gce2D_PORTER_DUFF_RULE
++{
++ gcvPD_CLEAR = 0,
++ gcvPD_SRC,
++ gcvPD_SRC_OVER,
++ gcvPD_DST_OVER,
++ gcvPD_SRC_IN,
++ gcvPD_DST_IN,
++ gcvPD_SRC_OUT,
++ gcvPD_DST_OUT,
++ gcvPD_SRC_ATOP,
++ gcvPD_DST_ATOP,
++ gcvPD_ADD,
++ gcvPD_XOR,
++ gcvPD_DST
++}
++gce2D_PORTER_DUFF_RULE;
++
++/* Alpha blending factor modes. */
++typedef enum _gce2D_YUV_COLOR_MODE
++{
++ gcv2D_YUV_601= 0,
++ gcv2D_YUV_709,
++ gcv2D_YUV_USER_DEFINED,
++ gcv2D_YUV_USER_DEFINED_CLAMP,
++
++ /* Default setting is for src. gcv2D_YUV_DST
++ can be ORed to set dst.
++ */
++ gcv2D_YUV_DST = 0x80000000,
++}
++gce2D_YUV_COLOR_MODE;
++
++typedef enum _gce2D_COMMAND
++{
++ gcv2D_CLEAR = 0,
++ gcv2D_LINE,
++ gcv2D_BLT,
++ gcv2D_STRETCH,
++ gcv2D_HOR_FILTER,
++ gcv2D_VER_FILTER,
++ gcv2D_MULTI_SOURCE_BLT,
++}
++gce2D_COMMAND;
++
++typedef enum _gce2D_TILE_STATUS_CONFIG
++{
++ gcv2D_TSC_DISABLE = 0,
++ gcv2D_TSC_ENABLE = 0x00000001,
++ gcv2D_TSC_COMPRESSED = 0x00000002,
++ gcv2D_TSC_DOWN_SAMPLER = 0x00000004,
++ gcv2D_TSC_2D_COMPRESSED = 0x00000008,
++}
++gce2D_TILE_STATUS_CONFIG;
++
++typedef enum _gce2D_QUERY
++{
++ gcv2D_QUERY_RGB_ADDRESS_MIN_ALIGN = 0,
++ gcv2D_QUERY_RGB_STRIDE_MIN_ALIGN,
++ gcv2D_QUERY_YUV_ADDRESS_MIN_ALIGN,
++ gcv2D_QUERY_YUV_STRIDE_MIN_ALIGN,
++}
++gce2D_QUERY;
++
++typedef enum _gce2D_SUPER_TILE_VERSION
++{
++ gcv2D_SUPER_TILE_VERSION_V1 = 1,
++ gcv2D_SUPER_TILE_VERSION_V2 = 2,
++ gcv2D_SUPER_TILE_VERSION_V3 = 3,
++}
++gce2D_SUPER_TILE_VERSION;
++
++typedef enum _gce2D_STATE
++{
++ gcv2D_STATE_SPECIAL_FILTER_MIRROR_MODE = 1,
++ gcv2D_STATE_SUPER_TILE_VERSION,
++ gcv2D_STATE_EN_GAMMA,
++ gcv2D_STATE_DE_GAMMA,
++ gcv2D_STATE_MULTI_SRC_BLIT_UNIFIED_DST_RECT,
++
++ gcv2D_STATE_ARRAY_EN_GAMMA = 0x10001,
++ gcv2D_STATE_ARRAY_DE_GAMMA,
++ gcv2D_STATE_ARRAY_CSC_YUV_TO_RGB,
++ gcv2D_STATE_ARRAY_CSC_RGB_TO_YUV,
++}
++gce2D_STATE;
++
++#ifndef VIVANTE_NO_3D
++/* Texture functions. */
++typedef enum _gceTEXTURE_FUNCTION
++{
++ gcvTEXTURE_DUMMY = 0,
++ gcvTEXTURE_REPLACE = 0,
++ gcvTEXTURE_MODULATE,
++ gcvTEXTURE_ADD,
++ gcvTEXTURE_ADD_SIGNED,
++ gcvTEXTURE_INTERPOLATE,
++ gcvTEXTURE_SUBTRACT,
++ gcvTEXTURE_DOT3
++}
++gceTEXTURE_FUNCTION;
++
++/* Texture sources. */
++typedef enum _gceTEXTURE_SOURCE
++{
++ gcvCOLOR_FROM_TEXTURE = 0,
++ gcvCOLOR_FROM_CONSTANT_COLOR,
++ gcvCOLOR_FROM_PRIMARY_COLOR,
++ gcvCOLOR_FROM_PREVIOUS_COLOR
++}
++gceTEXTURE_SOURCE;
++
++/* Texture source channels. */
++typedef enum _gceTEXTURE_CHANNEL
++{
++ gcvFROM_COLOR = 0,
++ gcvFROM_ONE_MINUS_COLOR,
++ gcvFROM_ALPHA,
++ gcvFROM_ONE_MINUS_ALPHA
++}
++gceTEXTURE_CHANNEL;
++#endif /* VIVANTE_NO_3D */
++
++/* Filter types. */
++typedef enum _gceFILTER_TYPE
++{
++ gcvFILTER_SYNC = 0,
++ gcvFILTER_BLUR,
++ gcvFILTER_USER
++}
++gceFILTER_TYPE;
++
++/* Filter pass types. */
++typedef enum _gceFILTER_PASS_TYPE
++{
++ gcvFILTER_HOR_PASS = 0,
++ gcvFILTER_VER_PASS
++}
++gceFILTER_PASS_TYPE;
++
++/* Endian hints. */
++typedef enum _gceENDIAN_HINT
++{
++ gcvENDIAN_NO_SWAP = 0,
++ gcvENDIAN_SWAP_WORD,
++ gcvENDIAN_SWAP_DWORD
++}
++gceENDIAN_HINT;
++
++/* Tiling modes. */
++typedef enum _gceTILING
++{
++ gcvLINEAR = 0,
++ gcvTILED,
++ gcvSUPERTILED,
++ gcvMULTI_TILED,
++ gcvMULTI_SUPERTILED,
++ gcvMINORTILED,
++}
++gceTILING;
++
++/* 2D pattern type. */
++typedef enum _gce2D_PATTERN
++{
++ gcv2D_PATTERN_SOLID = 0,
++ gcv2D_PATTERN_MONO,
++ gcv2D_PATTERN_COLOR,
++ gcv2D_PATTERN_INVALID
++}
++gce2D_PATTERN;
++
++/* 2D source type. */
++typedef enum _gce2D_SOURCE
++{
++ gcv2D_SOURCE_MASKED = 0,
++ gcv2D_SOURCE_MONO,
++ gcv2D_SOURCE_COLOR,
++ gcv2D_SOURCE_INVALID
++}
++gce2D_SOURCE;
++
++/* Pipes. */
++typedef enum _gcePIPE_SELECT
++{
++ gcvPIPE_INVALID = ~0,
++ gcvPIPE_3D = 0,
++ gcvPIPE_2D
++}
++gcePIPE_SELECT;
++
++/* Hardware type. */
++typedef enum _gceHARDWARE_TYPE
++{
++ gcvHARDWARE_INVALID = 0x00,
++ gcvHARDWARE_3D = 0x01,
++ gcvHARDWARE_2D = 0x02,
++ gcvHARDWARE_VG = 0x04,
++
++ gcvHARDWARE_3D2D = gcvHARDWARE_3D | gcvHARDWARE_2D
++}
++gceHARDWARE_TYPE;
++
++#define gcdCHIP_COUNT 3
++
++typedef enum _gceMMU_MODE
++{
++ gcvMMU_MODE_1K,
++ gcvMMU_MODE_4K,
++} gceMMU_MODE;
++
++/* User signal command codes. */
++typedef enum _gceUSER_SIGNAL_COMMAND_CODES
++{
++ gcvUSER_SIGNAL_CREATE,
++ gcvUSER_SIGNAL_DESTROY,
++ gcvUSER_SIGNAL_SIGNAL,
++ gcvUSER_SIGNAL_WAIT,
++ gcvUSER_SIGNAL_MAP,
++ gcvUSER_SIGNAL_UNMAP,
++}
++gceUSER_SIGNAL_COMMAND_CODES;
++
++/* Sync point command codes. */
++typedef enum _gceSYNC_POINT_COMMAND_CODES
++{
++ gcvSYNC_POINT_CREATE,
++ gcvSYNC_POINT_DESTROY,
++ gcvSYNC_POINT_SIGNAL,
++}
++gceSYNC_POINT_COMMAND_CODES;
++
++/* Event locations. */
++typedef enum _gceKERNEL_WHERE
++{
++ gcvKERNEL_COMMAND,
++ gcvKERNEL_VERTEX,
++ gcvKERNEL_TRIANGLE,
++ gcvKERNEL_TEXTURE,
++ gcvKERNEL_PIXEL,
++}
++gceKERNEL_WHERE;
++
++#if gcdENABLE_VG
++/* Hardware blocks. */
++typedef enum _gceBLOCK
++{
++ gcvBLOCK_COMMAND,
++ gcvBLOCK_TESSELLATOR,
++ gcvBLOCK_TESSELLATOR2,
++ gcvBLOCK_TESSELLATOR3,
++ gcvBLOCK_RASTER,
++ gcvBLOCK_VG,
++ gcvBLOCK_VG2,
++ gcvBLOCK_VG3,
++ gcvBLOCK_PIXEL,
++
++ /* Number of defined blocks. */
++ gcvBLOCK_COUNT
++}
++gceBLOCK;
++#endif
++
++/* gcdDUMP message type. */
++typedef enum _gceDEBUG_MESSAGE_TYPE
++{
++ gcvMESSAGE_TEXT,
++ gcvMESSAGE_DUMP
++}
++gceDEBUG_MESSAGE_TYPE;
++
++typedef enum _gceSPECIAL_HINT
++{
++ gceSPECIAL_HINT0,
++ gceSPECIAL_HINT1,
++ gceSPECIAL_HINT2,
++ gceSPECIAL_HINT3,
++ /* For disable dynamic stream/index */
++ gceSPECIAL_HINT4
++}
++gceSPECIAL_HINT;
++
++typedef enum _gceMACHINECODE
++{
++ gcvMACHINECODE_HOVERJET0 = 0x0,
++ gcvMACHINECODE_HOVERJET1 ,
++
++ gcvMACHINECODE_TAIJI0 ,
++ gcvMACHINECODE_TAIJI1 ,
++ gcvMACHINECODE_TAIJI2 ,
++
++ gcvMACHINECODE_ANTUTU0 ,
++
++ gcvMACHINECODE_GLB27_RELEASE_0,
++ gcvMACHINECODE_GLB27_RELEASE_1,
++
++ gcvMACHINECODE_WAVESCAPE0 ,
++ gcvMACHINECODE_WAVESCAPE1 ,
++
++ gcvMACHINECODE_NENAMARKV2_4_0 ,
++ gcvMACHINECODE_NENAMARKV2_4_1 ,
++
++ gcvMACHINECODE_GLB25_RELEASE_0,
++ gcvMACHINECODE_GLB25_RELEASE_1,
++ gcvMACHINECODE_GLB25_RELEASE_2,
++}
++gceMACHINECODE;
++
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gckCONTEXT * gckCONTEXT;
++typedef struct _gcoCMDBUF * gcoCMDBUF;
++typedef struct _gcsSTATE_DELTA * gcsSTATE_DELTA_PTR;
++typedef struct _gcsQUEUE * gcsQUEUE_PTR;
++typedef struct _gcoQUEUE * gcoQUEUE;
++typedef struct _gcsHAL_INTERFACE * gcsHAL_INTERFACE_PTR;
++typedef struct _gcs2D_PROFILE * gcs2D_PROFILE_PTR;
++
++#if gcdENABLE_VG
++typedef struct _gcoVGHARDWARE * gcoVGHARDWARE;
++typedef struct _gcoVGBUFFER * gcoVGBUFFER;
++typedef struct _gckVGHARDWARE * gckVGHARDWARE;
++typedef struct _gcsVGCONTEXT * gcsVGCONTEXT_PTR;
++typedef struct _gcsVGCONTEXT_MAP * gcsVGCONTEXT_MAP_PTR;
++typedef struct _gcsVGCMDQUEUE * gcsVGCMDQUEUE_PTR;
++typedef struct _gcsTASK_MASTER_TABLE * gcsTASK_MASTER_TABLE_PTR;
++typedef struct _gckVGKERNEL * gckVGKERNEL;
++typedef void * gctTHREAD;
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_enum_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h 2014-05-15 20:33:58.606018247 +0200
+@@ -0,0 +1,2652 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_h_
++#define __gc_hal_h_
++
++#include "gc_hal_rename.h"
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++#include "gc_hal_base.h"
++#include "gc_hal_profiler.h"
++#include "gc_hal_driver.h"
++#ifndef VIVANTE_NO_3D
++#include "gc_hal_statistics.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* Alignment Macros *******************************
++\******************************************************************************/
++
++#define gcmALIGN(n, align) \
++( \
++ ((n) + ((align) - 1)) & ~((align) - 1) \
++)
++
++#define gcmALIGN_BASE(n, align) \
++( \
++ ((n) & ~((align) - 1)) \
++)
++
++/******************************************************************************\
++***************************** Element Count Macro *****************************
++\******************************************************************************/
++
++#define gcmSIZEOF(a) \
++( \
++ (gctSIZE_T) (sizeof(a)) \
++)
++
++#define gcmCOUNTOF(a) \
++( \
++ sizeof(a) / sizeof(a[0]) \
++)
++
++/******************************************************************************\
++********************************* Cast Macro **********************************
++\******************************************************************************/
++#define gcmNAME_TO_PTR(na) \
++ gckKERNEL_QueryPointerFromName(kernel, gcmALL_TO_UINT32(na))
++
++#define gcmPTR_TO_NAME(ptr) \
++ gckKERNEL_AllocateNameFromPointer(kernel, ptr)
++
++#define gcmRELEASE_NAME(na) \
++ gckKERNEL_DeleteName(kernel, gcmALL_TO_UINT32(na))
++
++#ifdef __LP64__
++
++#define gcmALL_TO_UINT32(t) \
++( \
++ (gctUINT32) (gctUINTPTR_T) (t)\
++)
++
++#define gcmPTR_TO_UINT64(p) \
++( \
++ (gctUINT64) (p)\
++)
++
++#define gcmUINT64_TO_PTR(u) \
++( \
++ (gctPOINTER) (u)\
++)
++
++#else /* 32 bit */
++
++#define gcmALL_TO_UINT32(t) \
++( \
++ (gctUINT32) (t)\
++)
++
++#define gcmPTR_TO_UINT64(p) \
++( \
++ (gctUINT64) (gctUINTPTR_T) (p)\
++)
++
++#define gcmUINT64_TO_PTR(u) \
++( \
++ (gctPOINTER) (gctUINTPTR_T) (u)\
++)
++
++#endif
++
++#define gcmUINT64_TO_TYPE(u, t) \
++( \
++ (t) (gctUINTPTR_T) (u)\
++)
++
++/******************************************************************************\
++******************************** Useful Macro *********************************
++\******************************************************************************/
++
++#define gcvINVALID_ADDRESS ~0U
++
++#define gcmGET_PRE_ROTATION(rotate) \
++ ((rotate) & (~(gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y)))
++
++#define gcmGET_POST_ROTATION(rotate) \
++ ((rotate) & (gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y))
++
++/******************************************************************************\
++******************************** gcsOBJECT Object *******************************
++\******************************************************************************/
++
++/* Type of objects. */
++typedef enum _gceOBJECT_TYPE
++{
++ gcvOBJ_UNKNOWN = 0,
++ gcvOBJ_2D = gcmCC('2','D',' ',' '),
++ gcvOBJ_3D = gcmCC('3','D',' ',' '),
++ gcvOBJ_ATTRIBUTE = gcmCC('A','T','T','R'),
++ gcvOBJ_BRUSHCACHE = gcmCC('B','R','U','$'),
++ gcvOBJ_BRUSHNODE = gcmCC('B','R','U','n'),
++ gcvOBJ_BRUSH = gcmCC('B','R','U','o'),
++ gcvOBJ_BUFFER = gcmCC('B','U','F','R'),
++ gcvOBJ_COMMAND = gcmCC('C','M','D',' '),
++ gcvOBJ_COMMANDBUFFER = gcmCC('C','M','D','B'),
++ gcvOBJ_CONTEXT = gcmCC('C','T','X','T'),
++ gcvOBJ_DEVICE = gcmCC('D','E','V',' '),
++ gcvOBJ_DUMP = gcmCC('D','U','M','P'),
++ gcvOBJ_EVENT = gcmCC('E','V','N','T'),
++ gcvOBJ_FUNCTION = gcmCC('F','U','N','C'),
++ gcvOBJ_HAL = gcmCC('H','A','L',' '),
++ gcvOBJ_HARDWARE = gcmCC('H','A','R','D'),
++ gcvOBJ_HEAP = gcmCC('H','E','A','P'),
++ gcvOBJ_INDEX = gcmCC('I','N','D','X'),
++ gcvOBJ_INTERRUPT = gcmCC('I','N','T','R'),
++ gcvOBJ_KERNEL = gcmCC('K','E','R','N'),
++ gcvOBJ_KERNEL_FUNCTION = gcmCC('K','F','C','N'),
++ gcvOBJ_MEMORYBUFFER = gcmCC('M','E','M','B'),
++ gcvOBJ_MMU = gcmCC('M','M','U',' '),
++ gcvOBJ_OS = gcmCC('O','S',' ',' '),
++ gcvOBJ_OUTPUT = gcmCC('O','U','T','P'),
++ gcvOBJ_PAINT = gcmCC('P','N','T',' '),
++ gcvOBJ_PATH = gcmCC('P','A','T','H'),
++ gcvOBJ_QUEUE = gcmCC('Q','U','E',' '),
++ gcvOBJ_SAMPLER = gcmCC('S','A','M','P'),
++ gcvOBJ_SHADER = gcmCC('S','H','D','R'),
++ gcvOBJ_STREAM = gcmCC('S','T','R','M'),
++ gcvOBJ_SURF = gcmCC('S','U','R','F'),
++ gcvOBJ_TEXTURE = gcmCC('T','X','T','R'),
++ gcvOBJ_UNIFORM = gcmCC('U','N','I','F'),
++ gcvOBJ_VARIABLE = gcmCC('V','A','R','I'),
++ gcvOBJ_VERTEX = gcmCC('V','R','T','X'),
++ gcvOBJ_VIDMEM = gcmCC('V','M','E','M'),
++ gcvOBJ_VG = gcmCC('V','G',' ',' '),
++}
++gceOBJECT_TYPE;
++
++/* gcsOBJECT object defintinon. */
++typedef struct _gcsOBJECT
++{
++ /* Type of an object. */
++ gceOBJECT_TYPE type;
++}
++gcsOBJECT;
++
++typedef struct _gckHARDWARE * gckHARDWARE;
++
++/* CORE flags. */
++typedef enum _gceCORE
++{
++ gcvCORE_MAJOR = 0x0,
++ gcvCORE_2D = 0x1,
++ gcvCORE_VG = 0x2
++}
++gceCORE;
++
++#define gcdMAX_GPU_COUNT 3
++
++/*******************************************************************************
++**
++** gcmVERIFY_OBJECT
++**
++** Assert if an object is invalid or is not of the specified type. If the
++** object is invalid or not of the specified type, gcvSTATUS_INVALID_OBJECT
++** will be returned from the current function. In retail mode this macro
++** does nothing.
++**
++** ARGUMENTS:
++**
++** obj Object to test.
++** t Expected type of the object.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++#define _gcmVERIFY_OBJECT(prefix, obj, t) \
++ if ((obj) == gcvNULL) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT failed: NULL"); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT((obj) != gcvNULL); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \
++ return gcvSTATUS_INVALID_OBJECT; \
++ } \
++ else if (((gcsOBJECT*) (obj))->type != t) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT failed: %c%c%c%c", \
++ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \
++ return gcvSTATUS_INVALID_OBJECT; \
++ }
++
++# define gcmVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcm, obj, t)
++# define gcmkVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcmk, obj, t)
++#else
++# define gcmVERIFY_OBJECT(obj, t) do {} while (gcvFALSE)
++# define gcmkVERIFY_OBJECT(obj, t) do {} while (gcvFALSE)
++#endif
++
++/******************************************************************************/
++/*VERIFY_OBJECT if special return expected*/
++/******************************************************************************/
++#ifndef EGL_API_ANDROID
++# define _gcmVERIFY_OBJECT_RETURN(prefix, obj, t, retVal) \
++ do \
++ { \
++ if ((obj) == gcvNULL) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT_RETURN failed: NULL"); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT((obj) != gcvNULL); \
++ prefix##FOOTER_ARG("retVal=%d", retVal); \
++ return retVal; \
++ } \
++ else if (((gcsOBJECT*) (obj))->type != t) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT_RETURN failed: %c%c%c%c", \
++ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \
++ prefix##FOOTER_ARG("retVal=%d", retVal); \
++ return retVal; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_OBJECT_RETURN(obj, t, retVal) \
++ _gcmVERIFY_OBJECT_RETURN(gcm, obj, t, retVal)
++# define gcmkVERIFY_OBJECT_RETURN(obj, t, retVal) \
++ _gcmVERIFY_OBJECT_RETURN(gcmk, obj, t, retVal)
++#else
++# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE)
++# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE)
++#endif
++
++/******************************************************************************\
++********************************** gckOS Object *********************************
++\******************************************************************************/
++
++/* Construct a new gckOS object. */
++gceSTATUS
++gckOS_Construct(
++ IN gctPOINTER Context,
++ OUT gckOS * Os
++ );
++
++/* Destroy an gckOS object. */
++gceSTATUS
++gckOS_Destroy(
++ IN gckOS Os
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gckOS_QueryVideoMemory(
++ IN gckOS Os,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Allocate memory from the heap. */
++gceSTATUS
++gckOS_Allocate(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free allocated memory. */
++gceSTATUS
++gckOS_Free(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Wrapper for allocation memory.. */
++gceSTATUS
++gckOS_AllocateMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Wrapper for freeing memory. */
++gceSTATUS
++gckOS_FreeMemory(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate paged memory. */
++gceSTATUS
++gckOS_AllocatePagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ );
++
++/* Allocate paged memory. */
++gceSTATUS
++gckOS_AllocatePagedMemoryEx(
++ IN gckOS Os,
++ IN gctBOOL Contiguous,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ );
++
++/* Lock pages. */
++gceSTATUS
++gckOS_LockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Cacheable,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ );
++
++/* Map pages. */
++gceSTATUS
++gckOS_MapPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++#ifdef __QNXNTO__
++ IN gctPOINTER Logical,
++#endif
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ );
++
++/* Map pages. */
++gceSTATUS
++gckOS_MapPagesEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPHYS_ADDR Physical,
++#ifdef __QNXNTO__
++ IN gctPOINTER Logical,
++#endif
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ );
++
++/* Unlock pages. */
++gceSTATUS
++gckOS_UnlockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Free paged memory. */
++gceSTATUS
++gckOS_FreePagedMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Allocate non-paged memory. */
++gceSTATUS
++gckOS_AllocateNonPagedMemory(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free non-paged memory. */
++gceSTATUS
++gckOS_FreeNonPagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++/* Allocate contiguous memory. */
++gceSTATUS
++gckOS_AllocateContiguous(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free contiguous memory. */
++gceSTATUS
++gckOS_FreeContiguous(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Get the number fo bytes per page. */
++gceSTATUS
++gckOS_GetPageSize(
++ IN gckOS Os,
++ OUT gctSIZE_T * PageSize
++ );
++
++/* Get the physical address of a corresponding logical address. */
++gceSTATUS
++gckOS_GetPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++/* Get the physical address of a corresponding logical address. */
++gceSTATUS
++gckOS_GetPhysicalAddressProcess(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32 * Address
++ );
++
++/* Map physical memory. */
++gceSTATUS
++gckOS_MapPhysical(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap previously mapped physical memory. */
++gceSTATUS
++gckOS_UnmapPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Read data from a hardware register. */
++gceSTATUS
++gckOS_ReadRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++/* Read data from a hardware register. */
++gceSTATUS
++gckOS_ReadRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++/* Write data to a hardware register. */
++gceSTATUS
++gckOS_WriteRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Write data to a hardware register. */
++gceSTATUS
++gckOS_WriteRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Write data to a 32-bit memory location. */
++gceSTATUS
++gckOS_WriteMemory(
++ IN gckOS Os,
++ IN gctPOINTER Address,
++ IN gctUINT32 Data
++ );
++
++/* Map physical memory into the process space. */
++gceSTATUS
++gckOS_MapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap physical memory from the specified process space. */
++gceSTATUS
++gckOS_UnmapMemoryEx(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical,
++ IN gctUINT32 PID
++ );
++
++/* Unmap physical memory from the process space. */
++gceSTATUS
++gckOS_UnmapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Unmap user logical memory out of physical memory.
++ * This function is only supported in Linux currently.
++ */
++gceSTATUS
++gckOS_UnmapUserLogical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Create a new mutex. */
++gceSTATUS
++gckOS_CreateMutex(
++ IN gckOS Os,
++ OUT gctPOINTER * Mutex
++ );
++
++/* Delete a mutex. */
++gceSTATUS
++gckOS_DeleteMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Acquire a mutex. */
++gceSTATUS
++gckOS_AcquireMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ );
++
++/* Release a mutex. */
++gceSTATUS
++gckOS_ReleaseMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Atomically exchange a pair of 32-bit values. */
++gceSTATUS
++gckOS_AtomicExchange(
++ IN gckOS Os,
++ IN OUT gctUINT32_PTR Target,
++ IN gctUINT32 NewValue,
++ OUT gctUINT32_PTR OldValue
++ );
++
++/* Atomically exchange a pair of pointers. */
++gceSTATUS
++gckOS_AtomicExchangePtr(
++ IN gckOS Os,
++ IN OUT gctPOINTER * Target,
++ IN gctPOINTER NewValue,
++ OUT gctPOINTER * OldValue
++ );
++
++#if gcdSMP
++gceSTATUS
++gckOS_AtomSetMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ );
++
++gceSTATUS
++gckOS_AtomClearMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ );
++#endif
++
++gceSTATUS
++gckOS_DumpCallStack(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_GetProcessNameByPid(
++ IN gctINT Pid,
++ IN gctSIZE_T Length,
++ OUT gctUINT8_PTR String
++ );
++
++
++
++/*******************************************************************************
++**
++** gckOS_AtomConstruct
++**
++** Create an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Atom
++** Pointer to a variable receiving the constructed atom.
++*/
++gceSTATUS
++gckOS_AtomConstruct(
++ IN gckOS Os,
++ OUT gctPOINTER * Atom
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomDestroy
++**
++** Destroy an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomDestroy(
++ IN gckOS Os,
++ OUT gctPOINTER Atom
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomGet
++**
++** Get the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the value of the atom.
++*/
++gceSTATUS
++gckOS_AtomGet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomSet
++**
++** Set the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** gctINT32 Value
++** The value of the atom.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ IN gctINT32 Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomIncrement
++**
++** Atomically increment the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomIncrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomDecrement
++**
++** Atomically decrement the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomDecrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/* Delay a number of microseconds. */
++gceSTATUS
++gckOS_Delay(
++ IN gckOS Os,
++ IN gctUINT32 Delay
++ );
++
++/* Get time in milliseconds. */
++gceSTATUS
++gckOS_GetTicks(
++ OUT gctUINT32_PTR Time
++ );
++
++/* Compare time value. */
++gceSTATUS
++gckOS_TicksAfter(
++ IN gctUINT32 Time1,
++ IN gctUINT32 Time2,
++ OUT gctBOOL_PTR IsAfter
++ );
++
++/* Get time in microseconds. */
++gceSTATUS
++gckOS_GetTime(
++ OUT gctUINT64_PTR Time
++ );
++
++/* Memory barrier. */
++gceSTATUS
++gckOS_MemoryBarrier(
++ IN gckOS Os,
++ IN gctPOINTER Address
++ );
++
++/* Map user pointer. */
++gceSTATUS
++gckOS_MapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Unmap user pointer. */
++gceSTATUS
++gckOS_UnmapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ IN gctPOINTER KernelPointer
++ );
++
++/*******************************************************************************
++**
++** gckOS_QueryNeedCopy
++**
++** Query whether the memory can be accessed or mapped directly or it has to be
++** copied.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID of the current process.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR NeedCopy
++** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or
++** gcvFALSE if the memory can be accessed or mapped dircetly.
++*/
++gceSTATUS
++gckOS_QueryNeedCopy(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ OUT gctBOOL_PTR NeedCopy
++ );
++
++/*******************************************************************************
++**
++** gckOS_CopyFromUserData
++**
++** Copy data from user to kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyFromUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ );
++
++/*******************************************************************************
++**
++** gckOS_CopyToUserData
++**
++** Copy data from kernel to user memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyToUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ );
++
++#ifdef __QNXNTO__
++/* Map user physical address. */
++gceSTATUS
++gckOS_MapUserPhysical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Phys,
++ OUT gctPOINTER * KernelPointer
++ );
++#endif
++
++gceSTATUS
++gckOS_SuspendInterrupt(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_ResumeInterrupt(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++/* Get the base address for the physical memory. */
++gceSTATUS
++gckOS_GetBaseAddress(
++ IN gckOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++/* Perform a memory copy. */
++gceSTATUS
++gckOS_MemCopy(
++ IN gctPOINTER Destination,
++ IN gctCONST_POINTER Source,
++ IN gctSIZE_T Bytes
++ );
++
++/* Zero memory. */
++gceSTATUS
++gckOS_ZeroMemory(
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Bytes
++ );
++
++/* Device I/O control to the kernel HAL layer. */
++gceSTATUS
++gckOS_DeviceControl(
++ IN gckOS Os,
++ IN gctBOOL FromUser,
++ IN gctUINT32 IoControlCode,
++ IN gctPOINTER InputBuffer,
++ IN gctSIZE_T InputBufferSize,
++ OUT gctPOINTER OutputBuffer,
++ IN gctSIZE_T OutputBufferSize
++ );
++
++/*******************************************************************************
++**
++** gckOS_GetProcessID
++**
++** Get current process ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ProcessID
++** Pointer to the variable that receives the process ID.
++*/
++gceSTATUS
++gckOS_GetProcessID(
++ OUT gctUINT32_PTR ProcessID
++ );
++
++gceSTATUS
++gckOS_GetCurrentProcessID(
++ OUT gctUINT32_PTR ProcessID
++ );
++
++/*******************************************************************************
++**
++** gckOS_GetThreadID
++**
++** Get current thread ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ThreadID
++** Pointer to the variable that receives the thread ID.
++*/
++gceSTATUS
++gckOS_GetThreadID(
++ OUT gctUINT32_PTR ThreadID
++ );
++
++/******************************************************************************\
++********************************** Signal Object *********************************
++\******************************************************************************/
++
++/* Create a signal. */
++gceSTATUS
++gckOS_CreateSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ );
++
++/* Destroy a signal. */
++gceSTATUS
++gckOS_DestroySignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Signal a signal. */
++gceSTATUS
++gckOS_Signal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ );
++
++/* Wait for a signal. */
++gceSTATUS
++gckOS_WaitSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ );
++
++/* Map a user signal to the kernel space. */
++gceSTATUS
++gckOS_MapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process,
++ OUT gctSIGNAL * MappedSignal
++ );
++
++/* Unmap a user signal */
++gceSTATUS
++gckOS_UnmapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Map user memory. */
++gceSTATUS
++gckOS_MapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gckOS_UnmapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ );
++
++/******************************************************************************\
++************************** Android Native Fence Sync ***************************
++\******************************************************************************/
++gceSTATUS
++gckOS_CreateSyncTimeline(
++ IN gckOS Os,
++ OUT gctHANDLE * Timeline
++ );
++
++gceSTATUS
++gckOS_DestroySyncTimeline(
++ IN gckOS Os,
++ IN gctHANDLE Timeline
++ );
++
++gceSTATUS
++gckOS_CreateSyncPoint(
++ IN gckOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ );
++
++gceSTATUS
++gckOS_ReferenceSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_DestroySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_SignalSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_QuerySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctBOOL_PTR State
++ );
++
++gceSTATUS
++gckOS_CreateNativeFence(
++ IN gckOS Os,
++ IN gctHANDLE Timeline,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ );
++
++#if !USE_NEW_LINUX_SIGNAL
++/* Create signal to be used in the user space. */
++gceSTATUS
++gckOS_CreateUserSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctINT * SignalID
++ );
++
++/* Destroy signal used in the user space. */
++gceSTATUS
++gckOS_DestroyUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID
++ );
++
++/* Wait for signal used in the user space. */
++gceSTATUS
++gckOS_WaitUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctUINT32 Wait
++ );
++
++/* Signal a signal used in the user space. */
++gceSTATUS
++gckOS_SignalUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctBOOL State
++ );
++#endif /* USE_NEW_LINUX_SIGNAL */
++
++/* Set a signal owned by a process. */
++#if defined(__QNXNTO__)
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctINT Recvid,
++ IN gctINT Coid
++ );
++#else
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process
++ );
++#endif
++
++/******************************************************************************\
++** Cache Support
++*/
++
++gceSTATUS
++gckOS_CacheClean(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctPOINTER Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CacheFlush(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctPOINTER Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CacheInvalidate(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctPOINTER Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++/******************************************************************************\
++** Debug Support
++*/
++
++void
++gckOS_SetDebugLevel(
++ IN gctUINT32 Level
++ );
++
++void
++gckOS_SetDebugZone(
++ IN gctUINT32 Zone
++ );
++
++void
++gckOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ );
++
++void
++gckOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ );
++
++void
++gckOS_SetDebugFile(
++ IN gctCONST_STRING FileName
++ );
++
++/*******************************************************************************
++** Broadcast interface.
++*/
++
++typedef enum _gceBROADCAST
++{
++ /* GPU might be idle. */
++ gcvBROADCAST_GPU_IDLE,
++
++ /* A commit is going to happen. */
++ gcvBROADCAST_GPU_COMMIT,
++
++ /* GPU seems to be stuck. */
++ gcvBROADCAST_GPU_STUCK,
++
++ /* First process gets attached. */
++ gcvBROADCAST_FIRST_PROCESS,
++
++ /* Last process gets detached. */
++ gcvBROADCAST_LAST_PROCESS,
++
++ /* AXI bus error. */
++ gcvBROADCAST_AXI_BUS_ERROR,
++}
++gceBROADCAST;
++
++gceSTATUS
++gckOS_Broadcast(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gceBROADCAST Reason
++ );
++
++gceSTATUS
++gckOS_BroadcastHurry(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Urgency
++ );
++
++gceSTATUS
++gckOS_BroadcastCalibrateSpeed(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Idle,
++ IN gctUINT Time
++ );
++
++/*******************************************************************************
++**
++** gckOS_SetGPUPower
++**
++** Set the power of the GPU on or off.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.ß
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctBOOL Clock
++** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock.
++**
++** gctBOOL Power
++** gcvTRUE to turn on the power, or gcvFALSE to turn off the power.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUPower(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctBOOL Clock,
++ IN gctBOOL Power
++ );
++
++gceSTATUS
++gckOS_ResetGPU(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_PrepareGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_FinishGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_QueryGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 * Frequency,
++ OUT gctUINT8 * Scale
++ );
++
++gceSTATUS
++gckOS_SetGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT8 Scale
++ );
++
++/*******************************************************************************
++** Semaphores.
++*/
++
++/* Create a new semaphore. */
++gceSTATUS
++gckOS_CreateSemaphore(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ );
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_CreateSemaphoreVG(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ );
++#endif
++
++/* Delete a semahore. */
++gceSTATUS
++gckOS_DestroySemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Acquire a semahore. */
++gceSTATUS
++gckOS_AcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Try to acquire a semahore. */
++gceSTATUS
++gckOS_TryAcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Release a semahore. */
++gceSTATUS
++gckOS_ReleaseSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/*******************************************************************************
++** Timer API.
++*/
++
++typedef void (*gctTIMERFUNCTION)(gctPOINTER);
++
++/* Create a timer. */
++gceSTATUS
++gckOS_CreateTimer(
++ IN gckOS Os,
++ IN gctTIMERFUNCTION Function,
++ IN gctPOINTER Data,
++ OUT gctPOINTER * Timer
++ );
++
++/* Destory a timer. */
++gceSTATUS
++gckOS_DestroyTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ );
++
++/* Start a timer. */
++gceSTATUS
++gckOS_StartTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer,
++ IN gctUINT32 Delay
++ );
++
++/* Stop a timer. */
++gceSTATUS
++gckOS_StopTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ );
++
++/******************************************************************************\
++********************************* gckHEAP Object ********************************
++\******************************************************************************/
++
++typedef struct _gckHEAP * gckHEAP;
++
++/* Construct a new gckHEAP object. */
++gceSTATUS
++gckHEAP_Construct(
++ IN gckOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gckHEAP * Heap
++ );
++
++/* Destroy an gckHEAP object. */
++gceSTATUS
++gckHEAP_Destroy(
++ IN gckHEAP Heap
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gckHEAP_Allocate(
++ IN gckHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Node
++ );
++
++/* Free memory. */
++gceSTATUS
++gckHEAP_Free(
++ IN gckHEAP Heap,
++ IN gctPOINTER Node
++ );
++
++/* Profile the heap. */
++gceSTATUS
++gckHEAP_ProfileStart(
++ IN gckHEAP Heap
++ );
++
++gceSTATUS
++gckHEAP_ProfileEnd(
++ IN gckHEAP Heap,
++ IN gctCONST_STRING Title
++ );
++
++
++/******************************************************************************\
++******************************** gckVIDMEM Object ******************************
++\******************************************************************************/
++
++typedef struct _gckVIDMEM * gckVIDMEM;
++typedef struct _gckKERNEL * gckKERNEL;
++typedef struct _gckDB * gckDB;
++typedef struct _gckDVFS * gckDVFS;
++
++/* Construct a new gckVIDMEM object. */
++gceSTATUS
++gckVIDMEM_Construct(
++ IN gckOS Os,
++ IN gctUINT32 BaseAddress,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Threshold,
++ IN gctSIZE_T Banking,
++ OUT gckVIDMEM * Memory
++ );
++
++/* Destroy an gckVDIMEM object. */
++gceSTATUS
++gckVIDMEM_Destroy(
++ IN gckVIDMEM Memory
++ );
++
++/* Allocate rectangular memory. */
++gceSTATUS
++gckVIDMEM_Allocate(
++ IN gckVIDMEM Memory,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT BytesPerPixel,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Allocate linear memory. */
++gceSTATUS
++gckVIDMEM_AllocateLinear(
++ IN gckVIDMEM Memory,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Free memory. */
++gceSTATUS
++gckVIDMEM_Free(
++ IN gcuVIDMEM_NODE_PTR Node
++ );
++
++/* Lock memory. */
++gceSTATUS
++gckVIDMEM_Lock(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctBOOL Cacheable,
++ OUT gctUINT32 * Address
++ );
++
++/* Unlock memory. */
++gceSTATUS
++gckVIDMEM_Unlock(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gceSURF_TYPE Type,
++ IN OUT gctBOOL * Asynchroneous
++ );
++
++/* Construct a gcuVIDMEM_NODE union for virtual memory. */
++gceSTATUS
++gckVIDMEM_ConstructVirtual(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Contiguous,
++ IN gctSIZE_T Bytes,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Destroy a gcuVIDMEM_NODE union for virtual memory. */
++gceSTATUS
++gckVIDMEM_DestroyVirtual(
++ IN gcuVIDMEM_NODE_PTR Node
++ );
++
++/******************************************************************************\
++******************************** gckKERNEL Object ******************************
++\******************************************************************************/
++
++struct _gcsHAL_INTERFACE;
++
++/* Notifications. */
++typedef enum _gceNOTIFY
++{
++ gcvNOTIFY_INTERRUPT,
++ gcvNOTIFY_COMMAND_QUEUE,
++}
++gceNOTIFY;
++
++/* Flush flags. */
++typedef enum _gceKERNEL_FLUSH
++{
++ gcvFLUSH_COLOR = 0x01,
++ gcvFLUSH_DEPTH = 0x02,
++ gcvFLUSH_TEXTURE = 0x04,
++ gcvFLUSH_2D = 0x08,
++ gcvFLUSH_ALL = gcvFLUSH_COLOR
++ | gcvFLUSH_DEPTH
++ | gcvFLUSH_TEXTURE
++ | gcvFLUSH_2D,
++}
++gceKERNEL_FLUSH;
++
++/* Construct a new gckKERNEL object. */
++gceSTATUS
++gckKERNEL_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Context,
++ IN gckDB SharedDB,
++ OUT gckKERNEL * Kernel
++ );
++
++/* Destroy an gckKERNEL object. */
++gceSTATUS
++gckKERNEL_Destroy(
++ IN gckKERNEL Kernel
++ );
++
++/* Dispatch a user-level command. */
++gceSTATUS
++gckKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gckKERNEL_QueryVideoMemory(
++ IN gckKERNEL Kernel,
++ OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Lookup the gckVIDMEM object for a pool. */
++gceSTATUS
++gckKERNEL_GetVideoMemoryPool(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ OUT gckVIDMEM * VideoMemory
++ );
++
++#if gcdUSE_VIDMEM_PER_PID
++gceSTATUS
++gckKERNEL_GetVideoMemoryPoolPid(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ IN gctUINT32 Pid,
++ OUT gckVIDMEM * VideoMemory
++ );
++
++gceSTATUS
++gckKERNEL_CreateVideoMemoryPoolPid(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ IN gctUINT32 Pid,
++ OUT gckVIDMEM * VideoMemory
++ );
++
++gceSTATUS
++gckKERNEL_RemoveVideoMemoryPoolPid(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM VideoMemory
++ );
++#endif
++
++/* Map video memory. */
++gceSTATUS
++gckKERNEL_MapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++#ifdef __QNXNTO__
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes,
++#endif
++ OUT gctPOINTER * Logical
++ );
++
++/* Map video memory. */
++gceSTATUS
++gckKERNEL_MapVideoMemoryEx(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++#ifdef __QNXNTO__
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes,
++#endif
++ OUT gctPOINTER * Logical
++ );
++
++#ifdef __QNXNTO__
++/* Unmap video memory. */
++gceSTATUS
++gckKERNEL_UnmapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes
++ );
++#endif
++
++/* Map memory. */
++gceSTATUS
++gckKERNEL_MapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap memory. */
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Notification of events. */
++gceSTATUS
++gckKERNEL_Notify(
++ IN gckKERNEL Kernel,
++ IN gceNOTIFY Notifcation,
++ IN gctBOOL Data
++ );
++
++gceSTATUS
++gckKERNEL_QuerySettings(
++ IN gckKERNEL Kernel,
++ OUT gcsKERNEL_SETTINGS * Settings
++ );
++
++/*******************************************************************************
++**
++** gckKERNEL_Recovery
++**
++** Try to recover the GPU from a fatal error.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Recovery(
++ IN gckKERNEL Kernel
++ );
++
++/* Set the value of timeout on HW operation. */
++void
++gckKERNEL_SetTimeOut(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 timeOut
++ );
++
++/* Get access to the user data. */
++gceSTATUS
++gckKERNEL_OpenUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctPOINTER StaticStorage,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Release resources associated with the user data connection. */
++gceSTATUS
++gckKERNEL_CloseUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctBOOL FlushData,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++gceSTATUS
++gckDVFS_Construct(
++ IN gckHARDWARE Hardware,
++ OUT gckDVFS * Frequency
++ );
++
++gceSTATUS
++gckDVFS_Destroy(
++ IN gckDVFS Dvfs
++ );
++
++gceSTATUS
++gckDVFS_Start(
++ IN gckDVFS Dvfs
++ );
++
++gceSTATUS
++gckDVFS_Stop(
++ IN gckDVFS Dvfs
++ );
++
++/******************************************************************************\
++******************************* gckHARDWARE Object *****************************
++\******************************************************************************/
++
++/* Construct a new gckHARDWARE object. */
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ );
++
++/* Destroy an gckHARDWARE object. */
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ );
++
++/* Get hardware type. */
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ );
++
++/* Query system memory requirements. */
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ );
++
++/* Build virtual address. */
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Query command buffer requirements. */
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * Alignment,
++ OUT gctSIZE_T * ReservedHead,
++ OUT gctSIZE_T * ReservedTail
++ );
++
++/* Add a WAIT/LINK pair in the command queue. */
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctSIZE_T * WaitBytes
++ );
++
++/* Kickstart the command processor. */
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++#ifdef __QNXNTO__
++ IN gctPOINTER Physical,
++ IN gctBOOL PhysicalAddresses,
++#endif
++ IN gctSIZE_T Bytes
++ );
++
++/* Add an END command in the command queue. */
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a NOP command in the command queue. */
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a WAIT command in the command queue. */
++gceSTATUS
++gckHARDWARE_Wait(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Count,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a PIPESELECT command in the command queue. */
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a LINK command in the command queue. */
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER FetchAddress,
++ IN gctSIZE_T FetchSize,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add an EVENT command in the command queue. */
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Query the available memory. */
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ );
++
++/* Query the shader support. */
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctUINT * Varyings
++ );
++
++/* Split a harwdare specific address into API stuff. */
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Update command queue tail pointer. */
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ );
++
++/* Convert logical address to hardware specific address. */
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++#ifdef __QNXNTO__
++/* Convert physical address to hardware specific address. */
++gceSTATUS
++gckHARDWARE_ConvertPhysical(
++ IN gckHARDWARE Hardware,
++ IN gctPHYS_ADDR Physical,
++ OUT gctUINT32 * Address
++ );
++#endif
++
++/* Interrupt manager. */
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL InterruptValid
++ );
++
++/* Program MMU. */
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ );
++
++/* Flush the MMU. */
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ );
++
++/* Set the page table base address. */
++gceSTATUS
++gckHARDWARE_SetMMUv2(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Enable,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctBOOL FromPower
++ );
++
++/* Get idle register. */
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ );
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Enable/disable fast clear. */
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ );
++
++gceSTATUS
++gckHARDWARE_ReadInterrupt(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ );
++
++/* Power management. */
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ );
++
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ );
++
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ );
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ );
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ );
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++);
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++);
++#endif
++
++/* Profile 2D Engine. */
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OUT gcs2D_PROFILE_PTR Profile
++ );
++
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ );
++
++typedef gceSTATUS (*gctISRMANAGERFUNC)(gctPOINTER Context, gceCORE Core);
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ );
++
++/* Start a composition. */
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ );
++
++/* Check for Hardware features. */
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ );
++
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ );
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Frequency
++ );
++
++#if !gcdENABLE_VG
++/******************************************************************************\
++***************************** gckINTERRUPT Object ******************************
++\******************************************************************************/
++
++typedef struct _gckINTERRUPT * gckINTERRUPT;
++
++typedef gceSTATUS (* gctINTERRUPT_HANDLER)(
++ IN gckKERNEL Kernel
++ );
++
++gceSTATUS
++gckINTERRUPT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckINTERRUPT * Interrupt
++ );
++
++gceSTATUS
++gckINTERRUPT_Destroy(
++ IN gckINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckINTERRUPT_SetHandler(
++ IN gckINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ );
++
++gceSTATUS
++gckINTERRUPT_Notify(
++ IN gckINTERRUPT Interrupt,
++ IN gctBOOL Valid
++ );
++#endif
++/******************************************************************************\
++******************************** gckEVENT Object *******************************
++\******************************************************************************/
++
++typedef struct _gckEVENT * gckEVENT;
++
++/* Construct a new gckEVENT object. */
++gceSTATUS
++gckEVENT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckEVENT * Event
++ );
++
++/* Destroy an gckEVENT object. */
++gceSTATUS
++gckEVENT_Destroy(
++ IN gckEVENT Event
++ );
++
++/* Add a new event to the list of events. */
++gceSTATUS
++gckEVENT_AddList(
++ IN gckEVENT Event,
++ IN gcsHAL_INTERFACE_PTR Interface,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctBOOL AllocateAllowed,
++ IN gctBOOL FromKernel
++ );
++
++/* Schedule a FreeNonPagedMemory event. */
++gceSTATUS
++gckEVENT_FreeNonPagedMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeContiguousMemory event. */
++gceSTATUS
++gckEVENT_FreeContiguousMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeVideoMemory event. */
++gceSTATUS
++gckEVENT_FreeVideoMemory(
++ IN gckEVENT Event,
++ IN gcuVIDMEM_NODE_PTR VideoMemory,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a signal event. */
++gceSTATUS
++gckEVENT_Signal(
++ IN gckEVENT Event,
++ IN gctSIGNAL Signal,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule an Unlock event. */
++gceSTATUS
++gckEVENT_Unlock(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gceSURF_TYPE Type
++ );
++
++gceSTATUS
++gckEVENT_CommitDone(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++/* Schedule a FreeVirtualCommandBuffer event. */
++gceSTATUS
++gckEVENT_DestroyVirtualCommandBuffer(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++#endif
++
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower
++ );
++
++/* Commit an event queue. */
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue
++ );
++
++/* Schedule a composition event. */
++gceSTATUS
++gckEVENT_Compose(
++ IN gckEVENT Event,
++ IN gcsHAL_COMPOSE_PTR Info
++ );
++
++/* Event callback routine. */
++gceSTATUS
++gckEVENT_Notify(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ );
++
++/* Event callback routine. */
++gceSTATUS
++gckEVENT_Interrupt(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ );
++
++gceSTATUS
++gckEVENT_Dump(
++ IN gckEVENT Event
++ );
++/******************************************************************************\
++******************************* gckCOMMAND Object ******************************
++\******************************************************************************/
++
++typedef struct _gckCOMMAND * gckCOMMAND;
++
++/* Construct a new gckCOMMAND object. */
++gceSTATUS
++gckCOMMAND_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckCOMMAND * Command
++ );
++
++/* Destroy an gckCOMMAND object. */
++gceSTATUS
++gckCOMMAND_Destroy(
++ IN gckCOMMAND Command
++ );
++
++/* Acquire command queue synchronization objects. */
++gceSTATUS
++gckCOMMAND_EnterCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Release command queue synchronization objects. */
++gceSTATUS
++gckCOMMAND_ExitCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Start the command queue. */
++gceSTATUS
++gckCOMMAND_Start(
++ IN gckCOMMAND Command
++ );
++
++/* Stop the command queue. */
++gceSTATUS
++gckCOMMAND_Stop(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromRecovery
++ );
++
++/* Commit a buffer to the command queue. */
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID
++ );
++
++/* Reserve space in the command buffer. */
++gceSTATUS
++gckCOMMAND_Reserve(
++ IN gckCOMMAND Command,
++ IN gctSIZE_T RequestedBytes,
++ OUT gctPOINTER * Buffer,
++ OUT gctSIZE_T * BufferSize
++ );
++
++/* Execute reserved space in the command buffer. */
++gceSTATUS
++gckCOMMAND_Execute(
++ IN gckCOMMAND Command,
++ IN gctSIZE_T RequstedBytes
++ );
++
++/* Stall the command queue. */
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Attach user process. */
++gceSTATUS
++gckCOMMAND_Attach(
++ IN gckCOMMAND Command,
++ OUT gckCONTEXT * Context,
++ OUT gctSIZE_T * StateCount,
++ IN gctUINT32 ProcessID
++ );
++
++/* Detach user process. */
++gceSTATUS
++gckCOMMAND_Detach(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context
++ );
++
++#if gcdVIRTUAL_COMMAND_BUFFER
++gceSTATUS
++gckCOMMAND_DumpExecutingBuffer(
++ IN gckCOMMAND Command
++ );
++#endif
++
++/******************************************************************************\
++********************************* gckMMU Object ********************************
++\******************************************************************************/
++
++typedef struct _gckMMU * gckMMU;
++
++/* Construct a new gckMMU object. */
++gceSTATUS
++gckMMU_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ );
++
++/* Destroy an gckMMU object. */
++gceSTATUS
++gckMMU_Destroy(
++ IN gckMMU Mmu
++ );
++
++/* Enable the MMU. */
++gceSTATUS
++gckMMU_Enable(
++ IN gckMMU Mmu,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize
++ );
++
++/* Allocate pages inside the MMU. */
++gceSTATUS
++gckMMU_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++/* Remove a page table from the MMU. */
++gceSTATUS
++gckMMU_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ );
++
++/* Set the MMU page with info. */
++gceSTATUS
++gckMMU_SetPage(
++ IN gckMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ );
++
++#ifdef __QNXNTO__
++gceSTATUS
++gckMMU_InsertNode(
++ IN gckMMU Mmu,
++ IN gcuVIDMEM_NODE_PTR Node);
++
++gceSTATUS
++gckMMU_RemoveNode(
++ IN gckMMU Mmu,
++ IN gcuVIDMEM_NODE_PTR Node);
++#endif
++
++#ifdef __QNXNTO__
++gceSTATUS
++gckMMU_FreeHandleMemory(
++ IN gckKERNEL Kernel,
++ IN gckMMU Mmu,
++ IN gctUINT32 Pid
++ );
++#endif
++
++gceSTATUS
++gckMMU_Flush(
++ IN gckMMU Mmu
++ );
++
++gceSTATUS
++gckMMU_DumpPageTableEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ );
++
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Clear,
++ OUT gcsPROFILER_COUNTERS * Counters
++ );
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Clear,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ );
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ );
++#endif
++
++gceSTATUS
++gckOS_SignalQueryHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ OUT gckHARDWARE * Hardware
++ );
++
++gceSTATUS
++gckOS_SignalSetHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ gckHARDWARE Hardware
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#if gcdENABLE_VG
++#include "gc_hal_vg.h"
++#endif
++
++#endif /* __gc_hal_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,185 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_buffer_h_
++#define __gc_hal_kernel_buffer_h_
++
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++************************ Command Buffer and Event Objects **********************
++\******************************************************************************/
++
++/* The number of context buffers per user. */
++#define gcdCONTEXT_BUFFER_COUNT 2
++
++/* State delta record. */
++typedef struct _gcsSTATE_DELTA_RECORD * gcsSTATE_DELTA_RECORD_PTR;
++typedef struct _gcsSTATE_DELTA_RECORD
++{
++ /* State address. */
++ gctUINT address;
++
++ /* State mask. */
++ gctUINT32 mask;
++
++ /* State data. */
++ gctUINT32 data;
++}
++gcsSTATE_DELTA_RECORD;
++
++/* State delta. */
++typedef struct _gcsSTATE_DELTA
++{
++ /* For debugging: the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Main state delta ID. Every time state delta structure gets reinitialized,
++ main ID is incremented. If main state ID overflows, all map entry IDs get
++ reinitialized to make sure there is no potential erroneous match after
++ the overflow.*/
++ gctUINT id;
++
++ /* The number of contexts pending modification by the delta. */
++ gctINT refCount;
++
++ /* Vertex element count for the delta buffer. */
++ gctUINT elementCount;
++
++ /* Number of states currently stored in the record array. */
++ gctUINT recordCount;
++
++ /* Record array; holds all modified states in gcsSTATE_DELTA_RECORD. */
++ gctUINT64 recordArray;
++
++ /* Map entry ID is used for map entry validation. If map entry ID does not
++ match the main state delta ID, the entry and the corresponding state are
++ considered not in use. */
++ gctUINT64 mapEntryID;
++ gctUINT mapEntryIDSize;
++
++ /* If the map entry ID matches the main state delta ID, index points to
++ the state record in the record array. */
++ gctUINT64 mapEntryIndex;
++
++ /* Previous and next state deltas in gcsSTATE_DELTA. */
++ gctUINT64 prev;
++ gctUINT64 next;
++}
++gcsSTATE_DELTA;
++
++/* Command buffer object. */
++struct _gcoCMDBUF
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Command buffer entry and exit pipes. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Feature usage flags. */
++ gctBOOL using2D;
++ gctBOOL using3D;
++ gctBOOL usingFilterBlit;
++ gctBOOL usingPalette;
++
++ /* Physical address of command buffer. Just a name. */
++ gctUINT32 physical;
++
++ /* Logical address of command buffer. */
++ gctUINT64 logical;
++
++ /* Number of bytes in command buffer. */
++ gctUINT bytes;
++
++ /* Start offset into the command buffer. */
++ gctUINT startOffset;
++
++ /* Current offset into the command buffer. */
++ gctUINT offset;
++
++ /* Number of free bytes in command buffer. */
++ gctUINT free;
++
++ /* Location of the last reserved area. */
++ gctUINT64 lastReserve;
++ gctUINT lastOffset;
++
++#if gcdSECURE_USER
++ /* Hint array for the current command buffer. */
++ gctUINT hintArraySize;
++ gctUINT64 hintArray;
++ gctUINT64 hintArrayTail;
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Last load state command location and hardware address. */
++ gctUINT64 lastLoadStatePtr;
++ gctUINT32 lastLoadStateAddress;
++ gctUINT32 lastLoadStateCount;
++#endif
++};
++
++typedef struct _gcsQUEUE
++{
++ /* Pointer to next gcsQUEUE structure in gcsQUEUE. */
++ gctUINT64 next;
++
++ /* Event information. */
++ gcsHAL_INTERFACE iface;
++}
++gcsQUEUE;
++
++/* Event queue. */
++struct _gcoQUEUE
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to current event queue. */
++ gcsQUEUE_PTR head;
++ gcsQUEUE_PTR tail;
++
++#ifdef __QNXNTO__
++ /* Buffer for records. */
++ gcsQUEUE_PTR records;
++ gctUINT32 freeBytes;
++ gctUINT32 offset;
++#else
++ /* List of free records. */
++ gcsQUEUE_PTR freeList;
++#endif
++ #define gcdIN_QUEUE_RECORD_LIMIT 16
++ /* Number of records currently in queue */
++ gctUINT32 recordCount;
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_buffer_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,530 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/*
++** Include file for the local memory management.
++*/
++
++#ifndef __gc_hal_mem_h_
++#define __gc_hal_mem_h_
++#ifndef VIVANTE_NO_3D
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*******************************************************************************
++** Usage:
++
++ The macros to declare MemPool type and functions are
++ gcmMEM_DeclareFSMemPool (Type, TypeName, Prefix)
++ gcmMEM_DeclareVSMemPool (Type, TypeName, Prefix)
++ gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix)
++
++ The data structures for MemPool are
++ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
++ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
++ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
++
++ The MemPool constructor and destructor functions are
++ gcfMEM_InitFSMemPool(gcsMEM_FS_MEM_POOL *, gcoOS, gctUINT, gctUINT);
++ gcfMEM_FreeFSMemPool(gcsMEM_FS_MEM_POOL *);
++ gcfMEM_InitVSMemPool(gcsMEM_VS_MEM_POOL *, gcoOS, gctUINT, gctBOOL);
++ gcfMEM_FreeVSMemPool(gcsMEM_VS_MEM_POOL *);
++ gcfMEM_InitAFSMemPool(gcsMEM_AFS_MEM_POOL *, gcoOS, gctUINT);
++ gcfMEM_FreeAFSMemPool(gcsMEM_AFS_MEM_POOL *);
++
++ FS: for Fixed-Size data structures
++ VS: for Variable-size data structures
++ AFS: for Array of Fixed-Size data structures
++
++
++ // Example 1: For a fixed-size data structure, struct gcsNode.
++ // It is used locally in a file, so the functions are static without prefix.
++ // At top level, declear allocate and free functions.
++ // The first argument is the data type.
++ // The second armument is the short name used in the fuctions.
++ gcmMEM_DeclareFSMemPool(struct gcsNode, Node, );
++
++ // The previous macro creates two inline functions,
++ // _AllocateNode and _FreeNode.
++
++ // In function or struct
++ gcsMEM_FS_MEM_POOL nodeMemPool;
++
++ // In function,
++ struct gcsNode * node;
++ gceSTATUS status;
++
++ // Before using the memory pool, initialize it.
++ // The second argument is the gcoOS object.
++ // The third argument is the number of data structures to allocate for each chunk.
++ status = gcfMEM_InitFSMemPool(&nodeMemPool, os, 100, sizeof(struct gcsNode));
++ ...
++
++ // Allocate a node.
++ status = _AllocateNode(nodeMemPool, &node);
++ ...
++ // Free a node.
++ _FreeNode(nodeMemPool, node);
++
++ // After using the memory pool, free it.
++ gcfMEM_FreeFSMemPool(&nodeMemPool);
++
++
++ // Example 2: For array of fixed-size data structures, struct gcsNode.
++ // It is used in several files, so the functions are extern with prefix.
++ // At top level, declear allocate and free functions.
++ // The first argument is the data type, and the second one is the short name
++ // used in the fuctions.
++ gcmMEM_DeclareAFSMemPool(struct gcsNode, NodeArray, gcfOpt);
++
++ // The previous macro creates two inline functions,
++ // gcfOpt_AllocateNodeArray and gcfOpt_FreeNodeArray.
++
++ // In function or struct
++ gcsMEM_AFS_MEM_POOL nodeArrayMemPool;
++
++ // In function,
++ struct gcsNode * nodeArray;
++ gceSTATUS status;
++
++ // Before using the array memory pool, initialize it.
++ // The second argument is the gcoOS object, the third is the number of data
++ // structures to allocate for each chunk.
++ status = gcfMEM_InitAFSMemPool(&nodeArrayMemPool, os, sizeof(struct gcsNode));
++ ...
++
++ // Allocate a node array of size 100.
++ status = gcfOpt_AllocateNodeArray(nodeArrayMemPool, &nodeArray, 100);
++ ...
++ // Free a node array.
++ gcfOpt_FreeNodeArray(&nodeArrayMemPool, nodeArray);
++
++ // After using the array memory pool, free it.
++ gcfMEM_FreeAFSMemPool(&nodeArrayMemPool);
++
++*******************************************************************************/
++
++/*******************************************************************************
++** To switch back to use gcoOS_Allocate and gcoOS_Free, add
++** #define USE_LOCAL_MEMORY_POOL 0
++** before including this file.
++*******************************************************************************/
++#ifndef USE_LOCAL_MEMORY_POOL
++/*
++ USE_LOCAL_MEMORY_POOL
++
++ This define enables the local memory management to improve performance.
++*/
++#define USE_LOCAL_MEMORY_POOL 1
++#endif
++
++/*******************************************************************************
++** Memory Pool Data Structures
++*******************************************************************************/
++#if USE_LOCAL_MEMORY_POOL
++ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
++ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
++ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
++#else
++ typedef gcoOS gcsMEM_FS_MEM_POOL;
++ typedef gcoOS gcsMEM_VS_MEM_POOL;
++ typedef gcoOS gcsMEM_AFS_MEM_POOL;
++#endif
++
++/*******************************************************************************
++** Memory Pool Macros
++*******************************************************************************/
++#if USE_LOCAL_MEMORY_POOL
++#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ return(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ gcmERR_RETURN(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcfMEM_FSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName##List( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * FirstPointer, \
++ Type * LastPointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x FirstPointer=0x%x LastPointer=0x%x", MemPool, FirstPointer, LastPointer); \
++ status = gcfMEM_FSMemPoolFreeAList(MemPool, (gctPOINTER) FirstPointer, (gctPOINTER) LastPointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status;\
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ status = gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++ Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ gcmERR_RETURN(gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, size); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pinter); \
++ status = gcfMEM_VSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ status = gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ gcmERR_RETURN(gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcfMEM_AFSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#else
++
++#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcoOS_Allocate(MemPool, \
++ gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ status = gcoOS_Allocate(MemPool, \
++ Size, \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ Size, \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Size); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ status = gcoOS_Allocate(MemPool, \
++ Count * gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ Count * gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++#endif
++
++/*******************************************************************************
++** Memory Pool Data Functions
++*******************************************************************************/
++gceSTATUS
++gcfMEM_InitFSMemPool(
++ IN gcsMEM_FS_MEM_POOL * MemPool,
++ IN gcoOS OS,
++ IN gctUINT NodeCount,
++ IN gctUINT NodeSize
++ );
++
++gceSTATUS
++gcfMEM_FreeFSMemPool(
++ IN gcsMEM_FS_MEM_POOL * MemPool
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolGetANode(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolFreeANode(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolFreeAList(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ IN gctPOINTER FirstNode,
++ IN gctPOINTER LastNode
++ );
++
++gceSTATUS
++gcfMEM_InitVSMemPool(
++ IN gcsMEM_VS_MEM_POOL * MemPool,
++ IN gcoOS OS,
++ IN gctUINT BlockSize,
++ IN gctBOOL RecycleFreeNode
++ );
++
++gceSTATUS
++gcfMEM_FreeVSMemPool(
++ IN gcsMEM_VS_MEM_POOL * MemPool
++ );
++
++gceSTATUS
++gcfMEM_VSMemPoolGetANode(
++ IN gcsMEM_VS_MEM_POOL MemPool,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_VSMemPoolFreeANode(
++ IN gcsMEM_VS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++gceSTATUS
++gcfMEM_InitAFSMemPool(
++ IN gcsMEM_AFS_MEM_POOL *MemPool,
++ IN gcoOS OS,
++ IN gctUINT NodeCount,
++ IN gctUINT NodeSize
++ );
++
++gceSTATUS
++gcfMEM_FreeAFSMemPool(
++ IN gcsMEM_AFS_MEM_POOL *MemPool
++ );
++
++gceSTATUS
++gcfMEM_AFSMemPoolGetANode(
++ IN gcsMEM_AFS_MEM_POOL MemPool,
++ IN gctUINT Count,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_AFSMemPoolFreeANode(
++ IN gcsMEM_AFS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* VIVANTE_NO_3D */
++#endif /* __gc_hal_mem_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,947 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_options_h_
++#define __gc_hal_options_h_
++
++/*
++ gcdPRINT_VERSION
++
++ Print HAL version.
++*/
++#ifndef gcdPRINT_VERSION
++# define gcdPRINT_VERSION 0
++#endif
++
++/*
++ USE_NEW_LINUX_SIGNAL
++
++ This define enables the Linux kernel signaling between kernel and user.
++*/
++#ifndef USE_NEW_LINUX_SIGNAL
++# define USE_NEW_LINUX_SIGNAL 0
++#endif
++
++/*
++ VIVANTE_PROFILER
++
++ This define enables the profiler.
++*/
++#ifndef VIVANTE_PROFILER
++# define VIVANTE_PROFILER 1
++#endif
++
++#ifndef VIVANTE_PROFILER_PERDRAW
++# define VIVANTE_PROFILER_PERDRAW 0
++#endif
++
++/*
++ VIVANTE_PROFILER_CONTEXT
++
++ This define enables the profiler according to each hw context.
++*/
++#ifndef VIVANTE_PROFILER_CONTEXT
++# define VIVANTE_PROFILER_CONTEXT 1
++#endif
++
++/*
++ gcdUSE_VG
++
++ Enable VG HAL layer (only for GC350).
++*/
++#ifndef gcdUSE_VG
++# define gcdUSE_VG 0
++#endif
++
++/*
++ USE_SW_FB
++
++ Set to 1 if the frame buffer memory cannot be accessed by the GPU.
++*/
++#ifndef USE_SW_FB
++# define USE_SW_FB 0
++#endif
++
++/*
++ USE_SUPER_SAMPLING
++
++ This define enables super-sampling support.
++*/
++#define USE_SUPER_SAMPLING 0
++
++/*
++ PROFILE_HAL_COUNTERS
++
++ This define enables HAL counter profiling support. HW and SHADER
++ counter profiling depends on this.
++*/
++#ifndef PROFILE_HAL_COUNTERS
++# define PROFILE_HAL_COUNTERS 1
++#endif
++
++/*
++ PROFILE_HW_COUNTERS
++
++ This define enables HW counter profiling support.
++*/
++#ifndef PROFILE_HW_COUNTERS
++# define PROFILE_HW_COUNTERS 1
++#endif
++
++/*
++ PROFILE_SHADER_COUNTERS
++
++ This define enables SHADER counter profiling support.
++*/
++#ifndef PROFILE_SHADER_COUNTERS
++# define PROFILE_SHADER_COUNTERS 1
++#endif
++
++/*
++ COMMAND_PROCESSOR_VERSION
++
++ The version of the command buffer and task manager.
++*/
++#define COMMAND_PROCESSOR_VERSION 1
++
++/*
++ gcdDUMP_KEY
++
++ Set this to a string that appears in 'cat /proc/<pid>/cmdline'. E.g. 'camera'.
++ HAL will create dumps for the processes matching this key.
++*/
++#ifndef gcdDUMP_KEY
++# define gcdDUMP_KEY "process"
++#endif
++
++/*
++ gcdDUMP_PATH
++
++ The dump file location. Some processes cannot write to the sdcard.
++ Try apps' data dir, e.g. /data/data/com.android.launcher
++*/
++#ifndef gcdDUMP_PATH
++#if defined(ANDROID)
++# define gcdDUMP_PATH "/mnt/sdcard/"
++#else
++# define gcdDUMP_PATH "./"
++#endif
++#endif
++
++/*
++ gcdDUMP
++
++ When set to 1, a dump of all states and memory uploads, as well as other
++ hardware related execution will be printed to the debug console. This
++ data can be used for playing back applications.
++*/
++#ifndef gcdDUMP
++# define gcdDUMP 0
++#endif
++
++/*
++ gcdDUMP_API
++
++ When set to 1, a high level dump of the EGL and GL/VG APs's are
++ captured.
++*/
++#ifndef gcdDUMP_API
++# define gcdDUMP_API 0
++#endif
++
++/*
++ gcdDUMP_FRAMERATE
++ When set to a value other than zero, averaqe frame rate will be dumped.
++ The value set is the starting frame that the average will be calculated.
++ This is needed because sometimes first few frames are too slow to be included
++ in the average. Frame count starts from 1.
++*/
++#ifndef gcdDUMP_FRAMERATE
++# define gcdDUMP_FRAMERATE 0
++#endif
++
++/*
++ gcdVIRTUAL_COMMAND_BUFFER
++ When set to 1, user command buffer and context buffer will be allocated
++ from gcvPOOL_VIRTUAL.
++*/
++#ifndef gcdVIRTUAL_COMMAND_BUFFER
++# define gcdVIRTUAL_COMMAND_BUFFER 0
++#endif
++
++/*
++ gcdENABLE_FSCALE_VAL_ADJUST
++ When non-zero, FSCALE_VAL when gcvPOWER_ON can be adjusted externally.
++ */
++#ifndef gcdENABLE_FSCALE_VAL_ADJUST
++# define gcdENABLE_FSCALE_VAL_ADJUST 1
++#endif
++
++/*
++ gcdDUMP_IN_KERNEL
++
++ When set to 1, all dumps will happen in the kernel. This is handy if
++ you want the kernel to dump its command buffers as well and the data
++ needs to be in sync.
++*/
++#ifndef gcdDUMP_IN_KERNEL
++# define gcdDUMP_IN_KERNEL 0
++#endif
++
++/*
++ gcdDUMP_COMMAND
++
++ When set to non-zero, the command queue will dump all incoming command
++ and context buffers as well as all other modifications to the command
++ queue.
++*/
++#ifndef gcdDUMP_COMMAND
++# define gcdDUMP_COMMAND 0
++#endif
++
++/*
++ gcdDUMP_FRAME_TGA
++
++ When set to a value other than 0, a dump of the frame specified by the value,
++ will be done into frame.tga. Frame count starts from 1.
++ */
++#ifndef gcdDUMP_FRAME_TGA
++#define gcdDUMP_FRAME_TGA 0
++#endif
++/*
++ gcdNULL_DRIVER
++
++ Set to 1 for infinite speed hardware.
++ Set to 2 for bypassing the HAL.
++ Set to 3 for bypassing the drivers.
++*/
++#ifndef gcdNULL_DRIVER
++# define gcdNULL_DRIVER 0
++#endif
++
++/*
++ gcdENABLE_TIMEOUT_DETECTION
++
++ Enable timeout detection.
++*/
++#ifndef gcdENABLE_TIMEOUT_DETECTION
++# define gcdENABLE_TIMEOUT_DETECTION 0
++#endif
++
++/*
++ gcdCMD_BUFFER_SIZE
++
++ Number of bytes in a command buffer.
++*/
++#ifndef gcdCMD_BUFFER_SIZE
++# define gcdCMD_BUFFER_SIZE (128 << 10)
++#endif
++
++/*
++ gcdCMD_BUFFERS
++
++ Number of command buffers to use per client.
++*/
++#ifndef gcdCMD_BUFFERS
++# define gcdCMD_BUFFERS 2
++#endif
++
++/*
++ gcdMAX_CMD_BUFFERS
++
++ Maximum number of command buffers to use per client.
++*/
++#ifndef gcdMAX_CMD_BUFFERS
++# define gcdMAX_CMD_BUFFERS 8
++#endif
++
++/*
++ gcdCOMMAND_QUEUES
++
++ Number of command queues in the kernel.
++*/
++#ifndef gcdCOMMAND_QUEUES
++# define gcdCOMMAND_QUEUES 2
++#endif
++
++/*
++ gcdPOWER_CONTROL_DELAY
++
++ The delay in milliseconds required to wait until the GPU has woke up
++ from a suspend or power-down state. This is system dependent because
++ the bus clock also needs to stabalize.
++*/
++#ifndef gcdPOWER_CONTROL_DELAY
++# define gcdPOWER_CONTROL_DELAY 0
++#endif
++
++/*
++ gcdMIRROR_PAGETABLE
++
++ Enable it when GPUs with old MMU and new MMU exist at same SoC. It makes
++ each GPU use same virtual address to access same physical memory.
++*/
++#ifndef gcdMIRROR_PAGETABLE
++# define gcdMIRROR_PAGETABLE 0
++#endif
++
++/*
++ gcdMMU_SIZE
++
++ Size of the MMU page table in bytes. Each 4 bytes can hold 4kB worth of
++ virtual data.
++*/
++#ifndef gcdMMU_SIZE
++#if gcdMIRROR_PAGETABLE
++# define gcdMMU_SIZE 0x200000
++#else
++# define gcdMMU_SIZE (2048 << 10)
++#endif
++#endif
++
++/*
++ gcdSECURE_USER
++
++ Use logical addresses instead of physical addresses in user land. In
++ this case a hint table is created for both command buffers and context
++ buffers, and that hint table will be used to patch up those buffers in
++ the kernel when they are ready to submit.
++*/
++#ifndef gcdSECURE_USER
++# define gcdSECURE_USER 0
++#endif
++
++/*
++ gcdSECURE_CACHE_SLOTS
++
++ Number of slots in the logical to DMA address cache table. Each time a
++ logical address needs to be translated into a DMA address for the GPU,
++ this cache will be walked. The replacement scheme is LRU.
++*/
++#ifndef gcdSECURE_CACHE_SLOTS
++# define gcdSECURE_CACHE_SLOTS 1024
++#endif
++
++/*
++ gcdSECURE_CACHE_METHOD
++
++ Replacement scheme used for Secure Cache. The following options are
++ available:
++
++ gcdSECURE_CACHE_LRU
++ A standard LRU cache.
++
++ gcdSECURE_CACHE_LINEAR
++ A linear walker with the idea that an application will always
++ render the scene in a similar way, so the next entry in the
++ cache should be a hit most of the time.
++
++ gcdSECURE_CACHE_HASH
++ A 256-entry hash table.
++
++ gcdSECURE_CACHE_TABLE
++ A simple cache but with potential of a lot of cache replacement.
++*/
++#ifndef gcdSECURE_CACHE_METHOD
++# define gcdSECURE_CACHE_METHOD gcdSECURE_CACHE_HASH
++#endif
++
++/*
++ gcdREGISTER_ACCESS_FROM_USER
++
++ Set to 1 to allow IOCTL calls to get through from user land. This
++ should only be in debug or development drops.
++*/
++#ifndef gcdREGISTER_ACCESS_FROM_USER
++# define gcdREGISTER_ACCESS_FROM_USER 1
++#endif
++
++/*
++ gcdUSER_HEAP_ALLOCATOR
++
++ Set to 1 to enable user mode heap allocator for fast memory allocation
++ and destroying. Otherwise, memory allocation/destroying in user mode
++ will be directly managed by system. Only for linux for now.
++*/
++#ifndef gcdUSER_HEAP_ALLOCATOR
++# define gcdUSER_HEAP_ALLOCATOR 1
++#endif
++
++/*
++ gcdHEAP_SIZE
++
++ Set the allocation size for the internal heaps. Each time a heap is
++ full, a new heap will be allocated with this minmimum amount of bytes.
++ The bigger this size, the fewer heaps there are to allocate, the better
++ the performance. However, heaps won't be freed until they are
++ completely free, so there might be some more memory waste if the size is
++ too big.
++*/
++#ifndef gcdHEAP_SIZE
++# define gcdHEAP_SIZE (64 << 10)
++#endif
++
++/*
++ gcdPOWER_SUSNPEND_WHEN_IDLE
++
++ Set to 1 to make GPU enter gcvPOWER_SUSPEND when idle detected,
++ otherwise GPU will enter gcvPOWER_IDLE.
++*/
++#ifndef gcdPOWER_SUSNPEND_WHEN_IDLE
++# define gcdPOWER_SUSNPEND_WHEN_IDLE 1
++#endif
++
++/*
++ gcdFPGA_BUILD
++
++ This define enables work arounds for FPGA images.
++*/
++#ifndef gcdFPGA_BUILD
++# define gcdFPGA_BUILD 0
++#endif
++
++/*
++ gcdGPU_TIMEOUT
++
++ This define specified the number of milliseconds the system will wait
++ before it broadcasts the GPU is stuck. In other words, it will define
++ the timeout of any operation that needs to wait for the GPU.
++
++ If the value is 0, no timeout will be checked for.
++*/
++#ifndef gcdGPU_TIMEOUT
++#if gcdFPGA_BUILD
++# define gcdGPU_TIMEOUT 0
++# else
++# define gcdGPU_TIMEOUT 20000
++# endif
++#endif
++
++/*
++ gcdGPU_ADVANCETIMER
++
++ it is advance timer.
++*/
++#ifndef gcdGPU_ADVANCETIMER
++# define gcdGPU_ADVANCETIMER 250
++#endif
++
++/*
++ gcdSTATIC_LINK
++
++ This define disalbes static linking;
++*/
++#ifndef gcdSTATIC_LINK
++# define gcdSTATIC_LINK 0
++#endif
++
++/*
++ gcdUSE_NEW_HEAP
++
++ Setting this define to 1 enables new heap.
++*/
++#ifndef gcdUSE_NEW_HEAP
++# define gcdUSE_NEW_HEAP 0
++#endif
++
++/*
++ gcdCMD_NO_2D_CONTEXT
++
++ This define enables no-context 2D command buffer.
++*/
++#ifndef gcdCMD_NO_2D_CONTEXT
++# define gcdCMD_NO_2D_CONTEXT 1
++#endif
++
++/*
++ gcdENABLE_BANK_ALIGNMENT
++
++ When enabled, video memory is allocated bank aligned. The vendor can modify
++ _GetSurfaceBankAlignment() and gcoSURF_GetBankOffsetBytes() to define how
++ different types of allocations are bank and channel aligned.
++ When disabled (default), no bank alignment is done.
++*/
++#ifndef gcdENABLE_BANK_ALIGNMENT
++# define gcdENABLE_BANK_ALIGNMENT 0
++#endif
++
++/*
++ gcdBANK_BIT_START
++
++ Specifies the start bit of the bank (inclusive).
++*/
++#ifndef gcdBANK_BIT_START
++# define gcdBANK_BIT_START 12
++#endif
++
++/*
++ gcdBANK_BIT_END
++
++ Specifies the end bit of the bank (inclusive).
++*/
++#ifndef gcdBANK_BIT_END
++# define gcdBANK_BIT_END 14
++#endif
++
++/*
++ gcdBANK_CHANNEL_BIT
++
++ When set, video memory when allocated bank aligned is allocated such that
++ render and depth buffer addresses alternate on the channel bit specified.
++ This option has an effect only when gcdENABLE_BANK_ALIGNMENT is enabled.
++ When disabled (default), no alteration is done.
++*/
++#ifndef gcdBANK_CHANNEL_BIT
++# define gcdBANK_CHANNEL_BIT 7
++#endif
++
++/*
++ gcdDYNAMIC_SPEED
++
++ When non-zero, it informs the kernel driver to use the speed throttling
++ broadcasting functions to inform the system the GPU should be spet up or
++ slowed down. It will send a broadcast for slowdown each "interval"
++ specified by this define in milliseconds
++ (gckOS_BroadcastCalibrateSpeed).
++*/
++#ifndef gcdDYNAMIC_SPEED
++# define gcdDYNAMIC_SPEED 2000
++#endif
++
++/*
++ gcdDYNAMIC_EVENT_THRESHOLD
++
++ When non-zero, it specifies the maximum number of available events at
++ which the kernel driver will issue a broadcast to speed up the GPU
++ (gckOS_BroadcastHurry).
++*/
++#ifndef gcdDYNAMIC_EVENT_THRESHOLD
++# define gcdDYNAMIC_EVENT_THRESHOLD 5
++#endif
++
++/*
++ gcdENABLE_PROFILING
++
++ Enable profiling macros.
++*/
++#ifndef gcdENABLE_PROFILING
++# define gcdENABLE_PROFILING 0
++#endif
++
++/*
++ gcdENABLE_128B_MERGE
++
++ Enable 128B merge for the BUS control.
++*/
++#ifndef gcdENABLE_128B_MERGE
++# define gcdENABLE_128B_MERGE 0
++#endif
++
++/*
++ gcdFRAME_DB
++
++ When non-zero, it specified the number of frames inside the frame
++ database. The frame DB will collect per-frame timestamps and hardware
++ counters.
++*/
++#ifndef gcdFRAME_DB
++# define gcdFRAME_DB 0
++# define gcdFRAME_DB_RESET 0
++# define gcdFRAME_DB_NAME "/var/log/frameDB.log"
++#endif
++
++/*
++ gcdENABLE_VG
++ enable the 2D openVG
++*/
++
++#ifndef gcdENABLE_VG
++# define gcdENABLE_VG 0
++#endif
++
++/*
++ gcdDYNAMIC_MAP_RESERVED_MEMORY
++
++ When gcvPOOL_SYSTEM is constructed from RESERVED memory,
++ driver can map the whole reserved memory to kernel space
++ at the beginning, or just map a piece of memory when need
++ to access.
++
++ Notice:
++ - It's only for the 2D openVG. For other cores, there is
++ _NO_ need to map reserved memory to kernel.
++ - It's meaningless when memory is allocated by
++ gckOS_AllocateContiguous, in that case, memory is always
++ mapped by system when allocated.
++*/
++#ifndef gcdDYNAMIC_MAP_RESERVED_MEMORY
++# define gcdDYNAMIC_MAP_RESERVED_MEMORY 1
++#endif
++
++/*
++ gcdPAGED_MEMORY_CACHEABLE
++
++ When non-zero, paged memory will be cacheable.
++
++ Normally, driver will detemines whether a video memory
++ is cacheable or not. When cacheable is not neccessary,
++ it will be writecombine.
++
++ This option is only for those SOC which can't enable
++ writecombine without enabling cacheable.
++*/
++
++#ifndef gcdPAGED_MEMORY_CACHEABLE
++# define gcdPAGED_MEMORY_CACHEABLE 0
++#endif
++
++/*
++ gcdNONPAGED_MEMORY_CACHEABLE
++
++ When non-zero, non paged memory will be cacheable.
++*/
++
++#ifndef gcdNONPAGED_MEMORY_CACHEABLE
++# define gcdNONPAGED_MEMORY_CACHEABLE 0
++#endif
++
++/*
++ gcdNONPAGED_MEMORY_BUFFERABLE
++
++ When non-zero, non paged memory will be bufferable.
++ gcdNONPAGED_MEMORY_BUFFERABLE and gcdNONPAGED_MEMORY_CACHEABLE
++ can't be set 1 at same time
++*/
++
++#ifndef gcdNONPAGED_MEMORY_BUFFERABLE
++# define gcdNONPAGED_MEMORY_BUFFERABLE 1
++#endif
++
++/*
++ gcdENABLE_INFINITE_SPEED_HW
++ enable the Infinte HW , this is for 2D openVG
++*/
++
++#ifndef gcdENABLE_INFINITE_SPEED_HW
++# define gcdENABLE_INFINITE_SPEED_HW 0
++#endif
++
++/*
++ gcdENABLE_TS_DOUBLE_BUFFER
++ enable the TS double buffer, this is for 2D openVG
++*/
++
++#ifndef gcdENABLE_TS_DOUBLE_BUFFER
++# define gcdENABLE_TS_DOUBLE_BUFFER 1
++#endif
++
++/*
++ gcd6000_SUPPORT
++
++ Temporary define to enable/disable 6000 support.
++ */
++#ifndef gcd6000_SUPPORT
++# define gcd6000_SUPPORT 0
++#endif
++
++/*
++ gcdPOWEROFF_TIMEOUT
++
++ When non-zero, GPU will power off automatically from
++ idle state, and gcdPOWEROFF_TIMEOUT is also the default
++ timeout in milliseconds.
++ */
++
++#ifndef gcdPOWEROFF_TIMEOUT
++# define gcdPOWEROFF_TIMEOUT 300
++#endif
++
++/*
++ gcdUSE_VIDMEM_PER_PID
++*/
++#ifndef gcdUSE_VIDMEM_PER_PID
++# define gcdUSE_VIDMEM_PER_PID 0
++#endif
++
++/*
++ QNX_SINGLE_THREADED_DEBUGGING
++*/
++#ifndef QNX_SINGLE_THREADED_DEBUGGING
++# define QNX_SINGLE_THREADED_DEBUGGING 0
++#endif
++
++/*
++ gcdENABLE_RECOVERY
++
++ This define enables the recovery code.
++*/
++#ifndef gcdENABLE_RECOVERY
++# define gcdENABLE_RECOVERY 1
++#endif
++
++/*
++ gcdRENDER_THREADS
++
++ Number of render threads. Make it zero, and there will be no render
++ threads.
++*/
++#ifndef gcdRENDER_THREADS
++# define gcdRENDER_THREADS 0
++#endif
++
++/*
++ gcdSMP
++
++ This define enables SMP support.
++
++ Currently, it only works on Linux/Android,
++ Kbuild will config it according to whether
++ CONFIG_SMP is set.
++
++*/
++#ifndef gcdSMP
++# define gcdSMP 0
++#endif
++
++/*
++ gcdSUPPORT_SWAP_RECTANGLE
++
++ Support swap with a specific rectangle.
++
++ Set the rectangle with eglSetSwapRectangleVIV api.
++*/
++#ifndef gcdSUPPORT_SWAP_RECTANGLE
++# define gcdSUPPORT_SWAP_RECTANGLE 0
++#endif
++
++/*
++ gcdGPU_LINEAR_BUFFER_ENABLED
++
++ Use linear buffer for GPU apps so HWC can do 2D composition.
++*/
++#ifndef gcdGPU_LINEAR_BUFFER_ENABLED
++# define gcdGPU_LINEAR_BUFFER_ENABLED 1
++#endif
++
++/*
++ gcdENABLE_RENDER_INTO_WINDOW
++
++ Enable Render-Into-Window (ie, No-Resolve) feature on android.
++ NOTE that even if enabled, it still depends on hardware feature and
++ android application behavior. When hardware feature or application
++ behavior can not support render into window mode, it will fail back
++ to normal mode.
++ When Render-Into-Window is finally used, window back buffer of android
++ applications will be allocated matching render target tiling format.
++ Otherwise buffer tiling is decided by the above option
++ 'gcdGPU_LINEAR_BUFFER_ENABLED'.
++*/
++#ifndef gcdENABLE_RENDER_INTO_WINDOW
++# define gcdENABLE_RENDER_INTO_WINDOW 1
++#endif
++
++/*
++ gcdSHARED_RESOLVE_BUFFER_ENABLED
++
++ Use shared resolve buffer for all app buffers.
++*/
++#ifndef gcdSHARED_RESOLVE_BUFFER_ENABLED
++# define gcdSHARED_RESOLVE_BUFFER_ENABLED 0
++#endif
++
++/*
++ gcdUSE_TRIANGLE_STRIP_PATCH
++ */
++#ifndef gcdUSE_TRIANGLE_STRIP_PATCH
++# define gcdUSE_TRIANGLE_STRIP_PATCH 1
++#endif
++
++/*
++ gcdENABLE_OUTER_CACHE_PATCH
++
++ Enable the outer cache patch.
++*/
++#ifndef gcdENABLE_OUTER_CACHE_PATCH
++# define gcdENABLE_OUTER_CACHE_PATCH 0
++#endif
++
++#ifndef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
++# ifdef ANDROID
++# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 1
++# else
++# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 0
++# endif
++#endif
++
++#ifndef gcdENABLE_PE_DITHER_FIX
++# define gcdENABLE_PE_DITHER_FIX 1
++#endif
++
++#ifndef gcdSHARED_PAGETABLE
++# define gcdSHARED_PAGETABLE 1
++#endif
++#ifndef gcdUSE_PVR
++# define gcdUSE_PVR 1
++#endif
++
++/*
++ gcdSMALL_BLOCK_SIZE
++
++ When non-zero, a part of VIDMEM will be reserved for requests
++ whose requesting size is less than gcdSMALL_BLOCK_SIZE.
++
++ For Linux, it's the size of a page. If this requeset fallbacks
++ to gcvPOOL_CONTIGUOUS or gcvPOOL_VIRTUAL, memory will be wasted
++ because they allocate a page at least.
++ */
++#ifndef gcdSMALL_BLOCK_SIZE
++# define gcdSMALL_BLOCK_SIZE 4096
++# define gcdRATIO_FOR_SMALL_MEMORY 32
++#endif
++
++/*
++ gcdCONTIGUOUS_SIZE_LIMIT
++ When non-zero, size of video node from gcvPOOL_CONTIGUOUS is
++ limited by gcdCONTIGUOUS_SIZE_LIMIT.
++ */
++#ifndef gcdCONTIGUOUS_SIZE_LIMIT
++# define gcdCONTIGUOUS_SIZE_LIMIT 0
++#endif
++
++#ifndef gcdDISALBE_EARLY_EARLY_Z
++# define gcdDISALBE_EARLY_EARLY_Z 1
++#endif
++
++#ifndef gcdSHADER_SRC_BY_MACHINECODE
++# define gcdSHADER_SRC_BY_MACHINECODE 1
++#endif
++
++/*
++ gcdLINK_QUEUE_SIZE
++
++ When non-zero, driver maintains a queue to record information of
++ latest lined context buffer and command buffer. Data in this queue
++ is be used to debug.
++*/
++#ifndef gcdLINK_QUEUE_SIZE
++# define gcdLINK_QUEUE_SIZE 0
++#endif
++
++/* gcdALPHA_KILL_IN_SHADER
++ *
++ * Enable alpha kill inside the shader. This will be set automatically by the
++ * HAL if certain states match a criteria.
++ */
++#ifndef gcdALPHA_KILL_IN_SHADER
++# define gcdALPHA_KILL_IN_SHADER 1
++#endif
++
++/* gcdHIGH_PRECISION_DELAY_ENABLE
++ *
++ * Enable high precision schedule delay with 1ms unit. otherwise schedule delay up to 10ms.
++ * Browser app performance will have obvious drop without this enablement
++ */
++#ifndef gcdHIGH_PRECISION_DELAY_ENABLE
++# define gcdHIGH_PRECISION_DELAY_ENABLE 1
++#endif
++
++#ifndef gcdUSE_WCLIP_PATCH
++# define gcdUSE_WCLIP_PATCH 1
++#endif
++
++#ifndef gcdHZ_L2_DISALBE
++# define gcdHZ_L2_DISALBE 1
++#endif
++
++#ifndef gcdBUGFIX15_DISABLE
++# define gcdBUGFIX15_DISABLE 1
++#endif
++
++#ifndef gcdDISABLE_HZ_FAST_CLEAR
++# define gcdDISABLE_HZ_FAST_CLEAR 1
++#endif
++
++#ifndef gcdUSE_NPOT_PATCH
++#define gcdUSE_NPOT_PATCH 1
++#endif
++
++#ifndef gcdSYNC
++# define gcdSYNC 1
++#endif
++
++#ifndef gcdENABLE_SPECIAL_HINT3
++# define gcdENABLE_SPECIAL_HINT3 1
++#endif
++
++#if defined(ANDROID)
++#ifndef gcdPRE_ROTATION
++# define gcdPRE_ROTATION 1
++#endif
++#endif
++
++/*
++ gcdDVFS
++
++ When non-zero, software will make use of dynamic voltage and
++ frequency feature.
++ */
++#ifndef gcdDVFS
++# define gcdDVFS 0
++# define gcdDVFS_ANAYLSE_WINDOW 4
++# define gcdDVFS_POLLING_TIME (gcdDVFS_ANAYLSE_WINDOW * 4)
++#endif
++
++/*
++ gcdANDROID_NATIVE_FENCE_SYNC
++
++ Enable android native fence sync. It is introduced since jellybean-4.2.
++ Depends on linux kernel option: CONFIG_SYNC.
++
++ 0: Disabled
++ 1: Build framework for native fence sync feature, and EGL extension
++ 2: Enable async swap buffers for client
++ * Native fence sync for client 'queueBuffer' in EGL, which is
++ 'acquireFenceFd' for layer in compositor side.
++ 3. Enable async hwcomposer composition.
++ * 'releaseFenceFd' for layer in compositor side, which is native
++ fence sync when client 'dequeueBuffer'
++ * Native fence sync for compositor 'queueBuffer' in EGL, which is
++ 'acquireFenceFd' for framebuffer target for DC
++ */
++#ifndef gcdANDROID_NATIVE_FENCE_SYNC
++# define gcdANDROID_NATIVE_FENCE_SYNC 0
++#endif
++
++#ifndef gcdFORCE_MIPMAP
++# define gcdFORCE_MIPMAP 0
++#endif
++
++/*
++ gcdFORCE_GAL_LOAD_TWICE
++
++ When non-zero, each thread except the main one will load libGAL.so twice to avoid potential segmetantion fault when app using dlopen/dlclose.
++ If threads exit arbitrarily, libGAL.so may not unload until the process quit.
++ */
++#ifndef gcdFORCE_GAL_LOAD_TWICE
++# define gcdFORCE_GAL_LOAD_TWICE 0
++#endif
++
++#endif /* __gc_hal_options_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,584 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_profiler_h_
++#define __gc_hal_profiler_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define GLVERTEX_OBJECT 10
++#define GLVERTEX_OBJECT_BYTES 11
++
++#define GLINDEX_OBJECT 20
++#define GLINDEX_OBJECT_BYTES 21
++
++#define GLTEXTURE_OBJECT 30
++#define GLTEXTURE_OBJECT_BYTES 31
++
++#if VIVANTE_PROFILER
++#define gcmPROFILE_GC(Enum, Value) gcoPROFILER_Count(gcvNULL, Enum, Value)
++#else
++#define gcmPROFILE_GC(Enum, Value) do { } while (gcvFALSE)
++#endif
++
++#ifndef gcdNEW_PROFILER_FILE
++#define gcdNEW_PROFILER_FILE 1
++#endif
++
++#define ES11_CALLS 151
++#define ES11_DRAWCALLS (ES11_CALLS + 1)
++#define ES11_STATECHANGECALLS (ES11_DRAWCALLS + 1)
++#define ES11_POINTCOUNT (ES11_STATECHANGECALLS + 1)
++#define ES11_LINECOUNT (ES11_POINTCOUNT + 1)
++#define ES11_TRIANGLECOUNT (ES11_LINECOUNT + 1)
++
++#define ES20_CALLS 159
++#define ES20_DRAWCALLS (ES20_CALLS + 1)
++#define ES20_STATECHANGECALLS (ES20_DRAWCALLS + 1)
++#define ES20_POINTCOUNT (ES20_STATECHANGECALLS + 1)
++#define ES20_LINECOUNT (ES20_POINTCOUNT + 1)
++#define ES20_TRIANGLECOUNT (ES20_LINECOUNT + 1)
++
++#define VG11_CALLS 88
++#define VG11_DRAWCALLS (VG11_CALLS + 1)
++#define VG11_STATECHANGECALLS (VG11_DRAWCALLS + 1)
++#define VG11_FILLCOUNT (VG11_STATECHANGECALLS + 1)
++#define VG11_STROKECOUNT (VG11_FILLCOUNT + 1)
++/* End of Driver API ID Definitions. */
++
++/* HAL & MISC IDs. */
++#define HAL_VERTBUFNEWBYTEALLOC 1
++#define HAL_VERTBUFTOTALBYTEALLOC (HAL_VERTBUFNEWBYTEALLOC + 1)
++#define HAL_VERTBUFNEWOBJALLOC (HAL_VERTBUFTOTALBYTEALLOC + 1)
++#define HAL_VERTBUFTOTALOBJALLOC (HAL_VERTBUFNEWOBJALLOC + 1)
++#define HAL_INDBUFNEWBYTEALLOC (HAL_VERTBUFTOTALOBJALLOC + 1)
++#define HAL_INDBUFTOTALBYTEALLOC (HAL_INDBUFNEWBYTEALLOC + 1)
++#define HAL_INDBUFNEWOBJALLOC (HAL_INDBUFTOTALBYTEALLOC + 1)
++#define HAL_INDBUFTOTALOBJALLOC (HAL_INDBUFNEWOBJALLOC + 1)
++#define HAL_TEXBUFNEWBYTEALLOC (HAL_INDBUFTOTALOBJALLOC + 1)
++#define HAL_TEXBUFTOTALBYTEALLOC (HAL_TEXBUFNEWBYTEALLOC + 1)
++#define HAL_TEXBUFNEWOBJALLOC (HAL_TEXBUFTOTALBYTEALLOC + 1)
++#define HAL_TEXBUFTOTALOBJALLOC (HAL_TEXBUFNEWOBJALLOC + 1)
++
++#define GPU_CYCLES 1
++#define GPU_READ64BYTE (GPU_CYCLES + 1)
++#define GPU_WRITE64BYTE (GPU_READ64BYTE + 1)
++#define GPU_TOTALCYCLES (GPU_WRITE64BYTE + 1)
++#define GPU_IDLECYCLES (GPU_TOTALCYCLES + 1)
++
++#define VS_INSTCOUNT 1
++#define VS_BRANCHINSTCOUNT (VS_INSTCOUNT + 1)
++#define VS_TEXLDINSTCOUNT (VS_BRANCHINSTCOUNT + 1)
++#define VS_RENDEREDVERTCOUNT (VS_TEXLDINSTCOUNT + 1)
++#define VS_SOURCE (VS_RENDEREDVERTCOUNT + 1)
++
++#define PS_INSTCOUNT 1
++#define PS_BRANCHINSTCOUNT (PS_INSTCOUNT + 1)
++#define PS_TEXLDINSTCOUNT (PS_BRANCHINSTCOUNT + 1)
++#define PS_RENDEREDPIXCOUNT (PS_TEXLDINSTCOUNT + 1)
++#define PS_SOURCE (PS_RENDEREDPIXCOUNT + 1)
++
++#define PA_INVERTCOUNT 1
++#define PA_INPRIMCOUNT (PA_INVERTCOUNT + 1)
++#define PA_OUTPRIMCOUNT (PA_INPRIMCOUNT + 1)
++#define PA_DEPTHCLIPCOUNT (PA_OUTPRIMCOUNT + 1)
++#define PA_TRIVIALREJCOUNT (PA_DEPTHCLIPCOUNT + 1)
++#define PA_CULLCOUNT (PA_TRIVIALREJCOUNT + 1)
++
++#define SE_TRIANGLECOUNT 1
++#define SE_LINECOUNT (SE_TRIANGLECOUNT + 1)
++
++#define RA_VALIDPIXCOUNT 1
++#define RA_TOTALQUADCOUNT (RA_VALIDPIXCOUNT + 1)
++#define RA_VALIDQUADCOUNTEZ (RA_TOTALQUADCOUNT + 1)
++#define RA_TOTALPRIMCOUNT (RA_VALIDQUADCOUNTEZ + 1)
++#define RA_PIPECACHEMISSCOUNT (RA_TOTALPRIMCOUNT + 1)
++#define RA_PREFCACHEMISSCOUNT (RA_PIPECACHEMISSCOUNT + 1)
++#define RA_EEZCULLCOUNT (RA_PREFCACHEMISSCOUNT + 1)
++
++#define TX_TOTBILINEARREQ 1
++#define TX_TOTTRILINEARREQ (TX_TOTBILINEARREQ + 1)
++#define TX_TOTDISCARDTEXREQ (TX_TOTTRILINEARREQ + 1)
++#define TX_TOTTEXREQ (TX_TOTDISCARDTEXREQ + 1)
++#define TX_MEMREADCOUNT (TX_TOTTEXREQ + 1)
++#define TX_MEMREADIN8BCOUNT (TX_MEMREADCOUNT + 1)
++#define TX_CACHEMISSCOUNT (TX_MEMREADIN8BCOUNT + 1)
++#define TX_CACHEHITTEXELCOUNT (TX_CACHEMISSCOUNT + 1)
++#define TX_CACHEMISSTEXELCOUNT (TX_CACHEHITTEXELCOUNT + 1)
++
++#define PE_KILLEDBYCOLOR 1
++#define PE_KILLEDBYDEPTH (PE_KILLEDBYCOLOR + 1)
++#define PE_DRAWNBYCOLOR (PE_KILLEDBYDEPTH + 1)
++#define PE_DRAWNBYDEPTH (PE_DRAWNBYCOLOR + 1)
++
++#define MC_READREQ8BPIPE 1
++#define MC_READREQ8BIP (MC_READREQ8BPIPE + 1)
++#define MC_WRITEREQ8BPIPE (MC_READREQ8BIP + 1)
++
++#define AXI_READREQSTALLED 1
++#define AXI_WRITEREQSTALLED (AXI_READREQSTALLED + 1)
++#define AXI_WRITEDATASTALLED (AXI_WRITEREQSTALLED + 1)
++
++#define PVS_INSTRCOUNT 1
++#define PVS_ALUINSTRCOUNT (PVS_INSTRCOUNT + 1)
++#define PVS_TEXINSTRCOUNT (PVS_ALUINSTRCOUNT + 1)
++#define PVS_ATTRIBCOUNT (PVS_TEXINSTRCOUNT + 1)
++#define PVS_UNIFORMCOUNT (PVS_ATTRIBCOUNT + 1)
++#define PVS_FUNCTIONCOUNT (PVS_UNIFORMCOUNT + 1)
++#define PVS_SOURCE (PVS_FUNCTIONCOUNT + 1)
++
++#define PPS_INSTRCOUNT 1
++#define PPS_ALUINSTRCOUNT (PPS_INSTRCOUNT + 1)
++#define PPS_TEXINSTRCOUNT (PPS_ALUINSTRCOUNT + 1)
++#define PPS_ATTRIBCOUNT (PPS_TEXINSTRCOUNT + 1)
++#define PPS_UNIFORMCOUNT (PPS_ATTRIBCOUNT + 1)
++#define PPS_FUNCTIONCOUNT (PPS_UNIFORMCOUNT + 1)
++#define PPS_SOURCE (PPS_FUNCTIONCOUNT + 1)
++/* End of MISC Counter IDs. */
++
++#ifdef gcdNEW_PROFILER_FILE
++
++/* Category Constants. */
++#define VPHEADER 0x010000
++#define VPG_INFO 0x020000
++#define VPG_TIME 0x030000
++#define VPG_MEM 0x040000
++#define VPG_ES11 0x050000
++#define VPG_ES20 0x060000
++#define VPG_VG11 0x070000
++#define VPG_HAL 0x080000
++#define VPG_HW 0x090000
++#define VPG_GPU 0x0a0000
++#define VPG_VS 0x0b0000
++#define VPG_PS 0x0c0000
++#define VPG_PA 0x0d0000
++#define VPG_SETUP 0x0e0000
++#define VPG_RA 0x0f0000
++#define VPG_TX 0x100000
++#define VPG_PE 0x110000
++#define VPG_MC 0x120000
++#define VPG_AXI 0x130000
++#define VPG_PROG 0x140000
++#define VPG_PVS 0x150000
++#define VPG_PPS 0x160000
++#define VPG_ES11_TIME 0x170000
++#define VPG_ES20_TIME 0x180000
++#define VPG_FRAME 0x190000
++#define VPG_ES11_DRAW 0x200000
++#define VPG_ES20_DRAW 0x210000
++#define VPG_END 0xff0000
++
++/* Info. */
++#define VPC_INFOCOMPANY (VPG_INFO + 1)
++#define VPC_INFOVERSION (VPC_INFOCOMPANY + 1)
++#define VPC_INFORENDERER (VPC_INFOVERSION + 1)
++#define VPC_INFOREVISION (VPC_INFORENDERER + 1)
++#define VPC_INFODRIVER (VPC_INFOREVISION + 1)
++#define VPC_INFODRIVERMODE (VPC_INFODRIVER + 1)
++#define VPC_INFOSCREENSIZE (VPC_INFODRIVERMODE + 1)
++
++/* Counter Constants. */
++#define VPC_ELAPSETIME (VPG_TIME + 1)
++#define VPC_CPUTIME (VPC_ELAPSETIME + 1)
++
++#define VPC_MEMMAXRES (VPG_MEM + 1)
++#define VPC_MEMSHARED (VPC_MEMMAXRES + 1)
++#define VPC_MEMUNSHAREDDATA (VPC_MEMSHARED + 1)
++#define VPC_MEMUNSHAREDSTACK (VPC_MEMUNSHAREDDATA + 1)
++
++/* OpenGL ES11 Statics Counter IDs. */
++#define VPC_ES11CALLS (VPG_ES11 + ES11_CALLS)
++#define VPC_ES11DRAWCALLS (VPG_ES11 + ES11_DRAWCALLS)
++#define VPC_ES11STATECHANGECALLS (VPG_ES11 + ES11_STATECHANGECALLS)
++#define VPC_ES11POINTCOUNT (VPG_ES11 + ES11_POINTCOUNT)
++#define VPC_ES11LINECOUNT (VPG_ES11 + ES11_LINECOUNT)
++#define VPC_ES11TRIANGLECOUNT (VPG_ES11 + ES11_TRIANGLECOUNT)
++
++/* OpenGL ES20 Statistics Counter IDs. */
++#define VPC_ES20CALLS (VPG_ES20 + ES20_CALLS)
++#define VPC_ES20DRAWCALLS (VPG_ES20 + ES20_DRAWCALLS)
++#define VPC_ES20STATECHANGECALLS (VPG_ES20 + ES20_STATECHANGECALLS)
++#define VPC_ES20POINTCOUNT (VPG_ES20 + ES20_POINTCOUNT)
++#define VPC_ES20LINECOUNT (VPG_ES20 + ES20_LINECOUNT)
++#define VPC_ES20TRIANGLECOUNT (VPG_ES20 + ES20_TRIANGLECOUNT)
++
++/* OpenVG Statistics Counter IDs. */
++#define VPC_VG11CALLS (VPG_VG11 + VG11_CALLS)
++#define VPC_VG11DRAWCALLS (VPG_VG11 + VG11_DRAWCALLS)
++#define VPC_VG11STATECHANGECALLS (VPG_VG11 + VG11_STATECHANGECALLS)
++#define VPC_VG11FILLCOUNT (VPG_VG11 + VG11_FILLCOUNT)
++#define VPC_VG11STROKECOUNT (VPG_VG11 + VG11_STROKECOUNT)
++
++/* HAL Counters. */
++#define VPC_HALVERTBUFNEWBYTEALLOC (VPG_HAL + HAL_VERTBUFNEWBYTEALLOC)
++#define VPC_HALVERTBUFTOTALBYTEALLOC (VPG_HAL + HAL_VERTBUFTOTALBYTEALLOC)
++#define VPC_HALVERTBUFNEWOBJALLOC (VPG_HAL + HAL_VERTBUFNEWOBJALLOC)
++#define VPC_HALVERTBUFTOTALOBJALLOC (VPG_HAL + HAL_VERTBUFTOTALOBJALLOC)
++#define VPC_HALINDBUFNEWBYTEALLOC (VPG_HAL + HAL_INDBUFNEWBYTEALLOC)
++#define VPC_HALINDBUFTOTALBYTEALLOC (VPG_HAL + HAL_INDBUFTOTALBYTEALLOC)
++#define VPC_HALINDBUFNEWOBJALLOC (VPG_HAL + HAL_INDBUFNEWOBJALLOC)
++#define VPC_HALINDBUFTOTALOBJALLOC (VPG_HAL + HAL_INDBUFTOTALOBJALLOC)
++#define VPC_HALTEXBUFNEWBYTEALLOC (VPG_HAL + HAL_TEXBUFNEWBYTEALLOC)
++#define VPC_HALTEXBUFTOTALBYTEALLOC (VPG_HAL + HAL_TEXBUFTOTALBYTEALLOC)
++#define VPC_HALTEXBUFNEWOBJALLOC (VPG_HAL + HAL_TEXBUFNEWOBJALLOC)
++#define VPC_HALTEXBUFTOTALOBJALLOC (VPG_HAL + HAL_TEXBUFTOTALOBJALLOC)
++
++/* HW: GPU Counters. */
++#define VPC_GPUCYCLES (VPG_GPU + GPU_CYCLES)
++#define VPC_GPUREAD64BYTE (VPG_GPU + GPU_READ64BYTE)
++#define VPC_GPUWRITE64BYTE (VPG_GPU + GPU_WRITE64BYTE)
++#define VPC_GPUTOTALCYCLES (VPG_GPU + GPU_TOTALCYCLES)
++#define VPC_GPUIDLECYCLES (VPG_GPU + GPU_IDLECYCLES)
++
++/* HW: Shader Counters. */
++#define VPC_VSINSTCOUNT (VPG_VS + VS_INSTCOUNT)
++#define VPC_VSBRANCHINSTCOUNT (VPG_VS + VS_BRANCHINSTCOUNT)
++#define VPC_VSTEXLDINSTCOUNT (VPG_VS + VS_TEXLDINSTCOUNT)
++#define VPC_VSRENDEREDVERTCOUNT (VPG_VS + VS_RENDEREDVERTCOUNT)
++/* HW: PS Count. */
++#define VPC_PSINSTCOUNT (VPG_PS + PS_INSTCOUNT)
++#define VPC_PSBRANCHINSTCOUNT (VPG_PS + PS_BRANCHINSTCOUNT)
++#define VPC_PSTEXLDINSTCOUNT (VPG_PS + PS_TEXLDINSTCOUNT)
++#define VPC_PSRENDEREDPIXCOUNT (VPG_PS + PS_RENDEREDPIXCOUNT)
++
++
++/* HW: PA Counters. */
++#define VPC_PAINVERTCOUNT (VPG_PA + PA_INVERTCOUNT)
++#define VPC_PAINPRIMCOUNT (VPG_PA + PA_INPRIMCOUNT)
++#define VPC_PAOUTPRIMCOUNT (VPG_PA + PA_OUTPRIMCOUNT)
++#define VPC_PADEPTHCLIPCOUNT (VPG_PA + PA_DEPTHCLIPCOUNT)
++#define VPC_PATRIVIALREJCOUNT (VPG_PA + PA_TRIVIALREJCOUNT)
++#define VPC_PACULLCOUNT (VPG_PA + PA_CULLCOUNT)
++
++/* HW: Setup Counters. */
++#define VPC_SETRIANGLECOUNT (VPG_SETUP + SE_TRIANGLECOUNT)
++#define VPC_SELINECOUNT (VPG_SETUP + SE_LINECOUNT)
++
++/* HW: RA Counters. */
++#define VPC_RAVALIDPIXCOUNT (VPG_RA + RA_VALIDPIXCOUNT)
++#define VPC_RATOTALQUADCOUNT (VPG_RA + RA_TOTALQUADCOUNT)
++#define VPC_RAVALIDQUADCOUNTEZ (VPG_RA + RA_VALIDQUADCOUNTEZ)
++#define VPC_RATOTALPRIMCOUNT (VPG_RA + RA_TOTALPRIMCOUNT)
++#define VPC_RAPIPECACHEMISSCOUNT (VPG_RA + RA_PIPECACHEMISSCOUNT)
++#define VPC_RAPREFCACHEMISSCOUNT (VPG_RA + RA_PREFCACHEMISSCOUNT)
++#define VPC_RAEEZCULLCOUNT (VPG_RA + RA_EEZCULLCOUNT)
++
++/* HW: TEX Counters. */
++#define VPC_TXTOTBILINEARREQ (VPG_TX + TX_TOTBILINEARREQ)
++#define VPC_TXTOTTRILINEARREQ (VPG_TX + TX_TOTTRILINEARREQ)
++#define VPC_TXTOTDISCARDTEXREQ (VPG_TX + TX_TOTDISCARDTEXREQ)
++#define VPC_TXTOTTEXREQ (VPG_TX + TX_TOTTEXREQ)
++#define VPC_TXMEMREADCOUNT (VPG_TX + TX_MEMREADCOUNT)
++#define VPC_TXMEMREADIN8BCOUNT (VPG_TX + TX_MEMREADIN8BCOUNT)
++#define VPC_TXCACHEMISSCOUNT (VPG_TX + TX_CACHEMISSCOUNT)
++#define VPC_TXCACHEHITTEXELCOUNT (VPG_TX + TX_CACHEHITTEXELCOUNT)
++#define VPC_TXCACHEMISSTEXELCOUNT (VPG_TX + TX_CACHEMISSTEXELCOUNT)
++
++/* HW: PE Counters. */
++#define VPC_PEKILLEDBYCOLOR (VPG_PE + PE_KILLEDBYCOLOR)
++#define VPC_PEKILLEDBYDEPTH (VPG_PE + PE_KILLEDBYDEPTH)
++#define VPC_PEDRAWNBYCOLOR (VPG_PE + PE_DRAWNBYCOLOR)
++#define VPC_PEDRAWNBYDEPTH (VPG_PE + PE_DRAWNBYDEPTH)
++
++/* HW: MC Counters. */
++#define VPC_MCREADREQ8BPIPE (VPG_MC + MC_READREQ8BPIPE)
++#define VPC_MCREADREQ8BIP (VPG_MC + MC_READREQ8BIP)
++#define VPC_MCWRITEREQ8BPIPE (VPG_MC + MC_WRITEREQ8BPIPE)
++
++/* HW: AXI Counters. */
++#define VPC_AXIREADREQSTALLED (VPG_AXI + AXI_READREQSTALLED)
++#define VPC_AXIWRITEREQSTALLED (VPG_AXI + AXI_WRITEREQSTALLED)
++#define VPC_AXIWRITEDATASTALLED (VPG_AXI + AXI_WRITEDATASTALLED)
++
++/* PROGRAM: Shader program counters. */
++#define VPC_PVSINSTRCOUNT (VPG_PVS + PVS_INSTRCOUNT)
++#define VPC_PVSALUINSTRCOUNT (VPG_PVS + PVS_ALUINSTRCOUNT)
++#define VPC_PVSTEXINSTRCOUNT (VPG_PVS + PVS_TEXINSTRCOUNT)
++#define VPC_PVSATTRIBCOUNT (VPG_PVS + PVS_ATTRIBCOUNT)
++#define VPC_PVSUNIFORMCOUNT (VPG_PVS + PVS_UNIFORMCOUNT)
++#define VPC_PVSFUNCTIONCOUNT (VPG_PVS + PVS_FUNCTIONCOUNT)
++#define VPC_PVSSOURCE (VPG_PVS + PVS_SOURCE)
++
++#define VPC_PPSINSTRCOUNT (VPG_PPS + PPS_INSTRCOUNT)
++#define VPC_PPSALUINSTRCOUNT (VPG_PPS + PPS_ALUINSTRCOUNT)
++#define VPC_PPSTEXINSTRCOUNT (VPG_PPS + PPS_TEXINSTRCOUNT)
++#define VPC_PPSATTRIBCOUNT (VPG_PPS + PPS_ATTRIBCOUNT)
++#define VPC_PPSUNIFORMCOUNT (VPG_PPS + PPS_UNIFORMCOUNT)
++#define VPC_PPSFUNCTIONCOUNT (VPG_PPS + PPS_FUNCTIONCOUNT)
++#define VPC_PPSSOURCE (VPG_PPS + PPS_SOURCE)
++
++#define VPC_PROGRAMHANDLE (VPG_PROG + 1)
++
++#define VPG_ES20_DRAW_NO (VPG_ES20_DRAW + 1)
++#define VPG_ES11_DRAW_NO (VPG_ES11_DRAW + 1)
++
++#define VPG_FRAME_USEVBO (VPG_FRAME + 1)
++
++#endif
++
++
++/* HW profile information. */
++typedef struct _gcsPROFILER_COUNTERS
++{
++ /* HW static counters. */
++ gctUINT32 gpuClock;
++ gctUINT32 axiClock;
++ gctUINT32 shaderClock;
++
++ /* HW vairable counters. */
++ gctUINT32 gpuClockStart;
++ gctUINT32 gpuClockEnd;
++
++ /* HW vairable counters. */
++ gctUINT32 gpuCyclesCounter;
++ gctUINT32 gpuTotalCyclesCounter;
++ gctUINT32 gpuIdleCyclesCounter;
++ gctUINT32 gpuTotalRead64BytesPerFrame;
++ gctUINT32 gpuTotalWrite64BytesPerFrame;
++
++ /* PE */
++ gctUINT32 pe_pixel_count_killed_by_color_pipe;
++ gctUINT32 pe_pixel_count_killed_by_depth_pipe;
++ gctUINT32 pe_pixel_count_drawn_by_color_pipe;
++ gctUINT32 pe_pixel_count_drawn_by_depth_pipe;
++
++ /* SH */
++ gctUINT32 ps_inst_counter;
++ gctUINT32 rendered_pixel_counter;
++ gctUINT32 vs_inst_counter;
++ gctUINT32 rendered_vertice_counter;
++ gctUINT32 vtx_branch_inst_counter;
++ gctUINT32 vtx_texld_inst_counter;
++ gctUINT32 pxl_branch_inst_counter;
++ gctUINT32 pxl_texld_inst_counter;
++
++ /* PA */
++ gctUINT32 pa_input_vtx_counter;
++ gctUINT32 pa_input_prim_counter;
++ gctUINT32 pa_output_prim_counter;
++ gctUINT32 pa_depth_clipped_counter;
++ gctUINT32 pa_trivial_rejected_counter;
++ gctUINT32 pa_culled_counter;
++
++ /* SE */
++ gctUINT32 se_culled_triangle_count;
++ gctUINT32 se_culled_lines_count;
++
++ /* RA */
++ gctUINT32 ra_valid_pixel_count;
++ gctUINT32 ra_total_quad_count;
++ gctUINT32 ra_valid_quad_count_after_early_z;
++ gctUINT32 ra_total_primitive_count;
++ gctUINT32 ra_pipe_cache_miss_counter;
++ gctUINT32 ra_prefetch_cache_miss_counter;
++ gctUINT32 ra_eez_culled_counter;
++
++ /* TX */
++ gctUINT32 tx_total_bilinear_requests;
++ gctUINT32 tx_total_trilinear_requests;
++ gctUINT32 tx_total_discarded_texture_requests;
++ gctUINT32 tx_total_texture_requests;
++ gctUINT32 tx_mem_read_count;
++ gctUINT32 tx_mem_read_in_8B_count;
++ gctUINT32 tx_cache_miss_count;
++ gctUINT32 tx_cache_hit_texel_count;
++ gctUINT32 tx_cache_miss_texel_count;
++
++ /* MC */
++ gctUINT32 mc_total_read_req_8B_from_pipeline;
++ gctUINT32 mc_total_read_req_8B_from_IP;
++ gctUINT32 mc_total_write_req_8B_from_pipeline;
++
++ /* HI */
++ gctUINT32 hi_axi_cycles_read_request_stalled;
++ gctUINT32 hi_axi_cycles_write_request_stalled;
++ gctUINT32 hi_axi_cycles_write_data_stalled;
++}
++gcsPROFILER_COUNTERS;
++
++/* HAL profile information. */
++typedef struct _gcsPROFILER
++{
++ gctUINT32 enable;
++ gctBOOL enableHal;
++ gctBOOL enableHW;
++ gctBOOL enableSH;
++ gctBOOL isSyncMode;
++
++ gctBOOL useSocket;
++ gctINT sockFd;
++
++ gctFILE file;
++
++ /* Aggregate Information */
++
++ /* Clock Info */
++ gctUINT64 frameStart;
++ gctUINT64 frameEnd;
++
++ /* Current frame information */
++ gctUINT32 frameNumber;
++ gctUINT64 frameStartTimeusec;
++ gctUINT64 frameEndTimeusec;
++ gctUINT64 frameStartCPUTimeusec;
++ gctUINT64 frameEndCPUTimeusec;
++
++#if PROFILE_HAL_COUNTERS
++ gctUINT32 vertexBufferTotalBytesAlloc;
++ gctUINT32 vertexBufferNewBytesAlloc;
++ int vertexBufferTotalObjectsAlloc;
++ int vertexBufferNewObjectsAlloc;
++
++ gctUINT32 indexBufferTotalBytesAlloc;
++ gctUINT32 indexBufferNewBytesAlloc;
++ int indexBufferTotalObjectsAlloc;
++ int indexBufferNewObjectsAlloc;
++
++ gctUINT32 textureBufferTotalBytesAlloc;
++ gctUINT32 textureBufferNewBytesAlloc;
++ int textureBufferTotalObjectsAlloc;
++ int textureBufferNewObjectsAlloc;
++
++ gctUINT32 numCommits;
++ gctUINT32 drawPointCount;
++ gctUINT32 drawLineCount;
++ gctUINT32 drawTriangleCount;
++ gctUINT32 drawVertexCount;
++ gctUINT32 redundantStateChangeCalls;
++#endif
++
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++
++ char* psSource;
++ char* vsSource;
++
++}
++gcsPROFILER;
++
++/* Memory profile information. */
++struct _gcsMemProfile
++{
++ /* Memory Usage */
++ gctUINT32 videoMemUsed;
++ gctUINT32 systemMemUsed;
++ gctUINT32 commitBufferSize;
++ gctUINT32 contextBufferCopyBytes;
++};
++
++/* Shader profile information. */
++struct _gcsSHADER_PROFILER
++{
++ gctUINT32 shaderLength;
++ gctUINT32 shaderALUCycles;
++ gctUINT32 shaderTexLoadCycles;
++ gctUINT32 shaderTempRegCount;
++ gctUINT32 shaderSamplerRegCount;
++ gctUINT32 shaderInputRegCount;
++ gctUINT32 shaderOutputRegCount;
++};
++
++/* Initialize the gcsProfiler. */
++gceSTATUS
++gcoPROFILER_Initialize(
++ IN gcoHAL Hal
++ );
++
++/* Destroy the gcProfiler. */
++gceSTATUS
++gcoPROFILER_Destroy(
++ IN gcoHAL Hal
++ );
++
++/* Write data to profiler. */
++gceSTATUS
++gcoPROFILER_Write(
++ IN gcoHAL Hal,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Flush data out. */
++gceSTATUS
++gcoPROFILER_Flush(
++ IN gcoHAL Hal
++ );
++
++/* Call to signal end of frame. */
++gceSTATUS
++gcoPROFILER_EndFrame(
++ IN gcoHAL Hal
++ );
++
++/* Call to signal end of draw. */
++gceSTATUS
++gcoPROFILER_EndDraw(
++ IN gcoHAL Hal,
++ IN gctBOOL FirstDraw
++ );
++
++/* Increase profile counter Enum by Value. */
++gceSTATUS
++gcoPROFILER_Count(
++ IN gcoHAL Hal,
++ IN gctUINT32 Enum,
++ IN gctINT Value
++ );
++
++gceSTATUS
++gcoPROFILER_ShaderSourceFS(
++ IN gcoHAL Hal,
++ IN char* source
++ );
++
++gceSTATUS
++gcoPROFILER_ShaderSourceVS(
++ IN gcoHAL Hal,
++ IN char* source
++ );
++
++/* Profile input vertex shader. */
++gceSTATUS
++gcoPROFILER_ShaderVS(
++ IN gcoHAL Hal,
++ IN gctPOINTER Vs
++ );
++
++/* Profile input fragment shader. */
++gceSTATUS
++gcoPROFILER_ShaderFS(
++ IN gcoHAL Hal,
++ IN gctPOINTER Fs
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_profiler_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,1010 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_raster_h_
++#define __gc_hal_raster_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gcoBRUSH * gcoBRUSH;
++typedef struct _gcoBRUSH_CACHE * gcoBRUSH_CACHE;
++
++/******************************************************************************\
++******************************** gcoBRUSH Object *******************************
++\******************************************************************************/
++
++/* Create a new solid color gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructSingleColor(
++ IN gcoHAL Hal,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a new monochrome gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructMonochrome(
++ IN gcoHAL Hal,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a color gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructColor(
++ IN gcoHAL Hal,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctPOINTER Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Destroy an gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_Destroy(
++ IN gcoBRUSH Brush
++ );
++
++/******************************************************************************\
++******************************** gcoSURF Object *******************************
++\******************************************************************************/
++
++/* Set cipping rectangle. */
++gceSTATUS
++gcoSURF_SetClipping(
++ IN gcoSURF Surface
++ );
++
++/* Clear one or more rectangular areas. */
++gceSTATUS
++gcoSURF_Clear2D(
++ IN gcoSURF DestSurface,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 LoColor,
++ IN gctUINT32 HiColor
++ );
++
++/* Draw one or more Bresenham lines. */
++gceSTATUS
++gcoSURF_Line(
++ IN gcoSURF Surface,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++/* Generic rectangular blit. */
++gceSTATUS
++gcoSURF_Blit(
++ IN OPTIONAL gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 RectCount,
++ IN OPTIONAL gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN OPTIONAL gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN OPTIONAL gceSURF_TRANSPARENCY Transparency,
++ IN OPTIONAL gctUINT32 TransparencyColor,
++ IN OPTIONAL gctPOINTER Mask,
++ IN OPTIONAL gceSURF_MONOPACK MaskPack
++ );
++
++/* Monochrome blit. */
++gceSTATUS
++gcoSURF_MonoBlit(
++ IN gcoSURF DestSurface,
++ IN gctPOINTER Source,
++ IN gceSURF_MONOPACK SourcePack,
++ IN gcsPOINT_PTR SourceSize,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsRECT_PTR DestRect,
++ IN OPTIONAL gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gctBOOL ColorConvert,
++ IN gctUINT8 MonoTransparency,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor
++ );
++
++/* Filter blit. */
++gceSTATUS
++gcoSURF_FilterBlit(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
++gceSTATUS
++gcoSURF_EnableAlphaBlend(
++ IN gcoSURF Surface,
++ IN gctUINT8 SrcGlobalAlphaValue,
++ IN gctUINT8 DstGlobalAlphaValue,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
++ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
++ IN gceSURF_PIXEL_COLOR_MODE DstColorMode
++ );
++
++/* Disable alpha blending engine in the hardware and engage the ROP engine. */
++gceSTATUS
++gcoSURF_DisableAlphaBlend(
++ IN gcoSURF Surface
++ );
++
++/* Copy a rectangular area with format conversion. */
++gceSTATUS
++gcoSURF_CopyPixels(
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctINT SourceX,
++ IN gctINT SourceY,
++ IN gctINT TargetX,
++ IN gctINT TargetY,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++/* Read surface pixel. */
++gceSTATUS
++gcoSURF_ReadPixel(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gceSURF_FORMAT Format,
++ OUT gctPOINTER PixelValue
++ );
++
++/* Write surface pixel. */
++gceSTATUS
++gcoSURF_WritePixel(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gceSURF_FORMAT Format,
++ IN gctPOINTER PixelValue
++ );
++
++gceSTATUS
++gcoSURF_SetDither(
++ IN gcoSURF Surface,
++ IN gctBOOL Dither
++ );
++/******************************************************************************\
++********************************** gco2D Object *********************************
++\******************************************************************************/
++
++/* Construct a new gco2D object. */
++gceSTATUS
++gco2D_Construct(
++ IN gcoHAL Hal,
++ OUT gco2D * Hardware
++ );
++
++/* Destroy an gco2D object. */
++gceSTATUS
++gco2D_Destroy(
++ IN gco2D Hardware
++ );
++
++/* Sets the maximum number of brushes in the brush cache. */
++gceSTATUS
++gco2D_SetBrushLimit(
++ IN gco2D Hardware,
++ IN gctUINT MaxCount
++ );
++
++/* Flush the brush. */
++gceSTATUS
++gco2D_FlushBrush(
++ IN gco2D Engine,
++ IN gcoBRUSH Brush,
++ IN gceSURF_FORMAT Format
++ );
++
++/* Program the specified solid color brush. */
++gceSTATUS
++gco2D_LoadSolidBrush(
++ IN gco2D Engine,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask
++ );
++
++gceSTATUS
++gco2D_LoadMonochromeBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask
++ );
++
++gceSTATUS
++gco2D_LoadColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask
++ );
++
++/* Configure monochrome source. */
++gceSTATUS
++gco2D_SetMonochromeSource(
++ IN gco2D Engine,
++ IN gctBOOL ColorConvert,
++ IN gctUINT8 MonoTransparency,
++ IN gceSURF_MONOPACK DataPack,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor
++ );
++
++/* Configure color source. */
++gceSTATUS
++gco2D_SetColorSource(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 TransparencyColor
++ );
++
++/* Configure color source extension for full rotation. */
++gceSTATUS
++gco2D_SetColorSourceEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 TransparencyColor
++ );
++
++/* Configure color source. */
++gceSTATUS
++gco2D_SetColorSourceAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctBOOL CoordRelative
++ );
++
++gceSTATUS
++gco2D_SetColorSourceN(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctUINT32 SurfaceNumber
++ );
++
++/* Configure masked color source. */
++gceSTATUS
++gco2D_SetMaskedSource(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_MONOPACK MaskPack
++ );
++
++/* Configure masked color source extension for full rotation. */
++gceSTATUS
++gco2D_SetMaskedSourceEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_MONOPACK MaskPack,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++ );
++
++/* Setup the source rectangle. */
++gceSTATUS
++gco2D_SetSource(
++ IN gco2D Engine,
++ IN gcsRECT_PTR SrcRect
++ );
++
++/* Set clipping rectangle. */
++gceSTATUS
++gco2D_SetClipping(
++ IN gco2D Engine,
++ IN gcsRECT_PTR Rect
++ );
++
++/* Configure destination. */
++gceSTATUS
++gco2D_SetTarget(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth
++ );
++
++/* Configure destination extension for full rotation. */
++gceSTATUS
++gco2D_SetTargetEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++ );
++
++/* Calculate and program the stretch factors. */
++gceSTATUS
++gco2D_CalcStretchFactor(
++ IN gco2D Engine,
++ IN gctINT32 SrcSize,
++ IN gctINT32 DestSize,
++ OUT gctUINT32_PTR Factor
++ );
++
++gceSTATUS
++gco2D_SetStretchFactors(
++ IN gco2D Engine,
++ IN gctUINT32 HorFactor,
++ IN gctUINT32 VerFactor
++ );
++
++/* Calculate and program the stretch factors based on the rectangles. */
++gceSTATUS
++gco2D_SetStretchRectFactors(
++ IN gco2D Engine,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect
++ );
++
++/* Create a new solid color gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructSingleColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a new monochrome gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructMonochromeBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a color gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctPOINTER Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Clear one or more rectangular areas. */
++gceSTATUS
++gco2D_Clear(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT32 Color32,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Draw one or more Bresenham lines. */
++gceSTATUS
++gco2D_Line(
++ IN gco2D Engine,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Draw one or more Bresenham lines based on the 32-bit color. */
++gceSTATUS
++gco2D_ColorLine(
++ IN gco2D Engine,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gctUINT32 Color32,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Generic blit. */
++gceSTATUS
++gco2D_Blit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++gceSTATUS
++gco2D_Blend(
++ IN gco2D Engine,
++ IN gctUINT32 SrcCount,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Batch blit. */
++gceSTATUS
++gco2D_BatchBlit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Stretch blit. */
++gceSTATUS
++gco2D_StretchBlit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Monochrome blit. */
++gceSTATUS
++gco2D_MonoBlit(
++ IN gco2D Engine,
++ IN gctPOINTER StreamBits,
++ IN gcsPOINT_PTR StreamSize,
++ IN gcsRECT_PTR StreamRect,
++ IN gceSURF_MONOPACK SrcStreamPack,
++ IN gceSURF_MONOPACK DestStreamPack,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 FgRop,
++ IN gctUINT32 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++gceSTATUS
++gco2D_MonoBlitEx(
++ IN gco2D Engine,
++ IN gctPOINTER StreamBits,
++ IN gctINT32 StreamStride,
++ IN gctINT32 StreamWidth,
++ IN gctINT32 StreamHeight,
++ IN gctINT32 StreamX,
++ IN gctINT32 StreamY,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DstRect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++/* Set kernel size. */
++gceSTATUS
++gco2D_SetKernelSize(
++ IN gco2D Engine,
++ IN gctUINT8 HorKernelSize,
++ IN gctUINT8 VerKernelSize
++ );
++
++/* Set filter type. */
++gceSTATUS
++gco2D_SetFilterType(
++ IN gco2D Engine,
++ IN gceFILTER_TYPE FilterType
++ );
++
++/* Set the filter kernel by user. */
++gceSTATUS
++gco2D_SetUserFilterKernel(
++ IN gco2D Engine,
++ IN gceFILTER_PASS_TYPE PassType,
++ IN gctUINT16_PTR KernelArray
++ );
++
++/* Select the pass(es) to be done for user defined filter. */
++gceSTATUS
++gco2D_EnableUserFilterPasses(
++ IN gco2D Engine,
++ IN gctBOOL HorPass,
++ IN gctBOOL VerPass
++ );
++
++/* Frees the temporary buffer allocated by filter blit operation. */
++gceSTATUS
++gco2D_FreeFilterBuffer(
++ IN gco2D Engine
++ );
++
++/* Filter blit. */
++gceSTATUS
++gco2D_FilterBlit(
++ IN gco2D Engine,
++ IN gctUINT32 SrcAddress,
++ IN gctUINT SrcStride,
++ IN gctUINT32 SrcUAddress,
++ IN gctUINT SrcUStride,
++ IN gctUINT32 SrcVAddress,
++ IN gctUINT SrcVStride,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32 DestAddress,
++ IN gctUINT DestStride,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Filter blit extension for full rotation. */
++gceSTATUS
++gco2D_FilterBlitEx(
++ IN gco2D Engine,
++ IN gctUINT32 SrcAddress,
++ IN gctUINT SrcStride,
++ IN gctUINT32 SrcUAddress,
++ IN gctUINT SrcUStride,
++ IN gctUINT32 SrcVAddress,
++ IN gctUINT SrcVStride,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gctUINT32 SrcSurfaceHeight,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32 DestAddress,
++ IN gctUINT DestStride,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gctUINT32 DestSurfaceHeight,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++gceSTATUS
++gco2D_FilterBlitEx2(
++ IN gco2D Engine,
++ IN gctUINT32_PTR SrcAddresses,
++ IN gctUINT32 SrcAddressNum,
++ IN gctUINT32_PTR SrcStrides,
++ IN gctUINT32 SrcStrideNum,
++ IN gceTILING SrcTiling,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gctUINT32 SrcSurfaceHeight,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32_PTR DestAddresses,
++ IN gctUINT32 DestAddressNum,
++ IN gctUINT32_PTR DestStrides,
++ IN gctUINT32 DestStrideNum,
++ IN gceTILING DestTiling,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gctUINT32 DestSurfaceHeight,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
++gceSTATUS
++gco2D_EnableAlphaBlend(
++ IN gco2D Engine,
++ IN gctUINT8 SrcGlobalAlphaValue,
++ IN gctUINT8 DstGlobalAlphaValue,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
++ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
++ IN gceSURF_PIXEL_COLOR_MODE DstColorMode
++ );
++
++/* Enable alpha blending engine in the hardware. */
++gceSTATUS
++gco2D_EnableAlphaBlendAdvanced(
++ IN gco2D Engine,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode
++ );
++
++/* Enable alpha blending engine with Porter Duff rule. */
++gceSTATUS
++gco2D_SetPorterDuffBlending(
++ IN gco2D Engine,
++ IN gce2D_PORTER_DUFF_RULE Rule
++ );
++
++/* Disable alpha blending engine in the hardware and engage the ROP engine. */
++gceSTATUS
++gco2D_DisableAlphaBlend(
++ IN gco2D Engine
++ );
++
++/* Retrieve the maximum number of 32-bit data chunks for a single DE command. */
++gctUINT32
++gco2D_GetMaximumDataCount(
++ void
++ );
++
++/* Retrieve the maximum number of rectangles, that can be passed in a single DE command. */
++gctUINT32
++gco2D_GetMaximumRectCount(
++ void
++ );
++
++/* Returns the pixel alignment of the surface. */
++gceSTATUS
++gco2D_GetPixelAlignment(
++ gceSURF_FORMAT Format,
++ gcsPOINT_PTR Alignment
++ );
++
++/* Retrieve monochrome stream pack size. */
++gceSTATUS
++gco2D_GetPackSize(
++ IN gceSURF_MONOPACK StreamPack,
++ OUT gctUINT32 * PackWidth,
++ OUT gctUINT32 * PackHeight
++ );
++
++/* Flush the 2D pipeline. */
++gceSTATUS
++gco2D_Flush(
++ IN gco2D Engine
++ );
++
++/* Load 256-entry color table for INDEX8 source surfaces. */
++gceSTATUS
++gco2D_LoadPalette(
++ IN gco2D Engine,
++ IN gctUINT FirstIndex,
++ IN gctUINT IndexCount,
++ IN gctPOINTER ColorTable,
++ IN gctBOOL ColorConvert
++ );
++
++/* Enable/disable 2D BitBlt mirrorring. */
++gceSTATUS
++gco2D_SetBitBlitMirror(
++ IN gco2D Engine,
++ IN gctBOOL HorizontalMirror,
++ IN gctBOOL VerticalMirror
++ );
++
++/*
++ * Set the transparency for source, destination and pattern.
++ * It also enable or disable the DFB color key mode.
++ */
++gceSTATUS
++gco2D_SetTransparencyAdvancedEx(
++ IN gco2D Engine,
++ IN gce2D_TRANSPARENCY SrcTransparency,
++ IN gce2D_TRANSPARENCY DstTransparency,
++ IN gce2D_TRANSPARENCY PatTransparency,
++ IN gctBOOL EnableDFBColorKeyMode
++ );
++
++/* Set the transparency for source, destination and pattern. */
++gceSTATUS
++gco2D_SetTransparencyAdvanced(
++ IN gco2D Engine,
++ IN gce2D_TRANSPARENCY SrcTransparency,
++ IN gce2D_TRANSPARENCY DstTransparency,
++ IN gce2D_TRANSPARENCY PatTransparency
++ );
++
++/* Set the source color key. */
++gceSTATUS
++gco2D_SetSourceColorKeyAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKey
++ );
++
++/* Set the source color key range. */
++gceSTATUS
++gco2D_SetSourceColorKeyRangeAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKeyLow,
++ IN gctUINT32 ColorKeyHigh
++ );
++
++/* Set the target color key. */
++gceSTATUS
++gco2D_SetTargetColorKeyAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKey
++ );
++
++/* Set the target color key range. */
++gceSTATUS
++gco2D_SetTargetColorKeyRangeAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKeyLow,
++ IN gctUINT32 ColorKeyHigh
++ );
++
++/* Set the YUV color space mode. */
++gceSTATUS
++gco2D_SetYUVColorMode(
++ IN gco2D Engine,
++ IN gce2D_YUV_COLOR_MODE Mode
++ );
++
++/* Setup the source global color value in ARGB8 format. */
++gceSTATUS gco2D_SetSourceGlobalColorAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Color32
++ );
++
++/* Setup the target global color value in ARGB8 format. */
++gceSTATUS gco2D_SetTargetGlobalColorAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Color32
++ );
++
++/* Setup the source and target pixel multiply modes. */
++gceSTATUS
++gco2D_SetPixelMultiplyModeAdvanced(
++ IN gco2D Engine,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE SrcPremultiplySrcAlpha,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstPremultiplyDstAlpha,
++ IN gce2D_GLOBAL_COLOR_MULTIPLY_MODE SrcPremultiplyGlobalMode,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstDemultiplyDstAlpha
++ );
++
++/* Set the GPU clock cycles after which the idle engine will keep auto-flushing. */
++gceSTATUS
++gco2D_SetAutoFlushCycles(
++ IN gco2D Engine,
++ IN gctUINT32 Cycles
++ );
++
++#if VIVANTE_PROFILER
++/* Read the profile registers available in the 2D engine and sets them in the profile.
++ The function will also reset the pixelsRendered counter every time.
++*/
++gceSTATUS
++gco2D_ProfileEngine(
++ IN gco2D Engine,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ );
++#endif
++
++/* Enable or disable 2D dithering. */
++gceSTATUS
++gco2D_EnableDither(
++ IN gco2D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco2D_SetGenericSource(
++ IN gco2D Engine,
++ IN gctUINT32_PTR Addresses,
++ IN gctUINT32 AddressNum,
++ IN gctUINT32_PTR Strides,
++ IN gctUINT32 StrideNum,
++ IN gceTILING Tiling,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++);
++
++gceSTATUS
++gco2D_SetGenericTarget(
++ IN gco2D Engine,
++ IN gctUINT32_PTR Addresses,
++ IN gctUINT32 AddressNum,
++ IN gctUINT32_PTR Strides,
++ IN gctUINT32 StrideNum,
++ IN gceTILING Tiling,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++);
++
++gceSTATUS
++gco2D_SetCurrentSourceIndex(
++ IN gco2D Engine,
++ IN gctUINT32 SrcIndex
++ );
++
++gceSTATUS
++gco2D_MultiSourceBlit(
++ IN gco2D Engine,
++ IN gctUINT32 SourceMask,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 RectCount
++ );
++
++gceSTATUS
++gco2D_SetROP(
++ IN gco2D Engine,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++gceSTATUS
++gco2D_SetGdiStretchMode(
++ IN gco2D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco2D_SetSourceTileStatus(
++ IN gco2D Engine,
++ IN gce2D_TILE_STATUS_CONFIG TSControl,
++ IN gceSURF_FORMAT CompressedFormat,
++ IN gctUINT32 ClearValue,
++ IN gctUINT32 GpuAddress
++ );
++
++gceSTATUS
++gco2D_SetTargetTileStatus(
++ IN gco2D Engine,
++ IN gce2D_TILE_STATUS_CONFIG TileStatusConfig,
++ IN gceSURF_FORMAT CompressedFormat,
++ IN gctUINT32 ClearValue,
++ IN gctUINT32 GpuAddress
++ );
++
++gceSTATUS
++gco2D_QueryU32(
++ IN gco2D Engine,
++ IN gce2D_QUERY Item,
++ OUT gctUINT32_PTR Value
++ );
++
++gceSTATUS
++gco2D_SetStateU32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctUINT32 Value
++ );
++
++gceSTATUS
++gco2D_SetStateArrayI32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctINT32_PTR Array,
++ IN gctINT32 ArraySize
++ );
++
++gceSTATUS
++gco2D_SetStateArrayU32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctUINT32_PTR Array,
++ IN gctINT32 ArraySize
++ );
++
++gceSTATUS
++gco2D_SetTargetRect(
++ IN gco2D Engine,
++ IN gcsRECT_PTR Rect
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_raster_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,248 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_rename_h_
++#define __gc_hal_rename_h_
++
++
++#if defined(_HAL2D_APPENDIX)
++
++#define _HAL2D_RENAME_2(api, appendix) api ## appendix
++#define _HAL2D_RENAME_1(api, appendix) _HAL2D_RENAME_2(api, appendix)
++#define gcmHAL2D(api) _HAL2D_RENAME_1(api, _HAL2D_APPENDIX)
++
++
++#define gckOS_Construct gcmHAL2D(gckOS_Construct)
++#define gckOS_Destroy gcmHAL2D(gckOS_Destroy)
++#define gckOS_QueryVideoMemory gcmHAL2D(gckOS_QueryVideoMemory)
++#define gckOS_Allocate gcmHAL2D(gckOS_Allocate)
++#define gckOS_Free gcmHAL2D(gckOS_Free)
++#define gckOS_AllocateMemory gcmHAL2D(gckOS_AllocateMemory)
++#define gckOS_FreeMemory gcmHAL2D(gckOS_FreeMemory)
++#define gckOS_AllocatePagedMemory gcmHAL2D(gckOS_AllocatePagedMemory)
++#define gckOS_AllocatePagedMemoryEx gcmHAL2D(gckOS_AllocatePagedMemoryEx)
++#define gckOS_LockPages gcmHAL2D(gckOS_LockPages)
++#define gckOS_MapPages gcmHAL2D(gckOS_MapPages)
++#define gckOS_UnlockPages gcmHAL2D(gckOS_UnlockPages)
++#define gckOS_FreePagedMemory gcmHAL2D(gckOS_FreePagedMemory)
++#define gckOS_AllocateNonPagedMemory gcmHAL2D(gckOS_AllocateNonPagedMemory)
++#define gckOS_FreeNonPagedMemory gcmHAL2D(gckOS_FreeNonPagedMemory)
++#define gckOS_AllocateContiguous gcmHAL2D(gckOS_AllocateContiguous)
++#define gckOS_FreeContiguous gcmHAL2D(gckOS_FreeContiguous)
++#define gckOS_GetPageSize gcmHAL2D(gckOS_GetPageSize)
++#define gckOS_GetPhysicalAddress gcmHAL2D(gckOS_GetPhysicalAddress)
++#define gckOS_GetPhysicalAddressProcess gcmHAL2D(gckOS_GetPhysicalAddressProcess)
++#define gckOS_MapPhysical gcmHAL2D(gckOS_MapPhysical)
++#define gckOS_UnmapPhysical gcmHAL2D(gckOS_UnmapPhysical)
++#define gckOS_ReadRegister gcmHAL2D(gckOS_ReadRegister)
++#define gckOS_WriteRegister gcmHAL2D(gckOS_WriteRegister)
++#define gckOS_WriteMemory gcmHAL2D(gckOS_WriteMemory)
++#define gckOS_MapMemory gcmHAL2D(gckOS_MapMemory)
++#define gckOS_UnmapMemory gcmHAL2D(gckOS_UnmapMemory)
++#define gckOS_UnmapMemoryEx gcmHAL2D(gckOS_UnmapMemoryEx)
++#define gckOS_CreateMutex gcmHAL2D(gckOS_CreateMutex)
++#define gckOS_DeleteMutex gcmHAL2D(gckOS_DeleteMutex)
++#define gckOS_AcquireMutex gcmHAL2D(gckOS_AcquireMutex)
++#define gckOS_ReleaseMutex gcmHAL2D(gckOS_ReleaseMutex)
++#define gckOS_AtomicExchange gcmHAL2D(gckOS_AtomicExchange)
++#define gckOS_AtomicExchangePtr gcmHAL2D(gckOS_AtomicExchangePtr)
++#define gckOS_AtomConstruct gcmHAL2D(gckOS_AtomConstruct)
++#define gckOS_AtomDestroy gcmHAL2D(gckOS_AtomDestroy)
++#define gckOS_AtomGet gcmHAL2D(gckOS_AtomGet)
++#define gckOS_AtomIncrement gcmHAL2D(gckOS_AtomIncrement)
++#define gckOS_AtomDecrement gcmHAL2D(gckOS_AtomDecrement)
++#define gckOS_Delay gcmHAL2D(gckOS_Delay)
++#define gckOS_GetTime gcmHAL2D(gckOS_GetTime)
++#define gckOS_MemoryBarrier gcmHAL2D(gckOS_MemoryBarrier)
++#define gckOS_MapUserPointer gcmHAL2D(gckOS_MapUserPointer)
++#define gckOS_UnmapUserPointer gcmHAL2D(gckOS_UnmapUserPointer)
++#define gckOS_QueryNeedCopy gcmHAL2D(gckOS_QueryNeedCopy)
++#define gckOS_CopyFromUserData gcmHAL2D(gckOS_CopyFromUserData)
++#define gckOS_CopyToUserData gcmHAL2D(gckOS_CopyToUserData)
++#define gckOS_MapUserPhysical gcmHAL2D(gckOS_MapUserPhysical)
++#define gckOS_SuspendInterrupt gcmHAL2D(gckOS_SuspendInterrupt)
++#define gckOS_ResumeInterrupt gcmHAL2D(gckOS_ResumeInterrupt)
++#define gckOS_GetBaseAddress gcmHAL2D(gckOS_GetBaseAddress)
++#define gckOS_MemCopy gcmHAL2D(gckOS_MemCopy)
++#define gckOS_ZeroMemory gcmHAL2D(gckOS_ZeroMemory)
++#define gckOS_DeviceControl gcmHAL2D(gckOS_DeviceControl)
++#define gckOS_GetProcessID gcmHAL2D(gckOS_GetProcessID)
++#define gckOS_GetThreadID gcmHAL2D(gckOS_GetThreadID)
++#define gckOS_CreateSignal gcmHAL2D(gckOS_CreateSignal)
++#define gckOS_DestroySignal gcmHAL2D(gckOS_DestroySignal)
++#define gckOS_Signal gcmHAL2D(gckOS_Signal)
++#define gckOS_WaitSignal gcmHAL2D(gckOS_WaitSignal)
++#define gckOS_MapSignal gcmHAL2D(gckOS_MapSignal)
++#define gckOS_MapUserMemory gcmHAL2D(gckOS_MapUserMemory)
++#define gckOS_UnmapUserMemory gcmHAL2D(gckOS_UnmapUserMemory)
++#define gckOS_CreateUserSignal gcmHAL2D(gckOS_CreateUserSignal)
++#define gckOS_DestroyUserSignal gcmHAL2D(gckOS_DestroyUserSignal)
++#define gckOS_WaitUserSignal gcmHAL2D(gckOS_WaitUserSignal)
++#define gckOS_SignalUserSignal gcmHAL2D(gckOS_SignalUserSignal)
++#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal)
++#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal)
++#define gckOS_CacheClean gcmHAL2D(gckOS_CacheClean)
++#define gckOS_CacheFlush gcmHAL2D(gckOS_CacheFlush)
++#define gckOS_SetDebugLevel gcmHAL2D(gckOS_SetDebugLevel)
++#define gckOS_SetDebugZone gcmHAL2D(gckOS_SetDebugZone)
++#define gckOS_SetDebugLevelZone gcmHAL2D(gckOS_SetDebugLevelZone)
++#define gckOS_SetDebugZones gcmHAL2D(gckOS_SetDebugZones)
++#define gckOS_SetDebugFile gcmHAL2D(gckOS_SetDebugFile)
++#define gckOS_Broadcast gcmHAL2D(gckOS_Broadcast)
++#define gckOS_SetGPUPower gcmHAL2D(gckOS_SetGPUPower)
++#define gckOS_CreateSemaphore gcmHAL2D(gckOS_CreateSemaphore)
++#define gckOS_DestroySemaphore gcmHAL2D(gckOS_DestroySemaphore)
++#define gckOS_AcquireSemaphore gcmHAL2D(gckOS_AcquireSemaphore)
++#define gckOS_ReleaseSemaphore gcmHAL2D(gckOS_ReleaseSemaphore)
++#define gckHEAP_Construct gcmHAL2D(gckHEAP_Construct)
++#define gckHEAP_Destroy gcmHAL2D(gckHEAP_Destroy)
++#define gckHEAP_Allocate gcmHAL2D(gckHEAP_Allocate)
++#define gckHEAP_Free gcmHAL2D(gckHEAP_Free)
++#define gckHEAP_ProfileStart gcmHAL2D(gckHEAP_ProfileStart)
++#define gckHEAP_ProfileEnd gcmHAL2D(gckHEAP_ProfileEnd)
++#define gckHEAP_Test gcmHAL2D(gckHEAP_Test)
++#define gckVIDMEM_Construct gcmHAL2D(gckVIDMEM_Construct)
++#define gckVIDMEM_Destroy gcmHAL2D(gckVIDMEM_Destroy)
++#define gckVIDMEM_Allocate gcmHAL2D(gckVIDMEM_Allocate)
++#define gckVIDMEM_AllocateLinear gcmHAL2D(gckVIDMEM_AllocateLinear)
++#define gckVIDMEM_Free gcmHAL2D(gckVIDMEM_Free)
++#define gckVIDMEM_Lock gcmHAL2D(gckVIDMEM_Lock)
++#define gckVIDMEM_Unlock gcmHAL2D(gckVIDMEM_Unlock)
++#define gckVIDMEM_ConstructVirtual gcmHAL2D(gckVIDMEM_ConstructVirtual)
++#define gckVIDMEM_DestroyVirtual gcmHAL2D(gckVIDMEM_DestroyVirtual)
++#define gckKERNEL_Construct gcmHAL2D(gckKERNEL_Construct)
++#define gckKERNEL_Destroy gcmHAL2D(gckKERNEL_Destroy)
++#define gckKERNEL_Dispatch gcmHAL2D(gckKERNEL_Dispatch)
++#define gckKERNEL_QueryVideoMemory gcmHAL2D(gckKERNEL_QueryVideoMemory)
++#define gckKERNEL_GetVideoMemoryPool gcmHAL2D(gckKERNEL_GetVideoMemoryPool)
++#define gckKERNEL_MapVideoMemory gcmHAL2D(gckKERNEL_MapVideoMemory)
++#define gckKERNEL_UnmapVideoMemory gcmHAL2D(gckKERNEL_UnmapVideoMemory)
++#define gckKERNEL_MapMemory gcmHAL2D(gckKERNEL_MapMemory)
++#define gckKERNEL_UnmapMemory gcmHAL2D(gckKERNEL_UnmapMemory)
++#define gckKERNEL_Notify gcmHAL2D(gckKERNEL_Notify)
++#define gckKERNEL_QuerySettings gcmHAL2D(gckKERNEL_QuerySettings)
++#define gckKERNEL_Recovery gcmHAL2D(gckKERNEL_Recovery)
++#define gckKERNEL_OpenUserData gcmHAL2D(gckKERNEL_OpenUserData)
++#define gckKERNEL_CloseUserData gcmHAL2D(gckKERNEL_CloseUserData)
++#define gckHARDWARE_Construct gcmHAL2D(gckHARDWARE_Construct)
++#define gckHARDWARE_Destroy gcmHAL2D(gckHARDWARE_Destroy)
++#define gckHARDWARE_QuerySystemMemory gcmHAL2D(gckHARDWARE_QuerySystemMemory)
++#define gckHARDWARE_BuildVirtualAddress gcmHAL2D(gckHARDWARE_BuildVirtualAddress)
++#define gckHARDWARE_QueryCommandBuffer gcmHAL2D(gckHARDWARE_QueryCommandBuffer)
++#define gckHARDWARE_WaitLink gcmHAL2D(gckHARDWARE_WaitLink)
++#define gckHARDWARE_Execute gcmHAL2D(gckHARDWARE_Execute)
++#define gckHARDWARE_End gcmHAL2D(gckHARDWARE_End)
++#define gckHARDWARE_Nop gcmHAL2D(gckHARDWARE_Nop)
++#define gckHARDWARE_Wait gcmHAL2D(gckHARDWARE_Wait)
++#define gckHARDWARE_PipeSelect gcmHAL2D(gckHARDWARE_PipeSelect)
++#define gckHARDWARE_Link gcmHAL2D(gckHARDWARE_Link)
++#define gckHARDWARE_Event gcmHAL2D(gckHARDWARE_Event)
++#define gckHARDWARE_QueryMemory gcmHAL2D(gckHARDWARE_QueryMemory)
++#define gckHARDWARE_QueryChipIdentity gcmHAL2D(gckHARDWARE_QueryChipIdentity)
++#define gckHARDWARE_QueryChipSpecs gcmHAL2D(gckHARDWARE_QueryChipSpecs)
++#define gckHARDWARE_QueryShaderCaps gcmHAL2D(gckHARDWARE_QueryShaderCaps)
++#define gckHARDWARE_ConvertFormat gcmHAL2D(gckHARDWARE_ConvertFormat)
++#define gckHARDWARE_SplitMemory gcmHAL2D(gckHARDWARE_SplitMemory)
++#define gckHARDWARE_AlignToTile gcmHAL2D(gckHARDWARE_AlignToTile)
++#define gckHARDWARE_UpdateQueueTail gcmHAL2D(gckHARDWARE_UpdateQueueTail)
++#define gckHARDWARE_ConvertLogical gcmHAL2D(gckHARDWARE_ConvertLogical)
++#define gckHARDWARE_ConvertPhysical gcmHAL2D(gckHARDWARE_ConvertPhysical)
++#define gckHARDWARE_Interrupt gcmHAL2D(gckHARDWARE_Interrupt)
++#define gckHARDWARE_SetMMU gcmHAL2D(gckHARDWARE_SetMMU)
++#define gckHARDWARE_FlushMMU gcmHAL2D(gckHARDWARE_FlushMMU)
++#define gckHARDWARE_GetIdle gcmHAL2D(gckHARDWARE_GetIdle)
++#define gckHARDWARE_Flush gcmHAL2D(gckHARDWARE_Flush)
++#define gckHARDWARE_SetFastClear gcmHAL2D(gckHARDWARE_SetFastClear)
++#define gckHARDWARE_ReadInterrupt gcmHAL2D(gckHARDWARE_ReadInterrupt)
++#define gckHARDWARE_SetPowerManagementState gcmHAL2D(gckHARDWARE_SetPowerManagementState)
++#define gckHARDWARE_QueryPowerManagementState gcmHAL2D(gckHARDWARE_QueryPowerManagementState)
++#define gckHARDWARE_ProfileEngine2D gcmHAL2D(gckHARDWARE_ProfileEngine2D)
++#define gckHARDWARE_InitializeHardware gcmHAL2D(gckHARDWARE_InitializeHardware)
++#define gckHARDWARE_Reset gcmHAL2D(gckHARDWARE_Reset)
++#define gckINTERRUPT_Construct gcmHAL2D(gckINTERRUPT_Construct)
++#define gckINTERRUPT_Destroy gcmHAL2D(gckINTERRUPT_Destroy)
++#define gckINTERRUPT_SetHandler gcmHAL2D(gckINTERRUPT_SetHandler)
++#define gckINTERRUPT_Notify gcmHAL2D(gckINTERRUPT_Notify)
++#define gckEVENT_Construct gcmHAL2D(gckEVENT_Construct)
++#define gckEVENT_Destroy gcmHAL2D(gckEVENT_Destroy)
++#define gckEVENT_AddList gcmHAL2D(gckEVENT_AddList)
++#define gckEVENT_FreeNonPagedMemory gcmHAL2D(gckEVENT_FreeNonPagedMemory)
++#define gckEVENT_FreeContiguousMemory gcmHAL2D(gckEVENT_FreeContiguousMemory)
++#define gckEVENT_FreeVideoMemory gcmHAL2D(gckEVENT_FreeVideoMemory)
++#define gckEVENT_Signal gcmHAL2D(gckEVENT_Signal)
++#define gckEVENT_Unlock gcmHAL2D(gckEVENT_Unlock)
++#define gckEVENT_Submit gcmHAL2D(gckEVENT_Submit)
++#define gckEVENT_Commit gcmHAL2D(gckEVENT_Commit)
++#define gckEVENT_Notify gcmHAL2D(gckEVENT_Notify)
++#define gckEVENT_Interrupt gcmHAL2D(gckEVENT_Interrupt)
++#define gckCOMMAND_Construct gcmHAL2D(gckCOMMAND_Construct)
++#define gckCOMMAND_Destroy gcmHAL2D(gckCOMMAND_Destroy)
++#define gckCOMMAND_EnterCommit gcmHAL2D(gckCOMMAND_EnterCommit)
++#define gckCOMMAND_ExitCommit gcmHAL2D(gckCOMMAND_ExitCommit)
++#define gckCOMMAND_Start gcmHAL2D(gckCOMMAND_Start)
++#define gckCOMMAND_Stop gcmHAL2D(gckCOMMAND_Stop)
++#define gckCOMMAND_Commit gcmHAL2D(gckCOMMAND_Commit)
++#define gckCOMMAND_Reserve gcmHAL2D(gckCOMMAND_Reserve)
++#define gckCOMMAND_Execute gcmHAL2D(gckCOMMAND_Execute)
++#define gckCOMMAND_Stall gcmHAL2D(gckCOMMAND_Stall)
++#define gckCOMMAND_Attach gcmHAL2D(gckCOMMAND_Attach)
++#define gckCOMMAND_Detach gcmHAL2D(gckCOMMAND_Detach)
++#define gckMMU_Construct gcmHAL2D(gckMMU_Construct)
++#define gckMMU_Destroy gcmHAL2D(gckMMU_Destroy)
++#define gckMMU_AllocatePages gcmHAL2D(gckMMU_AllocatePages)
++#define gckMMU_FreePages gcmHAL2D(gckMMU_FreePages)
++#define gckMMU_InsertNode gcmHAL2D(gckMMU_InsertNode)
++#define gckMMU_RemoveNode gcmHAL2D(gckMMU_RemoveNode)
++#define gckMMU_FreeHandleMemory gcmHAL2D(gckMMU_FreeHandleMemory)
++#define gckMMU_Test gcmHAL2D(gckMMU_Test)
++#define gckHARDWARE_QueryProfileRegisters gcmHAL2D(gckHARDWARE_QueryProfileRegisters)
++
++
++#define FindMdlMap gcmHAL2D(FindMdlMap)
++#define OnProcessExit gcmHAL2D(OnProcessExit)
++
++#define gckGALDEVICE_Destroy gcmHAL2D(gckGALDEVICE_Destroy)
++#define gckOS_Print gcmHAL2D(gckOS_Print)
++#define gckGALDEVICE_FreeMemory gcmHAL2D(gckGALDEVICE_FreeMemory)
++#define gckGALDEVICE_AllocateMemory gcmHAL2D(gckGALDEVICE_AllocateMemory)
++#define gckOS_DebugBreak gcmHAL2D(gckOS_DebugBreak)
++#define gckGALDEVICE_Release_ISR gcmHAL2D(gckGALDEVICE_Release_ISR)
++#define gckOS_Verify gcmHAL2D(gckOS_Verify)
++#define gckCOMMAND_Release gcmHAL2D(gckCOMMAND_Release)
++#define gckGALDEVICE_Stop gcmHAL2D(gckGALDEVICE_Stop)
++#define gckGALDEVICE_Construct gcmHAL2D(gckGALDEVICE_Construct)
++#define gckOS_DebugFatal gcmHAL2D(gckOS_DebugFatal)
++#define gckOS_DebugTrace gcmHAL2D(gckOS_DebugTrace)
++#define gckHARDWARE_GetBaseAddress gcmHAL2D(gckHARDWARE_GetBaseAddress)
++#define gckGALDEVICE_Setup_ISR gcmHAL2D(gckGALDEVICE_Setup_ISR)
++#define gckKERNEL_AttachProcess gcmHAL2D(gckKERNEL_AttachProcess)
++#define gckKERNEL_AttachProcessEx gcmHAL2D(gckKERNEL_AttachProcessEx)
++#define gckGALDEVICE_Start_Thread gcmHAL2D(gckGALDEVICE_Start_Thread)
++#define gckHARDWARE_QueryIdle gcmHAL2D(gckHARDWARE_QueryIdle)
++#define gckGALDEVICE_Start gcmHAL2D(gckGALDEVICE_Start)
++#define gckOS_GetKernelLogical gcmHAL2D(gckOS_GetKernelLogical)
++#define gckOS_DebugTraceZone gcmHAL2D(gckOS_DebugTraceZone)
++#define gckGALDEVICE_Stop_Thread gcmHAL2D(gckGALDEVICE_Stop_Thread)
++#define gckHARDWARE_NeedBaseAddress gcmHAL2D(gckHARDWARE_NeedBaseAddress)
++
++#endif
++
++#endif /* __gc_hal_rename_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,115 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_statistics_h_
++#define __gc_hal_statistics_h_
++
++
++#define VIV_STAT_ENABLE_STATISTICS 0
++
++/* Toal number of frames for which the frame time is accounted. We have storage
++ to keep frame times for last this many frames.
++*/
++#define VIV_STAT_FRAME_BUFFER_SIZE 30
++
++/*
++ Total number of frames sampled for a mode. This means
++
++ # of frames for HZ Current : VIV_STAT_EARLY_Z_SAMPLE_FRAMES
++ # of frames for HZ Switched : VIV_STAT_EARLY_Z_SAMPLE_FRAMES
++ +
++ --------------------------------------------------------
++ : (2 * VIV_STAT_EARLY_Z_SAMPLE_FRAMES) frames needed
++
++ IMPORTANT: This total must be smaller than VIV_STAT_FRAME_BUFFER_SIZE
++*/
++#define VIV_STAT_EARLY_Z_SAMPLE_FRAMES 7
++#define VIV_STAT_EARLY_Z_LATENCY_FRAMES 2
++
++/* Multiplication factor for previous Hz off mode. Make it more than 1.0 to advertise HZ on.*/
++#define VIV_STAT_EARLY_Z_FACTOR (1.05f)
++
++/* Defines the statistical data keys monitored by the statistics module */
++typedef enum _gceSTATISTICS
++{
++ gcvFRAME_FPS = 1,
++}
++gceSTATISTICS;
++
++/* HAL statistics information. */
++typedef struct _gcsSTATISTICS_EARLYZ
++{
++ gctUINT switchBackCount;
++ gctUINT nextCheckPoint;
++ gctBOOL disabled;
++}
++gcsSTATISTICS_EARLYZ;
++
++
++/* Defines the statistical data keys monitored by the statistics module */
++typedef enum _gceSTATISTICS_Call
++{
++ gcvSTAT_ES11_GLDRAWELEMENTS = 1,
++}
++gceSTATISTICS_Call;
++
++
++/* HAL statistics information. */
++typedef struct _gcsSTATISTICS
++{
++ gctUINT64 frameTime[VIV_STAT_FRAME_BUFFER_SIZE];
++ gctUINT64 previousFrameTime;
++ gctUINT frame;
++ gcsSTATISTICS_EARLYZ earlyZ;
++ gctUINT ES11_drawElementsCount;
++ gctBOOL applyRTestVAFix;
++}
++gcsSTATISTICS;
++
++
++/* Add a frame based data into current statistics. */
++void
++gcfSTATISTICS_AddData(
++ IN gceSTATISTICS Key,
++ IN gctUINT Value
++ );
++
++/* Marks the frame end and triggers statistical calculations and decisions.*/
++void
++gcfSTATISTICS_MarkFrameEnd (
++ void
++ );
++
++/* Sets whether the dynmaic HZ is disabled or not .*/
++void
++gcfSTATISTICS_DisableDynamicEarlyZ (
++ IN gctBOOL Disabled
++ );
++
++/* Checks whether or not glDrawArray function call will be discarded */
++gctBOOL
++gcfSTATISTICS_DiscardCall(
++ gceSTATISTICS_Call Function
++ );
++
++
++#endif /*__gc_hal_statistics_h_ */
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,1079 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_types_h_
++#define __gc_hal_types_h_
++
++#include "gc_hal_version.h"
++#include "gc_hal_options.h"
++
++#ifdef _WIN32
++#pragma warning(disable:4127) /* Conditional expression is constant (do { }
++ ** while(0)). */
++#pragma warning(disable:4100) /* Unreferenced formal parameter. */
++#pragma warning(disable:4204) /* Non-constant aggregate initializer (C99). */
++#pragma warning(disable:4131) /* Uses old-style declarator (for Bison and
++ ** Flex generated files). */
++#pragma warning(disable:4206) /* Translation unit is empty. */
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++** Platform macros.
++*/
++
++#if defined(__GNUC__)
++# define gcdHAS_ELLIPSES 1 /* GCC always has it. */
++#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)
++# define gcdHAS_ELLIPSES 1 /* C99 has it. */
++#elif defined(_MSC_VER) && (_MSC_VER >= 1500)
++# define gcdHAS_ELLIPSES 1 /* MSVC 2007+ has it. */
++#elif defined(UNDER_CE)
++#if UNDER_CE >= 600
++# define gcdHAS_ELLIPSES 1
++# else
++# define gcdHAS_ELLIPSES 0
++# endif
++#else
++# error "gcdHAS_ELLIPSES: Platform could not be determined"
++#endif
++
++/******************************************************************************\
++************************************ Keyword ***********************************
++\******************************************************************************/
++
++#if (defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L))
++# define gcmINLINE inline /* C99 keyword. */
++#elif defined(__GNUC__)
++# define gcmINLINE __inline__ /* GNU keyword. */
++#elif defined(_MSC_VER) || defined(UNDER_CE)
++# define gcmINLINE __inline /* Internal keyword. */
++#else
++# error "gcmINLINE: Platform could not be determined"
++#endif
++
++/* Possible debug flags. */
++#define gcdDEBUG_NONE 0
++#define gcdDEBUG_ALL (1 << 0)
++#define gcdDEBUG_FATAL (1 << 1)
++#define gcdDEBUG_TRACE (1 << 2)
++#define gcdDEBUG_BREAK (1 << 3)
++#define gcdDEBUG_ASSERT (1 << 4)
++#define gcdDEBUG_CODE (1 << 5)
++#define gcdDEBUG_STACK (1 << 6)
++
++#define gcmIS_DEBUG(flag) ( gcdDEBUG & (flag | gcdDEBUG_ALL) )
++
++#ifndef gcdDEBUG
++#if (defined(DBG) && DBG) || defined(DEBUG) || defined(_DEBUG)
++# define gcdDEBUG gcdDEBUG_ALL
++# else
++# define gcdDEBUG gcdDEBUG_NONE
++# endif
++#endif
++
++#ifdef _USRDLL
++#ifdef _MSC_VER
++#ifdef HAL_EXPORTS
++# define HALAPI __declspec(dllexport)
++# else
++# define HALAPI __declspec(dllimport)
++# endif
++# define HALDECL __cdecl
++# else
++#ifdef HAL_EXPORTS
++# define HALAPI
++# else
++# define HALAPI extern
++# endif
++# endif
++#else
++# define HALAPI
++# define HALDECL
++#endif
++
++/******************************************************************************\
++********************************** Common Types ********************************
++\******************************************************************************/
++
++#define gcvFALSE 0
++#define gcvTRUE 1
++
++#define gcvINFINITE ((gctUINT32) ~0U)
++
++#define gcvINVALID_HANDLE ((gctHANDLE) ~0U)
++
++typedef int gctBOOL;
++typedef gctBOOL * gctBOOL_PTR;
++
++typedef int gctINT;
++typedef long gctLONG;
++typedef signed char gctINT8;
++typedef signed short gctINT16;
++typedef signed int gctINT32;
++typedef signed long long gctINT64;
++
++typedef gctINT * gctINT_PTR;
++typedef gctINT8 * gctINT8_PTR;
++typedef gctINT16 * gctINT16_PTR;
++typedef gctINT32 * gctINT32_PTR;
++typedef gctINT64 * gctINT64_PTR;
++
++typedef unsigned int gctUINT;
++typedef unsigned char gctUINT8;
++typedef unsigned short gctUINT16;
++typedef unsigned int gctUINT32;
++typedef unsigned long long gctUINT64;
++typedef unsigned long gctUINTPTR_T;
++
++typedef gctUINT * gctUINT_PTR;
++typedef gctUINT8 * gctUINT8_PTR;
++typedef gctUINT16 * gctUINT16_PTR;
++typedef gctUINT32 * gctUINT32_PTR;
++typedef gctUINT64 * gctUINT64_PTR;
++
++typedef unsigned long gctSIZE_T;
++typedef gctSIZE_T * gctSIZE_T_PTR;
++
++#ifdef __cplusplus
++# define gcvNULL 0
++#else
++# define gcvNULL ((void *) 0)
++#endif
++
++typedef float gctFLOAT;
++typedef signed int gctFIXED_POINT;
++typedef float * gctFLOAT_PTR;
++
++typedef void * gctPHYS_ADDR;
++typedef void * gctHANDLE;
++typedef void * gctFILE;
++typedef void * gctSIGNAL;
++typedef void * gctWINDOW;
++typedef void * gctIMAGE;
++typedef void * gctSYNC_POINT;
++
++typedef void * gctSEMAPHORE;
++
++typedef void * gctPOINTER;
++typedef const void * gctCONST_POINTER;
++
++typedef char gctCHAR;
++typedef char * gctSTRING;
++typedef const char * gctCONST_STRING;
++
++typedef struct _gcsCOUNT_STRING
++{
++ gctSIZE_T Length;
++ gctCONST_STRING String;
++}
++gcsCOUNT_STRING;
++
++typedef union _gcuFLOAT_UINT32
++{
++ gctFLOAT f;
++ gctUINT32 u;
++}
++gcuFLOAT_UINT32;
++
++/* Fixed point constants. */
++#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
++#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
++#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
++#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
++#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
++
++/* Stringizing macro. */
++#define gcmSTRING(Value) #Value
++
++/******************************************************************************\
++******************************* Fixed Point Math *******************************
++\******************************************************************************/
++
++#define gcmXMultiply(x1, x2) gcoMATH_MultiplyFixed(x1, x2)
++#define gcmXDivide(x1, x2) gcoMATH_DivideFixed(x1, x2)
++#define gcmXMultiplyDivide(x1, x2, x3) gcoMATH_MultiplyDivideFixed(x1, x2, x3)
++
++/* 2D Engine profile. */
++typedef struct _gcs2D_PROFILE
++{
++ /* Cycle count.
++ 32bit counter incremented every 2D clock cycle.
++ Wraps back to 0 when the counter overflows.
++ */
++ gctUINT32 cycleCount;
++
++ /* Pixels rendered by the 2D engine.
++ Resets to 0 every time it is read. */
++ gctUINT32 pixelsRendered;
++}
++gcs2D_PROFILE;
++
++/* Macro to combine four characters into a Charcater Code. */
++#define gcmCC(c1, c2, c3, c4) \
++( \
++ (char) (c1) \
++ | \
++ ((char) (c2) << 8) \
++ | \
++ ((char) (c3) << 16) \
++ | \
++ ((char) (c4) << 24) \
++)
++
++#define gcmPRINTABLE(c) ((((c) >= ' ') && ((c) <= '}')) ? ((c) != '%' ? (c) : ' ') : ' ')
++
++#define gcmCC_PRINT(cc) \
++ gcmPRINTABLE((char) ( (cc) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 8) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 16) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 24) & 0xFF))
++
++/******************************************************************************\
++****************************** Function Parameters *****************************
++\******************************************************************************/
++
++#define IN
++#define OUT
++#define OPTIONAL
++
++/******************************************************************************\
++********************************* Status Codes *********************************
++\******************************************************************************/
++
++typedef enum _gceSTATUS
++{
++ gcvSTATUS_OK = 0,
++ gcvSTATUS_FALSE = 0,
++ gcvSTATUS_TRUE = 1,
++ gcvSTATUS_NO_MORE_DATA = 2,
++ gcvSTATUS_CACHED = 3,
++ gcvSTATUS_MIPMAP_TOO_LARGE = 4,
++ gcvSTATUS_NAME_NOT_FOUND = 5,
++ gcvSTATUS_NOT_OUR_INTERRUPT = 6,
++ gcvSTATUS_MISMATCH = 7,
++ gcvSTATUS_MIPMAP_TOO_SMALL = 8,
++ gcvSTATUS_LARGER = 9,
++ gcvSTATUS_SMALLER = 10,
++ gcvSTATUS_CHIP_NOT_READY = 11,
++ gcvSTATUS_NEED_CONVERSION = 12,
++ gcvSTATUS_SKIP = 13,
++ gcvSTATUS_DATA_TOO_LARGE = 14,
++ gcvSTATUS_INVALID_CONFIG = 15,
++ gcvSTATUS_CHANGED = 16,
++ gcvSTATUS_NOT_SUPPORT_DITHER = 17,
++ gcvSTATUS_EXECUTED = 18,
++ gcvSTATUS_TERMINATE = 19,
++
++ gcvSTATUS_CONVERT_TO_SINGLE_STREAM = 20,
++
++ gcvSTATUS_INVALID_ARGUMENT = -1,
++ gcvSTATUS_INVALID_OBJECT = -2,
++ gcvSTATUS_OUT_OF_MEMORY = -3,
++ gcvSTATUS_MEMORY_LOCKED = -4,
++ gcvSTATUS_MEMORY_UNLOCKED = -5,
++ gcvSTATUS_HEAP_CORRUPTED = -6,
++ gcvSTATUS_GENERIC_IO = -7,
++ gcvSTATUS_INVALID_ADDRESS = -8,
++ gcvSTATUS_CONTEXT_LOSSED = -9,
++ gcvSTATUS_TOO_COMPLEX = -10,
++ gcvSTATUS_BUFFER_TOO_SMALL = -11,
++ gcvSTATUS_INTERFACE_ERROR = -12,
++ gcvSTATUS_NOT_SUPPORTED = -13,
++ gcvSTATUS_MORE_DATA = -14,
++ gcvSTATUS_TIMEOUT = -15,
++ gcvSTATUS_OUT_OF_RESOURCES = -16,
++ gcvSTATUS_INVALID_DATA = -17,
++ gcvSTATUS_INVALID_MIPMAP = -18,
++ gcvSTATUS_NOT_FOUND = -19,
++ gcvSTATUS_NOT_ALIGNED = -20,
++ gcvSTATUS_INVALID_REQUEST = -21,
++ gcvSTATUS_GPU_NOT_RESPONDING = -22,
++ gcvSTATUS_TIMER_OVERFLOW = -23,
++ gcvSTATUS_VERSION_MISMATCH = -24,
++ gcvSTATUS_LOCKED = -25,
++ gcvSTATUS_INTERRUPTED = -26,
++ gcvSTATUS_DEVICE = -27,
++ gcvSTATUS_NOT_MULTI_PIPE_ALIGNED = -28,
++
++ /* Linker errors. */
++ gcvSTATUS_GLOBAL_TYPE_MISMATCH = -1000,
++ gcvSTATUS_TOO_MANY_ATTRIBUTES = -1001,
++ gcvSTATUS_TOO_MANY_UNIFORMS = -1002,
++ gcvSTATUS_TOO_MANY_VARYINGS = -1003,
++ gcvSTATUS_UNDECLARED_VARYING = -1004,
++ gcvSTATUS_VARYING_TYPE_MISMATCH = -1005,
++ gcvSTATUS_MISSING_MAIN = -1006,
++ gcvSTATUS_NAME_MISMATCH = -1007,
++ gcvSTATUS_INVALID_INDEX = -1008,
++ gcvSTATUS_UNIFORM_TYPE_MISMATCH = -1009,
++
++ /* Compiler errors. */
++ gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR = -2000,
++ gcvSTATUS_COMPILER_FE_PARSER_ERROR = -2001,
++}
++gceSTATUS;
++
++/******************************************************************************\
++********************************* Status Macros ********************************
++\******************************************************************************/
++
++#define gcmIS_ERROR(status) (status < 0)
++#define gcmNO_ERROR(status) (status >= 0)
++#define gcmIS_SUCCESS(status) (status == gcvSTATUS_OK)
++
++/******************************************************************************\
++********************************* Field Macros *********************************
++\******************************************************************************/
++
++#define __gcmSTART(reg_field) \
++ (0 ? reg_field)
++
++#define __gcmEND(reg_field) \
++ (1 ? reg_field)
++
++#define __gcmGETSIZE(reg_field) \
++ (__gcmEND(reg_field) - __gcmSTART(reg_field) + 1)
++
++#define __gcmALIGN(data, reg_field) \
++ (((gctUINT32) (data)) << __gcmSTART(reg_field))
++
++#define __gcmMASK(reg_field) \
++ ((gctUINT32) ((__gcmGETSIZE(reg_field) == 32) \
++ ? ~0 \
++ : (~(~0 << __gcmGETSIZE(reg_field)))))
++
++/*******************************************************************************
++**
++** gcmFIELDMASK
++**
++** Get aligned field mask.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmFIELDMASK(reg, field) \
++( \
++ __gcmALIGN(__gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmGETFIELD
++**
++** Extract the value of a field from specified data.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmGETFIELD(data, reg, field) \
++( \
++ ((((gctUINT32) (data)) >> __gcmSTART(reg##_##field)) \
++ & __gcmMASK(reg##_##field)) \
++)
++
++/*******************************************************************************
++**
++** gcmSETFIELD
++**
++** Set the value of a field within specified data.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETFIELD(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) \
++ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
++ | __gcmALIGN((gctUINT32) (value) \
++ & __gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmSETFIELDVALUE
++**
++** Set the value of a field within specified data with a
++** predefined value.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Name of the value within the field.
++*/
++#define gcmSETFIELDVALUE(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) \
++ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
++ | __gcmALIGN(reg##_##field##_##value \
++ & __gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmGETMASKEDFIELDMASK
++**
++** Determine field mask of a masked field.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmGETMASKEDFIELDMASK(reg, field) \
++( \
++ gcmSETFIELD(0, reg, field, ~0) | \
++ gcmSETFIELD(0, reg, MASK_ ## field, ~0) \
++)
++
++/*******************************************************************************
++**
++** gcmSETMASKEDFIELD
++**
++** Set the value of a masked field with specified data.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETMASKEDFIELD(reg, field, value) \
++( \
++ gcmSETFIELD (~0, reg, field, value) & \
++ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
++)
++
++/*******************************************************************************
++**
++** gcmSETMASKEDFIELDVALUE
++**
++** Set the value of a masked field with specified data.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETMASKEDFIELDVALUE(reg, field, value) \
++( \
++ gcmSETFIELDVALUE(~0, reg, field, value) & \
++ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
++)
++
++/*******************************************************************************
++**
++** gcmVERIFYFIELDVALUE
++**
++** Verify if the value of a field within specified data equals a
++** predefined value.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Name of the value within the field.
++*/
++#define gcmVERIFYFIELDVALUE(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) >> __gcmSTART(reg##_##field) & \
++ __gcmMASK(reg##_##field)) \
++ == \
++ (reg##_##field##_##value & __gcmMASK(reg##_##field)) \
++)
++
++/*******************************************************************************
++** Bit field macros.
++*/
++
++#define __gcmSTARTBIT(Field) \
++ ( 1 ? Field )
++
++#define __gcmBITSIZE(Field) \
++ ( 0 ? Field )
++
++#define __gcmBITMASK(Field) \
++( \
++ (1 << __gcmBITSIZE(Field)) - 1 \
++)
++
++#define gcmGETBITS(Value, Type, Field) \
++( \
++ ( ((Type) (Value)) >> __gcmSTARTBIT(Field) ) \
++ & \
++ __gcmBITMASK(Field) \
++)
++
++#define gcmSETBITS(Value, Type, Field, NewValue) \
++( \
++ ( ((Type) (Value)) \
++ & ~(__gcmBITMASK(Field) << __gcmSTARTBIT(Field)) \
++ ) \
++ | \
++ ( ( ((Type) (NewValue)) \
++ & __gcmBITMASK(Field) \
++ ) << __gcmSTARTBIT(Field) \
++ ) \
++)
++
++/*******************************************************************************
++**
++** gcmISINREGRANGE
++**
++** Verify whether the specified address is in the register range.
++**
++** ARGUMENTS:
++**
++** Address Address to be verified.
++** Name Name of a register.
++*/
++
++#define gcmISINREGRANGE(Address, Name) \
++( \
++ ((Address & (~0U << Name ## _LSB)) == (Name ## _Address >> 2)) \
++)
++
++/*******************************************************************************
++**
++** A set of macros to aid state loading.
++**
++** ARGUMENTS:
++**
++** CommandBuffer Pointer to a gcoCMDBUF object.
++** StateDelta Pointer to a gcsSTATE_DELTA state delta structure.
++** Memory Destination memory pointer of gctUINT32_PTR type.
++** PartOfContext Whether or not the state is a part of the context.
++** FixedPoint Whether or not the state is of the fixed point format.
++** Count Number of consecutive states to be loaded.
++** Address State address.
++** Data Data to be set to the state.
++*/
++
++/*----------------------------------------------------------------------------*/
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++
++# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count) \
++ CommandBuffer->lastLoadStatePtr = gcmPTR_TO_UINT64(Memory); \
++ CommandBuffer->lastLoadStateAddress = Address; \
++ CommandBuffer->lastLoadStateCount = Count
++
++# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address) \
++ gcmASSERT( \
++ (gctUINT) (Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastLoadStatePtr, gctUINT32_PTR) - 1) \
++ == \
++ (gctUINT) (Address - CommandBuffer->lastLoadStateAddress) \
++ ); \
++ \
++ gcmASSERT(CommandBuffer->lastLoadStateCount > 0); \
++ \
++ CommandBuffer->lastLoadStateCount -= 1
++
++# define gcmVERIFYLOADSTATEDONE(CommandBuffer) \
++ gcmASSERT(CommandBuffer->lastLoadStateCount == 0)
++
++#else
++
++# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count)
++# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address)
++# define gcmVERIFYLOADSTATEDONE(CommandBuffer)
++
++#endif
++
++#if gcdSECURE_USER
++
++# define gcmDEFINESECUREUSER() \
++ gctUINT __secure_user_offset__; \
++ gctUINT32_PTR __secure_user_hintArray__;
++
++# define gcmBEGINSECUREUSER() \
++ __secure_user_offset__ = reserve->lastOffset; \
++ \
++ __secure_user_hintArray__ = gcmUINT64_TO_PTR(reserve->hintArrayTail)
++
++# define gcmENDSECUREUSER() \
++ reserve->hintArrayTail = gcmPTR_TO_UINT64(__secure_user_hintArray__)
++
++# define gcmSKIPSECUREUSER() \
++ __secure_user_offset__ += gcmSIZEOF(gctUINT32)
++
++# define gcmUPDATESECUREUSER() \
++ *__secure_user_hintArray__ = __secure_user_offset__; \
++ \
++ __secure_user_offset__ += gcmSIZEOF(gctUINT32); \
++ __secure_user_hintArray__ += 1
++
++#else
++
++# define gcmDEFINESECUREUSER()
++# define gcmBEGINSECUREUSER()
++# define gcmENDSECUREUSER()
++# define gcmSKIPSECUREUSER()
++# define gcmUPDATESECUREUSER()
++
++#endif
++
++/*----------------------------------------------------------------------------*/
++
++#if gcdDUMP
++# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data) \
++ if (FixedPoint) \
++ { \
++ gcmDUMP(gcvNULL, "@[state.x 0x%04X 0x%08X]", \
++ Address, Data \
++ ); \
++ } \
++ else \
++ { \
++ gcmDUMP(gcvNULL, "@[state 0x%04X 0x%08X]", \
++ Address, Data \
++ ); \
++ }
++#else
++# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data)
++#endif
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmDEFINESTATEBUFFER(CommandBuffer, StateDelta, Memory, ReserveSize) \
++ gcmDEFINESECUREUSER() \
++ gctSIZE_T ReserveSize; \
++ gcoCMDBUF CommandBuffer; \
++ gctUINT32_PTR Memory; \
++ gcsSTATE_DELTA_PTR StateDelta
++
++#define gcmBEGINSTATEBUFFER(Hardware, CommandBuffer, StateDelta, Memory, ReserveSize) \
++{ \
++ gcmONERROR(gcoBUFFER_Reserve( \
++ Hardware->buffer, ReserveSize, gcvTRUE, &CommandBuffer \
++ )); \
++ \
++ Memory = gcmUINT64_TO_PTR(CommandBuffer->lastReserve); \
++ \
++ StateDelta = Hardware->delta; \
++ \
++ gcmBEGINSECUREUSER(); \
++}
++
++#define gcmENDSTATEBUFFER(CommandBuffer, Memory, ReserveSize) \
++{ \
++ gcmENDSECUREUSER(); \
++ \
++ gcmASSERT( \
++ gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT8_PTR) + ReserveSize \
++ == \
++ (gctUINT8_PTR) Memory \
++ ); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, Count) \
++{ \
++ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \
++ gcmASSERT((gctUINT32)Count <= 1024); \
++ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count); \
++ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, FLOAT, FixedPoint) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, Address); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmENDSTATEBATCH(CommandBuffer, Memory) \
++{ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, FixedPoint, Address, 0, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, gcvFALSE, Address, __temp_data32__); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmSETFILLER(CommandBuffer, Memory) \
++{ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ Memory += 1; \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSINGLESTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLECTRLSTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++
++/*******************************************************************************
++**
++** gcmSETSTARTDECOMMAND
++**
++** Form a START_DE command.
++**
++** ARGUMENTS:
++**
++** Memory Destination memory pointer of gctUINT32_PTR type.
++** Count Number of the rectangles.
++*/
++
++#define gcmSETSTARTDECOMMAND(Memory, Count) \
++{ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_START_DE_COMMAND, OPCODE, START_DE) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, DATA_COUNT, 0); \
++ \
++ *Memory++ = 0xDEADDEED; \
++}
++
++/******************************************************************************\
++******************************** Ceiling Macro ********************************
++\******************************************************************************/
++#define gcmCEIL(x) ((x - (gctUINT32)x) == 0 ? (gctUINT32)x : (gctUINT32)x + 1)
++
++/******************************************************************************\
++******************************** Min/Max Macros ********************************
++\******************************************************************************/
++
++#define gcmMIN(x, y) (((x) <= (y)) ? (x) : (y))
++#define gcmMAX(x, y) (((x) >= (y)) ? (x) : (y))
++#define gcmCLAMP(x, min, max) (((x) < (min)) ? (min) : \
++ ((x) > (max)) ? (max) : (x))
++#define gcmABS(x) (((x) < 0) ? -(x) : (x))
++#define gcmNEG(x) (((x) < 0) ? (x) : -(x))
++
++/*******************************************************************************
++**
++** gcmPTR2INT
++**
++** Convert a pointer to an integer value.
++**
++** ARGUMENTS:
++**
++** p Pointer value.
++*/
++#if defined(_WIN32) || (defined(__LP64__) && __LP64__)
++# define gcmPTR2INT(p) \
++ ( \
++ (gctUINT32) (gctUINT64) (p) \
++ )
++#else
++# define gcmPTR2INT(p) \
++ ( \
++ (gctUINT32) (p) \
++ )
++#endif
++
++/*******************************************************************************
++**
++** gcmINT2PTR
++**
++** Convert an integer value into a pointer.
++**
++** ARGUMENTS:
++**
++** v Integer value.
++*/
++#ifdef __LP64__
++# define gcmINT2PTR(i) \
++ ( \
++ (gctPOINTER) (gctINT64) (i) \
++ )
++#else
++# define gcmINT2PTR(i) \
++ ( \
++ (gctPOINTER) (i) \
++ )
++#endif
++
++/*******************************************************************************
++**
++** gcmOFFSETOF
++**
++** Compute the byte offset of a field inside a structure.
++**
++** ARGUMENTS:
++**
++** s Structure name.
++** field Field name.
++*/
++#define gcmOFFSETOF(s, field) \
++( \
++ gcmPTR2INT(& (((struct s *) 0)->field)) \
++)
++
++#define gcmSWAB32(x) ((gctUINT32)( \
++ (((gctUINT32)(x) & (gctUINT32)0x000000FFUL) << 24) | \
++ (((gctUINT32)(x) & (gctUINT32)0x0000FF00UL) << 8) | \
++ (((gctUINT32)(x) & (gctUINT32)0x00FF0000UL) >> 8) | \
++ (((gctUINT32)(x) & (gctUINT32)0xFF000000UL) >> 24)))
++
++/*******************************************************************************
++***** Database ****************************************************************/
++
++typedef struct _gcsDATABASE_COUNTERS
++{
++ /* Number of currently allocated bytes. */
++ gctUINT64 bytes;
++
++ /* Maximum number of bytes allocated (memory footprint). */
++ gctUINT64 maxBytes;
++
++ /* Total number of bytes allocated. */
++ gctUINT64 totalBytes;
++}
++gcsDATABASE_COUNTERS;
++
++typedef struct _gcuDATABASE_INFO
++{
++ /* Counters. */
++ gcsDATABASE_COUNTERS counters;
++
++ /* Time value. */
++ gctUINT64 time;
++}
++gcuDATABASE_INFO;
++
++/*******************************************************************************
++***** Frame database **********************************************************/
++
++/* gcsHAL_FRAME_INFO */
++typedef struct _gcsHAL_FRAME_INFO
++{
++ /* Current timer tick. */
++ OUT gctUINT64 ticks;
++
++ /* Bandwidth counters. */
++ OUT gctUINT readBytes8[8];
++ OUT gctUINT writeBytes8[8];
++
++ /* Counters. */
++ OUT gctUINT cycles[8];
++ OUT gctUINT idleCycles[8];
++ OUT gctUINT mcCycles[8];
++ OUT gctUINT readRequests[8];
++ OUT gctUINT writeRequests[8];
++
++ /* FE counters. */
++ OUT gctUINT drawCount;
++ OUT gctUINT vertexOutCount;
++ OUT gctUINT vertexMissCount;
++
++ /* 3D counters. */
++ OUT gctUINT vertexCount;
++ OUT gctUINT primitiveCount;
++ OUT gctUINT rejectedPrimitives;
++ OUT gctUINT culledPrimitives;
++ OUT gctUINT clippedPrimitives;
++ OUT gctUINT droppedPrimitives;
++ OUT gctUINT frustumClippedPrimitives;
++ OUT gctUINT outPrimitives;
++ OUT gctUINT inPrimitives;
++ OUT gctUINT culledQuadCount;
++ OUT gctUINT totalQuadCount;
++ OUT gctUINT quadCount;
++ OUT gctUINT totalPixelCount;
++
++ /* PE counters. */
++ OUT gctUINT colorKilled[8];
++ OUT gctUINT colorDrawn[8];
++ OUT gctUINT depthKilled[8];
++ OUT gctUINT depthDrawn[8];
++
++ /* Shader counters. */
++ OUT gctUINT shaderCycles;
++ OUT gctUINT vsInstructionCount;
++ OUT gctUINT vsTextureCount;
++ OUT gctUINT vsBranchCount;
++ OUT gctUINT vsVertices;
++ OUT gctUINT psInstructionCount;
++ OUT gctUINT psTextureCount;
++ OUT gctUINT psBranchCount;
++ OUT gctUINT psPixels;
++
++ /* Texture counters. */
++ OUT gctUINT bilinearRequests;
++ OUT gctUINT trilinearRequests;
++ OUT gctUINT txBytes8[2];
++ OUT gctUINT txHitCount;
++ OUT gctUINT txMissCount;
++}
++gcsHAL_FRAME_INFO;
++
++typedef enum _gcePATCH_ID
++{
++ gcePATCH_UNKNOWN = 0xFFFFFFFF,
++
++ /* Benchmark list*/
++ gcePATCH_GLB11 = 0x0,
++ gcePATCH_GLB21,
++ gcePATCH_GLB25,
++ gcePATCH_GLB27,
++
++ gcePATCH_BM21,
++ gcePATCH_MM,
++ gcePATCH_MM06,
++ gcePATCH_MM07,
++ gcePATCH_QUADRANT,
++ gcePATCH_ANTUTU,
++ gcePATCH_SMARTBENCH,
++ gcePATCH_JPCT,
++ gcePATCH_NENAMARK,
++ gcePATCH_NENAMARK2,
++ gcePATCH_NEOCORE,
++ gcePATCH_GLB,
++ gcePATCH_GB,
++ gcePATCH_RTESTVA,
++ gcePATCH_BMX,
++ gcePATCH_BMGUI,
++
++ /* Game list */
++ gcePATCH_NBA2013,
++ gcePATCH_BARDTALE,
++ gcePATCH_BUSPARKING3D,
++ gcePATCH_FISHBOODLE,
++ gcePATCH_SUBWAYSURFER,
++ gcePATCH_HIGHWAYDRIVER,
++ gcePATCH_PREMIUM,
++ gcePATCH_RACEILLEGAL,
++ gcePATCH_BLABLA,
++ gcePATCH_MEGARUN,
++ gcePATCH_GALAXYONFIRE2,
++ gcePATCH_GLOFTR3HM,
++ gcePATCH_GLOFTSXHM,
++ gcePATCH_GLOFTF3HM,
++ gcePATCH_GLOFTGANG,
++ gcePATCH_XRUNNER,
++ gcePATCH_WP,
++ gcePATCH_DEVIL,
++ gcePATCH_HOLYARCH,
++ gcePATCH_MUSE,
++ gcePATCH_SG,
++ gcePATCH_SIEGECRAFT,
++ gcePATCH_CARCHALLENGE,
++ gcePATCH_HEROESCALL,
++ gcePATCH_MONOPOLY,
++ gcePATCH_CTGL20,
++ gcePATCH_FIREFOX,
++ gcePATCH_CHORME,
++ gcePATCH_DUOKANTV,
++ gcePATCH_TESTAPP,
++
++ /* Count enum*/
++ gcePATCH_COUNT,
++}
++gcePATCH_ID;
++
++#if gcdLINK_QUEUE_SIZE
++typedef struct _gckLINKDATA * gckLINKDATA;
++struct _gckLINKDATA
++{
++ gctUINT32 start;
++ gctUINT32 end;
++ gctINT pid;
++};
++
++typedef struct _gckLINKQUEUE * gckLINKQUEUE;
++struct _gckLINKQUEUE
++{
++ struct _gckLINKDATA data[gcdLINK_QUEUE_SIZE];
++ gctUINT32 rear;
++ gctUINT32 front;
++ gctUINT32 count;
++};
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_types_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,37 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_version_h_
++#define __gc_hal_version_h_
++
++#define gcvVERSION_MAJOR 4
++
++#define gcvVERSION_MINOR 6
++
++#define gcvVERSION_PATCH 9
++
++#define gcvVERSION_BUILD 9754
++
++#define gcvVERSION_DATE __DATE__
++
++#define gcvVERSION_TIME __TIME__
++
++#endif /* __gc_hal_version_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h 2014-05-15 20:33:58.646018535 +0200
+@@ -0,0 +1,913 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_vg_h_
++#define __gc_hal_vg_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#include "gc_hal_rename.h"
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++#include "gc_hal_base.h"
++
++#if gcdENABLE_VG
++
++/* Thread routine type. */
++#if defined(LINUX)
++ typedef gctINT gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE
++#elif defined(WIN32)
++ typedef gctUINT gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE __stdcall
++#elif defined(__QNXNTO__)
++ typedef void * gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE
++#endif
++
++typedef gctTHREADFUNCRESULT (gctTHREADFUNCTYPE * gctTHREADFUNC) (
++ gctTHREADFUNCPARAMETER ThreadParameter
++ );
++
++
++#if defined(gcvDEBUG)
++# undef gcvDEBUG
++#endif
++
++#define gcdFORCE_DEBUG 0
++#define gcdFORCE_MESSAGES 0
++
++
++#if DBG || defined(DEBUG) || defined(_DEBUG) || gcdFORCE_DEBUG
++# define gcvDEBUG 1
++#else
++# define gcvDEBUG 0
++#endif
++
++#define _gcmERROR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++
++#define gcmERROR_RETURN(func) _gcmERROR_RETURN(gcm, func)
++
++#define gcmLOG_LOCATION()
++
++#define gcmkIS_ERROR(status) (status < 0)
++
++#define gcmALIGNDOWN(n, align) \
++( \
++ (n) & ~((align) - 1) \
++)
++
++#define gcmIS_VALID_INDEX(Index, Array) \
++ (((gctUINT) (Index)) < gcmCOUNTOF(Array))
++
++
++#define gcmIS_NAN(x) \
++( \
++ ((* (gctUINT32_PTR) &(x)) & 0x7FFFFFFF) == 0x7FFFFFFF \
++)
++
++#define gcmLERP(v1, v2, w) \
++ ((v1) * (w) + (v2) * (1.0f - (w)))
++
++#define gcmINTERSECT(Start1, Start2, Length) \
++ (gcmABS((Start1) - (Start2)) < (Length))
++
++/*******************************************************************************
++**
++** gcmERR_GOTO
++**
++** Prints a message and terminates the current loop on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** Function
++** Function to evaluate.
++*/
++
++#define gcmERR_GOTO(Function) \
++ status = Function; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ gcmTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmERR_GOTO: status=%d @ line=%d in function %s.\n", \
++ status, __LINE__, __FUNCTION__ \
++ ); \
++ goto ErrorHandler; \
++ }
++
++#if gcvDEBUG || gcdFORCE_MESSAGES
++# define gcmVERIFY_BOOLEAN(Expression) \
++ gcmASSERT( \
++ ( (Expression) == gcvFALSE ) || \
++ ( (Expression) == gcvTRUE ) \
++ )
++#else
++# define gcmVERIFY_BOOLEAN(Expression)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFYFIELDFIT
++**
++** Verify whether the value fits in the field.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmVERIFYFIELDFIT(reg, field, value) \
++ gcmASSERT( \
++ (value) <= gcmFIELDMAX(reg, field) \
++ )
++/*******************************************************************************
++**
++** gcmFIELDMAX
++**
++** Get field maximum value.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmFIELDMAX(reg, field) \
++( \
++ (gctUINT32) \
++ ( \
++ (__gcmGETSIZE(reg##_##field) == 32) \
++ ? ~0 \
++ : (~(~0 << __gcmGETSIZE(reg##_##field))) \
++ ) \
++)
++
++
++/* ANSI C does not have the 'f' functions, define replacements here. */
++#define gcmSINF(x) ((gctFLOAT) sin(x))
++#define gcmCOSF(x) ((gctFLOAT) cos(x))
++#define gcmASINF(x) ((gctFLOAT) asin(x))
++#define gcmACOSF(x) ((gctFLOAT) acos(x))
++#define gcmSQRTF(x) ((gctFLOAT) sqrt(x))
++#define gcmFABSF(x) ((gctFLOAT) fabs(x))
++#define gcmFMODF(x, y) ((gctFLOAT) fmod((x), (y)))
++#define gcmCEILF(x) ((gctFLOAT) ceil(x))
++#define gcmFLOORF(x) ((gctFLOAT) floor(x))
++
++
++
++/* Fixed point constants. */
++#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
++#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
++#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
++#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
++#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
++
++/* Integer constants. */
++#define gcvMAX_POS_INT ((gctINT) 0x7FFFFFFF)
++#define gcvMAX_NEG_INT ((gctINT) 0x80000000)
++
++/* Float constants. */
++#define gcvMAX_POS_FLOAT ((gctFLOAT) 3.4028235e+038)
++#define gcvMAX_NEG_FLOAT ((gctFLOAT) -3.4028235e+038)
++
++/******************************************************************************\
++***************************** Miscellaneous Macro ******************************
++\******************************************************************************/
++
++#define gcmKB2BYTES(Kilobyte) \
++( \
++ (Kilobyte) << 10 \
++)
++
++#define gcmMB2BYTES(Megabyte) \
++( \
++ (Megabyte) << 20 \
++)
++
++#define gcmMAT(Matrix, Row, Column) \
++( \
++ (Matrix) [(Row) * 3 + (Column)] \
++)
++
++#define gcmMAKE2CHAR(Char1, Char2) \
++( \
++ ((gctUINT16) (gctUINT8) (Char1) << 0) | \
++ ((gctUINT16) (gctUINT8) (Char2) << 8) \
++)
++
++#define gcmMAKE4CHAR(Char1, Char2, Char3, Char4) \
++( \
++ ((gctUINT32)(gctUINT8) (Char1) << 0) | \
++ ((gctUINT32)(gctUINT8) (Char2) << 8) | \
++ ((gctUINT32)(gctUINT8) (Char3) << 16) | \
++ ((gctUINT32)(gctUINT8) (Char4) << 24) \
++)
++
++/* some platforms need to fix the physical address for HW to access*/
++#define gcmFIXADDRESS(address) \
++(\
++ (address)\
++)
++
++#define gcmkFIXADDRESS(address) \
++(\
++ (address)\
++)
++
++/******************************************************************************\
++****************************** Kernel Debug Macro ******************************
++\******************************************************************************/
++
++/* Set signal to signaled state for specified process. */
++gceSTATUS
++gckOS_SetSignal(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ );
++
++/* Return the kernel logical pointer for the given physical one. */
++gceSTATUS
++gckOS_GetKernelLogical(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Return the kernel logical pointer for the given physical one. */
++gceSTATUS
++gckOS_GetKernelLogicalEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----------------------------- Semaphore Object -----------------------------*/
++
++/* Increment the value of a semaphore. */
++gceSTATUS
++gckOS_IncrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ );
++
++/* Decrement the value of a semaphore (waiting might occur). */
++gceSTATUS
++gckOS_DecrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ );
++
++
++/*----------------------------------------------------------------------------*/
++/*------------------------------- Thread Object ------------------------------*/
++
++/* Start a thread. */
++gceSTATUS
++gckOS_StartThread(
++ IN gckOS Os,
++ IN gctTHREADFUNC ThreadFunction,
++ IN gctPOINTER ThreadParameter,
++ OUT gctTHREAD * Thread
++ );
++
++/* Stop a thread. */
++gceSTATUS
++gckOS_StopThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ );
++
++/* Verify whether the thread is still running. */
++gceSTATUS
++gckOS_VerifyThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ );
++
++
++/* Construct a new gckVGKERNEL object. */
++gceSTATUS
++gckVGKERNEL_Construct(
++ IN gckOS Os,
++ IN gctPOINTER Context,
++ IN gckKERNEL inKernel,
++ OUT gckVGKERNEL * Kernel
++ );
++
++/* Destroy an gckVGKERNEL object. */
++gceSTATUS
++gckVGKERNEL_Destroy(
++ IN gckVGKERNEL Kernel
++ );
++
++/* Allocate linear video memory. */
++gceSTATUS
++gckKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Unmap memory. */
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Dispatch a user-level command. */
++gceSTATUS
++gckVGKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Query command buffer requirements. */
++gceSTATUS
++gckKERNEL_QueryCommandBuffer(
++ IN gckKERNEL Kernel,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++
++#if gcdDYNAMIC_MAP_RESERVED_MEMORY
++gceSTATUS
++gckOS_MapReservedMemoryToKernel(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctINT Bytes,
++ IN OUT gctPOINTER *Virtual
++ );
++
++gceSTATUS
++gckOS_UnmapReservedMemoryFromKernel(
++ IN gctPOINTER Virtual
++ );
++#endif
++
++/******************************************************************************\
++******************************* gckVGHARDWARE Object ******************************
++\******************************************************************************/
++
++/* Construct a new gckVGHARDWARE object. */
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ );
++
++/* Destroy an gckVGHARDWARE object. */
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ );
++
++/* Query system memory requirements. */
++gceSTATUS
++gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ );
++
++/* Build virtual address. */
++gceSTATUS
++gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Kickstart the command processor. */
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Count
++ );
++
++/* Query the available memory. */
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL* ChipModel,
++ OUT gctUINT32* ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures1
++ );
++
++/* Convert an API format. */
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ );
++
++/* Split a harwdare specific address into API stuff. */
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Align size to tile boundary. */
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Width,
++ IN OUT gctUINT32_PTR Height
++ );
++
++/* Convert logical address to hardware specific address. */
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++/* Program MMU. */
++gceSTATUS
++gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ );
++
++/* Flush the MMU. */
++gceSTATUS
++gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ );
++
++/* Get idle register. */
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ );
++
++/* Flush the caches. */
++gceSTATUS
++gckVGHARDWARE_Flush(
++ IN gckVGHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Enable/disable fast clear. */
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ );
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ );
++
++/* Power management. */
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ );
++
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ );
++
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ );
++/******************************************************************************\
++*************************** Command Buffer Structures **************************
++\******************************************************************************/
++
++/* Vacant command buffer marker. */
++#define gcvVACANT_BUFFER ((gcsCOMPLETION_SIGNAL_PTR) (1))
++
++/* Command buffer header. */
++typedef struct _gcsCMDBUFFER * gcsCMDBUFFER_PTR;
++typedef struct _gcsCMDBUFFER
++{
++ /* Pointer to the completion signal. */
++ gcsCOMPLETION_SIGNAL_PTR completion;
++
++ /* The user sets this to the node of the container buffer whitin which
++ this particular command buffer resides. The kernel sets this to the
++ node of the internally allocated buffer. */
++ gctUINT64 node;
++
++ /* Command buffer hardware address. */
++ gctUINT32 address;
++
++ /* The offset of the buffer from the beginning of the header. */
++ gctUINT32 bufferOffset;
++
++ /* Size of the area allocated for the data portion of this particular
++ command buffer (headers and tail reserves are excluded). */
++ gctSIZE_T size;
++
++ /* Offset into the buffer [0..size]; reflects exactly how much data has
++ been put into the command buffer. */
++ gctUINT offset;
++
++ /* The number of command units in the buffer for the hardware to
++ execute. */
++ gctSIZE_T dataCount;
++
++ /* MANAGED BY : user HAL (gcoBUFFER object).
++ USED BY : user HAL (gcoBUFFER object).
++ Points to the immediate next allocated command buffer. */
++ gcsCMDBUFFER_PTR nextAllocated;
++
++ /* MANAGED BY : user layers (HAL and drivers).
++ USED BY : kernel HAL (gcoBUFFER object).
++ Points to the next subbuffer if any. A family of subbuffers are chained
++ together and are meant to be executed inseparably as a unit. Meaning
++ that context switching cannot occur while a chain of subbuffers is being
++ executed. */
++ gcsCMDBUFFER_PTR nextSubBuffer;
++}
++gcsCMDBUFFER;
++
++/* Command queue element. */
++typedef struct _gcsVGCMDQUEUE
++{
++ /* Pointer to the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Dynamic vs. static command buffer state. */
++ gctBOOL dynamic;
++}
++gcsVGCMDQUEUE;
++
++/* Context map entry. */
++typedef struct _gcsVGCONTEXT_MAP
++{
++ /* State index. */
++ gctUINT32 index;
++
++ /* New state value. */
++ gctUINT32 data;
++
++ /* Points to the next entry in the mod list. */
++ gcsVGCONTEXT_MAP_PTR next;
++}
++gcsVGCONTEXT_MAP;
++
++/* gcsVGCONTEXT structure that holds the current context. */
++typedef struct _gcsVGCONTEXT
++{
++ /* Context ID. */
++ gctUINT64 id;
++
++ /* State caching ebable flag. */
++ gctBOOL stateCachingEnabled;
++
++ /* Current pipe. */
++ gctUINT32 currentPipe;
++
++ /* State map/mod buffer. */
++ gctSIZE_T mapFirst;
++ gctSIZE_T mapLast;
++#ifdef __QNXNTO__
++ gctSIZE_T mapContainerSize;
++#endif
++ gcsVGCONTEXT_MAP_PTR mapContainer;
++ gcsVGCONTEXT_MAP_PTR mapPrev;
++ gcsVGCONTEXT_MAP_PTR mapCurr;
++ gcsVGCONTEXT_MAP_PTR firstPrevMap;
++ gcsVGCONTEXT_MAP_PTR firstCurrMap;
++
++ /* Main context buffer. */
++ gcsCMDBUFFER_PTR header;
++ gctUINT32_PTR buffer;
++
++ /* Completion signal. */
++ gctHANDLE process;
++ gctSIGNAL signal;
++
++#if defined(__QNXNTO__)
++ gctINT32 coid;
++ gctINT32 rcvid;
++#endif
++}
++gcsVGCONTEXT;
++
++/* User space task header. */
++typedef struct _gcsTASK * gcsTASK_PTR;
++typedef struct _gcsTASK
++{
++ /* Pointer to the next task for the same interrupt in user space. */
++ gcsTASK_PTR next;
++
++ /* Size of the task data that immediately follows the structure. */
++ gctUINT size;
++
++ /* Task data starts here. */
++ /* ... */
++}
++gcsTASK;
++
++/* User space task master table entry. */
++typedef struct _gcsTASK_MASTER_ENTRY * gcsTASK_MASTER_ENTRY_PTR;
++typedef struct _gcsTASK_MASTER_ENTRY
++{
++ /* Pointers to the head and to the tail of the task chain. */
++ gcsTASK_PTR head;
++ gcsTASK_PTR tail;
++}
++gcsTASK_MASTER_ENTRY;
++
++/* User space task master table entry. */
++typedef struct _gcsTASK_MASTER_TABLE
++{
++ /* Table with one entry per block. */
++ gcsTASK_MASTER_ENTRY table[gcvBLOCK_COUNT];
++
++ /* The total number of tasks sckeduled. */
++ gctUINT count;
++
++ /* The total size of event data in bytes. */
++ gctUINT size;
++
++#if defined(__QNXNTO__)
++ gctINT32 coid;
++ gctINT32 rcvid;
++#endif
++}
++gcsTASK_MASTER_TABLE;
++
++/******************************************************************************\
++***************************** gckVGINTERRUPT Object ******************************
++\******************************************************************************/
++
++typedef struct _gckVGINTERRUPT * gckVGINTERRUPT;
++
++typedef gceSTATUS (* gctINTERRUPT_HANDLER)(
++ IN gckVGKERNEL Kernel
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Construct(
++ IN gckVGKERNEL Kernel,
++ OUT gckVGINTERRUPT * Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Destroy(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Enable(
++ IN gckVGINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Disable(
++ IN gckVGINTERRUPT Interrupt,
++ IN gctINT32 Id
++ );
++
++#ifndef __QNXNTO__
++
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++#else
++
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt,
++ OUT gckOS *Os,
++ OUT gctSEMAPHORE *Semaphore
++ );
++
++#endif
++
++gceSTATUS
++gckVGINTERRUPT_DumpState(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++typedef struct _gckVGCOMMAND * gckVGCOMMAND;
++
++/* Construct a new gckVGCOMMAND object. */
++gceSTATUS
++gckVGCOMMAND_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT TaskGranularity,
++ IN gctUINT QueueSize,
++ OUT gckVGCOMMAND * Command
++ );
++
++/* Destroy an gckVGCOMMAND object. */
++gceSTATUS
++gckVGCOMMAND_Destroy(
++ IN gckVGCOMMAND Command
++ );
++
++/* Query command buffer attributes. */
++gceSTATUS
++gckVGCOMMAND_QueryCommandBuffer(
++ IN gckVGCOMMAND Command,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++
++/* Allocate a command queue. */
++gceSTATUS
++gckVGCOMMAND_Allocate(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer,
++ OUT gctPOINTER * Data
++ );
++
++/* Release memory held by the command queue. */
++gceSTATUS
++gckVGCOMMAND_Free(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ );
++
++/* Schedule the command queue for execution. */
++gceSTATUS
++gckVGCOMMAND_Execute(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ );
++
++/* Commit a buffer to the command queue. */
++gceSTATUS
++gckVGCOMMAND_Commit(
++ IN gckVGCOMMAND Command,
++ IN gcsVGCONTEXT_PTR Context,
++ IN gcsVGCMDQUEUE_PTR Queue,
++ IN gctUINT EntryCount,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable
++ );
++
++/******************************************************************************\
++********************************* gckVGMMU Object ********************************
++\******************************************************************************/
++
++typedef struct _gckVGMMU * gckVGMMU;
++
++/* Construct a new gckVGMMU object. */
++gceSTATUS
++gckVGMMU_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckVGMMU * Mmu
++ );
++
++/* Destroy an gckVGMMU object. */
++gceSTATUS
++gckVGMMU_Destroy(
++ IN gckVGMMU Mmu
++ );
++
++/* Allocate pages inside the MMU. */
++gceSTATUS
++gckVGMMU_AllocatePages(
++ IN gckVGMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++/* Remove a page table from the MMU. */
++gceSTATUS
++gckVGMMU_FreePages(
++ IN gckVGMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ );
++
++/* Set the MMU page with info. */
++gceSTATUS
++gckVGMMU_SetPage(
++ IN gckVGMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ );
++
++/* Flush MMU */
++gceSTATUS
++gckVGMMU_Flush(
++ IN gckVGMMU Mmu
++ );
++
++#endif /* gcdENABLE_VG */
++
++#ifdef __cplusplus
++} /* extern "C" */
++#endif
++
++#endif /* __gc_hal_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,795 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifdef MODULE
++#include <linux/module.h>
++#endif
++#include <linux/init.h>
++#include <linux/debugfs.h>
++#include <linux/slab.h>
++#ifdef MODVERSIONS
++#include <linux/modversions.h>
++#endif
++#include <linux/stddef.h>
++#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/mutex.h>
++#include <linux/vmalloc.h>
++#include <linux/types.h>
++#include <linux/fs.h>
++#include <linux/poll.h>
++#include <asm/uaccess.h>
++#include <linux/completion.h>
++#include "gc_hal_kernel_linux.h"
++
++/*
++ Prequsite:
++
++ 1) Debugfs feature must be enabled in the kernel.
++ 1.a) You can enable this, in the compilation of the uImage, all you have to do is, In the "make menuconfig" part,
++ you have to enable the debugfs in the kernel hacking part of the menu.
++
++ HOW TO USE:
++ 1) insert the driver with the following option logFileSize, Ex: insmod galcore.ko ...... logFileSize=10240
++ This gives a circular buffer of 10 MB
++
++ 2)Usually after inserting the driver, the debug file system is mounted under /sys/kernel/debug/
++
++ 2.a)If the debugfs is not mounted, you must do "mount -t debugfs none /sys/kernel/debug"
++
++ 3) To read what is being printed in the debugfs file system:
++ Ex : cat /sys/kernel/debug/gpu/galcore_trace
++
++ 4)To write into the debug file system from user side :
++ Ex: echo "hello" > cat /sys/kernel/debug/gpu/galcore_trace
++
++ 5)To write into debugfs from kernel side, Use the function called gckDebugFileSystemPrint
++
++
++ USECASE Kernel Dump:
++
++ 1) Go to /hal/inc/gc_hal_options.h, and enable the following flags:
++ - # define gcdDUMP 1
++ - # define gcdDUMP_IN_KERNEL 1
++ - # define gcdDUMP_COMMAND 1
++
++ 2) Go to /hal/kernel/gc_hal_kernel_command.c and disable the following flag
++ -#define gcdSIMPLE_COMMAND_DUMP 0
++
++ 3) Compile the driver
++ 4) insmod it with the logFileSize option
++ 5) Run an application
++ 6) You can get the dump by cat /sys/kernel/debug/gpu/galcore_trace
++
++ */
++
++/**/
++typedef va_list gctDBGARGS ;
++#define gcmkARGS_START(argument, pointer) va_start(argument, pointer)
++#define gcmkARGS_END(argument) va_end(argument)
++
++#define gcmkDBGFSPRINT(ArgumentSize, Message) \
++ { \
++ gctDBGARGS __arguments__; \
++ gcmkARGS_START(__arguments__, Message); \
++ _DebugFSPrint(ArgumentSize, Message, __arguments__);\
++ gcmkARGS_END(__arguments__); \
++ }
++
++/*Debug File System Node Struct*/
++struct _gcsDebugFileSystemNode
++{
++ /*wait queues for read and write operations*/
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ wait_queue_head_t read_q , write_q ;
++#else
++ struct wait_queue *read_q , *write_q ;
++#endif
++ struct dentry *parent ; /*parent directory*/
++ struct dentry *filen ; /*filename*/
++ struct semaphore sem ; /* mutual exclusion semaphore */
++ char *data ; /* The circular buffer data */
++ int size ; /* Size of the buffer pointed to by 'data' */
++ int refcount ; /* Files that have this buffer open */
++ int read_point ; /* Offset in circ. buffer of oldest data */
++ int write_point ; /* Offset in circ. buffer of newest data */
++ int offset ; /* Byte number of read_point in the stream */
++ struct _gcsDebugFileSystemNode *next ;
++} ;
++
++/* amount of data in the queue */
++#define gcmkNODE_QLEN(node) ( (node)->write_point >= (node)->read_point ? \
++ (node)->write_point - (node)->read_point : \
++ (node)->size - (node)->read_point + (node)->write_point)
++
++/* byte number of the last byte in the queue */
++#define gcmkNODE_FIRST_EMPTY_BYTE(node) ((node)->offset + gcmkNODE_QLEN(node))
++
++/*Synchronization primitives*/
++#define gcmkNODE_READQ(node) (&((node)->read_q))
++#define gcmkNODE_WRITEQ(node) (&((node)->write_q))
++#define gcmkNODE_SEM(node) (&((node)->sem))
++
++/*Utilities*/
++#define gcmkMIN(x, y) ((x) < (y) ? (x) : y)
++
++/*Debug File System Struct*/
++typedef struct _gcsDebugFileSystem
++{
++ gcsDebugFileSystemNode* linkedlist ;
++ gcsDebugFileSystemNode* currentNode ;
++ int isInited ;
++} gcsDebugFileSystem ;
++
++
++/*debug file system*/
++static gcsDebugFileSystem gc_dbgfs ;
++
++
++
++/*******************************************************************************
++ **
++ ** READ & WRITE FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** _ReadFromNode
++ **
++ ** 1) reading bytes out of a circular buffer with wraparound.
++ ** 2)returns caddr_t, pointer to data read, which the caller must free.
++ ** 3) length is (a pointer to) the number of bytes to be read, which will be set by this function to
++ ** be the number of bytes actually returned
++ **
++ *******************************************************************************/
++static caddr_t
++_ReadFromNode (
++ gcsDebugFileSystemNode* Node ,
++ size_t *Length ,
++ loff_t *Offset
++ )
++{
++ caddr_t retval ;
++ int bytes_copied = 0 , n , start_point , remaining ;
++
++ /* is the user trying to read data that has already scrolled off? */
++ if ( *Offset < Node->offset )
++ {
++ *Offset = Node->offset ;
++ }
++
++ /* is the user trying to read past EOF? */
++ if ( *Offset >= gcmkNODE_FIRST_EMPTY_BYTE ( Node ) )
++ {
++ return NULL ;
++ }
++
++ /* find the smaller of the total bytes we have available and what
++ * the user is asking for */
++
++ *Length = gcmkMIN ( *Length , gcmkNODE_FIRST_EMPTY_BYTE ( Node ) - *Offset ) ;
++
++ remaining = * Length ;
++
++ /* figure out where to start based on user's Offset */
++ start_point = Node->read_point + ( *Offset - Node->offset ) ;
++
++ start_point = start_point % Node->size ;
++
++ /* allocate memory to return */
++ if ( ( retval = kmalloc ( sizeof (char ) * remaining , GFP_KERNEL ) ) == NULL )
++ return NULL ;
++
++ /* copy the (possibly noncontiguous) data to our buffer */
++ while ( remaining )
++ {
++ n = gcmkMIN ( remaining , Node->size - start_point ) ;
++ memcpy ( retval + bytes_copied , Node->data + start_point , n ) ;
++ bytes_copied += n ;
++ remaining -= n ;
++ start_point = ( start_point + n ) % Node->size ;
++ }
++
++ /* advance user's file pointer */
++ *Offset += * Length ;
++
++ return retval ;
++}
++
++/*******************************************************************************
++ **
++ ** _WriteToNode
++ **
++ ** 1) writes to a circular buffer with wraparound.
++ ** 2)in case of an overflow, it overwrites the oldest unread data.
++ **
++ *********************************************************************************/
++static void
++_WriteToNode (
++ gcsDebugFileSystemNode* Node ,
++ caddr_t Buf ,
++ int Length
++ )
++{
++ int bytes_copied = 0 ;
++ int overflow = 0 ;
++ int n ;
++
++ if ( Length + gcmkNODE_QLEN ( Node ) >= ( Node->size - 1 ) )
++ {
++ overflow = 1 ;
++
++ /* in case of overflow, figure out where the new buffer will
++ * begin. we start by figuring out where the current buffer ENDS:
++ * node->parent->offset + gcmkNODE_QLEN. we then advance the end-offset
++ * by the Length of the current write, and work backwards to
++ * figure out what the oldest unoverwritten data will be (i.e.,
++ * size of the buffer). */
++ Node->offset = Node->offset + gcmkNODE_QLEN ( Node ) + Length
++ - Node->size + 1 ;
++ }
++
++ while ( Length )
++ {
++ /* how many contiguous bytes are available from the write point to
++ * the end of the circular buffer? */
++ n = gcmkMIN ( Length , Node->size - Node->write_point ) ;
++ memcpy ( Node->data + Node->write_point , Buf + bytes_copied , n ) ;
++ bytes_copied += n ;
++ Length -= n ;
++ Node->write_point = ( Node->write_point + n ) % Node->size ;
++ }
++
++ /* if there is an overflow, reset the read point to read whatever is
++ * the oldest data that we have, that has not yet been
++ * overwritten. */
++ if ( overflow )
++ {
++ Node->read_point = ( Node->write_point + 1 ) % Node->size ;
++ }
++}
++
++
++/*******************************************************************************
++ **
++ ** PRINTING UTILITY (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** _GetArgumentSize
++ **
++ **
++ *******************************************************************************/
++static gctINT
++_GetArgumentSize (
++ IN gctCONST_STRING Message
++ )
++{
++ gctINT i , count ;
++
++ for ( i = 0 , count = 0 ; Message[i] ; i += 1 )
++ {
++ if ( Message[i] == '%' )
++ {
++ count += 1 ;
++ }
++ }
++ return count * sizeof (unsigned int ) ;
++}
++
++/*******************************************************************************
++ **
++ ** _AppendString
++ **
++ **
++ *******************************************************************************/
++static ssize_t
++_AppendString (
++ IN gcsDebugFileSystemNode* Node ,
++ IN gctCONST_STRING String ,
++ IN int Length
++ )
++{
++ caddr_t message = NULL ;
++ int n ;
++
++ /* if the message is longer than the buffer, just take the beginning
++ * of it, in hopes that the reader (if any) will have time to read
++ * before we wrap around and obliterate it */
++ n = gcmkMIN ( Length , Node->size - 1 ) ;
++
++ /* make sure we have the memory for it */
++ if ( ( message = kmalloc ( n , GFP_KERNEL ) ) == NULL )
++ return - ENOMEM ;
++
++ /* copy into our temp buffer */
++ memcpy ( message , String , n ) ;
++
++ /* now copy it into the circular buffer and free our temp copy */
++ _WriteToNode ( Node , message , n ) ;
++ kfree ( message ) ;
++ return n ;
++}
++
++/*******************************************************************************
++ **
++ ** _DebugFSPrint
++ **
++ **
++ *******************************************************************************/
++static void
++_DebugFSPrint (
++ IN unsigned int ArgumentSize ,
++ IN const char* Message ,
++ IN gctDBGARGS Arguments
++
++ )
++{
++ char buffer[MAX_LINE_SIZE] ;
++ int len ;
++ down ( gcmkNODE_SEM ( gc_dbgfs.currentNode ) ) ;
++ len = vsnprintf ( buffer , sizeof (buffer ) , Message , *( va_list * ) & Arguments ) ;
++ buffer[len] = '\0' ;
++
++ /* Add end-of-line if missing. */
++ if ( buffer[len - 1] != '\n' )
++ {
++ buffer[len ++] = '\n' ;
++ buffer[len] = '\0' ;
++ }
++ _AppendString ( gc_dbgfs.currentNode , buffer , len ) ;
++ up ( gcmkNODE_SEM ( gc_dbgfs.currentNode ) ) ;
++ wake_up_interruptible ( gcmkNODE_READQ ( gc_dbgfs.currentNode ) ) ; /* blocked in read*/
++}
++
++/*******************************************************************************
++ **
++ ** LINUX SYSTEM FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** find the vivlog structure associated with an inode.
++ ** returns a pointer to the structure if found, NULL if not found
++ **
++ *******************************************************************************/
++static gcsDebugFileSystemNode*
++_GetNodeInfo (
++ IN struct inode *Inode
++ )
++{
++ gcsDebugFileSystemNode* node ;
++
++ if ( Inode == NULL )
++ return NULL ;
++
++ for ( node = gc_dbgfs.linkedlist ; node != NULL ; node = node->next )
++ if ( node->filen->d_inode->i_ino == Inode->i_ino )
++ return node ;
++
++ return NULL ;
++}
++
++/*******************************************************************************
++ **
++ ** _DebugFSRead
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSRead (
++ struct file *file ,
++ char __user * buffer ,
++ size_t length ,
++ loff_t * offset
++ )
++{
++ int retval ;
++ caddr_t data_to_return ;
++ gcsDebugFileSystemNode* node ;
++ /* get the metadata about this emlog */
++ if ( ( node = _GetNodeInfo ( file->f_dentry->d_inode ) ) == NULL )
++ {
++ printk ( "debugfs_read: record not found\n" ) ;
++ return - EIO ;
++ }
++
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++
++ /* wait until there's data available (unless we do nonblocking reads) */
++ while ( *offset >= gcmkNODE_FIRST_EMPTY_BYTE ( node ) )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ if ( file->f_flags & O_NONBLOCK )
++ {
++ return - EAGAIN ;
++ }
++ if ( wait_event_interruptible ( ( *( gcmkNODE_READQ ( node ) ) ) , ( *offset < gcmkNODE_FIRST_EMPTY_BYTE ( node ) ) ) )
++ {
++ return - ERESTARTSYS ; /* signal: tell the fs layer to handle it */
++ }
++ /* otherwise loop, but first reacquire the lock */
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++ }
++ data_to_return = _ReadFromNode ( node , &length , offset ) ;
++ if ( data_to_return == NULL )
++ {
++ retval = 0 ;
++ goto unlock ;
++ }
++ if ( copy_to_user ( buffer , data_to_return , length ) > 0 )
++ {
++ retval = - EFAULT ;
++ }
++ else
++ {
++ retval = length ;
++ }
++ kfree ( data_to_return ) ;
++unlock:
++ up ( gcmkNODE_SEM ( node ) ) ;
++ wake_up_interruptible ( gcmkNODE_WRITEQ ( node ) ) ;
++ return retval ;
++}
++
++/*******************************************************************************
++ **
++ **_DebugFSWrite
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSWrite (
++ struct file *file ,
++ const char __user * buffer ,
++ size_t length ,
++ loff_t * offset
++ )
++{
++ caddr_t message = NULL ;
++ int n ;
++ gcsDebugFileSystemNode*node ;
++
++ /* get the metadata about this log */
++ if ( ( node = _GetNodeInfo ( file->f_dentry->d_inode ) ) == NULL )
++ {
++ return - EIO ;
++ }
++
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++
++ /* if the message is longer than the buffer, just take the beginning
++ * of it, in hopes that the reader (if any) will have time to read
++ * before we wrap around and obliterate it */
++ n = gcmkMIN ( length , node->size - 1 ) ;
++
++ /* make sure we have the memory for it */
++ if ( ( message = kmalloc ( n , GFP_KERNEL ) ) == NULL )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ return - ENOMEM ;
++ }
++
++ /* copy into our temp buffer */
++ if ( copy_from_user ( message , buffer , n ) > 0 )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ kfree ( message ) ;
++ return - EFAULT ;
++ }
++
++ /* now copy it into the circular buffer and free our temp copy */
++ _WriteToNode ( node , message , n ) ;
++
++ kfree ( message ) ;
++ up ( gcmkNODE_SEM ( node ) ) ;
++
++ /* wake up any readers that might be waiting for the data. we call
++ * schedule in the vague hope that a reader will run before the
++ * writer's next write, to avoid losing data. */
++ wake_up_interruptible ( gcmkNODE_READQ ( node ) ) ;
++
++ return n ;
++}
++
++/*******************************************************************************
++ **
++ ** File Operations Table
++ **
++ *******************************************************************************/
++static const struct file_operations debugfs_operations = {
++ .owner = THIS_MODULE ,
++ .read = _DebugFSRead ,
++ .write = _DebugFSWrite ,
++} ;
++
++/*******************************************************************************
++ **
++ ** INTERFACE FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemIsEnabled
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++
++gctINT
++gckDebugFileSystemIsEnabled ( void )
++{
++ return gc_dbgfs.isInited ;
++}
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemInitialize
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++gctINT
++gckDebugFileSystemInitialize ( void )
++{
++ if ( ! gc_dbgfs.isInited )
++ {
++ gc_dbgfs.linkedlist = gcvNULL ;
++ gc_dbgfs.currentNode = gcvNULL ;
++ gc_dbgfs.isInited = 1 ;
++ }
++ return gc_dbgfs.isInited ;
++}
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemTerminate
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++gctINT
++gckDebugFileSystemTerminate ( void )
++{
++ gcsDebugFileSystemNode * next = gcvNULL ;
++ gcsDebugFileSystemNode * temp = gcvNULL ;
++ if ( gc_dbgfs.isInited )
++ {
++ temp = gc_dbgfs.linkedlist ;
++ while ( temp != gcvNULL )
++ {
++ next = temp->next ;
++ gckDebugFileSystemFreeNode ( temp ) ;
++ kfree ( temp ) ;
++ temp = next ;
++ }
++ gc_dbgfs.isInited = 0 ;
++ }
++ return 0 ;
++}
++
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemCreateNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ ** gckDebugFileSystemFreeNode * Device
++ ** Pointer to a variable receiving the gcsDebugFileSystemNode object pointer on
++ ** success.
++ *********************************************************************************/
++
++gctINT
++gckDebugFileSystemCreateNode (
++ IN gctINT SizeInKB ,
++ IN gctCONST_STRING ParentName ,
++ IN gctCONST_STRING NodeName ,
++ OUT gcsDebugFileSystemNode **Node
++ )
++{
++ gcsDebugFileSystemNode*node ;
++ /* allocate space for our metadata and initialize it */
++ if ( ( node = kmalloc ( sizeof (gcsDebugFileSystemNode ) , GFP_KERNEL ) ) == NULL )
++ goto struct_malloc_failed ;
++
++ /*Zero it out*/
++ memset ( node , 0 , sizeof (gcsDebugFileSystemNode ) ) ;
++
++ /*Init the sync primitives*/
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ init_waitqueue_head ( gcmkNODE_READQ ( node ) ) ;
++#else
++ init_waitqueue ( gcmkNODE_READQ ( node ) ) ;
++#endif
++
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ init_waitqueue_head ( gcmkNODE_WRITEQ ( node ) ) ;
++#else
++ init_waitqueue ( gcmkNODE_WRITEQ ( node ) ) ;
++#endif
++ sema_init ( gcmkNODE_SEM ( node ) , 1 ) ;
++ /*End the sync primitives*/
++
++
++ /* figure out how much of a buffer this should be and allocate the buffer */
++ node->size = 1024 * SizeInKB ;
++ if ( ( node->data = ( char * ) vmalloc ( sizeof (char ) * node->size ) ) == NULL )
++ goto data_malloc_failed ;
++
++ /*creating the debug file system*/
++ node->parent = debugfs_create_dir ( ParentName , NULL ) ;
++
++ /*creating the file*/
++ node->filen = debugfs_create_file ( NodeName , S_IRUGO | S_IWUSR , node->parent , NULL ,
++ &debugfs_operations ) ;
++
++ /* add it to our linked list */
++ node->next = gc_dbgfs.linkedlist ;
++ gc_dbgfs.linkedlist = node ;
++
++ /* pass the struct back */
++ *Node = node ;
++ return 0 ;
++
++ vfree ( node->data ) ;
++data_malloc_failed:
++ kfree ( node ) ;
++struct_malloc_failed:
++ return - ENOMEM ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemFreeNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDebugFileSystemFreeNode (
++ IN gcsDebugFileSystemNode * Node
++ )
++{
++
++ gcsDebugFileSystemNode **ptr ;
++
++ if ( Node == NULL )
++ {
++ printk ( "null passed to free_vinfo\n" ) ;
++ return ;
++ }
++
++ down ( gcmkNODE_SEM ( Node ) ) ;
++ /*free data*/
++ vfree ( Node->data ) ;
++
++ /*Close Debug fs*/
++ if ( Node->filen )
++ {
++ debugfs_remove ( Node->filen ) ;
++ }
++ if ( Node->parent )
++ {
++ debugfs_remove ( Node->parent ) ;
++ }
++
++ /* now delete the node from the linked list */
++ ptr = & ( gc_dbgfs.linkedlist ) ;
++ while ( *ptr != Node )
++ {
++ if ( ! *ptr )
++ {
++ printk ( "corrupt info list!\n" ) ;
++ break ;
++ }
++ else
++ ptr = & ( ( **ptr ).next ) ;
++ }
++ *ptr = Node->next ;
++ up ( gcmkNODE_SEM ( Node ) ) ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemSetCurrentNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDebugFileSystemSetCurrentNode (
++ IN gcsDebugFileSystemNode * Node
++ )
++{
++ gc_dbgfs.currentNode = Node ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemGetCurrentNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDebugFileSystemGetCurrentNode (
++ OUT gcsDebugFileSystemNode ** Node
++ )
++{
++ *Node = gc_dbgfs.currentNode ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDebugFileSystemPrint
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDebugFileSystemPrint (
++ IN gctCONST_STRING Message ,
++ ...
++ )
++{
++ gcmkDBGFSPRINT ( _GetArgumentSize ( Message ) , Message ) ;
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,84 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <stdarg.h>
++
++#ifndef __gc_hal_kernel_debugfs_h_
++#define __gc_hal_kernel_debugfs_h_
++
++ #define MAX_LINE_SIZE 768 /* Max bytes for a line of debug info */
++
++
++ typedef struct _gcsDebugFileSystemNode gcsDebugFileSystemNode ;
++
++
++/*******************************************************************************
++ **
++ ** System Related
++ **
++ *******************************************************************************/
++
++gctINT gckDebugFileSystemIsEnabled(void);
++
++gctINT gckDebugFileSystemInitialize(void);
++
++gctINT gckDebugFileSystemTerminate(void);
++
++
++/*******************************************************************************
++ **
++ ** Node Related
++ **
++ *******************************************************************************/
++
++gctINT gckDebugFileSystemCreateNode(
++ IN gctINT SizeInKB,
++ IN gctCONST_STRING ParentName ,
++ IN gctCONST_STRING NodeName,
++ OUT gcsDebugFileSystemNode **Node
++ );
++
++
++void gckDebugFileSystemFreeNode(
++ IN gcsDebugFileSystemNode * Node
++ );
++
++
++
++void gckDebugFileSystemSetCurrentNode(
++ IN gcsDebugFileSystemNode * Node
++ );
++
++
++
++void gckDebugFileSystemGetCurrentNode(
++ OUT gcsDebugFileSystemNode ** Node
++ );
++
++
++void gckDebugFileSystemPrint(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#endif
++
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,102 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_debug_h_
++#define __gc_hal_kernel_debug_h_
++
++#include <gc_hal_kernel_linux.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++#include <stdarg.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** OS-dependent Macros *****************************
++\******************************************************************************/
++
++typedef va_list gctARGUMENTS;
++
++#define gcmkARGUMENTS_START(Arguments, Pointer) \
++ va_start(Arguments, Pointer)
++
++#define gcmkARGUMENTS_END(Arguments) \
++ va_end(Arguments)
++
++#define gcmkDECLARE_LOCK(__spinLock__) \
++ static DEFINE_SPINLOCK(__spinLock__);
++
++#define gcmkLOCKSECTION(__spinLock__) \
++ spin_lock(&__spinLock__)
++
++#define gcmkUNLOCKSECTION(__spinLock__) \
++ spin_unlock(&__spinLock__)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++# define gcmkGETPROCESSID() \
++ task_tgid_vnr(current)
++#else
++# define gcmkGETPROCESSID() \
++ current->tgid
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++# define gcmkGETTHREADID() \
++ task_pid_vnr(current)
++#else
++# define gcmkGETTHREADID() \
++ current->pid
++#endif
++
++#define gcmkOUTPUT_STRING(String) \
++ if(gckDebugFileSystemIsEnabled()) \
++ gckDebugFileSystemPrint(String);\
++ else\
++ printk(String); \
++ touch_softlockup_watchdog()
++
++
++#define gcmkSPRINTF(Destination, Size, Message, Value) \
++ snprintf(Destination, Size, Message, Value)
++
++#define gcmkSPRINTF2(Destination, Size, Message, Value1, Value2) \
++ snprintf(Destination, Size, Message, Value1, Value2)
++
++#define gcmkSPRINTF3(Destination, Size, Message, Value1, Value2, Value3) \
++ snprintf(Destination, Size, Message, Value1, Value2, Value3)
++
++#define gcmkVSPRINTF(Destination, Size, Message, Arguments) \
++ vsnprintf(Destination, Size, Message, *(va_list *) &Arguments)
++
++#define gcmkSTRCAT(Destination, Size, String) \
++ strncat(Destination, String, Size)
++
++/* If not zero, forces data alignment in the variable argument list
++ by its individual size. */
++#define gcdALIGNBYSIZE 1
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_debug_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,1652 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mm.h>
++#include <linux/mman.h>
++#include <linux/slab.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++#include <mach/hardware.h>
++#endif
++#include <linux/pm_runtime.h>
++
++#define _GC_OBJ_ZONE gcvZONE_DEVICE
++
++#define DEBUG_FILE "galcore_trace"
++#define PARENT_FILE "gpu"
++
++
++#ifdef FLAREON
++ static struct dove_gpio_irq_handler gc500_handle;
++#endif
++
++#define gcmIS_CORE_PRESENT(Device, Core) (Device->irqLines[Core] > 0)
++
++/******************************************************************************\
++*************************** Memory Allocation Wrappers *************************
++\******************************************************************************/
++
++static gceSTATUS
++_AllocateMemory(
++ IN gckGALDEVICE Device,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER *Logical,
++ OUT gctPHYS_ADDR *Physical,
++ OUT gctUINT32 *PhysAddr
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Bytes=%lu", Device, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++ gcmkVERIFY_ARGUMENT(Logical != NULL);
++ gcmkVERIFY_ARGUMENT(Physical != NULL);
++ gcmkVERIFY_ARGUMENT(PhysAddr != NULL);
++
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Device->os, gcvFALSE, &Bytes, Physical, Logical
++ ));
++
++ *PhysAddr = ((PLINUX_MDL)*Physical)->dmaHandle - Device->baseAddress;
++
++ /* Success. */
++ gcmkFOOTER_ARG(
++ "*Logical=0x%x *Physical=0x%x *PhysAddr=0x%08x",
++ *Logical, *Physical, *PhysAddr
++ );
++
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_FreeMemory(
++ IN gckGALDEVICE Device,
++ IN gctPOINTER Logical,
++ IN gctPHYS_ADDR Physical)
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Logical=0x%x Physical=0x%x",
++ Device, Logical, Physical);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ status = gckOS_FreeContiguous(
++ Device->os, Physical, Logical,
++ ((PLINUX_MDL) Physical)->numPages * PAGE_SIZE
++ );
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++
++/******************************************************************************\
++******************************* Interrupt Handler ******************************
++\******************************************************************************/
++static irqreturn_t isrRoutine(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], gcvNOTIFY_INTERRUPT, gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ device->dataReadys[gcvCORE_MAJOR] = gcvTRUE;
++
++ up(&device->semas[gcvCORE_MAJOR]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_MAJOR]);
++ if (down); /*To make gcc 4.6 happye*/
++ device->dataReadys[gcvCORE_MAJOR] = gcvFALSE;
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], gcvNOTIFY_INTERRUPT, gcvFALSE);
++ }
++}
++
++static irqreturn_t isrRoutine2D(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_2D], gcvNOTIFY_INTERRUPT, gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ device->dataReadys[gcvCORE_2D] = gcvTRUE;
++
++ up(&device->semas[gcvCORE_2D]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine2D(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_2D]);
++ if (down); /*To make gcc 4.6 happye*/
++ device->dataReadys[gcvCORE_2D] = gcvFALSE;
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_2D], gcvNOTIFY_INTERRUPT, gcvFALSE);
++ }
++}
++
++static irqreturn_t isrRoutineVG(int irq, void *ctxt)
++{
++#if gcdENABLE_VG
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Serve the interrupt. */
++ status = gckVGINTERRUPT_Enque(device->kernels[gcvCORE_VG]->vg->interrupt);
++
++ /* Determine the return value. */
++ return (status == gcvSTATUS_NOT_OUR_INTERRUPT)
++ ? IRQ_RETVAL(0)
++ : IRQ_RETVAL(1);
++#else
++ return IRQ_NONE;
++#endif
++}
++
++static int threadRoutineVG(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_VG]);
++ if (down); /*To make gcc 4.6 happye*/
++ device->dataReadys[gcvCORE_VG] = gcvFALSE;
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_VG], gcvNOTIFY_INTERRUPT, gcvFALSE);
++ }
++}
++
++/******************************************************************************\
++******************************* gckGALDEVICE Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Setup_ISR
++**
++** Start the ISR routine.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Setup successfully.
++** gcvSTATUS_GENERIC_IO
++** Setup failed.
++*/
++static gceSTATUS
++gckGALDEVICE_Setup_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gceSTATUS status;
++ int ret = -1;
++
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[Core] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Hook up the isr based on the irq line. */
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutine, IRQF_DISABLED,
++ "galcore interrupt service", Device
++ );
++ break;
++ case gcvCORE_2D:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutine2D, IRQF_DISABLED,
++ "galcore 2D interrupt service", Device
++ );
++ break;
++ case gcvCORE_VG:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutineVG, IRQF_DISABLED,
++ "galcore VG interrupt service", Device
++ );
++ break;
++ default:
++ break;
++ }
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLines[Core], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++
++ /* Make sure ISR is disabled to start. */
++ disable_irq(Device->irqLines[Core]);
++ Device->isrEnabled[Core] = gcvFALSE;
++
++ /* Mark ISR as initialized. */
++ Device->isrInitializeds[Core] = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckGALDEVICE_Enable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[Core] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ spin_lock(&Device->kernels[Core]->irq_lock);
++ if (Device->isrEnabled[Core] == gcvFALSE)
++ {
++ enable_irq(Device->irqLines[Core]);
++ /* Mark ISR as initialized. */
++ Device->isrEnabled[Core] = gcvTRUE;
++ }
++ spin_unlock(&Device->kernels[Core]->irq_lock);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Release_ISR
++**
++** Release the irq line.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++static gceSTATUS
++gckGALDEVICE_Release_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ /* release the irq */
++ if (Device->isrInitializeds[Core])
++ {
++ free_irq(Device->irqLines[Core], Device);
++
++ Device->isrInitializeds[Core] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++gckGALDEVICE_Disable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ /* disable the irq */
++ spin_lock(&Device->kernels[Core]->irq_lock);
++ if (Device->isrEnabled[Core])
++ {
++ disable_irq(Device->irqLines[Core]);
++
++ Device->isrEnabled[Core] = gcvFALSE;
++ }
++ spin_unlock(&Device->kernels[Core]->irq_lock);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Start_Threads
++**
++** Start the daemon threads.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Start successfully.
++** gcvSTATUS_GENERIC_IO
++** Start failed.
++*/
++gceSTATUS
++gckGALDEVICE_Start_Threads(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++ struct task_struct * task;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine, Device, "galcore daemon thread");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_MAJOR] = task;
++ Device->threadInitializeds[gcvCORE_MAJOR] = gcvTRUE;
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine2D, Device, "galcore daemon thread for 2D");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_2D] = task;
++ Device->threadInitializeds[gcvCORE_2D] = gcvTRUE;
++ }
++ else
++ {
++ Device->threadInitializeds[gcvCORE_2D] = gcvFALSE;
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutineVG, Device, "galcore daemon thread for VG");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_VG] = task;
++ Device->threadInitializeds[gcvCORE_VG] = gcvTRUE;
++ }
++ else
++ {
++ Device->threadInitializeds[gcvCORE_VG] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Stop_Threads
++**
++** Stop the gal device, including the following actions: stop the daemon
++** thread, release the irq.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Stop_Threads(
++ gckGALDEVICE Device
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ /* Stop the kernel threads. */
++ if (Device->threadInitializeds[i])
++ {
++ Device->killThread = gcvTRUE;
++ up(&Device->semas[i]);
++
++ kthread_stop(Device->threadCtxts[i]);
++ Device->threadCtxts[i] = gcvNULL;
++ Device->threadInitializeds[i] = gcvFALSE;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Start
++**
++** Start the gal device, including the following actions: setup the isr routine
++** and start the daemoni thread.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Start successfully.
++*/
++gceSTATUS
++gckGALDEVICE_Start(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ /* Start the kernel thread. */
++ gcmkONERROR(gckGALDEVICE_Start_Threads(Device));
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_MAJOR));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_2D));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++ }
++
++#if gcdENABLE_VG
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_VG));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++ }
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Stop
++**
++** Stop the gal device, including the following actions: stop the daemon
++** thread, release the irq.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Stop(
++ gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF
++ ));
++
++ /* Remove the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_MAJOR));
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_2D));
++
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF
++ ));
++ }
++
++#if gcdENABLE_VG
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_VG));
++
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF
++ ));
++ }
++#endif
++
++ /* Stop the kernel thread. */
++ gcmkONERROR(gckGALDEVICE_Stop_Threads(Device));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Construct
++**
++** Constructor.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gckGALDEVICE * Device
++** Pointer to a variable receiving the gckGALDEVICE object pointer on
++** success.
++*/
++gceSTATUS
++gckGALDEVICE_Construct(
++ IN gctINT IrqLine,
++ IN gctUINT32 RegisterMemBase,
++ IN gctSIZE_T RegisterMemSize,
++ IN gctINT IrqLine2D,
++ IN gctUINT32 RegisterMemBase2D,
++ IN gctSIZE_T RegisterMemSize2D,
++ IN gctINT IrqLineVG,
++ IN gctUINT32 RegisterMemBaseVG,
++ IN gctSIZE_T RegisterMemSizeVG,
++ IN gctUINT32 ContiguousBase,
++ IN gctSIZE_T ContiguousSize,
++ IN gctSIZE_T BankSize,
++ IN gctINT FastClear,
++ IN gctINT Compression,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize,
++ IN gctINT Signal,
++ IN gctUINT LogFileSize,
++ IN struct device *pdev,
++ IN gctINT PowerManagement,
++ IN gctINT GpuProfiler,
++ OUT gckGALDEVICE *Device
++ )
++{
++ gctUINT32 internalBaseAddress = 0, internalAlignment = 0;
++ gctUINT32 externalBaseAddress = 0, externalAlignment = 0;
++ gctUINT32 horizontalTileSize, verticalTileSize;
++ struct resource* mem_region;
++ gctUINT32 physAddr;
++ gctUINT32 physical;
++ gckGALDEVICE device;
++ gceSTATUS status;
++ gctINT32 i;
++ gceHARDWARE_TYPE type;
++ gckDB sharedDB = gcvNULL;
++ gckKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("IrqLine=%d RegisterMemBase=0x%08x RegisterMemSize=%u "
++ "IrqLine2D=%d RegisterMemBase2D=0x%08x RegisterMemSize2D=%u "
++ "IrqLineVG=%d RegisterMemBaseVG=0x%08x RegisterMemSizeVG=%u "
++ "ContiguousBase=0x%08x ContiguousSize=%lu BankSize=%lu "
++ "FastClear=%d Compression=%d PhysBaseAddr=0x%x PhysSize=%d Signal=%d",
++ IrqLine, RegisterMemBase, RegisterMemSize,
++ IrqLine2D, RegisterMemBase2D, RegisterMemSize2D,
++ IrqLineVG, RegisterMemBaseVG, RegisterMemSizeVG,
++ ContiguousBase, ContiguousSize, BankSize, FastClear, Compression,
++ PhysBaseAddr, PhysSize, Signal);
++
++ /* Allocate device structure. */
++ device = kmalloc(sizeof(struct _gckGALDEVICE), GFP_KERNEL | __GFP_NOWARN);
++
++ if (!device)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ memset(device, 0, sizeof(struct _gckGALDEVICE));
++
++ device->dbgnode = gcvNULL;
++ if(LogFileSize != 0)
++ {
++ if(gckDebugFileSystemCreateNode(LogFileSize,PARENT_FILE,DEBUG_FILE,&(device->dbgnode)) != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the debug file system %s/%s \n",
++ __FUNCTION__, __LINE__,
++ PARENT_FILE, DEBUG_FILE
++ );
++ }
++ else
++ {
++ /*Everything is OK*/
++ gckDebugFileSystemSetCurrentNode(device->dbgnode);
++ }
++ }
++#ifdef CONFIG_PM
++ /*Init runtime pm for gpu*/
++ pm_runtime_enable(pdev);
++ device->pmdev = pdev;
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ /*get gpu regulator*/
++ device->gpu_regulator = regulator_get(pdev, "cpu_vddgpu");
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ device->gpu_regulator = devm_regulator_get(pdev, "pu");
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if (IS_ERR(device->gpu_regulator)) {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to get gpu regulator %s/%s \n",
++ __FUNCTION__, __LINE__,
++ PARENT_FILE, DEBUG_FILE);
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++#endif
++ /*Initialize the clock structure*/
++ if (IrqLine != -1) {
++ device->clk_3d_core = clk_get(pdev, "gpu3d_clk");
++ if (!IS_ERR(device->clk_3d_core)) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (cpu_is_mx6q()) {
++ device->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(device->clk_3d_shader)) {
++ IrqLine = -1;
++ clk_put(device->clk_3d_core);
++ device->clk_3d_core = NULL;
++ device->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++ }
++#else
++ device->clk_3d_axi = clk_get(pdev, "gpu3d_axi_clk");
++ device->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(device->clk_3d_shader)) {
++ IrqLine = -1;
++ clk_put(device->clk_3d_core);
++ device->clk_3d_core = NULL;
++ device->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++#endif
++ } else {
++ IrqLine = -1;
++ device->clk_3d_core = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_clk failed, disable 3d!\n");
++ }
++ }
++ if ((IrqLine2D != -1) || (IrqLineVG != -1)) {
++ device->clk_2d_core = clk_get(pdev, "gpu2d_clk");
++ if (IS_ERR(device->clk_2d_core)) {
++ IrqLine2D = -1;
++ IrqLineVG = -1;
++ device->clk_2d_core = NULL;
++ gckOS_Print("galcore: clk_get 2d core clock failed, disable 2d/vg!\n");
++ } else {
++ if (IrqLine2D != -1) {
++ device->clk_2d_axi = clk_get(pdev, "gpu2d_axi_clk");
++ if (IS_ERR(device->clk_2d_axi)) {
++ device->clk_2d_axi = NULL;
++ IrqLine2D = -1;
++ gckOS_Print("galcore: clk_get 2d axi clock failed, disable 2d\n");
++ }
++ }
++ if (IrqLineVG != -1) {
++ device->clk_vg_axi = clk_get(pdev, "openvg_axi_clk");
++ if (IS_ERR(device->clk_vg_axi)) {
++ IrqLineVG = -1;
++ device->clk_vg_axi = NULL;
++ gckOS_Print("galcore: clk_get vg clock failed, disable vg!\n");
++ }
++ }
++ }
++ }
++
++ if (IrqLine != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_MAJOR] = RegisterMemBase;
++ device->requestedRegisterMemSizes[gcvCORE_MAJOR] = RegisterMemSize;
++ }
++
++ if (IrqLine2D != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_2D] = RegisterMemBase2D;
++ device->requestedRegisterMemSizes[gcvCORE_2D] = RegisterMemSize2D;
++ }
++
++ if (IrqLineVG != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_VG] = RegisterMemBaseVG;
++ device->requestedRegisterMemSizes[gcvCORE_VG] = RegisterMemSizeVG;
++ }
++
++ device->requestedContiguousBase = 0;
++ device->requestedContiguousSize = 0;
++
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ physical = device->requestedRegisterMemBases[i];
++
++ /* Set up register memory region. */
++ if (physical != 0)
++ {
++ mem_region = request_mem_region(
++ physical, device->requestedRegisterMemSizes[i], "galcore register region"
++ );
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %lu bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSizes[i]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->registerBases[i] = (gctPOINTER) ioremap_nocache(
++ physical, device->requestedRegisterMemSizes[i]);
++
++ if (device->registerBases[i] == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unable to map %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSizes[i]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ physical += device->requestedRegisterMemSizes[i];
++ }
++ else
++ {
++ device->registerBases[i] = gcvNULL;
++ }
++ }
++
++ /* Set the base address */
++ device->baseAddress = PhysBaseAddr;
++
++ /* Construct the gckOS object. */
++ gcmkONERROR(gckOS_Construct(device, &device->os));
++
++ if (IrqLine != -1)
++ {
++ /* Construct the gckKERNEL object. */
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_MAJOR, device,
++ gcvNULL, &device->kernels[gcvCORE_MAJOR]));
++
++ sharedDB = device->kernels[gcvCORE_MAJOR]->db;
++
++ /* Initialize core mapping */
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_MAJOR;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_MAJOR]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Enable_ISR,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Disable_ISR,
++ device
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(
++ device->kernels[gcvCORE_MAJOR]->hardware, FastClear, Compression
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_MAJOR]->hardware, PowerManagement
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetGpuProfiler(
++ device->kernels[gcvCORE_MAJOR]->hardware, GpuProfiler
++ ));
++
++#if COMMAND_PROCESSOR_VERSION == 1
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_MAJOR]->command));
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_MAJOR] = gcvNULL;
++ }
++
++ if (IrqLine2D != -1)
++ {
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_2D, device,
++ sharedDB, &device->kernels[gcvCORE_2D]));
++
++ if (sharedDB == gcvNULL) sharedDB = device->kernels[gcvCORE_2D]->db;
++
++ /* Verify the hardware type */
++ gcmkONERROR(gckHARDWARE_GetType(device->kernels[gcvCORE_2D]->hardware, &type));
++
++ if (type != gcvHARDWARE_2D)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unexpected hardware type: %d\n",
++ __FUNCTION__, __LINE__,
++ type
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL)
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_2D;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_2D] = gcvCORE_2D;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_2D]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Enable_ISR,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Disable_ISR,
++ device
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_2D]->hardware, PowerManagement
++ ));
++
++
++#if COMMAND_PROCESSOR_VERSION == 1
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_2D]->command));
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_2D] = gcvNULL;
++ }
++
++ if (IrqLineVG != -1)
++ {
++#if gcdENABLE_VG
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_VG, device,
++ sharedDB, &device->kernels[gcvCORE_VG]));
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL
++ && device->kernels[gcvCORE_2D] == gcvNULL
++ )
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_VG;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_VG] = gcvCORE_VG;
++ }
++
++
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_VG]->vg->hardware,
++ PowerManagement
++ ));
++
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_VG] = gcvNULL;
++ }
++
++ /* Initialize the ISR. */
++ device->irqLines[gcvCORE_MAJOR] = IrqLine;
++ device->irqLines[gcvCORE_2D] = IrqLine2D;
++ device->irqLines[gcvCORE_VG] = IrqLineVG;
++
++ /* Initialize the kernel thread semaphores. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->irqLines[i] != -1) sema_init(&device->semas[i], 0);
++ }
++
++ device->signal = Signal;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL) break;
++ }
++
++ if (i == gcdMAX_GPU_COUNT)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ /* Query the ceiling of the system memory. */
++ gcmkONERROR(gckVGHARDWARE_QuerySystemMemory(
++ device->kernels[i]->vg->hardware,
++ &device->systemMemorySize,
++ &device->systemMemoryBaseAddress
++ ));
++ /* query the amount of video memory */
++ gcmkONERROR(gckVGHARDWARE_QueryMemory(
++ device->kernels[i]->vg->hardware,
++ &device->internalSize, &internalBaseAddress, &internalAlignment,
++ &device->externalSize, &externalBaseAddress, &externalAlignment,
++ &horizontalTileSize, &verticalTileSize
++ ));
++ }
++ else
++#endif
++ {
++ /* Query the ceiling of the system memory. */
++ gcmkONERROR(gckHARDWARE_QuerySystemMemory(
++ device->kernels[i]->hardware,
++ &device->systemMemorySize,
++ &device->systemMemoryBaseAddress
++ ));
++
++ /* query the amount of video memory */
++ gcmkONERROR(gckHARDWARE_QueryMemory(
++ device->kernels[i]->hardware,
++ &device->internalSize, &internalBaseAddress, &internalAlignment,
++ &device->externalSize, &externalBaseAddress, &externalAlignment,
++ &horizontalTileSize, &verticalTileSize
++ ));
++ }
++
++
++ /* Grab the first availiable kernel */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->irqLines[i] != -1)
++ {
++ kernel = device->kernels[i];
++ break;
++ }
++ }
++
++ /* Set up the internal memory region. */
++ if (device->internalSize > 0)
++ {
++ status = gckVIDMEM_Construct(
++ device->os,
++ internalBaseAddress, device->internalSize, internalAlignment,
++ 0, &device->internalVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable internal heap. */
++ device->internalSize = 0;
++ }
++ else
++ {
++ /* Map internal memory. */
++ device->internalLogical
++ = (gctPOINTER) ioremap_nocache(physical, device->internalSize);
++
++ if (device->internalLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->internalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical;
++ device->internalPhysicalName = gcmPTR_TO_NAME(device->internalPhysical);
++ physical += device->internalSize;
++ }
++ }
++
++ if (device->externalSize > 0)
++ {
++ /* create the external memory heap */
++ status = gckVIDMEM_Construct(
++ device->os,
++ externalBaseAddress, device->externalSize, externalAlignment,
++ 0, &device->externalVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable internal heap. */
++ device->externalSize = 0;
++ }
++ else
++ {
++ /* Map external memory. */
++ device->externalLogical
++ = (gctPOINTER) ioremap_nocache(physical, device->externalSize);
++
++ if (device->externalLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->externalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical;
++ device->externalPhysicalName = gcmPTR_TO_NAME(device->externalPhysical);
++ physical += device->externalSize;
++ }
++ }
++
++ /* set up the contiguous memory */
++ device->contiguousSize = ContiguousSize;
++
++ if (ContiguousSize > 0)
++ {
++ if (ContiguousBase == 0)
++ {
++ while (device->contiguousSize > 0)
++ {
++ /* Allocate contiguous memory. */
++ status = _AllocateMemory(
++ device,
++ device->contiguousSize,
++ &device->contiguousBase,
++ &device->contiguousPhysical,
++ &physAddr
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ device->contiguousPhysicalName = gcmPTR_TO_NAME(device->contiguousPhysical);
++ status = gckVIDMEM_Construct(
++ device->os,
++ physAddr | device->systemMemoryBaseAddress,
++ device->contiguousSize,
++ 64,
++ BankSize,
++ &device->contiguousVidMem
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ break;
++ }
++
++ gcmkONERROR(_FreeMemory(
++ device,
++ device->contiguousBase,
++ device->contiguousPhysical
++ ));
++
++ gcmRELEASE_NAME(device->contiguousPhysicalName);
++ device->contiguousBase = gcvNULL;
++ device->contiguousPhysical = gcvNULL;
++ }
++
++ if (device->contiguousSize <= (4 << 20))
++ {
++ device->contiguousSize = 0;
++ }
++ else
++ {
++ device->contiguousSize -= (4 << 20);
++ }
++ }
++ }
++ else
++ {
++ /* Create the contiguous memory heap. */
++ status = gckVIDMEM_Construct(
++ device->os,
++ ContiguousBase | device->systemMemoryBaseAddress,
++ ContiguousSize,
++ 64, BankSize,
++ &device->contiguousVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable contiguous memory pool. */
++ device->contiguousVidMem = gcvNULL;
++ device->contiguousSize = 0;
++ }
++ else
++ {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++ mem_region = request_mem_region(
++ ContiguousBase, ContiguousSize, "galcore managed memory"
++ );
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ ContiguousSize, ContiguousBase
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#endif
++
++ device->requestedContiguousBase = ContiguousBase;
++ device->requestedContiguousSize = ContiguousSize;
++
++#if !gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ if (gcmIS_CORE_PRESENT(device, gcvCORE_VG))
++ {
++ device->contiguousBase
++#if gcdPAGED_MEMORY_CACHEABLE
++ = (gctPOINTER) ioremap_cached(ContiguousBase, ContiguousSize);
++#else
++ = (gctPOINTER) ioremap_nocache(ContiguousBase, ContiguousSize);
++#endif
++ if (device->contiguousBase == gcvNULL)
++ {
++ device->contiguousVidMem = gcvNULL;
++ device->contiguousSize = 0;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++#endif
++
++ device->contiguousPhysical = gcvNULL;
++ device->contiguousPhysicalName = 0;
++ device->contiguousSize = ContiguousSize;
++ device->contiguousMapped = gcvTRUE;
++ }
++ }
++ }
++
++ /* Return pointer to the device. */
++ * Device = device;
++
++ gcmkFOOTER_ARG("*Device=0x%x", * Device);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Destroy
++**
++** Class destructor.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Destroy(
++ gckGALDEVICE Device)
++{
++ gctINT i;
++ gceSTATUS status = gcvSTATUS_OK;
++ gckKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ if (Device != gcvNULL)
++ {
++ /* Grab the first availiable kernel */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->irqLines[i] != -1)
++ {
++ kernel = Device->kernels[i];
++ break;
++ }
++ }
++ if (Device->internalPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->internalPhysicalName);
++ Device->internalPhysicalName = 0;
++ }
++ if (Device->externalPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->externalPhysicalName);
++ Device->externalPhysicalName = 0;
++ }
++ if (Device->contiguousPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->contiguousPhysicalName);
++ Device->contiguousPhysicalName = 0;
++ }
++
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->kernels[i] != gcvNULL)
++ {
++ /* Destroy the gckKERNEL object. */
++ gcmkVERIFY_OK(gckKERNEL_Destroy(Device->kernels[i]));
++ Device->kernels[i] = gcvNULL;
++ }
++ }
++
++ {
++ if (Device->internalLogical != gcvNULL)
++ {
++ /* Unmap the internal memory. */
++ iounmap(Device->internalLogical);
++ Device->internalLogical = gcvNULL;
++ }
++
++ if (Device->internalVidMem != gcvNULL)
++ {
++ /* Destroy the internal heap. */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->internalVidMem));
++ Device->internalVidMem = gcvNULL;
++ }
++ }
++
++ {
++ if (Device->externalLogical != gcvNULL)
++ {
++ /* Unmap the external memory. */
++ iounmap(Device->externalLogical);
++ Device->externalLogical = gcvNULL;
++ }
++
++ if (Device->externalVidMem != gcvNULL)
++ {
++ /* destroy the external heap */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->externalVidMem));
++ Device->externalVidMem = gcvNULL;
++ }
++ }
++
++ {
++ if (Device->contiguousBase != gcvNULL)
++ {
++ if (Device->contiguousMapped)
++ {
++#if !gcdDYNAMIC_MAP_RESERVED_MEMORY && gcdENABLE_VG
++ if (Device->contiguousBase)
++ {
++ /* Unmap the contiguous memory. */
++ iounmap(Device->contiguousBase);
++ }
++#endif
++ }
++ else
++ {
++ gcmkONERROR(_FreeMemory(
++ Device,
++ Device->contiguousBase,
++ Device->contiguousPhysical
++ ));
++ }
++
++ Device->contiguousBase = gcvNULL;
++ Device->contiguousPhysical = gcvNULL;
++ }
++
++ if (Device->requestedContiguousBase != 0)
++ {
++ release_mem_region(Device->requestedContiguousBase, Device->requestedContiguousSize);
++ Device->requestedContiguousBase = 0;
++ Device->requestedContiguousSize = 0;
++ }
++
++ if (Device->contiguousVidMem != gcvNULL)
++ {
++ /* Destroy the contiguous heap. */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->contiguousVidMem));
++ Device->contiguousVidMem = gcvNULL;
++ }
++ }
++
++ {
++ if(gckDebugFileSystemIsEnabled())
++ {
++ gckDebugFileSystemFreeNode(Device->dbgnode);
++ kfree(Device->dbgnode);
++ Device->dbgnode = gcvNULL;
++ }
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->registerBases[i] != gcvNULL)
++ {
++ /* Unmap register memory. */
++ iounmap(Device->registerBases[i]);
++ if (Device->requestedRegisterMemBases[i] != 0)
++ {
++ release_mem_region(Device->requestedRegisterMemBases[i], Device->requestedRegisterMemSizes[i]);
++ }
++
++ Device->registerBases[i] = gcvNULL;
++ Device->requestedRegisterMemBases[i] = 0;
++ Device->requestedRegisterMemSizes[i] = 0;
++ }
++ }
++
++ /*Disable clock*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ if (Device->clk_3d_axi) {
++ clk_put(Device->clk_3d_axi);
++ Device->clk_3d_axi = NULL;
++ }
++#endif
++ if (Device->clk_3d_core) {
++ clk_put(Device->clk_3d_core);
++ Device->clk_3d_core = NULL;
++ }
++ if (Device->clk_3d_shader) {
++ clk_put(Device->clk_3d_shader);
++ Device->clk_3d_shader = NULL;
++ }
++ if (Device->clk_2d_core) {
++ clk_put(Device->clk_2d_core);
++ Device->clk_2d_core = NULL;
++ }
++ if (Device->clk_2d_axi) {
++ clk_put(Device->clk_2d_axi);
++ Device->clk_2d_axi = NULL;
++ }
++ if (Device->clk_vg_axi) {
++ clk_put(Device->clk_vg_axi);
++ Device->clk_vg_axi = NULL;
++ }
++
++#ifdef CONFIG_PM
++ if(Device->pmdev)
++ pm_runtime_disable(Device->pmdev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (Device->gpu_regulator) {
++ regulator_put(Device->gpu_regulator);
++ Device->gpu_regulator = NULL;
++ }
++#endif
++
++ /* Destroy the gckOS object. */
++ if (Device->os != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Destroy(Device->os));
++ Device->os = gcvNULL;
++ }
++
++ /* Free the device. */
++ kfree(Device);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,172 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_device_h_
++#define __gc_hal_kernel_device_h_
++
++/******************************************************************************\
++******************************* gckGALDEVICE Structure *******************************
++\******************************************************************************/
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++struct contiguous_mem_pool {
++ struct dma_attrs attrs;
++ dma_addr_t phys;
++ void *virt;
++ size_t size;
++};
++#endif
++
++typedef struct _gckGALDEVICE
++{
++ /* Objects. */
++ gckOS os;
++ gckKERNEL kernels[gcdMAX_GPU_COUNT];
++
++ /* Attributes. */
++ gctSIZE_T internalSize;
++ gctPHYS_ADDR internalPhysical;
++ gctUINT32 internalPhysicalName;
++ gctPOINTER internalLogical;
++ gckVIDMEM internalVidMem;
++ gctSIZE_T externalSize;
++ gctPHYS_ADDR externalPhysical;
++ gctUINT32 externalPhysicalName;
++ gctPOINTER externalLogical;
++ gckVIDMEM externalVidMem;
++ gckVIDMEM contiguousVidMem;
++ gctPOINTER contiguousBase;
++ gctPHYS_ADDR contiguousPhysical;
++ gctUINT32 contiguousPhysicalName;
++ gctSIZE_T contiguousSize;
++ gctBOOL contiguousMapped;
++ gctPOINTER contiguousMappedUser;
++ gctSIZE_T systemMemorySize;
++ gctUINT32 systemMemoryBaseAddress;
++ gctPOINTER registerBases[gcdMAX_GPU_COUNT];
++ gctSIZE_T registerSizes[gcdMAX_GPU_COUNT];
++ gctUINT32 baseAddress;
++ gctUINT32 requestedRegisterMemBases[gcdMAX_GPU_COUNT];
++ gctSIZE_T requestedRegisterMemSizes[gcdMAX_GPU_COUNT];
++ gctUINT32 requestedContiguousBase;
++ gctSIZE_T requestedContiguousSize;
++
++ /* IRQ management. */
++ gctINT irqLines[gcdMAX_GPU_COUNT];
++ gctBOOL isrInitializeds[gcdMAX_GPU_COUNT];
++ gctINT isrEnabled[gcdMAX_GPU_COUNT];
++ gctBOOL dataReadys[gcdMAX_GPU_COUNT];
++
++ /* Thread management. */
++ struct task_struct *threadCtxts[gcdMAX_GPU_COUNT];
++ struct semaphore semas[gcdMAX_GPU_COUNT];
++ gctBOOL threadInitializeds[gcdMAX_GPU_COUNT];
++ gctBOOL killThread;
++
++ /* Signal management. */
++ gctINT signal;
++
++ /* Core mapping */
++ gceCORE coreMapping[8];
++
++ /* States before suspend. */
++ gceCHIPPOWERSTATE statesStored[gcdMAX_GPU_COUNT];
++
++ /*Device Debug File System Entry in Kernel*/
++ struct _gcsDebugFileSystemNode * dbgnode;
++
++ /* Clock management.*/
++ struct clk *clk_3d_core;
++ struct clk *clk_3d_shader;
++ struct clk *clk_3d_axi;
++ struct clk *clk_2d_core;
++ struct clk *clk_2d_axi;
++ struct clk *clk_vg_axi;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ /*Power management.*/
++ struct regulator *gpu_regulator;
++#endif
++ /*Run time pm*/
++ struct device *pmdev;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct contiguous_mem_pool *pool;
++ struct reset_control *rstc[gcdMAX_GPU_COUNT];
++#endif
++}
++* gckGALDEVICE;
++
++typedef struct _gcsHAL_PRIVATE_DATA
++{
++ gckGALDEVICE device;
++ gctPOINTER mappedMemory;
++ gctPOINTER contiguousLogical;
++ /* The process opening the device may not be the same as the one that closes it. */
++ gctUINT32 pidOpen;
++}
++gcsHAL_PRIVATE_DATA, * gcsHAL_PRIVATE_DATA_PTR;
++
++gceSTATUS gckGALDEVICE_Start_Threads(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Stop_Threads(
++ gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Start(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Stop(
++ gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Construct(
++ IN gctINT IrqLine,
++ IN gctUINT32 RegisterMemBase,
++ IN gctSIZE_T RegisterMemSize,
++ IN gctINT IrqLine2D,
++ IN gctUINT32 RegisterMemBase2D,
++ IN gctSIZE_T RegisterMemSize2D,
++ IN gctINT IrqLineVG,
++ IN gctUINT32 RegisterMemBaseVG,
++ IN gctSIZE_T RegisterMemSizeVG,
++ IN gctUINT32 ContiguousBase,
++ IN gctSIZE_T ContiguousSize,
++ IN gctSIZE_T BankSize,
++ IN gctINT FastClear,
++ IN gctINT Compression,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize,
++ IN gctINT Signal,
++ IN gctUINT LogFileSize,
++ IN struct device *pdev,
++ IN gctINT PowerManagement,
++ IN gctINT GpuProfiler,
++ OUT gckGALDEVICE *Device
++ );
++
++gceSTATUS gckGALDEVICE_Destroy(
++ IN gckGALDEVICE Device
++ );
++
++#endif /* __gc_hal_kernel_device_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,1472 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/notifier.h>
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_driver.h"
++
++#if USE_PLATFORM_DRIVER
++# include <linux/platform_device.h>
++#endif
++
++#ifdef CONFIG_PXA_DVFM
++# include <mach/dvfm.h>
++# include <mach/pxa3xx_dvfm.h>
++#endif
++
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++# include <linux/resmem_account.h>
++# include <linux/kernel.h>
++# include <linux/mm.h>
++# include <linux/oom.h>
++# include <linux/sched.h>
++# include <linux/notifier.h>
++
++struct task_struct *lowmem_deathpending;
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data);
++
++static struct notifier_block task_nb = {
++ .notifier_call = task_notify_func,
++};
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data)
++{
++ struct task_struct *task = data;
++
++ if (task == lowmem_deathpending)
++ lowmem_deathpending = NULL;
++
++ return NOTIFY_OK;
++}
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++#include <mach/viv_gpu.h>
++#else
++#include <linux/pm_runtime.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
++#include <mach/busfreq.h>
++#else
++#include <linux/busfreq-imx6.h>
++#include <linux/reset.h>
++#endif
++#endif
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_DRIVER
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++#include <linux/device_cooling.h>
++#define REG_THERMAL_NOTIFIER(a) register_devfreq_cooling_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_devfreq_cooling_notifier(a);
++#else
++extern int register_thermal_notifier(struct notifier_block *nb);
++extern int unregister_thermal_notifier(struct notifier_block *nb);
++#define REG_THERMAL_NOTIFIER(a) register_thermal_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_thermal_notifier(a);
++#endif
++#endif
++
++MODULE_DESCRIPTION("Vivante Graphics Driver");
++MODULE_LICENSE("GPL");
++
++static struct class* gpuClass;
++
++static gckGALDEVICE galDevice;
++
++static uint major = 199;
++module_param(major, uint, 0644);
++
++static int irqLine = -1;
++module_param(irqLine, int, 0644);
++
++static ulong registerMemBase = 0x80000000;
++module_param(registerMemBase, ulong, 0644);
++
++static ulong registerMemSize = 2 << 10;
++module_param(registerMemSize, ulong, 0644);
++
++static int irqLine2D = -1;
++module_param(irqLine2D, int, 0644);
++
++static ulong registerMemBase2D = 0x00000000;
++module_param(registerMemBase2D, ulong, 0644);
++
++static ulong registerMemSize2D = 2 << 10;
++module_param(registerMemSize2D, ulong, 0644);
++
++static int irqLineVG = -1;
++module_param(irqLineVG, int, 0644);
++
++static ulong registerMemBaseVG = 0x00000000;
++module_param(registerMemBaseVG, ulong, 0644);
++
++static ulong registerMemSizeVG = 2 << 10;
++module_param(registerMemSizeVG, ulong, 0644);
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++static ulong contiguousSize = 128 << 20;
++#else
++static ulong contiguousSize = 4 << 20;
++#endif
++module_param(contiguousSize, ulong, 0644);
++
++static ulong contiguousBase = 0;
++module_param(contiguousBase, ulong, 0644);
++
++static ulong bankSize = 0;
++module_param(bankSize, ulong, 0644);
++
++static int fastClear = -1;
++module_param(fastClear, int, 0644);
++
++static int compression = -1;
++module_param(compression, int, 0644);
++
++static int powerManagement = 1;
++module_param(powerManagement, int, 0644);
++
++static int gpuProfiler = 0;
++module_param(gpuProfiler, int, 0644);
++
++static int signal = 48;
++module_param(signal, int, 0644);
++
++static ulong baseAddress = 0;
++module_param(baseAddress, ulong, 0644);
++
++static ulong physSize = 0;
++module_param(physSize, ulong, 0644);
++
++static uint logFileSize=0;
++module_param(logFileSize,uint, 0644);
++
++static int showArgs = 0;
++module_param(showArgs, int, 0644);
++
++int gpu3DMinClock = 0;
++module_param(gpu3DMinClock, int, 0644);
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER
++ unsigned long coreClock = 156000000;
++ module_param(coreClock, ulong, 0644);
++#endif
++
++static int drv_open(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static int drv_release(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ );
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ );
++
++static struct file_operations driver_fops =
++{
++ .owner = THIS_MODULE,
++ .open = drv_open,
++ .release = drv_release,
++ .unlocked_ioctl = drv_ioctl,
++#ifdef HAVE_COMPAT_IOCTL
++ .compat_ioctl = drv_ioctl,
++#endif
++ .mmap = drv_mmap,
++};
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++static size_t viv_gpu_resmem_query(struct task_struct *p, struct reserved_memory_account *m);
++static struct reserved_memory_account viv_gpu_resmem_handler = {
++ .name = "viv_gpu",
++ .get_page_used_by_process = viv_gpu_resmem_query,
++};
++
++size_t viv_gpu_resmem_query(struct task_struct *p, struct reserved_memory_account *m)
++{
++ gcuDATABASE_INFO info;
++ unsigned int processid = p->pid;
++ gckKERNEL gpukernel = m->data;
++
++ /* ignore error happens in this api. */
++ if (gckKERNEL_QueryProcessDB(gpukernel, processid, false, gcvDB_VIDEO_MEMORY, &info) != gcvSTATUS_OK)
++ return 0;
++
++ /* we return pages. */
++ if (info.counters.bytes > 0)
++ return info.counters.bytes / PAGE_SIZE;
++ return 0;
++}
++#endif
++
++int drv_open(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gctBOOL attached = gcvFALSE;
++ gcsHAL_PRIVATE_DATA_PTR data = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = kmalloc(sizeof(gcsHAL_PRIVATE_DATA), GFP_KERNEL);
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ data->device = galDevice;
++ data->mappedMemory = gcvNULL;
++ data->contiguousLogical = gcvNULL;
++ gcmkONERROR(gckOS_GetProcessID(&data->pidOpen));
++
++ /* Attached the process. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvTRUE));
++ }
++ }
++ attached = gcvTRUE;
++
++ if (!galDevice->contiguousMapped)
++ {
++ gcmkONERROR(gckOS_MapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ &data->contiguousLogical
++ ));
++ }
++
++ filp->private_data = data;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ if (data != gcvNULL)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical
++ ));
++ }
++
++ kfree(data);
++ }
++
++ if (attached)
++ {
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvFALSE));
++ }
++ }
++ }
++
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++int drv_release(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (!device->contiguousMapped)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkONERROR(gckOS_UnmapMemoryEx(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical,
++ data->pidOpen
++ ));
++
++ data->contiguousLogical = gcvNULL;
++ }
++ }
++
++ /* A process gets detached. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcessEx(galDevice->kernels[i], gcvFALSE, data->pidOpen));
++ }
++ }
++
++ kfree(data);
++ filp->private_data = NULL;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gctUINT32 copyLen;
++ DRIVER_ARGS drvArgs;
++ gckGALDEVICE device;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gctINT32 i, count;
++
++ gcmkHEADER_ARG(
++ "filp=0x%08X ioctlCode=0x%08X arg=0x%08X",
++ filp, ioctlCode, arg
++ );
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if ((ioctlCode != IOCTL_GCHAL_INTERFACE)
++ && (ioctlCode != IOCTL_GCHAL_KERNEL_INTERFACE)
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown command %d\n",
++ __FUNCTION__, __LINE__,
++ ioctlCode
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Get the drvArgs. */
++ copyLen = copy_from_user(
++ &drvArgs, (void *) arg, sizeof(DRIVER_ARGS)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of the input arguments.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Now bring in the gcsHAL_INTERFACE structure. */
++ if ((drvArgs.InputBufferSize != sizeof(gcsHAL_INTERFACE))
++ || (drvArgs.OutputBufferSize != sizeof(gcsHAL_INTERFACE))
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): input or/and output structures are invalid.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ copyLen = copy_from_user(
++ &iface, gcmUINT64_TO_PTR(drvArgs.InputBuffer), sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of input HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (iface.command == gcvHAL_CHIP_INFO)
++ {
++ count = 0;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ iface.u.ChipInfo.types[count] = gcvHARDWARE_VG;
++ }
++ else
++#endif
++ {
++ gcmkVERIFY_OK(gckHARDWARE_GetType(device->kernels[i]->hardware,
++ &iface.u.ChipInfo.types[count]));
++ }
++ count++;
++ }
++ }
++
++ iface.u.ChipInfo.count = count;
++ iface.status = status = gcvSTATUS_OK;
++ }
++ else
++ {
++ if (iface.hardwareType < 0 || iface.hardwareType > 7)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown hardwareType %d\n",
++ __FUNCTION__, __LINE__,
++ iface.hardwareType
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (device->coreMapping[iface.hardwareType] == gcvCORE_VG)
++ {
++ status = gckVGKERNEL_Dispatch(device->kernels[gcvCORE_VG],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ else
++#endif
++ {
++ status = gckKERNEL_Dispatch(device->kernels[device->coreMapping[iface.hardwareType]],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ }
++
++ /* Redo system call after pending signal is handled. */
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkFOOTER();
++ return -ERESTARTSYS;
++ }
++
++ if (gcmIS_SUCCESS(status) && (iface.command == gcvHAL_LOCK_VIDEO_MEMORY))
++ {
++ gcuVIDMEM_NODE_PTR node = gcmUINT64_TO_PTR(iface.u.LockVideoMemory.node);
++ /* Special case for mapped memory. */
++ if ((data->mappedMemory != gcvNULL)
++ && (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ )
++ {
++ /* Compute offset into mapped memory. */
++ gctUINT32 offset
++ = (gctUINT8 *) gcmUINT64_TO_PTR(iface.u.LockVideoMemory.memory)
++ - (gctUINT8 *) device->contiguousBase;
++
++ /* Compute offset into user-mapped region. */
++ iface.u.LockVideoMemory.memory =
++ gcmPTR_TO_UINT64((gctUINT8 *) data->mappedMemory + offset);
++ }
++ }
++
++ /* Copy data back to the user. */
++ copyLen = copy_to_user(
++ gcmUINT64_TO_PTR(drvArgs.OutputBuffer), &iface, sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of output HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("filp=0x%08X vma=0x%08X", filp, vma);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if !gcdPAGED_MEMORY_CACHEABLE
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++ vma->vm_flags |= gcdVM_FLAGS;
++#endif
++ vma->vm_pgoff = 0;
++
++ if (device->contiguousMapped)
++ {
++ unsigned long size = vma->vm_end - vma->vm_start;
++ int ret = 0;
++
++ if (size > device->contiguousSize)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Invalid mapping size.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ ret = io_remap_pfn_range(
++ vma,
++ vma->vm_start,
++ device->requestedContiguousBase >> PAGE_SHIFT,
++ size,
++ vma->vm_page_prot
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): io_remap_pfn_range failed %d\n",
++ __FUNCTION__, __LINE__,
++ ret
++ );
++
++ data->mappedMemory = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ data->mappedMemory = (gctPOINTER) vma->vm_start;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++ }
++
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++
++#if !USE_PLATFORM_DRIVER
++static int __init drv_init(void)
++#else
++static int drv_init(struct device *pdev)
++#endif
++{
++ int ret;
++ int result = -EINVAL;
++ gceSTATUS status;
++ gckGALDEVICE device = gcvNULL;
++ struct class* device_class = gcvNULL;
++
++ gcmkHEADER();
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28))
++ {
++# if 0
++ struct clk * clk;
++
++ clk = clk_get(NULL, "GCCLK");
++
++ if (IS_ERR(clk))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): clk get error: %d\n",
++ __FUNCTION__, __LINE__,
++ PTR_ERR(clk)
++ );
++
++ result = -ENODEV;
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /*
++ * APMU_GC_156M, APMU_GC_312M, APMU_GC_PLL2, APMU_GC_PLL2_DIV2 currently.
++ * Use the 2X clock.
++ */
++ if (clk_set_rate(clk, coreClock * 2))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to set core clock.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ result = -EAGAIN;
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ clk_enable(clk);
++
++#if defined(CONFIG_PXA_DVFM) && (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29))
++ gc_pwr(1);
++# endif
++# endif
++ }
++#endif
++
++ printk(KERN_INFO "Galcore version %d.%d.%d.%d\n",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD);
++ /* when enable gpu profiler, we need to turn off gpu powerMangement */
++ if(gpuProfiler)
++ powerManagement = 0;
++ if (showArgs)
++ {
++ printk("galcore options:\n");
++ printk(" irqLine = %d\n", irqLine);
++ printk(" registerMemBase = 0x%08lX\n", registerMemBase);
++ printk(" registerMemSize = 0x%08lX\n", registerMemSize);
++
++ if (irqLine2D != -1)
++ {
++ printk(" irqLine2D = %d\n", irqLine2D);
++ printk(" registerMemBase2D = 0x%08lX\n", registerMemBase2D);
++ printk(" registerMemSize2D = 0x%08lX\n", registerMemSize2D);
++ }
++
++ if (irqLineVG != -1)
++ {
++ printk(" irqLineVG = %d\n", irqLineVG);
++ printk(" registerMemBaseVG = 0x%08lX\n", registerMemBaseVG);
++ printk(" registerMemSizeVG = 0x%08lX\n", registerMemSizeVG);
++ }
++
++ printk(" contiguousSize = %ld\n", contiguousSize);
++ printk(" contiguousBase = 0x%08lX\n", contiguousBase);
++ printk(" bankSize = 0x%08lX\n", bankSize);
++ printk(" fastClear = %d\n", fastClear);
++ printk(" compression = %d\n", compression);
++ printk(" signal = %d\n", signal);
++ printk(" baseAddress = 0x%08lX\n", baseAddress);
++ printk(" physSize = 0x%08lX\n", physSize);
++ printk(" logFileSize = %d KB \n", logFileSize);
++ printk(" powerManagement = %d\n", powerManagement);
++ printk(" gpuProfiler = %d\n", gpuProfiler);
++#if ENABLE_GPU_CLOCK_BY_DRIVER
++ printk(" coreClock = %lu\n", coreClock);
++#endif
++ }
++
++ if(logFileSize != 0)
++ {
++ gckDebugFileSystemInitialize();
++ }
++
++ /* Create the GAL device. */
++ gcmkONERROR(gckGALDEVICE_Construct(
++ irqLine,
++ registerMemBase, registerMemSize,
++ irqLine2D,
++ registerMemBase2D, registerMemSize2D,
++ irqLineVG,
++ registerMemBaseVG, registerMemSizeVG,
++ contiguousBase, contiguousSize,
++ bankSize, fastClear, compression, baseAddress, physSize, signal,
++ logFileSize,
++ pdev,
++ powerManagement,
++ gpuProfiler,
++ &device
++ ));
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ device->pool = dev_get_drvdata(pdev);
++#endif
++
++ /* Start the GAL device. */
++ gcmkONERROR(gckGALDEVICE_Start(device));
++
++ if ((physSize != 0)
++ && (device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ && (device->kernels[gcvCORE_MAJOR]->hardware->mmuVersion != 0))
++ {
++ status = gckMMU_Enable(device->kernels[gcvCORE_MAJOR]->mmu, baseAddress, physSize);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Enable new MMU: status=%d\n", status);
++
++ if ((device->kernels[gcvCORE_2D] != gcvNULL)
++ && (device->kernels[gcvCORE_2D]->hardware->mmuVersion != 0))
++ {
++ status = gckMMU_Enable(device->kernels[gcvCORE_2D]->mmu, baseAddress, physSize);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Enable new MMU for 2D: status=%d\n", status);
++ }
++
++ /* Reset the base address */
++ device->baseAddress = 0;
++ }
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++ task_free_register(&task_nb);
++ viv_gpu_resmem_handler.data = device->kernels[gcvCORE_MAJOR];
++ register_reserved_memory_account(&viv_gpu_resmem_handler);
++#endif
++
++
++ /* Register the character device. */
++ ret = register_chrdev(major, DRV_NAME, &driver_fops);
++
++ if (ret < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not allocate major number for mmap.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (major == 0)
++ {
++ major = ret;
++ }
++
++ /* Create the device class. */
++ device_class = class_create(THIS_MODULE, "graphics_class");
++
++ if (IS_ERR(device_class))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the class.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
++ device_create(device_class, NULL, MKDEV(major, 0), NULL, "galcore");
++#else
++ device_create(device_class, NULL, MKDEV(major, 0), "galcore");
++#endif
++
++ galDevice = device;
++ gpuClass = device_class;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "%s(%d): irqLine=%d, contiguousSize=%lu, memBase=0x%lX\n",
++ __FUNCTION__, __LINE__,
++ irqLine, contiguousSize, registerMemBase
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ /* Roll back. */
++ if (device_class != gcvNULL)
++ {
++ device_destroy(device_class, MKDEV(major, 0));
++ class_destroy(device_class);
++ }
++
++ if (device != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(device));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++ }
++
++ gcmkFOOTER();
++ return result;
++}
++
++#if !USE_PLATFORM_DRIVER
++static void __exit drv_exit(void)
++#else
++static void drv_exit(void)
++#endif
++{
++ gcmkHEADER();
++
++#ifdef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++ task_free_unregister(&task_nb);
++ unregister_reserved_memory_account(&viv_gpu_resmem_handler);
++#endif
++
++ gcmkASSERT(gpuClass != gcvNULL);
++ device_destroy(gpuClass, MKDEV(major, 0));
++ class_destroy(gpuClass);
++
++ unregister_chrdev(major, DRV_NAME);
++
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(galDevice));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(galDevice));
++
++ if(gckDebugFileSystemIsEnabled())
++ {
++ gckDebugFileSystemTerminate();
++ }
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
++ {
++# if 0
++ struct clk * clk = NULL;
++
++#if defined(CONFIG_PXA_DVFM) && (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,29))
++ gc_pwr(0);
++#endif
++ clk = clk_get(NULL, "GCCLK");
++ clk_disable(clk);
++# endif
++ }
++#endif
++
++ gcmkFOOTER_NO();
++}
++
++#if !USE_PLATFORM_DRIVER
++ module_init(drv_init);
++ module_exit(drv_exit);
++#else
++
++#ifdef CONFIG_DOVE_GPU
++# define DEVICE_NAME "dove_gpu"
++#else
++# define DEVICE_NAME "galcore"
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++static int thermal_hot_pm_notify(struct notifier_block *nb, unsigned long event,
++ void *dummy)
++{
++ static gctUINT orgFscale, minFscale, maxFscale;
++ static gctBOOL bAlreadyTooHot = gcvFALSE;
++ gckHARDWARE hardware = galDevice->kernels[gcvCORE_MAJOR]->hardware;
++
++ if (event && !bAlreadyTooHot) {
++ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale);
++ gckHARDWARE_SetFscaleValue(hardware, minFscale);
++ bAlreadyTooHot = gcvTRUE;
++ gckOS_Print("System is too hot. GPU3D will work at %d/64 clock.\n", minFscale);
++ } else if (!event && bAlreadyTooHot) {
++ gckHARDWARE_SetFscaleValue(hardware, orgFscale);
++ gckOS_Print("Hot alarm is canceled. GPU3D clock will return to %d/64\n", orgFscale);
++ bAlreadyTooHot = gcvFALSE;
++ }
++ return NOTIFY_OK;
++}
++
++static struct notifier_block thermal_hot_pm_notifier = {
++ .notifier_call = thermal_hot_pm_notify,
++ };
++#endif
++
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++static int gpu_probe(struct platform_device *pdev)
++#else
++static int __devinit gpu_probe(struct platform_device *pdev)
++#endif
++{
++ int ret = -ENODEV;
++ struct resource* res;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct contiguous_mem_pool *pool;
++ struct reset_control *rstc;
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct device_node *dn =pdev->dev.of_node;
++ const u32 *prop;
++#else
++ struct viv_gpu_platform_data *pdata;
++#endif
++ gcmkHEADER();
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phys_baseaddr");
++ if (res)
++ baseAddress = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_3d");
++ if (res)
++ irqLine = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_3d");
++ if (res)
++ {
++ registerMemBase = res->start;
++ registerMemSize = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_2d");
++ if (res)
++ irqLine2D = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_2d");
++ if (res)
++ {
++ registerMemBase2D = res->start;
++ registerMemSize2D = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_vg");
++ if (res)
++ irqLineVG = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_vg");
++ if (res)
++ {
++ registerMemBaseVG = res->start;
++ registerMemSizeVG = res->end - res->start + 1;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ pool = devm_kzalloc(&pdev->dev, sizeof(*pool), GFP_KERNEL);
++ if (!pool)
++ return -ENOMEM;
++ pool->size = contiguousSize;
++ init_dma_attrs(&pool->attrs);
++ dma_set_attr(DMA_ATTR_WRITE_COMBINE, &pool->attrs);
++ pool->virt = dma_alloc_attrs(&pdev->dev, pool->size, &pool->phys,
++ GFP_KERNEL, &pool->attrs);
++ if (!pool->virt) {
++ dev_err(&pdev->dev, "Failed to allocate contiguous memory\n");
++ return -ENOMEM;
++ }
++ contiguousBase = pool->phys;
++ dev_set_drvdata(&pdev->dev, pool);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ prop = of_get_property(dn, "contiguousbase", NULL);
++ if(prop)
++ contiguousBase = *prop;
++ of_property_read_u32(dn,"contiguoussize", (u32 *)&contiguousSize);
++#else
++ pdata = pdev->dev.platform_data;
++ if (pdata) {
++ contiguousBase = pdata->reserved_mem_base;
++ contiguousSize = pdata->reserved_mem_size;
++ }
++#endif
++ if (contiguousSize == 0)
++ gckOS_Print("Warning: No contiguous memory is reserverd for gpu.!\n ");
++ ret = drv_init(&pdev->dev);
++
++ if (!ret)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ rstc = devm_reset_control_get(&pdev->dev, "gpu3d");
++ galDevice->rstc[gcvCORE_MAJOR] = IS_ERR(rstc) ? NULL : rstc;
++
++ rstc = devm_reset_control_get(&pdev->dev, "gpu2d");
++ galDevice->rstc[gcvCORE_2D] = IS_ERR(rstc) ? NULL : rstc;
++
++ rstc = devm_reset_control_get(&pdev->dev, "gpuvg");
++ galDevice->rstc[gcvCORE_VG] = IS_ERR(rstc) ? NULL : rstc;
++#endif
++ platform_set_drvdata(pdev, galDevice);
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if (galDevice->kernels[gcvCORE_MAJOR])
++ REG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++#endif
++ gcmkFOOTER_NO();
++ return ret;
++ }
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++#endif
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ dma_free_attrs(&pdev->dev, pool->size, pool->virt, pool->phys,
++ &pool->attrs);
++#endif
++ gcmkFOOTER_ARG(KERN_INFO "Failed to register gpu driver: %d\n", ret);
++ return ret;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++static int gpu_remove(struct platform_device *pdev)
++#else
++static int __devexit gpu_remove(struct platform_device *pdev)
++#endif
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ gckGALDEVICE device = platform_get_drvdata(pdev);
++ struct contiguous_mem_pool *pool = device->pool;
++#endif
++ gcmkHEADER();
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if(galDevice->kernels[gcvCORE_MAJOR])
++ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++#endif
++ drv_exit();
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ dma_free_attrs(&pdev->dev, pool->size, pool->virt, pool->phys,
++ &pool->attrs);
++#endif
++ gcmkFOOTER_NO();
++ return 0;
++}
++
++static int gpu_suspend(struct platform_device *dev, pm_message_t state)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++
++ device = platform_get_drvdata(dev);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++ /* Store states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_QueryPowerManagementState(device->kernels[i]->vg->hardware, &device->statesStored[i]);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_QueryPowerManagementState(device->kernels[i]->hardware, &device->statesStored[i]);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_OFF);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_OFF);
++ }
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ }
++ }
++
++ return 0;
++}
++
++static int gpu_resume(struct platform_device *dev)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++ gceCHIPPOWERSTATE statesStored;
++
++ device = platform_get_drvdata(dev);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_ON);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_ON);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ /* Convert global state to crossponding internal state. */
++ switch(device->statesStored[i])
++ {
++ case gcvPOWER_OFF:
++ statesStored = gcvPOWER_OFF_BROADCAST;
++ break;
++ case gcvPOWER_IDLE:
++ statesStored = gcvPOWER_IDLE_BROADCAST;
++ break;
++ case gcvPOWER_SUSPEND:
++ statesStored = gcvPOWER_SUSPEND_BROADCAST;
++ break;
++ case gcvPOWER_ON:
++ statesStored = gcvPOWER_ON_AUTO;
++ break;
++ default:
++ statesStored = device->statesStored[i];
++ break;
++ }
++
++ /* Restore states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, statesStored);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, statesStored);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++ }
++ }
++
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++static const struct of_device_id mxs_gpu_dt_ids[] = {
++ { .compatible = "fsl,imx6q-gpu", },
++ {/* sentinel */}
++};
++MODULE_DEVICE_TABLE(of, mxs_gpu_dt_ids);
++
++#ifdef CONFIG_PM
++static int gpu_runtime_suspend(struct device *dev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 7)
++ release_bus_freq(BUS_FREQ_HIGH);
++#endif
++ return 0;
++}
++
++static int gpu_runtime_resume(struct device *dev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 7)
++ request_bus_freq(BUS_FREQ_HIGH);
++#endif
++ return 0;
++}
++
++static int gpu_system_suspend(struct device *dev)
++{
++ pm_message_t state={0};
++ return gpu_suspend(to_platform_device(dev), state);
++}
++
++static int gpu_system_resume(struct device *dev)
++{
++ return gpu_resume(to_platform_device(dev));
++}
++
++static const struct dev_pm_ops gpu_pm_ops = {
++ SET_RUNTIME_PM_OPS(gpu_runtime_suspend, gpu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(gpu_system_suspend, gpu_system_resume)
++};
++#endif
++#endif
++
++static struct platform_driver gpu_driver = {
++ .probe = gpu_probe,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++ .remove = gpu_remove,
++#else
++ .remove = __devexit_p(gpu_remove),
++#endif
++
++ .suspend = gpu_suspend,
++ .resume = gpu_resume,
++
++ .driver = {
++ .name = DEVICE_NAME,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ .of_match_table = mxs_gpu_dt_ids,
++#if CONFIG_PM
++ .pm = &gpu_pm_ops,
++#endif
++#endif
++ }
++};
++
++#if 0 /*CONFIG_DOVE_GPU*/
++static struct resource gpu_resources[] = {
++ {
++ .name = "gpu_irq",
++ .flags = IORESOURCE_IRQ,
++ },
++ {
++ .name = "gpu_base",
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .name = "gpu_mem",
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++static struct platform_device * gpu_device;
++#endif
++
++static int __init gpu_init(void)
++{
++ int ret = 0;
++
++#if 0 /*ndef CONFIG_DOVE_GPU*/
++ gpu_resources[0].start = gpu_resources[0].end = irqLine;
++
++ gpu_resources[1].start = registerMemBase;
++ gpu_resources[1].end = registerMemBase + registerMemSize - 1;
++
++ gpu_resources[2].start = contiguousBase;
++ gpu_resources[2].end = contiguousBase + contiguousSize - 1;
++
++ /* Allocate device */
++ gpu_device = platform_device_alloc(DEVICE_NAME, -1);
++ if (!gpu_device)
++ {
++ printk(KERN_ERR "galcore: platform_device_alloc failed.\n");
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* Insert resource */
++ ret = platform_device_add_resources(gpu_device, gpu_resources, 3);
++ if (ret)
++ {
++ printk(KERN_ERR "galcore: platform_device_add_resources failed.\n");
++ goto put_dev;
++ }
++
++ /* Add device */
++ ret = platform_device_add(gpu_device);
++ if (ret)
++ {
++ printk(KERN_ERR "galcore: platform_device_add failed.\n");
++ goto put_dev;
++ }
++#endif
++
++ ret = platform_driver_register(&gpu_driver);
++ if (!ret)
++ {
++ goto out;
++ }
++
++#if 0 /*ndef CONFIG_DOVE_GPU*/
++ platform_device_del(gpu_device);
++put_dev:
++ platform_device_put(gpu_device);
++#endif
++
++out:
++ return ret;
++}
++
++static void __exit gpu_exit(void)
++{
++ platform_driver_unregister(&gpu_driver);
++#if 0 /*ndef CONFIG_DOVE_GPU*/
++ platform_device_unregister(gpu_device);
++#endif
++}
++
++module_init(gpu_init);
++module_exit(gpu_exit);
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,481 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_QueryVideoMemory
++**
++** Query the amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to an gcsHAL_INTERFACE structure that will be filled in with
++** the memory information.
++*/
++gceSTATUS
++gckKERNEL_QueryVideoMemory(
++ IN gckKERNEL Kernel,
++ OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("Kernel=%p", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Get internal memory size and physical address. */
++ Interface->u.QueryVideoMemory.internalSize = device->internalSize;
++ Interface->u.QueryVideoMemory.internalPhysical = device->internalPhysicalName;
++
++ /* Get external memory size and physical address. */
++ Interface->u.QueryVideoMemory.externalSize = device->externalSize;
++ Interface->u.QueryVideoMemory.externalPhysical = device->externalPhysicalName;
++
++ /* Get contiguous memory size and physical address. */
++ Interface->u.QueryVideoMemory.contiguousSize = device->contiguousSize;
++ Interface->u.QueryVideoMemory.contiguousPhysical = device->contiguousPhysicalName;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_GetVideoMemoryPool
++**
++** Get the gckVIDMEM object belonging to the specified pool.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcePOOL Pool
++** Pool to query gckVIDMEM object for.
++**
++** OUTPUT:
++**
++** gckVIDMEM * VideoMemory
++** Pointer to a variable that will hold the pointer to the gckVIDMEM
++** object belonging to the requested pool.
++*/
++gceSTATUS
++gckKERNEL_GetVideoMemoryPool(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ OUT gckVIDMEM * VideoMemory
++ )
++{
++ gckGALDEVICE device;
++ gckVIDMEM videoMemory;
++
++ gcmkHEADER_ARG("Kernel=%p Pool=%d", Kernel, Pool);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(VideoMemory != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Dispatch on pool. */
++ switch (Pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ videoMemory = device->internalVidMem;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ videoMemory = device->externalVidMem;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ videoMemory = device->contiguousVidMem;
++ break;
++
++ default:
++ /* Unknown pool. */
++ videoMemory = NULL;
++ }
++
++ /* Return pointer to the gckVIDMEM object. */
++ *VideoMemory = videoMemory;
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*VideoMemory=%p", *VideoMemory);
++ return (videoMemory == NULL) ? gcvSTATUS_OUT_OF_MEMORY : gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapMemory
++**
++** Map video memory into the current process space.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of video memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the base address of the mapped
++** memory region.
++*/
++gceSTATUS
++gckKERNEL_MapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckKERNEL kernel = Kernel;
++ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical);
++
++ return gckOS_MapMemory(Kernel->os, physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_UnmapMemory
++**
++** Unmap video memory from the current process space.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of video memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** gctPOINTER Logical
++** Base address of the mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gckKERNEL kernel = Kernel;
++ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical);
++
++ return gckOS_UnmapMemory(Kernel->os, physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapVideoMemory
++**
++** Get the logical address for a hardware specific memory address for the
++** current process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE to map the memory into the user space.
++**
++** gctUINT32 Address
++** Hardware specific memory address.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** specified memory address.
++*/
++gceSTATUS
++gckKERNEL_MapVideoMemoryEx(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckGALDEVICE device;
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++ gcePOOL pool;
++ gctUINT32 offset, base;
++ gceSTATUS status;
++ gctPOINTER logical;
++
++ gcmkHEADER_ARG("Kernel=%p InUserSpace=%d Address=%08x",
++ Kernel, InUserSpace, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Logical != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkONERROR(
++ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware, Address, &pool, &offset));
++ }
++ else
++#endif
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkONERROR(
++ gckHARDWARE_SplitMemory(Kernel->hardware, Address, &pool, &offset));
++ }
++
++ /* Dispatch on pool. */
++ switch (pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ logical = device->internalLogical;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ logical = device->externalLogical;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ if (device->contiguousMapped)
++ {
++ logical = device->contiguousBase;
++ }
++ else
++ {
++ gctINT processID;
++ gckOS_GetProcessID(&processID);
++
++ mdl = (PLINUX_MDL) device->contiguousPhysical;
++
++ mdlMap = FindMdlMap(mdl, processID);
++ gcmkASSERT(mdlMap);
++
++ logical = (gctPOINTER) mdlMap->vmaAddr;
++ }
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware,
++ device->contiguousVidMem->baseAddress,
++ &pool,
++ &base));
++ }
++ else
++#endif
++ {
++ gctUINT32 baseAddress = 0;
++
++ if (Kernel->hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++ }
++
++ gcmkVERIFY_OK(
++ gckHARDWARE_SplitMemory(Kernel->hardware,
++ device->contiguousVidMem->baseAddress - baseAddress,
++ &pool,
++ &base));
++ }
++ offset -= base;
++ break;
++
++ default:
++ /* Invalid memory pool. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Build logical address of specified address. */
++ *Logical = (gctPOINTER) ((gctUINT8_PTR) logical + offset);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=%p", *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Retunn the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapVideoMemory
++**
++** Get the logical address for a hardware specific memory address for the
++** current process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE to map the memory into the user space.
++**
++** gctUINT32 Address
++** Hardware specific memory address.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** specified memory address.
++*/
++gceSTATUS
++gckKERNEL_MapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ return gckKERNEL_MapVideoMemoryEx(Kernel, gcvCORE_MAJOR, InUserSpace, Address, Logical);
++}
++/*******************************************************************************
++**
++** gckKERNEL_Notify
++**
++** This function iscalled by clients to notify the gckKERNRL object of an event.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gceNOTIFY Notification
++** Notification event.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Notify(
++ IN gckKERNEL Kernel,
++ IN gceNOTIFY Notification,
++ IN gctBOOL Data
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=%p Notification=%d Data=%d",
++ Kernel, Notification, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Dispatch on notifcation. */
++ switch (Notification)
++ {
++ case gcvNOTIFY_INTERRUPT:
++ /* Process the interrupt. */
++#if COMMAND_PROCESSOR_VERSION > 1
++ status = gckINTERRUPT_Notify(Kernel->interrupt, Data);
++#else
++ status = gckHARDWARE_Interrupt(Kernel->hardware, Data);
++#endif
++ break;
++
++ default:
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QuerySettings(
++ IN gckKERNEL Kernel,
++ OUT gcsKERNEL_SETTINGS * Settings
++ )
++{
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("Kernel=%p", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Settings != gcvNULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Fill in signal. */
++ Settings->signal = device->signal;
++
++ /* Success. */
++ gcmkFOOTER_ARG("Settings->signal=%d", Settings->signal);
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,94 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_linux_h_
++#define __gc_hal_kernel_linux_h_
++
++#include <linux/version.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#ifdef FLAREON
++# include <asm/arch-realview/dove_gpio_irq.h>
++#endif
++#include <linux/interrupt.h>
++#include <linux/vmalloc.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++
++#ifdef MODVERSIONS
++# include <linux/modversions.h>
++#endif
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++#endif
++
++#define NTSTRSAFE_NO_CCH_FUNCTIONS
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_device.h"
++#include "gc_hal_kernel_os.h"
++#include "gc_hal_kernel_debugfs.h"
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
++#define FIND_TASK_BY_PID(x) pid_task(find_vpid(x), PIDTYPE_PID)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
++#define FIND_TASK_BY_PID(x) find_task_by_vpid(x)
++#else
++#define FIND_TASK_BY_PID(x) find_task_by_pid(x)
++#endif
++
++#define _WIDE(string) L##string
++#define WIDE(string) _WIDE(string)
++
++#define countof(a) (sizeof(a) / sizeof(a[0]))
++
++#define DRV_NAME "galcore"
++
++#define GetPageCount(size, offset) ((((size) + ((offset) & ~PAGE_CACHE_MASK)) + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,7,0)
++#define gcdVM_FLAGS (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP)
++#else
++#define gcdVM_FLAGS (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_RESERVED)
++#endif
++
++static inline gctINT
++GetOrder(
++ IN gctINT numPages
++ )
++{
++ gctINT order = 0;
++
++ while ((1 << order) < numPages) order++;
++
++ return order;
++}
++
++#endif /* __gc_hal_kernel_linux_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,32 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++gctINT
++gckMATH_ModuloInt(
++ IN gctINT X,
++ IN gctINT Y
++ )
++{
++ if(Y ==0) {return 0;}
++ else {return X % Y;}
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,9022 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mm.h>
++#include <linux/mman.h>
++#include <linux/sched.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/idr.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++#include <mach/hardware.h>
++#endif
++#include <linux/workqueue.h>
++#include <linux/idr.h>
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
++#include <linux/math64.h>
++#endif
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++#include <linux/reset.h>
++static inline void imx_gpc_power_up_pu(bool flag) {}
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++#include <mach/common.h>
++#endif
++#include <linux/delay.h>
++#include <linux/pm_runtime.h>
++
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++#include <linux/file.h>
++#include "gc_hal_kernel_sync.h"
++#endif
++
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++/*******************************************************************************
++***** Version Signature *******************************************************/
++
++#ifdef ANDROID
++const char * _PLATFORM = "\n\0$PLATFORM$Android$\n";
++#else
++const char * _PLATFORM = "\n\0$PLATFORM$Linux$\n";
++#endif
++
++#define USER_SIGNAL_TABLE_LEN_INIT 64
++#define gcdSUPPRESS_OOM_MESSAGE 1
++
++#define MEMORY_LOCK(os) \
++ gcmkVERIFY_OK(gckOS_AcquireMutex( \
++ (os), \
++ (os)->memoryLock, \
++ gcvINFINITE))
++
++#define MEMORY_UNLOCK(os) \
++ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryLock))
++
++#define MEMORY_MAP_LOCK(os) \
++ gcmkVERIFY_OK(gckOS_AcquireMutex( \
++ (os), \
++ (os)->memoryMapLock, \
++ gcvINFINITE))
++
++#define MEMORY_MAP_UNLOCK(os) \
++ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryMapLock))
++
++/* Protection bit when mapping memroy to user sapce */
++#define gcmkPAGED_MEMROY_PROT(x) pgprot_writecombine(x)
++
++#if gcdNONPAGED_MEMORY_BUFFERABLE
++#define gcmkIOREMAP ioremap_wc
++#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_writecombine(x)
++#elif !gcdNONPAGED_MEMORY_CACHEABLE
++#define gcmkIOREMAP ioremap_nocache
++#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_noncached(x)
++#endif
++
++#if gcdSUPPRESS_OOM_MESSAGE
++#define gcdNOWARN __GFP_NOWARN
++#else
++#define gcdNOWARN 0
++#endif
++
++#define gcdINFINITE_TIMEOUT (60 * 1000)
++#define gcdDETECT_TIMEOUT 0
++#define gcdDETECT_DMA_ADDRESS 1
++#define gcdDETECT_DMA_STATE 1
++
++#define gcdUSE_NON_PAGED_MEMORY_CACHE 10
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++typedef struct _gcsNonPagedMemoryCache
++{
++#ifndef NO_DMA_COHERENT
++ gctINT size;
++ gctSTRING addr;
++ dma_addr_t dmaHandle;
++#else
++ long order;
++ struct page * page;
++#endif
++
++ struct _gcsNonPagedMemoryCache * prev;
++ struct _gcsNonPagedMemoryCache * next;
++}
++gcsNonPagedMemoryCache;
++#endif /* gcdUSE_NON_PAGED_MEMORY_CACHE */
++
++typedef struct _gcsUSER_MAPPING * gcsUSER_MAPPING_PTR;
++typedef struct _gcsUSER_MAPPING
++{
++ /* Pointer to next mapping structure. */
++ gcsUSER_MAPPING_PTR next;
++
++ /* Physical address of this mapping. */
++ gctUINT32 physical;
++
++ /* Logical address of this mapping. */
++ gctPOINTER logical;
++
++ /* Number of bytes of this mapping. */
++ gctSIZE_T bytes;
++
++ /* Starting address of this mapping. */
++ gctINT8_PTR start;
++
++ /* Ending address of this mapping. */
++ gctINT8_PTR end;
++}
++gcsUSER_MAPPING;
++
++typedef struct _gcsINTEGER_DB * gcsINTEGER_DB_PTR;
++typedef struct _gcsINTEGER_DB
++{
++ struct idr idr;
++ spinlock_t lock;
++ gctINT curr;
++}
++gcsINTEGER_DB;
++
++struct _gckOS
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Heap. */
++ gckHEAP heap;
++
++ /* Pointer to device */
++ gckGALDEVICE device;
++
++ /* Memory management */
++ gctPOINTER memoryLock;
++ gctPOINTER memoryMapLock;
++
++ struct _LINUX_MDL *mdlHead;
++ struct _LINUX_MDL *mdlTail;
++
++ /* Kernel process ID. */
++ gctUINT32 kernelProcessID;
++
++ /* Signal management. */
++
++ /* Lock. */
++ gctPOINTER signalMutex;
++
++ /* signal id database. */
++ gcsINTEGER_DB signalDB;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /* Lock. */
++ gctPOINTER syncPointMutex;
++
++ /* sync point id database. */
++ gcsINTEGER_DB syncPointDB;
++#endif
++
++ gcsUSER_MAPPING_PTR userMap;
++ gctPOINTER debugLock;
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ gctUINT cacheSize;
++ gcsNonPagedMemoryCache * cacheHead;
++ gcsNonPagedMemoryCache * cacheTail;
++#endif
++
++ /* workqueue for os timer. */
++ struct workqueue_struct * workqueue;
++};
++
++typedef struct _gcsSIGNAL * gcsSIGNAL_PTR;
++typedef struct _gcsSIGNAL
++{
++ /* Kernel sync primitive. */
++ struct completion obj;
++
++ /* Manual reset flag. */
++ gctBOOL manualReset;
++
++ /* The reference counter. */
++ atomic_t ref;
++
++ /* The owner of the signal. */
++ gctHANDLE process;
++
++ gckHARDWARE hardware;
++
++ /* ID. */
++ gctUINT32 id;
++}
++gcsSIGNAL;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++typedef struct _gcsSYNC_POINT * gcsSYNC_POINT_PTR;
++typedef struct _gcsSYNC_POINT
++{
++ /* The reference counter. */
++ atomic_t ref;
++
++ /* State. */
++ atomic_t state;
++
++ /* timeline. */
++ struct sync_timeline * timeline;
++
++ /* ID. */
++ gctUINT32 id;
++}
++gcsSYNC_POINT;
++#endif
++
++typedef struct _gcsPageInfo * gcsPageInfo_PTR;
++typedef struct _gcsPageInfo
++{
++ struct page **pages;
++ gctUINT32_PTR pageTable;
++}
++gcsPageInfo;
++
++typedef struct _gcsOSTIMER * gcsOSTIMER_PTR;
++typedef struct _gcsOSTIMER
++{
++ struct delayed_work work;
++ gctTIMERFUNCTION function;
++ gctPOINTER data;
++} gcsOSTIMER;
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++static gctINT
++_GetProcessID(
++ void
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++ return task_tgid_vnr(current);
++#else
++ return current->tgid;
++#endif
++}
++
++static gctINT
++_GetThreadID(
++ void
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++ return task_pid_vnr(current);
++#else
++ return current->pid;
++#endif
++}
++
++static PLINUX_MDL
++_CreateMdl(
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL mdl;
++
++ gcmkHEADER_ARG("ProcessID=%d", ProcessID);
++
++ mdl = (PLINUX_MDL)kzalloc(sizeof(struct _LINUX_MDL), GFP_KERNEL | gcdNOWARN);
++ if (mdl == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ mdl->pid = ProcessID;
++ mdl->maps = gcvNULL;
++ mdl->prev = gcvNULL;
++ mdl->next = gcvNULL;
++
++ gcmkFOOTER_ARG("0x%X", mdl);
++ return mdl;
++}
++
++static gceSTATUS
++_DestroyMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap
++ );
++
++static gceSTATUS
++_DestroyMdl(
++ IN PLINUX_MDL Mdl
++ )
++{
++ PLINUX_MDL_MAP mdlMap, next;
++
++ gcmkHEADER_ARG("Mdl=0x%X", Mdl);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Mdl != gcvNULL);
++
++ mdlMap = Mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ next = mdlMap->next;
++
++ gcmkVERIFY_OK(_DestroyMdlMap(Mdl, mdlMap));
++
++ mdlMap = next;
++ }
++
++ kfree(Mdl);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++static PLINUX_MDL_MAP
++_CreateMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID);
++
++ mdlMap = (PLINUX_MDL_MAP)kmalloc(sizeof(struct _LINUX_MDL_MAP), GFP_KERNEL | gcdNOWARN);
++ if (mdlMap == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ mdlMap->pid = ProcessID;
++ mdlMap->vmaAddr = gcvNULL;
++ mdlMap->vma = gcvNULL;
++ mdlMap->reference = 0;
++
++ mdlMap->next = Mdl->maps;
++ Mdl->maps = mdlMap;
++
++ gcmkFOOTER_ARG("0x%X", mdlMap);
++ return mdlMap;
++}
++
++static gceSTATUS
++_DestroyMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap
++ )
++{
++ PLINUX_MDL_MAP prevMdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X MdlMap=0x%X", Mdl, MdlMap);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(MdlMap != gcvNULL);
++ gcmkASSERT(Mdl->maps != gcvNULL);
++
++ if (Mdl->maps == MdlMap)
++ {
++ Mdl->maps = MdlMap->next;
++ }
++ else
++ {
++ prevMdlMap = Mdl->maps;
++
++ while (prevMdlMap->next != MdlMap)
++ {
++ prevMdlMap = prevMdlMap->next;
++
++ gcmkASSERT(prevMdlMap != gcvNULL);
++ }
++
++ prevMdlMap->next = MdlMap->next;
++ }
++
++ kfree(MdlMap);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++extern PLINUX_MDL_MAP
++FindMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID);
++ if(Mdl == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ mdlMap = Mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if (mdlMap->pid == ProcessID)
++ {
++ gcmkFOOTER_ARG("0x%X", mdlMap);
++ return mdlMap;
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvNULL;
++}
++
++void
++OnProcessExit(
++ IN gckOS Os,
++ IN gckKERNEL Kernel
++ )
++{
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
++static inline int
++is_vmalloc_addr(
++ void *Addr
++ )
++{
++ unsigned long addr = (unsigned long)Addr;
++
++ return addr >= VMALLOC_START && addr < VMALLOC_END;
++}
++#endif
++
++static void
++_NonContiguousFree(
++ IN struct page ** Pages,
++ IN gctUINT32 NumPages
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Pages=0x%X, NumPages=%d", Pages, NumPages);
++
++ gcmkASSERT(Pages != gcvNULL);
++
++ for (i = 0; i < NumPages; i++)
++ {
++ __free_page(Pages[i]);
++ }
++
++ if (is_vmalloc_addr(Pages))
++ {
++ vfree(Pages);
++ }
++ else
++ {
++ kfree(Pages);
++ }
++
++ gcmkFOOTER_NO();
++}
++
++static struct page **
++_NonContiguousAlloc(
++ IN gctUINT32 NumPages
++ )
++{
++ struct page ** pages;
++ struct page *p;
++ gctINT i, size;
++
++ gcmkHEADER_ARG("NumPages=%lu", NumPages);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)
++ if (NumPages > totalram_pages)
++#else
++ if (NumPages > num_physpages)
++#endif
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ size = NumPages * sizeof(struct page *);
++
++ pages = kmalloc(size, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ pages = vmalloc(size);
++
++ if (!pages)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ }
++
++ for (i = 0; i < NumPages; i++)
++ {
++ p = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN);
++
++ if (!p)
++ {
++ _NonContiguousFree(pages, i);
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ pages[i] = p;
++ }
++
++ gcmkFOOTER_ARG("pages=0x%X", pages);
++ return pages;
++}
++
++static inline struct page *
++_NonContiguousToPage(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return Pages[Index];
++}
++
++static inline unsigned long
++_NonContiguousToPfn(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return page_to_pfn(_NonContiguousToPage(Pages, Index));
++}
++
++static inline unsigned long
++_NonContiguousToPhys(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return page_to_phys(_NonContiguousToPage(Pages, Index));
++}
++
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++
++static gctBOOL
++_AddNonPagedMemoryCache(
++ gckOS Os,
++#ifndef NO_DMA_COHERENT
++ gctINT Size,
++ gctSTRING Addr,
++ dma_addr_t DmaHandle
++#else
++ long Order,
++ struct page * Page
++#endif
++ )
++{
++ gcsNonPagedMemoryCache *cache;
++
++ if (Os->cacheSize >= gcdUSE_NON_PAGED_MEMORY_CACHE)
++ {
++ return gcvFALSE;
++ }
++
++ /* Allocate the cache record */
++ cache = (gcsNonPagedMemoryCache *)kmalloc(sizeof(gcsNonPagedMemoryCache), GFP_ATOMIC);
++
++ if (cache == gcvNULL) return gcvFALSE;
++
++#ifndef NO_DMA_COHERENT
++ cache->size = Size;
++ cache->addr = Addr;
++ cache->dmaHandle = DmaHandle;
++#else
++ cache->order = Order;
++ cache->page = Page;
++#endif
++
++ /* Add to list */
++ if (Os->cacheHead == gcvNULL)
++ {
++ cache->prev = gcvNULL;
++ cache->next = gcvNULL;
++ Os->cacheHead =
++ Os->cacheTail = cache;
++ }
++ else
++ {
++ /* Add to the tail. */
++ cache->prev = Os->cacheTail;
++ cache->next = gcvNULL;
++ Os->cacheTail->next = cache;
++ Os->cacheTail = cache;
++ }
++
++ Os->cacheSize++;
++
++ return gcvTRUE;
++}
++
++#ifndef NO_DMA_COHERENT
++static gctSTRING
++_GetNonPagedMemoryCache(
++ gckOS Os,
++ gctINT Size,
++ dma_addr_t * DmaHandle
++ )
++#else
++static struct page *
++_GetNonPagedMemoryCache(
++ gckOS Os,
++ long Order
++ )
++#endif
++{
++ gcsNonPagedMemoryCache *cache;
++#ifndef NO_DMA_COHERENT
++ gctSTRING addr;
++#else
++ struct page * page;
++#endif
++
++ if (Os->cacheHead == gcvNULL) return gcvNULL;
++
++ /* Find the right cache */
++ cache = Os->cacheHead;
++
++ while (cache != gcvNULL)
++ {
++#ifndef NO_DMA_COHERENT
++ if (cache->size == Size) break;
++#else
++ if (cache->order == Order) break;
++#endif
++
++ cache = cache->next;
++ }
++
++ if (cache == gcvNULL) return gcvNULL;
++
++ /* Remove the cache from list */
++ if (cache == Os->cacheHead)
++ {
++ Os->cacheHead = cache->next;
++
++ if (Os->cacheHead == gcvNULL)
++ {
++ Os->cacheTail = gcvNULL;
++ }
++ }
++ else
++ {
++ cache->prev->next = cache->next;
++
++ if (cache == Os->cacheTail)
++ {
++ Os->cacheTail = cache->prev;
++ }
++ else
++ {
++ cache->next->prev = cache->prev;
++ }
++ }
++
++ /* Destroy cache */
++#ifndef NO_DMA_COHERENT
++ addr = cache->addr;
++ *DmaHandle = cache->dmaHandle;
++#else
++ page = cache->page;
++#endif
++
++ kfree(cache);
++
++ Os->cacheSize--;
++
++#ifndef NO_DMA_COHERENT
++ return addr;
++#else
++ return page;
++#endif
++}
++
++static void
++_FreeAllNonPagedMemoryCache(
++ gckOS Os
++ )
++{
++ gcsNonPagedMemoryCache *cache, *nextCache;
++
++ MEMORY_LOCK(Os);
++
++ cache = Os->cacheHead;
++
++ while (cache != gcvNULL)
++ {
++ if (cache != Os->cacheTail)
++ {
++ nextCache = cache->next;
++ }
++ else
++ {
++ nextCache = gcvNULL;
++ }
++
++ /* Remove the cache from list */
++ if (cache == Os->cacheHead)
++ {
++ Os->cacheHead = cache->next;
++
++ if (Os->cacheHead == gcvNULL)
++ {
++ Os->cacheTail = gcvNULL;
++ }
++ }
++ else
++ {
++ cache->prev->next = cache->next;
++
++ if (cache == Os->cacheTail)
++ {
++ Os->cacheTail = cache->prev;
++ }
++ else
++ {
++ cache->next->prev = cache->prev;
++ }
++ }
++
++#ifndef NO_DMA_COHERENT
++ dma_free_coherent(gcvNULL,
++ cache->size,
++ cache->addr,
++ cache->dmaHandle);
++#else
++ free_pages((unsigned long)page_address(cache->page), cache->order);
++#endif
++
++ kfree(cache);
++
++ cache = nextCache;
++ }
++
++ MEMORY_UNLOCK(Os);
++}
++
++#endif /* gcdUSE_NON_PAGED_MEMORY_CACHE */
++
++/*******************************************************************************
++** Integer Id Management.
++*/
++gceSTATUS
++_AllocateIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctPOINTER KernelPointer,
++ OUT gctUINT32 *Id
++ )
++{
++ int result;
++ gctINT next;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
++ idr_preload(GFP_KERNEL | gcdNOWARN);
++
++ spin_lock(&Database->lock);
++
++ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
++ result = idr_alloc(&Database->idr, KernelPointer, next, 0, GFP_ATOMIC);
++
++ if (!result)
++ {
++ Database->curr = *Id;
++ }
++
++ spin_unlock(&Database->lock);
++
++ idr_preload_end();
++
++ if (result < 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ *Id = result;
++#else
++again:
++ if (idr_pre_get(&Database->idr, GFP_KERNEL | gcdNOWARN) == 0)
++ {
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ spin_lock(&Database->lock);
++
++ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
++
++ /* Try to get a id greater than current id. */
++ result = idr_get_new_above(&Database->idr, KernelPointer, next, Id);
++
++ if (!result)
++ {
++ Database->curr = *Id;
++ }
++
++ spin_unlock(&Database->lock);
++
++ if (result == -EAGAIN)
++ {
++ goto again;
++ }
++
++ if (result != 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_QueryIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gctPOINTER pointer;
++
++ spin_lock(&Database->lock);
++
++ pointer = idr_find(&Database->idr, Id);
++
++ spin_unlock(&Database->lock);
++
++ if(pointer)
++ {
++ *KernelPointer = pointer;
++ return gcvSTATUS_OK;
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_OS,
++ "%s(%d) Id = %d is not found",
++ __FUNCTION__, __LINE__, Id);
++
++ return gcvSTATUS_NOT_FOUND;
++ }
++}
++
++gceSTATUS
++_DestroyIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctUINT32 Id
++ )
++{
++ spin_lock(&Database->lock);
++
++ idr_remove(&Database->idr, Id);
++
++ spin_unlock(&Database->lock);
++
++ return gcvSTATUS_OK;
++}
++
++static void
++_UnmapUserLogical(
++ IN gctINT Pid,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++)
++{
++ if (unlikely(current->mm == gcvNULL))
++ {
++ /* Do nothing if process is exiting. */
++ return;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ if (vm_munmap((unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): vm_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++#else
++ down_write(&current->mm->mmap_sem);
++ if (do_munmap(current->mm, (unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++ up_write(&current->mm->mmap_sem);
++#endif
++}
++
++gceSTATUS
++_QueryProcessPageTable(
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ spinlock_t *lock;
++ gctUINTPTR_T logical = (gctUINTPTR_T)Logical;
++ pgd_t *pgd;
++ pud_t *pud;
++ pmd_t *pmd;
++ pte_t *pte;
++
++ if (!current->mm)
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pgd = pgd_offset(current->mm, logical);
++ if (pgd_none(*pgd) || pgd_bad(*pgd))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pud = pud_offset(pgd, logical);
++ if (pud_none(*pud) || pud_bad(*pud))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pmd = pmd_offset(pud, logical);
++ if (pmd_none(*pmd) || pmd_bad(*pmd))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pte = pte_offset_map_lock(current->mm, pmd, logical, &lock);
++ if (!pte)
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ if (!pte_present(*pte))
++ {
++ pte_unmap_unlock(pte, lock);
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ *Address = (pte_pfn(*pte) << PAGE_SHIFT) | (logical & ~PAGE_MASK);
++ pte_unmap_unlock(pte, lock);
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Construct
++**
++** Construct a new gckOS object.
++**
++** INPUT:
++**
++** gctPOINTER Context
++** Pointer to the gckGALDEVICE class.
++**
++** OUTPUT:
++**
++** gckOS * Os
++** Pointer to a variable that will hold the pointer to the gckOS object.
++*/
++gceSTATUS
++gckOS_Construct(
++ IN gctPOINTER Context,
++ OUT gckOS * Os
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Context=0x%X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Os != gcvNULL);
++
++ /* Allocate the gckOS object. */
++ os = (gckOS) kmalloc(gcmSIZEOF(struct _gckOS), GFP_KERNEL | gcdNOWARN);
++
++ if (os == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ /* Zero the memory. */
++ gckOS_ZeroMemory(os, gcmSIZEOF(struct _gckOS));
++
++ /* Initialize the gckOS object. */
++ os->object.type = gcvOBJ_OS;
++
++ /* Set device device. */
++ os->device = Context;
++
++ /* IMPORTANT! No heap yet. */
++ os->heap = gcvNULL;
++
++ /* Initialize the memory lock. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->memoryLock));
++ gcmkONERROR(gckOS_CreateMutex(os, &os->memoryMapLock));
++
++ /* Create debug lock mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->debugLock));
++
++
++ os->mdlHead = os->mdlTail = gcvNULL;
++
++ /* Get the kernel process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&os->kernelProcessID));
++
++ /*
++ * Initialize the signal manager.
++ */
++
++ /* Initialize mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->signalMutex));
++
++ /* Initialize signal id database lock. */
++ spin_lock_init(&os->signalDB.lock);
++
++ /* Initialize signal id database. */
++ idr_init(&os->signalDB.idr);
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /*
++ * Initialize the sync point manager.
++ */
++
++ /* Initialize mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->syncPointMutex));
++
++ /* Initialize sync point id database lock. */
++ spin_lock_init(&os->syncPointDB.lock);
++
++ /* Initialize sync point id database. */
++ idr_init(&os->syncPointDB.idr);
++#endif
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ os->cacheSize = 0;
++ os->cacheHead = gcvNULL;
++ os->cacheTail = gcvNULL;
++#endif
++
++ /* Create a workqueue for os timer. */
++ os->workqueue = create_singlethread_workqueue("galcore workqueue");
++
++ if (os->workqueue == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Return pointer to the gckOS object. */
++ *Os = os;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Os=0x%X", *Os);
++ return gcvSTATUS_OK;
++
++OnError:
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ if (os->syncPointMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->syncPointMutex));
++ }
++#endif
++
++ if (os->signalMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->signalMutex));
++ }
++
++ if (os->heap != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckHEAP_Destroy(os->heap));
++ }
++
++ if (os->memoryMapLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->memoryMapLock));
++ }
++
++ if (os->memoryLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->memoryLock));
++ }
++
++ if (os->debugLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->debugLock));
++ }
++
++ if (os->workqueue != gcvNULL)
++ {
++ destroy_workqueue(os->workqueue);
++ }
++
++ kfree(os);
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Destroy
++**
++** Destroy an gckOS object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Destroy(
++ IN gckOS Os
++ )
++{
++ gckHEAP heap;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ _FreeAllNonPagedMemoryCache(Os);
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /*
++ * Destroy the sync point manager.
++ */
++
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->syncPointMutex));
++#endif
++
++ /*
++ * Destroy the signal manager.
++ */
++
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->signalMutex));
++
++ if (Os->heap != gcvNULL)
++ {
++ /* Mark gckHEAP as gone. */
++ heap = Os->heap;
++ Os->heap = gcvNULL;
++
++ /* Destroy the gckHEAP object. */
++ gcmkVERIFY_OK(gckHEAP_Destroy(heap));
++ }
++
++ /* Destroy the memory lock. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryMapLock));
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryLock));
++
++ /* Destroy debug lock mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->debugLock));
++
++ /* Wait for all works done. */
++ flush_workqueue(Os->workqueue);
++
++ /* Destory work queue. */
++ destroy_workqueue(Os->workqueue);
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(~0U);
++
++ /* Mark the gckOS object as unknown. */
++ Os->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckOS object. */
++ kfree(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++static gctSTRING
++_CreateKernelVirtualMapping(
++ IN PLINUX_MDL Mdl
++ )
++{
++ gctSTRING addr = 0;
++ gctINT numPages = Mdl->numPages;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ if (Mdl->contiguous)
++ {
++ addr = page_address(Mdl->u.contiguousPages);
++ }
++ else
++ {
++ addr = vmap(Mdl->u.nonContiguousPages,
++ numPages,
++ 0,
++ PAGE_KERNEL);
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++ }
++#else
++ struct page ** pages;
++ gctBOOL free = gcvFALSE;
++ gctINT i;
++
++ if (Mdl->contiguous)
++ {
++ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ return gcvNULL;
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ pages[i] = nth_page(Mdl->u.contiguousPages, i);
++ }
++
++ free = gcvTRUE;
++ }
++ else
++ {
++ pages = Mdl->u.nonContiguousPages;
++ }
++
++ /* ioremap() can't work on system memory since 2.6.38. */
++ addr = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL));
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++
++ if (free)
++ {
++ kfree(pages);
++ }
++
++#endif
++
++ return addr;
++}
++
++static void
++_DestoryKernelVirtualMapping(
++ IN gctSTRING Addr
++ )
++{
++#if !gcdNONPAGED_MEMORY_CACHEABLE
++ vunmap(Addr);
++#endif
++}
++
++gceSTATUS
++gckOS_CreateKernelVirtualMapping(
++ IN gctPHYS_ADDR Physical,
++ OUT gctSIZE_T * PageCount,
++ OUT gctPOINTER * Logical
++ )
++{
++ *PageCount = ((PLINUX_MDL)Physical)->numPages;
++ *Logical = _CreateKernelVirtualMapping((PLINUX_MDL)Physical);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DestroyKernelVirtualMapping(
++ IN gctPOINTER Logical
++ )
++{
++ _DestoryKernelVirtualMapping((gctSTRING)Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Allocate
++**
++** Allocate memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the allocated memory location.
++*/
++gceSTATUS
++gckOS_Allocate(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Do we have a heap? */
++ if (Os->heap != gcvNULL)
++ {
++ /* Allocate from the heap. */
++ gcmkONERROR(gckHEAP_Allocate(Os->heap, Bytes, Memory));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AllocateMemory(Os, Bytes, Memory));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%X", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Free
++**
++** Free allocated memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Memory
++** Pointer to memory allocation to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Free(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Memory=0x%X", Os, Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Do we have a heap? */
++ if (Os->heap != gcvNULL)
++ {
++ /* Free from the heap. */
++ gcmkONERROR(gckHEAP_Free(Os->heap, Memory));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_FreeMemory(Os, Memory));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocateMemory
++**
++** Allocate memory wrapper.
++**
++** INPUT:
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the allocated memory location.
++*/
++gceSTATUS
++gckOS_AllocateMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gctPOINTER memory;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ if (Bytes > PAGE_SIZE)
++ {
++ memory = (gctPOINTER) vmalloc(Bytes);
++ }
++ else
++ {
++ memory = (gctPOINTER) kmalloc(Bytes, GFP_KERNEL | gcdNOWARN);
++ }
++
++ if (memory == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Return pointer to the memory allocation. */
++ *Memory = memory;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%X", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeMemory
++**
++** Free allocated memory wrapper.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory allocation to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreeMemory(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ )
++{
++ gcmkHEADER_ARG("Memory=0x%X", Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Free the memory from the OS pool. */
++ if (is_vmalloc_addr(Memory))
++ {
++ vfree(Memory);
++ }
++ else
++ {
++ kfree(Memory);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapMemory
++**
++** Map physical memory into the current process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the logical address of the
++** mapped memory.
++*/
++gceSTATUS
++gckOS_MapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = FindMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++
++ if (mdlMap->vmaAddr == gcvNULL)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (char *)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (char *)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): mdl->numPages: %d mdl->vmaAddr: 0x%X",
++ __FUNCTION__, __LINE__,
++ mdl->numPages,
++ mdlMap->vmaAddr
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (!mdlMap->vma)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): find_vma error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ up_write(&current->mm->mmap_sem);
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++#ifndef NO_DMA_COHERENT
++ if (dma_mmap_coherent(gcvNULL,
++ mdlMap->vma,
++ mdl->addr,
++ mdl->dmaHandle,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): dma_mmap_coherent error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#else
++#if !gcdPAGED_MEMORY_CACHEABLE
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++# endif
++ mdlMap->vma->vm_pgoff = 0;
++
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ mdl->dmaHandle >> PAGE_SHIFT,
++ mdl->numPages*PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): remap_pfn_range error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#endif
++
++ up_write(&current->mm->mmap_sem);
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ *Logical = mdlMap->vmaAddr;
++
++ gcmkFOOTER_ARG("*Logical=0x%X", *Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapMemory
++**
++** Unmap physical memory out of the current process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gckOS_UnmapMemoryEx(Os, Physical, Bytes, Logical, _GetProcessID());
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckOS_UnmapMemoryEx
++**
++** Unmap physical memory in the specified process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** gctUINT32 PID
++** Pid of the process that opened the device and mapped this memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapMemoryEx(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical,
++ IN gctUINT32 PID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X PID=%d",
++ Os, Physical, Bytes, Logical, PID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PID != 0);
++
++ MEMORY_LOCK(Os);
++
++ if (Logical)
++ {
++ mdlMap = FindMdlMap(mdl, PID);
++
++ if (mdlMap == gcvNULL || mdlMap->vmaAddr == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ _UnmapUserLogical(PID, mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE);
++
++ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap));
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserLogical
++**
++** Unmap user logical memory out of physical memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserLogical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gckOS_UnmapMemory(Os, Physical, Bytes, Logical);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocateNonPagedMemory
++**
++** Allocate a number of pages from non-paged memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the pages need to be mapped into user space.
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that holds the number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that hold the number of bytes allocated.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that will hold the physical address of the
++** allocation.
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** allocation.
++*/
++gceSTATUS
++gckOS_AllocateNonPagedMemory(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gctSIZE_T bytes;
++ gctINT numPages;
++ PLINUX_MDL mdl = gcvNULL;
++ PLINUX_MDL_MAP mdlMap = gcvNULL;
++ gctSTRING addr;
++#ifdef NO_DMA_COHERENT
++ struct page * page;
++ long size, order;
++ gctPOINTER vaddr;
++#endif
++ gctBOOL locked = gcvFALSE;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ Os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Align number of bytes to page size. */
++ bytes = gcmALIGN(*Bytes, PAGE_SIZE);
++
++ /* Get total number of pages.. */
++ numPages = GetPageCount(bytes, 0);
++
++ /* Allocate mdl+vector structure */
++ mdl = _CreateMdl(_GetProcessID());
++ if (mdl == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mdl->pagedMem = 0;
++ mdl->numPages = numPages;
++
++ MEMORY_LOCK(Os);
++ locked = gcvTRUE;
++
++#ifndef NO_DMA_COHERENT
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ addr = _GetNonPagedMemoryCache(Os,
++ mdl->numPages * PAGE_SIZE,
++ &mdl->dmaHandle);
++
++ if (addr == gcvNULL)
++#endif
++ {
++ addr = dma_alloc_coherent(gcvNULL,
++ mdl->numPages * PAGE_SIZE,
++ &mdl->dmaHandle,
++ GFP_KERNEL | gcdNOWARN);
++ }
++#else
++ size = mdl->numPages * PAGE_SIZE;
++ order = get_order(size);
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ page = _GetNonPagedMemoryCache(Os, order);
++
++ if (page == gcvNULL)
++#endif
++ {
++ page = alloc_pages(GFP_KERNEL | gcdNOWARN, order);
++ }
++
++ if (page == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ vaddr = (gctPOINTER)page_address(page);
++ mdl->contiguous = gcvTRUE;
++ mdl->u.contiguousPages = page;
++ addr = _CreateKernelVirtualMapping(mdl);
++ mdl->dmaHandle = virt_to_phys(vaddr);
++ mdl->kaddr = vaddr;
++ mdl->u.contiguousPages = page;
++
++#if !defined(CONFIG_PPC)
++ /* Cache invalidate. */
++ dma_sync_single_for_device(
++ gcvNULL,
++ page_to_phys(page),
++ bytes,
++ DMA_FROM_DEVICE);
++#endif
++
++ while (size > 0)
++ {
++ SetPageReserved(virt_to_page(vaddr));
++
++ vaddr += PAGE_SIZE;
++ size -= PAGE_SIZE;
++ }
++#endif
++
++ if (addr == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mdl->addr = addr;
++
++ /* Return allocated memory. */
++ *Bytes = bytes;
++ *Physical = (gctPHYS_ADDR) mdl;
++
++ if (InUserSpace)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Only after mmap this will be valid. */
++
++ /* We need to map this to user space. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING) vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING) do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++#ifndef NO_DMA_COHERENT
++ if (dma_mmap_coherent(gcvNULL,
++ mdlMap->vma,
++ mdl->addr,
++ mdl->dmaHandle,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): dma_mmap_coherent error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#else
++ mdlMap->vma->vm_page_prot = gcmkNONPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++ mdlMap->vma->vm_pgoff = 0;
++
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ mdl->dmaHandle >> PAGE_SHIFT,
++ mdl->numPages * PAGE_SIZE,
++ mdlMap->vma->vm_page_prot))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): remap_pfn_range error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#endif /* NO_DMA_COHERENT */
++
++ up_write(&current->mm->mmap_sem);
++
++ *Logical = mdlMap->vmaAddr;
++ }
++ else
++ {
++ *Logical = (gctPOINTER)mdl->addr;
++ }
++
++ /*
++ * Add this to a global list.
++ * Will be used by get physical address
++ * and mapuser pointer functions.
++ */
++
++ if (!Os->mdlHead)
++ {
++ /* Initialize the queue. */
++ Os->mdlHead = Os->mdlTail = mdl;
++ }
++ else
++ {
++ /* Add to the tail. */
++ mdl->prev = Os->mdlTail;
++ Os->mdlTail->next = mdl;
++ Os->mdlTail = mdl;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X",
++ *Bytes, *Physical, *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mdlMap != gcvNULL)
++ {
++ /* Free LINUX_MDL_MAP. */
++ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap));
++ }
++
++ if (mdl != gcvNULL)
++ {
++ /* Free LINUX_MDL. */
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++ }
++
++ if (locked)
++ {
++ /* Unlock memory. */
++ MEMORY_UNLOCK(Os);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeNonPagedMemory
++**
++** Free previously allocated and mapped pages from non-paged memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes allocated.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocated memory.
++**
++** gctPOINTER Logical
++** Logical address of the allocated memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckOS_FreeNonPagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++#ifdef NO_DMA_COHERENT
++ unsigned size;
++ gctPOINTER vaddr;
++#endif /* NO_DMA_COHERENT */
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu Physical=0x%X Logical=0x%X",
++ Os, Bytes, Physical, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert physical address into a pointer to a MDL. */
++ mdl = (PLINUX_MDL) Physical;
++
++ MEMORY_LOCK(Os);
++
++#ifndef NO_DMA_COHERENT
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ if (!_AddNonPagedMemoryCache(Os,
++ mdl->numPages * PAGE_SIZE,
++ mdl->addr,
++ mdl->dmaHandle))
++#endif
++ {
++ dma_free_coherent(gcvNULL,
++ mdl->numPages * PAGE_SIZE,
++ mdl->addr,
++ mdl->dmaHandle);
++ }
++#else
++ size = mdl->numPages * PAGE_SIZE;
++ vaddr = mdl->kaddr;
++
++ while (size > 0)
++ {
++ ClearPageReserved(virt_to_page(vaddr));
++
++ vaddr += PAGE_SIZE;
++ size -= PAGE_SIZE;
++ }
++
++#if gcdUSE_NON_PAGED_MEMORY_CACHE
++ if (!_AddNonPagedMemoryCache(Os,
++ get_order(mdl->numPages * PAGE_SIZE),
++ virt_to_page(mdl->kaddr)))
++#endif
++ {
++ free_pages((unsigned long)mdl->kaddr, get_order(mdl->numPages * PAGE_SIZE));
++ }
++
++ _DestoryKernelVirtualMapping(mdl->addr);
++#endif /* NO_DMA_COHERENT */
++
++ mdlMap = mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if (mdlMap->vmaAddr != gcvNULL)
++ {
++ /* No mapped memory exists when free nonpaged memory */
++ gcmkASSERT(0);
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ /* Remove the node from global list.. */
++ if (mdl == Os->mdlHead)
++ {
++ if ((Os->mdlHead = mdl->next) == gcvNULL)
++ {
++ Os->mdlTail = gcvNULL;
++ }
++ }
++ else
++ {
++ mdl->prev->next = mdl->next;
++ if (mdl == Os->mdlTail)
++ {
++ Os->mdlTail = mdl->prev;
++ }
++ else
++ {
++ mdl->next->prev = mdl->prev;
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReadRegister
++**
++** Read data from a register.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Address of register.
++**
++** OUTPUT:
++**
++** gctUINT32 * Data
++** Pointer to a variable that receives the data read from the register.
++*/
++gceSTATUS
++gckOS_ReadRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ return gckOS_ReadRegisterEx(Os, gcvCORE_MAJOR, Address, Data);
++}
++
++gceSTATUS
++gckOS_ReadRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X", Os, Core, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ *Data = readl((gctUINT8 *)Os->device->registerBases[Core] + Address);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_WriteRegister
++**
++** Write data to a register.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Address of register.
++**
++** gctUINT32 Data
++** Data for register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WriteRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ return gckOS_WriteRegisterEx(Os, gcvCORE_MAJOR, Address, Data);
++}
++
++gceSTATUS
++gckOS_WriteRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X Data=0x%08x", Os, Core, Address, Data);
++
++ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
++
++ writel(Data, (gctUINT8 *)Os->device->registerBases[Core] + Address);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPageSize
++**
++** Get the system's page size.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * PageSize
++** Pointer to a variable that will receive the system's page size.
++*/
++gceSTATUS gckOS_GetPageSize(
++ IN gckOS Os,
++ OUT gctSIZE_T * PageSize
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(PageSize != gcvNULL);
++
++ /* Return the page size. */
++ *PageSize = (gctSIZE_T) PAGE_SIZE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*PageSize", *PageSize);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPhysicalAddress
++**
++** Get the physical system address of a corresponding virtual address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Poinetr to a variable that receives the 32-bit physical adress.
++*/
++gceSTATUS
++gckOS_GetPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X", Os, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Query page table of current process first. */
++ status = _QueryProcessPageTable(Logical, Address);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Get current process ID. */
++ processID = _GetProcessID();
++
++ /* Route through other function. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddressProcess(Os, Logical, processID, Address));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++static gceSTATUS
++gckOS_AddMapping(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gcsUSER_MAPPING_PTR map;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Logical=0x%X Bytes=%lu",
++ Os, Physical, Logical, Bytes);
++
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(gcsUSER_MAPPING),
++ (gctPOINTER *) &map));
++
++ map->next = Os->userMap;
++ map->physical = Physical - Os->device->baseAddress;
++ map->logical = Logical;
++ map->bytes = Bytes;
++ map->start = (gctINT8_PTR) Logical;
++ map->end = map->start + Bytes;
++
++ Os->userMap = map;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckOS_RemoveMapping(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gcsUSER_MAPPING_PTR map, prev;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu", Os, Logical, Bytes);
++
++ for (map = Os->userMap, prev = gcvNULL; map != gcvNULL; map = map->next)
++ {
++ if ((map->logical == Logical)
++ && (map->bytes == Bytes)
++ )
++ {
++ break;
++ }
++
++ prev = map;
++ }
++
++ if (map == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ADDRESS);
++ }
++
++ if (prev == gcvNULL)
++ {
++ Os->userMap = map->next;
++ }
++ else
++ {
++ prev->next = map->next;
++ }
++
++ gcmkONERROR(gcmkOS_SAFE_FREE(Os, map));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_ConvertLogical2Physical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ IN PLINUX_MDL Mdl,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ gctINT8_PTR base, vBase;
++ gctUINT32 offset;
++ PLINUX_MDL_MAP map;
++ gcsUSER_MAPPING_PTR userMap;
++
++ base = (Mdl == gcvNULL) ? gcvNULL : (gctINT8_PTR) Mdl->addr;
++
++ /* Check for the logical address match. */
++ if ((base != gcvNULL)
++ && ((gctINT8_PTR) Logical >= base)
++ && ((gctINT8_PTR) Logical < base + Mdl->numPages * PAGE_SIZE)
++ )
++ {
++ offset = (gctINT8_PTR) Logical - base;
++
++ if (Mdl->dmaHandle != 0)
++ {
++ /* The memory was from coherent area. */
++ *Physical = (gctUINT32) Mdl->dmaHandle + offset;
++ }
++ else if (Mdl->pagedMem && !Mdl->contiguous)
++ {
++ /* paged memory is not mapped to kernel space. */
++ return gcvSTATUS_INVALID_ADDRESS;
++ }
++ else
++ {
++ *Physical = gcmPTR2INT(virt_to_phys(base)) + offset;
++ }
++
++ return gcvSTATUS_OK;
++ }
++
++ /* Walk user maps. */
++ for (userMap = Os->userMap; userMap != gcvNULL; userMap = userMap->next)
++ {
++ if (((gctINT8_PTR) Logical >= userMap->start)
++ && ((gctINT8_PTR) Logical < userMap->end)
++ )
++ {
++ *Physical = userMap->physical
++ + (gctUINT32) ((gctINT8_PTR) Logical - userMap->start);
++
++ return gcvSTATUS_OK;
++ }
++ }
++
++ if (ProcessID != Os->kernelProcessID)
++ {
++ map = FindMdlMap(Mdl, (gctINT) ProcessID);
++ vBase = (map == gcvNULL) ? gcvNULL : (gctINT8_PTR) map->vmaAddr;
++
++ /* Is the given address within that range. */
++ if ((vBase != gcvNULL)
++ && ((gctINT8_PTR) Logical >= vBase)
++ && ((gctINT8_PTR) Logical < vBase + Mdl->numPages * PAGE_SIZE)
++ )
++ {
++ offset = (gctINT8_PTR) Logical - vBase;
++
++ if (Mdl->dmaHandle != 0)
++ {
++ /* The memory was from coherent area. */
++ *Physical = (gctUINT32) Mdl->dmaHandle + offset;
++ }
++ else if (Mdl->pagedMem && !Mdl->contiguous)
++ {
++ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, offset/PAGE_SIZE);
++ }
++ else
++ {
++ *Physical = page_to_phys(Mdl->u.contiguousPages) + offset;
++ }
++
++ return gcvSTATUS_OK;
++ }
++ }
++
++ /* Address not yet found. */
++ return gcvSTATUS_INVALID_ADDRESS;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPhysicalAddressProcess
++**
++** Get the physical system address of a corresponding virtual address for a
++** given process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** gctUINT32 ProcessID
++** Process ID.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Poinetr to a variable that receives the 32-bit physical adress.
++*/
++gceSTATUS
++gckOS_GetPhysicalAddressProcess(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32 * Address
++ )
++{
++ PLINUX_MDL mdl;
++ gctINT8_PTR base;
++ gceSTATUS status = gcvSTATUS_INVALID_ADDRESS;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X ProcessID=%d", Os, Logical, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ /* First try the contiguous memory pool. */
++ if (Os->device->contiguousMapped)
++ {
++ base = (gctINT8_PTR) Os->device->contiguousBase;
++
++ if (((gctINT8_PTR) Logical >= base)
++ && ((gctINT8_PTR) Logical < base + Os->device->contiguousSize)
++ )
++ {
++ /* Convert logical address into physical. */
++ *Address = Os->device->contiguousVidMem->baseAddress
++ + (gctINT8_PTR) Logical - base;
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Try the contiguous memory pool. */
++ mdl = (PLINUX_MDL) Os->device->contiguousPhysical;
++ status = _ConvertLogical2Physical(Os,
++ Logical,
++ ProcessID,
++ mdl,
++ Address);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Walk all MDLs. */
++ for (mdl = Os->mdlHead; mdl != gcvNULL; mdl = mdl->next)
++ {
++ /* Try this MDL. */
++ status = _ConvertLogical2Physical(Os,
++ Logical,
++ ProcessID,
++ mdl,
++ Address);
++ if (gcmIS_SUCCESS(status))
++ {
++ break;
++ }
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkONERROR(status);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapPhysical
++**
++** Map a physical address into kernel space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Physical
++** Physical address of the memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the base address of the mapped
++** memory.
++*/
++gceSTATUS
++gckOS_MapPhysical(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ gctPOINTER logical;
++ PLINUX_MDL mdl;
++ gctUINT32 physical = Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ /* Go through our mapping to see if we know this physical address already. */
++ mdl = Os->mdlHead;
++
++ while (mdl != gcvNULL)
++ {
++ if (mdl->dmaHandle != 0)
++ {
++ if ((physical >= mdl->dmaHandle)
++ && (physical < mdl->dmaHandle + mdl->numPages * PAGE_SIZE)
++ )
++ {
++ *Logical = mdl->addr + (physical - mdl->dmaHandle);
++ break;
++ }
++ }
++
++ mdl = mdl->next;
++ }
++
++ if (mdl == gcvNULL)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct contiguous_mem_pool *pool = Os->device->pool;
++
++ if (Physical >= pool->phys && Physical < pool->phys + pool->size)
++ logical = (gctPOINTER)(Physical - pool->phys + pool->virt);
++ else
++ logical = gcvNULL;
++#else
++ /* Map memory as cached memory. */
++ request_mem_region(physical, Bytes, "MapRegion");
++ logical = (gctPOINTER) ioremap_nocache(physical, Bytes);
++#endif
++
++ if (logical == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Failed to map physical address 0x%08x",
++ __FUNCTION__, __LINE__, Physical
++ );
++
++ MEMORY_UNLOCK(Os);
++
++ /* Out of resources. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Return pointer to mapped memory. */
++ *Logical = logical;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=0x%X", *Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapPhysical
++**
++** Unmap a previously mapped memory region from kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Pointer to the base address of the memory to unmap.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ PLINUX_MDL mdl;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu", Os, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ MEMORY_LOCK(Os);
++
++ mdl = Os->mdlHead;
++
++ while (mdl != gcvNULL)
++ {
++ if (mdl->addr != gcvNULL)
++ {
++ if (Logical >= (gctPOINTER)mdl->addr
++ && Logical < (gctPOINTER)((gctSTRING)mdl->addr + mdl->numPages * PAGE_SIZE))
++ {
++ break;
++ }
++ }
++
++ mdl = mdl->next;
++ }
++
++ if (mdl == gcvNULL)
++ {
++ /* Unmap the memory. */
++ iounmap(Logical);
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateMutex
++**
++** Create a new mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Mutex
++** Pointer to a variable that will hold a pointer to the mutex.
++*/
++gceSTATUS
++gckOS_CreateMutex(
++ IN gckOS Os,
++ OUT gctPOINTER * Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Allocate the mutex structure. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct mutex), Mutex));
++
++ /* Initialize the mutex. */
++ mutex_init(*Mutex);
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Mutex=0x%X", *Mutex);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DeleteMutex
++**
++** Delete a mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mute to be deleted.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DeleteMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%X", Os, Mutex);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Destroy the mutex. */
++ mutex_destroy(Mutex);
++
++ /* Free the mutex structure. */
++ gcmkONERROR(gckOS_Free(Os, Mutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AcquireMutex
++**
++** Acquire a mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mutex to be acquired.
++**
++** gctUINT32 Timeout
++** Timeout value specified in milliseconds.
++** Specify the value of gcvINFINITE to keep the thread suspended
++** until the mutex has been acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AcquireMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ )
++{
++#if gcdDETECT_TIMEOUT
++ gctUINT32 timeout;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x Timeout=%u", Os, Mutex, Timeout);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++#if gcdDETECT_TIMEOUT
++ timeout = 0;
++
++ for (;;)
++ {
++ /* Try to acquire the mutex. */
++ if (mutex_trylock(Mutex))
++ {
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Advance the timeout. */
++ timeout += 1;
++
++ if (Timeout == gcvINFINITE)
++ {
++ if (timeout == gcdINFINITE_TIMEOUT)
++ {
++ gctUINT32 dmaAddress1, dmaAddress2;
++ gctUINT32 dmaState1, dmaState2;
++
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkVERIFY_OK(_VerifyDMA(
++ Os, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++#if gcdDETECT_DMA_ADDRESS
++ /* Dump only if DMA appears stuck. */
++ if (
++ (dmaAddress1 == dmaAddress2)
++#if gcdDETECT_DMA_STATE
++ && (dmaState1 == dmaState2)
++# endif
++ )
++# endif
++ {
++ gcmkVERIFY_OK(_DumpGPUState(Os, gcvCORE_MAJOR));
++
++ gcmkPRINT(
++ "%s(%d): mutex 0x%X; forced message flush.",
++ __FUNCTION__, __LINE__, Mutex
++ );
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(dmaAddress2);
++ }
++
++ timeout = 0;
++ }
++ }
++ else
++ {
++ /* Timedout? */
++ if (timeout >= Timeout)
++ {
++ break;
++ }
++ }
++
++ /* Wait for 1 millisecond. */
++ gcmkVERIFY_OK(gckOS_Delay(Os, 1));
++ }
++#else
++ if (Timeout == gcvINFINITE)
++ {
++ /* Lock the mutex. */
++ mutex_lock(Mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ for (;;)
++ {
++ /* Try to acquire the mutex. */
++ if (mutex_trylock(Mutex))
++ {
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ if (Timeout-- == 0)
++ {
++ break;
++ }
++
++ /* Wait for 1 millisecond. */
++ gcmkVERIFY_OK(gckOS_Delay(Os, 1));
++ }
++#endif
++
++ /* Timeout. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_TIMEOUT);
++ return gcvSTATUS_TIMEOUT;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReleaseMutex
++**
++** Release an acquired mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mutex to be released.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ReleaseMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x", Os, Mutex);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Release the mutex. */
++ mutex_unlock(Mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicExchange
++**
++** Atomically exchange a pair of 32-bit values.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN OUT gctINT32_PTR Target
++** Pointer to the 32-bit value to exchange.
++**
++** IN gctINT32 NewValue
++** Specifies a new value for the 32-bit value pointed to by Target.
++**
++** OUT gctINT32_PTR OldValue
++** The old value of the 32-bit value pointed to by Target.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomicExchange(
++ IN gckOS Os,
++ IN OUT gctUINT32_PTR Target,
++ IN gctUINT32 NewValue,
++ OUT gctUINT32_PTR OldValue
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=%u", Os, Target, NewValue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ /* Exchange the pair of 32-bit values. */
++ *OldValue = (gctUINT32) atomic_xchg((atomic_t *) Target, (int) NewValue);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*OldValue=%u", *OldValue);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicExchangePtr
++**
++** Atomically exchange a pair of pointers.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN OUT gctPOINTER * Target
++** Pointer to the 32-bit value to exchange.
++**
++** IN gctPOINTER NewValue
++** Specifies a new value for the pointer pointed to by Target.
++**
++** OUT gctPOINTER * OldValue
++** The old value of the pointer pointed to by Target.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomicExchangePtr(
++ IN gckOS Os,
++ IN OUT gctPOINTER * Target,
++ IN gctPOINTER NewValue,
++ OUT gctPOINTER * OldValue
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=0x%X", Os, Target, NewValue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ /* Exchange the pair of pointers. */
++ *OldValue = (gctPOINTER)(gctUINTPTR_T) atomic_xchg((atomic_t *) Target, (int)(gctUINTPTR_T) NewValue);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*OldValue=0x%X", *OldValue);
++ return gcvSTATUS_OK;
++}
++
++#if gcdSMP
++/*******************************************************************************
++**
++** gckOS_AtomicSetMask
++**
++** Atomically set mask to Atom
++**
++** INPUT:
++** IN OUT gctPOINTER Atom
++** Pointer to the atom to set.
++**
++** IN gctUINT32 Mask
++** Mask to set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSetMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ )
++{
++ gctUINT32 oval, nval;
++
++ gcmkHEADER_ARG("Atom=0x%0x", Atom);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ do
++ {
++ oval = atomic_read((atomic_t *) Atom);
++ nval = oval | Mask;
++ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomClearMask
++**
++** Atomically clear mask from Atom
++**
++** INPUT:
++** IN OUT gctPOINTER Atom
++** Pointer to the atom to clear.
++**
++** IN gctUINT32 Mask
++** Mask to clear.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomClearMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ )
++{
++ gctUINT32 oval, nval;
++
++ gcmkHEADER_ARG("Atom=0x%0x", Atom);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ do
++ {
++ oval = atomic_read((atomic_t *) Atom);
++ nval = oval & ~Mask;
++ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_AtomConstruct
++**
++** Create an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Atom
++** Pointer to a variable receiving the constructed atom.
++*/
++gceSTATUS
++gckOS_AtomConstruct(
++ IN gckOS Os,
++ OUT gctPOINTER * Atom
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Allocate the atom. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(atomic_t), Atom));
++
++ /* Initialize the atom. */
++ atomic_set((atomic_t *) *Atom, 0);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Atom=0x%X", *Atom);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomDestroy
++**
++** Destroy an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomDestroy(
++ IN gckOS Os,
++ OUT gctPOINTER Atom
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Free the atom. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Os, Atom));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomGet
++**
++** Get the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the value of the atom.
++*/
++gceSTATUS
++gckOS_AtomGet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Return the current value of atom. */
++ *Value = atomic_read((atomic_t *) Atom);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomSet
++**
++** Set the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** gctINT32 Value
++** The value of the atom.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ IN gctINT32 Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x Value=%d", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Set the current value of atom. */
++ atomic_set((atomic_t *) Atom, Value);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomIncrement
++**
++** Atomically increment the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable that receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomIncrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Increment the atom. */
++ *Value = atomic_inc_return((atomic_t *) Atom) - 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomDecrement
++**
++** Atomically decrement the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable that receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomDecrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Decrement the atom. */
++ *Value = atomic_dec_return((atomic_t *) Atom) + 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Delay
++**
++** Delay execution of the current thread for a number of milliseconds.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Delay
++** Delay to sleep, specified in milliseconds.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Delay(
++ IN gckOS Os,
++ IN gctUINT32 Delay
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Delay=%u", Os, Delay);
++
++ if (Delay > 0)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)
++ ktime_t delay = ktime_set(Delay/1000, (Delay%1000) * NSEC_PER_MSEC);
++ __set_current_state(TASK_UNINTERRUPTIBLE);
++ schedule_hrtimeout(&delay, HRTIMER_MODE_REL);
++#else
++ msleep(Delay);
++#endif
++
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetTicks
++**
++** Get the number of milliseconds since the system started.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gctUINT32_PTR Time
++** Pointer to a variable to get time.
++**
++*/
++gceSTATUS
++gckOS_GetTicks(
++ OUT gctUINT32_PTR Time
++ )
++{
++ gcmkHEADER();
++
++ *Time = jiffies_to_msecs(jiffies);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_TicksAfter
++**
++** Compare time values got from gckOS_GetTicks.
++**
++** INPUT:
++** gctUINT32 Time1
++** First time value to be compared.
++**
++** gctUINT32 Time2
++** Second time value to be compared.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR IsAfter
++** Pointer to a variable to result.
++**
++*/
++gceSTATUS
++gckOS_TicksAfter(
++ IN gctUINT32 Time1,
++ IN gctUINT32 Time2,
++ OUT gctBOOL_PTR IsAfter
++ )
++{
++ gcmkHEADER();
++
++ *IsAfter = time_after((unsigned long)Time1, (unsigned long)Time2);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetTime
++**
++** Get the number of microseconds since the system started.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gctUINT64_PTR Time
++** Pointer to a variable to get time.
++**
++*/
++gceSTATUS
++gckOS_GetTime(
++ OUT gctUINT64_PTR Time
++ )
++{
++ gcmkHEADER();
++
++ *Time = 0;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MemoryBarrier
++**
++** Make sure the CPU has executed everything up to this point and the data got
++** written to the specified pointer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Address
++** Address of memory that needs to be barriered.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_MemoryBarrier(
++ IN gckOS Os,
++ IN gctPOINTER Address
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Address=0x%X", Os, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++#if gcdNONPAGED_MEMORY_BUFFERABLE \
++ && defined (CONFIG_ARM) \
++ && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34))
++ /* drain write buffer */
++ dsb();
++
++ /* drain outer cache's write buffer? */
++#else
++ mb();
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocatePagedMemory
++**
++** Allocate memory from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocatePagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++
++ /* Allocate the memory. */
++ gcmkONERROR(gckOS_AllocatePagedMemoryEx(Os, gcvFALSE, Bytes, Physical));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Physical=0x%X", *Physical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocatePagedMemoryEx
++**
++** Allocate memory from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL Contiguous
++** Need contiguous memory or not.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocatePagedMemoryEx(
++ IN gckOS Os,
++ IN gctBOOL Contiguous,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ )
++{
++ gctINT numPages;
++ gctINT i;
++ PLINUX_MDL mdl = gcvNULL;
++ gctSIZE_T bytes;
++ gctBOOL locked = gcvFALSE;
++ gceSTATUS status;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ gctPOINTER addr = gcvNULL;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%X Contiguous=%d Bytes=%lu", Os, Contiguous, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++
++ bytes = gcmALIGN(Bytes, PAGE_SIZE);
++
++ numPages = GetPageCount(bytes, 0);
++
++ MEMORY_LOCK(Os);
++ locked = gcvTRUE;
++
++ mdl = _CreateMdl(_GetProcessID());
++ if (mdl == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (Contiguous)
++ {
++ gctUINT32 order = get_order(bytes);
++
++ if (order >= MAX_ORDER)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ addr =
++ alloc_pages_exact(numPages * PAGE_SIZE, GFP_KERNEL | gcdNOWARN | __GFP_NORETRY);
++
++ mdl->u.contiguousPages = addr
++ ? virt_to_page(addr)
++ : gcvNULL;
++
++ mdl->exact = gcvTRUE;
++#else
++ mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | gcdNOWARN | __GFP_NORETRY, order);
++#endif
++ if (mdl->u.contiguousPages == gcvNULL)
++ {
++ mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN, order);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ mdl->exact = gcvFALSE;
++#endif
++ }
++ }
++ else
++ {
++ mdl->u.nonContiguousPages = _NonContiguousAlloc(numPages);
++ }
++
++ if (mdl->u.contiguousPages == gcvNULL && mdl->u.nonContiguousPages == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mdl->dmaHandle = 0;
++ mdl->addr = 0;
++ mdl->numPages = numPages;
++ mdl->pagedMem = 1;
++ mdl->contiguous = Contiguous;
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ struct page *page;
++
++ if (mdl->contiguous)
++ {
++ page = nth_page(mdl->u.contiguousPages, i);
++ }
++ else
++ {
++ page = _NonContiguousToPage(mdl->u.nonContiguousPages, i);
++ }
++
++ SetPageReserved(page);
++
++ if (!PageHighMem(page) && page_to_phys(page))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL,
++ (gctPOINTER)(gctUINTPTR_T)page_to_phys(page),
++ page_address(page),
++ PAGE_SIZE));
++ }
++ }
++
++ /* Return physical address. */
++ *Physical = (gctPHYS_ADDR) mdl;
++
++ /*
++ * Add this to a global list.
++ * Will be used by get physical address
++ * and mapuser pointer functions.
++ */
++ if (!Os->mdlHead)
++ {
++ /* Initialize the queue. */
++ Os->mdlHead = Os->mdlTail = mdl;
++ }
++ else
++ {
++ /* Add to tail. */
++ mdl->prev = Os->mdlTail;
++ Os->mdlTail->next = mdl;
++ Os->mdlTail = mdl;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Physical=0x%X", *Physical);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mdl != gcvNULL)
++ {
++ /* Free the memory. */
++ _DestroyMdl(mdl);
++ }
++
++ if (locked)
++ {
++ /* Unlock the memory. */
++ MEMORY_UNLOCK(Os);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreePagedMemory
++**
++** Free memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreePagedMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes
++ )
++{
++ PLINUX_MDL mdl = (PLINUX_MDL) Physical;
++ gctINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /*addr = mdl->addr;*/
++
++ MEMORY_LOCK(Os);
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ if (mdl->contiguous)
++ {
++ ClearPageReserved(nth_page(mdl->u.contiguousPages, i));
++ }
++ else
++ {
++ ClearPageReserved(_NonContiguousToPage(mdl->u.nonContiguousPages, i));
++ }
++ }
++
++ if (mdl->contiguous)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ if (mdl->exact == gcvTRUE)
++ {
++ free_pages_exact(page_address(mdl->u.contiguousPages), mdl->numPages * PAGE_SIZE);
++ }
++ else
++#endif
++ {
++ __free_pages(mdl->u.contiguousPages, GetOrder(mdl->numPages));
++ }
++ }
++ else
++ {
++ _NonContiguousFree(mdl->u.nonContiguousPages, mdl->numPages);
++ }
++
++ /* Remove the node from global list. */
++ if (mdl == Os->mdlHead)
++ {
++ if ((Os->mdlHead = mdl->next) == gcvNULL)
++ {
++ Os->mdlTail = gcvNULL;
++ }
++ }
++ else
++ {
++ mdl->prev->next = mdl->next;
++
++ if (mdl == Os->mdlTail)
++ {
++ Os->mdlTail = mdl->prev;
++ }
++ else
++ {
++ mdl->next->prev = mdl->prev;
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Free the structure... */
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_LockPages
++**
++** Lock memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** gctBOOL Cacheable
++** Cache mode of mapping.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the address of the mapped
++** memory.
++**
++** gctSIZE_T * PageCount
++** Pointer to a variable that receives the number of pages required for
++** the page table according to the GPU page size.
++*/
++gceSTATUS
++gckOS_LockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Cacheable,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ )
++{
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++ gctSTRING addr;
++ unsigned long start;
++ unsigned long pfn;
++ gctINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount != gcvNULL);
++
++ mdl = (PLINUX_MDL) Physical;
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = FindMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++
++ if (mdlMap->vmaAddr == gcvNULL)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr,
++ (gctUINT32)(gctUINTPTR_T)mdl
++ );
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++
++ if (Cacheable == gcvFALSE)
++ {
++ /* Make this mapping non-cached. */
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ }
++
++ addr = mdl->addr;
++
++ /* Now map all the vmalloc pages to this user address. */
++ if (mdl->contiguous)
++ {
++ /* map kernel memory to user space.. */
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ page_to_pfn(mdl->u.contiguousPages),
++ mdlMap->vma->vm_end - mdlMap->vma->vm_start,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): unable to mmap ret",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++ else
++ {
++ start = mdlMap->vma->vm_start;
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ pfn = _NonContiguousToPfn(mdl->u.nonContiguousPages, i);
++
++ if (remap_pfn_range(mdlMap->vma,
++ start,
++ pfn,
++ PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): gctPHYS_ADDR->0x%X Logical->0x%X Unable to map addr->0x%X to start->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)Physical,
++ (gctUINT32)(gctUINTPTR_T)*Logical,
++ (gctUINT32)(gctUINTPTR_T)addr,
++ (gctUINT32)(gctUINTPTR_T)start
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ start += PAGE_SIZE;
++ addr += PAGE_SIZE;
++ }
++ }
++
++ up_write(&current->mm->mmap_sem);
++ }
++
++#if 0
++ else
++ {
++ /* mdlMap->vmaAddr != gcvNULL means current process has already locked this node. */
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d, mdlMap->vmaAddr=%x", gcvSTATUS_MEMORY_LOCKED, mdlMap->vmaAddr);
++ return gcvSTATUS_MEMORY_LOCKED;
++ }
++#endif
++
++ /* Convert pointer to MDL. */
++ *Logical = mdlMap->vmaAddr;
++
++ /* Return the page number according to the GPU page size. */
++ gcmkASSERT((PAGE_SIZE % 4096) == 0);
++ gcmkASSERT((PAGE_SIZE / 4096) >= 1);
++
++ *PageCount = mdl->numPages * (PAGE_SIZE / 4096);
++
++ /* Increase reference count. */
++ mdlMap->reference++;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkVERIFY_OK(gckOS_CacheFlush(
++ Os,
++ _GetProcessID(),
++ Physical,
++ gcvNULL,
++ (gctPOINTER)mdlMap->vmaAddr,
++ mdl->numPages * PAGE_SIZE
++ ));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=0x%X *PageCount=%lu", *Logical, *PageCount);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapPages
++**
++** Map paged memory into a page table.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T PageCount
++** Number of pages required for the physical address.
++**
++** gctPOINTER PageTable
++** Pointer to the page table to fill in.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_MapPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ )
++{
++ return gckOS_MapPagesEx(Os,
++ gcvCORE_MAJOR,
++ Physical,
++ PageCount,
++ PageTable);
++}
++
++gceSTATUS
++gckOS_MapPagesEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ PLINUX_MDL mdl;
++ gctUINT32* table;
++ gctUINT32 offset;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gckMMU mmu;
++ PLINUX_MDL mmuMdl;
++ gctUINT32 bytes;
++ gctPHYS_ADDR pageTablePhysical;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Physical=0x%X PageCount=%u PageTable=0x%X",
++ Os, Core, Physical, PageCount, PageTable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++
++ /* Convert pointer to MDL. */
++ mdl = (PLINUX_MDL)Physical;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Physical->0x%X PageCount->0x%X PagedMemory->?%d",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)Physical,
++ (gctUINT32)(gctUINTPTR_T)PageCount,
++ mdl->pagedMem
++ );
++
++ MEMORY_LOCK(Os);
++
++ table = (gctUINT32 *)PageTable;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ mmu = Os->device->kernels[Core]->mmu;
++ bytes = PageCount * sizeof(*table);
++ mmuMdl = (PLINUX_MDL)mmu->pageTablePhysical;
++#endif
++
++ /* Get all the physical addresses and store them in the page table. */
++
++ offset = 0;
++
++ if (mdl->pagedMem)
++ {
++ /* Try to get the user pages so DMA can happen. */
++ while (PageCount-- > 0)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ if (mdl->contiguous)
++ {
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ page_to_phys(nth_page(mdl->u.contiguousPages, offset)),
++ table));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ _NonContiguousToPhys(mdl->u.nonContiguousPages, offset),
++ table));
++ }
++ }
++ else
++#endif
++ {
++ if (mdl->contiguous)
++ {
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ page_to_phys(nth_page(mdl->u.contiguousPages, offset)),
++ table));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ _NonContiguousToPhys(mdl->u.nonContiguousPages, offset),
++ table));
++ }
++ }
++
++ table++;
++ offset += 1;
++ }
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): we should not get this call for Non Paged Memory!",
++ __FUNCTION__, __LINE__
++ );
++
++ while (PageCount-- > 0)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ page_to_phys(nth_page(mdl->u.contiguousPages, offset)),
++ table));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ page_to_phys(nth_page(mdl->u.contiguousPages, offset)),
++ table));
++ }
++ table++;
++ offset += 1;
++ }
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Get physical address of pageTable */
++ pageTablePhysical = (gctPHYS_ADDR)(mmuMdl->dmaHandle +
++ ((gctUINT32 *)PageTable - mmu->pageTableLogical));
++
++ /* Flush the mmu page table cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Os,
++ _GetProcessID(),
++ gcvNULL,
++ pageTablePhysical,
++ PageTable,
++ bytes
++ ));
++#endif
++
++OnError:
++
++ MEMORY_UNLOCK(Os);
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnlockPages
++**
++** Unlock memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** gctPOINTER Logical
++** Address of the mapped memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnlockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%u Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Make sure there is already a mapping...*/
++ gcmkVERIFY_ARGUMENT(mdl->u.nonContiguousPages != gcvNULL
++ || mdl->u.contiguousPages != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if ((mdlMap->vmaAddr != gcvNULL) && (_GetProcessID() == mdlMap->pid))
++ {
++ if (--mdlMap->reference > 0)
++ {
++ continue;
++ }
++
++ _UnmapUserLogical(mdlMap->pid, mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE);
++ mdlMap->vmaAddr = gcvNULL;
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckOS_AllocateContiguous
++**
++** Allocate memory from the contiguous pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the pages need to be mapped into user space.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that receives the number of bytes allocated.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the logical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocateContiguous(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ Os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Same as non-paged memory for now. */
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(Os,
++ InUserSpace,
++ Bytes,
++ Physical,
++ Logical));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X",
++ *Bytes, *Physical, *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeContiguous
++**
++** Free memory allocated from the contiguous pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctPOINTER Logical
++** Logicval address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreeContiguous(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Logical=0x%X Bytes=%lu",
++ Os, Physical, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Same of non-paged memory for now. */
++ gcmkONERROR(gckOS_FreeNonPagedMemory(Os, Bytes, Physical, Logical));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_VG
++/******************************************************************************
++**
++** gckOS_GetKernelLogical
++**
++** Return the kernel logical pointer that corresponods to the specified
++** hardware address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Hardware physical address.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to a variable receiving the pointer in kernel address space.
++*/
++gceSTATUS
++gckOS_GetKernelLogical(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ return gckOS_GetKernelLogicalEx(Os, gcvCORE_MAJOR, Address, KernelPointer);
++}
++
++gceSTATUS
++gckOS_GetKernelLogicalEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%08x", Os, Core, Address);
++
++ do
++ {
++ gckGALDEVICE device;
++ gckKERNEL kernel;
++ gcePOOL pool;
++ gctUINT32 offset;
++ gctPOINTER logical;
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Os->device;
++
++ /* Kernel shortcut. */
++ kernel = device->kernels[Core];
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkERR_BREAK(gckVGHARDWARE_SplitMemory(
++ kernel->vg->hardware, Address, &pool, &offset
++ ));
++ }
++ else
++#endif
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkERR_BREAK(gckHARDWARE_SplitMemory(
++ kernel->hardware, Address, &pool, &offset
++ ));
++ }
++
++ /* Dispatch on pool. */
++ switch (pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ logical = device->internalLogical;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ logical = device->externalLogical;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ logical = device->contiguousBase;
++ break;
++
++ default:
++ /* Invalid memory pool. */
++ gcmkFOOTER();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Build logical address of specified address. */
++ * KernelPointer = ((gctUINT8_PTR) logical) + offset;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer);
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_MapUserPointer
++**
++** Map a pointer from the user process into the kernel address space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Pointer
++** Pointer in user process space that needs to be mapped.
++**
++** gctSIZE_T Size
++** Number of bytes that need to be mapped.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to a variable receiving the mapped pointer in kernel address
++** space.
++*/
++gceSTATUS
++gckOS_MapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gctPOINTER buf = gcvNULL;
++ gctUINT32 len;
++
++ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu", Os, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++
++ buf = kmalloc(Size, GFP_KERNEL | gcdNOWARN);
++ if (buf == gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to allocate memory.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ len = copy_from_user(buf, Pointer, Size);
++ if (len != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to copy data from user.",
++ __FUNCTION__, __LINE__
++ );
++
++ if (buf != gcvNULL)
++ {
++ kfree(buf);
++ }
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_GENERIC_IO);
++ return gcvSTATUS_GENERIC_IO;
++ }
++
++ *KernelPointer = buf;
++
++ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserPointer
++**
++** Unmap a user process pointer from the kernel address space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Pointer
++** Pointer in user process space that needs to be unmapped.
++**
++** gctSIZE_T Size
++** Number of bytes that need to be unmapped.
++**
++** gctPOINTER KernelPointer
++** Pointer in kernel address space that needs to be unmapped.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ IN gctPOINTER KernelPointer
++ )
++{
++ gctUINT32 len;
++
++ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu KernelPointer=0x%X",
++ Os, Pointer, Size, KernelPointer);
++
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++
++ len = copy_to_user(Pointer, KernelPointer, Size);
++
++ kfree(KernelPointer);
++
++ if (len != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to copy data to user.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_GENERIC_IO);
++ return gcvSTATUS_GENERIC_IO;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_QueryNeedCopy
++**
++** Query whether the memory can be accessed or mapped directly or it has to be
++** copied.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID of the current process.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR NeedCopy
++** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or
++** gcvFALSE if the memory can be accessed or mapped dircetly.
++*/
++gceSTATUS
++gckOS_QueryNeedCopy(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ OUT gctBOOL_PTR NeedCopy
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d", Os, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(NeedCopy != gcvNULL);
++
++ /* We need to copy data. */
++ *NeedCopy = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedCopy=%d", *NeedCopy);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyFromUserData
++**
++** Copy data from user to kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyFromUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu",
++ Os, KernelPointer, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Copy data from user. */
++ if (copy_from_user(KernelPointer, Pointer, Size) != 0)
++ {
++ /* Could not copy all the bytes. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyToUserData
++**
++** Copy data from kernel to user memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyToUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu",
++ Os, KernelPointer, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Copy data to user. */
++ if (copy_to_user(Pointer, KernelPointer, Size) != 0)
++ {
++ /* Could not copy all the bytes. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_WriteMemory
++**
++** Write data to a memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Address
++** Address of the memory to write to.
++**
++** gctUINT32 Data
++** Data for register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WriteMemory(
++ IN gckOS Os,
++ IN gctPOINTER Address,
++ IN gctUINT32 Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Os=0x%X Address=0x%X Data=%u", Os, Address, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Write memory. */
++ if (access_ok(VERIFY_WRITE, Address, 4))
++ {
++ /* User address. */
++ if(put_user(Data, (gctUINT32*)Address))
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ADDRESS);
++ }
++ }
++ else
++ {
++ /* Kernel address. */
++ *(gctUINT32 *)Address = Data;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapUserMemory
++**
++** Lock down a user buffer and return an DMA'able address to be used by the
++** hardware to access it.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory to lock down.
++**
++** gctSIZE_T Size
++** Size in bytes of the memory to lock down.
++**
++** OUTPUT:
++**
++** gctPOINTER * Info
++** Pointer to variable receiving the information record required by
++** gckOS_UnmapUserMemory.
++**
++** gctUINT32_PTR Address
++** Pointer to a variable that will receive the address DMA'able by the
++** hardware.
++*/
++gceSTATUS
++gckOS_MapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%x Core=%d Memory=0x%x Size=%lu", Os, Core, Memory, Size);
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckOS_AddMapping(Os, *Address, Memory, Size));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++#else
++{
++ gctSIZE_T pageCount, i, j;
++ gctUINT32_PTR pageTable;
++ gctUINT32 address = 0, physical = ~0U;
++ gctUINTPTR_T start, end, memory;
++ gctUINT32 offset;
++ gctINT result = 0;
++
++ gcsPageInfo_PTR info = gcvNULL;
++ struct page **pages = gcvNULL;
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL || Physical != ~0U);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ memory = (gctUINTPTR_T) Memory;
++
++ /* Get the number of required pages. */
++ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ start = memory >> PAGE_SHIFT;
++ pageCount = end - start;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pageCount: %d.",
++ __FUNCTION__, __LINE__,
++ pageCount
++ );
++
++ /* Overflow. */
++ if ((memory + Size) < memory)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ MEMORY_MAP_LOCK(Os);
++
++ /* Allocate the Info struct. */
++ info = (gcsPageInfo_PTR)kmalloc(sizeof(gcsPageInfo), GFP_KERNEL | gcdNOWARN);
++
++ if (info == gcvNULL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ /* Allocate the array of page addresses. */
++ pages = (struct page **)kmalloc(pageCount * sizeof(struct page *), GFP_KERNEL | gcdNOWARN);
++
++ if (pages == gcvNULL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ if (Physical != ~0U)
++ {
++ for (i = 0; i < pageCount; i++)
++ {
++ pages[i] = pfn_to_page((Physical >> PAGE_SHIFT) + i);
++ get_page(pages[i]);
++ }
++ }
++ else
++ {
++ /* Get the user pages. */
++ down_read(&current->mm->mmap_sem);
++
++ result = get_user_pages(current,
++ current->mm,
++ memory & PAGE_MASK,
++ pageCount,
++ 1,
++ 0,
++ pages,
++ gcvNULL
++ );
++
++ up_read(&current->mm->mmap_sem);
++
++ if (result <=0 || result < pageCount)
++ {
++ struct vm_area_struct *vma;
++
++ /* Release the pages if any. */
++ if (result > 0)
++ {
++ for (i = 0; i < result; i++)
++ {
++ if (pages[i] == gcvNULL)
++ {
++ break;
++ }
++
++ page_cache_release(pages[i]);
++ pages[i] = gcvNULL;
++ }
++
++ result = 0;
++ }
++
++ vma = find_vma(current->mm, memory);
++
++ if (vma && (vma->vm_flags & VM_PFNMAP))
++ {
++ pte_t * pte;
++ spinlock_t * ptl;
++ gctUINTPTR_T logical = memory;
++
++ for (i = 0; i < pageCount; i++)
++ {
++ pgd_t * pgd = pgd_offset(current->mm, logical);
++ pud_t * pud = pud_offset(pgd, logical);
++
++ if (pud)
++ {
++ pmd_t * pmd = pmd_offset(pud, logical);
++ pte = pte_offset_map_lock(current->mm, pmd, logical, &ptl);
++ if (!pte)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ pages[i] = pte_page(*pte);
++ pte_unmap_unlock(pte, ptl);
++
++ /* Advance to next. */
++ logical += PAGE_SIZE;
++ }
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Check if this memory is contiguous for old mmu. */
++ if (Os->device->kernels[Core]->hardware->mmuVersion == 0)
++ {
++ for (i = 1; i < pageCount; i++)
++ {
++ if (pages[i] != nth_page(pages[0], i))
++ {
++ /* Non-contiguous. */
++ break;
++ }
++ }
++
++ if (i == pageCount)
++ {
++ /* Contiguous memory. */
++ physical = page_to_phys(pages[0]) | (memory & ~PAGE_MASK);
++
++ if (!((physical - Os->device->baseAddress) & 0x80000000))
++ {
++ kfree(pages);
++ pages = gcvNULL;
++
++ info->pages = gcvNULL;
++ info->pageTable = gcvNULL;
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ *Address = physical - Os->device->baseAddress;
++ *Info = info;
++
++ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x",
++ *Info, *Address);
++
++ return gcvSTATUS_OK;
++ }
++ }
++ }
++
++ /* Reference pages. */
++ for (i = 0; i < pageCount; i++)
++ {
++ get_page(pages[i]);
++ }
++ }
++ }
++
++ for (i = 0; i < pageCount; i++)
++ {
++#ifdef CONFIG_ARM
++ gctUINT32 data;
++ get_user(data, (gctUINT32*)((memory & PAGE_MASK) + i * PAGE_SIZE));
++#endif
++
++ /* Flush(clean) the data cache. */
++ gcmkONERROR(gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL,
++ (gctPOINTER)(gctUINTPTR_T)page_to_phys(pages[i]),
++ (gctPOINTER)(memory & PAGE_MASK) + i*PAGE_SIZE,
++ PAGE_SIZE));
++ }
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckVGMMU_AllocatePages(Os->device->kernels[Core]->vg->mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++ }
++ else
++#endif
++ {
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckMMU_AllocatePages(Os->device->kernels[Core]->mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++ }
++
++ /* Fill the page table. */
++ for (i = 0; i < pageCount; i++)
++ {
++ gctUINT32 phys;
++ gctUINT32_PTR tab = pageTable + i * (PAGE_SIZE/4096);
++
++ phys = page_to_phys(pages[i]);
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Get the physical address from page struct. */
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ phys,
++ tab));
++ }
++ else
++#endif
++ {
++ /* Get the physical address from page struct. */
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ phys,
++ tab));
++ }
++
++ for (j = 1; j < (PAGE_SIZE/4096); j++)
++ {
++ pageTable[i * (PAGE_SIZE/4096) + j] = pageTable[i * (PAGE_SIZE/4096)] + 4096 * j;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pageTable[%d]: 0x%X 0x%X.",
++ __FUNCTION__, __LINE__,
++ i, phys, pageTable[i]);
++ }
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkONERROR(gckVGMMU_Flush(Os->device->kernels[Core]->vg->mmu));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckMMU_Flush(Os->device->kernels[Core]->mmu));
++ }
++
++ /* Save pointer to page table. */
++ info->pageTable = pageTable;
++ info->pages = pages;
++
++ *Info = (gctPOINTER) info;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): info->pages: 0x%X, info->pageTable: 0x%X, info: 0x%X.",
++ __FUNCTION__, __LINE__,
++ info->pages,
++ info->pageTable,
++ info
++ );
++
++ offset = (Physical != ~0U)
++ ? (Physical & ~PAGE_MASK)
++ : (memory & ~PAGE_MASK);
++
++ /* Return address. */
++ *Address = address + offset;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Address: 0x%X.",
++ __FUNCTION__, __LINE__,
++ *Address
++ );
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++OnError:
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error occured: %d.",
++ __FUNCTION__, __LINE__,
++ status
++ );
++
++ /* Release page array. */
++ if (result > 0 && pages != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: page table is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ for (i = 0; i < result; i++)
++ {
++ if (pages[i] == gcvNULL)
++ {
++ break;
++ }
++ page_cache_release(pages[i]);
++ }
++ }
++
++ if (info!= gcvNULL && pages != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: pages is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Free the page table. */
++ kfree(pages);
++ info->pages = gcvNULL;
++ }
++
++ /* Release page info struct. */
++ if (info != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: info is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Free the page info struct. */
++ kfree(info);
++ *Info = gcvNULL;
++ }
++ }
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ /* Return the status. */
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x", *Info, *Address);
++ }
++ else
++ {
++ gcmkFOOTER();
++ }
++
++ return status;
++}
++#endif
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserMemory
++**
++** Unlock a user buffer and that was previously locked down by
++** gckOS_MapUserMemory.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory to unlock.
++**
++** gctSIZE_T Size
++** Size in bytes of the memory to unlock.
++**
++** gctPOINTER Info
++** Information record returned by gckOS_MapUserMemory.
++**
++** gctUINT32_PTR Address
++** The address returned by gckOS_MapUserMemory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Memory=0x%X Size=%lu Info=0x%X Address0x%08x",
++ Os, Core, Memory, Size, Info, Address);
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckOS_RemoveMapping(Os, Memory, Size));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++#else
++{
++ gctUINTPTR_T memory, start, end;
++ gcsPageInfo_PTR info;
++ gctSIZE_T pageCount, i;
++ struct page **pages;
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ do
++ {
++ info = (gcsPageInfo_PTR) Info;
++
++ pages = info->pages;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): info=0x%X, pages=0x%X.",
++ __FUNCTION__, __LINE__,
++ info, pages
++ );
++
++ /* Invalid page array. */
++ if (pages == gcvNULL && info->pageTable == gcvNULL)
++ {
++ kfree(info);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ memory = (gctUINTPTR_T)Memory;
++ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ start = memory >> PAGE_SHIFT;
++ pageCount = end - start;
++
++ /* Overflow. */
++ if ((memory + Size) < memory)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): memory: 0x%X, pageCount: %d, pageTable: 0x%X.",
++ __FUNCTION__, __LINE__,
++ memory, pageCount, info->pageTable
++ );
++
++ MEMORY_MAP_LOCK(Os);
++
++ gcmkASSERT(info->pageTable != gcvNULL);
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Free the pages from the MMU. */
++ gcmkERR_BREAK(gckVGMMU_FreePages(Os->device->kernels[Core]->vg->mmu,
++ info->pageTable,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++ }
++ else
++#endif
++ {
++ /* Free the pages from the MMU. */
++ gcmkERR_BREAK(gckMMU_FreePages(Os->device->kernels[Core]->mmu,
++ info->pageTable,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++ }
++
++ /* Release the page cache. */
++ if (pages)
++ {
++ for (i = 0; i < pageCount; i++)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pages[%d]: 0x%X.",
++ __FUNCTION__, __LINE__,
++ i, pages[i]
++ );
++
++ if (!PageReserved(pages[i]))
++ {
++ SetPageDirty(pages[i]);
++ }
++
++ page_cache_release(pages[i]);
++ }
++ }
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ if (info != gcvNULL)
++ {
++ /* Free the page array. */
++ if (info->pages != gcvNULL)
++ {
++ kfree(info->pages);
++ }
++
++ kfree(info);
++ }
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++}
++
++/*******************************************************************************
++**
++** gckOS_GetBaseAddress
++**
++** Get the base address for the physical memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR BaseAddress
++** Pointer to a variable that will receive the base address.
++*/
++gceSTATUS
++gckOS_GetBaseAddress(
++ IN gckOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Return base address. */
++ *BaseAddress = Os->device->baseAddress;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_SuspendInterrupt(
++ IN gckOS Os
++ )
++{
++ return gckOS_SuspendInterruptEx(Os, gcvCORE_MAJOR);
++}
++
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ disable_irq(Os->device->irqLines[Core]);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_ResumeInterrupt(
++ IN gckOS Os
++ )
++{
++ return gckOS_ResumeInterruptEx(Os, gcvCORE_MAJOR);
++}
++
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ enable_irq(Os->device->irqLines[Core]);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_MemCopy(
++ IN gctPOINTER Destination,
++ IN gctCONST_POINTER Source,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Destination=0x%X Source=0x%X Bytes=%lu",
++ Destination, Source, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Destination != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Source != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ memcpy(Destination, Source, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_ZeroMemory(
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Memory=0x%X Bytes=%lu", Memory, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ memset(Memory, 0, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************* Cache Control ********************************
++*******************************************************************************/
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED && defined(CONFIG_OUTER_CACHE)
++static inline gceSTATUS
++outer_func(
++ gceCACHEOPERATION Type,
++ unsigned long Start,
++ unsigned long End
++ )
++{
++ switch (Type)
++ {
++ case gcvCACHE_CLEAN:
++ outer_clean_range(Start, End);
++ break;
++ case gcvCACHE_INVALIDATE:
++ outer_inv_range(Start, End);
++ break;
++ case gcvCACHE_FLUSH:
++ outer_flush_range(Start, End);
++ break;
++ default:
++ return gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_OUTER_CACHE_PATCH
++/*******************************************************************************
++** _HandleOuterCache
++**
++** Handle the outer cache for the specified addresses.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Physical
++** Physical address to flush.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++**
++** gceOUTERCACHE_OPERATION Type
++** Operation need to be execute.
++*/
++static gceSTATUS
++_HandleOuterCache(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Type
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i, pageNum;
++ unsigned long paddr;
++ gctPOINTER vaddr;
++
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ if (Physical != gcvNULL)
++ {
++ /* Non paged memory or gcvPOOL_USER surface */
++ paddr = (unsigned long) Physical;
++ gcmkONERROR(outer_func(Type, paddr, paddr + Bytes));
++ }
++ else if ((Handle == gcvNULL)
++ || (Handle != gcvNULL && ((PLINUX_MDL)Handle)->contiguous)
++ )
++ {
++ /* Video Memory or contiguous virtual memory */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Os, Logical, (gctUINT32*)&paddr));
++ gcmkONERROR(outer_func(Type, paddr, paddr + Bytes));
++ }
++ else
++ {
++ /* Non contiguous virtual memory */
++ vaddr = (gctPOINTER)gcmALIGN_BASE((gctUINTPTR_T)Logical, PAGE_SIZE);
++ pageNum = GetPageCount(Bytes, 0);
++
++ for (i = 0; i < pageNum; i += 1)
++ {
++ gcmkONERROR(_ConvertLogical2Physical(
++ Os,
++ vaddr + PAGE_SIZE * i,
++ ProcessID,
++ (PLINUX_MDL)Handle,
++ (gctUINT32*)&paddr
++ ));
++
++ gcmkONERROR(outer_func(Type, paddr, paddr + PAGE_SIZE));
++ }
++ }
++
++ mb();
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++#endif
++
++/*******************************************************************************
++** gckOS_CacheClean
++**
++** Clean the cache for the specified addresses. The GPU is going to need the
++** data. If the system is allocating memory as non-cachable, this function can
++** be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Physical
++** Physical address to flush.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheClean(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++
++ /* Inner cache. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
++ dmac_map_area(Logical, Bytes, DMA_TO_DEVICE);
++# else
++ dmac_clean_range(Logical, Logical + Bytes);
++# endif
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, ProcessID, Handle, Physical, Logical, Bytes, gcvCACHE_CLEAN);
++#else
++ outer_clean_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++
++ dma_cache_wback((unsigned long) Logical, Bytes);
++
++#elif defined(CONFIG_PPC)
++
++ /* TODO */
++
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_TO_DEVICE);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** gckOS_CacheInvalidate
++**
++** Invalidate the cache for the specified addresses. The GPU is going to need
++** data. If the system is allocating memory as non-cachable, this function can
++** be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheInvalidate(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++
++ /* Inner cache. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
++ dmac_map_area(Logical, Bytes, DMA_FROM_DEVICE);
++# else
++ dmac_inv_range(Logical, Logical + Bytes);
++# endif
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, ProcessID, Handle, Physical, Logical, Bytes, gcvCACHE_INVALIDATE);
++#else
++ outer_inv_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++ dma_cache_inv((unsigned long) Logical, Bytes);
++#elif defined(CONFIG_PPC)
++ /* TODO */
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_FROM_DEVICE);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** gckOS_CacheFlush
++**
++** Clean the cache for the specified addresses and invalidate the lines as
++** well. The GPU is going to need and modify the data. If the system is
++** allocating memory as non-cachable, this function can be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheFlush(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++ /* Inner cache. */
++ dmac_flush_range(Logical, Logical + Bytes);
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, ProcessID, Handle, Physical, Logical, Bytes, gcvCACHE_FLUSH);
++#else
++ outer_flush_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++ dma_cache_wback_inv((unsigned long) Logical, Bytes);
++#elif defined(CONFIG_PPC)
++ /* TODO */
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_BIDIRECTIONAL);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************* Broadcasting *********************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_Broadcast
++**
++** System hook for broadcast events from the kernel driver.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gceBROADCAST Reason
++** Reason for the broadcast. Can be one of the following values:
++**
++** gcvBROADCAST_GPU_IDLE
++** Broadcasted when the kernel driver thinks the GPU might be
++** idle. This can be used to handle power management.
++**
++** gcvBROADCAST_GPU_COMMIT
++** Broadcasted when any client process commits a command
++** buffer. This can be used to handle power management.
++**
++** gcvBROADCAST_GPU_STUCK
++** Broadcasted when the kernel driver hits the timeout waiting
++** for the GPU.
++**
++** gcvBROADCAST_FIRST_PROCESS
++** First process is trying to connect to the kernel.
++**
++** gcvBROADCAST_LAST_PROCESS
++** Last process has detached from the kernel.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Broadcast(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gceBROADCAST Reason
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Hardware=0x%X Reason=%d", Os, Hardware, Reason);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ switch (Reason)
++ {
++ case gcvBROADCAST_FIRST_PROCESS:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "First process has attached");
++ break;
++
++ case gcvBROADCAST_LAST_PROCESS:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "Last process has detached");
++
++ /* Put GPU OFF. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware,
++ gcvPOWER_OFF_BROADCAST));
++ break;
++
++ case gcvBROADCAST_GPU_IDLE:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "GPU idle.");
++
++ /* Put GPU IDLE. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware,
++#if gcdPOWER_SUSNPEND_WHEN_IDLE
++ gcvPOWER_SUSPEND_BROADCAST));
++#else
++ gcvPOWER_IDLE_BROADCAST));
++#endif
++
++ /* Add idle process DB. */
++ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel,
++ 1,
++ gcvDB_IDLE,
++ gcvNULL, gcvNULL, 0));
++ break;
++
++ case gcvBROADCAST_GPU_COMMIT:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "COMMIT has arrived.");
++
++ /* Add busy process DB. */
++ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel,
++ 0,
++ gcvDB_IDLE,
++ gcvNULL, gcvNULL, 0));
++
++ /* Put GPU ON. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware, gcvPOWER_ON_AUTO));
++ break;
++
++ case gcvBROADCAST_GPU_STUCK:
++ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_GPU_STUCK\n");
++#if !gcdENABLE_RECOVERY
++ gcmkONERROR(gckHARDWARE_DumpGPUState(Hardware));
++#endif
++ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel));
++ break;
++
++ case gcvBROADCAST_AXI_BUS_ERROR:
++ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_AXI_BUS_ERROR\n");
++ gcmkONERROR(gckHARDWARE_DumpGPUState(Hardware));
++ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel));
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_BroadcastHurry
++**
++** The GPU is running too slow.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT Urgency
++** The higher the number, the higher the urgency to speed up the GPU.
++** The maximum value is defined by the gcdDYNAMIC_EVENT_THRESHOLD.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_BroadcastHurry(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Urgency
++ )
++{
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Urgency=%u", Os, Hardware, Urgency);
++
++ /* Do whatever you need to do to speed up the GPU now. */
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_BroadcastCalibrateSpeed
++**
++** Calibrate the speed of the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT Idle, Time
++** Idle/Time will give the percentage the GPU is idle, so you can use
++** this to calibrate the working point of the GPU.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_BroadcastCalibrateSpeed(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Idle,
++ IN gctUINT Time
++ )
++{
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Idle=%u Time=%u",
++ Os, Hardware, Idle, Time);
++
++ /* Do whatever you need to do to callibrate the GPU speed. */
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************** Semaphores **********************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_CreateSemaphore
++**
++** Create a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Semaphore
++** Pointer to the variable that will receive the created semaphore.
++*/
++gceSTATUS
++gckOS_CreateSemaphore(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ )
++{
++ gceSTATUS status;
++ struct semaphore *sem = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Allocate the semaphore structure. */
++ sem = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN);
++ if (sem == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the semaphore. */
++ sema_init(sem, 1);
++
++ /* Return to caller. */
++ *Semaphore = (gctPOINTER) sem;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AcquireSemaphore
++**
++** Acquire a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%08X Semaphore=0x%08X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Acquire the semaphore. */
++ if (down_interruptible((struct semaphore *) Semaphore))
++ {
++ gcmkONERROR(gcvSTATUS_INTERRUPTED);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_TryAcquireSemaphore
++**
++** Try to acquire a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_TryAcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Acquire the semaphore. */
++ if (down_trylock((struct semaphore *) Semaphore))
++ {
++ /* Timeout. */
++ status = gcvSTATUS_TIMEOUT;
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReleaseSemaphore
++**
++** Release a previously acquired semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be released.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ReleaseSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Release the semaphore. */
++ up((struct semaphore *) Semaphore);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroySemaphore
++**
++** Destroy a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroySemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Free the sempahore structure. */
++ kfree(Semaphore);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetProcessID
++**
++** Get current process ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ProcessID
++** Pointer to the variable that receives the process ID.
++*/
++gceSTATUS
++gckOS_GetProcessID(
++ OUT gctUINT32_PTR ProcessID
++ )
++{
++ /* Get process ID. */
++ if (ProcessID != gcvNULL)
++ {
++ *ProcessID = _GetProcessID();
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetThreadID
++**
++** Get current thread ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ThreadID
++** Pointer to the variable that receives the thread ID.
++*/
++gceSTATUS
++gckOS_GetThreadID(
++ OUT gctUINT32_PTR ThreadID
++ )
++{
++ /* Get thread ID. */
++ if (ThreadID != gcvNULL)
++ {
++ *ThreadID = _GetThreadID();
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetGPUPower
++**
++** Set the power of the GPU on or off.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctBOOL Clock
++** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock.
++**
++** gctBOOL Power
++** gcvTRUE to turn on the power, or gcvFALSE to turn off the power.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUPower(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctBOOL Clock,
++ IN gctBOOL Power
++ )
++{
++ struct clk *clk_3dcore = Os->device->clk_3d_core;
++ struct clk *clk_3dshader = Os->device->clk_3d_shader;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct clk *clk_3d_axi = Os->device->clk_3d_axi;
++#endif
++ struct clk *clk_2dcore = Os->device->clk_2d_core;
++ struct clk *clk_2d_axi = Os->device->clk_2d_axi;
++ struct clk *clk_vg_axi = Os->device->clk_vg_axi;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ int ret;
++#endif
++
++ gctBOOL oldClockState = gcvFALSE;
++ gctBOOL oldPowerState = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Clock=%d Power=%d", Os, Core, Clock, Power);
++
++ if (Os->device->kernels[Core] != NULL)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ oldClockState = Os->device->kernels[Core]->vg->hardware->clockState;
++ oldPowerState = Os->device->kernels[Core]->vg->hardware->powerState;
++ }
++ else
++ {
++#endif
++ oldClockState = Os->device->kernels[Core]->hardware->clockState;
++ oldPowerState = Os->device->kernels[Core]->hardware->powerState;
++#if gcdENABLE_VG
++ }
++#endif
++ }
++ if((Power == gcvTRUE) && (oldPowerState == gcvFALSE))
++ {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if(!IS_ERR(Os->device->gpu_regulator)) {
++ ret = regulator_enable(Os->device->gpu_regulator);
++ if (ret != 0)
++ gckOS_Print("%s(%d): fail to enable pu regulator %d!\n",
++ __FUNCTION__, __LINE__, ret);
++ }
++#else
++ imx_gpc_power_up_pu(true);
++#endif
++
++#ifdef CONFIG_PM
++ pm_runtime_get_sync(Os->device->pmdev);
++#endif
++ }
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (Clock == gcvTRUE) {
++ if (oldClockState == gcvFALSE) {
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ clk_enable(clk_3dcore);
++ if (cpu_is_mx6q())
++ clk_enable(clk_3dshader);
++ break;
++ case gcvCORE_2D:
++ clk_enable(clk_2dcore);
++ clk_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_enable(clk_2dcore);
++ clk_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++ } else {
++ if (oldClockState == gcvTRUE) {
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ if (cpu_is_mx6q())
++ clk_disable(clk_3dshader);
++ clk_disable(clk_3dcore);
++ break;
++ case gcvCORE_2D:
++ clk_disable(clk_2dcore);
++ clk_disable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_disable(clk_2dcore);
++ clk_disable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++ }
++#else
++ if (Clock == gcvTRUE) {
++ if (oldClockState == gcvFALSE) {
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ clk_prepare(clk_3dcore);
++ clk_enable(clk_3dcore);
++ clk_prepare(clk_3dshader);
++ clk_enable(clk_3dshader);
++ clk_prepare(clk_3d_axi);
++ clk_enable(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_prepare(clk_2dcore);
++ clk_enable(clk_2dcore);
++ clk_prepare(clk_2d_axi);
++ clk_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_prepare(clk_2dcore);
++ clk_enable(clk_2dcore);
++ clk_prepare(clk_vg_axi);
++ clk_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++ } else {
++ if (oldClockState == gcvTRUE) {
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ clk_disable(clk_3dshader);
++ clk_unprepare(clk_3dshader);
++ clk_disable(clk_3dcore);
++ clk_unprepare(clk_3dcore);
++ clk_disable(clk_3d_axi);
++ clk_unprepare(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_disable(clk_2dcore);
++ clk_unprepare(clk_2dcore);
++ clk_disable(clk_2d_axi);
++ clk_unprepare(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_disable(clk_2dcore);
++ clk_unprepare(clk_2dcore);
++ clk_disable(clk_vg_axi);
++ clk_unprepare(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++ }
++#endif
++ if((Power == gcvFALSE) && (oldPowerState == gcvTRUE))
++ {
++#ifdef CONFIG_PM
++ pm_runtime_put_sync(Os->device->pmdev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if(!IS_ERR(Os->device->gpu_regulator))
++ regulator_disable(Os->device->gpu_regulator);
++#else
++ imx_gpc_power_up_pu(false);
++#endif
++
++ }
++ /* TODO: Put your code here. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ResetGPU
++**
++** Reset the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ResetGPU(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++#define SRC_SCR_OFFSET 0
++#define BP_SRC_SCR_GPU3D_RST 1
++#define BP_SRC_SCR_GPU2D_RST 4
++ void __iomem *src_base = IO_ADDRESS(SRC_BASE_ADDR);
++ gctUINT32 bit_offset,val;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ if(Core == gcvCORE_MAJOR) {
++ bit_offset = BP_SRC_SCR_GPU3D_RST;
++ } else if((Core == gcvCORE_VG)
++ ||(Core == gcvCORE_2D)) {
++ bit_offset = BP_SRC_SCR_GPU2D_RST;
++ } else {
++ return gcvSTATUS_INVALID_CONFIG;
++ }
++ val = __raw_readl(src_base + SRC_SCR_OFFSET);
++ val &= ~(1 << (bit_offset));
++ val |= (1 << (bit_offset));
++ __raw_writel(val, src_base + SRC_SCR_OFFSET);
++
++ while ((__raw_readl(src_base + SRC_SCR_OFFSET) &
++ (1 << (bit_offset))) != 0) {
++ }
++
++ gcmkFOOTER_NO();
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct reset_control *rstc = Os->device->rstc[Core];
++ if (rstc)
++ reset_control_reset(rstc);
++#else
++ imx_src_reset_gpu((int)Core);
++#endif
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_PrepareGPUFrequency
++**
++** Prepare to set GPU frequency and voltage.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose frequency and voltage will be set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_PrepareGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_FinishGPUFrequency
++**
++** Finish GPU frequency setting.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose frequency and voltage is set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FinishGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_QueryGPUFrequency
++**
++** Query the current frequency of the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctUINT32 * Frequency
++** Pointer to a gctUINT32 to obtain current frequency, in MHz.
++**
++** gctUINT8 * Scale
++** Pointer to a gctUINT8 to obtain current scale(1 - 64).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_QueryGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 * Frequency,
++ OUT gctUINT8 * Scale
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetGPUFrequency
++**
++** Set frequency and voltage of the GPU.
++**
++** 1. DVFS manager gives the target scale of full frequency, BSP must find
++** a real frequency according to this scale and board's configure.
++**
++** 2. BSP should find a suitable voltage for this frequency.
++**
++** 3. BSP must make sure setting take effect before this function returns.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctUINT8 Scale
++** Target scale of full frequency, range is [1, 64]. 1 means 1/64 of
++** full frequency and 64 means 64/64 of full frequency.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT8 Scale
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*----------------------------------------------------------------------------*/
++/*----- Profile --------------------------------------------------------------*/
++
++gceSTATUS
++gckOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ )
++{
++ struct timespec time;
++
++ ktime_get_ts(&time);
++
++ *Tick = time.tv_nsec + time.tv_sec * 1000000000ULL;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ )
++{
++ struct timespec res;
++
++ hrtimer_get_res(CLOCK_MONOTONIC, &res);
++
++ *TickRate = res.tv_nsec + res.tv_sec * 1000000000ULL;
++
++ return gcvSTATUS_OK;
++}
++
++gctUINT32
++gckOS_ProfileToMS(
++ IN gctUINT64 Ticks
++ )
++{
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
++ return div_u64(Ticks, 1000000);
++#else
++ gctUINT64 rem = Ticks;
++ gctUINT64 b = 1000000;
++ gctUINT64 res, d = 1;
++ gctUINT32 high = rem >> 32;
++
++ /* Reduce the thing a bit first */
++ res = 0;
++ if (high >= 1000000)
++ {
++ high /= 1000000;
++ res = (gctUINT64) high << 32;
++ rem -= (gctUINT64) (high * 1000000) << 32;
++ }
++
++ while (((gctINT64) b > 0) && (b < rem))
++ {
++ b <<= 1;
++ d <<= 1;
++ }
++
++ do
++ {
++ if (rem >= b)
++ {
++ rem -= b;
++ res += d;
++ }
++
++ b >>= 1;
++ d >>= 1;
++ }
++ while (d);
++
++ return (gctUINT32) res;
++#endif
++}
++
++/******************************************************************************\
++******************************* Signal Management ******************************
++\******************************************************************************/
++
++#undef _GC_OBJ_ZONE
++#define _GC_OBJ_ZONE gcvZONE_SIGNAL
++
++/*******************************************************************************
++**
++** gckOS_CreateSignal
++**
++** Create a new signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL ManualReset
++** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in
++** order to set the signal to nonsignaled state.
++** If set to gcvFALSE, the signal will automatically be set to
++** nonsignaled state by gckOS_WaitSignal function.
++**
++** OUTPUT:
++**
++** gctSIGNAL * Signal
++** Pointer to a variable receiving the created gctSIGNAL.
++*/
++gceSTATUS
++gckOS_CreateSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X ManualReset=%d", Os, ManualReset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ /* Create an event structure. */
++ signal = (gcsSIGNAL_PTR) kmalloc(sizeof(gcsSIGNAL), GFP_KERNEL | gcdNOWARN);
++
++ if (signal == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Save the process ID. */
++ signal->process = (gctHANDLE)(gctUINTPTR_T) _GetProcessID();
++ signal->manualReset = ManualReset;
++ signal->hardware = gcvNULL;
++ init_completion(&signal->obj);
++ atomic_set(&signal->ref, 1);
++
++ gcmkONERROR(_AllocateIntegerId(&Os->signalDB, signal, &signal->id));
++
++ *Signal = (gctSIGNAL)(gctUINTPTR_T)signal->id;
++
++ gcmkFOOTER_ARG("*Signal=0x%X", *Signal);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (signal != gcvNULL)
++ {
++ kfree(signal);
++ }
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalQueryHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ *Hardware = signal->hardware;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalSetHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ signal->hardware = Hardware;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroySignal
++**
++** Destroy a signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroySignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X", Os, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ if (atomic_dec_and_test(&signal->ref))
++ {
++ gcmkVERIFY_OK(_DestroyIntegerId(&Os->signalDB, signal->id));
++
++ /* Free the sgianl. */
++ kfree(signal);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Signal
++**
++** Set a state of the specified signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctBOOL State
++** If gcvTRUE, the signal will be set to signaled state.
++** If gcvFALSE, the signal will be set to nonsignaled state.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Signal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X State=%d", Os, Signal, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ if (State)
++ {
++ /* unbind the signal from hardware. */
++ signal->hardware = gcvNULL;
++
++ /* Set the event to a signaled state. */
++ complete(&signal->obj);
++ }
++ else
++ {
++ /* Set the event to an unsignaled state. */
++ INIT_COMPLETION(signal->obj);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_SetSignalVG(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++ struct task_struct * userTask;
++ struct siginfo info;
++
++ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process);
++
++ if (userTask != gcvNULL)
++ {
++ info.si_signo = 48;
++ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL);
++ info.si_pid = 0;
++ info.si_uid = 0;
++ info.si_ptr = (gctPOINTER) Signal;
++
++ /* Signals with numbers between 32 and 63 are real-time,
++ send a real-time signal to the user process. */
++ result = send_sig_info(48, &info, userTask);
++
++ printk("gckOS_SetSignalVG:0x%x\n", result);
++ /* Error? */
++ if (result < 0)
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ else
++ {
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Return status. */
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_UserSignal
++**
++** Set the specified signal which is owned by a process to signaled state.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process
++ )
++{
++ gceSTATUS status;
++ gctSIGNAL signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=%d",
++ Os, Signal, (gctINT32)(gctUINTPTR_T)Process);
++
++ /* Map the signal into kernel space. */
++ gcmkONERROR(gckOS_MapSignal(Os, Signal, Process, &signal));
++
++ /* Signal. */
++ status = gckOS_Signal(Os, signal, gcvTRUE);
++
++ /* Unmap the signal */
++ gcmkVERIFY_OK(gckOS_UnmapSignal(Os, Signal));
++
++ gcmkFOOTER();
++ return status;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_WaitSignal
++**
++** Wait for a signal to become signaled.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctUINT32 Wait
++** Number of milliseconds to wait.
++** Pass the value of gcvINFINITE for an infinite wait.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WaitSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Wait=0x%08X", Os, Signal, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ might_sleep();
++
++ spin_lock_irq(&signal->obj.wait.lock);
++
++ if (signal->obj.done)
++ {
++ if (!signal->manualReset)
++ {
++ signal->obj.done = 0;
++ }
++
++ status = gcvSTATUS_OK;
++ }
++ else if (Wait == 0)
++ {
++ status = gcvSTATUS_TIMEOUT;
++ }
++ else
++ {
++ /* Convert wait to milliseconds. */
++#if gcdDETECT_TIMEOUT
++ gctINT timeout = (Wait == gcvINFINITE)
++ ? gcdINFINITE_TIMEOUT * HZ / 1000
++ : Wait * HZ / 1000;
++
++ gctUINT complained = 0;
++#else
++ gctINT timeout = (Wait == gcvINFINITE)
++ ? MAX_SCHEDULE_TIMEOUT
++ : Wait * HZ / 1000;
++#endif
++
++ DECLARE_WAITQUEUE(wait, current);
++ wait.flags |= WQ_FLAG_EXCLUSIVE;
++ __add_wait_queue_tail(&signal->obj.wait, &wait);
++
++ while (gcvTRUE)
++ {
++ if (signal_pending(current))
++ {
++ /* Interrupt received. */
++ status = gcvSTATUS_INTERRUPTED;
++ break;
++ }
++
++ __set_current_state(TASK_INTERRUPTIBLE);
++ spin_unlock_irq(&signal->obj.wait.lock);
++ timeout = schedule_timeout(timeout);
++ spin_lock_irq(&signal->obj.wait.lock);
++
++ if (signal->obj.done)
++ {
++ if (!signal->manualReset)
++ {
++ signal->obj.done = 0;
++ }
++
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++#if gcdDETECT_TIMEOUT
++ if ((Wait == gcvINFINITE) && (timeout == 0))
++ {
++ gctUINT32 dmaAddress1, dmaAddress2;
++ gctUINT32 dmaState1, dmaState2;
++
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkVERIFY_OK(_VerifyDMA(
++ Os, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++#if gcdDETECT_DMA_ADDRESS
++ /* Dump only if DMA appears stuck. */
++ if (
++ (dmaAddress1 == dmaAddress2)
++#if gcdDETECT_DMA_STATE
++ && (dmaState1 == dmaState2)
++#endif
++ )
++#endif
++ {
++ /* Increment complain count. */
++ complained += 1;
++
++ gcmkVERIFY_OK(_DumpGPUState(Os, gcvCORE_MAJOR));
++
++ gcmkPRINT(
++ "%s(%d): signal 0x%X; forced message flush (%d).",
++ __FUNCTION__, __LINE__, Signal, complained
++ );
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(dmaAddress2);
++ }
++
++ /* Reset timeout. */
++ timeout = gcdINFINITE_TIMEOUT * HZ / 1000;
++ }
++#endif
++
++ if (timeout == 0)
++ {
++
++ status = gcvSTATUS_TIMEOUT;
++ break;
++ }
++ }
++
++ __remove_wait_queue(&signal->obj.wait, &wait);
++
++#if gcdDETECT_TIMEOUT
++ if (complained)
++ {
++ gcmkPRINT(
++ "%s(%d): signal=0x%X; waiting done; status=%d",
++ __FUNCTION__, __LINE__, Signal, status
++ );
++ }
++#endif
++ }
++
++ spin_unlock_irq(&signal->obj.wait.lock);
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER_ARG("Signal=0x%X status=%d", Signal, status);
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapSignal
++**
++** Map a signal in to the current process space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to tha gctSIGNAL to map.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** OUTPUT:
++**
++** gctSIGNAL * MappedSignal
++** Pointer to a variable receiving the mapped gctSIGNAL.
++*/
++gceSTATUS
++gckOS_MapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process,
++ OUT gctSIGNAL * MappedSignal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=0x%X", Os, Signal, Process);
++
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++ gcmkVERIFY_ARGUMENT(MappedSignal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ if(atomic_inc_return(&signal->ref) <= 1)
++ {
++ /* The previous value is 0, it has been deleted. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ *MappedSignal = (gctSIGNAL) Signal;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*MappedSignal=0x%X", *MappedSignal);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapSignal
++**
++** Unmap a signal .
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to that gctSIGNAL mapped.
++*/
++gceSTATUS
++gckOS_UnmapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ return gckOS_DestroySignal(Os, Signal);
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateUserSignal
++**
++** Create a new signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL ManualReset
++** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in
++** order to set the signal to nonsignaled state.
++** If set to gcvFALSE, the signal will automatically be set to
++** nonsignaled state by gckOS_WaitSignal function.
++**
++** OUTPUT:
++**
++** gctINT * SignalID
++** Pointer to a variable receiving the created signal's ID.
++*/
++gceSTATUS
++gckOS_CreateUserSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctINT * SignalID
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T signal;
++
++ /* Create a new signal. */
++ status = gckOS_CreateSignal(Os, ManualReset, (gctSIGNAL *) &signal);
++ *SignalID = (gctINT) signal;
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroyUserSignal
++**
++** Destroy a signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** The signal's ID.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroyUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID
++ )
++{
++ return gckOS_DestroySignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID);
++}
++
++/*******************************************************************************
++**
++** gckOS_WaitUserSignal
++**
++** Wait for a signal used in the user mode to become signaled.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** Signal ID.
++**
++** gctUINT32 Wait
++** Number of milliseconds to wait.
++** Pass the value of gcvINFINITE for an infinite wait.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WaitUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctUINT32 Wait
++ )
++{
++ return gckOS_WaitSignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, Wait);
++}
++
++/*******************************************************************************
++**
++** gckOS_SignalUserSignal
++**
++** Set a state of the specified signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** SignalID.
++**
++** gctBOOL State
++** If gcvTRUE, the signal will be set to signaled state.
++** If gcvFALSE, the signal will be set to nonsignaled state.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SignalUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctBOOL State
++ )
++{
++ return gckOS_Signal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, State);
++}
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_CreateSemaphoreVG(
++ IN gckOS Os,
++ OUT gctSEMAPHORE * Semaphore
++ )
++{
++ gceSTATUS status;
++ struct semaphore * newSemaphore;
++
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ do
++ {
++ /* Allocate the semaphore structure. */
++ newSemaphore = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN);
++ if (newSemaphore == gcvNULL)
++ {
++ gcmkERR_BREAK(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the semaphore. */
++ sema_init(newSemaphore, 0);
++
++ /* Set the handle. */
++ * Semaphore = (gctSEMAPHORE) newSemaphore;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++
++gceSTATUS
++gckOS_IncrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Increment the semaphore's count. */
++ up((struct semaphore *) Semaphore);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DecrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ do
++ {
++ /* Decrement the semaphore's count. If the count is zero, wait
++ until it gets incremented. */
++ result = down_interruptible((struct semaphore *) Semaphore);
++
++ /* Signal received? */
++ if (result != 0)
++ {
++ status = gcvSTATUS_TERMINATE;
++ break;
++ }
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetSignal
++**
++** Set the specified signal to signaled state.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetSignal(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++ struct task_struct * userTask;
++ struct siginfo info;
++
++ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process);
++
++ if (userTask != gcvNULL)
++ {
++ info.si_signo = 48;
++ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL);
++ info.si_pid = 0;
++ info.si_uid = 0;
++ info.si_ptr = (gctPOINTER) Signal;
++
++ /* Signals with numbers between 32 and 63 are real-time,
++ send a real-time signal to the user process. */
++ result = send_sig_info(48, &info, userTask);
++
++ /* Error? */
++ if (result < 0)
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ else
++ {
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Return status. */
++ return status;
++}
++
++/******************************************************************************\
++******************************** Thread Object *********************************
++\******************************************************************************/
++
++gceSTATUS
++gckOS_StartThread(
++ IN gckOS Os,
++ IN gctTHREADFUNC ThreadFunction,
++ IN gctPOINTER ThreadParameter,
++ OUT gctTHREAD * Thread
++ )
++{
++ gceSTATUS status;
++ struct task_struct * thread;
++
++ gcmkHEADER_ARG("Os=0x%X ", Os);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(ThreadFunction != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ do
++ {
++ /* Create the thread. */
++ thread = kthread_create(
++ ThreadFunction,
++ ThreadParameter,
++ "Vivante Kernel Thread"
++ );
++
++ /* Failed? */
++ if (IS_ERR(thread))
++ {
++ status = gcvSTATUS_GENERIC_IO;
++ break;
++ }
++
++ /* Start the thread. */
++ wake_up_process(thread);
++
++ /* Set the thread handle. */
++ * Thread = (gctTHREAD) thread;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++gceSTATUS
++gckOS_StopThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ /* Thread should have already been enabled to terminate. */
++ kthread_stop((struct task_struct *) Thread);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_VerifyThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++/******************************************************************************\
++******************************** Software Timer ********************************
++\******************************************************************************/
++
++void
++_TimerFunction(
++ struct work_struct * work
++ )
++{
++ gcsOSTIMER_PTR timer = (gcsOSTIMER_PTR)work;
++
++ gctTIMERFUNCTION function = timer->function;
++
++ function(timer->data);
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateTimer
++**
++** Create a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctTIMERFUNCTION Function.
++** Pointer to a call back function which will be called when timer is
++** expired.
++**
++** gctPOINTER Data.
++** Private data which will be passed to call back function.
++**
++** OUTPUT:
++**
++** gctPOINTER * Timer
++** Pointer to a variable receiving the created timer.
++*/
++gceSTATUS
++gckOS_CreateTimer(
++ IN gckOS Os,
++ IN gctTIMERFUNCTION Function,
++ IN gctPOINTER Data,
++ OUT gctPOINTER * Timer
++ )
++{
++ gceSTATUS status;
++ gcsOSTIMER_PTR pointer;
++ gcmkHEADER_ARG("Os=0x%X Function=0x%X Data=0x%X", Os, Function, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ gcmkONERROR(gckOS_Allocate(Os, sizeof(gcsOSTIMER), (gctPOINTER)&pointer));
++
++ pointer->function = Function;
++ pointer->data = Data;
++
++ INIT_DELAYED_WORK(&pointer->work, _TimerFunction);
++
++ *Timer = pointer;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroyTimer
++**
++** Destory a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be destoryed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroyTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ )
++{
++ gcsOSTIMER_PTR timer;
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)
++ cancel_delayed_work_sync(&timer->work);
++#else
++ cancel_delayed_work(&timer->work);
++ flush_workqueue(Os->workqueue);
++#endif
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, Timer));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_StartTimer
++**
++** Schedule a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be scheduled.
++**
++** gctUINT32 Delay
++** Delay in milliseconds.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_StartTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer,
++ IN gctUINT32 Delay
++ )
++{
++ gcsOSTIMER_PTR timer;
++
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X Delay=%u", Os, Timer, Delay);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Delay != 0);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++ if (unlikely(delayed_work_pending(&timer->work)))
++ {
++ cancel_delayed_work(&timer->work);
++ }
++
++ queue_delayed_work(Os->workqueue, &timer->work, msecs_to_jiffies(Delay));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_StopTimer
++**
++** Cancel a unscheduled timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be cancel.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_StopTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ )
++{
++ gcsOSTIMER_PTR timer;
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++ cancel_delayed_work(&timer->work);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckOS_DumpCallStack(
++ IN gckOS Os
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ dump_stack();
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckOS_GetProcessNameByPid(
++ IN gctINT Pid,
++ IN gctSIZE_T Length,
++ OUT gctUINT8_PTR String
++ )
++{
++ struct task_struct *task;
++
++ /* Get the task_struct of the task with pid. */
++ rcu_read_lock();
++
++ task = FIND_TASK_BY_PID(Pid);
++
++ if (task == gcvNULL)
++ {
++ rcu_read_unlock();
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ /* Get name of process. */
++ strncpy(String, task->comm, Length);
++
++ rcu_read_unlock();
++
++ return gcvSTATUS_OK;
++}
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++
++gceSTATUS
++gckOS_CreateSyncPoint(
++ IN gckOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ /* Create an sync point structure. */
++ syncPoint = (gcsSYNC_POINT_PTR) kmalloc(
++ sizeof(gcsSYNC_POINT), GFP_KERNEL | gcdNOWARN);
++
++ if (syncPoint == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the sync point. */
++ atomic_set(&syncPoint->ref, 1);
++ atomic_set(&syncPoint->state, 0);
++
++ gcmkONERROR(_AllocateIntegerId(&Os->syncPointDB, syncPoint, &syncPoint->id));
++
++ *SyncPoint = (gctSYNC_POINT)(gctUINTPTR_T)syncPoint->id;
++
++ gcmkFOOTER_ARG("*SyncPonint=%d", syncPoint->id);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (syncPoint != gcvNULL)
++ {
++ kfree(syncPoint);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_ReferenceSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ /* Initialize the sync point. */
++ atomic_inc(&syncPoint->ref);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_DestroySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ if (atomic_dec_and_test(&syncPoint->ref))
++ {
++ gcmkVERIFY_OK(_DestroyIntegerId(&Os->syncPointDB, syncPoint->id));
++
++ /* Free the sgianl. */
++ syncPoint->timeline = gcvNULL;
++ kfree(syncPoint);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Get state. */
++ atomic_set(&syncPoint->state, gcvTRUE);
++
++ /* Signal timeline. */
++ if (syncPoint->timeline)
++ {
++ sync_timeline_signal(syncPoint->timeline);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_QuerySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctBOOL_PTR State
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Get state. */
++ *State = atomic_read(&syncPoint->state);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_CreateSyncTimeline(
++ IN gckOS Os,
++ OUT gctHANDLE * Timeline
++ )
++{
++ struct viv_sync_timeline * timeline;
++
++ /* Create viv sync timeline. */
++ timeline = viv_sync_timeline_create("viv timeline", Os);
++
++ if (timeline == gcvNULL)
++ {
++ /* Out of memory. */
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ *Timeline = (gctHANDLE) timeline;
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DestroySyncTimeline(
++ IN gckOS Os,
++ IN gctHANDLE Timeline
++ )
++{
++ struct viv_sync_timeline * timeline;
++ gcmkASSERT(Timeline != gcvNULL);
++
++ /* Destroy timeline. */
++ timeline = (struct viv_sync_timeline *) Timeline;
++ sync_timeline_destroy(&timeline->obj);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CreateNativeFence(
++ IN gckOS Os,
++ IN gctHANDLE Timeline,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ )
++{
++ int fd = -1;
++ struct viv_sync_timeline *timeline;
++ struct sync_pt * pt = gcvNULL;
++ struct sync_fence * fence;
++ char name[32];
++ gcsSYNC_POINT_PTR syncPoint;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Timeline=0x%X SyncPoint=%d",
++ Os, Timeline, (gctUINT)(gctUINTPTR_T)SyncPoint);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ /* Cast timeline. */
++ timeline = (struct viv_sync_timeline *) Timeline;
++
++ fd = get_unused_fd();
++
++ if (fd < 0)
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Create viv_sync_pt. */
++ pt = viv_sync_pt_create(timeline, SyncPoint);
++
++ if (pt == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Reference sync_timeline. */
++ syncPoint->timeline = &timeline->obj;
++
++ /* Build fence name. */
++ snprintf(name, 32, "viv sync_fence-%u", (gctUINT)(gctUINTPTR_T)SyncPoint);
++
++ /* Create sync_fence. */
++ fence = sync_fence_create(name, pt);
++
++ if (fence == NULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Install fence to fd. */
++ sync_fence_install(fence, fd);
++
++ *FenceFD = fd;
++ gcmkFOOTER_ARG("*FenceFD=%d", fd);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Error roll back. */
++ if (pt)
++ {
++ sync_pt_free(pt);
++ }
++
++ if (fd > 0)
++ {
++ put_unused_fd(fd);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,83 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_os_h_
++#define __gc_hal_kernel_os_h_
++
++typedef struct _LINUX_MDL_MAP
++{
++ gctINT pid;
++ gctPOINTER vmaAddr;
++ struct vm_area_struct * vma;
++ gctINT reference;
++ struct _LINUX_MDL_MAP * next;
++}
++LINUX_MDL_MAP;
++
++typedef struct _LINUX_MDL_MAP * PLINUX_MDL_MAP;
++
++typedef struct _LINUX_MDL
++{
++ gctINT pid;
++ char * addr;
++
++ union _pages
++ {
++ /* Pointer to a array of pages. */
++ struct page * contiguousPages;
++ /* Pointer to a array of pointers to page. */
++ struct page ** nonContiguousPages;
++ }
++ u;
++
++#ifdef NO_DMA_COHERENT
++ gctPOINTER kaddr;
++#endif /* NO_DMA_COHERENT */
++
++ gctINT numPages;
++ gctINT pagedMem;
++ gctBOOL contiguous;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ gctBOOL exact;
++#endif
++ dma_addr_t dmaHandle;
++ PLINUX_MDL_MAP maps;
++ struct _LINUX_MDL * prev;
++ struct _LINUX_MDL * next;
++}
++LINUX_MDL, *PLINUX_MDL;
++
++extern PLINUX_MDL_MAP
++FindMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT PID
++ );
++
++typedef struct _DRIVER_ARGS
++{
++ gctUINT64 InputBuffer;
++ gctUINT64 InputBufferSize;
++ gctUINT64 OutputBuffer;
++ gctUINT64 OutputBufferSize;
++}
++DRIVER_ARGS;
++
++#endif /* __gc_hal_kernel_os_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,174 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <linux/kernel.h>
++#include <linux/file.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/module.h>
++#include <linux/syscalls.h>
++#include <linux/uaccess.h>
++
++#include "gc_hal_kernel_sync.h"
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++
++static struct sync_pt *
++viv_sync_pt_dup(
++ struct sync_pt * sync_pt
++ )
++{
++ gceSTATUS status;
++ struct viv_sync_pt *pt;
++ struct viv_sync_pt *src;
++ struct viv_sync_timeline *obj;
++
++ src = (struct viv_sync_pt *) sync_pt;
++ obj = (struct viv_sync_timeline *) sync_pt->parent;
++
++ /* Create the new sync_pt. */
++ pt = (struct viv_sync_pt *)
++ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
++
++ pt->stamp = src->stamp;
++ pt->sync = src->sync;
++
++ /* Reference sync point. */
++ status = gckOS_ReferenceSyncPoint(obj->os, pt->sync);
++
++ if (gcmIS_ERROR(status))
++ {
++ sync_pt_free((struct sync_pt *)pt);
++ return NULL;
++ }
++
++ return (struct sync_pt *)pt;
++}
++
++static int
++viv_sync_pt_has_signaled(
++ struct sync_pt * sync_pt
++ )
++{
++ gceSTATUS status;
++ gctBOOL state;
++ struct viv_sync_pt * pt;
++ struct viv_sync_timeline * obj;
++
++ pt = (struct viv_sync_pt *)sync_pt;
++ obj = (struct viv_sync_timeline *)sync_pt->parent;
++
++ status = gckOS_QuerySyncPoint(obj->os, pt->sync, &state);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error. */
++ return -1;
++ }
++
++ return state;
++}
++
++static int
++viv_sync_pt_compare(
++ struct sync_pt * a,
++ struct sync_pt * b
++ )
++{
++ int ret;
++ struct viv_sync_pt * pt1 = (struct viv_sync_pt *) a;
++ struct viv_sync_pt * pt2 = (struct viv_sync_pt *) b;
++
++ ret = (pt1->stamp < pt2->stamp) ? -1
++ : (pt1->stamp == pt2->stamp) ? 0
++ : 1;
++
++ return ret;
++}
++
++static void
++viv_sync_pt_free(
++ struct sync_pt * sync_pt
++ )
++{
++ struct viv_sync_pt * pt;
++ struct viv_sync_timeline * obj;
++
++ pt = (struct viv_sync_pt *) sync_pt;
++ obj = (struct viv_sync_timeline *) sync_pt->parent;
++
++ gckOS_DestroySyncPoint(obj->os, pt->sync);
++}
++
++static struct sync_timeline_ops viv_timeline_ops =
++{
++ .driver_name = "viv_sync",
++ .dup = viv_sync_pt_dup,
++ .has_signaled = viv_sync_pt_has_signaled,
++ .compare = viv_sync_pt_compare,
++ .free_pt = viv_sync_pt_free,
++};
++
++struct viv_sync_timeline *
++viv_sync_timeline_create(
++ const char * name,
++ gckOS os
++ )
++{
++ struct viv_sync_timeline * obj;
++
++ obj = (struct viv_sync_timeline *)
++ sync_timeline_create(&viv_timeline_ops, sizeof(struct viv_sync_timeline), name);
++
++ obj->os = os;
++ obj->stamp = 0;
++
++ return obj;
++}
++
++struct sync_pt *
++viv_sync_pt_create(
++ struct viv_sync_timeline * obj,
++ gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ struct viv_sync_pt * pt;
++
++ pt = (struct viv_sync_pt *)
++ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
++
++ pt->stamp = obj->stamp++;
++ pt->sync = SyncPoint;
++
++ /* Dup signal. */
++ status = gckOS_ReferenceSyncPoint(obj->os, SyncPoint);
++
++ if (gcmIS_ERROR(status))
++ {
++ sync_pt_free((struct sync_pt *)pt);
++ return NULL;
++ }
++
++ return (struct sync_pt *) pt;
++}
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,71 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_sync_h_
++#define __gc_hal_kernel_sync_h_
++
++#include <linux/types.h>
++
++#include <linux/sync.h>
++
++#include <gc_hal.h>
++#include <gc_hal_base.h>
++
++struct viv_sync_timeline
++{
++ /* Parent object. */
++ struct sync_timeline obj;
++
++ /* Timestamp when sync_pt is created. */
++ gctUINT stamp;
++
++ /* Pointer to os struct. */
++ gckOS os;
++};
++
++
++struct viv_sync_pt
++{
++ /* Parent object. */
++ struct sync_pt pt;
++
++ /* Reference sync point*/
++ gctSYNC_POINT sync;
++
++ /* Timestamp when sync_pt is created. */
++ gctUINT stamp;
++};
++
++/* Create viv_sync_timeline object. */
++struct viv_sync_timeline *
++viv_sync_timeline_create(
++ const char * Name,
++ gckOS Os
++ );
++
++/* Create viv_sync_pt object. */
++struct sync_pt *
++viv_sync_pt_create(
++ struct viv_sync_timeline * Obj,
++ gctSYNC_POINT SyncPoint
++ );
++
++#endif /* __gc_hal_kernel_sync_h_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/Kbuild linux-linaro-stable-mx6/drivers/mxc/gpu-viv/Kbuild
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/Kbuild 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/Kbuild 2014-05-15 20:33:58.586018102 +0200
+@@ -0,0 +1,236 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2013 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++#
++# Linux build file for kernel HAL driver.
++#
++
++AQROOT := $(srctree)/drivers/mxc/gpu-viv
++AQARCH := $(AQROOT)/arch/XAQ2
++AQVGARCH := $(AQROOT)/arch/GC350
++
++include $(AQROOT)/config
++
++KERNEL_DIR ?= $(TOOL_DIR)/kernel
++
++OS_KERNEL_DIR := hal/os/linux/kernel
++ARCH_KERNEL_DIR := arch/$(notdir $(AQARCH))/hal/kernel
++ARCH_VG_KERNEL_DIR := arch/$(notdir $(AQVGARCH))/hal/kernel
++HAL_KERNEL_DIR := hal/kernel
++
++EXTRA_CFLAGS += -Werror
++
++OBJS := $(OS_KERNEL_DIR)/gc_hal_kernel_device.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_driver.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_linux.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_math.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_os.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_debugfs.o
++
++OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_db.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_debug.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_event.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_heap.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_mmu.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_video_memory.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_power.o
++
++OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_context.o \
++ $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware.o
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++OBJS +=\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_command_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_interrupt_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_mmu_vg.o\
++ $(ARCH_VG_KERNEL_DIR)/gc_hal_kernel_hardware_command_vg.o\
++ $(ARCH_VG_KERNEL_DIR)/gc_hal_kernel_hardware_vg.o
++endif
++
++ifneq ($(CONFIG_SYNC),)
++OBJS += $(OS_KERNEL_DIR)/gc_hal_kernel_sync.o
++endif
++
++ifeq ($(KERNELRELEASE), )
++
++.PHONY: all clean install
++
++# Define targets.
++all:
++ @make V=$(V) ARCH=$(ARCH_TYPE) -C $(KERNEL_DIR) SUBDIRS=`pwd` modules
++
++clean:
++ @rm -rf $(OBJS)
++ @rm -rf modules.order Module.symvers
++ @find $(AQROOT) -name ".gc_*.cmd" | xargs rm -f
++
++install: all
++ @mkdir -p $(SDK_DIR)/drivers
++
++else
++
++
++EXTRA_CFLAGS += -DLINUX -DDRIVER
++
++ifeq ($(ENUM_WORKAROUND), 1)
++EXTRA_CFLAGS += -DENUM_WORKAROUND=1
++else
++EXTRA_CFLAGS += -DENUM_WORKAROUND=0
++endif
++
++ifeq ($(FLAREON),1)
++EXTRA_CFLAGS += -DFLAREON
++endif
++
++ifeq ($(DEBUG), 1)
++EXTRA_CFLAGS += -DDBG=1 -DDEBUG -D_DEBUG
++else
++EXTRA_CFLAGS += -DDBG=0
++endif
++
++ifeq ($(NO_DMA_COHERENT), 1)
++EXTRA_CFLAGS += -DNO_DMA_COHERENT
++endif
++
++ifeq ($(CONFIG_DOVE_GPU), 1)
++EXTRA_CFLAGS += -DCONFIG_DOVE_GPU=1
++endif
++
++ifneq ($(USE_PLATFORM_DRIVER), 0)
++EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=1
++else
++EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=0
++endif
++
++
++EXTRA_CFLAGS += -DVIVANTE_PROFILER=1
++EXTRA_CFLAGS += -DVIVANTE_PROFILER_CONTEXT=1
++
++
++ifeq ($(ANDROID), 1)
++EXTRA_CFLAGS += -DANDROID=1
++endif
++
++ifeq ($(ENABLE_GPU_CLOCK_BY_DRIVER), 1)
++EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=1
++else
++EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=0
++endif
++
++ifeq ($(USE_NEW_LINUX_SIGNAL), 1)
++EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=1
++else
++EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=0
++endif
++
++ifeq ($(NO_USER_DIRECT_ACCESS_FROM_KERNEL), 1)
++EXTRA_CFLAGS += -DNO_USER_DIRECT_ACCESS_FROM_KERNEL=1
++else
++EXTRA_CFLAGS += -DNO_USER_DIRECT_ACCESS_FROM_KERNEL=0
++endif
++
++ifeq ($(FORCE_ALL_VIDEO_MEMORY_CACHED), 1)
++EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=1
++else
++EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=0
++endif
++
++ifeq ($(NONPAGED_MEMORY_CACHEABLE), 1)
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=1
++else
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=0
++endif
++
++ifeq ($(NONPAGED_MEMORY_BUFFERABLE), 1)
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=1
++else
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=0
++endif
++
++ifeq ($(CACHE_FUNCTION_UNIMPLEMENTED), 1)
++EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=1
++else
++EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=0
++endif
++
++ifeq ($(SUPPORT_SWAP_RECTANGLE), 1)
++EXTRA_CFLAGS += -DgcdSUPPORT_SWAP_RECTANGLE=1
++else
++EXTRA_CFLAGS += -DgcdSUPPORT_SWAP_RECTANGLE=0
++endif
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++EXTRA_CFLAGS += -DgcdENABLE_VG=1
++else
++EXTRA_CFLAGS += -DgcdENABLE_VG=0
++endif
++
++ifeq ($(CONFIG_SMP), y)
++EXTRA_CFLAGS += -DgcdSMP=1
++else
++EXTRA_CFLAGS += -DgcdSMP=0
++endif
++
++ifeq ($(VIVANTE_NO_3D),1)
++EXTRA_CFLAGS += -DVIVANTE_NO_3D
++endif
++
++ifeq ($(ENABLE_OUTER_CACHE_PATCH), 1)
++EXTRA_CFLAGS += -DgcdENABLE_OUTER_CACHE_PATCH=1
++else
++EXTRA_CFLAGS += -DgcdENABLE_OUTER_CACHE_PATCH=0
++endif
++
++ifeq ($(USE_BANK_ALIGNMENT), 1)
++ EXTRA_CFLAGS += -DgcdENABLE_BANK_ALIGNMENT=1
++ ifneq ($(BANK_BIT_START), 0)
++ ifneq ($(BANK_BIT_END), 0)
++ EXTRA_CFLAGS += -DgcdBANK_BIT_START=$(BANK_BIT_START)
++ EXTRA_CFLAGS += -DgcdBANK_BIT_END=$(BANK_BIT_END)
++ endif
++ endif
++
++ ifneq ($(BANK_CHANNEL_BIT), 0)
++ EXTRA_CFLAGS += -DgcdBANK_CHANNEL_BIT=$(BANK_CHANNEL_BIT)
++ endif
++endif
++
++ifneq ($(CONFIG_SYNC),)
++EXTRA_CFLAGS += -DgcdANDROID_NATIVE_FENCE_SYNC=1
++endif
++
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel/inc
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel
++EXTRA_CFLAGS += -I$(AQARCH)/hal/kernel
++EXTRA_CFLAGS += -I$(AQROOT)/hal/os/linux/kernel
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++EXTRA_CFLAGS += -I$(AQVGARCH)/hal/kernel
++endif
++
++obj-$(CONFIG_MXC_GPU_VIV) += galcore.o
++
++galcore-objs := $(OBJS)
++
++endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/gpu-viv/Kconfig linux-linaro-stable-mx6/drivers/mxc/gpu-viv/Kconfig
+--- linux-3.10.30.orig/drivers/mxc/gpu-viv/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/gpu-viv/Kconfig 2014-05-15 20:33:58.586018102 +0200
+@@ -0,0 +1,9 @@
++menu "MXC Vivante GPU support"
++ depends on SOC_IMX6Q
++
++config MXC_GPU_VIV
++ tristate "MXC Vivante GPU support"
++ ---help---
++ Say Y to get the GPU driver support.
++
++endmenu
+diff -Nur linux-3.10.30.orig/drivers/mxc/hdmi-cec/Kconfig linux-linaro-stable-mx6/drivers/mxc/hdmi-cec/Kconfig
+--- linux-3.10.30.orig/drivers/mxc/hdmi-cec/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/hdmi-cec/Kconfig 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,11 @@
++
++menu "MXC HDMI CEC (Consumer Electronics Control) support"
++
++config MXC_HDMI_CEC
++ tristate "Support for MXC HDMI CEC (Consumer Electronics Control)"
++ depends on MFD_MXC_HDMI
++ depends on FB_MXC_HDMI
++ help
++ The HDMI CEC device implement low level protocol on i.MX6x platforms.
++
++endmenu
+diff -Nur linux-3.10.30.orig/drivers/mxc/hdmi-cec/Makefile linux-linaro-stable-mx6/drivers/mxc/hdmi-cec/Makefile
+--- linux-3.10.30.orig/drivers/mxc/hdmi-cec/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/hdmi-cec/Makefile 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1 @@
++obj-$(CONFIG_MXC_HDMI_CEC) += mxc_hdmi-cec.o
+diff -Nur linux-3.10.30.orig/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c linux-linaro-stable-mx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c
+--- linux-3.10.30.orig/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,608 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_hdmi-cec.c
++ *
++ * @brief HDMI CEC system initialization and file operation implementation
++ *
++ * @ingroup HDMI
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/fs.h>
++#include <linux/stat.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/uaccess.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/workqueue.h>
++#include <linux/sizes.h>
++
++#include <linux/console.h>
++#include <linux/types.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/pinctrl/consumer.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "mxc_hdmi-cec.h"
++
++
++#define MAX_MESSAGE_LEN 17
++
++#define MESSAGE_TYPE_RECEIVE_SUCCESS 1
++#define MESSAGE_TYPE_NOACK 2
++#define MESSAGE_TYPE_DISCONNECTED 3
++#define MESSAGE_TYPE_CONNECTED 4
++#define MESSAGE_TYPE_SEND_SUCCESS 5
++
++#define CEC_TX_INPROGRESS -1
++#define CEC_TX_AVAIL 0
++
++struct hdmi_cec_priv {
++ int receive_error;
++ int send_error;
++ u8 Logical_address;
++ bool cec_state;
++ u8 last_msg[MAX_MESSAGE_LEN];
++ u8 msg_len;
++ int tx_answer;
++ u16 latest_cec_stat;
++ u8 link_status;
++ spinlock_t irq_lock;
++ struct delayed_work hdmi_cec_work;
++ struct mutex lock;
++};
++
++struct hdmi_cec_event {
++ int event_type;
++ int msg_len;
++ u8 msg[MAX_MESSAGE_LEN];
++ struct list_head list;
++};
++
++
++static LIST_HEAD(head);
++
++static int hdmi_cec_major;
++static struct class *hdmi_cec_class;
++static struct hdmi_cec_priv hdmi_cec_data;
++static u8 open_count;
++
++static wait_queue_head_t hdmi_cec_queue;
++static wait_queue_head_t tx_cec_queue;
++
++static irqreturn_t mxc_hdmi_cec_isr(int irq, void *data)
++{
++ struct hdmi_cec_priv *hdmi_cec = data;
++ u16 cec_stat = 0;
++ unsigned long flags;
++ u8 phy_stat0;
++ irqreturn_t ret = IRQ_HANDLED;
++
++ spin_lock_irqsave(&hdmi_cec->irq_lock, flags);
++
++ hdmi_writeb(0x7f, HDMI_IH_MUTE_CEC_STAT0);
++
++ cec_stat = hdmi_readb(HDMI_IH_CEC_STAT0);
++ hdmi_writeb(cec_stat, HDMI_IH_CEC_STAT0);
++ phy_stat0 = hdmi_readb(HDMI_PHY_STAT0) & 0x02;
++
++ if ((cec_stat & (HDMI_IH_CEC_STAT0_ERROR_INIT | \
++ HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM | \
++ HDMI_IH_CEC_STAT0_DONE)) == 0) {
++ ret = IRQ_NONE;
++ cec_stat = 0;
++ }
++ if (hdmi_cec->link_status ^ phy_stat0) {
++ /* HPD value changed */
++ hdmi_cec->link_status = phy_stat0;
++ if (hdmi_cec->link_status)
++ cec_stat |= 0x80; /* Connected */
++ else
++ cec_stat |= 0x100; /* Disconnected */
++ }
++ pr_debug("HDMI CEC interrupt received\n");
++ hdmi_cec->latest_cec_stat = cec_stat ;
++
++ schedule_delayed_work(&(hdmi_cec->hdmi_cec_work), msecs_to_jiffies(20));
++
++ spin_unlock_irqrestore(&hdmi_cec->irq_lock, flags);
++
++ return ret;
++}
++
++void mxc_hdmi_cec_handle(u16 cec_stat)
++{
++ u8 val = 0, i = 0;
++ struct hdmi_cec_event *event = NULL;
++ /*The current transmission is successful (for initiator only).*/
++ if (!open_count)
++ return;
++
++ if (cec_stat & HDMI_IH_CEC_STAT0_DONE) {
++ hdmi_cec_data.tx_answer = cec_stat;
++ wake_up(&tx_cec_queue);
++ }
++ /*EOM is detected so that the received data is ready in the receiver data buffer*/
++ if (cec_stat & HDMI_IH_CEC_STAT0_EOM) {
++ hdmi_writeb(0x02, HDMI_IH_CEC_STAT0);
++ event = vmalloc(sizeof(struct hdmi_cec_event));
++ if (NULL == event) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return;
++ }
++ memset(event, 0, sizeof(struct hdmi_cec_event));
++ event->msg_len = hdmi_readb(HDMI_CEC_RX_CNT);
++ if (!event->msg_len) {
++ pr_err("%s: Invalid CEC message length!\n", __func__);
++ return;
++ }
++ event->event_type = MESSAGE_TYPE_RECEIVE_SUCCESS;
++ for (i = 0; i < event->msg_len; i++)
++ event->msg[i] = hdmi_readb(HDMI_CEC_RX_DATA0+i);
++ hdmi_writeb(0x0, HDMI_CEC_LOCK);
++ mutex_lock(&hdmi_cec_data.lock);
++ list_add_tail(&event->list, &head);
++ mutex_unlock(&hdmi_cec_data.lock);
++ wake_up(&hdmi_cec_queue);
++ }
++ /*An error is detected on cec line (for initiator only). */
++ if (cec_stat & HDMI_IH_CEC_STAT0_ERROR_INIT) {
++ mutex_lock(&hdmi_cec_data.lock);
++ hdmi_cec_data.send_error++;
++ if (hdmi_cec_data.send_error > 2) {
++ pr_err("%s:Re-transmission is attempted more than 2 times!\n", __func__);
++ hdmi_cec_data.send_error = 0;
++ mutex_unlock(&hdmi_cec_data.lock);
++ hdmi_cec_data.tx_answer = cec_stat;
++ wake_up(&tx_cec_queue);
++ return;
++ }
++ for (i = 0; i < hdmi_cec_data.msg_len; i++)
++ hdmi_writeb(hdmi_cec_data.last_msg[i], HDMI_CEC_TX_DATA0+i);
++ hdmi_writeb(hdmi_cec_data.msg_len, HDMI_CEC_TX_CNT);
++ val = hdmi_readb(HDMI_CEC_CTRL);
++ val |= 0x01;
++ hdmi_writeb(val, HDMI_CEC_CTRL);
++ mutex_unlock(&hdmi_cec_data.lock);
++ }
++ /*A frame is not acknowledged in a directly addressed message. Or a frame is negatively acknowledged in
++ a broadcast message (for initiator only).*/
++ if (cec_stat & HDMI_IH_CEC_STAT0_NACK) {
++ hdmi_cec_data.tx_answer = cec_stat;
++ wake_up(&tx_cec_queue);
++ }
++ /*An error is notified by a follower. Abnormal logic data bit error (for follower).*/
++ if (cec_stat & HDMI_IH_CEC_STAT0_ERROR_FOLL) {
++ hdmi_cec_data.receive_error++;
++ }
++ /*HDMI cable connected*/
++ if (cec_stat & 0x80) {
++ pr_info("HDMI link connected\n");
++ event = vmalloc(sizeof(struct hdmi_cec_event));
++ if (NULL == event) {
++ pr_err("%s: Not enough memory\n", __func__);
++ return;
++ }
++ memset(event, 0, sizeof(struct hdmi_cec_event));
++ event->event_type = MESSAGE_TYPE_CONNECTED;
++ mutex_lock(&hdmi_cec_data.lock);
++ list_add_tail(&event->list, &head);
++ mutex_unlock(&hdmi_cec_data.lock);
++ wake_up(&hdmi_cec_queue);
++ }
++ /*HDMI cable disconnected*/
++ if (cec_stat & 0x100) {
++ pr_info("HDMI link disconnected\n");
++ event = vmalloc(sizeof(struct hdmi_cec_event));
++ if (NULL == event) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return;
++ }
++ memset(event, 0, sizeof(struct hdmi_cec_event));
++ event->event_type = MESSAGE_TYPE_DISCONNECTED;
++ mutex_lock(&hdmi_cec_data.lock);
++ list_add_tail(&event->list, &head);
++ mutex_unlock(&hdmi_cec_data.lock);
++ wake_up(&hdmi_cec_queue);
++ }
++ return;
++}
++EXPORT_SYMBOL(mxc_hdmi_cec_handle);
++static void mxc_hdmi_cec_worker(struct work_struct *work)
++{
++ u8 val;
++ mxc_hdmi_cec_handle(hdmi_cec_data.latest_cec_stat);
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL | HDMI_IH_CEC_STAT0_ARB_LOST;
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++}
++
++/*!
++ * @brief open function for cec file operation
++ *
++ * @return 0 on success or negative error code on error
++ */
++static int hdmi_cec_open(struct inode *inode, struct file *filp)
++{
++ mutex_lock(&hdmi_cec_data.lock);
++ if (open_count) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EBUSY;
++ }
++ open_count = 1;
++ filp->private_data = (void *)(&hdmi_cec_data);
++ hdmi_cec_data.Logical_address = 15;
++ hdmi_cec_data.cec_state = false;
++ mutex_unlock(&hdmi_cec_data.lock);
++ return 0;
++}
++
++static ssize_t hdmi_cec_read(struct file *file, char __user *buf, size_t count,
++ loff_t *ppos)
++{
++ struct hdmi_cec_event *event = NULL;
++ pr_debug("function : %s\n", __func__);
++
++ if (!open_count)
++ return -ENODEV;
++ mutex_lock(&hdmi_cec_data.lock);
++ if (false == hdmi_cec_data.cec_state) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EACCES;
++ }
++
++ if (list_empty(&head)) {
++ if (file->f_flags & O_NONBLOCK) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EAGAIN;
++ } else {
++ do {
++ mutex_unlock(&hdmi_cec_data.lock);
++ if (wait_event_interruptible(hdmi_cec_queue, (!list_empty(&head))))
++ return -ERESTARTSYS;
++ mutex_lock(&hdmi_cec_data.lock);
++ } while (list_empty(&head));
++ }
++ }
++
++ event = list_first_entry(&head, struct hdmi_cec_event, list);
++ list_del(&event->list);
++ mutex_unlock(&hdmi_cec_data.lock);
++ if (copy_to_user(buf, event,
++ sizeof(struct hdmi_cec_event) - sizeof(struct list_head))) {
++ vfree(event);
++ return -EFAULT;
++ }
++ vfree(event);
++ return (sizeof(struct hdmi_cec_event) - sizeof(struct list_head));
++}
++
++static ssize_t hdmi_cec_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ int ret = 0 , i = 0;
++ u8 msg[MAX_MESSAGE_LEN];
++ u8 msg_len = 0, val = 0;
++
++ pr_debug("function : %s\n", __func__);
++
++ if (!open_count)
++ return -ENODEV;
++ mutex_lock(&hdmi_cec_data.lock);
++ if (false == hdmi_cec_data.cec_state) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EACCES;
++ }
++ /* Ensure that there is only one writer who is the only listener of tx_cec_queue */
++ if (hdmi_cec_data.tx_answer != CEC_TX_AVAIL) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EBUSY;
++ }
++ mutex_unlock(&hdmi_cec_data.lock);
++ if (count > MAX_MESSAGE_LEN)
++ return -EINVAL;
++ memset(&msg, 0, MAX_MESSAGE_LEN);
++ ret = copy_from_user(&msg, buf, count);
++ if (ret)
++ return -EACCES;
++ mutex_lock(&hdmi_cec_data.lock);
++ hdmi_cec_data.send_error = 0;
++ hdmi_cec_data.tx_answer = CEC_TX_INPROGRESS;
++ msg_len = count;
++ hdmi_writeb(msg_len, HDMI_CEC_TX_CNT);
++ for (i = 0; i < msg_len; i++)
++ hdmi_writeb(msg[i], HDMI_CEC_TX_DATA0+i);
++ val = hdmi_readb(HDMI_CEC_CTRL);
++ val |= 0x01;
++ hdmi_writeb(val, HDMI_CEC_CTRL);
++ memcpy(hdmi_cec_data.last_msg, msg, msg_len);
++ hdmi_cec_data.msg_len = msg_len;
++ mutex_unlock(&hdmi_cec_data.lock);
++
++ ret = wait_event_interruptible_timeout(tx_cec_queue, hdmi_cec_data.tx_answer != CEC_TX_INPROGRESS, HZ);
++
++ if (ret < 0) {
++ ret = -ERESTARTSYS;
++ goto tx_out;
++ }
++
++ if (hdmi_cec_data.tx_answer & HDMI_IH_CEC_STAT0_DONE)
++ /* msg correctly sent */
++ ret = msg_len;
++ else
++ ret = -EIO;
++
++ tx_out:
++ hdmi_cec_data.tx_answer = CEC_TX_AVAIL;
++ return ret;
++}
++
++
++static void hdmi_stop_device(void)
++{
++ u8 val;
++
++ hdmi_writeb(0x10, HDMI_CEC_CTRL);
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL | HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_ARB_LOST | \
++ HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM | HDMI_IH_CEC_STAT0_DONE;
++ hdmi_writeb(val, HDMI_CEC_MASK);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(0x0, HDMI_CEC_POLARITY);
++ val = hdmi_readb(HDMI_MC_CLKDIS);
++ val |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(val, HDMI_MC_CLKDIS);
++ mutex_lock(&hdmi_cec_data.lock);
++ hdmi_cec_data.cec_state = false;
++ mutex_unlock(&hdmi_cec_data.lock);
++}
++
++/*!
++ * @brief IO ctrl function for vpu file operation
++ * @param cmd IO ctrl command
++ * @return 0 on success or negative error code on error
++ */
++static long hdmi_cec_ioctl(struct file *filp, u_int cmd,
++ u_long arg)
++{
++ int ret = 0, status = 0;
++ u8 val = 0, msg = 0;
++ struct mxc_edid_cfg hdmi_edid_cfg;
++ pr_debug("function : %s\n", __func__);
++ if (!open_count)
++ return -ENODEV;
++ switch (cmd) {
++ case HDMICEC_IOC_SETLOGICALADDRESS:
++ mutex_lock(&hdmi_cec_data.lock);
++ if (false == hdmi_cec_data.cec_state) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ pr_err("Trying to set logical address while not started\n");
++ return -EACCES;
++ }
++ hdmi_cec_data.Logical_address = (u8)arg;
++ if (hdmi_cec_data.Logical_address <= 7) {
++ val = 1 << hdmi_cec_data.Logical_address;
++ hdmi_writeb(val, HDMI_CEC_ADDR_L);
++ hdmi_writeb(0, HDMI_CEC_ADDR_H);
++ } else if (hdmi_cec_data.Logical_address > 7 && hdmi_cec_data.Logical_address <= 15) {
++ val = 1 << (hdmi_cec_data.Logical_address - 8);
++ hdmi_writeb(val, HDMI_CEC_ADDR_H);
++ hdmi_writeb(0, HDMI_CEC_ADDR_L);
++ } else
++ ret = -EINVAL;
++ /*Send Polling message with same source and destination address*/
++ if (0 == ret && 15 != hdmi_cec_data.Logical_address) {
++ msg = (hdmi_cec_data.Logical_address << 4)|hdmi_cec_data.Logical_address;
++ hdmi_writeb(1, HDMI_CEC_TX_CNT);
++ hdmi_writeb(msg, HDMI_CEC_TX_DATA0);
++ val = hdmi_readb(HDMI_CEC_CTRL);
++ val |= 0x01;
++ hdmi_writeb(val, HDMI_CEC_CTRL);
++ }
++ mutex_unlock(&hdmi_cec_data.lock);
++ break;
++ case HDMICEC_IOC_STARTDEVICE:
++ val = hdmi_readb(HDMI_MC_CLKDIS);
++ val &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(val, HDMI_MC_CLKDIS);
++ hdmi_writeb(0x02, HDMI_CEC_CTRL);
++ /* Force read unlock */
++ hdmi_writeb(0x0, HDMI_CEC_LOCK);
++ val = HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM | HDMI_IH_CEC_STAT0_DONE;
++ hdmi_writeb(val, HDMI_CEC_POLARITY);
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL | HDMI_IH_CEC_STAT0_ARB_LOST;
++ hdmi_writeb(val, HDMI_CEC_MASK);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_cec_data.link_status = hdmi_readb(HDMI_PHY_STAT0) & 0x02;
++ mutex_lock(&hdmi_cec_data.lock);
++ hdmi_cec_data.cec_state = true;
++ mutex_unlock(&hdmi_cec_data.lock);
++ break;
++ case HDMICEC_IOC_STOPDEVICE:
++ hdmi_stop_device();
++ break;
++ case HDMICEC_IOC_GETPHYADDRESS:
++ hdmi_get_edid_cfg(&hdmi_edid_cfg);
++ status = copy_to_user((void __user *)arg,
++ &hdmi_edid_cfg.physical_address,
++ 4*sizeof(u8));
++ if (status)
++ ret = -EFAULT;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++ return ret;
++}
++
++/*!
++ * @brief Release function for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int hdmi_cec_release(struct inode *inode, struct file *filp)
++{
++ mutex_lock(&hdmi_cec_data.lock);
++ if (open_count) {
++ open_count = 0;
++ hdmi_cec_data.cec_state = false;
++ hdmi_cec_data.Logical_address = 15;
++ }
++ mutex_unlock(&hdmi_cec_data.lock);
++
++ return 0;
++}
++
++static unsigned int hdmi_cec_poll(struct file *file, poll_table *wait)
++{
++ unsigned int mask = 0;
++
++ pr_debug("function : %s\n", __func__);
++
++ poll_wait(file, &hdmi_cec_queue, wait);
++
++ mutex_lock(&hdmi_cec_data.lock);
++ if (hdmi_cec_data.tx_answer == CEC_TX_AVAIL)
++ mask = (POLLOUT | POLLWRNORM);
++ if (!list_empty(&head))
++ mask |= (POLLIN | POLLRDNORM);
++ mutex_unlock(&hdmi_cec_data.lock);
++ return mask;
++}
++
++
++const struct file_operations hdmi_cec_fops = {
++ .owner = THIS_MODULE,
++ .read = hdmi_cec_read,
++ .write = hdmi_cec_write,
++ .open = hdmi_cec_open,
++ .unlocked_ioctl = hdmi_cec_ioctl,
++ .release = hdmi_cec_release,
++ .poll = hdmi_cec_poll,
++};
++
++static int hdmi_cec_dev_probe(struct platform_device *pdev)
++{
++ int err = 0;
++ struct device *temp_class;
++ struct resource *res;
++ struct pinctrl *pinctrl;
++ int irq = platform_get_irq(pdev, 0);
++
++ hdmi_cec_major = register_chrdev(hdmi_cec_major, "mxc_hdmi_cec", &hdmi_cec_fops);
++ if (hdmi_cec_major < 0) {
++ dev_err(&pdev->dev, "hdmi_cec: unable to get a major for HDMI CEC\n");
++ err = -EBUSY;
++ goto out;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (unlikely(res == NULL)) {
++ dev_err(&pdev->dev, "hdmi_cec:No HDMI irq line provided\n");
++ goto err_out_chrdev;
++ }
++ spin_lock_init(&hdmi_cec_data.irq_lock);
++
++ err = devm_request_irq(&pdev->dev, irq, mxc_hdmi_cec_isr, IRQF_SHARED,
++ dev_name(&pdev->dev), &hdmi_cec_data);
++ if (err < 0) {
++ dev_err(&pdev->dev, "hdmi_cec:Unable to request irq: %d\n", err);
++ goto err_out_chrdev;
++ }
++
++ hdmi_cec_class = class_create(THIS_MODULE, "mxc_hdmi_cec");
++ if (IS_ERR(hdmi_cec_class)) {
++ err = PTR_ERR(hdmi_cec_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(hdmi_cec_class, NULL, MKDEV(hdmi_cec_major, 0),
++ NULL, "mxc_hdmi_cec");
++ if (IS_ERR(temp_class)) {
++ err = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "can't get/select CEC pinctrl\n");
++ goto err_out_class;
++ }
++
++ init_waitqueue_head(&hdmi_cec_queue);
++ init_waitqueue_head(&tx_cec_queue);
++
++ INIT_LIST_HEAD(&head);
++
++ mutex_init(&hdmi_cec_data.lock);
++ hdmi_cec_data.Logical_address = 15;
++ hdmi_cec_data.tx_answer = CEC_TX_AVAIL;
++ platform_set_drvdata(pdev, &hdmi_cec_data);
++ INIT_DELAYED_WORK(&hdmi_cec_data.hdmi_cec_work, mxc_hdmi_cec_worker);
++
++ dev_info(&pdev->dev, "HDMI CEC initialized\n");
++ goto out;
++
++err_out_class:
++ device_destroy(hdmi_cec_class, MKDEV(hdmi_cec_major, 0));
++ class_destroy(hdmi_cec_class);
++err_out_chrdev:
++ unregister_chrdev(hdmi_cec_major, "mxc_hdmi_cec");
++out:
++ return err;
++}
++
++static int hdmi_cec_dev_remove(struct platform_device *pdev)
++{
++ if (hdmi_cec_data.cec_state)
++ hdmi_stop_device();
++ if (hdmi_cec_major > 0) {
++ device_destroy(hdmi_cec_class, MKDEV(hdmi_cec_major, 0));
++ class_destroy(hdmi_cec_class);
++ unregister_chrdev(hdmi_cec_major, "mxc_hdmi_cec");
++ hdmi_cec_major = 0;
++}
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_cec_match[] = {
++ { .compatible = "fsl,imx6q-hdmi-cec", },
++ { .compatible = "fsl,imx6dl-hdmi-cec", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_hdmi_cec_driver = {
++ .probe = hdmi_cec_dev_probe,
++ .remove = hdmi_cec_dev_remove,
++ .driver = {
++ .name = "mxc_hdmi_cec",
++ .of_match_table = imx_hdmi_cec_match,
++ },
++};
++
++module_platform_driver(mxc_hdmi_cec_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Linux HDMI CEC driver for Freescale i.MX/MXC");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:mxc_hdmi_cec");
++
+diff -Nur linux-3.10.30.orig/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h linux-linaro-stable-mx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h
+--- linux-3.10.30.orig/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h 2014-05-15 20:33:58.650018564 +0200
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef _HDMICEC_H_
++#define _HDMICEC_H_
++#include <linux/ioctl.h>
++
++/*
++ * Ioctl definitions
++ */
++
++/* Use 'k' as magic number */
++#define HDMICEC_IOC_MAGIC 'H'
++/*
++ * S means "Set" through a ptr,
++ * T means "Tell" directly with the argument value
++ * G means "Get": reply by setting through a pointer
++ * Q means "Query": response is on the return value
++ * X means "eXchange": G and S atomically
++ * H means "sHift": T and Q atomically
++ */
++#define HDMICEC_IOC_SETLOGICALADDRESS \
++ _IOW(HDMICEC_IOC_MAGIC, 1, unsigned char)
++#define HDMICEC_IOC_STARTDEVICE _IO(HDMICEC_IOC_MAGIC, 2)
++#define HDMICEC_IOC_STOPDEVICE _IO(HDMICEC_IOC_MAGIC, 3)
++#define HDMICEC_IOC_GETPHYADDRESS \
++ _IOR(HDMICEC_IOC_MAGIC, 4, unsigned char[4])
++
++#endif /* !_HDMICEC_H_ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,491 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_calc_stripes_sizes.c
++ *
++ * @brief IPU IC functions
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/math64.h>
++
++#define BPP_32 0
++#define BPP_16 3
++#define BPP_8 5
++#define BPP_24 1
++#define BPP_12 4
++#define BPP_18 2
++
++static u32 truncate(u32 up, /* 0: down; else: up */
++ u64 a, /* must be non-negative */
++ u32 b)
++{
++ u32 d;
++ u64 div;
++ div = div_u64(a, b);
++ d = b * (div >> 32);
++ if (up && (a > (((u64)d) << 32)))
++ return d+b;
++ else
++ return d;
++}
++
++static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
++{/* return input_f */
++ unsigned int f_calculated = 0;
++ switch (pfs) {
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV444P:
++ f_calculated = 16;
++ break;
++
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ f_calculated = 8;
++ break;
++
++ case IPU_PIX_FMT_NV12:
++ f_calculated = 8;
++ break;
++
++ default:
++ f_calculated = 0;
++ break;
++
++ }
++ if (!f_calculated) {
++ switch (bpp) {
++ case BPP_32:
++ f_calculated = 2;
++ break;
++
++ case BPP_16:
++ f_calculated = 4;
++ break;
++
++ case BPP_8:
++ case BPP_24:
++ f_calculated = 8;
++ break;
++
++ case BPP_12:
++ f_calculated = 16;
++ break;
++
++ case BPP_18:
++ f_calculated = 32;
++ break;
++
++ default:
++ f_calculated = 0;
++ break;
++ }
++ }
++ return f_calculated;
++}
++
++
++static unsigned int m_calc(unsigned int pfs)
++{
++ unsigned int m_calculated = 0;
++ switch (pfs) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV444P:
++ m_calculated = 16;
++ break;
++
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ m_calculated = 8;
++ break;
++
++ default:
++ m_calculated = 8;
++ break;
++
++ }
++ return m_calculated;
++}
++
++static int calc_split_resize_coeffs(unsigned int inSize, unsigned int outSize,
++ unsigned int *resizeCoeff,
++ unsigned int *downsizeCoeff)
++{
++ uint32_t tempSize;
++ uint32_t tempDownsize;
++
++ if (inSize > 4096) {
++ pr_debug("IC input size(%d) cannot exceed 4096\n",
++ inSize);
++ return -EINVAL;
++ }
++
++ if (outSize > 1024) {
++ pr_debug("IC output size(%d) cannot exceed 1024\n",
++ outSize);
++ return -EINVAL;
++ }
++
++ if ((outSize << 3) < inSize) {
++ pr_debug("IC cannot downsize more than 8:1\n");
++ return -EINVAL;
++ }
++
++ /* Compute downsizing coefficient */
++ /* Output of downsizing unit cannot be more than 1024 */
++ tempDownsize = 0;
++ tempSize = inSize;
++ while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
++ (tempDownsize < 2)) {
++ tempSize >>= 1;
++ tempDownsize++;
++ }
++ *downsizeCoeff = tempDownsize;
++
++ /* compute resizing coefficient using the following equation:
++ resizeCoeff = M*(SI -1)/(SO - 1)
++ where M = 2^13, SI - input size, SO - output size */
++ *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
++ if (*resizeCoeff >= 16384L) {
++ pr_debug("Overflow on IC resize coefficient.\n");
++ return -EINVAL;
++ }
++
++ pr_debug("resizing from %u -> %u pixels, "
++ "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
++ *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
++ ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
++
++ return 0;
++}
++
++/* Stripe parameters calculator */
++/**************************************************************************
++Notes:
++MSW = the maximal width allowed for a stripe
++ i.MX31: 720, i.MX35: 800, i.MX37/51/53: 1024
++cirr = the maximal inverse resizing ratio for which overlap in the input
++ is requested; typically cirr~2
++flags
++ bit 0 - equal_stripes
++ 0 each stripe is allowed to have independent parameters
++ for maximal image quality
++ 1 the stripes are requested to have identical parameters
++ (except the base address), for maximal performance
++ bit 1 - vertical/horizontal
++ 0 horizontal
++ 1 vertical
++
++If performance is the top priority (above image quality)
++ Avoid overlap, by setting CIRR = 0
++ This will also force effectively identical_stripes = 1
++ Choose IF & OF that corresponds to the same IOX/SX for both stripes
++ Choose IFW & OFW such that
++ IFW/IM, IFW/IF, OFW/OM, OFW/OF are even integers
++ The function returns an error status:
++ 0: no error
++ 1: invalid input parameters -> aborted without result
++ Valid parameters should satisfy the following conditions
++ IFW <= OFW, otherwise downsizing is required
++ - which is not supported yet
++ 4 <= IFW,OFW, so some interpolation may be needed even without overlap
++ IM, OM, IF, OF should not vanish
++ 2*IF <= IFW
++ so the frame can be split to two equal stripes, even without overlap
++ 2*(OF+IF/irr_opt) <= OFW
++ so a valid positive INW exists even for equal stripes
++ OF <= MSW, otherwise, the left stripe cannot be sufficiently large
++ MSW < OFW, so splitting to stripes is required
++ OFW <= 2*MSW, so two stripes are sufficient
++ (this also implies that 2<=MSW)
++ 2: OF is not a multiple of OM - not fully-supported yet
++ Output is produced but OW is not guaranited to be a multiple of OM
++ 4: OFW reduced to be a multiple of OM
++ 8: CIRR > 1: truncated to 1
++ Overlap is not supported (and not needed) y for upsizing)
++**************************************************************************/
++int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
++ /* input frame width;>1 */
++ unsigned int output_frame_width, /* output frame width; >1 */
++ const unsigned int maximal_stripe_width,
++ /* the maximal width allowed for a stripe */
++ const unsigned long long cirr, /* see above */
++ const unsigned int flags, /* see above */
++ u32 input_pixelformat,/* pixel format after of read channel*/
++ u32 output_pixelformat,/* pixel format after of write channel*/
++ struct stripe_param *left,
++ struct stripe_param *right)
++{
++ const unsigned int irr_frac_bits = 13;
++ const unsigned long irr_steps = 1 << irr_frac_bits;
++ const u64 dirr = ((u64)1) << (32 - 2);
++ /* The maximum relative difference allowed between the irrs */
++ const u64 cr = ((u64)4) << 32;
++ /* The importance ratio between the two terms in the cost function below */
++
++ unsigned int status;
++ unsigned int temp;
++ unsigned int onw_min;
++ unsigned int inw = 0, onw = 0, inw_best = 0;
++ /* number of pixels in the left stripe NOT hidden by the right stripe */
++ u64 irr_opt; /* the optimal inverse resizing ratio */
++ u64 rr_opt; /* the optimal resizing ratio = 1/irr_opt*/
++ u64 dinw; /* the misalignment between the stripes */
++ /* (measured in units of input columns) */
++ u64 difwl, difwr = 0;
++ /* The number of input columns not reflected in the output */
++ /* the resizing ratio used for the right stripe is */
++ /* left->irr and right->irr respectively */
++ u64 cost, cost_min;
++ u64 div; /* result of division */
++ bool equal_stripes = (flags & 0x1) != 0;
++ bool vertical = (flags & 0x2) != 0;
++
++ unsigned int input_m, input_f, output_m, output_f; /* parameters for upsizing by stripes */
++ unsigned int resize_coeff;
++ unsigned int downsize_coeff;
++
++ status = 0;
++
++ if (vertical) {
++ input_f = 2;
++ input_m = 8;
++ output_f = 8;
++ output_m = 2;
++ } else {
++ input_f = f_calc(input_pixelformat, 0, NULL);
++ input_m = m_calc(input_pixelformat);
++ output_f = input_m;
++ output_m = m_calc(output_pixelformat);
++ }
++ if ((input_frame_width < 4) || (output_frame_width < 4))
++ return 1;
++
++ irr_opt = div_u64((((u64)(input_frame_width - 1)) << 32),
++ (output_frame_width - 1));
++ rr_opt = div_u64((((u64)(output_frame_width - 1)) << 32),
++ (input_frame_width - 1));
++
++ if ((input_m == 0) || (output_m == 0) || (input_f == 0) || (output_f == 0)
++ || (input_frame_width < (2 * input_f))
++ || ((((u64)output_frame_width) << 32) <
++ (2 * ((((u64)output_f) << 32) + (input_f * rr_opt))))
++ || (maximal_stripe_width < output_f)
++ || (output_frame_width <= maximal_stripe_width)
++ || ((2 * maximal_stripe_width) < output_frame_width))
++ return 1;
++
++ if (output_f % output_m)
++ status += 2;
++
++ temp = truncate(0, (((u64)output_frame_width) << 32), output_m);
++ if (temp < output_frame_width) {
++ output_frame_width = temp;
++ status += 4;
++ }
++
++ pr_debug("---------------->\n"
++ "if = %d\n"
++ "im = %d\n"
++ "of = %d\n"
++ "om = %d\n"
++ "irr_opt = %llu\n"
++ "rr_opt = %llu\n"
++ "cirr = %llu\n"
++ "pixel in = %08x\n"
++ "pixel out = %08x\n"
++ "ifw = %d\n"
++ "ofwidth = %d\n",
++ input_f,
++ input_m,
++ output_f,
++ output_m,
++ irr_opt,
++ rr_opt,
++ cirr,
++ input_pixelformat,
++ output_pixelformat,
++ input_frame_width,
++ output_frame_width
++ );
++
++ if (equal_stripes) {
++ if ((irr_opt > cirr) /* overlap in the input is not requested */
++ && ((input_frame_width % (input_m << 1)) == 0)
++ && ((input_frame_width % (input_f << 1)) == 0)
++ && ((output_frame_width % (output_m << 1)) == 0)
++ && ((output_frame_width % (output_f << 1)) == 0)) {
++ /* without overlap */
++ left->input_width = right->input_width = right->input_column =
++ input_frame_width >> 1;
++ left->output_width = right->output_width = right->output_column =
++ output_frame_width >> 1;
++ left->input_column = 0;
++ left->output_column = 0;
++ div = div_u64(((((u64)irr_steps) << 32) *
++ (right->input_width - 1)), (right->output_width - 1));
++ left->irr = right->irr = truncate(0, div, 1);
++ } else { /* with overlap */
++ onw = truncate(0, (((u64)output_frame_width - 1) << 32) >> 1,
++ output_f);
++ inw = truncate(0, onw * irr_opt, input_f);
++ /* this is the maximal inw which allows the same resizing ratio */
++ /* in both stripes */
++ onw = truncate(1, (inw * rr_opt), output_f);
++ div = div_u64((((u64)(irr_steps * inw)) <<
++ 32), onw);
++ left->irr = right->irr = truncate(0, div, 1);
++ left->output_width = right->output_width =
++ output_frame_width - onw;
++ /* These are valid assignments for output_width, */
++ /* assuming output_f is a multiple of output_m */
++ div = (((u64)(left->output_width-1) * (left->irr)) << 32);
++ div = (((u64)1) << 32) + div_u64(div, irr_steps);
++
++ left->input_width = right->input_width = truncate(1, div, input_m);
++
++ div = div_u64((((u64)((right->output_width - 1) * right->irr)) <<
++ 32), irr_steps);
++ difwr = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
++ div = div_u64((difwr + (((u64)input_f) << 32)), 2);
++ left->input_column = truncate(0, div, input_f);
++
++
++ /* This splits the truncated input columns evenly */
++ /* between the left and right margins */
++ right->input_column = left->input_column + inw;
++ left->output_column = 0;
++ right->output_column = onw;
++ }
++ if (left->input_width > left->output_width) {
++ if (calc_split_resize_coeffs(left->input_width,
++ left->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++ left->irr = right->irr =
++ (downsize_coeff << 14) | resize_coeff;
++ }
++ pr_debug("inw %d, onw %d, ilw %d, ilc %d, olw %d,"
++ " irw %d, irc %d, orw %d, orc %d, "
++ "difwr %llu, lirr %u\n",
++ inw, onw, left->input_width,
++ left->input_column, left->output_width,
++ right->input_width, right->input_column,
++ right->output_width,
++ right->output_column, difwr, left->irr);
++ } else { /* independent stripes */
++ onw_min = output_frame_width - maximal_stripe_width;
++ /* onw is a multiple of output_f, in the range */
++ /* [max(output_f,output_frame_width-maximal_stripe_width),*/
++ /*min(output_frame_width-2,maximal_stripe_width)] */
++ /* definitely beyond the cost of any valid setting */
++ cost_min = (((u64)input_frame_width) << 32) + cr;
++ onw = truncate(0, ((u64)maximal_stripe_width), output_f);
++ if (output_frame_width - onw == 1)
++ onw -= output_f; /* => onw and output_frame_width-1-onw are positive */
++ inw = truncate(0, onw * irr_opt, input_f);
++ /* this is the maximal inw which allows the same resizing ratio */
++ /* in both stripes */
++ onw = truncate(1, inw * rr_opt, output_f);
++ do {
++ div = div_u64((((u64)(irr_steps * inw)) << 32), onw);
++ left->irr = truncate(0, div, 1);
++ div = div_u64((((u64)(onw * left->irr)) << 32),
++ irr_steps);
++ dinw = (((u64)inw) << 32) - div;
++
++ div = div_u64((((u64)((output_frame_width - 1 - onw) * left->irr)) <<
++ 32), irr_steps);
++
++ difwl = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
++
++ cost = difwl + (((u64)(cr * dinw)) >> 32);
++
++ if (cost < cost_min) {
++ inw_best = inw;
++ cost_min = cost;
++ }
++
++ inw -= input_f;
++ onw = truncate(1, inw * rr_opt, output_f);
++ /* This is the minimal onw which allows the same resizing ratio */
++ /* in both stripes */
++ } while (onw >= onw_min);
++
++ inw = inw_best;
++ onw = truncate(1, inw * rr_opt, output_f);
++ div = div_u64((((u64)(irr_steps * inw)) << 32), onw);
++ left->irr = truncate(0, div, 1);
++
++ left->output_width = onw;
++ right->output_width = output_frame_width - onw;
++ /* These are valid assignments for output_width, */
++ /* assuming output_f is a multiple of output_m */
++ left->input_width = truncate(1, ((u64)(inw + 1)) << 32, input_m);
++ right->input_width = truncate(1, ((u64)(input_frame_width - inw)) <<
++ 32, input_m);
++
++ div = div_u64((((u64)(irr_steps * (input_frame_width - 1 - inw))) <<
++ 32), (right->output_width - 1));
++ right->irr = truncate(0, div, 1);
++ temp = truncate(0, ((u64)left->irr) * ((((u64)1) << 32) + dirr), 1);
++ if (temp < right->irr)
++ right->irr = temp;
++ div = div_u64(((u64)((right->output_width - 1) * right->irr) <<
++ 32), irr_steps);
++ difwr = (u64)(input_frame_width - 1 - inw) - div;
++
++
++ div = div_u64((difwr + (((u64)input_f) << 32)), 2);
++ left->input_column = truncate(0, div, input_f);
++
++ /* This splits the truncated input columns evenly */
++ /* between the left and right margins */
++ right->input_column = left->input_column + inw;
++ left->output_column = 0;
++ right->output_column = onw;
++ if (left->input_width > left->output_width) {
++ if (calc_split_resize_coeffs(left->input_width,
++ left->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++ left->irr = (downsize_coeff << 14) | resize_coeff;
++ }
++ if (right->input_width > right->output_width) {
++ if (calc_split_resize_coeffs(right->input_width,
++ right->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++ right->irr = (downsize_coeff << 14) | resize_coeff;
++ }
++ }
++ return status;
++}
++EXPORT_SYMBOL(ipu_calc_stripes_sizes);
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_capture.c linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_capture.c
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_capture.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_capture.c 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,819 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_capture.c
++ *
++ * @brief IPU capture dase functions
++ *
++ * @ingroup IPU
++ */
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include "ipu_prv.h"
++#include "ipu_regs.h"
++
++/*!
++ * _ipu_csi_mclk_set
++ *
++ * @param ipu ipu handler
++ * @param pixel_clk desired pixel clock frequency in Hz
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_mclk_set(struct ipu_soc *ipu, uint32_t pixel_clk, uint32_t csi)
++{
++ uint32_t temp;
++ uint32_t div_ratio;
++
++ div_ratio = (clk_get_rate(ipu->ipu_clk) / pixel_clk) - 1;
++
++ if (div_ratio > 0xFF || div_ratio < 0) {
++ dev_dbg(ipu->dev, "value of pixel_clk extends normal range\n");
++ return -EINVAL;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SENS_CONF);
++ temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
++ ipu_csi_write(ipu, csi, temp |
++ (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
++ CSI_SENS_CONF);
++
++ return 0;
++}
++
++/*!
++ * ipu_csi_init_interface
++ * Sets initial values for the CSI registers.
++ * The width and height of the sensor and the actual frame size will be
++ * set to the same values.
++ * @param ipu ipu handler
++ * @param width Sensor width
++ * @param height Sensor height
++ * @param pixel_fmt pixel format
++ * @param cfg_param ipu_csi_signal_cfg_t structure
++ * @param csi csi 0 or csi 1
++ *
++ * @return 0 for success, -EINVAL for error
++ */
++int32_t
++ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
++ uint32_t pixel_fmt, ipu_csi_signal_cfg_t cfg_param)
++{
++ uint32_t data = 0;
++ uint32_t csi = cfg_param.csi;
++
++ /* Set SENS_DATA_FORMAT bits (8, 9 and 10)
++ RGB or YUV444 is 0 which is current value in data so not set
++ explicitly
++ This is also the default value if attempts are made to set it to
++ something invalid. */
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_YUYV:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
++ break;
++ case IPU_PIX_FMT_UYVY:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
++ break;
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_BGR24:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
++ break;
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_GENERIC_16:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
++ break;
++ case IPU_PIX_FMT_RGB565:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
++ break;
++ case IPU_PIX_FMT_RGB555:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* Set the CSI_SENS_CONF register remaining fields */
++ data |= cfg_param.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
++ cfg_param.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
++ cfg_param.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
++ cfg_param.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
++ cfg_param.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
++ cfg_param.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
++ cfg_param.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
++ cfg_param.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
++ cfg_param.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
++ cfg_param.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
++ cfg_param.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu_csi_write(ipu, csi, data, CSI_SENS_CONF);
++
++ /* Setup the mclk */
++ if (cfg_param.mclk > 0)
++ _ipu_csi_mclk_set(ipu, cfg_param.mclk, csi);
++
++ /* Setup sensor frame size */
++ ipu_csi_write(ipu, csi, (width - 1) | (height - 1) << 16, CSI_SENS_FRM_SIZE);
++
++ /* Set CCIR registers */
++ if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) {
++ ipu_csi_write(ipu, csi, 0x40030, CSI_CCIR_CODE_1);
++ ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
++ } else if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) {
++ if (width == 720 && height == 625) {
++ /* PAL case */
++ /*
++ * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
++ * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
++ */
++ ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_1);
++ /*
++ * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
++ * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
++ */
++ ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_2);
++ ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
++
++ } else if (width == 720 && height == 525) {
++ /* NTSC case */
++ /*
++ * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
++ * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
++ */
++ ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_1);
++ /*
++ * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
++ * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
++ */
++ ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_2);
++ ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
++ } else {
++ dev_err(ipu->dev, "Unsupported CCIR656 interlaced "
++ "video mode\n");
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return -EINVAL;
++ }
++ _ipu_csi_ccir_err_detection_enable(ipu, csi);
++ } else if ((cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR)) {
++ ipu_csi_write(ipu, csi, 0x40030, CSI_CCIR_CODE_1);
++ ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3);
++ _ipu_csi_ccir_err_detection_enable(ipu, csi);
++ } else if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_GATED_CLK) ||
++ (cfg_param.clk_mode == IPU_CSI_CLK_MODE_NONGATED_CLK)) {
++ _ipu_csi_ccir_err_detection_disable(ipu, csi);
++ }
++
++ dev_dbg(ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
++ ipu_csi_read(ipu, csi, CSI_SENS_CONF));
++ dev_dbg(ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
++ ipu_csi_read(ipu, csi, CSI_ACT_FRM_SIZE));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_csi_init_interface);
++
++/*!
++ * ipu_csi_get_sensor_protocol
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns sensor protocol
++ */
++int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi)
++{
++ int ret;
++ _ipu_get(ipu);
++ ret = (ipu_csi_read(ipu, csi, CSI_SENS_CONF) &
++ CSI_SENS_CONF_SENS_PRTCL_MASK) >>
++ CSI_SENS_CONF_SENS_PRTCL_SHIFT;
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_csi_get_sensor_protocol);
++
++/*!
++ * ipu_csi_enable_mclk
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ * @param flag true to enable mclk, false to disable mclk
++ * @param wait true to wait 100ms make clock stable, false not wait
++ *
++ * @return Returns 0 on success
++ */
++int ipu_csi_enable_mclk(struct ipu_soc *ipu, int csi, bool flag, bool wait)
++{
++ /* Return immediately if there is no csi_clk to manage */
++ if (ipu->csi_clk[csi] == NULL)
++ return 0;
++
++ if (flag) {
++ clk_enable(ipu->csi_clk[csi]);
++ if (wait == true)
++ msleep(10);
++ } else {
++ clk_disable(ipu->csi_clk[csi]);
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_csi_enable_mclk);
++
++/*!
++ * ipu_csi_get_window_size
++ *
++ * @param ipu ipu handler
++ * @param width pointer to window width
++ * @param height pointer to window height
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi)
++{
++ uint32_t reg;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ reg = ipu_csi_read(ipu, csi, CSI_ACT_FRM_SIZE);
++ *width = (reg & 0xFFFF) + 1;
++ *height = (reg >> 16 & 0xFFFF) + 1;
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_get_window_size);
++
++/*!
++ * ipu_csi_set_window_size
++ *
++ * @param ipu ipu handler
++ * @param width window width
++ * @param height window height
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi)
++{
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu_csi_write(ipu, csi, (width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_set_window_size);
++
++/*!
++ * ipu_csi_set_window_pos
++ *
++ * @param ipu ipu handler
++ * @param left uint32 window x start
++ * @param top uint32 window y start
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi)
++{
++ uint32_t temp;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
++ temp |= ((top << CSI_VSC_SHIFT) | (left << CSI_HSC_SHIFT));
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_set_window_pos);
++
++/*!
++ * _ipu_csi_horizontal_downsize_enable
++ * Enable horizontal downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_horizontal_downsize_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp |= CSI_HORI_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_horizontal_downsize_disable
++ * Disable horizontal downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_horizontal_downsize_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~CSI_HORI_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_vertical_downsize_enable
++ * Enable vertical downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_vertical_downsize_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp |= CSI_VERT_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_vertical_downsize_disable
++ * Disable vertical downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_vertical_downsize_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~CSI_VERT_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_set_test_generator
++ *
++ * @param ipu ipu handler
++ * @param active 1 for active and 0 for inactive
++ * @param r_value red value for the generated pattern of even pixel
++ * @param g_value green value for the generated pattern of even
++ * pixel
++ * @param b_value blue value for the generated pattern of even pixel
++ * @param pixel_clk desired pixel clock frequency in Hz
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
++ uint32_t g_value, uint32_t b_value, uint32_t pix_clk, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_TST_CTRL);
++
++ if (active == false) {
++ temp &= ~CSI_TEST_GEN_MODE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_TST_CTRL);
++ } else {
++ /* Set sensb_mclk div_ratio*/
++ _ipu_csi_mclk_set(ipu, pix_clk, csi);
++
++ temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
++ CSI_TEST_GEN_B_MASK);
++ temp |= CSI_TEST_GEN_MODE_EN;
++ temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
++ (g_value << CSI_TEST_GEN_G_SHIFT) |
++ (b_value << CSI_TEST_GEN_B_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_TST_CTRL);
++ }
++}
++
++/*!
++ * _ipu_csi_ccir_err_detection_en
++ * Enable error detection and correction for
++ * CCIR interlaced mode with protection bit.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_CCIR_CODE_1);
++ temp |= CSI_CCIR_ERR_DET_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_CCIR_CODE_1);
++
++}
++
++/*!
++ * _ipu_csi_ccir_err_detection_disable
++ * Disable error detection and correction for
++ * CCIR interlaced mode with protection bit.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_CCIR_CODE_1);
++ temp &= ~CSI_CCIR_ERR_DET_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_CCIR_CODE_1);
++
++}
++
++/*!
++ * _ipu_csi_set_mipi_di
++ *
++ * @param ipu ipu handler
++ * @param num MIPI data identifier 0-3 handled by CSI
++ * @param di_val data identifier value
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (di_val > 0xFFL) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_MIPI_DI);
++
++ switch (num) {
++ case IPU_CSI_MIPI_DI0:
++ temp &= ~CSI_MIPI_DI0_MASK;
++ temp |= (di_val << CSI_MIPI_DI0_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI1:
++ temp &= ~CSI_MIPI_DI1_MASK;
++ temp |= (di_val << CSI_MIPI_DI1_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI2:
++ temp &= ~CSI_MIPI_DI2_MASK;
++ temp |= (di_val << CSI_MIPI_DI2_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI3:
++ temp &= ~CSI_MIPI_DI3_MASK;
++ temp |= (di_val << CSI_MIPI_DI3_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ default:
++ retval = -EINVAL;
++ }
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_csi_set_skip_isp
++ *
++ * @param ipu ipu handler
++ * @param skip select frames to be skipped and set the
++ * correspond bits to 1
++ * @param max_ratio number of frames in a skipping set and the
++ * maximum value of max_ratio is 5
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_skip_isp(struct ipu_soc *ipu, uint32_t skip, uint32_t max_ratio, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (max_ratio > 5) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SKIP);
++ temp &= ~(CSI_MAX_RATIO_SKIP_ISP_MASK | CSI_SKIP_ISP_MASK);
++ temp |= (max_ratio << CSI_MAX_RATIO_SKIP_ISP_SHIFT) |
++ (skip << CSI_SKIP_ISP_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_SKIP);
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_csi_set_skip_smfc
++ *
++ * @param ipu ipu handler
++ * @param skip select frames to be skipped and set the
++ * correspond bits to 1
++ * @param max_ratio number of frames in a skipping set and the
++ * maximum value of max_ratio is 5
++ * @param id csi to smfc skipping id
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_skip_smfc(struct ipu_soc *ipu, uint32_t skip,
++ uint32_t max_ratio, uint32_t id, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (max_ratio > 5 || id > 3) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SKIP);
++ temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
++ CSI_SKIP_SMFC_MASK);
++ temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
++ (id << CSI_ID_2_SKIP_SHIFT) |
++ (skip << CSI_SKIP_SMFC_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_SKIP);
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_smfc_init
++ * Map CSI frames to IDMAC channels.
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param mipi_id mipi id number 0-3
++ * @param csi csi0 or csi1
++ */
++void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_MAP);
++
++ switch (channel) {
++ case CSI_MEM0:
++ temp &= ~SMFC_MAP_CH0_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH0_SHIFT;
++ break;
++ case CSI_MEM1:
++ temp &= ~SMFC_MAP_CH1_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH1_SHIFT;
++ break;
++ case CSI_MEM2:
++ temp &= ~SMFC_MAP_CH2_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH2_SHIFT;
++ break;
++ case CSI_MEM3:
++ temp &= ~SMFC_MAP_CH3_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH3_SHIFT;
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_MAP);
++}
++
++/*!
++ * _ipu_smfc_set_wmc
++ * Caution: The number of required channels, the enabled channels
++ * and the FIFO size per channel are configured restrictedly.
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param set set 1 or clear 0
++ * @param level water mark level when FIFO is on the
++ * relative size
++ */
++void _ipu_smfc_set_wmc(struct ipu_soc *ipu, ipu_channel_t channel, bool set, uint32_t level)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_WMC);
++
++ switch (channel) {
++ case CSI_MEM0:
++ if (set == true) {
++ temp &= ~SMFC_WM0_SET_MASK;
++ temp |= level << SMFC_WM0_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM0_CLR_MASK;
++ temp |= level << SMFC_WM0_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM1:
++ if (set == true) {
++ temp &= ~SMFC_WM1_SET_MASK;
++ temp |= level << SMFC_WM1_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM1_CLR_MASK;
++ temp |= level << SMFC_WM1_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM2:
++ if (set == true) {
++ temp &= ~SMFC_WM2_SET_MASK;
++ temp |= level << SMFC_WM2_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM2_CLR_MASK;
++ temp |= level << SMFC_WM2_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM3:
++ if (set == true) {
++ temp &= ~SMFC_WM3_SET_MASK;
++ temp |= level << SMFC_WM3_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM3_CLR_MASK;
++ temp |= level << SMFC_WM3_CLR_SHIFT;
++ }
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_WMC);
++}
++
++/*!
++ * _ipu_smfc_set_burst_size
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param bs burst size of IDMAC channel,
++ * the value programmed here shoud be BURST_SIZE-1
++ */
++void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_BS);
++
++ switch (channel) {
++ case CSI_MEM0:
++ temp &= ~SMFC_BS0_MASK;
++ temp |= bs << SMFC_BS0_SHIFT;
++ break;
++ case CSI_MEM1:
++ temp &= ~SMFC_BS1_MASK;
++ temp |= bs << SMFC_BS1_SHIFT;
++ break;
++ case CSI_MEM2:
++ temp &= ~SMFC_BS2_MASK;
++ temp |= bs << SMFC_BS2_SHIFT;
++ break;
++ case CSI_MEM3:
++ temp &= ~SMFC_BS3_MASK;
++ temp |= bs << SMFC_BS3_SHIFT;
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_BS);
++}
++
++/*!
++ * _ipu_csi_init
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi)
++{
++ uint32_t csi_sens_conf, csi_dest;
++ int retval = 0;
++
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ csi_dest = CSI_DATA_DEST_IDMAC;
++ break;
++ case CSI_PRP_ENC_MEM:
++ case CSI_PRP_VF_MEM:
++ csi_dest = CSI_DATA_DEST_IC;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ csi_sens_conf = ipu_csi_read(ipu, csi, CSI_SENS_CONF);
++ csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
++ ipu_csi_write(ipu, csi, csi_sens_conf | (csi_dest <<
++ CSI_SENS_CONF_DATA_DEST_SHIFT), CSI_SENS_CONF);
++err:
++ return retval;
++}
++
++/*!
++ * csi_irq_handler
++ *
++ * @param irq interrupt id
++ * @param dev_id pointer to ipu handler
++ *
++ * @return Returns if irq is handled
++ */
++static irqreturn_t csi_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_soc *ipu = dev_id;
++ struct completion *comp = &ipu->csi_comp;
++
++ complete(comp);
++ return IRQ_HANDLED;
++}
++
++/*!
++ * _ipu_csi_wait4eof
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel
++ *
++ */
++void _ipu_csi_wait4eof(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int ret;
++ int irq = 0;
++
++ if (channel == CSI_MEM0)
++ irq = IPU_IRQ_CSI0_OUT_EOF;
++ else if (channel == CSI_MEM1)
++ irq = IPU_IRQ_CSI1_OUT_EOF;
++ else if (channel == CSI_MEM2)
++ irq = IPU_IRQ_CSI2_OUT_EOF;
++ else if (channel == CSI_MEM3)
++ irq = IPU_IRQ_CSI3_OUT_EOF;
++ else if (channel == CSI_PRP_ENC_MEM)
++ irq = IPU_IRQ_PRP_ENC_OUT_EOF;
++ else if (channel == CSI_PRP_VF_MEM)
++ irq = IPU_IRQ_PRP_VF_OUT_EOF;
++ else{
++ dev_err(ipu->dev, "Not a CSI channel\n");
++ return;
++ }
++
++ init_completion(&ipu->csi_comp);
++ ret = ipu_request_irq(ipu, irq, csi_irq_handler, 0, NULL, ipu);
++ if (ret < 0) {
++ dev_err(ipu->dev, "CSI irq %d in use\n", irq);
++ return;
++ }
++ ret = wait_for_completion_timeout(&ipu->csi_comp, msecs_to_jiffies(500));
++ ipu_free_irq(ipu, irq, ipu);
++ dev_dbg(ipu->dev, "CSI stop timeout - %d * 10ms\n", 5 - ret);
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_common.c linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_common.c
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_common.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_common.c 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,3134 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_common.c
++ *
++ * @brief This file contains the IPU driver common API functions.
++ *
++ * @ingroup IPU
++ */
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/irq.h>
++#include <linux/irqdesc.h>
++#include <linux/module.h>
++#include <linux/mod_devicetable.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include <asm/cacheflush.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++static struct ipu_soc ipu_array[MXC_IPU_MAX_NUM];
++int g_ipu_hw_rev;
++
++/* Static functions */
++static irqreturn_t ipu_sync_irq_handler(int irq, void *desc);
++static irqreturn_t ipu_err_irq_handler(int irq, void *desc);
++
++static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
++{
++ return ((uint32_t) ch >> (6 * type)) & 0x3F;
++};
++
++static inline int _ipu_is_ic_chan(uint32_t dma_chan)
++{
++ return (((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) &&
++ (dma_chan != 18)));
++}
++
++static inline int _ipu_is_vdi_out_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 5);
++}
++
++static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 14 || dma_chan == 15);
++}
++
++/* Either DP BG or DP FG can be graphic window */
++static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 23 || dma_chan == 27);
++}
++
++static inline int _ipu_is_irt_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 45) && (dma_chan <= 50));
++}
++
++static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 23) && (dma_chan <= 29));
++}
++
++static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 0) && (dma_chan <= 3));
++}
++
++static inline int _ipu_is_trb_chan(uint32_t dma_chan)
++{
++ return (((dma_chan == 8) || (dma_chan == 9) ||
++ (dma_chan == 10) || (dma_chan == 13) ||
++ (dma_chan == 21) || (dma_chan == 23) ||
++ (dma_chan == 27) || (dma_chan == 28)) &&
++ (g_ipu_hw_rev >= IPU_V3DEX));
++}
++
++/*
++ * We usually use IDMAC 23 as full plane and IDMAC 27 as partial
++ * plane.
++ * IDMAC 23/24/28/41 can drive a display respectively - primary
++ * IDMAC 27 depends on IDMAC 23 - nonprimary
++ */
++static inline int _ipu_is_primary_disp_chan(uint32_t dma_chan)
++{
++ return ((dma_chan == 23) || (dma_chan == 24) ||
++ (dma_chan == 28) || (dma_chan == 41));
++}
++
++static inline int _ipu_is_sync_irq(uint32_t irq)
++{
++ /* sync interrupt register number */
++ int reg_num = irq / 32 + 1;
++
++ return ((reg_num == 1) || (reg_num == 2) || (reg_num == 3) ||
++ (reg_num == 4) || (reg_num == 7) || (reg_num == 8) ||
++ (reg_num == 11) || (reg_num == 12) || (reg_num == 13) ||
++ (reg_num == 14) || (reg_num == 15));
++}
++
++#define idma_is_valid(ch) (ch != NO_DMA)
++#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
++#define idma_is_set(ipu, reg, dma) (ipu_idmac_read(ipu, reg(dma)) & idma_mask(dma))
++#define tri_cur_buf_mask(ch) (idma_mask(ch*2) * 3)
++#define tri_cur_buf_shift(ch) (ffs(idma_mask(ch*2)) - 1)
++
++static int ipu_clk_setup_enable(struct ipu_soc *ipu,
++ struct ipu_pltfm_data *pdata)
++{
++ char pixel_clk_0[] = "ipu1_pclk_0";
++ char pixel_clk_1[] = "ipu1_pclk_1";
++ char pixel_clk_0_sel[] = "ipu1_pclk0_sel";
++ char pixel_clk_1_sel[] = "ipu1_pclk1_sel";
++ char pixel_clk_0_div[] = "ipu1_pclk0_div";
++ char pixel_clk_1_div[] = "ipu1_pclk1_div";
++ char *ipu_pixel_clk_sel[] = { "ipu1", "ipu1_di0", "ipu1_di1", };
++ char *pclk_sel;
++ struct clk *clk;
++ int ret;
++ int i;
++
++ pixel_clk_0[3] += pdata->id;
++ pixel_clk_1[3] += pdata->id;
++ pixel_clk_0_sel[3] += pdata->id;
++ pixel_clk_1_sel[3] += pdata->id;
++ pixel_clk_0_div[3] += pdata->id;
++ pixel_clk_1_div[3] += pdata->id;
++ for (i = 0; i < ARRAY_SIZE(ipu_pixel_clk_sel); i++) {
++ pclk_sel = ipu_pixel_clk_sel[i];
++ pclk_sel[3] += pdata->id;
++ }
++ dev_dbg(ipu->dev, "ipu_clk = %lu\n", clk_get_rate(ipu->ipu_clk));
++
++ clk = clk_register_mux_pix_clk(ipu->dev, pixel_clk_0_sel,
++ (const char **)ipu_pixel_clk_sel,
++ ARRAY_SIZE(ipu_pixel_clk_sel),
++ 0, pdata->id, 0, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk_register mux di0 failed");
++ return PTR_ERR(clk);
++ }
++ ipu->pixel_clk_sel[0] = clk;
++ clk = clk_register_mux_pix_clk(ipu->dev, pixel_clk_1_sel,
++ (const char **)ipu_pixel_clk_sel,
++ ARRAY_SIZE(ipu_pixel_clk_sel),
++ 0, pdata->id, 1, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk_register mux di1 failed");
++ return PTR_ERR(clk);
++ }
++ ipu->pixel_clk_sel[1] = clk;
++
++ clk = clk_register_div_pix_clk(ipu->dev, pixel_clk_0_div,
++ pixel_clk_0_sel, 0, pdata->id, 0, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk register di0 div failed");
++ return PTR_ERR(clk);
++ }
++ clk = clk_register_div_pix_clk(ipu->dev, pixel_clk_1_div,
++ pixel_clk_1_sel, CLK_SET_RATE_PARENT, pdata->id, 1, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk register di1 div failed");
++ return PTR_ERR(clk);
++ }
++
++ ipu->pixel_clk[0] = clk_register_gate_pix_clk(ipu->dev, pixel_clk_0,
++ pixel_clk_0_div, CLK_SET_RATE_PARENT,
++ pdata->id, 0, 0);
++ if (IS_ERR(ipu->pixel_clk[0])) {
++ dev_err(ipu->dev, "clk register di0 gate failed");
++ return PTR_ERR(ipu->pixel_clk[0]);
++ }
++ ipu->pixel_clk[1] = clk_register_gate_pix_clk(ipu->dev, pixel_clk_1,
++ pixel_clk_1_div, CLK_SET_RATE_PARENT,
++ pdata->id, 1, 0);
++ if (IS_ERR(ipu->pixel_clk[1])) {
++ dev_err(ipu->dev, "clk register di1 gate failed");
++ return PTR_ERR(ipu->pixel_clk[1]);
++ }
++
++ ret = clk_set_parent(ipu->pixel_clk_sel[0], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "clk set parent failed");
++ return ret;
++ }
++
++ ret = clk_set_parent(ipu->pixel_clk_sel[1], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "clk set parent failed");
++ return ret;
++ }
++
++ ipu->di_clk[0] = devm_clk_get(ipu->dev, "di0");
++ if (IS_ERR(ipu->di_clk[0])) {
++ dev_err(ipu->dev, "clk_get di0 failed");
++ return PTR_ERR(ipu->di_clk[0]);
++ }
++ ipu->di_clk[1] = devm_clk_get(ipu->dev, "di1");
++ if (IS_ERR(ipu->di_clk[1])) {
++ dev_err(ipu->dev, "clk_get di1 failed");
++ return PTR_ERR(ipu->di_clk[1]);
++ }
++
++ ipu->di_clk_sel[0] = devm_clk_get(ipu->dev, "di0_sel");
++ if (IS_ERR(ipu->di_clk_sel[0])) {
++ dev_err(ipu->dev, "clk_get di0_sel failed");
++ return PTR_ERR(ipu->di_clk_sel[0]);
++ }
++ ipu->di_clk_sel[1] = devm_clk_get(ipu->dev, "di1_sel");
++ if (IS_ERR(ipu->di_clk_sel[1])) {
++ dev_err(ipu->dev, "clk_get di1_sel failed");
++ return PTR_ERR(ipu->di_clk_sel[1]);
++ }
++
++ return 0;
++}
++
++static int ipu_mem_reset(struct ipu_soc *ipu)
++{
++ int timeout = 1000;
++
++ ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
++
++ while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
++ if (!timeout--)
++ return -ETIME;
++ msleep(1);
++ }
++
++ return 0;
++}
++
++struct ipu_soc *ipu_get_soc(int id)
++{
++ if (id >= MXC_IPU_MAX_NUM)
++ return ERR_PTR(-ENODEV);
++ else if (!ipu_array[id].online)
++ return ERR_PTR(-ENODEV);
++ else
++ return &(ipu_array[id]);
++}
++EXPORT_SYMBOL_GPL(ipu_get_soc);
++
++void _ipu_get(struct ipu_soc *ipu)
++{
++ int ret;
++
++ ret = clk_enable(ipu->ipu_clk);
++ if (ret < 0)
++ BUG();
++}
++
++void _ipu_put(struct ipu_soc *ipu)
++{
++ clk_disable(ipu->ipu_clk);
++}
++
++void ipu_disable_hsp_clk(struct ipu_soc *ipu)
++{
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_disable_hsp_clk);
++
++static struct platform_device_id imx_ipu_type[] = {
++ {
++ .name = "ipu-imx6q",
++ .driver_data = IPU_V3H,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_ipu_type);
++
++static const struct of_device_id imx_ipuv3_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ipu", .data = &imx_ipu_type[IMX6Q_IPU], },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_ipuv3_dt_ids);
++
++/*!
++ * This function is called by the driver framework to initialize the IPU
++ * hardware.
++ *
++ * @param dev The device structure for the IPU passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int ipu_probe(struct platform_device *pdev)
++{
++ struct ipu_soc *ipu;
++ struct resource *res;
++ unsigned long ipu_base;
++ const struct of_device_id *of_id =
++ of_match_device(imx_ipuv3_dt_ids, &pdev->dev);
++ struct ipu_pltfm_data *pltfm_data;
++ int ret = 0;
++ u32 bypass_reset;
++
++ dev_dbg(&pdev->dev, "<%s>\n", __func__);
++
++ pltfm_data = devm_kzalloc(&pdev->dev, sizeof(struct ipu_pltfm_data),
++ GFP_KERNEL);
++ if (!pltfm_data)
++ return -ENOMEM;
++
++ ret = of_property_read_u32(pdev->dev.of_node,
++ "bypass_reset", &bypass_reset);
++ if (ret < 0) {
++ dev_dbg(&pdev->dev, "can not get bypass_reset\n");
++ return ret;
++ }
++ pltfm_data->bypass_reset = (bool)bypass_reset;
++
++ pltfm_data->id = of_alias_get_id(pdev->dev.of_node, "ipu");
++ if (pltfm_data->id < 0) {
++ dev_dbg(&pdev->dev, "can not get alias id\n");
++ return pltfm_data->id;
++ }
++
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ pltfm_data->devtype = pdev->id_entry->driver_data;
++ g_ipu_hw_rev = pltfm_data->devtype;
++
++ ipu = &ipu_array[pltfm_data->id];
++ memset(ipu, 0, sizeof(struct ipu_soc));
++ ipu->dev = &pdev->dev;
++ ipu->pdata = pltfm_data;
++ dev_dbg(ipu->dev, "IPU rev:%d\n", g_ipu_hw_rev);
++ spin_lock_init(&ipu->int_reg_spin_lock);
++ spin_lock_init(&ipu->rdy_reg_spin_lock);
++ mutex_init(&ipu->mutex_lock);
++
++ ipu->irq_sync = platform_get_irq(pdev, 0);
++ ipu->irq_err = platform_get_irq(pdev, 1);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (!res || ipu->irq_sync < 0 || ipu->irq_err < 0) {
++ dev_err(&pdev->dev, "can't get device resources\n");
++ return -ENODEV;
++ }
++
++ if (!devm_request_mem_region(&pdev->dev, res->start,
++ resource_size(res), pdev->name))
++ return -EBUSY;
++
++ ret = devm_request_irq(&pdev->dev, ipu->irq_sync,
++ ipu_sync_irq_handler, 0, pdev->name, ipu);
++ if (ret) {
++ dev_err(ipu->dev, "request SYNC interrupt failed\n");
++ return ret;
++ }
++ ret = devm_request_irq(&pdev->dev, ipu->irq_err,
++ ipu_err_irq_handler, 0, pdev->name, ipu);
++ if (ret) {
++ dev_err(ipu->dev, "request ERR interrupt failed\n");
++ return ret;
++ }
++
++ ipu_base = res->start;
++ /* base fixup */
++ if (g_ipu_hw_rev == IPU_V3H) /* IPUv3H */
++ ipu_base += IPUV3H_REG_BASE;
++ else if (g_ipu_hw_rev == IPU_V3M) /* IPUv3M */
++ ipu_base += IPUV3M_REG_BASE;
++ else /* IPUv3D, v3E, v3EX */
++ ipu_base += IPUV3DEX_REG_BASE;
++
++ ipu->cm_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
++ ipu->ic_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
++ ipu->idmac_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
++ /* DP Registers are accessed thru the SRM */
++ ipu->dp_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
++ ipu->dc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
++ ipu->dmfc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
++ ipu->di_reg[0] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
++ ipu->di_reg[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
++ ipu->smfc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
++ ipu->csi_reg[0] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
++ ipu->csi_reg[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
++ ipu->cpmem_base = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CPMEM_REG_BASE, SZ_128K);
++ ipu->tpmem_base = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_TPM_REG_BASE, SZ_64K);
++ ipu->dc_tmpl_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
++ ipu->vdi_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
++ ipu->disp_base[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DISP1_BASE, SZ_4K);
++ if (!ipu->cm_reg || !ipu->ic_reg || !ipu->idmac_reg ||
++ !ipu->dp_reg || !ipu->dc_reg || !ipu->dmfc_reg ||
++ !ipu->di_reg[0] || !ipu->di_reg[1] || !ipu->smfc_reg ||
++ !ipu->csi_reg[0] || !ipu->csi_reg[1] || !ipu->cpmem_base ||
++ !ipu->tpmem_base || !ipu->dc_tmpl_reg || !ipu->disp_base[1]
++ || !ipu->vdi_reg)
++ return -ENOMEM;
++
++ dev_dbg(ipu->dev, "IPU CM Regs = %p\n", ipu->cm_reg);
++ dev_dbg(ipu->dev, "IPU IC Regs = %p\n", ipu->ic_reg);
++ dev_dbg(ipu->dev, "IPU IDMAC Regs = %p\n", ipu->idmac_reg);
++ dev_dbg(ipu->dev, "IPU DP Regs = %p\n", ipu->dp_reg);
++ dev_dbg(ipu->dev, "IPU DC Regs = %p\n", ipu->dc_reg);
++ dev_dbg(ipu->dev, "IPU DMFC Regs = %p\n", ipu->dmfc_reg);
++ dev_dbg(ipu->dev, "IPU DI0 Regs = %p\n", ipu->di_reg[0]);
++ dev_dbg(ipu->dev, "IPU DI1 Regs = %p\n", ipu->di_reg[1]);
++ dev_dbg(ipu->dev, "IPU SMFC Regs = %p\n", ipu->smfc_reg);
++ dev_dbg(ipu->dev, "IPU CSI0 Regs = %p\n", ipu->csi_reg[0]);
++ dev_dbg(ipu->dev, "IPU CSI1 Regs = %p\n", ipu->csi_reg[1]);
++ dev_dbg(ipu->dev, "IPU CPMem = %p\n", ipu->cpmem_base);
++ dev_dbg(ipu->dev, "IPU TPMem = %p\n", ipu->tpmem_base);
++ dev_dbg(ipu->dev, "IPU DC Template Mem = %p\n", ipu->dc_tmpl_reg);
++ dev_dbg(ipu->dev, "IPU Display Region 1 Mem = %p\n", ipu->disp_base[1]);
++ dev_dbg(ipu->dev, "IPU VDI Regs = %p\n", ipu->vdi_reg);
++
++ ipu->ipu_clk = devm_clk_get(ipu->dev, "bus");
++ if (IS_ERR(ipu->ipu_clk)) {
++ dev_err(ipu->dev, "clk_get ipu failed");
++ return PTR_ERR(ipu->ipu_clk);
++ }
++
++ /* ipu_clk is always prepared */
++ ret = clk_prepare_enable(ipu->ipu_clk);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ipu clk enable failed\n");
++ return ret;
++ }
++
++ ipu->online = true;
++ ret = ipu_clk_setup_enable(ipu, pltfm_data);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ipu clk setup failed\n");
++ ipu->online = false;
++ return ret;
++ }
++
++ platform_set_drvdata(pdev, ipu);
++
++ if (!pltfm_data->bypass_reset) {
++ ret = device_reset(&pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to reset: %d\n", ret);
++ return ret;
++ }
++
++ ipu_mem_reset(ipu);
++
++ ipu_disp_init(ipu);
++
++ /* Set MCU_T to divide MCU access window into 2 */
++ ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
++ IPU_DISP_GEN);
++ }
++
++ /* Set sync refresh channels and CSI->mem channel as high priority */
++ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
++
++ /* Enable error interrupts by default */
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
++
++ if (!pltfm_data->bypass_reset)
++ clk_disable(ipu->ipu_clk);
++
++ register_ipu_device(ipu, ipu->pdata->id);
++
++ pm_runtime_enable(&pdev->dev);
++
++ return ret;
++}
++
++int ipu_remove(struct platform_device *pdev)
++{
++ struct ipu_soc *ipu = platform_get_drvdata(pdev);
++
++ unregister_ipu_device(ipu, ipu->pdata->id);
++
++ clk_put(ipu->ipu_clk);
++
++ return 0;
++}
++
++void ipu_dump_registers(struct ipu_soc *ipu)
++{
++ dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", ipu_cm_read(ipu, IPU_CONF));
++ dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", ipu_idmac_read(ipu, IDMAC_CONF));
++ dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
++ dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
++ dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
++ dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
++ dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
++ if (g_ipu_hw_rev >= IPU_V3DEX) {
++ dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL0 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(0)));
++ dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(32)));
++ }
++ dev_dbg(ipu->dev, "DMFC_WR_CHAN = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_WR_CHAN));
++ dev_dbg(ipu->dev, "DMFC_WR_CHAN_DEF = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_WR_CHAN_DEF));
++ dev_dbg(ipu->dev, "DMFC_DP_CHAN = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_DP_CHAN));
++ dev_dbg(ipu->dev, "DMFC_DP_CHAN_DEF = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_DP_CHAN_DEF));
++ dev_dbg(ipu->dev, "DMFC_IC_CTRL = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_IC_CTRL));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
++ dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
++ dev_dbg(ipu->dev, "IPU_VDIC_VDI_FSIZE = \t0x%08X\n",
++ ipu_vdi_read(ipu, VDI_FSIZE));
++ dev_dbg(ipu->dev, "IPU_VDIC_VDI_C = \t0x%08X\n",
++ ipu_vdi_read(ipu, VDI_C));
++ dev_dbg(ipu->dev, "IPU_IC_CONF = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_CONF));
++}
++
++/*!
++ * This function is called to initialize a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID to init.
++ *
++ * @param params Input parameter containing union of channel
++ * initialization parameters.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
++{
++ int ret = 0;
++ bool bad_pixfmt;
++ uint32_t ipu_conf, reg, in_g_pixel_fmt, sec_dma;
++
++ dev_dbg(ipu->dev, "init channel = %d\n", IPU_CHAN_ID(channel));
++
++ ret = pm_runtime_get_sync(ipu->dev);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ch = %d, pm_runtime_get failed:%d!\n",
++ IPU_CHAN_ID(channel), ret);
++ dump_stack();
++ return ret;
++ }
++ /*
++ * Here, ret could be 1 if the device's runtime PM status was
++ * already 'active', so clear it to be 0.
++ */
++ ret = 0;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* Re-enable error interrupts every time a channel is initialized */
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
++
++ if (ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
++ dev_warn(ipu->dev, "Warning: channel already initialized %d\n",
++ IPU_CHAN_ID(channel));
++ }
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ if (params->csi_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ if (params->csi_mem.interlaced)
++ ipu->chan_is_interlaced[channel_2_dma(channel,
++ IPU_OUTPUT_BUFFER)] = true;
++ else
++ ipu->chan_is_interlaced[channel_2_dma(channel,
++ IPU_OUTPUT_BUFFER)] = false;
++
++ ipu->smfc_use_count++;
++ ipu->csi_channel[params->csi_mem.csi] = channel;
++
++ /*SMFC setting*/
++ if (params->csi_mem.mipi_en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_mem.csi));
++ _ipu_smfc_init(ipu, channel, params->csi_mem.mipi_vc,
++ params->csi_mem.csi);
++ _ipu_csi_set_mipi_di(ipu, params->csi_mem.mipi_vc,
++ params->csi_mem.mipi_id, params->csi_mem.csi);
++ } else {
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_mem.csi));
++ _ipu_smfc_init(ipu, channel, 0, params->csi_mem.csi);
++ }
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_mem.csi);
++ break;
++ case CSI_PRP_ENC_MEM:
++ if (params->csi_prp_enc_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++ if ((ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = CSI_PRP_ENC_MEM;
++
++ ipu->ic_use_count++;
++ ipu->csi_channel[params->csi_prp_enc_mem.csi] = channel;
++
++ if (params->csi_prp_enc_mem.mipi_en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_enc_mem.csi));
++ _ipu_csi_set_mipi_di(ipu,
++ params->csi_prp_enc_mem.mipi_vc,
++ params->csi_prp_enc_mem.mipi_id,
++ params->csi_prp_enc_mem.csi);
++ } else
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_enc_mem.csi));
++
++ /*CSI0/1 feed into IC*/
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ if (params->csi_prp_enc_mem.csi)
++ ipu_conf |= IPU_CONF_CSI_SEL;
++ else
++ ipu_conf &= ~IPU_CONF_CSI_SEL;
++
++ /*PRP skip buffer in memory, only valid when RWS_EN is true*/
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_prp_enc_mem.csi);
++ _ipu_ic_init_prpenc(ipu, params, true);
++ break;
++ case CSI_PRP_VF_MEM:
++ if (params->csi_prp_vf_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++ if ((ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = CSI_PRP_VF_MEM;
++
++ ipu->ic_use_count++;
++ ipu->csi_channel[params->csi_prp_vf_mem.csi] = channel;
++
++ if (params->csi_prp_vf_mem.mipi_en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_vf_mem.csi));
++ _ipu_csi_set_mipi_di(ipu,
++ params->csi_prp_vf_mem.mipi_vc,
++ params->csi_prp_vf_mem.mipi_id,
++ params->csi_prp_vf_mem.csi);
++ } else
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_vf_mem.csi));
++
++ /*CSI0/1 feed into IC*/
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ if (params->csi_prp_vf_mem.csi)
++ ipu_conf |= IPU_CONF_CSI_SEL;
++ else
++ ipu_conf &= ~IPU_CONF_CSI_SEL;
++
++ /*PRP skip buffer in memory, only valid when RWS_EN is true*/
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_prp_vf_mem.csi);
++ _ipu_ic_init_prpvf(ipu, params, true);
++ break;
++ case MEM_PRP_VF_MEM:
++ if (params->mem_prp_vf_mem.graphics_combine_en) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ in_g_pixel_fmt = params->mem_prp_vf_mem.in_g_pixel_fmt;
++ bad_pixfmt =
++ _ipu_ch_param_bad_alpha_pos(in_g_pixel_fmt);
++
++ if (params->mem_prp_vf_mem.alpha_chan_en) {
++ if (bad_pixfmt) {
++ dev_err(ipu->dev, "bad pixel format "
++ "for graphics plane from "
++ "ch%d\n", sec_dma);
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ _ipu_ic_init_prpvf(ipu, params, false);
++ ipu->ic_use_count++;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM) ||
++ (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
++ ipu->ic_use_count++;
++ ipu->vdi_use_count++;
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ reg &= ~FS_VDI_SRC_SEL_MASK;
++ ipu_cm_write(ipu, reg , IPU_FS_PROC_FLOW1);
++
++ if (params->mem_prp_vf_mem.graphics_combine_en)
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ _ipu_ic_init_prpvf(ipu, params, false);
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ case MEM_VDI_PRP_VF_MEM_N:
++ case MEM_VDI_MEM_P:
++ case MEM_VDI_MEM_N:
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_VDI_MEM:
++ if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = MEM_VDI_MEM;
++ ipu->ic_use_count++;
++ ipu->vdi_use_count++;
++ _ipu_ic_init_prpvf(ipu, params, false);
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_ROT_VF_MEM:
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ _ipu_ic_init_rotate_vf(ipu, params);
++ break;
++ case MEM_PRP_ENC_MEM:
++ ipu->ic_use_count++;
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++ _ipu_ic_init_prpenc(ipu, params, false);
++ break;
++ case MEM_ROT_ENC_MEM:
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ _ipu_ic_init_rotate_enc(ipu, params);
++ break;
++ case MEM_PP_MEM:
++ if (params->mem_pp_mem.graphics_combine_en) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ in_g_pixel_fmt = params->mem_pp_mem.in_g_pixel_fmt;
++ bad_pixfmt =
++ _ipu_ch_param_bad_alpha_pos(in_g_pixel_fmt);
++
++ if (params->mem_pp_mem.alpha_chan_en) {
++ if (bad_pixfmt) {
++ dev_err(ipu->dev, "bad pixel format "
++ "for graphics plane from "
++ "ch%d\n", sec_dma);
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ _ipu_ic_init_pp(ipu, params);
++ ipu->ic_use_count++;
++ break;
++ case MEM_ROT_PP_MEM:
++ _ipu_ic_init_rotate_pp(ipu, params);
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ break;
++ case MEM_DC_SYNC:
++ if (params->mem_dc_sync.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[1] = params->mem_dc_sync.di;
++ _ipu_dc_init(ipu, 1, params->mem_dc_sync.di,
++ params->mem_dc_sync.interlaced,
++ params->mem_dc_sync.out_pixel_fmt);
++ ipu->di_use_count[params->mem_dc_sync.di]++;
++ ipu->dc_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case MEM_BG_SYNC:
++ if (params->mem_dp_bg_sync.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ if (params->mem_dp_bg_sync.alpha_chan_en)
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++
++ ipu->dc_di_assignment[5] = params->mem_dp_bg_sync.di;
++ _ipu_dp_init(ipu, channel, params->mem_dp_bg_sync.in_pixel_fmt,
++ params->mem_dp_bg_sync.out_pixel_fmt);
++ _ipu_dc_init(ipu, 5, params->mem_dp_bg_sync.di,
++ params->mem_dp_bg_sync.interlaced,
++ params->mem_dp_bg_sync.out_pixel_fmt);
++ ipu->di_use_count[params->mem_dp_bg_sync.di]++;
++ ipu->dc_use_count++;
++ ipu->dp_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case MEM_FG_SYNC:
++ _ipu_dp_init(ipu, channel, params->mem_dp_fg_sync.in_pixel_fmt,
++ params->mem_dp_fg_sync.out_pixel_fmt);
++
++ if (params->mem_dp_fg_sync.alpha_chan_en)
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++
++ ipu->dc_use_count++;
++ ipu->dp_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case DIRECT_ASYNC0:
++ if (params->direct_async.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[8] = params->direct_async.di;
++ _ipu_dc_init(ipu, 8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
++ ipu->di_use_count[params->direct_async.di]++;
++ ipu->dc_use_count++;
++ break;
++ case DIRECT_ASYNC1:
++ if (params->direct_async.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[9] = params->direct_async.di;
++ _ipu_dc_init(ipu, 9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
++ ipu->di_use_count[params->direct_async.di]++;
++ ipu->dc_use_count++;
++ break;
++ default:
++ dev_err(ipu->dev, "Missing channel initialization\n");
++ break;
++ }
++
++ ipu->channel_init_mask |= 1L << IPU_CHAN_ID(channel);
++
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_init_channel);
++
++/*!
++ * This function is called to uninitialize a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID to uninit.
++ */
++void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t in_dma, out_dma = 0;
++ uint32_t ipu_conf;
++ uint32_t dc_chan = 0;
++ int ret;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if ((ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
++ dev_dbg(ipu->dev, "Channel already uninitialized %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return;
++ }
++
++ /* Make sure channel is disabled */
++ /* Get input and output dma channels */
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++
++ if (idma_is_set(ipu, IDMAC_CHA_EN, in_dma) ||
++ idma_is_set(ipu, IDMAC_CHA_EN, out_dma)) {
++ dev_err(ipu->dev,
++ "Channel %d is not disabled, disable first\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return;
++ }
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++
++ /* Reset the double buffer */
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(in_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(out_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
++
++ /* Reset the triple buffer */
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(in_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_TRB_MODE_SEL(in_dma));
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(out_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_TRB_MODE_SEL(out_dma));
++
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = false;
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = false;
++ }
++
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ ipu->smfc_use_count--;
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case CSI_PRP_ENC_MEM:
++ ipu->ic_use_count--;
++ if (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpenc(ipu);
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case CSI_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ if (ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpvf(ipu);
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case MEM_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_prpvf(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ ipu->vdi_use_count--;
++ if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpvf(ipu);
++ _ipu_vdi_uninit(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_VDI_MEM:
++ ipu->ic_use_count--;
++ ipu->vdi_use_count--;
++ if (ipu->using_ic_dirct_ch == MEM_VDI_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpvf(ipu);
++ _ipu_vdi_uninit(ipu);
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ case MEM_VDI_PRP_VF_MEM_N:
++ case MEM_VDI_MEM_P:
++ case MEM_VDI_MEM_N:
++ break;
++ case MEM_ROT_VF_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_vf(ipu);
++ break;
++ case MEM_PRP_ENC_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_prpenc(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_ROT_ENC_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_enc(ipu);
++ break;
++ case MEM_PP_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_pp(ipu);
++ break;
++ case MEM_ROT_PP_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_pp(ipu);
++ break;
++ case MEM_DC_SYNC:
++ dc_chan = 1;
++ _ipu_dc_uninit(ipu, 1);
++ ipu->di_use_count[ipu->dc_di_assignment[1]]--;
++ ipu->dc_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case MEM_BG_SYNC:
++ dc_chan = 5;
++ _ipu_dp_uninit(ipu, channel);
++ _ipu_dc_uninit(ipu, 5);
++ ipu->di_use_count[ipu->dc_di_assignment[5]]--;
++ ipu->dc_use_count--;
++ ipu->dp_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case MEM_FG_SYNC:
++ _ipu_dp_uninit(ipu, channel);
++ ipu->dc_use_count--;
++ ipu->dp_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case DIRECT_ASYNC0:
++ dc_chan = 8;
++ _ipu_dc_uninit(ipu, 8);
++ ipu->di_use_count[ipu->dc_di_assignment[8]]--;
++ ipu->dc_use_count--;
++ break;
++ case DIRECT_ASYNC1:
++ dc_chan = 9;
++ _ipu_dc_uninit(ipu, 9);
++ ipu->di_use_count[ipu->dc_di_assignment[9]]--;
++ ipu->dc_use_count--;
++ break;
++ default:
++ break;
++ }
++
++ if (ipu->ic_use_count == 0)
++ ipu_conf &= ~IPU_CONF_IC_EN;
++ if (ipu->vdi_use_count == 0) {
++ ipu_conf &= ~IPU_CONF_ISP_EN;
++ ipu_conf &= ~IPU_CONF_VDI_EN;
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ }
++ if (ipu->rot_use_count == 0)
++ ipu_conf &= ~IPU_CONF_ROT_EN;
++ if (ipu->dc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DC_EN;
++ if (ipu->dp_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DP_EN;
++ if (ipu->dmfc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DMFC_EN;
++ if (ipu->di_use_count[0] == 0) {
++ ipu_conf &= ~IPU_CONF_DI0_EN;
++ }
++ if (ipu->di_use_count[1] == 0) {
++ ipu_conf &= ~IPU_CONF_DI1_EN;
++ }
++ if (ipu->smfc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_SMFC_EN;
++
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++ ipu->channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
++
++ /*
++ * Disable pixel clk and its parent clock(if the parent clock
++ * usecount is 1) after clearing DC/DP/DI bits in IPU_CONF
++ * register to prevent LVDS display channel starvation.
++ */
++ if (_ipu_is_primary_disp_chan(in_dma))
++ clk_disable_unprepare(ipu->pixel_clk[ipu->dc_di_assignment[dc_chan]]);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ ret = pm_runtime_put_sync_suspend(ipu->dev);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ch = %d, pm_runtime_put failed:%d!\n",
++ IPU_CHAN_ID(channel), ret);
++ dump_stack();
++ }
++
++ WARN_ON(ipu->ic_use_count < 0);
++ WARN_ON(ipu->vdi_use_count < 0);
++ WARN_ON(ipu->rot_use_count < 0);
++ WARN_ON(ipu->dc_use_count < 0);
++ WARN_ON(ipu->dp_use_count < 0);
++ WARN_ON(ipu->dmfc_use_count < 0);
++ WARN_ON(ipu->smfc_use_count < 0);
++}
++EXPORT_SYMBOL(ipu_uninit_channel);
++
++/*!
++ * This function is called to initialize buffer(s) for logical IPU channel.
++ *
++ * @param ipu ipu handler
++ *
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width Input parameter for width of buffer in pixels.
++ *
++ * @param height Input parameter for height of buffer in pixels.
++ *
++ * @param stride Input parameter for stride length of buffer
++ * in pixels.
++ *
++ * @param rot_mode Input parameter for rotation setting of buffer.
++ * A rotation setting other than
++ * IPU_ROTATE_VERT_FLIP
++ * should only be used for input buffers of
++ * rotation channels.
++ *
++ * @param phyaddr_0 Input parameter buffer 0 physical address.
++ *
++ * @param phyaddr_1 Input parameter buffer 1 physical address.
++ * Setting this to a value other than NULL enables
++ * double buffering mode.
++ *
++ * @param phyaddr_2 Input parameter buffer 2 physical address.
++ * Setting this to a value other than NULL enables
++ * triple buffering mode, phyaddr_1 should not be
++ * NULL then.
++ *
++ * @param u private u offset for additional cropping,
++ * zero if not used.
++ *
++ * @param v private v offset for additional cropping,
++ * zero if not used.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ ipu_rotate_mode_t rot_mode,
++ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
++ dma_addr_t phyaddr_2,
++ uint32_t u, uint32_t v)
++{
++ uint32_t reg;
++ uint32_t dma_chan;
++ uint32_t burst_size;
++
++ dma_chan = channel_2_dma(channel, type);
++ if (!idma_is_valid(dma_chan))
++ return -EINVAL;
++
++ if (stride < width * bytes_per_pixel(pixel_fmt))
++ stride = width * bytes_per_pixel(pixel_fmt);
++
++ if (stride % 4) {
++ dev_err(ipu->dev,
++ "Stride not 32-bit aligned, stride = %d\n", stride);
++ return -EINVAL;
++ }
++ /* IC & IRT channels' width must be multiple of 8 pixels */
++ if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
++ && (width % 8)) {
++ dev_err(ipu->dev, "Width must be 8 pixel multiple\n");
++ return -EINVAL;
++ }
++
++ if (_ipu_is_vdi_out_chan(dma_chan) &&
++ ((width < 16) || (height < 16) || (width % 2) || (height % 4))) {
++ dev_err(ipu->dev, "vdi width/height limited err\n");
++ return -EINVAL;
++ }
++
++ /* IPUv3EX and IPUv3M support triple buffer */
++ if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
++ dev_err(ipu->dev, "Chan%d doesn't support triple buffer "
++ "mode\n", dma_chan);
++ return -EINVAL;
++ }
++ if (!phyaddr_1 && phyaddr_2) {
++ dev_err(ipu->dev, "Chan%d's buf1 physical addr is NULL for "
++ "triple buffer mode\n", dma_chan);
++ return -EINVAL;
++ }
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* Build parameter memory data for DMA channel */
++ _ipu_ch_param_init(ipu, dma_chan, pixel_fmt, width, height, stride, u, v, 0,
++ phyaddr_0, phyaddr_1, phyaddr_2);
++
++ /* Set correlative channel parameter of local alpha channel */
++ if ((_ipu_is_ic_graphic_chan(dma_chan) ||
++ _ipu_is_dp_graphic_chan(dma_chan)) &&
++ (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
++ _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, true);
++ _ipu_ch_param_set_alpha_buffer_memory(ipu, dma_chan);
++ _ipu_ch_param_set_alpha_condition_read(ipu, dma_chan);
++ /* fix alpha width as 8 and burst size as 16*/
++ _ipu_ch_params_set_alpha_width(ipu, dma_chan, 8);
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
++ } else if (_ipu_is_ic_graphic_chan(dma_chan) &&
++ ipu_pixel_format_has_alpha(pixel_fmt))
++ _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, false);
++
++ if (rot_mode)
++ _ipu_ch_param_set_rotation(ipu, dma_chan, rot_mode);
++
++ /* IC and ROT channels have restriction of 8 or 16 pix burst length */
++ if (_ipu_is_ic_chan(dma_chan) || _ipu_is_vdi_out_chan(dma_chan)) {
++ if ((width % 16) == 0)
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
++ else
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
++ } else if (_ipu_is_irt_chan(dma_chan)) {
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
++ _ipu_ch_param_set_block_mode(ipu, dma_chan);
++ } else if (_ipu_is_dmfc_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ _ipu_dmfc_set_wait4eot(ipu, dma_chan, width);
++ _ipu_dmfc_set_burst_size(ipu, dma_chan, burst_size);
++ }
++
++ if (_ipu_disp_chan_is_interlaced(ipu, channel) ||
++ ipu->chan_is_interlaced[dma_chan])
++ _ipu_ch_param_set_interlaced_scan(ipu, dma_chan);
++
++ if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan) ||
++ _ipu_is_vdi_out_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ _ipu_ic_idma_init(ipu, dma_chan, width, height, burst_size,
++ rot_mode);
++ } else if (_ipu_is_smfc_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ /*
++ * This is different from IPUv3 spec, but it is confirmed
++ * in IPUforum that SMFC burst size should be NPB[6:3]
++ * when IDMAC works in 16-bit generic data mode.
++ */
++ if (pixel_fmt == IPU_PIX_FMT_GENERIC)
++ /* 8 bits per pixel */
++ burst_size = burst_size >> 4;
++ else if (pixel_fmt == IPU_PIX_FMT_GENERIC_16)
++ /* 16 bits per pixel */
++ burst_size = burst_size >> 3;
++ else
++ burst_size = burst_size >> 2;
++ _ipu_smfc_set_burst_size(ipu, channel, burst_size-1);
++ }
++
++ /* AXI-id */
++ if (idma_is_set(ipu, IDMAC_CHA_PRI, dma_chan)) {
++ unsigned reg = IDMAC_CH_LOCK_EN_1;
++ uint32_t value = 0;
++ if (ipu->pdata->devtype == IPU_V3H) {
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 0);
++ switch (dma_chan) {
++ case 5:
++ value = 0x3;
++ break;
++ case 11:
++ value = 0x3 << 2;
++ break;
++ case 12:
++ value = 0x3 << 4;
++ break;
++ case 14:
++ value = 0x3 << 6;
++ break;
++ case 15:
++ value = 0x3 << 8;
++ break;
++ case 20:
++ value = 0x3 << 10;
++ break;
++ case 21:
++ value = 0x3 << 12;
++ break;
++ case 22:
++ value = 0x3 << 14;
++ break;
++ case 23:
++ value = 0x3 << 16;
++ break;
++ case 27:
++ value = 0x3 << 18;
++ break;
++ case 28:
++ value = 0x3 << 20;
++ break;
++ case 45:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 0;
++ break;
++ case 46:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 2;
++ break;
++ case 47:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 4;
++ break;
++ case 48:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 6;
++ break;
++ case 49:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 8;
++ break;
++ case 50:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 10;
++ break;
++ default:
++ break;
++ }
++ value |= ipu_idmac_read(ipu, reg);
++ ipu_idmac_write(ipu, value, reg);
++ } else
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
++ } else {
++ if (ipu->pdata->devtype == IPU_V3H)
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
++ }
++
++ _ipu_ch_param_dump(ipu, dma_chan);
++
++ if (phyaddr_2 && g_ipu_hw_rev >= IPU_V3DEX) {
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
++
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ reg |= idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
++
++ /* Set IDMAC third buffer's cpmem number */
++ /* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
++ ipu_idmac_write(ipu, 0x00444047L, IDMAC_SUB_ADDR_4);
++ ipu_idmac_write(ipu, 0x46004241L, IDMAC_SUB_ADDR_3);
++ ipu_idmac_write(ipu, 0x00000045L, IDMAC_SUB_ADDR_1);
++
++ /* Reset to buffer 0 */
++ ipu_cm_write(ipu, tri_cur_buf_mask(dma_chan),
++ IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
++ } else {
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
++
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
++ if (phyaddr_1)
++ reg |= idma_mask(dma_chan);
++ else
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
++
++ /* Reset to buffer 0 */
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_CUR_BUF(dma_chan));
++
++ }
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_channel_buffer);
++
++/*!
++ * This function is called to update the physical address of a buffer for
++ * a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param bufNum Input parameter for buffer number to update.
++ * 0 or 1 are the only valid values.
++ *
++ * @param phyaddr Input parameter buffer physical address.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail. This function will fail if the buffer is set to ready.
++ */
++int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum, dma_addr_t phyaddr)
++{
++ uint32_t reg;
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if (bufNum == 0)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
++
++ if ((reg & idma_mask(dma_chan)) == 0)
++ _ipu_ch_param_set_buffer(ipu, dma_chan, bufNum, phyaddr);
++ else
++ ret = -EACCES;
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_update_channel_buffer);
++
++/*!
++ * This function is called to update the band mode setting for
++ * a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ *
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param band_height Input parameter for band lines:
++ * shoule be log2(4/8/16/32/64/128/256).
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t band_height)
++{
++ uint32_t reg;
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++
++ if ((2 > band_height) || (8 < band_height))
++ return -EINVAL;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ reg = ipu_idmac_read(ipu, IDMAC_BAND_EN(dma_chan));
++ reg |= 1 << (dma_chan % 32);
++ ipu_idmac_write(ipu, reg, IDMAC_BAND_EN(dma_chan));
++
++ _ipu_ch_param_set_bandmode(ipu, dma_chan, band_height);
++ dev_dbg(ipu->dev, "dma_chan:%d, band_height:%d.\n\n",
++ dma_chan, 1 << band_height);
++ mutex_unlock(&ipu->mutex_lock);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_set_channel_bandmode);
++
++/*!
++ * This function is called to initialize a buffer for logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width Input parameter for width of buffer in pixels.
++ *
++ * @param height Input parameter for height of buffer in pixels.
++ *
++ * @param stride Input parameter for stride length of buffer
++ * in pixels.
++ *
++ * @param u predefined private u offset for additional cropping,
++ * zero if not used.
++ *
++ * @param v predefined private v offset for additional cropping,
++ * zero if not used.
++ *
++ * @param vertical_offset vertical offset for Y coordinate
++ * in the existed frame
++ *
++ *
++ * @param horizontal_offset horizontal offset for X coordinate
++ * in the existed frame
++ *
++ *
++ * @return Returns 0 on success or negative error code on fail
++ * This function will fail if any buffer is set to ready.
++ */
++
++int32_t ipu_update_channel_offset(struct ipu_soc *ipu,
++ ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t vertical_offset, uint32_t horizontal_offset)
++{
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if ((ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
++ (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan)) & idma_mask(dma_chan)) ||
++ ((ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan)) & idma_mask(dma_chan)) &&
++ (ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan)) & idma_mask(dma_chan)) &&
++ _ipu_is_trb_chan(dma_chan)))
++ ret = -EACCES;
++ else
++ _ipu_ch_offset_update(ipu, dma_chan, pixel_fmt, width, height, stride,
++ u, v, 0, vertical_offset, horizontal_offset);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_update_channel_offset);
++
++
++/*!
++ * This function is called to set a channel's buffer as ready.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param bufNum Input parameter for which buffer number set to
++ * ready state.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum)
++{
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Mark buffer to be ready. */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF2_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_select_buffer);
++
++/*!
++ * This function is called to set a channel's buffer as ready.
++ *
++ * @param ipu ipu handler
++ * @param bufNum Input parameter for which buffer number set to
++ * ready state.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum)
++{
++
++ uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
++ uint32_t mask_bit =
++ idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
++ idma_mask(dma_chan)|
++ idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Mark buffers to be ready. */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF0_RDY(dma_chan));
++ else
++ ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF1_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
++
++#define NA -1
++static int proc_dest_sel[] = {
++ 0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
++ 0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
++static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
++ NA, NA, NA, NA, NA, 1, 2, 3, 4, 7, 8, NA, 8, NA };
++static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
++ NA, NA, NA, NA, NA, 1, NA, 2, NA, 3, 4, 4, 4, 4 };
++
++
++/*!
++ * This function links 2 channels together for automatic frame
++ * synchronization. The output of the source channel is linked to the input of
++ * the destination channel.
++ *
++ * @param ipu ipu handler
++ * @param src_ch Input parameter for the logical channel ID of
++ * the source channel.
++ *
++ * @param dest_ch Input parameter for the logical channel ID of
++ * the destination channel.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
++{
++ int retval = 0;
++ uint32_t fs_proc_flow1;
++ uint32_t fs_proc_flow2;
++ uint32_t fs_proc_flow3;
++ uint32_t fs_disp_flow1;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
++ fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
++ fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
++
++ switch (src_ch) {
++ case CSI_MEM0:
++ fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC0_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM1:
++ fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC1_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM2:
++ fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC2_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM3:
++ fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC3_DEST_SEL_OFFSET;
++ break;
++ case CSI_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_DEST_SEL_OFFSET;
++ break;
++ case CSI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PP_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PP_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_VDOA_MEM:
++ fs_proc_flow3 &= ~FS_VDOA_DEST_SEL_MASK;
++ if (MEM_VDI_MEM == dest_ch)
++ fs_proc_flow3 |= FS_VDOA_DEST_SEL_VDI;
++ else if (MEM_PP_MEM == dest_ch)
++ fs_proc_flow3 |= FS_VDOA_DEST_SEL_IC;
++ else {
++ retval = -EINVAL;
++ goto err;
++ }
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ switch (dest_ch) {
++ case MEM_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
++ if (MEM_VDOA_MEM == src_ch)
++ fs_proc_flow1 |= FS_PP_SRC_SEL_VDOA;
++ else
++ fs_proc_flow1 |= proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PP_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PRPENC_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PRPVF_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_DC_SYNC:
++ fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_BG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_SYNC0_SRC_SEL_OFFSET;
++ break;
++ case MEM_FG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_SYNC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_DC_ASYNC:
++ fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
++ break;
++ case MEM_BG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_ASYNC0_SRC_SEL_OFFSET;
++ break;
++ case MEM_FG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_ASYNC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_VDI_MEM:
++ fs_proc_flow1 &= ~FS_VDI_SRC_SEL_MASK;
++ if (MEM_VDOA_MEM == src_ch)
++ fs_proc_flow1 |= FS_VDI_SRC_SEL_VDOA;
++ else {
++ retval = -EINVAL;
++ goto err;
++ }
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
++ ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
++ ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return retval;
++}
++EXPORT_SYMBOL(ipu_link_channels);
++
++/*!
++ * This function unlinks 2 channels and disables automatic frame
++ * synchronization.
++ *
++ * @param ipu ipu handler
++ * @param src_ch Input parameter for the logical channel ID of
++ * the source channel.
++ *
++ * @param dest_ch Input parameter for the logical channel ID of
++ * the destination channel.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
++{
++ int retval = 0;
++ uint32_t fs_proc_flow1;
++ uint32_t fs_proc_flow2;
++ uint32_t fs_proc_flow3;
++ uint32_t fs_disp_flow1;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
++ fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
++ fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
++
++ switch (src_ch) {
++ case CSI_MEM0:
++ fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
++ break;
++ case CSI_MEM1:
++ fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
++ break;
++ case CSI_MEM2:
++ fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
++ break;
++ case CSI_MEM3:
++ fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
++ break;
++ case CSI_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ break;
++ case CSI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_VDOA_MEM:
++ fs_proc_flow3 &= ~FS_VDOA_DEST_SEL_MASK;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ switch (dest_ch) {
++ case MEM_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_DC_SYNC:
++ fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
++ break;
++ case MEM_BG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
++ break;
++ case MEM_FG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
++ break;
++ case MEM_DC_ASYNC:
++ fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
++ break;
++ case MEM_BG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
++ break;
++ case MEM_FG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
++ break;
++ case MEM_VDI_MEM:
++ fs_proc_flow1 &= ~FS_VDI_SRC_SEL_MASK;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
++ ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
++ ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return retval;
++}
++EXPORT_SYMBOL(ipu_unlink_channels);
++
++/*!
++ * This function check whether a logical channel was enabled.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 1 while request channel is enabled or
++ * 0 for not enabled.
++ */
++int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t in_dma;
++ uint32_t out_dma;
++
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ if (reg & idma_mask(in_dma))
++ return 1;
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ if (reg & idma_mask(out_dma))
++ return 1;
++ return 0;
++}
++EXPORT_SYMBOL(ipu_is_channel_busy);
++
++/*!
++ * This function enables a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t ipu_conf;
++ uint32_t in_dma;
++ uint32_t out_dma;
++ uint32_t sec_dma;
++ uint32_t thrd_dma;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
++ dev_err(ipu->dev, "Warning: channel already enabled %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return -EACCES;
++ }
++
++ /* Get input and output dma channels */
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++ if (ipu->di_use_count[0] > 0) {
++ ipu_conf |= IPU_CONF_DI0_EN;
++ }
++ if (ipu->di_use_count[1] > 0) {
++ ipu_conf |= IPU_CONF_DI1_EN;
++ }
++ if (ipu->dp_use_count > 0)
++ ipu_conf |= IPU_CONF_DP_EN;
++ if (ipu->dc_use_count > 0)
++ ipu_conf |= IPU_CONF_DC_EN;
++ if (ipu->dmfc_use_count > 0)
++ ipu_conf |= IPU_CONF_DMFC_EN;
++ if (ipu->ic_use_count > 0)
++ ipu_conf |= IPU_CONF_IC_EN;
++ if (ipu->vdi_use_count > 0) {
++ ipu_conf |= IPU_CONF_ISP_EN;
++ ipu_conf |= IPU_CONF_VDI_EN;
++ ipu_conf |= IPU_CONF_IC_INPUT;
++ }
++ if (ipu->rot_use_count > 0)
++ ipu_conf |= IPU_CONF_ROT_EN;
++ if (ipu->smfc_use_count > 0)
++ ipu_conf |= IPU_CONF_SMFC_EN;
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++ if (idma_is_valid(in_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
++ }
++ if (idma_is_valid(out_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
++ }
++
++ if ((ipu->sec_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
++ (channel == MEM_VDI_PRP_VF_MEM))) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
++ }
++ if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
++ } else if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
++ }
++
++ if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
++ (channel == MEM_FG_SYNC)) {
++ reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
++
++ _ipu_dp_dc_enable(ipu, channel);
++ }
++
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
++ _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma) ||
++ _ipu_is_vdi_out_chan(out_dma))
++ _ipu_ic_enable_task(ipu, channel);
++
++ ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_enable_channel);
++
++/*!
++ * This function check buffer ready for a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to clear.
++ *
++ * @param bufNum Input parameter for which buffer number clear
++ * ready state.
++ *
++ */
++int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if (bufNum == 0)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ if (reg & idma_mask(dma_chan))
++ return 1;
++ else
++ return 0;
++}
++EXPORT_SYMBOL(ipu_check_buffer_ready);
++
++/*!
++ * This function clear buffer ready for a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to clear.
++ *
++ * @param bufNum Input parameter for which buffer number clear
++ * ready state.
++ *
++ */
++void _ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ uint32_t dma_ch = channel_2_dma(channel, type);
++
++ if (!idma_is_valid(dma_ch))
++ return;
++
++ ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF0_RDY(dma_ch));
++ else if (bufNum == 1)
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF1_RDY(dma_ch));
++ else
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF2_RDY(dma_ch));
++ ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
++}
++
++void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ _ipu_clear_buffer_ready(ipu, channel, type, bufNum);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++}
++EXPORT_SYMBOL(ipu_clear_buffer_ready);
++
++/*!
++ * This function disables a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param wait_for_stop Flag to set whether to wait for channel end
++ * of frame or return immediately.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop)
++{
++ uint32_t reg;
++ uint32_t in_dma;
++ uint32_t out_dma;
++ uint32_t sec_dma = NO_DMA;
++ uint32_t thrd_dma = NO_DMA;
++ uint16_t fg_pos_x, fg_pos_y;
++ unsigned long lock_flags;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if ((ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
++ dev_dbg(ipu->dev, "Channel already disabled %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return -EACCES;
++ }
++
++ /* Get input and output dma channels */
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ if ((idma_is_valid(in_dma) &&
++ !idma_is_set(ipu, IDMAC_CHA_EN, in_dma))
++ && (idma_is_valid(out_dma) &&
++ !idma_is_set(ipu, IDMAC_CHA_EN, out_dma))) {
++ mutex_unlock(&ipu->mutex_lock);
++ return -EINVAL;
++ }
++
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)])
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ }
++
++ if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
++ (channel == MEM_DC_SYNC)) {
++ if (channel == MEM_FG_SYNC) {
++ _ipu_disp_get_window_pos(ipu, channel, &fg_pos_x, &fg_pos_y);
++ _ipu_disp_set_window_pos(ipu, channel, 0, 0);
++ }
++
++ _ipu_dp_dc_disable(ipu, channel, false);
++
++ /*
++ * wait for BG channel EOF then disable FG-IDMAC,
++ * it avoid FG NFB4EOF error.
++ */
++ if ((channel == MEM_FG_SYNC) && (ipu_is_channel_busy(ipu, MEM_BG_SYNC))) {
++ int timeout = 50;
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
++ IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF));
++ while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) &
++ IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) {
++ msleep(10);
++ timeout -= 10;
++ if (timeout <= 0) {
++ dev_err(ipu->dev, "warning: wait for bg sync eof timeout\n");
++ break;
++ }
++ }
++ }
++ } else if (wait_for_stop && !_ipu_is_smfc_chan(out_dma) &&
++ channel != CSI_PRP_VF_MEM && channel != CSI_PRP_ENC_MEM) {
++ while (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma) ||
++ idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma) ||
++ (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma)) ||
++ (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))) {
++ uint32_t irq = 0xffffffff;
++ int timeout = 50000;
++
++ if (idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma))
++ irq = out_dma;
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma))
++ irq = sec_dma;
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))
++ irq = thrd_dma;
++ if (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma))
++ irq = in_dma;
++
++ if (irq == 0xffffffff) {
++ dev_dbg(ipu->dev, "warning: no channel busy, break\n");
++ break;
++ }
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq),
++ IPUIRQ_2_STATREG(irq));
++
++ dev_dbg(ipu->dev, "warning: channel %d busy, need wait\n", irq);
++
++ while (((ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq))
++ & IPUIRQ_2_MASK(irq)) == 0) &&
++ (idma_is_set(ipu, IDMAC_CHA_BUSY, irq))) {
++ udelay(10);
++ timeout -= 10;
++ if (timeout <= 0) {
++ ipu_dump_registers(ipu);
++ dev_err(ipu->dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
++ break;
++ }
++ }
++ dev_dbg(ipu->dev, "wait_time:%d\n", 50000 - timeout);
++
++ }
++ }
++
++ if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
++ (channel == MEM_DC_SYNC)) {
++ reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
++ }
++
++ /* Disable IC task */
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
++ _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma) ||
++ _ipu_is_vdi_out_chan(out_dma))
++ _ipu_ic_disable_task(ipu, channel);
++
++ /* Disable DMA channel(s) */
++ if (idma_is_valid(in_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
++ ipu_cm_write(ipu, idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(in_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(in_dma));
++ }
++ if (idma_is_valid(out_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
++ ipu_cm_write(ipu, idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(out_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(out_dma));
++ }
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
++ ipu_cm_write(ipu, idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
++ }
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
++ } else {
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
++ }
++ ipu_cm_write(ipu, idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
++ }
++
++ if (channel == MEM_FG_SYNC)
++ _ipu_disp_set_window_pos(ipu, channel, fg_pos_x, fg_pos_y);
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Set channel buffers NOT to be ready */
++ if (idma_is_valid(in_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 1);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 2);
++ }
++ if (idma_is_valid(out_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 1);
++ }
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 1);
++ }
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 1);
++ }
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disable_channel);
++
++/*!
++ * This function enables CSI.
++ *
++ * @param ipu ipu handler
++ * @param csi csi num 0 or 1
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t reg;
++
++ if (csi > 1) {
++ dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
++ return -EINVAL;
++ }
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ipu->csi_use_count[csi]++;
++
++ if (ipu->csi_use_count[csi] == 1) {
++ reg = ipu_cm_read(ipu, IPU_CONF);
++ if (csi == 0)
++ ipu_cm_write(ipu, reg | IPU_CONF_CSI0_EN, IPU_CONF);
++ else
++ ipu_cm_write(ipu, reg | IPU_CONF_CSI1_EN, IPU_CONF);
++ }
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_enable_csi);
++
++/*!
++ * This function disables CSI.
++ *
++ * @param ipu ipu handler
++ * @param csi csi num 0 or 1
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t reg;
++
++ if (csi > 1) {
++ dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
++ return -EINVAL;
++ }
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ipu->csi_use_count[csi]--;
++ if (ipu->csi_use_count[csi] == 0) {
++ _ipu_csi_wait4eof(ipu, ipu->csi_channel[csi]);
++ reg = ipu_cm_read(ipu, IPU_CONF);
++ if (csi == 0)
++ ipu_cm_write(ipu, reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
++ else
++ ipu_cm_write(ipu, reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
++ }
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disable_csi);
++
++static irqreturn_t ipu_sync_irq_handler(int irq, void *desc)
++{
++ struct ipu_soc *ipu = desc;
++ int i;
++ uint32_t line, bit, int_stat, int_ctrl;
++ irqreturn_t result = IRQ_NONE;
++ const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
++
++ spin_lock(&ipu->int_reg_spin_lock);
++
++ for (i = 0; int_reg[i] != 0; i++) {
++ int_stat = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
++ int_ctrl = ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
++ int_stat &= int_ctrl;
++ ipu_cm_write(ipu, int_stat, IPU_INT_STAT(int_reg[i]));
++ while ((line = ffs(int_stat)) != 0) {
++ bit = --line;
++ int_stat &= ~(1UL << line);
++ line += (int_reg[i] - 1) * 32;
++ result |=
++ ipu->irq_list[line].handler(line,
++ ipu->irq_list[line].
++ dev_id);
++ if (ipu->irq_list[line].flags & IPU_IRQF_ONESHOT) {
++ int_ctrl &= ~(1UL << bit);
++ ipu_cm_write(ipu, int_ctrl,
++ IPU_INT_CTRL(int_reg[i]));
++ }
++ }
++ }
++
++ spin_unlock(&ipu->int_reg_spin_lock);
++
++ return result;
++}
++
++static irqreturn_t ipu_err_irq_handler(int irq, void *desc)
++{
++ struct ipu_soc *ipu = desc;
++ int i;
++ uint32_t int_stat;
++ const int err_reg[] = { 5, 6, 9, 10, 0 };
++
++ spin_lock(&ipu->int_reg_spin_lock);
++
++ for (i = 0; err_reg[i] != 0; i++) {
++ int_stat = ipu_cm_read(ipu, IPU_INT_STAT(err_reg[i]));
++ int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i]));
++ if (int_stat) {
++ ipu_cm_write(ipu, int_stat, IPU_INT_STAT(err_reg[i]));
++ dev_warn(ipu->dev,
++ "IPU Warning - IPU_INT_STAT_%d = 0x%08X\n",
++ err_reg[i], int_stat);
++ /* Disable interrupts so we only get error once */
++ int_stat = ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i])) &
++ ~int_stat;
++ ipu_cm_write(ipu, int_stat, IPU_INT_CTRL(err_reg[i]));
++ }
++ }
++
++ spin_unlock(&ipu->int_reg_spin_lock);
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * This function enables the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to enable interrupt for.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int ret = 0;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ /*
++ * Check sync interrupt handler only, since we do nothing for
++ * error interrupts but than print out register values in the
++ * error interrupt source handler.
++ */
++ if (_ipu_is_sync_irq(irq) && (ipu->irq_list[irq].handler == NULL)) {
++ dev_err(ipu->dev, "handler hasn't been registered on sync "
++ "irq %d\n", irq);
++ ret = -EACCES;
++ goto out;
++ }
++
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg |= IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++out:
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_enable_irq);
++
++/*!
++ * This function disables the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to disable interrupt for.
++ *
++ */
++void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg &= ~IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_disable_irq);
++
++/*!
++ * This function clears the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to clear interrupt for.
++ *
++ */
++void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_clear_irq);
++
++/*!
++ * This function returns the current interrupt status for the specified
++ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @return Returns true if the interrupt is pending/asserted or false if
++ * the interrupt is not pending.
++ */
++bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++ reg = ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq));
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ if (reg & IPUIRQ_2_MASK(irq))
++ return true;
++ else
++ return false;
++}
++EXPORT_SYMBOL(ipu_get_irq_status);
++
++/*!
++ * This function registers an interrupt handler function for the specified
++ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @param handler Input parameter for address of the handler
++ * function.
++ *
++ * @param irq_flags Flags for interrupt mode. Currently not used.
++ *
++ * @param devname Input parameter for string name of driver
++ * registering the handler.
++ *
++ * @param dev_id Input parameter for pointer of data to be
++ * passed to the handler.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
++ irqreturn_t(*handler) (int, void *),
++ uint32_t irq_flags, const char *devname, void *dev_id)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int ret = 0;
++
++ BUG_ON(irq >= IPU_IRQ_COUNT);
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ if (ipu->irq_list[irq].handler != NULL) {
++ dev_err(ipu->dev,
++ "handler already installed on irq %d\n", irq);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ /*
++ * Check sync interrupt handler only, since we do nothing for
++ * error interrupts but than print out register values in the
++ * error interrupt source handler.
++ */
++ if (_ipu_is_sync_irq(irq) && (handler == NULL)) {
++ dev_err(ipu->dev, "handler is NULL for sync irq %d\n", irq);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ ipu->irq_list[irq].handler = handler;
++ ipu->irq_list[irq].flags = irq_flags;
++ ipu->irq_list[irq].dev_id = dev_id;
++ ipu->irq_list[irq].name = devname;
++
++ /* clear irq stat for previous use */
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
++ /* enable the interrupt */
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg |= IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++out:
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_request_irq);
++
++/*!
++ * This function unregisters an interrupt handler for the specified interrupt
++ * line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @param dev_id Input parameter for pointer of data to be passed
++ * to the handler. This must match value passed to
++ * ipu_request_irq().
++ *
++ */
++void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ /* disable the interrupt */
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg &= ~IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++ if (ipu->irq_list[irq].dev_id == dev_id)
++ memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq]));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_free_irq);
++
++uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type)
++{
++ uint32_t reg, dma_chan;
++
++ dma_chan = channel_2_dma(channel, type);
++ if (!idma_is_valid(dma_chan))
++ return -EINVAL;
++
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ if ((reg & idma_mask(dma_chan)) && _ipu_is_trb_chan(dma_chan)) {
++ reg = ipu_cm_read(ipu, IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
++ return (reg & tri_cur_buf_mask(dma_chan)) >>
++ tri_cur_buf_shift(dma_chan);
++ } else {
++ reg = ipu_cm_read(ipu, IPU_CHA_CUR_BUF(dma_chan));
++ if (reg & idma_mask(dma_chan))
++ return 1;
++ else
++ return 0;
++ }
++}
++EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
++
++uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t stat = 0;
++ uint32_t task_stat_reg = ipu_cm_read(ipu, IPU_PROC_TASK_STAT);
++
++ switch (channel) {
++ case MEM_PRP_VF_MEM:
++ stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ stat =
++ (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ stat =
++ (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
++ TSTAT_ENC_ROT_OFFSET;
++ break;
++ case MEM_PP_MEM:
++ stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ stat =
++ (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
++ break;
++
++ default:
++ stat = TASK_STAT_IDLE;
++ break;
++ }
++ return stat;
++}
++
++/*!
++ * This function check for a logical channel status
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 0 on idle and 1 on busy.
++ *
++ */
++uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t dma_status;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ dma_status = ipu_is_channel_busy(ipu, channel);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++
++ dev_dbg(ipu->dev, "%s, dma_status:%d.\n", __func__, dma_status);
++
++ return dma_status;
++}
++EXPORT_SYMBOL(ipu_channel_status);
++
++int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
++ int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* enable target channel */
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(to_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
++
++ ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
++
++ /* switch dp dc */
++ _ipu_dp_dc_disable(ipu, from_ch, true);
++
++ /* disable source channel */
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(from_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
++ ipu_cm_write(ipu, idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(from_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(from_dma));
++
++ ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 1);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 2);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_swap_channel);
++
++uint32_t bytes_per_pixel(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_GENERIC: /*generic data */
++ case IPU_PIX_FMT_RGB332:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV444P:
++ return 1;
++ break;
++ case IPU_PIX_FMT_GENERIC_16: /* generic data */
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ return 2;
++ break;
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ return 3;
++ break;
++ case IPU_PIX_FMT_GENERIC_32: /*generic data */
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ return 4;
++ break;
++ default:
++ return 1;
++ break;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(bytes_per_pixel);
++
++ipu_color_space_t format_to_colorspace(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGB666:
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_GBR24:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ case IPU_PIX_FMT_LVDS666:
++ case IPU_PIX_FMT_LVDS888:
++ return RGB;
++ break;
++
++ default:
++ return YCbCr;
++ break;
++ }
++ return RGB;
++}
++
++bool ipu_pixel_format_has_alpha(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_ABGR32:
++ return true;
++ break;
++ default:
++ return false;
++ break;
++ }
++ return false;
++}
++
++bool ipu_ch_param_bad_alpha_pos(uint32_t pixel_fmt)
++{
++ return _ipu_ch_param_bad_alpha_pos(pixel_fmt);
++}
++EXPORT_SYMBOL(ipu_ch_param_bad_alpha_pos);
++
++#ifdef CONFIG_PM
++static int ipu_suspend(struct device *dev)
++{
++ struct ipu_soc *ipu = dev_get_drvdata(dev);
++
++ /* All IDMAC channel and IPU clock should be disabled.*/
++ if (ipu->pdata->pg)
++ ipu->pdata->pg(1);
++
++ dev_dbg(dev, "ipu suspend.\n");
++ return 0;
++}
++
++static int ipu_resume(struct device *dev)
++{
++ struct ipu_soc *ipu = dev_get_drvdata(dev);
++
++ if (ipu->pdata->pg) {
++ ipu->pdata->pg(0);
++
++ _ipu_get(ipu);
++ _ipu_dmfc_init(ipu, dmfc_type_setup, 1);
++ /* Set sync refresh channels as high priority */
++ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
++ _ipu_put(ipu);
++ }
++ dev_dbg(dev, "ipu resume.\n");
++ return 0;
++}
++
++int ipu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "ipu busfreq high release.\n");
++
++ return 0;
++}
++
++int ipu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "ipu busfreq high requst.\n");
++
++ return 0;
++}
++
++static const struct dev_pm_ops ipu_pm_ops = {
++ SET_RUNTIME_PM_OPS(ipu_runtime_suspend, ipu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(ipu_suspend, ipu_resume)
++};
++#endif
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxcipu_driver = {
++ .driver = {
++ .name = "imx-ipuv3",
++ .of_match_table = imx_ipuv3_dt_ids,
++ #ifdef CONFIG_PM
++ .pm = &ipu_pm_ops,
++ #endif
++ },
++ .probe = ipu_probe,
++ .id_table = imx_ipu_type,
++ .remove = ipu_remove,
++};
++
++int32_t __init ipu_gen_init(void)
++{
++ int32_t ret;
++
++ ret = platform_driver_register(&mxcipu_driver);
++ return 0;
++}
++
++subsys_initcall(ipu_gen_init);
++
++static void __exit ipu_gen_uninit(void)
++{
++ platform_driver_unregister(&mxcipu_driver);
++}
++
++module_exit(ipu_gen_uninit);
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_device.c linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_device.c
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_device.c 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,3690 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_device.c
++ *
++ * @brief This file contains the IPUv3 driver device interface and fops functions.
++ *
++ * @ingroup IPU
++ */
++#include <linux/clk.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/sched.h>
++#include <linux/sched/rt.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++#include <linux/types.h>
++#include <linux/vmalloc.h>
++#include <linux/wait.h>
++
++#include <asm/cacheflush.h>
++#include <asm/outercache.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++#include "vdoa.h"
++
++#define CHECK_RETCODE(cont, str, err, label, ret) \
++do { \
++ if (cont) { \
++ dev_err(t->dev, "ERR:[0x%p]-no:0x%x "#str" ret:%d," \
++ "line:%d\n", t, t->task_no, ret, __LINE__);\
++ if (ret != -EACCES) { \
++ t->state = err; \
++ goto label; \
++ } \
++ } \
++} while (0)
++
++#define CHECK_RETCODE_CONT(cont, str, err, ret) \
++do { \
++ if (cont) { \
++ dev_err(t->dev, "ERR:[0x%p]-no:0x%x"#str" ret:%d," \
++ "line:%d\n", t, t->task_no, ret, __LINE__);\
++ if (ret != -EACCES) { \
++ if (t->state == STATE_OK) \
++ t->state = err; \
++ } \
++ } \
++} while (0)
++
++#undef DBG_IPU_PERF
++#ifdef DBG_IPU_PERF
++#define CHECK_PERF(ts) \
++do { \
++ getnstimeofday(ts); \
++} while (0)
++
++#define DECLARE_PERF_VAR \
++ struct timespec ts_queue; \
++ struct timespec ts_dotask; \
++ struct timespec ts_waitirq; \
++ struct timespec ts_sche; \
++ struct timespec ts_rel; \
++ struct timespec ts_frame
++
++#define PRINT_TASK_STATISTICS \
++do { \
++ ts_queue = timespec_sub(tsk->ts_dotask, tsk->ts_queue); \
++ ts_dotask = timespec_sub(tsk->ts_waitirq, tsk->ts_dotask); \
++ ts_waitirq = timespec_sub(tsk->ts_inirq, tsk->ts_waitirq); \
++ ts_sche = timespec_sub(tsk->ts_wakeup, tsk->ts_inirq); \
++ ts_rel = timespec_sub(tsk->ts_rel, tsk->ts_wakeup); \
++ ts_frame = timespec_sub(tsk->ts_rel, tsk->ts_queue); \
++ dev_dbg(tsk->dev, "[0x%p] no-0x%x, ts_q:%ldus, ts_do:%ldus," \
++ "ts_waitirq:%ldus,ts_sche:%ldus, ts_rel:%ldus," \
++ "ts_frame: %ldus\n", tsk, tsk->task_no, \
++ ts_queue.tv_nsec / NSEC_PER_USEC + ts_queue.tv_sec * USEC_PER_SEC,\
++ ts_dotask.tv_nsec / NSEC_PER_USEC + ts_dotask.tv_sec * USEC_PER_SEC,\
++ ts_waitirq.tv_nsec / NSEC_PER_USEC + ts_waitirq.tv_sec * USEC_PER_SEC,\
++ ts_sche.tv_nsec / NSEC_PER_USEC + ts_sche.tv_sec * USEC_PER_SEC,\
++ ts_rel.tv_nsec / NSEC_PER_USEC + ts_rel.tv_sec * USEC_PER_SEC,\
++ ts_frame.tv_nsec / NSEC_PER_USEC + ts_frame.tv_sec * USEC_PER_SEC); \
++ if ((ts_frame.tv_nsec/NSEC_PER_USEC + ts_frame.tv_sec*USEC_PER_SEC) > \
++ 80000) \
++ dev_dbg(tsk->dev, "ts_frame larger than 80ms [0x%p] no-0x%x.\n"\
++ , tsk, tsk->task_no); \
++} while (0)
++#else
++#define CHECK_PERF(ts)
++#define DECLARE_PERF_VAR
++#define PRINT_TASK_STATISTICS
++#endif
++
++#define IPU_PP_CH_VF (IPU_TASK_ID_VF - 1)
++#define IPU_PP_CH_PP (IPU_TASK_ID_PP - 1)
++#define MAX_PP_CH (IPU_TASK_ID_MAX - 1)
++#define VDOA_DEF_TIMEOUT_MS (HZ/2)
++
++/* Strucutures and variables for exporting MXC IPU as device*/
++typedef enum {
++ STATE_OK = 0,
++ STATE_QUEUE,
++ STATE_IN_PROGRESS,
++ STATE_ERR,
++ STATE_TIMEOUT,
++ STATE_RES_TIMEOUT,
++ STATE_NO_IPU,
++ STATE_NO_IRQ,
++ STATE_IPU_BUSY,
++ STATE_IRQ_FAIL,
++ STATE_IRQ_TIMEOUT,
++ STATE_ENABLE_CHAN_FAIL,
++ STATE_DISABLE_CHAN_FAIL,
++ STATE_SEL_BUF_FAIL,
++ STATE_INIT_CHAN_FAIL,
++ STATE_LINK_CHAN_FAIL,
++ STATE_UNLINK_CHAN_FAIL,
++ STATE_INIT_CHAN_BUF_FAIL,
++ STATE_INIT_CHAN_BAND_FAIL,
++ STATE_SYS_NO_MEM,
++ STATE_VDOA_IRQ_TIMEOUT,
++ STATE_VDOA_IRQ_FAIL,
++ STATE_VDOA_TASK_FAIL,
++} ipu_state_t;
++
++enum {
++ INPUT_CHAN_VDI_P = 1,
++ INPUT_CHAN,
++ INPUT_CHAN_VDI_N,
++};
++
++struct ipu_state_msg {
++ int state;
++ char *msg;
++} state_msg[] = {
++ {STATE_OK, "ok"},
++ {STATE_QUEUE, "split queue"},
++ {STATE_IN_PROGRESS, "split in progress"},
++ {STATE_ERR, "error"},
++ {STATE_TIMEOUT, "split task timeout"},
++ {STATE_RES_TIMEOUT, "wait resource timeout"},
++ {STATE_NO_IPU, "no ipu found"},
++ {STATE_NO_IRQ, "no irq found for task"},
++ {STATE_IPU_BUSY, "ipu busy"},
++ {STATE_IRQ_FAIL, "request irq failed"},
++ {STATE_IRQ_TIMEOUT, "wait for irq timeout"},
++ {STATE_ENABLE_CHAN_FAIL, "ipu enable channel fail"},
++ {STATE_DISABLE_CHAN_FAIL, "ipu disable channel fail"},
++ {STATE_SEL_BUF_FAIL, "ipu select buf fail"},
++ {STATE_INIT_CHAN_FAIL, "ipu init channel fail"},
++ {STATE_LINK_CHAN_FAIL, "ipu link channel fail"},
++ {STATE_UNLINK_CHAN_FAIL, "ipu unlink channel fail"},
++ {STATE_INIT_CHAN_BUF_FAIL, "ipu init channel buffer fail"},
++ {STATE_INIT_CHAN_BAND_FAIL, "ipu init channel band mode fail"},
++ {STATE_SYS_NO_MEM, "sys no mem: -ENOMEM"},
++ {STATE_VDOA_IRQ_TIMEOUT, "wait for vdoa irq timeout"},
++ {STATE_VDOA_IRQ_FAIL, "vdoa irq fail"},
++ {STATE_VDOA_TASK_FAIL, "vdoa task fail"},
++};
++
++struct stripe_setting {
++ u32 iw;
++ u32 ih;
++ u32 ow;
++ u32 oh;
++ u32 outh_resize_ratio;
++ u32 outv_resize_ratio;
++ u32 i_left_pos;
++ u32 i_right_pos;
++ u32 i_top_pos;
++ u32 i_bottom_pos;
++ u32 o_left_pos;
++ u32 o_right_pos;
++ u32 o_top_pos;
++ u32 o_bottom_pos;
++ u32 rl_split_line;
++ u32 ud_split_line;
++};
++
++struct task_set {
++#define NULL_MODE 0x0
++#define IC_MODE 0x1
++#define ROT_MODE 0x2
++#define VDI_MODE 0x4
++#define IPU_PREPROCESS_MODE_MASK (IC_MODE | ROT_MODE | VDI_MODE)
++/* VDOA_MODE means this task use vdoa, and VDOA has two modes:
++ * BAND MODE and non-BAND MODE. Non-band mode will do transfer data
++ * to memory. BAND mode needs hareware sync with IPU, it is used default
++ * if connected to VDIC.
++ */
++#define VDOA_MODE 0x8
++#define VDOA_BAND_MODE 0x10
++ u8 mode;
++#define IC_VF 0x1
++#define IC_PP 0x2
++#define ROT_VF 0x4
++#define ROT_PP 0x8
++#define VDI_VF 0x10
++#define VDOA_ONLY 0x20
++ u8 task;
++#define NO_SPLIT 0x0
++#define RL_SPLIT 0x1
++#define UD_SPLIT 0x2
++#define LEFT_STRIPE 0x1
++#define RIGHT_STRIPE 0x2
++#define UP_STRIPE 0x4
++#define DOWN_STRIPE 0x8
++#define SPLIT_MASK 0xF
++ u8 split_mode;
++ u8 band_lines;
++ ipu_channel_t ic_chan;
++ ipu_channel_t rot_chan;
++ ipu_channel_t vdi_ic_p_chan;
++ ipu_channel_t vdi_ic_n_chan;
++
++ u32 i_off;
++ u32 i_uoff;
++ u32 i_voff;
++ u32 istride;
++
++ u32 ov_off;
++ u32 ov_uoff;
++ u32 ov_voff;
++ u32 ovstride;
++
++ u32 ov_alpha_off;
++ u32 ov_alpha_stride;
++
++ u32 o_off;
++ u32 o_uoff;
++ u32 o_voff;
++ u32 ostride;
++
++ u32 r_fmt;
++ u32 r_width;
++ u32 r_height;
++ u32 r_stride;
++ dma_addr_t r_paddr;
++
++ struct stripe_setting sp_setting;
++};
++
++struct ipu_split_task {
++ struct ipu_task task;
++ struct ipu_task_entry *parent_task;
++ struct ipu_task_entry *child_task;
++ u32 task_no;
++};
++
++struct ipu_task_entry {
++ struct ipu_input input;
++ struct ipu_output output;
++
++ bool overlay_en;
++ struct ipu_overlay overlay;
++#define DEF_TIMEOUT_MS 1000
++#define DEF_DELAY_MS 20
++ int timeout;
++ int irq;
++
++ u8 task_id;
++ u8 ipu_id;
++ u8 task_in_list;
++ u8 split_done;
++ struct mutex split_lock;
++ wait_queue_head_t split_waitq;
++
++ struct list_head node;
++ struct list_head split_list;
++ struct ipu_soc *ipu;
++ struct device *dev;
++ struct task_set set;
++ wait_queue_head_t task_waitq;
++ struct completion irq_comp;
++ struct kref refcount;
++ ipu_state_t state;
++ u32 task_no;
++ atomic_t done;
++ atomic_t res_free;
++ atomic_t res_get;
++
++ struct ipu_task_entry *parent;
++ char *vditmpbuf[2];
++ u32 old_save_lines;
++ u32 old_size;
++ bool buf1filled;
++ bool buf0filled;
++
++ vdoa_handle_t vdoa_handle;
++ struct vdoa_output_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ int size;
++ } vdoa_dma;
++
++#ifdef DBG_IPU_PERF
++ struct timespec ts_queue;
++ struct timespec ts_dotask;
++ struct timespec ts_waitirq;
++ struct timespec ts_inirq;
++ struct timespec ts_wakeup;
++ struct timespec ts_rel;
++#endif
++};
++
++struct ipu_channel_tabel {
++ struct mutex lock;
++ u8 used[MXC_IPU_MAX_NUM][MAX_PP_CH];
++ u8 vdoa_used;
++};
++
++struct ipu_thread_data {
++ struct ipu_soc *ipu;
++ u32 id;
++ u32 is_vdoa;
++};
++
++struct ipu_alloc_list {
++ struct list_head list;
++ dma_addr_t phy_addr;
++ void *cpu_addr;
++ u32 size;
++ void *file_index;
++};
++
++static LIST_HEAD(ipu_alloc_list);
++static DEFINE_MUTEX(ipu_alloc_lock);
++static struct ipu_channel_tabel ipu_ch_tbl;
++static LIST_HEAD(ipu_task_list);
++static DEFINE_SPINLOCK(ipu_task_list_lock);
++static DECLARE_WAIT_QUEUE_HEAD(thread_waitq);
++static DECLARE_WAIT_QUEUE_HEAD(res_waitq);
++static atomic_t req_cnt;
++static atomic_t file_index = ATOMIC_INIT(1);
++static int major;
++static int max_ipu_no;
++static int thread_id;
++static atomic_t frame_no;
++static struct class *ipu_class;
++static struct device *ipu_dev;
++static int debug;
++module_param(debug, int, 0600);
++#ifdef DBG_IPU_PERF
++static struct timespec ts_frame_max;
++static u32 ts_frame_avg;
++static atomic_t frame_cnt;
++#endif
++
++static bool deinterlace_3_field(struct ipu_task_entry *t)
++{
++ return ((t->set.mode & VDI_MODE) &&
++ (t->input.deinterlace.motion != HIGH_MOTION));
++}
++
++static u32 tiled_filed_size(struct ipu_task_entry *t)
++{
++ u32 field_size;
++
++ /* note: page_align is required by VPU hw ouput buffer */
++ field_size = TILED_NV12_FRAME_SIZE(t->input.width, t->input.height/2);
++ return field_size;
++}
++
++static bool only_ic(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return ((mode == IC_MODE) || (mode == VDI_MODE));
++}
++
++static bool only_rot(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return (mode == ROT_MODE);
++}
++
++static bool ic_and_rot(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return ((mode == (IC_MODE | ROT_MODE)) ||
++ (mode == (VDI_MODE | ROT_MODE)));
++}
++
++static bool need_split(struct ipu_task_entry *t)
++{
++ return ((t->set.split_mode != NO_SPLIT) || (t->task_no & SPLIT_MASK));
++}
++
++unsigned int fmt_to_bpp(unsigned int pixelformat)
++{
++ u32 bpp;
++
++ switch (pixelformat) {
++ case IPU_PIX_FMT_RGB565:
++ /*interleaved 422*/
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ /*non-interleaved 422*/
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ bpp = 16;
++ break;
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_YUV444P:
++ bpp = 24;
++ break;
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ bpp = 32;
++ break;
++ /*non-interleaved 420*/
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_NV12:
++ bpp = 12;
++ break;
++ default:
++ bpp = 8;
++ break;
++ }
++ return bpp;
++}
++EXPORT_SYMBOL_GPL(fmt_to_bpp);
++
++cs_t colorspaceofpixel(int fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_ABGR32:
++ return RGB_CS;
++ break;
++ case IPU_PIX_FMT_UYVY:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_YUV444P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_TILED_NV12:
++ case IPU_PIX_FMT_TILED_NV12F:
++ return YUV_CS;
++ break;
++ default:
++ return NULL_CS;
++ }
++}
++EXPORT_SYMBOL_GPL(colorspaceofpixel);
++
++int need_csc(int ifmt, int ofmt)
++{
++ cs_t ics, ocs;
++
++ ics = colorspaceofpixel(ifmt);
++ ocs = colorspaceofpixel(ofmt);
++
++ if ((ics == NULL_CS) || (ocs == NULL_CS))
++ return -1;
++ else if (ics != ocs)
++ return 1;
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(need_csc);
++
++static int soc_max_in_width(u32 is_vdoa)
++{
++ return is_vdoa ? 8192 : 4096;
++}
++
++static int soc_max_vdi_in_width(void)
++{
++ return IPU_MAX_VDI_IN_WIDTH;
++}
++static int soc_max_in_height(void)
++{
++ return 4096;
++}
++
++static int soc_max_out_width(void)
++{
++ /* mx51/mx53/mx6q is 1024*/
++ return 1024;
++}
++
++static int soc_max_out_height(void)
++{
++ /* mx51/mx53/mx6q is 1024*/
++ return 1024;
++}
++
++static void dump_task_info(struct ipu_task_entry *t)
++{
++ if (!debug)
++ return;
++ dev_dbg(t->dev, "[0x%p]input:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->input.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->input.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->input.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n", (void *)t, t->input.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n", (void *)t, t->input.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->input.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->input.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]input buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->input.paddr);
++ dev_dbg(t->dev, "[0x%p]\ti_off = 0x%x\n", (void *)t, t->set.i_off);
++ dev_dbg(t->dev, "[0x%p]\ti_uoff = 0x%x\n", (void *)t, t->set.i_uoff);
++ dev_dbg(t->dev, "[0x%p]\ti_voff = 0x%x\n", (void *)t, t->set.i_voff);
++ dev_dbg(t->dev, "[0x%p]\tistride = %d\n", (void *)t, t->set.istride);
++ if (t->input.deinterlace.enable) {
++ dev_dbg(t->dev, "[0x%p]deinterlace enabled with:\n", (void *)t);
++ if (t->input.deinterlace.motion != HIGH_MOTION) {
++ dev_dbg(t->dev, "[0x%p]\tlow/medium motion\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr_n = 0x%x\n",
++ (void *)t, t->input.paddr_n);
++ } else
++ dev_dbg(t->dev, "[0x%p]\thigh motion\n", (void *)t);
++ }
++
++ dev_dbg(t->dev, "[0x%p]output:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->output.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->output.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->output.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n", (void *)t, t->output.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n", (void *)t, t->output.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->output.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->output.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]\trotate = %d\n", (void *)t, t->output.rotate);
++ dev_dbg(t->dev, "[0x%p]output buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->output.paddr);
++ dev_dbg(t->dev, "[0x%p]\to_off = 0x%x\n", (void *)t, t->set.o_off);
++ dev_dbg(t->dev, "[0x%p]\to_uoff = 0x%x\n", (void *)t, t->set.o_uoff);
++ dev_dbg(t->dev, "[0x%p]\to_voff = 0x%x\n", (void *)t, t->set.o_voff);
++ dev_dbg(t->dev, "[0x%p]\tostride = %d\n", (void *)t, t->set.ostride);
++
++ if (t->overlay_en) {
++ dev_dbg(t->dev, "[0x%p]overlay:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n",
++ (void *)t, t->overlay.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n",
++ (void *)t, t->overlay.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n",
++ (void *)t, t->overlay.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n",
++ (void *)t, t->overlay.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n",
++ (void *)t, t->overlay.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->overlay.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->overlay.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]overlay buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n",
++ (void *)t, t->overlay.paddr);
++ dev_dbg(t->dev, "[0x%p]\tov_off = 0x%x\n",
++ (void *)t, t->set.ov_off);
++ dev_dbg(t->dev, "[0x%p]\tov_uoff = 0x%x\n",
++ (void *)t, t->set.ov_uoff);
++ dev_dbg(t->dev, "[0x%p]\tov_voff = 0x%x\n",
++ (void *)t, t->set.ov_voff);
++ dev_dbg(t->dev, "[0x%p]\tovstride = %d\n",
++ (void *)t, t->set.ovstride);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ dev_dbg(t->dev, "[0x%p]local alpha enabled with:\n",
++ (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n",
++ (void *)t, t->overlay.alpha.loc_alp_paddr);
++ dev_dbg(t->dev, "[0x%p]\tov_alpha_off = 0x%x\n",
++ (void *)t, t->set.ov_alpha_off);
++ dev_dbg(t->dev, "[0x%p]\tov_alpha_stride = %d\n",
++ (void *)t, t->set.ov_alpha_stride);
++ } else
++ dev_dbg(t->dev, "[0x%p]globle alpha enabled with value 0x%x\n",
++ (void *)t, t->overlay.alpha.gvalue);
++ if (t->overlay.colorkey.enable)
++ dev_dbg(t->dev, "[0x%p]colorkey enabled with value 0x%x\n",
++ (void *)t, t->overlay.colorkey.value);
++ }
++
++ dev_dbg(t->dev, "[0x%p]want task_id = %d\n", (void *)t, t->task_id);
++ dev_dbg(t->dev, "[0x%p]want task mode is 0x%x\n",
++ (void *)t, t->set.mode);
++ dev_dbg(t->dev, "[0x%p]\tIC_MODE = 0x%x\n", (void *)t, IC_MODE);
++ dev_dbg(t->dev, "[0x%p]\tROT_MODE = 0x%x\n", (void *)t, ROT_MODE);
++ dev_dbg(t->dev, "[0x%p]\tVDI_MODE = 0x%x\n", (void *)t, VDI_MODE);
++ dev_dbg(t->dev, "[0x%p]\tTask_no = 0x%x\n\n\n", (void *)t, t->task_no);
++}
++
++static void dump_check_err(struct device *dev, int err)
++{
++ switch (err) {
++ case IPU_CHECK_ERR_INPUT_CROP:
++ dev_err(dev, "input crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_OUTPUT_CROP:
++ dev_err(dev, "output crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_OVERLAY_CROP:
++ dev_err(dev, "overlay crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_INPUT_OVER_LIMIT:
++ dev_err(dev, "input over limitation\n");
++ break;
++ case IPU_CHECK_ERR_OVERLAY_WITH_VDI:
++ dev_err(dev, "do not support overlay with deinterlace\n");
++ break;
++ case IPU_CHECK_ERR_OV_OUT_NO_FIT:
++ dev_err(dev,
++ "width/height of overlay and ic output should be same\n");
++ break;
++ case IPU_CHECK_ERR_PROC_NO_NEED:
++ dev_err(dev, "no ipu processing need\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_INPUTW_OVER:
++ dev_err(dev, "split mode input width overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_INPUTH_OVER:
++ dev_err(dev, "split mode input height overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER:
++ dev_err(dev, "split mode output width overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER:
++ dev_err(dev, "split mode output height overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_WITH_ROT:
++ dev_err(dev, "not support split mode with rotation\n");
++ break;
++ case IPU_CHECK_ERR_W_DOWNSIZE_OVER:
++ dev_err(dev, "horizontal downsizing ratio overflow\n");
++ break;
++ case IPU_CHECK_ERR_H_DOWNSIZE_OVER:
++ dev_err(dev, "vertical downsizing ratio overflow\n");
++ break;
++ default:
++ break;
++ }
++}
++
++static void dump_check_warn(struct device *dev, int warn)
++{
++ if (warn & IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN)
++ dev_warn(dev, "input u/v offset not 8 align\n");
++ if (warn & IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN)
++ dev_warn(dev, "output u/v offset not 8 align\n");
++ if (warn & IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN)
++ dev_warn(dev, "overlay u/v offset not 8 align\n");
++}
++
++static int set_crop(struct ipu_crop *crop, int width, int height, int fmt)
++{
++ if ((width == 0) || (height == 0)) {
++ pr_err("Invalid param: width=%d, height=%d\n", width, height);
++ return -EINVAL;
++ }
++
++ if ((IPU_PIX_FMT_TILED_NV12 == fmt) ||
++ (IPU_PIX_FMT_TILED_NV12F == fmt)) {
++ if (crop->w || crop->h) {
++ if (((crop->w + crop->pos.x) > width)
++ || ((crop->h + crop->pos.y) > height)
++ || (0 != (crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->pos.x % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->pos.y % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ ) {
++ pr_err("set_crop error MB align.\n");
++ return -EINVAL;
++ }
++ } else {
++ crop->pos.x = 0;
++ crop->pos.y = 0;
++ crop->w = width;
++ crop->h = height;
++ if ((0 != (crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN))) {
++ pr_err("set_crop error w/h MB align.\n");
++ return -EINVAL;
++ }
++ }
++ } else {
++ if (crop->w || crop->h) {
++ if (((crop->w + crop->pos.x) > (width + 16))
++ || ((crop->h + crop->pos.y) > height + 16)) {
++ pr_err("set_crop error exceeds width/height.\n");
++ return -EINVAL;
++ }
++ } else {
++ crop->pos.x = 0;
++ crop->pos.y = 0;
++ crop->w = width;
++ crop->h = height;
++ }
++ crop->w -= crop->w%8;
++ crop->h -= crop->h%8;
++ }
++
++ if ((crop->w == 0) || (crop->h == 0)) {
++ pr_err("Invalid crop param: crop.w=%d, crop.h=%d\n",
++ crop->w, crop->h);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static void update_offset(unsigned int fmt,
++ unsigned int width, unsigned int height,
++ unsigned int pos_x, unsigned int pos_y,
++ int *off, int *uoff, int *voff, int *stride)
++{
++ /* NOTE: u v offset should based on start point of off*/
++ switch (fmt) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + (width/2) * (pos_y/2) + pos_x/2;
++ /* In case height is odd, round up to even */
++ *voff = *uoff + (width/2) * ((height+1)/2);
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ *off = pos_y * width + pos_x;
++ *voff = (width * (height - pos_y) - pos_x)
++ + (width/2) * (pos_y/2) + pos_x/2;
++ /* In case height is odd, round up to even */
++ *uoff = *voff + (width/2) * ((height+1)/2);
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ *off = pos_y * width + pos_x;
++ *voff = (width * (height - pos_y) - pos_x)
++ + (width/2) * pos_y + pos_x/2;
++ *uoff = *voff + (width/2) * height;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + (width/2) * pos_y + pos_x/2;
++ *voff = *uoff + (width/2) * height;
++ break;
++ case IPU_PIX_FMT_YUV444P:
++ *off = pos_y * width + pos_x;
++ *uoff = width * height;
++ *voff = width * height * 2;
++ break;
++ case IPU_PIX_FMT_NV12:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + width * (pos_y/2) + pos_x;
++ break;
++ case IPU_PIX_FMT_TILED_NV12:
++ /*
++ * tiled format, progressive:
++ * assuming that line is aligned with MB height (aligned to 16)
++ * offset = line * stride + (pixel / MB_width) * pixels_in_MB
++ * = line * stride + (pixel / 16) * 256
++ * = line * stride + pixel * 16
++ */
++ *off = pos_y * width + (pos_x << 4);
++ *uoff = ALIGN(width * height, SZ_4K) + (*off >> 1) - *off;
++ break;
++ case IPU_PIX_FMT_TILED_NV12F:
++ /*
++ * tiled format, interlaced:
++ * same as above, only number of pixels in MB is 128,
++ * instead of 256
++ */
++ *off = (pos_y >> 1) * width + (pos_x << 3);
++ *uoff = ALIGN(width * height/2, SZ_4K) + (*off >> 1) - *off;
++ break;
++ default:
++ *off = (pos_y * width + pos_x) * fmt_to_bpp(fmt)/8;
++ break;
++ }
++ *stride = width * bytes_per_pixel(fmt);
++}
++
++static int update_split_setting(struct ipu_task_entry *t, bool vdi_split)
++{
++ struct stripe_param left_stripe;
++ struct stripe_param right_stripe;
++ struct stripe_param up_stripe;
++ struct stripe_param down_stripe;
++ u32 iw, ih, ow, oh;
++ u32 max_width;
++ int ret;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT)
++ return IPU_CHECK_ERR_SPLIT_WITH_ROT;
++
++ iw = t->input.crop.w;
++ ih = t->input.crop.h;
++
++ ow = t->output.crop.w;
++ oh = t->output.crop.h;
++
++ memset(&left_stripe, 0, sizeof(left_stripe));
++ memset(&right_stripe, 0, sizeof(right_stripe));
++ memset(&up_stripe, 0, sizeof(up_stripe));
++ memset(&down_stripe, 0, sizeof(down_stripe));
++
++ if (t->set.split_mode & RL_SPLIT) {
++ /*
++ * We do want equal strips: initialize stripes in case
++ * calc_stripes returns before actually doing the calculation
++ */
++ left_stripe.input_width = iw / 2;
++ left_stripe.output_width = ow / 2;
++ right_stripe.input_column = iw / 2;
++ right_stripe.output_column = ow / 2;
++
++ if (vdi_split)
++ max_width = soc_max_vdi_in_width();
++ else
++ max_width = soc_max_out_width();
++ ret = ipu_calc_stripes_sizes(iw,
++ ow,
++ max_width,
++ (((unsigned long long)1) << 32), /* 32bit for fractional*/
++ 1, /* equal stripes */
++ t->input.format,
++ t->output.format,
++ &left_stripe,
++ &right_stripe);
++ if (ret < 0)
++ return IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++ else if (ret)
++ dev_dbg(t->dev, "Warn: no:0x%x,calc_stripes ret:%d\n",
++ t->task_no, ret);
++ t->set.sp_setting.iw = left_stripe.input_width;
++ t->set.sp_setting.ow = left_stripe.output_width;
++ t->set.sp_setting.outh_resize_ratio = left_stripe.irr;
++ t->set.sp_setting.i_left_pos = left_stripe.input_column;
++ t->set.sp_setting.o_left_pos = left_stripe.output_column;
++ t->set.sp_setting.i_right_pos = right_stripe.input_column;
++ t->set.sp_setting.o_right_pos = right_stripe.output_column;
++ } else {
++ t->set.sp_setting.iw = iw;
++ t->set.sp_setting.ow = ow;
++ t->set.sp_setting.outh_resize_ratio = 0;
++ t->set.sp_setting.i_left_pos = 0;
++ t->set.sp_setting.o_left_pos = 0;
++ t->set.sp_setting.i_right_pos = 0;
++ t->set.sp_setting.o_right_pos = 0;
++ }
++ if ((t->set.sp_setting.iw + t->set.sp_setting.i_right_pos) > (iw+16))
++ return IPU_CHECK_ERR_SPLIT_INPUTW_OVER;
++ if (((t->set.sp_setting.ow + t->set.sp_setting.o_right_pos) > ow)
++ || (t->set.sp_setting.ow > soc_max_out_width()))
++ return IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER;
++ if (rounddown(t->set.sp_setting.ow, 8) * 8 <=
++ rounddown(t->set.sp_setting.iw, 8))
++ return IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++
++ if (t->set.split_mode & UD_SPLIT) {
++ /*
++ * We do want equal strips: initialize stripes in case
++ * calc_stripes returns before actually doing the calculation
++ */
++ up_stripe.input_width = ih / 2;
++ up_stripe.output_width = oh / 2;
++ down_stripe.input_column = ih / 2;
++ down_stripe.output_column = oh / 2;
++ ret = ipu_calc_stripes_sizes(ih,
++ oh,
++ soc_max_out_height(),
++ (((unsigned long long)1) << 32), /* 32bit for fractional*/
++ 0x1 | 0x2, /* equal stripes and vertical */
++ t->input.format,
++ t->output.format,
++ &up_stripe,
++ &down_stripe);
++ if (ret < 0)
++ return IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++ else if (ret)
++ dev_err(t->dev, "Warn: no:0x%x,calc_stripes ret:%d\n",
++ t->task_no, ret);
++ t->set.sp_setting.ih = up_stripe.input_width;
++ t->set.sp_setting.oh = up_stripe.output_width;
++ t->set.sp_setting.outv_resize_ratio = up_stripe.irr;
++ t->set.sp_setting.i_top_pos = up_stripe.input_column;
++ t->set.sp_setting.o_top_pos = up_stripe.output_column;
++ t->set.sp_setting.i_bottom_pos = down_stripe.input_column;
++ t->set.sp_setting.o_bottom_pos = down_stripe.output_column;
++ } else {
++ t->set.sp_setting.ih = ih;
++ t->set.sp_setting.oh = oh;
++ t->set.sp_setting.outv_resize_ratio = 0;
++ t->set.sp_setting.i_top_pos = 0;
++ t->set.sp_setting.o_top_pos = 0;
++ t->set.sp_setting.i_bottom_pos = 0;
++ t->set.sp_setting.o_bottom_pos = 0;
++ }
++
++ /* downscale case: enforce limits */
++ if (((t->set.sp_setting.ih + t->set.sp_setting.i_bottom_pos) > (ih))
++ && (t->set.sp_setting.ih >= t->set.sp_setting.oh))
++ return IPU_CHECK_ERR_SPLIT_INPUTH_OVER;
++ /* upscale case: relax limits because ipu_calc_stripes_sizes() may
++ create input stripe that falls just outside of the input window */
++ else if ((t->set.sp_setting.ih + t->set.sp_setting.i_bottom_pos)
++ > (ih+16))
++ return IPU_CHECK_ERR_SPLIT_INPUTH_OVER;
++ if (((t->set.sp_setting.oh + t->set.sp_setting.o_bottom_pos) > oh)
++ || (t->set.sp_setting.oh > soc_max_out_height()))
++ return IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER;
++ if (rounddown(t->set.sp_setting.oh, 8) * 8 <=
++ rounddown(t->set.sp_setting.ih, 8))
++ return IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++
++ return IPU_CHECK_OK;
++}
++
++static int check_task(struct ipu_task_entry *t)
++{
++ int tmp;
++ int ret = IPU_CHECK_OK;
++ int timeout;
++ bool vdi_split = false;
++ int ocw, och;
++
++ if ((IPU_PIX_FMT_TILED_NV12 == t->overlay.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->overlay.format) ||
++ (IPU_PIX_FMT_TILED_NV12 == t->output.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->output.format) ||
++ ((IPU_PIX_FMT_TILED_NV12F == t->input.format) &&
++ !t->input.deinterlace.enable)) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++
++ /* check input */
++ ret = set_crop(&t->input.crop, t->input.width, t->input.height,
++ t->input.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_INPUT_CROP;
++ goto done;
++ } else
++ update_offset(t->input.format, t->input.width, t->input.height,
++ t->input.crop.pos.x, t->input.crop.pos.y,
++ &t->set.i_off, &t->set.i_uoff,
++ &t->set.i_voff, &t->set.istride);
++
++ /* check output */
++ ret = set_crop(&t->output.crop, t->output.width, t->output.height,
++ t->output.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_OUTPUT_CROP;
++ goto done;
++ } else
++ update_offset(t->output.format,
++ t->output.width, t->output.height,
++ t->output.crop.pos.x, t->output.crop.pos.y,
++ &t->set.o_off, &t->set.o_uoff,
++ &t->set.o_voff, &t->set.ostride);
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*
++ * Cache output width and height and
++ * swap them so that we may check
++ * downsize overflow correctly.
++ */
++ ocw = t->output.crop.h;
++ och = t->output.crop.w;
++ } else {
++ ocw = t->output.crop.w;
++ och = t->output.crop.h;
++ }
++
++ if (ocw * 8 <= t->input.crop.w) {
++ ret = IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++ goto done;
++ }
++
++ if (och * 8 <= t->input.crop.h) {
++ ret = IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++ goto done;
++ }
++
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ if ((t->input.crop.w > soc_max_in_width(1)) ||
++ (t->input.crop.h > soc_max_in_height())) {
++ ret = IPU_CHECK_ERR_INPUT_OVER_LIMIT;
++ goto done;
++ }
++ /* output fmt: NV12 and YUYV, now don't support resize */
++ if (((IPU_PIX_FMT_NV12 != t->output.format) &&
++ (IPU_PIX_FMT_YUYV != t->output.format)) ||
++ (t->input.crop.w != t->output.crop.w) ||
++ (t->input.crop.h != t->output.crop.h)) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++ }
++
++ /* check overlay if there is */
++ if (t->overlay_en) {
++ if (t->input.deinterlace.enable) {
++ ret = IPU_CHECK_ERR_OVERLAY_WITH_VDI;
++ goto done;
++ }
++
++ ret = set_crop(&t->overlay.crop, t->overlay.width,
++ t->overlay.height, t->overlay.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_OVERLAY_CROP;
++ goto done;
++ } else {
++ ocw = t->output.crop.w;
++ och = t->output.crop.h;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ ocw = t->output.crop.h;
++ och = t->output.crop.w;
++ }
++ if ((t->overlay.crop.w != ocw) ||
++ (t->overlay.crop.h != och)) {
++ ret = IPU_CHECK_ERR_OV_OUT_NO_FIT;
++ goto done;
++ }
++
++ update_offset(t->overlay.format,
++ t->overlay.width, t->overlay.height,
++ t->overlay.crop.pos.x, t->overlay.crop.pos.y,
++ &t->set.ov_off, &t->set.ov_uoff,
++ &t->set.ov_voff, &t->set.ovstride);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ t->set.ov_alpha_stride = t->overlay.width;
++ t->set.ov_alpha_off = t->overlay.crop.pos.y *
++ t->overlay.width + t->overlay.crop.pos.x;
++ }
++ }
++ }
++
++ /* input overflow? */
++ if (!((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format))) {
++ if ((t->input.crop.w > soc_max_in_width(0)) ||
++ (t->input.crop.h > soc_max_in_height())) {
++ ret = IPU_CHECK_ERR_INPUT_OVER_LIMIT;
++ goto done;
++ }
++ }
++
++ /* check task mode */
++ t->set.mode = NULL_MODE;
++ t->set.split_mode = NO_SPLIT;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*output swap*/
++ tmp = t->output.crop.w;
++ t->output.crop.w = t->output.crop.h;
++ t->output.crop.h = tmp;
++ }
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT)
++ t->set.mode |= ROT_MODE;
++
++ /*need resize or CSC?*/
++ if ((t->input.crop.w != t->output.crop.w) ||
++ (t->input.crop.h != t->output.crop.h) ||
++ need_csc(t->input.format, t->output.format))
++ t->set.mode |= IC_MODE;
++
++ /*need flip?*/
++ if ((t->set.mode == NULL_MODE) && (t->output.rotate > IPU_ROTATE_NONE))
++ t->set.mode |= IC_MODE;
++
++ /*need IDMAC do format(same color space)?*/
++ if ((t->set.mode == NULL_MODE) && (t->input.format != t->output.format))
++ t->set.mode |= IC_MODE;
++
++ /*overlay support*/
++ if (t->overlay_en)
++ t->set.mode |= IC_MODE;
++
++ /*deinterlace*/
++ if (t->input.deinterlace.enable) {
++ t->set.mode &= ~IC_MODE;
++ t->set.mode |= VDI_MODE;
++ }
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ if (t->set.mode & ROT_MODE) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++ t->set.mode |= VDOA_MODE;
++ if (IPU_PIX_FMT_TILED_NV12F == t->input.format)
++ t->set.mode |= VDOA_BAND_MODE;
++ t->set.mode &= ~IC_MODE;
++ }
++
++ if ((t->set.mode & (IC_MODE | VDI_MODE)) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ if (t->output.crop.w > soc_max_out_width())
++ t->set.split_mode |= RL_SPLIT;
++ if (t->output.crop.h > soc_max_out_height())
++ t->set.split_mode |= UD_SPLIT;
++ if (!t->set.split_mode && (t->set.mode & VDI_MODE) &&
++ (t->input.crop.w > soc_max_vdi_in_width())) {
++ t->set.split_mode |= RL_SPLIT;
++ vdi_split = true;
++ }
++ if (t->set.split_mode) {
++ if ((t->set.split_mode == RL_SPLIT) ||
++ (t->set.split_mode == UD_SPLIT))
++ timeout = DEF_TIMEOUT_MS * 2 + DEF_DELAY_MS;
++ else
++ timeout = DEF_TIMEOUT_MS * 4 + DEF_DELAY_MS;
++ if (t->timeout < timeout)
++ t->timeout = timeout;
++
++ ret = update_split_setting(t, vdi_split);
++ if (ret > IPU_CHECK_ERR_MIN)
++ goto done;
++ }
++ }
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*output swap*/
++ tmp = t->output.crop.w;
++ t->output.crop.w = t->output.crop.h;
++ t->output.crop.h = tmp;
++ }
++
++ if (t->set.mode == NULL_MODE) {
++ ret = IPU_CHECK_ERR_PROC_NO_NEED;
++ goto done;
++ }
++
++ if ((t->set.i_uoff % 8) || (t->set.i_voff % 8))
++ ret |= IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN;
++ if ((t->set.o_uoff % 8) || (t->set.o_voff % 8))
++ ret |= IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN;
++ if (t->overlay_en && ((t->set.ov_uoff % 8) || (t->set.ov_voff % 8)))
++ ret |= IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN;
++
++done:
++ /* dump msg */
++ if (debug) {
++ if (ret > IPU_CHECK_ERR_MIN)
++ dump_check_err(t->dev, ret);
++ else if (ret != IPU_CHECK_OK)
++ dump_check_warn(t->dev, ret);
++ }
++
++ return ret;
++}
++
++static int prepare_task(struct ipu_task_entry *t)
++{
++ int ret = 0;
++
++ ret = check_task(t);
++ if (ret > IPU_CHECK_ERR_MIN)
++ return -EINVAL;
++
++ if (t->set.mode & VDI_MODE) {
++ t->task_id = IPU_TASK_ID_VF;
++ t->set.task = VDI_VF;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_VF;
++ }
++
++ if (VDOA_MODE == t->set.mode) {
++ if (t->set.task != 0) {
++ dev_err(t->dev, "ERR: vdoa only task:0x%x, [0x%p].\n",
++ t->set.task, t);
++ return -EINVAL;
++ }
++ t->set.task |= VDOA_ONLY;
++ }
++
++ if (VDOA_BAND_MODE & t->set.mode) {
++ /* to save band size: 1<<3 = 8 lines */
++ t->set.band_lines = 3;
++ }
++
++ dump_task_info(t);
++
++ return ret;
++}
++
++static uint32_t ic_vf_pp_is_busy(struct ipu_soc *ipu, bool is_vf)
++{
++ uint32_t status;
++ uint32_t status_vf;
++ uint32_t status_rot;
++
++ if (is_vf) {
++ status = ipu_channel_status(ipu, MEM_VDI_PRP_VF_MEM);
++ status_vf = ipu_channel_status(ipu, MEM_PRP_VF_MEM);
++ status_rot = ipu_channel_status(ipu, MEM_ROT_VF_MEM);
++ return status || status_vf || status_rot;
++ } else {
++ status = ipu_channel_status(ipu, MEM_PP_MEM);
++ status_rot = ipu_channel_status(ipu, MEM_ROT_PP_MEM);
++ return status || status_rot;
++ }
++}
++
++static int _get_vdoa_ipu_res(struct ipu_task_entry *t)
++{
++ int i;
++ struct ipu_soc *ipu;
++ u8 *used;
++ uint32_t found_ipu = 0;
++ uint32_t found_vdoa = 0;
++ struct ipu_channel_tabel *tbl = &ipu_ch_tbl;
++
++ mutex_lock(&tbl->lock);
++ if (t->set.mode & VDOA_MODE) {
++ if (NULL != t->vdoa_handle)
++ found_vdoa = 1;
++ else {
++ found_vdoa = tbl->vdoa_used ? 0 : 1;
++ if (found_vdoa) {
++ tbl->vdoa_used = 1;
++ vdoa_get_handle(&t->vdoa_handle);
++ } else
++ /* first get vdoa->ipu resource sequence */
++ goto out;
++ if (t->set.task & VDOA_ONLY)
++ goto out;
++ }
++ }
++
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu = ipu_get_soc(i);
++ if (IS_ERR(ipu))
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, ipu:%d\n",
++ t->task_no, found_vdoa, i);
++
++ used = &tbl->used[i][IPU_PP_CH_VF];
++ if (t->set.mode & VDI_MODE) {
++ if (0 == *used) {
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ } else if ((t->set.mode & IC_MODE) || only_rot(t->set.mode)) {
++ if (0 == *used) {
++ t->task_id = IPU_TASK_ID_VF;
++ if (t->set.mode & IC_MODE)
++ t->set.task |= IC_VF;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_VF;
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ } else
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, mode:0x%x\n",
++ t->task_no, found_vdoa, t->set.mode);
++ }
++ if (found_ipu)
++ goto next;
++
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu = ipu_get_soc(i);
++ if (IS_ERR(ipu))
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, ipu:%d\n",
++ t->task_no, found_vdoa, i);
++
++ if ((t->set.mode & IC_MODE) || only_rot(t->set.mode)) {
++ used = &tbl->used[i][IPU_PP_CH_PP];
++ if (0 == *used) {
++ t->task_id = IPU_TASK_ID_PP;
++ if (t->set.mode & IC_MODE)
++ t->set.task |= IC_PP;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_PP;
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ }
++ }
++
++next:
++ if (found_ipu) {
++ t->ipu = ipu;
++ t->ipu_id = i;
++ t->dev = ipu->dev;
++ if (atomic_inc_return(&t->res_get) == 2)
++ dev_err(t->dev,
++ "ERR no:0x%x,found_vdoa:%d,get ipu twice\n",
++ t->task_no, found_vdoa);
++ }
++out:
++ dev_dbg(t->dev,
++ "%s:no:0x%x,found_vdoa:%d, found_ipu:%d\n",
++ __func__, t->task_no, found_vdoa, found_ipu);
++ mutex_unlock(&tbl->lock);
++ if (t->set.task & VDOA_ONLY)
++ return found_vdoa;
++ else if (t->set.mode & VDOA_MODE)
++ return found_vdoa && found_ipu;
++ else
++ return found_ipu;
++}
++
++static void put_vdoa_ipu_res(struct ipu_task_entry *tsk, int vdoa_only)
++{
++ int ret;
++ int rel_vdoa = 0, rel_ipu = 0;
++ struct ipu_channel_tabel *tbl = &ipu_ch_tbl;
++
++ mutex_lock(&tbl->lock);
++ if (tsk->set.mode & VDOA_MODE) {
++ if (!tbl->vdoa_used && tsk->vdoa_handle)
++ dev_err(tsk->dev,
++ "ERR no:0x%x,vdoa not used,mode:0x%x\n",
++ tsk->task_no, tsk->set.mode);
++ if (tbl->vdoa_used && tsk->vdoa_handle) {
++ tbl->vdoa_used = 0;
++ vdoa_put_handle(&tsk->vdoa_handle);
++ if (tsk->ipu)
++ tsk->ipu->vdoa_en = 0;
++ rel_vdoa = 1;
++ if (vdoa_only || (tsk->set.task & VDOA_ONLY))
++ goto out;
++ }
++ }
++
++ tbl->used[tsk->ipu_id][tsk->task_id - 1] = 0;
++ rel_ipu = 1;
++ ret = atomic_inc_return(&tsk->res_free);
++ if (ret == 2)
++ dev_err(tsk->dev,
++ "ERR no:0x%x,rel_vdoa:%d,put ipu twice\n",
++ tsk->task_no, rel_vdoa);
++out:
++ dev_dbg(tsk->dev,
++ "%s:no:0x%x,rel_vdoa:%d, rel_ipu:%d\n",
++ __func__, tsk->task_no, rel_vdoa, rel_ipu);
++ mutex_unlock(&tbl->lock);
++}
++
++static int get_vdoa_ipu_res(struct ipu_task_entry *t)
++{
++ int ret;
++ uint32_t found = 0;
++
++ found = _get_vdoa_ipu_res(t);
++ if (!found) {
++ t->ipu_id = -1;
++ t->ipu = NULL;
++ /* blocking to get resource */
++ ret = atomic_inc_return(&req_cnt);
++ dev_dbg(t->dev,
++ "wait_res:no:0x%x,req_cnt:%d\n", t->task_no, ret);
++ ret = wait_event_timeout(res_waitq, _get_vdoa_ipu_res(t),
++ msecs_to_jiffies(t->timeout - DEF_DELAY_MS));
++ if (ret == 0) {
++ dev_err(t->dev, "ERR[0x%p,no-0x%x] wait_res timeout:%dms!\n",
++ t, t->task_no, t->timeout - DEF_DELAY_MS);
++ ret = -ETIMEDOUT;
++ t->state = STATE_RES_TIMEOUT;
++ goto out;
++ } else {
++ if (!(t->set.task & VDOA_ONLY) && (!t->ipu))
++ dev_err(t->dev,
++ "ERR[no-0x%x] can not get ipu!\n",
++ t->task_no);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0)
++ ret = atomic_dec_return(&req_cnt);
++ else
++ dev_err(t->dev,
++ "ERR[no-0x%x] req_cnt:%d mismatch!\n",
++ t->task_no, ret);
++ dev_dbg(t->dev, "no-0x%x,[0x%p],req_cnt:%d, got_res!\n",
++ t->task_no, t, ret);
++ found = 1;
++ }
++ }
++
++out:
++ return found;
++}
++
++static struct ipu_task_entry *create_task_entry(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++
++ tsk = kzalloc(sizeof(struct ipu_task_entry), GFP_KERNEL);
++ if (!tsk)
++ return ERR_PTR(-ENOMEM);
++ kref_init(&tsk->refcount);
++ tsk->state = -EINVAL;
++ tsk->ipu_id = -1;
++ tsk->dev = ipu_dev;
++ tsk->input = task->input;
++ tsk->output = task->output;
++ tsk->overlay_en = task->overlay_en;
++ if (tsk->overlay_en)
++ tsk->overlay = task->overlay;
++ if (task->timeout > DEF_TIMEOUT_MS)
++ tsk->timeout = task->timeout;
++ else
++ tsk->timeout = DEF_TIMEOUT_MS;
++
++ return tsk;
++}
++
++static void task_mem_free(struct kref *ref)
++{
++ struct ipu_task_entry *tsk =
++ container_of(ref, struct ipu_task_entry, refcount);
++ kfree(tsk);
++}
++
++int create_split_child_task(struct ipu_split_task *sp_task)
++{
++ int ret = 0;
++ struct ipu_task_entry *tsk;
++
++ tsk = create_task_entry(&sp_task->task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ sp_task->child_task = tsk;
++ tsk->task_no = sp_task->task_no;
++
++ ret = prepare_task(tsk);
++ if (ret < 0)
++ goto err;
++
++ tsk->parent = sp_task->parent_task;
++ tsk->set.sp_setting = sp_task->parent_task->set.sp_setting;
++
++ list_add(&tsk->node, &tsk->parent->split_list);
++ dev_dbg(tsk->dev, "[0x%p] sp_tsk Q list,no-0x%x\n", tsk, tsk->task_no);
++ tsk->state = STATE_QUEUE;
++ CHECK_PERF(&tsk->ts_queue);
++err:
++ return ret;
++}
++
++static inline int sp_task_check_done(struct ipu_split_task *sp_task,
++ struct ipu_task_entry *parent, int num, int *idx)
++{
++ int i;
++ int ret = 0;
++ struct ipu_task_entry *tsk;
++ struct mutex *lock = &parent->split_lock;
++
++ *idx = -EINVAL;
++ mutex_lock(lock);
++ for (i = 0; i < num; i++) {
++ tsk = sp_task[i].child_task;
++ if (tsk && tsk->split_done) {
++ *idx = i;
++ ret = 1;
++ goto out;
++ }
++ }
++
++out:
++ mutex_unlock(lock);
++ return ret;
++}
++
++static int create_split_task(
++ int stripe,
++ struct ipu_split_task *sp_task)
++{
++ struct ipu_task *task = &(sp_task->task);
++ struct ipu_task_entry *t = sp_task->parent_task;
++ int ret;
++
++ sp_task->task_no |= stripe;
++
++ task->input = t->input;
++ task->output = t->output;
++ task->overlay_en = t->overlay_en;
++ if (task->overlay_en)
++ task->overlay = t->overlay;
++ task->task_id = t->task_id;
++ if ((t->set.split_mode == RL_SPLIT) ||
++ (t->set.split_mode == UD_SPLIT))
++ task->timeout = t->timeout / 2;
++ else
++ task->timeout = t->timeout / 4;
++
++ task->input.crop.w = t->set.sp_setting.iw;
++ task->input.crop.h = t->set.sp_setting.ih;
++ if (task->overlay_en) {
++ task->overlay.crop.w = t->set.sp_setting.ow;
++ task->overlay.crop.h = t->set.sp_setting.oh;
++ }
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ task->output.crop.w = t->set.sp_setting.oh;
++ task->output.crop.h = t->set.sp_setting.ow;
++ t->set.sp_setting.rl_split_line = t->set.sp_setting.o_bottom_pos;
++ t->set.sp_setting.ud_split_line = t->set.sp_setting.o_right_pos;
++
++ } else {
++ task->output.crop.w = t->set.sp_setting.ow;
++ task->output.crop.h = t->set.sp_setting.oh;
++ t->set.sp_setting.rl_split_line = t->set.sp_setting.o_right_pos;
++ t->set.sp_setting.ud_split_line = t->set.sp_setting.o_bottom_pos;
++ }
++
++ if (stripe & LEFT_STRIPE)
++ task->input.crop.pos.x += t->set.sp_setting.i_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->input.crop.pos.x += t->set.sp_setting.i_right_pos;
++ if (stripe & UP_STRIPE)
++ task->input.crop.pos.y += t->set.sp_setting.i_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->input.crop.pos.y += t->set.sp_setting.i_bottom_pos;
++
++ if (task->overlay_en) {
++ if (stripe & LEFT_STRIPE)
++ task->overlay.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->overlay.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->overlay.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->overlay.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ }
++
++ switch (t->output.rotate) {
++ case IPU_ROTATE_NONE:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ break;
++ case IPU_ROTATE_VERT_FLIP:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ break;
++ case IPU_ROTATE_HORIZ_FLIP:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ break;
++ case IPU_ROTATE_180:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ break;
++ case IPU_ROTATE_90_RIGHT:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_right_pos;
++ break;
++ case IPU_ROTATE_90_RIGHT_HFLIP:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_bottom_pos;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_right_pos;
++ break;
++ case IPU_ROTATE_90_RIGHT_VFLIP:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ break;
++ case IPU_ROTATE_90_LEFT:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_bottom_pos;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ break;
++ default:
++ dev_err(t->dev, "ERR:should not be here\n");
++ break;
++ }
++
++ ret = create_split_child_task(sp_task);
++ if (ret < 0)
++ dev_err(t->dev, "ERR:create_split_child_task() ret:%d\n", ret);
++ return ret;
++}
++
++static int queue_split_task(struct ipu_task_entry *t,
++ struct ipu_split_task *sp_task, uint32_t size)
++{
++ int err[4];
++ int ret = 0;
++ int i, j;
++ struct ipu_task_entry *tsk = NULL;
++ struct mutex *lock = &t->split_lock;
++
++ dev_dbg(t->dev, "Split task 0x%p, no-0x%x, size:%d\n",
++ t, t->task_no, size);
++ mutex_init(lock);
++ init_waitqueue_head(&t->split_waitq);
++ INIT_LIST_HEAD(&t->split_list);
++ for (j = 0; j < size; j++) {
++ memset(&sp_task[j], 0, sizeof(*sp_task));
++ sp_task[j].parent_task = t;
++ sp_task[j].task_no = t->task_no;
++ }
++
++ if (t->set.split_mode == RL_SPLIT) {
++ i = 0;
++ err[i] = create_split_task(RIGHT_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(LEFT_STRIPE, &sp_task[i]);
++ } else if (t->set.split_mode == UD_SPLIT) {
++ i = 0;
++ err[i] = create_split_task(DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(UP_STRIPE, &sp_task[i]);
++ } else {
++ i = 0;
++ err[i] = create_split_task(RIGHT_STRIPE | DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(LEFT_STRIPE | DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 2;
++ err[i] = create_split_task(RIGHT_STRIPE | UP_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 3;
++ err[i] = create_split_task(LEFT_STRIPE | UP_STRIPE, &sp_task[i]);
++ }
++
++err_start:
++ for (j = 0; j < (i + 1); j++) {
++ if (err[j] < 0) {
++ if (sp_task[j].child_task)
++ dev_err(t->dev,
++ "sp_task[%d],no-0x%x fail state:%d, queue err:%d.\n",
++ j, sp_task[j].child_task->task_no,
++ sp_task[j].child_task->state, err[j]);
++ goto err_exit;
++ }
++ dev_dbg(t->dev, "[0x%p] sp_task[%d], no-0x%x state:%s, queue ret:%d.\n",
++ sp_task[j].child_task, j, sp_task[j].child_task->task_no,
++ state_msg[sp_task[j].child_task->state].msg, err[j]);
++ }
++
++ return ret;
++
++err_exit:
++ for (j = 0; j < (i + 1); j++) {
++ if (err[j] < 0 && !ret)
++ ret = err[j];
++ tsk = sp_task[j].child_task;
++ if (!tsk)
++ continue;
++ kfree(tsk);
++ }
++ t->state = STATE_ERR;
++ return ret;
++
++}
++
++static int init_tiled_buf(struct ipu_soc *ipu, struct ipu_task_entry *t,
++ ipu_channel_t channel, uint32_t ch_type)
++{
++ int ret = 0;
++ int i;
++ uint32_t ipu_fmt;
++ dma_addr_t inbuf_base = 0;
++ u32 field_size;
++ struct vdoa_params param;
++ struct vdoa_ipu_buf buf;
++ struct ipu_soc *ipu_idx;
++ u32 ipu_stride, obuf_size;
++ u32 height, width;
++ ipu_buffer_t type;
++
++ if ((IPU_PIX_FMT_YUYV != t->output.format) &&
++ (IPU_PIX_FMT_NV12 != t->output.format)) {
++ dev_err(t->dev, "ERR:[0x%d] output format\n", t->task_no);
++ return -EINVAL;
++ }
++
++ memset(&param, 0, sizeof(param));
++ /* init channel tiled bufs */
++ if (deinterlace_3_field(t) &&
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ field_size = tiled_filed_size(t);
++ if (INPUT_CHAN_VDI_P == ch_type) {
++ inbuf_base = t->input.paddr + field_size;
++ param.vfield_buf.prev_veba = inbuf_base + t->set.i_off;
++ } else if (INPUT_CHAN == ch_type) {
++ inbuf_base = t->input.paddr_n;
++ param.vfield_buf.cur_veba = inbuf_base + t->set.i_off;
++ } else if (INPUT_CHAN_VDI_N == ch_type) {
++ inbuf_base = t->input.paddr_n + field_size;
++ param.vfield_buf.next_veba = inbuf_base + t->set.i_off;
++ } else
++ return -EINVAL;
++ height = t->input.crop.h >> 1; /* field format for vdoa */
++ width = t->input.crop.w;
++ param.vfield_buf.vubo = t->set.i_uoff;
++ param.interlaced = 1;
++ param.scan_order = 1;
++ type = IPU_INPUT_BUFFER;
++ } else if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) &&
++ (INPUT_CHAN == ch_type)) {
++ height = t->input.crop.h;
++ width = t->input.crop.w;
++ param.vframe_buf.veba = t->input.paddr + t->set.i_off;
++ param.vframe_buf.vubo = t->set.i_uoff;
++ type = IPU_INPUT_BUFFER;
++ } else
++ return -EINVAL;
++
++ param.band_mode = (t->set.mode & VDOA_BAND_MODE) ? 1 : 0;
++ if (param.band_mode && (t->set.band_lines != 3) &&
++ (t->set.band_lines != 4) && (t->set.band_lines != 5))
++ return -EINVAL;
++ else if (param.band_mode)
++ param.band_lines = (1 << t->set.band_lines);
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu_idx = ipu_get_soc(i);
++ if (!IS_ERR(ipu_idx) && ipu_idx == ipu)
++ break;
++ }
++ if (t->set.task & VDOA_ONLY)
++ /* dummy, didn't need ipu res */
++ i = 0;
++ if (max_ipu_no == i) {
++ dev_err(t->dev, "ERR:[0x%p] get ipu num\n", t);
++ return -EINVAL;
++ }
++
++ param.ipu_num = i;
++ param.vpu_stride = t->input.width;
++ param.height = height;
++ param.width = width;
++ if (IPU_PIX_FMT_NV12 == t->output.format)
++ param.pfs = VDOA_PFS_NV12;
++ else
++ param.pfs = VDOA_PFS_YUYV;
++ ipu_fmt = (param.pfs == VDOA_PFS_YUYV) ? IPU_PIX_FMT_YUYV :
++ IPU_PIX_FMT_NV12;
++ ipu_stride = param.width * bytes_per_pixel(ipu_fmt);
++ obuf_size = PAGE_ALIGN(param.width * param.height *
++ fmt_to_bpp(ipu_fmt)/8);
++ dev_dbg(t->dev, "band_mode:%d, band_lines:%d\n",
++ param.band_mode, param.band_lines);
++ if (!param.band_mode) {
++ /* note: if only for tiled -> raster convert and
++ no other post-processing, we don't need alloc buf
++ and use output buffer directly.
++ */
++ if (t->set.task & VDOA_ONLY)
++ param.ieba0 = t->output.paddr;
++ else {
++ dev_err(t->dev, "ERR:[0x%d] vdoa task\n", t->task_no);
++ return -EINVAL;
++ }
++ } else {
++ if (IPU_PIX_FMT_TILED_NV12F != t->input.format) {
++ dev_err(t->dev, "ERR [0x%d] vdoa task\n", t->task_no);
++ return -EINVAL;
++ }
++ }
++ ret = vdoa_setup(t->vdoa_handle, &param);
++ if (ret)
++ goto done;
++ vdoa_get_output_buf(t->vdoa_handle, &buf);
++ if (t->set.task & VDOA_ONLY)
++ goto done;
++
++ ret = ipu_init_channel_buffer(ipu,
++ channel,
++ type,
++ ipu_fmt,
++ width,
++ height,
++ ipu_stride,
++ IPU_ROTATE_NONE,
++ buf.ieba0,
++ buf.ieba1,
++ 0,
++ buf.iubo,
++ 0);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ if (param.band_mode) {
++ ret = ipu_set_channel_bandmode(ipu, channel,
++ type, t->set.band_lines);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BAND_FAIL;
++ goto done;
++ }
++ }
++done:
++ return ret;
++}
++
++static int init_tiled_ch_bufs(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++
++ if (IPU_PIX_FMT_TILED_NV12 == t->input.format) {
++ ret = init_tiled_buf(ipu, t, t->set.ic_chan, INPUT_CHAN);
++ CHECK_RETCODE(ret < 0, "init tiled_ch", t->state, done, ret);
++ } else if (IPU_PIX_FMT_TILED_NV12F == t->input.format) {
++ ret = init_tiled_buf(ipu, t, t->set.ic_chan, INPUT_CHAN);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-c", t->state, done, ret);
++ ret = init_tiled_buf(ipu, t, t->set.vdi_ic_p_chan,
++ INPUT_CHAN_VDI_P);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-p", t->state, done, ret);
++ ret = init_tiled_buf(ipu, t, t->set.vdi_ic_n_chan,
++ INPUT_CHAN_VDI_N);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-n", t->state, done, ret);
++ } else {
++ ret = -EINVAL;
++ dev_err(t->dev, "ERR[no-0x%x] invalid fmt:0x%x!\n",
++ t->task_no, t->input.format);
++ }
++
++done:
++ return ret;
++}
++
++static int init_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++ ipu_channel_params_t params;
++ dma_addr_t inbuf = 0, ovbuf = 0, ov_alp_buf = 0;
++ dma_addr_t inbuf_p = 0, inbuf_n = 0;
++ dma_addr_t outbuf = 0;
++ int out_uoff = 0, out_voff = 0, out_rot;
++ int out_w = 0, out_h = 0, out_stride;
++ int out_fmt;
++ u32 vdi_frame_idx = 0;
++
++ memset(&params, 0, sizeof(params));
++
++ /* is it need link a rot channel */
++ if (ic_and_rot(t->set.mode)) {
++ outbuf = t->set.r_paddr;
++ out_w = t->set.r_width;
++ out_h = t->set.r_height;
++ out_stride = t->set.r_stride;
++ out_fmt = t->set.r_fmt;
++ out_uoff = 0;
++ out_voff = 0;
++ out_rot = IPU_ROTATE_NONE;
++ } else {
++ outbuf = t->output.paddr + t->set.o_off;
++ out_w = t->output.crop.w;
++ out_h = t->output.crop.h;
++ out_stride = t->set.ostride;
++ out_fmt = t->output.format;
++ out_uoff = t->set.o_uoff;
++ out_voff = t->set.o_voff;
++ out_rot = t->output.rotate;
++ }
++
++ /* settings */
++ params.mem_prp_vf_mem.in_width = t->input.crop.w;
++ params.mem_prp_vf_mem.out_width = out_w;
++ params.mem_prp_vf_mem.in_height = t->input.crop.h;
++ params.mem_prp_vf_mem.out_height = out_h;
++ params.mem_prp_vf_mem.in_pixel_fmt = t->input.format;
++ params.mem_prp_vf_mem.out_pixel_fmt = out_fmt;
++ params.mem_prp_vf_mem.motion_sel = t->input.deinterlace.motion;
++
++ params.mem_prp_vf_mem.outh_resize_ratio =
++ t->set.sp_setting.outh_resize_ratio;
++ params.mem_prp_vf_mem.outv_resize_ratio =
++ t->set.sp_setting.outv_resize_ratio;
++
++ if (t->overlay_en) {
++ params.mem_prp_vf_mem.in_g_pixel_fmt = t->overlay.format;
++ params.mem_prp_vf_mem.graphics_combine_en = 1;
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_GLOBAL)
++ params.mem_prp_vf_mem.global_alpha_en = 1;
++ else if (t->overlay.alpha.loc_alp_paddr)
++ params.mem_prp_vf_mem.alpha_chan_en = 1;
++ /* otherwise, alpha bending per pixel is used. */
++ params.mem_prp_vf_mem.alpha = t->overlay.alpha.gvalue;
++ if (t->overlay.colorkey.enable) {
++ params.mem_prp_vf_mem.key_color_en = 1;
++ params.mem_prp_vf_mem.key_color = t->overlay.colorkey.value;
++ }
++ }
++
++ if (t->input.deinterlace.enable) {
++ if (t->input.deinterlace.field_fmt & IPU_DEINTERLACE_FIELD_MASK)
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ else
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++
++ if (t->input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN)
++ vdi_frame_idx = t->input.deinterlace.field_fmt &
++ IPU_DEINTERLACE_RATE_FRAME1;
++ }
++
++ if (t->set.mode & VDOA_MODE)
++ ipu->vdoa_en = 1;
++
++ /* init channels */
++ if (!(t->set.task & VDOA_ONLY)) {
++ ret = ipu_init_channel(ipu, t->set.ic_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ }
++
++ if (deinterlace_3_field(t)) {
++ ret = ipu_init_channel(ipu, t->set.vdi_ic_p_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ ret = ipu_init_channel(ipu, t->set.vdi_ic_n_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ }
++
++ /* init channel bufs */
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ ret = init_tiled_ch_bufs(ipu, t);
++ if (ret < 0)
++ goto done;
++ } else {
++ if ((deinterlace_3_field(t)) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ if (params.mem_prp_vf_mem.field_fmt ==
++ IPU_DEINTERLACE_FIELD_TOP) {
++ if (vdi_frame_idx) {
++ inbuf_p = t->input.paddr + t->set.istride +
++ t->set.i_off;
++ inbuf = t->input.paddr_n + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.istride +
++ t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ } else {
++ inbuf_p = t->input.paddr + t->set.i_off;
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.i_off;
++ }
++ } else {
++ if (vdi_frame_idx) {
++ inbuf_p = t->input.paddr + t->set.i_off;
++ inbuf = t->input.paddr_n + t->set.istride + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++ } else {
++ inbuf_p = t->input.paddr + t->set.istride +
++ t->set.i_off;
++ inbuf = t->input.paddr + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.istride +
++ t->set.i_off;
++ }
++ }
++ } else {
++ if (t->input.deinterlace.enable) {
++ if (params.mem_prp_vf_mem.field_fmt ==
++ IPU_DEINTERLACE_FIELD_TOP) {
++ if (vdi_frame_idx) {
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ } else
++ inbuf = t->input.paddr + t->set.i_off;
++ } else {
++ if (vdi_frame_idx) {
++ inbuf = t->input.paddr + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++ } else
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ }
++ } else
++ inbuf = t->input.paddr + t->set.i_off;
++ }
++
++ if (t->overlay_en)
++ ovbuf = t->overlay.paddr + t->set.ov_off;
++ }
++ if (t->overlay_en && (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL))
++ ov_alp_buf = t->overlay.alpha.loc_alp_paddr
++ + t->set.ov_alpha_off;
++
++ if ((IPU_PIX_FMT_TILED_NV12 != t->input.format) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++ if (deinterlace_3_field(t) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.vdi_ic_p_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf_p,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.vdi_ic_n_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf_n,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (t->overlay_en) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER,
++ t->overlay.format,
++ t->overlay.crop.w,
++ t->overlay.crop.h,
++ t->set.ovstride,
++ IPU_ROTATE_NONE,
++ ovbuf,
++ 0,
++ 0,
++ t->set.ov_uoff,
++ t->set.ov_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER,
++ IPU_PIX_FMT_GENERIC,
++ t->overlay.crop.w,
++ t->overlay.crop.h,
++ t->set.ov_alpha_stride,
++ IPU_ROTATE_NONE,
++ ov_alp_buf,
++ 0,
++ 0,
++ 0, 0);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (!(t->set.task & VDOA_ONLY)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_OUTPUT_BUFFER,
++ out_fmt,
++ out_w,
++ out_h,
++ out_stride,
++ out_rot,
++ outbuf,
++ 0,
++ 0,
++ out_uoff,
++ out_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if ((t->set.mode & VDOA_BAND_MODE) && (t->set.task & VDI_VF)) {
++ ret = ipu_link_channels(ipu, MEM_VDOA_MEM, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_link_ch vdoa_ic",
++ STATE_LINK_CHAN_FAIL, done, ret);
++ }
++
++done:
++ return ret;
++}
++
++static void uninit_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret;
++
++ if ((t->set.mode & VDOA_BAND_MODE) && (t->set.task & VDI_VF)) {
++ ret = ipu_unlink_channels(ipu, MEM_VDOA_MEM, t->set.ic_chan);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_unlink_ch vdoa_ic",
++ STATE_UNLINK_CHAN_FAIL, ret);
++ }
++ ipu_uninit_channel(ipu, t->set.ic_chan);
++ if (deinterlace_3_field(t)) {
++ ipu_uninit_channel(ipu, t->set.vdi_ic_p_chan);
++ ipu_uninit_channel(ipu, t->set.vdi_ic_n_chan);
++ }
++}
++
++static int init_rot(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++ dma_addr_t inbuf = 0, outbuf = 0;
++ int in_uoff = 0, in_voff = 0;
++ int in_fmt, in_width, in_height, in_stride;
++
++ /* init channel */
++ ret = ipu_init_channel(ipu, t->set.rot_chan, NULL);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++
++ /* init channel buf */
++ /* is it need link to a ic channel */
++ if (ic_and_rot(t->set.mode)) {
++ in_fmt = t->set.r_fmt;
++ in_width = t->set.r_width;
++ in_height = t->set.r_height;
++ in_stride = t->set.r_stride;
++ inbuf = t->set.r_paddr;
++ in_uoff = 0;
++ in_voff = 0;
++ } else {
++ in_fmt = t->input.format;
++ in_width = t->input.crop.w;
++ in_height = t->input.crop.h;
++ in_stride = t->set.istride;
++ inbuf = t->input.paddr + t->set.i_off;
++ in_uoff = t->set.i_uoff;
++ in_voff = t->set.i_voff;
++ }
++ outbuf = t->output.paddr + t->set.o_off;
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.rot_chan,
++ IPU_INPUT_BUFFER,
++ in_fmt,
++ in_width,
++ in_height,
++ in_stride,
++ t->output.rotate,
++ inbuf,
++ 0,
++ 0,
++ in_uoff,
++ in_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.rot_chan,
++ IPU_OUTPUT_BUFFER,
++ t->output.format,
++ t->output.crop.w,
++ t->output.crop.h,
++ t->set.ostride,
++ IPU_ROTATE_NONE,
++ outbuf,
++ 0,
++ 0,
++ t->set.o_uoff,
++ t->set.o_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++done:
++ return ret;
++}
++
++static void uninit_rot(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ ipu_uninit_channel(ipu, t->set.rot_chan);
++}
++
++static int get_irq(struct ipu_task_entry *t)
++{
++ int irq;
++ ipu_channel_t chan;
++
++ if (only_ic(t->set.mode))
++ chan = t->set.ic_chan;
++ else
++ chan = t->set.rot_chan;
++
++ switch (chan) {
++ case MEM_ROT_VF_MEM:
++ irq = IPU_IRQ_PRP_VF_ROT_OUT_EOF;
++ break;
++ case MEM_ROT_PP_MEM:
++ irq = IPU_IRQ_PP_ROT_OUT_EOF;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ irq = IPU_IRQ_PRP_VF_OUT_EOF;
++ break;
++ case MEM_PP_MEM:
++ irq = IPU_IRQ_PP_OUT_EOF;
++ break;
++ case MEM_VDI_MEM:
++ irq = IPU_IRQ_VDIC_OUT_EOF;
++ break;
++ default:
++ irq = -EINVAL;
++ }
++
++ return irq;
++}
++
++static irqreturn_t task_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_task_entry *prev_tsk = dev_id;
++
++ CHECK_PERF(&prev_tsk->ts_inirq);
++ complete(&prev_tsk->irq_comp);
++ dev_dbg(prev_tsk->dev, "[0x%p] no-0x%x in-irq!",
++ prev_tsk, prev_tsk->task_no);
++
++ return IRQ_HANDLED;
++}
++
++/* Fix deinterlace up&down split mode medium line */
++static void vdi_split_process(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ u32 vdi_size;
++ u32 vdi_save_lines;
++ u32 stripe_mode;
++ u32 task_no;
++ u32 i, offset_addr;
++ unsigned char *base_off;
++ struct ipu_task_entry *parent = t->parent;
++
++ if (!parent) {
++ dev_err(t->dev, "ERR[0x%x]invalid parent\n", t->task_no);
++ return;
++ }
++ stripe_mode = t->task_no & 0xf;
++ task_no = t->task_no >> 4;
++
++ base_off = (char *) __va(t->output.paddr);
++ if (base_off == NULL) {
++ dev_err(t->dev, "ERR[0x%p]Falied get vitual address\n", t);
++ return;
++ }
++
++ vdi_save_lines = (t->output.crop.h - t->set.sp_setting.ud_split_line)/2;
++ vdi_size = vdi_save_lines * t->output.crop.w * 2;
++
++ if (vdi_save_lines <= 0) {
++ dev_err(t->dev, "[0x%p] vdi_save_line error\n", (void *)t);
++ return;
++ }
++
++ /*check vditmpbuf buffer have alloced or buffer size is changed */
++ if ((vdi_save_lines != parent->old_save_lines) ||
++ (vdi_size != parent->old_size)) {
++ if (parent->vditmpbuf[0] != NULL)
++ kfree(parent->vditmpbuf[0]);
++ if (parent->vditmpbuf[1] != NULL)
++ kfree(parent->vditmpbuf[1]);
++
++ parent->vditmpbuf[0] = kmalloc(vdi_size, GFP_KERNEL);
++ if (parent->vditmpbuf[0] == NULL) {
++ dev_err(t->dev,
++ "[0x%p]Falied Alloc vditmpbuf[0]\n", (void *)t);
++ return;
++ }
++ memset(parent->vditmpbuf[0], 0, vdi_size);
++
++ parent->vditmpbuf[1] = kmalloc(vdi_size, GFP_KERNEL);
++ if (parent->vditmpbuf[1] == NULL) {
++ dev_err(t->dev,
++ "[0x%p]Falied Alloc vditmpbuf[1]\n", (void *)t);
++ return;
++ }
++ memset(parent->vditmpbuf[1], 0, vdi_size);
++
++ parent->old_save_lines = vdi_save_lines;
++ parent->old_size = vdi_size;
++ }
++
++ /* UP stripe or UP&LEFT stripe */
++ if ((stripe_mode == UP_STRIPE) ||
++ (stripe_mode == (UP_STRIPE | LEFT_STRIPE))) {
++ if (!parent->buf0filled) {
++ offset_addr = t->set.o_off +
++ t->set.sp_setting.ud_split_line*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[0] + i*t->output.crop.w*2,
++ base_off + offset_addr +
++ i*t->set.ostride, t->output.crop.w*2);
++ parent->buf0filled = true;
++ } else {
++ offset_addr = t->set.o_off + (t->output.crop.h -
++ vdi_save_lines) * t->set.ostride;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[0] + i*t->output.crop.w*2,
++ t->output.crop.w*2);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf0filled = false;
++ }
++ }
++ /*Down stripe or Down&Left stripe*/
++ else if ((stripe_mode == DOWN_STRIPE) ||
++ (stripe_mode == (DOWN_STRIPE | LEFT_STRIPE))) {
++ if (!parent->buf0filled) {
++ offset_addr = t->set.o_off + vdi_save_lines*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[0] + i*t->output.crop.w*2,
++ base_off + offset_addr + i*t->set.ostride,
++ t->output.crop.w*2);
++ parent->buf0filled = true;
++ } else {
++ offset_addr = t->set.o_off;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[0] + i*t->output.crop.w*2,
++ t->output.crop.w*2);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf0filled = false;
++ }
++ }
++ /*Up&Right stripe*/
++ else if (stripe_mode == (UP_STRIPE | RIGHT_STRIPE)) {
++ if (!parent->buf1filled) {
++ offset_addr = t->set.o_off +
++ t->set.sp_setting.ud_split_line*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[1] + i*t->output.crop.w*2,
++ base_off + offset_addr + i*t->set.ostride,
++ t->output.crop.w*2);
++ parent->buf1filled = true;
++ } else {
++ offset_addr = t->set.o_off +
++ (t->output.crop.h - vdi_save_lines)*t->set.ostride;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[1] + i*t->output.crop.w*2,
++ t->output.crop.w*2);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf1filled = false;
++ }
++ }
++ /*Down stripe or Down&Right stript*/
++ else if (stripe_mode == (DOWN_STRIPE | RIGHT_STRIPE)) {
++ if (!parent->buf1filled) {
++ offset_addr = t->set.o_off + vdi_save_lines*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_save_lines*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_save_lines*t->set.ostride);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[1] + i*t->output.crop.w*2,
++ base_off + offset_addr + i*t->set.ostride,
++ t->output.crop.w*2);
++ parent->buf1filled = true;
++ } else {
++ offset_addr = t->set.o_off;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[1] + i*t->output.crop.w*2,
++ t->output.crop.w*2);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_save_lines*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_save_lines*t->set.ostride);
++ parent->buf1filled = false;
++ }
++ }
++}
++
++static void do_task_release(struct ipu_task_entry *t, int fail)
++{
++ int ret;
++ struct ipu_soc *ipu = t->ipu;
++
++ if (t->input.deinterlace.enable && !fail &&
++ (t->task_no & (UP_STRIPE | DOWN_STRIPE)))
++ vdi_split_process(ipu, t);
++
++ ipu_free_irq(ipu, t->irq, t);
++
++ if (t->vdoa_dma.vaddr)
++ dma_free_coherent(t->dev,
++ t->vdoa_dma.size,
++ t->vdoa_dma.vaddr,
++ t->vdoa_dma.paddr);
++
++ if (only_ic(t->set.mode)) {
++ ret = ipu_disable_channel(ipu, t->set.ic_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_p_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic_p",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_n_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic_n",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ }
++ } else if (only_rot(t->set.mode)) {
++ ret = ipu_disable_channel(ipu, t->set.rot_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_rot",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ ret = ipu_unlink_channels(ipu, t->set.ic_chan, t->set.rot_chan);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_unlink_ch",
++ STATE_UNLINK_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.rot_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch ic_and_rot-rot",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.ic_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch ic_and_rot-ic",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_p_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch icrot-ic-p",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_n_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch icrot-ic-n",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ }
++ }
++
++ if (only_ic(t->set.mode))
++ uninit_ic(ipu, t);
++ else if (only_rot(t->set.mode))
++ uninit_rot(ipu, t);
++ else if (ic_and_rot(t->set.mode)) {
++ uninit_ic(ipu, t);
++ uninit_rot(ipu, t);
++ }
++
++ t->state = STATE_OK;
++ CHECK_PERF(&t->ts_rel);
++ return;
++}
++
++static void do_task_vdoa_only(struct ipu_task_entry *t)
++{
++ int ret;
++
++ ret = init_tiled_ch_bufs(NULL, t);
++ CHECK_RETCODE(ret < 0, "do_vdoa_only", STATE_ERR, out, ret);
++ ret = vdoa_start(t->vdoa_handle, VDOA_DEF_TIMEOUT_MS);
++ vdoa_stop(t->vdoa_handle);
++ CHECK_RETCODE(ret < 0, "vdoa_wait4complete, do_vdoa_only",
++ STATE_VDOA_IRQ_TIMEOUT, out, ret);
++
++ t->state = STATE_OK;
++out:
++ return;
++}
++
++static void do_task(struct ipu_task_entry *t)
++{
++ int r_size;
++ int irq;
++ int ret;
++ uint32_t busy;
++ struct ipu_soc *ipu = t->ipu;
++
++ CHECK_PERF(&t->ts_dotask);
++
++ if (!ipu) {
++ t->state = STATE_NO_IPU;
++ return;
++ }
++
++ init_completion(&t->irq_comp);
++ dev_dbg(ipu->dev, "[0x%p]Do task no:0x%x: id %d\n", (void *)t,
++ t->task_no, t->task_id);
++ dump_task_info(t);
++
++ if (t->set.task & IC_PP) {
++ t->set.ic_chan = MEM_PP_MEM;
++ dev_dbg(ipu->dev, "[0x%p]ic channel MEM_PP_MEM\n", (void *)t);
++ } else if (t->set.task & IC_VF) {
++ t->set.ic_chan = MEM_PRP_VF_MEM;
++ dev_dbg(ipu->dev, "[0x%p]ic channel MEM_PRP_VF_MEM\n", (void *)t);
++ } else if (t->set.task & VDI_VF) {
++ if (t->set.mode & VDOA_BAND_MODE) {
++ t->set.ic_chan = MEM_VDI_MEM;
++ if (deinterlace_3_field(t)) {
++ t->set.vdi_ic_p_chan = MEM_VDI_MEM_P;
++ t->set.vdi_ic_n_chan = MEM_VDI_MEM_N;
++ }
++ dev_dbg(ipu->dev, "[0x%p]ic ch MEM_VDI_MEM\n",
++ (void *)t);
++ } else {
++ t->set.ic_chan = MEM_VDI_PRP_VF_MEM;
++ if (deinterlace_3_field(t)) {
++ t->set.vdi_ic_p_chan = MEM_VDI_PRP_VF_MEM_P;
++ t->set.vdi_ic_n_chan = MEM_VDI_PRP_VF_MEM_N;
++ }
++ dev_dbg(ipu->dev,
++ "[0x%p]ic ch MEM_VDI_PRP_VF_MEM\n", t);
++ }
++ }
++
++ if (t->set.task & ROT_PP) {
++ t->set.rot_chan = MEM_ROT_PP_MEM;
++ dev_dbg(ipu->dev, "[0x%p]rot channel MEM_ROT_PP_MEM\n", (void *)t);
++ } else if (t->set.task & ROT_VF) {
++ t->set.rot_chan = MEM_ROT_VF_MEM;
++ dev_dbg(ipu->dev, "[0x%p]rot channel MEM_ROT_VF_MEM\n", (void *)t);
++ }
++
++ if (t->task_id == IPU_TASK_ID_VF)
++ busy = ic_vf_pp_is_busy(ipu, true);
++ else if (t->task_id == IPU_TASK_ID_PP)
++ busy = ic_vf_pp_is_busy(ipu, false);
++ else {
++ dev_err(ipu->dev, "ERR[no:0x%x]ipu task_id:%d invalid!\n",
++ t->task_no, t->task_id);
++ return;
++ }
++ if (busy) {
++ dev_err(ipu->dev, "ERR[0x%p-no:0x%x]ipu task_id:%d busy!\n",
++ (void *)t, t->task_no, t->task_id);
++ t->state = STATE_IPU_BUSY;
++ return;
++ }
++
++ irq = get_irq(t);
++ if (irq < 0) {
++ t->state = STATE_NO_IRQ;
++ return;
++ }
++ t->irq = irq;
++
++ /* channel setup */
++ if (only_ic(t->set.mode)) {
++ dev_dbg(t->dev, "[0x%p]only ic mode\n", (void *)t);
++ ret = init_ic(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_ic only_ic",
++ t->state, chan_setup, ret);
++ } else if (only_rot(t->set.mode)) {
++ dev_dbg(t->dev, "[0x%p]only rot mode\n", (void *)t);
++ ret = init_rot(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_rot only_rot",
++ t->state, chan_setup, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ int rot_idx = (t->task_id == IPU_TASK_ID_VF) ? 0 : 1;
++
++ dev_dbg(t->dev, "[0x%p]ic + rot mode\n", (void *)t);
++ t->set.r_fmt = t->output.format;
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ t->set.r_width = t->output.crop.h;
++ t->set.r_height = t->output.crop.w;
++ } else {
++ t->set.r_width = t->output.crop.w;
++ t->set.r_height = t->output.crop.h;
++ }
++ t->set.r_stride = t->set.r_width *
++ bytes_per_pixel(t->set.r_fmt);
++ r_size = PAGE_ALIGN(t->set.r_width * t->set.r_height
++ * fmt_to_bpp(t->set.r_fmt)/8);
++
++ if (r_size > ipu->rot_dma[rot_idx].size) {
++ dev_dbg(t->dev, "[0x%p]realloc rot buffer\n", (void *)t);
++
++ if (ipu->rot_dma[rot_idx].vaddr)
++ dma_free_coherent(t->dev,
++ ipu->rot_dma[rot_idx].size,
++ ipu->rot_dma[rot_idx].vaddr,
++ ipu->rot_dma[rot_idx].paddr);
++
++ ipu->rot_dma[rot_idx].size = r_size;
++ ipu->rot_dma[rot_idx].vaddr = dma_alloc_coherent(t->dev,
++ r_size,
++ &ipu->rot_dma[rot_idx].paddr,
++ GFP_DMA | GFP_KERNEL);
++ CHECK_RETCODE(ipu->rot_dma[rot_idx].vaddr == NULL,
++ "ic_and_rot", STATE_SYS_NO_MEM,
++ chan_setup, -ENOMEM);
++ }
++ t->set.r_paddr = ipu->rot_dma[rot_idx].paddr;
++
++ dev_dbg(t->dev, "[0x%p]rotation:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->set.r_fmt);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->set.r_width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->set.r_height);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->set.r_paddr);
++ dev_dbg(t->dev, "[0x%p]\trstride = %d\n", (void *)t, t->set.r_stride);
++
++ ret = init_ic(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_ic ic_and_rot",
++ t->state, chan_setup, ret);
++ ret = init_rot(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_rot ic_and_rot",
++ t->state, chan_setup, ret);
++ ret = ipu_link_channels(ipu, t->set.ic_chan,
++ t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_link_ch ic_and_rot",
++ STATE_LINK_CHAN_FAIL, chan_setup, ret);
++ } else {
++ dev_err(t->dev, "ERR [0x%p]do task: should not be here\n", t);
++ t->state = STATE_ERR;
++ return;
++ }
++
++ ret = ipu_request_irq(ipu, irq, task_irq_handler, 0, NULL, t);
++ CHECK_RETCODE(ret < 0, "ipu_req_irq",
++ STATE_IRQ_FAIL, chan_setup, ret);
++
++ /* enable/start channel */
++ if (only_ic(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_p_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic_p",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_n_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic_n",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ }
++
++ ret = ipu_select_buffer(ipu, t->set.ic_chan, IPU_OUTPUT_BUFFER,
++ 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay_en) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_g",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_a",
++ STATE_SEL_BUF_FAIL, chan_buf,
++ ret);
++ }
++ }
++ if (!(t->set.mode & VDOA_BAND_MODE)) {
++ if (deinterlace_3_field(t))
++ ipu_select_multi_vdi_buffer(ipu, 0);
++ else {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ }
++ }
++ } else if (only_rot(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_rot",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_rot_o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_rot_i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-rot",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-ic",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_p_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-p",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_n_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-n",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ }
++
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-rot-o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay_en) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-g",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf icrot-ic-a",
++ STATE_SEL_BUF_FAIL,
++ chan_buf, ret);
++ }
++ }
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (deinterlace_3_field(t))
++ ipu_select_multi_vdi_buffer(ipu, 0);
++ else {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ }
++ }
++
++ if (need_split(t))
++ t->state = STATE_IN_PROGRESS;
++
++ if (t->set.mode & VDOA_BAND_MODE) {
++ ret = vdoa_start(t->vdoa_handle, VDOA_DEF_TIMEOUT_MS);
++ CHECK_RETCODE(ret < 0, "vdoa_wait4complete, do_vdoa_band",
++ STATE_VDOA_IRQ_TIMEOUT, chan_rel, ret);
++ }
++
++ CHECK_PERF(&t->ts_waitirq);
++ ret = wait_for_completion_timeout(&t->irq_comp,
++ msecs_to_jiffies(t->timeout - DEF_DELAY_MS));
++ CHECK_PERF(&t->ts_wakeup);
++ CHECK_RETCODE(ret == 0, "wait_for_comp_timeout",
++ STATE_IRQ_TIMEOUT, chan_rel, ret);
++ dev_dbg(t->dev, "[0x%p] no-0x%x ipu irq done!", t, t->task_no);
++
++chan_rel:
++chan_buf:
++chan_en:
++chan_setup:
++ if (t->set.mode & VDOA_BAND_MODE)
++ vdoa_stop(t->vdoa_handle);
++ do_task_release(t, t->state >= STATE_ERR);
++ return;
++}
++
++static void do_task_vdoa_vdi(struct ipu_task_entry *t)
++{
++ int i;
++ int ret;
++ u32 stripe_width;
++
++ /* FIXME: crop mode not support now */
++ stripe_width = t->input.width >> 1;
++ t->input.crop.pos.x = 0;
++ t->input.crop.pos.y = 0;
++ t->input.crop.w = stripe_width;
++ t->input.crop.h = t->input.height;
++ t->output.crop.w = stripe_width;
++ t->output.crop.h = t->input.height;
++
++ for (i = 0; i < 2; i++) {
++ t->input.crop.pos.x = t->input.crop.pos.x + i * stripe_width;
++ t->output.crop.pos.x = t->output.crop.pos.x + i * stripe_width;
++ /* check input */
++ ret = set_crop(&t->input.crop, t->input.width, t->input.height,
++ t->input.format);
++ if (ret < 0) {
++ ret = STATE_ERR;
++ goto done;
++ } else
++ update_offset(t->input.format,
++ t->input.width, t->input.height,
++ t->input.crop.pos.x,
++ t->input.crop.pos.y,
++ &t->set.i_off, &t->set.i_uoff,
++ &t->set.i_voff, &t->set.istride);
++ dev_dbg(t->dev, "i_off:0x%x, i_uoff:0x%x, istride:%d.\n",
++ t->set.i_off, t->set.i_uoff, t->set.istride);
++ /* check output */
++ ret = set_crop(&t->output.crop, t->input.width,
++ t->output.height, t->output.format);
++ if (ret < 0) {
++ ret = STATE_ERR;
++ goto done;
++ } else
++ update_offset(t->output.format,
++ t->output.width, t->output.height,
++ t->output.crop.pos.x,
++ t->output.crop.pos.y,
++ &t->set.o_off, &t->set.o_uoff,
++ &t->set.o_voff, &t->set.ostride);
++
++ dev_dbg(t->dev, "o_off:0x%x, o_uoff:0x%x, ostride:%d.\n",
++ t->set.o_off, t->set.o_uoff, t->set.ostride);
++
++ do_task(t);
++ }
++
++ return;
++done:
++ dev_err(t->dev, "ERR %s set_crop.\n", __func__);
++ t->state = ret;
++ return;
++}
++
++static void get_res_do_task(struct ipu_task_entry *t)
++{
++ uint32_t found;
++ uint32_t split_child;
++ struct mutex *lock;
++
++ found = get_vdoa_ipu_res(t);
++ if (!found) {
++ dev_err(t->dev, "ERR:[0x%p] no-0x%x can not get res\n",
++ t, t->task_no);
++ return;
++ } else {
++ if (t->set.task & VDOA_ONLY)
++ do_task_vdoa_only(t);
++ else if ((IPU_PIX_FMT_TILED_NV12F == t->input.format) &&
++ (t->set.mode & VDOA_BAND_MODE) &&
++ (t->input.crop.w > soc_max_vdi_in_width()))
++ do_task_vdoa_vdi(t);
++ else
++ do_task(t);
++ put_vdoa_ipu_res(t, 0);
++ }
++ if (t->state != STATE_OK) {
++ dev_err(t->dev, "ERR:[0x%p] no-0x%x state: %s\n",
++ t, t->task_no, state_msg[t->state].msg);
++ }
++
++ split_child = need_split(t) && t->parent;
++ if (split_child) {
++ lock = &t->parent->split_lock;
++ mutex_lock(lock);
++ t->split_done = 1;
++ mutex_unlock(lock);
++ wake_up(&t->parent->split_waitq);
++ }
++
++ return;
++}
++
++static void wait_split_task_complete(struct ipu_task_entry *parent,
++ struct ipu_split_task *sp_task, uint32_t size)
++{
++ struct ipu_task_entry *tsk = NULL;
++ int ret = 0, rc;
++ int j, idx = -1;
++ unsigned long flags;
++ struct mutex *lock = &parent->split_lock;
++ int k, busy_vf, busy_pp;
++ struct ipu_soc *ipu;
++ DECLARE_PERF_VAR;
++
++ for (j = 0; j < size; j++) {
++ rc = wait_event_timeout(
++ parent->split_waitq,
++ sp_task_check_done(sp_task, parent, size, &idx),
++ msecs_to_jiffies(parent->timeout - DEF_DELAY_MS));
++ if (!rc) {
++ dev_err(parent->dev,
++ "ERR:[0x%p] no-0x%x, split_task timeout,j:%d,"
++ "size:%d.\n",
++ parent, parent->task_no, j, size);
++ ret = -ETIMEDOUT;
++ goto out;
++ } else {
++ if (idx < 0) {
++ dev_err(parent->dev,
++ "ERR:[0x%p] no-0x%x, invalid task idx:%d\n",
++ parent, parent->task_no, idx);
++ continue;
++ }
++ tsk = sp_task[idx].child_task;
++ mutex_lock(lock);
++ if (!tsk->split_done || !tsk->ipu)
++ dev_err(tsk->dev,
++ "ERR:no-0x%x,split not done:%d/null ipu:0x%p\n",
++ tsk->task_no, tsk->split_done, tsk->ipu);
++ tsk->split_done = 0;
++ mutex_unlock(lock);
++
++ dev_dbg(tsk->dev,
++ "[0x%p] no-0x%x sp_tsk[%d] done,state:%d.\n",
++ tsk, tsk->task_no, idx, tsk->state);
++ #ifdef DBG_IPU_PERF
++ CHECK_PERF(&tsk->ts_rel);
++ PRINT_TASK_STATISTICS;
++ #endif
++ }
++ }
++
++out:
++ if (ret == -ETIMEDOUT) {
++ /* debug */
++ for (k = 0; k < max_ipu_no; k++) {
++ ipu = ipu_get_soc(k);
++ if (IS_ERR(ipu)) {
++ dev_err(parent->dev, "no:0x%x, null ipu:%d\n",
++ parent->task_no, k);
++ } else {
++ busy_vf = ic_vf_pp_is_busy(ipu, true);
++ busy_pp = ic_vf_pp_is_busy(ipu, false);
++ dev_err(parent->dev,
++ "ERR:ipu[%d] busy_vf:%d, busy_pp:%d.\n",
++ k, busy_vf, busy_pp);
++ }
++ }
++ for (k = 0; k < size; k++) {
++ tsk = sp_task[k].child_task;
++ if (!tsk)
++ continue;
++ dev_err(parent->dev,
++ "ERR: sp_task[%d][0x%p] no-0x%x done:%d,"
++ "state:%s,on_list:%d, ipu:0x%p,timeout!\n",
++ k, tsk, tsk->task_no, tsk->split_done,
++ state_msg[tsk->state].msg, tsk->task_in_list,
++ tsk->ipu);
++ }
++ }
++
++ for (j = 0; j < size; j++) {
++ tsk = sp_task[j].child_task;
++ if (!tsk)
++ continue;
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ dev_dbg(tsk->dev,
++ "[0x%p] no-0x%x,id:%d sp_tsk timeout list_del.\n",
++ tsk, tsk->task_no, tsk->task_id);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++ if (!tsk->ipu)
++ continue;
++ if (tsk->state != STATE_OK) {
++ dev_err(tsk->dev,
++ "ERR:[0x%p] no-0x%x,id:%d, sp_tsk state: %s\n",
++ tsk, tsk->task_no, tsk->task_id,
++ state_msg[tsk->state].msg);
++ }
++ kref_put(&tsk->refcount, task_mem_free);
++ }
++
++ kfree(parent->vditmpbuf[0]);
++ kfree(parent->vditmpbuf[1]);
++
++ if (ret < 0)
++ parent->state = STATE_TIMEOUT;
++ else
++ parent->state = STATE_OK;
++ return;
++}
++
++static inline int find_task(struct ipu_task_entry **t, int thread_id)
++{
++ int found;
++ unsigned long flags;
++ struct ipu_task_entry *tsk;
++ struct list_head *task_list = &ipu_task_list;
++
++ *t = NULL;
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ found = !list_empty(task_list);
++ if (found) {
++ tsk = list_first_entry(task_list, struct ipu_task_entry, node);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ *t = tsk;
++ kref_get(&tsk->refcount);
++ dev_dbg(tsk->dev,
++ "thread_id:%d,[0x%p] task_no:0x%x,mode:0x%x list_del\n",
++ thread_id, tsk, tsk->task_no, tsk->set.mode);
++ } else
++ dev_err(tsk->dev,
++ "thread_id:%d,task_no:0x%x,mode:0x%x not on list_del\n",
++ thread_id, tsk->task_no, tsk->set.mode);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++
++ return found;
++}
++
++static int ipu_task_thread(void *argv)
++{
++ struct ipu_task_entry *tsk;
++ struct ipu_task_entry *sp_tsk0;
++ struct ipu_split_task sp_task[4];
++ /* priority lower than irq_thread */
++ const struct sched_param param = {
++ .sched_priority = MAX_USER_RT_PRIO/2 - 1,
++ };
++ int ret;
++ int curr_thread_id;
++ uint32_t size;
++ unsigned long flags;
++ unsigned int cpu;
++ struct cpumask cpu_mask;
++ struct ipu_thread_data *data = (struct ipu_thread_data *)argv;
++
++ thread_id++;
++ curr_thread_id = thread_id;
++ sched_setscheduler(current, SCHED_FIFO, &param);
++
++ if (!data->is_vdoa) {
++ cpu = cpumask_first(cpu_online_mask);
++ cpumask_set_cpu(cpu, &cpu_mask);
++ ret = sched_setaffinity(data->ipu->thread[data->id]->pid,
++ &cpu_mask);
++ if (ret < 0) {
++ pr_err("%s: sched_setaffinity fail:%d.\n", __func__, ret);
++ }
++ pr_debug("%s: sched_setaffinity cpu:%d.\n", __func__, cpu);
++ }
++
++ while (!kthread_should_stop()) {
++ int split_fail = 0;
++ int split_parent;
++ int split_child;
++
++ wait_event_interruptible(thread_waitq, find_task(&tsk, curr_thread_id));
++
++ if (!tsk) {
++ pr_err("thread:%d can not find task.\n",
++ curr_thread_id);
++ continue;
++ }
++
++ /* note: other threads run split child task */
++ split_parent = need_split(tsk) && !tsk->parent;
++ split_child = need_split(tsk) && tsk->parent;
++ if (split_parent) {
++ if ((tsk->set.split_mode == RL_SPLIT) ||
++ (tsk->set.split_mode == UD_SPLIT))
++ size = 2;
++ else
++ size = 4;
++ ret = queue_split_task(tsk, sp_task, size);
++ if (ret < 0) {
++ split_fail = 1;
++ } else {
++ struct list_head *pos;
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++
++ sp_tsk0 = list_first_entry(&tsk->split_list,
++ struct ipu_task_entry, node);
++ list_del(&sp_tsk0->node);
++
++ list_for_each(pos, &tsk->split_list) {
++ struct ipu_task_entry *tmp;
++
++ tmp = list_entry(pos,
++ struct ipu_task_entry, node);
++ tmp->task_in_list = 1;
++ dev_dbg(tmp->dev,
++ "[0x%p] no-0x%x,id:%d sp_tsk "
++ "add_to_list.\n", tmp,
++ tmp->task_no, tmp->task_id);
++ }
++ /* add to global list */
++ list_splice(&tsk->split_list, &ipu_task_list);
++
++ spin_unlock_irqrestore(&ipu_task_list_lock,
++ flags);
++ /* let the parent thread do the first sp_task */
++ /* FIXME: ensure the correct sequence for split
++ 4size: 5/6->9/a*/
++ if (!sp_tsk0)
++ dev_err(tsk->dev,
++ "ERR: no-0x%x,can not get split_tsk0\n",
++ tsk->task_no);
++ wake_up_interruptible(&thread_waitq);
++ get_res_do_task(sp_tsk0);
++ dev_dbg(sp_tsk0->dev,
++ "thread:%d complete tsk no:0x%x.\n",
++ curr_thread_id, sp_tsk0->task_no);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0) {
++ wake_up(&res_waitq);
++ dev_dbg(sp_tsk0->dev,
++ "sp_tsk0 sche thread:%d no:0x%x,"
++ "req_cnt:%d\n", curr_thread_id,
++ sp_tsk0->task_no, ret);
++ /* For other threads to get_res */
++ schedule();
++ }
++ }
++ } else
++ get_res_do_task(tsk);
++
++ /* wait for all 4 sp_task finished here or timeout
++ and then release all resources */
++ if (split_parent && !split_fail)
++ wait_split_task_complete(tsk, sp_task, size);
++
++ if (!split_child) {
++ atomic_inc(&tsk->done);
++ wake_up(&tsk->task_waitq);
++ }
++
++ dev_dbg(tsk->dev, "thread:%d complete tsk no:0x%x-[0x%p].\n",
++ curr_thread_id, tsk->task_no, tsk);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0) {
++ wake_up(&res_waitq);
++ dev_dbg(tsk->dev, "sche thread:%d no:0x%x,req_cnt:%d\n",
++ curr_thread_id, tsk->task_no, ret);
++ /* note: give cpu to other threads to get_res */
++ schedule();
++ }
++
++ kref_put(&tsk->refcount, task_mem_free);
++ }
++
++ pr_info("ERR %s exit.\n", __func__);
++ return 0;
++}
++
++int ipu_check_task(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++ int ret = 0;
++
++ tsk = create_task_entry(task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ ret = check_task(tsk);
++
++ task->input = tsk->input;
++ task->output = tsk->output;
++ task->overlay = tsk->overlay;
++ dump_task_info(tsk);
++
++ kref_put(&tsk->refcount, task_mem_free);
++ if (ret != 0)
++ pr_debug("%s ret:%d.\n", __func__, ret);
++ return ret;
++}
++EXPORT_SYMBOL_GPL(ipu_check_task);
++
++int ipu_queue_task(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++ unsigned long flags;
++ int ret;
++ u32 tmp_task_no;
++ DECLARE_PERF_VAR;
++
++ tsk = create_task_entry(task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ CHECK_PERF(&tsk->ts_queue);
++ ret = prepare_task(tsk);
++ if (ret < 0)
++ goto done;
++
++ if (need_split(tsk)) {
++ CHECK_PERF(&tsk->ts_dotask);
++ CHECK_PERF(&tsk->ts_waitirq);
++ CHECK_PERF(&tsk->ts_inirq);
++ CHECK_PERF(&tsk->ts_wakeup);
++ }
++
++ /* task_no last four bits for split task type*/
++ tmp_task_no = atomic_inc_return(&frame_no);
++ tsk->task_no = tmp_task_no << 4;
++ init_waitqueue_head(&tsk->task_waitq);
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ list_add_tail(&tsk->node, &ipu_task_list);
++ tsk->task_in_list = 1;
++ dev_dbg(tsk->dev, "[0x%p,no-0x%x] list_add_tail\n", tsk, tsk->task_no);
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++ wake_up_interruptible(&thread_waitq);
++
++ ret = wait_event_timeout(tsk->task_waitq, atomic_read(&tsk->done),
++ msecs_to_jiffies(tsk->timeout));
++ if (0 == ret) {
++ /* note: the timeout should larger than the internal timeout!*/
++ ret = -ETIMEDOUT;
++ dev_err(tsk->dev, "ERR: [0x%p] no-0x%x, timeout:%dms!\n",
++ tsk, tsk->task_no, tsk->timeout);
++ } else {
++ if (STATE_OK != tsk->state) {
++ dev_err(tsk->dev, "ERR: [0x%p] no-0x%x,state %d: %s\n",
++ tsk, tsk->task_no, tsk->state,
++ state_msg[tsk->state].msg);
++ ret = -ECANCELED;
++ } else
++ ret = 0;
++ }
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ dev_dbg(tsk->dev, "[0x%p] no:0x%x list_del\n",
++ tsk, tsk->task_no);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++
++#ifdef DBG_IPU_PERF
++ CHECK_PERF(&tsk->ts_rel);
++ PRINT_TASK_STATISTICS;
++ if (ts_frame_avg == 0)
++ ts_frame_avg = ts_frame.tv_nsec / NSEC_PER_USEC +
++ ts_frame.tv_sec * USEC_PER_SEC;
++ else
++ ts_frame_avg = (ts_frame_avg + ts_frame.tv_nsec / NSEC_PER_USEC
++ + ts_frame.tv_sec * USEC_PER_SEC)/2;
++ if (timespec_compare(&ts_frame, &ts_frame_max) > 0)
++ ts_frame_max = ts_frame;
++
++ atomic_inc(&frame_cnt);
++
++ if ((atomic_read(&frame_cnt) % 1000) == 0)
++ pr_debug("ipu_dev: max frame time:%ldus, avg frame time:%dus,"
++ "frame_cnt:%d\n", ts_frame_max.tv_nsec / NSEC_PER_USEC
++ + ts_frame_max.tv_sec * USEC_PER_SEC,
++ ts_frame_avg, atomic_read(&frame_cnt));
++#endif
++done:
++ if (ret < 0)
++ dev_err(tsk->dev, "ERR: no-0x%x,ipu_queue_task err:%d\n",
++ tsk->task_no, ret);
++
++ kref_put(&tsk->refcount, task_mem_free);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(ipu_queue_task);
++
++static int mxc_ipu_open(struct inode *inode, struct file *file)
++{
++ file->private_data = (void *)atomic_inc_return(&file_index);
++ return 0;
++}
++
++static long mxc_ipu_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int __user *argp = (void __user *)arg;
++ int ret = 0;
++
++ switch (cmd) {
++ case IPU_CHECK_TASK:
++ {
++ struct ipu_task task;
++
++ if (copy_from_user
++ (&task, (struct ipu_task *) arg,
++ sizeof(struct ipu_task)))
++ return -EFAULT;
++ ret = ipu_check_task(&task);
++ if (copy_to_user((struct ipu_task *) arg,
++ &task, sizeof(struct ipu_task)))
++ return -EFAULT;
++ break;
++ }
++ case IPU_QUEUE_TASK:
++ {
++ struct ipu_task task;
++
++ if (copy_from_user
++ (&task, (struct ipu_task *) arg,
++ sizeof(struct ipu_task)))
++ return -EFAULT;
++ ret = ipu_queue_task(&task);
++ break;
++ }
++ case IPU_ALLOC:
++ {
++ int size;
++ struct ipu_alloc_list *mem;
++
++ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
++ if (mem == NULL)
++ return -ENOMEM;
++
++ if (get_user(size, argp))
++ return -EFAULT;
++
++ mem->size = PAGE_ALIGN(size);
++
++ mem->cpu_addr = dma_alloc_coherent(ipu_dev, size,
++ &mem->phy_addr,
++ GFP_DMA | GFP_KERNEL);
++ if (mem->cpu_addr == NULL) {
++ kfree(mem);
++ return -ENOMEM;
++ }
++ mem->file_index = file->private_data;
++ mutex_lock(&ipu_alloc_lock);
++ list_add(&mem->list, &ipu_alloc_list);
++ mutex_unlock(&ipu_alloc_lock);
++
++ dev_dbg(ipu_dev, "allocated %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ if (put_user(mem->phy_addr, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case IPU_FREE:
++ {
++ unsigned long offset;
++ struct ipu_alloc_list *mem;
++
++ if (get_user(offset, argp))
++ return -EFAULT;
++
++ ret = -EINVAL;
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry(mem, &ipu_alloc_list, list) {
++ if (mem->phy_addr == offset) {
++ list_del(&mem->list);
++ dma_free_coherent(ipu_dev,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ kfree(mem);
++ ret = 0;
++ break;
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ if (0 == ret)
++ dev_dbg(ipu_dev, "free %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ break;
++ }
++ default:
++ break;
++ }
++ return ret;
++}
++
++static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ bool found = false;
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++ struct ipu_alloc_list *mem;
++
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry(mem, &ipu_alloc_list, list) {
++ if (offset == mem->phy_addr) {
++ found = true;
++ len = mem->size;
++ break;
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ if (!found)
++ return -EINVAL;
++
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start,
++ vma->vm_page_prot)) {
++ printk(KERN_ERR
++ "mmap failed!\n");
++ return -ENOBUFS;
++ }
++ return 0;
++}
++
++static int mxc_ipu_release(struct inode *inode, struct file *file)
++{
++ struct ipu_alloc_list *mem;
++ struct ipu_alloc_list *n;
++
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry_safe(mem, n, &ipu_alloc_list, list) {
++ if ((mem->cpu_addr != 0) &&
++ (file->private_data == mem->file_index)) {
++ list_del(&mem->list);
++ dma_free_coherent(ipu_dev,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ dev_dbg(ipu_dev, "rel-free %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++ kfree(mem);
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ atomic_dec(&file_index);
++
++ return 0;
++}
++
++static struct file_operations mxc_ipu_fops = {
++ .owner = THIS_MODULE,
++ .open = mxc_ipu_open,
++ .mmap = mxc_ipu_mmap,
++ .release = mxc_ipu_release,
++ .unlocked_ioctl = mxc_ipu_ioctl,
++};
++
++int register_ipu_device(struct ipu_soc *ipu, int id)
++{
++ int ret = 0;
++ static int idx;
++ static struct ipu_thread_data thread_data[5];
++
++ if (!major) {
++ major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops);
++ if (major < 0) {
++ printk(KERN_ERR "Unable to register mxc_ipu as a char device\n");
++ ret = major;
++ goto register_cdev_fail;
++ }
++
++ ipu_class = class_create(THIS_MODULE, "mxc_ipu");
++ if (IS_ERR(ipu_class)) {
++ ret = PTR_ERR(ipu_class);
++ goto ipu_class_fail;
++ }
++
++ ipu_dev = device_create(ipu_class, NULL, MKDEV(major, 0),
++ NULL, "mxc_ipu");
++ if (IS_ERR(ipu_dev)) {
++ ret = PTR_ERR(ipu_dev);
++ goto dev_create_fail;
++ }
++ ipu_dev->dma_mask = kmalloc(sizeof(*ipu_dev->dma_mask), GFP_KERNEL);
++ *ipu_dev->dma_mask = DMA_BIT_MASK(32);
++ ipu_dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ mutex_init(&ipu_ch_tbl.lock);
++ }
++ max_ipu_no = ++id;
++ ipu->rot_dma[0].size = 0;
++ ipu->rot_dma[1].size = 0;
++
++ thread_data[idx].ipu = ipu;
++ thread_data[idx].id = 0;
++ thread_data[idx].is_vdoa = 0;
++ ipu->thread[0] = kthread_run(ipu_task_thread, &thread_data[idx++],
++ "ipu%d_task", id);
++ if (IS_ERR(ipu->thread[0])) {
++ ret = PTR_ERR(ipu->thread[0]);
++ goto kthread0_fail;
++ }
++
++ thread_data[idx].ipu = ipu;
++ thread_data[idx].id = 1;
++ thread_data[idx].is_vdoa = 0;
++ ipu->thread[1] = kthread_run(ipu_task_thread, &thread_data[idx++],
++ "ipu%d_task", id);
++ if (IS_ERR(ipu->thread[1])) {
++ ret = PTR_ERR(ipu->thread[1]);
++ goto kthread1_fail;
++ }
++
++
++ return ret;
++
++kthread1_fail:
++ kthread_stop(ipu->thread[0]);
++kthread0_fail:
++ if (id == 0)
++ device_destroy(ipu_class, MKDEV(major, 0));
++dev_create_fail:
++ if (id == 0) {
++ class_destroy(ipu_class);
++ }
++ipu_class_fail:
++ if (id == 0)
++ unregister_chrdev(major, "mxc_ipu");
++register_cdev_fail:
++ return ret;
++}
++
++void unregister_ipu_device(struct ipu_soc *ipu, int id)
++{
++ int i;
++
++ kthread_stop(ipu->thread[0]);
++ kthread_stop(ipu->thread[1]);
++ for (i = 0; i < 2; i++) {
++ if (ipu->rot_dma[i].vaddr)
++ dma_free_coherent(ipu_dev,
++ ipu->rot_dma[i].size,
++ ipu->rot_dma[i].vaddr,
++ ipu->rot_dma[i].paddr);
++ }
++
++ if (major) {
++ device_destroy(ipu_class, MKDEV(major, 0));
++ class_destroy(ipu_class);
++ unregister_chrdev(major, "mxc_ipu");
++ major = 0;
++ }
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_disp.c linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_disp.c
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_disp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_disp.c 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,1962 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_disp.c
++ *
++ * @brief IPU display submodule API functions
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/errno.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include <asm/atomic.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++struct dp_csc_param_t {
++ int mode;
++ void *coeff;
++};
++
++#define SYNC_WAVE 0
++#define NULL_WAVE (-1)
++#define ASYNC_SER_WAVE 6
++
++/* DC display ID assignments */
++#define DC_DISP_ID_SYNC(di) (di)
++#define DC_DISP_ID_SERIAL 2
++#define DC_DISP_ID_ASYNC 3
++
++int dmfc_type_setup;
++
++void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first)
++{
++ u32 dmfc_wr_chan, dmfc_dp_chan;
++
++ if (first) {
++ if (dmfc_type_setup > dmfc_type)
++ dmfc_type = dmfc_type_setup;
++ else
++ dmfc_type_setup = dmfc_type;
++
++ /* disable DMFC-IC channel*/
++ ipu_dmfc_write(ipu, 0x2, DMFC_IC_CTRL);
++ } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
++ dev_dbg(ipu->dev, "DMFC high resolution has set, will not change\n");
++ return;
++ } else
++ dmfc_type_setup = dmfc_type;
++
++ if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
++ /* 1 - segment 0~3;
++ * 5B - segement 4, 5;
++ * 5F - segement 6, 7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000088;
++ dmfc_dp_chan = 0x00009694;
++ ipu->dmfc_size_28 = 256*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 128*4;
++ } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
++ /* 1 - segment 0, 1;
++ * 5B - segement 2~5;
++ * 5F - segement 6,7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000090;
++ dmfc_dp_chan = 0x0000968a;
++ ipu->dmfc_size_28 = 128*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 256*4;
++ } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
++ /* 5B - segement 0~3;
++ * 5F - segement 4~7;
++ * 1, 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n");
++ dmfc_wr_chan = 0x00000000;
++ dmfc_dp_chan = 0x00008c88;
++ ipu->dmfc_size_28 = 0;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 256*4;
++ ipu->dmfc_size_23 = 256*4;
++ } else {
++ /* 1 - segment 0, 1;
++ * 5B - segement 4, 5;
++ * 5F - segement 6, 7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000090;
++ dmfc_dp_chan = 0x00009694;
++ ipu->dmfc_size_28 = 128*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 128*4;
++ }
++ ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
++ ipu_dmfc_write(ipu, 0x202020F6, DMFC_WR_CHAN_DEF);
++ ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
++ /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
++ ipu_dmfc_write(ipu, 0x2020F6F6, DMFC_DP_CHAN_DEF);
++}
++
++static int __init dmfc_setup(char *options)
++{
++ get_option(&options, &dmfc_type_setup);
++ if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP)
++ dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP;
++ return 1;
++}
++__setup("dmfc=", dmfc_setup);
++
++void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width)
++{
++ u32 dmfc_gen1 = ipu_dmfc_read(ipu, DMFC_GENERAL1);
++
++ if (width >= HIGH_RESOLUTION_WIDTH) {
++ if (dma_chan == 23)
++ _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DP, 0);
++ else if (dma_chan == 28)
++ _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DC, 0);
++ }
++
++ if (dma_chan == 23) { /*5B*/
++ if (ipu->dmfc_size_23/width > 3)
++ dmfc_gen1 |= 1UL << 20;
++ else
++ dmfc_gen1 &= ~(1UL << 20);
++ } else if (dma_chan == 24) { /*6B*/
++ if (ipu->dmfc_size_24/width > 1)
++ dmfc_gen1 |= 1UL << 22;
++ else
++ dmfc_gen1 &= ~(1UL << 22);
++ } else if (dma_chan == 27) { /*5F*/
++ if (ipu->dmfc_size_27/width > 2)
++ dmfc_gen1 |= 1UL << 21;
++ else
++ dmfc_gen1 &= ~(1UL << 21);
++ } else if (dma_chan == 28) { /*1*/
++ if (ipu->dmfc_size_28/width > 2)
++ dmfc_gen1 |= 1UL << 16;
++ else
++ dmfc_gen1 &= ~(1UL << 16);
++ } else if (dma_chan == 29) { /*6F*/
++ if (ipu->dmfc_size_29/width > 1)
++ dmfc_gen1 |= 1UL << 23;
++ else
++ dmfc_gen1 &= ~(1UL << 23);
++ }
++
++ ipu_dmfc_write(ipu, dmfc_gen1, DMFC_GENERAL1);
++}
++
++void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size)
++{
++ u32 dmfc_wr_chan = ipu_dmfc_read(ipu, DMFC_WR_CHAN);
++ u32 dmfc_dp_chan = ipu_dmfc_read(ipu, DMFC_DP_CHAN);
++ int dmfc_bs = 0;
++
++ switch (burst_size) {
++ case 64:
++ dmfc_bs = 0x40;
++ break;
++ case 32:
++ case 20:
++ dmfc_bs = 0x80;
++ break;
++ case 16:
++ dmfc_bs = 0xc0;
++ break;
++ default:
++ dev_err(ipu->dev, "Unsupported burst size %d\n",
++ burst_size);
++ return;
++ }
++
++ if (dma_chan == 23) { /*5B*/
++ dmfc_dp_chan &= ~(0xc0);
++ dmfc_dp_chan |= dmfc_bs;
++ } else if (dma_chan == 27) { /*5F*/
++ dmfc_dp_chan &= ~(0xc000);
++ dmfc_dp_chan |= (dmfc_bs << 8);
++ } else if (dma_chan == 28) { /*1*/
++ dmfc_wr_chan &= ~(0xc0);
++ dmfc_wr_chan |= dmfc_bs;
++ }
++
++ ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
++ ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
++}
++
++static void _ipu_di_data_wave_config(struct ipu_soc *ipu,
++ int di, int wave_gen,
++ int access_size, int component_size)
++{
++ u32 reg;
++ reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
++ (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
++ ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
++}
++
++static void _ipu_di_data_pin_config(struct ipu_soc *ipu,
++ int di, int wave_gen, int di_pin, int set,
++ int up, int down)
++{
++ u32 reg;
++
++ reg = ipu_di_read(ipu, di, DI_DW_GEN(wave_gen));
++ reg &= ~(0x3 << (di_pin * 2));
++ reg |= set << (di_pin * 2);
++ ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
++
++ ipu_di_write(ipu, di, (down << 16) | up, DI_DW_SET(wave_gen, set));
++}
++
++static void _ipu_di_sync_config(struct ipu_soc *ipu,
++ int di, int wave_gen,
++ int run_count, int run_src,
++ int offset_count, int offset_src,
++ int repeat_count, int cnt_clr_src,
++ int cnt_polarity_gen_en,
++ int cnt_polarity_clr_src,
++ int cnt_polarity_trigger_src,
++ int cnt_up, int cnt_down)
++{
++ u32 reg;
++
++ if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) ||
++ (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
++ dev_err(ipu->dev, "DI%d counters out of range.\n", di);
++ return;
++ }
++
++ reg = (run_count << 19) | (++run_src << 16) |
++ (offset_count << 3) | ++offset_src;
++ ipu_di_write(ipu, di, reg, DI_SW_GEN0(wave_gen));
++ reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
++ (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
++ reg |= (cnt_down << 16) | cnt_up;
++ if (repeat_count == 0) {
++ /* Enable auto reload */
++ reg |= 0x10000000;
++ }
++ ipu_di_write(ipu, di, reg, DI_SW_GEN1(wave_gen));
++ reg = ipu_di_read(ipu, di, DI_STP_REP(wave_gen));
++ reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
++ reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
++ ipu_di_write(ipu, di, reg, DI_STP_REP(wave_gen));
++}
++
++static void _ipu_dc_map_link(struct ipu_soc *ipu,
++ int current_map,
++ int base_map_0, int buf_num_0,
++ int base_map_1, int buf_num_1,
++ int base_map_2, int buf_num_2)
++{
++ int ptr_0 = base_map_0 * 3 + buf_num_0;
++ int ptr_1 = base_map_1 * 3 + buf_num_1;
++ int ptr_2 = base_map_2 * 3 + buf_num_2;
++ int ptr;
++ u32 reg;
++ ptr = (ptr_2 << 10) + (ptr_1 << 5) + ptr_0;
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(current_map));
++ reg &= ~(0x1F << ((16 * (current_map & 0x1))));
++ reg |= ptr << ((16 * (current_map & 0x1)));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(current_map));
++}
++
++static void _ipu_dc_map_config(struct ipu_soc *ipu,
++ int map, int byte_num, int offset, int mask)
++{
++ int ptr = map * 3 + byte_num;
++ u32 reg;
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_VAL(ptr));
++ reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
++ reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_VAL(ptr));
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
++ reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
++ reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(map));
++}
++
++static void _ipu_dc_map_clear(struct ipu_soc *ipu, int map)
++{
++ u32 reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
++ ipu_dc_write(ipu, reg & ~(0xFFFF << (16 * (map & 0x1))),
++ DC_MAP_CONF_PTR(map));
++}
++
++static void _ipu_dc_write_tmpl(struct ipu_soc *ipu,
++ int word, u32 opcode, u32 operand, int map,
++ int wave, int glue, int sync, int stop)
++{
++ u32 reg;
++
++ if (opcode == WRG) {
++ reg = sync;
++ reg |= (glue << 4);
++ reg |= (++wave << 11);
++ reg |= ((operand & 0x1FFFF) << 15);
++ ipu_dc_tmpl_write(ipu, reg, word * 2);
++
++ reg = (operand >> 17);
++ reg |= opcode << 7;
++ reg |= (stop << 9);
++ ipu_dc_tmpl_write(ipu, reg, word * 2 + 1);
++ } else {
++ reg = sync;
++ reg |= (glue << 4);
++ reg |= (++wave << 11);
++ reg |= (++map << 15);
++ reg |= (operand << 20) & 0xFFF00000;
++ ipu_dc_tmpl_write(ipu, reg, word * 2);
++
++ reg = (operand >> 12);
++ reg |= opcode << 4;
++ reg |= (stop << 9);
++ ipu_dc_tmpl_write(ipu, reg, word * 2 + 1);
++ }
++}
++
++static void _ipu_dc_link_event(struct ipu_soc *ipu,
++ int chan, int event, int addr, int priority)
++{
++ u32 reg;
++ u32 address_shift;
++ if (event < DC_EVEN_UGDE0) {
++ reg = ipu_dc_read(ipu, DC_RL_CH(chan, event));
++ reg &= ~(0xFFFF << (16 * (event & 0x1)));
++ reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
++ ipu_dc_write(ipu, reg, DC_RL_CH(chan, event));
++ } else {
++ reg = ipu_dc_read(ipu, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
++ if ((event - DC_EVEN_UGDE0) & 0x1) {
++ reg &= ~(0x2FF << 16);
++ reg |= (addr << 16);
++ reg |= priority ? (2 << 24) : 0x0;
++ } else {
++ reg &= ~0xFC00FFFF;
++ if (priority)
++ chan = (chan >> 1) +
++ ((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
++ else
++ chan = 0x7;
++ address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
++ reg |= (addr << address_shift) | (priority << 3) | chan;
++ }
++ ipu_dc_write(ipu, reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
++ }
++}
++
++/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
++ U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
++ V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;*/
++static const int rgb2ycbcr_coeff[5][3] = {
++ {0x4D, 0x96, 0x1D},
++ {-0x2B, -0x55, 0x80},
++ {0x80, -0x6B, -0x15},
++ {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
++ {0x2, 0x2, 0x2}, /* S0, S1, S2 */
++};
++
++/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
++ G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
++ B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
++static const int ycbcr2rgb_coeff[5][3] = {
++ {0x095, 0x000, 0x0CC},
++ {0x095, 0x3CE, 0x398},
++ {0x095, 0x0FF, 0x000},
++ {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
++ {0x1, 0x1, 0x1}, /*S0,S1,S2 */
++};
++
++#define mask_a(a) ((u32)(a) & 0x3FF)
++#define mask_b(b) ((u32)(b) & 0x3FFF)
++
++/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
++static int _rgb_to_yuv(int n, int red, int green, int blue)
++{
++ int c;
++ c = red * rgb2ycbcr_coeff[n][0];
++ c += green * rgb2ycbcr_coeff[n][1];
++ c += blue * rgb2ycbcr_coeff[n][2];
++ c /= 16;
++ c += rgb2ycbcr_coeff[3][n] * 4;
++ c += 8;
++ c /= 16;
++ if (c < 0)
++ c = 0;
++ if (c > 255)
++ c = 255;
++ return c;
++}
++
++/*
++ * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
++ * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
++ */
++static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
++{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} },
++{{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} },
++{{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} },
++{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
++{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }
++};
++
++void __ipu_dp_csc_setup(struct ipu_soc *ipu,
++ int dp, struct dp_csc_param_t dp_csc_param,
++ bool srm_mode_update)
++{
++ u32 reg;
++ const int (*coeff)[5][3];
++
++ if (dp_csc_param.mode >= 0) {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
++ reg &= ~DP_COM_CONF_CSC_DEF_MASK;
++ reg |= dp_csc_param.mode;
++ ipu_dp_write(ipu, reg, DP_COM_CONF(dp));
++ }
++
++ coeff = dp_csc_param.coeff;
++
++ if (coeff) {
++ ipu_dp_write(ipu, mask_a((*coeff)[0][0]) |
++ (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[0][2]) |
++ (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[1][1]) |
++ (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[2][0]) |
++ (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[2][2]) |
++ (mask_b((*coeff)[3][0]) << 16) |
++ ((*coeff)[4][0] << 30), DP_CSC_0(dp));
++ ipu_dp_write(ipu, mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
++ (mask_b((*coeff)[3][2]) << 16) |
++ ((*coeff)[4][2] << 30), DP_CSC_1(dp));
++ }
++
++ if (srm_mode_update) {
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++}
++
++int _ipu_dp_init(struct ipu_soc *ipu,
++ ipu_channel_t channel, uint32_t in_pixel_fmt,
++ uint32_t out_pixel_fmt)
++{
++ int in_fmt, out_fmt;
++ int dp;
++ int partial = false;
++ uint32_t reg;
++
++ if (channel == MEM_FG_SYNC) {
++ dp = DP_SYNC;
++ partial = true;
++ } else if (channel == MEM_BG_SYNC) {
++ dp = DP_SYNC;
++ partial = false;
++ } else if (channel == MEM_BG_ASYNC0) {
++ dp = DP_ASYNC0;
++ partial = false;
++ } else {
++ return -EINVAL;
++ }
++
++ in_fmt = format_to_colorspace(in_pixel_fmt);
++ out_fmt = format_to_colorspace(out_pixel_fmt);
++
++ if (partial) {
++ if (in_fmt == RGB) {
++ if (out_fmt == RGB)
++ ipu->fg_csc_type = RGB2RGB;
++ else
++ ipu->fg_csc_type = RGB2YUV;
++ } else {
++ if (out_fmt == RGB)
++ ipu->fg_csc_type = YUV2RGB;
++ else
++ ipu->fg_csc_type = YUV2YUV;
++ }
++ } else {
++ if (in_fmt == RGB) {
++ if (out_fmt == RGB)
++ ipu->bg_csc_type = RGB2RGB;
++ else
++ ipu->bg_csc_type = RGB2YUV;
++ } else {
++ if (out_fmt == RGB)
++ ipu->bg_csc_type = YUV2RGB;
++ else
++ ipu->bg_csc_type = YUV2YUV;
++ }
++ }
++
++ /* Transform color key from rgb to yuv if CSC is enabled */
++ reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
++ if (ipu->color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
++ (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB)))) {
++ int red, green, blue;
++ int y, u, v;
++ uint32_t color_key = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL;
++
++ dev_dbg(ipu->dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key);
++
++ red = (color_key >> 16) & 0xFF;
++ green = (color_key >> 8) & 0xFF;
++ blue = color_key & 0xFF;
++
++ y = _rgb_to_yuv(0, red, green, blue);
++ u = _rgb_to_yuv(1, red, green, blue);
++ v = _rgb_to_yuv(2, red, green, blue);
++ color_key = (y << 16) | (u << 8) | v;
++
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
++ ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(dp));
++ ipu->color_key_4rgb = false;
++
++ dev_dbg(ipu->dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key);
++ }
++
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], true);
++
++ return 0;
++}
++
++void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int dp;
++ int partial = false;
++
++ if (channel == MEM_FG_SYNC) {
++ dp = DP_SYNC;
++ partial = true;
++ } else if (channel == MEM_BG_SYNC) {
++ dp = DP_SYNC;
++ partial = false;
++ } else if (channel == MEM_BG_ASYNC0) {
++ dp = DP_ASYNC0;
++ partial = false;
++ } else {
++ return;
++ }
++
++ if (partial)
++ ipu->fg_csc_type = CSC_NONE;
++ else
++ ipu->bg_csc_type = CSC_NONE;
++
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], false);
++}
++
++void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
++{
++ u32 reg = 0;
++
++ if ((dc_chan == 1) || (dc_chan == 5)) {
++ if (interlaced) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 1);
++ } else {
++ if (di) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 2, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 3, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 1, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
++ }
++ } else {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 5, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 6, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 12, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
++ }
++ }
++ }
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
++
++ reg = 0x2;
++ reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
++ reg |= di << 2;
++ if (interlaced)
++ reg |= DC_WR_CH_CONF_FIELD_MODE;
++ } else if ((dc_chan == 8) || (dc_chan == 9)) {
++ /* async channels */
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
++
++ reg = 0x3;
++ reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
++ }
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ ipu_dc_write(ipu, 0x00000000, DC_WR_CH_ADDR(dc_chan));
++
++ ipu_dc_write(ipu, 0x00000084, DC_GEN);
++}
++
++void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan)
++{
++ if ((dc_chan == 1) || (dc_chan == 5)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 0, 0);
++ } else if ((dc_chan == 8) || (dc_chan == 9)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
++ }
++}
++
++int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ if (channel == MEM_DC_SYNC)
++ return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_1) &
++ DC_WR_CH_CONF_FIELD_MODE);
++ else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
++ return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_5) &
++ DC_WR_CH_CONF_FIELD_MODE);
++ return 0;
++}
++
++void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int di;
++ uint32_t reg;
++ uint32_t dc_chan;
++ int irq = 0;
++
++ if (channel == MEM_FG_SYNC)
++ irq = IPU_IRQ_DP_SF_END;
++ else if (channel == MEM_DC_SYNC)
++ dc_chan = 1;
++ else if (channel == MEM_BG_SYNC)
++ dc_chan = 5;
++ else
++ return;
++
++ if (channel == MEM_FG_SYNC) {
++ /* Enable FG channel */
++ reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ return;
++ } else if (channel == MEM_BG_SYNC) {
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++
++ di = ipu->dc_di_assignment[dc_chan];
++
++ /* Make sure other DC sync channel is not assigned same DI */
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(6 - dc_chan));
++ if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
++ reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
++ reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
++ }
++
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ clk_prepare_enable(ipu->pixel_clk[di]);
++}
++
++static irqreturn_t dc_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_soc *ipu = dev_id;
++ struct completion *comp = &ipu->dc_comp;
++ uint32_t reg;
++ uint32_t dc_chan;
++
++ if (irq == IPU_IRQ_DC_FC_1)
++ dc_chan = 1;
++ else
++ dc_chan = 5;
++
++ if (!ipu->dc_swap) {
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ reg = ipu_cm_read(ipu, IPU_DISP_GEN);
++ if (ipu->dc_di_assignment[dc_chan])
++ reg &= ~DI1_COUNTER_RELEASE;
++ else
++ reg &= ~DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, reg, IPU_DISP_GEN);
++ }
++
++ complete(comp);
++ return IRQ_HANDLED;
++}
++
++void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap)
++{
++ int ret;
++ uint32_t reg;
++ uint32_t csc;
++ uint32_t dc_chan;
++ int irq = 0;
++ int timeout = 50;
++
++ ipu->dc_swap = swap;
++
++ if (channel == MEM_DC_SYNC) {
++ dc_chan = 1;
++ irq = IPU_IRQ_DC_FC_1;
++ } else if (channel == MEM_BG_SYNC) {
++ dc_chan = 5;
++ irq = IPU_IRQ_DP_SF_END;
++ } else if (channel == MEM_FG_SYNC) {
++ /* Disable FG channel */
++ dc_chan = 5;
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
++ csc = reg & DP_COM_CONF_CSC_DEF_MASK;
++ if (csc == DP_COM_CONF_CSC_DEF_FG)
++ reg &= ~DP_COM_CONF_CSC_DEF_MASK;
++
++ reg &= ~DP_COM_CONF_FG_EN;
++ ipu_dp_write(ipu, reg, DP_COM_CONF(DP_SYNC));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ if (ipu_is_channel_busy(ipu, MEM_BG_SYNC)) {
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
++ IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
++ while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
++ IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
++ msleep(2);
++ timeout -= 2;
++ if (timeout <= 0)
++ break;
++ }
++ }
++ return;
++ } else {
++ return;
++ }
++
++ init_completion(&ipu->dc_comp);
++ ret = ipu_request_irq(ipu, irq, dc_irq_handler, 0, NULL, ipu);
++ if (ret < 0) {
++ dev_err(ipu->dev, "DC irq %d in use\n", irq);
++ return;
++ }
++ ret = wait_for_completion_timeout(&ipu->dc_comp, msecs_to_jiffies(50));
++ ipu_free_irq(ipu, irq, ipu);
++ dev_dbg(ipu->dev, "DC stop timeout - %d * 10ms\n", 5 - ret);
++
++ if (ipu->dc_swap) {
++ /* Swap DC channel 1 and 5 settings, and disable old dc chan */
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
++ reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
++ reg ^= DC_WR_CH_CONF_PROG_DI_ID;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++ }
++}
++
++void _ipu_init_dc_mappings(struct ipu_soc *ipu)
++{
++ /* IPU_PIX_FMT_RGB24 */
++ _ipu_dc_map_clear(ipu, 0);
++ _ipu_dc_map_config(ipu, 0, 0, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 0, 1, 15, 0xFF);
++ _ipu_dc_map_config(ipu, 0, 2, 23, 0xFF);
++
++ /* IPU_PIX_FMT_RGB666 */
++ _ipu_dc_map_clear(ipu, 1);
++ _ipu_dc_map_config(ipu, 1, 0, 5, 0xFC);
++ _ipu_dc_map_config(ipu, 1, 1, 11, 0xFC);
++ _ipu_dc_map_config(ipu, 1, 2, 17, 0xFC);
++
++ /* IPU_PIX_FMT_YUV444 */
++ _ipu_dc_map_clear(ipu, 2);
++ _ipu_dc_map_config(ipu, 2, 0, 15, 0xFF);
++ _ipu_dc_map_config(ipu, 2, 1, 23, 0xFF);
++ _ipu_dc_map_config(ipu, 2, 2, 7, 0xFF);
++
++ /* IPU_PIX_FMT_RGB565 */
++ _ipu_dc_map_clear(ipu, 3);
++ _ipu_dc_map_config(ipu, 3, 0, 4, 0xF8);
++ _ipu_dc_map_config(ipu, 3, 1, 10, 0xFC);
++ _ipu_dc_map_config(ipu, 3, 2, 15, 0xF8);
++
++ /* IPU_PIX_FMT_LVDS666 */
++ _ipu_dc_map_clear(ipu, 4);
++ _ipu_dc_map_config(ipu, 4, 0, 5, 0xFC);
++ _ipu_dc_map_config(ipu, 4, 1, 13, 0xFC);
++ _ipu_dc_map_config(ipu, 4, 2, 21, 0xFC);
++
++ /* IPU_PIX_FMT_VYUY 16bit width */
++ _ipu_dc_map_clear(ipu, 5);
++ _ipu_dc_map_config(ipu, 5, 0, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 5, 1, 0, 0x0);
++ _ipu_dc_map_config(ipu, 5, 2, 15, 0xFF);
++ _ipu_dc_map_clear(ipu, 6);
++ _ipu_dc_map_config(ipu, 6, 0, 0, 0x0);
++ _ipu_dc_map_config(ipu, 6, 1, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 6, 2, 15, 0xFF);
++
++ /* IPU_PIX_FMT_UYUV 16bit width */
++ _ipu_dc_map_clear(ipu, 7);
++ _ipu_dc_map_link(ipu, 7, 6, 0, 6, 1, 6, 2);
++ _ipu_dc_map_clear(ipu, 8);
++ _ipu_dc_map_link(ipu, 8, 5, 0, 5, 1, 5, 2);
++
++ /* IPU_PIX_FMT_YUYV 16bit width */
++ _ipu_dc_map_clear(ipu, 9);
++ _ipu_dc_map_link(ipu, 9, 5, 2, 5, 1, 5, 0);
++ _ipu_dc_map_clear(ipu, 10);
++ _ipu_dc_map_link(ipu, 10, 5, 1, 5, 2, 5, 0);
++
++ /* IPU_PIX_FMT_YVYU 16bit width */
++ _ipu_dc_map_clear(ipu, 11);
++ _ipu_dc_map_link(ipu, 11, 5, 1, 5, 2, 5, 0);
++ _ipu_dc_map_clear(ipu, 12);
++ _ipu_dc_map_link(ipu, 12, 5, 2, 5, 1, 5, 0);
++
++ /* IPU_PIX_FMT_GBR24 */
++ /* IPU_PIX_FMT_VYU444 */
++ _ipu_dc_map_clear(ipu, 13);
++ _ipu_dc_map_link(ipu, 13, 0, 2, 0, 0, 0, 1);
++
++ /* IPU_PIX_FMT_BGR24 */
++ _ipu_dc_map_clear(ipu, 14);
++ _ipu_dc_map_link(ipu, 14, 0, 2, 0, 1, 0, 0);
++}
++
++int _ipu_pixfmt_to_map(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_RGB24:
++ return 0;
++ case IPU_PIX_FMT_RGB666:
++ return 1;
++ case IPU_PIX_FMT_YUV444:
++ return 2;
++ case IPU_PIX_FMT_RGB565:
++ return 3;
++ case IPU_PIX_FMT_LVDS666:
++ return 4;
++ case IPU_PIX_FMT_VYUY:
++ return 6;
++ case IPU_PIX_FMT_UYVY:
++ return 8;
++ case IPU_PIX_FMT_YUYV:
++ return 10;
++ case IPU_PIX_FMT_YVYU:
++ return 12;
++ case IPU_PIX_FMT_GBR24:
++ case IPU_PIX_FMT_VYU444:
++ return 13;
++ case IPU_PIX_FMT_BGR24:
++ return 14;
++ }
++
++ return -1;
++}
++
++/*!
++ * This function sets the colorspace for of dp.
++ * modes.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param param If it's not NULL, update the csc table
++ * with this parameter.
++ *
++ * @return N/A
++ */
++void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
++{
++ int dp;
++ struct dp_csc_param_t dp_csc_param;
++
++ if (channel == MEM_FG_SYNC)
++ dp = DP_SYNC;
++ else if (channel == MEM_BG_SYNC)
++ dp = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0)
++ dp = DP_ASYNC0;
++ else
++ return;
++
++ dp_csc_param.mode = -1;
++ dp_csc_param.coeff = param;
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_param, true);
++}
++
++void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
++{
++ _ipu_dp_set_csc_coefficients(ipu, channel, param);
++}
++EXPORT_SYMBOL(ipu_set_csc_coefficients);
++
++/*!
++ * This function is called to adapt synchronous LCD panel to IPU restriction.
++ *
++ */
++void adapt_panel_to_ipu_restricitions(struct ipu_soc *ipu, uint16_t *v_start_width,
++ uint16_t *v_sync_width,
++ uint16_t *v_end_width)
++{
++ if (*v_end_width < 2) {
++ uint16_t diff = 2 - *v_end_width;
++ if (*v_start_width >= diff) {
++ *v_end_width = 2;
++ *v_start_width = *v_start_width - diff;
++ } else if (*v_sync_width > diff) {
++ *v_end_width = 2;
++ *v_sync_width = *v_sync_width - diff;
++ } else
++ dev_err(ipu->dev, "WARNING: try to adapt timming, but failed\n");
++ dev_err(ipu->dev, "WARNING: adapt panel end blank lines\n");
++ }
++}
++
++/*!
++ * This function is called to initialize a synchronous LCD panel.
++ *
++ * @param ipu ipu handler
++ * @param disp The DI the panel is attached to.
++ *
++ * @param pixel_clk Desired pixel clock frequency in Hz.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width The width of panel in pixels.
++ *
++ * @param height The height of panel in pixels.
++ *
++ * @param hStartWidth The number of pixel clocks between the HSYNC
++ * signal pulse and the start of valid data.
++ *
++ * @param hSyncWidth The width of the HSYNC signal in units of pixel
++ * clocks.
++ *
++ * @param hEndWidth The number of pixel clocks between the end of
++ * valid data and the HSYNC signal for next line.
++ *
++ * @param vStartWidth The number of lines between the VSYNC
++ * signal pulse and the start of valid data.
++ *
++ * @param vSyncWidth The width of the VSYNC signal in units of lines
++ *
++ * @param vEndWidth The number of lines between the end of valid
++ * data and the VSYNC signal for next frame.
++ *
++ * @param sig Bitfield of signal polarities for LCD interface.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
++ uint16_t width, uint16_t height,
++ uint32_t pixel_fmt,
++ uint16_t h_start_width, uint16_t h_sync_width,
++ uint16_t h_end_width, uint16_t v_start_width,
++ uint16_t v_sync_width, uint16_t v_end_width,
++ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
++{
++ uint32_t field0_offset = 0;
++ uint32_t field1_offset;
++ uint32_t reg;
++ uint32_t di_gen, vsync_cnt;
++ uint32_t div, rounded_pixel_clk;
++ uint32_t h_total, v_total;
++ int map;
++ int ret;
++ struct clk *ldb_di0_clk, *ldb_di1_clk;
++ struct clk *di_parent;
++
++ dev_dbg(ipu->dev, "panel size = %d x %d\n", width, height);
++
++ if ((v_sync_width == 0) || (h_sync_width == 0))
++ return -EINVAL;
++
++ adapt_panel_to_ipu_restricitions(ipu, &v_start_width, &v_sync_width, &v_end_width);
++ h_total = width + h_sync_width + h_start_width + h_end_width;
++ v_total = height + v_sync_width + v_start_width + v_end_width;
++
++ /* Init clocking */
++ dev_dbg(ipu->dev, "pixel clk = %d\n", pixel_clk);
++
++ di_parent = clk_get_parent(ipu->di_clk_sel[disp]);
++ if (!di_parent) {
++ dev_err(ipu->dev, "get di clk parent fail\n");
++ return -EINVAL;
++ }
++ ldb_di0_clk = clk_get(ipu->dev, "ldb_di0");
++ if (IS_ERR(ldb_di0_clk)) {
++ dev_err(ipu->dev, "clk_get di0 failed");
++ return PTR_ERR(ldb_di0_clk);
++ }
++ ldb_di1_clk = clk_get(ipu->dev, "ldb_di1");
++ if (IS_ERR(ldb_di1_clk)) {
++ dev_err(ipu->dev, "clk_get di1 failed");
++ return PTR_ERR(ldb_di1_clk);
++ }
++
++ if (ldb_di0_clk == di_parent || ldb_di1_clk == di_parent) {
++ /* if di clk parent is tve/ldb, then keep it;*/
++ dev_dbg(ipu->dev, "use special clk parent\n");
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp], ipu->di_clk[disp]);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk error:%d\n", ret);
++ return ret;
++ }
++ clk_put(ldb_di0_clk);
++ clk_put(ldb_di1_clk);
++ } else {
++ /* try ipu clk first*/
++ dev_dbg(ipu->dev, "try ipu internal clk\n");
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk error:%d\n", ret);
++ return ret;
++ }
++ rounded_pixel_clk = clk_round_rate(ipu->pixel_clk[disp], pixel_clk);
++ dev_dbg(ipu->dev, "rounded pix clk:%d\n", rounded_pixel_clk);
++ /*
++ * we will only use 1/2 fraction for ipu clk,
++ * so if the clk rate is not fit, try ext clk.
++ */
++ if (!sig.int_clk &&
++ ((rounded_pixel_clk >= pixel_clk + pixel_clk/200) ||
++ (rounded_pixel_clk <= pixel_clk - pixel_clk/200))) {
++ dev_dbg(ipu->dev, "try ipu ext di clk\n");
++
++ rounded_pixel_clk =
++ clk_round_rate(ipu->di_clk[disp], pixel_clk);
++ ret = clk_set_rate(ipu->di_clk[disp],
++ rounded_pixel_clk);
++ if (ret) {
++ dev_err(ipu->dev,
++ "set di clk rate error:%d\n", ret);
++ return ret;
++ }
++ dev_dbg(ipu->dev, "di clk:%d\n", rounded_pixel_clk);
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp],
++ ipu->di_clk[disp]);
++ if (ret) {
++ dev_err(ipu->dev,
++ "set pixel clk parent error:%d\n", ret);
++ return ret;
++ }
++ }
++ }
++ rounded_pixel_clk = clk_round_rate(ipu->pixel_clk[disp], pixel_clk);
++ dev_dbg(ipu->dev, "round pixel clk:%d\n", rounded_pixel_clk);
++ ret = clk_set_rate(ipu->pixel_clk[disp], rounded_pixel_clk);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk rate error:%d\n", ret);
++ return ret;
++ }
++ msleep(5);
++ /* Get integer portion of divider */
++ div = clk_get_rate(clk_get_parent(ipu->pixel_clk_sel[disp])) / rounded_pixel_clk;
++ dev_dbg(ipu->dev, "div:%d\n", div);
++ if (!div) {
++ dev_err(ipu->dev, "invalid pixel clk div = 0\n");
++ return -EINVAL;
++ }
++
++
++ mutex_lock(&ipu->mutex_lock);
++
++ _ipu_di_data_wave_config(ipu, disp, SYNC_WAVE, div - 1, div - 1);
++ _ipu_di_data_pin_config(ipu, disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
++
++ map = _ipu_pixfmt_to_map(pixel_fmt);
++ if (map < 0) {
++ dev_dbg(ipu->dev, "IPU_DISP: No MAP\n");
++ mutex_unlock(&ipu->mutex_lock);
++ return -EINVAL;
++ }
++
++ /*clear DI*/
++ di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
++ di_gen &= (0x3 << 20);
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ if (sig.interlaced) {
++ if (g_ipu_hw_rev >= IPU_V3DEX) {
++ /* Setup internal HSYNC waveform */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 1, /* counter */
++ h_total/2 - 1, /* run count */
++ DI_SYNC_CLK, /* run_resolution */
++ 0, /* offset */
++ DI_SYNC_NONE, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Field 1 VSYNC waveform */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 2, /* counter */
++ h_total - 1, /* run count */
++ DI_SYNC_CLK, /* run_resolution */
++ 0, /* offset */
++ DI_SYNC_NONE, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 2*div /* COUNT DOWN */
++ );
++
++ /* Setup internal HSYNC waveform */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 3, /* counter */
++ v_total*2 - 1, /* run count */
++ DI_SYNC_INT_HSYNC, /* run_resolution */
++ 1, /* offset */
++ DI_SYNC_INT_HSYNC, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 2*div /* COUNT DOWN */
++ );
++
++ /* Active Field ? */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 4, /* counter */
++ v_total/2 - 1, /* run count */
++ DI_SYNC_HSYNC, /* run_resolution */
++ v_start_width, /* offset */
++ DI_SYNC_HSYNC, /* offset resolution */
++ 2, /* repeat count */
++ DI_SYNC_VSYNC, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Active Line */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 5, /* counter */
++ 0, /* run count */
++ DI_SYNC_HSYNC, /* run_resolution */
++ 0, /* offset */
++ DI_SYNC_NONE, /* offset resolution */
++ height/2, /* repeat count */
++ 4, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Field 0 VSYNC waveform */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 6, /* counter */
++ v_total - 1, /* run count */
++ DI_SYNC_HSYNC, /* run_resolution */
++ 0, /* offset */
++ DI_SYNC_NONE, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* DC VSYNC waveform */
++ vsync_cnt = 7;
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 7, /* counter */
++ v_total/2 - 1, /* run count */
++ DI_SYNC_HSYNC, /* run_resolution */
++ 9, /* offset */
++ DI_SYNC_HSYNC, /* offset resolution */
++ 2, /* repeat count */
++ DI_SYNC_VSYNC, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* active pixel waveform */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 8, /* counter */
++ 0, /* run count */
++ DI_SYNC_CLK, /* run_resolution */
++ h_start_width, /* offset */
++ DI_SYNC_CLK, /* offset resolution */
++ width, /* repeat count */
++ 5, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Second VSYNC */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ 9, /* counter */
++ v_total - 1, /* run count */
++ DI_SYNC_INT_HSYNC, /* run_resolution */
++ v_total/2, /* offset */
++ DI_SYNC_INT_HSYNC, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_HSYNC, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 2*div /* COUNT DOWN */
++ );
++
++ /* set gentime select and tag sel */
++ reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
++ reg &= 0x1FFFFFFF;
++ reg |= (3-1)<<29 | 0x00008000;
++ ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
++
++ ipu_di_write(ipu, disp, v_total / 2 - 1, DI_SCR_CONF);
++
++ /* set y_sel = 1 */
++ di_gen |= 0x10000000;
++ di_gen |= DI_GEN_POLARITY_5;
++ di_gen |= DI_GEN_POLARITY_8;
++ } else {
++ /* Setup internal HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ field1_offset = v_sync_width + v_start_width + height / 2 +
++ v_end_width;
++ if (sig.odd_field_first) {
++ field0_offset = field1_offset - 1;
++ field1_offset = 0;
++ }
++ v_total += v_start_width + v_end_width;
++
++ /* Field 1 VSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, 2, v_total - 1, 1,
++ field0_offset,
++ field0_offset ? 1 : DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
++
++ /* Setup internal HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, 3, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
++
++ /* Active Field ? */
++ _ipu_di_sync_config(ipu, disp, 4,
++ field0_offset ?
++ field0_offset : field1_offset - 2,
++ 1, v_start_width + v_sync_width, 1, 2, 2,
++ 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
++
++ /* Active Line */
++ _ipu_di_sync_config(ipu, disp, 5, 0, 1,
++ 0, DI_SYNC_NONE,
++ height / 2, 4, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* Field 0 VSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, 6, v_total - 1, 1,
++ 0, DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* DC VSYNC waveform */
++ vsync_cnt = 7;
++ _ipu_di_sync_config(ipu, disp, 7, 0, 1,
++ field1_offset,
++ field1_offset ? 1 : DI_SYNC_NONE,
++ 1, 2, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
++
++ /* active pixel waveform */
++ _ipu_di_sync_config(ipu, disp, 8, 0, DI_SYNC_CLK,
++ h_sync_width + h_start_width, DI_SYNC_CLK,
++ width, 5, 0, DI_SYNC_NONE, DI_SYNC_NONE,
++ 0, 0);
++
++ /* ??? */
++ _ipu_di_sync_config(ipu, disp, 9, v_total - 1, 2,
++ 0, DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 6, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
++ reg |= 0x8000;
++ ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
++
++ ipu_di_write(ipu, disp, v_sync_width + v_start_width +
++ v_end_width + height / 2 - 1, DI_SCR_CONF);
++ }
++
++ /* Init template microcode */
++ _ipu_dc_write_tmpl(ipu, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
++
++ if (sig.Hsync_pol)
++ di_gen |= DI_GEN_POLARITY_3;
++ if (sig.Vsync_pol)
++ di_gen |= DI_GEN_POLARITY_2;
++ } else {
++ /* Setup internal HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, 1, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* Setup external (delayed) HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1,
++ DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
++ DI_SYNC_CLK, 0, h_sync_width * 2);
++ /* Setup VSYNC waveform */
++ vsync_cnt = DI_SYNC_VSYNC;
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1,
++ DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, 1, DI_SYNC_NONE,
++ DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
++ ipu_di_write(ipu, disp, v_total - 1, DI_SCR_CONF);
++
++ /* Setup active data waveform to sync with DC */
++ _ipu_di_sync_config(ipu, disp, 4, 0, DI_SYNC_HSYNC,
++ v_sync_width + v_start_width, DI_SYNC_HSYNC, height,
++ DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++ _ipu_di_sync_config(ipu, disp, 5, 0, DI_SYNC_CLK,
++ h_sync_width + h_start_width, DI_SYNC_CLK,
++ width, 4, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
++ 0);
++
++ /* set VGA delayed hsync/vsync no matter VGA enabled */
++ if (disp) {
++ /* couter 7 for VGA delay HSYNC */
++ _ipu_di_sync_config(ipu, disp, 7,
++ h_total - 1, DI_SYNC_CLK,
++ 18, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE,
++ 1, DI_SYNC_NONE, DI_SYNC_CLK,
++ 0, h_sync_width * 2);
++
++ /* couter 8 for VGA delay VSYNC */
++ _ipu_di_sync_config(ipu, disp, 8,
++ v_total - 1, DI_SYNC_INT_HSYNC,
++ 1, DI_SYNC_INT_HSYNC,
++ 0, DI_SYNC_NONE,
++ 1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC,
++ 0, v_sync_width * 2);
++ }
++
++ /* reset all unused counters */
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(6));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(6));
++ if (!disp) {
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(7));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(7));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(7));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(8));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(8));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(8));
++ }
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(9));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(9));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(9));
++
++ reg = ipu_di_read(ipu, disp, DI_STP_REP(6));
++ reg &= 0x0000FFFF;
++ ipu_di_write(ipu, disp, reg, DI_STP_REP(6));
++
++ /* Init template microcode */
++ if (disp) {
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
++ _ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));
++ }
++ _ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
++ _ipu_dc_write_tmpl(ipu, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
++ _ipu_dc_write_tmpl(ipu, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
++ _ipu_dc_write_tmpl(ipu, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
++
++ } else {
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, 5, 1);
++ _ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp));
++ }
++ _ipu_dc_write_tmpl(ipu, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
++ _ipu_dc_write_tmpl(ipu, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
++ _ipu_dc_write_tmpl(ipu, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
++ _ipu_dc_write_tmpl(ipu, 12, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
++ }
++
++ if (sig.Hsync_pol) {
++ di_gen |= DI_GEN_POLARITY_2;
++ if (disp)
++ di_gen |= DI_GEN_POLARITY_7;
++ }
++ if (sig.Vsync_pol) {
++ di_gen |= DI_GEN_POLARITY_3;
++ if (disp)
++ di_gen |= DI_GEN_POLARITY_8;
++ }
++ }
++ /* changinc DISP_CLK polarity: it can be wrong for some applications */
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY))
++ di_gen |= 0x00020000;
++
++ if (!sig.clk_pol)
++ di_gen |= DI_GEN_POLARITY_DISP_CLK;
++
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ ipu_di_write(ipu, disp, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
++ 0x00000002, DI_SYNC_AS_GEN);
++ reg = ipu_di_read(ipu, disp, DI_POL);
++ reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
++ if (sig.enable_pol)
++ reg |= DI_POL_DRDY_POLARITY_15;
++ if (sig.data_pol)
++ reg |= DI_POL_DRDY_DATA_POLARITY;
++ ipu_di_write(ipu, disp, reg, DI_POL);
++
++ ipu_dc_write(ipu, width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_sync_panel);
++
++void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp)
++{
++ uint32_t reg;
++ uint32_t di_gen;
++
++ if ((disp != 0) || (disp != 1))
++ return;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
++ di_gen |= 0x3ff | DI_GEN_POLARITY_DISP_CLK;
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ reg = ipu_di_read(ipu, disp, DI_POL);
++ reg |= 0x3ffffff;
++ ipu_di_write(ipu, disp, reg, DI_POL);
++
++ mutex_unlock(&ipu->mutex_lock);
++}
++EXPORT_SYMBOL(ipu_uninit_sync_panel);
++
++int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
++ uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
++{
++ int map;
++ u32 ser_conf = 0;
++ u32 div;
++ u32 di_clk = clk_get_rate(ipu->ipu_clk);
++
++ /* round up cycle_time, then calcalate the divider using scaled math */
++ cycle_time += (1000000000UL / di_clk) - 1;
++ div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL);
++
++ map = _ipu_pixfmt_to_map(pixel_fmt);
++ if (map < 0)
++ return -EINVAL;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (type == IPU_PANEL_SERIAL) {
++ ipu_di_write(ipu, disp, (div << 24) | ((sig.ifc_width - 1) << 4),
++ DI_DW_GEN(ASYNC_SER_WAVE));
++
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_CS,
++ 0, 0, (div * 2) + 1);
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK,
++ 1, div, div * 2);
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_RS,
++ 2, 0, 0);
++
++ _ipu_dc_write_tmpl(ipu, 0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0, 1);
++
++ /* Configure DC for serial panel */
++ ipu_dc_write(ipu, 0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL));
++
++ if (sig.clk_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_CLK_POL;
++ if (sig.data_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_DATA_POL;
++ if (sig.rs_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_RS_POL;
++ if (sig.cs_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_CS_POL;
++ ipu_di_write(ipu, disp, ser_conf, DI_SER_CONF);
++ }
++
++ mutex_unlock(&ipu->mutex_lock);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_async_panel);
++
++/*!
++ * This function sets the foreground and background plane global alpha blending
++ * modes. This function also sets the DP graphic plane according to the
++ * parameter of IPUv3 DP channel.
++ *
++ * @param ipu ipu handler
++ * @param channel IPUv3 DP channel
++ *
++ * @param enable Boolean to enable or disable global alpha
++ * blending. If disabled, local blending is used.
++ *
++ * @param alpha Global alpha value.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel,
++ bool enable, uint8_t alpha)
++{
++ uint32_t reg;
++ uint32_t flow;
++ bool bg_chan;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
++ channel == MEM_BG_ASYNC1)
++ bg_chan = true;
++ else
++ bg_chan = false;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (bg_chan) {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
++ }
++
++ if (enable) {
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
++ ipu_dp_write(ipu, reg | ((uint32_t) alpha << 24),
++ DP_GRAPH_WIND_CTRL(flow));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
++ }
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_global_alpha);
++
++/*!
++ * This function sets the transparent color key for SDC graphic plane.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param enable Boolean to enable or disable color key
++ *
++ * @param colorKey 24-bit RGB color for transparent color key.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel,
++ bool enable, uint32_t color_key)
++{
++ uint32_t reg, flow;
++ int y, u, v;
++ int red, green, blue;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu->color_key_4rgb = true;
++ /* Transform color key from rgb to yuv if CSC is enabled */
++ if (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB))) {
++
++ dev_dbg(ipu->dev, "color key 0x%x need change to yuv fmt\n", color_key);
++
++ red = (color_key >> 16) & 0xFF;
++ green = (color_key >> 8) & 0xFF;
++ blue = color_key & 0xFF;
++
++ y = _rgb_to_yuv(0, red, green, blue);
++ u = _rgb_to_yuv(1, red, green, blue);
++ v = _rgb_to_yuv(2, red, green, blue);
++ color_key = (y << 16) | (u << 8) | v;
++
++ ipu->color_key_4rgb = false;
++
++ dev_dbg(ipu->dev, "color key change to yuv fmt 0x%x\n", color_key);
++ }
++
++ if (enable) {
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
++ ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(flow));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
++ }
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_color_key);
++
++/*!
++ * This function sets the gamma correction for DP output.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param enable Boolean to enable or disable gamma correction.
++ *
++ * @param constk Gamma piecewise linear approximation constk coeff.
++ *
++ * @param slopek Gamma piecewise linear approximation slopek coeff.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, int constk[], int slopek[])
++{
++ uint32_t reg, flow, i;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ for (i = 0; i < 8; i++)
++ ipu_dp_write(ipu, (constk[2*i] & 0x1ff) | ((constk[2*i+1] & 0x1ff) << 16), DP_GAMMA_C(flow, i));
++ for (i = 0; i < 4; i++)
++ ipu_dp_write(ipu, (slopek[4*i] & 0xff) | ((slopek[4*i+1] & 0xff) << 8) |
++ ((slopek[4*i+2] & 0xff) << 16) | ((slopek[4*i+3] & 0xff) << 24), DP_GAMMA_S(flow, i));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ if (enable) {
++ if ((ipu->bg_csc_type == RGB2YUV) || (ipu->bg_csc_type == YUV2YUV))
++ reg |= DP_COM_CONF_GAMMA_YUV_EN;
++ else
++ reg &= ~DP_COM_CONF_GAMMA_YUV_EN;
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
++ } else
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_gamma_correction);
++
++/*!
++ * This function sets the window position of the foreground or background plane.
++ * modes.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param x_pos The X coordinate position to place window at.
++ * The position is relative to the top left corner.
++ *
++ * @param y_pos The Y coordinate position to place window at.
++ * The position is relative to the top left corner.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos)
++{
++ u32 reg;
++ uint32_t flow = 0;
++ uint32_t dp_srm_shift;
++
++ if ((channel == MEM_FG_SYNC) || (channel == MEM_BG_SYNC)) {
++ flow = DP_SYNC;
++ dp_srm_shift = 3;
++ } else if (channel == MEM_FG_ASYNC0) {
++ flow = DP_ASYNC0;
++ dp_srm_shift = 5;
++ } else if (channel == MEM_FG_ASYNC1) {
++ flow = DP_ASYNC1;
++ dp_srm_shift = 7;
++ } else
++ return -EINVAL;
++
++ ipu_dp_write(ipu, (x_pos << 16) | y_pos, DP_FG_POS(flow));
++
++ if (ipu_is_channel_busy(ipu, channel)) {
++ /* controled by FSU if channel enabled */
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
++ reg |= (0x1 << dp_srm_shift);
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ } else {
++ /* disable auto swap, controled by MCU if channel disabled */
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++
++ return 0;
++}
++
++int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos)
++{
++ int ret;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ret = _ipu_disp_set_window_pos(ipu, channel, x_pos, y_pos);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_disp_set_window_pos);
++
++int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos)
++{
++ u32 reg;
++ uint32_t flow = 0;
++
++ if (channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ reg = ipu_dp_read(ipu, DP_FG_POS(flow));
++
++ *x_pos = (reg >> 16) & 0x7FF;
++ *y_pos = reg & 0x7FF;
++
++ return 0;
++}
++int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos)
++{
++ int ret;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ret = _ipu_disp_get_window_pos(ipu, channel, x_pos, y_pos);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_disp_get_window_pos);
++
++void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset)
++{
++ if (channel == DIRECT_ASYNC0)
++ writel(value, ipu->disp_base[0] + offset);
++ else if (channel == DIRECT_ASYNC1)
++ writel(value, ipu->disp_base[1] + offset);
++}
++EXPORT_SYMBOL(ipu_disp_direct_write);
++
++void ipu_reset_disp_panel(struct ipu_soc *ipu)
++{
++ uint32_t tmp;
++
++ tmp = ipu_di_read(ipu, 1, DI_GENERAL);
++ ipu_di_write(ipu, 1, tmp | 0x08, DI_GENERAL);
++ msleep(10); /* tRES >= 100us */
++ tmp = ipu_di_read(ipu, 1, DI_GENERAL);
++ ipu_di_write(ipu, 1, tmp & ~0x08, DI_GENERAL);
++ msleep(60);
++
++ return;
++}
++EXPORT_SYMBOL(ipu_reset_disp_panel);
++
++void ipu_disp_init(struct ipu_soc *ipu)
++{
++ ipu->fg_csc_type = ipu->bg_csc_type = CSC_NONE;
++ ipu->color_key_4rgb = true;
++ _ipu_init_dc_mappings(ipu);
++ _ipu_dmfc_init(ipu, DMFC_NORMAL, 1);
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_ic.c linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_ic.c
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_ic.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_ic.c 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,924 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_ic.c
++ *
++ * @brief IPU IC functions
++ *
++ * @ingroup IPU
++ */
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++#include <linux/videodev2.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++enum {
++ IC_TASK_VIEWFINDER,
++ IC_TASK_ENCODER,
++ IC_TASK_POST_PROCESSOR
++};
++
++static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
++ ipu_color_space_t out_format, int csc_index);
++
++static int _calc_resize_coeffs(struct ipu_soc *ipu,
++ uint32_t inSize, uint32_t outSize,
++ uint32_t *resizeCoeff,
++ uint32_t *downsizeCoeff);
++
++void _ipu_vdi_set_top_field_man(struct ipu_soc *ipu, bool top_field_0)
++{
++ uint32_t reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ if (top_field_0)
++ reg &= ~VDI_C_TOP_FIELD_MAN_1;
++ else
++ reg |= VDI_C_TOP_FIELD_MAN_1;
++ ipu_vdi_write(ipu, reg, VDI_C);
++}
++
++void _ipu_vdi_set_motion(struct ipu_soc *ipu, ipu_motion_sel motion_sel)
++{
++ uint32_t reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ reg &= ~(VDI_C_MOT_SEL_FULL | VDI_C_MOT_SEL_MED | VDI_C_MOT_SEL_LOW);
++ if (motion_sel == HIGH_MOTION)
++ reg |= VDI_C_MOT_SEL_FULL;
++ else if (motion_sel == MED_MOTION)
++ reg |= VDI_C_MOT_SEL_MED;
++ else
++ reg |= VDI_C_MOT_SEL_LOW;
++
++ ipu_vdi_write(ipu, reg, VDI_C);
++ dev_dbg(ipu->dev, "VDI_C = \t0x%08X\n", reg);
++}
++
++void ic_dump_register(struct ipu_soc *ipu)
++{
++ printk(KERN_DEBUG "IC_CONF = \t0x%08X\n", ipu_ic_read(ipu, IC_CONF));
++ printk(KERN_DEBUG "IC_PRP_ENC_RSC = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_PRP_ENC_RSC));
++ printk(KERN_DEBUG "IC_PRP_VF_RSC = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_PRP_VF_RSC));
++ printk(KERN_DEBUG "IC_PP_RSC = \t0x%08X\n", ipu_ic_read(ipu, IC_PP_RSC));
++ printk(KERN_DEBUG "IC_IDMAC_1 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_1));
++ printk(KERN_DEBUG "IC_IDMAC_2 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_2));
++ printk(KERN_DEBUG "IC_IDMAC_3 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_3));
++}
++
++void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t ic_conf;
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++ switch (channel) {
++ case CSI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN | IC_CONF_RWS_EN ;
++ break;
++ case MEM_ROT_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_ROT_EN;
++ break;
++ case CSI_PRP_ENC_MEM:
++ case MEM_PRP_ENC_MEM:
++ ic_conf |= IC_CONF_PRPENC_EN;
++ break;
++ case MEM_ROT_ENC_MEM:
++ ic_conf |= IC_CONF_PRPENC_ROT_EN;
++ break;
++ case MEM_PP_MEM:
++ ic_conf |= IC_CONF_PP_EN;
++ break;
++ case MEM_ROT_PP_MEM:
++ ic_conf |= IC_CONF_PP_ROT_EN;
++ break;
++ default:
++ break;
++ }
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++}
++
++void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t ic_conf;
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++ switch (channel) {
++ case CSI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_MEM:
++ ic_conf &= ~(IC_CONF_PRPVF_EN | IC_CONF_RWS_EN);
++ break;
++ case MEM_ROT_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_ROT_EN;
++ break;
++ case CSI_PRP_ENC_MEM:
++ case MEM_PRP_ENC_MEM:
++ ic_conf &= ~IC_CONF_PRPENC_EN;
++ break;
++ case MEM_ROT_ENC_MEM:
++ ic_conf &= ~IC_CONF_PRPENC_ROT_EN;
++ break;
++ case MEM_PP_MEM:
++ ic_conf &= ~IC_CONF_PP_EN;
++ break;
++ case MEM_ROT_PP_MEM:
++ ic_conf &= ~IC_CONF_PP_ROT_EN;
++ break;
++ default:
++ break;
++ }
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++}
++
++void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
++{
++ uint32_t reg;
++ uint32_t pixel_fmt;
++ uint32_t pix_per_burst;
++
++ reg = ((params->mem_prp_vf_mem.in_height-1) << 16) |
++ (params->mem_prp_vf_mem.in_width-1);
++ ipu_vdi_write(ipu, reg, VDI_FSIZE);
++
++ /* Full motion, only vertical filter is used
++ Burst size is 4 accesses */
++ if (params->mem_prp_vf_mem.in_pixel_fmt ==
++ IPU_PIX_FMT_UYVY ||
++ params->mem_prp_vf_mem.in_pixel_fmt ==
++ IPU_PIX_FMT_YUYV) {
++ pixel_fmt = VDI_C_CH_422;
++ pix_per_burst = 32;
++ } else {
++ pixel_fmt = VDI_C_CH_420;
++ pix_per_burst = 64;
++ }
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ reg |= pixel_fmt;
++ switch (channel) {
++ case MEM_VDI_PRP_VF_MEM:
++ reg |= VDI_C_BURST_SIZE2_4;
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_SET_1 | VDI_C_VWM1_CLR_2;
++ break;
++ case MEM_VDI_PRP_VF_MEM_N:
++ reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_SET_1 | VDI_C_VWM3_CLR_2;
++ break;
++
++ case MEM_VDI_MEM:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE2_OFFSET;
++ break;
++ case MEM_VDI_MEM_P:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE1_OFFSET;
++ reg |= VDI_C_VWM1_SET_2 | VDI_C_VWM1_CLR_2;
++ break;
++ case MEM_VDI_MEM_N:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE3_OFFSET;
++ reg |= VDI_C_VWM3_SET_2 | VDI_C_VWM3_CLR_2;
++ break;
++ default:
++ break;
++ }
++ ipu_vdi_write(ipu, reg, VDI_C);
++
++ if (params->mem_prp_vf_mem.field_fmt == IPU_DEINTERLACE_FIELD_TOP)
++ _ipu_vdi_set_top_field_man(ipu, true);
++ else if (params->mem_prp_vf_mem.field_fmt == IPU_DEINTERLACE_FIELD_BOTTOM)
++ _ipu_vdi_set_top_field_man(ipu, false);
++
++ _ipu_vdi_set_motion(ipu, params->mem_prp_vf_mem.motion_sel);
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_RWS_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_vdi_uninit(struct ipu_soc *ipu)
++{
++ ipu_vdi_write(ipu, 0, VDI_FSIZE);
++ ipu_vdi_write(ipu, 0, VDI_C);
++}
++
++int _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_prp_vf_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_height,
++ params->mem_prp_vf_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpvf height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else
++ reg = (params->mem_prp_vf_mem.outv_resize_ratio) << 16;
++
++ /* Setup horizontal resizing */
++ if (!params->mem_prp_vf_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_width,
++ params->mem_prp_vf_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpvf width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else
++ reg |= params->mem_prp_vf_mem.outh_resize_ratio;
++
++ ipu_ic_write(ipu, reg, IC_PRP_VF_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_prp_vf_mem.graphics_combine_en) {
++ ic_conf |= IC_CONF_PRPVF_CMB;
++
++ if (!(ic_conf & IC_CONF_PRPVF_CSC1)) {
++ /* need transparent CSC1 conversion */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, RGB, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->RGB CSC */
++ }
++ in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_g_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC2 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 2);
++ ic_conf |= IC_CONF_PRPVF_CSC2;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC2 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 2);
++ ic_conf |= IC_CONF_PRPVF_CSC2;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_prp_vf_mem.global_alpha_en) {
++ ic_conf |= IC_CONF_IC_GLB_LOC_A;
++ reg = ipu_ic_read(ipu, IC_CMBP_1);
++ reg &= ~(0xff);
++ reg |= params->mem_prp_vf_mem.alpha;
++ ipu_ic_write(ipu, reg, IC_CMBP_1);
++ } else
++ ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
++
++ if (params->mem_prp_vf_mem.key_color_en) {
++ ic_conf |= IC_CONF_KEY_COLOR_EN;
++ ipu_ic_write(ipu, params->mem_prp_vf_mem.key_color,
++ IC_CMBP_2);
++ } else
++ ic_conf &= ~IC_CONF_KEY_COLOR_EN;
++ } else {
++ ic_conf &= ~IC_CONF_PRPVF_CMB;
++ }
++
++ if (src_is_csi)
++ ic_conf &= ~IC_CONF_RWS_EN;
++ else
++ ic_conf |= IC_CONF_RWS_EN;
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB |
++ IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_PRPVF_ROT_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_prp_enc_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu,
++ params->mem_prp_enc_mem.in_height,
++ params->mem_prp_enc_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpenc height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else
++ reg = (params->mem_prp_enc_mem.outv_resize_ratio) << 16;
++
++ /* Setup horizontal resizing */
++ if (!params->mem_prp_enc_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_enc_mem.in_width,
++ params->mem_prp_enc_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpenc width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else
++ reg |= params->mem_prp_enc_mem.outh_resize_ratio;
++
++ ipu_ic_write(ipu, reg, IC_PRP_ENC_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_ENCODER, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PRPENC_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_ENCODER, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PRPENC_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (src_is_csi)
++ ic_conf &= ~IC_CONF_RWS_EN;
++ else
++ ic_conf |= IC_CONF_RWS_EN;
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPENC_ROT_EN);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_pp_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_pp_mem.in_height,
++ params->mem_pp_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate pp height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else {
++ reg = (params->mem_pp_mem.outv_resize_ratio) << 16;
++ }
++
++ /* Setup horizontal resizing */
++ if (!params->mem_pp_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_pp_mem.in_width,
++ params->mem_pp_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate pp width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else {
++ reg |= params->mem_pp_mem.outh_resize_ratio;
++ }
++
++ ipu_ic_write(ipu, reg, IC_PP_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PP_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PP_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_pp_mem.graphics_combine_en) {
++ ic_conf |= IC_CONF_PP_CMB;
++
++ if (!(ic_conf & IC_CONF_PP_CSC1)) {
++ /* need transparent CSC1 conversion */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, RGB, 1);
++ ic_conf |= IC_CONF_PP_CSC1; /* Enable RGB->RGB CSC */
++ }
++
++ in_fmt = format_to_colorspace(params->mem_pp_mem.in_g_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC2 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 2);
++ ic_conf |= IC_CONF_PP_CSC2;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC2 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 2);
++ ic_conf |= IC_CONF_PP_CSC2;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_pp_mem.global_alpha_en) {
++ ic_conf |= IC_CONF_IC_GLB_LOC_A;
++ reg = ipu_ic_read(ipu, IC_CMBP_1);
++ reg &= ~(0xff00);
++ reg |= (params->mem_pp_mem.alpha << 8);
++ ipu_ic_write(ipu, reg, IC_CMBP_1);
++ } else
++ ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
++
++ if (params->mem_pp_mem.key_color_en) {
++ ic_conf |= IC_CONF_KEY_COLOR_EN;
++ ipu_ic_write(ipu, params->mem_pp_mem.key_color,
++ IC_CMBP_2);
++ } else
++ ic_conf &= ~IC_CONF_KEY_COLOR_EN;
++ } else {
++ ic_conf &= ~IC_CONF_PP_CMB;
++ }
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_pp(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 |
++ IC_CONF_PP_CMB);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_PP_ROT_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan,
++ uint16_t width, uint16_t height,
++ int burst_size, ipu_rotate_mode_t rot)
++{
++ u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
++ u32 temp_rot = bitrev8(rot) >> 5;
++ bool need_hor_flip = false;
++
++ if ((burst_size != 8) && (burst_size != 16)) {
++ dev_dbg(ipu->dev, "Illegal burst length for IC\n");
++ return -EINVAL;
++ }
++
++ width--;
++ height--;
++
++ if (temp_rot & 0x2) /* Need horizontal flip */
++ need_hor_flip = true;
++
++ ic_idmac_1 = ipu_ic_read(ipu, IC_IDMAC_1);
++ ic_idmac_2 = ipu_ic_read(ipu, IC_IDMAC_2);
++ ic_idmac_3 = ipu_ic_read(ipu, IC_IDMAC_3);
++ if (dma_chan == 22) { /* PP output - CB2 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
++ } else if (dma_chan == 11) { /* PP Input - CB5 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
++ } else if (dma_chan == 47) { /* PP Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
++ }
++
++ if (dma_chan == 12) { /* PRP Input - CB6 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
++ }
++
++ if (dma_chan == 20) { /* PRP ENC output - CB0 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
++
++ } else if (dma_chan == 45) { /* PRP ENC Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
++ }
++
++ if (dma_chan == 21) { /* PRP VF output - CB1 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
++
++ } else if (dma_chan == 46) { /* PRP VF Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
++ }
++
++ if (dma_chan == 14) { /* PRP VF graphics combining input - CB3 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
++ } else if (dma_chan == 15) { /* PP graphics combining input - CB4 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
++ } else if (dma_chan == 5) { /* VDIC OUTPUT - CB7 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16;
++ }
++
++ ipu_ic_write(ipu, ic_idmac_1, IC_IDMAC_1);
++ ipu_ic_write(ipu, ic_idmac_2, IC_IDMAC_2);
++ ipu_ic_write(ipu, ic_idmac_3, IC_IDMAC_3);
++ return 0;
++}
++
++static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
++ ipu_color_space_t out_format, int csc_index)
++{
++ /*
++ * Y = 0.257 * R + 0.504 * G + 0.098 * B + 16;
++ * U = -0.148 * R - 0.291 * G + 0.439 * B + 128;
++ * V = 0.439 * R - 0.368 * G - 0.071 * B + 128;
++ */
++ static const uint32_t rgb2ycbcr_coeff[4][3] = {
++ {0x0042, 0x0081, 0x0019},
++ {0x01DA, 0x01B6, 0x0070},
++ {0x0070, 0x01A2, 0x01EE},
++ {0x0040, 0x0200, 0x0200}, /* A0, A1, A2 */
++ };
++
++ /* transparent RGB->RGB matrix for combining
++ */
++ static const uint32_t rgb2rgb_coeff[4][3] = {
++ {0x0080, 0x0000, 0x0000},
++ {0x0000, 0x0080, 0x0000},
++ {0x0000, 0x0000, 0x0080},
++ {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */
++ };
++
++/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
++ G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
++ B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
++ static const uint32_t ycbcr2rgb_coeff[4][3] = {
++ {149, 0, 204},
++ {149, 462, 408},
++ {149, 255, 0},
++ {8192 - 446, 266, 8192 - 554}, /* A0, A1, A2 */
++ };
++
++ uint32_t param;
++ uint32_t *base = NULL;
++
++ if (ic_task == IC_TASK_ENCODER) {
++ base = ipu->tpmem_base + 0x2008 / 4;
++ } else if (ic_task == IC_TASK_VIEWFINDER) {
++ if (csc_index == 1)
++ base = ipu->tpmem_base + 0x4028 / 4;
++ else
++ base = ipu->tpmem_base + 0x4040 / 4;
++ } else if (ic_task == IC_TASK_POST_PROCESSOR) {
++ if (csc_index == 1)
++ base = ipu->tpmem_base + 0x6060 / 4;
++ else
++ base = ipu->tpmem_base + 0x6078 / 4;
++ } else {
++ BUG();
++ }
++
++ if ((in_format == YCbCr) && (out_format == RGB)) {
++ /* Init CSC (YCbCr->RGB) */
++ param = (ycbcr2rgb_coeff[3][0] << 27) |
++ (ycbcr2rgb_coeff[0][0] << 18) |
++ (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2];
++ writel(param, base++);
++ /* scale = 2, sat = 0 */
++ param = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32));
++ writel(param, base++);
++
++ param = (ycbcr2rgb_coeff[3][1] << 27) |
++ (ycbcr2rgb_coeff[0][1] << 18) |
++ (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0];
++ writel(param, base++);
++ param = (ycbcr2rgb_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param = (ycbcr2rgb_coeff[3][2] << 27) |
++ (ycbcr2rgb_coeff[0][2] << 18) |
++ (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1];
++ writel(param, base++);
++ param = (ycbcr2rgb_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else if ((in_format == RGB) && (out_format == YCbCr)) {
++ /* Init CSC (RGB->YCbCr) */
++ param = (rgb2ycbcr_coeff[3][0] << 27) |
++ (rgb2ycbcr_coeff[0][0] << 18) |
++ (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2];
++ writel(param, base++);
++ /* scale = 1, sat = 0 */
++ param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8);
++ writel(param, base++);
++
++ param = (rgb2ycbcr_coeff[3][1] << 27) |
++ (rgb2ycbcr_coeff[0][1] << 18) |
++ (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0];
++ writel(param, base++);
++ param = (rgb2ycbcr_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param = (rgb2ycbcr_coeff[3][2] << 27) |
++ (rgb2ycbcr_coeff[0][2] << 18) |
++ (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1];
++ writel(param, base++);
++ param = (rgb2ycbcr_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else if ((in_format == RGB) && (out_format == RGB)) {
++ /* Init CSC */
++ param =
++ (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) |
++ (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2];
++ writel(param, base++);
++ /* scale = 2, sat = 0 */
++ param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8);
++ writel(param, base++);
++
++ param =
++ (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) |
++ (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0];
++ writel(param, base++);
++ param = (rgb2rgb_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param =
++ (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) |
++ (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1];
++ writel(param, base++);
++ param = (rgb2rgb_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else {
++ dev_err(ipu->dev, "Unsupported color space conversion\n");
++ }
++}
++
++static int _calc_resize_coeffs(struct ipu_soc *ipu,
++ uint32_t inSize, uint32_t outSize,
++ uint32_t *resizeCoeff,
++ uint32_t *downsizeCoeff)
++{
++ uint32_t tempSize;
++ uint32_t tempDownsize;
++
++ if (inSize > 4096) {
++ dev_err(ipu->dev, "IC input size(%d) cannot exceed 4096\n",
++ inSize);
++ return -EINVAL;
++ }
++
++ if (outSize > 1024) {
++ dev_err(ipu->dev, "IC output size(%d) cannot exceed 1024\n",
++ outSize);
++ return -EINVAL;
++ }
++
++ if ((outSize << 3) < inSize) {
++ dev_err(ipu->dev, "IC cannot downsize more than 8:1\n");
++ return -EINVAL;
++ }
++
++ /* Compute downsizing coefficient */
++ /* Output of downsizing unit cannot be more than 1024 */
++ tempDownsize = 0;
++ tempSize = inSize;
++ while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
++ (tempDownsize < 2)) {
++ tempSize >>= 1;
++ tempDownsize++;
++ }
++ *downsizeCoeff = tempDownsize;
++
++ /* compute resizing coefficient using the following equation:
++ resizeCoeff = M*(SI -1)/(SO - 1)
++ where M = 2^13, SI - input size, SO - output size */
++ *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
++ if (*resizeCoeff >= 16384L) {
++ dev_err(ipu->dev, "Overflow on IC resize coefficient.\n");
++ return -EINVAL;
++ }
++
++ dev_dbg(ipu->dev, "resizing from %u -> %u pixels, "
++ "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
++ *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
++ ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
++
++ return 0;
++}
++
++void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ uint32_t mask_reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ mask_reg = reg & VDI_C_TOP_FIELD_MAN_1;
++ if (mask_reg == VDI_C_TOP_FIELD_MAN_1)
++ reg &= ~VDI_C_TOP_FIELD_MAN_1;
++ else
++ reg |= VDI_C_TOP_FIELD_MAN_1;
++
++ ipu_vdi_write(ipu, reg, VDI_C);
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_param_mem.h linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_param_mem.h
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_param_mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_param_mem.h 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,921 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __INCLUDE_IPU_PARAM_MEM_H__
++#define __INCLUDE_IPU_PARAM_MEM_H__
++
++#include <linux/bitrev.h>
++#include <linux/types.h>
++
++#include "ipu_prv.h"
++
++extern u32 *ipu_cpmem_base;
++
++struct ipu_ch_param_word {
++ uint32_t data[5];
++ uint32_t res[3];
++};
++
++struct ipu_ch_param {
++ struct ipu_ch_param_word word[2];
++};
++
++#define ipu_ch_param_addr(ipu, ch) (((struct ipu_ch_param *)ipu->cpmem_base) + (ch))
++
++#define _param_word(base, w) \
++ (((struct ipu_ch_param *)(base))->word[(w)].data)
++
++#define ipu_ch_param_set_field(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ _param_word(base, w)[i] |= (v) << off; \
++ if (((bit)+(size)-1)/32 > i) { \
++ _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
++ } \
++}
++
++#define ipu_ch_param_set_field_io(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ unsigned reg_offset; \
++ u32 temp; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp |= (v) << off; \
++ writel(temp, (u32 *)base + reg_offset); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp |= (v) >> (off ? (32 - off) : 0); \
++ writel(temp, (u32 *)base + reg_offset); \
++ } \
++}
++
++#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ u32 temp = _param_word(base, w)[i]; \
++ temp &= ~(mask << off); \
++ _param_word(base, w)[i] = temp | (v) << off; \
++ if (((bit)+(size)-1)/32 > i) { \
++ temp = _param_word(base, w)[i + 1]; \
++ temp &= ~(mask >> (32 - off)); \
++ _param_word(base, w)[i + 1] = \
++ temp | ((v) >> (off ? (32 - off) : 0)); \
++ } \
++}
++
++#define ipu_ch_param_mod_field_io(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ unsigned reg_offset; \
++ u32 temp; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp &= ~(mask << off); \
++ temp |= (v) << off; \
++ writel(temp, (u32 *)base + reg_offset); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp &= ~(mask >> (32 - off)); \
++ temp |= ((v) >> (off ? (32 - off) : 0)); \
++ writel(temp, (u32 *)base + reg_offset); \
++ } \
++}
++
++#define ipu_ch_param_read_field(base, w, bit, size) ({ \
++ u32 temp2; \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ u32 temp1 = _param_word(base, w)[i]; \
++ temp1 = mask & (temp1 >> off); \
++ if (((bit)+(size)-1)/32 > i) { \
++ temp2 = _param_word(base, w)[i + 1]; \
++ temp2 &= mask >> (off ? (32 - off) : 0); \
++ temp1 |= temp2 << (off ? (32 - off) : 0); \
++ } \
++ temp1; \
++})
++
++#define ipu_ch_param_read_field_io(base, w, bit, size) ({ \
++ u32 temp1, temp2; \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ unsigned reg_offset; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp1 = readl((u32 *)base + reg_offset); \
++ temp1 = mask & (temp1 >> off); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp2 = readl((u32 *)base + reg_offset); \
++ temp2 &= mask >> (off ? (32 - off) : 0); \
++ temp1 |= temp2 << (off ? (32 - off) : 0); \
++ } \
++ temp1; \
++})
++
++static inline int __ipu_ch_get_third_buf_cpmem_num(int ch)
++{
++ switch (ch) {
++ case 8:
++ return 64;
++ case 9:
++ return 65;
++ case 10:
++ return 66;
++ case 13:
++ return 67;
++ case 21:
++ return 68;
++ case 23:
++ return 69;
++ case 27:
++ return 70;
++ case 28:
++ return 71;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static inline void _ipu_ch_params_set_packing(struct ipu_ch_param *p,
++ int red_width, int red_offset,
++ int green_width, int green_offset,
++ int blue_width, int blue_offset,
++ int alpha_width, int alpha_offset)
++{
++ /* Setup red width and offset */
++ ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
++ ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
++ /* Setup green width and offset */
++ ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
++ ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
++ /* Setup blue width and offset */
++ ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
++ ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
++ /* Setup alpha width and offset */
++ ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
++ ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
++}
++
++static inline void _ipu_ch_param_dump(struct ipu_soc *ipu, int ch)
++{
++ struct ipu_ch_param *p = ipu_ch_param_addr(ipu, ch);
++ dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
++ p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
++ p->word[0].data[3], p->word[0].data[4]);
++ dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
++ p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
++ p->word[1].data[3], p->word[1].data[4]);
++ dev_dbg(ipu->dev, "PFS 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 85, 4));
++ dev_dbg(ipu->dev, "BPP 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 107, 3));
++ dev_dbg(ipu->dev, "NPB 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7));
++
++ dev_dbg(ipu->dev, "FW %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 125, 13));
++ dev_dbg(ipu->dev, "FH %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 138, 12));
++ dev_dbg(ipu->dev, "EBA0 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 0, 29) << 3);
++ dev_dbg(ipu->dev, "EBA1 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 29, 29) << 3);
++ dev_dbg(ipu->dev, "Stride %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14));
++ dev_dbg(ipu->dev, "scan_order %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 113, 1));
++ dev_dbg(ipu->dev, "uv_stride %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 128, 14));
++ dev_dbg(ipu->dev, "u_offset 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22) << 3);
++ dev_dbg(ipu->dev, "v_offset 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22) << 3);
++
++ dev_dbg(ipu->dev, "Width0 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 116, 3));
++ dev_dbg(ipu->dev, "Width1 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 119, 3));
++ dev_dbg(ipu->dev, "Width2 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 122, 3));
++ dev_dbg(ipu->dev, "Width3 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 125, 3));
++ dev_dbg(ipu->dev, "Offset0 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 128, 5));
++ dev_dbg(ipu->dev, "Offset1 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 133, 5));
++ dev_dbg(ipu->dev, "Offset2 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 138, 5));
++ dev_dbg(ipu->dev, "Offset3 %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 143, 5));
++}
++
++static inline void fill_cpmem(struct ipu_soc *ipu, int ch, struct ipu_ch_param *params)
++{
++ int i, w;
++ void *addr = ipu_ch_param_addr(ipu, ch);
++
++ /* 2 words, 5 valid data */
++ for (w = 0; w < 2; w++) {
++ for (i = 0; i < 5; i++) {
++ writel(params->word[w].data[i], addr);
++ addr += 4;
++ }
++ addr += 12;
++ }
++}
++
++static inline void _ipu_ch_param_init(struct ipu_soc *ipu, int ch,
++ uint32_t pixel_fmt, uint32_t width,
++ uint32_t height, uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t uv_stride, dma_addr_t addr0,
++ dma_addr_t addr1, dma_addr_t addr2)
++{
++ uint32_t u_offset = 0;
++ uint32_t v_offset = 0;
++ int32_t sub_ch = 0;
++ struct ipu_ch_param params;
++
++ memset(&params, 0, sizeof(params));
++
++ ipu_ch_param_set_field(&params, 0, 125, 13, width - 1);
++
++ if (((ch == 8) || (ch == 9) || (ch == 10)) && !ipu->vdoa_en) {
++ ipu_ch_param_set_field(&params, 0, 138, 12, (height / 2) - 1);
++ ipu_ch_param_set_field(&params, 1, 102, 14, (stride * 2) - 1);
++ } else {
++ /* note: for vdoa+vdi- ch8/9/10, always use band mode */
++ ipu_ch_param_set_field(&params, 0, 138, 12, height - 1);
++ ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
++ }
++
++ /* EBA is 8-byte aligned */
++ ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
++ ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
++ if (addr0%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's EBA0 is not 8-byte aligned\n", ch);
++ if (addr1%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's EBA1 is not 8-byte aligned\n", ch);
++
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ /*Represents 8-bit Generic data */
++ ipu_ch_param_set_field(&params, 0, 107, 3, 5); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 6); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 63); /* burst size */
++
++ break;
++ case IPU_PIX_FMT_GENERIC_16:
++ /* Represents 16-bit generic data */
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 6); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ break;
++ case IPU_PIX_FMT_GENERIC_32:
++ /*Represents 32-bit Generic data */
++ break;
++ case IPU_PIX_FMT_RGB565:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);
++ break;
++ case IPU_PIX_FMT_BGR24:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);
++ break;
++ case IPU_PIX_FMT_VYU444:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 8, 8, 0, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);
++ break;
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);
++ break;
++ case IPU_PIX_FMT_ABGR32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_UYVY:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0xA); /* pix format */
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YUYV:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0x8); /* pix format */
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ if (ipu->vdoa_en) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31);
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15);
++ }
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ ipu_ch_param_set_field(&params, 1, 85, 4, 2); /* pix format */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * height;
++ v_offset = u_offset + (uv_stride * height / 2);
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ uv_stride = uv_stride*2;
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ ipu_ch_param_set_field(&params, 1, 85, 4, 2); /* pix format */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * height;
++ u_offset = v_offset + (uv_stride * height / 2);
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ uv_stride = uv_stride*2;
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = (v == 0) ? stride * height : v;
++ u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = (u == 0) ? stride * height : u;
++ v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
++ break;
++ case IPU_PIX_FMT_YUV444P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ uv_stride = stride;
++ u_offset = (u == 0) ? stride * height : u;
++ v_offset = (v == 0) ? u_offset * 2 : v;
++ break;
++ case IPU_PIX_FMT_NV12:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 4); /* pix format */
++ uv_stride = stride;
++ u_offset = (u == 0) ? stride * height : u;
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ if (ipu->vdoa_en) {
++ /* one field buffer, memory width 64bits */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 63);
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15);
++ /* top/bottom field in one buffer*/
++ uv_stride = uv_stride*2;
++ }
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ default:
++ dev_err(ipu->dev, "mxc ipu: unimplemented pixel format\n");
++ break;
++ }
++ /*set burst size to 16*/
++
++
++ if (uv_stride)
++ ipu_ch_param_set_field(&params, 1, 128, 14, uv_stride - 1);
++
++ /* Get the uv offset from user when need cropping */
++ if (u || v) {
++ u_offset = u;
++ v_offset = v;
++ }
++
++ /* UBO and VBO are 22-bit and 8-byte aligned */
++ if (u_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset exceeds IPU limitation\n", ch);
++ if (v_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset exceeds IPU limitation\n", ch);
++ if (u_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset is not 8-byte aligned\n", ch);
++ if (v_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset is not 8-byte aligned\n", ch);
++
++ ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
++ ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
++
++ dev_dbg(ipu->dev, "initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ipu, ch));
++ fill_cpmem(ipu, ch, &params);
++ if (addr2) {
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++
++ ipu_ch_param_set_field(&params, 1, 0, 29, addr2 >> 3);
++ ipu_ch_param_set_field(&params, 1, 29, 29, 0);
++ if (addr2%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's sub-CPMEM entry%d EBA0 is not "
++ "8-byte aligned\n", ch, sub_ch);
++
++ dev_dbg(ipu->dev, "initializing idma ch %d @ %p sub cpmem\n", ch,
++ ipu_ch_param_addr(ipu, sub_ch));
++ fill_cpmem(ipu, sub_ch, &params);
++ }
++};
++
++static inline void _ipu_ch_param_set_burst_size(struct ipu_soc *ipu,
++ uint32_t ch,
++ uint16_t burst_pixels)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7,
++ burst_pixels - 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 78, 7,
++ burst_pixels - 1);
++};
++
++static inline int _ipu_ch_param_get_burst_size(struct ipu_soc *ipu, uint32_t ch)
++{
++ return ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7) + 1;
++};
++
++static inline int _ipu_ch_param_get_bpp(struct ipu_soc *ipu, uint32_t ch)
++{
++ return ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 107, 3);
++};
++
++static inline void _ipu_ch_param_set_buffer(struct ipu_soc *ipu, uint32_t ch,
++ int bufNum, dma_addr_t phyaddr)
++{
++ if (bufNum == 2) {
++ ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (ch <= 0)
++ return;
++ bufNum = 0;
++ }
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 29 * bufNum, 29,
++ phyaddr / 8);
++};
++
++static inline void _ipu_ch_param_set_rotation(struct ipu_soc *ipu, uint32_t ch,
++ ipu_rotate_mode_t rot)
++{
++ u32 temp_rot = bitrev8(rot) >> 5;
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 119, 3, temp_rot);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 119, 3, temp_rot);
++};
++
++static inline void _ipu_ch_param_set_block_mode(struct ipu_soc *ipu, uint32_t ch)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 117, 2, 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 117, 2, 1);
++};
++
++static inline void _ipu_ch_param_set_alpha_use_separate_channel(struct ipu_soc *ipu,
++ uint32_t ch,
++ bool option)
++{
++ int32_t sub_ch = 0;
++
++ if (option) {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 89, 1, 1);
++ } else {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 89, 1, 0);
++ }
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++
++ if (option) {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 89, 1, 1);
++ } else {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 89, 1, 0);
++ }
++};
++
++static inline void _ipu_ch_param_set_alpha_condition_read(struct ipu_soc *ipu, uint32_t ch)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 149, 1, 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 149, 1, 1);
++};
++
++static inline void _ipu_ch_param_set_alpha_buffer_memory(struct ipu_soc *ipu, uint32_t ch)
++{
++ int alp_mem_idx;
++ int32_t sub_ch = 0;
++
++ switch (ch) {
++ case 14: /* PRP graphic */
++ alp_mem_idx = 0;
++ break;
++ case 15: /* PP graphic */
++ alp_mem_idx = 1;
++ break;
++ case 23: /* DP BG SYNC graphic */
++ alp_mem_idx = 4;
++ break;
++ case 27: /* DP FG SYNC graphic */
++ alp_mem_idx = 2;
++ break;
++ default:
++ dev_err(ipu->dev, "unsupported correlative channel of local "
++ "alpha channel\n");
++ return;
++ }
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 90, 3, alp_mem_idx);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 90, 3, alp_mem_idx);
++};
++
++static inline void _ipu_ch_param_set_interlaced_scan(struct ipu_soc *ipu, uint32_t ch)
++{
++ u32 stride;
++ int32_t sub_ch = 0;
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch), 0, 113, 1, 1);
++ if (sub_ch > 0)
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 113, 1, 1);
++ stride = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14) + 1;
++ /* ILO is 20-bit and 8-byte aligned */
++ if (stride/8 > 0xfffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's ILO exceeds IPU limitation\n", ch);
++ if (stride%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's ILO is not 8-byte aligned\n", ch);
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 58, 20, stride / 8);
++ if (sub_ch > 0)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 58, 20,
++ stride / 8);
++ stride *= 2;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14, stride - 1);
++ if (sub_ch > 0)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 102, 14,
++ stride - 1);
++};
++
++static inline void _ipu_ch_param_set_axi_id(struct ipu_soc *ipu, uint32_t ch, uint32_t id)
++{
++ int32_t sub_ch = 0;
++
++ id %= 4;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 93, 2, id);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 93, 2, id);
++};
++
++/* IDMAC U/V offset changing support */
++/* U and V input is not affected, */
++/* the update is done by new calculation according to */
++/* vertical_offset and horizontal_offset */
++static inline void _ipu_ch_offset_update(struct ipu_soc *ipu,
++ int ch,
++ uint32_t pixel_fmt,
++ uint32_t width,
++ uint32_t height,
++ uint32_t stride,
++ uint32_t u,
++ uint32_t v,
++ uint32_t uv_stride,
++ uint32_t vertical_offset,
++ uint32_t horizontal_offset)
++{
++ uint32_t u_offset = 0;
++ uint32_t v_offset = 0;
++ uint32_t old_offset = 0;
++ uint32_t u_fix = 0;
++ uint32_t v_fix = 0;
++ int32_t sub_ch = 0;
++
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_GENERIC_16:
++ case IPU_PIX_FMT_GENERIC_32:
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_ABGR32:
++ case IPU_PIX_FMT_UYVY:
++ case IPU_PIX_FMT_YUYV:
++ break;
++
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset / 2;
++ v_offset = u_offset + (uv_stride * height / 2);
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset / 2;
++ u_offset = v_offset + (uv_stride * height / 2);
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset / 2;
++ u_offset = v_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset / 2;
++ v_offset = u_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++ break;
++
++ case IPU_PIX_FMT_YUV444P:
++ uv_stride = stride;
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset;
++ v_offset = u_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset -
++ (stride * vertical_offset) -
++ (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset -
++ (stride * vertical_offset) -
++ (horizontal_offset)) :
++ v_offset;
++ break;
++ case IPU_PIX_FMT_NV12:
++ uv_stride = stride;
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset;
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ horizontal_offset -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++
++ break;
++ default:
++ dev_err(ipu->dev, "mxc ipu: unimplemented pixel format\n");
++ break;
++ }
++
++
++
++ if (u_fix > u_offset)
++ u_offset = u_fix;
++
++ if (v_fix > v_offset)
++ v_offset = v_fix;
++
++ /* UBO and VBO are 22-bit and 8-byte aligned */
++ if (u_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset exceeds IPU limitation\n", ch);
++ if (v_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset exceeds IPU limitation\n", ch);
++ if (u_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset is not 8-byte aligned\n", ch);
++ if (v_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset is not 8-byte aligned\n", ch);
++
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22);
++ if (old_offset != u_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22, u_offset / 8);
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22);
++ if (old_offset != v_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22, v_offset / 8);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 46, 22);
++ if (old_offset != u_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 46, 22, u_offset / 8);
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 68, 22);
++ if (old_offset != v_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 68, 22, v_offset / 8);
++};
++
++static inline void _ipu_ch_params_set_alpha_width(struct ipu_soc *ipu, uint32_t ch, int alpha_width)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch), 1, 125, 3, alpha_width - 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 125, 3, alpha_width - 1);
++};
++
++static inline void _ipu_ch_param_set_bandmode(struct ipu_soc *ipu,
++ uint32_t ch, uint32_t band_height)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch),
++ 0, 114, 3, band_height - 1);
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch),
++ 0, 114, 3, band_height - 1);
++
++ dev_dbg(ipu->dev, "BNDM 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 114, 3));
++}
++
++/*
++ * The IPUv3 IDMAC has a bug to read 32bpp pixels from a graphics plane
++ * whose alpha component is at the most significant 8 bits. The bug only
++ * impacts on cases in which the relevant separate alpha channel is enabled.
++ *
++ * Return true on bad alpha component position, otherwise, return false.
++ */
++static inline bool _ipu_ch_param_bad_alpha_pos(uint32_t pixel_fmt)
++{
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ return true;
++ }
++
++ return false;
++}
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_pixel_clk.c linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_pixel_clk.c
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_pixel_clk.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_pixel_clk.c 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,317 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_pixel_clk.c
++ *
++ * @brief IPU pixel clock implementation
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++
++#include "ipu_prv.h"
++#include "ipu_regs.h"
++
++ /*
++ * muxd clock implementation
++ */
++struct clk_di_mux {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++ u8 index;
++};
++#define to_clk_di_mux(_hw) container_of(_hw, struct clk_di_mux, hw)
++
++static int _ipu_pixel_clk_set_parent(struct clk_hw *hw, u8 index)
++{
++ struct clk_di_mux *mux = to_clk_di_mux(hw);
++ struct ipu_soc *ipu = ipu_get_soc(mux->ipu_id);
++ u32 di_gen;
++
++ di_gen = ipu_di_read(ipu, mux->di_id, DI_GENERAL);
++ if (index == 0)
++ /* ipu1_clk or ipu2_clk internal clk */
++ di_gen &= ~DI_GEN_DI_CLK_EXT;
++ else
++ di_gen |= DI_GEN_DI_CLK_EXT;
++
++ ipu_di_write(ipu, mux->di_id, di_gen, DI_GENERAL);
++ mux->index = index;
++ pr_debug("ipu_pixel_clk: di_clk_ext:0x%x, di_gen reg:0x%x.\n",
++ !(di_gen & DI_GEN_DI_CLK_EXT), di_gen);
++ return 0;
++}
++
++static u8 _ipu_pixel_clk_get_parent(struct clk_hw *hw)
++{
++ struct clk_di_mux *mux = to_clk_di_mux(hw);
++
++ return mux->index;
++}
++
++const struct clk_ops clk_mux_di_ops = {
++ .get_parent = _ipu_pixel_clk_get_parent,
++ .set_parent = _ipu_pixel_clk_set_parent,
++};
++
++struct clk *clk_register_mux_pix_clk(struct device *dev, const char *name,
++ const char **parent_names, u8 num_parents, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_mux_flags)
++{
++ struct clk_di_mux *mux;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ mux = kzalloc(sizeof(struct clk_di_mux), GFP_KERNEL);
++ if (!mux)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ init.ops = &clk_mux_di_ops;
++ init.flags = flags;
++ init.parent_names = parent_names;
++ init.num_parents = num_parents;
++
++ mux->ipu_id = ipu_id;
++ mux->di_id = di_id;
++ mux->flags = clk_mux_flags | CLK_SET_RATE_PARENT;
++ mux->hw.init = &init;
++
++ clk = clk_register(dev, &mux->hw);
++ if (IS_ERR(clk))
++ kfree(mux);
++
++ return clk;
++}
++
++/*
++ * Gated clock implementation
++ */
++struct clk_di_div {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++};
++#define to_clk_di_div(_hw) container_of(_hw, struct clk_di_div, hw)
++
++static unsigned long _ipu_pixel_clk_div_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct clk_di_div *di_div = to_clk_di_div(hw);
++ struct ipu_soc *ipu = ipu_get_soc(di_div->ipu_id);
++ u32 div;
++ u64 final_rate = (unsigned long long)parent_rate * 16;
++
++ _ipu_get(ipu);
++ div = ipu_di_read(ipu, di_div->di_id, DI_BS_CLKGEN0);
++ _ipu_put(ipu);
++ pr_debug("ipu_di%d read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
++ di_div->di_id, div, final_rate, parent_rate);
++
++ if (div == 0)
++ return 0;
++ do_div(final_rate, div);
++
++ return (unsigned long)final_rate;
++}
++
++static long _ipu_pixel_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long *parent_clk_rate)
++{
++ u64 div, final_rate;
++ u32 remainder;
++ u64 parent_rate = (unsigned long long)(*parent_clk_rate) * 16;
++
++ /*
++ * Calculate divider
++ * Fractional part is 4 bits,
++ * so simply multiply by 2^4 to get fractional part.
++ */
++ div = parent_rate;
++ remainder = do_div(div, rate);
++ /* Round the divider value */
++ if (remainder > (rate/2))
++ div++;
++ if (div < 0x10) /* Min DI disp clock divider is 1 */
++ div = 0x10;
++ if (div & ~0xFEF)
++ div &= 0xFF8;
++ else {
++ /* Round up divider if it gets us closer to desired pix clk */
++ if ((div & 0xC) == 0xC) {
++ div += 0x10;
++ div &= ~0xF;
++ }
++ }
++ final_rate = parent_rate;
++ do_div(final_rate, div);
++
++ return final_rate;
++}
++
++static int _ipu_pixel_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long parent_clk_rate)
++{
++ struct clk_di_div *di_div = to_clk_di_div(hw);
++ struct ipu_soc *ipu = ipu_get_soc(di_div->ipu_id);
++ u64 div, parent_rate;
++ u32 remainder;
++
++ parent_rate = (unsigned long long)parent_clk_rate * 16;
++ div = parent_rate;
++ remainder = do_div(div, rate);
++ /* Round the divider value */
++ if (remainder > (rate/2))
++ div++;
++
++ /* Round up divider if it gets us closer to desired pix clk */
++ if ((div & 0xC) == 0xC) {
++ div += 0x10;
++ div &= ~0xF;
++ }
++ if (div > 0x1000)
++ pr_err("Overflow, di:%d, DI_BS_CLKGEN0 div:0x%x\n",
++ di_div->di_id, (u32)div);
++ _ipu_get(ipu);
++ ipu_di_write(ipu, di_div->di_id, (u32)div, DI_BS_CLKGEN0);
++
++ /* Setup pixel clock timing */
++ /* FIXME: needs to be more flexible */
++ /* Down time is half of period */
++ ipu_di_write(ipu, di_div->di_id, ((u32)div / 16) << 16, DI_BS_CLKGEN1);
++ _ipu_put(ipu);
++
++ return 0;
++}
++
++static struct clk_ops clk_div_ops = {
++ .recalc_rate = _ipu_pixel_clk_div_recalc_rate,
++ .round_rate = _ipu_pixel_clk_div_round_rate,
++ .set_rate = _ipu_pixel_clk_div_set_rate,
++};
++
++struct clk *clk_register_div_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_div_flags)
++{
++ struct clk_di_div *di_div;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ di_div = kzalloc(sizeof(struct clk_di_div), GFP_KERNEL);
++ if (!di_div)
++ return ERR_PTR(-ENOMEM);
++
++ /* struct clk_di_div assignments */
++ di_div->ipu_id = ipu_id;
++ di_div->di_id = di_id;
++ di_div->flags = clk_div_flags;
++
++ init.name = name;
++ init.ops = &clk_div_ops;
++ init.flags = flags | CLK_SET_RATE_PARENT;
++ init.parent_names = parent_name ? &parent_name : NULL;
++ init.num_parents = parent_name ? 1 : 0;
++
++ di_div->hw.init = &init;
++
++ clk = clk_register(dev, &di_div->hw);
++ if (IS_ERR(clk))
++ kfree(clk);
++
++ return clk;
++}
++
++/*
++ * Gated clock implementation
++ */
++struct clk_di_gate {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++};
++#define to_clk_di_gate(_hw) container_of(_hw, struct clk_di_gate, hw)
++
++static int _ipu_pixel_clk_enable(struct clk_hw *hw)
++{
++ struct clk_di_gate *gate = to_clk_di_gate(hw);
++ struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
++ u32 disp_gen;
++
++ disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
++ disp_gen |= gate->di_id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
++
++ return 0;
++}
++
++static void _ipu_pixel_clk_disable(struct clk_hw *hw)
++{
++ struct clk_di_gate *gate = to_clk_di_gate(hw);
++ struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
++ u32 disp_gen;
++
++ disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
++ disp_gen &= gate->di_id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
++
++}
++
++
++static struct clk_ops clk_gate_di_ops = {
++ .enable = _ipu_pixel_clk_enable,
++ .disable = _ipu_pixel_clk_disable,
++};
++
++struct clk *clk_register_gate_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_gate_flags)
++{
++ struct clk_di_gate *gate;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ gate = kzalloc(sizeof(struct clk_di_gate), GFP_KERNEL);
++ if (!gate)
++ return ERR_PTR(-ENOMEM);
++
++ gate->ipu_id = ipu_id;
++ gate->di_id = di_id;
++ gate->flags = clk_gate_flags;
++
++ init.name = name;
++ init.ops = &clk_gate_di_ops;
++ init.flags = flags | CLK_SET_RATE_PARENT;
++ init.parent_names = parent_name ? &parent_name : NULL;
++ init.num_parents = parent_name ? 1 : 0;
++
++ gate->hw.init = &init;
++
++ clk = clk_register(dev, &gate->hw);
++ if (IS_ERR(clk))
++ kfree(clk);
++
++ return clk;
++}
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_prv.h linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_prv.h
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_prv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_prv.h 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,356 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __INCLUDE_IPU_PRV_H__
++#define __INCLUDE_IPU_PRV_H__
++
++#include <linux/clkdev.h>
++#include <linux/device.h>
++#include <linux/fsl_devices.h>
++#include <linux/interrupt.h>
++#include <linux/types.h>
++
++#define MXC_IPU_MAX_NUM 2
++#define MXC_DI_NUM_PER_IPU 2
++
++/* Globals */
++extern int dmfc_type_setup;
++
++#define IDMA_CHAN_INVALID 0xFF
++#define HIGH_RESOLUTION_WIDTH 1024
++
++struct ipu_irq_node {
++ irqreturn_t(*handler) (int, void *); /*!< the ISR */
++ const char *name; /*!< device associated with the interrupt */
++ void *dev_id; /*!< some unique information for the ISR */
++ __u32 flags; /*!< not used */
++};
++
++enum csc_type_t {
++ RGB2YUV = 0,
++ YUV2RGB,
++ RGB2RGB,
++ YUV2YUV,
++ CSC_NONE,
++ CSC_NUM
++};
++
++enum imx_ipu_type {
++ IMX6Q_IPU,
++};
++
++struct ipu_pltfm_data {
++ u32 id;
++ u32 devtype;
++ int (*init) (int);
++ void (*pg) (int);
++
++ /*
++ * Bypass reset to avoid display channel being
++ * stopped by probe since it may starts to work
++ * in bootloader.
++ */
++ bool bypass_reset;
++};
++
++struct ipu_soc {
++ bool online;
++ struct ipu_pltfm_data *pdata;
++
++ /*clk*/
++ struct clk *ipu_clk;
++ struct clk *di_clk[2];
++ struct clk *di_clk_sel[2];
++ struct clk *pixel_clk[2];
++ struct clk *pixel_clk_sel[2];
++ struct clk *csi_clk[2];
++
++ /*irq*/
++ int irq_sync;
++ int irq_err;
++ struct ipu_irq_node irq_list[IPU_IRQ_COUNT];
++
++ /*reg*/
++ u32 *cm_reg;
++ u32 *idmac_reg;
++ u32 *dp_reg;
++ u32 *ic_reg;
++ u32 *dc_reg;
++ u32 *dc_tmpl_reg;
++ u32 *dmfc_reg;
++ u32 *di_reg[2];
++ u32 *smfc_reg;
++ u32 *csi_reg[2];
++ u32 *cpmem_base;
++ u32 *tpmem_base;
++ u32 *disp_base[2];
++ u32 *vdi_reg;
++
++ struct device *dev;
++
++ ipu_channel_t csi_channel[2];
++ ipu_channel_t using_ic_dirct_ch;
++ unsigned char dc_di_assignment[10];
++ bool sec_chan_en[24];
++ bool thrd_chan_en[24];
++ bool chan_is_interlaced[52];
++ uint32_t channel_init_mask;
++ uint32_t channel_enable_mask;
++
++ /*use count*/
++ int dc_use_count;
++ int dp_use_count;
++ int dmfc_use_count;
++ int smfc_use_count;
++ int ic_use_count;
++ int rot_use_count;
++ int vdi_use_count;
++ int di_use_count[2];
++ int csi_use_count[2];
++
++ struct mutex mutex_lock;
++ spinlock_t int_reg_spin_lock;
++ spinlock_t rdy_reg_spin_lock;
++
++ int dmfc_size_28;
++ int dmfc_size_29;
++ int dmfc_size_24;
++ int dmfc_size_27;
++ int dmfc_size_23;
++
++ enum csc_type_t fg_csc_type;
++ enum csc_type_t bg_csc_type;
++ bool color_key_4rgb;
++ bool dc_swap;
++ struct completion dc_comp;
++ struct completion csi_comp;
++
++ struct rot_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ int size;
++ } rot_dma[2];
++
++ int vdoa_en;
++ struct task_struct *thread[2];
++
++};
++
++struct ipu_channel {
++ u8 video_in_dma;
++ u8 alpha_in_dma;
++ u8 graph_in_dma;
++ u8 out_dma;
++};
++
++enum ipu_dmfc_type {
++ DMFC_NORMAL = 0,
++ DMFC_HIGH_RESOLUTION_DC,
++ DMFC_HIGH_RESOLUTION_DP,
++ DMFC_HIGH_RESOLUTION_ONLY_DP,
++};
++
++static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->cm_reg + offset);
++}
++
++static inline void ipu_cm_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->cm_reg + offset);
++}
++
++static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->idmac_reg + offset);
++}
++
++static inline void ipu_idmac_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->idmac_reg + offset);
++}
++
++static inline u32 ipu_dc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dc_reg + offset);
++}
++
++static inline void ipu_dc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dc_reg + offset);
++}
++
++static inline u32 ipu_dc_tmpl_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dc_tmpl_reg + offset);
++}
++
++static inline void ipu_dc_tmpl_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dc_tmpl_reg + offset);
++}
++
++static inline u32 ipu_dmfc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dmfc_reg + offset);
++}
++
++static inline void ipu_dmfc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dmfc_reg + offset);
++}
++
++static inline u32 ipu_dp_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dp_reg + offset);
++}
++
++static inline void ipu_dp_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dp_reg + offset);
++}
++
++static inline u32 ipu_di_read(struct ipu_soc *ipu, int di, unsigned offset)
++{
++ return readl(ipu->di_reg[di] + offset);
++}
++
++static inline void ipu_di_write(struct ipu_soc *ipu, int di,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->di_reg[di] + offset);
++}
++
++static inline u32 ipu_csi_read(struct ipu_soc *ipu, int csi, unsigned offset)
++{
++ return readl(ipu->csi_reg[csi] + offset);
++}
++
++static inline void ipu_csi_write(struct ipu_soc *ipu, int csi,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->csi_reg[csi] + offset);
++}
++
++static inline u32 ipu_smfc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->smfc_reg + offset);
++}
++
++static inline void ipu_smfc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->smfc_reg + offset);
++}
++
++static inline u32 ipu_vdi_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->vdi_reg + offset);
++}
++
++static inline void ipu_vdi_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->vdi_reg + offset);
++}
++
++static inline u32 ipu_ic_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->ic_reg + offset);
++}
++
++static inline void ipu_ic_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->ic_reg + offset);
++}
++
++int register_ipu_device(struct ipu_soc *ipu, int id);
++void unregister_ipu_device(struct ipu_soc *ipu, int id);
++ipu_color_space_t format_to_colorspace(uint32_t fmt);
++bool ipu_pixel_format_has_alpha(uint32_t fmt);
++
++void ipu_dump_registers(struct ipu_soc *ipu);
++
++uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
++
++void ipu_disp_init(struct ipu_soc *ipu);
++void _ipu_init_dc_mappings(struct ipu_soc *ipu);
++int _ipu_dp_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t in_pixel_fmt,
++ uint32_t out_pixel_fmt);
++void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt);
++void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan);
++void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap);
++void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first);
++void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width);
++void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size);
++int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel);
++
++void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel);
++int _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi);
++void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
++void _ipu_vdi_uninit(struct ipu_soc *ipu);
++void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu);
++void _ipu_ic_init_csi(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_csi(struct ipu_soc *ipu);
++int _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi);
++void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu);
++int _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_pp(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu);
++int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan, uint16_t width, uint16_t height,
++ int burst_size, ipu_rotate_mode_t rot);
++void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu);
++int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi);
++int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi);
++void ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
++ uint32_t g_value, uint32_t b_value,
++ uint32_t pix_clk, uint32_t csi);
++void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi);
++void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi);
++void _ipu_csi_wait4eof(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi);
++void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs);
++void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
++int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos);
++int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos);
++void _ipu_get(struct ipu_soc *ipu);
++void _ipu_put(struct ipu_soc *ipu);
++
++struct clk *clk_register_mux_pix_clk(struct device *dev, const char *name,
++ const char **parent_names, u8 num_parents, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_mux_flags);
++struct clk *clk_register_div_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_div_flags);
++struct clk *clk_register_gate_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_gate_flags);
++#endif /* __INCLUDE_IPU_PRV_H__ */
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/ipu_regs.h linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_regs.h
+--- linux-3.10.30.orig/drivers/mxc/ipu3/ipu_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/ipu_regs.h 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,719 @@
++/*
++ * Copyright (C) 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_regs.h
++ *
++ * @brief IPU Register definitions
++ *
++ * @ingroup IPU
++ */
++#ifndef __IPU_REGS_INCLUDED__
++#define __IPU_REGS_INCLUDED__
++
++enum imx_ipu_rev {
++ IPU_V3DEX = 2,
++ IPU_V3M,
++ IPU_V3H,
++};
++
++/*
++ * hw_rev 2: IPUV3DEX
++ * hw_rev 3: IPUV3M
++ * hw_rev 4: IPUV3H
++ */
++extern int g_ipu_hw_rev;
++
++#define IPU_MAX_VDI_IN_WIDTH ({g_ipu_hw_rev >= 3 ? \
++ (968) : \
++ (720); })
++#define IPU_DISP0_BASE 0x00000000
++#define IPU_MCU_T_DEFAULT 8
++#define IPU_DISP1_BASE ({g_ipu_hw_rev < 4 ? \
++ (IPU_MCU_T_DEFAULT << 25) : \
++ (0x00000000); })
++#define IPUV3DEX_REG_BASE 0x1E000000
++#define IPUV3M_REG_BASE 0x06000000
++#define IPUV3H_REG_BASE 0x00200000
++
++#define IPU_CM_REG_BASE 0x00000000
++#define IPU_IDMAC_REG_BASE 0x00008000
++#define IPU_ISP_REG_BASE 0x00010000
++#define IPU_DP_REG_BASE 0x00018000
++#define IPU_IC_REG_BASE 0x00020000
++#define IPU_IRT_REG_BASE 0x00028000
++#define IPU_CSI0_REG_BASE 0x00030000
++#define IPU_CSI1_REG_BASE 0x00038000
++#define IPU_DI0_REG_BASE 0x00040000
++#define IPU_DI1_REG_BASE 0x00048000
++#define IPU_SMFC_REG_BASE 0x00050000
++#define IPU_DC_REG_BASE 0x00058000
++#define IPU_DMFC_REG_BASE 0x00060000
++#define IPU_VDI_REG_BASE 0x00068000
++#define IPU_CPMEM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00100000) : \
++ (0x01000000); })
++#define IPU_LUT_REG_BASE 0x01020000
++#define IPU_SRM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00140000) : \
++ (0x01040000); })
++#define IPU_TPM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00160000) : \
++ (0x01060000); })
++#define IPU_DC_TMPL_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00180000) : \
++ (0x01080000); })
++#define IPU_ISP_TBPR_REG_BASE 0x010C0000
++
++/* Register addresses */
++/* IPU Common registers */
++#define IPU_CONF (0)
++
++#define IPU_SRM_PRI1 (0x00A0/4)
++#define IPU_SRM_PRI2 (0x00A4/4)
++#define IPU_FS_PROC_FLOW1 (0x00A8/4)
++#define IPU_FS_PROC_FLOW2 (0x00AC/4)
++#define IPU_FS_PROC_FLOW3 (0x00B0/4)
++#define IPU_FS_DISP_FLOW1 (0x00B4/4)
++#define IPU_FS_DISP_FLOW2 (0x00B8/4)
++#define IPU_SKIP (0x00BC/4)
++#define IPU_DISP_ALT_CONF (0x00C0/4)
++#define IPU_DISP_GEN (0x00C4/4)
++#define IPU_DISP_ALT1 (0x00C8/4)
++#define IPU_DISP_ALT2 (0x00CC/4)
++#define IPU_DISP_ALT3 (0x00D0/4)
++#define IPU_DISP_ALT4 (0x00D4/4)
++#define IPU_SNOOP (0x00D8/4)
++#define IPU_MEM_RST (0x00DC/4)
++#define IPU_PM (0x00E0/4)
++#define IPU_GPR (0x00E4/4)
++#define IPU_CHA_DB_MODE_SEL(ch) (0x0150/4 + (ch / 32))
++#define IPU_ALT_CHA_DB_MODE_SEL(ch) (0x0168/4 + (ch / 32))
++/*
++ * IPUv3D doesn't support triple buffer, so point
++ * IPU_CHA_TRB_MODE_SEL, IPU_CHA_TRIPLE_CUR_BUF and
++ * IPU_CHA_BUF2_RDY to readonly
++ * IPU_ALT_CUR_BUF0 for IPUv3D.
++ */
++#define IPU_CHA_TRB_MODE_SEL(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0178/4 + (ch / 32)) : \
++ (0x012C/4); })
++#define IPU_CHA_TRIPLE_CUR_BUF(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0258/4 + ((ch*2) / 32)) : \
++ (0x012C/4); })
++#define IPU_CHA_BUF2_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0288/4 + (ch / 32)) : \
++ (0x012C/4); })
++#define IPU_CHA_CUR_BUF(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x023C/4 + (ch / 32)) : \
++ (0x0124/4 + (ch / 32)); })
++#define IPU_ALT_CUR_BUF0 ({g_ipu_hw_rev >= 2 ? \
++ (0x0244/4) : \
++ (0x012C/4); })
++#define IPU_ALT_CUR_BUF1 ({g_ipu_hw_rev >= 2 ? \
++ (0x0248/4) : \
++ (0x0130/4); })
++#define IPU_SRM_STAT ({g_ipu_hw_rev >= 2 ? \
++ (0x024C/4) : \
++ (0x0134/4); })
++#define IPU_PROC_TASK_STAT ({g_ipu_hw_rev >= 2 ? \
++ (0x0250/4) : \
++ (0x0138/4); })
++#define IPU_DISP_TASK_STAT ({g_ipu_hw_rev >= 2 ? \
++ (0x0254/4) : \
++ (0x013C/4); })
++#define IPU_CHA_BUF0_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0268/4 + (ch / 32)) : \
++ (0x0140/4 + (ch / 32)); })
++#define IPU_CHA_BUF1_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0270/4 + (ch / 32)) : \
++ (0x0148/4 + (ch / 32)); })
++#define IPU_ALT_CHA_BUF0_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0278/4 + (ch / 32)) : \
++ (0x0158/4 + (ch / 32)); })
++#define IPU_ALT_CHA_BUF1_RDY(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0280/4 + (ch / 32)) : \
++ (0x0160/4 + (ch / 32)); })
++
++#define IPU_INT_CTRL(n) (0x003C/4 + ((n) - 1))
++#define IPU_INT_CTRL_IRQ(irq) IPU_INT_CTRL(((irq) / 32))
++#define IPU_INT_STAT_IRQ(irq) IPU_INT_STAT(((irq) / 32))
++#define IPU_INT_STAT(n) ({g_ipu_hw_rev >= 2 ? \
++ (0x0200/4 + ((n) - 1)) : \
++ (0x00E8/4 + ((n) - 1)); })
++
++#define IPUIRQ_2_STATREG(irq) (IPU_INT_STAT(1) + ((irq) / 32))
++#define IPUIRQ_2_CTRLREG(irq) (IPU_INT_CTRL(1) + ((irq) / 32))
++#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))
++
++#define VDI_FSIZE (0)
++#define VDI_C (0x0004/4)
++
++/* CMOS Sensor Interface Registers */
++#define CSI_SENS_CONF (0)
++#define CSI_SENS_FRM_SIZE (0x0004/4)
++#define CSI_ACT_FRM_SIZE (0x0008/4)
++#define CSI_OUT_FRM_CTRL (0x000C/4)
++#define CSI_TST_CTRL (0x0010/4)
++#define CSI_CCIR_CODE_1 (0x0014/4)
++#define CSI_CCIR_CODE_2 (0x0018/4)
++#define CSI_CCIR_CODE_3 (0x001C/4)
++#define CSI_MIPI_DI (0x0020/4)
++#define CSI_SKIP (0x0024/4)
++#define CSI_CPD_CTRL (0x0028/4)
++#define CSI_CPD_RC(n) (0x002C/4 + n)
++#define CSI_CPD_RS(n) (0x004C/4 + n)
++#define CSI_CPD_GRC(n) (0x005C/4 + n)
++#define CSI_CPD_GRS(n) (0x007C/4 + n)
++#define CSI_CPD_GBC(n) (0x008C/4 + n)
++#define CSI_CPD_GBS(n) (0x00AC/4 + n)
++#define CSI_CPD_BC(n) (0x00BC/4 + n)
++#define CSI_CPD_BS(n) (0x00DC/4 + n)
++#define CSI_CPD_OFFSET1 (0x00EC/4)
++#define CSI_CPD_OFFSET2 (0x00F0/4)
++
++/*SMFC Registers */
++#define SMFC_MAP (0)
++#define SMFC_WMC (0x0004/4)
++#define SMFC_BS (0x0008/4)
++
++/* Image Converter Registers */
++#define IC_CONF 0
++#define IC_PRP_ENC_RSC (0x0004/4)
++#define IC_PRP_VF_RSC (0x0008/4)
++#define IC_PP_RSC (0x000C/4)
++#define IC_CMBP_1 (0x0010/4)
++#define IC_CMBP_2 (0x0014/4)
++#define IC_IDMAC_1 (0x0018/4)
++#define IC_IDMAC_2 (0x001C/4)
++#define IC_IDMAC_3 (0x0020/4)
++#define IC_IDMAC_4 (0x0024/4)
++
++#define IDMAC_CONF (0x0000)
++#define IDMAC_CHA_EN(ch) (0x0004/4 + (ch/32))
++#define IDMAC_SEP_ALPHA (0x000C/4)
++#define IDMAC_ALT_SEP_ALPHA (0x0010/4)
++#define IDMAC_CHA_PRI(ch) (0x0014/4 + (ch/32))
++#define IDMAC_WM_EN(ch) (0x001C/4 + (ch/32))
++#define IDMAC_CH_LOCK_EN_1 ({g_ipu_hw_rev >= 2 ? \
++ (0x0024/4) : 0; })
++#define IDMAC_CH_LOCK_EN_2 ({g_ipu_hw_rev >= 2 ? \
++ (0x0028/4) : \
++ (0x0024/4); })
++#define IDMAC_SUB_ADDR_0 ({g_ipu_hw_rev >= 2 ? \
++ (0x002C/4) : \
++ (0x0028/4); })
++#define IDMAC_SUB_ADDR_1 ({g_ipu_hw_rev >= 2 ? \
++ (0x0030/4) : \
++ (0x002C/4); })
++#define IDMAC_SUB_ADDR_2 ({g_ipu_hw_rev >= 2 ? \
++ (0x0034/4) : \
++ (0x0030/4); })
++/*
++ * IPUv3D doesn't support IDMAC_SUB_ADDR_3 and IDMAC_SUB_ADDR_4,
++ * so point them to readonly IDMAC_CHA_BUSY1 for IPUv3D.
++ */
++#define IDMAC_SUB_ADDR_3 ({g_ipu_hw_rev >= 2 ? \
++ (0x0038/4) : \
++ (0x0040/4); })
++#define IDMAC_SUB_ADDR_4 ({g_ipu_hw_rev >= 2 ? \
++ (0x003c/4) : \
++ (0x0040/4); })
++#define IDMAC_BAND_EN(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0040/4 + (ch/32)) : \
++ (0x0034/4 + (ch/32)); })
++#define IDMAC_CHA_BUSY(ch) ({g_ipu_hw_rev >= 2 ? \
++ (0x0100/4 + (ch/32)) : \
++ (0x0040/4 + (ch/32)); })
++
++#define DI_GENERAL (0)
++#define DI_BS_CLKGEN0 (0x0004/4)
++#define DI_BS_CLKGEN1 (0x0008/4)
++
++#define DI_SW_GEN0(gen) (0x000C/4 + (gen - 1))
++#define DI_SW_GEN1(gen) (0x0030/4 + (gen - 1))
++#define DI_STP_REP(gen) (0x0148/4 + (gen - 1)/2)
++#define DI_SYNC_AS_GEN (0x0054/4)
++#define DI_DW_GEN(gen) (0x0058/4 + gen)
++#define DI_DW_SET(gen, set) (0x0088/4 + gen + 0xC*set)
++#define DI_SER_CONF (0x015C/4)
++#define DI_SSC (0x0160/4)
++#define DI_POL (0x0164/4)
++#define DI_AW0 (0x0168/4)
++#define DI_AW1 (0x016C/4)
++#define DI_SCR_CONF (0x0170/4)
++#define DI_STAT (0x0174/4)
++
++#define DMFC_RD_CHAN (0)
++#define DMFC_WR_CHAN (0x0004/4)
++#define DMFC_WR_CHAN_DEF (0x0008/4)
++#define DMFC_DP_CHAN (0x000C/4)
++#define DMFC_DP_CHAN_DEF (0x0010/4)
++#define DMFC_GENERAL1 (0x0014/4)
++#define DMFC_GENERAL2 (0x0018/4)
++#define DMFC_IC_CTRL (0x001C/4)
++#define DMFC_STAT (0x0020/4)
++
++#define DC_MAP_CONF_PTR(n) (0x0108/4 + n/2)
++#define DC_MAP_CONF_VAL(n) (0x0144/4 + n/2)
++
++#define _RL_CH_2_OFFSET(ch) ((ch == 0) ? 8 : ( \
++ (ch == 1) ? 0x24 : ( \
++ (ch == 2) ? 0x40 : ( \
++ (ch == 5) ? 0x64 : ( \
++ (ch == 6) ? 0x80 : ( \
++ (ch == 8) ? 0x9C : ( \
++ (ch == 9) ? 0xBC : (-1))))))))
++#define DC_RL_CH(ch, evt) (_RL_CH_2_OFFSET(ch)/4 + evt/2)
++
++#define DC_EVT_NF 0
++#define DC_EVT_NL 1
++#define DC_EVT_EOF 2
++#define DC_EVT_NFIELD 3
++#define DC_EVT_EOL 4
++#define DC_EVT_EOFIELD 5
++#define DC_EVT_NEW_ADDR 6
++#define DC_EVT_NEW_CHAN 7
++#define DC_EVT_NEW_DATA 8
++
++#define DC_EVT_NEW_ADDR_W_0 0
++#define DC_EVT_NEW_ADDR_W_1 1
++#define DC_EVT_NEW_CHAN_W_0 2
++#define DC_EVT_NEW_CHAN_W_1 3
++#define DC_EVT_NEW_DATA_W_0 4
++#define DC_EVT_NEW_DATA_W_1 5
++#define DC_EVT_NEW_ADDR_R_0 6
++#define DC_EVT_NEW_ADDR_R_1 7
++#define DC_EVT_NEW_CHAN_R_0 8
++#define DC_EVT_NEW_CHAN_R_1 9
++#define DC_EVT_NEW_DATA_R_0 10
++#define DC_EVT_NEW_DATA_R_1 11
++#define DC_EVEN_UGDE0 12
++#define DC_ODD_UGDE0 13
++#define DC_EVEN_UGDE1 14
++#define DC_ODD_UGDE1 15
++#define DC_EVEN_UGDE2 16
++#define DC_ODD_UGDE2 17
++#define DC_EVEN_UGDE3 18
++#define DC_ODD_UGDE3 19
++
++#define dc_ch_offset(ch) \
++({ \
++ const u8 _offset[] = { \
++ 0, 0x1C, 0x38, 0x54, 0x58, 0x5C, 0x78, 0, 0x94, 0xB4}; \
++ _offset[ch]; \
++})
++#define DC_WR_CH_CONF(ch) (dc_ch_offset(ch)/4)
++#define DC_WR_CH_ADDR(ch) (dc_ch_offset(ch)/4 + 4/4)
++
++#define DC_WR_CH_CONF_1 (0x001C/4)
++#define DC_WR_CH_ADDR_1 (0x0020/4)
++#define DC_WR_CH_CONF_5 (0x005C/4)
++#define DC_WR_CH_ADDR_5 (0x0060/4)
++#define DC_GEN (0x00D4/4)
++#define DC_DISP_CONF1(disp) (0x00D8/4 + disp)
++#define DC_DISP_CONF2(disp) (0x00E8/4 + disp)
++#define DC_STAT (0x01C8/4)
++#define DC_UGDE_0(evt) (0x0174/4 + evt*4)
++#define DC_UGDE_1(evt) (0x0178/4 + evt*4)
++#define DC_UGDE_2(evt) (0x017C/4 + evt*4)
++#define DC_UGDE_3(evt) (0x0180/4 + evt*4)
++
++#define DP_SYNC 0
++#define DP_ASYNC0 0x60
++#define DP_ASYNC1 0xBC
++#define DP_COM_CONF(flow) (flow/4)
++#define DP_GRAPH_WIND_CTRL(flow) (0x0004/4 + flow/4)
++#define DP_FG_POS(flow) (0x0008/4 + flow/4)
++#define DP_GAMMA_C(flow, i) (0x0014/4 + flow/4 + i)
++#define DP_GAMMA_S(flow, i) (0x0034/4 + flow/4 + i)
++#define DP_CSC_A_0(flow) (0x0044/4 + flow/4)
++#define DP_CSC_A_1(flow) (0x0048/4 + flow/4)
++#define DP_CSC_A_2(flow) (0x004C/4 + flow/4)
++#define DP_CSC_A_3(flow) (0x0050/4 + flow/4)
++#define DP_CSC_0(flow) (0x0054/4 + flow/4)
++#define DP_CSC_1(flow) (0x0058/4 + flow/4)
++
++enum {
++ IPU_CONF_CSI0_EN = 0x00000001,
++ IPU_CONF_CSI1_EN = 0x00000002,
++ IPU_CONF_IC_EN = 0x00000004,
++ IPU_CONF_ROT_EN = 0x00000008,
++ IPU_CONF_ISP_EN = 0x00000010,
++ IPU_CONF_DP_EN = 0x00000020,
++ IPU_CONF_DI0_EN = 0x00000040,
++ IPU_CONF_DI1_EN = 0x00000080,
++ IPU_CONF_DMFC_EN = 0x00000400,
++ IPU_CONF_SMFC_EN = 0x00000100,
++ IPU_CONF_DC_EN = 0x00000200,
++ IPU_CONF_VDI_EN = 0x00001000,
++ IPU_CONF_IDMAC_DIS = 0x00400000,
++ IPU_CONF_IC_DMFC_SEL = 0x02000000,
++ IPU_CONF_IC_DMFC_SYNC = 0x04000000,
++ IPU_CONF_VDI_DMFC_SYNC = 0x08000000,
++ IPU_CONF_CSI0_DATA_SOURCE = 0x10000000,
++ IPU_CONF_CSI0_DATA_SOURCE_OFFSET = 28,
++ IPU_CONF_CSI1_DATA_SOURCE = 0x20000000,
++ IPU_CONF_IC_INPUT = 0x40000000,
++ IPU_CONF_CSI_SEL = 0x80000000,
++
++ DI0_COUNTER_RELEASE = 0x01000000,
++ DI1_COUNTER_RELEASE = 0x02000000,
++
++ FS_PRPVF_ROT_SRC_SEL_MASK = 0x00000F00,
++ FS_PRPVF_ROT_SRC_SEL_OFFSET = 8,
++ FS_PRPENC_ROT_SRC_SEL_MASK = 0x0000000F,
++ FS_PRPENC_ROT_SRC_SEL_OFFSET = 0,
++ FS_PP_ROT_SRC_SEL_MASK = 0x000F0000,
++ FS_PP_ROT_SRC_SEL_OFFSET = 16,
++ FS_PP_SRC_SEL_MASK = 0x0000F000,
++ FS_PP_SRC_SEL_VDOA = 0x00008000,
++ FS_PP_SRC_SEL_OFFSET = 12,
++ FS_PRP_SRC_SEL_MASK = 0x0F000000,
++ FS_PRP_SRC_SEL_OFFSET = 24,
++ FS_VF_IN_VALID = 0x80000000,
++ FS_ENC_IN_VALID = 0x40000000,
++ FS_VDI_SRC_SEL_MASK = 0x30000000,
++ FS_VDI_SRC_SEL_VDOA = 0x20000000,
++ FS_VDOA_DEST_SEL_MASK = 0x00030000,
++ FS_VDOA_DEST_SEL_VDI = 0x00020000,
++ FS_VDOA_DEST_SEL_IC = 0x00010000,
++ FS_VDI_SRC_SEL_OFFSET = 28,
++
++
++ FS_PRPENC_DEST_SEL_MASK = 0x0000000F,
++ FS_PRPENC_DEST_SEL_OFFSET = 0,
++ FS_PRPVF_DEST_SEL_MASK = 0x000000F0,
++ FS_PRPVF_DEST_SEL_OFFSET = 4,
++ FS_PRPVF_ROT_DEST_SEL_MASK = 0x00000F00,
++ FS_PRPVF_ROT_DEST_SEL_OFFSET = 8,
++ FS_PP_DEST_SEL_MASK = 0x0000F000,
++ FS_PP_DEST_SEL_OFFSET = 12,
++ FS_PP_ROT_DEST_SEL_MASK = 0x000F0000,
++ FS_PP_ROT_DEST_SEL_OFFSET = 16,
++ FS_PRPENC_ROT_DEST_SEL_MASK = 0x00F00000,
++ FS_PRPENC_ROT_DEST_SEL_OFFSET = 20,
++
++ FS_SMFC0_DEST_SEL_MASK = 0x0000000F,
++ FS_SMFC0_DEST_SEL_OFFSET = 0,
++ FS_SMFC1_DEST_SEL_MASK = 0x00000070,
++ FS_SMFC1_DEST_SEL_OFFSET = 4,
++ FS_SMFC2_DEST_SEL_MASK = 0x00000780,
++ FS_SMFC2_DEST_SEL_OFFSET = 7,
++ FS_SMFC3_DEST_SEL_MASK = 0x00003800,
++ FS_SMFC3_DEST_SEL_OFFSET = 11,
++
++ FS_DC1_SRC_SEL_MASK = 0x00F00000,
++ FS_DC1_SRC_SEL_OFFSET = 20,
++ FS_DC2_SRC_SEL_MASK = 0x000F0000,
++ FS_DC2_SRC_SEL_OFFSET = 16,
++ FS_DP_SYNC0_SRC_SEL_MASK = 0x0000000F,
++ FS_DP_SYNC0_SRC_SEL_OFFSET = 0,
++ FS_DP_SYNC1_SRC_SEL_MASK = 0x000000F0,
++ FS_DP_SYNC1_SRC_SEL_OFFSET = 4,
++ FS_DP_ASYNC0_SRC_SEL_MASK = 0x00000F00,
++ FS_DP_ASYNC0_SRC_SEL_OFFSET = 8,
++ FS_DP_ASYNC1_SRC_SEL_MASK = 0x0000F000,
++ FS_DP_ASYNC1_SRC_SEL_OFFSET = 12,
++
++ FS_AUTO_REF_PER_MASK = 0,
++ FS_AUTO_REF_PER_OFFSET = 16,
++
++ TSTAT_VF_MASK = 0x0000000C,
++ TSTAT_VF_OFFSET = 2,
++ TSTAT_VF_ROT_MASK = 0x00000300,
++ TSTAT_VF_ROT_OFFSET = 8,
++ TSTAT_ENC_MASK = 0x00000003,
++ TSTAT_ENC_OFFSET = 0,
++ TSTAT_ENC_ROT_MASK = 0x000000C0,
++ TSTAT_ENC_ROT_OFFSET = 6,
++ TSTAT_PP_MASK = 0x00000030,
++ TSTAT_PP_OFFSET = 4,
++ TSTAT_PP_ROT_MASK = 0x00000C00,
++ TSTAT_PP_ROT_OFFSET = 10,
++
++ TASK_STAT_IDLE = 0,
++ TASK_STAT_ACTIVE = 1,
++ TASK_STAT_WAIT4READY = 2,
++
++ /* Image Converter Register bits */
++ IC_CONF_PRPENC_EN = 0x00000001,
++ IC_CONF_PRPENC_CSC1 = 0x00000002,
++ IC_CONF_PRPENC_ROT_EN = 0x00000004,
++ IC_CONF_PRPVF_EN = 0x00000100,
++ IC_CONF_PRPVF_CSC1 = 0x00000200,
++ IC_CONF_PRPVF_CSC2 = 0x00000400,
++ IC_CONF_PRPVF_CMB = 0x00000800,
++ IC_CONF_PRPVF_ROT_EN = 0x00001000,
++ IC_CONF_PP_EN = 0x00010000,
++ IC_CONF_PP_CSC1 = 0x00020000,
++ IC_CONF_PP_CSC2 = 0x00040000,
++ IC_CONF_PP_CMB = 0x00080000,
++ IC_CONF_PP_ROT_EN = 0x00100000,
++ IC_CONF_IC_GLB_LOC_A = 0x10000000,
++ IC_CONF_KEY_COLOR_EN = 0x20000000,
++ IC_CONF_RWS_EN = 0x40000000,
++ IC_CONF_CSI_MEM_WR_EN = 0x80000000,
++
++ IC_RSZ_MAX_RESIZE_RATIO = 0x00004000,
++
++ IC_IDMAC_1_CB0_BURST_16 = 0x00000001,
++ IC_IDMAC_1_CB1_BURST_16 = 0x00000002,
++ IC_IDMAC_1_CB2_BURST_16 = 0x00000004,
++ IC_IDMAC_1_CB3_BURST_16 = 0x00000008,
++ IC_IDMAC_1_CB4_BURST_16 = 0x00000010,
++ IC_IDMAC_1_CB5_BURST_16 = 0x00000020,
++ IC_IDMAC_1_CB6_BURST_16 = 0x00000040,
++ IC_IDMAC_1_CB7_BURST_16 = 0x00000080,
++ IC_IDMAC_1_PRPENC_ROT_MASK = 0x00003800,
++ IC_IDMAC_1_PRPENC_ROT_OFFSET = 11,
++ IC_IDMAC_1_PRPVF_ROT_MASK = 0x0001C000,
++ IC_IDMAC_1_PRPVF_ROT_OFFSET = 14,
++ IC_IDMAC_1_PP_ROT_MASK = 0x000E0000,
++ IC_IDMAC_1_PP_ROT_OFFSET = 17,
++ IC_IDMAC_1_PP_FLIP_RS = 0x00400000,
++ IC_IDMAC_1_PRPVF_FLIP_RS = 0x00200000,
++ IC_IDMAC_1_PRPENC_FLIP_RS = 0x00100000,
++
++ IC_IDMAC_2_PRPENC_HEIGHT_MASK = 0x000003FF,
++ IC_IDMAC_2_PRPENC_HEIGHT_OFFSET = 0,
++ IC_IDMAC_2_PRPVF_HEIGHT_MASK = 0x000FFC00,
++ IC_IDMAC_2_PRPVF_HEIGHT_OFFSET = 10,
++ IC_IDMAC_2_PP_HEIGHT_MASK = 0x3FF00000,
++ IC_IDMAC_2_PP_HEIGHT_OFFSET = 20,
++
++ IC_IDMAC_3_PRPENC_WIDTH_MASK = 0x000003FF,
++ IC_IDMAC_3_PRPENC_WIDTH_OFFSET = 0,
++ IC_IDMAC_3_PRPVF_WIDTH_MASK = 0x000FFC00,
++ IC_IDMAC_3_PRPVF_WIDTH_OFFSET = 10,
++ IC_IDMAC_3_PP_WIDTH_MASK = 0x3FF00000,
++ IC_IDMAC_3_PP_WIDTH_OFFSET = 20,
++
++ CSI_SENS_CONF_DATA_FMT_SHIFT = 8,
++ CSI_SENS_CONF_DATA_FMT_MASK = 0x00000700,
++ CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0L,
++ CSI_SENS_CONF_DATA_FMT_YUV422_YUYV = 1L,
++ CSI_SENS_CONF_DATA_FMT_YUV422_UYVY = 2L,
++ CSI_SENS_CONF_DATA_FMT_BAYER = 3L,
++ CSI_SENS_CONF_DATA_FMT_RGB565 = 4L,
++ CSI_SENS_CONF_DATA_FMT_RGB555 = 5L,
++ CSI_SENS_CONF_DATA_FMT_RGB444 = 6L,
++ CSI_SENS_CONF_DATA_FMT_JPEG = 7L,
++
++ CSI_SENS_CONF_VSYNC_POL_SHIFT = 0,
++ CSI_SENS_CONF_HSYNC_POL_SHIFT = 1,
++ CSI_SENS_CONF_DATA_POL_SHIFT = 2,
++ CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3,
++ CSI_SENS_CONF_SENS_PRTCL_MASK = 0x00000070L,
++ CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4,
++ CSI_SENS_CONF_PACK_TIGHT_SHIFT = 7,
++ CSI_SENS_CONF_DATA_WIDTH_SHIFT = 11,
++ CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15,
++ CSI_SENS_CONF_DIVRATIO_SHIFT = 16,
++
++ CSI_SENS_CONF_DIVRATIO_MASK = 0x00FF0000L,
++ CSI_SENS_CONF_DATA_DEST_SHIFT = 24,
++ CSI_SENS_CONF_DATA_DEST_MASK = 0x07000000L,
++ CSI_SENS_CONF_JPEG8_EN_SHIFT = 27,
++ CSI_SENS_CONF_JPEG_EN_SHIFT = 28,
++ CSI_SENS_CONF_FORCE_EOF_SHIFT = 29,
++ CSI_SENS_CONF_DATA_EN_POL_SHIFT = 31,
++
++ CSI_DATA_DEST_ISP = 1L,
++ CSI_DATA_DEST_IC = 2L,
++ CSI_DATA_DEST_IDMAC = 4L,
++
++ CSI_CCIR_ERR_DET_EN = 0x01000000L,
++ CSI_HORI_DOWNSIZE_EN = 0x80000000L,
++ CSI_VERT_DOWNSIZE_EN = 0x40000000L,
++ CSI_TEST_GEN_MODE_EN = 0x01000000L,
++
++ CSI_HSC_MASK = 0x1FFF0000,
++ CSI_HSC_SHIFT = 16,
++ CSI_VSC_MASK = 0x00000FFF,
++ CSI_VSC_SHIFT = 0,
++
++ CSI_TEST_GEN_R_MASK = 0x000000FFL,
++ CSI_TEST_GEN_R_SHIFT = 0,
++ CSI_TEST_GEN_G_MASK = 0x0000FF00L,
++ CSI_TEST_GEN_G_SHIFT = 8,
++ CSI_TEST_GEN_B_MASK = 0x00FF0000L,
++ CSI_TEST_GEN_B_SHIFT = 16,
++
++ CSI_MIPI_DI0_MASK = 0x000000FFL,
++ CSI_MIPI_DI0_SHIFT = 0,
++ CSI_MIPI_DI1_MASK = 0x0000FF00L,
++ CSI_MIPI_DI1_SHIFT = 8,
++ CSI_MIPI_DI2_MASK = 0x00FF0000L,
++ CSI_MIPI_DI2_SHIFT = 16,
++ CSI_MIPI_DI3_MASK = 0xFF000000L,
++ CSI_MIPI_DI3_SHIFT = 24,
++
++ CSI_MAX_RATIO_SKIP_ISP_MASK = 0x00070000L,
++ CSI_MAX_RATIO_SKIP_ISP_SHIFT = 16,
++ CSI_SKIP_ISP_MASK = 0x00F80000L,
++ CSI_SKIP_ISP_SHIFT = 19,
++ CSI_MAX_RATIO_SKIP_SMFC_MASK = 0x00000007L,
++ CSI_MAX_RATIO_SKIP_SMFC_SHIFT = 0,
++ CSI_SKIP_SMFC_MASK = 0x000000F8L,
++ CSI_SKIP_SMFC_SHIFT = 3,
++ CSI_ID_2_SKIP_MASK = 0x00000300L,
++ CSI_ID_2_SKIP_SHIFT = 8,
++
++ CSI_COLOR_FIRST_ROW_MASK = 0x00000002L,
++ CSI_COLOR_FIRST_COMP_MASK = 0x00000001L,
++
++ SMFC_MAP_CH0_MASK = 0x00000007L,
++ SMFC_MAP_CH0_SHIFT = 0,
++ SMFC_MAP_CH1_MASK = 0x00000038L,
++ SMFC_MAP_CH1_SHIFT = 3,
++ SMFC_MAP_CH2_MASK = 0x000001C0L,
++ SMFC_MAP_CH2_SHIFT = 6,
++ SMFC_MAP_CH3_MASK = 0x00000E00L,
++ SMFC_MAP_CH3_SHIFT = 9,
++
++ SMFC_WM0_SET_MASK = 0x00000007L,
++ SMFC_WM0_SET_SHIFT = 0,
++ SMFC_WM1_SET_MASK = 0x000001C0L,
++ SMFC_WM1_SET_SHIFT = 6,
++ SMFC_WM2_SET_MASK = 0x00070000L,
++ SMFC_WM2_SET_SHIFT = 16,
++ SMFC_WM3_SET_MASK = 0x01C00000L,
++ SMFC_WM3_SET_SHIFT = 22,
++
++ SMFC_WM0_CLR_MASK = 0x00000038L,
++ SMFC_WM0_CLR_SHIFT = 3,
++ SMFC_WM1_CLR_MASK = 0x00000E00L,
++ SMFC_WM1_CLR_SHIFT = 9,
++ SMFC_WM2_CLR_MASK = 0x00380000L,
++ SMFC_WM2_CLR_SHIFT = 19,
++ SMFC_WM3_CLR_MASK = 0x0E000000L,
++ SMFC_WM3_CLR_SHIFT = 25,
++
++ SMFC_BS0_MASK = 0x0000000FL,
++ SMFC_BS0_SHIFT = 0,
++ SMFC_BS1_MASK = 0x000000F0L,
++ SMFC_BS1_SHIFT = 4,
++ SMFC_BS2_MASK = 0x00000F00L,
++ SMFC_BS2_SHIFT = 8,
++ SMFC_BS3_MASK = 0x0000F000L,
++ SMFC_BS3_SHIFT = 12,
++
++ PF_CONF_TYPE_MASK = 0x00000007,
++ PF_CONF_TYPE_SHIFT = 0,
++ PF_CONF_PAUSE_EN = 0x00000010,
++ PF_CONF_RESET = 0x00008000,
++ PF_CONF_PAUSE_ROW_MASK = 0x00FF0000,
++ PF_CONF_PAUSE_ROW_SHIFT = 16,
++
++ DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
++ DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
++
++ DI_GEN_DI_CLK_EXT = 0x100000,
++ DI_GEN_POLARITY_DISP_CLK = 0x00020000,
++ DI_GEN_POLARITY_1 = 0x00000001,
++ DI_GEN_POLARITY_2 = 0x00000002,
++ DI_GEN_POLARITY_3 = 0x00000004,
++ DI_GEN_POLARITY_4 = 0x00000008,
++ DI_GEN_POLARITY_5 = 0x00000010,
++ DI_GEN_POLARITY_6 = 0x00000020,
++ DI_GEN_POLARITY_7 = 0x00000040,
++ DI_GEN_POLARITY_8 = 0x00000080,
++
++ DI_POL_DRDY_DATA_POLARITY = 0x00000080,
++ DI_POL_DRDY_POLARITY_15 = 0x00000010,
++
++ DI_VSYNC_SEL_OFFSET = 13,
++
++ DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
++ DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
++ DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
++ DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
++ DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
++ DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
++
++ DC_UGDE_0_ODD_EN = 0x02000000,
++ DC_UGDE_0_ID_CODED_MASK = 0x00000007,
++ DC_UGDE_0_ID_CODED_OFFSET = 0,
++ DC_UGDE_0_EV_PRIORITY_MASK = 0x00000078,
++ DC_UGDE_0_EV_PRIORITY_OFFSET = 3,
++
++ DP_COM_CONF_FG_EN = 0x00000001,
++ DP_COM_CONF_GWSEL = 0x00000002,
++ DP_COM_CONF_GWAM = 0x00000004,
++ DP_COM_CONF_GWCKE = 0x00000008,
++ DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
++ DP_COM_CONF_CSC_DEF_OFFSET = 8,
++ DP_COM_CONF_CSC_DEF_FG = 0x00000300,
++ DP_COM_CONF_CSC_DEF_BG = 0x00000200,
++ DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
++ DP_COM_CONF_GAMMA_EN = 0x00001000,
++ DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
++
++ DI_SER_CONF_LLA_SER_ACCESS = 0x00000020,
++ DI_SER_CONF_SERIAL_CLK_POL = 0x00000010,
++ DI_SER_CONF_SERIAL_DATA_POL = 0x00000008,
++ DI_SER_CONF_SERIAL_RS_POL = 0x00000004,
++ DI_SER_CONF_SERIAL_CS_POL = 0x00000002,
++ DI_SER_CONF_WAIT4SERIAL = 0x00000001,
++
++ VDI_C_CH_420 = 0x00000000,
++ VDI_C_CH_422 = 0x00000002,
++ VDI_C_MOT_SEL_FULL = 0x00000008,
++ VDI_C_MOT_SEL_LOW = 0x00000004,
++ VDI_C_MOT_SEL_MED = 0x00000000,
++ VDI_C_BURST_SIZE1_4 = 0x00000030,
++ VDI_C_BURST_SIZE2_4 = 0x00000300,
++ VDI_C_BURST_SIZE3_4 = 0x00003000,
++ VDI_C_BURST_SIZE_MASK = 0xF,
++ VDI_C_BURST_SIZE1_OFFSET = 4,
++ VDI_C_BURST_SIZE2_OFFSET = 8,
++ VDI_C_BURST_SIZE3_OFFSET = 12,
++ VDI_C_VWM1_SET_1 = 0x00000000,
++ VDI_C_VWM1_SET_2 = 0x00010000,
++ VDI_C_VWM1_CLR_2 = 0x00080000,
++ VDI_C_VWM3_SET_1 = 0x00000000,
++ VDI_C_VWM3_SET_2 = 0x00400000,
++ VDI_C_VWM3_CLR_2 = 0x02000000,
++ VDI_C_TOP_FIELD_MAN_1 = 0x40000000,
++ VDI_C_TOP_FIELD_AUTO_1 = 0x80000000,
++};
++
++enum di_pins {
++ DI_PIN11 = 0,
++ DI_PIN12 = 1,
++ DI_PIN13 = 2,
++ DI_PIN14 = 3,
++ DI_PIN15 = 4,
++ DI_PIN16 = 5,
++ DI_PIN17 = 6,
++ DI_PIN_CS = 7,
++
++ DI_PIN_SER_CLK = 0,
++ DI_PIN_SER_RS = 1,
++};
++
++enum di_sync_wave {
++ DI_SYNC_NONE = -1,
++ DI_SYNC_CLK = 0,
++ DI_SYNC_INT_HSYNC = 1,
++ DI_SYNC_HSYNC = 2,
++ DI_SYNC_VSYNC = 3,
++ DI_SYNC_DE = 5,
++};
++
++/* DC template opcodes */
++#define WROD(lf) (0x18 | (lf << 1))
++#define WRG (0x01)
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/Kconfig linux-linaro-stable-mx6/drivers/mxc/ipu3/Kconfig
+--- linux-3.10.30.orig/drivers/mxc/ipu3/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/Kconfig 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,2 @@
++config MXC_IPU_V3
++ bool
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/Makefile linux-linaro-stable-mx6/drivers/mxc/ipu3/Makefile
+--- linux-3.10.30.orig/drivers/mxc/ipu3/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/Makefile 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,4 @@
++obj-$(CONFIG_MXC_IPU_V3) = mxc_ipu.o
++
++mxc_ipu-objs := ipu_common.o ipu_ic.o ipu_disp.o ipu_capture.o ipu_device.o \
++ ipu_calc_stripes_sizes.o vdoa.o ipu_pixel_clk.o
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/vdoa.c linux-linaro-stable-mx6/drivers/mxc/ipu3/vdoa.c
+--- linux-3.10.30.orig/drivers/mxc/ipu3/vdoa.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/vdoa.c 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,543 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ipu.h>
++#include <linux/genalloc.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++
++#include "vdoa.h"
++/* 6band(3field* double buffer) * (width*2) * bandline(8)
++ = 6x1024x2x8 = 96k or 72k(1.5byte) */
++#define MAX_VDOA_IRAM_SIZE (1024*96)
++#define VDOA_IRAM_SIZE (1024*72)
++
++#define VDOAC_BAND_HEIGHT_32LINES (32)
++#define VDOAC_BAND_HEIGHT_16LINES (16)
++#define VDOAC_BAND_HEIGHT_8LINES (8)
++#define VDOAC_THREE_FRAMES (0x1 << 2)
++#define VDOAC_SYNC_BAND_MODE (0x1 << 3)
++#define VDOAC_SCAN_ORDER_INTERLACED (0x1 << 4)
++#define VDOAC_PFS_YUYV (0x1 << 5)
++#define VDOAC_IPU_SEL_1 (0x1 << 6)
++#define VDOAFP_FH_MASK (0x1FFF)
++#define VDOAFP_FH_SHIFT (16)
++#define VDOAFP_FW_MASK (0x3FFF)
++#define VDOAFP_FW_SHIFT (0)
++#define VDOASL_VSLY_MASK (0x3FFF)
++#define VDOASL_VSLY_SHIFT (16)
++#define VDOASL_ISLY_MASK (0x7FFF)
++#define VDOASL_ISLY_SHIFT (0)
++#define VDOASRR_START_XFER (0x2)
++#define VDOASRR_SWRST (0x1)
++#define VDOAIEIST_TRANSFER_ERR (0x2)
++#define VDOAIEIST_TRANSFER_END (0x1)
++
++#define VDOAC (0x0) /* Control Register */
++#define VDOASRR (0x4) /* Start and Reset Register */
++#define VDOAIE (0x8) /* Interrupt Enable Register */
++#define VDOAIST (0xc) /* Interrupt Status Register */
++#define VDOAFP (0x10) /* Frame Parameters Register */
++#define VDOAIEBA00 (0x14) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA01 (0x18) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA02 (0x1c) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA10 (0x20) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA11 (0x24) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA12 (0x28) /* External Buffer n Frame m Address Register */
++#define VDOASL (0x2c) /* IPU Stride Line Register */
++#define VDOAIUBO (0x30) /* IPU Chroma Buffer Offset Register */
++#define VDOAVEBA0 (0x34) /* External Buffer m Address Register */
++#define VDOAVEBA1 (0x38) /* External Buffer m Address Register */
++#define VDOAVEBA2 (0x3c) /* External Buffer m Address Register */
++#define VDOAVUBO (0x40) /* VPU Chroma Buffer Offset */
++#define VDOASR (0x44) /* Status Register */
++#define VDOATD (0x48) /* Test Debug Register */
++
++
++enum {
++ VDOA_INIT = 0x1,
++ VDOA_GET = 0x2,
++ VDOA_SETUP = 0x4,
++ VDOA_GET_OBUF = 0x8,
++ VDOA_START = 0x10,
++ VDOA_INIRQ = 0x20,
++ VDOA_STOP = 0x40,
++ VDOA_PUT = VDOA_INIT,
++};
++
++enum {
++ VDOA_NULL = 0,
++ VDOA_FRAME = 1,
++ VDOA_PREV_FIELD = 2,
++ VDOA_CURR_FIELD = 3,
++ VDOA_NEXT_FIELD = 4,
++};
++
++#define CHECK_STATE(expect, retcode) \
++do { \
++ if (!((expect) & vdoa->state)) { \
++ dev_err(vdoa->dev, "ERR: %s state:0x%x, expect:0x%x.\n",\
++ __func__, vdoa->state, (expect)); \
++ retcode; \
++ } \
++} while (0)
++
++#define CHECK_NULL_PTR(ptr) \
++do { \
++ pr_debug("vdoa_ptr:0x%p in %s state:0x%x.\n", \
++ vdoa, __func__, vdoa->state); \
++ if (NULL == (ptr)) { \
++ pr_err("ERR vdoa: %s state:0x%x null ptr.\n", \
++ __func__, vdoa->state); \
++ } \
++} while (0)
++
++struct vdoa_info {
++ int state;
++ struct device *dev;
++ struct clk *vdoa_clk;
++ void __iomem *reg_base;
++ struct gen_pool *iram_pool;
++ unsigned long iram_base;
++ unsigned long iram_paddr;
++ int irq;
++ int field;
++ struct completion comp;
++};
++
++static struct vdoa_info *g_vdoa;
++static unsigned long iram_size;
++static DEFINE_MUTEX(vdoa_lock);
++
++static inline void vdoa_read_register(struct vdoa_info *vdoa,
++ u32 reg, u32 *val)
++{
++ *val = ioread32(vdoa->reg_base + reg);
++ dev_dbg(vdoa->dev, "read_reg:0x%02x, val:0x%08x.\n", reg, *val);
++}
++
++static inline void vdoa_write_register(struct vdoa_info *vdoa,
++ u32 reg, u32 val)
++{
++ iowrite32(val, vdoa->reg_base + reg);
++ dev_dbg(vdoa->dev, "\t\twrite_reg:0x%02x, val:0x%08x.\n", reg, val);
++}
++
++static void dump_registers(struct vdoa_info *vdoa)
++{
++ int i;
++ u32 data;
++
++ for (i = VDOAC; i < VDOATD; i += 4)
++ vdoa_read_register(vdoa, i, &data);
++}
++
++int vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params)
++{
++ int band_size;
++ int total_band_size = 0;
++ int ipu_stride;
++ u32 data;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET | VDOA_GET_OBUF | VDOA_STOP, return -EINVAL);
++ if (VDOA_GET == vdoa->state) {
++ dev_dbg(vdoa->dev, "w:%d, h:%d.\n",
++ params->width, params->height);
++ data = (params->band_lines == VDOAC_BAND_HEIGHT_32LINES) ? 2 :
++ ((params->band_lines == VDOAC_BAND_HEIGHT_16LINES) ?
++ 1 : 0);
++ data |= params->scan_order ? VDOAC_SCAN_ORDER_INTERLACED : 0;
++ data |= params->band_mode ? VDOAC_SYNC_BAND_MODE : 0;
++ data |= params->pfs ? VDOAC_PFS_YUYV : 0;
++ data |= params->ipu_num ? VDOAC_IPU_SEL_1 : 0;
++ vdoa_write_register(vdoa, VDOAC, data);
++
++ data = ((params->width & VDOAFP_FW_MASK) << VDOAFP_FW_SHIFT) |
++ ((params->height & VDOAFP_FH_MASK) << VDOAFP_FH_SHIFT);
++ vdoa_write_register(vdoa, VDOAFP, data);
++
++ ipu_stride = params->pfs ? params->width << 1 : params->width;
++ data = ((params->vpu_stride & VDOASL_VSLY_MASK) <<
++ VDOASL_VSLY_SHIFT) |
++ ((ipu_stride & VDOASL_ISLY_MASK) << VDOASL_ISLY_SHIFT);
++ vdoa_write_register(vdoa, VDOASL, data);
++
++ dev_dbg(vdoa->dev, "band_mode:%d, band_line:%d, base:0x%lx.\n",
++ params->band_mode, params->band_lines, vdoa->iram_paddr);
++ }
++ /*
++ * band size = (luma_per_line + chroma_per_line) * bandLines
++ * = width * (3/2 or 2) * bandLines
++ * double buffer mode used.
++ */
++ if (params->pfs)
++ band_size = (params->width << 1) * params->band_lines;
++ else
++ band_size = ((params->width * 3) >> 1) *
++ params->band_lines;
++ if (params->interlaced) {
++ total_band_size = 6 * band_size; /* 3 frames*double buffer */
++ if (iram_size < total_band_size) {
++ dev_err(vdoa->dev, "iram_size:0x%lx is smaller than "
++ "request:0x%x!\n", iram_size, total_band_size);
++ return -EINVAL;
++ }
++ if (params->vfield_buf.prev_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA00,
++ vdoa->iram_paddr);
++ vdoa_write_register(vdoa, VDOAIEBA10,
++ vdoa->iram_paddr + band_size);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA00,
++ params->ieba0);
++ vdoa_write_register(vdoa, VDOAVEBA0,
++ params->vfield_buf.prev_veba);
++ vdoa->field = VDOA_PREV_FIELD;
++ }
++ if (params->vfield_buf.cur_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA01,
++ vdoa->iram_paddr + band_size * 2);
++ vdoa_write_register(vdoa, VDOAIEBA11,
++ vdoa->iram_paddr + band_size * 3);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA01,
++ params->ieba1);
++ vdoa_write_register(vdoa, VDOAVEBA1,
++ params->vfield_buf.cur_veba);
++ vdoa->field = VDOA_CURR_FIELD;
++ }
++ if (params->vfield_buf.next_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA02,
++ vdoa->iram_paddr + band_size * 4);
++ vdoa_write_register(vdoa, VDOAIEBA12,
++ vdoa->iram_paddr + band_size * 5);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA02,
++ params->ieba2);
++ vdoa_write_register(vdoa, VDOAVEBA2,
++ params->vfield_buf.next_veba);
++ vdoa->field = VDOA_NEXT_FIELD;
++ vdoa_read_register(vdoa, VDOAC, &data);
++ data |= VDOAC_THREE_FRAMES;
++ vdoa_write_register(vdoa, VDOAC, data);
++ }
++
++ if (!params->pfs)
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->band_lines);
++ vdoa_write_register(vdoa, VDOAVUBO,
++ params->vfield_buf.vubo);
++ dev_dbg(vdoa->dev, "total band_size:0x%x.\n", band_size*6);
++ } else if (params->band_mode) {
++ /* used for progressive frame resize on PrP channel */
++ BUG(); /* currently not support */
++ /* progressvie frame: band mode */
++ vdoa_write_register(vdoa, VDOAIEBA00, vdoa->iram_paddr);
++ vdoa_write_register(vdoa, VDOAIEBA10,
++ vdoa->iram_paddr + band_size);
++ if (!params->pfs)
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->band_lines);
++ dev_dbg(vdoa->dev, "total band_size:0x%x\n", band_size*2);
++ } else {
++ /* progressive frame: mem->mem, non-band mode */
++ vdoa->field = VDOA_FRAME;
++ vdoa_write_register(vdoa, VDOAVEBA0, params->vframe_buf.veba);
++ vdoa_write_register(vdoa, VDOAVUBO, params->vframe_buf.vubo);
++ vdoa_write_register(vdoa, VDOAIEBA00, params->ieba0);
++ if (!params->pfs)
++ /* note: iubo is relative value, based on ieba0 */
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->height);
++ }
++ vdoa->state = VDOA_SETUP;
++ return 0;
++}
++
++void vdoa_get_output_buf(vdoa_handle_t handle, struct vdoa_ipu_buf *buf)
++{
++ u32 data;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_SETUP, return);
++ vdoa->state = VDOA_GET_OBUF;
++ memset(buf, 0, sizeof(*buf));
++
++ vdoa_read_register(vdoa, VDOAC, &data);
++ switch (vdoa->field) {
++ case VDOA_FRAME:
++ case VDOA_PREV_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA00, &buf->ieba0);
++ if (data & VDOAC_SYNC_BAND_MODE)
++ vdoa_read_register(vdoa, VDOAIEBA10, &buf->ieba1);
++ break;
++ case VDOA_CURR_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA01, &buf->ieba0);
++ vdoa_read_register(vdoa, VDOAIEBA11, &buf->ieba1);
++ break;
++ case VDOA_NEXT_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA02, &buf->ieba0);
++ vdoa_read_register(vdoa, VDOAIEBA12, &buf->ieba1);
++ break;
++ default:
++ BUG();
++ break;
++ }
++ if (!(data & VDOAC_PFS_YUYV))
++ vdoa_read_register(vdoa, VDOAIUBO, &buf->iubo);
++}
++
++int vdoa_start(vdoa_handle_t handle, int timeout_ms)
++{
++ int ret;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET_OBUF, return -EINVAL);
++ vdoa->state = VDOA_START;
++ init_completion(&vdoa->comp);
++ vdoa_write_register(vdoa, VDOAIST,
++ VDOAIEIST_TRANSFER_ERR | VDOAIEIST_TRANSFER_END);
++ vdoa_write_register(vdoa, VDOAIE,
++ VDOAIEIST_TRANSFER_ERR | VDOAIEIST_TRANSFER_END);
++
++ enable_irq(vdoa->irq);
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_START_XFER);
++ dump_registers(vdoa);
++
++ ret = wait_for_completion_timeout(&vdoa->comp,
++ msecs_to_jiffies(timeout_ms));
++
++ return ret > 0 ? 0 : -ETIMEDOUT;
++}
++
++void vdoa_stop(vdoa_handle_t handle)
++{
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET | VDOA_START | VDOA_INIRQ, return);
++ vdoa->state = VDOA_STOP;
++
++ disable_irq(vdoa->irq);
++
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_SWRST);
++}
++
++void vdoa_get_handle(vdoa_handle_t *handle)
++{
++ struct vdoa_info *vdoa = g_vdoa;
++
++ CHECK_NULL_PTR(handle);
++ *handle = (vdoa_handle_t *)NULL;
++ CHECK_STATE(VDOA_INIT, return);
++ mutex_lock(&vdoa_lock);
++ clk_prepare_enable(vdoa->vdoa_clk);
++ vdoa->state = VDOA_GET;
++ vdoa->field = VDOA_NULL;
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_SWRST);
++
++ *handle = (vdoa_handle_t *)vdoa;
++}
++
++void vdoa_put_handle(vdoa_handle_t *handle)
++{
++ struct vdoa_info *vdoa = (struct vdoa_info *)(*handle);
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_STOP, return);
++ if (vdoa != g_vdoa)
++ BUG();
++
++ clk_disable_unprepare(vdoa->vdoa_clk);
++ vdoa->state = VDOA_PUT;
++ *handle = (vdoa_handle_t *)NULL;
++ mutex_unlock(&vdoa_lock);
++}
++
++static irqreturn_t vdoa_irq_handler(int irq, void *data)
++{
++ u32 status, mask, val;
++ struct vdoa_info *vdoa = data;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_START, return IRQ_HANDLED);
++ vdoa->state = VDOA_INIRQ;
++ vdoa_read_register(vdoa, VDOAIST, &status);
++ vdoa_read_register(vdoa, VDOAIE, &mask);
++ val = status & mask;
++ vdoa_write_register(vdoa, VDOAIST, val);
++ if (VDOAIEIST_TRANSFER_ERR & val)
++ dev_err(vdoa->dev, "vdoa Transfer err irq!\n");
++ if (VDOAIEIST_TRANSFER_END & val)
++ dev_dbg(vdoa->dev, "vdoa Transfer end irq!\n");
++ if (0 == val) {
++ dev_err(vdoa->dev, "vdoa unknown irq!\n");
++ BUG();
++ }
++
++ complete(&vdoa->comp);
++ return IRQ_HANDLED;
++}
++
++/* IRAM Size in Kbytes, example:vdoa_iram_size=64, 64KBytes */
++static int __init vdoa_iram_size_setup(char *options)
++{
++ int ret;
++
++ ret = strict_strtoul(options, 0, &iram_size);
++ if (ret)
++ iram_size = 0;
++ else
++ iram_size *= SZ_1K;
++
++ return 1;
++}
++__setup("vdoa_iram_size=", vdoa_iram_size_setup);
++
++static const struct of_device_id imx_vdoa_dt_ids[] = {
++ { .compatible = "fsl,imx6q-vdoa", },
++ { /* sentinel */ }
++};
++
++static int vdoa_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct vdoa_info *vdoa;
++ struct resource *res;
++ struct resource *res_irq;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = pdev->dev.of_node;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(dev, "can't get device resources\n");
++ return -ENOENT;
++ }
++
++ res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (!res_irq) {
++ dev_err(dev, "failed to get irq resource\n");
++ return -ENOENT;
++ }
++
++ vdoa = devm_kzalloc(dev, sizeof(struct vdoa_info), GFP_KERNEL);
++ if (!vdoa)
++ return -ENOMEM;
++ vdoa->dev = dev;
++
++ vdoa->reg_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (!vdoa->reg_base)
++ return -EBUSY;
++
++ vdoa->irq = res_irq->start;
++ ret = devm_request_irq(dev, vdoa->irq, vdoa_irq_handler, 0,
++ "vdoa", vdoa);
++ if (ret) {
++ dev_err(dev, "can't claim irq %d\n", vdoa->irq);
++ return ret;
++ }
++ disable_irq(vdoa->irq);
++
++ vdoa->vdoa_clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(vdoa->vdoa_clk)) {
++ dev_err(dev, "failed to get vdoa_clk\n");
++ return PTR_ERR(vdoa->vdoa_clk);
++ }
++
++ vdoa->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!vdoa->iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ return -ENOMEM;
++ }
++
++ if ((iram_size == 0) || (iram_size > MAX_VDOA_IRAM_SIZE))
++ iram_size = VDOA_IRAM_SIZE;
++
++ vdoa->iram_base = gen_pool_alloc(vdoa->iram_pool, iram_size);
++ if (!vdoa->iram_base) {
++ dev_err(&pdev->dev, "unable to alloc iram\n");
++ return -ENOMEM;
++ }
++
++ vdoa->iram_paddr = gen_pool_virt_to_phys(vdoa->iram_pool,
++ vdoa->iram_base);
++
++ dev_dbg(dev, "iram_base:0x%lx,iram_paddr:0x%lx,size:0x%lx\n",
++ vdoa->iram_base, vdoa->iram_paddr, iram_size);
++
++ vdoa->state = VDOA_INIT;
++ dev_set_drvdata(dev, vdoa);
++ g_vdoa = vdoa;
++ dev_info(dev, "i.MX Video Data Order Adapter(VDOA) driver probed\n");
++ return 0;
++}
++
++static int vdoa_remove(struct platform_device *pdev)
++{
++ struct vdoa_info *vdoa = dev_get_drvdata(&pdev->dev);
++
++ gen_pool_free(vdoa->iram_pool, vdoa->iram_base, iram_size);
++ kfree(vdoa);
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static struct platform_driver vdoa_driver = {
++ .driver = {
++ .name = "mxc_vdoa",
++ .of_match_table = imx_vdoa_dt_ids,
++ },
++ .probe = vdoa_probe,
++ .remove = vdoa_remove,
++};
++
++static int __init vdoa_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&vdoa_driver);
++ if (err) {
++ pr_err("vdoa_driver register failed\n");
++ return -ENODEV;
++ }
++ return 0;
++}
++
++static void __exit vdoa_cleanup(void)
++{
++ platform_driver_unregister(&vdoa_driver);
++}
++
++module_init(vdoa_init);
++module_exit(vdoa_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX Video Data Order Adapter(VDOA) driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mxc/ipu3/vdoa.h linux-linaro-stable-mx6/drivers/mxc/ipu3/vdoa.h
+--- linux-3.10.30.orig/drivers/mxc/ipu3/vdoa.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/ipu3/vdoa.h 2014-05-15 20:33:58.654018592 +0200
+@@ -0,0 +1,69 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __VDOA_H__
++#define __VDOA_H__
++
++#define VDOA_PFS_YUYV (1)
++#define VDOA_PFS_NV12 (0)
++
++
++struct vfield_buf {
++ u32 prev_veba;
++ u32 cur_veba;
++ u32 next_veba;
++ u32 vubo;
++};
++
++struct vframe_buf {
++ u32 veba;
++ u32 vubo;
++};
++
++struct vdoa_params {
++ u32 width;
++ u32 height;
++ int vpu_stride;
++ int interlaced;
++ int scan_order;
++ int ipu_num;
++ int band_lines;
++ int band_mode;
++ int pfs;
++ u32 ieba0;
++ u32 ieba1;
++ u32 ieba2;
++ struct vframe_buf vframe_buf;
++ struct vfield_buf vfield_buf;
++};
++struct vdoa_ipu_buf {
++ u32 ieba0;
++ u32 ieba1;
++ u32 iubo;
++};
++
++struct vdoa_info;
++typedef void *vdoa_handle_t;
++
++int vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params);
++void vdoa_get_output_buf(vdoa_handle_t handle, struct vdoa_ipu_buf *buf);
++int vdoa_start(vdoa_handle_t handle, int timeout_ms);
++void vdoa_stop(vdoa_handle_t handle);
++void vdoa_get_handle(vdoa_handle_t *handle);
++void vdoa_put_handle(vdoa_handle_t *handle);
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/Kconfig linux-linaro-stable-mx6/drivers/mxc/Kconfig
+--- linux-3.10.30.orig/drivers/mxc/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/Kconfig 2014-05-15 20:33:58.586018102 +0200
+@@ -0,0 +1,24 @@
++# drivers/mxc/Kconfig
++
++if ARCH_MXC
++
++menu "MXC support drivers"
++
++config MXC_IPU
++ bool "Image Processing Unit Driver"
++ select MXC_IPU_V3
++ help
++ If you plan to use the Image Processing unit, say
++ Y here. IPU is needed by Framebuffer and V4L2 drivers.
++
++source "drivers/mxc/gpu-viv/Kconfig"
++source "drivers/mxc/ipu3/Kconfig"
++source "drivers/mxc/asrc/Kconfig"
++source "drivers/mxc/vpu/Kconfig"
++source "drivers/mxc/hdmi-cec/Kconfig"
++source "drivers/mxc/mipi/Kconfig"
++source "drivers/mxc/mlb/Kconfig"
++
++endmenu
++
++endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/Makefile linux-linaro-stable-mx6/drivers/mxc/Makefile
+--- linux-3.10.30.orig/drivers/mxc/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/Makefile 2014-05-15 20:33:58.586018102 +0200
+@@ -0,0 +1,7 @@
++obj-$(CONFIG_MXC_GPU_VIV) += gpu-viv/
++obj-$(CONFIG_MXC_IPU_V3) += ipu3/
++obj-$(CONFIG_MXC_ASRC) += asrc/
++obj-$(CONFIG_MXC_VPU) += vpu/
++obj-$(CONFIG_MXC_HDMI_CEC) += hdmi-cec/
++obj-$(CONFIG_MXC_MIPI_CSI2) += mipi/
++obj-$(CONFIG_MXC_MLB) += mlb/
+diff -Nur linux-3.10.30.orig/drivers/mxc/mipi/Kconfig linux-linaro-stable-mx6/drivers/mxc/mipi/Kconfig
+--- linux-3.10.30.orig/drivers/mxc/mipi/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/mipi/Kconfig 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,14 @@
++#
++# MIPI configuration
++#
++
++menu "MXC MIPI Support"
++
++config MXC_MIPI_CSI2
++ tristate "MIPI CSI2 support"
++ depends on SOC_IMX6Q
++ default n
++ ---help---
++ Say Y to get the MIPI CSI2 support.
++
++endmenu
+diff -Nur linux-3.10.30.orig/drivers/mxc/mipi/Makefile linux-linaro-stable-mx6/drivers/mxc/mipi/Makefile
+--- linux-3.10.30.orig/drivers/mxc/mipi/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/mipi/Makefile 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,4 @@
++#
++# Makefile for the mipi interface driver
++#
++obj-$(CONFIG_MXC_MIPI_CSI2) += mxc_mipi_csi2.o
+diff -Nur linux-3.10.30.orig/drivers/mxc/mipi/mxc_mipi_csi2.c linux-linaro-stable-mx6/drivers/mxc/mipi/mxc_mipi_csi2.c
+--- linux-3.10.30.orig/drivers/mxc/mipi/mxc_mipi_csi2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/mipi/mxc_mipi_csi2.c 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,531 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/irqdesc.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++
++#include <linux/mipi_csi2.h>
++
++#include "mxc_mipi_csi2.h"
++
++static struct mipi_csi2_info *gmipi_csi2;
++
++void _mipi_csi2_lock(struct mipi_csi2_info *info)
++{
++ if (!in_irq() && !in_softirq())
++ mutex_lock(&info->mutex_lock);
++}
++
++void _mipi_csi2_unlock(struct mipi_csi2_info *info)
++{
++ if (!in_irq() && !in_softirq())
++ mutex_unlock(&info->mutex_lock);
++}
++
++static inline void mipi_csi2_write(struct mipi_csi2_info *info,
++ unsigned value, unsigned offset)
++{
++ writel(value, info->mipi_csi2_base + offset);
++}
++
++static inline unsigned int mipi_csi2_read(struct mipi_csi2_info *info,
++ unsigned offset)
++{
++ return readl(info->mipi_csi2_base + offset);
++}
++
++/*!
++ * This function is called to enable the mipi csi2 interface.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++bool mipi_csi2_enable(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++
++ if (!info->mipi_en) {
++ info->mipi_en = true;
++ clk_prepare_enable(info->dphy_clk);
++ } else
++ mipi_dbg("mipi csi2 already enabled!\n");
++
++ status = info->mipi_en;
++
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_enable);
++
++/*!
++ * This function is called to disable the mipi csi2 interface.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++bool mipi_csi2_disable(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++
++ if (info->mipi_en) {
++ info->mipi_en = false;
++ clk_disable_unprepare(info->dphy_clk);
++ } else
++ mipi_dbg("mipi csi2 already disabled!\n");
++
++ status = info->mipi_en;
++
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_disable);
++
++/*!
++ * This function is called to get mipi csi2 disable/enable status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns mipi csi2 status
++ */
++bool mipi_csi2_get_status(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++ status = info->mipi_en;
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_get_status);
++
++/*!
++ * This function is called to set mipi lanes.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++unsigned int mipi_csi2_set_lanes(struct mipi_csi2_info *info)
++{
++ unsigned int lanes;
++
++ _mipi_csi2_lock(info);
++ mipi_csi2_write(info, info->lanes - 1, CSI2_N_LANES);
++ lanes = mipi_csi2_read(info, CSI2_N_LANES);
++ _mipi_csi2_unlock(info);
++
++ return lanes;
++}
++EXPORT_SYMBOL(mipi_csi2_set_lanes);
++
++/*!
++ * This function is called to set mipi data type.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info,
++ unsigned int datatype)
++{
++ unsigned int dtype;
++
++ _mipi_csi2_lock(info);
++ info->datatype = datatype;
++ dtype = info->datatype;
++ _mipi_csi2_unlock(info);
++
++ return dtype;
++}
++EXPORT_SYMBOL(mipi_csi2_set_datatype);
++
++/*!
++ * This function is called to get mipi data type.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns mipi data type
++ */
++unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info)
++{
++ unsigned int dtype;
++
++ _mipi_csi2_lock(info);
++ dtype = info->datatype;
++ _mipi_csi2_unlock(info);
++
++ return dtype;
++}
++EXPORT_SYMBOL(mipi_csi2_get_datatype);
++
++/*!
++ * This function is called to get mipi csi2 dphy status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns dphy status
++ */
++unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info)
++{
++ unsigned int status;
++
++ _mipi_csi2_lock(info);
++ status = mipi_csi2_read(info, CSI2_PHY_STATE);
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_dphy_status);
++
++/*!
++ * This function is called to get mipi csi2 error1 status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns error1 value
++ */
++unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info)
++{
++ unsigned int err1;
++
++ _mipi_csi2_lock(info);
++ err1 = mipi_csi2_read(info, CSI2_ERR1);
++ _mipi_csi2_unlock(info);
++
++ return err1;
++}
++EXPORT_SYMBOL(mipi_csi2_get_error1);
++
++/*!
++ * This function is called to get mipi csi2 error1 status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns error1 value
++ */
++unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info)
++{
++ unsigned int err2;
++
++ _mipi_csi2_lock(info);
++ err2 = mipi_csi2_read(info, CSI2_ERR2);
++ _mipi_csi2_unlock(info);
++
++ return err2;
++}
++EXPORT_SYMBOL(mipi_csi2_get_error2);
++
++/*!
++ * This function is called to enable mipi to ipu pixel clock.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info)
++{
++ return clk_prepare_enable(info->pixel_clk);
++}
++EXPORT_SYMBOL(mipi_csi2_pixelclk_enable);
++
++/*!
++ * This function is called to disable mipi to ipu pixel clock.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info)
++{
++ clk_disable_unprepare(info->pixel_clk);
++}
++EXPORT_SYMBOL(mipi_csi2_pixelclk_disable);
++
++/*!
++ * This function is called to power on mipi csi2.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++int mipi_csi2_reset(struct mipi_csi2_info *info)
++{
++ _mipi_csi2_lock(info);
++
++ mipi_csi2_write(info, 0x0, CSI2_PHY_SHUTDOWNZ);
++ mipi_csi2_write(info, 0x0, CSI2_DPHY_RSTZ);
++ mipi_csi2_write(info, 0x0, CSI2_RESETN);
++
++ mipi_csi2_write(info, 0x00000001, CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000000, CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000000, CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000002, CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00010044, CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000000, CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000014, CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000002, CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000000, CSI2_PHY_TST_CTRL0);
++
++ mipi_csi2_write(info, 0xffffffff, CSI2_PHY_SHUTDOWNZ);
++ mipi_csi2_write(info, 0xffffffff, CSI2_DPHY_RSTZ);
++ mipi_csi2_write(info, 0xffffffff, CSI2_RESETN);
++
++ _mipi_csi2_unlock(info);
++
++ return 0;
++}
++EXPORT_SYMBOL(mipi_csi2_reset);
++
++/*!
++ * This function is called to get mipi csi2 info.
++ *
++ * @return Returns mipi csi2 info struct pointor
++ */
++struct mipi_csi2_info *mipi_csi2_get_info(void)
++{
++ return gmipi_csi2;
++}
++EXPORT_SYMBOL(mipi_csi2_get_info);
++
++/*!
++ * This function is called to get mipi csi2 bind ipu num.
++ *
++ * @return Returns mipi csi2 bind ipu num
++ */
++int mipi_csi2_get_bind_ipu(struct mipi_csi2_info *info)
++{
++ int ipu_id;
++
++ _mipi_csi2_lock(info);
++ ipu_id = info->ipu_id;
++ _mipi_csi2_unlock(info);
++
++ return ipu_id;
++}
++EXPORT_SYMBOL(mipi_csi2_get_bind_ipu);
++
++/*!
++ * This function is called to get mipi csi2 bind csi num.
++ *
++ * @return Returns mipi csi2 bind csi num
++ */
++unsigned int mipi_csi2_get_bind_csi(struct mipi_csi2_info *info)
++{
++ unsigned int csi_id;
++
++ _mipi_csi2_lock(info);
++ csi_id = info->csi_id;
++ _mipi_csi2_unlock(info);
++
++ return csi_id;
++}
++EXPORT_SYMBOL(mipi_csi2_get_bind_csi);
++
++/*!
++ * This function is called to get mipi csi2 virtual channel.
++ *
++ * @return Returns mipi csi2 virtual channel num
++ */
++unsigned int mipi_csi2_get_virtual_channel(struct mipi_csi2_info *info)
++{
++ unsigned int v_channel;
++
++ _mipi_csi2_lock(info);
++ v_channel = info->v_channel;
++ _mipi_csi2_unlock(info);
++
++ return v_channel;
++}
++EXPORT_SYMBOL(mipi_csi2_get_virtual_channel);
++
++/**
++ * This function is called by the driver framework to initialize the MIPI CSI2
++ * device.
++ *
++ * @param pdev The device structure for the MIPI CSI2 passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int mipi_csi2_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *np = pdev->dev.of_node;
++ struct resource *res;
++ u32 mipi_csi2_dphy_ver;
++ int ret;
++
++ gmipi_csi2 = kmalloc(sizeof(struct mipi_csi2_info), GFP_KERNEL);
++ if (!gmipi_csi2) {
++ ret = -ENOMEM;
++ goto alloc_failed;
++ }
++
++ ret = of_property_read_u32(np, "ipu_id", &(gmipi_csi2->ipu_id));
++ if (ret) {
++ dev_err(&pdev->dev, "ipu_id missing or invalid\n");
++ goto err;
++ }
++
++ ret = of_property_read_u32(np, "csi_id", &(gmipi_csi2->csi_id));
++ if (ret) {
++ dev_err(&pdev->dev, "csi_id missing or invalid\n");
++ goto err;
++ }
++
++ ret = of_property_read_u32(np, "v_channel", &(gmipi_csi2->v_channel));
++ if (ret) {
++ dev_err(&pdev->dev, "v_channel missing or invalid\n");
++ goto err;
++ }
++
++ ret = of_property_read_u32(np, "lanes", &(gmipi_csi2->lanes));
++ if (ret) {
++ dev_err(&pdev->dev, "lanes missing or invalid\n");
++ goto err;
++ }
++
++ if ((gmipi_csi2->ipu_id < 0) || (gmipi_csi2->ipu_id > 1) ||
++ (gmipi_csi2->csi_id > 1) || (gmipi_csi2->v_channel > 3) ||
++ (gmipi_csi2->lanes > 4)) {
++ dev_err(&pdev->dev, "invalid param for mipi csi2!\n");
++ ret = -EINVAL;
++ goto err;
++ }
++
++ /* initialize mutex */
++ mutex_init(&gmipi_csi2->mutex_lock);
++
++ /* get mipi csi2 informaiton */
++ gmipi_csi2->pdev = pdev;
++ gmipi_csi2->mipi_en = false;
++
++ /* get mipi dphy clk */
++ gmipi_csi2->dphy_clk = devm_clk_get(dev, "dphy_clk");
++ if (IS_ERR(gmipi_csi2->dphy_clk)) {
++ dev_err(&pdev->dev, "failed to get dphy pll_ref_clk\n");
++ ret = PTR_ERR(gmipi_csi2->dphy_clk);
++ goto err;
++ }
++
++ /* get mipi to ipu pixel clk */
++ gmipi_csi2->pixel_clk = devm_clk_get(dev, "pixel_clk");
++ if (IS_ERR(gmipi_csi2->pixel_clk)) {
++ dev_err(&pdev->dev, "failed to get mipi pixel clk\n");
++ ret = PTR_ERR(gmipi_csi2->pixel_clk);
++ goto err;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ ret = -ENODEV;
++ goto err;
++ }
++
++ /* mipi register mapping */
++ gmipi_csi2->mipi_csi2_base = ioremap(res->start, PAGE_SIZE);
++ if (!gmipi_csi2->mipi_csi2_base) {
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ /* mipi dphy clk enable for register access */
++ clk_prepare_enable(gmipi_csi2->dphy_clk);
++ /* get mipi csi2 dphy version */
++ mipi_csi2_dphy_ver = mipi_csi2_read(gmipi_csi2, CSI2_VERSION);
++
++ clk_disable_unprepare(gmipi_csi2->dphy_clk);
++
++ platform_set_drvdata(pdev, gmipi_csi2);
++
++ dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed\n");
++ dev_info(&pdev->dev, "i.MX MIPI CSI2 dphy version is 0x%x\n",
++ mipi_csi2_dphy_ver);
++
++ return 0;
++
++err:
++ kfree(gmipi_csi2);
++alloc_failed:
++ dev_err(&pdev->dev, "i.MX MIPI CSI2 driver probed - error\n");
++ return ret;
++}
++
++static int mipi_csi2_remove(struct platform_device *pdev)
++{
++ /* unmapping mipi register */
++ iounmap(gmipi_csi2->mipi_csi2_base);
++
++ kfree(gmipi_csi2);
++
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static const struct of_device_id imx_mipi_csi2_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mipi-csi2", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mipi_csi2_driver = {
++ .driver = {
++ .name = "mxc_mipi_csi2",
++ .of_match_table = imx_mipi_csi2_dt_ids,
++ },
++ .probe = mipi_csi2_probe,
++ .remove = mipi_csi2_remove,
++};
++
++static int __init mipi_csi2_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&mipi_csi2_driver);
++ if (err) {
++ pr_err("mipi_csi2_driver register failed\n");
++ return -ENODEV;
++ }
++
++ pr_info("MIPI CSI2 driver module loaded\n");
++
++ return 0;
++}
++
++static void __exit mipi_csi2_cleanup(void)
++{
++ platform_driver_unregister(&mipi_csi2_driver);
++}
++
++subsys_initcall(mipi_csi2_init);
++module_exit(mipi_csi2_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX MIPI CSI2 driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mxc/mipi/mxc_mipi_csi2.h linux-linaro-stable-mx6/drivers/mxc/mipi/mxc_mipi_csi2.h
+--- linux-3.10.30.orig/drivers/mxc/mipi/mxc_mipi_csi2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/mipi/mxc_mipi_csi2.h 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,45 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MXC_MIPI_CSI2_H__
++#define __MXC_MIPI_CSI2_H__
++
++#ifdef DEBUG
++#define mipi_dbg(fmt, ...) \
++ printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
++#else
++#define mipi_dbg(fmt, ...)
++#endif
++
++/* driver private data */
++struct mipi_csi2_info {
++ bool mipi_en;
++ int ipu_id;
++ unsigned int csi_id;
++ unsigned int v_channel;
++ unsigned int lanes;
++ unsigned int datatype;
++ struct clk *dphy_clk;
++ struct clk *pixel_clk;
++ unsigned int *mipi_csi2_base;
++ struct platform_device *pdev;
++
++ struct mutex mutex_lock;
++};
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/mlb/Kconfig linux-linaro-stable-mx6/drivers/mxc/mlb/Kconfig
+--- linux-3.10.30.orig/drivers/mxc/mlb/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/mlb/Kconfig 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,17 @@
++#
++# MLB150 configuration
++#
++
++menu "MXC Media Local Bus Driver"
++
++config MXC_MLB
++ boolean
++
++config MXC_MLB150
++ tristate "MLB150 support"
++ depends on SOC_IMX6Q
++ select MXC_MLB
++ ---help---
++ Say Y to get the MLB150 support.
++
++endmenu
+diff -Nur linux-3.10.30.orig/drivers/mxc/mlb/Makefile linux-linaro-stable-mx6/drivers/mxc/mlb/Makefile
+--- linux-3.10.30.orig/drivers/mxc/mlb/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/mlb/Makefile 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,5 @@
++#
++# Makefile for the i.MX6Q/DL MLB150 driver
++#
++
++obj-$(CONFIG_MXC_MLB150) += mxc_mlb150.o
+diff -Nur linux-3.10.30.orig/drivers/mxc/mlb/mxc_mlb150.c linux-linaro-stable-mx6/drivers/mxc/mlb/mxc_mlb150.c
+--- linux-3.10.30.orig/drivers/mxc/mlb/mxc_mlb150.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/mlb/mxc_mlb150.c 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,2778 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/cdev.h>
++#include <linux/circ_buf.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/fs.h>
++#include <linux/genalloc.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxc_mlb.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/regulator/consumer.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/uaccess.h>
++
++#define DRIVER_NAME "mxc_mlb150"
++
++/*
++ * MLB module memory map registers define
++ */
++#define REG_MLBC0 0x0
++#define MLBC0_MLBEN (0x1)
++#define MLBC0_MLBCLK_MASK (0x7 << 2)
++#define MLBC0_MLBCLK_SHIFT (2)
++#define MLBC0_MLBPEN (0x1 << 5)
++#define MLBC0_MLBLK (0x1 << 7)
++#define MLBC0_ASYRETRY (0x1 << 12)
++#define MLBC0_CTLRETRY (0x1 << 12)
++#define MLBC0_FCNT_MASK (0x7 << 15)
++#define MLBC0_FCNT_SHIFT (15)
++
++#define REG_MLBPC0 0x8
++#define MLBPC0_MCLKHYS (0x1 << 11)
++
++#define REG_MS0 0xC
++#define REG_MS1 0x14
++
++#define REG_MSS 0x20
++#define MSS_RSTSYSCMD (0x1)
++#define MSS_LKSYSCMD (0x1 << 1)
++#define MSS_ULKSYSCMD (0x1 << 2)
++#define MSS_CSSYSCMD (0x1 << 3)
++#define MSS_SWSYSCMD (0x1 << 4)
++#define MSS_SERVREQ (0x1 << 5)
++
++#define REG_MSD 0x24
++
++#define REG_MIEN 0x2C
++#define MIEN_ISOC_PE (0x1)
++#define MIEN_ISOC_BUFO (0x1 << 1)
++#define MIEN_SYNC_PE (0x1 << 16)
++#define MIEN_ARX_DONE (0x1 << 17)
++#define MIEN_ARX_PE (0x1 << 18)
++#define MIEN_ARX_BREAK (0x1 << 19)
++#define MIEN_ATX_DONE (0x1 << 20)
++#define MIEN_ATX_PE (0x1 << 21)
++#define MIEN_ATX_BREAK (0x1 << 22)
++#define MIEN_CRX_DONE (0x1 << 24)
++#define MIEN_CRX_PE (0x1 << 25)
++#define MIEN_CRX_BREAK (0x1 << 26)
++#define MIEN_CTX_DONE (0x1 << 27)
++#define MIEN_CTX_PE (0x1 << 28)
++#define MIEN_CTX_BREAK (0x1 << 29)
++
++#define REG_MLBPC2 0x34
++#define REG_MLBPC1 0x38
++#define MLBPC1_VAL (0x00000888)
++
++#define REG_MLBC1 0x3C
++#define MLBC1_LOCK (0x1 << 6)
++#define MLBC1_CLKM (0x1 << 7)
++#define MLBC1_NDA_MASK (0xFF << 8)
++#define MLBC1_NDA_SHIFT (8)
++
++#define REG_HCTL 0x80
++#define HCTL_RST0 (0x1)
++#define HCTL_RST1 (0x1 << 1)
++#define HCTL_EN (0x1 << 15)
++
++#define REG_HCMR0 0x88
++#define REG_HCMR1 0x8C
++#define REG_HCER0 0x90
++#define REG_HCER1 0x94
++#define REG_HCBR0 0x98
++#define REG_HCBR1 0x9C
++
++#define REG_MDAT0 0xC0
++#define REG_MDAT1 0xC4
++#define REG_MDAT2 0xC8
++#define REG_MDAT3 0xCC
++
++#define REG_MDWE0 0xD0
++#define REG_MDWE1 0xD4
++#define REG_MDWE2 0xD8
++#define REG_MDWE3 0xDC
++
++#define REG_MCTL 0xE0
++#define MCTL_XCMP (0x1)
++
++#define REG_MADR 0xE4
++#define MADR_WNR (0x1 << 31)
++#define MADR_TB (0x1 << 30)
++#define MADR_ADDR_MASK (0x7f << 8)
++#define MADR_ADDR_SHIFT (0)
++
++#define REG_ACTL 0x3C0
++#define ACTL_MPB (0x1 << 4)
++#define ACTL_DMAMODE (0x1 << 2)
++#define ACTL_SMX (0x1 << 1)
++#define ACTL_SCE (0x1)
++
++#define REG_ACSR0 0x3D0
++#define REG_ACSR1 0x3D4
++#define REG_ACMR0 0x3D8
++#define REG_ACMR1 0x3DC
++
++#define REG_CAT_MDATn(ch) (REG_MDAT0 + ((ch % 8) >> 1) * 4)
++#define REG_CAT_MDWEn(ch) (REG_MDWE0 + ((ch % 8) >> 1) * 4)
++
++#define INT_AHB0_CH_START (0)
++#define INT_AHB1_CH_START (32)
++
++#define LOGIC_CH_NUM (64)
++#define BUF_CDT_OFFSET (0x0)
++#define BUF_ADT_OFFSET (0x40)
++#define BUF_CAT_MLB_OFFSET (0x80)
++#define BUF_CAT_HBI_OFFSET (0x88)
++#define BUF_CTR_END_OFFSET (0x8F)
++
++#define CAT_MODE_RX (0x1 << 0)
++#define CAT_MODE_TX (0x1 << 1)
++#define CAT_MODE_INBOUND_DMA (0x1 << 8)
++#define CAT_MODE_OUTBOUND_DMA (0x1 << 9)
++
++#define CH_SYNC_DEFAULT_QUAD (1)
++#define CH_SYNC_MAX_QUAD (15)
++#define CH_SYNC_CDT_BUF_DEP (CH_SYNC_DEFAULT_QUAD * 4 * 4)
++#define CH_SYNC_ADT_BUF_MULTI (4)
++#define CH_SYNC_ADT_BUF_DEP (CH_SYNC_CDT_BUF_DEP * CH_SYNC_ADT_BUF_MULTI)
++#define CH_SYNC_BUF_SZ (CH_SYNC_MAX_QUAD * 4 * 4 * \
++ CH_SYNC_ADT_BUF_MULTI)
++#define CH_CTRL_CDT_BUF_DEP (64)
++#define CH_CTRL_ADT_BUF_DEP (CH_CTRL_CDT_BUF_DEP)
++#define CH_CTRL_BUF_SZ (CH_CTRL_ADT_BUF_DEP)
++#define CH_ASYNC_MDP_PACKET_LEN (1024)
++#define CH_ASYNC_MEP_PACKET_LEN (1536)
++#define CH_ASYNC_CDT_BUF_DEP (CH_ASYNC_MEP_PACKET_LEN)
++#define CH_ASYNC_ADT_BUF_DEP (CH_ASYNC_CDT_BUF_DEP)
++#define CH_ASYNC_BUF_SZ (CH_ASYNC_ADT_BUF_DEP)
++#define CH_ISOC_BLK_SIZE_188 (188)
++#define CH_ISOC_BLK_SIZE_196 (196)
++#define CH_ISOC_BLK_SIZE (CH_ISOC_BLK_SIZE_188)
++#define CH_ISOC_BLK_NUM (1)
++#define CH_ISOC_CDT_BUF_DEP (CH_ISOC_BLK_SIZE * CH_ISOC_BLK_NUM)
++#define CH_ISOC_ADT_BUF_DEP (CH_ISOC_CDT_BUF_DEP)
++#define CH_ISOC_BUF_SZ (1024)
++
++#define CH_SYNC_DBR_BUF_OFFSET (0x0)
++#define CH_CTRL_DBR_BUF_OFFSET (CH_SYNC_DBR_BUF_OFFSET + \
++ 2 * (CH_SYNC_MAX_QUAD * 4 * 4))
++#define CH_ASYNC_DBR_BUF_OFFSET (CH_CTRL_DBR_BUF_OFFSET + \
++ 2 * CH_CTRL_CDT_BUF_DEP)
++#define CH_ISOC_DBR_BUF_OFFSET (CH_ASYNC_DBR_BUF_OFFSET + \
++ 2 * CH_ASYNC_CDT_BUF_DEP)
++
++#define DBR_BUF_START 0x00000
++
++#define CDT_LEN (16)
++#define ADT_LEN (16)
++#define CAT_LEN (2)
++
++#define CDT_SZ (CDT_LEN * LOGIC_CH_NUM)
++#define ADT_SZ (ADT_LEN * LOGIC_CH_NUM)
++#define CAT_SZ (CAT_LEN * LOGIC_CH_NUM * 2)
++
++#define CDT_BASE(base) (base + BUF_CDT_OFFSET)
++#define ADT_BASE(base) (base + BUF_ADT_OFFSET)
++#define CAT_MLB_BASE(base) (base + BUF_CAT_MLB_OFFSET)
++#define CAT_HBI_BASE(base) (base + BUF_CAT_HBI_OFFSET)
++
++#define CDTn_ADDR(base, n) (base + BUF_CDT_OFFSET + n * CDT_LEN)
++#define ADTn_ADDR(base, n) (base + BUF_ADT_OFFSET + n * ADT_LEN)
++#define CATn_MLB_ADDR(base, n) (base + BUF_CAT_MLB_OFFSET + n * CAT_LEN)
++#define CATn_HBI_ADDR(base, n) (base + BUF_CAT_HBI_OFFSET + n * CAT_LEN)
++
++#define CAT_CL_SHIFT (0x0)
++#define CAT_CT_SHIFT (8)
++#define CAT_CE (0x1 << 11)
++#define CAT_RNW (0x1 << 12)
++#define CAT_MT (0x1 << 13)
++#define CAT_FCE (0x1 << 14)
++#define CAT_MFE (0x1 << 14)
++
++#define CDT_WSBC_SHIFT (14)
++#define CDT_WPC_SHIFT (11)
++#define CDT_RSBC_SHIFT (30)
++#define CDT_RPC_SHIFT (27)
++#define CDT_WPC_1_SHIFT (12)
++#define CDT_RPC_1_SHIFT (28)
++#define CDT_WPTR_SHIFT (0)
++#define CDT_SYNC_WSTS_MASK (0x0000f000)
++#define CDT_SYNC_WSTS_SHIFT (12)
++#define CDT_CTRL_ASYNC_WSTS_MASK (0x0000f000)
++#define CDT_CTRL_ASYNC_WSTS_SHIFT (12)
++#define CDT_ISOC_WSTS_MASK (0x0000e000)
++#define CDT_ISOC_WSTS_SHIFT (13)
++#define CDT_RPTR_SHIFT (16)
++#define CDT_SYNC_RSTS_MASK (0xf0000000)
++#define CDT_SYNC_RSTS_SHIFT (28)
++#define CDT_CTRL_ASYNC_RSTS_MASK (0xf0000000)
++#define CDT_CTRL_ASYNC_RSTS_SHIFT (28)
++#define CDT_ISOC_RSTS_MASK (0xe0000000)
++#define CDT_ISOC_RSTS_SHIFT (29)
++#define CDT_CTRL_ASYNC_WSTS_1 (0x1 << 14)
++#define CDT_CTRL_ASYNC_RSTS_1 (0x1 << 15)
++#define CDT_BD_SHIFT (0)
++#define CDT_BA_SHIFT (16)
++#define CDT_BS_SHIFT (0)
++#define CDT_BF_SHIFT (31)
++
++#define ADT_PG (0x1 << 13)
++#define ADT_LE (0x1 << 14)
++#define ADT_CE (0x1 << 15)
++#define ADT_BD1_SHIFT (0)
++#define ADT_ERR1 (0x1 << 13)
++#define ADT_DNE1 (0x1 << 14)
++#define ADT_RDY1 (0x1 << 15)
++#define ADT_BD2_SHIFT (16)
++#define ADT_ERR2 (0x1 << 29)
++#define ADT_DNE2 (0x1 << 30)
++#define ADT_RDY2 (0x1 << 31)
++#define ADT_BA1_SHIFT (0x0)
++#define ADT_BA2_SHIFT (0x0)
++#define ADT_PS1 (0x1 << 12)
++#define ADT_PS2 (0x1 << 28)
++#define ADT_MEP1 (0x1 << 11)
++#define ADT_MEP2 (0x1 << 27)
++
++#define MLB_MINOR_DEVICES 4
++#define MLB_CONTROL_DEV_NAME "ctrl"
++#define MLB_ASYNC_DEV_NAME "async"
++#define MLB_SYNC_DEV_NAME "sync"
++#define MLB_ISOC_DEV_NAME "isoc"
++
++#define TX_CHANNEL 0
++#define RX_CHANNEL 1
++
++#define TRANS_RING_NODES (1 << 3)
++
++enum MLB_CTYPE {
++ MLB_CTYPE_SYNC,
++ MLB_CTYPE_CTRL,
++ MLB_CTYPE_ASYNC,
++ MLB_CTYPE_ISOC,
++};
++
++enum CLK_SPEED {
++ CLK_256FS,
++ CLK_512FS,
++ CLK_1024FS,
++ CLK_2048FS,
++ CLK_3072FS,
++ CLK_4096FS,
++ CLK_6144FS,
++ CLK_8192FS,
++};
++
++struct mlb_ringbuf {
++ s8 *virt_bufs[TRANS_RING_NODES];
++ u32 phy_addrs[TRANS_RING_NODES];
++ s32 head;
++ s32 tail;
++ s32 unit_size;
++ s32 total_size;
++ rwlock_t rb_lock ____cacheline_aligned; /* ring index lock */
++};
++
++struct mlb_channel_info {
++ /* Input MLB channel address */
++ u32 address;
++ /* Internal AHB channel label */
++ u32 cl;
++ /* DBR buf head */
++ u32 dbr_buf_head;
++};
++
++struct mlb_dev_info {
++ /* device node name */
++ const char dev_name[20];
++ /* channel type */
++ const unsigned int channel_type;
++ /* ch fps */
++ enum CLK_SPEED fps;
++ /* channel info for tx/rx */
++ struct mlb_channel_info channels[2];
++ /* ring buffer */
++ u8 *rbuf_base_virt;
++ u32 rbuf_base_phy;
++ struct mlb_ringbuf rx_rbuf;
++ struct mlb_ringbuf tx_rbuf;
++ /* exception event */
++ unsigned long ex_event;
++ /* tx busy indicator */
++ unsigned long tx_busy;
++ /* channel started up or not */
++ atomic_t on;
++ /* device open count */
++ atomic_t opencnt;
++ /* wait queue head for channel */
++ wait_queue_head_t rx_wq;
++ wait_queue_head_t tx_wq;
++ /* TX OK */
++ s32 tx_ok;
++ /* spinlock for event access */
++ spinlock_t event_lock;
++ /*
++ * Block size for isoc mode
++ * This variable can be configured in ioctl
++ */
++ u32 isoc_blksz;
++ /*
++ * Quads number for sync mode
++ * This variable can be confifured in ioctl
++ */
++ u32 sync_quad;
++ /* Buffer depth in cdt */
++ u32 cdt_buf_dep;
++ /* Buffer depth in adt */
++ u32 adt_buf_dep;
++ /* Buffer size to hold data */
++ u32 buf_size;
++};
++
++struct mlb_data {
++ struct mlb_dev_info *devinfo;
++ struct clk *clk_mlb3p;
++ struct clk *clk_mlb6p;
++ struct cdev cdev;
++ struct class *class; /* device class */
++ dev_t firstdev;
++#ifdef CONFIG_REGULATOR
++ struct regulator *nvcc;
++#endif
++ void __iomem *membase; /* mlb module base address */
++ struct gen_pool *iram_pool;
++ u32 iram_size;
++ u32 irq_ahb0;
++ u32 irq_ahb1;
++ u32 irq_mlb;
++};
++
++/*
++ * For optimization, we use fixed channel label for
++ * input channels of each mode
++ * SYNC: CL = 0 for RX, CL = 64 for TX
++ * CTRL: CL = 1 for RX, CL = 65 for TX
++ * ASYNC: CL = 2 for RX, CL = 66 for TX
++ * ISOC: CL = 3 for RX, CL = 67 for TX
++ */
++#define SYNC_RX_CL_AHB0 0
++#define CTRL_RX_CL_AHB0 1
++#define ASYNC_RX_CL_AHB0 2
++#define ISOC_RX_CL_AHB0 3
++#define SYNC_TX_CL_AHB0 4
++#define CTRL_TX_CL_AHB0 5
++#define ASYNC_TX_CL_AHB0 6
++#define ISOC_TX_CL_AHB0 7
++
++#define SYNC_RX_CL_AHB1 32
++#define CTRL_RX_CL_AHB1 33
++#define ASYNC_RX_CL_AHB1 34
++#define ISOC_RX_CL_AHB1 35
++#define SYNC_TX_CL_AHB1 36
++#define CTRL_TX_CL_AHB1 37
++#define ASYNC_TX_CL_AHB1 38
++#define ISOC_TX_CL_AHB1 39
++
++#define SYNC_RX_CL SYNC_RX_CL_AHB0
++#define CTRL_RX_CL CTRL_RX_CL_AHB0
++#define ASYNC_RX_CL ASYNC_RX_CL_AHB0
++#define ISOC_RX_CL ISOC_RX_CL_AHB0
++
++#define SYNC_TX_CL SYNC_TX_CL_AHB0
++#define CTRL_TX_CL CTRL_TX_CL_AHB0
++#define ASYNC_TX_CL ASYNC_TX_CL_AHB0
++#define ISOC_TX_CL ISOC_TX_CL_AHB0
++
++static struct mlb_dev_info mlb_devinfo[MLB_MINOR_DEVICES] = {
++ {
++ .dev_name = MLB_SYNC_DEV_NAME,
++ .channel_type = MLB_CTYPE_SYNC,
++ .channels = {
++ [0] = {
++ .cl = SYNC_TX_CL,
++ .dbr_buf_head = CH_SYNC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = SYNC_RX_CL,
++ .dbr_buf_head = CH_SYNC_DBR_BUF_OFFSET
++ + CH_SYNC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_SYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[0].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_SYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[0].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_SYNC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_SYNC_ADT_BUF_DEP,
++ .buf_size = CH_SYNC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[0].event_lock),
++ },
++ {
++ .dev_name = MLB_CONTROL_DEV_NAME,
++ .channel_type = MLB_CTYPE_CTRL,
++ .channels = {
++ [0] = {
++ .cl = CTRL_TX_CL,
++ .dbr_buf_head = CH_CTRL_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = CTRL_RX_CL,
++ .dbr_buf_head = CH_CTRL_DBR_BUF_OFFSET
++ + CH_CTRL_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_CTRL_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[1].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_CTRL_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[1].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_CTRL_CDT_BUF_DEP,
++ .adt_buf_dep = CH_CTRL_ADT_BUF_DEP,
++ .buf_size = CH_CTRL_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[1].event_lock),
++ },
++ {
++ .dev_name = MLB_ASYNC_DEV_NAME,
++ .channel_type = MLB_CTYPE_ASYNC,
++ .channels = {
++ [0] = {
++ .cl = ASYNC_TX_CL,
++ .dbr_buf_head = CH_ASYNC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = ASYNC_RX_CL,
++ .dbr_buf_head = CH_ASYNC_DBR_BUF_OFFSET
++ + CH_ASYNC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_ASYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[2].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_ASYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[2].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_ASYNC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_ASYNC_ADT_BUF_DEP,
++ .buf_size = CH_ASYNC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[2].event_lock),
++ },
++ {
++ .dev_name = MLB_ISOC_DEV_NAME,
++ .channel_type = MLB_CTYPE_ISOC,
++ .channels = {
++ [0] = {
++ .cl = ISOC_TX_CL,
++ .dbr_buf_head = CH_ISOC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = ISOC_RX_CL,
++ .dbr_buf_head = CH_ISOC_DBR_BUF_OFFSET
++ + CH_ISOC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_ISOC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[3].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_ISOC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[3].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_ISOC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_ISOC_ADT_BUF_DEP,
++ .buf_size = CH_ISOC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[3].event_lock),
++ .isoc_blksz = CH_ISOC_BLK_SIZE_188,
++ },
++};
++
++static void __iomem *mlb_base;
++
++DEFINE_SPINLOCK(ctr_lock);
++
++#ifdef DEBUG
++#define DUMP_REG(reg) pr_debug(#reg": 0x%08x\n", __raw_readl(mlb_base + reg))
++
++static void mlb150_dev_dump_reg(void)
++{
++ pr_debug("mxc_mlb150: Dump registers:\n");
++ DUMP_REG(REG_MLBC0);
++ DUMP_REG(REG_MLBPC0);
++ DUMP_REG(REG_MS0);
++ DUMP_REG(REG_MS1);
++ DUMP_REG(REG_MSS);
++ DUMP_REG(REG_MSD);
++ DUMP_REG(REG_MIEN);
++ DUMP_REG(REG_MLBPC2);
++ DUMP_REG(REG_MLBPC1);
++ DUMP_REG(REG_MLBC1);
++ DUMP_REG(REG_HCTL);
++ DUMP_REG(REG_HCMR0);
++ DUMP_REG(REG_HCMR1);
++ DUMP_REG(REG_HCER0);
++ DUMP_REG(REG_HCER1);
++ DUMP_REG(REG_HCBR0);
++ DUMP_REG(REG_HCBR1);
++ DUMP_REG(REG_MDAT0);
++ DUMP_REG(REG_MDAT1);
++ DUMP_REG(REG_MDAT2);
++ DUMP_REG(REG_MDAT3);
++ DUMP_REG(REG_MDWE0);
++ DUMP_REG(REG_MDWE1);
++ DUMP_REG(REG_MDWE2);
++ DUMP_REG(REG_MDWE3);
++ DUMP_REG(REG_MCTL);
++ DUMP_REG(REG_MADR);
++ DUMP_REG(REG_ACTL);
++ DUMP_REG(REG_ACSR0);
++ DUMP_REG(REG_ACSR1);
++ DUMP_REG(REG_ACMR0);
++ DUMP_REG(REG_ACMR1);
++}
++
++static void mlb150_dev_dump_hex(const u8 *buf, u32 len)
++{
++ print_hex_dump(KERN_DEBUG, "CTR DUMP:",
++ DUMP_PREFIX_OFFSET, 8, 1, buf, len, 0);
++}
++#endif
++
++static inline void mlb150_dev_enable_ctr_write(u32 mdat0_bits_en,
++ u32 mdat1_bits_en, u32 mdat2_bits_en, u32 mdat3_bits_en)
++{
++ __raw_writel(mdat0_bits_en, mlb_base + REG_MDWE0);
++ __raw_writel(mdat1_bits_en, mlb_base + REG_MDWE1);
++ __raw_writel(mdat2_bits_en, mlb_base + REG_MDWE2);
++ __raw_writel(mdat3_bits_en, mlb_base + REG_MDWE3);
++}
++
++#ifdef DEBUG
++static inline u8 mlb150_dev_dbr_read(u32 dbr_addr)
++{
++ s32 timeout = 1000;
++ u8 dbr_val = 0;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(MADR_TB | dbr_addr,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (0 == timeout) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ return -ETIME;
++ }
++
++ dbr_val = __raw_readl(mlb_base + REG_MDAT0) & 0x000000ff;
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return dbr_val;
++}
++
++static inline s32 mlb150_dev_dbr_write(u32 dbr_addr, u8 dbr_val)
++{
++ s32 timeout = 1000;
++ u32 mdat0 = dbr_val & 0x000000ff;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(mdat0, mlb_base + REG_MDAT0);
++
++ __raw_writel(MADR_WNR | MADR_TB | dbr_addr,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ return -ETIME;
++ }
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_dbr_dump(u32 addr, u32 size)
++{
++ u8 *dump_buf = NULL;
++ u8 *buf_ptr = NULL;
++ s32 i;
++
++ dump_buf = kzalloc(size, GFP_KERNEL);
++ if (!dump_buf) {
++ pr_err("can't allocate enough memory\n");
++ return -ENOMEM;
++ }
++
++ for (i = 0, buf_ptr = dump_buf;
++ i < size; ++i, ++buf_ptr)
++ *buf_ptr = mlb150_dev_dbr_read(addr + i);
++
++ mlb150_dev_dump_hex(dump_buf, size);
++
++ kfree(dump_buf);
++
++ return 0;
++}
++#endif
++
++static s32 mlb150_dev_ctr_read(u32 ctr_offset, u32 *ctr_val)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(ctr_offset, mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Read CTR timeout\n");
++ return -ETIME;
++ }
++
++ ctr_val[0] = __raw_readl(mlb_base + REG_MDAT0);
++ ctr_val[1] = __raw_readl(mlb_base + REG_MDAT1);
++ ctr_val[2] = __raw_readl(mlb_base + REG_MDAT2);
++ ctr_val[3] = __raw_readl(mlb_base + REG_MDAT3);
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return 0;
++}
++
++static s32 mlb150_dev_ctr_write(u32 ctr_offset, const u32 *ctr_val)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++
++ __raw_writel(ctr_val[0], mlb_base + REG_MDAT0);
++ __raw_writel(ctr_val[1], mlb_base + REG_MDAT1);
++ __raw_writel(ctr_val[2], mlb_base + REG_MDAT2);
++ __raw_writel(ctr_val[3], mlb_base + REG_MDAT3);
++
++ __raw_writel(MADR_WNR | ctr_offset,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Write CTR timeout\n");
++ return -ETIME;
++ }
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++#ifdef DEBUG_CTR
++ {
++ u32 ctr_rd[4] = { 0 };
++
++ if (!mlb150_dev_ctr_read(ctr_offset, ctr_rd)) {
++ if (ctr_val[0] == ctr_rd[0] &&
++ ctr_val[1] == ctr_rd[1] &&
++ ctr_val[2] == ctr_rd[2] &&
++ ctr_val[3] == ctr_rd[3])
++ return 0;
++ else {
++ pr_debug("mxc_mlb150: ctr write failed\n");
++ pr_debug("offset: 0x%x\n", ctr_offset);
++ pr_debug("Write: 0x%x 0x%x 0x%x 0x%x\n",
++ ctr_val[3], ctr_val[2],
++ ctr_val[1], ctr_val[0]);
++ pr_debug("Read: 0x%x 0x%x 0x%x 0x%x\n",
++ ctr_rd[3], ctr_rd[2],
++ ctr_rd[1], ctr_rd[0]);
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: ctr read failed\n");
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++#ifdef DEBUG
++static s32 mlb150_dev_cat_read(u32 ctr_offset, u32 ch, u16 *cat_val)
++{
++ u16 ctr_val[8] = { 0 };
++
++ if (mlb150_dev_ctr_read(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ /*
++ * Use u16 array to get u32 array value,
++ * need to convert
++ */
++ cat_val = ctr_val[ch % 8];
++
++ return 0;
++}
++#endif
++
++static s32 mlb150_dev_cat_write(u32 ctr_offset, u32 ch, const u16 cat_val)
++{
++ u16 ctr_val[8] = { 0 };
++
++ if (mlb150_dev_ctr_read(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ ctr_val[ch % 8] = cat_val;
++ if (mlb150_dev_ctr_write(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++#define mlb150_dev_cat_mlb_read(ch, cat_val) \
++ mlb150_dev_cat_read(BUF_CAT_MLB_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_mlb_write(ch, cat_val) \
++ mlb150_dev_cat_write(BUF_CAT_MLB_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_hbi_read(ch, cat_val) \
++ mlb150_dev_cat_read(BUF_CAT_HBI_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_hbi_write(ch, cat_val) \
++ mlb150_dev_cat_write(BUF_CAT_HBI_OFFSET + (ch >> 3), ch, cat_val)
++
++#define mlb150_dev_cdt_read(ch, cdt_val) \
++ mlb150_dev_ctr_read(BUF_CDT_OFFSET + ch, cdt_val)
++#define mlb150_dev_cdt_write(ch, cdt_val) \
++ mlb150_dev_ctr_write(BUF_CDT_OFFSET + ch, cdt_val)
++#define mlb150_dev_adt_read(ch, adt_val) \
++ mlb150_dev_ctr_read(BUF_ADT_OFFSET + ch, adt_val)
++#define mlb150_dev_adt_write(ch, adt_val) \
++ mlb150_dev_ctr_write(BUF_ADT_OFFSET + ch, adt_val)
++
++static s32 mlb150_dev_get_adt_sts(u32 ch)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(BUF_ADT_OFFSET + ch,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Read CTR timeout\n");
++ return -ETIME;
++ }
++
++ reg = __raw_readl(mlb_base + REG_MDAT1);
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++#ifdef DEBUG_ADT
++ pr_debug("mxc_mlb150: Get ch %d adt sts: 0x%08x\n", ch, reg);
++#endif
++
++ return reg;
++}
++
++#ifdef DEBUG
++static void mlb150_dev_dump_ctr_tbl(u32 ch_start, u32 ch_end)
++{
++ u32 i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ pr_debug("mxc_mlb150: CDT Table");
++ for (i = BUF_CDT_OFFSET + ch_start;
++ i < BUF_CDT_OFFSET + ch_end;
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: ADT Table");
++ for (i = BUF_ADT_OFFSET + ch_start;
++ i < BUF_ADT_OFFSET + ch_end;
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: CAT MLB Table");
++ for (i = BUF_CAT_MLB_OFFSET + (ch_start >> 3);
++ i <= BUF_CAT_MLB_OFFSET + ((ch_end + 8) >> 3);
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: CAT HBI Table");
++ for (i = BUF_CAT_HBI_OFFSET + (ch_start >> 3);
++ i <= BUF_CAT_HBI_OFFSET + ((ch_end + 8) >> 3);
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++}
++#endif
++
++/*
++ * Initial the MLB module device
++ */
++static inline void mlb150_dev_enable_dma_irq(u32 enable)
++{
++ u32 ch_rx_mask = (1 << SYNC_RX_CL_AHB0) | (1 << CTRL_RX_CL_AHB0)
++ | (1 << ASYNC_RX_CL_AHB0) | (1 << ISOC_RX_CL_AHB0)
++ | (1 << SYNC_TX_CL_AHB0) | (1 << CTRL_TX_CL_AHB0)
++ | (1 << ASYNC_TX_CL_AHB0) | (1 << ISOC_TX_CL_AHB0);
++ u32 ch_tx_mask = (1 << (SYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (SYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_TX_CL_AHB1 - INT_AHB1_CH_START));
++
++ if (enable) {
++ __raw_writel(ch_rx_mask, mlb_base + REG_ACMR0);
++ __raw_writel(ch_tx_mask, mlb_base + REG_ACMR1);
++ } else {
++ __raw_writel(0x0, mlb_base + REG_ACMR0);
++ __raw_writel(0x0, mlb_base + REG_ACMR1);
++ }
++}
++
++
++static void mlb150_dev_init_ir_amba_ahb(void)
++{
++ u32 reg = 0;
++
++ /*
++ * Step 1. Program the ACMRn registers to enable interrupts from all
++ * active DMA channels
++ */
++ mlb150_dev_enable_dma_irq(1);
++
++ /*
++ * Step 2. Select the status clear method:
++ * ACTL.SCE = 0, hardware clears on read
++ * ACTL.SCE = 1, software writes a '1' to clear
++ * We only support DMA MODE 1
++ */
++ reg = __raw_readl(mlb_base + REG_ACTL);
++ reg |= ACTL_DMAMODE;
++#ifdef MULTIPLE_PACKAGE_MODE
++ reg |= REG_ACTL_MPB;
++#endif
++
++ /*
++ * Step 3. Select 1 or 2 interrupt signals:
++ * ACTL.SMX = 0: one interrupt for channels 0 - 31 on ahb_init[0]
++ * and another interrupt for channels 32 - 63 on ahb_init[1]
++ * ACTL.SMX = 1: singel interrupt all channels on ahb_init[0]
++ */
++ reg &= ~ACTL_SMX;
++
++ __raw_writel(reg, mlb_base + REG_ACTL);
++}
++
++static inline void mlb150_dev_enable_ir_mlb(u32 enable)
++{
++ /*
++ * Step 1, Select the MSn to be cleared by software,
++ * writing a '0' to the appropriate bits
++ */
++ __raw_writel(0, mlb_base + REG_MS0);
++ __raw_writel(0, mlb_base + REG_MS1);
++
++ /*
++ * Step 1, Program MIEN to enable protocol error
++ * interrupts for all active MLB channels
++ */
++ if (enable)
++ __raw_writel(MIEN_CTX_PE |
++ MIEN_CRX_PE | MIEN_ATX_PE |
++ MIEN_ARX_PE | MIEN_SYNC_PE |
++ MIEN_ISOC_PE,
++ mlb_base + REG_MIEN);
++ else
++ __raw_writel(0, mlb_base + REG_MIEN);
++}
++
++static inline void mlb150_enable_pll(struct mlb_data *drvdata)
++{
++ u32 c0_val;
++
++ __raw_writel(MLBPC1_VAL,
++ drvdata->membase + REG_MLBPC1);
++
++ c0_val = __raw_readl(drvdata->membase + REG_MLBC0);
++ if (c0_val & MLBC0_MLBPEN) {
++ c0_val &= ~MLBC0_MLBPEN;
++ __raw_writel(c0_val,
++ drvdata->membase + REG_MLBC0);
++ }
++
++ clk_prepare_enable(drvdata->clk_mlb6p);
++
++ c0_val |= (MLBC0_MLBPEN);
++ __raw_writel(c0_val, drvdata->membase + REG_MLBC0);
++}
++
++static inline void mlb150_disable_pll(struct mlb_data *drvdata)
++{
++ u32 c0_val;
++
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ c0_val = __raw_readl(drvdata->membase + REG_MLBC0);
++
++ __raw_writel(0x0, drvdata->membase + REG_MLBPC1);
++
++ c0_val &= ~MLBC0_MLBPEN;
++ __raw_writel(c0_val, drvdata->membase + REG_MLBC0);
++}
++
++static void mlb150_dev_reset_cdt(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM); ++i)
++ mlb150_dev_ctr_write(BUF_CDT_OFFSET + i, ctr_val);
++}
++
++static s32 mlb150_dev_init_ch_cdt(struct mlb_dev_info *pdevinfo, u32 ch,
++ enum MLB_CTYPE ctype, u32 ch_func)
++{
++ u32 cdt_val[4] = { 0 };
++
++ /* a. Set the 14-bit base address (BA) */
++ pr_debug("mxc_mlb150: ctype: %d, ch: %d, dbr_buf_head: 0x%08x",
++ ctype, ch, pdevinfo->channels[ch_func].dbr_buf_head);
++ cdt_val[3] = (pdevinfo->channels[ch_func].dbr_buf_head)
++ << CDT_BA_SHIFT;
++ /*
++ * b. Set the 12-bit or 13-bit buffer depth (BD)
++ * BD = buffer depth in bytes - 1
++ * For synchronous channels: (BD + 1) = 4 * m * bpf
++ * For control channels: (BD + 1) >= max packet length (64)
++ * For asynchronous channels: (BD + 1) >= max packet length
++ * 1024 for a MOST Data packet (MDP);
++ * 1536 for a MOST Ethernet Packet (MEP)
++ * For isochronous channels: (BD + 1) mod (BS + 1) = 0
++ * BS
++ */
++ if (MLB_CTYPE_ISOC == ctype)
++ cdt_val[1] |= (pdevinfo->isoc_blksz - 1);
++ /* BD */
++ cdt_val[3] |= (pdevinfo->cdt_buf_dep - 1) << CDT_BD_SHIFT;
++
++ pr_debug("mxc_mlb150: Set CDT val of channel %d, type: %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ ch, ctype, cdt_val[3], cdt_val[2], cdt_val[1], cdt_val[0]);
++
++ if (mlb150_dev_cdt_write(ch, cdt_val))
++ return -ETIME;
++
++#ifdef DEBUG_CTR
++ {
++ u32 cdt_rd[4] = { 0 };
++ if (!mlb150_dev_cdt_read(ch, cdt_rd)) {
++ pr_debug("mxc_mlb150: CDT val of channel %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ ch, cdt_rd[3], cdt_rd[2], cdt_rd[1], cdt_rd[0]);
++ if (cdt_rd[3] == cdt_val[3] &&
++ cdt_rd[2] == cdt_val[2] &&
++ cdt_rd[1] == cdt_val[1] &&
++ cdt_rd[0] == cdt_val[0]) {
++ pr_debug("mxc_mlb150: set cdt succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set cdt failed!\n");
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: Read CDT val of channel %d failed\n",
++ ch);
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++static s32 mlb150_dev_init_ch_cat(u32 ch, u32 cl,
++ u32 cat_mode, enum MLB_CTYPE ctype)
++{
++ u16 cat_val = 0;
++#ifdef DEBUG_CTR
++ u16 cat_rd = 0;
++#endif
++
++ cat_val = CAT_CE | (ctype << CAT_CT_SHIFT) | cl;
++
++ if (cat_mode & CAT_MODE_OUTBOUND_DMA)
++ cat_val |= CAT_RNW;
++
++ if (MLB_CTYPE_SYNC == ctype)
++ cat_val |= CAT_MT;
++
++ switch (cat_mode) {
++ case CAT_MODE_RX | CAT_MODE_INBOUND_DMA:
++ case CAT_MODE_TX | CAT_MODE_OUTBOUND_DMA:
++ pr_debug("mxc_mlb150: set CAT val of channel %d, type: %d: 0x%04x\n",
++ ch, ctype, cat_val);
++
++ if (mlb150_dev_cat_mlb_write(ch, cat_val))
++ return -ETIME;
++#ifdef DEBUG_CTR
++ if (!mlb150_dev_cat_mlb_read(ch, &cat_rd))
++ pr_debug("mxc_mlb150: CAT val of mlb channel %d: 0x%04x",
++ ch, cat_rd);
++ else {
++ pr_debug("mxc_mlb150: Read CAT of mlb channel %d failed\n",
++ ch);
++ return -EBADE;
++ }
++#endif
++ break;
++ case CAT_MODE_TX | CAT_MODE_INBOUND_DMA:
++ case CAT_MODE_RX | CAT_MODE_OUTBOUND_DMA:
++ pr_debug("mxc_mlb150: set CAT val of channel %d, type: %d: 0x%04x\n",
++ cl, ctype, cat_val);
++
++ if (mlb150_dev_cat_hbi_write(cl, cat_val))
++ return -ETIME;
++#ifdef DEBUG_CTR
++ if (!mlb150_dev_cat_hbi_read(cl, &cat_rd))
++ pr_debug("mxc_mlb150: CAT val of hbi channel %d: 0x%04x",
++ cl, cat_rd);
++ else {
++ pr_debug("mxc_mlb150: Read CAT of hbi channel %d failed\n",
++ cl);
++ return -EBADE;
++ }
++#endif
++ break;
++ default:
++ return EBADRQC;
++ }
++
++#ifdef DEBUG_CTR
++ {
++ if (cat_val == cat_rd) {
++ pr_debug("mxc_mlb150: set cat succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set cat failed!\n");
++ return -EBADE;
++ }
++ }
++#endif
++ return 0;
++}
++
++static void mlb150_dev_reset_cat(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM >> 3); ++i) {
++ mlb150_dev_ctr_write(BUF_CAT_MLB_OFFSET + i, ctr_val);
++ mlb150_dev_ctr_write(BUF_CAT_HBI_OFFSET + i, ctr_val);
++ }
++}
++
++static void mlb150_dev_init_rfb(struct mlb_dev_info *pdevinfo, u32 rx_ch,
++ u32 tx_ch, enum MLB_CTYPE ctype)
++{
++ u32 rx_cl = pdevinfo->channels[RX_CHANNEL].cl;
++ u32 tx_cl = pdevinfo->channels[TX_CHANNEL].cl;
++ /* Step 1, Initialize all bits of CAT to '0' */
++ mlb150_dev_reset_cat();
++ mlb150_dev_reset_cdt();
++ /*
++ * Step 2, Initialize logical channel
++ * Step 3, Program the CDT for channel N
++ */
++ mlb150_dev_init_ch_cdt(pdevinfo, rx_cl, ctype, RX_CHANNEL);
++ mlb150_dev_init_ch_cdt(pdevinfo, tx_cl, ctype, TX_CHANNEL);
++
++ /* Step 4&5, Program the CAT for the inbound and outbound DMA */
++ mlb150_dev_init_ch_cat(rx_ch, rx_cl,
++ CAT_MODE_RX | CAT_MODE_INBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(rx_ch, rx_cl,
++ CAT_MODE_RX | CAT_MODE_OUTBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(tx_ch, tx_cl,
++ CAT_MODE_TX | CAT_MODE_INBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(tx_ch, tx_cl,
++ CAT_MODE_TX | CAT_MODE_OUTBOUND_DMA,
++ ctype);
++}
++
++static void mlb150_dev_reset_adt(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM); ++i)
++ mlb150_dev_ctr_write(BUF_ADT_OFFSET + i, ctr_val);
++}
++
++static void mlb150_dev_reset_whole_ctr(void)
++{
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++ mlb150_dev_reset_cdt();
++ mlb150_dev_reset_adt();
++ mlb150_dev_reset_cat();
++}
++
++#define CLR_REG(reg) __raw_writel(0x0, mlb_base + reg)
++
++static void mlb150_dev_reset_all_regs(void)
++{
++ CLR_REG(REG_MLBC0);
++ CLR_REG(REG_MLBPC0);
++ CLR_REG(REG_MS0);
++ CLR_REG(REG_MS1);
++ CLR_REG(REG_MSS);
++ CLR_REG(REG_MSD);
++ CLR_REG(REG_MIEN);
++ CLR_REG(REG_MLBPC2);
++ CLR_REG(REG_MLBPC1);
++ CLR_REG(REG_MLBC1);
++ CLR_REG(REG_HCTL);
++ CLR_REG(REG_HCMR0);
++ CLR_REG(REG_HCMR1);
++ CLR_REG(REG_HCER0);
++ CLR_REG(REG_HCER1);
++ CLR_REG(REG_HCBR0);
++ CLR_REG(REG_HCBR1);
++ CLR_REG(REG_MDAT0);
++ CLR_REG(REG_MDAT1);
++ CLR_REG(REG_MDAT2);
++ CLR_REG(REG_MDAT3);
++ CLR_REG(REG_MDWE0);
++ CLR_REG(REG_MDWE1);
++ CLR_REG(REG_MDWE2);
++ CLR_REG(REG_MDWE3);
++ CLR_REG(REG_MCTL);
++ CLR_REG(REG_MADR);
++ CLR_REG(REG_ACTL);
++ CLR_REG(REG_ACSR0);
++ CLR_REG(REG_ACSR1);
++ CLR_REG(REG_ACMR0);
++ CLR_REG(REG_ACMR1);
++}
++
++static inline s32 mlb150_dev_pipo_start(struct mlb_ringbuf *rbuf,
++ u32 ahb_ch, u32 buf_addr)
++{
++ u32 ctr_val[4] = { 0 };
++
++ ctr_val[1] |= ADT_RDY1;
++ ctr_val[2] = buf_addr;
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_pipo_next(u32 ahb_ch, enum MLB_CTYPE ctype,
++ u32 dne_sts, u32 buf_addr)
++{
++ u32 ctr_val[4] = { 0 };
++
++ if (MLB_CTYPE_ASYNC == ctype ||
++ MLB_CTYPE_CTRL == ctype) {
++ ctr_val[1] |= ADT_PS1;
++ ctr_val[1] |= ADT_PS2;
++ }
++
++ /*
++ * Clear DNE1 and ERR1
++ * Set the page ready bit (RDY1)
++ */
++ if (dne_sts & ADT_DNE1) {
++ ctr_val[1] |= ADT_RDY2;
++ ctr_val[3] = buf_addr;
++ } else {
++ ctr_val[1] |= ADT_RDY1;
++ ctr_val[2] = buf_addr;
++ }
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_pipo_stop(struct mlb_ringbuf *rbuf, u32 ahb_ch)
++{
++ u32 ctr_val[4] = { 0 };
++ unsigned long flags;
++
++ write_lock_irqsave(&rbuf->rb_lock, flags);
++ rbuf->head = rbuf->tail = 0;
++ write_unlock_irqrestore(&rbuf->rb_lock, flags);
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static s32 mlb150_dev_init_ch_amba_ahb(struct mlb_dev_info *pdevinfo,
++ struct mlb_channel_info *chinfo,
++ enum MLB_CTYPE ctype)
++{
++ u32 ctr_val[4] = { 0 };
++
++ /* a. Set the 32-bit base address (BA1) */
++ ctr_val[3] = 0;
++ ctr_val[2] = 0;
++ ctr_val[1] = (pdevinfo->adt_buf_dep - 1) << ADT_BD1_SHIFT;
++ ctr_val[1] |= (pdevinfo->adt_buf_dep - 1) << ADT_BD2_SHIFT;
++ if (MLB_CTYPE_ASYNC == ctype ||
++ MLB_CTYPE_CTRL == ctype) {
++ ctr_val[1] |= ADT_PS1;
++ ctr_val[1] |= ADT_PS2;
++ }
++
++ ctr_val[0] |= (ADT_LE | ADT_CE);
++
++ pr_debug("mxc_mlb150: Set ADT val of channel %d, ctype: %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ chinfo->cl, ctype, ctr_val[3], ctr_val[2],
++ ctr_val[1], ctr_val[0]);
++
++ if (mlb150_dev_adt_write(chinfo->cl, ctr_val))
++ return -ETIME;
++
++#ifdef DEBUG_CTR
++ {
++ u32 ctr_rd[4] = { 0 };
++ if (!mlb150_dev_adt_read(chinfo->cl, ctr_rd)) {
++ pr_debug("mxc_mlb150: ADT val of channel %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ chinfo->cl, ctr_rd[3], ctr_rd[2],
++ ctr_rd[1], ctr_rd[0]);
++ if (ctr_rd[3] == ctr_val[3] &&
++ ctr_rd[2] == ctr_val[2] &&
++ ctr_rd[1] == ctr_val[1] &&
++ ctr_rd[0] == ctr_val[0]) {
++ pr_debug("mxc_mlb150: set adt succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set adt failed!\n");
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: Read ADT val of channel %d failed\n",
++ chinfo->cl);
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++static void mlb150_dev_init_amba_ahb(struct mlb_dev_info *pdevinfo,
++ enum MLB_CTYPE ctype)
++{
++ struct mlb_channel_info *tx_chinfo = &pdevinfo->channels[TX_CHANNEL];
++ struct mlb_channel_info *rx_chinfo = &pdevinfo->channels[RX_CHANNEL];
++
++ /* Step 1, Initialize all bits of the ADT to '0' */
++ mlb150_dev_reset_adt();
++
++ /*
++ * Step 2, Select a logic channel
++ * Step 3, Program the AMBA AHB block ping page for channel N
++ * Step 4, Program the AMBA AHB block pong page for channel N
++ */
++ mlb150_dev_init_ch_amba_ahb(pdevinfo, rx_chinfo, ctype);
++ mlb150_dev_init_ch_amba_ahb(pdevinfo, tx_chinfo, ctype);
++}
++
++static void mlb150_dev_exit(void)
++{
++ u32 c0_val, hctl_val;
++
++ /* Disable EN bits */
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~(MLBC0_MLBEN | MLBC0_MLBPEN);
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ hctl_val = __raw_readl(mlb_base + REG_HCTL);
++ hctl_val &= ~HCTL_EN;
++ __raw_writel(hctl_val, mlb_base + REG_HCTL);
++
++ __raw_writel(0x0, mlb_base + REG_HCMR0);
++ __raw_writel(0x0, mlb_base + REG_HCMR1);
++
++ mlb150_dev_enable_dma_irq(0);
++ mlb150_dev_enable_ir_mlb(0);
++}
++
++static void mlb150_dev_init(void)
++{
++ u32 c0_val;
++ u32 ch_rx_mask = (1 << SYNC_RX_CL_AHB0) | (1 << CTRL_RX_CL_AHB0)
++ | (1 << ASYNC_RX_CL_AHB0) | (1 << ISOC_RX_CL_AHB0)
++ | (1 << SYNC_TX_CL_AHB0) | (1 << CTRL_TX_CL_AHB0)
++ | (1 << ASYNC_TX_CL_AHB0) | (1 << ISOC_TX_CL_AHB0);
++ u32 ch_tx_mask = (1 << (SYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (SYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_TX_CL_AHB1 - INT_AHB1_CH_START));
++
++ /* Disable EN bits */
++ mlb150_dev_exit();
++
++ /*
++ * Step 1. Initialize CTR and registers
++ * a. Set all bit of the CTR (CAT, CDT, and ADT) to 0.
++ */
++ mlb150_dev_reset_whole_ctr();
++
++ /* a. Set all bit of the CTR (CAT, CDT, and ADT) to 0. */
++ mlb150_dev_reset_all_regs();
++
++ /*
++ * Step 2, Configure the MediaLB interface
++ * Select pin mode and clock, 3-pin and 256fs
++ */
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~(MLBC0_MLBPEN | MLBC0_MLBCLK_MASK);
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ c0_val |= MLBC0_MLBEN;
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ /* Step 3, Configure the HBI interface */
++ __raw_writel(ch_rx_mask, mlb_base + REG_HCMR0);
++ __raw_writel(ch_tx_mask, mlb_base + REG_HCMR1);
++ __raw_writel(HCTL_EN, mlb_base + REG_HCTL);
++
++ mlb150_dev_init_ir_amba_ahb();
++
++ mlb150_dev_enable_ir_mlb(1);
++}
++
++static s32 mlb150_dev_unmute_syn_ch(u32 rx_ch, u32 rx_cl, u32 tx_ch, u32 tx_cl)
++{
++ u32 timeout = 10000;
++
++ /*
++ * Check that MediaLB clock is running (MLBC1.CLKM = 0)
++ * If MLBC1.CLKM = 1, clear the register bit, wait one
++ * APB or I/O clock cycle and repeat the check
++ */
++ while ((__raw_readl(mlb_base + REG_MLBC1) & MLBC1_CLKM)
++ && --timeout)
++ __raw_writel(~MLBC1_CLKM, mlb_base + REG_MLBC1);
++
++ if (0 == timeout)
++ return -ETIME;
++
++ timeout = 10000;
++ /* Poll for MLB lock (MLBC0.MLBLK = 1) */
++ while (!(__raw_readl(mlb_base + REG_MLBC0) & MLBC0_MLBLK)
++ && --timeout)
++ ;
++
++ if (0 == timeout)
++ return -ETIME;
++
++ /* Unmute synchronous channel(s) */
++ mlb150_dev_cat_mlb_write(rx_ch, CAT_CE | rx_cl);
++ mlb150_dev_cat_mlb_write(tx_ch,
++ CAT_CE | tx_cl | CAT_RNW);
++ mlb150_dev_cat_hbi_write(rx_cl,
++ CAT_CE | rx_cl | CAT_RNW);
++ mlb150_dev_cat_hbi_write(tx_cl, CAT_CE | tx_cl);
++
++ return 0;
++}
++
++/* In case the user calls channel shutdown, but rx or tx is not completed yet */
++static s32 mlb150_trans_complete_check(struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ s32 timeout = 1024;
++
++ while (timeout--) {
++ read_lock(&tx_rbuf->rb_lock);
++ if (!CIRC_CNT(tx_rbuf->head, tx_rbuf->tail, TRANS_RING_NODES)) {
++ read_unlock(&tx_rbuf->rb_lock);
++ break;
++ } else
++ read_unlock(&tx_rbuf->rb_lock);
++ }
++
++ if (timeout <= 0) {
++ pr_debug("TX complete check timeout!\n");
++ return -ETIME;
++ }
++
++ timeout = 1024;
++ while (timeout--) {
++ read_lock(&rx_rbuf->rb_lock);
++ if (!CIRC_CNT(rx_rbuf->head, rx_rbuf->tail, TRANS_RING_NODES)) {
++ read_unlock(&rx_rbuf->rb_lock);
++ break;
++ } else
++ read_unlock(&rx_rbuf->rb_lock);
++ }
++
++ if (timeout <= 0) {
++ pr_debug("RX complete check timeout!\n");
++ return -ETIME;
++ }
++
++ /*
++ * Interrupt from TX can only inform that the data is sent
++ * to AHB bus, not mean that it is sent to MITB. Thus we add
++ * a delay here for data to be completed sent.
++ */
++ udelay(1000);
++
++ return 0;
++}
++
++/*
++ * Enable/Disable the MLB IRQ
++ */
++static void mxc_mlb150_irq_enable(struct mlb_data *drvdata, u8 enable)
++{
++ if (enable) {
++ enable_irq(drvdata->irq_ahb0);
++ enable_irq(drvdata->irq_ahb1);
++ enable_irq(drvdata->irq_mlb);
++ } else {
++ disable_irq(drvdata->irq_ahb0);
++ disable_irq(drvdata->irq_ahb1);
++ disable_irq(drvdata->irq_mlb);
++ }
++}
++
++/*
++ * Enable the MLB channel
++ */
++static s32 mlb_channel_enable(struct mlb_data *drvdata,
++ int chan_dev_id, int on)
++{
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_channel_info *tx_chinfo = &pdevinfo->channels[TX_CHANNEL];
++ struct mlb_channel_info *rx_chinfo = &pdevinfo->channels[RX_CHANNEL];
++ u32 tx_ch = tx_chinfo->address;
++ u32 rx_ch = rx_chinfo->address;
++ u32 tx_cl = tx_chinfo->cl;
++ u32 rx_cl = rx_chinfo->cl;
++ s32 ret = 0;
++
++ /*
++ * setup the direction, enable, channel type,
++ * mode select, channel address and mask buf start
++ */
++ if (on) {
++ u32 ctype = pdevinfo->channel_type;
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++ mlb150_dev_init_rfb(pdevinfo, rx_ch, tx_ch, ctype);
++
++ mlb150_dev_init_amba_ahb(pdevinfo, ctype);
++
++#ifdef DEBUG
++ mlb150_dev_dump_ctr_tbl(0, tx_chinfo->cl + 1);
++#endif
++ /* Synchronize and unmute synchrouous channel */
++ if (MLB_CTYPE_SYNC == ctype) {
++ ret = mlb150_dev_unmute_syn_ch(rx_ch, rx_cl,
++ tx_ch, tx_cl);
++ if (ret)
++ return ret;
++ }
++
++ mlb150_dev_enable_ctr_write(0x0, ADT_RDY1 | ADT_DNE1 |
++ ADT_ERR1 | ADT_PS1 |
++ ADT_RDY2 | ADT_DNE2 | ADT_ERR2 | ADT_PS2,
++ 0xffffffff, 0xffffffff);
++
++ if (pdevinfo->fps >= CLK_2048FS)
++ mlb150_enable_pll(drvdata);
++
++ atomic_set(&pdevinfo->on, 1);
++
++#ifdef DEBUG
++ mlb150_dev_dump_reg();
++ mlb150_dev_dump_ctr_tbl(0, tx_chinfo->cl + 1);
++#endif
++ /* Init RX ADT */
++ mlb150_dev_pipo_start(&pdevinfo->rx_rbuf, rx_cl,
++ pdevinfo->rx_rbuf.phy_addrs[0]);
++ } else {
++ mlb150_dev_pipo_stop(&pdevinfo->rx_rbuf, rx_cl);
++
++ mlb150_dev_enable_dma_irq(0);
++ mlb150_dev_enable_ir_mlb(0);
++
++ mlb150_dev_reset_cat();
++
++ atomic_set(&pdevinfo->on, 0);
++
++ if (pdevinfo->fps >= CLK_2048FS)
++ mlb150_disable_pll(drvdata);
++ }
++
++ return 0;
++}
++
++/*
++ * MLB interrupt handler
++ */
++static void mlb_rx_isr(s32 ctype, u32 ahb_ch, struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ s32 head, tail, adt_sts;
++ u32 rx_buf_ptr;
++
++#ifdef DEBUG_RX
++ pr_debug("mxc_mlb150: mlb_rx_isr\n");
++#endif
++
++ read_lock(&rx_rbuf->rb_lock);
++
++ head = (rx_rbuf->head + 1) & (TRANS_RING_NODES - 1);
++ tail = ACCESS_ONCE(rx_rbuf->tail);
++ read_unlock(&rx_rbuf->rb_lock);
++
++ if (CIRC_SPACE(head, tail, TRANS_RING_NODES) >= 1) {
++ rx_buf_ptr = rx_rbuf->phy_addrs[head];
++
++ /* commit the item before incrementing the head */
++ smp_wmb();
++
++ write_lock(&rx_rbuf->rb_lock);
++ rx_rbuf->head = head;
++ write_unlock(&rx_rbuf->rb_lock);
++
++ /* wake up the reader */
++ wake_up_interruptible(&pdevinfo->rx_wq);
++ } else {
++ rx_buf_ptr = rx_rbuf->phy_addrs[head];
++ pr_debug("drop RX package, due to no space, (%d,%d)\n",
++ head, tail);
++ }
++
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++ /* Set ADT for RX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, rx_buf_ptr);
++}
++
++static void mlb_tx_isr(s32 ctype, u32 ahb_ch, struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ s32 head, tail, adt_sts;
++ u32 tx_buf_ptr;
++
++ read_lock(&tx_rbuf->rb_lock);
++
++ head = ACCESS_ONCE(tx_rbuf->head);
++ tail = (tx_rbuf->tail + 1) & (TRANS_RING_NODES - 1);
++ read_unlock(&tx_rbuf->rb_lock);
++
++ smp_mb();
++ write_lock(&tx_rbuf->rb_lock);
++ tx_rbuf->tail = tail;
++ write_unlock(&tx_rbuf->rb_lock);
++
++ /* check the current tx buffer is available or not */
++ if (CIRC_CNT(head, tail, TRANS_RING_NODES) >= 1) {
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ tx_buf_ptr = tx_rbuf->phy_addrs[tail];
++
++ wake_up_interruptible(&pdevinfo->tx_wq);
++
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++ /* Set ADT for TX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, tx_buf_ptr);
++ }
++}
++
++static irqreturn_t mlb_ahb_isr(int irq, void *dev_id)
++{
++ u32 acsr0, hcer0;
++ u32 ch_mask = (1 << SYNC_RX_CL) | (1 << CTRL_RX_CL)
++ | (1 << ASYNC_RX_CL) | (1 << ISOC_RX_CL)
++ | (1 << SYNC_TX_CL) | (1 << CTRL_TX_CL)
++ | (1 << ASYNC_TX_CL) | (1 << ISOC_TX_CL);
++
++ /*
++ * Step 5, Read the ACSRn registers to determine which channel or
++ * channels are causing the interrupt
++ */
++ acsr0 = __raw_readl(mlb_base + REG_ACSR0);
++
++ hcer0 = __raw_readl(mlb_base + REG_HCER0);
++
++ /*
++ * Step 6, If ACTL.SCE = 1, write the result of step 5 back to ACSR0
++ * and ACSR1 to clear the interrupt
++ * We'll not set ACTL_SCE
++ */
++
++ if (ch_mask & hcer0)
++ pr_err("CH encounters an AHB error: 0x%x\n", hcer0);
++
++ if ((1 << SYNC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_SYNC, SYNC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_SYNC]);
++
++ if ((1 << CTRL_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_CTRL, CTRL_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_CTRL]);
++
++ if ((1 << ASYNC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_ASYNC, ASYNC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_ASYNC]);
++
++ if ((1 << ISOC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_ISOC, ISOC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_ISOC]);
++
++ if ((1 << SYNC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_SYNC, SYNC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_SYNC]);
++
++ if ((1 << CTRL_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_CTRL, CTRL_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_CTRL]);
++
++ if ((1 << ASYNC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_ASYNC, ASYNC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_ASYNC]);
++
++ if ((1 << ISOC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_ASYNC, ISOC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_ISOC]);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mlb_isr(int irq, void *dev_id)
++{
++ u32 rx_int_sts, tx_int_sts, ms0,
++ ms1, tx_cis, rx_cis, ctype;
++ int minor;
++ u32 cdt_val[4] = { 0 };
++
++ /*
++ * Step 4, Read the MSn register to determine which channel(s)
++ * are causing the interrupt
++ */
++ ms0 = __raw_readl(mlb_base + REG_MS0);
++ ms1 = __raw_readl(mlb_base + REG_MS1);
++
++ /*
++ * The MLB150_MS0, MLB150_MS1 registers need to be cleared. In
++ * the spec description, the registers should be cleared when
++ * enabling interrupt. In fact, we also should clear it in ISR.
++ */
++ __raw_writel(0, mlb_base + REG_MS0);
++ __raw_writel(0, mlb_base + REG_MS1);
++
++ pr_debug("mxc_mlb150: mlb interrupt:0x%08x 0x%08x\n",
++ (u32)ms0, (u32)ms1);
++
++ for (minor = 0; minor < MLB_MINOR_DEVICES; minor++) {
++ struct mlb_dev_info *pdevinfo = &mlb_devinfo[minor];
++ u32 rx_mlb_ch = pdevinfo->channels[RX_CHANNEL].address;
++ u32 tx_mlb_ch = pdevinfo->channels[TX_CHANNEL].address;
++ u32 rx_mlb_cl = pdevinfo->channels[RX_CHANNEL].cl;
++ u32 tx_mlb_cl = pdevinfo->channels[TX_CHANNEL].cl;
++
++ tx_cis = rx_cis = 0;
++
++ ctype = pdevinfo->channel_type;
++ rx_int_sts = (rx_mlb_ch < 31) ? ms0 : ms1;
++ tx_int_sts = (tx_mlb_ch < 31) ? ms0 : ms1;
++
++ pr_debug("mxc_mlb150: channel interrupt: "
++ "tx %d: 0x%08x, rx %d: 0x%08x\n",
++ tx_mlb_ch, (u32)tx_int_sts, rx_mlb_ch, (u32)rx_int_sts);
++
++ /* Get tx channel interrupt status */
++ if (tx_int_sts & (1 << (tx_mlb_ch % 32))) {
++ mlb150_dev_cdt_read(tx_mlb_cl, cdt_val);
++ pr_debug("mxc_mlb150: TX_CH: %d, cdt_val[3]: 0x%08x, "
++ "cdt_val[2]: 0x%08x, "
++ "cdt_val[1]: 0x%08x, "
++ "cdt_val[0]: 0x%08x\n",
++ tx_mlb_ch, cdt_val[3], cdt_val[2],
++ cdt_val[1], cdt_val[0]);
++ switch (ctype) {
++ case MLB_CTYPE_SYNC:
++ tx_cis = (cdt_val[2] & ~CDT_SYNC_WSTS_MASK)
++ >> CDT_SYNC_WSTS_SHIFT;
++ /*
++ * Clear RSTS/WSTS errors to resume
++ * channel operation
++ * a. For synchronous channels: WSTS[3] = 0
++ */
++ cdt_val[2] &= ~(0x8 << CDT_SYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_CTRL:
++ case MLB_CTYPE_ASYNC:
++ tx_cis = (cdt_val[2] &
++ ~CDT_CTRL_ASYNC_WSTS_MASK)
++ >> CDT_CTRL_ASYNC_WSTS_SHIFT;
++ tx_cis = (cdt_val[3] & CDT_CTRL_ASYNC_WSTS_1) ?
++ (tx_cis | (0x1 << 4)) : tx_cis;
++ /*
++ * b. For async and ctrl channels:
++ * RSTS[4]/WSTS[4] = 0
++ * and RSTS[2]/WSTS[2] = 0
++ */
++ cdt_val[3] &= ~CDT_CTRL_ASYNC_WSTS_1;
++ cdt_val[2] &=
++ ~(0x4 << CDT_CTRL_ASYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_ISOC:
++ tx_cis = (cdt_val[2] & ~CDT_ISOC_WSTS_MASK)
++ >> CDT_ISOC_WSTS_SHIFT;
++ /* c. For isoc channels: WSTS[2:1] = 0x00 */
++ cdt_val[2] &= ~(0x6 << CDT_ISOC_WSTS_SHIFT);
++ break;
++ default:
++ break;
++ }
++ mlb150_dev_cdt_write(tx_mlb_ch, cdt_val);
++ }
++
++ /* Get rx channel interrupt status */
++ if (rx_int_sts & (1 << (rx_mlb_ch % 32))) {
++ mlb150_dev_cdt_read(rx_mlb_cl, cdt_val);
++ pr_debug("mxc_mlb150: RX_CH: %d, cdt_val[3]: 0x%08x, "
++ "cdt_val[2]: 0x%08x, "
++ "cdt_val[1]: 0x%08x, "
++ "cdt_val[0]: 0x%08x\n",
++ rx_mlb_ch, cdt_val[3], cdt_val[2],
++ cdt_val[1], cdt_val[0]);
++ switch (ctype) {
++ case MLB_CTYPE_SYNC:
++ tx_cis = (cdt_val[2] & ~CDT_SYNC_RSTS_MASK)
++ >> CDT_SYNC_RSTS_SHIFT;
++ cdt_val[2] &= ~(0x8 << CDT_SYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_CTRL:
++ case MLB_CTYPE_ASYNC:
++ tx_cis =
++ (cdt_val[2] & ~CDT_CTRL_ASYNC_RSTS_MASK)
++ >> CDT_CTRL_ASYNC_RSTS_SHIFT;
++ tx_cis = (cdt_val[3] & CDT_CTRL_ASYNC_RSTS_1) ?
++ (tx_cis | (0x1 << 4)) : tx_cis;
++ cdt_val[3] &= ~CDT_CTRL_ASYNC_RSTS_1;
++ cdt_val[2] &=
++ ~(0x4 << CDT_CTRL_ASYNC_RSTS_SHIFT);
++ break;
++ case MLB_CTYPE_ISOC:
++ tx_cis = (cdt_val[2] & ~CDT_ISOC_RSTS_MASK)
++ >> CDT_ISOC_RSTS_SHIFT;
++ cdt_val[2] &= ~(0x6 << CDT_ISOC_WSTS_SHIFT);
++ break;
++ default:
++ break;
++ }
++ mlb150_dev_cdt_write(rx_mlb_ch, cdt_val);
++ }
++
++ if (!tx_cis && !rx_cis)
++ continue;
++
++ /* fill exception event */
++ spin_lock(&pdevinfo->event_lock);
++ pdevinfo->ex_event |= (rx_cis << 16) | tx_cis;
++ spin_unlock(&pdevinfo->event_lock);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int mxc_mlb150_open(struct inode *inode, struct file *filp)
++{
++ int minor, ring_buf_size, buf_size, j, ret;
++ void __iomem *buf_addr;
++ ulong phy_addr;
++ struct mlb_dev_info *pdevinfo = NULL;
++ struct mlb_channel_info *pchinfo = NULL;
++ struct mlb_data *drvdata;
++
++ minor = MINOR(inode->i_rdev);
++ drvdata = container_of(inode->i_cdev, struct mlb_data, cdev);
++
++ if (minor < 0 || minor >= MLB_MINOR_DEVICES) {
++ pr_err("no device\n");
++ return -ENODEV;
++ }
++
++ /* open for each channel device */
++ if (atomic_cmpxchg(&mlb_devinfo[minor].opencnt, 0, 1) != 0) {
++ pr_err("busy\n");
++ return -EBUSY;
++ }
++
++ clk_prepare_enable(drvdata->clk_mlb3p);
++
++ /* initial MLB module */
++ mlb150_dev_init();
++
++ pdevinfo = &mlb_devinfo[minor];
++ pchinfo = &pdevinfo->channels[TX_CHANNEL];
++
++ ring_buf_size = pdevinfo->buf_size;
++ buf_size = ring_buf_size * (TRANS_RING_NODES * 2);
++ buf_addr = (void __iomem *)gen_pool_alloc(drvdata->iram_pool, buf_size);
++ if (buf_addr == NULL) {
++ ret = -ENOMEM;
++ pr_err("can not alloc rx/tx buffers: %d\n", buf_size);
++ return ret;
++ }
++ phy_addr = gen_pool_virt_to_phys(drvdata->iram_pool, (ulong)buf_addr);
++ pr_debug("IRAM Range: Virt 0x%p - 0x%p, Phys 0x%x - 0x%x, size: 0x%x\n",
++ buf_addr, (buf_addr + buf_size - 1), (u32)phy_addr,
++ (u32)(phy_addr + buf_size - 1), buf_size);
++ pdevinfo->rbuf_base_virt = buf_addr;
++ pdevinfo->rbuf_base_phy = phy_addr;
++ drvdata->iram_size = buf_size;
++
++ memset(buf_addr, 0, buf_size);
++
++ for (j = 0; j < (TRANS_RING_NODES);
++ ++j, buf_addr += ring_buf_size, phy_addr += ring_buf_size) {
++ pdevinfo->rx_rbuf.virt_bufs[j] = buf_addr;
++ pdevinfo->rx_rbuf.phy_addrs[j] = phy_addr;
++ pr_debug("RX Ringbuf[%d]: 0x%p 0x%x\n",
++ j, buf_addr, (u32)phy_addr);
++ }
++ pdevinfo->rx_rbuf.unit_size = ring_buf_size;
++ pdevinfo->rx_rbuf.total_size = buf_size;
++ for (j = 0; j < (TRANS_RING_NODES);
++ ++j, buf_addr += ring_buf_size, phy_addr += ring_buf_size) {
++ pdevinfo->tx_rbuf.virt_bufs[j] = buf_addr;
++ pdevinfo->tx_rbuf.phy_addrs[j] = phy_addr;
++ pr_debug("TX Ringbuf[%d]: 0x%p 0x%x\n",
++ j, buf_addr, (u32)phy_addr);
++ }
++
++ pdevinfo->tx_rbuf.unit_size = ring_buf_size;
++ pdevinfo->tx_rbuf.total_size = buf_size;
++
++ /* reset the buffer read/write ptr */
++ pdevinfo->rx_rbuf.head = pdevinfo->rx_rbuf.tail = 0;
++ pdevinfo->tx_rbuf.head = pdevinfo->tx_rbuf.tail = 0;
++ pdevinfo->ex_event = 0;
++ pdevinfo->tx_ok = 0;
++
++ init_waitqueue_head(&pdevinfo->rx_wq);
++ init_waitqueue_head(&pdevinfo->tx_wq);
++
++ drvdata = container_of(inode->i_cdev, struct mlb_data, cdev);
++ drvdata->devinfo = pdevinfo;
++ mxc_mlb150_irq_enable(drvdata, 1);
++ filp->private_data = drvdata;
++
++ return 0;
++}
++
++static int mxc_mlb150_release(struct inode *inode, struct file *filp)
++{
++ int minor;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ minor = MINOR(inode->i_rdev);
++ mxc_mlb150_irq_enable(drvdata, 0);
++
++#ifdef DEBUG
++ mlb150_dev_dump_reg();
++ mlb150_dev_dump_ctr_tbl(0, pdevinfo->channels[TX_CHANNEL].cl + 1);
++#endif
++
++ gen_pool_free(drvdata->iram_pool,
++ (ulong)pdevinfo->rbuf_base_virt, drvdata->iram_size);
++
++ mlb150_dev_exit();
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ atomic_set(&pdevinfo->on, 0);
++
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++ /* decrease the open count */
++ atomic_set(&pdevinfo->opencnt, 0);
++
++ drvdata->devinfo = NULL;
++
++ return 0;
++}
++
++static long mxc_mlb150_ioctl(struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ struct inode *inode = filp->f_dentry->d_inode;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ void __user *argp = (void __user *)arg;
++ unsigned long flags, event;
++ int minor;
++
++ minor = MINOR(inode->i_rdev);
++
++ switch (cmd) {
++ case MLB_CHAN_SETADDR:
++ {
++ unsigned int caddr;
++ /* get channel address from user space */
++ if (copy_from_user(&caddr, argp, sizeof(caddr))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++ pdevinfo->channels[TX_CHANNEL].address =
++ (caddr >> 16) & 0xFFFF;
++ pdevinfo->channels[RX_CHANNEL].address = caddr & 0xFFFF;
++ pr_debug("mxc_mlb150: set ch addr, tx: %d, rx: %d\n",
++ pdevinfo->channels[TX_CHANNEL].address,
++ pdevinfo->channels[RX_CHANNEL].address);
++ break;
++ }
++
++ case MLB_CHAN_STARTUP:
++ if (atomic_read(&pdevinfo->on)) {
++ pr_debug("mxc_mlb150: channel alreadly startup\n");
++ break;
++ }
++ if (mlb_channel_enable(drvdata, minor, 1))
++ return -EFAULT;
++ break;
++ case MLB_CHAN_SHUTDOWN:
++ if (atomic_read(&pdevinfo->on) == 0) {
++ pr_debug("mxc_mlb150: channel areadly shutdown\n");
++ break;
++ }
++ mlb150_trans_complete_check(pdevinfo);
++ mlb_channel_enable(drvdata, minor, 0);
++ break;
++ case MLB_CHAN_GETEVENT:
++ /* get and clear the ex_event */
++ spin_lock_irqsave(&pdevinfo->event_lock, flags);
++ event = pdevinfo->ex_event;
++ pdevinfo->ex_event = 0;
++ spin_unlock_irqrestore(&pdevinfo->event_lock, flags);
++
++ if (event) {
++ if (copy_to_user(argp, &event, sizeof(event))) {
++ pr_err("mxc_mlb150: copy to user failed\n");
++ return -EFAULT;
++ }
++ } else
++ return -EAGAIN;
++ break;
++ case MLB_SET_ISOC_BLKSIZE_188:
++ pdevinfo->isoc_blksz = 188;
++ pdevinfo->cdt_buf_dep = pdevinfo->adt_buf_dep =
++ pdevinfo->isoc_blksz * CH_ISOC_BLK_NUM;
++ break;
++ case MLB_SET_ISOC_BLKSIZE_196:
++ pdevinfo->isoc_blksz = 196;
++ pdevinfo->cdt_buf_dep = pdevinfo->adt_buf_dep =
++ pdevinfo->isoc_blksz * CH_ISOC_BLK_NUM;
++ break;
++ case MLB_SET_SYNC_QUAD:
++ {
++ u32 quad;
++
++ if (copy_from_user(&quad, argp, sizeof(quad))) {
++ pr_err("mxc_mlb150: get quad number "
++ "from user failed\n");
++ return -EFAULT;
++ }
++ if (quad <= 0 || quad > 3) {
++ pr_err("mxc_mlb150: Invalid Quadlets!"
++ "Quadlets in Sync mode can "
++ "only be 1, 2, 3\n");
++ return -EINVAL;
++ }
++ pdevinfo->sync_quad = quad;
++ /* Each quadlets is 4 bytes */
++ pdevinfo->cdt_buf_dep = quad * 4 * 4;
++ pdevinfo->adt_buf_dep =
++ pdevinfo->cdt_buf_dep * CH_SYNC_ADT_BUF_MULTI;
++ }
++ break;
++ case MLB_SET_FPS:
++ {
++ u32 fps, c0_val;
++
++ /* get fps from user space */
++ if (copy_from_user(&fps, argp, sizeof(fps))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~MLBC0_MLBCLK_MASK;
++
++ /* check fps value */
++ switch (fps) {
++ case 256:
++ case 512:
++ case 1024:
++ pdevinfo->fps = fps >> 9;
++ c0_val &= ~MLBC0_MLBPEN;
++ c0_val |= (fps >> 9)
++ << MLBC0_MLBCLK_SHIFT;
++
++ if (1024 == fps) {
++ /*
++ * Invert output clock phase
++ * in 1024 fps
++ */
++ __raw_writel(0x1,
++ mlb_base + REG_MLBPC2);
++ }
++ break;
++ case 2048:
++ case 3072:
++ case 4096:
++ pdevinfo->fps = (fps >> 10) + 1;
++ c0_val |= ((fps >> 10) + 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ case 6144:
++ pdevinfo->fps = fps >> 10;
++ c0_val |= ((fps >> 10) + 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ case 8192:
++ pdevinfo->fps = (fps >> 10) - 1;
++ c0_val |= ((fps >> 10) - 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ default:
++ pr_debug("mxc_mlb150: invalid fps argument: %d\n",
++ fps);
++ return -EINVAL;
++ }
++
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ pr_debug("mxc_mlb150: set fps to %d, MLBC0: 0x%08x\n",
++ fps,
++ (u32)__raw_readl(mlb_base + REG_MLBC0));
++
++ break;
++ }
++
++ case MLB_GET_VER:
++ {
++ u32 version;
++
++ /* get MLB device module version */
++ version = 0x03030003;
++
++ pr_debug("mxc_mlb150: get version: 0x%08x\n",
++ version);
++
++ if (copy_to_user(argp, &version, sizeof(version))) {
++ pr_err("mxc_mlb150: copy to user failed\n");
++ return -EFAULT;
++ }
++ break;
++ }
++
++ case MLB_SET_DEVADDR:
++ {
++ u32 c1_val;
++ u8 devaddr;
++
++ /* get MLB device address from user space */
++ if (copy_from_user
++ (&devaddr, argp, sizeof(unsigned char))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ c1_val = __raw_readl(mlb_base + REG_MLBC1);
++ c1_val &= ~MLBC1_NDA_MASK;
++ c1_val |= devaddr << MLBC1_NDA_SHIFT;
++ __raw_writel(c1_val, mlb_base + REG_MLBC1);
++ pr_debug("mxc_mlb150: set dev addr, dev addr: %d, "
++ "MLBC1: 0x%08x\n", devaddr,
++ (u32)__raw_readl(mlb_base + REG_MLBC1));
++
++ break;
++ }
++
++ case MLB_IRQ_DISABLE:
++ {
++ disable_irq(drvdata->irq_mlb);
++ break;
++ }
++
++ case MLB_IRQ_ENABLE:
++ {
++ enable_irq(drvdata->irq_mlb);
++ break;
++ }
++ default:
++ pr_info("mxc_mlb150: Invalid ioctl command\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * MLB read routine
++ * Read the current received data from queued buffer,
++ * and free this buffer for hw to fill ingress data.
++ */
++static ssize_t mxc_mlb150_read(struct file *filp, char __user *buf,
++ size_t count, loff_t *f_pos)
++{
++ int size;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++
++ head = ACCESS_ONCE(rx_rbuf->head);
++ tail = rx_rbuf->tail;
++
++ read_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ /* check the current rx buffer is available or not */
++ if (0 == CIRC_CNT(head, tail, TRANS_RING_NODES)) {
++
++ if (filp->f_flags & O_NONBLOCK)
++ return -EAGAIN;
++
++ do {
++ DEFINE_WAIT(__wait);
++
++ for (;;) {
++ prepare_to_wait(&pdevinfo->rx_wq,
++ &__wait, TASK_INTERRUPTIBLE);
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ if (CIRC_CNT(rx_rbuf->head, rx_rbuf->tail,
++ TRANS_RING_NODES) > 0) {
++ read_unlock_irqrestore(&rx_rbuf->rb_lock,
++ flags);
++ break;
++ }
++ read_unlock_irqrestore(&rx_rbuf->rb_lock,
++ flags);
++
++ if (!signal_pending(current)) {
++ schedule();
++ continue;
++ }
++ return -ERESTARTSYS;
++ }
++ finish_wait(&pdevinfo->rx_wq, &__wait);
++ } while (0);
++ }
++
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ size = pdevinfo->adt_buf_dep;
++ if (size > count) {
++ /* the user buffer is too small */
++ pr_warning
++ ("mxc_mlb150: received data size is bigger than "
++ "size: %d, count: %d\n", size, count);
++ return -EINVAL;
++ }
++
++ /* extract one item from the buffer */
++ if (copy_to_user(buf, rx_rbuf->virt_bufs[tail], size)) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ /* finish reading descriptor before incrementing tail */
++ smp_mb();
++
++ write_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ rx_rbuf->tail = (tail + 1) & (TRANS_RING_NODES - 1);
++ write_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ *f_pos = 0;
++
++ return size;
++}
++
++/*
++ * MLB write routine
++ * Copy the user data to tx channel buffer,
++ * and prepare the channel current/next buffer ptr.
++ */
++static ssize_t mxc_mlb150_write(struct file *filp, const char __user *buf,
++ size_t count, loff_t *f_pos)
++{
++ s32 ret = 0;
++ struct mlb_channel_info *pchinfo = NULL;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++ /*
++ * minor = MINOR(filp->f_dentry->d_inode->i_rdev);
++ */
++ pchinfo = &pdevinfo->channels[TX_CHANNEL];
++
++ if (count > pdevinfo->buf_size) {
++ /* too many data to write */
++ pr_warning("mxc_mlb150: overflow write data\n");
++ return -EFBIG;
++ }
++
++ *f_pos = 0;
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++
++ head = tx_rbuf->head;
++ tail = ACCESS_ONCE(tx_rbuf->tail);
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ if (0 == CIRC_SPACE(head, tail, TRANS_RING_NODES)) {
++ if (filp->f_flags & O_NONBLOCK)
++ return -EAGAIN;
++ do {
++ DEFINE_WAIT(__wait);
++
++ for (;;) {
++ prepare_to_wait(&pdevinfo->tx_wq,
++ &__wait, TASK_INTERRUPTIBLE);
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ if (CIRC_SPACE(tx_rbuf->head, tx_rbuf->tail,
++ TRANS_RING_NODES) > 0) {
++ read_unlock_irqrestore(&tx_rbuf->rb_lock,
++ flags);
++ break;
++ }
++ read_unlock_irqrestore(&tx_rbuf->rb_lock,
++ flags);
++
++ if (!signal_pending(current)) {
++ schedule();
++ continue;
++ }
++ return -ERESTARTSYS;
++ }
++ finish_wait(&pdevinfo->tx_wq, &__wait);
++ } while (0);
++ }
++
++ if (copy_from_user((void *)tx_rbuf->virt_bufs[head], buf, count)) {
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++ pr_err("mxc_mlb: copy from user failed\n");
++ ret = -EFAULT;
++ goto out;
++ }
++
++ write_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ smp_wmb();
++ tx_rbuf->head = (head + 1) & (TRANS_RING_NODES - 1);
++ write_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ if (0 == CIRC_CNT(head, tail, TRANS_RING_NODES)) {
++ u32 tx_buf_ptr, ahb_ch;
++ s32 adt_sts;
++ u32 ctype = pdevinfo->channel_type;
++
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ tx_buf_ptr = tx_rbuf->phy_addrs[tail];
++
++ ahb_ch = pdevinfo->channels[TX_CHANNEL].cl;
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++
++ /* Set ADT for TX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, tx_buf_ptr);
++ }
++
++ ret = count;
++out:
++ return ret;
++}
++
++static unsigned int mxc_mlb150_poll(struct file *filp,
++ struct poll_table_struct *wait)
++{
++ int minor;
++ unsigned int ret = 0;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++
++ minor = MINOR(filp->f_dentry->d_inode->i_rdev);
++
++ poll_wait(filp, &pdevinfo->rx_wq, wait);
++ poll_wait(filp, &pdevinfo->tx_wq, wait);
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ head = tx_rbuf->head;
++ tail = tx_rbuf->tail;
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ /* check the tx buffer is avaiable or not */
++ if (CIRC_SPACE(head, tail, TRANS_RING_NODES) >= 1)
++ ret |= POLLOUT | POLLWRNORM;
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ head = rx_rbuf->head;
++ tail = rx_rbuf->tail;
++ read_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ /* check the rx buffer filled or not */
++ if (CIRC_CNT(head, tail, TRANS_RING_NODES) >= 1)
++ ret |= POLLIN | POLLRDNORM;
++
++
++ /* check the exception event */
++ if (pdevinfo->ex_event)
++ ret |= POLLIN | POLLRDNORM;
++
++ return ret;
++}
++
++/*
++ * char dev file operations structure
++ */
++static const struct file_operations mxc_mlb150_fops = {
++
++ .owner = THIS_MODULE,
++ .open = mxc_mlb150_open,
++ .release = mxc_mlb150_release,
++ .unlocked_ioctl = mxc_mlb150_ioctl,
++ .poll = mxc_mlb150_poll,
++ .read = mxc_mlb150_read,
++ .write = mxc_mlb150_write,
++};
++
++static struct platform_device_id imx_mlb150_devtype[] = {
++ {
++ .name = "imx6q-mlb150",
++ .driver_data = 0,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_mlb150_devtype);
++
++static const struct of_device_id mlb150_imx_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mlb150", .data = &imx_mlb150_devtype[0], },
++ { /* sentinel */ }
++};
++
++/*
++ * This function is called whenever the MLB device is detected.
++ */
++static int mxc_mlb150_probe(struct platform_device *pdev)
++{
++ int ret, mlb_major, i;
++ struct mlb_data *drvdata;
++ struct resource *res;
++ struct device_node *np = pdev->dev.of_node;
++
++ drvdata = devm_kzalloc(&pdev->dev, sizeof(struct mlb_data),
++ GFP_KERNEL);
++ if (!drvdata) {
++ dev_err(&pdev->dev, "can't allocate enough memory\n");
++ return -ENOMEM;
++ }
++
++ /*
++ * Register MLB lld as four character devices
++ */
++ ret = alloc_chrdev_region(&drvdata->firstdev, 0,
++ MLB_MINOR_DEVICES, "mxc_mlb150");
++ if (ret < 0) {
++ dev_err(&pdev->dev, "alloc region error\n");
++ goto err_reg;
++ }
++ mlb_major = MAJOR(drvdata->firstdev);
++ dev_dbg(&pdev->dev, "MLB device major: %d\n", mlb_major);
++
++ cdev_init(&drvdata->cdev, &mxc_mlb150_fops);
++ drvdata->cdev.owner = THIS_MODULE;
++
++ ret = cdev_add(&drvdata->cdev, drvdata->firstdev, MLB_MINOR_DEVICES);
++ if (ret) {
++ dev_err(&pdev->dev, "can't add cdev\n");
++ goto err_reg;
++ }
++
++ /* create class and device for udev information */
++ drvdata->class = class_create(THIS_MODULE, "mlb150");
++ if (IS_ERR(drvdata->class)) {
++ dev_err(&pdev->dev, "failed to create device class\n");
++ ret = -ENOMEM;
++ goto err_class;
++ }
++
++ for (i = 0; i < MLB_MINOR_DEVICES; i++) {
++ struct device *class_dev;
++
++ class_dev = device_create(drvdata->class, NULL,
++ MKDEV(mlb_major, i),
++ NULL, mlb_devinfo[i].dev_name);
++ if (IS_ERR(class_dev)) {
++ dev_err(&pdev->dev, "failed to create mlb150 %s"
++ " class device\n", mlb_devinfo[i].dev_name);
++ ret = -ENOMEM;
++ goto err_dev;
++ }
++ }
++
++ /* ahb0 irq */
++ drvdata->irq_ahb0 = platform_get_irq(pdev, 1);
++ if (drvdata->irq_ahb0 < 0) {
++ dev_err(&pdev->dev, "No ahb0 irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "ahb0_irq: %d\n", drvdata->irq_ahb0);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_ahb0, mlb_ahb_isr,
++ 0, "mlb_ahb0", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_ahb0);
++ goto err_dev;
++ }
++
++ /* ahb1 irq */
++ drvdata->irq_ahb1 = platform_get_irq(pdev, 2);
++ if (drvdata->irq_ahb1 < 0) {
++ dev_err(&pdev->dev, "No ahb1 irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "ahb1_irq: %d\n", drvdata->irq_ahb1);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_ahb1, mlb_ahb_isr,
++ 0, "mlb_ahb1", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_ahb1);
++ goto err_dev;
++ }
++
++ /* mlb irq */
++ drvdata->irq_mlb = platform_get_irq(pdev, 0);
++ if (drvdata->irq_mlb < 0) {
++ dev_err(&pdev->dev, "No mlb irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "mlb_irq: %d\n", drvdata->irq_mlb);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_mlb, mlb_isr,
++ 0, "mlb", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_mlb);
++ goto err_dev;
++ }
++
++ /* ioremap from phy mlb to kernel space */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "can't get device resources\n");
++ ret = -ENOENT;
++ goto err_dev;
++ }
++ mlb_base = devm_request_and_ioremap(&pdev->dev, res);
++ dev_dbg(&pdev->dev, "mapped base address: 0x%08x\n", (u32)mlb_base);
++ if (IS_ERR(mlb_base)) {
++ dev_err(&pdev->dev,
++ "failed to get ioremap base\n");
++ ret = PTR_ERR(mlb_base);
++ goto err_dev;
++ }
++ drvdata->membase = mlb_base;
++
++#ifdef CONFIG_REGULATOR
++ drvdata->nvcc = devm_regulator_get(&pdev->dev, "reg_nvcc");
++ if (!IS_ERR(drvdata->nvcc)) {
++ regulator_set_voltage(drvdata->nvcc, 2500000, 2500000);
++ dev_err(&pdev->dev, "enalbe regulator\n");
++ ret = regulator_enable(drvdata->nvcc);
++ if (ret) {
++ dev_err(&pdev->dev, "vdd set voltage error\n");
++ goto err_dev;
++ }
++ }
++#endif
++
++ /* enable clock */
++ drvdata->clk_mlb3p = devm_clk_get(&pdev->dev, "mlb");
++ if (IS_ERR(drvdata->clk_mlb3p)) {
++ dev_err(&pdev->dev, "unable to get mlb clock\n");
++ ret = PTR_ERR(drvdata->clk_mlb3p);
++ goto err_dev;
++ }
++
++ drvdata->clk_mlb6p = devm_clk_get(&pdev->dev, "pll8_mlb");
++ if (IS_ERR(drvdata->clk_mlb6p)) {
++ dev_err(&pdev->dev, "unable to get mlb pll clock\n");
++ ret = PTR_ERR(drvdata->clk_mlb6p);
++ goto err_dev;
++ }
++
++
++ drvdata->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!drvdata->iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ ret = -ENOMEM;
++ goto err_dev;
++ }
++
++ drvdata->devinfo = NULL;
++ mxc_mlb150_irq_enable(drvdata, 0);
++ platform_set_drvdata(pdev, drvdata);
++ return 0;
++
++err_dev:
++ for (--i; i >= 0; i--)
++ device_destroy(drvdata->class, MKDEV(mlb_major, i));
++
++ class_destroy(drvdata->class);
++err_class:
++ cdev_del(&drvdata->cdev);
++err_reg:
++ unregister_chrdev_region(drvdata->firstdev, MLB_MINOR_DEVICES);
++
++ return ret;
++}
++
++static int mxc_mlb150_remove(struct platform_device *pdev)
++{
++ int i;
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt))
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++
++ /* disable mlb power */
++#ifdef CONFIG_REGULATOR
++ if (!IS_ERR(drvdata->nvcc))
++ regulator_disable(drvdata->nvcc);
++#endif
++
++ /* destroy mlb device class */
++ for (i = MLB_MINOR_DEVICES - 1; i >= 0; i--)
++ device_destroy(drvdata->class,
++ MKDEV(MAJOR(drvdata->firstdev), i));
++ class_destroy(drvdata->class);
++
++ cdev_del(&drvdata->cdev);
++
++ /* Unregister the two MLB devices */
++ unregister_chrdev_region(drvdata->firstdev, MLB_MINOR_DEVICES);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int mxc_mlb150_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt)) {
++ mlb150_dev_exit();
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++ }
++
++ return 0;
++}
++
++static int mxc_mlb150_resume(struct platform_device *pdev)
++{
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt)) {
++ clk_prepare_enable(drvdata->clk_mlb3p);
++ mlb150_dev_init();
++ }
++
++ if (pdevinfo && atomic_read(&pdevinfo->on) &&
++ (pdevinfo->fps >= CLK_2048FS))
++ clk_prepare_enable(drvdata->clk_mlb6p);
++
++ return 0;
++}
++#else
++#define mxc_mlb150_suspend NULL
++#define mxc_mlb150_resume NULL
++#endif
++
++/*
++ * platform driver structure for MLB
++ */
++static struct platform_driver mxc_mlb150_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = mlb150_imx_dt_ids,
++ },
++ .probe = mxc_mlb150_probe,
++ .remove = mxc_mlb150_remove,
++ .suspend = mxc_mlb150_suspend,
++ .resume = mxc_mlb150_resume,
++ .id_table = imx_mlb150_devtype,
++};
++
++static int __init mxc_mlb150_init(void)
++{
++ return platform_driver_register(&mxc_mlb150_driver);
++}
++
++static void __exit mxc_mlb150_exit(void)
++{
++ platform_driver_unregister(&mxc_mlb150_driver);
++}
++
++module_init(mxc_mlb150_init);
++module_exit(mxc_mlb150_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MLB150 low level driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/mxc/vpu/Kconfig linux-linaro-stable-mx6/drivers/mxc/vpu/Kconfig
+--- linux-3.10.30.orig/drivers/mxc/vpu/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/vpu/Kconfig 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,31 @@
++#
++# Codec configuration
++#
++
++menu "MXC VPU(Video Processing Unit) support"
++
++config MXC_VPU
++ tristate "Support for MXC VPU(Video Processing Unit)"
++ depends on (SOC_IMX27 || SOC_IMX5 || SOC_IMX6Q)
++ default y
++ ---help---
++ The VPU codec device provides codec function for H.264/MPEG4/H.263,
++ as well as MPEG2/VC-1/DivX on some platforms.
++
++config MXC_VPU_DEBUG
++ bool "MXC VPU debugging"
++ depends on MXC_VPU != n
++ help
++ This is an option for the developers; most people should
++ say N here. This enables MXC VPU driver debugging.
++
++config MX6_VPU_352M
++ bool "MX6 VPU 352M"
++ depends on MXC_VPU
++ default n
++ help
++ Increase VPU frequncy to 352M, the config will disable bus frequency
++ adjust dynamic, and CPU lowest setpoint will be 352Mhz.
++ This config is used for special VPU use case.
++
++endmenu
+diff -Nur linux-3.10.30.orig/drivers/mxc/vpu/Makefile linux-linaro-stable-mx6/drivers/mxc/vpu/Makefile
+--- linux-3.10.30.orig/drivers/mxc/vpu/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/vpu/Makefile 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,9 @@
++#
++# Makefile for the VPU drivers.
++#
++
++obj-$(CONFIG_MXC_VPU) += mxc_vpu.o
++
++ifeq ($(CONFIG_MXC_VPU_DEBUG),y)
++EXTRA_CFLAGS += -DDEBUG
++endif
+diff -Nur linux-3.10.30.orig/drivers/mxc/vpu/mxc_vpu.c linux-linaro-stable-mx6/drivers/mxc/vpu/mxc_vpu.c
+--- linux-3.10.30.orig/drivers/mxc/vpu/mxc_vpu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/mxc/vpu/mxc_vpu.c 2014-05-15 20:33:58.658018622 +0200
+@@ -0,0 +1,1342 @@
++/*
++ * Copyright 2006-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_vpu.c
++ *
++ * @brief VPU system initialization and file operation implementation
++ *
++ * @ingroup VPU
++ */
++
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/stat.h>
++#include <linux/platform_device.h>
++#include <linux/kdev_t.h>
++#include <linux/dma-mapping.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/uaccess.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/workqueue.h>
++#include <linux/sched.h>
++#include <linux/vmalloc.h>
++#include <linux/regulator/consumer.h>
++#include <linux/page-flags.h>
++#include <linux/mm_types.h>
++#include <linux/types.h>
++#include <linux/memblock.h>
++#include <linux/memory.h>
++#include <linux/version.h>
++#include <asm/page.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++#include <linux/module.h>
++#include <linux/pm_runtime.h>
++#include <linux/sizes.h>
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
++#include <linux/iram_alloc.h>
++#include <mach/clock.h>
++#include <mach/hardware.h>
++#include <mach/mxc_vpu.h>
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/genalloc.h>
++#include <linux/mxc_vpu.h>
++#include <linux/of.h>
++#include <linux/reset.h>
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++#include <mach/busfreq.h>
++#include <mach/common.h>
++#else
++#include <asm/sizes.h>
++#endif
++
++/* Define one new pgprot which combined uncached and XN(never executable) */
++#define pgprot_noncachedxn(prot) \
++ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
++
++struct vpu_priv {
++ struct fasync_struct *async_queue;
++ struct work_struct work;
++ struct workqueue_struct *workqueue;
++ struct mutex lock;
++};
++
++/* To track the allocated memory buffer */
++struct memalloc_record {
++ struct list_head list;
++ struct vpu_mem_desc mem;
++};
++
++struct iram_setting {
++ u32 start;
++ u32 end;
++};
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static struct gen_pool *iram_pool;
++static u32 iram_base;
++#endif
++
++static LIST_HEAD(head);
++
++static int vpu_major;
++static int vpu_clk_usercount;
++static struct class *vpu_class;
++static struct vpu_priv vpu_data;
++static u8 open_count;
++static struct clk *vpu_clk;
++static struct vpu_mem_desc bitwork_mem = { 0 };
++static struct vpu_mem_desc pic_para_mem = { 0 };
++static struct vpu_mem_desc user_data_mem = { 0 };
++static struct vpu_mem_desc share_mem = { 0 };
++static struct vpu_mem_desc vshare_mem = { 0 };
++
++static void __iomem *vpu_base;
++static int vpu_ipi_irq;
++static u32 phy_vpu_base_addr;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++static phys_addr_t top_address_DRAM;
++static struct mxc_vpu_platform_data *vpu_plat;
++#endif
++
++static struct device *vpu_dev;
++
++/* IRAM setting */
++static struct iram_setting iram;
++
++/* implement the blocking ioctl */
++static int irq_status;
++static int codec_done;
++static wait_queue_head_t vpu_queue;
++
++#ifdef CONFIG_SOC_IMX6Q
++#define MXC_VPU_HAS_JPU
++#endif
++
++#ifdef MXC_VPU_HAS_JPU
++static int vpu_jpu_irq;
++#endif
++
++#ifdef CONFIG_PM
++static unsigned int regBk[64];
++static unsigned int pc_before_suspend;
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static struct regulator *vpu_regulator;
++#endif
++static atomic_t clk_cnt_from_ioc = ATOMIC_INIT(0);
++
++#define READ_REG(x) readl_relaxed(vpu_base + x)
++#define WRITE_REG(val, x) writel_relaxed(val, vpu_base + x)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++/* redirect to static functions */
++static int cpu_is_mx6dl(void)
++{
++ int ret;
++ ret = of_machine_is_compatible("fsl,imx6dl");
++ return ret;
++}
++
++static int cpu_is_mx6q(void)
++{
++ int ret;
++ ret = of_machine_is_compatible("fsl,imx6q");
++ return ret;
++}
++#endif
++
++static void vpu_reset(void)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ device_reset(vpu_dev);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ imx_src_reset_vpu();
++#else
++ if (vpu_plat->reset)
++ vpu_plat->reset();
++#endif
++}
++
++static long vpu_power_get(bool on)
++{
++ long ret = 0;
++
++ if (on) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ vpu_regulator = regulator_get(NULL, "cpu_vddvpu");
++ ret = IS_ERR(vpu_regulator);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ vpu_regulator = devm_regulator_get(vpu_dev, "pu");
++ ret = IS_ERR(vpu_regulator);
++#endif
++ } else {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (!IS_ERR(vpu_regulator))
++ regulator_put(vpu_regulator);
++#endif
++ }
++ return ret;
++}
++
++static void vpu_power_up(bool on)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ int ret = 0;
++
++ if (on) {
++ if (!IS_ERR(vpu_regulator)) {
++ ret = regulator_enable(vpu_regulator);
++ if (ret)
++ dev_err(vpu_dev, "failed to power up vpu\n");
++ }
++ } else {
++ if (!IS_ERR(vpu_regulator)) {
++ ret = regulator_disable(vpu_regulator);
++ if (ret)
++ dev_err(vpu_dev, "failed to power down vpu\n");
++ }
++ }
++#else
++ imx_gpc_power_up_pu(on);
++#endif
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static int cpu_is_mx53(void)
++{
++ return 0;
++}
++
++static int cpu_is_mx51(void)
++{
++ return 0;
++}
++
++#define VM_RESERVED 0
++#endif
++
++/*!
++ * Private function to alloc dma buffer
++ * @return status 0 success.
++ */
++static int vpu_alloc_dma_buffer(struct vpu_mem_desc *mem)
++{
++ mem->cpu_addr = (unsigned long)
++ dma_alloc_coherent(NULL, PAGE_ALIGN(mem->size),
++ (dma_addr_t *) (&mem->phy_addr),
++ GFP_DMA | GFP_KERNEL);
++ dev_dbg(vpu_dev, "[ALLOC] mem alloc cpu_addr = 0x%x\n", mem->cpu_addr);
++ if ((void *)(mem->cpu_addr) == NULL) {
++ dev_err(vpu_dev, "Physical memory allocation error!\n");
++ return -1;
++ }
++ return 0;
++}
++
++/*!
++ * Private function to free dma buffer
++ */
++static void vpu_free_dma_buffer(struct vpu_mem_desc *mem)
++{
++ if (mem->cpu_addr != 0) {
++ dma_free_coherent(0, PAGE_ALIGN(mem->size),
++ (void *)mem->cpu_addr, mem->phy_addr);
++ }
++}
++
++/*!
++ * Private function to free buffers
++ * @return status 0 success.
++ */
++static int vpu_free_buffers(void)
++{
++ struct memalloc_record *rec, *n;
++ struct vpu_mem_desc mem;
++
++ list_for_each_entry_safe(rec, n, &head, list) {
++ mem = rec->mem;
++ if (mem.cpu_addr != 0) {
++ vpu_free_dma_buffer(&mem);
++ dev_dbg(vpu_dev, "[FREE] freed paddr=0x%08X\n", mem.phy_addr);
++ /* delete from list */
++ list_del(&rec->list);
++ kfree(rec);
++ }
++ }
++
++ return 0;
++}
++
++static inline void vpu_worker_callback(struct work_struct *w)
++{
++ struct vpu_priv *dev = container_of(w, struct vpu_priv,
++ work);
++
++ if (dev->async_queue)
++ kill_fasync(&dev->async_queue, SIGIO, POLL_IN);
++
++ irq_status = 1;
++ /*
++ * Clock is gated on when dec/enc started, gate it off when
++ * codec is done.
++ */
++ if (codec_done)
++ codec_done = 0;
++
++ wake_up_interruptible(&vpu_queue);
++}
++
++/*!
++ * @brief vpu interrupt handler
++ */
++static irqreturn_t vpu_ipi_irq_handler(int irq, void *dev_id)
++{
++ struct vpu_priv *dev = dev_id;
++ unsigned long reg;
++
++ reg = READ_REG(BIT_INT_REASON);
++ if (reg & 0x8)
++ codec_done = 1;
++ WRITE_REG(0x1, BIT_INT_CLEAR);
++
++ queue_work(dev->workqueue, &dev->work);
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * @brief vpu jpu interrupt handler
++ */
++#ifdef MXC_VPU_HAS_JPU
++static irqreturn_t vpu_jpu_irq_handler(int irq, void *dev_id)
++{
++ struct vpu_priv *dev = dev_id;
++ unsigned long reg;
++
++ reg = READ_REG(MJPEG_PIC_STATUS_REG);
++ if (reg & 0x3)
++ codec_done = 1;
++
++ queue_work(dev->workqueue, &dev->work);
++
++ return IRQ_HANDLED;
++}
++#endif
++
++/*!
++ * @brief check phy memory prepare to pass to vpu is valid or not, we
++ * already address some issue that if pass a wrong address to vpu
++ * (like virtual address), system will hang.
++ *
++ * @return true return is a valid phy memory address, false return not.
++ */
++bool vpu_is_valid_phy_memory(u32 paddr)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (paddr > top_address_DRAM)
++ return false;
++#endif
++
++ return true;
++}
++
++/*!
++ * @brief open function for vpu file operation
++ *
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_open(struct inode *inode, struct file *filp)
++{
++
++ mutex_lock(&vpu_data.lock);
++
++ if (open_count++ == 0) {
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_get_sync(vpu_dev);
++#endif
++ vpu_power_up(true);
++
++#ifdef CONFIG_SOC_IMX6Q
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_CUR_PC))
++ dev_dbg(vpu_dev, "Not power off before vpu open!\n");
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++#endif
++ }
++
++ filp->private_data = (void *)(&vpu_data);
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++/*!
++ * @brief IO ctrl function for vpu file operation
++ * @param cmd IO ctrl command
++ * @return 0 on success or negative error code on error
++ */
++static long vpu_ioctl(struct file *filp, u_int cmd,
++ u_long arg)
++{
++ int ret = 0;
++
++ switch (cmd) {
++ case VPU_IOC_PHYMEM_ALLOC:
++ {
++ struct memalloc_record *rec;
++
++ rec = kzalloc(sizeof(*rec), GFP_KERNEL);
++ if (!rec)
++ return -ENOMEM;
++
++ ret = copy_from_user(&(rec->mem),
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ kfree(rec);
++ return -EFAULT;
++ }
++
++ dev_dbg(vpu_dev, "[ALLOC] mem alloc size = 0x%x\n",
++ rec->mem.size);
++
++ ret = vpu_alloc_dma_buffer(&(rec->mem));
++ if (ret == -1) {
++ kfree(rec);
++ dev_err(vpu_dev,
++ "Physical memory allocation error!\n");
++ break;
++ }
++ ret = copy_to_user((void __user *)arg, &(rec->mem),
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ kfree(rec);
++ ret = -EFAULT;
++ break;
++ }
++
++ mutex_lock(&vpu_data.lock);
++ list_add(&rec->list, &head);
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ case VPU_IOC_PHYMEM_FREE:
++ {
++ struct memalloc_record *rec, *n;
++ struct vpu_mem_desc vpu_mem;
++
++ ret = copy_from_user(&vpu_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret)
++ return -EACCES;
++
++ dev_dbg(vpu_dev, "[FREE] mem freed cpu_addr = 0x%x\n",
++ vpu_mem.cpu_addr);
++ if ((void *)vpu_mem.cpu_addr != NULL)
++ vpu_free_dma_buffer(&vpu_mem);
++
++ mutex_lock(&vpu_data.lock);
++ list_for_each_entry_safe(rec, n, &head, list) {
++ if (rec->mem.cpu_addr == vpu_mem.cpu_addr) {
++ /* delete from list */
++ list_del(&rec->list);
++ kfree(rec);
++ break;
++ }
++ }
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ case VPU_IOC_WAIT4INT:
++ {
++ u_long timeout = (u_long) arg;
++ if (!wait_event_interruptible_timeout
++ (vpu_queue, irq_status != 0,
++ msecs_to_jiffies(timeout))) {
++ dev_warn(vpu_dev, "VPU blocking: timeout.\n");
++ ret = -ETIME;
++ } else if (signal_pending(current)) {
++ dev_warn(vpu_dev, "VPU interrupt received.\n");
++ ret = -ERESTARTSYS;
++ } else
++ irq_status = 0;
++ break;
++ }
++ case VPU_IOC_IRAM_SETTING:
++ {
++ ret = copy_to_user((void __user *)arg, &iram,
++ sizeof(struct iram_setting));
++ if (ret)
++ ret = -EFAULT;
++
++ break;
++ }
++ case VPU_IOC_CLKGATE_SETTING:
++ {
++ u32 clkgate_en;
++
++ if (get_user(clkgate_en, (u32 __user *) arg))
++ return -EFAULT;
++
++ if (clkgate_en) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ atomic_inc(&clk_cnt_from_ioc);
++ } else {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ atomic_dec(&clk_cnt_from_ioc);
++ }
++
++ break;
++ }
++ case VPU_IOC_GET_SHARE_MEM:
++ {
++ mutex_lock(&vpu_data.lock);
++ if (share_mem.cpu_addr != 0) {
++ ret = copy_to_user((void __user *)arg,
++ &share_mem,
++ sizeof(struct vpu_mem_desc));
++ mutex_unlock(&vpu_data.lock);
++ break;
++ } else {
++ if (copy_from_user(&share_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc))) {
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++ if (vpu_alloc_dma_buffer(&share_mem) == -1)
++ ret = -EFAULT;
++ else {
++ if (copy_to_user((void __user *)arg,
++ &share_mem,
++ sizeof(struct
++ vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ }
++ mutex_unlock(&vpu_data.lock);
++ break;
++ }
++ case VPU_IOC_REQ_VSHARE_MEM:
++ {
++ mutex_lock(&vpu_data.lock);
++ if (vshare_mem.cpu_addr != 0) {
++ ret = copy_to_user((void __user *)arg,
++ &vshare_mem,
++ sizeof(struct vpu_mem_desc));
++ mutex_unlock(&vpu_data.lock);
++ break;
++ } else {
++ if (copy_from_user(&vshare_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct
++ vpu_mem_desc))) {
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++ /* vmalloc shared memory if not allocated */
++ if (!vshare_mem.cpu_addr)
++ vshare_mem.cpu_addr =
++ (unsigned long)
++ vmalloc_user(vshare_mem.size);
++ if (copy_to_user
++ ((void __user *)arg, &vshare_mem,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ mutex_unlock(&vpu_data.lock);
++ break;
++ }
++ case VPU_IOC_GET_WORK_ADDR:
++ {
++ if (bitwork_mem.cpu_addr != 0) {
++ ret =
++ copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct vpu_mem_desc));
++ break;
++ } else {
++ if (copy_from_user(&bitwork_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc)))
++ return -EFAULT;
++
++ if (vpu_alloc_dma_buffer(&bitwork_mem) == -1)
++ ret = -EFAULT;
++ else if (copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct
++ vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ break;
++ }
++ /*
++ * The following two ioctl is used when user allocates working buffer
++ * and register it to vpu driver.
++ */
++ case VPU_IOC_QUERY_BITWORK_MEM:
++ {
++ if (copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ break;
++ }
++ case VPU_IOC_SET_BITWORK_MEM:
++ {
++ if (copy_from_user(&bitwork_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ break;
++ }
++ case VPU_IOC_SYS_SW_RESET:
++ {
++ vpu_reset();
++ break;
++ }
++ case VPU_IOC_REG_DUMP:
++ break;
++ case VPU_IOC_PHYMEM_DUMP:
++ break;
++ case VPU_IOC_PHYMEM_CHECK:
++ {
++ struct vpu_mem_desc check_memory;
++ ret = copy_from_user(&check_memory,
++ (void __user *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret != 0) {
++ dev_err(vpu_dev, "copy from user failure:%d\n", ret);
++ ret = -EFAULT;
++ break;
++ }
++ ret = vpu_is_valid_phy_memory((u32)check_memory.phy_addr);
++
++ dev_dbg(vpu_dev, "vpu: memory phy:0x%x %s phy memory\n",
++ check_memory.phy_addr, (ret ? "is" : "isn't"));
++ /* borrow .size to pass back the result. */
++ check_memory.size = ret;
++ ret = copy_to_user((void __user *)arg, &check_memory,
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ ret = -EFAULT;
++ break;
++ }
++ break;
++ }
++ case VPU_IOC_LOCK_DEV:
++ {
++ u32 lock_en;
++
++ if (get_user(lock_en, (u32 __user *) arg))
++ return -EFAULT;
++
++ if (lock_en)
++ mutex_lock(&vpu_data.lock);
++ else
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ default:
++ {
++ dev_err(vpu_dev, "No such IOCTL, cmd is %d\n", cmd);
++ ret = -EINVAL;
++ break;
++ }
++ }
++ return ret;
++}
++
++/*!
++ * @brief Release function for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_release(struct inode *inode, struct file *filp)
++{
++ int i;
++ unsigned long timeout;
++
++ mutex_lock(&vpu_data.lock);
++
++ if (open_count > 0 && !(--open_count)) {
++
++ /* Wait for vpu go to idle state */
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_CUR_PC)) {
++
++ timeout = jiffies + HZ;
++ while (READ_REG(BIT_BUSY_FLAG)) {
++ msleep(1);
++ if (time_after(jiffies, timeout)) {
++ dev_warn(vpu_dev, "VPU timeout during release\n");
++ break;
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ /* Clean up interrupt */
++ cancel_work_sync(&vpu_data.work);
++ flush_workqueue(vpu_data.workqueue);
++ irq_status = 0;
++
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_BUSY_FLAG)) {
++
++ if (cpu_is_mx51() || cpu_is_mx53()) {
++ dev_err(vpu_dev,
++ "fatal error: can't gate/power off when VPU is busy\n");
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++
++#ifdef CONFIG_SOC_IMX6Q
++ if (cpu_is_mx6dl() || cpu_is_mx6q()) {
++ WRITE_REG(0x11, 0x10F0);
++ timeout = jiffies + HZ;
++ while (READ_REG(0x10F4) != 0x77) {
++ msleep(1);
++ if (time_after(jiffies, timeout))
++ break;
++ }
++
++ if (READ_REG(0x10F4) != 0x77) {
++ dev_err(vpu_dev,
++ "fatal error: can't gate/power off when VPU is busy\n");
++ WRITE_REG(0x0, 0x10F0);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ } else
++ vpu_reset();
++ }
++#endif
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ vpu_free_buffers();
++
++ /* Free shared memory when vpu device is idle */
++ vpu_free_dma_buffer(&share_mem);
++ share_mem.cpu_addr = 0;
++ vfree((void *)vshare_mem.cpu_addr);
++ vshare_mem.cpu_addr = 0;
++
++ vpu_clk_usercount = atomic_read(&clk_cnt_from_ioc);
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ atomic_dec(&clk_cnt_from_ioc);
++ }
++
++ vpu_power_up(false);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_put_sync_suspend(vpu_dev);
++#endif
++
++ }
++ mutex_unlock(&vpu_data.lock);
++
++ return 0;
++}
++
++/*!
++ * @brief fasync function for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_fasync(int fd, struct file *filp, int mode)
++{
++ struct vpu_priv *dev = (struct vpu_priv *)filp->private_data;
++ return fasync_helper(fd, filp, mode, &dev->async_queue);
++}
++
++/*!
++ * @brief memory map function of harware registers for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_hwregs(struct file *fp, struct vm_area_struct *vm)
++{
++ unsigned long pfn;
++
++ vm->vm_flags |= VM_IO | VM_RESERVED;
++ /*
++ * Since vpu registers have been mapped with ioremap() at probe
++ * which L_PTE_XN is 1, and the same physical address must be
++ * mapped multiple times with same type, so set L_PTE_XN to 1 here.
++ * Otherwise, there may be unexpected result in video codec.
++ */
++ vm->vm_page_prot = pgprot_noncachedxn(vm->vm_page_prot);
++ pfn = phy_vpu_base_addr >> PAGE_SHIFT;
++ dev_dbg(vpu_dev, "size=0x%x, page no.=0x%x\n",
++ (int)(vm->vm_end - vm->vm_start), (int)pfn);
++ return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end - vm->vm_start,
++ vm->vm_page_prot) ? -EAGAIN : 0;
++}
++
++/*!
++ * @brief memory map function of memory for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_dma_mem(struct file *fp, struct vm_area_struct *vm)
++{
++ int request_size;
++ request_size = vm->vm_end - vm->vm_start;
++
++ dev_dbg(vpu_dev, "start=0x%x, pgoff=0x%x, size=0x%x\n",
++ (unsigned int)(vm->vm_start), (unsigned int)(vm->vm_pgoff),
++ request_size);
++
++ vm->vm_flags |= VM_IO | VM_RESERVED;
++ vm->vm_page_prot = pgprot_writecombine(vm->vm_page_prot);
++
++ return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff,
++ request_size, vm->vm_page_prot) ? -EAGAIN : 0;
++
++}
++
++/* !
++ * @brief memory map function of vmalloced share memory
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_vshare_mem(struct file *fp, struct vm_area_struct *vm)
++{
++ int ret = -EINVAL;
++
++ ret = remap_vmalloc_range(vm, (void *)(vm->vm_pgoff << PAGE_SHIFT), 0);
++ vm->vm_flags |= VM_IO;
++
++ return ret;
++}
++/*!
++ * @brief memory map interface for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
++{
++ unsigned long offset;
++
++ offset = vshare_mem.cpu_addr >> PAGE_SHIFT;
++
++ if (vm->vm_pgoff && (vm->vm_pgoff == offset))
++ return vpu_map_vshare_mem(fp, vm);
++ else if (vm->vm_pgoff)
++ return vpu_map_dma_mem(fp, vm);
++ else
++ return vpu_map_hwregs(fp, vm);
++}
++
++const struct file_operations vpu_fops = {
++ .owner = THIS_MODULE,
++ .open = vpu_open,
++ .unlocked_ioctl = vpu_ioctl,
++ .release = vpu_release,
++ .fasync = vpu_fasync,
++ .mmap = vpu_mmap,
++};
++
++/*!
++ * This function is called by the driver framework to initialize the vpu device.
++ * @param dev The device structure for the vpu passed in by the framework.
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_dev_probe(struct platform_device *pdev)
++{
++ int err = 0;
++ struct device *temp_class;
++ struct resource *res;
++ unsigned long addr = 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ struct device_node *np = pdev->dev.of_node;
++ u32 iramsize;
++
++ err = of_property_read_u32(np, "iramsize", (u32 *)&iramsize);
++ if (!err && iramsize)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ {
++ iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ return -ENOMEM;
++ }
++
++ iram_base = gen_pool_alloc(iram_pool, iramsize);
++ if (!iram_base) {
++ dev_err(&pdev->dev, "unable to alloc iram\n");
++ return -ENOMEM;
++ }
++
++ addr = gen_pool_virt_to_phys(iram_pool, iram_base);
++ }
++#else
++ iram_alloc(iramsize, &addr);
++#endif
++ if (addr == 0)
++ iram.start = iram.end = 0;
++ else {
++ iram.start = addr;
++ iram.end = addr + iramsize - 1;
++ }
++#else
++
++ vpu_plat = pdev->dev.platform_data;
++
++ if (vpu_plat && vpu_plat->iram_enable && vpu_plat->iram_size)
++ iram_alloc(vpu_plat->iram_size, &addr);
++ if (addr == 0)
++ iram.start = iram.end = 0;
++ else {
++ iram.start = addr;
++ iram.end = addr + vpu_plat->iram_size - 1;
++ }
++#endif
++
++ vpu_dev = &pdev->dev;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu_regs");
++ if (!res) {
++ dev_err(vpu_dev, "vpu: unable to get vpu base addr\n");
++ return -ENODEV;
++ }
++ phy_vpu_base_addr = res->start;
++ vpu_base = ioremap(res->start, res->end - res->start);
++
++ vpu_major = register_chrdev(vpu_major, "mxc_vpu", &vpu_fops);
++ if (vpu_major < 0) {
++ dev_err(vpu_dev, "vpu: unable to get a major for VPU\n");
++ err = -EBUSY;
++ goto error;
++ }
++
++ vpu_class = class_create(THIS_MODULE, "mxc_vpu");
++ if (IS_ERR(vpu_class)) {
++ err = PTR_ERR(vpu_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(vpu_class, NULL, MKDEV(vpu_major, 0),
++ NULL, "mxc_vpu");
++ if (IS_ERR(temp_class)) {
++ err = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ vpu_clk = clk_get(&pdev->dev, "vpu_clk");
++ if (IS_ERR(vpu_clk)) {
++ err = -ENOENT;
++ goto err_out_class;
++ }
++
++ vpu_ipi_irq = platform_get_irq_byname(pdev, "vpu_ipi_irq");
++ if (vpu_ipi_irq < 0) {
++ dev_err(vpu_dev, "vpu: unable to get vpu interrupt\n");
++ err = -ENXIO;
++ goto err_out_class;
++ }
++ err = request_irq(vpu_ipi_irq, vpu_ipi_irq_handler, 0, "VPU_CODEC_IRQ",
++ (void *)(&vpu_data));
++ if (err)
++ goto err_out_class;
++ if (vpu_power_get(true)) {
++ if (!(cpu_is_mx51() || cpu_is_mx53())) {
++ dev_err(vpu_dev, "failed to get vpu power\n");
++ goto err_out_class;
++ } else {
++ /* regulator_get will return error on MX5x,
++ * just igore it everywhere*/
++ dev_warn(vpu_dev, "failed to get vpu power\n");
++ }
++ }
++
++#ifdef MXC_VPU_HAS_JPU
++ vpu_jpu_irq = platform_get_irq_byname(pdev, "vpu_jpu_irq");
++ if (vpu_jpu_irq < 0) {
++ dev_err(vpu_dev, "vpu: unable to get vpu jpu interrupt\n");
++ err = -ENXIO;
++ free_irq(vpu_ipi_irq, &vpu_data);
++ goto err_out_class;
++ }
++ err = request_irq(vpu_jpu_irq, vpu_jpu_irq_handler, IRQF_TRIGGER_RISING,
++ "VPU_JPG_IRQ", (void *)(&vpu_data));
++ if (err) {
++ free_irq(vpu_ipi_irq, &vpu_data);
++ goto err_out_class;
++ }
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_enable(&pdev->dev);
++#endif
++
++ vpu_data.workqueue = create_workqueue("vpu_wq");
++ INIT_WORK(&vpu_data.work, vpu_worker_callback);
++ mutex_init(&vpu_data.lock);
++ dev_info(vpu_dev, "VPU initialized\n");
++ goto out;
++
++err_out_class:
++ device_destroy(vpu_class, MKDEV(vpu_major, 0));
++ class_destroy(vpu_class);
++err_out_chrdev:
++ unregister_chrdev(vpu_major, "mxc_vpu");
++error:
++ iounmap(vpu_base);
++out:
++ return err;
++}
++
++static int vpu_dev_remove(struct platform_device *pdev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_disable(&pdev->dev);
++#endif
++ free_irq(vpu_ipi_irq, &vpu_data);
++#ifdef MXC_VPU_HAS_JPU
++ free_irq(vpu_jpu_irq, &vpu_data);
++#endif
++ cancel_work_sync(&vpu_data.work);
++ flush_workqueue(vpu_data.workqueue);
++ destroy_workqueue(vpu_data.workqueue);
++
++ iounmap(vpu_base);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ if (iram.start)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ gen_pool_free(iram_pool, iram_base, iram.end-iram.start+1);
++#else
++ iram_free(iram.start, iram.end-iram.start+1);
++#endif
++#else
++ if (vpu_plat && vpu_plat->iram_enable && vpu_plat->iram_size)
++ iram_free(iram.start, vpu_plat->iram_size);
++#endif
++
++ vpu_power_get(false);
++ return 0;
++}
++
++#ifdef CONFIG_PM
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_suspend(struct device *dev)
++#else
++static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
++#endif
++{
++ int i;
++ unsigned long timeout;
++
++ mutex_lock(&vpu_data.lock);
++ if (open_count == 0) {
++ /* VPU is released (all instances are freed),
++ * clock is already off, context is no longer needed,
++ * power is already off on MX6,
++ * gate power on MX51 */
++ if (cpu_is_mx51()) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(1);
++#endif
++ }
++ } else {
++ /* Wait for vpu go to idle state, suspect vpu cannot be changed
++ to idle state after about 1 sec */
++ timeout = jiffies + HZ;
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ while (READ_REG(BIT_BUSY_FLAG)) {
++ msleep(1);
++ if (time_after(jiffies, timeout)) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EAGAIN;
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ /* Make sure clock is disabled before suspend */
++ vpu_clk_usercount = atomic_read(&clk_cnt_from_ioc);
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++ if (cpu_is_mx53()) {
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++ }
++
++ if (bitwork_mem.cpu_addr != 0) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ /* Save 64 registers from BIT_CODE_BUF_ADDR */
++ for (i = 0; i < 64; i++)
++ regBk[i] = READ_REG(BIT_CODE_BUF_ADDR + (i * 4));
++ pc_before_suspend = READ_REG(BIT_CUR_PC);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(1);
++#endif
++
++ /* If VPU is working before suspend, disable
++ * regulator to make usecount right. */
++ vpu_power_up(false);
++ }
++
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_resume(struct device *dev)
++#else
++static int vpu_resume(struct platform_device *pdev)
++#endif
++{
++ int i;
++
++ mutex_lock(&vpu_data.lock);
++ if (open_count == 0) {
++ /* VPU is released (all instances are freed),
++ * clock should be kept off, context is no longer needed,
++ * power should be kept off on MX6,
++ * disable power gating on MX51 */
++ if (cpu_is_mx51()) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(0);
++#endif
++ }
++ } else {
++ if (cpu_is_mx53())
++ goto recover_clk;
++
++ /* If VPU is working before suspend, enable
++ * regulator to make usecount right. */
++ vpu_power_up(true);
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(0);
++#endif
++
++ if (bitwork_mem.cpu_addr != 0) {
++ u32 *p = (u32 *) bitwork_mem.cpu_addr;
++ u32 data, pc;
++ u16 data_hi;
++ u16 data_lo;
++
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++
++ pc = READ_REG(BIT_CUR_PC);
++ if (pc) {
++ dev_warn(vpu_dev, "Not power off after suspend (PC=0x%x)\n", pc);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ goto recover_clk;
++ }
++
++ /* Restore registers */
++ for (i = 0; i < 64; i++)
++ WRITE_REG(regBk[i], BIT_CODE_BUF_ADDR + (i * 4));
++
++ WRITE_REG(0x0, BIT_RESET_CTRL);
++ WRITE_REG(0x0, BIT_CODE_RUN);
++ /* MX6 RTL has a bug not to init MBC_SET_SUBBLK_EN on reset */
++#ifdef CONFIG_SOC_IMX6Q
++ WRITE_REG(0x0, MBC_SET_SUBBLK_EN);
++#endif
++
++ /*
++ * Re-load boot code, from the codebuffer in external RAM.
++ * Thankfully, we only need 4096 bytes, same for all platforms.
++ */
++ for (i = 0; i < 2048; i += 4) {
++ data = p[(i / 2) + 1];
++ data_hi = (data >> 16) & 0xFFFF;
++ data_lo = data & 0xFFFF;
++ WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN);
++ WRITE_REG(((i + 1) << 16) | data_lo,
++ BIT_CODE_DOWN);
++
++ data = p[i / 2];
++ data_hi = (data >> 16) & 0xFFFF;
++ data_lo = data & 0xFFFF;
++ WRITE_REG(((i + 2) << 16) | data_hi,
++ BIT_CODE_DOWN);
++ WRITE_REG(((i + 3) << 16) | data_lo,
++ BIT_CODE_DOWN);
++ }
++
++ if (pc_before_suspend) {
++ WRITE_REG(0x1, BIT_BUSY_FLAG);
++ WRITE_REG(0x1, BIT_CODE_RUN);
++ while (READ_REG(BIT_BUSY_FLAG))
++ ;
++ } else {
++ dev_warn(vpu_dev, "PC=0 before suspend\n");
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++recover_clk:
++ /* Recover vpu clock */
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ }
++ }
++
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int vpu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static const struct dev_pm_ops vpu_pm_ops = {
++ SET_RUNTIME_PM_OPS(vpu_runtime_suspend, vpu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
++};
++#endif
++
++#else
++#define vpu_suspend NULL
++#define vpu_resume NULL
++#endif /* !CONFIG_PM */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static const struct of_device_id vpu_of_match[] = {
++ { .compatible = "fsl,imx6-vpu", },
++ {/* sentinel */}
++};
++MODULE_DEVICE_TABLE(of, vpu_of_match);
++#endif
++
++/*! Driver definition
++ *
++ */
++static struct platform_driver mxcvpu_driver = {
++ .driver = {
++ .name = "mxc_vpu",
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ .of_match_table = vpu_of_match,
++#ifdef CONFIG_PM
++ .pm = &vpu_pm_ops,
++#endif
++#endif
++ },
++ .probe = vpu_dev_probe,
++ .remove = vpu_dev_remove,
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ .suspend = vpu_suspend,
++ .resume = vpu_resume,
++#endif
++};
++
++static int __init vpu_init(void)
++{
++ int ret = platform_driver_register(&mxcvpu_driver);
++
++ init_waitqueue_head(&vpu_queue);
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ memblock_analyze();
++ top_address_DRAM = memblock_end_of_DRAM_with_reserved();
++#endif
++
++ return ret;
++}
++
++static void __exit vpu_exit(void)
++{
++ if (vpu_major > 0) {
++ device_destroy(vpu_class, MKDEV(vpu_major, 0));
++ class_destroy(vpu_class);
++ unregister_chrdev(vpu_major, "mxc_vpu");
++ vpu_major = 0;
++ }
++
++ vpu_free_dma_buffer(&bitwork_mem);
++ vpu_free_dma_buffer(&pic_para_mem);
++ vpu_free_dma_buffer(&user_data_mem);
++
++ /* reset VPU state */
++ vpu_power_up(true);
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ vpu_reset();
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ vpu_power_up(false);
++
++ clk_put(vpu_clk);
++
++ platform_driver_unregister(&mxcvpu_driver);
++ return;
++}
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX/MXC");
++MODULE_LICENSE("GPL");
++
++module_init(vpu_init);
++module_exit(vpu_exit);
+diff -Nur linux-3.10.30.orig/drivers/net/can/flexcan.c linux-linaro-stable-mx6/drivers/net/can/flexcan.c
+--- linux-3.10.30.orig/drivers/net/can/flexcan.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/can/flexcan.c 2014-05-15 20:33:58.714019025 +0200
+@@ -33,11 +33,14 @@
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/list.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/pinctrl/consumer.h>
++#include <linux/regmap.h>
+
+ #define DRV_NAME "flexcan"
+
+@@ -123,10 +126,12 @@
+ (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
+ #define FLEXCAN_ESR_ALL_INT \
+ (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
+- FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
++ FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
++ FLEXCAN_ESR_WAK_INT)
+
+ /* FLEXCAN interrupt flag register (IFLAG) bits */
+-#define FLEXCAN_TX_BUF_ID 8
++#define FLEXCAN_RESERVED_BUF_ID 8
++#define FLEXCAN_TX_BUF_ID 13
+ #define FLEXCAN_IFLAG_BUF(x) BIT(x)
+ #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
+ #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
+@@ -161,6 +166,7 @@
+ */
+ #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
+ #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
++#define FLEXCAN_HAS_ERR005829 BIT(3) /* have errata ERR005829 */
+
+ /* Structure of the message buffer */
+ struct flexcan_mb {
+@@ -212,6 +218,8 @@
+ struct clk *clk_per;
+ struct flexcan_platform_data *pdata;
+ const struct flexcan_devtype_data *devtype_data;
++ struct regmap *gpr;
++ int id;
+ };
+
+ static struct flexcan_devtype_data fsl_p1010_devtype_data = {
+@@ -219,7 +227,7 @@
+ };
+ static struct flexcan_devtype_data fsl_imx28_devtype_data;
+ static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
+- .features = FLEXCAN_HAS_V10_FEATURES,
++ .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_ERR005829,
+ };
+
+ static const struct can_bittiming_const flexcan_bittiming_const = {
+@@ -259,6 +267,32 @@
+ }
+ #endif
+
++static inline void flexcan_enter_stop_mode(struct flexcan_priv *priv)
++{
++ int val;
++
++ /* enable stop request */
++ if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) {
++ val = priv->id ? IMX6Q_GPR13_CAN2_STOP_REQ :
++ IMX6Q_GPR13_CAN1_STOP_REQ;
++ regmap_update_bits(priv->gpr, IOMUXC_GPR13,
++ val, val);
++ }
++}
++
++static inline void flexcan_exit_stop_mode(struct flexcan_priv *priv)
++{
++ int val;
++
++ /* remove stop request */
++ if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) {
++ val = priv->id ? IMX6Q_GPR13_CAN2_STOP_REQ :
++ IMX6Q_GPR13_CAN1_STOP_REQ;
++ regmap_update_bits(priv->gpr, IOMUXC_GPR13,
++ val, 0);
++ }
++}
++
+ /*
+ * Swtich transceiver on or off
+ */
+@@ -347,6 +381,11 @@
+ flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
+ flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+
++ if (priv->devtype_data->features & FLEXCAN_HAS_ERR005829) {
++ writel(0x0, &regs->cantxfg[FLEXCAN_RESERVED_BUF_ID].can_ctrl);
++ writel(0x0, &regs->cantxfg[FLEXCAN_RESERVED_BUF_ID].can_ctrl);
++ }
++
+ return NETDEV_TX_OK;
+ }
+
+@@ -623,6 +662,9 @@
+ if (reg_esr & FLEXCAN_ESR_ALL_INT)
+ flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+
++ if (reg_esr & FLEXCAN_ESR_WAK_INT)
++ flexcan_exit_stop_mode(priv);
++
+ /*
+ * schedule NAPI in case of:
+ * - rx IRQ
+@@ -741,13 +783,14 @@
+ * enable warning int
+ * choose format C
+ * disable local echo
+- *
++ * enable self wakeup
+ */
+ reg_mcr = flexcan_read(&regs->mcr);
+ reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
+ reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
+ FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
+ FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
++ FLEXCAN_MCR_WAK_MSK | FLEXCAN_MCR_SLF_WAK |
+ FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
+ netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
+ flexcan_write(reg_mcr, &regs->mcr);
+@@ -1003,6 +1046,7 @@
+ resource_size_t mem_size;
+ int err, irq;
+ u32 clock_freq = 0;
++ int wakeup = 1;
+
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl))
+@@ -1019,7 +1063,6 @@
+ err = PTR_ERR(clk_ipg);
+ goto failed_clock;
+ }
+- clock_freq = clk_get_rate(clk_ipg);
+
+ clk_per = devm_clk_get(&pdev->dev, "per");
+ if (IS_ERR(clk_per)) {
+@@ -1027,6 +1070,8 @@
+ err = PTR_ERR(clk_per);
+ goto failed_clock;
+ }
++
++ clock_freq = clk_get_rate(clk_per);
+ }
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -1097,6 +1142,23 @@
+
+ devm_can_led_init(dev);
+
++ if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) {
++ priv->gpr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++ "gpr");
++ if (IS_ERR(priv->gpr)) {
++ wakeup = 0;
++ dev_dbg(&pdev->dev, "can not get grp\n");
++ }
++
++ priv->id = of_alias_get_id(pdev->dev.of_node, "flexcan");
++ if (priv->id < 0) {
++ wakeup = 0;
++ dev_dbg(&pdev->dev, "can not get alias id\n");
++ }
++ }
++
++ device_set_wakeup_capable(&pdev->dev, wakeup);
++
+ dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
+ priv->base, dev->irq);
+
+@@ -1138,11 +1200,21 @@
+ struct net_device *dev = platform_get_drvdata(pdev);
+ struct flexcan_priv *priv = netdev_priv(dev);
+
+- flexcan_chip_disable(priv);
+-
+ if (netif_running(dev)) {
+ netif_stop_queue(dev);
+ netif_device_detach(dev);
++ /*
++ * if wakeup is enabled, enter stop mode
++ * else enter disabled mode.
++ */
++ if (device_may_wakeup(&pdev->dev)) {
++ enable_irq_wake(dev->irq);
++ flexcan_enter_stop_mode(priv);
++ } else {
++ flexcan_chip_disable(priv);
++ }
++ } else {
++ flexcan_chip_disable(priv);
+ }
+ priv->can.state = CAN_STATE_SLEEPING;
+
+@@ -1158,8 +1230,16 @@
+ if (netif_running(dev)) {
+ netif_device_attach(dev);
+ netif_start_queue(dev);
++
++ if (device_may_wakeup(&pdev->dev)) {
++ disable_irq_wake(dev->irq);
++ flexcan_exit_stop_mode(priv);
++ } else {
++ flexcan_chip_enable(priv);
++ }
++ } else {
++ flexcan_chip_enable(priv);
+ }
+- flexcan_chip_enable(priv);
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/8390/ne.c linux-linaro-stable-mx6/drivers/net/ethernet/8390/ne.c
+--- linux-3.10.30.orig/drivers/net/ethernet/8390/ne.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/8390/ne.c 2014-05-15 20:33:58.822019803 +0200
+@@ -849,7 +849,6 @@
+ free_irq(dev->irq, dev);
+ release_region(dev->base_addr, NE_IO_EXTENT);
+ free_netdev(dev);
+- platform_set_drvdata(pdev, NULL);
+ }
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/adi/bfin_mac.c linux-linaro-stable-mx6/drivers/net/ethernet/adi/bfin_mac.c
+--- linux-3.10.30.orig/drivers/net/ethernet/adi/bfin_mac.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/adi/bfin_mac.c 2014-05-15 20:33:58.826019832 +0200
+@@ -1719,7 +1719,6 @@
+ mdiobus_unregister(lp->mii_bus);
+ mdiobus_free(lp->mii_bus);
+ out_err_probe_mac:
+- platform_set_drvdata(pdev, NULL);
+ free_netdev(ndev);
+
+ return rc;
+@@ -1732,8 +1731,6 @@
+
+ bfin_phc_release(lp);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ lp->mii_bus->priv = NULL;
+
+ unregister_netdev(ndev);
+@@ -1868,7 +1865,6 @@
+ struct bfin_mii_bus_platform_data *mii_bus_pd =
+ dev_get_platdata(&pdev->dev);
+
+- platform_set_drvdata(pdev, NULL);
+ mdiobus_unregister(miibus);
+ kfree(miibus->irq);
+ mdiobus_free(miibus);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/amd/au1000_eth.c linux-linaro-stable-mx6/drivers/net/ethernet/amd/au1000_eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/amd/au1000_eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/amd/au1000_eth.c 2014-05-15 20:33:58.830019861 +0200
+@@ -1301,8 +1301,6 @@
+ int i;
+ struct resource *base, *macen;
+
+- platform_set_drvdata(pdev, NULL);
+-
+ unregister_netdev(dev);
+ mdiobus_unregister(aup->mii_bus);
+ mdiobus_free(aup->mii_bus);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/broadcom/bcm63xx_enet.c linux-linaro-stable-mx6/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+--- linux-3.10.30.orig/drivers/net/ethernet/broadcom/bcm63xx_enet.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/broadcom/bcm63xx_enet.c 2014-05-15 20:33:58.942020668 +0200
+@@ -1847,7 +1847,6 @@
+ clk_disable_unprepare(priv->mac_clk);
+ clk_put(priv->mac_clk);
+
+- platform_set_drvdata(pdev, NULL);
+ free_netdev(dev);
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/cadence/at91_ether.c linux-linaro-stable-mx6/drivers/net/ethernet/cadence/at91_ether.c
+--- linux-3.10.30.orig/drivers/net/ethernet/cadence/at91_ether.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/cadence/at91_ether.c 2014-05-15 20:33:59.062021532 +0200
+@@ -435,7 +435,6 @@
+ unregister_netdev(dev);
+ clk_disable(lp->pclk);
+ free_netdev(dev);
+- platform_set_drvdata(pdev, NULL);
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/cadence/macb.c linux-linaro-stable-mx6/drivers/net/ethernet/cadence/macb.c
+--- linux-3.10.30.orig/drivers/net/ethernet/cadence/macb.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/cadence/macb.c 2014-05-15 20:33:59.062021532 +0200
+@@ -1649,7 +1649,6 @@
+ err_out_free_dev:
+ free_netdev(dev);
+ err_out:
+- platform_set_drvdata(pdev, NULL);
+ return err;
+ }
+
+@@ -1675,7 +1674,6 @@
+ clk_disable_unprepare(bp->pclk);
+ clk_put(bp->pclk);
+ free_netdev(dev);
+- platform_set_drvdata(pdev, NULL);
+ }
+
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/calxeda/xgmac.c linux-linaro-stable-mx6/drivers/net/ethernet/calxeda/xgmac.c
+--- linux-3.10.30.orig/drivers/net/ethernet/calxeda/xgmac.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/calxeda/xgmac.c 2014-05-15 20:33:59.062021532 +0200
+@@ -1790,7 +1790,6 @@
+ free_netdev(ndev);
+ err_alloc:
+ release_mem_region(res->start, resource_size(res));
+- platform_set_drvdata(pdev, NULL);
+ return ret;
+ }
+
+@@ -1813,7 +1812,6 @@
+ free_irq(ndev->irq, ndev);
+ free_irq(priv->pmt_irq, ndev);
+
+- platform_set_drvdata(pdev, NULL);
+ unregister_netdev(ndev);
+ netif_napi_del(&priv->napi);
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/cirrus/ep93xx_eth.c linux-linaro-stable-mx6/drivers/net/ethernet/cirrus/ep93xx_eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/cirrus/ep93xx_eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/cirrus/ep93xx_eth.c 2014-05-15 20:33:59.178022369 +0200
+@@ -783,7 +783,6 @@
+ dev = platform_get_drvdata(pdev);
+ if (dev == NULL)
+ return 0;
+- platform_set_drvdata(pdev, NULL);
+
+ ep = netdev_priv(dev);
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/davicom/dm9000.c linux-linaro-stable-mx6/drivers/net/ethernet/davicom/dm9000.c
+--- linux-3.10.30.orig/drivers/net/ethernet/davicom/dm9000.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/davicom/dm9000.c 2014-05-15 20:33:59.186022426 +0200
+@@ -1673,8 +1673,6 @@
+ {
+ struct net_device *ndev = platform_get_drvdata(pdev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ unregister_netdev(ndev);
+ dm9000_release_board(pdev, netdev_priv(ndev));
+ free_netdev(ndev); /* free device structure */
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/ethoc.c linux-linaro-stable-mx6/drivers/net/ethernet/ethoc.c
+--- linux-3.10.30.orig/drivers/net/ethernet/ethoc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/ethoc.c 2014-05-15 20:33:59.206022570 +0200
+@@ -1147,8 +1147,6 @@
+ struct net_device *netdev = platform_get_drvdata(pdev);
+ struct ethoc *priv = netdev_priv(netdev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ if (netdev) {
+ netif_napi_del(&priv->napi);
+ phy_disconnect(priv->phy);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/faraday/ftgmac100.c linux-linaro-stable-mx6/drivers/net/ethernet/faraday/ftgmac100.c
+--- linux-3.10.30.orig/drivers/net/ethernet/faraday/ftgmac100.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/faraday/ftgmac100.c 2014-05-15 20:33:59.218022657 +0200
+@@ -1311,7 +1311,6 @@
+ release_resource(priv->res);
+ err_req_mem:
+ netif_napi_del(&priv->napi);
+- platform_set_drvdata(pdev, NULL);
+ free_netdev(netdev);
+ err_alloc_etherdev:
+ return err;
+@@ -1335,7 +1334,6 @@
+ release_resource(priv->res);
+
+ netif_napi_del(&priv->napi);
+- platform_set_drvdata(pdev, NULL);
+ free_netdev(netdev);
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/faraday/ftmac100.c linux-linaro-stable-mx6/drivers/net/ethernet/faraday/ftmac100.c
+--- linux-3.10.30.orig/drivers/net/ethernet/faraday/ftmac100.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/faraday/ftmac100.c 2014-05-15 20:33:59.218022657 +0200
+@@ -1149,7 +1149,6 @@
+ release_resource(priv->res);
+ err_req_mem:
+ netif_napi_del(&priv->napi);
+- platform_set_drvdata(pdev, NULL);
+ free_netdev(netdev);
+ err_alloc_etherdev:
+ return err;
+@@ -1169,7 +1168,6 @@
+ release_resource(priv->res);
+
+ netif_napi_del(&priv->napi);
+- platform_set_drvdata(pdev, NULL);
+ free_netdev(netdev);
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fec.h linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec.h
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fec.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec.h 2014-05-15 20:33:59.242022829 +0200
+@@ -16,6 +16,9 @@
+ #include <linux/clocksource.h>
+ #include <linux/net_tstamp.h>
+ #include <linux/ptp_clock_kernel.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/circ_buf.h>
+
+ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+ defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
+@@ -60,6 +63,61 @@
+ #define BM_MIIGSK_CFGR_RMII 0x01
+ #define BM_MIIGSK_CFGR_FRCONT_10M 0x40
+
++#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
++#define RMON_T_PACKETS 0x204 /* RMON TX packet count */
++#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
++#define RMON_T_MC_PKT 0x20C /* RMON TX multicast pkts */
++#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
++#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
++#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
++#define RMON_T_FRAG 0x21C /* RMON TX pkts < 64 bytes, bad CRC */
++#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
++#define RMON_T_COL 0x224 /* RMON TX collision count */
++#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
++#define RMON_T_P65TO127 0x22C /* RMON TX 65 to 127 byte pkts */
++#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
++#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
++#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
++#define RMON_T_P1024TO2047 0x23C /* RMON TX 1024 to 2047 byte pkts */
++#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
++#define RMON_T_OCTETS 0x244 /* RMON TX octets */
++#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
++#define IEEE_T_FRAME_OK 0x24C /* Frames tx'd OK */
++#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
++#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
++#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
++#define IEEE_T_LCOL 0x25C /* Frames tx'd with late collision */
++#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
++#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
++#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
++#define IEEE_T_SQE 0x26C /* Frames tx'd with SQE err */
++#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
++#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
++#define RMON_R_PACKETS 0x284 /* RMON RX packet count */
++#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
++#define RMON_R_MC_PKT 0x28C /* RMON RX multicast pkts */
++#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
++#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
++#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
++#define RMON_R_FRAG 0x29C /* RMON RX pkts < 64 bytes, bad CRC */
++#define RMON_R_JAB 0x2A0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
++#define RMON_R_RESVD_O 0x2A4 /* Reserved */
++#define RMON_R_P64 0x2A8 /* RMON RX 64 byte pkts */
++#define RMON_R_P65TO127 0x2AC /* RMON RX 65 to 127 byte pkts */
++#define RMON_R_P128TO255 0x2B0 /* RMON RX 128 to 255 byte pkts */
++#define RMON_R_P256TO511 0x2B4 /* RMON RX 256 to 511 byte pkts */
++#define RMON_R_P512TO1023 0x2B8 /* RMON RX 512 to 1023 byte pkts */
++#define RMON_R_P1024TO2047 0x2BC /* RMON RX 1024 to 2047 byte pkts */
++#define RMON_R_P_GTE2048 0x2C0 /* RMON RX pkts > 2048 bytes */
++#define RMON_R_OCTETS 0x2C4 /* RMON RX octets */
++#define IEEE_R_DROP 0x2C8 /* Count frames not counted correctly */
++#define IEEE_R_FRAME_OK 0x2CC /* Frames rx'd OK */
++#define IEEE_R_CRC 0x2D0 /* Frames rx'd with CRC err */
++#define IEEE_R_ALIGN 0x2D4 /* Frames rx'd with alignment err */
++#define IEEE_R_MACERR 0x2D8 /* Receive FIFO overflow count */
++#define IEEE_R_FDXFC 0x2DC /* Flow control pause frames rx'd */
++#define IEEE_R_OCTETS_OK 0x2E0 /* Octet cnt for frames rx'd w/o err */
++
+ #else
+
+ #define FEC_ECNTRL 0x000 /* Ethernet control reg */
+@@ -148,6 +206,9 @@
+ #define BD_ENET_RX_CL ((ushort)0x0001)
+ #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
+
++/* Enhanced buffer descriptor control/status used by Ethernet receive */
++#define BD_ENET_RX_VLAN 0x00000004
++
+ /* Buffer descriptor control/status used by Ethernet transmit.
+ */
+ #define BD_ENET_TX_READY ((ushort)0x8000)
+@@ -198,9 +259,121 @@
+ #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
+ #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
+
++#define FALSE 0
++#define TRUE 1
++
++/* Interrupt events/masks. */
++#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
++#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
++#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
++#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
++#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
++#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
++#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
++#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
++#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
++#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
++#define FEC_ENET_TS_AVAIL ((uint)0x00010000)
++#define FEC_ENET_TS_TIMER ((uint)0x00008000)
++
++#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | FEC_ENET_TS_TIMER)
++#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
++
++/* IEEE 1588 definition */
++#define FEC_T_PERIOD_ONE_SEC 0x3B9ACA00
++
++#define DEFAULT_PTP_RX_BUF_SZ 64
++#define DEFAULT_PTP_TX_BUF_SZ 64
++
++/* 1588stack API defines */
++#define PTP_ENBL_TXTS_IOCTL SIOCDEVPRIVATE
++#define PTP_DSBL_TXTS_IOCTL (SIOCDEVPRIVATE + 1)
++#define PTP_ENBL_RXTS_IOCTL (SIOCDEVPRIVATE + 2)
++#define PTP_DSBL_RXTS_IOCTL (SIOCDEVPRIVATE + 3)
++#define PTP_GET_TX_TIMESTAMP (SIOCDEVPRIVATE + 4)
++#define PTP_GET_RX_TIMESTAMP (SIOCDEVPRIVATE + 5)
++#define PTP_SET_RTC_TIME (SIOCDEVPRIVATE + 6)
++#define PTP_GET_CURRENT_TIME (SIOCDEVPRIVATE + 7)
++#define PTP_SET_COMPENSATION (SIOCDEVPRIVATE + 9)
++#define PTP_GET_ORIG_COMP (SIOCDEVPRIVATE + 10)
++#define PTP_FLUSH_TIMESTAMP (SIOCDEVPRIVATE + 11)
++
++/* IEEE1588 ptp head format */
++#define PTP_CTRL_OFFS 0x52
++#define PTP_SOURCE_PORT_LENGTH 10
++#define PTP_HEADER_SEQ_OFFS 30
++#define PTP_HEADER_CTL_OFFS 32
++#define PTP_SPID_OFFS 20
++#define PTP_HEADER_SZE 34
++#define PTP_EVENT_PORT 0x013F
++
++#define FEC_VLAN_TAG_LEN 0x04
++#define FEC_ETHTYPE_LEN 0x02
++
++/* 1588-2008 network protocol enumeration values */
++#define FEC_PTP_PROT_IPV4 1
++#define FEC_PTP_PROT_IPV6 2
++#define FEC_PTP_PROT_802_3 3
++#define FEC_PTP_PROT_DONTCARE 0xFFFF
++#define FEC_PACKET_TYPE_UDP 0x11
++
++#define FEC_PTP_ORIG_COMP 0x15555555
++#define FEC_PTP_SPINNER_2 2
++#define FEC_PTP_SPINNER_4 4
++#define FEC_PTP_TIMEOUT_TS 10
++#define FEC_PTP_TIMEOUT_EVENT 1000
++
++/* PTP standard time representation structure */
++struct ptp_time{
++ u64 sec; /* seconds */
++ u32 nsec; /* nanoseconds */
++};
++
++/* struct needed to identify a timestamp */
++struct fec_ptp_ident {
++ u8 version;
++ u8 message_type;
++ u16 netw_prot;
++ u16 seq_id;
++ u8 spid[10];
++};
++
++/* interface for PTP driver command GET_TX_TIME */
++struct fec_ptp_ts_data {
++ struct fec_ptp_ident ident;
++ /* PTP timestamp */
++ struct ptp_time ts;
++};
++
++/* circular buffer for ptp timestamps over ioctl */
++struct fec_ptp_circular {
++ int front;
++ int end;
++ int size;
++ struct fec_ptp_ts_data *data_buf;
++};
++
++/* interface for PTP driver command SET_RTC_TIME/GET_CURRENT_TIME */
++struct ptp_rtc_time {
++ struct ptp_time rtc_time;
++};
++
++/* interface for PTP driver command SET_COMPENSATION */
++struct ptp_set_comp {
++ u32 drift;
++ bool o_ops;
++ u32 freq_compensation;
++};
++
++struct ptp_time_correct {
++ u32 corr_period;
++ u32 corr_inc;
++};
++
+ struct fec_enet_delayed_work {
+ struct delayed_work delay_work;
+ bool timeout;
++ bool trig_tx;
+ };
+
+ /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
+@@ -237,6 +410,9 @@
+ /* The ring entries to be free()ed */
+ struct bufdesc *dirty_tx;
+
++ unsigned short tx_ring_size;
++ unsigned short rx_ring_size;
++
+ struct platform_device *pdev;
+
+ int opened;
+@@ -253,12 +429,21 @@
+ int speed;
+ struct completion mdio_done;
+ int irq[FEC_IRQ_NUM];
++ /* HW timestamping over ioctl enabled flag */
++ int hwts_tx_en_ioctl;
++ int hwts_rx_en_ioctl;
++ struct fec_ptp_circular tx_timestamps;
++ struct fec_ptp_circular rx_timestamps;
++ u64 prtc;
+ int bufdesc_ex;
+ int pause_flag;
+
+ struct napi_struct napi;
+ int csum_flags;
+
++ int phy_reset_gpio;
++ int reset_duration;
++
+ struct ptp_clock *ptp_clock;
+ struct ptp_clock_info ptp_caps;
+ unsigned long last_overflow_check;
+@@ -272,11 +457,21 @@
+ int hwts_tx_en;
+ struct timer_list time_keep;
+ struct fec_enet_delayed_work delay_work;
++ struct regulator *reg_phy;
+ };
+
+-void fec_ptp_init(struct net_device *ndev, struct platform_device *pdev);
++void fec_ptp_init(struct platform_device *pdev);
+ void fec_ptp_start_cyclecounter(struct net_device *ndev);
+ int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd);
++void fec_ptp_cleanup(struct fec_enet_private *priv);
++void fec_ptp_stop(struct net_device *ndev);
++int fec_ptp_do_txstamp(struct sk_buff *skb);
++void fec_ptp_store_txstamp(struct fec_enet_private *priv,
++ struct sk_buff *skb,
++ struct bufdesc *bdp);
++void fec_ptp_store_rxstamp(struct fec_enet_private *priv,
++ struct sk_buff *skb,
++ struct bufdesc *bdp);
+
+ /****************************************************************************/
+ #endif /* FEC_H */
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fec_main.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec_main.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fec_main.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec_main.c 2014-05-15 20:33:59.278023090 +0200
+@@ -18,7 +18,7 @@
+ * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
+ * Copyright (c) 2004-2006 Macq Electronique SA.
+ *
+- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ */
+
+ #include <linux/module.h>
+@@ -53,13 +53,25 @@
+ #include <linux/of_device.h>
+ #include <linux/of_gpio.h>
+ #include <linux/of_net.h>
+-#include <linux/pinctrl/consumer.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/if_vlan.h>
++#include <linux/pm_runtime.h>
++#include <linux/pm_qos.h>
++#include <linux/version.h>
+
+ #include <asm/cacheflush.h>
+
+ #include "fec.h"
+
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++#include <linux/busfreq-imx6.h>
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++#include <mach/busfreq.h>
++#endif
++
++static void set_multicast_list(struct net_device *ndev);
++static void fec_reset_phy(struct platform_device *pdev);
++
+ #if defined(CONFIG_ARM)
+ #define FEC_ALIGNMENT 0xf
+ #else
+@@ -67,7 +79,6 @@
+ #endif
+
+ #define DRIVER_NAME "fec"
+-#define FEC_NAPI_WEIGHT 64
+
+ /* Pause frame feild and FIFO threshold */
+ #define FEC_ENET_FCE (1 << 5)
+@@ -89,6 +100,26 @@
+ #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
+ /* Controller has hardware checksum support */
+ #define FEC_QUIRK_HAS_CSUM (1 << 5)
++/* Controller has hardware vlan support */
++#define FEC_QUIRK_HAS_VLAN (1 << 6)
++/* Controller is FEC-MAC */
++#define FEC_QUIRK_FEC_MAC (1 << 7)
++/* ENET IP errata ERR006358
++ *
++ * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
++ * detected as not set during a prior frame transmission, then the
++ * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
++ * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
++ * frames not being transmitted until there is a 0-to-1 transition on
++ * ENET_TDAR[TDAR].
++ */
++#define FEC_QUIRK_ERR006358 (1 << 8)
++/*
++ * i.MX6Q/DL ENET cannot wake up system in wait mode because ENET tx & rx
++ * interrupt signal don't connect to GPC. So use pm qos to avoid cpu enter
++ * to wait mode.
++ */
++#define FEC_QUIRK_BUG_WAITMODE (1 << 9)
+
+ static struct platform_device_id fec_devtype[] = {
+ {
+@@ -97,7 +128,7 @@
+ .driver_data = 0,
+ }, {
+ .name = "imx25-fec",
+- .driver_data = FEC_QUIRK_USE_GASKET,
++ .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_FEC_MAC,
+ }, {
+ .name = "imx27-fec",
+ .driver_data = 0,
+@@ -107,7 +138,9 @@
+ }, {
+ .name = "imx6q-fec",
+ .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
+- FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM,
++ FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
++ FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
++ FEC_QUIRK_BUG_WAITMODE,
+ }, {
+ .name = "mvf600-fec",
+ .driver_data = FEC_QUIRK_ENET_MAC,
+@@ -163,26 +196,11 @@
+ #error "FEC: descriptor ring size constants too large"
+ #endif
+
+-/* Interrupt events/masks. */
+-#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
+-#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
+-#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
+-#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
+-#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
+-#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
+-#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
+-#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
+-#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
+-#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
+-
+-#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
+-#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
+-
+-/* The FEC stores dest/src/type, data, and checksum for receive packets.
++/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
+ */
+-#define PKT_MAXBUF_SIZE 1518
++#define PKT_MAXBUF_SIZE 1522
+ #define PKT_MINBUF_SIZE 64
+-#define PKT_MAXBLR_SIZE 1520
++#define PKT_MAXBLR_SIZE 1536
+
+ /* FEC receive acceleration */
+ #define FEC_RACC_IPDIS (1 << 1)
+@@ -220,22 +238,57 @@
+
+ static int mii_cnt;
+
+-static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
++static inline
++struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
+ {
+- struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
+- if (is_ex)
+- return (struct bufdesc *)(ex + 1);
++ struct bufdesc *new_bd = bdp + 1;
++ struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
++ struct bufdesc_ex *ex_base;
++ struct bufdesc *base;
++ int ring_size;
++
++ if (bdp >= fep->tx_bd_base) {
++ base = fep->tx_bd_base;
++ ring_size = fep->tx_ring_size;
++ ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
++ } else {
++ base = fep->rx_bd_base;
++ ring_size = fep->rx_ring_size;
++ ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
++ }
++
++ if (fep->bufdesc_ex)
++ return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
++ ex_base : ex_new_bd);
+ else
+- return bdp + 1;
++ return (new_bd >= (base + ring_size)) ?
++ base : new_bd;
+ }
+
+-static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
++static inline
++struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
+ {
+- struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
+- if (is_ex)
+- return (struct bufdesc *)(ex - 1);
++ struct bufdesc *new_bd = bdp - 1;
++ struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
++ struct bufdesc_ex *ex_base;
++ struct bufdesc *base;
++ int ring_size;
++
++ if (bdp >= fep->tx_bd_base) {
++ base = fep->tx_bd_base;
++ ring_size = fep->tx_ring_size;
++ ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
++ } else {
++ base = fep->rx_bd_base;
++ ring_size = fep->rx_ring_size;
++ ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
++ }
++
++ if (fep->bufdesc_ex)
++ return (struct bufdesc *)((ex_new_bd < ex_base) ?
++ (ex_new_bd + ring_size) : ex_new_bd);
+ else
+- return bdp - 1;
++ return (new_bd < base) ? (new_bd + ring_size) : new_bd;
+ }
+
+ static void *swap_buffer(void *bufaddr, int len)
+@@ -243,7 +296,7 @@
+ int i;
+ unsigned int *buf = bufaddr;
+
+- for (i = 0; i < (len + 3) / 4; i++, buf++)
++ for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
+ *buf = cpu_to_be32(*buf);
+
+ return bufaddr;
+@@ -270,16 +323,11 @@
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ const struct platform_device_id *id_entry =
+ platform_get_device_id(fep->pdev);
+- struct bufdesc *bdp;
++ struct bufdesc *bdp, *bdp_pre;
+ void *bufaddr;
+ unsigned short status;
+ unsigned int index;
+
+- if (!fep->link) {
+- /* Link is down or auto-negotiation is in progress. */
+- return NETDEV_TX_BUSY;
+- }
+-
+ /* Fill in a Tx ring entry */
+ bdp = fep->cur_tx;
+
+@@ -337,8 +385,15 @@
+ * data.
+ */
+ bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
+- FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
+-
++ skb->len, DMA_TO_DEVICE);
++ if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
++ bdp->cbd_bufaddr = 0;
++ fep->tx_skbuff[index] = NULL;
++ dev_kfree_skb_any(skb);
++ if (net_ratelimit())
++ netdev_err(ndev, "Tx DMA memory map failed\n");
++ return NETDEV_TX_OK;
++ }
+ /* Send it on its way. Tell FEC it's ready, interrupt when done,
+ * it's the last BD of the frame, and to put the CRC on the end.
+ */
+@@ -351,7 +406,8 @@
+ struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
+ ebdp->cbd_bdu = 0;
+ if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
+- fep->hwts_tx_en)) {
++ fep->hwts_tx_en) || unlikely(fep->hwts_tx_en_ioctl &&
++ fec_ptp_do_txstamp(skb))) {
+ ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
+ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+ } else {
+@@ -365,11 +421,17 @@
+ ebdp->cbd_esc |= BD_ENET_TX_PINS;
+ }
+ }
++
++ bdp_pre = fec_enet_get_prevdesc(bdp, fep);
++ if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
++ !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
++ fep->delay_work.trig_tx = true;
++ schedule_delayed_work(&(fep->delay_work.delay_work),
++ msecs_to_jiffies(1));
++ }
++
+ /* If this was the last BD in the ring, start at the beginning again. */
+- if (status & BD_ENET_TX_WRAP)
+- bdp = fep->tx_bd_base;
+- else
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
+
+ skb_tx_timestamp(skb);
+
+@@ -394,18 +456,18 @@
+
+ /* Initialize the receive buffer descriptors. */
+ bdp = fep->rx_bd_base;
+- for (i = 0; i < RX_RING_SIZE; i++) {
++ for (i = 0; i < fep->rx_ring_size; i++) {
+
+ /* Initialize the BD for every fragment in the page. */
+ if (bdp->cbd_bufaddr)
+ bdp->cbd_sc = BD_ENET_RX_EMPTY;
+ else
+ bdp->cbd_sc = 0;
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
+ }
+
+ /* Set the last buffer to wrap */
+- bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_prevdesc(bdp, fep);
+ bdp->cbd_sc |= BD_SC_WRAP;
+
+ fep->cur_rx = fep->rx_bd_base;
+@@ -413,7 +475,7 @@
+ /* ...and the same for transmit */
+ bdp = fep->tx_bd_base;
+ fep->cur_tx = bdp;
+- for (i = 0; i < TX_RING_SIZE; i++) {
++ for (i = 0; i < fep->tx_ring_size; i++) {
+
+ /* Initialize the BD for every fragment in the page. */
+ bdp->cbd_sc = 0;
+@@ -422,11 +484,11 @@
+ fep->tx_skbuff[i] = NULL;
+ }
+ bdp->cbd_bufaddr = 0;
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
+ }
+
+ /* Set the last buffer to wrap */
+- bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_prevdesc(bdp, fep);
+ bdp->cbd_sc |= BD_SC_WRAP;
+ fep->dirty_tx = bdp;
+ }
+@@ -462,7 +524,8 @@
+ * enet-mac reset will reset mac address registers too,
+ * so need to reconfigure it.
+ */
+- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
++ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC ||
++ id_entry->driver_data & FEC_QUIRK_FEC_MAC) {
+ memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
+ writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+ writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+@@ -471,9 +534,8 @@
+ /* Clear any outstanding interrupt. */
+ writel(0xffc00000, fep->hwp + FEC_IEVENT);
+
+- /* Reset all multicast. */
+- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
+- writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
++ /* Setup multicast filter. */
++ set_multicast_list(ndev);
+ #ifndef CONFIG_M5272
+ writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
+ writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
+@@ -488,10 +550,10 @@
+ writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
+ if (fep->bufdesc_ex)
+ writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
+- * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
++ * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
+ else
+ writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
+- * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
++ * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
+
+
+ for (i = 0; i <= TX_RING_MOD_MASK; i++) {
+@@ -609,6 +671,11 @@
+ if (fep->bufdesc_ex)
+ ecntl |= (1 << 4);
+
++#ifndef CONFIG_M5272
++ /* Enable the MIB statistic event counters */
++ writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
++#endif
++
+ /* And last, enable the transmit and receive processing */
+ writel(ecntl, fep->hwp + FEC_ECNTRL);
+ writel(0, fep->hwp + FEC_R_DES_ACTIVE);
+@@ -649,6 +716,11 @@
+ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+ writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
+
++ if (fep->bufdesc_ex && (fep->hwts_tx_en_ioctl ||
++ fep->hwts_rx_en_ioctl || fep->hwts_tx_en ||
++ fep->hwts_rx_en))
++ fec_ptp_stop(ndev);
++
+ /* We have to keep ENET enabled to have MII interrupt stay working */
+ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+ writel(2, fep->hwp + FEC_ECNTRL);
+@@ -656,12 +728,14 @@
+ }
+ }
+
++static uint last_ievents;
+
+ static void
+ fec_timeout(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
++ pr_err("%s: last=%x %x, mask %x\n", __func__, last_ievents, readl(fep->hwp + FEC_IEVENT), readl(fep->hwp + FEC_IMASK));
+ ndev->stats.tx_errors++;
+
+ fep->delay_work.timeout = true;
+@@ -680,6 +754,11 @@
+ fec_restart(fep->netdev, fep->full_duplex);
+ netif_wake_queue(fep->netdev);
+ }
++
++ if (fep->delay_work.trig_tx) {
++ fep->delay_work.trig_tx = false;
++ writel(0, fep->hwp + FEC_X_DES_ACTIVE);
++ }
+ }
+
+ static void
+@@ -695,10 +774,7 @@
+ bdp = fep->dirty_tx;
+
+ /* get next bdp of dirty_tx */
+- if (bdp->cbd_sc & BD_ENET_TX_WRAP)
+- bdp = fep->tx_bd_base;
+- else
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
+
+ while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
+
+@@ -712,11 +788,10 @@
+ else
+ index = bdp - fep->tx_bd_base;
+
+- dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
+- FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
+- bdp->cbd_bufaddr = 0;
+-
+ skb = fep->tx_skbuff[index];
++ dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
++ DMA_TO_DEVICE);
++ bdp->cbd_bufaddr = 0;
+
+ /* Check for errors. */
+ if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
+@@ -735,10 +810,11 @@
+ ndev->stats.tx_carrier_errors++;
+ } else {
+ ndev->stats.tx_packets++;
++ ndev->stats.tx_bytes += bdp->cbd_datlen;
+ }
+
+- if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
+- fep->bufdesc_ex) {
++ if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
++ fep->hwts_tx_en) && fep->bufdesc_ex) {
+ struct skb_shared_hwtstamps shhwtstamps;
+ unsigned long flags;
+ struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
+@@ -749,7 +825,8 @@
+ timecounter_cyc2time(&fep->tc, ebdp->ts));
+ spin_unlock_irqrestore(&fep->tmreg_lock, flags);
+ skb_tstamp_tx(skb, &shhwtstamps);
+- }
++ } else if (unlikely(fep->hwts_tx_en_ioctl) && fep->bufdesc_ex)
++ fec_ptp_store_txstamp(fep, skb, bdp);
+
+ if (status & BD_ENET_TX_READY)
+ netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
+@@ -767,10 +844,7 @@
+ fep->dirty_tx = bdp;
+
+ /* Update pointer to next buffer descriptor to be transmitted */
+- if (status & BD_ENET_TX_WRAP)
+- bdp = fep->tx_bd_base;
+- else
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
+
+ /* Since we have freed up a buffer, the ring is no longer full
+ */
+@@ -800,6 +874,10 @@
+ ushort pkt_len;
+ __u8 *data;
+ int pkt_received = 0;
++ struct bufdesc_ex *ebdp = NULL;
++ bool vlan_packet_rcvd = false;
++ u16 vlan_tag = 0;
++ int index = 0;
+
+ #ifdef CONFIG_M532x
+ flush_cache_all();
+@@ -855,36 +933,64 @@
+ ndev->stats.rx_packets++;
+ pkt_len = bdp->cbd_datlen;
+ ndev->stats.rx_bytes += pkt_len;
+- data = (__u8*)__va(bdp->cbd_bufaddr);
+
+- dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
+- FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
++ if (fep->bufdesc_ex)
++ index = (struct bufdesc_ex *)bdp -
++ (struct bufdesc_ex *)fep->rx_bd_base;
++ else
++ index = bdp - fep->rx_bd_base;
++ data = fep->rx_skbuff[index]->data;
++ dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
++ FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+
+ if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
+ swap_buffer(data, pkt_len);
+
++ /* Extract the enhanced buffer descriptor */
++ ebdp = NULL;
++ if (fep->bufdesc_ex)
++ ebdp = (struct bufdesc_ex *)bdp;
++
++ /* If this is a VLAN packet remove the VLAN Tag */
++ vlan_packet_rcvd = false;
++ if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
++ fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
++ /* Push and remove the vlan tag */
++ struct vlan_hdr *vlan_header =
++ (struct vlan_hdr *) (data + ETH_HLEN);
++ vlan_tag = ntohs(vlan_header->h_vlan_TCI);
++ pkt_len -= VLAN_HLEN;
++
++ vlan_packet_rcvd = true;
++ }
++
+ /* This does 16 byte alignment, exactly what we need.
+ * The packet length includes FCS, but we don't want to
+ * include that when passing upstream as it messes up
+ * bridging applications.
+ */
+- skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
++ skb = __netdev_alloc_skb_ip_align(ndev, pkt_len - 4,
++ GFP_ATOMIC | __GFP_NOWARN);
+
+ if (unlikely(!skb)) {
+ ndev->stats.rx_dropped++;
+ } else {
+- skb_reserve(skb, NET_IP_ALIGN);
++ int payload_offset = (2 * ETH_ALEN);
+ skb_put(skb, pkt_len - 4); /* Make room */
+- skb_copy_to_linear_data(skb, data, pkt_len - 4);
+- skb->protocol = eth_type_trans(skb, ndev);
++
++ /* Extract the frame data without the VLAN header. */
++ skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
++ if (vlan_packet_rcvd)
++ payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
++ skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
++ data + payload_offset,
++ pkt_len - 4 - (2 * ETH_ALEN));
+
+ /* Get receive timestamp from the skb */
+ if (fep->hwts_rx_en && fep->bufdesc_ex) {
+ struct skb_shared_hwtstamps *shhwtstamps =
+ skb_hwtstamps(skb);
+ unsigned long flags;
+- struct bufdesc_ex *ebdp =
+- (struct bufdesc_ex *)bdp;
+
+ memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+
+@@ -892,12 +998,13 @@
+ shhwtstamps->hwtstamp = ns_to_ktime(
+ timecounter_cyc2time(&fep->tc, ebdp->ts));
+ spin_unlock_irqrestore(&fep->tmreg_lock, flags);
+- }
++ } else if (unlikely(fep->hwts_rx_en_ioctl) &&
++ fep->bufdesc_ex)
++ fec_ptp_store_rxstamp(fep, skb, bdp);
+
++ skb->protocol = eth_type_trans(skb, ndev);
+ if (fep->bufdesc_ex &&
+- (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
+- struct bufdesc_ex *ebdp =
+- (struct bufdesc_ex *)bdp;
++ (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
+ if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
+ /* don't check it */
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+@@ -906,12 +1013,17 @@
+ }
+ }
+
+- if (!skb_defer_rx_timestamp(skb))
+- napi_gro_receive(&fep->napi, skb);
++ /* Handle received VLAN packets */
++ if (vlan_packet_rcvd)
++ __vlan_hwaccel_put_tag(skb,
++ htons(ETH_P_8021Q),
++ vlan_tag);
++
++ napi_gro_receive(&fep->napi, skb);
+ }
+
+- bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
+- FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
++ dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
++ FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+ rx_processing_done:
+ /* Clear the status flags for this buffer */
+ status &= ~BD_ENET_RX_STATS;
+@@ -929,10 +1041,8 @@
+ }
+
+ /* Update BD pointer to next entry */
+- if (status & BD_ENET_RX_WRAP)
+- bdp = fep->rx_bd_base;
+- else
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
++
+ /* Doing this here will keep the FEC running while we process
+ * incoming frames. On a heavily loaded network, we should be
+ * able to keep up at the expense of system resources.
+@@ -949,29 +1059,37 @@
+ {
+ struct net_device *ndev = dev_id;
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- uint int_events;
++ uint int_events, eir;
+ irqreturn_t ret = IRQ_NONE;
+
+- do {
+- int_events = readl(fep->hwp + FEC_IEVENT);
+- writel(int_events, fep->hwp + FEC_IEVENT);
++ while (1) {
++ eir = readl(fep->hwp + FEC_IEVENT);
++ int_events = eir & readl(fep->hwp + FEC_IMASK);
++ if (!int_events)
++ break;
++ last_ievents = eir;
+
++ if ((int_events & FEC_ENET_TS_TIMER) && fep->bufdesc_ex) {
++ ret = IRQ_HANDLED;
++ if (fep->hwts_tx_en_ioctl || fep->hwts_rx_en_ioctl)
++ fep->prtc++;
++ writel(FEC_ENET_TS_TIMER, fep->hwp + FEC_IEVENT);
++ }
+ if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
+ ret = IRQ_HANDLED;
+-
+- /* Disable the RX interrupt */
+ if (napi_schedule_prep(&fep->napi)) {
+- writel(FEC_RX_DISABLED_IMASK,
+- fep->hwp + FEC_IMASK);
++ /* Disable the RX/TX interrupt */
++ writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
+ __napi_schedule(&fep->napi);
+ }
+ }
+
+ if (int_events & FEC_ENET_MII) {
++ writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
+ ret = IRQ_HANDLED;
+ complete(&fep->mdio_done);
+ }
+- } while (int_events);
++ }
+
+ return ret;
+ }
+@@ -979,14 +1097,20 @@
+ static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
+ {
+ struct net_device *ndev = napi->dev;
+- int pkts = fec_enet_rx(ndev, budget);
+ struct fec_enet_private *fep = netdev_priv(ndev);
++ int pkts;
+
++ writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
++ pkts = fec_enet_rx(ndev, budget);
+ fec_enet_tx(ndev);
+
+ if (pkts < budget) {
+- napi_complete(napi);
+- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
++ uint int_events = readl(fep->hwp + FEC_IEVENT);
++
++ if (!(int_events & (FEC_ENET_RXF | FEC_ENET_TXF))) {
++ napi_complete(napi);
++ writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
++ }
+ }
+ return pkts;
+ }
+@@ -995,7 +1119,7 @@
+ static void fec_get_mac(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
++ struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
+ unsigned char *iap, tmpaddr[ETH_ALEN];
+
+ /*
+@@ -1035,10 +1159,10 @@
+ * 4) FEC mac registers set by bootloader
+ */
+ if (!is_valid_ether_addr(iap)) {
+- *((unsigned long *) &tmpaddr[0]) =
+- be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
+- *((unsigned short *) &tmpaddr[4]) =
+- be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
++ *((__be32 *) &tmpaddr[0]) =
++ cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
++ *((__be16 *) &tmpaddr[4]) =
++ cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
+ iap = &tmpaddr[0];
+ }
+
+@@ -1165,6 +1289,47 @@
+ return 0;
+ }
+
++static inline int fec_enet_clk_enable(struct net_device *ndev, bool enable)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int ret = 0;
++
++ if (enable) {
++ ret = clk_prepare_enable(fep->clk_ahb);
++ if (ret)
++ goto failed_clk;
++
++ ret = clk_prepare_enable(fep->clk_ipg);
++ if (ret)
++ goto failed_clk_ipg;
++
++ if (fep->clk_enet_out) {
++ ret = clk_prepare_enable(fep->clk_enet_out);
++ if (ret)
++ goto failed_clk_enet_out;
++ }
++
++ if (fep->clk_ptp) {
++ ret = clk_prepare_enable(fep->clk_ptp);
++ if (ret)
++ goto failed_clk_ptp;
++ }
++ return ret;
++ }
++
++ if (fep->clk_ptp)
++ clk_disable_unprepare(fep->clk_ptp);
++failed_clk_ptp:
++ if (fep->clk_enet_out)
++ clk_disable_unprepare(fep->clk_enet_out);
++failed_clk_enet_out:
++ clk_disable_unprepare(fep->clk_ipg);
++failed_clk_ipg:
++ clk_disable_unprepare(fep->clk_ahb);
++failed_clk:
++ return ret;
++}
++
+ static int fec_enet_mii_probe(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+@@ -1274,7 +1439,7 @@
+ * Reference Manual has an error on this, and gets fixed on i.MX6Q
+ * document.
+ */
+- fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
++ fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
+ if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
+ fep->phy_speed--;
+ fep->phy_speed <<= 1;
+@@ -1446,6 +1611,118 @@
+
+ #endif /* !defined(CONFIG_M5272) */
+
++#ifndef CONFIG_M5272
++static const struct fec_stat {
++ char name[ETH_GSTRING_LEN];
++ u16 offset;
++} fec_stats[] = {
++ /* RMON TX */
++ { "tx_dropped", RMON_T_DROP },
++ { "tx_packets", RMON_T_PACKETS },
++ { "tx_broadcast", RMON_T_BC_PKT },
++ { "tx_multicast", RMON_T_MC_PKT },
++ { "tx_crc_errors", RMON_T_CRC_ALIGN },
++ { "tx_undersize", RMON_T_UNDERSIZE },
++ { "tx_oversize", RMON_T_OVERSIZE },
++ { "tx_fragment", RMON_T_FRAG },
++ { "tx_jabber", RMON_T_JAB },
++ { "tx_collision", RMON_T_COL },
++ { "tx_64byte", RMON_T_P64 },
++ { "tx_65to127byte", RMON_T_P65TO127 },
++ { "tx_128to255byte", RMON_T_P128TO255 },
++ { "tx_256to511byte", RMON_T_P256TO511 },
++ { "tx_512to1023byte", RMON_T_P512TO1023 },
++ { "tx_1024to2047byte", RMON_T_P1024TO2047 },
++ { "tx_GTE2048byte", RMON_T_P_GTE2048 },
++ { "tx_octets", RMON_T_OCTETS },
++
++ /* IEEE TX */
++ { "IEEE_tx_drop", IEEE_T_DROP },
++ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
++ { "IEEE_tx_1col", IEEE_T_1COL },
++ { "IEEE_tx_mcol", IEEE_T_MCOL },
++ { "IEEE_tx_def", IEEE_T_DEF },
++ { "IEEE_tx_lcol", IEEE_T_LCOL },
++ { "IEEE_tx_excol", IEEE_T_EXCOL },
++ { "IEEE_tx_macerr", IEEE_T_MACERR },
++ { "IEEE_tx_cserr", IEEE_T_CSERR },
++ { "IEEE_tx_sqe", IEEE_T_SQE },
++ { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
++ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
++
++ /* RMON RX */
++ { "rx_packets", RMON_R_PACKETS },
++ { "rx_broadcast", RMON_R_BC_PKT },
++ { "rx_multicast", RMON_R_MC_PKT },
++ { "rx_crc_errors", RMON_R_CRC_ALIGN },
++ { "rx_undersize", RMON_R_UNDERSIZE },
++ { "rx_oversize", RMON_R_OVERSIZE },
++ { "rx_fragment", RMON_R_FRAG },
++ { "rx_jabber", RMON_R_JAB },
++ { "rx_64byte", RMON_R_P64 },
++ { "rx_65to127byte", RMON_R_P65TO127 },
++ { "rx_128to255byte", RMON_R_P128TO255 },
++ { "rx_256to511byte", RMON_R_P256TO511 },
++ { "rx_512to1023byte", RMON_R_P512TO1023 },
++ { "rx_1024to2047byte", RMON_R_P1024TO2047 },
++ { "rx_GTE2048byte", RMON_R_P_GTE2048 },
++ { "rx_octets", RMON_R_OCTETS },
++
++ /* IEEE RX */
++ { "IEEE_rx_drop", IEEE_R_DROP },
++ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
++ { "IEEE_rx_crc", IEEE_R_CRC },
++ { "IEEE_rx_align", IEEE_R_ALIGN },
++ { "IEEE_rx_macerr", IEEE_R_MACERR },
++ { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
++ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
++};
++
++static void fec_enet_get_ethtool_stats(struct net_device *dev,
++ struct ethtool_stats *stats, u64 *data)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
++ data[i] = readl(fep->hwp + fec_stats[i].offset);
++}
++
++static void fec_enet_get_strings(struct net_device *netdev,
++ u32 stringset, u8 *data)
++{
++ int i;
++ switch (stringset) {
++ case ETH_SS_STATS:
++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
++ memcpy(data + i * ETH_GSTRING_LEN,
++ fec_stats[i].name, ETH_GSTRING_LEN);
++ break;
++ }
++}
++
++static int fec_enet_get_sset_count(struct net_device *dev, int sset)
++{
++ switch (sset) {
++ case ETH_SS_STATS:
++ return ARRAY_SIZE(fec_stats);
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++#endif
++
++static int fec_enet_nway_reset(struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ struct phy_device *phydev = fep->phy_dev;
++
++ if (!phydev)
++ return -ENODEV;
++
++ return genphy_restart_aneg(phydev);
++}
++
+ static const struct ethtool_ops fec_enet_ethtool_ops = {
+ #if !defined(CONFIG_M5272)
+ .get_pauseparam = fec_enet_get_pauseparam,
+@@ -1456,6 +1733,12 @@
+ .get_drvinfo = fec_enet_get_drvinfo,
+ .get_link = ethtool_op_get_link,
+ .get_ts_info = fec_enet_get_ts_info,
++ .nway_reset = fec_enet_nway_reset,
++#ifndef CONFIG_M5272
++ .get_ethtool_stats = fec_enet_get_ethtool_stats,
++ .get_strings = fec_enet_get_strings,
++ .get_sset_count = fec_enet_get_sset_count,
++#endif
+ };
+
+ static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
+@@ -1469,8 +1752,11 @@
+ if (!phydev)
+ return -ENODEV;
+
+- if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
++ if (((cmd == SIOCSHWTSTAMP) || ((cmd >= PTP_ENBL_TXTS_IOCTL) &&
++ (cmd <= PTP_FLUSH_TIMESTAMP))) && fep->bufdesc_ex)
+ return fec_ptp_ioctl(ndev, rq, cmd);
++ else if (fep->bufdesc_ex)
++ return -ENODEV;
+
+ return phy_mii_ioctl(phydev, rq, cmd);
+ }
+@@ -1483,7 +1769,7 @@
+ struct bufdesc *bdp;
+
+ bdp = fep->rx_bd_base;
+- for (i = 0; i < RX_RING_SIZE; i++) {
++ for (i = 0; i < fep->rx_ring_size; i++) {
+ skb = fep->rx_skbuff[i];
+
+ if (bdp->cbd_bufaddr)
+@@ -1491,11 +1777,11 @@
+ FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+ if (skb)
+ dev_kfree_skb(skb);
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
+ }
+
+ bdp = fep->tx_bd_base;
+- for (i = 0; i < TX_RING_SIZE; i++)
++ for (i = 0; i < fep->tx_ring_size; i++)
+ kfree(fep->tx_bounce[i]);
+ }
+
+@@ -1507,7 +1793,7 @@
+ struct bufdesc *bdp;
+
+ bdp = fep->rx_bd_base;
+- for (i = 0; i < RX_RING_SIZE; i++) {
++ for (i = 0; i < fep->rx_ring_size; i++) {
+ skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
+ if (!skb) {
+ fec_enet_free_buffers(ndev);
+@@ -1517,6 +1803,12 @@
+
+ bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
+ FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
++ if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
++ fec_enet_free_buffers(ndev);
++ if (net_ratelimit())
++ netdev_err(ndev, "Rx DMA memory map failed\n");
++ return -ENOMEM;
++ }
+ bdp->cbd_sc = BD_ENET_RX_EMPTY;
+
+ if (fep->bufdesc_ex) {
+@@ -1524,15 +1816,15 @@
+ ebdp->cbd_esc = BD_ENET_RX_INT;
+ }
+
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
+ }
+
+ /* Set the last buffer to wrap. */
+- bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_prevdesc(bdp, fep);
+ bdp->cbd_sc |= BD_SC_WRAP;
+
+ bdp = fep->tx_bd_base;
+- for (i = 0; i < TX_RING_SIZE; i++) {
++ for (i = 0; i < fep->tx_ring_size; i++) {
+ fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
+
+ bdp->cbd_sc = 0;
+@@ -1543,11 +1835,11 @@
+ ebdp->cbd_esc = BD_ENET_TX_INT;
+ }
+
+- bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_nextdesc(bdp, fep);
+ }
+
+ /* Set the last buffer to wrap. */
+- bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
++ bdp = fec_enet_get_prevdesc(bdp, fep);
+ bdp->cbd_sc |= BD_SC_WRAP;
+
+ return 0;
+@@ -1557,9 +1849,25 @@
+ fec_enet_open(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
++ const struct platform_device_id *id_entry =
++ platform_get_device_id(fep->pdev);
+ int ret;
+
+- napi_enable(&fep->napi);
++ pm_runtime_get_sync(ndev->dev.parent);
++ if (id_entry->driver_data & FEC_QUIRK_BUG_WAITMODE)
++ pm_qos_add_request(&ndev->pm_qos_req,
++ PM_QOS_CPU_DMA_LATENCY,
++ 0);
++ else
++ pm_qos_add_request(&ndev->pm_qos_req,
++ PM_QOS_CPU_DMA_LATENCY,
++ PM_QOS_DEFAULT_VALUE);
++
++ pinctrl_pm_select_default_state(&fep->pdev->dev);
++
++ ret = fec_enet_clk_enable(ndev, true);
++ if (ret)
++ return ret;
+
+ /* I should reset the ring buffers here, but I don't yet know
+ * a simple way to do that.
+@@ -1575,9 +1883,15 @@
+ fec_enet_free_buffers(ndev);
+ return ret;
+ }
++
++ napi_enable(&fep->napi);
+ phy_start(fep->phy_dev);
+ netif_start_queue(ndev);
+ fep->opened = 1;
++
++ /* reset phy */
++ fec_reset_phy(fep->pdev);
++
+ return 0;
+ }
+
+@@ -1585,6 +1899,7 @@
+ fec_enet_close(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
++ int ret;
+
+ /* Don't know what to do yet. */
+ napi_disable(&fep->napi);
+@@ -1597,6 +1912,13 @@
+ phy_disconnect(fep->phy_dev);
+ }
+
++ ret = fec_enet_clk_enable(ndev, false);
++
++ pinctrl_pm_select_sleep_state(&fep->pdev->dev);
++
++ pm_qos_remove_request(&ndev->pm_qos_req);
++ pm_runtime_put_sync_suspend(ndev->dev.parent);
++
+ fec_enet_free_buffers(ndev);
+
+ return 0;
+@@ -1787,13 +2109,17 @@
+ /* Get the Ethernet address */
+ fec_get_mac(ndev);
+
++ /* init the tx & rx ring size */
++ fep->tx_ring_size = TX_RING_SIZE;
++ fep->rx_ring_size = RX_RING_SIZE;
++
+ /* Set receive and transmit descriptor base. */
+ fep->rx_bd_base = cbd_base;
+ if (fep->bufdesc_ex)
+ fep->tx_bd_base = (struct bufdesc *)
+- (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
++ (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
+ else
+- fep->tx_bd_base = cbd_base + RX_RING_SIZE;
++ fep->tx_bd_base = cbd_base + fep->rx_ring_size;
+
+ /* The FEC Ethernet specific entries in the device structure */
+ ndev->watchdog_timeo = TX_TIMEOUT;
+@@ -1801,7 +2127,13 @@
+ ndev->ethtool_ops = &fec_enet_ethtool_ops;
+
+ writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
+- netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
++ netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
++
++ if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
++ /* enable hw VLAN support */
++ ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
++ ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
++ }
+
+ if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
+ /* enable hw accelerator */
+@@ -1817,43 +2149,51 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_OF
+-static void fec_reset_phy(struct platform_device *pdev)
++static void fec_of_init(struct platform_device *pdev)
+ {
+- int err, phy_reset;
+- int msec = 1;
+ struct device_node *np = pdev->dev.of_node;
++ struct net_device *ndev = platform_get_drvdata(pdev);
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int err;
++
++ /*
++ * init phy-reset-gpio to one invalid GPIO for no phy
++ * gpio reset platform
++ */
++ fep->phy_reset_gpio = -1;
+
+ if (!np)
+ return;
+
+- of_property_read_u32(np, "phy-reset-duration", &msec);
++ of_property_read_u32(np, "phy-reset-duration",
++ &fep->reset_duration);
+ /* A sane reset duration should not be longer than 1s */
+- if (msec > 1000)
+- msec = 1;
++ if ((fep->reset_duration > 1000) || (fep->reset_duration == 0))
++ fep->reset_duration = 1;
+
+- phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
+- if (!gpio_is_valid(phy_reset))
++ fep->phy_reset_gpio = of_get_named_gpio(np, "phy-reset-gpios", 0);
++ if (!gpio_is_valid(fep->phy_reset_gpio))
+ return;
+
+- err = devm_gpio_request_one(&pdev->dev, phy_reset,
+- GPIOF_OUT_INIT_LOW, "phy-reset");
++ err = devm_gpio_request_one(&pdev->dev, fep->phy_reset_gpio,
++ GPIOF_OUT_INIT_HIGH, "phy-reset");
+ if (err) {
+ dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
+- return;
++ fep->phy_reset_gpio = -1;
+ }
+- msleep(msec);
+- gpio_set_value(phy_reset, 1);
+ }
+-#else /* CONFIG_OF */
++
+ static void fec_reset_phy(struct platform_device *pdev)
+ {
+- /*
+- * In case of platform probe, the reset has been done
+- * by machine code.
+- */
++ struct net_device *ndev = platform_get_drvdata(pdev);
++ struct fec_enet_private *fep = netdev_priv(ndev);
++
++ /* check GPIO valid to avoid kernel print warning when no gpio reset */
++ if (gpio_is_valid(fep->phy_reset_gpio)) {
++ msleep(fep->reset_duration);
++ gpio_set_value(fep->phy_reset_gpio, 1);
++ }
+ }
+-#endif /* CONFIG_OF */
+
+ static int
+ fec_probe(struct platform_device *pdev)
+@@ -1865,17 +2205,11 @@
+ struct resource *r;
+ const struct of_device_id *of_id;
+ static int dev_id;
+- struct pinctrl *pinctrl;
+- struct regulator *reg_phy;
+
+ of_id = of_match_device(fec_dt_ids, &pdev->dev);
+ if (of_id)
+ pdev->id_entry = of_id->data;
+
+- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!r)
+- return -ENXIO;
+-
+ /* Init network device */
+ ndev = alloc_etherdev(sizeof(struct fec_enet_private));
+ if (!ndev)
+@@ -1893,22 +2227,27 @@
+ fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
+ #endif
+
+- fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
++ /* Select default pin state */
++ pinctrl_pm_select_default_state(&pdev->dev);
++
++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ fep->hwp = devm_ioremap_resource(&pdev->dev, r);
++ if (IS_ERR(fep->hwp)) {
++ ret = PTR_ERR(fep->hwp);
++ goto failed_ioremap;
++ }
++
+ fep->pdev = pdev;
+ fep->dev_id = dev_id++;
+
+ fep->bufdesc_ex = 0;
+
+- if (!fep->hwp) {
+- ret = -ENOMEM;
+- goto failed_ioremap;
+- }
+-
+ platform_set_drvdata(pdev, ndev);
+
++ fec_of_init(pdev);
+ ret = of_get_phy_mode(pdev->dev.of_node);
+ if (ret < 0) {
+- pdata = pdev->dev.platform_data;
++ pdata = dev_get_platdata(&pdev->dev);
+ if (pdata)
+ fep->phy_interface = pdata->phy;
+ else
+@@ -1917,12 +2256,6 @@
+ fep->phy_interface = ret;
+ }
+
+- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+- if (IS_ERR(pinctrl)) {
+- ret = PTR_ERR(pinctrl);
+- goto failed_pin;
+- }
+-
+ fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+ if (IS_ERR(fep->clk_ipg)) {
+ ret = PTR_ERR(fep->clk_ipg);
+@@ -1943,30 +2276,31 @@
+ fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
+ fep->bufdesc_ex =
+ pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
+- if (IS_ERR(fep->clk_ptp)) {
++ if (IS_ERR(fep->clk_ptp) || !fep->bufdesc_ex) {
+ fep->clk_ptp = NULL;
+ fep->bufdesc_ex = 0;
+ }
+
+- clk_prepare_enable(fep->clk_ahb);
+- clk_prepare_enable(fep->clk_ipg);
+- clk_prepare_enable(fep->clk_enet_out);
+- clk_prepare_enable(fep->clk_ptp);
+-
+- reg_phy = devm_regulator_get(&pdev->dev, "phy");
+- if (!IS_ERR(reg_phy)) {
+- ret = regulator_enable(reg_phy);
++ pm_runtime_enable(&pdev->dev);
++
++ ret = fec_enet_clk_enable(ndev, true);
++ if (ret)
++ goto failed_clk;
++
++ fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
++ if (!IS_ERR(fep->reg_phy)) {
++ ret = regulator_enable(fep->reg_phy);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Failed to enable phy regulator: %d\n", ret);
+ goto failed_regulator;
+ }
++ } else {
++ fep->reg_phy = NULL;
+ }
+
+- fec_reset_phy(pdev);
+-
+ if (fep->bufdesc_ex)
+- fec_ptp_init(ndev, pdev);
++ fec_ptp_init(pdev);
+
+ ret = fec_enet_init(ndev);
+ if (ret)
+@@ -1980,14 +2314,10 @@
+ ret = irq;
+ goto failed_irq;
+ }
+- ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
+- if (ret) {
+- while (--i >= 0) {
+- irq = platform_get_irq(pdev, i);
+- free_irq(irq, ndev);
+- }
++ ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
++ 0, pdev->name, ndev);
++ if (ret)
+ goto failed_irq;
+- }
+ }
+
+ ret = fec_enet_mii_init(pdev);
+@@ -1996,6 +2326,10 @@
+
+ /* Carrier starts down, phylib will bring it up */
+ netif_carrier_off(ndev);
++ fec_enet_clk_enable(ndev, false);
++
++ /* Select sleep pin state */
++ pinctrl_pm_select_sleep_state(&pdev->dev);
+
+ ret = register_netdev(ndev);
+ if (ret)
+@@ -2010,19 +2344,13 @@
+ failed_register:
+ fec_enet_mii_remove(fep);
+ failed_mii_init:
+-failed_init:
+- for (i = 0; i < FEC_IRQ_NUM; i++) {
+- irq = platform_get_irq(pdev, i);
+- if (irq > 0)
+- free_irq(irq, ndev);
+- }
+ failed_irq:
++failed_init:
++ if (fep->reg_phy)
++ regulator_disable(fep->reg_phy);
+ failed_regulator:
+- clk_disable_unprepare(fep->clk_ahb);
+- clk_disable_unprepare(fep->clk_ipg);
+- clk_disable_unprepare(fep->clk_enet_out);
+- clk_disable_unprepare(fep->clk_ptp);
+-failed_pin:
++ if (fep->clk_ptp)
++ clk_disable_unprepare(fep->clk_ptp);
+ failed_clk:
+ failed_ioremap:
+ free_netdev(ndev);
+@@ -2035,44 +2363,47 @@
+ {
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- int i;
++ int ret;
+
+ cancel_delayed_work_sync(&(fep->delay_work.delay_work));
+ unregister_netdev(ndev);
+- fec_enet_mii_remove(fep);
+- del_timer_sync(&fep->time_keep);
+- clk_disable_unprepare(fep->clk_ptp);
+- if (fep->ptp_clock)
+- ptp_clock_unregister(fep->ptp_clock);
+- clk_disable_unprepare(fep->clk_enet_out);
+- clk_disable_unprepare(fep->clk_ahb);
+- clk_disable_unprepare(fep->clk_ipg);
+- for (i = 0; i < FEC_IRQ_NUM; i++) {
+- int irq = platform_get_irq(pdev, i);
+- if (irq > 0)
+- free_irq(irq, ndev);
+- }
++ fec_enet_mii_remove(fep);
++
++ if (fep->bufdesc_ex) {
++ fec_ptp_cleanup(fep);
++ del_timer_sync(&fep->time_keep);
++ }
++ if (fep->reg_phy)
++ regulator_disable(fep->reg_phy);
++
++ ret = fec_enet_clk_enable(ndev, false);
++
++ if (fep->bufdesc_ex) {
++ if (fep->ptp_clock)
++ ptp_clock_unregister(fep->ptp_clock);
++ }
+ free_netdev(ndev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ return 0;
+ }
+
+-#ifdef CONFIG_PM_SLEEP
++#ifdef CONFIG_PM
+ static int
+ fec_suspend(struct device *dev)
+ {
+ struct net_device *ndev = dev_get_drvdata(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
++ int ret;
+
+ if (netif_running(ndev)) {
+ fec_stop(ndev);
+ netif_device_detach(ndev);
++ ret = fec_enet_clk_enable(ndev, false);
++ pinctrl_pm_select_sleep_state(&fep->pdev->dev);
+ }
+- clk_disable_unprepare(fep->clk_enet_out);
+- clk_disable_unprepare(fep->clk_ahb);
+- clk_disable_unprepare(fep->clk_ipg);
++
++ if (fep->reg_phy)
++ regulator_disable(fep->reg_phy);
+
+ return 0;
+ }
+@@ -2082,20 +2413,51 @@
+ {
+ struct net_device *ndev = dev_get_drvdata(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
++ int ret = 0;
++
++ if (fep->reg_phy) {
++ ret = regulator_enable(fep->reg_phy);
++ if (ret)
++ goto failed_clk;
++ }
+
+- clk_prepare_enable(fep->clk_enet_out);
+- clk_prepare_enable(fep->clk_ahb);
+- clk_prepare_enable(fep->clk_ipg);
+ if (netif_running(ndev)) {
++ pinctrl_pm_select_default_state(&fep->pdev->dev);
++ ret = fec_enet_clk_enable(ndev, true);
++ if (ret)
++ goto failed_clk;
++
+ fec_restart(ndev, fep->full_duplex);
+ netif_device_attach(ndev);
+ }
+
++failed_clk:
++ return ret;
++}
++
++static int fec_runtime_suspend(struct device *dev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ release_bus_freq(BUS_FREQ_HIGH);
++#endif
++ return 0;
++}
++
++static int fec_runtime_resume(struct device *dev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ request_bus_freq(BUS_FREQ_HIGH);
++#endif
+ return 0;
+ }
++
++static const struct dev_pm_ops fec_pm_ops = {
++ SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
++};
++
+ #endif /* CONFIG_PM_SLEEP */
+
+-static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
+
+ static struct platform_driver fec_driver = {
+ .driver = {
+@@ -2111,4 +2473,5 @@
+
+ module_platform_driver(fec_driver);
+
++MODULE_ALIAS("platform:"DRIVER_NAME);
+ MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fec_mpc52xx.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec_mpc52xx.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fec_mpc52xx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec_mpc52xx.c 2014-05-15 20:33:59.278023090 +0200
+@@ -981,7 +981,7 @@
+ goto err_node;
+
+ /* We're done ! */
+- dev_set_drvdata(&op->dev, ndev);
++ platform_set_drvdata(op, ndev);
+ netdev_info(ndev, "%s MAC %pM\n",
+ op->dev.of_node->full_name, ndev->dev_addr);
+
+@@ -1010,7 +1010,7 @@
+ struct net_device *ndev;
+ struct mpc52xx_fec_priv *priv;
+
+- ndev = dev_get_drvdata(&op->dev);
++ ndev = platform_get_drvdata(op);
+ priv = netdev_priv(ndev);
+
+ unregister_netdev(ndev);
+@@ -1030,14 +1030,13 @@
+
+ free_netdev(ndev);
+
+- dev_set_drvdata(&op->dev, NULL);
+ return 0;
+ }
+
+ #ifdef CONFIG_PM
+ static int mpc52xx_fec_of_suspend(struct platform_device *op, pm_message_t state)
+ {
+- struct net_device *dev = dev_get_drvdata(&op->dev);
++ struct net_device *dev = platform_get_drvdata(op);
+
+ if (netif_running(dev))
+ mpc52xx_fec_close(dev);
+@@ -1047,7 +1046,7 @@
+
+ static int mpc52xx_fec_of_resume(struct platform_device *op)
+ {
+- struct net_device *dev = dev_get_drvdata(&op->dev);
++ struct net_device *dev = platform_get_drvdata(op);
+
+ mpc52xx_fec_hw_init(dev);
+ mpc52xx_fec_reset_stats(dev);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec_mpc52xx_phy.c 2014-05-15 20:33:59.278023090 +0200
+@@ -123,12 +123,10 @@
+
+ static int mpc52xx_fec_mdio_remove(struct platform_device *of)
+ {
+- struct device *dev = &of->dev;
+- struct mii_bus *bus = dev_get_drvdata(dev);
++ struct mii_bus *bus = platform_get_drvdata(of);
+ struct mpc52xx_fec_mdio_priv *priv = bus->priv;
+
+ mdiobus_unregister(bus);
+- dev_set_drvdata(dev, NULL);
+ iounmap(priv->regs);
+ kfree(priv);
+ mdiobus_free(bus);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fec_ptp.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec_ptp.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fec_ptp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fec_ptp.c 2014-05-15 20:33:59.278023090 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Fast Ethernet Controller (ENET) PTP driver for MX6x.
+ *
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+@@ -37,6 +37,9 @@
+ #include <linux/workqueue.h>
+ #include <linux/bitops.h>
+ #include <linux/io.h>
++#include <linux/vmalloc.h>
++#include <linux/ip.h>
++#include <linux/udp.h>
+ #include <linux/irq.h>
+ #include <linux/clk.h>
+ #include <linux/platform_device.h>
+@@ -49,6 +52,7 @@
+
+ #include "fec.h"
+
++
+ /* FEC 1588 register bits */
+ #define FEC_T_CTRL_SLAVE 0x00002000
+ #define FEC_T_CTRL_CAPTURE 0x00000800
+@@ -71,6 +75,472 @@
+ #define FEC_TS_TIMESTAMP 0x418
+
+ #define FEC_CC_MULT (1 << 31)
++
++/* Alloc the ring resource */
++static int fec_ptp_init_circ(struct fec_ptp_circular *buf, int size)
++{
++ buf->data_buf = (struct fec_ptp_ts_data *)
++ vmalloc(size * sizeof(struct fec_ptp_ts_data));
++
++ if (!buf->data_buf)
++ return 1;
++ buf->front = 0;
++ buf->end = 0;
++ buf->size = size;
++ return 0;
++}
++
++static inline int fec_ptp_calc_index(int size, int curr_index, int offset)
++{
++ return (curr_index + offset) % size;
++}
++
++static int fec_ptp_is_empty(struct fec_ptp_circular *buf)
++{
++ return (buf->front == buf->end);
++}
++
++static int fec_ptp_nelems(struct fec_ptp_circular *buf)
++{
++ const int front = buf->front;
++ const int end = buf->end;
++ const int size = buf->size;
++ int n_items;
++
++ if (end > front)
++ n_items = end - front;
++ else if (end < front)
++ n_items = size - (front - end);
++ else
++ n_items = 0;
++
++ return n_items;
++}
++
++static int fec_ptp_is_full(struct fec_ptp_circular *buf)
++{
++ if (fec_ptp_nelems(buf) == (buf->size - 1))
++ return 1;
++ else
++ return 0;
++}
++
++static int fec_ptp_insert(struct fec_ptp_circular *ptp_buf,
++ struct fec_ptp_ts_data *data)
++{
++ struct fec_ptp_ts_data *tmp;
++
++ if (fec_ptp_is_full(ptp_buf))
++ ptp_buf->end = fec_ptp_calc_index(ptp_buf->size,
++ ptp_buf->end, 1);
++
++ tmp = (ptp_buf->data_buf + ptp_buf->end);
++ memcpy(tmp, data, sizeof(struct fec_ptp_ts_data));
++ ptp_buf->end = fec_ptp_calc_index(ptp_buf->size, ptp_buf->end, 1);
++
++ return 0;
++}
++
++static int fec_ptp_find_and_remove(struct fec_ptp_circular *ptp_buf,
++ struct fec_ptp_ident *ident, struct ptp_time *ts)
++{
++ int i;
++ int size = ptp_buf->size, end = ptp_buf->end;
++ struct fec_ptp_ident *tmp_ident;
++
++ if (fec_ptp_is_empty(ptp_buf))
++ return 1;
++
++ i = ptp_buf->front;
++ while (i != end) {
++ tmp_ident = &(ptp_buf->data_buf + i)->ident;
++ if (tmp_ident->version == ident->version) {
++ if (tmp_ident->message_type == ident->message_type) {
++ if ((tmp_ident->netw_prot == ident->netw_prot)
++ || (ident->netw_prot ==
++ FEC_PTP_PROT_DONTCARE)) {
++ if (tmp_ident->seq_id ==
++ ident->seq_id) {
++ int ret =
++ memcmp(tmp_ident->spid,
++ ident->spid,
++ PTP_SOURCE_PORT_LENGTH);
++ if (0 == ret)
++ break;
++ }
++ }
++ }
++ }
++ /* get next */
++ i = fec_ptp_calc_index(size, i, 1);
++ }
++
++ /* not found ? */
++ if (i == end) {
++ /* buffer full ? */
++ if (fec_ptp_is_full(ptp_buf))
++ /* drop one in front */
++ ptp_buf->front =
++ fec_ptp_calc_index(size, ptp_buf->front, 1);
++
++ return 1;
++ }
++ *ts = (ptp_buf->data_buf + i)->ts;
++ ptp_buf->front = fec_ptp_calc_index(size, ptp_buf->front, 1);
++
++ return 0;
++}
++
++/* 1588 Module intialization */
++void fec_ptp_start(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ unsigned long flags;
++ int inc;
++
++ inc = FEC_T_PERIOD_ONE_SEC / clk_get_rate(fep->clk_ptp);
++
++ spin_lock_irqsave(&fep->tmreg_lock, flags);
++ /* Select 1588 Timer source and enable module for starting Tmr Clock */
++ writel(FEC_T_CTRL_RESTART, fep->hwp + FEC_ATIME_CTRL);
++ writel(inc << FEC_T_INC_OFFSET,
++ fep->hwp + FEC_ATIME_INC);
++ writel(FEC_T_PERIOD_ONE_SEC, fep->hwp + FEC_ATIME_EVT_PERIOD);
++ /* start counter */
++ writel(FEC_T_CTRL_PERIOD_RST | FEC_T_CTRL_ENABLE,
++ fep->hwp + FEC_ATIME_CTRL);
++ spin_unlock_irqrestore(&fep->tmreg_lock, flags);
++}
++
++/* Cleanup routine for 1588 module.
++ * When PTP is disabled this routing is called */
++void fec_ptp_stop(struct net_device *ndev)
++{
++ struct fec_enet_private *priv = netdev_priv(ndev);
++
++ writel(0, priv->hwp + FEC_ATIME_CTRL);
++ writel(FEC_T_CTRL_RESTART, priv->hwp + FEC_ATIME_CTRL);
++}
++
++static void fec_get_curr_cnt(struct fec_enet_private *priv,
++ struct ptp_rtc_time *curr_time)
++{
++ u32 tempval, old_sec;
++ u32 timeout_event, timeout_ts = 0;
++
++ do {
++ old_sec = priv->prtc;
++ timeout_event = 0;
++
++ tempval = readl(priv->hwp + FEC_ATIME_CTRL);
++ tempval |= FEC_T_CTRL_CAPTURE;
++ writel(tempval, priv->hwp + FEC_ATIME_CTRL);
++
++ curr_time->rtc_time.nsec = readl(priv->hwp + FEC_ATIME);
++
++ while (readl(priv->hwp + FEC_IEVENT) & FEC_ENET_TS_TIMER) {
++ timeout_event++;
++ udelay(20);
++
++ if (timeout_event >= FEC_PTP_TIMEOUT_EVENT)
++ break;
++ }
++
++ curr_time->rtc_time.sec = priv->prtc;
++ timeout_ts++;
++
++ if (timeout_event >= FEC_PTP_TIMEOUT_EVENT)
++ pr_err("timeout: TS TIMER event\n");
++
++ } while (old_sec != curr_time->rtc_time.sec &&
++ timeout_ts < FEC_PTP_TIMEOUT_TS);
++
++ if (timeout_ts >= FEC_PTP_TIMEOUT_TS)
++ pr_err("timeout: current timestamp unmatched\n");
++}
++
++/* Set the 1588 timer counter registers */
++static void fec_set_1588cnt(struct fec_enet_private *priv,
++ struct ptp_rtc_time *fec_time)
++{
++ u32 tempval;
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->tmreg_lock, flags);
++ priv->prtc = fec_time->rtc_time.sec;
++
++ tempval = fec_time->rtc_time.nsec;
++ writel(tempval, priv->hwp + FEC_ATIME);
++ spin_unlock_irqrestore(&priv->tmreg_lock, flags);
++}
++
++/**
++ * Parse packets if they are PTP.
++ * The PTP header can be found in an IPv4, IPv6 or in an IEEE802.3
++ * ethernet frame. The function returns the position of the PTP packet
++ * or NULL, if no PTP found
++ */
++u8 *fec_ptp_parse_packet(struct sk_buff *skb, u16 *eth_type)
++{
++ u8 *position = skb->data + ETH_ALEN + ETH_ALEN;
++ u8 *ptp_loc = NULL;
++
++ *eth_type = *((u16 *)position);
++ /* Check if outer vlan tag is here */
++ if (ntohs(*eth_type) == ETH_P_8021Q) {
++ position += FEC_VLAN_TAG_LEN;
++ *eth_type = *((u16 *)position);
++ }
++
++ /* set position after ethertype */
++ position += FEC_ETHTYPE_LEN;
++ if (ETH_P_1588 == ntohs(*eth_type)) {
++ ptp_loc = position;
++ /* IEEE1588 event message which needs timestamping */
++ if ((ptp_loc[0] & 0xF) <= 3) {
++ if (skb->len >=
++ ((ptp_loc - skb->data) + PTP_HEADER_SZE))
++ return ptp_loc;
++ }
++ } else if (ETH_P_IP == ntohs(*eth_type)) {
++ u8 *ip_header, *prot, *udp_header;
++ u8 ip_version, ip_hlen;
++ ip_header = position;
++ ip_version = ip_header[0] >> 4; /* correct IP version? */
++ if (0x04 == ip_version) { /* IPv4 */
++ prot = ip_header + 9; /* protocol */
++ if (FEC_PACKET_TYPE_UDP == *prot) {
++ u16 udp_dstPort;
++ /* retrieve the size of the ip-header
++ * with the first byte of the ip-header:
++ * version ( 4 bits) + Internet header
++ * length (4 bits)
++ */
++ ip_hlen = (*ip_header & 0xf) * 4;
++ udp_header = ip_header + ip_hlen;
++ udp_dstPort = *((u16 *)(udp_header + 2));
++ /* check the destination port address
++ * ( 319 (0x013F) = PTP event port )
++ */
++ if (ntohs(udp_dstPort) == PTP_EVENT_PORT) {
++ ptp_loc = udp_header + 8;
++ /* long enough ? */
++ if (skb->len >= ((ptp_loc - skb->data)
++ + PTP_HEADER_SZE))
++ return ptp_loc;
++ }
++ }
++ }
++ } else if (ETH_P_IPV6 == ntohs(*eth_type)) {
++ u8 *ip_header, *udp_header, *prot;
++ u8 ip_version;
++ ip_header = position;
++ ip_version = ip_header[0] >> 4;
++ if (0x06 == ip_version) {
++ prot = ip_header + 6;
++ if (FEC_PACKET_TYPE_UDP == *prot) {
++ u16 udp_dstPort;
++ udp_header = ip_header + 40;
++ udp_dstPort = *((u16 *)(udp_header + 2));
++ /* check the destination port address
++ * ( 319 (0x013F) = PTP event port )
++ */
++ if (ntohs(udp_dstPort) == PTP_EVENT_PORT) {
++ ptp_loc = udp_header + 8;
++ /* long enough ? */
++ if (skb->len >= ((ptp_loc - skb->data)
++ + PTP_HEADER_SZE))
++ return ptp_loc;
++ }
++ }
++ }
++ }
++
++ return NULL; /* no PTP frame */
++}
++
++/* Set the BD to ptp */
++int fec_ptp_do_txstamp(struct sk_buff *skb)
++{
++ u8 *ptp_loc;
++ u16 eth_type;
++
++ ptp_loc = fec_ptp_parse_packet(skb, &eth_type);
++ if (ptp_loc != NULL)
++ return 1;
++
++ return 0;
++}
++
++void fec_ptp_store_txstamp(struct fec_enet_private *priv,
++ struct sk_buff *skb,
++ struct bufdesc *bdp)
++{
++ struct fec_ptp_ts_data tmp_tx_time;
++ struct bufdesc_ex *bdp_ex = NULL;
++ struct ptp_rtc_time curr_time;
++ u8 *ptp_loc;
++ u16 eth_type;
++
++ bdp_ex = container_of(bdp, struct bufdesc_ex, desc);
++ ptp_loc = fec_ptp_parse_packet(skb, &eth_type);
++ if (ptp_loc != NULL) {
++ /* store identification data */
++ switch (ntohs(eth_type)) {
++ case ETH_P_IP:
++ tmp_tx_time.ident.netw_prot = FEC_PTP_PROT_IPV4;
++ break;
++ case ETH_P_IPV6:
++ tmp_tx_time.ident.netw_prot = FEC_PTP_PROT_IPV6;
++ break;
++ case ETH_P_1588:
++ tmp_tx_time.ident.netw_prot = FEC_PTP_PROT_802_3;
++ break;
++ default:
++ return;
++ }
++ tmp_tx_time.ident.version = (*(ptp_loc + 1)) & 0X0F;
++ tmp_tx_time.ident.message_type = (*(ptp_loc)) & 0x0F;
++ tmp_tx_time.ident.seq_id =
++ ntohs(*((u16 *)(ptp_loc + PTP_HEADER_SEQ_OFFS)));
++ memcpy(tmp_tx_time.ident.spid, &ptp_loc[PTP_SPID_OFFS],
++ PTP_SOURCE_PORT_LENGTH);
++ /* store tx timestamp */
++ fec_get_curr_cnt(priv, &curr_time);
++ if (curr_time.rtc_time.nsec < bdp_ex->ts)
++ tmp_tx_time.ts.sec = curr_time.rtc_time.sec - 1;
++ else
++ tmp_tx_time.ts.sec = curr_time.rtc_time.sec;
++ tmp_tx_time.ts.nsec = bdp_ex->ts;
++ /* insert timestamp in circular buffer */
++ fec_ptp_insert(&(priv->tx_timestamps), &tmp_tx_time);
++ }
++}
++
++void fec_ptp_store_rxstamp(struct fec_enet_private *priv,
++ struct sk_buff *skb,
++ struct bufdesc *bdp)
++{
++ struct fec_ptp_ts_data tmp_rx_time;
++ struct bufdesc_ex *bdp_ex = NULL;
++ struct ptp_rtc_time curr_time;
++ u8 *ptp_loc;
++ u16 eth_type;
++
++ bdp_ex = container_of(bdp, struct bufdesc_ex, desc);
++ ptp_loc = fec_ptp_parse_packet(skb, &eth_type);
++ if (ptp_loc != NULL) {
++ /* store identification data */
++ tmp_rx_time.ident.version = (*(ptp_loc + 1)) & 0X0F;
++ tmp_rx_time.ident.message_type = (*(ptp_loc)) & 0x0F;
++ switch (ntohs(eth_type)) {
++ case ETH_P_IP:
++ tmp_rx_time.ident.netw_prot = FEC_PTP_PROT_IPV4;
++ break;
++ case ETH_P_IPV6:
++ tmp_rx_time.ident.netw_prot = FEC_PTP_PROT_IPV6;
++ break;
++ case ETH_P_1588:
++ tmp_rx_time.ident.netw_prot = FEC_PTP_PROT_802_3;
++ break;
++ default:
++ return;
++ }
++ tmp_rx_time.ident.seq_id =
++ ntohs(*((u16 *)(ptp_loc + PTP_HEADER_SEQ_OFFS)));
++ memcpy(tmp_rx_time.ident.spid, &ptp_loc[PTP_SPID_OFFS],
++ PTP_SOURCE_PORT_LENGTH);
++ /* store rx timestamp */
++ fec_get_curr_cnt(priv, &curr_time);
++ if (curr_time.rtc_time.nsec < bdp_ex->ts)
++ tmp_rx_time.ts.sec = curr_time.rtc_time.sec - 1;
++ else
++ tmp_rx_time.ts.sec = curr_time.rtc_time.sec;
++ tmp_rx_time.ts.nsec = bdp_ex->ts;
++
++ /* insert timestamp in circular buffer */
++ fec_ptp_insert(&(priv->rx_timestamps), &tmp_rx_time);
++ }
++}
++
++
++static void fec_handle_ptpdrift(struct fec_enet_private *priv,
++ struct ptp_set_comp *comp, struct ptp_time_correct *ptc)
++{
++ u32 ndrift;
++ u32 i, adj_inc, adj_period;
++ u32 tmp_current, tmp_winner;
++ u32 ptp_ts_clk, ptp_inc;
++
++ ptp_ts_clk = clk_get_rate(priv->clk_ptp);
++ ptp_inc = FEC_T_PERIOD_ONE_SEC / ptp_ts_clk;
++
++ ndrift = comp->drift;
++
++ if (ndrift == 0) {
++ ptc->corr_inc = 0;
++ ptc->corr_period = 0;
++ return;
++ } else if (ndrift >= ptp_ts_clk) {
++ ptc->corr_inc = (u32)(ndrift / ptp_ts_clk);
++ ptc->corr_period = 1;
++ return;
++ } else {
++ tmp_winner = 0xFFFFFFFF;
++ adj_inc = 1;
++
++ if (ndrift > (ptp_ts_clk / ptp_inc)) {
++ adj_inc = ptp_inc / FEC_PTP_SPINNER_2;
++ } else if (ndrift > (ptp_ts_clk /
++ (ptp_inc * FEC_PTP_SPINNER_4))) {
++ adj_inc = ptp_inc / FEC_PTP_SPINNER_4;
++ adj_period = FEC_PTP_SPINNER_2;
++ } else {
++ adj_inc = FEC_PTP_SPINNER_4;
++ adj_period = FEC_PTP_SPINNER_4;
++ }
++
++ for (i = 1; i < adj_inc; i++) {
++ tmp_current = (ptp_ts_clk * i) % ndrift;
++ if (tmp_current == 0) {
++ ptc->corr_inc = i;
++ ptc->corr_period = (u32)((ptp_ts_clk *
++ adj_period * i) / ndrift);
++ break;
++ } else if (tmp_current < tmp_winner) {
++ ptc->corr_inc = i;
++ ptc->corr_period = (u32)((ptp_ts_clk *
++ adj_period * i) / ndrift);
++ tmp_winner = tmp_current;
++ }
++ }
++ }
++}
++
++static void fec_set_drift(struct fec_enet_private *priv,
++ struct ptp_set_comp *comp)
++{
++ struct ptp_time_correct tc;
++ u32 tmp, corr_ns;
++ u32 ptp_inc;
++
++ memset(&tc, 0, sizeof(struct ptp_time_correct));
++ fec_handle_ptpdrift(priv, comp, &tc);
++ if (tc.corr_inc == 0)
++ return;
++
++ ptp_inc = FEC_T_PERIOD_ONE_SEC / clk_get_rate(priv->clk_ptp);
++ if (comp->o_ops == TRUE)
++ corr_ns = ptp_inc + tc.corr_inc;
++ else
++ corr_ns = ptp_inc - tc.corr_inc;
++
++ tmp = readl(priv->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
++ tmp |= corr_ns << FEC_T_INC_CORR_OFFSET;
++ writel(tmp, priv->hwp + FEC_ATIME_INC);
++ writel(tc.corr_period, priv->hwp + FEC_ATIME_CORR);
++}
++
+ /**
+ * fec_ptp_read - read raw cycle counter (to be used by time counter)
+ * @cc: the cyclecounter structure
+@@ -106,18 +576,25 @@
+ unsigned long flags;
+ int inc;
+
+- inc = 1000000000 / fep->cycle_speed;
++ inc = FEC_T_PERIOD_ONE_SEC / fep->cycle_speed;
+
+ /* grab the ptp lock */
+ spin_lock_irqsave(&fep->tmreg_lock, flags);
++ writel(FEC_T_CTRL_RESTART, fep->hwp + FEC_ATIME_CTRL);
+
+ /* 1ns counter */
+ writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
+
+- /* use free running count */
+- writel(0, fep->hwp + FEC_ATIME_EVT_PERIOD);
+-
+- writel(FEC_T_CTRL_ENABLE, fep->hwp + FEC_ATIME_CTRL);
++ if (fep->hwts_rx_en_ioctl || fep->hwts_tx_en_ioctl) {
++ writel(FEC_T_PERIOD_ONE_SEC, fep->hwp + FEC_ATIME_EVT_PERIOD);
++ /* start counter */
++ writel(FEC_T_CTRL_PERIOD_RST | FEC_T_CTRL_ENABLE,
++ fep->hwp + FEC_ATIME_CTRL);
++ } else if (fep->hwts_tx_en || fep->hwts_tx_en) {
++ /* use free running count */
++ writel(0, fep->hwp + FEC_ATIME_EVT_PERIOD);
++ writel(FEC_T_CTRL_ENABLE, fep->hwp + FEC_ATIME_CTRL);
++ }
+
+ memset(&fep->cc, 0, sizeof(fep->cc));
+ fep->cc.read = fec_ptp_read;
+@@ -277,50 +754,140 @@
+ int fec_ptp_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+-
+ struct hwtstamp_config config;
+-
+- if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
+- return -EFAULT;
+-
+- /* reserved for future extensions */
+- if (config.flags)
+- return -EINVAL;
+-
+- switch (config.tx_type) {
+- case HWTSTAMP_TX_OFF:
++ struct ptp_rtc_time curr_time;
++ struct ptp_time rx_time, tx_time;
++ struct fec_ptp_ts_data p_ts;
++ struct fec_ptp_ts_data *p_ts_user;
++ struct ptp_set_comp p_comp;
++ u32 freq_compensation;
++ int retval = 0;
++
++ switch (cmd) {
++ case SIOCSHWTSTAMP:
++ if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
++ return -EFAULT;
++
++ /* reserved for future extensions */
++ if (config.flags)
++ return -EINVAL;
++
++ switch (config.tx_type) {
++ case HWTSTAMP_TX_OFF:
++ fep->hwts_tx_en = 0;
++ break;
++ case HWTSTAMP_TX_ON:
++ fep->hwts_tx_en = 1;
++ fep->hwts_tx_en_ioctl = 0;
++ break;
++ default:
++ return -ERANGE;
++ }
++
++ switch (config.rx_filter) {
++ case HWTSTAMP_FILTER_NONE:
++ if (fep->hwts_rx_en)
++ fep->hwts_rx_en = 0;
++ config.rx_filter = HWTSTAMP_FILTER_NONE;
++ break;
++
++ default:
++ /*
++ * register RXMTRL must be set in order
++ * to do V1 packets, therefore it is not
++ * possible to time stamp both V1 Sync and
++ * Delay_Req messages and hardware does not support
++ * timestamping all packets => return error
++ */
++ fep->hwts_rx_en = 1;
++ fep->hwts_rx_en_ioctl = 0;
++ config.rx_filter = HWTSTAMP_FILTER_ALL;
++ break;
++ }
++
++ fec_ptp_start_cyclecounter(ndev);
++ return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
++ -EFAULT : 0;
++ break;
++ case PTP_ENBL_TXTS_IOCTL:
++ case PTP_ENBL_RXTS_IOCTL:
++ fep->hwts_rx_en_ioctl = 1;
++ fep->hwts_tx_en_ioctl = 1;
++ fep->hwts_rx_en = 0;
+ fep->hwts_tx_en = 0;
++ fec_ptp_start_cyclecounter(ndev);
+ break;
+- case HWTSTAMP_TX_ON:
+- fep->hwts_tx_en = 1;
++ case PTP_DSBL_RXTS_IOCTL:
++ case PTP_DSBL_TXTS_IOCTL:
++ fep->hwts_rx_en_ioctl = 0;
++ fep->hwts_tx_en_ioctl = 0;
+ break;
+- default:
+- return -ERANGE;
+- }
+-
+- switch (config.rx_filter) {
+- case HWTSTAMP_FILTER_NONE:
+- if (fep->hwts_rx_en)
+- fep->hwts_rx_en = 0;
+- config.rx_filter = HWTSTAMP_FILTER_NONE;
++ case PTP_GET_RX_TIMESTAMP:
++ p_ts_user = (struct fec_ptp_ts_data *)ifr->ifr_data;
++ if (0 != copy_from_user(&p_ts.ident,
++ &p_ts_user->ident, sizeof(p_ts.ident)))
++ return -EINVAL;
++ retval = fec_ptp_find_and_remove(&fep->rx_timestamps,
++ &p_ts.ident, &rx_time);
++ if (retval == 0 &&
++ copy_to_user((void __user *)(&p_ts_user->ts),
++ &rx_time, sizeof(rx_time)))
++ return -EFAULT;
+ break;
+-
+- default:
+- /*
+- * register RXMTRL must be set in order to do V1 packets,
+- * therefore it is not possible to time stamp both V1 Sync and
+- * Delay_Req messages and hardware does not support
+- * timestamping all packets => return error
+- */
+- fep->hwts_rx_en = 1;
+- config.rx_filter = HWTSTAMP_FILTER_ALL;
++ case PTP_GET_TX_TIMESTAMP:
++ p_ts_user = (struct fec_ptp_ts_data *)ifr->ifr_data;
++ if (0 != copy_from_user(&p_ts.ident,
++ &p_ts_user->ident, sizeof(p_ts.ident)))
++ return -EINVAL;
++ retval = fec_ptp_find_and_remove(&fep->tx_timestamps,
++ &p_ts.ident, &tx_time);
++ if (retval == 0 &&
++ copy_to_user((void __user *)(&p_ts_user->ts),
++ &tx_time, sizeof(tx_time)))
++ retval = -EFAULT;
++ break;
++ case PTP_GET_CURRENT_TIME:
++ fec_get_curr_cnt(fep, &curr_time);
++ if (0 != copy_to_user(ifr->ifr_data,
++ &(curr_time.rtc_time),
++ sizeof(struct ptp_time)))
++ return -EFAULT;
++ break;
++ case PTP_SET_RTC_TIME:
++ if (0 != copy_from_user(&(curr_time.rtc_time),
++ ifr->ifr_data,
++ sizeof(struct ptp_time)))
++ return -EINVAL;
++ fec_set_1588cnt(fep, &curr_time);
+ break;
++ case PTP_FLUSH_TIMESTAMP:
++ /* reset tx-timestamping buffer */
++ fep->tx_timestamps.front = 0;
++ fep->tx_timestamps.end = 0;
++ fep->tx_timestamps.size = (DEFAULT_PTP_TX_BUF_SZ + 1);
++ /* reset rx-timestamping buffer */
++ fep->rx_timestamps.front = 0;
++ fep->rx_timestamps.end = 0;
++ fep->rx_timestamps.size = (DEFAULT_PTP_RX_BUF_SZ + 1);
++ break;
++ case PTP_SET_COMPENSATION:
++ if (0 != copy_from_user(&p_comp, ifr->ifr_data,
++ sizeof(struct ptp_set_comp)))
++ return -EINVAL;
++ fec_set_drift(fep, &p_comp);
++ break;
++ case PTP_GET_ORIG_COMP:
++ freq_compensation = FEC_PTP_ORIG_COMP;
++ if (copy_to_user(ifr->ifr_data, &freq_compensation,
++ sizeof(freq_compensation)) > 0)
++ return -EFAULT;
++ break;
++ default:
++ return -EINVAL;
+ }
+
+- return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
+- -EFAULT : 0;
++ return retval;
+ }
+-
+ /**
+ * fec_time_keep - call timecounter_read every second to avoid timer overrun
+ * because ENET just support 32bit counter, will timeout in 4s
+@@ -347,8 +914,9 @@
+ * cyclecounter init routine and exits.
+ */
+
+-void fec_ptp_init(struct net_device *ndev, struct platform_device *pdev)
++void fec_ptp_init(struct platform_device *pdev)
+ {
++ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
+ fep->ptp_caps.owner = THIS_MODULE;
+@@ -382,4 +950,22 @@
+ fep->ptp_clock = NULL;
+ pr_err("ptp_clock_register failed\n");
+ }
++
++ /* initialize circular buffer for tx timestamps */
++ if (fec_ptp_init_circ(&(fep->tx_timestamps),
++ (DEFAULT_PTP_TX_BUF_SZ+1)))
++ pr_err("init tx circular buffer failed\n");
++ /* initialize circular buffer for rx timestamps */
++ if (fec_ptp_init_circ(&(fep->rx_timestamps),
++ (DEFAULT_PTP_RX_BUF_SZ+1)))
++ pr_err("init rx curcular buffer failed\n");
+ }
++
++void fec_ptp_cleanup(struct fec_enet_private *priv)
++{
++ if (priv->tx_timestamps.data_buf)
++ vfree(priv->tx_timestamps.data_buf);
++ if (priv->rx_timestamps.data_buf)
++ vfree(priv->rx_timestamps.data_buf);
++}
++
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/fs_enet-main.c 2014-05-15 20:33:59.282023118 +0200
+@@ -583,7 +583,6 @@
+ struct sk_buff *skb)
+ {
+ struct sk_buff *new_skb;
+- struct fs_enet_private *fep = netdev_priv(dev);
+
+ /* Alloc new skb */
+ new_skb = netdev_alloc_skb(dev, skb->len + 4);
+@@ -1000,6 +999,8 @@
+ struct fs_enet_private *fep;
+ struct fs_platform_info *fpi;
+ const u32 *data;
++ struct clk *clk;
++ int err;
+ const u8 *mac_addr;
+ const char *phy_connection_type;
+ int privsize, len, ret = -ENODEV;
+@@ -1037,6 +1038,20 @@
+ fpi->use_rmii = 1;
+ }
+
++ /* make clock lookup non-fatal (the driver is shared among platforms),
++ * but require enable to succeed when a clock was specified/found,
++ * keep a reference to the clock upon successful acquisition
++ */
++ clk = devm_clk_get(&ofdev->dev, "per");
++ if (!IS_ERR(clk)) {
++ err = clk_prepare_enable(clk);
++ if (err) {
++ ret = err;
++ goto out_free_fpi;
++ }
++ fpi->clk_per = clk;
++ }
++
+ privsize = sizeof(*fep) +
+ sizeof(struct sk_buff **) *
+ (fpi->rx_ring + fpi->tx_ring);
+@@ -1048,7 +1063,7 @@
+ }
+
+ SET_NETDEV_DEV(ndev, &ofdev->dev);
+- dev_set_drvdata(&ofdev->dev, ndev);
++ platform_set_drvdata(ofdev, ndev);
+
+ fep = netdev_priv(ndev);
+ fep->dev = &ofdev->dev;
+@@ -1068,7 +1083,7 @@
+
+ mac_addr = of_get_mac_address(ofdev->dev.of_node);
+ if (mac_addr)
+- memcpy(ndev->dev_addr, mac_addr, 6);
++ memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
+
+ ret = fep->ops->allocate_bd(ndev);
+ if (ret)
+@@ -1106,9 +1121,10 @@
+ fep->ops->cleanup_data(ndev);
+ out_free_dev:
+ free_netdev(ndev);
+- dev_set_drvdata(&ofdev->dev, NULL);
+ out_put:
+ of_node_put(fpi->phy_node);
++ if (fpi->clk_per)
++ clk_disable_unprepare(fpi->clk_per);
+ out_free_fpi:
+ kfree(fpi);
+ return ret;
+@@ -1116,7 +1132,7 @@
+
+ static int fs_enet_remove(struct platform_device *ofdev)
+ {
+- struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
++ struct net_device *ndev = platform_get_drvdata(ofdev);
+ struct fs_enet_private *fep = netdev_priv(ndev);
+
+ unregister_netdev(ndev);
+@@ -1125,6 +1141,8 @@
+ fep->ops->cleanup_data(ndev);
+ dev_set_drvdata(fep->dev, NULL);
+ of_node_put(fep->fpi->phy_node);
++ if (fep->fpi->clk_per)
++ clk_disable_unprepare(fep->fpi->clk_per);
+ free_netdev(ndev);
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/Kconfig linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/Kconfig
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/Kconfig 2014-05-15 20:33:59.282023118 +0200
+@@ -1,7 +1,6 @@
+ config FS_ENET
+ tristate "Freescale Ethernet Driver"
+ depends on NET_VENDOR_FREESCALE && (CPM1 || CPM2 || PPC_MPC512x)
+- select NET_CORE
+ select MII
+ select PHYLIB
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mac-fcc.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mac-fcc.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mac-fcc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mac-fcc.c 2014-05-15 20:33:59.282023118 +0200
+@@ -32,7 +32,9 @@
+ #include <linux/fs.h>
+ #include <linux/platform_device.h>
+ #include <linux/phy.h>
++#include <linux/of_address.h>
+ #include <linux/of_device.h>
++#include <linux/of_irq.h>
+ #include <linux/gfp.h>
+
+ #include <asm/immap_cpm2.h>
+@@ -88,7 +90,7 @@
+ struct fs_platform_info *fpi = fep->fpi;
+ int ret = -EINVAL;
+
+- fep->interrupt = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
++ fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0);
+ if (fep->interrupt == NO_IRQ)
+ goto out;
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mac-fec.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mac-fec.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mac-fec.c 2014-05-15 20:33:59.282023118 +0200
+@@ -31,7 +31,9 @@
+ #include <linux/bitops.h>
+ #include <linux/fs.h>
+ #include <linux/platform_device.h>
++#include <linux/of_address.h>
+ #include <linux/of_device.h>
++#include <linux/of_irq.h>
+ #include <linux/gfp.h>
+
+ #include <asm/irq.h>
+@@ -98,7 +100,7 @@
+ {
+ struct platform_device *ofdev = to_platform_device(fep->dev);
+
+- fep->interrupt = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
++ fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0);
+ if (fep->interrupt == NO_IRQ)
+ return -EINVAL;
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mac-scc.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mac-scc.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mac-scc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mac-scc.c 2014-05-15 20:33:59.282023118 +0200
+@@ -31,6 +31,8 @@
+ #include <linux/bitops.h>
+ #include <linux/fs.h>
+ #include <linux/platform_device.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
+ #include <linux/of_platform.h>
+
+ #include <asm/irq.h>
+@@ -98,7 +100,7 @@
+ {
+ struct platform_device *ofdev = to_platform_device(fep->dev);
+
+- fep->interrupt = of_irq_to_resource(ofdev->dev.of_node, 0, NULL);
++ fep->interrupt = irq_of_parse_and_map(ofdev->dev.of_node, 0);
+ if (fep->interrupt == NO_IRQ)
+ return -EINVAL;
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mii-bitbang.c 2014-05-15 20:33:59.282023118 +0200
+@@ -22,6 +22,7 @@
+ #include <linux/mii.h>
+ #include <linux/platform_device.h>
+ #include <linux/mdio-bitbang.h>
++#include <linux/of_address.h>
+ #include <linux/of_mdio.h>
+ #include <linux/of_platform.h>
+
+@@ -179,7 +180,7 @@
+ }
+
+ new_bus->parent = &ofdev->dev;
+- dev_set_drvdata(&ofdev->dev, new_bus);
++ platform_set_drvdata(ofdev, new_bus);
+
+ ret = of_mdiobus_register(new_bus, ofdev->dev.of_node);
+ if (ret)
+@@ -188,7 +189,6 @@
+ return 0;
+
+ out_free_irqs:
+- dev_set_drvdata(&ofdev->dev, NULL);
+ kfree(new_bus->irq);
+ out_unmap_regs:
+ iounmap(bitbang->dir);
+@@ -202,11 +202,10 @@
+
+ static int fs_enet_mdio_remove(struct platform_device *ofdev)
+ {
+- struct mii_bus *bus = dev_get_drvdata(&ofdev->dev);
++ struct mii_bus *bus = platform_get_drvdata(ofdev);
+ struct bb_info *bitbang = bus->priv;
+
+ mdiobus_unregister(bus);
+- dev_set_drvdata(&ofdev->dev, NULL);
+ kfree(bus->irq);
+ free_mdio_bitbang(bus);
+ iounmap(bitbang->dir);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mii-fec.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mii-fec.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fs_enet/mii-fec.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fs_enet/mii-fec.c 2014-05-15 20:33:59.282023118 +0200
+@@ -31,6 +31,7 @@
+ #include <linux/ethtool.h>
+ #include <linux/bitops.h>
+ #include <linux/platform_device.h>
++#include <linux/of_address.h>
+ #include <linux/of_platform.h>
+
+ #include <asm/pgtable.h>
+@@ -180,7 +181,7 @@
+ }
+
+ new_bus->parent = &ofdev->dev;
+- dev_set_drvdata(&ofdev->dev, new_bus);
++ platform_set_drvdata(ofdev, new_bus);
+
+ ret = of_mdiobus_register(new_bus, ofdev->dev.of_node);
+ if (ret)
+@@ -189,7 +190,6 @@
+ return 0;
+
+ out_free_irqs:
+- dev_set_drvdata(&ofdev->dev, NULL);
+ kfree(new_bus->irq);
+ out_unmap_regs:
+ iounmap(fec->fecp);
+@@ -204,11 +204,10 @@
+
+ static int fs_enet_mdio_remove(struct platform_device *ofdev)
+ {
+- struct mii_bus *bus = dev_get_drvdata(&ofdev->dev);
++ struct mii_bus *bus = platform_get_drvdata(ofdev);
+ struct fec_info *fec = bus->priv;
+
+ mdiobus_unregister(bus);
+- dev_set_drvdata(&ofdev->dev, NULL);
+ kfree(bus->irq);
+ iounmap(fec->fecp);
+ kfree(fec);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/fsl_pq_mdio.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fsl_pq_mdio.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/fsl_pq_mdio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/fsl_pq_mdio.c 2014-05-15 20:33:59.282023118 +0200
+@@ -409,7 +409,7 @@
+ priv->regs = priv->map + data->mii_offset;
+
+ new_bus->parent = &pdev->dev;
+- dev_set_drvdata(&pdev->dev, new_bus);
++ platform_set_drvdata(pdev, new_bus);
+
+ if (data->get_tbipa) {
+ for_each_child_of_node(np, tbi) {
+@@ -468,8 +468,6 @@
+
+ mdiobus_unregister(bus);
+
+- dev_set_drvdata(device, NULL);
+-
+ iounmap(priv->map);
+ mdiobus_free(bus);
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/gianfar.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/gianfar.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/gianfar.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/gianfar.c 2014-05-15 20:33:59.282023118 +0200
+@@ -78,6 +78,8 @@
+ #include <linux/if_vlan.h>
+ #include <linux/spinlock.h>
+ #include <linux/mm.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
+ #include <linux/of_mdio.h>
+ #include <linux/of_platform.h>
+ #include <linux/ip.h>
+@@ -88,6 +90,7 @@
+
+ #include <asm/io.h>
+ #include <asm/reg.h>
++#include <asm/mpc85xx.h>
+ #include <asm/irq.h>
+ #include <asm/uaccess.h>
+ #include <linux/module.h>
+@@ -128,6 +131,7 @@
+ static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
+ static void gfar_configure_serdes(struct net_device *dev);
+ static int gfar_poll(struct napi_struct *napi, int budget);
++static int gfar_poll_sq(struct napi_struct *napi, int budget);
+ #ifdef CONFIG_NET_POLL_CONTROLLER
+ static void gfar_netpoll(struct net_device *dev);
+ #endif
+@@ -592,7 +596,6 @@
+ return -EINVAL;
+ }
+
+- grp->grp_id = priv->num_grps;
+ grp->priv = priv;
+ spin_lock_init(&grp->grplock);
+ if (priv->mode == MQ_MG_MODE) {
+@@ -939,9 +942,8 @@
+ }
+ }
+
+-static void gfar_detect_errata(struct gfar_private *priv)
++static void __gfar_detect_errata_83xx(struct gfar_private *priv)
+ {
+- struct device *dev = &priv->ofdev->dev;
+ unsigned int pvr = mfspr(SPRN_PVR);
+ unsigned int svr = mfspr(SPRN_SVR);
+ unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
+@@ -957,15 +959,33 @@
+ (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
+ priv->errata |= GFAR_ERRATA_76;
+
+- /* MPC8313 and MPC837x all rev */
+- if ((pvr == 0x80850010 && mod == 0x80b0) ||
+- (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
+- priv->errata |= GFAR_ERRATA_A002;
++ /* MPC8313 Rev < 2.0 */
++ if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
++ priv->errata |= GFAR_ERRATA_12;
++}
+
+- /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
+- if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
+- (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
++static void __gfar_detect_errata_85xx(struct gfar_private *priv)
++{
++ unsigned int svr = mfspr(SPRN_SVR);
++
++ if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
+ priv->errata |= GFAR_ERRATA_12;
++ if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
++ ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)))
++ priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
++}
++
++static void gfar_detect_errata(struct gfar_private *priv)
++{
++ struct device *dev = &priv->ofdev->dev;
++
++ /* no plans to fix */
++ priv->errata |= GFAR_ERRATA_A002;
++
++ if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
++ __gfar_detect_errata_85xx(priv);
++ else /* non-mpc85xx parts, i.e. e300 core based */
++ __gfar_detect_errata_83xx(priv);
+
+ if (priv->errata)
+ dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
+@@ -1000,7 +1020,7 @@
+ spin_lock_init(&priv->bflock);
+ INIT_WORK(&priv->reset_task, gfar_reset_task);
+
+- dev_set_drvdata(&ofdev->dev, priv);
++ platform_set_drvdata(ofdev, priv);
+ regs = priv->gfargrp[0].regs;
+
+ gfar_detect_errata(priv);
+@@ -1016,7 +1036,14 @@
+ /* We need to delay at least 3 TX clocks */
+ udelay(2);
+
+- tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
++ tempval = 0;
++ if (!priv->pause_aneg_en && priv->tx_pause_en)
++ tempval |= MACCFG1_TX_FLOW;
++ if (!priv->pause_aneg_en && priv->rx_pause_en)
++ tempval |= MACCFG1_RX_FLOW;
++ /* the soft reset bit is not self-resetting, so we need to
++ * clear it before resuming normal operation
++ */
+ gfar_write(&regs->maccfg1, tempval);
+
+ /* Initialize MACCFG2. */
+@@ -1038,9 +1065,13 @@
+ dev->ethtool_ops = &gfar_ethtool_ops;
+
+ /* Register for napi ...We are registering NAPI for each grp */
+- for (i = 0; i < priv->num_grps; i++)
+- netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
++ if (priv->mode == SQ_SG_MODE)
++ netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
+ GFAR_DEV_WEIGHT);
++ else
++ for (i = 0; i < priv->num_grps; i++)
++ netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
++ GFAR_DEV_WEIGHT);
+
+ if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
+ dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
+@@ -1240,15 +1271,13 @@
+
+ static int gfar_remove(struct platform_device *ofdev)
+ {
+- struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
++ struct gfar_private *priv = platform_get_drvdata(ofdev);
+
+ if (priv->phy_node)
+ of_node_put(priv->phy_node);
+ if (priv->tbi_node)
+ of_node_put(priv->tbi_node);
+
+- dev_set_drvdata(&ofdev->dev, NULL);
+-
+ unregister_netdev(priv->ndev);
+ unmap_group_regs(priv);
+ free_gfar_dev(priv);
+@@ -1458,7 +1487,7 @@
+ struct gfar_private *priv = netdev_priv(dev);
+ uint gigabit_support =
+ priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
+- SUPPORTED_1000baseT_Full : 0;
++ GFAR_SUPPORTED_GBIT : 0;
+ phy_interface_t interface;
+
+ priv->oldlink = 0;
+@@ -1590,7 +1619,7 @@
+ /* Normaly TSEC should not hang on GRS commands, so we should
+ * actually wait for IEVENT_GRSC flag.
+ */
+- if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
++ if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
+ return 0;
+
+ /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
+@@ -2049,6 +2078,24 @@
+ return skip_txbd(bdp, 1, base, ring_size);
+ }
+
++/* eTSEC12: csum generation not supported for some fcb offsets */
++static inline bool gfar_csum_errata_12(struct gfar_private *priv,
++ unsigned long fcb_addr)
++{
++ return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
++ (fcb_addr % 0x20) > 0x18);
++}
++
++/* eTSEC76: csum generation for frames larger than 2500 may
++ * cause excess delays before start of transmission
++ */
++static inline bool gfar_csum_errata_76(struct gfar_private *priv,
++ unsigned int len)
++{
++ return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
++ (len > 2500));
++}
++
+ /* This is called by the kernel when a frame is ready for transmission.
+ * It is pointed to by the dev->hard_start_xmit function pointer
+ */
+@@ -2061,23 +2108,11 @@
+ struct txfcb *fcb = NULL;
+ struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
+ u32 lstatus;
+- int i, rq = 0, do_tstamp = 0;
++ int i, rq = 0;
++ int do_tstamp, do_csum, do_vlan;
+ u32 bufaddr;
+ unsigned long flags;
+- unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
+-
+- /* TOE=1 frames larger than 2500 bytes may see excess delays
+- * before start of transmission.
+- */
+- if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
+- skb->ip_summed == CHECKSUM_PARTIAL &&
+- skb->len > 2500)) {
+- int ret;
+-
+- ret = skb_checksum_help(skb);
+- if (ret)
+- return ret;
+- }
++ unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
+
+ rq = skb->queue_mapping;
+ tx_queue = priv->tx_queue[rq];
+@@ -2085,21 +2120,23 @@
+ base = tx_queue->tx_bd_base;
+ regs = tx_queue->grp->regs;
+
++ do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
++ do_vlan = vlan_tx_tag_present(skb);
++ do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
++ priv->hwts_tx_en;
++
++ if (do_csum || do_vlan)
++ fcb_len = GMAC_FCB_LEN;
++
+ /* check if time stamp should be generated */
+- if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
+- priv->hwts_tx_en)) {
+- do_tstamp = 1;
+- fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
+- }
++ if (unlikely(do_tstamp))
++ fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
+
+ /* make space for additional header when fcb is needed */
+- if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
+- vlan_tx_tag_present(skb) ||
+- unlikely(do_tstamp)) &&
+- (skb_headroom(skb) < fcb_length)) {
++ if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
+ struct sk_buff *skb_new;
+
+- skb_new = skb_realloc_headroom(skb, fcb_length);
++ skb_new = skb_realloc_headroom(skb, fcb_len);
+ if (!skb_new) {
+ dev->stats.tx_errors++;
+ kfree_skb(skb);
+@@ -2130,7 +2167,10 @@
+ }
+
+ /* Update transmit stats */
+- tx_queue->stats.tx_bytes += skb->len;
++ bytes_sent = skb->len;
++ tx_queue->stats.tx_bytes += bytes_sent;
++ /* keep Tx bytes on wire for BQL accounting */
++ GFAR_CB(skb)->bytes_sent = bytes_sent;
+ tx_queue->stats.tx_packets++;
+
+ txbdp = txbdp_start = tx_queue->cur_tx;
+@@ -2150,12 +2190,13 @@
+ } else {
+ /* Place the fragment addresses and lengths into the TxBDs */
+ for (i = 0; i < nr_frags; i++) {
++ unsigned int frag_len;
+ /* Point at the next BD, wrapping as needed */
+ txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
+
+- length = skb_shinfo(skb)->frags[i].size;
++ frag_len = skb_shinfo(skb)->frags[i].size;
+
+- lstatus = txbdp->lstatus | length |
++ lstatus = txbdp->lstatus | frag_len |
+ BD_LFLAG(TXBD_READY);
+
+ /* Handle the last BD specially */
+@@ -2165,7 +2206,7 @@
+ bufaddr = skb_frag_dma_map(priv->dev,
+ &skb_shinfo(skb)->frags[i],
+ 0,
+- length,
++ frag_len,
+ DMA_TO_DEVICE);
+
+ /* set the TxBD length and buffer pointer */
+@@ -2182,36 +2223,38 @@
+ memset(skb->data, 0, GMAC_TXPAL_LEN);
+ }
+
+- /* Set up checksumming */
+- if (CHECKSUM_PARTIAL == skb->ip_summed) {
++ /* Add TxFCB if required */
++ if (fcb_len) {
+ fcb = gfar_add_fcb(skb);
+- /* as specified by errata */
+- if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12) &&
+- ((unsigned long)fcb % 0x20) > 0x18)) {
++ lstatus |= BD_LFLAG(TXBD_TOE);
++ }
++
++ /* Set up checksumming */
++ if (do_csum) {
++ gfar_tx_checksum(skb, fcb, fcb_len);
++
++ if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
++ unlikely(gfar_csum_errata_76(priv, skb->len))) {
+ __skb_pull(skb, GMAC_FCB_LEN);
+ skb_checksum_help(skb);
+- } else {
+- lstatus |= BD_LFLAG(TXBD_TOE);
+- gfar_tx_checksum(skb, fcb, fcb_length);
++ if (do_vlan || do_tstamp) {
++ /* put back a new fcb for vlan/tstamp TOE */
++ fcb = gfar_add_fcb(skb);
++ } else {
++ /* Tx TOE not used */
++ lstatus &= ~(BD_LFLAG(TXBD_TOE));
++ fcb = NULL;
++ }
+ }
+ }
+
+- if (vlan_tx_tag_present(skb)) {
+- if (unlikely(NULL == fcb)) {
+- fcb = gfar_add_fcb(skb);
+- lstatus |= BD_LFLAG(TXBD_TOE);
+- }
+-
++ if (do_vlan)
+ gfar_tx_vlan(skb, fcb);
+- }
+
+ /* Setup tx hardware time stamping if requested */
+ if (unlikely(do_tstamp)) {
+ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+- if (fcb == NULL)
+- fcb = gfar_add_fcb(skb);
+ fcb->ptp = 1;
+- lstatus |= BD_LFLAG(TXBD_TOE);
+ }
+
+ txbdp_start->bufPtr = dma_map_single(priv->dev, skb->data,
+@@ -2223,15 +2266,15 @@
+ * the full frame length.
+ */
+ if (unlikely(do_tstamp)) {
+- txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
++ txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_len;
+ txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
+- (skb_headlen(skb) - fcb_length);
++ (skb_headlen(skb) - fcb_len);
+ lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
+ } else {
+ lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
+ }
+
+- netdev_tx_sent_queue(txq, skb->len);
++ netdev_tx_sent_queue(txq, bytes_sent);
+
+ /* We can work in parallel with gfar_clean_tx_ring(), except
+ * when modifying num_txbdfree. Note that we didn't grab the lock
+@@ -2551,7 +2594,7 @@
+ bdp = next_txbd(bdp, base, tx_ring_size);
+ }
+
+- bytes_sent += skb->len;
++ bytes_sent += GFAR_CB(skb)->bytes_sent;
+
+ dev_kfree_skb_any(skb);
+
+@@ -2825,6 +2868,48 @@
+ return howmany;
+ }
+
++static int gfar_poll_sq(struct napi_struct *napi, int budget)
++{
++ struct gfar_priv_grp *gfargrp =
++ container_of(napi, struct gfar_priv_grp, napi);
++ struct gfar __iomem *regs = gfargrp->regs;
++ struct gfar_priv_tx_q *tx_queue = gfargrp->priv->tx_queue[0];
++ struct gfar_priv_rx_q *rx_queue = gfargrp->priv->rx_queue[0];
++ int work_done = 0;
++
++ /* Clear IEVENT, so interrupts aren't called again
++ * because of the packets that have already arrived
++ */
++ gfar_write(&regs->ievent, IEVENT_RTX_MASK);
++
++ /* run Tx cleanup to completion */
++ if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
++ gfar_clean_tx_ring(tx_queue);
++
++ work_done = gfar_clean_rx_ring(rx_queue, budget);
++
++ if (work_done < budget) {
++ napi_complete(napi);
++ /* Clear the halt bit in RSTAT */
++ gfar_write(&regs->rstat, gfargrp->rstat);
++
++ gfar_write(&regs->imask, IMASK_DEFAULT);
++
++ /* If we are coalescing interrupts, update the timer
++ * Otherwise, clear it
++ */
++ gfar_write(&regs->txic, 0);
++ if (likely(tx_queue->txcoalescing))
++ gfar_write(&regs->txic, tx_queue->txic);
++
++ gfar_write(&regs->rxic, 0);
++ if (unlikely(rx_queue->rxcoalescing))
++ gfar_write(&regs->rxic, rx_queue->rxic);
++ }
++
++ return work_done;
++}
++
+ static int gfar_poll(struct napi_struct *napi, int budget)
+ {
+ struct gfar_priv_grp *gfargrp =
+@@ -2835,7 +2920,7 @@
+ struct gfar_priv_rx_q *rx_queue = NULL;
+ int work_done = 0, work_done_per_q = 0;
+ int i, budget_per_q = 0;
+- int has_tx_work;
++ int has_tx_work = 0;
+ unsigned long rstat_rxf;
+ int num_act_queues;
+
+@@ -2850,62 +2935,51 @@
+ if (num_act_queues)
+ budget_per_q = budget/num_act_queues;
+
+- while (1) {
+- has_tx_work = 0;
+- for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
+- tx_queue = priv->tx_queue[i];
+- /* run Tx cleanup to completion */
+- if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
+- gfar_clean_tx_ring(tx_queue);
+- has_tx_work = 1;
+- }
++ for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
++ tx_queue = priv->tx_queue[i];
++ /* run Tx cleanup to completion */
++ if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
++ gfar_clean_tx_ring(tx_queue);
++ has_tx_work = 1;
+ }
++ }
+
+- for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
+- /* skip queue if not active */
+- if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
+- continue;
+-
+- rx_queue = priv->rx_queue[i];
+- work_done_per_q =
+- gfar_clean_rx_ring(rx_queue, budget_per_q);
+- work_done += work_done_per_q;
+-
+- /* finished processing this queue */
+- if (work_done_per_q < budget_per_q) {
+- /* clear active queue hw indication */
+- gfar_write(&regs->rstat,
+- RSTAT_CLEAR_RXF0 >> i);
+- rstat_rxf &= ~(RSTAT_CLEAR_RXF0 >> i);
+- num_act_queues--;
+-
+- if (!num_act_queues)
+- break;
+- /* recompute budget per Rx queue */
+- budget_per_q =
+- (budget - work_done) / num_act_queues;
+- }
+- }
++ for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
++ /* skip queue if not active */
++ if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
++ continue;
+
+- if (work_done >= budget)
+- break;
++ rx_queue = priv->rx_queue[i];
++ work_done_per_q =
++ gfar_clean_rx_ring(rx_queue, budget_per_q);
++ work_done += work_done_per_q;
++
++ /* finished processing this queue */
++ if (work_done_per_q < budget_per_q) {
++ /* clear active queue hw indication */
++ gfar_write(&regs->rstat,
++ RSTAT_CLEAR_RXF0 >> i);
++ num_act_queues--;
+
+- if (!num_act_queues && !has_tx_work) {
++ if (!num_act_queues)
++ break;
++ }
++ }
+
+- napi_complete(napi);
++ if (!num_act_queues && !has_tx_work) {
+
+- /* Clear the halt bit in RSTAT */
+- gfar_write(&regs->rstat, gfargrp->rstat);
++ napi_complete(napi);
+
+- gfar_write(&regs->imask, IMASK_DEFAULT);
++ /* Clear the halt bit in RSTAT */
++ gfar_write(&regs->rstat, gfargrp->rstat);
+
+- /* If we are coalescing interrupts, update the timer
+- * Otherwise, clear it
+- */
+- gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
+- gfargrp->tx_bit_map);
+- break;
+- }
++ gfar_write(&regs->imask, IMASK_DEFAULT);
++
++ /* If we are coalescing interrupts, update the timer
++ * Otherwise, clear it
++ */
++ gfar_configure_coalescing(priv, gfargrp->rx_bit_map,
++ gfargrp->tx_bit_map);
+ }
+
+ return work_done;
+@@ -2969,6 +3043,41 @@
+ return IRQ_HANDLED;
+ }
+
++static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
++{
++ struct phy_device *phydev = priv->phydev;
++ u32 val = 0;
++
++ if (!phydev->duplex)
++ return val;
++
++ if (!priv->pause_aneg_en) {
++ if (priv->tx_pause_en)
++ val |= MACCFG1_TX_FLOW;
++ if (priv->rx_pause_en)
++ val |= MACCFG1_RX_FLOW;
++ } else {
++ u16 lcl_adv, rmt_adv;
++ u8 flowctrl;
++ /* get link partner capabilities */
++ rmt_adv = 0;
++ if (phydev->pause)
++ rmt_adv = LPA_PAUSE_CAP;
++ if (phydev->asym_pause)
++ rmt_adv |= LPA_PAUSE_ASYM;
++
++ lcl_adv = mii_advertise_flowctrl(phydev->advertising);
++
++ flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
++ if (flowctrl & FLOW_CTRL_TX)
++ val |= MACCFG1_TX_FLOW;
++ if (flowctrl & FLOW_CTRL_RX)
++ val |= MACCFG1_RX_FLOW;
++ }
++
++ return val;
++}
++
+ /* Called every time the controller might need to be made
+ * aware of new link state. The PHY code conveys this
+ * information through variables in the phydev structure, and this
+@@ -2987,6 +3096,7 @@
+ lock_tx_qs(priv);
+
+ if (phydev->link) {
++ u32 tempval1 = gfar_read(&regs->maccfg1);
+ u32 tempval = gfar_read(&regs->maccfg2);
+ u32 ecntrl = gfar_read(&regs->ecntrl);
+
+@@ -3035,6 +3145,10 @@
+ priv->oldspeed = phydev->speed;
+ }
+
++ tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
++ tempval1 |= gfar_get_flowctrl_cfg(priv);
++
++ gfar_write(&regs->maccfg1, tempval1);
+ gfar_write(&regs->maccfg2, tempval);
+ gfar_write(&regs->ecntrl, ecntrl);
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/gianfar_ethtool.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/gianfar_ethtool.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/gianfar_ethtool.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/gianfar_ethtool.c 2014-05-15 20:33:59.282023118 +0200
+@@ -535,6 +535,78 @@
+ return err;
+ }
+
++static void gfar_gpauseparam(struct net_device *dev,
++ struct ethtool_pauseparam *epause)
++{
++ struct gfar_private *priv = netdev_priv(dev);
++
++ epause->autoneg = !!priv->pause_aneg_en;
++ epause->rx_pause = !!priv->rx_pause_en;
++ epause->tx_pause = !!priv->tx_pause_en;
++}
++
++static int gfar_spauseparam(struct net_device *dev,
++ struct ethtool_pauseparam *epause)
++{
++ struct gfar_private *priv = netdev_priv(dev);
++ struct phy_device *phydev = priv->phydev;
++ struct gfar __iomem *regs = priv->gfargrp[0].regs;
++ u32 oldadv, newadv;
++
++ if (!(phydev->supported & SUPPORTED_Pause) ||
++ (!(phydev->supported & SUPPORTED_Asym_Pause) &&
++ (epause->rx_pause != epause->tx_pause)))
++ return -EINVAL;
++
++ priv->rx_pause_en = priv->tx_pause_en = 0;
++ if (epause->rx_pause) {
++ priv->rx_pause_en = 1;
++
++ if (epause->tx_pause) {
++ priv->tx_pause_en = 1;
++ /* FLOW_CTRL_RX & TX */
++ newadv = ADVERTISED_Pause;
++ } else /* FLOW_CTLR_RX */
++ newadv = ADVERTISED_Pause | ADVERTISED_Asym_Pause;
++ } else if (epause->tx_pause) {
++ priv->tx_pause_en = 1;
++ /* FLOW_CTLR_TX */
++ newadv = ADVERTISED_Asym_Pause;
++ } else
++ newadv = 0;
++
++ if (epause->autoneg)
++ priv->pause_aneg_en = 1;
++ else
++ priv->pause_aneg_en = 0;
++
++ oldadv = phydev->advertising &
++ (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
++ if (oldadv != newadv) {
++ phydev->advertising &=
++ ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
++ phydev->advertising |= newadv;
++ if (phydev->autoneg)
++ /* inform link partner of our
++ * new flow ctrl settings
++ */
++ return phy_start_aneg(phydev);
++
++ if (!epause->autoneg) {
++ u32 tempval;
++ tempval = gfar_read(&regs->maccfg1);
++ tempval &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
++ if (priv->tx_pause_en)
++ tempval |= MACCFG1_TX_FLOW;
++ if (priv->rx_pause_en)
++ tempval |= MACCFG1_RX_FLOW;
++ gfar_write(&regs->maccfg1, tempval);
++ }
++ }
++
++ return 0;
++}
++
+ int gfar_set_features(struct net_device *dev, netdev_features_t features)
+ {
+ struct gfar_private *priv = netdev_priv(dev);
+@@ -1806,6 +1878,8 @@
+ .set_coalesce = gfar_scoalesce,
+ .get_ringparam = gfar_gringparam,
+ .set_ringparam = gfar_sringparam,
++ .get_pauseparam = gfar_gpauseparam,
++ .set_pauseparam = gfar_spauseparam,
+ .get_strings = gfar_gstrings,
+ .get_sset_count = gfar_sset_count,
+ .get_ethtool_stats = gfar_fill_stats,
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/gianfar.h linux-linaro-stable-mx6/drivers/net/ethernet/freescale/gianfar.h
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/gianfar.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/gianfar.h 2014-05-15 20:33:59.282023118 +0200
+@@ -146,6 +146,10 @@
+ | SUPPORTED_Autoneg \
+ | SUPPORTED_MII)
+
++#define GFAR_SUPPORTED_GBIT (SUPPORTED_1000baseT_Full \
++ | SUPPORTED_Pause \
++ | SUPPORTED_Asym_Pause)
++
+ /* TBI register addresses */
+ #define MII_TBICON 0x11
+
+@@ -571,7 +575,7 @@
+ };
+
+ struct gianfar_skb_cb {
+- int alignamount;
++ unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */
+ };
+
+ #define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
+@@ -1009,7 +1013,6 @@
+ * @napi: the napi poll function
+ * @priv: back pointer to the priv structure
+ * @regs: the ioremapped register space for this group
+- * @grp_id: group id for this group
+ * @irqinfo: TX/RX/ER irq data for this group
+ */
+
+@@ -1018,11 +1021,10 @@
+ struct napi_struct napi;
+ struct gfar_private *priv;
+ struct gfar __iomem *regs;
+- unsigned int grp_id;
++ unsigned int rstat;
+ unsigned long num_rx_queues;
+ unsigned long rx_bit_map;
+ /* cacheline 3 */
+- unsigned int rstat;
+ unsigned int tstat;
+ unsigned long num_tx_queues;
+ unsigned long tx_bit_map;
+@@ -1102,7 +1104,11 @@
+ /* Wake-on-LAN enabled */
+ wol_en:1,
+ /* Enable priorty based Tx scheduling in Hw */
+- prio_sched_en:1;
++ prio_sched_en:1,
++ /* Flow control flags */
++ pause_aneg_en:1,
++ tx_pause_en:1,
++ rx_pause_en:1;
+
+ /* The total tx and rx ring size for the enabled queues */
+ unsigned int total_tx_ring_size;
+@@ -1171,21 +1177,21 @@
+ *fpr = gfar_read(&regs->rqfpr);
+ }
+
+-extern void lock_rx_qs(struct gfar_private *priv);
+-extern void lock_tx_qs(struct gfar_private *priv);
+-extern void unlock_rx_qs(struct gfar_private *priv);
+-extern void unlock_tx_qs(struct gfar_private *priv);
+-extern irqreturn_t gfar_receive(int irq, void *dev_id);
+-extern int startup_gfar(struct net_device *dev);
+-extern void stop_gfar(struct net_device *dev);
+-extern void gfar_halt(struct net_device *dev);
+-extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
+- int enable, u32 regnum, u32 read);
+-extern void gfar_configure_coalescing_all(struct gfar_private *priv);
++void lock_rx_qs(struct gfar_private *priv);
++void lock_tx_qs(struct gfar_private *priv);
++void unlock_rx_qs(struct gfar_private *priv);
++void unlock_tx_qs(struct gfar_private *priv);
++irqreturn_t gfar_receive(int irq, void *dev_id);
++int startup_gfar(struct net_device *dev);
++void stop_gfar(struct net_device *dev);
++void gfar_halt(struct net_device *dev);
++void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable,
++ u32 regnum, u32 read);
++void gfar_configure_coalescing_all(struct gfar_private *priv);
+ void gfar_init_sysfs(struct net_device *dev);
+ int gfar_set_features(struct net_device *dev, netdev_features_t features);
+-extern void gfar_check_rx_parser_mode(struct gfar_private *priv);
+-extern void gfar_vlan_mode(struct net_device *dev, netdev_features_t features);
++void gfar_check_rx_parser_mode(struct gfar_private *priv);
++void gfar_vlan_mode(struct net_device *dev, netdev_features_t features);
+
+ extern const struct ethtool_ops gfar_ethtool_ops;
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/gianfar_ptp.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/gianfar_ptp.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/gianfar_ptp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/gianfar_ptp.c 2014-05-15 20:33:59.282023118 +0200
+@@ -452,7 +452,9 @@
+ err = -ENODEV;
+
+ etsects->caps = ptp_gianfar_caps;
+- etsects->cksel = DEFAULT_CKSEL;
++
++ if (get_of_u32(node, "fsl,cksel", &etsects->cksel))
++ etsects->cksel = DEFAULT_CKSEL;
+
+ if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
+ get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
+@@ -519,7 +521,7 @@
+ }
+ gfar_phc_index = ptp_clock_index(etsects->clock);
+
+- dev_set_drvdata(&dev->dev, etsects);
++ platform_set_drvdata(dev, etsects);
+
+ return 0;
+
+@@ -537,7 +539,7 @@
+
+ static int gianfar_ptp_remove(struct platform_device *dev)
+ {
+- struct etsects *etsects = dev_get_drvdata(&dev->dev);
++ struct etsects *etsects = platform_get_drvdata(dev);
+
+ gfar_write(&etsects->regs->tmr_temask, 0);
+ gfar_write(&etsects->regs->tmr_ctrl, 0);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/ucc_geth.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/ucc_geth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/ucc_geth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/ucc_geth.c 2014-05-15 20:33:59.286023146 +0200
+@@ -31,6 +31,8 @@
+ #include <linux/mii.h>
+ #include <linux/phy.h>
+ #include <linux/workqueue.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
+ #include <linux/of_mdio.h>
+ #include <linux/of_net.h>
+ #include <linux/of_platform.h>
+@@ -3564,7 +3566,7 @@
+
+ static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
+ {
+- struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
++ struct net_device *ndev = platform_get_drvdata(ofdev);
+ struct ucc_geth_private *ugeth = netdev_priv(ndev);
+
+ if (!netif_running(ndev))
+@@ -3592,7 +3594,7 @@
+
+ static int ucc_geth_resume(struct platform_device *ofdev)
+ {
+- struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
++ struct net_device *ndev = platform_get_drvdata(ofdev);
+ struct ucc_geth_private *ugeth = netdev_priv(ndev);
+ int err;
+
+@@ -3899,7 +3901,7 @@
+
+ mac_addr = of_get_mac_address(np);
+ if (mac_addr)
+- memcpy(dev->dev_addr, mac_addr, 6);
++ memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
+
+ ugeth->ug_info = ug_info;
+ ugeth->dev = device;
+@@ -3911,14 +3913,12 @@
+
+ static int ucc_geth_remove(struct platform_device* ofdev)
+ {
+- struct device *device = &ofdev->dev;
+- struct net_device *dev = dev_get_drvdata(device);
++ struct net_device *dev = platform_get_drvdata(ofdev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
+
+ unregister_netdev(dev);
+ free_netdev(dev);
+ ucc_geth_memclean(ugeth);
+- dev_set_drvdata(device, NULL);
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/freescale/xgmac_mdio.c linux-linaro-stable-mx6/drivers/net/ethernet/freescale/xgmac_mdio.c
+--- linux-3.10.30.orig/drivers/net/ethernet/freescale/xgmac_mdio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/freescale/xgmac_mdio.c 2014-05-15 20:33:59.286023146 +0200
+@@ -17,6 +17,7 @@
+ #include <linux/module.h>
+ #include <linux/phy.h>
+ #include <linux/mdio.h>
++#include <linux/of_address.h>
+ #include <linux/of_platform.h>
+ #include <linux/of_mdio.h>
+
+@@ -227,7 +228,7 @@
+ goto err_registration;
+ }
+
+- dev_set_drvdata(&pdev->dev, bus);
++ platform_set_drvdata(pdev, bus);
+
+ return 0;
+
+@@ -242,7 +243,7 @@
+
+ static int xgmac_mdio_remove(struct platform_device *pdev)
+ {
+- struct mii_bus *bus = dev_get_drvdata(&pdev->dev);
++ struct mii_bus *bus = platform_get_drvdata(pdev);
+
+ mdiobus_unregister(bus);
+ iounmap(bus->priv);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/korina.c linux-linaro-stable-mx6/drivers/net/ethernet/korina.c
+--- linux-3.10.30.orig/drivers/net/ethernet/korina.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/korina.c 2014-05-15 20:33:59.606025453 +0200
+@@ -1214,7 +1214,6 @@
+ iounmap(lp->rx_dma_regs);
+ iounmap(lp->tx_dma_regs);
+
+- platform_set_drvdata(pdev, NULL);
+ unregister_netdev(bif->dev);
+ free_netdev(bif->dev);
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/marvell/mv643xx_eth.c linux-linaro-stable-mx6/drivers/net/ethernet/marvell/mv643xx_eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/marvell/mv643xx_eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/marvell/mv643xx_eth.c 2014-05-15 20:33:59.610025481 +0200
+@@ -2811,8 +2811,6 @@
+
+ free_netdev(mp->dev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/marvell/mvneta.c linux-linaro-stable-mx6/drivers/net/ethernet/marvell/mvneta.c
+--- linux-3.10.30.orig/drivers/net/ethernet/marvell/mvneta.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/marvell/mvneta.c 2014-05-15 20:33:59.650025770 +0200
+@@ -2815,8 +2815,6 @@
+ irq_dispose_mapping(dev->irq);
+ free_netdev(dev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/marvell/pxa168_eth.c linux-linaro-stable-mx6/drivers/net/ethernet/marvell/pxa168_eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/marvell/pxa168_eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/marvell/pxa168_eth.c 2014-05-15 20:33:59.650025770 +0200
+@@ -1602,7 +1602,6 @@
+ unregister_netdev(dev);
+ cancel_work_sync(&pep->tx_timeout_task);
+ free_netdev(dev);
+- platform_set_drvdata(pdev, NULL);
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/micrel/ks8695net.c linux-linaro-stable-mx6/drivers/net/ethernet/micrel/ks8695net.c
+--- linux-3.10.30.orig/drivers/net/ethernet/micrel/ks8695net.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/micrel/ks8695net.c 2014-05-15 20:33:59.662025857 +0200
+@@ -1600,7 +1600,6 @@
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct ks8695_priv *ksp = netdev_priv(ndev);
+
+- platform_set_drvdata(pdev, NULL);
+ netif_napi_del(&ksp->napi);
+
+ unregister_netdev(ndev);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/micrel/ks8842.c linux-linaro-stable-mx6/drivers/net/ethernet/micrel/ks8842.c
+--- linux-3.10.30.orig/drivers/net/ethernet/micrel/ks8842.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/micrel/ks8842.c 2014-05-15 20:33:59.666025885 +0200
+@@ -1250,7 +1250,6 @@
+ iounmap(adapter->hw_addr);
+ free_netdev(netdev);
+ release_mem_region(iomem->start, resource_size(iomem));
+- platform_set_drvdata(pdev, NULL);
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/micrel/ks8851_mll.c linux-linaro-stable-mx6/drivers/net/ethernet/micrel/ks8851_mll.c
+--- linux-3.10.30.orig/drivers/net/ethernet/micrel/ks8851_mll.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/micrel/ks8851_mll.c 2014-05-15 20:33:59.666025885 +0200
+@@ -1671,7 +1671,6 @@
+ iounmap(ks->hw_addr);
+ free_netdev(netdev);
+ release_mem_region(iomem->start, resource_size(iomem));
+- platform_set_drvdata(pdev, NULL);
+ return 0;
+
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/netx-eth.c linux-linaro-stable-mx6/drivers/net/ethernet/netx-eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/netx-eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/netx-eth.c 2014-05-15 20:33:59.742026433 +0200
+@@ -422,7 +422,6 @@
+ exit_free_xc:
+ free_xc(priv->xc);
+ exit_free_netdev:
+- platform_set_drvdata(pdev, NULL);
+ free_netdev(ndev);
+ exit:
+ return ret;
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/nuvoton/w90p910_ether.c linux-linaro-stable-mx6/drivers/net/ethernet/nuvoton/w90p910_ether.c
+--- linux-3.10.30.orig/drivers/net/ethernet/nuvoton/w90p910_ether.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/nuvoton/w90p910_ether.c 2014-05-15 20:33:59.742026433 +0200
+@@ -1051,7 +1051,6 @@
+ clk_put(ether->clk);
+ failed_free_rxirq:
+ free_irq(ether->rxirq, pdev);
+- platform_set_drvdata(pdev, NULL);
+ failed_free_txirq:
+ free_irq(ether->txirq, pdev);
+ failed_free_io:
+@@ -1080,7 +1079,6 @@
+ free_irq(ether->rxirq, dev);
+
+ del_timer_sync(&ether->check_timer);
+- platform_set_drvdata(pdev, NULL);
+
+ free_netdev(dev);
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/nxp/lpc_eth.c linux-linaro-stable-mx6/drivers/net/ethernet/nxp/lpc_eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/nxp/lpc_eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/nxp/lpc_eth.c 2014-05-15 20:33:59.746026462 +0200
+@@ -1483,7 +1483,6 @@
+ return 0;
+
+ err_out_unregister_netdev:
+- platform_set_drvdata(pdev, NULL);
+ unregister_netdev(ndev);
+ err_out_dma_unmap:
+ if (!use_iram_for_net(&pldat->pdev->dev) ||
+@@ -1511,7 +1510,6 @@
+ struct netdata_local *pldat = netdev_priv(ndev);
+
+ unregister_netdev(ndev);
+- platform_set_drvdata(pdev, NULL);
+
+ if (!use_iram_for_net(&pldat->pdev->dev) ||
+ pldat->dma_buff_size > lpc32xx_return_iram_size())
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/renesas/sh_eth.c linux-linaro-stable-mx6/drivers/net/ethernet/renesas/sh_eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/renesas/sh_eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/renesas/sh_eth.c 2014-05-15 20:33:59.814026951 +0200
+@@ -2814,7 +2814,6 @@
+ unregister_netdev(ndev);
+ pm_runtime_disable(&pdev->dev);
+ free_netdev(ndev);
+- platform_set_drvdata(pdev, NULL);
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/s6gmac.c linux-linaro-stable-mx6/drivers/net/ethernet/s6gmac.c
+--- linux-3.10.30.orig/drivers/net/ethernet/s6gmac.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/s6gmac.c 2014-05-15 20:33:59.814026951 +0200
+@@ -1040,7 +1040,6 @@
+ unregister_netdev(dev);
+ free_irq(dev->irq, dev);
+ free_netdev(dev);
+- platform_set_drvdata(pdev, NULL);
+ }
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/seeq/sgiseeq.c linux-linaro-stable-mx6/drivers/net/ethernet/seeq/sgiseeq.c
+--- linux-3.10.30.orig/drivers/net/ethernet/seeq/sgiseeq.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/seeq/sgiseeq.c 2014-05-15 20:33:59.818026980 +0200
+@@ -818,7 +818,6 @@
+ dma_free_noncoherent(&pdev->dev, sizeof(*sp->srings), sp->srings,
+ sp->srings_dma);
+ free_netdev(dev);
+- platform_set_drvdata(pdev, NULL);
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/sgi/meth.c linux-linaro-stable-mx6/drivers/net/ethernet/sgi/meth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/sgi/meth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/sgi/meth.c 2014-05-15 20:33:59.826027038 +0200
+@@ -863,7 +863,6 @@
+
+ unregister_netdev(dev);
+ free_netdev(dev);
+- platform_set_drvdata(pdev, NULL);
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/smsc/smc911x.c linux-linaro-stable-mx6/drivers/net/ethernet/smsc/smc911x.c
+--- linux-3.10.30.orig/drivers/net/ethernet/smsc/smc911x.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/smsc/smc911x.c 2014-05-15 20:33:59.830027066 +0200
+@@ -2087,7 +2087,6 @@
+ ndev->base_addr = res->start;
+ ret = smc911x_probe(ndev);
+ if (ret != 0) {
+- platform_set_drvdata(pdev, NULL);
+ iounmap(addr);
+ release_both:
+ free_netdev(ndev);
+@@ -2113,7 +2112,6 @@
+ struct resource *res;
+
+ DBG(SMC_DEBUG_FUNC, "--> %s\n", __func__);
+- platform_set_drvdata(pdev, NULL);
+
+ unregister_netdev(ndev);
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/smsc/smc91x.c linux-linaro-stable-mx6/drivers/net/ethernet/smsc/smc91x.c
+--- linux-3.10.30.orig/drivers/net/ethernet/smsc/smc91x.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/smsc/smc91x.c 2014-05-15 20:33:59.834027096 +0200
+@@ -1896,7 +1896,7 @@
+ SMC_SELECT_BANK(lp, 1);
+ val = SMC_GET_BASE(lp);
+ val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
+- if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
++ if (((unsigned long)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
+ printk("%s: IOADDR %p doesn't match configuration (%x).\n",
+ CARDNAME, ioaddr, val);
+ }
+@@ -2299,7 +2299,6 @@
+ return 0;
+
+ out_iounmap:
+- platform_set_drvdata(pdev, NULL);
+ iounmap(addr);
+ out_release_attrib:
+ smc_release_attrib(pdev, ndev);
+@@ -2319,8 +2318,6 @@
+ struct smc_local *lp = netdev_priv(ndev);
+ struct resource *res;
+
+- platform_set_drvdata(pdev, NULL);
+-
+ unregister_netdev(ndev);
+
+ free_irq(ndev->irq, ndev);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/smsc/smsc911x.c linux-linaro-stable-mx6/drivers/net/ethernet/smsc/smsc911x.c
+--- linux-3.10.30.orig/drivers/net/ethernet/smsc/smsc911x.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/smsc/smsc911x.c 2014-05-15 20:33:59.834027096 +0200
+@@ -2284,7 +2284,6 @@
+ mdiobus_unregister(pdata->mii_bus);
+ mdiobus_free(pdata->mii_bus);
+
+- platform_set_drvdata(pdev, NULL);
+ unregister_netdev(dev);
+ free_irq(dev->irq, dev);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+@@ -2539,7 +2538,6 @@
+ out_enable_resources_fail:
+ smsc911x_free_resources(pdev);
+ out_request_resources_fail:
+- platform_set_drvdata(pdev, NULL);
+ iounmap(pdata->ioaddr);
+ free_netdev(dev);
+ out_release_io_1:
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c linux-linaro-stable-mx6/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+--- linux-3.10.30.orig/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 2014-05-15 20:33:59.850027210 +0200
+@@ -171,8 +171,6 @@
+ if (priv->plat->exit)
+ priv->plat->exit(pdev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ return ret;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/ti/cpsw.c linux-linaro-stable-mx6/drivers/net/ethernet/ti/cpsw.c
+--- linux-3.10.30.orig/drivers/net/ethernet/ti/cpsw.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/ti/cpsw.c 2014-05-15 20:33:59.862027297 +0200
+@@ -1940,7 +1940,6 @@
+ struct cpsw_priv *priv = netdev_priv(ndev);
+ int i;
+
+- platform_set_drvdata(pdev, NULL);
+ if (priv->data.dual_emac)
+ unregister_netdev(cpsw_get_slave_ndev(priv, 1));
+ unregister_netdev(ndev);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/ti/davinci_emac.c linux-linaro-stable-mx6/drivers/net/ethernet/ti/davinci_emac.c
+--- linux-3.10.30.orig/drivers/net/ethernet/ti/davinci_emac.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/ti/davinci_emac.c 2014-05-15 20:33:59.862027297 +0200
+@@ -2036,8 +2036,6 @@
+
+ dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
+
+- platform_set_drvdata(pdev, NULL);
+-
+ if (priv->txchan)
+ cpdma_chan_destroy(priv->txchan);
+ if (priv->rxchan)
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/tundra/tsi108_eth.c linux-linaro-stable-mx6/drivers/net/ethernet/tundra/tsi108_eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/tundra/tsi108_eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/tundra/tsi108_eth.c 2014-05-15 20:33:59.886027470 +0200
+@@ -1682,7 +1682,6 @@
+
+ unregister_netdev(dev);
+ tsi108_stop_ethernet(dev);
+- platform_set_drvdata(pdev, NULL);
+ iounmap(priv->regs);
+ iounmap(priv->phyregs);
+ free_netdev(dev);
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/wiznet/w5100.c linux-linaro-stable-mx6/drivers/net/ethernet/wiznet/w5100.c
+--- linux-3.10.30.orig/drivers/net/ethernet/wiznet/w5100.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/wiznet/w5100.c 2014-05-15 20:33:59.914027672 +0200
+@@ -734,7 +734,6 @@
+ unregister_netdev(ndev);
+ err_register:
+ free_netdev(ndev);
+- platform_set_drvdata(pdev, NULL);
+ return err;
+ }
+
+@@ -750,7 +749,6 @@
+
+ unregister_netdev(ndev);
+ free_netdev(ndev);
+- platform_set_drvdata(pdev, NULL);
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/wiznet/w5300.c linux-linaro-stable-mx6/drivers/net/ethernet/wiznet/w5300.c
+--- linux-3.10.30.orig/drivers/net/ethernet/wiznet/w5300.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/wiznet/w5300.c 2014-05-15 20:33:59.918027701 +0200
+@@ -646,7 +646,6 @@
+ unregister_netdev(ndev);
+ err_register:
+ free_netdev(ndev);
+- platform_set_drvdata(pdev, NULL);
+ return err;
+ }
+
+@@ -662,7 +661,6 @@
+
+ unregister_netdev(ndev);
+ free_netdev(ndev);
+- platform_set_drvdata(pdev, NULL);
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/net/ethernet/xscale/ixp4xx_eth.c linux-linaro-stable-mx6/drivers/net/ethernet/xscale/ixp4xx_eth.c
+--- linux-3.10.30.orig/drivers/net/ethernet/xscale/ixp4xx_eth.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/ethernet/xscale/ixp4xx_eth.c 2014-05-15 20:33:59.942027873 +0200
+@@ -1472,7 +1472,6 @@
+ phy_disconnect(port->phydev);
+ err_free_mem:
+ npe_port_tab[NPE_ID(port->id)] = NULL;
+- platform_set_drvdata(pdev, NULL);
+ release_resource(port->mem_res);
+ err_npe_rel:
+ npe_release(port->npe);
+@@ -1489,7 +1488,6 @@
+ unregister_netdev(dev);
+ phy_disconnect(port->phydev);
+ npe_port_tab[NPE_ID(port->id)] = NULL;
+- platform_set_drvdata(pdev, NULL);
+ npe_release(port->npe);
+ release_resource(port->mem_res);
+ free_netdev(dev);
+diff -Nur linux-3.10.30.orig/drivers/net/phy/phy.c linux-linaro-stable-mx6/drivers/net/phy/phy.c
+--- linux-3.10.30.orig/drivers/net/phy/phy.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/phy/phy.c 2014-05-15 20:34:00.050028652 +0200
+@@ -439,7 +439,7 @@
+ {
+ phydev->adjust_state = handler;
+
+- schedule_delayed_work(&phydev->state_queue, HZ);
++ queue_delayed_work(system_power_efficient_wq, &phydev->state_queue, HZ);
+ }
+
+ /**
+@@ -500,7 +500,7 @@
+ disable_irq_nosync(irq);
+ atomic_inc(&phydev->irq_disable);
+
+- schedule_work(&phydev->phy_queue);
++ queue_work(system_power_efficient_wq, &phydev->phy_queue);
+
+ return IRQ_HANDLED;
+ }
+@@ -655,7 +655,7 @@
+
+ /* reschedule state queue work to run as soon as possible */
+ cancel_delayed_work_sync(&phydev->state_queue);
+- schedule_delayed_work(&phydev->state_queue, 0);
++ queue_delayed_work(system_power_efficient_wq, &phydev->state_queue, 0);
+
+ return;
+
+@@ -918,7 +918,8 @@
+ if (err < 0)
+ phy_error(phydev);
+
+- schedule_delayed_work(&phydev->state_queue, PHY_STATE_TIME * HZ);
++ queue_delayed_work(system_power_efficient_wq, &phydev->state_queue,
++ PHY_STATE_TIME * HZ);
+ }
+
+ static inline void mmd_phy_indirect(struct mii_bus *bus, int prtad, int devad,
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/ath/ath6kl/hif.h linux-linaro-stable-mx6/drivers/net/wireless/ath/ath6kl/hif.h
+--- linux-3.10.30.orig/drivers/net/wireless/ath/ath6kl/hif.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/ath/ath6kl/hif.h 2014-05-15 20:34:00.358030871 +0200
+@@ -197,9 +197,9 @@
+ /* bounce buffer for upper layers to copy to/from */
+ u8 *virt_dma_buf;
+
+- struct hif_scatter_item scat_list[1];
+-
+ u32 scat_q_depth;
++
++ struct hif_scatter_item scat_list[0];
+ };
+
+ struct ath6kl_irq_proc_registers {
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/ath/ath6kl/sdio.c linux-linaro-stable-mx6/drivers/net/wireless/ath/ath6kl/sdio.c
+--- linux-3.10.30.orig/drivers/net/wireless/ath/ath6kl/sdio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/ath/ath6kl/sdio.c 2014-05-15 20:34:00.362030900 +0200
+@@ -222,6 +222,7 @@
+ struct mmc_data *data)
+ {
+ struct scatterlist *sg;
++ struct hif_scatter_item *scat_list;
+ int i;
+
+ data->blksz = HIF_MBOX_BLOCK_SIZE;
+@@ -240,14 +241,14 @@
+ sg = scat_req->sgentries;
+ sg_init_table(sg, scat_req->scat_entries);
+
++ scat_list = &scat_req->scat_list[0];
++
+ /* assemble SG list */
+- for (i = 0; i < scat_req->scat_entries; i++, sg++) {
++ for (i = 0; i < scat_req->scat_entries; i++, sg++, scat_list++) {
+ ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n",
+- i, scat_req->scat_list[i].buf,
+- scat_req->scat_list[i].len);
++ i, scat_list->buf, scat_list->len);
+
+- sg_set_buf(sg, scat_req->scat_list[i].buf,
+- scat_req->scat_list[i].len);
++ sg_set_buf(sg, scat_list->buf, scat_list->len);
+ }
+
+ /* set scatter-gather table for request */
+@@ -348,7 +349,7 @@
+ int i, scat_req_sz, scat_list_sz, sg_sz, buf_sz;
+ u8 *virt_buf;
+
+- scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item);
++ scat_list_sz = n_scat_entry * sizeof(struct hif_scatter_item);
+ scat_req_sz = sizeof(*s_req) + scat_list_sz;
+
+ if (!virt_scat)
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/bcdc.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/bcdc.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/bcdc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/bcdc.c 2014-05-15 20:34:00.550032255 +0200
+@@ -0,0 +1,375 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++/*******************************************************************************
++ * Communicates with the dongle by using dcmd codes.
++ * For certain dcmd codes, the dongle interprets string data from the host.
++ ******************************************************************************/
++
++#include <linux/types.h>
++#include <linux/netdevice.h>
++
++#include <brcmu_utils.h>
++#include <brcmu_wifi.h>
++
++#include "dhd.h"
++#include "dhd_bus.h"
++#include "fwsignal.h"
++#include "dhd_dbg.h"
++#include "tracepoint.h"
++#include "proto.h"
++#include "bcdc.h"
++
++struct brcmf_proto_bcdc_dcmd {
++ __le32 cmd; /* dongle command value */
++ __le32 len; /* lower 16: output buflen;
++ * upper 16: input buflen (excludes header) */
++ __le32 flags; /* flag defns given below */
++ __le32 status; /* status code returned from the device */
++};
++
++/* BCDC flag definitions */
++#define BCDC_DCMD_ERROR 0x01 /* 1=cmd failed */
++#define BCDC_DCMD_SET 0x02 /* 0=get, 1=set cmd */
++#define BCDC_DCMD_IF_MASK 0xF000 /* I/F index */
++#define BCDC_DCMD_IF_SHIFT 12
++#define BCDC_DCMD_ID_MASK 0xFFFF0000 /* id an cmd pairing */
++#define BCDC_DCMD_ID_SHIFT 16 /* ID Mask shift bits */
++#define BCDC_DCMD_ID(flags) \
++ (((flags) & BCDC_DCMD_ID_MASK) >> BCDC_DCMD_ID_SHIFT)
++
++/*
++ * BCDC header - Broadcom specific extension of CDC.
++ * Used on data packets to convey priority across USB.
++ */
++#define BCDC_HEADER_LEN 4
++#define BCDC_PROTO_VER 2 /* Protocol version */
++#define BCDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */
++#define BCDC_FLAG_VER_SHIFT 4 /* Protocol version shift */
++#define BCDC_FLAG_SUM_GOOD 0x04 /* Good RX checksums */
++#define BCDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */
++#define BCDC_PRIORITY_MASK 0x7
++#define BCDC_FLAG2_IF_MASK 0x0f /* packet rx interface in APSTA */
++#define BCDC_FLAG2_IF_SHIFT 0
++
++#define BCDC_GET_IF_IDX(hdr) \
++ ((int)((((hdr)->flags2) & BCDC_FLAG2_IF_MASK) >> BCDC_FLAG2_IF_SHIFT))
++#define BCDC_SET_IF_IDX(hdr, idx) \
++ ((hdr)->flags2 = (((hdr)->flags2 & ~BCDC_FLAG2_IF_MASK) | \
++ ((idx) << BCDC_FLAG2_IF_SHIFT)))
++
++/**
++ * struct brcmf_proto_bcdc_header - BCDC header format
++ *
++ * @flags: flags contain protocol and checksum info.
++ * @priority: 802.1d priority and USB flow control info (bit 4:7).
++ * @flags2: additional flags containing dongle interface index.
++ * @data_offset: start of packet data. header is following by firmware signals.
++ */
++struct brcmf_proto_bcdc_header {
++ u8 flags;
++ u8 priority;
++ u8 flags2;
++ u8 data_offset;
++};
++
++/*
++ * maximum length of firmware signal data between
++ * the BCDC header and packet data in the tx path.
++ */
++#define BRCMF_PROT_FW_SIGNAL_MAX_TXBYTES 12
++
++#define RETRIES 2 /* # of retries to retrieve matching dcmd response */
++#define BUS_HEADER_LEN (16+64) /* Must be atleast SDPCM_RESERVE
++ * (amount of header tha might be added)
++ * plus any space that might be needed
++ * for bus alignment padding.
++ */
++struct brcmf_bcdc {
++ u16 reqid;
++ u8 bus_header[BUS_HEADER_LEN];
++ struct brcmf_proto_bcdc_dcmd msg;
++ unsigned char buf[BRCMF_DCMD_MAXLEN];
++};
++
++
++static int
++brcmf_proto_bcdc_msg(struct brcmf_pub *drvr, int ifidx, uint cmd, void *buf,
++ uint len, bool set)
++{
++ struct brcmf_bcdc *bcdc = (struct brcmf_bcdc *)drvr->proto->pd;
++ struct brcmf_proto_bcdc_dcmd *msg = &bcdc->msg;
++ u32 flags;
++
++ brcmf_dbg(BCDC, "Enter\n");
++
++ memset(msg, 0, sizeof(struct brcmf_proto_bcdc_dcmd));
++
++ msg->cmd = cpu_to_le32(cmd);
++ msg->len = cpu_to_le32(len);
++ flags = (++bcdc->reqid << BCDC_DCMD_ID_SHIFT);
++ if (set)
++ flags |= BCDC_DCMD_SET;
++ flags = (flags & ~BCDC_DCMD_IF_MASK) |
++ (ifidx << BCDC_DCMD_IF_SHIFT);
++ msg->flags = cpu_to_le32(flags);
++
++ if (buf)
++ memcpy(bcdc->buf, buf, len);
++
++ len += sizeof(*msg);
++ if (len > BRCMF_TX_IOCTL_MAX_MSG_SIZE)
++ len = BRCMF_TX_IOCTL_MAX_MSG_SIZE;
++
++ /* Send request */
++ return brcmf_bus_txctl(drvr->bus_if, (unsigned char *)&bcdc->msg, len);
++}
++
++static int brcmf_proto_bcdc_cmplt(struct brcmf_pub *drvr, u32 id, u32 len)
++{
++ int ret;
++ struct brcmf_bcdc *bcdc = (struct brcmf_bcdc *)drvr->proto->pd;
++
++ brcmf_dbg(BCDC, "Enter\n");
++ len += sizeof(struct brcmf_proto_bcdc_dcmd);
++ do {
++ ret = brcmf_bus_rxctl(drvr->bus_if, (unsigned char *)&bcdc->msg,
++ len);
++ if (ret < 0)
++ break;
++ } while (BCDC_DCMD_ID(le32_to_cpu(bcdc->msg.flags)) != id);
++
++ return ret;
++}
++
++static int
++brcmf_proto_bcdc_query_dcmd(struct brcmf_pub *drvr, int ifidx, uint cmd,
++ void *buf, uint len)
++{
++ struct brcmf_bcdc *bcdc = (struct brcmf_bcdc *)drvr->proto->pd;
++ struct brcmf_proto_bcdc_dcmd *msg = &bcdc->msg;
++ void *info;
++ int ret = 0, retries = 0;
++ u32 id, flags;
++
++ brcmf_dbg(BCDC, "Enter, cmd %d len %d\n", cmd, len);
++
++ ret = brcmf_proto_bcdc_msg(drvr, ifidx, cmd, buf, len, false);
++ if (ret < 0) {
++ brcmf_err("brcmf_proto_bcdc_msg failed w/status %d\n",
++ ret);
++ goto done;
++ }
++
++retry:
++ /* wait for interrupt and get first fragment */
++ ret = brcmf_proto_bcdc_cmplt(drvr, bcdc->reqid, len);
++ if (ret < 0)
++ goto done;
++
++ flags = le32_to_cpu(msg->flags);
++ id = (flags & BCDC_DCMD_ID_MASK) >> BCDC_DCMD_ID_SHIFT;
++
++ if ((id < bcdc->reqid) && (++retries < RETRIES))
++ goto retry;
++ if (id != bcdc->reqid) {
++ brcmf_err("%s: unexpected request id %d (expected %d)\n",
++ brcmf_ifname(drvr, ifidx), id, bcdc->reqid);
++ ret = -EINVAL;
++ goto done;
++ }
++
++ /* Check info buffer */
++ info = (void *)&msg[1];
++
++ /* Copy info buffer */
++ if (buf) {
++ if (ret < (int)len)
++ len = ret;
++ memcpy(buf, info, len);
++ }
++
++ /* Check the ERROR flag */
++ if (flags & BCDC_DCMD_ERROR)
++ ret = le32_to_cpu(msg->status);
++
++done:
++ return ret;
++}
++
++static int
++brcmf_proto_bcdc_set_dcmd(struct brcmf_pub *drvr, int ifidx, uint cmd,
++ void *buf, uint len)
++{
++ struct brcmf_bcdc *bcdc = (struct brcmf_bcdc *)drvr->proto->pd;
++ struct brcmf_proto_bcdc_dcmd *msg = &bcdc->msg;
++ int ret = 0;
++ u32 flags, id;
++
++ brcmf_dbg(BCDC, "Enter, cmd %d len %d\n", cmd, len);
++
++ ret = brcmf_proto_bcdc_msg(drvr, ifidx, cmd, buf, len, true);
++ if (ret < 0)
++ goto done;
++
++ ret = brcmf_proto_bcdc_cmplt(drvr, bcdc->reqid, len);
++ if (ret < 0)
++ goto done;
++
++ flags = le32_to_cpu(msg->flags);
++ id = (flags & BCDC_DCMD_ID_MASK) >> BCDC_DCMD_ID_SHIFT;
++
++ if (id != bcdc->reqid) {
++ brcmf_err("%s: unexpected request id %d (expected %d)\n",
++ brcmf_ifname(drvr, ifidx), id, bcdc->reqid);
++ ret = -EINVAL;
++ goto done;
++ }
++
++ /* Check the ERROR flag */
++ if (flags & BCDC_DCMD_ERROR)
++ ret = le32_to_cpu(msg->status);
++
++done:
++ return ret;
++}
++
++static void
++brcmf_proto_bcdc_hdrpush(struct brcmf_pub *drvr, int ifidx, u8 offset,
++ struct sk_buff *pktbuf)
++{
++ struct brcmf_proto_bcdc_header *h;
++
++ brcmf_dbg(BCDC, "Enter\n");
++
++ /* Push BDC header used to convey priority for buses that don't */
++ skb_push(pktbuf, BCDC_HEADER_LEN);
++
++ h = (struct brcmf_proto_bcdc_header *)(pktbuf->data);
++
++ h->flags = (BCDC_PROTO_VER << BCDC_FLAG_VER_SHIFT);
++ if (pktbuf->ip_summed == CHECKSUM_PARTIAL)
++ h->flags |= BCDC_FLAG_SUM_NEEDED;
++
++ h->priority = (pktbuf->priority & BCDC_PRIORITY_MASK);
++ h->flags2 = 0;
++ h->data_offset = offset;
++ BCDC_SET_IF_IDX(h, ifidx);
++ trace_brcmf_bcdchdr(pktbuf->data);
++}
++
++static int
++brcmf_proto_bcdc_hdrpull(struct brcmf_pub *drvr, bool do_fws, u8 *ifidx,
++ struct sk_buff *pktbuf)
++{
++ struct brcmf_proto_bcdc_header *h;
++
++ brcmf_dbg(BCDC, "Enter\n");
++
++ /* Pop BCDC header used to convey priority for buses that don't */
++ if (pktbuf->len <= BCDC_HEADER_LEN) {
++ brcmf_dbg(INFO, "rx data too short (%d <= %d)\n",
++ pktbuf->len, BCDC_HEADER_LEN);
++ return -EBADE;
++ }
++
++ trace_brcmf_bcdchdr(pktbuf->data);
++ h = (struct brcmf_proto_bcdc_header *)(pktbuf->data);
++
++ *ifidx = BCDC_GET_IF_IDX(h);
++ if (*ifidx >= BRCMF_MAX_IFS) {
++ brcmf_err("rx data ifnum out of range (%d)\n", *ifidx);
++ return -EBADE;
++ }
++ /* The ifidx is the idx to map to matching netdev/ifp. When receiving
++ * events this is easy because it contains the bssidx which maps
++ * 1-on-1 to the netdev/ifp. But for data frames the ifidx is rcvd.
++ * bssidx 1 is used for p2p0 and no data can be received or
++ * transmitted on it. Therefor bssidx is ifidx + 1 if ifidx > 0
++ */
++ if (*ifidx)
++ (*ifidx)++;
++
++ if (((h->flags & BCDC_FLAG_VER_MASK) >> BCDC_FLAG_VER_SHIFT) !=
++ BCDC_PROTO_VER) {
++ brcmf_err("%s: non-BCDC packet received, flags 0x%x\n",
++ brcmf_ifname(drvr, *ifidx), h->flags);
++ return -EBADE;
++ }
++
++ if (h->flags & BCDC_FLAG_SUM_GOOD) {
++ brcmf_dbg(BCDC, "%s: BDC rcv, good checksum, flags 0x%x\n",
++ brcmf_ifname(drvr, *ifidx), h->flags);
++ pktbuf->ip_summed = CHECKSUM_UNNECESSARY;
++ }
++
++ pktbuf->priority = h->priority & BCDC_PRIORITY_MASK;
++
++ skb_pull(pktbuf, BCDC_HEADER_LEN);
++ if (do_fws)
++ brcmf_fws_hdrpull(drvr, *ifidx, h->data_offset << 2, pktbuf);
++ else
++ skb_pull(pktbuf, h->data_offset << 2);
++
++ if (pktbuf->len == 0)
++ return -ENODATA;
++ return 0;
++}
++
++static int
++brcmf_proto_bcdc_txdata(struct brcmf_pub *drvr, int ifidx, u8 offset,
++ struct sk_buff *pktbuf)
++{
++ brcmf_proto_bcdc_hdrpush(drvr, ifidx, offset, pktbuf);
++ return brcmf_bus_txdata(drvr->bus_if, pktbuf);
++}
++
++
++int brcmf_proto_bcdc_attach(struct brcmf_pub *drvr)
++{
++ struct brcmf_bcdc *bcdc;
++
++ bcdc = kzalloc(sizeof(*bcdc), GFP_ATOMIC);
++ if (!bcdc)
++ goto fail;
++
++ /* ensure that the msg buf directly follows the cdc msg struct */
++ if ((unsigned long)(&bcdc->msg + 1) != (unsigned long)bcdc->buf) {
++ brcmf_err("struct brcmf_proto_bcdc is not correctly defined\n");
++ goto fail;
++ }
++
++ drvr->proto->hdrpull = brcmf_proto_bcdc_hdrpull;
++ drvr->proto->query_dcmd = brcmf_proto_bcdc_query_dcmd;
++ drvr->proto->set_dcmd = brcmf_proto_bcdc_set_dcmd;
++ drvr->proto->txdata = brcmf_proto_bcdc_txdata;
++ drvr->proto->pd = bcdc;
++
++ drvr->hdrlen += BCDC_HEADER_LEN + BRCMF_PROT_FW_SIGNAL_MAX_TXBYTES;
++ drvr->bus_if->maxctl = BRCMF_DCMD_MAXLEN +
++ sizeof(struct brcmf_proto_bcdc_dcmd);
++ return 0;
++
++fail:
++ kfree(bcdc);
++ return -ENOMEM;
++}
++
++void brcmf_proto_bcdc_detach(struct brcmf_pub *drvr)
++{
++ kfree(drvr->proto->pd);
++ drvr->proto->pd = NULL;
++}
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/bcdc.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/bcdc.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/bcdc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/bcdc.h 2014-05-15 20:34:00.554032284 +0200
+@@ -0,0 +1,24 @@
++/*
++ * Copyright (c) 2013 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_BCDC_H
++#define BRCMFMAC_BCDC_H
++
++
++int brcmf_proto_bcdc_attach(struct brcmf_pub *drvr);
++void brcmf_proto_bcdc_detach(struct brcmf_pub *drvr);
++
++
++#endif /* BRCMFMAC_BCDC_H */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c 2014-05-15 20:34:00.554032284 +0200
+@@ -17,15 +17,23 @@
+
+ #include <linux/types.h>
+ #include <linux/netdevice.h>
+-#include <linux/export.h>
+ #include <linux/pci.h>
+ #include <linux/pci_ids.h>
+ #include <linux/sched.h>
+ #include <linux/completion.h>
++#include <linux/scatterlist.h>
+ #include <linux/mmc/sdio.h>
++#include <linux/mmc/core.h>
+ #include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
+ #include <linux/mmc/card.h>
++#include <linux/mmc/host.h>
++#include <linux/platform_device.h>
+ #include <linux/platform_data/brcmfmac-sdio.h>
++#include <linux/suspend.h>
++#include <linux/errno.h>
++#include <linux/module.h>
++#include <net/cfg80211.h>
+
+ #include <defs.h>
+ #include <brcm_hw_ids.h>
+@@ -35,11 +43,19 @@
+ #include "dhd_bus.h"
+ #include "dhd_dbg.h"
+ #include "sdio_host.h"
++#include "sdio_chip.h"
+
+ #define SDIOH_API_ACCESS_RETRY_LIMIT 2
+
++#define DMA_ALIGN_MASK 0x03
+
+-static irqreturn_t brcmf_sdio_oob_irqhandler(int irq, void *dev_id)
++#define SDIO_FUNC1_BLOCKSIZE 64
++#define SDIO_FUNC2_BLOCKSIZE 512
++/* Maximum milliseconds to wait for F2 to come up */
++#define SDIO_WAIT_F2RDY 3000
++
++
++static irqreturn_t brcmf_sdiod_oob_irqhandler(int irq, void *dev_id)
+ {
+ struct brcmf_bus *bus_if = dev_get_drvdata(dev_id);
+ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+@@ -54,27 +70,46 @@
+ sdiodev->irq_en = false;
+ }
+
+- brcmf_sdbrcm_isr(sdiodev->bus);
++ brcmf_sdio_isr(sdiodev->bus);
+
+ return IRQ_HANDLED;
+ }
+
+-static void brcmf_sdio_ib_irqhandler(struct sdio_func *func)
++static void brcmf_sdiod_ib_irqhandler(struct sdio_func *func)
+ {
+ struct brcmf_bus *bus_if = dev_get_drvdata(&func->dev);
+ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+
+ brcmf_dbg(INTR, "IB intr triggered\n");
+
+- brcmf_sdbrcm_isr(sdiodev->bus);
++ brcmf_sdio_isr(sdiodev->bus);
+ }
+
+ /* dummy handler for SDIO function 2 interrupt */
+-static void brcmf_sdio_dummy_irqhandler(struct sdio_func *func)
++static void brcmf_sdiod_dummy_irqhandler(struct sdio_func *func)
++{
++}
++
++static bool brcmf_sdiod_pm_resume_error(struct brcmf_sdio_dev *sdiodev)
+ {
++ bool is_err = false;
++#ifdef CONFIG_PM_SLEEP
++ is_err = atomic_read(&sdiodev->suspend);
++#endif
++ return is_err;
+ }
+
+-int brcmf_sdio_intr_register(struct brcmf_sdio_dev *sdiodev)
++static void brcmf_sdiod_pm_resume_wait(struct brcmf_sdio_dev *sdiodev,
++ wait_queue_head_t *wq)
++{
++#ifdef CONFIG_PM_SLEEP
++ int retry = 0;
++ while (atomic_read(&sdiodev->suspend) && retry++ != 30)
++ wait_event_timeout(*wq, false, HZ/100);
++#endif
++}
++
++int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev)
+ {
+ int ret = 0;
+ u8 data;
+@@ -84,7 +119,7 @@
+ brcmf_dbg(SDIO, "Enter, register OOB IRQ %d\n",
+ sdiodev->pdata->oob_irq_nr);
+ ret = request_irq(sdiodev->pdata->oob_irq_nr,
+- brcmf_sdio_oob_irqhandler,
++ brcmf_sdiod_oob_irqhandler,
+ sdiodev->pdata->oob_irq_flags,
+ "brcmf_oob_intr",
+ &sdiodev->func[1]->dev);
+@@ -108,36 +143,36 @@
+ sdio_claim_host(sdiodev->func[1]);
+
+ /* must configure SDIO_CCCR_IENx to enable irq */
+- data = brcmf_sdio_regrb(sdiodev, SDIO_CCCR_IENx, &ret);
++ data = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_IENx, &ret);
+ data |= 1 << SDIO_FUNC_1 | 1 << SDIO_FUNC_2 | 1;
+- brcmf_sdio_regwb(sdiodev, SDIO_CCCR_IENx, data, &ret);
++ brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_IENx, data, &ret);
+
+ /* redirect, configure and enable io for interrupt signal */
+ data = SDIO_SEPINT_MASK | SDIO_SEPINT_OE;
+ if (sdiodev->pdata->oob_irq_flags & IRQF_TRIGGER_HIGH)
+ data |= SDIO_SEPINT_ACT_HI;
+- brcmf_sdio_regwb(sdiodev, SDIO_CCCR_BRCM_SEPINT, data, &ret);
++ brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_SEPINT, data, &ret);
+
+ sdio_release_host(sdiodev->func[1]);
+ } else {
+ brcmf_dbg(SDIO, "Entering\n");
+ sdio_claim_host(sdiodev->func[1]);
+- sdio_claim_irq(sdiodev->func[1], brcmf_sdio_ib_irqhandler);
+- sdio_claim_irq(sdiodev->func[2], brcmf_sdio_dummy_irqhandler);
++ sdio_claim_irq(sdiodev->func[1], brcmf_sdiod_ib_irqhandler);
++ sdio_claim_irq(sdiodev->func[2], brcmf_sdiod_dummy_irqhandler);
+ sdio_release_host(sdiodev->func[1]);
+ }
+
+ return 0;
+ }
+
+-int brcmf_sdio_intr_unregister(struct brcmf_sdio_dev *sdiodev)
++int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev)
+ {
+ brcmf_dbg(SDIO, "Entering\n");
+
+ if ((sdiodev->pdata) && (sdiodev->pdata->oob_irq_supported)) {
+ sdio_claim_host(sdiodev->func[1]);
+- brcmf_sdio_regwb(sdiodev, SDIO_CCCR_BRCM_SEPINT, 0, NULL);
+- brcmf_sdio_regwb(sdiodev, SDIO_CCCR_IENx, 0, NULL);
++ brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_SEPINT, 0, NULL);
++ brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_IENx, 0, NULL);
+ sdio_release_host(sdiodev->func[1]);
+
+ if (sdiodev->oob_irq_requested) {
+@@ -160,102 +195,188 @@
+ return 0;
+ }
+
+-int
+-brcmf_sdcard_set_sbaddr_window(struct brcmf_sdio_dev *sdiodev, u32 address)
++static inline int brcmf_sdiod_f0_writeb(struct sdio_func *func,
++ uint regaddr, u8 byte)
+ {
+- int err = 0, i;
+- u8 addr[3];
+- s32 retry;
++ int err_ret;
+
+- addr[0] = (address >> 8) & SBSDIO_SBADDRLOW_MASK;
+- addr[1] = (address >> 16) & SBSDIO_SBADDRMID_MASK;
+- addr[2] = (address >> 24) & SBSDIO_SBADDRHIGH_MASK;
++ /*
++ * Can only directly write to some F0 registers.
++ * Handle CCCR_IENx and CCCR_ABORT command
++ * as a special case.
++ */
++ if ((regaddr == SDIO_CCCR_ABORT) ||
++ (regaddr == SDIO_CCCR_IENx))
++ sdio_writeb(func, byte, regaddr, &err_ret);
++ else
++ sdio_f0_writeb(func, byte, regaddr, &err_ret);
+
+- for (i = 0; i < 3; i++) {
+- retry = 0;
+- do {
+- if (retry)
+- usleep_range(1000, 2000);
+- err = brcmf_sdioh_request_byte(sdiodev, SDIOH_WRITE,
+- SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW + i,
+- &addr[i]);
+- } while (err != 0 && retry++ < SDIOH_API_ACCESS_RETRY_LIMIT);
++ return err_ret;
++}
+
+- if (err) {
+- brcmf_err("failed at addr:0x%0x\n",
+- SBSDIO_FUNC1_SBADDRLOW + i);
+- break;
++static int brcmf_sdiod_request_data(struct brcmf_sdio_dev *sdiodev, u8 fn,
++ u32 addr, u8 regsz, void *data, bool write)
++{
++ struct sdio_func *func;
++ int ret;
++
++ brcmf_dbg(SDIO, "rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
++ write, fn, addr, regsz);
++
++ brcmf_sdiod_pm_resume_wait(sdiodev, &sdiodev->request_word_wait);
++ if (brcmf_sdiod_pm_resume_error(sdiodev))
++ return -EIO;
++
++ /* only allow byte access on F0 */
++ if (WARN_ON(regsz > 1 && !fn))
++ return -EINVAL;
++ func = sdiodev->func[fn];
++
++ switch (regsz) {
++ case sizeof(u8):
++ if (write) {
++ if (fn)
++ sdio_writeb(func, *(u8 *)data, addr, &ret);
++ else
++ ret = brcmf_sdiod_f0_writeb(func, addr,
++ *(u8 *)data);
++ } else {
++ if (fn)
++ *(u8 *)data = sdio_readb(func, addr, &ret);
++ else
++ *(u8 *)data = sdio_f0_readb(func, addr, &ret);
+ }
++ break;
++ case sizeof(u16):
++ if (write)
++ sdio_writew(func, *(u16 *)data, addr, &ret);
++ else
++ *(u16 *)data = sdio_readw(func, addr, &ret);
++ break;
++ case sizeof(u32):
++ if (write)
++ sdio_writel(func, *(u32 *)data, addr, &ret);
++ else
++ *(u32 *)data = sdio_readl(func, addr, &ret);
++ break;
++ default:
++ brcmf_err("invalid size: %d\n", regsz);
++ break;
+ }
+
+- return err;
++ if (ret) {
++ /*
++ * SleepCSR register access can fail when
++ * waking up the device so reduce this noise
++ * in the logs.
++ */
++ if (addr != SBSDIO_FUNC1_SLEEPCSR)
++ brcmf_err("failed to %s data F%d@0x%05x, err: %d\n",
++ write ? "write" : "read", fn, addr, ret);
++ else
++ brcmf_dbg(SDIO, "failed to %s data F%d@0x%05x, err: %d\n",
++ write ? "write" : "read", fn, addr, ret);
++ }
++ return ret;
+ }
+
+-int
+-brcmf_sdio_regrw_helper(struct brcmf_sdio_dev *sdiodev, u32 addr,
+- void *data, bool write)
++static int brcmf_sdiod_regrw_helper(struct brcmf_sdio_dev *sdiodev, u32 addr,
++ u8 regsz, void *data, bool write)
+ {
+- u8 func_num, reg_size;
+- u32 bar;
++ u8 func_num;
+ s32 retry = 0;
+ int ret;
+
++ if (sdiodev->bus_if->state == BRCMF_BUS_NOMEDIUM)
++ return -ENOMEDIUM;
++
+ /*
+ * figure out how to read the register based on address range
+ * 0x00 ~ 0x7FF: function 0 CCCR and FBR
+ * 0x10000 ~ 0x1FFFF: function 1 miscellaneous registers
+ * The rest: function 1 silicon backplane core registers
+ */
+- if ((addr & ~REG_F0_REG_MASK) == 0) {
++ if ((addr & ~REG_F0_REG_MASK) == 0)
+ func_num = SDIO_FUNC_0;
+- reg_size = 1;
+- } else if ((addr & ~REG_F1_MISC_MASK) == 0) {
+- func_num = SDIO_FUNC_1;
+- reg_size = 1;
+- } else {
++ else
+ func_num = SDIO_FUNC_1;
+- reg_size = 4;
+-
+- /* Set the window for SB core register */
+- bar = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
+- if (bar != sdiodev->sbwad) {
+- ret = brcmf_sdcard_set_sbaddr_window(sdiodev, bar);
+- if (ret != 0) {
+- memset(data, 0xFF, reg_size);
+- return ret;
+- }
+- sdiodev->sbwad = bar;
+- }
+- addr &= SBSDIO_SB_OFT_ADDR_MASK;
+- addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
+- }
+
+ do {
+ if (!write)
+- memset(data, 0, reg_size);
+- if (retry) /* wait for 1 ms till bus get settled down */
++ memset(data, 0, regsz);
++ /* for retry wait for 1 ms till bus get settled down */
++ if (retry)
+ usleep_range(1000, 2000);
+- if (reg_size == 1)
+- ret = brcmf_sdioh_request_byte(sdiodev, write,
+- func_num, addr, data);
+- else
+- ret = brcmf_sdioh_request_word(sdiodev, write,
+- func_num, addr, data, 4);
+- } while (ret != 0 && retry++ < SDIOH_API_ACCESS_RETRY_LIMIT);
+-
+- if (ret != 0)
++ ret = brcmf_sdiod_request_data(sdiodev, func_num, addr, regsz,
++ data, write);
++ } while (ret != 0 && ret != -ENOMEDIUM &&
++ retry++ < SDIOH_API_ACCESS_RETRY_LIMIT);
++
++ if (ret == -ENOMEDIUM)
++ brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_NOMEDIUM);
++ else if (ret != 0)
+ brcmf_err("failed with %d\n", ret);
+
+ return ret;
+ }
+
+-u8 brcmf_sdio_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
++static int
++brcmf_sdiod_set_sbaddr_window(struct brcmf_sdio_dev *sdiodev, u32 address)
++{
++ int err = 0, i;
++ u8 addr[3];
++
++ if (sdiodev->bus_if->state == BRCMF_BUS_NOMEDIUM)
++ return -ENOMEDIUM;
++
++ addr[0] = (address >> 8) & SBSDIO_SBADDRLOW_MASK;
++ addr[1] = (address >> 16) & SBSDIO_SBADDRMID_MASK;
++ addr[2] = (address >> 24) & SBSDIO_SBADDRHIGH_MASK;
++
++ for (i = 0; i < 3; i++) {
++ err = brcmf_sdiod_regrw_helper(sdiodev,
++ SBSDIO_FUNC1_SBADDRLOW + i,
++ sizeof(u8), &addr[i], true);
++ if (err) {
++ brcmf_err("failed at addr: 0x%0x\n",
++ SBSDIO_FUNC1_SBADDRLOW + i);
++ break;
++ }
++ }
++
++ return err;
++}
++
++static int
++brcmf_sdiod_addrprep(struct brcmf_sdio_dev *sdiodev, uint width, u32 *addr)
++{
++ uint bar0 = *addr & ~SBSDIO_SB_OFT_ADDR_MASK;
++ int err = 0;
++
++ if (bar0 != sdiodev->sbwad) {
++ err = brcmf_sdiod_set_sbaddr_window(sdiodev, bar0);
++ if (err)
++ return err;
++
++ sdiodev->sbwad = bar0;
++ }
++
++ *addr &= SBSDIO_SB_OFT_ADDR_MASK;
++
++ if (width == 4)
++ *addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++
++ return 0;
++}
++
++u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
+ {
+ u8 data;
+ int retval;
+
+ brcmf_dbg(SDIO, "addr:0x%08x\n", addr);
+- retval = brcmf_sdio_regrw_helper(sdiodev, addr, &data, false);
++ retval = brcmf_sdiod_regrw_helper(sdiodev, addr, sizeof(data), &data,
++ false);
+ brcmf_dbg(SDIO, "data:0x%02x\n", data);
+
+ if (ret)
+@@ -264,74 +385,269 @@
+ return data;
+ }
+
+-u32 brcmf_sdio_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
++u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret)
+ {
+ u32 data;
+ int retval;
+
+ brcmf_dbg(SDIO, "addr:0x%08x\n", addr);
+- retval = brcmf_sdio_regrw_helper(sdiodev, addr, &data, false);
++ retval = brcmf_sdiod_addrprep(sdiodev, sizeof(data), &addr);
++ if (retval)
++ goto done;
++ retval = brcmf_sdiod_regrw_helper(sdiodev, addr, sizeof(data), &data,
++ false);
+ brcmf_dbg(SDIO, "data:0x%08x\n", data);
+
++done:
+ if (ret)
+ *ret = retval;
+
+ return data;
+ }
+
+-void brcmf_sdio_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr,
++void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr,
+ u8 data, int *ret)
+ {
+ int retval;
+
+ brcmf_dbg(SDIO, "addr:0x%08x, data:0x%02x\n", addr, data);
+- retval = brcmf_sdio_regrw_helper(sdiodev, addr, &data, true);
+-
++ retval = brcmf_sdiod_regrw_helper(sdiodev, addr, sizeof(data), &data,
++ true);
+ if (ret)
+ *ret = retval;
+ }
+
+-void brcmf_sdio_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr,
++void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr,
+ u32 data, int *ret)
+ {
+ int retval;
+
+ brcmf_dbg(SDIO, "addr:0x%08x, data:0x%08x\n", addr, data);
+- retval = brcmf_sdio_regrw_helper(sdiodev, addr, &data, true);
++ retval = brcmf_sdiod_addrprep(sdiodev, sizeof(data), &addr);
++ if (retval)
++ goto done;
++ retval = brcmf_sdiod_regrw_helper(sdiodev, addr, sizeof(data), &data,
++ true);
+
++done:
+ if (ret)
+ *ret = retval;
+ }
+
+-static int brcmf_sdcard_recv_prepare(struct brcmf_sdio_dev *sdiodev, uint fn,
+- uint flags, uint width, u32 *addr)
++static int brcmf_sdiod_buffrw(struct brcmf_sdio_dev *sdiodev, uint fn,
++ bool write, u32 addr, struct sk_buff *pkt)
+ {
+- uint bar0 = *addr & ~SBSDIO_SB_OFT_ADDR_MASK;
+- int err = 0;
++ unsigned int req_sz;
++ int err;
+
+- /* Async not implemented yet */
+- if (flags & SDIO_REQ_ASYNC)
+- return -ENOTSUPP;
++ brcmf_sdiod_pm_resume_wait(sdiodev, &sdiodev->request_buffer_wait);
++ if (brcmf_sdiod_pm_resume_error(sdiodev))
++ return -EIO;
+
+- if (bar0 != sdiodev->sbwad) {
+- err = brcmf_sdcard_set_sbaddr_window(sdiodev, bar0);
+- if (err)
+- return err;
++ /* Single skb use the standard mmc interface */
++ req_sz = pkt->len + 3;
++ req_sz &= (uint)~3;
++
++ if (write)
++ err = sdio_memcpy_toio(sdiodev->func[fn], addr,
++ ((u8 *)(pkt->data)), req_sz);
++ else if (fn == 1)
++ err = sdio_memcpy_fromio(sdiodev->func[fn], ((u8 *)(pkt->data)),
++ addr, req_sz);
++ else
++ /* function 2 read is FIFO operation */
++ err = sdio_readsb(sdiodev->func[fn], ((u8 *)(pkt->data)), addr,
++ req_sz);
++ if (err == -ENOMEDIUM)
++ brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_NOMEDIUM);
++ return err;
++}
+
+- sdiodev->sbwad = bar0;
++/**
++ * brcmf_sdiod_sglist_rw - SDIO interface function for block data access
++ * @sdiodev: brcmfmac sdio device
++ * @fn: SDIO function number
++ * @write: direction flag
++ * @addr: dongle memory address as source/destination
++ * @pkt: skb pointer
++ *
++ * This function takes the respbonsibility as the interface function to MMC
++ * stack for block data access. It assumes that the skb passed down by the
++ * caller has already been padded and aligned.
++ */
++static int brcmf_sdiod_sglist_rw(struct brcmf_sdio_dev *sdiodev, uint fn,
++ bool write, u32 addr,
++ struct sk_buff_head *pktlist)
++{
++ unsigned int req_sz, func_blk_sz, sg_cnt, sg_data_sz, pkt_offset;
++ unsigned int max_req_sz, orig_offset, dst_offset;
++ unsigned short max_seg_cnt, seg_sz;
++ unsigned char *pkt_data, *orig_data, *dst_data;
++ struct sk_buff *pkt_next = NULL, *local_pkt_next;
++ struct sk_buff_head local_list, *target_list;
++ struct mmc_request mmc_req;
++ struct mmc_command mmc_cmd;
++ struct mmc_data mmc_dat;
++ struct sg_table st;
++ struct scatterlist *sgl;
++ int ret = 0;
++
++ if (!pktlist->qlen)
++ return -EINVAL;
++
++ brcmf_sdiod_pm_resume_wait(sdiodev, &sdiodev->request_buffer_wait);
++ if (brcmf_sdiod_pm_resume_error(sdiodev))
++ return -EIO;
++
++ target_list = pktlist;
++ /* for host with broken sg support, prepare a page aligned list */
++ __skb_queue_head_init(&local_list);
++ if (sdiodev->pdata && sdiodev->pdata->broken_sg_support && !write) {
++ req_sz = 0;
++ skb_queue_walk(pktlist, pkt_next)
++ req_sz += pkt_next->len;
++ req_sz = ALIGN(req_sz, sdiodev->func[fn]->cur_blksize);
++ while (req_sz > PAGE_SIZE) {
++ pkt_next = brcmu_pkt_buf_get_skb(PAGE_SIZE);
++ if (pkt_next == NULL) {
++ ret = -ENOMEM;
++ goto exit;
++ }
++ __skb_queue_tail(&local_list, pkt_next);
++ req_sz -= PAGE_SIZE;
++ }
++ pkt_next = brcmu_pkt_buf_get_skb(req_sz);
++ if (pkt_next == NULL) {
++ ret = -ENOMEM;
++ goto exit;
++ }
++ __skb_queue_tail(&local_list, pkt_next);
++ target_list = &local_list;
+ }
+
+- *addr &= SBSDIO_SB_OFT_ADDR_MASK;
++ func_blk_sz = sdiodev->func[fn]->cur_blksize;
++ max_req_sz = sdiodev->max_request_size;
++ max_seg_cnt = min_t(unsigned short, sdiodev->max_segment_count,
++ target_list->qlen);
++ seg_sz = target_list->qlen;
++ pkt_offset = 0;
++ pkt_next = target_list->next;
++
++ if (sg_alloc_table(&st, max_seg_cnt, GFP_KERNEL)) {
++ ret = -ENOMEM;
++ goto exit;
++ }
+
+- if (width == 4)
+- *addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++ memset(&mmc_req, 0, sizeof(struct mmc_request));
++ memset(&mmc_cmd, 0, sizeof(struct mmc_command));
++ memset(&mmc_dat, 0, sizeof(struct mmc_data));
++
++ mmc_dat.sg = st.sgl;
++ mmc_dat.blksz = func_blk_sz;
++ mmc_dat.flags = write ? MMC_DATA_WRITE : MMC_DATA_READ;
++ mmc_cmd.opcode = SD_IO_RW_EXTENDED;
++ mmc_cmd.arg = write ? 1<<31 : 0; /* write flag */
++ mmc_cmd.arg |= (fn & 0x7) << 28; /* SDIO func num */
++ mmc_cmd.arg |= 1<<27; /* block mode */
++ /* for function 1 the addr will be incremented */
++ mmc_cmd.arg |= (fn == 1) ? 1<<26 : 0;
++ mmc_cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
++ mmc_req.cmd = &mmc_cmd;
++ mmc_req.data = &mmc_dat;
++
++ while (seg_sz) {
++ req_sz = 0;
++ sg_cnt = 0;
++ sgl = st.sgl;
++ /* prep sg table */
++ while (pkt_next != (struct sk_buff *)target_list) {
++ pkt_data = pkt_next->data + pkt_offset;
++ sg_data_sz = pkt_next->len - pkt_offset;
++ if (sg_data_sz > sdiodev->max_segment_size)
++ sg_data_sz = sdiodev->max_segment_size;
++ if (sg_data_sz > max_req_sz - req_sz)
++ sg_data_sz = max_req_sz - req_sz;
++
++ sg_set_buf(sgl, pkt_data, sg_data_sz);
++
++ sg_cnt++;
++ sgl = sg_next(sgl);
++ req_sz += sg_data_sz;
++ pkt_offset += sg_data_sz;
++ if (pkt_offset == pkt_next->len) {
++ pkt_offset = 0;
++ pkt_next = pkt_next->next;
++ }
+
+- return 0;
++ if (req_sz >= max_req_sz || sg_cnt >= max_seg_cnt)
++ break;
++ }
++ seg_sz -= sg_cnt;
++
++ if (req_sz % func_blk_sz != 0) {
++ brcmf_err("sg request length %u is not %u aligned\n",
++ req_sz, func_blk_sz);
++ ret = -ENOTBLK;
++ goto exit;
++ }
++
++ mmc_dat.sg_len = sg_cnt;
++ mmc_dat.blocks = req_sz / func_blk_sz;
++ mmc_cmd.arg |= (addr & 0x1FFFF) << 9; /* address */
++ mmc_cmd.arg |= mmc_dat.blocks & 0x1FF; /* block count */
++ /* incrementing addr for function 1 */
++ if (fn == 1)
++ addr += req_sz;
++
++ mmc_set_data_timeout(&mmc_dat, sdiodev->func[fn]->card);
++ mmc_wait_for_req(sdiodev->func[fn]->card->host, &mmc_req);
++
++ ret = mmc_cmd.error ? mmc_cmd.error : mmc_dat.error;
++ if (ret == -ENOMEDIUM) {
++ brcmf_bus_change_state(sdiodev->bus_if,
++ BRCMF_BUS_NOMEDIUM);
++ break;
++ } else if (ret != 0) {
++ brcmf_err("CMD53 sg block %s failed %d\n",
++ write ? "write" : "read", ret);
++ ret = -EIO;
++ break;
++ }
++ }
++
++ if (sdiodev->pdata && sdiodev->pdata->broken_sg_support && !write) {
++ local_pkt_next = local_list.next;
++ orig_offset = 0;
++ skb_queue_walk(pktlist, pkt_next) {
++ dst_offset = 0;
++ do {
++ req_sz = local_pkt_next->len - orig_offset;
++ req_sz = min_t(uint, pkt_next->len - dst_offset,
++ req_sz);
++ orig_data = local_pkt_next->data + orig_offset;
++ dst_data = pkt_next->data + dst_offset;
++ memcpy(dst_data, orig_data, req_sz);
++ orig_offset += req_sz;
++ dst_offset += req_sz;
++ if (orig_offset == local_pkt_next->len) {
++ orig_offset = 0;
++ local_pkt_next = local_pkt_next->next;
++ }
++ if (dst_offset == pkt_next->len)
++ break;
++ } while (!skb_queue_empty(&local_list));
++ }
++ }
++
++exit:
++ sg_free_table(&st);
++ while ((pkt_next = __skb_dequeue(&local_list)) != NULL)
++ brcmu_pkt_buf_free_skb(pkt_next);
++
++ return ret;
+ }
+
+-int
+-brcmf_sdcard_recv_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, u8 *buf, uint nbytes)
++int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes)
+ {
+ struct sk_buff *mypkt;
+ int err;
+@@ -343,7 +659,7 @@
+ return -EIO;
+ }
+
+- err = brcmf_sdcard_recv_pkt(sdiodev, addr, fn, flags, mypkt);
++ err = brcmf_sdiod_recv_pkt(sdiodev, mypkt);
+ if (!err)
+ memcpy(buf, mypkt->data, nbytes);
+
+@@ -351,58 +667,66 @@
+ return err;
+ }
+
+-int
+-brcmf_sdcard_recv_pkt(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, struct sk_buff *pkt)
++int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt)
+ {
+- uint incr_fix;
+- uint width;
++ u32 addr = sdiodev->sbwad;
+ int err = 0;
+
+- brcmf_dbg(SDIO, "fun = %d, addr = 0x%x, size = %d\n",
+- fn, addr, pkt->len);
++ brcmf_dbg(SDIO, "addr = 0x%x, size = %d\n", addr, pkt->len);
+
+- width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
+- err = brcmf_sdcard_recv_prepare(sdiodev, fn, flags, width, &addr);
++ err = brcmf_sdiod_addrprep(sdiodev, 4, &addr);
+ if (err)
+ goto done;
+
+- incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
+- err = brcmf_sdioh_request_buffer(sdiodev, incr_fix, SDIOH_READ,
+- fn, addr, pkt);
++ err = brcmf_sdiod_buffrw(sdiodev, SDIO_FUNC_2, false, addr, pkt);
+
+ done:
+ return err;
+ }
+
+-int brcmf_sdcard_recv_chain(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, struct sk_buff_head *pktq)
++int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
++ struct sk_buff_head *pktq, uint totlen)
+ {
+- uint incr_fix;
+- uint width;
++ struct sk_buff *glom_skb;
++ struct sk_buff *skb;
++ u32 addr = sdiodev->sbwad;
+ int err = 0;
+
+- brcmf_dbg(SDIO, "fun = %d, addr = 0x%x, size = %d\n",
+- fn, addr, pktq->qlen);
++ brcmf_dbg(SDIO, "addr = 0x%x, size = %d\n",
++ addr, pktq->qlen);
+
+- width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
+- err = brcmf_sdcard_recv_prepare(sdiodev, fn, flags, width, &addr);
++ err = brcmf_sdiod_addrprep(sdiodev, 4, &addr);
+ if (err)
+ goto done;
+
+- incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
+- err = brcmf_sdioh_request_chain(sdiodev, incr_fix, SDIOH_READ, fn, addr,
+- pktq);
++ if (pktq->qlen == 1)
++ err = brcmf_sdiod_buffrw(sdiodev, SDIO_FUNC_2, false, addr,
++ pktq->next);
++ else if (!sdiodev->sg_support) {
++ glom_skb = brcmu_pkt_buf_get_skb(totlen);
++ if (!glom_skb)
++ return -ENOMEM;
++ err = brcmf_sdiod_buffrw(sdiodev, SDIO_FUNC_2, false, addr,
++ glom_skb);
++ if (err)
++ goto done;
++
++ skb_queue_walk(pktq, skb) {
++ memcpy(skb->data, glom_skb->data, skb->len);
++ skb_pull(glom_skb, skb->len);
++ }
++ } else
++ err = brcmf_sdiod_sglist_rw(sdiodev, SDIO_FUNC_2, false, addr,
++ pktq);
+
+ done:
+ return err;
+ }
+
+-int
+-brcmf_sdcard_send_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, u8 *buf, uint nbytes)
++int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes)
+ {
+ struct sk_buff *mypkt;
++ u32 addr = sdiodev->sbwad;
+ int err;
+
+ mypkt = brcmu_pkt_buf_get_skb(nbytes);
+@@ -413,54 +737,48 @@
+ }
+
+ memcpy(mypkt->data, buf, nbytes);
+- err = brcmf_sdcard_send_pkt(sdiodev, addr, fn, flags, mypkt);
++
++ err = brcmf_sdiod_addrprep(sdiodev, 4, &addr);
++
++ if (!err)
++ err = brcmf_sdiod_buffrw(sdiodev, SDIO_FUNC_2, true, addr,
++ mypkt);
+
+ brcmu_pkt_buf_free_skb(mypkt);
+ return err;
+
+ }
+
+-int
+-brcmf_sdcard_send_pkt(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, struct sk_buff *pkt)
++int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
++ struct sk_buff_head *pktq)
+ {
+- uint incr_fix;
+- uint width;
+- uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
+- int err = 0;
+-
+- brcmf_dbg(SDIO, "fun = %d, addr = 0x%x, size = %d\n",
+- fn, addr, pkt->len);
+-
+- /* Async not implemented yet */
+- if (flags & SDIO_REQ_ASYNC)
+- return -ENOTSUPP;
+-
+- if (bar0 != sdiodev->sbwad) {
+- err = brcmf_sdcard_set_sbaddr_window(sdiodev, bar0);
+- if (err)
+- goto done;
+-
+- sdiodev->sbwad = bar0;
+- }
++ struct sk_buff *skb;
++ u32 addr = sdiodev->sbwad;
++ int err;
+
+- addr &= SBSDIO_SB_OFT_ADDR_MASK;
++ brcmf_dbg(SDIO, "addr = 0x%x, size = %d\n", addr, pktq->qlen);
+
+- incr_fix = (flags & SDIO_REQ_FIXED) ? SDIOH_DATA_FIX : SDIOH_DATA_INC;
+- width = (flags & SDIO_REQ_4BYTE) ? 4 : 2;
+- if (width == 4)
+- addr |= SBSDIO_SB_ACCESS_2_4B_FLAG;
++ err = brcmf_sdiod_addrprep(sdiodev, 4, &addr);
++ if (err)
++ return err;
+
+- err = brcmf_sdioh_request_buffer(sdiodev, incr_fix, SDIOH_WRITE, fn,
+- addr, pkt);
++ if (pktq->qlen == 1 || !sdiodev->sg_support)
++ skb_queue_walk(pktq, skb) {
++ err = brcmf_sdiod_buffrw(sdiodev, SDIO_FUNC_2, true,
++ addr, skb);
++ if (err)
++ break;
++ }
++ else
++ err = brcmf_sdiod_sglist_rw(sdiodev, SDIO_FUNC_2, true, addr,
++ pktq);
+
+-done:
+ return err;
+ }
+
+ int
+-brcmf_sdio_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
+- u8 *data, uint size)
++brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
++ u8 *data, uint size)
+ {
+ int bcmerror = 0;
+ struct sk_buff *pkt;
+@@ -487,7 +805,7 @@
+ /* Do the transfer(s) */
+ while (size) {
+ /* Set the backplane window to include the start address */
+- bcmerror = brcmf_sdcard_set_sbaddr_window(sdiodev, address);
++ bcmerror = brcmf_sdiod_set_sbaddr_window(sdiodev, address);
+ if (bcmerror)
+ break;
+
+@@ -501,9 +819,8 @@
+ skb_put(pkt, dsize);
+ if (write)
+ memcpy(pkt->data, data, dsize);
+- bcmerror = brcmf_sdioh_request_buffer(sdiodev, SDIOH_DATA_INC,
+- write, SDIO_FUNC_1,
+- sdaddr, pkt);
++ bcmerror = brcmf_sdiod_buffrw(sdiodev, SDIO_FUNC_1, write,
++ sdaddr, pkt);
+ if (bcmerror) {
+ brcmf_err("membytes transfer failed\n");
+ break;
+@@ -525,7 +842,7 @@
+ dev_kfree_skb(pkt);
+
+ /* Return the window to backplane enumeration space for core access */
+- if (brcmf_sdcard_set_sbaddr_window(sdiodev, sdiodev->sbwad))
++ if (brcmf_sdiod_set_sbaddr_window(sdiodev, sdiodev->sbwad))
+ brcmf_err("FAILED to set window back to 0x%x\n",
+ sdiodev->sbwad);
+
+@@ -534,67 +851,335 @@
+ return bcmerror;
+ }
+
+-int brcmf_sdcard_abort(struct brcmf_sdio_dev *sdiodev, uint fn)
++int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn)
+ {
+ char t_func = (char)fn;
+ brcmf_dbg(SDIO, "Enter\n");
+
+ /* issue abort cmd52 command through F0 */
+- brcmf_sdioh_request_byte(sdiodev, SDIOH_WRITE, SDIO_FUNC_0,
+- SDIO_CCCR_ABORT, &t_func);
++ brcmf_sdiod_request_data(sdiodev, SDIO_FUNC_0, SDIO_CCCR_ABORT,
++ sizeof(t_func), &t_func, true);
+
+ brcmf_dbg(SDIO, "Exit\n");
+ return 0;
+ }
+
+-int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
++static int brcmf_sdiod_remove(struct brcmf_sdio_dev *sdiodev)
+ {
+- u32 regs = 0;
++ if (sdiodev->bus) {
++ brcmf_sdio_remove(sdiodev->bus);
++ sdiodev->bus = NULL;
++ }
++
++ /* Disable Function 2 */
++ sdio_claim_host(sdiodev->func[2]);
++ sdio_disable_func(sdiodev->func[2]);
++ sdio_release_host(sdiodev->func[2]);
++
++ /* Disable Function 1 */
++ sdio_claim_host(sdiodev->func[1]);
++ sdio_disable_func(sdiodev->func[1]);
++ sdio_release_host(sdiodev->func[1]);
++
++ sdiodev->sbwad = 0;
++
++ return 0;
++}
++
++static int brcmf_sdiod_probe(struct brcmf_sdio_dev *sdiodev)
++{
++ struct sdio_func *func;
++ struct mmc_host *host;
++ uint max_blocks;
+ int ret = 0;
+
+- ret = brcmf_sdioh_attach(sdiodev);
+- if (ret)
++ sdiodev->num_funcs = 2;
++
++ sdio_claim_host(sdiodev->func[1]);
++
++ ret = sdio_set_block_size(sdiodev->func[1], SDIO_FUNC1_BLOCKSIZE);
++ if (ret) {
++ brcmf_err("Failed to set F1 blocksize\n");
++ sdio_release_host(sdiodev->func[1]);
++ goto out;
++ }
++ ret = sdio_set_block_size(sdiodev->func[2], SDIO_FUNC2_BLOCKSIZE);
++ if (ret) {
++ brcmf_err("Failed to set F2 blocksize\n");
++ sdio_release_host(sdiodev->func[1]);
++ goto out;
++ }
++
++ /* increase F2 timeout */
++ sdiodev->func[2]->enable_timeout = SDIO_WAIT_F2RDY;
++
++ /* Enable Function 1 */
++ ret = sdio_enable_func(sdiodev->func[1]);
++ sdio_release_host(sdiodev->func[1]);
++ if (ret) {
++ brcmf_err("Failed to enable F1: err=%d\n", ret);
+ goto out;
++ }
+
+- regs = SI_ENUM_BASE;
++ /*
++ * determine host related variables after brcmf_sdiod_probe()
++ * as func->cur_blksize is properly set and F2 init has been
++ * completed successfully.
++ */
++ func = sdiodev->func[2];
++ host = func->card->host;
++ sdiodev->sg_support = host->max_segs > 1;
++ max_blocks = min_t(uint, host->max_blk_count, 511u);
++ sdiodev->max_request_size = min_t(uint, host->max_req_size,
++ max_blocks * func->cur_blksize);
++ sdiodev->max_segment_count = min_t(uint, host->max_segs,
++ SG_MAX_SINGLE_ALLOC);
++ sdiodev->max_segment_size = host->max_seg_size;
+
+ /* try to attach to the target device */
+- sdiodev->bus = brcmf_sdbrcm_probe(regs, sdiodev);
++ sdiodev->bus = brcmf_sdio_probe(sdiodev);
+ if (!sdiodev->bus) {
+- brcmf_err("device attach failed\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ out:
+ if (ret)
+- brcmf_sdio_remove(sdiodev);
++ brcmf_sdiod_remove(sdiodev);
+
+ return ret;
+ }
+-EXPORT_SYMBOL(brcmf_sdio_probe);
+
+-int brcmf_sdio_remove(struct brcmf_sdio_dev *sdiodev)
++/* devices we support, null terminated */
++static const struct sdio_device_id brcmf_sdmmc_ids[] = {
++ {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43143)},
++ {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43241)},
++ {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329)},
++ {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330)},
++ {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334)},
++ {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43362)},
++ {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM,
++ SDIO_DEVICE_ID_BROADCOM_4335_4339)},
++ { /* end: all zeroes */ },
++};
++MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids);
++
++static struct brcmfmac_sdio_platform_data *brcmfmac_sdio_pdata;
++
++
++static int brcmf_ops_sdio_probe(struct sdio_func *func,
++ const struct sdio_device_id *id)
+ {
+- sdiodev->bus_if->state = BRCMF_BUS_DOWN;
++ int err;
++ struct brcmf_sdio_dev *sdiodev;
++ struct brcmf_bus *bus_if;
+
+- if (sdiodev->bus) {
+- brcmf_sdbrcm_disconnect(sdiodev->bus);
+- sdiodev->bus = NULL;
++ brcmf_dbg(SDIO, "Enter\n");
++ brcmf_dbg(SDIO, "Class=%x\n", func->class);
++ brcmf_dbg(SDIO, "sdio vendor ID: 0x%04x\n", func->vendor);
++ brcmf_dbg(SDIO, "sdio device ID: 0x%04x\n", func->device);
++ brcmf_dbg(SDIO, "Function#: %d\n", func->num);
++
++ /* Consume func num 1 but dont do anything with it. */
++ if (func->num == 1)
++ return 0;
++
++ /* Ignore anything but func 2 */
++ if (func->num != 2)
++ return -ENODEV;
++
++ bus_if = kzalloc(sizeof(struct brcmf_bus), GFP_KERNEL);
++ if (!bus_if)
++ return -ENOMEM;
++ sdiodev = kzalloc(sizeof(struct brcmf_sdio_dev), GFP_KERNEL);
++ if (!sdiodev) {
++ kfree(bus_if);
++ return -ENOMEM;
+ }
+
+- brcmf_sdioh_detach(sdiodev);
++ /* store refs to functions used. mmc_card does
++ * not hold the F0 function pointer.
++ */
++ sdiodev->func[0] = kmemdup(func, sizeof(*func), GFP_KERNEL);
++ sdiodev->func[0]->num = 0;
++ sdiodev->func[1] = func->card->sdio_func[0];
++ sdiodev->func[2] = func;
++
++ sdiodev->bus_if = bus_if;
++ bus_if->bus_priv.sdio = sdiodev;
++ bus_if->proto_type = BRCMF_PROTO_BCDC;
++ dev_set_drvdata(&func->dev, bus_if);
++ dev_set_drvdata(&sdiodev->func[1]->dev, bus_if);
++ sdiodev->dev = &sdiodev->func[1]->dev;
++ sdiodev->pdata = brcmfmac_sdio_pdata;
++
++ atomic_set(&sdiodev->suspend, false);
++ init_waitqueue_head(&sdiodev->request_word_wait);
++ init_waitqueue_head(&sdiodev->request_buffer_wait);
++
++ brcmf_dbg(SDIO, "F2 found, calling brcmf_sdiod_probe...\n");
++ err = brcmf_sdiod_probe(sdiodev);
++ if (err) {
++ brcmf_err("F2 error, probe failed %d...\n", err);
++ goto fail;
++ }
+
+- sdiodev->sbwad = 0;
++ brcmf_dbg(SDIO, "F2 init completed...\n");
++ return 0;
++
++fail:
++ dev_set_drvdata(&func->dev, NULL);
++ dev_set_drvdata(&sdiodev->func[1]->dev, NULL);
++ kfree(sdiodev->func[0]);
++ kfree(sdiodev);
++ kfree(bus_if);
++ return err;
++}
++
++static void brcmf_ops_sdio_remove(struct sdio_func *func)
++{
++ struct brcmf_bus *bus_if;
++ struct brcmf_sdio_dev *sdiodev;
++
++ brcmf_dbg(SDIO, "Enter\n");
++ brcmf_dbg(SDIO, "sdio vendor ID: 0x%04x\n", func->vendor);
++ brcmf_dbg(SDIO, "sdio device ID: 0x%04x\n", func->device);
++ brcmf_dbg(SDIO, "Function: %d\n", func->num);
++
++ if (func->num != 1 && func->num != 2)
++ return;
++
++ bus_if = dev_get_drvdata(&func->dev);
++ if (bus_if) {
++ sdiodev = bus_if->bus_priv.sdio;
++ brcmf_sdiod_remove(sdiodev);
++
++ dev_set_drvdata(&sdiodev->func[1]->dev, NULL);
++ dev_set_drvdata(&sdiodev->func[2]->dev, NULL);
++
++ kfree(bus_if);
++ kfree(sdiodev->func[0]);
++ kfree(sdiodev);
++ }
++
++ brcmf_dbg(SDIO, "Exit\n");
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int brcmf_ops_sdio_suspend(struct device *dev)
++{
++ mmc_pm_flag_t sdio_flags;
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ int ret = 0;
++
++ brcmf_dbg(SDIO, "\n");
++
++ atomic_set(&sdiodev->suspend, true);
++
++ sdio_flags = sdio_get_host_pm_caps(sdiodev->func[1]);
++ if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
++ brcmf_err("Host can't keep power while suspended\n");
++ return -EINVAL;
++ }
++
++ ret = sdio_set_host_pm_flags(sdiodev->func[1], MMC_PM_KEEP_POWER);
++ if (ret) {
++ brcmf_err("Failed to set pm_flags\n");
++ return ret;
++ }
++
++ brcmf_sdio_wd_timer(sdiodev->bus, 0);
++
++ return ret;
++}
++
++static int brcmf_ops_sdio_resume(struct device *dev)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++
++ brcmf_sdio_wd_timer(sdiodev->bus, BRCMF_WD_POLL_MS);
++ atomic_set(&sdiodev->suspend, false);
++ return 0;
++}
++
++static const struct dev_pm_ops brcmf_sdio_pm_ops = {
++ .suspend = brcmf_ops_sdio_suspend,
++ .resume = brcmf_ops_sdio_resume,
++};
++#endif /* CONFIG_PM_SLEEP */
++
++static struct sdio_driver brcmf_sdmmc_driver = {
++ .probe = brcmf_ops_sdio_probe,
++ .remove = brcmf_ops_sdio_remove,
++ .name = BRCMFMAC_SDIO_PDATA_NAME,
++ .id_table = brcmf_sdmmc_ids,
++#ifdef CONFIG_PM_SLEEP
++ .drv = {
++ .pm = &brcmf_sdio_pm_ops,
++ },
++#endif /* CONFIG_PM_SLEEP */
++};
++
++static int brcmf_sdio_pd_probe(struct platform_device *pdev)
++{
++ brcmf_dbg(SDIO, "Enter\n");
++
++ brcmfmac_sdio_pdata = dev_get_platdata(&pdev->dev);
++
++ if (brcmfmac_sdio_pdata->power_on)
++ brcmfmac_sdio_pdata->power_on();
++
++ return 0;
++}
++
++static int brcmf_sdio_pd_remove(struct platform_device *pdev)
++{
++ brcmf_dbg(SDIO, "Enter\n");
++
++ if (brcmfmac_sdio_pdata->power_off)
++ brcmfmac_sdio_pdata->power_off();
++
++ sdio_unregister_driver(&brcmf_sdmmc_driver);
+
+ return 0;
+ }
+-EXPORT_SYMBOL(brcmf_sdio_remove);
+
+-void brcmf_sdio_wdtmr_enable(struct brcmf_sdio_dev *sdiodev, bool enable)
++static struct platform_driver brcmf_sdio_pd = {
++ .remove = brcmf_sdio_pd_remove,
++ .driver = {
++ .name = BRCMFMAC_SDIO_PDATA_NAME,
++ .owner = THIS_MODULE,
++ }
++};
++
++void brcmf_sdio_register(void)
++{
++ int ret;
++
++ ret = sdio_register_driver(&brcmf_sdmmc_driver);
++ if (ret)
++ brcmf_err("sdio_register_driver failed: %d\n", ret);
++}
++
++void brcmf_sdio_exit(void)
+ {
+- if (enable)
+- brcmf_sdbrcm_wd_timer(sdiodev->bus, BRCMF_WD_POLL_MS);
++ brcmf_dbg(SDIO, "Enter\n");
++
++ if (brcmfmac_sdio_pdata)
++ platform_driver_unregister(&brcmf_sdio_pd);
+ else
+- brcmf_sdbrcm_wd_timer(sdiodev->bus, 0);
++ sdio_unregister_driver(&brcmf_sdmmc_driver);
++}
++
++void __init brcmf_sdio_init(void)
++{
++ int ret;
++
++ brcmf_dbg(SDIO, "Enter\n");
++
++ ret = platform_driver_probe(&brcmf_sdio_pd, brcmf_sdio_pd_probe);
++ if (ret == -ENODEV)
++ brcmf_dbg(SDIO, "No platform data available.\n");
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh_sdmmc.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,635 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#include <linux/types.h>
+-#include <linux/netdevice.h>
+-#include <linux/mmc/sdio.h>
+-#include <linux/mmc/core.h>
+-#include <linux/mmc/sdio_func.h>
+-#include <linux/mmc/sdio_ids.h>
+-#include <linux/mmc/card.h>
+-#include <linux/suspend.h>
+-#include <linux/errno.h>
+-#include <linux/sched.h> /* request_irq() */
+-#include <linux/module.h>
+-#include <linux/platform_device.h>
+-#include <linux/platform_data/brcmfmac-sdio.h>
+-#include <net/cfg80211.h>
+-
+-#include <defs.h>
+-#include <brcm_hw_ids.h>
+-#include <brcmu_utils.h>
+-#include <brcmu_wifi.h>
+-#include "sdio_host.h"
+-#include "dhd_dbg.h"
+-#include "dhd_bus.h"
+-
+-#define SDIO_VENDOR_ID_BROADCOM 0x02d0
+-
+-#define DMA_ALIGN_MASK 0x03
+-
+-#define SDIO_DEVICE_ID_BROADCOM_43143 43143
+-#define SDIO_DEVICE_ID_BROADCOM_43241 0x4324
+-#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
+-#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
+-#define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
+-#define SDIO_DEVICE_ID_BROADCOM_4335 0x4335
+-
+-#define SDIO_FUNC1_BLOCKSIZE 64
+-#define SDIO_FUNC2_BLOCKSIZE 512
+-
+-/* devices we support, null terminated */
+-static const struct sdio_device_id brcmf_sdmmc_ids[] = {
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43143)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43241)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4335)},
+- { /* end: all zeroes */ },
+-};
+-MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids);
+-
+-static struct brcmfmac_sdio_platform_data *brcmfmac_sdio_pdata;
+-
+-
+-static bool
+-brcmf_pm_resume_error(struct brcmf_sdio_dev *sdiodev)
+-{
+- bool is_err = false;
+-#ifdef CONFIG_PM_SLEEP
+- is_err = atomic_read(&sdiodev->suspend);
+-#endif
+- return is_err;
+-}
+-
+-static void
+-brcmf_pm_resume_wait(struct brcmf_sdio_dev *sdiodev, wait_queue_head_t *wq)
+-{
+-#ifdef CONFIG_PM_SLEEP
+- int retry = 0;
+- while (atomic_read(&sdiodev->suspend) && retry++ != 30)
+- wait_event_timeout(*wq, false, HZ/100);
+-#endif
+-}
+-
+-static inline int brcmf_sdioh_f0_write_byte(struct brcmf_sdio_dev *sdiodev,
+- uint regaddr, u8 *byte)
+-{
+- struct sdio_func *sdfunc = sdiodev->func[0];
+- int err_ret;
+-
+- /*
+- * Can only directly write to some F0 registers.
+- * Handle F2 enable/disable and Abort command
+- * as a special case.
+- */
+- if (regaddr == SDIO_CCCR_IOEx) {
+- sdfunc = sdiodev->func[2];
+- if (sdfunc) {
+- if (*byte & SDIO_FUNC_ENABLE_2) {
+- /* Enable Function 2 */
+- err_ret = sdio_enable_func(sdfunc);
+- if (err_ret)
+- brcmf_err("enable F2 failed:%d\n",
+- err_ret);
+- } else {
+- /* Disable Function 2 */
+- err_ret = sdio_disable_func(sdfunc);
+- if (err_ret)
+- brcmf_err("Disable F2 failed:%d\n",
+- err_ret);
+- }
+- }
+- } else if ((regaddr == SDIO_CCCR_ABORT) ||
+- (regaddr == SDIO_CCCR_IENx)) {
+- sdfunc = kmemdup(sdiodev->func[0], sizeof(struct sdio_func),
+- GFP_KERNEL);
+- if (!sdfunc)
+- return -ENOMEM;
+- sdfunc->num = 0;
+- sdio_writeb(sdfunc, *byte, regaddr, &err_ret);
+- kfree(sdfunc);
+- } else if (regaddr < 0xF0) {
+- brcmf_err("F0 Wr:0x%02x: write disallowed\n", regaddr);
+- err_ret = -EPERM;
+- } else {
+- sdio_f0_writeb(sdfunc, *byte, regaddr, &err_ret);
+- }
+-
+- return err_ret;
+-}
+-
+-int brcmf_sdioh_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw, uint func,
+- uint regaddr, u8 *byte)
+-{
+- int err_ret;
+-
+- brcmf_dbg(SDIO, "rw=%d, func=%d, addr=0x%05x\n", rw, func, regaddr);
+-
+- brcmf_pm_resume_wait(sdiodev, &sdiodev->request_byte_wait);
+- if (brcmf_pm_resume_error(sdiodev))
+- return -EIO;
+-
+- if (rw && func == 0) {
+- /* handle F0 separately */
+- err_ret = brcmf_sdioh_f0_write_byte(sdiodev, regaddr, byte);
+- } else {
+- if (rw) /* CMD52 Write */
+- sdio_writeb(sdiodev->func[func], *byte, regaddr,
+- &err_ret);
+- else if (func == 0) {
+- *byte = sdio_f0_readb(sdiodev->func[func], regaddr,
+- &err_ret);
+- } else {
+- *byte = sdio_readb(sdiodev->func[func], regaddr,
+- &err_ret);
+- }
+- }
+-
+- if (err_ret)
+- brcmf_err("Failed to %s byte F%d:@0x%05x=%02x, Err: %d\n",
+- rw ? "write" : "read", func, regaddr, *byte, err_ret);
+-
+- return err_ret;
+-}
+-
+-int brcmf_sdioh_request_word(struct brcmf_sdio_dev *sdiodev,
+- uint rw, uint func, uint addr, u32 *word,
+- uint nbytes)
+-{
+- int err_ret = -EIO;
+-
+- if (func == 0) {
+- brcmf_err("Only CMD52 allowed to F0\n");
+- return -EINVAL;
+- }
+-
+- brcmf_dbg(SDIO, "rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
+- rw, func, addr, nbytes);
+-
+- brcmf_pm_resume_wait(sdiodev, &sdiodev->request_word_wait);
+- if (brcmf_pm_resume_error(sdiodev))
+- return -EIO;
+-
+- if (rw) { /* CMD52 Write */
+- if (nbytes == 4)
+- sdio_writel(sdiodev->func[func], *word, addr,
+- &err_ret);
+- else if (nbytes == 2)
+- sdio_writew(sdiodev->func[func], (*word & 0xFFFF),
+- addr, &err_ret);
+- else
+- brcmf_err("Invalid nbytes: %d\n", nbytes);
+- } else { /* CMD52 Read */
+- if (nbytes == 4)
+- *word = sdio_readl(sdiodev->func[func], addr, &err_ret);
+- else if (nbytes == 2)
+- *word = sdio_readw(sdiodev->func[func], addr,
+- &err_ret) & 0xFFFF;
+- else
+- brcmf_err("Invalid nbytes: %d\n", nbytes);
+- }
+-
+- if (err_ret)
+- brcmf_err("Failed to %s word, Err: 0x%08x\n",
+- rw ? "write" : "read", err_ret);
+-
+- return err_ret;
+-}
+-
+-/* precondition: host controller is claimed */
+-static int
+-brcmf_sdioh_request_data(struct brcmf_sdio_dev *sdiodev, uint write, bool fifo,
+- uint func, uint addr, struct sk_buff *pkt, uint pktlen)
+-{
+- int err_ret = 0;
+-
+- if ((write) && (!fifo)) {
+- err_ret = sdio_memcpy_toio(sdiodev->func[func], addr,
+- ((u8 *) (pkt->data)), pktlen);
+- } else if (write) {
+- err_ret = sdio_memcpy_toio(sdiodev->func[func], addr,
+- ((u8 *) (pkt->data)), pktlen);
+- } else if (fifo) {
+- err_ret = sdio_readsb(sdiodev->func[func],
+- ((u8 *) (pkt->data)), addr, pktlen);
+- } else {
+- err_ret = sdio_memcpy_fromio(sdiodev->func[func],
+- ((u8 *) (pkt->data)),
+- addr, pktlen);
+- }
+-
+- return err_ret;
+-}
+-
+-/*
+- * This function takes a queue of packets. The packets on the queue
+- * are assumed to be properly aligned by the caller.
+- */
+-int
+-brcmf_sdioh_request_chain(struct brcmf_sdio_dev *sdiodev, uint fix_inc,
+- uint write, uint func, uint addr,
+- struct sk_buff_head *pktq)
+-{
+- bool fifo = (fix_inc == SDIOH_DATA_FIX);
+- u32 SGCount = 0;
+- int err_ret = 0;
+-
+- struct sk_buff *pkt;
+-
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- brcmf_pm_resume_wait(sdiodev, &sdiodev->request_chain_wait);
+- if (brcmf_pm_resume_error(sdiodev))
+- return -EIO;
+-
+- skb_queue_walk(pktq, pkt) {
+- uint pkt_len = pkt->len;
+- pkt_len += 3;
+- pkt_len &= 0xFFFFFFFC;
+-
+- err_ret = brcmf_sdioh_request_data(sdiodev, write, fifo, func,
+- addr, pkt, pkt_len);
+- if (err_ret) {
+- brcmf_err("%s FAILED %p[%d], addr=0x%05x, pkt_len=%d, ERR=0x%08x\n",
+- write ? "TX" : "RX", pkt, SGCount, addr,
+- pkt_len, err_ret);
+- } else {
+- brcmf_dbg(SDIO, "%s xfr'd %p[%d], addr=0x%05x, len=%d\n",
+- write ? "TX" : "RX", pkt, SGCount, addr,
+- pkt_len);
+- }
+- if (!fifo)
+- addr += pkt_len;
+-
+- SGCount++;
+- }
+-
+- brcmf_dbg(SDIO, "Exit\n");
+- return err_ret;
+-}
+-
+-/*
+- * This function takes a single DMA-able packet.
+- */
+-int brcmf_sdioh_request_buffer(struct brcmf_sdio_dev *sdiodev,
+- uint fix_inc, uint write, uint func, uint addr,
+- struct sk_buff *pkt)
+-{
+- int status;
+- uint pkt_len;
+- bool fifo = (fix_inc == SDIOH_DATA_FIX);
+-
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- if (pkt == NULL)
+- return -EINVAL;
+- pkt_len = pkt->len;
+-
+- brcmf_pm_resume_wait(sdiodev, &sdiodev->request_buffer_wait);
+- if (brcmf_pm_resume_error(sdiodev))
+- return -EIO;
+-
+- pkt_len += 3;
+- pkt_len &= (uint)~3;
+-
+- status = brcmf_sdioh_request_data(sdiodev, write, fifo, func,
+- addr, pkt, pkt_len);
+- if (status) {
+- brcmf_err("%s FAILED %p, addr=0x%05x, pkt_len=%d, ERR=0x%08x\n",
+- write ? "TX" : "RX", pkt, addr, pkt_len, status);
+- } else {
+- brcmf_dbg(SDIO, "%s xfr'd %p, addr=0x%05x, len=%d\n",
+- write ? "TX" : "RX", pkt, addr, pkt_len);
+- }
+-
+- return status;
+-}
+-
+-static int brcmf_sdioh_get_cisaddr(struct brcmf_sdio_dev *sdiodev, u32 regaddr)
+-{
+- /* read 24 bits and return valid 17 bit addr */
+- int i, ret;
+- u32 scratch, regdata;
+- __le32 scratch_le;
+- u8 *ptr = (u8 *)&scratch_le;
+-
+- for (i = 0; i < 3; i++) {
+- regdata = brcmf_sdio_regrl(sdiodev, regaddr, &ret);
+- if (ret != 0)
+- brcmf_err("Can't read!\n");
+-
+- *ptr++ = (u8) regdata;
+- regaddr++;
+- }
+-
+- /* Only the lower 17-bits are valid */
+- scratch = le32_to_cpu(scratch_le);
+- scratch &= 0x0001FFFF;
+- return scratch;
+-}
+-
+-static int brcmf_sdioh_enablefuncs(struct brcmf_sdio_dev *sdiodev)
+-{
+- int err_ret;
+- u32 fbraddr;
+- u8 func;
+-
+- brcmf_dbg(SDIO, "\n");
+-
+- /* Get the Card's common CIS address */
+- sdiodev->func_cis_ptr[0] = brcmf_sdioh_get_cisaddr(sdiodev,
+- SDIO_CCCR_CIS);
+- brcmf_dbg(SDIO, "Card's Common CIS Ptr = 0x%x\n",
+- sdiodev->func_cis_ptr[0]);
+-
+- /* Get the Card's function CIS (for each function) */
+- for (fbraddr = SDIO_FBR_BASE(1), func = 1;
+- func <= sdiodev->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) {
+- sdiodev->func_cis_ptr[func] =
+- brcmf_sdioh_get_cisaddr(sdiodev, SDIO_FBR_CIS + fbraddr);
+- brcmf_dbg(SDIO, "Function %d CIS Ptr = 0x%x\n",
+- func, sdiodev->func_cis_ptr[func]);
+- }
+-
+- /* Enable Function 1 */
+- err_ret = sdio_enable_func(sdiodev->func[1]);
+- if (err_ret)
+- brcmf_err("Failed to enable F1 Err: 0x%08x\n", err_ret);
+-
+- return false;
+-}
+-
+-/*
+- * Public entry points & extern's
+- */
+-int brcmf_sdioh_attach(struct brcmf_sdio_dev *sdiodev)
+-{
+- int err_ret = 0;
+-
+- brcmf_dbg(SDIO, "\n");
+-
+- sdiodev->num_funcs = 2;
+-
+- sdio_claim_host(sdiodev->func[1]);
+-
+- err_ret = sdio_set_block_size(sdiodev->func[1], SDIO_FUNC1_BLOCKSIZE);
+- if (err_ret) {
+- brcmf_err("Failed to set F1 blocksize\n");
+- goto out;
+- }
+-
+- err_ret = sdio_set_block_size(sdiodev->func[2], SDIO_FUNC2_BLOCKSIZE);
+- if (err_ret) {
+- brcmf_err("Failed to set F2 blocksize\n");
+- goto out;
+- }
+-
+- brcmf_sdioh_enablefuncs(sdiodev);
+-
+-out:
+- sdio_release_host(sdiodev->func[1]);
+- brcmf_dbg(SDIO, "Done\n");
+- return err_ret;
+-}
+-
+-void brcmf_sdioh_detach(struct brcmf_sdio_dev *sdiodev)
+-{
+- brcmf_dbg(SDIO, "\n");
+-
+- /* Disable Function 2 */
+- sdio_claim_host(sdiodev->func[2]);
+- sdio_disable_func(sdiodev->func[2]);
+- sdio_release_host(sdiodev->func[2]);
+-
+- /* Disable Function 1 */
+- sdio_claim_host(sdiodev->func[1]);
+- sdio_disable_func(sdiodev->func[1]);
+- sdio_release_host(sdiodev->func[1]);
+-
+-}
+-
+-static int brcmf_ops_sdio_probe(struct sdio_func *func,
+- const struct sdio_device_id *id)
+-{
+- int err;
+- struct brcmf_sdio_dev *sdiodev;
+- struct brcmf_bus *bus_if;
+-
+- brcmf_dbg(SDIO, "Enter\n");
+- brcmf_dbg(SDIO, "Class=%x\n", func->class);
+- brcmf_dbg(SDIO, "sdio vendor ID: 0x%04x\n", func->vendor);
+- brcmf_dbg(SDIO, "sdio device ID: 0x%04x\n", func->device);
+- brcmf_dbg(SDIO, "Function#: %d\n", func->num);
+-
+- /* Consume func num 1 but dont do anything with it. */
+- if (func->num == 1)
+- return 0;
+-
+- /* Ignore anything but func 2 */
+- if (func->num != 2)
+- return -ENODEV;
+-
+- bus_if = kzalloc(sizeof(struct brcmf_bus), GFP_KERNEL);
+- if (!bus_if)
+- return -ENOMEM;
+- sdiodev = kzalloc(sizeof(struct brcmf_sdio_dev), GFP_KERNEL);
+- if (!sdiodev) {
+- kfree(bus_if);
+- return -ENOMEM;
+- }
+-
+- sdiodev->func[0] = func->card->sdio_func[0];
+- sdiodev->func[1] = func->card->sdio_func[0];
+- sdiodev->func[2] = func;
+-
+- sdiodev->bus_if = bus_if;
+- bus_if->bus_priv.sdio = sdiodev;
+- bus_if->align = BRCMF_SDALIGN;
+- dev_set_drvdata(&func->dev, bus_if);
+- dev_set_drvdata(&sdiodev->func[1]->dev, bus_if);
+- sdiodev->dev = &sdiodev->func[1]->dev;
+- sdiodev->pdata = brcmfmac_sdio_pdata;
+-
+- atomic_set(&sdiodev->suspend, false);
+- init_waitqueue_head(&sdiodev->request_byte_wait);
+- init_waitqueue_head(&sdiodev->request_word_wait);
+- init_waitqueue_head(&sdiodev->request_chain_wait);
+- init_waitqueue_head(&sdiodev->request_buffer_wait);
+-
+- brcmf_dbg(SDIO, "F2 found, calling brcmf_sdio_probe...\n");
+- err = brcmf_sdio_probe(sdiodev);
+- if (err) {
+- brcmf_err("F2 error, probe failed %d...\n", err);
+- goto fail;
+- }
+- brcmf_dbg(SDIO, "F2 init completed...\n");
+- return 0;
+-
+-fail:
+- dev_set_drvdata(&func->dev, NULL);
+- dev_set_drvdata(&sdiodev->func[1]->dev, NULL);
+- kfree(sdiodev);
+- kfree(bus_if);
+- return err;
+-}
+-
+-static void brcmf_ops_sdio_remove(struct sdio_func *func)
+-{
+- struct brcmf_bus *bus_if;
+- struct brcmf_sdio_dev *sdiodev;
+-
+- brcmf_dbg(SDIO, "Enter\n");
+- brcmf_dbg(SDIO, "sdio vendor ID: 0x%04x\n", func->vendor);
+- brcmf_dbg(SDIO, "sdio device ID: 0x%04x\n", func->device);
+- brcmf_dbg(SDIO, "Function: %d\n", func->num);
+-
+- if (func->num != 1 && func->num != 2)
+- return;
+-
+- bus_if = dev_get_drvdata(&func->dev);
+- if (bus_if) {
+- sdiodev = bus_if->bus_priv.sdio;
+- brcmf_sdio_remove(sdiodev);
+-
+- dev_set_drvdata(&sdiodev->func[1]->dev, NULL);
+- dev_set_drvdata(&sdiodev->func[2]->dev, NULL);
+-
+- kfree(bus_if);
+- kfree(sdiodev);
+- }
+-
+- brcmf_dbg(SDIO, "Exit\n");
+-}
+-
+-#ifdef CONFIG_PM_SLEEP
+-static int brcmf_sdio_suspend(struct device *dev)
+-{
+- mmc_pm_flag_t sdio_flags;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- int ret = 0;
+-
+- brcmf_dbg(SDIO, "\n");
+-
+- atomic_set(&sdiodev->suspend, true);
+-
+- sdio_flags = sdio_get_host_pm_caps(sdiodev->func[1]);
+- if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
+- brcmf_err("Host can't keep power while suspended\n");
+- return -EINVAL;
+- }
+-
+- ret = sdio_set_host_pm_flags(sdiodev->func[1], MMC_PM_KEEP_POWER);
+- if (ret) {
+- brcmf_err("Failed to set pm_flags\n");
+- return ret;
+- }
+-
+- brcmf_sdio_wdtmr_enable(sdiodev, false);
+-
+- return ret;
+-}
+-
+-static int brcmf_sdio_resume(struct device *dev)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+-
+- brcmf_sdio_wdtmr_enable(sdiodev, true);
+- atomic_set(&sdiodev->suspend, false);
+- return 0;
+-}
+-
+-static const struct dev_pm_ops brcmf_sdio_pm_ops = {
+- .suspend = brcmf_sdio_suspend,
+- .resume = brcmf_sdio_resume,
+-};
+-#endif /* CONFIG_PM_SLEEP */
+-
+-static struct sdio_driver brcmf_sdmmc_driver = {
+- .probe = brcmf_ops_sdio_probe,
+- .remove = brcmf_ops_sdio_remove,
+- .name = BRCMFMAC_SDIO_PDATA_NAME,
+- .id_table = brcmf_sdmmc_ids,
+-#ifdef CONFIG_PM_SLEEP
+- .drv = {
+- .pm = &brcmf_sdio_pm_ops,
+- },
+-#endif /* CONFIG_PM_SLEEP */
+-};
+-
+-static int brcmf_sdio_pd_probe(struct platform_device *pdev)
+-{
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- brcmfmac_sdio_pdata = pdev->dev.platform_data;
+-
+- if (brcmfmac_sdio_pdata->power_on)
+- brcmfmac_sdio_pdata->power_on();
+-
+- return 0;
+-}
+-
+-static int brcmf_sdio_pd_remove(struct platform_device *pdev)
+-{
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- if (brcmfmac_sdio_pdata->power_off)
+- brcmfmac_sdio_pdata->power_off();
+-
+- sdio_unregister_driver(&brcmf_sdmmc_driver);
+-
+- return 0;
+-}
+-
+-static struct platform_driver brcmf_sdio_pd = {
+- .remove = brcmf_sdio_pd_remove,
+- .driver = {
+- .name = BRCMFMAC_SDIO_PDATA_NAME
+- }
+-};
+-
+-void brcmf_sdio_register(void)
+-{
+- int ret;
+-
+- ret = sdio_register_driver(&brcmf_sdmmc_driver);
+- if (ret)
+- brcmf_err("sdio_register_driver failed: %d\n", ret);
+-}
+-
+-void brcmf_sdio_exit(void)
+-{
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- if (brcmfmac_sdio_pdata)
+- platform_driver_unregister(&brcmf_sdio_pd);
+- else
+- sdio_unregister_driver(&brcmf_sdmmc_driver);
+-}
+-
+-void __init brcmf_sdio_init(void)
+-{
+- int ret;
+-
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- ret = platform_driver_probe(&brcmf_sdio_pd, brcmf_sdio_pd_probe);
+- if (ret == -ENODEV)
+- brcmf_dbg(SDIO, "No platform data available.\n");
+-}
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h 2014-05-15 20:34:00.554032284 +0200
+@@ -17,13 +17,23 @@
+ #ifndef _BRCMF_BUS_H_
+ #define _BRCMF_BUS_H_
+
++#include "dhd_dbg.h"
++
+ /* The level of bus communication with the dongle */
+ enum brcmf_bus_state {
++ BRCMF_BUS_UNKNOWN, /* Not determined yet */
++ BRCMF_BUS_NOMEDIUM, /* No medium access to dongle */
+ BRCMF_BUS_DOWN, /* Not ready for frame transfers */
+ BRCMF_BUS_LOAD, /* Download access only (CPU reset) */
+ BRCMF_BUS_DATA /* Ready for frame transfers */
+ };
+
++/* The level of bus communication with the dongle */
++enum brcmf_bus_protocol_type {
++ BRCMF_PROTO_BCDC,
++ BRCMF_PROTO_MSGBUF
++};
++
+ struct brcmf_bus_dcmd {
+ char *name;
+ char *param;
+@@ -34,9 +44,14 @@
+ /**
+ * struct brcmf_bus_ops - bus callback operations.
+ *
++ * @preinit: execute bus/device specific dongle init commands (optional).
+ * @init: prepare for communication with dongle.
+ * @stop: clear pending frames, disable data flow.
+- * @txdata: send a data frame to the dongle (callee disposes skb).
++ * @txdata: send a data frame to the dongle. When the data
++ * has been transferred, the common driver must be
++ * notified using brcmf_txcomplete(). The common
++ * driver calls this function with interrupts
++ * disabled.
+ * @txctl: transmit a control request message to dongle.
+ * @rxctl: receive a control response message from dongle.
+ * @gettxq: obtain a reference of bus transmit queue (optional).
+@@ -47,6 +62,7 @@
+ * indicated otherwise these callbacks are mandatory.
+ */
+ struct brcmf_bus_ops {
++ int (*preinit)(struct device *dev);
+ int (*init)(struct device *dev);
+ void (*stop)(struct device *dev);
+ int (*txdata)(struct device *dev, struct sk_buff *skb);
+@@ -59,13 +75,13 @@
+ * struct brcmf_bus - interface structure between common and bus layer
+ *
+ * @bus_priv: pointer to private bus device.
++ * @proto_type: protocol type, bcdc or msgbuf
+ * @dev: device pointer of bus device.
+ * @drvr: public driver information.
+ * @state: operational state of the bus interface.
+ * @maxctl: maximum size for rxctl request message.
+ * @tx_realloc: number of tx packets realloced for headroom.
+ * @dstats: dongle-based statistical data.
+- * @align: alignment requirement for the bus.
+ * @dcmd_list: bus/device specific dongle initialization commands.
+ * @chip: device identifier of the dongle chip.
+ * @chiprev: revision of the dongle chip.
+@@ -75,15 +91,14 @@
+ struct brcmf_sdio_dev *sdio;
+ struct brcmf_usbdev *usb;
+ } bus_priv;
++ enum brcmf_bus_protocol_type proto_type;
+ struct device *dev;
+ struct brcmf_pub *drvr;
+ enum brcmf_bus_state state;
+ uint maxctl;
+ unsigned long tx_realloc;
+- u8 align;
+ u32 chip;
+ u32 chiprev;
+- struct list_head dcmd_list;
+
+ struct brcmf_bus_ops *ops;
+ };
+@@ -91,6 +106,13 @@
+ /*
+ * callback wrappers
+ */
++static inline int brcmf_bus_preinit(struct brcmf_bus *bus)
++{
++ if (!bus->ops->preinit)
++ return 0;
++ return bus->ops->preinit(bus->dev);
++}
++
+ static inline int brcmf_bus_init(struct brcmf_bus *bus)
+ {
+ return bus->ops->init(bus->dev);
+@@ -126,39 +148,58 @@
+
+ return bus->ops->gettxq(bus->dev);
+ }
++
++static inline bool brcmf_bus_ready(struct brcmf_bus *bus)
++{
++ return bus->state == BRCMF_BUS_LOAD || bus->state == BRCMF_BUS_DATA;
++}
++
++static inline void brcmf_bus_change_state(struct brcmf_bus *bus,
++ enum brcmf_bus_state new_state)
++{
++ /* NOMEDIUM is permanent */
++ if (bus->state == BRCMF_BUS_NOMEDIUM)
++ return;
++
++ brcmf_dbg(TRACE, "%d -> %d\n", bus->state, new_state);
++ bus->state = new_state;
++}
++
+ /*
+ * interface functions from common layer
+ */
+
+-extern bool brcmf_c_prec_enq(struct device *dev, struct pktq *q,
+- struct sk_buff *pkt, int prec);
++bool brcmf_c_prec_enq(struct device *dev, struct pktq *q, struct sk_buff *pkt,
++ int prec);
+
+ /* Receive frame for delivery to OS. Callee disposes of rxp. */
+-extern void brcmf_rx_frames(struct device *dev, struct sk_buff_head *rxlist);
++void brcmf_rx_frame(struct device *dev, struct sk_buff *rxp);
+
+ /* Indication from bus module regarding presence/insertion of dongle. */
+-extern int brcmf_attach(uint bus_hdrlen, struct device *dev);
++int brcmf_attach(struct device *dev);
+ /* Indication from bus module regarding removal/absence of dongle */
+-extern void brcmf_detach(struct device *dev);
++void brcmf_detach(struct device *dev);
+ /* Indication from bus module that dongle should be reset */
+-extern void brcmf_dev_reset(struct device *dev);
++void brcmf_dev_reset(struct device *dev);
+ /* Indication from bus module to change flow-control state */
+-extern void brcmf_txflowblock(struct device *dev, bool state);
++void brcmf_txflowblock(struct device *dev, bool state);
+
+ /* Notify the bus has transferred the tx packet to firmware */
+-extern void brcmf_txcomplete(struct device *dev, struct sk_buff *txp,
+- bool success);
++void brcmf_txcomplete(struct device *dev, struct sk_buff *txp, bool success);
+
+-extern int brcmf_bus_start(struct device *dev);
++int brcmf_bus_start(struct device *dev);
++s32 brcmf_iovar_data_set(struct device *dev, char *name, void *data,
++ u32 len);
++void brcmf_bus_add_txhdrlen(struct device *dev, uint len);
+
+ #ifdef CONFIG_BRCMFMAC_SDIO
+-extern void brcmf_sdio_exit(void);
+-extern void brcmf_sdio_init(void);
+-extern void brcmf_sdio_register(void);
++void brcmf_sdio_exit(void);
++void brcmf_sdio_init(void);
++void brcmf_sdio_register(void);
+ #endif
+ #ifdef CONFIG_BRCMFMAC_USB
+-extern void brcmf_usb_exit(void);
+-extern void brcmf_usb_register(void);
++void brcmf_usb_exit(void);
++void brcmf_usb_register(void);
+ #endif
+
+ #endif /* _BRCMF_BUS_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_cdc.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_cdc.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_cdc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_cdc.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,389 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-/*******************************************************************************
+- * Communicates with the dongle by using dcmd codes.
+- * For certain dcmd codes, the dongle interprets string data from the host.
+- ******************************************************************************/
+-
+-#include <linux/types.h>
+-#include <linux/netdevice.h>
+-
+-#include <brcmu_utils.h>
+-#include <brcmu_wifi.h>
+-
+-#include "dhd.h"
+-#include "dhd_proto.h"
+-#include "dhd_bus.h"
+-#include "fwsignal.h"
+-#include "dhd_dbg.h"
+-
+-struct brcmf_proto_cdc_dcmd {
+- __le32 cmd; /* dongle command value */
+- __le32 len; /* lower 16: output buflen;
+- * upper 16: input buflen (excludes header) */
+- __le32 flags; /* flag defns given below */
+- __le32 status; /* status code returned from the device */
+-};
+-
+-/* Max valid buffer size that can be sent to the dongle */
+-#define CDC_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
+-
+-/* CDC flag definitions */
+-#define CDC_DCMD_ERROR 0x01 /* 1=cmd failed */
+-#define CDC_DCMD_SET 0x02 /* 0=get, 1=set cmd */
+-#define CDC_DCMD_IF_MASK 0xF000 /* I/F index */
+-#define CDC_DCMD_IF_SHIFT 12
+-#define CDC_DCMD_ID_MASK 0xFFFF0000 /* id an cmd pairing */
+-#define CDC_DCMD_ID_SHIFT 16 /* ID Mask shift bits */
+-#define CDC_DCMD_ID(flags) \
+- (((flags) & CDC_DCMD_ID_MASK) >> CDC_DCMD_ID_SHIFT)
+-
+-/*
+- * BDC header - Broadcom specific extension of CDC.
+- * Used on data packets to convey priority across USB.
+- */
+-#define BDC_HEADER_LEN 4
+-#define BDC_PROTO_VER 2 /* Protocol version */
+-#define BDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */
+-#define BDC_FLAG_VER_SHIFT 4 /* Protocol version shift */
+-#define BDC_FLAG_SUM_GOOD 0x04 /* Good RX checksums */
+-#define BDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */
+-#define BDC_PRIORITY_MASK 0x7
+-#define BDC_FLAG2_IF_MASK 0x0f /* packet rx interface in APSTA */
+-#define BDC_FLAG2_IF_SHIFT 0
+-
+-#define BDC_GET_IF_IDX(hdr) \
+- ((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT))
+-#define BDC_SET_IF_IDX(hdr, idx) \
+- ((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | \
+- ((idx) << BDC_FLAG2_IF_SHIFT)))
+-
+-/**
+- * struct brcmf_proto_bdc_header - BDC header format
+- *
+- * @flags: flags contain protocol and checksum info.
+- * @priority: 802.1d priority and USB flow control info (bit 4:7).
+- * @flags2: additional flags containing dongle interface index.
+- * @data_offset: start of packet data. header is following by firmware signals.
+- */
+-struct brcmf_proto_bdc_header {
+- u8 flags;
+- u8 priority;
+- u8 flags2;
+- u8 data_offset;
+-};
+-
+-/*
+- * maximum length of firmware signal data between
+- * the BDC header and packet data in the tx path.
+- */
+-#define BRCMF_PROT_FW_SIGNAL_MAX_TXBYTES 12
+-
+-#define RETRIES 2 /* # of retries to retrieve matching dcmd response */
+-#define BUS_HEADER_LEN (16+64) /* Must be atleast SDPCM_RESERVE
+- * (amount of header tha might be added)
+- * plus any space that might be needed
+- * for bus alignment padding.
+- */
+-#define ROUND_UP_MARGIN 2048 /* Biggest bus block size possible for
+- * round off at the end of buffer
+- * Currently is SDIO
+- */
+-
+-struct brcmf_proto {
+- u16 reqid;
+- u8 bus_header[BUS_HEADER_LEN];
+- struct brcmf_proto_cdc_dcmd msg;
+- unsigned char buf[BRCMF_DCMD_MAXLEN + ROUND_UP_MARGIN];
+-};
+-
+-static int brcmf_proto_cdc_msg(struct brcmf_pub *drvr)
+-{
+- struct brcmf_proto *prot = drvr->prot;
+- int len = le32_to_cpu(prot->msg.len) +
+- sizeof(struct brcmf_proto_cdc_dcmd);
+-
+- brcmf_dbg(CDC, "Enter\n");
+-
+- /* NOTE : cdc->msg.len holds the desired length of the buffer to be
+- * returned. Only up to CDC_MAX_MSG_SIZE of this buffer area
+- * is actually sent to the dongle
+- */
+- if (len > CDC_MAX_MSG_SIZE)
+- len = CDC_MAX_MSG_SIZE;
+-
+- /* Send request */
+- return brcmf_bus_txctl(drvr->bus_if, (unsigned char *)&prot->msg, len);
+-}
+-
+-static int brcmf_proto_cdc_cmplt(struct brcmf_pub *drvr, u32 id, u32 len)
+-{
+- int ret;
+- struct brcmf_proto *prot = drvr->prot;
+-
+- brcmf_dbg(CDC, "Enter\n");
+- len += sizeof(struct brcmf_proto_cdc_dcmd);
+- do {
+- ret = brcmf_bus_rxctl(drvr->bus_if, (unsigned char *)&prot->msg,
+- len);
+- if (ret < 0)
+- break;
+- } while (CDC_DCMD_ID(le32_to_cpu(prot->msg.flags)) != id);
+-
+- return ret;
+-}
+-
+-int
+-brcmf_proto_cdc_query_dcmd(struct brcmf_pub *drvr, int ifidx, uint cmd,
+- void *buf, uint len)
+-{
+- struct brcmf_proto *prot = drvr->prot;
+- struct brcmf_proto_cdc_dcmd *msg = &prot->msg;
+- void *info;
+- int ret = 0, retries = 0;
+- u32 id, flags;
+-
+- brcmf_dbg(CDC, "Enter, cmd %d len %d\n", cmd, len);
+-
+- memset(msg, 0, sizeof(struct brcmf_proto_cdc_dcmd));
+-
+- msg->cmd = cpu_to_le32(cmd);
+- msg->len = cpu_to_le32(len);
+- flags = (++prot->reqid << CDC_DCMD_ID_SHIFT);
+- flags = (flags & ~CDC_DCMD_IF_MASK) |
+- (ifidx << CDC_DCMD_IF_SHIFT);
+- msg->flags = cpu_to_le32(flags);
+-
+- if (buf)
+- memcpy(prot->buf, buf, len);
+-
+- ret = brcmf_proto_cdc_msg(drvr);
+- if (ret < 0) {
+- brcmf_err("brcmf_proto_cdc_msg failed w/status %d\n",
+- ret);
+- goto done;
+- }
+-
+-retry:
+- /* wait for interrupt and get first fragment */
+- ret = brcmf_proto_cdc_cmplt(drvr, prot->reqid, len);
+- if (ret < 0)
+- goto done;
+-
+- flags = le32_to_cpu(msg->flags);
+- id = (flags & CDC_DCMD_ID_MASK) >> CDC_DCMD_ID_SHIFT;
+-
+- if ((id < prot->reqid) && (++retries < RETRIES))
+- goto retry;
+- if (id != prot->reqid) {
+- brcmf_err("%s: unexpected request id %d (expected %d)\n",
+- brcmf_ifname(drvr, ifidx), id, prot->reqid);
+- ret = -EINVAL;
+- goto done;
+- }
+-
+- /* Check info buffer */
+- info = (void *)&msg[1];
+-
+- /* Copy info buffer */
+- if (buf) {
+- if (ret < (int)len)
+- len = ret;
+- memcpy(buf, info, len);
+- }
+-
+- /* Check the ERROR flag */
+- if (flags & CDC_DCMD_ERROR)
+- ret = le32_to_cpu(msg->status);
+-
+-done:
+- return ret;
+-}
+-
+-int brcmf_proto_cdc_set_dcmd(struct brcmf_pub *drvr, int ifidx, uint cmd,
+- void *buf, uint len)
+-{
+- struct brcmf_proto *prot = drvr->prot;
+- struct brcmf_proto_cdc_dcmd *msg = &prot->msg;
+- int ret = 0;
+- u32 flags, id;
+-
+- brcmf_dbg(CDC, "Enter, cmd %d len %d\n", cmd, len);
+-
+- memset(msg, 0, sizeof(struct brcmf_proto_cdc_dcmd));
+-
+- msg->cmd = cpu_to_le32(cmd);
+- msg->len = cpu_to_le32(len);
+- flags = (++prot->reqid << CDC_DCMD_ID_SHIFT) | CDC_DCMD_SET;
+- flags = (flags & ~CDC_DCMD_IF_MASK) |
+- (ifidx << CDC_DCMD_IF_SHIFT);
+- msg->flags = cpu_to_le32(flags);
+-
+- if (buf)
+- memcpy(prot->buf, buf, len);
+-
+- ret = brcmf_proto_cdc_msg(drvr);
+- if (ret < 0)
+- goto done;
+-
+- ret = brcmf_proto_cdc_cmplt(drvr, prot->reqid, len);
+- if (ret < 0)
+- goto done;
+-
+- flags = le32_to_cpu(msg->flags);
+- id = (flags & CDC_DCMD_ID_MASK) >> CDC_DCMD_ID_SHIFT;
+-
+- if (id != prot->reqid) {
+- brcmf_err("%s: unexpected request id %d (expected %d)\n",
+- brcmf_ifname(drvr, ifidx), id, prot->reqid);
+- ret = -EINVAL;
+- goto done;
+- }
+-
+- /* Check the ERROR flag */
+- if (flags & CDC_DCMD_ERROR)
+- ret = le32_to_cpu(msg->status);
+-
+-done:
+- return ret;
+-}
+-
+-static bool pkt_sum_needed(struct sk_buff *skb)
+-{
+- return skb->ip_summed == CHECKSUM_PARTIAL;
+-}
+-
+-static void pkt_set_sum_good(struct sk_buff *skb, bool x)
+-{
+- skb->ip_summed = (x ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
+-}
+-
+-void brcmf_proto_hdrpush(struct brcmf_pub *drvr, int ifidx, u8 offset,
+- struct sk_buff *pktbuf)
+-{
+- struct brcmf_proto_bdc_header *h;
+-
+- brcmf_dbg(CDC, "Enter\n");
+-
+- /* Push BDC header used to convey priority for buses that don't */
+- skb_push(pktbuf, BDC_HEADER_LEN);
+-
+- h = (struct brcmf_proto_bdc_header *)(pktbuf->data);
+-
+- h->flags = (BDC_PROTO_VER << BDC_FLAG_VER_SHIFT);
+- if (pkt_sum_needed(pktbuf))
+- h->flags |= BDC_FLAG_SUM_NEEDED;
+-
+- h->priority = (pktbuf->priority & BDC_PRIORITY_MASK);
+- h->flags2 = 0;
+- h->data_offset = offset;
+- BDC_SET_IF_IDX(h, ifidx);
+-}
+-
+-int brcmf_proto_hdrpull(struct brcmf_pub *drvr, bool do_fws, u8 *ifidx,
+- struct sk_buff *pktbuf)
+-{
+- struct brcmf_proto_bdc_header *h;
+-
+- brcmf_dbg(CDC, "Enter\n");
+-
+- /* Pop BDC header used to convey priority for buses that don't */
+-
+- if (pktbuf->len <= BDC_HEADER_LEN) {
+- brcmf_dbg(INFO, "rx data too short (%d <= %d)\n",
+- pktbuf->len, BDC_HEADER_LEN);
+- return -EBADE;
+- }
+-
+- h = (struct brcmf_proto_bdc_header *)(pktbuf->data);
+-
+- *ifidx = BDC_GET_IF_IDX(h);
+- if (*ifidx >= BRCMF_MAX_IFS) {
+- brcmf_err("rx data ifnum out of range (%d)\n", *ifidx);
+- return -EBADE;
+- }
+- /* The ifidx is the idx to map to matching netdev/ifp. When receiving
+- * events this is easy because it contains the bssidx which maps
+- * 1-on-1 to the netdev/ifp. But for data frames the ifidx is rcvd.
+- * bssidx 1 is used for p2p0 and no data can be received or
+- * transmitted on it. Therefor bssidx is ifidx + 1 if ifidx > 0
+- */
+- if (*ifidx)
+- (*ifidx)++;
+-
+- if (((h->flags & BDC_FLAG_VER_MASK) >> BDC_FLAG_VER_SHIFT) !=
+- BDC_PROTO_VER) {
+- brcmf_err("%s: non-BDC packet received, flags 0x%x\n",
+- brcmf_ifname(drvr, *ifidx), h->flags);
+- return -EBADE;
+- }
+-
+- if (h->flags & BDC_FLAG_SUM_GOOD) {
+- brcmf_dbg(CDC, "%s: BDC rcv, good checksum, flags 0x%x\n",
+- brcmf_ifname(drvr, *ifidx), h->flags);
+- pkt_set_sum_good(pktbuf, true);
+- }
+-
+- pktbuf->priority = h->priority & BDC_PRIORITY_MASK;
+-
+- skb_pull(pktbuf, BDC_HEADER_LEN);
+- if (do_fws)
+- brcmf_fws_hdrpull(drvr, *ifidx, h->data_offset << 2, pktbuf);
+- else
+- skb_pull(pktbuf, h->data_offset << 2);
+-
+- if (pktbuf->len == 0)
+- return -ENODATA;
+- return 0;
+-}
+-
+-int brcmf_proto_attach(struct brcmf_pub *drvr)
+-{
+- struct brcmf_proto *cdc;
+-
+- cdc = kzalloc(sizeof(struct brcmf_proto), GFP_ATOMIC);
+- if (!cdc)
+- goto fail;
+-
+- /* ensure that the msg buf directly follows the cdc msg struct */
+- if ((unsigned long)(&cdc->msg + 1) != (unsigned long)cdc->buf) {
+- brcmf_err("struct brcmf_proto is not correctly defined\n");
+- goto fail;
+- }
+-
+- drvr->prot = cdc;
+- drvr->hdrlen += BDC_HEADER_LEN + BRCMF_PROT_FW_SIGNAL_MAX_TXBYTES;
+- drvr->bus_if->maxctl = BRCMF_DCMD_MAXLEN +
+- sizeof(struct brcmf_proto_cdc_dcmd) + ROUND_UP_MARGIN;
+- return 0;
+-
+-fail:
+- kfree(cdc);
+- return -ENOMEM;
+-}
+-
+-/* ~NOTE~ What if another thread is waiting on the semaphore? Holding it? */
+-void brcmf_proto_detach(struct brcmf_pub *drvr)
+-{
+- kfree(drvr->prot);
+- drvr->prot = NULL;
+-}
+-
+-void brcmf_proto_stop(struct brcmf_pub *drvr)
+-{
+- /* Nothing to do for CDC */
+-}
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c 2014-05-15 20:34:00.554032284 +0200
+@@ -21,9 +21,9 @@
+ #include <brcmu_utils.h>
+ #include "dhd.h"
+ #include "dhd_bus.h"
+-#include "dhd_proto.h"
+ #include "dhd_dbg.h"
+ #include "fwil.h"
++#include "fwil_types.h"
+ #include "tracepoint.h"
+
+ #define PKTFILTER_BUF_SIZE 128
+@@ -32,15 +32,6 @@
+ #define BRCMF_DEFAULT_SCAN_UNASSOC_TIME 40
+ #define BRCMF_DEFAULT_PACKET_FILTER "100 0 0 0 0x01 0x00"
+
+-#ifdef DEBUG
+-static const char brcmf_version[] =
+- "Dongle Host Driver, version " BRCMF_VERSION_STR "\nCompiled on "
+- __DATE__ " at " __TIME__;
+-#else
+-static const char brcmf_version[] =
+- "Dongle Host Driver, version " BRCMF_VERSION_STR;
+-#endif
+-
+
+ bool brcmf_c_prec_enq(struct device *dev, struct pktq *q,
+ struct sk_buff *pkt, int prec)
+@@ -257,8 +248,6 @@
+ u8 buf[BRCMF_DCMD_SMLEN];
+ char *ptr;
+ s32 err;
+- struct brcmf_bus_dcmd *cmdlst;
+- struct list_head *cur, *q;
+
+ /* retreive mac address */
+ err = brcmf_fil_iovar_data_get(ifp, "cur_etheraddr", ifp->mac_addr,
+@@ -281,9 +270,14 @@
+ }
+ ptr = (char *)buf;
+ strsep(&ptr, "\n");
++
+ /* Print fw version info */
+ brcmf_err("Firmware version = %s\n", buf);
+
++ /* locate firmware version number for ethtool */
++ ptr = strrchr(buf, ' ') + 1;
++ strlcpy(ifp->drvr->fwver, ptr, sizeof(ifp->drvr->fwver));
++
+ /*
+ * Setup timeout if Beacons are lost and roam is off to report
+ * link down
+@@ -342,17 +336,8 @@
+ brcmf_c_pktfilter_offload_enable(ifp, BRCMF_DEFAULT_PACKET_FILTER,
+ 0, true);
+
+- /* set bus specific command if there is any */
+- list_for_each_safe(cur, q, &ifp->drvr->bus_if->dcmd_list) {
+- cmdlst = list_entry(cur, struct brcmf_bus_dcmd, list);
+- if (cmdlst->name && cmdlst->param && cmdlst->param_len) {
+- brcmf_fil_iovar_data_set(ifp, cmdlst->name,
+- cmdlst->param,
+- cmdlst->param_len);
+- }
+- list_del(cur);
+- kfree(cmdlst);
+- }
++ /* do bus specific preinit here */
++ err = brcmf_bus_preinit(ifp->drvr->bus_if);
+ done:
+ return err;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.c 2014-05-15 20:34:00.554032284 +0200
+@@ -22,7 +22,6 @@
+ #include "dhd.h"
+ #include "dhd_bus.h"
+ #include "dhd_dbg.h"
+-#include "tracepoint.h"
+
+ static struct dentry *root_folder;
+
+@@ -42,6 +41,40 @@
+ root_folder = NULL;
+ }
+
++static
++ssize_t brcmf_debugfs_chipinfo_read(struct file *f, char __user *data,
++ size_t count, loff_t *ppos)
++{
++ struct brcmf_pub *drvr = f->private_data;
++ struct brcmf_bus *bus = drvr->bus_if;
++ char buf[40];
++ int res;
++
++ /* only allow read from start */
++ if (*ppos > 0)
++ return 0;
++
++ res = scnprintf(buf, sizeof(buf), "chip: %x(%u) rev %u\n",
++ bus->chip, bus->chip, bus->chiprev);
++ return simple_read_from_buffer(data, count, ppos, buf, res);
++}
++
++static const struct file_operations brcmf_debugfs_chipinfo_ops = {
++ .owner = THIS_MODULE,
++ .open = simple_open,
++ .read = brcmf_debugfs_chipinfo_read
++};
++
++static int brcmf_debugfs_create_chipinfo(struct brcmf_pub *drvr)
++{
++ struct dentry *dentry = drvr->dbgfs_dir;
++
++ if (!IS_ERR_OR_NULL(dentry))
++ debugfs_create_file("chipinfo", S_IRUGO, dentry, drvr,
++ &brcmf_debugfs_chipinfo_ops);
++ return 0;
++}
++
+ int brcmf_debugfs_attach(struct brcmf_pub *drvr)
+ {
+ struct device *dev = drvr->bus_if->dev;
+@@ -50,7 +83,8 @@
+ return -ENODEV;
+
+ drvr->dbgfs_dir = debugfs_create_dir(dev_name(dev), root_folder);
+- return PTR_RET(drvr->dbgfs_dir);
++ brcmf_debugfs_create_chipinfo(drvr);
++ return PTR_ERR_OR_ZERO(drvr->dbgfs_dir);
+ }
+
+ void brcmf_debugfs_detach(struct brcmf_pub *drvr)
+@@ -156,8 +190,11 @@
+ "txs_suppr_core: %u\n"
+ "txs_suppr_ps: %u\n"
+ "txs_tossed: %u\n"
++ "txs_host_tossed: %u\n"
++ "bus_flow_block: %u\n"
++ "fws_flow_block: %u\n"
+ "send_pkts: BK:%u BE:%u VO:%u VI:%u BCMC:%u\n"
+- "fifo_credits_sent: BK:%u BE:%u VO:%u VI:%u BCMC:%u\n",
++ "requested_sent: BK:%u BE:%u VO:%u VI:%u BCMC:%u\n",
+ fwstats->header_pulls,
+ fwstats->header_only_pkt,
+ fwstats->tlv_parse_failed,
+@@ -176,14 +213,17 @@
+ fwstats->txs_supp_core,
+ fwstats->txs_supp_ps,
+ fwstats->txs_tossed,
++ fwstats->txs_host_tossed,
++ fwstats->bus_flow_block,
++ fwstats->fws_flow_block,
+ fwstats->send_pkts[0], fwstats->send_pkts[1],
+ fwstats->send_pkts[2], fwstats->send_pkts[3],
+ fwstats->send_pkts[4],
+- fwstats->fifo_credits_sent[0],
+- fwstats->fifo_credits_sent[1],
+- fwstats->fifo_credits_sent[2],
+- fwstats->fifo_credits_sent[3],
+- fwstats->fifo_credits_sent[4]);
++ fwstats->requested_sent[0],
++ fwstats->requested_sent[1],
++ fwstats->requested_sent[2],
++ fwstats->requested_sent[3],
++ fwstats->requested_sent[4]);
+
+ return simple_read_from_buffer(data, count, ppos, buf, res);
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h 2014-05-15 20:34:00.554032284 +0200
+@@ -33,7 +33,7 @@
+ #define BRCMF_USB_VAL 0x00002000
+ #define BRCMF_SCAN_VAL 0x00004000
+ #define BRCMF_CONN_VAL 0x00008000
+-#define BRCMF_CDC_VAL 0x00010000
++#define BRCMF_BCDC_VAL 0x00010000
+ #define BRCMF_SDIO_VAL 0x00020000
+
+ /* set default print format */
+@@ -141,8 +141,7 @@
+ u32 header_pulls;
+ u32 pkt2bus;
+ u32 send_pkts[5];
+- u32 fifo_credits_sent[5];
+- u32 fifo_credits_back[6];
++ u32 requested_sent[5];
+ u32 generic_error;
+ u32 mac_update_failed;
+ u32 mac_ps_update_failed;
+@@ -158,6 +157,9 @@
+ u32 txs_supp_core;
+ u32 txs_supp_ps;
+ u32 txs_tossed;
++ u32 txs_host_tossed;
++ u32 bus_flow_block;
++ u32 fws_flow_block;
+ };
+
+ struct brcmf_pub;
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd.h 2014-05-15 20:34:00.554032284 +0200
+@@ -21,479 +21,33 @@
+ #ifndef _BRCMF_H_
+ #define _BRCMF_H_
+
+-#define BRCMF_VERSION_STR "4.218.248.5"
+-
+ #include "fweh.h"
+
+-/*******************************************************************************
+- * IO codes that are interpreted by dongle firmware
+- ******************************************************************************/
+-#define BRCMF_C_GET_VERSION 1
+-#define BRCMF_C_UP 2
+-#define BRCMF_C_DOWN 3
+-#define BRCMF_C_SET_PROMISC 10
+-#define BRCMF_C_GET_RATE 12
+-#define BRCMF_C_GET_INFRA 19
+-#define BRCMF_C_SET_INFRA 20
+-#define BRCMF_C_GET_AUTH 21
+-#define BRCMF_C_SET_AUTH 22
+-#define BRCMF_C_GET_BSSID 23
+-#define BRCMF_C_GET_SSID 25
+-#define BRCMF_C_SET_SSID 26
+-#define BRCMF_C_TERMINATED 28
+-#define BRCMF_C_GET_CHANNEL 29
+-#define BRCMF_C_SET_CHANNEL 30
+-#define BRCMF_C_GET_SRL 31
+-#define BRCMF_C_SET_SRL 32
+-#define BRCMF_C_GET_LRL 33
+-#define BRCMF_C_SET_LRL 34
+-#define BRCMF_C_GET_RADIO 37
+-#define BRCMF_C_SET_RADIO 38
+-#define BRCMF_C_GET_PHYTYPE 39
+-#define BRCMF_C_SET_KEY 45
+-#define BRCMF_C_SET_PASSIVE_SCAN 49
+-#define BRCMF_C_SCAN 50
+-#define BRCMF_C_SCAN_RESULTS 51
+-#define BRCMF_C_DISASSOC 52
+-#define BRCMF_C_REASSOC 53
+-#define BRCMF_C_SET_ROAM_TRIGGER 55
+-#define BRCMF_C_SET_ROAM_DELTA 57
+-#define BRCMF_C_GET_BCNPRD 75
+-#define BRCMF_C_SET_BCNPRD 76
+-#define BRCMF_C_GET_DTIMPRD 77
+-#define BRCMF_C_SET_DTIMPRD 78
+-#define BRCMF_C_SET_COUNTRY 84
+-#define BRCMF_C_GET_PM 85
+-#define BRCMF_C_SET_PM 86
+-#define BRCMF_C_GET_CURR_RATESET 114
+-#define BRCMF_C_GET_AP 117
+-#define BRCMF_C_SET_AP 118
+-#define BRCMF_C_GET_RSSI 127
+-#define BRCMF_C_GET_WSEC 133
+-#define BRCMF_C_SET_WSEC 134
+-#define BRCMF_C_GET_PHY_NOISE 135
+-#define BRCMF_C_GET_BSS_INFO 136
+-#define BRCMF_C_GET_BANDLIST 140
+-#define BRCMF_C_SET_SCB_TIMEOUT 158
+-#define BRCMF_C_GET_PHYLIST 180
+-#define BRCMF_C_SET_SCAN_CHANNEL_TIME 185
+-#define BRCMF_C_SET_SCAN_UNASSOC_TIME 187
+-#define BRCMF_C_SCB_DEAUTHENTICATE_FOR_REASON 201
+-#define BRCMF_C_GET_VALID_CHANNELS 217
+-#define BRCMF_C_GET_KEY_PRIMARY 235
+-#define BRCMF_C_SET_KEY_PRIMARY 236
+-#define BRCMF_C_SET_SCAN_PASSIVE_TIME 258
+-#define BRCMF_C_GET_VAR 262
+-#define BRCMF_C_SET_VAR 263
+-
+-/* phy types (returned by WLC_GET_PHYTPE) */
+-#define WLC_PHY_TYPE_A 0
+-#define WLC_PHY_TYPE_B 1
+-#define WLC_PHY_TYPE_G 2
+-#define WLC_PHY_TYPE_N 4
+-#define WLC_PHY_TYPE_LP 5
+-#define WLC_PHY_TYPE_SSN 6
+-#define WLC_PHY_TYPE_HT 7
+-#define WLC_PHY_TYPE_LCN 8
+-#define WLC_PHY_TYPE_NULL 0xf
+-
+-#define BRCMF_EVENTING_MASK_LEN 16
+-
+ #define TOE_TX_CSUM_OL 0x00000001
+ #define TOE_RX_CSUM_OL 0x00000002
+
+-#define BRCMF_BSS_INFO_VERSION 109 /* curr ver of brcmf_bss_info_le struct */
+-
+-/* size of brcmf_scan_params not including variable length array */
+-#define BRCMF_SCAN_PARAMS_FIXED_SIZE 64
+-
+-/* masks for channel and ssid count */
+-#define BRCMF_SCAN_PARAMS_COUNT_MASK 0x0000ffff
+-#define BRCMF_SCAN_PARAMS_NSSID_SHIFT 16
+-
+-/* primary (ie tx) key */
+-#define BRCMF_PRIMARY_KEY (1 << 1)
+-
+ /* For supporting multiple interfaces */
+ #define BRCMF_MAX_IFS 16
+
+-#define DOT11_BSSTYPE_ANY 2
+ #define DOT11_MAX_DEFAULT_KEYS 4
+
+-#define BRCMF_ESCAN_REQ_VERSION 1
+-
+-#define WLC_BSS_RSSI_ON_CHANNEL 0x0002
+-
+-#define BRCMF_MAXRATES_IN_SET 16 /* max # of rates in rateset */
+-#define BRCMF_STA_ASSOC 0x10 /* Associated */
+-
+-#define BRCMF_E_STATUS_SUCCESS 0
+-#define BRCMF_E_STATUS_FAIL 1
+-#define BRCMF_E_STATUS_TIMEOUT 2
+-#define BRCMF_E_STATUS_NO_NETWORKS 3
+-#define BRCMF_E_STATUS_ABORT 4
+-#define BRCMF_E_STATUS_NO_ACK 5
+-#define BRCMF_E_STATUS_UNSOLICITED 6
+-#define BRCMF_E_STATUS_ATTEMPT 7
+-#define BRCMF_E_STATUS_PARTIAL 8
+-#define BRCMF_E_STATUS_NEWSCAN 9
+-#define BRCMF_E_STATUS_NEWASSOC 10
+-#define BRCMF_E_STATUS_11HQUIET 11
+-#define BRCMF_E_STATUS_SUPPRESS 12
+-#define BRCMF_E_STATUS_NOCHANS 13
+-#define BRCMF_E_STATUS_CS_ABORT 15
+-#define BRCMF_E_STATUS_ERROR 16
+-
+-#define BRCMF_E_REASON_INITIAL_ASSOC 0
+-#define BRCMF_E_REASON_LOW_RSSI 1
+-#define BRCMF_E_REASON_DEAUTH 2
+-#define BRCMF_E_REASON_DISASSOC 3
+-#define BRCMF_E_REASON_BCNS_LOST 4
+-#define BRCMF_E_REASON_MINTXRATE 9
+-#define BRCMF_E_REASON_TXFAIL 10
+-
+-#define BRCMF_E_REASON_LINK_BSSCFG_DIS 4
+-#define BRCMF_E_REASON_FAST_ROAM_FAILED 5
+-#define BRCMF_E_REASON_DIRECTED_ROAM 6
+-#define BRCMF_E_REASON_TSPEC_REJECTED 7
+-#define BRCMF_E_REASON_BETTER_AP 8
+-
+-#define BRCMF_E_PRUNE_ENCR_MISMATCH 1
+-#define BRCMF_E_PRUNE_BCAST_BSSID 2
+-#define BRCMF_E_PRUNE_MAC_DENY 3
+-#define BRCMF_E_PRUNE_MAC_NA 4
+-#define BRCMF_E_PRUNE_REG_PASSV 5
+-#define BRCMF_E_PRUNE_SPCT_MGMT 6
+-#define BRCMF_E_PRUNE_RADAR 7
+-#define BRCMF_E_RSN_MISMATCH 8
+-#define BRCMF_E_PRUNE_NO_COMMON_RATES 9
+-#define BRCMF_E_PRUNE_BASIC_RATES 10
+-#define BRCMF_E_PRUNE_CIPHER_NA 12
+-#define BRCMF_E_PRUNE_KNOWN_STA 13
+-#define BRCMF_E_PRUNE_WDS_PEER 15
+-#define BRCMF_E_PRUNE_QBSS_LOAD 16
+-#define BRCMF_E_PRUNE_HOME_AP 17
+-
+-#define BRCMF_E_SUP_OTHER 0
+-#define BRCMF_E_SUP_DECRYPT_KEY_DATA 1
+-#define BRCMF_E_SUP_BAD_UCAST_WEP128 2
+-#define BRCMF_E_SUP_BAD_UCAST_WEP40 3
+-#define BRCMF_E_SUP_UNSUP_KEY_LEN 4
+-#define BRCMF_E_SUP_PW_KEY_CIPHER 5
+-#define BRCMF_E_SUP_MSG3_TOO_MANY_IE 6
+-#define BRCMF_E_SUP_MSG3_IE_MISMATCH 7
+-#define BRCMF_E_SUP_NO_INSTALL_FLAG 8
+-#define BRCMF_E_SUP_MSG3_NO_GTK 9
+-#define BRCMF_E_SUP_GRP_KEY_CIPHER 10
+-#define BRCMF_E_SUP_GRP_MSG1_NO_GTK 11
+-#define BRCMF_E_SUP_GTK_DECRYPT_FAIL 12
+-#define BRCMF_E_SUP_SEND_FAIL 13
+-#define BRCMF_E_SUP_DEAUTH 14
+-
+-#define BRCMF_E_IF_ADD 1
+-#define BRCMF_E_IF_DEL 2
+-#define BRCMF_E_IF_CHANGE 3
+-
+-#define BRCMF_E_IF_ROLE_STA 0
+-#define BRCMF_E_IF_ROLE_AP 1
+-#define BRCMF_E_IF_ROLE_WDS 2
+-
+-#define BRCMF_E_LINK_BCN_LOSS 1
+-#define BRCMF_E_LINK_DISASSOC 2
+-#define BRCMF_E_LINK_ASSOC_REC 3
+-#define BRCMF_E_LINK_BSSCFG_DIS 4
+-
+ /* Small, medium and maximum buffer size for dcmd
+ */
+ #define BRCMF_DCMD_SMLEN 256
+ #define BRCMF_DCMD_MEDLEN 1536
+ #define BRCMF_DCMD_MAXLEN 8192
+
+-/* Pattern matching filter. Specifies an offset within received packets to
+- * start matching, the pattern to match, the size of the pattern, and a bitmask
+- * that indicates which bits within the pattern should be matched.
+- */
+-struct brcmf_pkt_filter_pattern_le {
+- /*
+- * Offset within received packet to start pattern matching.
+- * Offset '0' is the first byte of the ethernet header.
+- */
+- __le32 offset;
+- /* Size of the pattern. Bitmask must be the same size.*/
+- __le32 size_bytes;
+- /*
+- * Variable length mask and pattern data. mask starts at offset 0.
+- * Pattern immediately follows mask.
+- */
+- u8 mask_and_pattern[1];
+-};
+-
+-/* IOVAR "pkt_filter_add" parameter. Used to install packet filters. */
+-struct brcmf_pkt_filter_le {
+- __le32 id; /* Unique filter id, specified by app. */
+- __le32 type; /* Filter type (WL_PKT_FILTER_TYPE_xxx). */
+- __le32 negate_match; /* Negate the result of filter matches */
+- union { /* Filter definitions */
+- struct brcmf_pkt_filter_pattern_le pattern; /* Filter pattern */
+- } u;
+-};
+-
+-/* IOVAR "pkt_filter_enable" parameter. */
+-struct brcmf_pkt_filter_enable_le {
+- __le32 id; /* Unique filter id */
+- __le32 enable; /* Enable/disable bool */
+-};
+-
+-/* BSS info structure
+- * Applications MUST CHECK ie_offset field and length field to access IEs and
+- * next bss_info structure in a vector (in struct brcmf_scan_results)
+- */
+-struct brcmf_bss_info_le {
+- __le32 version; /* version field */
+- __le32 length; /* byte length of data in this record,
+- * starting at version and including IEs
+- */
+- u8 BSSID[ETH_ALEN];
+- __le16 beacon_period; /* units are Kusec */
+- __le16 capability; /* Capability information */
+- u8 SSID_len;
+- u8 SSID[32];
+- struct {
+- __le32 count; /* # rates in this set */
+- u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
+- } rateset; /* supported rates */
+- __le16 chanspec; /* chanspec for bss */
+- __le16 atim_window; /* units are Kusec */
+- u8 dtim_period; /* DTIM period */
+- __le16 RSSI; /* receive signal strength (in dBm) */
+- s8 phy_noise; /* noise (in dBm) */
+-
+- u8 n_cap; /* BSS is 802.11N Capable */
+- /* 802.11N BSS Capabilities (based on HT_CAP_*): */
+- __le32 nbss_cap;
+- u8 ctl_ch; /* 802.11N BSS control channel number */
+- __le32 reserved32[1]; /* Reserved for expansion of BSS properties */
+- u8 flags; /* flags */
+- u8 reserved[3]; /* Reserved for expansion of BSS properties */
+- u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */
+-
+- __le16 ie_offset; /* offset at which IEs start, from beginning */
+- __le32 ie_length; /* byte length of Information Elements */
+- __le16 SNR; /* average SNR of during frame reception */
+- /* Add new fields here */
+- /* variable length Information Elements */
+-};
+-
+-struct brcm_rateset_le {
+- /* # rates in this set */
+- __le32 count;
+- /* rates in 500kbps units w/hi bit set if basic */
+- u8 rates[BRCMF_MAXRATES_IN_SET];
+-};
+-
+-struct brcmf_ssid {
+- u32 SSID_len;
+- unsigned char SSID[32];
+-};
+-
+-struct brcmf_ssid_le {
+- __le32 SSID_len;
+- unsigned char SSID[32];
+-};
+-
+-struct brcmf_scan_params_le {
+- struct brcmf_ssid_le ssid_le; /* default: {0, ""} */
+- u8 bssid[ETH_ALEN]; /* default: bcast */
+- s8 bss_type; /* default: any,
+- * DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT
+- */
+- u8 scan_type; /* flags, 0 use default */
+- __le32 nprobes; /* -1 use default, number of probes per channel */
+- __le32 active_time; /* -1 use default, dwell time per channel for
+- * active scanning
+- */
+- __le32 passive_time; /* -1 use default, dwell time per channel
+- * for passive scanning
+- */
+- __le32 home_time; /* -1 use default, dwell time for the
+- * home channel between channel scans
+- */
+- __le32 channel_num; /* count of channels and ssids that follow
+- *
+- * low half is count of channels in
+- * channel_list, 0 means default (use all
+- * available channels)
+- *
+- * high half is entries in struct brcmf_ssid
+- * array that follows channel_list, aligned for
+- * s32 (4 bytes) meaning an odd channel count
+- * implies a 2-byte pad between end of
+- * channel_list and first ssid
+- *
+- * if ssid count is zero, single ssid in the
+- * fixed parameter portion is assumed, otherwise
+- * ssid in the fixed portion is ignored
+- */
+- __le16 channel_list[1]; /* list of chanspecs */
+-};
+-
+-struct brcmf_scan_results {
+- u32 buflen;
+- u32 version;
+- u32 count;
+- struct brcmf_bss_info_le bss_info_le[];
+-};
+-
+-struct brcmf_escan_params_le {
+- __le32 version;
+- __le16 action;
+- __le16 sync_id;
+- struct brcmf_scan_params_le params_le;
+-};
+-
+-struct brcmf_escan_result_le {
+- __le32 buflen;
+- __le32 version;
+- __le16 sync_id;
+- __le16 bss_count;
+- struct brcmf_bss_info_le bss_info_le;
+-};
+-
+-#define WL_ESCAN_RESULTS_FIXED_SIZE (sizeof(struct brcmf_escan_result_le) - \
+- sizeof(struct brcmf_bss_info_le))
+-
+-/* used for association with a specific BSSID and chanspec list */
+-struct brcmf_assoc_params_le {
+- /* 00:00:00:00:00:00: broadcast scan */
+- u8 bssid[ETH_ALEN];
+- /* 0: all available channels, otherwise count of chanspecs in
+- * chanspec_list */
+- __le32 chanspec_num;
+- /* list of chanspecs */
+- __le16 chanspec_list[1];
+-};
+-
+-/* used for join with or without a specific bssid and channel list */
+-struct brcmf_join_params {
+- struct brcmf_ssid_le ssid_le;
+- struct brcmf_assoc_params_le params_le;
+-};
+-
+-/* scan params for extended join */
+-struct brcmf_join_scan_params_le {
+- u8 scan_type; /* 0 use default, active or passive scan */
+- __le32 nprobes; /* -1 use default, nr of probes per channel */
+- __le32 active_time; /* -1 use default, dwell time per channel for
+- * active scanning
+- */
+- __le32 passive_time; /* -1 use default, dwell time per channel
+- * for passive scanning
+- */
+- __le32 home_time; /* -1 use default, dwell time for the home
+- * channel between channel scans
+- */
+-};
+-
+-/* extended join params */
+-struct brcmf_ext_join_params_le {
+- struct brcmf_ssid_le ssid_le; /* {0, ""}: wildcard scan */
+- struct brcmf_join_scan_params_le scan_le;
+- struct brcmf_assoc_params_le assoc_le;
+-};
+-
+-struct brcmf_wsec_key {
+- u32 index; /* key index */
+- u32 len; /* key length */
+- u8 data[WLAN_MAX_KEY_LEN]; /* key data */
+- u32 pad_1[18];
+- u32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
+- u32 flags; /* misc flags */
+- u32 pad_2[3];
+- u32 iv_initialized; /* has IV been initialized already? */
+- u32 pad_3;
+- /* Rx IV */
+- struct {
+- u32 hi; /* upper 32 bits of IV */
+- u16 lo; /* lower 16 bits of IV */
+- } rxiv;
+- u32 pad_4[2];
+- u8 ea[ETH_ALEN]; /* per station */
+-};
+-
+-/*
+- * dongle requires same struct as above but with fields in little endian order
++/* IOCTL from host to device are limited in lenght. A device can only handle
++ * ethernet frame size. This limitation is to be applied by protocol layer.
+ */
+-struct brcmf_wsec_key_le {
+- __le32 index; /* key index */
+- __le32 len; /* key length */
+- u8 data[WLAN_MAX_KEY_LEN]; /* key data */
+- __le32 pad_1[18];
+- __le32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
+- __le32 flags; /* misc flags */
+- __le32 pad_2[3];
+- __le32 iv_initialized; /* has IV been initialized already? */
+- __le32 pad_3;
+- /* Rx IV */
+- struct {
+- __le32 hi; /* upper 32 bits of IV */
+- __le16 lo; /* lower 16 bits of IV */
+- } rxiv;
+- __le32 pad_4[2];
+- u8 ea[ETH_ALEN]; /* per station */
+-};
+-
+-/* Used to get specific STA parameters */
+-struct brcmf_scb_val_le {
+- __le32 val;
+- u8 ea[ETH_ALEN];
+-};
+-
+-/* channel encoding */
+-struct brcmf_channel_info_le {
+- __le32 hw_channel;
+- __le32 target_channel;
+- __le32 scan_channel;
+-};
+-
+-struct brcmf_sta_info_le {
+- __le16 ver; /* version of this struct */
+- __le16 len; /* length in bytes of this structure */
+- __le16 cap; /* sta's advertised capabilities */
+- __le32 flags; /* flags defined below */
+- __le32 idle; /* time since data pkt rx'd from sta */
+- u8 ea[ETH_ALEN]; /* Station address */
+- __le32 count; /* # rates in this set */
+- u8 rates[BRCMF_MAXRATES_IN_SET]; /* rates in 500kbps units */
+- /* w/hi bit set if basic */
+- __le32 in; /* seconds elapsed since associated */
+- __le32 listen_interval_inms; /* Min Listen interval in ms for STA */
+- __le32 tx_pkts; /* # of packets transmitted */
+- __le32 tx_failures; /* # of packets failed */
+- __le32 rx_ucast_pkts; /* # of unicast packets received */
+- __le32 rx_mcast_pkts; /* # of multicast packets received */
+- __le32 tx_rate; /* Rate of last successful tx frame */
+- __le32 rx_rate; /* Rate of last successful rx frame */
+- __le32 rx_decrypt_succeeds; /* # of packet decrypted successfully */
+- __le32 rx_decrypt_failures; /* # of packet decrypted failed */
+-};
++#define BRCMF_TX_IOCTL_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
+
+-struct brcmf_chanspec_list {
+- __le32 count; /* # of entries */
+- __le32 element[1]; /* variable length uint32 list */
+-};
++#define BRCMF_AMPDU_RX_REORDER_MAXFLOWS 256
+
+-/*
+- * WLC_E_PROBRESP_MSG
+- * WLC_E_P2P_PROBREQ_MSG
+- * WLC_E_ACTION_FRAME_RX
++/* Length of firmware version string stored for
++ * ethtool driver info which uses 32 bytes as well.
+ */
+-struct brcmf_rx_mgmt_data {
+- __be16 version;
+- __be16 chanspec;
+- __be32 rssi;
+- __be32 mactime;
+- __be32 rate;
+-};
++#define BRCMF_DRIVER_FIRMWARE_VERSION_LEN 32
+
+ /* Bus independent dongle command */
+ struct brcmf_dcmd {
+@@ -505,6 +59,25 @@
+ uint needed; /* bytes needed (optional) */
+ };
+
++/**
++ * struct brcmf_ampdu_rx_reorder - AMPDU receive reorder info
++ *
++ * @pktslots: dynamic allocated array for ordering AMPDU packets.
++ * @flow_id: AMPDU flow identifier.
++ * @cur_idx: last AMPDU index from firmware.
++ * @exp_idx: expected next AMPDU index.
++ * @max_idx: maximum amount of packets per AMPDU.
++ * @pend_pkts: number of packets currently in @pktslots.
++ */
++struct brcmf_ampdu_rx_reorder {
++ struct sk_buff **pktslots;
++ u8 flow_id;
++ u8 cur_idx;
++ u8 exp_idx;
++ u8 max_idx;
++ u8 pend_pkts;
++};
++
+ /* Forward decls for struct brcmf_pub (see below) */
+ struct brcmf_proto; /* device communication protocol info */
+ struct brcmf_cfg80211_dev; /* cfg80211 device info */
+@@ -514,7 +87,7 @@
+ struct brcmf_pub {
+ /* Linkage ponters */
+ struct brcmf_bus *bus_if;
+- struct brcmf_proto *prot;
++ struct brcmf_proto *proto;
+ struct brcmf_cfg80211_info *config;
+
+ /* Internal brcmf items */
+@@ -523,7 +96,7 @@
+ u8 wme_dp; /* wme discard priority */
+
+ /* Dongle media info */
+- unsigned long drv_version; /* Version of dongle-resident driver */
++ char fwver[BRCMF_DRIVER_FIRMWARE_VERSION_LEN];
+ u8 mac[ETH_ALEN]; /* MAC address obtained from dongle */
+
+ /* Multicast data packets sent to dongle */
+@@ -536,22 +109,15 @@
+
+ struct brcmf_fweh_info fweh;
+
+- bool fw_signals;
+ struct brcmf_fws_info *fws;
+- spinlock_t fws_spinlock;
++
++ struct brcmf_ampdu_rx_reorder
++ *reorder_flows[BRCMF_AMPDU_RX_REORDER_MAXFLOWS];
+ #ifdef DEBUG
+ struct dentry *dbgfs_dir;
+ #endif
+ };
+
+-struct brcmf_if_event {
+- u8 ifidx;
+- u8 action;
+- u8 flags;
+- u8 bssidx;
+- u8 role;
+-};
+-
+ /* forward declarations */
+ struct brcmf_cfg80211_vif;
+ struct brcmf_fws_mac_descriptor;
+@@ -583,6 +149,7 @@
+ * @bssidx: index of bss associated with this interface.
+ * @mac_addr: assigned mac address.
+ * @netif_stop: bitmap indicates reason why netif queues are stopped.
++ * @netif_stop_lock: spinlock for update netif_stop from multiple sources.
+ * @pend_8021x_cnt: tracks outstanding number of 802.1x frames.
+ * @pend_8021x_wait: used for signalling change in count.
+ */
+@@ -598,34 +165,31 @@
+ s32 bssidx;
+ u8 mac_addr[ETH_ALEN];
+ u8 netif_stop;
++ spinlock_t netif_stop_lock;
+ atomic_t pend_8021x_cnt;
+ wait_queue_head_t pend_8021x_wait;
+ };
+
++struct brcmf_skb_reorder_data {
++ u8 *reorder;
++};
+
+-extern int brcmf_netdev_wait_pend8021x(struct net_device *ndev);
++int brcmf_netdev_wait_pend8021x(struct net_device *ndev);
+
+ /* Return pointer to interface name */
+-extern char *brcmf_ifname(struct brcmf_pub *drvr, int idx);
++char *brcmf_ifname(struct brcmf_pub *drvr, int idx);
+
+-/* Query dongle */
+-extern int brcmf_proto_cdc_query_dcmd(struct brcmf_pub *drvr, int ifidx,
+- uint cmd, void *buf, uint len);
+-extern int brcmf_proto_cdc_set_dcmd(struct brcmf_pub *drvr, int ifidx, uint cmd,
+- void *buf, uint len);
+-
+-/* Remove any protocol-specific data header. */
+-extern int brcmf_proto_hdrpull(struct brcmf_pub *drvr, bool do_fws, u8 *ifidx,
+- struct sk_buff *rxp);
+-
+-extern int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked);
+-extern struct brcmf_if *brcmf_add_if(struct brcmf_pub *drvr, s32 bssidx,
+- s32 ifidx, char *name, u8 *mac_addr);
+-extern void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx);
++int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked);
++struct brcmf_if *brcmf_add_if(struct brcmf_pub *drvr, s32 bssidx, s32 ifidx,
++ char *name, u8 *mac_addr);
++void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx);
+ void brcmf_txflowblock_if(struct brcmf_if *ifp,
+ enum brcmf_netif_stop_reason reason, bool state);
+-extern u32 brcmf_get_chip_info(struct brcmf_if *ifp);
+-extern void brcmf_txfinalize(struct brcmf_pub *drvr, struct sk_buff *txp,
+- bool success);
++u32 brcmf_get_chip_info(struct brcmf_if *ifp);
++void brcmf_txfinalize(struct brcmf_pub *drvr, struct sk_buff *txp,
++ bool success);
++
++/* Sets dongle media info (drv_version, mac address). */
++int brcmf_c_preinit_dcmds(struct brcmf_if *ifp);
+
+ #endif /* _BRCMF_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c 2014-05-15 20:34:00.554032284 +0200
+@@ -24,13 +24,13 @@
+
+ #include "dhd.h"
+ #include "dhd_bus.h"
+-#include "dhd_proto.h"
+ #include "dhd_dbg.h"
+ #include "fwil_types.h"
+ #include "p2p.h"
+ #include "wl_cfg80211.h"
+ #include "fwil.h"
+ #include "fwsignal.h"
++#include "proto.h"
+
+ MODULE_AUTHOR("Broadcom Corporation");
+ MODULE_DESCRIPTION("Broadcom 802.11 wireless LAN fullmac driver.");
+@@ -38,6 +38,19 @@
+
+ #define MAX_WAIT_FOR_8021X_TX 50 /* msecs */
+
++/* AMPDU rx reordering definitions */
++#define BRCMF_RXREORDER_FLOWID_OFFSET 0
++#define BRCMF_RXREORDER_MAXIDX_OFFSET 2
++#define BRCMF_RXREORDER_FLAGS_OFFSET 4
++#define BRCMF_RXREORDER_CURIDX_OFFSET 6
++#define BRCMF_RXREORDER_EXPIDX_OFFSET 8
++
++#define BRCMF_RXREORDER_DEL_FLOW 0x01
++#define BRCMF_RXREORDER_FLUSH_ALL 0x02
++#define BRCMF_RXREORDER_CURIDX_VALID 0x04
++#define BRCMF_RXREORDER_EXPIDX_VALID 0x08
++#define BRCMF_RXREORDER_NEW_HOLE 0x10
++
+ /* Error bits */
+ int brcmf_msg_level;
+ module_param_named(debug, brcmf_msg_level, int, S_IRUSR | S_IWUSR);
+@@ -179,7 +192,7 @@
+ struct brcmf_pub *drvr = ifp->drvr;
+ struct ethhdr *eh;
+
+- brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
++ brcmf_dbg(DATA, "Enter, idx=%d\n", ifp->bssidx);
+
+ /* Can the device send data? */
+ if (drvr->bus_if->state != BRCMF_BUS_DATA) {
+@@ -240,11 +253,15 @@
+ void brcmf_txflowblock_if(struct brcmf_if *ifp,
+ enum brcmf_netif_stop_reason reason, bool state)
+ {
+- if (!ifp)
++ unsigned long flags;
++
++ if (!ifp || !ifp->ndev)
+ return;
+
+ brcmf_dbg(TRACE, "enter: idx=%d stop=0x%X reason=%d state=%d\n",
+ ifp->bssidx, ifp->netif_stop, reason, state);
++
++ spin_lock_irqsave(&ifp->netif_stop_lock, flags);
+ if (state) {
+ if (!ifp->netif_stop)
+ netif_stop_queue(ifp->ndev);
+@@ -254,97 +271,271 @@
+ if (!ifp->netif_stop)
+ netif_wake_queue(ifp->ndev);
+ }
++ spin_unlock_irqrestore(&ifp->netif_stop_lock, flags);
+ }
+
+ void brcmf_txflowblock(struct device *dev, bool state)
+ {
+ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+ struct brcmf_pub *drvr = bus_if->drvr;
+- int i;
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+- for (i = 0; i < BRCMF_MAX_IFS; i++)
+- brcmf_txflowblock_if(drvr->iflist[i],
+- BRCMF_NETIF_STOP_REASON_BLOCK_BUS, state);
++ brcmf_fws_bus_blocked(drvr, state);
+ }
+
+-void brcmf_rx_frames(struct device *dev, struct sk_buff_head *skb_list)
++static void brcmf_netif_rx(struct brcmf_if *ifp, struct sk_buff *skb)
+ {
+- unsigned char *eth;
+- uint len;
+- struct sk_buff *skb, *pnext;
+- struct brcmf_if *ifp;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+- u8 ifidx;
+- int ret;
++ skb->dev = ifp->ndev;
++ skb->protocol = eth_type_trans(skb, skb->dev);
+
+- brcmf_dbg(TRACE, "Enter\n");
++ if (skb->pkt_type == PACKET_MULTICAST)
++ ifp->stats.multicast++;
++
++ /* Process special event packets */
++ brcmf_fweh_process_skb(ifp->drvr, skb);
++
++ if (!(ifp->ndev->flags & IFF_UP)) {
++ brcmu_pkt_buf_free_skb(skb);
++ return;
++ }
+
+- skb_queue_walk_safe(skb_list, skb, pnext) {
+- skb_unlink(skb, skb_list);
++ ifp->stats.rx_bytes += skb->len;
++ ifp->stats.rx_packets++;
+
+- /* process and remove protocol-specific header */
+- ret = brcmf_proto_hdrpull(drvr, drvr->fw_signals, &ifidx, skb);
+- ifp = drvr->iflist[ifidx];
+-
+- if (ret || !ifp || !ifp->ndev) {
+- if ((ret != -ENODATA) && ifp)
+- ifp->stats.rx_errors++;
+- brcmu_pkt_buf_free_skb(skb);
+- continue;
+- }
+-
+- /* Get the protocol, maintain skb around eth_type_trans()
+- * The main reason for this hack is for the limitation of
+- * Linux 2.4 where 'eth_type_trans' uses the
+- * 'net->hard_header_len'
+- * to perform skb_pull inside vs ETH_HLEN. Since to avoid
+- * coping of the packet coming from the network stack to add
+- * BDC, Hardware header etc, during network interface
+- * registration
+- * we set the 'net->hard_header_len' to ETH_HLEN + extra space
+- * required
+- * for BDC, Hardware header etc. and not just the ETH_HLEN
++ brcmf_dbg(DATA, "rx proto=0x%X\n", ntohs(skb->protocol));
++ if (in_interrupt())
++ netif_rx(skb);
++ else
++ /* If the receive is not processed inside an ISR,
++ * the softirqd must be woken explicitly to service
++ * the NET_RX_SOFTIRQ. This is handled by netif_rx_ni().
+ */
+- eth = skb->data;
+- len = skb->len;
++ netif_rx_ni(skb);
++}
+
+- skb->dev = ifp->ndev;
+- skb->protocol = eth_type_trans(skb, skb->dev);
++static void brcmf_rxreorder_get_skb_list(struct brcmf_ampdu_rx_reorder *rfi,
++ u8 start, u8 end,
++ struct sk_buff_head *skb_list)
++{
++ /* initialize return list */
++ __skb_queue_head_init(skb_list);
+
+- if (skb->pkt_type == PACKET_MULTICAST)
+- ifp->stats.multicast++;
++ if (rfi->pend_pkts == 0) {
++ brcmf_dbg(INFO, "no packets in reorder queue\n");
++ return;
++ }
+
+- skb->data = eth;
+- skb->len = len;
++ do {
++ if (rfi->pktslots[start]) {
++ __skb_queue_tail(skb_list, rfi->pktslots[start]);
++ rfi->pktslots[start] = NULL;
++ }
++ start++;
++ if (start > rfi->max_idx)
++ start = 0;
++ } while (start != end);
++ rfi->pend_pkts -= skb_queue_len(skb_list);
++}
++
++static void brcmf_rxreorder_process_info(struct brcmf_if *ifp, u8 *reorder_data,
++ struct sk_buff *pkt)
++{
++ u8 flow_id, max_idx, cur_idx, exp_idx, end_idx;
++ struct brcmf_ampdu_rx_reorder *rfi;
++ struct sk_buff_head reorder_list;
++ struct sk_buff *pnext;
++ u8 flags;
++ u32 buf_size;
++
++ flow_id = reorder_data[BRCMF_RXREORDER_FLOWID_OFFSET];
++ flags = reorder_data[BRCMF_RXREORDER_FLAGS_OFFSET];
++
++ /* validate flags and flow id */
++ if (flags == 0xFF) {
++ brcmf_err("invalid flags...so ignore this packet\n");
++ brcmf_netif_rx(ifp, pkt);
++ return;
++ }
+
+- /* Strip header, count, deliver upward */
+- skb_pull(skb, ETH_HLEN);
++ rfi = ifp->drvr->reorder_flows[flow_id];
++ if (flags & BRCMF_RXREORDER_DEL_FLOW) {
++ brcmf_dbg(INFO, "flow-%d: delete\n",
++ flow_id);
++
++ if (rfi == NULL) {
++ brcmf_dbg(INFO, "received flags to cleanup, but no flow (%d) yet\n",
++ flow_id);
++ brcmf_netif_rx(ifp, pkt);
++ return;
++ }
+
+- /* Process special event packets */
+- brcmf_fweh_process_skb(drvr, skb);
++ brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, rfi->exp_idx,
++ &reorder_list);
++ /* add the last packet */
++ __skb_queue_tail(&reorder_list, pkt);
++ kfree(rfi);
++ ifp->drvr->reorder_flows[flow_id] = NULL;
++ goto netif_rx;
++ }
++ /* from here on we need a flow reorder instance */
++ if (rfi == NULL) {
++ buf_size = sizeof(*rfi);
++ max_idx = reorder_data[BRCMF_RXREORDER_MAXIDX_OFFSET];
++
++ buf_size += (max_idx + 1) * sizeof(pkt);
++
++ /* allocate space for flow reorder info */
++ brcmf_dbg(INFO, "flow-%d: start, maxidx %d\n",
++ flow_id, max_idx);
++ rfi = kzalloc(buf_size, GFP_ATOMIC);
++ if (rfi == NULL) {
++ brcmf_err("failed to alloc buffer\n");
++ brcmf_netif_rx(ifp, pkt);
++ return;
++ }
+
+- if (!(ifp->ndev->flags & IFF_UP)) {
+- brcmu_pkt_buf_free_skb(skb);
+- continue;
++ ifp->drvr->reorder_flows[flow_id] = rfi;
++ rfi->pktslots = (struct sk_buff **)(rfi+1);
++ rfi->max_idx = max_idx;
++ }
++ if (flags & BRCMF_RXREORDER_NEW_HOLE) {
++ if (rfi->pend_pkts) {
++ brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx,
++ rfi->exp_idx,
++ &reorder_list);
++ WARN_ON(rfi->pend_pkts);
++ } else {
++ __skb_queue_head_init(&reorder_list);
+ }
++ rfi->cur_idx = reorder_data[BRCMF_RXREORDER_CURIDX_OFFSET];
++ rfi->exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
++ rfi->max_idx = reorder_data[BRCMF_RXREORDER_MAXIDX_OFFSET];
++ rfi->pktslots[rfi->cur_idx] = pkt;
++ rfi->pend_pkts++;
++ brcmf_dbg(DATA, "flow-%d: new hole %d (%d), pending %d\n",
++ flow_id, rfi->cur_idx, rfi->exp_idx, rfi->pend_pkts);
++ } else if (flags & BRCMF_RXREORDER_CURIDX_VALID) {
++ cur_idx = reorder_data[BRCMF_RXREORDER_CURIDX_OFFSET];
++ exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
++
++ if ((exp_idx == rfi->exp_idx) && (cur_idx != rfi->exp_idx)) {
++ /* still in the current hole */
++ /* enqueue the current on the buffer chain */
++ if (rfi->pktslots[cur_idx] != NULL) {
++ brcmf_dbg(INFO, "HOLE: ERROR buffer pending..free it\n");
++ brcmu_pkt_buf_free_skb(rfi->pktslots[cur_idx]);
++ rfi->pktslots[cur_idx] = NULL;
++ }
++ rfi->pktslots[cur_idx] = pkt;
++ rfi->pend_pkts++;
++ rfi->cur_idx = cur_idx;
++ brcmf_dbg(DATA, "flow-%d: store pkt %d (%d), pending %d\n",
++ flow_id, cur_idx, exp_idx, rfi->pend_pkts);
+
+- ifp->stats.rx_bytes += skb->len;
+- ifp->stats.rx_packets++;
++ /* can return now as there is no reorder
++ * list to process.
++ */
++ return;
++ }
++ if (rfi->exp_idx == cur_idx) {
++ if (rfi->pktslots[cur_idx] != NULL) {
++ brcmf_dbg(INFO, "error buffer pending..free it\n");
++ brcmu_pkt_buf_free_skb(rfi->pktslots[cur_idx]);
++ rfi->pktslots[cur_idx] = NULL;
++ }
++ rfi->pktslots[cur_idx] = pkt;
++ rfi->pend_pkts++;
+
+- if (in_interrupt())
+- netif_rx(skb);
+- else
+- /* If the receive is not processed inside an ISR,
+- * the softirqd must be woken explicitly to service
+- * the NET_RX_SOFTIRQ. In 2.6 kernels, this is handled
+- * by netif_rx_ni(), but in earlier kernels, we need
+- * to do it manually.
++ /* got the expected one. flush from current to expected
++ * and update expected
+ */
+- netif_rx_ni(skb);
++ brcmf_dbg(DATA, "flow-%d: expected %d (%d), pending %d\n",
++ flow_id, cur_idx, exp_idx, rfi->pend_pkts);
++
++ rfi->cur_idx = cur_idx;
++ rfi->exp_idx = exp_idx;
++
++ brcmf_rxreorder_get_skb_list(rfi, cur_idx, exp_idx,
++ &reorder_list);
++ brcmf_dbg(DATA, "flow-%d: freeing buffers %d, pending %d\n",
++ flow_id, skb_queue_len(&reorder_list),
++ rfi->pend_pkts);
++ } else {
++ u8 end_idx;
++
++ brcmf_dbg(DATA, "flow-%d (0x%x): both moved, old %d/%d, new %d/%d\n",
++ flow_id, flags, rfi->cur_idx, rfi->exp_idx,
++ cur_idx, exp_idx);
++ if (flags & BRCMF_RXREORDER_FLUSH_ALL)
++ end_idx = rfi->exp_idx;
++ else
++ end_idx = exp_idx;
++
++ /* flush pkts first */
++ brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, end_idx,
++ &reorder_list);
++
++ if (exp_idx == ((cur_idx + 1) % (rfi->max_idx + 1))) {
++ __skb_queue_tail(&reorder_list, pkt);
++ } else {
++ rfi->pktslots[cur_idx] = pkt;
++ rfi->pend_pkts++;
++ }
++ rfi->exp_idx = exp_idx;
++ rfi->cur_idx = cur_idx;
++ }
++ } else {
++ /* explicity window move updating the expected index */
++ exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
++
++ brcmf_dbg(DATA, "flow-%d (0x%x): change expected: %d -> %d\n",
++ flow_id, flags, rfi->exp_idx, exp_idx);
++ if (flags & BRCMF_RXREORDER_FLUSH_ALL)
++ end_idx = rfi->exp_idx;
++ else
++ end_idx = exp_idx;
++
++ brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, end_idx,
++ &reorder_list);
++ __skb_queue_tail(&reorder_list, pkt);
++ /* set the new expected idx */
++ rfi->exp_idx = exp_idx;
++ }
++netif_rx:
++ skb_queue_walk_safe(&reorder_list, pkt, pnext) {
++ __skb_unlink(pkt, &reorder_list);
++ brcmf_netif_rx(ifp, pkt);
++ }
++}
++
++void brcmf_rx_frame(struct device *dev, struct sk_buff *skb)
++{
++ struct brcmf_if *ifp;
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++ struct brcmf_skb_reorder_data *rd;
++ u8 ifidx;
++ int ret;
++
++ brcmf_dbg(DATA, "Enter: %s: rxp=%p\n", dev_name(dev), skb);
++
++ /* process and remove protocol-specific header */
++ ret = brcmf_proto_hdrpull(drvr, true, &ifidx, skb);
++ ifp = drvr->iflist[ifidx];
++
++ if (ret || !ifp || !ifp->ndev) {
++ if ((ret != -ENODATA) && ifp)
++ ifp->stats.rx_errors++;
++ brcmu_pkt_buf_free_skb(skb);
++ return;
+ }
++
++ rd = (struct brcmf_skb_reorder_data *)skb->cb;
++ if (rd->reorder)
++ brcmf_rxreorder_process_info(ifp, rd->reorder, skb);
++ else
++ brcmf_netif_rx(ifp, skb);
+ }
+
+ void brcmf_txfinalize(struct brcmf_pub *drvr, struct sk_buff *txp,
+@@ -401,28 +592,6 @@
+ return &ifp->stats;
+ }
+
+-/*
+- * Set current toe component enables in toe_ol iovar,
+- * and set toe global enable iovar
+- */
+-static int brcmf_toe_set(struct brcmf_if *ifp, u32 toe_ol)
+-{
+- s32 err;
+-
+- err = brcmf_fil_iovar_int_set(ifp, "toe_ol", toe_ol);
+- if (err < 0) {
+- brcmf_err("Setting toe_ol failed, %d\n", err);
+- return err;
+- }
+-
+- err = brcmf_fil_iovar_int_set(ifp, "toe", (toe_ol != 0));
+- if (err < 0)
+- brcmf_err("Setting toe failed, %d\n", err);
+-
+- return err;
+-
+-}
+-
+ static void brcmf_ethtool_get_drvinfo(struct net_device *ndev,
+ struct ethtool_drvinfo *info)
+ {
+@@ -430,8 +599,8 @@
+ struct brcmf_pub *drvr = ifp->drvr;
+
+ strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
+- snprintf(info->version, sizeof(info->version), "%lu",
+- drvr->drv_version);
++ snprintf(info->version, sizeof(info->version), "n/a");
++ strlcpy(info->fw_version, drvr->fwver, sizeof(info->fw_version));
+ strlcpy(info->bus_info, dev_name(drvr->bus_if->dev),
+ sizeof(info->bus_info));
+ }
+@@ -440,124 +609,6 @@
+ .get_drvinfo = brcmf_ethtool_get_drvinfo,
+ };
+
+-static int brcmf_ethtool(struct brcmf_if *ifp, void __user *uaddr)
+-{
+- struct brcmf_pub *drvr = ifp->drvr;
+- struct ethtool_drvinfo info;
+- char drvname[sizeof(info.driver)];
+- u32 cmd;
+- struct ethtool_value edata;
+- u32 toe_cmpnt, csum_dir;
+- int ret;
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
+-
+- /* all ethtool calls start with a cmd word */
+- if (copy_from_user(&cmd, uaddr, sizeof(u32)))
+- return -EFAULT;
+-
+- switch (cmd) {
+- case ETHTOOL_GDRVINFO:
+- /* Copy out any request driver name */
+- if (copy_from_user(&info, uaddr, sizeof(info)))
+- return -EFAULT;
+- strncpy(drvname, info.driver, sizeof(info.driver));
+- drvname[sizeof(info.driver) - 1] = '\0';
+-
+- /* clear struct for return */
+- memset(&info, 0, sizeof(info));
+- info.cmd = cmd;
+-
+- /* if requested, identify ourselves */
+- if (strcmp(drvname, "?dhd") == 0) {
+- sprintf(info.driver, "dhd");
+- strcpy(info.version, BRCMF_VERSION_STR);
+- }
+- /* report dongle driver type */
+- else
+- sprintf(info.driver, "wl");
+-
+- sprintf(info.version, "%lu", drvr->drv_version);
+- if (copy_to_user(uaddr, &info, sizeof(info)))
+- return -EFAULT;
+- brcmf_dbg(TRACE, "given %*s, returning %s\n",
+- (int)sizeof(drvname), drvname, info.driver);
+- break;
+-
+- /* Get toe offload components from dongle */
+- case ETHTOOL_GRXCSUM:
+- case ETHTOOL_GTXCSUM:
+- ret = brcmf_fil_iovar_int_get(ifp, "toe_ol", &toe_cmpnt);
+- if (ret < 0)
+- return ret;
+-
+- csum_dir =
+- (cmd == ETHTOOL_GTXCSUM) ? TOE_TX_CSUM_OL : TOE_RX_CSUM_OL;
+-
+- edata.cmd = cmd;
+- edata.data = (toe_cmpnt & csum_dir) ? 1 : 0;
+-
+- if (copy_to_user(uaddr, &edata, sizeof(edata)))
+- return -EFAULT;
+- break;
+-
+- /* Set toe offload components in dongle */
+- case ETHTOOL_SRXCSUM:
+- case ETHTOOL_STXCSUM:
+- if (copy_from_user(&edata, uaddr, sizeof(edata)))
+- return -EFAULT;
+-
+- /* Read the current settings, update and write back */
+- ret = brcmf_fil_iovar_int_get(ifp, "toe_ol", &toe_cmpnt);
+- if (ret < 0)
+- return ret;
+-
+- csum_dir =
+- (cmd == ETHTOOL_STXCSUM) ? TOE_TX_CSUM_OL : TOE_RX_CSUM_OL;
+-
+- if (edata.data != 0)
+- toe_cmpnt |= csum_dir;
+- else
+- toe_cmpnt &= ~csum_dir;
+-
+- ret = brcmf_toe_set(ifp, toe_cmpnt);
+- if (ret < 0)
+- return ret;
+-
+- /* If setting TX checksum mode, tell Linux the new mode */
+- if (cmd == ETHTOOL_STXCSUM) {
+- if (edata.data)
+- ifp->ndev->features |= NETIF_F_IP_CSUM;
+- else
+- ifp->ndev->features &= ~NETIF_F_IP_CSUM;
+- }
+-
+- break;
+-
+- default:
+- return -EOPNOTSUPP;
+- }
+-
+- return 0;
+-}
+-
+-static int brcmf_netdev_ioctl_entry(struct net_device *ndev, struct ifreq *ifr,
+- int cmd)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_pub *drvr = ifp->drvr;
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d, cmd=0x%04x\n", ifp->bssidx, cmd);
+-
+- if (!drvr->iflist[ifp->bssidx])
+- return -1;
+-
+- if (cmd == SIOCETHTOOL)
+- return brcmf_ethtool(ifp, ifr->ifr_data);
+-
+- return -EOPNOTSUPP;
+-}
+-
+ static int brcmf_netdev_stop(struct net_device *ndev)
+ {
+ struct brcmf_if *ifp = netdev_priv(ndev);
+@@ -578,7 +629,6 @@
+ struct brcmf_pub *drvr = ifp->drvr;
+ struct brcmf_bus *bus_if = drvr->bus_if;
+ u32 toe_ol;
+- s32 ret = 0;
+
+ brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
+
+@@ -597,21 +647,20 @@
+ else
+ ndev->features &= ~NETIF_F_IP_CSUM;
+
+- /* Allow transmit calls */
+- netif_start_queue(ndev);
+ if (brcmf_cfg80211_up(ndev)) {
+ brcmf_err("failed to bring up cfg80211\n");
+- return -1;
++ return -EIO;
+ }
+
+- return ret;
++ /* Allow transmit calls */
++ netif_start_queue(ndev);
++ return 0;
+ }
+
+ static const struct net_device_ops brcmf_netdev_ops_pri = {
+ .ndo_open = brcmf_netdev_open,
+ .ndo_stop = brcmf_netdev_stop,
+ .ndo_get_stats = brcmf_netdev_get_stats,
+- .ndo_do_ioctl = brcmf_netdev_ioctl_entry,
+ .ndo_start_xmit = brcmf_netdev_start_xmit,
+ .ndo_set_mac_address = brcmf_netdev_set_mac_address,
+ .ndo_set_rx_mode = brcmf_netdev_set_multicast_list
+@@ -630,7 +679,7 @@
+ /* set appropriate operations */
+ ndev->netdev_ops = &brcmf_netdev_ops_pri;
+
+- ndev->hard_header_len = ETH_HLEN + drvr->hdrlen;
++ ndev->hard_header_len += drvr->hdrlen;
+ ndev->ethtool_ops = &brcmf_ethtool_ops;
+
+ drvr->rxsz = ndev->mtu + ndev->hard_header_len +
+@@ -653,7 +702,7 @@
+
+ brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
+
+- ndev->destructor = free_netdev;
++ ndev->destructor = brcmf_cfg80211_free_netdev;
+ return 0;
+
+ fail:
+@@ -677,13 +726,6 @@
+ return brcmf_cfg80211_down(ndev);
+ }
+
+-static int brcmf_net_p2p_do_ioctl(struct net_device *ndev,
+- struct ifreq *ifr, int cmd)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+- return 0;
+-}
+-
+ static netdev_tx_t brcmf_net_p2p_start_xmit(struct sk_buff *skb,
+ struct net_device *ndev)
+ {
+@@ -696,7 +738,6 @@
+ static const struct net_device_ops brcmf_netdev_ops_p2p = {
+ .ndo_open = brcmf_net_p2p_open,
+ .ndo_stop = brcmf_net_p2p_stop,
+- .ndo_do_ioctl = brcmf_net_p2p_do_ioctl,
+ .ndo_start_xmit = brcmf_net_p2p_start_xmit
+ };
+
+@@ -779,6 +820,7 @@
+ ifp->bssidx = bssidx;
+
+ init_waitqueue_head(&ifp->pend_8021x_wait);
++ spin_lock_init(&ifp->netif_stop_lock);
+
+ if (mac_addr != NULL)
+ memcpy(ifp->mac_addr, mac_addr, ETH_ALEN);
+@@ -817,14 +859,12 @@
+ }
+ /* unregister will take care of freeing it */
+ unregister_netdev(ifp->ndev);
+- if (bssidx == 0)
+- brcmf_cfg80211_detach(drvr->config);
+ } else {
+ kfree(ifp);
+ }
+ }
+
+-int brcmf_attach(uint bus_hdrlen, struct device *dev)
++int brcmf_attach(struct device *dev)
+ {
+ struct brcmf_pub *drvr = NULL;
+ int ret = 0;
+@@ -839,7 +879,7 @@
+ mutex_init(&drvr->proto_block);
+
+ /* Link to bus module */
+- drvr->hdrlen = bus_hdrlen;
++ drvr->hdrlen = 0;
+ drvr->bus_if = dev_get_drvdata(dev);
+ drvr->bus_if->drvr = drvr;
+
+@@ -856,8 +896,6 @@
+ /* attach firmware event handler */
+ brcmf_fweh_attach(drvr);
+
+- INIT_LIST_HEAD(&drvr->bus_if->dcmd_list);
+-
+ return ret;
+
+ fail:
+@@ -896,14 +934,13 @@
+ p2p_ifp = NULL;
+
+ /* signal bus ready */
+- bus_if->state = BRCMF_BUS_DATA;
++ brcmf_bus_change_state(bus_if, BRCMF_BUS_DATA);
+
+ /* Bus is ready, do any initialization */
+ ret = brcmf_c_preinit_dcmds(ifp);
+ if (ret < 0)
+ goto fail;
+
+- drvr->fw_signals = true;
+ ret = brcmf_fws_init(drvr);
+ if (ret < 0)
+ goto fail;
+@@ -924,8 +961,7 @@
+ fail:
+ if (ret < 0) {
+ brcmf_err("failed: %d\n", ret);
+- if (drvr->config)
+- brcmf_cfg80211_detach(drvr->config);
++ brcmf_cfg80211_detach(drvr->config);
+ if (drvr->fws) {
+ brcmf_fws_del_interface(ifp);
+ brcmf_fws_deinit(drvr);
+@@ -947,14 +983,21 @@
+ return 0;
+ }
+
++void brcmf_bus_add_txhdrlen(struct device *dev, uint len)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++
++ if (drvr) {
++ drvr->hdrlen += len;
++ }
++}
++
+ static void brcmf_bus_detach(struct brcmf_pub *drvr)
+ {
+ brcmf_dbg(TRACE, "Enter\n");
+
+ if (drvr) {
+- /* Stop the protocol module */
+- brcmf_proto_stop(drvr);
+-
+ /* Stop the bus module */
+ brcmf_bus_stop(drvr->bus_if);
+ }
+@@ -986,6 +1029,8 @@
+ /* stop firmware event handling */
+ brcmf_fweh_detach(drvr);
+
++ brcmf_bus_change_state(bus_if, BRCMF_BUS_DOWN);
++
+ /* make sure primary interface removed last */
+ for (i = BRCMF_MAX_IFS-1; i > -1; i--)
+ if (drvr->iflist[i]) {
+@@ -993,10 +1038,11 @@
+ brcmf_del_if(drvr, i);
+ }
+
++ brcmf_cfg80211_detach(drvr->config);
++
+ brcmf_bus_detach(drvr);
+
+- if (drvr->prot)
+- brcmf_proto_detach(drvr);
++ brcmf_proto_detach(drvr);
+
+ brcmf_fws_deinit(drvr);
+
+@@ -1005,6 +1051,14 @@
+ kfree(drvr);
+ }
+
++s32 brcmf_iovar_data_set(struct device *dev, char *name, void *data, u32 len)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_if *ifp = bus_if->drvr->iflist[0];
++
++ return brcmf_fil_iovar_data_set(ifp, name, data, len);
++}
++
+ static int brcmf_get_pend_8021x_cnt(struct brcmf_if *ifp)
+ {
+ return atomic_read(&ifp->pend_8021x_cnt);
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_proto.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_proto.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_proto.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_proto.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,42 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#ifndef _BRCMF_PROTO_H_
+-#define _BRCMF_PROTO_H_
+-
+-/*
+- * Exported from the brcmf protocol module (brcmf_cdc)
+- */
+-
+-/* Linkage, sets prot link and updates hdrlen in pub */
+-extern int brcmf_proto_attach(struct brcmf_pub *drvr);
+-
+-/* Unlink, frees allocated protocol memory (including brcmf_proto) */
+-extern void brcmf_proto_detach(struct brcmf_pub *drvr);
+-
+-/* Stop protocol: sync w/dongle state. */
+-extern void brcmf_proto_stop(struct brcmf_pub *drvr);
+-
+-/* Add any protocol-specific data header.
+- * Caller must reserve prot_hdrlen prepend space.
+- */
+-extern void brcmf_proto_hdrpush(struct brcmf_pub *, int ifidx, u8 offset,
+- struct sk_buff *txp);
+-
+-/* Sets dongle media info (drv_version, mac address). */
+-extern int brcmf_c_preinit_dcmds(struct brcmf_if *ifp);
+-
+-#endif /* _BRCMF_PROTO_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c 2014-05-15 20:34:00.554032284 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/debugfs.h>
+ #include <linux/vmalloc.h>
+ #include <linux/platform_data/brcmfmac-sdio.h>
++#include <linux/moduleparam.h>
+ #include <asm/unaligned.h>
+ #include <defs.h>
+ #include <brcmu_wifi.h>
+@@ -40,6 +41,7 @@
+ #include <soc.h>
+ #include "sdio_host.h"
+ #include "sdio_chip.h"
++#include "nvram.h"
+
+ #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
+
+@@ -110,6 +112,8 @@
+ #define BRCMF_TXBOUND 20 /* Default for max tx frames in
+ one scheduling */
+
++#define BRCMF_DEFAULT_TXGLOM_SIZE 32 /* max tx frames in glom chain */
++
+ #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
+
+ #define MEMBLOCK 2048 /* Block size used for downloading
+@@ -201,13 +205,6 @@
+ #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
+ #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
+
+-/* HW frame tag */
+-#define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
+-
+-/* Total length of frame header for dongle protocol */
+-#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
+-#define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
+-
+ /*
+ * Software allocation of To SB Mailbox resources
+ */
+@@ -250,38 +247,6 @@
+ /* Current protocol version */
+ #define SDPCM_PROT_VERSION 4
+
+-/* SW frame header */
+-#define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
+-
+-#define SDPCM_CHANNEL_MASK 0x00000f00
+-#define SDPCM_CHANNEL_SHIFT 8
+-#define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
+-
+-#define SDPCM_NEXTLEN_OFFSET 2
+-
+-/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
+-#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
+-#define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
+-#define SDPCM_DOFFSET_MASK 0xff000000
+-#define SDPCM_DOFFSET_SHIFT 24
+-#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
+-#define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
+-#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
+-#define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
+-
+-#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
+-
+-/* logical channel numbers */
+-#define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
+-#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
+-#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
+-#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
+-#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
+-
+-#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
+-
+-#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
+-
+ /*
+ * Shared structure between dongle and the host.
+ * The structure contains pointers to trap or assert information.
+@@ -296,9 +261,6 @@
+ #define MAX_HDR_READ (1 << 6)
+ #define MAX_RX_DATASZ 2048
+
+-/* Maximum milliseconds to wait for F2 to come up */
+-#define BRCMF_WAIT_F2RDY 3000
+-
+ /* Bump up limit on waiting for HT to account for first startup;
+ * if the image is doing a CRC calculation before programming the PMU
+ * for HT availability, it could take a couple hundred ms more, so
+@@ -314,11 +276,6 @@
+ /* Flags for SDH calls */
+ #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
+
+-#define BRCMF_SDIO_FW_NAME "brcm/brcmfmac-sdio.bin"
+-#define BRCMF_SDIO_NV_NAME "brcm/brcmfmac-sdio.txt"
+-MODULE_FIRMWARE(BRCMF_SDIO_FW_NAME);
+-MODULE_FIRMWARE(BRCMF_SDIO_NV_NAME);
+-
+ #define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */
+ #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
+ * when idle
+@@ -396,23 +353,23 @@
+ __le32 brpt_addr;
+ };
+
+-/* SDIO read frame info */
+-struct brcmf_sdio_read {
++/* dongle SDIO bus specific header info */
++struct brcmf_sdio_hdrinfo {
+ u8 seq_num;
+ u8 channel;
+ u16 len;
+ u16 len_left;
+ u16 len_nxtfrm;
+ u8 dat_offset;
++ bool lastfrm;
++ u16 tail_pad;
+ };
+
+ /* misc chip info needed by some of the routines */
+ /* Private data for SDIO bus interaction */
+ struct brcmf_sdio {
+ struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
+- struct chip_info *ci; /* Chip info struct */
+- char *vars; /* Variables (from CIS and/or other) */
+- uint varsz; /* Size of variables buffer */
++ struct brcmf_chip *ci; /* Chip info struct */
+
+ u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
+
+@@ -428,10 +385,10 @@
+ u8 tx_seq; /* Transmit sequence number (next) */
+ u8 tx_max; /* Maximum transmit sequence allowed */
+
+- u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
++ u8 *hdrbuf; /* buffer for handling rx frame */
+ u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
+ u8 rx_seq; /* Receive sequence number (expected) */
+- struct brcmf_sdio_read cur_read;
++ struct brcmf_sdio_hdrinfo cur_read;
+ /* info of current read frame */
+ bool rxskip; /* Skip receive (awaiting NAK ACK) */
+ bool rxpending; /* Data frame pending in dongle */
+@@ -448,8 +405,6 @@
+ uint rxblen; /* Allocated length of rxbuf */
+ u8 *rxctl; /* Aligned pointer into rxbuf */
+ u8 *rxctl_orig; /* pointer for freeing rxctl */
+- u8 *databuf; /* Buffer for receiving big glom packet */
+- u8 *dataptr; /* Aligned pointer into databuf */
+ uint rxlen; /* Length of valid data in buffer */
+ spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
+
+@@ -473,8 +428,6 @@
+ s32 idletime; /* Control for activity timeout */
+ s32 idlecount; /* Activity timeout counter */
+ s32 idleclock; /* How to set bus driver when idle */
+- s32 sd_rxchain;
+- bool use_rxchain; /* If brcmf should use PKT chains */
+ bool rxflow_mode; /* Rx flow control mode */
+ bool rxflow; /* Is rx flow control on */
+ bool alp_only; /* Don't use HT clock (ALP only) */
+@@ -495,16 +448,18 @@
+
+ struct workqueue_struct *brcmf_wq;
+ struct work_struct datawork;
+- struct list_head dpc_tsklst;
+- spinlock_t dpc_tl_lock;
+-
+- const struct firmware *firmware;
+- u32 fw_ptr;
++ atomic_t dpc_tskcnt;
+
+ bool txoff; /* Transmit flow-controlled */
+ struct brcmf_sdio_count sdcnt;
+ bool sr_enabled; /* SaveRestore enabled */
+ bool sleeping; /* SDIO bus sleeping */
++
++ u8 tx_hdrlen; /* sdio bus header length for tx packet */
++ bool txglom; /* host tx glomming enable flag */
++ struct sk_buff *txglom_sgpad; /* scatter-gather padding buffer */
++ u16 head_align; /* buffer pointer alignment */
++ u16 sgentry_align; /* scatter-gather buffer alignment */
+ };
+
+ /* clkstate */
+@@ -515,7 +470,6 @@
+
+ #ifdef DEBUG
+ static int qcount[NUMPRIO];
+-static int tx_packets[NUMPRIO];
+ #endif /* DEBUG */
+
+ #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
+@@ -530,12 +484,120 @@
+
+ #define ALIGNMENT 4
+
++static int brcmf_sdio_txglomsz = BRCMF_DEFAULT_TXGLOM_SIZE;
++module_param_named(txglomsz, brcmf_sdio_txglomsz, int, 0);
++MODULE_PARM_DESC(txglomsz, "maximum tx packet chain size [SDIO]");
++
+ enum brcmf_sdio_frmtype {
+ BRCMF_SDIO_FT_NORMAL,
+ BRCMF_SDIO_FT_SUPER,
+ BRCMF_SDIO_FT_SUB,
+ };
+
++#define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
++#define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
++#define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
++#define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
++#define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
++#define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
++#define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
++#define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
++#define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
++#define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
++#define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
++#define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
++#define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
++#define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
++#define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
++#define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
++#define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
++#define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
++
++MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
++
++struct brcmf_firmware_names {
++ u32 chipid;
++ u32 revmsk;
++ const char *bin;
++ const char *nv;
++};
++
++enum brcmf_firmware_type {
++ BRCMF_FIRMWARE_BIN,
++ BRCMF_FIRMWARE_NVRAM
++};
++
++#define BRCMF_FIRMWARE_NVRAM(name) \
++ name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
++
++static const struct brcmf_firmware_names brcmf_fwname_data[] = {
++ { BCM43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
++ { BCM43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
++ { BCM43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
++ { BCM4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
++ { BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
++ { BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
++ { BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
++ { BCM43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
++ { BCM4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }
++};
++
++
++static const struct firmware *brcmf_sdio_get_fw(struct brcmf_sdio *bus,
++ enum brcmf_firmware_type type)
++{
++ const struct firmware *fw;
++ const char *name;
++ int err, i;
++
++ for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
++ if (brcmf_fwname_data[i].chipid == bus->ci->chip &&
++ brcmf_fwname_data[i].revmsk & BIT(bus->ci->chiprev)) {
++ switch (type) {
++ case BRCMF_FIRMWARE_BIN:
++ name = brcmf_fwname_data[i].bin;
++ break;
++ case BRCMF_FIRMWARE_NVRAM:
++ name = brcmf_fwname_data[i].nv;
++ break;
++ default:
++ brcmf_err("invalid firmware type (%d)\n", type);
++ return NULL;
++ }
++ goto found;
++ }
++ }
++ brcmf_err("Unknown chipid %d [%d]\n",
++ bus->ci->chip, bus->ci->chiprev);
++ return NULL;
++
++found:
++ err = request_firmware(&fw, name, &bus->sdiodev->func[2]->dev);
++ if ((err) || (!fw)) {
++ brcmf_err("fail to request firmware %s (%d)\n", name, err);
++ return NULL;
++ }
++
++ return fw;
++}
++
+ static void pkt_align(struct sk_buff *p, int len, int align)
+ {
+ uint datalign;
+@@ -563,8 +625,8 @@
+ u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
+ int ret;
+
+- *regvar = brcmf_sdio_regrl(bus->sdiodev,
+- bus->ci->c_inf[idx].base + offset, &ret);
++ *regvar = brcmf_sdiod_regrl(bus->sdiodev,
++ bus->ci->c_inf[idx].base + offset, &ret);
+
+ return ret;
+ }
+@@ -575,15 +637,15 @@
+ u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
+ int ret;
+
+- brcmf_sdio_regwl(bus->sdiodev,
+- bus->ci->c_inf[idx].base + reg_offset,
+- regval, &ret);
++ brcmf_sdiod_regwl(bus->sdiodev,
++ bus->ci->c_inf[idx].base + reg_offset,
++ regval, &ret);
+
+ return ret;
+ }
+
+ static int
+-brcmf_sdbrcm_kso_control(struct brcmf_sdio *bus, bool on)
++brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
+ {
+ u8 wr_val = 0, rd_val, cmp_val, bmask;
+ int err = 0;
+@@ -593,8 +655,8 @@
+
+ wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
+ /* 1st KSO write goes to AOS wake up core if device is asleep */
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- wr_val, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
++ wr_val, &err);
+ if (err) {
+ brcmf_err("SDIO_AOS KSO write error: %d\n", err);
+ return err;
+@@ -624,15 +686,15 @@
+ * just one write attempt may fail,
+ * read it back until it matches written value
+ */
+- rd_val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- &err);
++ rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
++ &err);
+ if (((rd_val & bmask) == cmp_val) && !err)
+ break;
+ brcmf_dbg(SDIO, "KSO wr/rd retry:%d (max: %d) ERR:%x\n",
+ try_cnt, MAX_KSO_ATTEMPTS, err);
+ udelay(KSO_WAIT_US);
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- wr_val, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
++ wr_val, &err);
+ } while (try_cnt++ < MAX_KSO_ATTEMPTS);
+
+ return err;
+@@ -643,7 +705,7 @@
+ #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
+
+ /* Turn backplane clock on or off */
+-static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
++static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
+ {
+ int err;
+ u8 clkctl, clkreq, devctl;
+@@ -663,16 +725,16 @@
+ clkreq =
+ bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
+
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- clkreq, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ clkreq, &err);
+ if (err) {
+ brcmf_err("HT Avail request error: %d\n", err);
+ return -EBADE;
+ }
+
+ /* Check current status */
+- clkctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
++ clkctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, &err);
+ if (err) {
+ brcmf_err("HT Avail read error: %d\n", err);
+ return -EBADE;
+@@ -681,8 +743,8 @@
+ /* Go to pending and await interrupt if appropriate */
+ if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
+ /* Allow only clock-available interrupt */
+- devctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
+ if (err) {
+ brcmf_err("Devctl error setting CA: %d\n",
+ err);
+@@ -690,28 +752,28 @@
+ }
+
+ devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
+- devctl, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
++ devctl, &err);
+ brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
+ bus->clkstate = CLK_PENDING;
+
+ return 0;
+ } else if (bus->clkstate == CLK_PENDING) {
+ /* Cancel CA-only interrupt filter */
+- devctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
+ devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
+- devctl, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
++ devctl, &err);
+ }
+
+ /* Otherwise, wait here (polling) for HT Avail */
+ timeout = jiffies +
+ msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
+ while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
+- clkctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR,
+- &err);
++ clkctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR,
++ &err);
+ if (time_after(jiffies, timeout))
+ break;
+ else
+@@ -744,16 +806,16 @@
+
+ if (bus->clkstate == CLK_PENDING) {
+ /* Cancel CA-only interrupt filter */
+- devctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
+ devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
+- devctl, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
++ devctl, &err);
+ }
+
+ bus->clkstate = CLK_SDONLY;
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- clkreq, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ clkreq, &err);
+ brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
+ if (err) {
+ brcmf_err("Failed access turning clock off: %d\n",
+@@ -765,7 +827,7 @@
+ }
+
+ /* Change idle/active SD state */
+-static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on)
++static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
+ {
+ brcmf_dbg(SDIO, "Enter\n");
+
+@@ -778,7 +840,7 @@
+ }
+
+ /* Transition SD and backplane clock readiness */
+-static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
++static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
+ {
+ #ifdef DEBUG
+ uint oldstate = bus->clkstate;
+@@ -789,7 +851,7 @@
+ /* Early exit if we're already there */
+ if (bus->clkstate == target) {
+ if (target == CLK_AVAIL) {
+- brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
++ brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+ bus->activity = true;
+ }
+ return 0;
+@@ -799,32 +861,32 @@
+ case CLK_AVAIL:
+ /* Make sure SD clock is available */
+ if (bus->clkstate == CLK_NONE)
+- brcmf_sdbrcm_sdclk(bus, true);
++ brcmf_sdio_sdclk(bus, true);
+ /* Now request HT Avail on the backplane */
+- brcmf_sdbrcm_htclk(bus, true, pendok);
+- brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
++ brcmf_sdio_htclk(bus, true, pendok);
++ brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+ bus->activity = true;
+ break;
+
+ case CLK_SDONLY:
+ /* Remove HT request, or bring up SD clock */
+ if (bus->clkstate == CLK_NONE)
+- brcmf_sdbrcm_sdclk(bus, true);
++ brcmf_sdio_sdclk(bus, true);
+ else if (bus->clkstate == CLK_AVAIL)
+- brcmf_sdbrcm_htclk(bus, false, false);
++ brcmf_sdio_htclk(bus, false, false);
+ else
+ brcmf_err("request for %d -> %d\n",
+ bus->clkstate, target);
+- brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
++ brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+ break;
+
+ case CLK_NONE:
+ /* Make sure to remove HT request */
+ if (bus->clkstate == CLK_AVAIL)
+- brcmf_sdbrcm_htclk(bus, false, false);
++ brcmf_sdio_htclk(bus, false, false);
+ /* Now remove the SD clock */
+- brcmf_sdbrcm_sdclk(bus, false);
+- brcmf_sdbrcm_wd_timer(bus, 0);
++ brcmf_sdio_sdclk(bus, false);
++ brcmf_sdio_wd_timer(bus, 0);
+ break;
+ }
+ #ifdef DEBUG
+@@ -835,7 +897,7 @@
+ }
+
+ static int
+-brcmf_sdbrcm_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
++brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
+ {
+ int err = 0;
+ brcmf_dbg(TRACE, "Enter\n");
+@@ -858,13 +920,13 @@
+ brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
+ data_ok(bus)))
+ return -EBUSY;
+- err = brcmf_sdbrcm_kso_control(bus, false);
++ err = brcmf_sdio_kso_control(bus, false);
+ /* disable watchdog */
+ if (!err)
+- brcmf_sdbrcm_wd_timer(bus, 0);
++ brcmf_sdio_wd_timer(bus, 0);
+ } else {
+ bus->idlecount = 0;
+- err = brcmf_sdbrcm_kso_control(bus, true);
++ err = brcmf_sdio_kso_control(bus, true);
+ }
+ if (!err) {
+ /* Change state */
+@@ -882,16 +944,16 @@
+ /* control clocks */
+ if (sleep) {
+ if (!bus->sr_enabled)
+- brcmf_sdbrcm_clkctl(bus, CLK_NONE, pendok);
++ brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
+ } else {
+- brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, pendok);
++ brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
+ }
+
+ return err;
+
+ }
+
+-static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus)
++static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
+ {
+ u32 intstatus = 0;
+ u32 hmb_data;
+@@ -967,7 +1029,7 @@
+ return intstatus;
+ }
+
+-static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
++static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
+ {
+ uint retries = 0;
+ u16 lastrbc;
+@@ -979,18 +1041,18 @@
+ rtx ? ", send NAK" : "");
+
+ if (abort)
+- brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
++ brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
+
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
+- SFC_RF_TERM, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
++ SFC_RF_TERM, &err);
+ bus->sdcnt.f1regdata++;
+
+ /* Wait until the packet has been flushed (device/FIFO stable) */
+ for (lastrbc = retries = 0xffff; retries > 0; retries--) {
+- hi = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_RFRAMEBCHI, &err);
+- lo = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_RFRAMEBCLO, &err);
++ hi = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_RFRAMEBCHI, &err);
++ lo = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_RFRAMEBCLO, &err);
+ bus->sdcnt.f1regdata += 2;
+
+ if ((hi == 0) && (lo == 0))
+@@ -1020,37 +1082,10 @@
+
+ /* Clear partial in any case */
+ bus->cur_read.len = 0;
+-
+- /* If we can't reach the device, signal failure */
+- if (err)
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
+-}
+-
+-/* copy a buffer into a pkt buffer chain */
+-static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_sdio *bus, uint len)
+-{
+- uint n, ret = 0;
+- struct sk_buff *p;
+- u8 *buf;
+-
+- buf = bus->dataptr;
+-
+- /* copy the data */
+- skb_queue_walk(&bus->glom, p) {
+- n = min_t(uint, p->len, len);
+- memcpy(p->data, buf, n);
+- buf += n;
+- len -= n;
+- ret += n;
+- if (!len)
+- break;
+- }
+-
+- return ret;
+ }
+
+ /* return total length of buffer chain */
+-static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus)
++static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
+ {
+ struct sk_buff *p;
+ uint total;
+@@ -1061,7 +1096,7 @@
+ return total;
+ }
+
+-static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus)
++static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
+ {
+ struct sk_buff *cur, *next;
+
+@@ -1071,18 +1106,74 @@
+ }
+ }
+
+-static int brcmf_sdio_hdparser(struct brcmf_sdio *bus, u8 *header,
+- struct brcmf_sdio_read *rd,
+- enum brcmf_sdio_frmtype type)
++/**
++ * brcmfmac sdio bus specific header
++ * This is the lowest layer header wrapped on the packets transmitted between
++ * host and WiFi dongle which contains information needed for SDIO core and
++ * firmware
++ *
++ * It consists of 3 parts: hardware header, hardware extension header and
++ * software header
++ * hardware header (frame tag) - 4 bytes
++ * Byte 0~1: Frame length
++ * Byte 2~3: Checksum, bit-wise inverse of frame length
++ * hardware extension header - 8 bytes
++ * Tx glom mode only, N/A for Rx or normal Tx
++ * Byte 0~1: Packet length excluding hw frame tag
++ * Byte 2: Reserved
++ * Byte 3: Frame flags, bit 0: last frame indication
++ * Byte 4~5: Reserved
++ * Byte 6~7: Tail padding length
++ * software header - 8 bytes
++ * Byte 0: Rx/Tx sequence number
++ * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
++ * Byte 2: Length of next data frame, reserved for Tx
++ * Byte 3: Data offset
++ * Byte 4: Flow control bits, reserved for Tx
++ * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
++ * Byte 6~7: Reserved
++ */
++#define SDPCM_HWHDR_LEN 4
++#define SDPCM_HWEXT_LEN 8
++#define SDPCM_SWHDR_LEN 8
++#define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
++/* software header */
++#define SDPCM_SEQ_MASK 0x000000ff
++#define SDPCM_SEQ_WRAP 256
++#define SDPCM_CHANNEL_MASK 0x00000f00
++#define SDPCM_CHANNEL_SHIFT 8
++#define SDPCM_CONTROL_CHANNEL 0 /* Control */
++#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
++#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
++#define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
++#define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
++#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
++#define SDPCM_NEXTLEN_MASK 0x00ff0000
++#define SDPCM_NEXTLEN_SHIFT 16
++#define SDPCM_DOFFSET_MASK 0xff000000
++#define SDPCM_DOFFSET_SHIFT 24
++#define SDPCM_FCMASK_MASK 0x000000ff
++#define SDPCM_WINDOW_MASK 0x0000ff00
++#define SDPCM_WINDOW_SHIFT 8
++
++static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
++{
++ u32 hdrvalue;
++ hdrvalue = *(u32 *)swheader;
++ return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
++}
++
++static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
++ struct brcmf_sdio_hdrinfo *rd,
++ enum brcmf_sdio_frmtype type)
+ {
+ u16 len, checksum;
+ u8 rx_seq, fc, tx_seq_max;
++ u32 swheader;
+
+- /*
+- * 4 bytes hardware header (frame tag)
+- * Byte 0~1: Frame length
+- * Byte 2~3: Checksum, bit-wise inverse of frame length
+- */
++ trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
++
++ /* hw header */
+ len = get_unaligned_le16(header);
+ checksum = get_unaligned_le16(header + sizeof(u16));
+ /* All zero means no more to read */
+@@ -1093,7 +1184,7 @@
+ if ((u16)(~(len ^ checksum))) {
+ brcmf_err("HW header checksum error\n");
+ bus->sdcnt.rx_badhdr++;
+- brcmf_sdbrcm_rxfail(bus, false, false);
++ brcmf_sdio_rxfail(bus, false, false);
+ return -EIO;
+ }
+ if (len < SDPCM_HDRLEN) {
+@@ -1111,29 +1202,21 @@
+ }
+ rd->len = len;
+
+- /*
+- * 8 bytes hardware header
+- * Byte 0: Rx sequence number
+- * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
+- * Byte 2: Length of next data frame
+- * Byte 3: Data offset
+- * Byte 4: Flow control bits
+- * Byte 5: Maximum Sequence number allow for Tx
+- * Byte 6~7: Reserved
+- */
+- if (type == BRCMF_SDIO_FT_SUPER &&
+- SDPCM_GLOMDESC(&header[SDPCM_FRAMETAG_LEN])) {
++ /* software header */
++ header += SDPCM_HWHDR_LEN;
++ swheader = le32_to_cpu(*(__le32 *)header);
++ if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
+ brcmf_err("Glom descriptor found in superframe head\n");
+ rd->len = 0;
+ return -EINVAL;
+ }
+- rx_seq = SDPCM_PACKET_SEQUENCE(&header[SDPCM_FRAMETAG_LEN]);
+- rd->channel = SDPCM_PACKET_CHANNEL(&header[SDPCM_FRAMETAG_LEN]);
++ rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
++ rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
+ if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
+ type != BRCMF_SDIO_FT_SUPER) {
+ brcmf_err("HW header length too long\n");
+ bus->sdcnt.rx_toolong++;
+- brcmf_sdbrcm_rxfail(bus, false, false);
++ brcmf_sdio_rxfail(bus, false, false);
+ rd->len = 0;
+ return -EPROTO;
+ }
+@@ -1148,11 +1231,11 @@
+ rd->len = 0;
+ return -EINVAL;
+ }
+- rd->dat_offset = SDPCM_DOFFSET_VALUE(&header[SDPCM_FRAMETAG_LEN]);
++ rd->dat_offset = brcmf_sdio_getdatoffset(header);
+ if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
+ brcmf_err("seq %d: bad data offset\n", rx_seq);
+ bus->sdcnt.rx_badhdr++;
+- brcmf_sdbrcm_rxfail(bus, false, false);
++ brcmf_sdio_rxfail(bus, false, false);
+ rd->len = 0;
+ return -ENXIO;
+ }
+@@ -1165,14 +1248,15 @@
+ /* no need to check the reset for subframe */
+ if (type == BRCMF_SDIO_FT_SUB)
+ return 0;
+- rd->len_nxtfrm = header[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
++ rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
+ if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
+ /* only warm for NON glom packet */
+ if (rd->channel != SDPCM_GLOM_CHANNEL)
+ brcmf_err("seq %d: next length error\n", rx_seq);
+ rd->len_nxtfrm = 0;
+ }
+- fc = SDPCM_FCMASK_VALUE(&header[SDPCM_FRAMETAG_LEN]);
++ swheader = le32_to_cpu(*(__le32 *)(header + 4));
++ fc = swheader & SDPCM_FCMASK_MASK;
+ if (bus->flowcontrol != fc) {
+ if (~bus->flowcontrol & fc)
+ bus->sdcnt.fc_xoff++;
+@@ -1181,7 +1265,7 @@
+ bus->sdcnt.fc_rcvd++;
+ bus->flowcontrol = fc;
+ }
+- tx_seq_max = SDPCM_WINDOW_VALUE(&header[SDPCM_FRAMETAG_LEN]);
++ tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
+ if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
+ brcmf_err("seq %d: max tx seq number error\n", rx_seq);
+ tx_seq_max = bus->tx_seq + 2;
+@@ -1191,20 +1275,50 @@
+ return 0;
+ }
+
+-static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
++static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
++{
++ *(__le16 *)header = cpu_to_le16(frm_length);
++ *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
++}
++
++static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
++ struct brcmf_sdio_hdrinfo *hd_info)
++{
++ u32 hdrval;
++ u8 hdr_offset;
++
++ brcmf_sdio_update_hwhdr(header, hd_info->len);
++ hdr_offset = SDPCM_HWHDR_LEN;
++
++ if (bus->txglom) {
++ hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
++ *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
++ hdrval = (u16)hd_info->tail_pad << 16;
++ *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
++ hdr_offset += SDPCM_HWEXT_LEN;
++ }
++
++ hdrval = hd_info->seq_num;
++ hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
++ SDPCM_CHANNEL_MASK;
++ hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
++ SDPCM_DOFFSET_MASK;
++ *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
++ *(((__le32 *)(header + hdr_offset)) + 1) = 0;
++ trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
++}
++
++static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
+ {
+ u16 dlen, totlen;
+ u8 *dptr, num = 0;
+-
+ u16 sublen;
+ struct sk_buff *pfirst, *pnext;
+
+ int errcode;
+ u8 doff, sfdoff;
+
+- bool usechain = bus->use_rxchain;
+-
+- struct brcmf_sdio_read rd_new;
++ struct brcmf_sdio_hdrinfo rd_new;
+
+ /* If packets, issue read(s) and send up packet chain */
+ /* Return sequence numbers consumed? */
+@@ -1235,10 +1349,9 @@
+ pnext = NULL;
+ break;
+ }
+- if (sublen % BRCMF_SDALIGN) {
++ if (sublen % bus->sgentry_align) {
+ brcmf_err("sublen %d not multiple of %d\n",
+- sublen, BRCMF_SDALIGN);
+- usechain = false;
++ sublen, bus->sgentry_align);
+ }
+ totlen += sublen;
+
+@@ -1251,7 +1364,7 @@
+ }
+
+ /* Allocate/chain packet for next subframe */
+- pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
++ pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
+ if (pnext == NULL) {
+ brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
+ num, sublen);
+@@ -1260,7 +1373,7 @@
+ skb_queue_tail(&bus->glom, pnext);
+
+ /* Adhere to start alignment requirements */
+- pkt_align(pnext, sublen, BRCMF_SDALIGN);
++ pkt_align(pnext, sublen, bus->sgentry_align);
+ }
+
+ /* If all allocations succeeded, save packet chain
+@@ -1275,7 +1388,7 @@
+ }
+ pfirst = pnext = NULL;
+ } else {
+- brcmf_sdbrcm_free_glom(bus);
++ brcmf_sdio_free_glom(bus);
+ num = 0;
+ }
+
+@@ -1298,34 +1411,15 @@
+ }
+
+ pfirst = skb_peek(&bus->glom);
+- dlen = (u16) brcmf_sdbrcm_glom_len(bus);
++ dlen = (u16) brcmf_sdio_glom_len(bus);
+
+ /* Do an SDIO read for the superframe. Configurable iovar to
+ * read directly into the chained packet, or allocate a large
+ * packet and and copy into the chain.
+ */
+ sdio_claim_host(bus->sdiodev->func[1]);
+- if (usechain) {
+- errcode = brcmf_sdcard_recv_chain(bus->sdiodev,
+- bus->sdiodev->sbwad,
+- SDIO_FUNC_2, F2SYNC, &bus->glom);
+- } else if (bus->dataptr) {
+- errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
+- bus->sdiodev->sbwad,
+- SDIO_FUNC_2, F2SYNC,
+- bus->dataptr, dlen);
+- sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
+- if (sublen != dlen) {
+- brcmf_err("FAILED TO COPY, dlen %d sublen %d\n",
+- dlen, sublen);
+- errcode = -1;
+- }
+- pnext = NULL;
+- } else {
+- brcmf_err("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
+- dlen);
+- errcode = -1;
+- }
++ errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
++ &bus->glom, dlen);
+ sdio_release_host(bus->sdiodev->func[1]);
+ bus->sdcnt.f2rxdata++;
+
+@@ -1336,12 +1430,12 @@
+
+ sdio_claim_host(bus->sdiodev->func[1]);
+ if (bus->glomerr++ < 3) {
+- brcmf_sdbrcm_rxfail(bus, true, true);
++ brcmf_sdio_rxfail(bus, true, true);
+ } else {
+ bus->glomerr = 0;
+- brcmf_sdbrcm_rxfail(bus, true, false);
++ brcmf_sdio_rxfail(bus, true, false);
+ bus->sdcnt.rxglomfail++;
+- brcmf_sdbrcm_free_glom(bus);
++ brcmf_sdio_free_glom(bus);
+ }
+ sdio_release_host(bus->sdiodev->func[1]);
+ return 0;
+@@ -1354,8 +1448,8 @@
+ rd_new.seq_num = rxseq;
+ rd_new.len = dlen;
+ sdio_claim_host(bus->sdiodev->func[1]);
+- errcode = brcmf_sdio_hdparser(bus, pfirst->data, &rd_new,
+- BRCMF_SDIO_FT_SUPER);
++ errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
++ BRCMF_SDIO_FT_SUPER);
+ sdio_release_host(bus->sdiodev->func[1]);
+ bus->cur_read.len = rd_new.len_nxtfrm << 4;
+
+@@ -1373,8 +1467,8 @@
+ rd_new.len = pnext->len;
+ rd_new.seq_num = rxseq++;
+ sdio_claim_host(bus->sdiodev->func[1]);
+- errcode = brcmf_sdio_hdparser(bus, pnext->data, &rd_new,
+- BRCMF_SDIO_FT_SUB);
++ errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
++ BRCMF_SDIO_FT_SUB);
+ sdio_release_host(bus->sdiodev->func[1]);
+ brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
+ pnext->data, 32, "subframe:\n");
+@@ -1389,12 +1483,12 @@
+ if (bus->glomerr++ < 3) {
+ /* Restore superframe header space */
+ skb_push(pfirst, sfdoff);
+- brcmf_sdbrcm_rxfail(bus, true, true);
++ brcmf_sdio_rxfail(bus, true, true);
+ } else {
+ bus->glomerr = 0;
+- brcmf_sdbrcm_rxfail(bus, true, false);
++ brcmf_sdio_rxfail(bus, true, false);
+ bus->sdcnt.rxglomfail++;
+- brcmf_sdbrcm_free_glom(bus);
++ brcmf_sdio_free_glom(bus);
+ }
+ sdio_release_host(bus->sdiodev->func[1]);
+ bus->cur_read.len = 0;
+@@ -1406,7 +1500,7 @@
+ skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
+ dptr = (u8 *) (pfirst->data);
+ sublen = get_unaligned_le16(dptr);
+- doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
++ doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
+
+ brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
+ dptr, pfirst->len,
+@@ -1428,19 +1522,18 @@
+ bus->glom.qlen, pfirst, pfirst->data,
+ pfirst->len, pfirst->next,
+ pfirst->prev);
++ skb_unlink(pfirst, &bus->glom);
++ brcmf_rx_frame(bus->sdiodev->dev, pfirst);
++ bus->sdcnt.rxglompkts++;
+ }
+- /* sent any remaining packets up */
+- if (bus->glom.qlen)
+- brcmf_rx_frames(bus->sdiodev->dev, &bus->glom);
+
+ bus->sdcnt.rxglomframes++;
+- bus->sdcnt.rxglompkts += bus->glom.qlen;
+ }
+ return num;
+ }
+
+-static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
+- bool *pending)
++static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
++ bool *pending)
+ {
+ DECLARE_WAITQUEUE(wait, current);
+ int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
+@@ -1461,7 +1554,7 @@
+ return timeout;
+ }
+
+-static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus)
++static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
+ {
+ if (waitqueue_active(&bus->dcmd_resp_wait))
+ wake_up_interruptible(&bus->dcmd_resp_wait);
+@@ -1469,7 +1562,7 @@
+ return 0;
+ }
+ static void
+-brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
++brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
+ {
+ uint rdlen, pad;
+ u8 *buf = NULL, *rbuf;
+@@ -1483,9 +1576,9 @@
+ goto done;
+
+ rbuf = bus->rxbuf;
+- pad = ((unsigned long)rbuf % BRCMF_SDALIGN);
++ pad = ((unsigned long)rbuf % bus->head_align);
+ if (pad)
+- rbuf += (BRCMF_SDALIGN - pad);
++ rbuf += (bus->head_align - pad);
+
+ /* Copy the already-read portion over */
+ memcpy(buf, hdr, BRCMF_FIRSTREAD);
+@@ -1499,19 +1592,15 @@
+ if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
+ ((len + pad) < bus->sdiodev->bus_if->maxctl))
+ rdlen += pad;
+- } else if (rdlen % BRCMF_SDALIGN) {
+- rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
++ } else if (rdlen % bus->head_align) {
++ rdlen += bus->head_align - (rdlen % bus->head_align);
+ }
+
+- /* Satisfy length-alignment requirements */
+- if (rdlen & (ALIGNMENT - 1))
+- rdlen = roundup(rdlen, ALIGNMENT);
+-
+ /* Drop if the read is too big or it exceeds our maximum */
+ if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
+ brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
+ rdlen, bus->sdiodev->bus_if->maxctl);
+- brcmf_sdbrcm_rxfail(bus, false, false);
++ brcmf_sdio_rxfail(bus, false, false);
+ goto done;
+ }
+
+@@ -1519,15 +1608,12 @@
+ brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
+ len, len - doff, bus->sdiodev->bus_if->maxctl);
+ bus->sdcnt.rx_toolong++;
+- brcmf_sdbrcm_rxfail(bus, false, false);
++ brcmf_sdio_rxfail(bus, false, false);
+ goto done;
+ }
+
+ /* Read remain of frame body */
+- sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
+- bus->sdiodev->sbwad,
+- SDIO_FUNC_2,
+- F2SYNC, rbuf, rdlen);
++ sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
+ bus->sdcnt.f2rxdata++;
+
+ /* Control frame failures need retransmission */
+@@ -1535,7 +1621,7 @@
+ brcmf_err("read %d control bytes failed: %d\n",
+ rdlen, sdret);
+ bus->sdcnt.rxc_errors++;
+- brcmf_sdbrcm_rxfail(bus, true, true);
++ brcmf_sdio_rxfail(bus, true, true);
+ goto done;
+ } else
+ memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
+@@ -1560,31 +1646,30 @@
+
+ done:
+ /* Awake any waiters */
+- brcmf_sdbrcm_dcmd_resp_wake(bus);
++ brcmf_sdio_dcmd_resp_wake(bus);
+ }
+
+ /* Pad read to blocksize for efficiency */
+-static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
++static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
+ {
+ if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
+ *pad = bus->blocksize - (*rdlen % bus->blocksize);
+ if (*pad <= bus->roundup && *pad < bus->blocksize &&
+ *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
+ *rdlen += *pad;
+- } else if (*rdlen % BRCMF_SDALIGN) {
+- *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
++ } else if (*rdlen % bus->head_align) {
++ *rdlen += bus->head_align - (*rdlen % bus->head_align);
+ }
+ }
+
+ static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
+ {
+ struct sk_buff *pkt; /* Packet for event or data frames */
+- struct sk_buff_head pktlist; /* needed for bus interface */
+ u16 pad; /* Number of pad bytes to read */
+ uint rxleft = 0; /* Remaining number of frames allowed */
+ int ret; /* Return code from calls */
+ uint rxcount = 0; /* Total frames read */
+- struct brcmf_sdio_read *rd = &bus->cur_read, rd_new;
++ struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
+ u8 head_read = 0;
+
+ brcmf_dbg(TRACE, "Enter\n");
+@@ -1593,8 +1678,7 @@
+ bus->rxpending = true;
+
+ for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
+- !bus->rxskip && rxleft &&
+- bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN;
++ !bus->rxskip && rxleft && brcmf_bus_ready(bus->sdiodev->bus_if);
+ rd->seq_num++, rxleft--) {
+
+ /* Handle glomming separately */
+@@ -1602,7 +1686,7 @@
+ u8 cnt;
+ brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
+ bus->glomd, skb_peek(&bus->glom));
+- cnt = brcmf_sdbrcm_rxglom(bus, rd->seq_num);
++ cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
+ brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
+ rd->seq_num += cnt - 1;
+ rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
+@@ -1613,17 +1697,14 @@
+ /* read header first for unknow frame length */
+ sdio_claim_host(bus->sdiodev->func[1]);
+ if (!rd->len) {
+- ret = brcmf_sdcard_recv_buf(bus->sdiodev,
+- bus->sdiodev->sbwad,
+- SDIO_FUNC_2, F2SYNC,
+- bus->rxhdr,
+- BRCMF_FIRSTREAD);
++ ret = brcmf_sdiod_recv_buf(bus->sdiodev,
++ bus->rxhdr, BRCMF_FIRSTREAD);
+ bus->sdcnt.f2rxhdrs++;
+ if (ret < 0) {
+ brcmf_err("RXHEADER FAILED: %d\n",
+ ret);
+ bus->sdcnt.rx_hdrfail++;
+- brcmf_sdbrcm_rxfail(bus, true, true);
++ brcmf_sdio_rxfail(bus, true, true);
+ sdio_release_host(bus->sdiodev->func[1]);
+ continue;
+ }
+@@ -1632,8 +1713,8 @@
+ bus->rxhdr, SDPCM_HDRLEN,
+ "RxHdr:\n");
+
+- if (brcmf_sdio_hdparser(bus, bus->rxhdr, rd,
+- BRCMF_SDIO_FT_NORMAL)) {
++ if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
++ BRCMF_SDIO_FT_NORMAL)) {
+ sdio_release_host(bus->sdiodev->func[1]);
+ if (!bus->rxpending)
+ break;
+@@ -1642,9 +1723,9 @@
+ }
+
+ if (rd->channel == SDPCM_CONTROL_CHANNEL) {
+- brcmf_sdbrcm_read_control(bus, bus->rxhdr,
+- rd->len,
+- rd->dat_offset);
++ brcmf_sdio_read_control(bus, bus->rxhdr,
++ rd->len,
++ rd->dat_offset);
+ /* prepare the descriptor for the next read */
+ rd->len = rd->len_nxtfrm << 4;
+ rd->len_nxtfrm = 0;
+@@ -1658,23 +1739,22 @@
+ head_read = BRCMF_FIRSTREAD;
+ }
+
+- brcmf_pad(bus, &pad, &rd->len_left);
++ brcmf_sdio_pad(bus, &pad, &rd->len_left);
+
+ pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
+- BRCMF_SDALIGN);
++ bus->head_align);
+ if (!pkt) {
+ /* Give up on data, request rtx of events */
+ brcmf_err("brcmu_pkt_buf_get_skb failed\n");
+- brcmf_sdbrcm_rxfail(bus, false,
++ brcmf_sdio_rxfail(bus, false,
+ RETRYCHAN(rd->channel));
+ sdio_release_host(bus->sdiodev->func[1]);
+ continue;
+ }
+ skb_pull(pkt, head_read);
+- pkt_align(pkt, rd->len_left, BRCMF_SDALIGN);
++ pkt_align(pkt, rd->len_left, bus->head_align);
+
+- ret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
+- SDIO_FUNC_2, F2SYNC, pkt);
++ ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
+ bus->sdcnt.f2rxdata++;
+ sdio_release_host(bus->sdiodev->func[1]);
+
+@@ -1683,7 +1763,7 @@
+ rd->len, rd->channel, ret);
+ brcmu_pkt_buf_free_skb(pkt);
+ sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdbrcm_rxfail(bus, true,
++ brcmf_sdio_rxfail(bus, true,
+ RETRYCHAN(rd->channel));
+ sdio_release_host(bus->sdiodev->func[1]);
+ continue;
+@@ -1697,8 +1777,8 @@
+ memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
+ rd_new.seq_num = rd->seq_num;
+ sdio_claim_host(bus->sdiodev->func[1]);
+- if (brcmf_sdio_hdparser(bus, bus->rxhdr, &rd_new,
+- BRCMF_SDIO_FT_NORMAL)) {
++ if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
++ BRCMF_SDIO_FT_NORMAL)) {
+ rd->len = 0;
+ brcmu_pkt_buf_free_skb(pkt);
+ }
+@@ -1708,7 +1788,7 @@
+ rd->len,
+ roundup(rd_new.len, 16) >> 4);
+ rd->len = 0;
+- brcmf_sdbrcm_rxfail(bus, true, true);
++ brcmf_sdio_rxfail(bus, true, true);
+ sdio_release_host(bus->sdiodev->func[1]);
+ brcmu_pkt_buf_free_skb(pkt);
+ continue;
+@@ -1730,7 +1810,7 @@
+ /* Force retry w/normal header read */
+ rd->len = 0;
+ sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdbrcm_rxfail(bus, false, true);
++ brcmf_sdio_rxfail(bus, false, true);
+ sdio_release_host(bus->sdiodev->func[1]);
+ brcmu_pkt_buf_free_skb(pkt);
+ continue;
+@@ -1742,7 +1822,7 @@
+
+ /* Save superframe descriptor and allocate packet frame */
+ if (rd->channel == SDPCM_GLOM_CHANNEL) {
+- if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
++ if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
+ brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
+ rd->len);
+ brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
+@@ -1755,7 +1835,7 @@
+ brcmf_err("%s: glom superframe w/o "
+ "descriptor!\n", __func__);
+ sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdbrcm_rxfail(bus, false, false);
++ brcmf_sdio_rxfail(bus, false, false);
+ sdio_release_host(bus->sdiodev->func[1]);
+ }
+ /* prepare the descriptor for the next read */
+@@ -1781,9 +1861,7 @@
+ continue;
+ }
+
+- skb_queue_head_init(&pktlist);
+- skb_queue_tail(&pktlist, pkt);
+- brcmf_rx_frames(bus->sdiodev->dev, &pktlist);
++ brcmf_rx_frame(bus->sdiodev->dev, pkt);
+ }
+
+ rxcount = maxframes - rxleft;
+@@ -1801,92 +1879,237 @@
+ }
+
+ static void
+-brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus)
++brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
+ {
+ if (waitqueue_active(&bus->ctrl_wait))
+ wake_up_interruptible(&bus->ctrl_wait);
+ return;
+ }
+
+-/* Writes a HW/SW header into the packet and sends it. */
+-/* Assumes: (a) header space already there, (b) caller holds lock */
+-static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt,
+- uint chan)
++static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
+ {
+- int ret;
+- u8 *frame;
+- u16 len, pad = 0;
+- u32 swheader;
+- int i;
+-
+- brcmf_dbg(TRACE, "Enter\n");
++ u16 head_pad;
++ u8 *dat_buf;
+
+- frame = (u8 *) (pkt->data);
++ dat_buf = (u8 *)(pkt->data);
+
+- /* Add alignment padding, allocate new packet if needed */
+- pad = ((unsigned long)frame % BRCMF_SDALIGN);
+- if (pad) {
+- if (skb_headroom(pkt) < pad) {
+- brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
+- skb_headroom(pkt), pad);
++ /* Check head padding */
++ head_pad = ((unsigned long)dat_buf % bus->head_align);
++ if (head_pad) {
++ if (skb_headroom(pkt) < head_pad) {
+ bus->sdiodev->bus_if->tx_realloc++;
+- ret = skb_cow(pkt, BRCMF_SDALIGN);
+- if (ret)
+- goto done;
+- pad = ((unsigned long)frame % BRCMF_SDALIGN);
+- }
+- skb_push(pkt, pad);
+- frame = (u8 *) (pkt->data);
+- memset(frame, 0, pad + SDPCM_HDRLEN);
+- }
+- /* precondition: pad < BRCMF_SDALIGN */
+-
+- /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
+- len = (u16) (pkt->len);
+- *(__le16 *) frame = cpu_to_le16(len);
+- *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
+-
+- /* Software tag: channel, sequence number, data offset */
+- swheader =
+- ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
+- (((pad +
+- SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
++ head_pad = 0;
++ if (skb_cow(pkt, head_pad))
++ return -ENOMEM;
++ }
++ skb_push(pkt, head_pad);
++ dat_buf = (u8 *)(pkt->data);
++ memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
++ }
++ return head_pad;
++}
+
+- *(((__le32 *) frame) + 1) = cpu_to_le32(swheader);
+- *(((__le32 *) frame) + 2) = 0;
++/**
++ * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
++ * bus layer usage.
++ */
++/* flag marking a dummy skb added for DMA alignment requirement */
++#define ALIGN_SKB_FLAG 0x8000
++/* bit mask of data length chopped from the previous packet */
++#define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
++
++static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
++ struct sk_buff_head *pktq,
++ struct sk_buff *pkt, u16 total_len)
++{
++ struct brcmf_sdio_dev *sdiodev;
++ struct sk_buff *pkt_pad;
++ u16 tail_pad, tail_chop, chain_pad;
++ unsigned int blksize;
++ bool lastfrm;
++ int ntail, ret;
++
++ sdiodev = bus->sdiodev;
++ blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
++ /* sg entry alignment should be a divisor of block size */
++ WARN_ON(blksize % bus->sgentry_align);
++
++ /* Check tail padding */
++ lastfrm = skb_queue_is_last(pktq, pkt);
++ tail_pad = 0;
++ tail_chop = pkt->len % bus->sgentry_align;
++ if (tail_chop)
++ tail_pad = bus->sgentry_align - tail_chop;
++ chain_pad = (total_len + tail_pad) % blksize;
++ if (lastfrm && chain_pad)
++ tail_pad += blksize - chain_pad;
++ if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
++ pkt_pad = bus->txglom_sgpad;
++ if (pkt_pad == NULL)
++ brcmu_pkt_buf_get_skb(tail_pad + tail_chop);
++ if (pkt_pad == NULL)
++ return -ENOMEM;
++ ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
++ if (unlikely(ret < 0))
++ return ret;
++ memcpy(pkt_pad->data,
++ pkt->data + pkt->len - tail_chop,
++ tail_chop);
++ *(u32 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
++ skb_trim(pkt, pkt->len - tail_chop);
++ __skb_queue_after(pktq, pkt, pkt_pad);
++ } else {
++ ntail = pkt->data_len + tail_pad -
++ (pkt->end - pkt->tail);
++ if (skb_cloned(pkt) || ntail > 0)
++ if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
++ return -ENOMEM;
++ if (skb_linearize(pkt))
++ return -ENOMEM;
++ __skb_put(pkt, tail_pad);
++ }
+
+-#ifdef DEBUG
+- tx_packets[pkt->priority]++;
+-#endif
++ return tail_pad;
++}
+
+- brcmf_dbg_hex_dump(BRCMF_BYTES_ON() &&
+- ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
+- (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)),
+- frame, len, "Tx Frame:\n");
+- brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
+- ((BRCMF_CTL_ON() &&
+- chan == SDPCM_CONTROL_CHANNEL) ||
+- (BRCMF_DATA_ON() &&
+- chan != SDPCM_CONTROL_CHANNEL))) &&
+- BRCMF_HDRS_ON(),
+- frame, min_t(u16, len, 16), "TxHdr:\n");
++/**
++ * brcmf_sdio_txpkt_prep - packet preparation for transmit
++ * @bus: brcmf_sdio structure pointer
++ * @pktq: packet list pointer
++ * @chan: virtual channel to transmit the packet
++ *
++ * Processes to be applied to the packet
++ * - Align data buffer pointer
++ * - Align data buffer length
++ * - Prepare header
++ * Return: negative value if there is error
++ */
++static int
++brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
++ uint chan)
++{
++ u16 head_pad, total_len;
++ struct sk_buff *pkt_next;
++ u8 txseq;
++ int ret;
++ struct brcmf_sdio_hdrinfo hd_info = {0};
+
+- /* Raise len to next SDIO block to eliminate tail command */
+- if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
+- u16 pad = bus->blocksize - (len % bus->blocksize);
+- if ((pad <= bus->roundup) && (pad < bus->blocksize))
+- len += pad;
+- } else if (len % BRCMF_SDALIGN) {
+- len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
++ txseq = bus->tx_seq;
++ total_len = 0;
++ skb_queue_walk(pktq, pkt_next) {
++ /* alignment packet inserted in previous
++ * loop cycle can be skipped as it is
++ * already properly aligned and does not
++ * need an sdpcm header.
++ */
++ if (*(u32 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
++ continue;
++
++ /* align packet data pointer */
++ ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
++ if (ret < 0)
++ return ret;
++ head_pad = (u16)ret;
++ if (head_pad)
++ memset(pkt_next->data, 0, head_pad + bus->tx_hdrlen);
++
++ total_len += pkt_next->len;
++
++ hd_info.len = pkt_next->len;
++ hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
++ if (bus->txglom && pktq->qlen > 1) {
++ ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
++ pkt_next, total_len);
++ if (ret < 0)
++ return ret;
++ hd_info.tail_pad = (u16)ret;
++ total_len += (u16)ret;
++ }
++
++ hd_info.channel = chan;
++ hd_info.dat_offset = head_pad + bus->tx_hdrlen;
++ hd_info.seq_num = txseq++;
++
++ /* Now fill the header */
++ brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
++
++ if (BRCMF_BYTES_ON() &&
++ ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
++ (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
++ brcmf_dbg_hex_dump(true, pkt_next, hd_info.len,
++ "Tx Frame:\n");
++ else if (BRCMF_HDRS_ON())
++ brcmf_dbg_hex_dump(true, pkt_next,
++ head_pad + bus->tx_hdrlen,
++ "Tx Header:\n");
++ }
++ /* Hardware length tag of the first packet should be total
++ * length of the chain (including padding)
++ */
++ if (bus->txglom)
++ brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
++ return 0;
++}
++
++/**
++ * brcmf_sdio_txpkt_postp - packet post processing for transmit
++ * @bus: brcmf_sdio structure pointer
++ * @pktq: packet list pointer
++ *
++ * Processes to be applied to the packet
++ * - Remove head padding
++ * - Remove tail padding
++ */
++static void
++brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
++{
++ u8 *hdr;
++ u32 dat_offset;
++ u16 tail_pad;
++ u32 dummy_flags, chop_len;
++ struct sk_buff *pkt_next, *tmp, *pkt_prev;
++
++ skb_queue_walk_safe(pktq, pkt_next, tmp) {
++ dummy_flags = *(u32 *)(pkt_next->cb);
++ if (dummy_flags & ALIGN_SKB_FLAG) {
++ chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
++ if (chop_len) {
++ pkt_prev = pkt_next->prev;
++ skb_put(pkt_prev, chop_len);
++ }
++ __skb_unlink(pkt_next, pktq);
++ brcmu_pkt_buf_free_skb(pkt_next);
++ } else {
++ hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
++ dat_offset = le32_to_cpu(*(__le32 *)hdr);
++ dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
++ SDPCM_DOFFSET_SHIFT;
++ skb_pull(pkt_next, dat_offset);
++ if (bus->txglom) {
++ tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
++ skb_trim(pkt_next, pkt_next->len - tail_pad);
++ }
++ }
+ }
++}
+
+- /* Some controllers have trouble with odd bytes -- round to even */
+- if (len & (ALIGNMENT - 1))
+- len = roundup(len, ALIGNMENT);
++/* Writes a HW/SW header into the packet and sends it. */
++/* Assumes: (a) header space already there, (b) caller holds lock */
++static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
++ uint chan)
++{
++ int ret;
++ int i;
++ struct sk_buff *pkt_next, *tmp;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
++ if (ret)
++ goto done;
+
+ sdio_claim_host(bus->sdiodev->func[1]);
+- ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad,
+- SDIO_FUNC_2, F2SYNC, pkt);
++ ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
+ bus->sdcnt.f2txdata++;
+
+ if (ret < 0) {
+@@ -1895,59 +2118,71 @@
+ ret);
+ bus->sdcnt.tx_sderrs++;
+
+- brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
+- SFC_WF_TERM, NULL);
++ brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
++ SFC_WF_TERM, NULL);
+ bus->sdcnt.f1regdata++;
+
+ for (i = 0; i < 3; i++) {
+ u8 hi, lo;
+- hi = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCHI, NULL);
+- lo = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCLO, NULL);
++ hi = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_WFRAMEBCHI, NULL);
++ lo = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_WFRAMEBCLO, NULL);
+ bus->sdcnt.f1regdata += 2;
+ if ((hi == 0) && (lo == 0))
+ break;
+ }
+-
+ }
+ sdio_release_host(bus->sdiodev->func[1]);
+- if (ret == 0)
+- bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
+
+ done:
+- /* restore pkt buffer pointer before calling tx complete routine */
+- skb_pull(pkt, SDPCM_HDRLEN + pad);
+- brcmf_txcomplete(bus->sdiodev->dev, pkt, ret == 0);
++ brcmf_sdio_txpkt_postp(bus, pktq);
++ if (ret == 0)
++ bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
++ skb_queue_walk_safe(pktq, pkt_next, tmp) {
++ __skb_unlink(pkt_next, pktq);
++ brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
++ }
+ return ret;
+ }
+
+-static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes)
++static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
+ {
+ struct sk_buff *pkt;
++ struct sk_buff_head pktq;
+ u32 intstatus = 0;
+- int ret = 0, prec_out;
++ int ret = 0, prec_out, i;
+ uint cnt = 0;
+- uint datalen;
+- u8 tx_prec_map;
++ u8 tx_prec_map, pkt_num;
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+ tx_prec_map = ~bus->flowcontrol;
+
+ /* Send frames until the limit or some other event */
+- for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
++ for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
++ pkt_num = 1;
++ __skb_queue_head_init(&pktq);
++ if (bus->txglom)
++ pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
++ brcmf_sdio_txglomsz);
++ pkt_num = min_t(u32, pkt_num,
++ brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
+ spin_lock_bh(&bus->txqlock);
+- pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
+- if (pkt == NULL) {
+- spin_unlock_bh(&bus->txqlock);
+- break;
++ for (i = 0; i < pkt_num; i++) {
++ pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
++ &prec_out);
++ if (pkt == NULL)
++ break;
++ __skb_queue_tail(&pktq, pkt);
+ }
+ spin_unlock_bh(&bus->txqlock);
+- datalen = pkt->len - SDPCM_HDRLEN;
++ if (i == 0)
++ break;
+
+- ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL);
++ ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
++ cnt += i;
+
+ /* In poll mode, need to check for other events */
+ if (!bus->intr && cnt) {
+@@ -1975,7 +2210,7 @@
+ return cnt;
+ }
+
+-static void brcmf_sdbrcm_bus_stop(struct device *dev)
++static void brcmf_sdio_bus_stop(struct device *dev)
+ {
+ u32 local_hostintmask;
+ u8 saveclk;
+@@ -1992,62 +2227,57 @@
+ bus->watchdog_tsk = NULL;
+ }
+
+- sdio_claim_host(bus->sdiodev->func[1]);
++ if (bus_if->state == BRCMF_BUS_DOWN) {
++ sdio_claim_host(sdiodev->func[1]);
+
+- /* Enable clock for device interrupts */
+- brcmf_sdbrcm_bus_sleep(bus, false, false);
++ /* Enable clock for device interrupts */
++ brcmf_sdio_bus_sleep(bus, false, false);
+
+- /* Disable and clear interrupts at the chip level also */
+- w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
+- local_hostintmask = bus->hostintmask;
+- bus->hostintmask = 0;
++ /* Disable and clear interrupts at the chip level also */
++ w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
++ local_hostintmask = bus->hostintmask;
++ bus->hostintmask = 0;
++
++ /* Force backplane clocks to assure F2 interrupt propagates */
++ saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ &err);
++ if (!err)
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ (saveclk | SBSDIO_FORCE_HT), &err);
++ if (err)
++ brcmf_err("Failed to force clock for F2: err %d\n",
++ err);
+
+- /* Change our idea of bus state */
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
++ /* Turn off the bus (F2), free any pending packets */
++ brcmf_dbg(INTR, "disable SDIO interrupts\n");
++ sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
++
++ /* Clear any pending interrupts now that F2 is disabled */
++ w_sdreg32(bus, local_hostintmask,
++ offsetof(struct sdpcmd_regs, intstatus));
+
+- /* Force clocks on backplane to be sure F2 interrupt propagates */
+- saveclk = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
+- if (!err) {
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- (saveclk | SBSDIO_FORCE_HT), &err);
++ sdio_release_host(sdiodev->func[1]);
+ }
+- if (err)
+- brcmf_err("Failed to force clock for F2: err %d\n", err);
+-
+- /* Turn off the bus (F2), free any pending packets */
+- brcmf_dbg(INTR, "disable SDIO interrupts\n");
+- brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, SDIO_FUNC_ENABLE_1,
+- NULL);
+-
+- /* Clear any pending interrupts now that F2 is disabled */
+- w_sdreg32(bus, local_hostintmask,
+- offsetof(struct sdpcmd_regs, intstatus));
+-
+- /* Turn off the backplane clock (only) */
+- brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+ /* Clear the data packet queues */
+ brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
+
+ /* Clear any held glomming stuff */
+ if (bus->glomd)
+ brcmu_pkt_buf_free_skb(bus->glomd);
+- brcmf_sdbrcm_free_glom(bus);
++ brcmf_sdio_free_glom(bus);
+
+ /* Clear rx control and wake any waiters */
+ spin_lock_bh(&bus->rxctl_lock);
+ bus->rxlen = 0;
+ spin_unlock_bh(&bus->rxctl_lock);
+- brcmf_sdbrcm_dcmd_resp_wake(bus);
++ brcmf_sdio_dcmd_resp_wake(bus);
+
+ /* Reset some F2 state stuff */
+ bus->rxskip = false;
+ bus->tx_seq = bus->rx_seq = 0;
+ }
+
+-static inline void brcmf_sdbrcm_clrintr(struct brcmf_sdio *bus)
++static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
+ {
+ unsigned long flags;
+
+@@ -2061,23 +2291,6 @@
+ }
+ }
+
+-static inline void brcmf_sdbrcm_adddpctsk(struct brcmf_sdio *bus)
+-{
+- struct list_head *new_hd;
+- unsigned long flags;
+-
+- if (in_interrupt())
+- new_hd = kzalloc(sizeof(struct list_head), GFP_ATOMIC);
+- else
+- new_hd = kzalloc(sizeof(struct list_head), GFP_KERNEL);
+- if (new_hd == NULL)
+- return;
+-
+- spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+- list_add_tail(new_hd, &bus->dpc_tsklst);
+- spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+-}
+-
+ static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
+ {
+ u8 idx;
+@@ -2089,7 +2302,7 @@
+ addr = bus->ci->c_inf[idx].base +
+ offsetof(struct sdpcmd_regs, intstatus);
+
+- ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, false);
++ val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
+ bus->sdcnt.f1regdata++;
+ if (ret != 0)
+ val = 0;
+@@ -2099,7 +2312,7 @@
+
+ /* Clear interrupts */
+ if (val) {
+- ret = brcmf_sdio_regrw_helper(bus->sdiodev, addr, &val, true);
++ brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
+ bus->sdcnt.f1regdata++;
+ }
+
+@@ -2113,7 +2326,7 @@
+ return ret;
+ }
+
+-static void brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
++static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
+ {
+ u32 newstatus = 0;
+ unsigned long intstatus;
+@@ -2132,48 +2345,29 @@
+
+ #ifdef DEBUG
+ /* Check for inconsistent device control */
+- devctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
+- if (err) {
+- brcmf_err("error reading DEVCTL: %d\n", err);
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
+- }
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
+ #endif /* DEBUG */
+
+ /* Read CSR, if clock on switch to AVAIL, else ignore */
+- clkctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
+- if (err) {
+- brcmf_err("error reading CSR: %d\n",
+- err);
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
+- }
++ clkctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, &err);
+
+ brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
+ devctl, clkctl);
+
+ if (SBSDIO_HTAV(clkctl)) {
+- devctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
+- if (err) {
+- brcmf_err("error reading DEVCTL: %d\n",
+- err);
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
+- }
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
+ devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
+- devctl, &err);
+- if (err) {
+- brcmf_err("error writing DEVCTL: %d\n",
+- err);
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
+- }
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
++ devctl, &err);
+ bus->clkstate = CLK_AVAIL;
+ }
+ }
+
+ /* Make sure backplane clock is on */
+- brcmf_sdbrcm_bus_sleep(bus, false, true);
++ brcmf_sdio_bus_sleep(bus, false, true);
+
+ /* Pending interrupt indicates new device status */
+ if (atomic_read(&bus->ipend) > 0) {
+@@ -2204,7 +2398,7 @@
+ /* Handle host mailbox indication */
+ if (intstatus & I_HMB_HOST_INT) {
+ intstatus &= ~I_HMB_HOST_INT;
+- intstatus |= brcmf_sdbrcm_hostmail(bus);
++ intstatus |= brcmf_sdio_hostmail(bus);
+ }
+
+ sdio_release_host(bus->sdiodev->func[1]);
+@@ -2249,16 +2443,15 @@
+ set_bit(n, (unsigned long *)&bus->intstatus.counter);
+ }
+
+- brcmf_sdbrcm_clrintr(bus);
++ brcmf_sdio_clrintr(bus);
+
+ if (data_ok(bus) && bus->ctrl_frame_stat &&
+ (bus->clkstate == CLK_AVAIL)) {
+ int i;
+
+ sdio_claim_host(bus->sdiodev->func[1]);
+- err = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
+- SDIO_FUNC_2, F2SYNC, bus->ctrl_frame_buf,
+- (u32) bus->ctrl_frame_len);
++ err = brcmf_sdiod_send_buf(bus->sdiodev, bus->ctrl_frame_buf,
++ (u32)bus->ctrl_frame_len);
+
+ if (err < 0) {
+ /* On failure, abort the command and
+@@ -2267,31 +2460,31 @@
+ err);
+ bus->sdcnt.tx_sderrs++;
+
+- brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
++ brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
+
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
+- SFC_WF_TERM, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
++ SFC_WF_TERM, &err);
+ bus->sdcnt.f1regdata++;
+
+ for (i = 0; i < 3; i++) {
+ u8 hi, lo;
+- hi = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCHI,
+- &err);
+- lo = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCLO,
+- &err);
++ hi = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_WFRAMEBCHI,
++ &err);
++ lo = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_WFRAMEBCLO,
++ &err);
+ bus->sdcnt.f1regdata += 2;
+ if ((hi == 0) && (lo == 0))
+ break;
+ }
+
+ } else {
+- bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
++ bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
+ }
+ sdio_release_host(bus->sdiodev->func[1]);
+ bus->ctrl_frame_stat = false;
+- brcmf_sdbrcm_wait_event_wakeup(bus);
++ brcmf_sdio_wait_event_wakeup(bus);
+ }
+ /* Send queued frames (limit 1 if rx may still be pending) */
+ else if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
+@@ -2299,20 +2492,19 @@
+ && data_ok(bus)) {
+ framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
+ txlimit;
+- framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
++ framecnt = brcmf_sdio_sendfromq(bus, framecnt);
+ txlimit -= framecnt;
+ }
+
+- if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) || (err != 0)) {
++ if (!brcmf_bus_ready(bus->sdiodev->bus_if) || (err != 0)) {
+ brcmf_err("failed backplane access over SDIO, halting operation\n");
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
+ atomic_set(&bus->intstatus, 0);
+ } else if (atomic_read(&bus->intstatus) ||
+ atomic_read(&bus->ipend) > 0 ||
+ (!atomic_read(&bus->fcstate) &&
+ brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
+ data_ok(bus)) || PKT_AVAILABLE()) {
+- brcmf_sdbrcm_adddpctsk(bus);
++ atomic_inc(&bus->dpc_tskcnt);
+ }
+
+ /* If we're done for now, turn off clock request. */
+@@ -2321,12 +2513,12 @@
+ bus->activity = false;
+ brcmf_dbg(SDIO, "idle state\n");
+ sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdbrcm_bus_sleep(bus, true, false);
++ brcmf_sdio_bus_sleep(bus, true, false);
+ sdio_release_host(bus->sdiodev->func[1]);
+ }
+ }
+
+-static struct pktq *brcmf_sdbrcm_bus_gettxq(struct device *dev)
++static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
+ {
+ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+@@ -2335,21 +2527,21 @@
+ return &bus->txq;
+ }
+
+-static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt)
++static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
+ {
+ int ret = -EBADE;
+ uint datalen, prec;
+ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+ struct brcmf_sdio *bus = sdiodev->bus;
+- unsigned long flags;
++ ulong flags;
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+ datalen = pkt->len;
+
+ /* Add space for the header */
+- skb_push(pkt, SDPCM_HDRLEN);
++ skb_push(pkt, bus->tx_hdrlen);
+ /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
+
+ prec = prio2prec((pkt->priority & PRIOMASK));
+@@ -2360,35 +2552,29 @@
+ bus->sdcnt.fcqueued++;
+
+ /* Priority based enq */
+- spin_lock_bh(&bus->txqlock);
++ spin_lock_irqsave(&bus->txqlock, flags);
+ if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) {
+- skb_pull(pkt, SDPCM_HDRLEN);
+- brcmf_txcomplete(bus->sdiodev->dev, pkt, false);
++ skb_pull(pkt, bus->tx_hdrlen);
+ brcmf_err("out of bus->txq !!!\n");
+ ret = -ENOSR;
+ } else {
+ ret = 0;
+ }
+- spin_unlock_bh(&bus->txqlock);
+
+ if (pktq_len(&bus->txq) >= TXHI) {
+ bus->txoff = true;
+ brcmf_txflowblock(bus->sdiodev->dev, true);
+ }
++ spin_unlock_irqrestore(&bus->txqlock, flags);
+
+ #ifdef DEBUG
+ if (pktq_plen(&bus->txq, prec) > qcount[prec])
+ qcount[prec] = pktq_plen(&bus->txq, prec);
+ #endif
+
+- spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+- if (list_empty(&bus->dpc_tsklst)) {
+- spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+-
+- brcmf_sdbrcm_adddpctsk(bus);
++ if (atomic_read(&bus->dpc_tskcnt) == 0) {
++ atomic_inc(&bus->dpc_tskcnt);
+ queue_work(bus->brcmf_wq, &bus->datawork);
+- } else {
+- spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+ }
+
+ return ret;
+@@ -2397,7 +2583,7 @@
+ #ifdef DEBUG
+ #define CONSOLE_LINE_MAX 192
+
+-static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
++static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
+ {
+ struct brcmf_console *c = &bus->console;
+ u8 line[CONSOLE_LINE_MAX], ch;
+@@ -2410,8 +2596,8 @@
+
+ /* Read console log struct */
+ addr = bus->console_addr + offsetof(struct rte_console, log_le);
+- rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
+- sizeof(c->log_le));
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
++ sizeof(c->log_le));
+ if (rv < 0)
+ return rv;
+
+@@ -2436,7 +2622,7 @@
+
+ /* Read the console buffer */
+ addr = le32_to_cpu(c->log_le.buf);
+- rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
+ if (rv < 0)
+ return rv;
+
+@@ -2474,14 +2660,13 @@
+ }
+ #endif /* DEBUG */
+
+-static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
++static int brcmf_sdio_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
+ {
+ int i;
+ int ret;
+
+ bus->ctrl_frame_stat = false;
+- ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
+- SDIO_FUNC_2, F2SYNC, frame, len);
++ ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
+
+ if (ret < 0) {
+ /* On failure, abort the command and terminate the frame */
+@@ -2489,18 +2674,18 @@
+ ret);
+ bus->sdcnt.tx_sderrs++;
+
+- brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
++ brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
+
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
+- SFC_WF_TERM, NULL);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
++ SFC_WF_TERM, NULL);
+ bus->sdcnt.f1regdata++;
+
+ for (i = 0; i < 3; i++) {
+ u8 hi, lo;
+- hi = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCHI, NULL);
+- lo = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCLO, NULL);
++ hi = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_WFRAMEBCHI, NULL);
++ lo = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_WFRAMEBCLO, NULL);
+ bus->sdcnt.f1regdata += 2;
+ if (hi == 0 && lo == 0)
+ break;
+@@ -2508,74 +2693,69 @@
+ return ret;
+ }
+
+- bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
++ bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
+
+ return ret;
+ }
+
+ static int
+-brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
++brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
+ {
+ u8 *frame;
+- u16 len;
+- u32 swheader;
++ u16 len, pad;
+ uint retries = 0;
+ u8 doff = 0;
+ int ret = -1;
+ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+ struct brcmf_sdio *bus = sdiodev->bus;
+- unsigned long flags;
++ struct brcmf_sdio_hdrinfo hd_info = {0};
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+ /* Back the pointer to make a room for bus header */
+- frame = msg - SDPCM_HDRLEN;
+- len = (msglen += SDPCM_HDRLEN);
++ frame = msg - bus->tx_hdrlen;
++ len = (msglen += bus->tx_hdrlen);
+
+ /* Add alignment padding (optional for ctl frames) */
+- doff = ((unsigned long)frame % BRCMF_SDALIGN);
++ doff = ((unsigned long)frame % bus->head_align);
+ if (doff) {
+ frame -= doff;
+ len += doff;
+ msglen += doff;
+- memset(frame, 0, doff + SDPCM_HDRLEN);
++ memset(frame, 0, doff + bus->tx_hdrlen);
+ }
+- /* precondition: doff < BRCMF_SDALIGN */
+- doff += SDPCM_HDRLEN;
++ /* precondition: doff < bus->head_align */
++ doff += bus->tx_hdrlen;
+
+ /* Round send length to next SDIO block */
++ pad = 0;
+ if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
+- u16 pad = bus->blocksize - (len % bus->blocksize);
+- if ((pad <= bus->roundup) && (pad < bus->blocksize))
+- len += pad;
+- } else if (len % BRCMF_SDALIGN) {
+- len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
++ pad = bus->blocksize - (len % bus->blocksize);
++ if ((pad > bus->roundup) || (pad >= bus->blocksize))
++ pad = 0;
++ } else if (len % bus->head_align) {
++ pad = bus->head_align - (len % bus->head_align);
+ }
+-
+- /* Satisfy length-alignment requirements */
+- if (len & (ALIGNMENT - 1))
+- len = roundup(len, ALIGNMENT);
++ len += pad;
+
+ /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
+
+ /* Make sure backplane clock is on */
+ sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdbrcm_bus_sleep(bus, false, false);
++ brcmf_sdio_bus_sleep(bus, false, false);
+ sdio_release_host(bus->sdiodev->func[1]);
+
+- /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
+- *(__le16 *) frame = cpu_to_le16((u16) msglen);
+- *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
+-
+- /* Software tag: channel, sequence number, data offset */
+- swheader =
+- ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
+- SDPCM_CHANNEL_MASK)
+- | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
+- SDPCM_DOFFSET_MASK);
+- put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
+- put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
++ hd_info.len = (u16)msglen;
++ hd_info.channel = SDPCM_CONTROL_CHANNEL;
++ hd_info.dat_offset = doff;
++ hd_info.seq_num = bus->tx_seq;
++ hd_info.lastfrm = true;
++ hd_info.tail_pad = pad;
++ brcmf_sdio_hdpack(bus, frame, &hd_info);
++
++ if (bus->txglom)
++ brcmf_sdio_update_hwhdr(frame, len);
+
+ if (!data_ok(bus)) {
+ brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
+@@ -2607,23 +2787,18 @@
+
+ do {
+ sdio_claim_host(bus->sdiodev->func[1]);
+- ret = brcmf_tx_frame(bus, frame, len);
++ ret = brcmf_sdio_tx_frame(bus, frame, len);
+ sdio_release_host(bus->sdiodev->func[1]);
+ } while (ret < 0 && retries++ < TXRETRIES);
+ }
+
+- spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+ if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) &&
+- list_empty(&bus->dpc_tsklst)) {
+- spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+-
++ atomic_read(&bus->dpc_tskcnt) == 0) {
+ bus->activity = false;
+ sdio_claim_host(bus->sdiodev->func[1]);
+ brcmf_dbg(INFO, "idle\n");
+- brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
++ brcmf_sdio_clkctl(bus, CLK_NONE, true);
+ sdio_release_host(bus->sdiodev->func[1]);
+- } else {
+- spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+ }
+
+ if (ret)
+@@ -2656,8 +2831,8 @@
+ * address of sdpcm_shared structure
+ */
+ sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdbrcm_bus_sleep(bus, false, false);
+- rv = brcmf_sdio_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4);
++ brcmf_sdio_bus_sleep(bus, false, false);
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4);
+ sdio_release_host(bus->sdiodev->func[1]);
+ if (rv < 0)
+ return rv;
+@@ -2677,8 +2852,8 @@
+ }
+
+ /* Read hndrte_shared structure */
+- rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
+- sizeof(struct sdpcm_shared_le));
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
++ sizeof(struct sdpcm_shared_le));
+ if (rv < 0)
+ return rv;
+
+@@ -2714,22 +2889,22 @@
+
+ /* obtain console information from device memory */
+ addr = sh->console_addr + offsetof(struct rte_console, log_le);
+- rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr,
+- (u8 *)&sh_val, sizeof(u32));
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
++ (u8 *)&sh_val, sizeof(u32));
+ if (rv < 0)
+ return rv;
+ console_ptr = le32_to_cpu(sh_val);
+
+ addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
+- rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr,
+- (u8 *)&sh_val, sizeof(u32));
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
++ (u8 *)&sh_val, sizeof(u32));
+ if (rv < 0)
+ return rv;
+ console_size = le32_to_cpu(sh_val);
+
+ addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
+- rv = brcmf_sdio_ramrw(bus->sdiodev, false, addr,
+- (u8 *)&sh_val, sizeof(u32));
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
++ (u8 *)&sh_val, sizeof(u32));
+ if (rv < 0)
+ return rv;
+ console_index = le32_to_cpu(sh_val);
+@@ -2743,8 +2918,8 @@
+
+ /* obtain the console data from device */
+ conbuf[console_size] = '\0';
+- rv = brcmf_sdio_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
+- console_size);
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
++ console_size);
+ if (rv < 0)
+ goto done;
+
+@@ -2781,8 +2956,8 @@
+ return 0;
+ }
+
+- error = brcmf_sdio_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
+- sizeof(struct brcmf_trap_info));
++ error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
++ sizeof(struct brcmf_trap_info));
+ if (error < 0)
+ return error;
+
+@@ -2825,14 +3000,14 @@
+
+ sdio_claim_host(bus->sdiodev->func[1]);
+ if (sh->assert_file_addr != 0) {
+- error = brcmf_sdio_ramrw(bus->sdiodev, false,
+- sh->assert_file_addr, (u8 *)file, 80);
++ error = brcmf_sdiod_ramrw(bus->sdiodev, false,
++ sh->assert_file_addr, (u8 *)file, 80);
+ if (error < 0)
+ return error;
+ }
+ if (sh->assert_exp_addr != 0) {
+- error = brcmf_sdio_ramrw(bus->sdiodev, false,
+- sh->assert_exp_addr, (u8 *)expr, 80);
++ error = brcmf_sdiod_ramrw(bus->sdiodev, false,
++ sh->assert_exp_addr, (u8 *)expr, 80);
+ if (error < 0)
+ return error;
+ }
+@@ -2844,7 +3019,7 @@
+ return simple_read_from_buffer(data, count, &pos, buf, res);
+ }
+
+-static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus)
++static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
+ {
+ int error;
+ struct sdpcm_shared sh;
+@@ -2865,8 +3040,8 @@
+ return 0;
+ }
+
+-static int brcmf_sdbrcm_died_dump(struct brcmf_sdio *bus, char __user *data,
+- size_t count, loff_t *ppos)
++static int brcmf_sdio_died_dump(struct brcmf_sdio *bus, char __user *data,
++ size_t count, loff_t *ppos)
+ {
+ int error = 0;
+ struct sdpcm_shared sh;
+@@ -2907,7 +3082,7 @@
+ struct brcmf_sdio *bus = f->private_data;
+ int res;
+
+- res = brcmf_sdbrcm_died_dump(bus, data, count, ppos);
++ res = brcmf_sdio_died_dump(bus, data, count, ppos);
+ if (res > 0)
+ *ppos += res;
+ return (ssize_t)res;
+@@ -2932,7 +3107,7 @@
+ brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt);
+ }
+ #else
+-static int brcmf_sdbrcm_checkdied(struct brcmf_sdio *bus)
++static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
+ {
+ return 0;
+ }
+@@ -2943,7 +3118,7 @@
+ #endif /* DEBUG */
+
+ static int
+-brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
++brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
+ {
+ int timeleft;
+ uint rxlen = 0;
+@@ -2956,7 +3131,7 @@
+ brcmf_dbg(TRACE, "Enter\n");
+
+ /* Wait until control frame is available */
+- timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
++ timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
+
+ spin_lock_bh(&bus->rxctl_lock);
+ rxlen = bus->rxlen;
+@@ -2973,13 +3148,13 @@
+ rxlen, msglen);
+ } else if (timeleft == 0) {
+ brcmf_err("resumed on timeout\n");
+- brcmf_sdbrcm_checkdied(bus);
++ brcmf_sdio_checkdied(bus);
+ } else if (pending) {
+ brcmf_dbg(CTL, "cancelled\n");
+ return -ERESTARTSYS;
+ } else {
+ brcmf_dbg(CTL, "resumed for unknown reason?\n");
+- brcmf_sdbrcm_checkdied(bus);
++ brcmf_sdio_checkdied(bus);
+ }
+
+ if (rxlen)
+@@ -2990,222 +3165,183 @@
+ return rxlen ? (int)rxlen : -ETIMEDOUT;
+ }
+
+-static bool brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
++#ifdef DEBUG
++static bool
++brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
++ u8 *ram_data, uint ram_sz)
+ {
+- struct chip_info *ci = bus->ci;
+-
+- /* To enter download state, disable ARM and reset SOCRAM.
+- * To exit download state, simply reset ARM (default is RAM boot).
+- */
+- if (enter) {
+- bus->alp_only = true;
+-
+- brcmf_sdio_chip_enter_download(bus->sdiodev, ci);
+- } else {
+- if (!brcmf_sdio_chip_exit_download(bus->sdiodev, ci, bus->vars,
+- bus->varsz))
+- return false;
++ char *ram_cmp;
++ int err;
++ bool ret = true;
++ int address;
++ int offset;
++ int len;
+
+- /* Allow HT Clock now that the ARM is running. */
+- bus->alp_only = false;
++ /* read back and verify */
++ brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
++ ram_sz);
++ ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
++ /* do not proceed while no memory but */
++ if (!ram_cmp)
++ return true;
+
+- bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD;
++ address = ram_addr;
++ offset = 0;
++ while (offset < ram_sz) {
++ len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
++ ram_sz - offset;
++ err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
++ if (err) {
++ brcmf_err("error %d on reading %d membytes at 0x%08x\n",
++ err, len, address);
++ ret = false;
++ break;
++ } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
++ brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
++ offset, len);
++ ret = false;
++ break;
++ }
++ offset += len;
++ address += len;
+ }
+
+- return true;
+-}
++ kfree(ram_cmp);
+
+-static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_sdio *bus)
++ return ret;
++}
++#else /* DEBUG */
++static bool
++brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
++ u8 *ram_data, uint ram_sz)
+ {
+- if (bus->firmware->size < bus->fw_ptr + len)
+- len = bus->firmware->size - bus->fw_ptr;
+-
+- memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
+- bus->fw_ptr += len;
+- return len;
++ return true;
+ }
++#endif /* DEBUG */
+
+-static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus)
++static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
++ const struct firmware *fw)
+ {
++ int err;
+ int offset;
+- uint len;
+- u8 *memblock = NULL, *memptr;
+- int ret;
+- u8 idx;
++ int address;
++ int len;
+
+- brcmf_dbg(INFO, "Enter\n");
+-
+- ret = request_firmware(&bus->firmware, BRCMF_SDIO_FW_NAME,
+- &bus->sdiodev->func[2]->dev);
+- if (ret) {
+- brcmf_err("Fail to request firmware %d\n", ret);
+- return ret;
+- }
+- bus->fw_ptr = 0;
++ brcmf_dbg(TRACE, "Enter\n");
+
+- memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
+- if (memblock == NULL) {
+- ret = -ENOMEM;
+- goto err;
+- }
+- if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
+- memptr += (BRCMF_SDALIGN -
+- ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
+-
+- offset = bus->ci->rambase;
+-
+- /* Download image */
+- len = brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus);
+- idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_ARM_CR4);
+- if (BRCMF_MAX_CORENUM != idx)
+- memcpy(&bus->ci->rst_vec, memptr, sizeof(bus->ci->rst_vec));
+- while (len) {
+- ret = brcmf_sdio_ramrw(bus->sdiodev, true, offset, memptr, len);
+- if (ret) {
++ err = 0;
++ offset = 0;
++ address = bus->ci->rambase;
++ while (offset < fw->size) {
++ len = ((offset + MEMBLOCK) < fw->size) ? MEMBLOCK :
++ fw->size - offset;
++ err = brcmf_sdiod_ramrw(bus->sdiodev, true, address,
++ (u8 *)&fw->data[offset], len);
++ if (err) {
+ brcmf_err("error %d on writing %d membytes at 0x%08x\n",
+- ret, MEMBLOCK, offset);
+- goto err;
++ err, len, address);
++ return err;
+ }
+-
+- offset += MEMBLOCK;
+- len = brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus);
++ offset += len;
++ address += len;
+ }
++ if (!err)
++ if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
++ (u8 *)fw->data, fw->size))
++ err = -EIO;
+
+-err:
+- kfree(memblock);
++ return err;
++}
+
+- release_firmware(bus->firmware);
+- bus->fw_ptr = 0;
++static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
++ const struct firmware *nv)
++{
++ void *vars;
++ u32 varsz;
++ int address;
++ int err;
+
+- return ret;
+-}
++ brcmf_dbg(TRACE, "Enter\n");
+
+-/*
+- * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
+- * and ending in a NUL.
+- * Removes carriage returns, empty lines, comment lines, and converts
+- * newlines to NULs.
+- * Shortens buffer as needed and pads with NULs. End of buffer is marked
+- * by two NULs.
+-*/
+-
+-static int brcmf_process_nvram_vars(struct brcmf_sdio *bus)
+-{
+- char *varbuf;
+- char *dp;
+- bool findNewline;
+- int column;
+- int ret = 0;
+- uint buf_len, n, len;
+-
+- len = bus->firmware->size;
+- varbuf = vmalloc(len);
+- if (!varbuf)
+- return -ENOMEM;
++ vars = brcmf_nvram_strip(nv, &varsz);
+
+- memcpy(varbuf, bus->firmware->data, len);
+- dp = varbuf;
++ if (vars == NULL)
++ return -EINVAL;
+
+- findNewline = false;
+- column = 0;
++ address = bus->ci->ramsize - varsz + bus->ci->rambase;
++ err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
++ if (err)
++ brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
++ err, varsz, address);
++ else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
++ err = -EIO;
+
+- for (n = 0; n < len; n++) {
+- if (varbuf[n] == 0)
+- break;
+- if (varbuf[n] == '\r')
+- continue;
+- if (findNewline && varbuf[n] != '\n')
+- continue;
+- findNewline = false;
+- if (varbuf[n] == '#') {
+- findNewline = true;
+- continue;
+- }
+- if (varbuf[n] == '\n') {
+- if (column == 0)
+- continue;
+- *dp++ = 0;
+- column = 0;
+- continue;
+- }
+- *dp++ = varbuf[n];
+- column++;
+- }
+- buf_len = dp - varbuf;
+- while (dp < varbuf + n)
+- *dp++ = 0;
+-
+- kfree(bus->vars);
+- /* roundup needed for download to device */
+- bus->varsz = roundup(buf_len + 1, 4);
+- bus->vars = kmalloc(bus->varsz, GFP_KERNEL);
+- if (bus->vars == NULL) {
+- bus->varsz = 0;
+- ret = -ENOMEM;
+- goto err;
+- }
++ brcmf_nvram_free(vars);
+
+- /* copy the processed variables and add null termination */
+- memcpy(bus->vars, varbuf, buf_len);
+- bus->vars[buf_len] = 0;
+-err:
+- vfree(varbuf);
+- return ret;
++ return err;
+ }
+
+-static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus)
++static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus)
+ {
+- int ret;
+-
+- ret = request_firmware(&bus->firmware, BRCMF_SDIO_NV_NAME,
+- &bus->sdiodev->func[2]->dev);
+- if (ret) {
+- brcmf_err("Fail to request nvram %d\n", ret);
+- return ret;
+- }
++ int bcmerror = -EFAULT;
++ const struct firmware *fw;
++ u32 rstvec;
+
+- ret = brcmf_process_nvram_vars(bus);
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
+
+- release_firmware(bus->firmware);
++ /* Keep arm in reset */
++ brcmf_sdio_chip_enter_download(bus->sdiodev, bus->ci);
+
+- return ret;
+-}
++ fw = brcmf_sdio_get_fw(bus, BRCMF_FIRMWARE_BIN);
++ if (fw == NULL) {
++ bcmerror = -ENOENT;
++ goto err;
++ }
+
+-static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
+-{
+- int bcmerror = -1;
++ rstvec = get_unaligned_le32(fw->data);
++ brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
+
+- /* Keep arm in reset */
+- if (!brcmf_sdbrcm_download_state(bus, true)) {
+- brcmf_err("error placing ARM core in reset\n");
++ bcmerror = brcmf_sdio_download_code_file(bus, fw);
++ release_firmware(fw);
++ if (bcmerror) {
++ brcmf_err("dongle image file download failed\n");
+ goto err;
+ }
+
+- if (brcmf_sdbrcm_download_code_file(bus)) {
+- brcmf_err("dongle image file download failed\n");
++ fw = brcmf_sdio_get_fw(bus, BRCMF_FIRMWARE_NVRAM);
++ if (fw == NULL) {
++ bcmerror = -ENOENT;
+ goto err;
+ }
+
+- if (brcmf_sdbrcm_download_nvram(bus)) {
++ bcmerror = brcmf_sdio_download_nvram(bus, fw);
++ release_firmware(fw);
++ if (bcmerror) {
+ brcmf_err("dongle nvram file download failed\n");
+ goto err;
+ }
+
+ /* Take arm out of reset */
+- if (!brcmf_sdbrcm_download_state(bus, false)) {
++ if (!brcmf_sdio_chip_exit_download(bus->sdiodev, bus->ci, rstvec)) {
+ brcmf_err("error getting out of ARM core reset\n");
+ goto err;
+ }
+
++ /* Allow HT Clock now that the ARM is running. */
++ brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_LOAD);
+ bcmerror = 0;
+
+ err:
++ brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
++ sdio_release_host(bus->sdiodev->func[1]);
+ return bcmerror;
+ }
+
+-static bool brcmf_sdbrcm_sr_capable(struct brcmf_sdio *bus)
++static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus)
+ {
+- u32 addr, reg;
++ u32 addr, reg, pmu_cc3_mask = ~0;
++ int err;
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+@@ -3213,49 +3349,61 @@
+ if (bus->ci->pmurev < 17)
+ return false;
+
+- /* read PMU chipcontrol register 3*/
+- addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr);
+- brcmf_sdio_regwl(bus->sdiodev, addr, 3, NULL);
+- addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data);
+- reg = brcmf_sdio_regrl(bus->sdiodev, addr, NULL);
++ switch (bus->ci->chip) {
++ case BCM43241_CHIP_ID:
++ case BCM4335_CHIP_ID:
++ case BCM4339_CHIP_ID:
++ /* read PMU chipcontrol register 3 */
++ addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr);
++ brcmf_sdiod_regwl(bus->sdiodev, addr, 3, NULL);
++ addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data);
++ reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
++ return (reg & pmu_cc3_mask) != 0;
++ default:
++ addr = CORE_CC_REG(bus->ci->c_inf[0].base, pmucapabilities_ext);
++ reg = brcmf_sdiod_regrl(bus->sdiodev, addr, &err);
++ if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
++ return false;
+
+- return (bool)reg;
++ addr = CORE_CC_REG(bus->ci->c_inf[0].base, retention_ctl);
++ reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
++ return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
++ PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
++ }
+ }
+
+-static void brcmf_sdbrcm_sr_init(struct brcmf_sdio *bus)
++static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
+ {
+ int err = 0;
+ u8 val;
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+- val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL,
+- &err);
++ val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
+ if (err) {
+ brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
+ return;
+ }
+
+ val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL,
+- val, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
+ if (err) {
+ brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
+ return;
+ }
+
+ /* Add CMD14 Support */
+- brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
+- (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
+- SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
+- &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
++ (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
++ SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
++ &err);
+ if (err) {
+ brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
+ return;
+ }
+
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- SBSDIO_FORCE_HT, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ SBSDIO_FORCE_HT, &err);
+ if (err) {
+ brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
+ return;
+@@ -3267,7 +3415,7 @@
+ }
+
+ /* enable KSO bit */
+-static int brcmf_sdbrcm_kso_init(struct brcmf_sdio *bus)
++static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
+ {
+ u8 val;
+ int err = 0;
+@@ -3278,8 +3426,7 @@
+ if (bus->ci->c_inf[1].rev < 12)
+ return 0;
+
+- val = brcmf_sdio_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- &err);
++ val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
+ if (err) {
+ brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
+ return err;
+@@ -3288,8 +3435,8 @@
+ if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
+ val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
+ SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- val, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
++ val, &err);
+ if (err) {
+ brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
+ return err;
+@@ -3300,31 +3447,70 @@
+ }
+
+
+-static bool
+-brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
++static int brcmf_sdio_bus_preinit(struct device *dev)
+ {
+- bool ret;
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio *bus = sdiodev->bus;
++ uint pad_size;
++ u32 value;
++ u8 idx;
++ int err;
+
+- brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
++ /* the commands below use the terms tx and rx from
++ * a device perspective, ie. bus:txglom affects the
++ * bus transfers from device to host.
++ */
++ idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
++ if (bus->ci->c_inf[idx].rev < 12) {
++ /* for sdio core rev < 12, disable txgloming */
++ value = 0;
++ err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
++ sizeof(u32));
++ } else {
++ /* otherwise, set txglomalign */
++ value = 4;
++ if (sdiodev->pdata)
++ value = sdiodev->pdata->sd_sgentry_align;
++ /* SDIO ADMA requires at least 32 bit alignment */
++ value = max_t(u32, value, 4);
++ err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
++ sizeof(u32));
++ }
+
+- ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
++ if (err < 0)
++ goto done;
+
+- brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
++ bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
++ if (sdiodev->sg_support) {
++ bus->txglom = false;
++ value = 1;
++ pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
++ bus->txglom_sgpad = brcmu_pkt_buf_get_skb(pad_size);
++ if (!bus->txglom_sgpad)
++ brcmf_err("allocating txglom padding skb failed, reduced performance\n");
+
+- sdio_release_host(bus->sdiodev->func[1]);
++ err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
++ &value, sizeof(u32));
++ if (err < 0) {
++ /* bus:rxglom is allowed to fail */
++ err = 0;
++ } else {
++ bus->txglom = true;
++ bus->tx_hdrlen += SDPCM_HWEXT_LEN;
++ }
++ }
++ brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
+
+- return ret;
++done:
++ return err;
+ }
+
+-static int brcmf_sdbrcm_bus_init(struct device *dev)
++static int brcmf_sdio_bus_init(struct device *dev)
+ {
+ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+ struct brcmf_sdio *bus = sdiodev->bus;
+- unsigned long timeout;
+- u8 ready, enable;
+ int err, ret = 0;
+ u8 saveclk;
+
+@@ -3332,8 +3518,11 @@
+
+ /* try to download image and nvram to the dongle */
+ if (bus_if->state == BRCMF_BUS_DOWN) {
+- if (!(brcmf_sdbrcm_download_firmware(bus)))
+- return -1;
++ bus->alp_only = true;
++ err = brcmf_sdio_download_firmware(bus);
++ if (err)
++ return err;
++ bus->alp_only = false;
+ }
+
+ if (!bus->sdiodev->bus_if->drvr)
+@@ -3341,21 +3530,21 @@
+
+ /* Start the watchdog timer */
+ bus->sdcnt.tickcnt = 0;
+- brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
++ brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+
+ sdio_claim_host(bus->sdiodev->func[1]);
+
+ /* Make sure backplane clock is on, needed to generate F2 interrupt */
+- brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
++ brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
+ if (bus->clkstate != CLK_AVAIL)
+ goto exit;
+
+ /* Force clocks on backplane to be sure F2 interrupt propagates */
+- saveclk = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
++ saveclk = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, &err);
+ if (!err) {
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- (saveclk | SBSDIO_FORCE_HT), &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ (saveclk | SBSDIO_FORCE_HT), &err);
+ }
+ if (err) {
+ brcmf_err("Failed to force clock for F2: err %d\n", err);
+@@ -3365,56 +3554,42 @@
+ /* Enable function 2 (frame transfers) */
+ w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
+ offsetof(struct sdpcmd_regs, tosbmailboxdata));
+- enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
++ err = sdio_enable_func(bus->sdiodev->func[SDIO_FUNC_2]);
+
+- brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL);
+
+- timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
+- ready = 0;
+- while (enable != ready) {
+- ready = brcmf_sdio_regrb(bus->sdiodev,
+- SDIO_CCCR_IORx, NULL);
+- if (time_after(jiffies, timeout))
+- break;
+- else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
+- /* prevent busy waiting if it takes too long */
+- msleep_interruptible(20);
+- }
+-
+- brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
++ brcmf_dbg(INFO, "enable F2: err=%d\n", err);
+
+ /* If F2 successfully enabled, set core and enable interrupts */
+- if (ready == enable) {
++ if (!err) {
+ /* Set up the interrupt mask and enable interrupts */
+ bus->hostintmask = HOSTINTMASK;
+ w_sdreg32(bus, bus->hostintmask,
+ offsetof(struct sdpcmd_regs, hostintmask));
+
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err);
+ } else {
+ /* Disable F2 again */
+- enable = SDIO_FUNC_ENABLE_1;
+- brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx, enable, NULL);
++ sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
+ ret = -ENODEV;
+ }
+
+- if (brcmf_sdbrcm_sr_capable(bus)) {
+- brcmf_sdbrcm_sr_init(bus);
++ if (brcmf_sdio_sr_capable(bus)) {
++ brcmf_sdio_sr_init(bus);
+ } else {
+ /* Restore previous clock setting */
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- saveclk, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ saveclk, &err);
+ }
+
+ if (ret == 0) {
+- ret = brcmf_sdio_intr_register(bus->sdiodev);
++ ret = brcmf_sdiod_intr_register(bus->sdiodev);
+ if (ret != 0)
+ brcmf_err("intr register failed:%d\n", ret);
+ }
+
+ /* If we didn't come up, turn off backplane clock */
+- if (bus_if->state != BRCMF_BUS_DATA)
+- brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
++ if (ret != 0)
++ brcmf_sdio_clkctl(bus, CLK_NONE, false);
+
+ exit:
+ sdio_release_host(bus->sdiodev->func[1]);
+@@ -3422,10 +3597,8 @@
+ return ret;
+ }
+
+-void brcmf_sdbrcm_isr(void *arg)
++void brcmf_sdio_isr(struct brcmf_sdio *bus)
+ {
+- struct brcmf_sdio *bus = (struct brcmf_sdio *) arg;
+-
+ brcmf_dbg(TRACE, "Enter\n");
+
+ if (!bus) {
+@@ -3433,7 +3606,7 @@
+ return;
+ }
+
+- if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
++ if (!brcmf_bus_ready(bus->sdiodev->bus_if)) {
+ brcmf_err("bus is down. we have nothing to do\n");
+ return;
+ }
+@@ -3444,23 +3617,21 @@
+ else
+ if (brcmf_sdio_intr_rstatus(bus)) {
+ brcmf_err("failed backplane access\n");
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
+ }
+
+ /* Disable additional interrupts (is this needed now)? */
+ if (!bus->intr)
+ brcmf_err("isr w/o interrupt configured!\n");
+
+- brcmf_sdbrcm_adddpctsk(bus);
++ atomic_inc(&bus->dpc_tskcnt);
+ queue_work(bus->brcmf_wq, &bus->datawork);
+ }
+
+-static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
++static bool brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
+ {
+ #ifdef DEBUG
+ struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
+ #endif /* DEBUG */
+- unsigned long flags;
+
+ brcmf_dbg(TIMER, "Enter\n");
+
+@@ -3476,22 +3647,17 @@
+ if (!bus->intr ||
+ (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
+
+- spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+- if (list_empty(&bus->dpc_tsklst)) {
++ if (atomic_read(&bus->dpc_tskcnt) == 0) {
+ u8 devpend;
+- spin_unlock_irqrestore(&bus->dpc_tl_lock,
+- flags);
++
+ sdio_claim_host(bus->sdiodev->func[1]);
+- devpend = brcmf_sdio_regrb(bus->sdiodev,
+- SDIO_CCCR_INTx,
+- NULL);
++ devpend = brcmf_sdiod_regrb(bus->sdiodev,
++ SDIO_CCCR_INTx,
++ NULL);
+ sdio_release_host(bus->sdiodev->func[1]);
+ intstatus =
+ devpend & (INTR_STATUS_FUNC1 |
+ INTR_STATUS_FUNC2);
+- } else {
+- spin_unlock_irqrestore(&bus->dpc_tl_lock,
+- flags);
+ }
+
+ /* If there is something, make like the ISR and
+@@ -3500,7 +3666,7 @@
+ bus->sdcnt.pollcnt++;
+ atomic_set(&bus->ipend, 1);
+
+- brcmf_sdbrcm_adddpctsk(bus);
++ atomic_inc(&bus->dpc_tskcnt);
+ queue_work(bus->brcmf_wq, &bus->datawork);
+ }
+ }
+@@ -3517,8 +3683,8 @@
+ bus->console.count -= bus->console_interval;
+ sdio_claim_host(bus->sdiodev->func[1]);
+ /* Make sure backplane clock is on */
+- brcmf_sdbrcm_bus_sleep(bus, false, false);
+- if (brcmf_sdbrcm_readconsole(bus) < 0)
++ brcmf_sdio_bus_sleep(bus, false, false);
++ if (brcmf_sdio_readconsole(bus) < 0)
+ /* stop on error */
+ bus->console_interval = 0;
+ sdio_release_host(bus->sdiodev->func[1]);
+@@ -3532,11 +3698,11 @@
+ bus->idlecount = 0;
+ if (bus->activity) {
+ bus->activity = false;
+- brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
++ brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+ } else {
+ brcmf_dbg(SDIO, "idle\n");
+ sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdbrcm_bus_sleep(bus, true, false);
++ brcmf_sdio_bus_sleep(bus, true, false);
+ sdio_release_host(bus->sdiodev->func[1]);
+ }
+ }
+@@ -3545,92 +3711,19 @@
+ return (atomic_read(&bus->ipend) > 0);
+ }
+
+-static bool brcmf_sdbrcm_chipmatch(u16 chipid)
+-{
+- if (chipid == BCM43143_CHIP_ID)
+- return true;
+- if (chipid == BCM43241_CHIP_ID)
+- return true;
+- if (chipid == BCM4329_CHIP_ID)
+- return true;
+- if (chipid == BCM4330_CHIP_ID)
+- return true;
+- if (chipid == BCM4334_CHIP_ID)
+- return true;
+- if (chipid == BCM4335_CHIP_ID)
+- return true;
+- return false;
+-}
+-
+ static void brcmf_sdio_dataworker(struct work_struct *work)
+ {
+ struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
+ datawork);
+- struct list_head *cur_hd, *tmp_hd;
+- unsigned long flags;
+
+- spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+- list_for_each_safe(cur_hd, tmp_hd, &bus->dpc_tsklst) {
+- spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+-
+- brcmf_sdbrcm_dpc(bus);
+-
+- spin_lock_irqsave(&bus->dpc_tl_lock, flags);
+- list_del(cur_hd);
+- kfree(cur_hd);
++ while (atomic_read(&bus->dpc_tskcnt)) {
++ brcmf_sdio_dpc(bus);
++ atomic_dec(&bus->dpc_tskcnt);
+ }
+- spin_unlock_irqrestore(&bus->dpc_tl_lock, flags);
+-}
+-
+-static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- kfree(bus->rxbuf);
+- bus->rxctl = bus->rxbuf = NULL;
+- bus->rxlen = 0;
+-
+- kfree(bus->databuf);
+- bus->databuf = NULL;
+-}
+-
+-static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (bus->sdiodev->bus_if->maxctl) {
+- bus->rxblen =
+- roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
+- ALIGNMENT) + BRCMF_SDALIGN;
+- bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
+- if (!(bus->rxbuf))
+- goto fail;
+- }
+-
+- /* Allocate buffer to receive glomed packet */
+- bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
+- if (!(bus->databuf)) {
+- /* release rxbuf which was already located as above */
+- if (!bus->rxblen)
+- kfree(bus->rxbuf);
+- goto fail;
+- }
+-
+- /* Align the buffer */
+- if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
+- bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
+- ((unsigned long)bus->databuf % BRCMF_SDALIGN));
+- else
+- bus->dataptr = bus->databuf;
+-
+- return true;
+-
+-fail:
+- return false;
+ }
+
+ static bool
+-brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva)
++brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
+ {
+ u8 clkctl = 0;
+ int err = 0;
+@@ -3638,23 +3731,21 @@
+ u32 reg_val;
+ u32 drivestrength;
+
+- bus->alp_only = true;
+-
+ sdio_claim_host(bus->sdiodev->func[1]);
+
+ pr_debug("F1 signature read @0x18000000=0x%4x\n",
+- brcmf_sdio_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
++ brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
+
+ /*
+ * Force PLL off until brcmf_sdio_chip_attach()
+ * programs PLL control regs
+ */
+
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- BRCMF_INIT_CLKCTL1, &err);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ BRCMF_INIT_CLKCTL1, &err);
+ if (!err)
+- clkctl = brcmf_sdio_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
++ clkctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, &err);
+
+ if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
+ brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
+@@ -3662,17 +3753,17 @@
+ goto fail;
+ }
+
+- if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
+- brcmf_err("brcmf_sdio_chip_attach failed!\n");
+- goto fail;
+- }
++ /* SDIO register access works so moving
++ * state from UNKNOWN to DOWN.
++ */
++ brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_DOWN);
+
+- if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
+- brcmf_err("unsupported chip: 0x%04x\n", bus->ci->chip);
++ if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci)) {
++ brcmf_err("brcmf_sdio_chip_attach failed!\n");
+ goto fail;
+ }
+
+- if (brcmf_sdbrcm_kso_init(bus)) {
++ if (brcmf_sdio_kso_init(bus)) {
+ brcmf_err("error enabling KSO\n");
+ goto fail;
+ }
+@@ -3691,33 +3782,33 @@
+ }
+
+ /* Set card control so an SDIO card reset does a WLAN backplane reset */
+- reg_val = brcmf_sdio_regrb(bus->sdiodev,
+- SDIO_CCCR_BRCM_CARDCTRL, &err);
++ reg_val = brcmf_sdiod_regrb(bus->sdiodev,
++ SDIO_CCCR_BRCM_CARDCTRL, &err);
+ if (err)
+ goto fail;
+
+ reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
+
+- brcmf_sdio_regwb(bus->sdiodev,
+- SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
++ brcmf_sdiod_regwb(bus->sdiodev,
++ SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
+ if (err)
+ goto fail;
+
+ /* set PMUControl so a backplane reset does PMU state reload */
+ reg_addr = CORE_CC_REG(bus->ci->c_inf[0].base,
+ pmucontrol);
+- reg_val = brcmf_sdio_regrl(bus->sdiodev,
+- reg_addr,
+- &err);
++ reg_val = brcmf_sdiod_regrl(bus->sdiodev,
++ reg_addr,
++ &err);
+ if (err)
+ goto fail;
+
+ reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
+
+- brcmf_sdio_regwl(bus->sdiodev,
+- reg_addr,
+- reg_val,
+- &err);
++ brcmf_sdiod_regwl(bus->sdiodev,
++ reg_addr,
++ reg_val,
++ &err);
+ if (err)
+ goto fail;
+
+@@ -3726,9 +3817,13 @@
+
+ brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
+
++ /* allocate header buffer */
++ bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
++ if (!bus->hdrbuf)
++ return false;
+ /* Locate an appropriately-aligned portion of hdrbuf */
+ bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
+- BRCMF_SDALIGN);
++ bus->head_align);
+
+ /* Set the poll and/or interrupt flags */
+ bus->intr = true;
+@@ -3743,46 +3838,8 @@
+ return false;
+ }
+
+-static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+-
+- /* Disable F2 to clear any intermediate frame state on the dongle */
+- brcmf_sdio_regwb(bus->sdiodev, SDIO_CCCR_IOEx,
+- SDIO_FUNC_ENABLE_1, NULL);
+-
+- bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
+- bus->rxflow = false;
+-
+- /* Done with backplane-dependent accesses, can drop clock... */
+- brcmf_sdio_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
+-
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+- /* ...and initialize clock/power states */
+- bus->clkstate = CLK_SDONLY;
+- bus->idletime = BRCMF_IDLE_INTERVAL;
+- bus->idleclock = BRCMF_IDLE_ACTIVE;
+-
+- /* Query the F2 block size, set roundup accordingly */
+- bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
+- bus->roundup = min(max_roundup, bus->blocksize);
+-
+- /* bus module does not support packet chaining */
+- bus->use_rxchain = false;
+- bus->sd_rxchain = false;
+-
+- /* SR state */
+- bus->sleeping = false;
+- bus->sr_enabled = false;
+-
+- return true;
+-}
+-
+ static int
+-brcmf_sdbrcm_watchdog_thread(void *data)
++brcmf_sdio_watchdog_thread(void *data)
+ {
+ struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
+
+@@ -3792,7 +3849,7 @@
+ if (kthread_should_stop())
+ break;
+ if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
+- brcmf_sdbrcm_bus_watchdog(bus);
++ brcmf_sdio_bus_watchdog(bus);
+ /* Count the tick for reference */
+ bus->sdcnt.tickcnt++;
+ } else
+@@ -3802,7 +3859,7 @@
+ }
+
+ static void
+-brcmf_sdbrcm_watchdog(unsigned long data)
++brcmf_sdio_watchdog(unsigned long data)
+ {
+ struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
+
+@@ -3815,73 +3872,23 @@
+ }
+ }
+
+-static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (bus->ci) {
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
+- brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
+- sdio_release_host(bus->sdiodev->func[1]);
+- brcmf_sdio_chip_detach(&bus->ci);
+- if (bus->vars && bus->varsz)
+- kfree(bus->vars);
+- bus->vars = NULL;
+- }
+-
+- brcmf_dbg(TRACE, "Disconnected\n");
+-}
+-
+-/* Detach and free everything */
+-static void brcmf_sdbrcm_release(struct brcmf_sdio *bus)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (bus) {
+- /* De-register interrupt handler */
+- brcmf_sdio_intr_unregister(bus->sdiodev);
+-
+- cancel_work_sync(&bus->datawork);
+- if (bus->brcmf_wq)
+- destroy_workqueue(bus->brcmf_wq);
+-
+- if (bus->sdiodev->bus_if->drvr) {
+- brcmf_detach(bus->sdiodev->dev);
+- brcmf_sdbrcm_release_dongle(bus);
+- }
+-
+- brcmf_sdbrcm_release_malloc(bus);
+-
+- kfree(bus);
+- }
+-
+- brcmf_dbg(TRACE, "Disconnected\n");
+-}
+-
+ static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
+- .stop = brcmf_sdbrcm_bus_stop,
+- .init = brcmf_sdbrcm_bus_init,
+- .txdata = brcmf_sdbrcm_bus_txdata,
+- .txctl = brcmf_sdbrcm_bus_txctl,
+- .rxctl = brcmf_sdbrcm_bus_rxctl,
+- .gettxq = brcmf_sdbrcm_bus_gettxq,
++ .stop = brcmf_sdio_bus_stop,
++ .preinit = brcmf_sdio_bus_preinit,
++ .init = brcmf_sdio_bus_init,
++ .txdata = brcmf_sdio_bus_txdata,
++ .txctl = brcmf_sdio_bus_txctl,
++ .rxctl = brcmf_sdio_bus_rxctl,
++ .gettxq = brcmf_sdio_bus_gettxq,
+ };
+
+-void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
++struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
+ {
+ int ret;
+ struct brcmf_sdio *bus;
+- struct brcmf_bus_dcmd *dlst;
+- u32 dngl_txglom;
+- u32 dngl_txglomalign;
+- u8 idx;
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+- /* We make an assumption about address window mappings:
+- * regsva == SI_ENUM_BASE*/
+-
+ /* Allocate private bus interface state */
+ bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
+ if (!bus)
+@@ -3893,7 +3900,19 @@
+ bus->txbound = BRCMF_TXBOUND;
+ bus->rxbound = BRCMF_RXBOUND;
+ bus->txminmax = BRCMF_TXMINMAX;
+- bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
++ bus->tx_seq = SDPCM_SEQ_WRAP - 1;
++
++ /* platform specific configuration:
++ * alignments must be at least 4 bytes for ADMA
++ */
++ bus->head_align = ALIGNMENT;
++ bus->sgentry_align = ALIGNMENT;
++ if (sdiodev->pdata) {
++ if (sdiodev->pdata->sd_head_align > ALIGNMENT)
++ bus->head_align = sdiodev->pdata->sd_head_align;
++ if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
++ bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
++ }
+
+ INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
+ bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq");
+@@ -3903,8 +3922,8 @@
+ }
+
+ /* attempt to attach to the dongle */
+- if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
+- brcmf_err("brcmf_sdbrcm_probe_attach failed\n");
++ if (!(brcmf_sdio_probe_attach(bus))) {
++ brcmf_err("brcmf_sdio_probe_attach failed\n");
+ goto fail;
+ }
+
+@@ -3916,19 +3935,18 @@
+ /* Set up the watchdog timer */
+ init_timer(&bus->timer);
+ bus->timer.data = (unsigned long)bus;
+- bus->timer.function = brcmf_sdbrcm_watchdog;
++ bus->timer.function = brcmf_sdio_watchdog;
+
+ /* Initialize watchdog thread */
+ init_completion(&bus->watchdog_wait);
+- bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
++ bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
+ bus, "brcmf_watchdog");
+ if (IS_ERR(bus->watchdog_tsk)) {
+ pr_warn("brcmf_watchdog thread failed to start\n");
+ bus->watchdog_tsk = NULL;
+ }
+ /* Initialize DPC thread */
+- INIT_LIST_HEAD(&bus->dpc_tsklst);
+- spin_lock_init(&bus->dpc_tl_lock);
++ atomic_set(&bus->dpc_tskcnt, 0);
+
+ /* Assign bus interface call back */
+ bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
+@@ -3936,47 +3954,56 @@
+ bus->sdiodev->bus_if->chip = bus->ci->chip;
+ bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
+
+- /* Attach to the brcmf/OS/network interface */
+- ret = brcmf_attach(SDPCM_RESERVE, bus->sdiodev->dev);
++ /* default sdio bus header length for tx packet */
++ bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
++
++ /* Attach to the common layer, reserve hdr space */
++ ret = brcmf_attach(bus->sdiodev->dev);
+ if (ret != 0) {
+ brcmf_err("brcmf_attach failed\n");
+ goto fail;
+ }
+
+ /* Allocate buffers */
+- if (!(brcmf_sdbrcm_probe_malloc(bus))) {
+- brcmf_err("brcmf_sdbrcm_probe_malloc failed\n");
+- goto fail;
++ if (bus->sdiodev->bus_if->maxctl) {
++ bus->rxblen =
++ roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
++ ALIGNMENT) + bus->head_align;
++ bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
++ if (!(bus->rxbuf)) {
++ brcmf_err("rxbuf allocation failed\n");
++ goto fail;
++ }
+ }
+
+- if (!(brcmf_sdbrcm_probe_init(bus))) {
+- brcmf_err("brcmf_sdbrcm_probe_init failed\n");
+- goto fail;
+- }
++ sdio_claim_host(bus->sdiodev->func[1]);
++
++ /* Disable F2 to clear any intermediate frame state on the dongle */
++ sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
++
++ bus->rxflow = false;
++
++ /* Done with backplane-dependent accesses, can drop clock... */
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
++
++ sdio_release_host(bus->sdiodev->func[1]);
++
++ /* ...and initialize clock/power states */
++ bus->clkstate = CLK_SDONLY;
++ bus->idletime = BRCMF_IDLE_INTERVAL;
++ bus->idleclock = BRCMF_IDLE_ACTIVE;
++
++ /* Query the F2 block size, set roundup accordingly */
++ bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
++ bus->roundup = min(max_roundup, bus->blocksize);
++
++ /* SR state */
++ bus->sleeping = false;
++ bus->sr_enabled = false;
+
+ brcmf_sdio_debugfs_create(bus);
+ brcmf_dbg(INFO, "completed!!\n");
+
+- /* sdio bus core specific dcmd */
+- idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
+- dlst = kzalloc(sizeof(struct brcmf_bus_dcmd), GFP_KERNEL);
+- if (dlst) {
+- if (bus->ci->c_inf[idx].rev < 12) {
+- /* for sdio core rev < 12, disable txgloming */
+- dngl_txglom = 0;
+- dlst->name = "bus:txglom";
+- dlst->param = (char *)&dngl_txglom;
+- dlst->param_len = sizeof(u32);
+- } else {
+- /* otherwise, set txglomalign */
+- dngl_txglomalign = bus->sdiodev->bus_if->align;
+- dlst->name = "bus:txglomalign";
+- dlst->param = (char *)&dngl_txglomalign;
+- dlst->param_len = sizeof(u32);
+- }
+- list_add(&dlst->list, &bus->sdiodev->bus_if->dcmd_list);
+- }
+-
+ /* if firmware path present try to download and bring up bus */
+ ret = brcmf_bus_start(bus->sdiodev->dev);
+ if (ret != 0) {
+@@ -3987,24 +4014,55 @@
+ return bus;
+
+ fail:
+- brcmf_sdbrcm_release(bus);
++ brcmf_sdio_remove(bus);
+ return NULL;
+ }
+
+-void brcmf_sdbrcm_disconnect(void *ptr)
++/* Detach and free everything */
++void brcmf_sdio_remove(struct brcmf_sdio *bus)
+ {
+- struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr;
+-
+ brcmf_dbg(TRACE, "Enter\n");
+
+- if (bus)
+- brcmf_sdbrcm_release(bus);
++ if (bus) {
++ /* De-register interrupt handler */
++ brcmf_sdiod_intr_unregister(bus->sdiodev);
++
++ cancel_work_sync(&bus->datawork);
++ if (bus->brcmf_wq)
++ destroy_workqueue(bus->brcmf_wq);
++
++ if (bus->sdiodev->bus_if->drvr) {
++ brcmf_detach(bus->sdiodev->dev);
++ }
++
++ if (bus->ci) {
++ if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
++ /* Leave the device in state where it is
++ * 'quiet'. This is done by putting it in
++ * download_state which essentially resets
++ * all necessary cores.
++ */
++ msleep(20);
++ brcmf_sdio_chip_enter_download(bus->sdiodev,
++ bus->ci);
++ brcmf_sdio_clkctl(bus, CLK_NONE, false);
++ sdio_release_host(bus->sdiodev->func[1]);
++ }
++ brcmf_sdio_chip_detach(&bus->ci);
++ }
++
++ brcmu_pkt_buf_free_skb(bus->txglom_sgpad);
++ kfree(bus->rxbuf);
++ kfree(bus->hdrbuf);
++ kfree(bus);
++ }
+
+ brcmf_dbg(TRACE, "Disconnected\n");
+ }
+
+-void
+-brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick)
++void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
+ {
+ /* Totally stop the timer */
+ if (!wdtick && bus->wd_timer_valid) {
+@@ -4015,7 +4073,7 @@
+ }
+
+ /* don't start the wd until fw is loaded */
+- if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN)
++ if (bus->sdiodev->bus_if->state != BRCMF_BUS_DATA)
+ return;
+
+ if (wdtick) {
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fweh.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fweh.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fweh.c 2014-05-15 20:34:00.554032284 +0200
+@@ -185,6 +185,10 @@
+ ifevent->action, ifevent->ifidx, ifevent->bssidx,
+ ifevent->flags, ifevent->role);
+
++ if (ifevent->flags & BRCMF_E_IF_FLAG_NOIF) {
++ brcmf_dbg(EVENT, "event can be ignored\n");
++ return;
++ }
+ if (ifevent->ifidx >= BRCMF_MAX_IFS) {
+ brcmf_err("invalid interface index: %u\n",
+ ifevent->ifidx);
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fweh.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fweh.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fweh.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fweh.h 2014-05-15 20:34:00.554032284 +0200
+@@ -101,7 +101,9 @@
+ BRCMF_ENUM_DEF(P2P_PROBEREQ_MSG, 72) \
+ BRCMF_ENUM_DEF(DCS_REQUEST, 73) \
+ BRCMF_ENUM_DEF(FIFO_CREDIT_MAP, 74) \
+- BRCMF_ENUM_DEF(ACTION_FRAME_RX, 75)
++ BRCMF_ENUM_DEF(ACTION_FRAME_RX, 75) \
++ BRCMF_ENUM_DEF(BCMC_CREDIT_SUPPORT, 127) \
++ BRCMF_ENUM_DEF(PSTA_PRIMARY_INTF_IND, 128)
+
+ #define BRCMF_ENUM_DEF(id, val) \
+ BRCMF_E_##id = (val),
+@@ -113,11 +115,59 @@
+ };
+ #undef BRCMF_ENUM_DEF
+
++#define BRCMF_EVENTING_MASK_LEN DIV_ROUND_UP(BRCMF_E_LAST, 8)
++
+ /* flags field values in struct brcmf_event_msg */
+ #define BRCMF_EVENT_MSG_LINK 0x01
+ #define BRCMF_EVENT_MSG_FLUSHTXQ 0x02
+ #define BRCMF_EVENT_MSG_GROUP 0x04
+
++/* status field values in struct brcmf_event_msg */
++#define BRCMF_E_STATUS_SUCCESS 0
++#define BRCMF_E_STATUS_FAIL 1
++#define BRCMF_E_STATUS_TIMEOUT 2
++#define BRCMF_E_STATUS_NO_NETWORKS 3
++#define BRCMF_E_STATUS_ABORT 4
++#define BRCMF_E_STATUS_NO_ACK 5
++#define BRCMF_E_STATUS_UNSOLICITED 6
++#define BRCMF_E_STATUS_ATTEMPT 7
++#define BRCMF_E_STATUS_PARTIAL 8
++#define BRCMF_E_STATUS_NEWSCAN 9
++#define BRCMF_E_STATUS_NEWASSOC 10
++#define BRCMF_E_STATUS_11HQUIET 11
++#define BRCMF_E_STATUS_SUPPRESS 12
++#define BRCMF_E_STATUS_NOCHANS 13
++#define BRCMF_E_STATUS_CS_ABORT 15
++#define BRCMF_E_STATUS_ERROR 16
++
++/* reason field values in struct brcmf_event_msg */
++#define BRCMF_E_REASON_INITIAL_ASSOC 0
++#define BRCMF_E_REASON_LOW_RSSI 1
++#define BRCMF_E_REASON_DEAUTH 2
++#define BRCMF_E_REASON_DISASSOC 3
++#define BRCMF_E_REASON_BCNS_LOST 4
++#define BRCMF_E_REASON_MINTXRATE 9
++#define BRCMF_E_REASON_TXFAIL 10
++
++#define BRCMF_E_REASON_LINK_BSSCFG_DIS 4
++#define BRCMF_E_REASON_FAST_ROAM_FAILED 5
++#define BRCMF_E_REASON_DIRECTED_ROAM 6
++#define BRCMF_E_REASON_TSPEC_REJECTED 7
++#define BRCMF_E_REASON_BETTER_AP 8
++
++/* action field values for brcmf_ifevent */
++#define BRCMF_E_IF_ADD 1
++#define BRCMF_E_IF_DEL 2
++#define BRCMF_E_IF_CHANGE 3
++
++/* flag field values for brcmf_ifevent */
++#define BRCMF_E_IF_FLAG_NOIF 1
++
++/* role field values for brcmf_ifevent */
++#define BRCMF_E_IF_ROLE_STA 0
++#define BRCMF_E_IF_ROLE_AP 1
++#define BRCMF_E_IF_ROLE_WDS 2
++
+ /**
+ * definitions for event packet validation.
+ */
+@@ -156,6 +206,14 @@
+ u8 bsscfgidx;
+ };
+
++struct brcmf_if_event {
++ u8 ifidx;
++ u8 action;
++ u8 flags;
++ u8 bssidx;
++ u8 role;
++};
++
+ typedef int (*brcmf_fweh_handler_t)(struct brcmf_if *ifp,
+ const struct brcmf_event_msg *evtmsg,
+ void *data);
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwil.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwil.c 2014-05-15 20:34:00.578032457 +0200
+@@ -27,6 +27,7 @@
+ #include "dhd_dbg.h"
+ #include "tracepoint.h"
+ #include "fwil.h"
++#include "proto.h"
+
+
+ #define MAX_HEX_DUMP_LEN 64
+@@ -46,11 +47,9 @@
+ if (data != NULL)
+ len = min_t(uint, len, BRCMF_DCMD_MAXLEN);
+ if (set)
+- err = brcmf_proto_cdc_set_dcmd(drvr, ifp->ifidx, cmd, data,
+- len);
++ err = brcmf_proto_set_dcmd(drvr, ifp->ifidx, cmd, data, len);
+ else
+- err = brcmf_proto_cdc_query_dcmd(drvr, ifp->ifidx, cmd, data,
+- len);
++ err = brcmf_proto_query_dcmd(drvr, ifp->ifidx, cmd, data, len);
+
+ if (err >= 0)
+ err = 0;
+@@ -69,7 +68,7 @@
+
+ brcmf_dbg(FIL, "cmd=%d, len=%d\n", cmd, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+- min_t(uint, len, MAX_HEX_DUMP_LEN), "data");
++ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+ err = brcmf_fil_cmd_data(ifp, cmd, data, len, true);
+ mutex_unlock(&ifp->drvr->proto_block);
+@@ -87,7 +86,7 @@
+
+ brcmf_dbg(FIL, "cmd=%d, len=%d\n", cmd, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+- min_t(uint, len, MAX_HEX_DUMP_LEN), "data");
++ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+ mutex_unlock(&ifp->drvr->proto_block);
+
+@@ -156,7 +155,7 @@
+
+ brcmf_dbg(FIL, "name=%s, len=%d\n", name, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+- min_t(uint, len, MAX_HEX_DUMP_LEN), "data");
++ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+ buflen = brcmf_create_iovar(name, data, len, drvr->proto_buf,
+ sizeof(drvr->proto_buf));
+@@ -196,7 +195,7 @@
+
+ brcmf_dbg(FIL, "name=%s, len=%d\n", name, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+- min_t(uint, len, MAX_HEX_DUMP_LEN), "data");
++ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+ mutex_unlock(&drvr->proto_block);
+ return err;
+@@ -279,7 +278,7 @@
+
+ brcmf_dbg(FIL, "bssidx=%d, name=%s, len=%d\n", ifp->bssidx, name, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+- min_t(uint, len, MAX_HEX_DUMP_LEN), "data");
++ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+ buflen = brcmf_create_bsscfg(ifp->bssidx, name, data, len,
+ drvr->proto_buf, sizeof(drvr->proto_buf));
+@@ -318,7 +317,7 @@
+ }
+ brcmf_dbg(FIL, "bssidx=%d, name=%s, len=%d\n", ifp->bssidx, name, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+- min_t(uint, len, MAX_HEX_DUMP_LEN), "data");
++ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+ mutex_unlock(&drvr->proto_block);
+ return err;
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwil.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwil.h 2014-05-15 20:34:00.578032457 +0200
+@@ -17,6 +17,67 @@
+ #ifndef _fwil_h_
+ #define _fwil_h_
+
++/*******************************************************************************
++ * Dongle command codes that are interpreted by firmware
++ ******************************************************************************/
++#define BRCMF_C_GET_VERSION 1
++#define BRCMF_C_UP 2
++#define BRCMF_C_DOWN 3
++#define BRCMF_C_SET_PROMISC 10
++#define BRCMF_C_GET_RATE 12
++#define BRCMF_C_GET_INFRA 19
++#define BRCMF_C_SET_INFRA 20
++#define BRCMF_C_GET_AUTH 21
++#define BRCMF_C_SET_AUTH 22
++#define BRCMF_C_GET_BSSID 23
++#define BRCMF_C_GET_SSID 25
++#define BRCMF_C_SET_SSID 26
++#define BRCMF_C_TERMINATED 28
++#define BRCMF_C_GET_CHANNEL 29
++#define BRCMF_C_SET_CHANNEL 30
++#define BRCMF_C_GET_SRL 31
++#define BRCMF_C_SET_SRL 32
++#define BRCMF_C_GET_LRL 33
++#define BRCMF_C_SET_LRL 34
++#define BRCMF_C_GET_RADIO 37
++#define BRCMF_C_SET_RADIO 38
++#define BRCMF_C_GET_PHYTYPE 39
++#define BRCMF_C_SET_KEY 45
++#define BRCMF_C_SET_PASSIVE_SCAN 49
++#define BRCMF_C_SCAN 50
++#define BRCMF_C_SCAN_RESULTS 51
++#define BRCMF_C_DISASSOC 52
++#define BRCMF_C_REASSOC 53
++#define BRCMF_C_SET_ROAM_TRIGGER 55
++#define BRCMF_C_SET_ROAM_DELTA 57
++#define BRCMF_C_GET_BCNPRD 75
++#define BRCMF_C_SET_BCNPRD 76
++#define BRCMF_C_GET_DTIMPRD 77
++#define BRCMF_C_SET_DTIMPRD 78
++#define BRCMF_C_SET_COUNTRY 84
++#define BRCMF_C_GET_PM 85
++#define BRCMF_C_SET_PM 86
++#define BRCMF_C_GET_CURR_RATESET 114
++#define BRCMF_C_GET_AP 117
++#define BRCMF_C_SET_AP 118
++#define BRCMF_C_GET_RSSI 127
++#define BRCMF_C_GET_WSEC 133
++#define BRCMF_C_SET_WSEC 134
++#define BRCMF_C_GET_PHY_NOISE 135
++#define BRCMF_C_GET_BSS_INFO 136
++#define BRCMF_C_GET_BANDLIST 140
++#define BRCMF_C_SET_SCB_TIMEOUT 158
++#define BRCMF_C_GET_PHYLIST 180
++#define BRCMF_C_SET_SCAN_CHANNEL_TIME 185
++#define BRCMF_C_SET_SCAN_UNASSOC_TIME 187
++#define BRCMF_C_SCB_DEAUTHENTICATE_FOR_REASON 201
++#define BRCMF_C_GET_VALID_CHANNELS 217
++#define BRCMF_C_GET_KEY_PRIMARY 235
++#define BRCMF_C_SET_KEY_PRIMARY 236
++#define BRCMF_C_SET_SCAN_PASSIVE_TIME 258
++#define BRCMF_C_GET_VAR 262
++#define BRCMF_C_SET_VAR 263
++
+ s32 brcmf_fil_cmd_data_set(struct brcmf_if *ifp, u32 cmd, void *data, u32 len);
+ s32 brcmf_fil_cmd_data_get(struct brcmf_if *ifp, u32 cmd, void *data, u32 len);
+ s32 brcmf_fil_cmd_int_set(struct brcmf_if *ifp, u32 cmd, u32 data);
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h 2014-05-15 20:34:00.578032457 +0200
+@@ -29,6 +29,24 @@
+ #define BRCMF_ARP_OL_HOST_AUTO_REPLY 0x00000004
+ #define BRCMF_ARP_OL_PEER_AUTO_REPLY 0x00000008
+
++#define BRCMF_BSS_INFO_VERSION 109 /* curr ver of brcmf_bss_info_le struct */
++#define BRCMF_BSS_RSSI_ON_CHANNEL 0x0002
++
++#define BRCMF_STA_ASSOC 0x10 /* Associated */
++
++/* size of brcmf_scan_params not including variable length array */
++#define BRCMF_SCAN_PARAMS_FIXED_SIZE 64
++
++/* masks for channel and ssid count */
++#define BRCMF_SCAN_PARAMS_COUNT_MASK 0x0000ffff
++#define BRCMF_SCAN_PARAMS_NSSID_SHIFT 16
++
++/* primary (ie tx) key */
++#define BRCMF_PRIMARY_KEY (1 << 1)
++#define DOT11_BSSTYPE_ANY 2
++#define BRCMF_ESCAN_REQ_VERSION 1
++
++#define BRCMF_MAXRATES_IN_SET 16 /* max # of rates in rateset */
+
+ enum brcmf_fil_p2p_if_types {
+ BRCMF_FIL_P2P_IF_CLIENT,
+@@ -69,4 +87,311 @@
+ __le32 enable;
+ };
+
++/**
++ * struct tdls_iovar - common structure for tdls iovars.
++ *
++ * @ea: ether address of peer station.
++ * @mode: mode value depending on specific tdls iovar.
++ * @chanspec: channel specification.
++ * @pad: unused (for future use).
++ */
++struct brcmf_tdls_iovar_le {
++ u8 ea[ETH_ALEN]; /* Station address */
++ u8 mode; /* mode: depends on iovar */
++ __le16 chanspec;
++ __le32 pad; /* future */
++};
++
++enum brcmf_tdls_manual_ep_ops {
++ BRCMF_TDLS_MANUAL_EP_CREATE = 1,
++ BRCMF_TDLS_MANUAL_EP_DELETE = 3,
++ BRCMF_TDLS_MANUAL_EP_DISCOVERY = 6
++};
++
++/* Pattern matching filter. Specifies an offset within received packets to
++ * start matching, the pattern to match, the size of the pattern, and a bitmask
++ * that indicates which bits within the pattern should be matched.
++ */
++struct brcmf_pkt_filter_pattern_le {
++ /*
++ * Offset within received packet to start pattern matching.
++ * Offset '0' is the first byte of the ethernet header.
++ */
++ __le32 offset;
++ /* Size of the pattern. Bitmask must be the same size.*/
++ __le32 size_bytes;
++ /*
++ * Variable length mask and pattern data. mask starts at offset 0.
++ * Pattern immediately follows mask.
++ */
++ u8 mask_and_pattern[1];
++};
++
++/* IOVAR "pkt_filter_add" parameter. Used to install packet filters. */
++struct brcmf_pkt_filter_le {
++ __le32 id; /* Unique filter id, specified by app. */
++ __le32 type; /* Filter type (WL_PKT_FILTER_TYPE_xxx). */
++ __le32 negate_match; /* Negate the result of filter matches */
++ union { /* Filter definitions */
++ struct brcmf_pkt_filter_pattern_le pattern; /* Filter pattern */
++ } u;
++};
++
++/* IOVAR "pkt_filter_enable" parameter. */
++struct brcmf_pkt_filter_enable_le {
++ __le32 id; /* Unique filter id */
++ __le32 enable; /* Enable/disable bool */
++};
++
++/* BSS info structure
++ * Applications MUST CHECK ie_offset field and length field to access IEs and
++ * next bss_info structure in a vector (in struct brcmf_scan_results)
++ */
++struct brcmf_bss_info_le {
++ __le32 version; /* version field */
++ __le32 length; /* byte length of data in this record,
++ * starting at version and including IEs
++ */
++ u8 BSSID[ETH_ALEN];
++ __le16 beacon_period; /* units are Kusec */
++ __le16 capability; /* Capability information */
++ u8 SSID_len;
++ u8 SSID[32];
++ struct {
++ __le32 count; /* # rates in this set */
++ u8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
++ } rateset; /* supported rates */
++ __le16 chanspec; /* chanspec for bss */
++ __le16 atim_window; /* units are Kusec */
++ u8 dtim_period; /* DTIM period */
++ __le16 RSSI; /* receive signal strength (in dBm) */
++ s8 phy_noise; /* noise (in dBm) */
++
++ u8 n_cap; /* BSS is 802.11N Capable */
++ /* 802.11N BSS Capabilities (based on HT_CAP_*): */
++ __le32 nbss_cap;
++ u8 ctl_ch; /* 802.11N BSS control channel number */
++ __le32 reserved32[1]; /* Reserved for expansion of BSS properties */
++ u8 flags; /* flags */
++ u8 reserved[3]; /* Reserved for expansion of BSS properties */
++ u8 basic_mcs[MCSSET_LEN]; /* 802.11N BSS required MCS set */
++
++ __le16 ie_offset; /* offset at which IEs start, from beginning */
++ __le32 ie_length; /* byte length of Information Elements */
++ __le16 SNR; /* average SNR of during frame reception */
++ /* Add new fields here */
++ /* variable length Information Elements */
++};
++
++struct brcm_rateset_le {
++ /* # rates in this set */
++ __le32 count;
++ /* rates in 500kbps units w/hi bit set if basic */
++ u8 rates[BRCMF_MAXRATES_IN_SET];
++};
++
++struct brcmf_ssid {
++ u32 SSID_len;
++ unsigned char SSID[32];
++};
++
++struct brcmf_ssid_le {
++ __le32 SSID_len;
++ unsigned char SSID[32];
++};
++
++struct brcmf_scan_params_le {
++ struct brcmf_ssid_le ssid_le; /* default: {0, ""} */
++ u8 bssid[ETH_ALEN]; /* default: bcast */
++ s8 bss_type; /* default: any,
++ * DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT
++ */
++ u8 scan_type; /* flags, 0 use default */
++ __le32 nprobes; /* -1 use default, number of probes per channel */
++ __le32 active_time; /* -1 use default, dwell time per channel for
++ * active scanning
++ */
++ __le32 passive_time; /* -1 use default, dwell time per channel
++ * for passive scanning
++ */
++ __le32 home_time; /* -1 use default, dwell time for the
++ * home channel between channel scans
++ */
++ __le32 channel_num; /* count of channels and ssids that follow
++ *
++ * low half is count of channels in
++ * channel_list, 0 means default (use all
++ * available channels)
++ *
++ * high half is entries in struct brcmf_ssid
++ * array that follows channel_list, aligned for
++ * s32 (4 bytes) meaning an odd channel count
++ * implies a 2-byte pad between end of
++ * channel_list and first ssid
++ *
++ * if ssid count is zero, single ssid in the
++ * fixed parameter portion is assumed, otherwise
++ * ssid in the fixed portion is ignored
++ */
++ __le16 channel_list[1]; /* list of chanspecs */
++};
++
++struct brcmf_scan_results {
++ u32 buflen;
++ u32 version;
++ u32 count;
++ struct brcmf_bss_info_le bss_info_le[];
++};
++
++struct brcmf_escan_params_le {
++ __le32 version;
++ __le16 action;
++ __le16 sync_id;
++ struct brcmf_scan_params_le params_le;
++};
++
++struct brcmf_escan_result_le {
++ __le32 buflen;
++ __le32 version;
++ __le16 sync_id;
++ __le16 bss_count;
++ struct brcmf_bss_info_le bss_info_le;
++};
++
++#define WL_ESCAN_RESULTS_FIXED_SIZE (sizeof(struct brcmf_escan_result_le) - \
++ sizeof(struct brcmf_bss_info_le))
++
++/* used for association with a specific BSSID and chanspec list */
++struct brcmf_assoc_params_le {
++ /* 00:00:00:00:00:00: broadcast scan */
++ u8 bssid[ETH_ALEN];
++ /* 0: all available channels, otherwise count of chanspecs in
++ * chanspec_list */
++ __le32 chanspec_num;
++ /* list of chanspecs */
++ __le16 chanspec_list[1];
++};
++
++/* used for join with or without a specific bssid and channel list */
++struct brcmf_join_params {
++ struct brcmf_ssid_le ssid_le;
++ struct brcmf_assoc_params_le params_le;
++};
++
++/* scan params for extended join */
++struct brcmf_join_scan_params_le {
++ u8 scan_type; /* 0 use default, active or passive scan */
++ __le32 nprobes; /* -1 use default, nr of probes per channel */
++ __le32 active_time; /* -1 use default, dwell time per channel for
++ * active scanning
++ */
++ __le32 passive_time; /* -1 use default, dwell time per channel
++ * for passive scanning
++ */
++ __le32 home_time; /* -1 use default, dwell time for the home
++ * channel between channel scans
++ */
++};
++
++/* extended join params */
++struct brcmf_ext_join_params_le {
++ struct brcmf_ssid_le ssid_le; /* {0, ""}: wildcard scan */
++ struct brcmf_join_scan_params_le scan_le;
++ struct brcmf_assoc_params_le assoc_le;
++};
++
++struct brcmf_wsec_key {
++ u32 index; /* key index */
++ u32 len; /* key length */
++ u8 data[WLAN_MAX_KEY_LEN]; /* key data */
++ u32 pad_1[18];
++ u32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
++ u32 flags; /* misc flags */
++ u32 pad_2[3];
++ u32 iv_initialized; /* has IV been initialized already? */
++ u32 pad_3;
++ /* Rx IV */
++ struct {
++ u32 hi; /* upper 32 bits of IV */
++ u16 lo; /* lower 16 bits of IV */
++ } rxiv;
++ u32 pad_4[2];
++ u8 ea[ETH_ALEN]; /* per station */
++};
++
++/*
++ * dongle requires same struct as above but with fields in little endian order
++ */
++struct brcmf_wsec_key_le {
++ __le32 index; /* key index */
++ __le32 len; /* key length */
++ u8 data[WLAN_MAX_KEY_LEN]; /* key data */
++ __le32 pad_1[18];
++ __le32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
++ __le32 flags; /* misc flags */
++ __le32 pad_2[3];
++ __le32 iv_initialized; /* has IV been initialized already? */
++ __le32 pad_3;
++ /* Rx IV */
++ struct {
++ __le32 hi; /* upper 32 bits of IV */
++ __le16 lo; /* lower 16 bits of IV */
++ } rxiv;
++ __le32 pad_4[2];
++ u8 ea[ETH_ALEN]; /* per station */
++};
++
++/* Used to get specific STA parameters */
++struct brcmf_scb_val_le {
++ __le32 val;
++ u8 ea[ETH_ALEN];
++};
++
++/* channel encoding */
++struct brcmf_channel_info_le {
++ __le32 hw_channel;
++ __le32 target_channel;
++ __le32 scan_channel;
++};
++
++struct brcmf_sta_info_le {
++ __le16 ver; /* version of this struct */
++ __le16 len; /* length in bytes of this structure */
++ __le16 cap; /* sta's advertised capabilities */
++ __le32 flags; /* flags defined below */
++ __le32 idle; /* time since data pkt rx'd from sta */
++ u8 ea[ETH_ALEN]; /* Station address */
++ __le32 count; /* # rates in this set */
++ u8 rates[BRCMF_MAXRATES_IN_SET]; /* rates in 500kbps units */
++ /* w/hi bit set if basic */
++ __le32 in; /* seconds elapsed since associated */
++ __le32 listen_interval_inms; /* Min Listen interval in ms for STA */
++ __le32 tx_pkts; /* # of packets transmitted */
++ __le32 tx_failures; /* # of packets failed */
++ __le32 rx_ucast_pkts; /* # of unicast packets received */
++ __le32 rx_mcast_pkts; /* # of multicast packets received */
++ __le32 tx_rate; /* Rate of last successful tx frame */
++ __le32 rx_rate; /* Rate of last successful rx frame */
++ __le32 rx_decrypt_succeeds; /* # of packet decrypted successfully */
++ __le32 rx_decrypt_failures; /* # of packet decrypted failed */
++};
++
++struct brcmf_chanspec_list {
++ __le32 count; /* # of entries */
++ __le32 element[1]; /* variable length uint32 list */
++};
++
++/*
++ * WLC_E_PROBRESP_MSG
++ * WLC_E_P2P_PROBREQ_MSG
++ * WLC_E_ACTION_FRAME_RX
++ */
++struct brcmf_rx_mgmt_data {
++ __be16 version;
++ __be16 chanspec;
++ __be32 rssi;
++ __be32 mactime;
++ __be32 rate;
++};
++
+ #endif /* FWIL_TYPES_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c 2014-05-15 20:34:00.578032457 +0200
+@@ -22,13 +22,11 @@
+ #include <linux/etherdevice.h>
+ #include <linux/err.h>
+ #include <linux/jiffies.h>
+-#include <uapi/linux/nl80211.h>
+ #include <net/cfg80211.h>
+
+ #include <brcmu_utils.h>
+ #include <brcmu_wifi.h>
+ #include "dhd.h"
+-#include "dhd_proto.h"
+ #include "dhd_dbg.h"
+ #include "dhd_bus.h"
+ #include "fwil.h"
+@@ -37,6 +35,7 @@
+ #include "fwsignal.h"
+ #include "p2p.h"
+ #include "wl_cfg80211.h"
++#include "proto.h"
+
+ /**
+ * DOC: Firmware Signalling
+@@ -106,6 +105,7 @@
+ };
+ #undef BRCMF_FWS_TLV_DEF
+
++
+ static const char *brcmf_fws_get_tlv_name(enum brcmf_fws_tlv_type id)
+ {
+ int i;
+@@ -124,6 +124,12 @@
+ #endif /* DEBUG */
+
+ /*
++ * The PKTTAG tlv has additional bytes when firmware-signalling
++ * mode has REUSESEQ flag set.
++ */
++#define BRCMF_FWS_TYPE_SEQ_LEN 2
++
++/*
+ * flags used to enable tlv signalling from firmware.
+ */
+ #define BRCMF_FWS_FLAGS_RSSI_SIGNALS 0x0001
+@@ -142,14 +148,21 @@
+ #define BRCMF_FWS_FLOWCONTROL_HIWATER 128
+ #define BRCMF_FWS_FLOWCONTROL_LOWATER 64
+
+-#define BRCMF_FWS_PSQ_PREC_COUNT ((NL80211_NUM_ACS + 1) * 2)
++#define BRCMF_FWS_PSQ_PREC_COUNT ((BRCMF_FWS_FIFO_COUNT + 1) * 2)
+ #define BRCMF_FWS_PSQ_LEN 256
+
+ #define BRCMF_FWS_HTOD_FLAG_PKTFROMHOST 0x01
+ #define BRCMF_FWS_HTOD_FLAG_PKT_REQUESTED 0x02
+
+-#define BRCMF_FWS_RET_OK_NOSCHEDULE 0
+-#define BRCMF_FWS_RET_OK_SCHEDULE 1
++#define BRCMF_FWS_RET_OK_NOSCHEDULE 0
++#define BRCMF_FWS_RET_OK_SCHEDULE 1
++
++#define BRCMF_FWS_MODE_REUSESEQ_SHIFT 3 /* seq reuse */
++#define BRCMF_FWS_MODE_SET_REUSESEQ(x, val) ((x) = \
++ ((x) & ~(1 << BRCMF_FWS_MODE_REUSESEQ_SHIFT)) | \
++ (((val) & 1) << BRCMF_FWS_MODE_REUSESEQ_SHIFT))
++#define BRCMF_FWS_MODE_GET_REUSESEQ(x) \
++ (((x) >> BRCMF_FWS_MODE_REUSESEQ_SHIFT) & 1)
+
+ /**
+ * enum brcmf_fws_skb_state - indicates processing state of skb.
+@@ -157,18 +170,22 @@
+ * @BRCMF_FWS_SKBSTATE_NEW: sk_buff is newly arrived in the driver.
+ * @BRCMF_FWS_SKBSTATE_DELAYED: sk_buff had to wait on queue.
+ * @BRCMF_FWS_SKBSTATE_SUPPRESSED: sk_buff has been suppressed by firmware.
++ * @BRCMF_FWS_SKBSTATE_TIM: allocated for TIM update info.
+ */
+ enum brcmf_fws_skb_state {
+ BRCMF_FWS_SKBSTATE_NEW,
+ BRCMF_FWS_SKBSTATE_DELAYED,
+- BRCMF_FWS_SKBSTATE_SUPPRESSED
++ BRCMF_FWS_SKBSTATE_SUPPRESSED,
++ BRCMF_FWS_SKBSTATE_TIM
+ };
+
+ /**
+ * struct brcmf_skbuff_cb - control buffer associated with skbuff.
+ *
++ * @bus_flags: 2 bytes reserved for bus specific parameters
+ * @if_flags: holds interface index and packet related flags.
+ * @htod: host to device packet identifier (used in PKTTAG tlv).
++ * @htod_seq: this 16-bit is original seq number for every suppress packet.
+ * @state: transmit state of the packet.
+ * @mac: descriptor related to destination for this packet.
+ *
+@@ -176,8 +193,10 @@
+ * provides 48 bytes of storage so this structure should not exceed that.
+ */
+ struct brcmf_skbuff_cb {
++ u16 bus_flags;
+ u16 if_flags;
+ u32 htod;
++ u16 htod_seq;
+ enum brcmf_fws_skb_state state;
+ struct brcmf_fws_mac_descriptor *mac;
+ };
+@@ -193,9 +212,8 @@
+ * b[11] - packet sent upon firmware request.
+ * b[10] - packet only contains signalling data.
+ * b[9] - packet is a tx packet.
+- * b[8] - packet uses FIFO credit (non-pspoll).
++ * b[8] - packet used requested credit
+ * b[7] - interface in AP mode.
+- * b[6:4] - AC FIFO number.
+ * b[3:0] - interface index.
+ */
+ #define BRCMF_SKB_IF_FLAGS_REQUESTED_MASK 0x0800
+@@ -204,12 +222,10 @@
+ #define BRCMF_SKB_IF_FLAGS_SIGNAL_ONLY_SHIFT 10
+ #define BRCMF_SKB_IF_FLAGS_TRANSMIT_MASK 0x0200
+ #define BRCMF_SKB_IF_FLAGS_TRANSMIT_SHIFT 9
+-#define BRCMF_SKB_IF_FLAGS_CREDITCHECK_MASK 0x0100
+-#define BRCMF_SKB_IF_FLAGS_CREDITCHECK_SHIFT 8
++#define BRCMF_SKB_IF_FLAGS_REQ_CREDIT_MASK 0x0100
++#define BRCMF_SKB_IF_FLAGS_REQ_CREDIT_SHIFT 8
+ #define BRCMF_SKB_IF_FLAGS_IF_AP_MASK 0x0080
+ #define BRCMF_SKB_IF_FLAGS_IF_AP_SHIFT 7
+-#define BRCMF_SKB_IF_FLAGS_FIFO_MASK 0x0070
+-#define BRCMF_SKB_IF_FLAGS_FIFO_SHIFT 4
+ #define BRCMF_SKB_IF_FLAGS_INDEX_MASK 0x000f
+ #define BRCMF_SKB_IF_FLAGS_INDEX_SHIFT 0
+
+@@ -246,7 +262,7 @@
+ #define BRCMF_SKB_HTOD_TAG_HSLOT_MASK 0x00ffff00
+ #define BRCMF_SKB_HTOD_TAG_HSLOT_SHIFT 8
+ #define BRCMF_SKB_HTOD_TAG_FREERUN_MASK 0x000000ff
+-#define BRCMF_SKB_HTOD_TAG_FREERUN_SHIFT 0
++#define BRCMF_SKB_HTOD_TAG_FREERUN_SHIFT 0
+
+ #define brcmf_skb_htod_tag_set_field(skb, field, value) \
+ brcmu_maskset32(&(brcmf_skbcb(skb)->htod), \
+@@ -257,6 +273,22 @@
+ BRCMF_SKB_HTOD_TAG_ ## field ## _MASK, \
+ BRCMF_SKB_HTOD_TAG_ ## field ## _SHIFT)
+
++#define BRCMF_SKB_HTOD_SEQ_FROMFW_MASK 0x2000
++#define BRCMF_SKB_HTOD_SEQ_FROMFW_SHIFT 13
++#define BRCMF_SKB_HTOD_SEQ_FROMDRV_MASK 0x1000
++#define BRCMF_SKB_HTOD_SEQ_FROMDRV_SHIFT 12
++#define BRCMF_SKB_HTOD_SEQ_NR_MASK 0x0fff
++#define BRCMF_SKB_HTOD_SEQ_NR_SHIFT 0
++
++#define brcmf_skb_htod_seq_set_field(skb, field, value) \
++ brcmu_maskset16(&(brcmf_skbcb(skb)->htod_seq), \
++ BRCMF_SKB_HTOD_SEQ_ ## field ## _MASK, \
++ BRCMF_SKB_HTOD_SEQ_ ## field ## _SHIFT, (value))
++#define brcmf_skb_htod_seq_get_field(skb, field) \
++ brcmu_maskget16(brcmf_skbcb(skb)->htod_seq, \
++ BRCMF_SKB_HTOD_SEQ_ ## field ## _MASK, \
++ BRCMF_SKB_HTOD_SEQ_ ## field ## _SHIFT)
++
+ #define BRCMF_FWS_TXSTAT_GENERATION_MASK 0x80000000
+ #define BRCMF_FWS_TXSTAT_GENERATION_SHIFT 31
+ #define BRCMF_FWS_TXSTAT_FLAGS_MASK 0x78000000
+@@ -265,8 +297,8 @@
+ #define BRCMF_FWS_TXSTAT_FIFO_SHIFT 24
+ #define BRCMF_FWS_TXSTAT_HSLOT_MASK 0x00FFFF00
+ #define BRCMF_FWS_TXSTAT_HSLOT_SHIFT 8
+-#define BRCMF_FWS_TXSTAT_PKTID_MASK 0x00FFFFFF
+-#define BRCMF_FWS_TXSTAT_PKTID_SHIFT 0
++#define BRCMF_FWS_TXSTAT_FREERUN_MASK 0x000000FF
++#define BRCMF_FWS_TXSTAT_FREERUN_SHIFT 0
+
+ #define brcmf_txstatus_get_field(txs, field) \
+ brcmu_maskget32(txs, BRCMF_FWS_TXSTAT_ ## field ## _MASK, \
+@@ -278,6 +310,7 @@
+ /**
+ * enum brcmf_fws_fifo - fifo indices used by dongle firmware.
+ *
++ * @BRCMF_FWS_FIFO_FIRST: first fifo, ie. background.
+ * @BRCMF_FWS_FIFO_AC_BK: fifo for background traffic.
+ * @BRCMF_FWS_FIFO_AC_BE: fifo for best-effort traffic.
+ * @BRCMF_FWS_FIFO_AC_VI: fifo for video traffic.
+@@ -287,7 +320,8 @@
+ * @BRCMF_FWS_FIFO_COUNT: number of fifos.
+ */
+ enum brcmf_fws_fifo {
+- BRCMF_FWS_FIFO_AC_BK,
++ BRCMF_FWS_FIFO_FIRST,
++ BRCMF_FWS_FIFO_AC_BK = BRCMF_FWS_FIFO_FIRST,
+ BRCMF_FWS_FIFO_AC_BE,
+ BRCMF_FWS_FIFO_AC_VI,
+ BRCMF_FWS_FIFO_AC_VO,
+@@ -307,12 +341,15 @@
+ * firmware suppress the packet as device is already in PS mode.
+ * @BRCMF_FWS_TXSTATUS_FW_TOSSED:
+ * firmware tossed the packet.
++ * @BRCMF_FWS_TXSTATUS_HOST_TOSSED:
++ * host tossed the packet.
+ */
+ enum brcmf_fws_txstatus {
+ BRCMF_FWS_TXSTATUS_DISCARD,
+ BRCMF_FWS_TXSTATUS_CORE_SUPPRESS,
+ BRCMF_FWS_TXSTATUS_FW_PS_SUPPRESS,
+- BRCMF_FWS_TXSTATUS_FW_TOSSED
++ BRCMF_FWS_TXSTATUS_FW_TOSSED,
++ BRCMF_FWS_TXSTATUS_HOST_TOSSED
+ };
+
+ enum brcmf_fws_fcmode {
+@@ -343,6 +380,7 @@
+ * @transit_count: packet in transit to firmware.
+ */
+ struct brcmf_fws_mac_descriptor {
++ char name[16];
+ u8 occupied;
+ u8 mac_handle;
+ u8 interface_id;
+@@ -356,7 +394,6 @@
+ u8 seq[BRCMF_FWS_FIFO_COUNT];
+ struct pktq psq;
+ int transit_count;
+- int suppress_count;
+ int suppr_transit_count;
+ bool send_tim_signal;
+ u8 traffic_pending_bmp;
+@@ -383,12 +420,10 @@
+ * struct brcmf_fws_hanger_item - single entry for tx pending packet.
+ *
+ * @state: entry is either free or occupied.
+- * @gen: generation.
+ * @pkt: packet itself.
+ */
+ struct brcmf_fws_hanger_item {
+ enum brcmf_fws_hanger_item_state state;
+- u8 gen;
+ struct sk_buff *pkt;
+ };
+
+@@ -421,9 +456,13 @@
+
+ struct brcmf_fws_info {
+ struct brcmf_pub *drvr;
++ spinlock_t spinlock;
++ ulong flags;
+ struct brcmf_fws_stats stats;
+ struct brcmf_fws_hanger hanger;
+ enum brcmf_fws_fcmode fcmode;
++ bool fw_signals;
++ bool bcmc_credit_check;
+ struct brcmf_fws_macdesc_table desc;
+ struct workqueue_struct *fws_wq;
+ struct work_struct fws_dequeue_work;
+@@ -434,6 +473,9 @@
+ u32 fifo_credit_map;
+ u32 fifo_delay_map;
+ unsigned long borrow_defer_timestamp;
++ bool bus_flow_blocked;
++ bool creditmap_received;
++ u8 mode;
+ };
+
+ /*
+@@ -479,6 +521,18 @@
+ }
+ #undef BRCMF_FWS_TLV_DEF
+
++static void brcmf_fws_lock(struct brcmf_fws_info *fws)
++ __acquires(&fws->spinlock)
++{
++ spin_lock_irqsave(&fws->spinlock, fws->flags);
++}
++
++static void brcmf_fws_unlock(struct brcmf_fws_info *fws)
++ __releases(&fws->spinlock)
++{
++ spin_unlock_irqrestore(&fws->spinlock, fws->flags);
++}
++
+ static bool brcmf_fws_ifidx_match(struct sk_buff *skb, void *arg)
+ {
+ u32 ifidx = brcmf_skb_if_flags_get_field(skb, INDEX);
+@@ -507,7 +561,6 @@
+ {
+ int i;
+
+- brcmf_dbg(TRACE, "enter\n");
+ memset(hanger, 0, sizeof(*hanger));
+ for (i = 0; i < ARRAY_SIZE(hanger->items); i++)
+ hanger->items[i].state = BRCMF_FWS_HANGER_ITEM_STATE_FREE;
+@@ -517,7 +570,6 @@
+ {
+ u32 i;
+
+- brcmf_dbg(TRACE, "enter\n");
+ i = (h->slot_pos + 1) % BRCMF_FWS_HANGER_MAXITEMS;
+
+ while (i != h->slot_pos) {
+@@ -533,14 +585,12 @@
+ h->failed_slotfind++;
+ i = BRCMF_FWS_HANGER_MAXITEMS;
+ done:
+- brcmf_dbg(TRACE, "exit: %d\n", i);
+ return i;
+ }
+
+ static int brcmf_fws_hanger_pushpkt(struct brcmf_fws_hanger *h,
+- struct sk_buff *pkt, u32 slot_id)
++ struct sk_buff *pkt, u32 slot_id)
+ {
+- brcmf_dbg(TRACE, "enter\n");
+ if (slot_id >= BRCMF_FWS_HANGER_MAXITEMS)
+ return -ENOENT;
+
+@@ -560,7 +610,6 @@
+ u32 slot_id, struct sk_buff **pktout,
+ bool remove_item)
+ {
+- brcmf_dbg(TRACE, "enter\n");
+ if (slot_id >= BRCMF_FWS_HANGER_MAXITEMS)
+ return -ENOENT;
+
+@@ -574,23 +623,18 @@
+ if (remove_item) {
+ h->items[slot_id].state = BRCMF_FWS_HANGER_ITEM_STATE_FREE;
+ h->items[slot_id].pkt = NULL;
+- h->items[slot_id].gen = 0xff;
+ h->popped++;
+ }
+ return 0;
+ }
+
+ static int brcmf_fws_hanger_mark_suppressed(struct brcmf_fws_hanger *h,
+- u32 slot_id, u8 gen)
++ u32 slot_id)
+ {
+- brcmf_dbg(TRACE, "enter\n");
+-
+ if (slot_id >= BRCMF_FWS_HANGER_MAXITEMS)
+ return -ENOENT;
+
+- h->items[slot_id].gen = gen;
+-
+- if (h->items[slot_id].state != BRCMF_FWS_HANGER_ITEM_STATE_INUSE) {
++ if (h->items[slot_id].state == BRCMF_FWS_HANGER_ITEM_STATE_FREE) {
+ brcmf_err("entry not in use\n");
+ return -EINVAL;
+ }
+@@ -599,25 +643,6 @@
+ return 0;
+ }
+
+-static int brcmf_fws_hanger_get_genbit(struct brcmf_fws_hanger *hanger,
+- struct sk_buff *pkt, u32 slot_id,
+- int *gen)
+-{
+- brcmf_dbg(TRACE, "enter\n");
+- *gen = 0xff;
+-
+- if (slot_id >= BRCMF_FWS_HANGER_MAXITEMS)
+- return -ENOENT;
+-
+- if (hanger->items[slot_id].state == BRCMF_FWS_HANGER_ITEM_STATE_FREE) {
+- brcmf_err("slot not in use\n");
+- return -EINVAL;
+- }
+-
+- *gen = hanger->items[slot_id].gen;
+- return 0;
+-}
+-
+ static void brcmf_fws_hanger_cleanup(struct brcmf_fws_info *fws,
+ bool (*fn)(struct sk_buff *, void *),
+ int ifidx)
+@@ -627,7 +652,6 @@
+ int i;
+ enum brcmf_fws_hanger_item_state s;
+
+- brcmf_dbg(TRACE, "enter: ifidx=%d\n", ifidx);
+ for (i = 0; i < ARRAY_SIZE(h->items); i++) {
+ s = h->items[i].state;
+ if (s == BRCMF_FWS_HANGER_ITEM_STATE_INUSE ||
+@@ -644,14 +668,28 @@
+ }
+ }
+
+-static void brcmf_fws_init_mac_descriptor(struct brcmf_fws_mac_descriptor *desc,
+- u8 *addr, u8 ifidx)
++static void brcmf_fws_macdesc_set_name(struct brcmf_fws_info *fws,
++ struct brcmf_fws_mac_descriptor *desc)
++{
++ if (desc == &fws->desc.other)
++ strlcpy(desc->name, "MAC-OTHER", sizeof(desc->name));
++ else if (desc->mac_handle)
++ scnprintf(desc->name, sizeof(desc->name), "MAC-%d:%d",
++ desc->mac_handle, desc->interface_id);
++ else
++ scnprintf(desc->name, sizeof(desc->name), "MACIF:%d",
++ desc->interface_id);
++}
++
++static void brcmf_fws_macdesc_init(struct brcmf_fws_mac_descriptor *desc,
++ u8 *addr, u8 ifidx)
+ {
+ brcmf_dbg(TRACE,
+ "enter: desc %p ea=%pM, ifidx=%u\n", desc, addr, ifidx);
+ desc->occupied = 1;
+ desc->state = BRCMF_FWS_STATE_OPEN;
+ desc->requested_credit = 0;
++ desc->requested_packet = 0;
+ /* depending on use may need ifp->bssidx instead */
+ desc->interface_id = ifidx;
+ desc->ac_bitmap = 0xff; /* update this when handling APSD */
+@@ -660,22 +698,22 @@
+ }
+
+ static
+-void brcmf_fws_clear_mac_descriptor(struct brcmf_fws_mac_descriptor *desc)
++void brcmf_fws_macdesc_deinit(struct brcmf_fws_mac_descriptor *desc)
+ {
+ brcmf_dbg(TRACE,
+ "enter: ea=%pM, ifidx=%u\n", desc->ea, desc->interface_id);
+ desc->occupied = 0;
+ desc->state = BRCMF_FWS_STATE_CLOSE;
+ desc->requested_credit = 0;
++ desc->requested_packet = 0;
+ }
+
+ static struct brcmf_fws_mac_descriptor *
+-brcmf_fws_mac_descriptor_lookup(struct brcmf_fws_info *fws, u8 *ea)
++brcmf_fws_macdesc_lookup(struct brcmf_fws_info *fws, u8 *ea)
+ {
+ struct brcmf_fws_mac_descriptor *entry;
+ int i;
+
+- brcmf_dbg(TRACE, "enter: ea=%pM\n", ea);
+ if (ea == NULL)
+ return ERR_PTR(-EINVAL);
+
+@@ -690,42 +728,33 @@
+ }
+
+ static struct brcmf_fws_mac_descriptor*
+-brcmf_fws_find_mac_desc(struct brcmf_fws_info *fws, struct brcmf_if *ifp,
+- u8 *da)
++brcmf_fws_macdesc_find(struct brcmf_fws_info *fws, struct brcmf_if *ifp, u8 *da)
+ {
+ struct brcmf_fws_mac_descriptor *entry = &fws->desc.other;
+ bool multicast;
+- enum nl80211_iftype iftype;
+-
+- brcmf_dbg(TRACE, "enter: idx=%d\n", ifp->bssidx);
+
+ multicast = is_multicast_ether_addr(da);
+- iftype = brcmf_cfg80211_get_iftype(ifp);
+
+- /* Multicast destination and P2P clients get the interface entry.
+- * STA gets the interface entry if there is no exact match. For
+- * example, TDLS destinations have their own entry.
++ /* Multicast destination, STA and P2P clients get the interface entry.
++ * STA/GC gets the Mac Entry for TDLS destinations, TDLS destinations
++ * have their own entry.
+ */
+- entry = NULL;
+- if ((multicast || iftype == NL80211_IFTYPE_STATION ||
+- iftype == NL80211_IFTYPE_P2P_CLIENT) && ifp->fws_desc)
++ if (multicast && ifp->fws_desc) {
+ entry = ifp->fws_desc;
+-
+- if (entry != NULL && iftype != NL80211_IFTYPE_STATION)
+ goto done;
++ }
+
+- entry = brcmf_fws_mac_descriptor_lookup(fws, da);
++ entry = brcmf_fws_macdesc_lookup(fws, da);
+ if (IS_ERR(entry))
+- entry = &fws->desc.other;
++ entry = ifp->fws_desc;
+
+ done:
+- brcmf_dbg(TRACE, "exit: entry=%p\n", entry);
+ return entry;
+ }
+
+-static bool brcmf_fws_mac_desc_closed(struct brcmf_fws_info *fws,
+- struct brcmf_fws_mac_descriptor *entry,
+- int fifo)
++static bool brcmf_fws_macdesc_closed(struct brcmf_fws_info *fws,
++ struct brcmf_fws_mac_descriptor *entry,
++ int fifo)
+ {
+ struct brcmf_fws_mac_descriptor *if_entry;
+ bool closed;
+@@ -748,15 +777,11 @@
+ return closed || !(entry->ac_bitmap & BIT(fifo));
+ }
+
+-static void brcmf_fws_mac_desc_cleanup(struct brcmf_fws_info *fws,
+- struct brcmf_fws_mac_descriptor *entry,
+- int ifidx)
++static void brcmf_fws_macdesc_cleanup(struct brcmf_fws_info *fws,
++ struct brcmf_fws_mac_descriptor *entry,
++ int ifidx)
+ {
+- brcmf_dbg(TRACE, "enter: entry=(ea=%pM, ifid=%d), ifidx=%d\n",
+- entry->ea, entry->interface_id, ifidx);
+ if (entry->occupied && (ifidx == -1 || ifidx == entry->interface_id)) {
+- brcmf_dbg(TRACE, "flush psq: ifidx=%d, qlen=%d\n",
+- ifidx, entry->psq.len);
+ brcmf_fws_psq_flush(fws, &entry->psq, ifidx);
+ entry->occupied = !!(entry->psq.len);
+ }
+@@ -772,7 +797,6 @@
+ int prec;
+ u32 hslot;
+
+- brcmf_dbg(TRACE, "enter: ifidx=%d\n", ifidx);
+ txq = brcmf_bus_gettxq(fws->drvr->bus_if);
+ if (IS_ERR(txq)) {
+ brcmf_dbg(TRACE, "no txq to clean up\n");
+@@ -798,7 +822,6 @@
+ struct brcmf_fws_mac_descriptor *table;
+ bool (*matchfn)(struct sk_buff *, void *) = NULL;
+
+- brcmf_dbg(TRACE, "enter: ifidx=%d\n", ifidx);
+ if (fws == NULL)
+ return;
+
+@@ -808,51 +831,132 @@
+ /* cleanup individual nodes */
+ table = &fws->desc.nodes[0];
+ for (i = 0; i < ARRAY_SIZE(fws->desc.nodes); i++)
+- brcmf_fws_mac_desc_cleanup(fws, &table[i], ifidx);
++ brcmf_fws_macdesc_cleanup(fws, &table[i], ifidx);
+
+- brcmf_fws_mac_desc_cleanup(fws, &fws->desc.other, ifidx);
++ brcmf_fws_macdesc_cleanup(fws, &fws->desc.other, ifidx);
+ brcmf_fws_bus_txq_cleanup(fws, matchfn, ifidx);
+ brcmf_fws_hanger_cleanup(fws, matchfn, ifidx);
+ }
+
+-static void brcmf_fws_tim_update(struct brcmf_fws_info *ctx,
+- struct brcmf_fws_mac_descriptor *entry,
+- int prec)
++static u8 brcmf_fws_hdrpush(struct brcmf_fws_info *fws, struct sk_buff *skb)
+ {
+- brcmf_dbg(TRACE, "enter: ea=%pM\n", entry->ea);
+- if (entry->state == BRCMF_FWS_STATE_CLOSE) {
+- /* check delayedQ and suppressQ in one call using bitmap */
+- if (brcmu_pktq_mlen(&entry->psq, 3 << (prec * 2)) == 0)
+- entry->traffic_pending_bmp =
+- entry->traffic_pending_bmp & ~NBITVAL(prec);
+- else
+- entry->traffic_pending_bmp =
+- entry->traffic_pending_bmp | NBITVAL(prec);
++ struct brcmf_fws_mac_descriptor *entry = brcmf_skbcb(skb)->mac;
++ u8 *wlh;
++ u16 data_offset = 0;
++ u8 fillers;
++ __le32 pkttag = cpu_to_le32(brcmf_skbcb(skb)->htod);
++ __le16 pktseq = cpu_to_le16(brcmf_skbcb(skb)->htod_seq);
++
++ brcmf_dbg(TRACE, "enter: %s, idx=%d hslot=%d htod %X seq %X\n",
++ entry->name, brcmf_skb_if_flags_get_field(skb, INDEX),
++ (le32_to_cpu(pkttag) >> 8) & 0xffff,
++ brcmf_skbcb(skb)->htod, brcmf_skbcb(skb)->htod_seq);
++ if (entry->send_tim_signal)
++ data_offset += 2 + BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP_LEN;
++ if (BRCMF_FWS_MODE_GET_REUSESEQ(fws->mode))
++ data_offset += BRCMF_FWS_TYPE_SEQ_LEN;
++ /* +2 is for Type[1] and Len[1] in TLV, plus TIM signal */
++ data_offset += 2 + BRCMF_FWS_TYPE_PKTTAG_LEN;
++ fillers = round_up(data_offset, 4) - data_offset;
++ data_offset += fillers;
++
++ skb_push(skb, data_offset);
++ wlh = skb->data;
++
++ wlh[0] = BRCMF_FWS_TYPE_PKTTAG;
++ wlh[1] = BRCMF_FWS_TYPE_PKTTAG_LEN;
++ memcpy(&wlh[2], &pkttag, sizeof(pkttag));
++ if (BRCMF_FWS_MODE_GET_REUSESEQ(fws->mode)) {
++ wlh[1] += BRCMF_FWS_TYPE_SEQ_LEN;
++ memcpy(&wlh[2 + BRCMF_FWS_TYPE_PKTTAG_LEN], &pktseq,
++ sizeof(pktseq));
++ }
++ wlh += wlh[1] + 2;
++
++ if (entry->send_tim_signal) {
++ entry->send_tim_signal = 0;
++ wlh[0] = BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP;
++ wlh[1] = BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP_LEN;
++ wlh[2] = entry->mac_handle;
++ wlh[3] = entry->traffic_pending_bmp;
++ brcmf_dbg(TRACE, "adding TIM info: handle %d bmp 0x%X\n",
++ entry->mac_handle, entry->traffic_pending_bmp);
++ wlh += BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP_LEN + 2;
++ entry->traffic_lastreported_bmp = entry->traffic_pending_bmp;
+ }
+- /* request a TIM update to firmware at the next piggyback opportunity */
++ if (fillers)
++ memset(wlh, BRCMF_FWS_TYPE_FILLER, fillers);
++
++ return (u8)(data_offset >> 2);
++}
++
++static bool brcmf_fws_tim_update(struct brcmf_fws_info *fws,
++ struct brcmf_fws_mac_descriptor *entry,
++ int fifo, bool send_immediately)
++{
++ struct sk_buff *skb;
++ struct brcmf_skbuff_cb *skcb;
++ s32 err;
++ u32 len;
++ u8 data_offset;
++ int ifidx;
++
++ /* check delayedQ and suppressQ in one call using bitmap */
++ if (brcmu_pktq_mlen(&entry->psq, 3 << (fifo * 2)) == 0)
++ entry->traffic_pending_bmp &= ~NBITVAL(fifo);
++ else
++ entry->traffic_pending_bmp |= NBITVAL(fifo);
++
++ entry->send_tim_signal = false;
+ if (entry->traffic_lastreported_bmp != entry->traffic_pending_bmp)
+ entry->send_tim_signal = true;
++ if (send_immediately && entry->send_tim_signal &&
++ entry->state == BRCMF_FWS_STATE_CLOSE) {
++ /* create a dummy packet and sent that. The traffic */
++ /* bitmap info will automatically be attached to that packet */
++ len = BRCMF_FWS_TYPE_PKTTAG_LEN + 2 +
++ BRCMF_FWS_TYPE_SEQ_LEN +
++ BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP_LEN + 2 +
++ 4 + fws->drvr->hdrlen;
++ skb = brcmu_pkt_buf_get_skb(len);
++ if (skb == NULL)
++ return false;
++ skb_pull(skb, len);
++ skcb = brcmf_skbcb(skb);
++ skcb->mac = entry;
++ skcb->state = BRCMF_FWS_SKBSTATE_TIM;
++ skcb->htod = 0;
++ skcb->htod_seq = 0;
++ data_offset = brcmf_fws_hdrpush(fws, skb);
++ ifidx = brcmf_skb_if_flags_get_field(skb, INDEX);
++ brcmf_fws_unlock(fws);
++ err = brcmf_proto_txdata(fws->drvr, ifidx, data_offset, skb);
++ brcmf_fws_lock(fws);
++ if (err)
++ brcmu_pkt_buf_free_skb(skb);
++ return true;
++ }
++ return false;
+ }
+
+ static void
+ brcmf_fws_flow_control_check(struct brcmf_fws_info *fws, struct pktq *pq,
+ u8 if_id)
+ {
+- struct brcmf_if *ifp = fws->drvr->iflist[if_id];
++ struct brcmf_if *ifp = fws->drvr->iflist[!if_id ? 0 : if_id + 1];
+
+ if (WARN_ON(!ifp))
+ return;
+
+- brcmf_dbg(TRACE,
+- "enter: bssidx=%d, ifidx=%d\n", ifp->bssidx, ifp->ifidx);
+-
+ if ((ifp->netif_stop & BRCMF_NETIF_STOP_REASON_FWS_FC) &&
+ pq->len <= BRCMF_FWS_FLOWCONTROL_LOWATER)
+ brcmf_txflowblock_if(ifp,
+ BRCMF_NETIF_STOP_REASON_FWS_FC, false);
+ if (!(ifp->netif_stop & BRCMF_NETIF_STOP_REASON_FWS_FC) &&
+- pq->len >= BRCMF_FWS_FLOWCONTROL_HIWATER)
++ pq->len >= BRCMF_FWS_FLOWCONTROL_HIWATER) {
++ fws->stats.fws_flow_block++;
+ brcmf_txflowblock_if(ifp, BRCMF_NETIF_STOP_REASON_FWS_FC, true);
++ }
+ return;
+ }
+
+@@ -876,34 +980,44 @@
+
+ entry = &fws->desc.nodes[mac_handle & 0x1F];
+ if (type == BRCMF_FWS_TYPE_MACDESC_DEL) {
+- brcmf_dbg(TRACE, "deleting mac %pM idx %d\n", addr, ifidx);
+ if (entry->occupied) {
+- brcmf_fws_mac_desc_cleanup(fws, entry, -1);
+- brcmf_fws_clear_mac_descriptor(entry);
++ brcmf_dbg(TRACE, "deleting %s mac %pM\n",
++ entry->name, addr);
++ brcmf_fws_lock(fws);
++ brcmf_fws_macdesc_cleanup(fws, entry, -1);
++ brcmf_fws_macdesc_deinit(entry);
++ brcmf_fws_unlock(fws);
+ } else
+ fws->stats.mac_update_failed++;
+ return 0;
+ }
+
+- brcmf_dbg(TRACE,
+- "add mac %pM handle %u idx %d\n", addr, mac_handle, ifidx);
+- existing = brcmf_fws_mac_descriptor_lookup(fws, addr);
++ existing = brcmf_fws_macdesc_lookup(fws, addr);
+ if (IS_ERR(existing)) {
+ if (!entry->occupied) {
++ brcmf_fws_lock(fws);
+ entry->mac_handle = mac_handle;
+- brcmf_fws_init_mac_descriptor(entry, addr, ifidx);
++ brcmf_fws_macdesc_init(entry, addr, ifidx);
++ brcmf_fws_macdesc_set_name(fws, entry);
+ brcmu_pktq_init(&entry->psq, BRCMF_FWS_PSQ_PREC_COUNT,
+ BRCMF_FWS_PSQ_LEN);
++ brcmf_fws_unlock(fws);
++ brcmf_dbg(TRACE, "add %s mac %pM\n", entry->name, addr);
+ } else {
+ fws->stats.mac_update_failed++;
+ }
+ } else {
+ if (entry != existing) {
+- brcmf_dbg(TRACE, "relocate mac\n");
++ brcmf_dbg(TRACE, "copy mac %s\n", existing->name);
++ brcmf_fws_lock(fws);
+ memcpy(entry, existing,
+ offsetof(struct brcmf_fws_mac_descriptor, psq));
+ entry->mac_handle = mac_handle;
+- brcmf_fws_clear_mac_descriptor(existing);
++ brcmf_fws_macdesc_deinit(existing);
++ brcmf_fws_macdesc_set_name(fws, entry);
++ brcmf_fws_unlock(fws);
++ brcmf_dbg(TRACE, "relocate %s mac %pM\n", entry->name,
++ addr);
+ } else {
+ brcmf_dbg(TRACE, "use existing\n");
+ WARN_ON(entry->mac_handle != mac_handle);
+@@ -918,7 +1032,7 @@
+ {
+ struct brcmf_fws_mac_descriptor *entry;
+ u8 mac_handle;
+- int i;
++ int ret;
+
+ mac_handle = data[0];
+ entry = &fws->desc.nodes[mac_handle & 0x1F];
+@@ -926,18 +1040,23 @@
+ fws->stats.mac_ps_update_failed++;
+ return -ESRCH;
+ }
+-
+- /* a state update should wipe old credits? */
++ brcmf_fws_lock(fws);
++ /* a state update should wipe old credits */
+ entry->requested_credit = 0;
++ entry->requested_packet = 0;
+ if (type == BRCMF_FWS_TYPE_MAC_OPEN) {
+ entry->state = BRCMF_FWS_STATE_OPEN;
+- return BRCMF_FWS_RET_OK_SCHEDULE;
++ ret = BRCMF_FWS_RET_OK_SCHEDULE;
+ } else {
+ entry->state = BRCMF_FWS_STATE_CLOSE;
+- for (i = BRCMF_FWS_FIFO_AC_BE; i < NL80211_NUM_ACS; i++)
+- brcmf_fws_tim_update(fws, entry, i);
++ brcmf_fws_tim_update(fws, entry, BRCMF_FWS_FIFO_AC_BK, false);
++ brcmf_fws_tim_update(fws, entry, BRCMF_FWS_FIFO_AC_BE, false);
++ brcmf_fws_tim_update(fws, entry, BRCMF_FWS_FIFO_AC_VI, false);
++ brcmf_fws_tim_update(fws, entry, BRCMF_FWS_FIFO_AC_VO, true);
++ ret = BRCMF_FWS_RET_OK_NOSCHEDULE;
+ }
+- return BRCMF_FWS_RET_OK_NOSCHEDULE;
++ brcmf_fws_unlock(fws);
++ return ret;
+ }
+
+ static int brcmf_fws_interface_state_indicate(struct brcmf_fws_info *fws,
+@@ -949,7 +1068,6 @@
+
+ ifidx = data[0];
+
+- brcmf_dbg(TRACE, "enter: ifidx=%d\n", ifidx);
+ if (ifidx >= BRCMF_MAX_IFS) {
+ ret = -ERANGE;
+ goto fail;
+@@ -961,17 +1079,26 @@
+ goto fail;
+ }
+
++ brcmf_dbg(TRACE, "%s (%d): %s\n", brcmf_fws_get_tlv_name(type), type,
++ entry->name);
++ brcmf_fws_lock(fws);
+ switch (type) {
+ case BRCMF_FWS_TYPE_INTERFACE_OPEN:
+ entry->state = BRCMF_FWS_STATE_OPEN;
+- return BRCMF_FWS_RET_OK_SCHEDULE;
++ ret = BRCMF_FWS_RET_OK_SCHEDULE;
++ break;
+ case BRCMF_FWS_TYPE_INTERFACE_CLOSE:
+ entry->state = BRCMF_FWS_STATE_CLOSE;
+- return BRCMF_FWS_RET_OK_NOSCHEDULE;
++ ret = BRCMF_FWS_RET_OK_NOSCHEDULE;
++ break;
+ default:
+ ret = -EINVAL;
+- break;
++ brcmf_fws_unlock(fws);
++ goto fail;
+ }
++ brcmf_fws_unlock(fws);
++ return ret;
++
+ fail:
+ fws->stats.if_update_failed++;
+ return ret;
+@@ -991,15 +1118,51 @@
+ return -ESRCH;
+ }
+
++ brcmf_dbg(TRACE, "%s (%d): %s cnt %d bmp %d\n",
++ brcmf_fws_get_tlv_name(type), type, entry->name,
++ data[0], data[2]);
++ brcmf_fws_lock(fws);
+ if (type == BRCMF_FWS_TYPE_MAC_REQUEST_CREDIT)
+ entry->requested_credit = data[0];
+ else
+ entry->requested_packet = data[0];
+
+ entry->ac_bitmap = data[2];
++ brcmf_fws_unlock(fws);
+ return BRCMF_FWS_RET_OK_SCHEDULE;
+ }
+
++static void
++brcmf_fws_macdesc_use_req_credit(struct brcmf_fws_mac_descriptor *entry,
++ struct sk_buff *skb)
++{
++ if (entry->requested_credit > 0) {
++ entry->requested_credit--;
++ brcmf_skb_if_flags_set_field(skb, REQUESTED, 1);
++ brcmf_skb_if_flags_set_field(skb, REQ_CREDIT, 1);
++ if (entry->state != BRCMF_FWS_STATE_CLOSE)
++ brcmf_err("requested credit set while mac not closed!\n");
++ } else if (entry->requested_packet > 0) {
++ entry->requested_packet--;
++ brcmf_skb_if_flags_set_field(skb, REQUESTED, 1);
++ brcmf_skb_if_flags_set_field(skb, REQ_CREDIT, 0);
++ if (entry->state != BRCMF_FWS_STATE_CLOSE)
++ brcmf_err("requested packet set while mac not closed!\n");
++ } else {
++ brcmf_skb_if_flags_set_field(skb, REQUESTED, 0);
++ brcmf_skb_if_flags_set_field(skb, REQ_CREDIT, 0);
++ }
++}
++
++static void brcmf_fws_macdesc_return_req_credit(struct sk_buff *skb)
++{
++ struct brcmf_fws_mac_descriptor *entry = brcmf_skbcb(skb)->mac;
++
++ if ((brcmf_skb_if_flags_get_field(skb, REQ_CREDIT)) &&
++ (entry->state == BRCMF_FWS_STATE_CLOSE))
++ entry->requested_credit++;
++}
++
+ static void brcmf_fws_return_credits(struct brcmf_fws_info *fws,
+ u8 fifo, u8 credits)
+ {
+@@ -1010,6 +1173,8 @@
+ if (!credits)
+ return;
+
++ fws->fifo_credit_map |= 1 << fifo;
++
+ if ((fifo == BRCMF_FWS_FIFO_AC_BE) &&
+ (fws->credits_borrowed[0])) {
+ for (lender_ac = BRCMF_FWS_FIFO_AC_VO; lender_ac >= 0;
+@@ -1031,46 +1196,30 @@
+ }
+ }
+
+- fws->fifo_credit_map |= 1 << fifo;
+ fws->fifo_credit[fifo] += credits;
+ }
+
+ static void brcmf_fws_schedule_deq(struct brcmf_fws_info *fws)
+ {
+ /* only schedule dequeue when there are credits for delayed traffic */
+- if (fws->fifo_credit_map & fws->fifo_delay_map)
++ if ((fws->fifo_credit_map & fws->fifo_delay_map) ||
++ (!brcmf_fws_fc_active(fws) && fws->fifo_delay_map))
+ queue_work(fws->fws_wq, &fws->fws_dequeue_work);
+ }
+
+-static void brcmf_skb_pick_up_credit(struct brcmf_fws_info *fws, int fifo,
+- struct sk_buff *p)
+-{
+- struct brcmf_fws_mac_descriptor *entry = brcmf_skbcb(p)->mac;
+-
+- if (brcmf_skbcb(p)->if_flags & BRCMF_SKB_IF_FLAGS_CREDITCHECK_MASK) {
+- if (fws->fcmode != BRCMF_FWS_FCMODE_IMPLIED_CREDIT)
+- return;
+- brcmf_fws_return_credits(fws, fifo, 1);
+- } else {
+- /*
+- * if this packet did not count against FIFO credit, it
+- * must have taken a requested_credit from the destination
+- * entry (for pspoll etc.)
+- */
+- if (!brcmf_skb_if_flags_get_field(p, REQUESTED))
+- entry->requested_credit++;
+- }
+- brcmf_fws_schedule_deq(fws);
+-}
+-
+ static int brcmf_fws_enq(struct brcmf_fws_info *fws,
+ enum brcmf_fws_skb_state state, int fifo,
+ struct sk_buff *p)
+ {
+ int prec = 2 * fifo;
+ u32 *qfull_stat = &fws->stats.delayq_full_error;
+-
+ struct brcmf_fws_mac_descriptor *entry;
++ struct pktq *pq;
++ struct sk_buff_head *queue;
++ struct sk_buff *p_head;
++ struct sk_buff *p_tail;
++ u32 fr_new;
++ u32 fr_compare;
+
+ entry = brcmf_skbcb(p)->mac;
+ if (entry == NULL) {
+@@ -1078,13 +1227,59 @@
+ return -ENOENT;
+ }
+
+- brcmf_dbg(TRACE, "enter: ea=%pM, qlen=%d\n", entry->ea, entry->psq.len);
++ brcmf_dbg(DATA, "enter: fifo %d skb %p\n", fifo, p);
+ if (state == BRCMF_FWS_SKBSTATE_SUPPRESSED) {
+ prec += 1;
+ qfull_stat = &fws->stats.supprq_full_error;
+- }
+
+- if (brcmu_pktq_penq(&entry->psq, prec, p) == NULL) {
++ /* Fix out of order delivery of frames. Dont assume frame */
++ /* can be inserted at the end, but look for correct position */
++ pq = &entry->psq;
++ if (pktq_full(pq) || pktq_pfull(pq, prec)) {
++ *qfull_stat += 1;
++ return -ENFILE;
++ }
++ queue = &pq->q[prec].skblist;
++
++ p_head = skb_peek(queue);
++ p_tail = skb_peek_tail(queue);
++ fr_new = brcmf_skb_htod_tag_get_field(p, FREERUN);
++
++ while (p_head != p_tail) {
++ fr_compare = brcmf_skb_htod_tag_get_field(p_tail,
++ FREERUN);
++ /* be sure to handle wrap of 256 */
++ if (((fr_new > fr_compare) &&
++ ((fr_new - fr_compare) < 128)) ||
++ ((fr_new < fr_compare) &&
++ ((fr_compare - fr_new) > 128)))
++ break;
++ p_tail = skb_queue_prev(queue, p_tail);
++ }
++ /* Position found. Determine what to do */
++ if (p_tail == NULL) {
++ /* empty list */
++ __skb_queue_tail(queue, p);
++ } else {
++ fr_compare = brcmf_skb_htod_tag_get_field(p_tail,
++ FREERUN);
++ if (((fr_new > fr_compare) &&
++ ((fr_new - fr_compare) < 128)) ||
++ ((fr_new < fr_compare) &&
++ ((fr_compare - fr_new) > 128))) {
++ /* After tail */
++ __skb_queue_after(queue, p_tail, p);
++ } else {
++ /* Before tail */
++ __skb_insert(p, p_tail->prev, p_tail, queue);
++ }
++ }
++
++ /* Complete the counters and statistics */
++ pq->len++;
++ if (pq->hi_prec < prec)
++ pq->hi_prec = (u8) prec;
++ } else if (brcmu_pktq_penq(&entry->psq, prec, p) == NULL) {
+ *qfull_stat += 1;
+ return -ENFILE;
+ }
+@@ -1095,14 +1290,12 @@
+
+ /* update the sk_buff state */
+ brcmf_skbcb(p)->state = state;
+- if (state == BRCMF_FWS_SKBSTATE_SUPPRESSED)
+- entry->suppress_count++;
+
+ /*
+ * A packet has been pushed so update traffic
+ * availability bitmap, if applicable
+ */
+- brcmf_fws_tim_update(fws, entry, fifo);
++ brcmf_fws_tim_update(fws, entry, fifo, true);
+ brcmf_fws_flow_control_check(fws, &entry->psq,
+ brcmf_skb_if_flags_get_field(p, INDEX));
+ return 0;
+@@ -1113,7 +1306,6 @@
+ struct brcmf_fws_mac_descriptor *table;
+ struct brcmf_fws_mac_descriptor *entry;
+ struct sk_buff *p;
+- int use_credit = 1;
+ int num_nodes;
+ int node_pos;
+ int prec_out;
+@@ -1127,7 +1319,7 @@
+ for (i = 0; i < num_nodes; i++) {
+ entry = &table[(node_pos + i) % num_nodes];
+ if (!entry->occupied ||
+- brcmf_fws_mac_desc_closed(fws, entry, fifo))
++ brcmf_fws_macdesc_closed(fws, entry, fifo))
+ continue;
+
+ if (entry->suppressed)
+@@ -1137,9 +1329,8 @@
+ p = brcmu_pktq_mdeq(&entry->psq, pmsk << (fifo * 2), &prec_out);
+ if (p == NULL) {
+ if (entry->suppressed) {
+- if (entry->suppr_transit_count >
+- entry->suppress_count)
+- return NULL;
++ if (entry->suppr_transit_count)
++ continue;
+ entry->suppressed = false;
+ p = brcmu_pktq_mdeq(&entry->psq,
+ 1 << (fifo * 2), &prec_out);
+@@ -1148,26 +1339,7 @@
+ if (p == NULL)
+ continue;
+
+- /* did the packet come from suppress sub-queue? */
+- if (entry->requested_credit > 0) {
+- entry->requested_credit--;
+- /*
+- * if the packet was pulled out while destination is in
+- * closed state but had a non-zero packets requested,
+- * then this should not count against the FIFO credit.
+- * That is due to the fact that the firmware will
+- * most likely hold onto this packet until a suitable
+- * time later to push it to the appropriate AC FIFO.
+- */
+- if (entry->state == BRCMF_FWS_STATE_CLOSE)
+- use_credit = 0;
+- } else if (entry->requested_packet > 0) {
+- entry->requested_packet--;
+- brcmf_skb_if_flags_set_field(p, REQUESTED, 1);
+- if (entry->state == BRCMF_FWS_STATE_CLOSE)
+- use_credit = 0;
+- }
+- brcmf_skb_if_flags_set_field(p, CREDITCHECK, use_credit);
++ brcmf_fws_macdesc_use_req_credit(entry, p);
+
+ /* move dequeue position to ensure fair round-robin */
+ fws->deq_node_pos[fifo] = (node_pos + i + 1) % num_nodes;
+@@ -1179,7 +1351,7 @@
+ * A packet has been picked up, update traffic
+ * availability bitmap, if applicable
+ */
+- brcmf_fws_tim_update(fws, entry, fifo);
++ brcmf_fws_tim_update(fws, entry, fifo, false);
+
+ /*
+ * decrement total enqueued fifo packets and
+@@ -1192,32 +1364,47 @@
+ }
+ p = NULL;
+ done:
+- brcmf_dbg(TRACE, "exit: fifo %d skb %p\n", fifo, p);
++ brcmf_dbg(DATA, "exit: fifo %d skb %p\n", fifo, p);
+ return p;
+ }
+
+ static int brcmf_fws_txstatus_suppressed(struct brcmf_fws_info *fws, int fifo,
+- struct sk_buff *skb, u32 genbit)
++ struct sk_buff *skb, u32 genbit,
++ u16 seq)
+ {
+ struct brcmf_fws_mac_descriptor *entry = brcmf_skbcb(skb)->mac;
+ u32 hslot;
+ int ret;
++ u8 ifidx;
+
+ hslot = brcmf_skb_htod_tag_get_field(skb, HSLOT);
+
+ /* this packet was suppressed */
+- if (!entry->suppressed || entry->generation != genbit) {
++ if (!entry->suppressed) {
+ entry->suppressed = true;
+- entry->suppress_count = brcmu_pktq_mlen(&entry->psq,
+- 1 << (fifo * 2 + 1));
+ entry->suppr_transit_count = entry->transit_count;
++ brcmf_dbg(DATA, "suppress %s: transit %d\n",
++ entry->name, entry->transit_count);
+ }
+
+ entry->generation = genbit;
+
+- ret = brcmf_fws_enq(fws, BRCMF_FWS_SKBSTATE_SUPPRESSED, fifo, skb);
++ ret = brcmf_proto_hdrpull(fws->drvr, false, &ifidx, skb);
++ if (ret == 0) {
++ brcmf_skb_htod_tag_set_field(skb, GENERATION, genbit);
++ brcmf_skbcb(skb)->htod_seq = seq;
++ if (brcmf_skb_htod_seq_get_field(skb, FROMFW)) {
++ brcmf_skb_htod_seq_set_field(skb, FROMDRV, 1);
++ brcmf_skb_htod_seq_set_field(skb, FROMFW, 0);
++ } else {
++ brcmf_skb_htod_seq_set_field(skb, FROMDRV, 0);
++ }
++ ret = brcmf_fws_enq(fws, BRCMF_FWS_SKBSTATE_SUPPRESSED, fifo,
++ skb);
++ }
++
+ if (ret != 0) {
+- /* suppress q is full, drop this packet */
++ /* suppress q is full or hdrpull failed, drop this packet */
+ brcmf_fws_hanger_poppkt(&fws->hanger, hslot, &skb,
+ true);
+ } else {
+@@ -1225,26 +1412,24 @@
+ * Mark suppressed to avoid a double free during
+ * wlfc cleanup
+ */
+- brcmf_fws_hanger_mark_suppressed(&fws->hanger, hslot,
+- genbit);
+- entry->suppress_count++;
++ brcmf_fws_hanger_mark_suppressed(&fws->hanger, hslot);
+ }
+
+ return ret;
+ }
+
+ static int
+-brcmf_fws_txstatus_process(struct brcmf_fws_info *fws, u8 flags, u32 hslot,
+- u32 genbit)
++brcmf_fws_txs_process(struct brcmf_fws_info *fws, u8 flags, u32 hslot,
++ u32 genbit, u16 seq)
+ {
+ u32 fifo;
+ int ret;
+ bool remove_from_hanger = true;
+ struct sk_buff *skb;
++ struct brcmf_skbuff_cb *skcb;
+ struct brcmf_fws_mac_descriptor *entry = NULL;
+
+- brcmf_dbg(TRACE, "status: flags=0x%X, hslot=%d\n",
+- flags, hslot);
++ brcmf_dbg(DATA, "flags %d\n", flags);
+
+ if (flags == BRCMF_FWS_TXSTATUS_DISCARD)
+ fws->stats.txs_discard++;
+@@ -1256,6 +1441,8 @@
+ remove_from_hanger = false;
+ } else if (flags == BRCMF_FWS_TXSTATUS_FW_TOSSED)
+ fws->stats.txs_tossed++;
++ else if (flags == BRCMF_FWS_TXSTATUS_HOST_TOSSED)
++ fws->stats.txs_host_tossed++;
+ else
+ brcmf_err("unexpected txstatus\n");
+
+@@ -1266,26 +1453,36 @@
+ return ret;
+ }
+
+- entry = brcmf_skbcb(skb)->mac;
++ skcb = brcmf_skbcb(skb);
++ entry = skcb->mac;
+ if (WARN_ON(!entry)) {
+ brcmu_pkt_buf_free_skb(skb);
+ return -EINVAL;
+ }
++ entry->transit_count--;
++ if (entry->suppressed && entry->suppr_transit_count)
++ entry->suppr_transit_count--;
++
++ brcmf_dbg(DATA, "%s flags %d htod %X seq %X\n", entry->name, flags,
++ skcb->htod, seq);
+
+ /* pick up the implicit credit from this packet */
+ fifo = brcmf_skb_htod_tag_get_field(skb, FIFO);
+- brcmf_skb_pick_up_credit(fws, fifo, skb);
++ if ((fws->fcmode == BRCMF_FWS_FCMODE_IMPLIED_CREDIT) ||
++ (brcmf_skb_if_flags_get_field(skb, REQ_CREDIT)) ||
++ (flags == BRCMF_FWS_TXSTATUS_HOST_TOSSED)) {
++ brcmf_fws_return_credits(fws, fifo, 1);
++ brcmf_fws_schedule_deq(fws);
++ }
++ brcmf_fws_macdesc_return_req_credit(skb);
+
+ if (!remove_from_hanger)
+- ret = brcmf_fws_txstatus_suppressed(fws, fifo, skb, genbit);
+-
+- if (remove_from_hanger || ret) {
+- entry->transit_count--;
+- if (entry->suppressed)
+- entry->suppr_transit_count--;
++ ret = brcmf_fws_txstatus_suppressed(fws, fifo, skb, genbit,
++ seq);
+
++ if (remove_from_hanger || ret)
+ brcmf_txfinalize(fws->drvr, skb, true);
+- }
++
+ return 0;
+ }
+
+@@ -1299,22 +1496,26 @@
+ return BRCMF_FWS_RET_OK_NOSCHEDULE;
+ }
+
+- brcmf_dbg(TRACE, "enter: data %pM\n", data);
++ brcmf_dbg(DATA, "enter: data %pM\n", data);
++ brcmf_fws_lock(fws);
+ for (i = 0; i < BRCMF_FWS_FIFO_COUNT; i++)
+ brcmf_fws_return_credits(fws, i, data[i]);
+
+- brcmf_dbg(INFO, "map: credit %x delay %x\n", fws->fifo_credit_map,
++ brcmf_dbg(DATA, "map: credit %x delay %x\n", fws->fifo_credit_map,
+ fws->fifo_delay_map);
++ brcmf_fws_unlock(fws);
+ return BRCMF_FWS_RET_OK_SCHEDULE;
+ }
+
+ static int brcmf_fws_txstatus_indicate(struct brcmf_fws_info *fws, u8 *data)
+ {
+ __le32 status_le;
++ __le16 seq_le;
+ u32 status;
+ u32 hslot;
+ u32 genbit;
+ u8 flags;
++ u16 seq;
+
+ fws->stats.txs_indicate++;
+ memcpy(&status_le, data, sizeof(status_le));
+@@ -1322,8 +1523,18 @@
+ flags = brcmf_txstatus_get_field(status, FLAGS);
+ hslot = brcmf_txstatus_get_field(status, HSLOT);
+ genbit = brcmf_txstatus_get_field(status, GENERATION);
++ if (BRCMF_FWS_MODE_GET_REUSESEQ(fws->mode)) {
++ memcpy(&seq_le, &data[BRCMF_FWS_TYPE_PKTTAG_LEN],
++ sizeof(seq_le));
++ seq = le16_to_cpu(seq_le);
++ } else {
++ seq = 0;
++ }
+
+- return brcmf_fws_txstatus_process(fws, flags, hslot, genbit);
++ brcmf_fws_lock(fws);
++ brcmf_fws_txs_process(fws, flags, hslot, genbit, seq);
++ brcmf_fws_unlock(fws);
++ return BRCMF_FWS_RET_OK_NOSCHEDULE;
+ }
+
+ static int brcmf_fws_dbg_seqnum_check(struct brcmf_fws_info *fws, u8 *data)
+@@ -1331,42 +1542,30 @@
+ __le32 timestamp;
+
+ memcpy(&timestamp, &data[2], sizeof(timestamp));
+- brcmf_dbg(INFO, "received: seq %d, timestamp %d\n", data[1],
++ brcmf_dbg(CTL, "received: seq %d, timestamp %d\n", data[1],
+ le32_to_cpu(timestamp));
+ return 0;
+ }
+
+-/* using macro so sparse checking does not complain
+- * about locking imbalance.
+- */
+-#define brcmf_fws_lock(drvr, flags) \
+-do { \
+- flags = 0; \
+- spin_lock_irqsave(&((drvr)->fws_spinlock), (flags)); \
+-} while (0)
+-
+-/* using macro so sparse checking does not complain
+- * about locking imbalance.
+- */
+-#define brcmf_fws_unlock(drvr, flags) \
+- spin_unlock_irqrestore(&((drvr)->fws_spinlock), (flags))
+-
+ static int brcmf_fws_notify_credit_map(struct brcmf_if *ifp,
+ const struct brcmf_event_msg *e,
+ void *data)
+ {
+ struct brcmf_fws_info *fws = ifp->drvr->fws;
+ int i;
+- ulong flags;
+ u8 *credits = data;
+
+ if (e->datalen < BRCMF_FWS_FIFO_COUNT) {
+ brcmf_err("event payload too small (%d)\n", e->datalen);
+ return -EINVAL;
+ }
++ if (fws->creditmap_received)
++ return 0;
++
++ fws->creditmap_received = true;
+
+ brcmf_dbg(TRACE, "enter: credits %pM\n", credits);
+- brcmf_fws_lock(ifp->drvr, flags);
++ brcmf_fws_lock(fws);
+ for (i = 0; i < ARRAY_SIZE(fws->fifo_credit); i++) {
+ if (*credits)
+ fws->fifo_credit_map |= 1 << i;
+@@ -1375,15 +1574,28 @@
+ fws->fifo_credit[i] = *credits++;
+ }
+ brcmf_fws_schedule_deq(fws);
+- brcmf_fws_unlock(ifp->drvr, flags);
++ brcmf_fws_unlock(fws);
++ return 0;
++}
++
++static int brcmf_fws_notify_bcmc_credit_support(struct brcmf_if *ifp,
++ const struct brcmf_event_msg *e,
++ void *data)
++{
++ struct brcmf_fws_info *fws = ifp->drvr->fws;
++
++ brcmf_fws_lock(fws);
++ if (fws)
++ fws->bcmc_credit_check = true;
++ brcmf_fws_unlock(fws);
+ return 0;
+ }
+
+ int brcmf_fws_hdrpull(struct brcmf_pub *drvr, int ifidx, s16 signal_len,
+ struct sk_buff *skb)
+ {
++ struct brcmf_skb_reorder_data *rd;
+ struct brcmf_fws_info *fws = drvr->fws;
+- ulong flags;
+ u8 *signal_data;
+ s16 data_len;
+ u8 type;
+@@ -1392,20 +1604,19 @@
+ s32 status;
+ s32 err;
+
+- brcmf_dbg(TRACE, "enter: ifidx %d, skblen %u, sig %d\n",
++ brcmf_dbg(HDRS, "enter: ifidx %d, skblen %u, sig %d\n",
+ ifidx, skb->len, signal_len);
+
+ WARN_ON(signal_len > skb->len);
+
++ if (!signal_len)
++ return 0;
+ /* if flow control disabled, skip to packet data and leave */
+- if (!signal_len || !drvr->fw_signals) {
++ if (!fws->fw_signals) {
+ skb_pull(skb, signal_len);
+ return 0;
+ }
+
+- /* lock during tlv parsing */
+- brcmf_fws_lock(drvr, flags);
+-
+ fws->stats.header_pulls++;
+ data_len = signal_len;
+ signal_data = skb->data;
+@@ -1426,21 +1637,25 @@
+ len = signal_data[1];
+ data = signal_data + 2;
+
+- brcmf_dbg(INFO, "tlv type=%d (%s), len=%d, data[0]=%d\n", type,
+- brcmf_fws_get_tlv_name(type), len, *data);
++ brcmf_dbg(HDRS, "tlv type=%s (%d), len=%d (%d)\n",
++ brcmf_fws_get_tlv_name(type), type, len,
++ brcmf_fws_get_tlv_len(fws, type));
+
+ /* abort parsing when length invalid */
+ if (data_len < len + 2)
+ break;
+
+- if (len != brcmf_fws_get_tlv_len(fws, type))
++ if (len < brcmf_fws_get_tlv_len(fws, type))
+ break;
+
+ err = BRCMF_FWS_RET_OK_NOSCHEDULE;
+ switch (type) {
+- case BRCMF_FWS_TYPE_HOST_REORDER_RXPKTS:
+ case BRCMF_FWS_TYPE_COMP_TXSTATUS:
+ break;
++ case BRCMF_FWS_TYPE_HOST_REORDER_RXPKTS:
++ rd = (struct brcmf_skb_reorder_data *)skb->cb;
++ rd->reorder = data;
++ break;
+ case BRCMF_FWS_TYPE_MACDESC_ADD:
+ case BRCMF_FWS_TYPE_MACDESC_DEL:
+ brcmf_fws_macdesc_indicate(fws, type, data);
+@@ -1498,203 +1713,74 @@
+ if (skb->len == 0)
+ fws->stats.header_only_pkt++;
+
+- brcmf_fws_unlock(drvr, flags);
+ return 0;
+ }
+
+-static int brcmf_fws_hdrpush(struct brcmf_fws_info *fws, struct sk_buff *skb)
+-{
+- struct brcmf_fws_mac_descriptor *entry = brcmf_skbcb(skb)->mac;
+- u8 *wlh;
+- u16 data_offset = 0;
+- u8 fillers;
+- __le32 pkttag = cpu_to_le32(brcmf_skbcb(skb)->htod);
+-
+- brcmf_dbg(TRACE, "enter: ea=%pM, ifidx=%u, pkttag=0x%08X\n",
+- entry->ea, entry->interface_id, le32_to_cpu(pkttag));
+- if (entry->send_tim_signal)
+- data_offset += 2 + BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP_LEN;
+-
+- /* +2 is for Type[1] and Len[1] in TLV, plus TIM signal */
+- data_offset += 2 + BRCMF_FWS_TYPE_PKTTAG_LEN;
+- fillers = round_up(data_offset, 4) - data_offset;
+- data_offset += fillers;
+-
+- skb_push(skb, data_offset);
+- wlh = skb->data;
+-
+- wlh[0] = BRCMF_FWS_TYPE_PKTTAG;
+- wlh[1] = BRCMF_FWS_TYPE_PKTTAG_LEN;
+- memcpy(&wlh[2], &pkttag, sizeof(pkttag));
+- wlh += BRCMF_FWS_TYPE_PKTTAG_LEN + 2;
+-
+- if (entry->send_tim_signal) {
+- entry->send_tim_signal = 0;
+- wlh[0] = BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP;
+- wlh[1] = BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP_LEN;
+- wlh[2] = entry->mac_handle;
+- wlh[3] = entry->traffic_pending_bmp;
+- wlh += BRCMF_FWS_TYPE_PENDING_TRAFFIC_BMP_LEN + 2;
+- entry->traffic_lastreported_bmp = entry->traffic_pending_bmp;
+- }
+- if (fillers)
+- memset(wlh, BRCMF_FWS_TYPE_FILLER, fillers);
+-
+- brcmf_proto_hdrpush(fws->drvr, brcmf_skb_if_flags_get_field(skb, INDEX),
+- data_offset >> 2, skb);
+- return 0;
+-}
+-
+-static int brcmf_fws_precommit_skb(struct brcmf_fws_info *fws, int fifo,
++static u8 brcmf_fws_precommit_skb(struct brcmf_fws_info *fws, int fifo,
+ struct sk_buff *p)
+ {
+ struct brcmf_skbuff_cb *skcb = brcmf_skbcb(p);
+ struct brcmf_fws_mac_descriptor *entry = skcb->mac;
+- int rc = 0;
+- bool header_needed;
+- int hslot = BRCMF_FWS_HANGER_MAXITEMS;
+- u8 free_ctr;
+- u8 ifidx;
+ u8 flags;
+
+- header_needed = skcb->state != BRCMF_FWS_SKBSTATE_SUPPRESSED;
+-
+- if (header_needed) {
+- /* obtaining free slot may fail, but that will be caught
+- * by the hanger push. This assures the packet has a BDC
+- * header upon return.
+- */
+- hslot = brcmf_fws_hanger_get_free_slot(&fws->hanger);
+- free_ctr = entry->seq[fifo];
+- brcmf_skb_htod_tag_set_field(p, HSLOT, hslot);
+- brcmf_skb_htod_tag_set_field(p, FREERUN, free_ctr);
+- brcmf_skb_htod_tag_set_field(p, GENERATION, 1);
+- entry->transit_count++;
+- }
+- brcmf_skb_if_flags_set_field(p, TRANSMIT, 1);
+- brcmf_skb_htod_tag_set_field(p, FIFO, fifo);
+-
++ if (skcb->state != BRCMF_FWS_SKBSTATE_SUPPRESSED)
++ brcmf_skb_htod_tag_set_field(p, GENERATION, entry->generation);
+ flags = BRCMF_FWS_HTOD_FLAG_PKTFROMHOST;
+- if (!(skcb->if_flags & BRCMF_SKB_IF_FLAGS_CREDITCHECK_MASK)) {
++ if (brcmf_skb_if_flags_get_field(p, REQUESTED)) {
+ /*
+- Indicate that this packet is being sent in response to an
+- explicit request from the firmware side.
+- */
++ * Indicate that this packet is being sent in response to an
++ * explicit request from the firmware side.
++ */
+ flags |= BRCMF_FWS_HTOD_FLAG_PKT_REQUESTED;
+ }
+ brcmf_skb_htod_tag_set_field(p, FLAGS, flags);
+- if (header_needed) {
+- brcmf_fws_hdrpush(fws, p);
+- rc = brcmf_fws_hanger_pushpkt(&fws->hanger, p, hslot);
+- if (rc)
+- brcmf_err("hanger push failed: rc=%d\n", rc);
+- } else {
+- int gen;
+-
+- /* remove old header */
+- rc = brcmf_proto_hdrpull(fws->drvr, false, &ifidx, p);
+- if (rc == 0) {
+- hslot = brcmf_skb_htod_tag_get_field(p, HSLOT);
+- brcmf_fws_hanger_get_genbit(&fws->hanger, p,
+- hslot, &gen);
+- brcmf_skb_htod_tag_set_field(p, GENERATION, gen);
+-
+- /* push new header */
+- brcmf_fws_hdrpush(fws, p);
+- }
+- }
+-
+- return rc;
++ return brcmf_fws_hdrpush(fws, p);
+ }
+
+-static void
+-brcmf_fws_rollback_toq(struct brcmf_fws_info *fws, struct sk_buff *skb)
++static void brcmf_fws_rollback_toq(struct brcmf_fws_info *fws,
++ struct sk_buff *skb, int fifo)
+ {
+- /*
+- put the packet back to the head of queue
+-
+- - suppressed packet goes back to suppress sub-queue
+- - pull out the header, if new or delayed packet
+-
+- Note: hslot is used only when header removal is done.
+- */
+ struct brcmf_fws_mac_descriptor *entry;
+- enum brcmf_fws_skb_state state;
+ struct sk_buff *pktout;
++ int qidx, hslot;
+ int rc = 0;
+- int fifo;
+- int hslot;
+- u8 ifidx;
+
+- fifo = brcmf_skb_if_flags_get_field(skb, FIFO);
+- state = brcmf_skbcb(skb)->state;
+ entry = brcmf_skbcb(skb)->mac;
+-
+- if (entry != NULL) {
+- if (state == BRCMF_FWS_SKBSTATE_SUPPRESSED) {
+- /* wl-header is saved for suppressed packets */
+- pktout = brcmu_pktq_penq_head(&entry->psq, 2 * fifo + 1,
+- skb);
+- if (pktout == NULL) {
+- brcmf_err("suppress queue full\n");
+- rc = -ENOSPC;
+- }
+- } else {
+- hslot = brcmf_skb_htod_tag_get_field(skb, HSLOT);
+-
+- /* remove header first */
+- rc = brcmf_proto_hdrpull(fws->drvr, false, &ifidx, skb);
+- if (rc) {
+- brcmf_err("header removal failed\n");
+- /* free the hanger slot */
+- brcmf_fws_hanger_poppkt(&fws->hanger, hslot,
+- &pktout, true);
+- rc = -EINVAL;
+- goto fail;
+- }
+-
+- /* delay-q packets are going to delay-q */
+- pktout = brcmu_pktq_penq_head(&entry->psq,
+- 2 * fifo, skb);
+- if (pktout == NULL) {
+- brcmf_err("delay queue full\n");
+- rc = -ENOSPC;
+- }
+-
+- /* free the hanger slot */
+- brcmf_fws_hanger_poppkt(&fws->hanger, hslot, &pktout,
+- true);
+-
+- /* decrement sequence count */
+- entry->seq[fifo]--;
++ if (entry->occupied) {
++ qidx = 2 * fifo;
++ if (brcmf_skbcb(skb)->state == BRCMF_FWS_SKBSTATE_SUPPRESSED)
++ qidx++;
++
++ pktout = brcmu_pktq_penq_head(&entry->psq, qidx, skb);
++ if (pktout == NULL) {
++ brcmf_err("%s queue %d full\n", entry->name, qidx);
++ rc = -ENOSPC;
+ }
+- /*
+- if this packet did not count against FIFO credit, it must have
+- taken a requested_credit from the firmware (for pspoll etc.)
+- */
+- if (!(brcmf_skbcb(skb)->if_flags &
+- BRCMF_SKB_IF_FLAGS_CREDITCHECK_MASK))
+- entry->requested_credit++;
+ } else {
+- brcmf_err("no mac entry linked\n");
++ brcmf_err("%s entry removed\n", entry->name);
+ rc = -ENOENT;
+ }
+
+-
+-fail:
+ if (rc) {
+- brcmf_txfinalize(fws->drvr, skb, false);
+ fws->stats.rollback_failed++;
+- } else
++ hslot = brcmf_skb_htod_tag_get_field(skb, HSLOT);
++ brcmf_fws_txs_process(fws, BRCMF_FWS_TXSTATUS_HOST_TOSSED,
++ hslot, 0, 0);
++ } else {
+ fws->stats.rollback_success++;
++ brcmf_fws_return_credits(fws, fifo, 1);
++ brcmf_fws_macdesc_return_req_credit(skb);
++ }
+ }
+
+ static int brcmf_fws_borrow_credit(struct brcmf_fws_info *fws)
+ {
+ int lender_ac;
+
+- if (time_after(fws->borrow_defer_timestamp, jiffies))
++ if (time_after(fws->borrow_defer_timestamp, jiffies)) {
++ fws->fifo_credit_map &= ~(1 << BRCMF_FWS_FIFO_AC_BE);
+ return -ENAVAIL;
++ }
+
+ for (lender_ac = 0; lender_ac <= BRCMF_FWS_FIFO_AC_VO; lender_ac++) {
+ if (fws->fifo_credit[lender_ac]) {
+@@ -1702,99 +1788,75 @@
+ fws->fifo_credit[lender_ac]--;
+ if (fws->fifo_credit[lender_ac] == 0)
+ fws->fifo_credit_map &= ~(1 << lender_ac);
+- brcmf_dbg(TRACE, "borrow credit from: %d\n", lender_ac);
++ fws->fifo_credit_map |= (1 << BRCMF_FWS_FIFO_AC_BE);
++ brcmf_dbg(DATA, "borrow credit from: %d\n", lender_ac);
+ return 0;
+ }
+ }
++ fws->fifo_credit_map &= ~(1 << BRCMF_FWS_FIFO_AC_BE);
+ return -ENAVAIL;
+ }
+
+-static int brcmf_fws_consume_credit(struct brcmf_fws_info *fws, int fifo,
+- struct sk_buff *skb)
+-{
+- struct brcmf_fws_mac_descriptor *entry = brcmf_skbcb(skb)->mac;
+- int *credit = &fws->fifo_credit[fifo];
+- int use_credit = 1;
+-
+- brcmf_dbg(TRACE, "enter: ac=%d, credits=%d\n", fifo, *credit);
+-
+- if (entry->requested_credit > 0) {
+- /*
+- * if the packet was pulled out while destination is in
+- * closed state but had a non-zero packets requested,
+- * then this should not count against the FIFO credit.
+- * That is due to the fact that the firmware will
+- * most likely hold onto this packet until a suitable
+- * time later to push it to the appropriate AC FIFO.
+- */
+- entry->requested_credit--;
+- if (entry->state == BRCMF_FWS_STATE_CLOSE)
+- use_credit = 0;
+- } else if (entry->requested_packet > 0) {
+- entry->requested_packet--;
+- brcmf_skb_if_flags_set_field(skb, REQUESTED, 1);
+- if (entry->state == BRCMF_FWS_STATE_CLOSE)
+- use_credit = 0;
+- }
+- brcmf_skb_if_flags_set_field(skb, CREDITCHECK, use_credit);
+- if (!use_credit) {
+- brcmf_dbg(TRACE, "exit: no creditcheck set\n");
+- return 0;
+- }
+-
+- if (fifo != BRCMF_FWS_FIFO_AC_BE)
+- fws->borrow_defer_timestamp = jiffies +
+- BRCMF_FWS_BORROW_DEFER_PERIOD;
+-
+- if (!(*credit)) {
+- /* Try to borrow a credit from other queue */
+- if (fifo == BRCMF_FWS_FIFO_AC_BE &&
+- brcmf_fws_borrow_credit(fws) == 0)
+- return 0;
+-
+- brcmf_dbg(TRACE, "exit: ac=%d, credits depleted\n", fifo);
+- return -ENAVAIL;
+- }
+- (*credit)--;
+- if (!(*credit))
+- fws->fifo_credit_map &= ~(1 << fifo);
+- brcmf_dbg(TRACE, "exit: ac=%d, credits=%d\n", fifo, *credit);
+- return 0;
+-}
+-
+ static int brcmf_fws_commit_skb(struct brcmf_fws_info *fws, int fifo,
+ struct sk_buff *skb)
+ {
+ struct brcmf_skbuff_cb *skcb = brcmf_skbcb(skb);
+ struct brcmf_fws_mac_descriptor *entry;
+- struct brcmf_bus *bus = fws->drvr->bus_if;
+ int rc;
++ u8 ifidx;
++ u8 data_offset;
+
+ entry = skcb->mac;
+ if (IS_ERR(entry))
+ return PTR_ERR(entry);
+
+- rc = brcmf_fws_precommit_skb(fws, fifo, skb);
++ data_offset = brcmf_fws_precommit_skb(fws, fifo, skb);
++ entry->transit_count++;
++ if (entry->suppressed)
++ entry->suppr_transit_count++;
++ ifidx = brcmf_skb_if_flags_get_field(skb, INDEX);
++ brcmf_fws_unlock(fws);
++ rc = brcmf_proto_txdata(fws->drvr, ifidx, data_offset, skb);
++ brcmf_fws_lock(fws);
++ brcmf_dbg(DATA, "%s flags %X htod %X bus_tx %d\n", entry->name,
++ skcb->if_flags, skcb->htod, rc);
+ if (rc < 0) {
+- fws->stats.generic_error++;
++ entry->transit_count--;
++ if (entry->suppressed)
++ entry->suppr_transit_count--;
++ brcmf_proto_hdrpull(fws->drvr, false, &ifidx, skb);
+ goto rollback;
+ }
+
+- rc = brcmf_bus_txdata(bus, skb);
+- if (rc < 0)
+- goto rollback;
+-
+- entry->seq[fifo]++;
+ fws->stats.pkt2bus++;
+- if (brcmf_skbcb(skb)->if_flags & BRCMF_SKB_IF_FLAGS_CREDITCHECK_MASK) {
+- fws->stats.send_pkts[fifo]++;
+- fws->stats.fifo_credits_sent[fifo]++;
+- }
++ fws->stats.send_pkts[fifo]++;
++ if (brcmf_skb_if_flags_get_field(skb, REQUESTED))
++ fws->stats.requested_sent[fifo]++;
+
+ return rc;
+
+ rollback:
+- brcmf_fws_rollback_toq(fws, skb);
++ brcmf_fws_rollback_toq(fws, skb, fifo);
++ return rc;
++}
++
++static int brcmf_fws_assign_htod(struct brcmf_fws_info *fws, struct sk_buff *p,
++ int fifo)
++{
++ struct brcmf_skbuff_cb *skcb = brcmf_skbcb(p);
++ int rc, hslot;
++
++ skcb->htod = 0;
++ skcb->htod_seq = 0;
++ hslot = brcmf_fws_hanger_get_free_slot(&fws->hanger);
++ brcmf_skb_htod_tag_set_field(p, HSLOT, hslot);
++ brcmf_skb_htod_tag_set_field(p, FREERUN, skcb->mac->seq[fifo]);
++ brcmf_skb_htod_tag_set_field(p, FIFO, fifo);
++ rc = brcmf_fws_hanger_pushpkt(&fws->hanger, p, hslot);
++ if (!rc)
++ skcb->mac->seq[fifo]++;
++ else
++ fws->stats.generic_error++;
+ return rc;
+ }
+
+@@ -1804,53 +1866,47 @@
+ struct brcmf_fws_info *fws = drvr->fws;
+ struct brcmf_skbuff_cb *skcb = brcmf_skbcb(skb);
+ struct ethhdr *eh = (struct ethhdr *)(skb->data);
+- ulong flags;
+ int fifo = BRCMF_FWS_FIFO_BCMC;
+ bool multicast = is_multicast_ether_addr(eh->h_dest);
++ bool pae = eh->h_proto == htons(ETH_P_PAE);
+
++ brcmf_dbg(DATA, "tx proto=0x%X\n", ntohs(eh->h_proto));
+ /* determine the priority */
+ if (!skb->priority)
+ skb->priority = cfg80211_classify8021d(skb);
+
+ drvr->tx_multicast += !!multicast;
+- if (ntohs(eh->h_proto) == ETH_P_PAE)
++ if (pae)
+ atomic_inc(&ifp->pend_8021x_cnt);
+
+- if (!brcmf_fws_fc_active(fws)) {
+- /* If the protocol uses a data header, apply it */
+- brcmf_proto_hdrpush(drvr, ifp->ifidx, 0, skb);
+-
+- /* Use bus module to send data frame */
+- return brcmf_bus_txdata(drvr->bus_if, skb);
+- }
+-
+ /* set control buffer information */
+ skcb->if_flags = 0;
+- skcb->mac = brcmf_fws_find_mac_desc(fws, ifp, eh->h_dest);
+ skcb->state = BRCMF_FWS_SKBSTATE_NEW;
+ brcmf_skb_if_flags_set_field(skb, INDEX, ifp->ifidx);
+ if (!multicast)
+ fifo = brcmf_fws_prio2fifo[skb->priority];
+- brcmf_skb_if_flags_set_field(skb, FIFO, fifo);
+
+- brcmf_dbg(TRACE, "ea=%pM, multi=%d, fifo=%d\n", eh->h_dest,
+- multicast, fifo);
++ brcmf_fws_lock(fws);
++ if (fifo != BRCMF_FWS_FIFO_AC_BE && fifo < BRCMF_FWS_FIFO_BCMC)
++ fws->borrow_defer_timestamp = jiffies +
++ BRCMF_FWS_BORROW_DEFER_PERIOD;
+
+- brcmf_fws_lock(drvr, flags);
+- if (skcb->mac->suppressed ||
+- brcmf_fws_mac_desc_closed(fws, skcb->mac, fifo) ||
+- brcmu_pktq_mlen(&skcb->mac->psq, 3 << (fifo * 2)) ||
+- (!multicast &&
+- brcmf_fws_consume_credit(fws, fifo, skb) < 0)) {
+- /* enqueue the packet in delayQ */
+- drvr->fws->fifo_delay_map |= 1 << fifo;
++ skcb->mac = brcmf_fws_macdesc_find(fws, ifp, eh->h_dest);
++ brcmf_dbg(DATA, "%s mac %pM multi %d fifo %d\n", skcb->mac->name,
++ eh->h_dest, multicast, fifo);
++ if (!brcmf_fws_assign_htod(fws, skb, fifo)) {
+ brcmf_fws_enq(fws, BRCMF_FWS_SKBSTATE_DELAYED, fifo, skb);
++ brcmf_fws_schedule_deq(fws);
+ } else {
+- if (brcmf_fws_commit_skb(fws, fifo, skb))
+- if (!multicast)
+- brcmf_skb_pick_up_credit(fws, fifo, skb);
++ brcmf_err("drop skb: no hanger slot\n");
++ if (pae) {
++ atomic_dec(&ifp->pend_8021x_cnt);
++ if (waitqueue_active(&ifp->pend_8021x_wait))
++ wake_up(&ifp->pend_8021x_wait);
++ }
++ brcmu_pkt_buf_free_skb(skb);
+ }
+- brcmf_fws_unlock(drvr, flags);
++ brcmf_fws_unlock(fws);
+ return 0;
+ }
+
+@@ -1862,7 +1918,7 @@
+ if (!entry)
+ return;
+
+- brcmf_fws_init_mac_descriptor(entry, ifp->mac_addr, ifp->ifidx);
++ brcmf_fws_macdesc_init(entry, ifp->mac_addr, ifp->ifidx);
+ }
+
+ void brcmf_fws_add_interface(struct brcmf_if *ifp)
+@@ -1870,87 +1926,104 @@
+ struct brcmf_fws_info *fws = ifp->drvr->fws;
+ struct brcmf_fws_mac_descriptor *entry;
+
+- brcmf_dbg(TRACE, "enter: idx=%d, mac=%pM\n",
+- ifp->bssidx, ifp->mac_addr);
+- if (!ifp->ndev || !ifp->drvr->fw_signals)
++ if (!ifp->ndev)
+ return;
+
+ entry = &fws->desc.iface[ifp->ifidx];
+ ifp->fws_desc = entry;
+- brcmf_fws_init_mac_descriptor(entry, ifp->mac_addr, ifp->ifidx);
++ brcmf_fws_macdesc_init(entry, ifp->mac_addr, ifp->ifidx);
++ brcmf_fws_macdesc_set_name(fws, entry);
+ brcmu_pktq_init(&entry->psq, BRCMF_FWS_PSQ_PREC_COUNT,
+ BRCMF_FWS_PSQ_LEN);
++ brcmf_dbg(TRACE, "added %s\n", entry->name);
+ }
+
+ void brcmf_fws_del_interface(struct brcmf_if *ifp)
+ {
+ struct brcmf_fws_mac_descriptor *entry = ifp->fws_desc;
+- ulong flags;
+
+- brcmf_dbg(TRACE, "enter: idx=%d\n", ifp->bssidx);
+ if (!entry)
+ return;
+
+- brcmf_fws_lock(ifp->drvr, flags);
++ brcmf_fws_lock(ifp->drvr->fws);
+ ifp->fws_desc = NULL;
+- brcmf_fws_clear_mac_descriptor(entry);
++ brcmf_dbg(TRACE, "deleting %s\n", entry->name);
++ brcmf_fws_macdesc_deinit(entry);
+ brcmf_fws_cleanup(ifp->drvr->fws, ifp->ifidx);
+- brcmf_fws_unlock(ifp->drvr, flags);
++ brcmf_fws_unlock(ifp->drvr->fws);
+ }
+
+ static void brcmf_fws_dequeue_worker(struct work_struct *worker)
+ {
+ struct brcmf_fws_info *fws;
++ struct brcmf_pub *drvr;
+ struct sk_buff *skb;
+- ulong flags;
+ int fifo;
+- int credit;
++ u32 hslot;
++ u32 ifidx;
++ int ret;
+
+ fws = container_of(worker, struct brcmf_fws_info, fws_dequeue_work);
++ drvr = fws->drvr;
+
+- brcmf_dbg(TRACE, "enter: fws=%p\n", fws);
+- brcmf_fws_lock(fws->drvr, flags);
+- for (fifo = NL80211_NUM_ACS; fifo >= 0; fifo--) {
+- brcmf_dbg(TRACE, "fifo %d credit %d\n", fifo,
+- fws->fifo_credit[fifo]);
+- for (credit = 0; credit < fws->fifo_credit[fifo]; /* nop */) {
++ brcmf_fws_lock(fws);
++ for (fifo = BRCMF_FWS_FIFO_BCMC; fifo >= 0 && !fws->bus_flow_blocked;
++ fifo--) {
++ if (!brcmf_fws_fc_active(fws)) {
++ while ((skb = brcmf_fws_deq(fws, fifo)) != NULL) {
++ hslot = brcmf_skb_htod_tag_get_field(skb,
++ HSLOT);
++ brcmf_fws_hanger_poppkt(&fws->hanger, hslot,
++ &skb, true);
++ ifidx = brcmf_skb_if_flags_get_field(skb,
++ INDEX);
++ /* Use proto layer to send data frame */
++ brcmf_fws_unlock(fws);
++ ret = brcmf_proto_txdata(drvr, ifidx, 0, skb);
++ brcmf_fws_lock(fws);
++ if (ret < 0)
++ brcmf_txfinalize(drvr, skb, false);
++ if (fws->bus_flow_blocked)
++ break;
++ }
++ continue;
++ }
++ while ((fws->fifo_credit[fifo]) || ((!fws->bcmc_credit_check) &&
++ (fifo == BRCMF_FWS_FIFO_BCMC))) {
+ skb = brcmf_fws_deq(fws, fifo);
+- if (!skb || brcmf_fws_commit_skb(fws, fifo, skb))
++ if (!skb)
++ break;
++ fws->fifo_credit[fifo]--;
++ if (brcmf_fws_commit_skb(fws, fifo, skb))
++ break;
++ if (fws->bus_flow_blocked)
+ break;
+- if (brcmf_skbcb(skb)->if_flags &
+- BRCMF_SKB_IF_FLAGS_CREDITCHECK_MASK)
+- credit++;
+ }
+ if ((fifo == BRCMF_FWS_FIFO_AC_BE) &&
+- (credit == fws->fifo_credit[fifo])) {
+- fws->fifo_credit[fifo] -= credit;
++ (fws->fifo_credit[fifo] == 0) &&
++ (!fws->bus_flow_blocked)) {
+ while (brcmf_fws_borrow_credit(fws) == 0) {
+ skb = brcmf_fws_deq(fws, fifo);
+ if (!skb) {
+ brcmf_fws_return_credits(fws, fifo, 1);
+ break;
+ }
+- if (brcmf_fws_commit_skb(fws, fifo, skb)) {
+- brcmf_fws_return_credits(fws, fifo, 1);
++ if (brcmf_fws_commit_skb(fws, fifo, skb))
++ break;
++ if (fws->bus_flow_blocked)
+ break;
+- }
+ }
+- } else {
+- fws->fifo_credit[fifo] -= credit;
+ }
+ }
+- brcmf_fws_unlock(fws->drvr, flags);
++ brcmf_fws_unlock(fws);
+ }
+
+ int brcmf_fws_init(struct brcmf_pub *drvr)
+ {
++ struct brcmf_fws_info *fws;
+ u32 tlv = BRCMF_FWS_FLAGS_RSSI_SIGNALS;
+ int rc;
+-
+- if (!drvr->fw_signals)
+- return 0;
+-
+- spin_lock_init(&drvr->fws_spinlock);
++ u32 mode;
+
+ drvr->fws = kzalloc(sizeof(*(drvr->fws)), GFP_KERNEL);
+ if (!drvr->fws) {
+@@ -1958,23 +2031,28 @@
+ goto fail;
+ }
+
++ fws = drvr->fws;
++
++ spin_lock_init(&fws->spinlock);
++
+ /* set linkage back */
+- drvr->fws->drvr = drvr;
+- drvr->fws->fcmode = fcmode;
++ fws->drvr = drvr;
++ fws->fcmode = fcmode;
+
+- drvr->fws->fws_wq = create_singlethread_workqueue("brcmf_fws_wq");
+- if (drvr->fws->fws_wq == NULL) {
++ fws->fws_wq = create_singlethread_workqueue("brcmf_fws_wq");
++ if (fws->fws_wq == NULL) {
+ brcmf_err("workqueue creation failed\n");
+ rc = -EBADF;
+ goto fail;
+ }
+- INIT_WORK(&drvr->fws->fws_dequeue_work, brcmf_fws_dequeue_worker);
++ INIT_WORK(&fws->fws_dequeue_work, brcmf_fws_dequeue_worker);
+
+ /* enable firmware signalling if fcmode active */
+- if (drvr->fws->fcmode != BRCMF_FWS_FCMODE_NONE)
++ if (fws->fcmode != BRCMF_FWS_FCMODE_NONE)
+ tlv |= BRCMF_FWS_FLAGS_XONXOFF_SIGNALS |
+ BRCMF_FWS_FLAGS_CREDIT_STATUS_SIGNALS |
+- BRCMF_FWS_FLAGS_HOST_PROPTXSTATUS_ACTIVE;
++ BRCMF_FWS_FLAGS_HOST_PROPTXSTATUS_ACTIVE |
++ BRCMF_FWS_FLAGS_HOST_RXREORDER_ACTIVE;
+
+ rc = brcmf_fweh_register(drvr, BRCMF_E_FIFO_CREDIT_MAP,
+ brcmf_fws_notify_credit_map);
+@@ -1982,31 +2060,53 @@
+ brcmf_err("register credit map handler failed\n");
+ goto fail;
+ }
++ rc = brcmf_fweh_register(drvr, BRCMF_E_BCMC_CREDIT_SUPPORT,
++ brcmf_fws_notify_bcmc_credit_support);
++ if (rc < 0) {
++ brcmf_err("register bcmc credit handler failed\n");
++ brcmf_fweh_unregister(drvr, BRCMF_E_FIFO_CREDIT_MAP);
++ goto fail;
++ }
+
+- /* setting the iovar may fail if feature is unsupported
++ /* Setting the iovar may fail if feature is unsupported
+ * so leave the rc as is so driver initialization can
+- * continue.
++ * continue. Set mode back to none indicating not enabled.
+ */
++ fws->fw_signals = true;
+ if (brcmf_fil_iovar_int_set(drvr->iflist[0], "tlv", tlv)) {
+ brcmf_err("failed to set bdcv2 tlv signaling\n");
+- goto fail_event;
++ fws->fcmode = BRCMF_FWS_FCMODE_NONE;
++ fws->fw_signals = false;
+ }
+
+- brcmf_fws_hanger_init(&drvr->fws->hanger);
+- brcmf_fws_init_mac_descriptor(&drvr->fws->desc.other, NULL, 0);
+- brcmu_pktq_init(&drvr->fws->desc.other.psq, BRCMF_FWS_PSQ_PREC_COUNT,
++ if (brcmf_fil_iovar_int_set(drvr->iflist[0], "ampdu_hostreorder", 1))
++ brcmf_dbg(INFO, "enabling AMPDU host-reorder failed\n");
++
++ /* Enable seq number reuse, if supported */
++ if (brcmf_fil_iovar_int_get(drvr->iflist[0], "wlfc_mode", &mode) == 0) {
++ if (BRCMF_FWS_MODE_GET_REUSESEQ(mode)) {
++ mode = 0;
++ BRCMF_FWS_MODE_SET_REUSESEQ(mode, 1);
++ if (brcmf_fil_iovar_int_set(drvr->iflist[0],
++ "wlfc_mode", mode) == 0) {
++ BRCMF_FWS_MODE_SET_REUSESEQ(fws->mode, 1);
++ }
++ }
++ }
++
++ brcmf_fws_hanger_init(&fws->hanger);
++ brcmf_fws_macdesc_init(&fws->desc.other, NULL, 0);
++ brcmf_fws_macdesc_set_name(fws, &fws->desc.other);
++ brcmu_pktq_init(&fws->desc.other.psq, BRCMF_FWS_PSQ_PREC_COUNT,
+ BRCMF_FWS_PSQ_LEN);
+
+ /* create debugfs file for statistics */
+- brcmf_debugfs_create_fws_stats(drvr, &drvr->fws->stats);
++ brcmf_debugfs_create_fws_stats(drvr, &fws->stats);
+
+- /* TODO: remove upon feature delivery */
+- brcmf_err("%s bdcv2 tlv signaling [%x]\n",
+- drvr->fw_signals ? "enabled" : "disabled", tlv);
++ brcmf_dbg(INFO, "%s bdcv2 tlv signaling [%x]\n",
++ fws->fw_signals ? "enabled" : "disabled", tlv);
+ return 0;
+
+-fail_event:
+- brcmf_fweh_unregister(drvr, BRCMF_E_FIFO_CREDIT_MAP);
+ fail:
+ brcmf_fws_deinit(drvr);
+ return rc;
+@@ -2015,24 +2115,18 @@
+ void brcmf_fws_deinit(struct brcmf_pub *drvr)
+ {
+ struct brcmf_fws_info *fws = drvr->fws;
+- ulong flags;
+
+ if (!fws)
+ return;
+
+- /* disable firmware signalling entirely
+- * to avoid using the workqueue.
+- */
+- drvr->fw_signals = false;
+-
+ if (drvr->fws->fws_wq)
+ destroy_workqueue(drvr->fws->fws_wq);
+
+ /* cleanup */
+- brcmf_fws_lock(drvr, flags);
++ brcmf_fws_lock(fws);
+ brcmf_fws_cleanup(fws, -1);
+ drvr->fws = NULL;
+- brcmf_fws_unlock(drvr, flags);
++ brcmf_fws_unlock(fws);
+
+ /* free top structure */
+ kfree(fws);
+@@ -2040,28 +2134,33 @@
+
+ bool brcmf_fws_fc_active(struct brcmf_fws_info *fws)
+ {
+- if (!fws)
++ if (!fws->creditmap_received)
+ return false;
+
+- brcmf_dbg(TRACE, "enter: mode=%d\n", fws->fcmode);
+ return fws->fcmode != BRCMF_FWS_FCMODE_NONE;
+ }
+
+ void brcmf_fws_bustxfail(struct brcmf_fws_info *fws, struct sk_buff *skb)
+ {
+- ulong flags;
++ u32 hslot;
+
+- brcmf_fws_lock(fws->drvr, flags);
+- brcmf_fws_txstatus_process(fws, BRCMF_FWS_TXSTATUS_FW_TOSSED,
+- brcmf_skb_htod_tag_get_field(skb, HSLOT), 0);
+- /* the packet never reached firmware so reclaim credit */
+- if (fws->fcmode == BRCMF_FWS_FCMODE_EXPLICIT_CREDIT &&
+- brcmf_skbcb(skb)->if_flags & BRCMF_SKB_IF_FLAGS_CREDITCHECK_MASK) {
+- brcmf_fws_return_credits(fws,
+- brcmf_skb_htod_tag_get_field(skb,
+- FIFO),
+- 1);
+- brcmf_fws_schedule_deq(fws);
++ if (brcmf_skbcb(skb)->state == BRCMF_FWS_SKBSTATE_TIM) {
++ brcmu_pkt_buf_free_skb(skb);
++ return;
+ }
+- brcmf_fws_unlock(fws->drvr, flags);
++ brcmf_fws_lock(fws);
++ hslot = brcmf_skb_htod_tag_get_field(skb, HSLOT);
++ brcmf_fws_txs_process(fws, BRCMF_FWS_TXSTATUS_HOST_TOSSED, hslot, 0, 0);
++ brcmf_fws_unlock(fws);
++}
++
++void brcmf_fws_bus_blocked(struct brcmf_pub *drvr, bool flow_blocked)
++{
++ struct brcmf_fws_info *fws = drvr->fws;
++
++ fws->bus_flow_blocked = flow_blocked;
++ if (!flow_blocked)
++ brcmf_fws_schedule_deq(fws);
++ else
++ fws->stats.bus_flow_block++;
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.h 2014-05-15 20:34:00.578032457 +0200
+@@ -29,5 +29,6 @@
+ void brcmf_fws_add_interface(struct brcmf_if *ifp);
+ void brcmf_fws_del_interface(struct brcmf_if *ifp);
+ void brcmf_fws_bustxfail(struct brcmf_fws_info *fws, struct sk_buff *skb);
++void brcmf_fws_bus_blocked(struct brcmf_pub *drvr, bool flow_blocked);
+
+ #endif /* FWSIGNAL_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/Makefile linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/Makefile
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/Makefile 2014-05-15 20:34:00.550032255 +0200
+@@ -28,14 +28,15 @@
+ fweh.o \
+ fwsignal.o \
+ p2p.o \
+- dhd_cdc.o \
++ proto.o \
++ bcdc.o \
+ dhd_common.o \
+ dhd_linux.o \
++ nvram.o \
+ btcoex.o
+ brcmfmac-$(CONFIG_BRCMFMAC_SDIO) += \
+ dhd_sdio.o \
+ bcmsdh.o \
+- bcmsdh_sdmmc.o \
+ sdio_chip.o
+ brcmfmac-$(CONFIG_BRCMFMAC_USB) += \
+ usb.o
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/nvram.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/nvram.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/nvram.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/nvram.c 2014-05-15 20:34:00.578032457 +0200
+@@ -0,0 +1,94 @@
++/*
++ * Copyright (c) 2013 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/firmware.h>
++
++#include "nvram.h"
++
++/* brcmf_nvram_strip :Takes a buffer of "<var>=<value>\n" lines read from a file
++ * and ending in a NUL. Removes carriage returns, empty lines, comment lines,
++ * and converts newlines to NULs. Shortens buffer as needed and pads with NULs.
++ * End of buffer is completed with token identifying length of buffer.
++ */
++void *brcmf_nvram_strip(const struct firmware *nv, u32 *new_length)
++{
++ u8 *nvram;
++ u32 i;
++ u32 len;
++ u32 column;
++ u8 val;
++ bool comment;
++ u32 token;
++ __le32 token_le;
++
++ /* Alloc for extra 0 byte + roundup by 4 + length field */
++ nvram = kmalloc(nv->size + 1 + 3 + sizeof(token_le), GFP_KERNEL);
++ if (!nvram)
++ return NULL;
++
++ len = 0;
++ column = 0;
++ comment = false;
++ for (i = 0; i < nv->size; i++) {
++ val = nv->data[i];
++ if (val == 0)
++ break;
++ if (val == '\r')
++ continue;
++ if (comment && (val != '\n'))
++ continue;
++ comment = false;
++ if (val == '#') {
++ comment = true;
++ continue;
++ }
++ if (val == '\n') {
++ if (column == 0)
++ continue;
++ nvram[len] = 0;
++ len++;
++ column = 0;
++ continue;
++ }
++ nvram[len] = val;
++ len++;
++ column++;
++ }
++ column = len;
++ *new_length = roundup(len + 1, 4);
++ while (column != *new_length) {
++ nvram[column] = 0;
++ column++;
++ }
++
++ token = *new_length / 4;
++ token = (~token << 16) | (token & 0x0000FFFF);
++ token_le = cpu_to_le32(token);
++
++ memcpy(&nvram[*new_length], &token_le, sizeof(token_le));
++ *new_length += sizeof(token_le);
++
++ return nvram;
++}
++
++void brcmf_nvram_free(void *nvram)
++{
++ kfree(nvram);
++}
++
++
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/nvram.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/nvram.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/nvram.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/nvram.h 2014-05-15 20:34:00.578032457 +0200
+@@ -0,0 +1,24 @@
++/*
++ * Copyright (c) 2013 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_NVRAM_H
++#define BRCMFMAC_NVRAM_H
++
++
++void *brcmf_nvram_strip(const struct firmware *nv, u32 *new_length);
++void brcmf_nvram_free(void *nvram);
++
++
++#endif /* BRCMFMAC_NVRAM_H */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/p2p.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/p2p.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/p2p.c 2014-05-15 20:34:00.578032457 +0200
+@@ -823,6 +823,7 @@
+ }
+ err = brcmf_p2p_escan(p2p, num_nodfs, chanspecs, search_state,
+ action, P2PAPI_BSSCFG_DEVICE);
++ kfree(chanspecs);
+ }
+ exit:
+ if (err)
+@@ -1242,7 +1243,7 @@
+ IEEE80211_P2P_ATTR_DEVICE_ID,
+ p2p_dev_addr, sizeof(p2p_dev_addr));
+ if ((err >= 0) &&
+- (!memcmp(p2p_dev_addr, afx_hdl->tx_dst_addr, ETH_ALEN))) {
++ (ether_addr_equal(p2p_dev_addr, afx_hdl->tx_dst_addr))) {
+ if (!bi->ctl_ch) {
+ ch.chspec = le16_to_cpu(bi->chanspec);
+ cfg->d11inf.decchspec(&ch);
+@@ -1379,8 +1380,7 @@
+ (brcmf_p2p_gon_req_collision(p2p, (u8 *)e->addr))) {
+ if (test_bit(BRCMF_P2P_STATUS_FINDING_COMMON_CHANNEL,
+ &p2p->status) &&
+- (memcmp(afx_hdl->tx_dst_addr, e->addr,
+- ETH_ALEN) == 0)) {
++ (ether_addr_equal(afx_hdl->tx_dst_addr, e->addr))) {
+ afx_hdl->peer_chan = ch.chnum;
+ brcmf_dbg(INFO, "GON request: Peer found, channel=%d\n",
+ afx_hdl->peer_chan);
+@@ -1864,7 +1864,7 @@
+ cfg->d11inf.decchspec(&ch);
+
+ if (test_bit(BRCMF_P2P_STATUS_FINDING_COMMON_CHANNEL, &p2p->status) &&
+- (memcmp(afx_hdl->tx_dst_addr, e->addr, ETH_ALEN) == 0)) {
++ (ether_addr_equal(afx_hdl->tx_dst_addr, e->addr))) {
+ afx_hdl->peer_chan = ch.chnum;
+ brcmf_dbg(INFO, "PROBE REQUEST: Peer found, channel=%d\n",
+ afx_hdl->peer_chan);
+@@ -1955,21 +1955,21 @@
+ err = brcmf_fil_iovar_int_set(pri_ifp, "p2p_disc", 1);
+ if (err < 0) {
+ brcmf_err("set p2p_disc error\n");
+- brcmf_free_vif(cfg, p2p_vif);
++ brcmf_free_vif(p2p_vif);
+ goto exit;
+ }
+ /* obtain bsscfg index for P2P discovery */
+ err = brcmf_fil_iovar_int_get(pri_ifp, "p2p_dev", &bssidx);
+ if (err < 0) {
+ brcmf_err("retrieving discover bsscfg index failed\n");
+- brcmf_free_vif(cfg, p2p_vif);
++ brcmf_free_vif(p2p_vif);
+ goto exit;
+ }
+ /* Verify that firmware uses same bssidx as driver !! */
+ if (p2p_ifp->bssidx != bssidx) {
+ brcmf_err("Incorrect bssidx=%d, compared to p2p_ifp->bssidx=%d\n",
+ bssidx, p2p_ifp->bssidx);
+- brcmf_free_vif(cfg, p2p_vif);
++ brcmf_free_vif(p2p_vif);
+ goto exit;
+ }
+
+@@ -1997,7 +1997,7 @@
+ brcmf_p2p_cancel_remain_on_channel(vif->ifp);
+ brcmf_p2p_deinit_discovery(p2p);
+ /* remove discovery interface */
+- brcmf_free_vif(p2p->cfg, vif);
++ brcmf_free_vif(vif);
+ p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
+ }
+ /* just set it all to zero */
+@@ -2222,7 +2222,7 @@
+ return &p2p_vif->wdev;
+
+ fail:
+- brcmf_free_vif(p2p->cfg, p2p_vif);
++ brcmf_free_vif(p2p_vif);
+ return ERR_PTR(err);
+ }
+
+@@ -2231,31 +2231,12 @@
+ *
+ * @vif: virtual interface object to delete.
+ */
+-static void brcmf_p2p_delete_p2pdev(struct brcmf_cfg80211_info *cfg,
++static void brcmf_p2p_delete_p2pdev(struct brcmf_p2p_info *p2p,
+ struct brcmf_cfg80211_vif *vif)
+ {
+ cfg80211_unregister_wdev(&vif->wdev);
+- cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
+- brcmf_free_vif(cfg, vif);
+-}
+-
+-/**
+- * brcmf_p2p_free_p2p_if() - free up net device related data.
+- *
+- * @ndev: net device that needs to be freed.
+- */
+-static void brcmf_p2p_free_p2p_if(struct net_device *ndev)
+-{
+- struct brcmf_cfg80211_info *cfg;
+- struct brcmf_cfg80211_vif *vif;
+- struct brcmf_if *ifp;
+-
+- ifp = netdev_priv(ndev);
+- cfg = ifp->drvr->config;
+- vif = ifp->vif;
+-
+- brcmf_free_vif(cfg, vif);
+- free_netdev(ifp->ndev);
++ p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
++ brcmf_free_vif(vif);
+ }
+
+ /**
+@@ -2335,8 +2316,6 @@
+ brcmf_err("Registering netdevice failed\n");
+ goto fail;
+ }
+- /* override destructor */
+- ifp->ndev->destructor = brcmf_p2p_free_p2p_if;
+
+ cfg->p2p.bss_idx[P2PAPI_BSSCFG_CONNECTION].vif = vif;
+ /* Disable firmware roaming for P2P interface */
+@@ -2349,7 +2328,7 @@
+ return &ifp->vif->wdev;
+
+ fail:
+- brcmf_free_vif(cfg, vif);
++ brcmf_free_vif(vif);
+ return ERR_PTR(err);
+ }
+
+@@ -2358,8 +2337,6 @@
+ *
+ * @wiphy: wiphy device of interface.
+ * @wdev: wireless device of interface.
+- *
+- * TODO: not yet supported.
+ */
+ int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
+ {
+@@ -2385,7 +2362,7 @@
+ break;
+
+ case NL80211_IFTYPE_P2P_DEVICE:
+- brcmf_p2p_delete_p2pdev(cfg, vif);
++ brcmf_p2p_delete_p2pdev(p2p, vif);
+ return 0;
+ default:
+ return -ENOTSUPP;
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/proto.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/proto.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/proto.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/proto.c 2014-05-15 20:34:00.578032457 +0200
+@@ -0,0 +1,62 @@
++/*
++ * Copyright (c) 2013 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++ #include <linux/types.h>
++#include <linux/slab.h>
++#include <linux/netdevice.h>
++
++#include <brcmu_wifi.h>
++#include "dhd.h"
++#include "dhd_dbg.h"
++#include "proto.h"
++#include "bcdc.h"
++
++
++int brcmf_proto_attach(struct brcmf_pub *drvr)
++{
++ struct brcmf_proto *proto;
++
++ proto = kzalloc(sizeof(*proto), GFP_ATOMIC);
++ if (!proto)
++ goto fail;
++
++ drvr->proto = proto;
++ /* BCDC protocol is only protocol supported for the moment */
++ if (brcmf_proto_bcdc_attach(drvr))
++ goto fail;
++
++ if ((proto->txdata == NULL) || (proto->hdrpull == NULL) ||
++ (proto->query_dcmd == NULL) || (proto->set_dcmd == NULL)) {
++ brcmf_err("Not all proto handlers have been installed\n");
++ goto fail;
++ }
++ return 0;
++
++fail:
++ kfree(proto);
++ drvr->proto = NULL;
++ return -ENOMEM;
++}
++
++void brcmf_proto_detach(struct brcmf_pub *drvr)
++{
++ if (drvr->proto) {
++ brcmf_proto_bcdc_detach(drvr);
++ kfree(drvr->proto);
++ drvr->proto = NULL;
++ }
++}
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/proto.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/proto.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/proto.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/proto.h 2014-05-15 20:34:00.578032457 +0200
+@@ -0,0 +1,57 @@
++/*
++ * Copyright (c) 2013 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_PROTO_H
++#define BRCMFMAC_PROTO_H
++
++struct brcmf_proto {
++ int (*hdrpull)(struct brcmf_pub *drvr, bool do_fws, u8 *ifidx,
++ struct sk_buff *skb);
++ int (*query_dcmd)(struct brcmf_pub *drvr, int ifidx, uint cmd,
++ void *buf, uint len);
++ int (*set_dcmd)(struct brcmf_pub *drvr, int ifidx, uint cmd, void *buf,
++ uint len);
++ int (*txdata)(struct brcmf_pub *drvr, int ifidx, u8 offset,
++ struct sk_buff *skb);
++ void *pd;
++};
++
++
++int brcmf_proto_attach(struct brcmf_pub *drvr);
++void brcmf_proto_detach(struct brcmf_pub *drvr);
++
++static inline int brcmf_proto_hdrpull(struct brcmf_pub *drvr, bool do_fws,
++ u8 *ifidx, struct sk_buff *skb)
++{
++ return drvr->proto->hdrpull(drvr, do_fws, ifidx, skb);
++}
++static inline int brcmf_proto_query_dcmd(struct brcmf_pub *drvr, int ifidx,
++ uint cmd, void *buf, uint len)
++{
++ return drvr->proto->query_dcmd(drvr, ifidx, cmd, buf, len);
++}
++static inline int brcmf_proto_set_dcmd(struct brcmf_pub *drvr, int ifidx,
++ uint cmd, void *buf, uint len)
++{
++ return drvr->proto->set_dcmd(drvr, ifidx, cmd, buf, len);
++}
++static inline int brcmf_proto_txdata(struct brcmf_pub *drvr, int ifidx,
++ u8 offset, struct sk_buff *skb)
++{
++ return drvr->proto->txdata(drvr, ifidx, offset, skb);
++}
++
++
++#endif /* BRCMFMAC_PROTO_H */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c 2014-05-15 20:34:00.578032457 +0200
+@@ -18,6 +18,8 @@
+ #include <linux/types.h>
+ #include <linux/netdevice.h>
+ #include <linux/mmc/card.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/sdio_ids.h>
+ #include <linux/ssb/ssb_regs.h>
+ #include <linux/bcma/bcma.h>
+
+@@ -49,6 +51,9 @@
+ #define BCM43143_CORE_ARM_BASE 0x18003000
+ #define BCM43143_RAMSIZE 0x70000
+
++/* All D11 cores, ID 0x812 */
++#define BCM43xx_CORE_D11_BASE 0x18001000
++
+ #define SBCOREREV(sbidh) \
+ ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
+ ((sbidh) & SSB_IDHIGH_RCLO))
+@@ -64,6 +69,10 @@
+ /* ARM CR4 core specific control flag bits */
+ #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
+
++/* D11 core specific control flag bits */
++#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
++#define D11_BCMA_IOCTL_PHYRESET 0x0008
++
+ #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
+ /* SDIO Pad drive strength to select value mappings */
+ struct sdiod_drive_str {
+@@ -82,6 +91,24 @@
+ {0, 0x1}
+ };
+
++/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
++static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
++ {6, 0x7},
++ {5, 0x6},
++ {4, 0x5},
++ {3, 0x4},
++ {2, 0x2},
++ {1, 0x1},
++ {0, 0x0}
++};
++
++/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
++static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
++ {3, 0x3},
++ {2, 0x2},
++ {1, 0x1},
++ {0, 0x0} };
++
+ /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
+ static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
+ {16, 0x7},
+@@ -91,7 +118,7 @@
+ };
+
+ u8
+-brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid)
++brcmf_sdio_chip_getinfidx(struct brcmf_chip *ci, u16 coreid)
+ {
+ u8 idx;
+
+@@ -104,22 +131,22 @@
+
+ static u32
+ brcmf_sdio_sb_corerev(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid)
++ struct brcmf_chip *ci, u16 coreid)
+ {
+ u32 regdata;
+ u8 idx;
+
+ idx = brcmf_sdio_chip_getinfidx(ci, coreid);
+
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbidhigh),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbidhigh),
++ NULL);
+ return SBCOREREV(regdata);
+ }
+
+ static u32
+ brcmf_sdio_ai_corerev(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid)
++ struct brcmf_chip *ci, u16 coreid)
+ {
+ u8 idx;
+
+@@ -130,16 +157,18 @@
+
+ static bool
+ brcmf_sdio_sb_iscoreup(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid)
++ struct brcmf_chip *ci, u16 coreid)
+ {
+ u32 regdata;
+ u8 idx;
+
+ idx = brcmf_sdio_chip_getinfidx(ci, coreid);
++ if (idx == BRCMF_MAX_CORENUM)
++ return false;
+
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
++ NULL);
+ regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
+ SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
+ return (SSB_TMSLOW_CLOCK == regdata);
+@@ -147,21 +176,23 @@
+
+ static bool
+ brcmf_sdio_ai_iscoreup(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid)
++ struct brcmf_chip *ci, u16 coreid)
+ {
+ u32 regdata;
+ u8 idx;
+ bool ret;
+
+ idx = brcmf_sdio_chip_getinfidx(ci, coreid);
++ if (idx == BRCMF_MAX_CORENUM)
++ return false;
+
+- regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
++ NULL);
+ ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
+
+- regdata = brcmf_sdio_regrl(sdiodev,
+- ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
++ NULL);
+ ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
+
+ return ret;
+@@ -169,7 +200,8 @@
+
+ static void
+ brcmf_sdio_sb_coredisable(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid, u32 core_bits)
++ struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits,
++ u32 in_resetbits)
+ {
+ u32 regdata, base;
+ u8 idx;
+@@ -177,223 +209,223 @@
+ idx = brcmf_sdio_chip_getinfidx(ci, coreid);
+ base = ci->c_inf[idx].base;
+
+- regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, CORE_SB(base, sbtmstatelow), NULL);
+ if (regdata & SSB_TMSLOW_RESET)
+ return;
+
+- regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow), NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, CORE_SB(base, sbtmstatelow), NULL);
+ if ((regdata & SSB_TMSLOW_CLOCK) != 0) {
+ /*
+ * set target reject and spin until busy is clear
+ * (preserve core-specific bits)
+ */
+- regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow),
+- NULL);
+- brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow),
+- regdata | SSB_TMSLOW_REJECT, NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbtmstatelow), NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_SB(base, sbtmstatelow),
++ regdata | SSB_TMSLOW_REJECT, NULL);
+
+- regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbtmstatelow), NULL);
+ udelay(1);
+- SPINWAIT((brcmf_sdio_regrl(sdiodev,
+- CORE_SB(base, sbtmstatehigh),
+- NULL) &
+- SSB_TMSHIGH_BUSY), 100000);
+-
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(base, sbtmstatehigh),
+- NULL);
++ SPINWAIT((brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbtmstatehigh),
++ NULL) &
++ SSB_TMSHIGH_BUSY), 100000);
++
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbtmstatehigh),
++ NULL);
+ if (regdata & SSB_TMSHIGH_BUSY)
+ brcmf_err("core state still busy\n");
+
+- regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbidlow),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, CORE_SB(base, sbidlow),
++ NULL);
+ if (regdata & SSB_IDLOW_INITIATOR) {
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(base, sbimstate),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbimstate),
++ NULL);
+ regdata |= SSB_IMSTATE_REJECT;
+- brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbimstate),
+- regdata, NULL);
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(base, sbimstate),
+- NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_SB(base, sbimstate),
++ regdata, NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbimstate),
++ NULL);
+ udelay(1);
+- SPINWAIT((brcmf_sdio_regrl(sdiodev,
+- CORE_SB(base, sbimstate),
+- NULL) &
+- SSB_IMSTATE_BUSY), 100000);
++ SPINWAIT((brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbimstate),
++ NULL) &
++ SSB_IMSTATE_BUSY), 100000);
+ }
+
+ /* set reset and reject while enabling the clocks */
+ regdata = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
+ SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
+- brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow),
+- regdata, NULL);
+- regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbtmstatelow),
+- NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_SB(base, sbtmstatelow),
++ regdata, NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbtmstatelow), NULL);
+ udelay(10);
+
+ /* clear the initiator reject bit */
+- regdata = brcmf_sdio_regrl(sdiodev, CORE_SB(base, sbidlow),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, CORE_SB(base, sbidlow),
++ NULL);
+ if (regdata & SSB_IDLOW_INITIATOR) {
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(base, sbimstate),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(base, sbimstate),
++ NULL);
+ regdata &= ~SSB_IMSTATE_REJECT;
+- brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbimstate),
+- regdata, NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_SB(base, sbimstate),
++ regdata, NULL);
+ }
+ }
+
+ /* leave reset and reject asserted */
+- brcmf_sdio_regwl(sdiodev, CORE_SB(base, sbtmstatelow),
+- (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET), NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_SB(base, sbtmstatelow),
++ (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET), NULL);
+ udelay(1);
+ }
+
+ static void
+ brcmf_sdio_ai_coredisable(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid, u32 core_bits)
++ struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits,
++ u32 in_resetbits)
+ {
+ u8 idx;
+ u32 regdata;
++ u32 wrapbase;
+
+ idx = brcmf_sdio_chip_getinfidx(ci, coreid);
++ if (idx == BRCMF_MAX_CORENUM)
++ return;
++
++ wrapbase = ci->c_inf[idx].wrapbase;
+
+ /* if core is already in reset, just return */
+- regdata = brcmf_sdio_regrl(sdiodev,
+- ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_RESET_CTL, NULL);
+ if ((regdata & BCMA_RESET_CTL_RESET) != 0)
+ return;
+
+- /* ensure no pending backplane operation
+- * 300uc should be sufficient for backplane ops to be finish
+- * extra 10ms is taken into account for firmware load stage
+- * after 10300us carry on disabling the core anyway
+- */
+- SPINWAIT(brcmf_sdio_regrl(sdiodev,
+- ci->c_inf[idx].wrapbase+BCMA_RESET_ST,
+- NULL), 10300);
+- regdata = brcmf_sdio_regrl(sdiodev,
+- ci->c_inf[idx].wrapbase+BCMA_RESET_ST,
+- NULL);
+- if (regdata)
+- brcmf_err("disabling core 0x%x with reset status %x\n",
+- coreid, regdata);
+-
+- brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
+- BCMA_RESET_CTL_RESET, NULL);
+- udelay(1);
+-
+- brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
+- core_bits, NULL);
+- regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
+- NULL);
++ /* configure reset */
++ brcmf_sdiod_regwl(sdiodev, wrapbase + BCMA_IOCTL, pre_resetbits |
++ BCMA_IOCTL_FGC | BCMA_IOCTL_CLK, NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_IOCTL, NULL);
++
++ /* put in reset */
++ brcmf_sdiod_regwl(sdiodev, wrapbase + BCMA_RESET_CTL,
++ BCMA_RESET_CTL_RESET, NULL);
+ usleep_range(10, 20);
+
++ /* wait till reset is 1 */
++ SPINWAIT(brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_RESET_CTL, NULL) !=
++ BCMA_RESET_CTL_RESET, 300);
++
++ /* post reset configure */
++ brcmf_sdiod_regwl(sdiodev, wrapbase + BCMA_IOCTL, pre_resetbits |
++ BCMA_IOCTL_FGC | BCMA_IOCTL_CLK, NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_IOCTL, NULL);
+ }
+
+ static void
+ brcmf_sdio_sb_resetcore(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid, u32 core_bits)
++ struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits,
++ u32 in_resetbits, u32 post_resetbits)
+ {
+ u32 regdata;
+ u8 idx;
+
+ idx = brcmf_sdio_chip_getinfidx(ci, coreid);
++ if (idx == BRCMF_MAX_CORENUM)
++ return;
+
+ /*
+ * Must do the disable sequence first to work for
+ * arbitrary current core state.
+ */
+- brcmf_sdio_sb_coredisable(sdiodev, ci, coreid, 0);
++ brcmf_sdio_sb_coredisable(sdiodev, ci, coreid, pre_resetbits,
++ in_resetbits);
+
+ /*
+ * Now do the initialization sequence.
+ * set reset while enabling the clock and
+ * forcing them on throughout the core
+ */
+- brcmf_sdio_regwl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
+- SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET,
+- NULL);
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
+- NULL);
++ brcmf_sdiod_regwl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
++ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET,
++ NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
++ NULL);
+ udelay(1);
+
+ /* clear any serror */
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbtmstatehigh),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbtmstatehigh),
++ NULL);
+ if (regdata & SSB_TMSHIGH_SERR)
+- brcmf_sdio_regwl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbtmstatehigh),
+- 0, NULL);
+-
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbimstate),
+- NULL);
++ brcmf_sdiod_regwl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbtmstatehigh),
++ 0, NULL);
++
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbimstate),
++ NULL);
+ if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO))
+- brcmf_sdio_regwl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbimstate),
+- regdata & ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO),
+- NULL);
++ brcmf_sdiod_regwl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbimstate),
++ regdata & ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO),
++ NULL);
+
+ /* clear reset and allow it to propagate throughout the core */
+- brcmf_sdio_regwl(sdiodev, CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
+- SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK, NULL);
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
+- NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
++ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK, NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
++ NULL);
+ udelay(1);
+
+ /* leave clock enabled */
+- brcmf_sdio_regwl(sdiodev, CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
+- SSB_TMSLOW_CLOCK, NULL);
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
+- NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
++ SSB_TMSLOW_CLOCK, NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_SB(ci->c_inf[idx].base, sbtmstatelow),
++ NULL);
+ udelay(1);
+ }
+
+ static void
+ brcmf_sdio_ai_resetcore(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid, u32 core_bits)
++ struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits,
++ u32 in_resetbits, u32 post_resetbits)
+ {
+ u8 idx;
+ u32 regdata;
++ u32 wrapbase;
+
+ idx = brcmf_sdio_chip_getinfidx(ci, coreid);
++ if (idx == BRCMF_MAX_CORENUM)
++ return;
++
++ wrapbase = ci->c_inf[idx].wrapbase;
+
+ /* must disable first to work for arbitrary current core state */
+- brcmf_sdio_ai_coredisable(sdiodev, ci, coreid, core_bits);
++ brcmf_sdio_ai_coredisable(sdiodev, ci, coreid, pre_resetbits,
++ in_resetbits);
+
+- /* now do initialization sequence */
+- brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
+- core_bits | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK, NULL);
+- regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
+- NULL);
+- brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
+- 0, NULL);
+- regdata = brcmf_sdio_regrl(sdiodev,
+- ci->c_inf[idx].wrapbase+BCMA_RESET_CTL,
+- NULL);
+- udelay(1);
++ while (brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_RESET_CTL, NULL) &
++ BCMA_RESET_CTL_RESET) {
++ brcmf_sdiod_regwl(sdiodev, wrapbase + BCMA_RESET_CTL, 0, NULL);
++ usleep_range(40, 60);
++ }
+
+- brcmf_sdio_regwl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
+- core_bits | BCMA_IOCTL_CLK, NULL);
+- regdata = brcmf_sdio_regrl(sdiodev, ci->c_inf[idx].wrapbase+BCMA_IOCTL,
+- NULL);
+- udelay(1);
++ brcmf_sdiod_regwl(sdiodev, wrapbase + BCMA_IOCTL, post_resetbits |
++ BCMA_IOCTL_CLK, NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_IOCTL, NULL);
+ }
+
+ #ifdef DEBUG
+ /* safety check for chipinfo */
+-static int brcmf_sdio_chip_cichk(struct chip_info *ci)
++static int brcmf_sdio_chip_cichk(struct brcmf_chip *ci)
+ {
+ u8 core_idx;
+
+@@ -420,155 +452,213 @@
+ return 0;
+ }
+ #else /* DEBUG */
+-static inline int brcmf_sdio_chip_cichk(struct chip_info *ci)
++static inline int brcmf_sdio_chip_cichk(struct brcmf_chip *ci)
+ {
+ return 0;
+ }
+ #endif
+
+ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u32 regs)
++ struct brcmf_chip *ci)
+ {
+ u32 regdata;
+- int ret;
++ u32 socitype;
+
+ /* Get CC core rev
+- * Chipid is assume to be at offset 0 from regs arg
++ * Chipid is assume to be at offset 0 from SI_ENUM_BASE
+ * For different chiptypes or old sdio hosts w/o chipcommon,
+ * other ways of recognition should be added here.
+ */
+- ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
+- ci->c_inf[0].base = regs;
+- regdata = brcmf_sdio_regrl(sdiodev,
+- CORE_CC_REG(ci->c_inf[0].base, chipid),
+- NULL);
++ regdata = brcmf_sdiod_regrl(sdiodev,
++ CORE_CC_REG(SI_ENUM_BASE, chipid),
++ NULL);
+ ci->chip = regdata & CID_ID_MASK;
+ ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
+- ci->socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
+-
+- brcmf_dbg(INFO, "chipid=0x%x chiprev=%d\n", ci->chip, ci->chiprev);
++ if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
++ ci->chiprev >= 2)
++ ci->chip = BCM4339_CHIP_ID;
++ socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
++
++ brcmf_dbg(INFO, "found %s chip: id=0x%x, rev=%d\n",
++ socitype == SOCI_SB ? "SB" : "AXI", ci->chip, ci->chiprev);
++
++ if (socitype == SOCI_SB) {
++ if (ci->chip != BCM4329_CHIP_ID) {
++ brcmf_err("SB chip is not supported\n");
++ return -ENODEV;
++ }
++ ci->iscoreup = brcmf_sdio_sb_iscoreup;
++ ci->corerev = brcmf_sdio_sb_corerev;
++ ci->coredisable = brcmf_sdio_sb_coredisable;
++ ci->resetcore = brcmf_sdio_sb_resetcore;
+
+- /* Address of cores for new chips should be added here */
+- switch (ci->chip) {
+- case BCM43143_CHIP_ID:
+- ci->c_inf[0].wrapbase = ci->c_inf[0].base + 0x00100000;
+- ci->c_inf[0].cib = 0x2b000000;
+- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
+- ci->c_inf[1].base = BCM43143_CORE_BUS_BASE;
+- ci->c_inf[1].wrapbase = ci->c_inf[1].base + 0x00100000;
+- ci->c_inf[1].cib = 0x18000000;
+- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
+- ci->c_inf[2].base = BCM43143_CORE_SOCRAM_BASE;
+- ci->c_inf[2].wrapbase = ci->c_inf[2].base + 0x00100000;
+- ci->c_inf[2].cib = 0x14000000;
+- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
+- ci->c_inf[3].base = BCM43143_CORE_ARM_BASE;
+- ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
+- ci->c_inf[3].cib = 0x07000000;
+- ci->ramsize = BCM43143_RAMSIZE;
+- break;
+- case BCM43241_CHIP_ID:
+- ci->c_inf[0].wrapbase = 0x18100000;
+- ci->c_inf[0].cib = 0x2a084411;
+- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
+- ci->c_inf[1].base = 0x18002000;
+- ci->c_inf[1].wrapbase = 0x18102000;
+- ci->c_inf[1].cib = 0x0e004211;
+- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
+- ci->c_inf[2].base = 0x18004000;
+- ci->c_inf[2].wrapbase = 0x18104000;
+- ci->c_inf[2].cib = 0x14080401;
+- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
+- ci->c_inf[3].base = 0x18003000;
+- ci->c_inf[3].wrapbase = 0x18103000;
+- ci->c_inf[3].cib = 0x07004211;
+- ci->ramsize = 0x90000;
+- break;
+- case BCM4329_CHIP_ID:
++ ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
++ ci->c_inf[0].base = SI_ENUM_BASE;
+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
+ ci->c_inf[1].base = BCM4329_CORE_BUS_BASE;
+ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
+ ci->c_inf[2].base = BCM4329_CORE_SOCRAM_BASE;
+ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
+ ci->c_inf[3].base = BCM4329_CORE_ARM_BASE;
++ ci->c_inf[4].id = BCMA_CORE_80211;
++ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
+ ci->ramsize = BCM4329_RAMSIZE;
+- break;
+- case BCM4330_CHIP_ID:
+- ci->c_inf[0].wrapbase = 0x18100000;
+- ci->c_inf[0].cib = 0x27004211;
+- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
+- ci->c_inf[1].base = 0x18002000;
+- ci->c_inf[1].wrapbase = 0x18102000;
+- ci->c_inf[1].cib = 0x07004211;
+- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
+- ci->c_inf[2].base = 0x18004000;
+- ci->c_inf[2].wrapbase = 0x18104000;
+- ci->c_inf[2].cib = 0x0d080401;
+- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
+- ci->c_inf[3].base = 0x18003000;
+- ci->c_inf[3].wrapbase = 0x18103000;
+- ci->c_inf[3].cib = 0x03004211;
+- ci->ramsize = 0x48000;
+- break;
+- case BCM4334_CHIP_ID:
+- ci->c_inf[0].wrapbase = 0x18100000;
+- ci->c_inf[0].cib = 0x29004211;
+- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
+- ci->c_inf[1].base = 0x18002000;
+- ci->c_inf[1].wrapbase = 0x18102000;
+- ci->c_inf[1].cib = 0x0d004211;
+- ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
+- ci->c_inf[2].base = 0x18004000;
+- ci->c_inf[2].wrapbase = 0x18104000;
+- ci->c_inf[2].cib = 0x13080401;
+- ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
+- ci->c_inf[3].base = 0x18003000;
+- ci->c_inf[3].wrapbase = 0x18103000;
+- ci->c_inf[3].cib = 0x07004211;
+- ci->ramsize = 0x80000;
+- break;
+- case BCM4335_CHIP_ID:
+- ci->c_inf[0].wrapbase = 0x18100000;
+- ci->c_inf[0].cib = 0x2b084411;
+- ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
+- ci->c_inf[1].base = 0x18005000;
+- ci->c_inf[1].wrapbase = 0x18105000;
+- ci->c_inf[1].cib = 0x0f004211;
+- ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
+- ci->c_inf[2].base = 0x18002000;
+- ci->c_inf[2].wrapbase = 0x18102000;
+- ci->c_inf[2].cib = 0x01084411;
+- ci->ramsize = 0xc0000;
+- ci->rambase = 0x180000;
+- break;
+- default:
+- brcmf_err("chipid 0x%x is not supported\n", ci->chip);
+- return -ENODEV;
+- }
+-
+- ret = brcmf_sdio_chip_cichk(ci);
+- if (ret)
+- return ret;
+-
+- switch (ci->socitype) {
+- case SOCI_SB:
+- ci->iscoreup = brcmf_sdio_sb_iscoreup;
+- ci->corerev = brcmf_sdio_sb_corerev;
+- ci->coredisable = brcmf_sdio_sb_coredisable;
+- ci->resetcore = brcmf_sdio_sb_resetcore;
+- break;
+- case SOCI_AI:
++ } else if (socitype == SOCI_AI) {
+ ci->iscoreup = brcmf_sdio_ai_iscoreup;
+ ci->corerev = brcmf_sdio_ai_corerev;
+ ci->coredisable = brcmf_sdio_ai_coredisable;
+ ci->resetcore = brcmf_sdio_ai_resetcore;
+- break;
+- default:
+- brcmf_err("socitype %u not supported\n", ci->socitype);
++
++ ci->c_inf[0].id = BCMA_CORE_CHIPCOMMON;
++ ci->c_inf[0].base = SI_ENUM_BASE;
++
++ /* Address of cores for new chips should be added here */
++ switch (ci->chip) {
++ case BCM43143_CHIP_ID:
++ ci->c_inf[0].wrapbase = ci->c_inf[0].base + 0x00100000;
++ ci->c_inf[0].cib = 0x2b000000;
++ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
++ ci->c_inf[1].base = BCM43143_CORE_BUS_BASE;
++ ci->c_inf[1].wrapbase = ci->c_inf[1].base + 0x00100000;
++ ci->c_inf[1].cib = 0x18000000;
++ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
++ ci->c_inf[2].base = BCM43143_CORE_SOCRAM_BASE;
++ ci->c_inf[2].wrapbase = ci->c_inf[2].base + 0x00100000;
++ ci->c_inf[2].cib = 0x14000000;
++ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
++ ci->c_inf[3].base = BCM43143_CORE_ARM_BASE;
++ ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
++ ci->c_inf[3].cib = 0x07000000;
++ ci->c_inf[4].id = BCMA_CORE_80211;
++ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
++ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
++ ci->ramsize = BCM43143_RAMSIZE;
++ break;
++ case BCM43241_CHIP_ID:
++ ci->c_inf[0].wrapbase = 0x18100000;
++ ci->c_inf[0].cib = 0x2a084411;
++ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
++ ci->c_inf[1].base = 0x18002000;
++ ci->c_inf[1].wrapbase = 0x18102000;
++ ci->c_inf[1].cib = 0x0e004211;
++ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
++ ci->c_inf[2].base = 0x18004000;
++ ci->c_inf[2].wrapbase = 0x18104000;
++ ci->c_inf[2].cib = 0x14080401;
++ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
++ ci->c_inf[3].base = 0x18003000;
++ ci->c_inf[3].wrapbase = 0x18103000;
++ ci->c_inf[3].cib = 0x07004211;
++ ci->c_inf[4].id = BCMA_CORE_80211;
++ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
++ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
++ ci->ramsize = 0x90000;
++ break;
++ case BCM4330_CHIP_ID:
++ ci->c_inf[0].wrapbase = 0x18100000;
++ ci->c_inf[0].cib = 0x27004211;
++ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
++ ci->c_inf[1].base = 0x18002000;
++ ci->c_inf[1].wrapbase = 0x18102000;
++ ci->c_inf[1].cib = 0x07004211;
++ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
++ ci->c_inf[2].base = 0x18004000;
++ ci->c_inf[2].wrapbase = 0x18104000;
++ ci->c_inf[2].cib = 0x0d080401;
++ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
++ ci->c_inf[3].base = 0x18003000;
++ ci->c_inf[3].wrapbase = 0x18103000;
++ ci->c_inf[3].cib = 0x03004211;
++ ci->c_inf[4].id = BCMA_CORE_80211;
++ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
++ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
++ ci->ramsize = 0x48000;
++ break;
++ case BCM4334_CHIP_ID:
++ ci->c_inf[0].wrapbase = 0x18100000;
++ ci->c_inf[0].cib = 0x29004211;
++ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
++ ci->c_inf[1].base = 0x18002000;
++ ci->c_inf[1].wrapbase = 0x18102000;
++ ci->c_inf[1].cib = 0x0d004211;
++ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
++ ci->c_inf[2].base = 0x18004000;
++ ci->c_inf[2].wrapbase = 0x18104000;
++ ci->c_inf[2].cib = 0x13080401;
++ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
++ ci->c_inf[3].base = 0x18003000;
++ ci->c_inf[3].wrapbase = 0x18103000;
++ ci->c_inf[3].cib = 0x07004211;
++ ci->c_inf[4].id = BCMA_CORE_80211;
++ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
++ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
++ ci->ramsize = 0x80000;
++ break;
++ case BCM4335_CHIP_ID:
++ ci->c_inf[0].wrapbase = 0x18100000;
++ ci->c_inf[0].cib = 0x2b084411;
++ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
++ ci->c_inf[1].base = 0x18005000;
++ ci->c_inf[1].wrapbase = 0x18105000;
++ ci->c_inf[1].cib = 0x0f004211;
++ ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
++ ci->c_inf[2].base = 0x18002000;
++ ci->c_inf[2].wrapbase = 0x18102000;
++ ci->c_inf[2].cib = 0x01084411;
++ ci->c_inf[3].id = BCMA_CORE_80211;
++ ci->c_inf[3].base = BCM43xx_CORE_D11_BASE;
++ ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
++ ci->ramsize = 0xc0000;
++ ci->rambase = 0x180000;
++ break;
++ case BCM43362_CHIP_ID:
++ ci->c_inf[0].wrapbase = 0x18100000;
++ ci->c_inf[0].cib = 0x27004211;
++ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
++ ci->c_inf[1].base = 0x18002000;
++ ci->c_inf[1].wrapbase = 0x18102000;
++ ci->c_inf[1].cib = 0x0a004211;
++ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
++ ci->c_inf[2].base = 0x18004000;
++ ci->c_inf[2].wrapbase = 0x18104000;
++ ci->c_inf[2].cib = 0x08080401;
++ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
++ ci->c_inf[3].base = 0x18003000;
++ ci->c_inf[3].wrapbase = 0x18103000;
++ ci->c_inf[3].cib = 0x03004211;
++ ci->c_inf[4].id = BCMA_CORE_80211;
++ ci->c_inf[4].base = BCM43xx_CORE_D11_BASE;
++ ci->c_inf[4].wrapbase = ci->c_inf[4].base + 0x00100000;
++ ci->ramsize = 0x3C000;
++ break;
++ case BCM4339_CHIP_ID:
++ ci->c_inf[0].wrapbase = 0x18100000;
++ ci->c_inf[0].cib = 0x2e084411;
++ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
++ ci->c_inf[1].base = 0x18005000;
++ ci->c_inf[1].wrapbase = 0x18105000;
++ ci->c_inf[1].cib = 0x15004211;
++ ci->c_inf[2].id = BCMA_CORE_ARM_CR4;
++ ci->c_inf[2].base = 0x18002000;
++ ci->c_inf[2].wrapbase = 0x18102000;
++ ci->c_inf[2].cib = 0x04084411;
++ ci->c_inf[3].id = BCMA_CORE_80211;
++ ci->c_inf[3].base = BCM43xx_CORE_D11_BASE;
++ ci->c_inf[3].wrapbase = ci->c_inf[3].base + 0x00100000;
++ ci->ramsize = 0xc0000;
++ ci->rambase = 0x180000;
++ break;
++ default:
++ brcmf_err("AXI chip is not supported\n");
++ return -ENODEV;
++ }
++ } else {
++ brcmf_err("chip backplane type %u is not supported\n",
++ socitype);
+ return -ENODEV;
+ }
+
+- return 0;
++ return brcmf_sdio_chip_cichk(ci);
+ }
+
+ static int
+@@ -579,7 +669,7 @@
+
+ /* Try forcing SDIO core to do ALPAvail request only */
+ clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
+- brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
+ if (err) {
+ brcmf_err("error writing for HT off\n");
+ return err;
+@@ -587,8 +677,8 @@
+
+ /* If register supported, wait for ALPAvail and then force ALP */
+ /* This may take up to 15 milliseconds */
+- clkval = brcmf_sdio_regrb(sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, NULL);
++ clkval = brcmf_sdiod_regrb(sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, NULL);
+
+ if ((clkval & ~SBSDIO_AVBITS) != clkset) {
+ brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
+@@ -596,8 +686,8 @@
+ return -EACCES;
+ }
+
+- SPINWAIT(((clkval = brcmf_sdio_regrb(sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
++ SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
+ !SBSDIO_ALPAV(clkval)),
+ PMU_MAX_TRANSITION_DLY);
+ if (!SBSDIO_ALPAV(clkval)) {
+@@ -607,18 +697,18 @@
+ }
+
+ clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
+- brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
+ udelay(65);
+
+ /* Also, disable the extra SDIO pull-ups */
+- brcmf_sdio_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
+
+ return 0;
+ }
+
+ static void
+ brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci)
++ struct brcmf_chip *ci)
+ {
+ u32 base = ci->c_inf[0].base;
+
+@@ -626,16 +716,16 @@
+ ci->c_inf[0].rev = ci->corerev(sdiodev, ci, ci->c_inf[0].id);
+
+ /* get chipcommon capabilites */
+- ci->c_inf[0].caps = brcmf_sdio_regrl(sdiodev,
+- CORE_CC_REG(base, capabilities),
+- NULL);
++ ci->c_inf[0].caps = brcmf_sdiod_regrl(sdiodev,
++ CORE_CC_REG(base, capabilities),
++ NULL);
+
+ /* get pmu caps & rev */
+ if (ci->c_inf[0].caps & CC_CAP_PMU) {
+ ci->pmucaps =
+- brcmf_sdio_regrl(sdiodev,
+- CORE_CC_REG(base, pmucapabilities),
+- NULL);
++ brcmf_sdiod_regrl(sdiodev,
++ CORE_CC_REG(base, pmucapabilities),
++ NULL);
+ ci->pmurev = ci->pmucaps & PCAP_REV_MASK;
+ }
+
+@@ -649,19 +739,18 @@
+ * Make sure any on-chip ARM is off (in case strapping is wrong),
+ * or downloaded code was already running.
+ */
+- ci->coredisable(sdiodev, ci, BCMA_CORE_ARM_CM3, 0);
++ ci->coredisable(sdiodev, ci, BCMA_CORE_ARM_CM3, 0, 0);
+ }
+
+ int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info **ci_ptr, u32 regs)
++ struct brcmf_chip **ci_ptr)
+ {
+ int ret;
+- struct chip_info *ci;
++ struct brcmf_chip *ci;
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+- /* alloc chip_info_t */
+- ci = kzalloc(sizeof(struct chip_info), GFP_ATOMIC);
++ ci = kzalloc(sizeof(*ci), GFP_ATOMIC);
+ if (!ci)
+ return -ENOMEM;
+
+@@ -669,16 +758,16 @@
+ if (ret != 0)
+ goto err;
+
+- ret = brcmf_sdio_chip_recognition(sdiodev, ci, regs);
++ ret = brcmf_sdio_chip_recognition(sdiodev, ci);
+ if (ret != 0)
+ goto err;
+
+ brcmf_sdio_chip_buscoresetup(sdiodev, ci);
+
+- brcmf_sdio_regwl(sdiodev, CORE_CC_REG(ci->c_inf[0].base, gpiopullup),
+- 0, NULL);
+- brcmf_sdio_regwl(sdiodev, CORE_CC_REG(ci->c_inf[0].base, gpiopulldown),
+- 0, NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_CC_REG(ci->c_inf[0].base, gpiopullup),
++ 0, NULL);
++ brcmf_sdiod_regwl(sdiodev, CORE_CC_REG(ci->c_inf[0].base, gpiopulldown),
++ 0, NULL);
+
+ *ci_ptr = ci;
+ return 0;
+@@ -689,7 +778,7 @@
+ }
+
+ void
+-brcmf_sdio_chip_detach(struct chip_info **ci_ptr)
++brcmf_sdio_chip_detach(struct brcmf_chip **ci_ptr)
+ {
+ brcmf_dbg(TRACE, "Enter\n");
+
+@@ -708,7 +797,7 @@
+
+ void
+ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u32 drivestrength)
++ struct brcmf_chip *ci, u32 drivestrength)
+ {
+ const struct sdiod_drive_str *str_tab = NULL;
+ u32 str_mask;
+@@ -729,6 +818,11 @@
+ str_mask = 0x00003800;
+ str_shift = 11;
+ break;
++ case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17):
++ str_tab = sdiod_drvstr_tab6_1v8;
++ str_mask = 0x00001800;
++ str_shift = 11;
++ break;
+ case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17):
+ /* note: 43143 does not support tristate */
+ i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
+@@ -741,6 +835,11 @@
+ brcmf_sdio_chip_name(ci->chip, chn, 8),
+ drivestrength);
+ break;
++ case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
++ str_tab = sdiod_drive_strength_tab5_1v8;
++ str_mask = 0x00003800;
++ str_shift = 11;
++ break;
+ default:
+ brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
+ brcmf_sdio_chip_name(ci->chip, chn, 8),
+@@ -756,119 +855,31 @@
+ }
+ }
+ addr = CORE_CC_REG(base, chipcontrol_addr);
+- brcmf_sdio_regwl(sdiodev, addr, 1, NULL);
+- cc_data_temp = brcmf_sdio_regrl(sdiodev, addr, NULL);
++ brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
++ cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
+ cc_data_temp &= ~str_mask;
+ drivestrength_sel <<= str_shift;
+ cc_data_temp |= drivestrength_sel;
+- brcmf_sdio_regwl(sdiodev, addr, cc_data_temp, NULL);
++ brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
+
+ brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
+ str_tab[i].strength, drivestrength, cc_data_temp);
+ }
+ }
+
+-#ifdef DEBUG
+-static bool
+-brcmf_sdio_chip_verifynvram(struct brcmf_sdio_dev *sdiodev, u32 nvram_addr,
+- char *nvram_dat, uint nvram_sz)
+-{
+- char *nvram_ularray;
+- int err;
+- bool ret = true;
+-
+- /* read back and verify */
+- brcmf_dbg(INFO, "Compare NVRAM dl & ul; size=%d\n", nvram_sz);
+- nvram_ularray = kmalloc(nvram_sz, GFP_KERNEL);
+- /* do not proceed while no memory but */
+- if (!nvram_ularray)
+- return true;
+-
+- /* Upload image to verify downloaded contents. */
+- memset(nvram_ularray, 0xaa, nvram_sz);
+-
+- /* Read the vars list to temp buffer for comparison */
+- err = brcmf_sdio_ramrw(sdiodev, false, nvram_addr, nvram_ularray,
+- nvram_sz);
+- if (err) {
+- brcmf_err("error %d on reading %d nvram bytes at 0x%08x\n",
+- err, nvram_sz, nvram_addr);
+- } else if (memcmp(nvram_dat, nvram_ularray, nvram_sz)) {
+- brcmf_err("Downloaded NVRAM image is corrupted\n");
+- ret = false;
+- }
+- kfree(nvram_ularray);
+-
+- return ret;
+-}
+-#else /* DEBUG */
+-static inline bool
+-brcmf_sdio_chip_verifynvram(struct brcmf_sdio_dev *sdiodev, u32 nvram_addr,
+- char *nvram_dat, uint nvram_sz)
+-{
+- return true;
+-}
+-#endif /* DEBUG */
+-
+-static bool brcmf_sdio_chip_writenvram(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci,
+- char *nvram_dat, uint nvram_sz)
+-{
+- int err;
+- u32 nvram_addr;
+- u32 token;
+- __le32 token_le;
+-
+- nvram_addr = (ci->ramsize - 4) - nvram_sz + ci->rambase;
+-
+- /* Write the vars list */
+- err = brcmf_sdio_ramrw(sdiodev, true, nvram_addr, nvram_dat, nvram_sz);
+- if (err) {
+- brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
+- err, nvram_sz, nvram_addr);
+- return false;
+- }
+-
+- if (!brcmf_sdio_chip_verifynvram(sdiodev, nvram_addr,
+- nvram_dat, nvram_sz))
+- return false;
+-
+- /* generate token:
+- * nvram size, converted to words, in lower 16-bits, checksum
+- * in upper 16-bits.
+- */
+- token = nvram_sz / 4;
+- token = (~token << 16) | (token & 0x0000FFFF);
+- token_le = cpu_to_le32(token);
+-
+- brcmf_dbg(INFO, "RAM size: %d\n", ci->ramsize);
+- brcmf_dbg(INFO, "nvram is placed at %d, size %d, token=0x%08x\n",
+- nvram_addr, nvram_sz, token);
+-
+- /* Write the length token to the last word */
+- if (brcmf_sdio_ramrw(sdiodev, true, (ci->ramsize - 4 + ci->rambase),
+- (u8 *)&token_le, 4))
+- return false;
+-
+- return true;
+-}
+-
+ static void
+ brcmf_sdio_chip_cm3_enterdl(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci)
++ struct brcmf_chip *ci)
+ {
+- u32 zeros = 0;
+-
+- ci->coredisable(sdiodev, ci, BCMA_CORE_ARM_CM3, 0);
+- ci->resetcore(sdiodev, ci, BCMA_CORE_INTERNAL_MEM, 0);
+-
+- /* clear length token */
+- brcmf_sdio_ramrw(sdiodev, true, ci->ramsize - 4, (u8 *)&zeros, 4);
++ ci->coredisable(sdiodev, ci, BCMA_CORE_ARM_CM3, 0, 0);
++ ci->resetcore(sdiodev, ci, BCMA_CORE_80211,
++ D11_BCMA_IOCTL_PHYRESET | D11_BCMA_IOCTL_PHYCLOCKEN,
++ D11_BCMA_IOCTL_PHYCLOCKEN, D11_BCMA_IOCTL_PHYCLOCKEN);
++ ci->resetcore(sdiodev, ci, BCMA_CORE_INTERNAL_MEM, 0, 0, 0);
+ }
+
+-static bool
+-brcmf_sdio_chip_cm3_exitdl(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
+- char *nvram_dat, uint nvram_sz)
++static bool brcmf_sdio_chip_cm3_exitdl(struct brcmf_sdio_dev *sdiodev,
++ struct brcmf_chip *ci)
+ {
+ u8 core_idx;
+ u32 reg_addr;
+@@ -878,56 +889,64 @@
+ return false;
+ }
+
+- if (!brcmf_sdio_chip_writenvram(sdiodev, ci, nvram_dat, nvram_sz))
+- return false;
+-
+ /* clear all interrupts */
+ core_idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_SDIO_DEV);
+ reg_addr = ci->c_inf[core_idx].base;
+ reg_addr += offsetof(struct sdpcmd_regs, intstatus);
+- brcmf_sdio_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
++ brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
+
+- ci->resetcore(sdiodev, ci, BCMA_CORE_ARM_CM3, 0);
++ ci->resetcore(sdiodev, ci, BCMA_CORE_ARM_CM3, 0, 0, 0);
+
+ return true;
+ }
+
+ static inline void
+ brcmf_sdio_chip_cr4_enterdl(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci)
++ struct brcmf_chip *ci)
+ {
+- ci->resetcore(sdiodev, ci, BCMA_CORE_ARM_CR4,
+- ARMCR4_BCMA_IOCTL_CPUHALT);
++ u8 idx;
++ u32 regdata;
++ u32 wrapbase;
++ idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_ARM_CR4);
++
++ if (idx == BRCMF_MAX_CORENUM)
++ return;
++
++ wrapbase = ci->c_inf[idx].wrapbase;
++ regdata = brcmf_sdiod_regrl(sdiodev, wrapbase + BCMA_IOCTL, NULL);
++ regdata &= ARMCR4_BCMA_IOCTL_CPUHALT;
++ ci->resetcore(sdiodev, ci, BCMA_CORE_ARM_CR4, regdata,
++ ARMCR4_BCMA_IOCTL_CPUHALT, ARMCR4_BCMA_IOCTL_CPUHALT);
++ ci->resetcore(sdiodev, ci, BCMA_CORE_80211,
++ D11_BCMA_IOCTL_PHYRESET | D11_BCMA_IOCTL_PHYCLOCKEN,
++ D11_BCMA_IOCTL_PHYCLOCKEN, D11_BCMA_IOCTL_PHYCLOCKEN);
+ }
+
+-static bool
+-brcmf_sdio_chip_cr4_exitdl(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
+- char *nvram_dat, uint nvram_sz)
++static bool brcmf_sdio_chip_cr4_exitdl(struct brcmf_sdio_dev *sdiodev,
++ struct brcmf_chip *ci, u32 rstvec)
+ {
+ u8 core_idx;
+ u32 reg_addr;
+
+- if (!brcmf_sdio_chip_writenvram(sdiodev, ci, nvram_dat, nvram_sz))
+- return false;
+-
+ /* clear all interrupts */
+ core_idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_SDIO_DEV);
+ reg_addr = ci->c_inf[core_idx].base;
+ reg_addr += offsetof(struct sdpcmd_regs, intstatus);
+- brcmf_sdio_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
++ brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
+
+ /* Write reset vector to address 0 */
+- brcmf_sdio_ramrw(sdiodev, true, 0, (void *)&ci->rst_vec,
+- sizeof(ci->rst_vec));
++ brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
++ sizeof(rstvec));
+
+ /* restore ARM */
+- ci->resetcore(sdiodev, ci, BCMA_CORE_ARM_CR4, 0);
++ ci->resetcore(sdiodev, ci, BCMA_CORE_ARM_CR4, ARMCR4_BCMA_IOCTL_CPUHALT,
++ 0, 0);
+
+ return true;
+ }
+
+ void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci)
++ struct brcmf_chip *ci)
+ {
+ u8 arm_core_idx;
+
+@@ -941,15 +960,13 @@
+ }
+
+ bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, char *nvram_dat,
+- uint nvram_sz)
++ struct brcmf_chip *ci, u32 rstvec)
+ {
+ u8 arm_core_idx;
+
+ arm_core_idx = brcmf_sdio_chip_getinfidx(ci, BCMA_CORE_ARM_CM3);
+ if (BRCMF_MAX_CORENUM != arm_core_idx)
+- return brcmf_sdio_chip_cm3_exitdl(sdiodev, ci, nvram_dat,
+- nvram_sz);
++ return brcmf_sdio_chip_cm3_exitdl(sdiodev, ci);
+
+- return brcmf_sdio_chip_cr4_exitdl(sdiodev, ci, nvram_dat, nvram_sz);
++ return brcmf_sdio_chip_cr4_exitdl(sdiodev, ci, rstvec);
+ }
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h 2014-05-15 20:34:00.578032457 +0200
+@@ -54,7 +54,7 @@
+
+ #define BRCMF_MAX_CORENUM 6
+
+-struct chip_core_info {
++struct brcmf_core {
+ u16 id;
+ u16 rev;
+ u32 base;
+@@ -63,27 +63,28 @@
+ u32 cib;
+ };
+
+-struct chip_info {
++struct brcmf_chip {
+ u32 chip;
+ u32 chiprev;
+- u32 socitype;
+ /* core info */
+ /* always put chipcommon core at 0, bus core at 1 */
+- struct chip_core_info c_inf[BRCMF_MAX_CORENUM];
++ struct brcmf_core c_inf[BRCMF_MAX_CORENUM];
+ u32 pmurev;
+ u32 pmucaps;
+ u32 ramsize;
+ u32 rambase;
+ u32 rst_vec; /* reset vertor for ARM CR4 core */
+
+- bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
++ bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct brcmf_chip *ci,
+ u16 coreid);
+- u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct chip_info *ci,
++ u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct brcmf_chip *ci,
+ u16 coreid);
+ void (*coredisable)(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid, u32 core_bits);
++ struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits,
++ u32 in_resetbits);
+ void (*resetcore)(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, u16 coreid, u32 core_bits);
++ struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits,
++ u32 in_resetbits, u32 post_resetbits);
+ };
+
+ struct sbconfig {
+@@ -215,17 +216,16 @@
+ u16 PAD[0x80];
+ };
+
+-extern int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info **ci_ptr, u32 regs);
+-extern void brcmf_sdio_chip_detach(struct chip_info **ci_ptr);
+-extern void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci,
+- u32 drivestrength);
+-extern u8 brcmf_sdio_chip_getinfidx(struct chip_info *ci, u16 coreid);
+-extern void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci);
+-extern bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev *sdiodev,
+- struct chip_info *ci, char *nvram_dat,
+- uint nvram_sz);
++int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
++ struct brcmf_chip **ci_ptr);
++void brcmf_sdio_chip_detach(struct brcmf_chip **ci_ptr);
++void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
++ struct brcmf_chip *ci,
++ u32 drivestrength);
++u8 brcmf_sdio_chip_getinfidx(struct brcmf_chip *ci, u16 coreid);
++void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev *sdiodev,
++ struct brcmf_chip *ci);
++bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev *sdiodev,
++ struct brcmf_chip *ci, u32 rstvec);
+
+ #endif /* _BRCMFMAC_SDIO_CHIP_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h 2014-05-15 20:34:00.578032457 +0200
+@@ -164,13 +164,10 @@
+ struct brcmf_sdio_dev {
+ struct sdio_func *func[SDIO_MAX_FUNCS];
+ u8 num_funcs; /* Supported funcs on client */
+- u32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
+ u32 sbwad; /* Save backplane window address */
+- void *bus;
++ struct brcmf_sdio *bus;
+ atomic_t suspend; /* suspend flag */
+- wait_queue_head_t request_byte_wait;
+ wait_queue_head_t request_word_wait;
+- wait_queue_head_t request_chain_wait;
+ wait_queue_head_t request_buffer_wait;
+ struct device *dev;
+ struct brcmf_bus *bus_if;
+@@ -179,25 +176,26 @@
+ bool irq_en; /* irq enable flags */
+ spinlock_t irq_en_lock;
+ bool irq_wake; /* irq wake enable flags */
++ bool sg_support;
++ uint max_request_size;
++ ushort max_segment_count;
++ uint max_segment_size;
+ };
+
+ /* Register/deregister interrupt handler. */
+-extern int brcmf_sdio_intr_register(struct brcmf_sdio_dev *sdiodev);
+-extern int brcmf_sdio_intr_unregister(struct brcmf_sdio_dev *sdiodev);
++int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
++int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
+
+ /* sdio device register access interface */
+-extern u8 brcmf_sdio_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
+-extern u32 brcmf_sdio_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
+-extern void brcmf_sdio_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr,
+- u8 data, int *ret);
+-extern void brcmf_sdio_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr,
+- u32 data, int *ret);
+-extern int brcmf_sdio_regrw_helper(struct brcmf_sdio_dev *sdiodev, u32 addr,
+- void *data, bool write);
++u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
++u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
++void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data,
++ int *ret);
++void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
++ int *ret);
+
+ /* Buffer transfer to/from device (client) core via cmd53.
+ * fn: function number
+- * addr: backplane address (i.e. >= regsva from attach)
+ * flags: backplane width, address increment, sync/async
+ * buf: pointer to memory data buffer
+ * nbytes: number of bytes to transfer to/from buf
+@@ -207,22 +205,14 @@
+ * Returns 0 or error code.
+ * NOTE: Async operation is not currently supported.
+ */
+-extern int
+-brcmf_sdcard_send_pkt(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, struct sk_buff *pkt);
+-extern int
+-brcmf_sdcard_send_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, u8 *buf, uint nbytes);
+-
+-extern int
+-brcmf_sdcard_recv_pkt(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, struct sk_buff *pkt);
+-extern int
+-brcmf_sdcard_recv_buf(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, u8 *buf, uint nbytes);
+-extern int
+-brcmf_sdcard_recv_chain(struct brcmf_sdio_dev *sdiodev, u32 addr, uint fn,
+- uint flags, struct sk_buff_head *pktq);
++int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
++ struct sk_buff_head *pktq);
++int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
++
++int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt);
++int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
++int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
++ struct sk_buff_head *pktq, uint totlen);
+
+ /* Flags bits */
+
+@@ -230,8 +220,6 @@
+ #define SDIO_REQ_4BYTE 0x1
+ /* Fixed address (FIFO) (vs. incrementing address) */
+ #define SDIO_REQ_FIXED 0x2
+-/* Async request (vs. sync request) */
+-#define SDIO_REQ_ASYNC 0x4
+
+ /* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
+ * rw: read or write (0/1)
+@@ -240,55 +228,16 @@
+ * nbytes: number of bytes to transfer to/from buf
+ * Returns 0 or error code.
+ */
+-extern int brcmf_sdcard_rwdata(struct brcmf_sdio_dev *sdiodev, uint rw,
+- u32 addr, u8 *buf, uint nbytes);
+-extern int brcmf_sdio_ramrw(struct brcmf_sdio_dev *sdiodev, bool write,
+- u32 address, u8 *data, uint size);
++int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
++ u8 *data, uint size);
+
+ /* Issue an abort to the specified function */
+-extern int brcmf_sdcard_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
++int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
+
+-/* platform specific/high level functions */
+-extern int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
+-extern int brcmf_sdio_remove(struct brcmf_sdio_dev *sdiodev);
+-
+-extern int brcmf_sdcard_set_sbaddr_window(struct brcmf_sdio_dev *sdiodev,
+- u32 address);
+-
+-/* attach, return handler on success, NULL if failed.
+- * The handler shall be provided by all subsequent calls. No local cache
+- * cfghdl points to the starting address of pci device mapped memory
+- */
+-extern int brcmf_sdioh_attach(struct brcmf_sdio_dev *sdiodev);
+-extern void brcmf_sdioh_detach(struct brcmf_sdio_dev *sdiodev);
++struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
++void brcmf_sdio_remove(struct brcmf_sdio *bus);
++void brcmf_sdio_isr(struct brcmf_sdio *bus);
+
+-/* read or write one byte using cmd52 */
+-extern int brcmf_sdioh_request_byte(struct brcmf_sdio_dev *sdiodev, uint rw,
+- uint fnc, uint addr, u8 *byte);
+-
+-/* read or write 2/4 bytes using cmd53 */
+-extern int
+-brcmf_sdioh_request_word(struct brcmf_sdio_dev *sdiodev,
+- uint rw, uint fnc, uint addr,
+- u32 *word, uint nbyte);
+-
+-/* read or write any buffer using cmd53 */
+-extern int
+-brcmf_sdioh_request_buffer(struct brcmf_sdio_dev *sdiodev,
+- uint fix_inc, uint rw, uint fnc_num, u32 addr,
+- struct sk_buff *pkt);
+-extern int
+-brcmf_sdioh_request_chain(struct brcmf_sdio_dev *sdiodev, uint fix_inc,
+- uint write, uint func, uint addr,
+- struct sk_buff_head *pktq);
+-
+-/* Watchdog timer interface for pm ops */
+-extern void brcmf_sdio_wdtmr_enable(struct brcmf_sdio_dev *sdiodev,
+- bool enable);
+-
+-extern void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev);
+-extern void brcmf_sdbrcm_disconnect(void *ptr);
+-extern void brcmf_sdbrcm_isr(void *arg);
++void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick);
+
+-extern void brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick);
+ #endif /* _BRCM_SDH_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/tracepoint.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/tracepoint.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/tracepoint.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/tracepoint.h 2014-05-15 20:34:00.578032457 +0200
+@@ -78,13 +78,64 @@
+ TP_ARGS(data, len),
+ TP_STRUCT__entry(
+ __field(unsigned long, len)
++ __field(unsigned long, addr)
+ __dynamic_array(u8, hdata, len)
+ ),
+ TP_fast_assign(
+ __entry->len = len;
++ __entry->addr = (unsigned long)data;
+ memcpy(__get_dynamic_array(hdata), data, len);
+ ),
+- TP_printk("hexdump [length=%lu]", __entry->len)
++ TP_printk("hexdump [addr=%lx, length=%lu]", __entry->addr, __entry->len)
++);
++
++TRACE_EVENT(brcmf_bcdchdr,
++ TP_PROTO(void *data),
++ TP_ARGS(data),
++ TP_STRUCT__entry(
++ __field(u8, flags)
++ __field(u8, prio)
++ __field(u8, flags2)
++ __field(u32, siglen)
++ __dynamic_array(u8, signal, *((u8 *)data + 3) * 4)
++ ),
++ TP_fast_assign(
++ __entry->flags = *(u8 *)data;
++ __entry->prio = *((u8 *)data + 1);
++ __entry->flags2 = *((u8 *)data + 2);
++ __entry->siglen = *((u8 *)data + 3) * 4;
++ memcpy(__get_dynamic_array(signal),
++ (u8 *)data + 4, __entry->siglen);
++ ),
++ TP_printk("bcdc: prio=%d siglen=%d", __entry->prio, __entry->siglen)
++);
++
++#ifndef SDPCM_RX
++#define SDPCM_RX 0
++#endif
++#ifndef SDPCM_TX
++#define SDPCM_TX 1
++#endif
++#ifndef SDPCM_GLOM
++#define SDPCM_GLOM 2
++#endif
++
++TRACE_EVENT(brcmf_sdpcm_hdr,
++ TP_PROTO(u8 dir, void *data),
++ TP_ARGS(dir, data),
++ TP_STRUCT__entry(
++ __field(u8, dir)
++ __field(u16, len)
++ __dynamic_array(u8, hdr, dir == SDPCM_GLOM ? 20 : 12)
++ ),
++ TP_fast_assign(
++ memcpy(__get_dynamic_array(hdr), data, dir == SDPCM_GLOM ? 20 : 12);
++ __entry->len = *(u8 *)data | (*((u8 *)data + 1) << 8);
++ __entry->dir = dir;
++ ),
++ TP_printk("sdpcm: %s len %u, seq %d",
++ __entry->dir == SDPCM_RX ? "RX" : "TX",
++ __entry->len, ((u8 *)__get_dynamic_array(hdr))[4])
+ );
+
+ #ifdef CONFIG_BRCM_TRACING
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/usb.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/usb.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/usb.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/usb.c 2014-05-15 20:34:00.582032485 +0200
+@@ -82,6 +82,7 @@
+ int tx_high_watermark;
+ int tx_freecount;
+ bool tx_flowblock;
++ spinlock_t tx_flowblock_lock;
+
+ struct brcmf_usbreq *tx_reqs;
+ struct brcmf_usbreq *rx_reqs;
+@@ -411,6 +412,7 @@
+ {
+ struct brcmf_usbreq *req = (struct brcmf_usbreq *)urb->context;
+ struct brcmf_usbdev_info *devinfo = req->devinfo;
++ unsigned long flags;
+
+ brcmf_dbg(USB, "Enter, urb->status=%d, skb=%p\n", urb->status,
+ req->skb);
+@@ -419,11 +421,13 @@
+ brcmf_txcomplete(devinfo->dev, req->skb, urb->status == 0);
+ req->skb = NULL;
+ brcmf_usb_enq(devinfo, &devinfo->tx_freeq, req, &devinfo->tx_freecount);
++ spin_lock_irqsave(&devinfo->tx_flowblock_lock, flags);
+ if (devinfo->tx_freecount > devinfo->tx_high_watermark &&
+ devinfo->tx_flowblock) {
+ brcmf_txflowblock(devinfo->dev, false);
+ devinfo->tx_flowblock = false;
+ }
++ spin_unlock_irqrestore(&devinfo->tx_flowblock_lock, flags);
+ }
+
+ static void brcmf_usb_rx_complete(struct urb *urb)
+@@ -431,7 +435,6 @@
+ struct brcmf_usbreq *req = (struct brcmf_usbreq *)urb->context;
+ struct brcmf_usbdev_info *devinfo = req->devinfo;
+ struct sk_buff *skb;
+- struct sk_buff_head skbq;
+
+ brcmf_dbg(USB, "Enter, urb->status=%d\n", urb->status);
+ brcmf_usb_del_fromq(devinfo, req);
+@@ -446,10 +449,8 @@
+ }
+
+ if (devinfo->bus_pub.state == BRCMFMAC_USB_STATE_UP) {
+- skb_queue_head_init(&skbq);
+- skb_queue_tail(&skbq, skb);
+ skb_put(skb, urb->actual_length);
+- brcmf_rx_frames(devinfo->dev, &skbq);
++ brcmf_rx_frame(devinfo->dev, skb);
+ brcmf_usb_rx_refill(devinfo, req);
+ } else {
+ brcmu_pkt_buf_free_skb(skb);
+@@ -521,10 +522,10 @@
+ /* update state of upper layer */
+ if (state == BRCMFMAC_USB_STATE_DOWN) {
+ brcmf_dbg(USB, "DBUS is down\n");
+- bcmf_bus->state = BRCMF_BUS_DOWN;
++ brcmf_bus_change_state(bcmf_bus, BRCMF_BUS_DOWN);
+ } else if (state == BRCMFMAC_USB_STATE_UP) {
+ brcmf_dbg(USB, "DBUS is up\n");
+- bcmf_bus->state = BRCMF_BUS_DATA;
++ brcmf_bus_change_state(bcmf_bus, BRCMF_BUS_DATA);
+ } else {
+ brcmf_dbg(USB, "DBUS current state=%d\n", state);
+ }
+@@ -568,6 +569,7 @@
+ struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
+ struct brcmf_usbreq *req;
+ int ret;
++ unsigned long flags;
+
+ brcmf_dbg(USB, "Enter, skb=%p\n", skb);
+ if (devinfo->bus_pub.state != BRCMFMAC_USB_STATE_UP) {
+@@ -599,15 +601,16 @@
+ goto fail;
+ }
+
++ spin_lock_irqsave(&devinfo->tx_flowblock_lock, flags);
+ if (devinfo->tx_freecount < devinfo->tx_low_watermark &&
+ !devinfo->tx_flowblock) {
+ brcmf_txflowblock(dev, true);
+ devinfo->tx_flowblock = true;
+ }
++ spin_unlock_irqrestore(&devinfo->tx_flowblock_lock, flags);
+ return 0;
+
+ fail:
+- brcmf_txcomplete(dev, skb, false);
+ return ret;
+ }
+
+@@ -1164,6 +1167,7 @@
+
+ /* Initialize the spinlocks */
+ spin_lock_init(&devinfo->qlock);
++ spin_lock_init(&devinfo->tx_flowblock_lock);
+
+ INIT_LIST_HEAD(&devinfo->rx_freeq);
+ INIT_LIST_HEAD(&devinfo->rx_postq);
+@@ -1249,9 +1253,10 @@
+ bus->ops = &brcmf_usb_bus_ops;
+ bus->chip = bus_pub->devid;
+ bus->chiprev = bus_pub->chiprev;
++ bus->proto_type = BRCMF_PROTO_BCDC;
+
+ /* Attach to the common driver interface */
+- ret = brcmf_attach(0, dev);
++ ret = brcmf_attach(dev);
+ if (ret) {
+ brcmf_err("brcmf_attach failed\n");
+ goto fail;
+@@ -1450,7 +1455,7 @@
+ struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(&usb->dev);
+
+ brcmf_dbg(USB, "Enter\n");
+- if (!brcmf_attach(0, devinfo->dev))
++ if (!brcmf_attach(devinfo->dev))
+ return brcmf_bus_start(&usb->dev);
+
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c 2014-05-15 20:34:00.582032485 +0200
+@@ -1093,9 +1093,12 @@
+ brcmf_dbg(INFO, "Call WLC_DISASSOC to stop excess roaming\n ");
+ err = brcmf_fil_cmd_data_set(vif->ifp,
+ BRCMF_C_DISASSOC, NULL, 0);
+- if (err)
++ if (err) {
+ brcmf_err("WLC_DISASSOC failed (%d)\n", err);
++ }
+ clear_bit(BRCMF_VIF_STATUS_CONNECTED, &vif->sme_state);
++ cfg80211_disconnected(vif->wdev.netdev, 0, NULL, 0, GFP_KERNEL);
++
+ }
+ clear_bit(BRCMF_VIF_STATUS_CONNECTING, &vif->sme_state);
+ clear_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
+@@ -1755,6 +1758,7 @@
+ return -EIO;
+
+ clear_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state);
++ cfg80211_disconnected(ndev, reason_code, NULL, 0, GFP_KERNEL);
+
+ memcpy(&scbval.ea, &profile->bssid, ETH_ALEN);
+ scbval.val = cpu_to_le32(reason_code);
+@@ -2553,8 +2557,8 @@
+ ch_bss.band == ch_bss_info_le.band &&
+ bss_info_le->SSID_len == bss->SSID_len &&
+ !memcmp(bss_info_le->SSID, bss->SSID, bss_info_le->SSID_len)) {
+- if ((bss->flags & WLC_BSS_RSSI_ON_CHANNEL) ==
+- (bss_info_le->flags & WLC_BSS_RSSI_ON_CHANNEL)) {
++ if ((bss->flags & BRCMF_BSS_RSSI_ON_CHANNEL) ==
++ (bss_info_le->flags & BRCMF_BSS_RSSI_ON_CHANNEL)) {
+ s16 bss_rssi = le16_to_cpu(bss->RSSI);
+ s16 bss_info_rssi = le16_to_cpu(bss_info_le->RSSI);
+
+@@ -2563,13 +2567,13 @@
+ */
+ if (bss_info_rssi > bss_rssi)
+ bss->RSSI = bss_info_le->RSSI;
+- } else if ((bss->flags & WLC_BSS_RSSI_ON_CHANNEL) &&
+- (bss_info_le->flags & WLC_BSS_RSSI_ON_CHANNEL) == 0) {
++ } else if ((bss->flags & BRCMF_BSS_RSSI_ON_CHANNEL) &&
++ (bss_info_le->flags & BRCMF_BSS_RSSI_ON_CHANNEL) == 0) {
+ /* preserve the on-channel rssi measurement
+ * if the new measurement is off channel
+ */
+ bss->RSSI = bss_info_le->RSSI;
+- bss->flags |= WLC_BSS_RSSI_ON_CHANNEL;
++ bss->flags |= BRCMF_BSS_RSSI_ON_CHANNEL;
+ }
+ return 1;
+ }
+@@ -2985,6 +2989,7 @@
+ }
+
+ set_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
++ cfg->escan_info.run = brcmf_run_escan;
+ err = brcmf_do_escan(cfg, wiphy, ifp, request);
+ if (err) {
+ clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
+@@ -3152,7 +3157,9 @@
+ }
+
+ #ifdef CONFIG_NL80211_TESTMODE
+-static int brcmf_cfg80211_testmode(struct wiphy *wiphy, void *data, int len)
++static int brcmf_cfg80211_testmode(struct wiphy *wiphy,
++ struct wireless_dev *wdev,
++ void *data, int len)
+ {
+ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+ struct net_device *ndev = cfg_to_ndev(cfg);
+@@ -3982,6 +3989,7 @@
+ struct brcmf_fil_af_params_le *af_params;
+ bool ack;
+ s32 chan_nr;
++ u32 freq;
+
+ brcmf_dbg(TRACE, "Enter\n");
+
+@@ -3994,6 +4002,8 @@
+ return -EPERM;
+ }
+
++ vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
++
+ if (ieee80211_is_probe_resp(mgmt->frame_control)) {
+ /* Right now the only reason to get a probe response */
+ /* is for p2p listen response or for p2p GO from */
+@@ -4009,7 +4019,6 @@
+ ie_offset = DOT11_MGMT_HDR_LEN +
+ DOT11_BCN_PRB_FIXED_LEN;
+ ie_len = len - ie_offset;
+- vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
+ if (vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif)
+ vif = cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif;
+ err = brcmf_vif_set_mgmt_ie(vif,
+@@ -4033,16 +4042,22 @@
+ memcpy(&af_params->bssid[0], &mgmt->bssid[0], ETH_ALEN);
+ /* Add the length exepted for 802.11 header */
+ action_frame->len = cpu_to_le16(len - DOT11_MGMT_HDR_LEN);
+- /* Add the channel */
+- chan_nr = ieee80211_frequency_to_channel(chan->center_freq);
++ /* Add the channel. Use the one specified as parameter if any or
++ * the current one (got from the firmware) otherwise
++ */
++ if (chan)
++ freq = chan->center_freq;
++ else
++ brcmf_fil_cmd_int_get(vif->ifp, BRCMF_C_GET_CHANNEL,
++ &freq);
++ chan_nr = ieee80211_frequency_to_channel(freq);
+ af_params->channel = cpu_to_le32(chan_nr);
+
+ memcpy(action_frame->data, &buf[DOT11_MGMT_HDR_LEN],
+ le16_to_cpu(action_frame->len));
+
+ brcmf_dbg(TRACE, "Action frame, cookie=%lld, len=%d, freq=%d\n",
+- *cookie, le16_to_cpu(action_frame->len),
+- chan->center_freq);
++ *cookie, le16_to_cpu(action_frame->len), freq);
+
+ ack = brcmf_p2p_send_action_frame(cfg, cfg_to_ndev(cfg),
+ af_params);
+@@ -4115,6 +4130,53 @@
+ clear_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
+ }
+
++static int brcmf_convert_nl80211_tdls_oper(enum nl80211_tdls_operation oper)
++{
++ int ret;
++
++ switch (oper) {
++ case NL80211_TDLS_DISCOVERY_REQ:
++ ret = BRCMF_TDLS_MANUAL_EP_DISCOVERY;
++ break;
++ case NL80211_TDLS_SETUP:
++ ret = BRCMF_TDLS_MANUAL_EP_CREATE;
++ break;
++ case NL80211_TDLS_TEARDOWN:
++ ret = BRCMF_TDLS_MANUAL_EP_DELETE;
++ break;
++ default:
++ brcmf_err("unsupported operation: %d\n", oper);
++ ret = -EOPNOTSUPP;
++ }
++ return ret;
++}
++
++static int brcmf_cfg80211_tdls_oper(struct wiphy *wiphy,
++ struct net_device *ndev, u8 *peer,
++ enum nl80211_tdls_operation oper)
++{
++ struct brcmf_if *ifp;
++ struct brcmf_tdls_iovar_le info;
++ int ret = 0;
++
++ ret = brcmf_convert_nl80211_tdls_oper(oper);
++ if (ret < 0)
++ return ret;
++
++ ifp = netdev_priv(ndev);
++ memset(&info, 0, sizeof(info));
++ info.mode = (u8)ret;
++ if (peer)
++ memcpy(info.ea, peer, ETH_ALEN);
++
++ ret = brcmf_fil_iovar_data_set(ifp, "tdls_endpoint",
++ &info, sizeof(info));
++ if (ret < 0)
++ brcmf_err("tdls_endpoint iovar failed: ret=%d\n", ret);
++
++ return ret;
++}
++
+ static struct cfg80211_ops wl_cfg80211_ops = {
+ .add_virtual_intf = brcmf_cfg80211_add_iface,
+ .del_virtual_intf = brcmf_cfg80211_del_iface,
+@@ -4153,9 +4215,8 @@
+ .stop_p2p_device = brcmf_p2p_stop_device,
+ .crit_proto_start = brcmf_cfg80211_crit_proto_start,
+ .crit_proto_stop = brcmf_cfg80211_crit_proto_stop,
+-#ifdef CONFIG_NL80211_TESTMODE
+- .testmode_cmd = brcmf_cfg80211_testmode
+-#endif
++ .tdls_oper = brcmf_cfg80211_tdls_oper,
++ CFG80211_TESTMODE_CMD(brcmf_cfg80211_testmode)
+ };
+
+ static s32 brcmf_nl80211_iftype_to_mode(enum nl80211_iftype type)
+@@ -4276,7 +4337,8 @@
+ wiphy->n_cipher_suites = ARRAY_SIZE(__wl_cipher_suites);
+ wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT |
+ WIPHY_FLAG_OFFCHAN_TX |
+- WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
++ WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
++ WIPHY_FLAG_SUPPORTS_TDLS;
+ wiphy->mgmt_stypes = brcmf_txrx_stypes;
+ wiphy->max_remain_on_channel_duration = 5000;
+ brcmf_wiphy_pno_params(wiphy);
+@@ -4298,9 +4360,6 @@
+ {
+ struct brcmf_cfg80211_vif *vif;
+
+- if (cfg->vif_cnt == BRCMF_IFACE_MAX_CNT)
+- return ERR_PTR(-ENOSPC);
+-
+ brcmf_dbg(TRACE, "allocating virtual interface (size=%zu)\n",
+ sizeof(*vif));
+ vif = kzalloc(sizeof(*vif), GFP_KERNEL);
+@@ -4317,21 +4376,25 @@
+ brcmf_init_prof(&vif->profile);
+
+ list_add_tail(&vif->list, &cfg->vif_list);
+- cfg->vif_cnt++;
+ return vif;
+ }
+
+-void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_cfg80211_vif *vif)
++void brcmf_free_vif(struct brcmf_cfg80211_vif *vif)
+ {
+ list_del(&vif->list);
+- cfg->vif_cnt--;
+-
+ kfree(vif);
+- if (!cfg->vif_cnt) {
+- wiphy_unregister(cfg->wiphy);
+- wiphy_free(cfg->wiphy);
+- }
++}
++
++void brcmf_cfg80211_free_netdev(struct net_device *ndev)
++{
++ struct brcmf_cfg80211_vif *vif;
++ struct brcmf_if *ifp;
++
++ ifp = netdev_priv(ndev);
++ vif = ifp->vif;
++
++ brcmf_free_vif(vif);
++ free_netdev(ndev);
+ }
+
+ static bool brcmf_is_linkup(const struct brcmf_event_msg *e)
+@@ -4897,6 +4960,12 @@
+ goto cfg80211_p2p_attach_out;
+ }
+
++ err = brcmf_fil_iovar_int_set(ifp, "tdls_enable", 1);
++ if (err) {
++ brcmf_dbg(INFO, "TDLS not enabled (%d)\n", err);
++ wiphy->flags &= ~WIPHY_FLAG_SUPPORTS_TDLS;
++ }
++
+ err = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_VERSION,
+ &io_type);
+ if (err) {
+@@ -4912,20 +4981,20 @@
+ wl_deinit_priv(cfg);
+
+ cfg80211_attach_out:
+- brcmf_free_vif(cfg, vif);
++ brcmf_free_vif(vif);
+ return NULL;
+ }
+
+ void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg)
+ {
+- struct brcmf_cfg80211_vif *vif;
+- struct brcmf_cfg80211_vif *tmp;
++ if (!cfg)
++ return;
+
+- wl_deinit_priv(cfg);
++ WARN_ON(!list_empty(&cfg->vif_list));
++ wiphy_unregister(cfg->wiphy);
+ brcmf_btcoex_detach(cfg);
+- list_for_each_entry_safe(vif, tmp, &cfg->vif_list, list) {
+- brcmf_free_vif(cfg, vif);
+- }
++ wl_deinit_priv(cfg);
++ wiphy_free(cfg->wiphy);
+ }
+
+ static s32
+@@ -5020,7 +5089,8 @@
+ }
+
+
+-static s32 brcmf_construct_reginfo(struct brcmf_cfg80211_info *cfg, u32 bw_cap)
++static s32 brcmf_construct_reginfo(struct brcmf_cfg80211_info *cfg,
++ u32 bw_cap[])
+ {
+ struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
+ struct ieee80211_channel *band_chan_arr;
+@@ -5033,7 +5103,6 @@
+ enum ieee80211_band band;
+ u32 channel;
+ u32 *n_cnt;
+- bool ht40_allowed;
+ u32 index;
+ u32 ht40_flag;
+ bool update;
+@@ -5066,18 +5135,17 @@
+ array_size = ARRAY_SIZE(__wl_2ghz_channels);
+ n_cnt = &__wl_band_2ghz.n_channels;
+ band = IEEE80211_BAND_2GHZ;
+- ht40_allowed = (bw_cap == WLC_N_BW_40ALL);
+ } else if (ch.band == BRCMU_CHAN_BAND_5G) {
+ band_chan_arr = __wl_5ghz_a_channels;
+ array_size = ARRAY_SIZE(__wl_5ghz_a_channels);
+ n_cnt = &__wl_band_5ghz_a.n_channels;
+ band = IEEE80211_BAND_5GHZ;
+- ht40_allowed = !(bw_cap == WLC_N_BW_20ALL);
+ } else {
+- brcmf_err("Invalid channel Sepc. 0x%x.\n", ch.chspec);
++ brcmf_err("Invalid channel Spec. 0x%x.\n", ch.chspec);
+ continue;
+ }
+- if (!ht40_allowed && ch.bw == BRCMU_CHAN_BW_40)
++ if (!(bw_cap[band] & WLC_BW_40MHZ_BIT) &&
++ ch.bw == BRCMU_CHAN_BW_40)
+ continue;
+ update = false;
+ for (j = 0; (j < *n_cnt && (*n_cnt < array_size)); j++) {
+@@ -5095,7 +5163,10 @@
+ ieee80211_channel_to_frequency(ch.chnum, band);
+ band_chan_arr[index].hw_value = ch.chnum;
+
+- if (ch.bw == BRCMU_CHAN_BW_40 && ht40_allowed) {
++ brcmf_err("channel %d: f=%d bw=%d sb=%d\n",
++ ch.chnum, band_chan_arr[index].center_freq,
++ ch.bw, ch.sb);
++ if (ch.bw == BRCMU_CHAN_BW_40) {
+ /* assuming the order is HT20, HT40 Upper,
+ * HT40 lower from chanspecs
+ */
+@@ -5146,6 +5217,46 @@
+ return err;
+ }
+
++static void brcmf_get_bwcap(struct brcmf_if *ifp, u32 bw_cap[])
++{
++ u32 band, mimo_bwcap;
++ int err;
++
++ band = WLC_BAND_2G;
++ err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &band);
++ if (!err) {
++ bw_cap[IEEE80211_BAND_2GHZ] = band;
++ band = WLC_BAND_5G;
++ err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &band);
++ if (!err) {
++ bw_cap[IEEE80211_BAND_5GHZ] = band;
++ return;
++ }
++ WARN_ON(1);
++ return;
++ }
++ brcmf_dbg(INFO, "fallback to mimo_bw_cap info\n");
++ mimo_bwcap = 0;
++ err = brcmf_fil_iovar_int_get(ifp, "mimo_bw_cap", &mimo_bwcap);
++ if (err)
++ /* assume 20MHz if firmware does not give a clue */
++ mimo_bwcap = WLC_N_BW_20ALL;
++
++ switch (mimo_bwcap) {
++ case WLC_N_BW_40ALL:
++ bw_cap[IEEE80211_BAND_2GHZ] |= WLC_BW_40MHZ_BIT;
++ /* fall-thru */
++ case WLC_N_BW_20IN2G_40IN5G:
++ bw_cap[IEEE80211_BAND_5GHZ] |= WLC_BW_40MHZ_BIT;
++ /* fall-thru */
++ case WLC_N_BW_20ALL:
++ bw_cap[IEEE80211_BAND_2GHZ] |= WLC_BW_20MHZ_BIT;
++ bw_cap[IEEE80211_BAND_5GHZ] |= WLC_BW_20MHZ_BIT;
++ break;
++ default:
++ brcmf_err("invalid mimo_bw_cap value\n");
++ }
++}
+
+ static s32 brcmf_update_wiphybands(struct brcmf_cfg80211_info *cfg)
+ {
+@@ -5154,13 +5265,13 @@
+ s32 phy_list;
+ u32 band_list[3];
+ u32 nmode;
+- u32 bw_cap = 0;
++ u32 bw_cap[2] = { 0, 0 };
+ s8 phy;
+ s32 err;
+ u32 nband;
+ s32 i;
+- struct ieee80211_supported_band *bands[IEEE80211_NUM_BANDS];
+- s32 index;
++ struct ieee80211_supported_band *bands[2] = { NULL, NULL };
++ struct ieee80211_supported_band *band;
+
+ err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_PHYLIST,
+ &phy_list, sizeof(phy_list));
+@@ -5186,11 +5297,10 @@
+ if (err) {
+ brcmf_err("nmode error (%d)\n", err);
+ } else {
+- err = brcmf_fil_iovar_int_get(ifp, "mimo_bw_cap", &bw_cap);
+- if (err)
+- brcmf_err("mimo_bw_cap error (%d)\n", err);
++ brcmf_get_bwcap(ifp, bw_cap);
+ }
+- brcmf_dbg(INFO, "nmode=%d, mimo_bw_cap=%d\n", nmode, bw_cap);
++ brcmf_dbg(INFO, "nmode=%d, bw_cap=(%d, %d)\n", nmode,
++ bw_cap[IEEE80211_BAND_2GHZ], bw_cap[IEEE80211_BAND_5GHZ]);
+
+ err = brcmf_construct_reginfo(cfg, bw_cap);
+ if (err) {
+@@ -5199,40 +5309,33 @@
+ }
+
+ nband = band_list[0];
+- memset(bands, 0, sizeof(bands));
+
+ for (i = 1; i <= nband && i < ARRAY_SIZE(band_list); i++) {
+- index = -1;
++ band = NULL;
+ if ((band_list[i] == WLC_BAND_5G) &&
+- (__wl_band_5ghz_a.n_channels > 0)) {
+- index = IEEE80211_BAND_5GHZ;
+- bands[index] = &__wl_band_5ghz_a;
+- if ((bw_cap == WLC_N_BW_40ALL) ||
+- (bw_cap == WLC_N_BW_20IN2G_40IN5G))
+- bands[index]->ht_cap.cap |=
+- IEEE80211_HT_CAP_SGI_40;
+- } else if ((band_list[i] == WLC_BAND_2G) &&
+- (__wl_band_2ghz.n_channels > 0)) {
+- index = IEEE80211_BAND_2GHZ;
+- bands[index] = &__wl_band_2ghz;
+- if (bw_cap == WLC_N_BW_40ALL)
+- bands[index]->ht_cap.cap |=
+- IEEE80211_HT_CAP_SGI_40;
+- }
+-
+- if ((index >= 0) && nmode) {
+- bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
+- bands[index]->ht_cap.cap |= IEEE80211_HT_CAP_DSSSCCK40;
+- bands[index]->ht_cap.ht_supported = true;
+- bands[index]->ht_cap.ampdu_factor =
+- IEEE80211_HT_MAX_AMPDU_64K;
+- bands[index]->ht_cap.ampdu_density =
+- IEEE80211_HT_MPDU_DENSITY_16;
+- /* An HT shall support all EQM rates for one spatial
+- * stream
+- */
+- bands[index]->ht_cap.mcs.rx_mask[0] = 0xff;
+- }
++ (__wl_band_5ghz_a.n_channels > 0))
++ band = &__wl_band_5ghz_a;
++ else if ((band_list[i] == WLC_BAND_2G) &&
++ (__wl_band_2ghz.n_channels > 0))
++ band = &__wl_band_2ghz;
++ else
++ continue;
++
++ if (bw_cap[band->band] & WLC_BW_40MHZ_BIT) {
++ band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
++ band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
++ }
++ band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
++ band->ht_cap.cap |= IEEE80211_HT_CAP_DSSSCCK40;
++ band->ht_cap.ht_supported = true;
++ band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
++ band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
++ /* An HT shall support all EQM rates for one spatial
++ * stream
++ */
++ band->ht_cap.mcs.rx_mask[0] = 0xff;
++ band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
++ bands[band->band] = band;
+ }
+
+ wiphy = cfg_to_wiphy(cfg);
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h 2014-05-15 20:34:00.582032485 +0200
+@@ -412,7 +412,6 @@
+ struct work_struct escan_timeout_work;
+ u8 *escan_ioctl_buf;
+ struct list_head vif_list;
+- u8 vif_cnt;
+ struct brcmf_cfg80211_vif_event vif_event;
+ struct completion vif_disabled;
+ struct brcmu_d11inf d11inf;
+@@ -487,8 +486,7 @@
+ struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
+ enum nl80211_iftype type,
+ bool pm_block);
+-void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_cfg80211_vif *vif);
++void brcmf_free_vif(struct brcmf_cfg80211_vif *vif);
+
+ s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
+ const u8 *vndr_ie_buf, u32 vndr_ie_len);
+@@ -507,5 +505,6 @@
+ bool fw_abort);
+ void brcmf_set_mpc(struct brcmf_if *ndev, int mpc);
+ void brcmf_abort_scanning(struct brcmf_cfg80211_info *cfg);
++void brcmf_cfg80211_free_netdev(struct net_device *ndev);
+
+ #endif /* _wl_cfg80211_h_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c 2014-05-15 20:34:00.582032485 +0200
+@@ -679,27 +679,6 @@
+ return mode == BCMA_CLKMODE_FAST;
+ }
+
+-void ai_pci_up(struct si_pub *sih)
+-{
+- struct si_info *sii;
+-
+- sii = container_of(sih, struct si_info, pub);
+-
+- if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
+- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
+-}
+-
+-/* Unconfigure and/or apply various WARs when going down */
+-void ai_pci_down(struct si_pub *sih)
+-{
+- struct si_info *sii;
+-
+- sii = container_of(sih, struct si_info, pub);
+-
+- if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
+- bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
+-}
+-
+ /* Enable BT-COEX & Ex-PA for 4313 */
+ void ai_epa_4313war(struct si_pub *sih)
+ {
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h 2014-05-15 20:34:00.582032485 +0200
+@@ -172,22 +172,19 @@
+
+
+ /* AMBA Interconnect exported externs */
+-extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
++u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
+
+ /* === exported functions === */
+-extern struct si_pub *ai_attach(struct bcma_bus *pbus);
+-extern void ai_detach(struct si_pub *sih);
+-extern uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
+-extern void ai_clkctl_init(struct si_pub *sih);
+-extern u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
+-extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
+-extern bool ai_deviceremoved(struct si_pub *sih);
+-
+-extern void ai_pci_down(struct si_pub *sih);
+-extern void ai_pci_up(struct si_pub *sih);
++struct si_pub *ai_attach(struct bcma_bus *pbus);
++void ai_detach(struct si_pub *sih);
++uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val);
++void ai_clkctl_init(struct si_pub *sih);
++u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih);
++bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
++bool ai_deviceremoved(struct si_pub *sih);
+
+ /* Enable Ex-PA for 4313 */
+-extern void ai_epa_4313war(struct si_pub *sih);
++void ai_epa_4313war(struct si_pub *sih);
+
+ static inline u32 ai_get_cccaps(struct si_pub *sih)
+ {
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c 2014-05-15 20:34:00.582032485 +0200
+@@ -900,7 +900,7 @@
+ if (supr_status) {
+ update_rate = false;
+ if (supr_status == TX_STATUS_SUPR_BADCH) {
+- brcms_err(wlc->hw->d11core,
++ brcms_dbg_ht(wlc->hw->d11core,
+ "%s: Pkt tx suppressed, illegal channel possibly %d\n",
+ __func__, CHSPEC_CHANNEL(
+ wlc->default_bss->chanspec));
+@@ -928,9 +928,9 @@
+ }
+ } else if (txs->phyerr) {
+ update_rate = false;
+- brcms_err(wlc->hw->d11core,
+- "%s: ampdu tx phy error (0x%x)\n",
+- __func__, txs->phyerr);
++ brcms_dbg_ht(wlc->hw->d11core,
++ "%s: ampdu tx phy error (0x%x)\n",
++ __func__, txs->phyerr);
+ }
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/ampdu.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/ampdu.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/ampdu.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/ampdu.h 2014-05-15 20:34:00.582032485 +0200
+@@ -37,17 +37,17 @@
+ u16 dma_len;
+ };
+
+-extern void brcms_c_ampdu_reset_session(struct brcms_ampdu_session *session,
+- struct brcms_c_info *wlc);
+-extern int brcms_c_ampdu_add_frame(struct brcms_ampdu_session *session,
+- struct sk_buff *p);
+-extern void brcms_c_ampdu_finalize(struct brcms_ampdu_session *session);
++void brcms_c_ampdu_reset_session(struct brcms_ampdu_session *session,
++ struct brcms_c_info *wlc);
++int brcms_c_ampdu_add_frame(struct brcms_ampdu_session *session,
++ struct sk_buff *p);
++void brcms_c_ampdu_finalize(struct brcms_ampdu_session *session);
+
+-extern struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc);
+-extern void brcms_c_ampdu_detach(struct ampdu_info *ampdu);
+-extern void brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
+- struct sk_buff *p, struct tx_status *txs);
+-extern void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc);
+-extern void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu);
++struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc);
++void brcms_c_ampdu_detach(struct ampdu_info *ampdu);
++void brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
++ struct sk_buff *p, struct tx_status *txs);
++void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc);
++void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu);
+
+ #endif /* _BRCM_AMPDU_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/antsel.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/antsel.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/antsel.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/antsel.h 2014-05-15 20:34:00.582032485 +0200
+@@ -17,13 +17,11 @@
+ #ifndef _BRCM_ANTSEL_H_
+ #define _BRCM_ANTSEL_H_
+
+-extern struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc);
+-extern void brcms_c_antsel_detach(struct antsel_info *asi);
+-extern void brcms_c_antsel_init(struct antsel_info *asi);
+-extern void brcms_c_antsel_antcfg_get(struct antsel_info *asi, bool usedef,
+- bool sel,
+- u8 id, u8 fbid, u8 *antcfg,
+- u8 *fbantcfg);
+-extern u8 brcms_c_antsel_antsel2id(struct antsel_info *asi, u16 antsel);
++struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc);
++void brcms_c_antsel_detach(struct antsel_info *asi);
++void brcms_c_antsel_init(struct antsel_info *asi);
++void brcms_c_antsel_antcfg_get(struct antsel_info *asi, bool usedef, bool sel,
++ u8 id, u8 fbid, u8 *antcfg, u8 *fbantcfg);
++u8 brcms_c_antsel_antsel2id(struct antsel_info *asi, u16 antsel);
+
+ #endif /* _BRCM_ANTSEL_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/channel.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/channel.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/channel.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/channel.c 2014-05-15 20:34:00.594032572 +0200
+@@ -684,7 +684,8 @@
+ continue;
+
+ if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {
+- rule = freq_reg_info(wiphy, ch->center_freq);
++ rule = freq_reg_info(wiphy,
++ MHZ_TO_KHZ(ch->center_freq));
+ if (IS_ERR(rule))
+ continue;
+
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/channel.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/channel.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/channel.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/channel.h 2014-05-15 20:34:00.594032572 +0200
+@@ -32,20 +32,16 @@
+
+ #define BRCMS_DFS_EU (BRCMS_DFS_TPC | BRCMS_RADAR_TYPE_EU) /* Flag for DFS EU */
+
+-extern struct brcms_cm_info *
+-brcms_c_channel_mgr_attach(struct brcms_c_info *wlc);
++struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc);
+
+-extern void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm);
++void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm);
+
+-extern bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm,
+- u16 chspec);
++bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm, u16 chspec);
+
+-extern void brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm,
+- u16 chanspec,
+- struct txpwr_limits *txpwr);
+-extern void brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm,
+- u16 chanspec,
+- u8 local_constraint_qdbm);
+-extern void brcms_c_regd_init(struct brcms_c_info *wlc);
++void brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm, u16 chanspec,
++ struct txpwr_limits *txpwr);
++void brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm, u16 chanspec,
++ u8 local_constraint_qdbm);
++void brcms_c_regd_init(struct brcms_c_info *wlc);
+
+ #endif /* _WLC_CHANNEL_H */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/debug.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/debug.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/debug.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/debug.c 2014-05-15 20:34:00.594032572 +0200
+@@ -56,7 +56,7 @@
+
+ drvr->dbgfs_dir = debugfs_create_dir(
+ dev_name(&drvr->wlc->hw->d11core->dev), root_folder);
+- return PTR_RET(drvr->dbgfs_dir);
++ return PTR_ERR_OR_ZERO(drvr->dbgfs_dir);
+ }
+
+ void brcms_debugfs_detach(struct brcms_pub *drvr)
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c 2014-05-15 20:34:00.602032629 +0200
+@@ -457,6 +457,8 @@
+ if (err != 0)
+ brcms_err(wl->wlc->hw->d11core, "%s: brcms_up() returned %d\n",
+ __func__, err);
++
++ bcma_core_pci_power_save(wl->wlc->hw->d11core->bus, true);
+ return err;
+ }
+
+@@ -479,6 +481,8 @@
+ return;
+ }
+
++ bcma_core_pci_power_save(wl->wlc->hw->d11core->bus, false);
++
+ /* put driver in down state */
+ spin_lock_bh(&wl->lock);
+ brcms_down(wl);
+@@ -1067,7 +1071,6 @@
+ hw->max_rates = 2; /* Primary rate and 1 fallback rate */
+
+ /* channel change time is dependent on chip and band */
+- hw->channel_change_time = 7 * 1000;
+ hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
+ BIT(NL80211_IFTYPE_AP) |
+ BIT(NL80211_IFTYPE_ADHOC);
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.h 2014-05-15 20:34:00.602032629 +0200
+@@ -88,26 +88,26 @@
+ };
+
+ /* misc callbacks */
+-extern void brcms_init(struct brcms_info *wl);
+-extern uint brcms_reset(struct brcms_info *wl);
+-extern void brcms_intrson(struct brcms_info *wl);
+-extern u32 brcms_intrsoff(struct brcms_info *wl);
+-extern void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask);
+-extern int brcms_up(struct brcms_info *wl);
+-extern void brcms_down(struct brcms_info *wl);
+-extern void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
+- bool state, int prio);
+-extern bool brcms_rfkill_set_hw_state(struct brcms_info *wl);
++void brcms_init(struct brcms_info *wl);
++uint brcms_reset(struct brcms_info *wl);
++void brcms_intrson(struct brcms_info *wl);
++u32 brcms_intrsoff(struct brcms_info *wl);
++void brcms_intrsrestore(struct brcms_info *wl, u32 macintmask);
++int brcms_up(struct brcms_info *wl);
++void brcms_down(struct brcms_info *wl);
++void brcms_txflowcontrol(struct brcms_info *wl, struct brcms_if *wlif,
++ bool state, int prio);
++bool brcms_rfkill_set_hw_state(struct brcms_info *wl);
+
+ /* timer functions */
+-extern struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
+- void (*fn) (void *arg), void *arg,
+- const char *name);
+-extern void brcms_free_timer(struct brcms_timer *timer);
+-extern void brcms_add_timer(struct brcms_timer *timer, uint ms, int periodic);
+-extern bool brcms_del_timer(struct brcms_timer *timer);
+-extern void brcms_dpc(unsigned long data);
+-extern void brcms_timer(struct brcms_timer *t);
+-extern void brcms_fatal_error(struct brcms_info *wl);
++struct brcms_timer *brcms_init_timer(struct brcms_info *wl,
++ void (*fn) (void *arg), void *arg,
++ const char *name);
++void brcms_free_timer(struct brcms_timer *timer);
++void brcms_add_timer(struct brcms_timer *timer, uint ms, int periodic);
++bool brcms_del_timer(struct brcms_timer *timer);
++void brcms_dpc(unsigned long data);
++void brcms_timer(struct brcms_timer *t);
++void brcms_fatal_error(struct brcms_info *wl);
+
+ #endif /* _BRCM_MAC80211_IF_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/main.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/main.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/main.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/main.c 2014-05-15 20:34:00.618032744 +0200
+@@ -882,8 +882,8 @@
+ mcl = le16_to_cpu(txh->MacTxControlLow);
+
+ if (txs->phyerr)
+- brcms_err(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
+- txs->phyerr, txh->MainRates);
++ brcms_dbg_tx(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
++ txs->phyerr, txh->MainRates);
+
+ if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
+ brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
+@@ -1906,14 +1906,14 @@
+
+ /* If macaddr exists, use it (Sromrev4, CIS, ...). */
+ if (!is_zero_ether_addr(sprom->il0mac)) {
+- memcpy(etheraddr, sprom->il0mac, 6);
++ memcpy(etheraddr, sprom->il0mac, ETH_ALEN);
+ return;
+ }
+
+ if (wlc_hw->_nbands > 1)
+- memcpy(etheraddr, sprom->et1mac, 6);
++ memcpy(etheraddr, sprom->et1mac, ETH_ALEN);
+ else
+- memcpy(etheraddr, sprom->il0mac, 6);
++ memcpy(etheraddr, sprom->il0mac, ETH_ALEN);
+ }
+
+ /* power both the pll and external oscillator on/off */
+@@ -4652,7 +4652,9 @@
+ wlc->band->phyrev = wlc_hw->band->phyrev;
+ wlc->band->radioid = wlc_hw->band->radioid;
+ wlc->band->radiorev = wlc_hw->band->radiorev;
+-
++ brcms_dbg_info(core, "wl%d: phy %u/%u radio %x/%u\n", unit,
++ wlc->band->phytype, wlc->band->phyrev,
++ wlc->band->radioid, wlc->band->radiorev);
+ /* default contention windows size limits */
+ wlc_hw->band->CWmin = APHY_CWMIN;
+ wlc_hw->band->CWmax = PHY_CWMAX;
+@@ -4667,7 +4669,7 @@
+ brcms_c_coredisable(wlc_hw);
+
+ /* Match driver "down" state */
+- ai_pci_down(wlc_hw->sih);
++ bcma_core_pci_down(wlc_hw->d11core->bus);
+
+ /* turn off pll and xtal to match driver "down" state */
+ brcms_b_xtal(wlc_hw, OFF);
+@@ -5010,12 +5012,12 @@
+ */
+ if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
+ /* put SB PCI in down state again */
+- ai_pci_down(wlc_hw->sih);
++ bcma_core_pci_down(wlc_hw->d11core->bus);
+ brcms_b_xtal(wlc_hw, OFF);
+ return -ENOMEDIUM;
+ }
+
+- ai_pci_up(wlc_hw->sih);
++ bcma_core_pci_up(wlc_hw->d11core->bus);
+
+ /* reset the d11 core */
+ brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
+@@ -5212,7 +5214,7 @@
+
+ /* turn off primary xtal and pll */
+ if (!wlc_hw->noreset) {
+- ai_pci_down(wlc_hw->sih);
++ bcma_core_pci_down(wlc_hw->d11core->bus);
+ brcms_b_xtal(wlc_hw, OFF);
+ }
+ }
+@@ -5693,7 +5695,7 @@
+ return true;
+ if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
+ return true;
+- if (device == BCM4313_D11N2G_ID)
++ if (device == BCM4313_D11N2G_ID || device == BCM4313_CHIP_ID)
+ return true;
+ if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
+ return true;
+@@ -7106,7 +7108,6 @@
+ struct sk_buff *p,
+ struct ieee80211_rx_status *rx_status)
+ {
+- int preamble;
+ int channel;
+ u32 rspec;
+ unsigned char *plcp;
+@@ -7189,7 +7190,6 @@
+ rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
+
+ /* Determine short preamble and rate_idx */
+- preamble = 0;
+ if (is_cck_rate(rspec)) {
+ if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
+ rx_status->flag |= RX_FLAG_SHORTPRE;
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/main.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/main.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/main.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/main.h 2014-05-15 20:34:00.618032744 +0200
+@@ -616,66 +616,54 @@
+ struct brcms_bss_info *current_bss;
+ };
+
+-extern int brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo,
+- struct sk_buff *p);
+-extern int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
+- uint *blocks);
++int brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p);
++int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
++ uint *blocks);
+
+-extern int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config);
+-extern void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags);
+-extern u16 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
+- uint mac_len);
+-extern u32 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc,
+- u32 rspec,
+- bool use_rspec, u16 mimo_ctlchbw);
+-extern u16 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
+- u32 rts_rate,
+- u32 frame_rate,
+- u8 rts_preamble_type,
+- u8 frame_preamble_type, uint frame_len,
+- bool ba);
+-extern void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
+- struct ieee80211_sta *sta,
+- void (*dma_callback_fn));
+-extern void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend);
+-extern int brcms_c_set_nmode(struct brcms_c_info *wlc);
+-extern void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
+- u32 bcn_rate);
+-extern void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw,
+- u8 antsel_type);
+-extern void brcms_b_set_chanspec(struct brcms_hardware *wlc_hw,
+- u16 chanspec,
+- bool mute, struct txpwr_limits *txpwr);
+-extern void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset,
+- u16 v);
+-extern u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset);
+-extern void brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask,
+- u16 val, int bands);
+-extern void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags);
+-extern void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val);
+-extern void brcms_b_phy_reset(struct brcms_hardware *wlc_hw);
+-extern void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw);
+-extern void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw);
+-extern void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
+- u32 override_bit);
+-extern void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
+- u32 override_bit);
+-extern void brcms_b_write_template_ram(struct brcms_hardware *wlc_hw,
+- int offset, int len, void *buf);
+-extern u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate);
+-extern void brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw,
+- uint offset, const void *buf, int len,
+- u32 sel);
+-extern void brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset,
+- void *buf, int len, u32 sel);
+-extern void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode);
+-extern u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw);
+-extern void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk);
+-extern void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk);
+-extern void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on);
+-extern void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant);
+-extern void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw,
+- u8 stf_mode);
+-extern void brcms_c_init_scb(struct scb *scb);
++int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config);
++void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags);
++u16 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec, uint mac_len);
++u32 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
++ bool use_rspec, u16 mimo_ctlchbw);
++u16 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
++ u32 rts_rate, u32 frame_rate,
++ u8 rts_preamble_type, u8 frame_preamble_type,
++ uint frame_len, bool ba);
++void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
++ struct ieee80211_sta *sta, void (*dma_callback_fn));
++void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend);
++int brcms_c_set_nmode(struct brcms_c_info *wlc);
++void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc, u32 bcn_rate);
++void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type);
++void brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
++ bool mute, struct txpwr_limits *txpwr);
++void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v);
++u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset);
++void brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
++ int bands);
++void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags);
++void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val);
++void brcms_b_phy_reset(struct brcms_hardware *wlc_hw);
++void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw);
++void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw);
++void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
++ u32 override_bit);
++void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
++ u32 override_bit);
++void brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset,
++ int len, void *buf);
++u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate);
++void brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
++ const void *buf, int len, u32 sel);
++void brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset,
++ void *buf, int len, u32 sel);
++void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode);
++u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw);
++void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk);
++void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk);
++void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on);
++void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant);
++void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode);
++void brcms_c_init_scb(struct scb *scb);
+
+ #endif /* _BRCM_MAIN_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_hal.h 2014-05-15 20:34:00.670033120 +0200
+@@ -179,121 +179,106 @@
+ };
+
+
+-extern struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp);
+-extern struct brcms_phy_pub *wlc_phy_attach(struct shared_phy *sh,
+- struct bcma_device *d11core,
+- int bandtype, struct wiphy *wiphy);
+-extern void wlc_phy_detach(struct brcms_phy_pub *ppi);
+-
+-extern bool wlc_phy_get_phyversion(struct brcms_phy_pub *pih, u16 *phytype,
+- u16 *phyrev, u16 *radioid,
+- u16 *radiover);
+-extern bool wlc_phy_get_encore(struct brcms_phy_pub *pih);
+-extern u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih);
+-
+-extern void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *ppi, bool newstate);
+-extern void wlc_phy_hw_state_upd(struct brcms_phy_pub *ppi, bool newstate);
+-extern void wlc_phy_init(struct brcms_phy_pub *ppi, u16 chanspec);
+-extern void wlc_phy_watchdog(struct brcms_phy_pub *ppi);
+-extern int wlc_phy_down(struct brcms_phy_pub *ppi);
+-extern u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih);
+-extern void wlc_phy_cal_init(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_antsel_init(struct brcms_phy_pub *ppi, bool lut_init);
+-
+-extern void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi,
+- u16 chanspec);
+-extern u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi,
+- u16 newch);
+-extern u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi, u16 bw);
+-
+-extern int wlc_phy_rssi_compute(struct brcms_phy_pub *pih,
+- struct d11rxhdr *rxh);
+-extern void wlc_phy_por_inform(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_noise_sample_intr(struct brcms_phy_pub *ppi);
+-extern bool wlc_phy_bist_check_phy(struct brcms_phy_pub *ppi);
+-
+-extern void wlc_phy_set_deaf(struct brcms_phy_pub *ppi, bool user_flag);
+-
+-extern void wlc_phy_switch_radio(struct brcms_phy_pub *ppi, bool on);
+-extern void wlc_phy_anacore(struct brcms_phy_pub *ppi, bool on);
+-
+-
+-extern void wlc_phy_BSSinit(struct brcms_phy_pub *ppi, bool bonlyap, int rssi);
+-
+-extern void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi,
+- bool wide_filter);
+-extern void wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi, uint band,
+- struct brcms_chanvec *channels);
+-extern u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi,
+- uint band);
+-
+-extern void wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi, uint chan,
+- u8 *_min_, u8 *_max_, int rate);
+-extern void wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi,
+- uint chan, u8 *_max_, u8 *_min_);
+-extern void wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi,
+- uint band, s32 *, s32 *, u32 *);
+-extern void wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi,
+- struct txpwr_limits *,
+- u16 chanspec);
+-extern int wlc_phy_txpower_get(struct brcms_phy_pub *ppi, uint *qdbm,
+- bool *override);
+-extern int wlc_phy_txpower_set(struct brcms_phy_pub *ppi, uint qdbm,
+- bool override);
+-extern void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi,
+- struct txpwr_limits *);
+-extern bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi,
+- bool hwpwrctrl);
+-extern u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi);
+-extern u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi);
+-extern bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *pih);
+-
+-extern void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih, u8 txchain,
+- u8 rxchain);
+-extern void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih, u8 txchain,
+- u8 rxchain);
+-extern void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih, u8 *txchain,
+- u8 *rxchain);
+-extern u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih);
+-extern s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih,
+- u16 chanspec);
+-extern void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool val);
+-
+-extern void wlc_phy_cal_perical(struct brcms_phy_pub *ppi, u8 reason);
+-extern void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih, bool lock);
+-extern void wlc_phy_cal_papd_recal(struct brcms_phy_pub *ppi);
+-
+-extern void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val);
+-extern void wlc_phy_clear_tssi(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_hold_upd(struct brcms_phy_pub *ppi, u32 id, bool val);
+-extern void wlc_phy_mute_upd(struct brcms_phy_pub *ppi, bool val, u32 flags);
+-
+-extern void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi, u8 antsel_type);
+-
+-extern void wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi,
+- struct tx_power *power, uint channel);
+-
+-extern void wlc_phy_initcal_enable(struct brcms_phy_pub *pih, bool initcal);
+-extern bool wlc_phy_test_ison(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi,
+- u8 txpwr_percent);
+-extern void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih, bool war);
+-extern void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih,
+- bool bf_preempt);
+-extern void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi, u32 machwcap);
+-
+-extern void wlc_phy_runbist_config(struct brcms_phy_pub *ppi, bool start_end);
+-
+-extern void wlc_phy_freqtrack_start(struct brcms_phy_pub *ppi);
+-extern void wlc_phy_freqtrack_end(struct brcms_phy_pub *ppi);
+-
+-extern const u8 *wlc_phy_get_ofdm_rate_lookup(void);
+-
+-extern s8 wlc_phy_get_tx_power_offset_by_mcs(struct brcms_phy_pub *ppi,
+- u8 mcs_offset);
+-extern s8 wlc_phy_get_tx_power_offset(struct brcms_phy_pub *ppi, u8 tbl_offset);
++struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp);
++struct brcms_phy_pub *wlc_phy_attach(struct shared_phy *sh,
++ struct bcma_device *d11core, int bandtype,
++ struct wiphy *wiphy);
++void wlc_phy_detach(struct brcms_phy_pub *ppi);
++
++bool wlc_phy_get_phyversion(struct brcms_phy_pub *pih, u16 *phytype,
++ u16 *phyrev, u16 *radioid, u16 *radiover);
++bool wlc_phy_get_encore(struct brcms_phy_pub *pih);
++u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih);
++
++void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *ppi, bool newstate);
++void wlc_phy_hw_state_upd(struct brcms_phy_pub *ppi, bool newstate);
++void wlc_phy_init(struct brcms_phy_pub *ppi, u16 chanspec);
++void wlc_phy_watchdog(struct brcms_phy_pub *ppi);
++int wlc_phy_down(struct brcms_phy_pub *ppi);
++u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih);
++void wlc_phy_cal_init(struct brcms_phy_pub *ppi);
++void wlc_phy_antsel_init(struct brcms_phy_pub *ppi, bool lut_init);
++
++void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi, u16 chanspec);
++u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi);
++void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi, u16 newch);
++u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi);
++void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi, u16 bw);
++
++int wlc_phy_rssi_compute(struct brcms_phy_pub *pih, struct d11rxhdr *rxh);
++void wlc_phy_por_inform(struct brcms_phy_pub *ppi);
++void wlc_phy_noise_sample_intr(struct brcms_phy_pub *ppi);
++bool wlc_phy_bist_check_phy(struct brcms_phy_pub *ppi);
++
++void wlc_phy_set_deaf(struct brcms_phy_pub *ppi, bool user_flag);
++
++void wlc_phy_switch_radio(struct brcms_phy_pub *ppi, bool on);
++void wlc_phy_anacore(struct brcms_phy_pub *ppi, bool on);
++
++
++void wlc_phy_BSSinit(struct brcms_phy_pub *ppi, bool bonlyap, int rssi);
++
++void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi,
++ bool wide_filter);
++void wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi, uint band,
++ struct brcms_chanvec *channels);
++u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi, uint band);
++
++void wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi, uint chan, u8 *_min_,
++ u8 *_max_, int rate);
++void wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi, uint chan,
++ u8 *_max_, u8 *_min_);
++void wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi, uint band,
++ s32 *, s32 *, u32 *);
++void wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi, struct txpwr_limits *,
++ u16 chanspec);
++int wlc_phy_txpower_get(struct brcms_phy_pub *ppi, uint *qdbm, bool *override);
++int wlc_phy_txpower_set(struct brcms_phy_pub *ppi, uint qdbm, bool override);
++void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi,
++ struct txpwr_limits *);
++bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi);
++void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi, bool hwpwrctrl);
++u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi);
++u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi);
++bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *pih);
++
++void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain);
++void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain);
++void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih, u8 *txchain, u8 *rxchain);
++u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih);
++s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih, u16 chanspec);
++void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool val);
++
++void wlc_phy_cal_perical(struct brcms_phy_pub *ppi, u8 reason);
++void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *ppi);
++void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih, bool lock);
++void wlc_phy_cal_papd_recal(struct brcms_phy_pub *ppi);
++
++void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val);
++void wlc_phy_clear_tssi(struct brcms_phy_pub *ppi);
++void wlc_phy_hold_upd(struct brcms_phy_pub *ppi, u32 id, bool val);
++void wlc_phy_mute_upd(struct brcms_phy_pub *ppi, bool val, u32 flags);
++
++void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi, u8 antsel_type);
++
++void wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi,
++ struct tx_power *power, uint channel);
++
++void wlc_phy_initcal_enable(struct brcms_phy_pub *pih, bool initcal);
++bool wlc_phy_test_ison(struct brcms_phy_pub *ppi);
++void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi, u8 txpwr_percent);
++void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih, bool war);
++void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih, bool bf_preempt);
++void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi, u32 machwcap);
++
++void wlc_phy_runbist_config(struct brcms_phy_pub *ppi, bool start_end);
++
++void wlc_phy_freqtrack_start(struct brcms_phy_pub *ppi);
++void wlc_phy_freqtrack_end(struct brcms_phy_pub *ppi);
++
++const u8 *wlc_phy_get_ofdm_rate_lookup(void);
++
++s8 wlc_phy_get_tx_power_offset_by_mcs(struct brcms_phy_pub *ppi,
++ u8 mcs_offset);
++s8 wlc_phy_get_tx_power_offset(struct brcms_phy_pub *ppi, u8 tbl_offset);
+ #endif /* _BRCM_PHY_HAL_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_int.h 2014-05-15 20:34:00.670033120 +0200
+@@ -910,113 +910,103 @@
+ u8 do_init_g;
+ };
+
+-extern u16 read_phy_reg(struct brcms_phy *pi, u16 addr);
+-extern void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
+-extern void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
+-extern void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
+-extern void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
+-
+-extern u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
+-extern void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
+-extern void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
+-extern void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask,
+- u16 val);
+-extern void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask);
+-
+-extern void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
+-
+-extern void wlc_phyreg_enter(struct brcms_phy_pub *pih);
+-extern void wlc_phyreg_exit(struct brcms_phy_pub *pih);
+-extern void wlc_radioreg_enter(struct brcms_phy_pub *pih);
+-extern void wlc_radioreg_exit(struct brcms_phy_pub *pih);
+-
+-extern void wlc_phy_read_table(struct brcms_phy *pi,
+- const struct phytbl_info *ptbl_info,
+- u16 tblAddr, u16 tblDataHi,
+- u16 tblDatalo);
+-extern void wlc_phy_write_table(struct brcms_phy *pi,
+- const struct phytbl_info *ptbl_info,
+- u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
+-extern void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id,
+- uint tbl_offset, u16 tblAddr, u16 tblDataHi,
+- u16 tblDataLo);
+-extern void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val);
+-
+-extern void write_phy_channel_reg(struct brcms_phy *pi, uint val);
+-extern void wlc_phy_txpower_update_shm(struct brcms_phy *pi);
+-
+-extern u8 wlc_phy_nbits(s32 value);
+-extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
+-
+-extern uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
+- struct radio_20xx_regs *radioregs);
+-extern uint wlc_phy_init_radio_regs(struct brcms_phy *pi,
+- const struct radio_regs *radioregs,
+- u16 core_offset);
+-
+-extern void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi);
+-
+-extern void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on);
+-extern void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real,
+- s32 *eps_imag);
+-
+-extern void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi);
+-extern void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi);
+-
+-extern bool wlc_phy_attach_nphy(struct brcms_phy *pi);
+-extern bool wlc_phy_attach_lcnphy(struct brcms_phy *pi);
+-
+-extern void wlc_phy_detach_lcnphy(struct brcms_phy *pi);
+-
+-extern void wlc_phy_init_nphy(struct brcms_phy *pi);
+-extern void wlc_phy_init_lcnphy(struct brcms_phy *pi);
+-
+-extern void wlc_phy_cal_init_nphy(struct brcms_phy *pi);
+-extern void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi);
+-
+-extern void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi,
+- u16 chanspec);
+-extern void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi,
+- u16 chanspec);
+-extern void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi,
+- u16 chanspec);
+-extern int wlc_phy_channel2freq(uint channel);
+-extern int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
+-extern int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec);
+-
+-extern void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode);
+-extern s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi);
+-
+-extern void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi);
+-extern void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi);
+-extern void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi);
+-
+-extern void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index);
+-extern void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable);
+-extern void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi);
+-extern void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz,
+- u16 max_val, bool iqcalmode);
+-
+-extern void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan,
+- u8 *max_pwr, u8 rate_id);
+-extern void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
+- u8 rate_mcs_end,
+- u8 rate_ofdm_start);
+-extern void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power,
+- u8 rate_ofdm_start,
+- u8 rate_ofdm_end,
+- u8 rate_mcs_start);
+-
+-extern u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode);
+-extern s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode);
+-extern s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode);
+-extern s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode);
+-extern void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi);
+-extern void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel);
+-extern void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode);
+-extern void wlc_2064_vco_cal(struct brcms_phy *pi);
++u16 read_phy_reg(struct brcms_phy *pi, u16 addr);
++void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
++void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
++void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val);
++void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
++
++u16 read_radio_reg(struct brcms_phy *pi, u16 addr);
++void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
++void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
++void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val);
++void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask);
++
++void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val);
++
++void wlc_phyreg_enter(struct brcms_phy_pub *pih);
++void wlc_phyreg_exit(struct brcms_phy_pub *pih);
++void wlc_radioreg_enter(struct brcms_phy_pub *pih);
++void wlc_radioreg_exit(struct brcms_phy_pub *pih);
++
++void wlc_phy_read_table(struct brcms_phy *pi,
++ const struct phytbl_info *ptbl_info,
++ u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
++void wlc_phy_write_table(struct brcms_phy *pi,
++ const struct phytbl_info *ptbl_info,
++ u16 tblAddr, u16 tblDataHi, u16 tblDatalo);
++void wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset,
++ u16 tblAddr, u16 tblDataHi, u16 tblDataLo);
++void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val);
++
++void write_phy_channel_reg(struct brcms_phy *pi, uint val);
++void wlc_phy_txpower_update_shm(struct brcms_phy *pi);
++
++u8 wlc_phy_nbits(s32 value);
++void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
++
++uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
++ struct radio_20xx_regs *radioregs);
++uint wlc_phy_init_radio_regs(struct brcms_phy *pi,
++ const struct radio_regs *radioregs,
++ u16 core_offset);
++
++void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi);
++
++void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on);
++void wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag);
++
++void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi);
++void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi);
++
++bool wlc_phy_attach_nphy(struct brcms_phy *pi);
++bool wlc_phy_attach_lcnphy(struct brcms_phy *pi);
++
++void wlc_phy_detach_lcnphy(struct brcms_phy *pi);
++
++void wlc_phy_init_nphy(struct brcms_phy *pi);
++void wlc_phy_init_lcnphy(struct brcms_phy *pi);
++
++void wlc_phy_cal_init_nphy(struct brcms_phy *pi);
++void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi);
++
++void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi, u16 chanspec);
++void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi, u16 chanspec);
++void wlc_phy_chanspec_set_fixup_lcnphy(struct brcms_phy *pi, u16 chanspec);
++int wlc_phy_channel2freq(uint channel);
++int wlc_phy_chanspec_freq2bandrange_lpssn(uint);
++int wlc_phy_chanspec_bandrange_get(struct brcms_phy *, u16 chanspec);
++
++void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi, u16 mode);
++s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi);
++
++void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi);
++void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi);
++void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi);
++
++void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi, int index);
++void wlc_lcnphy_tx_pu(struct brcms_phy *pi, bool bEnable);
++void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi);
++void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi, s32 f_kHz, u16 max_val,
++ bool iqcalmode);
++
++void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi, uint chan,
++ u8 *max_pwr, u8 rate_id);
++void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power, u8 rate_mcs_start,
++ u8 rate_mcs_end, u8 rate_ofdm_start);
++void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power, u8 rate_ofdm_start,
++ u8 rate_ofdm_end, u8 rate_mcs_start);
++
++u16 wlc_lcnphy_tempsense(struct brcms_phy *pi, bool mode);
++s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi, bool mode);
++s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi, bool mode);
++s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi, bool mode);
++void wlc_phy_carrier_suppress_lcnphy(struct brcms_phy *pi);
++void wlc_lcnphy_crsuprs(struct brcms_phy *pi, int channel);
++void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode);
++void wlc_2064_vco_cal(struct brcms_phy *pi);
+
+-extern void wlc_phy_txpower_recalc_target(struct brcms_phy *pi);
++void wlc_phy_txpower_recalc_target(struct brcms_phy *pi);
+
+ #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
+ #define LCNPHY_TX_POWER_TABLE_SIZE 128
+@@ -1030,26 +1020,24 @@
+
+ #define LCNPHY_TX_PWR_CTRL_TEMPBASED 0xE001
+
+-extern void wlc_lcnphy_write_table(struct brcms_phy *pi,
+- const struct phytbl_info *pti);
+-extern void wlc_lcnphy_read_table(struct brcms_phy *pi,
+- struct phytbl_info *pti);
+-extern void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b);
+-extern void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq);
+-extern void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b);
+-extern u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi);
+-extern void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0,
+- u8 *eq0, u8 *fi0, u8 *fq0);
+-extern void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode);
+-extern void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode);
+-extern bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi);
+-extern void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi);
+-extern s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
+-extern void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr,
+- s8 *cck_pwr);
+-extern void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi);
++void wlc_lcnphy_write_table(struct brcms_phy *pi,
++ const struct phytbl_info *pti);
++void wlc_lcnphy_read_table(struct brcms_phy *pi, struct phytbl_info *pti);
++void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi, u16 a, u16 b);
++void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi, u16 didq);
++void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi, u16 *a, u16 *b);
++u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi);
++void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi, u8 *ei0, u8 *eq0, u8 *fi0,
++ u8 *fq0);
++void wlc_lcnphy_calib_modes(struct brcms_phy *pi, uint mode);
++void wlc_lcnphy_deaf_mode(struct brcms_phy *pi, bool mode);
++bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi);
++void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi);
++s32 wlc_lcnphy_tssi2dbm(s32 tssi, s32 a1, s32 b0, s32 b1);
++void wlc_lcnphy_get_tssi(struct brcms_phy *pi, s8 *ofdm_pwr, s8 *cck_pwr);
++void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi);
+
+-extern s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index);
++s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi, s32 gain_index);
+
+ #define NPHY_MAX_HPVGA1_INDEX 10
+ #define NPHY_DEF_HPVGA1_INDEXLIMIT 7
+@@ -1060,9 +1048,8 @@
+ u32 q_pwr;
+ };
+
+-extern void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi,
+- bool enable);
+-extern void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode);
++void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi, bool enable);
++void wlc_nphy_deaf_mode(struct brcms_phy *pi, bool mode);
+
+ #define wlc_phy_write_table_nphy(pi, pti) \
+ wlc_phy_write_table(pi, pti, 0x72, 0x74, 0x73)
+@@ -1076,10 +1063,10 @@
+ #define wlc_nphy_table_data_write(pi, w, v) \
+ wlc_phy_table_data_write((pi), (w), (v))
+
+-extern void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o,
+- u32 w, void *d);
+-extern void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32,
+- u32, const void *);
++void wlc_phy_table_read_nphy(struct brcms_phy *pi, u32, u32 l, u32 o, u32 w,
++ void *d);
++void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32, u32,
++ const void *);
+
+ #define PHY_IPA(pi) \
+ ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
+@@ -1089,73 +1076,67 @@
+ if (NREV_LT((pi)->pubpi.phy_rev, 3)) \
+ (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol))
+
+-extern void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
+-extern void wlc_phy_aci_reset_nphy(struct brcms_phy *pi);
+-extern void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en);
+-
+-extern u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan);
+-extern void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on);
+-
+-extern void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi);
+-
+-extern void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd);
+-extern s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi);
+-
+-extern u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val);
+-
+-extern void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
+- u16 num_samps, u8 wait_time,
+- u8 wait_for_crs);
+-
+-extern void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
+- struct nphy_iq_comp *comp);
+-extern void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi);
+-
+-extern void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih,
+- u8 rxcore_bitmask);
+-extern u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih);
+-
+-extern void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type);
+-extern void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi);
+-extern void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi);
+-extern void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi);
+-extern u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi);
+-
+-extern struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi);
+-extern int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi,
+- struct nphy_txgains target_gain,
+- bool full, bool m);
+-extern int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi,
+- struct nphy_txgains target_gain,
+- u8 type, bool d);
+-extern void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask,
+- s8 txpwrindex, bool res);
+-extern void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type);
+-extern int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type,
+- s32 *rssi_buf, u8 nsamps);
+-extern void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi);
+-extern int wlc_phy_aci_scan_nphy(struct brcms_phy *pi);
+-extern void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi,
+- s32 dBm_targetpower, bool debug);
+-extern int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val,
+- u8 mode, u8, bool);
+-extern void wlc_phy_stopplayback_nphy(struct brcms_phy *pi);
+-extern void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf,
+- u8 num_samps);
+-extern void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi);
++void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
++void wlc_phy_aci_reset_nphy(struct brcms_phy *pi);
++void wlc_phy_pa_override_nphy(struct brcms_phy *pi, bool en);
++
++u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi, uint chan);
++void wlc_phy_switch_radio_nphy(struct brcms_phy *pi, bool on);
++
++void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi);
++
++void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi, u8 cmd);
++s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi);
++
++u16 wlc_phy_classifier_nphy(struct brcms_phy *pi, u16 mask, u16 val);
++
++void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi, struct phy_iq_est *est,
++ u16 num_samps, u8 wait_time, u8 wait_for_crs);
++
++void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi, u8 write,
++ struct nphy_iq_comp *comp);
++void wlc_phy_aci_and_noise_reduction_nphy(struct brcms_phy *pi);
++
++void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih, u8 rxcore_bitmask);
++u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih);
++
++void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi, u8 ctrl_type);
++void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi);
++void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi);
++void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi);
++u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi);
++
++struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi);
++int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi,
++ struct nphy_txgains target_gain, bool full, bool m);
++int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi, struct nphy_txgains target_gain,
++ u8 type, bool d);
++void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi, u8 core_mask,
++ s8 txpwrindex, bool res);
++void wlc_phy_rssisel_nphy(struct brcms_phy *pi, u8 core, u8 rssi_type);
++int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi, u8 rssi_type,
++ s32 *rssi_buf, u8 nsamps);
++void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi);
++int wlc_phy_aci_scan_nphy(struct brcms_phy *pi);
++void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi, s32 dBm_targetpower,
++ bool debug);
++int wlc_phy_tx_tone_nphy(struct brcms_phy *pi, u32 f_kHz, u16 max_val, u8 mode,
++ u8, bool);
++void wlc_phy_stopplayback_nphy(struct brcms_phy *pi);
++void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi, s32 *qdBm_pwrbuf,
++ u8 num_samps);
++void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi);
+
+-extern int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi,
+- struct d11rxhdr *rxh);
++int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi, struct d11rxhdr *rxh);
+
+ #define NPHY_TESTPATTERN_BPHY_EVM 0
+ #define NPHY_TESTPATTERN_BPHY_RFCS 1
+
+-extern void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs);
++void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi, u8 rifs);
+
+ void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset,
+ s8 *ofdmoffset);
+-extern s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi,
+- u16 chanspec);
++s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec);
+
+-extern bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih);
++bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pih);
+ #endif /* _BRCM_PHY_INT_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c 2014-05-15 20:34:00.674033148 +0200
+@@ -1137,8 +1137,9 @@
+ gain0_15 = ((biq1 & 0xf) << 12) |
+ ((tia & 0xf) << 8) |
+ ((lna2 & 0x3) << 6) |
+- ((lna2 &
+- 0x3) << 4) | ((lna1 & 0x3) << 2) | ((lna1 & 0x3) << 0);
++ ((lna2 & 0x3) << 4) |
++ ((lna1 & 0x3) << 2) |
++ ((lna1 & 0x3) << 0);
+
+ mod_phy_reg(pi, 0x4b6, (0xffff << 0), gain0_15 << 0);
+ mod_phy_reg(pi, 0x4b7, (0xf << 0), gain16_19 << 0);
+@@ -1328,6 +1329,43 @@
+ return (iq_est.i_pwr + iq_est.q_pwr) / nsamples;
+ }
+
++static bool wlc_lcnphy_rx_iq_cal_gain(struct brcms_phy *pi, u16 biq1_gain,
++ u16 tia_gain, u16 lna2_gain)
++{
++ u32 i_thresh_l, q_thresh_l;
++ u32 i_thresh_h, q_thresh_h;
++ struct lcnphy_iq_est iq_est_h, iq_est_l;
++
++ wlc_lcnphy_set_rx_gain_by_distribution(pi, 0, 0, 0, biq1_gain, tia_gain,
++ lna2_gain, 0);
++
++ wlc_lcnphy_rx_gain_override_enable(pi, true);
++ wlc_lcnphy_start_tx_tone(pi, 2000, (40 >> 1), 0);
++ udelay(500);
++ write_radio_reg(pi, RADIO_2064_REG112, 0);
++ if (!wlc_lcnphy_rx_iq_est(pi, 1024, 32, &iq_est_l))
++ return false;
++
++ wlc_lcnphy_start_tx_tone(pi, 2000, 40, 0);
++ udelay(500);
++ write_radio_reg(pi, RADIO_2064_REG112, 0);
++ if (!wlc_lcnphy_rx_iq_est(pi, 1024, 32, &iq_est_h))
++ return false;
++
++ i_thresh_l = (iq_est_l.i_pwr << 1);
++ i_thresh_h = (iq_est_l.i_pwr << 2) + iq_est_l.i_pwr;
++
++ q_thresh_l = (iq_est_l.q_pwr << 1);
++ q_thresh_h = (iq_est_l.q_pwr << 2) + iq_est_l.q_pwr;
++ if ((iq_est_h.i_pwr > i_thresh_l) &&
++ (iq_est_h.i_pwr < i_thresh_h) &&
++ (iq_est_h.q_pwr > q_thresh_l) &&
++ (iq_est_h.q_pwr < q_thresh_h))
++ return true;
++
++ return false;
++}
++
+ static bool
+ wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi,
+ const struct lcnphy_rx_iqcomp *iqcomp,
+@@ -1342,8 +1380,8 @@
+ RFOverrideVal0_old, rfoverride2_old, rfoverride2val_old,
+ rfoverride3_old, rfoverride3val_old, rfoverride4_old,
+ rfoverride4val_old, afectrlovr_old, afectrlovrval_old;
+- int tia_gain;
+- u32 received_power, rx_pwr_threshold;
++ int tia_gain, lna2_gain, biq1_gain;
++ bool set_gain;
+ u16 old_sslpnCalibClkEnCtrl, old_sslpnRxFeClkEnCtrl;
+ u16 values_to_save[11];
+ s16 *ptr;
+@@ -1368,127 +1406,126 @@
+ goto cal_done;
+ }
+
+- if (module == 1) {
++ WARN_ON(module != 1);
++ tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
++ wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
+
+- tx_pwr_ctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
+- wlc_lcnphy_set_tx_pwr_ctrl(pi, LCNPHY_TX_PWR_CTRL_OFF);
++ for (i = 0; i < 11; i++)
++ values_to_save[i] =
++ read_radio_reg(pi, rxiq_cal_rf_reg[i]);
++ Core1TxControl_old = read_phy_reg(pi, 0x631);
+
+- for (i = 0; i < 11; i++)
+- values_to_save[i] =
+- read_radio_reg(pi, rxiq_cal_rf_reg[i]);
+- Core1TxControl_old = read_phy_reg(pi, 0x631);
+-
+- or_phy_reg(pi, 0x631, 0x0015);
+-
+- RFOverride0_old = read_phy_reg(pi, 0x44c);
+- RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
+- rfoverride2_old = read_phy_reg(pi, 0x4b0);
+- rfoverride2val_old = read_phy_reg(pi, 0x4b1);
+- rfoverride3_old = read_phy_reg(pi, 0x4f9);
+- rfoverride3val_old = read_phy_reg(pi, 0x4fa);
+- rfoverride4_old = read_phy_reg(pi, 0x938);
+- rfoverride4val_old = read_phy_reg(pi, 0x939);
+- afectrlovr_old = read_phy_reg(pi, 0x43b);
+- afectrlovrval_old = read_phy_reg(pi, 0x43c);
+- old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
+- old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
+-
+- tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
+- if (tx_gain_override_old) {
+- wlc_lcnphy_get_tx_gain(pi, &old_gains);
+- tx_gain_index_old = pi_lcn->lcnphy_current_index;
+- }
++ or_phy_reg(pi, 0x631, 0x0015);
+
+- wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
++ RFOverride0_old = read_phy_reg(pi, 0x44c);
++ RFOverrideVal0_old = read_phy_reg(pi, 0x44d);
++ rfoverride2_old = read_phy_reg(pi, 0x4b0);
++ rfoverride2val_old = read_phy_reg(pi, 0x4b1);
++ rfoverride3_old = read_phy_reg(pi, 0x4f9);
++ rfoverride3val_old = read_phy_reg(pi, 0x4fa);
++ rfoverride4_old = read_phy_reg(pi, 0x938);
++ rfoverride4val_old = read_phy_reg(pi, 0x939);
++ afectrlovr_old = read_phy_reg(pi, 0x43b);
++ afectrlovrval_old = read_phy_reg(pi, 0x43c);
++ old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
++ old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 0x6db);
+
+- mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
+- mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
++ tx_gain_override_old = wlc_lcnphy_tx_gain_override_enabled(pi);
++ if (tx_gain_override_old) {
++ wlc_lcnphy_get_tx_gain(pi, &old_gains);
++ tx_gain_index_old = pi_lcn->lcnphy_current_index;
++ }
+
+- mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
+- mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
++ wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx);
+
+- write_radio_reg(pi, RADIO_2064_REG116, 0x06);
+- write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
+- write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
+- write_radio_reg(pi, RADIO_2064_REG098, 0x03);
+- write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
+- mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
+- write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
+- write_radio_reg(pi, RADIO_2064_REG114, 0x01);
+- write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
+- write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
+-
+- mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
+- mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
+- mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
+- mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
+- mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
+- mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
+- mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
+- mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
+- mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
+- mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
+-
+- mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
+- mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
+-
+- wlc_lcnphy_start_tx_tone(pi, 2000, 120, 0);
+- write_phy_reg(pi, 0x6da, 0xffff);
+- or_phy_reg(pi, 0x6db, 0x3);
+- wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
+- wlc_lcnphy_rx_gain_override_enable(pi, true);
+-
+- tia_gain = 8;
+- rx_pwr_threshold = 950;
+- while (tia_gain > 0) {
+- tia_gain -= 1;
+- wlc_lcnphy_set_rx_gain_by_distribution(pi,
+- 0, 0, 2, 2,
+- (u16)
+- tia_gain, 1, 0);
+- udelay(500);
+-
+- received_power =
+- wlc_lcnphy_measure_digital_power(pi, 2000);
+- if (received_power < rx_pwr_threshold)
+- break;
+- }
+- result = wlc_lcnphy_calc_rx_iq_comp(pi, 0xffff);
++ mod_phy_reg(pi, 0x4f9, (0x1 << 0), 1 << 0);
++ mod_phy_reg(pi, 0x4fa, (0x1 << 0), 0 << 0);
+
+- wlc_lcnphy_stop_tx_tone(pi);
++ mod_phy_reg(pi, 0x43b, (0x1 << 1), 1 << 1);
++ mod_phy_reg(pi, 0x43c, (0x1 << 1), 0 << 1);
+
+- write_phy_reg(pi, 0x631, Core1TxControl_old);
++ write_radio_reg(pi, RADIO_2064_REG116, 0x06);
++ write_radio_reg(pi, RADIO_2064_REG12C, 0x07);
++ write_radio_reg(pi, RADIO_2064_REG06A, 0xd3);
++ write_radio_reg(pi, RADIO_2064_REG098, 0x03);
++ write_radio_reg(pi, RADIO_2064_REG00B, 0x7);
++ mod_radio_reg(pi, RADIO_2064_REG113, 1 << 4, 1 << 4);
++ write_radio_reg(pi, RADIO_2064_REG01D, 0x01);
++ write_radio_reg(pi, RADIO_2064_REG114, 0x01);
++ write_radio_reg(pi, RADIO_2064_REG02E, 0x10);
++ write_radio_reg(pi, RADIO_2064_REG12A, 0x08);
++
++ mod_phy_reg(pi, 0x938, (0x1 << 0), 1 << 0);
++ mod_phy_reg(pi, 0x939, (0x1 << 0), 0 << 0);
++ mod_phy_reg(pi, 0x938, (0x1 << 1), 1 << 1);
++ mod_phy_reg(pi, 0x939, (0x1 << 1), 1 << 1);
++ mod_phy_reg(pi, 0x938, (0x1 << 2), 1 << 2);
++ mod_phy_reg(pi, 0x939, (0x1 << 2), 1 << 2);
++ mod_phy_reg(pi, 0x938, (0x1 << 3), 1 << 3);
++ mod_phy_reg(pi, 0x939, (0x1 << 3), 1 << 3);
++ mod_phy_reg(pi, 0x938, (0x1 << 5), 1 << 5);
++ mod_phy_reg(pi, 0x939, (0x1 << 5), 0 << 5);
+
+- write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
+- write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
+- write_phy_reg(pi, 0x4b0, rfoverride2_old);
+- write_phy_reg(pi, 0x4b1, rfoverride2val_old);
+- write_phy_reg(pi, 0x4f9, rfoverride3_old);
+- write_phy_reg(pi, 0x4fa, rfoverride3val_old);
+- write_phy_reg(pi, 0x938, rfoverride4_old);
+- write_phy_reg(pi, 0x939, rfoverride4val_old);
+- write_phy_reg(pi, 0x43b, afectrlovr_old);
+- write_phy_reg(pi, 0x43c, afectrlovrval_old);
+- write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
+- write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
+-
+- wlc_lcnphy_clear_trsw_override(pi);
+-
+- mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
+-
+- for (i = 0; i < 11; i++)
+- write_radio_reg(pi, rxiq_cal_rf_reg[i],
+- values_to_save[i]);
++ mod_phy_reg(pi, 0x43b, (0x1 << 0), 1 << 0);
++ mod_phy_reg(pi, 0x43c, (0x1 << 0), 0 << 0);
+
+- if (tx_gain_override_old)
+- wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
+- else
+- wlc_lcnphy_disable_tx_gain_override(pi);
++ write_phy_reg(pi, 0x6da, 0xffff);
++ or_phy_reg(pi, 0x6db, 0x3);
++
++ wlc_lcnphy_set_trsw_override(pi, tx_switch, rx_switch);
++ for (lna2_gain = 3; lna2_gain >= 0; lna2_gain--) {
++ for (tia_gain = 4; tia_gain >= 0; tia_gain--) {
++ for (biq1_gain = 6; biq1_gain >= 0; biq1_gain--) {
++ set_gain = wlc_lcnphy_rx_iq_cal_gain(pi,
++ (u16)
++ biq1_gain,
++ (u16)
++ tia_gain,
++ (u16)
++ lna2_gain);
++ if (!set_gain)
++ continue;
+
+- wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
+- wlc_lcnphy_rx_gain_override_enable(pi, false);
++ result = wlc_lcnphy_calc_rx_iq_comp(pi, 1024);
++ goto stop_tone;
++ }
++ }
+ }
+
++stop_tone:
++ wlc_lcnphy_stop_tx_tone(pi);
++
++ write_phy_reg(pi, 0x631, Core1TxControl_old);
++
++ write_phy_reg(pi, 0x44c, RFOverrideVal0_old);
++ write_phy_reg(pi, 0x44d, RFOverrideVal0_old);
++ write_phy_reg(pi, 0x4b0, rfoverride2_old);
++ write_phy_reg(pi, 0x4b1, rfoverride2val_old);
++ write_phy_reg(pi, 0x4f9, rfoverride3_old);
++ write_phy_reg(pi, 0x4fa, rfoverride3val_old);
++ write_phy_reg(pi, 0x938, rfoverride4_old);
++ write_phy_reg(pi, 0x939, rfoverride4val_old);
++ write_phy_reg(pi, 0x43b, afectrlovr_old);
++ write_phy_reg(pi, 0x43c, afectrlovrval_old);
++ write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
++ write_phy_reg(pi, 0x6db, old_sslpnRxFeClkEnCtrl);
++
++ wlc_lcnphy_clear_trsw_override(pi);
++
++ mod_phy_reg(pi, 0x44c, (0x1 << 2), 0 << 2);
++
++ for (i = 0; i < 11; i++)
++ write_radio_reg(pi, rxiq_cal_rf_reg[i],
++ values_to_save[i]);
++
++ if (tx_gain_override_old)
++ wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_index_old);
++ else
++ wlc_lcnphy_disable_tx_gain_override(pi);
++
++ wlc_lcnphy_set_tx_pwr_ctrl(pi, tx_pwr_ctrl);
++ wlc_lcnphy_rx_gain_override_enable(pi, false);
++
+ cal_done:
+ kfree(ptr);
+ return result;
+@@ -1789,6 +1826,19 @@
+ write_radio_reg(pi, RADIO_2064_REG038, 3);
+ write_radio_reg(pi, RADIO_2064_REG091, 7);
+ }
++
++ if (!(pi->sh->boardflags & BFL_FEM)) {
++ static const u8 reg038[14] = {
++ 0xd, 0xe, 0xd, 0xd, 0xd, 0xc, 0xa,
++ 0xb, 0xb, 0x3, 0x3, 0x2, 0x0, 0x0
++ };
++
++ write_radio_reg(pi, RADIO_2064_REG02A, 0xf);
++ write_radio_reg(pi, RADIO_2064_REG091, 0x3);
++ write_radio_reg(pi, RADIO_2064_REG038, 0x3);
++
++ write_radio_reg(pi, RADIO_2064_REG038, reg038[channel - 1]);
++ }
+ }
+
+ static int
+@@ -1983,6 +2033,16 @@
+ } else {
+ mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1);
+ mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
++ mod_radio_reg(pi, RADIO_2064_REG028, 0x1, 0x0);
++ mod_radio_reg(pi, RADIO_2064_REG11A, 0x4, 1<<2);
++ mod_radio_reg(pi, RADIO_2064_REG036, 0x10, 0x0);
++ mod_radio_reg(pi, RADIO_2064_REG11A, 0x10, 1<<4);
++ mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0);
++ mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x77);
++ mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0xe<<1);
++ mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1<<7);
++ mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 1<<1);
++ mod_radio_reg(pi, RADIO_2064_REG029, 0xf0, 0<<4);
+ }
+ } else {
+ mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2);
+@@ -2069,13 +2129,23 @@
+ (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12));
+
+ mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5));
++ mod_radio_reg(pi, RADIO_2064_REG07C, (1 << 0), (1 << 0));
+ }
+
+ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi)
+ {
+ struct phytbl_info tab;
+ u32 rfseq, ind;
++ enum lcnphy_tssi_mode mode;
++ u8 tssi_sel;
+
++ if (pi->sh->boardflags & BFL_FEM) {
++ tssi_sel = 0x1;
++ mode = LCNPHY_TSSI_EXT;
++ } else {
++ tssi_sel = 0xe;
++ mode = LCNPHY_TSSI_POST_PA;
++ }
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_ptr = &ind;
+@@ -2096,7 +2166,7 @@
+
+ mod_phy_reg(pi, 0x503, (0x1 << 4), (1) << 4);
+
+- wlc_lcnphy_set_tssi_mux(pi, LCNPHY_TSSI_EXT);
++ wlc_lcnphy_set_tssi_mux(pi, mode);
+ mod_phy_reg(pi, 0x4a4, (0x1 << 14), (0) << 14);
+
+ mod_phy_reg(pi, 0x4a4, (0x1 << 15), (1) << 15);
+@@ -2132,9 +2202,10 @@
+ mod_phy_reg(pi, 0x49a, (0x1ff << 0), (0xff) << 0);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+- mod_radio_reg(pi, RADIO_2064_REG028, 0xf, 0xe);
++ mod_radio_reg(pi, RADIO_2064_REG028, 0xf, tssi_sel);
+ mod_radio_reg(pi, RADIO_2064_REG086, 0x4, 0x4);
+ } else {
++ mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, tssi_sel << 1);
+ mod_radio_reg(pi, RADIO_2064_REG03A, 0x1, 1);
+ mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 1 << 3);
+ }
+@@ -2181,6 +2252,10 @@
+
+ mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8);
+
++ mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x0);
++ mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0);
++ mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8);
++
+ wlc_lcnphy_pwrctrl_rssiparams(pi);
+ }
+
+@@ -2799,6 +2874,8 @@
+ read_radio_reg(pi, RADIO_2064_REG007) & 1;
+ u16 SAVE_jtag_auxpga = read_radio_reg(pi, RADIO_2064_REG0FF) & 0x10;
+ u16 SAVE_iqadc_aux_en = read_radio_reg(pi, RADIO_2064_REG11F) & 4;
++ u8 SAVE_bbmult = wlc_lcnphy_get_bbmult(pi);
++
+ idleTssi = read_phy_reg(pi, 0x4ab);
+ suspend = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
+ MCTL_EN_MAC));
+@@ -2816,6 +2893,12 @@
+ mod_radio_reg(pi, RADIO_2064_REG0FF, 0x10, 1 << 4);
+ mod_radio_reg(pi, RADIO_2064_REG11F, 0x4, 1 << 2);
+ wlc_lcnphy_tssi_setup(pi);
++
++ mod_phy_reg(pi, 0x4d7, (0x1 << 0), (1 << 0));
++ mod_phy_reg(pi, 0x4d7, (0x1 << 6), (1 << 6));
++
++ wlc_lcnphy_set_bbmult(pi, 0x0);
++
+ wlc_phy_do_dummy_tx(pi, true, OFF);
+ idleTssi = ((read_phy_reg(pi, 0x4ab) & (0x1ff << 0))
+ >> 0);
+@@ -2837,6 +2920,7 @@
+
+ mod_phy_reg(pi, 0x44c, (0x1 << 12), (0) << 12);
+
++ wlc_lcnphy_set_bbmult(pi, SAVE_bbmult);
+ wlc_lcnphy_set_tx_gain_override(pi, tx_gain_override_old);
+ wlc_lcnphy_set_tx_gain(pi, &old_gains);
+ wlc_lcnphy_set_tx_pwr_ctrl(pi, SAVE_txpwrctrl);
+@@ -3050,6 +3134,11 @@
+ wlc_lcnphy_write_table(pi, &tab);
+ tab.tbl_offset++;
+ }
++ mod_phy_reg(pi, 0x4d0, (0x1 << 0), (0) << 0);
++ mod_phy_reg(pi, 0x4d3, (0xff << 0), (0) << 0);
++ mod_phy_reg(pi, 0x4d3, (0xff << 8), (0) << 8);
++ mod_phy_reg(pi, 0x4d0, (0x1 << 4), (0) << 4);
++ mod_phy_reg(pi, 0x4d0, (0x1 << 2), (0) << 2);
+
+ mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7);
+
+@@ -3851,7 +3940,6 @@
+ target_gains.pad_gain = 21;
+ target_gains.dac_gain = 0;
+ wlc_lcnphy_set_tx_gain(pi, &target_gains);
+- wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 1) || pi_lcn->lcnphy_hw_iqcal_en) {
+
+@@ -3862,6 +3950,7 @@
+ lcnphy_recal ? LCNPHY_CAL_RECAL :
+ LCNPHY_CAL_FULL), false);
+ } else {
++ wlc_lcnphy_set_tx_pwr_by_index(pi, 16);
+ wlc_lcnphy_tx_iqlo_soft_cal_full(pi);
+ }
+
+@@ -4283,20 +4372,20 @@
+ u16 pa_gain;
+ u16 gm_gain;
+
+- if (CHSPEC_IS5G(pi->radio_chanspec))
+- pa_gain = 0x70;
+- else
+- pa_gain = 0x70;
+-
+ if (pi->sh->boardflags & BFL_FEM)
+ pa_gain = 0x10;
++ else
++ pa_gain = 0x60;
+ tab.tbl_id = LCNPHY_TBL_ID_TXPWRCTL;
+ tab.tbl_width = 32;
+ tab.tbl_len = 1;
+ tab.tbl_ptr = &val;
+
++ /* fixed gm_gain value for iPA */
++ gm_gain = 15;
+ for (j = 0; j < 128; j++) {
+- gm_gain = gain_table[j].gm;
++ if (pi->sh->boardflags & BFL_FEM)
++ gm_gain = gain_table[j].gm;
+ val = (((u32) pa_gain << 24) |
+ (gain_table[j].pad << 16) |
+ (gain_table[j].pga << 8) | gm_gain);
+@@ -4507,7 +4596,10 @@
+
+ write_phy_reg(pi, 0x4ea, 0x4688);
+
+- mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
++ if (pi->sh->boardflags & BFL_FEM)
++ mod_phy_reg(pi, 0x4eb, (0x7 << 0), 2 << 0);
++ else
++ mod_phy_reg(pi, 0x4eb, (0x7 << 0), 3 << 0);
+
+ mod_phy_reg(pi, 0x4eb, (0x7 << 6), 0 << 6);
+
+@@ -4518,6 +4610,13 @@
+ wlc_lcnphy_rcal(pi);
+
+ wlc_lcnphy_rc_cal(pi);
++
++ if (!(pi->sh->boardflags & BFL_FEM)) {
++ write_radio_reg(pi, RADIO_2064_REG032, 0x6f);
++ write_radio_reg(pi, RADIO_2064_REG033, 0x19);
++ write_radio_reg(pi, RADIO_2064_REG039, 0xe);
++ }
++
+ }
+
+ static void wlc_lcnphy_radio_init(struct brcms_phy *pi)
+@@ -4530,6 +4629,7 @@
+ uint idx;
+ u8 phybw40;
+ struct phytbl_info tab;
++ const struct phytbl_info *tb;
+ u32 val;
+
+ phybw40 = CHSPEC_IS40(pi->radio_chanspec);
+@@ -4547,22 +4647,20 @@
+ wlc_lcnphy_write_table(pi, &tab);
+ }
+
+- tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
+- tab.tbl_width = 16;
+- tab.tbl_ptr = &val;
+- tab.tbl_len = 1;
+-
+- val = 114;
+- tab.tbl_offset = 0;
+- wlc_lcnphy_write_table(pi, &tab);
++ if (!(pi->sh->boardflags & BFL_FEM)) {
++ tab.tbl_id = LCNPHY_TBL_ID_RFSEQ;
++ tab.tbl_width = 16;
++ tab.tbl_ptr = &val;
++ tab.tbl_len = 1;
+
+- val = 130;
+- tab.tbl_offset = 1;
+- wlc_lcnphy_write_table(pi, &tab);
++ val = 150;
++ tab.tbl_offset = 0;
++ wlc_lcnphy_write_table(pi, &tab);
+
+- val = 6;
+- tab.tbl_offset = 8;
+- wlc_lcnphy_write_table(pi, &tab);
++ val = 220;
++ tab.tbl_offset = 1;
++ wlc_lcnphy_write_table(pi, &tab);
++ }
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+ if (pi->sh->boardflags & BFL_FEM)
+@@ -4576,7 +4674,6 @@
+ }
+
+ if (LCNREV_IS(pi->pubpi.phy_rev, 2)) {
+- const struct phytbl_info *tb;
+ int l;
+
+ if (CHSPEC_IS2G(pi->radio_chanspec)) {
+@@ -4597,21 +4694,22 @@
+ wlc_lcnphy_write_table(pi, &tb[idx]);
+ }
+
+- if ((pi->sh->boardflags & BFL_FEM)
+- && !(pi->sh->boardflags & BFL_FEM_BT))
+- wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313_epa);
+- else if (pi->sh->boardflags & BFL_FEM_BT) {
+- if (pi->sh->boardrev < 0x1250)
+- wlc_lcnphy_write_table(
+- pi,
+- &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa);
++ if (pi->sh->boardflags & BFL_FEM) {
++ if (pi->sh->boardflags & BFL_FEM_BT) {
++ if (pi->sh->boardrev < 0x1250)
++ tb = &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa;
++ else
++ tb = &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250;
++ } else {
++ tb = &dot11lcn_sw_ctrl_tbl_info_4313_epa;
++ }
++ } else {
++ if (pi->sh->boardflags & BFL_FEM_BT)
++ tb = &dot11lcn_sw_ctrl_tbl_info_4313_bt_ipa;
+ else
+- wlc_lcnphy_write_table(
+- pi,
+- &dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250);
+- } else
+- wlc_lcnphy_write_table(pi, &dot11lcn_sw_ctrl_tbl_info_4313);
+-
++ tb = &dot11lcn_sw_ctrl_tbl_info_4313;
++ }
++ wlc_lcnphy_write_table(pi, tb);
+ wlc_lcnphy_load_rfpower(pi);
+
+ wlc_lcnphy_clear_papd_comptable(pi);
+@@ -4955,6 +5053,8 @@
+ wlc_lcnphy_load_tx_iir_filter(pi, true, 3);
+
+ mod_phy_reg(pi, 0x4eb, (0x7 << 3), (1) << 3);
++ if (wlc_lcnphy_tssi_based_pwr_ctrl_enabled(pi))
++ wlc_lcnphy_tssi_setup(pi);
+ }
+
+ void wlc_phy_detach_lcnphy(struct brcms_phy *pi)
+@@ -4993,8 +5093,7 @@
+ if (!wlc_phy_txpwr_srom_read_lcnphy(pi))
+ return false;
+
+- if ((pi->sh->boardflags & BFL_FEM) &&
+- (LCNREV_IS(pi->pubpi.phy_rev, 1))) {
++ if (LCNREV_IS(pi->pubpi.phy_rev, 1)) {
+ if (pi_lcn->lcnphy_tempsense_option == 3) {
+ pi->hwpwrctrl = true;
+ pi->hwpwrctrl_capable = true;
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.c 2014-05-15 20:34:00.698033322 +0200
+@@ -1507,117 +1507,103 @@
+
+ const struct phytbl_info dot11lcnphytbl_rx_gain_info_rev0[] = {
+ {&dot11lcn_gain_tbl_rev0,
+- sizeof(dot11lcn_gain_tbl_rev0) / sizeof(dot11lcn_gain_tbl_rev0[0]), 18,
++ ARRAY_SIZE(dot11lcn_gain_tbl_rev0), 18,
+ 0, 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_rev0,
+- sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
+- sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
++ ARRAY_SIZE(dot11lcn_aux_gain_idx_tbl_rev0), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_rev0,
+- sizeof(dot11lcn_gain_idx_tbl_rev0) /
+- sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
++ ARRAY_SIZE(dot11lcn_gain_idx_tbl_rev0), 13, 0, 32}
+ ,
+ };
+
+ static const struct phytbl_info dot11lcnphytbl_rx_gain_info_rev1[] = {
+ {&dot11lcn_gain_tbl_rev1,
+- sizeof(dot11lcn_gain_tbl_rev1) / sizeof(dot11lcn_gain_tbl_rev1[0]), 18,
++ ARRAY_SIZE(dot11lcn_gain_tbl_rev1), 18,
+ 0, 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_rev0,
+- sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
+- sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
++ ARRAY_SIZE(dot11lcn_aux_gain_idx_tbl_rev0), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_rev0,
+- sizeof(dot11lcn_gain_idx_tbl_rev0) /
+- sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
++ ARRAY_SIZE(dot11lcn_gain_idx_tbl_rev0), 13, 0, 32}
+ ,
+ };
+
+ const struct phytbl_info dot11lcnphytbl_rx_gain_info_2G_rev2[] = {
+ {&dot11lcn_gain_tbl_2G,
+- sizeof(dot11lcn_gain_tbl_2G) / sizeof(dot11lcn_gain_tbl_2G[0]), 18, 0,
++ ARRAY_SIZE(dot11lcn_gain_tbl_2G), 18, 0,
+ 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_2G,
+- sizeof(dot11lcn_aux_gain_idx_tbl_2G) /
+- sizeof(dot11lcn_aux_gain_idx_tbl_2G[0]), 14, 0, 16}
++ ARRAY_SIZE(dot11lcn_aux_gain_idx_tbl_2G), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_2G,
+- sizeof(dot11lcn_gain_idx_tbl_2G) / sizeof(dot11lcn_gain_idx_tbl_2G[0]),
++ ARRAY_SIZE(dot11lcn_gain_idx_tbl_2G),
+ 13, 0, 32}
+ ,
+ {&dot11lcn_gain_val_tbl_2G,
+- sizeof(dot11lcn_gain_val_tbl_2G) / sizeof(dot11lcn_gain_val_tbl_2G[0]),
++ ARRAY_SIZE(dot11lcn_gain_val_tbl_2G),
+ 17, 0, 8}
+ };
+
+ const struct phytbl_info dot11lcnphytbl_rx_gain_info_5G_rev2[] = {
+ {&dot11lcn_gain_tbl_5G,
+- sizeof(dot11lcn_gain_tbl_5G) / sizeof(dot11lcn_gain_tbl_5G[0]), 18, 0,
++ ARRAY_SIZE(dot11lcn_gain_tbl_5G), 18, 0,
+ 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_5G,
+- sizeof(dot11lcn_aux_gain_idx_tbl_5G) /
+- sizeof(dot11lcn_aux_gain_idx_tbl_5G[0]), 14, 0, 16}
++ ARRAY_SIZE(dot11lcn_aux_gain_idx_tbl_5G), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_5G,
+- sizeof(dot11lcn_gain_idx_tbl_5G) / sizeof(dot11lcn_gain_idx_tbl_5G[0]),
++ ARRAY_SIZE(dot11lcn_gain_idx_tbl_5G),
+ 13, 0, 32}
+ ,
+ {&dot11lcn_gain_val_tbl_5G,
+- sizeof(dot11lcn_gain_val_tbl_5G) / sizeof(dot11lcn_gain_val_tbl_5G[0]),
++ ARRAY_SIZE(dot11lcn_gain_val_tbl_5G),
+ 17, 0, 8}
+ };
+
+ const struct phytbl_info dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[] = {
+ {&dot11lcn_gain_tbl_extlna_2G,
+- sizeof(dot11lcn_gain_tbl_extlna_2G) /
+- sizeof(dot11lcn_gain_tbl_extlna_2G[0]), 18, 0, 32}
++ ARRAY_SIZE(dot11lcn_gain_tbl_extlna_2G), 18, 0, 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_extlna_2G,
+- sizeof(dot11lcn_aux_gain_idx_tbl_extlna_2G) /
+- sizeof(dot11lcn_aux_gain_idx_tbl_extlna_2G[0]), 14, 0, 16}
++ ARRAY_SIZE(dot11lcn_aux_gain_idx_tbl_extlna_2G), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_extlna_2G,
+- sizeof(dot11lcn_gain_idx_tbl_extlna_2G) /
+- sizeof(dot11lcn_gain_idx_tbl_extlna_2G[0]), 13, 0, 32}
++ ARRAY_SIZE(dot11lcn_gain_idx_tbl_extlna_2G), 13, 0, 32}
+ ,
+ {&dot11lcn_gain_val_tbl_extlna_2G,
+- sizeof(dot11lcn_gain_val_tbl_extlna_2G) /
+- sizeof(dot11lcn_gain_val_tbl_extlna_2G[0]), 17, 0, 8}
++ ARRAY_SIZE(dot11lcn_gain_val_tbl_extlna_2G), 17, 0, 8}
+ };
+
+ const struct phytbl_info dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[] = {
+ {&dot11lcn_gain_tbl_5G,
+- sizeof(dot11lcn_gain_tbl_5G) / sizeof(dot11lcn_gain_tbl_5G[0]), 18, 0,
++ ARRAY_SIZE(dot11lcn_gain_tbl_5G), 18, 0,
+ 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_5G,
+- sizeof(dot11lcn_aux_gain_idx_tbl_5G) /
+- sizeof(dot11lcn_aux_gain_idx_tbl_5G[0]), 14, 0, 16}
++ ARRAY_SIZE(dot11lcn_aux_gain_idx_tbl_5G), 14, 0, 16}
+ ,
+ {&dot11lcn_gain_idx_tbl_5G,
+- sizeof(dot11lcn_gain_idx_tbl_5G) / sizeof(dot11lcn_gain_idx_tbl_5G[0]),
++ ARRAY_SIZE(dot11lcn_gain_idx_tbl_5G),
+ 13, 0, 32}
+ ,
+ {&dot11lcn_gain_val_tbl_5G,
+- sizeof(dot11lcn_gain_val_tbl_5G) / sizeof(dot11lcn_gain_val_tbl_5G[0]),
++ ARRAY_SIZE(dot11lcn_gain_val_tbl_5G),
+ 17, 0, 8}
+ };
+
+ const u32 dot11lcnphytbl_rx_gain_info_sz_rev0 =
+- sizeof(dot11lcnphytbl_rx_gain_info_rev0) /
+- sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]);
++ ARRAY_SIZE(dot11lcnphytbl_rx_gain_info_rev0);
+
+ const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz =
+- sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) /
+- sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]);
++ ARRAY_SIZE(dot11lcnphytbl_rx_gain_info_2G_rev2);
+
+ const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz =
+- sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) /
+- sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]);
++ ARRAY_SIZE(dot11lcnphytbl_rx_gain_info_5G_rev2);
+
+ static const u16 dot11lcn_min_sig_sq_tbl_rev0[] = {
+ 0x014d,
+@@ -2058,6 +2044,73 @@
+ 0x0005,
+ };
+
++static const u16 dot11lcn_sw_ctrl_tbl_4313_ipa_rev0_combo[] = {
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++ 0x0005,
++ 0x0006,
++ 0x0009,
++ 0x000a,
++};
++
+ static const u16 dot11lcn_sw_ctrl_tbl_rev0[] = {
+ 0x0004,
+ 0x0004,
+@@ -2771,89 +2824,79 @@
+
+ const struct phytbl_info dot11lcnphytbl_info_rev0[] = {
+ {&dot11lcn_min_sig_sq_tbl_rev0,
+- sizeof(dot11lcn_min_sig_sq_tbl_rev0) /
+- sizeof(dot11lcn_min_sig_sq_tbl_rev0[0]), 2, 0, 16}
++ ARRAY_SIZE(dot11lcn_min_sig_sq_tbl_rev0), 2, 0, 16}
+ ,
+ {&dot11lcn_noise_scale_tbl_rev0,
+- sizeof(dot11lcn_noise_scale_tbl_rev0) /
+- sizeof(dot11lcn_noise_scale_tbl_rev0[0]), 1, 0, 16}
++ ARRAY_SIZE(dot11lcn_noise_scale_tbl_rev0), 1, 0, 16}
+ ,
+ {&dot11lcn_fltr_ctrl_tbl_rev0,
+- sizeof(dot11lcn_fltr_ctrl_tbl_rev0) /
+- sizeof(dot11lcn_fltr_ctrl_tbl_rev0[0]), 11, 0, 32}
++ ARRAY_SIZE(dot11lcn_fltr_ctrl_tbl_rev0), 11, 0, 32}
+ ,
+ {&dot11lcn_ps_ctrl_tbl_rev0,
+- sizeof(dot11lcn_ps_ctrl_tbl_rev0) /
+- sizeof(dot11lcn_ps_ctrl_tbl_rev0[0]), 12, 0, 32}
++ ARRAY_SIZE(dot11lcn_ps_ctrl_tbl_rev0), 12, 0, 32}
+ ,
+ {&dot11lcn_gain_idx_tbl_rev0,
+- sizeof(dot11lcn_gain_idx_tbl_rev0) /
+- sizeof(dot11lcn_gain_idx_tbl_rev0[0]), 13, 0, 32}
++ ARRAY_SIZE(dot11lcn_gain_idx_tbl_rev0), 13, 0, 32}
+ ,
+ {&dot11lcn_aux_gain_idx_tbl_rev0,
+- sizeof(dot11lcn_aux_gain_idx_tbl_rev0) /
+- sizeof(dot11lcn_aux_gain_idx_tbl_rev0[0]), 14, 0, 16}
++ ARRAY_SIZE(dot11lcn_aux_gain_idx_tbl_rev0), 14, 0, 16}
+ ,
+ {&dot11lcn_sw_ctrl_tbl_rev0,
+- sizeof(dot11lcn_sw_ctrl_tbl_rev0) /
+- sizeof(dot11lcn_sw_ctrl_tbl_rev0[0]), 15, 0, 16}
++ ARRAY_SIZE(dot11lcn_sw_ctrl_tbl_rev0), 15, 0, 16}
+ ,
+ {&dot11lcn_nf_table_rev0,
+- sizeof(dot11lcn_nf_table_rev0) / sizeof(dot11lcn_nf_table_rev0[0]), 16,
++ ARRAY_SIZE(dot11lcn_nf_table_rev0), 16,
+ 0, 8}
+ ,
+ {&dot11lcn_gain_val_tbl_rev0,
+- sizeof(dot11lcn_gain_val_tbl_rev0) /
+- sizeof(dot11lcn_gain_val_tbl_rev0[0]), 17, 0, 8}
++ ARRAY_SIZE(dot11lcn_gain_val_tbl_rev0), 17, 0, 8}
+ ,
+ {&dot11lcn_gain_tbl_rev0,
+- sizeof(dot11lcn_gain_tbl_rev0) / sizeof(dot11lcn_gain_tbl_rev0[0]), 18,
++ ARRAY_SIZE(dot11lcn_gain_tbl_rev0), 18,
+ 0, 32}
+ ,
+ {&dot11lcn_spur_tbl_rev0,
+- sizeof(dot11lcn_spur_tbl_rev0) / sizeof(dot11lcn_spur_tbl_rev0[0]), 20,
++ ARRAY_SIZE(dot11lcn_spur_tbl_rev0), 20,
+ 0, 8}
+ ,
+ {&dot11lcn_unsup_mcs_tbl_rev0,
+- sizeof(dot11lcn_unsup_mcs_tbl_rev0) /
+- sizeof(dot11lcn_unsup_mcs_tbl_rev0[0]), 23, 0, 16}
++ ARRAY_SIZE(dot11lcn_unsup_mcs_tbl_rev0), 23, 0, 16}
+ ,
+ {&dot11lcn_iq_local_tbl_rev0,
+- sizeof(dot11lcn_iq_local_tbl_rev0) /
+- sizeof(dot11lcn_iq_local_tbl_rev0[0]), 0, 0, 16}
++ ARRAY_SIZE(dot11lcn_iq_local_tbl_rev0), 0, 0, 16}
+ ,
+ {&dot11lcn_papd_compdelta_tbl_rev0,
+- sizeof(dot11lcn_papd_compdelta_tbl_rev0) /
+- sizeof(dot11lcn_papd_compdelta_tbl_rev0[0]), 24, 0, 32}
++ ARRAY_SIZE(dot11lcn_papd_compdelta_tbl_rev0), 24, 0, 32}
+ ,
+ };
+
+ const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313 = {
+ &dot11lcn_sw_ctrl_tbl_4313_rev0,
+- sizeof(dot11lcn_sw_ctrl_tbl_4313_rev0) /
+- sizeof(dot11lcn_sw_ctrl_tbl_4313_rev0[0]), 15, 0, 16
++ ARRAY_SIZE(dot11lcn_sw_ctrl_tbl_4313_rev0), 15, 0, 16
++};
++
++const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_ipa = {
++ &dot11lcn_sw_ctrl_tbl_4313_ipa_rev0_combo,
++ ARRAY_SIZE(dot11lcn_sw_ctrl_tbl_4313_ipa_rev0_combo), 15, 0, 16
+ };
+
+ const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_epa = {
+ &dot11lcn_sw_ctrl_tbl_4313_epa_rev0,
+- sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0) /
+- sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0[0]), 15, 0, 16
++ ARRAY_SIZE(dot11lcn_sw_ctrl_tbl_4313_epa_rev0), 15, 0, 16
+ };
+
+ const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_epa = {
+ &dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo,
+- sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo) /
+- sizeof(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[0]), 15, 0, 16
++ ARRAY_SIZE(dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo), 15, 0, 16
+ };
+
+ const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = {
+ &dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0,
+- sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0) /
+- sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16
++ ARRAY_SIZE(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0), 15, 0, 16
+ };
+
+ const u32 dot11lcnphytbl_info_sz_rev0 =
+- sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]);
++ ARRAY_SIZE(dot11lcnphytbl_info_rev0);
+
+ const struct lcnphy_tx_gain_tbl_entry
+ dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = {
+@@ -2988,134 +3031,134 @@
+ };
+
+ const struct lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_gaintable_rev0[128] = {
+- {7, 0, 31, 0, 72},
+- {7, 0, 31, 0, 70},
+- {7, 0, 31, 0, 68},
+- {7, 0, 30, 0, 67},
+- {7, 0, 29, 0, 68},
+- {7, 0, 28, 0, 68},
+- {7, 0, 27, 0, 69},
+- {7, 0, 26, 0, 70},
+- {7, 0, 25, 0, 70},
+- {7, 0, 24, 0, 71},
+- {7, 0, 23, 0, 72},
+- {7, 0, 23, 0, 70},
+- {7, 0, 22, 0, 71},
+- {7, 0, 21, 0, 72},
+- {7, 0, 21, 0, 70},
+- {7, 0, 21, 0, 68},
+- {7, 0, 21, 0, 66},
+- {7, 0, 21, 0, 64},
+- {7, 0, 21, 0, 63},
+- {7, 0, 20, 0, 64},
+- {7, 0, 19, 0, 65},
+- {7, 0, 19, 0, 64},
+- {7, 0, 18, 0, 65},
+- {7, 0, 18, 0, 64},
+- {7, 0, 17, 0, 65},
+- {7, 0, 17, 0, 64},
+- {7, 0, 16, 0, 65},
+- {7, 0, 16, 0, 64},
+- {7, 0, 16, 0, 62},
+- {7, 0, 16, 0, 60},
+- {7, 0, 16, 0, 58},
+- {7, 0, 15, 0, 61},
+- {7, 0, 15, 0, 59},
+- {7, 0, 14, 0, 61},
+- {7, 0, 14, 0, 60},
+- {7, 0, 14, 0, 58},
+- {7, 0, 13, 0, 60},
+- {7, 0, 13, 0, 59},
+- {7, 0, 12, 0, 62},
+- {7, 0, 12, 0, 60},
+- {7, 0, 12, 0, 58},
+- {7, 0, 11, 0, 62},
+- {7, 0, 11, 0, 60},
+- {7, 0, 11, 0, 59},
+- {7, 0, 11, 0, 57},
+- {7, 0, 10, 0, 61},
+- {7, 0, 10, 0, 59},
+- {7, 0, 10, 0, 57},
+- {7, 0, 9, 0, 62},
+- {7, 0, 9, 0, 60},
+- {7, 0, 9, 0, 58},
+- {7, 0, 9, 0, 57},
+- {7, 0, 8, 0, 62},
+- {7, 0, 8, 0, 60},
+- {7, 0, 8, 0, 58},
+- {7, 0, 8, 0, 57},
+- {7, 0, 8, 0, 55},
+- {7, 0, 7, 0, 61},
++ {15, 0, 31, 0, 72},
++ {15, 0, 31, 0, 70},
++ {15, 0, 31, 0, 68},
++ {15, 0, 30, 0, 68},
++ {15, 0, 29, 0, 69},
++ {15, 0, 28, 0, 69},
++ {15, 0, 27, 0, 70},
++ {15, 0, 26, 0, 70},
++ {15, 0, 25, 0, 71},
++ {15, 0, 24, 0, 72},
++ {15, 0, 23, 0, 73},
++ {15, 0, 23, 0, 71},
++ {15, 0, 22, 0, 72},
++ {15, 0, 21, 0, 73},
++ {15, 0, 21, 0, 71},
++ {15, 0, 21, 0, 69},
++ {15, 0, 21, 0, 67},
++ {15, 0, 21, 0, 65},
++ {15, 0, 21, 0, 63},
++ {15, 0, 20, 0, 65},
++ {15, 0, 19, 0, 66},
++ {15, 0, 19, 0, 64},
++ {15, 0, 18, 0, 66},
++ {15, 0, 18, 0, 64},
++ {15, 0, 17, 0, 66},
++ {15, 0, 17, 0, 64},
++ {15, 0, 16, 0, 66},
++ {15, 0, 16, 0, 64},
++ {15, 0, 16, 0, 62},
++ {15, 0, 16, 0, 61},
++ {15, 0, 16, 0, 59},
++ {15, 0, 15, 0, 61},
++ {15, 0, 15, 0, 59},
++ {15, 0, 14, 0, 62},
++ {15, 0, 14, 0, 60},
++ {15, 0, 14, 0, 58},
++ {15, 0, 13, 0, 61},
++ {15, 0, 13, 0, 59},
++ {15, 0, 12, 0, 62},
++ {15, 0, 12, 0, 61},
++ {15, 0, 12, 0, 59},
++ {15, 0, 11, 0, 62},
++ {15, 0, 11, 0, 61},
++ {15, 0, 11, 0, 59},
++ {15, 0, 11, 0, 57},
++ {15, 0, 10, 0, 61},
++ {15, 0, 10, 0, 59},
++ {15, 0, 10, 0, 58},
++ {15, 0, 9, 0, 62},
++ {15, 0, 9, 0, 61},
++ {15, 0, 9, 0, 59},
++ {15, 0, 9, 0, 57},
++ {15, 0, 8, 0, 62},
++ {15, 0, 8, 0, 61},
++ {15, 0, 8, 0, 59},
++ {15, 0, 8, 0, 57},
++ {15, 0, 8, 0, 56},
++ {15, 0, 8, 0, 54},
++ {15, 0, 8, 0, 53},
++ {15, 0, 8, 0, 51},
++ {15, 0, 8, 0, 50},
++ {7, 0, 7, 0, 69},
++ {7, 0, 7, 0, 67},
++ {7, 0, 7, 0, 65},
++ {7, 0, 7, 0, 64},
++ {7, 0, 7, 0, 62},
+ {7, 0, 7, 0, 60},
+ {7, 0, 7, 0, 58},
+- {7, 0, 7, 0, 56},
++ {7, 0, 7, 0, 57},
+ {7, 0, 7, 0, 55},
+ {7, 0, 6, 0, 62},
+- {7, 0, 6, 0, 60},
+- {7, 0, 6, 0, 58},
++ {7, 0, 6, 0, 61},
++ {7, 0, 6, 0, 59},
+ {7, 0, 6, 0, 57},
+- {7, 0, 6, 0, 55},
++ {7, 0, 6, 0, 56},
+ {7, 0, 6, 0, 54},
+- {7, 0, 6, 0, 52},
++ {7, 0, 6, 0, 53},
+ {7, 0, 5, 0, 61},
+- {7, 0, 5, 0, 59},
+- {7, 0, 5, 0, 57},
++ {7, 0, 5, 0, 60},
++ {7, 0, 5, 0, 58},
+ {7, 0, 5, 0, 56},
+- {7, 0, 5, 0, 54},
++ {7, 0, 5, 0, 55},
+ {7, 0, 5, 0, 53},
+- {7, 0, 5, 0, 51},
+- {7, 0, 4, 0, 62},
+- {7, 0, 4, 0, 60},
+- {7, 0, 4, 0, 58},
++ {7, 0, 5, 0, 52},
++ {7, 0, 5, 0, 50},
++ {7, 0, 5, 0, 49},
++ {7, 0, 5, 0, 47},
+ {7, 0, 4, 0, 57},
+- {7, 0, 4, 0, 55},
++ {7, 0, 4, 0, 56},
+ {7, 0, 4, 0, 54},
+- {7, 0, 4, 0, 52},
++ {7, 0, 4, 0, 53},
+ {7, 0, 4, 0, 51},
+- {7, 0, 4, 0, 49},
++ {7, 0, 4, 0, 50},
+ {7, 0, 4, 0, 48},
++ {7, 0, 4, 0, 47},
+ {7, 0, 4, 0, 46},
+- {7, 0, 3, 0, 60},
+- {7, 0, 3, 0, 58},
+- {7, 0, 3, 0, 57},
+- {7, 0, 3, 0, 55},
+- {7, 0, 3, 0, 54},
+- {7, 0, 3, 0, 52},
++ {7, 0, 4, 0, 44},
++ {7, 0, 4, 0, 43},
++ {7, 0, 4, 0, 42},
++ {7, 0, 4, 0, 41},
++ {7, 0, 4, 0, 40},
+ {7, 0, 3, 0, 51},
+- {7, 0, 3, 0, 49},
++ {7, 0, 3, 0, 50},
+ {7, 0, 3, 0, 48},
++ {7, 0, 3, 0, 47},
+ {7, 0, 3, 0, 46},
+- {7, 0, 3, 0, 45},
+ {7, 0, 3, 0, 44},
+ {7, 0, 3, 0, 43},
++ {7, 0, 3, 0, 42},
+ {7, 0, 3, 0, 41},
+- {7, 0, 2, 0, 61},
+- {7, 0, 2, 0, 59},
+- {7, 0, 2, 0, 57},
+- {7, 0, 2, 0, 56},
+- {7, 0, 2, 0, 54},
+- {7, 0, 2, 0, 53},
+- {7, 0, 2, 0, 51},
+- {7, 0, 2, 0, 50},
+- {7, 0, 2, 0, 48},
+- {7, 0, 2, 0, 47},
+- {7, 0, 2, 0, 46},
+- {7, 0, 2, 0, 44},
+- {7, 0, 2, 0, 43},
+- {7, 0, 2, 0, 42},
+- {7, 0, 2, 0, 41},
+- {7, 0, 2, 0, 39},
+- {7, 0, 2, 0, 38},
+- {7, 0, 2, 0, 37},
+- {7, 0, 2, 0, 36},
+- {7, 0, 2, 0, 35},
+- {7, 0, 2, 0, 34},
+- {7, 0, 2, 0, 33},
+- {7, 0, 2, 0, 32},
+- {7, 0, 1, 0, 63},
+- {7, 0, 1, 0, 61},
+- {7, 0, 1, 0, 59},
+- {7, 0, 1, 0, 57},
++ {3, 0, 3, 0, 56},
++ {3, 0, 3, 0, 54},
++ {3, 0, 3, 0, 53},
++ {3, 0, 3, 0, 51},
++ {3, 0, 3, 0, 50},
++ {3, 0, 3, 0, 48},
++ {3, 0, 3, 0, 47},
++ {3, 0, 3, 0, 46},
++ {3, 0, 3, 0, 44},
++ {3, 0, 3, 0, 43},
++ {3, 0, 3, 0, 42},
++ {3, 0, 3, 0, 41},
++ {3, 0, 3, 0, 39},
++ {3, 0, 3, 0, 38},
++ {3, 0, 3, 0, 37},
++ {3, 0, 3, 0, 36},
++ {3, 0, 3, 0, 35},
++ {3, 0, 3, 0, 34},
+ };
+
+ const struct lcnphy_tx_gain_tbl_entry dot11lcnphy_5GHz_gaintable_rev0[128] = {
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy/phytbl_lcn.h 2014-05-15 20:34:00.698033322 +0200
+@@ -20,6 +20,7 @@
+ extern const struct phytbl_info dot11lcnphytbl_rx_gain_info_rev0[];
+ extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev0;
+ extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313;
++extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_ipa;
+ extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_epa;
+ extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_epa_combo;
+ extern const struct phytbl_info dot11lcn_sw_ctrl_tbl_info_4313_bt_epa;
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/phy_shim.h 2014-05-15 20:34:00.706033378 +0200
+@@ -124,56 +124,49 @@
+
+ struct brcms_phy;
+
+-extern struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw,
+- struct brcms_info *wl,
+- struct brcms_c_info *wlc);
+-extern void wlc_phy_shim_detach(struct phy_shim_info *physhim);
++struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw,
++ struct brcms_info *wl,
++ struct brcms_c_info *wlc);
++void wlc_phy_shim_detach(struct phy_shim_info *physhim);
+
+ /* PHY to WL utility functions */
+-extern struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim,
+- void (*fn) (struct brcms_phy *pi),
+- void *arg, const char *name);
+-extern void wlapi_free_timer(struct wlapi_timer *t);
+-extern void wlapi_add_timer(struct wlapi_timer *t, uint ms, int periodic);
+-extern bool wlapi_del_timer(struct wlapi_timer *t);
+-extern void wlapi_intrson(struct phy_shim_info *physhim);
+-extern u32 wlapi_intrsoff(struct phy_shim_info *physhim);
+-extern void wlapi_intrsrestore(struct phy_shim_info *physhim,
+- u32 macintmask);
+-
+-extern void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset,
+- u16 v);
+-extern u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset);
+-extern void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx,
+- u16 mask, u16 val, int bands);
+-extern void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags);
+-extern void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim);
+-extern void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode);
+-extern void wlapi_enable_mac(struct phy_shim_info *physhim);
+-extern void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask,
+- u32 val);
+-extern void wlapi_bmac_phy_reset(struct phy_shim_info *physhim);
+-extern void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw);
+-extern void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk);
+-extern void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk);
+-extern void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on);
+-extern void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim);
+-extern void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *
+- physhim);
+-extern void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *
+- physhim);
+-extern void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int o,
+- int len, void *buf);
+-extern u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim,
+- u8 rate);
+-extern void wlapi_ucode_sample_init(struct phy_shim_info *physhim);
+-extern void wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint,
+- void *buf, int, u32 sel);
+-extern void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint,
+- const void *buf, int, u32);
+-
+-extern void wlapi_high_update_phy_mode(struct phy_shim_info *physhim,
+- u32 phy_mode);
+-extern u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
++struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim,
++ void (*fn)(struct brcms_phy *pi),
++ void *arg, const char *name);
++void wlapi_free_timer(struct wlapi_timer *t);
++void wlapi_add_timer(struct wlapi_timer *t, uint ms, int periodic);
++bool wlapi_del_timer(struct wlapi_timer *t);
++void wlapi_intrson(struct phy_shim_info *physhim);
++u32 wlapi_intrsoff(struct phy_shim_info *physhim);
++void wlapi_intrsrestore(struct phy_shim_info *physhim, u32 macintmask);
++
++void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v);
++u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset);
++void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, u16 val,
++ int bands);
++void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags);
++void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim);
++void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode);
++void wlapi_enable_mac(struct phy_shim_info *physhim);
++void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val);
++void wlapi_bmac_phy_reset(struct phy_shim_info *physhim);
++void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw);
++void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk);
++void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk);
++void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on);
++void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim);
++void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim);
++void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim);
++void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int o,
++ int len, void *buf);
++u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim, u8 rate);
++void wlapi_ucode_sample_init(struct phy_shim_info *physhim);
++void wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint, void *buf,
++ int, u32 sel);
++void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint, const void *buf,
++ int, u32);
++
++void wlapi_high_update_phy_mode(struct phy_shim_info *physhim, u32 phy_mode);
++u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim);
+
+ #endif /* _BRCM_PHY_SHIM_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/pmu.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/pmu.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/pmu.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/pmu.h 2014-05-15 20:34:00.714033437 +0200
+@@ -20,7 +20,7 @@
+
+ #include "types.h"
+
+-extern u16 si_pmu_fast_pwrup_delay(struct si_pub *sih);
+-extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
++u16 si_pmu_fast_pwrup_delay(struct si_pub *sih);
++u32 si_pmu_measure_alpclk(struct si_pub *sih);
+
+ #endif /* _BRCM_PMU_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/pub.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/pub.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/pub.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/pub.h 2014-05-15 20:34:00.714033437 +0200
+@@ -266,83 +266,76 @@
+ };
+
+ /* common functions for every port */
+-extern struct brcms_c_info *
+-brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
+- bool piomode, uint *perr);
+-extern uint brcms_c_detach(struct brcms_c_info *wlc);
+-extern int brcms_c_up(struct brcms_c_info *wlc);
+-extern uint brcms_c_down(struct brcms_c_info *wlc);
++struct brcms_c_info *brcms_c_attach(struct brcms_info *wl,
++ struct bcma_device *core, uint unit,
++ bool piomode, uint *perr);
++uint brcms_c_detach(struct brcms_c_info *wlc);
++int brcms_c_up(struct brcms_c_info *wlc);
++uint brcms_c_down(struct brcms_c_info *wlc);
+
+-extern bool brcms_c_chipmatch(struct bcma_device *core);
+-extern void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx);
+-extern void brcms_c_reset(struct brcms_c_info *wlc);
++bool brcms_c_chipmatch(struct bcma_device *core);
++void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx);
++void brcms_c_reset(struct brcms_c_info *wlc);
+
+-extern void brcms_c_intrson(struct brcms_c_info *wlc);
+-extern u32 brcms_c_intrsoff(struct brcms_c_info *wlc);
+-extern void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask);
+-extern bool brcms_c_intrsupd(struct brcms_c_info *wlc);
+-extern bool brcms_c_isr(struct brcms_c_info *wlc);
+-extern bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded);
+-extern bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc,
+- struct sk_buff *sdu,
+- struct ieee80211_hw *hw);
+-extern bool brcms_c_aggregatable(struct brcms_c_info *wlc, u8 tid);
+-extern void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx,
+- int val);
+-extern int brcms_c_get_header_len(void);
+-extern void brcms_c_set_addrmatch(struct brcms_c_info *wlc,
+- int match_reg_offset,
+- const u8 *addr);
+-extern void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
+- const struct ieee80211_tx_queue_params *arg,
+- bool suspend);
+-extern struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc);
+-extern void brcms_c_ampdu_flush(struct brcms_c_info *wlc,
+- struct ieee80211_sta *sta, u16 tid);
+-extern void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
+- u8 ba_wsize, uint max_rx_ampdu_bytes);
+-extern int brcms_c_module_register(struct brcms_pub *pub,
+- const char *name, struct brcms_info *hdl,
+- int (*down_fn)(void *handle));
+-extern int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
+- struct brcms_info *hdl);
+-extern void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc);
+-extern void brcms_c_enable_mac(struct brcms_c_info *wlc);
+-extern void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state);
+-extern void brcms_c_scan_start(struct brcms_c_info *wlc);
+-extern void brcms_c_scan_stop(struct brcms_c_info *wlc);
+-extern int brcms_c_get_curband(struct brcms_c_info *wlc);
+-extern int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel);
+-extern int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl);
+-extern void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
++void brcms_c_intrson(struct brcms_c_info *wlc);
++u32 brcms_c_intrsoff(struct brcms_c_info *wlc);
++void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask);
++bool brcms_c_intrsupd(struct brcms_c_info *wlc);
++bool brcms_c_isr(struct brcms_c_info *wlc);
++bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded);
++bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
++ struct ieee80211_hw *hw);
++bool brcms_c_aggregatable(struct brcms_c_info *wlc, u8 tid);
++void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val);
++int brcms_c_get_header_len(void);
++void brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
++ const u8 *addr);
++void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
++ const struct ieee80211_tx_queue_params *arg,
++ bool suspend);
++struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc);
++void brcms_c_ampdu_flush(struct brcms_c_info *wlc, struct ieee80211_sta *sta,
++ u16 tid);
++void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc, u8 tid,
++ u8 ba_wsize, uint max_rx_ampdu_bytes);
++int brcms_c_module_register(struct brcms_pub *pub, const char *name,
++ struct brcms_info *hdl,
++ int (*down_fn)(void *handle));
++int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
++ struct brcms_info *hdl);
++void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc);
++void brcms_c_enable_mac(struct brcms_c_info *wlc);
++void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state);
++void brcms_c_scan_start(struct brcms_c_info *wlc);
++void brcms_c_scan_stop(struct brcms_c_info *wlc);
++int brcms_c_get_curband(struct brcms_c_info *wlc);
++int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel);
++int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl);
++void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
+ struct brcm_rateset *currs);
+-extern int brcms_c_set_rateset(struct brcms_c_info *wlc,
+- struct brcm_rateset *rs);
+-extern int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period);
+-extern u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx);
+-extern void brcms_c_set_shortslot_override(struct brcms_c_info *wlc,
++int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs);
++int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period);
++u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx);
++void brcms_c_set_shortslot_override(struct brcms_c_info *wlc,
+ s8 sslot_override);
+-extern void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc,
+- u8 interval);
+-extern u64 brcms_c_tsf_get(struct brcms_c_info *wlc);
+-extern void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf);
+-extern int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr);
+-extern int brcms_c_get_tx_power(struct brcms_c_info *wlc);
+-extern bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc);
+-extern void brcms_c_mute(struct brcms_c_info *wlc, bool on);
+-extern bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc);
+-extern void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr);
+-extern void brcms_c_start_ap(struct brcms_c_info *wlc, u8 *addr,
+- const u8 *bssid, u8 *ssid, size_t ssid_len);
+-extern void brcms_c_start_adhoc(struct brcms_c_info *wlc, u8 *addr);
+-extern void brcms_c_update_beacon(struct brcms_c_info *wlc);
+-extern void brcms_c_set_new_beacon(struct brcms_c_info *wlc,
+- struct sk_buff *beacon, u16 tim_offset,
+- u16 dtim_period);
+-extern void brcms_c_set_new_probe_resp(struct brcms_c_info *wlc,
+- struct sk_buff *probe_resp);
+-extern void brcms_c_enable_probe_resp(struct brcms_c_info *wlc, bool enable);
+-extern void brcms_c_set_ssid(struct brcms_c_info *wlc, u8 *ssid,
+- size_t ssid_len);
++void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval);
++u64 brcms_c_tsf_get(struct brcms_c_info *wlc);
++void brcms_c_tsf_set(struct brcms_c_info *wlc, u64 tsf);
++int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr);
++int brcms_c_get_tx_power(struct brcms_c_info *wlc);
++bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc);
++void brcms_c_mute(struct brcms_c_info *wlc, bool on);
++bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc);
++void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr);
++void brcms_c_start_ap(struct brcms_c_info *wlc, u8 *addr, const u8 *bssid,
++ u8 *ssid, size_t ssid_len);
++void brcms_c_start_adhoc(struct brcms_c_info *wlc, u8 *addr);
++void brcms_c_update_beacon(struct brcms_c_info *wlc);
++void brcms_c_set_new_beacon(struct brcms_c_info *wlc, struct sk_buff *beacon,
++ u16 tim_offset, u16 dtim_period);
++void brcms_c_set_new_probe_resp(struct brcms_c_info *wlc,
++ struct sk_buff *probe_resp);
++void brcms_c_enable_probe_resp(struct brcms_c_info *wlc, bool enable);
++void brcms_c_set_ssid(struct brcms_c_info *wlc, u8 *ssid, size_t ssid_len);
+
+ #endif /* _BRCM_PUB_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/rate.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/rate.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/rate.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/rate.h 2014-05-15 20:34:00.714033437 +0200
+@@ -216,34 +216,30 @@
+
+ /* sanitize, and sort a rateset with the basic bit(s) preserved, validate
+ * rateset */
+-extern bool
+-brcms_c_rate_hwrs_filter_sort_validate(struct brcms_c_rateset *rs,
+- const struct brcms_c_rateset *hw_rs,
+- bool check_brate, u8 txstreams);
++bool brcms_c_rate_hwrs_filter_sort_validate(struct brcms_c_rateset *rs,
++ const struct brcms_c_rateset *hw_rs,
++ bool check_brate, u8 txstreams);
+ /* copy rateset src to dst as-is (no masking or sorting) */
+-extern void brcms_c_rateset_copy(const struct brcms_c_rateset *src,
+- struct brcms_c_rateset *dst);
++void brcms_c_rateset_copy(const struct brcms_c_rateset *src,
++ struct brcms_c_rateset *dst);
+
+ /* would be nice to have these documented ... */
+-extern u32 brcms_c_compute_rspec(struct d11rxhdr *rxh, u8 *plcp);
++u32 brcms_c_compute_rspec(struct d11rxhdr *rxh, u8 *plcp);
+
+-extern void brcms_c_rateset_filter(struct brcms_c_rateset *src,
+- struct brcms_c_rateset *dst, bool basic_only, u8 rates, uint xmask,
+- bool mcsallow);
+-
+-extern void
+-brcms_c_rateset_default(struct brcms_c_rateset *rs_tgt,
+- const struct brcms_c_rateset *rs_hw, uint phy_type,
+- int bandtype, bool cck_only, uint rate_mask,
+- bool mcsallow, u8 bw, u8 txstreams);
+-
+-extern s16 brcms_c_rate_legacy_phyctl(uint rate);
+-
+-extern void brcms_c_rateset_mcs_upd(struct brcms_c_rateset *rs, u8 txstreams);
+-extern void brcms_c_rateset_mcs_clear(struct brcms_c_rateset *rateset);
+-extern void brcms_c_rateset_mcs_build(struct brcms_c_rateset *rateset,
+- u8 txstreams);
+-extern void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset,
+- u8 bw);
++void brcms_c_rateset_filter(struct brcms_c_rateset *src,
++ struct brcms_c_rateset *dst, bool basic_only,
++ u8 rates, uint xmask, bool mcsallow);
++
++void brcms_c_rateset_default(struct brcms_c_rateset *rs_tgt,
++ const struct brcms_c_rateset *rs_hw, uint phy_type,
++ int bandtype, bool cck_only, uint rate_mask,
++ bool mcsallow, u8 bw, u8 txstreams);
++
++s16 brcms_c_rate_legacy_phyctl(uint rate);
++
++void brcms_c_rateset_mcs_upd(struct brcms_c_rateset *rs, u8 txstreams);
++void brcms_c_rateset_mcs_clear(struct brcms_c_rateset *rateset);
++void brcms_c_rateset_mcs_build(struct brcms_c_rateset *rateset, u8 txstreams);
++void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset, u8 bw);
+
+ #endif /* _BRCM_RATE_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/stf.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/stf.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/stf.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/stf.h 2014-05-15 20:34:00.714033437 +0200
+@@ -19,24 +19,19 @@
+
+ #include "types.h"
+
+-extern int brcms_c_stf_attach(struct brcms_c_info *wlc);
+-extern void brcms_c_stf_detach(struct brcms_c_info *wlc);
++int brcms_c_stf_attach(struct brcms_c_info *wlc);
++void brcms_c_stf_detach(struct brcms_c_info *wlc);
+
+-extern void brcms_c_tempsense_upd(struct brcms_c_info *wlc);
+-extern void brcms_c_stf_ss_algo_channel_get(struct brcms_c_info *wlc,
+- u16 *ss_algo_channel,
+- u16 chanspec);
+-extern int brcms_c_stf_ss_update(struct brcms_c_info *wlc,
+- struct brcms_band *band);
+-extern void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
+-extern int brcms_c_stf_txchain_set(struct brcms_c_info *wlc, s32 int_val,
+- bool force);
+-extern bool brcms_c_stf_stbc_rx_set(struct brcms_c_info *wlc, s32 int_val);
+-extern void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
+-extern void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc);
+-extern u16 brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc,
+- u32 rspec);
+-extern u16 brcms_c_stf_d11hdrs_phyctl_txant(struct brcms_c_info *wlc,
+- u32 rspec);
++void brcms_c_tempsense_upd(struct brcms_c_info *wlc);
++void brcms_c_stf_ss_algo_channel_get(struct brcms_c_info *wlc,
++ u16 *ss_algo_channel, u16 chanspec);
++int brcms_c_stf_ss_update(struct brcms_c_info *wlc, struct brcms_band *band);
++void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
++int brcms_c_stf_txchain_set(struct brcms_c_info *wlc, s32 int_val, bool force);
++bool brcms_c_stf_stbc_rx_set(struct brcms_c_info *wlc, s32 int_val);
++void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc);
++void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc);
++u16 brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc, u32 rspec);
++u16 brcms_c_stf_d11hdrs_phyctl_txant(struct brcms_c_info *wlc, u32 rspec);
+
+ #endif /* _BRCM_STF_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/ucode_loader.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/ucode_loader.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/brcmsmac/ucode_loader.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/brcmsmac/ucode_loader.h 2014-05-15 20:34:00.714033437 +0200
+@@ -43,16 +43,14 @@
+ u32 *bcm43xx_bomminor;
+ };
+
+-extern int
+-brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode);
++int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode);
+
+-extern void brcms_ucode_data_free(struct brcms_ucode *ucode);
++void brcms_ucode_data_free(struct brcms_ucode *ucode);
+
+-extern int brcms_ucode_init_buf(struct brcms_info *wl, void **pbuf,
+- unsigned int idx);
+-extern int brcms_ucode_init_uint(struct brcms_info *wl, size_t *n_bytes,
+- unsigned int idx);
+-extern void brcms_ucode_free_buf(void *);
+-extern int brcms_check_firmwares(struct brcms_info *wl);
++int brcms_ucode_init_buf(struct brcms_info *wl, void **pbuf, unsigned int idx);
++int brcms_ucode_init_uint(struct brcms_info *wl, size_t *n_bytes,
++ unsigned int idx);
++void brcms_ucode_free_buf(void *);
++int brcms_check_firmwares(struct brcms_info *wl);
+
+ #endif /* _BRCM_UCODE_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h 2014-05-15 20:34:00.714033437 +0200
+@@ -41,5 +41,7 @@
+ #define BCM4331_CHIP_ID 0x4331
+ #define BCM4334_CHIP_ID 0x4334
+ #define BCM4335_CHIP_ID 0x4335
++#define BCM43362_CHIP_ID 43362
++#define BCM4339_CHIP_ID 0x4339
+
+ #endif /* _BRCM_HW_IDS_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/include/brcmu_d11.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/include/brcmu_d11.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/include/brcmu_d11.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/include/brcmu_d11.h 2014-05-15 20:34:00.718033465 +0200
+@@ -140,6 +140,6 @@
+ void (*decchspec)(struct brcmu_chan *ch);
+ };
+
+-extern void brcmu_d11_attach(struct brcmu_d11inf *d11inf);
++void brcmu_d11_attach(struct brcmu_d11inf *d11inf);
+
+ #endif /* _BRCMU_CHANNELS_H_ */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/include/brcmu_utils.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/include/brcmu_utils.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/include/brcmu_utils.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/include/brcmu_utils.h 2014-05-15 20:34:00.718033465 +0200
+@@ -114,31 +114,29 @@
+ return skb_peek_tail(&pq->q[prec].skblist);
+ }
+
+-extern struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec,
+- struct sk_buff *p);
+-extern struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
+- struct sk_buff *p);
+-extern struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec);
+-extern struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec);
+-extern struct sk_buff *brcmu_pktq_pdeq_match(struct pktq *pq, int prec,
+- bool (*match_fn)(struct sk_buff *p,
+- void *arg),
+- void *arg);
++struct sk_buff *brcmu_pktq_penq(struct pktq *pq, int prec, struct sk_buff *p);
++struct sk_buff *brcmu_pktq_penq_head(struct pktq *pq, int prec,
++ struct sk_buff *p);
++struct sk_buff *brcmu_pktq_pdeq(struct pktq *pq, int prec);
++struct sk_buff *brcmu_pktq_pdeq_tail(struct pktq *pq, int prec);
++struct sk_buff *brcmu_pktq_pdeq_match(struct pktq *pq, int prec,
++ bool (*match_fn)(struct sk_buff *p,
++ void *arg),
++ void *arg);
+
+ /* packet primitives */
+-extern struct sk_buff *brcmu_pkt_buf_get_skb(uint len);
+-extern void brcmu_pkt_buf_free_skb(struct sk_buff *skb);
++struct sk_buff *brcmu_pkt_buf_get_skb(uint len);
++void brcmu_pkt_buf_free_skb(struct sk_buff *skb);
+
+ /* Empty the queue at particular precedence level */
+ /* callback function fn(pkt, arg) returns true if pkt belongs to if */
+-extern void brcmu_pktq_pflush(struct pktq *pq, int prec,
+- bool dir, bool (*fn)(struct sk_buff *, void *), void *arg);
++void brcmu_pktq_pflush(struct pktq *pq, int prec, bool dir,
++ bool (*fn)(struct sk_buff *, void *), void *arg);
+
+ /* operations on a set of precedences in packet queue */
+
+-extern int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp);
+-extern struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp,
+- int *prec_out);
++int brcmu_pktq_mlen(struct pktq *pq, uint prec_bmp);
++struct sk_buff *brcmu_pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
+
+ /* operations on packet queue as a whole */
+
+@@ -167,11 +165,11 @@
+ return pq->len == 0;
+ }
+
+-extern void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len);
++void brcmu_pktq_init(struct pktq *pq, int num_prec, int max_len);
+ /* prec_out may be NULL if caller is not interested in return value */
+-extern struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out);
+-extern void brcmu_pktq_flush(struct pktq *pq, bool dir,
+- bool (*fn)(struct sk_buff *, void *), void *arg);
++struct sk_buff *brcmu_pktq_peek_tail(struct pktq *pq, int *prec_out);
++void brcmu_pktq_flush(struct pktq *pq, bool dir,
++ bool (*fn)(struct sk_buff *, void *), void *arg);
+
+ /* externs */
+ /* ip address */
+@@ -204,13 +202,13 @@
+ /* externs */
+ /* format/print */
+ #ifdef DEBUG
+-extern void brcmu_prpkt(const char *msg, struct sk_buff *p0);
++void brcmu_prpkt(const char *msg, struct sk_buff *p0);
+ #else
+ #define brcmu_prpkt(a, b)
+ #endif /* DEBUG */
+
+ #ifdef DEBUG
+-extern __printf(3, 4)
++__printf(3, 4)
+ void brcmu_dbg_hex_dump(const void *data, size_t size, const char *fmt, ...);
+ #else
+ __printf(3, 4)
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/include/brcmu_wifi.h linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/include/brcmu_wifi.h
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/include/brcmu_wifi.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/include/brcmu_wifi.h 2014-05-15 20:34:00.718033465 +0200
+@@ -82,6 +82,20 @@
+ #define WLC_N_BW_40ALL 1
+ #define WLC_N_BW_20IN2G_40IN5G 2
+
++#define WLC_BW_20MHZ_BIT BIT(0)
++#define WLC_BW_40MHZ_BIT BIT(1)
++#define WLC_BW_80MHZ_BIT BIT(2)
++#define WLC_BW_160MHZ_BIT BIT(3)
++
++/* Bandwidth capabilities */
++#define WLC_BW_CAP_20MHZ (WLC_BW_20MHZ_BIT)
++#define WLC_BW_CAP_40MHZ (WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
++#define WLC_BW_CAP_80MHZ (WLC_BW_80MHZ_BIT|WLC_BW_40MHZ_BIT| \
++ WLC_BW_20MHZ_BIT)
++#define WLC_BW_CAP_160MHZ (WLC_BW_160MHZ_BIT|WLC_BW_80MHZ_BIT| \
++ WLC_BW_40MHZ_BIT|WLC_BW_20MHZ_BIT)
++#define WLC_BW_CAP_UNRESTRICTED 0xFF
++
+ /* band types */
+ #define WLC_BAND_AUTO 0 /* auto-select */
+ #define WLC_BAND_5G 1 /* 5 Ghz */
+diff -Nur linux-3.10.30.orig/drivers/net/wireless/brcm80211/Kconfig linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/Kconfig
+--- linux-3.10.30.orig/drivers/net/wireless/brcm80211/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/net/wireless/brcm80211/Kconfig 2014-05-15 20:34:00.550032255 +0200
+@@ -4,11 +4,12 @@
+ config BRCMSMAC
+ tristate "Broadcom IEEE802.11n PCIe SoftMAC WLAN driver"
+ depends on MAC80211
+- depends on BCMA
++ depends on BCMA_POSSIBLE
++ select BCMA
++ select NEW_LEDS if BCMA_DRIVER_GPIO
++ select LEDS_CLASS if BCMA_DRIVER_GPIO
+ select BRCMUTIL
+ select FW_LOADER
+- select CRC_CCITT
+- select CRC8
+ select CORDIC
+ ---help---
+ This module adds support for PCIe wireless adapters based on Broadcom
+@@ -28,7 +29,7 @@
+
+ config BRCMFMAC_SDIO
+ bool "SDIO bus interface support for FullMAC driver"
+- depends on MMC
++ depends on (MMC = y || MMC = BRCMFMAC)
+ depends on BRCMFMAC
+ select FW_LOADER
+ default y
+@@ -39,7 +40,7 @@
+
+ config BRCMFMAC_USB
+ bool "USB bus interface support for FullMAC driver"
+- depends on USB
++ depends on (USB = y || USB = BRCMFMAC)
+ depends on BRCMFMAC
+ select FW_LOADER
+ ---help---
+diff -Nur linux-3.10.30.orig/drivers/of/address.c linux-linaro-stable-mx6/drivers/of/address.c
+--- linux-3.10.30.orig/drivers/of/address.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/of/address.c 2014-05-15 20:34:01.626040008 +0200
+@@ -223,6 +223,73 @@
+ return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
+ }
+ EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
++
++int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++ struct device_node *node)
++{
++ const int na = 3, ns = 2;
++ int rlen;
++
++ parser->node = node;
++ parser->pna = of_n_addr_cells(node);
++ parser->np = parser->pna + na + ns;
++
++ parser->range = of_get_property(node, "ranges", &rlen);
++ if (parser->range == NULL)
++ return -ENOENT;
++
++ parser->end = parser->range + rlen / sizeof(__be32);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
++
++struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
++ struct of_pci_range *range)
++{
++ const int na = 3, ns = 2;
++
++ if (!range)
++ return NULL;
++
++ if (!parser->range || parser->range + parser->np > parser->end)
++ return NULL;
++
++ range->pci_space = parser->range[0];
++ range->flags = of_bus_pci_get_flags(parser->range);
++ range->pci_addr = of_read_number(parser->range + 1, ns);
++ range->cpu_addr = of_translate_address(parser->node,
++ parser->range + na);
++ range->size = of_read_number(parser->range + parser->pna + na, ns);
++
++ parser->range += parser->np;
++
++ /* Now consume following elements while they are contiguous */
++ while (parser->range + parser->np <= parser->end) {
++ u32 flags, pci_space;
++ u64 pci_addr, cpu_addr, size;
++
++ pci_space = be32_to_cpup(parser->range);
++ flags = of_bus_pci_get_flags(parser->range);
++ pci_addr = of_read_number(parser->range + 1, ns);
++ cpu_addr = of_translate_address(parser->node,
++ parser->range + na);
++ size = of_read_number(parser->range + parser->pna + na, ns);
++
++ if (flags != range->flags)
++ break;
++ if (pci_addr != range->pci_addr + range->size ||
++ cpu_addr != range->cpu_addr + range->size)
++ break;
++
++ range->size += size;
++ parser->range += parser->np;
++ }
++
++ return range;
++}
++EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
++
+ #endif /* CONFIG_PCI */
+
+ /*
+diff -Nur linux-3.10.30.orig/drivers/of/base.c linux-linaro-stable-mx6/drivers/of/base.c
+--- linux-3.10.30.orig/drivers/of/base.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/of/base.c 2014-05-15 20:34:01.626040008 +0200
+@@ -18,6 +18,7 @@
+ * 2 of the License, or (at your option) any later version.
+ */
+ #include <linux/ctype.h>
++#include <linux/cpu.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/spinlock.h>
+@@ -32,6 +33,7 @@
+ EXPORT_SYMBOL(of_allnodes);
+ struct device_node *of_chosen;
+ struct device_node *of_aliases;
++static struct device_node *of_stdout;
+
+ DEFINE_MUTEX(of_aliases_mutex);
+
+@@ -230,6 +232,100 @@
+ }
+ EXPORT_SYMBOL(of_get_property);
+
++/*
++ * arch_match_cpu_phys_id - Match the given logical CPU and physical id
++ *
++ * @cpu: logical cpu index of a core/thread
++ * @phys_id: physical identifier of a core/thread
++ *
++ * CPU logical to physical index mapping is architecture specific.
++ * However this __weak function provides a default match of physical
++ * id to logical cpu index. phys_id provided here is usually values read
++ * from the device tree which must match the hardware internal registers.
++ *
++ * Returns true if the physical identifier and the logical cpu index
++ * correspond to the same core/thread, false otherwise.
++ */
++bool __weak arch_match_cpu_phys_id(int cpu, u64 phys_id)
++{
++ return (u32)phys_id == cpu;
++}
++
++/**
++ * Checks if the given "prop_name" property holds the physical id of the
++ * core/thread corresponding to the logical cpu 'cpu'. If 'thread' is not
++ * NULL, local thread number within the core is returned in it.
++ */
++static bool __of_find_n_match_cpu_property(struct device_node *cpun,
++ const char *prop_name, int cpu, unsigned int *thread)
++{
++ const __be32 *cell;
++ int ac, prop_len, tid;
++ u64 hwid;
++
++ ac = of_n_addr_cells(cpun);
++ cell = of_get_property(cpun, prop_name, &prop_len);
++ if (!cell)
++ return false;
++ prop_len /= sizeof(*cell);
++ for (tid = 0; tid < prop_len; tid++) {
++ hwid = of_read_number(cell, ac);
++ if (arch_match_cpu_phys_id(cpu, hwid)) {
++ if (thread)
++ *thread = tid;
++ return true;
++ }
++ cell += ac;
++ }
++ return false;
++}
++
++/**
++ * of_get_cpu_node - Get device node associated with the given logical CPU
++ *
++ * @cpu: CPU number(logical index) for which device node is required
++ * @thread: if not NULL, local thread number within the physical core is
++ * returned
++ *
++ * The main purpose of this function is to retrieve the device node for the
++ * given logical CPU index. It should be used to initialize the of_node in
++ * cpu device. Once of_node in cpu device is populated, all the further
++ * references can use that instead.
++ *
++ * CPU logical to physical index mapping is architecture specific and is built
++ * before booting secondary cores. This function uses arch_match_cpu_phys_id
++ * which can be overridden by architecture specific implementation.
++ *
++ * Returns a node pointer for the logical cpu if found, else NULL.
++ */
++struct device_node *of_get_cpu_node(int cpu, unsigned int *thread)
++{
++ struct device_node *cpun, *cpus;
++
++ cpus = of_find_node_by_path("/cpus");
++ if (!cpus) {
++ pr_warn("Missing cpus node, bailing out\n");
++ return NULL;
++ }
++
++ for_each_child_of_node(cpus, cpun) {
++ if (of_node_cmp(cpun->type, "cpu"))
++ continue;
++ /* Check for non-standard "ibm,ppc-interrupt-server#s" property
++ * for thread ids on PowerPC. If it doesn't exist fallback to
++ * standard "reg" property.
++ */
++ if (IS_ENABLED(CONFIG_PPC) &&
++ __of_find_n_match_cpu_property(cpun,
++ "ibm,ppc-interrupt-server#s", cpu, thread))
++ return cpun;
++ if (__of_find_n_match_cpu_property(cpun, "reg", cpu, thread))
++ return cpun;
++ }
++ return NULL;
++}
++EXPORT_SYMBOL(of_get_cpu_node);
++
+ /** Checks if the given "compat" string matches one of the strings in
+ * the device's "compatible" property
+ */
+@@ -1080,65 +1176,10 @@
+ }
+ EXPORT_SYMBOL_GPL(of_property_count_strings);
+
+-/**
+- * of_parse_phandle - Resolve a phandle property to a device_node pointer
+- * @np: Pointer to device node holding phandle property
+- * @phandle_name: Name of property holding a phandle value
+- * @index: For properties holding a table of phandles, this is the index into
+- * the table
+- *
+- * Returns the device_node pointer with refcount incremented. Use
+- * of_node_put() on it when done.
+- */
+-struct device_node *of_parse_phandle(const struct device_node *np,
+- const char *phandle_name, int index)
+-{
+- const __be32 *phandle;
+- int size;
+-
+- phandle = of_get_property(np, phandle_name, &size);
+- if ((!phandle) || (size < sizeof(*phandle) * (index + 1)))
+- return NULL;
+-
+- return of_find_node_by_phandle(be32_to_cpup(phandle + index));
+-}
+-EXPORT_SYMBOL(of_parse_phandle);
+-
+-/**
+- * of_parse_phandle_with_args() - Find a node pointed by phandle in a list
+- * @np: pointer to a device tree node containing a list
+- * @list_name: property name that contains a list
+- * @cells_name: property name that specifies phandles' arguments count
+- * @index: index of a phandle to parse out
+- * @out_args: optional pointer to output arguments structure (will be filled)
+- *
+- * This function is useful to parse lists of phandles and their arguments.
+- * Returns 0 on success and fills out_args, on error returns appropriate
+- * errno value.
+- *
+- * Caller is responsible to call of_node_put() on the returned out_args->node
+- * pointer.
+- *
+- * Example:
+- *
+- * phandle1: node1 {
+- * #list-cells = <2>;
+- * }
+- *
+- * phandle2: node2 {
+- * #list-cells = <1>;
+- * }
+- *
+- * node3 {
+- * list = <&phandle1 1 2 &phandle2 3>;
+- * }
+- *
+- * To get a device_node of the `node2' node you may call this:
+- * of_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args);
+- */
+ static int __of_parse_phandle_with_args(const struct device_node *np,
+ const char *list_name,
+- const char *cells_name, int index,
++ const char *cells_name,
++ int cell_count, int index,
+ struct of_phandle_args *out_args)
+ {
+ const __be32 *list, *list_end;
+@@ -1166,19 +1207,32 @@
+ if (phandle) {
+ /*
+ * Find the provider node and parse the #*-cells
+- * property to determine the argument length
++ * property to determine the argument length.
++ *
++ * This is not needed if the cell count is hard-coded
++ * (i.e. cells_name not set, but cell_count is set),
++ * except when we're going to return the found node
++ * below.
+ */
+- node = of_find_node_by_phandle(phandle);
+- if (!node) {
+- pr_err("%s: could not find phandle\n",
+- np->full_name);
+- goto err;
++ if (cells_name || cur_index == index) {
++ node = of_find_node_by_phandle(phandle);
++ if (!node) {
++ pr_err("%s: could not find phandle\n",
++ np->full_name);
++ goto err;
++ }
+ }
+- if (of_property_read_u32(node, cells_name, &count)) {
+- pr_err("%s: could not get %s for %s\n",
+- np->full_name, cells_name,
+- node->full_name);
+- goto err;
++
++ if (cells_name) {
++ if (of_property_read_u32(node, cells_name,
++ &count)) {
++ pr_err("%s: could not get %s for %s\n",
++ np->full_name, cells_name,
++ node->full_name);
++ goto err;
++ }
++ } else {
++ count = cell_count;
+ }
+
+ /*
+@@ -1238,17 +1292,117 @@
+ return rc;
+ }
+
++/**
++ * of_parse_phandle - Resolve a phandle property to a device_node pointer
++ * @np: Pointer to device node holding phandle property
++ * @phandle_name: Name of property holding a phandle value
++ * @index: For properties holding a table of phandles, this is the index into
++ * the table
++ *
++ * Returns the device_node pointer with refcount incremented. Use
++ * of_node_put() on it when done.
++ */
++struct device_node *of_parse_phandle(const struct device_node *np,
++ const char *phandle_name, int index)
++{
++ struct of_phandle_args args;
++
++ if (index < 0)
++ return NULL;
++
++ if (__of_parse_phandle_with_args(np, phandle_name, NULL, 0,
++ index, &args))
++ return NULL;
++
++ return args.np;
++}
++EXPORT_SYMBOL(of_parse_phandle);
++
++/**
++ * of_parse_phandle_with_args() - Find a node pointed by phandle in a list
++ * @np: pointer to a device tree node containing a list
++ * @list_name: property name that contains a list
++ * @cells_name: property name that specifies phandles' arguments count
++ * @index: index of a phandle to parse out
++ * @out_args: optional pointer to output arguments structure (will be filled)
++ *
++ * This function is useful to parse lists of phandles and their arguments.
++ * Returns 0 on success and fills out_args, on error returns appropriate
++ * errno value.
++ *
++ * Caller is responsible to call of_node_put() on the returned out_args->node
++ * pointer.
++ *
++ * Example:
++ *
++ * phandle1: node1 {
++ * #list-cells = <2>;
++ * }
++ *
++ * phandle2: node2 {
++ * #list-cells = <1>;
++ * }
++ *
++ * node3 {
++ * list = <&phandle1 1 2 &phandle2 3>;
++ * }
++ *
++ * To get a device_node of the `node2' node you may call this:
++ * of_parse_phandle_with_args(node3, "list", "#list-cells", 1, &args);
++ */
+ int of_parse_phandle_with_args(const struct device_node *np, const char *list_name,
+ const char *cells_name, int index,
+ struct of_phandle_args *out_args)
+ {
+ if (index < 0)
+ return -EINVAL;
+- return __of_parse_phandle_with_args(np, list_name, cells_name, index, out_args);
++ return __of_parse_phandle_with_args(np, list_name, cells_name, 0,
++ index, out_args);
+ }
+ EXPORT_SYMBOL(of_parse_phandle_with_args);
+
+ /**
++ * of_parse_phandle_with_fixed_args() - Find a node pointed by phandle in a list
++ * @np: pointer to a device tree node containing a list
++ * @list_name: property name that contains a list
++ * @cell_count: number of argument cells following the phandle
++ * @index: index of a phandle to parse out
++ * @out_args: optional pointer to output arguments structure (will be filled)
++ *
++ * This function is useful to parse lists of phandles and their arguments.
++ * Returns 0 on success and fills out_args, on error returns appropriate
++ * errno value.
++ *
++ * Caller is responsible to call of_node_put() on the returned out_args->node
++ * pointer.
++ *
++ * Example:
++ *
++ * phandle1: node1 {
++ * }
++ *
++ * phandle2: node2 {
++ * }
++ *
++ * node3 {
++ * list = <&phandle1 0 2 &phandle2 2 3>;
++ * }
++ *
++ * To get a device_node of the `node2' node you may call this:
++ * of_parse_phandle_with_fixed_args(node3, "list", 2, 1, &args);
++ */
++int of_parse_phandle_with_fixed_args(const struct device_node *np,
++ const char *list_name, int cell_count,
++ int index, struct of_phandle_args *out_args)
++{
++ if (index < 0)
++ return -EINVAL;
++ return __of_parse_phandle_with_args(np, list_name, NULL, cell_count,
++ index, out_args);
++}
++EXPORT_SYMBOL(of_parse_phandle_with_fixed_args);
++
++/**
+ * of_count_phandle_with_args() - Find the number of phandles references in a property
+ * @np: pointer to a device tree node containing a list
+ * @list_name: property name that contains a list
+@@ -1266,7 +1420,8 @@
+ int of_count_phandle_with_args(const struct device_node *np, const char *list_name,
+ const char *cells_name)
+ {
+- return __of_parse_phandle_with_args(np, list_name, cells_name, -1, NULL);
++ return __of_parse_phandle_with_args(np, list_name, cells_name, 0, -1,
++ NULL);
+ }
+ EXPORT_SYMBOL(of_count_phandle_with_args);
+
+@@ -1595,6 +1750,15 @@
+ of_chosen = of_find_node_by_path("/chosen");
+ if (of_chosen == NULL)
+ of_chosen = of_find_node_by_path("/chosen@0");
++
++ if (of_chosen) {
++ const char *name;
++
++ name = of_get_property(of_chosen, "linux,stdout-path", NULL);
++ if (name)
++ of_stdout = of_find_node_by_path(name);
++ }
++
+ of_aliases = of_find_node_by_path("/aliases");
+ if (!of_aliases)
+ return;
+@@ -1704,3 +1868,19 @@
+ return curv;
+ }
+ EXPORT_SYMBOL_GPL(of_prop_next_string);
++
++/**
++ * of_device_is_stdout_path - check if a device node matches the
++ * linux,stdout-path property
++ *
++ * Check if this device node matches the linux,stdout-path property
++ * in the chosen node. return true if yes, false otherwise.
++ */
++int of_device_is_stdout_path(struct device_node *dn)
++{
++ if (!of_stdout)
++ return false;
++
++ return of_stdout == dn;
++}
++EXPORT_SYMBOL_GPL(of_device_is_stdout_path);
+diff -Nur linux-3.10.30.orig/drivers/of/fdt.c linux-linaro-stable-mx6/drivers/of/fdt.c
+--- linux-3.10.30.orig/drivers/of/fdt.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/of/fdt.c 2014-05-15 20:34:01.634040066 +0200
+@@ -125,13 +125,13 @@
+ return score;
+ }
+
+-static void *unflatten_dt_alloc(unsigned long *mem, unsigned long size,
++static void *unflatten_dt_alloc(void **mem, unsigned long size,
+ unsigned long align)
+ {
+ void *res;
+
+- *mem = ALIGN(*mem, align);
+- res = (void *)*mem;
++ *mem = PTR_ALIGN(*mem, align);
++ res = *mem;
+ *mem += size;
+
+ return res;
+@@ -146,9 +146,9 @@
+ * @allnextpp: pointer to ->allnext from last allocated device_node
+ * @fpsize: Size of the node path up at the current depth.
+ */
+-static unsigned long unflatten_dt_node(struct boot_param_header *blob,
+- unsigned long mem,
+- unsigned long *p,
++static void * unflatten_dt_node(struct boot_param_header *blob,
++ void *mem,
++ void **p,
+ struct device_node *dad,
+ struct device_node ***allnextpp,
+ unsigned long fpsize)
+@@ -161,15 +161,15 @@
+ int has_name = 0;
+ int new_format = 0;
+
+- tag = be32_to_cpup((__be32 *)(*p));
++ tag = be32_to_cpup(*p);
+ if (tag != OF_DT_BEGIN_NODE) {
+ pr_err("Weird tag at start of node: %x\n", tag);
+ return mem;
+ }
+ *p += 4;
+- pathp = (char *)*p;
++ pathp = *p;
+ l = allocl = strlen(pathp) + 1;
+- *p = ALIGN(*p + l, 4);
++ *p = PTR_ALIGN(*p + l, 4);
+
+ /* version 0x10 has a more compact unit name here instead of the full
+ * path. we accumulate the full path size using "fpsize", we'll rebuild
+@@ -239,7 +239,7 @@
+ u32 sz, noff;
+ char *pname;
+
+- tag = be32_to_cpup((__be32 *)(*p));
++ tag = be32_to_cpup(*p);
+ if (tag == OF_DT_NOP) {
+ *p += 4;
+ continue;
+@@ -247,11 +247,11 @@
+ if (tag != OF_DT_PROP)
+ break;
+ *p += 4;
+- sz = be32_to_cpup((__be32 *)(*p));
+- noff = be32_to_cpup((__be32 *)((*p) + 4));
++ sz = be32_to_cpup(*p);
++ noff = be32_to_cpup(*p + 4);
+ *p += 8;
+ if (be32_to_cpu(blob->version) < 0x10)
+- *p = ALIGN(*p, sz >= 8 ? 8 : 4);
++ *p = PTR_ALIGN(*p, sz >= 8 ? 8 : 4);
+
+ pname = of_fdt_get_string(blob, noff);
+ if (pname == NULL) {
+@@ -281,11 +281,11 @@
+ np->phandle = be32_to_cpup((__be32 *)*p);
+ pp->name = pname;
+ pp->length = sz;
+- pp->value = (void *)*p;
++ pp->value = *p;
+ *prev_pp = pp;
+ prev_pp = &pp->next;
+ }
+- *p = ALIGN((*p) + sz, 4);
++ *p = PTR_ALIGN((*p) + sz, 4);
+ }
+ /* with version 0x10 we may not have the name property, recreate
+ * it here from the unit name if absent
+@@ -334,7 +334,7 @@
+ else
+ mem = unflatten_dt_node(blob, mem, p, np, allnextpp,
+ fpsize);
+- tag = be32_to_cpup((__be32 *)(*p));
++ tag = be32_to_cpup(*p);
+ }
+ if (tag != OF_DT_END_NODE) {
+ pr_err("Weird tag at end of node: %x\n", tag);
+@@ -360,7 +360,8 @@
+ struct device_node **mynodes,
+ void * (*dt_alloc)(u64 size, u64 align))
+ {
+- unsigned long start, mem, size;
++ unsigned long size;
++ void *start, *mem;
+ struct device_node **allnextp = mynodes;
+
+ pr_debug(" -> unflatten_device_tree()\n");
+@@ -381,32 +382,28 @@
+ }
+
+ /* First pass, scan for size */
+- start = ((unsigned long)blob) +
+- be32_to_cpu(blob->off_dt_struct);
+- size = unflatten_dt_node(blob, 0, &start, NULL, NULL, 0);
+- size = (size | 3) + 1;
++ start = ((void *)blob) + be32_to_cpu(blob->off_dt_struct);
++ size = (unsigned long)unflatten_dt_node(blob, 0, &start, NULL, NULL, 0);
++ size = ALIGN(size, 4);
+
+ pr_debug(" size is %lx, allocating...\n", size);
+
+ /* Allocate memory for the expanded device tree */
+- mem = (unsigned long)
+- dt_alloc(size + 4, __alignof__(struct device_node));
++ mem = dt_alloc(size + 4, __alignof__(struct device_node));
++ memset(mem, 0, size);
+
+- memset((void *)mem, 0, size);
++ *(__be32 *)(mem + size) = cpu_to_be32(0xdeadbeef);
+
+- ((__be32 *)mem)[size / 4] = cpu_to_be32(0xdeadbeef);
+-
+- pr_debug(" unflattening %lx...\n", mem);
++ pr_debug(" unflattening %p...\n", mem);
+
+ /* Second pass, do actual unflattening */
+- start = ((unsigned long)blob) +
+- be32_to_cpu(blob->off_dt_struct);
++ start = ((void *)blob) + be32_to_cpu(blob->off_dt_struct);
+ unflatten_dt_node(blob, mem, &start, NULL, &allnextp, 0);
+- if (be32_to_cpup((__be32 *)start) != OF_DT_END)
+- pr_warning("Weird tag at end of tree: %08x\n", *((u32 *)start));
+- if (be32_to_cpu(((__be32 *)mem)[size / 4]) != 0xdeadbeef)
++ if (be32_to_cpup(start) != OF_DT_END)
++ pr_warning("Weird tag at end of tree: %08x\n", be32_to_cpup(start));
++ if (be32_to_cpup(mem + size) != 0xdeadbeef)
+ pr_warning("End of tree marker overwritten: %08x\n",
+- be32_to_cpu(((__be32 *)mem)[size / 4]));
++ be32_to_cpup(mem + size));
+ *allnextp = NULL;
+
+ pr_debug(" <- unflatten_device_tree()\n");
+diff -Nur linux-3.10.30.orig/drivers/of/of_pci.c linux-linaro-stable-mx6/drivers/of/of_pci.c
+--- linux-3.10.30.orig/drivers/of/of_pci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/of/of_pci.c 2014-05-15 20:34:01.642040123 +0200
+@@ -5,14 +5,15 @@
+ #include <asm/prom.h>
+
+ static inline int __of_pci_pci_compare(struct device_node *node,
+- unsigned int devfn)
++ unsigned int data)
+ {
+- unsigned int size;
+- const __be32 *reg = of_get_property(node, "reg", &size);
++ int devfn;
+
+- if (!reg || size < 5 * sizeof(__be32))
++ devfn = of_pci_get_devfn(node);
++ if (devfn < 0)
+ return 0;
+- return ((be32_to_cpup(&reg[0]) >> 8) & 0xff) == devfn;
++
++ return devfn == data;
+ }
+
+ struct device_node *of_pci_find_child_device(struct device_node *parent,
+@@ -40,3 +41,96 @@
+ return NULL;
+ }
+ EXPORT_SYMBOL_GPL(of_pci_find_child_device);
++
++/**
++ * of_pci_get_devfn() - Get device and function numbers for a device node
++ * @np: device node
++ *
++ * Parses a standard 5-cell PCI resource and returns an 8-bit value that can
++ * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
++ * and function numbers respectively. On error a negative error code is
++ * returned.
++ */
++int of_pci_get_devfn(struct device_node *np)
++{
++ unsigned int size;
++ const __be32 *reg;
++
++ reg = of_get_property(np, "reg", &size);
++
++ if (!reg || size < 5 * sizeof(__be32))
++ return -EINVAL;
++
++ return (be32_to_cpup(reg) >> 8) & 0xff;
++}
++EXPORT_SYMBOL_GPL(of_pci_get_devfn);
++
++/**
++ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
++ * @node: device node
++ * @res: address to a struct resource to return the bus-range
++ *
++ * Returns 0 on success or a negative error-code on failure.
++ */
++int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
++{
++ const __be32 *values;
++ int len;
++
++ values = of_get_property(node, "bus-range", &len);
++ if (!values || len < sizeof(*values) * 2)
++ return -EINVAL;
++
++ res->name = node->name;
++ res->start = be32_to_cpup(values++);
++ res->end = be32_to_cpup(values);
++ res->flags = IORESOURCE_BUS;
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
++
++#ifdef CONFIG_PCI_MSI
++
++static LIST_HEAD(of_pci_msi_chip_list);
++static DEFINE_MUTEX(of_pci_msi_chip_mutex);
++
++int of_pci_msi_chip_add(struct msi_chip *chip)
++{
++ if (!of_property_read_bool(chip->of_node, "msi-controller"))
++ return -EINVAL;
++
++ mutex_lock(&of_pci_msi_chip_mutex);
++ list_add(&chip->list, &of_pci_msi_chip_list);
++ mutex_unlock(&of_pci_msi_chip_mutex);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(of_pci_msi_chip_add);
++
++void of_pci_msi_chip_remove(struct msi_chip *chip)
++{
++ mutex_lock(&of_pci_msi_chip_mutex);
++ list_del(&chip->list);
++ mutex_unlock(&of_pci_msi_chip_mutex);
++}
++EXPORT_SYMBOL_GPL(of_pci_msi_chip_remove);
++
++struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node *of_node)
++{
++ struct msi_chip *c;
++
++ mutex_lock(&of_pci_msi_chip_mutex);
++ list_for_each_entry(c, &of_pci_msi_chip_list, list) {
++ if (c->of_node == of_node) {
++ mutex_unlock(&of_pci_msi_chip_mutex);
++ return c;
++ }
++ }
++ mutex_unlock(&of_pci_msi_chip_mutex);
++
++ return NULL;
++}
++EXPORT_SYMBOL_GPL(of_pci_find_msi_chip_by_node);
++
++#endif /* CONFIG_PCI_MSI */
+diff -Nur linux-3.10.30.orig/drivers/pci/host/Kconfig linux-linaro-stable-mx6/drivers/pci/host/Kconfig
+--- linux-3.10.30.orig/drivers/pci/host/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/host/Kconfig 2014-05-15 20:34:01.698040526 +0200
+@@ -0,0 +1,39 @@
++menu "PCI host controller drivers"
++ depends on PCI
++
++config PCI_MVEBU
++ bool "Marvell EBU PCIe controller"
++ depends on ARCH_MVEBU || ARCH_KIRKWOOD
++
++config PCIE_DW
++ bool
++
++config PCI_EXYNOS
++ bool "Samsung Exynos PCIe controller"
++ depends on SOC_EXYNOS5440
++ select PCIEPORTBUS
++ select PCIE_DW
++
++config PCI_IMX6
++ bool "Freescale i.MX6 PCIe controller"
++ depends on SOC_IMX6Q
++ select PCIEPORTBUS
++ select PCIE_DW
++
++config EP_MODE_IN_EP_RC_SYS
++ bool "PCI Express EP mode in the IMX6 RC/EP interconnection system"
++ depends on PCI_IMX6
++
++config EP_SELF_IO_TEST
++ bool "PCI Express EP_SELF_IO_TEST in EP mode"
++ depends on EP_MODE_IN_EP_RC_SYS
++
++config RC_MODE_IN_EP_RC_SYS
++ bool "PCI Express RC mode in the IMX6 RC/EP interconnection system"
++ depends on PCI_IMX6
++
++config PCI_TEGRA
++ bool "NVIDIA Tegra PCIe controller"
++ depends on ARCH_TEGRA
++
++endmenu
+diff -Nur linux-3.10.30.orig/drivers/pci/host/Makefile linux-linaro-stable-mx6/drivers/pci/host/Makefile
+--- linux-3.10.30.orig/drivers/pci/host/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/host/Makefile 2014-05-15 20:34:01.698040526 +0200
+@@ -0,0 +1,4 @@
++obj-$(CONFIG_PCIE_DW) += pcie-designware.o
++obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
++obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
++obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
+diff -Nur linux-3.10.30.orig/drivers/pci/host/pcie-designware.c linux-linaro-stable-mx6/drivers/pci/host/pcie-designware.c
+--- linux-3.10.30.orig/drivers/pci/host/pcie-designware.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/host/pcie-designware.c 2014-05-15 20:34:01.698040526 +0200
+@@ -0,0 +1,773 @@
++/*
++ * Synopsys Designware PCIe host controller driver
++ *
++ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
++ * http://www.samsung.com
++ *
++ * Author: Jingoo Han <jg1.han@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/irq.h>
++#include <linux/irqdomain.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/msi.h>
++#include <linux/of_address.h>
++#include <linux/pci.h>
++#include <linux/pci_regs.h>
++#include <linux/types.h>
++
++#include "pcie-designware.h"
++
++static struct hw_pci dw_pci;
++
++static unsigned long global_io_offset;
++
++static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
++{
++ return sys->private_data;
++}
++
++int cfg_read(void __iomem *addr, int where, int size, u32 *val)
++{
++ *val = readl(addr);
++
++ if (size == 1)
++ *val = (*val >> (8 * (where & 3))) & 0xff;
++ else if (size == 2)
++ *val = (*val >> (8 * (where & 3))) & 0xffff;
++ else if (size != 4)
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++int cfg_write(void __iomem *addr, int where, int size, u32 val)
++{
++ if (size == 4)
++ writel(val, addr);
++ else if (size == 2)
++ writew(val, addr + (where & 2));
++ else if (size == 1)
++ writeb(val, addr + (where & 3));
++ else
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static inline void dw_pcie_readl_rc(struct pcie_port *pp,
++ void __iomem *dbi_addr, u32 *val)
++{
++ if (pp->ops->readl_rc)
++ pp->ops->readl_rc(pp, dbi_addr, val);
++ else
++ *val = readl(dbi_addr);
++}
++
++static inline void dw_pcie_writel_rc(struct pcie_port *pp,
++ u32 val, void __iomem *dbi_addr)
++{
++ if (pp->ops->writel_rc)
++ pp->ops->writel_rc(pp, val, dbi_addr);
++ else
++ writel(val, dbi_addr);
++}
++
++static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
++ u32 *val)
++{
++ int ret;
++
++ if (pp->ops->rd_own_conf)
++ ret = pp->ops->rd_own_conf(pp, where, size, val);
++ else
++ ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
++
++ return ret;
++}
++
++static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
++ u32 val)
++{
++ int ret;
++
++ if (pp->ops->wr_own_conf)
++ ret = pp->ops->wr_own_conf(pp, where, size, val);
++ else
++ ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
++ val);
++
++ return ret;
++}
++
++static struct irq_chip dw_msi_irq_chip = {
++ .name = "PCI-MSI",
++ .irq_enable = unmask_msi_irq,
++ .irq_disable = mask_msi_irq,
++ .irq_mask = mask_msi_irq,
++ .irq_unmask = unmask_msi_irq,
++};
++
++/* MSI int handler */
++void dw_handle_msi_irq(struct pcie_port *pp)
++{
++ unsigned long val;
++ int i, pos, irq;
++
++ for (i = 0; i < MAX_MSI_CTRLS; i++) {
++ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
++ (u32 *)&val);
++ if (val) {
++ pos = 0;
++ while ((pos = find_next_bit(&val, 32, pos)) != 32) {
++ irq = irq_find_mapping(pp->irq_domain,
++ i * 32 + pos);
++ generic_handle_irq(irq);
++ pos++;
++ }
++ }
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
++ }
++}
++
++void dw_pcie_msi_init(struct pcie_port *pp)
++{
++ pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
++
++ /* program the msi_data */
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
++ virt_to_phys((void *)pp->msi_data));
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
++}
++
++static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
++{
++ int flag = 1;
++
++ do {
++ pos = find_next_zero_bit(pp->msi_irq_in_use,
++ MAX_MSI_IRQS, pos);
++ /*if you have reached to the end then get out from here.*/
++ if (pos == MAX_MSI_IRQS)
++ return -ENOSPC;
++ /*
++ * Check if this position is at correct offset.nvec is always a
++ * power of two. pos0 must be nvec bit alligned.
++ */
++ if (pos % msgvec)
++ pos += msgvec - (pos % msgvec);
++ else
++ flag = 0;
++ } while (flag);
++
++ *pos0 = pos;
++ return 0;
++}
++
++static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
++{
++ int res, bit, irq, pos0, pos1, i;
++ u32 val;
++ struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
++
++ if (!pp) {
++ BUG();
++ return -EINVAL;
++ }
++
++ pos0 = find_first_zero_bit(pp->msi_irq_in_use,
++ MAX_MSI_IRQS);
++ if (pos0 % no_irqs) {
++ if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
++ goto no_valid_irq;
++ }
++ if (no_irqs > 1) {
++ pos1 = find_next_bit(pp->msi_irq_in_use,
++ MAX_MSI_IRQS, pos0);
++ /* there must be nvec number of consecutive free bits */
++ while ((pos1 - pos0) < no_irqs) {
++ if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
++ goto no_valid_irq;
++ pos1 = find_next_bit(pp->msi_irq_in_use,
++ MAX_MSI_IRQS, pos0);
++ }
++ }
++
++ irq = irq_find_mapping(pp->irq_domain, pos0);
++ if (!irq)
++ goto no_valid_irq;
++
++ i = 0;
++ while (i < no_irqs) {
++ set_bit(pos0 + i, pp->msi_irq_in_use);
++ irq_alloc_descs((irq + i), (irq + i), 1, 0);
++ irq_set_msi_desc(irq + i, desc);
++ /*Enable corresponding interrupt in MSI interrupt controller */
++ res = ((pos0 + i) / 32) * 12;
++ bit = (pos0 + i) % 32;
++ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
++ val |= 1 << bit;
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
++ i++;
++ }
++
++ *pos = pos0;
++ return irq;
++
++no_valid_irq:
++ *pos = pos0;
++ return -ENOSPC;
++}
++
++static void clear_irq(unsigned int irq)
++{
++ int res, bit, val, pos;
++ struct irq_desc *desc;
++ struct msi_desc *msi;
++ struct pcie_port *pp;
++ struct irq_data *data = irq_get_irq_data(irq);
++
++ /* get the port structure */
++ desc = irq_to_desc(irq);
++ msi = irq_desc_get_msi_desc(desc);
++ pp = sys_to_pcie(msi->dev->bus->sysdata);
++ if (!pp) {
++ BUG();
++ return;
++ }
++
++ pos = data->hwirq;
++
++ irq_free_desc(irq);
++
++ clear_bit(pos, pp->msi_irq_in_use);
++
++ /* Disable corresponding interrupt on MSI interrupt controller */
++ res = (pos / 32) * 12;
++ bit = pos % 32;
++ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
++ val &= ~(1 << bit);
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
++}
++
++static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
++ struct msi_desc *desc)
++{
++ int irq, pos, msgvec;
++ u16 msg_ctr;
++ struct msi_msg msg;
++ struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
++
++ if (!pp) {
++ BUG();
++ return -EINVAL;
++ }
++
++ if (pp->quirks & DW_PCIE_QUIRK_NO_MSI_VEC) {
++ irq = assign_irq(1, desc, &pos);
++ set_irq_flags(irq, IRQF_VALID);
++ } else {
++ pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
++ &msg_ctr);
++ msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
++ if (msgvec == 0)
++ msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
++ if (msgvec > 5)
++ msgvec = 0;
++
++ irq = assign_irq((1 << msgvec), desc, &pos);
++ if (irq < 0)
++ return irq;
++
++ msg_ctr &= ~PCI_MSI_FLAGS_QSIZE;
++ msg_ctr |= msgvec << 4;
++ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
++ msg_ctr);
++ desc->msi_attrib.multiple = msgvec;
++ }
++
++ msg.address_lo = virt_to_phys((void *)pp->msi_data);
++ msg.address_hi = 0x0;
++ msg.data = pos;
++ write_msi_msg(irq, &msg);
++
++ return 0;
++}
++
++static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
++{
++ clear_irq(irq);
++}
++
++static int dw_msi_check_device(struct msi_chip *chip, struct pci_dev *pdev,
++ int nvec, int type)
++{
++ struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
++ u32 val;
++
++ if (pp->quirks & DW_PCIE_QUIRK_MSI_SELF_EN) {
++ if ((type == PCI_CAP_ID_MSI) || (type == PCI_CAP_ID_MSIX)) {
++ /* Set MSI enable of RC here */
++ val = readl(pp->dbi_base + 0x50);
++ if ((val & (PCI_MSI_FLAGS_ENABLE << 16)) == 0) {
++ val |= PCI_MSI_FLAGS_ENABLE << 16;
++ writel(val, pp->dbi_base + 0x50);
++ }
++ }
++ }
++
++ return 0;
++}
++
++static struct msi_chip dw_pcie_msi_chip = {
++ .setup_irq = dw_msi_setup_irq,
++ .teardown_irq = dw_msi_teardown_irq,
++ .check_device = dw_msi_check_device,
++};
++
++int dw_pcie_link_up(struct pcie_port *pp)
++{
++ if (pp->ops->link_up)
++ return pp->ops->link_up(pp);
++ else
++ return 0;
++}
++
++static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
++ irq_hw_number_t hwirq)
++{
++ irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
++ irq_set_chip_data(irq, domain->host_data);
++ set_irq_flags(irq, IRQF_VALID);
++
++ return 0;
++}
++
++static const struct irq_domain_ops msi_domain_ops = {
++ .map = dw_pcie_msi_map,
++};
++
++int __init dw_pcie_host_init(struct pcie_port *pp)
++{
++ struct device_node *np = pp->dev->of_node;
++ struct of_pci_range range;
++ struct of_pci_range_parser parser;
++ u32 val;
++ int i;
++
++ if (of_pci_range_parser_init(&parser, np)) {
++ dev_err(pp->dev, "missing ranges property\n");
++ return -EINVAL;
++ }
++
++ /* Get the I/O and memory ranges from DT */
++ for_each_of_pci_range(&parser, &range) {
++ unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
++ if (restype == IORESOURCE_IO) {
++ of_pci_range_to_resource(&range, np, &pp->io);
++ pp->io.name = "I/O";
++ pp->io.start = max_t(resource_size_t,
++ PCIBIOS_MIN_IO,
++ range.pci_addr + global_io_offset);
++ pp->io.end = min_t(resource_size_t,
++ IO_SPACE_LIMIT,
++ range.pci_addr + range.size
++ + global_io_offset);
++ pp->config.io_size = resource_size(&pp->io);
++ pp->config.io_bus_addr = range.pci_addr;
++ }
++ if (restype == IORESOURCE_MEM) {
++ of_pci_range_to_resource(&range, np, &pp->mem);
++ pp->mem.name = "MEM";
++ pp->config.mem_size = resource_size(&pp->mem);
++ pp->config.mem_bus_addr = range.pci_addr;
++ }
++ if (restype == 0) {
++ of_pci_range_to_resource(&range, np, &pp->cfg);
++ pp->config.cfg0_size = resource_size(&pp->cfg)/2;
++ pp->config.cfg1_size = resource_size(&pp->cfg)/2;
++ }
++ }
++
++ if (!pp->dbi_base) {
++ pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
++ resource_size(&pp->cfg));
++ if (!pp->dbi_base) {
++ dev_err(pp->dev, "error with ioremap\n");
++ return -ENOMEM;
++ }
++ }
++
++ pp->cfg0_base = pp->cfg.start;
++ pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
++ pp->io_base = pp->io.start;
++ pp->mem_base = pp->mem.start;
++
++ pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
++ pp->config.cfg0_size);
++ if (!pp->va_cfg0_base) {
++ dev_err(pp->dev, "error with ioremap in function\n");
++ return -ENOMEM;
++ }
++ pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
++ pp->config.cfg1_size);
++ if (!pp->va_cfg1_base) {
++ dev_err(pp->dev, "error with ioremap\n");
++ return -ENOMEM;
++ }
++
++ if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
++ dev_err(pp->dev, "Failed to parse the number of lanes\n");
++ return -EINVAL;
++ }
++
++ if (IS_ENABLED(CONFIG_PCI_MSI)) {
++ pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
++ MAX_MSI_IRQS, &msi_domain_ops,
++ &dw_pcie_msi_chip);
++ if (!pp->irq_domain) {
++ dev_err(pp->dev, "irq domain init failed\n");
++ return -ENXIO;
++ }
++
++ for (i = 0; i < MAX_MSI_IRQS; i++)
++ irq_create_mapping(pp->irq_domain, i);
++ }
++
++ if (pp->ops->host_init)
++ pp->ops->host_init(pp);
++
++ dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
++
++ /* program correct class for RC */
++ dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
++
++ dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
++ val |= PORT_LOGIC_SPEED_CHANGE;
++ dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
++
++ dw_pci.nr_controllers = 1;
++ dw_pci.private_data = (void **)&pp;
++
++ pci_common_init(&dw_pci);
++ pci_assign_unassigned_resources();
++#ifdef CONFIG_PCI_DOMAINS
++ dw_pci.domain++;
++#endif
++
++ return 0;
++}
++
++static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
++{
++ u32 val;
++ void __iomem *dbi_base = pp->dbi_base;
++
++ /* Program viewport 0 : OUTBOUND : CFG0 */
++ val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0;
++ dw_pcie_writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT);
++ dw_pcie_writel_rc(pp, pp->cfg0_base, dbi_base + PCIE_ATU_LOWER_BASE);
++ dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32),
++ dbi_base + PCIE_ATU_UPPER_BASE);
++ dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
++ dbi_base + PCIE_ATU_LIMIT);
++ dw_pcie_writel_rc(pp, busdev, dbi_base + PCIE_ATU_LOWER_TARGET);
++ dw_pcie_writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET);
++ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, dbi_base + PCIE_ATU_CR1);
++ val = PCIE_ATU_ENABLE;
++ dw_pcie_writel_rc(pp, val, dbi_base + PCIE_ATU_CR2);
++}
++
++static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
++{
++ u32 val;
++ void __iomem *dbi_base = pp->dbi_base;
++
++ /* Program viewport 1 : OUTBOUND : CFG1 */
++ val = PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1;
++ dw_pcie_writel_rc(pp, val, dbi_base + PCIE_ATU_VIEWPORT);
++ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, dbi_base + PCIE_ATU_CR1);
++ val = PCIE_ATU_ENABLE;
++ dw_pcie_writel_rc(pp, val, dbi_base + PCIE_ATU_CR2);
++ dw_pcie_writel_rc(pp, pp->cfg1_base, dbi_base + PCIE_ATU_LOWER_BASE);
++ dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32),
++ dbi_base + PCIE_ATU_UPPER_BASE);
++ dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
++ dbi_base + PCIE_ATU_LIMIT);
++ dw_pcie_writel_rc(pp, busdev, dbi_base + PCIE_ATU_LOWER_TARGET);
++ dw_pcie_writel_rc(pp, 0, dbi_base + PCIE_ATU_UPPER_TARGET);
++}
++
++static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
++ u32 devfn, int where, int size, u32 *val)
++{
++ int ret = PCIBIOS_SUCCESSFUL;
++ u32 address, busdev;
++
++ busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
++ PCIE_ATU_FUNC(PCI_FUNC(devfn));
++ address = where & ~0x3;
++
++ if (bus->parent->number == pp->root_bus_nr) {
++ dw_pcie_prog_viewport_cfg0(pp, busdev);
++ ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
++ } else {
++ dw_pcie_prog_viewport_cfg1(pp, busdev);
++ ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
++ }
++
++ return ret;
++}
++
++static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
++ u32 devfn, int where, int size, u32 val)
++{
++ int ret = PCIBIOS_SUCCESSFUL;
++ u32 address, busdev;
++
++ busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
++ PCIE_ATU_FUNC(PCI_FUNC(devfn));
++ address = where & ~0x3;
++
++ if (bus->parent->number == pp->root_bus_nr) {
++ dw_pcie_prog_viewport_cfg0(pp, busdev);
++ ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
++ } else {
++ dw_pcie_prog_viewport_cfg1(pp, busdev);
++ ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
++ }
++
++ return ret;
++}
++
++
++static int dw_pcie_valid_config(struct pcie_port *pp,
++ struct pci_bus *bus, int dev)
++{
++ /* If there is no link, then there is no device */
++ if (bus->number != pp->root_bus_nr) {
++ if (!dw_pcie_link_up(pp))
++ return 0;
++ }
++
++ /* access only one slot on each root port */
++ if (bus->number == pp->root_bus_nr && dev > 0)
++ return 0;
++
++ /*
++ * do not read more than one device on the bus directly attached
++ * to RC's (Virtual Bridge's) DS side.
++ */
++ if (bus->primary == pp->root_bus_nr && dev > 0)
++ return 0;
++
++ return 1;
++}
++
++static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
++ int size, u32 *val)
++{
++ struct pcie_port *pp = sys_to_pcie(bus->sysdata);
++ unsigned long flags;
++ int ret;
++
++ if (!pp) {
++ BUG();
++ return -EINVAL;
++ }
++
++ if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
++ *val = 0xffffffff;
++ return PCIBIOS_DEVICE_NOT_FOUND;
++ }
++
++ spin_lock_irqsave(&pp->conf_lock, flags);
++ if (bus->number != pp->root_bus_nr)
++ ret = dw_pcie_rd_other_conf(pp, bus, devfn,
++ where, size, val);
++ else
++ ret = dw_pcie_rd_own_conf(pp, where, size, val);
++ spin_unlock_irqrestore(&pp->conf_lock, flags);
++
++ return ret;
++}
++
++static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
++ int where, int size, u32 val)
++{
++ struct pcie_port *pp = sys_to_pcie(bus->sysdata);
++ unsigned long flags;
++ int ret;
++
++ if (!pp) {
++ BUG();
++ return -EINVAL;
++ }
++
++ if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ spin_lock_irqsave(&pp->conf_lock, flags);
++ if (bus->number != pp->root_bus_nr)
++ ret = dw_pcie_wr_other_conf(pp, bus, devfn,
++ where, size, val);
++ else
++ ret = dw_pcie_wr_own_conf(pp, where, size, val);
++ spin_unlock_irqrestore(&pp->conf_lock, flags);
++
++ return ret;
++}
++
++static struct pci_ops dw_pcie_ops = {
++ .read = dw_pcie_rd_conf,
++ .write = dw_pcie_wr_conf,
++};
++
++static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
++{
++ struct pcie_port *pp;
++
++ pp = sys_to_pcie(sys);
++
++ if (!pp)
++ return 0;
++
++ if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
++ sys->io_offset = global_io_offset - pp->config.io_bus_addr;
++ pci_ioremap_io(sys->io_offset, pp->io.start);
++ global_io_offset += SZ_64K;
++ pci_add_resource_offset(&sys->resources, &pp->io,
++ sys->io_offset);
++ }
++
++ sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
++ pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
++
++ return 1;
++}
++
++static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
++{
++ struct pci_bus *bus;
++ struct pcie_port *pp = sys_to_pcie(sys);
++
++ if (pp) {
++ pp->root_bus_nr = sys->busnr;
++ bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
++ sys, &sys->resources);
++ } else {
++ bus = NULL;
++ BUG();
++ }
++
++ return bus;
++}
++
++static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
++
++ switch (pin) {
++ case 1: return pp->irq;
++ case 2: return pp->irq - 1;
++ case 3: return pp->irq - 2;
++ case 4: return pp->irq - 3;
++ default: return -1;
++ }
++}
++
++static void dw_pcie_add_bus(struct pci_bus *bus)
++{
++ if (IS_ENABLED(CONFIG_PCI_MSI)) {
++ struct pcie_port *pp = sys_to_pcie(bus->sysdata);
++
++ dw_pcie_msi_chip.dev = pp->dev;
++ bus->msi = &dw_pcie_msi_chip;
++ }
++}
++
++static struct hw_pci dw_pci = {
++ .setup = dw_pcie_setup,
++ .scan = dw_pcie_scan_bus,
++ .map_irq = dw_pcie_map_irq,
++ .add_bus = dw_pcie_add_bus,
++};
++
++void dw_pcie_setup_rc(struct pcie_port *pp)
++{
++ struct pcie_port_info *config = &pp->config;
++ void __iomem *dbi_base = pp->dbi_base;
++ u32 val;
++ u32 membase;
++ u32 memlimit;
++
++ /* set the number of lines as 4 */
++ dw_pcie_readl_rc(pp, dbi_base + PCIE_PORT_LINK_CONTROL, &val);
++ val &= ~PORT_LINK_MODE_MASK;
++ switch (pp->lanes) {
++ case 1:
++ val |= PORT_LINK_MODE_1_LANES;
++ break;
++ case 2:
++ val |= PORT_LINK_MODE_2_LANES;
++ break;
++ case 4:
++ val |= PORT_LINK_MODE_4_LANES;
++ break;
++ }
++ dw_pcie_writel_rc(pp, val, dbi_base + PCIE_PORT_LINK_CONTROL);
++
++ /* set link width speed control register */
++ dw_pcie_readl_rc(pp, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
++ val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
++ switch (pp->lanes) {
++ case 1:
++ val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
++ break;
++ case 2:
++ val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
++ break;
++ case 4:
++ val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
++ break;
++ }
++ dw_pcie_writel_rc(pp, val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
++
++ /* setup RC BARs */
++ dw_pcie_writel_rc(pp, 0x00000004, dbi_base + PCI_BASE_ADDRESS_0);
++ dw_pcie_writel_rc(pp, 0x00000004, dbi_base + PCI_BASE_ADDRESS_1);
++
++ /* setup interrupt pins */
++ dw_pcie_readl_rc(pp, dbi_base + PCI_INTERRUPT_LINE, &val);
++ val &= 0xffff00ff;
++ val |= 0x00000100;
++ dw_pcie_writel_rc(pp, val, dbi_base + PCI_INTERRUPT_LINE);
++
++ /* setup bus numbers */
++ dw_pcie_readl_rc(pp, dbi_base + PCI_PRIMARY_BUS, &val);
++ val &= 0xff000000;
++ val |= 0x00010100;
++ dw_pcie_writel_rc(pp, val, dbi_base + PCI_PRIMARY_BUS);
++
++ /* setup memory base, memory limit */
++ membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
++ memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
++ val = memlimit | membase;
++ dw_pcie_writel_rc(pp, val, dbi_base + PCI_MEMORY_BASE);
++
++ /* setup command register */
++ dw_pcie_readl_rc(pp, dbi_base + PCI_COMMAND, &val);
++ val &= 0xffff0000;
++ val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
++ PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
++ dw_pcie_writel_rc(pp, val, dbi_base + PCI_COMMAND);
++}
++
++MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
++MODULE_DESCRIPTION("Designware PCIe host controller driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/pci/host/pcie-designware.h linux-linaro-stable-mx6/drivers/pci/host/pcie-designware.h
+--- linux-3.10.30.orig/drivers/pci/host/pcie-designware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/host/pcie-designware.h 2014-05-15 20:34:01.698040526 +0200
+@@ -0,0 +1,124 @@
++/*
++ * Synopsys Designware PCIe host controller driver
++ *
++ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
++ * http://www.samsung.com
++ *
++ * Author: Jingoo Han <jg1.han@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef _PCIE_DESIGNWARE_H
++#define _PCIE_DESIGNWARE_H
++
++/* Synopsis specific PCIE configuration registers */
++#define PCIE_PORT_LINK_CONTROL 0x710
++#define PORT_LINK_MODE_MASK (0x3f << 16)
++#define PORT_LINK_MODE_1_LANES (0x1 << 16)
++#define PORT_LINK_MODE_2_LANES (0x3 << 16)
++#define PORT_LINK_MODE_4_LANES (0x7 << 16)
++
++#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
++#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
++#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
++#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
++#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
++#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
++
++#define PCIE_MSI_ADDR_LO 0x820
++#define PCIE_MSI_ADDR_HI 0x824
++#define PCIE_MSI_INTR0_ENABLE 0x828
++#define PCIE_MSI_INTR0_MASK 0x82C
++#define PCIE_MSI_INTR0_STATUS 0x830
++
++#define PCIE_ATU_VIEWPORT 0x900
++#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
++#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
++#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
++#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
++#define PCIE_ATU_CR1 0x904
++#define PCIE_ATU_TYPE_MEM (0x0 << 0)
++#define PCIE_ATU_TYPE_IO (0x2 << 0)
++#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
++#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
++#define PCIE_ATU_CR2 0x908
++#define PCIE_ATU_ENABLE (0x1 << 31)
++#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
++#define PCIE_ATU_LOWER_BASE 0x90C
++#define PCIE_ATU_UPPER_BASE 0x910
++#define PCIE_ATU_LIMIT 0x914
++#define PCIE_ATU_LOWER_TARGET 0x918
++#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
++#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
++#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
++#define PCIE_ATU_UPPER_TARGET 0x91C
++
++struct pcie_port_info {
++ u32 cfg0_size;
++ u32 cfg1_size;
++ u32 io_size;
++ u32 mem_size;
++ phys_addr_t io_bus_addr;
++ phys_addr_t mem_bus_addr;
++};
++
++/*
++ * Maximum number of MSI IRQs can be 256 per controller. But keep
++ * it 32 as of now. Probably we will never need more than 32. If needed,
++ * then increment it in multiple of 32.
++ */
++#define MAX_MSI_IRQS 32
++#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
++
++struct pcie_port {
++ struct device *dev;
++ u8 root_bus_nr;
++ void __iomem *dbi_base;
++ u64 cfg0_base;
++ void __iomem *va_cfg0_base;
++ u64 cfg1_base;
++ void __iomem *va_cfg1_base;
++ u64 io_base;
++ u64 mem_base;
++ spinlock_t conf_lock;
++ struct resource cfg;
++ struct resource io;
++ struct resource mem;
++ struct pcie_port_info config;
++ int irq;
++ u32 lanes;
++ struct pcie_host_ops *ops;
++ u32 quirks; /* Deviations from spec. */
++/* Controller doesn't support MSI VEC */
++#define DW_PCIE_QUIRK_NO_MSI_VEC (1<<0)
++/* MSI EN of Controller should be configured when MSI is enabled */
++#define DW_PCIE_QUIRK_MSI_SELF_EN (1<<1)
++ int msi_irq;
++ struct irq_domain *irq_domain;
++ unsigned long msi_data;
++ DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
++};
++
++struct pcie_host_ops {
++ void (*readl_rc)(struct pcie_port *pp,
++ void __iomem *dbi_base, u32 *val);
++ void (*writel_rc)(struct pcie_port *pp,
++ u32 val, void __iomem *dbi_base);
++ int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
++ int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
++ int (*link_up)(struct pcie_port *pp);
++ void (*host_init)(struct pcie_port *pp);
++};
++
++int cfg_read(void __iomem *addr, int where, int size, u32 *val);
++int cfg_write(void __iomem *addr, int where, int size, u32 val);
++void dw_handle_msi_irq(struct pcie_port *pp);
++void dw_pcie_msi_init(struct pcie_port *pp);
++int dw_pcie_link_up(struct pcie_port *pp);
++void dw_pcie_setup_rc(struct pcie_port *pp);
++int dw_pcie_host_init(struct pcie_port *pp);
++
++#endif /* _PCIE_DESIGNWARE_H */
+diff -Nur linux-3.10.30.orig/drivers/pci/host/pci-exynos.c linux-linaro-stable-mx6/drivers/pci/host/pci-exynos.c
+--- linux-3.10.30.orig/drivers/pci/host/pci-exynos.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/host/pci-exynos.c 2014-05-15 20:34:01.698040526 +0200
+@@ -0,0 +1,648 @@
++/*
++ * PCIe host controller driver for Samsung EXYNOS SoCs
++ *
++ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
++ * http://www.samsung.com
++ *
++ * Author: Jingoo Han <jg1.han@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pci.h>
++#include <linux/platform_device.h>
++#include <linux/resource.h>
++#include <linux/signal.h>
++#include <linux/types.h>
++
++#include "pcie-designware.h"
++
++#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
++
++struct exynos_pcie {
++ void __iomem *elbi_base;
++ void __iomem *phy_base;
++ void __iomem *block_base;
++ int reset_gpio;
++ struct clk *clk;
++ struct clk *bus_clk;
++ struct pcie_port pp;
++};
++
++/* PCIe ELBI registers */
++#define PCIE_IRQ_PULSE 0x000
++#define IRQ_INTA_ASSERT (0x1 << 0)
++#define IRQ_INTB_ASSERT (0x1 << 2)
++#define IRQ_INTC_ASSERT (0x1 << 4)
++#define IRQ_INTD_ASSERT (0x1 << 6)
++#define PCIE_IRQ_LEVEL 0x004
++#define PCIE_IRQ_SPECIAL 0x008
++#define PCIE_IRQ_EN_PULSE 0x00c
++#define PCIE_IRQ_EN_LEVEL 0x010
++#define IRQ_MSI_ENABLE (0x1 << 2)
++#define PCIE_IRQ_EN_SPECIAL 0x014
++#define PCIE_PWR_RESET 0x018
++#define PCIE_CORE_RESET 0x01c
++#define PCIE_CORE_RESET_ENABLE (0x1 << 0)
++#define PCIE_STICKY_RESET 0x020
++#define PCIE_NONSTICKY_RESET 0x024
++#define PCIE_APP_INIT_RESET 0x028
++#define PCIE_APP_LTSSM_ENABLE 0x02c
++#define PCIE_ELBI_RDLH_LINKUP 0x064
++#define PCIE_ELBI_LTSSM_ENABLE 0x1
++#define PCIE_ELBI_SLV_AWMISC 0x11c
++#define PCIE_ELBI_SLV_ARMISC 0x120
++#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21)
++
++/* PCIe Purple registers */
++#define PCIE_PHY_GLOBAL_RESET 0x000
++#define PCIE_PHY_COMMON_RESET 0x004
++#define PCIE_PHY_CMN_REG 0x008
++#define PCIE_PHY_MAC_RESET 0x00c
++#define PCIE_PHY_PLL_LOCKED 0x010
++#define PCIE_PHY_TRSVREG_RESET 0x020
++#define PCIE_PHY_TRSV_RESET 0x024
++
++/* PCIe PHY registers */
++#define PCIE_PHY_IMPEDANCE 0x004
++#define PCIE_PHY_PLL_DIV_0 0x008
++#define PCIE_PHY_PLL_BIAS 0x00c
++#define PCIE_PHY_DCC_FEEDBACK 0x014
++#define PCIE_PHY_PLL_DIV_1 0x05c
++#define PCIE_PHY_COMMON_POWER 0x064
++#define PCIE_PHY_COMMON_PD_CMN (0x1 << 3)
++#define PCIE_PHY_TRSV0_EMP_LVL 0x084
++#define PCIE_PHY_TRSV0_DRV_LVL 0x088
++#define PCIE_PHY_TRSV0_RXCDR 0x0ac
++#define PCIE_PHY_TRSV0_POWER 0x0c4
++#define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7)
++#define PCIE_PHY_TRSV0_LVCC 0x0dc
++#define PCIE_PHY_TRSV1_EMP_LVL 0x144
++#define PCIE_PHY_TRSV1_RXCDR 0x16c
++#define PCIE_PHY_TRSV1_POWER 0x184
++#define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7)
++#define PCIE_PHY_TRSV1_LVCC 0x19c
++#define PCIE_PHY_TRSV2_EMP_LVL 0x204
++#define PCIE_PHY_TRSV2_RXCDR 0x22c
++#define PCIE_PHY_TRSV2_POWER 0x244
++#define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7)
++#define PCIE_PHY_TRSV2_LVCC 0x25c
++#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
++#define PCIE_PHY_TRSV3_RXCDR 0x2ec
++#define PCIE_PHY_TRSV3_POWER 0x304
++#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
++#define PCIE_PHY_TRSV3_LVCC 0x31c
++
++static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++
++ if (on) {
++ val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
++ val |= PCIE_ELBI_SLV_DBI_ENABLE;
++ writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
++ } else {
++ val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
++ val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
++ writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC);
++ }
++}
++
++static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++
++ if (on) {
++ val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
++ val |= PCIE_ELBI_SLV_DBI_ENABLE;
++ writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
++ } else {
++ val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
++ val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
++ writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC);
++ }
++}
++
++static void exynos_pcie_assert_core_reset(struct pcie_port *pp)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ void __iomem *elbi_base = exynos_pcie->elbi_base;
++
++ val = readl(elbi_base + PCIE_CORE_RESET);
++ val &= ~PCIE_CORE_RESET_ENABLE;
++ writel(val, elbi_base + PCIE_CORE_RESET);
++ writel(0, elbi_base + PCIE_PWR_RESET);
++ writel(0, elbi_base + PCIE_STICKY_RESET);
++ writel(0, elbi_base + PCIE_NONSTICKY_RESET);
++}
++
++static void exynos_pcie_deassert_core_reset(struct pcie_port *pp)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ void __iomem *elbi_base = exynos_pcie->elbi_base;
++ void __iomem *block_base = exynos_pcie->block_base;
++
++ val = readl(elbi_base + PCIE_CORE_RESET);
++ val |= PCIE_CORE_RESET_ENABLE;
++ writel(val, elbi_base + PCIE_CORE_RESET);
++ writel(1, elbi_base + PCIE_STICKY_RESET);
++ writel(1, elbi_base + PCIE_NONSTICKY_RESET);
++ writel(1, elbi_base + PCIE_APP_INIT_RESET);
++ writel(0, elbi_base + PCIE_APP_INIT_RESET);
++ writel(1, block_base + PCIE_PHY_MAC_RESET);
++}
++
++static void exynos_pcie_assert_phy_reset(struct pcie_port *pp)
++{
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ void __iomem *block_base = exynos_pcie->block_base;
++
++ writel(0, block_base + PCIE_PHY_MAC_RESET);
++ writel(1, block_base + PCIE_PHY_GLOBAL_RESET);
++}
++
++static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp)
++{
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ void __iomem *elbi_base = exynos_pcie->elbi_base;
++ void __iomem *block_base = exynos_pcie->block_base;
++
++ writel(0, block_base + PCIE_PHY_GLOBAL_RESET);
++ writel(1, elbi_base + PCIE_PWR_RESET);
++ writel(0, block_base + PCIE_PHY_COMMON_RESET);
++ writel(0, block_base + PCIE_PHY_CMN_REG);
++ writel(0, block_base + PCIE_PHY_TRSVREG_RESET);
++ writel(0, block_base + PCIE_PHY_TRSV_RESET);
++}
++
++static void exynos_pcie_power_on_phy(struct pcie_port *pp)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
++ val &= ~PCIE_PHY_COMMON_PD_CMN;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
++ val &= ~PCIE_PHY_TRSV0_PD_TSV;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
++ val &= ~PCIE_PHY_TRSV1_PD_TSV;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
++ val &= ~PCIE_PHY_TRSV2_PD_TSV;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
++ val &= ~PCIE_PHY_TRSV3_PD_TSV;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
++}
++
++static void exynos_pcie_power_off_phy(struct pcie_port *pp)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER);
++ val |= PCIE_PHY_COMMON_PD_CMN;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER);
++ val |= PCIE_PHY_TRSV0_PD_TSV;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER);
++ val |= PCIE_PHY_TRSV1_PD_TSV;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER);
++ val |= PCIE_PHY_TRSV2_PD_TSV;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER);
++
++ val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER);
++ val |= PCIE_PHY_TRSV3_PD_TSV;
++ exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER);
++}
++
++static void exynos_pcie_init_phy(struct pcie_port *pp)
++{
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ void __iomem *phy_base = exynos_pcie->phy_base;
++
++ /* DCC feedback control off */
++ writel(0x29, phy_base + PCIE_PHY_DCC_FEEDBACK);
++
++ /* set TX/RX impedance */
++ writel(0xd5, phy_base + PCIE_PHY_IMPEDANCE);
++
++ /* set 50Mhz PHY clock */
++ writel(0x14, phy_base + PCIE_PHY_PLL_DIV_0);
++ writel(0x12, phy_base + PCIE_PHY_PLL_DIV_1);
++
++ /* set TX Differential output for lane 0 */
++ writel(0x7f, phy_base + PCIE_PHY_TRSV0_DRV_LVL);
++
++ /* set TX Pre-emphasis Level Control for lane 0 to minimum */
++ writel(0x0, phy_base + PCIE_PHY_TRSV0_EMP_LVL);
++
++ /* set RX clock and data recovery bandwidth */
++ writel(0xe7, phy_base + PCIE_PHY_PLL_BIAS);
++ writel(0x82, phy_base + PCIE_PHY_TRSV0_RXCDR);
++ writel(0x82, phy_base + PCIE_PHY_TRSV1_RXCDR);
++ writel(0x82, phy_base + PCIE_PHY_TRSV2_RXCDR);
++ writel(0x82, phy_base + PCIE_PHY_TRSV3_RXCDR);
++
++ /* change TX Pre-emphasis Level Control for lanes */
++ writel(0x39, phy_base + PCIE_PHY_TRSV0_EMP_LVL);
++ writel(0x39, phy_base + PCIE_PHY_TRSV1_EMP_LVL);
++ writel(0x39, phy_base + PCIE_PHY_TRSV2_EMP_LVL);
++ writel(0x39, phy_base + PCIE_PHY_TRSV3_EMP_LVL);
++
++ /* set LVCC */
++ writel(0x20, phy_base + PCIE_PHY_TRSV0_LVCC);
++ writel(0xa0, phy_base + PCIE_PHY_TRSV1_LVCC);
++ writel(0xa0, phy_base + PCIE_PHY_TRSV2_LVCC);
++ writel(0xa0, phy_base + PCIE_PHY_TRSV3_LVCC);
++}
++
++static void exynos_pcie_assert_reset(struct pcie_port *pp)
++{
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++
++ if (exynos_pcie->reset_gpio >= 0)
++ devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio,
++ GPIOF_OUT_INIT_HIGH, "RESET");
++ return;
++}
++
++static int exynos_pcie_establish_link(struct pcie_port *pp)
++{
++ u32 val;
++ int count = 0;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ void __iomem *elbi_base = exynos_pcie->elbi_base;
++ void __iomem *block_base = exynos_pcie->block_base;
++ void __iomem *phy_base = exynos_pcie->phy_base;
++
++ if (dw_pcie_link_up(pp)) {
++ dev_err(pp->dev, "Link already up\n");
++ return 0;
++ }
++
++ /* assert reset signals */
++ exynos_pcie_assert_core_reset(pp);
++ exynos_pcie_assert_phy_reset(pp);
++
++ /* de-assert phy reset */
++ exynos_pcie_deassert_phy_reset(pp);
++
++ /* power on phy */
++ exynos_pcie_power_on_phy(pp);
++
++ /* initialize phy */
++ exynos_pcie_init_phy(pp);
++
++ /* pulse for common reset */
++ writel(1, block_base + PCIE_PHY_COMMON_RESET);
++ udelay(500);
++ writel(0, block_base + PCIE_PHY_COMMON_RESET);
++
++ /* de-assert core reset */
++ exynos_pcie_deassert_core_reset(pp);
++
++ /* setup root complex */
++ dw_pcie_setup_rc(pp);
++
++ /* assert reset signal */
++ exynos_pcie_assert_reset(pp);
++
++ /* assert LTSSM enable */
++ writel(PCIE_ELBI_LTSSM_ENABLE, elbi_base + PCIE_APP_LTSSM_ENABLE);
++
++ /* check if the link is up or not */
++ while (!dw_pcie_link_up(pp)) {
++ mdelay(100);
++ count++;
++ if (count == 10) {
++ while (readl(phy_base + PCIE_PHY_PLL_LOCKED) == 0) {
++ val = readl(block_base + PCIE_PHY_PLL_LOCKED);
++ dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
++ }
++ /* power off phy */
++ exynos_pcie_power_off_phy(pp);
++
++ dev_err(pp->dev, "PCIe Link Fail\n");
++ return -EINVAL;
++ }
++ }
++
++ dev_info(pp->dev, "Link up\n");
++
++ return 0;
++}
++
++static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ void __iomem *elbi_base = exynos_pcie->elbi_base;
++
++ val = readl(elbi_base + PCIE_IRQ_PULSE);
++ writel(val, elbi_base + PCIE_IRQ_PULSE);
++ return;
++}
++
++static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ void __iomem *elbi_base = exynos_pcie->elbi_base;
++
++ /* enable INTX interrupt */
++ val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT |
++ IRQ_INTC_ASSERT | IRQ_INTD_ASSERT,
++ writel(val, elbi_base + PCIE_IRQ_EN_PULSE);
++ return;
++}
++
++static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
++{
++ struct pcie_port *pp = arg;
++
++ exynos_pcie_clear_irq_pulse(pp);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
++{
++ struct pcie_port *pp = arg;
++
++ dw_handle_msi_irq(pp);
++
++ return IRQ_HANDLED;
++}
++
++static void exynos_pcie_msi_init(struct pcie_port *pp)
++{
++ u32 val;
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++
++ dw_pcie_msi_init(pp);
++
++ /* enable MSI interrupt */
++ val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL);
++ val |= IRQ_MSI_ENABLE;
++ exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL);
++ return;
++}
++
++static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
++{
++ exynos_pcie_enable_irq_pulse(pp);
++
++ if (IS_ENABLED(CONFIG_PCI_MSI))
++ exynos_pcie_msi_init(pp);
++
++ return;
++}
++
++static inline void exynos_pcie_readl_rc(struct pcie_port *pp,
++ void __iomem *dbi_base, u32 *val)
++{
++ exynos_pcie_sideband_dbi_r_mode(pp, true);
++ *val = readl(dbi_base);
++ exynos_pcie_sideband_dbi_r_mode(pp, false);
++ return;
++}
++
++static inline void exynos_pcie_writel_rc(struct pcie_port *pp,
++ u32 val, void __iomem *dbi_base)
++{
++ exynos_pcie_sideband_dbi_w_mode(pp, true);
++ writel(val, dbi_base);
++ exynos_pcie_sideband_dbi_w_mode(pp, false);
++ return;
++}
++
++static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
++ u32 *val)
++{
++ int ret;
++
++ exynos_pcie_sideband_dbi_r_mode(pp, true);
++ ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
++ exynos_pcie_sideband_dbi_r_mode(pp, false);
++ return ret;
++}
++
++static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
++ u32 val)
++{
++ int ret;
++
++ exynos_pcie_sideband_dbi_w_mode(pp, true);
++ ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
++ exynos_pcie_sideband_dbi_w_mode(pp, false);
++ return ret;
++}
++
++static int exynos_pcie_link_up(struct pcie_port *pp)
++{
++ struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
++ u32 val = readl(exynos_pcie->elbi_base + PCIE_ELBI_RDLH_LINKUP);
++
++ if (val == PCIE_ELBI_LTSSM_ENABLE)
++ return 1;
++
++ return 0;
++}
++
++static void exynos_pcie_host_init(struct pcie_port *pp)
++{
++ exynos_pcie_establish_link(pp);
++ exynos_pcie_enable_interrupts(pp);
++}
++
++static struct pcie_host_ops exynos_pcie_host_ops = {
++ .readl_rc = exynos_pcie_readl_rc,
++ .writel_rc = exynos_pcie_writel_rc,
++ .rd_own_conf = exynos_pcie_rd_own_conf,
++ .wr_own_conf = exynos_pcie_wr_own_conf,
++ .link_up = exynos_pcie_link_up,
++ .host_init = exynos_pcie_host_init,
++};
++
++static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
++{
++ int ret;
++
++ pp->irq = platform_get_irq(pdev, 1);
++ if (!pp->irq) {
++ dev_err(&pdev->dev, "failed to get irq\n");
++ return -ENODEV;
++ }
++ ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler,
++ IRQF_SHARED, "exynos-pcie", pp);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request irq\n");
++ return ret;
++ }
++
++ if (IS_ENABLED(CONFIG_PCI_MSI)) {
++ pp->msi_irq = platform_get_irq(pdev, 0);
++ if (!pp->msi_irq) {
++ dev_err(&pdev->dev, "failed to get msi irq\n");
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, pp->msi_irq,
++ exynos_pcie_msi_irq_handler,
++ IRQF_SHARED, "exynos-pcie", pp);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request msi irq\n");
++ return ret;
++ }
++ }
++
++ pp->root_bus_nr = -1;
++ pp->ops = &exynos_pcie_host_ops;
++
++ spin_lock_init(&pp->conf_lock);
++ ret = dw_pcie_host_init(pp);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to initialize host\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static int __init exynos_pcie_probe(struct platform_device *pdev)
++{
++ struct exynos_pcie *exynos_pcie;
++ struct pcie_port *pp;
++ struct device_node *np = pdev->dev.of_node;
++ struct resource *elbi_base;
++ struct resource *phy_base;
++ struct resource *block_base;
++ int ret;
++
++ exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
++ GFP_KERNEL);
++ if (!exynos_pcie) {
++ dev_err(&pdev->dev, "no memory for exynos pcie\n");
++ return -ENOMEM;
++ }
++
++ pp = &exynos_pcie->pp;
++
++ pp->dev = &pdev->dev;
++
++ exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
++
++ exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie");
++ if (IS_ERR(exynos_pcie->clk)) {
++ dev_err(&pdev->dev, "Failed to get pcie rc clock\n");
++ return PTR_ERR(exynos_pcie->clk);
++ }
++ ret = clk_prepare_enable(exynos_pcie->clk);
++ if (ret)
++ return ret;
++
++ exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
++ if (IS_ERR(exynos_pcie->bus_clk)) {
++ dev_err(&pdev->dev, "Failed to get pcie bus clock\n");
++ ret = PTR_ERR(exynos_pcie->bus_clk);
++ goto fail_clk;
++ }
++ ret = clk_prepare_enable(exynos_pcie->bus_clk);
++ if (ret)
++ goto fail_clk;
++
++ elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
++ if (IS_ERR(exynos_pcie->elbi_base)) {
++ ret = PTR_ERR(exynos_pcie->elbi_base);
++ goto fail_bus_clk;
++ }
++
++ phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
++ if (IS_ERR(exynos_pcie->phy_base)) {
++ ret = PTR_ERR(exynos_pcie->phy_base);
++ goto fail_bus_clk;
++ }
++
++ block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
++ exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
++ if (IS_ERR(exynos_pcie->block_base)) {
++ ret = PTR_ERR(exynos_pcie->block_base);
++ goto fail_bus_clk;
++ }
++
++ ret = add_pcie_port(pp, pdev);
++ if (ret < 0)
++ goto fail_bus_clk;
++
++ platform_set_drvdata(pdev, exynos_pcie);
++ return 0;
++
++fail_bus_clk:
++ clk_disable_unprepare(exynos_pcie->bus_clk);
++fail_clk:
++ clk_disable_unprepare(exynos_pcie->clk);
++ return ret;
++}
++
++static int __exit exynos_pcie_remove(struct platform_device *pdev)
++{
++ struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev);
++
++ clk_disable_unprepare(exynos_pcie->bus_clk);
++ clk_disable_unprepare(exynos_pcie->clk);
++
++ return 0;
++}
++
++static const struct of_device_id exynos_pcie_of_match[] = {
++ { .compatible = "samsung,exynos5440-pcie", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, exynos_pcie_of_match);
++
++static struct platform_driver exynos_pcie_driver = {
++ .remove = __exit_p(exynos_pcie_remove),
++ .driver = {
++ .name = "exynos-pcie",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(exynos_pcie_of_match),
++ },
++};
++
++/* Exynos PCIe driver does not allow module unload */
++
++static int __init pcie_init(void)
++{
++ return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe);
++}
++subsys_initcall(pcie_init);
++
++MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
++MODULE_DESCRIPTION("Samsung PCIe host controller driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/pci/host/pci-imx6.c linux-linaro-stable-mx6/drivers/pci/host/pci-imx6.c
+--- linux-3.10.30.orig/drivers/pci/host/pci-imx6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/host/pci-imx6.c 2014-05-15 20:34:01.698040526 +0200
+@@ -0,0 +1,857 @@
++/*
++ * PCIe host controller driver for Freescale i.MX6 SoCs
++ *
++ * Copyright (C) 2013 Kosagi
++ * http://www.kosagi.com
++ *
++ * Author: Sean Cross <xobs@kosagi.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/pci.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/resource.h>
++#include <linux/signal.h>
++#include <linux/types.h>
++#include <linux/busfreq-imx6.h>
++
++#include "pcie-designware.h"
++
++#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
++
++/*
++ * The default values of the RC's reserved ddr memory
++ * used to verify EP mode.
++ * BTW, here is the layout of the 1G ddr on SD boards
++ * 0x1000_0000 ~ 0x4FFF_FFFF
++ */
++static u32 rc_ddr_test_region = 0x40000000;
++static u32 test_region_size = SZ_2M;
++
++struct imx6_pcie {
++ int reset_gpio;
++ int power_on_gpio;
++ int wake_up_gpio;
++ int disable_gpio;
++ struct clk *lvds_gate;
++ struct clk *sata_ref_100m;
++ struct clk *pcie_ref_125m;
++ struct clk *pcie_axi;
++ struct pcie_port pp;
++ struct regmap *iomuxc_gpr;
++ void __iomem *mem_base;
++};
++
++/* PCIe Port Logic registers (memory-mapped) */
++#define PL_OFFSET 0x700
++#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
++#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
++
++#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
++#define PCIE_PHY_CTRL_DATA_LOC 0
++#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
++#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
++#define PCIE_PHY_CTRL_WR_LOC 18
++#define PCIE_PHY_CTRL_RD_LOC 19
++
++#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
++#define PCIE_PHY_STAT_ACK_LOC 16
++
++/* PHY registers (not memory-mapped) */
++#define PCIE_PHY_RX_ASIC_OUT 0x100D
++
++#define PHY_RX_OVRD_IN_LO 0x1005
++#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
++#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
++
++static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
++{
++ u32 val;
++ u32 max_iterations = 10;
++ u32 wait_counter = 0;
++
++ do {
++ val = readl(dbi_base + PCIE_PHY_STAT);
++ val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
++ wait_counter++;
++
++ if (val == exp_val)
++ return 0;
++
++ udelay(1);
++ } while (wait_counter < max_iterations);
++
++ return -ETIMEDOUT;
++}
++
++static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
++{
++ u32 val;
++ int ret;
++
++ val = addr << PCIE_PHY_CTRL_DATA_LOC;
++ writel(val, dbi_base + PCIE_PHY_CTRL);
++
++ val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
++ writel(val, dbi_base + PCIE_PHY_CTRL);
++
++ ret = pcie_phy_poll_ack(dbi_base, 1);
++ if (ret)
++ return ret;
++
++ val = addr << PCIE_PHY_CTRL_DATA_LOC;
++ writel(val, dbi_base + PCIE_PHY_CTRL);
++
++ ret = pcie_phy_poll_ack(dbi_base, 0);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
++static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
++{
++ u32 val, phy_ctl;
++ int ret;
++
++ ret = pcie_phy_wait_ack(dbi_base, addr);
++ if (ret)
++ return ret;
++
++ /* assert Read signal */
++ phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
++ writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
++
++ ret = pcie_phy_poll_ack(dbi_base, 1);
++ if (ret)
++ return ret;
++
++ val = readl(dbi_base + PCIE_PHY_STAT);
++ *data = val & 0xffff;
++
++ /* deassert Read signal */
++ writel(0x00, dbi_base + PCIE_PHY_CTRL);
++
++ ret = pcie_phy_poll_ack(dbi_base, 0);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
++{
++ u32 var;
++ int ret;
++
++ /* write addr */
++ /* cap addr */
++ ret = pcie_phy_wait_ack(dbi_base, addr);
++ if (ret)
++ return ret;
++
++ var = data << PCIE_PHY_CTRL_DATA_LOC;
++ writel(var, dbi_base + PCIE_PHY_CTRL);
++
++ /* capture data */
++ var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
++ writel(var, dbi_base + PCIE_PHY_CTRL);
++
++ ret = pcie_phy_poll_ack(dbi_base, 1);
++ if (ret)
++ return ret;
++
++ /* deassert cap data */
++ var = data << PCIE_PHY_CTRL_DATA_LOC;
++ writel(var, dbi_base + PCIE_PHY_CTRL);
++
++ /* wait for ack de-assertion */
++ ret = pcie_phy_poll_ack(dbi_base, 0);
++ if (ret)
++ return ret;
++
++ /* assert wr signal */
++ var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
++ writel(var, dbi_base + PCIE_PHY_CTRL);
++
++ /* wait for ack */
++ ret = pcie_phy_poll_ack(dbi_base, 1);
++ if (ret)
++ return ret;
++
++ /* deassert wr signal */
++ var = data << PCIE_PHY_CTRL_DATA_LOC;
++ writel(var, dbi_base + PCIE_PHY_CTRL);
++
++ /* wait for ack de-assertion */
++ ret = pcie_phy_poll_ack(dbi_base, 0);
++ if (ret)
++ return ret;
++
++ writel(0x0, dbi_base + PCIE_PHY_CTRL);
++
++ return 0;
++}
++
++/* Added for PCI abort handling */
++static int imx6q_pcie_abort_handler(unsigned long addr,
++ unsigned int fsr, struct pt_regs *regs)
++{
++ return 0;
++}
++
++static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
++{
++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++ int ret;
++
++ if (gpio_is_valid(imx6_pcie->power_on_gpio))
++ gpio_set_value(imx6_pcie->power_on_gpio, 1);
++
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
++ if (ret) {
++ dev_err(pp->dev, "unable to enable sata_ref_100m\n");
++ goto err_sata_ref;
++ }
++
++ ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
++ if (ret) {
++ dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
++ goto err_pcie_ref;
++ }
++
++ if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
++ && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) {
++ ret = clk_prepare_enable(imx6_pcie->lvds_gate);
++ if (ret) {
++ dev_err(pp->dev, "unable to enable lvds_gate\n");
++ goto err_lvds_gate;
++ }
++ }
++
++ ret = clk_prepare_enable(imx6_pcie->pcie_axi);
++ if (ret) {
++ dev_err(pp->dev, "unable to enable pcie_axi\n");
++ goto err_pcie_axi;
++ }
++
++ /* allow the clocks to stabilize */
++ usleep_range(200, 500);
++
++ if (gpio_is_valid(imx6_pcie->reset_gpio)) {
++ gpio_set_value(imx6_pcie->reset_gpio, 0);
++ msleep(100);
++ gpio_set_value(imx6_pcie->reset_gpio, 1);
++ }
++
++ return 0;
++
++err_pcie_axi:
++ clk_disable_unprepare(imx6_pcie->lvds_gate);
++err_lvds_gate:
++ clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
++err_pcie_ref:
++ clk_disable_unprepare(imx6_pcie->sata_ref_100m);
++err_sata_ref:
++ release_bus_freq(BUS_FREQ_HIGH);
++ return ret;
++
++}
++
++static void imx6_pcie_init_phy(struct pcie_port *pp)
++{
++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
++
++ /* configure constant input signal to the pcie ctrl and phy */
++ if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS))
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_DEVICE_TYPE,
++ PCI_EXP_TYPE_ENDPOINT << 12);
++ else
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_DEVICE_TYPE,
++ PCI_EXP_TYPE_ROOT_PORT << 12);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
++
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++ IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++ IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++ IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++ IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
++ IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
++}
++
++static irqreturn_t imx_pcie_msi_irq_handler(int irq, void *arg)
++{
++ struct pcie_port *pp = arg;
++
++ dw_handle_msi_irq(pp);
++
++ return IRQ_HANDLED;
++}
++
++static void imx6_pcie_host_init(struct pcie_port *pp)
++{
++ int count = 0;
++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++
++ imx6_pcie_init_phy(pp);
++
++ imx6_pcie_deassert_core_reset(pp);
++
++ dw_pcie_setup_rc(pp);
++
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
++
++ while (!dw_pcie_link_up(pp)) {
++ usleep_range(100, 1000);
++ count++;
++ if (count >= 200) {
++ dev_err(pp->dev, "phy link never came up\n");
++ dev_dbg(pp->dev,
++ "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
++ readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
++ readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
++ return;
++ }
++ }
++
++ if (IS_ENABLED(CONFIG_PCI_MSI)) {
++ pp->quirks |= DW_PCIE_QUIRK_NO_MSI_VEC;
++ pp->quirks |= DW_PCIE_QUIRK_MSI_SELF_EN;
++ dw_pcie_msi_init(pp);
++ }
++
++ return;
++}
++
++static int imx6_pcie_link_up(struct pcie_port *pp)
++{
++ u32 rc, ltssm, rx_valid, temp;
++
++ /* link is debug bit 36, debug register 1 starts at bit 32 */
++ rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32));
++ if (rc)
++ return -EAGAIN;
++
++ /*
++ * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
++ * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
++ * If (MAC/LTSSM.state == Recovery.RcvrLock)
++ * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
++ * to gen2 is stuck
++ */
++ pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
++ ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F;
++
++ if (rx_valid & 0x01)
++ return 0;
++
++ if (ltssm != 0x0d)
++ return 0;
++
++ dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
++
++ pcie_phy_read(pp->dbi_base,
++ PHY_RX_OVRD_IN_LO, &temp);
++ temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
++ | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
++ pcie_phy_write(pp->dbi_base,
++ PHY_RX_OVRD_IN_LO, temp);
++
++ usleep_range(2000, 3000);
++
++ pcie_phy_read(pp->dbi_base,
++ PHY_RX_OVRD_IN_LO, &temp);
++ temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
++ | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
++ pcie_phy_write(pp->dbi_base,
++ PHY_RX_OVRD_IN_LO, temp);
++
++ return 0;
++}
++
++static struct pcie_host_ops imx6_pcie_host_ops = {
++ .link_up = imx6_pcie_link_up,
++ .host_init = imx6_pcie_host_init,
++};
++
++static int imx6_add_pcie_port(struct pcie_port *pp,
++ struct platform_device *pdev)
++{
++ int ret;
++
++ pp->irq = platform_get_irq(pdev, 0);
++ if (!pp->irq) {
++ dev_err(&pdev->dev, "failed to get irq\n");
++ return -ENODEV;
++ }
++
++ if (IS_ENABLED(CONFIG_PCI_MSI)) {
++ pp->msi_irq = pp->irq - 3;
++ if (!pp->msi_irq) {
++ dev_err(&pdev->dev, "failed to get msi irq\n");
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, pp->msi_irq,
++ imx_pcie_msi_irq_handler,
++ IRQF_SHARED, "imx6q-pcie", pp);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request msi irq\n");
++ return ret;
++ }
++ }
++
++ pp->root_bus_nr = -1;
++ pp->ops = &imx6_pcie_host_ops;
++
++ spin_lock_init(&pp->conf_lock);
++ ret = dw_pcie_host_init(pp);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to initialize host\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static void imx_pcie_regions_setup(struct device *dev)
++{
++ struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
++ struct pcie_port *pp = &imx6_pcie->pp;
++
++ /*
++ * region0 outbound used to access RC's reserved ddr memory
++ */
++ writel(0, pp->dbi_base + PCIE_ATU_VIEWPORT);
++ writel(0x01000000, pp->dbi_base + PCIE_ATU_LOWER_BASE);
++ writel(0, pp->dbi_base + PCIE_ATU_UPPER_BASE);
++ writel(0x01000000 + test_region_size,
++ pp->dbi_base + PCIE_ATU_LIMIT);
++
++ writel(rc_ddr_test_region,
++ pp->dbi_base + PCIE_ATU_LOWER_TARGET);
++ writel(0, pp->dbi_base + PCIE_ATU_UPPER_TARGET);
++ writel(PCIE_ATU_TYPE_MEM, pp->dbi_base + PCIE_ATU_CR1);
++ writel(PCIE_ATU_ENABLE, pp->dbi_base + PCIE_ATU_CR2);
++}
++
++static ssize_t imx_pcie_rc_memw_info(struct device *dev,
++ struct device_attribute *devattr, char *buf)
++{
++ return sprintf(buf, "imx-pcie-rc-memw-info start 0x%08x, size 0x%08x\n",
++ rc_ddr_test_region, test_region_size);
++}
++
++static ssize_t
++imx_pcie_rc_memw_start(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ u32 memw_start;
++
++ sscanf(buf, "%x\n", &memw_start);
++
++ if (memw_start < 0x10000000) {
++ dev_err(dev, "Invalid memory start address.\n");
++ dev_info(dev, "For example: echo 0x41000000 > /sys/...");
++ return -1;
++ }
++
++ if (rc_ddr_test_region != memw_start) {
++ rc_ddr_test_region = memw_start;
++ /* Re-setup the iATU */
++ imx_pcie_regions_setup(dev);
++ }
++
++ return count;
++}
++
++static ssize_t
++imx_pcie_rc_memw_size(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ u32 memw_size;
++
++ sscanf(buf, "%x\n", &memw_size);
++
++ if ((memw_size > (SZ_16M - SZ_16K)) || (memw_size < SZ_64K)) {
++ dev_err(dev, "Invalid, should be [SZ_64K,SZ_16M - SZ_16KB].\n");
++ dev_info(dev, "For example: echo 0x800000 > /sys/...");
++ return -1;
++ }
++
++ if (test_region_size != memw_size) {
++ test_region_size = memw_size;
++ /* Re-setup the iATU */
++ imx_pcie_regions_setup(dev);
++ }
++
++ return count;
++}
++
++static DEVICE_ATTR(rc_memw_info, S_IRUGO, imx_pcie_rc_memw_info, NULL);
++static DEVICE_ATTR(rc_memw_start_set, S_IWUGO, NULL, imx_pcie_rc_memw_start);
++static DEVICE_ATTR(rc_memw_size_set, S_IWUGO, NULL, imx_pcie_rc_memw_size);
++
++static struct attribute *imx_pcie_attrs[] = {
++ /*
++ * The start address, and the limitation (64KB ~ (16MB - 16KB))
++ * of the ddr mem window reserved by RC, and used for EP to access.
++ * BTW, these attrs are only configured at EP side.
++ */
++ &dev_attr_rc_memw_info.attr,
++ &dev_attr_rc_memw_start_set.attr,
++ &dev_attr_rc_memw_size_set.attr,
++ NULL
++};
++
++static struct attribute_group imx_pcie_attrgroup = {
++ .attrs = imx_pcie_attrs,
++};
++
++static int __init imx6_pcie_probe(struct platform_device *pdev)
++{
++ struct imx6_pcie *imx6_pcie;
++ struct pcie_port *pp;
++ struct device_node *np = pdev->dev.of_node;
++ struct resource *dbi_base;
++ int ret, i;
++ void *test_reg1, *test_reg2;
++ void __iomem *pcie_arb_base_addr;
++ struct timeval tv1, tv2, tv3;
++ u32 tv_count1, tv_count2;
++
++ imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
++ if (!imx6_pcie)
++ return -ENOMEM;
++
++ pp = &imx6_pcie->pp;
++ pp->dev = &pdev->dev;
++
++ if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
++ /* add attributes for device */
++ ret = sysfs_create_group(&pdev->dev.kobj, &imx_pcie_attrgroup);
++ if (ret)
++ return -EINVAL;
++ }
++
++ /* Added for PCI abort handling */
++ hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
++ "imprecise external abort");
++
++ dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!dbi_base) {
++ dev_err(&pdev->dev, "dbi_base memory resource not found\n");
++ return -ENODEV;
++ }
++
++ pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
++ if (IS_ERR(pp->dbi_base)) {
++ ret = PTR_ERR(pp->dbi_base);
++ goto err;
++ }
++
++ /* Fetch GPIOs */
++ imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
++ if (gpio_is_valid(imx6_pcie->reset_gpio)) {
++ ret = devm_gpio_request_one(&pdev->dev,
++ imx6_pcie->reset_gpio,
++ GPIOF_OUT_INIT_LOW,
++ "PCIe reset");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to get reset gpio\n");
++ goto err;
++ }
++ }
++
++ imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0);
++ if (gpio_is_valid(imx6_pcie->power_on_gpio)) {
++ ret = devm_gpio_request_one(&pdev->dev,
++ imx6_pcie->power_on_gpio,
++ GPIOF_OUT_INIT_LOW,
++ "PCIe power enable");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to get power-on gpio\n");
++ goto err;
++ }
++ }
++
++ imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
++ if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
++ ret = devm_gpio_request_one(&pdev->dev,
++ imx6_pcie->wake_up_gpio,
++ GPIOF_IN,
++ "PCIe wake up");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to get wake-up gpio\n");
++ goto err;
++ }
++ }
++
++ imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
++ if (gpio_is_valid(imx6_pcie->disable_gpio)) {
++ ret = devm_gpio_request_one(&pdev->dev,
++ imx6_pcie->disable_gpio,
++ GPIOF_OUT_INIT_HIGH,
++ "PCIe disable endpoint");
++ if (ret) {
++ dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
++ goto err;
++ }
++ }
++
++ /* Fetch clocks */
++ imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
++ if (IS_ERR(imx6_pcie->lvds_gate)) {
++ dev_err(&pdev->dev,
++ "lvds_gate clock select missing or invalid\n");
++ ret = PTR_ERR(imx6_pcie->lvds_gate);
++ goto err;
++ }
++
++ imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
++ if (IS_ERR(imx6_pcie->sata_ref_100m)) {
++ dev_err(&pdev->dev,
++ "sata_ref_100m clock source missing or invalid\n");
++ ret = PTR_ERR(imx6_pcie->sata_ref_100m);
++ goto err;
++ }
++
++ imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
++ if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
++ dev_err(&pdev->dev,
++ "pcie_ref_125m clock source missing or invalid\n");
++ ret = PTR_ERR(imx6_pcie->pcie_ref_125m);
++ goto err;
++ }
++
++ imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
++ if (IS_ERR(imx6_pcie->pcie_axi)) {
++ dev_err(&pdev->dev,
++ "pcie_axi clock source missing or invalid\n");
++ ret = PTR_ERR(imx6_pcie->pcie_axi);
++ goto err;
++ }
++
++ /* Grab GPR config register range */
++ imx6_pcie->iomuxc_gpr =
++ syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
++ dev_err(&pdev->dev, "unable to find iomuxc registers\n");
++ ret = PTR_ERR(imx6_pcie->iomuxc_gpr);
++ goto err;
++ }
++
++ if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
++ if (IS_ENABLED(CONFIG_EP_SELF_IO_TEST)) {
++ /* Prepare the test regions and data */
++ test_reg1 = devm_kzalloc(&pdev->dev,
++ test_region_size, GFP_KERNEL);
++ if (!test_reg1) {
++ pr_err("pcie ep: can't alloc the test reg1.\n");
++ ret = PTR_ERR(test_reg1);
++ goto err;
++ }
++
++ test_reg2 = devm_kzalloc(&pdev->dev,
++ test_region_size, GFP_KERNEL);
++ if (!test_reg2) {
++ pr_err("pcie ep: can't alloc the test reg2.\n");
++ ret = PTR_ERR(test_reg1);
++ goto err;
++ }
++
++ pcie_arb_base_addr = ioremap_cached(0x01000000,
++ test_region_size);
++
++ if (!pcie_arb_base_addr) {
++ pr_err("error with ioremap in ep selftest\n");
++ ret = PTR_ERR(pcie_arb_base_addr);
++ goto err;
++ }
++
++ for (i = 0; i < test_region_size; i = i + 4) {
++ writel(0xE6600D00 + i, test_reg1 + i);
++ writel(0xDEADBEAF, test_reg2 + i);
++ }
++ }
++
++ imx6_pcie_init_phy(pp);
++
++ imx6_pcie_deassert_core_reset(pp);
++
++ /* assert LTSSM enable */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
++
++
++ dev_info(&pdev->dev, "PCIe EP: waiting for link up...\n");
++
++ platform_set_drvdata(pdev, imx6_pcie);
++ /* link is indicated by the bit4 of DB_R1 register */
++ do {
++ usleep_range(10, 20);
++ } while ((readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & 0x10) == 0);
++
++ /* CMD reg:I/O space, MEM space, and Bus Master Enable */
++ writel(readl(pp->dbi_base + PCI_COMMAND)
++ | PCI_COMMAND_IO
++ | PCI_COMMAND_MEMORY
++ | PCI_COMMAND_MASTER,
++ pp->dbi_base + PCI_COMMAND);
++
++ /*
++ * configure the class_rev(emaluate one memory ram ep device),
++ * bar0 and bar1 of ep
++ */
++ writel(0xdeadbeaf, pp->dbi_base + PCI_VENDOR_ID);
++ writel(readl(pp->dbi_base + PCI_CLASS_REVISION)
++ | (PCI_CLASS_MEMORY_RAM << 16),
++ pp->dbi_base + PCI_CLASS_REVISION);
++ writel(0xdeadbeaf, pp->dbi_base
++ + PCI_SUBSYSTEM_VENDOR_ID);
++
++ /* 32bit none-prefetchable 8M bytes memory on bar0 */
++ writel(0x0, pp->dbi_base + PCI_BASE_ADDRESS_0);
++ writel(SZ_8M - 1, pp->dbi_base + (1 << 12)
++ + PCI_BASE_ADDRESS_0);
++
++ /* None used bar1 */
++ writel(0x0, pp->dbi_base + PCI_BASE_ADDRESS_1);
++ writel(0, pp->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_1);
++
++ /* 4K bytes IO on bar2 */
++ writel(0x1, pp->dbi_base + PCI_BASE_ADDRESS_2);
++ writel(SZ_4K - 1, pp->dbi_base + (1 << 12) +
++ PCI_BASE_ADDRESS_2);
++
++ /*
++ * 32bit prefetchable 1M bytes memory on bar3
++ * FIXME BAR MASK3 is not changable, the size
++ * is fixed to 256 bytes.
++ */
++ writel(0x8, pp->dbi_base + PCI_BASE_ADDRESS_3);
++ writel(SZ_1M - 1, pp->dbi_base + (1 << 12)
++ + PCI_BASE_ADDRESS_3);
++
++ /*
++ * 64bit prefetchable 1M bytes memory on bar4-5.
++ * FIXME BAR4,5 are not enabled yet
++ */
++ writel(0xc, pp->dbi_base + PCI_BASE_ADDRESS_4);
++ writel(SZ_1M - 1, pp->dbi_base + (1 << 12)
++ + PCI_BASE_ADDRESS_4);
++ writel(0, pp->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_5);
++
++ /* Re-setup the iATU */
++ imx_pcie_regions_setup(&pdev->dev);
++
++ if (IS_ENABLED(CONFIG_EP_SELF_IO_TEST)) {
++ /* PCIe EP start the data transfer after link up */
++ pr_info("pcie ep: Starting data transfer...\n");
++ do_gettimeofday(&tv1);
++
++ memcpy((unsigned long *)pcie_arb_base_addr,
++ (unsigned long *)test_reg1,
++ test_region_size);
++
++ do_gettimeofday(&tv2);
++
++ memcpy((unsigned long *)test_reg2,
++ (unsigned long *)pcie_arb_base_addr,
++ test_region_size);
++
++ do_gettimeofday(&tv3);
++
++ if (memcmp(test_reg2, test_reg1, test_region_size) == 0) {
++ tv_count1 = (tv2.tv_sec - tv1.tv_sec)
++ * USEC_PER_SEC
++ + tv2.tv_usec - tv1.tv_usec;
++ tv_count2 = (tv3.tv_sec - tv2.tv_sec)
++ * USEC_PER_SEC
++ + tv3.tv_usec - tv2.tv_usec;
++
++ pr_info("pcie ep: Data transfer is successful."
++ " tv_count1 %dus,"
++ " tv_count2 %dus.\n",
++ tv_count1, tv_count2);
++ pr_info("pcie ep: Data write speed:%ldMB/s.\n",
++ ((test_region_size/1024)
++ * MSEC_PER_SEC)
++ /(tv_count1));
++ pr_info("pcie ep: Data read speed:%ldMB/s.\n",
++ ((test_region_size/1024)
++ * MSEC_PER_SEC)
++ /(tv_count2));
++ } else {
++ pr_info("pcie ep: Data transfer is failed.\n");
++ }
++ }
++ } else {
++ ret = imx6_add_pcie_port(pp, pdev);
++ if (ret < 0)
++ goto err;
++
++ platform_set_drvdata(pdev, imx6_pcie);
++ }
++ return 0;
++
++err:
++ return ret;
++}
++
++static const struct of_device_id imx6_pcie_of_match[] = {
++ { .compatible = "fsl,imx6q-pcie", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
++
++static struct platform_driver imx6_pcie_driver = {
++ .driver = {
++ .name = "imx6q-pcie",
++ .owner = THIS_MODULE,
++ .of_match_table = imx6_pcie_of_match,
++ },
++};
++
++/* Freescale PCIe driver does not allow module unload */
++
++static int __init imx6_pcie_init(void)
++{
++ return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
++}
++fs_initcall(imx6_pcie_init);
++
++MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
++MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/pci/host/pci-mvebu.c linux-linaro-stable-mx6/drivers/pci/host/pci-mvebu.c
+--- linux-3.10.30.orig/drivers/pci/host/pci-mvebu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/host/pci-mvebu.c 2014-05-15 20:34:01.698040526 +0200
+@@ -0,0 +1,881 @@
++/*
++ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/kernel.h>
++#include <linux/pci.h>
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/mbus.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++#include <linux/of_address.h>
++#include <linux/of_pci.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++
++/*
++ * PCIe unit register offsets.
++ */
++#define PCIE_DEV_ID_OFF 0x0000
++#define PCIE_CMD_OFF 0x0004
++#define PCIE_DEV_REV_OFF 0x0008
++#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
++#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
++#define PCIE_HEADER_LOG_4_OFF 0x0128
++#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
++#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
++#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
++#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
++#define PCIE_WIN5_CTRL_OFF 0x1880
++#define PCIE_WIN5_BASE_OFF 0x1884
++#define PCIE_WIN5_REMAP_OFF 0x188c
++#define PCIE_CONF_ADDR_OFF 0x18f8
++#define PCIE_CONF_ADDR_EN 0x80000000
++#define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
++#define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
++#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
++#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
++#define PCIE_CONF_ADDR(bus, devfn, where) \
++ (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
++ PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
++ PCIE_CONF_ADDR_EN)
++#define PCIE_CONF_DATA_OFF 0x18fc
++#define PCIE_MASK_OFF 0x1910
++#define PCIE_MASK_ENABLE_INTS 0x0f000000
++#define PCIE_CTRL_OFF 0x1a00
++#define PCIE_CTRL_X1_MODE 0x0001
++#define PCIE_STAT_OFF 0x1a04
++#define PCIE_STAT_BUS 0xff00
++#define PCIE_STAT_LINK_DOWN BIT(0)
++#define PCIE_DEBUG_CTRL 0x1a60
++#define PCIE_DEBUG_SOFT_RESET BIT(20)
++
++/*
++ * This product ID is registered by Marvell, and used when the Marvell
++ * SoC is not the root complex, but an endpoint on the PCIe bus. It is
++ * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
++ * bridge.
++ */
++#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
++
++/* PCI configuration space of a PCI-to-PCI bridge */
++struct mvebu_sw_pci_bridge {
++ u16 vendor;
++ u16 device;
++ u16 command;
++ u16 status;
++ u16 class;
++ u8 interface;
++ u8 revision;
++ u8 bist;
++ u8 header_type;
++ u8 latency_timer;
++ u8 cache_line_size;
++ u32 bar[2];
++ u8 primary_bus;
++ u8 secondary_bus;
++ u8 subordinate_bus;
++ u8 secondary_latency_timer;
++ u8 iobase;
++ u8 iolimit;
++ u16 secondary_status;
++ u16 membase;
++ u16 memlimit;
++ u16 prefmembase;
++ u16 prefmemlimit;
++ u32 prefbaseupper;
++ u32 preflimitupper;
++ u16 iobaseupper;
++ u16 iolimitupper;
++ u8 cappointer;
++ u8 reserved1;
++ u16 reserved2;
++ u32 romaddr;
++ u8 intline;
++ u8 intpin;
++ u16 bridgectrl;
++};
++
++struct mvebu_pcie_port;
++
++/* Structure representing all PCIe interfaces */
++struct mvebu_pcie {
++ struct platform_device *pdev;
++ struct mvebu_pcie_port *ports;
++ struct resource io;
++ struct resource realio;
++ struct resource mem;
++ struct resource busn;
++ int nports;
++};
++
++/* Structure representing one PCIe interface */
++struct mvebu_pcie_port {
++ char *name;
++ void __iomem *base;
++ spinlock_t conf_lock;
++ int haslink;
++ u32 port;
++ u32 lane;
++ int devfn;
++ struct clk *clk;
++ struct mvebu_sw_pci_bridge bridge;
++ struct device_node *dn;
++ struct mvebu_pcie *pcie;
++ phys_addr_t memwin_base;
++ size_t memwin_size;
++ phys_addr_t iowin_base;
++ size_t iowin_size;
++};
++
++static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
++{
++ return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
++}
++
++static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
++{
++ u32 stat;
++
++ stat = readl(port->base + PCIE_STAT_OFF);
++ stat &= ~PCIE_STAT_BUS;
++ stat |= nr << 8;
++ writel(stat, port->base + PCIE_STAT_OFF);
++}
++
++/*
++ * Setup PCIE BARs and Address Decode Wins:
++ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
++ * WIN[0-3] -> DRAM bank[0-3]
++ */
++static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
++{
++ const struct mbus_dram_target_info *dram;
++ u32 size;
++ int i;
++
++ dram = mv_mbus_dram_info();
++
++ /* First, disable and clear BARs and windows. */
++ for (i = 1; i < 3; i++) {
++ writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
++ writel(0, port->base + PCIE_BAR_LO_OFF(i));
++ writel(0, port->base + PCIE_BAR_HI_OFF(i));
++ }
++
++ for (i = 0; i < 5; i++) {
++ writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
++ writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
++ writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
++ }
++
++ writel(0, port->base + PCIE_WIN5_CTRL_OFF);
++ writel(0, port->base + PCIE_WIN5_BASE_OFF);
++ writel(0, port->base + PCIE_WIN5_REMAP_OFF);
++
++ /* Setup windows for DDR banks. Count total DDR size on the fly. */
++ size = 0;
++ for (i = 0; i < dram->num_cs; i++) {
++ const struct mbus_dram_window *cs = dram->cs + i;
++
++ writel(cs->base & 0xffff0000,
++ port->base + PCIE_WIN04_BASE_OFF(i));
++ writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
++ writel(((cs->size - 1) & 0xffff0000) |
++ (cs->mbus_attr << 8) |
++ (dram->mbus_dram_target_id << 4) | 1,
++ port->base + PCIE_WIN04_CTRL_OFF(i));
++
++ size += cs->size;
++ }
++
++ /* Round up 'size' to the nearest power of two. */
++ if ((size & (size - 1)) != 0)
++ size = 1 << fls(size);
++
++ /* Setup BAR[1] to all DRAM banks. */
++ writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
++ writel(0, port->base + PCIE_BAR_HI_OFF(1));
++ writel(((size - 1) & 0xffff0000) | 1,
++ port->base + PCIE_BAR_CTRL_OFF(1));
++}
++
++static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
++{
++ u16 cmd;
++ u32 mask;
++
++ /* Point PCIe unit MBUS decode windows to DRAM space. */
++ mvebu_pcie_setup_wins(port);
++
++ /* Master + slave enable. */
++ cmd = readw(port->base + PCIE_CMD_OFF);
++ cmd |= PCI_COMMAND_IO;
++ cmd |= PCI_COMMAND_MEMORY;
++ cmd |= PCI_COMMAND_MASTER;
++ writew(cmd, port->base + PCIE_CMD_OFF);
++
++ /* Enable interrupt lines A-D. */
++ mask = readl(port->base + PCIE_MASK_OFF);
++ mask |= PCIE_MASK_ENABLE_INTS;
++ writel(mask, port->base + PCIE_MASK_OFF);
++}
++
++static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
++ struct pci_bus *bus,
++ u32 devfn, int where, int size, u32 *val)
++{
++ writel(PCIE_CONF_ADDR(bus->number, devfn, where),
++ port->base + PCIE_CONF_ADDR_OFF);
++
++ *val = readl(port->base + PCIE_CONF_DATA_OFF);
++
++ if (size == 1)
++ *val = (*val >> (8 * (where & 3))) & 0xff;
++ else if (size == 2)
++ *val = (*val >> (8 * (where & 3))) & 0xffff;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
++ struct pci_bus *bus,
++ u32 devfn, int where, int size, u32 val)
++{
++ int ret = PCIBIOS_SUCCESSFUL;
++
++ writel(PCIE_CONF_ADDR(bus->number, devfn, where),
++ port->base + PCIE_CONF_ADDR_OFF);
++
++ if (size == 4)
++ writel(val, port->base + PCIE_CONF_DATA_OFF);
++ else if (size == 2)
++ writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
++ else if (size == 1)
++ writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
++ else
++ ret = PCIBIOS_BAD_REGISTER_NUMBER;
++
++ return ret;
++}
++
++static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
++{
++ phys_addr_t iobase;
++
++ /* Are the new iobase/iolimit values invalid? */
++ if (port->bridge.iolimit < port->bridge.iobase ||
++ port->bridge.iolimitupper < port->bridge.iobaseupper) {
++
++ /* If a window was configured, remove it */
++ if (port->iowin_base) {
++ mvebu_mbus_del_window(port->iowin_base,
++ port->iowin_size);
++ port->iowin_base = 0;
++ port->iowin_size = 0;
++ }
++
++ return;
++ }
++
++ /*
++ * We read the PCI-to-PCI bridge emulated registers, and
++ * calculate the base address and size of the address decoding
++ * window to setup, according to the PCI-to-PCI bridge
++ * specifications. iobase is the bus address, port->iowin_base
++ * is the CPU address.
++ */
++ iobase = ((port->bridge.iobase & 0xF0) << 8) |
++ (port->bridge.iobaseupper << 16);
++ port->iowin_base = port->pcie->io.start + iobase;
++ port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
++ (port->bridge.iolimitupper << 16)) -
++ iobase);
++
++ mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
++ port->iowin_size,
++ iobase,
++ MVEBU_MBUS_PCI_IO);
++
++ pci_ioremap_io(iobase, port->iowin_base);
++}
++
++static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
++{
++ /* Are the new membase/memlimit values invalid? */
++ if (port->bridge.memlimit < port->bridge.membase) {
++
++ /* If a window was configured, remove it */
++ if (port->memwin_base) {
++ mvebu_mbus_del_window(port->memwin_base,
++ port->memwin_size);
++ port->memwin_base = 0;
++ port->memwin_size = 0;
++ }
++
++ return;
++ }
++
++ /*
++ * We read the PCI-to-PCI bridge emulated registers, and
++ * calculate the base address and size of the address decoding
++ * window to setup, according to the PCI-to-PCI bridge
++ * specifications.
++ */
++ port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
++ port->memwin_size =
++ (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
++ port->memwin_base;
++
++ mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
++ port->memwin_size,
++ MVEBU_MBUS_NO_REMAP,
++ MVEBU_MBUS_PCI_MEM);
++}
++
++/*
++ * Initialize the configuration space of the PCI-to-PCI bridge
++ * associated with the given PCIe interface.
++ */
++static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
++{
++ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
++
++ memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
++
++ bridge->status = PCI_STATUS_CAP_LIST;
++ bridge->class = PCI_CLASS_BRIDGE_PCI;
++ bridge->vendor = PCI_VENDOR_ID_MARVELL;
++ bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
++ bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
++ bridge->cache_line_size = 0x10;
++
++ /* We support 32 bits I/O addressing */
++ bridge->iobase = PCI_IO_RANGE_TYPE_32;
++ bridge->iolimit = PCI_IO_RANGE_TYPE_32;
++}
++
++/*
++ * Read the configuration space of the PCI-to-PCI bridge associated to
++ * the given PCIe interface.
++ */
++static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
++ unsigned int where, int size, u32 *value)
++{
++ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
++
++ switch (where & ~3) {
++ case PCI_VENDOR_ID:
++ *value = bridge->device << 16 | bridge->vendor;
++ break;
++
++ case PCI_COMMAND:
++ *value = bridge->status << 16 | bridge->command;
++ break;
++
++ case PCI_CLASS_REVISION:
++ *value = bridge->class << 16 | bridge->interface << 8 |
++ bridge->revision;
++ break;
++
++ case PCI_CACHE_LINE_SIZE:
++ *value = bridge->bist << 24 | bridge->header_type << 16 |
++ bridge->latency_timer << 8 | bridge->cache_line_size;
++ break;
++
++ case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
++ *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
++ break;
++
++ case PCI_PRIMARY_BUS:
++ *value = (bridge->secondary_latency_timer << 24 |
++ bridge->subordinate_bus << 16 |
++ bridge->secondary_bus << 8 |
++ bridge->primary_bus);
++ break;
++
++ case PCI_IO_BASE:
++ *value = (bridge->secondary_status << 16 |
++ bridge->iolimit << 8 |
++ bridge->iobase);
++ break;
++
++ case PCI_MEMORY_BASE:
++ *value = (bridge->memlimit << 16 | bridge->membase);
++ break;
++
++ case PCI_PREF_MEMORY_BASE:
++ *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
++ break;
++
++ case PCI_PREF_BASE_UPPER32:
++ *value = bridge->prefbaseupper;
++ break;
++
++ case PCI_PREF_LIMIT_UPPER32:
++ *value = bridge->preflimitupper;
++ break;
++
++ case PCI_IO_BASE_UPPER16:
++ *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
++ break;
++
++ case PCI_ROM_ADDRESS1:
++ *value = 0;
++ break;
++
++ default:
++ *value = 0xffffffff;
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ }
++
++ if (size == 2)
++ *value = (*value >> (8 * (where & 3))) & 0xffff;
++ else if (size == 1)
++ *value = (*value >> (8 * (where & 3))) & 0xff;
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++/* Write to the PCI-to-PCI bridge configuration space */
++static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
++ unsigned int where, int size, u32 value)
++{
++ struct mvebu_sw_pci_bridge *bridge = &port->bridge;
++ u32 mask, reg;
++ int err;
++
++ if (size == 4)
++ mask = 0x0;
++ else if (size == 2)
++ mask = ~(0xffff << ((where & 3) * 8));
++ else if (size == 1)
++ mask = ~(0xff << ((where & 3) * 8));
++ else
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
++ if (err)
++ return err;
++
++ value = (reg & mask) | value << ((where & 3) * 8);
++
++ switch (where & ~3) {
++ case PCI_COMMAND:
++ bridge->command = value & 0xffff;
++ bridge->status = value >> 16;
++ break;
++
++ case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
++ bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
++ break;
++
++ case PCI_IO_BASE:
++ /*
++ * We also keep bit 1 set, it is a read-only bit that
++ * indicates we support 32 bits addressing for the
++ * I/O
++ */
++ bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
++ bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
++ bridge->secondary_status = value >> 16;
++ mvebu_pcie_handle_iobase_change(port);
++ break;
++
++ case PCI_MEMORY_BASE:
++ bridge->membase = value & 0xffff;
++ bridge->memlimit = value >> 16;
++ mvebu_pcie_handle_membase_change(port);
++ break;
++
++ case PCI_PREF_MEMORY_BASE:
++ bridge->prefmembase = value & 0xffff;
++ bridge->prefmemlimit = value >> 16;
++ break;
++
++ case PCI_PREF_BASE_UPPER32:
++ bridge->prefbaseupper = value;
++ break;
++
++ case PCI_PREF_LIMIT_UPPER32:
++ bridge->preflimitupper = value;
++ break;
++
++ case PCI_IO_BASE_UPPER16:
++ bridge->iobaseupper = value & 0xffff;
++ bridge->iolimitupper = value >> 16;
++ mvebu_pcie_handle_iobase_change(port);
++ break;
++
++ case PCI_PRIMARY_BUS:
++ bridge->primary_bus = value & 0xff;
++ bridge->secondary_bus = (value >> 8) & 0xff;
++ bridge->subordinate_bus = (value >> 16) & 0xff;
++ bridge->secondary_latency_timer = (value >> 24) & 0xff;
++ mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
++ break;
++
++ default:
++ break;
++ }
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
++{
++ return sys->private_data;
++}
++
++static struct mvebu_pcie_port *
++mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
++ int devfn)
++{
++ int i;
++
++ for (i = 0; i < pcie->nports; i++) {
++ struct mvebu_pcie_port *port = &pcie->ports[i];
++ if (bus->number == 0 && port->devfn == devfn)
++ return port;
++ if (bus->number != 0 &&
++ port->bridge.secondary_bus == bus->number)
++ return port;
++ }
++
++ return NULL;
++}
++
++/* PCI configuration space write function */
++static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
++ int where, int size, u32 val)
++{
++ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
++ struct mvebu_pcie_port *port;
++ unsigned long flags;
++ int ret;
++
++ port = mvebu_pcie_find_port(pcie, bus, devfn);
++ if (!port)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ /* Access the emulated PCI-to-PCI bridge */
++ if (bus->number == 0)
++ return mvebu_sw_pci_bridge_write(port, where, size, val);
++
++ if (!port->haslink || PCI_SLOT(devfn) != 0)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ /* Access the real PCIe interface */
++ spin_lock_irqsave(&port->conf_lock, flags);
++ ret = mvebu_pcie_hw_wr_conf(port, bus,
++ PCI_DEVFN(1, PCI_FUNC(devfn)),
++ where, size, val);
++ spin_unlock_irqrestore(&port->conf_lock, flags);
++
++ return ret;
++}
++
++/* PCI configuration space read function */
++static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
++ int size, u32 *val)
++{
++ struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
++ struct mvebu_pcie_port *port;
++ unsigned long flags;
++ int ret;
++
++ port = mvebu_pcie_find_port(pcie, bus, devfn);
++ if (!port) {
++ *val = 0xffffffff;
++ return PCIBIOS_DEVICE_NOT_FOUND;
++ }
++
++ /* Access the emulated PCI-to-PCI bridge */
++ if (bus->number == 0)
++ return mvebu_sw_pci_bridge_read(port, where, size, val);
++
++ if (!port->haslink || PCI_SLOT(devfn) != 0) {
++ *val = 0xffffffff;
++ return PCIBIOS_DEVICE_NOT_FOUND;
++ }
++
++ /* Access the real PCIe interface */
++ spin_lock_irqsave(&port->conf_lock, flags);
++ ret = mvebu_pcie_hw_rd_conf(port, bus,
++ PCI_DEVFN(1, PCI_FUNC(devfn)),
++ where, size, val);
++ spin_unlock_irqrestore(&port->conf_lock, flags);
++
++ return ret;
++}
++
++static struct pci_ops mvebu_pcie_ops = {
++ .read = mvebu_pcie_rd_conf,
++ .write = mvebu_pcie_wr_conf,
++};
++
++static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
++{
++ struct mvebu_pcie *pcie = sys_to_pcie(sys);
++ int i;
++
++ pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
++ pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
++ pci_add_resource(&sys->resources, &pcie->busn);
++
++ for (i = 0; i < pcie->nports; i++) {
++ struct mvebu_pcie_port *port = &pcie->ports[i];
++ mvebu_pcie_setup_hw(port);
++ }
++
++ return 1;
++}
++
++static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++ struct of_irq oirq;
++ int ret;
++
++ ret = of_irq_map_pci(dev, &oirq);
++ if (ret)
++ return ret;
++
++ return irq_create_of_mapping(oirq.controller, oirq.specifier,
++ oirq.size);
++}
++
++static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
++{
++ struct mvebu_pcie *pcie = sys_to_pcie(sys);
++ struct pci_bus *bus;
++
++ bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
++ &mvebu_pcie_ops, sys, &sys->resources);
++ if (!bus)
++ return NULL;
++
++ pci_scan_child_bus(bus);
++
++ return bus;
++}
++
++resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
++ const struct resource *res,
++ resource_size_t start,
++ resource_size_t size,
++ resource_size_t align)
++{
++ if (dev->bus->number != 0)
++ return start;
++
++ /*
++ * On the PCI-to-PCI bridge side, the I/O windows must have at
++ * least a 64 KB size and be aligned on their size, and the
++ * memory windows must have at least a 1 MB size and be
++ * aligned on their size
++ */
++ if (res->flags & IORESOURCE_IO)
++ return round_up(start, max((resource_size_t)SZ_64K, size));
++ else if (res->flags & IORESOURCE_MEM)
++ return round_up(start, max((resource_size_t)SZ_1M, size));
++ else
++ return start;
++}
++
++static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
++{
++ struct hw_pci hw;
++
++ memset(&hw, 0, sizeof(hw));
++
++ hw.nr_controllers = 1;
++ hw.private_data = (void **)&pcie;
++ hw.setup = mvebu_pcie_setup;
++ hw.scan = mvebu_pcie_scan_bus;
++ hw.map_irq = mvebu_pcie_map_irq;
++ hw.ops = &mvebu_pcie_ops;
++ hw.align_resource = mvebu_pcie_align_resource;
++
++ pci_common_init(&hw);
++}
++
++/*
++ * Looks up the list of register addresses encoded into the reg =
++ * <...> property for one that matches the given port/lane. Once
++ * found, maps it.
++ */
++static void __iomem * __init
++mvebu_pcie_map_registers(struct platform_device *pdev,
++ struct device_node *np,
++ struct mvebu_pcie_port *port)
++{
++ struct resource regs;
++ int ret = 0;
++
++ ret = of_address_to_resource(np, 0, &regs);
++ if (ret)
++ return NULL;
++
++ return devm_request_and_ioremap(&pdev->dev, &regs);
++}
++
++static int __init mvebu_pcie_probe(struct platform_device *pdev)
++{
++ struct mvebu_pcie *pcie;
++ struct device_node *np = pdev->dev.of_node;
++ struct of_pci_range range;
++ struct of_pci_range_parser parser;
++ struct device_node *child;
++ int i, ret;
++
++ pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
++ GFP_KERNEL);
++ if (!pcie)
++ return -ENOMEM;
++
++ pcie->pdev = pdev;
++
++ if (of_pci_range_parser_init(&parser, np))
++ return -EINVAL;
++
++ /* Get the I/O and memory ranges from DT */
++ for_each_of_pci_range(&parser, &range) {
++ unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
++ if (restype == IORESOURCE_IO) {
++ of_pci_range_to_resource(&range, np, &pcie->io);
++ of_pci_range_to_resource(&range, np, &pcie->realio);
++ pcie->io.name = "I/O";
++ pcie->realio.start = max_t(resource_size_t,
++ PCIBIOS_MIN_IO,
++ range.pci_addr);
++ pcie->realio.end = min_t(resource_size_t,
++ IO_SPACE_LIMIT,
++ range.pci_addr + range.size);
++ }
++ if (restype == IORESOURCE_MEM) {
++ of_pci_range_to_resource(&range, np, &pcie->mem);
++ pcie->mem.name = "MEM";
++ }
++ }
++
++ /* Get the bus range */
++ ret = of_pci_parse_bus_range(np, &pcie->busn);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
++ ret);
++ return ret;
++ }
++
++ for_each_child_of_node(pdev->dev.of_node, child) {
++ if (!of_device_is_available(child))
++ continue;
++ pcie->nports++;
++ }
++
++ pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
++ sizeof(struct mvebu_pcie_port),
++ GFP_KERNEL);
++ if (!pcie->ports)
++ return -ENOMEM;
++
++ i = 0;
++ for_each_child_of_node(pdev->dev.of_node, child) {
++ struct mvebu_pcie_port *port = &pcie->ports[i];
++
++ if (!of_device_is_available(child))
++ continue;
++
++ port->pcie = pcie;
++
++ if (of_property_read_u32(child, "marvell,pcie-port",
++ &port->port)) {
++ dev_warn(&pdev->dev,
++ "ignoring PCIe DT node, missing pcie-port property\n");
++ continue;
++ }
++
++ if (of_property_read_u32(child, "marvell,pcie-lane",
++ &port->lane))
++ port->lane = 0;
++
++ port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
++ port->port, port->lane);
++
++ port->devfn = of_pci_get_devfn(child);
++ if (port->devfn < 0)
++ continue;
++
++ port->base = mvebu_pcie_map_registers(pdev, child, port);
++ if (!port->base) {
++ dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
++ port->port, port->lane);
++ continue;
++ }
++
++ if (mvebu_pcie_link_up(port)) {
++ port->haslink = 1;
++ dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
++ port->port, port->lane);
++ } else {
++ port->haslink = 0;
++ dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
++ port->port, port->lane);
++ }
++
++ port->clk = of_clk_get_by_name(child, NULL);
++ if (!port->clk) {
++ dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
++ port->port, port->lane);
++ iounmap(port->base);
++ port->haslink = 0;
++ continue;
++ }
++
++ port->dn = child;
++
++ clk_prepare_enable(port->clk);
++ spin_lock_init(&port->conf_lock);
++
++ mvebu_sw_pci_bridge_init(port);
++
++ i++;
++ }
++
++ mvebu_pcie_enable(pcie);
++
++ return 0;
++}
++
++static const struct of_device_id mvebu_pcie_of_match_table[] = {
++ { .compatible = "marvell,armada-xp-pcie", },
++ { .compatible = "marvell,armada-370-pcie", },
++ { .compatible = "marvell,kirkwood-pcie", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
++
++static struct platform_driver mvebu_pcie_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "mvebu-pcie",
++ .of_match_table =
++ of_match_ptr(mvebu_pcie_of_match_table),
++ },
++};
++
++static int __init mvebu_pcie_init(void)
++{
++ return platform_driver_probe(&mvebu_pcie_driver,
++ mvebu_pcie_probe);
++}
++
++subsys_initcall(mvebu_pcie_init);
++
++MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
++MODULE_DESCRIPTION("Marvell EBU PCIe driver");
++MODULE_LICENSE("GPLv2");
+diff -Nur linux-3.10.30.orig/drivers/pci/Kconfig linux-linaro-stable-mx6/drivers/pci/Kconfig
+--- linux-3.10.30.orig/drivers/pci/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/Kconfig 2014-05-15 20:34:01.694040498 +0200
+@@ -119,3 +119,5 @@
+ config PCI_LABEL
+ def_bool y if (DMI || ACPI)
+ select NLS
++
++source "drivers/pci/host/Kconfig"
+diff -Nur linux-3.10.30.orig/drivers/pci/Makefile linux-linaro-stable-mx6/drivers/pci/Makefile
+--- linux-3.10.30.orig/drivers/pci/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/Makefile 2014-05-15 20:34:01.694040498 +0200
+@@ -67,3 +67,6 @@
+ obj-$(CONFIG_OF) += of.o
+
+ ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
++
++# PCI host controller drivers
++obj-y += host/
+diff -Nur linux-3.10.30.orig/drivers/pci/msi.c linux-linaro-stable-mx6/drivers/pci/msi.c
+--- linux-3.10.30.orig/drivers/pci/msi.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/msi.c 2014-05-15 20:34:01.758040959 +0200
+@@ -30,20 +30,44 @@
+
+ /* Arch hooks */
+
+-#ifndef arch_msi_check_device
+-int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
++int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
+ {
++ struct msi_chip *chip = dev->bus->msi;
++ int err;
++
++ if (!chip || !chip->setup_irq)
++ return -EINVAL;
++
++ err = chip->setup_irq(chip, dev, desc);
++ if (err < 0)
++ return err;
++
++ irq_set_chip_data(desc->irq, chip);
++
+ return 0;
+ }
+-#endif
+
+-#ifndef arch_setup_msi_irqs
+-# define arch_setup_msi_irqs default_setup_msi_irqs
+-# define HAVE_DEFAULT_MSI_SETUP_IRQS
+-#endif
++void __weak arch_teardown_msi_irq(unsigned int irq)
++{
++ struct msi_chip *chip = irq_get_chip_data(irq);
++
++ if (!chip || !chip->teardown_irq)
++ return;
++
++ chip->teardown_irq(chip, irq);
++}
++
++int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
++{
++ struct msi_chip *chip = dev->bus->msi;
++
++ if (!chip || !chip->check_device)
++ return 0;
++
++ return chip->check_device(chip, dev, nvec, type);
++}
+
+-#ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
+-int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
++int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+ {
+ struct msi_desc *entry;
+ int ret;
+@@ -65,14 +89,11 @@
+
+ return 0;
+ }
+-#endif
+
+-#ifndef arch_teardown_msi_irqs
+-# define arch_teardown_msi_irqs default_teardown_msi_irqs
+-# define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
+-#endif
+-
+-#ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
++/*
++ * We have a default implementation available as a separate non-weak
++ * function, as it is used by the Xen x86 PCI code
++ */
+ void default_teardown_msi_irqs(struct pci_dev *dev)
+ {
+ struct msi_desc *entry;
+@@ -81,19 +102,20 @@
+ int i, nvec;
+ if (entry->irq == 0)
+ continue;
+- nvec = 1 << entry->msi_attrib.multiple;
++ if (entry->nvec_used)
++ nvec = entry->nvec_used;
++ else
++ nvec = 1 << entry->msi_attrib.multiple;
+ for (i = 0; i < nvec; i++)
+ arch_teardown_msi_irq(entry->irq + i);
+ }
+ }
+-#endif
+
+-#ifndef arch_restore_msi_irqs
+-# define arch_restore_msi_irqs default_restore_msi_irqs
+-# define HAVE_DEFAULT_MSI_RESTORE_IRQS
+-#endif
++void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
++{
++ return default_teardown_msi_irqs(dev);
++}
+
+-#ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
+ void default_restore_msi_irqs(struct pci_dev *dev, int irq)
+ {
+ struct msi_desc *entry;
+@@ -111,7 +133,11 @@
+ if (entry)
+ write_msi_msg(irq, &entry->msg);
+ }
+-#endif
++
++void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq)
++{
++ return default_restore_msi_irqs(dev, irq);
++}
+
+ static void msi_set_enable(struct pci_dev *dev, int enable)
+ {
+@@ -336,7 +362,10 @@
+ int i, nvec;
+ if (!entry->irq)
+ continue;
+- nvec = 1 << entry->msi_attrib.multiple;
++ if (entry->nvec_used)
++ nvec = entry->nvec_used;
++ else
++ nvec = 1 << entry->msi_attrib.multiple;
+ #ifdef CONFIG_GENERIC_HARDIRQS
+ for (i = 0; i < nvec; i++)
+ BUG_ON(irq_has_action(entry->irq + i));
+diff -Nur linux-3.10.30.orig/drivers/pci/probe.c linux-linaro-stable-mx6/drivers/pci/probe.c
+--- linux-3.10.30.orig/drivers/pci/probe.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pci/probe.c 2014-05-15 20:34:01.794041218 +0200
+@@ -634,6 +634,7 @@
+
+ child->parent = parent;
+ child->ops = parent->ops;
++ child->msi = parent->msi;
+ child->sysdata = parent->sysdata;
+ child->bus_flags = parent->bus_flags;
+
+diff -Nur linux-3.10.30.orig/drivers/pinctrl/core.c linux-linaro-stable-mx6/drivers/pinctrl/core.c
+--- linux-3.10.30.orig/drivers/pinctrl/core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pinctrl/core.c 2014-05-15 20:34:01.866041737 +0200
+@@ -280,6 +280,29 @@
+ }
+
+ /**
++ * gpio_to_pin() - GPIO range GPIO number to pin number translation
++ * @range: GPIO range used for the translation
++ * @gpio: gpio pin to translate to a pin number
++ *
++ * Finds the pin number for a given GPIO using the specified GPIO range
++ * as a base for translation. The distinction between linear GPIO ranges
++ * and pin list based GPIO ranges is managed correctly by this function.
++ *
++ * This function assumes the gpio is part of the specified GPIO range, use
++ * only after making sure this is the case (e.g. by calling it on the
++ * result of successful pinctrl_get_device_gpio_range calls)!
++ */
++static inline int gpio_to_pin(struct pinctrl_gpio_range *range,
++ unsigned int gpio)
++{
++ unsigned int offset = gpio - range->base;
++ if (range->pins)
++ return range->pins[offset];
++ else
++ return range->pin_base + offset;
++}
++
++/**
+ * pinctrl_match_gpio_range() - check if a certain GPIO pin is in range
+ * @pctldev: pin controller device to check
+ * @gpio: gpio pin to check taken from the global GPIO pin space
+@@ -444,8 +467,14 @@
+ /* Loop over the ranges */
+ list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+ /* Check if we're in the valid range */
+- if (pin >= range->pin_base &&
+- pin < range->pin_base + range->npins) {
++ if (range->pins) {
++ int a;
++ for (a = 0; a < range->npins; a++) {
++ if (range->pins[a] == pin)
++ return range;
++ }
++ } else if (pin >= range->pin_base &&
++ pin < range->pin_base + range->npins) {
+ mutex_unlock(&pctldev->mutex);
+ return range;
+ }
+@@ -528,7 +557,7 @@
+ }
+
+ /* Convert to the pin controllers number space */
+- pin = gpio - range->base + range->pin_base;
++ pin = gpio_to_pin(range, gpio);
+
+ ret = pinmux_request_gpio(pctldev, range, pin, gpio);
+
+@@ -562,7 +591,7 @@
+ mutex_lock(&pctldev->mutex);
+
+ /* Convert to the pin controllers number space */
+- pin = gpio - range->base + range->pin_base;
++ pin = gpio_to_pin(range, gpio);
+
+ pinmux_free_gpio(pctldev, pin, range);
+
+@@ -589,7 +618,7 @@
+ mutex_lock(&pctldev->mutex);
+
+ /* Convert to the pin controllers number space */
+- pin = gpio - range->base + range->pin_base;
++ pin = gpio_to_pin(range, gpio);
+ ret = pinmux_gpio_direction(pctldev, range, pin, input);
+
+ mutex_unlock(&pctldev->mutex);
+@@ -1204,6 +1233,67 @@
+ }
+ EXPORT_SYMBOL_GPL(pinctrl_force_default);
+
++#ifdef CONFIG_PM
++
++/**
++ * pinctrl_pm_select_default_state() - select default pinctrl state for PM
++ * @dev: device to select default state for
++ */
++int pinctrl_pm_select_default_state(struct device *dev)
++{
++ struct dev_pin_info *pins = dev->pins;
++ int ret;
++
++ if (!pins)
++ return 0;
++ if (IS_ERR(pins->default_state))
++ return 0; /* No default state */
++ ret = pinctrl_select_state(pins->p, pins->default_state);
++ if (ret)
++ dev_err(dev, "failed to activate default pinctrl state\n");
++ return ret;
++}
++
++/**
++ * pinctrl_pm_select_sleep_state() - select sleep pinctrl state for PM
++ * @dev: device to select sleep state for
++ */
++int pinctrl_pm_select_sleep_state(struct device *dev)
++{
++ struct dev_pin_info *pins = dev->pins;
++ int ret;
++
++ if (!pins)
++ return 0;
++ if (IS_ERR(pins->sleep_state))
++ return 0; /* No sleep state */
++ ret = pinctrl_select_state(pins->p, pins->sleep_state);
++ if (ret)
++ dev_err(dev, "failed to activate pinctrl sleep state\n");
++ return ret;
++}
++
++/**
++ * pinctrl_pm_select_idle_state() - select idle pinctrl state for PM
++ * @dev: device to select idle state for
++ */
++int pinctrl_pm_select_idle_state(struct device *dev)
++{
++ struct dev_pin_info *pins = dev->pins;
++ int ret;
++
++ if (!pins)
++ return 0;
++ if (IS_ERR(pins->idle_state))
++ return 0; /* No idle state */
++ ret = pinctrl_select_state(pins->p, pins->idle_state);
++ if (ret)
++ dev_err(dev, "failed to activate pinctrl idle state\n");
++ return ret;
++}
++
++#endif
++
+ #ifdef CONFIG_DEBUG_FS
+
+ static int pinctrl_pins_show(struct seq_file *s, void *what)
+@@ -1296,11 +1386,21 @@
+
+ /* Loop over the ranges */
+ list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+- seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n",
+- range->id, range->name,
+- range->base, (range->base + range->npins - 1),
+- range->pin_base,
+- (range->pin_base + range->npins - 1));
++ if (range->pins) {
++ int a;
++ seq_printf(s, "%u: %s GPIOS [%u - %u] PINS {",
++ range->id, range->name,
++ range->base, (range->base + range->npins - 1));
++ for (a = 0; a < range->npins - 1; a++)
++ seq_printf(s, "%u, ", range->pins[a]);
++ seq_printf(s, "%u}\n", range->pins[a]);
++ }
++ else
++ seq_printf(s, "%u: %s GPIOS [%u - %u] PINS [%u - %u]\n",
++ range->id, range->name,
++ range->base, (range->base + range->npins - 1),
++ range->pin_base,
++ (range->pin_base + range->npins - 1));
+ }
+
+ mutex_unlock(&pctldev->mutex);
+diff -Nur linux-3.10.30.orig/drivers/pinctrl/devicetree.c linux-linaro-stable-mx6/drivers/pinctrl/devicetree.c
+--- linux-3.10.30.orig/drivers/pinctrl/devicetree.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pinctrl/devicetree.c 2014-05-15 20:34:01.870041766 +0200
+@@ -18,6 +18,7 @@
+
+ #include <linux/device.h>
+ #include <linux/of.h>
++#include <linux/of_gpio.h>
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/slab.h>
+
+@@ -172,6 +173,43 @@
+ return dt_remember_or_free_map(p, statename, NULL, map, 1);
+ }
+
++static int dt_gpio_assert_pinctrl(struct pinctrl *p)
++{
++ struct device_node *np = p->dev->of_node;
++ enum of_gpio_flags flags;
++ int gpio;
++ int index = 0;
++ int ret;
++
++ if (!of_find_property(np, "pinctrl-assert-gpios", NULL))
++ return 0; /* Missing the property, so nothing to be done */
++
++ for (;; index++) {
++ gpio = of_get_named_gpio_flags(np, "pinctrl-assert-gpios",
++ index, &flags);
++ if (gpio < 0)
++ break; /* End of the phandle list */
++
++ if (!gpio_is_valid(gpio))
++ return -EINVAL;
++
++ ret = devm_gpio_request_one(p->dev, gpio, GPIOF_OUT_INIT_LOW,
++ NULL);
++ if (ret < 0)
++ return ret;
++
++ if (flags & OF_GPIO_ACTIVE_LOW)
++ continue;
++
++ if (gpio_cansleep(gpio))
++ gpio_set_value_cansleep(gpio, 1);
++ else
++ gpio_set_value(gpio, 1);
++ }
++
++ return 0;
++}
++
+ int pinctrl_dt_to_map(struct pinctrl *p)
+ {
+ struct device_node *np = p->dev->of_node;
+@@ -190,6 +228,12 @@
+ return 0;
+ }
+
++ ret = dt_gpio_assert_pinctrl(p);
++ if (ret) {
++ dev_dbg(p->dev, "failed to assert pinctrl setting: %d\n", ret);
++ return ret;
++ }
++
+ /* We may store pointers to property names within the node */
+ of_node_get(np);
+
+diff -Nur linux-3.10.30.orig/drivers/pinctrl/Kconfig linux-linaro-stable-mx6/drivers/pinctrl/Kconfig
+--- linux-3.10.30.orig/drivers/pinctrl/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pinctrl/Kconfig 2014-05-15 20:34:01.858041679 +0200
+@@ -108,6 +108,14 @@
+ help
+ Say Y here to enable the imx6sl pinctrl driver
+
++config PINCTRL_VF610
++ bool "Freescale Vybrid VF610 pinctrl driver"
++ depends on OF
++ depends on SOC_VF610
++ select PINCTRL_IMX
++ help
++ Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
++
+ config PINCTRL_LANTIQ
+ bool
+ depends on LANTIQ
+diff -Nur linux-3.10.30.orig/drivers/pinctrl/Makefile linux-linaro-stable-mx6/drivers/pinctrl/Makefile
+--- linux-3.10.30.orig/drivers/pinctrl/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pinctrl/Makefile 2014-05-15 20:34:01.858041679 +0200
+@@ -22,6 +22,7 @@
+ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
+ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
+ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
++obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
+ obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
+ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
+ obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
+@@ -45,6 +46,7 @@
+ obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
+ obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
+ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
++obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
+
+ obj-$(CONFIG_PLAT_ORION) += mvebu/
+ obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
+diff -Nur linux-3.10.30.orig/drivers/pinctrl/pinctrl-imx6sl.c linux-linaro-stable-mx6/drivers/pinctrl/pinctrl-imx6sl.c
+--- linux-3.10.30.orig/drivers/pinctrl/pinctrl-imx6sl.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pinctrl/pinctrl-imx6sl.c 2014-05-15 20:34:01.906042026 +0200
+@@ -384,6 +384,10 @@
+ },
+ .probe = imx6sl_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
++#ifdef CONFIG_PM
++ .suspend = imx_pinctrl_suspend,
++ .resume = imx_pinctrl_resume,
++#endif
+ };
+
+ static int __init imx6sl_pinctrl_init(void)
+diff -Nur linux-3.10.30.orig/drivers/pinctrl/pinctrl-imx.c linux-linaro-stable-mx6/drivers/pinctrl/pinctrl-imx.c
+--- linux-3.10.30.orig/drivers/pinctrl/pinctrl-imx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pinctrl/pinctrl-imx.c 2014-05-15 20:34:01.898041967 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Core driver for the imx pin controller
+ *
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+@@ -221,18 +221,56 @@
+ pin_id = pins[i];
+ pin_reg = &info->pin_regs[pin_id];
+
+- if (!pin_reg->mux_reg) {
++ if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
+ dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+- writel(mux[i], ipctl->base + pin_reg->mux_reg);
++ if (info->flags & SHARE_MUX_CONF_REG) {
++ u32 reg;
++ reg = readl(ipctl->base + pin_reg->mux_reg);
++ reg &= ~(0x7 << 20);
++ reg |= (mux[i] << 20);
++ writel(reg, ipctl->base + pin_reg->mux_reg);
++ } else {
++ writel(mux[i], ipctl->base + pin_reg->mux_reg);
++ }
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, mux[i]);
+
+- /* some pins also need select input setting, set it if found */
+- if (input_reg[i]) {
++ /*
++ * If the select input value begins with 0xff, it's a quirky
++ * select input and the value should be interpreted as below.
++ * 31 23 15 7 0
++ * | 0xff | shift | width | select |
++ * It's used to work around the problem that the select
++ * input for some pin is not implemented in the select
++ * input register but in some general purpose register.
++ * We encode the select input value, width and shift of
++ * the bit field into input_val cell of pin function ID
++ * in device tree, and then decode them here for setting
++ * up the select input bits in general purpose register.
++ */
++ if (input_val[i] >> 24 == 0xff) {
++ u32 val = input_val[i];
++ u8 select = val & 0xff;
++ u8 width = (val >> 8) & 0xff;
++ u8 shift = (val >> 16) & 0xff;
++ u32 mask = ((1 << width) - 1) << shift;
++ /*
++ * The input_reg[i] here is actually some IOMUXC general
++ * purpose register, not regular select input register.
++ */
++ val = readl(ipctl->base + input_reg[i]);
++ val &= ~mask;
++ val |= select << shift;
++ writel(val, ipctl->base + input_reg[i]);
++ } else if (input_reg[i]) {
++ /*
++ * Regular select input register can never be at offset
++ * 0, and we only print register value for regular case.
++ */
+ writel(input_val[i], ipctl->base + input_reg[i]);
+ dev_dbg(ipctl->dev,
+ "==>select_input: offset 0x%x val 0x%x\n",
+@@ -287,7 +325,7 @@
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+
+- if (!pin_reg->conf_reg) {
++ if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
+ dev_err(info->dev, "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+@@ -295,6 +333,9 @@
+
+ *config = readl(ipctl->base + pin_reg->conf_reg);
+
++ if (info->flags & SHARE_MUX_CONF_REG)
++ *config &= 0xffff;
++
+ return 0;
+ }
+
+@@ -305,7 +346,7 @@
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+
+- if (!pin_reg->conf_reg) {
++ if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
+ dev_err(info->dev, "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+@@ -314,7 +355,15 @@
+ dev_dbg(ipctl->dev, "pinconf set pin %s\n",
+ info->pins[pin_id].name);
+
+- writel(config, ipctl->base + pin_reg->conf_reg);
++ if (info->flags & SHARE_MUX_CONF_REG) {
++ u32 reg;
++ reg = readl(ipctl->base + pin_reg->conf_reg);
++ reg &= ~0xffff;
++ reg |= config;
++ writel(reg, ipctl->base + pin_reg->conf_reg);
++ } else {
++ writel(config, ipctl->base + pin_reg->conf_reg);
++ }
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
+ pin_reg->conf_reg, config);
+
+@@ -381,19 +430,24 @@
+ * 1 u32 CONFIG, so 24 types in total for each pin.
+ */
+ #define FSL_PIN_SIZE 24
++#define SHARE_FSL_PIN_SIZE 20
+
+ static int imx_pinctrl_parse_groups(struct device_node *np,
+ struct imx_pin_group *grp,
+ struct imx_pinctrl_soc_info *info,
+ u32 index)
+ {
+- int size;
++ int size, pin_size;
+ const __be32 *list;
+ int i;
+ u32 config;
+
+ dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+
++ if (info->flags & SHARE_MUX_CONF_REG)
++ pin_size = SHARE_FSL_PIN_SIZE;
++ else
++ pin_size = FSL_PIN_SIZE;
+ /* Initialise group */
+ grp->name = np->name;
+
+@@ -403,12 +457,12 @@
+ */
+ list = of_get_property(np, "fsl,pins", &size);
+ /* we do not check return since it's safe node passed down */
+- if (!size || size % FSL_PIN_SIZE) {
++ if (!size || size % pin_size) {
+ dev_err(info->dev, "Invalid fsl,pins property\n");
+ return -EINVAL;
+ }
+
+- grp->npins = size / FSL_PIN_SIZE;
++ grp->npins = size / pin_size;
+ grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+ GFP_KERNEL);
+ grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
+@@ -421,10 +475,17 @@
+ GFP_KERNEL);
+ for (i = 0; i < grp->npins; i++) {
+ u32 mux_reg = be32_to_cpu(*list++);
+- u32 conf_reg = be32_to_cpu(*list++);
+- unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+- struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
++ u32 conf_reg;
++ unsigned int pin_id;
++ struct imx_pin_reg *pin_reg;
++
++ if (info->flags & SHARE_MUX_CONF_REG)
++ conf_reg = mux_reg;
++ else
++ conf_reg = be32_to_cpu(*list++);
+
++ pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
++ pin_reg = &info->pin_regs[pin_id];
+ grp->pins[i] = pin_id;
+ pin_reg->mux_reg = mux_reg;
+ pin_reg->conf_reg = conf_reg;
+@@ -588,3 +649,25 @@
+
+ return 0;
+ }
++
++#ifdef CONFIG_PM
++int imx_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
++
++ if (!ipctl)
++ return -EINVAL;
++
++ return pinctrl_force_sleep(ipctl->pctl);
++}
++
++int imx_pinctrl_resume(struct platform_device *pdev)
++{
++ struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
++
++ if (!ipctl)
++ return -EINVAL;
++
++ return pinctrl_force_default(ipctl->pctl);
++}
++#endif
+diff -Nur linux-3.10.30.orig/drivers/pinctrl/pinctrl-imx.h linux-linaro-stable-mx6/drivers/pinctrl/pinctrl-imx.h
+--- linux-3.10.30.orig/drivers/pinctrl/pinctrl-imx.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pinctrl/pinctrl-imx.h 2014-05-15 20:34:01.898041967 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * IMX pinmux core definitions
+ *
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+@@ -74,8 +74,12 @@
+ unsigned int ngroups;
+ struct imx_pmx_func *functions;
+ unsigned int nfunctions;
++ unsigned int flags;
+ };
+
++#define ZERO_OFFSET_VALID 0x1
++#define SHARE_MUX_CONF_REG 0x2
++
+ #define NO_MUX 0x0
+ #define NO_PAD 0x0
+
+@@ -88,4 +92,8 @@
+ int imx_pinctrl_probe(struct platform_device *pdev,
+ struct imx_pinctrl_soc_info *info);
+ int imx_pinctrl_remove(struct platform_device *pdev);
++#ifdef CONFIG_PM
++int imx_pinctrl_suspend(struct platform_device *pdev, pm_message_t state);
++int imx_pinctrl_resume(struct platform_device *pdev);
++#endif
+ #endif /* __DRIVERS_PINCTRL_IMX_H */
+diff -Nur linux-3.10.30.orig/drivers/pinctrl/pinctrl-vf610.c linux-linaro-stable-mx6/drivers/pinctrl/pinctrl-vf610.c
+--- linux-3.10.30.orig/drivers/pinctrl/pinctrl-vf610.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pinctrl/pinctrl-vf610.c 2014-05-15 20:34:01.954042371 +0200
+@@ -0,0 +1,338 @@
++/*
++ * VF610 pinctrl driver based on imx pinmux and pinconf core
++ *
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/pinctrl.h>
++
++#include "pinctrl-imx.h"
++
++enum vf610_pads {
++ VF610_PAD_PTA6 = 0,
++ VF610_PAD_PTA8 = 1,
++ VF610_PAD_PTA9 = 2,
++ VF610_PAD_PTA10 = 3,
++ VF610_PAD_PTA11 = 4,
++ VF610_PAD_PTA12 = 5,
++ VF610_PAD_PTA16 = 6,
++ VF610_PAD_PTA17 = 7,
++ VF610_PAD_PTA18 = 8,
++ VF610_PAD_PTA19 = 9,
++ VF610_PAD_PTA20 = 10,
++ VF610_PAD_PTA21 = 11,
++ VF610_PAD_PTA22 = 12,
++ VF610_PAD_PTA23 = 13,
++ VF610_PAD_PTA24 = 14,
++ VF610_PAD_PTA25 = 15,
++ VF610_PAD_PTA26 = 16,
++ VF610_PAD_PTA27 = 17,
++ VF610_PAD_PTA28 = 18,
++ VF610_PAD_PTA29 = 19,
++ VF610_PAD_PTA30 = 20,
++ VF610_PAD_PTA31 = 21,
++ VF610_PAD_PTB0 = 22,
++ VF610_PAD_PTB1 = 23,
++ VF610_PAD_PTB2 = 24,
++ VF610_PAD_PTB3 = 25,
++ VF610_PAD_PTB4 = 26,
++ VF610_PAD_PTB5 = 27,
++ VF610_PAD_PTB6 = 28,
++ VF610_PAD_PTB7 = 29,
++ VF610_PAD_PTB8 = 30,
++ VF610_PAD_PTB9 = 31,
++ VF610_PAD_PTB10 = 32,
++ VF610_PAD_PTB11 = 33,
++ VF610_PAD_PTB12 = 34,
++ VF610_PAD_PTB13 = 35,
++ VF610_PAD_PTB14 = 36,
++ VF610_PAD_PTB15 = 37,
++ VF610_PAD_PTB16 = 38,
++ VF610_PAD_PTB17 = 39,
++ VF610_PAD_PTB18 = 40,
++ VF610_PAD_PTB19 = 41,
++ VF610_PAD_PTB20 = 42,
++ VF610_PAD_PTB21 = 43,
++ VF610_PAD_PTB22 = 44,
++ VF610_PAD_PTC0 = 45,
++ VF610_PAD_PTC1 = 46,
++ VF610_PAD_PTC2 = 47,
++ VF610_PAD_PTC3 = 48,
++ VF610_PAD_PTC4 = 49,
++ VF610_PAD_PTC5 = 50,
++ VF610_PAD_PTC6 = 51,
++ VF610_PAD_PTC7 = 52,
++ VF610_PAD_PTC8 = 53,
++ VF610_PAD_PTC9 = 54,
++ VF610_PAD_PTC10 = 55,
++ VF610_PAD_PTC11 = 56,
++ VF610_PAD_PTC12 = 57,
++ VF610_PAD_PTC13 = 58,
++ VF610_PAD_PTC14 = 59,
++ VF610_PAD_PTC15 = 60,
++ VF610_PAD_PTC16 = 61,
++ VF610_PAD_PTC17 = 62,
++ VF610_PAD_PTD31 = 63,
++ VF610_PAD_PTD30 = 64,
++ VF610_PAD_PTD29 = 65,
++ VF610_PAD_PTD28 = 66,
++ VF610_PAD_PTD27 = 67,
++ VF610_PAD_PTD26 = 68,
++ VF610_PAD_PTD25 = 69,
++ VF610_PAD_PTD24 = 70,
++ VF610_PAD_PTD23 = 71,
++ VF610_PAD_PTD22 = 72,
++ VF610_PAD_PTD21 = 73,
++ VF610_PAD_PTD20 = 74,
++ VF610_PAD_PTD19 = 75,
++ VF610_PAD_PTD18 = 76,
++ VF610_PAD_PTD17 = 77,
++ VF610_PAD_PTD16 = 78,
++ VF610_PAD_PTD0 = 79,
++ VF610_PAD_PTD1 = 80,
++ VF610_PAD_PTD2 = 81,
++ VF610_PAD_PTD3 = 82,
++ VF610_PAD_PTD4 = 83,
++ VF610_PAD_PTD5 = 84,
++ VF610_PAD_PTD6 = 85,
++ VF610_PAD_PTD7 = 86,
++ VF610_PAD_PTD8 = 87,
++ VF610_PAD_PTD9 = 88,
++ VF610_PAD_PTD10 = 89,
++ VF610_PAD_PTD11 = 90,
++ VF610_PAD_PTD12 = 91,
++ VF610_PAD_PTD13 = 92,
++ VF610_PAD_PTB23 = 93,
++ VF610_PAD_PTB24 = 94,
++ VF610_PAD_PTB25 = 95,
++ VF610_PAD_PTB26 = 96,
++ VF610_PAD_PTB27 = 97,
++ VF610_PAD_PTB28 = 98,
++ VF610_PAD_PTC26 = 99,
++ VF610_PAD_PTC27 = 100,
++ VF610_PAD_PTC28 = 101,
++ VF610_PAD_PTC29 = 102,
++ VF610_PAD_PTC30 = 103,
++ VF610_PAD_PTC31 = 104,
++ VF610_PAD_PTE0 = 105,
++ VF610_PAD_PTE1 = 106,
++ VF610_PAD_PTE2 = 107,
++ VF610_PAD_PTE3 = 108,
++ VF610_PAD_PTE4 = 109,
++ VF610_PAD_PTE5 = 110,
++ VF610_PAD_PTE6 = 111,
++ VF610_PAD_PTE7 = 112,
++ VF610_PAD_PTE8 = 113,
++ VF610_PAD_PTE9 = 114,
++ VF610_PAD_PTE10 = 115,
++ VF610_PAD_PTE11 = 116,
++ VF610_PAD_PTE12 = 117,
++ VF610_PAD_PTE13 = 118,
++ VF610_PAD_PTE14 = 119,
++ VF610_PAD_PTE15 = 120,
++ VF610_PAD_PTE16 = 121,
++ VF610_PAD_PTE17 = 122,
++ VF610_PAD_PTE18 = 123,
++ VF610_PAD_PTE19 = 124,
++ VF610_PAD_PTE20 = 125,
++ VF610_PAD_PTE21 = 126,
++ VF610_PAD_PTE22 = 127,
++ VF610_PAD_PTE23 = 128,
++ VF610_PAD_PTE24 = 129,
++ VF610_PAD_PTE25 = 130,
++ VF610_PAD_PTE26 = 131,
++ VF610_PAD_PTE27 = 132,
++ VF610_PAD_PTE28 = 133,
++ VF610_PAD_PTA7 = 134,
++};
++
++/* Pad names for the pinmux subsystem */
++static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
++ IMX_PINCTRL_PIN(VF610_PAD_PTA6),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA8),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA9),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA10),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA11),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA12),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA16),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA17),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA18),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA19),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA20),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA21),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA22),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA23),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA24),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA25),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA26),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA27),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA28),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA29),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA30),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA31),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB0),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB1),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB2),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB3),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB4),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB5),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB6),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB7),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB8),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB9),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB10),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB11),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB12),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB13),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB14),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB15),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB16),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB17),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB18),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB19),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB20),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB21),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB22),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC0),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC1),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC2),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC3),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC4),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC5),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC6),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC7),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC8),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC9),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC10),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC11),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC12),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC13),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC14),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC15),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC16),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC17),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD31),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD30),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD29),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD28),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD27),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD26),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD25),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD24),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD23),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD22),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD21),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD20),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD19),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD18),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD17),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD16),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD0),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD1),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD2),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD3),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD4),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD5),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD6),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD7),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD8),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD9),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD10),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD11),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD12),
++ IMX_PINCTRL_PIN(VF610_PAD_PTD13),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB23),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB24),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB25),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB26),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB27),
++ IMX_PINCTRL_PIN(VF610_PAD_PTB28),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC26),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC27),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC28),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC29),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC30),
++ IMX_PINCTRL_PIN(VF610_PAD_PTC31),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE0),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE1),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE2),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE3),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE4),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE5),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE6),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE7),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE8),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE9),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE10),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE11),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE12),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE13),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE14),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE15),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE16),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE17),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE18),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE19),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE20),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE21),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE22),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE23),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE24),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE25),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE26),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE27),
++ IMX_PINCTRL_PIN(VF610_PAD_PTE28),
++ IMX_PINCTRL_PIN(VF610_PAD_PTA7),
++};
++
++static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
++ .pins = vf610_pinctrl_pads,
++ .npins = ARRAY_SIZE(vf610_pinctrl_pads),
++ .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
++};
++
++static struct of_device_id vf610_pinctrl_of_match[] = {
++ { .compatible = "fsl,vf610-iomuxc", },
++ { /* sentinel */ }
++};
++
++static int vf610_pinctrl_probe(struct platform_device *pdev)
++{
++ return imx_pinctrl_probe(pdev, &vf610_pinctrl_info);
++}
++
++static struct platform_driver vf610_pinctrl_driver = {
++ .driver = {
++ .name = "vf610-pinctrl",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(vf610_pinctrl_of_match),
++ },
++ .probe = vf610_pinctrl_probe,
++ .remove = imx_pinctrl_remove,
++};
++
++static int __init vf610_pinctrl_init(void)
++{
++ return platform_driver_register(&vf610_pinctrl_driver);
++}
++arch_initcall(vf610_pinctrl_init);
++
++static void __exit vf610_pinctrl_exit(void)
++{
++ platform_driver_unregister(&vf610_pinctrl_driver);
++}
++module_exit(vf610_pinctrl_exit);
++
++MODULE_DESCRIPTION("Freescale VF610 pinctrl driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/power/imx6_usb_charger.c linux-linaro-stable-mx6/drivers/power/imx6_usb_charger.c
+--- linux-3.10.30.orig/drivers/power/imx6_usb_charger.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/power/imx6_usb_charger.c 2014-05-15 20:34:02.266044619 +0200
+@@ -0,0 +1,294 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/power/imx6_usb_charger.h>
++#include <linux/regmap.h>
++
++#define HW_ANADIG_REG_3P0_SET (0x00000124)
++#define HW_ANADIG_REG_3P0_CLR (0x00000128)
++#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004
++#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001
++
++#define HW_ANADIG_USB1_CHRG_DETECT_SET (0x000001b4)
++#define HW_ANADIG_USB1_CHRG_DETECT_CLR (0x000001b8)
++
++#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000
++#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000
++#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000
++
++#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001c0)
++
++#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008
++
++#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001d0)
++
++#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004
++#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
++#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001
++
++static char *imx6_usb_charger_supplied_to[] = {
++ "imx6_usb_charger",
++};
++
++static enum power_supply_property imx6_usb_charger_power_props[] = {
++ POWER_SUPPLY_PROP_PRESENT, /* Charger detected */
++ POWER_SUPPLY_PROP_ONLINE, /* VBUS online */
++ POWER_SUPPLY_PROP_CURRENT_MAX, /* Maximum current in mA */
++};
++
++static int imx6_usb_charger_get_property(struct power_supply *psy,
++ enum power_supply_property psp,
++ union power_supply_propval *val)
++{
++ struct usb_charger *charger =
++ container_of(psy, struct usb_charger, psy);
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_PRESENT:
++ val->intval = charger->present;
++ break;
++ case POWER_SUPPLY_PROP_ONLINE:
++ val->intval = charger->online;
++ break;
++ case POWER_SUPPLY_PROP_CURRENT_MAX:
++ val->intval = charger->max_current;
++ break;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static void disable_charger_detector(struct regmap *regmap)
++{
++ regmap_write(regmap, HW_ANADIG_USB1_CHRG_DETECT_SET,
++ BM_ANADIG_USB1_CHRG_DETECT_EN_B |
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
++}
++
++static void disable_current_limiter(struct regmap *regmap)
++{
++ /* Disable the vdd3p0 current limiter */
++ regmap_write(regmap, HW_ANADIG_REG_3P0_CLR,
++ BM_ANADIG_REG_3P0_ENABLE_ILIMIT);
++}
++
++/* Return value if the charger is present */
++static int imx6_usb_charger_detect(struct usb_charger *charger)
++{
++ struct regmap *regmap = charger->anatop;
++ u32 val;
++ int i, data_pin_contact_count = 0;
++
++ /* Enable the vdd3p0 curret limiter */
++ regmap_write(regmap, HW_ANADIG_REG_3P0_SET,
++ BM_ANADIG_REG_3P0_ENABLE_LINREG |
++ BM_ANADIG_REG_3P0_ENABLE_ILIMIT);
++
++ /* check if vbus is valid */
++ regmap_read(regmap, HW_ANADIG_USB1_VBUS_DET_STAT, &val);
++ if (!(val & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)) {
++ dev_err(charger->dev, "vbus is error\n");
++ disable_current_limiter(regmap);
++ return -EINVAL;
++ }
++
++ /* Enable charger detector */
++ regmap_write(regmap, HW_ANADIG_USB1_CHRG_DETECT_CLR,
++ BM_ANADIG_USB1_CHRG_DETECT_EN_B);
++ /*
++ * - Do not check whether a charger is connected to the USB port
++ * - Check whether the USB plug has been in contact with each other
++ */
++ regmap_write(regmap, HW_ANADIG_USB1_CHRG_DETECT_SET,
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT |
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
++
++ /* Check if plug is connected */
++ for (i = 0; i < 100; i = i + 1) {
++ regmap_read(regmap, HW_ANADIG_USB1_CHRG_DET_STAT, &val);
++ if (val & BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT) {
++ if (data_pin_contact_count++ > 5)
++ /* Data pin makes contact */
++ break;
++ } else {
++ msleep(20);
++ }
++ }
++
++ if (i == 100) {
++ dev_err(charger->dev,
++ "VBUS is coming from a dedicated power supply.\n");
++ disable_current_limiter(regmap);
++ disable_charger_detector(regmap);
++ return -ENXIO;
++ }
++
++ /*
++ * - Do check whether a charger is connected to the USB port
++ * - Do not Check whether the USB plug has been in contact with
++ * each other
++ */
++ regmap_write(regmap, HW_ANADIG_USB1_CHRG_DETECT_CLR,
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT |
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
++ msleep(45);
++
++ /* Check if it is a charger */
++ regmap_read(regmap, HW_ANADIG_USB1_CHRG_DET_STAT, &val);
++ if (!(val & BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) {
++ dev_dbg(charger->dev, "It is a stardard downstream port\n");
++ charger->psy.type = POWER_SUPPLY_TYPE_USB;
++ charger->max_current = 500;
++ disable_charger_detector(regmap);
++ } else {
++ /* It is a charger */
++ disable_charger_detector(regmap);
++ msleep(45);
++ }
++
++ disable_current_limiter(regmap);
++
++ return 0;
++}
++
++/*
++ * imx6_usb_vbus_connect - inform about VBUS connection
++ * @charger: the usb charger
++ *
++ * Inform the charger VBUS is connected, vbus detect supplier should call it.
++ * Besides, the USB device controller is expected to keep the dataline
++ * pullups disabled.
++ */
++int imx6_usb_vbus_connect(struct usb_charger *charger)
++{
++ int ret;
++
++ charger->online = 1;
++
++ mutex_lock(&charger->lock);
++
++ /* Start the 1st period charger detection. */
++ ret = imx6_usb_charger_detect(charger);
++ if (ret)
++ dev_err(charger->dev,
++ "Error occurs during detection: %d\n",
++ ret);
++ else
++ charger->present = 1;
++
++ mutex_unlock(&charger->lock);
++
++ return ret;
++}
++EXPORT_SYMBOL(imx6_usb_vbus_connect);
++
++/*
++ * It must be called after dp is pulled up (from USB controller driver),
++ * That is used to differentiate DCP and CDP
++ */
++int imx6_usb_charger_detect_post(struct usb_charger *charger)
++{
++ struct regmap *regmap = charger->anatop;
++ int val;
++
++ mutex_lock(&charger->lock);
++
++ msleep(40);
++
++ regmap_read(regmap, HW_ANADIG_USB1_CHRG_DET_STAT, &val);
++ if (val & BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE) {
++ dev_dbg(charger->dev, "It is a dedicate charging port\n");
++ charger->psy.type = POWER_SUPPLY_TYPE_USB_DCP;
++ charger->max_current = 1500;
++ } else {
++ dev_dbg(charger->dev, "It is a charging downstream port\n");
++ charger->psy.type = POWER_SUPPLY_TYPE_USB_CDP;
++ charger->max_current = 900;
++ }
++
++ power_supply_changed(&charger->psy);
++
++ mutex_unlock(&charger->lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(imx6_usb_charger_detect_post);
++
++/*
++ * imx6_usb_vbus_disconnect - inform about VBUS disconnection
++ * @charger: the usb charger
++ *
++ * Inform the charger that VBUS is disconnected. The charging will be
++ * stopped and the charger properties cleared.
++ */
++int imx6_usb_vbus_disconnect(struct usb_charger *charger)
++{
++ charger->online = 0;
++ charger->present = 0;
++ charger->max_current = 0;
++ charger->psy.type = POWER_SUPPLY_TYPE_MAINS;
++
++ power_supply_changed(&charger->psy);
++
++ return 0;
++}
++EXPORT_SYMBOL(imx6_usb_vbus_disconnect);
++
++/*
++ * imx6_usb_create_charger - create a USB charger
++ * @charger: the charger to be initialized
++ * @name: name for the power supply
++
++ * Registers a power supply for the charger. The USB Controller
++ * driver will call this after filling struct usb_charger.
++ */
++int imx6_usb_create_charger(struct usb_charger *charger,
++ const char *name)
++{
++ struct power_supply *psy = &charger->psy;
++
++ if (!charger->dev)
++ return -EINVAL;
++
++ if (name)
++ psy->name = name;
++ else
++ psy->name = "imx6_usb_charger";
++
++ charger->bc = BATTERY_CHARGING_SPEC_1_2;
++ mutex_init(&charger->lock);
++
++ psy->type = POWER_SUPPLY_TYPE_MAINS;
++ psy->properties = imx6_usb_charger_power_props;
++ psy->num_properties = ARRAY_SIZE(imx6_usb_charger_power_props);
++ psy->get_property = imx6_usb_charger_get_property;
++ psy->supplied_to = imx6_usb_charger_supplied_to;
++ psy->num_supplicants = sizeof(imx6_usb_charger_supplied_to)
++ / sizeof(char *);
++
++ return power_supply_register(charger->dev, psy);
++}
++EXPORT_SYMBOL(imx6_usb_create_charger);
++
++/*
++ * imx6_usb_remove_charger - remove a USB charger
++ * @charger: the charger to be removed
++ *
++ * Unregister the chargers power supply.
++ */
++void imx6_usb_remove_charger(struct usb_charger *charger)
++{
++ power_supply_unregister(&charger->psy);
++}
++EXPORT_SYMBOL(imx6_usb_remove_charger);
+diff -Nur linux-3.10.30.orig/drivers/power/Kconfig linux-linaro-stable-mx6/drivers/power/Kconfig
+--- linux-3.10.30.orig/drivers/power/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/power/Kconfig 2014-05-15 20:34:02.258044562 +0200
+@@ -269,6 +269,14 @@
+ pins based on the status of charger connections with interrupt
+ handlers.
+
++config SABRESD_MAX8903
++ tristate "Sabresd Board Battery DC-DC Charger for USB and Adapter Power"
++ depends on GENERIC_HARDIRQS && TOUCHSCREEN_MAX11801
++ help
++ Say Y to enable support for the MAX8903 DC-DC charger and sysfs on
++ sabresd board.The driver supports controlling charger and battery
++ based on the status of charger connections with interrupt handlers.
++
+ config CHARGER_TWL4030
+ tristate "OMAP TWL4030 BCI charger driver"
+ depends on TWL4030_CORE
+@@ -362,6 +370,12 @@
+ Say Y to enable support for the battery and AC power in the
+ Goldfish emulator.
+
++config IMX6_USB_CHARGER
++ bool "Freescale imx6 USB Charger"
++ depends on SOC_IMX6Q || SOC_IMX6SL
++ help
++ Say Y to enable Freescale imx6 USB Charger Detect.
++
+ source "drivers/power/reset/Kconfig"
+
+ endif # POWER_SUPPLY
+diff -Nur linux-3.10.30.orig/drivers/power/Makefile linux-linaro-stable-mx6/drivers/power/Makefile
+--- linux-3.10.30.orig/drivers/power/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/power/Makefile 2014-05-15 20:34:02.258044562 +0200
+@@ -42,6 +42,7 @@
+ obj-$(CONFIG_AB8500_BM) += ab8500_bmdata.o ab8500_charger.o ab8500_fg.o ab8500_btemp.o abx500_chargalg.o pm2301_charger.o
+ obj-$(CONFIG_CHARGER_ISP1704) += isp1704_charger.o
+ obj-$(CONFIG_CHARGER_MAX8903) += max8903_charger.o
++obj-$(CONFIG_SABRESD_MAX8903) += sabresd_battery.o
+ obj-$(CONFIG_CHARGER_TWL4030) += twl4030_charger.o
+ obj-$(CONFIG_CHARGER_LP8727) += lp8727_charger.o
+ obj-$(CONFIG_CHARGER_LP8788) += lp8788-charger.o
+@@ -54,3 +55,4 @@
+ obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o
+ obj-$(CONFIG_CHARGER_TPS65090) += tps65090-charger.o
+ obj-$(CONFIG_POWER_RESET) += reset/
++obj-$(CONFIG_IMX6_USB_CHARGER) += imx6_usb_charger.o
+diff -Nur linux-3.10.30.orig/drivers/power/reset/Kconfig linux-linaro-stable-mx6/drivers/power/reset/Kconfig
+--- linux-3.10.30.orig/drivers/power/reset/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/power/reset/Kconfig 2014-05-15 20:34:02.270044648 +0200
+@@ -32,7 +32,8 @@
+ user presses a key. u-boot then boots into Linux.
+
+ config POWER_RESET_VEXPRESS
+- bool
++ bool "ARM Versatile Express power-off and reset driver"
++ depends on ARM || ARM64
+ depends on POWER_RESET
+ help
+ Power off and reset support for the ARM Ltd. Versatile
+diff -Nur linux-3.10.30.orig/drivers/power/sabresd_battery.c linux-linaro-stable-mx6/drivers/power/sabresd_battery.c
+--- linux-3.10.30.orig/drivers/power/sabresd_battery.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/power/sabresd_battery.c 2014-05-15 20:34:02.270044648 +0200
+@@ -0,0 +1,998 @@
++/*
++ * sabresd_battery.c - Maxim 8903 USB/Adapter Charger Driver
++ *
++ * Copyright (C) 2011 Samsung Electronics
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ * Based on max8903_charger.c
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/power_supply.h>
++#include <linux/platform_device.h>
++#include <linux/power/sabresd_battery.h>
++#include <linux/slab.h>
++
++#define BATTERY_UPDATE_INTERVAL 5 /*seconds*/
++#define LOW_VOLT_THRESHOLD 2800000
++#define HIGH_VOLT_THRESHOLD 4200000
++#define ADC_SAMPLE_COUNT 6
++
++struct max8903_data {
++ struct max8903_pdata *pdata;
++ struct device *dev;
++ struct power_supply psy;
++ struct power_supply usb;
++ bool fault;
++ bool usb_in;
++ bool ta_in;
++ bool chg_state;
++ struct delayed_work work;
++ unsigned int interval;
++ unsigned short thermal_raw;
++ int voltage_uV;
++ int current_uA;
++ int battery_status;
++ int charger_online;
++ int charger_voltage_uV;
++ int real_capacity;
++ int percent;
++ int old_percent;
++ int usb_charger_online;
++ int first_delay_count;
++ struct power_supply bat;
++ struct power_supply detect_usb;
++};
++
++typedef struct {
++ u32 voltage;
++ u32 percent;
++} battery_capacity , *pbattery_capacity;
++
++static int offset_discharger;
++static int offset_charger;
++static int offset_usb_charger;
++
++static battery_capacity chargingTable[] = {
++ {4050, 99},
++ {4040, 98},
++ {4020, 97},
++ {4010, 96},
++ {3990, 95},
++ {3980, 94},
++ {3970, 93},
++ {3960, 92},
++ {3950, 91},
++ {3940, 90},
++ {3930, 85},
++ {3920, 81},
++ {3910, 77},
++ {3900, 73},
++ {3890, 70},
++ {3860, 65},
++ {3830, 60},
++ {3780, 55},
++ {3760, 50},
++ {3740, 45},
++ {3720, 40},
++ {3700, 35},
++ {3680, 30},
++ {3660, 25},
++ {3640, 20},
++ {3620, 17},
++ {3600, 14},
++ {3580, 13},
++ {3560, 12},
++ {3540, 11},
++ {3520, 10},
++ {3500, 9},
++ {3480, 8},
++ {3460, 7},
++ {3440, 6},
++ {3430, 5},
++ {3420, 4},
++ {3020, 0},
++};
++
++static battery_capacity dischargingTable[] = {
++ {4050, 100},
++ {4035, 99},
++ {4020, 98},
++ {4010, 97},
++ {4000, 96},
++ {3990, 96},
++ {3980, 95},
++ {3970, 92},
++ {3960, 91},
++ {3950, 90},
++ {3940, 88},
++ {3930, 86},
++ {3920, 84},
++ {3910, 82},
++ {3900, 80},
++ {3890, 74},
++ {3860, 69},
++ {3830, 64},
++ {3780, 59},
++ {3760, 54},
++ {3740, 49},
++ {3720, 44},
++ {3700, 39},
++ {3680, 34},
++ {3660, 29},
++ {3640, 24},
++ {3620, 19},
++ {3600, 14},
++ {3580, 13},
++ {3560, 12},
++ {3540, 11},
++ {3520, 10},
++ {3500, 9},
++ {3480, 8},
++ {3460, 7},
++ {3440, 6},
++ {3430, 5},
++ {3420, 4},
++ {3020, 0},
++};
++
++u32 calibrate_battery_capability_percent(struct max8903_data *data)
++{
++ u8 i;
++ pbattery_capacity pTable;
++ u32 tableSize;
++
++ if (data->battery_status == POWER_SUPPLY_STATUS_DISCHARGING) {
++ pTable = dischargingTable;
++ tableSize = sizeof(dischargingTable)/
++ sizeof(dischargingTable[0]);
++ } else {
++ pTable = chargingTable;
++ tableSize = sizeof(chargingTable)/
++ sizeof(chargingTable[0]);
++ }
++ for (i = 0; i < tableSize; i++) {
++ if (data->voltage_uV >= pTable[i].voltage)
++ return pTable[i].percent;
++ }
++
++ return 0;
++}
++
++static enum power_supply_property max8903_charger_props[] = {
++ POWER_SUPPLY_PROP_ONLINE,
++};
++
++static enum power_supply_property max8903_battery_props[] = {
++ POWER_SUPPLY_PROP_VOLTAGE_NOW,
++ POWER_SUPPLY_PROP_STATUS,
++ POWER_SUPPLY_PROP_PRESENT,
++ POWER_SUPPLY_PROP_CAPACITY,
++ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
++ POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
++ POWER_SUPPLY_PROP_HEALTH,
++ POWER_SUPPLY_PROP_CAPACITY_LEVEL,
++};
++
++extern u32 max11801_read_adc(void);
++
++static void max8903_charger_update_status(struct max8903_data *data)
++{
++ if (data->ta_in) {
++ data->charger_online = 1;
++ } else if (data->usb_in) {
++ data->usb_charger_online = 1;
++ } else {
++ data->charger_online = 0;
++ data->usb_charger_online = 0;
++ }
++
++ if (!data->charger_online && !data->usb_charger_online) {
++ data->battery_status = POWER_SUPPLY_STATUS_DISCHARGING;
++ } else if (gpio_get_value(data->pdata->chg) == 0) {
++ data->battery_status = POWER_SUPPLY_STATUS_CHARGING;
++ } else if ((data->ta_in || data->usb_in) &&
++ gpio_get_value(data->pdata->chg) > 0) {
++ if (!data->pdata->feature_flag) {
++ if (data->percent >= 99)
++ data->battery_status = POWER_SUPPLY_STATUS_FULL;
++ else
++ data->battery_status =
++ POWER_SUPPLY_STATUS_NOT_CHARGING;
++ } else {
++ data->battery_status = POWER_SUPPLY_STATUS_FULL;
++ }
++ }
++}
++
++u32 calibration_voltage(struct max8903_data *data)
++{
++ u32 voltage_data = 0;
++ int i;
++ int offset;
++
++ if (!data->charger_online && !data->usb_charger_online)
++ offset = offset_discharger;
++ else if (data->usb_charger_online)
++ offset = offset_usb_charger;
++ else if (data->charger_online)
++ offset = offset_charger;
++
++ /* simple average */
++ for (i = 0; i < ADC_SAMPLE_COUNT; i++)
++ voltage_data += max11801_read_adc()-offset;
++ voltage_data = voltage_data / ADC_SAMPLE_COUNT;
++ dev_dbg(data->dev, "volt: %d\n", voltage_data);
++
++ return voltage_data;
++}
++
++static void max8903_battery_update_status(struct max8903_data *data)
++{
++ if (!data->pdata->feature_flag) {
++ data->voltage_uV = calibration_voltage(data);
++ data->percent = calibrate_battery_capability_percent(data);
++ if (data->percent != data->old_percent) {
++ data->old_percent = data->percent;
++ power_supply_changed(&data->bat);
++ }
++ /*
++ * because boot time gap between led framwork and charger
++ * framwork,when system boots with charger attatched,
++ * charger led framwork loses the first charger online event,
++ * add once extra power_supply_changed can fix this issure
++ */
++ if (data->first_delay_count < 200) {
++ data->first_delay_count = data->first_delay_count + 1;
++ power_supply_changed(&data->bat);
++ }
++ }
++}
++
++static int max8903_battery_get_property(struct power_supply *bat,
++ enum power_supply_property psp,
++ union power_supply_propval *val)
++{
++ struct max8903_data *di = container_of(bat, struct max8903_data, bat);
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_STATUS:
++ val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
++ if (gpio_get_value(di->pdata->chg) == 0) {
++ di->battery_status = POWER_SUPPLY_STATUS_CHARGING;
++ } else if ((di->ta_in || di->usb_in) &&
++ gpio_get_value(di->pdata->chg) > 0) {
++ if (!di->pdata->feature_flag) {
++ if (di->percent >= 99)
++ di->battery_status =
++ POWER_SUPPLY_STATUS_FULL;
++ else
++ di->battery_status =
++ POWER_SUPPLY_STATUS_NOT_CHARGING;
++ } else {
++ di->battery_status = POWER_SUPPLY_STATUS_FULL;
++ }
++ }
++ val->intval = di->battery_status;
++ return 0;
++ default:
++ break;
++ }
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_VOLTAGE_NOW:
++ val->intval = di->voltage_uV;
++ break;
++ case POWER_SUPPLY_PROP_CHARGE_NOW:
++ val->intval = 0;
++ break;
++ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
++ val->intval = HIGH_VOLT_THRESHOLD;
++ break;
++ case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
++ val->intval = LOW_VOLT_THRESHOLD;
++ break;
++ case POWER_SUPPLY_PROP_PRESENT:
++ val->intval = 1;
++ break;
++ case POWER_SUPPLY_PROP_CAPACITY:
++ val->intval = di->percent < 0 ? 0 :
++ (di->percent > 100 ? 100 : di->percent);
++ break;
++ case POWER_SUPPLY_PROP_HEALTH:
++ val->intval = POWER_SUPPLY_HEALTH_GOOD;
++ if (di->fault)
++ val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE;
++ break;
++ case POWER_SUPPLY_PROP_CAPACITY_LEVEL:
++ if (di->battery_status == POWER_SUPPLY_STATUS_FULL)
++ val->intval = POWER_SUPPLY_CAPACITY_LEVEL_FULL;
++ else if (di->percent <= 15)
++ val->intval = POWER_SUPPLY_CAPACITY_LEVEL_LOW;
++ else
++ val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int max8903_get_property(struct power_supply *psy,
++ enum power_supply_property psp,
++ union power_supply_propval *val)
++{
++ struct max8903_data *data = container_of(psy,
++ struct max8903_data, psy);
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_ONLINE:
++ val->intval = 0;
++ if (data->ta_in)
++ val->intval = 1;
++ data->charger_online = val->intval;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int max8903_get_usb_property(struct power_supply *usb,
++ enum power_supply_property psp,
++ union power_supply_propval *val)
++{
++ struct max8903_data *data = container_of(usb,
++ struct max8903_data, usb);
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_ONLINE:
++ val->intval = 0;
++ if (data->usb_in)
++ val->intval = 1;
++ data->usb_charger_online = val->intval;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static irqreturn_t max8903_dcin(int irq, void *_data)
++{
++ struct max8903_data *data = _data;
++ struct max8903_pdata *pdata = data->pdata;
++ bool ta_in = false;
++
++ if (pdata->dok)
++ ta_in = gpio_get_value(pdata->dok) ? false : true;
++
++ if (ta_in == data->ta_in)
++ return IRQ_HANDLED;
++
++ data->ta_in = ta_in;
++ dev_info(data->dev, "TA(DC-IN) Charger %s.\n", ta_in ?
++ "Connected" : "Disconnected");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->psy);
++ power_supply_changed(&data->bat);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t max8903_usbin(int irq, void *_data)
++{
++ struct max8903_data *data = _data;
++ struct max8903_pdata *pdata = data->pdata;
++ bool usb_in = false;
++
++ if (pdata->uok)
++ usb_in = gpio_get_value(pdata->uok) ? false : true;
++ if (usb_in == data->usb_in)
++ return IRQ_HANDLED;
++ data->usb_in = usb_in;
++ dev_info(data->dev, "USB Charger %s.\n", usb_in ?
++ "Connected" : "Disconnected");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->bat);
++ power_supply_changed(&data->usb);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t max8903_fault(int irq, void *_data)
++{
++ struct max8903_data *data = _data;
++ struct max8903_pdata *pdata = data->pdata;
++ bool fault;
++
++ fault = gpio_get_value(pdata->flt) ? false : true;
++
++ if (fault == data->fault)
++ return IRQ_HANDLED;
++ data->fault = fault;
++
++ if (fault)
++ dev_err(data->dev, "Charger suffers a fault and stops.\n");
++ else
++ dev_err(data->dev, "Charger recovered from a fault.\n");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->psy);
++ power_supply_changed(&data->bat);
++ power_supply_changed(&data->usb);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t max8903_chg(int irq, void *_data)
++{
++ struct max8903_data *data = _data;
++ struct max8903_pdata *pdata = data->pdata;
++ int chg_state;
++
++ chg_state = gpio_get_value(pdata->chg) ? false : true;
++
++ if (chg_state == data->chg_state)
++ return IRQ_HANDLED;
++ data->chg_state = chg_state;
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->psy);
++ power_supply_changed(&data->bat);
++ power_supply_changed(&data->usb);
++
++ return IRQ_HANDLED;
++}
++
++static void max8903_battery_work(struct work_struct *work)
++{
++ struct max8903_data *data;
++
++ data = container_of(work, struct max8903_data, work.work);
++ data->interval = HZ * BATTERY_UPDATE_INTERVAL;
++
++ max8903_charger_update_status(data);
++ max8903_battery_update_status(data);
++ dev_dbg(data->dev, "battery voltage: %4d mV\n", data->voltage_uV);
++ dev_dbg(data->dev, "charger online status: %d\n",
++ data->charger_online);
++ dev_dbg(data->dev, "battery status : %d\n" , data->battery_status);
++ dev_dbg(data->dev, "battery capacity percent: %3d\n", data->percent);
++ dev_dbg(data->dev, "data->usb_in: %x , data->ta_in: %x\n",
++ data->usb_in, data->ta_in);
++ /* reschedule for the next time */
++ schedule_delayed_work(&data->work, data->interval);
++}
++
++static ssize_t max8903_voltage_offset_discharger_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "read offset_discharger:%04d\n",
++ offset_discharger);
++}
++
++static ssize_t max8903_voltage_offset_discharger_store(struct device *dev,
++ struct device_attribute *attr, const char *buf,
++ size_t count)
++{
++ int ret;
++ unsigned long data;
++
++ ret = strict_strtoul(buf, 10, &data);
++ offset_discharger = (int)data;
++ pr_info("read offset_discharger:%04d\n", offset_discharger);
++
++ return count;
++}
++
++static ssize_t max8903_voltage_offset_charger_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "read offset_charger:%04d\n",
++ offset_charger);
++}
++
++static ssize_t max8903_voltage_offset_charger_store(struct device *dev,
++ struct device_attribute *attr, const char *buf,
++ size_t count)
++{
++ int ret;
++ unsigned long data;
++
++ ret = strict_strtoul(buf, 10, &data);
++ offset_charger = (int)data;
++ pr_info("read offset_charger:%04d\n", offset_charger);
++ return count;
++}
++
++static ssize_t max8903_voltage_offset_usb_charger_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "read offset_usb_charger:%04d\n",
++ offset_usb_charger);
++}
++
++static ssize_t max8903_voltage_offset_usb_charger_store(struct device *dev,
++ struct device_attribute *attr, const char *buf,
++ size_t count)
++{
++ int ret;
++ unsigned long data;
++
++ ret = strict_strtoul(buf, 10, &data);
++ offset_usb_charger = (int)data;
++ pr_info("read offset_charger:%04d\n", offset_usb_charger);
++
++ return count;
++}
++
++static struct device_attribute max8903_discharger_dev_attr = {
++ .attr = {
++ .name = "max8903_ctl_offset_discharger",
++ .mode = S_IRUSR | S_IWUSR,
++ },
++ .show = max8903_voltage_offset_discharger_show,
++ .store = max8903_voltage_offset_discharger_store,
++};
++
++static struct device_attribute max8903_charger_dev_attr = {
++ .attr = {
++ .name = "max8903_ctl_offset_charger",
++ .mode = S_IRUSR | S_IWUSR,
++ },
++ .show = max8903_voltage_offset_charger_show,
++ .store = max8903_voltage_offset_charger_store,
++};
++
++static struct device_attribute max8903_usb_charger_dev_attr = {
++ .attr = {
++ .name = "max8903_ctl_offset_usb_charger",
++ .mode = S_IRUSR | S_IWUSR,
++ },
++ .show = max8903_voltage_offset_usb_charger_show,
++ .store = max8903_voltage_offset_usb_charger_store,
++};
++
++#if defined(CONFIG_OF)
++static const struct of_device_id max8903_dt_ids[] = {
++ { .compatible = "fsl,max8903-charger", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, max8903_dt_ids);
++
++static struct max8903_pdata *max8903_of_populate_pdata(
++ struct device *dev)
++{
++ struct device_node *of_node = dev->of_node;
++ struct max8903_pdata *pdata = dev->platform_data;
++
++ if (!of_node || pdata)
++ return pdata;
++
++ pdata = devm_kzalloc(dev, sizeof(struct max8903_pdata),
++ GFP_KERNEL);
++ if (!pdata)
++ return pdata;
++
++ if (of_get_property(of_node, "fsl,dcm_always_high", NULL))
++ pdata->dcm_always_high = true;
++ if (of_get_property(of_node, "fsl,dc_valid", NULL))
++ pdata->dc_valid = true;
++ if (of_get_property(of_node, "fsl,usb_valid", NULL))
++ pdata->usb_valid = true;
++ if (of_get_property(of_node, "fsl,adc_disable", NULL))
++ pdata->feature_flag = true;
++
++ if (pdata->dc_valid) {
++ pdata->dok = of_get_named_gpio(of_node, "dok_input", 0);
++ if (!gpio_is_valid(pdata->dok)) {
++ dev_err(dev, "pin pdata->dok: invalid gpio %d\n", pdata->dok);
++ return NULL;
++ }
++ }
++ if (pdata->usb_valid) {
++ pdata->uok = of_get_named_gpio(of_node, "uok_input", 0);
++ if (!gpio_is_valid(pdata->uok)) {
++ dev_err(dev, "pin pdata->uok: invalid gpio %d\n", pdata->uok);
++ return NULL;
++ }
++ }
++ pdata->chg = of_get_named_gpio(of_node, "chg_input", 0);
++ if (!gpio_is_valid(pdata->chg)) {
++ dev_err(dev, "pin pdata->chg: invalid gpio %d\n", pdata->chg);
++ return NULL;
++ }
++ pdata->flt = of_get_named_gpio(of_node, "flt_input", 0);
++ if (!gpio_is_valid(pdata->flt)) {
++ dev_err(dev, "pin pdata->flt: invalid gpio %d\n", pdata->flt);
++ return NULL;
++ }
++ /* no need check offset without adc converter */
++ if (!pdata->feature_flag) {
++ if (of_property_read_u32(of_node, "offset-charger",
++ &offset_charger))
++ dev_err(dev, "Not setting offset-charger in dts!\n");
++
++ if (of_property_read_u32(of_node, "offset-discharger",
++ &offset_discharger))
++ dev_err(dev, "Not setting offset-discharger in dts!\n");
++
++ if (of_property_read_u32(of_node, "offset-usb-charger",
++ &offset_usb_charger))
++ dev_err(dev, "Not setting offset-usb-charger in dts!\n");
++ }
++
++ return pdata;
++}
++#endif
++
++static int max8903_probe(struct platform_device *pdev)
++{
++ struct max8903_data *data;
++ struct device *dev = &pdev->dev;
++ struct max8903_pdata *pdata = pdev->dev.platform_data;
++ int ret = 0;
++ int gpio = 0;
++ int ta_in = 0;
++ int usb_in = 0;
++ int retval;
++
++ data = devm_kzalloc(dev, sizeof(struct max8903_data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ pdata = pdev->dev.platform_data;
++ if (!pdata) {
++ pdata = max8903_of_populate_pdata(&pdev->dev);
++ if (!pdata)
++ return -EINVAL;
++ }
++
++ data->first_delay_count = 0;
++ data->pdata = pdata;
++ data->dev = dev;
++ data->usb_in = 0;
++ data->ta_in = 0;
++ platform_set_drvdata(pdev, data);
++
++ if (pdata->dc_valid == false && pdata->usb_valid == false) {
++ dev_err(dev, "No valid power sources.\n");
++ ret = -EINVAL;
++ goto err;
++ }
++ if (pdata->dc_valid) {
++ if (pdata->dok && pdata->dcm_always_high) {
++ gpio = pdata->dok;
++ ret = gpio_request_one(gpio, GPIOF_IN, "max8903-DOK");
++ if (ret) {
++ dev_err(dev, "request max8903-DOK error!!\n");
++ goto err;
++ }
++ ta_in = gpio_get_value(gpio) ? 0 : 1;
++ } else {
++ dev_err(dev, "When DC is wired, DOK and DCM should be"
++ " wired as well or set dcm always high!\n");
++ ret = -EINVAL;
++ goto err;
++ }
++ }
++
++ if (pdata->usb_valid) {
++ if (pdata->uok) {
++ gpio = pdata->uok;
++ ret = gpio_request_one(gpio, GPIOF_IN, "max8903-UOK");
++ if (ret) {
++ dev_err(dev, "request max8903-UOK error!!\n");
++ goto err;
++ }
++ usb_in = gpio_get_value(gpio) ? 0 : 1;
++ } else {
++ dev_err(dev, "When USB is wired, UOK should be wired"
++ " as well.\n");
++ ret = -EINVAL;
++ goto err;
++ }
++ }
++
++ if (pdata->chg) {
++ ret = gpio_request_one(pdata->chg, GPIOF_IN, "max8903-CHG");
++ if (ret) {
++ dev_err(dev, "request max8903-CHG error!!\n");
++ goto err;
++ }
++ }
++
++ if (pdata->flt) {
++ ret = gpio_request_one(pdata->flt, GPIOF_IN, "max8903-FLT");
++ if (ret) {
++ dev_err(dev, "request max8903-FLT error!!\n");
++ goto err;
++ }
++ }
++
++ data->fault = false;
++ data->ta_in = ta_in;
++ data->usb_in = usb_in;
++ data->psy.name = "max8903-ac";
++ data->psy.type = POWER_SUPPLY_TYPE_MAINS;
++ data->psy.get_property = max8903_get_property;
++ data->psy.properties = max8903_charger_props;
++ data->psy.num_properties = ARRAY_SIZE(max8903_charger_props);
++ ret = power_supply_register(dev, &data->psy);
++ if (ret) {
++ dev_err(dev, "failed: power supply register.\n");
++ goto err_psy;
++ }
++
++ data->usb.name = "max8903-usb";
++ data->usb.type = POWER_SUPPLY_TYPE_USB;
++ data->usb.get_property = max8903_get_usb_property;
++ data->usb.properties = max8903_charger_props;
++ data->usb.num_properties = ARRAY_SIZE(max8903_charger_props);
++ ret = power_supply_register(dev, &data->usb);
++ if (ret) {
++ dev_err(dev, "failed: power supply register.\n");
++ goto err_psy;
++ }
++
++ data->bat.name = "max8903-charger";
++ data->bat.type = POWER_SUPPLY_TYPE_BATTERY;
++ data->bat.properties = max8903_battery_props;
++ data->bat.num_properties = ARRAY_SIZE(max8903_battery_props);
++ data->bat.get_property = max8903_battery_get_property;
++ data->bat.use_for_apm = 1;
++ retval = power_supply_register(&pdev->dev, &data->bat);
++ if (retval) {
++ dev_err(data->dev, "failed to register battery\n");
++ goto battery_failed;
++ }
++
++ INIT_DELAYED_WORK(&data->work, max8903_battery_work);
++ schedule_delayed_work(&data->work, data->interval);
++
++ if (pdata->dc_valid) {
++ ret = request_threaded_irq(gpio_to_irq(pdata->dok), NULL,
++ max8903_dcin, IRQF_TRIGGER_FALLING |
++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "MAX8903 DC IN",
++ data);
++ if (ret) {
++ dev_err(dev, "Cannot request irq %d for DC (%d)\n",
++ gpio_to_irq(pdata->dok), ret);
++ goto err_dc_irq;
++ }
++ }
++
++ if (pdata->usb_valid) {
++ ret = request_threaded_irq(gpio_to_irq(pdata->uok), NULL,
++ max8903_usbin, IRQF_TRIGGER_FALLING |
++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "MAX8903 USB IN",
++ data);
++ if (ret) {
++ dev_err(dev, "Cannot request irq %d for USB (%d)\n",
++ gpio_to_irq(pdata->uok), ret);
++ goto err_usb_irq;
++ }
++ }
++
++ if (pdata->flt) {
++ ret = request_threaded_irq(gpio_to_irq(pdata->flt), NULL,
++ max8903_fault, IRQF_TRIGGER_FALLING |
++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "MAX8903 Fault",
++ data);
++ if (ret) {
++ dev_err(dev, "Cannot request irq %d for Fault (%d)\n",
++ gpio_to_irq(pdata->flt), ret);
++ goto err_flt_irq;
++ }
++ }
++
++ if (pdata->chg) {
++ ret = request_threaded_irq(gpio_to_irq(pdata->chg), NULL,
++ max8903_chg, IRQF_TRIGGER_FALLING |
++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "MAX8903 Status",
++ data);
++ if (ret) {
++ dev_err(dev, "Cannot request irq %d for Status (%d)\n",
++ gpio_to_irq(pdata->flt), ret);
++ goto err_chg_irq;
++ }
++ }
++
++ ret = device_create_file(&pdev->dev, &max8903_discharger_dev_attr);
++ if (ret)
++ dev_err(&pdev->dev, "create device file failed!\n");
++ ret = device_create_file(&pdev->dev, &max8903_charger_dev_attr);
++ if (ret)
++ dev_err(&pdev->dev, "create device file failed!\n");
++ ret = device_create_file(&pdev->dev, &max8903_usb_charger_dev_attr);
++ if (ret)
++ dev_err(&pdev->dev, "create device file failed!\n");
++
++ device_set_wakeup_capable(&pdev->dev, true);
++
++ max8903_charger_update_status(data);
++ max8903_battery_update_status(data);
++
++ return 0;
++err_psy:
++ power_supply_unregister(&data->psy);
++battery_failed:
++ power_supply_unregister(&data->bat);
++err_usb_irq:
++ if (pdata->usb_valid)
++ free_irq(gpio_to_irq(pdata->uok), data);
++ cancel_delayed_work(&data->work);
++err_dc_irq:
++ if (pdata->dc_valid)
++ free_irq(gpio_to_irq(pdata->dok), data);
++ cancel_delayed_work(&data->work);
++err_flt_irq:
++ if (pdata->usb_valid)
++ free_irq(gpio_to_irq(pdata->uok), data);
++ cancel_delayed_work(&data->work);
++err_chg_irq:
++ if (pdata->dc_valid)
++ free_irq(gpio_to_irq(pdata->dok), data);
++ cancel_delayed_work(&data->work);
++err:
++ if (pdata->uok)
++ gpio_free(pdata->uok);
++ if (pdata->dok)
++ gpio_free(pdata->dok);
++ if (pdata->flt)
++ gpio_free(pdata->flt);
++ if (pdata->chg)
++ gpio_free(pdata->chg);
++ return ret;
++}
++
++static int max8903_remove(struct platform_device *pdev)
++{
++ struct max8903_data *data = platform_get_drvdata(pdev);
++ if (data) {
++ struct max8903_pdata *pdata = data->pdata;
++
++ cancel_delayed_work_sync(&data->work);
++ power_supply_unregister(&data->psy);
++ power_supply_unregister(&data->usb);
++ power_supply_unregister(&data->bat);
++
++ if (pdata->flt) {
++ free_irq(gpio_to_irq(pdata->flt), data);
++ gpio_free(pdata->flt);
++ }
++ if (pdata->usb_valid && pdata->uok) {
++ free_irq(gpio_to_irq(pdata->uok), data);
++ gpio_free(pdata->uok);
++ }
++ if (pdata->dc_valid) {
++ if (pdata->dok) {
++ free_irq(gpio_to_irq(pdata->dok), data);
++ gpio_free(pdata->dok);
++ } else if (pdata->chg) {
++ free_irq(gpio_to_irq(pdata->chg), data);
++ gpio_free(pdata->chg);
++ }
++ }
++
++ device_remove_file(&pdev->dev, &max8903_discharger_dev_attr);
++ device_remove_file(&pdev->dev, &max8903_charger_dev_attr);
++ device_remove_file(&pdev->dev, &max8903_usb_charger_dev_attr);
++
++ platform_set_drvdata(pdev, NULL);
++ kfree(data);
++ }
++
++ return 0;
++}
++
++static int max8903_suspend(struct platform_device *pdev,
++ pm_message_t state)
++{
++ struct max8903_data *data = platform_get_drvdata(pdev);
++ int irq;
++ if (data) {
++ struct max8903_pdata *pdata = data->pdata;
++ if (pdata) {
++ if (pdata->dc_valid && device_may_wakeup(&pdev->dev)) {
++ irq = gpio_to_irq(pdata->dok);
++ enable_irq_wake(irq);
++ }
++
++ if (pdata->usb_valid && device_may_wakeup(&pdev->dev)) {
++ irq = gpio_to_irq(pdata->uok);
++ enable_irq_wake(irq);
++ }
++ cancel_delayed_work(&data->work);
++ }
++ }
++ return 0;
++}
++
++static int max8903_resume(struct platform_device *pdev)
++{
++ struct max8903_data *data = platform_get_drvdata(pdev);
++ bool ta_in = false;
++ bool usb_in = false;
++ int irq;
++
++ if (data) {
++ struct max8903_pdata *pdata = data->pdata;
++
++ if (pdata) {
++ if (pdata->dok)
++ ta_in = gpio_get_value(pdata->dok) ? false : true;
++ if (pdata->uok)
++ usb_in = gpio_get_value(pdata->uok) ? false : true;
++
++ if (ta_in != data->ta_in) {
++ data->ta_in = ta_in;
++ dev_info(data->dev, "TA(DC-IN) Charger %s.\n", ta_in ?
++ "Connected" : "Disconnected");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->psy);
++ }
++
++ if (usb_in != data->usb_in) {
++ data->usb_in = usb_in;
++ dev_info(data->dev, "USB Charger %s.\n", usb_in ?
++ "Connected" : "Disconnected");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->usb);
++ }
++
++ if (pdata->dc_valid && device_may_wakeup(&pdev->dev)) {
++ irq = gpio_to_irq(pdata->dok);
++ disable_irq_wake(irq);
++ }
++ if (pdata->usb_valid && device_may_wakeup(&pdev->dev)) {
++ irq = gpio_to_irq(pdata->uok);
++ disable_irq_wake(irq);
++ }
++
++ schedule_delayed_work(&data->work,
++ BATTERY_UPDATE_INTERVAL);
++ }
++ }
++
++ return 0;
++}
++
++static struct platform_driver max8903_driver = {
++ .probe = max8903_probe,
++ .remove = max8903_remove,
++ .suspend = max8903_suspend,
++ .resume = max8903_resume,
++ .driver = {
++ .name = "max8903-charger",
++ .owner = THIS_MODULE,
++ .of_match_table = max8903_dt_ids,
++ },
++};
++module_platform_driver(max8903_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Sabresd Battery Driver");
++MODULE_ALIAS("sabresd_battery");
+diff -Nur linux-3.10.30.orig/drivers/pwm/pwm-imx.c linux-linaro-stable-mx6/drivers/pwm/pwm-imx.c
+--- linux-3.10.30.orig/drivers/pwm/pwm-imx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/pwm/pwm-imx.c 2014-05-15 20:34:02.318044993 +0200
+@@ -1,4 +1,5 @@
+ /*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * simple driver for PWM (Pulse Width Modulator) controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -292,10 +293,34 @@
+ return pwmchip_remove(&imx->chip);
+ }
+
++#ifdef CONFIG_PM
++static int imx_pwm_suspend(struct device *dev)
++{
++ pinctrl_pm_select_sleep_state(dev);
++
++ return 0;
++}
++
++static int imx_pwm_resume(struct device *dev)
++{
++ pinctrl_pm_select_default_state(dev);
++
++ return 0;
++}
++
++static const struct dev_pm_ops imx_pwm_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(imx_pwm_suspend, imx_pwm_resume)
++};
++#endif
++
++
+ static struct platform_driver imx_pwm_driver = {
+ .driver = {
+ .name = "imx-pwm",
+ .of_match_table = of_match_ptr(imx_pwm_dt_ids),
++#ifdef CONFIG_PM
++ .pm = &imx_pwm_pm_ops,
++#endif
+ },
+ .probe = imx_pwm_probe,
+ .remove = imx_pwm_remove,
+diff -Nur linux-3.10.30.orig/drivers/regulator/anatop-regulator.c linux-linaro-stable-mx6/drivers/regulator/anatop-regulator.c
+--- linux-3.10.30.orig/drivers/regulator/anatop-regulator.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/regulator/anatop-regulator.c 2014-05-15 20:34:02.378045426 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2011, 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+ /*
+@@ -34,6 +34,22 @@
+ #define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
+ #define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
+
++#define REG_SET 0x4
++#define REG_CLR 0x8
++#define SOC_PU_FIELD_OFFSET 0x9
++
++/*
++ * for CORE, SOC and PU regulator, the register field
++ * has following definition: 00001 -- Target core voltage
++ * = 0.725V, which means the lowest setting in this
++ * field is 0.725V once the regulator is enabled. So
++ * when these regulators are turned on from off status,
++ * we need to count the voltage step of 0V to 0.7V, it will
++ * need additional delay, so the additional step number is
++ * 700mV / 25mV = 28.
++ */
++#define CORE_REG_ENABLE_STEP_ADD 28
++
+ struct anatop_regulator {
+ const char *name;
+ u32 control_reg;
+@@ -97,12 +113,86 @@
+ return regulator_get_voltage_sel_regmap(reg);
+ }
+
++/*
++ * currently on anatop regulators, only PU regulator supports
++ * enable/disable function, and its voltage must be equal
++ * to SOC voltage, so we need to get SOC voltage then set
++ * into PU regulator. Other regulators are always on due
++ * to hardware design, so enable/disable/is_enabled/enable_time
++ * functions are only used by PU regulator.
++ */
++static int anatop_regmap_enable(struct regulator_dev *reg)
++{
++ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++ u32 val;
++
++ if (!anatop_reg->control_reg)
++ return -ENOTSUPP;
++
++ regmap_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
++ val &= ((1 << anatop_reg->vol_bit_width) - 1) <<
++ (anatop_reg->vol_bit_shift + SOC_PU_FIELD_OFFSET);
++ regmap_write(anatop_reg->anatop, anatop_reg->control_reg +
++ REG_SET, val >> SOC_PU_FIELD_OFFSET);
++
++ return 0;
++}
++
++static int anatop_regmap_disable(struct regulator_dev *reg)
++{
++ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++
++ if (!anatop_reg->control_reg)
++ return -ENOTSUPP;
++
++ regmap_write(anatop_reg->anatop, anatop_reg->control_reg +
++ REG_CLR, ((1 << anatop_reg->vol_bit_width) - 1) <<
++ anatop_reg->vol_bit_shift);
++
++ return 0;
++}
++
++static int anatop_regmap_is_enabled(struct regulator_dev *reg)
++{
++ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++ u32 val;
++
++ if (!anatop_reg->control_reg)
++ return -ENOTSUPP;
++
++ regmap_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
++
++ return (val >> anatop_reg->vol_bit_shift) &
++ ((1 << anatop_reg->vol_bit_width) - 1) ? 1 : 0;
++}
++
++static int anatop_regmap_enable_time(struct regulator_dev *reg)
++{
++ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++ u32 val, soc_val;
++
++ if (!anatop_reg->control_reg)
++ return -ENOTSUPP;
++
++ regmap_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
++ soc_val = (val >> (anatop_reg->vol_bit_shift +
++ SOC_PU_FIELD_OFFSET)) &
++ ((1 << anatop_reg->vol_bit_width) - 1);
++
++ return anatop_regmap_set_voltage_time_sel(reg, 0,
++ soc_val + CORE_REG_ENABLE_STEP_ADD);
++}
++
+ static struct regulator_ops anatop_rops = {
+ .set_voltage_sel = anatop_regmap_set_voltage_sel,
+ .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
+ .get_voltage_sel = anatop_regmap_get_voltage_sel,
++ .enable = anatop_regmap_enable,
++ .disable = anatop_regmap_disable,
++ .is_enabled = anatop_regmap_is_enabled,
+ .list_voltage = regulator_list_voltage_linear,
+ .map_voltage = regulator_map_voltage_linear,
++ .enable_time = anatop_regmap_enable_time,
+ };
+
+ static int anatop_regulator_probe(struct platform_device *pdev)
+@@ -198,6 +288,7 @@
+ config.driver_data = sreg;
+ config.of_node = pdev->dev.of_node;
+ config.regmap = sreg->anatop;
++ config.ena_gpio = -EINVAL;
+
+ /* register regulator */
+ rdev = regulator_register(rdesc, &config);
+diff -Nur linux-3.10.30.orig/drivers/regulator/core.c linux-linaro-stable-mx6/drivers/regulator/core.c
+--- linux-3.10.30.orig/drivers/regulator/core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/regulator/core.c 2014-05-15 20:34:02.378045426 +0200
+@@ -3,6 +3,7 @@
+ *
+ * Copyright 2007, 2008 Wolfson Microelectronics PLC.
+ * Copyright 2008 SlimLogic Ltd.
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Liam Girdwood <lrg@slimlogic.co.uk>
+ *
+@@ -1618,6 +1619,7 @@
+ }
+
+ trace_regulator_enable_complete(rdev_get_name(rdev));
++ _notifier_call_chain(rdev, REGULATOR_EVENT_ENABLE, NULL);
+
+ return 0;
+ }
+@@ -1695,6 +1697,7 @@
+ {
+ int ret;
+
++ _notifier_call_chain(rdev, REGULATOR_EVENT_PRE_DISABLE, NULL);
+ trace_regulator_disable(rdev_get_name(rdev));
+
+ if (rdev->ena_pin) {
+@@ -1890,8 +1893,9 @@
+ rdev->deferred_disables++;
+ mutex_unlock(&rdev->mutex);
+
+- ret = schedule_delayed_work(&rdev->disable_work,
+- msecs_to_jiffies(ms));
++ ret = queue_delayed_work(system_power_efficient_wq,
++ &rdev->disable_work,
++ msecs_to_jiffies(ms));
+ if (ret < 0)
+ return ret;
+ else
+@@ -3608,7 +3612,7 @@
+
+ dev_set_drvdata(&rdev->dev, rdev);
+
+- if (config->ena_gpio && gpio_is_valid(config->ena_gpio)) {
++ if (gpio_is_valid(config->ena_gpio)) {
+ ret = regulator_ena_gpio_request(rdev, config);
+ if (ret != 0) {
+ rdev_err(rdev, "Failed to request enable GPIO%d: %d\n",
+diff -Nur linux-3.10.30.orig/drivers/regulator/dummy.c linux-linaro-stable-mx6/drivers/regulator/dummy.c
+--- linux-3.10.30.orig/drivers/regulator/dummy.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/regulator/dummy.c 2014-05-15 20:34:02.382045455 +0200
+@@ -44,6 +44,7 @@
+
+ config.dev = &pdev->dev;
+ config.init_data = &dummy_initdata;
++ config.ena_gpio = -EINVAL;
+
+ dummy_regulator_rdev = regulator_register(&dummy_desc, &config);
+ if (IS_ERR(dummy_regulator_rdev)) {
+diff -Nur linux-3.10.30.orig/drivers/regulator/fixed.c linux-linaro-stable-mx6/drivers/regulator/fixed.c
+--- linux-3.10.30.orig/drivers/regulator/fixed.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/regulator/fixed.c 2014-05-15 20:34:02.382045455 +0200
+@@ -188,8 +188,7 @@
+
+ drvdata->microvolts = config->microvolts;
+
+- if (config->gpio >= 0)
+- cfg.ena_gpio = config->gpio;
++ cfg.ena_gpio = config->gpio;
+ cfg.ena_gpio_invert = !config->enable_high;
+ if (config->enabled_at_boot) {
+ if (config->enable_high) {
+diff -Nur linux-3.10.30.orig/drivers/regulator/Kconfig linux-linaro-stable-mx6/drivers/regulator/Kconfig
+--- linux-3.10.30.orig/drivers/regulator/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/regulator/Kconfig 2014-05-15 20:34:02.374045398 +0200
+@@ -178,6 +178,10 @@
+ regulator via I2C bus. The provided regulator is suitable
+ for PXA27x chips to control VCC_CORE and VCC_USIM voltages.
+
++config REGULATOR_MAX17135
++ tristate "Maxim MAX17135 Regulator Support"
++ depends on MFD_MAX17135
++
+ config REGULATOR_MAX8649
+ tristate "Maxim 8649 voltage regulator"
+ depends on I2C
+@@ -300,6 +304,14 @@
+ Say Y here to support the voltage regulators and convertors
+ on PCF50633
+
++config REGULATOR_PFUZE100
++ tristate "Support regulators on Freescale PFUZE100 PMIC"
++ depends on I2C
++ select REGMAP_I2C
++ help
++ Say y here to support the regulators found on the Freescale PFUZE100
++ PMIC.
++
+ config REGULATOR_RC5T583
+ tristate "RICOH RC5T583 Power regulators"
+ depends on MFD_RC5T583
+diff -Nur linux-3.10.30.orig/drivers/regulator/Makefile linux-linaro-stable-mx6/drivers/regulator/Makefile
+--- linux-3.10.30.orig/drivers/regulator/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/regulator/Makefile 2014-05-15 20:34:02.374045398 +0200
+@@ -32,6 +32,7 @@
+ obj-$(CONFIG_REGULATOR_LP8788) += lp8788-ldo.o
+ obj-$(CONFIG_REGULATOR_LP8755) += lp8755.o
+ obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
++obj-$(CONFIG_REGULATOR_MAX17135) += max17135-regulator.o
+ obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o
+ obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o
+ obj-$(CONFIG_REGULATOR_MAX8907) += max8907-regulator.o
+@@ -45,6 +46,7 @@
+ obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
+ obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
+ obj-$(CONFIG_REGULATOR_PALMAS) += palmas-regulator.o
++obj-$(CONFIG_REGULATOR_PFUZE100) += pfuze100-regulator.o
+ obj-$(CONFIG_REGULATOR_TPS51632) += tps51632-regulator.o
+ obj-$(CONFIG_REGULATOR_PCAP) += pcap-regulator.o
+ obj-$(CONFIG_REGULATOR_PCF50633) += pcf50633-regulator.o
+diff -Nur linux-3.10.30.orig/drivers/regulator/max17135-regulator.c linux-linaro-stable-mx6/drivers/regulator/max17135-regulator.c
+--- linux-3.10.30.orig/drivers/regulator/max17135-regulator.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/regulator/max17135-regulator.c 2014-05-15 20:34:02.382045455 +0200
+@@ -0,0 +1,838 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/of_regulator.h>
++#include <linux/mfd/max17135.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++
++/*
++ * Regulator definitions
++ * *_MIN_uV - minimum microvolt for regulator
++ * *_MAX_uV - maximum microvolt for regulator
++ * *_STEP_uV - microvolts between regulator output levels
++ * *_MIN_VAL - minimum register field value for regulator
++ * *_MAX_VAL - maximum register field value for regulator
++ */
++#define MAX17135_HVINP_MIN_uV 5000000
++#define MAX17135_HVINP_MAX_uV 20000000
++#define MAX17135_HVINP_STEP_uV 1000000
++#define MAX17135_HVINP_MIN_VAL 0
++#define MAX17135_HVINP_MAX_VAL 1
++
++#define MAX17135_HVINN_MIN_uV 5000000
++#define MAX17135_HVINN_MAX_uV 20000000
++#define MAX17135_HVINN_STEP_uV 1000000
++#define MAX17135_HVINN_MIN_VAL 0
++#define MAX17135_HVINN_MAX_VAL 1
++
++#define MAX17135_GVDD_MIN_uV 5000000
++#define MAX17135_GVDD_MAX_uV 20000000
++#define MAX17135_GVDD_STEP_uV 1000000
++#define MAX17135_GVDD_MIN_VAL 0
++#define MAX17135_GVDD_MAX_VAL 1
++
++#define MAX17135_GVEE_MIN_uV 5000000
++#define MAX17135_GVEE_MAX_uV 20000000
++#define MAX17135_GVEE_STEP_uV 1000000
++#define MAX17135_GVEE_MIN_VAL 0
++#define MAX17135_GVEE_MAX_VAL 1
++
++#define MAX17135_VCOM_MIN_VAL 0
++#define MAX17135_VCOM_MAX_VAL 255
++
++#define MAX17135_VNEG_MIN_uV 5000000
++#define MAX17135_VNEG_MAX_uV 20000000
++#define MAX17135_VNEG_STEP_uV 1000000
++#define MAX17135_VNEG_MIN_VAL 0
++#define MAX17135_VNEG_MAX_VAL 1
++
++#define MAX17135_VPOS_MIN_uV 5000000
++#define MAX17135_VPOS_MAX_uV 20000000
++#define MAX17135_VPOS_STEP_uV 1000000
++#define MAX17135_VPOS_MIN_VAL 0
++#define MAX17135_VPOS_MAX_VAL 1
++
++struct max17135_vcom_programming_data {
++ int vcom_min_uV;
++ int vcom_max_uV;
++ int vcom_step_uV;
++};
++
++struct max17135_data {
++ int num_regulators;
++ struct max17135 *max17135;
++ struct regulator_dev **rdev;
++};
++
++static long unsigned int max17135_pass_num = { 1 };
++static int max17135_vcom = { -1250000 };
++
++struct max17135_vcom_programming_data vcom_data[2] = {
++ {
++ -4325000,
++ -500000,
++ 15000,
++ },
++ {
++ -3050000,
++ -500000,
++ 10000,
++ },
++};
++
++static int max17135_is_power_good(struct max17135 *max17135);
++
++/*
++ * Regulator operations
++ */
++static int max17135_hvinp_set_voltage(struct regulator_dev *reg,
++ int minuV, int uV, unsigned *selector)
++{
++ unsigned int reg_val;
++ unsigned int fld_val;
++
++ if ((uV >= MAX17135_HVINP_MIN_uV) &&
++ (uV <= MAX17135_HVINP_MAX_uV))
++ fld_val = (uV - MAX17135_HVINP_MIN_uV) /
++ MAX17135_HVINP_STEP_uV;
++ else
++ return -EINVAL;
++
++ max17135_reg_read(REG_MAX17135_HVINP, &reg_val);
++
++ reg_val &= ~BITFMASK(HVINP);
++ reg_val |= BITFVAL(HVINP, fld_val); /* shift to correct bit */
++
++ return max17135_reg_write(REG_MAX17135_HVINP, reg_val);
++}
++
++static int max17135_hvinp_get_voltage(struct regulator_dev *reg)
++{
++ unsigned int reg_val;
++ unsigned int fld_val;
++ int volt;
++
++ max17135_reg_read(REG_MAX17135_HVINP, &reg_val);
++
++ fld_val = (reg_val & BITFMASK(HVINP)) >> HVINP_LSH;
++
++ if ((fld_val >= MAX17135_HVINP_MIN_VAL) &&
++ (fld_val <= MAX17135_HVINP_MAX_VAL)) {
++ volt = (fld_val * MAX17135_HVINP_STEP_uV) +
++ MAX17135_HVINP_MIN_uV;
++ } else {
++ printk(KERN_ERR "MAX17135: HVINP voltage is out of range\n");
++ volt = 0;
++ }
++ return volt;
++}
++
++static int max17135_hvinp_enable(struct regulator_dev *reg)
++{
++ return 0;
++}
++
++static int max17135_hvinp_disable(struct regulator_dev *reg)
++{
++ return 0;
++}
++
++/* Convert uV to the VCOM register bitfield setting */
++static inline int vcom_uV_to_rs(int uV, int pass_num)
++{
++ return (vcom_data[pass_num].vcom_max_uV - uV)
++ / vcom_data[pass_num].vcom_step_uV;
++}
++
++/* Convert the VCOM register bitfield setting to uV */
++static inline int vcom_rs_to_uV(int rs, int pass_num)
++{
++ return vcom_data[pass_num].vcom_max_uV
++ - (vcom_data[pass_num].vcom_step_uV * rs);
++}
++
++static int max17135_vcom_set_voltage(struct regulator_dev *reg,
++ int minuV, int uV, unsigned *selector)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++ unsigned int reg_val;
++ int vcom_read;
++
++ if ((uV < vcom_data[max17135->pass_num-1].vcom_min_uV)
++ || (uV > vcom_data[max17135->pass_num-1].vcom_max_uV))
++ return -EINVAL;
++
++ max17135_reg_read(REG_MAX17135_DVR, &reg_val);
++
++ /*
++ * Only program VCOM if it is not set to the desired value.
++ * Programming VCOM excessively degrades ability to keep
++ * DVR register value persistent.
++ */
++ vcom_read = vcom_rs_to_uV(reg_val, max17135->pass_num-1);
++ if (vcom_read != max17135->vcom_uV) {
++ reg_val &= ~BITFMASK(DVR);
++ reg_val |= BITFVAL(DVR, vcom_uV_to_rs(uV,
++ max17135->pass_num-1));
++ max17135_reg_write(REG_MAX17135_DVR, reg_val);
++
++ reg_val = BITFVAL(CTRL_DVR, true); /* shift to correct bit */
++ return max17135_reg_write(REG_MAX17135_PRGM_CTRL, reg_val);
++ }
++
++ return 0;
++}
++
++static int max17135_vcom_get_voltage(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_DVR, &reg_val);
++ return vcom_rs_to_uV(BITFEXT(reg_val, DVR), max17135->pass_num-1);
++}
++
++static int max17135_vcom_enable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ /*
++ * Check to see if we need to set the VCOM voltage.
++ * Should only be done one time. And, we can
++ * only change vcom voltage if we have been enabled.
++ */
++ if (!max17135->vcom_setup && max17135_is_power_good(max17135)) {
++ max17135_vcom_set_voltage(reg,
++ max17135->vcom_uV,
++ max17135->vcom_uV,
++ NULL);
++ max17135->vcom_setup = true;
++ }
++
++ /* enable VCOM regulator output */
++ if (max17135->pass_num == 1)
++ gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 1);
++ else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= ~BITFMASK(VCOM_ENABLE);
++ reg_val |= BITFVAL(VCOM_ENABLE, 1); /* shift to correct bit */
++ max17135_reg_write(REG_MAX17135_ENABLE, reg_val);
++ }
++
++ return 0;
++}
++
++static int max17135_vcom_disable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ if (max17135->pass_num == 1)
++ gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 0);
++ else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= ~BITFMASK(VCOM_ENABLE);
++ max17135_reg_write(REG_MAX17135_ENABLE, reg_val);
++ }
++
++ return 0;
++}
++
++static int max17135_vcom_is_enabled(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ /* read VCOM regulator enable setting */
++ if (max17135->pass_num == 1) {
++ int gpio = gpio_get_value(max17135->gpio_pmic_vcom_ctrl);
++ if (gpio == 0)
++ return 0;
++ else
++ return 1;
++ } else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= BITFMASK(VCOM_ENABLE);
++ if (reg_val != 0)
++ return 1;
++ else
++ return 0;
++ }
++}
++
++static int max17135_is_power_good(struct max17135 *max17135)
++{
++ unsigned int reg_val;
++ unsigned int fld_val;
++
++ max17135_reg_read(REG_MAX17135_FAULT, &reg_val);
++ fld_val = (reg_val & BITFMASK(FAULT_POK)) >> FAULT_POK_LSH;
++
++ /* Check the POK bit */
++ return fld_val;
++}
++
++static int max17135_wait_power_good(struct max17135 *max17135)
++{
++ int i;
++
++ for (i = 0; i < max17135->max_wait * 3; i++) {
++ if (max17135_is_power_good(max17135))
++ return 0;
++
++ msleep(1);
++ }
++
++ return -ETIMEDOUT;
++}
++
++static int max17135_display_enable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ /* The Pass 1 parts cannot turn on the PMIC via I2C. */
++ if (max17135->pass_num == 1)
++ gpio_set_value(max17135->gpio_pmic_wakeup, 1);
++ else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= ~BITFMASK(ENABLE);
++ reg_val |= BITFVAL(ENABLE, 1);
++ max17135_reg_write(REG_MAX17135_ENABLE, reg_val);
++ }
++
++ return max17135_wait_power_good(max17135);
++}
++
++static int max17135_display_disable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ if (max17135->pass_num == 1)
++ gpio_set_value(max17135->gpio_pmic_wakeup, 0);
++ else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= ~BITFMASK(ENABLE);
++ max17135_reg_write(REG_MAX17135_ENABLE, reg_val);
++ }
++
++ msleep(max17135->max_wait);
++
++ return 0;
++}
++
++static int max17135_display_is_enabled(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++ int gpio = gpio_get_value(max17135->gpio_pmic_wakeup);
++
++ if (gpio == 0)
++ return 0;
++ else
++ return 1;
++}
++
++static int max17135_v3p3_enable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ gpio_set_value(max17135->gpio_pmic_v3p3, 1);
++ return 0;
++}
++
++static int max17135_v3p3_disable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ gpio_set_value(max17135->gpio_pmic_v3p3, 0);
++ return 0;
++}
++
++static int max17135_v3p3_is_enabled(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++ int gpio = gpio_get_value(max17135->gpio_pmic_v3p3);
++
++ if (gpio == 0)
++ return 0;
++ else
++ return 1;
++}
++
++/*
++ * Regulator operations
++ */
++
++static struct regulator_ops max17135_display_ops = {
++ .enable = max17135_display_enable,
++ .disable = max17135_display_disable,
++ .is_enabled = max17135_display_is_enabled,
++};
++
++static struct regulator_ops max17135_gvdd_ops = {
++};
++
++static struct regulator_ops max17135_gvee_ops = {
++};
++
++static struct regulator_ops max17135_hvinn_ops = {
++};
++
++static struct regulator_ops max17135_hvinp_ops = {
++ .enable = max17135_hvinp_enable,
++ .disable = max17135_hvinp_disable,
++ .get_voltage = max17135_hvinp_get_voltage,
++ .set_voltage = max17135_hvinp_set_voltage,
++};
++
++static struct regulator_ops max17135_vcom_ops = {
++ .enable = max17135_vcom_enable,
++ .disable = max17135_vcom_disable,
++ .get_voltage = max17135_vcom_get_voltage,
++ .set_voltage = max17135_vcom_set_voltage,
++ .is_enabled = max17135_vcom_is_enabled,
++};
++
++static struct regulator_ops max17135_vneg_ops = {
++};
++
++static struct regulator_ops max17135_vpos_ops = {
++};
++
++static struct regulator_ops max17135_v3p3_ops = {
++ .enable = max17135_v3p3_enable,
++ .disable = max17135_v3p3_disable,
++ .is_enabled = max17135_v3p3_is_enabled,
++};
++
++
++/*
++ * Regulator descriptors
++ */
++static struct regulator_desc max17135_reg[MAX17135_NUM_REGULATORS] = {
++{
++ .name = "DISPLAY",
++ .id = MAX17135_DISPLAY,
++ .ops = &max17135_display_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "GVDD",
++ .id = MAX17135_GVDD,
++ .ops = &max17135_gvdd_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "GVEE",
++ .id = MAX17135_GVEE,
++ .ops = &max17135_gvee_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "HVINN",
++ .id = MAX17135_HVINN,
++ .ops = &max17135_hvinn_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "HVINP",
++ .id = MAX17135_HVINP,
++ .ops = &max17135_hvinp_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "VCOM",
++ .id = MAX17135_VCOM,
++ .ops = &max17135_vcom_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "VNEG",
++ .id = MAX17135_VNEG,
++ .ops = &max17135_vneg_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "VPOS",
++ .id = MAX17135_VPOS,
++ .ops = &max17135_vpos_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "V3P3",
++ .id = MAX17135_V3P3,
++ .ops = &max17135_v3p3_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++};
++
++static void max17135_setup_timings(struct max17135 *max17135)
++{
++ unsigned int reg_val;
++
++ int timing1, timing2, timing3, timing4,
++ timing5, timing6, timing7, timing8;
++
++ max17135_reg_read(REG_MAX17135_TIMING1, &timing1);
++ max17135_reg_read(REG_MAX17135_TIMING2, &timing2);
++ max17135_reg_read(REG_MAX17135_TIMING3, &timing3);
++ max17135_reg_read(REG_MAX17135_TIMING4, &timing4);
++ max17135_reg_read(REG_MAX17135_TIMING5, &timing5);
++ max17135_reg_read(REG_MAX17135_TIMING6, &timing6);
++ max17135_reg_read(REG_MAX17135_TIMING7, &timing7);
++ max17135_reg_read(REG_MAX17135_TIMING8, &timing8);
++
++ if ((timing1 != max17135->gvee_pwrup) ||
++ (timing2 != max17135->vneg_pwrup) ||
++ (timing3 != max17135->vpos_pwrup) ||
++ (timing4 != max17135->gvdd_pwrup) ||
++ (timing5 != max17135->gvdd_pwrdn) ||
++ (timing6 != max17135->vpos_pwrdn) ||
++ (timing7 != max17135->vneg_pwrdn) ||
++ (timing8 != max17135->gvee_pwrdn)) {
++ max17135_reg_write(REG_MAX17135_TIMING1, max17135->gvee_pwrup);
++ max17135_reg_write(REG_MAX17135_TIMING2, max17135->vneg_pwrup);
++ max17135_reg_write(REG_MAX17135_TIMING3, max17135->vpos_pwrup);
++ max17135_reg_write(REG_MAX17135_TIMING4, max17135->gvdd_pwrup);
++ max17135_reg_write(REG_MAX17135_TIMING5, max17135->gvdd_pwrdn);
++ max17135_reg_write(REG_MAX17135_TIMING6, max17135->vpos_pwrdn);
++ max17135_reg_write(REG_MAX17135_TIMING7, max17135->vneg_pwrdn);
++ max17135_reg_write(REG_MAX17135_TIMING8, max17135->gvee_pwrdn);
++
++ reg_val = BITFVAL(CTRL_TIMING, true); /* shift to correct bit */
++ max17135_reg_write(REG_MAX17135_PRGM_CTRL, reg_val);
++ }
++}
++
++#define CHECK_PROPERTY_ERROR_KFREE(prop) \
++do { \
++ int ret = of_property_read_u32(max17135->dev->of_node, \
++ #prop, &max17135->prop); \
++ if (ret < 0) { \
++ return ret; \
++ } \
++} while (0);
++
++#ifdef CONFIG_OF
++static int max17135_pmic_dt_parse_pdata(struct platform_device *pdev,
++ struct max17135_platform_data *pdata)
++{
++ struct max17135 *max17135 = dev_get_drvdata(pdev->dev.parent);
++ struct device_node *pmic_np, *regulators_np, *reg_np;
++ struct max17135_regulator_data *rdata;
++ int i, ret;
++
++ pmic_np = of_node_get(max17135->dev->of_node);
++ if (!pmic_np) {
++ dev_err(&pdev->dev, "could not find pmic sub-node\n");
++ return -ENODEV;
++ }
++
++ regulators_np = of_find_node_by_name(pmic_np, "regulators");
++ if (!regulators_np) {
++ dev_err(&pdev->dev, "could not find regulators sub-node\n");
++ return -EINVAL;
++ }
++
++ pdata->num_regulators = of_get_child_count(regulators_np);
++ dev_dbg(&pdev->dev, "num_regulators %d\n", pdata->num_regulators);
++
++ rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) *
++ pdata->num_regulators, GFP_KERNEL);
++ if (!rdata) {
++ of_node_put(regulators_np);
++ dev_err(&pdev->dev, "could not allocate memory for"
++ "regulator data\n");
++ return -ENOMEM;
++ }
++
++ pdata->regulators = rdata;
++ for_each_child_of_node(regulators_np, reg_np) {
++ for (i = 0; i < ARRAY_SIZE(max17135_reg); i++)
++ if (!of_node_cmp(reg_np->name, max17135_reg[i].name))
++ break;
++
++ if (i == ARRAY_SIZE(max17135_reg)) {
++ dev_warn(&pdev->dev, "don't know how to configure"
++ "regulator %s\n", reg_np->name);
++ continue;
++ }
++
++ rdata->id = i;
++ rdata->initdata = of_get_regulator_init_data(&pdev->dev,
++ reg_np);
++ rdata->reg_node = reg_np;
++ rdata++;
++ }
++ of_node_put(regulators_np);
++
++ CHECK_PROPERTY_ERROR_KFREE(vneg_pwrup);
++ CHECK_PROPERTY_ERROR_KFREE(gvee_pwrup);
++ CHECK_PROPERTY_ERROR_KFREE(vpos_pwrup);
++ CHECK_PROPERTY_ERROR_KFREE(gvdd_pwrup);
++ CHECK_PROPERTY_ERROR_KFREE(gvdd_pwrdn);
++ CHECK_PROPERTY_ERROR_KFREE(vpos_pwrdn);
++ CHECK_PROPERTY_ERROR_KFREE(gvee_pwrdn);
++ CHECK_PROPERTY_ERROR_KFREE(vneg_pwrdn);
++
++ dev_dbg(&pdev->dev, "vneg_pwrup %d, vneg_pwrdn %d, vpos_pwrup %d,"
++ "vpos_pwrdn %d, gvdd_pwrup %d, gvdd_pwrdn %d, gvee_pwrup %d,"
++ "gvee_pwrdn %d\n", max17135->vneg_pwrup, max17135->vneg_pwrdn,
++ max17135->vpos_pwrup, max17135->vpos_pwrdn,
++ max17135->gvdd_pwrup, max17135->gvdd_pwrdn,
++ max17135->gvee_pwrup, max17135->gvee_pwrdn);
++
++ max17135->max_wait = max17135->vpos_pwrup + max17135->vneg_pwrup +
++ max17135->gvdd_pwrup + max17135->gvee_pwrup;
++
++ max17135->gpio_pmic_wakeup = of_get_named_gpio(pmic_np,
++ "gpio_pmic_wakeup", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_wakeup)) {
++ dev_err(&pdev->dev, "no epdc pmic wakeup pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_wakeup,
++ GPIOF_OUT_INIT_LOW, "epdc-pmic-wake");
++ if (ret < 0)
++ goto err;
++
++ max17135->gpio_pmic_vcom_ctrl = of_get_named_gpio(pmic_np,
++ "gpio_pmic_vcom_ctrl", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_vcom_ctrl)) {
++ dev_err(&pdev->dev, "no epdc pmic vcom_ctrl pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_vcom_ctrl,
++ GPIOF_OUT_INIT_LOW, "epdc-vcom");
++ if (ret < 0)
++ goto err;
++
++ max17135->gpio_pmic_v3p3 = of_get_named_gpio(pmic_np,
++ "gpio_pmic_v3p3", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_v3p3)) {
++ dev_err(&pdev->dev, "no epdc pmic v3p3 pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_v3p3,
++ GPIOF_OUT_INIT_LOW, "epdc-v3p3");
++ if (ret < 0)
++ goto err;
++
++ max17135->gpio_pmic_intr = of_get_named_gpio(pmic_np,
++ "gpio_pmic_intr", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_intr)) {
++ dev_err(&pdev->dev, "no epdc pmic intr pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_intr,
++ GPIOF_IN, "epdc-pmic-int");
++ if (ret < 0)
++ goto err;
++
++ max17135->gpio_pmic_pwrgood = of_get_named_gpio(pmic_np,
++ "gpio_pmic_pwrgood", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_pwrgood)) {
++ dev_err(&pdev->dev, "no epdc pmic pwrgood pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_pwrgood,
++ GPIOF_IN, "epdc-pwrstat");
++ if (ret < 0)
++ goto err;
++
++err:
++ return 0;
++
++}
++#else
++static int max17135_pmic_dt_parse_pdata(struct platform_device *pdev,
++ struct max17135 *max17135)
++{
++ return 0;
++}
++#endif /* !CONFIG_OF */
++
++/*
++ * Regulator init/probing/exit functions
++ */
++static int max17135_regulator_probe(struct platform_device *pdev)
++{
++ struct max17135 *max17135 = dev_get_drvdata(pdev->dev.parent);
++ struct max17135_platform_data *pdata = max17135->pdata;
++ struct max17135_data *priv;
++ struct regulator_dev **rdev;
++ struct regulator_config config = { };
++ int size, i, ret = 0;
++
++ if (max17135->dev->of_node) {
++ ret = max17135_pmic_dt_parse_pdata(pdev, pdata);
++ if (ret)
++ return ret;
++ }
++ priv = devm_kzalloc(&pdev->dev, sizeof(struct max17135_data),
++ GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ size = sizeof(struct regulator_dev *) * pdata->num_regulators;
++ priv->rdev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
++ if (!priv->rdev)
++ return -ENOMEM;
++
++ rdev = priv->rdev;
++ priv->num_regulators = pdata->num_regulators;
++ platform_set_drvdata(pdev, priv);
++
++ max17135->vcom_setup = false;
++ max17135->pass_num = max17135_pass_num;
++ max17135->vcom_uV = max17135_vcom;
++
++ for (i = 0; i < pdata->num_regulators; i++) {
++ int id = pdata->regulators[i].id;
++
++ config.dev = max17135->dev;
++ config.init_data = pdata->regulators[i].initdata;
++ config.driver_data = max17135;
++ config.of_node = pdata->regulators[i].reg_node;
++
++ rdev[i] = regulator_register(&max17135_reg[id], &config);
++ if (IS_ERR(rdev[i])) {
++ ret = PTR_ERR(rdev[i]);
++ dev_err(&pdev->dev, "regulator init failed for %d\n",
++ id);
++ rdev[i] = NULL;
++ goto err;
++ }
++ }
++
++ /*
++ * Set up PMIC timing values.
++ * Should only be done one time! Timing values may only be
++ * changed a limited number of times according to spec.
++ */
++ max17135_setup_timings(max17135);
++
++ return 0;
++err:
++ while (--i >= 0)
++ regulator_unregister(rdev[i]);
++ return ret;
++}
++
++static int max17135_regulator_remove(struct platform_device *pdev)
++{
++ struct max17135_data *priv = platform_get_drvdata(pdev);
++ struct regulator_dev **rdev = priv->rdev;
++ int i;
++
++ for (i = 0; i < priv->num_regulators; i++)
++ regulator_unregister(rdev[i]);
++ return 0;
++}
++
++static const struct platform_device_id max17135_pmic_id[] = {
++ { "max17135-pmic", 0},
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(platform, max17135_pmic_id);
++
++static struct platform_driver max17135_regulator_driver = {
++ .probe = max17135_regulator_probe,
++ .remove = max17135_regulator_remove,
++ .id_table = max17135_pmic_id,
++ .driver = {
++ .name = "max17135-pmic",
++ },
++};
++
++static int __init max17135_regulator_init(void)
++{
++ return platform_driver_register(&max17135_regulator_driver);
++}
++subsys_initcall_sync(max17135_regulator_init);
++
++static void __exit max17135_regulator_exit(void)
++{
++ platform_driver_unregister(&max17135_regulator_driver);
++}
++module_exit(max17135_regulator_exit);
++
++/*
++ * Parse user specified options (`max17135:')
++ * example:
++ * max17135:pass=2,vcom=-1250000
++ */
++static int __init max17135_setup(char *options)
++{
++ int ret;
++ char *opt;
++ while ((opt = strsep(&options, ",")) != NULL) {
++ if (!*opt)
++ continue;
++ if (!strncmp(opt, "pass=", 5)) {
++ ret = strict_strtoul(opt + 5, 0, &max17135_pass_num);
++ if (ret < 0)
++ return ret;
++ }
++ if (!strncmp(opt, "vcom=", 5)) {
++ int offs = 5;
++ if (opt[5] == '-')
++ offs = 6;
++ ret = strict_strtoul(opt + offs, 0,
++ (long *)&max17135_vcom);
++ if (ret < 0)
++ return ret;
++ max17135_vcom = -max17135_vcom;
++ }
++ }
++
++ return 1;
++}
++
++__setup("max17135:", max17135_setup);
++
++/* Module information */
++MODULE_DESCRIPTION("MAX17135 regulator driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/regulator/pfuze100-regulator.c linux-linaro-stable-mx6/drivers/regulator/pfuze100-regulator.c
+--- linux-3.10.30.orig/drivers/regulator/pfuze100-regulator.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/regulator/pfuze100-regulator.c 2014-05-15 20:34:02.402045599 +0200
+@@ -0,0 +1,445 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/regulator/of_regulator.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/machine.h>
++#include <linux/regulator/pfuze100.h>
++#include <linux/i2c.h>
++#include <linux/slab.h>
++#include <linux/regmap.h>
++
++#define PFUZE_NUMREGS 128
++#define PFUZE100_VOL_OFFSET 0
++#define PFUZE100_STANDBY_OFFSET 1
++#define PFUZE100_MODE_OFFSET 3
++#define PFUZE100_CONF_OFFSET 4
++
++#define PFUZE100_DEVICEID 0x0
++#define PFUZE100_REVID 0x3
++#define PFUZE100_FABID 0x3
++
++#define PFUZE100_SW1ABVOL 0x20
++#define PFUZE100_SW1CVOL 0x2e
++#define PFUZE100_SW2VOL 0x35
++#define PFUZE100_SW3AVOL 0x3c
++#define PFUZE100_SW3BVOL 0x43
++#define PFUZE100_SW4VOL 0x4a
++#define PFUZE100_SWBSTCON1 0x66
++#define PFUZE100_VREFDDRCON 0x6a
++#define PFUZE100_VSNVSVOL 0x6b
++#define PFUZE100_VGEN1VOL 0x6c
++#define PFUZE100_VGEN2VOL 0x6d
++#define PFUZE100_VGEN3VOL 0x6e
++#define PFUZE100_VGEN4VOL 0x6f
++#define PFUZE100_VGEN5VOL 0x70
++#define PFUZE100_VGEN6VOL 0x71
++
++struct pfuze_regulator {
++ struct regulator_desc desc;
++ unsigned char stby_reg;
++ unsigned char stby_mask;
++};
++
++struct pfuze_chip {
++ struct regmap *regmap;
++ struct device *dev;
++ struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
++ struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
++};
++
++static const int pfuze100_swbst[] = {
++ 5000000, 5050000, 5100000, 5150000,
++};
++
++static const int pfuze100_vsnvs[] = {
++ 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
++};
++
++static const struct i2c_device_id pfuze_device_id[] = {
++ {.name = "pfuze100"},
++ {},
++};
++MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
++
++static const struct of_device_id pfuze_dt_ids[] = {
++ { .compatible = "fsl,pfuze100" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
++
++static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
++{
++ struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
++ int id = rdev->desc->id;
++ unsigned int ramp_bits;
++ int ret;
++
++ if (id < PFUZE100_SWBST) {
++ ramp_delay = 12500 / ramp_delay;
++ ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
++ ret = regmap_update_bits(pfuze100->regmap,
++ rdev->desc->vsel_reg + 4,
++ 0xc0, ramp_bits << 6);
++ if (ret < 0)
++ dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
++ } else
++ ret = -EACCES;
++
++ return ret;
++}
++
++static struct regulator_ops pfuze100_ldo_regulator_ops = {
++ .enable = regulator_enable_regmap,
++ .disable = regulator_disable_regmap,
++ .is_enabled = regulator_is_enabled_regmap,
++ .list_voltage = regulator_list_voltage_linear,
++ .set_voltage_sel = regulator_set_voltage_sel_regmap,
++ .get_voltage_sel = regulator_get_voltage_sel_regmap,
++};
++
++static struct regulator_ops pfuze100_fixed_regulator_ops = {
++ .list_voltage = regulator_list_voltage_linear,
++};
++
++static struct regulator_ops pfuze100_sw_regulator_ops = {
++ .list_voltage = regulator_list_voltage_linear,
++ .set_voltage_sel = regulator_set_voltage_sel_regmap,
++ .get_voltage_sel = regulator_get_voltage_sel_regmap,
++ .set_voltage_time_sel = regulator_set_voltage_time_sel,
++ .set_ramp_delay = pfuze100_set_ramp_delay,
++};
++
++static struct regulator_ops pfuze100_swb_regulator_ops = {
++ .list_voltage = regulator_list_voltage_table,
++ .map_voltage = regulator_map_voltage_ascend,
++ .set_voltage_sel = regulator_set_voltage_sel_regmap,
++ .get_voltage_sel = regulator_get_voltage_sel_regmap,
++
++};
++
++#define PFUZE100_FIXED_REG(_name, base, voltage) \
++ [PFUZE100_ ## _name] = { \
++ .desc = { \
++ .name = #_name, \
++ .n_voltages = 1, \
++ .ops = &pfuze100_fixed_regulator_ops, \
++ .type = REGULATOR_VOLTAGE, \
++ .id = PFUZE100_ ## _name, \
++ .owner = THIS_MODULE, \
++ .min_uV = (voltage), \
++ .enable_reg = (base), \
++ .enable_mask = 0x10, \
++ }, \
++ }
++
++#define PFUZE100_SW_REG(_name, base, min, max, step) \
++ [PFUZE100_ ## _name] = { \
++ .desc = { \
++ .name = #_name,\
++ .n_voltages = ((max) - (min)) / (step) + 1, \
++ .ops = &pfuze100_sw_regulator_ops, \
++ .type = REGULATOR_VOLTAGE, \
++ .id = PFUZE100_ ## _name, \
++ .owner = THIS_MODULE, \
++ .min_uV = (min), \
++ .uV_step = (step), \
++ .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
++ .vsel_mask = 0x3f, \
++ }, \
++ .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
++ .stby_mask = 0x3f, \
++ }
++
++#define PFUZE100_SWB_REG(_name, base, mask, voltages) \
++ [PFUZE100_ ## _name] = { \
++ .desc = { \
++ .name = #_name, \
++ .n_voltages = ARRAY_SIZE(voltages), \
++ .ops = &pfuze100_swb_regulator_ops, \
++ .type = REGULATOR_VOLTAGE, \
++ .id = PFUZE100_ ## _name, \
++ .owner = THIS_MODULE, \
++ .volt_table = voltages, \
++ .vsel_reg = (base), \
++ .vsel_mask = (mask), \
++ }, \
++ }
++
++#define PFUZE100_VGEN_REG(_name, base, min, max, step) \
++ [PFUZE100_ ## _name] = { \
++ .desc = { \
++ .name = #_name, \
++ .n_voltages = ((max) - (min)) / (step) + 1, \
++ .ops = &pfuze100_ldo_regulator_ops, \
++ .type = REGULATOR_VOLTAGE, \
++ .id = PFUZE100_ ## _name, \
++ .owner = THIS_MODULE, \
++ .min_uV = (min), \
++ .uV_step = (step), \
++ .vsel_reg = (base), \
++ .vsel_mask = 0xf, \
++ .enable_reg = (base), \
++ .enable_mask = 0x10, \
++ }, \
++ .stby_reg = (base), \
++ .stby_mask = 0x20, \
++ }
++
++static struct pfuze_regulator pfuze100_regulators[] = {
++ PFUZE100_SW_REG(SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
++ PFUZE100_SW_REG(SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
++ PFUZE100_SW_REG(SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
++ PFUZE100_SW_REG(SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
++ PFUZE100_SW_REG(SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
++ PFUZE100_SW_REG(SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
++ PFUZE100_SWB_REG(SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
++ PFUZE100_SWB_REG(VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
++ PFUZE100_FIXED_REG(VREFDDR, PFUZE100_VREFDDRCON, 750000),
++ PFUZE100_VGEN_REG(VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
++ PFUZE100_VGEN_REG(VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
++ PFUZE100_VGEN_REG(VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
++};
++
++#ifdef CONFIG_OF
++static struct of_regulator_match pfuze100_matches[] = {
++ { .name = "sw1ab", },
++ { .name = "sw1c", },
++ { .name = "sw2", },
++ { .name = "sw3a", },
++ { .name = "sw3b", },
++ { .name = "sw4", },
++ { .name = "swbst", },
++ { .name = "vsnvs", },
++ { .name = "vrefddr", },
++ { .name = "vgen1", },
++ { .name = "vgen2", },
++ { .name = "vgen3", },
++ { .name = "vgen4", },
++ { .name = "vgen5", },
++ { .name = "vgen6", },
++};
++
++static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
++{
++ struct device *dev = chip->dev;
++ struct device_node *np, *parent;
++ int ret;
++
++ np = of_node_get(dev->parent->of_node);
++ if (!np)
++ return 0;
++
++ parent = of_find_node_by_name(np, "regulators");
++ if (!parent) {
++ dev_err(dev, "regulators node not found\n");
++ return -EINVAL;
++ }
++
++ ret = of_regulator_match(dev, parent, pfuze100_matches,
++ ARRAY_SIZE(pfuze100_matches));
++
++ of_node_put(parent);
++ if (ret < 0) {
++ dev_err(dev, "Error parsing regulator init data: %d\n",
++ ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static inline struct regulator_init_data *match_init_data(int index)
++{
++ return pfuze100_matches[index].init_data;
++}
++
++static inline struct device_node *match_of_node(int index)
++{
++ return pfuze100_matches[index].of_node;
++}
++#else
++static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
++{
++ return 0;
++}
++
++static inline struct regulator_init_data *match_init_data(int index)
++{
++ return NULL;
++}
++
++static inline struct device_node *match_of_node(int index)
++{
++ return NULL;
++}
++#endif
++
++static int pfuze_identify(struct pfuze_chip *pfuze_chip)
++{
++ unsigned int value;
++ int ret;
++
++ ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
++ if (ret)
++ return ret;
++
++ if (value & 0x0f) {
++ dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
++ return -ENODEV;
++ }
++
++ ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
++ if (ret)
++ return ret;
++ dev_info(pfuze_chip->dev,
++ "Full lay: %x, Metal lay: %x\n",
++ (value & 0xf0) >> 4, value & 0x0f);
++
++ ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
++ if (ret)
++ return ret;
++ dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
++ (value & 0xc) >> 2, value & 0x3);
++
++ return 0;
++}
++
++static const struct regmap_config pfuze_regmap_config = {
++ .reg_bits = 8,
++ .val_bits = 8,
++ .max_register = PFUZE_NUMREGS - 1,
++ .cache_type = REGCACHE_RBTREE,
++};
++
++static int pfuze100_regulator_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct pfuze_chip *pfuze_chip;
++ struct pfuze_regulator_platform_data *pdata =
++ dev_get_platdata(&client->dev);
++ struct regulator_config config = { };
++ int i, ret;
++
++ pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
++ GFP_KERNEL);
++ if (!pfuze_chip)
++ return -ENOMEM;
++
++ i2c_set_clientdata(client, pfuze_chip);
++
++ memcpy(pfuze_chip->regulator_descs, pfuze100_regulators,
++ sizeof(pfuze_chip->regulator_descs));
++
++ pfuze_chip->dev = &client->dev;
++
++ pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
++ if (IS_ERR(pfuze_chip->regmap)) {
++ ret = PTR_ERR(pfuze_chip->regmap);
++ dev_err(&client->dev,
++ "regmap allocation failed with err %d\n", ret);
++ return ret;
++ }
++
++ ret = pfuze_identify(pfuze_chip);
++ if (ret) {
++ dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
++ return ret;
++ }
++
++ ret = pfuze_parse_regulators_dt(pfuze_chip);
++ if (ret)
++ return ret;
++
++ for (i = 0; i < PFUZE100_MAX_REGULATOR; i++) {
++ struct regulator_init_data *init_data;
++ struct regulator_desc *desc;
++ int val;
++
++ desc = &pfuze_chip->regulator_descs[i].desc;
++
++ if (pdata)
++ init_data = pdata->init_data[i];
++ else
++ init_data = match_init_data(i);
++
++ /* SW2~SW4 high bit check and modify the voltage value table */
++ if (i > PFUZE100_SW1C && i < PFUZE100_SWBST) {
++ regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
++ if (val & 0x40) {
++ desc->min_uV = 800000;
++ desc->uV_step = 50000;
++ desc->n_voltages = 51;
++ }
++ }
++
++ config.dev = &client->dev;
++ config.init_data = init_data;
++ config.driver_data = pfuze_chip;
++ config.of_node = match_of_node(i);
++
++ pfuze_chip->regulators[i] = regulator_register(desc, &config);
++ if (IS_ERR(pfuze_chip->regulators[i])) {
++ dev_err(&client->dev, "register regulator%s failed\n",
++ pfuze100_regulators[i].desc.name);
++ ret = PTR_ERR(pfuze_chip->regulators[i]);
++ while (--i >= 0)
++ regulator_unregister(pfuze_chip->regulators[i]);
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static int pfuze100_regulator_remove(struct i2c_client *client)
++{
++ int i;
++ struct pfuze_chip *pfuze_chip = i2c_get_clientdata(client);
++
++ for (i = 0; i < PFUZE100_MAX_REGULATOR; i++)
++ regulator_unregister(pfuze_chip->regulators[i]);
++
++ return 0;
++}
++
++static struct i2c_driver pfuze_driver = {
++ .id_table = pfuze_device_id,
++ .driver = {
++ .name = "pfuze100-regulator",
++ .owner = THIS_MODULE,
++ .of_match_table = pfuze_dt_ids,
++ },
++ .probe = pfuze100_regulator_probe,
++ .remove = pfuze100_regulator_remove,
++};
++module_i2c_driver(pfuze_driver);
++
++MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
++MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("i2c:pfuze100-regulator");
+diff -Nur linux-3.10.30.orig/drivers/reset/gpio-reset.c linux-linaro-stable-mx6/drivers/reset/gpio-reset.c
+--- linux-3.10.30.orig/drivers/reset/gpio-reset.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/reset/gpio-reset.c 2014-05-15 20:34:02.438045859 +0200
+@@ -0,0 +1,187 @@
++/*
++ * GPIO Reset Controller driver
++ *
++ * Copyright 2013 Philipp Zabel, Pengutronix
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/gpio.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++
++struct gpio_reset_data {
++ struct reset_controller_dev rcdev;
++ unsigned int gpio;
++ bool active_low;
++ s32 delay_us;
++};
++
++static void gpio_reset_set(struct reset_controller_dev *rcdev, int asserted)
++{
++ struct gpio_reset_data *drvdata = container_of(rcdev,
++ struct gpio_reset_data, rcdev);
++ int value = asserted;
++
++ if (drvdata->active_low)
++ value = !value;
++
++ if (gpio_cansleep(drvdata->gpio))
++ gpio_set_value_cansleep(drvdata->gpio, value);
++ else
++ gpio_set_value(drvdata->gpio, value);
++}
++
++static int gpio_reset(struct reset_controller_dev *rcdev, unsigned long id)
++{
++ struct gpio_reset_data *drvdata = container_of(rcdev,
++ struct gpio_reset_data, rcdev);
++
++ if (drvdata->delay_us < 0)
++ return -ENOSYS;
++
++ gpio_reset_set(rcdev, 1);
++ udelay(drvdata->delay_us);
++ gpio_reset_set(rcdev, 0);
++
++ return 0;
++}
++
++static int gpio_reset_assert(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ gpio_reset_set(rcdev, 1);
++
++ return 0;
++}
++
++static int gpio_reset_deassert(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ gpio_reset_set(rcdev, 0);
++
++ return 0;
++}
++
++static struct reset_control_ops gpio_reset_ops = {
++ .reset = gpio_reset,
++ .assert = gpio_reset_assert,
++ .deassert = gpio_reset_deassert,
++};
++
++static int of_gpio_reset_xlate(struct reset_controller_dev *rcdev,
++ const struct of_phandle_args *reset_spec)
++{
++ if (WARN_ON(reset_spec->args_count != 0))
++ return -EINVAL;
++
++ return 0;
++}
++
++static int gpio_reset_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct gpio_reset_data *drvdata;
++ enum of_gpio_flags flags;
++ unsigned long gpio_flags;
++ bool initially_in_reset;
++ int ret;
++
++ drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
++ if (drvdata == NULL)
++ return -ENOMEM;
++
++ if (of_gpio_named_count(np, "reset-gpios") != 1) {
++ dev_err(&pdev->dev,
++ "reset-gpios property missing, or not a single gpio\n");
++ return -EINVAL;
++ }
++
++ drvdata->gpio = of_get_named_gpio_flags(np, "reset-gpios", 0, &flags);
++ if (drvdata->gpio == -EPROBE_DEFER) {
++ return drvdata->gpio;
++ } else if (!gpio_is_valid(drvdata->gpio)) {
++ dev_err(&pdev->dev, "invalid reset gpio: %d\n", drvdata->gpio);
++ return drvdata->gpio;
++ }
++
++ drvdata->active_low = flags & OF_GPIO_ACTIVE_LOW;
++
++ ret = of_property_read_u32(np, "reset-delay-us", &drvdata->delay_us);
++ if (ret < 0)
++ drvdata->delay_us = -1;
++ else if (drvdata->delay_us < 0)
++ dev_warn(&pdev->dev, "reset delay too high\n");
++
++ initially_in_reset = of_property_read_bool(np, "initially-in-reset");
++ if (drvdata->active_low ^ initially_in_reset)
++ gpio_flags = GPIOF_OUT_INIT_HIGH;
++ else
++ gpio_flags = GPIOF_OUT_INIT_LOW;
++
++ ret = devm_gpio_request_one(&pdev->dev, drvdata->gpio, gpio_flags, NULL);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to request gpio %d: %d\n",
++ drvdata->gpio, ret);
++ return ret;
++ }
++
++ platform_set_drvdata(pdev, drvdata);
++
++ drvdata->rcdev.of_node = np;
++ drvdata->rcdev.owner = THIS_MODULE;
++ drvdata->rcdev.nr_resets = 1;
++ drvdata->rcdev.ops = &gpio_reset_ops;
++ drvdata->rcdev.of_xlate = of_gpio_reset_xlate;
++ reset_controller_register(&drvdata->rcdev);
++
++ return 0;
++}
++
++static int gpio_reset_remove(struct platform_device *pdev)
++{
++ struct gpio_reset_data *drvdata = platform_get_drvdata(pdev);
++
++ reset_controller_unregister(&drvdata->rcdev);
++
++ return 0;
++}
++
++static struct of_device_id gpio_reset_dt_ids[] = {
++ { .compatible = "gpio-reset" },
++ { }
++};
++
++static struct platform_driver gpio_reset_driver = {
++ .probe = gpio_reset_probe,
++ .remove = gpio_reset_remove,
++ .driver = {
++ .name = "gpio-reset",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(gpio_reset_dt_ids),
++ },
++};
++
++static int __init gpio_reset_init(void)
++{
++ return platform_driver_register(&gpio_reset_driver);
++}
++arch_initcall(gpio_reset_init);
++
++static void __exit gpio_reset_exit(void)
++{
++ platform_driver_unregister(&gpio_reset_driver);
++}
++module_exit(gpio_reset_exit);
++
++MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
++MODULE_DESCRIPTION("gpio reset controller");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:gpio-reset");
++MODULE_DEVICE_TABLE(of, gpio_reset_dt_ids);
+diff -Nur linux-3.10.30.orig/drivers/reset/Kconfig linux-linaro-stable-mx6/drivers/reset/Kconfig
+--- linux-3.10.30.orig/drivers/reset/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/reset/Kconfig 2014-05-15 20:34:02.434045830 +0200
+@@ -11,3 +11,15 @@
+ via GPIOs or SoC-internal reset controller modules.
+
+ If unsure, say no.
++
++if RESET_CONTROLLER
++
++config RESET_GPIO
++ tristate "GPIO reset controller support"
++ default y
++ depends on GPIOLIB && OF
++ help
++ This driver provides support for reset lines that are controlled
++ directly by GPIOs.
++
++endif
+diff -Nur linux-3.10.30.orig/drivers/reset/Makefile linux-linaro-stable-mx6/drivers/reset/Makefile
+--- linux-3.10.30.orig/drivers/reset/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/reset/Makefile 2014-05-15 20:34:02.434045830 +0200
+@@ -1 +1,2 @@
+ obj-$(CONFIG_RESET_CONTROLLER) += core.o
++obj-$(CONFIG_RESET_GPIO) += gpio-reset.o
+diff -Nur linux-3.10.30.orig/drivers/rtc/class.c linux-linaro-stable-mx6/drivers/rtc/class.c
+--- linux-3.10.30.orig/drivers/rtc/class.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/rtc/class.c 2014-05-15 20:34:02.442045887 +0200
+@@ -14,6 +14,7 @@
+ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+ #include <linux/module.h>
++#include <linux/of.h>
+ #include <linux/rtc.h>
+ #include <linux/kdev_t.h>
+ #include <linux/idr.h>
+@@ -38,7 +39,7 @@
+ int rtc_hctosys_ret = -ENODEV;
+ #endif
+
+-#if defined(CONFIG_PM) && defined(CONFIG_RTC_HCTOSYS_DEVICE)
++#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_RTC_HCTOSYS_DEVICE)
+ /*
+ * On suspend(), measure the delta between one RTC and the
+ * system's wall clock; restore it on resume().
+@@ -47,7 +48,7 @@
+ static struct timespec old_rtc, old_system, old_delta;
+
+
+-static int rtc_suspend(struct device *dev, pm_message_t mesg)
++static int rtc_suspend(struct device *dev)
+ {
+ struct rtc_device *rtc = to_rtc_device(dev);
+ struct rtc_time tm;
+@@ -135,9 +136,10 @@
+ return 0;
+ }
+
++static SIMPLE_DEV_PM_OPS(rtc_class_dev_pm_ops, rtc_suspend, rtc_resume);
++#define RTC_CLASS_DEV_PM_OPS (&rtc_class_dev_pm_ops)
+ #else
+-#define rtc_suspend NULL
+-#define rtc_resume NULL
++#define RTC_CLASS_DEV_PM_OPS NULL
+ #endif
+
+
+@@ -156,12 +158,27 @@
+ {
+ struct rtc_device *rtc;
+ struct rtc_wkalrm alrm;
+- int id, err;
++ int of_id = -1, id = -1, err;
++
++ if (dev->of_node)
++ of_id = of_alias_get_id(dev->of_node, "rtc");
++ else if (dev->parent && dev->parent->of_node)
++ of_id = of_alias_get_id(dev->parent->of_node, "rtc");
++
++ if (of_id >= 0) {
++ id = ida_simple_get(&rtc_ida, of_id, of_id + 1,
++ GFP_KERNEL);
++ if (id < 0)
++ dev_warn(dev, "/aliases ID %d not available\n",
++ of_id);
++ }
+
+- id = ida_simple_get(&rtc_ida, 0, 0, GFP_KERNEL);
+ if (id < 0) {
+- err = id;
+- goto exit;
++ id = ida_simple_get(&rtc_ida, 0, 0, GFP_KERNEL);
++ if (id < 0) {
++ err = id;
++ goto exit;
++ }
+ }
+
+ rtc = kzalloc(sizeof(struct rtc_device), GFP_KERNEL);
+@@ -336,8 +353,7 @@
+ pr_err("couldn't create class\n");
+ return PTR_ERR(rtc_class);
+ }
+- rtc_class->suspend = rtc_suspend;
+- rtc_class->resume = rtc_resume;
++ rtc_class->pm = RTC_CLASS_DEV_PM_OPS;
+ rtc_dev_init();
+ rtc_sysfs_init(rtc_class);
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/rtc/interface.c linux-linaro-stable-mx6/drivers/rtc/interface.c
+--- linux-3.10.30.orig/drivers/rtc/interface.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/rtc/interface.c 2014-05-15 20:34:02.442045887 +0200
+@@ -109,9 +109,9 @@
+ err = rtc->ops->set_time(rtc->dev.parent,
+ &new);
+ }
+- }
+- else
++ } else {
+ err = -EINVAL;
++ }
+
+ mutex_unlock(&rtc->ops_lock);
+ /* A timer might have just expired */
+@@ -367,14 +367,14 @@
+ err = mutex_lock_interruptible(&rtc->ops_lock);
+ if (err)
+ return err;
+- if (rtc->aie_timer.enabled) {
++ if (rtc->aie_timer.enabled)
+ rtc_timer_remove(rtc, &rtc->aie_timer);
+- }
++
+ rtc->aie_timer.node.expires = rtc_tm_to_ktime(alarm->time);
+ rtc->aie_timer.period = ktime_set(0, 0);
+- if (alarm->enabled) {
++ if (alarm->enabled)
+ err = rtc_timer_enqueue(rtc, &rtc->aie_timer);
+- }
++
+ mutex_unlock(&rtc->ops_lock);
+ return err;
+ }
+@@ -698,9 +698,9 @@
+ spin_lock_irqsave(&rtc->irq_task_lock, flags);
+ if (rtc->irq_task != NULL && task == NULL)
+ err = -EBUSY;
+- if (rtc->irq_task != task)
++ else if (rtc->irq_task != task)
+ err = -EACCES;
+- if (!err) {
++ else {
+ if (rtc_update_hrtimer(rtc, enabled) < 0) {
+ spin_unlock_irqrestore(&rtc->irq_task_lock, flags);
+ cpu_relax();
+@@ -734,9 +734,9 @@
+ spin_lock_irqsave(&rtc->irq_task_lock, flags);
+ if (rtc->irq_task != NULL && task == NULL)
+ err = -EBUSY;
+- if (rtc->irq_task != task)
++ else if (rtc->irq_task != task)
+ err = -EACCES;
+- if (!err) {
++ else {
+ rtc->irq_freq = freq;
+ if (rtc->pie_enabled && rtc_update_hrtimer(rtc, 1) < 0) {
+ spin_unlock_irqrestore(&rtc->irq_task_lock, flags);
+@@ -891,7 +891,7 @@
+ *
+ * Kernel interface to initializing an rtc_timer.
+ */
+-void rtc_timer_init(struct rtc_timer *timer, void (*f)(void* p), void* data)
++void rtc_timer_init(struct rtc_timer *timer, void (*f)(void *p), void *data)
+ {
+ timerqueue_init(&timer->node);
+ timer->enabled = 0;
+@@ -907,7 +907,7 @@
+ *
+ * Kernel interface to set an rtc_timer
+ */
+-int rtc_timer_start(struct rtc_device *rtc, struct rtc_timer* timer,
++int rtc_timer_start(struct rtc_device *rtc, struct rtc_timer *timer,
+ ktime_t expires, ktime_t period)
+ {
+ int ret = 0;
+@@ -930,7 +930,7 @@
+ *
+ * Kernel interface to cancel an rtc_timer
+ */
+-int rtc_timer_cancel(struct rtc_device *rtc, struct rtc_timer* timer)
++int rtc_timer_cancel(struct rtc_device *rtc, struct rtc_timer *timer)
+ {
+ int ret = 0;
+ mutex_lock(&rtc->ops_lock);
+diff -Nur linux-3.10.30.orig/drivers/rtc/rtc-pcf8523.c linux-linaro-stable-mx6/drivers/rtc/rtc-pcf8523.c
+--- linux-3.10.30.orig/drivers/rtc/rtc-pcf8523.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/rtc/rtc-pcf8523.c 2014-05-15 20:34:02.626047213 +0200
+@@ -7,6 +7,7 @@
+ */
+
+ #include <linux/bcd.h>
++#include <linux/delay.h>
+ #include <linux/i2c.h>
+ #include <linux/module.h>
+ #include <linux/rtc.h>
+@@ -82,24 +83,85 @@
+ return 0;
+ }
+
+-static int pcf8523_select_capacitance(struct i2c_client *client, bool high)
++static int pcf8523_rtc_check_oscillator(struct i2c_client *client)
+ {
+ u8 value;
+ int err;
+
+- err = pcf8523_read(client, REG_CONTROL1, &value);
++ err = pcf8523_read(client, REG_SECONDS, &value);
+ if (err < 0)
+ return err;
+
+- if (!high)
+- value &= ~REG_CONTROL1_CAP_SEL;
+- else
+- value |= REG_CONTROL1_CAP_SEL;
++ if (value & REG_SECONDS_OS) {
++ /*
++ * If the oscillator was stopped, try to clear the flag. Upon
++ * power-up the flag is always set, but if we cannot clear it
++ * the oscillator isn't running properly for some reason. The
++ * sensible thing therefore is to return an error, signalling
++ * that the clock cannot be assumed to be correct.
++ */
++
++ value &= ~REG_SECONDS_OS;
++
++ err = pcf8523_write(client, REG_SECONDS, value);
++ if (err < 0)
++ return err;
++
++ err = pcf8523_read(client, REG_SECONDS, &value);
++ if (err < 0)
++ return err;
++
++ if (value & REG_SECONDS_OS)
++ return -EAGAIN;
++ }
++
++ return 0;
++}
++
++static int pcf8523_switch_capacitance(struct i2c_client *client)
++{
++ u8 value;
++ int err;
++
++ err = pcf8523_read(client, REG_CONTROL1, &value);
++ if (err < 0)
++ goto out;
++
++ value ^= REG_CONTROL1_CAP_SEL;
+
+ err = pcf8523_write(client, REG_CONTROL1, value);
++
++out:
++ return err;
++}
++
++static int pcf8523_enable_oscillator(struct i2c_client *client)
++{
++ int err, loop;
++
++ loop = 0;
++ while (loop < 200) {
++ err = pcf8523_rtc_check_oscillator(client);
++ if (!err)
++ return 0;
++ loop++;
++ msleep(10);
++ }
++
++ err = pcf8523_switch_capacitance(client);
+ if (err < 0)
+- return err;
++ goto out;
+
++ loop = 0;
++ while (loop < 200) {
++ err = pcf8523_rtc_check_oscillator(client);
++ if (!err)
++ return 0;
++ loop++;
++ msleep(10);
++ }
++
++out:
+ return err;
+ }
+
+@@ -290,6 +352,7 @@
+ const struct i2c_device_id *id)
+ {
+ struct pcf8523 *pcf;
++ u8 value;
+ int err;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
+@@ -299,10 +362,20 @@
+ if (!pcf)
+ return -ENOMEM;
+
+- err = pcf8523_select_capacitance(client, true);
++ /* Check whether the RTC reports battery low */
++ err = pcf8523_read(client, REG_CONTROL3, &value);
+ if (err < 0)
+ return err;
+
++ if (value & REG_CONTROL3_BLF)
++ dev_warn(&client->dev, "RTC reports battery is low\n");
++
++ err = pcf8523_enable_oscillator(client);
++ if (err < 0) {
++ dev_warn(&client->dev, "RTC reports oscillator is not running\n");
++ return err;
++ }
++
+ err = pcf8523_set_pm(client, 0);
+ if (err < 0)
+ return err;
+@@ -317,11 +390,6 @@
+ return 0;
+ }
+
+-static int pcf8523_remove(struct i2c_client *client)
+-{
+- return 0;
+-}
+-
+ static const struct i2c_device_id pcf8523_id[] = {
+ { "pcf8523", 0 },
+ { }
+@@ -343,7 +411,6 @@
+ .of_match_table = of_match_ptr(pcf8523_of_match),
+ },
+ .probe = pcf8523_probe,
+- .remove = pcf8523_remove,
+ .id_table = pcf8523_id,
+ };
+ module_i2c_driver(pcf8523_driver);
+diff -Nur linux-3.10.30.orig/drivers/rtc/rtc-snvs.c linux-linaro-stable-mx6/drivers/rtc/rtc-snvs.c
+--- linux-3.10.30.orig/drivers/rtc/rtc-snvs.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/rtc/rtc-snvs.c 2014-05-15 20:34:02.634047270 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+@@ -41,6 +41,8 @@
+ spinlock_t lock;
+ };
+
++static void __iomem *snvs_base;
++
+ static u32 rtc_read_lp_counter(void __iomem *ioaddr)
+ {
+ u64 read1, read2;
+@@ -241,6 +243,15 @@
+ return events ? IRQ_HANDLED : IRQ_NONE;
+ }
+
++static void snvs_poweroff(void)
++{
++ u32 value;
++
++ value = readl(snvs_base + SNVS_LPCR);
++ /* set TOP and DP_EN bit */
++ writel(value | 0x60, snvs_base + SNVS_LPCR);
++}
++
+ static int snvs_rtc_probe(struct platform_device *pdev)
+ {
+ struct snvs_rtc_data *data;
+@@ -270,13 +281,15 @@
+ /* Clear interrupt status */
+ writel(0xffffffff, data->ioaddr + SNVS_LPSR);
+
++ snvs_base = data->ioaddr;
+ /* Enable RTC */
+ snvs_rtc_enable(data, true);
+
+ device_init_wakeup(&pdev->dev, true);
+
+ ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
+- IRQF_SHARED, "rtc alarm", &pdev->dev);
++ IRQF_SHARED | IRQF_NO_SUSPEND,
++ "rtc alarm", &pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request irq %d: %d\n",
+ data->irq, ret);
+@@ -290,6 +303,12 @@
+ dev_err(&pdev->dev, "failed to register rtc: %d\n", ret);
+ return ret;
+ }
++ /*
++ * if no specific power off function in board file, power off system by
++ * SNVS
++ */
++ if (!pm_power_off)
++ pm_power_off = snvs_poweroff;
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-altera.c linux-linaro-stable-mx6/drivers/spi/spi-altera.c
+--- linux-3.10.30.orig/drivers/spi/spi-altera.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-altera.c 2014-05-15 20:34:04.810062949 +0200
+@@ -103,16 +103,6 @@
+ }
+ }
+
+-static int altera_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
+-{
+- return 0;
+-}
+-
+-static int altera_spi_setup(struct spi_device *spi)
+-{
+- return 0;
+-}
+-
+ static inline unsigned int hw_txbyte(struct altera_spi *hw, int count)
+ {
+ if (hw->tx) {
+@@ -231,16 +221,14 @@
+ master->bus_num = pdev->id;
+ master->num_chipselect = 16;
+ master->mode_bits = SPI_CS_HIGH;
+- master->setup = altera_spi_setup;
+
+ hw = spi_master_get_devdata(master);
+ platform_set_drvdata(pdev, hw);
+
+ /* setup the state for the bitbang driver */
+- hw->bitbang.master = spi_master_get(master);
++ hw->bitbang.master = master;
+ if (!hw->bitbang.master)
+ return err;
+- hw->bitbang.setup_transfer = altera_spi_setupxfer;
+ hw->bitbang.chipselect = altera_spi_chipsel;
+ hw->bitbang.txrx_bufs = altera_spi_txrx;
+
+@@ -285,7 +273,6 @@
+ exit_busy:
+ err = -EBUSY;
+ exit:
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+ return err;
+ }
+@@ -296,7 +283,6 @@
+ struct spi_master *master = hw->bitbang.master;
+
+ spi_bitbang_stop(&hw->bitbang);
+- platform_set_drvdata(dev, NULL);
+ spi_master_put(master);
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-ath79.c linux-linaro-stable-mx6/drivers/spi/spi-ath79.c
+--- linux-3.10.30.orig/drivers/spi/spi-ath79.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-ath79.c 2014-05-15 20:34:04.810062949 +0200
+@@ -155,9 +155,6 @@
+ {
+ int status = 0;
+
+- if (spi->bits_per_word > 32)
+- return -EINVAL;
+-
+ if (!spi->controller_state) {
+ status = ath79_spi_setup_cs(spi);
+ if (status)
+@@ -226,6 +223,7 @@
+
+ pdata = pdev->dev.platform_data;
+
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
+ master->setup = ath79_spi_setup;
+ master->cleanup = ath79_spi_cleanup;
+ if (pdata) {
+@@ -233,7 +231,7 @@
+ master->num_chipselect = pdata->num_chipselect;
+ }
+
+- sp->bitbang.master = spi_master_get(master);
++ sp->bitbang.master = master;
+ sp->bitbang.chipselect = ath79_spi_chipselect;
+ sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
+@@ -287,7 +285,6 @@
+ err_unmap:
+ iounmap(sp->base);
+ err_put_master:
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(sp->bitbang.master);
+
+ return ret;
+@@ -302,7 +299,6 @@
+ clk_disable(sp->clk);
+ clk_put(sp->clk);
+ iounmap(sp->base);
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(sp->bitbang.master);
+
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-atmel.c linux-linaro-stable-mx6/drivers/spi/spi-atmel.c
+--- linux-3.10.30.orig/drivers/spi/spi-atmel.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-atmel.c 2014-05-15 20:34:04.814062977 +0200
+@@ -1268,13 +1268,6 @@
+ return -EINVAL;
+ }
+
+- if (bits < 8 || bits > 16) {
+- dev_dbg(&spi->dev,
+- "setup: invalid bits_per_word %u (8 to 16)\n",
+- bits);
+- return -EINVAL;
+- }
+-
+ /* see notes above re chipselect */
+ if (!atmel_spi_is_v2(as)
+ && spi->chip_select == 0
+@@ -1515,7 +1508,7 @@
+
+ /* the spi->mode bits understood by this driver: */
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+-
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
+ master->dev.of_node = pdev->dev.of_node;
+ master->bus_num = pdev->id;
+ master->num_chipselect = master->dev.of_node ? 0 : 4;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-au1550.c linux-linaro-stable-mx6/drivers/spi/spi-au1550.c
+--- linux-3.10.30.orig/drivers/spi/spi-au1550.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-au1550.c 2014-05-15 20:34:04.814062977 +0200
+@@ -248,11 +248,6 @@
+ hz = t->speed_hz;
+ }
+
+- if (bpw < 4 || bpw > 24) {
+- dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
+- bpw);
+- return -EINVAL;
+- }
+ if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
+ dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
+ hz);
+@@ -296,12 +291,6 @@
+ {
+ struct au1550_spi *hw = spi_master_get_devdata(spi->master);
+
+- if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
+- dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
+- spi->bits_per_word);
+- return -EINVAL;
+- }
+-
+ if (spi->max_speed_hz == 0)
+ spi->max_speed_hz = hw->freq_max;
+ if (spi->max_speed_hz > hw->freq_max
+@@ -782,6 +771,7 @@
+
+ /* the spi->mode bits understood by this driver: */
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 24);
+
+ hw = spi_master_get_devdata(master);
+
+@@ -987,8 +977,6 @@
+ au1xxx_dbdma_chan_free(hw->dma_tx_ch);
+ }
+
+- platform_set_drvdata(pdev, NULL);
+-
+ spi_master_put(hw->master);
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-bcm63xx.c linux-linaro-stable-mx6/drivers/spi/spi-bcm63xx.c
+--- linux-3.10.30.orig/drivers/spi/spi-bcm63xx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-bcm63xx.c 2014-05-15 20:34:04.814062977 +0200
+@@ -124,17 +124,6 @@
+ /* the spi->mode bits understood by this driver: */
+ #define MODEBITS (SPI_CPOL | SPI_CPHA)
+
+-static int bcm63xx_spi_setup(struct spi_device *spi)
+-{
+- if (spi->bits_per_word != 8) {
+- dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+- __func__, spi->bits_per_word);
+- return -EINVAL;
+- }
+-
+- return 0;
+-}
+-
+ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
+ unsigned int num_transfers)
+ {
+@@ -275,13 +264,6 @@
+ * full-duplex transfers.
+ */
+ list_for_each_entry(t, &m->transfers, transfer_list) {
+- if (t->bits_per_word != 8) {
+- dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
+- __func__, t->bits_per_word);
+- status = -EINVAL;
+- goto exit;
+- }
+-
+ if (!first)
+ first = t;
+
+@@ -428,11 +410,11 @@
+
+ master->bus_num = pdata->bus_num;
+ master->num_chipselect = pdata->num_chipselect;
+- master->setup = bcm63xx_spi_setup;
+ master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
+ master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
+ master->transfer_one_message = bcm63xx_spi_transfer_one;
+ master->mode_bits = MODEBITS;
++ master->bits_per_word_mask = SPI_BPW_MASK(8);
+ bs->msg_type_shift = pdata->msg_type_shift;
+ bs->msg_ctl_width = pdata->msg_ctl_width;
+ bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
+@@ -467,7 +449,6 @@
+ out_clk_disable:
+ clk_disable_unprepare(clk);
+ out_err:
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+ out_clk:
+ clk_put(clk);
+@@ -489,8 +470,6 @@
+ clk_disable_unprepare(bs->clk);
+ clk_put(bs->clk);
+
+- platform_set_drvdata(pdev, 0);
+-
+ spi_master_put(master);
+
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-bfin5xx.c linux-linaro-stable-mx6/drivers/spi/spi-bfin5xx.c
+--- linux-3.10.30.orig/drivers/spi/spi-bfin5xx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-bfin5xx.c 2014-05-15 20:34:04.814062977 +0200
+@@ -643,21 +643,16 @@
+
+ /* Bits per word setup */
+ bits_per_word = transfer->bits_per_word;
+- if (bits_per_word % 16 == 0) {
++ if (bits_per_word == 16) {
+ drv_data->n_bytes = bits_per_word/8;
+ drv_data->len = (transfer->len) >> 1;
+ cr_width = BIT_CTL_WORDSIZE;
+ drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
+- } else if (bits_per_word % 8 == 0) {
++ } else if (bits_per_word == 8) {
+ drv_data->n_bytes = bits_per_word/8;
+ drv_data->len = transfer->len;
+ cr_width = 0;
+ drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
+- } else {
+- dev_err(&drv_data->pdev->dev, "transfer: unsupported bits_per_word\n");
+- message->status = -EINVAL;
+- bfin_spi_giveback(drv_data);
+- return;
+ }
+ cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
+ cr |= cr_width;
+@@ -808,13 +803,13 @@
+ bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
+ else {
+ int loop;
+- if (bits_per_word % 16 == 0) {
++ if (bits_per_word == 16) {
+ u16 *buf = (u16 *)drv_data->tx;
+ for (loop = 0; loop < bits_per_word / 16;
+ loop++) {
+ bfin_write(&drv_data->regs->tdbr, *buf++);
+ }
+- } else if (bits_per_word % 8 == 0) {
++ } else if (bits_per_word == 8) {
+ u8 *buf = (u8 *)drv_data->tx;
+ for (loop = 0; loop < bits_per_word / 8; loop++)
+ bfin_write(&drv_data->regs->tdbr, *buf++);
+@@ -1033,12 +1028,6 @@
+ chip->ctl_reg &= bfin_ctl_reg;
+ }
+
+- if (spi->bits_per_word % 8) {
+- dev_err(&spi->dev, "%d bits_per_word is not supported\n",
+- spi->bits_per_word);
+- goto error;
+- }
+-
+ /* translate common spi framework into our register */
+ if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
+ dev_err(&spi->dev, "unsupported spi modes detected\n");
+@@ -1299,7 +1288,7 @@
+
+ /* the spi->mode bits supported by this driver: */
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
+-
++ master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bus_num = pdev->id;
+ master->num_chipselect = platform_info->num_chipselect;
+ master->cleanup = bfin_spi_cleanup;
+@@ -1418,9 +1407,6 @@
+
+ peripheral_free_list(drv_data->pin_req);
+
+- /* Prevent double remove */
+- platform_set_drvdata(pdev, NULL);
+-
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-bfin-sport.c linux-linaro-stable-mx6/drivers/spi/spi-bfin-sport.c
+--- linux-3.10.30.orig/drivers/spi/spi-bfin-sport.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-bfin-sport.c 2014-05-15 20:34:04.814062977 +0200
+@@ -417,7 +417,7 @@
+
+ /* Bits per word setup */
+ bits_per_word = transfer->bits_per_word;
+- if (bits_per_word % 16 == 0)
++ if (bits_per_word == 16)
+ drv_data->ops = &bfin_sport_transfer_ops_u16;
+ else
+ drv_data->ops = &bfin_sport_transfer_ops_u8;
+@@ -600,13 +600,6 @@
+ }
+ }
+
+- if (spi->bits_per_word % 8) {
+- dev_err(&spi->dev, "%d bits_per_word is not supported\n",
+- spi->bits_per_word);
+- ret = -EINVAL;
+- goto error;
+- }
+-
+ /* translate common spi framework into our register
+ * following configure contents are same for tx and rx.
+ */
+@@ -778,6 +771,7 @@
+ drv_data->pin_req = platform_info->pin_req;
+
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
++ master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bus_num = pdev->id;
+ master->num_chipselect = platform_info->num_chipselect;
+ master->cleanup = bfin_sport_spi_cleanup;
+@@ -882,9 +876,6 @@
+
+ peripheral_free_list(drv_data->pin_req);
+
+- /* Prevent double remove */
+- platform_set_drvdata(pdev, NULL);
+-
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-bitbang.c linux-linaro-stable-mx6/drivers/spi/spi-bitbang.c
+--- linux-3.10.30.orig/drivers/spi/spi-bitbang.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-bitbang.c 2014-05-15 20:34:04.814062977 +0200
+@@ -40,7 +40,7 @@
+ * to glue code. These bitbang setup() and cleanup() routines are always
+ * used, though maybe they're called from controller-aware code.
+ *
+- * chipselect() and friends may use use spi_device->controller_data and
++ * chipselect() and friends may use spi_device->controller_data and
+ * controller registers as appropriate.
+ *
+ *
+@@ -191,7 +191,7 @@
+ bitbang = spi_master_get_devdata(spi->master);
+
+ if (!cs) {
+- cs = kzalloc(sizeof *cs, GFP_KERNEL);
++ cs = kzalloc(sizeof(*cs), GFP_KERNEL);
+ if (!cs)
+ return -ENOMEM;
+ spi->controller_state = cs;
+@@ -255,150 +255,141 @@
+ * Drivers can provide word-at-a-time i/o primitives, or provide
+ * transfer-at-a-time ones to leverage dma or fifo hardware.
+ */
+-static void bitbang_work(struct work_struct *work)
++
++static int spi_bitbang_prepare_hardware(struct spi_master *spi)
+ {
+- struct spi_bitbang *bitbang =
+- container_of(work, struct spi_bitbang, work);
++ struct spi_bitbang *bitbang;
+ unsigned long flags;
+- struct spi_message *m, *_m;
++
++ bitbang = spi_master_get_devdata(spi);
+
+ spin_lock_irqsave(&bitbang->lock, flags);
+ bitbang->busy = 1;
+- list_for_each_entry_safe(m, _m, &bitbang->queue, queue) {
+- struct spi_device *spi;
+- unsigned nsecs;
+- struct spi_transfer *t = NULL;
+- unsigned tmp;
+- unsigned cs_change;
+- int status;
+- int do_setup = -1;
+-
+- list_del(&m->queue);
+- spin_unlock_irqrestore(&bitbang->lock, flags);
+-
+- /* FIXME this is made-up ... the correct value is known to
+- * word-at-a-time bitbang code, and presumably chipselect()
+- * should enforce these requirements too?
+- */
+- nsecs = 100;
++ spin_unlock_irqrestore(&bitbang->lock, flags);
+
+- spi = m->spi;
+- tmp = 0;
+- cs_change = 1;
+- status = 0;
++ return 0;
++}
+
+- list_for_each_entry (t, &m->transfers, transfer_list) {
++static int spi_bitbang_transfer_one(struct spi_master *master,
++ struct spi_message *m)
++{
++ struct spi_bitbang *bitbang;
++ unsigned nsecs;
++ struct spi_transfer *t = NULL;
++ unsigned cs_change;
++ int status;
++ int do_setup = -1;
++ struct spi_device *spi = m->spi;
++
++ bitbang = spi_master_get_devdata(master);
++
++ /* FIXME this is made-up ... the correct value is known to
++ * word-at-a-time bitbang code, and presumably chipselect()
++ * should enforce these requirements too?
++ */
++ nsecs = 100;
+
+- /* override speed or wordsize? */
+- if (t->speed_hz || t->bits_per_word)
+- do_setup = 1;
+-
+- /* init (-1) or override (1) transfer params */
+- if (do_setup != 0) {
+- status = bitbang->setup_transfer(spi, t);
+- if (status < 0)
+- break;
+- if (do_setup == -1)
+- do_setup = 0;
+- }
+-
+- /* set up default clock polarity, and activate chip;
+- * this implicitly updates clock and spi modes as
+- * previously recorded for this device via setup().
+- * (and also deselects any other chip that might be
+- * selected ...)
+- */
+- if (cs_change) {
+- bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
+- ndelay(nsecs);
+- }
+- cs_change = t->cs_change;
+- if (!t->tx_buf && !t->rx_buf && t->len) {
+- status = -EINVAL;
+- break;
+- }
++ cs_change = 1;
++ status = 0;
+
+- /* transfer data. the lower level code handles any
+- * new dma mappings it needs. our caller always gave
+- * us dma-safe buffers.
+- */
+- if (t->len) {
+- /* REVISIT dma API still needs a designated
+- * DMA_ADDR_INVALID; ~0 might be better.
+- */
+- if (!m->is_dma_mapped)
+- t->rx_dma = t->tx_dma = 0;
+- status = bitbang->txrx_bufs(spi, t);
+- }
+- if (status > 0)
+- m->actual_length += status;
+- if (status != t->len) {
+- /* always report some kind of error */
+- if (status >= 0)
+- status = -EREMOTEIO;
+- break;
+- }
+- status = 0;
++ list_for_each_entry(t, &m->transfers, transfer_list) {
+
+- /* protocol tweaks before next transfer */
+- if (t->delay_usecs)
+- udelay(t->delay_usecs);
+-
+- if (cs_change && !list_is_last(&t->transfer_list, &m->transfers)) {
+- /* sometimes a short mid-message deselect of the chip
+- * may be needed to terminate a mode or command
+- */
+- ndelay(nsecs);
+- bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
+- ndelay(nsecs);
+- }
++ /* override speed or wordsize? */
++ if (t->speed_hz || t->bits_per_word)
++ do_setup = 1;
++
++ /* init (-1) or override (1) transfer params */
++ if (do_setup != 0) {
++ status = bitbang->setup_transfer(spi, t);
++ if (status < 0)
++ break;
++ if (do_setup == -1)
++ do_setup = 0;
+ }
+
+- m->status = status;
+- m->complete(m->context);
++ /* set up default clock polarity, and activate chip;
++ * this implicitly updates clock and spi modes as
++ * previously recorded for this device via setup().
++ * (and also deselects any other chip that might be
++ * selected ...)
++ */
++ if (cs_change) {
++ bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
++ ndelay(nsecs);
++ }
++ cs_change = t->cs_change;
++ if (!t->tx_buf && !t->rx_buf && t->len) {
++ status = -EINVAL;
++ break;
++ }
+
+- /* normally deactivate chipselect ... unless no error and
+- * cs_change has hinted that the next message will probably
+- * be for this chip too.
++ /* transfer data. the lower level code handles any
++ * new dma mappings it needs. our caller always gave
++ * us dma-safe buffers.
+ */
+- if (!(status == 0 && cs_change)) {
++ if (t->len) {
++ /* REVISIT dma API still needs a designated
++ * DMA_ADDR_INVALID; ~0 might be better.
++ */
++ if (!m->is_dma_mapped)
++ t->rx_dma = t->tx_dma = 0;
++ status = bitbang->txrx_bufs(spi, t);
++ }
++ if (status > 0)
++ m->actual_length += status;
++ if (status != t->len) {
++ /* always report some kind of error */
++ if (status >= 0)
++ status = -EREMOTEIO;
++ break;
++ }
++ status = 0;
++
++ /* protocol tweaks before next transfer */
++ if (t->delay_usecs)
++ udelay(t->delay_usecs);
++
++ if (cs_change &&
++ !list_is_last(&t->transfer_list, &m->transfers)) {
++ /* sometimes a short mid-message deselect of the chip
++ * may be needed to terminate a mode or command
++ */
+ ndelay(nsecs);
+ bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
+ ndelay(nsecs);
+ }
++ }
++
++ m->status = status;
+
+- spin_lock_irqsave(&bitbang->lock, flags);
++ /* normally deactivate chipselect ... unless no error and
++ * cs_change has hinted that the next message will probably
++ * be for this chip too.
++ */
++ if (!(status == 0 && cs_change)) {
++ ndelay(nsecs);
++ bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
++ ndelay(nsecs);
+ }
+- bitbang->busy = 0;
+- spin_unlock_irqrestore(&bitbang->lock, flags);
++
++ spi_finalize_current_message(master);
++
++ return status;
+ }
+
+-/**
+- * spi_bitbang_transfer - default submit to transfer queue
+- */
+-int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
++static int spi_bitbang_unprepare_hardware(struct spi_master *spi)
+ {
+ struct spi_bitbang *bitbang;
+ unsigned long flags;
+- int status = 0;
+-
+- m->actual_length = 0;
+- m->status = -EINPROGRESS;
+
+- bitbang = spi_master_get_devdata(spi->master);
++ bitbang = spi_master_get_devdata(spi);
+
+ spin_lock_irqsave(&bitbang->lock, flags);
+- if (!spi->max_speed_hz)
+- status = -ENETDOWN;
+- else {
+- list_add_tail(&m->queue, &bitbang->queue);
+- queue_work(bitbang->workqueue, &bitbang->work);
+- }
++ bitbang->busy = 0;
+ spin_unlock_irqrestore(&bitbang->lock, flags);
+
+- return status;
++ return 0;
+ }
+-EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
+
+ /*----------------------------------------------------------------------*/
+
+@@ -424,24 +415,32 @@
+ * This routine registers the spi_master, which will process requests in a
+ * dedicated task, keeping IRQs unblocked most of the time. To stop
+ * processing those requests, call spi_bitbang_stop().
++ *
++ * On success, this routine will take a reference to master. The caller is
++ * responsible for calling spi_bitbang_stop() to decrement the reference and
++ * spi_master_put() as counterpart of spi_alloc_master() to prevent a memory
++ * leak.
+ */
+ int spi_bitbang_start(struct spi_bitbang *bitbang)
+ {
+ struct spi_master *master = bitbang->master;
+- int status;
++ int ret;
+
+ if (!master || !bitbang->chipselect)
+ return -EINVAL;
+
+- INIT_WORK(&bitbang->work, bitbang_work);
+ spin_lock_init(&bitbang->lock);
+- INIT_LIST_HEAD(&bitbang->queue);
+
+ if (!master->mode_bits)
+ master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;
+
+- if (!master->transfer)
+- master->transfer = spi_bitbang_transfer;
++ if (master->transfer || master->transfer_one_message)
++ return -EINVAL;
++
++ master->prepare_transfer_hardware = spi_bitbang_prepare_hardware;
++ master->unprepare_transfer_hardware = spi_bitbang_unprepare_hardware;
++ master->transfer_one_message = spi_bitbang_transfer_one;
++
+ if (!bitbang->txrx_bufs) {
+ bitbang->use_dma = 0;
+ bitbang->txrx_bufs = spi_bitbang_bufs;
+@@ -452,34 +451,16 @@
+ master->setup = spi_bitbang_setup;
+ master->cleanup = spi_bitbang_cleanup;
+ }
+- } else if (!master->setup)
+- return -EINVAL;
+- if (master->transfer == spi_bitbang_transfer &&
+- !bitbang->setup_transfer)
+- return -EINVAL;
+-
+- /* this task is the only thing to touch the SPI bits */
+- bitbang->busy = 0;
+- bitbang->workqueue = create_singlethread_workqueue(
+- dev_name(master->dev.parent));
+- if (bitbang->workqueue == NULL) {
+- status = -EBUSY;
+- goto err1;
+ }
+
+ /* driver may get busy before register() returns, especially
+ * if someone registered boardinfo for devices
+ */
+- status = spi_register_master(master);
+- if (status < 0)
+- goto err2;
+-
+- return status;
++ ret = spi_register_master(spi_master_get(master));
++ if (ret)
++ spi_master_put(master);
+
+-err2:
+- destroy_workqueue(bitbang->workqueue);
+-err1:
+- return status;
++ return 0;
+ }
+ EXPORT_SYMBOL_GPL(spi_bitbang_start);
+
+@@ -490,10 +471,6 @@
+ {
+ spi_unregister_master(bitbang->master);
+
+- WARN_ON(!list_empty(&bitbang->queue));
+-
+- destroy_workqueue(bitbang->workqueue);
+-
+ return 0;
+ }
+ EXPORT_SYMBOL_GPL(spi_bitbang_stop);
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-butterfly.c linux-linaro-stable-mx6/drivers/spi/spi-butterfly.c
+--- linux-3.10.30.orig/drivers/spi/spi-butterfly.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-butterfly.c 2014-05-15 20:34:04.814062977 +0200
+@@ -225,7 +225,7 @@
+ master->bus_num = 42;
+ master->num_chipselect = 2;
+
+- pp->bitbang.master = spi_master_get(master);
++ pp->bitbang.master = master;
+ pp->bitbang.chipselect = butterfly_chipselect;
+ pp->bitbang.txrx_word[SPI_MODE_0] = butterfly_txrx_word_mode0;
+
+diff -Nur linux-3.10.30.orig/drivers/spi/spi.c linux-linaro-stable-mx6/drivers/spi/spi.c
+--- linux-3.10.30.orig/drivers/spi/spi.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi.c 2014-05-15 20:34:04.982064187 +0200
+@@ -39,6 +39,9 @@
+ #include <linux/ioport.h>
+ #include <linux/acpi.h>
+
++#define CREATE_TRACE_POINTS
++#include <trace/events/spi.h>
++
+ static void spidev_release(struct device *dev)
+ {
+ struct spi_device *spi = to_spi_device(dev);
+@@ -58,11 +61,13 @@
+
+ return sprintf(buf, "%s%s\n", SPI_MODULE_PREFIX, spi->modalias);
+ }
++static DEVICE_ATTR_RO(modalias);
+
+-static struct device_attribute spi_dev_attrs[] = {
+- __ATTR_RO(modalias),
+- __ATTR_NULL,
++static struct attribute *spi_dev_attrs[] = {
++ &dev_attr_modalias.attr,
++ NULL,
+ };
++ATTRIBUTE_GROUPS(spi_dev);
+
+ /* modalias support makes "modprobe $MODALIAS" new-style hotplug work,
+ * and the sysfs version makes coldplug work too.
+@@ -229,7 +234,7 @@
+
+ struct bus_type spi_bus_type = {
+ .name = "spi",
+- .dev_attrs = spi_dev_attrs,
++ .dev_groups = spi_dev_groups,
+ .match = spi_match_device,
+ .uevent = spi_uevent,
+ .pm = &spi_pm,
+@@ -240,15 +245,27 @@
+ static int spi_drv_probe(struct device *dev)
+ {
+ const struct spi_driver *sdrv = to_spi_driver(dev->driver);
++ struct spi_device *spi = to_spi_device(dev);
++ int ret;
++
++ acpi_dev_pm_attach(&spi->dev, true);
++ ret = sdrv->probe(spi);
++ if (ret)
++ acpi_dev_pm_detach(&spi->dev, true);
+
+- return sdrv->probe(to_spi_device(dev));
++ return ret;
+ }
+
+ static int spi_drv_remove(struct device *dev)
+ {
+ const struct spi_driver *sdrv = to_spi_driver(dev->driver);
++ struct spi_device *spi = to_spi_device(dev);
++ int ret;
+
+- return sdrv->remove(to_spi_device(dev));
++ ret = sdrv->remove(spi);
++ acpi_dev_pm_detach(&spi->dev, true);
++
++ return ret;
+ }
+
+ static void spi_drv_shutdown(struct device *dev)
+@@ -323,7 +340,7 @@
+ if (!spi_master_get(master))
+ return NULL;
+
+- spi = kzalloc(sizeof *spi, GFP_KERNEL);
++ spi = kzalloc(sizeof(*spi), GFP_KERNEL);
+ if (!spi) {
+ dev_err(dev, "cannot alloc spi_device\n");
+ spi_master_put(master);
+@@ -523,6 +540,95 @@
+
+ /*-------------------------------------------------------------------------*/
+
++static void spi_set_cs(struct spi_device *spi, bool enable)
++{
++ if (spi->mode & SPI_CS_HIGH)
++ enable = !enable;
++
++ if (spi->cs_gpio >= 0)
++ gpio_set_value(spi->cs_gpio, !enable);
++ else if (spi->master->set_cs)
++ spi->master->set_cs(spi, !enable);
++}
++
++/*
++ * spi_transfer_one_message - Default implementation of transfer_one_message()
++ *
++ * This is a standard implementation of transfer_one_message() for
++ * drivers which impelment a transfer_one() operation. It provides
++ * standard handling of delays and chip select management.
++ */
++static int spi_transfer_one_message(struct spi_master *master,
++ struct spi_message *msg)
++{
++ struct spi_transfer *xfer;
++ bool cur_cs = true;
++ bool keep_cs = false;
++ int ret = 0;
++
++ spi_set_cs(msg->spi, true);
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ trace_spi_transfer_start(msg, xfer);
++
++ INIT_COMPLETION(master->xfer_completion);
++
++ ret = master->transfer_one(master, msg->spi, xfer);
++ if (ret < 0) {
++ dev_err(&msg->spi->dev,
++ "SPI transfer failed: %d\n", ret);
++ goto out;
++ }
++
++ if (ret > 0)
++ wait_for_completion(&master->xfer_completion);
++
++ trace_spi_transfer_stop(msg, xfer);
++
++ if (msg->status != -EINPROGRESS)
++ goto out;
++
++ if (xfer->delay_usecs)
++ udelay(xfer->delay_usecs);
++
++ if (xfer->cs_change) {
++ if (list_is_last(&xfer->transfer_list,
++ &msg->transfers)) {
++ keep_cs = true;
++ } else {
++ cur_cs = !cur_cs;
++ spi_set_cs(msg->spi, cur_cs);
++ }
++ }
++
++ msg->actual_length += xfer->len;
++ }
++
++out:
++ if (ret != 0 || !keep_cs)
++ spi_set_cs(msg->spi, false);
++
++ if (msg->status == -EINPROGRESS)
++ msg->status = ret;
++
++ spi_finalize_current_message(master);
++
++ return ret;
++}
++
++/**
++ * spi_finalize_current_transfer - report completion of a transfer
++ *
++ * Called by SPI drivers using the core transfer_one_message()
++ * implementation to notify it that the current interrupt driven
++ * transfer has finised and the next one may be scheduled.
++ */
++void spi_finalize_current_transfer(struct spi_master *master)
++{
++ complete(&master->xfer_completion);
++}
++EXPORT_SYMBOL_GPL(spi_finalize_current_transfer);
++
+ /**
+ * spi_pump_messages - kthread work function which processes spi message queue
+ * @work: pointer to kthread work struct contained in the master struct
+@@ -553,6 +659,11 @@
+ master->unprepare_transfer_hardware(master))
+ dev_err(&master->dev,
+ "failed to unprepare transfer hardware\n");
++ if (master->auto_runtime_pm) {
++ pm_runtime_mark_last_busy(master->dev.parent);
++ pm_runtime_put_autosuspend(master->dev.parent);
++ }
++ trace_spi_master_idle(master);
+ return;
+ }
+
+@@ -572,13 +683,42 @@
+ master->busy = true;
+ spin_unlock_irqrestore(&master->queue_lock, flags);
+
++ if (!was_busy && master->auto_runtime_pm) {
++ ret = pm_runtime_get_sync(master->dev.parent);
++ if (ret < 0) {
++ dev_err(&master->dev, "Failed to power device: %d\n",
++ ret);
++ return;
++ }
++ }
++
++ if (!was_busy)
++ trace_spi_master_busy(master);
++
+ if (!was_busy && master->prepare_transfer_hardware) {
+ ret = master->prepare_transfer_hardware(master);
+ if (ret) {
+ dev_err(&master->dev,
+ "failed to prepare transfer hardware\n");
++
++ if (master->auto_runtime_pm)
++ pm_runtime_put(master->dev.parent);
++ return;
++ }
++ }
++
++ trace_spi_message_start(master->cur_msg);
++
++ if (master->prepare_message) {
++ ret = master->prepare_message(master, master->cur_msg);
++ if (ret) {
++ dev_err(&master->dev,
++ "failed to prepare message: %d\n", ret);
++ master->cur_msg->status = ret;
++ spi_finalize_current_message(master);
+ return;
+ }
++ master->cur_msg_prepared = true;
+ }
+
+ ret = master->transfer_one_message(master, master->cur_msg);
+@@ -664,6 +804,7 @@
+ {
+ struct spi_message *mesg;
+ unsigned long flags;
++ int ret;
+
+ spin_lock_irqsave(&master->queue_lock, flags);
+ mesg = master->cur_msg;
+@@ -672,9 +813,20 @@
+ queue_kthread_work(&master->kworker, &master->pump_messages);
+ spin_unlock_irqrestore(&master->queue_lock, flags);
+
++ if (master->cur_msg_prepared && master->unprepare_message) {
++ ret = master->unprepare_message(master, mesg);
++ if (ret) {
++ dev_err(&master->dev,
++ "failed to unprepare message: %d\n", ret);
++ }
++ }
++ master->cur_msg_prepared = false;
++
+ mesg->state = NULL;
+ if (mesg->complete)
+ mesg->complete(mesg->context);
++
++ trace_spi_message_done(mesg);
+ }
+ EXPORT_SYMBOL_GPL(spi_finalize_current_message);
+
+@@ -776,7 +928,7 @@
+ msg->status = -EINPROGRESS;
+
+ list_add_tail(&msg->queue, &master->queue);
+- if (master->running && !master->busy)
++ if (!master->busy)
+ queue_kthread_work(&master->kworker, &master->pump_messages);
+
+ spin_unlock_irqrestore(&master->queue_lock, flags);
+@@ -789,6 +941,8 @@
+
+ master->queued = true;
+ master->transfer = spi_queued_transfer;
++ if (!master->transfer_one_message)
++ master->transfer_one_message = spi_transfer_one_message;
+
+ /* Initialize and start queue */
+ ret = spi_init_queue(master);
+@@ -824,10 +978,8 @@
+ {
+ struct spi_device *spi;
+ struct device_node *nc;
+- const __be32 *prop;
+- char modalias[SPI_NAME_SIZE + 4];
+ int rc;
+- int len;
++ u32 value;
+
+ if (!master->dev.of_node)
+ return;
+@@ -852,14 +1004,14 @@
+ }
+
+ /* Device address */
+- prop = of_get_property(nc, "reg", &len);
+- if (!prop || len < sizeof(*prop)) {
+- dev_err(&master->dev, "%s has no 'reg' property\n",
+- nc->full_name);
++ rc = of_property_read_u32(nc, "reg", &value);
++ if (rc) {
++ dev_err(&master->dev, "%s has no valid 'reg' property (%d)\n",
++ nc->full_name, rc);
+ spi_dev_put(spi);
+ continue;
+ }
+- spi->chip_select = be32_to_cpup(prop);
++ spi->chip_select = value;
+
+ /* Mode (clock phase/polarity/etc.) */
+ if (of_find_property(nc, "spi-cpha", NULL))
+@@ -871,15 +1023,54 @@
+ if (of_find_property(nc, "spi-3wire", NULL))
+ spi->mode |= SPI_3WIRE;
+
++ /* Device DUAL/QUAD mode */
++ if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) {
++ switch (value) {
++ case 1:
++ break;
++ case 2:
++ spi->mode |= SPI_TX_DUAL;
++ break;
++ case 4:
++ spi->mode |= SPI_TX_QUAD;
++ break;
++ default:
++ dev_err(&master->dev,
++ "spi-tx-bus-width %d not supported\n",
++ value);
++ spi_dev_put(spi);
++ continue;
++ }
++ }
++
++ if (!of_property_read_u32(nc, "spi-rx-bus-width", &value)) {
++ switch (value) {
++ case 1:
++ break;
++ case 2:
++ spi->mode |= SPI_RX_DUAL;
++ break;
++ case 4:
++ spi->mode |= SPI_RX_QUAD;
++ break;
++ default:
++ dev_err(&master->dev,
++ "spi-rx-bus-width %d not supported\n",
++ value);
++ spi_dev_put(spi);
++ continue;
++ }
++ }
++
+ /* Device speed */
+- prop = of_get_property(nc, "spi-max-frequency", &len);
+- if (!prop || len < sizeof(*prop)) {
+- dev_err(&master->dev, "%s has no 'spi-max-frequency' property\n",
+- nc->full_name);
++ rc = of_property_read_u32(nc, "spi-max-frequency", &value);
++ if (rc) {
++ dev_err(&master->dev, "%s has no valid 'spi-max-frequency' property (%d)\n",
++ nc->full_name, rc);
+ spi_dev_put(spi);
+ continue;
+ }
+- spi->max_speed_hz = be32_to_cpup(prop);
++ spi->max_speed_hz = value;
+
+ /* IRQ */
+ spi->irq = irq_of_parse_and_map(nc, 0);
+@@ -889,9 +1080,7 @@
+ spi->dev.of_node = nc;
+
+ /* Register the new device */
+- snprintf(modalias, sizeof(modalias), "%s%s", SPI_MODULE_PREFIX,
+- spi->modalias);
+- request_module(modalias);
++ request_module("%s%s", SPI_MODULE_PREFIX, spi->modalias);
+ rc = spi_add_device(spi);
+ if (rc) {
+ dev_err(&master->dev, "spi_device register error %s\n",
+@@ -970,8 +1159,10 @@
+ return AE_OK;
+ }
+
+- strlcpy(spi->modalias, dev_name(&adev->dev), sizeof(spi->modalias));
++ adev->power.flags.ignore_parent = true;
++ strlcpy(spi->modalias, acpi_device_hid(adev), sizeof(spi->modalias));
+ if (spi_add_device(spi)) {
++ adev->power.flags.ignore_parent = false;
+ dev_err(&master->dev, "failed to add SPI device %s from ACPI\n",
+ dev_name(&adev->dev));
+ spi_dev_put(spi);
+@@ -1042,7 +1233,7 @@
+ if (!dev)
+ return NULL;
+
+- master = kzalloc(size + sizeof *master, GFP_KERNEL);
++ master = kzalloc(size + sizeof(*master), GFP_KERNEL);
+ if (!master)
+ return NULL;
+
+@@ -1067,7 +1258,7 @@
+ return 0;
+
+ nb = of_gpio_named_count(np, "cs-gpios");
+- master->num_chipselect = max(nb, (int)master->num_chipselect);
++ master->num_chipselect = max_t(int, nb, master->num_chipselect);
+
+ /* Return error only for an incorrectly formed cs-gpios property */
+ if (nb == 0 || nb == -ENOENT)
+@@ -1154,6 +1345,7 @@
+ spin_lock_init(&master->bus_lock_spinlock);
+ mutex_init(&master->bus_lock_mutex);
+ master->bus_lock_flag = 0;
++ init_completion(&master->xfer_completion);
+
+ /* register the device, then userspace will see it.
+ * registration fails if the bus ID is in use.
+@@ -1171,7 +1363,7 @@
+ else {
+ status = spi_master_initialize_queue(master);
+ if (status) {
+- device_unregister(&master->dev);
++ device_del(&master->dev);
+ goto done;
+ }
+ }
+@@ -1190,6 +1382,41 @@
+ }
+ EXPORT_SYMBOL_GPL(spi_register_master);
+
++static void devm_spi_unregister(struct device *dev, void *res)
++{
++ spi_unregister_master(*(struct spi_master **)res);
++}
++
++/**
++ * dev_spi_register_master - register managed SPI master controller
++ * @dev: device managing SPI master
++ * @master: initialized master, originally from spi_alloc_master()
++ * Context: can sleep
++ *
++ * Register a SPI device as with spi_register_master() which will
++ * automatically be unregister
++ */
++int devm_spi_register_master(struct device *dev, struct spi_master *master)
++{
++ struct spi_master **ptr;
++ int ret;
++
++ ptr = devres_alloc(devm_spi_unregister, sizeof(*ptr), GFP_KERNEL);
++ if (!ptr)
++ return -ENOMEM;
++
++ ret = spi_register_master(master);
++ if (ret != 0) {
++ *ptr = master;
++ devres_add(dev, ptr);
++ } else {
++ devres_free(ptr);
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(devm_spi_register_master);
++
+ static int __unregister(struct device *dev, void *null)
+ {
+ spi_unregister_device(to_spi_device(dev));
+@@ -1318,6 +1545,19 @@
+ unsigned bad_bits;
+ int status = 0;
+
++ /* check mode to prevent that DUAL and QUAD set at the same time
++ */
++ if (((spi->mode & SPI_TX_DUAL) && (spi->mode & SPI_TX_QUAD)) ||
++ ((spi->mode & SPI_RX_DUAL) && (spi->mode & SPI_RX_QUAD))) {
++ dev_err(&spi->dev,
++ "setup: can not select dual and quad at the same time\n");
++ return -EINVAL;
++ }
++ /* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
++ */
++ if ((spi->mode & SPI_3WIRE) && (spi->mode &
++ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
++ return -EINVAL;
+ /* help drivers fail *cleanly* when they need options
+ * that aren't supported with their current master
+ */
+@@ -1334,8 +1574,7 @@
+ if (spi->master->setup)
+ status = spi->master->setup(spi);
+
+- dev_dbg(&spi->dev, "setup mode %d, %s%s%s%s"
+- "%u bits/w, %u Hz max --> %d\n",
++ dev_dbg(&spi->dev, "setup mode %d, %s%s%s%s%u bits/w, %u Hz max --> %d\n",
+ (int) (spi->mode & (SPI_CPOL | SPI_CPHA)),
+ (spi->mode & SPI_CS_HIGH) ? "cs_high, " : "",
+ (spi->mode & SPI_LSB_FIRST) ? "lsb, " : "",
+@@ -1353,6 +1592,15 @@
+ struct spi_master *master = spi->master;
+ struct spi_transfer *xfer;
+
++ message->spi = spi;
++
++ trace_spi_message_submit(message);
++
++ if (list_empty(&message->transfers))
++ return -EINVAL;
++ if (!message->complete)
++ return -EINVAL;
++
+ /* Half-duplex links include original MicroWire, and ones with
+ * only one data pin like SPI_3WIRE (switches direction) or where
+ * either MOSI or MISO is missing. They can also be caused by
+@@ -1375,12 +1623,20 @@
+ /**
+ * Set transfer bits_per_word and max speed as spi device default if
+ * it is not set for this transfer.
++ * Set transfer tx_nbits and rx_nbits as single transfer default
++ * (SPI_NBITS_SINGLE) if it is not set for this transfer.
+ */
+ list_for_each_entry(xfer, &message->transfers, transfer_list) {
++ message->frame_length += xfer->len;
+ if (!xfer->bits_per_word)
+ xfer->bits_per_word = spi->bits_per_word;
+- if (!xfer->speed_hz)
++ if (!xfer->speed_hz) {
+ xfer->speed_hz = spi->max_speed_hz;
++ if (master->max_speed_hz &&
++ xfer->speed_hz > master->max_speed_hz)
++ xfer->speed_hz = master->max_speed_hz;
++ }
++
+ if (master->bits_per_word_mask) {
+ /* Only 32 bits fit in the mask */
+ if (xfer->bits_per_word > 32)
+@@ -1389,9 +1645,56 @@
+ BIT(xfer->bits_per_word - 1)))
+ return -EINVAL;
+ }
++
++ if (xfer->speed_hz && master->min_speed_hz &&
++ xfer->speed_hz < master->min_speed_hz)
++ return -EINVAL;
++ if (xfer->speed_hz && master->max_speed_hz &&
++ xfer->speed_hz > master->max_speed_hz)
++ return -EINVAL;
++
++ if (xfer->tx_buf && !xfer->tx_nbits)
++ xfer->tx_nbits = SPI_NBITS_SINGLE;
++ if (xfer->rx_buf && !xfer->rx_nbits)
++ xfer->rx_nbits = SPI_NBITS_SINGLE;
++ /* check transfer tx/rx_nbits:
++ * 1. keep the value is not out of single, dual and quad
++ * 2. keep tx/rx_nbits is contained by mode in spi_device
++ * 3. if SPI_3WIRE, tx/rx_nbits should be in single
++ */
++ if (xfer->tx_buf) {
++ if (xfer->tx_nbits != SPI_NBITS_SINGLE &&
++ xfer->tx_nbits != SPI_NBITS_DUAL &&
++ xfer->tx_nbits != SPI_NBITS_QUAD)
++ return -EINVAL;
++ if ((xfer->tx_nbits == SPI_NBITS_DUAL) &&
++ !(spi->mode & (SPI_TX_DUAL | SPI_TX_QUAD)))
++ return -EINVAL;
++ if ((xfer->tx_nbits == SPI_NBITS_QUAD) &&
++ !(spi->mode & SPI_TX_QUAD))
++ return -EINVAL;
++ if ((spi->mode & SPI_3WIRE) &&
++ (xfer->tx_nbits != SPI_NBITS_SINGLE))
++ return -EINVAL;
++ }
++ /* check transfer rx_nbits */
++ if (xfer->rx_buf) {
++ if (xfer->rx_nbits != SPI_NBITS_SINGLE &&
++ xfer->rx_nbits != SPI_NBITS_DUAL &&
++ xfer->rx_nbits != SPI_NBITS_QUAD)
++ return -EINVAL;
++ if ((xfer->rx_nbits == SPI_NBITS_DUAL) &&
++ !(spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD)))
++ return -EINVAL;
++ if ((xfer->rx_nbits == SPI_NBITS_QUAD) &&
++ !(spi->mode & SPI_RX_QUAD))
++ return -EINVAL;
++ if ((spi->mode & SPI_3WIRE) &&
++ (xfer->rx_nbits != SPI_NBITS_SINGLE))
++ return -EINVAL;
++ }
+ }
+
+- message->spi = spi;
+ message->status = -EINPROGRESS;
+ return master->transfer(spi, message);
+ }
+@@ -1633,7 +1936,7 @@
+ EXPORT_SYMBOL_GPL(spi_bus_unlock);
+
+ /* portable code must never pass more than 32 bytes */
+-#define SPI_BUFSIZ max(32,SMP_CACHE_BYTES)
++#define SPI_BUFSIZ max(32, SMP_CACHE_BYTES)
+
+ static u8 *buf;
+
+@@ -1682,7 +1985,7 @@
+ }
+
+ spi_message_init(&message);
+- memset(x, 0, sizeof x);
++ memset(x, 0, sizeof(x));
+ if (n_tx) {
+ x[0].len = n_tx;
+ spi_message_add_tail(&x[0], &message);
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-clps711x.c linux-linaro-stable-mx6/drivers/spi/spi-clps711x.c
+--- linux-3.10.30.orig/drivers/spi/spi-clps711x.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-clps711x.c 2014-05-15 20:34:04.814062977 +0200
+@@ -42,12 +42,6 @@
+ {
+ struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
+
+- if (spi->bits_per_word != 8) {
+- dev_err(&spi->dev, "Unsupported master bus width %i\n",
+- spi->bits_per_word);
+- return -EINVAL;
+- }
+-
+ /* We are expect that SPI-device is not selected */
+ gpio_direction_output(hw->chipselect[spi->chip_select],
+ !(spi->mode & SPI_CS_HIGH));
+@@ -190,6 +184,7 @@
+
+ master->bus_num = pdev->id;
+ master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
++ master->bits_per_word_mask = SPI_BPW_MASK(8);
+ master->num_chipselect = pdata->num_chipselect;
+ master->setup = spi_clps711x_setup;
+ master->transfer_one_message = spi_clps711x_transfer_one_message;
+@@ -254,7 +249,6 @@
+ if (gpio_is_valid(hw->chipselect[i]))
+ gpio_free(hw->chipselect[i]);
+
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+ kfree(master);
+
+@@ -274,7 +268,6 @@
+ gpio_free(hw->chipselect[i]);
+
+ devm_clk_put(&pdev->dev, hw->spi_clk);
+- platform_set_drvdata(pdev, NULL);
+ spi_unregister_master(master);
+ kfree(master);
+
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-coldfire-qspi.c linux-linaro-stable-mx6/drivers/spi/spi-coldfire-qspi.c
+--- linux-3.10.30.orig/drivers/spi/spi-coldfire-qspi.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-coldfire-qspi.c 2014-05-15 20:34:04.814062977 +0200
+@@ -312,10 +312,7 @@
+ bool cs_high = spi->mode & SPI_CS_HIGH;
+ u16 qmr = MCFQSPI_QMR_MSTR;
+
+- if (t->bits_per_word)
+- qmr |= t->bits_per_word << 10;
+- else
+- qmr |= spi->bits_per_word << 10;
++ qmr |= t->bits_per_word << 10;
+ if (spi->mode & SPI_CPHA)
+ qmr |= MCFQSPI_QMR_CPHA;
+ if (spi->mode & SPI_CPOL)
+@@ -377,11 +374,6 @@
+
+ static int mcfqspi_setup(struct spi_device *spi)
+ {
+- if ((spi->bits_per_word < 8) || (spi->bits_per_word > 16)) {
+- dev_dbg(&spi->dev, "%d bits per word is not supported\n",
+- spi->bits_per_word);
+- return -EINVAL;
+- }
+ if (spi->chip_select >= spi->master->num_chipselect) {
+ dev_dbg(&spi->dev, "%d chip select is out of range\n",
+ spi->chip_select);
+@@ -477,6 +469,7 @@
+ mcfqspi->dev = &pdev->dev;
+
+ master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
+ master->setup = mcfqspi_setup;
+ master->transfer_one_message = mcfqspi_transfer_one_message;
+ master->prepare_transfer_hardware = mcfqspi_prepare_transfer_hw;
+@@ -524,7 +517,6 @@
+ /* disable the hardware (set the baud rate to 0) */
+ mcfqspi_wr_qmr(mcfqspi, MCFQSPI_QMR_MSTR);
+
+- platform_set_drvdata(pdev, NULL);
+ mcfqspi_cs_teardown(mcfqspi);
+ clk_disable(mcfqspi->clk);
+ clk_put(mcfqspi->clk);
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-davinci.c linux-linaro-stable-mx6/drivers/spi/spi-davinci.c
+--- linux-3.10.30.orig/drivers/spi/spi-davinci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-davinci.c 2014-05-15 20:34:04.814062977 +0200
+@@ -299,16 +299,15 @@
+ * Assign function pointer to appropriate transfer method
+ * 8bit, 16bit or 32bit transfer
+ */
+- if (bits_per_word <= 8 && bits_per_word >= 2) {
++ if (bits_per_word <= 8) {
+ dspi->get_rx = davinci_spi_rx_buf_u8;
+ dspi->get_tx = davinci_spi_tx_buf_u8;
+ dspi->bytes_per_word[spi->chip_select] = 1;
+- } else if (bits_per_word <= 16 && bits_per_word >= 2) {
++ } else {
+ dspi->get_rx = davinci_spi_rx_buf_u16;
+ dspi->get_tx = davinci_spi_tx_buf_u16;
+ dspi->bytes_per_word[spi->chip_select] = 2;
+- } else
+- return -EINVAL;
++ }
+
+ if (!hz)
+ hz = spi->max_speed_hz;
+@@ -917,7 +916,7 @@
+ if (ret)
+ goto unmap_io;
+
+- dspi->bitbang.master = spi_master_get(master);
++ dspi->bitbang.master = master;
+ if (dspi->bitbang.master == NULL) {
+ ret = -ENODEV;
+ goto irq_free;
+@@ -926,13 +925,14 @@
+ dspi->clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(dspi->clk)) {
+ ret = -ENODEV;
+- goto put_master;
++ goto irq_free;
+ }
+ clk_prepare_enable(dspi->clk);
+
+ master->dev.of_node = pdev->dev.of_node;
+ master->bus_num = pdev->id;
+ master->num_chipselect = pdata->num_chipselect;
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
+ master->setup = davinci_spi_setup;
+
+ dspi->bitbang.chipselect = davinci_spi_chipselect;
+@@ -1015,8 +1015,6 @@
+ free_clk:
+ clk_disable_unprepare(dspi->clk);
+ clk_put(dspi->clk);
+-put_master:
+- spi_master_put(master);
+ irq_free:
+ free_irq(dspi->irq, dspi);
+ unmap_io:
+@@ -1024,7 +1022,7 @@
+ release_region:
+ release_mem_region(dspi->pbase, resource_size(r));
+ free_master:
+- kfree(master);
++ spi_master_put(master);
+ err:
+ return ret;
+ }
+@@ -1051,11 +1049,11 @@
+
+ clk_disable_unprepare(dspi->clk);
+ clk_put(dspi->clk);
+- spi_master_put(master);
+ free_irq(dspi->irq, dspi);
+ iounmap(dspi->base);
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ release_mem_region(dspi->pbase, resource_size(r));
++ spi_master_put(master);
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-dw.c linux-linaro-stable-mx6/drivers/spi/spi-dw.c
+--- linux-3.10.30.orig/drivers/spi/spi-dw.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-dw.c 2014-05-15 20:34:04.814062977 +0200
+@@ -457,19 +457,7 @@
+ }
+ if (transfer->bits_per_word) {
+ bits = transfer->bits_per_word;
+-
+- switch (bits) {
+- case 8:
+- case 16:
+- dws->n_bytes = dws->dma_width = bits >> 3;
+- break;
+- default:
+- printk(KERN_ERR "MRST SPI0: unsupported bits:"
+- "%db\n", bits);
+- message->status = -EIO;
+- goto early_exit;
+- }
+-
++ dws->n_bytes = dws->dma_width = bits >> 3;
+ cr0 = (bits - 1)
+ | (chip->type << SPI_FRF_OFFSET)
+ | (spi->mode << SPI_MODE_OFFSET)
+@@ -629,9 +617,6 @@
+ struct dw_spi_chip *chip_info = NULL;
+ struct chip_data *chip;
+
+- if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
+- return -EINVAL;
+-
+ /* Only alloc on first setup */
+ chip = spi_get_ctldata(spi);
+ if (!chip) {
+@@ -660,16 +645,12 @@
+ chip->enable_dma = chip_info->enable_dma;
+ }
+
+- if (spi->bits_per_word <= 8) {
++ if (spi->bits_per_word == 8) {
+ chip->n_bytes = 1;
+ chip->dma_width = 1;
+- } else if (spi->bits_per_word <= 16) {
++ } else if (spi->bits_per_word == 16) {
+ chip->n_bytes = 2;
+ chip->dma_width = 2;
+- } else {
+- /* Never take >16b case for MRST SPIC */
+- dev_err(&spi->dev, "invalid wordsize\n");
+- return -EINVAL;
+ }
+ chip->bits_per_word = spi->bits_per_word;
+
+@@ -824,6 +805,7 @@
+ }
+
+ master->mode_bits = SPI_CPOL | SPI_CPHA;
++ master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bus_num = dws->bus_num;
+ master->num_chipselect = dws->num_cs;
+ master->cleanup = dw_spi_cleanup;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-dw-mmio.c linux-linaro-stable-mx6/drivers/spi/spi-dw-mmio.c
+--- linux-3.10.30.orig/drivers/spi/spi-dw-mmio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-dw-mmio.c 2014-05-15 20:34:04.814062977 +0200
+@@ -111,8 +111,6 @@
+ struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
+ struct resource *mem;
+
+- platform_set_drvdata(pdev, NULL);
+-
+ clk_disable(dwsmmio->clk);
+ clk_put(dwsmmio->clk);
+ dwsmmio->clk = NULL;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-ep93xx.c linux-linaro-stable-mx6/drivers/spi/spi-ep93xx.c
+--- linux-3.10.30.orig/drivers/spi/spi-ep93xx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-ep93xx.c 2014-05-15 20:34:04.814062977 +0200
+@@ -296,12 +296,6 @@
+ struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
+ struct ep93xx_spi_chip *chip;
+
+- if (spi->bits_per_word < 4 || spi->bits_per_word > 16) {
+- dev_err(&espi->pdev->dev, "invalid bits per word %d\n",
+- spi->bits_per_word);
+- return -EINVAL;
+- }
+-
+ chip = spi_get_ctldata(spi);
+ if (!chip) {
+ dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
+@@ -365,10 +359,6 @@
+
+ /* first validate each transfer */
+ list_for_each_entry(t, &msg->transfers, transfer_list) {
+- if (t->bits_per_word) {
+- if (t->bits_per_word < 4 || t->bits_per_word > 16)
+- return -EINVAL;
+- }
+ if (t->speed_hz && t->speed_hz < espi->min_rate)
+ return -EINVAL;
+ }
+@@ -1046,6 +1036,7 @@
+ master->bus_num = pdev->id;
+ master->num_chipselect = info->num_chipselect;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
+
+ platform_set_drvdata(pdev, master);
+
+@@ -1132,7 +1123,6 @@
+ clk_put(espi->clk);
+ fail_release_master:
+ spi_master_put(master);
+- platform_set_drvdata(pdev, NULL);
+
+ return error;
+ }
+@@ -1167,7 +1157,6 @@
+
+ ep93xx_spi_release_dma(espi);
+ clk_put(espi->clk);
+- platform_set_drvdata(pdev, NULL);
+
+ spi_unregister_master(master);
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-fsl-espi.c linux-linaro-stable-mx6/drivers/spi/spi-fsl-espi.c
+--- linux-3.10.30.orig/drivers/spi/spi-fsl-espi.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-fsl-espi.c 2014-05-15 20:34:04.814062977 +0200
+@@ -144,10 +144,6 @@
+ if (!bits_per_word)
+ bits_per_word = spi->bits_per_word;
+
+- /* Make sure its a bit width we support [4..16] */
+- if ((bits_per_word < 4) || (bits_per_word > 16))
+- return -EINVAL;
+-
+ if (!hz)
+ hz = spi->max_speed_hz;
+
+@@ -157,12 +153,10 @@
+ cs->get_tx = mpc8xxx_spi_tx_buf_u32;
+ if (bits_per_word <= 8) {
+ cs->rx_shift = 8 - bits_per_word;
+- } else if (bits_per_word <= 16) {
++ } else
+ cs->rx_shift = 16 - bits_per_word;
+ if (spi->mode & SPI_LSB_FIRST)
+ cs->get_tx = fsl_espi_tx_buf_lsb;
+- } else {
+- return -EINVAL;
+ }
+
+ mpc8xxx_spi->rx_shift = cs->rx_shift;
+@@ -609,6 +603,7 @@
+ if (ret)
+ goto err_probe;
+
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
+ master->setup = fsl_espi_setup;
+
+ mpc8xxx_spi = spi_master_get_devdata(master);
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-gpio.c linux-linaro-stable-mx6/drivers/spi/spi-gpio.c
+--- linux-3.10.30.orig/drivers/spi/spi-gpio.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-gpio.c 2014-05-15 20:34:04.814062977 +0200
+@@ -239,9 +239,6 @@
+ struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi);
+ struct device_node *np = spi->master->dev.of_node;
+
+- if (spi->bits_per_word > 32)
+- return -EINVAL;
+-
+ if (np) {
+ /*
+ * In DT environments, the CS GPIOs have already been
+@@ -446,6 +443,7 @@
+ if (pdata)
+ spi_gpio->pdata = *pdata;
+
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
+ master->flags = master_flags;
+ master->bus_num = pdev->id;
+ master->num_chipselect = SPI_N_CHIPSEL;
+@@ -469,7 +467,7 @@
+ }
+ #endif
+
+- spi_gpio->bitbang.master = spi_master_get(master);
++ spi_gpio->bitbang.master = master;
+ spi_gpio->bitbang.chipselect = spi_gpio_chipselect;
+
+ if ((master_flags & (SPI_MASTER_NO_TX | SPI_MASTER_NO_RX)) == 0) {
+@@ -488,7 +486,6 @@
+
+ status = spi_bitbang_start(&spi_gpio->bitbang);
+ if (status < 0) {
+- spi_master_put(spi_gpio->bitbang.master);
+ gpio_free:
+ if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
+ gpio_free(SPI_MISO_GPIO);
+@@ -512,15 +509,13 @@
+
+ /* stop() unregisters child devices too */
+ status = spi_bitbang_stop(&spi_gpio->bitbang);
+- spi_master_put(spi_gpio->bitbang.master);
+-
+- platform_set_drvdata(pdev, NULL);
+
+ if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
+ gpio_free(SPI_MISO_GPIO);
+ if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI)
+ gpio_free(SPI_MOSI_GPIO);
+ gpio_free(SPI_SCK_GPIO);
++ spi_master_put(spi_gpio->bitbang.master);
+
+ return status;
+ }
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-imx.c linux-linaro-stable-mx6/drivers/spi/spi-imx.c
+--- linux-3.10.30.orig/drivers/spi/spi-imx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-imx.c 2014-05-15 20:34:04.846063208 +0200
+@@ -37,7 +37,6 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/of_gpio.h>
+-#include <linux/pinctrl/consumer.h>
+
+ #include <linux/platform_data/spi-imx.h>
+
+@@ -620,6 +619,7 @@
+ { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
+ { /* sentinel */ }
+ };
++MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
+
+ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
+ {
+@@ -698,11 +698,10 @@
+ } else if (config.bpw <= 16) {
+ spi_imx->rx = spi_imx_buf_rx_u16;
+ spi_imx->tx = spi_imx_buf_tx_u16;
+- } else if (config.bpw <= 32) {
++ } else {
+ spi_imx->rx = spi_imx_buf_rx_u32;
+ spi_imx->tx = spi_imx_buf_tx_u32;
+- } else
+- BUG();
++ }
+
+ spi_imx->devtype_data->config(spi_imx, &config);
+
+@@ -750,6 +749,35 @@
+ {
+ }
+
++static int
++spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
++{
++ struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
++ int ret;
++
++ ret = clk_enable(spi_imx->clk_per);
++ if (ret)
++ return ret;
++
++ ret = clk_enable(spi_imx->clk_ipg);
++ if (ret) {
++ clk_disable(spi_imx->clk_per);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int
++spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
++{
++ struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
++
++ clk_disable(spi_imx->clk_ipg);
++ clk_disable(spi_imx->clk_per);
++ return 0;
++}
++
+ static int spi_imx_probe(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+@@ -760,7 +788,6 @@
+ struct spi_master *master;
+ struct spi_imx_data *spi_imx;
+ struct resource *res;
+- struct pinctrl *pinctrl;
+ int i, ret, num_cs;
+
+ if (!np && !mxc_platform_info) {
+@@ -783,11 +810,12 @@
+
+ platform_set_drvdata(pdev, master);
+
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
+ master->bus_num = pdev->id;
+ master->num_chipselect = num_cs;
+
+ spi_imx = spi_master_get_devdata(master);
+- spi_imx->bitbang.master = spi_master_get(master);
++ spi_imx->bitbang.master = master;
+
+ for (i = 0; i < master->num_chipselect; i++) {
+ int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
+@@ -798,10 +826,11 @@
+ if (!gpio_is_valid(cs_gpio))
+ continue;
+
+- ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
++ ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
++ DRIVER_NAME);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get cs gpios\n");
+- goto out_gpio_free;
++ goto out_master_put;
+ }
+ }
+
+@@ -810,6 +839,8 @@
+ spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
+ spi_imx->bitbang.master->setup = spi_imx_setup;
+ spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
++ spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
++ spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
+ spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+
+ init_completion(&spi_imx->xfer_done);
+@@ -818,56 +849,44 @@
+ (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!res) {
+- dev_err(&pdev->dev, "can't get platform resource\n");
+- ret = -ENOMEM;
+- goto out_gpio_free;
+- }
+-
+- if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+- dev_err(&pdev->dev, "request_mem_region failed\n");
+- ret = -EBUSY;
+- goto out_gpio_free;
+- }
+-
+- spi_imx->base = ioremap(res->start, resource_size(res));
+- if (!spi_imx->base) {
+- ret = -EINVAL;
+- goto out_release_mem;
++ spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(spi_imx->base)) {
++ ret = PTR_ERR(spi_imx->base);
++ goto out_master_put;
+ }
+
+ spi_imx->irq = platform_get_irq(pdev, 0);
+ if (spi_imx->irq < 0) {
+ ret = -EINVAL;
+- goto out_iounmap;
++ goto out_master_put;
+ }
+
+- ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
++ ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
++ DRIVER_NAME, spi_imx);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
+- goto out_iounmap;
+- }
+-
+- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+- if (IS_ERR(pinctrl)) {
+- ret = PTR_ERR(pinctrl);
+- goto out_free_irq;
++ goto out_master_put;
+ }
+
+ spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+ if (IS_ERR(spi_imx->clk_ipg)) {
+ ret = PTR_ERR(spi_imx->clk_ipg);
+- goto out_free_irq;
++ goto out_master_put;
+ }
+
+ spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
+ if (IS_ERR(spi_imx->clk_per)) {
+ ret = PTR_ERR(spi_imx->clk_per);
+- goto out_free_irq;
++ goto out_master_put;
+ }
+
+- clk_prepare_enable(spi_imx->clk_per);
+- clk_prepare_enable(spi_imx->clk_ipg);
++ ret = clk_prepare_enable(spi_imx->clk_per);
++ if (ret)
++ goto out_master_put;
++
++ ret = clk_prepare_enable(spi_imx->clk_ipg);
++ if (ret)
++ goto out_put_per;
+
+ spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
+
+@@ -884,53 +903,32 @@
+
+ dev_info(&pdev->dev, "probed\n");
+
++ clk_disable(spi_imx->clk_ipg);
++ clk_disable(spi_imx->clk_per);
+ return ret;
+
+ out_clk_put:
+- clk_disable_unprepare(spi_imx->clk_per);
+ clk_disable_unprepare(spi_imx->clk_ipg);
+-out_free_irq:
+- free_irq(spi_imx->irq, spi_imx);
+-out_iounmap:
+- iounmap(spi_imx->base);
+-out_release_mem:
+- release_mem_region(res->start, resource_size(res));
+-out_gpio_free:
+- while (--i >= 0) {
+- if (gpio_is_valid(spi_imx->chipselect[i]))
+- gpio_free(spi_imx->chipselect[i]);
+- }
++out_put_per:
++ clk_disable_unprepare(spi_imx->clk_per);
++out_master_put:
+ spi_master_put(master);
+- kfree(master);
+- platform_set_drvdata(pdev, NULL);
++
+ return ret;
+ }
+
+ static int spi_imx_remove(struct platform_device *pdev)
+ {
+ struct spi_master *master = platform_get_drvdata(pdev);
+- struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
+- int i;
+
+ spi_bitbang_stop(&spi_imx->bitbang);
+
+ writel(0, spi_imx->base + MXC_CSPICTRL);
+- clk_disable_unprepare(spi_imx->clk_per);
+ clk_disable_unprepare(spi_imx->clk_ipg);
+- free_irq(spi_imx->irq, spi_imx);
+- iounmap(spi_imx->base);
+-
+- for (i = 0; i < master->num_chipselect; i++)
+- if (gpio_is_valid(spi_imx->chipselect[i]))
+- gpio_free(spi_imx->chipselect[i]);
+-
++ clk_disable_unprepare(spi_imx->clk_per);
+ spi_master_put(master);
+
+- release_mem_region(res->start, resource_size(res));
+-
+- platform_set_drvdata(pdev, NULL);
+-
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-lm70llp.c linux-linaro-stable-mx6/drivers/spi/spi-lm70llp.c
+--- linux-3.10.30.orig/drivers/spi/spi-lm70llp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-lm70llp.c 2014-05-15 20:34:04.846063208 +0200
+@@ -222,7 +222,7 @@
+ /*
+ * SPI and bitbang hookup.
+ */
+- pp->bitbang.master = spi_master_get(master);
++ pp->bitbang.master = master;
+ pp->bitbang.chipselect = lm70_chipselect;
+ pp->bitbang.txrx_word[SPI_MODE_0] = lm70_txrx;
+ pp->bitbang.flags = SPI_3WIRE;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-mxs.c linux-linaro-stable-mx6/drivers/spi/spi-mxs.c
+--- linux-3.10.30.orig/drivers/spi/spi-mxs.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-mxs.c 2014-05-15 20:34:04.918063726 +0200
+@@ -75,12 +75,6 @@
+ if (t && t->bits_per_word)
+ bits_per_word = t->bits_per_word;
+
+- if (bits_per_word != 8) {
+- dev_err(&dev->dev, "%s, unsupported bits_per_word=%d\n",
+- __func__, bits_per_word);
+- return -EINVAL;
+- }
+-
+ hz = dev->max_speed_hz;
+ if (t && t->speed_hz)
+ hz = min(hz, t->speed_hz);
+@@ -548,6 +542,7 @@
+
+ master->transfer_one_message = mxs_spi_transfer_one;
+ master->setup = mxs_spi_setup;
++ master->bits_per_word_mask = SPI_BPW_MASK(8);
+ master->mode_bits = SPI_CPOL | SPI_CPHA;
+ master->num_chipselect = 3;
+ master->dev.of_node = np;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-nuc900.c linux-linaro-stable-mx6/drivers/spi/spi-nuc900.c
+--- linux-3.10.30.orig/drivers/spi/spi-nuc900.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-nuc900.c 2014-05-15 20:34:04.918063726 +0200
+@@ -174,17 +174,6 @@
+ spin_unlock_irqrestore(&hw->lock, flags);
+ }
+
+-static int nuc900_spi_setupxfer(struct spi_device *spi,
+- struct spi_transfer *t)
+-{
+- return 0;
+-}
+-
+-static int nuc900_spi_setup(struct spi_device *spi)
+-{
+- return 0;
+-}
+-
+ static inline unsigned int hw_txbyte(struct nuc900_spi *hw, int count)
+ {
+ return hw->tx ? hw->tx[count] : 0;
+@@ -377,10 +366,8 @@
+ master->num_chipselect = hw->pdata->num_cs;
+ master->bus_num = hw->pdata->bus_num;
+ hw->bitbang.master = hw->master;
+- hw->bitbang.setup_transfer = nuc900_spi_setupxfer;
+ hw->bitbang.chipselect = nuc900_spi_chipsel;
+ hw->bitbang.txrx_bufs = nuc900_spi_txrx;
+- hw->bitbang.master->setup = nuc900_spi_setup;
+
+ hw->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (hw->res == NULL) {
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-oc-tiny.c linux-linaro-stable-mx6/drivers/spi/spi-oc-tiny.c
+--- linux-3.10.30.orig/drivers/spi/spi-oc-tiny.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-oc-tiny.c 2014-05-15 20:34:04.918063726 +0200
+@@ -306,7 +306,7 @@
+ platform_set_drvdata(pdev, hw);
+
+ /* setup the state for the bitbang driver */
+- hw->bitbang.master = spi_master_get(master);
++ hw->bitbang.master = master;
+ if (!hw->bitbang.master)
+ return err;
+ hw->bitbang.setup_transfer = tiny_spi_setup_transfer;
+@@ -368,7 +368,6 @@
+ exit_busy:
+ err = -EBUSY;
+ exit:
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+ return err;
+ }
+@@ -382,7 +381,6 @@
+ spi_bitbang_stop(&hw->bitbang);
+ for (i = 0; i < hw->gpio_cs_count; i++)
+ gpio_free(hw->gpio_cs[i]);
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-omap-100k.c linux-linaro-stable-mx6/drivers/spi/spi-omap-100k.c
+--- linux-3.10.30.orig/drivers/spi/spi-omap-100k.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-omap-100k.c 2014-05-15 20:34:04.918063726 +0200
+@@ -298,12 +298,6 @@
+ struct omap1_spi100k *spi100k;
+ struct omap1_spi100k_cs *cs = spi->controller_state;
+
+- if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
+- dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
+- spi->bits_per_word);
+- return -EINVAL;
+- }
+-
+ spi100k = spi_master_get_devdata(spi->master);
+
+ if (!cs) {
+@@ -451,10 +445,7 @@
+ unsigned len = t->len;
+
+ if (t->speed_hz > OMAP1_SPI100K_MAX_FREQ
+- || (len && !(rx_buf || tx_buf))
+- || (t->bits_per_word &&
+- ( t->bits_per_word < 4
+- || t->bits_per_word > 32))) {
++ || (len && !(rx_buf || tx_buf))) {
+ dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
+ t->speed_hz,
+ len,
+@@ -509,6 +500,7 @@
+ master->cleanup = NULL;
+ master->num_chipselect = 2;
+ master->mode_bits = MODEBITS;
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
+
+ dev_set_drvdata(&pdev->dev, master);
+
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-omap2-mcspi.c linux-linaro-stable-mx6/drivers/spi/spi-omap2-mcspi.c
+--- linux-3.10.30.orig/drivers/spi/spi-omap2-mcspi.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-omap2-mcspi.c 2014-05-15 20:34:04.918063726 +0200
+@@ -857,12 +857,6 @@
+ struct omap2_mcspi_dma *mcspi_dma;
+ struct omap2_mcspi_cs *cs = spi->controller_state;
+
+- if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
+- dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
+- spi->bits_per_word);
+- return -EINVAL;
+- }
+-
+ mcspi_dma = &mcspi->dma_channels[spi->chip_select];
+
+ if (!cs) {
+@@ -1072,10 +1066,7 @@
+ unsigned len = t->len;
+
+ if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
+- || (len && !(rx_buf || tx_buf))
+- || (t->bits_per_word &&
+- ( t->bits_per_word < 4
+- || t->bits_per_word > 32))) {
++ || (len && !(rx_buf || tx_buf))) {
+ dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
+ t->speed_hz,
+ len,
+@@ -1196,7 +1187,7 @@
+
+ /* the spi->mode bits understood by this driver: */
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+-
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
+ master->setup = omap2_mcspi_setup;
+ master->prepare_transfer_hardware = omap2_prepare_transfer;
+ master->unprepare_transfer_hardware = omap2_unprepare_transfer;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-ppc4xx.c linux-linaro-stable-mx6/drivers/spi/spi-ppc4xx.c
+--- linux-3.10.30.orig/drivers/spi/spi-ppc4xx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-ppc4xx.c 2014-05-15 20:34:04.918063726 +0200
+@@ -190,12 +190,6 @@
+ speed = min(t->speed_hz, spi->max_speed_hz);
+ }
+
+- if (bits_per_word != 8) {
+- dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
+- bits_per_word);
+- return -EINVAL;
+- }
+-
+ if (!speed || (speed > spi->max_speed_hz)) {
+ dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
+ return -EINVAL;
+@@ -229,12 +223,6 @@
+ {
+ struct spi_ppc4xx_cs *cs = spi->controller_state;
+
+- if (spi->bits_per_word != 8) {
+- dev_err(&spi->dev, "invalid bits-per-word (%d)\n",
+- spi->bits_per_word);
+- return -EINVAL;
+- }
+-
+ if (!spi->max_speed_hz) {
+ dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
+ return -EINVAL;
+@@ -465,6 +453,7 @@
+ bbp->use_dma = 0;
+ bbp->master->setup = spi_ppc4xx_setup;
+ bbp->master->cleanup = spi_ppc4xx_cleanup;
++ bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
+
+ /* the spi->mode bits understood by this driver: */
+ bbp->master->mode_bits =
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-pxa2xx.c linux-linaro-stable-mx6/drivers/spi/spi-pxa2xx.c
+--- linux-3.10.30.orig/drivers/spi/spi-pxa2xx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-pxa2xx.c 2014-05-15 20:34:04.978064159 +0200
+@@ -881,21 +881,6 @@
+ rx_thres = RX_THRESH_DFLT;
+ }
+
+- if (!pxa25x_ssp_comp(drv_data)
+- && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
+- dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
+- "b/w not 4-32 for type non-PXA25x_SSP\n",
+- drv_data->ssp_type, spi->bits_per_word);
+- return -EINVAL;
+- } else if (pxa25x_ssp_comp(drv_data)
+- && (spi->bits_per_word < 4
+- || spi->bits_per_word > 16)) {
+- dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
+- "b/w not 4-16 for type PXA25x_SSP\n",
+- drv_data->ssp_type, spi->bits_per_word);
+- return -EINVAL;
+- }
+-
+ /* Only alloc on first setup */
+ chip = spi_get_ctldata(spi);
+ if (!chip) {
+@@ -1011,9 +996,6 @@
+ chip->n_bytes = 4;
+ chip->read = u32_reader;
+ chip->write = u32_writer;
+- } else {
+- dev_err(&spi->dev, "invalid wordsize\n");
+- return -ENODEV;
+ }
+ chip->bits_per_word = spi->bits_per_word;
+
+@@ -1190,11 +1172,13 @@
+ drv_data->ioaddr = ssp->mmio_base;
+ drv_data->ssdr_physical = ssp->phys_base + SSDR;
+ if (pxa25x_ssp_comp(drv_data)) {
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
+ drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
+ drv_data->dma_cr1 = 0;
+ drv_data->clear_sr = SSSR_ROR;
+ drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
+ } else {
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
+ drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
+ drv_data->dma_cr1 = DEFAULT_DMA_CR1;
+ drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
+@@ -1299,9 +1283,6 @@
+ /* Disconnect from the SPI framework */
+ spi_unregister_master(drv_data->master);
+
+- /* Prevent double remove */
+- platform_set_drvdata(pdev, NULL);
+-
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-s3c64xx.c linux-linaro-stable-mx6/drivers/spi/spi-s3c64xx.c
+--- linux-3.10.30.orig/drivers/spi/spi-s3c64xx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-s3c64xx.c 2014-05-15 20:34:04.978064159 +0200
+@@ -1314,7 +1314,8 @@
+ master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
+ master->num_chipselect = sci->num_cs;
+ master->dma_alignment = 8;
+- master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
++ master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
++ SPI_BPW_MASK(8);
+ /* the spi->mode bits understood by this driver: */
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+
+@@ -1399,7 +1400,6 @@
+ err2:
+ clk_disable_unprepare(sdd->clk);
+ err0:
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+
+ return ret;
+@@ -1420,7 +1420,6 @@
+
+ clk_disable_unprepare(sdd->clk);
+
+- platform_set_drvdata(pdev, NULL);
+ spi_master_put(master);
+
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-sirf.c linux-linaro-stable-mx6/drivers/spi/spi-sirf.c
+--- linux-3.10.30.orig/drivers/spi/spi-sirf.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-sirf.c 2014-05-15 20:34:04.978064159 +0200
+@@ -425,10 +425,6 @@
+ rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
+ SIRFSOC_SPI_FIFO_WIDTH_DWORD;
+ break;
+- default:
+- dev_err(&spi->dev, "Bits per word %d not supported\n",
+- bits_per_word);
+- return -EINVAL;
+ }
+
+ if (!(spi->mode & SPI_CS_HIGH))
+@@ -550,12 +546,14 @@
+ if (ret)
+ goto free_master;
+
+- sspi->bitbang.master = spi_master_get(master);
++ sspi->bitbang.master = master;
+ sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
+ sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
+ sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
+ sspi->bitbang.master->setup = spi_sirfsoc_setup;
+ master->bus_num = pdev->id;
++ master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
++ SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
+ sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
+
+ sspi->p = pinctrl_get_select_default(&pdev->dev);
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-ti-ssp.c linux-linaro-stable-mx6/drivers/spi/spi-ti-ssp.c
+--- linux-3.10.30.orig/drivers/spi/spi-ti-ssp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-ti-ssp.c 2014-05-15 20:34:04.982064187 +0200
+@@ -237,14 +237,6 @@
+ spin_unlock(&hw->lock);
+ }
+
+-static int ti_ssp_spi_setup(struct spi_device *spi)
+-{
+- if (spi->bits_per_word > 32)
+- return -EINVAL;
+-
+- return 0;
+-}
+-
+ static int ti_ssp_spi_transfer(struct spi_device *spi, struct spi_message *m)
+ {
+ struct ti_ssp_spi *hw;
+@@ -269,12 +261,6 @@
+ dev_err(&spi->dev, "invalid xfer, full duplex\n");
+ return -EINVAL;
+ }
+-
+- if (t->bits_per_word > 32) {
+- dev_err(&spi->dev, "invalid xfer width %d\n",
+- t->bits_per_word);
+- return -EINVAL;
+- }
+ }
+
+ spin_lock(&hw->lock);
+@@ -337,8 +323,8 @@
+ master->bus_num = pdev->id;
+ master->num_chipselect = pdata->num_cs;
+ master->mode_bits = MODE_BITS;
++ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
+ master->flags = SPI_MASTER_HALF_DUPLEX;
+- master->setup = ti_ssp_spi_setup;
+ master->transfer = ti_ssp_spi_transfer;
+
+ error = spi_register_master(master);
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-topcliff-pch.c linux-linaro-stable-mx6/drivers/spi/spi-topcliff-pch.c
+--- linux-3.10.30.orig/drivers/spi/spi-topcliff-pch.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-topcliff-pch.c 2014-05-15 20:34:04.982064187 +0200
+@@ -472,11 +472,6 @@
+ dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__);
+ }
+
+- if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) {
+- dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__);
+- return -EINVAL;
+- }
+-
+ /* Check baud rate setting */
+ /* if baud rate of chip is greater than
+ max we can support,return error */
+@@ -537,17 +532,6 @@
+ /* if baud rate has been specified validate the same */
+ if (transfer->speed_hz > PCH_MAX_BAUDRATE)
+ transfer->speed_hz = PCH_MAX_BAUDRATE;
+-
+- /* if bits per word has been specified validate the same */
+- if (transfer->bits_per_word) {
+- if ((transfer->bits_per_word != 8)
+- && (transfer->bits_per_word != 16)) {
+- retval = -EINVAL;
+- dev_err(&pspi->dev,
+- "%s Invalid bits per word\n", __func__);
+- goto err_return_spinlock;
+- }
+- }
+ }
+ spin_unlock_irqrestore(&data->lock, flags);
+
+@@ -1442,6 +1426,7 @@
+ master->setup = pch_spi_setup;
+ master->transfer = pch_spi_transfer;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
++ master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+
+ data->board_dat = board_dat;
+ data->plat_dev = plat_dev;
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-txx9.c linux-linaro-stable-mx6/drivers/spi/spi-txx9.c
+--- linux-3.10.30.orig/drivers/spi/spi-txx9.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-txx9.c 2014-05-15 20:34:04.982064187 +0200
+@@ -116,17 +116,12 @@
+ static int txx9spi_setup(struct spi_device *spi)
+ {
+ struct txx9spi *c = spi_master_get_devdata(spi->master);
+- u8 bits_per_word;
+
+ if (!spi->max_speed_hz
+ || spi->max_speed_hz > c->max_speed_hz
+ || spi->max_speed_hz < c->min_speed_hz)
+ return -EINVAL;
+
+- bits_per_word = spi->bits_per_word;
+- if (bits_per_word != 8 && bits_per_word != 16)
+- return -EINVAL;
+-
+ if (gpio_direction_output(spi->chip_select,
+ !(spi->mode & SPI_CS_HIGH))) {
+ dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
+@@ -319,8 +314,6 @@
+
+ if (!t->tx_buf && !t->rx_buf && t->len)
+ return -EINVAL;
+- if (bits_per_word != 8 && bits_per_word != 16)
+- return -EINVAL;
+ if (t->len & ((bits_per_word >> 3) - 1))
+ return -EINVAL;
+ if (speed_hz < c->min_speed_hz || speed_hz > c->max_speed_hz)
+@@ -411,6 +404,7 @@
+ master->setup = txx9spi_setup;
+ master->transfer = txx9spi_transfer;
+ master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
++ master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+
+ ret = spi_register_master(master);
+ if (ret)
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-xcomm.c linux-linaro-stable-mx6/drivers/spi/spi-xcomm.c
+--- linux-3.10.30.orig/drivers/spi/spi-xcomm.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-xcomm.c 2014-05-15 20:34:04.982064187 +0200
+@@ -76,7 +76,7 @@
+ {
+ unsigned int speed;
+
+- if ((t->bits_per_word && t->bits_per_word != 8) || t->len > 62)
++ if (t->len > 62)
+ return -EINVAL;
+
+ speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
+@@ -209,14 +209,6 @@
+ return status;
+ }
+
+-static int spi_xcomm_setup(struct spi_device *spi)
+-{
+- if (spi->bits_per_word != 8)
+- return -EINVAL;
+-
+- return 0;
+-}
+-
+ static int spi_xcomm_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+ {
+@@ -233,8 +225,8 @@
+
+ master->num_chipselect = 16;
+ master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_3WIRE;
++ master->bits_per_word_mask = SPI_BPW_MASK(8);
+ master->flags = SPI_MASTER_HALF_DUPLEX;
+- master->setup = spi_xcomm_setup;
+ master->transfer_one_message = spi_xcomm_transfer_one;
+ master->dev.of_node = i2c->dev.of_node;
+ i2c_set_clientdata(i2c, master);
+diff -Nur linux-3.10.30.orig/drivers/spi/spi-xilinx.c linux-linaro-stable-mx6/drivers/spi/spi-xilinx.c
+--- linux-3.10.30.orig/drivers/spi/spi-xilinx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/spi/spi-xilinx.c 2014-05-15 20:34:04.982064187 +0200
+@@ -232,21 +232,6 @@
+ return 0;
+ }
+
+-static int xilinx_spi_setup(struct spi_device *spi)
+-{
+- /* always return 0, we can not check the number of bits.
+- * There are cases when SPI setup is called before any driver is
+- * there, in that case the SPI core defaults to 8 bits, which we
+- * do not support in some cases. But if we return an error, the
+- * SPI device would not be registered and no driver can get hold of it
+- * When the driver is there, it will call SPI setup again with the
+- * correct number of bits per transfer.
+- * If a driver setups with the wrong bit number, it will fail when
+- * it tries to do a transfer
+- */
+- return 0;
+-}
+-
+ static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
+ {
+ u8 sr;
+@@ -369,11 +354,10 @@
+ master->mode_bits = SPI_CPOL | SPI_CPHA;
+
+ xspi = spi_master_get_devdata(master);
+- xspi->bitbang.master = spi_master_get(master);
++ xspi->bitbang.master = master;
+ xspi->bitbang.chipselect = xilinx_spi_chipselect;
+ xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
+ xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
+- xspi->bitbang.master->setup = xilinx_spi_setup;
+ init_completion(&xspi->done);
+
+ if (!request_mem_region(mem->start, resource_size(mem),
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/dw-hdmi-audio.c linux-linaro-stable-mx6/drivers/staging/imx-drm/dw-hdmi-audio.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/dw-hdmi-audio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/dw-hdmi-audio.c 2014-05-15 20:34:05.754069749 +0200
+@@ -0,0 +1,550 @@
++/*
++ * DesignWare HDMI audio driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * Written and tested against the (alleged) DW HDMI Tx found in iMX6S.
++ */
++#include <linux/io.h>
++#include <linux/interrupt.h>
++
++#include <sound/asoundef.h>
++#include <sound/core.h>
++#include <sound/initval.h>
++#include <sound/pcm.h>
++
++#include "imx-hdmi.h"
++#include "dw-hdmi-audio.h"
++
++#define DRIVER_NAME "dw-hdmi-audio"
++
++/* Provide some bits rather than bit offsets */
++enum {
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST = HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK = HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK,
++ HDMI_AHB_DMA_START_START = BIT(HDMI_AHB_DMA_START_START_OFFSET),
++ HDMI_AHB_DMA_STOP_STOP = BIT(HDMI_AHB_DMA_STOP_STOP_OFFSET),
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL =
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR |
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST |
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY |
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE |
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL |
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY,
++ HDMI_IH_AHBDMAAUD_STAT0_ALL =
++ HDMI_IH_AHBDMAAUD_STAT0_ERROR |
++ HDMI_IH_AHBDMAAUD_STAT0_LOST |
++ HDMI_IH_AHBDMAAUD_STAT0_RETRY |
++ HDMI_IH_AHBDMAAUD_STAT0_DONE |
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL |
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY,
++};
++
++struct snd_dw_hdmi {
++ struct snd_card *card;
++ struct snd_pcm *pcm;
++ void __iomem *base;
++ int irq;
++ struct imx_hdmi *hdmi;
++ struct snd_pcm_substream *substream;
++ void (*reformat)(struct snd_dw_hdmi *, size_t, size_t);
++ void *buf_base;
++ dma_addr_t buf_addr;
++ unsigned buf_offset;
++ unsigned buf_period;
++ unsigned buf_size;
++ unsigned channels;
++ uint8_t revision;
++ uint8_t iec_offset;
++ uint8_t cs[192][8];
++};
++
++static void dw_hdmi_writeb(unsigned long val, void __iomem *ptr)
++{
++ writeb(val, ptr);
++}
++
++static unsigned dw_hdmi_readb(void __iomem *ptr)
++{
++ return readb(ptr);
++}
++
++static void dw_hdmi_writel(unsigned long val, void __iomem *ptr)
++{
++ writeb_relaxed(val, ptr);
++ writeb_relaxed(val >> 8, ptr + 1);
++ writeb_relaxed(val >> 16, ptr + 2);
++ writeb_relaxed(val >> 24, ptr + 3);
++}
++
++/*
++ * Convert to hardware format: The userspace buffer contains IEC958 samples,
++ * with the PCUV bits in bits 31..28 and audio samples in bits 27..4. We
++ * need these to be in bits 27..24, with the IEC B bit in bit 28, and audio
++ * samples in 23..0.
++ *
++ * Default preamble in bits 3..0: 8 = block start, 4 = even 2 = odd
++ *
++ * Ideally, we could do with having the data properly formatted in userspace.
++ */
++static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw,
++ size_t offset, size_t bytes)
++{
++ uint32_t *ptr = dw->buf_base + offset;
++ uint32_t *end = dw->buf_base + offset + bytes;
++
++ do {
++ uint32_t b, sample = *ptr;
++
++ b = (sample & 8) << (28 - 3);
++
++ sample >>= 4;
++
++ *ptr++ = sample | b;
++ } while (ptr < end);
++}
++
++static uint32_t parity(uint32_t sample)
++{
++ sample ^= sample >> 16;
++ sample ^= sample >> 8;
++ sample ^= sample >> 4;
++ sample ^= sample >> 2;
++ sample ^= sample >> 1;
++ return (sample & 1) << 27;
++}
++
++static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw,
++ size_t offset, size_t bytes)
++{
++ uint32_t *ptr = dw->buf_base + offset;
++ uint32_t *end = dw->buf_base + offset + bytes;
++
++ do {
++ unsigned i;
++ uint8_t *cs;
++
++ cs = dw->cs[dw->iec_offset++];
++ if (dw->iec_offset >= 192)
++ dw->iec_offset = 0;
++
++ i = dw->channels;
++ do {
++ uint32_t sample = *ptr;
++
++ sample &= ~0xff000000;
++ sample |= *cs++ << 24;
++ sample |= parity(sample & ~0xf8000000);
++
++ *ptr++ = sample;
++ } while (--i);
++ } while (ptr < end);
++}
++
++static void dw_hdmi_create_cs(struct snd_dw_hdmi *dw,
++ struct snd_pcm_runtime *runtime)
++{
++ uint8_t cs[3];
++ unsigned ch, i, j;
++
++ cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE;
++ cs[1] = IEC958_AES1_CON_GENERAL;
++ cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC;
++ cs[3] = IEC958_AES3_CON_CLOCK_1000PPM;
++
++ switch (runtime->rate) {
++ case 32000:
++ cs[3] |= IEC958_AES3_CON_FS_32000;
++ break;
++ case 44100:
++ cs[3] |= IEC958_AES3_CON_FS_44100;
++ break;
++ case 48000:
++ cs[3] |= IEC958_AES3_CON_FS_48000;
++ break;
++ case 88200:
++ cs[3] |= IEC958_AES3_CON_FS_88200;
++ break;
++ case 96000:
++ cs[3] |= IEC958_AES3_CON_FS_96000;
++ break;
++ case 176400:
++ cs[3] |= IEC958_AES3_CON_FS_176400;
++ break;
++ case 192000:
++ cs[3] |= IEC958_AES3_CON_FS_192000;
++ break;
++ }
++
++ memset(dw->cs, 0, sizeof(dw->cs));
++
++ for (ch = 0; ch < 8; ch++) {
++ cs[2] &= ~IEC958_AES2_CON_CHANNEL;
++ cs[2] |= (ch + 1) << 4;
++
++ for (i = 0; i < ARRAY_SIZE(cs); i++) {
++ unsigned c = cs[i];
++
++ for (j = 0; j < 8; j++, c >>= 1)
++ dw->cs[i * 8 + j][ch] = (c & 1) << 2;
++ }
++ }
++ dw->cs[0][0] |= BIT(4);
++}
++
++static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw)
++{
++ unsigned long start, stop;
++
++ start = dw->buf_addr + dw->buf_offset;
++ stop = start + dw->buf_period - 1;
++
++ dw->reformat(dw, dw->buf_offset, dw->buf_period);
++
++ /* Setup the hardware start/stop addresses */
++ dw_hdmi_writel(start, dw->base + HDMI_AHB_DMA_STRADDR0);
++ dw_hdmi_writel(stop, dw->base + HDMI_AHB_DMA_STPADDR0);
++
++ /* Clear all irqs before enabling irqs and starting DMA */
++ dw_hdmi_writeb(HDMI_IH_AHBDMAAUD_STAT0_ALL,
++ dw->base + HDMI_IH_AHBDMAAUD_STAT0);
++ dw_hdmi_writeb(~HDMI_AHB_DMA_DONE, dw->base + HDMI_AHB_DMA_MASK);
++ dw_hdmi_writeb(HDMI_AHB_DMA_START_START, dw->base + HDMI_AHB_DMA_START);
++}
++
++static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw)
++{
++ dw->substream = NULL;
++
++ /* Disable interrupts before disabling DMA */
++ dw_hdmi_writeb(~0, dw->base + HDMI_AHB_DMA_MASK);
++ dw_hdmi_writeb(HDMI_AHB_DMA_STOP_STOP, dw->base + HDMI_AHB_DMA_STOP);
++}
++
++static irqreturn_t snd_dw_hdmi_irq(int irq, void *data)
++{
++ struct snd_dw_hdmi *dw = data;
++ struct snd_pcm_substream *substream;
++ unsigned stat;
++
++ stat = dw_hdmi_readb(dw->base + HDMI_IH_AHBDMAAUD_STAT0);
++ if (!stat)
++ return IRQ_NONE;
++
++ dw_hdmi_writeb(stat, dw->base + HDMI_IH_AHBDMAAUD_STAT0);
++
++ substream = dw->substream;
++ if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) {
++ dw->buf_offset += dw->buf_period;
++ if (dw->buf_offset >= dw->buf_size)
++ dw->buf_offset = 0;
++
++ snd_pcm_period_elapsed(substream);
++ if (dw->substream)
++ dw_hdmi_start_dma(dw);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static struct snd_pcm_hardware dw_hdmi_hw = {
++ .info = SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID,
++ .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE |
++ SNDRV_PCM_FMTBIT_S24_LE,
++ .rates = SNDRV_PCM_RATE_32000 |
++ SNDRV_PCM_RATE_44100 |
++ SNDRV_PCM_RATE_48000 |
++ SNDRV_PCM_RATE_88200 |
++ SNDRV_PCM_RATE_96000 |
++ SNDRV_PCM_RATE_176400 |
++ SNDRV_PCM_RATE_192000,
++ .channels_min = 2,
++ .channels_max = 8,
++ .buffer_bytes_max = 64 * 1024,
++ .period_bytes_min = 256,
++ .period_bytes_max = 8192, /* ERR004323: must limit to 8k */
++ .periods_min = 2,
++ .periods_max = 16,
++ .fifo_size = 0,
++};
++
++static unsigned rates_mask[] = {
++ SNDRV_PCM_RATE_32000,
++ SNDRV_PCM_RATE_44100,
++ SNDRV_PCM_RATE_48000,
++ SNDRV_PCM_RATE_88200,
++ SNDRV_PCM_RATE_96000,
++ SNDRV_PCM_RATE_176400,
++ SNDRV_PCM_RATE_192000,
++};
++
++static void dw_hdmi_parse_eld(struct snd_dw_hdmi *dw,
++ struct snd_pcm_runtime *runtime)
++{
++ uint8_t *sad, *eld = imx_hdmi_get_eld(dw->hdmi);
++ unsigned eld_ver, mnl, sad_count, rates, rate_mask, i;
++ unsigned max_channels;
++
++ eld_ver = eld[0] >> 3;
++ if (eld_ver != 2 && eld_ver != 31)
++ return;
++
++ mnl = eld[4] & 0x1f;
++ if (mnl > 16)
++ return;
++
++ sad_count = eld[5] >> 4;
++ sad = eld + 20 + mnl;
++
++ /* Start from the basic audio settings */
++ max_channels = 2;
++ rates = 7;
++ while (sad_count > 0) {
++ switch (sad[0] & 0x78) {
++ case 0x08: /* PCM */
++ max_channels = max(max_channels, (sad[0] & 7) + 1u);
++ rates |= sad[1];
++ break;
++ }
++ sad += 3;
++ sad_count -= 1;
++ }
++
++ for (rate_mask = i = 0; i < ARRAY_SIZE(rates_mask); i++)
++ if (rates & 1 << i)
++ rate_mask |= rates_mask[i];
++
++ runtime->hw.rates &= rate_mask;
++ runtime->hw.channels_max = min(runtime->hw.channels_max, max_channels);
++}
++
++static int dw_hdmi_open(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_dw_hdmi *dw = substream->private_data;
++ int ret;
++
++ /* Clear FIFO */
++ dw_hdmi_writeb(HDMI_AHB_DMA_CONF0_SW_FIFO_RST,
++ dw->base + HDMI_AHB_DMA_CONF0);
++
++ /* Configure interrupt polarities */
++ dw_hdmi_writeb(~0, dw->base + HDMI_AHB_DMA_POL);
++ dw_hdmi_writeb(~0, dw->base + HDMI_AHB_DMA_BUFFPOL);
++
++ /* Keep interrupts masked */
++ dw_hdmi_writeb(~0, dw->base + HDMI_AHB_DMA_MASK);
++
++ ret = request_irq(dw->irq, snd_dw_hdmi_irq, IRQF_SHARED,
++ "dw-hdmi-audio", dw);
++ if (ret)
++ return ret;
++
++ /* Un-mute done interrupt */
++ dw_hdmi_writeb(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL &
++ ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE,
++ dw->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++
++ runtime->hw = dw_hdmi_hw;
++ dw_hdmi_parse_eld(dw, runtime);
++ snd_pcm_limit_hw_rates(runtime);
++
++ return 0;
++}
++
++static int dw_hdmi_close(struct snd_pcm_substream *substream)
++{
++ struct snd_dw_hdmi *dw = substream->private_data;
++
++ /* Mute all interrupts */
++ dw_hdmi_writeb(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,
++ dw->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++
++ free_irq(dw->irq, dw);
++
++ return 0;
++}
++
++static int dw_hdmi_hw_free(struct snd_pcm_substream *substream)
++{
++ return snd_pcm_lib_free_pages(substream);
++}
++
++static int dw_hdmi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ return snd_pcm_lib_malloc_pages(substream,
++ params_buffer_bytes(params));
++}
++
++static int dw_hdmi_prepare(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_dw_hdmi *dw = substream->private_data;
++ uint8_t threshold, conf0, conf1;
++
++ /* Setup as per 3.0.5 FSL 4.1.0 BSP */
++ switch (dw->revision) {
++ case 0x0a:
++ conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
++ HDMI_AHB_DMA_CONF0_INCR4;
++ if (runtime->channels == 2)
++ threshold = 126;
++ else
++ threshold = 124;
++ break;
++ case 0x1a:
++ conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE |
++ HDMI_AHB_DMA_CONF0_INCR8;
++ threshold = 128;
++ break;
++ default:
++ /* NOTREACHED */
++ return -EINVAL;
++ }
++
++ imx_hdmi_set_sample_rate(dw->hdmi, runtime->rate);
++
++ /* Minimum number of bytes in the fifo. */
++ runtime->hw.fifo_size = threshold * 32;
++
++ conf0 |= HDMI_AHB_DMA_CONF0_EN_HLOCK;
++ conf1 = (1 << runtime->channels) - 1;
++
++ dw_hdmi_writeb(threshold, dw->base + HDMI_AHB_DMA_THRSLD);
++ dw_hdmi_writeb(conf0, dw->base + HDMI_AHB_DMA_CONF0);
++ dw_hdmi_writeb(conf1, dw->base + HDMI_AHB_DMA_CONF1);
++
++ switch (runtime->format) {
++ case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
++ dw->reformat = dw_hdmi_reformat_iec958;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ dw_hdmi_create_cs(dw, runtime);
++ dw->reformat = dw_hdmi_reformat_s24;
++ break;
++ }
++ dw->iec_offset = 0;
++ dw->channels = runtime->channels;
++ dw->buf_base = runtime->dma_area;
++ dw->buf_addr = runtime->dma_addr;
++ dw->buf_period = snd_pcm_lib_period_bytes(substream);
++ dw->buf_size = snd_pcm_lib_buffer_bytes(substream);
++
++ return 0;
++}
++
++static int dw_hdmi_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ struct snd_dw_hdmi *dw = substream->private_data;
++ int ret = 0;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ dw->buf_offset = 0;
++ dw->substream = substream;
++ dw_hdmi_start_dma(dw);
++ break;
++
++ case SNDRV_PCM_TRIGGER_STOP:
++ dw_hdmi_stop_dma(dw);
++ break;
++
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++static snd_pcm_uframes_t dw_hdmi_pointer(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_dw_hdmi *dw = substream->private_data;
++
++ return bytes_to_frames(runtime, dw->buf_offset);
++}
++
++static struct snd_pcm_ops snd_dw_hdmi_ops = {
++ .open = dw_hdmi_open,
++ .close = dw_hdmi_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = dw_hdmi_hw_params,
++ .hw_free = dw_hdmi_hw_free,
++ .prepare = dw_hdmi_prepare,
++ .trigger = dw_hdmi_trigger,
++ .pointer = dw_hdmi_pointer,
++};
++
++int snd_dw_hdmi_probe(struct snd_dw_hdmi **dwp, struct device *dev,
++ void __iomem *base, int irq, struct imx_hdmi *hdmi)
++{
++ struct snd_dw_hdmi *dw;
++ struct snd_card *card;
++ struct snd_pcm *pcm;
++ unsigned revision;
++ int ret;
++
++ dw_hdmi_writeb(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL,
++ base + HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ revision = dw_hdmi_readb(base + HDMI_REVISION_ID);
++ if (revision != 0x0a && revision != 0x1a) {
++ dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n",
++ revision);
++ return -ENXIO;
++ }
++
++ ret = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
++ THIS_MODULE, sizeof(struct snd_dw_hdmi), &card);
++ if (ret < 0)
++ return ret;
++
++ snd_card_set_dev(card, dev);
++
++ strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
++ strlcpy(card->shortname, "DW-HDMI", sizeof(card->shortname));
++ snprintf(card->longname, sizeof(card->longname),
++ "%s rev 0x%02x, irq %d", card->shortname, revision, irq);
++
++ dw = card->private_data;
++ dw->card = card;
++ dw->base = base;
++ dw->irq = irq;
++ dw->hdmi = hdmi;
++ dw->revision = revision;
++
++ ret = snd_pcm_new(card, "DW HDMI", 0, 1, 0, &pcm);
++ if (ret < 0)
++ goto err;
++
++ dw->pcm = pcm;
++ pcm->private_data = dw;
++ strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dw_hdmi_ops);
++
++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
++ NULL, 0, 64 * 1024);
++
++ ret = snd_card_register(card);
++ if (ret < 0)
++ goto err;
++
++ *dwp = dw;
++
++ return 0;
++
++err:
++ snd_card_free(card);
++ return ret;
++}
++
++void snd_dw_hdmi_remove(struct snd_dw_hdmi *dw)
++{
++ snd_card_free(dw->card);
++}
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/dw-hdmi-audio.h linux-linaro-stable-mx6/drivers/staging/imx-drm/dw-hdmi-audio.h
+--- linux-3.10.30.orig/drivers/staging/imx-drm/dw-hdmi-audio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/dw-hdmi-audio.h 2014-05-15 20:34:05.754069749 +0200
+@@ -0,0 +1,13 @@
++#ifndef DW_HDMI_AUDIO_H
++#define DW_HDMI_AUDIO_H
++
++#include <linux/irqreturn.h>
++
++struct snd_dw_hdmi;
++struct imx_hdmi;
++
++int snd_dw_hdmi_probe(struct snd_dw_hdmi **dwp, struct device *,
++ void __iomem *, int, struct imx_hdmi *);
++void snd_dw_hdmi_remove(struct snd_dw_hdmi *dw);
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/dw-hdmi-cec.c linux-linaro-stable-mx6/drivers/staging/imx-drm/dw-hdmi-cec.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/dw-hdmi-cec.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/dw-hdmi-cec.c 2014-05-15 20:34:05.754069749 +0200
+@@ -0,0 +1,561 @@
++/* http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c?h=imx_3.0.35_4.1.0 */
++#include <linux/cdev.h>
++#include <linux/device.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/list.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/wait.h>
++
++#include "imx-hdmi.h"
++#include "dw-hdmi-cec.h"
++
++#define MAX_MESSAGE_LEN 16
++#define DEV_NAME "mxc_hdmi_cec"
++
++enum {
++ CEC_STAT_DONE = BIT(0),
++ CEC_STAT_EOM = BIT(1),
++ CEC_STAT_NACK = BIT(2),
++ CEC_STAT_ARBLOST = BIT(3),
++ CEC_STAT_ERROR_INIT = BIT(4),
++ CEC_STAT_ERROR_FOLL = BIT(5),
++ CEC_STAT_WAKEUP = BIT(6),
++
++ CEC_CTRL_START = BIT(0),
++ CEC_CTRL_NORMAL = 1 << 1,
++};
++
++static struct class *cec_class;
++static int cec_major;
++
++struct dw_hdmi_cec {
++ struct device *dev;
++ struct cdev cdev;
++ void __iomem *base;
++ const struct dw_hdmi_cec_ops *ops;
++ void *ops_data;
++ int irq;
++
++ struct mutex mutex;
++ unsigned users;
++
++ spinlock_t lock;
++ wait_queue_head_t waitq;
++ struct list_head events;
++ uint8_t write_busy;
++
++ uint8_t retries;
++ uint16_t addresses;
++ uint16_t physical;
++};
++
++enum {
++ MESSAGE_TYPE_RECEIVE_SUCCESS = 1,
++ MESSAGE_TYPE_NOACK,
++ MESSAGE_TYPE_DISCONNECTED,
++ MESSAGE_TYPE_CONNECTED,
++ MESSAGE_TYPE_SEND_SUCCESS,
++ MESSAGE_TYPE_SEND_ERROR,
++};
++
++enum {
++ HDMICEC_IOC_MAGIC = 'H',
++ /* This is wrong: we pass the argument as a number, not a pointer */
++ HDMICEC_IOC_O_SETLOGICALADDRESS = _IOW(HDMICEC_IOC_MAGIC, 1, unsigned char),
++ HDMICEC_IOC_SETLOGICALADDRESS = _IO(HDMICEC_IOC_MAGIC, 1),
++ HDMICEC_IOC_STARTDEVICE = _IO(HDMICEC_IOC_MAGIC, 2),
++ HDMICEC_IOC_STOPDEVICE = _IO(HDMICEC_IOC_MAGIC, 3),
++ HDMICEC_IOC_GETPHYADDRESS = _IOR(HDMICEC_IOC_MAGIC, 4, unsigned char[4]),
++};
++
++struct dw_hdmi_cec_user_event {
++ uint32_t event_type;
++ uint32_t msg_len;
++ uint8_t msg[MAX_MESSAGE_LEN];
++};
++
++struct dw_hdmi_cec_event {
++ struct dw_hdmi_cec_user_event usr;
++ struct list_head node;
++};
++
++static void dw_hdmi_event(struct dw_hdmi_cec *cec, int type)
++{
++ struct dw_hdmi_cec_event *event;
++ unsigned long flags;
++
++ event = kzalloc(sizeof(*event), GFP_ATOMIC);
++ if (event) {
++ event->usr.event_type = type;
++
++ if (type == MESSAGE_TYPE_RECEIVE_SUCCESS) {
++ unsigned i;
++
++ event->usr.msg_len = readb(cec->base + HDMI_CEC_RX_CNT);
++
++ for (i = 0; i < event->usr.msg_len; i++)
++ event->usr.msg[i] = readb(cec->base + HDMI_CEC_RX_DATA0 + i);
++
++ writeb(0, cec->base + HDMI_CEC_LOCK);
++ }
++
++ spin_lock_irqsave(&cec->lock, flags);
++ list_add_tail(&event->node, &cec->events);
++ spin_unlock_irqrestore(&cec->lock, flags);
++ wake_up(&cec->waitq);
++ }
++}
++
++static void dw_hdmi_set_address(struct dw_hdmi_cec *cec)
++{
++ writeb(cec->addresses & 255, cec->base + HDMI_CEC_ADDR_L);
++ writeb(cec->addresses >> 8, cec->base + HDMI_CEC_ADDR_H);
++}
++
++static void dw_hdmi_send_message(struct dw_hdmi_cec *cec, uint8_t *msg,
++ size_t count)
++{
++ unsigned long flags;
++ unsigned i;
++
++ for (i = 0; i < count; i++)
++ writeb(msg[i], cec->base + HDMI_CEC_TX_DATA0 + i);
++
++ writeb(count, cec->base + HDMI_CEC_TX_CNT);
++
++ spin_lock_irqsave(&cec->lock, flags);
++ cec->retries = 5;
++ cec->write_busy = 1;
++ writeb(CEC_CTRL_NORMAL | CEC_CTRL_START, cec->base + HDMI_CEC_CTRL);
++ spin_unlock_irqrestore(&cec->lock, flags);
++}
++
++static int dw_hdmi_lock_write(struct dw_hdmi_cec *cec, struct file *file)
++ __acquires(cec->mutex)
++{
++ int ret;
++
++ do {
++ if (file->f_flags & O_NONBLOCK) {
++ if (cec->write_busy)
++ return -EAGAIN;
++ } else {
++ ret = wait_event_interruptible(cec->waitq,
++ !cec->write_busy);
++ if (ret)
++ break;
++ }
++
++ ret = mutex_lock_interruptible(&cec->mutex);
++ if (ret)
++ break;
++
++ if (!cec->write_busy)
++ break;
++
++ mutex_unlock(&cec->mutex);
++ } while (1);
++
++ return ret;
++}
++
++static irqreturn_t dw_hdmi_cec_irq(int irq, void *data)
++{
++ struct dw_hdmi_cec *cec = data;
++ unsigned stat = readb(cec->base + HDMI_IH_CEC_STAT0);
++
++ if (stat == 0)
++ return IRQ_NONE;
++
++ writeb(stat, cec->base + HDMI_IH_CEC_STAT0);
++
++ if (stat & CEC_STAT_ERROR_INIT) {
++ if (cec->retries) {
++ unsigned v = readb(cec->base + HDMI_CEC_CTRL);
++ writeb(v | CEC_CTRL_START, cec->base + HDMI_CEC_CTRL);
++ cec->retries -= 1;
++ } else {
++ cec->write_busy = 0;
++ dw_hdmi_event(cec, MESSAGE_TYPE_SEND_ERROR);
++ }
++ } else if (stat & (CEC_STAT_DONE | CEC_STAT_NACK)) {
++ cec->retries = 0;
++ cec->write_busy = 0;
++ if (stat & CEC_STAT_DONE) {
++ dw_hdmi_event(cec, MESSAGE_TYPE_SEND_SUCCESS);
++ } else {
++ dw_hdmi_event(cec, MESSAGE_TYPE_NOACK);
++ }
++ }
++
++ if (stat & CEC_STAT_EOM)
++ dw_hdmi_event(cec, MESSAGE_TYPE_RECEIVE_SUCCESS);
++
++ return IRQ_HANDLED;
++}
++EXPORT_SYMBOL(dw_hdmi_cec_irq);
++
++static ssize_t dw_hdmi_cec_read(struct file *file, char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ struct dw_hdmi_cec *cec = file->private_data;
++ ssize_t ret;
++
++ if (count > sizeof(struct dw_hdmi_cec_user_event))
++ count = sizeof(struct dw_hdmi_cec_user_event);
++
++ if (!access_ok(VERIFY_WRITE, buf, count))
++ return -EFAULT;
++
++ do {
++ struct dw_hdmi_cec_event *event = NULL;
++ unsigned long flags;
++
++ spin_lock_irqsave(&cec->lock, flags);
++ if (!list_empty(&cec->events)) {
++ event = list_first_entry(&cec->events,
++ struct dw_hdmi_cec_event, node);
++ list_del(&event->node);
++ }
++ spin_unlock_irqrestore(&cec->lock, flags);
++
++ if (event) {
++ ret = __copy_to_user(buf, &event->usr, count) ?
++ -EFAULT : count;
++ kfree(event);
++ break;
++ }
++
++ if (file->f_flags & O_NONBLOCK) {
++ ret = -EAGAIN;
++ break;
++ }
++
++ ret = wait_event_interruptible(cec->waitq,
++ !list_empty(&cec->events));
++ if (ret)
++ break;
++ } while (1);
++
++ return ret;
++}
++
++static ssize_t dw_hdmi_cec_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ struct dw_hdmi_cec *cec = file->private_data;
++ uint8_t msg[MAX_MESSAGE_LEN];
++ int ret;
++
++ if (count > sizeof(msg))
++ return -E2BIG;
++
++ if (copy_from_user(msg, buf, count))
++ return -EFAULT;
++
++ ret = dw_hdmi_lock_write(cec, file);
++ if (ret)
++ return ret;
++
++ dw_hdmi_send_message(cec, msg, count);
++
++ mutex_unlock(&cec->mutex);
++
++ return count;
++}
++
++static long dw_hdmi_cec_ioctl(struct file *file, u_int cmd, unsigned long arg)
++{
++ struct dw_hdmi_cec *cec = file->private_data;
++ int ret;
++
++ switch (cmd) {
++ case HDMICEC_IOC_O_SETLOGICALADDRESS:
++ case HDMICEC_IOC_SETLOGICALADDRESS:
++ if (arg > 15) {
++ ret = -EINVAL;
++ break;
++ }
++
++ ret = dw_hdmi_lock_write(cec, file);
++ if (ret == 0) {
++ unsigned char msg[1];
++
++ cec->addresses = BIT(arg);
++ dw_hdmi_set_address(cec);
++
++ /*
++ * Send a ping message with the source and destination
++ * set to our address; the result indicates whether
++ * unit has chosen our address simultaneously.
++ */
++ msg[0] = arg << 4 | arg;
++ dw_hdmi_send_message(cec, msg, sizeof(msg));
++ mutex_unlock(&cec->mutex);
++ }
++ break;
++
++ case HDMICEC_IOC_STARTDEVICE:
++ ret = mutex_lock_interruptible(&cec->mutex);
++ if (ret == 0) {
++ cec->addresses = BIT(15);
++ dw_hdmi_set_address(cec);
++ mutex_unlock(&cec->mutex);
++ }
++ break;
++
++ case HDMICEC_IOC_STOPDEVICE:
++ ret = 0;
++ break;
++
++ case HDMICEC_IOC_GETPHYADDRESS:
++ ret = put_user(cec->physical, (uint16_t __user *)arg);
++ ret = -ENOIOCTLCMD;
++ break;
++
++ default:
++ ret = -ENOIOCTLCMD;
++ break;
++ }
++
++ return ret;
++}
++
++static unsigned dw_hdmi_cec_poll(struct file *file, poll_table *wait)
++{
++ struct dw_hdmi_cec *cec = file->private_data;
++ unsigned mask = 0;
++
++ poll_wait(file, &cec->waitq, wait);
++
++ if (cec->write_busy == 0)
++ mask |= POLLOUT | POLLWRNORM;
++ if (!list_empty(&cec->events))
++ mask |= POLLIN | POLLRDNORM;
++
++ return mask;
++}
++
++static int dw_hdmi_cec_open(struct inode *inode, struct file *file)
++{
++ struct dw_hdmi_cec *cec = container_of(inode->i_cdev,
++ struct dw_hdmi_cec, cdev);
++ int ret = 0;
++
++ nonseekable_open(inode, file);
++
++ file->private_data = cec;
++
++ ret = mutex_lock_interruptible(&cec->mutex);
++ if (ret)
++ return ret;
++
++ if (cec->users++ == 0) {
++ unsigned irqs;
++
++ writeb(0, cec->base + HDMI_CEC_CTRL);
++ writeb(~0, cec->base + HDMI_IH_CEC_STAT0);
++ writeb(0, cec->base + HDMI_CEC_LOCK);
++
++ ret = request_irq(cec->irq, dw_hdmi_cec_irq, IRQF_SHARED,
++ DEV_NAME, cec);
++ if (ret < 0) {
++ cec->users = 0;
++ goto unlock;
++ }
++
++ cec->addresses = BIT(15);
++ dw_hdmi_set_address(cec);
++
++ cec->ops->enable(cec->ops_data);
++
++ irqs = CEC_STAT_ERROR_INIT | CEC_STAT_NACK | CEC_STAT_EOM |
++ CEC_STAT_DONE;
++ writeb(irqs, cec->base + HDMI_CEC_POLARITY);
++ writeb(~irqs, cec->base + HDMI_CEC_MASK);
++ writeb(~irqs, cec->base + HDMI_IH_MUTE_CEC_STAT0);
++ }
++ unlock:
++ mutex_unlock(&cec->mutex);
++
++ return ret;
++}
++
++static int dw_hdmi_cec_release(struct inode *inode, struct file *file)
++{
++ struct dw_hdmi_cec *cec = file->private_data;
++
++ mutex_lock(&cec->mutex);
++ if (cec->users >= 1)
++ cec->users -= 1;
++ if (cec->users == 0) {
++ /*
++ * Wait for any write to complete before shutting down.
++ * A message should complete in a maximum of 2.75ms *
++ * 160 bits + 4.7ms, or 444.7ms. Let's call that 500ms.
++ * If we time out, shutdown anyway.
++ */
++ wait_event_timeout(cec->waitq, !cec->write_busy,
++ msecs_to_jiffies(500));
++
++ writeb(~0, cec->base + HDMI_CEC_MASK);
++ writeb(~0, cec->base + HDMI_IH_MUTE_CEC_STAT0);
++ writeb(0, cec->base + HDMI_CEC_POLARITY);
++
++ free_irq(cec->irq, cec);
++
++ cec->ops->disable(cec->ops_data);
++
++ while (!list_empty(&cec->events)) {
++ struct dw_hdmi_cec_event *event;
++
++ event = list_first_entry(&cec->events,
++ struct dw_hdmi_cec_event, node);
++ list_del(&event->node);
++ kfree(event);
++ }
++ }
++ mutex_unlock(&cec->mutex);
++ return 0;
++}
++
++static const struct file_operations hdmi_cec_fops = {
++ .owner = THIS_MODULE,
++ .read = dw_hdmi_cec_read,
++ .write = dw_hdmi_cec_write,
++ .open = dw_hdmi_cec_open,
++ .unlocked_ioctl = dw_hdmi_cec_ioctl,
++ .release = dw_hdmi_cec_release,
++ .poll = dw_hdmi_cec_poll,
++};
++
++static int dw_hdmi_cec_probe(struct platform_device *pdev)
++{
++ struct dw_hdmi_cec_data *data = dev_get_platdata(&pdev->dev);
++ struct dw_hdmi_cec *cec;
++ struct device *cd;
++ dev_t devn = MKDEV(cec_major, 0);
++ int ret;
++
++ if (!data)
++ return -ENXIO;
++
++ cec = devm_kzalloc(&pdev->dev, sizeof(*cec), GFP_KERNEL);
++ if (!cec)
++ return -ENOMEM;
++
++ cec->dev = &pdev->dev;
++ cec->base = data->base;
++ cec->irq = data->irq;
++ cec->ops = data->ops;
++ cec->ops_data = data->ops_data;
++
++ INIT_LIST_HEAD(&cec->events);
++ init_waitqueue_head(&cec->waitq);
++ spin_lock_init(&cec->lock);
++ mutex_init(&cec->mutex);
++
++ /* FIXME: soft-reset the CEC interface */
++
++ cec->addresses = BIT(15);
++ dw_hdmi_set_address(cec);
++ writeb(0, cec->base + HDMI_CEC_TX_CNT);
++ writeb(~0, cec->base + HDMI_CEC_MASK);
++ writeb(~0, cec->base + HDMI_IH_MUTE_CEC_STAT0);
++ writeb(0, cec->base + HDMI_CEC_POLARITY);
++
++ cdev_init(&cec->cdev, &hdmi_cec_fops);
++ cec->cdev.owner = THIS_MODULE;
++ ret = cdev_add(&cec->cdev, devn, 1);
++ if (ret < 0)
++ goto err_cdev;
++
++ cd = device_create(cec_class, cec->dev, devn, NULL, DEV_NAME);
++ if (IS_ERR(cd)) {
++ ret = PTR_ERR(cd);
++ dev_err(cec->dev, "can't create device: %d\n", ret);
++ goto err_dev;
++ }
++
++ return 0;
++
++ err_dev:
++ cdev_del(&cec->cdev);
++ err_cdev:
++ return ret;
++}
++
++static int dw_hdmi_cec_remove(struct platform_device *pdev)
++{
++ struct dw_hdmi_cec *cec = platform_get_drvdata(pdev);
++ dev_t devn = MKDEV(cec_major, 0);
++
++ device_destroy(cec_class, devn);
++ cdev_del(&cec->cdev);
++
++ return 0;
++}
++
++static struct platform_driver dw_hdmi_cec_driver = {
++ .probe = dw_hdmi_cec_probe,
++ .remove = dw_hdmi_cec_remove,
++ .driver = {
++ .name = "dw-hdmi-cec",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int dw_hdmi_cec_init(void)
++{
++ dev_t dev;
++ int ret;
++
++ cec_class = class_create(THIS_MODULE, DEV_NAME);
++ if (IS_ERR(cec_class)) {
++ ret = PTR_ERR(cec_class);
++ pr_err("cec: can't create cec class: %d\n", ret);
++ goto err_class;
++ }
++
++ ret = alloc_chrdev_region(&dev, 0, 1, DEV_NAME);
++ if (ret) {
++ pr_err("cec: can't create character devices: %d\n", ret);
++ goto err_chrdev;
++ }
++
++ cec_major = MAJOR(dev);
++
++ ret = platform_driver_register(&dw_hdmi_cec_driver);
++ if (ret)
++ goto err_driver;
++
++ return 0;
++
++ err_driver:
++ unregister_chrdev_region(MKDEV(cec_major, 0), 1);
++ err_chrdev:
++ class_destroy(cec_class);
++ err_class:
++ return ret;
++}
++module_init(dw_hdmi_cec_init);
++
++static void dw_hdmi_cec_exit(void)
++{
++ platform_driver_unregister(&dw_hdmi_cec_driver);
++ unregister_chrdev_region(MKDEV(cec_major, 0), 1);
++ class_destroy(cec_class);
++}
++module_exit(dw_hdmi_cec_exit);
++
++MODULE_AUTHOR("Russell King <rmk+kernel@arm.linux.org.uk>");
++MODULE_DESCRIPTION("Synopsis Designware HDMI CEC driver for i.MX");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS(PLATFORM_MODULE_PREFIX "dw-hdmi-cec");
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/dw-hdmi-cec.h linux-linaro-stable-mx6/drivers/staging/imx-drm/dw-hdmi-cec.h
+--- linux-3.10.30.orig/drivers/staging/imx-drm/dw-hdmi-cec.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/dw-hdmi-cec.h 2014-05-15 20:34:05.754069749 +0200
+@@ -0,0 +1,16 @@
++#ifndef DW_HDMI_CEC_H
++#define DW_HDMI_CEC_H
++
++struct dw_hdmi_cec_ops {
++ void (*enable)(void *);
++ void (*disable)(void *);
++};
++
++struct dw_hdmi_cec_data {
++ void __iomem *base;
++ int irq;
++ const struct dw_hdmi_cec_ops *ops;
++ void *ops_data;
++};
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/imx-drm-core.c linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-drm-core.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/imx-drm-core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-drm-core.c 2014-05-15 20:34:05.754069749 +0200
+@@ -13,14 +13,14 @@
+ * GNU General Public License for more details.
+ *
+ */
+-
++#include <linux/component.h>
+ #include <linux/device.h>
++#include <linux/fb.h>
++#include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
+-#include <linux/fb.h>
+-#include <linux/module.h>
+ #include <drm/drm_gem_cma_helper.h>
+ #include <drm/drm_fb_cma_helper.h>
+
+@@ -28,151 +28,125 @@
+
+ #define MAX_CRTC 4
+
+-struct crtc_cookie {
+- void *cookie;
+- int id;
+- struct list_head list;
+-};
++struct imx_drm_crtc;
+
+ struct imx_drm_device {
+ struct drm_device *drm;
+- struct device *dev;
+- struct list_head crtc_list;
+- struct list_head encoder_list;
+- struct list_head connector_list;
+- struct mutex mutex;
+- int references;
++ struct imx_drm_crtc *crtc[MAX_CRTC];
+ int pipes;
+ struct drm_fbdev_cma *fbhelper;
+ };
+
+ struct imx_drm_crtc {
+ struct drm_crtc *crtc;
+- struct list_head list;
+- struct imx_drm_device *imxdrm;
+ int pipe;
+ struct imx_drm_crtc_helper_funcs imx_drm_helper_funcs;
+- struct module *owner;
+- struct crtc_cookie cookie;
++ void *cookie;
++ int di_id;
++ int ipu_id;
+ };
+
+-struct imx_drm_encoder {
+- struct drm_encoder *encoder;
+- struct list_head list;
+- struct module *owner;
+- struct list_head possible_crtcs;
+-};
++static int legacyfb_depth = 16;
++module_param(legacyfb_depth, int, 0444);
+
+-struct imx_drm_connector {
+- struct drm_connector *connector;
+- struct list_head list;
+- struct module *owner;
+-};
+-
+-static int imx_drm_driver_firstopen(struct drm_device *drm)
++int imx_drm_crtc_id(struct imx_drm_crtc *crtc)
+ {
+- if (!imx_drm_device_get())
+- return -EINVAL;
+-
+- return 0;
++ return crtc->pipe;
+ }
++EXPORT_SYMBOL_GPL(imx_drm_crtc_id);
+
+ static void imx_drm_driver_lastclose(struct drm_device *drm)
+ {
++#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
+ struct imx_drm_device *imxdrm = drm->dev_private;
+
+ if (imxdrm->fbhelper)
+ drm_fbdev_cma_restore_mode(imxdrm->fbhelper);
+-
+- imx_drm_device_put();
++#endif
+ }
+
+ static int imx_drm_driver_unload(struct drm_device *drm)
+ {
++#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
+ struct imx_drm_device *imxdrm = drm->dev_private;
++#endif
+
+- drm_mode_config_cleanup(imxdrm->drm);
+- drm_kms_helper_poll_fini(imxdrm->drm);
++ drm_kms_helper_poll_fini(drm);
++
++#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
++ if (imxdrm->fbhelper)
++ drm_fbdev_cma_fini(imxdrm->fbhelper);
++#endif
++
++ component_unbind_all(drm->dev, drm);
++
++ drm_vblank_cleanup(drm);
++ drm_mode_config_cleanup(drm);
+
+ return 0;
+ }
+
+-/*
+- * We don't care at all for crtc numbers, but the core expects the
+- * crtcs to be numbered
+- */
+-static struct imx_drm_crtc *imx_drm_crtc_by_num(struct imx_drm_device *imxdrm,
+- int num)
++struct imx_drm_crtc *imx_drm_find_crtc(struct drm_crtc *crtc)
+ {
+- struct imx_drm_crtc *imx_drm_crtc;
++ struct imx_drm_device *imxdrm = crtc->dev->dev_private;
++ unsigned i;
++
++ for (i = 0; i < MAX_CRTC; i++)
++ if (imxdrm->crtc[i] && imxdrm->crtc[i]->crtc == crtc)
++ return imxdrm->crtc[i];
+
+- list_for_each_entry(imx_drm_crtc, &imxdrm->crtc_list, list)
+- if (imx_drm_crtc->pipe == num)
+- return imx_drm_crtc;
+ return NULL;
+ }
+
+-int imx_drm_crtc_panel_format_pins(struct drm_crtc *crtc, u32 encoder_type,
++int imx_drm_panel_format_pins(struct drm_encoder *encoder,
+ u32 interface_pix_fmt, int hsync_pin, int vsync_pin)
+ {
+- struct imx_drm_device *imxdrm = crtc->dev->dev_private;
+- struct imx_drm_crtc *imx_crtc;
+ struct imx_drm_crtc_helper_funcs *helper;
++ struct imx_drm_crtc *imx_crtc;
+
+- mutex_lock(&imxdrm->mutex);
+-
+- list_for_each_entry(imx_crtc, &imxdrm->crtc_list, list)
+- if (imx_crtc->crtc == crtc)
+- goto found;
+-
+- mutex_unlock(&imxdrm->mutex);
+-
+- return -EINVAL;
+-found:
+- mutex_unlock(&imxdrm->mutex);
++ imx_crtc = imx_drm_find_crtc(encoder->crtc);
++ if (!imx_crtc)
++ return -EINVAL;
+
+ helper = &imx_crtc->imx_drm_helper_funcs;
+ if (helper->set_interface_pix_fmt)
+- return helper->set_interface_pix_fmt(crtc,
+- encoder_type, interface_pix_fmt,
++ return helper->set_interface_pix_fmt(encoder->crtc,
++ encoder->encoder_type, interface_pix_fmt,
+ hsync_pin, vsync_pin);
+ return 0;
+ }
+-EXPORT_SYMBOL_GPL(imx_drm_crtc_panel_format_pins);
++EXPORT_SYMBOL_GPL(imx_drm_panel_format_pins);
+
+-int imx_drm_crtc_panel_format(struct drm_crtc *crtc, u32 encoder_type,
+- u32 interface_pix_fmt)
++int imx_drm_panel_format(struct drm_encoder *encoder, u32 interface_pix_fmt)
+ {
+- return imx_drm_crtc_panel_format_pins(crtc, encoder_type,
+- interface_pix_fmt, 0, 0);
++ return imx_drm_panel_format_pins(encoder, interface_pix_fmt, 2, 3);
+ }
+-EXPORT_SYMBOL_GPL(imx_drm_crtc_panel_format);
++EXPORT_SYMBOL_GPL(imx_drm_panel_format);
+
+ int imx_drm_crtc_vblank_get(struct imx_drm_crtc *imx_drm_crtc)
+ {
+- return drm_vblank_get(imx_drm_crtc->imxdrm->drm, imx_drm_crtc->pipe);
++ return drm_vblank_get(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_crtc_vblank_get);
+
+ void imx_drm_crtc_vblank_put(struct imx_drm_crtc *imx_drm_crtc)
+ {
+- drm_vblank_put(imx_drm_crtc->imxdrm->drm, imx_drm_crtc->pipe);
++ drm_vblank_put(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_crtc_vblank_put);
+
+ void imx_drm_handle_vblank(struct imx_drm_crtc *imx_drm_crtc)
+ {
+- drm_handle_vblank(imx_drm_crtc->imxdrm->drm, imx_drm_crtc->pipe);
++ drm_handle_vblank(imx_drm_crtc->crtc->dev, imx_drm_crtc->pipe);
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_handle_vblank);
+
+ static int imx_drm_enable_vblank(struct drm_device *drm, int crtc)
+ {
+ struct imx_drm_device *imxdrm = drm->dev_private;
+- struct imx_drm_crtc *imx_drm_crtc;
++ struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc];
+ int ret;
+
+- imx_drm_crtc = imx_drm_crtc_by_num(imxdrm, crtc);
+ if (!imx_drm_crtc)
+ return -EINVAL;
+
+@@ -188,9 +162,8 @@
+ static void imx_drm_disable_vblank(struct drm_device *drm, int crtc)
+ {
+ struct imx_drm_device *imxdrm = drm->dev_private;
+- struct imx_drm_crtc *imx_drm_crtc;
++ struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc];
+
+- imx_drm_crtc = imx_drm_crtc_by_num(imxdrm, crtc);
+ if (!imx_drm_crtc)
+ return;
+
+@@ -200,6 +173,18 @@
+ imx_drm_crtc->imx_drm_helper_funcs.disable_vblank(imx_drm_crtc->crtc);
+ }
+
++static void imx_drm_driver_preclose(struct drm_device *drm,
++ struct drm_file *file)
++{
++ int i;
++
++ if (!file->is_master)
++ return;
++
++ for (i = 0; i < MAX_CRTC; i++)
++ imx_drm_disable_vblank(drm, i);
++}
++
+ static const struct file_operations imx_drm_driver_fops = {
+ .owner = THIS_MODULE,
+ .open = drm_open,
+@@ -207,337 +192,207 @@
+ .unlocked_ioctl = drm_ioctl,
+ .mmap = drm_gem_cma_mmap,
+ .poll = drm_poll,
+- .fasync = drm_fasync,
+ .read = drm_read,
+ .llseek = noop_llseek,
+ };
+
+-static struct imx_drm_device *imx_drm_device;
+-
+-static struct imx_drm_device *__imx_drm_device(void)
++int imx_drm_connector_mode_valid(struct drm_connector *connector,
++ struct drm_display_mode *mode)
+ {
+- return imx_drm_device;
++ return MODE_OK;
+ }
++EXPORT_SYMBOL(imx_drm_connector_mode_valid);
+
+-struct drm_device *imx_drm_device_get(void)
++void imx_drm_connector_destroy(struct drm_connector *connector)
+ {
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- struct imx_drm_encoder *enc;
+- struct imx_drm_connector *con;
+- struct imx_drm_crtc *crtc;
+-
+- mutex_lock(&imxdrm->mutex);
+-
+- list_for_each_entry(enc, &imxdrm->encoder_list, list) {
+- if (!try_module_get(enc->owner)) {
+- dev_err(imxdrm->dev, "could not get module %s\n",
+- module_name(enc->owner));
+- goto unwind_enc;
+- }
+- }
+-
+- list_for_each_entry(con, &imxdrm->connector_list, list) {
+- if (!try_module_get(con->owner)) {
+- dev_err(imxdrm->dev, "could not get module %s\n",
+- module_name(con->owner));
+- goto unwind_con;
+- }
+- }
+-
+- list_for_each_entry(crtc, &imxdrm->crtc_list, list) {
+- if (!try_module_get(crtc->owner)) {
+- dev_err(imxdrm->dev, "could not get module %s\n",
+- module_name(crtc->owner));
+- goto unwind_crtc;
+- }
+- }
+-
+- imxdrm->references++;
+-
+- mutex_unlock(&imxdrm->mutex);
+-
+- return imxdrm->drm;
+-
+-unwind_crtc:
+- list_for_each_entry_continue_reverse(crtc, &imxdrm->crtc_list, list)
+- module_put(crtc->owner);
+-unwind_con:
+- list_for_each_entry_continue_reverse(con, &imxdrm->connector_list, list)
+- module_put(con->owner);
+-unwind_enc:
+- list_for_each_entry_continue_reverse(enc, &imxdrm->encoder_list, list)
+- module_put(enc->owner);
+-
+- mutex_unlock(&imxdrm->mutex);
+-
+- return NULL;
+-
+-}
+-EXPORT_SYMBOL_GPL(imx_drm_device_get);
+-
+-void imx_drm_device_put(void)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- struct imx_drm_encoder *enc;
+- struct imx_drm_connector *con;
+- struct imx_drm_crtc *crtc;
+-
+- mutex_lock(&imxdrm->mutex);
+-
+- list_for_each_entry(crtc, &imxdrm->crtc_list, list)
+- module_put(crtc->owner);
+-
+- list_for_each_entry(con, &imxdrm->connector_list, list)
+- module_put(con->owner);
+-
+- list_for_each_entry(enc, &imxdrm->encoder_list, list)
+- module_put(enc->owner);
+-
+- imxdrm->references--;
+-
+- mutex_unlock(&imxdrm->mutex);
++ drm_sysfs_connector_remove(connector);
++ drm_connector_cleanup(connector);
+ }
+-EXPORT_SYMBOL_GPL(imx_drm_device_put);
++EXPORT_SYMBOL_GPL(imx_drm_connector_destroy);
+
+-static int drm_mode_group_reinit(struct drm_device *dev)
++void imx_drm_encoder_destroy(struct drm_encoder *encoder)
+ {
+- struct drm_mode_group *group = &dev->primary->mode_group;
+- uint32_t *id_list = group->id_list;
+- int ret;
+-
+- ret = drm_mode_group_init_legacy_group(dev, group);
+- if (ret < 0)
+- return ret;
+-
+- kfree(id_list);
+- return 0;
++ drm_encoder_cleanup(encoder);
+ }
++EXPORT_SYMBOL_GPL(imx_drm_encoder_destroy);
+
+-/*
+- * register an encoder to the drm core
+- */
+-static int imx_drm_encoder_register(struct imx_drm_encoder *imx_drm_encoder)
++static void imx_drm_output_poll_changed(struct drm_device *drm)
+ {
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+-
+- INIT_LIST_HEAD(&imx_drm_encoder->possible_crtcs);
+-
+- drm_encoder_init(imxdrm->drm, imx_drm_encoder->encoder,
+- imx_drm_encoder->encoder->funcs,
+- imx_drm_encoder->encoder->encoder_type);
+-
+- drm_mode_group_reinit(imxdrm->drm);
+-
+- return 0;
+-}
+-
+-/*
+- * unregister an encoder from the drm core
+- */
+-static void imx_drm_encoder_unregister(struct imx_drm_encoder
+- *imx_drm_encoder)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+-
+- drm_encoder_cleanup(imx_drm_encoder->encoder);
+-
+- drm_mode_group_reinit(imxdrm->drm);
+-}
+-
+-/*
+- * register a connector to the drm core
+- */
+-static int imx_drm_connector_register(
+- struct imx_drm_connector *imx_drm_connector)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+-
+- drm_connector_init(imxdrm->drm, imx_drm_connector->connector,
+- imx_drm_connector->connector->funcs,
+- imx_drm_connector->connector->connector_type);
+- drm_mode_group_reinit(imxdrm->drm);
+-
+- return drm_sysfs_connector_add(imx_drm_connector->connector);
+-}
+-
+-/*
+- * unregister a connector from the drm core
+- */
+-static void imx_drm_connector_unregister(
+- struct imx_drm_connector *imx_drm_connector)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+-
+- drm_sysfs_connector_remove(imx_drm_connector->connector);
+- drm_connector_cleanup(imx_drm_connector->connector);
++#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
++ struct imx_drm_device *imxdrm = drm->dev_private;
+
+- drm_mode_group_reinit(imxdrm->drm);
++ if (imxdrm->fbhelper)
++ drm_fbdev_cma_hotplug_event(imxdrm->fbhelper);
++#endif
+ }
+
+-/*
+- * register a crtc to the drm core
+- */
+-static int imx_drm_crtc_register(struct imx_drm_crtc *imx_drm_crtc)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- int ret;
+-
+- drm_crtc_init(imxdrm->drm, imx_drm_crtc->crtc,
+- imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs);
+- ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256);
+- if (ret)
+- return ret;
+-
+- drm_crtc_helper_add(imx_drm_crtc->crtc,
+- imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
+-
+- drm_mode_group_reinit(imxdrm->drm);
+-
+- return 0;
+-}
++static struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
++ .fb_create = drm_fb_cma_create,
++ .output_poll_changed = imx_drm_output_poll_changed,
++};
+
+ /*
+- * Called by the CRTC driver when all CRTCs are registered. This
+- * puts all the pieces together and initializes the driver.
+- * Once this is called no more CRTCs can be registered since
+- * the drm core has hardcoded the number of crtcs in several
+- * places.
++ * Main DRM initialisation. This binds, initialises and registers
++ * with DRM the subcomponents of the driver.
+ */
+ static int imx_drm_driver_load(struct drm_device *drm, unsigned long flags)
+ {
+- struct imx_drm_device *imxdrm = __imx_drm_device();
++ struct imx_drm_device *imxdrm;
++ struct drm_connector *connector;
+ int ret;
+
++ imxdrm = devm_kzalloc(drm->dev, sizeof(*imxdrm), GFP_KERNEL);
++ if (!imxdrm)
++ return -ENOMEM;
++
+ imxdrm->drm = drm;
+
+ drm->dev_private = imxdrm;
+
+ /*
+ * enable drm irq mode.
+- * - with irq_enabled = 1, we can use the vblank feature.
++ * - with irq_enabled = true, we can use the vblank feature.
+ *
+ * P.S. note that we wouldn't use drm irq handler but
+ * just specific driver own one instead because
+ * drm framework supports only one irq handler and
+ * drivers can well take care of their interrupts
+ */
+- drm->irq_enabled = 1;
++ drm->irq_enabled = true;
++
++ /*
++ * set max width and height as default value(4096x4096).
++ * this value would be used to check framebuffer size limitation
++ * at drm_mode_addfb().
++ */
++ drm->mode_config.min_width = 64;
++ drm->mode_config.min_height = 64;
++ drm->mode_config.max_width = 4096;
++ drm->mode_config.max_height = 4096;
++ drm->mode_config.funcs = &imx_drm_mode_config_funcs;
+
+ drm_mode_config_init(drm);
+- imx_drm_mode_config_init(drm);
+
+- mutex_lock(&imxdrm->mutex);
++ ret = drm_vblank_init(drm, MAX_CRTC);
++ if (ret)
++ goto err_kms;
+
+- drm_kms_helper_poll_init(imxdrm->drm);
++ /*
++ * with vblank_disable_allowed = true, vblank interrupt will be
++ * disabled by drm timer once a current process gives up ownership
++ * of vblank event. (after drm_vblank_put function is called)
++ */
++ drm->vblank_disable_allowed = true;
+
+- /* setup the grouping for the legacy output */
+- ret = drm_mode_group_init_legacy_group(imxdrm->drm,
+- &imxdrm->drm->primary->mode_group);
++ /* Now try and bind all our sub-components */
++ ret = component_bind_all(drm->dev, drm);
+ if (ret)
+- goto err_init;
++ goto err_vblank;
+
+- ret = drm_vblank_init(imxdrm->drm, MAX_CRTC);
+- if (ret)
+- goto err_init;
++ /*
++ * All components are now added, we can publish the connector sysfs
++ * entries to userspace. This will generate hotplug events and so
++ * userspace will expect to be able to access DRM at this point.
++ */
++ list_for_each_entry(connector, &drm->mode_config.connector_list, head) {
++ ret = drm_sysfs_connector_add(connector);
++ if (ret) {
++ dev_err(drm->dev,
++ "[CONNECTOR:%d:%s] drm_sysfs_connector_add failed: %d\n",
++ connector->base.id,
++ drm_get_connector_name(connector), ret);
++ goto err_unbind;
++ }
++ }
+
+ /*
+- * with vblank_disable_allowed = 1, vblank interrupt will be disabled
+- * by drm timer once a current process gives up ownership of
+- * vblank event.(after drm_vblank_put function is called)
++ * All components are now initialised, so setup the fb helper.
++ * The fb helper takes copies of key hardware information, so the
++ * crtcs/connectors/encoders must not change after this point.
+ */
+- imxdrm->drm->vblank_disable_allowed = 1;
++#if IS_ENABLED(CONFIG_DRM_IMX_FB_HELPER)
++ if (legacyfb_depth != 16 && legacyfb_depth != 32) {
++ dev_warn(drm->dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n");
++ legacyfb_depth = 16;
++ }
++ imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth,
++ drm->mode_config.num_crtc, MAX_CRTC);
++ if (IS_ERR(imxdrm->fbhelper)) {
++ ret = PTR_ERR(imxdrm->fbhelper);
++ imxdrm->fbhelper = NULL;
++ goto err_unbind;
++ }
++#endif
++
++ drm_kms_helper_poll_init(drm);
+
+- ret = 0;
++ return 0;
+
+-err_init:
+- mutex_unlock(&imxdrm->mutex);
++err_unbind:
++ component_unbind_all(drm->dev, drm);
++err_vblank:
++ drm_vblank_cleanup(drm);
++err_kms:
++ drm_mode_config_cleanup(drm);
+
+ return ret;
+ }
+
+-static void imx_drm_update_possible_crtcs(void)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- struct imx_drm_crtc *imx_drm_crtc;
+- struct imx_drm_encoder *enc;
+- struct crtc_cookie *cookie;
+-
+- list_for_each_entry(enc, &imxdrm->encoder_list, list) {
+- u32 possible_crtcs = 0;
+-
+- list_for_each_entry(cookie, &enc->possible_crtcs, list) {
+- list_for_each_entry(imx_drm_crtc, &imxdrm->crtc_list, list) {
+- if (imx_drm_crtc->cookie.cookie == cookie->cookie &&
+- imx_drm_crtc->cookie.id == cookie->id) {
+- possible_crtcs |= 1 << imx_drm_crtc->pipe;
+- }
+- }
+- }
+- enc->encoder->possible_crtcs = possible_crtcs;
+- enc->encoder->possible_clones = possible_crtcs;
+- }
+-}
+-
+ /*
+ * imx_drm_add_crtc - add a new crtc
+ *
+ * The return value if !NULL is a cookie for the caller to pass to
+ * imx_drm_remove_crtc later.
+ */
+-int imx_drm_add_crtc(struct drm_crtc *crtc,
++int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
+ struct imx_drm_crtc **new_crtc,
+ const struct imx_drm_crtc_helper_funcs *imx_drm_helper_funcs,
+- struct module *owner, void *cookie, int id)
++ void *cookie, int ipu_id, int di_id)
+ {
+- struct imx_drm_device *imxdrm = __imx_drm_device();
++ struct imx_drm_device *imxdrm = drm->dev_private;
+ struct imx_drm_crtc *imx_drm_crtc;
+- const struct drm_crtc_funcs *crtc_funcs;
+ int ret;
+
+- mutex_lock(&imxdrm->mutex);
++ /*
++ * The vblank arrays are dimensioned by MAX_CRTC - we can't
++ * pass IDs greater than this to those functions.
++ */
++ if (imxdrm->pipes >= MAX_CRTC)
++ return -EINVAL;
+
+- if (imxdrm->references) {
+- ret = -EBUSY;
+- goto err_busy;
+- }
++ if (imxdrm->drm->open_count)
++ return -EBUSY;
+
+ imx_drm_crtc = kzalloc(sizeof(*imx_drm_crtc), GFP_KERNEL);
+- if (!imx_drm_crtc) {
+- ret = -ENOMEM;
+- goto err_alloc;
+- }
++ if (!imx_drm_crtc)
++ return -ENOMEM;
+
+ imx_drm_crtc->imx_drm_helper_funcs = *imx_drm_helper_funcs;
+ imx_drm_crtc->pipe = imxdrm->pipes++;
+- imx_drm_crtc->cookie.cookie = cookie;
+- imx_drm_crtc->cookie.id = id;
+-
+- crtc_funcs = imx_drm_helper_funcs->crtc_funcs;
+-
++ imx_drm_crtc->cookie = cookie;
++ imx_drm_crtc->di_id = di_id;
++ imx_drm_crtc->ipu_id = ipu_id;
+ imx_drm_crtc->crtc = crtc;
+- imx_drm_crtc->imxdrm = imxdrm;
+-
+- imx_drm_crtc->owner = owner;
+
+- list_add_tail(&imx_drm_crtc->list, &imxdrm->crtc_list);
++ imxdrm->crtc[imx_drm_crtc->pipe] = imx_drm_crtc;
+
+ *new_crtc = imx_drm_crtc;
+
+- ret = imx_drm_crtc_register(imx_drm_crtc);
++ ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256);
+ if (ret)
+ goto err_register;
+
+- imx_drm_update_possible_crtcs();
++ drm_crtc_helper_add(crtc,
++ imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
+
+- mutex_unlock(&imxdrm->mutex);
++ drm_crtc_init(drm, crtc,
++ imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs);
+
+ return 0;
+
+ err_register:
++ imxdrm->crtc[imx_drm_crtc->pipe] = NULL;
+ kfree(imx_drm_crtc);
+-err_alloc:
+-err_busy:
+- mutex_unlock(&imxdrm->mutex);
+ return ret;
+ }
+ EXPORT_SYMBOL_GPL(imx_drm_add_crtc);
+@@ -547,17 +402,11 @@
+ */
+ int imx_drm_remove_crtc(struct imx_drm_crtc *imx_drm_crtc)
+ {
+- struct imx_drm_device *imxdrm = imx_drm_crtc->imxdrm;
+-
+- mutex_lock(&imxdrm->mutex);
++ struct imx_drm_device *imxdrm = imx_drm_crtc->crtc->dev->dev_private;
+
+ drm_crtc_cleanup(imx_drm_crtc->crtc);
+
+- list_del(&imx_drm_crtc->list);
+-
+- drm_mode_group_reinit(imxdrm->drm);
+-
+- mutex_unlock(&imxdrm->mutex);
++ imxdrm->crtc[imx_drm_crtc->pipe] = NULL;
+
+ kfree(imx_drm_crtc);
+
+@@ -566,243 +415,104 @@
+ EXPORT_SYMBOL_GPL(imx_drm_remove_crtc);
+
+ /*
+- * imx_drm_add_encoder - add a new encoder
++ * Find the DRM CRTC possible mask for the device node cookie/id.
++ *
++ * The encoder possible masks are defined by their position in the
++ * mode_config crtc_list. This means that CRTCs must not be added
++ * or removed once the DRM device has been fully initialised.
+ */
+-int imx_drm_add_encoder(struct drm_encoder *encoder,
+- struct imx_drm_encoder **newenc, struct module *owner)
++static uint32_t imx_drm_find_crtc_mask(struct imx_drm_device *imxdrm,
++ void *cookie, int id)
+ {
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- struct imx_drm_encoder *imx_drm_encoder;
+- int ret;
+-
+- mutex_lock(&imxdrm->mutex);
++ unsigned i;
+
+- if (imxdrm->references) {
+- ret = -EBUSY;
+- goto err_busy;
++ for (i = 0; i < MAX_CRTC; i++) {
++ struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[i];
++ if (imx_drm_crtc && imx_drm_crtc->di_id == id &&
++ imx_drm_crtc->cookie == cookie)
++ return drm_helper_crtc_possible_mask(imx_drm_crtc->crtc);
+ }
+
+- imx_drm_encoder = kzalloc(sizeof(*imx_drm_encoder), GFP_KERNEL);
+- if (!imx_drm_encoder) {
+- ret = -ENOMEM;
+- goto err_alloc;
+- }
+-
+- imx_drm_encoder->encoder = encoder;
+- imx_drm_encoder->owner = owner;
+-
+- ret = imx_drm_encoder_register(imx_drm_encoder);
+- if (ret) {
+- ret = -ENOMEM;
+- goto err_register;
+- }
+-
+- list_add_tail(&imx_drm_encoder->list, &imxdrm->encoder_list);
+-
+- *newenc = imx_drm_encoder;
+-
+- mutex_unlock(&imxdrm->mutex);
+-
+ return 0;
+-
+-err_register:
+- kfree(imx_drm_encoder);
+-err_alloc:
+-err_busy:
+- mutex_unlock(&imxdrm->mutex);
+-
+- return ret;
+ }
+-EXPORT_SYMBOL_GPL(imx_drm_add_encoder);
+-
+-int imx_drm_encoder_add_possible_crtcs(
+- struct imx_drm_encoder *imx_drm_encoder,
+- struct device_node *np)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- struct of_phandle_args args;
+- struct crtc_cookie *c;
+- int ret = 0;
+- int i;
+
+- if (!list_empty(&imx_drm_encoder->possible_crtcs))
+- return -EBUSY;
++int imx_drm_encoder_parse_of(struct drm_device *drm,
++ struct drm_encoder *encoder, struct device_node *np)
++{
++ struct imx_drm_device *imxdrm = drm->dev_private;
++ uint32_t crtc_mask = 0;
++ int i, ret = 0;
+
+ for (i = 0; !ret; i++) {
+- ret = of_parse_phandle_with_args(np, "crtcs",
+- "#crtc-cells", i, &args);
+- if (ret < 0)
++ struct of_phandle_args args;
++ uint32_t mask;
++ int id;
++
++ ret = of_parse_phandle_with_args(np, "crtcs", "#crtc-cells", i,
++ &args);
++ if (ret == -ENOENT)
+ break;
++ if (ret < 0)
++ return ret;
+
+- c = kzalloc(sizeof(*c), GFP_KERNEL);
+- if (!c) {
+- of_node_put(args.np);
+- return -ENOMEM;
+- }
+-
+- c->cookie = args.np;
+- c->id = args.args_count > 0 ? args.args[0] : 0;
+-
++ id = args.args_count > 0 ? args.args[0] : 0;
++ mask = imx_drm_find_crtc_mask(imxdrm, args.np, id);
+ of_node_put(args.np);
+
+- mutex_lock(&imxdrm->mutex);
+-
+- list_add_tail(&c->list, &imx_drm_encoder->possible_crtcs);
+-
+- mutex_unlock(&imxdrm->mutex);
+- }
+-
+- imx_drm_update_possible_crtcs();
+-
+- return 0;
+-}
+-EXPORT_SYMBOL_GPL(imx_drm_encoder_add_possible_crtcs);
++ /*
++ * If we failed to find the CRTC(s) which this encoder is
++ * supposed to be connected to, it's because the CRTC has
++ * not been registered yet. Defer probing, and hope that
++ * the required CRTC is added later.
++ */
++ if (mask == 0)
++ return -EPROBE_DEFER;
+
+-int imx_drm_encoder_get_mux_id(struct imx_drm_encoder *imx_drm_encoder,
+- struct drm_crtc *crtc)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- struct imx_drm_crtc *imx_crtc;
+- int i = 0;
+-
+- mutex_lock(&imxdrm->mutex);
+-
+- list_for_each_entry(imx_crtc, &imxdrm->crtc_list, list) {
+- if (imx_crtc->crtc == crtc)
+- goto found;
+- i++;
++ crtc_mask |= mask;
+ }
+
+- mutex_unlock(&imxdrm->mutex);
+-
+- return -EINVAL;
+-found:
+- mutex_unlock(&imxdrm->mutex);
+-
+- return i;
+-}
+-EXPORT_SYMBOL_GPL(imx_drm_encoder_get_mux_id);
+-
+-/*
+- * imx_drm_remove_encoder - remove an encoder
+- */
+-int imx_drm_remove_encoder(struct imx_drm_encoder *imx_drm_encoder)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- struct crtc_cookie *c, *tmp;
+-
+- mutex_lock(&imxdrm->mutex);
+-
+- imx_drm_encoder_unregister(imx_drm_encoder);
++ encoder->possible_crtcs = crtc_mask;
+
+- list_del(&imx_drm_encoder->list);
+-
+- list_for_each_entry_safe(c, tmp, &imx_drm_encoder->possible_crtcs,
+- list)
+- kfree(c);
+-
+- mutex_unlock(&imxdrm->mutex);
+-
+- kfree(imx_drm_encoder);
++ /* FIXME: this is the mask of outputs which can clone this output. */
++ encoder->possible_clones = ~0;
+
+ return 0;
+ }
+-EXPORT_SYMBOL_GPL(imx_drm_remove_encoder);
++EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of);
+
+-/*
+- * imx_drm_add_connector - add a connector
+- */
+-int imx_drm_add_connector(struct drm_connector *connector,
+- struct imx_drm_connector **new_con,
+- struct module *owner)
++int imx_drm_encoder_get_mux_id(struct drm_encoder *encoder)
+ {
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+- struct imx_drm_connector *imx_drm_connector;
+- int ret;
+-
+- mutex_lock(&imxdrm->mutex);
+-
+- if (imxdrm->references) {
+- ret = -EBUSY;
+- goto err_busy;
+- }
+-
+- imx_drm_connector = kzalloc(sizeof(*imx_drm_connector), GFP_KERNEL);
+- if (!imx_drm_connector) {
+- ret = -ENOMEM;
+- goto err_alloc;
+- }
+-
+- imx_drm_connector->connector = connector;
+- imx_drm_connector->owner = owner;
+-
+- ret = imx_drm_connector_register(imx_drm_connector);
+- if (ret)
+- goto err_register;
+-
+- list_add_tail(&imx_drm_connector->list, &imxdrm->connector_list);
+-
+- *new_con = imx_drm_connector;
+-
+- mutex_unlock(&imxdrm->mutex);
++ struct imx_drm_crtc *imx_crtc = imx_drm_find_crtc(encoder->crtc);
+
+- return 0;
+-
+-err_register:
+- kfree(imx_drm_connector);
+-err_alloc:
+-err_busy:
+- mutex_unlock(&imxdrm->mutex);
+-
+- return ret;
++ return imx_crtc ? imx_crtc->ipu_id * 2 + imx_crtc->di_id : -EINVAL;
+ }
+-EXPORT_SYMBOL_GPL(imx_drm_add_connector);
+-
+-void imx_drm_fb_helper_set(struct drm_fbdev_cma *fbdev_helper)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+-
+- imxdrm->fbhelper = fbdev_helper;
+-}
+-EXPORT_SYMBOL_GPL(imx_drm_fb_helper_set);
+-
+-/*
+- * imx_drm_remove_connector - remove a connector
+- */
+-int imx_drm_remove_connector(struct imx_drm_connector *imx_drm_connector)
+-{
+- struct imx_drm_device *imxdrm = __imx_drm_device();
+-
+- mutex_lock(&imxdrm->mutex);
+-
+- imx_drm_connector_unregister(imx_drm_connector);
+-
+- list_del(&imx_drm_connector->list);
+-
+- mutex_unlock(&imxdrm->mutex);
+-
+- kfree(imx_drm_connector);
+-
+- return 0;
+-}
+-EXPORT_SYMBOL_GPL(imx_drm_remove_connector);
++EXPORT_SYMBOL_GPL(imx_drm_encoder_get_mux_id);
+
+-static struct drm_ioctl_desc imx_drm_ioctls[] = {
++static const struct drm_ioctl_desc imx_drm_ioctls[] = {
+ /* none so far */
+ };
+
+ static struct drm_driver imx_drm_driver = {
+- .driver_features = DRIVER_MODESET | DRIVER_GEM,
++ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME,
+ .load = imx_drm_driver_load,
+ .unload = imx_drm_driver_unload,
+- .firstopen = imx_drm_driver_firstopen,
+ .lastclose = imx_drm_driver_lastclose,
++ .preclose = imx_drm_driver_preclose,
+ .gem_free_object = drm_gem_cma_free_object,
+ .gem_vm_ops = &drm_gem_cma_vm_ops,
+ .dumb_create = drm_gem_cma_dumb_create,
+ .dumb_map_offset = drm_gem_cma_dumb_map_offset,
+- .dumb_destroy = drm_gem_cma_dumb_destroy,
++ .dumb_destroy = drm_gem_dumb_destroy,
+
++ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
++ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
++ .gem_prime_import = drm_gem_prime_import,
++ .gem_prime_export = drm_gem_prime_export,
++ .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
++ .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
++ .gem_prime_vmap = drm_gem_cma_prime_vmap,
++ .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
++ .gem_prime_mmap = drm_gem_cma_prime_mmap,
+ .get_vblank_counter = drm_vblank_count,
+ .enable_vblank = imx_drm_enable_vblank,
+ .disable_vblank = imx_drm_disable_vblank,
+@@ -817,76 +527,103 @@
+ .patchlevel = 0,
+ };
+
+-static int imx_drm_platform_probe(struct platform_device *pdev)
++static int compare_parent_of(struct device *dev, void *data)
+ {
+- imx_drm_device->dev = &pdev->dev;
+-
+- return drm_platform_init(&imx_drm_driver, pdev);
++ struct of_phandle_args *args = data;
++ return dev->parent && dev->parent->of_node == args->np;
+ }
+
+-static int imx_drm_platform_remove(struct platform_device *pdev)
++static int compare_of(struct device *dev, void *data)
+ {
+- drm_platform_exit(&imx_drm_driver, pdev);
+-
+- return 0;
++ return dev->of_node == data;
+ }
+
+-static struct platform_driver imx_drm_pdrv = {
+- .probe = imx_drm_platform_probe,
+- .remove = imx_drm_platform_remove,
+- .driver = {
+- .owner = THIS_MODULE,
+- .name = "imx-drm",
+- },
+-};
+-
+-static struct platform_device *imx_drm_pdev;
+-
+-static int __init imx_drm_init(void)
++static int imx_drm_add_components(struct device *master, struct master *m)
+ {
++ struct device_node *np = master->of_node;
++ unsigned i;
+ int ret;
+
+- imx_drm_device = kzalloc(sizeof(*imx_drm_device), GFP_KERNEL);
+- if (!imx_drm_device)
+- return -ENOMEM;
++ for (i = 0; ; i++) {
++ struct of_phandle_args args;
++
++ ret = of_parse_phandle_with_fixed_args(np, "crtcs", 1,
++ i, &args);
++ if (ret)
++ break;
++
++ ret = component_master_add_child(m, compare_parent_of, &args);
++ of_node_put(args.np);
+
+- mutex_init(&imx_drm_device->mutex);
+- INIT_LIST_HEAD(&imx_drm_device->crtc_list);
+- INIT_LIST_HEAD(&imx_drm_device->connector_list);
+- INIT_LIST_HEAD(&imx_drm_device->encoder_list);
+-
+- imx_drm_pdev = platform_device_register_simple("imx-drm", -1, NULL, 0);
+- if (!imx_drm_pdev) {
+- ret = -EINVAL;
+- goto err_pdev;
++ if (ret)
++ return ret;
+ }
+
+- imx_drm_pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32),
++ for (i = 0; ; i++) {
++ struct device_node *node;
+
+- ret = platform_driver_register(&imx_drm_pdrv);
+- if (ret)
+- goto err_pdrv;
++ node = of_parse_phandle(np, "connectors", i);
++ if (!node)
++ break;
+
++ ret = component_master_add_child(m, compare_of, node);
++ of_node_put(node);
++
++ if (ret)
++ return ret;
++ }
+ return 0;
++}
+
+-err_pdrv:
+- platform_device_unregister(imx_drm_pdev);
+-err_pdev:
+- kfree(imx_drm_device);
++static int imx_drm_bind(struct device *dev)
++{
++ return drm_platform_init(&imx_drm_driver, to_platform_device(dev));
++}
+
+- return ret;
++static void imx_drm_unbind(struct device *dev)
++{
++ drm_platform_exit(&imx_drm_driver, to_platform_device(dev));
+ }
+
+-static void __exit imx_drm_exit(void)
++static const struct component_master_ops imx_drm_ops = {
++ .add_components = imx_drm_add_components,
++ .bind = imx_drm_bind,
++ .unbind = imx_drm_unbind,
++};
++
++static int imx_drm_platform_probe(struct platform_device *pdev)
+ {
+- platform_device_unregister(imx_drm_pdev);
+- platform_driver_unregister(&imx_drm_pdrv);
++ int ret;
+
+- kfree(imx_drm_device);
++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++ if (ret)
++ return ret;
++
++ return component_master_add(&pdev->dev, &imx_drm_ops);
+ }
+
+-module_init(imx_drm_init);
+-module_exit(imx_drm_exit);
++static int imx_drm_platform_remove(struct platform_device *pdev)
++{
++ component_master_del(&pdev->dev, &imx_drm_ops);
++ return 0;
++}
++
++static const struct of_device_id imx_drm_dt_ids[] = {
++ { .compatible = "fsl,imx-drm", },
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, imx_drm_dt_ids);
++
++static struct platform_driver imx_drm_pdrv = {
++ .probe = imx_drm_platform_probe,
++ .remove = imx_drm_platform_remove,
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "imx-drm",
++ .of_match_table = imx_drm_dt_ids,
++ },
++};
++module_platform_driver(imx_drm_pdrv);
+
+ MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+ MODULE_DESCRIPTION("i.MX drm driver core");
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/imx-drm.h linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-drm.h
+--- linux-3.10.30.orig/drivers/staging/imx-drm/imx-drm.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-drm.h 2014-05-15 20:34:05.754069749 +0200
+@@ -5,15 +5,19 @@
+
+ #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
+
++struct device_node;
+ struct drm_crtc;
+ struct drm_connector;
+ struct drm_device;
++struct drm_display_mode;
+ struct drm_encoder;
+-struct imx_drm_crtc;
+ struct drm_fbdev_cma;
+ struct drm_framebuffer;
++struct imx_drm_crtc;
+ struct platform_device;
+
++int imx_drm_crtc_id(struct imx_drm_crtc *crtc);
++
+ struct imx_drm_crtc_helper_funcs {
+ int (*enable_vblank)(struct drm_crtc *crtc);
+ void (*disable_vblank)(struct drm_crtc *crtc);
+@@ -23,10 +27,10 @@
+ const struct drm_crtc_funcs *crtc_funcs;
+ };
+
+-int imx_drm_add_crtc(struct drm_crtc *crtc,
++int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
+ struct imx_drm_crtc **new_crtc,
+ const struct imx_drm_crtc_helper_funcs *imx_helper_funcs,
+- struct module *owner, void *cookie, int id);
++ void *cookie, int ipu_id, int di_id);
+ int imx_drm_remove_crtc(struct imx_drm_crtc *);
+ int imx_drm_init_drm(struct platform_device *pdev,
+ int preferred_bpp);
+@@ -36,35 +40,22 @@
+ void imx_drm_crtc_vblank_put(struct imx_drm_crtc *imx_drm_crtc);
+ void imx_drm_handle_vblank(struct imx_drm_crtc *imx_drm_crtc);
+
+-struct imx_drm_encoder;
+-int imx_drm_add_encoder(struct drm_encoder *encoder,
+- struct imx_drm_encoder **new_enc,
+- struct module *owner);
+-int imx_drm_remove_encoder(struct imx_drm_encoder *);
+-
+-struct imx_drm_connector;
+-int imx_drm_add_connector(struct drm_connector *connector,
+- struct imx_drm_connector **new_con,
+- struct module *owner);
+-int imx_drm_remove_connector(struct imx_drm_connector *);
+-
+ void imx_drm_mode_config_init(struct drm_device *drm);
+
+ struct drm_gem_cma_object *imx_drm_fb_get_obj(struct drm_framebuffer *fb);
+
+-struct drm_device *imx_drm_device_get(void);
+-void imx_drm_device_put(void);
+-int imx_drm_crtc_panel_format_pins(struct drm_crtc *crtc, u32 encoder_type,
++int imx_drm_panel_format_pins(struct drm_encoder *encoder,
+ u32 interface_pix_fmt, int hsync_pin, int vsync_pin);
+-int imx_drm_crtc_panel_format(struct drm_crtc *crtc, u32 encoder_type,
++int imx_drm_panel_format(struct drm_encoder *encoder,
+ u32 interface_pix_fmt);
+-void imx_drm_fb_helper_set(struct drm_fbdev_cma *fbdev_helper);
+-
+-struct device_node;
+
+-int imx_drm_encoder_get_mux_id(struct imx_drm_encoder *imx_drm_encoder,
+- struct drm_crtc *crtc);
+-int imx_drm_encoder_add_possible_crtcs(struct imx_drm_encoder *imx_drm_encoder,
+- struct device_node *np);
++int imx_drm_encoder_get_mux_id(struct drm_encoder *encoder);
++int imx_drm_encoder_parse_of(struct drm_device *drm,
++ struct drm_encoder *encoder, struct device_node *np);
++
++int imx_drm_connector_mode_valid(struct drm_connector *connector,
++ struct drm_display_mode *mode);
++void imx_drm_connector_destroy(struct drm_connector *connector);
++void imx_drm_encoder_destroy(struct drm_encoder *encoder);
+
+ #endif /* _IMX_DRM_H_ */
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/imx-fb.c linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-fb.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/imx-fb.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-fb.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,47 +0,0 @@
+-/*
+- * i.MX drm driver
+- *
+- * Copyright (C) 2012 Sascha Hauer, Pengutronix
+- *
+- * Based on Samsung Exynos code
+- *
+- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * as published by the Free Software Foundation; either version 2
+- * of the License, or (at your option) any later version.
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- */
+-#include <linux/module.h>
+-#include <drm/drmP.h>
+-#include <drm/drm_crtc.h>
+-#include <drm/drm_crtc_helper.h>
+-#include <drm/drm_gem_cma_helper.h>
+-#include <drm/drm_fb_cma_helper.h>
+-
+-#include "imx-drm.h"
+-
+-static struct drm_mode_config_funcs imx_drm_mode_config_funcs = {
+- .fb_create = drm_fb_cma_create,
+-};
+-
+-void imx_drm_mode_config_init(struct drm_device *dev)
+-{
+- dev->mode_config.min_width = 64;
+- dev->mode_config.min_height = 64;
+-
+- /*
+- * set max width and height as default value(4096x4096).
+- * this value would be used to check framebuffer size limitation
+- * at drm_mode_addfb().
+- */
+- dev->mode_config.max_width = 4096;
+- dev->mode_config.max_height = 4096;
+-
+- dev->mode_config.funcs = &imx_drm_mode_config_funcs;
+-}
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/imx-fbdev.c linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-fbdev.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/imx-fbdev.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-fbdev.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,74 +0,0 @@
+-/*
+- * i.MX drm driver
+- *
+- * Copyright (C) 2012 Sascha Hauer, Pengutronix
+- *
+- * Based on Samsung Exynos code
+- *
+- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License
+- * as published by the Free Software Foundation; either version 2
+- * of the License, or (at your option) any later version.
+- * This program is distributed in the hope that it will be useful,
+- * but WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- * GNU General Public License for more details.
+- *
+- */
+-#include <linux/module.h>
+-#include <drm/drmP.h>
+-#include <drm/drm_crtc.h>
+-#include <drm/drm_crtc_helper.h>
+-#include <drm/drm_fb_cma_helper.h>
+-
+-#include "imx-drm.h"
+-
+-#define MAX_CONNECTOR 4
+-#define PREFERRED_BPP 16
+-
+-static struct drm_fbdev_cma *fbdev_cma;
+-
+-static int legacyfb_depth = 16;
+-
+-module_param(legacyfb_depth, int, 0444);
+-
+-static int __init imx_fb_helper_init(void)
+-{
+- struct drm_device *drm = imx_drm_device_get();
+-
+- if (!drm)
+- return -EINVAL;
+-
+- if (legacyfb_depth != 16 && legacyfb_depth != 32) {
+- pr_warn("i.MX legacyfb: invalid legacyfb_depth setting. defaulting to 16bpp\n");
+- legacyfb_depth = 16;
+- }
+-
+- fbdev_cma = drm_fbdev_cma_init(drm, legacyfb_depth,
+- drm->mode_config.num_crtc, MAX_CONNECTOR);
+-
+- if (IS_ERR(fbdev_cma)) {
+- imx_drm_device_put();
+- return PTR_ERR(fbdev_cma);
+- }
+-
+- imx_drm_fb_helper_set(fbdev_cma);
+-
+- return 0;
+-}
+-
+-static void __exit imx_fb_helper_exit(void)
+-{
+- imx_drm_fb_helper_set(NULL);
+- drm_fbdev_cma_fini(fbdev_cma);
+- imx_drm_device_put();
+-}
+-
+-late_initcall(imx_fb_helper_init);
+-module_exit(imx_fb_helper_exit);
+-
+-MODULE_DESCRIPTION("Freescale i.MX legacy fb driver");
+-MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/imx-hdmi.c linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-hdmi.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/imx-hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-hdmi.c 2014-05-15 20:34:05.754069749 +0200
+@@ -0,0 +1,1842 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
++ * for SLISHDMI13T and SLIPHDMIT IP cores
++ *
++ * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
++ */
++
++#include <linux/component.h>
++#include <linux/irq.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/of_device.h>
++
++#include <drm/drmP.h>
++#include <drm/drm_crtc_helper.h>
++#include <drm/drm_edid.h>
++#include <drm/drm_encoder_slave.h>
++
++#include "dw-hdmi-audio.h"
++#include "dw-hdmi-cec.h"
++#include "ipu-v3/imx-ipu-v3.h"
++#include "imx-hdmi.h"
++#include "imx-drm.h"
++
++#define HDMI_EDID_LEN 512
++
++#define RGB 0
++#define YCBCR444 1
++#define YCBCR422_16BITS 2
++#define YCBCR422_8BITS 3
++#define XVYCC444 4
++
++enum hdmi_datamap {
++ RGB444_8B = 0x01,
++ RGB444_10B = 0x03,
++ RGB444_12B = 0x05,
++ RGB444_16B = 0x07,
++ YCbCr444_8B = 0x09,
++ YCbCr444_10B = 0x0B,
++ YCbCr444_12B = 0x0D,
++ YCbCr444_16B = 0x0F,
++ YCbCr422_8B = 0x16,
++ YCbCr422_10B = 0x14,
++ YCbCr422_12B = 0x12,
++};
++
++enum hdmi_colorimetry {
++ ITU601,
++ ITU709,
++};
++
++enum imx_hdmi_devtype {
++ IMX6Q_HDMI,
++ IMX6DL_HDMI,
++};
++
++static const u16 csc_coeff_default[3][4] = {
++ { 0x2000, 0x0000, 0x0000, 0x0000 },
++ { 0x0000, 0x2000, 0x0000, 0x0000 },
++ { 0x0000, 0x0000, 0x2000, 0x0000 }
++};
++
++static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
++ { 0x2000, 0x6926, 0x74fd, 0x010e },
++ { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
++ { 0x2000, 0x0000, 0x38b4, 0x7e3b }
++};
++
++static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
++ { 0x2000, 0x7106, 0x7a02, 0x00a7 },
++ { 0x2000, 0x3264, 0x0000, 0x7e6d },
++ { 0x2000, 0x0000, 0x3b61, 0x7e25 }
++};
++
++static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
++ { 0x2591, 0x1322, 0x074b, 0x0000 },
++ { 0x6535, 0x2000, 0x7acc, 0x0200 },
++ { 0x6acd, 0x7534, 0x2000, 0x0200 }
++};
++
++static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
++ { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
++ { 0x62f0, 0x2000, 0x7d11, 0x0200 },
++ { 0x6756, 0x78ab, 0x2000, 0x0200 }
++};
++
++struct hdmi_vmode {
++ bool mdvi;
++ bool mhsyncpolarity;
++ bool mvsyncpolarity;
++ bool minterlaced;
++ bool mdataenablepolarity;
++
++ unsigned int mpixelclock;
++ unsigned int mpixelrepetitioninput;
++ unsigned int mpixelrepetitionoutput;
++};
++
++struct hdmi_data_info {
++ unsigned int enc_in_format;
++ unsigned int enc_out_format;
++ unsigned int enc_color_depth;
++ unsigned int colorimetry;
++ unsigned int pix_repet_factor;
++ unsigned int hdcp_enable;
++ struct hdmi_vmode video_mode;
++};
++
++struct imx_hdmi {
++ struct drm_connector connector;
++ struct drm_encoder encoder;
++
++ struct platform_device *cec;
++ struct snd_dw_hdmi *audio;
++ enum imx_hdmi_devtype dev_type;
++ struct device *dev;
++ struct clk *isfr_clk;
++ struct clk *iahb_clk;
++
++ enum drm_connector_status connector_status;
++
++ struct hdmi_data_info hdmi_data;
++ int vic;
++
++ u8 edid[HDMI_EDID_LEN];
++ u8 mc_clkdis;
++ bool cable_plugin;
++
++ bool phy_enabled;
++ struct drm_display_mode previous_mode;
++
++ struct regmap *regmap;
++ struct i2c_adapter *ddc;
++ void __iomem *regs;
++
++ unsigned int sample_rate;
++ int ratio;
++};
++
++static void imx_hdmi_set_ipu_di_mux(struct imx_hdmi *hdmi, int ipu_di)
++{
++ regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
++ IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
++ ipu_di << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
++}
++
++static inline void hdmi_writeb(struct imx_hdmi *hdmi, u8 val, int offset)
++{
++ writeb(val, hdmi->regs + offset);
++}
++
++static inline u8 hdmi_readb(struct imx_hdmi *hdmi, int offset)
++{
++ return readb(hdmi->regs + offset);
++}
++
++static void hdmi_modb(struct imx_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
++{
++ u8 val = hdmi_readb(hdmi, reg) & ~mask;
++ val |= data & mask;
++ hdmi_writeb(hdmi, val, reg);
++}
++
++static void hdmi_mask_writeb(struct imx_hdmi *hdmi, u8 data, unsigned int reg,
++ u8 shift, u8 mask)
++{
++ hdmi_modb(hdmi, data << shift, mask, reg);
++}
++
++static void hdmi_set_clock_regenerator_n(struct imx_hdmi *hdmi,
++ unsigned int value)
++{
++ hdmi_writeb(hdmi, value & 0xff, HDMI_AUD_N1);
++ hdmi_writeb(hdmi, (value >> 8) & 0xff, HDMI_AUD_N2);
++ hdmi_writeb(hdmi, (value >> 16) & 0x0f, HDMI_AUD_N3);
++
++ /* nshift factor = 0 */
++ hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
++}
++
++static void hdmi_regenerate_cts(struct imx_hdmi *hdmi, unsigned int cts)
++{
++ /* Must be set/cleared first */
++ hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
++
++ hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
++ hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
++ hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
++ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
++}
++
++static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
++ unsigned int ratio)
++{
++ unsigned int n = (128 * freq) / 1000;
++
++ switch (freq) {
++ case 32000:
++ if (pixel_clk == 25170000)
++ n = (ratio == 150) ? 9152 : 4576;
++ else if (pixel_clk == 27020000)
++ n = (ratio == 150) ? 8192 : 4096;
++ else if (pixel_clk == 74170000 || pixel_clk == 148350000)
++ n = 11648;
++ else
++ n = 4096;
++ break;
++
++ case 44100:
++ if (pixel_clk == 25170000)
++ n = 7007;
++ else if (pixel_clk == 74170000)
++ n = 17836;
++ else if (pixel_clk == 148350000)
++ n = (ratio == 150) ? 17836 : 8918;
++ else
++ n = 6272;
++ break;
++
++ case 48000:
++ if (pixel_clk == 25170000)
++ n = (ratio == 150) ? 9152 : 6864;
++ else if (pixel_clk == 27020000)
++ n = (ratio == 150) ? 8192 : 6144;
++ else if (pixel_clk == 74170000)
++ n = 11648;
++ else if (pixel_clk == 148350000)
++ n = (ratio == 150) ? 11648 : 5824;
++ else
++ n = 6144;
++ break;
++
++ case 88200:
++ n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
++ break;
++
++ case 96000:
++ n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
++ break;
++
++ case 176400:
++ n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
++ break;
++
++ case 192000:
++ n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
++ break;
++
++ default:
++ break;
++ }
++
++ return n;
++}
++
++static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
++ unsigned int ratio)
++{
++ unsigned int cts = 0;
++
++ pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
++ pixel_clk, ratio);
++
++ switch (freq) {
++ case 32000:
++ if (pixel_clk == 297000000) {
++ cts = 222750;
++ break;
++ }
++ case 48000:
++ case 96000:
++ case 192000:
++ switch (pixel_clk) {
++ case 25200000:
++ case 27000000:
++ case 54000000:
++ case 74250000:
++ case 148500000:
++ cts = pixel_clk / 1000;
++ break;
++ case 297000000:
++ cts = 247500;
++ break;
++ /*
++ * All other TMDS clocks are not supported by
++ * DWC_hdmi_tx. The TMDS clocks divided or
++ * multiplied by 1,001 coefficients are not
++ * supported.
++ */
++ default:
++ break;
++ }
++ break;
++ case 44100:
++ case 88200:
++ case 176400:
++ switch (pixel_clk) {
++ case 25200000:
++ cts = 28000;
++ break;
++ case 27000000:
++ cts = 30000;
++ break;
++ case 54000000:
++ cts = 60000;
++ break;
++ case 74250000:
++ cts = 82500;
++ break;
++ case 148500000:
++ cts = 165000;
++ break;
++ case 297000000:
++ cts = 247500;
++ break;
++ default:
++ break;
++ }
++ break;
++ default:
++ break;
++ }
++ if (ratio == 100)
++ return cts;
++ else
++ return (cts * ratio) / 100;
++}
++
++static void hdmi_set_clk_regenerator(struct imx_hdmi *hdmi,
++ unsigned long pixel_clk)
++{
++ unsigned int clk_n, clk_cts;
++
++ clk_n = hdmi_compute_n(hdmi->sample_rate, pixel_clk,
++ hdmi->ratio);
++ clk_cts = hdmi_compute_cts(hdmi->sample_rate, pixel_clk,
++ hdmi->ratio);
++
++ if (!clk_cts) {
++ dev_dbg(hdmi->dev, "%s: pixel clock not supported: %lu\n",
++ __func__, pixel_clk);
++ return;
++ }
++
++ dev_dbg(hdmi->dev, "%s: samplerate=%d ratio=%d pixelclk=%lu N=%d cts=%d\n",
++ __func__, hdmi->sample_rate, hdmi->ratio,
++ pixel_clk, clk_n, clk_cts);
++
++ hdmi_set_clock_regenerator_n(hdmi, clk_n);
++ hdmi_regenerate_cts(hdmi, clk_cts);
++}
++
++static void hdmi_init_clk_regenerator(struct imx_hdmi *hdmi)
++{
++ hdmi_set_clk_regenerator(hdmi, 74250000);
++}
++
++static void hdmi_clk_regenerator_update_pixel_clock(struct imx_hdmi *hdmi)
++{
++ hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
++}
++
++void imx_hdmi_set_sample_rate(struct imx_hdmi *hdmi, unsigned int rate)
++{
++ hdmi->sample_rate = rate;
++ hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock);
++}
++EXPORT_SYMBOL(imx_hdmi_set_sample_rate);
++
++uint8_t *imx_hdmi_get_eld(struct imx_hdmi *hdmi)
++{
++ return hdmi->connector.eld;
++}
++EXPORT_SYMBOL(imx_hdmi_get_eld);
++
++/*
++ * this submodule is responsible for the video data synchronization.
++ * for example, for RGB 4:4:4 input, the data map is defined as
++ * pin{47~40} <==> R[7:0]
++ * pin{31~24} <==> G[7:0]
++ * pin{15~8} <==> B[7:0]
++ */
++static void hdmi_video_sample(struct imx_hdmi *hdmi)
++{
++ int color_format = 0;
++ u8 val;
++
++ if (hdmi->hdmi_data.enc_in_format == RGB) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x01;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x03;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x05;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_format = 0x07;
++ else
++ return;
++ } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x09;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x0B;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x0D;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_format = 0x0F;
++ else
++ return;
++ } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x16;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x14;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x12;
++ else
++ return;
++ }
++
++ val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
++ ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
++ hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
++
++ /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
++ val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
++ hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
++ hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
++ hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
++ hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
++ hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
++ hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
++ hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
++}
++
++static int is_color_space_conversion(struct imx_hdmi *hdmi)
++{
++ return (hdmi->hdmi_data.enc_in_format !=
++ hdmi->hdmi_data.enc_out_format);
++}
++
++static int is_color_space_decimation(struct imx_hdmi *hdmi)
++{
++ return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
++ (hdmi->hdmi_data.enc_in_format == RGB ||
++ hdmi->hdmi_data.enc_in_format == YCBCR444));
++}
++
++static int is_color_space_interpolation(struct imx_hdmi *hdmi)
++{
++ return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
++ (hdmi->hdmi_data.enc_out_format == RGB ||
++ hdmi->hdmi_data.enc_out_format == YCBCR444));
++}
++
++static void imx_hdmi_update_csc_coeffs(struct imx_hdmi *hdmi)
++{
++ const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
++ unsigned i;
++ u32 csc_scale = 1;
++
++ if (is_color_space_conversion(hdmi)) {
++ if (hdmi->hdmi_data.enc_out_format == RGB) {
++ if (hdmi->hdmi_data.colorimetry == ITU601)
++ csc_coeff = &csc_coeff_rgb_out_eitu601;
++ else
++ csc_coeff = &csc_coeff_rgb_out_eitu709;
++ } else if (hdmi->hdmi_data.enc_in_format == RGB) {
++ if (hdmi->hdmi_data.colorimetry == ITU601)
++ csc_coeff = &csc_coeff_rgb_in_eitu601;
++ else
++ csc_coeff = &csc_coeff_rgb_in_eitu709;
++ csc_scale = 0;
++ }
++ }
++
++ /* The CSC registers are sequential, alternating MSB then LSB */
++ for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
++ u16 coeff_a = (*csc_coeff)[0][i];
++ u16 coeff_b = (*csc_coeff)[1][i];
++ u16 coeff_c = (*csc_coeff)[2][i];
++
++ hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
++ hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
++ hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
++ hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
++ hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
++ hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
++ }
++
++ hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
++ HDMI_CSC_SCALE);
++}
++
++static void hdmi_video_csc(struct imx_hdmi *hdmi)
++{
++ int color_depth = 0;
++ int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
++ int decimation = 0;
++
++ /* YCC422 interpolation to 444 mode */
++ if (is_color_space_interpolation(hdmi))
++ interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
++ else if (is_color_space_decimation(hdmi))
++ decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
++
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
++ else
++ return;
++
++ /* Configure the CSC registers */
++ hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
++ hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
++ HDMI_CSC_SCALE);
++
++ imx_hdmi_update_csc_coeffs(hdmi);
++}
++
++/*
++ * HDMI video packetizer is used to packetize the data.
++ * for example, if input is YCC422 mode or repeater is used,
++ * data should be repacked this module can be bypassed.
++ */
++static void hdmi_video_packetize(struct imx_hdmi *hdmi)
++{
++ unsigned int color_depth = 0;
++ unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
++ unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
++ struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
++ u8 val, vp_conf;
++
++ if (hdmi_data->enc_out_format == RGB
++ || hdmi_data->enc_out_format == YCBCR444) {
++ if (!hdmi_data->enc_color_depth)
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
++ else if (hdmi_data->enc_color_depth == 8) {
++ color_depth = 4;
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
++ } else if (hdmi_data->enc_color_depth == 10)
++ color_depth = 5;
++ else if (hdmi_data->enc_color_depth == 12)
++ color_depth = 6;
++ else if (hdmi_data->enc_color_depth == 16)
++ color_depth = 7;
++ else
++ return;
++ } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
++ if (!hdmi_data->enc_color_depth ||
++ hdmi_data->enc_color_depth == 8)
++ remap_size = HDMI_VP_REMAP_YCC422_16bit;
++ else if (hdmi_data->enc_color_depth == 10)
++ remap_size = HDMI_VP_REMAP_YCC422_20bit;
++ else if (hdmi_data->enc_color_depth == 12)
++ remap_size = HDMI_VP_REMAP_YCC422_24bit;
++ else
++ return;
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
++ } else
++ return;
++
++ /* set the packetizer registers */
++ val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
++ ((hdmi_data->pix_repet_factor <<
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
++ hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
++
++ hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
++ HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
++
++ /* Data from pixel repeater block */
++ if (hdmi_data->pix_repet_factor > 1) {
++ vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
++ } else { /* data from packetizer block */
++ vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
++ }
++
++ hdmi_modb(hdmi, vp_conf,
++ HDMI_VP_CONF_PR_EN_MASK |
++ HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
++
++ hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
++ HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
++
++ hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
++
++ if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
++ vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
++ HDMI_VP_CONF_PP_EN_ENABLE |
++ HDMI_VP_CONF_YCC422_EN_DISABLE;
++ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
++ vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
++ HDMI_VP_CONF_PP_EN_DISABLE |
++ HDMI_VP_CONF_YCC422_EN_ENABLE;
++ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
++ vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
++ HDMI_VP_CONF_PP_EN_DISABLE |
++ HDMI_VP_CONF_YCC422_EN_DISABLE;
++ } else {
++ return;
++ }
++
++ hdmi_modb(hdmi, vp_conf,
++ HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
++
++ hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
++ HDMI_VP_STUFF_PP_STUFFING_MASK |
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
++
++ hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
++ HDMI_VP_CONF);
++}
++
++static inline void hdmi_phy_test_clear(struct imx_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
++ HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_enable(struct imx_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
++ HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_clock(struct imx_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
++ HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_din(struct imx_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
++}
++
++static inline void hdmi_phy_test_dout(struct imx_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
++}
++
++static bool hdmi_phy_wait_i2c_done(struct imx_hdmi *hdmi, int msec)
++{
++ unsigned char val = 0;
++ val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3;
++ while (!val) {
++ udelay(1000);
++ if (msec-- == 0)
++ return false;
++ val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3;
++ }
++ return true;
++}
++
++static void __hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
++ unsigned char addr)
++{
++ hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
++ hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
++ hdmi_writeb(hdmi, (unsigned char)(data >> 8),
++ HDMI_PHY_I2CM_DATAO_1_ADDR);
++ hdmi_writeb(hdmi, (unsigned char)(data >> 0),
++ HDMI_PHY_I2CM_DATAO_0_ADDR);
++ hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
++ HDMI_PHY_I2CM_OPERATION_ADDR);
++ hdmi_phy_wait_i2c_done(hdmi, 1000);
++}
++
++static int hdmi_phy_i2c_write(struct imx_hdmi *hdmi, unsigned short data,
++ unsigned char addr)
++{
++ __hdmi_phy_i2c_write(hdmi, data, addr);
++ return 0;
++}
++
++static void imx_hdmi_phy_enable_power(struct imx_hdmi *hdmi, u8 enable)
++{
++ hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_PDZ_OFFSET,
++ HDMI_PHY_CONF0_PDZ_MASK);
++}
++
++static void imx_hdmi_phy_enable_tmds(struct imx_hdmi *hdmi, u8 enable)
++{
++ hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET,
++ HDMI_PHY_CONF0_ENTMDS_MASK);
++}
++
++static void imx_hdmi_phy_gen2_pddq(struct imx_hdmi *hdmi, u8 enable)
++{
++ hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
++}
++
++static void imx_hdmi_phy_gen2_txpwron(struct imx_hdmi *hdmi, u8 enable)
++{
++ hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
++}
++
++static void imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi *hdmi, u8 enable)
++{
++ hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK);
++}
++
++static void imx_hdmi_phy_sel_interface_control(struct imx_hdmi *hdmi, u8 enable)
++{
++ hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET,
++ HDMI_PHY_CONF0_SELDIPIF_MASK);
++}
++
++enum {
++ RES_8,
++ RES_10,
++ RES_12,
++ RES_MAX,
++};
++
++struct mpll_config {
++ unsigned long mpixelclock;
++ struct {
++ u16 cpce;
++ u16 gmp;
++ } res[RES_MAX];
++};
++
++static const struct mpll_config mpll_config[] = {
++ {
++ 45250000, {
++ { 0x01e0, 0x0000 },
++ { 0x21e1, 0x0000 },
++ { 0x41e2, 0x0000 }
++ },
++ }, {
++ 92500000, {
++ { 0x0140, 0x0005 },
++ { 0x2141, 0x0005 },
++ { 0x4142, 0x0005 },
++ },
++ }, {
++ 148500000, {
++ { 0x00a0, 0x000a },
++ { 0x20a1, 0x000a },
++ { 0x40a2, 0x000a },
++ },
++ }, {
++ ~0UL, {
++ { 0x00a0, 0x000a },
++ { 0x2001, 0x000f },
++ { 0x4002, 0x000f },
++ },
++ }
++};
++
++struct curr_ctrl {
++ unsigned long mpixelclock;
++ u16 curr[RES_MAX];
++};
++
++static const struct curr_ctrl curr_ctrl[] = {
++ /* pixelclk bpp8 bpp10 bpp12 */
++ {
++ 54000000, { 0x091c, 0x091c, 0x06dc },
++ }, {
++ 58400000, { 0x091c, 0x06dc, 0x06dc },
++ }, {
++ 72000000, { 0x06dc, 0x06dc, 0x091c },
++ }, {
++ 74250000, { 0x06dc, 0x0b5c, 0x091c },
++ }, {
++ 118800000, { 0x091c, 0x091c, 0x06dc },
++ }, {
++ 216000000, { 0x06dc, 0x0b5c, 0x091c },
++ }
++};
++
++static int hdmi_phy_configure(struct imx_hdmi *hdmi, unsigned char prep,
++ unsigned char res, int cscon)
++{
++ unsigned res_idx, i;
++ u8 val, msec;
++
++ if (prep)
++ return -EINVAL;
++
++ switch (res) {
++ case 0: /* color resolution 0 is 8 bit colour depth */
++ case 8:
++ res_idx = RES_8;
++ break;
++ case 10:
++ res_idx = RES_10;
++ break;
++ case 12:
++ res_idx = RES_12;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* Enable csc path */
++ if (cscon)
++ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
++ else
++ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
++
++ hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
++
++ /* gen2 tx power off */
++ imx_hdmi_phy_gen2_txpwron(hdmi, 0);
++
++ /* gen2 pddq */
++ imx_hdmi_phy_gen2_pddq(hdmi, 1);
++
++ /* PHY reset */
++ hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
++ hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
++
++ hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
++
++ hdmi_phy_test_clear(hdmi, 1);
++ hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
++ HDMI_PHY_I2CM_SLAVE_ADDR);
++ hdmi_phy_test_clear(hdmi, 0);
++
++ /* PLL/MPLL Cfg - always match on final entry */
++ for (i = 0; i < ARRAY_SIZE(mpll_config) - 1; i++)
++ if (hdmi->hdmi_data.video_mode.mpixelclock <=
++ mpll_config[i].mpixelclock)
++ break;
++
++ hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].cpce, 0x06);
++ hdmi_phy_i2c_write(hdmi, mpll_config[i].res[res_idx].gmp, 0x15);
++
++ for (i = 0; i < ARRAY_SIZE(curr_ctrl); i++)
++ if (hdmi->hdmi_data.video_mode.mpixelclock <=
++ curr_ctrl[i].mpixelclock)
++ break;
++
++ if (i >= ARRAY_SIZE(curr_ctrl)) {
++ dev_err(hdmi->dev,
++ "Pixel clock %d - unsupported by HDMI\n",
++ hdmi->hdmi_data.video_mode.mpixelclock);
++ return -EINVAL;
++ }
++
++ /* CURRCTRL */
++ hdmi_phy_i2c_write(hdmi, curr_ctrl[i].curr[res_idx], 0x10);
++
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
++ hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
++ /* RESISTANCE TERM 133Ohm Cfg */
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
++ /* PREEMP Cgf 0.00 */
++ hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */
++ /* TX/CK LVL 10 */
++ hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
++ /* REMOVE CLK TERM */
++ hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
++
++ imx_hdmi_phy_enable_power(hdmi, 1);
++
++ /* toggle TMDS enable */
++ imx_hdmi_phy_enable_tmds(hdmi, 0);
++ imx_hdmi_phy_enable_tmds(hdmi, 1);
++
++ /* gen2 tx power on */
++ imx_hdmi_phy_gen2_txpwron(hdmi, 1);
++ imx_hdmi_phy_gen2_pddq(hdmi, 0);
++
++ /*Wait for PHY PLL lock */
++ msec = 5;
++ do {
++ val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
++ if (!val)
++ break;
++
++ if (msec == 0) {
++ dev_err(hdmi->dev, "PHY PLL not locked\n");
++ return -EINVAL;
++ }
++
++ udelay(1000);
++ msec--;
++ } while (1);
++
++ return 0;
++}
++
++static int imx_hdmi_phy_init(struct imx_hdmi *hdmi)
++{
++ int i, ret;
++ bool cscon = false;
++
++ /*check csc whether needed activated in HDMI mode */
++ cscon = (is_color_space_conversion(hdmi) &&
++ !hdmi->hdmi_data.video_mode.mdvi);
++
++ /* HDMI Phy spec says to do the phy initialization sequence twice */
++ for (i = 0; i < 2; i++) {
++ imx_hdmi_phy_sel_data_en_pol(hdmi, 1);
++ imx_hdmi_phy_sel_interface_control(hdmi, 0);
++ imx_hdmi_phy_enable_tmds(hdmi, 0);
++ imx_hdmi_phy_enable_power(hdmi, 0);
++
++ /* Enable CSC */
++ ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
++ if (ret)
++ return ret;
++ }
++
++ hdmi->phy_enabled = true;
++ return 0;
++}
++
++static void hdmi_tx_hdcp_config(struct imx_hdmi *hdmi)
++{
++ u8 de;
++
++ if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
++ de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
++ else
++ de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
++
++ /* disable rx detect */
++ hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
++ HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
++
++ hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
++
++ hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
++ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
++}
++
++static void hdmi_config_AVI(struct imx_hdmi *hdmi)
++{
++ u8 val, pix_fmt, under_scan;
++ u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
++ bool aspect_16_9;
++
++ aspect_16_9 = false; /* FIXME */
++
++ /* AVI Data Byte 1 */
++ if (hdmi->hdmi_data.enc_out_format == YCBCR444)
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
++ else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
++ else
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
++
++ under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
++
++ /*
++ * Active format identification data is present in the AVI InfoFrame.
++ * Under scan info, no bar data
++ */
++ val = pix_fmt | under_scan |
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
++
++ hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
++
++ /* AVI Data Byte 2 -Set the Aspect Ratio */
++ if (aspect_16_9) {
++ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
++ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
++ } else {
++ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
++ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
++ }
++
++ /* Set up colorimetry */
++ if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
++ if (hdmi->hdmi_data.colorimetry == ITU601)
++ ext_colorimetry =
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ else /* hdmi->hdmi_data.colorimetry == ITU709 */
++ ext_colorimetry =
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
++ } else if (hdmi->hdmi_data.enc_out_format != RGB) {
++ if (hdmi->hdmi_data.colorimetry == ITU601)
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
++ else /* hdmi->hdmi_data.colorimetry == ITU709 */
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
++ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ } else { /* Carries no data */
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
++ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ }
++
++ val = colorimetry | coded_ratio | act_ratio;
++ hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
++
++ /* AVI Data Byte 3 */
++ val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
++ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
++ HDMI_FC_AVICONF2_SCALING_NONE;
++ hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
++
++ /* AVI Data Byte 4 */
++ hdmi_writeb(hdmi, hdmi->vic, HDMI_FC_AVIVID);
++
++ /* AVI Data Byte 5- set up input and output pixel repetition */
++ val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
++ ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
++ hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
++
++ /* IT Content and quantization range = don't care */
++ val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
++ hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
++
++ /* AVI Data Bytes 6-13 */
++ hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB0);
++ hdmi_writeb(hdmi, 0, HDMI_FC_AVIETB1);
++ hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB0);
++ hdmi_writeb(hdmi, 0, HDMI_FC_AVISBB1);
++ hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB0);
++ hdmi_writeb(hdmi, 0, HDMI_FC_AVIELB1);
++ hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB0);
++ hdmi_writeb(hdmi, 0, HDMI_FC_AVISRB1);
++}
++
++static void hdmi_av_composer(struct imx_hdmi *hdmi,
++ const struct drm_display_mode *mode)
++{
++ u8 inv_val;
++ struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
++ int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
++
++ vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
++ vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
++ vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
++ vmode->mpixelclock = mode->clock * 1000;
++
++ dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
++
++ /* Set up HDMI_FC_INVIDCONF */
++ inv_val = (hdmi->hdmi_data.hdcp_enable ?
++ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
++ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
++
++ inv_val |= (vmode->mvsyncpolarity ?
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
++
++ inv_val |= (vmode->mhsyncpolarity ?
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
++
++ inv_val |= (vmode->mdataenablepolarity ?
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
++
++ if (hdmi->vic == 39)
++ inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
++ else
++ inv_val |= (vmode->minterlaced ?
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
++
++ inv_val |= (vmode->minterlaced ?
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
++
++ inv_val |= (vmode->mdvi ?
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
++
++ hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
++
++ /* Set up horizontal active pixel width */
++ hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
++ hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
++
++ /* Set up vertical active lines */
++ hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
++ hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
++
++ /* Set up horizontal blanking pixel region width */
++ hblank = mode->htotal - mode->hdisplay;
++ hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
++ hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
++
++ /* Set up vertical blanking pixel region width */
++ vblank = mode->vtotal - mode->vdisplay;
++ hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
++
++ /* Set up HSYNC active edge delay width (in pixel clks) */
++ h_de_hs = mode->hsync_start - mode->hdisplay;
++ hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
++ hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
++
++ /* Set up VSYNC active edge delay (in lines) */
++ v_de_vs = mode->vsync_start - mode->vdisplay;
++ hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
++
++ /* Set up HSYNC active pulse width (in pixel clks) */
++ hsync_len = mode->hsync_end - mode->hsync_start;
++ hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
++ hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
++
++ /* Set up VSYNC active edge delay (in lines) */
++ vsync_len = mode->vsync_end - mode->vsync_start;
++ hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
++}
++
++static void imx_hdmi_phy_disable(struct imx_hdmi *hdmi)
++{
++ if (!hdmi->phy_enabled)
++ return;
++
++ imx_hdmi_phy_enable_tmds(hdmi, 0);
++ imx_hdmi_phy_enable_power(hdmi, 0);
++
++ hdmi->phy_enabled = false;
++}
++
++/* HDMI Initialization Step B.4 */
++static void imx_hdmi_enable_video_path(struct imx_hdmi *hdmi)
++{
++ /* control period minimum duration */
++ hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
++ hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
++ hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
++
++ /* Set to fill TMDS data channels */
++ hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
++ hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
++ hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
++
++ /* Enable pixel clock and tmds data path */
++ hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
++ HDMI_MC_CLKDIS_CSCCLK_DISABLE |
++ HDMI_MC_CLKDIS_AUDCLK_DISABLE |
++ HDMI_MC_CLKDIS_PREPCLK_DISABLE |
++ HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
++ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
++ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
++
++ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
++ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
++
++ /* Enable csc path */
++ if (is_color_space_conversion(hdmi)) {
++ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
++ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
++ }
++}
++
++static void hdmi_enable_audio_clk(struct imx_hdmi *hdmi)
++{
++ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
++ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
++}
++
++/* Workaround to clear the overflow condition */
++static void imx_hdmi_clear_overflow(struct imx_hdmi *hdmi)
++{
++ int count;
++ u8 val;
++
++ /* TMDS software reset */
++ hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
++
++ val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
++ if (hdmi->dev_type == IMX6DL_HDMI) {
++ hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
++ return;
++ }
++
++ for (count = 0; count < 4; count++)
++ hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
++}
++
++static void hdmi_enable_overflow_interrupts(struct imx_hdmi *hdmi)
++{
++ hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
++ hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
++}
++
++static void hdmi_disable_overflow_interrupts(struct imx_hdmi *hdmi)
++{
++ hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
++ HDMI_IH_MUTE_FC_STAT2);
++}
++
++static int imx_hdmi_setup(struct imx_hdmi *hdmi, struct drm_display_mode *mode)
++{
++ int ret;
++
++ hdmi_disable_overflow_interrupts(hdmi);
++
++ hdmi->vic = drm_match_cea_mode(mode);
++
++ if (!hdmi->vic) {
++ dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
++ hdmi->hdmi_data.video_mode.mdvi = true;
++ } else {
++ dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
++ hdmi->hdmi_data.video_mode.mdvi = false;
++ }
++
++ if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
++ (hdmi->vic == 21) || (hdmi->vic == 22) ||
++ (hdmi->vic == 2) || (hdmi->vic == 3) ||
++ (hdmi->vic == 17) || (hdmi->vic == 18))
++ hdmi->hdmi_data.colorimetry = ITU601;
++ else
++ hdmi->hdmi_data.colorimetry = ITU709;
++
++ if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
++ (hdmi->vic == 12) || (hdmi->vic == 13) ||
++ (hdmi->vic == 14) || (hdmi->vic == 15) ||
++ (hdmi->vic == 25) || (hdmi->vic == 26) ||
++ (hdmi->vic == 27) || (hdmi->vic == 28) ||
++ (hdmi->vic == 29) || (hdmi->vic == 30) ||
++ (hdmi->vic == 35) || (hdmi->vic == 36) ||
++ (hdmi->vic == 37) || (hdmi->vic == 38))
++ hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
++ else
++ hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
++
++ hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
++
++ /* TODO: Get input format from IPU (via FB driver interface) */
++ hdmi->hdmi_data.enc_in_format = RGB;
++
++ hdmi->hdmi_data.enc_out_format = RGB;
++
++ hdmi->hdmi_data.enc_color_depth = 8;
++ hdmi->hdmi_data.pix_repet_factor = 0;
++ hdmi->hdmi_data.hdcp_enable = 0;
++ hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
++
++ /* HDMI Initialization Step B.1 */
++ hdmi_av_composer(hdmi, mode);
++
++ /* HDMI Initializateion Step B.2 */
++ ret = imx_hdmi_phy_init(hdmi);
++ if (ret)
++ return ret;
++
++ /* HDMI Initialization Step B.3 */
++ imx_hdmi_enable_video_path(hdmi);
++
++ /* not for DVI mode */
++ if (hdmi->hdmi_data.video_mode.mdvi)
++ dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
++ else {
++ dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
++
++ /* HDMI Initialization Step E - Configure audio */
++ hdmi_clk_regenerator_update_pixel_clock(hdmi);
++ hdmi_enable_audio_clk(hdmi);
++
++ /* HDMI Initialization Step F - Configure AVI InfoFrame */
++ hdmi_config_AVI(hdmi);
++ }
++
++ hdmi_video_packetize(hdmi);
++ hdmi_video_csc(hdmi);
++ hdmi_video_sample(hdmi);
++ hdmi_tx_hdcp_config(hdmi);
++
++ imx_hdmi_clear_overflow(hdmi);
++ if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
++ hdmi_enable_overflow_interrupts(hdmi);
++
++ return 0;
++}
++
++/* Wait until we are registered to enable interrupts */
++static int imx_hdmi_fb_registered(struct imx_hdmi *hdmi)
++{
++ hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
++ HDMI_PHY_I2CM_INT_ADDR);
++
++ hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
++ HDMI_PHY_I2CM_CTLINT_ADDR);
++
++ /* enable cable hot plug irq */
++ hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
++
++ return 0;
++}
++
++static void initialize_hdmi_ih_mutes(struct imx_hdmi *hdmi)
++{
++ u8 ih_mute;
++
++ /*
++ * Boot up defaults are:
++ * HDMI_IH_MUTE = 0x03 (disabled)
++ * HDMI_IH_MUTE_* = 0x00 (enabled)
++ *
++ * Disable top level interrupt bits in HDMI block
++ */
++ ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
++
++ hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
++
++ /* by default mask all interrupts */
++ hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
++ hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
++ hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
++ hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
++ hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
++ hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
++ hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
++ hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
++ hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
++ hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
++ hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
++ hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
++ hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
++ hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
++ hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
++
++ /* Disable interrupts in the IH_MUTE_* registers */
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
++ hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++
++ /* Enable top level interrupt bits in HDMI block */
++ ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
++ hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
++}
++
++static void imx_hdmi_poweron(struct imx_hdmi *hdmi)
++{
++ imx_hdmi_setup(hdmi, &hdmi->previous_mode);
++}
++
++static void imx_hdmi_poweroff(struct imx_hdmi *hdmi)
++{
++ imx_hdmi_phy_disable(hdmi);
++}
++
++static enum drm_connector_status imx_hdmi_connector_detect(struct drm_connector
++ *connector, bool force)
++{
++ struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
++ connector);
++ return hdmi->connector_status;
++}
++
++static int imx_hdmi_connector_get_modes(struct drm_connector *connector)
++{
++ struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
++ connector);
++ struct edid *edid;
++ int ret;
++
++ if (!hdmi->ddc)
++ return 0;
++
++ edid = drm_get_edid(connector, hdmi->ddc);
++ if (edid) {
++ dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
++ edid->width_cm, edid->height_cm);
++
++ drm_mode_connector_update_edid_property(connector, edid);
++ ret = drm_add_edid_modes(connector, edid);
++ /* Store the ELD */
++ drm_edid_to_eld(connector, edid);
++ kfree(edid);
++ } else {
++ dev_dbg(hdmi->dev, "failed to get edid\n");
++ }
++
++ return 0;
++}
++
++static struct drm_encoder *imx_hdmi_connector_best_encoder(struct drm_connector
++ *connector)
++{
++ struct imx_hdmi *hdmi = container_of(connector, struct imx_hdmi,
++ connector);
++
++ return &hdmi->encoder;
++}
++
++static void imx_hdmi_encoder_mode_set(struct drm_encoder *encoder,
++ struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
++{
++ struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
++
++ imx_hdmi_setup(hdmi, mode);
++
++ /* Store the display mode for plugin/DKMS poweron events */
++ memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
++}
++
++static bool imx_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
++ const struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
++{
++ return true;
++}
++
++static void imx_hdmi_encoder_disable(struct drm_encoder *encoder)
++{
++}
++
++static void imx_hdmi_encoder_dpms(struct drm_encoder *encoder, int mode)
++{
++ struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
++
++ if (mode)
++ imx_hdmi_poweroff(hdmi);
++ else
++ imx_hdmi_poweron(hdmi);
++}
++
++static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
++{
++ struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
++
++ imx_hdmi_poweroff(hdmi);
++ imx_drm_panel_format(encoder, V4L2_PIX_FMT_RGB24);
++}
++
++static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
++{
++ struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
++ int mux = imx_drm_encoder_get_mux_id(encoder);
++
++ imx_hdmi_set_ipu_di_mux(hdmi, mux);
++
++ imx_hdmi_poweron(hdmi);
++}
++
++static struct drm_encoder_funcs imx_hdmi_encoder_funcs = {
++ .destroy = imx_drm_encoder_destroy,
++};
++
++static struct drm_encoder_helper_funcs imx_hdmi_encoder_helper_funcs = {
++ .dpms = imx_hdmi_encoder_dpms,
++ .prepare = imx_hdmi_encoder_prepare,
++ .commit = imx_hdmi_encoder_commit,
++ .mode_set = imx_hdmi_encoder_mode_set,
++ .mode_fixup = imx_hdmi_encoder_mode_fixup,
++ .disable = imx_hdmi_encoder_disable,
++};
++
++static struct drm_connector_funcs imx_hdmi_connector_funcs = {
++ .dpms = drm_helper_connector_dpms,
++ .fill_modes = drm_helper_probe_single_connector_modes,
++ .detect = imx_hdmi_connector_detect,
++ .destroy = imx_drm_connector_destroy,
++};
++
++static struct drm_connector_helper_funcs imx_hdmi_connector_helper_funcs = {
++ .get_modes = imx_hdmi_connector_get_modes,
++ .mode_valid = imx_drm_connector_mode_valid,
++ .best_encoder = imx_hdmi_connector_best_encoder,
++};
++
++static irqreturn_t imx_hdmi_hardirq(int irq, void *dev_id)
++{
++ struct imx_hdmi *hdmi = dev_id;
++ u8 intr_stat;
++
++ intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
++ if (intr_stat)
++ hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
++
++ return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
++}
++
++static irqreturn_t imx_hdmi_irq(int irq, void *dev_id)
++{
++ struct imx_hdmi *hdmi = dev_id;
++ u8 intr_stat;
++ u8 phy_int_pol;
++
++ intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
++
++ phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
++
++ if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
++ if (phy_int_pol & HDMI_PHY_HPD) {
++ dev_dbg(hdmi->dev, "EVENT=plugin\n");
++
++ hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
++
++ hdmi->connector_status = connector_status_connected;
++ imx_hdmi_poweron(hdmi);
++ } else {
++ dev_dbg(hdmi->dev, "EVENT=plugout\n");
++
++ hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD, HDMI_PHY_POL0);
++
++ hdmi->connector_status = connector_status_disconnected;
++ imx_hdmi_poweroff(hdmi);
++ }
++ drm_helper_hpd_irq_event(hdmi->connector.dev);
++ }
++
++ hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
++ hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
++
++ return IRQ_HANDLED;
++}
++
++static int imx_hdmi_register(struct drm_device *drm, struct imx_hdmi *hdmi)
++{
++ int ret;
++
++ ret = imx_drm_encoder_parse_of(drm, &hdmi->encoder,
++ hdmi->dev->of_node);
++ if (ret)
++ return ret;
++
++ hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
++
++ drm_encoder_helper_add(&hdmi->encoder, &imx_hdmi_encoder_helper_funcs);
++ drm_encoder_init(drm, &hdmi->encoder, &imx_hdmi_encoder_funcs,
++ DRM_MODE_ENCODER_TMDS);
++
++ drm_connector_helper_add(&hdmi->connector,
++ &imx_hdmi_connector_helper_funcs);
++ drm_connector_init(drm, &hdmi->connector, &imx_hdmi_connector_funcs,
++ DRM_MODE_CONNECTOR_HDMIA);
++
++ hdmi->connector.encoder = &hdmi->encoder;
++
++ drm_mode_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
++
++ return 0;
++}
++
++static void imx_hdmi_cec_enable(void *data)
++{
++ struct imx_hdmi *hdmi = data;
++
++ hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
++}
++
++static void imx_hdmi_cec_disable(void *data)
++{
++ struct imx_hdmi *hdmi = data;
++
++ hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
++}
++
++static const struct dw_hdmi_cec_ops imx_hdmi_cec_ops = {
++ .enable = imx_hdmi_cec_enable,
++ .disable = imx_hdmi_cec_disable,
++};
++
++static struct platform_device_id imx_hdmi_devtype[] = {
++ {
++ .name = "imx6q-hdmi",
++ .driver_data = IMX6Q_HDMI,
++ }, {
++ .name = "imx6dl-hdmi",
++ .driver_data = IMX6DL_HDMI,
++ }, { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++{ .compatible = "fsl,imx6q-hdmi", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
++{ .compatible = "fsl,imx6dl-hdmi", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
++{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
++
++static int imx_hdmi_bind(struct device *dev, struct device *master, void *data)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct platform_device_info pdevinfo;
++ const struct of_device_id *of_id =
++ of_match_device(imx_hdmi_dt_ids, dev);
++ struct drm_device *drm = data;
++ struct device_node *np = dev->of_node;
++ struct device_node *ddc_node;
++ struct dw_hdmi_cec_data cec;
++ struct imx_hdmi *hdmi;
++ struct resource *iores;
++ int ret, irq;
++
++ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
++ if (!hdmi)
++ return -ENOMEM;
++
++ hdmi->dev = dev;
++ hdmi->connector_status = connector_status_disconnected;
++ hdmi->sample_rate = 48000;
++ hdmi->ratio = 100;
++ hdmi->mc_clkdis = 0x7f;
++
++ if (of_id) {
++ const struct platform_device_id *device_id = of_id->data;
++ hdmi->dev_type = device_id->driver_data;
++ }
++
++ ddc_node = of_parse_phandle(np, "ddc", 0);
++ if (ddc_node) {
++ hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
++ if (!hdmi->ddc)
++ dev_dbg(hdmi->dev, "failed to read ddc node\n");
++
++ of_node_put(ddc_node);
++ } else {
++ dev_dbg(hdmi->dev, "no ddc property found\n");
++ }
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return -EINVAL;
++
++ ret = devm_request_threaded_irq(dev, irq, imx_hdmi_hardirq,
++ imx_hdmi_irq, IRQF_SHARED,
++ dev_name(dev), hdmi);
++ if (ret)
++ return ret;
++
++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ hdmi->regs = devm_ioremap_resource(dev, iores);
++ if (IS_ERR(hdmi->regs))
++ return PTR_ERR(hdmi->regs);
++
++ hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
++ if (IS_ERR(hdmi->regmap))
++ return PTR_ERR(hdmi->regmap);
++
++ hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
++ if (IS_ERR(hdmi->isfr_clk)) {
++ ret = PTR_ERR(hdmi->isfr_clk);
++ dev_err(hdmi->dev,
++ "Unable to get HDMI isfr clk: %d\n", ret);
++ return ret;
++ }
++
++ ret = clk_prepare_enable(hdmi->isfr_clk);
++ if (ret) {
++ dev_err(hdmi->dev,
++ "Cannot enable HDMI isfr clock: %d\n", ret);
++ return ret;
++ }
++
++ hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
++ if (IS_ERR(hdmi->iahb_clk)) {
++ ret = PTR_ERR(hdmi->iahb_clk);
++ dev_err(hdmi->dev,
++ "Unable to get HDMI iahb clk: %d\n", ret);
++ goto err_isfr;
++ }
++
++ ret = clk_prepare_enable(hdmi->iahb_clk);
++ if (ret) {
++ dev_err(hdmi->dev,
++ "Cannot enable HDMI iahb clock: %d\n", ret);
++ goto err_isfr;
++ }
++
++ /* Product and revision IDs */
++ dev_info(dev,
++ "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
++ hdmi_readb(hdmi, HDMI_DESIGN_ID),
++ hdmi_readb(hdmi, HDMI_REVISION_ID),
++ hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
++ hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
++
++ initialize_hdmi_ih_mutes(hdmi);
++
++ /*
++ * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
++ * N and cts values before enabling phy
++ */
++ hdmi_init_clk_regenerator(hdmi);
++
++ /*
++ * Configure registers related to HDMI interrupt
++ * generation before registering IRQ.
++ */
++ hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
++
++ ret = imx_hdmi_fb_registered(hdmi);
++ if (ret)
++ goto err_iahb;
++
++ ret = imx_hdmi_register(drm, hdmi);
++ if (ret)
++ goto err_iahb;
++
++ /* Unmute interrupts */
++ hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
++
++ ret = snd_dw_hdmi_probe(&hdmi->audio, dev, hdmi->regs, irq, hdmi);
++ if (ret)
++ goto err_audio;
++
++ cec.base = hdmi->regs;
++ cec.irq = irq;
++ cec.ops = &imx_hdmi_cec_ops;
++ cec.ops_data = hdmi;
++
++ memset(&pdevinfo, 0, sizeof(pdevinfo));
++ pdevinfo.parent = dev;
++ pdevinfo.name = "dw-hdmi-cec";
++ pdevinfo.id = PLATFORM_DEVID_AUTO;
++ pdevinfo.data = &cec;
++ pdevinfo.size_data = sizeof(cec);
++
++ hdmi->cec = platform_device_register_full(&pdevinfo);
++
++ dev_set_drvdata(dev, hdmi);
++
++ return 0;
++
++err_audio:
++ /* Disable all interrupts */
++ hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
++
++ hdmi->connector.funcs->destroy(&hdmi->connector);
++ hdmi->encoder.funcs->destroy(&hdmi->encoder);
++err_iahb:
++ clk_disable_unprepare(hdmi->iahb_clk);
++err_isfr:
++ clk_disable_unprepare(hdmi->isfr_clk);
++
++ return ret;
++}
++
++static void imx_hdmi_unbind(struct device *dev, struct device *master,
++ void *data)
++{
++ struct imx_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (!IS_ERR(hdmi->cec))
++ platform_device_unregister(hdmi->cec);
++ snd_dw_hdmi_remove(hdmi->audio);
++
++ /* Disable all interrupts */
++ hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
++
++ hdmi->connector.funcs->destroy(&hdmi->connector);
++ hdmi->encoder.funcs->destroy(&hdmi->encoder);
++
++ clk_disable_unprepare(hdmi->iahb_clk);
++ clk_disable_unprepare(hdmi->isfr_clk);
++ i2c_put_adapter(hdmi->ddc);
++}
++
++static const struct component_ops hdmi_ops = {
++ .bind = imx_hdmi_bind,
++ .unbind = imx_hdmi_unbind,
++};
++
++static int imx_hdmi_platform_probe(struct platform_device *pdev)
++{
++ return component_add(&pdev->dev, &hdmi_ops);
++}
++
++static int imx_hdmi_platform_remove(struct platform_device *pdev)
++{
++ component_del(&pdev->dev, &hdmi_ops);
++ return 0;
++}
++
++static struct platform_driver imx_hdmi_driver = {
++ .probe = imx_hdmi_platform_probe,
++ .remove = imx_hdmi_platform_remove,
++ .driver = {
++ .name = "imx-hdmi",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_hdmi_dt_ids,
++ },
++};
++
++module_platform_driver(imx_hdmi_driver);
++
++MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
++MODULE_DESCRIPTION("i.MX6 HDMI transmitter driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-hdmi");
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/imx-hdmi.h linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-hdmi.h
+--- linux-3.10.30.orig/drivers/staging/imx-drm/imx-hdmi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-hdmi.h 2014-05-15 20:34:05.754069749 +0200
+@@ -0,0 +1,1040 @@
++/*
++ * Copyright (C) 2011 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef __IMX_HDMI_H__
++#define __IMX_HDMI_H__
++
++/* Identification Registers */
++#define HDMI_DESIGN_ID 0x0000
++#define HDMI_REVISION_ID 0x0001
++#define HDMI_PRODUCT_ID0 0x0002
++#define HDMI_PRODUCT_ID1 0x0003
++#define HDMI_CONFIG0_ID 0x0004
++#define HDMI_CONFIG1_ID 0x0005
++#define HDMI_CONFIG2_ID 0x0006
++#define HDMI_CONFIG3_ID 0x0007
++
++/* Interrupt Registers */
++#define HDMI_IH_FC_STAT0 0x0100
++#define HDMI_IH_FC_STAT1 0x0101
++#define HDMI_IH_FC_STAT2 0x0102
++#define HDMI_IH_AS_STAT0 0x0103
++#define HDMI_IH_PHY_STAT0 0x0104
++#define HDMI_IH_I2CM_STAT0 0x0105
++#define HDMI_IH_CEC_STAT0 0x0106
++#define HDMI_IH_VP_STAT0 0x0107
++#define HDMI_IH_I2CMPHY_STAT0 0x0108
++#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
++
++#define HDMI_IH_MUTE_FC_STAT0 0x0180
++#define HDMI_IH_MUTE_FC_STAT1 0x0181
++#define HDMI_IH_MUTE_FC_STAT2 0x0182
++#define HDMI_IH_MUTE_AS_STAT0 0x0183
++#define HDMI_IH_MUTE_PHY_STAT0 0x0184
++#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
++#define HDMI_IH_MUTE_CEC_STAT0 0x0186
++#define HDMI_IH_MUTE_VP_STAT0 0x0187
++#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
++#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
++#define HDMI_IH_MUTE 0x01FF
++
++/* Video Sample Registers */
++#define HDMI_TX_INVID0 0x0200
++#define HDMI_TX_INSTUFFING 0x0201
++#define HDMI_TX_GYDATA0 0x0202
++#define HDMI_TX_GYDATA1 0x0203
++#define HDMI_TX_RCRDATA0 0x0204
++#define HDMI_TX_RCRDATA1 0x0205
++#define HDMI_TX_BCBDATA0 0x0206
++#define HDMI_TX_BCBDATA1 0x0207
++
++/* Video Packetizer Registers */
++#define HDMI_VP_STATUS 0x0800
++#define HDMI_VP_PR_CD 0x0801
++#define HDMI_VP_STUFF 0x0802
++#define HDMI_VP_REMAP 0x0803
++#define HDMI_VP_CONF 0x0804
++#define HDMI_VP_STAT 0x0805
++#define HDMI_VP_INT 0x0806
++#define HDMI_VP_MASK 0x0807
++#define HDMI_VP_POL 0x0808
++
++/* Frame Composer Registers */
++#define HDMI_FC_INVIDCONF 0x1000
++#define HDMI_FC_INHACTV0 0x1001
++#define HDMI_FC_INHACTV1 0x1002
++#define HDMI_FC_INHBLANK0 0x1003
++#define HDMI_FC_INHBLANK1 0x1004
++#define HDMI_FC_INVACTV0 0x1005
++#define HDMI_FC_INVACTV1 0x1006
++#define HDMI_FC_INVBLANK 0x1007
++#define HDMI_FC_HSYNCINDELAY0 0x1008
++#define HDMI_FC_HSYNCINDELAY1 0x1009
++#define HDMI_FC_HSYNCINWIDTH0 0x100A
++#define HDMI_FC_HSYNCINWIDTH1 0x100B
++#define HDMI_FC_VSYNCINDELAY 0x100C
++#define HDMI_FC_VSYNCINWIDTH 0x100D
++#define HDMI_FC_INFREQ0 0x100E
++#define HDMI_FC_INFREQ1 0x100F
++#define HDMI_FC_INFREQ2 0x1010
++#define HDMI_FC_CTRLDUR 0x1011
++#define HDMI_FC_EXCTRLDUR 0x1012
++#define HDMI_FC_EXCTRLSPAC 0x1013
++#define HDMI_FC_CH0PREAM 0x1014
++#define HDMI_FC_CH1PREAM 0x1015
++#define HDMI_FC_CH2PREAM 0x1016
++#define HDMI_FC_AVICONF3 0x1017
++#define HDMI_FC_GCP 0x1018
++#define HDMI_FC_AVICONF0 0x1019
++#define HDMI_FC_AVICONF1 0x101A
++#define HDMI_FC_AVICONF2 0x101B
++#define HDMI_FC_AVIVID 0x101C
++#define HDMI_FC_AVIETB0 0x101D
++#define HDMI_FC_AVIETB1 0x101E
++#define HDMI_FC_AVISBB0 0x101F
++#define HDMI_FC_AVISBB1 0x1020
++#define HDMI_FC_AVIELB0 0x1021
++#define HDMI_FC_AVIELB1 0x1022
++#define HDMI_FC_AVISRB0 0x1023
++#define HDMI_FC_AVISRB1 0x1024
++#define HDMI_FC_AUDICONF0 0x1025
++#define HDMI_FC_AUDICONF1 0x1026
++#define HDMI_FC_AUDICONF2 0x1027
++#define HDMI_FC_AUDICONF3 0x1028
++#define HDMI_FC_VSDIEEEID0 0x1029
++#define HDMI_FC_VSDSIZE 0x102A
++#define HDMI_FC_VSDIEEEID1 0x1030
++#define HDMI_FC_VSDIEEEID2 0x1031
++#define HDMI_FC_VSDPAYLOAD0 0x1032
++#define HDMI_FC_VSDPAYLOAD1 0x1033
++#define HDMI_FC_VSDPAYLOAD2 0x1034
++#define HDMI_FC_VSDPAYLOAD3 0x1035
++#define HDMI_FC_VSDPAYLOAD4 0x1036
++#define HDMI_FC_VSDPAYLOAD5 0x1037
++#define HDMI_FC_VSDPAYLOAD6 0x1038
++#define HDMI_FC_VSDPAYLOAD7 0x1039
++#define HDMI_FC_VSDPAYLOAD8 0x103A
++#define HDMI_FC_VSDPAYLOAD9 0x103B
++#define HDMI_FC_VSDPAYLOAD10 0x103C
++#define HDMI_FC_VSDPAYLOAD11 0x103D
++#define HDMI_FC_VSDPAYLOAD12 0x103E
++#define HDMI_FC_VSDPAYLOAD13 0x103F
++#define HDMI_FC_VSDPAYLOAD14 0x1040
++#define HDMI_FC_VSDPAYLOAD15 0x1041
++#define HDMI_FC_VSDPAYLOAD16 0x1042
++#define HDMI_FC_VSDPAYLOAD17 0x1043
++#define HDMI_FC_VSDPAYLOAD18 0x1044
++#define HDMI_FC_VSDPAYLOAD19 0x1045
++#define HDMI_FC_VSDPAYLOAD20 0x1046
++#define HDMI_FC_VSDPAYLOAD21 0x1047
++#define HDMI_FC_VSDPAYLOAD22 0x1048
++#define HDMI_FC_VSDPAYLOAD23 0x1049
++#define HDMI_FC_SPDVENDORNAME0 0x104A
++#define HDMI_FC_SPDVENDORNAME1 0x104B
++#define HDMI_FC_SPDVENDORNAME2 0x104C
++#define HDMI_FC_SPDVENDORNAME3 0x104D
++#define HDMI_FC_SPDVENDORNAME4 0x104E
++#define HDMI_FC_SPDVENDORNAME5 0x104F
++#define HDMI_FC_SPDVENDORNAME6 0x1050
++#define HDMI_FC_SPDVENDORNAME7 0x1051
++#define HDMI_FC_SDPPRODUCTNAME0 0x1052
++#define HDMI_FC_SDPPRODUCTNAME1 0x1053
++#define HDMI_FC_SDPPRODUCTNAME2 0x1054
++#define HDMI_FC_SDPPRODUCTNAME3 0x1055
++#define HDMI_FC_SDPPRODUCTNAME4 0x1056
++#define HDMI_FC_SDPPRODUCTNAME5 0x1057
++#define HDMI_FC_SDPPRODUCTNAME6 0x1058
++#define HDMI_FC_SDPPRODUCTNAME7 0x1059
++#define HDMI_FC_SDPPRODUCTNAME8 0x105A
++#define HDMI_FC_SDPPRODUCTNAME9 0x105B
++#define HDMI_FC_SDPPRODUCTNAME10 0x105C
++#define HDMI_FC_SDPPRODUCTNAME11 0x105D
++#define HDMI_FC_SDPPRODUCTNAME12 0x105E
++#define HDMI_FC_SDPPRODUCTNAME13 0x105F
++#define HDMI_FC_SDPPRODUCTNAME14 0x1060
++#define HDMI_FC_SPDPRODUCTNAME15 0x1061
++#define HDMI_FC_SPDDEVICEINF 0x1062
++#define HDMI_FC_AUDSCONF 0x1063
++#define HDMI_FC_AUDSSTAT 0x1064
++#define HDMI_FC_DATACH0FILL 0x1070
++#define HDMI_FC_DATACH1FILL 0x1071
++#define HDMI_FC_DATACH2FILL 0x1072
++#define HDMI_FC_CTRLQHIGH 0x1073
++#define HDMI_FC_CTRLQLOW 0x1074
++#define HDMI_FC_ACP0 0x1075
++#define HDMI_FC_ACP28 0x1076
++#define HDMI_FC_ACP27 0x1077
++#define HDMI_FC_ACP26 0x1078
++#define HDMI_FC_ACP25 0x1079
++#define HDMI_FC_ACP24 0x107A
++#define HDMI_FC_ACP23 0x107B
++#define HDMI_FC_ACP22 0x107C
++#define HDMI_FC_ACP21 0x107D
++#define HDMI_FC_ACP20 0x107E
++#define HDMI_FC_ACP19 0x107F
++#define HDMI_FC_ACP18 0x1080
++#define HDMI_FC_ACP17 0x1081
++#define HDMI_FC_ACP16 0x1082
++#define HDMI_FC_ACP15 0x1083
++#define HDMI_FC_ACP14 0x1084
++#define HDMI_FC_ACP13 0x1085
++#define HDMI_FC_ACP12 0x1086
++#define HDMI_FC_ACP11 0x1087
++#define HDMI_FC_ACP10 0x1088
++#define HDMI_FC_ACP9 0x1089
++#define HDMI_FC_ACP8 0x108A
++#define HDMI_FC_ACP7 0x108B
++#define HDMI_FC_ACP6 0x108C
++#define HDMI_FC_ACP5 0x108D
++#define HDMI_FC_ACP4 0x108E
++#define HDMI_FC_ACP3 0x108F
++#define HDMI_FC_ACP2 0x1090
++#define HDMI_FC_ACP1 0x1091
++#define HDMI_FC_ISCR1_0 0x1092
++#define HDMI_FC_ISCR1_16 0x1093
++#define HDMI_FC_ISCR1_15 0x1094
++#define HDMI_FC_ISCR1_14 0x1095
++#define HDMI_FC_ISCR1_13 0x1096
++#define HDMI_FC_ISCR1_12 0x1097
++#define HDMI_FC_ISCR1_11 0x1098
++#define HDMI_FC_ISCR1_10 0x1099
++#define HDMI_FC_ISCR1_9 0x109A
++#define HDMI_FC_ISCR1_8 0x109B
++#define HDMI_FC_ISCR1_7 0x109C
++#define HDMI_FC_ISCR1_6 0x109D
++#define HDMI_FC_ISCR1_5 0x109E
++#define HDMI_FC_ISCR1_4 0x109F
++#define HDMI_FC_ISCR1_3 0x10A0
++#define HDMI_FC_ISCR1_2 0x10A1
++#define HDMI_FC_ISCR1_1 0x10A2
++#define HDMI_FC_ISCR2_15 0x10A3
++#define HDMI_FC_ISCR2_14 0x10A4
++#define HDMI_FC_ISCR2_13 0x10A5
++#define HDMI_FC_ISCR2_12 0x10A6
++#define HDMI_FC_ISCR2_11 0x10A7
++#define HDMI_FC_ISCR2_10 0x10A8
++#define HDMI_FC_ISCR2_9 0x10A9
++#define HDMI_FC_ISCR2_8 0x10AA
++#define HDMI_FC_ISCR2_7 0x10AB
++#define HDMI_FC_ISCR2_6 0x10AC
++#define HDMI_FC_ISCR2_5 0x10AD
++#define HDMI_FC_ISCR2_4 0x10AE
++#define HDMI_FC_ISCR2_3 0x10AF
++#define HDMI_FC_ISCR2_2 0x10B0
++#define HDMI_FC_ISCR2_1 0x10B1
++#define HDMI_FC_ISCR2_0 0x10B2
++#define HDMI_FC_DATAUTO0 0x10B3
++#define HDMI_FC_DATAUTO1 0x10B4
++#define HDMI_FC_DATAUTO2 0x10B5
++#define HDMI_FC_DATMAN 0x10B6
++#define HDMI_FC_DATAUTO3 0x10B7
++#define HDMI_FC_RDRB0 0x10B8
++#define HDMI_FC_RDRB1 0x10B9
++#define HDMI_FC_RDRB2 0x10BA
++#define HDMI_FC_RDRB3 0x10BB
++#define HDMI_FC_RDRB4 0x10BC
++#define HDMI_FC_RDRB5 0x10BD
++#define HDMI_FC_RDRB6 0x10BE
++#define HDMI_FC_RDRB7 0x10BF
++#define HDMI_FC_STAT0 0x10D0
++#define HDMI_FC_INT0 0x10D1
++#define HDMI_FC_MASK0 0x10D2
++#define HDMI_FC_POL0 0x10D3
++#define HDMI_FC_STAT1 0x10D4
++#define HDMI_FC_INT1 0x10D5
++#define HDMI_FC_MASK1 0x10D6
++#define HDMI_FC_POL1 0x10D7
++#define HDMI_FC_STAT2 0x10D8
++#define HDMI_FC_INT2 0x10D9
++#define HDMI_FC_MASK2 0x10DA
++#define HDMI_FC_POL2 0x10DB
++#define HDMI_FC_PRCONF 0x10E0
++
++#define HDMI_FC_GMD_STAT 0x1100
++#define HDMI_FC_GMD_EN 0x1101
++#define HDMI_FC_GMD_UP 0x1102
++#define HDMI_FC_GMD_CONF 0x1103
++#define HDMI_FC_GMD_HB 0x1104
++#define HDMI_FC_GMD_PB0 0x1105
++#define HDMI_FC_GMD_PB1 0x1106
++#define HDMI_FC_GMD_PB2 0x1107
++#define HDMI_FC_GMD_PB3 0x1108
++#define HDMI_FC_GMD_PB4 0x1109
++#define HDMI_FC_GMD_PB5 0x110A
++#define HDMI_FC_GMD_PB6 0x110B
++#define HDMI_FC_GMD_PB7 0x110C
++#define HDMI_FC_GMD_PB8 0x110D
++#define HDMI_FC_GMD_PB9 0x110E
++#define HDMI_FC_GMD_PB10 0x110F
++#define HDMI_FC_GMD_PB11 0x1110
++#define HDMI_FC_GMD_PB12 0x1111
++#define HDMI_FC_GMD_PB13 0x1112
++#define HDMI_FC_GMD_PB14 0x1113
++#define HDMI_FC_GMD_PB15 0x1114
++#define HDMI_FC_GMD_PB16 0x1115
++#define HDMI_FC_GMD_PB17 0x1116
++#define HDMI_FC_GMD_PB18 0x1117
++#define HDMI_FC_GMD_PB19 0x1118
++#define HDMI_FC_GMD_PB20 0x1119
++#define HDMI_FC_GMD_PB21 0x111A
++#define HDMI_FC_GMD_PB22 0x111B
++#define HDMI_FC_GMD_PB23 0x111C
++#define HDMI_FC_GMD_PB24 0x111D
++#define HDMI_FC_GMD_PB25 0x111E
++#define HDMI_FC_GMD_PB26 0x111F
++#define HDMI_FC_GMD_PB27 0x1120
++
++#define HDMI_FC_DBGFORCE 0x1200
++#define HDMI_FC_DBGAUD0CH0 0x1201
++#define HDMI_FC_DBGAUD1CH0 0x1202
++#define HDMI_FC_DBGAUD2CH0 0x1203
++#define HDMI_FC_DBGAUD0CH1 0x1204
++#define HDMI_FC_DBGAUD1CH1 0x1205
++#define HDMI_FC_DBGAUD2CH1 0x1206
++#define HDMI_FC_DBGAUD0CH2 0x1207
++#define HDMI_FC_DBGAUD1CH2 0x1208
++#define HDMI_FC_DBGAUD2CH2 0x1209
++#define HDMI_FC_DBGAUD0CH3 0x120A
++#define HDMI_FC_DBGAUD1CH3 0x120B
++#define HDMI_FC_DBGAUD2CH3 0x120C
++#define HDMI_FC_DBGAUD0CH4 0x120D
++#define HDMI_FC_DBGAUD1CH4 0x120E
++#define HDMI_FC_DBGAUD2CH4 0x120F
++#define HDMI_FC_DBGAUD0CH5 0x1210
++#define HDMI_FC_DBGAUD1CH5 0x1211
++#define HDMI_FC_DBGAUD2CH5 0x1212
++#define HDMI_FC_DBGAUD0CH6 0x1213
++#define HDMI_FC_DBGAUD1CH6 0x1214
++#define HDMI_FC_DBGAUD2CH6 0x1215
++#define HDMI_FC_DBGAUD0CH7 0x1216
++#define HDMI_FC_DBGAUD1CH7 0x1217
++#define HDMI_FC_DBGAUD2CH7 0x1218
++#define HDMI_FC_DBGTMDS0 0x1219
++#define HDMI_FC_DBGTMDS1 0x121A
++#define HDMI_FC_DBGTMDS2 0x121B
++
++/* HDMI Source PHY Registers */
++#define HDMI_PHY_CONF0 0x3000
++#define HDMI_PHY_TST0 0x3001
++#define HDMI_PHY_TST1 0x3002
++#define HDMI_PHY_TST2 0x3003
++#define HDMI_PHY_STAT0 0x3004
++#define HDMI_PHY_INT0 0x3005
++#define HDMI_PHY_MASK0 0x3006
++#define HDMI_PHY_POL0 0x3007
++
++/* HDMI Master PHY Registers */
++#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
++#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
++#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
++#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
++#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
++#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
++#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
++#define HDMI_PHY_I2CM_INT_ADDR 0x3027
++#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
++#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
++#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
++
++/* Audio Sampler Registers */
++#define HDMI_AUD_CONF0 0x3100
++#define HDMI_AUD_CONF1 0x3101
++#define HDMI_AUD_INT 0x3102
++#define HDMI_AUD_CONF2 0x3103
++#define HDMI_AUD_N1 0x3200
++#define HDMI_AUD_N2 0x3201
++#define HDMI_AUD_N3 0x3202
++#define HDMI_AUD_CTS1 0x3203
++#define HDMI_AUD_CTS2 0x3204
++#define HDMI_AUD_CTS3 0x3205
++#define HDMI_AUD_INPUTCLKFS 0x3206
++#define HDMI_AUD_SPDIFINT 0x3302
++#define HDMI_AUD_CONF0_HBR 0x3400
++#define HDMI_AUD_HBR_STATUS 0x3401
++#define HDMI_AUD_HBR_INT 0x3402
++#define HDMI_AUD_HBR_POL 0x3403
++#define HDMI_AUD_HBR_MASK 0x3404
++
++/*
++ * Generic Parallel Audio Interface Registers
++ * Not used as GPAUD interface is not enabled in hw
++ */
++#define HDMI_GP_CONF0 0x3500
++#define HDMI_GP_CONF1 0x3501
++#define HDMI_GP_CONF2 0x3502
++#define HDMI_GP_STAT 0x3503
++#define HDMI_GP_INT 0x3504
++#define HDMI_GP_MASK 0x3505
++#define HDMI_GP_POL 0x3506
++
++/* Audio DMA Registers */
++#define HDMI_AHB_DMA_CONF0 0x3600
++#define HDMI_AHB_DMA_START 0x3601
++#define HDMI_AHB_DMA_STOP 0x3602
++#define HDMI_AHB_DMA_THRSLD 0x3603
++#define HDMI_AHB_DMA_STRADDR0 0x3604
++#define HDMI_AHB_DMA_STRADDR1 0x3605
++#define HDMI_AHB_DMA_STRADDR2 0x3606
++#define HDMI_AHB_DMA_STRADDR3 0x3607
++#define HDMI_AHB_DMA_STPADDR0 0x3608
++#define HDMI_AHB_DMA_STPADDR1 0x3609
++#define HDMI_AHB_DMA_STPADDR2 0x360a
++#define HDMI_AHB_DMA_STPADDR3 0x360b
++#define HDMI_AHB_DMA_BSTADDR0 0x360c
++#define HDMI_AHB_DMA_BSTADDR1 0x360d
++#define HDMI_AHB_DMA_BSTADDR2 0x360e
++#define HDMI_AHB_DMA_BSTADDR3 0x360f
++#define HDMI_AHB_DMA_MBLENGTH0 0x3610
++#define HDMI_AHB_DMA_MBLENGTH1 0x3611
++#define HDMI_AHB_DMA_STAT 0x3612
++#define HDMI_AHB_DMA_INT 0x3613
++#define HDMI_AHB_DMA_MASK 0x3614
++#define HDMI_AHB_DMA_POL 0x3615
++#define HDMI_AHB_DMA_CONF1 0x3616
++#define HDMI_AHB_DMA_BUFFSTAT 0x3617
++#define HDMI_AHB_DMA_BUFFINT 0x3618
++#define HDMI_AHB_DMA_BUFFMASK 0x3619
++#define HDMI_AHB_DMA_BUFFPOL 0x361a
++
++/* Main Controller Registers */
++#define HDMI_MC_SFRDIV 0x4000
++#define HDMI_MC_CLKDIS 0x4001
++#define HDMI_MC_SWRSTZ 0x4002
++#define HDMI_MC_OPCTRL 0x4003
++#define HDMI_MC_FLOWCTRL 0x4004
++#define HDMI_MC_PHYRSTZ 0x4005
++#define HDMI_MC_LOCKONCLOCK 0x4006
++#define HDMI_MC_HEACPHY_RST 0x4007
++
++/* Color Space Converter Registers */
++#define HDMI_CSC_CFG 0x4100
++#define HDMI_CSC_SCALE 0x4101
++#define HDMI_CSC_COEF_A1_MSB 0x4102
++#define HDMI_CSC_COEF_A1_LSB 0x4103
++#define HDMI_CSC_COEF_A2_MSB 0x4104
++#define HDMI_CSC_COEF_A2_LSB 0x4105
++#define HDMI_CSC_COEF_A3_MSB 0x4106
++#define HDMI_CSC_COEF_A3_LSB 0x4107
++#define HDMI_CSC_COEF_A4_MSB 0x4108
++#define HDMI_CSC_COEF_A4_LSB 0x4109
++#define HDMI_CSC_COEF_B1_MSB 0x410A
++#define HDMI_CSC_COEF_B1_LSB 0x410B
++#define HDMI_CSC_COEF_B2_MSB 0x410C
++#define HDMI_CSC_COEF_B2_LSB 0x410D
++#define HDMI_CSC_COEF_B3_MSB 0x410E
++#define HDMI_CSC_COEF_B3_LSB 0x410F
++#define HDMI_CSC_COEF_B4_MSB 0x4110
++#define HDMI_CSC_COEF_B4_LSB 0x4111
++#define HDMI_CSC_COEF_C1_MSB 0x4112
++#define HDMI_CSC_COEF_C1_LSB 0x4113
++#define HDMI_CSC_COEF_C2_MSB 0x4114
++#define HDMI_CSC_COEF_C2_LSB 0x4115
++#define HDMI_CSC_COEF_C3_MSB 0x4116
++#define HDMI_CSC_COEF_C3_LSB 0x4117
++#define HDMI_CSC_COEF_C4_MSB 0x4118
++#define HDMI_CSC_COEF_C4_LSB 0x4119
++
++/* HDCP Encryption Engine Registers */
++#define HDMI_A_HDCPCFG0 0x5000
++#define HDMI_A_HDCPCFG1 0x5001
++#define HDMI_A_HDCPOBS0 0x5002
++#define HDMI_A_HDCPOBS1 0x5003
++#define HDMI_A_HDCPOBS2 0x5004
++#define HDMI_A_HDCPOBS3 0x5005
++#define HDMI_A_APIINTCLR 0x5006
++#define HDMI_A_APIINTSTAT 0x5007
++#define HDMI_A_APIINTMSK 0x5008
++#define HDMI_A_VIDPOLCFG 0x5009
++#define HDMI_A_OESSWCFG 0x500A
++#define HDMI_A_TIMER1SETUP0 0x500B
++#define HDMI_A_TIMER1SETUP1 0x500C
++#define HDMI_A_TIMER2SETUP0 0x500D
++#define HDMI_A_TIMER2SETUP1 0x500E
++#define HDMI_A_100MSCFG 0x500F
++#define HDMI_A_2SCFG0 0x5010
++#define HDMI_A_2SCFG1 0x5011
++#define HDMI_A_5SCFG0 0x5012
++#define HDMI_A_5SCFG1 0x5013
++#define HDMI_A_SRMVERLSB 0x5014
++#define HDMI_A_SRMVERMSB 0x5015
++#define HDMI_A_SRMCTRL 0x5016
++#define HDMI_A_SFRSETUP 0x5017
++#define HDMI_A_I2CHSETUP 0x5018
++#define HDMI_A_INTSETUP 0x5019
++#define HDMI_A_PRESETUP 0x501A
++#define HDMI_A_SRM_BASE 0x5020
++
++/* CEC Engine Registers */
++#define HDMI_CEC_CTRL 0x7D00
++#define HDMI_CEC_STAT 0x7D01
++#define HDMI_CEC_MASK 0x7D02
++#define HDMI_CEC_POLARITY 0x7D03
++#define HDMI_CEC_INT 0x7D04
++#define HDMI_CEC_ADDR_L 0x7D05
++#define HDMI_CEC_ADDR_H 0x7D06
++#define HDMI_CEC_TX_CNT 0x7D07
++#define HDMI_CEC_RX_CNT 0x7D08
++#define HDMI_CEC_TX_DATA0 0x7D10
++#define HDMI_CEC_TX_DATA1 0x7D11
++#define HDMI_CEC_TX_DATA2 0x7D12
++#define HDMI_CEC_TX_DATA3 0x7D13
++#define HDMI_CEC_TX_DATA4 0x7D14
++#define HDMI_CEC_TX_DATA5 0x7D15
++#define HDMI_CEC_TX_DATA6 0x7D16
++#define HDMI_CEC_TX_DATA7 0x7D17
++#define HDMI_CEC_TX_DATA8 0x7D18
++#define HDMI_CEC_TX_DATA9 0x7D19
++#define HDMI_CEC_TX_DATA10 0x7D1a
++#define HDMI_CEC_TX_DATA11 0x7D1b
++#define HDMI_CEC_TX_DATA12 0x7D1c
++#define HDMI_CEC_TX_DATA13 0x7D1d
++#define HDMI_CEC_TX_DATA14 0x7D1e
++#define HDMI_CEC_TX_DATA15 0x7D1f
++#define HDMI_CEC_RX_DATA0 0x7D20
++#define HDMI_CEC_RX_DATA1 0x7D21
++#define HDMI_CEC_RX_DATA2 0x7D22
++#define HDMI_CEC_RX_DATA3 0x7D23
++#define HDMI_CEC_RX_DATA4 0x7D24
++#define HDMI_CEC_RX_DATA5 0x7D25
++#define HDMI_CEC_RX_DATA6 0x7D26
++#define HDMI_CEC_RX_DATA7 0x7D27
++#define HDMI_CEC_RX_DATA8 0x7D28
++#define HDMI_CEC_RX_DATA9 0x7D29
++#define HDMI_CEC_RX_DATA10 0x7D2a
++#define HDMI_CEC_RX_DATA11 0x7D2b
++#define HDMI_CEC_RX_DATA12 0x7D2c
++#define HDMI_CEC_RX_DATA13 0x7D2d
++#define HDMI_CEC_RX_DATA14 0x7D2e
++#define HDMI_CEC_RX_DATA15 0x7D2f
++#define HDMI_CEC_LOCK 0x7D30
++#define HDMI_CEC_WKUPCTRL 0x7D31
++
++/* I2C Master Registers (E-DDC) */
++#define HDMI_I2CM_SLAVE 0x7E00
++#define HDMI_I2CMESS 0x7E01
++#define HDMI_I2CM_DATAO 0x7E02
++#define HDMI_I2CM_DATAI 0x7E03
++#define HDMI_I2CM_OPERATION 0x7E04
++#define HDMI_I2CM_INT 0x7E05
++#define HDMI_I2CM_CTLINT 0x7E06
++#define HDMI_I2CM_DIV 0x7E07
++#define HDMI_I2CM_SEGADDR 0x7E08
++#define HDMI_I2CM_SOFTRSTZ 0x7E09
++#define HDMI_I2CM_SEGPTR 0x7E0A
++#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
++#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
++#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
++#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
++#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
++#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
++#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
++#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
++
++enum {
++/* IH_FC_INT2 field values */
++ HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_FC_STAT2 field values */
++ HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_PHY_STAT0 field values */
++ HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
++ HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
++ HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
++ HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
++ HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
++ HDMI_IH_PHY_STAT0_HPD = 0x1,
++
++/* IH_MUTE_I2CMPHY_STAT0 field values */
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
++
++/* IH_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE_FC_STAT2 field values */
++ HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_MUTE_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE field values */
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
++
++/* TX_INVID0 field values */
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
++ HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
++
++/* TX_INSTUFFING field values */
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
++
++/* VP_PR_CD field values */
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
++ HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
++
++/* VP_STUFF field values */
++ HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
++ HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
++
++/* VP_CONF field values */
++ HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
++ HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
++ HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PR_EN_MASK = 0x10,
++ HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
++ HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
++ HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
++ HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
++ HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
++
++/* VP_REMAP field values */
++ HDMI_VP_REMAP_MASK = 0x3,
++ HDMI_VP_REMAP_YCC422_24bit = 0x2,
++ HDMI_VP_REMAP_YCC422_20bit = 0x1,
++ HDMI_VP_REMAP_YCC422_16bit = 0x0,
++
++/* FC_INVIDCONF field values */
++ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
++ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
++ HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
++ HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
++
++/* FC_AUDICONF0 field values */
++ HDMI_FC_AUDICONF0_CC_OFFSET = 4,
++ HDMI_FC_AUDICONF0_CC_MASK = 0x70,
++ HDMI_FC_AUDICONF0_CT_OFFSET = 0,
++ HDMI_FC_AUDICONF0_CT_MASK = 0xF,
++
++/* FC_AUDICONF1 field values */
++ HDMI_FC_AUDICONF1_SS_OFFSET = 3,
++ HDMI_FC_AUDICONF1_SS_MASK = 0x18,
++ HDMI_FC_AUDICONF1_SF_OFFSET = 0,
++ HDMI_FC_AUDICONF1_SF_MASK = 0x7,
++
++/* FC_AUDICONF3 field values */
++ HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
++ HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
++ HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
++ HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
++ HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
++ HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
++
++/* FC_AUDSCHNLS0 field values */
++ HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
++
++/* FC_AUDSCHNLS3-6 field values */
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
++
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
++
++/* HDMI_FC_AUDSCHNLS7 field values */
++ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
++
++/* HDMI_FC_AUDSCHNLS8 field values */
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
++
++/* FC_AUDSCONF field values */
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
++
++/* FC_STAT2 field values */
++ HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_INT2 field values */
++ HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_MASK2 field values */
++ HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_PRCONF field values */
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
++
++/* FC_AVICONF0-FC_AVICONF3 field values */
++ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
++ HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
++ HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
++ HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
++ HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
++ HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
++ HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
++
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
++ HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
++ HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
++ HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
++ HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
++
++ HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
++ HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
++ HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
++ HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
++ HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
++ HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
++ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
++ HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
++ HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
++ HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
++ HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
++ HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
++
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
++ HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
++ HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
++
++/* FC_DBGFORCE field values */
++ HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
++ HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
++
++/* PHY_CONF0 field values */
++ HDMI_PHY_CONF0_PDZ_MASK = 0x80,
++ HDMI_PHY_CONF0_PDZ_OFFSET = 7,
++ HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
++ HDMI_PHY_CONF0_SPARECTRL = 0x20,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
++ HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
++
++/* PHY_TST0 field values */
++ HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
++ HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
++ HDMI_PHY_TST0_TSTEN_MASK = 0x10,
++ HDMI_PHY_TST0_TSTEN_OFFSET = 4,
++ HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
++ HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
++
++/* PHY_STAT0 field values */
++ HDMI_PHY_RX_SENSE3 = 0x80,
++ HDMI_PHY_RX_SENSE2 = 0x40,
++ HDMI_PHY_RX_SENSE1 = 0x20,
++ HDMI_PHY_RX_SENSE0 = 0x10,
++ HDMI_PHY_HPD = 0x02,
++ HDMI_PHY_TX_PHY_LOCK = 0x01,
++
++/* PHY_I2CM_SLAVE_ADDR field values */
++ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
++ HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
++
++/* PHY_I2CM_OPERATION_ADDR field values */
++ HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
++ HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
++
++/* HDMI_PHY_I2CM_INT_ADDR */
++ HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
++ HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
++
++/* HDMI_PHY_I2CM_CTLINT_ADDR */
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
++
++/* AUD_CTS3 field values */
++ HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
++ HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
++ HDMI_AUD_CTS3_N_SHIFT_1 = 0,
++ HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
++ HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
++ HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
++ HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
++ HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
++ /* note that the CTS3 MANUAL bit has been removed
++ from our part. Can't set it, will read as 0. */
++ HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
++ HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
++
++/* AHB_DMA_CONF0 field values */
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
++ HDMI_AHB_DMA_CONF0_HBR = 0x10,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
++ HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
++ HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
++ HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
++ HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
++
++/* HDMI_AHB_DMA_START field values */
++ HDMI_AHB_DMA_START_START_OFFSET = 0,
++ HDMI_AHB_DMA_START_START_MASK = 0x01,
++
++/* HDMI_AHB_DMA_STOP field values */
++ HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
++ HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
++
++/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
++ HDMI_AHB_DMA_DONE = 0x80,
++ HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
++ HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
++ HDMI_AHB_DMA_ERROR = 0x10,
++ HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
++ HDMI_AHB_DMA_FIFO_FULL = 0x02,
++ HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
++
++/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT,AHB_DMA_BUFFMASK,AHB_DMA_BUFFPOL values */
++ HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
++ HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
++
++/* MC_CLKDIS field values */
++ HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
++ HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
++ HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
++ HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
++ HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
++ HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
++ HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
++
++/* MC_SWRSTZ field values */
++ HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
++
++/* MC_FLOWCTRL field values */
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
++
++/* MC_PHYRSTZ field values */
++ HDMI_MC_PHYRSTZ_ASSERT = 0x0,
++ HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
++
++/* MC_HEACPHY_RST field values */
++ HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
++ HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
++
++/* CSC_CFG field values */
++ HDMI_CSC_CFG_INTMODE_MASK = 0x30,
++ HDMI_CSC_CFG_INTMODE_OFFSET = 4,
++ HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
++ HDMI_CSC_CFG_DECMODE_MASK = 0x3,
++ HDMI_CSC_CFG_DECMODE_OFFSET = 0,
++ HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
++
++/* CSC_SCALE field values */
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
++ HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
++
++/* A_HDCPCFG0 field values */
++ HDMI_A_HDCPCFG0_ELVENA_MASK = 0x80,
++ HDMI_A_HDCPCFG0_ELVENA_ENABLE = 0x80,
++ HDMI_A_HDCPCFG0_ELVENA_DISABLE = 0x00,
++ HDMI_A_HDCPCFG0_I2CFASTMODE_MASK = 0x40,
++ HDMI_A_HDCPCFG0_I2CFASTMODE_ENABLE = 0x40,
++ HDMI_A_HDCPCFG0_I2CFASTMODE_DISABLE = 0x00,
++ HDMI_A_HDCPCFG0_BYPENCRYPTION_MASK = 0x20,
++ HDMI_A_HDCPCFG0_BYPENCRYPTION_ENABLE = 0x20,
++ HDMI_A_HDCPCFG0_BYPENCRYPTION_DISABLE = 0x00,
++ HDMI_A_HDCPCFG0_SYNCRICHECK_MASK = 0x10,
++ HDMI_A_HDCPCFG0_SYNCRICHECK_ENABLE = 0x10,
++ HDMI_A_HDCPCFG0_SYNCRICHECK_DISABLE = 0x00,
++ HDMI_A_HDCPCFG0_AVMUTE_MASK = 0x8,
++ HDMI_A_HDCPCFG0_AVMUTE_ENABLE = 0x8,
++ HDMI_A_HDCPCFG0_AVMUTE_DISABLE = 0x0,
++ HDMI_A_HDCPCFG0_RXDETECT_MASK = 0x4,
++ HDMI_A_HDCPCFG0_RXDETECT_ENABLE = 0x4,
++ HDMI_A_HDCPCFG0_RXDETECT_DISABLE = 0x0,
++ HDMI_A_HDCPCFG0_EN11FEATURE_MASK = 0x2,
++ HDMI_A_HDCPCFG0_EN11FEATURE_ENABLE = 0x2,
++ HDMI_A_HDCPCFG0_EN11FEATURE_DISABLE = 0x0,
++ HDMI_A_HDCPCFG0_HDMIDVI_MASK = 0x1,
++ HDMI_A_HDCPCFG0_HDMIDVI_HDMI = 0x1,
++ HDMI_A_HDCPCFG0_HDMIDVI_DVI = 0x0,
++
++/* A_HDCPCFG1 field values */
++ HDMI_A_HDCPCFG1_DISSHA1CHECK_MASK = 0x8,
++ HDMI_A_HDCPCFG1_DISSHA1CHECK_DISABLE = 0x8,
++ HDMI_A_HDCPCFG1_DISSHA1CHECK_ENABLE = 0x0,
++ HDMI_A_HDCPCFG1_PH2UPSHFTENC_MASK = 0x4,
++ HDMI_A_HDCPCFG1_PH2UPSHFTENC_ENABLE = 0x4,
++ HDMI_A_HDCPCFG1_PH2UPSHFTENC_DISABLE = 0x0,
++ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK = 0x2,
++ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE = 0x2,
++ HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE = 0x0,
++ HDMI_A_HDCPCFG1_SWRESET_MASK = 0x1,
++ HDMI_A_HDCPCFG1_SWRESET_ASSERT = 0x0,
++
++/* A_VIDPOLCFG field values */
++ HDMI_A_VIDPOLCFG_UNENCRYPTCONF_MASK = 0x60,
++ HDMI_A_VIDPOLCFG_UNENCRYPTCONF_OFFSET = 5,
++ HDMI_A_VIDPOLCFG_DATAENPOL_MASK = 0x10,
++ HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH = 0x10,
++ HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW = 0x0,
++ HDMI_A_VIDPOLCFG_VSYNCPOL_MASK = 0x8,
++ HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH = 0x8,
++ HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW = 0x0,
++ HDMI_A_VIDPOLCFG_HSYNCPOL_MASK = 0x2,
++ HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH = 0x2,
++ HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
++};
++
++struct imx_hdmi;
++void imx_hdmi_set_sample_rate(struct imx_hdmi *hdmi, unsigned int rate);
++uint8_t *imx_hdmi_get_eld(struct imx_hdmi *hdmi);
++
++void hdmi_enable_cec(struct imx_hdmi *hdmi);
++void hdmi_disable_cec(struct imx_hdmi *hdmi);
++
++#endif /* __IMX_HDMI_H__ */
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/imx-ldb.c linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-ldb.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/imx-ldb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-ldb.c 2014-05-15 20:34:05.754069749 +0200
+@@ -0,0 +1,606 @@
++/*
++ * i.MX drm driver - LVDS display bridge
++ *
++ * Copyright (C) 2012 Sascha Hauer, Pengutronix
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ * MA 02110-1301, USA.
++ */
++
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/component.h>
++#include <drm/drmP.h>
++#include <drm/drm_fb_helper.h>
++#include <drm/drm_crtc_helper.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <video/of_videomode.h>
++#include <linux/regmap.h>
++#include <linux/videodev2.h>
++
++#include "imx-drm.h"
++
++#define DRIVER_NAME "imx-ldb"
++
++#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
++#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
++#define LDB_CH0_MODE_EN_MASK (3 << 0)
++#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
++#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
++#define LDB_CH1_MODE_EN_MASK (3 << 2)
++#define LDB_SPLIT_MODE_EN (1 << 4)
++#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
++#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
++#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
++#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
++#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
++#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
++#define LDB_BGREF_RMODE_INT (1 << 15)
++
++#define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
++#define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
++
++struct imx_ldb;
++
++struct imx_ldb_channel {
++ struct imx_ldb *ldb;
++ struct drm_connector connector;
++ struct drm_encoder encoder;
++ struct device_node *child;
++ int chno;
++ void *edid;
++ int edid_len;
++ struct drm_display_mode mode;
++ int mode_valid;
++};
++
++struct bus_mux {
++ int reg;
++ int shift;
++ int mask;
++};
++
++struct imx_ldb {
++ struct regmap *regmap;
++ struct device *dev;
++ struct imx_ldb_channel channel[2];
++ struct clk *clk[2]; /* our own clock */
++ struct clk *clk_sel[4]; /* parent of display clock */
++ struct clk *clk_pll[2]; /* upstream clock we can adjust */
++ u32 ldb_ctrl;
++ const struct bus_mux *lvds_mux;
++};
++
++static enum drm_connector_status imx_ldb_connector_detect(
++ struct drm_connector *connector, bool force)
++{
++ return connector_status_connected;
++}
++
++static int imx_ldb_connector_get_modes(struct drm_connector *connector)
++{
++ struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
++ int num_modes = 0;
++
++ if (imx_ldb_ch->edid) {
++ drm_mode_connector_update_edid_property(connector,
++ imx_ldb_ch->edid);
++ num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
++ }
++
++ if (imx_ldb_ch->mode_valid) {
++ struct drm_display_mode *mode;
++
++ mode = drm_mode_create(connector->dev);
++ drm_mode_copy(mode, &imx_ldb_ch->mode);
++ mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
++ drm_mode_probed_add(connector, mode);
++ num_modes++;
++ }
++
++ return num_modes;
++}
++
++static struct drm_encoder *imx_ldb_connector_best_encoder(
++ struct drm_connector *connector)
++{
++ struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
++
++ return &imx_ldb_ch->encoder;
++}
++
++static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
++{
++}
++
++static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
++ const struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
++{
++ return true;
++}
++
++static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
++ unsigned long serial_clk, unsigned long di_clk)
++{
++ int ret;
++
++ dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
++ clk_get_rate(ldb->clk_pll[chno]), serial_clk);
++ clk_set_rate(ldb->clk_pll[chno], serial_clk);
++
++ dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
++ clk_get_rate(ldb->clk_pll[chno]));
++
++ dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
++ clk_get_rate(ldb->clk[chno]),
++ (long int)di_clk);
++ clk_set_rate(ldb->clk[chno], di_clk);
++
++ dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
++ clk_get_rate(ldb->clk[chno]));
++
++ /* set display clock mux to LDB input clock */
++ ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
++ if (ret) {
++ dev_err(ldb->dev, "unable to set di%d parent clock to ldb_di%d\n", mux, chno);
++ }
++}
++
++static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
++{
++ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
++ struct imx_ldb *ldb = imx_ldb_ch->ldb;
++ struct drm_display_mode *mode = &encoder->crtc->mode;
++ u32 pixel_fmt;
++ unsigned long serial_clk;
++ unsigned long di_clk = mode->clock * 1000;
++ int mux = imx_drm_encoder_get_mux_id(encoder);
++
++ if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
++ /* dual channel LVDS mode */
++ serial_clk = 3500UL * mode->clock;
++ imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
++ imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
++ } else {
++ serial_clk = 7000UL * mode->clock;
++ imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, di_clk);
++ }
++
++ switch (imx_ldb_ch->chno) {
++ case 0:
++ pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ?
++ V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
++ break;
++ case 1:
++ pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ?
++ V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666;
++ break;
++ default:
++ dev_err(ldb->dev, "unable to config di%d panel format\n",
++ imx_ldb_ch->chno);
++ pixel_fmt = V4L2_PIX_FMT_RGB24;
++ }
++
++ imx_drm_panel_format(encoder, pixel_fmt);
++}
++
++static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
++{
++ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
++ struct imx_ldb *ldb = imx_ldb_ch->ldb;
++ int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
++ int mux = imx_drm_encoder_get_mux_id(encoder);
++
++ if (dual) {
++ clk_prepare_enable(ldb->clk[0]);
++ clk_prepare_enable(ldb->clk[1]);
++ }
++
++ if (imx_ldb_ch == &ldb->channel[0] || dual) {
++ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
++ if (mux == 0 || ldb->lvds_mux)
++ ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
++ else if (mux == 1)
++ ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
++ }
++ if (imx_ldb_ch == &ldb->channel[1] || dual) {
++ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
++ if (mux == 1 || ldb->lvds_mux)
++ ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
++ else if (mux == 0)
++ ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
++ }
++
++ if (ldb->lvds_mux) {
++ const struct bus_mux *lvds_mux = NULL;
++
++ if (imx_ldb_ch == &ldb->channel[0])
++ lvds_mux = &ldb->lvds_mux[0];
++ else if (imx_ldb_ch == &ldb->channel[1])
++ lvds_mux = &ldb->lvds_mux[1];
++
++ regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
++ mux << lvds_mux->shift);
++ }
++
++ regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
++}
++
++static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
++ struct drm_display_mode *mode,
++ struct drm_display_mode *adjusted_mode)
++{
++ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
++ struct imx_ldb *ldb = imx_ldb_ch->ldb;
++ int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
++
++ if (mode->clock > 170000) {
++ dev_warn(ldb->dev,
++ "%s: mode exceeds 170 MHz pixel clock\n", __func__);
++ }
++ if (mode->clock > 85000 && !dual) {
++ dev_warn(ldb->dev,
++ "%s: mode exceeds 85 MHz pixel clock\n", __func__);
++ }
++
++ /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
++ if (imx_ldb_ch == &ldb->channel[0]) {
++ if (mode->flags & DRM_MODE_FLAG_NVSYNC)
++ ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
++ else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
++ ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
++ }
++ if (imx_ldb_ch == &ldb->channel[1]) {
++ if (mode->flags & DRM_MODE_FLAG_NVSYNC)
++ ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
++ else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
++ ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
++ }
++}
++
++static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
++{
++ struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
++ struct imx_ldb *ldb = imx_ldb_ch->ldb;
++
++ /*
++ * imx_ldb_encoder_disable is called by
++ * drm_helper_disable_unused_functions without
++ * the encoder being enabled before.
++ */
++ if (imx_ldb_ch == &ldb->channel[0] &&
++ (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
++ return;
++ else if (imx_ldb_ch == &ldb->channel[1] &&
++ (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
++ return;
++
++ if (imx_ldb_ch == &ldb->channel[0])
++ ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
++ else if (imx_ldb_ch == &ldb->channel[1])
++ ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
++
++ regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
++
++ if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
++ clk_disable_unprepare(ldb->clk[0]);
++ clk_disable_unprepare(ldb->clk[1]);
++ }
++}
++
++static struct drm_connector_funcs imx_ldb_connector_funcs = {
++ .dpms = drm_helper_connector_dpms,
++ .fill_modes = drm_helper_probe_single_connector_modes,
++ .detect = imx_ldb_connector_detect,
++ .destroy = imx_drm_connector_destroy,
++};
++
++static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
++ .get_modes = imx_ldb_connector_get_modes,
++ .best_encoder = imx_ldb_connector_best_encoder,
++ .mode_valid = imx_drm_connector_mode_valid,
++};
++
++static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
++ .destroy = imx_drm_encoder_destroy,
++};
++
++static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
++ .dpms = imx_ldb_encoder_dpms,
++ .mode_fixup = imx_ldb_encoder_mode_fixup,
++ .prepare = imx_ldb_encoder_prepare,
++ .commit = imx_ldb_encoder_commit,
++ .mode_set = imx_ldb_encoder_mode_set,
++ .disable = imx_ldb_encoder_disable,
++};
++
++static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
++{
++ char clkname[16];
++
++ sprintf(clkname, "di%d", chno);
++ ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
++ if (IS_ERR(ldb->clk[chno]))
++ return PTR_ERR(ldb->clk[chno]);
++
++ sprintf(clkname, "di%d_pll", chno);
++ ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
++
++ return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
++}
++
++static int imx_ldb_register(struct drm_device *drm,
++ struct imx_ldb_channel *imx_ldb_ch)
++{
++ struct imx_ldb *ldb = imx_ldb_ch->ldb;
++ int ret;
++
++ ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
++ imx_ldb_ch->child);
++ if (ret)
++ return ret;
++
++ ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
++ if (ret)
++ return ret;
++
++ if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
++ ret = imx_ldb_get_clk(ldb, 1);
++ if (ret)
++ return ret;
++ }
++
++ drm_encoder_helper_add(&imx_ldb_ch->encoder,
++ &imx_ldb_encoder_helper_funcs);
++ drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
++ DRM_MODE_ENCODER_LVDS);
++
++ drm_connector_helper_add(&imx_ldb_ch->connector,
++ &imx_ldb_connector_helper_funcs);
++ drm_connector_init(drm, &imx_ldb_ch->connector,
++ &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
++
++ drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
++ &imx_ldb_ch->encoder);
++
++ return 0;
++}
++
++enum {
++ LVDS_BIT_MAP_SPWG,
++ LVDS_BIT_MAP_JEIDA
++};
++
++static const char *imx_ldb_bit_mappings[] = {
++ [LVDS_BIT_MAP_SPWG] = "spwg",
++ [LVDS_BIT_MAP_JEIDA] = "jeida",
++};
++
++static const int of_get_data_mapping(struct device_node *np)
++{
++ const char *bm;
++ int ret, i;
++
++ ret = of_property_read_string(np, "fsl,data-mapping", &bm);
++ if (ret < 0)
++ return ret;
++
++ for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++)
++ if (!strcasecmp(bm, imx_ldb_bit_mappings[i]))
++ return i;
++
++ return -EINVAL;
++}
++
++static struct bus_mux imx6q_lvds_mux[2] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .shift = 6,
++ .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
++ }, {
++ .reg = IOMUXC_GPR3,
++ .shift = 8,
++ .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
++ }
++};
++
++/*
++ * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
++ * of_match_device will walk through this list and take the first entry
++ * matching any of its compatible values. Therefore, the more generic
++ * entries (in this case fsl,imx53-ldb) need to be ordered last.
++ */
++static const struct of_device_id imx_ldb_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
++ { .compatible = "fsl,imx53-ldb", .data = NULL, },
++ { }
++};
++MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
++
++static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
++{
++ struct drm_device *drm = data;
++ struct device_node *np = dev->of_node;
++ const struct of_device_id *of_id =
++ of_match_device(imx_ldb_dt_ids, dev);
++ struct device_node *child;
++ const u8 *edidp;
++ struct imx_ldb *imx_ldb;
++ int datawidth;
++ int mapping;
++ int dual;
++ int ret;
++ int i;
++
++ imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
++ if (!imx_ldb)
++ return -ENOMEM;
++
++ imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
++ if (IS_ERR(imx_ldb->regmap)) {
++ dev_err(dev, "failed to get parent regmap\n");
++ return PTR_ERR(imx_ldb->regmap);
++ }
++
++ imx_ldb->dev = dev;
++
++ if (of_id)
++ imx_ldb->lvds_mux = of_id->data;
++
++ dual = of_property_read_bool(np, "fsl,dual-channel");
++ if (dual)
++ imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
++
++ /*
++ * There are three different possible clock mux configurations:
++ * i.MX53: ipu1_di0_sel, ipu1_di1_sel
++ * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
++ * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
++ * Map them all to di0_sel...di3_sel.
++ */
++ for (i = 0; i < 4; i++) {
++ char clkname[16];
++
++ sprintf(clkname, "di%d_sel", i);
++ imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
++ if (IS_ERR(imx_ldb->clk_sel[i])) {
++ ret = PTR_ERR(imx_ldb->clk_sel[i]);
++ imx_ldb->clk_sel[i] = NULL;
++ break;
++ }
++ }
++ if (i == 0)
++ return ret;
++
++ for_each_child_of_node(np, child) {
++ struct imx_ldb_channel *channel;
++
++ ret = of_property_read_u32(child, "reg", &i);
++ if (ret || i < 0 || i > 1)
++ return -EINVAL;
++
++ if (dual && i > 0) {
++ dev_warn(dev, "dual-channel mode, ignoring second output\n");
++ continue;
++ }
++
++ if (!of_device_is_available(child))
++ continue;
++
++ channel = &imx_ldb->channel[i];
++ channel->ldb = imx_ldb;
++ channel->chno = i;
++ channel->child = child;
++
++ edidp = of_get_property(child, "edid", &channel->edid_len);
++ if (edidp) {
++ channel->edid = kmemdup(edidp, channel->edid_len,
++ GFP_KERNEL);
++ } else {
++ ret = of_get_drm_display_mode(child, &channel->mode, 0);
++ if (!ret)
++ channel->mode_valid = 1;
++ }
++
++ ret = of_property_read_u32(child, "fsl,data-width", &datawidth);
++ if (ret)
++ datawidth = 0;
++ else if (datawidth != 18 && datawidth != 24)
++ return -EINVAL;
++
++ mapping = of_get_data_mapping(child);
++ switch (mapping) {
++ case LVDS_BIT_MAP_SPWG:
++ if (datawidth == 24) {
++ if (i == 0 || dual)
++ imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
++ if (i == 1 || dual)
++ imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
++ }
++ break;
++ case LVDS_BIT_MAP_JEIDA:
++ if (datawidth == 18) {
++ dev_err(dev, "JEIDA standard only supported in 24 bit\n");
++ return -EINVAL;
++ }
++ if (i == 0 || dual)
++ imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | LDB_BIT_MAP_CH0_JEIDA;
++ if (i == 1 || dual)
++ imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | LDB_BIT_MAP_CH1_JEIDA;
++ break;
++ default:
++ dev_err(dev, "data mapping not specified or invalid\n");
++ return -EINVAL;
++ }
++
++ ret = imx_ldb_register(drm, channel);
++ if (ret)
++ return ret;
++ }
++
++ dev_set_drvdata(dev, imx_ldb);
++
++ return 0;
++}
++
++static void imx_ldb_unbind(struct device *dev, struct device *master,
++ void *data)
++{
++ struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
++ int i;
++
++ for (i = 0; i < 2; i++) {
++ struct imx_ldb_channel *channel = &imx_ldb->channel[i];
++
++ channel->connector.funcs->destroy(&channel->connector);
++ channel->encoder.funcs->destroy(&channel->encoder);
++ }
++}
++
++static const struct component_ops imx_ldb_ops = {
++ .bind = imx_ldb_bind,
++ .unbind = imx_ldb_unbind,
++};
++
++static int imx_ldb_probe(struct platform_device *pdev)
++{
++ return component_add(&pdev->dev, &imx_ldb_ops);
++}
++
++static int imx_ldb_remove(struct platform_device *pdev)
++{
++ component_del(&pdev->dev, &imx_ldb_ops);
++ return 0;
++}
++
++static struct platform_driver imx_ldb_driver = {
++ .probe = imx_ldb_probe,
++ .remove = imx_ldb_remove,
++ .driver = {
++ .of_match_table = imx_ldb_dt_ids,
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ },
++};
++
++module_platform_driver(imx_ldb_driver);
++
++MODULE_DESCRIPTION("i.MX LVDS driver");
++MODULE_AUTHOR("Sascha Hauer, Pengutronix");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRIVER_NAME);
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/imx-tve.c linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-tve.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/imx-tve.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/imx-tve.c 2014-05-15 20:34:05.754069749 +0200
+@@ -20,9 +20,9 @@
+
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
++#include <linux/component.h>
+ #include <linux/module.h>
+-#include <linux/of_i2c.h>
+-#include <linux/pinctrl/consumer.h>
++#include <linux/i2c.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/spinlock.h>
+@@ -111,11 +111,8 @@
+
+ struct imx_tve {
+ struct drm_connector connector;
+- struct imx_drm_connector *imx_drm_connector;
+ struct drm_encoder encoder;
+- struct imx_drm_encoder *imx_drm_encoder;
+ struct device *dev;
+- spinlock_t enable_lock; /* serializes tve_enable/disable */
+ spinlock_t lock; /* register lock */
+ bool enabled;
+ int mode;
+@@ -132,12 +129,14 @@
+ };
+
+ static void tve_lock(void *__tve)
++__acquires(&tve->lock)
+ {
+ struct imx_tve *tve = __tve;
+ spin_lock(&tve->lock);
+ }
+
+ static void tve_unlock(void *__tve)
++__releases(&tve->lock)
+ {
+ struct imx_tve *tve = __tve;
+ spin_unlock(&tve->lock);
+@@ -145,12 +144,10 @@
+
+ static void tve_enable(struct imx_tve *tve)
+ {
+- unsigned long flags;
+ int ret;
+
+- spin_lock_irqsave(&tve->enable_lock, flags);
+ if (!tve->enabled) {
+- tve->enabled = 1;
++ tve->enabled = true;
+ clk_prepare_enable(tve->clk);
+ ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
+ TVE_IPU_CLK_EN | TVE_EN,
+@@ -165,23 +162,21 @@
+ regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
+ else
+ regmap_write(tve->regmap, TVE_INT_CONT_REG,
+- TVE_CD_SM_IEN | TVE_CD_LM_IEN | TVE_CD_MON_END_IEN);
+- spin_unlock_irqrestore(&tve->enable_lock, flags);
++ TVE_CD_SM_IEN |
++ TVE_CD_LM_IEN |
++ TVE_CD_MON_END_IEN);
+ }
+
+ static void tve_disable(struct imx_tve *tve)
+ {
+- unsigned long flags;
+ int ret;
+
+- spin_lock_irqsave(&tve->enable_lock, flags);
+ if (tve->enabled) {
+- tve->enabled = 0;
++ tve->enabled = false;
+ ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
+ TVE_IPU_CLK_EN | TVE_EN, 0);
+ clk_disable_unprepare(tve->clk);
+ }
+- spin_unlock_irqrestore(&tve->enable_lock, flags);
+ }
+
+ static int tve_setup_tvout(struct imx_tve *tve)
+@@ -229,11 +224,6 @@
+ return connector_status_connected;
+ }
+
+-static void imx_tve_connector_destroy(struct drm_connector *connector)
+-{
+- /* do not free here */
+-}
+-
+ static int imx_tve_connector_get_modes(struct drm_connector *connector)
+ {
+ struct imx_tve *tve = con_to_tve(connector);
+@@ -258,6 +248,11 @@
+ {
+ struct imx_tve *tve = con_to_tve(connector);
+ unsigned long rate;
++ int ret;
++
++ ret = imx_drm_connector_mode_valid(connector, mode);
++ if (ret != MODE_OK)
++ return ret;
+
+ /* pixel clock with 2x oversampling */
+ rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
+@@ -309,13 +304,11 @@
+
+ switch (tve->mode) {
+ case TVE_MODE_VGA:
+- imx_drm_crtc_panel_format_pins(encoder->crtc,
+- DRM_MODE_ENCODER_DAC, IPU_PIX_FMT_GBR24,
++ imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
+ tve->hsync_pin, tve->vsync_pin);
+ break;
+ case TVE_MODE_TVOUT:
+- imx_drm_crtc_panel_format(encoder->crtc, DRM_MODE_ENCODER_TVDAC,
+- V4L2_PIX_FMT_YUV444);
++ imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
+ break;
+ }
+ }
+@@ -368,16 +361,11 @@
+ tve_disable(tve);
+ }
+
+-static void imx_tve_encoder_destroy(struct drm_encoder *encoder)
+-{
+- /* do not free here */
+-}
+-
+ static struct drm_connector_funcs imx_tve_connector_funcs = {
+ .dpms = drm_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = imx_tve_connector_detect,
+- .destroy = imx_tve_connector_destroy,
++ .destroy = imx_drm_connector_destroy,
+ };
+
+ static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
+@@ -387,7 +375,7 @@
+ };
+
+ static struct drm_encoder_funcs imx_tve_encoder_funcs = {
+- .destroy = imx_tve_encoder_destroy,
++ .destroy = imx_drm_encoder_destroy,
+ };
+
+ static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
+@@ -466,7 +454,9 @@
+ else
+ val = TVE_DAC_FULL_RATE;
+
+- ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_DAC_SAMP_RATE_MASK, val);
++ ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
++ TVE_DAC_SAMP_RATE_MASK, val);
++
+ if (ret < 0) {
+ dev_err(tve->dev, "failed to set divider: %d\n", ret);
+ return ret;
+@@ -505,34 +495,27 @@
+ return 0;
+ }
+
+-static int imx_tve_register(struct imx_tve *tve)
++static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
+ {
++ int encoder_type;
+ int ret;
+
+- tve->connector.funcs = &imx_tve_connector_funcs;
+- tve->encoder.funcs = &imx_tve_encoder_funcs;
++ encoder_type = tve->mode == TVE_MODE_VGA ?
++ DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
+
+- tve->encoder.encoder_type = DRM_MODE_ENCODER_NONE;
+- tve->connector.connector_type = DRM_MODE_CONNECTOR_VGA;
++ ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
++ tve->dev->of_node);
++ if (ret)
++ return ret;
+
+ drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
+- ret = imx_drm_add_encoder(&tve->encoder, &tve->imx_drm_encoder,
+- THIS_MODULE);
+- if (ret) {
+- dev_err(tve->dev, "adding encoder failed with %d\n", ret);
+- return ret;
+- }
++ drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
++ encoder_type);
+
+ drm_connector_helper_add(&tve->connector,
+ &imx_tve_connector_helper_funcs);
+-
+- ret = imx_drm_add_connector(&tve->connector,
+- &tve->imx_drm_connector, THIS_MODULE);
+- if (ret) {
+- imx_drm_remove_encoder(tve->imx_drm_encoder);
+- dev_err(tve->dev, "adding connector failed with %d\n", ret);
+- return ret;
+- }
++ drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
++ DRM_MODE_CONNECTOR_VGA);
+
+ drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
+
+@@ -578,9 +561,11 @@
+ return -EINVAL;
+ }
+
+-static int imx_tve_probe(struct platform_device *pdev)
++static int imx_tve_bind(struct device *dev, struct device *master, void *data)
+ {
+- struct device_node *np = pdev->dev.of_node;
++ struct platform_device *pdev = to_platform_device(dev);
++ struct drm_device *drm = data;
++ struct device_node *np = dev->of_node;
+ struct device_node *ddc_node;
+ struct imx_tve *tve;
+ struct resource *res;
+@@ -589,13 +574,12 @@
+ int irq;
+ int ret;
+
+- tve = devm_kzalloc(&pdev->dev, sizeof(*tve), GFP_KERNEL);
++ tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
+ if (!tve)
+ return -ENOMEM;
+
+- tve->dev = &pdev->dev;
++ tve->dev = dev;
+ spin_lock_init(&tve->lock);
+- spin_lock_init(&tve->enable_lock);
+
+ ddc_node = of_parse_phandle(np, "ddc", 0);
+ if (ddc_node) {
+@@ -605,69 +589,57 @@
+
+ tve->mode = of_get_tve_mode(np);
+ if (tve->mode != TVE_MODE_VGA) {
+- dev_err(&pdev->dev, "only VGA mode supported, currently\n");
++ dev_err(dev, "only VGA mode supported, currently\n");
+ return -EINVAL;
+ }
+
+ if (tve->mode == TVE_MODE_VGA) {
+- struct pinctrl *pinctrl;
+-
+- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+- if (IS_ERR(pinctrl)) {
+- ret = PTR_ERR(pinctrl);
+- dev_warn(&pdev->dev, "failed to setup pinctrl: %d", ret);
+- return ret;
+- }
++ ret = of_property_read_u32(np, "fsl,hsync-pin",
++ &tve->hsync_pin);
+
+- ret = of_property_read_u32(np, "fsl,hsync-pin", &tve->hsync_pin);
+ if (ret < 0) {
+- dev_err(&pdev->dev, "failed to get vsync pin\n");
++ dev_err(dev, "failed to get vsync pin\n");
+ return ret;
+ }
+
+- ret |= of_property_read_u32(np, "fsl,vsync-pin", &tve->vsync_pin);
++ ret |= of_property_read_u32(np, "fsl,vsync-pin",
++ &tve->vsync_pin);
++
+ if (ret < 0) {
+- dev_err(&pdev->dev, "failed to get vsync pin\n");
++ dev_err(dev, "failed to get vsync pin\n");
+ return ret;
+ }
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!res) {
+- dev_err(&pdev->dev, "failed to get memory region\n");
+- return -ENOENT;
+- }
+-
+- base = devm_request_and_ioremap(&pdev->dev, res);
+- if (!base) {
+- dev_err(&pdev->dev, "failed to remap memory region\n");
+- return -ENOENT;
+- }
++ base = devm_ioremap_resource(dev, res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
+
+ tve_regmap_config.lock_arg = tve;
+- tve->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "tve", base,
++ tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
+ &tve_regmap_config);
+ if (IS_ERR(tve->regmap)) {
+- dev_err(&pdev->dev, "failed to init regmap: %ld\n",
++ dev_err(dev, "failed to init regmap: %ld\n",
+ PTR_ERR(tve->regmap));
+ return PTR_ERR(tve->regmap);
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+- dev_err(&pdev->dev, "failed to get irq\n");
++ dev_err(dev, "failed to get irq\n");
+ return irq;
+ }
+
+- ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
++ ret = devm_request_threaded_irq(dev, irq, NULL,
+ imx_tve_irq_handler, IRQF_ONESHOT,
+ "imx-tve", tve);
+ if (ret < 0) {
+- dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
++ dev_err(dev, "failed to request irq: %d\n", ret);
+ return ret;
+ }
+
+- tve->dac_reg = devm_regulator_get(&pdev->dev, "dac");
++ tve->dac_reg = devm_regulator_get(dev, "dac");
+ if (!IS_ERR(tve->dac_reg)) {
+ regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
+ ret = regulator_enable(tve->dac_reg);
+@@ -675,17 +647,17 @@
+ return ret;
+ }
+
+- tve->clk = devm_clk_get(&pdev->dev, "tve");
++ tve->clk = devm_clk_get(dev, "tve");
+ if (IS_ERR(tve->clk)) {
+- dev_err(&pdev->dev, "failed to get high speed tve clock: %ld\n",
++ dev_err(dev, "failed to get high speed tve clock: %ld\n",
+ PTR_ERR(tve->clk));
+ return PTR_ERR(tve->clk);
+ }
+
+ /* this is the IPU DI clock input selector, can be parented to tve_di */
+- tve->di_sel_clk = devm_clk_get(&pdev->dev, "di_sel");
++ tve->di_sel_clk = devm_clk_get(dev, "di_sel");
+ if (IS_ERR(tve->di_sel_clk)) {
+- dev_err(&pdev->dev, "failed to get ipu di mux clock: %ld\n",
++ dev_err(dev, "failed to get ipu di mux clock: %ld\n",
+ PTR_ERR(tve->di_sel_clk));
+ return PTR_ERR(tve->di_sel_clk);
+ }
+@@ -696,42 +668,51 @@
+
+ ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
+ if (ret < 0) {
+- dev_err(&pdev->dev, "failed to read configuration register: %d\n", ret);
++ dev_err(dev, "failed to read configuration register: %d\n", ret);
+ return ret;
+ }
+ if (val != 0x00100000) {
+- dev_err(&pdev->dev, "configuration register default value indicates this is not a TVEv2\n");
++ dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
+ return -ENODEV;
+- };
++ }
+
+ /* disable cable detection for VGA mode */
+ ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
+
+- ret = imx_tve_register(tve);
++ ret = imx_tve_register(drm, tve);
+ if (ret)
+ return ret;
+
+- ret = imx_drm_encoder_add_possible_crtcs(tve->imx_drm_encoder, np);
+-
+- platform_set_drvdata(pdev, tve);
++ dev_set_drvdata(dev, tve);
+
+ return 0;
+ }
+
+-static int imx_tve_remove(struct platform_device *pdev)
++static void imx_tve_unbind(struct device *dev, struct device *master,
++ void *data)
+ {
+- struct imx_tve *tve = platform_get_drvdata(pdev);
+- struct drm_connector *connector = &tve->connector;
+- struct drm_encoder *encoder = &tve->encoder;
++ struct imx_tve *tve = dev_get_drvdata(dev);
+
+- drm_mode_connector_detach_encoder(connector, encoder);
+-
+- imx_drm_remove_connector(tve->imx_drm_connector);
+- imx_drm_remove_encoder(tve->imx_drm_encoder);
++ tve->connector.funcs->destroy(&tve->connector);
++ tve->encoder.funcs->destroy(&tve->encoder);
+
+ if (!IS_ERR(tve->dac_reg))
+ regulator_disable(tve->dac_reg);
++}
++
++static const struct component_ops imx_tve_ops = {
++ .bind = imx_tve_bind,
++ .unbind = imx_tve_unbind,
++};
++
++static int imx_tve_probe(struct platform_device *pdev)
++{
++ return component_add(&pdev->dev, &imx_tve_ops);
++}
+
++static int imx_tve_remove(struct platform_device *pdev)
++{
++ component_del(&pdev->dev, &imx_tve_ops);
+ return 0;
+ }
+
+@@ -755,3 +736,4 @@
+ MODULE_DESCRIPTION("i.MX Television Encoder driver");
+ MODULE_AUTHOR("Philipp Zabel, Pengutronix");
+ MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-tve");
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.h 2014-05-15 20:34:05.754069749 +0200
+@@ -97,6 +97,7 @@
+
+ int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
+ int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
++int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
+
+ void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
+ bool doublebuffer);
+@@ -283,7 +284,7 @@
+ int width);
+
+ int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *,
+- struct ipu_rgb *rgb);
++ const struct ipu_rgb *rgb);
+
+ static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p,
+ int stride)
+@@ -303,6 +304,7 @@
+ int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
+ struct ipu_image *image);
+
++enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
+ enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
+
+ static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p,
+@@ -317,6 +319,7 @@
+ int dp;
+ int dmfc;
+ int dma[2];
++ int ipu;
+ };
+
+ #endif /* __DRM_IPU_H__ */
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-common.c linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-common.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-common.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-common.c 2014-05-15 20:34:05.754069749 +0200
+@@ -27,8 +27,11 @@
+ #include <linux/list.h>
+ #include <linux/irq.h>
+ #include <linux/irqchip/chained_irq.h>
++#include <linux/irqdomain.h>
+ #include <linux/of_device.h>
+
++#include <drm/drm_fourcc.h>
++
+ #include "imx-ipu-v3.h"
+ #include "ipu-prv.h"
+
+@@ -138,7 +141,7 @@
+ EXPORT_SYMBOL_GPL(ipu_ch_param_read_field);
+
+ int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *p,
+- struct ipu_rgb *rgb)
++ const struct ipu_rgb *rgb)
+ {
+ int bpp = 0, npb = 0, ro, go, bo, to;
+
+@@ -281,7 +284,7 @@
+ }
+ EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
+
+-static struct ipu_rgb def_rgb_32 = {
++static const struct ipu_rgb def_rgb_32 = {
+ .red = { .offset = 16, .length = 8, },
+ .green = { .offset = 8, .length = 8, },
+ .blue = { .offset = 0, .length = 8, },
+@@ -289,31 +292,31 @@
+ .bits_per_pixel = 32,
+ };
+
+-static struct ipu_rgb def_bgr_32 = {
+- .red = { .offset = 16, .length = 8, },
++static const struct ipu_rgb def_bgr_32 = {
++ .red = { .offset = 0, .length = 8, },
+ .green = { .offset = 8, .length = 8, },
+- .blue = { .offset = 0, .length = 8, },
++ .blue = { .offset = 16, .length = 8, },
+ .transp = { .offset = 24, .length = 8, },
+ .bits_per_pixel = 32,
+ };
+
+-static struct ipu_rgb def_rgb_24 = {
+- .red = { .offset = 0, .length = 8, },
++static const struct ipu_rgb def_rgb_24 = {
++ .red = { .offset = 16, .length = 8, },
+ .green = { .offset = 8, .length = 8, },
+- .blue = { .offset = 16, .length = 8, },
++ .blue = { .offset = 0, .length = 8, },
+ .transp = { .offset = 0, .length = 0, },
+ .bits_per_pixel = 24,
+ };
+
+-static struct ipu_rgb def_bgr_24 = {
+- .red = { .offset = 16, .length = 8, },
++static const struct ipu_rgb def_bgr_24 = {
++ .red = { .offset = 0, .length = 8, },
+ .green = { .offset = 8, .length = 8, },
+- .blue = { .offset = 0, .length = 8, },
++ .blue = { .offset = 16, .length = 8, },
+ .transp = { .offset = 0, .length = 0, },
+ .bits_per_pixel = 24,
+ };
+
+-static struct ipu_rgb def_rgb_16 = {
++static const struct ipu_rgb def_rgb_16 = {
+ .red = { .offset = 11, .length = 5, },
+ .green = { .offset = 5, .length = 6, },
+ .blue = { .offset = 0, .length = 5, },
+@@ -321,6 +324,14 @@
+ .bits_per_pixel = 16,
+ };
+
++static const struct ipu_rgb def_bgr_16 = {
++ .red = { .offset = 0, .length = 5, },
++ .green = { .offset = 5, .length = 6, },
++ .blue = { .offset = 11, .length = 5, },
++ .transp = { .offset = 0, .length = 0, },
++ .bits_per_pixel = 16,
++};
++
+ #define Y_OFFSET(pix, x, y) ((x) + pix->width * (y))
+ #define U_OFFSET(pix, x, y) ((pix->width * pix->height) + \
+ (pix->width * (y) / 4) + (x) / 2)
+@@ -328,17 +339,17 @@
+ (pix->width * pix->height / 4) + \
+ (pix->width * (y) / 4) + (x) / 2)
+
+-int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat)
++int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 drm_fourcc)
+ {
+- switch (pixelformat) {
+- case V4L2_PIX_FMT_YUV420:
+- case V4L2_PIX_FMT_YVU420:
++ switch (drm_fourcc) {
++ case DRM_FORMAT_YUV420:
++ case DRM_FORMAT_YVU420:
+ /* pix format */
+ ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 2);
+ /* burst size */
+ ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 63);
+ break;
+- case V4L2_PIX_FMT_UYVY:
++ case DRM_FORMAT_UYVY:
+ /* bits/pixel */
+ ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3);
+ /* pix format */
+@@ -346,7 +357,7 @@
+ /* burst size */
+ ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31);
+ break;
+- case V4L2_PIX_FMT_YUYV:
++ case DRM_FORMAT_YUYV:
+ /* bits/pixel */
+ ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3);
+ /* pix format */
+@@ -354,20 +365,25 @@
+ /* burst size */
+ ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31);
+ break;
+- case V4L2_PIX_FMT_RGB32:
+- ipu_cpmem_set_format_rgb(cpmem, &def_rgb_32);
++ case DRM_FORMAT_ABGR8888:
++ case DRM_FORMAT_XBGR8888:
++ ipu_cpmem_set_format_rgb(cpmem, &def_bgr_32);
+ break;
+- case V4L2_PIX_FMT_RGB565:
+- ipu_cpmem_set_format_rgb(cpmem, &def_rgb_16);
++ case DRM_FORMAT_ARGB8888:
++ case DRM_FORMAT_XRGB8888:
++ ipu_cpmem_set_format_rgb(cpmem, &def_rgb_32);
+ break;
+- case V4L2_PIX_FMT_BGR32:
+- ipu_cpmem_set_format_rgb(cpmem, &def_bgr_32);
++ case DRM_FORMAT_BGR888:
++ ipu_cpmem_set_format_rgb(cpmem, &def_bgr_24);
+ break;
+- case V4L2_PIX_FMT_RGB24:
++ case DRM_FORMAT_RGB888:
+ ipu_cpmem_set_format_rgb(cpmem, &def_rgb_24);
+ break;
+- case V4L2_PIX_FMT_BGR24:
+- ipu_cpmem_set_format_rgb(cpmem, &def_bgr_24);
++ case DRM_FORMAT_RGB565:
++ ipu_cpmem_set_format_rgb(cpmem, &def_rgb_16);
++ break;
++ case DRM_FORMAT_BGR565:
++ ipu_cpmem_set_format_rgb(cpmem, &def_bgr_16);
+ break;
+ default:
+ return -EINVAL;
+@@ -377,6 +393,79 @@
+ }
+ EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
+
++/*
++ * The V4L2 spec defines packed RGB formats in memory byte order, which from
++ * point of view of the IPU corresponds to little-endian words with the first
++ * component in the least significant bits.
++ * The DRM pixel formats and IPU internal representation are ordered the other
++ * way around, with the first named component ordered at the most significant
++ * bits. Further, V4L2 formats are not well defined:
++ * http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
++ * We choose the interpretation which matches GStreamer behavior.
++ */
++static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
++{
++ switch (pixelformat) {
++ case V4L2_PIX_FMT_RGB565:
++ /*
++ * Here we choose the 'corrected' interpretation of RGBP, a
++ * little-endian 16-bit word with the red component at the most
++ * significant bits:
++ * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
++ */
++ return DRM_FORMAT_RGB565;
++ case V4L2_PIX_FMT_BGR24:
++ /* B G R <=> [24:0] R:G:B */
++ return DRM_FORMAT_RGB888;
++ case V4L2_PIX_FMT_RGB24:
++ /* R G B <=> [24:0] B:G:R */
++ return DRM_FORMAT_BGR888;
++ case V4L2_PIX_FMT_BGR32:
++ /* B G R A <=> [32:0] A:B:G:R */
++ return DRM_FORMAT_XRGB8888;
++ case V4L2_PIX_FMT_RGB32:
++ /* R G B A <=> [32:0] A:B:G:R */
++ return DRM_FORMAT_XBGR8888;
++ case V4L2_PIX_FMT_UYVY:
++ return DRM_FORMAT_UYVY;
++ case V4L2_PIX_FMT_YUYV:
++ return DRM_FORMAT_YUYV;
++ case V4L2_PIX_FMT_YUV420:
++ return DRM_FORMAT_YUV420;
++ case V4L2_PIX_FMT_YVU420:
++ return DRM_FORMAT_YVU420;
++ }
++
++ return -EINVAL;
++}
++
++enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
++{
++ switch (drm_fourcc) {
++ case DRM_FORMAT_RGB565:
++ case DRM_FORMAT_BGR565:
++ case DRM_FORMAT_RGB888:
++ case DRM_FORMAT_BGR888:
++ case DRM_FORMAT_XRGB8888:
++ case DRM_FORMAT_XBGR8888:
++ case DRM_FORMAT_RGBX8888:
++ case DRM_FORMAT_BGRX8888:
++ case DRM_FORMAT_ARGB8888:
++ case DRM_FORMAT_ABGR8888:
++ case DRM_FORMAT_RGBA8888:
++ case DRM_FORMAT_BGRA8888:
++ return IPUV3_COLORSPACE_RGB;
++ case DRM_FORMAT_YUYV:
++ case DRM_FORMAT_UYVY:
++ case DRM_FORMAT_YUV420:
++ case DRM_FORMAT_YVU420:
++ return IPUV3_COLORSPACE_YUV;
++ default:
++ return IPUV3_COLORSPACE_UNKNOWN;
++ }
++}
++EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
++
+ int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
+ struct ipu_image *image)
+ {
+@@ -391,7 +480,7 @@
+ image->rect.height);
+ ipu_cpmem_set_stride(cpmem, pix->bytesperline);
+
+- ipu_cpmem_set_fmt(cpmem, pix->pixelformat);
++ ipu_cpmem_set_fmt(cpmem, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
+
+ switch (pix->pixelformat) {
+ case V4L2_PIX_FMT_YUV420:
+@@ -475,7 +564,7 @@
+ goto out;
+ }
+
+- channel->busy = 1;
++ channel->busy = true;
+ channel->num = num;
+
+ out:
+@@ -493,7 +582,7 @@
+
+ mutex_lock(&ipu->channel_lock);
+
+- channel->busy = 0;
++ channel->busy = false;
+
+ mutex_unlock(&ipu->channel_lock);
+ }
+@@ -609,24 +698,29 @@
+ }
+ EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
+
+-int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
++int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
+ {
+ struct ipu_soc *ipu = channel->ipu;
+- u32 val;
+- unsigned long flags;
+ unsigned long timeout;
+
+- timeout = jiffies + msecs_to_jiffies(50);
++ timeout = jiffies + msecs_to_jiffies(ms);
+ while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
+ idma_mask(channel->num)) {
+- if (time_after(jiffies, timeout)) {
+- dev_warn(ipu->dev, "disabling busy idmac channel %d\n",
+- channel->num);
+- break;
+- }
++ if (time_after(jiffies, timeout))
++ return -ETIMEDOUT;
+ cpu_relax();
+ }
+
++ return 0;
++}
++EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
++
++int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
++{
++ struct ipu_soc *ipu = channel->ipu;
++ u32 val;
++ unsigned long flags;
++
+ spin_lock_irqsave(&ipu->lock, flags);
+
+ /* Disable DMA channel(s) */
+@@ -799,16 +893,18 @@
+ static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
+ {
+ unsigned long status;
+- int i, bit, irq_base;
++ int i, bit, irq;
+
+ for (i = 0; i < num_regs; i++) {
+
+ status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
+ status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
+
+- irq_base = ipu->irq_start + regs[i] * 32;
+- for_each_set_bit(bit, &status, 32)
+- generic_handle_irq(irq_base + bit);
++ for_each_set_bit(bit, &status, 32) {
++ irq = irq_linear_revmap(ipu->domain, regs[i] * 32 + bit);
++ if (irq)
++ generic_handle_irq(irq);
++ }
+ }
+ }
+
+@@ -838,57 +934,15 @@
+ chained_irq_exit(chip, desc);
+ }
+
+-static void ipu_ack_irq(struct irq_data *d)
+-{
+- struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
+- unsigned int irq = d->irq - ipu->irq_start;
+-
+- ipu_cm_write(ipu, 1 << (irq % 32), IPU_INT_STAT(irq / 32));
+-}
+-
+-static void ipu_unmask_irq(struct irq_data *d)
+-{
+- struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
+- unsigned int irq = d->irq - ipu->irq_start;
+- unsigned long flags;
+- u32 reg;
+-
+- spin_lock_irqsave(&ipu->lock, flags);
+-
+- reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32));
+- reg |= 1 << (irq % 32);
+- ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32));
+-
+- spin_unlock_irqrestore(&ipu->lock, flags);
+-}
+-
+-static void ipu_mask_irq(struct irq_data *d)
+-{
+- struct ipu_soc *ipu = irq_data_get_irq_chip_data(d);
+- unsigned int irq = d->irq - ipu->irq_start;
+- unsigned long flags;
+- u32 reg;
+-
+- spin_lock_irqsave(&ipu->lock, flags);
+-
+- reg = ipu_cm_read(ipu, IPU_INT_CTRL(irq / 32));
+- reg &= ~(1 << (irq % 32));
+- ipu_cm_write(ipu, reg, IPU_INT_CTRL(irq / 32));
+-
+- spin_unlock_irqrestore(&ipu->lock, flags);
+-}
+-
+-static struct irq_chip ipu_irq_chip = {
+- .name = "IPU",
+- .irq_ack = ipu_ack_irq,
+- .irq_mask = ipu_mask_irq,
+- .irq_unmask = ipu_unmask_irq,
+-};
+-
+ int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
+ enum ipu_channel_irq irq_type)
+ {
+- return ipu->irq_start + irq_type + channel->num;
++ int irq = irq_linear_revmap(ipu->domain, irq_type + channel->num);
++
++ if (!irq)
++ irq = irq_create_mapping(ipu->domain, irq_type + channel->num);
++
++ return irq;
+ }
+ EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
+
+@@ -927,7 +981,7 @@
+ .dc = 5,
+ .dp = IPU_DP_FLOW_SYNC_BG,
+ .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
+- .dma[1] = -EINVAL,
++ .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
+ },
+ .name = "imx-ipuv3-crtc",
+ }, {
+@@ -942,51 +996,88 @@
+ },
+ };
+
++static DEFINE_MUTEX(ipu_client_id_mutex);
+ static int ipu_client_id;
+
+-static int ipu_add_subdevice_pdata(struct device *dev,
+- const struct ipu_platform_reg *reg)
++static int ipu_add_client_devices(struct ipu_soc *ipu)
+ {
+- struct platform_device *pdev;
++ struct device *dev = ipu->dev;
++ unsigned i;
++ int ipu_id, id, ret;
++
++ mutex_lock(&ipu_client_id_mutex);
++ id = ipu_client_id++;
++ mutex_unlock(&ipu_client_id_mutex);
+
+- pdev = platform_device_register_data(dev, reg->name, ipu_client_id++,
+- &reg->pdata, sizeof(struct ipu_platform_reg));
++ /* FIXME: this needs a better solution */
++ ipu_id = id;
+
+- return pdev ? 0 : -EINVAL;
+-}
+-
+-static int ipu_add_client_devices(struct ipu_soc *ipu)
+-{
+- int ret;
+- int i;
++ id *= ARRAY_SIZE(client_reg);
+
+ for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
+ const struct ipu_platform_reg *reg = &client_reg[i];
+- ret = ipu_add_subdevice_pdata(ipu->dev, reg);
+- if (ret)
++ struct ipu_client_platformdata pdata = reg->pdata;
++ struct platform_device *pdev;
++
++ pdata.ipu = ipu_id;
++
++ pdev = platform_device_register_data(dev, reg->name,
++ id++, &pdata, sizeof(pdata));
++
++ if (IS_ERR(pdev))
+ goto err_register;
+ }
+
+ return 0;
+
+ err_register:
+- platform_device_unregister_children(to_platform_device(ipu->dev));
++ platform_device_unregister_children(to_platform_device(dev));
+
+ return ret;
+ }
+
++
+ static int ipu_irq_init(struct ipu_soc *ipu)
+ {
+- int i;
++ struct irq_chip_generic *gc;
++ struct irq_chip_type *ct;
++ unsigned long unused[IPU_NUM_IRQS / 32] = {
++ 0x400100d0, 0xffe000fd,
++ 0x400100d0, 0xffe000fd,
++ 0x400100d0, 0xffe000fd,
++ 0x4077ffff, 0xffe7e1fd,
++ 0x23fffffe, 0x8880fff0,
++ 0xf98fe7d0, 0xfff81fff,
++ 0x400100d0, 0xffe000fd,
++ 0x00000000,
++ };
++ int ret, i;
++
++ ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
++ &irq_generic_chip_ops, ipu);
++ if (!ipu->domain) {
++ dev_err(ipu->dev, "failed to add irq domain\n");
++ return -ENODEV;
++ }
+
+- ipu->irq_start = irq_alloc_descs(-1, 0, IPU_NUM_IRQS, 0);
+- if (ipu->irq_start < 0)
+- return ipu->irq_start;
+-
+- for (i = ipu->irq_start; i < ipu->irq_start + IPU_NUM_IRQS; i++) {
+- irq_set_chip_and_handler(i, &ipu_irq_chip, handle_level_irq);
+- set_irq_flags(i, IRQF_VALID);
+- irq_set_chip_data(i, ipu);
++ ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
++ handle_level_irq, 0, IRQF_VALID, 0);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to alloc generic irq chips\n");
++ irq_domain_remove(ipu->domain);
++ return ret;
++ }
++
++ for (i = 0; i < IPU_NUM_IRQS; i += 32) {
++ gc = irq_get_domain_generic_chip(ipu->domain, i);
++ gc->reg_base = ipu->cm_reg;
++ gc->unused = unused[i / 32];
++ ct = gc->chip_types;
++ ct->chip.irq_ack = irq_gc_ack_set_bit;
++ ct->chip.irq_mask = irq_gc_mask_clr_bit;
++ ct->chip.irq_unmask = irq_gc_mask_set_bit;
++ ct->regs.ack = IPU_INT_STAT(i / 32);
++ ct->regs.mask = IPU_INT_CTRL(i / 32);
+ }
+
+ irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
+@@ -999,20 +1090,22 @@
+
+ static void ipu_irq_exit(struct ipu_soc *ipu)
+ {
+- int i;
++ int i, irq;
+
+ irq_set_chained_handler(ipu->irq_err, NULL);
+ irq_set_handler_data(ipu->irq_err, NULL);
+ irq_set_chained_handler(ipu->irq_sync, NULL);
+ irq_set_handler_data(ipu->irq_sync, NULL);
+
+- for (i = ipu->irq_start; i < ipu->irq_start + IPU_NUM_IRQS; i++) {
+- set_irq_flags(i, 0);
+- irq_set_chip(i, NULL);
+- irq_set_chip_data(i, NULL);
++ /* TODO: remove irq_domain_generic_chips */
++
++ for (i = 0; i < IPU_NUM_IRQS; i++) {
++ irq = irq_linear_revmap(ipu->domain, i);
++ if (irq)
++ irq_dispose_mapping(irq);
+ }
+
+- irq_free_descs(ipu->irq_start, IPU_NUM_IRQS);
++ irq_domain_remove(ipu->domain);
+ }
+
+ static int ipu_probe(struct platform_device *pdev)
+@@ -1082,21 +1175,23 @@
+ ipu->cpmem_base = devm_ioremap(&pdev->dev,
+ ipu_base + devtype->cpmem_ofs, PAGE_SIZE);
+
+- if (!ipu->cm_reg || !ipu->idmac_reg || !ipu->cpmem_base) {
+- ret = -ENOMEM;
+- goto failed_ioremap;
+- }
++ if (!ipu->cm_reg || !ipu->idmac_reg || !ipu->cpmem_base)
++ return -ENOMEM;
+
+ ipu->clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(ipu->clk)) {
+ ret = PTR_ERR(ipu->clk);
+ dev_err(&pdev->dev, "clk_get failed with %d", ret);
+- goto failed_clk_get;
++ return ret;
+ }
+
+ platform_set_drvdata(pdev, ipu);
+
+- clk_prepare_enable(ipu->clk);
++ ret = clk_prepare_enable(ipu->clk);
++ if (ret) {
++ dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
++ return ret;
++ }
+
+ ipu->dev = &pdev->dev;
+ ipu->irq_sync = irq_sync;
+@@ -1141,8 +1236,6 @@
+ ipu_irq_exit(ipu);
+ out_failed_irq:
+ clk_disable_unprepare(ipu->clk);
+-failed_clk_get:
+-failed_ioremap:
+ return ret;
+ }
+
+@@ -1170,6 +1263,7 @@
+
+ module_platform_driver(imx_ipu_driver);
+
++MODULE_ALIAS("platform:imx-ipuv3");
+ MODULE_DESCRIPTION("i.MX IPU v3 driver");
+ MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+ MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-dc.c linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-dc.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-dc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-dc.c 2014-05-15 20:34:05.754069749 +0200
+@@ -91,6 +91,7 @@
+ IPU_DC_MAP_RGB565,
+ IPU_DC_MAP_GBR24, /* TVEv2 */
+ IPU_DC_MAP_BGR666,
++ IPU_DC_MAP_BGR24,
+ };
+
+ struct ipu_dc {
+@@ -152,6 +153,8 @@
+ return IPU_DC_MAP_GBR24;
+ case V4L2_PIX_FMT_BGR666:
+ return IPU_DC_MAP_BGR666;
++ case V4L2_PIX_FMT_BGR24:
++ return IPU_DC_MAP_BGR24;
+ default:
+ return -EINVAL;
+ }
+@@ -161,14 +164,15 @@
+ u32 pixel_fmt, u32 width)
+ {
+ struct ipu_dc_priv *priv = dc->priv;
+- u32 reg = 0, map;
++ u32 reg = 0;
++ int map;
+
+ dc->di = ipu_di_get_num(di);
+
+ map = ipu_pixfmt_to_map(pixel_fmt);
+ if (map < 0) {
+ dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
+- return -EINVAL;
++ return map;
+ }
+
+ if (interlaced) {
+@@ -312,7 +316,7 @@
+ return ERR_PTR(-EBUSY);
+ }
+
+- dc->in_use = 1;
++ dc->in_use = true;
+
+ mutex_unlock(&priv->mutex);
+
+@@ -325,7 +329,7 @@
+ struct ipu_dc_priv *priv = dc->priv;
+
+ mutex_lock(&priv->mutex);
+- dc->in_use = 0;
++ dc->in_use = false;
+ mutex_unlock(&priv->mutex);
+ }
+ EXPORT_SYMBOL_GPL(ipu_dc_put);
+@@ -394,6 +398,12 @@
+ ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
+ ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
+
++ /* bgr24 */
++ ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
++ ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
++ ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
++ ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
++
+ return 0;
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-di.c linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-di.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-di.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-di.c 2014-05-15 20:34:05.758069778 +0200
+@@ -19,9 +19,6 @@
+ #include <linux/io.h>
+ #include <linux/err.h>
+ #include <linux/platform_device.h>
+-#include <linux/clk.h>
+-#include <linux/clk-provider.h>
+-#include <linux/clkdev.h>
+
+ #include "imx-ipu-v3.h"
+ #include "ipu-prv.h"
+@@ -33,10 +30,7 @@
+ struct clk *clk_di; /* display input clock */
+ struct clk *clk_ipu; /* IPU bus clock */
+ struct clk *clk_di_pixel; /* resulting pixel clock */
+- struct clk_hw clk_hw_out;
+- char *clk_name;
+ bool inuse;
+- unsigned long clkflags;
+ struct ipu_soc *ipu;
+ };
+
+@@ -141,130 +135,6 @@
+ writel(value, di->base + offset);
+ }
+
+-static int ipu_di_clk_calc_div(unsigned long inrate, unsigned long outrate)
+-{
+- u64 tmp = inrate;
+- int div;
+-
+- tmp *= 16;
+-
+- do_div(tmp, outrate);
+-
+- div = tmp;
+-
+- if (div < 0x10)
+- div = 0x10;
+-
+-#ifdef WTF_IS_THIS
+- /*
+- * Freescale has this in their Kernel. It is neither clear what
+- * it does nor why it does it
+- */
+- if (div & 0x10)
+- div &= ~0x7;
+- else {
+- /* Round up divider if it gets us closer to desired pix clk */
+- if ((div & 0xC) == 0xC) {
+- div += 0x10;
+- div &= ~0xF;
+- }
+- }
+-#endif
+- return div;
+-}
+-
+-static unsigned long clk_di_recalc_rate(struct clk_hw *hw,
+- unsigned long parent_rate)
+-{
+- struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
+- unsigned long outrate;
+- u32 div = ipu_di_read(di, DI_BS_CLKGEN0);
+-
+- if (div < 0x10)
+- div = 0x10;
+-
+- outrate = (parent_rate / div) * 16;
+-
+- return outrate;
+-}
+-
+-static long clk_di_round_rate(struct clk_hw *hw, unsigned long rate,
+- unsigned long *prate)
+-{
+- struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
+- unsigned long outrate;
+- int div;
+- u32 val;
+-
+- div = ipu_di_clk_calc_div(*prate, rate);
+-
+- outrate = (*prate / div) * 16;
+-
+- val = ipu_di_read(di, DI_GENERAL);
+-
+- if (!(val & DI_GEN_DI_CLK_EXT) && outrate > *prate / 2)
+- outrate = *prate / 2;
+-
+- dev_dbg(di->ipu->dev,
+- "%s: inrate: %ld div: 0x%08x outrate: %ld wanted: %ld\n",
+- __func__, *prate, div, outrate, rate);
+-
+- return outrate;
+-}
+-
+-static int clk_di_set_rate(struct clk_hw *hw, unsigned long rate,
+- unsigned long parent_rate)
+-{
+- struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
+- int div;
+- u32 clkgen0;
+-
+- clkgen0 = ipu_di_read(di, DI_BS_CLKGEN0) & ~0xfff;
+-
+- div = ipu_di_clk_calc_div(parent_rate, rate);
+-
+- ipu_di_write(di, clkgen0 | div, DI_BS_CLKGEN0);
+-
+- dev_dbg(di->ipu->dev, "%s: inrate: %ld desired: %ld div: 0x%08x\n",
+- __func__, parent_rate, rate, div);
+- return 0;
+-}
+-
+-static u8 clk_di_get_parent(struct clk_hw *hw)
+-{
+- struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
+- u32 val;
+-
+- val = ipu_di_read(di, DI_GENERAL);
+-
+- return val & DI_GEN_DI_CLK_EXT ? 1 : 0;
+-}
+-
+-static int clk_di_set_parent(struct clk_hw *hw, u8 index)
+-{
+- struct ipu_di *di = container_of(hw, struct ipu_di, clk_hw_out);
+- u32 val;
+-
+- val = ipu_di_read(di, DI_GENERAL);
+-
+- if (index)
+- val |= DI_GEN_DI_CLK_EXT;
+- else
+- val &= ~DI_GEN_DI_CLK_EXT;
+-
+- ipu_di_write(di, val, DI_GENERAL);
+-
+- return 0;
+-}
+-
+-static struct clk_ops clk_di_ops = {
+- .round_rate = clk_di_round_rate,
+- .set_rate = clk_di_set_rate,
+- .recalc_rate = clk_di_recalc_rate,
+- .set_parent = clk_di_set_parent,
+- .get_parent = clk_di_get_parent,
+-};
+-
+ static void ipu_di_data_wave_config(struct ipu_di *di,
+ int wave_gen,
+ int access_size, int component_size)
+@@ -528,15 +398,125 @@
+ ipu_di_sync_config(di, cfg_vga, 0, ARRAY_SIZE(cfg_vga));
+ }
+
++static void ipu_di_config_clock(struct ipu_di *di,
++ const struct ipu_di_signal_cfg *sig)
++{
++ struct clk *clk;
++ unsigned clkgen0;
++ uint32_t val;
++
++ if (sig->clkflags & IPU_DI_CLKMODE_EXT) {
++ /*
++ * CLKMODE_EXT means we must use the DI clock: this is
++ * needed for things like LVDS which needs to feed the
++ * DI and LDB with the same pixel clock.
++ */
++ clk = di->clk_di;
++
++ if (sig->clkflags & IPU_DI_CLKMODE_SYNC) {
++ /*
++ * CLKMODE_SYNC means that we want the DI to be
++ * clocked at the same rate as the parent clock.
++ * This is needed (eg) for LDB which needs to be
++ * fed with the same pixel clock. We assume that
++ * the LDB clock has already been set correctly.
++ */
++ clkgen0 = 1 << 4;
++ } else {
++ /*
++ * We can use the divider. We should really have
++ * a flag here indicating whether the bridge can
++ * cope with a fractional divider or not. For the
++ * time being, let's go for simplicitly and
++ * reliability.
++ */
++ unsigned long in_rate;
++ unsigned div;
++
++ clk_set_rate(clk, sig->pixelclock);
++
++ in_rate = clk_get_rate(clk);
++ div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
++ if (div == 0)
++ div = 1;
++
++ clkgen0 = div << 4;
++ }
++ } else {
++ /*
++ * For other interfaces, we can arbitarily select between
++ * the DI specific clock and the internal IPU clock. See
++ * DI_GENERAL bit 20. We select the IPU clock if it can
++ * give us a clock rate within 1% of the requested frequency,
++ * otherwise we use the DI clock.
++ */
++ unsigned long rate, clkrate;
++ unsigned div, error;
++
++ clkrate = clk_get_rate(di->clk_ipu);
++ div = (clkrate + sig->pixelclock / 2) / sig->pixelclock;
++ rate = clkrate / div;
++
++ error = rate / (sig->pixelclock / 1000);
++
++ dev_dbg(di->ipu->dev, " IPU clock can give %lu with divider %u, error %d.%u%%\n",
++ rate, div, (signed)(error - 1000) / 10, error % 10);
++
++ /* Allow a 1% error */
++ if (error < 1010 && error >= 990) {
++ clk = di->clk_ipu;
++
++ clkgen0 = div << 4;
++ } else {
++ unsigned long in_rate;
++ unsigned div;
++
++ clk = di->clk_di;
++
++ clk_set_rate(clk, sig->pixelclock);
++
++ in_rate = clk_get_rate(clk);
++ div = (in_rate + sig->pixelclock / 2) / sig->pixelclock;
++ if (div == 0)
++ div = 1;
++
++ clkgen0 = div << 4;
++ }
++ }
++
++ di->clk_di_pixel = clk;
++
++ /* Set the divider */
++ ipu_di_write(di, clkgen0, DI_BS_CLKGEN0);
++
++ /*
++ * Set the high/low periods. Bits 24:16 give us the falling edge,
++ * and bits 8:0 give the rising edge. LSB is fraction, and is
++ * based on the divider above. We want a 50% duty cycle, so set
++ * the falling edge to be half the divider.
++ */
++ ipu_di_write(di, (clkgen0 >> 4) << 16, DI_BS_CLKGEN1);
++
++ /* Finally select the input clock */
++ val = ipu_di_read(di, DI_GENERAL) & ~DI_GEN_DI_CLK_EXT;
++ if (clk == di->clk_di)
++ val |= DI_GEN_DI_CLK_EXT;
++ ipu_di_write(di, val, DI_GENERAL);
++
++ dev_dbg(di->ipu->dev, "Want %luHz IPU %luHz DI %luHz using %s, %luHz\n",
++ sig->pixelclock,
++ clk_get_rate(di->clk_ipu),
++ clk_get_rate(di->clk_di),
++ clk == di->clk_di ? "DI" : "IPU",
++ clk_get_rate(di->clk_di_pixel) / (clkgen0 >> 4));
++}
++
+ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
+ {
+ u32 reg;
+ u32 di_gen, vsync_cnt;
+ u32 div;
+ u32 h_total, v_total;
+- int ret;
+- unsigned long round;
+- struct clk *parent;
+
+ dev_dbg(di->ipu->dev, "disp %d: panel size = %d x %d\n",
+ di->id, sig->width, sig->height);
+@@ -544,33 +524,20 @@
+ if ((sig->v_sync_width == 0) || (sig->h_sync_width == 0))
+ return -EINVAL;
+
+- if (sig->clkflags & IPU_DI_CLKMODE_EXT)
+- parent = di->clk_di;
+- else
+- parent = di->clk_ipu;
+-
+- ret = clk_set_parent(di->clk_di_pixel, parent);
+- if (ret) {
+- dev_err(di->ipu->dev,
+- "setting pixel clock to parent %s failed with %d\n",
+- __clk_get_name(parent), ret);
+- return ret;
+- }
+-
+- if (sig->clkflags & IPU_DI_CLKMODE_SYNC)
+- round = clk_get_rate(parent);
+- else
+- round = clk_round_rate(di->clk_di_pixel, sig->pixelclock);
+-
+- ret = clk_set_rate(di->clk_di_pixel, round);
+-
+ h_total = sig->width + sig->h_sync_width + sig->h_start_width +
+ sig->h_end_width;
+ v_total = sig->height + sig->v_sync_width + sig->v_start_width +
+ sig->v_end_width;
+
++ dev_dbg(di->ipu->dev, "Clocks: IPU %luHz DI %luHz Needed %luHz\n",
++ clk_get_rate(di->clk_ipu),
++ clk_get_rate(di->clk_di),
++ sig->pixelclock);
++
+ mutex_lock(&di_mutex);
+
++ ipu_di_config_clock(di, sig);
++
+ div = ipu_di_read(di, DI_BS_CLKGEN0) & 0xfff;
+ div = div / 16; /* Now divider is integer portion */
+
+@@ -603,7 +570,12 @@
+
+ vsync_cnt = 3;
+ if (di->id == 1)
+- vsync_cnt = 6;
++ /*
++ * TODO: change only for TVEv2, parallel display
++ * uses pin 2 / 3
++ */
++ if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
++ vsync_cnt = 6;
+
+ if (sig->Hsync_pol) {
+ if (sig->hsync_pin == 2)
+@@ -614,11 +586,11 @@
+ di_gen |= DI_GEN_POLARITY_7;
+ }
+ if (sig->Vsync_pol) {
+- if (sig->hsync_pin == 3)
++ if (sig->vsync_pin == 3)
+ di_gen |= DI_GEN_POLARITY_3;
+- else if (sig->hsync_pin == 6)
++ else if (sig->vsync_pin == 6)
+ di_gen |= DI_GEN_POLARITY_6;
+- else if (sig->hsync_pin == 8)
++ else if (sig->vsync_pin == 8)
+ di_gen |= DI_GEN_POLARITY_8;
+ }
+ }
+@@ -649,7 +621,13 @@
+
+ int ipu_di_enable(struct ipu_di *di)
+ {
+- clk_prepare_enable(di->clk_di_pixel);
++ int ret;
++
++ WARN_ON(IS_ERR(di->clk_di_pixel));
++
++ ret = clk_prepare_enable(di->clk_di_pixel);
++ if (ret)
++ return ret;
+
+ ipu_module_enable(di->ipu, di->module);
+
+@@ -659,6 +637,8 @@
+
+ int ipu_di_disable(struct ipu_di *di)
+ {
++ WARN_ON(IS_ERR(di->clk_di_pixel));
++
+ ipu_module_disable(di->ipu, di->module);
+
+ clk_disable_unprepare(di->clk_di_pixel);
+@@ -714,13 +694,6 @@
+ u32 module, struct clk *clk_ipu)
+ {
+ struct ipu_di *di;
+- int ret;
+- const char *di_parent[2];
+- struct clk_init_data init = {
+- .ops = &clk_di_ops,
+- .num_parents = 2,
+- .flags = 0,
+- };
+
+ if (id > 1)
+ return -ENODEV;
+@@ -742,45 +715,16 @@
+ if (!di->base)
+ return -ENOMEM;
+
+- di_parent[0] = __clk_get_name(di->clk_ipu);
+- di_parent[1] = __clk_get_name(di->clk_di);
+-
+ ipu_di_write(di, 0x10, DI_BS_CLKGEN0);
+
+- init.parent_names = (const char **)&di_parent;
+- di->clk_name = kasprintf(GFP_KERNEL, "%s_di%d_pixel",
+- dev_name(dev), id);
+- if (!di->clk_name)
+- return -ENOMEM;
+-
+- init.name = di->clk_name;
+-
+- di->clk_hw_out.init = &init;
+- di->clk_di_pixel = clk_register(dev, &di->clk_hw_out);
+-
+- if (IS_ERR(di->clk_di_pixel)) {
+- ret = PTR_ERR(di->clk_di_pixel);
+- goto failed_clk_register;
+- }
+-
+ dev_dbg(dev, "DI%d base: 0x%08lx remapped to %p\n",
+ id, base, di->base);
+ di->inuse = false;
+ di->ipu = ipu;
+
+ return 0;
+-
+-failed_clk_register:
+-
+- kfree(di->clk_name);
+-
+- return ret;
+ }
+
+ void ipu_di_exit(struct ipu_soc *ipu, int id)
+ {
+- struct ipu_di *di = ipu->di_priv[id];
+-
+- clk_unregister(di->clk_di_pixel);
+- kfree(di->clk_name);
+ }
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-dmfc.c 2014-05-15 20:34:05.758069778 +0200
+@@ -61,7 +61,7 @@
+
+ static const struct dmfc_channel_data dmfcdata[] = {
+ {
+- .ipu_channel = 23,
++ .ipu_channel = IPUV3_CHANNEL_MEM_BG_SYNC,
+ .channel_reg = DMFC_DP_CHAN,
+ .shift = DMFC_DP_CHAN_5B_23,
+ .eot_shift = 20,
+@@ -73,13 +73,13 @@
+ .eot_shift = 22,
+ .max_fifo_lines = 1,
+ }, {
+- .ipu_channel = 27,
++ .ipu_channel = IPUV3_CHANNEL_MEM_FG_SYNC,
+ .channel_reg = DMFC_DP_CHAN,
+ .shift = DMFC_DP_CHAN_5F_27,
+ .eot_shift = 21,
+ .max_fifo_lines = 2,
+ }, {
+- .ipu_channel = 28,
++ .ipu_channel = IPUV3_CHANNEL_MEM_DC_SYNC,
+ .channel_reg = DMFC_WR_CHAN,
+ .shift = DMFC_WR_CHAN_1_28,
+ .eot_shift = 16,
+@@ -292,7 +292,7 @@
+ {
+ struct ipu_dmfc_priv *priv = dmfc->priv;
+ int slots = dmfc_bandwidth_to_slots(priv, bandwidth_pixel_per_second);
+- int segment = 0, ret = 0;
++ int segment = -1, ret = 0;
+
+ dev_dbg(priv->dev, "dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
+ bandwidth_pixel_per_second / 1000000,
+@@ -307,7 +307,17 @@
+ goto out;
+ }
+
+- segment = dmfc_find_slots(priv, slots);
++ /* For the MEM_BG channel, first try to allocate twice the slots */
++ if (dmfc->data->ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC)
++ segment = dmfc_find_slots(priv, slots * 2);
++ else if (slots < 2)
++ /* Always allocate at least 128*4 bytes (2 slots) */
++ slots = 2;
++
++ if (segment >= 0)
++ slots *= 2;
++ else
++ segment = dmfc_find_slots(priv, slots);
+ if (segment < 0) {
+ ret = -EBUSY;
+ goto out;
+@@ -391,7 +401,7 @@
+ * We have a total bandwidth of clkrate * 4pixel divided
+ * into 8 slots.
+ */
+- priv->bandwidth_per_slot = clk_get_rate(ipu_clk) / 8;
++ priv->bandwidth_per_slot = clk_get_rate(ipu_clk) * 4 / 8;
+
+ dev_dbg(dev, "dmfc: 8 slots with %ldMpixel/s bandwidth each\n",
+ priv->bandwidth_per_slot / 1000000);
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-dp.c linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-dp.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-dp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-dp.c 2014-05-15 20:34:05.758069778 +0200
+@@ -46,6 +46,8 @@
+ #define DP_COM_CONF_CSC_DEF_BG (2 << 8)
+ #define DP_COM_CONF_CSC_DEF_BOTH (1 << 8)
+
++#define IPUV3_NUM_FLOWS 3
++
+ struct ipu_dp_priv;
+
+ struct ipu_dp {
+@@ -67,7 +69,7 @@
+ struct ipu_soc *ipu;
+ struct device *dev;
+ void __iomem *base;
+- struct ipu_flow flow[3];
++ struct ipu_flow flow[IPUV3_NUM_FLOWS];
+ struct mutex mutex;
+ int use_count;
+ };
+@@ -280,7 +282,7 @@
+ struct ipu_dp_priv *priv = ipu->dp_priv;
+ struct ipu_dp *dp;
+
+- if (flow > 5)
++ if ((flow >> 1) >= IPUV3_NUM_FLOWS)
+ return ERR_PTR(-EINVAL);
+
+ if (flow & 1)
+@@ -309,20 +311,21 @@
+ int i;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
+ priv->dev = dev;
+ priv->ipu = ipu;
+
+ ipu->dp_priv = priv;
+
+ priv->base = devm_ioremap(dev, base, PAGE_SIZE);
+- if (!priv->base) {
++ if (!priv->base)
+ return -ENOMEM;
+- }
+
+ mutex_init(&priv->mutex);
+
+- for (i = 0; i < 3; i++) {
+- priv->flow[i].foreground.foreground = 1;
++ for (i = 0; i < IPUV3_NUM_FLOWS; i++) {
++ priv->flow[i].foreground.foreground = true;
+ priv->flow[i].base = priv->base + ipu_dp_flow_base[i];
+ priv->flow[i].priv = priv;
+ }
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-prv.h linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-prv.h
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipu-v3/ipu-prv.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipu-v3/ipu-prv.h 2014-05-15 20:34:05.758069778 +0200
+@@ -110,7 +110,7 @@
+ #define IDMAC_BAND_EN(ch) IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
+ #define IDMAC_CHA_BUSY(ch) IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
+
+-#define IPU_NUM_IRQS (32 * 5)
++#define IPU_NUM_IRQS (32 * 15)
+
+ enum ipu_modules {
+ IPU_CONF_CSI0_EN = (1 << 0),
+@@ -170,9 +170,9 @@
+
+ struct ipuv3_channel channel[64];
+
+- int irq_start;
+ int irq_sync;
+ int irq_err;
++ struct irq_domain *domain;
+
+ struct ipu_dc_priv *dc_priv;
+ struct ipu_dp_priv *dp_priv;
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipuv3-crtc.c linux-linaro-stable-mx6/drivers/staging/imx-drm/ipuv3-crtc.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipuv3-crtc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipuv3-crtc.c 2014-05-15 20:34:05.758069778 +0200
+@@ -17,44 +17,36 @@
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
++#include <linux/component.h>
+ #include <linux/module.h>
+ #include <linux/export.h>
+ #include <linux/device.h>
+ #include <linux/platform_device.h>
+ #include <drm/drmP.h>
+-#include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <linux/fb.h>
+ #include <linux/clk.h>
++#include <linux/errno.h>
+ #include <drm/drm_gem_cma_helper.h>
+ #include <drm/drm_fb_cma_helper.h>
+
+ #include "ipu-v3/imx-ipu-v3.h"
+ #include "imx-drm.h"
++#include "ipuv3-plane.h"
+
+ #define DRIVER_DESC "i.MX IPUv3 Graphics"
+
+-struct ipu_framebuffer {
+- struct drm_framebuffer base;
+- void *virt;
+- dma_addr_t phys;
+- size_t len;
+-};
+-
+ struct ipu_crtc {
+- struct drm_fb_helper fb_helper;
+- struct ipu_framebuffer ifb;
+- int num_crtcs;
+ struct device *dev;
+ struct drm_crtc base;
+ struct imx_drm_crtc *imx_crtc;
+- struct ipuv3_channel *ipu_ch;
++
++ /* plane[0] is the full plane, plane[1] is the partial plane */
++ struct ipu_plane *plane[2];
++
+ struct ipu_dc *dc;
+- struct ipu_dp *dp;
+- struct dmfc_channel *dmfc;
+ struct ipu_di *di;
+ int enabled;
+- struct ipu_priv *ipu_priv;
+ struct drm_pending_vblank_event *page_flip_event;
+ struct drm_framebuffer *newfb;
+ int irq;
+@@ -66,35 +58,14 @@
+
+ #define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
+
+-static int calc_vref(struct drm_display_mode *mode)
+-{
+- unsigned long htotal, vtotal;
+-
+- htotal = mode->htotal;
+- vtotal = mode->vtotal;
+-
+- if (!htotal || !vtotal)
+- return 60;
+-
+- return mode->clock * 1000 / vtotal / htotal;
+-}
+-
+-static int calc_bandwidth(struct drm_display_mode *mode, unsigned int vref)
+-{
+- return mode->hdisplay * mode->vdisplay * vref;
+-}
+-
+ static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
+ {
+ if (ipu_crtc->enabled)
+ return;
+
+ ipu_di_enable(ipu_crtc->di);
+- ipu_dmfc_enable_channel(ipu_crtc->dmfc);
+- ipu_idmac_enable_channel(ipu_crtc->ipu_ch);
+ ipu_dc_enable_channel(ipu_crtc->dc);
+- if (ipu_crtc->dp)
+- ipu_dp_enable_channel(ipu_crtc->dp);
++ ipu_plane_enable(ipu_crtc->plane[0]);
+
+ ipu_crtc->enabled = 1;
+ }
+@@ -104,11 +75,8 @@
+ if (!ipu_crtc->enabled)
+ return;
+
+- if (ipu_crtc->dp)
+- ipu_dp_disable_channel(ipu_crtc->dp);
++ ipu_plane_disable(ipu_crtc->plane[0]);
+ ipu_dc_disable_channel(ipu_crtc->dc);
+- ipu_idmac_disable_channel(ipu_crtc->ipu_ch);
+- ipu_dmfc_disable_channel(ipu_crtc->dmfc);
+ ipu_di_disable(ipu_crtc->di);
+
+ ipu_crtc->enabled = 0;
+@@ -134,7 +102,8 @@
+
+ static int ipu_page_flip(struct drm_crtc *crtc,
+ struct drm_framebuffer *fb,
+- struct drm_pending_vblank_event *event)
++ struct drm_pending_vblank_event *event,
++ uint32_t page_flip_flags)
+ {
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+ int ret;
+@@ -152,6 +121,7 @@
+
+ ipu_crtc->newfb = fb;
+ ipu_crtc->page_flip_event = event;
++ crtc->fb = fb;
+
+ return 0;
+ }
+@@ -162,33 +132,6 @@
+ .page_flip = ipu_page_flip,
+ };
+
+-static int ipu_drm_set_base(struct drm_crtc *crtc, int x, int y)
+-{
+- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+- struct drm_gem_cma_object *cma_obj;
+- struct drm_framebuffer *fb = crtc->fb;
+- unsigned long phys;
+-
+- cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
+- if (!cma_obj) {
+- DRM_LOG_KMS("entry is null.\n");
+- return -EFAULT;
+- }
+-
+- phys = cma_obj->paddr;
+- phys += x * (fb->bits_per_pixel >> 3);
+- phys += y * fb->pitches[0];
+-
+- dev_dbg(ipu_crtc->dev, "%s: phys: 0x%lx\n", __func__, phys);
+- dev_dbg(ipu_crtc->dev, "%s: xy: %dx%d\n", __func__, x, y);
+-
+- ipu_cpmem_set_stride(ipu_get_cpmem(ipu_crtc->ipu_ch), fb->pitches[0]);
+- ipu_cpmem_set_buffer(ipu_get_cpmem(ipu_crtc->ipu_ch),
+- 0, phys);
+-
+- return 0;
+-}
+-
+ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *orig_mode,
+ struct drm_display_mode *mode,
+@@ -196,41 +139,15 @@
+ struct drm_framebuffer *old_fb)
+ {
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+- struct drm_framebuffer *fb = ipu_crtc->base.fb;
+ int ret;
+ struct ipu_di_signal_cfg sig_cfg = {};
+ u32 out_pixel_fmt;
+- struct ipu_ch_param __iomem *cpmem = ipu_get_cpmem(ipu_crtc->ipu_ch);
+- int bpp;
+- u32 v4l2_fmt;
+
+ dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
+ mode->hdisplay);
+ dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
+ mode->vdisplay);
+
+- ipu_ch_param_zero(cpmem);
+-
+- switch (fb->pixel_format) {
+- case DRM_FORMAT_XRGB8888:
+- case DRM_FORMAT_ARGB8888:
+- v4l2_fmt = V4L2_PIX_FMT_RGB32;
+- bpp = 32;
+- break;
+- case DRM_FORMAT_RGB565:
+- v4l2_fmt = V4L2_PIX_FMT_RGB565;
+- bpp = 16;
+- break;
+- case DRM_FORMAT_RGB888:
+- v4l2_fmt = V4L2_PIX_FMT_RGB24;
+- bpp = 24;
+- break;
+- default:
+- dev_err(ipu_crtc->dev, "unsupported pixel format 0x%08x\n",
+- fb->pixel_format);
+- return -EINVAL;
+- }
+-
+ out_pixel_fmt = ipu_crtc->interface_pix_fmt;
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+@@ -241,7 +158,7 @@
+ sig_cfg.Vsync_pol = 1;
+
+ sig_cfg.enable_pol = 1;
+- sig_cfg.clk_pol = 0;
++ sig_cfg.clk_pol = 1;
+ sig_cfg.width = mode->hdisplay;
+ sig_cfg.height = mode->vdisplay;
+ sig_cfg.pixel_fmt = out_pixel_fmt;
+@@ -260,18 +177,6 @@
+ sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
+ sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
+
+- if (ipu_crtc->dp) {
+- ret = ipu_dp_setup_channel(ipu_crtc->dp, IPUV3_COLORSPACE_RGB,
+- IPUV3_COLORSPACE_RGB);
+- if (ret) {
+- dev_err(ipu_crtc->dev,
+- "initializing display processor failed with %d\n",
+- ret);
+- return ret;
+- }
+- ipu_dp_set_global_alpha(ipu_crtc->dp, 1, 0, 1);
+- }
+-
+ ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
+ out_pixel_fmt, mode->hdisplay);
+ if (ret) {
+@@ -288,30 +193,9 @@
+ return ret;
+ }
+
+- ipu_cpmem_set_resolution(cpmem, mode->hdisplay, mode->vdisplay);
+- ipu_cpmem_set_fmt(cpmem, v4l2_fmt);
+- ipu_cpmem_set_high_priority(ipu_crtc->ipu_ch);
+-
+- ret = ipu_dmfc_init_channel(ipu_crtc->dmfc, mode->hdisplay);
+- if (ret) {
+- dev_err(ipu_crtc->dev,
+- "initializing dmfc channel failed with %d\n",
+- ret);
+- return ret;
+- }
+-
+- ret = ipu_dmfc_alloc_bandwidth(ipu_crtc->dmfc,
+- calc_bandwidth(mode, calc_vref(mode)), 64);
+- if (ret) {
+- dev_err(ipu_crtc->dev,
+- "allocating dmfc bandwidth failed with %d\n",
+- ret);
+- return ret;
+- }
+-
+- ipu_drm_set_base(crtc, x, y);
+-
+- return 0;
++ return ipu_plane_mode_set(ipu_crtc->plane[0], crtc, mode, crtc->fb,
++ 0, 0, mode->hdisplay, mode->vdisplay,
++ x, y, mode->hdisplay, mode->vdisplay);
+ }
+
+ static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
+@@ -334,9 +218,8 @@
+ imx_drm_handle_vblank(ipu_crtc->imx_crtc);
+
+ if (ipu_crtc->newfb) {
+- ipu_crtc->base.fb = ipu_crtc->newfb;
+ ipu_crtc->newfb = NULL;
+- ipu_drm_set_base(&ipu_crtc->base, 0, 0);
++ ipu_plane_set_base(ipu_crtc->plane[0], ipu_crtc->base.fb, 0, 0);
+ ipu_crtc_handle_pageflip(ipu_crtc);
+ }
+
+@@ -364,25 +247,16 @@
+ ipu_fb_enable(ipu_crtc);
+ }
+
+-static void ipu_crtc_load_lut(struct drm_crtc *crtc)
+-{
+-}
+-
+ static struct drm_crtc_helper_funcs ipu_helper_funcs = {
+ .dpms = ipu_crtc_dpms,
+ .mode_fixup = ipu_crtc_mode_fixup,
+ .mode_set = ipu_crtc_mode_set,
+ .prepare = ipu_crtc_prepare,
+ .commit = ipu_crtc_commit,
+- .load_lut = ipu_crtc_load_lut,
+ };
+
+ static int ipu_enable_vblank(struct drm_crtc *crtc)
+ {
+- struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+-
+- enable_irq(ipu_crtc->irq);
+-
+ return 0;
+ }
+
+@@ -390,7 +264,8 @@
+ {
+ struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
+
+- disable_irq(ipu_crtc->irq);
++ ipu_crtc->page_flip_event = NULL;
++ ipu_crtc->newfb = NULL;
+ }
+
+ static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
+@@ -409,6 +284,7 @@
+ ipu_crtc->di_clkflags = IPU_DI_CLKMODE_SYNC |
+ IPU_DI_CLKMODE_EXT;
+ break;
++ case DRM_MODE_ENCODER_TMDS:
+ case DRM_MODE_ENCODER_NONE:
+ ipu_crtc->di_clkflags = 0;
+ break;
+@@ -427,12 +303,8 @@
+
+ static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
+ {
+- if (!IS_ERR_OR_NULL(ipu_crtc->ipu_ch))
+- ipu_idmac_put(ipu_crtc->ipu_ch);
+- if (!IS_ERR_OR_NULL(ipu_crtc->dmfc))
+- ipu_dmfc_put(ipu_crtc->dmfc);
+- if (!IS_ERR_OR_NULL(ipu_crtc->dp))
+- ipu_dp_put(ipu_crtc->dp);
++ if (!IS_ERR_OR_NULL(ipu_crtc->dc))
++ ipu_dc_put(ipu_crtc->dc);
+ if (!IS_ERR_OR_NULL(ipu_crtc->di))
+ ipu_di_put(ipu_crtc->di);
+ }
+@@ -443,32 +315,12 @@
+ struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
+ int ret;
+
+- ipu_crtc->ipu_ch = ipu_idmac_get(ipu, pdata->dma[0]);
+- if (IS_ERR(ipu_crtc->ipu_ch)) {
+- ret = PTR_ERR(ipu_crtc->ipu_ch);
+- goto err_out;
+- }
+-
+ ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
+ if (IS_ERR(ipu_crtc->dc)) {
+ ret = PTR_ERR(ipu_crtc->dc);
+ goto err_out;
+ }
+
+- ipu_crtc->dmfc = ipu_dmfc_get(ipu, pdata->dma[0]);
+- if (IS_ERR(ipu_crtc->dmfc)) {
+- ret = PTR_ERR(ipu_crtc->dmfc);
+- goto err_out;
+- }
+-
+- if (pdata->dp >= 0) {
+- ipu_crtc->dp = ipu_dp_get(ipu, pdata->dp);
+- if (IS_ERR(ipu_crtc->dp)) {
+- ret = PTR_ERR(ipu_crtc->dp);
+- goto err_out;
+- }
+- }
+-
+ ipu_crtc->di = ipu_di_get(ipu, pdata->di);
+ if (IS_ERR(ipu_crtc->di)) {
+ ret = PTR_ERR(ipu_crtc->di);
+@@ -483,10 +335,12 @@
+ }
+
+ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
+- struct ipu_client_platformdata *pdata)
++ struct ipu_client_platformdata *pdata, struct drm_device *drm)
+ {
+ struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
++ int dp = -EINVAL;
+ int ret;
++ int id;
+
+ ret = ipu_get_resources(ipu_crtc, pdata);
+ if (ret) {
+@@ -495,68 +349,111 @@
+ return ret;
+ }
+
+- ret = imx_drm_add_crtc(&ipu_crtc->base,
+- &ipu_crtc->imx_crtc,
+- &ipu_crtc_helper_funcs, THIS_MODULE,
+- ipu_crtc->dev->parent->of_node, pdata->di);
++ ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
++ &ipu_crtc_helper_funcs, ipu_crtc->dev->parent->of_node,
++ pdata->ipu, pdata->di);
+ if (ret) {
+ dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
+ goto err_put_resources;
+ }
+
+- ipu_crtc->irq = ipu_idmac_channel_irq(ipu, ipu_crtc->ipu_ch,
+- IPU_IRQ_EOF);
++ if (pdata->dp >= 0)
++ dp = IPU_DP_FLOW_SYNC_BG;
++ id = imx_drm_crtc_id(ipu_crtc->imx_crtc);
++ ipu_crtc->plane[0] = ipu_plane_init(ipu_crtc->base.dev, ipu,
++ pdata->dma[0], dp, BIT(id), true);
++ ret = ipu_plane_get_resources(ipu_crtc->plane[0]);
++ if (ret) {
++ dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n",
++ ret);
++ goto err_remove_crtc;
++ }
++
++ /* If this crtc is using the DP, add an overlay plane */
++ if (pdata->dp >= 0 && pdata->dma[1] > 0) {
++ ipu_crtc->plane[1] = ipu_plane_init(ipu_crtc->base.dev, ipu,
++ pdata->dma[1],
++ IPU_DP_FLOW_SYNC_FG,
++ BIT(id), false);
++ if (IS_ERR(ipu_crtc->plane[1]))
++ ipu_crtc->plane[1] = NULL;
++ }
++
++ ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]);
+ ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
+ "imx_drm", ipu_crtc);
+ if (ret < 0) {
+ dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
+- goto err_put_resources;
++ goto err_put_plane_res;
+ }
+
+- disable_irq(ipu_crtc->irq);
+-
+ return 0;
+
++err_put_plane_res:
++ ipu_plane_put_resources(ipu_crtc->plane[0]);
++err_remove_crtc:
++ imx_drm_remove_crtc(ipu_crtc->imx_crtc);
+ err_put_resources:
+ ipu_put_resources(ipu_crtc);
+
+ return ret;
+ }
+
+-static int ipu_drm_probe(struct platform_device *pdev)
++static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
+ {
+- struct ipu_client_platformdata *pdata = pdev->dev.platform_data;
++ struct ipu_client_platformdata *pdata = dev->platform_data;
++ struct drm_device *drm = data;
+ struct ipu_crtc *ipu_crtc;
+ int ret;
+
+- if (!pdata)
+- return -EINVAL;
+-
+- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+-
+- ipu_crtc = devm_kzalloc(&pdev->dev, sizeof(*ipu_crtc), GFP_KERNEL);
++ ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL);
+ if (!ipu_crtc)
+ return -ENOMEM;
+
+- ipu_crtc->dev = &pdev->dev;
++ ipu_crtc->dev = dev;
+
+- ret = ipu_crtc_init(ipu_crtc, pdata);
++ ret = ipu_crtc_init(ipu_crtc, pdata, drm);
+ if (ret)
+ return ret;
+
+- platform_set_drvdata(pdev, ipu_crtc);
++ dev_set_drvdata(dev, ipu_crtc);
+
+ return 0;
+ }
+
+-static int ipu_drm_remove(struct platform_device *pdev)
++static void ipu_drm_unbind(struct device *dev, struct device *master,
++ void *data)
+ {
+- struct ipu_crtc *ipu_crtc = platform_get_drvdata(pdev);
++ struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev);
+
+ imx_drm_remove_crtc(ipu_crtc->imx_crtc);
+
++ ipu_plane_put_resources(ipu_crtc->plane[0]);
+ ipu_put_resources(ipu_crtc);
++}
+
++static const struct component_ops ipu_crtc_ops = {
++ .bind = ipu_drm_bind,
++ .unbind = ipu_drm_unbind,
++};
++
++static int ipu_drm_probe(struct platform_device *pdev)
++{
++ int ret;
++
++ if (!pdev->dev.platform_data)
++ return -EINVAL;
++
++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++ if (ret)
++ return ret;
++
++ return component_add(&pdev->dev, &ipu_crtc_ops);
++}
++
++static int ipu_drm_remove(struct platform_device *pdev)
++{
++ component_del(&pdev->dev, &ipu_crtc_ops);
+ return 0;
+ }
+
+@@ -572,3 +469,4 @@
+ MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+ MODULE_DESCRIPTION(DRIVER_DESC);
+ MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-ipuv3-crtc");
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipuv3-plane.c linux-linaro-stable-mx6/drivers/staging/imx-drm/ipuv3-plane.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipuv3-plane.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipuv3-plane.c 2014-05-15 20:34:05.758069778 +0200
+@@ -0,0 +1,375 @@
++/*
++ * i.MX IPUv3 DP Overlay Planes
++ *
++ * Copyright (C) 2013 Philipp Zabel, Pengutronix
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <drm/drmP.h>
++#include <drm/drm_fb_cma_helper.h>
++#include <drm/drm_gem_cma_helper.h>
++
++#include "ipu-v3/imx-ipu-v3.h"
++#include "ipuv3-plane.h"
++
++#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
++
++static const uint32_t ipu_plane_formats[] = {
++ DRM_FORMAT_XRGB1555,
++ DRM_FORMAT_XBGR1555,
++ DRM_FORMAT_ARGB8888,
++ DRM_FORMAT_XRGB8888,
++ DRM_FORMAT_ABGR8888,
++ DRM_FORMAT_XBGR8888,
++ DRM_FORMAT_YUYV,
++ DRM_FORMAT_YVYU,
++ DRM_FORMAT_YUV420,
++ DRM_FORMAT_YVU420,
++};
++
++int ipu_plane_irq(struct ipu_plane *ipu_plane)
++{
++ return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
++ IPU_IRQ_EOF);
++}
++
++static int calc_vref(struct drm_display_mode *mode)
++{
++ unsigned long htotal, vtotal;
++
++ htotal = mode->htotal;
++ vtotal = mode->vtotal;
++
++ if (!htotal || !vtotal)
++ return 60;
++
++ return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
++}
++
++static inline int calc_bandwidth(int width, int height, unsigned int vref)
++{
++ return width * height * vref;
++}
++
++int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
++ int x, int y)
++{
++ struct ipu_ch_param __iomem *cpmem;
++ struct drm_gem_cma_object *cma_obj;
++
++ cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
++ if (!cma_obj) {
++ DRM_LOG_KMS("entry is null.\n");
++ return -EFAULT;
++ }
++
++ dev_dbg(ipu_plane->base.dev->dev, "phys = 0x%x, x = %d, y = %d",
++ cma_obj->paddr, x, y);
++
++ cpmem = ipu_get_cpmem(ipu_plane->ipu_ch);
++ ipu_cpmem_set_stride(cpmem, fb->pitches[0]);
++ ipu_cpmem_set_buffer(cpmem, 0, cma_obj->paddr + fb->offsets[0] +
++ fb->pitches[0] * y + x);
++
++ return 0;
++}
++
++int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
++ struct drm_display_mode *mode,
++ struct drm_framebuffer *fb, int crtc_x, int crtc_y,
++ unsigned int crtc_w, unsigned int crtc_h,
++ uint32_t src_x, uint32_t src_y,
++ uint32_t src_w, uint32_t src_h)
++{
++ struct ipu_ch_param __iomem *cpmem;
++ struct device *dev = ipu_plane->base.dev->dev;
++ int ret;
++
++ /* no scaling */
++ if (src_w != crtc_w || src_h != crtc_h)
++ return -EINVAL;
++
++ /* clip to crtc bounds */
++ if (crtc_x < 0) {
++ if (-crtc_x > crtc_w)
++ return -EINVAL;
++ src_x += -crtc_x;
++ src_w -= -crtc_x;
++ crtc_w -= -crtc_x;
++ crtc_x = 0;
++ }
++ if (crtc_y < 0) {
++ if (-crtc_y > crtc_h)
++ return -EINVAL;
++ src_y += -crtc_y;
++ src_h -= -crtc_y;
++ crtc_h -= -crtc_y;
++ crtc_y = 0;
++ }
++ if (crtc_x + crtc_w > mode->hdisplay) {
++ if (crtc_x > mode->hdisplay)
++ return -EINVAL;
++ crtc_w = mode->hdisplay - crtc_x;
++ src_w = crtc_w;
++ }
++ if (crtc_y + crtc_h > mode->vdisplay) {
++ if (crtc_y > mode->vdisplay)
++ return -EINVAL;
++ crtc_h = mode->vdisplay - crtc_y;
++ src_h = crtc_h;
++ }
++ /* full plane minimum width is 13 pixels */
++ if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
++ return -EINVAL;
++ if (crtc_h < 2)
++ return -EINVAL;
++
++ switch (ipu_plane->dp_flow) {
++ case IPU_DP_FLOW_SYNC_BG:
++ ret = ipu_dp_setup_channel(ipu_plane->dp,
++ IPUV3_COLORSPACE_RGB,
++ IPUV3_COLORSPACE_RGB);
++ if (ret) {
++ dev_err(dev,
++ "initializing display processor failed with %d\n",
++ ret);
++ return ret;
++ }
++ ipu_dp_set_global_alpha(ipu_plane->dp, 1, 0, 1);
++ break;
++ case IPU_DP_FLOW_SYNC_FG:
++ ipu_dp_setup_channel(ipu_plane->dp,
++ ipu_drm_fourcc_to_colorspace(fb->pixel_format),
++ IPUV3_COLORSPACE_UNKNOWN);
++ ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
++ break;
++ }
++
++ ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
++ if (ret) {
++ dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
++ return ret;
++ }
++
++ ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
++ calc_bandwidth(crtc_w, crtc_h,
++ calc_vref(mode)), 64);
++ if (ret) {
++ dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
++ return ret;
++ }
++
++ cpmem = ipu_get_cpmem(ipu_plane->ipu_ch);
++ ipu_ch_param_zero(cpmem);
++ ipu_cpmem_set_resolution(cpmem, src_w, src_h);
++ ret = ipu_cpmem_set_fmt(cpmem, fb->pixel_format);
++ if (ret < 0) {
++ dev_err(dev, "unsupported pixel format 0x%08x\n",
++ fb->pixel_format);
++ return ret;
++ }
++ ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
++
++ ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
++{
++ if (!IS_ERR_OR_NULL(ipu_plane->dp))
++ ipu_dp_put(ipu_plane->dp);
++ if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
++ ipu_dmfc_put(ipu_plane->dmfc);
++ if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
++ ipu_idmac_put(ipu_plane->ipu_ch);
++}
++
++int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
++{
++ int ret;
++
++ ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
++ if (IS_ERR(ipu_plane->ipu_ch)) {
++ ret = PTR_ERR(ipu_plane->ipu_ch);
++ DRM_ERROR("failed to get idmac channel: %d\n", ret);
++ return ret;
++ }
++
++ ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
++ if (IS_ERR(ipu_plane->dmfc)) {
++ ret = PTR_ERR(ipu_plane->dmfc);
++ DRM_ERROR("failed to get dmfc: ret %d\n", ret);
++ goto err_out;
++ }
++
++ if (ipu_plane->dp_flow >= 0) {
++ ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
++ if (IS_ERR(ipu_plane->dp)) {
++ ret = PTR_ERR(ipu_plane->dp);
++ DRM_ERROR("failed to get dp flow: %d\n", ret);
++ goto err_out;
++ }
++ }
++
++ return 0;
++err_out:
++ ipu_plane_put_resources(ipu_plane);
++
++ return ret;
++}
++
++void ipu_plane_enable(struct ipu_plane *ipu_plane)
++{
++ ipu_dmfc_enable_channel(ipu_plane->dmfc);
++ ipu_idmac_enable_channel(ipu_plane->ipu_ch);
++ if (ipu_plane->dp)
++ ipu_dp_enable_channel(ipu_plane->dp);
++
++ ipu_plane->enabled = true;
++}
++
++void ipu_plane_disable(struct ipu_plane *ipu_plane)
++{
++ ipu_plane->enabled = false;
++
++ ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
++
++ if (ipu_plane->dp)
++ ipu_dp_disable_channel(ipu_plane->dp);
++ ipu_idmac_disable_channel(ipu_plane->ipu_ch);
++ ipu_dmfc_disable_channel(ipu_plane->dmfc);
++}
++
++static void ipu_plane_dpms(struct ipu_plane *ipu_plane, int mode)
++{
++ bool enable;
++
++ DRM_DEBUG_KMS("mode = %d", mode);
++
++ enable = (mode == DRM_MODE_DPMS_ON);
++
++ if (enable == ipu_plane->enabled)
++ return;
++
++ if (enable) {
++ ipu_plane_enable(ipu_plane);
++ } else {
++ ipu_plane_disable(ipu_plane);
++
++ ipu_idmac_put(ipu_plane->ipu_ch);
++ ipu_dmfc_put(ipu_plane->dmfc);
++ ipu_dp_put(ipu_plane->dp);
++ }
++}
++
++/*
++ * drm_plane API
++ */
++
++static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
++ struct drm_framebuffer *fb, int crtc_x, int crtc_y,
++ unsigned int crtc_w, unsigned int crtc_h,
++ uint32_t src_x, uint32_t src_y,
++ uint32_t src_w, uint32_t src_h)
++{
++ struct ipu_plane *ipu_plane = to_ipu_plane(plane);
++ int ret = 0;
++
++ DRM_DEBUG_KMS("plane - %p\n", plane);
++
++ if (!ipu_plane->enabled)
++ ret = ipu_plane_get_resources(ipu_plane);
++ if (ret < 0)
++ return ret;
++
++ ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
++ crtc_x, crtc_y, crtc_w, crtc_h,
++ src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16);
++ if (ret < 0) {
++ ipu_plane_put_resources(ipu_plane);
++ return ret;
++ }
++
++ if (crtc != plane->crtc)
++ dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
++ plane->crtc, crtc);
++ plane->crtc = crtc;
++
++ ipu_plane_dpms(ipu_plane, DRM_MODE_DPMS_ON);
++
++ return 0;
++}
++
++static int ipu_disable_plane(struct drm_plane *plane)
++{
++ struct ipu_plane *ipu_plane = to_ipu_plane(plane);
++
++ DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
++
++ ipu_plane_dpms(ipu_plane, DRM_MODE_DPMS_OFF);
++
++ ipu_plane_put_resources(ipu_plane);
++
++ return 0;
++}
++
++static void ipu_plane_destroy(struct drm_plane *plane)
++{
++ struct ipu_plane *ipu_plane = to_ipu_plane(plane);
++
++ DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
++
++ ipu_disable_plane(plane);
++ drm_plane_cleanup(plane);
++ kfree(ipu_plane);
++}
++
++static struct drm_plane_funcs ipu_plane_funcs = {
++ .update_plane = ipu_update_plane,
++ .disable_plane = ipu_disable_plane,
++ .destroy = ipu_plane_destroy,
++};
++
++struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
++ int dma, int dp, unsigned int possible_crtcs,
++ bool priv)
++{
++ struct ipu_plane *ipu_plane;
++ int ret;
++
++ DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
++ dma, dp, possible_crtcs);
++
++ ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
++ if (!ipu_plane) {
++ DRM_ERROR("failed to allocate plane\n");
++ return ERR_PTR(-ENOMEM);
++ }
++
++ ipu_plane->ipu = ipu;
++ ipu_plane->dma = dma;
++ ipu_plane->dp_flow = dp;
++
++ ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
++ &ipu_plane_funcs, ipu_plane_formats,
++ ARRAY_SIZE(ipu_plane_formats),
++ priv);
++ if (ret) {
++ DRM_ERROR("failed to initialize plane\n");
++ kfree(ipu_plane);
++ return ERR_PTR(ret);
++ }
++
++ return ipu_plane;
++}
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/ipuv3-plane.h linux-linaro-stable-mx6/drivers/staging/imx-drm/ipuv3-plane.h
+--- linux-3.10.30.orig/drivers/staging/imx-drm/ipuv3-plane.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/ipuv3-plane.h 2014-05-15 20:34:05.758069778 +0200
+@@ -0,0 +1,55 @@
++#ifndef __IPUV3_PLANE_H__
++#define __IPUV3_PLANE_H__
++
++#include <drm/drm_crtc.h> /* drm_plane */
++
++struct drm_plane;
++struct drm_device;
++struct ipu_soc;
++struct drm_crtc;
++struct drm_framebuffer;
++
++struct ipuv3_channel;
++struct dmfc_channel;
++struct ipu_dp;
++
++struct ipu_plane {
++ struct drm_plane base;
++
++ struct ipu_soc *ipu;
++ struct ipuv3_channel *ipu_ch;
++ struct dmfc_channel *dmfc;
++ struct ipu_dp *dp;
++
++ int dma;
++ int dp_flow;
++
++ int x;
++ int y;
++
++ bool enabled;
++};
++
++struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
++ int dma, int dp, unsigned int possible_crtcs,
++ bool priv);
++
++/* Init IDMAC, DMFC, DP */
++int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
++ struct drm_display_mode *mode,
++ struct drm_framebuffer *fb, int crtc_x, int crtc_y,
++ unsigned int crtc_w, unsigned int crtc_h,
++ uint32_t src_x, uint32_t src_y, uint32_t src_w,
++ uint32_t src_h);
++
++void ipu_plane_enable(struct ipu_plane *plane);
++void ipu_plane_disable(struct ipu_plane *plane);
++int ipu_plane_set_base(struct ipu_plane *plane, struct drm_framebuffer *fb,
++ int x, int y);
++
++int ipu_plane_get_resources(struct ipu_plane *plane);
++void ipu_plane_put_resources(struct ipu_plane *plane);
++
++int ipu_plane_irq(struct ipu_plane *plane);
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/Kconfig linux-linaro-stable-mx6/drivers/staging/imx-drm/Kconfig
+--- linux-3.10.30.orig/drivers/staging/imx-drm/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/Kconfig 2014-05-15 20:34:05.754069749 +0200
+@@ -1,6 +1,7 @@
+ config DRM_IMX
+ tristate "DRM Support for Freescale i.MX"
+ select DRM_KMS_HELPER
++ select DRM_KMS_FB_HELPER
+ select VIDEOMODE_HELPERS
+ select DRM_GEM_CMA_HELPER
+ select DRM_KMS_CMA_HELPER
+@@ -15,7 +16,7 @@
+ help
+ The DRM framework can provide a legacy /dev/fb0 framebuffer
+ for your device. This is necessary to get a framebuffer console
+- and also for appplications using the legacy framebuffer API
++ and also for applications using the legacy framebuffer API
+
+ config DRM_IMX_PARALLEL_DISPLAY
+ tristate "Support for parallel displays"
+@@ -30,6 +31,13 @@
+ Choose this to enable the internal Television Encoder (TVe)
+ found on i.MX53 processors.
+
++config DRM_IMX_LDB
++ tristate "Support for LVDS displays"
++ depends on DRM_IMX && MFD_SYSCON
++ help
++ Choose this to enable the internal LVDS Display Bridge (LDB)
++ found on i.MX53 and i.MX6 processors.
++
+ config DRM_IMX_IPUV3_CORE
+ tristate "IPUv3 core support"
+ depends on DRM_IMX
+@@ -45,3 +53,17 @@
+ depends on DRM_IMX_IPUV3_CORE
+ help
+ Choose this if you have a i.MX5 or i.MX6 processor.
++
++config DRM_IMX_HDMI
++ tristate "Freescale i.MX DRM HDMI "
++ depends on DRM_IMX
++ help
++ Choose this if you want to use HDMI on i.MX6.
++
++config DRM_DW_HDMI_CEC
++ tristate "Synopsis Designware CEC interface"
++ depends on DRM_IMX_HDMI != n
++ help
++ Support the CEC interface which is part of the Synposis
++ Designware HDMI block. This is used in conjunction with
++ the i.MX HDMI driver.
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/Makefile linux-linaro-stable-mx6/drivers/staging/imx-drm/Makefile
+--- linux-3.10.30.orig/drivers/staging/imx-drm/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/Makefile 2014-05-15 20:34:05.754069749 +0200
+@@ -1,10 +1,15 @@
+
+-imxdrm-objs := imx-drm-core.o imx-fb.o
++imxdrm-objs := imx-drm-core.o
++imxhdmi-objs := imx-hdmi.o dw-hdmi-audio.o
+
+ obj-$(CONFIG_DRM_IMX) += imxdrm.o
+
+ obj-$(CONFIG_DRM_IMX_PARALLEL_DISPLAY) += parallel-display.o
+ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
+-obj-$(CONFIG_DRM_IMX_FB_HELPER) += imx-fbdev.o
++obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
+ obj-$(CONFIG_DRM_IMX_IPUV3_CORE) += ipu-v3/
+-obj-$(CONFIG_DRM_IMX_IPUV3) += ipuv3-crtc.o
++
++imx-ipuv3-crtc-objs := ipuv3-crtc.o ipuv3-plane.o
++obj-$(CONFIG_DRM_IMX_IPUV3) += imx-ipuv3-crtc.o
++obj-$(CONFIG_DRM_IMX_HDMI) += imxhdmi.o
++obj-$(CONFIG_DRM_DW_HDMI_CEC) += dw-hdmi-cec.o
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/parallel-display.c linux-linaro-stable-mx6/drivers/staging/imx-drm/parallel-display.c
+--- linux-3.10.30.orig/drivers/staging/imx-drm/parallel-display.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/parallel-display.c 2014-05-15 20:34:05.758069778 +0200
+@@ -18,12 +18,12 @@
+ * MA 02110-1301, USA.
+ */
+
++#include <linux/component.h>
+ #include <linux/module.h>
+ #include <drm/drmP.h>
+ #include <drm/drm_fb_helper.h>
+ #include <drm/drm_crtc_helper.h>
+ #include <linux/videodev2.h>
+-#include <linux/pinctrl/consumer.h>
+
+ #include "imx-drm.h"
+
+@@ -32,9 +32,7 @@
+
+ struct imx_parallel_display {
+ struct drm_connector connector;
+- struct imx_drm_connector *imx_drm_connector;
+ struct drm_encoder encoder;
+- struct imx_drm_encoder *imx_drm_encoder;
+ struct device *dev;
+ void *edid;
+ int edid_len;
+@@ -49,11 +47,6 @@
+ return connector_status_connected;
+ }
+
+-static void imx_pd_connector_destroy(struct drm_connector *connector)
+-{
+- /* do not free here */
+-}
+-
+ static int imx_pd_connector_get_modes(struct drm_connector *connector)
+ {
+ struct imx_parallel_display *imxpd = con_to_imxpd(connector);
+@@ -85,12 +78,6 @@
+ return num_modes;
+ }
+
+-static int imx_pd_connector_mode_valid(struct drm_connector *connector,
+- struct drm_display_mode *mode)
+-{
+- return 0;
+-}
+-
+ static struct drm_encoder *imx_pd_connector_best_encoder(
+ struct drm_connector *connector)
+ {
+@@ -114,8 +101,7 @@
+ {
+ struct imx_parallel_display *imxpd = enc_to_imxpd(encoder);
+
+- imx_drm_crtc_panel_format(encoder->crtc, DRM_MODE_ENCODER_NONE,
+- imxpd->interface_pix_fmt);
++ imx_drm_panel_format(encoder, imxpd->interface_pix_fmt);
+ }
+
+ static void imx_pd_encoder_commit(struct drm_encoder *encoder)
+@@ -132,26 +118,21 @@
+ {
+ }
+
+-static void imx_pd_encoder_destroy(struct drm_encoder *encoder)
+-{
+- /* do not free here */
+-}
+-
+ static struct drm_connector_funcs imx_pd_connector_funcs = {
+ .dpms = drm_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = imx_pd_connector_detect,
+- .destroy = imx_pd_connector_destroy,
++ .destroy = imx_drm_connector_destroy,
+ };
+
+ static struct drm_connector_helper_funcs imx_pd_connector_helper_funcs = {
+ .get_modes = imx_pd_connector_get_modes,
+ .best_encoder = imx_pd_connector_best_encoder,
+- .mode_valid = imx_pd_connector_mode_valid,
++ .mode_valid = imx_drm_connector_mode_valid,
+ };
+
+ static struct drm_encoder_funcs imx_pd_encoder_funcs = {
+- .destroy = imx_pd_encoder_destroy,
++ .destroy = imx_drm_encoder_destroy,
+ };
+
+ static struct drm_encoder_helper_funcs imx_pd_encoder_helper_funcs = {
+@@ -163,63 +144,45 @@
+ .disable = imx_pd_encoder_disable,
+ };
+
+-static int imx_pd_register(struct imx_parallel_display *imxpd)
++static int imx_pd_register(struct drm_device *drm,
++ struct imx_parallel_display *imxpd)
+ {
+ int ret;
+
+- drm_mode_connector_attach_encoder(&imxpd->connector, &imxpd->encoder);
+-
+- imxpd->connector.funcs = &imx_pd_connector_funcs;
+- imxpd->encoder.funcs = &imx_pd_encoder_funcs;
+-
+- imxpd->encoder.encoder_type = DRM_MODE_ENCODER_NONE;
+- imxpd->connector.connector_type = DRM_MODE_CONNECTOR_VGA;
++ ret = imx_drm_encoder_parse_of(drm, &imxpd->encoder,
++ imxpd->dev->of_node);
++ if (ret)
++ return ret;
+
+ drm_encoder_helper_add(&imxpd->encoder, &imx_pd_encoder_helper_funcs);
+- ret = imx_drm_add_encoder(&imxpd->encoder, &imxpd->imx_drm_encoder,
+- THIS_MODULE);
+- if (ret) {
+- dev_err(imxpd->dev, "adding encoder failed with %d\n", ret);
+- return ret;
+- }
++ drm_encoder_init(drm, &imxpd->encoder, &imx_pd_encoder_funcs,
++ DRM_MODE_ENCODER_NONE);
+
+ drm_connector_helper_add(&imxpd->connector,
+ &imx_pd_connector_helper_funcs);
++ drm_connector_init(drm, &imxpd->connector, &imx_pd_connector_funcs,
++ DRM_MODE_CONNECTOR_VGA);
+
+- ret = imx_drm_add_connector(&imxpd->connector,
+- &imxpd->imx_drm_connector, THIS_MODULE);
+- if (ret) {
+- imx_drm_remove_encoder(imxpd->imx_drm_encoder);
+- dev_err(imxpd->dev, "adding connector failed with %d\n", ret);
+- return ret;
+- }
++ drm_mode_connector_attach_encoder(&imxpd->connector, &imxpd->encoder);
+
+ imxpd->connector.encoder = &imxpd->encoder;
+
+ return 0;
+ }
+
+-static int imx_pd_probe(struct platform_device *pdev)
++static int imx_pd_bind(struct device *dev, struct device *master, void *data)
+ {
+- struct device_node *np = pdev->dev.of_node;
++ struct drm_device *drm = data;
++ struct device_node *np = dev->of_node;
+ const u8 *edidp;
+ struct imx_parallel_display *imxpd;
+ int ret;
+ const char *fmt;
+- struct pinctrl *pinctrl;
+
+- imxpd = devm_kzalloc(&pdev->dev, sizeof(*imxpd), GFP_KERNEL);
++ imxpd = devm_kzalloc(dev, sizeof(*imxpd), GFP_KERNEL);
+ if (!imxpd)
+ return -ENOMEM;
+
+- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+- if (IS_ERR(pinctrl)) {
+- ret = PTR_ERR(pinctrl);
+- dev_warn(&pdev->dev, "pinctrl_get_select_default failed with %d",
+- ret);
+- return ret;
+- }
+-
+ edidp = of_get_property(np, "edid", &imxpd->edid_len);
+ if (edidp)
+ imxpd->edid = kmemdup(edidp, imxpd->edid_len, GFP_KERNEL);
+@@ -234,30 +197,39 @@
+ imxpd->interface_pix_fmt = V4L2_PIX_FMT_BGR666;
+ }
+
+- imxpd->dev = &pdev->dev;
++ imxpd->dev = dev;
+
+- ret = imx_pd_register(imxpd);
++ ret = imx_pd_register(drm, imxpd);
+ if (ret)
+ return ret;
+
+- ret = imx_drm_encoder_add_possible_crtcs(imxpd->imx_drm_encoder, np);
+-
+- platform_set_drvdata(pdev, imxpd);
++ dev_set_drvdata(dev, imxpd);
+
+ return 0;
+ }
+
+-static int imx_pd_remove(struct platform_device *pdev)
++static void imx_pd_unbind(struct device *dev, struct device *master,
++ void *data)
+ {
+- struct imx_parallel_display *imxpd = platform_get_drvdata(pdev);
+- struct drm_connector *connector = &imxpd->connector;
+- struct drm_encoder *encoder = &imxpd->encoder;
++ struct imx_parallel_display *imxpd = dev_get_drvdata(dev);
+
+- drm_mode_connector_detach_encoder(connector, encoder);
++ imxpd->encoder.funcs->destroy(&imxpd->encoder);
++ imxpd->connector.funcs->destroy(&imxpd->connector);
++}
++
++static const struct component_ops imx_pd_ops = {
++ .bind = imx_pd_bind,
++ .unbind = imx_pd_unbind,
++};
+
+- imx_drm_remove_connector(imxpd->imx_drm_connector);
+- imx_drm_remove_encoder(imxpd->imx_drm_encoder);
++static int imx_pd_probe(struct platform_device *pdev)
++{
++ return component_add(&pdev->dev, &imx_pd_ops);
++}
+
++static int imx_pd_remove(struct platform_device *pdev)
++{
++ component_del(&pdev->dev, &imx_pd_ops);
+ return 0;
+ }
+
+@@ -265,6 +237,7 @@
+ { .compatible = "fsl,imx-parallel-display", },
+ { /* sentinel */ }
+ };
++MODULE_DEVICE_TABLE(of, imx_pd_dt_ids);
+
+ static struct platform_driver imx_pd_driver = {
+ .probe = imx_pd_probe,
+@@ -281,3 +254,4 @@
+ MODULE_DESCRIPTION("i.MX parallel display driver");
+ MODULE_AUTHOR("Sascha Hauer, Pengutronix");
+ MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-parallel-display");
+diff -Nur linux-3.10.30.orig/drivers/staging/imx-drm/TODO linux-linaro-stable-mx6/drivers/staging/imx-drm/TODO
+--- linux-3.10.30.orig/drivers/staging/imx-drm/TODO 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/staging/imx-drm/TODO 2014-05-15 20:34:05.754069749 +0200
+@@ -6,12 +6,9 @@
+ - Factor out more code to common helper functions
+ - decide where to put the base driver. It is not specific to a subsystem
+ and would be used by DRM/KMS and media/V4L2
+-- convert irq driver to irq_domain_add_linear
+
+ Missing features (not necessarily for moving out of staging):
+
+-- Add KMS plane support for CRTC driver
+-- Add LDB (LVDS Display Bridge) support
+ - Add i.MX6 HDMI support
+ - Add support for IC (Image converter)
+ - Add support for CSI (CMOS Sensor interface)
+diff -Nur linux-3.10.30.orig/drivers/thermal/cpu_cooling.c linux-linaro-stable-mx6/drivers/thermal/cpu_cooling.c
+--- linux-3.10.30.orig/drivers/thermal/cpu_cooling.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/thermal/cpu_cooling.c 2014-05-15 20:34:07.542082630 +0200
+@@ -167,7 +167,7 @@
+ continue;
+
+ /* get the frequency order */
+- if (freq != CPUFREQ_ENTRY_INVALID && descend != -1)
++ if (freq != CPUFREQ_ENTRY_INVALID && descend == -1)
+ descend = !!(freq > table[i].frequency);
+
+ freq = table[i].frequency;
+diff -Nur linux-3.10.30.orig/drivers/thermal/device_cooling.c linux-linaro-stable-mx6/drivers/thermal/device_cooling.c
+--- linux-3.10.30.orig/drivers/thermal/device_cooling.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/thermal/device_cooling.c 2014-05-15 20:34:07.542082630 +0200
+@@ -0,0 +1,151 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/thermal.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++
++struct devfreq_cooling_device {
++ int id;
++ struct thermal_cooling_device *cool_dev;
++ unsigned int devfreq_state;
++};
++
++static DEFINE_IDR(devfreq_idr);
++static DEFINE_MUTEX(devfreq_cooling_lock);
++
++#define MAX_STATE 1
++
++static BLOCKING_NOTIFIER_HEAD(devfreq_cooling_chain_head);
++
++int register_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return blocking_notifier_chain_register(
++ &devfreq_cooling_chain_head, nb);
++}
++EXPORT_SYMBOL_GPL(register_devfreq_cooling_notifier);
++
++int unregister_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return blocking_notifier_chain_unregister(
++ &devfreq_cooling_chain_head, nb);
++}
++EXPORT_SYMBOL_GPL(unregister_devfreq_cooling_notifier);
++
++static int devfreq_cooling_notifier_call_chain(unsigned long val)
++{
++ return (blocking_notifier_call_chain(
++ &devfreq_cooling_chain_head, val, NULL)
++ == NOTIFY_BAD) ? -EINVAL : 0;
++}
++
++static int devfreq_set_cur_state(struct thermal_cooling_device *cdev,
++ unsigned long state)
++{
++ struct devfreq_cooling_device *devfreq_device = cdev->devdata;
++ int ret;
++
++ ret = devfreq_cooling_notifier_call_chain(state);
++ if (ret)
++ return -EINVAL;
++ devfreq_device->devfreq_state = state;
++
++ return 0;
++}
++
++static int devfreq_get_max_state(struct thermal_cooling_device *cdev,
++ unsigned long *state)
++{
++ *state = MAX_STATE;
++
++ return 0;
++}
++
++static int devfreq_get_cur_state(struct thermal_cooling_device *cdev,
++ unsigned long *state)
++{
++ struct devfreq_cooling_device *devfreq_device = cdev->devdata;
++
++ *state = devfreq_device->devfreq_state;
++
++ return 0;
++}
++
++static struct thermal_cooling_device_ops const devfreq_cooling_ops = {
++ .get_max_state = devfreq_get_max_state,
++ .get_cur_state = devfreq_get_cur_state,
++ .set_cur_state = devfreq_set_cur_state,
++};
++
++static int get_idr(struct idr *idr, int *id)
++{
++ int ret;
++
++ mutex_lock(&devfreq_cooling_lock);
++ ret = idr_alloc(idr, NULL, 0, 0, GFP_KERNEL);
++ mutex_unlock(&devfreq_cooling_lock);
++ if (unlikely(ret < 0))
++ return ret;
++ *id = ret;
++
++ return 0;
++}
++
++static void release_idr(struct idr *idr, int id)
++{
++ mutex_lock(&devfreq_cooling_lock);
++ idr_remove(idr, id);
++ mutex_unlock(&devfreq_cooling_lock);
++}
++
++struct thermal_cooling_device *devfreq_cooling_register(void)
++{
++ struct thermal_cooling_device *cool_dev;
++ struct devfreq_cooling_device *devfreq_dev = NULL;
++ char dev_name[THERMAL_NAME_LENGTH];
++ int ret = 0;
++
++ devfreq_dev = kzalloc(sizeof(struct devfreq_cooling_device),
++ GFP_KERNEL);
++ if (!devfreq_dev)
++ return ERR_PTR(-ENOMEM);
++
++ ret = get_idr(&devfreq_idr, &devfreq_dev->id);
++ if (ret) {
++ kfree(devfreq_dev);
++ return ERR_PTR(-EINVAL);
++ }
++
++ snprintf(dev_name, sizeof(dev_name), "thermal-devfreq-%d",
++ devfreq_dev->id);
++
++ cool_dev = thermal_cooling_device_register(dev_name, devfreq_dev,
++ &devfreq_cooling_ops);
++ if (!cool_dev) {
++ release_idr(&devfreq_idr, devfreq_dev->id);
++ kfree(devfreq_dev);
++ return ERR_PTR(-EINVAL);
++ }
++ devfreq_dev->cool_dev = cool_dev;
++ devfreq_dev->devfreq_state = 0;
++
++ return cool_dev;
++}
++EXPORT_SYMBOL_GPL(devfreq_cooling_register);
++
++void devfreq_cooling_unregister(struct thermal_cooling_device *cdev)
++{
++ struct devfreq_cooling_device *devfreq_dev = cdev->devdata;
++
++ thermal_cooling_device_unregister(devfreq_dev->cool_dev);
++ release_idr(&devfreq_idr, devfreq_dev->id);
++ kfree(devfreq_dev);
++}
++EXPORT_SYMBOL_GPL(devfreq_cooling_unregister);
+diff -Nur linux-3.10.30.orig/drivers/thermal/imx_thermal.c linux-linaro-stable-mx6/drivers/thermal/imx_thermal.c
+--- linux-3.10.30.orig/drivers/thermal/imx_thermal.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/thermal/imx_thermal.c 2014-05-15 20:34:07.586082947 +0200
+@@ -0,0 +1,471 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/clk.h>
++#include <linux/cpu_cooling.h>
++#include <linux/cpufreq.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/device_cooling.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/slab.h>
++#include <linux/thermal.h>
++#include <linux/types.h>
++
++#define REG_SET 0x4
++#define REG_CLR 0x8
++#define REG_TOG 0xc
++
++#define MISC0 0x0150
++#define MISC0_REFTOP_SELBIASOFF (1 << 3)
++
++#define TEMPSENSE0 0x0180
++#define TEMPSENSE0_TEMP_CNT_SHIFT 8
++#define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT)
++#define TEMPSENSE0_FINISHED (1 << 2)
++#define TEMPSENSE0_MEASURE_TEMP (1 << 1)
++#define TEMPSENSE0_POWER_DOWN (1 << 0)
++
++#define TEMPSENSE1 0x0190
++#define TEMPSENSE1_MEASURE_FREQ 0xffff
++
++#define OCOTP_ANA1 0x04e0
++
++/* The driver supports 1 passive trip point and 1 critical trip point */
++enum imx_thermal_trip {
++ IMX_TRIP_PASSIVE,
++ IMX_TRIP_CRITICAL,
++ IMX_TRIP_NUM,
++};
++
++/*
++ * It defines the temperature in millicelsius for passive trip point
++ * that will trigger cooling action when crossed.
++ */
++#define IMX_TEMP_PASSIVE 85000
++#define IMX_TEMP_PASSIVE_COOL_DELTA 10000
++
++/*
++ * The maximum die temperature on imx parts is 105C, let's give some cushion
++ * for noise and possible temperature rise between measurements.
++ */
++#define IMX_TEMP_CRITICAL 100000
++
++#define IMX_POLLING_DELAY 2000 /* millisecond */
++#define IMX_PASSIVE_DELAY 1000
++
++#define FACTOR0 10000000
++#define FACTOR1 15976
++#define FACTOR2 4297157
++
++struct imx_thermal_data {
++ struct thermal_zone_device *tz;
++ struct thermal_cooling_device *cdev[2];
++ enum thermal_device_mode mode;
++ struct regmap *tempmon;
++ unsigned long trip_temp[IMX_TRIP_NUM];
++ u32 c1, c2; /* See formula in imx_get_sensor_data() */
++ struct clk *thermal_clk;
++};
++
++static int imx_get_temp(struct thermal_zone_device *tz, unsigned long *temp)
++{
++ struct imx_thermal_data *data = tz->devdata;
++ struct regmap *map = data->tempmon;
++ static unsigned long last_temp;
++ unsigned int n_meas;
++ u32 val;
++
++ clk_prepare_enable(data->thermal_clk);
++ /*
++ * Every time we measure the temperature, we will power on the
++ * temperature sensor, enable measurements, take a reading,
++ * disable measurements, power off the temperature sensor.
++ */
++ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
++ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
++
++ /*
++ * According to the temp sensor designers, it may require up to ~17us
++ * to complete a measurement.
++ */
++ usleep_range(20, 50);
++
++ regmap_read(map, TEMPSENSE0, &val);
++ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
++ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
++
++ if ((val & TEMPSENSE0_FINISHED) == 0) {
++ dev_dbg(&tz->device, "temp measurement never finished\n");
++ return -EAGAIN;
++ }
++
++ n_meas = (val & TEMPSENSE0_TEMP_CNT_MASK) >> TEMPSENSE0_TEMP_CNT_SHIFT;
++
++ /* See imx_get_sensor_data() for formula derivation */
++ *temp = data->c2 - n_meas * data->c1;
++
++ if (*temp != last_temp) {
++ dev_dbg(&tz->device, "millicelsius: %ld\n", *temp);
++ last_temp = *temp;
++ }
++
++ clk_disable_unprepare(data->thermal_clk);
++
++ return 0;
++}
++
++static int imx_get_mode(struct thermal_zone_device *tz,
++ enum thermal_device_mode *mode)
++{
++ struct imx_thermal_data *data = tz->devdata;
++
++ *mode = data->mode;
++
++ return 0;
++}
++
++static int imx_set_mode(struct thermal_zone_device *tz,
++ enum thermal_device_mode mode)
++{
++ struct imx_thermal_data *data = tz->devdata;
++
++ if (mode == THERMAL_DEVICE_ENABLED) {
++ tz->polling_delay = IMX_POLLING_DELAY;
++ tz->passive_delay = IMX_PASSIVE_DELAY;
++ } else {
++ tz->polling_delay = 0;
++ tz->passive_delay = 0;
++ }
++
++ data->mode = mode;
++ thermal_zone_device_update(tz);
++
++ return 0;
++}
++
++static int imx_get_trip_type(struct thermal_zone_device *tz, int trip,
++ enum thermal_trip_type *type)
++{
++ *type = (trip == IMX_TRIP_PASSIVE) ? THERMAL_TRIP_PASSIVE :
++ THERMAL_TRIP_CRITICAL;
++ return 0;
++}
++
++static int imx_get_crit_temp(struct thermal_zone_device *tz,
++ unsigned long *temp)
++{
++ struct imx_thermal_data *data = tz->devdata;
++
++ *temp = data->trip_temp[IMX_TRIP_CRITICAL];
++
++ return 0;
++}
++
++static int imx_get_trip_temp(struct thermal_zone_device *tz, int trip,
++ unsigned long *temp)
++{
++ struct imx_thermal_data *data = tz->devdata;
++
++ *temp = data->trip_temp[trip];
++
++ return 0;
++}
++
++static int imx_set_trip_temp(struct thermal_zone_device *tz, int trip,
++ unsigned long temp)
++{
++ struct imx_thermal_data *data = tz->devdata;
++
++ data->trip_temp[trip] = temp;
++
++ return 0;
++}
++
++static int imx_bind(struct thermal_zone_device *tz,
++ struct thermal_cooling_device *cdev)
++{
++ int ret;
++
++ ret = thermal_zone_bind_cooling_device(tz, IMX_TRIP_PASSIVE, cdev,
++ THERMAL_NO_LIMIT,
++ THERMAL_NO_LIMIT);
++ if (ret) {
++ dev_err(&tz->device,
++ "binding zone %s with cdev %s failed:%d\n",
++ tz->type, cdev->type, ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int imx_unbind(struct thermal_zone_device *tz,
++ struct thermal_cooling_device *cdev)
++{
++ int ret;
++
++ ret = thermal_zone_unbind_cooling_device(tz, IMX_TRIP_PASSIVE, cdev);
++ if (ret) {
++ dev_err(&tz->device,
++ "unbinding zone %s with cdev %s failed:%d\n",
++ tz->type, cdev->type, ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int imx_get_trend(struct thermal_zone_device *tz,
++ int trip, enum thermal_trend *trend)
++{
++ int ret;
++ unsigned long trip_temp;
++
++ ret = imx_get_trip_temp(tz, trip, &trip_temp);
++ if (ret < 0)
++ return ret;
++
++ if (tz->temperature >= (trip_temp - IMX_TEMP_PASSIVE_COOL_DELTA))
++ *trend = THERMAL_TREND_RAISE_FULL;
++ else
++ *trend = THERMAL_TREND_DROP_FULL;
++
++ return 0;
++}
++
++static const struct thermal_zone_device_ops imx_tz_ops = {
++ .bind = imx_bind,
++ .unbind = imx_unbind,
++ .get_temp = imx_get_temp,
++ .get_mode = imx_get_mode,
++ .set_mode = imx_set_mode,
++ .get_trip_type = imx_get_trip_type,
++ .get_trip_temp = imx_get_trip_temp,
++ .get_crit_temp = imx_get_crit_temp,
++ .get_trend = imx_get_trend,
++ .set_trip_temp = imx_set_trip_temp,
++};
++
++static int imx_get_sensor_data(struct platform_device *pdev)
++{
++ struct imx_thermal_data *data = platform_get_drvdata(pdev);
++ struct regmap *map;
++ int t1, n1;
++ int ret;
++ u32 val;
++ u64 temp64;
++
++ map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++ "fsl,tempmon-data");
++ if (IS_ERR(map)) {
++ ret = PTR_ERR(map);
++ dev_err(&pdev->dev, "failed to get sensor regmap: %d\n", ret);
++ return ret;
++ }
++
++ ret = regmap_read(map, OCOTP_ANA1, &val);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read sensor data: %d\n", ret);
++ return ret;
++ }
++
++ if (val == 0 || val == ~0) {
++ dev_err(&pdev->dev, "invalid sensor calibration data\n");
++ return -EINVAL;
++ }
++
++ /*
++ * Sensor data layout:
++ * [31:20] - sensor value @ 25C
++ * We use universal formula now and only need sensor value @ 25C
++ * slope = 0.4297157 - (0.0015976 * 25C fuse)
++ */
++ n1 = val >> 20;
++ t1 = 25; /* t1 always 25C */
++
++ /*
++ * Derived from linear interpolation:
++ * slope = 0.4297157 - (0.0015976 * 25C fuse)
++ * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
++ * (Nmeas - n1) / (Tmeas - t1) = slope
++ * We want to reduce this down to the minimum computation necessary
++ * for each temperature read. Also, we want Tmeas in millicelsius
++ * and we don't want to lose precision from integer division. So...
++ * Tmeas = (Nmeas - n1) / slope + t1
++ * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
++ * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
++ * Let constant c1 = (-1000 / slope)
++ * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
++ * Let constant c2 = n1 *c1 + 1000 * t1
++ * milli_Tmeas = c2 - Nmeas * c1
++ */
++ temp64 = FACTOR0;
++ temp64 *= 1000;
++ do_div(temp64, FACTOR1 * n1 - FACTOR2);
++ data->c1 = temp64;
++ data->c2 = n1 * data->c1 + 1000 * t1;
++
++ return 0;
++}
++
++static int imx_thermal_probe(struct platform_device *pdev)
++{
++ struct imx_thermal_data *data;
++ struct cpumask clip_cpus;
++ struct regmap *map;
++ int ret;
++
++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "fsl,tempmon");
++ if (IS_ERR(map)) {
++ ret = PTR_ERR(map);
++ dev_err(&pdev->dev, "failed to get tempmon regmap: %d\n", ret);
++ return ret;
++ }
++ data->tempmon = map;
++
++ platform_set_drvdata(pdev, data);
++
++ ret = imx_get_sensor_data(pdev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get sensor data\n");
++ return ret;
++ }
++
++ data->thermal_clk = devm_clk_get(&pdev->dev, NULL);
++ ret = IS_ERR(data->thermal_clk);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get thermal clk!\n");
++ return ret;
++ }
++
++ /* Make sure sensor is in known good state for measurements */
++ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
++ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
++ regmap_write(map, TEMPSENSE1 + REG_CLR, TEMPSENSE1_MEASURE_FREQ);
++ regmap_write(map, MISC0 + REG_SET, MISC0_REFTOP_SELBIASOFF);
++ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
++
++ cpumask_set_cpu(0, &clip_cpus);
++ data->cdev[0] = cpufreq_cooling_register(&clip_cpus);
++ if (IS_ERR(data->cdev[0])) {
++ ret = PTR_ERR(data->cdev[0]);
++ dev_err(&pdev->dev,
++ "failed to register cpufreq cooling device: %d\n", ret);
++ return ret;
++ }
++
++ data->cdev[1] = devfreq_cooling_register();
++ if (IS_ERR(data->cdev[1])) {
++ ret = PTR_ERR(data->cdev[1]);
++ dev_err(&pdev->dev,
++ "failed to register devfreq cooling device: %d\n", ret);
++ return ret;
++ }
++
++ data->trip_temp[IMX_TRIP_PASSIVE] = IMX_TEMP_PASSIVE;
++ data->trip_temp[IMX_TRIP_CRITICAL] = IMX_TEMP_CRITICAL;
++ data->tz = thermal_zone_device_register("imx_thermal_zone",
++ IMX_TRIP_NUM,
++ (1 << IMX_TRIP_NUM) - 1,
++ data,
++ &imx_tz_ops, NULL,
++ IMX_PASSIVE_DELAY,
++ IMX_POLLING_DELAY);
++ if (IS_ERR(data->tz)) {
++ ret = PTR_ERR(data->tz);
++ dev_err(&pdev->dev,
++ "failed to register thermal zone device %d\n", ret);
++ cpufreq_cooling_unregister(data->cdev[0]);
++ devfreq_cooling_unregister(data->cdev[1]);
++ return ret;
++ }
++
++ data->mode = THERMAL_DEVICE_ENABLED;
++
++ return 0;
++}
++
++static int imx_thermal_remove(struct platform_device *pdev)
++{
++ struct imx_thermal_data *data = platform_get_drvdata(pdev);
++
++ thermal_zone_device_unregister(data->tz);
++ cpufreq_cooling_unregister(data->cdev[0]);
++ devfreq_cooling_unregister(data->cdev[1]);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int imx_thermal_suspend(struct device *dev)
++{
++ struct imx_thermal_data *data = dev_get_drvdata(dev);
++ struct regmap *map = data->tempmon;
++ u32 val;
++
++ regmap_read(map, TEMPSENSE0, &val);
++ if ((val & TEMPSENSE0_POWER_DOWN) == 0) {
++ /*
++ * If a measurement is taking place, wait for a long enough
++ * time for it to finish, and then check again. If it still
++ * does not finish, something must go wrong.
++ */
++ udelay(50);
++ regmap_read(map, TEMPSENSE0, &val);
++ if ((val & TEMPSENSE0_POWER_DOWN) == 0)
++ return -ETIMEDOUT;
++ }
++
++ return 0;
++}
++
++static int imx_thermal_resume(struct device *dev)
++{
++ /* Nothing to do for now */
++ return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(imx_thermal_pm_ops,
++ imx_thermal_suspend, imx_thermal_resume);
++
++static const struct of_device_id of_imx_thermal_match[] = {
++ { .compatible = "fsl,imx6q-tempmon", },
++ { /* end */ }
++};
++MODULE_DEVICE_TABLE(of, of_imx_thermal_match);
++
++static struct platform_driver imx_thermal = {
++ .driver = {
++ .name = "imx_thermal",
++ .owner = THIS_MODULE,
++ .pm = &imx_thermal_pm_ops,
++ .of_match_table = of_imx_thermal_match,
++ },
++ .probe = imx_thermal_probe,
++ .remove = imx_thermal_remove,
++};
++module_platform_driver(imx_thermal);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Thermal driver for Freescale i.MX SoCs");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:imx-thermal");
+diff -Nur linux-3.10.30.orig/drivers/thermal/Kconfig linux-linaro-stable-mx6/drivers/thermal/Kconfig
+--- linux-3.10.30.orig/drivers/thermal/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/thermal/Kconfig 2014-05-15 20:34:07.542082630 +0200
+@@ -91,6 +91,24 @@
+ because userland can easily disable the thermal policy by simply
+ flooding this sysfs node with low temperature values.
+
++config IMX_THERMAL
++ tristate "Temperature sensor driver for Freescale i.MX SoCs"
++ depends on CPU_THERMAL
++ depends on MFD_SYSCON
++ depends on OF
++ help
++ Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs.
++ It supports one critical trip point and one passive trip point. The
++ cpufreq is used as the cooling device to throttle CPUs when the
++ passive trip is crossed.
++
++config DEVICE_THERMAL
++ tristate "generic device cooling support"
++ help
++ Support for device cooling.
++ It supports notification of crossing passive trip for devices,
++ devices need to do their own actions to cool down the SOC.
++
+ config SPEAR_THERMAL
+ bool "SPEAr thermal sensor driver"
+ depends on PLAT_SPEAR
+diff -Nur linux-3.10.30.orig/drivers/thermal/Makefile linux-linaro-stable-mx6/drivers/thermal/Makefile
+--- linux-3.10.30.orig/drivers/thermal/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/thermal/Makefile 2014-05-15 20:34:07.542082630 +0200
+@@ -21,6 +21,8 @@
+ obj-$(CONFIG_DOVE_THERMAL) += dove_thermal.o
+ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
+ obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
++obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
++obj-$(CONFIG_DEVICE_THERMAL) += device_cooling.o
+ obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
+ obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
+
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/ar933x_uart.c linux-linaro-stable-mx6/drivers/tty/serial/ar933x_uart.c
+--- linux-3.10.30.orig/drivers/tty/serial/ar933x_uart.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/ar933x_uart.c 2014-05-15 20:34:07.730083984 +0200
+@@ -703,7 +703,6 @@
+ struct ar933x_uart_port *up;
+
+ up = platform_get_drvdata(pdev);
+- platform_set_drvdata(pdev, NULL);
+
+ if (up) {
+ uart_remove_one_port(&ar933x_uart_driver, &up->port);
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/atmel_serial.c linux-linaro-stable-mx6/drivers/tty/serial/atmel_serial.c
+--- linux-3.10.30.orig/drivers/tty/serial/atmel_serial.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/atmel_serial.c 2014-05-15 20:34:07.730083984 +0200
+@@ -1853,7 +1853,6 @@
+ int ret = 0;
+
+ device_init_wakeup(&pdev->dev, 0);
+- platform_set_drvdata(pdev, NULL);
+
+ ret = uart_remove_one_port(&atmel_uart, port);
+
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/bcm63xx_uart.c linux-linaro-stable-mx6/drivers/tty/serial/bcm63xx_uart.c
+--- linux-3.10.30.orig/drivers/tty/serial/bcm63xx_uart.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/bcm63xx_uart.c 2014-05-15 20:34:07.730083984 +0200
+@@ -852,7 +852,6 @@
+
+ port = platform_get_drvdata(pdev);
+ uart_remove_one_port(&bcm_uart_driver, port);
+- platform_set_drvdata(pdev, NULL);
+ /* mark port as free */
+ ports[pdev->id].membase = 0;
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/clps711x.c linux-linaro-stable-mx6/drivers/tty/serial/clps711x.c
+--- linux-3.10.30.orig/drivers/tty/serial/clps711x.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/clps711x.c 2014-05-15 20:34:07.758084186 +0200
+@@ -438,8 +438,7 @@
+ s->uart_clk = devm_clk_get(&pdev->dev, "uart");
+ if (IS_ERR(s->uart_clk)) {
+ dev_err(&pdev->dev, "Can't get UART clocks\n");
+- ret = PTR_ERR(s->uart_clk);
+- goto err_out;
++ return PTR_ERR(s->uart_clk);
+ }
+
+ s->uart.owner = THIS_MODULE;
+@@ -461,7 +460,7 @@
+ if (ret) {
+ dev_err(&pdev->dev, "Registering UART driver failed\n");
+ devm_clk_put(&pdev->dev, s->uart_clk);
+- goto err_out;
++ return ret;
+ }
+
+ for (i = 0; i < UART_CLPS711X_NR; i++) {
+@@ -478,11 +477,6 @@
+ }
+
+ return 0;
+-
+-err_out:
+- platform_set_drvdata(pdev, NULL);
+-
+- return ret;
+ }
+
+ static int uart_clps711x_remove(struct platform_device *pdev)
+@@ -495,7 +489,6 @@
+
+ devm_clk_put(&pdev->dev, s->uart_clk);
+ uart_unregister_driver(&s->uart);
+- platform_set_drvdata(pdev, NULL);
+
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/efm32-uart.c linux-linaro-stable-mx6/drivers/tty/serial/efm32-uart.c
+--- linux-3.10.30.orig/drivers/tty/serial/efm32-uart.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/efm32-uart.c 2014-05-15 20:34:07.766084243 +0200
+@@ -778,8 +778,6 @@
+ {
+ struct efm32_uart_port *efm_port = platform_get_drvdata(pdev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ uart_remove_one_port(&efm32_uart_reg, &efm_port->port);
+
+ if (pdev->id >= 0 && pdev->id < ARRAY_SIZE(efm32_uart_ports))
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/fsl_lpuart.c linux-linaro-stable-mx6/drivers/tty/serial/fsl_lpuart.c
+--- linux-3.10.30.orig/drivers/tty/serial/fsl_lpuart.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/fsl_lpuart.c 2014-05-15 20:34:07.766084243 +0200
+@@ -0,0 +1,879 @@
++/*
++ * Freescale lpuart serial port driver
++ *
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
++#define SUPPORT_SYSRQ
++#endif
++
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/clk.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/console.h>
++#include <linux/serial_core.h>
++#include <linux/tty_flip.h>
++
++/* All registers are 8-bit width */
++#define UARTBDH 0x00
++#define UARTBDL 0x01
++#define UARTCR1 0x02
++#define UARTCR2 0x03
++#define UARTSR1 0x04
++#define UARTCR3 0x06
++#define UARTDR 0x07
++#define UARTCR4 0x0a
++#define UARTCR5 0x0b
++#define UARTMODEM 0x0d
++#define UARTPFIFO 0x10
++#define UARTCFIFO 0x11
++#define UARTSFIFO 0x12
++#define UARTTWFIFO 0x13
++#define UARTTCFIFO 0x14
++#define UARTRWFIFO 0x15
++
++#define UARTBDH_LBKDIE 0x80
++#define UARTBDH_RXEDGIE 0x40
++#define UARTBDH_SBR_MASK 0x1f
++
++#define UARTCR1_LOOPS 0x80
++#define UARTCR1_RSRC 0x20
++#define UARTCR1_M 0x10
++#define UARTCR1_WAKE 0x08
++#define UARTCR1_ILT 0x04
++#define UARTCR1_PE 0x02
++#define UARTCR1_PT 0x01
++
++#define UARTCR2_TIE 0x80
++#define UARTCR2_TCIE 0x40
++#define UARTCR2_RIE 0x20
++#define UARTCR2_ILIE 0x10
++#define UARTCR2_TE 0x08
++#define UARTCR2_RE 0x04
++#define UARTCR2_RWU 0x02
++#define UARTCR2_SBK 0x01
++
++#define UARTSR1_TDRE 0x80
++#define UARTSR1_TC 0x40
++#define UARTSR1_RDRF 0x20
++#define UARTSR1_IDLE 0x10
++#define UARTSR1_OR 0x08
++#define UARTSR1_NF 0x04
++#define UARTSR1_FE 0x02
++#define UARTSR1_PE 0x01
++
++#define UARTCR3_R8 0x80
++#define UARTCR3_T8 0x40
++#define UARTCR3_TXDIR 0x20
++#define UARTCR3_TXINV 0x10
++#define UARTCR3_ORIE 0x08
++#define UARTCR3_NEIE 0x04
++#define UARTCR3_FEIE 0x02
++#define UARTCR3_PEIE 0x01
++
++#define UARTCR4_MAEN1 0x80
++#define UARTCR4_MAEN2 0x40
++#define UARTCR4_M10 0x20
++#define UARTCR4_BRFA_MASK 0x1f
++#define UARTCR4_BRFA_OFF 0
++
++#define UARTCR5_TDMAS 0x80
++#define UARTCR5_RDMAS 0x20
++
++#define UARTMODEM_RXRTSE 0x08
++#define UARTMODEM_TXRTSPOL 0x04
++#define UARTMODEM_TXRTSE 0x02
++#define UARTMODEM_TXCTSE 0x01
++
++#define UARTPFIFO_TXFE 0x80
++#define UARTPFIFO_FIFOSIZE_MASK 0x7
++#define UARTPFIFO_TXSIZE_OFF 4
++#define UARTPFIFO_RXFE 0x08
++#define UARTPFIFO_RXSIZE_OFF 0
++
++#define UARTCFIFO_TXFLUSH 0x80
++#define UARTCFIFO_RXFLUSH 0x40
++#define UARTCFIFO_RXOFE 0x04
++#define UARTCFIFO_TXOFE 0x02
++#define UARTCFIFO_RXUFE 0x01
++
++#define UARTSFIFO_TXEMPT 0x80
++#define UARTSFIFO_RXEMPT 0x40
++#define UARTSFIFO_RXOF 0x04
++#define UARTSFIFO_TXOF 0x02
++#define UARTSFIFO_RXUF 0x01
++
++#define DRIVER_NAME "fsl-lpuart"
++#define DEV_NAME "ttyLP"
++#define UART_NR 6
++
++struct lpuart_port {
++ struct uart_port port;
++ struct clk *clk;
++ unsigned int txfifo_size;
++ unsigned int rxfifo_size;
++};
++
++static struct of_device_id lpuart_dt_ids[] = {
++ {
++ .compatible = "fsl,vf610-lpuart",
++ },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
++
++static void lpuart_stop_tx(struct uart_port *port)
++{
++ unsigned char temp;
++
++ temp = readb(port->membase + UARTCR2);
++ temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
++ writeb(temp, port->membase + UARTCR2);
++}
++
++static void lpuart_stop_rx(struct uart_port *port)
++{
++ unsigned char temp;
++
++ temp = readb(port->membase + UARTCR2);
++ writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
++}
++
++static void lpuart_enable_ms(struct uart_port *port)
++{
++}
++
++static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
++{
++ struct circ_buf *xmit = &sport->port.state->xmit;
++
++ while (!uart_circ_empty(xmit) &&
++ (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
++ writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
++ sport->port.icount.tx++;
++ }
++
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(&sport->port);
++
++ if (uart_circ_empty(xmit))
++ lpuart_stop_tx(&sport->port);
++}
++
++static void lpuart_start_tx(struct uart_port *port)
++{
++ struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
++ unsigned char temp;
++
++ temp = readb(port->membase + UARTCR2);
++ writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
++
++ if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
++ lpuart_transmit_buffer(sport);
++}
++
++static irqreturn_t lpuart_txint(int irq, void *dev_id)
++{
++ struct lpuart_port *sport = dev_id;
++ struct circ_buf *xmit = &sport->port.state->xmit;
++ unsigned long flags;
++
++ spin_lock_irqsave(&sport->port.lock, flags);
++ if (sport->port.x_char) {
++ writeb(sport->port.x_char, sport->port.membase + UARTDR);
++ goto out;
++ }
++
++ if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
++ lpuart_stop_tx(&sport->port);
++ goto out;
++ }
++
++ lpuart_transmit_buffer(sport);
++
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(&sport->port);
++
++out:
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t lpuart_rxint(int irq, void *dev_id)
++{
++ struct lpuart_port *sport = dev_id;
++ unsigned int flg, ignored = 0;
++ struct tty_port *port = &sport->port.state->port;
++ unsigned long flags;
++ unsigned char rx, sr;
++
++ spin_lock_irqsave(&sport->port.lock, flags);
++
++ while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
++ flg = TTY_NORMAL;
++ sport->port.icount.rx++;
++ /*
++ * to clear the FE, OR, NF, FE, PE flags,
++ * read SR1 then read DR
++ */
++ sr = readb(sport->port.membase + UARTSR1);
++ rx = readb(sport->port.membase + UARTDR);
++
++ if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
++ continue;
++
++ if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
++ if (sr & UARTSR1_PE)
++ sport->port.icount.parity++;
++ else if (sr & UARTSR1_FE)
++ sport->port.icount.frame++;
++
++ if (sr & UARTSR1_OR)
++ sport->port.icount.overrun++;
++
++ if (sr & sport->port.ignore_status_mask) {
++ if (++ignored > 100)
++ goto out;
++ continue;
++ }
++
++ sr &= sport->port.read_status_mask;
++
++ if (sr & UARTSR1_PE)
++ flg = TTY_PARITY;
++ else if (sr & UARTSR1_FE)
++ flg = TTY_FRAME;
++
++ if (sr & UARTSR1_OR)
++ flg = TTY_OVERRUN;
++
++#ifdef SUPPORT_SYSRQ
++ sport->port.sysrq = 0;
++#endif
++ }
++
++ tty_insert_flip_char(port, rx, flg);
++ }
++
++out:
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++
++ tty_flip_buffer_push(port);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t lpuart_int(int irq, void *dev_id)
++{
++ struct lpuart_port *sport = dev_id;
++ unsigned char sts;
++
++ sts = readb(sport->port.membase + UARTSR1);
++
++ if (sts & UARTSR1_RDRF)
++ lpuart_rxint(irq, dev_id);
++
++ if (sts & UARTSR1_TDRE &&
++ !(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS))
++ lpuart_txint(irq, dev_id);
++
++ return IRQ_HANDLED;
++}
++
++/* return TIOCSER_TEMT when transmitter is not busy */
++static unsigned int lpuart_tx_empty(struct uart_port *port)
++{
++ return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
++ TIOCSER_TEMT : 0;
++}
++
++static unsigned int lpuart_get_mctrl(struct uart_port *port)
++{
++ unsigned int temp = 0;
++ unsigned char reg;
++
++ reg = readb(port->membase + UARTMODEM);
++ if (reg & UARTMODEM_TXCTSE)
++ temp |= TIOCM_CTS;
++
++ if (reg & UARTMODEM_RXRTSE)
++ temp |= TIOCM_RTS;
++
++ return temp;
++}
++
++static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
++{
++ unsigned char temp;
++
++ temp = readb(port->membase + UARTMODEM) &
++ ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
++
++ if (mctrl & TIOCM_RTS)
++ temp |= UARTMODEM_RXRTSE;
++
++ if (mctrl & TIOCM_CTS)
++ temp |= UARTMODEM_TXCTSE;
++
++ writeb(temp, port->membase + UARTMODEM);
++}
++
++static void lpuart_break_ctl(struct uart_port *port, int break_state)
++{
++ unsigned char temp;
++
++ temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
++
++ if (break_state != 0)
++ temp |= UARTCR2_SBK;
++
++ writeb(temp, port->membase + UARTCR2);
++}
++
++static void lpuart_setup_watermark(struct lpuart_port *sport)
++{
++ unsigned char val, cr2;
++ unsigned char cr2_saved;
++
++ cr2 = readb(sport->port.membase + UARTCR2);
++ cr2_saved = cr2;
++ cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
++ UARTCR2_RIE | UARTCR2_RE);
++ writeb(cr2, sport->port.membase + UARTCR2);
++
++ /* determine FIFO size and enable FIFO mode */
++ val = readb(sport->port.membase + UARTPFIFO);
++
++ sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
++ UARTPFIFO_FIFOSIZE_MASK) + 1);
++
++ sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
++ UARTPFIFO_FIFOSIZE_MASK) + 1);
++
++ writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
++ sport->port.membase + UARTPFIFO);
++
++ /* flush Tx and Rx FIFO */
++ writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
++ sport->port.membase + UARTCFIFO);
++
++ writeb(2, sport->port.membase + UARTTWFIFO);
++ writeb(1, sport->port.membase + UARTRWFIFO);
++
++ /* Restore cr2 */
++ writeb(cr2_saved, sport->port.membase + UARTCR2);
++}
++
++static int lpuart_startup(struct uart_port *port)
++{
++ struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
++ int ret;
++ unsigned long flags;
++ unsigned char temp;
++
++ ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
++ DRIVER_NAME, sport);
++ if (ret)
++ return ret;
++
++ spin_lock_irqsave(&sport->port.lock, flags);
++
++ lpuart_setup_watermark(sport);
++
++ temp = readb(sport->port.membase + UARTCR2);
++ temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
++ writeb(temp, sport->port.membase + UARTCR2);
++
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++ return 0;
++}
++
++static void lpuart_shutdown(struct uart_port *port)
++{
++ struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
++ unsigned char temp;
++ unsigned long flags;
++
++ spin_lock_irqsave(&port->lock, flags);
++
++ /* disable Rx/Tx and interrupts */
++ temp = readb(port->membase + UARTCR2);
++ temp &= ~(UARTCR2_TE | UARTCR2_RE |
++ UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
++ writeb(temp, port->membase + UARTCR2);
++
++ spin_unlock_irqrestore(&port->lock, flags);
++
++ devm_free_irq(port->dev, port->irq, sport);
++}
++
++static void
++lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
++ struct ktermios *old)
++{
++ struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
++ unsigned long flags;
++ unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
++ unsigned int baud;
++ unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
++ unsigned int sbr, brfa;
++
++ cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
++ old_cr2 = readb(sport->port.membase + UARTCR2);
++ cr4 = readb(sport->port.membase + UARTCR4);
++ bdh = readb(sport->port.membase + UARTBDH);
++ modem = readb(sport->port.membase + UARTMODEM);
++ /*
++ * only support CS8 and CS7, and for CS7 must enable PE.
++ * supported mode:
++ * - (7,e/o,1)
++ * - (8,n,1)
++ * - (8,m/s,1)
++ * - (8,e/o,1)
++ */
++ while ((termios->c_cflag & CSIZE) != CS8 &&
++ (termios->c_cflag & CSIZE) != CS7) {
++ termios->c_cflag &= ~CSIZE;
++ termios->c_cflag |= old_csize;
++ old_csize = CS8;
++ }
++
++ if ((termios->c_cflag & CSIZE) == CS8 ||
++ (termios->c_cflag & CSIZE) == CS7)
++ cr1 = old_cr1 & ~UARTCR1_M;
++
++ if (termios->c_cflag & CMSPAR) {
++ if ((termios->c_cflag & CSIZE) != CS8) {
++ termios->c_cflag &= ~CSIZE;
++ termios->c_cflag |= CS8;
++ }
++ cr1 |= UARTCR1_M;
++ }
++
++ if (termios->c_cflag & CRTSCTS) {
++ modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
++ } else {
++ termios->c_cflag &= ~CRTSCTS;
++ modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
++ }
++
++ if (termios->c_cflag & CSTOPB)
++ termios->c_cflag &= ~CSTOPB;
++
++ /* parity must be enabled when CS7 to match 8-bits format */
++ if ((termios->c_cflag & CSIZE) == CS7)
++ termios->c_cflag |= PARENB;
++
++ if ((termios->c_cflag & PARENB)) {
++ if (termios->c_cflag & CMSPAR) {
++ cr1 &= ~UARTCR1_PE;
++ cr1 |= UARTCR1_M;
++ } else {
++ cr1 |= UARTCR1_PE;
++ if ((termios->c_cflag & CSIZE) == CS8)
++ cr1 |= UARTCR1_M;
++ if (termios->c_cflag & PARODD)
++ cr1 |= UARTCR1_PT;
++ else
++ cr1 &= ~UARTCR1_PT;
++ }
++ }
++
++ /* ask the core to calculate the divisor */
++ baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
++
++ spin_lock_irqsave(&sport->port.lock, flags);
++
++ sport->port.read_status_mask = 0;
++ if (termios->c_iflag & INPCK)
++ sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
++ if (termios->c_iflag & (BRKINT | PARMRK))
++ sport->port.read_status_mask |= UARTSR1_FE;
++
++ /* characters to ignore */
++ sport->port.ignore_status_mask = 0;
++ if (termios->c_iflag & IGNPAR)
++ sport->port.ignore_status_mask |= UARTSR1_PE;
++ if (termios->c_iflag & IGNBRK) {
++ sport->port.ignore_status_mask |= UARTSR1_FE;
++ /*
++ * if we're ignoring parity and break indicators,
++ * ignore overruns too (for real raw support).
++ */
++ if (termios->c_iflag & IGNPAR)
++ sport->port.ignore_status_mask |= UARTSR1_OR;
++ }
++
++ /* update the per-port timeout */
++ uart_update_timeout(port, termios->c_cflag, baud);
++
++ /* wait transmit engin complete */
++ while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
++ barrier();
++
++ /* disable transmit and receive */
++ writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
++ sport->port.membase + UARTCR2);
++
++ sbr = sport->port.uartclk / (16 * baud);
++ brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
++ bdh &= ~UARTBDH_SBR_MASK;
++ bdh |= (sbr >> 8) & 0x1F;
++ cr4 &= ~UARTCR4_BRFA_MASK;
++ brfa &= UARTCR4_BRFA_MASK;
++ writeb(cr4 | brfa, sport->port.membase + UARTCR4);
++ writeb(bdh, sport->port.membase + UARTBDH);
++ writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
++ writeb(cr1, sport->port.membase + UARTCR1);
++ writeb(modem, sport->port.membase + UARTMODEM);
++
++ /* restore control register */
++ writeb(old_cr2, sport->port.membase + UARTCR2);
++
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++}
++
++static const char *lpuart_type(struct uart_port *port)
++{
++ return "FSL_LPUART";
++}
++
++static void lpuart_release_port(struct uart_port *port)
++{
++ /* nothing to do */
++}
++
++static int lpuart_request_port(struct uart_port *port)
++{
++ return 0;
++}
++
++/* configure/autoconfigure the port */
++static void lpuart_config_port(struct uart_port *port, int flags)
++{
++ if (flags & UART_CONFIG_TYPE)
++ port->type = PORT_LPUART;
++}
++
++static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
++{
++ int ret = 0;
++
++ if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
++ ret = -EINVAL;
++ if (port->irq != ser->irq)
++ ret = -EINVAL;
++ if (ser->io_type != UPIO_MEM)
++ ret = -EINVAL;
++ if (port->uartclk / 16 != ser->baud_base)
++ ret = -EINVAL;
++ if (port->iobase != ser->port)
++ ret = -EINVAL;
++ if (ser->hub6 != 0)
++ ret = -EINVAL;
++ return ret;
++}
++
++static struct uart_ops lpuart_pops = {
++ .tx_empty = lpuart_tx_empty,
++ .set_mctrl = lpuart_set_mctrl,
++ .get_mctrl = lpuart_get_mctrl,
++ .stop_tx = lpuart_stop_tx,
++ .start_tx = lpuart_start_tx,
++ .stop_rx = lpuart_stop_rx,
++ .enable_ms = lpuart_enable_ms,
++ .break_ctl = lpuart_break_ctl,
++ .startup = lpuart_startup,
++ .shutdown = lpuart_shutdown,
++ .set_termios = lpuart_set_termios,
++ .type = lpuart_type,
++ .request_port = lpuart_request_port,
++ .release_port = lpuart_release_port,
++ .config_port = lpuart_config_port,
++ .verify_port = lpuart_verify_port,
++};
++
++static struct lpuart_port *lpuart_ports[UART_NR];
++
++#ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
++static void lpuart_console_putchar(struct uart_port *port, int ch)
++{
++ while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
++ barrier();
++
++ writeb(ch, port->membase + UARTDR);
++}
++
++static void
++lpuart_console_write(struct console *co, const char *s, unsigned int count)
++{
++ struct lpuart_port *sport = lpuart_ports[co->index];
++ unsigned char old_cr2, cr2;
++
++ /* first save CR2 and then disable interrupts */
++ cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
++ cr2 |= (UARTCR2_TE | UARTCR2_RE);
++ cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
++ writeb(cr2, sport->port.membase + UARTCR2);
++
++ uart_console_write(&sport->port, s, count, lpuart_console_putchar);
++
++ /* wait for transmitter finish complete and restore CR2 */
++ while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
++ barrier();
++
++ writeb(old_cr2, sport->port.membase + UARTCR2);
++}
++
++/*
++ * if the port was already initialised (eg, by a boot loader),
++ * try to determine the current setup.
++ */
++static void __init
++lpuart_console_get_options(struct lpuart_port *sport, int *baud,
++ int *parity, int *bits)
++{
++ unsigned char cr, bdh, bdl, brfa;
++ unsigned int sbr, uartclk, baud_raw;
++
++ cr = readb(sport->port.membase + UARTCR2);
++ cr &= UARTCR2_TE | UARTCR2_RE;
++ if (!cr)
++ return;
++
++ /* ok, the port was enabled */
++
++ cr = readb(sport->port.membase + UARTCR1);
++
++ *parity = 'n';
++ if (cr & UARTCR1_PE) {
++ if (cr & UARTCR1_PT)
++ *parity = 'o';
++ else
++ *parity = 'e';
++ }
++
++ if (cr & UARTCR1_M)
++ *bits = 9;
++ else
++ *bits = 8;
++
++ bdh = readb(sport->port.membase + UARTBDH);
++ bdh &= UARTBDH_SBR_MASK;
++ bdl = readb(sport->port.membase + UARTBDL);
++ sbr = bdh;
++ sbr <<= 8;
++ sbr |= bdl;
++ brfa = readb(sport->port.membase + UARTCR4);
++ brfa &= UARTCR4_BRFA_MASK;
++
++ uartclk = clk_get_rate(sport->clk);
++ /*
++ * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
++ */
++ baud_raw = uartclk / (16 * (sbr + brfa / 32));
++
++ if (*baud != baud_raw)
++ printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
++ "from %d to %d\n", baud_raw, *baud);
++}
++
++static int __init lpuart_console_setup(struct console *co, char *options)
++{
++ struct lpuart_port *sport;
++ int baud = 115200;
++ int bits = 8;
++ int parity = 'n';
++ int flow = 'n';
++
++ /*
++ * check whether an invalid uart number has been specified, and
++ * if so, search for the first available port that does have
++ * console support.
++ */
++ if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
++ co->index = 0;
++
++ sport = lpuart_ports[co->index];
++ if (sport == NULL)
++ return -ENODEV;
++
++ if (options)
++ uart_parse_options(options, &baud, &parity, &bits, &flow);
++ else
++ lpuart_console_get_options(sport, &baud, &parity, &bits);
++
++ lpuart_setup_watermark(sport);
++
++ return uart_set_options(&sport->port, co, baud, parity, bits, flow);
++}
++
++static struct uart_driver lpuart_reg;
++static struct console lpuart_console = {
++ .name = DEV_NAME,
++ .write = lpuart_console_write,
++ .device = uart_console_device,
++ .setup = lpuart_console_setup,
++ .flags = CON_PRINTBUFFER,
++ .index = -1,
++ .data = &lpuart_reg,
++};
++
++#define LPUART_CONSOLE (&lpuart_console)
++#else
++#define LPUART_CONSOLE NULL
++#endif
++
++static struct uart_driver lpuart_reg = {
++ .owner = THIS_MODULE,
++ .driver_name = DRIVER_NAME,
++ .dev_name = DEV_NAME,
++ .nr = ARRAY_SIZE(lpuart_ports),
++ .cons = LPUART_CONSOLE,
++};
++
++static int lpuart_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct lpuart_port *sport;
++ struct resource *res;
++ int ret;
++
++ sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
++ if (!sport)
++ return -ENOMEM;
++
++ pdev->dev.coherent_dma_mask = 0;
++
++ ret = of_alias_get_id(np, "serial");
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
++ return ret;
++ }
++ sport->port.line = ret;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENODEV;
++
++ sport->port.mapbase = res->start;
++ sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(sport->port.membase))
++ return PTR_ERR(sport->port.membase);
++
++ sport->port.dev = &pdev->dev;
++ sport->port.type = PORT_LPUART;
++ sport->port.iotype = UPIO_MEM;
++ sport->port.irq = platform_get_irq(pdev, 0);
++ sport->port.ops = &lpuart_pops;
++ sport->port.flags = UPF_BOOT_AUTOCONF;
++
++ sport->clk = devm_clk_get(&pdev->dev, "ipg");
++ if (IS_ERR(sport->clk)) {
++ ret = PTR_ERR(sport->clk);
++ dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
++ return ret;
++ }
++
++ ret = clk_prepare_enable(sport->clk);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
++ return ret;
++ }
++
++ sport->port.uartclk = clk_get_rate(sport->clk);
++
++ lpuart_ports[sport->port.line] = sport;
++
++ platform_set_drvdata(pdev, &sport->port);
++
++ ret = uart_add_one_port(&lpuart_reg, &sport->port);
++ if (ret) {
++ clk_disable_unprepare(sport->clk);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int lpuart_remove(struct platform_device *pdev)
++{
++ struct lpuart_port *sport = platform_get_drvdata(pdev);
++
++ uart_remove_one_port(&lpuart_reg, &sport->port);
++
++ clk_disable_unprepare(sport->clk);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int lpuart_suspend(struct device *dev)
++{
++ struct lpuart_port *sport = dev_get_drvdata(dev);
++
++ uart_suspend_port(&lpuart_reg, &sport->port);
++
++ return 0;
++}
++
++static int lpuart_resume(struct device *dev)
++{
++ struct lpuart_port *sport = dev_get_drvdata(dev);
++
++ uart_resume_port(&lpuart_reg, &sport->port);
++
++ return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
++
++static struct platform_driver lpuart_driver = {
++ .probe = lpuart_probe,
++ .remove = lpuart_remove,
++ .driver = {
++ .name = "fsl-lpuart",
++ .owner = THIS_MODULE,
++ .of_match_table = lpuart_dt_ids,
++ .pm = &lpuart_pm_ops,
++ },
++};
++
++static int __init lpuart_serial_init(void)
++{
++ int ret;
++
++ pr_info("serial: Freescale lpuart driver\n");
++
++ ret = uart_register_driver(&lpuart_reg);
++ if (ret)
++ return ret;
++
++ ret = platform_driver_register(&lpuart_driver);
++ if (ret)
++ uart_unregister_driver(&lpuart_reg);
++
++ return 0;
++}
++
++static void __exit lpuart_serial_exit(void)
++{
++ platform_driver_unregister(&lpuart_driver);
++ uart_unregister_driver(&lpuart_reg);
++}
++
++module_init(lpuart_serial_init);
++module_exit(lpuart_serial_exit);
++
++MODULE_DESCRIPTION("Freescale lpuart serial port driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/imx.c linux-linaro-stable-mx6/drivers/tty/serial/imx.c
+--- linux-3.10.30.orig/drivers/tty/serial/imx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/imx.c 2014-05-15 20:34:07.802084503 +0200
+@@ -47,11 +47,12 @@
+ #include <linux/slab.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+-#include <linux/pinctrl/consumer.h>
+ #include <linux/io.h>
++#include <linux/dma-mapping.h>
+
+ #include <asm/irq.h>
+ #include <linux/platform_data/serial-imx.h>
++#include <linux/platform_data/dma-imx.h>
+
+ /* Register definitions */
+ #define URXD0 0x0 /* Receiver Register */
+@@ -83,6 +84,7 @@
+ #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+ #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+ #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
++#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
+ #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+ #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+ #define UCR1_IREN (1<<7) /* Infrared interface enable */
+@@ -91,6 +93,7 @@
+ #define UCR1_SNDBRK (1<<4) /* Send break */
+ #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+ #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
++#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
+ #define UCR1_DOZE (1<<1) /* Doze */
+ #define UCR1_UARTEN (1<<0) /* UART enabled */
+ #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+@@ -126,6 +129,7 @@
+ #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+ #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+ #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
++#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
+ #define UCR4_IRSC (1<<5) /* IR special case */
+ #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+ #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+@@ -187,6 +191,7 @@
+ enum imx_uart_type {
+ IMX1_UART,
+ IMX21_UART,
++ IMX6Q_UART,
+ };
+
+ /* device type dependent stuff */
+@@ -201,6 +206,7 @@
+ unsigned int old_status;
+ int txirq, rxirq, rtsirq;
+ unsigned int have_rtscts:1;
++ unsigned int dte_mode:1;
+ unsigned int use_irda:1;
+ unsigned int irda_inv_rx:1;
+ unsigned int irda_inv_tx:1;
+@@ -208,6 +214,18 @@
+ struct clk *clk_ipg;
+ struct clk *clk_per;
+ const struct imx_uart_data *devdata;
++
++ /* DMA fields */
++ unsigned int dma_is_inited:1;
++ unsigned int dma_is_enabled:1;
++ unsigned int dma_is_rxing:1;
++ unsigned int dma_is_txing:1;
++ struct dma_chan *dma_chan_rx, *dma_chan_tx;
++ struct scatterlist rx_sgl, tx_sgl[2];
++ void *rx_buf;
++ unsigned int tx_bytes;
++ unsigned int dma_tx_nents;
++ wait_queue_head_t dma_wait;
+ };
+
+ struct imx_port_ucrs {
+@@ -231,6 +249,10 @@
+ .uts_reg = IMX21_UTS,
+ .devtype = IMX21_UART,
+ },
++ [IMX6Q_UART] = {
++ .uts_reg = IMX21_UTS,
++ .devtype = IMX6Q_UART,
++ },
+ };
+
+ static struct platform_device_id imx_uart_devtype[] = {
+@@ -241,12 +263,16 @@
+ .name = "imx21-uart",
+ .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
+ }, {
++ .name = "imx6q-uart",
++ .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
++ }, {
+ /* sentinel */
+ }
+ };
+ MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
+
+ static struct of_device_id imx_uart_dt_ids[] = {
++ { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
+ { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
+ { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
+ { /* sentinel */ }
+@@ -268,9 +294,14 @@
+ return sport->devdata->devtype == IMX21_UART;
+ }
+
++static inline int is_imx6q_uart(struct imx_port *sport)
++{
++ return sport->devdata->devtype == IMX6Q_UART;
++}
+ /*
+ * Save and restore functions for UCR1, UCR2 and UCR3 registers
+ */
++#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
+ static void imx_port_ucrs_save(struct uart_port *port,
+ struct imx_port_ucrs *ucr)
+ {
+@@ -288,6 +319,7 @@
+ writel(ucr->ucr2, port->membase + UCR2);
+ writel(ucr->ucr3, port->membase + UCR3);
+ }
++#endif
+
+ /*
+ * Handle any change of modem status signal since we were last called.
+@@ -384,6 +416,13 @@
+ return;
+ }
+
++ /*
++ * We are maybe in the SMP context, so if the DMA TX thread is running
++ * on other cpu, we have to wait for it to finish.
++ */
++ if (sport->dma_is_enabled && sport->dma_is_txing)
++ return;
++
+ temp = readl(sport->port.membase + UCR1);
+ writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
+ }
+@@ -396,6 +435,13 @@
+ struct imx_port *sport = (struct imx_port *)port;
+ unsigned long temp;
+
++ /*
++ * We are maybe in the SMP context, so if the DMA TX thread is running
++ * on other cpu, we have to wait for it to finish.
++ */
++ if (sport->dma_is_enabled && sport->dma_is_rxing)
++ return;
++
+ temp = readl(sport->port.membase + UCR2);
+ writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
+ }
+@@ -431,6 +477,85 @@
+ imx_stop_tx(&sport->port);
+ }
+
++static void dma_tx_callback(void *data)
++{
++ struct imx_port *sport = data;
++ struct scatterlist *sgl = &sport->tx_sgl[0];
++ struct circ_buf *xmit = &sport->port.state->xmit;
++ unsigned long flags;
++
++ dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
++
++ sport->dma_is_txing = 0;
++
++ /* update the stat */
++ spin_lock_irqsave(&sport->port.lock, flags);
++ xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
++ sport->port.icount.tx += sport->tx_bytes;
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++
++ dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
++
++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
++ uart_write_wakeup(&sport->port);
++
++ if (waitqueue_active(&sport->dma_wait)) {
++ wake_up(&sport->dma_wait);
++ dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
++ return;
++ }
++}
++
++static void imx_dma_tx(struct imx_port *sport)
++{
++ struct circ_buf *xmit = &sport->port.state->xmit;
++ struct scatterlist *sgl = sport->tx_sgl;
++ struct dma_async_tx_descriptor *desc;
++ struct dma_chan *chan = sport->dma_chan_tx;
++ struct device *dev = sport->port.dev;
++ enum dma_status status;
++ int ret;
++
++ status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
++ if (DMA_IN_PROGRESS == status)
++ return;
++
++ sport->tx_bytes = uart_circ_chars_pending(xmit);
++
++ if (xmit->tail > xmit->head && xmit->head > 0) {
++ sport->dma_tx_nents = 2;
++ sg_init_table(sgl, 2);
++ sg_set_buf(sgl, xmit->buf + xmit->tail,
++ UART_XMIT_SIZE - xmit->tail);
++ sg_set_buf(sgl + 1, xmit->buf, xmit->head);
++ } else {
++ sport->dma_tx_nents = 1;
++ sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
++ }
++
++ ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
++ if (ret == 0) {
++ dev_err(dev, "DMA mapping error for TX.\n");
++ return;
++ }
++ desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
++ DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
++ if (!desc) {
++ dev_err(dev, "We cannot prepare for the TX slave dma!\n");
++ return;
++ }
++ desc->callback = dma_tx_callback;
++ desc->callback_param = sport;
++
++ dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
++ uart_circ_chars_pending(xmit));
++ /* fire it */
++ sport->dma_is_txing = 1;
++ dmaengine_submit(desc);
++ dma_async_issue_pending(chan);
++ return;
++}
++
+ /*
+ * interrupts disabled on entry
+ */
+@@ -449,9 +574,18 @@
+ temp &= ~(UCR1_RRDYEN);
+ writel(temp, sport->port.membase + UCR1);
+ }
++ /* Clear any pending ORE flag before enabling interrupt */
++ temp = readl(sport->port.membase + USR2);
++ writel(temp | USR2_ORE, sport->port.membase + USR2);
+
+- temp = readl(sport->port.membase + UCR1);
+- writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
++ temp = readl(sport->port.membase + UCR4);
++ temp |= UCR4_OREN;
++ writel(temp, sport->port.membase + UCR4);
++
++ if (!sport->dma_is_enabled) {
++ temp = readl(sport->port.membase + UCR1);
++ writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
++ }
+
+ if (USE_IRDA(sport)) {
+ temp = readl(sport->port.membase + UCR1);
+@@ -463,6 +597,11 @@
+ writel(temp, sport->port.membase + UCR4);
+ }
+
++ if (sport->dma_is_enabled) {
++ imx_dma_tx(sport);
++ return;
++ }
++
+ if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
+ imx_transmit_buffer(sport);
+ }
+@@ -578,15 +717,43 @@
+ return IRQ_HANDLED;
+ }
+
++static int start_rx_dma(struct imx_port *sport);
++/*
++ * If the RXFIFO is filled with some data, and then we
++ * arise a DMA operation to receive them.
++ */
++static void imx_dma_rxint(struct imx_port *sport)
++{
++ unsigned long temp;
++
++ temp = readl(sport->port.membase + USR2);
++ if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
++ sport->dma_is_rxing = 1;
++
++ /* disable the `Recerver Ready Interrrupt` */
++ temp = readl(sport->port.membase + UCR1);
++ temp &= ~(UCR1_RRDYEN);
++ writel(temp, sport->port.membase + UCR1);
++
++ /* tell the DMA to receive the data. */
++ start_rx_dma(sport);
++ }
++}
++
+ static irqreturn_t imx_int(int irq, void *dev_id)
+ {
+ struct imx_port *sport = dev_id;
+ unsigned int sts;
++ unsigned int sts2;
+
+ sts = readl(sport->port.membase + USR1);
+
+- if (sts & USR1_RRDY)
+- imx_rxint(irq, dev_id);
++ if (sts & USR1_RRDY) {
++ if (sport->dma_is_enabled)
++ imx_dma_rxint(sport);
++ else
++ imx_rxint(irq, dev_id);
++ }
+
+ if (sts & USR1_TRDY &&
+ readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
+@@ -598,6 +765,13 @@
+ if (sts & USR1_AWAKE)
+ writel(USR1_AWAKE, sport->port.membase + USR1);
+
++ sts2 = readl(sport->port.membase + USR2);
++ if (sts2 & USR2_ORE) {
++ dev_err(sport->port.dev, "Rx FIFO overrun\n");
++ sport->port.icount.overrun++;
++ writel(sts2 | USR2_ORE, sport->port.membase + USR2);
++ }
++
+ return IRQ_HANDLED;
+ }
+
+@@ -607,8 +781,15 @@
+ static unsigned int imx_tx_empty(struct uart_port *port)
+ {
+ struct imx_port *sport = (struct imx_port *)port;
++ unsigned int ret;
++
++ ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
+
+- return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
++ /* If the TX DMA is working, return 0. */
++ if (sport->dma_is_enabled && sport->dma_is_txing)
++ ret = 0;
++
++ return ret;
+ }
+
+ /*
+@@ -625,6 +806,9 @@
+ if (readl(sport->port.membase + UCR2) & UCR2_CTS)
+ tmp |= TIOCM_RTS;
+
++ if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
++ tmp |= TIOCM_LOOP;
++
+ return tmp;
+ }
+
+@@ -636,9 +820,15 @@
+ temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
+
+ if (mctrl & TIOCM_RTS)
+- temp |= UCR2_CTS;
++ if (!sport->dma_is_enabled)
++ temp |= UCR2_CTS;
+
+ writel(temp, sport->port.membase + UCR2);
++
++ temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
++ if (mctrl & TIOCM_LOOP)
++ temp |= UTS_LOOP;
++ writel(temp, sport->port.membase + uts_reg(sport));
+ }
+
+ /*
+@@ -675,6 +865,206 @@
+ return 0;
+ }
+
++#define RX_BUF_SIZE (PAGE_SIZE)
++static void imx_rx_dma_done(struct imx_port *sport)
++{
++ unsigned long temp;
++
++ /* Enable this interrupt when the RXFIFO is empty. */
++ temp = readl(sport->port.membase + UCR1);
++ temp |= UCR1_RRDYEN;
++ writel(temp, sport->port.membase + UCR1);
++
++ sport->dma_is_rxing = 0;
++
++ /* Is the shutdown waiting for us? */
++ if (waitqueue_active(&sport->dma_wait))
++ wake_up(&sport->dma_wait);
++}
++
++/*
++ * There are three kinds of RX DMA interrupts(such as in the MX6Q):
++ * [1] the RX DMA buffer is full.
++ * [2] the Aging timer expires(wait for 8 bytes long)
++ * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
++ *
++ * The [2] is trigger when a character was been sitting in the FIFO
++ * meanwhile [3] can wait for 32 bytes long when the RX line is
++ * on IDLE state and RxFIFO is empty.
++ */
++static void dma_rx_callback(void *data)
++{
++ struct imx_port *sport = data;
++ struct dma_chan *chan = sport->dma_chan_rx;
++ struct scatterlist *sgl = &sport->rx_sgl;
++ struct tty_port *port = &sport->port.state->port;
++ struct dma_tx_state state;
++ enum dma_status status;
++ unsigned int count;
++
++ /* unmap it first */
++ dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
++
++ status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
++ count = RX_BUF_SIZE - state.residue;
++ dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
++
++ if (count) {
++ tty_insert_flip_string(port, sport->rx_buf, count);
++ tty_flip_buffer_push(port);
++
++ start_rx_dma(sport);
++ } else
++ imx_rx_dma_done(sport);
++}
++
++static int start_rx_dma(struct imx_port *sport)
++{
++ struct scatterlist *sgl = &sport->rx_sgl;
++ struct dma_chan *chan = sport->dma_chan_rx;
++ struct device *dev = sport->port.dev;
++ struct dma_async_tx_descriptor *desc;
++ int ret;
++
++ sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
++ ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
++ if (ret == 0) {
++ dev_err(dev, "DMA mapping error for RX.\n");
++ return -EINVAL;
++ }
++ desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
++ DMA_PREP_INTERRUPT);
++ if (!desc) {
++ dev_err(dev, "We cannot prepare for the RX slave dma!\n");
++ return -EINVAL;
++ }
++ desc->callback = dma_rx_callback;
++ desc->callback_param = sport;
++
++ dev_dbg(dev, "RX: prepare for the DMA.\n");
++ dmaengine_submit(desc);
++ dma_async_issue_pending(chan);
++ return 0;
++}
++
++static void imx_uart_dma_exit(struct imx_port *sport)
++{
++ if (sport->dma_chan_rx) {
++ dma_release_channel(sport->dma_chan_rx);
++ sport->dma_chan_rx = NULL;
++
++ kfree(sport->rx_buf);
++ sport->rx_buf = NULL;
++ }
++
++ if (sport->dma_chan_tx) {
++ dma_release_channel(sport->dma_chan_tx);
++ sport->dma_chan_tx = NULL;
++ }
++
++ sport->dma_is_inited = 0;
++}
++
++static int imx_uart_dma_init(struct imx_port *sport)
++{
++ struct dma_slave_config slave_config = {};
++ struct device *dev = sport->port.dev;
++ int ret;
++
++ /* Prepare for RX : */
++ sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
++ if (!sport->dma_chan_rx) {
++ dev_dbg(dev, "cannot get the DMA channel.\n");
++ ret = -EINVAL;
++ goto err;
++ }
++
++ slave_config.direction = DMA_DEV_TO_MEM;
++ slave_config.src_addr = sport->port.mapbase + URXD0;
++ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++ slave_config.src_maxburst = RXTL;
++ ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
++ if (ret) {
++ dev_err(dev, "error in RX dma configuration.\n");
++ goto err;
++ }
++
++ sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
++ if (!sport->rx_buf) {
++ dev_err(dev, "cannot alloc DMA buffer.\n");
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ /* Prepare for TX : */
++ sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
++ if (!sport->dma_chan_tx) {
++ dev_err(dev, "cannot get the TX DMA channel!\n");
++ ret = -EINVAL;
++ goto err;
++ }
++
++ slave_config.direction = DMA_MEM_TO_DEV;
++ slave_config.dst_addr = sport->port.mapbase + URTX0;
++ slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++ slave_config.dst_maxburst = TXTL;
++ ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
++ if (ret) {
++ dev_err(dev, "error in TX dma configuration.");
++ goto err;
++ }
++
++ sport->dma_is_inited = 1;
++
++ return 0;
++err:
++ imx_uart_dma_exit(sport);
++ return ret;
++}
++
++static void imx_enable_dma(struct imx_port *sport)
++{
++ unsigned long temp;
++
++ init_waitqueue_head(&sport->dma_wait);
++
++ /* set UCR1 */
++ temp = readl(sport->port.membase + UCR1);
++ temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
++ /* wait for 32 idle frames for IDDMA interrupt */
++ UCR1_ICD_REG(3);
++ writel(temp, sport->port.membase + UCR1);
++
++ /* set UCR4 */
++ temp = readl(sport->port.membase + UCR4);
++ temp |= UCR4_IDDMAEN;
++ writel(temp, sport->port.membase + UCR4);
++
++ sport->dma_is_enabled = 1;
++}
++
++static void imx_disable_dma(struct imx_port *sport)
++{
++ unsigned long temp;
++
++ /* clear UCR1 */
++ temp = readl(sport->port.membase + UCR1);
++ temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
++ writel(temp, sport->port.membase + UCR1);
++
++ /* clear UCR2 */
++ temp = readl(sport->port.membase + UCR2);
++ temp &= ~(UCR2_CTSC | UCR2_CTS);
++ writel(temp, sport->port.membase + UCR2);
++
++ /* clear UCR4 */
++ temp = readl(sport->port.membase + UCR4);
++ temp &= ~UCR4_IDDMAEN;
++ writel(temp, sport->port.membase + UCR4);
++
++ sport->dma_is_enabled = 0;
++}
++
+ /* half the RX buffer size */
+ #define CTSTL 16
+
+@@ -684,6 +1074,15 @@
+ int retval;
+ unsigned long flags, temp;
+
++ retval = clk_prepare_enable(sport->clk_per);
++ if (retval)
++ goto error_out1;
++ retval = clk_prepare_enable(sport->clk_ipg);
++ if (retval) {
++ clk_disable_unprepare(sport->clk_per);
++ goto error_out1;
++ }
++
+ imx_setup_ufcr(sport, 0);
+
+ /* disable the DREN bit (Data Ready interrupt enable) before
+@@ -774,7 +1173,7 @@
+ }
+ }
+
+- if (is_imx21_uart(sport)) {
++ if (!is_imx1_uart(sport)) {
+ temp = readl(sport->port.membase + UCR3);
+ temp |= IMX21_UCR3_RXDMUXSEL;
+ writel(temp, sport->port.membase + UCR3);
+@@ -804,7 +1203,7 @@
+
+ if (USE_IRDA(sport)) {
+ struct imxuart_platform_data *pdata;
+- pdata = sport->port.dev->platform_data;
++ pdata = dev_get_platdata(sport->port.dev);
+ sport->irda_inv_rx = pdata->irda_inv_rx;
+ sport->irda_inv_tx = pdata->irda_inv_tx;
+ sport->trcv_delay = pdata->transceiver_delay;
+@@ -830,6 +1229,15 @@
+ unsigned long temp;
+ unsigned long flags;
+
++ if (sport->dma_is_enabled) {
++ /* We have to wait for the DMA to finish. */
++ wait_event(sport->dma_wait,
++ !sport->dma_is_rxing && !sport->dma_is_txing);
++ imx_stop_rx(port);
++ imx_disable_dma(sport);
++ imx_uart_dma_exit(sport);
++ }
++
+ spin_lock_irqsave(&sport->port.lock, flags);
+ temp = readl(sport->port.membase + UCR2);
+ temp &= ~(UCR2_TXEN);
+@@ -838,7 +1246,7 @@
+
+ if (USE_IRDA(sport)) {
+ struct imxuart_platform_data *pdata;
+- pdata = sport->port.dev->platform_data;
++ pdata = dev_get_platdata(sport->port.dev);
+ if (pdata->irda_enable)
+ pdata->irda_enable(0);
+ }
+@@ -871,6 +1279,19 @@
+
+ writel(temp, sport->port.membase + UCR1);
+ spin_unlock_irqrestore(&sport->port.lock, flags);
++
++ clk_disable_unprepare(sport->clk_per);
++ clk_disable_unprepare(sport->clk_ipg);
++}
++
++static void imx_flush_buffer(struct uart_port *port)
++{
++ struct imx_port *sport = (struct imx_port *)port;
++
++ if (sport->dma_is_enabled) {
++ sport->tx_bytes = 0;
++ dmaengine_terminate_all(sport->dma_chan_tx);
++ }
+ }
+
+ static void
+@@ -913,6 +1334,11 @@
+ if (sport->have_rtscts) {
+ ucr2 &= ~UCR2_IRTS;
+ ucr2 |= UCR2_CTSC;
++
++ /* Can we enable the DMA support? */
++ if (is_imx6q_uart(sport) && !uart_console(port)
++ && !sport->dma_is_inited)
++ imx_uart_dma_init(sport);
+ } else {
+ termios->c_cflag &= ~CRTSCTS;
+ }
+@@ -986,6 +1412,11 @@
+ */
+ div = 1;
+ } else {
++ /* custom-baudrate handling */
++ div = sport->port.uartclk / (baud * 16);
++ if (baud == 38400 && quot != div)
++ baud = sport->port.uartclk / (quot * 16);
++
+ div = sport->port.uartclk / (baud * 16);
+ if (div > 7)
+ div = 7;
+@@ -1007,12 +1438,14 @@
+
+ ufcr = readl(sport->port.membase + UFCR);
+ ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
++ if (sport->dte_mode)
++ ufcr |= UFCR_DCEDTE;
+ writel(ufcr, sport->port.membase + UFCR);
+
+ writel(num, sport->port.membase + UBIR);
+ writel(denom, sport->port.membase + UBMR);
+
+- if (is_imx21_uart(sport))
++ if (!is_imx1_uart(sport))
+ writel(sport->port.uartclk / div / 1000,
+ sport->port.membase + IMX21_ONEMS);
+
+@@ -1024,6 +1457,8 @@
+ if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
+ imx_enable_ms(&sport->port);
+
++ if (sport->dma_is_inited && !sport->dma_is_enabled)
++ imx_enable_dma(sport);
+ spin_unlock_irqrestore(&sport->port.lock, flags);
+ }
+
+@@ -1095,7 +1530,7 @@
+ ret = -EINVAL;
+ if (sport->port.uartclk / 16 != ser->baud_base)
+ ret = -EINVAL;
+- if ((void *)sport->port.mapbase != ser->iomem_base)
++ if (sport->port.mapbase != (unsigned long)ser->iomem_base)
+ ret = -EINVAL;
+ if (sport->port.iobase != ser->port)
+ ret = -EINVAL;
+@@ -1179,6 +1614,7 @@
+ .break_ctl = imx_break_ctl,
+ .startup = imx_startup,
+ .shutdown = imx_shutdown,
++ .flush_buffer = imx_flush_buffer,
+ .set_termios = imx_set_termios,
+ .type = imx_type,
+ .release_port = imx_release_port,
+@@ -1215,6 +1651,16 @@
+ unsigned int ucr1;
+ unsigned long flags = 0;
+ int locked = 1;
++ int retval;
++
++ retval = clk_enable(sport->clk_per);
++ if (retval)
++ return;
++ retval = clk_enable(sport->clk_ipg);
++ if (retval) {
++ clk_disable(sport->clk_per);
++ return;
++ }
+
+ if (sport->port.sysrq)
+ locked = 0;
+@@ -1250,6 +1696,9 @@
+
+ if (locked)
+ spin_unlock_irqrestore(&sport->port.lock, flags);
++
++ clk_disable(sport->clk_ipg);
++ clk_disable(sport->clk_per);
+ }
+
+ /*
+@@ -1323,6 +1772,7 @@
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
++ int retval;
+
+ /*
+ * Check whether an invalid uart number has been specified, and
+@@ -1335,6 +1785,11 @@
+ if (sport == NULL)
+ return -ENODEV;
+
++ /* For setting the registers, we only need to enable the ipg clock. */
++ retval = clk_prepare_enable(sport->clk_ipg);
++ if (retval)
++ goto error_console;
++
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+ else
+@@ -1342,7 +1797,20 @@
+
+ imx_setup_ufcr(sport, 0);
+
+- return uart_set_options(&sport->port, co, baud, parity, bits, flow);
++ retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
++
++ clk_disable(sport->clk_ipg);
++ if (retval) {
++ clk_unprepare(sport->clk_ipg);
++ goto error_console;
++ }
++
++ retval = clk_prepare(sport->clk_per);
++ if (retval)
++ clk_disable_unprepare(sport->clk_ipg);
++
++error_console:
++ return retval;
+ }
+
+ static struct uart_driver imx_reg;
+@@ -1431,6 +1899,9 @@
+ if (of_get_property(np, "fsl,irda-mode", NULL))
+ sport->use_irda = 1;
+
++ if (of_get_property(np, "fsl,dte-mode", NULL))
++ sport->dte_mode = 1;
++
+ sport->devdata = of_id->data;
+
+ return 0;
+@@ -1446,7 +1917,7 @@
+ static void serial_imx_probe_pdata(struct imx_port *sport,
+ struct platform_device *pdev)
+ {
+- struct imxuart_platform_data *pdata = pdev->dev.platform_data;
++ struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
+
+ sport->port.line = pdev->id;
+ sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
+@@ -1468,7 +1939,6 @@
+ void __iomem *base;
+ int ret = 0;
+ struct resource *res;
+- struct pinctrl *pinctrl;
+
+ sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
+ if (!sport)
+@@ -1504,13 +1974,6 @@
+ sport->timer.function = imx_timeout;
+ sport->timer.data = (unsigned long)sport;
+
+- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+- if (IS_ERR(pinctrl)) {
+- ret = PTR_ERR(pinctrl);
+- dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
+- return ret;
+- }
+-
+ sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
+ if (IS_ERR(sport->clk_ipg)) {
+ ret = PTR_ERR(sport->clk_ipg);
+@@ -1525,18 +1988,15 @@
+ return ret;
+ }
+
+- clk_prepare_enable(sport->clk_per);
+- clk_prepare_enable(sport->clk_ipg);
+-
+ sport->port.uartclk = clk_get_rate(sport->clk_per);
+
+ imx_ports[sport->port.line] = sport;
+
+- pdata = pdev->dev.platform_data;
++ pdata = dev_get_platdata(&pdev->dev);
+ if (pdata && pdata->init) {
+ ret = pdata->init(pdev);
+ if (ret)
+- goto clkput;
++ return ret;
+ }
+
+ ret = uart_add_one_port(&imx_reg, &sport->port);
+@@ -1548,9 +2008,6 @@
+ deinit:
+ if (pdata && pdata->exit)
+ pdata->exit(pdev);
+-clkput:
+- clk_disable_unprepare(sport->clk_per);
+- clk_disable_unprepare(sport->clk_ipg);
+ return ret;
+ }
+
+@@ -1559,15 +2016,10 @@
+ struct imxuart_platform_data *pdata;
+ struct imx_port *sport = platform_get_drvdata(pdev);
+
+- pdata = pdev->dev.platform_data;
+-
+- platform_set_drvdata(pdev, NULL);
++ pdata = dev_get_platdata(&pdev->dev);
+
+ uart_remove_one_port(&imx_reg, &sport->port);
+
+- clk_disable_unprepare(sport->clk_per);
+- clk_disable_unprepare(sport->clk_ipg);
+-
+ if (pdata && pdata->exit)
+ pdata->exit(pdev);
+
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/Kconfig linux-linaro-stable-mx6/drivers/tty/serial/Kconfig
+--- linux-3.10.30.orig/drivers/tty/serial/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/Kconfig 2014-05-15 20:34:07.714083869 +0200
+@@ -1484,6 +1484,20 @@
+ If multiple cards are present, the default limit of 32 ports may
+ need to be increased.
+
++config SERIAL_FSL_LPUART
++ tristate "Freescale lpuart serial port support"
++ select SERIAL_CORE
++ help
++ Support for the on-chip lpuart on some Freescale SOCs.
++
++config SERIAL_FSL_LPUART_CONSOLE
++ bool "Console on Freescale lpuart serial port"
++ depends on SERIAL_FSL_LPUART=y
++ select SERIAL_CORE_CONSOLE
++ help
++ If you have enabled the lpuart serial port on the Freescale SoCs,
++ you can make it the console by answering Y to this option.
++
+ endmenu
+
+ endif # TTY
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/Makefile linux-linaro-stable-mx6/drivers/tty/serial/Makefile
+--- linux-3.10.30.orig/drivers/tty/serial/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/Makefile 2014-05-15 20:34:07.714083869 +0200
+@@ -85,3 +85,4 @@
+ obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
+ obj-$(CONFIG_SERIAL_ARC) += arc_uart.o
+ obj-$(CONFIG_SERIAL_RP2) += rp2.o
++obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/mpc52xx_uart.c linux-linaro-stable-mx6/drivers/tty/serial/mpc52xx_uart.c
+--- linux-3.10.30.orig/drivers/tty/serial/mpc52xx_uart.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/mpc52xx_uart.c 2014-05-15 20:34:07.838084762 +0200
+@@ -84,16 +84,6 @@
+ static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
+ static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
+
+-
+-/* Simple macro to test if a port is console or not. This one is taken
+- * for serial_core.c and maybe should be moved to serial_core.h ? */
+-#ifdef CONFIG_SERIAL_CORE_CONSOLE
+-#define uart_console(port) \
+- ((port)->cons && (port)->cons->index == (port)->line)
+-#else
+-#define uart_console(port) (0)
+-#endif
+-
+ /* ======================================================================== */
+ /* PSC fifo operations for isolating differences between 52xx and 512x */
+ /* ======================================================================== */
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/mxs-auart.c linux-linaro-stable-mx6/drivers/tty/serial/mxs-auart.c
+--- linux-3.10.30.orig/drivers/tty/serial/mxs-auart.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/mxs-auart.c 2014-05-15 20:34:07.850084848 +0200
+@@ -32,7 +32,6 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
+-#include <linux/pinctrl/consumer.h>
+ #include <linux/of_device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/dmaengine.h>
+@@ -1021,7 +1020,6 @@
+ u32 version;
+ int ret = 0;
+ struct resource *r;
+- struct pinctrl *pinctrl;
+
+ s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
+ if (!s) {
+@@ -1035,12 +1033,6 @@
+ else if (ret < 0)
+ goto out_free;
+
+- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+- if (IS_ERR(pinctrl)) {
+- ret = PTR_ERR(pinctrl);
+- goto out_free;
+- }
+-
+ if (of_id) {
+ pdev->id_entry = of_id->data;
+ s->devtype = pdev->id_entry->driver_data;
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/netx-serial.c linux-linaro-stable-mx6/drivers/tty/serial/netx-serial.c
+--- linux-3.10.30.orig/drivers/tty/serial/netx-serial.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/netx-serial.c 2014-05-15 20:34:07.858084907 +0200
+@@ -693,8 +693,6 @@
+ {
+ struct netx_port *sport = platform_get_drvdata(pdev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ if (sport)
+ uart_remove_one_port(&netx_reg, &sport->port);
+
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/pmac_zilog.c linux-linaro-stable-mx6/drivers/tty/serial/pmac_zilog.c
+--- linux-3.10.30.orig/drivers/tty/serial/pmac_zilog.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/pmac_zilog.c 2014-05-15 20:34:07.874085021 +0200
+@@ -1798,7 +1798,6 @@
+
+ uart_remove_one_port(&pmz_uart_reg, &uap->port);
+
+- platform_set_drvdata(pdev, NULL);
+ uap->port.dev = NULL;
+
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/pnx8xxx_uart.c linux-linaro-stable-mx6/drivers/tty/serial/pnx8xxx_uart.c
+--- linux-3.10.30.orig/drivers/tty/serial/pnx8xxx_uart.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/pnx8xxx_uart.c 2014-05-15 20:34:07.874085021 +0200
+@@ -801,8 +801,6 @@
+ {
+ struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ if (sport)
+ uart_remove_one_port(&pnx8xxx_reg, &sport->port);
+
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/pxa.c linux-linaro-stable-mx6/drivers/tty/serial/pxa.c
+--- linux-3.10.30.orig/drivers/tty/serial/pxa.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/pxa.c 2014-05-15 20:34:07.874085021 +0200
+@@ -945,8 +945,6 @@
+ {
+ struct uart_pxa_port *sport = platform_get_drvdata(dev);
+
+- platform_set_drvdata(dev, NULL);
+-
+ uart_remove_one_port(&serial_pxa_reg, &sport->port);
+
+ clk_unprepare(sport->clk);
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/sa1100.c linux-linaro-stable-mx6/drivers/tty/serial/sa1100.c
+--- linux-3.10.30.orig/drivers/tty/serial/sa1100.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/sa1100.c 2014-05-15 20:34:07.886085108 +0200
+@@ -864,8 +864,6 @@
+ {
+ struct sa1100_port *sport = platform_get_drvdata(pdev);
+
+- platform_set_drvdata(pdev, NULL);
+-
+ if (sport)
+ uart_remove_one_port(&sa1100_reg, &sport->port);
+
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/sccnxp.c linux-linaro-stable-mx6/drivers/tty/serial/sccnxp.c
+--- linux-3.10.30.orig/drivers/tty/serial/sccnxp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/sccnxp.c 2014-05-15 20:34:07.898085195 +0200
+@@ -997,8 +997,6 @@
+ }
+
+ err_out:
+- platform_set_drvdata(pdev, NULL);
+-
+ return ret;
+ }
+
+@@ -1016,7 +1014,6 @@
+ uart_remove_one_port(&s->uart, &s->port[i]);
+
+ uart_unregister_driver(&s->uart);
+- platform_set_drvdata(pdev, NULL);
+
+ if (!IS_ERR(s->regulator))
+ return regulator_disable(s->regulator);
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/serial_core.c linux-linaro-stable-mx6/drivers/tty/serial/serial_core.c
+--- linux-3.10.30.orig/drivers/tty/serial/serial_core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/serial_core.c 2014-05-15 20:34:07.910085281 +0200
+@@ -50,12 +50,6 @@
+
+ #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
+
+-#ifdef CONFIG_SERIAL_CORE_CONSOLE
+-#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
+-#else
+-#define uart_console(port) (0)
+-#endif
+-
+ static void uart_change_speed(struct tty_struct *tty, struct uart_state *state,
+ struct ktermios *old_termios);
+ static void uart_wait_until_sent(struct tty_struct *tty, int timeout);
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/sirfsoc_uart.c linux-linaro-stable-mx6/drivers/tty/serial/sirfsoc_uart.c
+--- linux-3.10.30.orig/drivers/tty/serial/sirfsoc_uart.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/sirfsoc_uart.c 2014-05-15 20:34:07.922085368 +0200
+@@ -716,7 +716,6 @@
+ clk_disable_unprepare(sirfport->clk);
+ clk_put(sirfport->clk);
+ clk_err:
+- platform_set_drvdata(pdev, NULL);
+ if (sirfport->hw_flow_ctrl)
+ pinctrl_put(sirfport->p);
+ err:
+@@ -727,7 +726,7 @@
+ {
+ struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
+ struct uart_port *port = &sirfport->port;
+- platform_set_drvdata(pdev, NULL);
++
+ if (sirfport->hw_flow_ctrl)
+ pinctrl_put(sirfport->p);
+ clk_disable_unprepare(sirfport->clk);
+diff -Nur linux-3.10.30.orig/drivers/tty/serial/vt8500_serial.c linux-linaro-stable-mx6/drivers/tty/serial/vt8500_serial.c
+--- linux-3.10.30.orig/drivers/tty/serial/vt8500_serial.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/tty/serial/vt8500_serial.c 2014-05-15 20:34:07.950085569 +0200
+@@ -631,7 +631,6 @@
+ {
+ struct vt8500_port *vt8500_port = platform_get_drvdata(pdev);
+
+- platform_set_drvdata(pdev, NULL);
+ clk_disable_unprepare(vt8500_port->clk);
+ uart_remove_one_port(&vt8500_uart_driver, &vt8500_port->uart);
+
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/bits.h linux-linaro-stable-mx6/drivers/usb/chipidea/bits.h
+--- linux-3.10.30.orig/drivers/usb/chipidea/bits.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/bits.h 2014-05-15 20:34:08.182087241 +0200
+@@ -48,10 +48,25 @@
+ #define PORTSC_SUSP BIT(7)
+ #define PORTSC_HSP BIT(9)
+ #define PORTSC_PTC (0x0FUL << 16)
++#define PORTSC_PHCD(d) ((d) ? BIT(22) : BIT(23))
++/* PTS and PTW for non lpm version only */
++#define PORTSC_PTS(d) \
++ ((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
++#define PORTSC_PTW BIT(28)
++#define PORTSC_STS BIT(29)
+
+ /* DEVLC */
+ #define DEVLC_PSPD (0x03UL << 25)
+-#define DEVLC_PSPD_HS (0x02UL << 25)
++#define DEVLC_PSPD_HS (0x02UL << 25)
++#define DEVLC_PTW BIT(27)
++#define DEVLC_STS BIT(28)
++#define DEVLC_PTS(d) (((d) & 0x7) << 29)
++
++/* Encoding for DEVLC_PTS and PORTSC_PTS */
++#define PTS_UTMI 0
++#define PTS_ULPI 2
++#define PTS_SERIAL 3
++#define PTS_HSIC 4
+
+ /* OTGSC */
+ #define OTGSC_IDPU BIT(5)
+@@ -65,11 +80,21 @@
+ #define OTGSC_ASVIS BIT(18)
+ #define OTGSC_BSVIS BIT(19)
+ #define OTGSC_BSEIS BIT(20)
++#define OTGSC_1MSIS BIT(21)
++#define OTGSC_DPIS BIT(22)
+ #define OTGSC_IDIE BIT(24)
+ #define OTGSC_AVVIE BIT(25)
+ #define OTGSC_ASVIE BIT(26)
+ #define OTGSC_BSVIE BIT(27)
+ #define OTGSC_BSEIE BIT(28)
++#define OTGSC_1MSIE BIT(29)
++#define OTGSC_DPIE BIT(30)
++#define OTGSC_INT_EN_BITS (OTGSC_IDIE | OTGSC_AVVIE | OTGSC_ASVIE \
++ | OTGSC_BSVIE | OTGSC_BSEIE | OTGSC_1MSIE \
++ | OTGSC_DPIE)
++#define OTGSC_INT_STATUS_BITS (OTGSC_IDIS | OTGSC_AVVIS | OTGSC_ASVIS \
++ | OTGSC_BSVIS | OTGSC_BSEIS | OTGSC_1MSIS \
++ | OTGSC_DPIS)
+
+ /* USBMODE */
+ #define USBMODE_CM (0x03UL << 0)
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci13xxx_imx.c linux-linaro-stable-mx6/drivers/usb/chipidea/ci13xxx_imx.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci13xxx_imx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci13xxx_imx.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,274 +0,0 @@
+-/*
+- * Copyright 2012 Freescale Semiconductor, Inc.
+- * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+- * on behalf of DENX Software Engineering GmbH
+- *
+- * The code contained herein is licensed under the GNU General Public
+- * License. You may obtain a copy of the GNU General Public License
+- * Version 2 or later at the following locations:
+- *
+- * http://www.opensource.org/licenses/gpl-license.html
+- * http://www.gnu.org/copyleft/gpl.html
+- */
+-
+-#include <linux/module.h>
+-#include <linux/of_platform.h>
+-#include <linux/of_gpio.h>
+-#include <linux/platform_device.h>
+-#include <linux/pm_runtime.h>
+-#include <linux/dma-mapping.h>
+-#include <linux/usb/chipidea.h>
+-#include <linux/clk.h>
+-#include <linux/regulator/consumer.h>
+-#include <linux/pinctrl/consumer.h>
+-
+-#include "ci.h"
+-#include "ci13xxx_imx.h"
+-
+-#define pdev_to_phy(pdev) \
+- ((struct usb_phy *)platform_get_drvdata(pdev))
+-
+-struct ci13xxx_imx_data {
+- struct device_node *phy_np;
+- struct usb_phy *phy;
+- struct platform_device *ci_pdev;
+- struct clk *clk;
+- struct regulator *reg_vbus;
+-};
+-
+-static const struct usbmisc_ops *usbmisc_ops;
+-
+-/* Common functions shared by usbmisc drivers */
+-
+-int usbmisc_set_ops(const struct usbmisc_ops *ops)
+-{
+- if (usbmisc_ops)
+- return -EBUSY;
+-
+- usbmisc_ops = ops;
+-
+- return 0;
+-}
+-EXPORT_SYMBOL_GPL(usbmisc_set_ops);
+-
+-void usbmisc_unset_ops(const struct usbmisc_ops *ops)
+-{
+- usbmisc_ops = NULL;
+-}
+-EXPORT_SYMBOL_GPL(usbmisc_unset_ops);
+-
+-int usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev)
+-{
+- struct device_node *np = dev->of_node;
+- struct of_phandle_args args;
+- int ret;
+-
+- usbdev->dev = dev;
+-
+- ret = of_parse_phandle_with_args(np, "fsl,usbmisc", "#index-cells",
+- 0, &args);
+- if (ret) {
+- dev_err(dev, "Failed to parse property fsl,usbmisc, errno %d\n",
+- ret);
+- memset(usbdev, 0, sizeof(*usbdev));
+- return ret;
+- }
+- usbdev->index = args.args[0];
+- of_node_put(args.np);
+-
+- if (of_find_property(np, "disable-over-current", NULL))
+- usbdev->disable_oc = 1;
+-
+- if (of_find_property(np, "external-vbus-divider", NULL))
+- usbdev->evdo = 1;
+-
+- return 0;
+-}
+-EXPORT_SYMBOL_GPL(usbmisc_get_init_data);
+-
+-/* End of common functions shared by usbmisc drivers*/
+-
+-static struct ci13xxx_platform_data ci13xxx_imx_platdata = {
+- .name = "ci13xxx_imx",
+- .flags = CI13XXX_REQUIRE_TRANSCEIVER |
+- CI13XXX_PULLUP_ON_VBUS |
+- CI13XXX_DISABLE_STREAMING,
+- .capoffset = DEF_CAPOFFSET,
+-};
+-
+-static int ci13xxx_imx_probe(struct platform_device *pdev)
+-{
+- struct ci13xxx_imx_data *data;
+- struct platform_device *plat_ci, *phy_pdev;
+- struct device_node *phy_np;
+- struct resource *res;
+- struct regulator *reg_vbus;
+- struct pinctrl *pinctrl;
+- int ret;
+-
+- if (of_find_property(pdev->dev.of_node, "fsl,usbmisc", NULL)
+- && !usbmisc_ops)
+- return -EPROBE_DEFER;
+-
+- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+- if (!data) {
+- dev_err(&pdev->dev, "Failed to allocate CI13xxx-IMX data!\n");
+- return -ENOMEM;
+- }
+-
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!res) {
+- dev_err(&pdev->dev, "Can't get device resources!\n");
+- return -ENOENT;
+- }
+-
+- pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+- if (IS_ERR(pinctrl))
+- dev_warn(&pdev->dev, "pinctrl get/select failed, err=%ld\n",
+- PTR_ERR(pinctrl));
+-
+- data->clk = devm_clk_get(&pdev->dev, NULL);
+- if (IS_ERR(data->clk)) {
+- dev_err(&pdev->dev,
+- "Failed to get clock, err=%ld\n", PTR_ERR(data->clk));
+- return PTR_ERR(data->clk);
+- }
+-
+- ret = clk_prepare_enable(data->clk);
+- if (ret) {
+- dev_err(&pdev->dev,
+- "Failed to prepare or enable clock, err=%d\n", ret);
+- return ret;
+- }
+-
+- phy_np = of_parse_phandle(pdev->dev.of_node, "fsl,usbphy", 0);
+- if (phy_np) {
+- data->phy_np = phy_np;
+- phy_pdev = of_find_device_by_node(phy_np);
+- if (phy_pdev) {
+- struct usb_phy *phy;
+- phy = pdev_to_phy(phy_pdev);
+- if (phy &&
+- try_module_get(phy_pdev->dev.driver->owner)) {
+- usb_phy_init(phy);
+- data->phy = phy;
+- }
+- }
+- }
+-
+- /* we only support host now, so enable vbus here */
+- reg_vbus = devm_regulator_get(&pdev->dev, "vbus");
+- if (!IS_ERR(reg_vbus)) {
+- ret = regulator_enable(reg_vbus);
+- if (ret) {
+- dev_err(&pdev->dev,
+- "Failed to enable vbus regulator, err=%d\n",
+- ret);
+- goto put_np;
+- }
+- data->reg_vbus = reg_vbus;
+- } else {
+- reg_vbus = NULL;
+- }
+-
+- ci13xxx_imx_platdata.phy = data->phy;
+-
+- if (!pdev->dev.dma_mask)
+- pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+- if (!pdev->dev.coherent_dma_mask)
+- pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+-
+- if (usbmisc_ops && usbmisc_ops->init) {
+- ret = usbmisc_ops->init(&pdev->dev);
+- if (ret) {
+- dev_err(&pdev->dev,
+- "usbmisc init failed, ret=%d\n", ret);
+- goto err;
+- }
+- }
+-
+- plat_ci = ci13xxx_add_device(&pdev->dev,
+- pdev->resource, pdev->num_resources,
+- &ci13xxx_imx_platdata);
+- if (IS_ERR(plat_ci)) {
+- ret = PTR_ERR(plat_ci);
+- dev_err(&pdev->dev,
+- "Can't register ci_hdrc platform device, err=%d\n",
+- ret);
+- goto err;
+- }
+-
+- if (usbmisc_ops && usbmisc_ops->post) {
+- ret = usbmisc_ops->post(&pdev->dev);
+- if (ret) {
+- dev_err(&pdev->dev,
+- "usbmisc post failed, ret=%d\n", ret);
+- goto put_np;
+- }
+- }
+-
+- data->ci_pdev = plat_ci;
+- platform_set_drvdata(pdev, data);
+-
+- pm_runtime_no_callbacks(&pdev->dev);
+- pm_runtime_enable(&pdev->dev);
+-
+- return 0;
+-
+-err:
+- if (reg_vbus)
+- regulator_disable(reg_vbus);
+-put_np:
+- if (phy_np)
+- of_node_put(phy_np);
+- clk_disable_unprepare(data->clk);
+- return ret;
+-}
+-
+-static int ci13xxx_imx_remove(struct platform_device *pdev)
+-{
+- struct ci13xxx_imx_data *data = platform_get_drvdata(pdev);
+-
+- pm_runtime_disable(&pdev->dev);
+- ci13xxx_remove_device(data->ci_pdev);
+-
+- if (data->reg_vbus)
+- regulator_disable(data->reg_vbus);
+-
+- if (data->phy) {
+- usb_phy_shutdown(data->phy);
+- module_put(data->phy->dev->driver->owner);
+- }
+-
+- of_node_put(data->phy_np);
+-
+- clk_disable_unprepare(data->clk);
+-
+- platform_set_drvdata(pdev, NULL);
+-
+- return 0;
+-}
+-
+-static const struct of_device_id ci13xxx_imx_dt_ids[] = {
+- { .compatible = "fsl,imx27-usb", },
+- { /* sentinel */ }
+-};
+-MODULE_DEVICE_TABLE(of, ci13xxx_imx_dt_ids);
+-
+-static struct platform_driver ci13xxx_imx_driver = {
+- .probe = ci13xxx_imx_probe,
+- .remove = ci13xxx_imx_remove,
+- .driver = {
+- .name = "imx_usb",
+- .owner = THIS_MODULE,
+- .of_match_table = ci13xxx_imx_dt_ids,
+- },
+-};
+-
+-module_platform_driver(ci13xxx_imx_driver);
+-
+-MODULE_ALIAS("platform:imx-usb");
+-MODULE_LICENSE("GPL v2");
+-MODULE_DESCRIPTION("CI13xxx i.MX USB binding");
+-MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
+-MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci13xxx_imx.h linux-linaro-stable-mx6/drivers/usb/chipidea/ci13xxx_imx.h
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci13xxx_imx.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci13xxx_imx.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,31 +0,0 @@
+-/*
+- * Copyright 2012 Freescale Semiconductor, Inc.
+- *
+- * The code contained herein is licensed under the GNU General Public
+- * License. You may obtain a copy of the GNU General Public License
+- * Version 2 or later at the following locations:
+- *
+- * http://www.opensource.org/licenses/gpl-license.html
+- * http://www.gnu.org/copyleft/gpl.html
+- */
+-
+-/* Used to set SoC specific callbacks */
+-struct usbmisc_ops {
+- /* It's called once when probe a usb device */
+- int (*init)(struct device *dev);
+- /* It's called once after adding a usb device */
+- int (*post)(struct device *dev);
+-};
+-
+-struct usbmisc_usb_device {
+- struct device *dev; /* usb controller device */
+- int index;
+-
+- unsigned int disable_oc:1; /* over current detect disabled */
+- unsigned int evdo:1; /* set external vbus divider option */
+-};
+-
+-int usbmisc_set_ops(const struct usbmisc_ops *ops);
+-void usbmisc_unset_ops(const struct usbmisc_ops *ops);
+-int
+-usbmisc_get_init_data(struct device *dev, struct usbmisc_usb_device *usbdev);
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci13xxx_msm.c linux-linaro-stable-mx6/drivers/usb/chipidea/ci13xxx_msm.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci13xxx_msm.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci13xxx_msm.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,99 +0,0 @@
+-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 and
+- * only version 2 as published by the Free Software Foundation.
+- */
+-
+-#include <linux/module.h>
+-#include <linux/platform_device.h>
+-#include <linux/pm_runtime.h>
+-#include <linux/usb/msm_hsusb_hw.h>
+-#include <linux/usb/ulpi.h>
+-#include <linux/usb/gadget.h>
+-#include <linux/usb/chipidea.h>
+-
+-#include "ci.h"
+-
+-#define MSM_USB_BASE (ci->hw_bank.abs)
+-
+-static void ci13xxx_msm_notify_event(struct ci13xxx *ci, unsigned event)
+-{
+- struct device *dev = ci->gadget.dev.parent;
+- int val;
+-
+- switch (event) {
+- case CI13XXX_CONTROLLER_RESET_EVENT:
+- dev_dbg(dev, "CI13XXX_CONTROLLER_RESET_EVENT received\n");
+- writel(0, USB_AHBBURST);
+- writel(0, USB_AHBMODE);
+- break;
+- case CI13XXX_CONTROLLER_STOPPED_EVENT:
+- dev_dbg(dev, "CI13XXX_CONTROLLER_STOPPED_EVENT received\n");
+- /*
+- * Put the transceiver in non-driving mode. Otherwise host
+- * may not detect soft-disconnection.
+- */
+- val = usb_phy_io_read(ci->transceiver, ULPI_FUNC_CTRL);
+- val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
+- val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
+- usb_phy_io_write(ci->transceiver, val, ULPI_FUNC_CTRL);
+- break;
+- default:
+- dev_dbg(dev, "unknown ci13xxx event\n");
+- break;
+- }
+-}
+-
+-static struct ci13xxx_platform_data ci13xxx_msm_platdata = {
+- .name = "ci13xxx_msm",
+- .flags = CI13XXX_REGS_SHARED |
+- CI13XXX_REQUIRE_TRANSCEIVER |
+- CI13XXX_PULLUP_ON_VBUS |
+- CI13XXX_DISABLE_STREAMING,
+-
+- .notify_event = ci13xxx_msm_notify_event,
+-};
+-
+-static int ci13xxx_msm_probe(struct platform_device *pdev)
+-{
+- struct platform_device *plat_ci;
+-
+- dev_dbg(&pdev->dev, "ci13xxx_msm_probe\n");
+-
+- plat_ci = ci13xxx_add_device(&pdev->dev,
+- pdev->resource, pdev->num_resources,
+- &ci13xxx_msm_platdata);
+- if (IS_ERR(plat_ci)) {
+- dev_err(&pdev->dev, "ci13xxx_add_device failed!\n");
+- return PTR_ERR(plat_ci);
+- }
+-
+- platform_set_drvdata(pdev, plat_ci);
+-
+- pm_runtime_no_callbacks(&pdev->dev);
+- pm_runtime_enable(&pdev->dev);
+-
+- return 0;
+-}
+-
+-static int ci13xxx_msm_remove(struct platform_device *pdev)
+-{
+- struct platform_device *plat_ci = platform_get_drvdata(pdev);
+-
+- pm_runtime_disable(&pdev->dev);
+- ci13xxx_remove_device(plat_ci);
+-
+- return 0;
+-}
+-
+-static struct platform_driver ci13xxx_msm_driver = {
+- .probe = ci13xxx_msm_probe,
+- .remove = ci13xxx_msm_remove,
+- .driver = { .name = "msm_hsusb", },
+-};
+-
+-module_platform_driver(ci13xxx_msm_driver);
+-
+-MODULE_ALIAS("platform:msm_hsusb");
+-MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci13xxx_pci.c linux-linaro-stable-mx6/drivers/usb/chipidea/ci13xxx_pci.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci13xxx_pci.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci13xxx_pci.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,158 +0,0 @@
+-/*
+- * ci13xxx_pci.c - MIPS USB IP core family device controller
+- *
+- * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
+- *
+- * Author: David Lopo
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#include <linux/platform_device.h>
+-#include <linux/module.h>
+-#include <linux/pci.h>
+-#include <linux/interrupt.h>
+-#include <linux/usb/gadget.h>
+-#include <linux/usb/chipidea.h>
+-
+-/* driver name */
+-#define UDC_DRIVER_NAME "ci13xxx_pci"
+-
+-/******************************************************************************
+- * PCI block
+- *****************************************************************************/
+-static struct ci13xxx_platform_data pci_platdata = {
+- .name = UDC_DRIVER_NAME,
+- .capoffset = DEF_CAPOFFSET,
+-};
+-
+-static struct ci13xxx_platform_data langwell_pci_platdata = {
+- .name = UDC_DRIVER_NAME,
+- .capoffset = 0,
+-};
+-
+-static struct ci13xxx_platform_data penwell_pci_platdata = {
+- .name = UDC_DRIVER_NAME,
+- .capoffset = 0,
+- .power_budget = 200,
+-};
+-
+-/**
+- * ci13xxx_pci_probe: PCI probe
+- * @pdev: USB device controller being probed
+- * @id: PCI hotplug ID connecting controller to UDC framework
+- *
+- * This function returns an error code
+- * Allocates basic PCI resources for this USB device controller, and then
+- * invokes the udc_probe() method to start the UDC associated with it
+- */
+-static int ci13xxx_pci_probe(struct pci_dev *pdev,
+- const struct pci_device_id *id)
+-{
+- struct ci13xxx_platform_data *platdata = (void *)id->driver_data;
+- struct platform_device *plat_ci;
+- struct resource res[3];
+- int retval = 0, nres = 2;
+-
+- if (!platdata) {
+- dev_err(&pdev->dev, "device doesn't provide driver data\n");
+- return -ENODEV;
+- }
+-
+- retval = pci_enable_device(pdev);
+- if (retval)
+- goto done;
+-
+- if (!pdev->irq) {
+- dev_err(&pdev->dev, "No IRQ, check BIOS/PCI setup!");
+- retval = -ENODEV;
+- goto disable_device;
+- }
+-
+- pci_set_power_state(pdev, PCI_D0);
+- pci_set_master(pdev);
+- pci_try_set_mwi(pdev);
+-
+- memset(res, 0, sizeof(res));
+- res[0].start = pci_resource_start(pdev, 0);
+- res[0].end = pci_resource_end(pdev, 0);
+- res[0].flags = IORESOURCE_MEM;
+- res[1].start = pdev->irq;
+- res[1].flags = IORESOURCE_IRQ;
+-
+- plat_ci = ci13xxx_add_device(&pdev->dev, res, nres, platdata);
+- if (IS_ERR(plat_ci)) {
+- dev_err(&pdev->dev, "ci13xxx_add_device failed!\n");
+- retval = PTR_ERR(plat_ci);
+- goto disable_device;
+- }
+-
+- pci_set_drvdata(pdev, plat_ci);
+-
+- return 0;
+-
+- disable_device:
+- pci_disable_device(pdev);
+- done:
+- return retval;
+-}
+-
+-/**
+- * ci13xxx_pci_remove: PCI remove
+- * @pdev: USB Device Controller being removed
+- *
+- * Reverses the effect of ci13xxx_pci_probe(),
+- * first invoking the udc_remove() and then releases
+- * all PCI resources allocated for this USB device controller
+- */
+-static void ci13xxx_pci_remove(struct pci_dev *pdev)
+-{
+- struct platform_device *plat_ci = pci_get_drvdata(pdev);
+-
+- ci13xxx_remove_device(plat_ci);
+- pci_set_drvdata(pdev, NULL);
+- pci_disable_device(pdev);
+-}
+-
+-/**
+- * PCI device table
+- * PCI device structure
+- *
+- * Check "pci.h" for details
+- */
+-static DEFINE_PCI_DEVICE_TABLE(ci13xxx_pci_id_table) = {
+- {
+- PCI_DEVICE(0x153F, 0x1004),
+- .driver_data = (kernel_ulong_t)&pci_platdata,
+- },
+- {
+- PCI_DEVICE(0x153F, 0x1006),
+- .driver_data = (kernel_ulong_t)&pci_platdata,
+- },
+- {
+- PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811),
+- .driver_data = (kernel_ulong_t)&langwell_pci_platdata,
+- },
+- {
+- PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829),
+- .driver_data = (kernel_ulong_t)&penwell_pci_platdata,
+- },
+- { 0, 0, 0, 0, 0, 0, 0 /* end: all zeroes */ }
+-};
+-MODULE_DEVICE_TABLE(pci, ci13xxx_pci_id_table);
+-
+-static struct pci_driver ci13xxx_pci_driver = {
+- .name = UDC_DRIVER_NAME,
+- .id_table = ci13xxx_pci_id_table,
+- .probe = ci13xxx_pci_probe,
+- .remove = ci13xxx_pci_remove,
+-};
+-
+-module_pci_driver(ci13xxx_pci_driver);
+-
+-MODULE_AUTHOR("MIPS - David Lopo <dlopo@chipidea.mips.com>");
+-MODULE_DESCRIPTION("MIPS CI13XXX USB Peripheral Controller");
+-MODULE_LICENSE("GPL");
+-MODULE_VERSION("June 2008");
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci.h linux-linaro-stable-mx6/drivers/usb/chipidea/ci.h
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci.h 2014-05-15 20:34:08.182087241 +0200
+@@ -22,14 +22,14 @@
+ * DEFINE
+ *****************************************************************************/
+ #define TD_PAGE_COUNT 5
+-#define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
++#define CI_HDRC_PAGE_SIZE 4096ul /* page size for TD's */
+ #define ENDPT_MAX 32
+
+ /******************************************************************************
+ * STRUCTURES
+ *****************************************************************************/
+ /**
+- * struct ci13xxx_ep - endpoint representation
++ * struct ci_hw_ep - endpoint representation
+ * @ep: endpoint structure for gadget drivers
+ * @dir: endpoint direction (TX/RX)
+ * @num: endpoint number
+@@ -41,7 +41,7 @@
+ * @lock: pointer to controller's spinlock
+ * @td_pool: pointer to controller's TD pool
+ */
+-struct ci13xxx_ep {
++struct ci_hw_ep {
+ struct usb_ep ep;
+ u8 dir;
+ u8 num;
+@@ -49,15 +49,16 @@
+ char name[16];
+ struct {
+ struct list_head queue;
+- struct ci13xxx_qh *ptr;
++ struct ci_hw_qh *ptr;
+ dma_addr_t dma;
+ } qh;
+ int wedge;
+
+ /* global resources */
+- struct ci13xxx *ci;
++ struct ci_hdrc *ci;
+ spinlock_t *lock;
+ struct dma_pool *td_pool;
++ struct td_node *pending_td;
+ };
+
+ enum ci_role {
+@@ -74,9 +75,9 @@
+ * name: role name string (host/gadget)
+ */
+ struct ci_role_driver {
+- int (*start)(struct ci13xxx *);
+- void (*stop)(struct ci13xxx *);
+- irqreturn_t (*irq)(struct ci13xxx *);
++ int (*start)(struct ci_hdrc *);
++ void (*stop)(struct ci_hdrc *);
++ irqreturn_t (*irq)(struct ci_hdrc *);
+ const char *name;
+ };
+
+@@ -101,7 +102,7 @@
+ };
+
+ /**
+- * struct ci13xxx - chipidea device representation
++ * struct ci_hdrc - chipidea device representation
+ * @dev: pointer to parent device
+ * @lock: access synchronization
+ * @hw_bank: hardware register mapping
+@@ -109,14 +110,14 @@
+ * @roles: array of supported roles for this controller
+ * @role: current role
+ * @is_otg: if the device is otg-capable
+- * @work: work for role changing
+- * @wq: workqueue thread
++ * @otg_task: the thread for handling otg task
++ * @otg_wait: the otg event waitqueue head
+ * @qh_pool: allocation pool for queue heads
+ * @td_pool: allocation pool for transfer descriptors
+ * @gadget: device side representation for peripheral controller
+ * @driver: gadget driver
+ * @hw_ep_max: total number of endpoints supported by hardware
+- * @ci13xxx_ep: array of endpoints
++ * @ci_hw_ep: array of endpoints
+ * @ep0_dir: ep0 direction
+ * @ep0out: pointer to ep0 OUT endpoint
+ * @ep0in: pointer to ep0 IN endpoint
+@@ -131,8 +132,16 @@
+ * @transceiver: pointer to USB PHY, if any
+ * @hcd: pointer to usb_hcd for ehci host driver
+ * @debugfs: root dentry for this controller in debugfs
++ * @id_event: indicates there is an id event, and handled at ci_otg_work
++ * @b_sess_valid_event: indicates there is a vbus event, and handled
++ * at ci_otg_work
++ * @imx28_write_fix: for fsl imx28 write
++ * @supports_runtime_pm: if runtime pm is supported
++ * @in_lpm: if the core in low power mode
++ * @wakeup_int: if wakeup interrupt occur
++ * @timer: timer to delay clock closing
+ */
+-struct ci13xxx {
++struct ci_hdrc {
+ struct device *dev;
+ spinlock_t lock;
+ struct hw_bank hw_bank;
+@@ -140,8 +149,8 @@
+ struct ci_role_driver *roles[CI_ROLE_END];
+ enum ci_role role;
+ bool is_otg;
+- struct work_struct work;
+- struct workqueue_struct *wq;
++ struct task_struct *otg_task;
++ wait_queue_head_t otg_wait;
+
+ struct dma_pool *qh_pool;
+ struct dma_pool *td_pool;
+@@ -149,9 +158,9 @@
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ unsigned hw_ep_max;
+- struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX];
++ struct ci_hw_ep ci_hw_ep[ENDPT_MAX];
+ u32 ep0_dir;
+- struct ci13xxx_ep *ep0out, *ep0in;
++ struct ci_hw_ep *ep0out, *ep0in;
+
+ struct usb_request *status;
+ bool setaddr;
+@@ -160,22 +169,30 @@
+ u8 suspended;
+ u8 test_mode;
+
+- struct ci13xxx_platform_data *platdata;
++ struct ci_hdrc_platform_data *platdata;
+ int vbus_active;
+ /* FIXME: some day, we'll not use global phy */
+ bool global_phy;
+ struct usb_phy *transceiver;
+ struct usb_hcd *hcd;
+ struct dentry *debugfs;
++ bool id_event;
++ bool b_sess_valid_event;
++ /* imx28 needs swp instruction for writing */
++ bool imx28_write_fix;
++ bool supports_runtime_pm;
++ bool in_lpm;
++ bool wakeup_int;
++ struct timer_list timer;
+ };
+
+-static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
++static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
+ {
+ BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
+ return ci->roles[ci->role];
+ }
+
+-static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
++static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role)
+ {
+ int ret;
+
+@@ -191,7 +208,7 @@
+ return ret;
+ }
+
+-static inline void ci_role_stop(struct ci13xxx *ci)
++static inline void ci_role_stop(struct ci_hdrc *ci)
+ {
+ enum ci_role role = ci->role;
+
+@@ -210,7 +227,7 @@
+ #define REG_BITS (32)
+
+ /* register indices */
+-enum ci13xxx_regs {
++enum ci_hw_regs {
+ CAP_CAPLENGTH,
+ CAP_HCCPARAMS,
+ CAP_DCCPARAMS,
+@@ -242,25 +259,45 @@
+ *
+ * This function returns register contents
+ */
+-static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
++static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)
+ {
+ return ioread32(ci->hw_bank.regmap[reg]) & mask;
+ }
+
++#ifdef CONFIG_SOC_IMX28
++static inline void imx28_ci_writel(u32 val32, volatile u32 *addr)
++{
++ __asm__ ("swp %0, %0, [%1]" : : "r"(val32), "r"(addr));
++}
++#endif
++
++static inline void __hw_write(struct ci_hdrc *ci, u32 val,
++ void __iomem *addr)
++{
++#ifdef CONFIG_SOC_IMX28
++ if (ci->imx28_write_fix)
++ imx28_ci_writel(val, addr);
++ else
++ iowrite32(val, addr);
++#else
++ iowrite32(val, addr);
++#endif
++}
++
+ /**
+ * hw_write: writes to a hw register
+ * @reg: register index
+ * @mask: bitfield mask
+ * @data: new value
+ */
+-static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
++static inline void hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
+ u32 mask, u32 data)
+ {
+ if (~mask)
+ data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
+ | (data & mask);
+
+- iowrite32(data, ci->hw_bank.regmap[reg]);
++ __hw_write(ci, data, ci->hw_bank.regmap[reg]);
+ }
+
+ /**
+@@ -270,12 +307,12 @@
+ *
+ * This function returns register contents
+ */
+-static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
++static inline u32 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg,
+ u32 mask)
+ {
+ u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
+
+- iowrite32(val, ci->hw_bank.regmap[reg]);
++ __hw_write(ci, val, ci->hw_bank.regmap[reg]);
+ return val;
+ }
+
+@@ -287,7 +324,7 @@
+ *
+ * This function returns register contents
+ */
+-static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
++static inline u32 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg,
+ u32 mask, u32 data)
+ {
+ u32 val = hw_read(ci, reg, ~0);
+@@ -296,10 +333,13 @@
+ return (val & mask) >> __ffs(mask);
+ }
+
+-int hw_device_reset(struct ci13xxx *ci, u32 mode);
++int hw_device_reset(struct ci_hdrc *ci, u32 mode);
++
++int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
+
+-int hw_port_test_set(struct ci13xxx *ci, u8 mode);
++u8 hw_port_test_get(struct ci_hdrc *ci);
+
+-u8 hw_port_test_get(struct ci13xxx *ci);
++int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
++ u32 value, unsigned int timeout_ms);
+
+ #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci_hdrc_imx.c linux-linaro-stable-mx6/drivers/usb/chipidea/ci_hdrc_imx.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci_hdrc_imx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci_hdrc_imx.c 2014-05-15 20:34:08.182087241 +0200
+@@ -0,0 +1,444 @@
++/*
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
++ * on behalf of DENX Software Engineering GmbH
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/dma-mapping.h>
++#include <linux/usb/chipidea.h>
++#include <linux/clk.h>
++#include <linux/busfreq-imx6.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/power/imx6_usb_charger.h>
++
++#include "ci.h"
++#include "ci_hdrc_imx.h"
++
++#define CI_HDRC_IMX_IMX28_WRITE_FIX BIT(0)
++#define CI_HDRC_IMX_SUPPORT_RUNTIME_PM BIT(1)
++#define CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK BIT(2)
++
++struct ci_hdrc_imx_platform_flag {
++ unsigned int flags;
++};
++
++static const struct ci_hdrc_imx_platform_flag imx27_usb_data = {
++};
++
++static const struct ci_hdrc_imx_platform_flag imx23_usb_data = {
++ .flags = CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK,
++};
++
++static const struct ci_hdrc_imx_platform_flag imx28_usb_data = {
++ .flags = CI_HDRC_IMX_IMX28_WRITE_FIX |
++ CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK,
++};
++
++static const struct ci_hdrc_imx_platform_flag imx6q_usb_data = {
++ .flags = CI_HDRC_IMX_SUPPORT_RUNTIME_PM |
++ CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK,
++};
++
++static const struct ci_hdrc_imx_platform_flag imx6sl_usb_data = {
++ .flags = CI_HDRC_IMX_SUPPORT_RUNTIME_PM,
++};
++
++static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
++ { .compatible = "fsl,imx6sl-usb", .data = &imx6sl_usb_data},
++ { .compatible = "fsl,imx6q-usb", .data = &imx6q_usb_data},
++ { .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
++ { .compatible = "fsl,imx23-usb", .data = &imx23_usb_data},
++ { .compatible = "fsl,imx27-usb", .data = &imx27_usb_data},
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ci_hdrc_imx_dt_ids);
++
++struct ci_hdrc_imx_data {
++ struct usb_phy *phy;
++ struct platform_device *ci_pdev;
++ struct clk *clk;
++ struct imx_usbmisc_data *usbmisc_data;
++ bool supports_runtime_pm;
++ bool in_lpm;
++ bool imx6_usb_charger_detection;
++ struct usb_charger charger;
++};
++
++/* Common functions shared by usbmisc drivers */
++
++static struct imx_usbmisc_data *usbmisc_get_init_data(struct device *dev)
++{
++ struct device_node *np = dev->of_node;
++ struct of_phandle_args args;
++ struct imx_usbmisc_data *data;
++ int ret;
++
++ /*
++ * In case the fsl,usbmisc property is not present this device doesn't
++ * need usbmisc. Return NULL (which is no error here)
++ */
++ if (!of_get_property(np, "fsl,usbmisc", NULL))
++ return NULL;
++
++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
++ if (!data)
++ return ERR_PTR(-ENOMEM);
++
++ ret = of_parse_phandle_with_args(np, "fsl,usbmisc", "#index-cells",
++ 0, &args);
++ if (ret) {
++ dev_err(dev, "Failed to parse property fsl,usbmisc, errno %d\n",
++ ret);
++ return ERR_PTR(ret);
++ }
++
++ data->index = args.args[0];
++ of_node_put(args.np);
++
++ if (of_find_property(np, "disable-over-current", NULL))
++ data->disable_oc = 1;
++
++ if (of_find_property(np, "external-vbus-divider", NULL))
++ data->evdo = 1;
++
++ return data;
++}
++
++/* End of common functions shared by usbmisc drivers*/
++
++static int ci_hdrc_imx_notify_event(struct ci_hdrc *ci, unsigned event)
++{
++ struct device *dev = ci->dev->parent;
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret = 0;
++
++ switch (event) {
++ case CI_HDRC_CONTROLLER_CHARGER_EVENT:
++ if (!data->imx6_usb_charger_detection)
++ return ret;
++ if (ci->vbus_active) {
++ ret = imx6_usb_vbus_connect(&data->charger);
++ if (!ret && data->charger.psy.type
++ != POWER_SUPPLY_TYPE_USB)
++ ret = CI_HDRC_NOTIFY_RET_DEFER_EVENT;
++ } else {
++ ret = imx6_usb_vbus_disconnect(&data->charger);
++ }
++ break;
++ case CI_HDRC_CONTROLLER_CHARGER_POST_EVENT:
++ if (!data->imx6_usb_charger_detection)
++ return ret;
++ imx6_usb_charger_detect_post(&data->charger);
++ break;
++ default:
++ dev_dbg(dev, "unknown event\n");
++ }
++
++ return ret;
++}
++
++static int ci_hdrc_imx_probe(struct platform_device *pdev)
++{
++ struct ci_hdrc_imx_data *data;
++ struct ci_hdrc_platform_data pdata = {
++ .name = "ci_hdrc_imx",
++ .capoffset = DEF_CAPOFFSET,
++ .flags = CI_HDRC_REQUIRE_TRANSCEIVER |
++ CI_HDRC_DISABLE_STREAMING,
++ .notify_event = ci_hdrc_imx_notify_event,
++ };
++ int ret;
++ const struct of_device_id *of_id =
++ of_match_device(ci_hdrc_imx_dt_ids, &pdev->dev);
++ const struct ci_hdrc_imx_platform_flag *imx_platform_flag = of_id->data;
++ struct device_node *np = pdev->dev.of_node;
++
++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++ if (!data) {
++ dev_err(&pdev->dev, "Failed to allocate ci_hdrc-imx data!\n");
++ return -ENOMEM;
++ }
++
++ platform_set_drvdata(pdev, data);
++
++ data->usbmisc_data = usbmisc_get_init_data(&pdev->dev);
++ if (IS_ERR(data->usbmisc_data))
++ return PTR_ERR(data->usbmisc_data);
++
++ data->clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(data->clk)) {
++ dev_err(&pdev->dev,
++ "Failed to get clock, err=%ld\n", PTR_ERR(data->clk));
++ return PTR_ERR(data->clk);
++ }
++
++ request_bus_freq(BUS_FREQ_HIGH);
++ ret = clk_prepare_enable(data->clk);
++ if (ret) {
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_err(&pdev->dev,
++ "Failed to prepare or enable clock, err=%d\n", ret);
++ return ret;
++ }
++
++ data->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "fsl,usbphy", 0);
++ if (IS_ERR(data->phy)) {
++ ret = PTR_ERR(data->phy);
++ goto err_clk;
++ }
++
++ pdata.phy = data->phy;
++
++ if (!pdev->dev.dma_mask)
++ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
++ if (!pdev->dev.coherent_dma_mask)
++ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++
++ if (imx_platform_flag->flags & CI_HDRC_IMX_IMX28_WRITE_FIX)
++ pdata.flags |= CI_HDRC_IMX28_WRITE_FIX;
++
++ if (imx_platform_flag->flags & CI_HDRC_IMX_SUPPORT_RUNTIME_PM) {
++ pdata.flags |= CI_HDRC_SUPPORTS_RUNTIME_PM;
++ data->supports_runtime_pm = true;
++ }
++
++ if (imx_platform_flag->flags & CI_HDRC_IMX_MXS_PHY_EHCI_QUIRK)
++ pdata.flags |= CI_HDRC_IMX_EHCI_QUIRK;
++
++ if (data->usbmisc_data) {
++ ret = imx_usbmisc_init(data->usbmisc_data);
++ if (ret) {
++ dev_err(&pdev->dev, "usbmisc init failed, ret=%d\n",
++ ret);
++ goto err_clk;
++ }
++ }
++
++ if (of_find_property(np, "imx6-usb-charger-detection", NULL) &&
++ IS_ENABLED(CONFIG_IMX6_USB_CHARGER))
++ data->imx6_usb_charger_detection = true;
++
++ if (data->imx6_usb_charger_detection) {
++ data->charger.anatop = syscon_regmap_lookup_by_phandle
++ (np, "fsl,anatop");
++ if (IS_ERR(data->charger.anatop)) {
++ dev_dbg(&pdev->dev,
++ "failed to find regmap for anatop\n");
++ ret = PTR_ERR(data->charger.anatop);
++ goto err_clk;
++ }
++ data->charger.dev = &pdev->dev;
++ ret = imx6_usb_create_charger(&data->charger,
++ "imx6_usb_charger");
++ if (ret)
++ goto err_clk;
++ dev_dbg(&pdev->dev, "USB Charger is created\n");
++ }
++
++ data->ci_pdev = ci_hdrc_add_device(&pdev->dev,
++ pdev->resource, pdev->num_resources,
++ &pdata);
++ if (IS_ERR(data->ci_pdev)) {
++ ret = PTR_ERR(data->ci_pdev);
++ dev_err(&pdev->dev,
++ "Can't register ci_hdrc platform device, err=%d\n",
++ ret);
++ goto remove_charger;
++ }
++
++ if (data->usbmisc_data) {
++ ret = imx_usbmisc_init_post(data->usbmisc_data);
++ if (ret) {
++ dev_err(&pdev->dev, "usbmisc post failed, ret=%d\n",
++ ret);
++ goto disable_device;
++ }
++ }
++
++ if (data->usbmisc_data) {
++ ret = imx_usbmisc_set_wakeup(data->usbmisc_data, false);
++ if (ret) {
++ dev_err(&pdev->dev, "usbmisc set_wakeup failed, ret=%d\n",
++ ret);
++ goto disable_device;
++ }
++ }
++
++ device_set_wakeup_capable(&pdev->dev, true);
++
++ if (data->supports_runtime_pm) {
++ pm_runtime_set_active(&pdev->dev);
++ pm_runtime_enable(&pdev->dev);
++ }
++
++ return 0;
++
++disable_device:
++ ci_hdrc_remove_device(data->ci_pdev);
++remove_charger:
++ if (data->imx6_usb_charger_detection)
++ imx6_usb_remove_charger(&data->charger);
++err_clk:
++ clk_disable_unprepare(data->clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++ return ret;
++}
++
++static int ci_hdrc_imx_remove(struct platform_device *pdev)
++{
++ struct ci_hdrc_imx_data *data = platform_get_drvdata(pdev);
++
++ ci_hdrc_remove_device(data->ci_pdev);
++ if (data->supports_runtime_pm) {
++ pm_runtime_get_sync(&pdev->dev);
++ pm_runtime_disable(&pdev->dev);
++ pm_runtime_put_noidle(&pdev->dev);
++ }
++ clk_disable_unprepare(data->clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++ if (data->imx6_usb_charger_detection)
++ imx6_usb_remove_charger(&data->charger);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int imx_controller_suspend(struct device *dev)
++{
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret;
++
++ dev_dbg(dev, "at %s\n", __func__);
++
++ if (data->in_lpm)
++ return 0;
++
++ if (data->usbmisc_data) {
++ ret = imx_usbmisc_set_wakeup(data->usbmisc_data, true);
++ if (ret) {
++ dev_err(dev,
++ "usbmisc set_wakeup failed, ret=%d\n",
++ ret);
++ return ret;
++ }
++ }
++
++ clk_disable_unprepare(data->clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++ data->in_lpm = true;
++
++ return 0;
++}
++
++static int imx_controller_resume(struct device *dev)
++{
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret = 0;
++
++ dev_dbg(dev, "at %s\n", __func__);
++
++ if (!data->in_lpm)
++ return 0;
++
++ request_bus_freq(BUS_FREQ_HIGH);
++ ret = clk_prepare_enable(data->clk);
++ if (ret) {
++ release_bus_freq(BUS_FREQ_HIGH);
++ return ret;
++ }
++
++ data->in_lpm = false;
++
++ if (data->usbmisc_data) {
++ ret = imx_usbmisc_set_wakeup(data->usbmisc_data, false);
++ if (ret) {
++ dev_err(dev,
++ "usbmisc set_wakeup failed, ret=%d\n",
++ ret);
++ ret = -EINVAL;
++ goto clk_disable;
++ }
++ }
++
++ return 0;
++
++clk_disable:
++ clk_disable_unprepare(data->clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++
++ return ret;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int ci_hdrc_imx_suspend(struct device *dev)
++{
++ return imx_controller_suspend(dev);
++}
++
++static int ci_hdrc_imx_resume(struct device *dev)
++{
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret;
++
++ ret = imx_controller_resume(dev);
++ if (!ret && data->supports_runtime_pm) {
++ pm_runtime_disable(dev);
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ }
++
++ return ret;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++#ifdef CONFIG_PM_RUNTIME
++static int ci_hdrc_imx_runtime_suspend(struct device *dev)
++{
++ return imx_controller_suspend(dev);
++}
++
++static int ci_hdrc_imx_runtime_resume(struct device *dev)
++{
++ return imx_controller_resume(dev);
++}
++#endif /* CONFIG_PM_RUNTIME */
++
++#endif /* CONFIG_PM */
++static const struct dev_pm_ops ci_hdrc_imx_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(ci_hdrc_imx_suspend, ci_hdrc_imx_resume)
++ SET_RUNTIME_PM_OPS(ci_hdrc_imx_runtime_suspend,
++ ci_hdrc_imx_runtime_resume, NULL)
++};
++
++static struct platform_driver ci_hdrc_imx_driver = {
++ .probe = ci_hdrc_imx_probe,
++ .remove = ci_hdrc_imx_remove,
++ .driver = {
++ .name = "imx_usb",
++ .owner = THIS_MODULE,
++ .of_match_table = ci_hdrc_imx_dt_ids,
++ .pm = &ci_hdrc_imx_pm_ops,
++ },
++};
++
++module_platform_driver(ci_hdrc_imx_driver);
++
++MODULE_ALIAS("platform:imx-usb");
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("CI HDRC i.MX USB binding");
++MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
++MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci_hdrc_imx.h linux-linaro-stable-mx6/drivers/usb/chipidea/ci_hdrc_imx.h
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci_hdrc_imx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci_hdrc_imx.h 2014-05-15 20:34:08.202087385 +0200
+@@ -0,0 +1,21 @@
++/*
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++struct imx_usbmisc_data {
++ int index;
++
++ unsigned int disable_oc:1; /* over current detect disabled */
++ unsigned int evdo:1; /* set external vbus divider option */
++};
++
++int imx_usbmisc_init(struct imx_usbmisc_data *);
++int imx_usbmisc_init_post(struct imx_usbmisc_data *);
++int imx_usbmisc_set_wakeup(struct imx_usbmisc_data *, bool);
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci_hdrc_msm.c linux-linaro-stable-mx6/drivers/usb/chipidea/ci_hdrc_msm.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci_hdrc_msm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci_hdrc_msm.c 2014-05-15 20:34:08.202087385 +0200
+@@ -0,0 +1,101 @@
++/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/usb/msm_hsusb_hw.h>
++#include <linux/usb/ulpi.h>
++#include <linux/usb/gadget.h>
++#include <linux/usb/chipidea.h>
++
++#include "ci.h"
++
++#define MSM_USB_BASE (ci->hw_bank.abs)
++
++static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
++{
++ struct device *dev = ci->gadget.dev.parent;
++ int val;
++
++ switch (event) {
++ case CI_HDRC_CONTROLLER_RESET_EVENT:
++ dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");
++ writel(0, USB_AHBBURST);
++ writel(0, USB_AHBMODE);
++ break;
++ case CI_HDRC_CONTROLLER_STOPPED_EVENT:
++ dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
++ /*
++ * Put the transceiver in non-driving mode. Otherwise host
++ * may not detect soft-disconnection.
++ */
++ val = usb_phy_io_read(ci->transceiver, ULPI_FUNC_CTRL);
++ val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
++ val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
++ usb_phy_io_write(ci->transceiver, val, ULPI_FUNC_CTRL);
++ break;
++ default:
++ dev_dbg(dev, "unknown ci_hdrc event\n");
++ break;
++ }
++
++ return 0;
++}
++
++static struct ci_hdrc_platform_data ci_hdrc_msm_platdata = {
++ .name = "ci_hdrc_msm",
++ .flags = CI_HDRC_REGS_SHARED |
++ CI_HDRC_REQUIRE_TRANSCEIVER |
++ CI_HDRC_DISABLE_STREAMING,
++
++ .notify_event = ci_hdrc_msm_notify_event,
++};
++
++static int ci_hdrc_msm_probe(struct platform_device *pdev)
++{
++ struct platform_device *plat_ci;
++
++ dev_dbg(&pdev->dev, "ci_hdrc_msm_probe\n");
++
++ plat_ci = ci_hdrc_add_device(&pdev->dev,
++ pdev->resource, pdev->num_resources,
++ &ci_hdrc_msm_platdata);
++ if (IS_ERR(plat_ci)) {
++ dev_err(&pdev->dev, "ci_hdrc_add_device failed!\n");
++ return PTR_ERR(plat_ci);
++ }
++
++ platform_set_drvdata(pdev, plat_ci);
++
++ pm_runtime_no_callbacks(&pdev->dev);
++ pm_runtime_enable(&pdev->dev);
++
++ return 0;
++}
++
++static int ci_hdrc_msm_remove(struct platform_device *pdev)
++{
++ struct platform_device *plat_ci = platform_get_drvdata(pdev);
++
++ pm_runtime_disable(&pdev->dev);
++ ci_hdrc_remove_device(plat_ci);
++
++ return 0;
++}
++
++static struct platform_driver ci_hdrc_msm_driver = {
++ .probe = ci_hdrc_msm_probe,
++ .remove = ci_hdrc_msm_remove,
++ .driver = { .name = "msm_hsusb", },
++};
++
++module_platform_driver(ci_hdrc_msm_driver);
++
++MODULE_ALIAS("platform:msm_hsusb");
++MODULE_ALIAS("platform:ci13xxx_msm");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/ci_hdrc_pci.c linux-linaro-stable-mx6/drivers/usb/chipidea/ci_hdrc_pci.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/ci_hdrc_pci.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/ci_hdrc_pci.c 2014-05-15 20:34:08.202087385 +0200
+@@ -0,0 +1,150 @@
++/*
++ * ci_hdrc_pci.c - MIPS USB IP core family device controller
++ *
++ * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
++ *
++ * Author: David Lopo
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/module.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include <linux/usb/gadget.h>
++#include <linux/usb/chipidea.h>
++
++/* driver name */
++#define UDC_DRIVER_NAME "ci_hdrc_pci"
++
++/******************************************************************************
++ * PCI block
++ *****************************************************************************/
++static struct ci_hdrc_platform_data pci_platdata = {
++ .name = UDC_DRIVER_NAME,
++ .capoffset = DEF_CAPOFFSET,
++};
++
++static struct ci_hdrc_platform_data langwell_pci_platdata = {
++ .name = UDC_DRIVER_NAME,
++ .capoffset = 0,
++};
++
++static struct ci_hdrc_platform_data penwell_pci_platdata = {
++ .name = UDC_DRIVER_NAME,
++ .capoffset = 0,
++ .power_budget = 200,
++};
++
++/**
++ * ci_hdrc_pci_probe: PCI probe
++ * @pdev: USB device controller being probed
++ * @id: PCI hotplug ID connecting controller to UDC framework
++ *
++ * This function returns an error code
++ * Allocates basic PCI resources for this USB device controller, and then
++ * invokes the udc_probe() method to start the UDC associated with it
++ */
++static int ci_hdrc_pci_probe(struct pci_dev *pdev,
++ const struct pci_device_id *id)
++{
++ struct ci_hdrc_platform_data *platdata = (void *)id->driver_data;
++ struct platform_device *plat_ci;
++ struct resource res[3];
++ int retval = 0, nres = 2;
++
++ if (!platdata) {
++ dev_err(&pdev->dev, "device doesn't provide driver data\n");
++ return -ENODEV;
++ }
++
++ retval = pcim_enable_device(pdev);
++ if (retval)
++ return retval;
++
++ if (!pdev->irq) {
++ dev_err(&pdev->dev, "No IRQ, check BIOS/PCI setup!");
++ return -ENODEV;
++ }
++
++ pci_set_power_state(pdev, PCI_D0);
++ pci_set_master(pdev);
++ pci_try_set_mwi(pdev);
++
++ memset(res, 0, sizeof(res));
++ res[0].start = pci_resource_start(pdev, 0);
++ res[0].end = pci_resource_end(pdev, 0);
++ res[0].flags = IORESOURCE_MEM;
++ res[1].start = pdev->irq;
++ res[1].flags = IORESOURCE_IRQ;
++
++ plat_ci = ci_hdrc_add_device(&pdev->dev, res, nres, platdata);
++ if (IS_ERR(plat_ci)) {
++ dev_err(&pdev->dev, "ci_hdrc_add_device failed!\n");
++ return PTR_ERR(plat_ci);
++ }
++
++ pci_set_drvdata(pdev, plat_ci);
++
++ return 0;
++}
++
++/**
++ * ci_hdrc_pci_remove: PCI remove
++ * @pdev: USB Device Controller being removed
++ *
++ * Reverses the effect of ci_hdrc_pci_probe(),
++ * first invoking the udc_remove() and then releases
++ * all PCI resources allocated for this USB device controller
++ */
++static void ci_hdrc_pci_remove(struct pci_dev *pdev)
++{
++ struct platform_device *plat_ci = pci_get_drvdata(pdev);
++
++ ci_hdrc_remove_device(plat_ci);
++}
++
++/**
++ * PCI device table
++ * PCI device structure
++ *
++ * Check "pci.h" for details
++ */
++static DEFINE_PCI_DEVICE_TABLE(ci_hdrc_pci_id_table) = {
++ {
++ PCI_DEVICE(0x153F, 0x1004),
++ .driver_data = (kernel_ulong_t)&pci_platdata,
++ },
++ {
++ PCI_DEVICE(0x153F, 0x1006),
++ .driver_data = (kernel_ulong_t)&pci_platdata,
++ },
++ {
++ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811),
++ .driver_data = (kernel_ulong_t)&langwell_pci_platdata,
++ },
++ {
++ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829),
++ .driver_data = (kernel_ulong_t)&penwell_pci_platdata,
++ },
++ { 0, 0, 0, 0, 0, 0, 0 /* end: all zeroes */ }
++};
++MODULE_DEVICE_TABLE(pci, ci_hdrc_pci_id_table);
++
++static struct pci_driver ci_hdrc_pci_driver = {
++ .name = UDC_DRIVER_NAME,
++ .id_table = ci_hdrc_pci_id_table,
++ .probe = ci_hdrc_pci_probe,
++ .remove = ci_hdrc_pci_remove,
++};
++
++module_pci_driver(ci_hdrc_pci_driver);
++
++MODULE_AUTHOR("MIPS - David Lopo <dlopo@chipidea.mips.com>");
++MODULE_DESCRIPTION("MIPS CI13XXX USB Peripheral Controller");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("June 2008");
++MODULE_ALIAS("platform:ci13xxx_pci");
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/core.c linux-linaro-stable-mx6/drivers/usb/chipidea/core.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/core.c 2014-05-15 20:34:08.202087385 +0200
+@@ -43,8 +43,7 @@
+ *
+ * TODO List
+ * - OTG
+- * - Isochronous & Interrupt Traffic
+- * - Handle requests which spawns into several TDs
++ * - Interrupt Traffic
+ * - GET_STATUS(device) - always reports 0
+ * - Gadget API (majority of optional features)
+ * - Suspend & Remote Wakeup
+@@ -64,12 +63,16 @@
+ #include <linux/usb/gadget.h>
+ #include <linux/usb/otg.h>
+ #include <linux/usb/chipidea.h>
++#include <linux/usb/of.h>
++#include <linux/phy.h>
++#include <linux/regulator/consumer.h>
+
+ #include "ci.h"
+ #include "udc.h"
+ #include "bits.h"
+ #include "host.h"
+ #include "debug.h"
++#include "otg.h"
+
+ /* Controller register map */
+ static uintptr_t ci_regs_nolpm[] = {
+@@ -116,7 +119,7 @@
+ [OP_ENDPTCTRL] = 0x0ECUL,
+ };
+
+-static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
++static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
+ {
+ int i;
+
+@@ -148,7 +151,7 @@
+ *
+ * This function returns an error code
+ */
+-int hw_port_test_set(struct ci13xxx *ci, u8 mode)
++int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
+ {
+ const u8 TEST_MODE_MAX = 7;
+
+@@ -164,12 +167,38 @@
+ *
+ * This function returns port test mode value
+ */
+-u8 hw_port_test_get(struct ci13xxx *ci)
++u8 hw_port_test_get(struct ci_hdrc *ci)
+ {
+ return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
+ }
+
+-static int hw_device_init(struct ci13xxx *ci, void __iomem *base)
++static void hw_wait_phy_stable(void)
++{
++ /* The controller needs at least 1ms to reflect PHY's status */
++ usleep_range(2000, 2500);
++}
++
++static void delay_runtime_pm_put_timer(unsigned long arg)
++{
++ struct ci_hdrc *ci = (struct ci_hdrc *)arg;
++
++ pm_runtime_put(ci->dev);
++}
++
++/* The PHY enters/leaves low power mode */
++static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
++{
++ enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
++ bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
++
++ if (enable && !lpm)
++ hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
++ PORTSC_PHCD(ci->hw_bank.lpm));
++ else if (!enable && lpm)
++ hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm), 0);
++}
++
++static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
+ {
+ u32 reg;
+
+@@ -196,6 +225,14 @@
+ if (ci->hw_ep_max > ENDPT_MAX)
+ return -ENODEV;
+
++ ci_hdrc_enter_lpm(ci, false);
++
++ /* Disable all interrupts bits */
++ hw_write(ci, OP_USBINTR, 0xffffffff, 0);
++
++ /* Clear all interrupts status bits*/
++ hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
++
+ dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
+ ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
+
+@@ -208,13 +245,52 @@
+ return 0;
+ }
+
++static void hw_phymode_configure(struct ci_hdrc *ci)
++{
++ u32 portsc, lpm, sts;
++
++ switch (ci->platdata->phy_mode) {
++ case USBPHY_INTERFACE_MODE_UTMI:
++ portsc = PORTSC_PTS(PTS_UTMI);
++ lpm = DEVLC_PTS(PTS_UTMI);
++ break;
++ case USBPHY_INTERFACE_MODE_UTMIW:
++ portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
++ lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
++ break;
++ case USBPHY_INTERFACE_MODE_ULPI:
++ portsc = PORTSC_PTS(PTS_ULPI);
++ lpm = DEVLC_PTS(PTS_ULPI);
++ break;
++ case USBPHY_INTERFACE_MODE_SERIAL:
++ portsc = PORTSC_PTS(PTS_SERIAL);
++ lpm = DEVLC_PTS(PTS_SERIAL);
++ sts = 1;
++ break;
++ case USBPHY_INTERFACE_MODE_HSIC:
++ portsc = PORTSC_PTS(PTS_HSIC);
++ lpm = DEVLC_PTS(PTS_HSIC);
++ break;
++ default:
++ return;
++ }
++
++ if (ci->hw_bank.lpm) {
++ hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
++ hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
++ } else {
++ hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
++ hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
++ }
++}
++
+ /**
+ * hw_device_reset: resets chip (execute without interruption)
+ * @ci: the controller
+ *
+ * This function returns an error code
+ */
+-int hw_device_reset(struct ci13xxx *ci, u32 mode)
++int hw_device_reset(struct ci_hdrc *ci, u32 mode)
+ {
+ /* should flush & stop before reset */
+ hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
+@@ -224,12 +300,11 @@
+ while (hw_read(ci, OP_USBCMD, USBCMD_RST))
+ udelay(10); /* not RTOS friendly */
+
+-
+ if (ci->platdata->notify_event)
+ ci->platdata->notify_event(ci,
+- CI13XXX_CONTROLLER_RESET_EVENT);
++ CI_HDRC_CONTROLLER_RESET_EVENT);
+
+- if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING)
++ if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
+ hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
+
+ /* USBMODE should be configured step by step */
+@@ -248,70 +323,127 @@
+ }
+
+ /**
+- * ci_otg_role - pick role based on ID pin state
++ * hw_wait_reg: wait the register value
++ *
++ * Sometimes, it needs to wait register value before going on.
++ * Eg, when switch to device mode, the vbus value should be lower
++ * than OTGSC_BSV before connects to host.
++ *
+ * @ci: the controller
++ * @reg: register index
++ * @mask: mast bit
++ * @value: the bit value to wait
++ * @timeout_ms: timeout in millisecond
++ *
++ * This function returns an error code if timeout
+ */
+-static enum ci_role ci_otg_role(struct ci13xxx *ci)
+-{
+- u32 sts = hw_read(ci, OP_OTGSC, ~0);
+- enum ci_role role = sts & OTGSC_ID
+- ? CI_ROLE_GADGET
+- : CI_ROLE_HOST;
+-
+- return role;
+-}
+-
+-/**
+- * ci_role_work - perform role changing based on ID pin
+- * @work: work struct
+- */
+-static void ci_role_work(struct work_struct *work)
++int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
++ u32 value, unsigned int timeout_ms)
+ {
+- struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
+- enum ci_role role = ci_otg_role(ci);
++ unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
+
+- if (role != ci->role) {
+- dev_dbg(ci->dev, "switching from %s to %s\n",
+- ci_role(ci)->name, ci->roles[role]->name);
+-
+- ci_role_stop(ci);
+- ci_role_start(ci, role);
++ while (hw_read(ci, reg, mask) != value) {
++ if (time_after(jiffies, elapse)) {
++ dev_err(ci->dev, "timeout waiting for %08x in %d\n",
++ mask, reg);
++ return -ETIMEDOUT;
++ }
++ msleep(20);
+ }
+
+- enable_irq(ci->irq);
++ return 0;
+ }
+
+ static irqreturn_t ci_irq(int irq, void *data)
+ {
+- struct ci13xxx *ci = data;
++ struct ci_hdrc *ci = data;
+ irqreturn_t ret = IRQ_NONE;
+ u32 otgsc = 0;
+
++ if (ci->in_lpm) {
++ disable_irq_nosync(irq);
++ ci->wakeup_int = true;
++ pm_runtime_get(ci->dev);
++ return IRQ_HANDLED;
++ }
++
+ if (ci->is_otg)
+ otgsc = hw_read(ci, OP_OTGSC, ~0);
+
+- if (ci->role != CI_ROLE_END)
+- ret = ci_role(ci)->irq(ci);
++ /*
++ * Handle id change interrupt, it indicates device/host function
++ * switch.
++ */
++ if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
++ ci->id_event = true;
++ ci_clear_otg_interrupt(ci, OTGSC_IDIS);
++ disable_irq_nosync(ci->irq);
++ wake_up(&ci->otg_wait);
++ return IRQ_HANDLED;
++ }
+
+- if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
+- hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
++ /*
++ * Handle vbus change interrupt, it indicates device connection
++ * and disconnection events.
++ */
++ if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
++ ci->b_sess_valid_event = true;
++ ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
+ disable_irq_nosync(ci->irq);
+- queue_work(ci->wq, &ci->work);
+- ret = IRQ_HANDLED;
++ wake_up(&ci->otg_wait);
++ return IRQ_HANDLED;
+ }
+
++ /* Handle device/host interrupt */
++ if (ci->role != CI_ROLE_END)
++ ret = ci_role(ci)->irq(ci);
++
+ return ret;
+ }
+
++static int ci_get_platdata(struct device *dev,
++ struct ci_hdrc_platform_data *platdata)
++{
++ if (!platdata->phy_mode)
++ platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
++
++ if (!platdata->dr_mode)
++ platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
++
++ if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
++ platdata->dr_mode = USB_DR_MODE_OTG;
++
++ if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
++ /* Get the vbus regulator */
++ platdata->reg_vbus = devm_regulator_get(dev, "vbus");
++ if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
++ return -EPROBE_DEFER;
++ } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
++ /* no vbus regualator is needed */
++ platdata->reg_vbus = NULL;
++ } else if (IS_ERR(platdata->reg_vbus)) {
++ dev_err(dev, "Getting regulator error: %ld\n",
++ PTR_ERR(platdata->reg_vbus));
++ return PTR_ERR(platdata->reg_vbus);
++ }
++ }
++
++ return 0;
++}
++
+ static DEFINE_IDA(ci_ida);
+
+-struct platform_device *ci13xxx_add_device(struct device *dev,
++struct platform_device *ci_hdrc_add_device(struct device *dev,
+ struct resource *res, int nres,
+- struct ci13xxx_platform_data *platdata)
++ struct ci_hdrc_platform_data *platdata)
+ {
+ struct platform_device *pdev;
+ int id, ret;
+
++ ret = ci_get_platdata(dev, platdata);
++ if (ret)
++ return ERR_PTR(ret);
++
+ id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
+ if (id < 0)
+ return ERR_PTR(id);
+@@ -347,23 +479,79 @@
+ ida_simple_remove(&ci_ida, id);
+ return ERR_PTR(ret);
+ }
+-EXPORT_SYMBOL_GPL(ci13xxx_add_device);
++EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
+
+-void ci13xxx_remove_device(struct platform_device *pdev)
++void ci_hdrc_remove_device(struct platform_device *pdev)
+ {
+ int id = pdev->id;
+ platform_device_unregister(pdev);
+ ida_simple_remove(&ci_ida, id);
+ }
+-EXPORT_SYMBOL_GPL(ci13xxx_remove_device);
++EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
++
++static inline void ci_role_destroy(struct ci_hdrc *ci)
++{
++ ci_hdrc_gadget_destroy(ci);
++ ci_hdrc_host_destroy(ci);
++ if (ci->is_otg)
++ ci_hdrc_otg_destroy(ci);
++}
++
++static void ci_get_otg_capable(struct ci_hdrc *ci)
++{
++ if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
++ ci->is_otg = false;
++ else
++ ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
++ DCCPARAMS_DC | DCCPARAMS_HC)
++ == (DCCPARAMS_DC | DCCPARAMS_HC));
++ if (ci->is_otg) {
++ dev_dbg(ci->dev, "It is OTG capable controller\n");
++ ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
++ ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
++ }
++}
++
++static int ci_usb_phy_init(struct ci_hdrc *ci)
++{
++ int ret;
++
++ if (ci->platdata->phy) {
++ ci->transceiver = ci->platdata->phy;
++ ret = usb_phy_init(ci->transceiver);
++ if (!ret)
++ hw_wait_phy_stable();
++ return ret;
++ } else {
++ ci->global_phy = true;
++ ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
++ if (IS_ERR(ci->transceiver))
++ ci->transceiver = NULL;
++
++ return 0;
++ }
++}
++
++static void ci_usb_phy_destroy(struct ci_hdrc *ci)
++{
++ if (!ci->transceiver)
++ return;
++
++ otg_set_peripheral(ci->transceiver->otg, NULL);
++ if (ci->global_phy)
++ usb_put_phy(ci->transceiver);
++ else
++ usb_phy_shutdown(ci->transceiver);
++}
+
+ static int ci_hdrc_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+- struct ci13xxx *ci;
++ struct ci_hdrc *ci;
+ struct resource *res;
+ void __iomem *base;
+ int ret;
++ enum usb_dr_mode dr_mode;
+
+ if (!dev->platform_data) {
+ dev_err(dev, "platform data missing\n");
+@@ -383,10 +571,8 @@
+
+ ci->dev = dev;
+ ci->platdata = dev->platform_data;
+- if (ci->platdata->phy)
+- ci->transceiver = ci->platdata->phy;
+- else
+- ci->global_phy = true;
++ ci->imx28_write_fix = !!(ci->platdata->flags &
++ CI_HDRC_IMX28_WRITE_FIX);
+
+ ret = hw_device_init(ci, base);
+ if (ret < 0) {
+@@ -394,52 +580,94 @@
+ return -ENODEV;
+ }
+
++ ret = ci_usb_phy_init(ci);
++ if (ret) {
++ dev_err(dev, "unable to init phy: %d\n", ret);
++ return ret;
++ }
++
+ ci->hw_bank.phys = res->start;
+
+ ci->irq = platform_get_irq(pdev, 0);
+ if (ci->irq < 0) {
+ dev_err(dev, "missing IRQ\n");
+- return -ENODEV;
++ ret = -ENODEV;
++ goto destroy_phy;
+ }
+
+- INIT_WORK(&ci->work, ci_role_work);
+- ci->wq = create_singlethread_workqueue("ci_otg");
+- if (!ci->wq) {
+- dev_err(dev, "can't create workqueue\n");
+- return -ENODEV;
+- }
++ ci_get_otg_capable(ci);
+
+- /* initialize role(s) before the interrupt is requested */
+- ret = ci_hdrc_host_init(ci);
+- if (ret)
+- dev_info(dev, "doesn't support host\n");
++ hw_phymode_configure(ci);
+
+- ret = ci_hdrc_gadget_init(ci);
+- if (ret)
+- dev_info(dev, "doesn't support gadget\n");
++ dr_mode = ci->platdata->dr_mode;
++
++ ci->supports_runtime_pm = !!(ci->platdata->flags &
++ CI_HDRC_SUPPORTS_RUNTIME_PM);
++
++ /* initialize role(s) before the interrupt is requested */
++ if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
++ ret = ci_hdrc_host_init(ci);
++ if (ret)
++ dev_info(dev, "doesn't support host\n");
++ }
++
++ if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
++ ret = ci_hdrc_gadget_init(ci);
++ if (ret)
++ dev_info(dev, "doesn't support gadget\n");
++ if (!ret && ci->transceiver) {
++ ret = otg_set_peripheral(ci->transceiver->otg,
++ &ci->gadget);
++ /*
++ * If we implement all USB functions using chipidea drivers,
++ * it doesn't need to call above API, meanwhile, if we only
++ * use gadget function, calling above API is useless.
++ */
++ if (ret && ret != -ENOTSUPP)
++ goto destroy_phy;
++ }
++ }
+
+ if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
+ dev_err(dev, "no supported roles\n");
+ ret = -ENODEV;
+- goto rm_wq;
++ goto destroy_phy;
++ }
++
++ if (ci->is_otg) {
++ ret = ci_hdrc_otg_init(ci);
++ if (ret) {
++ dev_err(dev, "init otg fails, ret = %d\n", ret);
++ goto stop;
++ }
+ }
+
+ if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
+- ci->is_otg = true;
+- /* ID pin needs 1ms debouce time, we delay 2ms for safe */
+- mdelay(2);
+- ci->role = ci_otg_role(ci);
++ if (ci->is_otg) {
++ ci->role = ci_otg_role(ci);
++ ci_enable_otg_interrupt(ci, OTGSC_IDIE);
++ } else {
++ /*
++ * If the controller is not OTG capable, but support
++ * role switch, the defalt role is gadget, and the
++ * user can switch it through debugfs.
++ */
++ ci->role = CI_ROLE_GADGET;
++ }
+ } else {
+ ci->role = ci->roles[CI_ROLE_HOST]
+ ? CI_ROLE_HOST
+ : CI_ROLE_GADGET;
+ }
+
++ /* Notify vbus connected event if it is existed */
++ if (ci->role == CI_ROLE_GADGET)
++ ci_handle_vbus_connected(ci);
++
+ ret = ci_role_start(ci, ci->role);
+ if (ret) {
+ dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
+- ret = -ENODEV;
+- goto rm_wq;
++ goto stop;
+ }
+
+ platform_set_drvdata(pdev, ci);
+@@ -448,48 +676,167 @@
+ if (ret)
+ goto stop;
+
+- if (ci->is_otg)
+- hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
++ device_set_wakeup_capable(&pdev->dev, true);
++
++ if (ci->supports_runtime_pm) {
++ pm_runtime_set_active(&pdev->dev);
++ pm_runtime_enable(&pdev->dev);
++ }
+
++ setup_timer(&ci->timer, delay_runtime_pm_put_timer,
++ (unsigned long)ci);
+ ret = dbg_create_files(ci);
+ if (!ret)
+ return 0;
+
+ free_irq(ci->irq, ci);
+ stop:
+- ci_role_stop(ci);
+-rm_wq:
+- flush_workqueue(ci->wq);
+- destroy_workqueue(ci->wq);
++ ci_role_destroy(ci);
++destroy_phy:
++ ci_usb_phy_destroy(ci);
+
+ return ret;
+ }
+
+ static int ci_hdrc_remove(struct platform_device *pdev)
+ {
+- struct ci13xxx *ci = platform_get_drvdata(pdev);
++ struct ci_hdrc *ci = platform_get_drvdata(pdev);
+
++ if (ci->supports_runtime_pm) {
++ pm_runtime_get_sync(&pdev->dev);
++ pm_runtime_disable(&pdev->dev);
++ pm_runtime_put_noidle(&pdev->dev);
++ }
+ dbg_remove_files(ci);
+- flush_workqueue(ci->wq);
+- destroy_workqueue(ci->wq);
+ free_irq(ci->irq, ci);
+- ci_role_stop(ci);
++ ci_role_destroy(ci);
++ ci_hdrc_enter_lpm(ci, true);
++ ci_usb_phy_destroy(ci);
++ kfree(ci->hw_bank.regmap);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int ci_controller_suspend(struct device *dev)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ dev_dbg(dev, "at %s\n", __func__);
++
++ if (ci->in_lpm)
++ return 0;
++
++ disable_irq(ci->irq);
++
++ if (ci->transceiver)
++ usb_phy_set_wakeup(ci->transceiver, true);
++
++ ci_hdrc_enter_lpm(ci, true);
++
++ if (ci->transceiver)
++ usb_phy_set_suspend(ci->transceiver, 1);
++
++ ci->in_lpm = true;
++
++ enable_irq(ci->irq);
++
++ return 0;
++}
++
++static int ci_controller_resume(struct device *dev)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ dev_dbg(dev, "at %s\n", __func__);
++
++ if (!ci->in_lpm)
++ return 0;
++
++ ci_hdrc_enter_lpm(ci, false);
++
++ if (ci->transceiver) {
++ usb_phy_set_suspend(ci->transceiver, 0);
++ usb_phy_set_wakeup(ci->transceiver, false);
++ hw_wait_phy_stable();
++ }
++
++ ci->in_lpm = false;
++
++ if (ci->wakeup_int) {
++ ci->wakeup_int = false;
++ enable_irq(ci->irq);
++ mod_timer(&ci->timer, jiffies + msecs_to_jiffies(2000));
++ }
+
+ return 0;
+ }
+
++#ifdef CONFIG_PM_SLEEP
++static int ci_suspend(struct device *dev)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++ int ret;
++
++ ret = ci_controller_suspend(dev);
++ if (ret)
++ return ret;
++
++ if (device_may_wakeup(dev))
++ enable_irq_wake(ci->irq);
++
++ return ret;
++}
++
++static int ci_resume(struct device *dev)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++ int ret;
++
++ if (device_may_wakeup(dev))
++ disable_irq_wake(ci->irq);
++
++ ret = ci_controller_resume(dev);
++ if (!ret && ci->supports_runtime_pm) {
++ pm_runtime_disable(dev);
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ }
++
++ return ret;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++#ifdef CONFIG_PM_RUNTIME
++static int ci_runtime_suspend(struct device *dev)
++{
++ return ci_controller_suspend(dev);
++}
++
++static int ci_runtime_resume(struct device *dev)
++{
++ return ci_controller_resume(dev);
++}
++#endif /* CONFIG_PM_RUNTIME */
++
++#endif /* CONFIG_PM */
++static const struct dev_pm_ops ci_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
++ SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
++};
++
+ static struct platform_driver ci_hdrc_driver = {
+ .probe = ci_hdrc_probe,
+ .remove = ci_hdrc_remove,
+ .driver = {
+ .name = "ci_hdrc",
++ .pm = &ci_pm_ops,
+ },
+ };
+
+ module_platform_driver(ci_hdrc_driver);
+
+ MODULE_ALIAS("platform:ci_hdrc");
+-MODULE_ALIAS("platform:ci13xxx");
+ MODULE_LICENSE("GPL v2");
+ MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
+ MODULE_DESCRIPTION("ChipIdea HDRC Driver");
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/debug.c linux-linaro-stable-mx6/drivers/usb/chipidea/debug.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/debug.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/debug.c 2014-05-15 20:34:08.202087385 +0200
+@@ -18,7 +18,7 @@
+ */
+ static int ci_device_show(struct seq_file *s, void *data)
+ {
+- struct ci13xxx *ci = s->private;
++ struct ci_hdrc *ci = s->private;
+ struct usb_gadget *gadget = &ci->gadget;
+
+ seq_printf(s, "speed = %d\n", gadget->speed);
+@@ -58,7 +58,7 @@
+ */
+ static int ci_port_test_show(struct seq_file *s, void *data)
+ {
+- struct ci13xxx *ci = s->private;
++ struct ci_hdrc *ci = s->private;
+ unsigned long flags;
+ unsigned mode;
+
+@@ -78,7 +78,7 @@
+ size_t count, loff_t *ppos)
+ {
+ struct seq_file *s = file->private_data;
+- struct ci13xxx *ci = s->private;
++ struct ci_hdrc *ci = s->private;
+ unsigned long flags;
+ unsigned mode;
+ char buf[32];
+@@ -115,7 +115,7 @@
+ */
+ static int ci_qheads_show(struct seq_file *s, void *data)
+ {
+- struct ci13xxx *ci = s->private;
++ struct ci_hdrc *ci = s->private;
+ unsigned long flags;
+ unsigned i, j;
+
+@@ -126,15 +126,15 @@
+
+ spin_lock_irqsave(&ci->lock, flags);
+ for (i = 0; i < ci->hw_ep_max/2; i++) {
+- struct ci13xxx_ep *mEpRx = &ci->ci13xxx_ep[i];
+- struct ci13xxx_ep *mEpTx =
+- &ci->ci13xxx_ep[i + ci->hw_ep_max/2];
++ struct ci_hw_ep *hweprx = &ci->ci_hw_ep[i];
++ struct ci_hw_ep *hweptx =
++ &ci->ci_hw_ep[i + ci->hw_ep_max/2];
+ seq_printf(s, "EP=%02i: RX=%08X TX=%08X\n",
+- i, (u32)mEpRx->qh.dma, (u32)mEpTx->qh.dma);
+- for (j = 0; j < (sizeof(struct ci13xxx_qh)/sizeof(u32)); j++)
++ i, (u32)hweprx->qh.dma, (u32)hweptx->qh.dma);
++ for (j = 0; j < (sizeof(struct ci_hw_qh)/sizeof(u32)); j++)
+ seq_printf(s, " %04X: %08X %08X\n", j,
+- *((u32 *)mEpRx->qh.ptr + j),
+- *((u32 *)mEpTx->qh.ptr + j));
++ *((u32 *)hweprx->qh.ptr + j),
++ *((u32 *)hweptx->qh.ptr + j));
+ }
+ spin_unlock_irqrestore(&ci->lock, flags);
+
+@@ -158,11 +158,12 @@
+ */
+ static int ci_requests_show(struct seq_file *s, void *data)
+ {
+- struct ci13xxx *ci = s->private;
++ struct ci_hdrc *ci = s->private;
+ unsigned long flags;
+ struct list_head *ptr = NULL;
+- struct ci13xxx_req *req = NULL;
+- unsigned i, j, qsize = sizeof(struct ci13xxx_td)/sizeof(u32);
++ struct ci_hw_req *req = NULL;
++ struct td_node *node, *tmpnode;
++ unsigned i, j, qsize = sizeof(struct ci_hw_td)/sizeof(u32);
+
+ if (ci->role != CI_ROLE_GADGET) {
+ seq_printf(s, "not in gadget mode\n");
+@@ -171,16 +172,20 @@
+
+ spin_lock_irqsave(&ci->lock, flags);
+ for (i = 0; i < ci->hw_ep_max; i++)
+- list_for_each(ptr, &ci->ci13xxx_ep[i].qh.queue) {
+- req = list_entry(ptr, struct ci13xxx_req, queue);
++ list_for_each(ptr, &ci->ci_hw_ep[i].qh.queue) {
++ req = list_entry(ptr, struct ci_hw_req, queue);
+
+- seq_printf(s, "EP=%02i: TD=%08X %s\n",
+- i % (ci->hw_ep_max / 2), (u32)req->dma,
+- ((i < ci->hw_ep_max/2) ? "RX" : "TX"));
+-
+- for (j = 0; j < qsize; j++)
+- seq_printf(s, " %04X: %08X\n", j,
+- *((u32 *)req->ptr + j));
++ list_for_each_entry_safe(node, tmpnode, &req->tds, td) {
++ seq_printf(s, "EP=%02i: TD=%08X %s\n",
++ i % (ci->hw_ep_max / 2),
++ (u32)node->dma,
++ ((i < ci->hw_ep_max/2) ?
++ "RX" : "TX"));
++
++ for (j = 0; j < qsize; j++)
++ seq_printf(s, " %04X: %08X\n", j,
++ *((u32 *)node->ptr + j));
++ }
+ }
+ spin_unlock_irqrestore(&ci->lock, flags);
+
+@@ -201,7 +206,7 @@
+
+ static int ci_role_show(struct seq_file *s, void *data)
+ {
+- struct ci13xxx *ci = s->private;
++ struct ci_hdrc *ci = s->private;
+
+ seq_printf(s, "%s\n", ci_role(ci)->name);
+
+@@ -212,7 +217,7 @@
+ size_t count, loff_t *ppos)
+ {
+ struct seq_file *s = file->private_data;
+- struct ci13xxx *ci = s->private;
++ struct ci_hdrc *ci = s->private;
+ enum ci_role role;
+ char buf[8];
+ int ret;
+@@ -254,7 +259,7 @@
+ *
+ * This function returns an error code
+ */
+-int dbg_create_files(struct ci13xxx *ci)
++int dbg_create_files(struct ci_hdrc *ci)
+ {
+ struct dentry *dent;
+
+@@ -295,7 +300,7 @@
+ * dbg_remove_files: destroys the attribute interface
+ * @ci: device
+ */
+-void dbg_remove_files(struct ci13xxx *ci)
++void dbg_remove_files(struct ci_hdrc *ci)
+ {
+ debugfs_remove_recursive(ci->debugfs);
+ }
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/debug.h linux-linaro-stable-mx6/drivers/usb/chipidea/debug.h
+--- linux-3.10.30.orig/drivers/usb/chipidea/debug.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/debug.h 2014-05-15 20:34:08.202087385 +0200
+@@ -14,15 +14,15 @@
+ #define __DRIVERS_USB_CHIPIDEA_DEBUG_H
+
+ #ifdef CONFIG_USB_CHIPIDEA_DEBUG
+-int dbg_create_files(struct ci13xxx *ci);
+-void dbg_remove_files(struct ci13xxx *ci);
++int dbg_create_files(struct ci_hdrc *ci);
++void dbg_remove_files(struct ci_hdrc *ci);
+ #else
+-static inline int dbg_create_files(struct ci13xxx *ci)
++static inline int dbg_create_files(struct ci_hdrc *ci)
+ {
+ return 0;
+ }
+
+-static inline void dbg_remove_files(struct ci13xxx *ci)
++static inline void dbg_remove_files(struct ci_hdrc *ci)
+ {
+ }
+ #endif
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/host.c linux-linaro-stable-mx6/drivers/usb/chipidea/host.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/host.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/host.c 2014-05-15 20:34:08.202087385 +0200
+@@ -24,6 +24,7 @@
+ #include <linux/usb.h>
+ #include <linux/usb/hcd.h>
+ #include <linux/usb/chipidea.h>
++#include <linux/regulator/consumer.h>
+
+ #include "../host/ehci.h"
+
+@@ -32,13 +33,183 @@
+ #include "host.h"
+
+ static struct hc_driver __read_mostly ci_ehci_hc_driver;
++static int (*orig_bus_suspend)(struct usb_hcd *hcd);
++static int (*orig_bus_resume)(struct usb_hcd *hcd);
++static int (*orig_hub_control)(struct usb_hcd *hcd,
++ u16 typeReq, u16 wValue, u16 wIndex,
++ char *buf, u16 wLength);
+
+-static irqreturn_t host_irq(struct ci13xxx *ci)
++static int ci_ehci_bus_suspend(struct usb_hcd *hcd)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++ int port;
++ u32 tmp;
++
++ int ret = orig_bus_suspend(hcd);
++
++ if (ret)
++ return ret;
++
++ port = HCS_N_PORTS(ehci->hcs_params);
++ while (port--) {
++ u32 __iomem *reg = &ehci->regs->port_status[port];
++ u32 portsc = ehci_readl(ehci, reg);
++
++ if (portsc & PORT_CONNECT) {
++ /*
++ * For chipidea, the resume signal will be ended
++ * automatically, so for remote wakeup case, the
++ * usbcmd.rs may not be set before the resume has
++ * ended if other resume path consumes too much
++ * time (~23ms-24ms), in that case, the SOF will not
++ * send out within 3ms after resume ends, then the
++ * device will enter suspend again.
++ */
++ if (hcd->self.root_hub->do_remote_wakeup) {
++ ehci_dbg(ehci,
++ "Remote wakeup is enabled, "
++ "and device is on the port\n");
++
++ tmp = ehci_readl(ehci, &ehci->regs->command);
++ tmp |= CMD_RUN;
++ ehci_writel(ehci, tmp, &ehci->regs->command);
++ /*
++ * It needs a short delay between set RUNSTOP
++ * and set PHCD.
++ */
++ udelay(125);
++ }
++ if (hcd->phy && test_bit(port, &ehci->bus_suspended)
++ && (ehci_port_speed(ehci, portsc) ==
++ USB_PORT_STAT_HIGH_SPEED))
++ /*
++ * notify the USB PHY, it is for global
++ * suspend case.
++ */
++ usb_phy_notify_suspend(hcd->phy,
++ USB_SPEED_HIGH);
++ }
++ }
++
++ return 0;
++}
++
++static int ci_imx_ehci_bus_resume(struct usb_hcd *hcd)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++ int port;
++
++ int ret = orig_bus_resume(hcd);
++
++ if (ret)
++ return ret;
++
++ port = HCS_N_PORTS(ehci->hcs_params);
++ while (port--) {
++ u32 __iomem *reg = &ehci->regs->port_status[port];
++ u32 portsc = ehci_readl(ehci, reg);
++ /*
++ * Notify PHY after resume signal has finished, it is
++ * for global suspend case.
++ */
++ if (hcd->phy
++ && test_bit(port, &ehci->bus_suspended)
++ && (portsc & PORT_CONNECT)
++ && (ehci_port_speed(ehci, portsc) ==
++ USB_PORT_STAT_HIGH_SPEED))
++ /* notify the USB PHY */
++ usb_phy_notify_resume(hcd->phy, USB_SPEED_HIGH);
++ }
++
++ return 0;
++}
++
++/* The below code is based on tegra ehci driver */
++static int ci_imx_ehci_hub_control(
++ struct usb_hcd *hcd,
++ u16 typeReq,
++ u16 wValue,
++ u16 wIndex,
++ char *buf,
++ u16 wLength
++)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++ u32 __iomem *status_reg;
++ u32 temp;
++ unsigned long flags;
++ int retval = 0;
++
++ status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
++
++ spin_lock_irqsave(&ehci->lock, flags);
++
++ if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
++ temp = ehci_readl(ehci, status_reg);
++ if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
++ retval = -EPIPE;
++ goto done;
++ }
++
++ temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
++ temp |= PORT_WKDISC_E | PORT_WKOC_E;
++ ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
++
++ /*
++ * If a transaction is in progress, there may be a delay in
++ * suspending the port. Poll until the port is suspended.
++ */
++ if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
++ PORT_SUSPEND, 5000))
++ ehci_err(ehci, "timeout waiting for SUSPEND\n");
++
++ spin_unlock_irqrestore(&ehci->lock, flags);
++ if (ehci_port_speed(ehci, temp) ==
++ USB_PORT_STAT_HIGH_SPEED && hcd->phy) {
++ /* notify the USB PHY */
++ usb_phy_notify_suspend(hcd->phy, USB_SPEED_HIGH);
++ }
++ spin_lock_irqsave(&ehci->lock, flags);
++
++ set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
++ goto done;
++ }
++
++ /*
++ * After resume has finished, it needs do some post resume
++ * operation for some SoCs.
++ */
++ else if (typeReq == ClearPortFeature &&
++ wValue == USB_PORT_FEAT_C_SUSPEND) {
++
++ /* Make sure the resume has finished, it should be finished */
++ if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 25000))
++ ehci_err(ehci, "timeout waiting for resume\n");
++
++ temp = ehci_readl(ehci, status_reg);
++
++ if (ehci_port_speed(ehci, temp) ==
++ USB_PORT_STAT_HIGH_SPEED && hcd->phy) {
++ /* notify the USB PHY */
++ usb_phy_notify_resume(hcd->phy, USB_SPEED_HIGH);
++ }
++ }
++
++ spin_unlock_irqrestore(&ehci->lock, flags);
++
++ /* Handle the hub control events here */
++ return orig_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
++done:
++ spin_unlock_irqrestore(&ehci->lock, flags);
++ return retval;
++}
++
++static irqreturn_t host_irq(struct ci_hdrc *ci)
+ {
+ return usb_hcd_irq(ci->irq, ci->hcd);
+ }
+
+-static int host_start(struct ci13xxx *ci)
++static int host_start(struct ci_hdrc *ci)
+ {
+ struct usb_hcd *hcd;
+ struct ehci_hcd *ehci;
+@@ -63,28 +234,58 @@
+ ehci = hcd_to_ehci(hcd);
+ ehci->caps = ci->hw_bank.cap;
+ ehci->has_hostpc = ci->hw_bank.lpm;
++ ehci->imx28_write_fix = ci->imx28_write_fix;
++
++ if (ci->platdata->reg_vbus) {
++ ret = regulator_enable(ci->platdata->reg_vbus);
++ if (ret) {
++ dev_err(ci->dev,
++ "Failed to enable vbus regulator, ret=%d\n",
++ ret);
++ goto put_hcd;
++ }
++ }
+
+ ret = usb_add_hcd(hcd, 0, 0);
+ if (ret)
+- usb_put_hcd(hcd);
++ goto disable_reg;
+ else
+ ci->hcd = hcd;
+
+- if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING)
++ if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
+ hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
+
+ return ret;
++
++disable_reg:
++ regulator_disable(ci->platdata->reg_vbus);
++
++put_hcd:
++ usb_put_hcd(hcd);
++
++ return ret;
+ }
+
+-static void host_stop(struct ci13xxx *ci)
++static void host_stop(struct ci_hdrc *ci)
+ {
+ struct usb_hcd *hcd = ci->hcd;
+
+- usb_remove_hcd(hcd);
+- usb_put_hcd(hcd);
++ if (hcd) {
++ usb_remove_hcd(hcd);
++ usb_put_hcd(hcd);
++ if (ci->platdata->reg_vbus)
++ regulator_disable(ci->platdata->reg_vbus);
++ }
++}
++
++
++void ci_hdrc_host_destroy(struct ci_hdrc *ci)
++{
++ if (ci->role == CI_ROLE_HOST && ci->hcd)
++ host_stop(ci);
+ }
+
+-int ci_hdrc_host_init(struct ci13xxx *ci)
++int ci_hdrc_host_init(struct ci_hdrc *ci)
+ {
+ struct ci_role_driver *rdrv;
+
+@@ -103,5 +304,15 @@
+
+ ehci_init_driver(&ci_ehci_hc_driver, NULL);
+
++ orig_bus_suspend = ci_ehci_hc_driver.bus_suspend;
++ orig_bus_resume = ci_ehci_hc_driver.bus_resume;
++ orig_hub_control = ci_ehci_hc_driver.hub_control;
++
++ ci_ehci_hc_driver.bus_suspend = ci_ehci_bus_suspend;
++ if (ci->platdata->flags & CI_HDRC_IMX_EHCI_QUIRK) {
++ ci_ehci_hc_driver.bus_resume = ci_imx_ehci_bus_resume;
++ ci_ehci_hc_driver.hub_control = ci_imx_ehci_hub_control;
++ }
++
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/host.h linux-linaro-stable-mx6/drivers/usb/chipidea/host.h
+--- linux-3.10.30.orig/drivers/usb/chipidea/host.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/host.h 2014-05-15 20:34:08.202087385 +0200
+@@ -3,15 +3,21 @@
+
+ #ifdef CONFIG_USB_CHIPIDEA_HOST
+
+-int ci_hdrc_host_init(struct ci13xxx *ci);
++int ci_hdrc_host_init(struct ci_hdrc *ci);
++void ci_hdrc_host_destroy(struct ci_hdrc *ci);
+
+ #else
+
+-static inline int ci_hdrc_host_init(struct ci13xxx *ci)
++static inline int ci_hdrc_host_init(struct ci_hdrc *ci)
+ {
+ return -ENXIO;
+ }
+
++static inline void ci_hdrc_host_destroy(struct ci_hdrc *ci)
++{
++
++}
++
+ #endif
+
+ #endif /* __DRIVERS_USB_CHIPIDEA_HOST_H */
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/Kconfig linux-linaro-stable-mx6/drivers/usb/chipidea/Kconfig
+--- linux-3.10.30.orig/drivers/usb/chipidea/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/Kconfig 2014-05-15 20:34:08.182087241 +0200
+@@ -1,6 +1,6 @@
+ config USB_CHIPIDEA
+ tristate "ChipIdea Highspeed Dual Role Controller"
+- depends on USB || USB_GADGET
++ depends on (USB_EHCI_HCD && USB_GADGET) || (USB_EHCI_HCD && !USB_GADGET) || (!USB_EHCI_HCD && USB_GADGET)
+ help
+ Say Y here if your system has a dual role high speed USB
+ controller based on ChipIdea silicon IP. Currently, only the
+@@ -12,15 +12,14 @@
+
+ config USB_CHIPIDEA_UDC
+ bool "ChipIdea device controller"
+- depends on USB_GADGET=y || USB_GADGET=USB_CHIPIDEA
++ depends on USB_GADGET
+ help
+ Say Y here to enable device controller functionality of the
+ ChipIdea driver.
+
+ config USB_CHIPIDEA_HOST
+ bool "ChipIdea host controller"
+- depends on USB=y || USB=USB_CHIPIDEA
+- depends on USB_EHCI_HCD=y
++ depends on USB_EHCI_HCD
+ select USB_EHCI_ROOT_HUB_TT
+ help
+ Say Y here to enable host controller functionality of the
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/Makefile linux-linaro-stable-mx6/drivers/usb/chipidea/Makefile
+--- linux-3.10.30.orig/drivers/usb/chipidea/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/Makefile 2014-05-15 20:34:08.182087241 +0200
+@@ -2,20 +2,20 @@
+
+ obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc.o
+
+-ci_hdrc-y := core.o
++ci_hdrc-y := core.o otg.o
+ ci_hdrc-$(CONFIG_USB_CHIPIDEA_UDC) += udc.o
+ ci_hdrc-$(CONFIG_USB_CHIPIDEA_HOST) += host.o
+ ci_hdrc-$(CONFIG_USB_CHIPIDEA_DEBUG) += debug.o
+
+ # Glue/Bridge layers go here
+
+-obj-$(CONFIG_USB_CHIPIDEA) += ci13xxx_msm.o
++obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_msm.o
+
+ # PCI doesn't provide stubs, need to check
+ ifneq ($(CONFIG_PCI),)
+- obj-$(CONFIG_USB_CHIPIDEA) += ci13xxx_pci.o
++ obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_pci.o
+ endif
+
+-ifneq ($(CONFIG_OF_DEVICE),)
+- obj-$(CONFIG_USB_CHIPIDEA) += ci13xxx_imx.o usbmisc_imx.o
++ifneq ($(CONFIG_OF),)
++ obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_imx.o usbmisc_imx.o
+ endif
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/otg.c linux-linaro-stable-mx6/drivers/usb/chipidea/otg.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/otg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/otg.c 2014-05-15 20:34:08.202087385 +0200
+@@ -0,0 +1,164 @@
++/*
++ * otg.c - ChipIdea USB IP core OTG driver
++ *
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * Author: Peter Chen
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/*
++ * This file mainly handles otgsc register, it may include OTG operation
++ * in the future.
++ */
++
++#include <linux/usb/otg.h>
++#include <linux/usb/gadget.h>
++#include <linux/usb/chipidea.h>
++#include <linux/kthread.h>
++#include <linux/freezer.h>
++
++#include "ci.h"
++#include "bits.h"
++#include "otg.h"
++
++/**
++ * ci_otg_role - pick role based on ID pin state
++ * @ci: the controller
++ */
++enum ci_role ci_otg_role(struct ci_hdrc *ci)
++{
++ u32 sts = hw_read(ci, OP_OTGSC, ~0);
++ enum ci_role role = sts & OTGSC_ID
++ ? CI_ROLE_GADGET
++ : CI_ROLE_HOST;
++
++ return role;
++}
++
++void ci_handle_vbus_connected(struct ci_hdrc *ci)
++{
++ u32 otgsc;
++
++ /*
++ * TODO: if the platform does not supply 5v to udc, or use other way
++ * to supply 5v, it needs to use other conditions to call
++ * usb_gadget_vbus_connect.
++ */
++ if (!ci->is_otg)
++ return;
++
++ otgsc = hw_read(ci, OP_OTGSC, ~0);
++
++ if (otgsc & OTGSC_BSV)
++ usb_gadget_vbus_connect(&ci->gadget);
++}
++
++void ci_handle_vbus_change(struct ci_hdrc *ci)
++{
++ u32 otgsc;
++
++ if (!ci->is_otg)
++ return;
++
++ otgsc = hw_read(ci, OP_OTGSC, ~0);
++
++ if (otgsc & OTGSC_BSV)
++ usb_gadget_vbus_connect(&ci->gadget);
++ else
++ usb_gadget_vbus_disconnect(&ci->gadget);
++}
++
++#define CI_VBUS_STABLE_TIMEOUT_MS 5000
++static void ci_handle_id_switch(struct ci_hdrc *ci)
++{
++ enum ci_role role = ci_otg_role(ci);
++
++ if (role != ci->role) {
++ dev_dbg(ci->dev, "switching from %s to %s\n",
++ ci_role(ci)->name, ci->roles[role]->name);
++
++ ci_role_stop(ci);
++ /* wait vbus lower than OTGSC_BSV */
++ hw_wait_reg(ci, OP_OTGSC, OTGSC_BSV, 0,
++ CI_VBUS_STABLE_TIMEOUT_MS);
++ ci_role_start(ci, role);
++ }
++}
++
++/* If there is pending otg event */
++static inline bool ci_otg_event_is_pending(struct ci_hdrc *ci)
++{
++ return ci->id_event || ci->b_sess_valid_event;
++}
++
++/**
++ * ci_otg_event - perform otg (vbus/id) event handle
++ * @ci: ci_hdrc struct
++ */
++static void ci_otg_event(struct ci_hdrc *ci)
++{
++ if (ci->id_event) {
++ ci->id_event = false;
++ /* Keep controller active during id switch */
++ pm_runtime_get_sync(ci->dev);
++ ci_handle_id_switch(ci);
++ pm_runtime_put_sync(ci->dev);
++ } else if (ci->b_sess_valid_event) {
++ ci->b_sess_valid_event = false;
++ pm_runtime_get_sync(ci->dev);
++ ci_handle_vbus_change(ci);
++ pm_runtime_put_sync(ci->dev);
++ } else
++ dev_dbg(ci->dev, "it should be quit event\n");
++
++ enable_irq(ci->irq);
++}
++
++static int ci_otg_thread(void *ptr)
++{
++ struct ci_hdrc *ci = ptr;
++
++ set_freezable();
++
++ do {
++ wait_event_freezable(ci->otg_wait,
++ ci_otg_event_is_pending(ci) ||
++ kthread_should_stop());
++ ci_otg_event(ci);
++ } while (!kthread_should_stop());
++
++ dev_warn(ci->dev, "ci_otg_thread quits\n");
++
++ return 0;
++}
++
++/**
++ * ci_hdrc_otg_init - initialize otg struct
++ * ci: the controller
++ */
++int ci_hdrc_otg_init(struct ci_hdrc *ci)
++{
++ init_waitqueue_head(&ci->otg_wait);
++ ci->otg_task = kthread_run(ci_otg_thread, ci, "ci otg thread");
++ if (IS_ERR(ci->otg_task)) {
++ dev_err(ci->dev, "error to create otg thread\n");
++ return PTR_ERR(ci->otg_task);
++ }
++
++ return 0;
++}
++
++/**
++ * ci_hdrc_otg_destroy - destroy otg struct
++ * ci: the controller
++ */
++void ci_hdrc_otg_destroy(struct ci_hdrc *ci)
++{
++ kthread_stop(ci->otg_task);
++ ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
++ ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
++}
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/otg.h linux-linaro-stable-mx6/drivers/usb/chipidea/otg.h
+--- linux-3.10.30.orig/drivers/usb/chipidea/otg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/otg.h 2014-05-15 20:34:08.202087385 +0200
+@@ -0,0 +1,36 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * Author: Peter Chen
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __DRIVERS_USB_CHIPIDEA_OTG_H
++#define __DRIVERS_USB_CHIPIDEA_OTG_H
++
++static inline void ci_clear_otg_interrupt(struct ci_hdrc *ci, u32 bits)
++{
++ /* Only clear request bits */
++ hw_write(ci, OP_OTGSC, OTGSC_INT_STATUS_BITS, bits);
++}
++
++static inline void ci_enable_otg_interrupt(struct ci_hdrc *ci, u32 bits)
++{
++ hw_write(ci, OP_OTGSC, bits, bits);
++}
++
++static inline void ci_disable_otg_interrupt(struct ci_hdrc *ci, u32 bits)
++{
++ hw_write(ci, OP_OTGSC, bits, 0);
++}
++
++int ci_hdrc_otg_init(struct ci_hdrc *ci);
++void ci_hdrc_otg_destroy(struct ci_hdrc *ci);
++enum ci_role ci_otg_role(struct ci_hdrc *ci);
++void ci_handle_vbus_change(struct ci_hdrc *ci);
++void ci_handle_vbus_connected(struct ci_hdrc *ci);
++
++#endif /* __DRIVERS_USB_CHIPIDEA_OTG_H */
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/udc.c linux-linaro-stable-mx6/drivers/usb/chipidea/udc.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/udc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/udc.c 2014-05-15 20:34:08.202087385 +0200
+@@ -20,13 +20,13 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
+-#include <linux/usb/otg.h>
+ #include <linux/usb/chipidea.h>
+
+ #include "ci.h"
+ #include "udc.h"
+ #include "bits.h"
+ #include "debug.h"
++#include "otg.h"
+
+ /* control endpoint description */
+ static const struct usb_endpoint_descriptor
+@@ -61,7 +61,7 @@
+ return num + (dir ? 16 : 0);
+ }
+
+-static inline int ep_to_bit(struct ci13xxx *ci, int n)
++static inline int ep_to_bit(struct ci_hdrc *ci, int n)
+ {
+ int fill = 16 - ci->hw_ep_max / 2;
+
+@@ -77,15 +77,17 @@
+ *
+ * This function returns an error code
+ */
+-static int hw_device_state(struct ci13xxx *ci, u32 dma)
++static int hw_device_state(struct ci_hdrc *ci, u32 dma)
+ {
+ if (dma) {
+ hw_write(ci, OP_ENDPTLISTADDR, ~0, dma);
+ /* interrupt, error, port change, reset, sleep/suspend */
+ hw_write(ci, OP_USBINTR, ~0,
+ USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
++ hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
+ } else {
+ hw_write(ci, OP_USBINTR, ~0, 0);
++ hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
+ }
+ return 0;
+ }
+@@ -97,7 +99,7 @@
+ *
+ * This function returns an error code
+ */
+-static int hw_ep_flush(struct ci13xxx *ci, int num, int dir)
++static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir)
+ {
+ int n = hw_ep_bit(num, dir);
+
+@@ -118,7 +120,7 @@
+ *
+ * This function returns an error code
+ */
+-static int hw_ep_disable(struct ci13xxx *ci, int num, int dir)
++static int hw_ep_disable(struct ci_hdrc *ci, int num, int dir)
+ {
+ hw_ep_flush(ci, num, dir);
+ hw_write(ci, OP_ENDPTCTRL + num,
+@@ -134,7 +136,7 @@
+ *
+ * This function returns an error code
+ */
+-static int hw_ep_enable(struct ci13xxx *ci, int num, int dir, int type)
++static int hw_ep_enable(struct ci_hdrc *ci, int num, int dir, int type)
+ {
+ u32 mask, data;
+
+@@ -168,7 +170,7 @@
+ *
+ * This function returns 1 if endpoint halted
+ */
+-static int hw_ep_get_halt(struct ci13xxx *ci, int num, int dir)
++static int hw_ep_get_halt(struct ci_hdrc *ci, int num, int dir)
+ {
+ u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
+
+@@ -182,7 +184,7 @@
+ *
+ * This function returns setup status
+ */
+-static int hw_test_and_clear_setup_status(struct ci13xxx *ci, int n)
++static int hw_test_and_clear_setup_status(struct ci_hdrc *ci, int n)
+ {
+ n = ep_to_bit(ci, n);
+ return hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(n));
+@@ -196,7 +198,7 @@
+ *
+ * This function returns an error code
+ */
+-static int hw_ep_prime(struct ci13xxx *ci, int num, int dir, int is_ctrl)
++static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl)
+ {
+ int n = hw_ep_bit(num, dir);
+
+@@ -223,13 +225,13 @@
+ *
+ * This function returns an error code
+ */
+-static int hw_ep_set_halt(struct ci13xxx *ci, int num, int dir, int value)
++static int hw_ep_set_halt(struct ci_hdrc *ci, int num, int dir, int value)
+ {
+ if (value != 0 && value != 1)
+ return -EINVAL;
+
+ do {
+- enum ci13xxx_regs reg = OP_ENDPTCTRL + num;
++ enum ci_hw_regs reg = OP_ENDPTCTRL + num;
+ u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
+ u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
+
+@@ -246,7 +248,7 @@
+ *
+ * This function returns true if high speed port
+ */
+-static int hw_port_is_high_speed(struct ci13xxx *ci)
++static int hw_port_is_high_speed(struct ci_hdrc *ci)
+ {
+ return ci->hw_bank.lpm ? hw_read(ci, OP_DEVLC, DEVLC_PSPD) :
+ hw_read(ci, OP_PORTSC, PORTSC_HSP);
+@@ -257,7 +259,7 @@
+ *
+ * This function returns register data
+ */
+-static u32 hw_read_intr_enable(struct ci13xxx *ci)
++static u32 hw_read_intr_enable(struct ci_hdrc *ci)
+ {
+ return hw_read(ci, OP_USBINTR, ~0);
+ }
+@@ -267,7 +269,7 @@
+ *
+ * This function returns register data
+ */
+-static u32 hw_read_intr_status(struct ci13xxx *ci)
++static u32 hw_read_intr_status(struct ci_hdrc *ci)
+ {
+ return hw_read(ci, OP_USBSTS, ~0);
+ }
+@@ -279,7 +281,7 @@
+ *
+ * This function returns complete status
+ */
+-static int hw_test_and_clear_complete(struct ci13xxx *ci, int n)
++static int hw_test_and_clear_complete(struct ci_hdrc *ci, int n)
+ {
+ n = ep_to_bit(ci, n);
+ return hw_test_and_clear(ci, OP_ENDPTCOMPLETE, BIT(n));
+@@ -291,7 +293,7 @@
+ *
+ * This function returns active interrutps
+ */
+-static u32 hw_test_and_clear_intr_active(struct ci13xxx *ci)
++static u32 hw_test_and_clear_intr_active(struct ci_hdrc *ci)
+ {
+ u32 reg = hw_read_intr_status(ci) & hw_read_intr_enable(ci);
+
+@@ -305,7 +307,7 @@
+ *
+ * This function returns guard value
+ */
+-static int hw_test_and_clear_setup_guard(struct ci13xxx *ci)
++static int hw_test_and_clear_setup_guard(struct ci_hdrc *ci)
+ {
+ return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, 0);
+ }
+@@ -316,7 +318,7 @@
+ *
+ * This function returns guard value
+ */
+-static int hw_test_and_set_setup_guard(struct ci13xxx *ci)
++static int hw_test_and_set_setup_guard(struct ci_hdrc *ci)
+ {
+ return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
+ }
+@@ -328,7 +330,7 @@
+ * This function explicitly sets the address, without the "USBADRA" (advance)
+ * feature, which is not supported by older versions of the controller.
+ */
+-static void hw_usb_set_address(struct ci13xxx *ci, u8 value)
++static void hw_usb_set_address(struct ci_hdrc *ci, u8 value)
+ {
+ hw_write(ci, OP_DEVICEADDR, DEVICEADDR_USBADR,
+ value << __ffs(DEVICEADDR_USBADR));
+@@ -340,7 +342,7 @@
+ *
+ * This function returns an error code
+ */
+-static int hw_usb_reset(struct ci13xxx *ci)
++static int hw_usb_reset(struct ci_hdrc *ci)
+ {
+ hw_usb_set_address(ci, 0);
+
+@@ -368,11 +370,60 @@
+ /******************************************************************************
+ * UTIL block
+ *****************************************************************************/
++
++static int add_td_to_list(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq,
++ unsigned length)
++{
++ int i;
++ u32 temp;
++ struct td_node *lastnode, *node = kzalloc(sizeof(struct td_node),
++ GFP_ATOMIC);
++
++ if (node == NULL)
++ return -ENOMEM;
++
++ node->ptr = dma_pool_alloc(hwep->td_pool, GFP_ATOMIC,
++ &node->dma);
++ if (node->ptr == NULL) {
++ kfree(node);
++ return -ENOMEM;
++ }
++
++ memset(node->ptr, 0, sizeof(struct ci_hw_td));
++ node->ptr->token = cpu_to_le32(length << __ffs(TD_TOTAL_BYTES));
++ node->ptr->token &= cpu_to_le32(TD_TOTAL_BYTES);
++ node->ptr->token |= cpu_to_le32(TD_STATUS_ACTIVE);
++
++ temp = (u32) (hwreq->req.dma + hwreq->req.actual);
++ if (length) {
++ node->ptr->page[0] = cpu_to_le32(temp);
++ for (i = 1; i < TD_PAGE_COUNT; i++) {
++ u32 page = temp + i * CI_HDRC_PAGE_SIZE;
++ page &= ~TD_RESERVED_MASK;
++ node->ptr->page[i] = cpu_to_le32(page);
++ }
++ }
++
++ hwreq->req.actual += length;
++
++ if (!list_empty(&hwreq->tds)) {
++ /* get the last entry */
++ lastnode = list_entry(hwreq->tds.prev,
++ struct td_node, td);
++ lastnode->ptr->next = cpu_to_le32(node->dma);
++ }
++
++ INIT_LIST_HEAD(&node->td);
++ list_add_tail(&node->td, &hwreq->tds);
++
++ return 0;
++}
++
+ /**
+ * _usb_addr: calculates endpoint address from direction & number
+ * @ep: endpoint
+ */
+-static inline u8 _usb_addr(struct ci13xxx_ep *ep)
++static inline u8 _usb_addr(struct ci_hw_ep *ep)
+ {
+ return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
+ }
+@@ -380,75 +431,73 @@
+ /**
+ * _hardware_queue: configures a request at hardware level
+ * @gadget: gadget
+- * @mEp: endpoint
++ * @hwep: endpoint
+ *
+ * This function returns an error code
+ */
+-static int _hardware_enqueue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
++static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
+ {
+- struct ci13xxx *ci = mEp->ci;
+- unsigned i;
++ struct ci_hdrc *ci = hwep->ci;
+ int ret = 0;
+- unsigned length = mReq->req.length;
++ unsigned rest = hwreq->req.length;
++ int pages = TD_PAGE_COUNT;
++ struct td_node *firstnode, *lastnode;
+
+ /* don't queue twice */
+- if (mReq->req.status == -EALREADY)
++ if (hwreq->req.status == -EALREADY)
+ return -EALREADY;
+
+- mReq->req.status = -EALREADY;
++ hwreq->req.status = -EALREADY;
+
+- if (mReq->req.zero && length && (length % mEp->ep.maxpacket == 0)) {
+- mReq->zptr = dma_pool_alloc(mEp->td_pool, GFP_ATOMIC,
+- &mReq->zdma);
+- if (mReq->zptr == NULL)
+- return -ENOMEM;
+-
+- memset(mReq->zptr, 0, sizeof(*mReq->zptr));
+- mReq->zptr->next = cpu_to_le32(TD_TERMINATE);
+- mReq->zptr->token = cpu_to_le32(TD_STATUS_ACTIVE);
+- if (!mReq->req.no_interrupt)
+- mReq->zptr->token |= cpu_to_le32(TD_IOC);
+- }
+- ret = usb_gadget_map_request(&ci->gadget, &mReq->req, mEp->dir);
++ ret = usb_gadget_map_request(&ci->gadget, &hwreq->req, hwep->dir);
+ if (ret)
+ return ret;
+
+ /*
+- * TD configuration
+- * TODO - handle requests which spawns into several TDs
++ * The first buffer could be not page aligned.
++ * In that case we have to span into one extra td.
+ */
+- memset(mReq->ptr, 0, sizeof(*mReq->ptr));
+- mReq->ptr->token = cpu_to_le32(length << __ffs(TD_TOTAL_BYTES));
+- mReq->ptr->token &= cpu_to_le32(TD_TOTAL_BYTES);
+- mReq->ptr->token |= cpu_to_le32(TD_STATUS_ACTIVE);
+- if (mReq->zptr) {
+- mReq->ptr->next = cpu_to_le32(mReq->zdma);
+- } else {
+- mReq->ptr->next = cpu_to_le32(TD_TERMINATE);
+- if (!mReq->req.no_interrupt)
+- mReq->ptr->token |= cpu_to_le32(TD_IOC);
+- }
+- mReq->ptr->page[0] = cpu_to_le32(mReq->req.dma);
+- for (i = 1; i < TD_PAGE_COUNT; i++) {
+- u32 page = mReq->req.dma + i * CI13XXX_PAGE_SIZE;
+- page &= ~TD_RESERVED_MASK;
+- mReq->ptr->page[i] = cpu_to_le32(page);
++ if (hwreq->req.dma % PAGE_SIZE)
++ pages--;
++
++ if (rest == 0)
++ add_td_to_list(hwep, hwreq, 0);
++
++ while (rest > 0) {
++ unsigned count = min(hwreq->req.length - hwreq->req.actual,
++ (unsigned)(pages * CI_HDRC_PAGE_SIZE));
++ add_td_to_list(hwep, hwreq, count);
++ rest -= count;
+ }
+
++ if (hwreq->req.zero && hwreq->req.length
++ && (hwreq->req.length % hwep->ep.maxpacket == 0))
++ add_td_to_list(hwep, hwreq, 0);
++
++ firstnode = list_first_entry(&hwreq->tds, struct td_node, td);
++
++ lastnode = list_entry(hwreq->tds.prev,
++ struct td_node, td);
++
++ lastnode->ptr->next = cpu_to_le32(TD_TERMINATE);
++ if (!hwreq->req.no_interrupt)
++ lastnode->ptr->token |= cpu_to_le32(TD_IOC);
+ wmb();
+
+- if (!list_empty(&mEp->qh.queue)) {
+- struct ci13xxx_req *mReqPrev;
+- int n = hw_ep_bit(mEp->num, mEp->dir);
++ hwreq->req.actual = 0;
++ if (!list_empty(&hwep->qh.queue)) {
++ struct ci_hw_req *hwreqprev;
++ int n = hw_ep_bit(hwep->num, hwep->dir);
+ int tmp_stat;
+- u32 next = mReq->dma & TD_ADDR_MASK;
++ struct td_node *prevlastnode;
++ u32 next = firstnode->dma & TD_ADDR_MASK;
++
++ hwreqprev = list_entry(hwep->qh.queue.prev,
++ struct ci_hw_req, queue);
++ prevlastnode = list_entry(hwreqprev->tds.prev,
++ struct td_node, td);
+
+- mReqPrev = list_entry(mEp->qh.queue.prev,
+- struct ci13xxx_req, queue);
+- if (mReqPrev->zptr)
+- mReqPrev->zptr->next = cpu_to_le32(next);
+- else
+- mReqPrev->ptr->next = cpu_to_le32(next);
++ prevlastnode->ptr->next = cpu_to_le32(next);
+ wmb();
+ if (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
+ goto done;
+@@ -462,99 +511,152 @@
+ }
+
+ /* QH configuration */
+- mEp->qh.ptr->td.next = cpu_to_le32(mReq->dma); /* TERMINATE = 0 */
+- mEp->qh.ptr->td.token &=
++ hwep->qh.ptr->td.next = cpu_to_le32(firstnode->dma);
++ hwep->qh.ptr->td.token &=
+ cpu_to_le32(~(TD_STATUS_HALTED|TD_STATUS_ACTIVE));
+
++ if (hwep->type == USB_ENDPOINT_XFER_ISOC) {
++ u32 mul = hwreq->req.length / hwep->ep.maxpacket;
++
++ if (hwreq->req.length % hwep->ep.maxpacket)
++ mul++;
++ hwep->qh.ptr->cap |= mul << __ffs(QH_MULT);
++ }
++
+ wmb(); /* synchronize before ep prime */
+
+- ret = hw_ep_prime(ci, mEp->num, mEp->dir,
+- mEp->type == USB_ENDPOINT_XFER_CONTROL);
++ ret = hw_ep_prime(ci, hwep->num, hwep->dir,
++ hwep->type == USB_ENDPOINT_XFER_CONTROL);
+ done:
+ return ret;
+ }
+
++/*
++ * free_pending_td: remove a pending request for the endpoint
++ * @hwep: endpoint
++ */
++static void free_pending_td(struct ci_hw_ep *hwep)
++{
++ struct td_node *pending = hwep->pending_td;
++
++ dma_pool_free(hwep->td_pool, pending->ptr, pending->dma);
++ hwep->pending_td = NULL;
++ kfree(pending);
++}
++
+ /**
+ * _hardware_dequeue: handles a request at hardware level
+ * @gadget: gadget
+- * @mEp: endpoint
++ * @hwep: endpoint
+ *
+ * This function returns an error code
+ */
+-static int _hardware_dequeue(struct ci13xxx_ep *mEp, struct ci13xxx_req *mReq)
++static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
+ {
+- u32 tmptoken = le32_to_cpu(mReq->ptr->token);
++ u32 tmptoken;
++ struct td_node *node, *tmpnode;
++ unsigned remaining_length;
++ unsigned actual = hwreq->req.length;
+
+- if (mReq->req.status != -EALREADY)
++ if (hwreq->req.status != -EALREADY)
+ return -EINVAL;
+
+- if ((TD_STATUS_ACTIVE & tmptoken) != 0)
+- return -EBUSY;
++ hwreq->req.status = 0;
+
+- if (mReq->zptr) {
+- if ((cpu_to_le32(TD_STATUS_ACTIVE) & mReq->zptr->token) != 0)
++ list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
++ tmptoken = le32_to_cpu(node->ptr->token);
++ if ((TD_STATUS_ACTIVE & tmptoken) != 0) {
++ hwreq->req.status = -EALREADY;
+ return -EBUSY;
+- dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
+- mReq->zptr = NULL;
+- }
++ }
++
++ remaining_length = (tmptoken & TD_TOTAL_BYTES);
++ remaining_length >>= __ffs(TD_TOTAL_BYTES);
++ actual -= remaining_length;
++
++ hwreq->req.status = tmptoken & TD_STATUS;
++ if ((TD_STATUS_HALTED & hwreq->req.status)) {
++ hwreq->req.status = -EPIPE;
++ break;
++ } else if ((TD_STATUS_DT_ERR & hwreq->req.status)) {
++ hwreq->req.status = -EPROTO;
++ break;
++ } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
++ hwreq->req.status = -EILSEQ;
++ break;
++ }
+
+- mReq->req.status = 0;
++ if (remaining_length) {
++ if (hwep->dir) {
++ hwreq->req.status = -EPROTO;
++ break;
++ }
++ }
++ /*
++ * As the hardware could still address the freed td
++ * which will run the udc unusable, the cleanup of the
++ * td has to be delayed by one.
++ */
++ if (hwep->pending_td)
++ free_pending_td(hwep);
+
+- usb_gadget_unmap_request(&mEp->ci->gadget, &mReq->req, mEp->dir);
++ hwep->pending_td = node;
++ list_del_init(&node->td);
++ }
++
++ usb_gadget_unmap_request(&hwep->ci->gadget, &hwreq->req, hwep->dir);
+
+- mReq->req.status = tmptoken & TD_STATUS;
+- if ((TD_STATUS_HALTED & mReq->req.status) != 0)
+- mReq->req.status = -1;
+- else if ((TD_STATUS_DT_ERR & mReq->req.status) != 0)
+- mReq->req.status = -1;
+- else if ((TD_STATUS_TR_ERR & mReq->req.status) != 0)
+- mReq->req.status = -1;
++ hwreq->req.actual += actual;
+
+- mReq->req.actual = tmptoken & TD_TOTAL_BYTES;
+- mReq->req.actual >>= __ffs(TD_TOTAL_BYTES);
+- mReq->req.actual = mReq->req.length - mReq->req.actual;
+- mReq->req.actual = mReq->req.status ? 0 : mReq->req.actual;
++ if (hwreq->req.status)
++ return hwreq->req.status;
+
+- return mReq->req.actual;
++ return hwreq->req.actual;
+ }
+
+ /**
+ * _ep_nuke: dequeues all endpoint requests
+- * @mEp: endpoint
++ * @hwep: endpoint
+ *
+ * This function returns an error code
+ * Caller must hold lock
+ */
+-static int _ep_nuke(struct ci13xxx_ep *mEp)
+-__releases(mEp->lock)
+-__acquires(mEp->lock)
++static int _ep_nuke(struct ci_hw_ep *hwep)
++__releases(hwep->lock)
++__acquires(hwep->lock)
+ {
+- if (mEp == NULL)
++ struct td_node *node, *tmpnode;
++ if (hwep == NULL)
+ return -EINVAL;
+
+- hw_ep_flush(mEp->ci, mEp->num, mEp->dir);
++ hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
+
+- while (!list_empty(&mEp->qh.queue)) {
++ while (!list_empty(&hwep->qh.queue)) {
+
+ /* pop oldest request */
+- struct ci13xxx_req *mReq = \
+- list_entry(mEp->qh.queue.next,
+- struct ci13xxx_req, queue);
+-
+- if (mReq->zptr) {
+- dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
+- mReq->zptr = NULL;
++ struct ci_hw_req *hwreq = list_entry(hwep->qh.queue.next,
++ struct ci_hw_req, queue);
++
++ list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
++ dma_pool_free(hwep->td_pool, node->ptr, node->dma);
++ list_del_init(&node->td);
++ node->ptr = NULL;
++ kfree(node);
+ }
+
+- list_del_init(&mReq->queue);
+- mReq->req.status = -ESHUTDOWN;
++ list_del_init(&hwreq->queue);
++ hwreq->req.status = -ESHUTDOWN;
+
+- if (mReq->req.complete != NULL) {
+- spin_unlock(mEp->lock);
+- mReq->req.complete(&mEp->ep, &mReq->req);
+- spin_lock(mEp->lock);
++ if (hwreq->req.complete != NULL) {
++ spin_unlock(hwep->lock);
++ hwreq->req.complete(&hwep->ep, &hwreq->req);
++ spin_lock(hwep->lock);
+ }
+ }
++
++ if (hwep->pending_td)
++ free_pending_td(hwep);
++
+ return 0;
+ }
+
+@@ -567,15 +669,9 @@
+ static int _gadget_stop_activity(struct usb_gadget *gadget)
+ {
+ struct usb_ep *ep;
+- struct ci13xxx *ci = container_of(gadget, struct ci13xxx, gadget);
++ struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
+ unsigned long flags;
+
+- spin_lock_irqsave(&ci->lock, flags);
+- ci->gadget.speed = USB_SPEED_UNKNOWN;
+- ci->remote_wakeup = 0;
+- ci->suspended = 0;
+- spin_unlock_irqrestore(&ci->lock, flags);
+-
+ /* flush all endpoints */
+ gadget_for_each_ep(ep, gadget) {
+ usb_ep_fifo_flush(ep);
+@@ -583,9 +679,6 @@
+ usb_ep_fifo_flush(&ci->ep0out->ep);
+ usb_ep_fifo_flush(&ci->ep0in->ep);
+
+- if (ci->driver)
+- ci->driver->disconnect(gadget);
+-
+ /* make sure to disable all endpoints */
+ gadget_for_each_ep(ep, gadget) {
+ usb_ep_disable(ep);
+@@ -596,6 +689,12 @@
+ ci->status = NULL;
+ }
+
++ spin_lock_irqsave(&ci->lock, flags);
++ ci->gadget.speed = USB_SPEED_UNKNOWN;
++ ci->remote_wakeup = 0;
++ ci->suspended = 0;
++ spin_unlock_irqrestore(&ci->lock, flags);
++
+ return 0;
+ }
+
+@@ -608,13 +707,18 @@
+ *
+ * This function resets USB engine after a bus reset occurred
+ */
+-static void isr_reset_handler(struct ci13xxx *ci)
++static void isr_reset_handler(struct ci_hdrc *ci)
+ __releases(ci->lock)
+ __acquires(ci->lock)
+ {
+ int retval;
+
+ spin_unlock(&ci->lock);
++ if (ci->gadget.speed != USB_SPEED_UNKNOWN) {
++ if (ci->driver)
++ ci->driver->disconnect(&ci->gadget);
++ }
++
+ retval = _gadget_stop_activity(&ci->gadget);
+ if (retval)
+ goto done;
+@@ -658,47 +762,48 @@
+ static int _ep_queue(struct usb_ep *ep, struct usb_request *req,
+ gfp_t __maybe_unused gfp_flags)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+- struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
+- struct ci13xxx *ci = mEp->ci;
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
++ struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
++ struct ci_hdrc *ci = hwep->ci;
+ int retval = 0;
+
+- if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
++ if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
+ return -EINVAL;
+
+- if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
++ if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
+ if (req->length)
+- mEp = (ci->ep0_dir == RX) ?
++ hwep = (ci->ep0_dir == RX) ?
+ ci->ep0out : ci->ep0in;
+- if (!list_empty(&mEp->qh.queue)) {
+- _ep_nuke(mEp);
++ if (!list_empty(&hwep->qh.queue)) {
++ _ep_nuke(hwep);
+ retval = -EOVERFLOW;
+- dev_warn(mEp->ci->dev, "endpoint ctrl %X nuked\n",
+- _usb_addr(mEp));
++ dev_warn(hwep->ci->dev, "endpoint ctrl %X nuked\n",
++ _usb_addr(hwep));
+ }
+ }
+
+- /* first nuke then test link, e.g. previous status has not sent */
+- if (!list_empty(&mReq->queue)) {
+- dev_err(mEp->ci->dev, "request already in queue\n");
+- return -EBUSY;
++ if (usb_endpoint_xfer_isoc(hwep->ep.desc) &&
++ hwreq->req.length > (1 + hwep->ep.mult) * hwep->ep.maxpacket) {
++ dev_err(hwep->ci->dev, "request length too big for isochronous\n");
++ return -EMSGSIZE;
+ }
+
+- if (req->length > (TD_PAGE_COUNT - 1) * CI13XXX_PAGE_SIZE) {
+- dev_err(mEp->ci->dev, "request bigger than one td\n");
+- return -EMSGSIZE;
++ /* first nuke then test link, e.g. previous status has not sent */
++ if (!list_empty(&hwreq->queue)) {
++ dev_err(hwep->ci->dev, "request already in queue\n");
++ return -EBUSY;
+ }
+
+ /* push request */
+- mReq->req.status = -EINPROGRESS;
+- mReq->req.actual = 0;
++ hwreq->req.status = -EINPROGRESS;
++ hwreq->req.actual = 0;
+
+- retval = _hardware_enqueue(mEp, mReq);
++ retval = _hardware_enqueue(hwep, hwreq);
+
+ if (retval == -EALREADY)
+ retval = 0;
+ if (!retval)
+- list_add_tail(&mReq->queue, &mEp->qh.queue);
++ list_add_tail(&hwreq->queue, &hwep->qh.queue);
+
+ return retval;
+ }
+@@ -710,22 +815,22 @@
+ *
+ * This function returns an error code
+ */
+-static int isr_get_status_response(struct ci13xxx *ci,
++static int isr_get_status_response(struct ci_hdrc *ci,
+ struct usb_ctrlrequest *setup)
+-__releases(mEp->lock)
+-__acquires(mEp->lock)
++__releases(hwep->lock)
++__acquires(hwep->lock)
+ {
+- struct ci13xxx_ep *mEp = ci->ep0in;
++ struct ci_hw_ep *hwep = ci->ep0in;
+ struct usb_request *req = NULL;
+ gfp_t gfp_flags = GFP_ATOMIC;
+ int dir, num, retval;
+
+- if (mEp == NULL || setup == NULL)
++ if (hwep == NULL || setup == NULL)
+ return -EINVAL;
+
+- spin_unlock(mEp->lock);
+- req = usb_ep_alloc_request(&mEp->ep, gfp_flags);
+- spin_lock(mEp->lock);
++ spin_unlock(hwep->lock);
++ req = usb_ep_alloc_request(&hwep->ep, gfp_flags);
++ spin_lock(hwep->lock);
+ if (req == NULL)
+ return -ENOMEM;
+
+@@ -750,7 +855,7 @@
+ }
+ /* else do nothing; reserved for future use */
+
+- retval = _ep_queue(&mEp->ep, req, gfp_flags);
++ retval = _ep_queue(&hwep->ep, req, gfp_flags);
+ if (retval)
+ goto err_free_buf;
+
+@@ -759,9 +864,9 @@
+ err_free_buf:
+ kfree(req->buf);
+ err_free_req:
+- spin_unlock(mEp->lock);
+- usb_ep_free_request(&mEp->ep, req);
+- spin_lock(mEp->lock);
++ spin_unlock(hwep->lock);
++ usb_ep_free_request(&hwep->ep, req);
++ spin_lock(hwep->lock);
+ return retval;
+ }
+
+@@ -776,7 +881,7 @@
+ static void
+ isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
+ {
+- struct ci13xxx *ci = req->context;
++ struct ci_hdrc *ci = req->context;
+ unsigned long flags;
+
+ if (ci->setaddr) {
+@@ -796,48 +901,48 @@
+ *
+ * This function returns an error code
+ */
+-static int isr_setup_status_phase(struct ci13xxx *ci)
++static int isr_setup_status_phase(struct ci_hdrc *ci)
+ {
+ int retval;
+- struct ci13xxx_ep *mEp;
++ struct ci_hw_ep *hwep;
+
+- mEp = (ci->ep0_dir == TX) ? ci->ep0out : ci->ep0in;
++ hwep = (ci->ep0_dir == TX) ? ci->ep0out : ci->ep0in;
+ ci->status->context = ci;
+ ci->status->complete = isr_setup_status_complete;
+
+- retval = _ep_queue(&mEp->ep, ci->status, GFP_ATOMIC);
++ retval = _ep_queue(&hwep->ep, ci->status, GFP_ATOMIC);
+
+ return retval;
+ }
+
+ /**
+ * isr_tr_complete_low: transaction complete low level handler
+- * @mEp: endpoint
++ * @hwep: endpoint
+ *
+ * This function returns an error code
+ * Caller must hold lock
+ */
+-static int isr_tr_complete_low(struct ci13xxx_ep *mEp)
+-__releases(mEp->lock)
+-__acquires(mEp->lock)
++static int isr_tr_complete_low(struct ci_hw_ep *hwep)
++__releases(hwep->lock)
++__acquires(hwep->lock)
+ {
+- struct ci13xxx_req *mReq, *mReqTemp;
+- struct ci13xxx_ep *mEpTemp = mEp;
++ struct ci_hw_req *hwreq, *hwreqtemp;
++ struct ci_hw_ep *hweptemp = hwep;
+ int retval = 0;
+
+- list_for_each_entry_safe(mReq, mReqTemp, &mEp->qh.queue,
++ list_for_each_entry_safe(hwreq, hwreqtemp, &hwep->qh.queue,
+ queue) {
+- retval = _hardware_dequeue(mEp, mReq);
++ retval = _hardware_dequeue(hwep, hwreq);
+ if (retval < 0)
+ break;
+- list_del_init(&mReq->queue);
+- if (mReq->req.complete != NULL) {
+- spin_unlock(mEp->lock);
+- if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
+- mReq->req.length)
+- mEpTemp = mEp->ci->ep0in;
+- mReq->req.complete(&mEpTemp->ep, &mReq->req);
+- spin_lock(mEp->lock);
++ list_del_init(&hwreq->queue);
++ if (hwreq->req.complete != NULL) {
++ spin_unlock(hwep->lock);
++ if ((hwep->type == USB_ENDPOINT_XFER_CONTROL) &&
++ hwreq->req.length)
++ hweptemp = hwep->ci->ep0in;
++ hwreq->req.complete(&hweptemp->ep, &hwreq->req);
++ spin_lock(hwep->lock);
+ }
+ }
+
+@@ -853,7 +958,7 @@
+ *
+ * This function handles traffic events
+ */
+-static void isr_tr_complete_handler(struct ci13xxx *ci)
++static void isr_tr_complete_handler(struct ci_hdrc *ci)
+ __releases(ci->lock)
+ __acquires(ci->lock)
+ {
+@@ -861,21 +966,21 @@
+ u8 tmode = 0;
+
+ for (i = 0; i < ci->hw_ep_max; i++) {
+- struct ci13xxx_ep *mEp = &ci->ci13xxx_ep[i];
++ struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
+ int type, num, dir, err = -EINVAL;
+ struct usb_ctrlrequest req;
+
+- if (mEp->ep.desc == NULL)
++ if (hwep->ep.desc == NULL)
+ continue; /* not configured */
+
+ if (hw_test_and_clear_complete(ci, i)) {
+- err = isr_tr_complete_low(mEp);
+- if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
++ err = isr_tr_complete_low(hwep);
++ if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
+ if (err > 0) /* needs status phase */
+ err = isr_setup_status_phase(ci);
+ if (err < 0) {
+ spin_unlock(&ci->lock);
+- if (usb_ep_set_halt(&mEp->ep))
++ if (usb_ep_set_halt(&hwep->ep))
+ dev_err(ci->dev,
+ "error: ep_set_halt\n");
+ spin_lock(&ci->lock);
+@@ -883,7 +988,7 @@
+ }
+ }
+
+- if (mEp->type != USB_ENDPOINT_XFER_CONTROL ||
++ if (hwep->type != USB_ENDPOINT_XFER_CONTROL ||
+ !hw_test_and_clear_setup_status(ci, i))
+ continue;
+
+@@ -902,7 +1007,7 @@
+ /* read_setup_packet */
+ do {
+ hw_test_and_set_setup_guard(ci);
+- memcpy(&req, &mEp->qh.ptr->setup, sizeof(req));
++ memcpy(&req, &hwep->qh.ptr->setup, sizeof(req));
+ } while (!hw_test_and_clear_setup_guard(ci));
+
+ type = req.bRequestType;
+@@ -921,10 +1026,10 @@
+ num &= USB_ENDPOINT_NUMBER_MASK;
+ if (dir) /* TX */
+ num += ci->hw_ep_max/2;
+- if (!ci->ci13xxx_ep[num].wedge) {
++ if (!ci->ci_hw_ep[num].wedge) {
+ spin_unlock(&ci->lock);
+ err = usb_ep_clear_halt(
+- &ci->ci13xxx_ep[num].ep);
++ &ci->ci_hw_ep[num].ep);
+ spin_lock(&ci->lock);
+ if (err)
+ break;
+@@ -974,7 +1079,7 @@
+ num += ci->hw_ep_max/2;
+
+ spin_unlock(&ci->lock);
+- err = usb_ep_set_halt(&ci->ci13xxx_ep[num].ep);
++ err = usb_ep_set_halt(&ci->ci_hw_ep[num].ep);
+ spin_lock(&ci->lock);
+ if (!err)
+ isr_setup_status_phase(ci);
+@@ -1021,7 +1126,7 @@
+
+ if (err < 0) {
+ spin_unlock(&ci->lock);
+- if (usb_ep_set_halt(&mEp->ep))
++ if (usb_ep_set_halt(&hwep->ep))
+ dev_err(ci->dev, "error: ep_set_halt\n");
+ spin_lock(&ci->lock);
+ }
+@@ -1039,7 +1144,7 @@
+ static int ep_enable(struct usb_ep *ep,
+ const struct usb_endpoint_descriptor *desc)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
+ int retval = 0;
+ unsigned long flags;
+ u32 cap = 0;
+@@ -1047,39 +1152,41 @@
+ if (ep == NULL || desc == NULL)
+ return -EINVAL;
+
+- spin_lock_irqsave(mEp->lock, flags);
++ spin_lock_irqsave(hwep->lock, flags);
+
+ /* only internal SW should enable ctrl endpts */
+
+- mEp->ep.desc = desc;
++ hwep->ep.desc = desc;
+
+- if (!list_empty(&mEp->qh.queue))
+- dev_warn(mEp->ci->dev, "enabling a non-empty endpoint!\n");
++ if (!list_empty(&hwep->qh.queue))
++ dev_warn(hwep->ci->dev, "enabling a non-empty endpoint!\n");
+
+- mEp->dir = usb_endpoint_dir_in(desc) ? TX : RX;
+- mEp->num = usb_endpoint_num(desc);
+- mEp->type = usb_endpoint_type(desc);
++ hwep->dir = usb_endpoint_dir_in(desc) ? TX : RX;
++ hwep->num = usb_endpoint_num(desc);
++ hwep->type = usb_endpoint_type(desc);
+
+- mEp->ep.maxpacket = usb_endpoint_maxp(desc);
++ hwep->ep.maxpacket = usb_endpoint_maxp(desc) & 0x07ff;
++ hwep->ep.mult = QH_ISO_MULT(usb_endpoint_maxp(desc));
+
+- if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
++ if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
+ cap |= QH_IOS;
+- if (mEp->num)
++ if (hwep->num)
+ cap |= QH_ZLT;
+- cap |= (mEp->ep.maxpacket << __ffs(QH_MAX_PKT)) & QH_MAX_PKT;
++ cap |= (hwep->ep.maxpacket << __ffs(QH_MAX_PKT)) & QH_MAX_PKT;
+
+- mEp->qh.ptr->cap = cpu_to_le32(cap);
++ hwep->qh.ptr->cap = cpu_to_le32(cap);
+
+- mEp->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */
++ hwep->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */
+
+ /*
+ * Enable endpoints in the HW other than ep0 as ep0
+ * is always enabled
+ */
+- if (mEp->num)
+- retval |= hw_ep_enable(mEp->ci, mEp->num, mEp->dir, mEp->type);
++ if (hwep->num)
++ retval |= hw_ep_enable(hwep->ci, hwep->num, hwep->dir,
++ hwep->type);
+
+- spin_unlock_irqrestore(mEp->lock, flags);
++ spin_unlock_irqrestore(hwep->lock, flags);
+ return retval;
+ }
+
+@@ -1090,32 +1197,36 @@
+ */
+ static int ep_disable(struct usb_ep *ep)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
+ int direction, retval = 0;
+ unsigned long flags;
+
+ if (ep == NULL)
+ return -EINVAL;
+- else if (mEp->ep.desc == NULL)
++ else if (hwep->ep.desc == NULL)
+ return -EBUSY;
+
+- spin_lock_irqsave(mEp->lock, flags);
++ spin_lock_irqsave(hwep->lock, flags);
++ if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return 0;
++ }
+
+ /* only internal SW should disable ctrl endpts */
+
+- direction = mEp->dir;
++ direction = hwep->dir;
+ do {
+- retval |= _ep_nuke(mEp);
+- retval |= hw_ep_disable(mEp->ci, mEp->num, mEp->dir);
++ retval |= _ep_nuke(hwep);
++ retval |= hw_ep_disable(hwep->ci, hwep->num, hwep->dir);
+
+- if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
+- mEp->dir = (mEp->dir == TX) ? RX : TX;
++ if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
++ hwep->dir = (hwep->dir == TX) ? RX : TX;
+
+- } while (mEp->dir != direction);
++ } while (hwep->dir != direction);
+
+- mEp->ep.desc = NULL;
++ hwep->ep.desc = NULL;
+
+- spin_unlock_irqrestore(mEp->lock, flags);
++ spin_unlock_irqrestore(hwep->lock, flags);
+ return retval;
+ }
+
+@@ -1126,25 +1237,18 @@
+ */
+ static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+- struct ci13xxx_req *mReq = NULL;
++ struct ci_hw_req *hwreq = NULL;
+
+ if (ep == NULL)
+ return NULL;
+
+- mReq = kzalloc(sizeof(struct ci13xxx_req), gfp_flags);
+- if (mReq != NULL) {
+- INIT_LIST_HEAD(&mReq->queue);
+-
+- mReq->ptr = dma_pool_alloc(mEp->td_pool, gfp_flags,
+- &mReq->dma);
+- if (mReq->ptr == NULL) {
+- kfree(mReq);
+- mReq = NULL;
+- }
++ hwreq = kzalloc(sizeof(struct ci_hw_req), gfp_flags);
++ if (hwreq != NULL) {
++ INIT_LIST_HEAD(&hwreq->queue);
++ INIT_LIST_HEAD(&hwreq->tds);
+ }
+
+- return (mReq == NULL) ? NULL : &mReq->req;
++ return (hwreq == NULL) ? NULL : &hwreq->req;
+ }
+
+ /**
+@@ -1154,24 +1258,30 @@
+ */
+ static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+- struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
++ struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
++ struct td_node *node, *tmpnode;
+ unsigned long flags;
+
+ if (ep == NULL || req == NULL) {
+ return;
+- } else if (!list_empty(&mReq->queue)) {
+- dev_err(mEp->ci->dev, "freeing queued request\n");
++ } else if (!list_empty(&hwreq->queue)) {
++ dev_err(hwep->ci->dev, "freeing queued request\n");
+ return;
+ }
+
+- spin_lock_irqsave(mEp->lock, flags);
++ spin_lock_irqsave(hwep->lock, flags);
++
++ list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
++ dma_pool_free(hwep->td_pool, node->ptr, node->dma);
++ list_del_init(&node->td);
++ node->ptr = NULL;
++ kfree(node);
++ }
+
+- if (mReq->ptr)
+- dma_pool_free(mEp->td_pool, mReq->ptr, mReq->dma);
+- kfree(mReq);
++ kfree(hwreq);
+
+- spin_unlock_irqrestore(mEp->lock, flags);
++ spin_unlock_irqrestore(hwep->lock, flags);
+ }
+
+ /**
+@@ -1182,16 +1292,20 @@
+ static int ep_queue(struct usb_ep *ep, struct usb_request *req,
+ gfp_t __maybe_unused gfp_flags)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
+ int retval = 0;
+ unsigned long flags;
+
+- if (ep == NULL || req == NULL || mEp->ep.desc == NULL)
++ if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
+ return -EINVAL;
+
+- spin_lock_irqsave(mEp->lock, flags);
++ spin_lock_irqsave(hwep->lock, flags);
++ if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return 0;
++ }
+ retval = _ep_queue(ep, req, gfp_flags);
+- spin_unlock_irqrestore(mEp->lock, flags);
++ spin_unlock_irqrestore(hwep->lock, flags);
+ return retval;
+ }
+
+@@ -1202,33 +1316,33 @@
+ */
+ static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
+- struct ci13xxx_req *mReq = container_of(req, struct ci13xxx_req, req);
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
++ struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
+ unsigned long flags;
+
+- if (ep == NULL || req == NULL || mReq->req.status != -EALREADY ||
+- mEp->ep.desc == NULL || list_empty(&mReq->queue) ||
+- list_empty(&mEp->qh.queue))
++ if (ep == NULL || req == NULL || hwreq->req.status != -EALREADY ||
++ hwep->ep.desc == NULL || list_empty(&hwreq->queue) ||
++ list_empty(&hwep->qh.queue))
+ return -EINVAL;
+
+- spin_lock_irqsave(mEp->lock, flags);
+-
+- hw_ep_flush(mEp->ci, mEp->num, mEp->dir);
++ spin_lock_irqsave(hwep->lock, flags);
++ if (hwep->ci->gadget.speed != USB_SPEED_UNKNOWN)
++ hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
+
+ /* pop request */
+- list_del_init(&mReq->queue);
++ list_del_init(&hwreq->queue);
+
+- usb_gadget_unmap_request(&mEp->ci->gadget, req, mEp->dir);
++ usb_gadget_unmap_request(&hwep->ci->gadget, req, hwep->dir);
+
+ req->status = -ECONNRESET;
+
+- if (mReq->req.complete != NULL) {
+- spin_unlock(mEp->lock);
+- mReq->req.complete(&mEp->ep, &mReq->req);
+- spin_lock(mEp->lock);
++ if (hwreq->req.complete != NULL) {
++ spin_unlock(hwep->lock);
++ hwreq->req.complete(&hwep->ep, &hwreq->req);
++ spin_lock(hwep->lock);
+ }
+
+- spin_unlock_irqrestore(mEp->lock, flags);
++ spin_unlock_irqrestore(hwep->lock, flags);
+ return 0;
+ }
+
+@@ -1239,37 +1353,44 @@
+ */
+ static int ep_set_halt(struct usb_ep *ep, int value)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
+ int direction, retval = 0;
+ unsigned long flags;
+
+- if (ep == NULL || mEp->ep.desc == NULL)
++ if (ep == NULL || hwep->ep.desc == NULL)
+ return -EINVAL;
+
+- spin_lock_irqsave(mEp->lock, flags);
++ if (usb_endpoint_xfer_isoc(hwep->ep.desc))
++ return -EOPNOTSUPP;
+
++ spin_lock_irqsave(hwep->lock, flags);
++
++ if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return 0;
++ }
+ #ifndef STALL_IN
+ /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
+- if (value && mEp->type == USB_ENDPOINT_XFER_BULK && mEp->dir == TX &&
+- !list_empty(&mEp->qh.queue)) {
+- spin_unlock_irqrestore(mEp->lock, flags);
++ if (value && hwep->type == USB_ENDPOINT_XFER_BULK && hwep->dir == TX &&
++ !list_empty(&hwep->qh.queue)) {
++ spin_unlock_irqrestore(hwep->lock, flags);
+ return -EAGAIN;
+ }
+ #endif
+
+- direction = mEp->dir;
++ direction = hwep->dir;
+ do {
+- retval |= hw_ep_set_halt(mEp->ci, mEp->num, mEp->dir, value);
++ retval |= hw_ep_set_halt(hwep->ci, hwep->num, hwep->dir, value);
+
+ if (!value)
+- mEp->wedge = 0;
++ hwep->wedge = 0;
+
+- if (mEp->type == USB_ENDPOINT_XFER_CONTROL)
+- mEp->dir = (mEp->dir == TX) ? RX : TX;
++ if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
++ hwep->dir = (hwep->dir == TX) ? RX : TX;
+
+- } while (mEp->dir != direction);
++ } while (hwep->dir != direction);
+
+- spin_unlock_irqrestore(mEp->lock, flags);
++ spin_unlock_irqrestore(hwep->lock, flags);
+ return retval;
+ }
+
+@@ -1280,15 +1401,15 @@
+ */
+ static int ep_set_wedge(struct usb_ep *ep)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
+ unsigned long flags;
+
+- if (ep == NULL || mEp->ep.desc == NULL)
++ if (ep == NULL || hwep->ep.desc == NULL)
+ return -EINVAL;
+
+- spin_lock_irqsave(mEp->lock, flags);
+- mEp->wedge = 1;
+- spin_unlock_irqrestore(mEp->lock, flags);
++ spin_lock_irqsave(hwep->lock, flags);
++ hwep->wedge = 1;
++ spin_unlock_irqrestore(hwep->lock, flags);
+
+ return usb_ep_set_halt(ep);
+ }
+@@ -1300,19 +1421,23 @@
+ */
+ static void ep_fifo_flush(struct usb_ep *ep)
+ {
+- struct ci13xxx_ep *mEp = container_of(ep, struct ci13xxx_ep, ep);
++ struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
+ unsigned long flags;
+
+ if (ep == NULL) {
+- dev_err(mEp->ci->dev, "%02X: -EINVAL\n", _usb_addr(mEp));
++ dev_err(hwep->ci->dev, "%02X: -EINVAL\n", _usb_addr(hwep));
+ return;
+ }
+
+- spin_lock_irqsave(mEp->lock, flags);
++ spin_lock_irqsave(hwep->lock, flags);
++ if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return;
++ }
+
+- hw_ep_flush(mEp->ci, mEp->num, mEp->dir);
++ hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
+
+- spin_unlock_irqrestore(mEp->lock, flags);
++ spin_unlock_irqrestore(hwep->lock, flags);
+ }
+
+ /**
+@@ -1334,14 +1459,12 @@
+ /******************************************************************************
+ * GADGET block
+ *****************************************************************************/
+-static int ci13xxx_vbus_session(struct usb_gadget *_gadget, int is_active)
++static int ci_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
+ {
+- struct ci13xxx *ci = container_of(_gadget, struct ci13xxx, gadget);
++ struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
+ unsigned long flags;
+ int gadget_ready = 0;
+-
+- if (!(ci->platdata->flags & CI13XXX_PULLUP_ON_VBUS))
+- return -EOPNOTSUPP;
++ int ret;
+
+ spin_lock_irqsave(&ci->lock, flags);
+ ci->vbus_active = is_active;
+@@ -1349,31 +1472,66 @@
+ gadget_ready = 1;
+ spin_unlock_irqrestore(&ci->lock, flags);
+
++ /* Charger Detection */
++ if (ci->platdata->notify_event) {
++ /*
++ * Keep controller active when the cable is connected,
++ * It can make disconnect interrupt (BSV 1->0) occur when
++ * the cable is disconnected.
++ */
++ if (is_active) {
++ pm_runtime_get_sync(&_gadget->dev);
++ hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
++ } else {
++ pm_runtime_put_sync(&_gadget->dev);
++ }
++
++ ret = ci->platdata->notify_event
++ (ci, CI_HDRC_CONTROLLER_CHARGER_EVENT);
++ if (ret == CI_HDRC_NOTIFY_RET_DEFER_EVENT) {
++ hw_device_reset(ci, USBMODE_CM_DC);
++ /* Pull up dp */
++ hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
++ ci->platdata->notify_event
++ (ci, CI_HDRC_CONTROLLER_CHARGER_POST_EVENT);
++ /* Pull down dp */
++ hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
++ }
++ }
++
+ if (gadget_ready) {
+ if (is_active) {
+ pm_runtime_get_sync(&_gadget->dev);
+ hw_device_reset(ci, USBMODE_CM_DC);
+ hw_device_state(ci, ci->ep0out->qh.dma);
++ dev_dbg(ci->dev, "Connected to host\n");
+ } else {
++ if (ci->driver)
++ ci->driver->disconnect(&ci->gadget);
+ hw_device_state(ci, 0);
+ if (ci->platdata->notify_event)
+ ci->platdata->notify_event(ci,
+- CI13XXX_CONTROLLER_STOPPED_EVENT);
++ CI_HDRC_CONTROLLER_STOPPED_EVENT);
+ _gadget_stop_activity(&ci->gadget);
+ pm_runtime_put_sync(&_gadget->dev);
++ dev_dbg(ci->dev, "Disconnected from host\n");
+ }
+ }
+
+ return 0;
+ }
+
+-static int ci13xxx_wakeup(struct usb_gadget *_gadget)
++static int ci_udc_wakeup(struct usb_gadget *_gadget)
+ {
+- struct ci13xxx *ci = container_of(_gadget, struct ci13xxx, gadget);
++ struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
+ unsigned long flags;
+ int ret = 0;
+
+ spin_lock_irqsave(&ci->lock, flags);
++ if (ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(&ci->lock, flags);
++ return 0;
++ }
+ if (!ci->remote_wakeup) {
+ ret = -EOPNOTSUPP;
+ goto out;
+@@ -1388,21 +1546,24 @@
+ return ret;
+ }
+
+-static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
++static int ci_udc_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
+ {
+- struct ci13xxx *ci = container_of(_gadget, struct ci13xxx, gadget);
++ struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
+
+ if (ci->transceiver)
+- return usb_phy_set_power(ci->transceiver, mA);
++ return usb_phy_set_power(ci->transceiver, ma);
+ return -ENOTSUPP;
+ }
+
+ /* Change Data+ pullup status
+ * this func is used by usb_gadget_connect/disconnet
+ */
+-static int ci13xxx_pullup(struct usb_gadget *_gadget, int is_on)
++static int ci_udc_pullup(struct usb_gadget *_gadget, int is_on)
+ {
+- struct ci13xxx *ci = container_of(_gadget, struct ci13xxx, gadget);
++ struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
++
++ if (!ci->vbus_active)
++ return -EOPNOTSUPP;
+
+ if (is_on)
+ hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
+@@ -1412,9 +1573,9 @@
+ return 0;
+ }
+
+-static int ci13xxx_start(struct usb_gadget *gadget,
++static int ci_udc_start(struct usb_gadget *gadget,
+ struct usb_gadget_driver *driver);
+-static int ci13xxx_stop(struct usb_gadget *gadget,
++static int ci_udc_stop(struct usb_gadget *gadget,
+ struct usb_gadget_driver *driver);
+ /**
+ * Device operations part of the API to the USB controller hardware,
+@@ -1422,46 +1583,46 @@
+ * Check "usb_gadget.h" for details
+ */
+ static const struct usb_gadget_ops usb_gadget_ops = {
+- .vbus_session = ci13xxx_vbus_session,
+- .wakeup = ci13xxx_wakeup,
+- .pullup = ci13xxx_pullup,
+- .vbus_draw = ci13xxx_vbus_draw,
+- .udc_start = ci13xxx_start,
+- .udc_stop = ci13xxx_stop,
++ .vbus_session = ci_udc_vbus_session,
++ .wakeup = ci_udc_wakeup,
++ .pullup = ci_udc_pullup,
++ .vbus_draw = ci_udc_vbus_draw,
++ .udc_start = ci_udc_start,
++ .udc_stop = ci_udc_stop,
+ };
+
+-static int init_eps(struct ci13xxx *ci)
++static int init_eps(struct ci_hdrc *ci)
+ {
+ int retval = 0, i, j;
+
+ for (i = 0; i < ci->hw_ep_max/2; i++)
+ for (j = RX; j <= TX; j++) {
+ int k = i + j * ci->hw_ep_max/2;
+- struct ci13xxx_ep *mEp = &ci->ci13xxx_ep[k];
++ struct ci_hw_ep *hwep = &ci->ci_hw_ep[k];
+
+- scnprintf(mEp->name, sizeof(mEp->name), "ep%i%s", i,
++ scnprintf(hwep->name, sizeof(hwep->name), "ep%i%s", i,
+ (j == TX) ? "in" : "out");
+
+- mEp->ci = ci;
+- mEp->lock = &ci->lock;
+- mEp->td_pool = ci->td_pool;
++ hwep->ci = ci;
++ hwep->lock = &ci->lock;
++ hwep->td_pool = ci->td_pool;
+
+- mEp->ep.name = mEp->name;
+- mEp->ep.ops = &usb_ep_ops;
++ hwep->ep.name = hwep->name;
++ hwep->ep.ops = &usb_ep_ops;
+ /*
+ * for ep0: maxP defined in desc, for other
+ * eps, maxP is set by epautoconfig() called
+ * by gadget layer
+ */
+- mEp->ep.maxpacket = (unsigned short)~0;
++ hwep->ep.maxpacket = (unsigned short)~0;
+
+- INIT_LIST_HEAD(&mEp->qh.queue);
+- mEp->qh.ptr = dma_pool_alloc(ci->qh_pool, GFP_KERNEL,
+- &mEp->qh.dma);
+- if (mEp->qh.ptr == NULL)
++ INIT_LIST_HEAD(&hwep->qh.queue);
++ hwep->qh.ptr = dma_pool_alloc(ci->qh_pool, GFP_KERNEL,
++ &hwep->qh.dma);
++ if (hwep->qh.ptr == NULL)
+ retval = -ENOMEM;
+ else
+- memset(mEp->qh.ptr, 0, sizeof(*mEp->qh.ptr));
++ memset(hwep->qh.ptr, 0, sizeof(*hwep->qh.ptr));
+
+ /*
+ * set up shorthands for ep0 out and in endpoints,
+@@ -1469,42 +1630,44 @@
+ */
+ if (i == 0) {
+ if (j == RX)
+- ci->ep0out = mEp;
++ ci->ep0out = hwep;
+ else
+- ci->ep0in = mEp;
++ ci->ep0in = hwep;
+
+- mEp->ep.maxpacket = CTRL_PAYLOAD_MAX;
++ hwep->ep.maxpacket = CTRL_PAYLOAD_MAX;
+ continue;
+ }
+
+- list_add_tail(&mEp->ep.ep_list, &ci->gadget.ep_list);
++ list_add_tail(&hwep->ep.ep_list, &ci->gadget.ep_list);
+ }
+
+ return retval;
+ }
+
+-static void destroy_eps(struct ci13xxx *ci)
++static void destroy_eps(struct ci_hdrc *ci)
+ {
+ int i;
+
+ for (i = 0; i < ci->hw_ep_max; i++) {
+- struct ci13xxx_ep *mEp = &ci->ci13xxx_ep[i];
++ struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
+
+- dma_pool_free(ci->qh_pool, mEp->qh.ptr, mEp->qh.dma);
++ if (hwep->pending_td)
++ free_pending_td(hwep);
++ dma_pool_free(ci->qh_pool, hwep->qh.ptr, hwep->qh.dma);
+ }
+ }
+
+ /**
+- * ci13xxx_start: register a gadget driver
++ * ci_udc_start: register a gadget driver
+ * @gadget: our gadget
+ * @driver: the driver being registered
+ *
+ * Interrupts are enabled here.
+ */
+-static int ci13xxx_start(struct usb_gadget *gadget,
++static int ci_udc_start(struct usb_gadget *gadget,
+ struct usb_gadget_driver *driver)
+ {
+- struct ci13xxx *ci = container_of(gadget, struct ci13xxx, gadget);
++ struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
+ unsigned long flags;
+ int retval = -ENOMEM;
+
+@@ -1521,53 +1684,48 @@
+ retval = usb_ep_enable(&ci->ep0in->ep);
+ if (retval)
+ return retval;
+- spin_lock_irqsave(&ci->lock, flags);
+
+ ci->driver = driver;
+ pm_runtime_get_sync(&ci->gadget.dev);
+- if (ci->platdata->flags & CI13XXX_PULLUP_ON_VBUS) {
+- if (ci->vbus_active) {
+- if (ci->platdata->flags & CI13XXX_REGS_SHARED)
+- hw_device_reset(ci, USBMODE_CM_DC);
+- } else {
+- pm_runtime_put_sync(&ci->gadget.dev);
+- goto done;
+- }
++ if (ci->vbus_active) {
++ spin_lock_irqsave(&ci->lock, flags);
++ hw_device_reset(ci, USBMODE_CM_DC);
++ } else {
++ pm_runtime_put_sync(&ci->gadget.dev);
++ return retval;
+ }
+
+ retval = hw_device_state(ci, ci->ep0out->qh.dma);
++ spin_unlock_irqrestore(&ci->lock, flags);
+ if (retval)
+ pm_runtime_put_sync(&ci->gadget.dev);
+
+- done:
+- spin_unlock_irqrestore(&ci->lock, flags);
+ return retval;
+ }
+
+ /**
+- * ci13xxx_stop: unregister a gadget driver
++ * ci_udc_stop: unregister a gadget driver
+ */
+-static int ci13xxx_stop(struct usb_gadget *gadget,
++static int ci_udc_stop(struct usb_gadget *gadget,
+ struct usb_gadget_driver *driver)
+ {
+- struct ci13xxx *ci = container_of(gadget, struct ci13xxx, gadget);
++ struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
+ unsigned long flags;
+
+ spin_lock_irqsave(&ci->lock, flags);
+
+- if (!(ci->platdata->flags & CI13XXX_PULLUP_ON_VBUS) ||
+- ci->vbus_active) {
++ if (ci->vbus_active) {
+ hw_device_state(ci, 0);
+ if (ci->platdata->notify_event)
+ ci->platdata->notify_event(ci,
+- CI13XXX_CONTROLLER_STOPPED_EVENT);
+- ci->driver = NULL;
++ CI_HDRC_CONTROLLER_STOPPED_EVENT);
+ spin_unlock_irqrestore(&ci->lock, flags);
+ _gadget_stop_activity(&ci->gadget);
+ spin_lock_irqsave(&ci->lock, flags);
+ pm_runtime_put(&ci->gadget.dev);
+ }
+
++ ci->driver = NULL;
+ spin_unlock_irqrestore(&ci->lock, flags);
+
+ return 0;
+@@ -1582,7 +1740,7 @@
+ * This function returns IRQ_HANDLED if the IRQ has been handled
+ * It locks access to registers
+ */
+-static irqreturn_t udc_irq(struct ci13xxx *ci)
++static irqreturn_t udc_irq(struct ci_hdrc *ci)
+ {
+ irqreturn_t retval;
+ u32 intr;
+@@ -1592,7 +1750,7 @@
+
+ spin_lock(&ci->lock);
+
+- if (ci->platdata->flags & CI13XXX_REGS_SHARED) {
++ if (ci->platdata->flags & CI_HDRC_REGS_SHARED) {
+ if (hw_read(ci, OP_USBMODE, USBMODE_CM) !=
+ USBMODE_CM_DC) {
+ spin_unlock(&ci->lock);
+@@ -1642,7 +1800,7 @@
+ * udc_start: initialize gadget role
+ * @ci: chipidea controller
+ */
+-static int udc_start(struct ci13xxx *ci)
++static int udc_start(struct ci_hdrc *ci)
+ {
+ struct device *dev = ci->dev;
+ int retval = 0;
+@@ -1658,15 +1816,15 @@
+ INIT_LIST_HEAD(&ci->gadget.ep_list);
+
+ /* alloc resources */
+- ci->qh_pool = dma_pool_create("ci13xxx_qh", dev,
+- sizeof(struct ci13xxx_qh),
+- 64, CI13XXX_PAGE_SIZE);
++ ci->qh_pool = dma_pool_create("ci_hw_qh", dev,
++ sizeof(struct ci_hw_qh),
++ 64, CI_HDRC_PAGE_SIZE);
+ if (ci->qh_pool == NULL)
+ return -ENOMEM;
+
+- ci->td_pool = dma_pool_create("ci13xxx_td", dev,
+- sizeof(struct ci13xxx_td),
+- 64, CI13XXX_PAGE_SIZE);
++ ci->td_pool = dma_pool_create("ci_hw_td", dev,
++ sizeof(struct ci_hw_td),
++ 64, CI_HDRC_PAGE_SIZE);
+ if (ci->td_pool == NULL) {
+ retval = -ENOMEM;
+ goto free_qh_pool;
+@@ -1678,52 +1836,15 @@
+
+ ci->gadget.ep0 = &ci->ep0in->ep;
+
+- if (ci->global_phy) {
+- ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+- if (IS_ERR(ci->transceiver))
+- ci->transceiver = NULL;
+- }
+-
+- if (ci->platdata->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
+- if (ci->transceiver == NULL) {
+- retval = -ENODEV;
+- goto destroy_eps;
+- }
+- }
+-
+- if (!(ci->platdata->flags & CI13XXX_REGS_SHARED)) {
+- retval = hw_device_reset(ci, USBMODE_CM_DC);
+- if (retval)
+- goto put_transceiver;
+- }
+-
+- if (ci->transceiver) {
+- retval = otg_set_peripheral(ci->transceiver->otg,
+- &ci->gadget);
+- if (retval)
+- goto put_transceiver;
+- }
+-
+ retval = usb_add_gadget_udc(dev, &ci->gadget);
+ if (retval)
+- goto remove_trans;
++ goto destroy_eps;
+
+ pm_runtime_no_callbacks(&ci->gadget.dev);
+ pm_runtime_enable(&ci->gadget.dev);
+
+ return retval;
+
+-remove_trans:
+- if (ci->transceiver) {
+- otg_set_peripheral(ci->transceiver->otg, NULL);
+- if (ci->global_phy)
+- usb_put_phy(ci->transceiver);
+- }
+-
+- dev_err(dev, "error = %i\n", retval);
+-put_transceiver:
+- if (ci->transceiver && ci->global_phy)
+- usb_put_phy(ci->transceiver);
+ destroy_eps:
+ destroy_eps(ci);
+ free_pools:
+@@ -1734,13 +1855,13 @@
+ }
+
+ /**
+- * udc_remove: parent remove must call this to remove UDC
++ * ci_hdrc_gadget_destroy: parent remove must call this to remove UDC
+ *
+ * No interrupts active, the IRQ has been released
+ */
+-static void udc_stop(struct ci13xxx *ci)
++void ci_hdrc_gadget_destroy(struct ci_hdrc *ci)
+ {
+- if (ci == NULL)
++ if (!ci->roles[CI_ROLE_GADGET])
+ return;
+
+ usb_del_gadget_udc(&ci->gadget);
+@@ -1755,17 +1876,34 @@
+ if (ci->global_phy)
+ usb_put_phy(ci->transceiver);
+ }
+- /* my kobject is dynamic, I swear! */
+- memset(&ci->gadget, 0, sizeof(ci->gadget));
++}
++
++static int udc_id_switch_for_device(struct ci_hdrc *ci)
++{
++ if (ci->is_otg) {
++ ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
++ ci_enable_otg_interrupt(ci, OTGSC_BSVIE);
++ }
++
++ return 0;
++}
++
++static void udc_id_switch_for_host(struct ci_hdrc *ci)
++{
++ if (ci->is_otg) {
++ /* host doesn't care B_SESSION_VALID event */
++ ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
++ ci_disable_otg_interrupt(ci, OTGSC_BSVIE);
++ }
+ }
+
+ /**
+ * ci_hdrc_gadget_init - initialize device related bits
+ * ci: the controller
+ *
+- * This function enables the gadget role, if the device is "device capable".
++ * This function initializes the gadget, if the device is "device capable".
+ */
+-int ci_hdrc_gadget_init(struct ci13xxx *ci)
++int ci_hdrc_gadget_init(struct ci_hdrc *ci)
+ {
+ struct ci_role_driver *rdrv;
+
+@@ -1776,11 +1914,11 @@
+ if (!rdrv)
+ return -ENOMEM;
+
+- rdrv->start = udc_start;
+- rdrv->stop = udc_stop;
++ rdrv->start = udc_id_switch_for_device;
++ rdrv->stop = udc_id_switch_for_host;
+ rdrv->irq = udc_irq;
+ rdrv->name = "gadget";
+ ci->roles[CI_ROLE_GADGET] = rdrv;
+
+- return 0;
++ return udc_start(ci);
+ }
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/udc.h linux-linaro-stable-mx6/drivers/usb/chipidea/udc.h
+--- linux-3.10.30.orig/drivers/usb/chipidea/udc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/udc.h 2014-05-15 20:34:08.202087385 +0200
+@@ -20,7 +20,7 @@
+ #define TX 1 /* similar to USB_DIR_IN but can be used as an index */
+
+ /* DMA layout of transfer descriptors */
+-struct ci13xxx_td {
++struct ci_hw_td {
+ /* 0 */
+ u32 next;
+ #define TD_TERMINATE BIT(0)
+@@ -43,24 +43,31 @@
+ } __attribute__ ((packed, aligned(4)));
+
+ /* DMA layout of queue heads */
+-struct ci13xxx_qh {
++struct ci_hw_qh {
+ /* 0 */
+ u32 cap;
+ #define QH_IOS BIT(15)
+ #define QH_MAX_PKT (0x07FFUL << 16)
+ #define QH_ZLT BIT(29)
+ #define QH_MULT (0x0003UL << 30)
++#define QH_ISO_MULT(x) ((x >> 11) & 0x03)
+ /* 1 */
+ u32 curr;
+ /* 2 - 8 */
+- struct ci13xxx_td td;
++ struct ci_hw_td td;
+ /* 9 */
+ u32 RESERVED;
+ struct usb_ctrlrequest setup;
+ } __attribute__ ((packed, aligned(4)));
+
++struct td_node {
++ struct list_head td;
++ dma_addr_t dma;
++ struct ci_hw_td *ptr;
++};
++
+ /**
+- * struct ci13xxx_req - usb request representation
++ * struct ci_hw_req - usb request representation
+ * @req: request structure for gadget drivers
+ * @queue: link to QH list
+ * @ptr: transfer descriptor for this request
+@@ -68,26 +75,29 @@
+ * @zptr: transfer descriptor for the zero packet
+ * @zdma: dma address of the zero packet's transfer descriptor
+ */
+-struct ci13xxx_req {
++struct ci_hw_req {
+ struct usb_request req;
+ struct list_head queue;
+- struct ci13xxx_td *ptr;
+- dma_addr_t dma;
+- struct ci13xxx_td *zptr;
+- dma_addr_t zdma;
++ struct list_head tds;
+ };
+
+ #ifdef CONFIG_USB_CHIPIDEA_UDC
+
+-int ci_hdrc_gadget_init(struct ci13xxx *ci);
++int ci_hdrc_gadget_init(struct ci_hdrc *ci);
++void ci_hdrc_gadget_destroy(struct ci_hdrc *ci);
+
+ #else
+
+-static inline int ci_hdrc_gadget_init(struct ci13xxx *ci)
++static inline int ci_hdrc_gadget_init(struct ci_hdrc *ci)
+ {
+ return -ENXIO;
+ }
+
++static inline void ci_hdrc_gadget_destroy(struct ci_hdrc *ci)
++{
++
++}
++
+ #endif
+
+ #endif /* __DRIVERS_USB_CHIPIDEA_UDC_H */
+diff -Nur linux-3.10.30.orig/drivers/usb/chipidea/usbmisc_imx.c linux-linaro-stable-mx6/drivers/usb/chipidea/usbmisc_imx.c
+--- linux-3.10.30.orig/drivers/usb/chipidea/usbmisc_imx.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/chipidea/usbmisc_imx.c 2014-05-15 20:34:08.202087385 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+@@ -11,14 +11,11 @@
+
+ #include <linux/module.h>
+ #include <linux/of_platform.h>
+-#include <linux/clk.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/delay.h>
+
+-#include "ci13xxx_imx.h"
+-
+-#define USB_DEV_MAX 4
++#include "ci_hdrc_imx.h"
+
+ #define MX25_USB_PHY_CTRL_OFFSET 0x08
+ #define MX25_BM_EXTERNAL_VBUS_DIVIDER BIT(23)
+@@ -31,52 +28,40 @@
+ #define MX53_BM_OVER_CUR_DIS_UHx BIT(30)
+
+ #define MX6_BM_OVER_CUR_DIS BIT(7)
++#define MX6_BM_WAKEUP_ENABLE BIT(10)
++#define MX6_BM_ID_WAKEUP BIT(16)
++#define MX6_BM_VBUS_WAKEUP BIT(17)
++#define MX6_BM_WAKEUP_INTR BIT(31)
++
++struct usbmisc_ops {
++ /* It's called once when probe a usb device */
++ int (*init)(struct imx_usbmisc_data *data);
++ /* It's called once after adding a usb device */
++ int (*post)(struct imx_usbmisc_data *data);
++ /* It's called when we need to enable usb wakeup */
++ int (*set_wakeup)(struct imx_usbmisc_data *data, bool enabled);
++};
+
+ struct imx_usbmisc {
+ void __iomem *base;
+ spinlock_t lock;
+- struct clk *clk;
+- struct usbmisc_usb_device usbdev[USB_DEV_MAX];
+ const struct usbmisc_ops *ops;
+ };
+
+ static struct imx_usbmisc *usbmisc;
+
+-static struct usbmisc_usb_device *get_usbdev(struct device *dev)
+-{
+- int i, ret;
+-
+- for (i = 0; i < USB_DEV_MAX; i++) {
+- if (usbmisc->usbdev[i].dev == dev)
+- return &usbmisc->usbdev[i];
+- else if (!usbmisc->usbdev[i].dev)
+- break;
+- }
+-
+- if (i >= USB_DEV_MAX)
+- return ERR_PTR(-EBUSY);
+-
+- ret = usbmisc_get_init_data(dev, &usbmisc->usbdev[i]);
+- if (ret)
+- return ERR_PTR(ret);
+-
+- return &usbmisc->usbdev[i];
+-}
+-
+-static int usbmisc_imx25_post(struct device *dev)
++static int usbmisc_imx25_post(struct imx_usbmisc_data *data)
+ {
+- struct usbmisc_usb_device *usbdev;
+ void __iomem *reg;
+ unsigned long flags;
+ u32 val;
+
+- usbdev = get_usbdev(dev);
+- if (IS_ERR(usbdev))
+- return PTR_ERR(usbdev);
++ if (data->index > 2)
++ return -EINVAL;
+
+ reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET;
+
+- if (usbdev->evdo) {
++ if (data->evdo) {
+ spin_lock_irqsave(&usbmisc->lock, flags);
+ val = readl(reg);
+ writel(val | MX25_BM_EXTERNAL_VBUS_DIVIDER, reg);
+@@ -87,20 +72,18 @@
+ return 0;
+ }
+
+-static int usbmisc_imx53_init(struct device *dev)
++static int usbmisc_imx53_init(struct imx_usbmisc_data *data)
+ {
+- struct usbmisc_usb_device *usbdev;
+ void __iomem *reg = NULL;
+ unsigned long flags;
+ u32 val = 0;
+
+- usbdev = get_usbdev(dev);
+- if (IS_ERR(usbdev))
+- return PTR_ERR(usbdev);
++ if (data->index > 3)
++ return -EINVAL;
+
+- if (usbdev->disable_oc) {
++ if (data->disable_oc) {
+ spin_lock_irqsave(&usbmisc->lock, flags);
+- switch (usbdev->index) {
++ switch (data->index) {
+ case 0:
+ reg = usbmisc->base + MX53_USB_OTG_PHY_CTRL_0_OFFSET;
+ val = readl(reg) | MX53_BM_OVER_CUR_DIS_OTG;
+@@ -126,28 +109,49 @@
+ return 0;
+ }
+
+-static int usbmisc_imx6q_init(struct device *dev)
++static int usbmisc_imx6q_init(struct imx_usbmisc_data *data)
+ {
+-
+- struct usbmisc_usb_device *usbdev;
+ unsigned long flags;
+ u32 reg;
+
+- usbdev = get_usbdev(dev);
+- if (IS_ERR(usbdev))
+- return PTR_ERR(usbdev);
++ if (data->index > 3)
++ return -EINVAL;
+
+- if (usbdev->disable_oc) {
++ if (data->disable_oc) {
+ spin_lock_irqsave(&usbmisc->lock, flags);
+- reg = readl(usbmisc->base + usbdev->index * 4);
++ reg = readl(usbmisc->base + data->index * 4);
+ writel(reg | MX6_BM_OVER_CUR_DIS,
+- usbmisc->base + usbdev->index * 4);
++ usbmisc->base + data->index * 4);
+ spin_unlock_irqrestore(&usbmisc->lock, flags);
+ }
+
+ return 0;
+ }
+
++static int usbmisc_imx6q_set_wakeup
++ (struct imx_usbmisc_data *data, bool enabled)
++{
++ unsigned long flags;
++ u32 reg, val = MX6_BM_WAKEUP_ENABLE | MX6_BM_VBUS_WAKEUP
++ | MX6_BM_ID_WAKEUP;
++
++ if (data->index > 3)
++ return -EINVAL;
++
++ spin_lock_irqsave(&usbmisc->lock, flags);
++ reg = readl(usbmisc->base + data->index * 4);
++ if (enabled) {
++ writel(reg | val, usbmisc->base + data->index * 4);
++ } else {
++ if (reg & MX6_BM_WAKEUP_INTR)
++ pr_debug("wakeup int at ci_hdrc.%d\n", data->index);
++ writel(reg & ~val, usbmisc->base + data->index * 4);
++ }
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++
++ return 0;
++}
++
+ static const struct usbmisc_ops imx25_usbmisc_ops = {
+ .post = usbmisc_imx25_post,
+ };
+@@ -158,8 +162,39 @@
+
+ static const struct usbmisc_ops imx6q_usbmisc_ops = {
+ .init = usbmisc_imx6q_init,
++ .set_wakeup = usbmisc_imx6q_set_wakeup,
+ };
+
++int imx_usbmisc_init(struct imx_usbmisc_data *data)
++{
++ if (!usbmisc)
++ return -EPROBE_DEFER;
++ if (!usbmisc->ops->init)
++ return 0;
++ return usbmisc->ops->init(data);
++}
++EXPORT_SYMBOL_GPL(imx_usbmisc_init);
++
++int imx_usbmisc_init_post(struct imx_usbmisc_data *data)
++{
++ if (!usbmisc)
++ return -EPROBE_DEFER;
++ if (!usbmisc->ops->post)
++ return 0;
++ return usbmisc->ops->post(data);
++}
++EXPORT_SYMBOL_GPL(imx_usbmisc_init_post);
++
++int imx_usbmisc_set_wakeup(struct imx_usbmisc_data *data, bool enabled)
++{
++ if (!usbmisc)
++ return -ENODEV;
++ if (!usbmisc->ops->set_wakeup)
++ return 0;
++ return usbmisc->ops->set_wakeup(data, enabled);
++}
++EXPORT_SYMBOL_GPL(imx_usbmisc_set_wakeup);
++
+ static const struct of_device_id usbmisc_imx_dt_ids[] = {
+ {
+ .compatible = "fsl,imx25-usbmisc",
+@@ -175,12 +210,12 @@
+ },
+ { /* sentinel */ }
+ };
++MODULE_DEVICE_TABLE(of, usbmisc_imx_dt_ids);
+
+ static int usbmisc_imx_probe(struct platform_device *pdev)
+ {
+ struct resource *res;
+ struct imx_usbmisc *data;
+- int ret;
+ struct of_device_id *tmp_dev;
+
+ if (usbmisc)
+@@ -197,38 +232,16 @@
+ if (IS_ERR(data->base))
+ return PTR_ERR(data->base);
+
+- data->clk = devm_clk_get(&pdev->dev, NULL);
+- if (IS_ERR(data->clk)) {
+- dev_err(&pdev->dev,
+- "failed to get clock, err=%ld\n", PTR_ERR(data->clk));
+- return PTR_ERR(data->clk);
+- }
+-
+- ret = clk_prepare_enable(data->clk);
+- if (ret) {
+- dev_err(&pdev->dev,
+- "clk_prepare_enable failed, err=%d\n", ret);
+- return ret;
+- }
+-
+ tmp_dev = (struct of_device_id *)
+ of_match_device(usbmisc_imx_dt_ids, &pdev->dev);
+ data->ops = (const struct usbmisc_ops *)tmp_dev->data;
+ usbmisc = data;
+- ret = usbmisc_set_ops(data->ops);
+- if (ret) {
+- usbmisc = NULL;
+- clk_disable_unprepare(data->clk);
+- return ret;
+- }
+
+ return 0;
+ }
+
+ static int usbmisc_imx_remove(struct platform_device *pdev)
+ {
+- usbmisc_unset_ops(usbmisc->ops);
+- clk_disable_unprepare(usbmisc->clk);
+ usbmisc = NULL;
+ return 0;
+ }
+@@ -243,17 +256,7 @@
+ },
+ };
+
+-int usbmisc_imx_drv_init(void)
+-{
+- return platform_driver_register(&usbmisc_imx_driver);
+-}
+-subsys_initcall(usbmisc_imx_drv_init);
+-
+-void usbmisc_imx_drv_exit(void)
+-{
+- platform_driver_unregister(&usbmisc_imx_driver);
+-}
+-module_exit(usbmisc_imx_drv_exit);
++module_platform_driver(usbmisc_imx_driver);
+
+ MODULE_ALIAS("platform:usbmisc-imx");
+ MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/usb/core/hcd.c linux-linaro-stable-mx6/drivers/usb/core/hcd.c
+--- linux-3.10.30.orig/drivers/usb/core/hcd.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/core/hcd.c 2014-05-15 20:34:08.234087614 +0200
+@@ -2575,12 +2575,6 @@
+ if (hcd->uses_new_polling && HCD_POLL_RH(hcd))
+ usb_hcd_poll_rh_status(hcd);
+
+- /*
+- * Host controllers don't generate their own wakeup requests;
+- * they only forward requests from the root hub. Therefore
+- * controllers should always be enabled for remote wakeup.
+- */
+- device_wakeup_enable(hcd->self.controller);
+ return retval;
+
+ error_create_attr_group:
+diff -Nur linux-3.10.30.orig/drivers/usb/core/hub.c linux-linaro-stable-mx6/drivers/usb/core/hub.c
+--- linux-3.10.30.orig/drivers/usb/core/hub.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/core/hub.c 2014-05-15 20:34:08.234087614 +0200
+@@ -4372,8 +4372,7 @@
+
+ /* Disconnect any existing devices under this port */
+ if (udev) {
+- if (hcd->phy && !hdev->parent &&
+- !(portstatus & USB_PORT_STAT_CONNECTION))
++ if (hcd->phy && !hdev->parent)
+ usb_phy_notify_disconnect(hcd->phy, udev->speed);
+ usb_disconnect(&hub->ports[port1 - 1]->child);
+ }
+diff -Nur linux-3.10.30.orig/drivers/usb/gadget/f_mass_storage.c linux-linaro-stable-mx6/drivers/usb/gadget/f_mass_storage.c
+--- linux-3.10.30.orig/drivers/usb/gadget/f_mass_storage.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/gadget/f_mass_storage.c 2014-05-15 20:34:08.306088134 +0200
+@@ -349,8 +349,15 @@
+
+ struct usb_ep *bulk_in;
+ struct usb_ep *bulk_out;
++#ifdef CONFIG_FSL_UTP
++ void *utp;
++#endif
+ };
+
++#ifdef CONFIG_FSL_UTP
++#include "fsl_updater.h"
++#endif
++
+ static inline int __fsg_is_set(struct fsg_common *common,
+ const char *func, unsigned line)
+ {
+@@ -1143,6 +1150,13 @@
+ }
+ #endif
+
++#ifdef CONFIG_FSL_UTP
++ if (utp_get_sense(common->fsg) == 0) { /* got the sense from the UTP */
++ sd = UTP_CTX(common->fsg)->sd;
++ sdinfo = UTP_CTX(common->fsg)->sdinfo;
++ valid = 0;
++ } else
++#endif
+ if (!curlun) { /* Unsupported LUNs are okay */
+ common->bad_lun_okay = 1;
+ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
+@@ -1164,6 +1178,9 @@
+ buf[7] = 18 - 8; /* Additional sense length */
+ buf[12] = ASC(sd);
+ buf[13] = ASCQ(sd);
++#ifdef CONFIG_FSL_UTP
++ put_unaligned_be32(UTP_CTX(common->fsg)->sdinfo_h, &buf[8]);
++#endif
+ return 18;
+ }
+
+@@ -1657,7 +1674,18 @@
+ sd = SS_INVALID_COMMAND;
+ } else if (sd != SS_NO_SENSE) {
+ DBG(common, "sending command-failure status\n");
++#ifdef CONFIG_FSL_UTP
++/*
++ * mfgtool host frequently reset bus during transfer
++ * - the response in csw to request sense will be 1 due to UTP change
++ * some storage information
++ * - host will reset the bus if response to request sense is 1
++ * - change the response to 0 if CONFIG_FSL_UTP is defined
++ */
++ status = US_BULK_STAT_OK;
++#else
+ status = US_BULK_STAT_FAIL;
++#endif
+ VDBG(common, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
+ " info x%x\n",
+ SK(sd), ASC(sd), ASCQ(sd), sdinfo);
+@@ -1848,6 +1876,13 @@
+ common->phase_error = 0;
+ common->short_packet_received = 0;
+
++#ifdef CONFIG_FSL_UTP
++ reply = utp_handle_message(common->fsg, common->cmnd, reply);
++
++ if (reply != -EINVAL)
++ return reply;
++#endif
++
+ down_read(&common->filesem); /* We're using the backing file */
+ switch (common->cmnd[0]) {
+
+@@ -2507,12 +2542,14 @@
+ /* Allow the thread to be frozen */
+ set_freezable();
+
++#ifndef CONFIG_FSL_UTP
+ /*
+ * Arrange for userspace references to be interpreted as kernel
+ * pointers. That way we can pass a kernel pointer to a routine
+ * that expects a __user pointer and it will work okay.
+ */
+ set_fs(get_ds());
++#endif
+
+ /* The main loop */
+ while (common->state != FSG_STATE_TERMINATED) {
+@@ -2877,8 +2914,15 @@
+ fsg_common_put(common);
+ usb_free_all_descriptors(&fsg->function);
+ kfree(fsg);
++#ifdef CONFIG_FSL_UTP
++ utp_exit(fsg);
++#endif
+ }
+
++#ifdef CONFIG_FSL_UTP
++#include "fsl_updater.c"
++#endif
++
+ static int fsg_bind(struct usb_configuration *c, struct usb_function *f)
+ {
+ struct fsg_dev *fsg = fsg_from_func(f);
+@@ -2897,6 +2941,10 @@
+ fsg_intf_desc.bInterfaceNumber = i;
+ fsg->interface_number = i;
+
++#ifdef CONFIG_FSL_UTP
++ utp_init(fsg);
++#endif
++
+ /* Find all the endpoints we will use */
+ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
+ if (!ep)
+diff -Nur linux-3.10.30.orig/drivers/usb/gadget/fsl_updater.c linux-linaro-stable-mx6/drivers/usb/gadget/fsl_updater.c
+--- linux-3.10.30.orig/drivers/usb/gadget/fsl_updater.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/gadget/fsl_updater.c 2014-05-15 20:34:08.318088220 +0200
+@@ -0,0 +1,594 @@
++/*
++ * Freescale UUT driver
++ *
++ * Copyright 2008-2013 Freescale Semiconductor, Inc.
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++static u64 get_be64(u8 *buf)
++{
++ return ((u64)get_unaligned_be32(buf) << 32) |
++ get_unaligned_be32(buf + 4);
++}
++
++static int utp_init(struct fsg_dev *fsg)
++{
++ init_waitqueue_head(&utp_context.wq);
++ init_waitqueue_head(&utp_context.list_full_wq);
++
++ INIT_LIST_HEAD(&utp_context.read);
++ INIT_LIST_HEAD(&utp_context.write);
++ mutex_init(&utp_context.lock);
++
++ /* the max message is 64KB */
++ utp_context.buffer = vmalloc(0x10000);
++ if (!utp_context.buffer)
++ return -EIO;
++ utp_context.utp_version = 0x1ull;
++ fsg->utp = &utp_context;
++ return misc_register(&utp_dev);
++}
++
++static void utp_exit(struct fsg_dev *fsg)
++{
++ vfree(utp_context.buffer);
++ misc_deregister(&utp_dev);
++}
++
++static struct utp_user_data *utp_user_data_alloc(size_t size)
++{
++ struct utp_user_data *uud;
++
++ uud = vmalloc(size + sizeof(*uud));
++ if (!uud)
++ return uud;
++ memset(uud, 0, size + sizeof(*uud));
++ uud->data.size = size + sizeof(uud->data);
++ INIT_LIST_HEAD(&uud->link);
++ return uud;
++}
++
++static void utp_user_data_free(struct utp_user_data *uud)
++{
++ mutex_lock(&utp_context.lock);
++ list_del(&uud->link);
++ mutex_unlock(&utp_context.lock);
++ vfree(uud);
++}
++
++/* Get the number of element for list */
++static u32 count_list(struct list_head *l)
++{
++ u32 count = 0;
++ struct list_head *tmp;
++
++ mutex_lock(&utp_context.lock);
++ list_for_each(tmp, l) {
++ count++;
++ }
++ mutex_unlock(&utp_context.lock);
++
++ return count;
++}
++/* The routine will not go on if utp_context.queue is empty */
++#define WAIT_ACTIVITY(queue) \
++ wait_event_interruptible(utp_context.wq, !list_empty(&utp_context.queue))
++
++/* Called by userspace program (uuc) */
++static ssize_t utp_file_read(struct file *file,
++ char __user *buf,
++ size_t size,
++ loff_t *off)
++{
++ struct utp_user_data *uud;
++ size_t size_to_put;
++ int free = 0;
++
++ WAIT_ACTIVITY(read);
++
++ mutex_lock(&utp_context.lock);
++ uud = list_first_entry(&utp_context.read, struct utp_user_data, link);
++ mutex_unlock(&utp_context.lock);
++ size_to_put = uud->data.size;
++
++ if (size >= size_to_put)
++ free = !0;
++ if (copy_to_user(buf, &uud->data, size_to_put)) {
++ printk(KERN_INFO "[ %s ] copy error\n", __func__);
++ return -EACCES;
++ }
++ if (free)
++ utp_user_data_free(uud);
++ else {
++ pr_info("sizeof = %d, size = %d\n",
++ sizeof(uud->data),
++ uud->data.size);
++
++ pr_err("Will not free utp_user_data, because buffer size = %d,"
++ "need to put %d\n", size, size_to_put);
++ }
++
++ /*
++ * The user program has already finished data process,
++ * go on getting data from the host
++ */
++ wake_up(&utp_context.list_full_wq);
++
++ return size_to_put;
++}
++
++static ssize_t utp_file_write(struct file *file, const char __user *buf,
++ size_t size, loff_t *off)
++{
++ struct utp_user_data *uud;
++
++ if (size < sizeof(uud->data))
++ return -EINVAL;
++ uud = utp_user_data_alloc(size);
++ if (uud == NULL)
++ return -ENOMEM;
++ if (copy_from_user(&uud->data, buf, size)) {
++ printk(KERN_INFO "[ %s ] copy error!\n", __func__);
++ vfree(uud);
++ return -EACCES;
++ }
++ mutex_lock(&utp_context.lock);
++ list_add_tail(&uud->link, &utp_context.write);
++ /* Go on EXEC routine process */
++ wake_up(&utp_context.wq);
++ mutex_unlock(&utp_context.lock);
++ return size;
++}
++
++/*
++ * uuc should change to use soc bus infrastructure to soc information
++ * /sys/devices/soc0/soc_id
++ * this function can be removed.
++ */
++static long
++utp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ int cpu_id = 0;
++
++ switch (cmd) {
++ case UTP_GET_CPU_ID:
++ return put_user(cpu_id, (int __user *)arg);
++ default:
++ return -ENOIOCTLCMD;
++ }
++}
++
++/* Will be called when the host wants to get the sense data */
++static int utp_get_sense(struct fsg_dev *fsg)
++{
++ if (UTP_CTX(fsg)->processed == 0)
++ return -1;
++
++ UTP_CTX(fsg)->processed = 0;
++ return 0;
++}
++
++static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size)
++{
++ struct fsg_buffhd *bh;
++ int rc;
++ u32 amount_left;
++ unsigned int amount;
++
++ /* Get the starting Logical Block Address and check that it's
++ * not too big */
++
++ amount_left = size;
++ if (unlikely(amount_left == 0))
++ return -EIO; /* No default reply*/
++
++ pr_debug("%s: sending %d\n", __func__, size);
++ for (;;) {
++ /* Figure out how much we need to read:
++ * Try to read the remaining amount.
++ * But don't read more than the buffer size.
++ * And don't try to read past the end of the file.
++ * Finally, if we're not at a page boundary, don't read past
++ * the next page.
++ * If this means reading 0 then we were asked to read past
++ * the end of file. */
++ amount = min((unsigned int) amount_left, FSG_BUFLEN);
++
++ /* Wait for the next buffer to become available */
++ bh = fsg->common->next_buffhd_to_fill;
++ while (bh->state != BUF_STATE_EMPTY) {
++ rc = sleep_thread(fsg->common);
++ if (rc)
++ return rc;
++ }
++
++ /* If we were asked to read past the end of file,
++ * end with an empty buffer. */
++ if (amount == 0) {
++ bh->inreq->length = 0;
++ bh->state = BUF_STATE_FULL;
++ break;
++ }
++
++ /* Perform the read */
++ pr_info("Copied to %p, %d bytes started from %d\n",
++ bh->buf, amount, size - amount_left);
++ /* from upt buffer to file_storeage buffer */
++ memcpy(bh->buf, data + size - amount_left, amount);
++ amount_left -= amount;
++ fsg->common->residue -= amount;
++
++ bh->inreq->length = amount;
++ bh->state = BUF_STATE_FULL;
++
++ /* Send this buffer and go read some more */
++ bh->inreq->zero = 0;
++
++ /* USB Physical transfer: Data from device to host */
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++
++ fsg->common->next_buffhd_to_fill = bh->next;
++
++ if (amount_left <= 0)
++ break;
++ }
++
++ return size - amount_left;
++}
++
++static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size)
++{
++ struct fsg_buffhd *bh;
++ int get_some_more;
++ u32 amount_left_to_req, amount_left_to_write;
++ unsigned int amount;
++ int rc;
++ loff_t offset;
++
++ /* Carry out the file writes */
++ get_some_more = 1;
++ amount_left_to_req = amount_left_to_write = size;
++
++ if (unlikely(amount_left_to_write == 0))
++ return -EIO;
++
++ offset = 0;
++ while (amount_left_to_write > 0) {
++
++ /* Queue a request for more data from the host */
++ bh = fsg->common->next_buffhd_to_fill;
++ if (bh->state == BUF_STATE_EMPTY && get_some_more) {
++
++ /* Figure out how much we want to get:
++ * Try to get the remaining amount.
++ * But don't get more than the buffer size.
++ * And don't try to go past the end of the file.
++ * If we're not at a page boundary,
++ * don't go past the next page.
++ * If this means getting 0, then we were asked
++ * to write past the end of file.
++ * Finally, round down to a block boundary. */
++ amount = min(amount_left_to_req, FSG_BUFLEN);
++
++ if (amount == 0) {
++ get_some_more = 0;
++ /* cry now */
++ continue;
++ }
++
++ /* Get the next buffer */
++ amount_left_to_req -= amount;
++ if (amount_left_to_req == 0)
++ get_some_more = 0;
++
++ /* amount is always divisible by 512, hence by
++ * the bulk-out maxpacket size */
++ bh->outreq->length = bh->bulk_out_intended_length =
++ amount;
++ bh->outreq->short_not_ok = 1;
++ start_transfer(fsg, fsg->bulk_out, bh->outreq,
++ &bh->outreq_busy, &bh->state);
++ fsg->common->next_buffhd_to_fill = bh->next;
++ continue;
++ }
++
++ /* Write the received data to the backing file */
++ bh = fsg->common->next_buffhd_to_drain;
++ if (bh->state == BUF_STATE_EMPTY && !get_some_more)
++ break; /* We stopped early */
++ if (bh->state == BUF_STATE_FULL) {
++ smp_rmb();
++ fsg->common->next_buffhd_to_drain = bh->next;
++ bh->state = BUF_STATE_EMPTY;
++
++ /* Did something go wrong with the transfer? */
++ if (bh->outreq->status != 0)
++ /* cry again, COMMUNICATION_FAILURE */
++ break;
++
++ amount = bh->outreq->actual;
++
++ /* Perform the write */
++ memcpy(data + offset, bh->buf, amount);
++
++ offset += amount;
++ if (signal_pending(current))
++ return -EINTR; /* Interrupted!*/
++ amount_left_to_write -= amount;
++ fsg->common->residue -= amount;
++
++ /* Did the host decide to stop early? */
++ if (bh->outreq->actual != bh->outreq->length) {
++ fsg->common->short_packet_received = 1;
++ break;
++ }
++ continue;
++ }
++
++ /* Wait for something to happen */
++ rc = sleep_thread(fsg->common);
++ if (rc)
++ return rc;
++ }
++
++ return -EIO;
++}
++
++static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply)
++{
++ UTP_CTX(fsg)->processed = true;
++ UTP_CTX(fsg)->sdinfo = reply & 0xFFFFFFFF;
++ UTP_CTX(fsg)->sdinfo_h = (reply >> 32) & 0xFFFFFFFF;
++ UTP_CTX(fsg)->sd = (UTP_SENSE_KEY << 16) | code;
++}
++
++static void utp_poll(struct fsg_dev *fsg)
++{
++ struct utp_context *ctx = UTP_CTX(fsg);
++ struct utp_user_data *uud = NULL;
++
++ mutex_lock(&ctx->lock);
++ if (!list_empty(&ctx->write))
++ uud = list_first_entry(&ctx->write, struct utp_user_data, link);
++ mutex_unlock(&ctx->lock);
++
++ if (uud) {
++ if (uud->data.flags & UTP_FLAG_STATUS) {
++ printk(KERN_WARNING "%s: exit with status %d\n",
++ __func__, uud->data.status);
++ UTP_SS_EXIT(fsg, uud->data.status);
++ } else if (uud->data.flags & UTP_FLAG_REPORT_BUSY) {
++ UTP_SS_BUSY(fsg, --ctx->counter);
++ } else {
++ printk("%s: pass returned.\n", __func__);
++ UTP_SS_PASS(fsg);
++ }
++ utp_user_data_free(uud);
++ } else {
++ if (utp_context.cur_state & UTP_FLAG_DATA) {
++ if (count_list(&ctx->read) < 7) {
++ pr_debug("%s: pass returned in POLL stage. \n", __func__);
++ UTP_SS_PASS(fsg);
++ utp_context.cur_state = 0;
++ return;
++ }
++ }
++ UTP_SS_BUSY(fsg, --ctx->counter);
++ }
++}
++
++static int utp_exec(struct fsg_dev *fsg,
++ char *command,
++ int cmdsize,
++ unsigned long long payload)
++{
++ struct utp_user_data *uud = NULL, *uud2r;
++ struct utp_context *ctx = UTP_CTX(fsg);
++
++ ctx->counter = 0xFFFF;
++ uud2r = utp_user_data_alloc(cmdsize + 1);
++ if (!uud2r)
++ return -ENOMEM;
++ uud2r->data.flags = UTP_FLAG_COMMAND;
++ uud2r->data.payload = payload;
++ strncpy(uud2r->data.command, command, cmdsize);
++
++ mutex_lock(&ctx->lock);
++ list_add_tail(&uud2r->link, &ctx->read);
++ mutex_unlock(&ctx->lock);
++ /* wake up the read routine */
++ wake_up(&ctx->wq);
++
++ if (command[0] == '!') /* there will be no response */
++ return 0;
++
++ /*
++ * the user program (uuc) will return utp_message
++ * and add list to write list
++ */
++ WAIT_ACTIVITY(write);
++
++ mutex_lock(&ctx->lock);
++ if (!list_empty(&ctx->write)) {
++ uud = list_first_entry(&ctx->write, struct utp_user_data, link);
++#ifdef DEBUG
++ pr_info("UUD:\n\tFlags = %02X\n", uud->data.flags);
++ if (uud->data.flags & UTP_FLAG_DATA) {
++ pr_info("\tbufsize = %d\n", uud->data.bufsize);
++ print_hex_dump(KERN_DEBUG, "\t", DUMP_PREFIX_NONE,
++ 16, 2, uud->data.data, uud->data.bufsize, true);
++ }
++ if (uud->data.flags & UTP_FLAG_REPORT_BUSY)
++ pr_info("\tBUSY\n");
++#endif
++ }
++ mutex_unlock(&ctx->lock);
++
++ if (uud->data.flags & UTP_FLAG_DATA) {
++ memcpy(ctx->buffer, uud->data.data, uud->data.bufsize);
++ UTP_SS_SIZE(fsg, uud->data.bufsize);
++ } else if (uud->data.flags & UTP_FLAG_REPORT_BUSY) {
++ UTP_SS_BUSY(fsg, ctx->counter);
++ } else if (uud->data.flags & UTP_FLAG_STATUS) {
++ printk(KERN_WARNING "%s: exit with status %d\n", __func__,
++ uud->data.status);
++ UTP_SS_EXIT(fsg, uud->data.status);
++ } else {
++ pr_debug("%s: pass returned in EXEC stage. \n", __func__);
++ UTP_SS_PASS(fsg);
++ }
++ utp_user_data_free(uud);
++ return 0;
++}
++
++static int utp_send_status(struct fsg_dev *fsg)
++{
++ struct fsg_buffhd *bh;
++ u8 status = US_BULK_STAT_OK;
++ struct bulk_cs_wrap *csw;
++ int rc;
++
++ /* Wait for the next buffer to become available */
++ bh = fsg->common->next_buffhd_to_fill;
++ while (bh->state != BUF_STATE_EMPTY) {
++ rc = sleep_thread(fsg->common);
++ if (rc)
++ return rc;
++ }
++
++ if (fsg->common->phase_error) {
++ DBG(fsg, "sending phase-error status\n");
++ status = US_BULK_STAT_PHASE;
++
++ } else if ((UTP_CTX(fsg)->sd & 0xFFFF) != UTP_REPLY_PASS) {
++ status = US_BULK_STAT_FAIL;
++ }
++
++ csw = bh->buf;
++
++ /* Store and send the Bulk-only CSW */
++ csw->Signature = __constant_cpu_to_le32(US_BULK_CS_SIGN);
++ csw->Tag = fsg->common->tag;
++ csw->Residue = cpu_to_le32(fsg->common->residue);
++ csw->Status = status;
++
++ bh->inreq->length = US_BULK_CS_WRAP_LEN;
++ bh->inreq->zero = 0;
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++ fsg->common->next_buffhd_to_fill = bh->next;
++ return 0;
++}
++
++static int utp_handle_message(struct fsg_dev *fsg,
++ char *cdb_data,
++ int default_reply)
++{
++ struct utp_msg *m = (struct utp_msg *)cdb_data;
++ void *data = NULL;
++ int r;
++ struct utp_user_data *uud2r;
++ unsigned long long param;
++ unsigned long tag;
++
++ if (m->f0 != 0xF0)
++ return default_reply;
++
++ tag = get_unaligned_be32((void *)&m->utp_msg_tag);
++ param = get_be64((void *)&m->param);
++ pr_debug("Type 0x%x, tag 0x%08lx, param %llx\n",
++ m->utp_msg_type, tag, param);
++
++ switch ((enum utp_msg_type)m->utp_msg_type) {
++
++ case UTP_POLL:
++ if (get_be64((void *)&m->param) == 1) {
++ pr_debug("%s: version request\n", __func__);
++ UTP_SS_EXIT(fsg, UTP_CTX(fsg)->utp_version);
++ break;
++ }
++ utp_poll(fsg);
++ break;
++ case UTP_EXEC:
++ pr_debug("%s: EXEC\n", __func__);
++ data = vmalloc(fsg->common->data_size);
++ memset(data, 0, fsg->common->data_size);
++ /* copy data from usb buffer to utp buffer */
++ utp_do_write(fsg, data, fsg->common->data_size);
++ utp_exec(fsg, data, fsg->common->data_size, param);
++ vfree(data);
++ break;
++ case UTP_GET: /* data from device to host */
++ pr_debug("%s: GET, %d bytes\n", __func__,
++ fsg->common->data_size);
++ r = utp_do_read(fsg, UTP_CTX(fsg)->buffer,
++ fsg->common->data_size);
++ UTP_SS_PASS(fsg);
++ break;
++ case UTP_PUT:
++ utp_context.cur_state = UTP_FLAG_DATA;
++ pr_debug("%s: PUT, Received %d bytes\n", __func__, fsg->common->data_size);/* data from host to device */
++ uud2r = utp_user_data_alloc(fsg->common->data_size);
++ if (!uud2r)
++ return -ENOMEM;
++ uud2r->data.bufsize = fsg->common->data_size;
++ uud2r->data.flags = UTP_FLAG_DATA;
++ utp_do_write(fsg, uud2r->data.data, fsg->common->data_size);
++ /* don't know what will be written */
++ mutex_lock(&UTP_CTX(fsg)->lock);
++ list_add_tail(&uud2r->link, &UTP_CTX(fsg)->read);
++ mutex_unlock(&UTP_CTX(fsg)->lock);
++ wake_up(&UTP_CTX(fsg)->wq);
++ /*
++ * Return PASS or FAIL according to uuc's status
++ * Please open it if need to check uuc's status
++ * and use another version uuc
++ */
++#if 0
++ struct utp_user_data *uud = NULL;
++ struct utp_context *ctx;
++ WAIT_ACTIVITY(write);
++ ctx = UTP_CTX(fsg);
++ mutex_lock(&ctx->lock);
++
++ if (!list_empty(&ctx->write))
++ uud = list_first_entry(&ctx->write,
++ struct utp_user_data, link);
++
++ mutex_unlock(&ctx->lock);
++ if (uud) {
++ if (uud->data.flags & UTP_FLAG_STATUS) {
++ printk(KERN_WARNING "%s: exit with status %d\n",
++ __func__, uud->data.status);
++ UTP_SS_EXIT(fsg, uud->data.status);
++ } else {
++ pr_debug("%s: pass\n", __func__);
++ UTP_SS_PASS(fsg);
++ }
++ utp_user_data_free(uud);
++ } else{
++ UTP_SS_PASS(fsg);
++ }
++#endif
++ if (count_list(&UTP_CTX(fsg)->read) < 7) {
++ utp_context.cur_state = 0;
++ UTP_SS_PASS(fsg);
++ } else
++ UTP_SS_BUSY(fsg, UTP_CTX(fsg)->counter);
++
++ break;
++ }
++
++ utp_send_status(fsg);
++ return -1;
++}
+diff -Nur linux-3.10.30.orig/drivers/usb/gadget/fsl_updater.h linux-linaro-stable-mx6/drivers/usb/gadget/fsl_updater.h
+--- linux-3.10.30.orig/drivers/usb/gadget/fsl_updater.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/gadget/fsl_updater.h 2014-05-15 20:34:08.330088306 +0200
+@@ -0,0 +1,150 @@
++/*
++ * Freescale UUT driver
++ *
++ * Copyright 2008-2013 Freescale Semiconductor, Inc.
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef __FSL_UPDATER_H
++#define __FSL_UPDATER_H
++
++#include <linux/miscdevice.h>
++#include <linux/list.h>
++#include <linux/vmalloc.h>
++#include <linux/ioctl.h>
++/* #include <mach/hardware.h> */
++
++static int utp_init(struct fsg_dev *fsg);
++static void utp_exit(struct fsg_dev *fsg);
++static ssize_t utp_file_read(struct file *file,
++ char __user *buf,
++ size_t size,
++ loff_t *off);
++
++static ssize_t utp_file_write(struct file *file,
++ const char __user *buf,
++ size_t size,
++ loff_t *off);
++
++static long utp_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg);
++static struct utp_user_data *utp_user_data_alloc(size_t size);
++static void utp_user_data_free(struct utp_user_data *uud);
++static int utp_get_sense(struct fsg_dev *fsg);
++static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size);
++static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size);
++static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply);
++static int utp_handle_message(struct fsg_dev *fsg,
++ char *cdb_data,
++ int default_reply);
++
++#define UTP_REPLY_PASS 0
++#define UTP_REPLY_EXIT 0x8001
++#define UTP_REPLY_BUSY 0x8002
++#define UTP_REPLY_SIZE 0x8003
++#define UTP_SENSE_KEY 9
++
++#define UTP_MINOR 222
++/* MISC_DYNAMIC_MINOR would be better, but... */
++
++#define UTP_COMMAND_SIZE 80
++
++#define UTP_SS_EXIT(fsg, r) utp_set_sense(fsg, UTP_REPLY_EXIT, (u64)r)
++#define UTP_SS_PASS(fsg) utp_set_sense(fsg, UTP_REPLY_PASS, 0)
++#define UTP_SS_BUSY(fsg, r) utp_set_sense(fsg, UTP_REPLY_BUSY, (u64)r)
++#define UTP_SS_SIZE(fsg, r) utp_set_sense(fsg, UTP_REPLY_SIZE, (u64)r)
++
++#define UTP_IOCTL_BASE 'U'
++#define UTP_GET_CPU_ID _IOR(UTP_IOCTL_BASE, 0, int)
++/* the structure of utp message which is mapped to 16-byte SCSI CBW's CDB */
++#pragma pack(1)
++struct utp_msg {
++ u8 f0;
++ u8 utp_msg_type;
++ u32 utp_msg_tag;
++ union {
++ struct {
++ u32 param_lsb;
++ u32 param_msb;
++ };
++ u64 param;
++ };
++};
++
++enum utp_msg_type {
++ UTP_POLL = 0,
++ UTP_EXEC,
++ UTP_GET,
++ UTP_PUT,
++};
++
++static struct utp_context {
++ wait_queue_head_t wq;
++ wait_queue_head_t list_full_wq;
++ struct mutex lock;
++ struct list_head read;
++ struct list_head write;
++ u32 sd, sdinfo, sdinfo_h; /* sense data */
++ int processed;
++ u8 *buffer;
++ u32 counter;
++ u64 utp_version;
++ u32 cur_state;
++} utp_context;
++
++static const struct file_operations utp_fops = {
++ .open = nonseekable_open,
++ .read = utp_file_read,
++ .write = utp_file_write,
++ /* .ioctl = utp_ioctl, */
++ .unlocked_ioctl = utp_ioctl,
++};
++
++static struct miscdevice utp_dev = {
++ .minor = UTP_MINOR,
++ .name = "utp",
++ .fops = &utp_fops,
++};
++
++#define UTP_FLAG_COMMAND 0x00000001
++#define UTP_FLAG_DATA 0x00000002
++#define UTP_FLAG_STATUS 0x00000004
++#define UTP_FLAG_REPORT_BUSY 0x10000000
++struct utp_message {
++ u32 flags;
++ size_t size;
++ union {
++ struct {
++ u64 payload;
++ char command[1];
++ };
++ struct {
++ size_t bufsize;
++ u8 data[1];
++ };
++ u32 status;
++ };
++};
++
++struct utp_user_data {
++ struct list_head link;
++ struct utp_message data;
++};
++#pragma pack()
++
++static inline struct utp_context *UTP_CTX(struct fsg_dev *fsg)
++{
++ return (struct utp_context *)fsg->utp;
++}
++
++#endif /* __FSL_UPDATER_H */
++
+diff -Nur linux-3.10.30.orig/drivers/usb/gadget/Kconfig linux-linaro-stable-mx6/drivers/usb/gadget/Kconfig
+--- linux-3.10.30.orig/drivers/usb/gadget/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/gadget/Kconfig 2014-05-15 20:34:08.242087673 +0200
+@@ -751,6 +751,12 @@
+ Say "y" to link the driver statically, or "m" to build
+ a dynamically linked module called "g_mass_storage".
+
++config FSL_UTP
++ bool "UTP over Storage Gadget"
++ depends on USB_MASS_STORAGE
++ help
++ Freescale's extension to MSC protocol
++
+ config USB_GADGET_TARGET
+ tristate "USB Gadget Target Fabric Module"
+ depends on TARGET_CORE
+diff -Nur linux-3.10.30.orig/drivers/usb/gadget/mass_storage.c linux-linaro-stable-mx6/drivers/usb/gadget/mass_storage.c
+--- linux-3.10.30.orig/drivers/usb/gadget/mass_storage.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/gadget/mass_storage.c 2014-05-15 20:34:08.366088565 +0200
+@@ -189,7 +189,7 @@
+ {
+ return usb_composite_probe(&msg_driver);
+ }
+-module_init(msg_init);
++late_initcall(msg_init);
+
+ static void msg_cleanup(void)
+ {
+diff -Nur linux-3.10.30.orig/drivers/usb/gadget/zero.c linux-linaro-stable-mx6/drivers/usb/gadget/zero.c
+--- linux-3.10.30.orig/drivers/usb/gadget/zero.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/gadget/zero.c 2014-05-15 20:34:08.502089546 +0200
+@@ -95,6 +95,18 @@
+ module_param(autoresume, uint, S_IRUGO);
+ MODULE_PARM_DESC(autoresume, "zero, or seconds before remote wakeup");
+
++/* Maximum Autoresume time */
++unsigned max_autoresume;
++module_param(max_autoresume, uint, S_IRUGO);
++MODULE_PARM_DESC(max_autoresume, "maximum seconds before remote wakeup");
++
++/* Interval between two remote wakeups */
++unsigned autoresume_interval_ms;
++module_param(autoresume_interval_ms, uint, S_IRUGO);
++MODULE_PARM_DESC(autoresume_interval_ms,
++ "milliseconds to increase successive wakeup delays");
++
++static unsigned autoresume_step_ms;
+ /*-------------------------------------------------------------------------*/
+
+ static struct usb_device_descriptor device_desc = {
+@@ -183,8 +195,16 @@
+ return;
+
+ if (autoresume) {
+- mod_timer(&autoresume_timer, jiffies + (HZ * autoresume));
+- DBG(cdev, "suspend, wakeup in %d seconds\n", autoresume);
++ if (max_autoresume &&
++ (autoresume_step_ms > max_autoresume * 1000))
++ autoresume_step_ms = autoresume * 1000;
++
++ mod_timer(&autoresume_timer, jiffies +
++ msecs_to_jiffies(autoresume_step_ms));
++ DBG(cdev, "suspend, wakeup in %d milliseconds\n",
++ autoresume_step_ms);
++
++ autoresume_step_ms += autoresume_interval_ms;
+ } else
+ DBG(cdev, "%s\n", __func__);
+ }
+@@ -316,6 +336,7 @@
+ if (autoresume) {
+ sourcesink_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
+ loopback_driver.bmAttributes |= USB_CONFIG_ATT_WAKEUP;
++ autoresume_step_ms = autoresume * 1000;
+ }
+
+ /* support OTG systems */
+diff -Nur linux-3.10.30.orig/drivers/usb/host/ehci.h linux-linaro-stable-mx6/drivers/usb/host/ehci.h
+--- linux-3.10.30.orig/drivers/usb/host/ehci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/host/ehci.h 2014-05-15 20:34:08.542089834 +0200
+@@ -816,6 +816,8 @@
+ extern void ehci_init_driver(struct hc_driver *drv,
+ const struct ehci_driver_overrides *over);
+ extern int ehci_setup(struct usb_hcd *hcd);
++extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
++ u32 mask, u32 done, int usec);
+
+ #ifdef CONFIG_PM
+ extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
+diff -Nur linux-3.10.30.orig/drivers/usb/host/ehci-hcd.c linux-linaro-stable-mx6/drivers/usb/host/ehci-hcd.c
+--- linux-3.10.30.orig/drivers/usb/host/ehci-hcd.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/host/ehci-hcd.c 2014-05-15 20:34:08.534089775 +0200
+@@ -139,7 +139,7 @@
+ /*-------------------------------------------------------------------------*/
+
+ /*
+- * handshake - spin reading hc until handshake completes or fails
++ * ehci_handshake - spin reading hc until handshake completes or fails
+ * @ptr: address of hc register to be read
+ * @mask: bits to look at in result of read
+ * @done: value of those bits when handshake succeeds
+@@ -155,8 +155,8 @@
+ * before driver shutdown. But it also seems to be caused by bugs in cardbus
+ * bridge shutdown: shutting down the bridge before the devices using it.
+ */
+-static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
+- u32 mask, u32 done, int usec)
++int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
++ u32 mask, u32 done, int usec)
+ {
+ u32 result;
+
+@@ -172,6 +172,7 @@
+ } while (usec > 0);
+ return -ETIMEDOUT;
+ }
++EXPORT_SYMBOL_GPL(ehci_handshake);
+
+ /* check TDI/ARC silicon is in host mode */
+ static int tdi_in_host_mode (struct ehci_hcd *ehci)
+@@ -212,7 +213,7 @@
+ spin_unlock_irq(&ehci->lock);
+ synchronize_irq(ehci_to_hcd(ehci)->irq);
+
+- return handshake(ehci, &ehci->regs->status,
++ return ehci_handshake(ehci, &ehci->regs->status,
+ STS_HALT, STS_HALT, 16 * 125);
+ }
+
+@@ -251,7 +252,7 @@
+ ehci_writel(ehci, command, &ehci->regs->command);
+ ehci->rh_state = EHCI_RH_HALTED;
+ ehci->next_statechange = jiffies;
+- retval = handshake (ehci, &ehci->regs->command,
++ retval = ehci_handshake(ehci, &ehci->regs->command,
+ CMD_RESET, 0, 250 * 1000);
+
+ if (ehci->has_hostpc) {
+@@ -286,7 +287,8 @@
+
+ /* wait for any schedule enables/disables to take effect */
+ temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
+- handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp, 16 * 125);
++ ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp,
++ 16 * 125);
+
+ /* then disable anything that's still active */
+ spin_lock_irq(&ehci->lock);
+@@ -295,7 +297,8 @@
+ spin_unlock_irq(&ehci->lock);
+
+ /* hardware can take 16 microframes to turn off ... */
+- handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0, 16 * 125);
++ ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0,
++ 16 * 125);
+ }
+
+ /*-------------------------------------------------------------------------*/
+diff -Nur linux-3.10.30.orig/drivers/usb/host/ehci-hub.c linux-linaro-stable-mx6/drivers/usb/host/ehci-hub.c
+--- linux-3.10.30.orig/drivers/usb/host/ehci-hub.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/host/ehci-hub.c 2014-05-15 20:34:08.534089775 +0200
+@@ -877,7 +877,7 @@
+ PORT_SUSPEND | PORT_RESUME);
+ ehci_writel(ehci, temp, status_reg);
+ clear_bit(wIndex, &ehci->resuming_ports);
+- retval = handshake(ehci, status_reg,
++ retval = ehci_handshake(ehci, status_reg,
+ PORT_RESUME, 0, 2000 /* 2msec */);
+ if (retval != 0) {
+ ehci_err(ehci,
+@@ -903,7 +903,7 @@
+ /* REVISIT: some hardware needs 550+ usec to clear
+ * this bit; seems too long to spin routinely...
+ */
+- retval = handshake(ehci, status_reg,
++ retval = ehci_handshake(ehci, status_reg,
+ PORT_RESET, 0, 1000);
+ if (retval != 0) {
+ ehci_err (ehci, "port %d reset error %d\n",
+diff -Nur linux-3.10.30.orig/drivers/usb/host/ehci-tegra.c linux-linaro-stable-mx6/drivers/usb/host/ehci-tegra.c
+--- linux-3.10.30.orig/drivers/usb/host/ehci-tegra.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/host/ehci-tegra.c 2014-05-15 20:34:08.538089805 +0200
+@@ -179,7 +179,7 @@
+ * If a transaction is in progress, there may be a delay in
+ * suspending the port. Poll until the port is suspended.
+ */
+- if (handshake(ehci, status_reg, PORT_SUSPEND,
++ if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
+ PORT_SUSPEND, 5000))
+ pr_err("%s: timeout waiting for SUSPEND\n", __func__);
+
+@@ -227,9 +227,9 @@
+ spin_lock_irqsave(&ehci->lock, flags);
+
+ /* Poll until the controller clears RESUME and SUSPEND */
+- if (handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
++ if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
+ pr_err("%s: timeout waiting for RESUME\n", __func__);
+- if (handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
++ if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
+ pr_err("%s: timeout waiting for SUSPEND\n", __func__);
+
+ ehci->reset_done[wIndex-1] = 0;
+@@ -511,14 +511,14 @@
+ }
+
+ /* Poll until CCS is enabled */
+- if (handshake(ehci, &hw->port_status[0], PORT_CONNECT,
++ if (ehci_handshake(ehci, &hw->port_status[0], PORT_CONNECT,
+ PORT_CONNECT, 2000)) {
+ pr_err("%s: timeout waiting for PORT_CONNECT\n", __func__);
+ goto restart;
+ }
+
+ /* Poll until PE is enabled */
+- if (handshake(ehci, &hw->port_status[0], PORT_PE,
++ if (ehci_handshake(ehci, &hw->port_status[0], PORT_PE,
+ PORT_PE, 2000)) {
+ pr_err("%s: timeout waiting for USB_PORTSC1_PE\n", __func__);
+ goto restart;
+@@ -536,7 +536,7 @@
+ writel(val, &hw->port_status[0]);
+
+ /* Wait until port suspend completes */
+- if (handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
++ if (ehci_handshake(ehci, &hw->port_status[0], PORT_SUSPEND,
+ PORT_SUSPEND, 1000)) {
+ pr_err("%s: timeout waiting for PORT_SUSPEND\n",
+ __func__);
+diff -Nur linux-3.10.30.orig/drivers/usb/host/Kconfig linux-linaro-stable-mx6/drivers/usb/host/Kconfig
+--- linux-3.10.30.orig/drivers/usb/host/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/host/Kconfig 2014-05-15 20:34:08.502089546 +0200
+@@ -65,7 +65,7 @@
+
+ config USB_EHCI_ROOT_HUB_TT
+ bool "Root Hub Transaction Translators"
+- depends on USB_EHCI_HCD || USB_CHIPIDEA_HOST
++ depends on USB_EHCI_HCD
+ ---help---
+ Some EHCI chips have vendor-specific extensions to integrate
+ transaction translators, so that no OHCI or UHCI companion
+@@ -77,7 +77,7 @@
+
+ config USB_EHCI_TT_NEWSCHED
+ bool "Improved Transaction Translator scheduling"
+- depends on USB_EHCI_HCD || USB_CHIPIDEA_HOST
++ depends on USB_EHCI_HCD
+ default y
+ ---help---
+ This changes the periodic scheduling code to fill more of the low
+diff -Nur linux-3.10.30.orig/drivers/usb/phy/Makefile linux-linaro-stable-mx6/drivers/usb/phy/Makefile
+--- linux-3.10.30.orig/drivers/usb/phy/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/phy/Makefile 2014-05-15 20:34:08.902092426 +0200
+@@ -5,6 +5,7 @@
+ ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
+
+ obj-$(CONFIG_USB_PHY) += phy.o
++obj-$(CONFIG_OF) += of.o
+
+ # transceiver drivers, keep the list sorted
+
+diff -Nur linux-3.10.30.orig/drivers/usb/phy/of.c linux-linaro-stable-mx6/drivers/usb/phy/of.c
+--- linux-3.10.30.orig/drivers/usb/phy/of.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/phy/of.c 2014-05-15 20:34:08.902092426 +0200
+@@ -0,0 +1,47 @@
++/*
++ * USB of helper code
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/usb/of.h>
++#include <linux/usb/otg.h>
++
++static const char *const usbphy_modes[] = {
++ [USBPHY_INTERFACE_MODE_UNKNOWN] = "",
++ [USBPHY_INTERFACE_MODE_UTMI] = "utmi",
++ [USBPHY_INTERFACE_MODE_UTMIW] = "utmi_wide",
++ [USBPHY_INTERFACE_MODE_ULPI] = "ulpi",
++ [USBPHY_INTERFACE_MODE_SERIAL] = "serial",
++ [USBPHY_INTERFACE_MODE_HSIC] = "hsic",
++};
++
++/**
++ * of_usb_get_phy_mode - Get phy mode for given device_node
++ * @np: Pointer to the given device_node
++ *
++ * The function gets phy interface string from property 'phy_type',
++ * and returns the correspondig enum usb_phy_interface
++ */
++enum usb_phy_interface of_usb_get_phy_mode(struct device_node *np)
++{
++ const char *phy_type;
++ int err, i;
++
++ err = of_property_read_string(np, "phy_type", &phy_type);
++ if (err < 0)
++ return USBPHY_INTERFACE_MODE_UNKNOWN;
++
++ for (i = 0; i < ARRAY_SIZE(usbphy_modes); i++)
++ if (!strcmp(phy_type, usbphy_modes[i]))
++ return i;
++
++ return USBPHY_INTERFACE_MODE_UNKNOWN;
++}
++EXPORT_SYMBOL_GPL(of_usb_get_phy_mode);
+diff -Nur linux-3.10.30.orig/drivers/usb/phy/phy-mxs-usb.c linux-linaro-stable-mx6/drivers/usb/phy/phy-mxs-usb.c
+--- linux-3.10.30.orig/drivers/usb/phy/phy-mxs-usb.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/phy/phy-mxs-usb.c 2014-05-15 20:34:08.902092426 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+@@ -20,6 +20,9 @@
+ #include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
+
+ #define DRIVER_NAME "mxs_phy"
+
+@@ -28,42 +31,267 @@
+ #define HW_USBPHY_CTRL_SET 0x34
+ #define HW_USBPHY_CTRL_CLR 0x38
+
++#define HW_USBPHY_DEBUG_SET 0x54
++#define HW_USBPHY_DEBUG_CLR 0x58
++
++#define HW_USBPHY_IP 0x90
++#define HW_USBPHY_IP_SET 0x94
++#define HW_USBPHY_IP_CLR 0x98
++
+ #define BM_USBPHY_CTRL_SFTRST BIT(31)
+ #define BM_USBPHY_CTRL_CLKGATE BIT(30)
++#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
++#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
++#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
++#define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
++#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
++#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
++#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
++#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18)
+ #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
+ #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
+ #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
+
++#define BM_USBPHY_IP_FIX (BIT(17) | BIT(18))
++
++#define BM_USBPHY_DEBUG_CLKGATE BIT(30)
++
++/* Anatop Registers */
++#define ANADIG_ANA_MISC0 0x150
++#define ANADIG_ANA_MISC0_SET 0x154
++#define ANADIG_ANA_MISC0_CLR 0x158
++
++#define ANADIG_USB1_VBUS_DET_STAT 0x1c0
++#define ANADIG_USB2_VBUS_DET_STAT 0x220
++
++#define ANADIG_USB1_LOOPBACK_SET 0x1e4
++#define ANADIG_USB1_LOOPBACK_CLR 0x1e8
++#define ANADIG_USB2_LOOPBACK_SET 0x244
++#define ANADIG_USB2_LOOPBACK_CLR 0x248
++
++#define ANADIG_USB1_MISC 0x1f0
++#define ANADIG_USB2_MISC 0x250
++
++#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12)
++#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
++
++#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
++#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
++
++#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2)
++#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5)
++#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2)
++#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5)
++
++#define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29)
++#define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28)
++#define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29)
++#define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28)
++
++#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
++
++/* Do disconnection between PHY and controller without vbus */
++#define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0)
++
++/*
++ * The PHY will be in messy if there is an wakeup after putting
++ * bus to suspend (set portsc.suspendM) but before setting PHY to low
++ * power mode (set portsc.phcd).
++ */
++#define MXS_PHY_ABNORAML_IN_SUSPEND BIT(1)
++
++/*
++ * The SOF sends too fast after resuming, it will cause disconnection
++ * between host and high speed device.
++ */
++#define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2)
++
++/* The SoCs who have anatop module */
++#define MXS_PHY_HAS_ANATOP BIT(3)
++
++struct mxs_phy_data {
++ unsigned int flags;
++};
++
++static const struct mxs_phy_data imx23_phy_data = {
++ .flags = MXS_PHY_ABNORAML_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
++};
++
++static const struct mxs_phy_data imx6q_phy_data = {
++ .flags = MXS_PHY_SENDING_SOF_TOO_FAST |
++ MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
++ MXS_PHY_HAS_ANATOP,
++};
++
++static const struct mxs_phy_data imx6sl_phy_data = {
++ .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
++ MXS_PHY_HAS_ANATOP,
++};
++
++static const struct of_device_id mxs_phy_dt_ids[] = {
++ { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
++ { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
++ { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
++
+ struct mxs_phy {
+ struct usb_phy phy;
+ struct clk *clk;
++ const struct mxs_phy_data *data;
++ struct regmap *regmap_anatop;
++ int port_id;
+ };
+
+-#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
++static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
++{
++ return mxs_phy->data == &imx6q_phy_data;
++}
+
+-static void mxs_phy_hw_init(struct mxs_phy *mxs_phy)
++static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
++{
++ return mxs_phy->data == &imx6sl_phy_data;
++}
++
++/*
++ * PHY needs some 32K cycles to switch from 32K clock to
++ * bus (such as AHB/AXI, etc) clock.
++ */
++static void mxs_phy_clock_switch(void)
+ {
++ usleep_range(300, 400);
++}
++
++static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
++{
++ int ret;
+ void __iomem *base = mxs_phy->phy.io_priv;
+
+- stmp_reset_block(base + HW_USBPHY_CTRL);
++ ret = stmp_reset_block(base + HW_USBPHY_CTRL);
++ if (ret)
++ return ret;
+
+ /* Power up the PHY */
+ writel(0, base + HW_USBPHY_PWD);
+
+- /* enable FS/LS device */
+- writel(BM_USBPHY_CTRL_ENUTMILEVEL2 |
+- BM_USBPHY_CTRL_ENUTMILEVEL3,
++ /*
++ * USB PHY Ctrl Setting
++ * - Auto clock/power on
++ * - Enable full/low speed support
++ */
++ writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
++ BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
++ BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
++ BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
++ BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
++ BM_USBPHY_CTRL_ENUTMILEVEL2 |
++ BM_USBPHY_CTRL_ENUTMILEVEL3,
+ base + HW_USBPHY_CTRL_SET);
++
++ /* Enable IC solution */
++ if (is_imx6q_phy(mxs_phy) || is_imx6sl_phy(mxs_phy))
++ writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
++
++ return 0;
++}
++
++/* Return true if the vbus is there */
++static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
++{
++ unsigned int vbus_value;
++
++ if (mxs_phy->port_id == 0)
++ regmap_read(mxs_phy->regmap_anatop,
++ ANADIG_USB1_VBUS_DET_STAT,
++ &vbus_value);
++ else if (mxs_phy->port_id == 1)
++ regmap_read(mxs_phy->regmap_anatop,
++ ANADIG_USB2_VBUS_DET_STAT,
++ &vbus_value);
++
++ if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
++ return true;
++ else
++ return false;
++}
++
++static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
++{
++ void __iomem *base = mxs_phy->phy.io_priv;
++ u32 reg;
++
++ if (disconnect)
++ writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
++ base + HW_USBPHY_DEBUG_CLR);
++
++ if (mxs_phy->port_id == 0) {
++ reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
++ : ANADIG_USB1_LOOPBACK_CLR;
++ regmap_write(mxs_phy->regmap_anatop, reg,
++ BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
++ BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
++ } else if (mxs_phy->port_id == 1) {
++ reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
++ : ANADIG_USB2_LOOPBACK_CLR;
++ regmap_write(mxs_phy->regmap_anatop, reg,
++ BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 |
++ BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
++ }
++
++ if (!disconnect)
++ writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
++ base + HW_USBPHY_DEBUG_SET);
++
++ /* Delay some time, and let Linestate be SE0 for controller */
++ if (disconnect)
++ usleep_range(500, 1000);
++}
++
++static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
++{
++ bool vbus_is_on = false;
++
++ /* If the SoCs don't need to disconnect line without vbus, quit */
++ if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
++ return;
++
++ /* If the SoCs don't have anatop, quit */
++ if (!mxs_phy->regmap_anatop)
++ return;
++
++ vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
++
++ if (on && !vbus_is_on)
++ __mxs_phy_disconnect_line(mxs_phy, true);
++ else
++ __mxs_phy_disconnect_line(mxs_phy, false);
++
++}
++
++static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
++{
++ unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR;
++
++ /* If the SoCs don't have anatop, quit */
++ if (!mxs_phy->regmap_anatop)
++ return;
++
++ if (is_imx6q_phy(mxs_phy))
++ regmap_write(mxs_phy->regmap_anatop, reg,
++ BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG);
++ else if (is_imx6sl_phy(mxs_phy))
++ regmap_write(mxs_phy->regmap_anatop,
++ reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL);
+ }
+
+ static int mxs_phy_init(struct usb_phy *phy)
+ {
+ struct mxs_phy *mxs_phy = to_mxs_phy(phy);
+
++ mxs_phy_clock_switch();
+ clk_prepare_enable(mxs_phy->clk);
+- mxs_phy_hw_init(mxs_phy);
+-
+- return 0;
++ return mxs_phy_hw_init(mxs_phy);
+ }
+
+ static void mxs_phy_shutdown(struct usb_phy *phy)
+@@ -76,16 +304,60 @@
+ clk_disable_unprepare(mxs_phy->clk);
+ }
+
++static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy)
++{
++ unsigned int line_state;
++ /* bit definition is the same for all controllers */
++ unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS,
++ dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS;
++ unsigned int reg = ANADIG_USB1_MISC;
++
++ /* If the SoCs don't have anatop, quit */
++ if (!mxs_phy->regmap_anatop)
++ return false;
++
++ if (mxs_phy->port_id == 0)
++ reg = ANADIG_USB1_MISC;
++ else if (mxs_phy->port_id == 1)
++ reg = ANADIG_USB2_MISC;
++
++ regmap_read(mxs_phy->regmap_anatop, reg, &line_state);
++
++ if ((line_state & (dp_bit | dm_bit)) == dm_bit)
++ return true;
++ else
++ return false;
++}
++
+ static int mxs_phy_suspend(struct usb_phy *x, int suspend)
+ {
+ struct mxs_phy *mxs_phy = to_mxs_phy(x);
++ bool low_speed_connection, vbus_is_on;
++
++ low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy);
++ vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
+
+ if (suspend) {
+- writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
++ /*
++ * FIXME: Do not power down RXPWD1PT1 bit for low speed
++ * connect. The low speed connection will have problem at
++ * very rare cases during usb suspend and resume process.
++ */
++ if (low_speed_connection & vbus_is_on) {
++ /*
++ * If value to be set as pwd value is not 0xffffffff,
++ * several 32Khz cycles are needed.
++ */
++ mxs_phy_clock_switch();
++ writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
++ } else {
++ writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
++ }
+ writel(BM_USBPHY_CTRL_CLKGATE,
+ x->io_priv + HW_USBPHY_CTRL_SET);
+ clk_disable_unprepare(mxs_phy->clk);
+ } else {
++ mxs_phy_clock_switch();
+ clk_prepare_enable(mxs_phy->clk);
+ writel(BM_USBPHY_CTRL_CLKGATE,
+ x->io_priv + HW_USBPHY_CTRL_CLR);
+@@ -95,11 +367,28 @@
+ return 0;
+ }
+
++static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled)
++{
++ struct mxs_phy *mxs_phy = to_mxs_phy(x);
++ u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
++ BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
++ BM_USBPHY_CTRL_ENIDCHG_WKUP;
++ if (enabled) {
++ mxs_phy_disconnect_line(mxs_phy, true);
++ writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
++ } else {
++ writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
++ mxs_phy_disconnect_line(mxs_phy, false);
++ }
++
++ return 0;
++}
++
+ static int mxs_phy_on_connect(struct usb_phy *phy,
+ enum usb_device_speed speed)
+ {
+- dev_dbg(phy->dev, "%s speed device has connected\n",
+- (speed == USB_SPEED_HIGH) ? "high" : "non-high");
++ dev_dbg(phy->dev, "%s device has connected\n",
++ (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
+
+ if (speed == USB_SPEED_HIGH)
+ writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
+@@ -111,8 +400,8 @@
+ static int mxs_phy_on_disconnect(struct usb_phy *phy,
+ enum usb_device_speed speed)
+ {
+- dev_dbg(phy->dev, "%s speed device has disconnected\n",
+- (speed == USB_SPEED_HIGH) ? "high" : "non-high");
++ dev_dbg(phy->dev, "%s device has disconnected\n",
++ (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
+
+ if (speed == USB_SPEED_HIGH)
+ writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
+@@ -121,6 +410,48 @@
+ return 0;
+ }
+
++static int mxs_phy_on_suspend(struct usb_phy *phy,
++ enum usb_device_speed speed)
++{
++ struct mxs_phy *mxs_phy = to_mxs_phy(phy);
++
++ dev_dbg(phy->dev, "%s device has suspended\n",
++ (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
++
++ /* delay 4ms to wait bus entering idle */
++ usleep_range(4000, 5000);
++
++ if (mxs_phy->data->flags & MXS_PHY_ABNORAML_IN_SUSPEND) {
++ writel_relaxed(0xffffffff, phy->io_priv + HW_USBPHY_PWD);
++ writel_relaxed(0, phy->io_priv + HW_USBPHY_PWD);
++ }
++
++ if (speed == USB_SPEED_HIGH)
++ writel_relaxed(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
++ phy->io_priv + HW_USBPHY_CTRL_CLR);
++
++ return 0;
++}
++
++/*
++ * The resume signal must be finished here.
++ */
++static int mxs_phy_on_resume(struct usb_phy *phy,
++ enum usb_device_speed speed)
++{
++ dev_dbg(phy->dev, "%s device has resumed\n",
++ (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
++
++ if (speed == USB_SPEED_HIGH) {
++ /* Make sure the device has switched to High-Speed mode */
++ udelay(500);
++ writel_relaxed(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
++ phy->io_priv + HW_USBPHY_CTRL_SET);
++ }
++
++ return 0;
++}
++
+ static int mxs_phy_probe(struct platform_device *pdev)
+ {
+ struct resource *res;
+@@ -128,6 +459,9 @@
+ struct clk *clk;
+ struct mxs_phy *mxs_phy;
+ int ret;
++ const struct of_device_id *of_id =
++ of_match_device(mxs_phy_dt_ids, &pdev->dev);
++ struct device_node *np = pdev->dev.of_node;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+@@ -147,6 +481,13 @@
+ return -ENOMEM;
+ }
+
++ ret = of_alias_get_id(np, "usbphy");
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
++ return ret;
++ }
++ mxs_phy->port_id = ret;
++
+ mxs_phy->phy.io_priv = base;
+ mxs_phy->phy.dev = &pdev->dev;
+ mxs_phy->phy.label = DRIVER_NAME;
+@@ -156,12 +497,31 @@
+ mxs_phy->phy.notify_connect = mxs_phy_on_connect;
+ mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect;
+ mxs_phy->phy.type = USB_PHY_TYPE_USB2;
++ mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup;
+
+ ATOMIC_INIT_NOTIFIER_HEAD(&mxs_phy->phy.notifier);
+
+ mxs_phy->clk = clk;
++ mxs_phy->data = of_id->data;
++
++ if (mxs_phy->data->flags & MXS_PHY_SENDING_SOF_TOO_FAST) {
++ mxs_phy->phy.notify_suspend = mxs_phy_on_suspend;
++ mxs_phy->phy.notify_resume = mxs_phy_on_resume;
++ }
++
++ platform_set_drvdata(pdev, mxs_phy);
++
++ if (mxs_phy->data->flags & MXS_PHY_HAS_ANATOP) {
++ mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
++ (np, "fsl,anatop");
++ if (IS_ERR(mxs_phy->regmap_anatop)) {
++ dev_dbg(&pdev->dev,
++ "failed to find regmap for anatop\n");
++ return PTR_ERR(mxs_phy->regmap_anatop);
++ }
++ }
+
+- platform_set_drvdata(pdev, &mxs_phy->phy);
++ device_set_wakeup_capable(&pdev->dev, true);
+
+ ret = usb_add_phy_dev(&mxs_phy->phy);
+ if (ret)
+@@ -179,11 +539,27 @@
+ return 0;
+ }
+
+-static const struct of_device_id mxs_phy_dt_ids[] = {
+- { .compatible = "fsl,imx23-usbphy", },
+- { /* sentinel */ }
+-};
+-MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
++static int mxs_phy_system_suspend(struct device *dev)
++{
++ struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
++
++ if (device_may_wakeup(dev))
++ mxs_phy_enable_ldo_in_suspend(mxs_phy, true);
++
++ return 0;
++}
++
++static int mxs_phy_system_resume(struct device *dev)
++{
++ struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
++
++ if (device_may_wakeup(dev))
++ mxs_phy_enable_ldo_in_suspend(mxs_phy, false);
++
++ return 0;
++}
++
++SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, mxs_phy_system_resume);
+
+ static struct platform_driver mxs_phy_driver = {
+ .probe = mxs_phy_probe,
+@@ -192,6 +568,7 @@
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = mxs_phy_dt_ids,
++ .pm = &mxs_phy_pm,
+ },
+ };
+
+diff -Nur linux-3.10.30.orig/drivers/usb/usb-common.c linux-linaro-stable-mx6/drivers/usb/usb-common.c
+--- linux-3.10.30.orig/drivers/usb/usb-common.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/usb/usb-common.c 2014-05-15 20:34:09.082093724 +0200
+@@ -13,7 +13,9 @@
+
+ #include <linux/kernel.h>
+ #include <linux/module.h>
++#include <linux/of.h>
+ #include <linux/usb/ch9.h>
++#include <linux/usb/of.h>
+ #include <linux/usb/otg.h>
+
+ const char *usb_otg_state_string(enum usb_otg_state state)
+@@ -79,4 +81,37 @@
+ }
+ EXPORT_SYMBOL_GPL(usb_state_string);
+
++#ifdef CONFIG_OF
++static const char *const usb_dr_modes[] = {
++ [USB_DR_MODE_UNKNOWN] = "",
++ [USB_DR_MODE_HOST] = "host",
++ [USB_DR_MODE_PERIPHERAL] = "peripheral",
++ [USB_DR_MODE_OTG] = "otg",
++};
++
++/**
++ * of_usb_get_dr_mode - Get dual role mode for given device_node
++ * @np: Pointer to the given device_node
++ *
++ * The function gets phy interface string from property 'dr_mode',
++ * and returns the correspondig enum usb_dr_mode
++ */
++enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
++{
++ const char *dr_mode;
++ int err, i;
++
++ err = of_property_read_string(np, "dr_mode", &dr_mode);
++ if (err < 0)
++ return USB_DR_MODE_UNKNOWN;
++
++ for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
++ if (!strcmp(dr_mode, usb_dr_modes[i]))
++ return i;
++
++ return USB_DR_MODE_UNKNOWN;
++}
++EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
++#endif
++
+ MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/video/amba-clcd.c linux-linaro-stable-mx6/drivers/video/amba-clcd.c
+--- linux-3.10.30.orig/drivers/video/amba-clcd.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/amba-clcd.c 2014-05-15 20:34:09.234094818 +0200
+@@ -16,7 +16,10 @@
+ #include <linux/string.h>
+ #include <linux/slab.h>
+ #include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/memblock.h>
+ #include <linux/mm.h>
++#include <linux/of.h>
+ #include <linux/fb.h>
+ #include <linux/init.h>
+ #include <linux/ioport.h>
+@@ -30,6 +33,16 @@
+
+ #define to_clcd(info) container_of(info, struct clcd_fb, fb)
+
++#ifdef CONFIG_ARM
++#define clcdfb_dma_alloc dma_alloc_writecombine
++#define clcdfb_dma_free dma_free_writecombine
++#define clcdfb_dma_mmap dma_mmap_writecombine
++#else
++#define clcdfb_dma_alloc dma_alloc_coherent
++#define clcdfb_dma_free dma_free_coherent
++#define clcdfb_dma_mmap dma_mmap_coherent
++#endif
++
+ /* This is limited to 16 characters when displayed by X startup */
+ static const char *clcd_name = "CLCD FB";
+
+@@ -392,6 +405,44 @@
+ return 0;
+ }
+
++int clcdfb_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vma)
++{
++ return clcdfb_dma_mmap(&fb->dev->dev, vma,
++ fb->fb.screen_base,
++ fb->fb.fix.smem_start,
++ fb->fb.fix.smem_len);
++}
++
++int clcdfb_mmap_io(struct clcd_fb *fb, struct vm_area_struct *vma)
++{
++ unsigned long user_count, count, pfn, off;
++
++ user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
++ count = PAGE_ALIGN(fb->fb.fix.smem_len) >> PAGE_SHIFT;
++ pfn = fb->fb.fix.smem_start >> PAGE_SHIFT;
++ off = vma->vm_pgoff;
++
++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++
++ if (off < count && user_count <= (count - off))
++ return remap_pfn_range(vma, vma->vm_start, pfn + off,
++ user_count << PAGE_SHIFT,
++ vma->vm_page_prot);
++
++ return -ENXIO;
++}
++
++void clcdfb_remove_dma(struct clcd_fb *fb)
++{
++ clcdfb_dma_free(&fb->dev->dev, fb->fb.fix.smem_len,
++ fb->fb.screen_base, fb->fb.fix.smem_start);
++}
++
++void clcdfb_remove_io(struct clcd_fb *fb)
++{
++ iounmap(fb->fb.screen_base);
++}
++
+ static int clcdfb_mmap(struct fb_info *info,
+ struct vm_area_struct *vma)
+ {
+@@ -542,14 +593,239 @@
+ return ret;
+ }
+
++struct string_lookup {
++ const char *string;
++ const u32 val;
++};
++
++static struct string_lookup vmode_lookups[] = {
++ { "FB_VMODE_NONINTERLACED", FB_VMODE_NONINTERLACED},
++ { "FB_VMODE_INTERLACED", FB_VMODE_INTERLACED},
++ { "FB_VMODE_DOUBLE", FB_VMODE_DOUBLE},
++ { "FB_VMODE_ODD_FLD_FIRST", FB_VMODE_ODD_FLD_FIRST},
++ { NULL, 0 },
++};
++
++static struct string_lookup tim2_lookups[] = {
++ { "TIM2_CLKSEL", TIM2_CLKSEL},
++ { "TIM2_IVS", TIM2_IVS},
++ { "TIM2_IHS", TIM2_IHS},
++ { "TIM2_IPC", TIM2_IPC},
++ { "TIM2_IOE", TIM2_IOE},
++ { "TIM2_BCD", TIM2_BCD},
++ { NULL, 0},
++};
++static struct string_lookup cntl_lookups[] = {
++ {"CNTL_LCDEN", CNTL_LCDEN},
++ {"CNTL_LCDBPP1", CNTL_LCDBPP1},
++ {"CNTL_LCDBPP2", CNTL_LCDBPP2},
++ {"CNTL_LCDBPP4", CNTL_LCDBPP4},
++ {"CNTL_LCDBPP8", CNTL_LCDBPP8},
++ {"CNTL_LCDBPP16", CNTL_LCDBPP16},
++ {"CNTL_LCDBPP16_565", CNTL_LCDBPP16_565},
++ {"CNTL_LCDBPP16_444", CNTL_LCDBPP16_444},
++ {"CNTL_LCDBPP24", CNTL_LCDBPP24},
++ {"CNTL_LCDBW", CNTL_LCDBW},
++ {"CNTL_LCDTFT", CNTL_LCDTFT},
++ {"CNTL_LCDMONO8", CNTL_LCDMONO8},
++ {"CNTL_LCDDUAL", CNTL_LCDDUAL},
++ {"CNTL_BGR", CNTL_BGR},
++ {"CNTL_BEBO", CNTL_BEBO},
++ {"CNTL_BEPO", CNTL_BEPO},
++ {"CNTL_LCDPWR", CNTL_LCDPWR},
++ {"CNTL_LCDVCOMP(1)", CNTL_LCDVCOMP(1)},
++ {"CNTL_LCDVCOMP(2)", CNTL_LCDVCOMP(2)},
++ {"CNTL_LCDVCOMP(3)", CNTL_LCDVCOMP(3)},
++ {"CNTL_LCDVCOMP(4)", CNTL_LCDVCOMP(4)},
++ {"CNTL_LCDVCOMP(5)", CNTL_LCDVCOMP(5)},
++ {"CNTL_LCDVCOMP(6)", CNTL_LCDVCOMP(6)},
++ {"CNTL_LCDVCOMP(7)", CNTL_LCDVCOMP(7)},
++ {"CNTL_LDMAFIFOTIME", CNTL_LDMAFIFOTIME},
++ {"CNTL_WATERMARK", CNTL_WATERMARK},
++ { NULL, 0},
++};
++static struct string_lookup caps_lookups[] = {
++ {"CLCD_CAP_RGB444", CLCD_CAP_RGB444},
++ {"CLCD_CAP_RGB5551", CLCD_CAP_RGB5551},
++ {"CLCD_CAP_RGB565", CLCD_CAP_RGB565},
++ {"CLCD_CAP_RGB888", CLCD_CAP_RGB888},
++ {"CLCD_CAP_BGR444", CLCD_CAP_BGR444},
++ {"CLCD_CAP_BGR5551", CLCD_CAP_BGR5551},
++ {"CLCD_CAP_BGR565", CLCD_CAP_BGR565},
++ {"CLCD_CAP_BGR888", CLCD_CAP_BGR888},
++ {"CLCD_CAP_444", CLCD_CAP_444},
++ {"CLCD_CAP_5551", CLCD_CAP_5551},
++ {"CLCD_CAP_565", CLCD_CAP_565},
++ {"CLCD_CAP_888", CLCD_CAP_888},
++ {"CLCD_CAP_RGB", CLCD_CAP_RGB},
++ {"CLCD_CAP_BGR", CLCD_CAP_BGR},
++ {"CLCD_CAP_ALL", CLCD_CAP_ALL},
++ { NULL, 0},
++};
++
++u32 parse_setting(struct string_lookup *lookup, const char *name)
++{
++ int i = 0;
++ while (lookup[i].string != NULL) {
++ if (strcmp(lookup[i].string, name) == 0)
++ return lookup[i].val;
++ ++i;
++ }
++ return -EINVAL;
++}
++
++u32 get_string_lookup(struct device_node *node, const char *name,
++ struct string_lookup *lookup)
++{
++ const char *string;
++ int count, i, ret = 0;
++
++ count = of_property_count_strings(node, name);
++ if (count >= 0)
++ for (i = 0; i < count; i++)
++ if (of_property_read_string_index(node, name, i,
++ &string) == 0)
++ ret |= parse_setting(lookup, string);
++ return ret;
++}
++
++int get_val(struct device_node *node, const char *string)
++{
++ u32 ret = 0;
++
++ if (of_property_read_u32(node, string, &ret))
++ ret = -1;
++ return ret;
++}
++
++struct clcd_panel *getPanel(struct device_node *node)
++{
++ static struct clcd_panel panel;
++
++ panel.mode.refresh = get_val(node, "refresh");
++ panel.mode.xres = get_val(node, "xres");
++ panel.mode.yres = get_val(node, "yres");
++ panel.mode.pixclock = get_val(node, "pixclock");
++ panel.mode.left_margin = get_val(node, "left_margin");
++ panel.mode.right_margin = get_val(node, "right_margin");
++ panel.mode.upper_margin = get_val(node, "upper_margin");
++ panel.mode.lower_margin = get_val(node, "lower_margin");
++ panel.mode.hsync_len = get_val(node, "hsync_len");
++ panel.mode.vsync_len = get_val(node, "vsync_len");
++ panel.mode.sync = get_val(node, "sync");
++ panel.bpp = get_val(node, "bpp");
++ panel.width = (signed short) get_val(node, "width");
++ panel.height = (signed short) get_val(node, "height");
++
++ panel.mode.vmode = get_string_lookup(node, "vmode", vmode_lookups);
++ panel.tim2 = get_string_lookup(node, "tim2", tim2_lookups);
++ panel.cntl = get_string_lookup(node, "cntl", cntl_lookups);
++ panel.caps = get_string_lookup(node, "caps", caps_lookups);
++
++ return &panel;
++}
++
++struct clcd_panel *clcdfb_get_panel(const char *name)
++{
++ struct device_node *node = NULL;
++ const char *mode;
++ struct clcd_panel *panel = NULL;
++
++ do {
++ node = of_find_compatible_node(node, NULL, "panel");
++ if (node)
++ if (of_property_read_string(node, "mode", &mode) == 0)
++ if (strcmp(mode, name) == 0) {
++ panel = getPanel(node);
++ panel->mode.name = name;
++ }
++ } while (node != NULL);
++
++ return panel;
++}
++
++#ifdef CONFIG_OF
++static int clcdfb_dt_init(struct clcd_fb *fb)
++{
++ int err = 0;
++ struct device_node *node;
++ const char *mode;
++ dma_addr_t dma;
++ u32 use_dma;
++ const __be32 *prop;
++ int len, na, ns;
++ phys_addr_t fb_base, fb_size;
++
++ node = fb->dev->dev.of_node;
++ if (!node)
++ return -ENODEV;
++
++ na = of_n_addr_cells(node);
++ ns = of_n_size_cells(node);
++
++ if (WARN_ON(of_property_read_string(node, "mode", &mode)))
++ return -ENODEV;
++
++ fb->panel = clcdfb_get_panel(mode);
++ if (!fb->panel)
++ return -EINVAL;
++ fb->fb.fix.smem_len = fb->panel->mode.xres * fb->panel->mode.yres * 2;
++
++ fb->board->name = "Device Tree CLCD PL111";
++ fb->board->caps = CLCD_CAP_5551 | CLCD_CAP_565;
++ fb->board->check = clcdfb_check;
++ fb->board->decode = clcdfb_decode;
++
++ if (of_property_read_u32(node, "use_dma", &use_dma))
++ use_dma = 0;
++
++ if (use_dma) {
++ fb->fb.screen_base = clcdfb_dma_alloc(&fb->dev->dev,
++ fb->fb.fix.smem_len,
++ &dma, GFP_KERNEL);
++ if (!fb->fb.screen_base) {
++ pr_err("CLCD: unable to map framebuffer\n");
++ return -ENOMEM;
++ }
++
++ fb->fb.fix.smem_start = dma;
++ fb->board->mmap = clcdfb_mmap_dma;
++ fb->board->remove = clcdfb_remove_dma;
++ } else {
++ prop = of_get_property(node, "framebuffer", &len);
++ if (WARN_ON(!prop || len < (na + ns) * sizeof(*prop)))
++ return -EINVAL;
++
++ fb_base = of_read_number(prop, na);
++ fb_size = of_read_number(prop + na, ns);
++
++ fb->fb.fix.smem_start = fb_base;
++ fb->fb.screen_base = ioremap_wc(fb_base, fb_size);
++ fb->board->mmap = clcdfb_mmap_io;
++ fb->board->remove = clcdfb_remove_io;
++ }
++
++ return err;
++}
++#endif /* CONFIG_OF */
++
+ static int clcdfb_probe(struct amba_device *dev, const struct amba_id *id)
+ {
+ struct clcd_board *board = dev->dev.platform_data;
+ struct clcd_fb *fb;
+ int ret;
+
+- if (!board)
+- return -EINVAL;
++ if (!board) {
++#ifdef CONFIG_OF
++ if (dev->dev.of_node) {
++ board = kzalloc(sizeof(struct clcd_board), GFP_KERNEL);
++ if (!board)
++ return -ENOMEM;
++ board->setup = clcdfb_dt_init;
++ } else
++#endif
++ return -EINVAL;
++ }
+
+ ret = amba_request_regions(dev, NULL);
+ if (ret) {
+diff -Nur linux-3.10.30.orig/drivers/video/arm-hdlcd.c linux-linaro-stable-mx6/drivers/video/arm-hdlcd.c
+--- linux-3.10.30.orig/drivers/video/arm-hdlcd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/arm-hdlcd.c 2014-05-15 20:34:09.234094818 +0200
+@@ -0,0 +1,844 @@
++/*
++ * drivers/video/arm-hdlcd.c
++ *
++ * Copyright (C) 2011 ARM Limited
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * ARM HDLCD Controller
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/ctype.h>
++#include <linux/mm.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/fb.h>
++#include <linux/clk.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/memblock.h>
++#include <linux/arm-hdlcd.h>
++#ifdef HDLCD_COUNT_BUFFERUNDERRUNS
++#include <linux/proc_fs.h>
++#include <linux/seq_file.h>
++#endif
++
++#include "edid.h"
++
++#ifdef CONFIG_SERIAL_AMBA_PCU_UART
++int get_edid(u8 *msgbuf);
++#else
++#endif
++
++#define to_hdlcd_device(info) container_of(info, struct hdlcd_device, fb)
++
++static struct of_device_id hdlcd_of_matches[] = {
++ { .compatible = "arm,hdlcd" },
++ {},
++};
++
++/* Framebuffer size. */
++static unsigned long framebuffer_size;
++
++#ifdef HDLCD_COUNT_BUFFERUNDERRUNS
++static unsigned long buffer_underrun_events;
++static DEFINE_SPINLOCK(hdlcd_underrun_lock);
++
++static void hdlcd_underrun_set(unsigned long val)
++{
++ spin_lock(&hdlcd_underrun_lock);
++ buffer_underrun_events = val;
++ spin_unlock(&hdlcd_underrun_lock);
++}
++
++static unsigned long hdlcd_underrun_get(void)
++{
++ unsigned long val;
++ spin_lock(&hdlcd_underrun_lock);
++ val = buffer_underrun_events;
++ spin_unlock(&hdlcd_underrun_lock);
++ return val;
++}
++
++#ifdef CONFIG_PROC_FS
++static int hdlcd_underrun_show(struct seq_file *m, void *v)
++{
++ unsigned char underrun_string[32];
++ snprintf(underrun_string, 32, "%lu\n", hdlcd_underrun_get());
++ seq_puts(m, underrun_string);
++ return 0;
++}
++
++static int proc_hdlcd_underrun_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, hdlcd_underrun_show, NULL);
++}
++
++static const struct file_operations proc_hdlcd_underrun_operations = {
++ .open = proc_hdlcd_underrun_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static int hdlcd_underrun_init(void)
++{
++ hdlcd_underrun_set(0);
++ proc_create("hdlcd_underrun", 0, NULL, &proc_hdlcd_underrun_operations);
++ return 0;
++}
++static void hdlcd_underrun_close(void)
++{
++ remove_proc_entry("hdlcd_underrun", NULL);
++}
++#else
++static int hdlcd_underrun_init(void) { return 0; }
++static void hdlcd_underrun_close(void) { }
++#endif
++#endif
++
++static char *fb_mode = "1680x1050-32@60\0\0\0\0\0";
++
++static struct fb_var_screeninfo cached_var_screeninfo;
++
++static struct fb_videomode hdlcd_default_mode = {
++ .refresh = 60,
++ .xres = 1680,
++ .yres = 1050,
++ .pixclock = 8403,
++ .left_margin = 80,
++ .right_margin = 48,
++ .upper_margin = 21,
++ .lower_margin = 3,
++ .hsync_len = 32,
++ .vsync_len = 6,
++ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ .vmode = FB_VMODE_NONINTERLACED
++};
++
++static inline void hdlcd_enable(struct hdlcd_device *hdlcd)
++{
++ dev_dbg(hdlcd->dev, "HDLCD: output enabled\n");
++ writel(1, hdlcd->base + HDLCD_REG_COMMAND);
++}
++
++static inline void hdlcd_disable(struct hdlcd_device *hdlcd)
++{
++ dev_dbg(hdlcd->dev, "HDLCD: output disabled\n");
++ writel(0, hdlcd->base + HDLCD_REG_COMMAND);
++}
++
++static int hdlcd_set_bitfields(struct hdlcd_device *hdlcd,
++ struct fb_var_screeninfo *var)
++{
++ int ret = 0;
++
++ memset(&var->transp, 0, sizeof(var->transp));
++ var->red.msb_right = 0;
++ var->green.msb_right = 0;
++ var->blue.msb_right = 0;
++ var->blue.offset = 0;
++
++ switch (var->bits_per_pixel) {
++ case 8:
++ /* pseudocolor */
++ var->red.length = 8;
++ var->green.length = 8;
++ var->blue.length = 8;
++ break;
++ case 16:
++ /* 565 format */
++ var->red.length = 5;
++ var->green.length = 6;
++ var->blue.length = 5;
++ break;
++ case 32:
++ var->transp.length = 8;
++ case 24:
++ var->red.length = 8;
++ var->green.length = 8;
++ var->blue.length = 8;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ if (!ret) {
++ if(var->bits_per_pixel != 32)
++ {
++ var->green.offset = var->blue.length;
++ var->red.offset = var->green.offset + var->green.length;
++ }
++ else
++ {
++ /* Previously, the byte ordering for 32-bit color was
++ * (msb)<alpha><red><green><blue>(lsb)
++ * but this does not match what android expects and
++ * the colors are odd. Instead, use
++ * <alpha><blue><green><red>
++ * Since we tell fb what we are doing, console
++ * , X and directfb access should work fine.
++ */
++ var->green.offset = var->red.length;
++ var->blue.offset = var->green.offset + var->green.length;
++ var->transp.offset = var->blue.offset + var->blue.length;
++ }
++ }
++
++ return ret;
++}
++
++static int hdlcd_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ struct hdlcd_device *hdlcd = to_hdlcd_device(info);
++ int bytes_per_pixel = var->bits_per_pixel / 8;
++
++#ifdef HDLCD_NO_VIRTUAL_SCREEN
++ var->yres_virtual = var->yres;
++#else
++ var->yres_virtual = 2 * var->yres;
++#endif
++
++ if ((var->xres_virtual * bytes_per_pixel * var->yres_virtual) > hdlcd->fb.fix.smem_len)
++ return -ENOMEM;
++
++ if (var->xres > HDLCD_MAX_XRES || var->yres > HDLCD_MAX_YRES)
++ return -EINVAL;
++
++ /* make sure the bitfields are set appropriately */
++ return hdlcd_set_bitfields(hdlcd, var);
++}
++
++/* prototype */
++static int hdlcd_pan_display(struct fb_var_screeninfo *var,
++ struct fb_info *info);
++
++#define WRITE_HDLCD_REG(reg, value) writel((value), hdlcd->base + (reg))
++#define READ_HDLCD_REG(reg) readl(hdlcd->base + (reg))
++
++static int hdlcd_set_par(struct fb_info *info)
++{
++ struct hdlcd_device *hdlcd = to_hdlcd_device(info);
++ int bytes_per_pixel = hdlcd->fb.var.bits_per_pixel / 8;
++ int polarities;
++ int old_yoffset;
++
++ /* check for shortcuts */
++ old_yoffset = cached_var_screeninfo.yoffset;
++ cached_var_screeninfo.yoffset = info->var.yoffset;
++ if (!memcmp(&info->var, &cached_var_screeninfo,
++ sizeof(struct fb_var_screeninfo))) {
++ if(old_yoffset != info->var.yoffset) {
++ /* we only changed yoffset, and we already
++ * already recorded it a couple lines up
++ */
++ hdlcd_pan_display(&info->var, info);
++ }
++ /* or no change */
++ return 0;
++ }
++
++ hdlcd->fb.fix.line_length = hdlcd->fb.var.xres * bytes_per_pixel;
++
++ if (hdlcd->fb.var.bits_per_pixel >= 16)
++ hdlcd->fb.fix.visual = FB_VISUAL_TRUECOLOR;
++ else
++ hdlcd->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
++
++ memcpy(&cached_var_screeninfo, &info->var, sizeof(struct fb_var_screeninfo));
++
++ polarities = HDLCD_POLARITY_DATAEN |
++#ifndef CONFIG_ARCH_TUSCAN
++ HDLCD_POLARITY_PIXELCLK |
++#endif
++ HDLCD_POLARITY_DATA;
++ polarities |= (hdlcd->fb.var.sync & FB_SYNC_HOR_HIGH_ACT) ? HDLCD_POLARITY_HSYNC : 0;
++ polarities |= (hdlcd->fb.var.sync & FB_SYNC_VERT_HIGH_ACT) ? HDLCD_POLARITY_VSYNC : 0;
++
++ hdlcd_disable(hdlcd);
++
++ WRITE_HDLCD_REG(HDLCD_REG_FB_LINE_LENGTH, hdlcd->fb.var.xres * bytes_per_pixel);
++ WRITE_HDLCD_REG(HDLCD_REG_FB_LINE_PITCH, hdlcd->fb.var.xres * bytes_per_pixel);
++ WRITE_HDLCD_REG(HDLCD_REG_FB_LINE_COUNT, hdlcd->fb.var.yres - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_V_SYNC, hdlcd->fb.var.vsync_len - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_V_BACK_PORCH, hdlcd->fb.var.upper_margin - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_V_DATA, hdlcd->fb.var.yres - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_V_FRONT_PORCH, hdlcd->fb.var.lower_margin - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_H_SYNC, hdlcd->fb.var.hsync_len - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_H_BACK_PORCH, hdlcd->fb.var.left_margin - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_H_DATA, hdlcd->fb.var.xres - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_H_FRONT_PORCH, hdlcd->fb.var.right_margin - 1);
++ WRITE_HDLCD_REG(HDLCD_REG_POLARITIES, polarities);
++ WRITE_HDLCD_REG(HDLCD_REG_PIXEL_FORMAT, (bytes_per_pixel - 1) << 3);
++#ifdef HDLCD_RED_DEFAULT_COLOUR
++ WRITE_HDLCD_REG(HDLCD_REG_RED_SELECT, (0x00ff0000 | (hdlcd->fb.var.red.length & 0xf) << 8) \
++ | hdlcd->fb.var.red.offset);
++#else
++ WRITE_HDLCD_REG(HDLCD_REG_RED_SELECT, ((hdlcd->fb.var.red.length & 0xf) << 8) | hdlcd->fb.var.red.offset);
++#endif
++ WRITE_HDLCD_REG(HDLCD_REG_GREEN_SELECT, ((hdlcd->fb.var.green.length & 0xf) << 8) | hdlcd->fb.var.green.offset);
++ WRITE_HDLCD_REG(HDLCD_REG_BLUE_SELECT, ((hdlcd->fb.var.blue.length & 0xf) << 8) | hdlcd->fb.var.blue.offset);
++
++ clk_set_rate(hdlcd->clk, (1000000000 / hdlcd->fb.var.pixclock) * 1000);
++ clk_enable(hdlcd->clk);
++
++ hdlcd_enable(hdlcd);
++
++ return 0;
++}
++
++static int hdlcd_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
++ unsigned int blue, unsigned int transp, struct fb_info *info)
++{
++ if (regno < 16) {
++ u32 *pal = info->pseudo_palette;
++
++ pal[regno] = ((red >> 8) << info->var.red.offset) |
++ ((green >> 8) << info->var.green.offset) |
++ ((blue >> 8) << info->var.blue.offset);
++ }
++
++ return 0;
++}
++
++static irqreturn_t hdlcd_irq(int irq, void *data)
++{
++ struct hdlcd_device *hdlcd = data;
++ unsigned long irq_mask, irq_status;
++
++ irq_mask = READ_HDLCD_REG(HDLCD_REG_INT_MASK);
++ irq_status = READ_HDLCD_REG(HDLCD_REG_INT_STATUS);
++
++ /* acknowledge interrupt(s) */
++ WRITE_HDLCD_REG(HDLCD_REG_INT_CLEAR, irq_status);
++#ifdef HDLCD_COUNT_BUFFERUNDERRUNS
++ if (irq_status & HDLCD_INTERRUPT_UNDERRUN) {
++ /* increment the count */
++ hdlcd_underrun_set(hdlcd_underrun_get() + 1);
++ }
++#endif
++ if (irq_status & HDLCD_INTERRUPT_VSYNC) {
++ /* disable future VSYNC interrupts */
++ WRITE_HDLCD_REG(HDLCD_REG_INT_MASK, irq_mask & ~HDLCD_INTERRUPT_VSYNC);
++
++ complete(&hdlcd->vsync_completion);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int hdlcd_wait_for_vsync(struct fb_info *info)
++{
++ struct hdlcd_device *hdlcd = to_hdlcd_device(info);
++ unsigned long irq_mask;
++ int err;
++
++ /* enable VSYNC interrupt */
++ irq_mask = READ_HDLCD_REG(HDLCD_REG_INT_MASK);
++ WRITE_HDLCD_REG(HDLCD_REG_INT_MASK, irq_mask | HDLCD_INTERRUPT_VSYNC);
++
++ err = wait_for_completion_interruptible_timeout(&hdlcd->vsync_completion,
++ msecs_to_jiffies(100));
++
++ if (!err)
++ return -ETIMEDOUT;
++
++ return 0;
++}
++
++static int hdlcd_blank(int blank_mode, struct fb_info *info)
++{
++ struct hdlcd_device *hdlcd = to_hdlcd_device(info);
++
++ switch (blank_mode) {
++ case FB_BLANK_POWERDOWN:
++ clk_disable(hdlcd->clk);
++ case FB_BLANK_NORMAL:
++ hdlcd_disable(hdlcd);
++ break;
++ case FB_BLANK_UNBLANK:
++ clk_enable(hdlcd->clk);
++ hdlcd_enable(hdlcd);
++ break;
++ case FB_BLANK_VSYNC_SUSPEND:
++ case FB_BLANK_HSYNC_SUSPEND:
++ default:
++ return 1;
++ }
++
++ return 0;
++}
++
++static void hdlcd_mmap_open(struct vm_area_struct *vma)
++{
++}
++
++static void hdlcd_mmap_close(struct vm_area_struct *vma)
++{
++}
++
++static struct vm_operations_struct hdlcd_mmap_ops = {
++ .open = hdlcd_mmap_open,
++ .close = hdlcd_mmap_close,
++};
++
++static int hdlcd_mmap(struct fb_info *info, struct vm_area_struct *vma)
++{
++ struct hdlcd_device *hdlcd = to_hdlcd_device(info);
++ unsigned long off;
++ unsigned long start;
++ unsigned long len = hdlcd->fb.fix.smem_len;
++
++ if (vma->vm_end - vma->vm_start == 0)
++ return 0;
++ if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
++ return -EINVAL;
++
++ off = vma->vm_pgoff << PAGE_SHIFT;
++ if ((off >= len) || (vma->vm_end - vma->vm_start + off) > len)
++ return -EINVAL;
++
++ start = hdlcd->fb.fix.smem_start;
++ off += start;
++
++ vma->vm_pgoff = off >> PAGE_SHIFT;
++ vma->vm_flags |= VM_IO;
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++ vma->vm_ops = &hdlcd_mmap_ops;
++ if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
++ vma->vm_end - vma->vm_start,
++ vma->vm_page_prot))
++ return -EAGAIN;
++
++ return 0;
++}
++
++static int hdlcd_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ struct hdlcd_device *hdlcd = to_hdlcd_device(info);
++
++ hdlcd->fb.var.yoffset = var->yoffset;
++ WRITE_HDLCD_REG(HDLCD_REG_FB_BASE, hdlcd->fb.fix.smem_start +
++ (var->yoffset * hdlcd->fb.fix.line_length));
++
++ hdlcd_wait_for_vsync(info);
++
++ return 0;
++}
++
++static int hdlcd_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
++{
++ int err;
++
++ switch (cmd) {
++ case FBIO_WAITFORVSYNC:
++ err = hdlcd_wait_for_vsync(info);
++ break;
++ default:
++ err = -ENOIOCTLCMD;
++ break;
++ }
++
++ return err;
++}
++
++static struct fb_ops hdlcd_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = hdlcd_check_var,
++ .fb_set_par = hdlcd_set_par,
++ .fb_setcolreg = hdlcd_setcolreg,
++ .fb_blank = hdlcd_blank,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++ .fb_mmap = hdlcd_mmap,
++ .fb_pan_display = hdlcd_pan_display,
++ .fb_ioctl = hdlcd_ioctl,
++ .fb_compat_ioctl = hdlcd_ioctl
++};
++
++static int hdlcd_setup(struct hdlcd_device *hdlcd)
++{
++ u32 version;
++ int err = -EFAULT;
++
++ hdlcd->fb.device = hdlcd->dev;
++
++ hdlcd->clk = clk_get(hdlcd->dev, NULL);
++ if (IS_ERR(hdlcd->clk)) {
++ dev_err(hdlcd->dev, "HDLCD: unable to find clock data\n");
++ return PTR_ERR(hdlcd->clk);
++ }
++
++ err = clk_prepare(hdlcd->clk);
++ if (err)
++ goto clk_prepare_err;
++
++ hdlcd->base = ioremap_nocache(hdlcd->fb.fix.mmio_start, hdlcd->fb.fix.mmio_len);
++ if (!hdlcd->base) {
++ dev_err(hdlcd->dev, "HDLCD: unable to map registers\n");
++ goto remap_err;
++ }
++
++ hdlcd->fb.pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
++ if (!hdlcd->fb.pseudo_palette) {
++ dev_err(hdlcd->dev, "HDLCD: unable to allocate pseudo_palette memory\n");
++ err = -ENOMEM;
++ goto kmalloc_err;
++ }
++
++ version = readl(hdlcd->base + HDLCD_REG_VERSION);
++ if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
++ dev_err(hdlcd->dev, "HDLCD: unknown product id: 0x%x\n", version);
++ err = -EINVAL;
++ goto kmalloc_err;
++ }
++ dev_info(hdlcd->dev, "HDLCD: found ARM HDLCD version r%dp%d\n",
++ (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
++ version & HDLCD_VERSION_MINOR_MASK);
++
++ strcpy(hdlcd->fb.fix.id, "hdlcd");
++ hdlcd->fb.fbops = &hdlcd_ops;
++ hdlcd->fb.flags = FBINFO_FLAG_DEFAULT/* | FBINFO_VIRTFB*/;
++
++ hdlcd->fb.fix.type = FB_TYPE_PACKED_PIXELS;
++ hdlcd->fb.fix.type_aux = 0;
++ hdlcd->fb.fix.xpanstep = 0;
++ hdlcd->fb.fix.ypanstep = 1;
++ hdlcd->fb.fix.ywrapstep = 0;
++ hdlcd->fb.fix.accel = FB_ACCEL_NONE;
++
++ hdlcd->fb.var.nonstd = 0;
++ hdlcd->fb.var.activate = FB_ACTIVATE_NOW;
++ hdlcd->fb.var.height = -1;
++ hdlcd->fb.var.width = -1;
++ hdlcd->fb.var.accel_flags = 0;
++
++ init_completion(&hdlcd->vsync_completion);
++
++ if (hdlcd->edid) {
++ /* build modedb from EDID */
++ fb_edid_to_monspecs(hdlcd->edid, &hdlcd->fb.monspecs);
++ fb_videomode_to_modelist(hdlcd->fb.monspecs.modedb,
++ hdlcd->fb.monspecs.modedb_len,
++ &hdlcd->fb.modelist);
++ fb_find_mode(&hdlcd->fb.var, &hdlcd->fb, fb_mode,
++ hdlcd->fb.monspecs.modedb,
++ hdlcd->fb.monspecs.modedb_len,
++ &hdlcd_default_mode, 32);
++ } else {
++ hdlcd->fb.monspecs.hfmin = 0;
++ hdlcd->fb.monspecs.hfmax = 100000;
++ hdlcd->fb.monspecs.vfmin = 0;
++ hdlcd->fb.monspecs.vfmax = 400;
++ hdlcd->fb.monspecs.dclkmin = 1000000;
++ hdlcd->fb.monspecs.dclkmax = 100000000;
++ fb_find_mode(&hdlcd->fb.var, &hdlcd->fb, fb_mode, NULL, 0, &hdlcd_default_mode, 32);
++ }
++
++ dev_info(hdlcd->dev, "using %dx%d-%d@%d mode\n", hdlcd->fb.var.xres,
++ hdlcd->fb.var.yres, hdlcd->fb.var.bits_per_pixel,
++ hdlcd->fb.mode ? hdlcd->fb.mode->refresh : 60);
++ hdlcd->fb.var.xres_virtual = hdlcd->fb.var.xres;
++#ifdef HDLCD_NO_VIRTUAL_SCREEN
++ hdlcd->fb.var.yres_virtual = hdlcd->fb.var.yres;
++#else
++ hdlcd->fb.var.yres_virtual = hdlcd->fb.var.yres * 2;
++#endif
++
++ /* initialise and set the palette */
++ if (fb_alloc_cmap(&hdlcd->fb.cmap, NR_PALETTE, 0)) {
++ dev_err(hdlcd->dev, "failed to allocate cmap memory\n");
++ err = -ENOMEM;
++ goto setup_err;
++ }
++ fb_set_cmap(&hdlcd->fb.cmap, &hdlcd->fb);
++
++ /* Allow max number of outstanding requests with the largest beat burst */
++ WRITE_HDLCD_REG(HDLCD_REG_BUS_OPTIONS, HDLCD_BUS_MAX_OUTSTAND | HDLCD_BUS_BURST_16);
++ /* Set the framebuffer base to start of allocated memory */
++ WRITE_HDLCD_REG(HDLCD_REG_FB_BASE, hdlcd->fb.fix.smem_start);
++#ifdef HDLCD_COUNT_BUFFERUNDERRUNS
++ /* turn on underrun interrupt for counting */
++ WRITE_HDLCD_REG(HDLCD_REG_INT_MASK, HDLCD_INTERRUPT_UNDERRUN);
++#else
++ /* Ensure interrupts are disabled */
++ WRITE_HDLCD_REG(HDLCD_REG_INT_MASK, 0);
++#endif
++ fb_set_var(&hdlcd->fb, &hdlcd->fb.var);
++
++ if (!register_framebuffer(&hdlcd->fb)) {
++ return 0;
++ }
++
++ dev_err(hdlcd->dev, "HDLCD: cannot register framebuffer\n");
++
++ fb_dealloc_cmap(&hdlcd->fb.cmap);
++setup_err:
++ iounmap(hdlcd->base);
++kmalloc_err:
++ kfree(hdlcd->fb.pseudo_palette);
++remap_err:
++ clk_unprepare(hdlcd->clk);
++clk_prepare_err:
++ clk_put(hdlcd->clk);
++ return err;
++}
++
++static inline unsigned char atohex(u8 data)
++{
++ if (!isxdigit(data))
++ return 0;
++ /* truncate the upper nibble and add 9 to non-digit values */
++ return (data > 0x39) ? ((data & 0xf) + 9) : (data & 0xf);
++}
++
++/* EDID data is passed from devicetree in a literal string that can contain spaces and
++ the hexadecimal dump of the data */
++static int parse_edid_data(struct hdlcd_device *hdlcd, const u8 *edid_data, int data_len)
++{
++ int i, j;
++
++ if (!edid_data)
++ return -EINVAL;
++
++ hdlcd->edid = kzalloc(EDID_LENGTH, GFP_KERNEL);
++ if (!hdlcd->edid)
++ return -ENOMEM;
++
++ for (i = 0, j = 0; i < data_len; i++) {
++ if (isspace(edid_data[i]))
++ continue;
++ hdlcd->edid[j++] = atohex(edid_data[i]);
++ if (j >= EDID_LENGTH)
++ break;
++ }
++
++ if (j < EDID_LENGTH) {
++ kfree(hdlcd->edid);
++ hdlcd->edid = NULL;
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int hdlcd_probe(struct platform_device *pdev)
++{
++ int err = 0, i;
++ struct hdlcd_device *hdlcd;
++ struct resource *mem;
++#ifdef CONFIG_OF
++ struct device_node *of_node;
++#endif
++
++ memset(&cached_var_screeninfo, 0, sizeof(struct fb_var_screeninfo));
++
++ dev_dbg(&pdev->dev, "HDLCD: probing\n");
++
++ hdlcd = kzalloc(sizeof(*hdlcd), GFP_KERNEL);
++ if (!hdlcd)
++ return -ENOMEM;
++
++#ifdef CONFIG_OF
++ of_node = pdev->dev.of_node;
++ if (of_node) {
++ int len;
++ const u8 *edid;
++ const __be32 *prop = of_get_property(of_node, "mode", &len);
++ if (prop)
++ strncpy(fb_mode, (char *)prop, len);
++ prop = of_get_property(of_node, "framebuffer", &len);
++ if (prop) {
++ hdlcd->fb.fix.smem_start = of_read_ulong(prop,
++ of_n_addr_cells(of_node));
++ prop += of_n_addr_cells(of_node);
++ framebuffer_size = of_read_ulong(prop,
++ of_n_size_cells(of_node));
++ if (framebuffer_size > HDLCD_MAX_FRAMEBUFFER_SIZE)
++ framebuffer_size = HDLCD_MAX_FRAMEBUFFER_SIZE;
++ dev_dbg(&pdev->dev, "HDLCD: phys_addr = 0x%lx, size = 0x%lx\n",
++ hdlcd->fb.fix.smem_start, framebuffer_size);
++ }
++ edid = of_get_property(of_node, "edid", &len);
++ if (edid) {
++ err = parse_edid_data(hdlcd, edid, len);
++#ifdef CONFIG_SERIAL_AMBA_PCU_UART
++ } else {
++ /* ask the firmware to fetch the EDID */
++ dev_dbg(&pdev->dev, "HDLCD: Requesting EDID data\n");
++ hdlcd->edid = kzalloc(EDID_LENGTH, GFP_KERNEL);
++ if (!hdlcd->edid)
++ return -ENOMEM;
++ err = get_edid(hdlcd->edid);
++#endif /* CONFIG_SERIAL_AMBA_PCU_UART */
++ }
++ if (err)
++ dev_info(&pdev->dev, "HDLCD: Failed to parse EDID data\n");
++ }
++#endif /* CONFIG_OF */
++
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!mem) {
++ dev_err(&pdev->dev, "HDLCD: cannot get platform resources\n");
++ err = -EINVAL;
++ goto resource_err;
++ }
++
++ i = platform_get_irq(pdev, 0);
++ if (i < 0) {
++ dev_err(&pdev->dev, "HDLCD: no irq defined for vsync\n");
++ err = -ENOENT;
++ goto resource_err;
++ } else {
++ err = request_irq(i, hdlcd_irq, 0, dev_name(&pdev->dev), hdlcd);
++ if (err) {
++ dev_err(&pdev->dev, "HDLCD: unable to request irq\n");
++ goto resource_err;
++ }
++ hdlcd->irq = i;
++ }
++
++ if (!request_mem_region(mem->start, resource_size(mem), dev_name(&pdev->dev))) {
++ err = -ENXIO;
++ goto request_err;
++ }
++
++ if (!hdlcd->fb.fix.smem_start) {
++ dev_err(&pdev->dev, "platform did not allocate frame buffer memory\n");
++ err = -ENOMEM;
++ goto memalloc_err;
++ }
++ hdlcd->fb.screen_base = ioremap_wc(hdlcd->fb.fix.smem_start, framebuffer_size);
++ if (!hdlcd->fb.screen_base) {
++ dev_err(&pdev->dev, "unable to ioremap framebuffer\n");
++ err = -ENOMEM;
++ goto probe_err;
++ }
++
++ hdlcd->fb.screen_size = framebuffer_size;
++ hdlcd->fb.fix.smem_len = framebuffer_size;
++ hdlcd->fb.fix.mmio_start = mem->start;
++ hdlcd->fb.fix.mmio_len = resource_size(mem);
++
++ /* Clear the framebuffer */
++ memset(hdlcd->fb.screen_base, 0, framebuffer_size);
++
++ hdlcd->dev = &pdev->dev;
++
++ dev_dbg(&pdev->dev, "HDLCD: framebuffer virt base %p, phys base 0x%lX\n",
++ hdlcd->fb.screen_base, (unsigned long)hdlcd->fb.fix.smem_start);
++
++ err = hdlcd_setup(hdlcd);
++
++ if (err)
++ goto probe_err;
++
++ platform_set_drvdata(pdev, hdlcd);
++ return 0;
++
++probe_err:
++ iounmap(hdlcd->fb.screen_base);
++ memblock_free(hdlcd->fb.fix.smem_start, hdlcd->fb.fix.smem_start);
++
++memalloc_err:
++ release_mem_region(mem->start, resource_size(mem));
++
++request_err:
++ free_irq(hdlcd->irq, hdlcd);
++
++resource_err:
++ kfree(hdlcd);
++
++ return err;
++}
++
++static int hdlcd_remove(struct platform_device *pdev)
++{
++ struct hdlcd_device *hdlcd = platform_get_drvdata(pdev);
++
++ clk_disable(hdlcd->clk);
++ clk_unprepare(hdlcd->clk);
++ clk_put(hdlcd->clk);
++
++ /* unmap memory */
++ iounmap(hdlcd->fb.screen_base);
++ iounmap(hdlcd->base);
++
++ /* deallocate fb memory */
++ fb_dealloc_cmap(&hdlcd->fb.cmap);
++ kfree(hdlcd->fb.pseudo_palette);
++ memblock_free(hdlcd->fb.fix.smem_start, hdlcd->fb.fix.smem_start);
++ release_mem_region(hdlcd->fb.fix.mmio_start, hdlcd->fb.fix.mmio_len);
++
++ free_irq(hdlcd->irq, NULL);
++ kfree(hdlcd);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int hdlcd_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ /* not implemented yet */
++ return 0;
++}
++
++static int hdlcd_resume(struct platform_device *pdev)
++{
++ /* not implemented yet */
++ return 0;
++}
++#else
++#define hdlcd_suspend NULL
++#define hdlcd_resume NULL
++#endif
++
++static struct platform_driver hdlcd_driver = {
++ .probe = hdlcd_probe,
++ .remove = hdlcd_remove,
++ .suspend = hdlcd_suspend,
++ .resume = hdlcd_resume,
++ .driver = {
++ .name = "hdlcd",
++ .owner = THIS_MODULE,
++ .of_match_table = hdlcd_of_matches,
++ },
++};
++
++static int __init hdlcd_init(void)
++{
++#ifdef HDLCD_COUNT_BUFFERUNDERRUNS
++ int err = platform_driver_register(&hdlcd_driver);
++ if (!err)
++ hdlcd_underrun_init();
++ return err;
++#else
++ return platform_driver_register(&hdlcd_driver);
++#endif
++}
++
++void __exit hdlcd_exit(void)
++{
++#ifdef HDLCD_COUNT_BUFFERUNDERRUNS
++ hdlcd_underrun_close();
++#endif
++ platform_driver_unregister(&hdlcd_driver);
++}
++
++module_init(hdlcd_init);
++module_exit(hdlcd_exit);
++
++MODULE_AUTHOR("Liviu Dudau");
++MODULE_DESCRIPTION("ARM HDLCD core driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/drivers/video/backlight/backlight.c linux-linaro-stable-mx6/drivers/video/backlight/backlight.c
+--- linux-3.10.30.orig/drivers/video/backlight/backlight.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/backlight/backlight.c 2014-05-15 20:34:09.282095164 +0200
+@@ -38,6 +38,8 @@
+ {
+ struct backlight_device *bd;
+ struct fb_event *evdata = data;
++ int node = evdata->info->node;
++ int fb_blank = 0;
+
+ /* If we aren't interested in this event, skip it immediately ... */
+ if (event != FB_EVENT_BLANK && event != FB_EVENT_CONBLANK)
+@@ -48,12 +50,24 @@
+ if (bd->ops)
+ if (!bd->ops->check_fb ||
+ bd->ops->check_fb(bd, evdata->info)) {
+- bd->props.fb_blank = *(int *)evdata->data;
+- if (bd->props.fb_blank == FB_BLANK_UNBLANK)
+- bd->props.state &= ~BL_CORE_FBBLANK;
+- else
+- bd->props.state |= BL_CORE_FBBLANK;
+- backlight_update_status(bd);
++ fb_blank = *(int *)evdata->data;
++ if (fb_blank == FB_BLANK_UNBLANK &&
++ !bd->fb_bl_on[node]) {
++ bd->fb_bl_on[node] = true;
++ if (!bd->use_count++) {
++ bd->props.state &= ~BL_CORE_FBBLANK;
++ bd->props.fb_blank = FB_BLANK_UNBLANK;
++ backlight_update_status(bd);
++ }
++ } else if (fb_blank != FB_BLANK_UNBLANK &&
++ bd->fb_bl_on[node]) {
++ bd->fb_bl_on[node] = false;
++ if (!(--bd->use_count)) {
++ bd->props.state |= BL_CORE_FBBLANK;
++ bd->props.fb_blank = FB_BLANK_POWERDOWN;
++ backlight_update_status(bd);
++ }
++ }
+ }
+ mutex_unlock(&bd->ops_lock);
+ return 0;
+diff -Nur linux-3.10.30.orig/drivers/video/console/fbcon.c linux-linaro-stable-mx6/drivers/video/console/fbcon.c
+--- linux-3.10.30.orig/drivers/video/console/fbcon.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/console/fbcon.c 2014-05-15 20:34:09.378095855 +0200
+@@ -404,7 +404,7 @@
+ struct fb_info *info = (struct fb_info *) dev_addr;
+ struct fbcon_ops *ops = info->fbcon_par;
+
+- schedule_work(&info->queue);
++ queue_work(system_power_efficient_wq, &info->queue);
+ mod_timer(&ops->cursor_timer, jiffies + HZ/5);
+ }
+
+diff -Nur linux-3.10.30.orig/drivers/video/Kconfig linux-linaro-stable-mx6/drivers/video/Kconfig
+--- linux-3.10.30.orig/drivers/video/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/Kconfig 2014-05-15 20:34:09.234094818 +0200
+@@ -39,6 +39,11 @@
+ config HDMI
+ bool
+
++config VEXPRESS_DVI_CONTROL
++ bool "Versatile Express DVI control"
++ depends on FB && VEXPRESS_CONFIG
++ default y
++
+ menuconfig FB
+ tristate "Support for frame buffer devices"
+ ---help---
+@@ -312,7 +317,8 @@
+
+ config FB_ARMCLCD
+ tristate "ARM PrimeCell PL110 support"
+- depends on FB && ARM && ARM_AMBA
++ depends on ARM || ARM64 || COMPILE_TEST
++ depends on FB && ARM_AMBA
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+@@ -326,6 +332,21 @@
+ here and read <file:Documentation/kbuild/modules.txt>. The module
+ will be called amba-clcd.
+
++config FB_ARMHDLCD
++ tristate "ARM High Definition LCD support"
++ depends on FB && ARM
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ help
++ This framebuffer device driver is for the ARM High Definition
++ Colour LCD controller.
++
++ If you want to compile this as a module (=code which can be
++ inserted into and removed from the running kernel), say M
++ here and read <file:Documentation/kbuild/modules.txt>. The module
++ will be called arm-hdlcd.
++
+ config FB_ACORN
+ bool "Acorn VIDC support"
+ depends on (FB = y) && ARM && ARCH_ACORN
+@@ -2424,7 +2445,7 @@
+
+ config FB_MXS
+ tristate "MXS LCD framebuffer support"
+- depends on FB && ARCH_MXS
++ depends on FB && (ARCH_MXS || ARCH_MXC)
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+@@ -2476,6 +2497,10 @@
+ source "drivers/video/mmp/Kconfig"
+ source "drivers/video/backlight/Kconfig"
+
++if ARCH_MXC
++source "drivers/video/mxc/Kconfig"
++endif
++
+ if VT
+ source "drivers/video/console/Kconfig"
+ endif
+diff -Nur linux-3.10.30.orig/drivers/video/Makefile linux-linaro-stable-mx6/drivers/video/Makefile
+--- linux-3.10.30.orig/drivers/video/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/Makefile 2014-05-15 20:34:09.234094818 +0200
+@@ -53,6 +53,7 @@
+ obj-$(CONFIG_FB_SAVAGE) += savage/
+ obj-$(CONFIG_FB_GEODE) += geode/
+ obj-$(CONFIG_FB_MBX) += mbx/
++obj-$(CONFIG_FB_MXC) += mxc/
+ obj-$(CONFIG_FB_NEOMAGIC) += neofb.o
+ obj-$(CONFIG_FB_3DFX) += tdfxfb.o
+ obj-$(CONFIG_FB_CONTROL) += controlfb.o
+@@ -99,6 +100,7 @@
+ obj-$(CONFIG_FB_PVR2) += pvr2fb.o
+ obj-$(CONFIG_FB_VOODOO1) += sstfb.o
+ obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o
++obj-$(CONFIG_FB_ARMHDLCD) += arm-hdlcd.o
+ obj-$(CONFIG_FB_GOLDFISH) += goldfishfb.o
+ obj-$(CONFIG_FB_68328) += 68328fb.o
+ obj-$(CONFIG_FB_GBE) += gbefb.o
+@@ -177,3 +179,6 @@
+ ifeq ($(CONFIG_OF),y)
+ obj-$(CONFIG_VIDEOMODE_HELPERS) += of_display_timing.o of_videomode.o
+ endif
++
++# platform specific output drivers
++obj-$(CONFIG_VEXPRESS_DVI_CONTROL) += vexpress-dvi.o
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/epdc_regs.h linux-linaro-stable-mx6/drivers/video/mxc/epdc_regs.h
+--- linux-3.10.30.orig/drivers/video/mxc/epdc_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/epdc_regs.h 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,442 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef __EPDC_REGS_INCLUDED__
++#define __EPDC_REGS_INCLUDED__
++
++extern void __iomem *epdc_base;
++
++/*************************************
++ * Register addresses
++ **************************************/
++
++#define EPDC_CTRL (epdc_base + 0x000)
++#define EPDC_CTRL_SET (epdc_base + 0x004)
++#define EPDC_CTRL_CLEAR (epdc_base + 0x008)
++#define EPDC_CTRL_TOGGLE (epdc_base + 0x00C)
++#define EPDC_WVADDR (epdc_base + 0x020)
++#define EPDC_WB_ADDR (epdc_base + 0x030)
++#define EPDC_RES (epdc_base + 0x040)
++#define EPDC_FORMAT (epdc_base + 0x050)
++#define EPDC_FORMAT_SET (epdc_base + 0x054)
++#define EPDC_FORMAT_CLEAR (epdc_base + 0x058)
++#define EPDC_FORMAT_TOGGLE (epdc_base + 0x05C)
++#define EPDC_FIFOCTRL (epdc_base + 0x0A0)
++#define EPDC_FIFOCTRL_SET (epdc_base + 0x0A4)
++#define EPDC_FIFOCTRL_CLEAR (epdc_base + 0x0A8)
++#define EPDC_FIFOCTRL_TOGGLE (epdc_base + 0x0AC)
++#define EPDC_UPD_ADDR (epdc_base + 0x100)
++#define EPDC_UPD_STRIDE (epdc_base + 0x110)
++#define EPDC_UPD_CORD (epdc_base + 0x120)
++#define EPDC_UPD_SIZE (epdc_base + 0x140)
++#define EPDC_UPD_CTRL (epdc_base + 0x160)
++#define EPDC_UPD_FIXED (epdc_base + 0x180)
++#define EPDC_TEMP (epdc_base + 0x1A0)
++#define EPDC_AUTOWV_LUT (epdc_base + 0x1C0)
++#define EPDC_TCE_CTRL (epdc_base + 0x200)
++#define EPDC_TCE_SDCFG (epdc_base + 0x220)
++#define EPDC_TCE_GDCFG (epdc_base + 0x240)
++#define EPDC_TCE_HSCAN1 (epdc_base + 0x260)
++#define EPDC_TCE_HSCAN2 (epdc_base + 0x280)
++#define EPDC_TCE_VSCAN (epdc_base + 0x2A0)
++#define EPDC_TCE_OE (epdc_base + 0x2C0)
++#define EPDC_TCE_POLARITY (epdc_base + 0x2E0)
++#define EPDC_TCE_TIMING1 (epdc_base + 0x300)
++#define EPDC_TCE_TIMING2 (epdc_base + 0x310)
++#define EPDC_TCE_TIMING3 (epdc_base + 0x320)
++#define EPDC_PIGEON_CTRL0 (epdc_base + 0x380)
++#define EPDC_PIGEON_CTRL1 (epdc_base + 0x390)
++#define EPDC_IRQ_MASK1 (epdc_base + 0x3C0)
++#define EPDC_IRQ_MASK1_SET (epdc_base + 0x3C4)
++#define EPDC_IRQ_MASK1_CLEAR (epdc_base + 0x3C8)
++#define EPDC_IRQ_MASK1_TOGGLE (epdc_base + 0x3CC)
++#define EPDC_IRQ_MASK2 (epdc_base + 0x3D0)
++#define EPDC_IRQ_MASK2_SET (epdc_base + 0x3D4)
++#define EPDC_IRQ_MASK2_CLEAR (epdc_base + 0x3D8)
++#define EPDC_IRQ_MASK2_TOGGLE (epdc_base + 0x3DC)
++#define EPDC_IRQ1 (epdc_base + 0x3E0)
++#define EPDC_IRQ1_SET (epdc_base + 0x3E4)
++#define EPDC_IRQ1_CLEAR (epdc_base + 0x3E8)
++#define EPDC_IRQ1_TOGGLE (epdc_base + 0x3EC)
++#define EPDC_IRQ2 (epdc_base + 0x3F0)
++#define EPDC_IRQ2_SET (epdc_base + 0x3F4)
++#define EPDC_IRQ2_CLEAR (epdc_base + 0x3F8)
++#define EPDC_IRQ2_TOGGLE (epdc_base + 0x3FC)
++#define EPDC_IRQ_MASK (epdc_base + 0x400)
++#define EPDC_IRQ_MASK_SET (epdc_base + 0x404)
++#define EPDC_IRQ_MASK_CLEAR (epdc_base + 0x408)
++#define EPDC_IRQ_MASK_TOGGLE (epdc_base + 0x40C)
++#define EPDC_IRQ (epdc_base + 0x420)
++#define EPDC_IRQ_SET (epdc_base + 0x424)
++#define EPDC_IRQ_CLEAR (epdc_base + 0x428)
++#define EPDC_IRQ_TOGGLE (epdc_base + 0x42C)
++#define EPDC_STATUS_LUTS (epdc_base + 0x440)
++#define EPDC_STATUS_LUTS_SET (epdc_base + 0x444)
++#define EPDC_STATUS_LUTS_CLEAR (epdc_base + 0x448)
++#define EPDC_STATUS_LUTS_TOGGLE (epdc_base + 0x44C)
++#define EPDC_STATUS_LUTS2 (epdc_base + 0x450)
++#define EPDC_STATUS_LUTS2_SET (epdc_base + 0x454)
++#define EPDC_STATUS_LUTS2_CLEAR (epdc_base + 0x458)
++#define EPDC_STATUS_LUTS2_TOGGLE (epdc_base + 0x45C)
++#define EPDC_STATUS_NEXTLUT (epdc_base + 0x460)
++#define EPDC_STATUS_COL (epdc_base + 0x480)
++#define EPDC_STATUS_COL2 (epdc_base + 0x490)
++#define EPDC_STATUS (epdc_base + 0x4A0)
++#define EPDC_STATUS_SET (epdc_base + 0x4A4)
++#define EPDC_STATUS_CLEAR (epdc_base + 0x4A8)
++#define EPDC_STATUS_TOGGLE (epdc_base + 0x4AC)
++#define EPDC_UPD_COL_CORD (epdc_base + 0x4C0)
++#define EPDC_UPD_COL_SIZE (epdc_base + 0x4E0)
++#define EPDC_DEBUG (epdc_base + 0x500)
++#define EPDC_DEBUG_LUT (epdc_base + 0x530)
++#define EPDC_HIST1_PARAM (epdc_base + 0x600)
++#define EPDC_HIST2_PARAM (epdc_base + 0x610)
++#define EPDC_HIST4_PARAM (epdc_base + 0x620)
++#define EPDC_HIST8_PARAM0 (epdc_base + 0x630)
++#define EPDC_HIST8_PARAM1 (epdc_base + 0x640)
++#define EPDC_HIST16_PARAM0 (epdc_base + 0x650)
++#define EPDC_HIST16_PARAM1 (epdc_base + 0x660)
++#define EPDC_HIST16_PARAM2 (epdc_base + 0x670)
++#define EPDC_HIST16_PARAM3 (epdc_base + 0x680)
++#define EPDC_GPIO (epdc_base + 0x700)
++#define EPDC_VERSION (epdc_base + 0x7F0)
++#define EPDC_PIGEON_0_0 (epdc_base + 0x800)
++#define EPDC_PIGEON_0_1 (epdc_base + 0x810)
++#define EPDC_PIGEON_0_2 (epdc_base + 0x820)
++#define EPDC_PIGEON_1_0 (epdc_base + 0x840)
++#define EPDC_PIGEON_1_1 (epdc_base + 0x850)
++#define EPDC_PIGEON_1_2 (epdc_base + 0x860)
++#define EPDC_PIGEON_2_0 (epdc_base + 0x880)
++#define EPDC_PIGEON_2_1 (epdc_base + 0x890)
++#define EPDC_PIGEON_2_2 (epdc_base + 0x8A0)
++#define EPDC_PIGEON_3_0 (epdc_base + 0x8C0)
++#define EPDC_PIGEON_3_1 (epdc_base + 0x8D0)
++#define EPDC_PIGEON_3_2 (epdc_base + 0x8E0)
++#define EPDC_PIGEON_4_0 (epdc_base + 0x900)
++#define EPDC_PIGEON_4_1 (epdc_base + 0x910)
++#define EPDC_PIGEON_4_2 (epdc_base + 0x920)
++#define EPDC_PIGEON_5_0 (epdc_base + 0x940)
++#define EPDC_PIGEON_5_1 (epdc_base + 0x950)
++#define EPDC_PIGEON_5_2 (epdc_base + 0x960)
++#define EPDC_PIGEON_6_0 (epdc_base + 0x980)
++#define EPDC_PIGEON_6_1 (epdc_base + 0x990)
++#define EPDC_PIGEON_6_2 (epdc_base + 0x9A0)
++#define EPDC_PIGEON_7_0 (epdc_base + 0x9C0)
++#define EPDC_PIGEON_7_1 (epdc_base + 0x9D0)
++#define EPDC_PIGEON_7_2 (epdc_base + 0x9E0)
++#define EPDC_PIGEON_8_0 (epdc_base + 0xA00)
++#define EPDC_PIGEON_8_1 (epdc_base + 0xA10)
++#define EPDC_PIGEON_8_2 (epdc_base + 0xA20)
++#define EPDC_PIGEON_9_0 (epdc_base + 0xA40)
++#define EPDC_PIGEON_9_1 (epdc_base + 0xA50)
++#define EPDC_PIGEON_9_2 (epdc_base + 0xA60)
++#define EPDC_PIGEON_10_0 (epdc_base + 0xA80)
++#define EPDC_PIGEON_10_1 (epdc_base + 0xA90)
++#define EPDC_PIGEON_10_2 (epdc_base + 0xAA0)
++#define EPDC_PIGEON_11_0 (epdc_base + 0xAC0)
++#define EPDC_PIGEON_11_1 (epdc_base + 0xAD0)
++#define EPDC_PIGEON_11_2 (epdc_base + 0xAE0)
++#define EPDC_PIGEON_12_0 (epdc_base + 0xB00)
++#define EPDC_PIGEON_12_1 (epdc_base + 0xB10)
++#define EPDC_PIGEON_12_2 (epdc_base + 0xB20)
++#define EPDC_PIGEON_13_0 (epdc_base + 0xB40)
++#define EPDC_PIGEON_13_1 (epdc_base + 0xB50)
++#define EPDC_PIGEON_13_2 (epdc_base + 0xB60)
++#define EPDC_PIGEON_14_0 (epdc_base + 0xB80)
++#define EPDC_PIGEON_14_1 (epdc_base + 0xB90)
++#define EPDC_PIGEON_14_2 (epdc_base + 0xBA0)
++#define EPDC_PIGEON_15_0 (epdc_base + 0xBC0)
++#define EPDC_PIGEON_15_1 (epdc_base + 0xBD0)
++#define EPDC_PIGEON_15_2 (epdc_base + 0xBE0)
++#define EPDC_WB_ADDR_TCE (epdc_base + 0xC10)
++
++/*
++ * Register field definitions
++ */
++
++enum {
++/* EPDC_CTRL field values */
++ EPDC_CTRL_SFTRST = 0x80000000,
++ EPDC_CTRL_CLKGATE = 0x40000000,
++ EPDC_CTRL_SRAM_POWERDOWN = 0x100,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
++ EPDC_CTRL_BURST_LEN_8_8 = 0x1,
++ EPDC_CTRL_BURST_LEN_8_16 = 0,
++
++/* EPDC_RES field values */
++ EPDC_RES_VERTICAL_MASK = 0x1FFF0000,
++ EPDC_RES_VERTICAL_OFFSET = 16,
++ EPDC_RES_HORIZONTAL_MASK = 0x1FFF,
++ EPDC_RES_HORIZONTAL_OFFSET = 0,
++
++/* EPDC_FORMAT field values */
++ EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
++ EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000,
++ EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK = 0x700,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
++ EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
++ EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
++ EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
++ EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
++
++/* EPDC_FIFOCTRL field values */
++ EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
++ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000,
++ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
++ EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00,
++ EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
++ EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF,
++ EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
++
++/* EPDC_UPD_CORD field values */
++ EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000,
++ EPDC_UPD_CORD_YCORD_OFFSET = 16,
++ EPDC_UPD_CORD_XCORD_MASK = 0x1FFF,
++ EPDC_UPD_CORD_XCORD_OFFSET = 0,
++
++/* EPDC_UPD_SIZE field values */
++ EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000,
++ EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
++ EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF,
++ EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
++
++/* EPDC_UPD_CTRL field values */
++ EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
++ EPDC_UPD_CTRL_LUT_SEL_MASK = 0x3F0000,
++ EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
++ EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00,
++ EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
++ EPDC_UPD_CTRL_AUTOWV_PAUSE = 0x8,
++ EPDC_UPD_CTRL_AUTOWV = 0x4,
++ EPDC_UPD_CTRL_DRY_RUN = 0x2,
++ EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
++
++/* EPDC_UPD_FIXED field values */
++ EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
++ EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
++ EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00,
++ EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
++ EPDC_UPD_FIXED_FIXCP_MASK = 0xFF,
++ EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
++
++/* EPDC_AUTOWV_LUT field values */
++ EPDC_AUTOWV_LUT_DATA_MASK = 0xFF0000,
++ EPDC_AUTOWV_LUT_DATA_OFFSET = 16,
++ EPDC_AUTOWV_LUT_ADDR_MASK = 0xFF,
++ EPDC_AUTOWV_LUT_ADDR_OFFSET = 0,
++
++/* EPDC_TCE_CTRL field values */
++ EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000,
++ EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
++ EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00,
++ EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
++ EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
++ EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
++ EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
++ EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
++ EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
++ EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
++ EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
++ EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
++ EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
++ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
++ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
++ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
++
++/* EPDC_TCE_SDCFG field values */
++ EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
++ EPDC_TCE_SDCFG_SDSHR = 0x100000,
++ EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000,
++ EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
++ EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
++ EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
++ EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
++ EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF,
++ EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
++
++/* EPDC_TCE_GDCFG field values */
++ EPDC_TCE_SDCFG_GDRL = 0x10,
++ EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
++ EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
++ EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
++
++/* EPDC_TCE_HSCAN1 field values */
++ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000,
++ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
++ EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF,
++ EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
++
++/* EPDC_TCE_HSCAN2 field values */
++ EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000,
++ EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
++ EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF,
++ EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
++
++/* EPDC_TCE_VSCAN field values */
++ EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000,
++ EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
++ EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00,
++ EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
++ EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF,
++ EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
++
++/* EPDC_TCE_OE field values */
++ EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000,
++ EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
++ EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000,
++ EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
++ EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00,
++ EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
++ EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF,
++ EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
++
++/* EPDC_TCE_POLARITY field values */
++ EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
++ EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
++ EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
++ EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
++ EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
++
++/* EPDC_TCE_TIMING1 field values */
++ EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
++ EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
++ EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
++ EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
++ EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
++ EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
++ EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
++ EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
++ EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
++
++/* EPDC_TCE_TIMING2 field values */
++ EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000,
++ EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
++ EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF,
++ EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
++
++/* EPDC_TCE_TIMING3 field values */
++ EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000,
++ EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
++ EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF,
++ EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
++
++/* EPDC_IRQ_MASK/EPDC_IRQ field values */
++ EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
++ EPDC_IRQ_LUT_COL_IRQ = 0x20000,
++ EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
++ EPDC_IRQ_FRAME_END_IRQ = 0x80000,
++ EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
++ EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
++ EPDC_IRQ_UPD_DONE_IRQ = 0x400000,
++ EPDC_IRQ_PWR_IRQ = 0x800000,
++
++/* EPDC_STATUS_NEXTLUT field values */
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0x3F,
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
++
++/* EPDC_STATUS field values */
++ EPDC_STATUS_HISTOGRAM_CP_MASK = 0x1F0000,
++ EPDC_STATUS_HISTOGRAM_CP_OFFSET = 16,
++ EPDC_STATUS_HISTOGRAM_NP_MASK = 0x1F00,
++ EPDC_STATUS_HISTOGRAM_NP_OFFSET = 8,
++ EPDC_STATUS_UPD_VOID = 0x8,
++ EPDC_STATUS_LUTS_UNDERRUN = 0x4,
++ EPDC_STATUS_LUTS_BUSY = 0x2,
++ EPDC_STATUS_WB_BUSY = 0x1,
++
++/* EPDC_UPD_COL_CORD field values */
++ EPDC_UPD_COL_CORD_YCORD_MASK = 0x1FFF0000,
++ EPDC_UPD_COL_CORD_YCORD_OFFSET = 16,
++ EPDC_UPD_COL_CORD_XCORD_MASK = 0x1FFF,
++ EPDC_UPD_COL_CORD_XCORD_OFFSET = 0,
++
++/* EPDC_UPD_COL_SIZE field values */
++ EPDC_UPD_COL_SIZE_HEIGHT_MASK = 0x1FFF0000,
++ EPDC_UPD_COL_SIZE_HEIGHT_OFFSET = 16,
++ EPDC_UPD_COL_SIZE_WIDTH_MASK = 0x1FFF,
++ EPDC_UPD_COL_SIZE_WIDTH_OFFSET = 0,
++
++/* EPDC_DEBUG field values */
++ EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
++ EPDC_DEBUG_COLLISION_OFF = 0x1,
++
++/* EPDC_HISTx_PARAM field values */
++ EPDC_HIST_PARAM_VALUE0_MASK = 0x1F,
++ EPDC_HIST_PARAM_VALUE0_OFFSET = 0,
++ EPDC_HIST_PARAM_VALUE1_MASK = 0x1F00,
++ EPDC_HIST_PARAM_VALUE1_OFFSET = 8,
++ EPDC_HIST_PARAM_VALUE2_MASK = 0x1F0000,
++ EPDC_HIST_PARAM_VALUE2_OFFSET = 16,
++ EPDC_HIST_PARAM_VALUE3_MASK = 0x1F000000,
++ EPDC_HIST_PARAM_VALUE3_OFFSET = 24,
++ EPDC_HIST_PARAM_VALUE4_MASK = 0x1F,
++ EPDC_HIST_PARAM_VALUE4_OFFSET = 0,
++ EPDC_HIST_PARAM_VALUE5_MASK = 0x1F00,
++ EPDC_HIST_PARAM_VALUE5_OFFSET = 8,
++ EPDC_HIST_PARAM_VALUE6_MASK = 0x1F0000,
++ EPDC_HIST_PARAM_VALUE6_OFFSET = 16,
++ EPDC_HIST_PARAM_VALUE7_MASK = 0x1F000000,
++ EPDC_HIST_PARAM_VALUE7_OFFSET = 24,
++ EPDC_HIST_PARAM_VALUE8_MASK = 0x1F,
++ EPDC_HIST_PARAM_VALUE8_OFFSET = 0,
++ EPDC_HIST_PARAM_VALUE9_MASK = 0x1F00,
++ EPDC_HIST_PARAM_VALUE9_OFFSET = 8,
++ EPDC_HIST_PARAM_VALUE10_MASK = 0x1F0000,
++ EPDC_HIST_PARAM_VALUE10_OFFSET = 16,
++ EPDC_HIST_PARAM_VALUE11_MASK = 0x1F000000,
++ EPDC_HIST_PARAM_VALUE11_OFFSET = 24,
++ EPDC_HIST_PARAM_VALUE12_MASK = 0x1F,
++ EPDC_HIST_PARAM_VALUE12_OFFSET = 0,
++ EPDC_HIST_PARAM_VALUE13_MASK = 0x1F00,
++ EPDC_HIST_PARAM_VALUE13_OFFSET = 8,
++ EPDC_HIST_PARAM_VALUE14_MASK = 0x1F0000,
++ EPDC_HIST_PARAM_VALUE14_OFFSET = 16,
++ EPDC_HIST_PARAM_VALUE15_MASK = 0x1F000000,
++ EPDC_HIST_PARAM_VALUE15_OFFSET = 24,
++
++/* EPDC_GPIO field values */
++ EPDC_GPIO_PWRCOM = 0x40,
++ EPDC_GPIO_PWRCTRL_MASK = 0x3C,
++ EPDC_GPIO_PWRCTRL_OFFSET = 2,
++ EPDC_GPIO_BDR_MASK = 0x3,
++ EPDC_GPIO_BDR_OFFSET = 0,
++
++/* EPDC_VERSION field values */
++ EPDC_VERSION_MAJOR_MASK = 0xFF000000,
++ EPDC_VERSION_MAJOR_OFFSET = 24,
++ EPDC_VERSION_MINOR_MASK = 0xFF0000,
++ EPDC_VERSION_MINOR_OFFSET = 16,
++ EPDC_VERSION_STEP_MASK = 0xFFFF,
++ EPDC_VERSION_STEP_OFFSET = 0,
++};
++
++#endif /* __EPDC_REGS_INCLUDED__ */
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/Kconfig linux-linaro-stable-mx6/drivers/video/mxc/Kconfig
+--- linux-3.10.30.orig/drivers/video/mxc/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/Kconfig 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,63 @@
++config FB_MXC
++ tristate "MXC Framebuffer support"
++ depends on FB
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MODE_HELPERS
++ default y
++ help
++ This is a framebuffer device for the MXC LCD Controller.
++ See <http://www.linux-fbdev.org/> for information on framebuffer
++ devices.
++
++ If you plan to use the LCD display with your MXC system, say
++ Y here.
++
++config FB_MXC_SYNC_PANEL
++ depends on FB_MXC
++ tristate "Synchronous Panel Framebuffer"
++
++config FB_MXC_LDB
++ tristate "MXC LDB"
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3
++
++config FB_MXC_MIPI_DSI
++ tristate "MXC MIPI_DSI"
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3
++
++config FB_MXC_TRULY_WVGA_SYNC_PANEL
++ tristate "TRULY WVGA Panel"
++ depends on FB_MXC_SYNC_PANEL
++ depends on FB_MXC_MIPI_DSI
++
++config FB_MXC_HDMI
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3
++ depends on I2C
++ tristate "MXC HDMI driver support"
++ select MFD_MXC_HDMI
++ help
++ Driver for the on-chip MXC HDMI controller.
++
++config FB_MXC_EDID
++ depends on FB_MXC && I2C
++ tristate "MXC EDID support"
++ default y
++
++config FB_MXC_EINK_PANEL
++ depends on FB_MXC
++ depends on DMA_ENGINE
++ select FB_DEFERRED_IO
++ tristate "E-Ink Panel Framebuffer"
++
++config FB_MXC_EINK_AUTO_UPDATE_MODE
++ bool "E-Ink Auto-update Mode Support"
++ default n
++ depends on FB_MXC_EINK_PANEL
++
++config FB_MXS_SII902X
++ tristate "Si Image SII9022 DVI/HDMI Interface Chip"
++ depends on FB_MXS && I2C
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/ldb.c linux-linaro-stable-mx6/drivers/video/mxc/ldb.c
+--- linux-3.10.30.orig/drivers/video/mxc/ldb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/ldb.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,1036 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file mxc_ldb.c
++ *
++ * @brief This file contains the LDB driver device interface and fops
++ * functions.
++ */
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/ipu.h>
++#include <linux/mxcfb.h>
++#include <linux/regulator/consumer.h>
++#include <linux/spinlock.h>
++#include <linux/of_device.h>
++#include <linux/mod_devicetable.h>
++#include "mxc_dispdrv.h"
++
++#define DISPDRV_LDB "ldb"
++
++#define LDB_BGREF_RMODE_MASK 0x00008000
++#define LDB_BGREF_RMODE_INT 0x00008000
++#define LDB_BGREF_RMODE_EXT 0x0
++
++#define LDB_DI1_VS_POL_MASK 0x00000400
++#define LDB_DI1_VS_POL_ACT_LOW 0x00000400
++#define LDB_DI1_VS_POL_ACT_HIGH 0x0
++#define LDB_DI0_VS_POL_MASK 0x00000200
++#define LDB_DI0_VS_POL_ACT_LOW 0x00000200
++#define LDB_DI0_VS_POL_ACT_HIGH 0x0
++
++#define LDB_BIT_MAP_CH1_MASK 0x00000100
++#define LDB_BIT_MAP_CH1_JEIDA 0x00000100
++#define LDB_BIT_MAP_CH1_SPWG 0x0
++#define LDB_BIT_MAP_CH0_MASK 0x00000040
++#define LDB_BIT_MAP_CH0_JEIDA 0x00000040
++#define LDB_BIT_MAP_CH0_SPWG 0x0
++
++#define LDB_DATA_WIDTH_CH1_MASK 0x00000080
++#define LDB_DATA_WIDTH_CH1_24 0x00000080
++#define LDB_DATA_WIDTH_CH1_18 0x0
++#define LDB_DATA_WIDTH_CH0_MASK 0x00000020
++#define LDB_DATA_WIDTH_CH0_24 0x00000020
++#define LDB_DATA_WIDTH_CH0_18 0x0
++
++#define LDB_CH1_MODE_MASK 0x0000000C
++#define LDB_CH1_MODE_EN_TO_DI1 0x0000000C
++#define LDB_CH1_MODE_EN_TO_DI0 0x00000004
++#define LDB_CH1_MODE_DISABLE 0x0
++#define LDB_CH0_MODE_MASK 0x00000003
++#define LDB_CH0_MODE_EN_TO_DI1 0x00000003
++#define LDB_CH0_MODE_EN_TO_DI0 0x00000001
++#define LDB_CH0_MODE_DISABLE 0x0
++
++#define LDB_SPLIT_MODE_EN 0x00000010
++
++enum {
++ IMX6_LDB,
++};
++
++enum {
++ LDB_IMX6 = 1,
++};
++
++struct fsl_mxc_ldb_platform_data {
++ int devtype;
++ u32 ext_ref;
++#define LDB_SPL_DI0 1
++#define LDB_SPL_DI1 2
++#define LDB_DUL_DI0 3
++#define LDB_DUL_DI1 4
++#define LDB_SIN0 5
++#define LDB_SIN1 6
++#define LDB_SEP0 7
++#define LDB_SEP1 8
++ int mode;
++ int ipu_id;
++ int disp_id;
++
++ /*only work for separate mode*/
++ int sec_ipu_id;
++ int sec_disp_id;
++};
++
++struct ldb_data {
++ struct platform_device *pdev;
++ struct mxc_dispdrv_handle *disp_ldb;
++ uint32_t *reg;
++ uint32_t *control_reg;
++ uint32_t *gpr3_reg;
++ uint32_t control_reg_data;
++ struct regulator *lvds_bg_reg;
++ int mode;
++ bool inited;
++ struct ldb_setting {
++ struct clk *di_clk;
++ struct clk *ldb_di_clk;
++ struct clk *div_3_5_clk;
++ struct clk *div_7_clk;
++ struct clk *div_sel_clk;
++ bool active;
++ bool clk_en;
++ int ipu;
++ int di;
++ uint32_t ch_mask;
++ uint32_t ch_val;
++ } setting[2];
++ struct notifier_block nb;
++};
++
++static int g_ldb_mode;
++
++static struct fb_videomode ldb_modedb[] = {
++ {
++ "LDB-WXGA", 60, 1280, 800, 14065,
++ 40, 40,
++ 10, 3,
++ 80, 10,
++ 0,
++ FB_VMODE_NONINTERLACED,
++ FB_MODE_IS_DETAILED,},
++ {
++ "LDB-XGA", 60, 1024, 768, 15385,
++ 220, 40,
++ 21, 7,
++ 60, 10,
++ 0,
++ FB_VMODE_NONINTERLACED,
++ FB_MODE_IS_DETAILED,},
++ {
++ "LDB-1080P60", 60, 1920, 1080, 7692,
++ 100, 40,
++ 30, 3,
++ 10, 2,
++ 0,
++ FB_VMODE_NONINTERLACED,
++ FB_MODE_IS_DETAILED,},
++};
++static int ldb_modedb_sz = ARRAY_SIZE(ldb_modedb);
++
++static inline int is_imx6_ldb(struct fsl_mxc_ldb_platform_data *plat_data)
++{
++ return (plat_data->devtype == LDB_IMX6);
++}
++
++static int bits_per_pixel(int pixel_fmt)
++{
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ return 24;
++ break;
++ case IPU_PIX_FMT_BGR666:
++ case IPU_PIX_FMT_RGB666:
++ case IPU_PIX_FMT_LVDS666:
++ return 18;
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++static int valid_mode(int pixel_fmt)
++{
++ return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR24) ||
++ (pixel_fmt == IPU_PIX_FMT_LVDS666) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB666) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR666));
++}
++
++static int parse_ldb_mode(char *mode)
++{
++ int ldb_mode;
++
++ if (!strcmp(mode, "spl0"))
++ ldb_mode = LDB_SPL_DI0;
++ else if (!strcmp(mode, "spl1"))
++ ldb_mode = LDB_SPL_DI1;
++ else if (!strcmp(mode, "dul0"))
++ ldb_mode = LDB_DUL_DI0;
++ else if (!strcmp(mode, "dul1"))
++ ldb_mode = LDB_DUL_DI1;
++ else if (!strcmp(mode, "sin0"))
++ ldb_mode = LDB_SIN0;
++ else if (!strcmp(mode, "sin1"))
++ ldb_mode = LDB_SIN1;
++ else if (!strcmp(mode, "sep0"))
++ ldb_mode = LDB_SEP0;
++ else if (!strcmp(mode, "sep1"))
++ ldb_mode = LDB_SEP1;
++ else
++ ldb_mode = -EINVAL;
++
++ return ldb_mode;
++}
++
++#ifndef MODULE
++/*
++ * "ldb=spl0/1" -- split mode on DI0/1
++ * "ldb=dul0/1" -- dual mode on DI0/1
++ * "ldb=sin0/1" -- single mode on LVDS0/1
++ * "ldb=sep0/1" -- separate mode begin from LVDS0/1
++ *
++ * there are two LVDS channels(LVDS0 and LVDS1) which can transfer video
++ * datas, there two channels can be used as split/dual/single/separate mode.
++ *
++ * split mode means display data from DI0 or DI1 will send to both channels
++ * LVDS0+LVDS1.
++ * dual mode means display data from DI0 or DI1 will be duplicated on LVDS0
++ * and LVDS1, it said, LVDS0 and LVDS1 has the same content.
++ * single mode means only work for DI0/DI1->LVDS0 or DI0/DI1->LVDS1.
++ * separate mode means you can make DI0/DI1->LVDS0 and DI0/DI1->LVDS1 work
++ * at the same time.
++ */
++static int __init ldb_setup(char *options)
++{
++ g_ldb_mode = parse_ldb_mode(options);
++ return (g_ldb_mode < 0) ? 0 : 1;
++}
++__setup("ldb=", ldb_setup);
++#endif
++
++static int ldb_get_of_property(struct platform_device *pdev,
++ struct fsl_mxc_ldb_platform_data *plat_data)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++ u32 ipu_id, disp_id;
++ u32 sec_ipu_id, sec_disp_id;
++ char *mode;
++ u32 ext_ref;
++
++ err = of_property_read_string(np, "mode", (const char **)&mode);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property mode fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "ext_ref", &ext_ref);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ext_ref fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "disp_id", &disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "sec_ipu_id", &sec_ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property sec_ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "sec_disp_id", &sec_disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property sec_disp_id fail\n");
++ return err;
++ }
++
++ plat_data->mode = parse_ldb_mode(mode);
++ plat_data->ext_ref = ext_ref;
++ plat_data->ipu_id = ipu_id;
++ plat_data->disp_id = disp_id;
++ plat_data->sec_ipu_id = sec_ipu_id;
++ plat_data->sec_disp_id = sec_disp_id;
++
++ return err;
++}
++
++static int find_ldb_setting(struct ldb_data *ldb, struct fb_info *fbi)
++{
++ char *id_di[] = {
++ "DISP3 BG",
++ "DISP3 BG - DI1",
++ };
++ char id[16];
++ int i;
++
++ for (i = 0; i < 2; i++) {
++ if (ldb->setting[i].active) {
++ memset(id, 0, 16);
++ memcpy(id, id_di[ldb->setting[i].di],
++ strlen(id_di[ldb->setting[i].di]));
++ id[4] += ldb->setting[i].ipu;
++ if (!strcmp(id, fbi->fix.id))
++ return i;
++ }
++ }
++ return -EINVAL;
++}
++
++static int ldb_disp_setup(struct mxc_dispdrv_handle *disp, struct fb_info *fbi)
++{
++ uint32_t reg, val;
++ uint32_t pixel_clk, rounded_pixel_clk;
++ struct clk *ldb_clk_parent;
++ struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
++ int setting_idx, di;
++ int ret;
++
++ setting_idx = find_ldb_setting(ldb, fbi);
++ if (setting_idx < 0)
++ return setting_idx;
++
++ di = ldb->setting[setting_idx].di;
++
++ /* restore channel mode setting */
++ val = readl(ldb->control_reg);
++ val |= ldb->setting[setting_idx].ch_val;
++ writel(val, ldb->control_reg);
++ dev_dbg(&ldb->pdev->dev, "LDB setup, control reg:0x%x\n",
++ readl(ldb->control_reg));
++
++ /* vsync setup */
++ reg = readl(ldb->control_reg);
++ if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) {
++ if (di == 0)
++ reg = (reg & ~LDB_DI0_VS_POL_MASK)
++ | LDB_DI0_VS_POL_ACT_HIGH;
++ else
++ reg = (reg & ~LDB_DI1_VS_POL_MASK)
++ | LDB_DI1_VS_POL_ACT_HIGH;
++ } else {
++ if (di == 0)
++ reg = (reg & ~LDB_DI0_VS_POL_MASK)
++ | LDB_DI0_VS_POL_ACT_LOW;
++ else
++ reg = (reg & ~LDB_DI1_VS_POL_MASK)
++ | LDB_DI1_VS_POL_ACT_LOW;
++ }
++ writel(reg, ldb->control_reg);
++
++ /* clk setup */
++ if (ldb->setting[setting_idx].clk_en)
++ clk_disable_unprepare(ldb->setting[setting_idx].ldb_di_clk);
++ pixel_clk = (PICOS2KHZ(fbi->var.pixclock)) * 1000UL;
++ ldb_clk_parent = clk_get_parent(ldb->setting[setting_idx].ldb_di_clk);
++ if (IS_ERR(ldb_clk_parent)) {
++ dev_err(&ldb->pdev->dev, "get ldb di parent clk fail\n");
++ return PTR_ERR(ldb_clk_parent);
++ }
++ if ((ldb->mode == LDB_SPL_DI0) || (ldb->mode == LDB_SPL_DI1))
++ ret = clk_set_rate(ldb_clk_parent, pixel_clk * 7 / 2);
++ else
++ ret = clk_set_rate(ldb_clk_parent, pixel_clk * 7);
++ if (ret < 0) {
++ dev_err(&ldb->pdev->dev, "set ldb parent clk fail:%d\n", ret);
++ return ret;
++ }
++ rounded_pixel_clk = clk_round_rate(ldb->setting[setting_idx].ldb_di_clk,
++ pixel_clk);
++ dev_dbg(&ldb->pdev->dev, "pixel_clk:%d, rounded_pixel_clk:%d\n",
++ pixel_clk, rounded_pixel_clk);
++ ret = clk_set_rate(ldb->setting[setting_idx].ldb_di_clk,
++ rounded_pixel_clk);
++ if (ret < 0) {
++ dev_err(&ldb->pdev->dev, "set ldb di clk fail:%d\n", ret);
++ return ret;
++ }
++ ret = clk_prepare_enable(ldb->setting[setting_idx].ldb_di_clk);
++ if (ret < 0) {
++ dev_err(&ldb->pdev->dev, "enable ldb di clk fail:%d\n", ret);
++ return ret;
++ }
++
++ if (!ldb->setting[setting_idx].clk_en)
++ ldb->setting[setting_idx].clk_en = true;
++
++ return 0;
++}
++
++int ldb_fb_event(struct notifier_block *nb, unsigned long val, void *v)
++{
++ struct ldb_data *ldb = container_of(nb, struct ldb_data, nb);
++ struct fb_event *event = v;
++ struct fb_info *fbi = event->info;
++ int index;
++ uint32_t data;
++
++ index = find_ldb_setting(ldb, fbi);
++ if (index < 0)
++ return 0;
++
++ fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var,
++ &fbi->modelist);
++
++ if (!fbi->mode) {
++ dev_warn(&ldb->pdev->dev,
++ "LDB: can not find mode for xres=%d, yres=%d\n",
++ fbi->var.xres, fbi->var.yres);
++ if (ldb->setting[index].clk_en) {
++ clk_disable(ldb->setting[index].ldb_di_clk);
++ ldb->setting[index].clk_en = false;
++ data = readl(ldb->control_reg);
++ data &= ~ldb->setting[index].ch_mask;
++ writel(data, ldb->control_reg);
++ }
++ return 0;
++ }
++
++ switch (val) {
++ case FB_EVENT_BLANK:
++ {
++ if (*((int *)event->data) == FB_BLANK_UNBLANK) {
++ if (!ldb->setting[index].clk_en) {
++ clk_enable(ldb->setting[index].ldb_di_clk);
++ ldb->setting[index].clk_en = true;
++ }
++ } else {
++ if (ldb->setting[index].clk_en) {
++ clk_disable(ldb->setting[index].ldb_di_clk);
++ ldb->setting[index].clk_en = false;
++ data = readl(ldb->control_reg);
++ data &= ~ldb->setting[index].ch_mask;
++ writel(data, ldb->control_reg);
++ dev_dbg(&ldb->pdev->dev,
++ "LDB blank, control reg:0x%x\n",
++ readl(ldb->control_reg));
++ }
++ }
++ break;
++ }
++ case FB_EVENT_SUSPEND:
++ if (ldb->setting[index].clk_en) {
++ clk_disable(ldb->setting[index].ldb_di_clk);
++ ldb->setting[index].clk_en = false;
++ }
++ break;
++ default:
++ break;
++ }
++ return 0;
++}
++
++#define LVDS_MUX_CTL_WIDTH 2
++#define LVDS_MUX_CTL_MASK 3
++#define LVDS0_MUX_CTL_OFFS 6
++#define LVDS1_MUX_CTL_OFFS 8
++#define LVDS0_MUX_CTL_MASK (LVDS_MUX_CTL_MASK << 6)
++#define LVDS1_MUX_CTL_MASK (LVDS_MUX_CTL_MASK << 8)
++#define ROUTE_IPU_DI(ipu, di) (((ipu << 1) | di) & LVDS_MUX_CTL_MASK)
++static int ldb_ipu_ldb_route(int ipu, int di, struct ldb_data *ldb)
++{
++ uint32_t reg;
++ int channel;
++ int shift;
++ int mode = ldb->mode;
++
++ reg = readl(ldb->gpr3_reg);
++ if (mode < LDB_SIN0) {
++ reg &= ~(LVDS0_MUX_CTL_MASK | LVDS1_MUX_CTL_MASK);
++ reg |= (ROUTE_IPU_DI(ipu, di) << LVDS0_MUX_CTL_OFFS) |
++ (ROUTE_IPU_DI(ipu, di) << LVDS1_MUX_CTL_OFFS);
++ dev_dbg(&ldb->pdev->dev,
++ "Dual/Split mode both channels route to IPU%d-DI%d\n",
++ ipu, di);
++ } else if ((mode == LDB_SIN0) || (mode == LDB_SIN1)) {
++ reg &= ~(LVDS0_MUX_CTL_MASK | LVDS1_MUX_CTL_MASK);
++ channel = mode - LDB_SIN0;
++ shift = LVDS0_MUX_CTL_OFFS + channel * LVDS_MUX_CTL_WIDTH;
++ reg |= ROUTE_IPU_DI(ipu, di) << shift;
++ dev_dbg(&ldb->pdev->dev,
++ "Single mode channel %d route to IPU%d-DI%d\n",
++ channel, ipu, di);
++ } else {
++ static bool first = true;
++
++ if (first) {
++ if (mode == LDB_SEP0) {
++ reg &= ~LVDS0_MUX_CTL_MASK;
++ channel = 0;
++ } else {
++ reg &= ~LVDS1_MUX_CTL_MASK;
++ channel = 1;
++ }
++ first = false;
++ } else {
++ if (mode == LDB_SEP0) {
++ reg &= ~LVDS1_MUX_CTL_MASK;
++ channel = 1;
++ } else {
++ reg &= ~LVDS0_MUX_CTL_MASK;
++ channel = 0;
++ }
++ }
++
++ shift = LVDS0_MUX_CTL_OFFS + channel * LVDS_MUX_CTL_WIDTH;
++ reg |= ROUTE_IPU_DI(ipu, di) << shift;
++
++ dev_dbg(&ldb->pdev->dev,
++ "Separate mode channel %d route to IPU%d-DI%d\n",
++ channel, ipu, di);
++ }
++ writel(reg, ldb->gpr3_reg);
++
++ return 0;
++}
++
++static int ldb_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret = 0, i, lvds_channel = 0;
++ struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
++ struct fsl_mxc_ldb_platform_data *plat_data = ldb->pdev->dev.platform_data;
++ struct resource *res;
++ uint32_t reg, setting_idx;
++ uint32_t ch_mask = 0, ch_val = 0;
++ uint32_t ipu_id, disp_id;
++ char di_clk[] = "ipu1_di0_sel";
++ char ldb_clk[] = "ldb_di0";
++ char div_3_5_clk[] = "di0_div_3_5";
++ char div_7_clk[] = "di0_div_7";
++ char div_sel_clk[] = "di0_div_sel";
++
++ /* if input format not valid, make RGB666 as default*/
++ if (!valid_mode(setting->if_fmt)) {
++ dev_warn(&ldb->pdev->dev, "Input pixel format not valid"
++ " use default RGB666\n");
++ setting->if_fmt = IPU_PIX_FMT_RGB666;
++ }
++
++ if (!ldb->inited) {
++ setting_idx = 0;
++ res = platform_get_resource(ldb->pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&ldb->pdev->dev, "get iomem fail.\n");
++ return -ENOMEM;
++ }
++
++ ldb->reg = devm_ioremap(&ldb->pdev->dev, res->start,
++ resource_size(res));
++ ldb->control_reg = ldb->reg + 2;
++ ldb->gpr3_reg = ldb->reg + 3;
++
++ /* ipu selected by platform data setting */
++ setting->dev_id = plat_data->ipu_id;
++
++ reg = readl(ldb->control_reg);
++
++ /* refrence resistor select */
++ reg &= ~LDB_BGREF_RMODE_MASK;
++ if (plat_data->ext_ref)
++ reg |= LDB_BGREF_RMODE_EXT;
++ else
++ reg |= LDB_BGREF_RMODE_INT;
++
++ /* TODO: now only use SPWG data mapping for both channel */
++ reg &= ~(LDB_BIT_MAP_CH0_MASK | LDB_BIT_MAP_CH1_MASK);
++ reg |= LDB_BIT_MAP_CH0_SPWG | LDB_BIT_MAP_CH1_SPWG;
++
++ /* channel mode setting */
++ reg &= ~(LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
++ reg &= ~(LDB_DATA_WIDTH_CH0_MASK | LDB_DATA_WIDTH_CH1_MASK);
++
++ if (bits_per_pixel(setting->if_fmt) == 24)
++ reg |= LDB_DATA_WIDTH_CH0_24 | LDB_DATA_WIDTH_CH1_24;
++ else
++ reg |= LDB_DATA_WIDTH_CH0_18 | LDB_DATA_WIDTH_CH1_18;
++
++ if (g_ldb_mode >= LDB_SPL_DI0)
++ ldb->mode = g_ldb_mode;
++ else
++ ldb->mode = plat_data->mode;
++
++ if ((ldb->mode == LDB_SIN0) || (ldb->mode == LDB_SIN1)) {
++ ret = ldb->mode - LDB_SIN0;
++ if (plat_data->disp_id != ret) {
++ dev_warn(&ldb->pdev->dev,
++ "change IPU DI%d to IPU DI%d for LDB "
++ "channel%d.\n",
++ plat_data->disp_id, ret, ret);
++ plat_data->disp_id = ret;
++ }
++ } else if (((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1))
++ && is_imx6_ldb(plat_data)) {
++ if (plat_data->disp_id == plat_data->sec_disp_id) {
++ dev_err(&ldb->pdev->dev,
++ "For LVDS separate mode,"
++ "two DIs should be different!\n");
++ return -EINVAL;
++ }
++
++ if (((!plat_data->disp_id) && (ldb->mode == LDB_SEP1))
++ || ((plat_data->disp_id) &&
++ (ldb->mode == LDB_SEP0))) {
++ dev_dbg(&ldb->pdev->dev,
++ "LVDS separate mode:"
++ "swap DI configuration!\n");
++ ipu_id = plat_data->ipu_id;
++ disp_id = plat_data->disp_id;
++ plat_data->ipu_id = plat_data->sec_ipu_id;
++ plat_data->disp_id = plat_data->sec_disp_id;
++ plat_data->sec_ipu_id = ipu_id;
++ plat_data->sec_disp_id = disp_id;
++ }
++ }
++
++ if (ldb->mode == LDB_SPL_DI0) {
++ reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI0
++ | LDB_CH1_MODE_EN_TO_DI0;
++ setting->disp_id = 0;
++ } else if (ldb->mode == LDB_SPL_DI1) {
++ reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI1
++ | LDB_CH1_MODE_EN_TO_DI1;
++ setting->disp_id = 1;
++ } else if (ldb->mode == LDB_DUL_DI0) {
++ reg &= ~LDB_SPLIT_MODE_EN;
++ reg |= LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI0;
++ setting->disp_id = 0;
++ } else if (ldb->mode == LDB_DUL_DI1) {
++ reg &= ~LDB_SPLIT_MODE_EN;
++ reg |= LDB_CH0_MODE_EN_TO_DI1 | LDB_CH1_MODE_EN_TO_DI1;
++ setting->disp_id = 1;
++ } else if (ldb->mode == LDB_SIN0) {
++ reg &= ~LDB_SPLIT_MODE_EN;
++ setting->disp_id = plat_data->disp_id;
++ if (setting->disp_id == 0)
++ reg |= LDB_CH0_MODE_EN_TO_DI0;
++ else
++ reg |= LDB_CH0_MODE_EN_TO_DI1;
++ ch_mask = LDB_CH0_MODE_MASK;
++ ch_val = reg & LDB_CH0_MODE_MASK;
++ } else if (ldb->mode == LDB_SIN1) {
++ reg &= ~LDB_SPLIT_MODE_EN;
++ setting->disp_id = plat_data->disp_id;
++ if (setting->disp_id == 0)
++ reg |= LDB_CH1_MODE_EN_TO_DI0;
++ else
++ reg |= LDB_CH1_MODE_EN_TO_DI1;
++ ch_mask = LDB_CH1_MODE_MASK;
++ ch_val = reg & LDB_CH1_MODE_MASK;
++ } else { /* separate mode*/
++ setting->disp_id = plat_data->disp_id;
++
++ /* first output is LVDS0 or LVDS1 */
++ if (ldb->mode == LDB_SEP0)
++ lvds_channel = 0;
++ else
++ lvds_channel = 1;
++
++ reg &= ~LDB_SPLIT_MODE_EN;
++
++ if ((lvds_channel == 0) && (setting->disp_id == 0))
++ reg |= LDB_CH0_MODE_EN_TO_DI0;
++ else if ((lvds_channel == 0) && (setting->disp_id == 1))
++ reg |= LDB_CH0_MODE_EN_TO_DI1;
++ else if ((lvds_channel == 1) && (setting->disp_id == 0))
++ reg |= LDB_CH1_MODE_EN_TO_DI0;
++ else
++ reg |= LDB_CH1_MODE_EN_TO_DI1;
++ ch_mask = lvds_channel ? LDB_CH1_MODE_MASK :
++ LDB_CH0_MODE_MASK;
++ ch_val = reg & ch_mask;
++
++ if (bits_per_pixel(setting->if_fmt) == 24) {
++ if (lvds_channel == 0)
++ reg &= ~LDB_DATA_WIDTH_CH1_24;
++ else
++ reg &= ~LDB_DATA_WIDTH_CH0_24;
++ } else {
++ if (lvds_channel == 0)
++ reg &= ~LDB_DATA_WIDTH_CH1_18;
++ else
++ reg &= ~LDB_DATA_WIDTH_CH0_18;
++ }
++ }
++
++ writel(reg, ldb->control_reg);
++ if (ldb->mode < LDB_SIN0) {
++ ch_mask = LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK;
++ ch_val = reg & (LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
++ }
++ } else { /* second time for separate mode */
++ if ((ldb->mode == LDB_SPL_DI0) ||
++ (ldb->mode == LDB_SPL_DI1) ||
++ (ldb->mode == LDB_DUL_DI0) ||
++ (ldb->mode == LDB_DUL_DI1) ||
++ (ldb->mode == LDB_SIN0) ||
++ (ldb->mode == LDB_SIN1)) {
++ dev_err(&ldb->pdev->dev, "for second ldb disp"
++ "ldb mode should in separate mode\n");
++ return -EINVAL;
++ }
++
++ setting_idx = 1;
++ if (is_imx6_ldb(plat_data)) {
++ setting->dev_id = plat_data->sec_ipu_id;
++ setting->disp_id = plat_data->sec_disp_id;
++ } else {
++ setting->dev_id = plat_data->ipu_id;
++ setting->disp_id = !plat_data->disp_id;
++ }
++ if (setting->disp_id == ldb->setting[0].di) {
++ dev_err(&ldb->pdev->dev, "Err: for second ldb disp in"
++ "separate mode, DI should be different!\n");
++ return -EINVAL;
++ }
++
++ /* second output is LVDS0 or LVDS1 */
++ if (ldb->mode == LDB_SEP0)
++ lvds_channel = 1;
++ else
++ lvds_channel = 0;
++
++ reg = readl(ldb->control_reg);
++ if ((lvds_channel == 0) && (setting->disp_id == 0))
++ reg |= LDB_CH0_MODE_EN_TO_DI0;
++ else if ((lvds_channel == 0) && (setting->disp_id == 1))
++ reg |= LDB_CH0_MODE_EN_TO_DI1;
++ else if ((lvds_channel == 1) && (setting->disp_id == 0))
++ reg |= LDB_CH1_MODE_EN_TO_DI0;
++ else
++ reg |= LDB_CH1_MODE_EN_TO_DI1;
++ ch_mask = lvds_channel ? LDB_CH1_MODE_MASK :
++ LDB_CH0_MODE_MASK;
++ ch_val = reg & ch_mask;
++
++ if (bits_per_pixel(setting->if_fmt) == 24) {
++ if (lvds_channel == 0)
++ reg |= LDB_DATA_WIDTH_CH0_24;
++ else
++ reg |= LDB_DATA_WIDTH_CH1_24;
++ } else {
++ if (lvds_channel == 0)
++ reg |= LDB_DATA_WIDTH_CH0_18;
++ else
++ reg |= LDB_DATA_WIDTH_CH1_18;
++ }
++ writel(reg, ldb->control_reg);
++ }
++
++ /* get clocks */
++ if (is_imx6_ldb(plat_data) &&
++ ((ldb->mode == LDB_SEP0) || (ldb->mode == LDB_SEP1))) {
++ ldb_clk[6] += lvds_channel;
++ div_3_5_clk[2] += lvds_channel;
++ div_7_clk[2] += lvds_channel;
++ div_sel_clk[2] += lvds_channel;
++ } else {
++ ldb_clk[6] += setting->disp_id;
++ div_3_5_clk[2] += setting->disp_id;
++ div_7_clk[2] += setting->disp_id;
++ div_sel_clk[2] += setting->disp_id;
++ }
++ ldb->setting[setting_idx].ldb_di_clk = clk_get(&ldb->pdev->dev,
++ ldb_clk);
++ if (IS_ERR(ldb->setting[setting_idx].ldb_di_clk)) {
++ dev_err(&ldb->pdev->dev, "get ldb clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].ldb_di_clk);
++ }
++
++ ldb->setting[setting_idx].div_3_5_clk = clk_get(&ldb->pdev->dev,
++ div_3_5_clk);
++ if (IS_ERR(ldb->setting[setting_idx].div_3_5_clk)) {
++ dev_err(&ldb->pdev->dev, "get div 3.5 clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].div_3_5_clk);
++ }
++ ldb->setting[setting_idx].div_7_clk = clk_get(&ldb->pdev->dev,
++ div_7_clk);
++ if (IS_ERR(ldb->setting[setting_idx].div_7_clk)) {
++ dev_err(&ldb->pdev->dev, "get div 7 clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].div_7_clk);
++ }
++
++ ldb->setting[setting_idx].div_sel_clk = clk_get(&ldb->pdev->dev,
++ div_sel_clk);
++ if (IS_ERR(ldb->setting[setting_idx].div_sel_clk)) {
++ dev_err(&ldb->pdev->dev, "get div sel clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].div_sel_clk);
++ }
++
++ di_clk[3] += setting->dev_id;
++ di_clk[7] += setting->disp_id;
++ ldb->setting[setting_idx].di_clk = clk_get(&ldb->pdev->dev,
++ di_clk);
++ if (IS_ERR(ldb->setting[setting_idx].di_clk)) {
++ dev_err(&ldb->pdev->dev, "get di clk failed\n");
++ return PTR_ERR(ldb->setting[setting_idx].di_clk);
++ }
++
++ ldb->setting[setting_idx].ch_mask = ch_mask;
++ ldb->setting[setting_idx].ch_val = ch_val;
++
++ if (is_imx6_ldb(plat_data))
++ ldb_ipu_ldb_route(setting->dev_id, setting->disp_id, ldb);
++
++ /* must use spec video mode defined by driver */
++ ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
++ ldb_modedb, ldb_modedb_sz, NULL, setting->default_bpp);
++ if (ret != 1)
++ fb_videomode_to_var(&setting->fbi->var, &ldb_modedb[0]);
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < ldb_modedb_sz; i++) {
++ struct fb_videomode m;
++ fb_var_to_videomode(&m, &setting->fbi->var);
++ if (fb_mode_is_equal(&m, &ldb_modedb[i])) {
++ fb_add_videomode(&ldb_modedb[i],
++ &setting->fbi->modelist);
++ break;
++ }
++ }
++
++ ldb->setting[setting_idx].ipu = setting->dev_id;
++ ldb->setting[setting_idx].di = setting->disp_id;
++
++ return ret;
++}
++
++static int ldb_post_disp_init(struct mxc_dispdrv_handle *disp,
++ int ipu_id, int disp_id)
++{
++ struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
++ int setting_idx = ldb->inited ? 1 : 0;
++ int ret = 0;
++
++ if (!ldb->inited) {
++ ldb->nb.notifier_call = ldb_fb_event;
++ fb_register_client(&ldb->nb);
++ }
++
++ ret = clk_set_parent(ldb->setting[setting_idx].di_clk,
++ ldb->setting[setting_idx].ldb_di_clk);
++ if (ret) {
++ dev_err(&ldb->pdev->dev, "fail to set ldb_di clk as"
++ "the parent of ipu_di clk\n");
++ return ret;
++ }
++
++ if ((ldb->mode == LDB_SPL_DI0) || (ldb->mode == LDB_SPL_DI1)) {
++ ret = clk_set_parent(ldb->setting[setting_idx].div_sel_clk,
++ ldb->setting[setting_idx].div_3_5_clk);
++ if (ret) {
++ dev_err(&ldb->pdev->dev, "fail to set div 3.5 clk as"
++ "the parent of div sel clk\n");
++ return ret;
++ }
++ } else {
++ ret = clk_set_parent(ldb->setting[setting_idx].div_sel_clk,
++ ldb->setting[setting_idx].div_7_clk);
++ if (ret) {
++ dev_err(&ldb->pdev->dev, "fail to set div 7 clk as"
++ "the parent of div sel clk\n");
++ return ret;
++ }
++ }
++
++ /* save active ldb setting for fb notifier */
++ ldb->setting[setting_idx].active = true;
++
++ ldb->inited = true;
++ return ret;
++}
++
++static void ldb_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct ldb_data *ldb = mxc_dispdrv_getdata(disp);
++ int i;
++
++ writel(0, ldb->control_reg);
++
++ for (i = 0; i < 2; i++) {
++ clk_disable(ldb->setting[i].ldb_di_clk);
++ clk_put(ldb->setting[i].ldb_di_clk);
++ clk_put(ldb->setting[i].div_3_5_clk);
++ clk_put(ldb->setting[i].div_7_clk);
++ clk_put(ldb->setting[i].div_sel_clk);
++ }
++
++ fb_unregister_client(&ldb->nb);
++}
++
++static struct mxc_dispdrv_driver ldb_drv = {
++ .name = DISPDRV_LDB,
++ .init = ldb_disp_init,
++ .post_init = ldb_post_disp_init,
++ .deinit = ldb_disp_deinit,
++ .setup = ldb_disp_setup,
++};
++
++static int ldb_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct ldb_data *ldb = dev_get_drvdata(&pdev->dev);
++ uint32_t data;
++
++ if (!ldb->inited)
++ return 0;
++ data = readl(ldb->control_reg);
++ ldb->control_reg_data = data;
++ data &= ~(LDB_CH0_MODE_MASK | LDB_CH1_MODE_MASK);
++ writel(data, ldb->control_reg);
++
++ return 0;
++}
++
++static int ldb_resume(struct platform_device *pdev)
++{
++ struct ldb_data *ldb = dev_get_drvdata(&pdev->dev);
++
++ if (!ldb->inited)
++ return 0;
++ writel(ldb->control_reg_data, ldb->control_reg);
++
++ return 0;
++}
++
++static struct platform_device_id imx_ldb_devtype[] = {
++ {
++ .name = "ldb-imx6",
++ .driver_data = LDB_IMX6,
++ }, {
++ /* sentinel */
++ }
++};
++
++static const struct of_device_id imx_ldb_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ldb", .data = &imx_ldb_devtype[IMX6_LDB],},
++ { /* sentinel */ }
++};
++
++/*!
++ * This function is called by the driver framework to initialize the LDB
++ * device.
++ *
++ * @param dev The device structure for the LDB passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int ldb_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++ struct ldb_data *ldb;
++ struct fsl_mxc_ldb_platform_data *plat_data;
++ const struct of_device_id *of_id =
++ of_match_device(imx_ldb_dt_ids, &pdev->dev);
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ ldb = devm_kzalloc(&pdev->dev, sizeof(struct ldb_data), GFP_KERNEL);
++ if (!ldb)
++ return -ENOMEM;
++
++ plat_data = devm_kzalloc(&pdev->dev,
++ sizeof(struct fsl_mxc_ldb_platform_data),
++ GFP_KERNEL);
++ if (!plat_data)
++ return -ENOMEM;
++ pdev->dev.platform_data = plat_data;
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ plat_data->devtype = pdev->id_entry->driver_data;
++
++ ret = ldb_get_of_property(pdev, plat_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get ldb of property fail\n");
++ return ret;
++ }
++
++ ldb->pdev = pdev;
++ ldb->disp_ldb = mxc_dispdrv_register(&ldb_drv);
++ mxc_dispdrv_setdata(ldb->disp_ldb, ldb);
++
++ dev_set_drvdata(&pdev->dev, ldb);
++
++ dev_dbg(&pdev->dev, "%s exit\n", __func__);
++ return ret;
++}
++
++static int ldb_remove(struct platform_device *pdev)
++{
++ struct ldb_data *ldb = dev_get_drvdata(&pdev->dev);
++
++ if (!ldb->inited)
++ return 0;
++ mxc_dispdrv_puthandle(ldb->disp_ldb);
++ mxc_dispdrv_unregister(ldb->disp_ldb);
++ return 0;
++}
++
++static struct platform_driver mxcldb_driver = {
++ .driver = {
++ .name = "mxc_ldb",
++ .of_match_table = imx_ldb_dt_ids,
++ },
++ .probe = ldb_probe,
++ .remove = ldb_remove,
++ .suspend = ldb_suspend,
++ .resume = ldb_resume,
++};
++
++static int __init ldb_init(void)
++{
++ return platform_driver_register(&mxcldb_driver);
++}
++
++static void __exit ldb_uninit(void)
++{
++ platform_driver_unregister(&mxcldb_driver);
++}
++
++module_init(ldb_init);
++module_exit(ldb_uninit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC LDB driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/Makefile linux-linaro-stable-mx6/drivers/video/mxc/Makefile
+--- linux-3.10.30.orig/drivers/video/mxc/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/Makefile 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,8 @@
++obj-$(CONFIG_FB_MXC_LDB) += ldb.o
++obj-$(CONFIG_FB_MXC_MIPI_DSI) += mipi_dsi.o
++obj-$(CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL) += mxcfb_hx8369_wvga.o
++obj-$(CONFIG_FB_MXC_HDMI) += mxc_hdmi.o
++obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o
++obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_dispdrv.o mxc_lcdif.o mxc_ipuv3_fb.o
++obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o
++obj-$(CONFIG_FB_MXS_SII902X) += mxsfb_sii902x.o
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mipi_dsi.c linux-linaro-stable-mx6/drivers/video/mxc/mipi_dsi.c
+--- linux-3.10.30.orig/drivers/video/mxc/mipi_dsi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mipi_dsi.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,953 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/ipu.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/mipi_dsi.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/backlight.h>
++#include <linux/of_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++#include <linux/delay.h>
++#include <video/mipi_display.h>
++
++#include "mxc_dispdrv.h"
++#include "mipi_dsi.h"
++
++#define DISPDRV_MIPI "mipi_dsi"
++#define ROUND_UP(x) ((x)+1)
++#define NS2PS_RATIO (1000)
++#define NUMBER_OF_CHUNKS (0x8)
++#define NULL_PKT_SIZE (0x8)
++#define PHY_BTA_MAXTIME (0xd00)
++#define PHY_LP2HS_MAXTIME (0x40)
++#define PHY_HS2LP_MAXTIME (0x40)
++#define PHY_STOP_WAIT_TIME (0x20)
++#define DSI_CLKMGR_CFG_CLK_DIV (0x107)
++#define DSI_GEN_PLD_DATA_BUF_ENTRY (0x10)
++#define MIPI_MUX_CTRL(v) (((v) & 0x3) << 4)
++#define MIPI_LCD_SLEEP_MODE_DELAY (120)
++#define MIPI_DSI_REG_RW_TIMEOUT (20)
++#define MIPI_DSI_PHY_TIMEOUT (10)
++
++static struct mipi_dsi_match_lcd mipi_dsi_lcd_db[] = {
++#ifdef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++ {
++ "TRULY-WVGA",
++ {mipid_hx8369_get_lcd_videomode, mipid_hx8369_lcd_setup}
++ },
++#endif
++ {
++ "", {NULL, NULL}
++ }
++};
++
++struct _mipi_dsi_phy_pll_clk {
++ u32 max_phy_clk;
++ u32 config;
++};
++
++/* configure data for DPHY PLL 27M reference clk out */
++static const struct _mipi_dsi_phy_pll_clk mipi_dsi_phy_pll_clk_table[] = {
++ {1000, 0x74}, /* 950-1000MHz */
++ {950, 0x54}, /* 900-950Mhz */
++ {900, 0x34}, /* 850-900Mhz */
++ {850, 0x14}, /* 800-850MHz */
++ {800, 0x32}, /* 750-800MHz */
++ {750, 0x12}, /* 700-750Mhz */
++ {700, 0x30}, /* 650-700Mhz */
++ {650, 0x10}, /* 600-650MHz */
++ {600, 0x2e}, /* 550-600MHz */
++ {550, 0x0e}, /* 500-550Mhz */
++ {500, 0x2c}, /* 450-500Mhz */
++ {450, 0x0c}, /* 400-450MHz */
++ {400, 0x4a}, /* 360-400MHz */
++ {360, 0x2a}, /* 330-360Mhz */
++ {330, 0x48}, /* 300-330Mhz */
++ {300, 0x28}, /* 270-300MHz */
++ {270, 0x08}, /* 250-270MHz */
++ {250, 0x46}, /* 240-250Mhz */
++ {240, 0x26}, /* 210-240Mhz */
++ {210, 0x06}, /* 200-210MHz */
++ {200, 0x44}, /* 180-200MHz */
++ {180, 0x24}, /* 160-180MHz */
++ {160, 0x04}, /* 150-160MHz */
++};
++
++static int valid_mode(int pixel_fmt)
++{
++ return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR24) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB666) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB565) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR666) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB332));
++}
++
++static inline void mipi_dsi_read_register(struct mipi_dsi_info *mipi_dsi,
++ u32 reg, u32 *val)
++{
++ *val = ioread32(mipi_dsi->mmio_base + reg);
++ dev_dbg(&mipi_dsi->pdev->dev, "read_reg:0x%02x, val:0x%08x.\n",
++ reg, *val);
++}
++
++static inline void mipi_dsi_write_register(struct mipi_dsi_info *mipi_dsi,
++ u32 reg, u32 val)
++{
++ iowrite32(val, mipi_dsi->mmio_base + reg);
++ dev_dbg(&mipi_dsi->pdev->dev, "\t\twrite_reg:0x%02x, val:0x%08x.\n",
++ reg, val);
++}
++
++int mipi_dsi_pkt_write(struct mipi_dsi_info *mipi_dsi,
++ u8 data_type, const u32 *buf, int len)
++{
++ u32 val;
++ u32 status = 0;
++ int write_len = len;
++ uint32_t timeout = 0;
++
++ if (len) {
++ /* generic long write command */
++ while (len / DSI_GEN_PLD_DATA_BUF_SIZE) {
++ mipi_dsi_write_register(mipi_dsi,
++ MIPI_DSI_GEN_PLD_DATA, *buf);
++ buf++;
++ len -= DSI_GEN_PLD_DATA_BUF_SIZE;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ while ((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ }
++ }
++ /* write the remainder bytes */
++ if (len > 0) {
++ while ((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ }
++ mipi_dsi_write_register(mipi_dsi,
++ MIPI_DSI_GEN_PLD_DATA, *buf);
++ }
++
++ val = data_type | ((write_len & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ } else {
++ /* generic short write command */
++ val = data_type | ((*buf & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ }
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &status);
++ while ((status & DSI_CMD_PKT_STATUS_GEN_CMD_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_CMD_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &status);
++ }
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_GEN_HDR, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &status);
++ while (!((status & DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY) ==
++ DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY) ||
++ !((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY)) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &status);
++ }
++
++ return 0;
++}
++
++int mipi_dsi_pkt_read(struct mipi_dsi_info *mipi_dsi,
++ u8 data_type, u32 *buf, int len)
++{
++ u32 val;
++ int read_len = 0;
++ uint32_t timeout = 0;
++
++ if (!len) {
++ mipi_dbg("%s, len = 0 invalid error!\n", __func__);
++ return -EINVAL;
++ }
++
++ val = data_type | ((*buf & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ memset(buf, 0, len);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_GEN_HDR, val);
++
++ /* wait for cmd to sent out */
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &val);
++ while ((val & DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) !=
++ DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ }
++ /* wait for entire response stroed in FIFO */
++ while ((val & DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) ==
++ DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ }
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &val);
++ while (!(val & DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY)) {
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_GEN_PLD_DATA, buf);
++ read_len += DSI_GEN_PLD_DATA_BUF_SIZE;
++ buf++;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ if (read_len == (DSI_GEN_PLD_DATA_BUF_ENTRY *
++ DSI_GEN_PLD_DATA_BUF_SIZE))
++ break;
++ }
++
++ if ((len <= read_len) &&
++ ((len + DSI_GEN_PLD_DATA_BUF_SIZE) >= read_len))
++ return 0;
++ else {
++ dev_err(&mipi_dsi->pdev->dev,
++ "actually read_len:%d != len:%d.\n", read_len, len);
++ return -ERANGE;
++ }
++}
++
++int mipi_dsi_dcs_cmd(struct mipi_dsi_info *mipi_dsi,
++ u8 cmd, const u32 *param, int num)
++{
++ int err = 0;
++ u32 buf[DSI_CMD_BUF_MAXSIZE];
++
++ switch (cmd) {
++ case MIPI_DCS_EXIT_SLEEP_MODE:
++ case MIPI_DCS_ENTER_SLEEP_MODE:
++ case MIPI_DCS_SET_DISPLAY_ON:
++ case MIPI_DCS_SET_DISPLAY_OFF:
++ buf[0] = cmd;
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_DCS_SHORT_WRITE, buf, 0);
++ break;
++
++ default:
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command:0x%x Not supported!\n", cmd);
++ break;
++ }
++
++ return err;
++}
++
++static void mipi_dsi_dphy_init(struct mipi_dsi_info *mipi_dsi,
++ u32 cmd, u32 data)
++{
++ u32 val;
++ u32 timeout = 0;
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP, DSI_PWRUP_POWERUP);
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL1,
++ (0x10000 | cmd));
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 2);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL1, (0 | data));
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 2);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ val = DSI_PHY_RSTZ_EN_CLK | DSI_PHY_RSTZ_DISABLE_RST |
++ DSI_PHY_RSTZ_DISABLE_SHUTDOWN;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ while ((val & DSI_PHY_STATUS_LOCK) != DSI_PHY_STATUS_LOCK) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_PHY_TIMEOUT) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "Error: phy lock timeout!\n");
++ break;
++ }
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ }
++ timeout = 0;
++ while ((val & DSI_PHY_STATUS_STOPSTATE_CLK_LANE) !=
++ DSI_PHY_STATUS_STOPSTATE_CLK_LANE) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_PHY_TIMEOUT) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "Error: phy lock lane timeout!\n");
++ break;
++ }
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ }
++}
++
++static void mipi_dsi_enable_controller(struct mipi_dsi_info *mipi_dsi,
++ bool init)
++{
++ u32 val;
++ u32 lane_byte_clk_period;
++ struct fb_videomode *mode = mipi_dsi->mode;
++ struct mipi_lcd_config *lcd_config = mipi_dsi->lcd_config;
++
++ if (init) {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ,
++ DSI_PHY_RSTZ_RST);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CLKMGR_CFG,
++ DSI_CLKMGR_CFG_CLK_DIV);
++
++ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
++ val = DSI_DPI_CFG_VSYNC_ACT_LOW;
++ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
++ val |= DSI_DPI_CFG_HSYNC_ACT_LOW;
++ if ((mode->sync & FB_SYNC_OE_LOW_ACT))
++ val |= DSI_DPI_CFG_DATAEN_ACT_LOW;
++ if (MIPI_RGB666_LOOSELY == lcd_config->dpi_fmt)
++ val |= DSI_DPI_CFG_EN18LOOSELY;
++ val |= (lcd_config->dpi_fmt & DSI_DPI_CFG_COLORCODE_MASK)
++ << DSI_DPI_CFG_COLORCODE_SHIFT;
++ val |= (lcd_config->virtual_ch & DSI_DPI_CFG_VID_MASK)
++ << DSI_DPI_CFG_VID_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_DPI_CFG, val);
++
++ val = DSI_PCKHDL_CFG_EN_BTA |
++ DSI_PCKHDL_CFG_EN_ECC_RX |
++ DSI_PCKHDL_CFG_EN_CRC_RX;
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PCKHDL_CFG, val);
++
++ val = (mode->xres & DSI_VID_PKT_CFG_VID_PKT_SZ_MASK)
++ << DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT;
++ val |= (NUMBER_OF_CHUNKS & DSI_VID_PKT_CFG_NUM_CHUNKS_MASK)
++ << DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT;
++ val |= (NULL_PKT_SIZE & DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK)
++ << DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_PKT_CFG, val);
++
++ /* enable LP mode when TX DCS cmd and enable DSI command mode */
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG,
++ MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER);
++
++ /* mipi lane byte clk period in ns unit */
++ lane_byte_clk_period = NS2PS_RATIO /
++ (lcd_config->max_phy_clk / BITS_PER_BYTE);
++ val = ROUND_UP(mode->hsync_len * mode->pixclock /
++ NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HSA_TIME_SHIFT;
++ val |= ROUND_UP(mode->left_margin * mode->pixclock /
++ NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HBP_TIME_SHIFT;
++ val |= ROUND_UP((mode->left_margin + mode->right_margin +
++ mode->hsync_len + mode->xres) * mode->pixclock
++ / NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HLINE_TIME_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_TMR_LINE_CFG, val);
++
++ val = ((mode->vsync_len & DSI_VTIMING_CFG_VSA_LINES_MASK)
++ << DSI_VTIMING_CFG_VSA_LINES_SHIFT);
++ val |= ((mode->upper_margin & DSI_VTIMING_CFG_VBP_LINES_MASK)
++ << DSI_VTIMING_CFG_VBP_LINES_SHIFT);
++ val |= ((mode->lower_margin & DSI_VTIMING_CFG_VFP_LINES_MASK)
++ << DSI_VTIMING_CFG_VFP_LINES_SHIFT);
++ val |= ((mode->yres & DSI_VTIMING_CFG_V_ACT_LINES_MASK)
++ << DSI_VTIMING_CFG_V_ACT_LINES_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VTIMING_CFG, val);
++
++ val = ((PHY_BTA_MAXTIME & DSI_PHY_TMR_CFG_BTA_TIME_MASK)
++ << DSI_PHY_TMR_CFG_BTA_TIME_SHIFT);
++ val |= ((PHY_LP2HS_MAXTIME & DSI_PHY_TMR_CFG_LP2HS_TIME_MASK)
++ << DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT);
++ val |= ((PHY_HS2LP_MAXTIME & DSI_PHY_TMR_CFG_HS2LP_TIME_MASK)
++ << DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TMR_CFG, val);
++
++ val = (((lcd_config->data_lane_num - 1) &
++ DSI_PHY_IF_CFG_N_LANES_MASK)
++ << DSI_PHY_IF_CFG_N_LANES_SHIFT);
++ val |= ((PHY_STOP_WAIT_TIME & DSI_PHY_IF_CFG_WAIT_TIME_MASK)
++ << DSI_PHY_IF_CFG_WAIT_TIME_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CFG, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST0, &val);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST1, &val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_ERROR_MSK0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_ERROR_MSK1, 0);
++
++ mipi_dsi_dphy_init(mipi_dsi, DSI_PHY_CLK_INIT_COMMAND,
++ mipi_dsi->dphy_pll_config);
++ } else {
++ mipi_dsi_dphy_init(mipi_dsi, DSI_PHY_CLK_INIT_COMMAND,
++ mipi_dsi->dphy_pll_config);
++ }
++}
++
++static void mipi_dsi_disable_controller(struct mipi_dsi_info *mipi_dsi)
++{
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP, DSI_PWRUP_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ, DSI_PHY_RSTZ_RST);
++}
++
++static irqreturn_t mipi_dsi_irq_handler(int irq, void *data)
++{
++ u32 mask0;
++ u32 mask1;
++ u32 status0;
++ u32 status1;
++ struct mipi_dsi_info *mipi_dsi;
++
++ mipi_dsi = (struct mipi_dsi_info *)data;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST0, &status0);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST1, &status1);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_MSK0, &mask0);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_MSK1, &mask1);
++
++ if ((status0 & (~mask0)) || (status1 & (~mask1))) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "mipi_dsi IRQ status0:0x%x, status1:0x%x!\n",
++ status0, status1);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static inline void mipi_dsi_set_mode(struct mipi_dsi_info *mipi_dsi,
++ bool cmd_mode)
++{
++ u32 val;
++
++ if (cmd_mode) {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, &val);
++ val |= MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_MODE_CFG, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_POWERUP);
++ } else {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ /* Disable Command mode when tranfering video data */
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, &val);
++ val &= ~MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, val);
++ val = DSI_VID_MODE_CFG_EN | DSI_VID_MODE_CFG_EN_BURSTMODE |
++ DSI_VID_MODE_CFG_EN_LP_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_MODE_CFG, val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_POWERUP);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_TX_REQ_CLK_HS);
++ }
++}
++
++static int mipi_dsi_power_on(struct mxc_dispdrv_handle *disp)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (!mipi_dsi->dsi_power_on) {
++ clk_prepare_enable(mipi_dsi->dphy_clk);
++ clk_prepare_enable(mipi_dsi->cfg_clk);
++ mipi_dsi_enable_controller(mipi_dsi, false);
++ mipi_dsi_set_mode(mipi_dsi, false);
++ /* host send pclk/hsync/vsync for two frames before sleep-out */
++ msleep((1000/mipi_dsi->mode->refresh + 1) << 1);
++ mipi_dsi_set_mode(mipi_dsi, true);
++ err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_EXIT_SLEEP_MODE,
++ NULL, 0);
++ if (err) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command sleep-in error!\n");
++ }
++ msleep(MIPI_LCD_SLEEP_MODE_DELAY);
++ mipi_dsi_set_mode(mipi_dsi, false);
++ mipi_dsi->dsi_power_on = 1;
++ }
++
++ return 0;
++}
++
++void mipi_dsi_power_off(struct mxc_dispdrv_handle *disp)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (mipi_dsi->dsi_power_on) {
++ mipi_dsi_set_mode(mipi_dsi, true);
++ err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_ENTER_SLEEP_MODE,
++ NULL, 0);
++ if (err) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command display on error!\n");
++ }
++ /* To allow time for the supply voltages
++ * and clock circuits to stabilize.
++ */
++ msleep(5);
++ /* video stream timing on */
++ mipi_dsi_set_mode(mipi_dsi, false);
++ msleep(MIPI_LCD_SLEEP_MODE_DELAY);
++
++ mipi_dsi_set_mode(mipi_dsi, true);
++ mipi_dsi_disable_controller(mipi_dsi);
++ mipi_dsi->dsi_power_on = 0;
++ clk_disable_unprepare(mipi_dsi->dphy_clk);
++ clk_disable_unprepare(mipi_dsi->cfg_clk);
++ }
++}
++
++static int mipi_dsi_lcd_init(struct mipi_dsi_info *mipi_dsi,
++ struct mxc_dispdrv_setting *setting)
++{
++ int err;
++ int size;
++ int i;
++ struct fb_videomode *mipi_lcd_modedb;
++ struct fb_videomode mode;
++ struct device *dev = &mipi_dsi->pdev->dev;
++
++ for (i = 0; i < ARRAY_SIZE(mipi_dsi_lcd_db); i++) {
++ if (!strcmp(mipi_dsi->lcd_panel,
++ mipi_dsi_lcd_db[i].lcd_panel)) {
++ mipi_dsi->lcd_callback =
++ &mipi_dsi_lcd_db[i].lcd_callback;
++ break;
++ }
++ }
++ if (i == ARRAY_SIZE(mipi_dsi_lcd_db)) {
++ dev_err(dev, "failed to find supported lcd panel.\n");
++ return -EINVAL;
++ }
++ /* get the videomode in the order: cmdline->platform data->driver */
++ mipi_dsi->lcd_callback->get_mipi_lcd_videomode(&mipi_lcd_modedb, &size,
++ &mipi_dsi->lcd_config);
++ err = fb_find_mode(&setting->fbi->var, setting->fbi,
++ setting->dft_mode_str,
++ mipi_lcd_modedb, size, NULL,
++ setting->default_bpp);
++ if (err != 1)
++ fb_videomode_to_var(&setting->fbi->var, mipi_lcd_modedb);
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < size; i++) {
++ fb_var_to_videomode(&mode, &setting->fbi->var);
++ if (fb_mode_is_equal(&mode, mipi_lcd_modedb + i)) {
++ err = fb_add_videomode(mipi_lcd_modedb + i,
++ &setting->fbi->modelist);
++ /* Note: only support fb mode from driver */
++ mipi_dsi->mode = mipi_lcd_modedb + i;
++ break;
++ }
++ }
++ if ((err < 0) || (size == i)) {
++ dev_err(dev, "failed to add videomode.\n");
++ return err;
++ }
++
++ for (i = 0; i < ARRAY_SIZE(mipi_dsi_phy_pll_clk_table); i++) {
++ if (mipi_dsi_phy_pll_clk_table[i].max_phy_clk <
++ mipi_dsi->lcd_config->max_phy_clk)
++ break;
++ }
++ if ((i == ARRAY_SIZE(mipi_dsi_phy_pll_clk_table)) ||
++ (mipi_dsi->lcd_config->max_phy_clk >
++ mipi_dsi_phy_pll_clk_table[0].max_phy_clk)) {
++ dev_err(dev, "failed to find data in"
++ "mipi_dsi_phy_pll_clk_table.\n");
++ return -EINVAL;
++ }
++ mipi_dsi->dphy_pll_config = mipi_dsi_phy_pll_clk_table[--i].config;
++ dev_dbg(dev, "dphy_pll_config:0x%x.\n", mipi_dsi->dphy_pll_config);
++
++ return 0;
++}
++
++int mipi_dsi_enable(struct mxc_dispdrv_handle *disp)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (!mipi_dsi->lcd_inited) {
++ err = clk_prepare_enable(mipi_dsi->dphy_clk);
++ err |= clk_prepare_enable(mipi_dsi->cfg_clk);
++ if (err)
++ dev_err(&mipi_dsi->pdev->dev,
++ "clk enable error:%d!\n", err);
++ mipi_dsi_enable_controller(mipi_dsi, true);
++ err = mipi_dsi->lcd_callback->mipi_lcd_setup(
++ mipi_dsi);
++ if (err < 0) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "failed to init mipi lcd.");
++ clk_disable_unprepare(mipi_dsi->dphy_clk);
++ clk_disable_unprepare(mipi_dsi->cfg_clk);
++ return err;
++ }
++ mipi_dsi_set_mode(mipi_dsi, false);
++ mipi_dsi->dsi_power_on = 1;
++ mipi_dsi->lcd_inited = 1;
++ }
++ mipi_dsi_power_on(mipi_dsi->disp_mipi);
++
++ return 0;
++}
++
++static int mipi_dsi_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++ struct device *dev = &mipi_dsi->pdev->dev;
++ int ret = 0;
++
++ if (!valid_mode(setting->if_fmt)) {
++ dev_warn(dev, "Input pixel format not valid"
++ "use default RGB24\n");
++ setting->if_fmt = IPU_PIX_FMT_RGB24;
++ }
++
++ setting->dev_id = mipi_dsi->dev_id;
++ setting->disp_id = mipi_dsi->disp_id;
++
++ ret = mipi_dsi_lcd_init(mipi_dsi, setting);
++ if (ret) {
++ dev_err(dev, "failed to init mipi dsi lcd\n");
++ return ret;
++ }
++
++ dev_dbg(dev, "MIPI DSI dispdrv inited!\n");
++ return ret;
++}
++
++static void mipi_dsi_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct mipi_dsi_info *mipi_dsi;
++
++ mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ mipi_dsi_power_off(mipi_dsi->disp_mipi);
++ if (mipi_dsi->bl)
++ backlight_device_unregister(mipi_dsi->bl);
++}
++
++static struct mxc_dispdrv_driver mipi_dsi_drv = {
++ .name = DISPDRV_MIPI,
++ .init = mipi_dsi_disp_init,
++ .deinit = mipi_dsi_disp_deinit,
++ .enable = mipi_dsi_enable,
++ .disable = mipi_dsi_power_off,
++};
++
++static int imx6q_mipi_dsi_get_mux(int dev_id, int disp_id)
++{
++ if (dev_id > 1 || disp_id > 1)
++ return -EINVAL;
++
++ return (dev_id << 5) | (disp_id << 4);
++}
++
++static struct mipi_dsi_bus_mux imx6q_mipi_dsi_mux[] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .mask = IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
++ .get_mux = imx6q_mipi_dsi_get_mux,
++ },
++};
++
++static int imx6dl_mipi_dsi_get_mux(int dev_id, int disp_id)
++{
++ if (dev_id > 1 || disp_id > 1)
++ return -EINVAL;
++
++ /* MIPI DSI source is LCDIF */
++ if (dev_id)
++ disp_id = 0;
++
++ return (dev_id << 5) | (disp_id << 4);
++}
++
++static struct mipi_dsi_bus_mux imx6dl_mipi_dsi_mux[] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .mask = IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
++ .get_mux = imx6dl_mipi_dsi_get_mux,
++ },
++};
++
++static const struct of_device_id imx_mipi_dsi_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mipi-dsi", .data = imx6q_mipi_dsi_mux, },
++ { .compatible = "fsl,imx6dl-mipi-dsi", .data = imx6dl_mipi_dsi_mux, },
++ { }
++};
++MODULE_DEVICE_TABLE(of, imx_mipi_dsi_dt_ids);
++
++/**
++ * This function is called by the driver framework to initialize the MIPI DSI
++ * device.
++ *
++ * @param pdev The device structure for the MIPI DSI passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int mipi_dsi_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ const struct of_device_id *of_id =
++ of_match_device(of_match_ptr(imx_mipi_dsi_dt_ids),
++ &pdev->dev);
++ struct mipi_dsi_info *mipi_dsi;
++ struct resource *res;
++ u32 dev_id, disp_id;
++ const char *lcd_panel;
++ unsigned int mux;
++ int ret = 0;
++
++ mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
++ if (!mipi_dsi)
++ return -ENOMEM;
++
++ ret = of_property_read_string(np, "lcd_panel", &lcd_panel);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property lcd_panel\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "dev_id", &dev_id);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property dev_id\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "disp_id", &disp_id);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property disp_id\n");
++ return ret;
++ }
++ mipi_dsi->dev_id = dev_id;
++ mipi_dsi->disp_id = disp_id;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "failed to get platform resource 0\n");
++ return -ENODEV;
++ }
++
++ if (!devm_request_mem_region(&pdev->dev, res->start,
++ resource_size(res), pdev->name))
++ return -EBUSY;
++
++ mipi_dsi->mmio_base = devm_ioremap(&pdev->dev, res->start,
++ resource_size(res));
++ if (!mipi_dsi->mmio_base)
++ return -EBUSY;
++
++ mipi_dsi->irq = platform_get_irq(pdev, 0);
++ if (mipi_dsi->irq < 0) {
++ dev_err(&pdev->dev, "failed get device irq\n");
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, mipi_dsi->irq,
++ mipi_dsi_irq_handler,
++ 0, "mipi_dsi", mipi_dsi);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request irq\n");
++ return ret;
++ }
++
++ mipi_dsi->dphy_clk = devm_clk_get(&pdev->dev, "mipi_pllref_clk");
++ if (IS_ERR(mipi_dsi->dphy_clk)) {
++ dev_err(&pdev->dev, "failed to get dphy pll_ref_clk\n");
++ return PTR_ERR(mipi_dsi->dphy_clk);
++ }
++
++ mipi_dsi->cfg_clk = devm_clk_get(&pdev->dev, "mipi_cfg_clk");
++ if (IS_ERR(mipi_dsi->cfg_clk)) {
++ dev_err(&pdev->dev, "failed to get cfg_clk\n");
++ return PTR_ERR(mipi_dsi->cfg_clk);
++ }
++
++ mipi_dsi->disp_power_on = devm_regulator_get(&pdev->dev,
++ "disp-power-on");
++ if (!IS_ERR(mipi_dsi->disp_power_on)) {
++ ret = regulator_enable(mipi_dsi->disp_power_on);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to enable display "
++ "power regulator, err=%d\n", ret);
++ return ret;
++ }
++ } else {
++ mipi_dsi->disp_power_on = NULL;
++ }
++
++ ret = device_reset(&pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to reset: %d\n", ret);
++ goto dev_reset_fail;
++ }
++
++ if (of_id)
++ mipi_dsi->bus_mux = of_id->data;
++
++ mipi_dsi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
++ if (IS_ERR(mipi_dsi->regmap)) {
++ dev_err(&pdev->dev, "failed to get parent regmap\n");
++ ret = PTR_ERR(mipi_dsi->regmap);
++ goto get_parent_regmap_fail;
++ }
++
++ mux = mipi_dsi->bus_mux->get_mux(dev_id, disp_id);
++ if (mux >= 0)
++ regmap_update_bits(mipi_dsi->regmap, mipi_dsi->bus_mux->reg,
++ mipi_dsi->bus_mux->mask, mux);
++ else
++ dev_warn(&pdev->dev, "invalid dev_id or disp_id muxing\n");
++
++ mipi_dsi->lcd_panel = kstrdup(lcd_panel, GFP_KERNEL);
++ if (!mipi_dsi->lcd_panel) {
++ dev_err(&pdev->dev, "failed to allocate lcd panel name\n");
++ ret = -ENOMEM;
++ goto kstrdup_fail;
++ }
++
++ mipi_dsi->pdev = pdev;
++ mipi_dsi->disp_mipi = mxc_dispdrv_register(&mipi_dsi_drv);
++ if (IS_ERR(mipi_dsi->disp_mipi)) {
++ dev_err(&pdev->dev, "mxc_dispdrv_register error\n");
++ ret = PTR_ERR(mipi_dsi->disp_mipi);
++ goto dispdrv_reg_fail;
++ }
++
++ mxc_dispdrv_setdata(mipi_dsi->disp_mipi, mipi_dsi);
++ dev_set_drvdata(&pdev->dev, mipi_dsi);
++
++ dev_info(&pdev->dev, "i.MX MIPI DSI driver probed\n");
++ return ret;
++
++dispdrv_reg_fail:
++ kfree(mipi_dsi->lcd_panel);
++kstrdup_fail:
++get_parent_regmap_fail:
++dev_reset_fail:
++ if (mipi_dsi->disp_power_on)
++ regulator_disable(mipi_dsi->disp_power_on);
++ return ret;
++}
++
++static void mipi_dsi_shutdown(struct platform_device *pdev)
++{
++ struct mipi_dsi_info *mipi_dsi = dev_get_drvdata(&pdev->dev);
++
++ mipi_dsi_power_off(mipi_dsi->disp_mipi);
++}
++
++static int mipi_dsi_remove(struct platform_device *pdev)
++{
++ struct mipi_dsi_info *mipi_dsi = dev_get_drvdata(&pdev->dev);
++
++ mxc_dispdrv_puthandle(mipi_dsi->disp_mipi);
++ mxc_dispdrv_unregister(mipi_dsi->disp_mipi);
++
++ if (mipi_dsi->disp_power_on)
++ regulator_disable(mipi_dsi->disp_power_on);
++
++ kfree(mipi_dsi->lcd_panel);
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static struct platform_driver mipi_dsi_driver = {
++ .driver = {
++ .of_match_table = imx_mipi_dsi_dt_ids,
++ .name = "mxc_mipi_dsi",
++ },
++ .probe = mipi_dsi_probe,
++ .remove = mipi_dsi_remove,
++ .shutdown = mipi_dsi_shutdown,
++};
++
++static int __init mipi_dsi_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&mipi_dsi_driver);
++ if (err) {
++ pr_err("mipi_dsi_driver register failed\n");
++ return -ENODEV;
++ }
++ pr_info("MIPI DSI driver module loaded\n");
++ return 0;
++}
++
++static void __exit mipi_dsi_cleanup(void)
++{
++ platform_driver_unregister(&mipi_dsi_driver);
++}
++
++module_init(mipi_dsi_init);
++module_exit(mipi_dsi_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX MIPI DSI driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mipi_dsi.h linux-linaro-stable-mx6/drivers/video/mxc/mipi_dsi.h
+--- linux-3.10.30.orig/drivers/video/mxc/mipi_dsi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mipi_dsi.h 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,112 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MIPI_DSI_H__
++#define __MIPI_DSI_H__
++
++#include <linux/regmap.h>
++
++#ifdef DEBUG
++#define mipi_dbg(fmt, ...) printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
++#else
++#define mipi_dbg(fmt, ...)
++#endif
++
++#define DSI_CMD_BUF_MAXSIZE (32)
++
++/* DPI interface pixel color coding map */
++enum mipi_dsi_dpi_fmt {
++ MIPI_RGB565_PACKED = 0,
++ MIPI_RGB565_LOOSELY,
++ MIPI_RGB565_CONFIG3,
++ MIPI_RGB666_PACKED,
++ MIPI_RGB666_LOOSELY,
++ MIPI_RGB888,
++};
++
++struct mipi_lcd_config {
++ u32 virtual_ch;
++ u32 data_lane_num;
++ /* device max DPHY clock in MHz unit */
++ u32 max_phy_clk;
++ enum mipi_dsi_dpi_fmt dpi_fmt;
++};
++
++struct mipi_dsi_info;
++struct mipi_dsi_lcd_callback {
++ /* callback for lcd panel operation */
++ void (*get_mipi_lcd_videomode)(struct fb_videomode **, int *,
++ struct mipi_lcd_config **);
++ int (*mipi_lcd_setup)(struct mipi_dsi_info *);
++
++};
++
++struct mipi_dsi_match_lcd {
++ char *lcd_panel;
++ struct mipi_dsi_lcd_callback lcd_callback;
++};
++
++struct mipi_dsi_bus_mux {
++ int reg;
++ int mask;
++ int (*get_mux) (int dev_id, int disp_id);
++};
++
++/* driver private data */
++struct mipi_dsi_info {
++ struct platform_device *pdev;
++ void __iomem *mmio_base;
++ struct regmap *regmap;
++ const struct mipi_dsi_bus_mux *bus_mux;
++ int dsi_power_on;
++ int lcd_inited;
++ u32 dphy_pll_config;
++ int dev_id;
++ int disp_id;
++ char *lcd_panel;
++ int irq;
++ struct clk *dphy_clk;
++ struct clk *cfg_clk;
++ struct mxc_dispdrv_handle *disp_mipi;
++ struct fb_videomode *mode;
++ struct regulator *disp_power_on;
++ struct mipi_lcd_config *lcd_config;
++ /* board related power control */
++ struct backlight_device *bl;
++ /* callback for lcd panel operation */
++ struct mipi_dsi_lcd_callback *lcd_callback;
++};
++
++int mipi_dsi_pkt_write(struct mipi_dsi_info *mipi,
++ u8 data_type, const u32 *buf, int len);
++int mipi_dsi_pkt_read(struct mipi_dsi_info *mipi,
++ u8 data_type, u32 *buf, int len);
++int mipi_dsi_dcs_cmd(struct mipi_dsi_info *mipi,
++ u8 cmd, const u32 *param, int num);
++
++#ifdef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++void mipid_hx8369_get_lcd_videomode(struct fb_videomode **mode, int *size,
++ struct mipi_lcd_config **data);
++int mipid_hx8369_lcd_setup(struct mipi_dsi_info *);
++#endif
++
++#ifndef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++#error "Please configure MIPI LCD panel, we cannot find one!"
++#endif
++
++#endif
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxc_dispdrv.c linux-linaro-stable-mx6/drivers/video/mxc/mxc_dispdrv.c
+--- linux-3.10.30.orig/drivers/video/mxc/mxc_dispdrv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxc_dispdrv.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,150 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_dispdrv.c
++ * @brief mxc display driver framework.
++ *
++ * A display device driver could call mxc_dispdrv_register(drv) in its dev_probe() function.
++ * Move all dev_probe() things into mxc_dispdrv_driver->init(), init() function should init
++ * and feedback setting;
++ * Necessary deferred operations can be done in mxc_dispdrv_driver->post_init(),
++ * after dev_id and disp_id pass usage check;
++ * Move all dev_remove() things into mxc_dispdrv_driver->deinit();
++ * Move all dev_suspend() things into fb_notifier for SUSPEND, if there is;
++ * Move all dev_resume() things into fb_notifier for RESUME, if there is;
++ *
++ * ipuv3 fb driver could call mxc_dispdrv_gethandle(name, setting) before a fb
++ * need be added, with fbi param passing by setting, after
++ * mxc_dispdrv_gethandle() return, FB driver should get the basic setting
++ * about fbi info and ipuv3-hw (ipu_id and disp_id).
++ *
++ * @ingroup Framebuffer
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/string.h>
++#include "mxc_dispdrv.h"
++
++static LIST_HEAD(dispdrv_list);
++static DEFINE_MUTEX(dispdrv_lock);
++
++struct mxc_dispdrv_entry {
++ /* Note: drv always the first element */
++ struct mxc_dispdrv_driver *drv;
++ bool active;
++ void *priv;
++ struct list_head list;
++};
++
++struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv)
++{
++ struct mxc_dispdrv_entry *new;
++
++ mutex_lock(&dispdrv_lock);
++
++ new = kzalloc(sizeof(struct mxc_dispdrv_entry), GFP_KERNEL);
++ if (!new) {
++ mutex_unlock(&dispdrv_lock);
++ return ERR_PTR(-ENOMEM);
++ }
++
++ new->drv = drv;
++ list_add_tail(&new->list, &dispdrv_list);
++
++ mutex_unlock(&dispdrv_lock);
++
++ return (struct mxc_dispdrv_handle *)new;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_register);
++
++int mxc_dispdrv_unregister(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ mutex_lock(&dispdrv_lock);
++ list_del(&entry->list);
++ mutex_unlock(&dispdrv_lock);
++ kfree(entry);
++ return 0;
++ } else
++ return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_unregister);
++
++struct mxc_dispdrv_handle *mxc_dispdrv_gethandle(char *name,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret, found = 0;
++ struct mxc_dispdrv_entry *entry;
++
++ mutex_lock(&dispdrv_lock);
++ list_for_each_entry(entry, &dispdrv_list, list) {
++ if (!strcmp(entry->drv->name, name) && (entry->drv->init)) {
++ ret = entry->drv->init((struct mxc_dispdrv_handle *)
++ entry, setting);
++ if (ret >= 0) {
++ entry->active = true;
++ found = 1;
++ break;
++ }
++ }
++ }
++ mutex_unlock(&dispdrv_lock);
++
++ return found ? (struct mxc_dispdrv_handle *)entry:ERR_PTR(-ENODEV);
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_gethandle);
++
++void mxc_dispdrv_puthandle(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ mutex_lock(&dispdrv_lock);
++ if (entry && entry->active && entry->drv->deinit) {
++ entry->drv->deinit(handle);
++ entry->active = false;
++ }
++ mutex_unlock(&dispdrv_lock);
++
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_puthandle);
++
++int mxc_dispdrv_setdata(struct mxc_dispdrv_handle *handle, void *data)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ entry->priv = data;
++ return 0;
++ } else
++ return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_setdata);
++
++void *mxc_dispdrv_getdata(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ return entry->priv;
++ } else
++ return ERR_PTR(-EINVAL);
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_getdata);
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxc_dispdrv.h linux-linaro-stable-mx6/drivers/video/mxc/mxc_dispdrv.h
+--- linux-3.10.30.orig/drivers/video/mxc/mxc_dispdrv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxc_dispdrv.h 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,54 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __MXC_DISPDRV_H__
++#define __MXC_DISPDRV_H__
++#include <linux/fb.h>
++
++struct mxc_dispdrv_handle {
++ struct mxc_dispdrv_driver *drv;
++};
++
++struct mxc_dispdrv_setting {
++ /*input-feedback parameter*/
++ struct fb_info *fbi;
++ int if_fmt;
++ int default_bpp;
++ char *dft_mode_str;
++
++ /*feedback parameter*/
++ int dev_id;
++ int disp_id;
++};
++
++struct mxc_dispdrv_driver {
++ const char *name;
++ int (*init) (struct mxc_dispdrv_handle *, struct mxc_dispdrv_setting *);
++ /* deferred operations after dev_id and disp_id pass usage check */
++ int (*post_init) (struct mxc_dispdrv_handle *, int dev_id, int disp_id);
++ void (*deinit) (struct mxc_dispdrv_handle *);
++ /* display driver enable function for extension */
++ int (*enable) (struct mxc_dispdrv_handle *);
++ /* display driver disable function, called at early part of fb_blank */
++ void (*disable) (struct mxc_dispdrv_handle *);
++ /* display driver setup function, called at early part of fb_set_par */
++ int (*setup) (struct mxc_dispdrv_handle *, struct fb_info *fbi);
++};
++
++struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv);
++int mxc_dispdrv_unregister(struct mxc_dispdrv_handle *handle);
++struct mxc_dispdrv_handle *mxc_dispdrv_gethandle(char *name,
++ struct mxc_dispdrv_setting *setting);
++void mxc_dispdrv_puthandle(struct mxc_dispdrv_handle *handle);
++int mxc_dispdrv_setdata(struct mxc_dispdrv_handle *handle, void *data);
++void *mxc_dispdrv_getdata(struct mxc_dispdrv_handle *handle);
++#endif
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxc_edid.c linux-linaro-stable-mx6/drivers/video/mxc/mxc_edid.c
+--- linux-3.10.30.orig/drivers/video/mxc/mxc_edid.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxc_edid.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,762 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxc_edid.c
++ *
++ * @brief MXC EDID driver
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/i2c.h>
++#include <linux/fb.h>
++#include <video/mxc_edid.h>
++#include "../edid.h"
++
++#undef DEBUG /* define this for verbose EDID parsing output */
++#ifdef DEBUG
++#define DPRINTK(fmt, args...) printk(fmt, ## args)
++#else
++#define DPRINTK(fmt, args...)
++#endif
++
++const struct fb_videomode mxc_cea_mode[64] = {
++ /* #1: 640x480p@59.94/60Hz 4:3 */
++ [1] = {
++ NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #2: 720x480p@59.94/60Hz 4:3 */
++ [2] = {
++ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #3: 720x480p@59.94/60Hz 16:9 */
++ [3] = {
++ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #4: 1280x720p@59.94/60Hz 16:9 */
++ [4] = {
++ NULL, 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++ /* #5: 1920x1080i@59.94/60Hz 16:9 */
++ [5] = {
++ NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #6: 720(1440)x480iH@59.94/60Hz 4:3 */
++ [6] = {
++ NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #7: 720(1440)x480iH@59.94/60Hz 16:9 */
++ [7] = {
++ NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #8: 720(1440)x240pH@59.94/60Hz 4:3 */
++ [8] = {
++ NULL, 60, 1440, 240, 37108, 114, 38, 15, 4, 124, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #9: 720(1440)x240pH@59.94/60Hz 16:9 */
++ [9] = {
++ NULL, 60, 1440, 240, 37108, 114, 38, 15, 4, 124, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #14: 1440x480p@59.94/60Hz 4:3 */
++ [14] = {
++ NULL, 60, 1440, 480, 18500, 120, 32, 30, 9, 124, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #15: 1440x480p@59.94/60Hz 16:9 */
++ [15] = {
++ NULL, 60, 1440, 480, 18500, 120, 32, 30, 9, 124, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #16: 1920x1080p@60Hz 16:9 */
++ [16] = {
++ NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #17: 720x576pH@50Hz 4:3 */
++ [17] = {
++ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #18: 720x576pH@50Hz 16:9 */
++ [18] = {
++ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #19: 1280x720p@50Hz */
++ [19] = {
++ NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #20: 1920x1080i@50Hz */
++ [20] = {
++ NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #23: 720(1440)x288pH@50Hz 4:3 */
++ [23] = {
++ NULL, 50, 1440, 288, 37037, 138, 24, 19, 2, 126, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #24: 720(1440)x288pH@50Hz 16:9 */
++ [24] = {
++ NULL, 50, 1440, 288, 37037, 138, 24, 19, 2, 126, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #29: 720(1440)x576pH@50Hz 4:3 */
++ [29] = {
++ NULL, 50, 1440, 576, 18518, 136, 24, 39, 5, 128, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #30: 720(1440)x576pH@50Hz 16:9 */
++ [30] = {
++ NULL, 50, 1440, 576, 18518, 136, 24, 39, 5, 128, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #31: 1920x1080p@50Hz */
++ [31] = {
++ NULL, 50, 1920, 1080, 6734, 148, 528, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #32: 1920x1080p@23.98/24Hz */
++ [32] = {
++ NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #33: 1920x1080p@25Hz */
++ [33] = {
++ NULL, 25, 1920, 1080, 13468, 148, 528, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #34: 1920x1080p@30Hz */
++ [34] = {
++ NULL, 30, 1920, 1080, 13468, 148, 88, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #41: 1280x720p@100Hz 16:9 */
++ [41] = {
++ NULL, 100, 1280, 720, 6734, 220, 440, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++ /* #47: 1280x720p@119.88/120Hz 16:9 */
++ [47] = {
++ NULL, 120, 1280, 720, 6734, 220, 110, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++};
++
++/*
++ * We have a special version of fb_mode_is_equal that ignores
++ * pixclock, since for many CEA modes, 2 frequencies are supported
++ * e.g. 640x480 @ 60Hz or 59.94Hz
++ */
++int mxc_edid_fb_mode_is_equal(bool use_aspect,
++ const struct fb_videomode *mode1,
++ const struct fb_videomode *mode2)
++{
++ u32 mask;
++
++ if (use_aspect)
++ mask = ~0;
++ else
++ mask = ~FB_VMODE_ASPECT_MASK;
++
++ return (mode1->xres == mode2->xres &&
++ mode1->yres == mode2->yres &&
++ mode1->hsync_len == mode2->hsync_len &&
++ mode1->vsync_len == mode2->vsync_len &&
++ mode1->left_margin == mode2->left_margin &&
++ mode1->right_margin == mode2->right_margin &&
++ mode1->upper_margin == mode2->upper_margin &&
++ mode1->lower_margin == mode2->lower_margin &&
++ mode1->sync == mode2->sync &&
++ /* refresh check, 59.94Hz and 60Hz have the same parameter
++ * in struct of mxc_cea_mode */
++ abs(mode1->refresh - mode2->refresh) <= 1 &&
++ (mode1->vmode & mask) == (mode2->vmode & mask));
++}
++
++static void get_detailed_timing(unsigned char *block,
++ struct fb_videomode *mode)
++{
++ mode->xres = H_ACTIVE;
++ mode->yres = V_ACTIVE;
++ mode->pixclock = PIXEL_CLOCK;
++ mode->pixclock /= 1000;
++ mode->pixclock = KHZ2PICOS(mode->pixclock);
++ mode->right_margin = H_SYNC_OFFSET;
++ mode->left_margin = (H_ACTIVE + H_BLANKING) -
++ (H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
++ mode->upper_margin = V_BLANKING - V_SYNC_OFFSET -
++ V_SYNC_WIDTH;
++ mode->lower_margin = V_SYNC_OFFSET;
++ mode->hsync_len = H_SYNC_WIDTH;
++ mode->vsync_len = V_SYNC_WIDTH;
++ if (HSYNC_POSITIVE)
++ mode->sync |= FB_SYNC_HOR_HIGH_ACT;
++ if (VSYNC_POSITIVE)
++ mode->sync |= FB_SYNC_VERT_HIGH_ACT;
++ mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) *
++ (V_ACTIVE + V_BLANKING));
++ if (INTERLACED) {
++ mode->yres *= 2;
++ mode->upper_margin *= 2;
++ mode->lower_margin *= 2;
++ mode->vsync_len *= 2;
++ mode->vmode |= FB_VMODE_INTERLACED;
++ }
++ mode->flag = FB_MODE_IS_DETAILED;
++
++ if ((H_SIZE / 16) == (V_SIZE / 9))
++ mode->vmode |= FB_VMODE_ASPECT_16_9;
++ else if ((H_SIZE / 4) == (V_SIZE / 3))
++ mode->vmode |= FB_VMODE_ASPECT_4_3;
++ else if ((mode->xres / 16) == (mode->yres / 9))
++ mode->vmode |= FB_VMODE_ASPECT_16_9;
++ else if ((mode->xres / 4) == (mode->yres / 3))
++ mode->vmode |= FB_VMODE_ASPECT_4_3;
++
++ if (mode->vmode & FB_VMODE_ASPECT_16_9)
++ DPRINTK("Aspect ratio: 16:9\n");
++ if (mode->vmode & FB_VMODE_ASPECT_4_3)
++ DPRINTK("Aspect ratio: 4:3\n");
++ DPRINTK(" %d MHz ", PIXEL_CLOCK/1000000);
++ DPRINTK("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET,
++ H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING);
++ DPRINTK("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET,
++ V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING);
++ DPRINTK("%sHSync %sVSync\n\n", (HSYNC_POSITIVE) ? "+" : "-",
++ (VSYNC_POSITIVE) ? "+" : "-");
++}
++
++int mxc_edid_parse_ext_blk(unsigned char *edid,
++ struct mxc_edid_cfg *cfg,
++ struct fb_monspecs *specs)
++{
++ char detail_timing_desc_offset;
++ struct fb_videomode *mode, *m;
++ unsigned char index = 0x0;
++ unsigned char *block;
++ int i, num = 0, revision;
++
++ if (edid[index++] != 0x2) /* only support cea ext block now */
++ return -1;
++ revision = edid[index++];
++ DPRINTK("cea extent revision %d\n", revision);
++ mode = kzalloc(50 * sizeof(struct fb_videomode), GFP_KERNEL);
++ if (mode == NULL)
++ return -1;
++
++ detail_timing_desc_offset = edid[index++];
++
++ if (revision >= 2) {
++ cfg->cea_underscan = (edid[index] >> 7) & 0x1;
++ cfg->cea_basicaudio = (edid[index] >> 6) & 0x1;
++ cfg->cea_ycbcr444 = (edid[index] >> 5) & 0x1;
++ cfg->cea_ycbcr422 = (edid[index] >> 4) & 0x1;
++
++ DPRINTK("CEA underscan %d\n", cfg->cea_underscan);
++ DPRINTK("CEA basicaudio %d\n", cfg->cea_basicaudio);
++ DPRINTK("CEA ycbcr444 %d\n", cfg->cea_ycbcr444);
++ DPRINTK("CEA ycbcr422 %d\n", cfg->cea_ycbcr422);
++ }
++
++ if (revision >= 3) {
++ /* short desc */
++ DPRINTK("CEA Short desc timmings\n");
++ index++;
++ while (index < detail_timing_desc_offset) {
++ unsigned char tagcode, blklen;
++
++ tagcode = (edid[index] >> 5) & 0x7;
++ blklen = (edid[index]) & 0x1f;
++
++ DPRINTK("Tagcode %x Len %d\n", tagcode, blklen);
++
++ switch (tagcode) {
++ case 0x2: /*Video data block*/
++ {
++ int cea_idx;
++ i = 0;
++ while (i < blklen) {
++ index++;
++ cea_idx = edid[index] & 0x7f;
++ if (cea_idx < ARRAY_SIZE(mxc_cea_mode) &&
++ (mxc_cea_mode[cea_idx].xres)) {
++ DPRINTK("Support CEA Format #%d\n", cea_idx);
++ mode[num] = mxc_cea_mode[cea_idx];
++ mode[num].flag |= FB_MODE_IS_STANDARD;
++ num++;
++ }
++ i++;
++ }
++ break;
++ }
++ case 0x3: /*Vendor specific data*/
++ {
++ unsigned char IEEE_reg_iden[3];
++ unsigned char deep_color;
++ unsigned char latency_present;
++ unsigned char I_latency_present;
++ unsigned char hdmi_video_present;
++ unsigned char hdmi_3d_present;
++ unsigned char hdmi_3d_multi_present;
++ unsigned char hdmi_vic_len;
++ unsigned char hdmi_3d_len;
++ unsigned char index_inc = 0;
++ unsigned char vsd_end;
++
++ vsd_end = index + blklen;
++
++ IEEE_reg_iden[0] = edid[index+1];
++ IEEE_reg_iden[1] = edid[index+2];
++ IEEE_reg_iden[2] = edid[index+3];
++ cfg->physical_address[0] = (edid[index+4] & 0xf0) >> 4;
++ cfg->physical_address[1] = (edid[index+4] & 0x0f);
++ cfg->physical_address[2] = (edid[index+5] & 0xf0) >> 4;
++ cfg->physical_address[3] = (edid[index+5] & 0x0f);
++
++ if ((IEEE_reg_iden[0] == 0x03) &&
++ (IEEE_reg_iden[1] == 0x0c) &&
++ (IEEE_reg_iden[2] == 0x00))
++ cfg->hdmi_cap = 1;
++
++ if (blklen > 5) {
++ deep_color = edid[index+6];
++ if (deep_color & 0x80)
++ cfg->vsd_support_ai = true;
++ if (deep_color & 0x40)
++ cfg->vsd_dc_48bit = true;
++ if (deep_color & 0x20)
++ cfg->vsd_dc_36bit = true;
++ if (deep_color & 0x10)
++ cfg->vsd_dc_30bit = true;
++ if (deep_color & 0x08)
++ cfg->vsd_dc_y444 = true;
++ if (deep_color & 0x01)
++ cfg->vsd_dvi_dual = true;
++ }
++
++ DPRINTK("VSD hdmi capability %d\n", cfg->hdmi_cap);
++ DPRINTK("VSD support ai %d\n", cfg->vsd_support_ai);
++ DPRINTK("VSD support deep color 48bit %d\n", cfg->vsd_dc_48bit);
++ DPRINTK("VSD support deep color 36bit %d\n", cfg->vsd_dc_36bit);
++ DPRINTK("VSD support deep color 30bit %d\n", cfg->vsd_dc_30bit);
++ DPRINTK("VSD support deep color y444 %d\n", cfg->vsd_dc_y444);
++ DPRINTK("VSD support dvi dual %d\n", cfg->vsd_dvi_dual);
++
++ if (blklen > 6)
++ cfg->vsd_max_tmdsclk_rate = edid[index+7] * 5;
++ DPRINTK("VSD MAX TMDS CLOCK RATE %d\n", cfg->vsd_max_tmdsclk_rate);
++
++ if (blklen > 7) {
++ latency_present = edid[index+8] >> 7;
++ I_latency_present = (edid[index+8] & 0x40) >> 6;
++ hdmi_video_present = (edid[index+8] & 0x20) >> 5;
++ cfg->vsd_cnc3 = (edid[index+8] & 0x8) >> 3;
++ cfg->vsd_cnc2 = (edid[index+8] & 0x4) >> 2;
++ cfg->vsd_cnc1 = (edid[index+8] & 0x2) >> 1;
++ cfg->vsd_cnc0 = edid[index+8] & 0x1;
++
++ DPRINTK("VSD cnc0 %d\n", cfg->vsd_cnc0);
++ DPRINTK("VSD cnc1 %d\n", cfg->vsd_cnc1);
++ DPRINTK("VSD cnc2 %d\n", cfg->vsd_cnc2);
++ DPRINTK("VSD cnc3 %d\n", cfg->vsd_cnc3);
++ DPRINTK("latency_present %d\n", latency_present);
++ DPRINTK("I_latency_present %d\n", I_latency_present);
++ DPRINTK("hdmi_video_present %d\n", hdmi_video_present);
++
++ } else {
++ index += blklen;
++ break;
++ }
++
++ index += 9;
++
++ /*latency present */
++ if (latency_present) {
++ cfg->vsd_video_latency = edid[index++];
++ cfg->vsd_audio_latency = edid[index++];
++
++ if (I_latency_present) {
++ cfg->vsd_I_video_latency = edid[index++];
++ cfg->vsd_I_audio_latency = edid[index++];
++ } else {
++ cfg->vsd_I_video_latency = cfg->vsd_video_latency;
++ cfg->vsd_I_audio_latency = cfg->vsd_audio_latency;
++ }
++
++ DPRINTK("VSD latency video_latency %d\n", cfg->vsd_video_latency);
++ DPRINTK("VSD latency audio_latency %d\n", cfg->vsd_audio_latency);
++ DPRINTK("VSD latency I_video_latency %d\n", cfg->vsd_I_video_latency);
++ DPRINTK("VSD latency I_audio_latency %d\n", cfg->vsd_I_audio_latency);
++ }
++
++ if (hdmi_video_present) {
++ hdmi_3d_present = edid[index] >> 7;
++ hdmi_3d_multi_present = (edid[index] & 0x60) >> 5;
++ index++;
++ hdmi_vic_len = (edid[index] & 0xe0) >> 5;
++ hdmi_3d_len = edid[index] & 0x1f;
++ index++;
++
++ DPRINTK("hdmi_3d_present %d\n", hdmi_3d_present);
++ DPRINTK("hdmi_3d_multi_present %d\n", hdmi_3d_multi_present);
++ DPRINTK("hdmi_vic_len %d\n", hdmi_vic_len);
++ DPRINTK("hdmi_3d_len %d\n", hdmi_3d_len);
++
++ if (hdmi_vic_len > 0) {
++ for (i = 0; i < hdmi_vic_len; i++) {
++ cfg->hdmi_vic[i] = edid[index++];
++ DPRINTK("HDMI_vic=%d\n", cfg->hdmi_vic[i]);
++ }
++ }
++
++ if (hdmi_3d_len > 0) {
++ if (hdmi_3d_present) {
++ if (hdmi_3d_multi_present == 0x1) {
++ cfg->hdmi_3d_struct_all = (edid[index] << 8) | edid[index+1];
++ index_inc = 2;
++ } else if (hdmi_3d_multi_present == 0x2) {
++ cfg->hdmi_3d_struct_all = (edid[index] << 8) | edid[index+1];
++ cfg->hdmi_3d_mask_all = (edid[index+2] << 8) | edid[index+3];
++ index_inc = 4;
++ } else
++ index_inc = 0;
++ }
++
++ DPRINTK("HDMI 3d struct all =0x%x\n", cfg->hdmi_3d_struct_all);
++ DPRINTK("HDMI 3d mask all =0x%x\n", cfg->hdmi_3d_mask_all);
++
++ /* Read 2D vic 3D_struct */
++ if ((hdmi_3d_len - index_inc) > 0) {
++ DPRINTK("Support 3D video format\n");
++ i = 0;
++ while ((hdmi_3d_len - index_inc) > 0) {
++
++ cfg->hdmi_3d_format[i].vic_order_2d = edid[index+index_inc] >> 4;
++ cfg->hdmi_3d_format[i].struct_3d = edid[index+index_inc] & 0x0f;
++ index_inc++;
++
++ if (cfg->hdmi_3d_format[i].struct_3d == 8) {
++ cfg->hdmi_3d_format[i].detail_3d = edid[index+index_inc] >> 4;
++ index_inc++;
++ } else if (cfg->hdmi_3d_format[i].struct_3d > 8) {
++ cfg->hdmi_3d_format[i].detail_3d = 0;
++ index_inc++;
++ }
++
++ DPRINTK("vic_order_2d=%d, 3d_struct=%d, 3d_detail=0x%x\n",
++ cfg->hdmi_3d_format[i].vic_order_2d,
++ cfg->hdmi_3d_format[i].struct_3d,
++ cfg->hdmi_3d_format[i].detail_3d);
++ i++;
++ }
++ }
++ index += index_inc;
++ }
++ }
++
++ index = vsd_end;
++
++ break;
++ }
++ case 0x1: /*Audio data block*/
++ {
++ u8 audio_format, max_ch, byte1, byte2, byte3;
++
++ i = 0;
++ cfg->max_channels = 0;
++ cfg->sample_rates = 0;
++ cfg->sample_sizes = 0;
++
++ while (i < blklen) {
++ byte1 = edid[index + 1];
++ byte2 = edid[index + 2];
++ byte3 = edid[index + 3];
++ index += 3;
++ i += 3;
++
++ audio_format = byte1 >> 3;
++ max_ch = (byte1 & 0x07) + 1;
++
++ DPRINTK("Audio Format Descriptor : %2d\n", audio_format);
++ DPRINTK("Max Number of Channels : %2d\n", max_ch);
++ DPRINTK("Sample Rates : %02x\n", byte2);
++
++ /* ALSA can't specify specific compressed
++ * formats, so only care about PCM for now. */
++ if (audio_format == AUDIO_CODING_TYPE_LPCM) {
++ if (max_ch > cfg->max_channels)
++ cfg->max_channels = max_ch;
++
++ cfg->sample_rates |= byte2;
++ cfg->sample_sizes |= byte3 & 0x7;
++ DPRINTK("Sample Sizes : %02x\n",
++ byte3 & 0x7);
++ }
++ }
++ break;
++ }
++ case 0x4: /*Speaker allocation block*/
++ {
++ i = 0;
++ while (i < blklen) {
++ cfg->speaker_alloc = edid[index + 1];
++ index += 3;
++ i += 3;
++ DPRINTK("Speaker Alloc : %02x\n", cfg->speaker_alloc);
++ }
++ break;
++ }
++ case 0x7: /*User extended block*/
++ default:
++ /* skip */
++ DPRINTK("Not handle block, tagcode = 0x%x\n", tagcode);
++ index += blklen;
++ break;
++ }
++
++ index++;
++ }
++ }
++
++ /* long desc */
++ DPRINTK("CEA long desc timmings\n");
++ index = detail_timing_desc_offset;
++ block = edid + index;
++ while (index < (EDID_LENGTH - DETAILED_TIMING_DESCRIPTION_SIZE)) {
++ if (!(block[0] == 0x00 && block[1] == 0x00)) {
++ get_detailed_timing(block, &mode[num]);
++ num++;
++ }
++ block += DETAILED_TIMING_DESCRIPTION_SIZE;
++ index += DETAILED_TIMING_DESCRIPTION_SIZE;
++ }
++
++ if (!num) {
++ kfree(mode);
++ return 0;
++ }
++
++ m = kmalloc((num + specs->modedb_len) *
++ sizeof(struct fb_videomode), GFP_KERNEL);
++ if (!m)
++ return 0;
++
++ if (specs->modedb_len) {
++ memmove(m, specs->modedb,
++ specs->modedb_len * sizeof(struct fb_videomode));
++ kfree(specs->modedb);
++ }
++ memmove(m+specs->modedb_len, mode,
++ num * sizeof(struct fb_videomode));
++ kfree(mode);
++
++ specs->modedb_len += num;
++ specs->modedb = m;
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_edid_parse_ext_blk);
++
++static int mxc_edid_readblk(struct i2c_adapter *adp,
++ unsigned short addr, unsigned char *edid)
++{
++ int ret = 0, extblknum = 0;
++ unsigned char regaddr = 0x0;
++ struct i2c_msg msg[2] = {
++ {
++ .addr = addr,
++ .flags = 0,
++ .len = 1,
++ .buf = &regaddr,
++ }, {
++ .addr = addr,
++ .flags = I2C_M_RD,
++ .len = EDID_LENGTH,
++ .buf = edid,
++ },
++ };
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++
++ if (edid[1] == 0x00)
++ return -ENOENT;
++
++ extblknum = edid[0x7E];
++
++ if (extblknum) {
++ regaddr = 128;
++ msg[1].buf = edid + EDID_LENGTH;
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID ext block\n");
++ return -EIO;
++ }
++ }
++
++ return extblknum;
++}
++
++static int mxc_edid_readsegblk(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, int seg_num)
++{
++ int ret = 0;
++ unsigned char segment = 0x1, regaddr = 0;
++ struct i2c_msg msg[3] = {
++ {
++ .addr = 0x30,
++ .flags = 0,
++ .len = 1,
++ .buf = &segment,
++ }, {
++ .addr = addr,
++ .flags = 0,
++ .len = 1,
++ .buf = &regaddr,
++ }, {
++ .addr = addr,
++ .flags = I2C_M_RD,
++ .len = EDID_LENGTH,
++ .buf = edid,
++ },
++ };
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++
++ if (seg_num == 2) {
++ regaddr = 128;
++ msg[2].buf = edid + EDID_LENGTH;
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++ }
++
++ return ret;
++}
++
++int mxc_edid_var_to_vic(struct fb_var_screeninfo *var)
++{
++ int i;
++ struct fb_videomode m;
++
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ fb_var_to_videomode(&m, var);
++ if (mxc_edid_fb_mode_is_equal(false, &m, &mxc_cea_mode[i]))
++ break;
++ }
++
++ if (i == ARRAY_SIZE(mxc_cea_mode))
++ return 0;
++
++ return i;
++}
++EXPORT_SYMBOL(mxc_edid_var_to_vic);
++
++int mxc_edid_mode_to_vic(const struct fb_videomode *mode)
++{
++ int i;
++ bool use_aspect = (mode->vmode & FB_VMODE_ASPECT_MASK);
++
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ if (mxc_edid_fb_mode_is_equal(use_aspect, mode, &mxc_cea_mode[i]))
++ break;
++ }
++
++ if (i == ARRAY_SIZE(mxc_cea_mode))
++ return 0;
++
++ return i;
++}
++EXPORT_SYMBOL(mxc_edid_mode_to_vic);
++
++/* make sure edid has 512 bytes*/
++int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi)
++{
++ int ret = 0, extblknum;
++ if (!adp || !edid || !cfg || !fbi)
++ return -EINVAL;
++
++ memset(edid, 0, EDID_LENGTH*4);
++ memset(cfg, 0, sizeof(struct mxc_edid_cfg));
++
++ extblknum = mxc_edid_readblk(adp, addr, edid);
++ if (extblknum < 0)
++ return extblknum;
++
++ /* edid first block parsing */
++ memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
++ fb_edid_to_monspecs(edid, &fbi->monspecs);
++
++ if (extblknum) {
++ int i;
++
++ /* need read segment block? */
++ if (extblknum > 1) {
++ ret = mxc_edid_readsegblk(adp, addr,
++ edid + EDID_LENGTH*2, extblknum - 1);
++ if (ret < 0)
++ return ret;
++ }
++
++ for (i = 1; i <= extblknum; i++)
++ /* edid ext block parsing */
++ mxc_edid_parse_ext_blk(edid + i*EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_edid_read);
++
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxc_epdc_fb.c linux-linaro-stable-mx6/drivers/video/mxc/mxc_epdc_fb.c
+--- linux-3.10.30.orig/drivers/video/mxc/mxc_epdc_fb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxc_epdc_fb.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,5541 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * Based on STMP378X LCDIF
++ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++#include <linux/busfreq-imx6.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/uaccess.h>
++#include <linux/cpufreq.h>
++#include <linux/firmware.h>
++#include <linux/kthread.h>
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++#include <linux/pm_runtime.h>
++#include <linux/mxcfb.h>
++#include <linux/mxcfb_epdc.h>
++#include <linux/gpio.h>
++#include <linux/regulator/driver.h>
++#include <linux/fsl_devices.h>
++#include <linux/bitops.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_data/dma-imx.h>
++#include <asm/cacheflush.h>
++
++#include "epdc_regs.h"
++
++/*
++ * Enable this define to have a default panel
++ * loaded during driver initialization
++ */
++/*#define DEFAULT_PANEL_HW_INIT*/
++
++#define NUM_SCREENS_MIN 2
++
++#define EPDC_V1_NUM_LUTS 16
++#define EPDC_V1_MAX_NUM_UPDATES 20
++#define EPDC_V2_NUM_LUTS 64
++#define EPDC_V2_MAX_NUM_UPDATES 64
++#define EPDC_MAX_NUM_BUFFERS 2
++#define INVALID_LUT (-1)
++#define DRY_RUN_NO_LUT 100
++
++/* Maximum update buffer image width due to v2.0 and v2.1 errata ERR005313. */
++#define EPDC_V2_MAX_UPDATE_WIDTH 2047
++#define EPDC_V2_ROTATION_ALIGNMENT 8
++
++#define DEFAULT_TEMP_INDEX 0
++#define DEFAULT_TEMP 20 /* room temp in deg Celsius */
++
++#define INIT_UPDATE_MARKER 0x12345678
++#define PAN_UPDATE_MARKER 0x12345679
++
++#define POWER_STATE_OFF 0
++#define POWER_STATE_ON 1
++
++#define MERGE_OK 0
++#define MERGE_FAIL 1
++#define MERGE_BLOCK 2
++
++static unsigned long default_bpp = 16;
++
++struct update_marker_data {
++ struct list_head full_list;
++ struct list_head upd_list;
++ u32 update_marker;
++ struct completion update_completion;
++ int lut_num;
++ bool collision_test;
++ bool waiting;
++};
++
++struct update_desc_list {
++ struct list_head list;
++ struct mxcfb_update_data upd_data;/* Update parameters */
++ u32 epdc_offs; /* Added to buffer ptr to resolve alignment */
++ u32 epdc_stride; /* Depends on rotation & whether we skip PxP */
++ struct list_head upd_marker_list; /* List of markers for this update */
++ u32 update_order; /* Numeric ordering value for update */
++};
++
++/* This structure represents a list node containing both
++ * a memory region allocated as an output buffer for the PxP
++ * update processing task, and the update description (mode, region, etc.) */
++struct update_data_list {
++ struct list_head list;
++ dma_addr_t phys_addr; /* Pointer to phys address of processed Y buf */
++ void *virt_addr;
++ struct update_desc_list *update_desc;
++ int lut_num; /* Assigned before update is processed into working buffer */
++ u64 collision_mask; /* Set when update creates collision */
++ /* Mask of the LUTs the update collides with */
++};
++
++struct mxc_epdc_fb_data {
++ struct fb_info info;
++ struct fb_var_screeninfo epdc_fb_var; /* Internal copy of screeninfo
++ so we can sync changes to it */
++ u32 pseudo_palette[16];
++ char fw_str[24];
++ struct list_head list;
++ struct imx_epdc_fb_mode *cur_mode;
++ struct imx_epdc_fb_platform_data *pdata;
++ int blank;
++ u32 max_pix_size;
++ ssize_t map_size;
++ dma_addr_t phys_start;
++ u32 fb_offset;
++ int default_bpp;
++ int native_width;
++ int native_height;
++ int num_screens;
++ int epdc_irq;
++ struct device *dev;
++ int power_state;
++ int wait_for_powerdown;
++ struct completion powerdown_compl;
++ struct clk *epdc_clk_axi;
++ struct clk *epdc_clk_pix;
++ struct regulator *display_regulator;
++ struct regulator *vcom_regulator;
++ struct regulator *v3p3_regulator;
++ bool fw_default_load;
++ int rev;
++
++ /* FB elements related to EPDC updates */
++ int num_luts;
++ int max_num_updates;
++ bool in_init;
++ bool hw_ready;
++ bool hw_initializing;
++ bool waiting_for_idle;
++ u32 auto_mode;
++ u32 upd_scheme;
++ struct list_head upd_pending_list;
++ struct list_head upd_buf_queue;
++ struct list_head upd_buf_free_list;
++ struct list_head upd_buf_collision_list;
++ struct update_data_list *cur_update;
++ struct mutex queue_mutex;
++ int trt_entries;
++ int temp_index;
++ u8 *temp_range_bounds;
++ struct mxcfb_waveform_modes wv_modes;
++ bool wv_modes_update;
++ u32 *waveform_buffer_virt;
++ u32 waveform_buffer_phys;
++ u32 waveform_buffer_size;
++ u32 *working_buffer_virt;
++ u32 working_buffer_phys;
++ u32 working_buffer_size;
++ dma_addr_t *phys_addr_updbuf;
++ void **virt_addr_updbuf;
++ u32 upd_buffer_num;
++ u32 max_num_buffers;
++ dma_addr_t phys_addr_copybuf; /* Phys address of copied update data */
++ void *virt_addr_copybuf; /* Used for PxP SW workaround */
++ u32 order_cnt;
++ struct list_head full_marker_list;
++ u32 *lut_update_order; /* Array size = number of luts */
++ u64 epdc_colliding_luts;
++ u64 luts_complete_wb;
++ struct completion updates_done;
++ struct delayed_work epdc_done_work;
++ struct workqueue_struct *epdc_submit_workqueue;
++ struct work_struct epdc_submit_work;
++ struct workqueue_struct *epdc_intr_workqueue;
++ struct work_struct epdc_intr_work;
++ bool waiting_for_wb;
++ bool waiting_for_lut;
++ bool waiting_for_lut15;
++ struct completion update_res_free;
++ struct completion lut15_free;
++ struct completion eof_event;
++ int eof_sync_period;
++ struct mutex power_mutex;
++ bool powering_down;
++ bool updates_active;
++ int pwrdown_delay;
++ unsigned long tce_prevent;
++ bool restrict_width; /* work around rev >=2.0 width and
++ stride restriction */
++
++ /* FB elements related to PxP DMA */
++ struct completion pxp_tx_cmpl;
++ struct pxp_channel *pxp_chan;
++ struct pxp_config_data pxp_conf;
++ struct dma_async_tx_descriptor *txd;
++ dma_cookie_t cookie;
++ struct scatterlist sg[2];
++ struct mutex pxp_mutex; /* protects access to PxP */
++};
++
++struct waveform_data_header {
++ unsigned int wi0;
++ unsigned int wi1;
++ unsigned int wi2;
++ unsigned int wi3;
++ unsigned int wi4;
++ unsigned int wi5;
++ unsigned int wi6;
++ unsigned int xwia:24;
++ unsigned int cs1:8;
++ unsigned int wmta:24;
++ unsigned int fvsn:8;
++ unsigned int luts:8;
++ unsigned int mc:8;
++ unsigned int trc:8;
++ unsigned int reserved0_0:8;
++ unsigned int eb:8;
++ unsigned int sb:8;
++ unsigned int reserved0_1:8;
++ unsigned int reserved0_2:8;
++ unsigned int reserved0_3:8;
++ unsigned int reserved0_4:8;
++ unsigned int reserved0_5:8;
++ unsigned int cs2:8;
++};
++
++struct mxcfb_waveform_data_file {
++ struct waveform_data_header wdh;
++ u32 *data; /* Temperature Range Table + Waveform Data */
++};
++
++static struct fb_videomode e60_v110_mode = {
++ .name = "E60_V110",
++ .refresh = 50,
++ .xres = 800,
++ .yres = 600,
++ .pixclock = 18604700,
++ .left_margin = 8,
++ .right_margin = 178,
++ .upper_margin = 4,
++ .lower_margin = 10,
++ .hsync_len = 20,
++ .vsync_len = 4,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ .flag = 0,
++};
++
++static struct fb_videomode e60_v220_mode = {
++ .name = "E60_V220",
++ .refresh = 85,
++ .xres = 800,
++ .yres = 600,
++ .pixclock = 30000000,
++ .left_margin = 8,
++ .right_margin = 164,
++ .upper_margin = 4,
++ .lower_margin = 8,
++ .hsync_len = 4,
++ .vsync_len = 1,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ .flag = 0,
++};
++
++static struct fb_videomode e060scm_mode = {
++ .name = "E060SCM",
++ .refresh = 85,
++ .xres = 800,
++ .yres = 600,
++ .pixclock = 26666667,
++ .left_margin = 8,
++ .right_margin = 100,
++ .upper_margin = 4,
++ .lower_margin = 8,
++ .hsync_len = 4,
++ .vsync_len = 1,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ .flag = 0,
++};
++
++static struct fb_videomode e97_v110_mode = {
++ .name = "E97_V110",
++ .refresh = 50,
++ .xres = 1200,
++ .yres = 825,
++ .pixclock = 32000000,
++ .left_margin = 12,
++ .right_margin = 128,
++ .upper_margin = 4,
++ .lower_margin = 10,
++ .hsync_len = 20,
++ .vsync_len = 4,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ .flag = 0,
++};
++
++static struct imx_epdc_fb_mode panel_modes[] = {
++ {
++ &e60_v110_mode,
++ 4, /* vscan_holdoff */
++ 10, /* sdoed_width */
++ 20, /* sdoed_delay */
++ 10, /* sdoez_width */
++ 20, /* sdoez_delay */
++ 428, /* gdclk_hp_offs */
++ 20, /* gdsp_offs */
++ 0, /* gdoe_offs */
++ 1, /* gdclk_offs */
++ 1, /* num_ce */
++ },
++ {
++ &e60_v220_mode,
++ 4, /* vscan_holdoff */
++ 10, /* sdoed_width */
++ 20, /* sdoed_delay */
++ 10, /* sdoez_width */
++ 20, /* sdoez_delay */
++ 465, /* gdclk_hp_offs */
++ 20, /* gdsp_offs */
++ 0, /* gdoe_offs */
++ 9, /* gdclk_offs */
++ 1, /* num_ce */
++ },
++ {
++ &e060scm_mode,
++ 4, /* vscan_holdoff */
++ 10, /* sdoed_width */
++ 20, /* sdoed_delay */
++ 10, /* sdoez_width */
++ 20, /* sdoez_delay */
++ 419, /* gdclk_hp_offs */
++ 20, /* gdsp_offs */
++ 0, /* gdoe_offs */
++ 5, /* gdclk_offs */
++ 1, /* num_ce */
++ },
++ {
++ &e97_v110_mode,
++ 8, /* vscan_holdoff */
++ 10, /* sdoed_width */
++ 20, /* sdoed_delay */
++ 10, /* sdoez_width */
++ 20, /* sdoez_delay */
++ 632, /* gdclk_hp_offs */
++ 20, /* gdsp_offs */
++ 0, /* gdoe_offs */
++ 1, /* gdclk_offs */
++ 3, /* num_ce */
++ }
++};
++
++static struct imx_epdc_fb_platform_data epdc_data = {
++ .epdc_mode = panel_modes,
++ .num_modes = ARRAY_SIZE(panel_modes),
++};
++
++void __iomem *epdc_base;
++
++struct mxc_epdc_fb_data *g_fb_data;
++
++/* forward declaration */
++static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data,
++ int temp);
++static void mxc_epdc_fb_flush_updates(struct mxc_epdc_fb_data *fb_data);
++static int mxc_epdc_fb_blank(int blank, struct fb_info *info);
++static int mxc_epdc_fb_init_hw(struct fb_info *info);
++static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
++ u32 src_width, u32 src_height,
++ struct mxcfb_rect *update_region);
++static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat);
++
++static void draw_mode0(struct mxc_epdc_fb_data *fb_data);
++static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data);
++
++static void do_dithering_processing_Y1_v1_0(
++ unsigned char *update_region_ptr,
++ struct mxcfb_rect *update_region,
++ unsigned long update_region_stride,
++ int *err_dist);
++static void do_dithering_processing_Y4_v1_0(
++ unsigned char *update_region_ptr,
++ struct mxcfb_rect *update_region,
++ unsigned long update_region_stride,
++ int *err_dist);
++
++#ifdef DEBUG
++static void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
++ struct pxp_config_data *pxp_conf)
++{
++ dev_info(fb_data->dev, "S0 fmt 0x%x",
++ pxp_conf->s0_param.pixel_fmt);
++ dev_info(fb_data->dev, "S0 width 0x%x",
++ pxp_conf->s0_param.width);
++ dev_info(fb_data->dev, "S0 height 0x%x",
++ pxp_conf->s0_param.height);
++ dev_info(fb_data->dev, "S0 ckey 0x%x",
++ pxp_conf->s0_param.color_key);
++ dev_info(fb_data->dev, "S0 ckey en 0x%x",
++ pxp_conf->s0_param.color_key_enable);
++
++ dev_info(fb_data->dev, "OL0 combine en 0x%x",
++ pxp_conf->ol_param[0].combine_enable);
++ dev_info(fb_data->dev, "OL0 fmt 0x%x",
++ pxp_conf->ol_param[0].pixel_fmt);
++ dev_info(fb_data->dev, "OL0 width 0x%x",
++ pxp_conf->ol_param[0].width);
++ dev_info(fb_data->dev, "OL0 height 0x%x",
++ pxp_conf->ol_param[0].height);
++ dev_info(fb_data->dev, "OL0 ckey 0x%x",
++ pxp_conf->ol_param[0].color_key);
++ dev_info(fb_data->dev, "OL0 ckey en 0x%x",
++ pxp_conf->ol_param[0].color_key_enable);
++ dev_info(fb_data->dev, "OL0 alpha 0x%x",
++ pxp_conf->ol_param[0].global_alpha);
++ dev_info(fb_data->dev, "OL0 alpha en 0x%x",
++ pxp_conf->ol_param[0].global_alpha_enable);
++ dev_info(fb_data->dev, "OL0 local alpha en 0x%x",
++ pxp_conf->ol_param[0].local_alpha_enable);
++
++ dev_info(fb_data->dev, "Out fmt 0x%x",
++ pxp_conf->out_param.pixel_fmt);
++ dev_info(fb_data->dev, "Out width 0x%x",
++ pxp_conf->out_param.width);
++ dev_info(fb_data->dev, "Out height 0x%x",
++ pxp_conf->out_param.height);
++
++ dev_info(fb_data->dev,
++ "drect left 0x%x right 0x%x width 0x%x height 0x%x",
++ pxp_conf->proc_data.drect.left, pxp_conf->proc_data.drect.top,
++ pxp_conf->proc_data.drect.width,
++ pxp_conf->proc_data.drect.height);
++ dev_info(fb_data->dev,
++ "srect left 0x%x right 0x%x width 0x%x height 0x%x",
++ pxp_conf->proc_data.srect.left, pxp_conf->proc_data.srect.top,
++ pxp_conf->proc_data.srect.width,
++ pxp_conf->proc_data.srect.height);
++ dev_info(fb_data->dev, "Scaling en 0x%x", pxp_conf->proc_data.scaling);
++ dev_info(fb_data->dev, "HFlip en 0x%x", pxp_conf->proc_data.hflip);
++ dev_info(fb_data->dev, "VFlip en 0x%x", pxp_conf->proc_data.vflip);
++ dev_info(fb_data->dev, "Rotation 0x%x", pxp_conf->proc_data.rotate);
++ dev_info(fb_data->dev, "BG Color 0x%x", pxp_conf->proc_data.bgcolor);
++}
++
++static void dump_epdc_reg(void)
++{
++ printk(KERN_DEBUG "\n\n");
++ printk(KERN_DEBUG "EPDC_CTRL 0x%x\n", __raw_readl(EPDC_CTRL));
++ printk(KERN_DEBUG "EPDC_WVADDR 0x%x\n", __raw_readl(EPDC_WVADDR));
++ printk(KERN_DEBUG "EPDC_WB_ADDR 0x%x\n", __raw_readl(EPDC_WB_ADDR));
++ printk(KERN_DEBUG "EPDC_RES 0x%x\n", __raw_readl(EPDC_RES));
++ printk(KERN_DEBUG "EPDC_FORMAT 0x%x\n", __raw_readl(EPDC_FORMAT));
++ printk(KERN_DEBUG "EPDC_FIFOCTRL 0x%x\n", __raw_readl(EPDC_FIFOCTRL));
++ printk(KERN_DEBUG "EPDC_UPD_ADDR 0x%x\n", __raw_readl(EPDC_UPD_ADDR));
++ printk(KERN_DEBUG "EPDC_UPD_STRIDE 0x%x\n", __raw_readl(EPDC_UPD_STRIDE));
++ printk(KERN_DEBUG "EPDC_UPD_FIXED 0x%x\n", __raw_readl(EPDC_UPD_FIXED));
++ printk(KERN_DEBUG "EPDC_UPD_CORD 0x%x\n", __raw_readl(EPDC_UPD_CORD));
++ printk(KERN_DEBUG "EPDC_UPD_SIZE 0x%x\n", __raw_readl(EPDC_UPD_SIZE));
++ printk(KERN_DEBUG "EPDC_UPD_CTRL 0x%x\n", __raw_readl(EPDC_UPD_CTRL));
++ printk(KERN_DEBUG "EPDC_TEMP 0x%x\n", __raw_readl(EPDC_TEMP));
++ printk(KERN_DEBUG "EPDC_AUTOWV_LUT 0x%x\n", __raw_readl(EPDC_AUTOWV_LUT));
++ printk(KERN_DEBUG "EPDC_TCE_CTRL 0x%x\n", __raw_readl(EPDC_TCE_CTRL));
++ printk(KERN_DEBUG "EPDC_TCE_SDCFG 0x%x\n", __raw_readl(EPDC_TCE_SDCFG));
++ printk(KERN_DEBUG "EPDC_TCE_GDCFG 0x%x\n", __raw_readl(EPDC_TCE_GDCFG));
++ printk(KERN_DEBUG "EPDC_TCE_HSCAN1 0x%x\n", __raw_readl(EPDC_TCE_HSCAN1));
++ printk(KERN_DEBUG "EPDC_TCE_HSCAN2 0x%x\n", __raw_readl(EPDC_TCE_HSCAN2));
++ printk(KERN_DEBUG "EPDC_TCE_VSCAN 0x%x\n", __raw_readl(EPDC_TCE_VSCAN));
++ printk(KERN_DEBUG "EPDC_TCE_OE 0x%x\n", __raw_readl(EPDC_TCE_OE));
++ printk(KERN_DEBUG "EPDC_TCE_POLARITY 0x%x\n", __raw_readl(EPDC_TCE_POLARITY));
++ printk(KERN_DEBUG "EPDC_TCE_TIMING1 0x%x\n", __raw_readl(EPDC_TCE_TIMING1));
++ printk(KERN_DEBUG "EPDC_TCE_TIMING2 0x%x\n", __raw_readl(EPDC_TCE_TIMING2));
++ printk(KERN_DEBUG "EPDC_TCE_TIMING3 0x%x\n", __raw_readl(EPDC_TCE_TIMING3));
++ printk(KERN_DEBUG "EPDC_PIGEON_CTRL0 0x%x\n", __raw_readl(EPDC_PIGEON_CTRL0));
++ printk(KERN_DEBUG "EPDC_PIGEON_CTRL1 0x%x\n", __raw_readl(EPDC_PIGEON_CTRL1));
++ printk(KERN_DEBUG "EPDC_IRQ_MASK1 0x%x\n", __raw_readl(EPDC_IRQ_MASK1));
++ printk(KERN_DEBUG "EPDC_IRQ_MASK2 0x%x\n", __raw_readl(EPDC_IRQ_MASK2));
++ printk(KERN_DEBUG "EPDC_IRQ1 0x%x\n", __raw_readl(EPDC_IRQ1));
++ printk(KERN_DEBUG "EPDC_IRQ2 0x%x\n", __raw_readl(EPDC_IRQ2));
++ printk(KERN_DEBUG "EPDC_IRQ_MASK 0x%x\n", __raw_readl(EPDC_IRQ_MASK));
++ printk(KERN_DEBUG "EPDC_IRQ 0x%x\n", __raw_readl(EPDC_IRQ));
++ printk(KERN_DEBUG "EPDC_STATUS_LUTS 0x%x\n", __raw_readl(EPDC_STATUS_LUTS));
++ printk(KERN_DEBUG "EPDC_STATUS_LUTS2 0x%x\n", __raw_readl(EPDC_STATUS_LUTS2));
++ printk(KERN_DEBUG "EPDC_STATUS_NEXTLUT 0x%x\n", __raw_readl(EPDC_STATUS_NEXTLUT));
++ printk(KERN_DEBUG "EPDC_STATUS_COL1 0x%x\n", __raw_readl(EPDC_STATUS_COL));
++ printk(KERN_DEBUG "EPDC_STATUS_COL2 0x%x\n", __raw_readl(EPDC_STATUS_COL2));
++ printk(KERN_DEBUG "EPDC_STATUS 0x%x\n", __raw_readl(EPDC_STATUS));
++ printk(KERN_DEBUG "EPDC_UPD_COL_CORD 0x%x\n", __raw_readl(EPDC_UPD_COL_CORD));
++ printk(KERN_DEBUG "EPDC_UPD_COL_SIZE 0x%x\n", __raw_readl(EPDC_UPD_COL_SIZE));
++ printk(KERN_DEBUG "EPDC_DEBUG 0x%x\n", __raw_readl(EPDC_DEBUG));
++ printk(KERN_DEBUG "EPDC_DEBUG_LUT 0x%x\n", __raw_readl(EPDC_DEBUG_LUT));
++ printk(KERN_DEBUG "EPDC_HIST1_PARAM 0x%x\n", __raw_readl(EPDC_HIST1_PARAM));
++ printk(KERN_DEBUG "EPDC_HIST2_PARAM 0x%x\n", __raw_readl(EPDC_HIST2_PARAM));
++ printk(KERN_DEBUG "EPDC_HIST4_PARAM 0x%x\n", __raw_readl(EPDC_HIST4_PARAM));
++ printk(KERN_DEBUG "EPDC_HIST8_PARAM0 0x%x\n", __raw_readl(EPDC_HIST8_PARAM0));
++ printk(KERN_DEBUG "EPDC_HIST8_PARAM1 0x%x\n", __raw_readl(EPDC_HIST8_PARAM1));
++ printk(KERN_DEBUG "EPDC_HIST16_PARAM0 0x%x\n", __raw_readl(EPDC_HIST16_PARAM0));
++ printk(KERN_DEBUG "EPDC_HIST16_PARAM1 0x%x\n", __raw_readl(EPDC_HIST16_PARAM1));
++ printk(KERN_DEBUG "EPDC_HIST16_PARAM2 0x%x\n", __raw_readl(EPDC_HIST16_PARAM2));
++ printk(KERN_DEBUG "EPDC_HIST16_PARAM3 0x%x\n", __raw_readl(EPDC_HIST16_PARAM3));
++ printk(KERN_DEBUG "EPDC_GPIO 0x%x\n", __raw_readl(EPDC_GPIO));
++ printk(KERN_DEBUG "EPDC_VERSION 0x%x\n", __raw_readl(EPDC_VERSION));
++ printk(KERN_DEBUG "\n\n");
++}
++
++static void dump_update_data(struct device *dev,
++ struct update_data_list *upd_data_list)
++{
++ dev_info(dev,
++ "X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, "
++ "LUT = %d, Coll Mask = 0x%llx, order = %d\n",
++ upd_data_list->update_desc->upd_data.update_region.left,
++ upd_data_list->update_desc->upd_data.update_region.top,
++ upd_data_list->update_desc->upd_data.update_region.width,
++ upd_data_list->update_desc->upd_data.update_region.height,
++ upd_data_list->update_desc->upd_data.waveform_mode,
++ upd_data_list->lut_num,
++ upd_data_list->collision_mask,
++ upd_data_list->update_desc->update_order);
++}
++
++static void dump_collision_list(struct mxc_epdc_fb_data *fb_data)
++{
++ struct update_data_list *plist;
++
++ dev_info(fb_data->dev, "Collision List:\n");
++ if (list_empty(&fb_data->upd_buf_collision_list))
++ dev_info(fb_data->dev, "Empty");
++ list_for_each_entry(plist, &fb_data->upd_buf_collision_list, list) {
++ dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
++ (u32)plist->virt_addr, plist->phys_addr);
++ dump_update_data(fb_data->dev, plist);
++ }
++}
++
++static void dump_free_list(struct mxc_epdc_fb_data *fb_data)
++{
++ struct update_data_list *plist;
++
++ dev_info(fb_data->dev, "Free List:\n");
++ if (list_empty(&fb_data->upd_buf_free_list))
++ dev_info(fb_data->dev, "Empty");
++ list_for_each_entry(plist, &fb_data->upd_buf_free_list, list)
++ dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
++ (u32)plist->virt_addr, plist->phys_addr);
++}
++
++static void dump_queue(struct mxc_epdc_fb_data *fb_data)
++{
++ struct update_data_list *plist;
++
++ dev_info(fb_data->dev, "Queue:\n");
++ if (list_empty(&fb_data->upd_buf_queue))
++ dev_info(fb_data->dev, "Empty");
++ list_for_each_entry(plist, &fb_data->upd_buf_queue, list) {
++ dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
++ (u32)plist->virt_addr, plist->phys_addr);
++ dump_update_data(fb_data->dev, plist);
++ }
++}
++
++static void dump_desc_data(struct device *dev,
++ struct update_desc_list *upd_desc_list)
++{
++ dev_info(dev,
++ "X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, "
++ "order = %d\n",
++ upd_desc_list->upd_data.update_region.left,
++ upd_desc_list->upd_data.update_region.top,
++ upd_desc_list->upd_data.update_region.width,
++ upd_desc_list->upd_data.update_region.height,
++ upd_desc_list->upd_data.waveform_mode,
++ upd_desc_list->update_order);
++}
++
++static void dump_pending_list(struct mxc_epdc_fb_data *fb_data)
++{
++ struct update_desc_list *plist;
++
++ dev_info(fb_data->dev, "Queue:\n");
++ if (list_empty(&fb_data->upd_pending_list))
++ dev_info(fb_data->dev, "Empty");
++ list_for_each_entry(plist, &fb_data->upd_pending_list, list)
++ dump_desc_data(fb_data->dev, plist);
++}
++
++static void dump_all_updates(struct mxc_epdc_fb_data *fb_data)
++{
++ dump_free_list(fb_data);
++ dump_queue(fb_data);
++ dump_collision_list(fb_data);
++ dev_info(fb_data->dev, "Current update being processed:\n");
++ if (fb_data->cur_update == NULL)
++ dev_info(fb_data->dev, "No current update\n");
++ else
++ dump_update_data(fb_data->dev, fb_data->cur_update);
++}
++#else
++static inline void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
++ struct pxp_config_data *pxp_conf) {}
++static inline void dump_epdc_reg(void) {}
++static inline void dump_update_data(struct device *dev,
++ struct update_data_list *upd_data_list) {}
++static inline void dump_collision_list(struct mxc_epdc_fb_data *fb_data) {}
++static inline void dump_free_list(struct mxc_epdc_fb_data *fb_data) {}
++static inline void dump_queue(struct mxc_epdc_fb_data *fb_data) {}
++static inline void dump_all_updates(struct mxc_epdc_fb_data *fb_data) {}
++
++#endif
++
++
++/********************************************************
++ * Start Low-Level EPDC Functions
++ ********************************************************/
++
++static inline void epdc_lut_complete_intr(int rev, u32 lut_num, bool enable)
++{
++ if (rev < 20) {
++ if (enable)
++ __raw_writel(1 << lut_num, EPDC_IRQ_MASK_SET);
++ else
++ __raw_writel(1 << lut_num, EPDC_IRQ_MASK_CLEAR);
++ } else {
++ if (enable) {
++ if (lut_num < 32)
++ __raw_writel(1 << lut_num, EPDC_IRQ_MASK1_SET);
++ else
++ __raw_writel(1 << (lut_num - 32),
++ EPDC_IRQ_MASK2_SET);
++ } else {
++ if (lut_num < 32)
++ __raw_writel(1 << lut_num,
++ EPDC_IRQ_MASK1_CLEAR);
++ else
++ __raw_writel(1 << (lut_num - 32),
++ EPDC_IRQ_MASK2_CLEAR);
++ }
++ }
++}
++
++static inline void epdc_working_buf_intr(bool enable)
++{
++ if (enable)
++ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_SET);
++ else
++ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_CLEAR);
++}
++
++static inline void epdc_clear_working_buf_irq(void)
++{
++ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ | EPDC_IRQ_LUT_COL_IRQ,
++ EPDC_IRQ_CLEAR);
++}
++
++static inline void epdc_eof_intr(bool enable)
++{
++ if (enable)
++ __raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_MASK_SET);
++ else
++ __raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_MASK_CLEAR);
++}
++
++static inline void epdc_clear_eof_irq(void)
++{
++ __raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_CLEAR);
++}
++
++static inline bool epdc_signal_eof(void)
++{
++ return (__raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ)
++ & EPDC_IRQ_FRAME_END_IRQ) ? true : false;
++}
++
++static inline void epdc_set_temp(u32 temp)
++{
++ __raw_writel(temp, EPDC_TEMP);
++}
++
++static inline void epdc_set_screen_res(u32 width, u32 height)
++{
++ u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
++ __raw_writel(val, EPDC_RES);
++}
++
++static inline void epdc_set_update_addr(u32 addr)
++{
++ __raw_writel(addr, EPDC_UPD_ADDR);
++}
++
++static inline void epdc_set_update_coord(u32 x, u32 y)
++{
++ u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
++ __raw_writel(val, EPDC_UPD_CORD);
++}
++
++static inline void epdc_set_update_dimensions(u32 width, u32 height)
++{
++ u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
++ __raw_writel(val, EPDC_UPD_SIZE);
++}
++
++static void epdc_set_update_waveform(struct mxcfb_waveform_modes *wv_modes)
++{
++ u32 val;
++
++ /* Configure the auto-waveform look-up table based on waveform modes */
++
++ /* Entry 1 = DU, 2 = GC4, 3 = GC8, etc. */
++ val = (wv_modes->mode_du << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (0 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_du << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (1 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_gc4 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (2 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_gc8 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (3 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_gc16 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (4 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_gc32 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (5 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++}
++
++static void epdc_set_update_stride(u32 stride)
++{
++ __raw_writel(stride, EPDC_UPD_STRIDE);
++}
++
++static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
++ bool use_dry_run, bool use_test_mode, u32 np_val)
++{
++ u32 reg_val = 0;
++
++ if (use_test_mode) {
++ reg_val |=
++ ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
++ EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
++
++ __raw_writel(reg_val, EPDC_UPD_FIXED);
++
++ reg_val = EPDC_UPD_CTRL_USE_FIXED;
++ } else {
++ __raw_writel(reg_val, EPDC_UPD_FIXED);
++ }
++
++ if (waveform_mode == WAVEFORM_MODE_AUTO)
++ reg_val |= EPDC_UPD_CTRL_AUTOWV;
++ else
++ reg_val |= ((waveform_mode <<
++ EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
++ EPDC_UPD_CTRL_WAVEFORM_MODE_MASK);
++
++ reg_val |= (use_dry_run ? EPDC_UPD_CTRL_DRY_RUN : 0) |
++ ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
++ EPDC_UPD_CTRL_LUT_SEL_MASK) |
++ update_mode;
++
++ __raw_writel(reg_val, EPDC_UPD_CTRL);
++}
++
++static inline bool epdc_is_lut_complete(int rev, u32 lut_num)
++{
++ u32 val;
++ bool is_compl;
++ if (rev < 20) {
++ val = __raw_readl(EPDC_IRQ);
++ is_compl = val & (1 << lut_num) ? true : false;
++ } else if (lut_num < 32) {
++ val = __raw_readl(EPDC_IRQ1);
++ is_compl = val & (1 << lut_num) ? true : false;
++ } else {
++ val = __raw_readl(EPDC_IRQ2);
++ is_compl = val & (1 << (lut_num - 32)) ? true : false;
++ }
++
++ return is_compl;
++}
++
++static inline void epdc_clear_lut_complete_irq(int rev, u32 lut_num)
++{
++ if (rev < 20)
++ __raw_writel(1 << lut_num, EPDC_IRQ_CLEAR);
++ else if (lut_num < 32)
++ __raw_writel(1 << lut_num, EPDC_IRQ1_CLEAR);
++ else
++ __raw_writel(1 << (lut_num - 32), EPDC_IRQ2_CLEAR);
++}
++
++static inline bool epdc_is_lut_active(u32 lut_num)
++{
++ u32 val;
++ bool is_active;
++
++ if (lut_num < 32) {
++ val = __raw_readl(EPDC_STATUS_LUTS);
++ is_active = val & (1 << lut_num) ? true : false;
++ } else {
++ val = __raw_readl(EPDC_STATUS_LUTS2);
++ is_active = val & (1 << (lut_num - 32)) ? true : false;
++ }
++
++ return is_active;
++}
++
++static inline bool epdc_any_luts_active(int rev)
++{
++ bool any_active;
++
++ if (rev < 20)
++ any_active = __raw_readl(EPDC_STATUS_LUTS) ? true : false;
++ else
++ any_active = (__raw_readl(EPDC_STATUS_LUTS) |
++ __raw_readl(EPDC_STATUS_LUTS2)) ? true : false;
++
++ return any_active;
++}
++
++static inline bool epdc_any_luts_available(void)
++{
++ bool luts_available =
++ (__raw_readl(EPDC_STATUS_NEXTLUT) &
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID) ? true : false;
++ return luts_available;
++}
++
++static inline int epdc_get_next_lut(void)
++{
++ u32 val =
++ __raw_readl(EPDC_STATUS_NEXTLUT) &
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK;
++ return val;
++}
++
++static int epdc_choose_next_lut(int rev, int *next_lut)
++{
++ u64 luts_status, unprocessed_luts, used_luts;
++ /* Available LUTs are reduced to 16 in 5-bit waveform mode */
++ bool format_p5n = ((__raw_readl(EPDC_FORMAT) &
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK) ==
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N);
++
++ luts_status = __raw_readl(EPDC_STATUS_LUTS);
++ if ((rev < 20) || format_p5n)
++ luts_status &= 0xFFFF;
++ else
++ luts_status |= ((u64)__raw_readl(EPDC_STATUS_LUTS2) << 32);
++
++ if (rev < 20) {
++ unprocessed_luts = __raw_readl(EPDC_IRQ) & 0xFFFF;
++ } else {
++ unprocessed_luts = __raw_readl(EPDC_IRQ1) |
++ ((u64)__raw_readl(EPDC_IRQ2) << 32);
++ if (format_p5n)
++ unprocessed_luts &= 0xFFFF;
++ }
++
++ /*
++ * Note on unprocessed_luts: There is a race condition
++ * where a LUT completes, but has not been processed by
++ * IRQ handler workqueue, and then a new update request
++ * attempts to use that LUT. We prevent that here by
++ * ensuring that the LUT we choose doesn't have its IRQ
++ * bit set (indicating it has completed but not yet been
++ * processed).
++ */
++ used_luts = luts_status | unprocessed_luts;
++
++ /*
++ * Selecting a LUT to minimize incidence of TCE Underrun Error
++ * --------------------------------------------------------
++ * We want to find the lowest order LUT that is of greater
++ * order than all other active LUTs. If highest order LUT
++ * is active, then we want to choose the lowest order
++ * available LUT.
++ *
++ * NOTE: For EPDC version 2.0 and later, TCE Underrun error
++ * bug is fixed, so it doesn't matter which LUT is used.
++ */
++
++ if ((rev < 20) || format_p5n) {
++ *next_lut = fls64(used_luts);
++ if (*next_lut > 15)
++ *next_lut = ffz(used_luts);
++ } else {
++ if ((u32)used_luts != ~0UL)
++ *next_lut = ffz((u32)used_luts);
++ else if ((u32)(used_luts >> 32) != ~0UL)
++ *next_lut = ffz((u32)(used_luts >> 32)) + 32;
++ else
++ *next_lut = INVALID_LUT;
++ }
++
++ if (used_luts & 0x8000)
++ return 1;
++ else
++ return 0;
++}
++
++static inline bool epdc_is_working_buffer_busy(void)
++{
++ u32 val = __raw_readl(EPDC_STATUS);
++ bool is_busy = (val & EPDC_STATUS_WB_BUSY) ? true : false;
++
++ return is_busy;
++}
++
++static inline bool epdc_is_working_buffer_complete(void)
++{
++ u32 val = __raw_readl(EPDC_IRQ);
++ bool is_compl = (val & EPDC_IRQ_WB_CMPLT_IRQ) ? true : false;
++
++ return is_compl;
++}
++
++static inline bool epdc_is_lut_cancelled(void)
++{
++ u32 val = __raw_readl(EPDC_STATUS);
++ bool is_void = (val & EPDC_STATUS_UPD_VOID) ? true : false;
++
++ return is_void;
++}
++
++static inline bool epdc_is_collision(void)
++{
++ u32 val = __raw_readl(EPDC_IRQ);
++ return (val & EPDC_IRQ_LUT_COL_IRQ) ? true : false;
++}
++
++static inline u64 epdc_get_colliding_luts(int rev)
++{
++ u32 val = __raw_readl(EPDC_STATUS_COL);
++ if (rev >= 20)
++ val |= (u64)__raw_readl(EPDC_STATUS_COL2) << 32;
++ return val;
++}
++
++static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end,
++ u32 hsync_width, u32 hsync_line_length)
++{
++ u32 reg_val =
++ ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) &
++ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
++ | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) &
++ EPDC_TCE_HSCAN1_LINE_SYNC_MASK);
++ __raw_writel(reg_val, EPDC_TCE_HSCAN1);
++
++ reg_val =
++ ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) &
++ EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
++ | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) &
++ EPDC_TCE_HSCAN2_LINE_END_MASK);
++ __raw_writel(reg_val, EPDC_TCE_HSCAN2);
++}
++
++static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
++ u32 vsync_width)
++{
++ u32 reg_val =
++ ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) &
++ EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
++ | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) &
++ EPDC_TCE_VSCAN_FRAME_END_MASK)
++ | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) &
++ EPDC_TCE_VSCAN_FRAME_SYNC_MASK);
++ __raw_writel(reg_val, EPDC_TCE_VSCAN);
++}
++
++static void epdc_init_settings(struct mxc_epdc_fb_data *fb_data)
++{
++ struct imx_epdc_fb_mode *epdc_mode = fb_data->cur_mode;
++ struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var;
++ u32 reg_val;
++ int num_ce;
++ int i;
++
++ /* Enable clocks to access EPDC regs */
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++ clk_prepare_enable(fb_data->epdc_clk_pix);
++
++ /* Reset */
++ __raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_SET);
++ while (!(__raw_readl(EPDC_CTRL) & EPDC_CTRL_CLKGATE))
++ ;
++ __raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_CLEAR);
++
++ /* Enable clock gating (clear to enable) */
++ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
++ while (__raw_readl(EPDC_CTRL) & (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
++ ;
++
++ /* EPDC_CTRL */
++ reg_val = __raw_readl(EPDC_CTRL);
++ reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK;
++ reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP;
++ reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK;
++ reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP;
++ __raw_writel(reg_val, EPDC_CTRL_SET);
++
++ /* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */
++ reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT
++ | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N
++ | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) &
++ EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK);
++ __raw_writel(reg_val, EPDC_FORMAT);
++
++ /* EPDC_FIFOCTRL (disabled) */
++ reg_val =
++ ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) &
++ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
++ | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) &
++ EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
++ | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) &
++ EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK);
++ __raw_writel(reg_val, EPDC_FIFOCTRL);
++
++ /* EPDC_TEMP - Use default temp to get index */
++ epdc_set_temp(mxc_epdc_fb_get_temp_index(fb_data, DEFAULT_TEMP));
++
++ /* EPDC_RES */
++ epdc_set_screen_res(epdc_mode->vmode->xres, epdc_mode->vmode->yres);
++
++ /* EPDC_AUTOWV_LUT */
++ /* Initialize all auto-wavefrom look-up values to 2 - GC16 */
++ for (i = 0; i < 8; i++)
++ __raw_writel((2 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (i << EPDC_AUTOWV_LUT_ADDR_OFFSET), EPDC_AUTOWV_LUT);
++
++ /*
++ * EPDC_TCE_CTRL
++ * VSCAN_HOLDOFF = 4
++ * VCOM_MODE = MANUAL
++ * VCOM_VAL = 0
++ * DDR_MODE = DISABLED
++ * LVDS_MODE_CE = DISABLED
++ * LVDS_MODE = DISABLED
++ * DUAL_SCAN = DISABLED
++ * SDDO_WIDTH = 8bit
++ * PIXELS_PER_SDCLK = 4
++ */
++ reg_val =
++ ((epdc_mode->vscan_holdoff << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
++ EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
++ | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
++ __raw_writel(reg_val, EPDC_TCE_CTRL);
++
++ /* EPDC_TCE_HSCAN */
++ epdc_set_horizontal_timing(screeninfo->left_margin,
++ screeninfo->right_margin,
++ screeninfo->hsync_len,
++ screeninfo->hsync_len);
++
++ /* EPDC_TCE_VSCAN */
++ epdc_set_vertical_timing(screeninfo->upper_margin,
++ screeninfo->lower_margin,
++ screeninfo->vsync_len);
++
++ /* EPDC_TCE_OE */
++ reg_val =
++ ((epdc_mode->sdoed_width << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
++ EPDC_TCE_OE_SDOED_WIDTH_MASK)
++ | ((epdc_mode->sdoed_delay << EPDC_TCE_OE_SDOED_DLY_OFFSET) &
++ EPDC_TCE_OE_SDOED_DLY_MASK)
++ | ((epdc_mode->sdoez_width << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
++ EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
++ | ((epdc_mode->sdoez_delay << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
++ EPDC_TCE_OE_SDOEZ_DLY_MASK);
++ __raw_writel(reg_val, EPDC_TCE_OE);
++
++ /* EPDC_TCE_TIMING1 */
++ __raw_writel(0x0, EPDC_TCE_TIMING1);
++
++ /* EPDC_TCE_TIMING2 */
++ reg_val =
++ ((epdc_mode->gdclk_hp_offs << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
++ EPDC_TCE_TIMING2_GDCLK_HP_MASK)
++ | ((epdc_mode->gdsp_offs << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
++ EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
++ __raw_writel(reg_val, EPDC_TCE_TIMING2);
++
++ /* EPDC_TCE_TIMING3 */
++ reg_val =
++ ((epdc_mode->gdoe_offs << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
++ EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
++ | ((epdc_mode->gdclk_offs << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
++ EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
++ __raw_writel(reg_val, EPDC_TCE_TIMING3);
++
++ /*
++ * EPDC_TCE_SDCFG
++ * SDCLK_HOLD = 1
++ * SDSHR = 1
++ * NUM_CE = 1
++ * SDDO_REFORMAT = FLIP_PIXELS
++ * SDDO_INVERT = DISABLED
++ * PIXELS_PER_CE = display horizontal resolution
++ */
++ num_ce = epdc_mode->num_ce;
++ if (num_ce == 0)
++ num_ce = 1;
++ reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
++ | ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) &
++ EPDC_TCE_SDCFG_NUM_CE_MASK)
++ | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
++ | ((epdc_mode->vmode->xres/num_ce << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
++ EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
++ __raw_writel(reg_val, EPDC_TCE_SDCFG);
++
++ /*
++ * EPDC_TCE_GDCFG
++ * GDRL = 1
++ * GDOE_MODE = 0;
++ * GDSP_MODE = 0;
++ */
++ reg_val = EPDC_TCE_SDCFG_GDRL;
++ __raw_writel(reg_val, EPDC_TCE_GDCFG);
++
++ /*
++ * EPDC_TCE_POLARITY
++ * SDCE_POL = ACTIVE LOW
++ * SDLE_POL = ACTIVE HIGH
++ * SDOE_POL = ACTIVE HIGH
++ * GDOE_POL = ACTIVE HIGH
++ * GDSP_POL = ACTIVE LOW
++ */
++ reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH
++ | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH
++ | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH;
++ __raw_writel(reg_val, EPDC_TCE_POLARITY);
++
++ /* EPDC_IRQ_MASK */
++ __raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_MASK);
++
++ /*
++ * EPDC_GPIO
++ * PWRCOM = ?
++ * PWRCTRL = ?
++ * BDR = ?
++ */
++ reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
++ | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
++ __raw_writel(reg_val, EPDC_GPIO);
++
++ __raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR);
++ __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR);
++ __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR_TCE);
++
++ /* Disable clock */
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++ clk_disable_unprepare(fb_data->epdc_clk_pix);
++}
++
++static void epdc_powerup(struct mxc_epdc_fb_data *fb_data)
++{
++ int ret = 0;
++ mutex_lock(&fb_data->power_mutex);
++
++ /*
++ * If power down request is pending, clear
++ * powering_down to cancel the request.
++ */
++ if (fb_data->powering_down)
++ fb_data->powering_down = false;
++
++ if (fb_data->power_state == POWER_STATE_ON) {
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++
++ dev_dbg(fb_data->dev, "EPDC Powerup\n");
++
++ fb_data->updates_active = true;
++
++ /* Enable the v3p3 regulator */
++ ret = regulator_enable(fb_data->v3p3_regulator);
++ if (IS_ERR((void *)ret)) {
++ dev_err(fb_data->dev, "Unable to enable V3P3 regulator."
++ "err = 0x%x\n", ret);
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++
++ msleep(1);
++
++ pm_runtime_get_sync(fb_data->dev);
++
++ /* Enable clocks to EPDC */
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++ clk_prepare_enable(fb_data->epdc_clk_pix);
++
++ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
++
++ /* Enable power to the EPD panel */
++ ret = regulator_enable(fb_data->display_regulator);
++ if (IS_ERR((void *)ret)) {
++ dev_err(fb_data->dev, "Unable to enable DISPLAY regulator."
++ "err = 0x%x\n", ret);
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++ ret = regulator_enable(fb_data->vcom_regulator);
++ if (IS_ERR((void *)ret)) {
++ dev_err(fb_data->dev, "Unable to enable VCOM regulator."
++ "err = 0x%x\n", ret);
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++
++ fb_data->power_state = POWER_STATE_ON;
++
++ mutex_unlock(&fb_data->power_mutex);
++}
++
++static void epdc_powerdown(struct mxc_epdc_fb_data *fb_data)
++{
++ mutex_lock(&fb_data->power_mutex);
++
++ /* If powering_down has been cleared, a powerup
++ * request is pre-empting this powerdown request.
++ */
++ if (!fb_data->powering_down
++ || (fb_data->power_state == POWER_STATE_OFF)) {
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++
++ dev_dbg(fb_data->dev, "EPDC Powerdown\n");
++
++ /* Disable power to the EPD panel */
++ regulator_disable(fb_data->vcom_regulator);
++ regulator_disable(fb_data->display_regulator);
++
++ /* Disable clocks to EPDC */
++ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET);
++ clk_disable_unprepare(fb_data->epdc_clk_pix);
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++
++ pm_runtime_put_sync_suspend(fb_data->dev);
++
++ /* turn off the V3p3 */
++ regulator_disable(fb_data->v3p3_regulator);
++
++ fb_data->power_state = POWER_STATE_OFF;
++ fb_data->powering_down = false;
++
++ if (fb_data->wait_for_powerdown) {
++ fb_data->wait_for_powerdown = false;
++ complete(&fb_data->powerdown_compl);
++ }
++
++ mutex_unlock(&fb_data->power_mutex);
++}
++
++static void epdc_init_sequence(struct mxc_epdc_fb_data *fb_data)
++{
++ /* Initialize EPDC, passing pointer to EPDC registers */
++ epdc_init_settings(fb_data);
++ fb_data->in_init = true;
++ epdc_powerup(fb_data);
++ draw_mode0(fb_data);
++ /* Force power down event */
++ fb_data->powering_down = true;
++ epdc_powerdown(fb_data);
++ fb_data->updates_active = false;
++}
++
++static int mxc_epdc_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
++{
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++
++ if (offset < info->fix.smem_len) {
++ /* mapping framebuffer memory */
++ len = info->fix.smem_len - offset;
++ vma->vm_pgoff = (info->fix.smem_start + offset) >> PAGE_SHIFT;
++ } else
++ return -EINVAL;
++
++ len = PAGE_ALIGN(len);
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ /* make buffers bufferable */
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++ dev_dbg(info->device, "mmap remap_pfn_range failed\n");
++ return -ENOBUFS;
++ }
++
++ return 0;
++}
++
++static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
++{
++ chan &= 0xffff;
++ chan >>= 16 - bf->length;
++ return chan << bf->offset;
++}
++
++static int mxc_epdc_fb_setcolreg(u_int regno, u_int red, u_int green,
++ u_int blue, u_int transp, struct fb_info *info)
++{
++ unsigned int val;
++ int ret = 1;
++
++ /*
++ * If greyscale is true, then we convert the RGB value
++ * to greyscale no matter what visual we are using.
++ */
++ if (info->var.grayscale)
++ red = green = blue = (19595 * red + 38470 * green +
++ 7471 * blue) >> 16;
++ switch (info->fix.visual) {
++ case FB_VISUAL_TRUECOLOR:
++ /*
++ * 16-bit True Colour. We encode the RGB value
++ * according to the RGB bitfield information.
++ */
++ if (regno < 16) {
++ u32 *pal = info->pseudo_palette;
++
++ val = _chan_to_field(red, &info->var.red);
++ val |= _chan_to_field(green, &info->var.green);
++ val |= _chan_to_field(blue, &info->var.blue);
++
++ pal[regno] = val;
++ ret = 0;
++ }
++ break;
++
++ case FB_VISUAL_STATIC_PSEUDOCOLOR:
++ case FB_VISUAL_PSEUDOCOLOR:
++ break;
++ }
++
++ return ret;
++}
++
++static int mxc_epdc_fb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
++{
++ int count, index, r;
++ u16 *red, *green, *blue, *transp;
++ u16 trans = 0xffff;
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ int i;
++
++ dev_dbg(fb_data->dev, "setcmap\n");
++
++ if (info->fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) {
++ /* Only support an 8-bit, 256 entry lookup */
++ if (cmap->len != 256)
++ return 1;
++
++ mxc_epdc_fb_flush_updates(fb_data);
++
++ mutex_lock(&fb_data->pxp_mutex);
++ /*
++ * Store colormap in pxp_conf structure for later transmit
++ * to PxP during update process to convert gray pixels.
++ *
++ * Since red=blue=green for pseudocolor visuals, we can
++ * just use red values.
++ */
++ for (i = 0; i < 256; i++)
++ fb_data->pxp_conf.proc_data.lut_map[i] = cmap->red[i] & 0xFF;
++
++ fb_data->pxp_conf.proc_data.lut_map_updated = true;
++
++ mutex_unlock(&fb_data->pxp_mutex);
++ } else {
++ red = cmap->red;
++ green = cmap->green;
++ blue = cmap->blue;
++ transp = cmap->transp;
++ index = cmap->start;
++
++ for (count = 0; count < cmap->len; count++) {
++ if (transp)
++ trans = *transp++;
++ r = mxc_epdc_fb_setcolreg(index++, *red++, *green++, *blue++,
++ trans, info);
++ if (r != 0)
++ return r;
++ }
++ }
++
++ return 0;
++}
++
++static void adjust_coordinates(u32 xres, u32 yres, u32 rotation,
++ struct mxcfb_rect *update_region, struct mxcfb_rect *adj_update_region)
++{
++ u32 temp;
++
++ /* If adj_update_region == NULL, pass result back in update_region */
++ /* If adj_update_region == valid, use it to pass back result */
++ if (adj_update_region)
++ switch (rotation) {
++ case FB_ROTATE_UR:
++ adj_update_region->top = update_region->top;
++ adj_update_region->left = update_region->left;
++ adj_update_region->width = update_region->width;
++ adj_update_region->height = update_region->height;
++ break;
++ case FB_ROTATE_CW:
++ adj_update_region->top = update_region->left;
++ adj_update_region->left = yres -
++ (update_region->top + update_region->height);
++ adj_update_region->width = update_region->height;
++ adj_update_region->height = update_region->width;
++ break;
++ case FB_ROTATE_UD:
++ adj_update_region->width = update_region->width;
++ adj_update_region->height = update_region->height;
++ adj_update_region->top = yres -
++ (update_region->top + update_region->height);
++ adj_update_region->left = xres -
++ (update_region->left + update_region->width);
++ break;
++ case FB_ROTATE_CCW:
++ adj_update_region->left = update_region->top;
++ adj_update_region->top = xres -
++ (update_region->left + update_region->width);
++ adj_update_region->width = update_region->height;
++ adj_update_region->height = update_region->width;
++ break;
++ }
++ else
++ switch (rotation) {
++ case FB_ROTATE_UR:
++ /* No adjustment needed */
++ break;
++ case FB_ROTATE_CW:
++ temp = update_region->top;
++ update_region->top = update_region->left;
++ update_region->left = yres -
++ (temp + update_region->height);
++ temp = update_region->width;
++ update_region->width = update_region->height;
++ update_region->height = temp;
++ break;
++ case FB_ROTATE_UD:
++ update_region->top = yres -
++ (update_region->top + update_region->height);
++ update_region->left = xres -
++ (update_region->left + update_region->width);
++ break;
++ case FB_ROTATE_CCW:
++ temp = update_region->left;
++ update_region->left = update_region->top;
++ update_region->top = xres -
++ (temp + update_region->width);
++ temp = update_region->width;
++ update_region->width = update_region->height;
++ update_region->height = temp;
++ break;
++ }
++}
++
++/*
++ * Set fixed framebuffer parameters based on variable settings.
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxc_epdc_fb_set_fix(struct fb_info *info)
++{
++ struct fb_fix_screeninfo *fix = &info->fix;
++ struct fb_var_screeninfo *var = &info->var;
++
++ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
++
++ fix->type = FB_TYPE_PACKED_PIXELS;
++ fix->accel = FB_ACCEL_NONE;
++ if (var->grayscale)
++ fix->visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
++ else
++ fix->visual = FB_VISUAL_TRUECOLOR;
++ fix->xpanstep = 1;
++ fix->ypanstep = 1;
++
++ return 0;
++}
++
++/*
++ * This routine actually sets the video mode. It's in here where we
++ * the hardware state info->par and fix which can be affected by the
++ * change in par. For this driver it doesn't do much.
++ *
++ */
++static int mxc_epdc_fb_set_par(struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
++ struct imx_epdc_fb_mode *epdc_modes = fb_data->pdata->epdc_mode;
++ int i;
++ int ret;
++ __u32 xoffset_old, yoffset_old;
++
++ /*
++ * Can't change the FB parameters until current updates have completed.
++ * This function returns when all active updates are done.
++ */
++ mxc_epdc_fb_flush_updates(fb_data);
++
++ mutex_lock(&fb_data->queue_mutex);
++ /*
++ * Set all screeninfo except for xoffset/yoffset
++ * Subsequent call to pan_display will handle those.
++ */
++ xoffset_old = fb_data->epdc_fb_var.xoffset;
++ yoffset_old = fb_data->epdc_fb_var.yoffset;
++ fb_data->epdc_fb_var = *screeninfo;
++ fb_data->epdc_fb_var.xoffset = xoffset_old;
++ fb_data->epdc_fb_var.yoffset = yoffset_old;
++ mutex_unlock(&fb_data->queue_mutex);
++
++ mutex_lock(&fb_data->pxp_mutex);
++
++ /*
++ * Update PxP config data (used to process FB regions for updates)
++ * based on FB info and processing tasks required
++ */
++
++ /* Initialize non-channel-specific PxP parameters */
++ proc_data->drect.left = proc_data->srect.left = 0;
++ proc_data->drect.top = proc_data->srect.top = 0;
++ proc_data->drect.width = proc_data->srect.width = screeninfo->xres;
++ proc_data->drect.height = proc_data->srect.height = screeninfo->yres;
++ proc_data->scaling = 0;
++ proc_data->hflip = 0;
++ proc_data->vflip = 0;
++ proc_data->rotate = screeninfo->rotate;
++ proc_data->bgcolor = 0;
++ proc_data->overlay_state = 0;
++ proc_data->lut_transform = PXP_LUT_NONE;
++
++ /*
++ * configure S0 channel parameters
++ * Parameters should match FB format/width/height
++ */
++ if (screeninfo->grayscale)
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_GREY;
++ else {
++ switch (screeninfo->bits_per_pixel) {
++ case 16:
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++ break;
++ case 24:
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB24;
++ break;
++ case 32:
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB32;
++ break;
++ default:
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++ break;
++ }
++ }
++ pxp_conf->s0_param.width = screeninfo->xres_virtual;
++ pxp_conf->s0_param.height = screeninfo->yres;
++ pxp_conf->s0_param.color_key = -1;
++ pxp_conf->s0_param.color_key_enable = false;
++
++ /*
++ * Initialize Output channel parameters
++ * Output is Y-only greyscale
++ * Output width/height will vary based on update region size
++ */
++ pxp_conf->out_param.width = screeninfo->xres;
++ pxp_conf->out_param.height = screeninfo->yres;
++ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
++
++ mutex_unlock(&fb_data->pxp_mutex);
++
++ /*
++ * If HW not yet initialized, check to see if we are being sent
++ * an initialization request.
++ */
++ if (!fb_data->hw_ready) {
++ struct fb_videomode mode;
++ u32 xres_temp;
++
++ fb_var_to_videomode(&mode, screeninfo);
++
++ /* When comparing requested fb mode,
++ we need to use unrotated dimensions */
++ if ((screeninfo->rotate == FB_ROTATE_CW) ||
++ (screeninfo->rotate == FB_ROTATE_CCW)) {
++ xres_temp = mode.xres;
++ mode.xres = mode.yres;
++ mode.yres = xres_temp;
++ }
++
++ /*
++ * If requested video mode does not match current video
++ * mode, search for a matching panel.
++ */
++ if (fb_data->cur_mode &&
++ !fb_mode_is_equal(fb_data->cur_mode->vmode,
++ &mode)) {
++ bool found_match = false;
++
++ /* Match videomode against epdc modes */
++ for (i = 0; i < fb_data->pdata->num_modes; i++) {
++ if (!fb_mode_is_equal(epdc_modes[i].vmode,
++ &mode))
++ continue;
++ fb_data->cur_mode = &epdc_modes[i];
++ found_match = true;
++ break;
++ }
++
++ if (!found_match) {
++ dev_err(fb_data->dev,
++ "Failed to match requested "
++ "video mode\n");
++ return EINVAL;
++ }
++ }
++
++ /* Found a match - Grab timing params */
++ screeninfo->left_margin = mode.left_margin;
++ screeninfo->right_margin = mode.right_margin;
++ screeninfo->upper_margin = mode.upper_margin;
++ screeninfo->lower_margin = mode.lower_margin;
++ screeninfo->hsync_len = mode.hsync_len;
++ screeninfo->vsync_len = mode.vsync_len;
++
++ fb_data->hw_initializing = true;
++
++ /* Initialize EPDC settings and init panel */
++ ret =
++ mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
++ if (ret) {
++ dev_err(fb_data->dev,
++ "Failed to load panel waveform data\n");
++ return ret;
++ }
++ }
++
++ /*
++ * EOF sync delay (in us) should be equal to the vscan holdoff time
++ * VSCAN_HOLDOFF time = (VSCAN_HOLDOFF value + 1) * Vertical lines
++ * Add 25us for additional margin
++ */
++ fb_data->eof_sync_period = (fb_data->cur_mode->vscan_holdoff + 1) *
++ 1000000/(fb_data->cur_mode->vmode->refresh *
++ (fb_data->cur_mode->vmode->upper_margin +
++ fb_data->cur_mode->vmode->yres +
++ fb_data->cur_mode->vmode->lower_margin +
++ fb_data->cur_mode->vmode->vsync_len)) + 25;
++
++ mxc_epdc_fb_set_fix(info);
++
++ return 0;
++}
++
++static int mxc_epdc_fb_check_var(struct fb_var_screeninfo *var,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++
++ if (!var->xres)
++ var->xres = 1;
++ if (!var->yres)
++ var->yres = 1;
++
++ if (var->xres_virtual < var->xoffset + var->xres)
++ var->xres_virtual = var->xoffset + var->xres;
++ if (var->yres_virtual < var->yoffset + var->yres)
++ var->yres_virtual = var->yoffset + var->yres;
++
++ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
++ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
++ var->bits_per_pixel = default_bpp;
++
++ switch (var->bits_per_pixel) {
++ case 8:
++ if (var->grayscale != 0) {
++ /*
++ * For 8-bit grayscale, R, G, and B offset are equal.
++ *
++ */
++ var->red.length = 8;
++ var->red.offset = 0;
++ var->red.msb_right = 0;
++
++ var->green.length = 8;
++ var->green.offset = 0;
++ var->green.msb_right = 0;
++
++ var->blue.length = 8;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ } else {
++ var->red.length = 3;
++ var->red.offset = 5;
++ var->red.msb_right = 0;
++
++ var->green.length = 3;
++ var->green.offset = 2;
++ var->green.msb_right = 0;
++
++ var->blue.length = 2;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ }
++ break;
++ case 16:
++ var->red.length = 5;
++ var->red.offset = 11;
++ var->red.msb_right = 0;
++
++ var->green.length = 6;
++ var->green.offset = 5;
++ var->green.msb_right = 0;
++
++ var->blue.length = 5;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ break;
++ case 24:
++ var->red.length = 8;
++ var->red.offset = 16;
++ var->red.msb_right = 0;
++
++ var->green.length = 8;
++ var->green.offset = 8;
++ var->green.msb_right = 0;
++
++ var->blue.length = 8;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ break;
++ case 32:
++ var->red.length = 8;
++ var->red.offset = 16;
++ var->red.msb_right = 0;
++
++ var->green.length = 8;
++ var->green.offset = 8;
++ var->green.msb_right = 0;
++
++ var->blue.length = 8;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 8;
++ var->transp.offset = 24;
++ var->transp.msb_right = 0;
++ break;
++ }
++
++ switch (var->rotate) {
++ case FB_ROTATE_UR:
++ case FB_ROTATE_UD:
++ var->xres = fb_data->native_width;
++ var->yres = fb_data->native_height;
++ break;
++ case FB_ROTATE_CW:
++ case FB_ROTATE_CCW:
++ var->xres = fb_data->native_height;
++ var->yres = fb_data->native_width;
++ break;
++ default:
++ /* Invalid rotation value */
++ var->rotate = 0;
++ dev_dbg(fb_data->dev, "Invalid rotation request\n");
++ return -EINVAL;
++ }
++
++ var->xres_virtual = ALIGN(var->xres, 32);
++ var->yres_virtual = ALIGN(var->yres, 128) * fb_data->num_screens;
++
++ var->height = -1;
++ var->width = -1;
++
++ return 0;
++}
++
++void mxc_epdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ mutex_lock(&fb_data->queue_mutex);
++
++ memcpy(&fb_data->wv_modes, modes, sizeof(struct mxcfb_waveform_modes));
++
++ /* Set flag to ensure that new waveform modes
++ * are programmed into EPDC before next update */
++ fb_data->wv_modes_update = true;
++
++ mutex_unlock(&fb_data->queue_mutex);
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_waveform_modes);
++
++static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data, int temp)
++{
++ int i;
++ int index = -1;
++
++ if (fb_data->trt_entries == 0) {
++ dev_err(fb_data->dev,
++ "No TRT exists...using default temp index\n");
++ return DEFAULT_TEMP_INDEX;
++ }
++
++ /* Search temperature ranges for a match */
++ for (i = 0; i < fb_data->trt_entries - 1; i++) {
++ if ((temp >= fb_data->temp_range_bounds[i])
++ && (temp < fb_data->temp_range_bounds[i+1])) {
++ index = i;
++ break;
++ }
++ }
++
++ if (index < 0) {
++ dev_err(fb_data->dev,
++ "No TRT index match...using default temp index\n");
++ return DEFAULT_TEMP_INDEX;
++ }
++
++ dev_dbg(fb_data->dev, "Using temperature index %d\n", index);
++
++ return index;
++}
++
++int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ /* Store temp index. Used later when configuring updates. */
++ mutex_lock(&fb_data->queue_mutex);
++ fb_data->temp_index = mxc_epdc_fb_get_temp_index(fb_data, temperature);
++ mutex_unlock(&fb_data->queue_mutex);
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_temperature);
++
++int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ dev_dbg(fb_data->dev, "Setting auto update mode to %d\n", auto_mode);
++
++ if ((auto_mode == AUTO_UPDATE_MODE_AUTOMATIC_MODE)
++ || (auto_mode == AUTO_UPDATE_MODE_REGION_MODE))
++ fb_data->auto_mode = auto_mode;
++ else {
++ dev_err(fb_data->dev, "Invalid auto update mode parameter.\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_auto_update);
++
++int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ dev_dbg(fb_data->dev, "Setting optimization level to %d\n", upd_scheme);
++
++ /*
++ * Can't change the scheme until current updates have completed.
++ * This function returns when all active updates are done.
++ */
++ mxc_epdc_fb_flush_updates(fb_data);
++
++ if ((upd_scheme == UPDATE_SCHEME_SNAPSHOT)
++ || (upd_scheme == UPDATE_SCHEME_QUEUE)
++ || (upd_scheme == UPDATE_SCHEME_QUEUE_AND_MERGE))
++ fb_data->upd_scheme = upd_scheme;
++ else {
++ dev_err(fb_data->dev, "Invalid update scheme specified.\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_upd_scheme);
++
++static void copy_before_process(struct mxc_epdc_fb_data *fb_data,
++ struct update_data_list *upd_data_list)
++{
++ struct mxcfb_update_data *upd_data =
++ &upd_data_list->update_desc->upd_data;
++ int i;
++ unsigned char *temp_buf_ptr = fb_data->virt_addr_copybuf;
++ unsigned char *src_ptr;
++ struct mxcfb_rect *src_upd_region;
++ int temp_buf_stride;
++ int src_stride;
++ int bpp = fb_data->epdc_fb_var.bits_per_pixel;
++ int left_offs, right_offs;
++ int x_trailing_bytes, y_trailing_bytes;
++ int alt_buf_offset;
++
++ /* Set source buf pointer based on input source, panning, etc. */
++ if (upd_data->flags & EPDC_FLAG_USE_ALT_BUFFER) {
++ src_upd_region = &upd_data->alt_buffer_data.alt_update_region;
++ src_stride =
++ upd_data->alt_buffer_data.width * bpp/8;
++ alt_buf_offset = upd_data->alt_buffer_data.phys_addr -
++ fb_data->info.fix.smem_start;
++ src_ptr = fb_data->info.screen_base + alt_buf_offset
++ + src_upd_region->top * src_stride;
++ } else {
++ src_upd_region = &upd_data->update_region;
++ src_stride = fb_data->epdc_fb_var.xres_virtual * bpp/8;
++ src_ptr = fb_data->info.screen_base + fb_data->fb_offset
++ + src_upd_region->top * src_stride;
++ }
++
++ temp_buf_stride = ALIGN(src_upd_region->width, 8) * bpp/8;
++ left_offs = src_upd_region->left * bpp/8;
++ right_offs = src_upd_region->width * bpp/8;
++ x_trailing_bytes = (ALIGN(src_upd_region->width, 8)
++ - src_upd_region->width) * bpp/8;
++
++ for (i = 0; i < src_upd_region->height; i++) {
++ /* Copy the full line */
++ memcpy(temp_buf_ptr, src_ptr + left_offs,
++ src_upd_region->width * bpp/8);
++
++ /* Clear any unwanted pixels at the end of each line */
++ if (src_upd_region->width & 0x7) {
++ memset(temp_buf_ptr + right_offs, 0x0,
++ x_trailing_bytes);
++ }
++
++ temp_buf_ptr += temp_buf_stride;
++ src_ptr += src_stride;
++ }
++
++ /* Clear any unwanted pixels at the bottom of the end of each line */
++ if (src_upd_region->height & 0x7) {
++ y_trailing_bytes = (ALIGN(src_upd_region->height, 8)
++ - src_upd_region->height) *
++ ALIGN(src_upd_region->width, 8) * bpp/8;
++ memset(temp_buf_ptr, 0x0, y_trailing_bytes);
++ }
++}
++
++static int epdc_process_update(struct update_data_list *upd_data_list,
++ struct mxc_epdc_fb_data *fb_data)
++{
++ struct mxcfb_rect *src_upd_region; /* Region of src buffer for update */
++ struct mxcfb_rect pxp_upd_region;
++ u32 src_width, src_height;
++ u32 offset_from_4, bytes_per_pixel;
++ u32 post_rotation_xcoord, post_rotation_ycoord, width_pxp_blocks;
++ u32 pxp_input_offs, pxp_output_offs, pxp_output_shift;
++ u32 hist_stat = 0;
++ int width_unaligned, height_unaligned;
++ bool input_unaligned = false;
++ bool line_overflow = false;
++ int pix_per_line_added;
++ bool use_temp_buf = false;
++ struct mxcfb_rect temp_buf_upd_region;
++ struct update_desc_list *upd_desc_list = upd_data_list->update_desc;
++
++ int ret;
++
++ /*
++ * Gotta do a whole bunch of buffer ptr manipulation to
++ * work around HW restrictions for PxP & EPDC
++ * Note: Applies to pre-2.0 versions of EPDC/PxP
++ */
++
++ /*
++ * Are we using FB or an alternate (overlay)
++ * buffer for source of update?
++ */
++ if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_ALT_BUFFER) {
++ src_width = upd_desc_list->upd_data.alt_buffer_data.width;
++ src_height = upd_desc_list->upd_data.alt_buffer_data.height;
++ src_upd_region = &upd_desc_list->upd_data.alt_buffer_data.alt_update_region;
++ } else {
++ src_width = fb_data->epdc_fb_var.xres_virtual;
++ src_height = fb_data->epdc_fb_var.yres;
++ src_upd_region = &upd_desc_list->upd_data.update_region;
++ }
++
++ bytes_per_pixel = fb_data->epdc_fb_var.bits_per_pixel/8;
++
++ /*
++ * SW workaround for PxP limitation (for pre-v2.0 HW)
++ *
++ * There are 3 cases where we cannot process the update data
++ * directly from the input buffer:
++ *
++ * 1) PxP must process 8x8 pixel blocks, and all pixels in each block
++ * are considered for auto-waveform mode selection. If the
++ * update region is not 8x8 aligned, additional unwanted pixels
++ * will be considered in auto-waveform mode selection.
++ *
++ * 2) PxP input must be 32-bit aligned, so any update
++ * address not 32-bit aligned must be shifted to meet the
++ * 32-bit alignment. The PxP will thus end up processing pixels
++ * outside of the update region to satisfy this alignment restriction,
++ * which can affect auto-waveform mode selection.
++ *
++ * 3) If input fails 32-bit alignment, and the resulting expansion
++ * of the processed region would add at least 8 pixels more per
++ * line than the original update line width, the EPDC would
++ * cause screen artifacts by incorrectly handling the 8+ pixels
++ * at the end of each line.
++ *
++ * Workaround is to copy from source buffer into a temporary
++ * buffer, which we pad with zeros to match the 8x8 alignment
++ * requirement. This temp buffer becomes the input to the PxP.
++ */
++ width_unaligned = src_upd_region->width & 0x7;
++ height_unaligned = src_upd_region->height & 0x7;
++
++ offset_from_4 = src_upd_region->left & 0x3;
++ input_unaligned = ((offset_from_4 * bytes_per_pixel % 4) != 0) ?
++ true : false;
++
++ pix_per_line_added = (offset_from_4 * bytes_per_pixel % 4)
++ / bytes_per_pixel;
++ if ((((fb_data->epdc_fb_var.rotate == FB_ROTATE_UR) ||
++ fb_data->epdc_fb_var.rotate == FB_ROTATE_UD)) &&
++ (ALIGN(src_upd_region->width, 8) <
++ ALIGN(src_upd_region->width + pix_per_line_added, 8)))
++ line_overflow = true;
++
++ /* Grab pxp_mutex here so that we protect access
++ * to copybuf in addition to the PxP structures */
++ mutex_lock(&fb_data->pxp_mutex);
++
++ if (((((width_unaligned || height_unaligned || input_unaligned) &&
++ (upd_desc_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO))
++ || line_overflow) && (fb_data->rev < 20)) ||
++ fb_data->restrict_width) {
++ dev_dbg(fb_data->dev, "Copying update before processing.\n");
++
++ /* Update to reflect what the new source buffer will be */
++ src_width = ALIGN(src_upd_region->width, 8);
++ src_height = ALIGN(src_upd_region->height, 8);
++
++ copy_before_process(fb_data, upd_data_list);
++
++ /*
++ * src_upd_region should now describe
++ * the new update buffer attributes.
++ */
++ temp_buf_upd_region.left = 0;
++ temp_buf_upd_region.top = 0;
++ temp_buf_upd_region.width = src_upd_region->width;
++ temp_buf_upd_region.height = src_upd_region->height;
++ src_upd_region = &temp_buf_upd_region;
++
++ use_temp_buf = true;
++ }
++
++ /*
++ * For pre-2.0 HW, input address must be 32-bit aligned
++ * Compute buffer offset to account for this PxP limitation
++ */
++ offset_from_4 = src_upd_region->left & 0x3;
++ input_unaligned = ((offset_from_4 * bytes_per_pixel % 4) != 0) ?
++ true : false;
++ if ((fb_data->rev < 20) && input_unaligned) {
++ /* Leave a gap between PxP input addr and update region pixels */
++ pxp_input_offs =
++ (src_upd_region->top * src_width + src_upd_region->left)
++ * bytes_per_pixel & 0xFFFFFFFC;
++ /* Update region left changes to reflect relative position to input ptr */
++ pxp_upd_region.left = (offset_from_4 * bytes_per_pixel % 4)
++ / bytes_per_pixel;
++ } else {
++ pxp_input_offs =
++ (src_upd_region->top * src_width + src_upd_region->left)
++ * bytes_per_pixel;
++ pxp_upd_region.left = 0;
++ }
++
++ pxp_upd_region.top = 0;
++
++ /*
++ * For version 2.0 and later of EPDC & PxP, if no rotation, we don't
++ * need to align width & height (rotation always requires 8-pixel
++ * width & height alignment, per PxP limitations)
++ */
++ if ((fb_data->epdc_fb_var.rotate == 0) && (fb_data->rev >= 20)) {
++ pxp_upd_region.width = src_upd_region->width;
++ pxp_upd_region.height = src_upd_region->height;
++ } else {
++ /* Update region dimensions to meet 8x8 pixel requirement */
++ pxp_upd_region.width = ALIGN(src_upd_region->width + pxp_upd_region.left, 8);
++ pxp_upd_region.height = ALIGN(src_upd_region->height, 8);
++ }
++
++ switch (fb_data->epdc_fb_var.rotate) {
++ case FB_ROTATE_UR:
++ default:
++ post_rotation_xcoord = pxp_upd_region.left;
++ post_rotation_ycoord = pxp_upd_region.top;
++ width_pxp_blocks = pxp_upd_region.width;
++ break;
++ case FB_ROTATE_CW:
++ width_pxp_blocks = pxp_upd_region.height;
++ post_rotation_xcoord = width_pxp_blocks - src_upd_region->height;
++ post_rotation_ycoord = pxp_upd_region.left;
++ break;
++ case FB_ROTATE_UD:
++ width_pxp_blocks = pxp_upd_region.width;
++ post_rotation_xcoord = width_pxp_blocks - src_upd_region->width - pxp_upd_region.left;
++ post_rotation_ycoord = pxp_upd_region.height - src_upd_region->height - pxp_upd_region.top;
++ break;
++ case FB_ROTATE_CCW:
++ width_pxp_blocks = pxp_upd_region.height;
++ post_rotation_xcoord = pxp_upd_region.top;
++ post_rotation_ycoord = pxp_upd_region.width - src_upd_region->width - pxp_upd_region.left;
++ break;
++ }
++
++ /* Update region start coord to force PxP to process full 8x8 regions */
++ pxp_upd_region.top &= ~0x7;
++ pxp_upd_region.left &= ~0x7;
++
++ if (fb_data->rev < 20) {
++ pxp_output_shift = ALIGN(post_rotation_xcoord, 8)
++ - post_rotation_xcoord;
++
++ pxp_output_offs = post_rotation_ycoord * width_pxp_blocks
++ + pxp_output_shift;
++
++ upd_desc_list->epdc_offs = ALIGN(pxp_output_offs, 8);
++ } else {
++ pxp_output_shift = 0;
++ pxp_output_offs = post_rotation_ycoord * width_pxp_blocks
++ + post_rotation_xcoord;
++
++ upd_desc_list->epdc_offs = pxp_output_offs;
++ }
++
++ upd_desc_list->epdc_stride = width_pxp_blocks;
++
++ /* Source address either comes from alternate buffer
++ provided in update data, or from the framebuffer. */
++ if (use_temp_buf)
++ sg_dma_address(&fb_data->sg[0]) =
++ fb_data->phys_addr_copybuf;
++ else if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_ALT_BUFFER)
++ sg_dma_address(&fb_data->sg[0]) =
++ upd_desc_list->upd_data.alt_buffer_data.phys_addr
++ + pxp_input_offs;
++ else {
++ sg_dma_address(&fb_data->sg[0]) =
++ fb_data->info.fix.smem_start + fb_data->fb_offset
++ + pxp_input_offs;
++ sg_set_page(&fb_data->sg[0],
++ virt_to_page(fb_data->info.screen_base),
++ fb_data->info.fix.smem_len,
++ offset_in_page(fb_data->info.screen_base));
++ }
++
++ /* Update sg[1] to point to output of PxP proc task */
++ sg_dma_address(&fb_data->sg[1]) = upd_data_list->phys_addr
++ + pxp_output_shift;
++ sg_set_page(&fb_data->sg[1], virt_to_page(upd_data_list->virt_addr),
++ fb_data->max_pix_size,
++ offset_in_page(upd_data_list->virt_addr));
++
++ /*
++ * Set PxP LUT transform type based on update flags.
++ */
++ fb_data->pxp_conf.proc_data.lut_transform = 0;
++ if (upd_desc_list->upd_data.flags & EPDC_FLAG_ENABLE_INVERSION)
++ fb_data->pxp_conf.proc_data.lut_transform |= PXP_LUT_INVERT;
++ if (upd_desc_list->upd_data.flags & EPDC_FLAG_FORCE_MONOCHROME)
++ fb_data->pxp_conf.proc_data.lut_transform |=
++ PXP_LUT_BLACK_WHITE;
++ if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_CMAP)
++ fb_data->pxp_conf.proc_data.lut_transform |=
++ PXP_LUT_USE_CMAP;
++
++ /*
++ * Toggle inversion processing if 8-bit
++ * inverted is the current pixel format.
++ */
++ if (fb_data->epdc_fb_var.grayscale == GRAYSCALE_8BIT_INVERTED)
++ fb_data->pxp_conf.proc_data.lut_transform ^= PXP_LUT_INVERT;
++
++ /* This is a blocking call, so upon return PxP tx should be done */
++ ret = pxp_process_update(fb_data, src_width, src_height,
++ &pxp_upd_region);
++ if (ret) {
++ dev_err(fb_data->dev, "Unable to submit PxP update task.\n");
++ mutex_unlock(&fb_data->pxp_mutex);
++ return ret;
++ }
++
++ /* If needed, enable EPDC HW while ePxP is processing */
++ if ((fb_data->power_state == POWER_STATE_OFF)
++ || fb_data->powering_down) {
++ epdc_powerup(fb_data);
++ }
++
++ /* This is a blocking call, so upon return PxP tx should be done */
++ ret = pxp_complete_update(fb_data, &hist_stat);
++ if (ret) {
++ dev_err(fb_data->dev, "Unable to complete PxP update task.\n");
++ mutex_unlock(&fb_data->pxp_mutex);
++ return ret;
++ }
++
++ mutex_unlock(&fb_data->pxp_mutex);
++
++ /* Update waveform mode from PxP histogram results */
++ if ((fb_data->rev <= 20) &&
++ (upd_desc_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO)) {
++ if (hist_stat & 0x1)
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_du;
++ else if (hist_stat & 0x2)
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_gc4;
++ else if (hist_stat & 0x4)
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_gc8;
++ else if (hist_stat & 0x8)
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_gc16;
++ else
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_gc32;
++
++ dev_dbg(fb_data->dev, "hist_stat = 0x%x, new waveform = 0x%x\n",
++ hist_stat, upd_desc_list->upd_data.waveform_mode);
++ }
++
++ return 0;
++}
++
++static int epdc_submit_merge(struct update_desc_list *upd_desc_list,
++ struct update_desc_list *update_to_merge,
++ struct mxc_epdc_fb_data *fb_data)
++{
++ struct mxcfb_update_data *a, *b;
++ struct mxcfb_rect *arect, *brect;
++ struct mxcfb_rect combine;
++ bool use_flags = false;
++
++ a = &upd_desc_list->upd_data;
++ b = &update_to_merge->upd_data;
++ arect = &upd_desc_list->upd_data.update_region;
++ brect = &update_to_merge->upd_data.update_region;
++
++ /* Do not merge a dry-run collision test update */
++ if ((a->flags & EPDC_FLAG_TEST_COLLISION) ||
++ (b->flags & EPDC_FLAG_TEST_COLLISION))
++ return MERGE_BLOCK;
++
++ /*
++ * Updates with different flags must be executed sequentially.
++ * Halt the merge process to ensure this.
++ */
++ if (a->flags != b->flags) {
++ /*
++ * Special exception: if update regions are identical,
++ * we may be able to merge them.
++ */
++ if ((arect->left != brect->left) ||
++ (arect->top != brect->top) ||
++ (arect->width != brect->width) ||
++ (arect->height != brect->height))
++ return MERGE_BLOCK;
++
++ use_flags = true;
++ }
++
++ if (a->update_mode != b->update_mode)
++ a->update_mode = UPDATE_MODE_FULL;
++
++ if (a->waveform_mode != b->waveform_mode)
++ a->waveform_mode = WAVEFORM_MODE_AUTO;
++
++ if (arect->left > (brect->left + brect->width) ||
++ brect->left > (arect->left + arect->width) ||
++ arect->top > (brect->top + brect->height) ||
++ brect->top > (arect->top + arect->height))
++ return MERGE_FAIL;
++
++ combine.left = arect->left < brect->left ? arect->left : brect->left;
++ combine.top = arect->top < brect->top ? arect->top : brect->top;
++ combine.width = (arect->left + arect->width) >
++ (brect->left + brect->width) ?
++ (arect->left + arect->width - combine.left) :
++ (brect->left + brect->width - combine.left);
++ combine.height = (arect->top + arect->height) >
++ (brect->top + brect->height) ?
++ (arect->top + arect->height - combine.top) :
++ (brect->top + brect->height - combine.top);
++
++ /* Don't merge if combined width exceeds max width */
++ if (fb_data->restrict_width) {
++ u32 max_width = EPDC_V2_MAX_UPDATE_WIDTH;
++ u32 combined_width = combine.width;
++ if (fb_data->epdc_fb_var.rotate != FB_ROTATE_UR)
++ max_width -= EPDC_V2_ROTATION_ALIGNMENT;
++ if ((fb_data->epdc_fb_var.rotate == FB_ROTATE_CW) ||
++ (fb_data->epdc_fb_var.rotate == FB_ROTATE_CCW))
++ combined_width = combine.height;
++ if (combined_width > max_width)
++ return MERGE_FAIL;
++ }
++
++ *arect = combine;
++
++ /* Use flags of the later update */
++ if (use_flags)
++ a->flags = b->flags;
++
++ /* Merge markers */
++ list_splice_tail(&update_to_merge->upd_marker_list,
++ &upd_desc_list->upd_marker_list);
++
++ /* Merged update should take on the earliest order */
++ upd_desc_list->update_order =
++ (upd_desc_list->update_order > update_to_merge->update_order) ?
++ upd_desc_list->update_order : update_to_merge->update_order;
++
++ return MERGE_OK;
++}
++
++static void epdc_submit_work_func(struct work_struct *work)
++{
++ int temp_index;
++ struct update_data_list *next_update, *temp_update;
++ struct update_desc_list *next_desc, *temp_desc;
++ struct update_marker_data *next_marker, *temp_marker;
++ struct mxc_epdc_fb_data *fb_data =
++ container_of(work, struct mxc_epdc_fb_data, epdc_submit_work);
++ struct update_data_list *upd_data_list = NULL;
++ struct mxcfb_rect adj_update_region, *upd_region;
++ bool end_merge = false;
++ bool is_transform;
++ u32 update_addr;
++ int *err_dist;
++ int ret;
++
++ /* Protect access to buffer queues and to update HW */
++ mutex_lock(&fb_data->queue_mutex);
++
++ /*
++ * Are any of our collision updates able to go now?
++ * Go through all updates in the collision list and check to see
++ * if the collision mask has been fully cleared
++ */
++ list_for_each_entry_safe(next_update, temp_update,
++ &fb_data->upd_buf_collision_list, list) {
++
++ if (next_update->collision_mask != 0)
++ continue;
++
++ dev_dbg(fb_data->dev, "A collision update is ready to go!\n");
++
++ /* Force waveform mode to auto for resubmitted collisions */
++ next_update->update_desc->upd_data.waveform_mode =
++ WAVEFORM_MODE_AUTO;
++
++ /*
++ * We have a collision cleared, so select it for resubmission.
++ * If an update is already selected, attempt to merge.
++ */
++ if (!upd_data_list) {
++ upd_data_list = next_update;
++ list_del_init(&next_update->list);
++ if (fb_data->upd_scheme == UPDATE_SCHEME_QUEUE)
++ /* If not merging, we have our update */
++ break;
++ } else {
++ switch (epdc_submit_merge(upd_data_list->update_desc,
++ next_update->update_desc,
++ fb_data)) {
++ case MERGE_OK:
++ dev_dbg(fb_data->dev,
++ "Update merged [collision]\n");
++ list_del_init(&next_update->update_desc->list);
++ kfree(next_update->update_desc);
++ next_update->update_desc = NULL;
++ list_del_init(&next_update->list);
++ /* Add to free buffer list */
++ list_add_tail(&next_update->list,
++ &fb_data->upd_buf_free_list);
++ break;
++ case MERGE_FAIL:
++ dev_dbg(fb_data->dev,
++ "Update not merged [collision]\n");
++ break;
++ case MERGE_BLOCK:
++ dev_dbg(fb_data->dev,
++ "Merge blocked [collision]\n");
++ end_merge = true;
++ break;
++ }
++
++ if (end_merge) {
++ end_merge = false;
++ break;
++ }
++ }
++ }
++
++ /*
++ * Skip pending update list only if we found a collision
++ * update and we are not merging
++ */
++ if (!((fb_data->upd_scheme == UPDATE_SCHEME_QUEUE) &&
++ upd_data_list)) {
++ /*
++ * If we didn't find a collision update ready to go, we
++ * need to get a free buffer and match it to a pending update.
++ */
++
++ /*
++ * Can't proceed if there are no free buffers (and we don't
++ * already have a collision update selected)
++ */
++ if (!upd_data_list &&
++ list_empty(&fb_data->upd_buf_free_list)) {
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ list_for_each_entry_safe(next_desc, temp_desc,
++ &fb_data->upd_pending_list, list) {
++
++ dev_dbg(fb_data->dev, "Found a pending update!\n");
++
++ if (!upd_data_list) {
++ if (list_empty(&fb_data->upd_buf_free_list))
++ break;
++ upd_data_list =
++ list_entry(fb_data->upd_buf_free_list.next,
++ struct update_data_list, list);
++ list_del_init(&upd_data_list->list);
++ upd_data_list->update_desc = next_desc;
++ list_del_init(&next_desc->list);
++ if (fb_data->upd_scheme == UPDATE_SCHEME_QUEUE)
++ /* If not merging, we have an update */
++ break;
++ } else {
++ switch (epdc_submit_merge(upd_data_list->update_desc,
++ next_desc, fb_data)) {
++ case MERGE_OK:
++ dev_dbg(fb_data->dev,
++ "Update merged [queue]\n");
++ list_del_init(&next_desc->list);
++ kfree(next_desc);
++ break;
++ case MERGE_FAIL:
++ dev_dbg(fb_data->dev,
++ "Update not merged [queue]\n");
++ break;
++ case MERGE_BLOCK:
++ dev_dbg(fb_data->dev,
++ "Merge blocked [collision]\n");
++ end_merge = true;
++ break;
++ }
++
++ if (end_merge)
++ break;
++ }
++ }
++ }
++
++ /* Is update list empty? */
++ if (!upd_data_list) {
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ /*
++ * If no processing required, skip update processing
++ * No processing means:
++ * - FB unrotated
++ * - FB pixel format = 8-bit grayscale
++ * - No look-up transformations (inversion, posterization, etc.)
++ *
++ * Note: A bug with EPDC stride prevents us from skipping
++ * PxP in versions 2.0 and earlier of EPDC.
++ */
++ is_transform = upd_data_list->update_desc->upd_data.flags &
++ (EPDC_FLAG_ENABLE_INVERSION | EPDC_FLAG_USE_DITHERING_Y1 |
++ EPDC_FLAG_USE_DITHERING_Y4 | EPDC_FLAG_FORCE_MONOCHROME |
++ EPDC_FLAG_USE_CMAP) ? true : false;
++
++ if ((fb_data->epdc_fb_var.rotate == FB_ROTATE_UR) &&
++ (fb_data->epdc_fb_var.grayscale == GRAYSCALE_8BIT) &&
++ !is_transform && (fb_data->rev > 20) &&
++ !fb_data->restrict_width) {
++
++ /* If needed, enable EPDC HW while ePxP is processing */
++ if ((fb_data->power_state == POWER_STATE_OFF)
++ || fb_data->powering_down)
++ epdc_powerup(fb_data);
++
++ /*
++ * Set update buffer pointer to the start of
++ * the update region in the frame buffer.
++ */
++ upd_region = &upd_data_list->update_desc->upd_data.update_region;
++ update_addr = fb_data->info.fix.smem_start +
++ ((upd_region->top * fb_data->info.var.xres_virtual) +
++ upd_region->left) * fb_data->info.var.bits_per_pixel/8;
++ upd_data_list->update_desc->epdc_stride =
++ fb_data->info.var.xres_virtual *
++ fb_data->info.var.bits_per_pixel/8;
++ } else {
++ /* Select from PxP output buffers */
++ upd_data_list->phys_addr =
++ fb_data->phys_addr_updbuf[fb_data->upd_buffer_num];
++ upd_data_list->virt_addr =
++ fb_data->virt_addr_updbuf[fb_data->upd_buffer_num];
++ fb_data->upd_buffer_num++;
++ if (fb_data->upd_buffer_num > fb_data->max_num_buffers-1)
++ fb_data->upd_buffer_num = 0;
++
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++
++ /* Perform PXP processing - EPDC power will also be enabled */
++ if (epdc_process_update(upd_data_list, fb_data)) {
++ dev_dbg(fb_data->dev, "PXP processing error.\n");
++ /* Protect access to buffer queues and to update HW */
++ mutex_lock(&fb_data->queue_mutex);
++ list_del_init(&upd_data_list->update_desc->list);
++ kfree(upd_data_list->update_desc);
++ upd_data_list->update_desc = NULL;
++ /* Add to free buffer list */
++ list_add_tail(&upd_data_list->list,
++ &fb_data->upd_buf_free_list);
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ /* Protect access to buffer queues and to update HW */
++ mutex_lock(&fb_data->queue_mutex);
++
++ update_addr = upd_data_list->phys_addr
++ + upd_data_list->update_desc->epdc_offs;
++ }
++
++ /* Get rotation-adjusted coordinates */
++ adjust_coordinates(fb_data->epdc_fb_var.xres,
++ fb_data->epdc_fb_var.yres, fb_data->epdc_fb_var.rotate,
++ &upd_data_list->update_desc->upd_data.update_region,
++ &adj_update_region);
++
++ /*
++ * Is the working buffer idle?
++ * If the working buffer is busy, we must wait for the resource
++ * to become free. The IST will signal this event.
++ */
++ if (fb_data->cur_update != NULL) {
++ dev_dbg(fb_data->dev, "working buf busy!\n");
++
++ /* Initialize event signalling an update resource is free */
++ init_completion(&fb_data->update_res_free);
++
++ fb_data->waiting_for_wb = true;
++
++ /* Leave spinlock while waiting for WB to complete */
++ mutex_unlock(&fb_data->queue_mutex);
++ wait_for_completion(&fb_data->update_res_free);
++ mutex_lock(&fb_data->queue_mutex);
++ }
++
++ /*
++ * Dithering Processing (Version 1.0 - for i.MX508 and i.MX6SL)
++ */
++ if (upd_data_list->update_desc->upd_data.flags &
++ EPDC_FLAG_USE_DITHERING_Y1) {
++
++ err_dist = kzalloc((fb_data->info.var.xres_virtual + 3) * 3
++ * sizeof(int), GFP_KERNEL);
++
++ /* Dithering Y8 -> Y1 */
++ do_dithering_processing_Y1_v1_0(
++ (uint8_t *)(upd_data_list->virt_addr +
++ upd_data_list->update_desc->epdc_offs),
++ &adj_update_region,
++ (fb_data->rev < 20) ?
++ ALIGN(adj_update_region.width, 8) :
++ adj_update_region.width,
++ err_dist);
++
++ kfree(err_dist);
++ } else if (upd_data_list->update_desc->upd_data.flags &
++ EPDC_FLAG_USE_DITHERING_Y4) {
++
++ err_dist = kzalloc((fb_data->info.var.xres_virtual + 3) * 3
++ * sizeof(int), GFP_KERNEL);
++
++ /* Dithering Y8 -> Y1 */
++ do_dithering_processing_Y4_v1_0(
++ (uint8_t *)(upd_data_list->virt_addr +
++ upd_data_list->update_desc->epdc_offs),
++ &adj_update_region,
++ (fb_data->rev < 20) ?
++ ALIGN(adj_update_region.width, 8) :
++ adj_update_region.width,
++ err_dist);
++
++ kfree(err_dist);
++ }
++
++ /*
++ * If there are no LUTs available,
++ * then we must wait for the resource to become free.
++ * The IST will signal this event.
++ */
++ if (!epdc_any_luts_available()) {
++ dev_dbg(fb_data->dev, "no luts available!\n");
++
++ /* Initialize event signalling an update resource is free */
++ init_completion(&fb_data->update_res_free);
++
++ fb_data->waiting_for_lut = true;
++
++ /* Leave spinlock while waiting for LUT to free up */
++ mutex_unlock(&fb_data->queue_mutex);
++ wait_for_completion(&fb_data->update_res_free);
++ mutex_lock(&fb_data->queue_mutex);
++ }
++
++ ret = epdc_choose_next_lut(fb_data->rev, &upd_data_list->lut_num);
++ /*
++ * If LUT15 is in use (for pre-EPDC v2.0 hardware):
++ * - Wait for LUT15 to complete is if TCE underrun prevent is enabled
++ * - If we go ahead with update, sync update submission with EOF
++ */
++ if (ret && fb_data->tce_prevent && (fb_data->rev < 20)) {
++ dev_dbg(fb_data->dev, "Waiting for LUT15\n");
++
++ /* Initialize event signalling that lut15 is free */
++ init_completion(&fb_data->lut15_free);
++
++ fb_data->waiting_for_lut15 = true;
++
++ /* Leave spinlock while waiting for LUT to free up */
++ mutex_unlock(&fb_data->queue_mutex);
++ wait_for_completion(&fb_data->lut15_free);
++ mutex_lock(&fb_data->queue_mutex);
++
++ epdc_choose_next_lut(fb_data->rev, &upd_data_list->lut_num);
++ } else if (ret && (fb_data->rev < 20)) {
++ /* Synchronize update submission time to reduce
++ chances of TCE underrun */
++ init_completion(&fb_data->eof_event);
++
++ epdc_eof_intr(true);
++
++ /* Leave spinlock while waiting for EOF event */
++ mutex_unlock(&fb_data->queue_mutex);
++ ret = wait_for_completion_timeout(&fb_data->eof_event,
++ msecs_to_jiffies(1000));
++ if (!ret) {
++ dev_err(fb_data->dev, "Missed EOF event!\n");
++ epdc_eof_intr(false);
++ }
++ udelay(fb_data->eof_sync_period);
++ mutex_lock(&fb_data->queue_mutex);
++
++ }
++
++ /* LUTs are available, so we get one here */
++ fb_data->cur_update = upd_data_list;
++
++ /* Reset mask for LUTS that have completed during WB processing */
++ fb_data->luts_complete_wb = 0;
++
++ /* If we are just testing for collision, we don't assign a LUT,
++ * so we don't need to update LUT-related resources. */
++ if (!(upd_data_list->update_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION)) {
++ /* Associate LUT with update marker */
++ list_for_each_entry_safe(next_marker, temp_marker,
++ &upd_data_list->update_desc->upd_marker_list, upd_list)
++ next_marker->lut_num = fb_data->cur_update->lut_num;
++
++ /* Mark LUT with order */
++ fb_data->lut_update_order[upd_data_list->lut_num] =
++ upd_data_list->update_desc->update_order;
++
++ epdc_lut_complete_intr(fb_data->rev, upd_data_list->lut_num,
++ true);
++ }
++
++ /* Enable Collision and WB complete IRQs */
++ epdc_working_buf_intr(true);
++
++ /* Program EPDC update to process buffer */
++ if (upd_data_list->update_desc->upd_data.temp != TEMP_USE_AMBIENT) {
++ temp_index = mxc_epdc_fb_get_temp_index(fb_data,
++ upd_data_list->update_desc->upd_data.temp);
++ epdc_set_temp(temp_index);
++ } else
++ epdc_set_temp(fb_data->temp_index);
++ epdc_set_update_addr(update_addr);
++ epdc_set_update_coord(adj_update_region.left, adj_update_region.top);
++ epdc_set_update_dimensions(adj_update_region.width,
++ adj_update_region.height);
++ if (fb_data->rev > 20)
++ epdc_set_update_stride(upd_data_list->update_desc->epdc_stride);
++ if (fb_data->wv_modes_update &&
++ (upd_data_list->update_desc->upd_data.waveform_mode
++ == WAVEFORM_MODE_AUTO)) {
++ epdc_set_update_waveform(&fb_data->wv_modes);
++ fb_data->wv_modes_update = false;
++ }
++
++ epdc_submit_update(upd_data_list->lut_num,
++ upd_data_list->update_desc->upd_data.waveform_mode,
++ upd_data_list->update_desc->upd_data.update_mode,
++ (upd_data_list->update_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION) ? true : false,
++ false, 0);
++
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++}
++
++static int mxc_epdc_fb_send_single_update(struct mxcfb_update_data *upd_data,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++ struct update_data_list *upd_data_list = NULL;
++ struct mxcfb_rect *screen_upd_region; /* Region on screen to update */
++ int temp_index;
++ int ret;
++ struct update_desc_list *upd_desc;
++ struct update_marker_data *marker_data, *next_marker, *temp_marker;
++
++ /* Has EPDC HW been initialized? */
++ if (!fb_data->hw_ready) {
++ /* Throw message if we are not mid-initialization */
++ if (!fb_data->hw_initializing)
++ dev_err(fb_data->dev, "Display HW not properly"
++ "initialized. Aborting update.\n");
++ return -EPERM;
++ }
++
++ /* Check validity of update params */
++ if ((upd_data->update_mode != UPDATE_MODE_PARTIAL) &&
++ (upd_data->update_mode != UPDATE_MODE_FULL)) {
++ dev_err(fb_data->dev,
++ "Update mode 0x%x is invalid. Aborting update.\n",
++ upd_data->update_mode);
++ return -EINVAL;
++ }
++ if ((upd_data->waveform_mode > 255) &&
++ (upd_data->waveform_mode != WAVEFORM_MODE_AUTO)) {
++ dev_err(fb_data->dev,
++ "Update waveform mode 0x%x is invalid."
++ " Aborting update.\n",
++ upd_data->waveform_mode);
++ return -EINVAL;
++ }
++ if ((upd_data->update_region.left + upd_data->update_region.width > fb_data->epdc_fb_var.xres) ||
++ (upd_data->update_region.top + upd_data->update_region.height > fb_data->epdc_fb_var.yres)) {
++ dev_err(fb_data->dev,
++ "Update region is outside bounds of framebuffer."
++ "Aborting update.\n");
++ return -EINVAL;
++ }
++ if (upd_data->flags & EPDC_FLAG_USE_ALT_BUFFER) {
++ if ((upd_data->update_region.width !=
++ upd_data->alt_buffer_data.alt_update_region.width) ||
++ (upd_data->update_region.height !=
++ upd_data->alt_buffer_data.alt_update_region.height)) {
++ dev_err(fb_data->dev,
++ "Alternate update region dimensions must "
++ "match screen update region dimensions.\n");
++ return -EINVAL;
++ }
++ /* Validate physical address parameter */
++ if ((upd_data->alt_buffer_data.phys_addr <
++ fb_data->info.fix.smem_start) ||
++ (upd_data->alt_buffer_data.phys_addr >
++ fb_data->info.fix.smem_start + fb_data->map_size)) {
++ dev_err(fb_data->dev,
++ "Invalid physical address for alternate "
++ "buffer. Aborting update...\n");
++ return -EINVAL;
++ }
++ }
++
++ mutex_lock(&fb_data->queue_mutex);
++
++ /*
++ * If we are waiting to go into suspend, or the FB is blanked,
++ * we do not accept new updates
++ */
++ if ((fb_data->waiting_for_idle) ||
++ (fb_data->blank != FB_BLANK_UNBLANK)) {
++ dev_dbg(fb_data->dev, "EPDC not active."
++ "Update request abort.\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return -EPERM;
++ }
++
++ if (fb_data->upd_scheme == UPDATE_SCHEME_SNAPSHOT) {
++ int count = 0;
++ struct update_data_list *plist;
++
++ /*
++ * If next update is a FULL mode update, then we must
++ * ensure that all pending & active updates are complete
++ * before submitting the update. Otherwise, the FULL
++ * mode update may cause an endless collision loop with
++ * other updates. Block here until updates are flushed.
++ */
++ if (upd_data->update_mode == UPDATE_MODE_FULL) {
++ mutex_unlock(&fb_data->queue_mutex);
++ mxc_epdc_fb_flush_updates(fb_data);
++ mutex_lock(&fb_data->queue_mutex);
++ }
++
++ /* Count buffers in free buffer list */
++ list_for_each_entry(plist, &fb_data->upd_buf_free_list, list)
++ count++;
++
++ /* Use count to determine if we have enough
++ * free buffers to handle this update request */
++ if (count + fb_data->max_num_buffers
++ <= fb_data->max_num_updates) {
++ dev_err(fb_data->dev,
++ "No free intermediate buffers available.\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return -ENOMEM;
++ }
++
++ /* Grab first available buffer and delete from the free list */
++ upd_data_list =
++ list_entry(fb_data->upd_buf_free_list.next,
++ struct update_data_list, list);
++
++ list_del_init(&upd_data_list->list);
++ }
++
++ /*
++ * Create new update data structure, fill it with new update
++ * data and add it to the list of pending updates
++ */
++ upd_desc = kzalloc(sizeof(struct update_desc_list), GFP_KERNEL);
++ if (!upd_desc) {
++ dev_err(fb_data->dev,
++ "Insufficient system memory for update! Aborting.\n");
++ if (fb_data->upd_scheme == UPDATE_SCHEME_SNAPSHOT) {
++ list_add(&upd_data_list->list,
++ &fb_data->upd_buf_free_list);
++ }
++ mutex_unlock(&fb_data->queue_mutex);
++ return -EPERM;
++ }
++ /* Initialize per-update marker list */
++ INIT_LIST_HEAD(&upd_desc->upd_marker_list);
++ upd_desc->upd_data = *upd_data;
++ upd_desc->update_order = fb_data->order_cnt++;
++ list_add_tail(&upd_desc->list, &fb_data->upd_pending_list);
++
++ /* If marker specified, associate it with a completion */
++ if (upd_data->update_marker != 0) {
++ /* Allocate new update marker and set it up */
++ marker_data = kzalloc(sizeof(struct update_marker_data),
++ GFP_KERNEL);
++ if (!marker_data) {
++ dev_err(fb_data->dev, "No memory for marker!\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return -ENOMEM;
++ }
++ list_add_tail(&marker_data->upd_list,
++ &upd_desc->upd_marker_list);
++ marker_data->update_marker = upd_data->update_marker;
++ if (upd_desc->upd_data.flags & EPDC_FLAG_TEST_COLLISION)
++ marker_data->lut_num = DRY_RUN_NO_LUT;
++ else
++ marker_data->lut_num = INVALID_LUT;
++ init_completion(&marker_data->update_completion);
++ /* Add marker to master marker list */
++ list_add_tail(&marker_data->full_list,
++ &fb_data->full_marker_list);
++ }
++
++ if (fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT) {
++ /* Queued update scheme processing */
++
++ mutex_unlock(&fb_data->queue_mutex);
++
++ /* Signal workqueue to handle new update */
++ queue_work(fb_data->epdc_submit_workqueue,
++ &fb_data->epdc_submit_work);
++
++ return 0;
++ }
++
++ /* Snapshot update scheme processing */
++
++ /* Set descriptor for current update, delete from pending list */
++ upd_data_list->update_desc = upd_desc;
++ list_del_init(&upd_desc->list);
++
++ mutex_unlock(&fb_data->queue_mutex);
++
++ /*
++ * Hold on to original screen update region, which we
++ * will ultimately use when telling EPDC where to update on panel
++ */
++ screen_upd_region = &upd_desc->upd_data.update_region;
++
++ /* Select from PxP output buffers */
++ upd_data_list->phys_addr =
++ fb_data->phys_addr_updbuf[fb_data->upd_buffer_num];
++ upd_data_list->virt_addr =
++ fb_data->virt_addr_updbuf[fb_data->upd_buffer_num];
++ fb_data->upd_buffer_num++;
++ if (fb_data->upd_buffer_num > fb_data->max_num_buffers-1)
++ fb_data->upd_buffer_num = 0;
++
++ ret = epdc_process_update(upd_data_list, fb_data);
++ if (ret) {
++ mutex_unlock(&fb_data->pxp_mutex);
++ return ret;
++ }
++
++ /* Pass selected waveform mode back to user */
++ upd_data->waveform_mode = upd_desc->upd_data.waveform_mode;
++
++ /* Get rotation-adjusted coordinates */
++ adjust_coordinates(fb_data->epdc_fb_var.xres,
++ fb_data->epdc_fb_var.yres, fb_data->epdc_fb_var.rotate,
++ &upd_desc->upd_data.update_region, NULL);
++
++ /* Grab lock for queue manipulation and update submission */
++ mutex_lock(&fb_data->queue_mutex);
++
++ /*
++ * Is the working buffer idle?
++ * If either the working buffer is busy, or there are no LUTs available,
++ * then we return and let the ISR handle the update later
++ */
++ if ((fb_data->cur_update != NULL) || !epdc_any_luts_available()) {
++ /* Add processed Y buffer to update list */
++ list_add_tail(&upd_data_list->list, &fb_data->upd_buf_queue);
++
++ /* Return and allow the update to be submitted by the ISR. */
++ mutex_unlock(&fb_data->queue_mutex);
++ return 0;
++ }
++
++ /* LUTs are available, so we get one here */
++ ret = epdc_choose_next_lut(fb_data->rev, &upd_data_list->lut_num);
++ if (ret && fb_data->tce_prevent && (fb_data->rev < 20)) {
++ dev_dbg(fb_data->dev, "Must wait for LUT15\n");
++ /* Add processed Y buffer to update list */
++ list_add_tail(&upd_data_list->list, &fb_data->upd_buf_queue);
++
++ /* Return and allow the update to be submitted by the ISR. */
++ mutex_unlock(&fb_data->queue_mutex);
++ return 0;
++ }
++
++ if (!(upd_data_list->update_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION)) {
++
++ /* Save current update */
++ fb_data->cur_update = upd_data_list;
++
++ /* Reset mask for LUTS that have completed during WB processing */
++ fb_data->luts_complete_wb = 0;
++
++ /* Associate LUT with update marker */
++ list_for_each_entry_safe(next_marker, temp_marker,
++ &upd_data_list->update_desc->upd_marker_list, upd_list)
++ next_marker->lut_num = upd_data_list->lut_num;
++
++ /* Mark LUT as containing new update */
++ fb_data->lut_update_order[upd_data_list->lut_num] =
++ upd_desc->update_order;
++
++ epdc_lut_complete_intr(fb_data->rev, upd_data_list->lut_num,
++ true);
++ }
++
++ /* Clear status and Enable LUT complete and WB complete IRQs */
++ epdc_working_buf_intr(true);
++
++ /* Program EPDC update to process buffer */
++ epdc_set_update_addr(upd_data_list->phys_addr + upd_desc->epdc_offs);
++ epdc_set_update_coord(screen_upd_region->left, screen_upd_region->top);
++ epdc_set_update_dimensions(screen_upd_region->width,
++ screen_upd_region->height);
++ if (fb_data->rev > 20)
++ epdc_set_update_stride(upd_desc->epdc_stride);
++ if (upd_desc->upd_data.temp != TEMP_USE_AMBIENT) {
++ temp_index = mxc_epdc_fb_get_temp_index(fb_data,
++ upd_desc->upd_data.temp);
++ epdc_set_temp(temp_index);
++ } else
++ epdc_set_temp(fb_data->temp_index);
++ if (fb_data->wv_modes_update &&
++ (upd_desc->upd_data.waveform_mode == WAVEFORM_MODE_AUTO)) {
++ epdc_set_update_waveform(&fb_data->wv_modes);
++ fb_data->wv_modes_update = false;
++ }
++
++ epdc_submit_update(upd_data_list->lut_num,
++ upd_desc->upd_data.waveform_mode,
++ upd_desc->upd_data.update_mode,
++ (upd_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION) ? true : false,
++ false, 0);
++
++ mutex_unlock(&fb_data->queue_mutex);
++ return 0;
++}
++
++int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ if (!fb_data->restrict_width) {
++ /* No width restriction, send entire update region */
++ return mxc_epdc_fb_send_single_update(upd_data, info);
++ } else {
++ int ret;
++ __u32 width, left;
++ __u32 marker;
++ __u32 *region_width, *region_left;
++ u32 max_upd_width = EPDC_V2_MAX_UPDATE_WIDTH;
++
++ /* Further restrict max width due to pxp rotation
++ * alignment requirement
++ */
++ if (fb_data->epdc_fb_var.rotate != FB_ROTATE_UR)
++ max_upd_width -= EPDC_V2_ROTATION_ALIGNMENT;
++
++ /* Select split of width or height based on rotation */
++ if ((fb_data->epdc_fb_var.rotate == FB_ROTATE_UR) ||
++ (fb_data->epdc_fb_var.rotate == FB_ROTATE_UD)) {
++ region_width = &upd_data->update_region.width;
++ region_left = &upd_data->update_region.left;
++ } else {
++ region_width = &upd_data->update_region.height;
++ region_left = &upd_data->update_region.top;
++ }
++
++ if (*region_width <= max_upd_width)
++ return mxc_epdc_fb_send_single_update(upd_data, info);
++
++ width = *region_width;
++ left = *region_left;
++ marker = upd_data->update_marker;
++ upd_data->update_marker = 0;
++
++ do {
++ *region_width = max_upd_width;
++ *region_left = left;
++ ret = mxc_epdc_fb_send_single_update(upd_data, info);
++ if (ret)
++ return ret;
++ width -= max_upd_width;
++ left += max_upd_width;
++ } while (width > max_upd_width);
++
++ *region_width = width;
++ *region_left = left;
++ upd_data->update_marker = marker;
++ return mxc_epdc_fb_send_single_update(upd_data, info);
++ }
++}
++EXPORT_SYMBOL(mxc_epdc_fb_send_update);
++
++int mxc_epdc_fb_wait_update_complete(struct mxcfb_update_marker_data *marker_data,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++ struct update_marker_data *next_marker;
++ struct update_marker_data *temp;
++ bool marker_found = false;
++ int ret = 0;
++
++ /* 0 is an invalid update_marker value */
++ if (marker_data->update_marker == 0)
++ return -EINVAL;
++
++ /*
++ * Find completion associated with update_marker requested.
++ * Note: If update completed already, marker will have been
++ * cleared, it won't be found, and function will just return.
++ */
++
++ /* Grab queue lock to protect access to marker list */
++ mutex_lock(&fb_data->queue_mutex);
++
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->full_marker_list, full_list) {
++ if (next_marker->update_marker == marker_data->update_marker) {
++ dev_dbg(fb_data->dev, "Waiting for marker %d\n",
++ marker_data->update_marker);
++ next_marker->waiting = true;
++ marker_found = true;
++ break;
++ }
++ }
++
++ mutex_unlock(&fb_data->queue_mutex);
++
++ /*
++ * If marker not found, it has either been signalled already
++ * or the update request failed. In either case, just return.
++ */
++ if (!marker_found)
++ return ret;
++
++ ret = wait_for_completion_timeout(&next_marker->update_completion,
++ msecs_to_jiffies(5000));
++ if (!ret) {
++ dev_err(fb_data->dev,
++ "Timed out waiting for update completion\n");
++ return -ETIMEDOUT;
++ }
++
++ marker_data->collision_test = next_marker->collision_test;
++
++ /* Free update marker object */
++ kfree(next_marker);
++
++ return ret;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_wait_update_complete);
++
++int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ fb_data->pwrdown_delay = pwrdown_delay;
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_pwrdown_delay);
++
++int mxc_epdc_get_pwrdown_delay(struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ return fb_data->pwrdown_delay;
++}
++EXPORT_SYMBOL(mxc_epdc_get_pwrdown_delay);
++
++static int mxc_epdc_fb_ioctl(struct fb_info *info, unsigned int cmd,
++ unsigned long arg)
++{
++ void __user *argp = (void __user *)arg;
++ int ret = -EINVAL;
++
++ switch (cmd) {
++ case MXCFB_SET_WAVEFORM_MODES:
++ {
++ struct mxcfb_waveform_modes modes;
++ if (!copy_from_user(&modes, argp, sizeof(modes))) {
++ mxc_epdc_fb_set_waveform_modes(&modes, info);
++ ret = 0;
++ }
++ break;
++ }
++ case MXCFB_SET_TEMPERATURE:
++ {
++ int temperature;
++ if (!get_user(temperature, (int32_t __user *) arg))
++ ret = mxc_epdc_fb_set_temperature(temperature,
++ info);
++ break;
++ }
++ case MXCFB_SET_AUTO_UPDATE_MODE:
++ {
++ u32 auto_mode = 0;
++ if (!get_user(auto_mode, (__u32 __user *) arg))
++ ret = mxc_epdc_fb_set_auto_update(auto_mode,
++ info);
++ break;
++ }
++ case MXCFB_SET_UPDATE_SCHEME:
++ {
++ u32 upd_scheme = 0;
++ if (!get_user(upd_scheme, (__u32 __user *) arg))
++ ret = mxc_epdc_fb_set_upd_scheme(upd_scheme,
++ info);
++ break;
++ }
++ case MXCFB_SEND_UPDATE:
++ {
++ struct mxcfb_update_data upd_data;
++ if (!copy_from_user(&upd_data, argp,
++ sizeof(upd_data))) {
++ ret = mxc_epdc_fb_send_update(&upd_data, info);
++ if (ret == 0 && copy_to_user(argp, &upd_data,
++ sizeof(upd_data)))
++ ret = -EFAULT;
++ } else {
++ ret = -EFAULT;
++ }
++
++ break;
++ }
++ case MXCFB_WAIT_FOR_UPDATE_COMPLETE:
++ {
++ struct mxcfb_update_marker_data upd_marker_data;
++ if (!copy_from_user(&upd_marker_data, argp,
++ sizeof(upd_marker_data))) {
++ ret = mxc_epdc_fb_wait_update_complete(
++ &upd_marker_data, info);
++ if (copy_to_user(argp, &upd_marker_data,
++ sizeof(upd_marker_data)))
++ ret = -EFAULT;
++ } else {
++ ret = -EFAULT;
++ }
++
++ break;
++ }
++
++ case MXCFB_SET_PWRDOWN_DELAY:
++ {
++ int delay = 0;
++ if (!get_user(delay, (__u32 __user *) arg))
++ ret =
++ mxc_epdc_fb_set_pwrdown_delay(delay, info);
++ break;
++ }
++
++ case MXCFB_GET_PWRDOWN_DELAY:
++ {
++ int pwrdown_delay = mxc_epdc_get_pwrdown_delay(info);
++ if (put_user(pwrdown_delay,
++ (int __user *)argp))
++ ret = -EFAULT;
++ ret = 0;
++ break;
++ }
++
++ case MXCFB_GET_WORK_BUFFER:
++ {
++ /* copy the epdc working buffer to the user space */
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++ flush_cache_all();
++ outer_flush_all();
++ if (copy_to_user((void __user *)arg,
++ (const void *) fb_data->working_buffer_virt,
++ fb_data->working_buffer_size))
++ ret = -EFAULT;
++ else
++ ret = 0;
++ flush_cache_all();
++ outer_flush_all();
++ break;
++ }
++
++ default:
++ break;
++ }
++ return ret;
++}
++
++static void mxc_epdc_fb_update_pages(struct mxc_epdc_fb_data *fb_data,
++ u16 y1, u16 y2)
++{
++ struct mxcfb_update_data update;
++
++ /* Do partial screen update, Update full horizontal lines */
++ update.update_region.left = 0;
++ update.update_region.width = fb_data->epdc_fb_var.xres;
++ update.update_region.top = y1;
++ update.update_region.height = y2 - y1;
++ update.waveform_mode = WAVEFORM_MODE_AUTO;
++ update.update_mode = UPDATE_MODE_FULL;
++ update.update_marker = 0;
++ update.temp = TEMP_USE_AMBIENT;
++ update.flags = 0;
++
++ mxc_epdc_fb_send_update(&update, &fb_data->info);
++}
++
++/* this is called back from the deferred io workqueue */
++static void mxc_epdc_fb_deferred_io(struct fb_info *info,
++ struct list_head *pagelist)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ struct page *page;
++ unsigned long beg, end;
++ int y1, y2, miny, maxy;
++
++ if (fb_data->auto_mode != AUTO_UPDATE_MODE_AUTOMATIC_MODE)
++ return;
++
++ miny = INT_MAX;
++ maxy = 0;
++ list_for_each_entry(page, pagelist, lru) {
++ beg = page->index << PAGE_SHIFT;
++ end = beg + PAGE_SIZE - 1;
++ y1 = beg / info->fix.line_length;
++ y2 = end / info->fix.line_length;
++ if (y2 >= fb_data->epdc_fb_var.yres)
++ y2 = fb_data->epdc_fb_var.yres - 1;
++ if (miny > y1)
++ miny = y1;
++ if (maxy < y2)
++ maxy = y2;
++ }
++
++ mxc_epdc_fb_update_pages(fb_data, miny, maxy);
++}
++
++void mxc_epdc_fb_flush_updates(struct mxc_epdc_fb_data *fb_data)
++{
++ int ret;
++
++ if (fb_data->in_init)
++ return;
++
++ /* Grab queue lock to prevent any new updates from being submitted */
++ mutex_lock(&fb_data->queue_mutex);
++
++ /*
++ * 3 places to check for updates that are active or pending:
++ * 1) Updates in the pending list
++ * 2) Update buffers in use (e.g., PxP processing)
++ * 3) Active updates to panel - We can key off of EPDC
++ * power state to know if we have active updates.
++ */
++ if (!list_empty(&fb_data->upd_pending_list) ||
++ !is_free_list_full(fb_data) ||
++ (fb_data->updates_active == true)) {
++ /* Initialize event signalling updates are done */
++ init_completion(&fb_data->updates_done);
++ fb_data->waiting_for_idle = true;
++
++ mutex_unlock(&fb_data->queue_mutex);
++ /* Wait for any currently active updates to complete */
++ ret = wait_for_completion_timeout(&fb_data->updates_done,
++ msecs_to_jiffies(8000));
++ if (!ret)
++ dev_err(fb_data->dev,
++ "Flush updates timeout! ret = 0x%x\n", ret);
++
++ mutex_lock(&fb_data->queue_mutex);
++ fb_data->waiting_for_idle = false;
++ }
++
++ mutex_unlock(&fb_data->queue_mutex);
++}
++
++static int mxc_epdc_fb_blank(int blank, struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ int ret;
++
++ dev_dbg(fb_data->dev, "blank = %d\n", blank);
++
++ if (fb_data->blank == blank)
++ return 0;
++
++ fb_data->blank = blank;
++
++ switch (blank) {
++ case FB_BLANK_POWERDOWN:
++ mxc_epdc_fb_flush_updates(fb_data);
++ /* Wait for powerdown */
++ mutex_lock(&fb_data->power_mutex);
++ if ((fb_data->power_state == POWER_STATE_ON) &&
++ (fb_data->pwrdown_delay == FB_POWERDOWN_DISABLE)) {
++
++ /* Powerdown disabled, so we disable EPDC manually */
++ int count = 0;
++ int sleep_ms = 10;
++
++ mutex_unlock(&fb_data->power_mutex);
++
++ /* If any active updates, wait for them to complete */
++ while (fb_data->updates_active) {
++ /* Timeout after 1 sec */
++ if ((count * sleep_ms) > 1000)
++ break;
++ msleep(sleep_ms);
++ count++;
++ }
++
++ fb_data->powering_down = true;
++ epdc_powerdown(fb_data);
++ } else if (fb_data->power_state != POWER_STATE_OFF) {
++ fb_data->wait_for_powerdown = true;
++ init_completion(&fb_data->powerdown_compl);
++ mutex_unlock(&fb_data->power_mutex);
++ ret = wait_for_completion_timeout(&fb_data->powerdown_compl,
++ msecs_to_jiffies(5000));
++ if (!ret) {
++ dev_err(fb_data->dev,
++ "No powerdown received!\n");
++ return -ETIMEDOUT;
++ }
++ } else
++ mutex_unlock(&fb_data->power_mutex);
++ break;
++ case FB_BLANK_VSYNC_SUSPEND:
++ case FB_BLANK_HSYNC_SUSPEND:
++ case FB_BLANK_NORMAL:
++ mxc_epdc_fb_flush_updates(fb_data);
++ break;
++ }
++ return 0;
++}
++
++static int mxc_epdc_fb_pan_display(struct fb_var_screeninfo *var,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ u_int y_bottom;
++
++ dev_dbg(info->device, "%s: var->yoffset %d, info->var.yoffset %d\n",
++ __func__, var->yoffset, info->var.yoffset);
++ /* check if var is valid; also, xpan is not supported */
++ if (!var || (var->xoffset != info->var.xoffset) ||
++ (var->yoffset + var->yres > var->yres_virtual)) {
++ dev_dbg(info->device, "x panning not supported\n");
++ return -EINVAL;
++ }
++
++ if ((fb_data->epdc_fb_var.xoffset == var->xoffset) &&
++ (fb_data->epdc_fb_var.yoffset == var->yoffset))
++ return 0; /* No change, do nothing */
++
++ y_bottom = var->yoffset;
++
++ if (!(var->vmode & FB_VMODE_YWRAP))
++ y_bottom += var->yres;
++
++ if (y_bottom > info->var.yres_virtual)
++ return -EINVAL;
++
++ mutex_lock(&fb_data->queue_mutex);
++
++ fb_data->fb_offset = (var->yoffset * var->xres_virtual + var->xoffset)
++ * (var->bits_per_pixel) / 8;
++
++ fb_data->epdc_fb_var.xoffset = var->xoffset;
++ fb_data->epdc_fb_var.yoffset = var->yoffset;
++
++ if (var->vmode & FB_VMODE_YWRAP)
++ info->var.vmode |= FB_VMODE_YWRAP;
++ else
++ info->var.vmode &= ~FB_VMODE_YWRAP;
++
++ mutex_unlock(&fb_data->queue_mutex);
++
++ return 0;
++}
++
++static struct fb_ops mxc_epdc_fb_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = mxc_epdc_fb_check_var,
++ .fb_set_par = mxc_epdc_fb_set_par,
++ .fb_setcmap = mxc_epdc_fb_setcmap,
++ .fb_setcolreg = mxc_epdc_fb_setcolreg,
++ .fb_pan_display = mxc_epdc_fb_pan_display,
++ .fb_ioctl = mxc_epdc_fb_ioctl,
++ .fb_mmap = mxc_epdc_fb_mmap,
++ .fb_blank = mxc_epdc_fb_blank,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++};
++
++static struct fb_deferred_io mxc_epdc_fb_defio = {
++ .delay = HZ,
++ .deferred_io = mxc_epdc_fb_deferred_io,
++};
++
++static void epdc_done_work_func(struct work_struct *work)
++{
++ struct mxc_epdc_fb_data *fb_data =
++ container_of(work, struct mxc_epdc_fb_data,
++ epdc_done_work.work);
++ epdc_powerdown(fb_data);
++}
++
++static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data)
++{
++ int count = 0;
++ struct update_data_list *plist;
++
++ /* Count buffers in free buffer list */
++ list_for_each_entry(plist, &fb_data->upd_buf_free_list, list)
++ count++;
++
++ /* Check to see if all buffers are in this list */
++ if (count == fb_data->max_num_updates)
++ return true;
++ else
++ return false;
++}
++
++static irqreturn_t mxc_epdc_irq_handler(int irq, void *dev_id)
++{
++ struct mxc_epdc_fb_data *fb_data = dev_id;
++ u32 ints_fired, luts1_ints_fired, luts2_ints_fired;
++
++ /*
++ * If we just completed one-time panel init, bypass
++ * queue handling, clear interrupt and return
++ */
++ if (fb_data->in_init) {
++ if (epdc_is_working_buffer_complete()) {
++ epdc_working_buf_intr(false);
++ epdc_clear_working_buf_irq();
++ dev_dbg(fb_data->dev, "Cleared WB for init update\n");
++ }
++
++ if (epdc_is_lut_complete(fb_data->rev, 0)) {
++ epdc_lut_complete_intr(fb_data->rev, 0, false);
++ epdc_clear_lut_complete_irq(fb_data->rev, 0);
++ fb_data->in_init = false;
++ dev_dbg(fb_data->dev, "Cleared LUT complete for init update\n");
++ }
++
++ return IRQ_HANDLED;
++ }
++
++ ints_fired = __raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ);
++ if (fb_data->rev < 20) {
++ luts1_ints_fired = 0;
++ luts2_ints_fired = 0;
++ } else {
++ luts1_ints_fired = __raw_readl(EPDC_IRQ_MASK1) & __raw_readl(EPDC_IRQ1);
++ luts2_ints_fired = __raw_readl(EPDC_IRQ_MASK2) & __raw_readl(EPDC_IRQ2);
++ }
++
++ if (!(ints_fired || luts1_ints_fired || luts2_ints_fired))
++ return IRQ_HANDLED;
++
++ if (__raw_readl(EPDC_IRQ) & EPDC_IRQ_TCE_UNDERRUN_IRQ) {
++ dev_err(fb_data->dev,
++ "TCE underrun! Will continue to update panel\n");
++ /* Clear TCE underrun IRQ */
++ __raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_CLEAR);
++ }
++
++ /* Check if we are waiting on EOF to sync a new update submission */
++ if (epdc_signal_eof()) {
++ epdc_eof_intr(false);
++ epdc_clear_eof_irq();
++ complete(&fb_data->eof_event);
++ }
++
++ /*
++ * Workaround for EPDC v2.0/v2.1 errata: Must read collision status
++ * before clearing IRQ, or else collision status for bits 16:63
++ * will be automatically cleared. So we read it here, and there is
++ * no conflict with using it in epdc_intr_work_func since the
++ * working buffer processing flow is strictly sequential (i.e.,
++ * only one WB processing done at a time, so the data grabbed
++ * here should be up-to-date and accurate when the WB processing
++ * completes. Also, note that there is no impact to other versions
++ * of EPDC by reading LUT status here.
++ */
++ if (fb_data->cur_update != NULL)
++ fb_data->epdc_colliding_luts = epdc_get_colliding_luts(fb_data->rev);
++
++ /* Clear the interrupt mask for any interrupts signalled */
++ __raw_writel(ints_fired, EPDC_IRQ_MASK_CLEAR);
++ __raw_writel(luts1_ints_fired, EPDC_IRQ_MASK1_CLEAR);
++ __raw_writel(luts2_ints_fired, EPDC_IRQ_MASK2_CLEAR);
++
++ dev_dbg(fb_data->dev, "EPDC interrupts fired = 0x%x, "
++ "LUTS1 fired = 0x%x, LUTS2 fired = 0x%x\n",
++ ints_fired, luts1_ints_fired, luts2_ints_fired);
++
++ queue_work(fb_data->epdc_intr_workqueue,
++ &fb_data->epdc_intr_work);
++
++ return IRQ_HANDLED;
++}
++
++static void epdc_intr_work_func(struct work_struct *work)
++{
++ struct mxc_epdc_fb_data *fb_data =
++ container_of(work, struct mxc_epdc_fb_data, epdc_intr_work);
++ struct update_data_list *collision_update;
++ struct mxcfb_rect *next_upd_region;
++ struct update_marker_data *next_marker;
++ struct update_marker_data *temp;
++ int temp_index;
++ u64 temp_mask;
++ u32 lut;
++ bool ignore_collision = false;
++ int i;
++ bool wb_lut_done = false;
++ bool free_update = true;
++ int next_lut, epdc_next_lut_15;
++ u32 epdc_luts_active, epdc_wb_busy, epdc_luts_avail, epdc_lut_cancelled;
++ u32 epdc_collision;
++ u64 epdc_irq_stat;
++ bool epdc_waiting_on_wb;
++ u32 coll_coord, coll_size;
++ struct mxcfb_rect coll_region;
++
++ /* Protect access to buffer queues and to update HW */
++ mutex_lock(&fb_data->queue_mutex);
++
++ /* Capture EPDC status one time to limit exposure to race conditions */
++ epdc_luts_active = epdc_any_luts_active(fb_data->rev);
++ epdc_wb_busy = epdc_is_working_buffer_busy();
++ epdc_lut_cancelled = epdc_is_lut_cancelled();
++ epdc_luts_avail = epdc_any_luts_available();
++ epdc_collision = epdc_is_collision();
++ if (fb_data->rev < 20)
++ epdc_irq_stat = __raw_readl(EPDC_IRQ);
++ else
++ epdc_irq_stat = (u64)__raw_readl(EPDC_IRQ1) |
++ ((u64)__raw_readl(EPDC_IRQ2) << 32);
++ epdc_waiting_on_wb = (fb_data->cur_update != NULL) ? true : false;
++
++ /* Free any LUTs that have completed */
++ for (i = 0; i < fb_data->num_luts; i++) {
++ if ((epdc_irq_stat & (1ULL << i)) == 0)
++ continue;
++
++ dev_dbg(fb_data->dev, "LUT %d completed\n", i);
++
++ /* Disable IRQ for completed LUT */
++ epdc_lut_complete_intr(fb_data->rev, i, false);
++
++ /*
++ * Go through all updates in the collision list and
++ * unmask any updates that were colliding with
++ * the completed LUT.
++ */
++ list_for_each_entry(collision_update,
++ &fb_data->upd_buf_collision_list, list) {
++ collision_update->collision_mask =
++ collision_update->collision_mask & ~(1 << i);
++ }
++
++ epdc_clear_lut_complete_irq(fb_data->rev, i);
++
++ fb_data->luts_complete_wb |= 1ULL << i;
++
++ fb_data->lut_update_order[i] = 0;
++
++ /* Signal completion if submit workqueue needs a LUT */
++ if (fb_data->waiting_for_lut) {
++ complete(&fb_data->update_res_free);
++ fb_data->waiting_for_lut = false;
++ }
++
++ /* Signal completion if LUT15 free and is needed */
++ if (fb_data->waiting_for_lut15 && (i == 15)) {
++ complete(&fb_data->lut15_free);
++ fb_data->waiting_for_lut15 = false;
++ }
++
++ /* Detect race condition where WB and its LUT complete
++ (i.e. full update completes) in one swoop */
++ if (epdc_waiting_on_wb &&
++ (i == fb_data->cur_update->lut_num))
++ wb_lut_done = true;
++
++ /* Signal completion if anyone waiting on this LUT */
++ if (!wb_lut_done)
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->full_marker_list,
++ full_list) {
++ if (next_marker->lut_num != i)
++ continue;
++
++ /* Found marker to signal - remove from list */
++ list_del_init(&next_marker->full_list);
++
++ /* Signal completion of update */
++ dev_dbg(fb_data->dev, "Signaling marker %d\n",
++ next_marker->update_marker);
++ if (next_marker->waiting)
++ complete(&next_marker->update_completion);
++ else
++ kfree(next_marker);
++ }
++ }
++
++ /* Check to see if all updates have completed */
++ if (list_empty(&fb_data->upd_pending_list) &&
++ is_free_list_full(fb_data) &&
++ !epdc_waiting_on_wb &&
++ !epdc_luts_active) {
++
++ fb_data->updates_active = false;
++
++ if (fb_data->pwrdown_delay != FB_POWERDOWN_DISABLE) {
++ /*
++ * Set variable to prevent overlapping
++ * enable/disable requests
++ */
++ fb_data->powering_down = true;
++
++ /* Schedule task to disable EPDC HW until next update */
++ schedule_delayed_work(&fb_data->epdc_done_work,
++ msecs_to_jiffies(fb_data->pwrdown_delay));
++
++ /* Reset counter to reduce chance of overflow */
++ fb_data->order_cnt = 0;
++ }
++
++ if (fb_data->waiting_for_idle)
++ complete(&fb_data->updates_done);
++ }
++
++ /* Is Working Buffer busy? */
++ if (epdc_wb_busy) {
++ /* Can't submit another update until WB is done */
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ /*
++ * Were we waiting on working buffer?
++ * If so, update queues and check for collisions
++ */
++ if (epdc_waiting_on_wb) {
++ dev_dbg(fb_data->dev, "\nWorking buffer completed\n");
++
++ /* Signal completion if submit workqueue was waiting on WB */
++ if (fb_data->waiting_for_wb) {
++ complete(&fb_data->update_res_free);
++ fb_data->waiting_for_wb = false;
++ }
++
++ if (fb_data->cur_update->update_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION) {
++ /* This was a dry run to test for collision */
++
++ /* Signal marker */
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->full_marker_list,
++ full_list) {
++ if (next_marker->lut_num != DRY_RUN_NO_LUT)
++ continue;
++
++ if (epdc_collision)
++ next_marker->collision_test = true;
++ else
++ next_marker->collision_test = false;
++
++ dev_dbg(fb_data->dev,
++ "In IRQ, collision_test = %d\n",
++ next_marker->collision_test);
++
++ /* Found marker to signal - remove from list */
++ list_del_init(&next_marker->full_list);
++
++ /* Signal completion of update */
++ dev_dbg(fb_data->dev, "Signaling marker "
++ "for dry-run - %d\n",
++ next_marker->update_marker);
++ complete(&next_marker->update_completion);
++ }
++ } else if (epdc_lut_cancelled && !epdc_collision) {
++ /*
++ * Note: The update may be cancelled (void) if all
++ * pixels collided. In that case we handle it as a
++ * collision, not a cancel.
++ */
++
++ /* Clear LUT status (might be set if no AUTOWV used) */
++
++ /*
++ * Disable and clear IRQ for the LUT used.
++ * Even though LUT is cancelled in HW, the LUT
++ * complete bit may be set if AUTOWV not used.
++ */
++ epdc_lut_complete_intr(fb_data->rev,
++ fb_data->cur_update->lut_num, false);
++ epdc_clear_lut_complete_irq(fb_data->rev,
++ fb_data->cur_update->lut_num);
++
++ fb_data->lut_update_order[fb_data->cur_update->lut_num] = 0;
++
++ /* Signal completion if submit workqueue needs a LUT */
++ if (fb_data->waiting_for_lut) {
++ complete(&fb_data->update_res_free);
++ fb_data->waiting_for_lut = false;
++ }
++
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->cur_update->update_desc->upd_marker_list,
++ upd_list) {
++
++ /* Del from per-update & full list */
++ list_del_init(&next_marker->upd_list);
++ list_del_init(&next_marker->full_list);
++
++ /* Signal completion of update */
++ dev_dbg(fb_data->dev,
++ "Signaling marker (cancelled) %d\n",
++ next_marker->update_marker);
++ if (next_marker->waiting)
++ complete(&next_marker->update_completion);
++ else
++ kfree(next_marker);
++ }
++ } else if (epdc_collision) {
++ /* Real update (no dry-run), collision occurred */
++
++ /* Check list of colliding LUTs, and add to our collision mask */
++ fb_data->cur_update->collision_mask =
++ fb_data->epdc_colliding_luts;
++
++ /* Clear collisions that completed since WB began */
++ fb_data->cur_update->collision_mask &=
++ ~fb_data->luts_complete_wb;
++
++ dev_dbg(fb_data->dev, "Collision mask = 0x%llx\n",
++ fb_data->epdc_colliding_luts);
++
++ /* For EPDC 2.0 and later, minimum collision bounds
++ are provided by HW. Recompute new bounds here. */
++ if ((fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT)
++ && (fb_data->rev >= 20)) {
++ u32 xres, yres, rotate;
++ struct mxcfb_rect *cur_upd_rect =
++ &fb_data->cur_update->update_desc->upd_data.update_region;
++
++ /* Get collision region coords from EPDC */
++ coll_coord = __raw_readl(EPDC_UPD_COL_CORD);
++ coll_size = __raw_readl(EPDC_UPD_COL_SIZE);
++ coll_region.left =
++ (coll_coord & EPDC_UPD_COL_CORD_XCORD_MASK)
++ >> EPDC_UPD_COL_CORD_XCORD_OFFSET;
++ coll_region.top =
++ (coll_coord & EPDC_UPD_COL_CORD_YCORD_MASK)
++ >> EPDC_UPD_COL_CORD_YCORD_OFFSET;
++ coll_region.width =
++ (coll_size & EPDC_UPD_COL_SIZE_WIDTH_MASK)
++ >> EPDC_UPD_COL_SIZE_WIDTH_OFFSET;
++ coll_region.height =
++ (coll_size & EPDC_UPD_COL_SIZE_HEIGHT_MASK)
++ >> EPDC_UPD_COL_SIZE_HEIGHT_OFFSET;
++ dev_dbg(fb_data->dev, "Coll region: l = %d, "
++ "t = %d, w = %d, h = %d\n",
++ coll_region.left, coll_region.top,
++ coll_region.width, coll_region.height);
++
++ /* Convert coords back to orig orientation */
++ switch (fb_data->epdc_fb_var.rotate) {
++ case FB_ROTATE_CW:
++ xres = fb_data->epdc_fb_var.yres;
++ yres = fb_data->epdc_fb_var.xres;
++ rotate = FB_ROTATE_CCW;
++ break;
++ case FB_ROTATE_UD:
++ xres = fb_data->epdc_fb_var.xres;
++ yres = fb_data->epdc_fb_var.yres;
++ rotate = FB_ROTATE_UD;
++ break;
++ case FB_ROTATE_CCW:
++ xres = fb_data->epdc_fb_var.yres;
++ yres = fb_data->epdc_fb_var.xres;
++ rotate = FB_ROTATE_CW;
++ break;
++ default:
++ xres = fb_data->epdc_fb_var.xres;
++ yres = fb_data->epdc_fb_var.yres;
++ rotate = FB_ROTATE_UR;
++ break;
++ }
++ adjust_coordinates(xres, yres, rotate,
++ &coll_region, cur_upd_rect);
++
++ dev_dbg(fb_data->dev, "Adj coll region: l = %d, "
++ "t = %d, w = %d, h = %d\n",
++ cur_upd_rect->left, cur_upd_rect->top,
++ cur_upd_rect->width,
++ cur_upd_rect->height);
++ }
++
++ /*
++ * If we collide with newer updates, then
++ * we don't need to re-submit the update. The
++ * idea is that the newer updates should take
++ * precedence anyways, so we don't want to
++ * overwrite them.
++ */
++ for (temp_mask = fb_data->cur_update->collision_mask, lut = 0;
++ temp_mask != 0;
++ lut++, temp_mask = temp_mask >> 1) {
++ if (!(temp_mask & 0x1))
++ continue;
++
++ if (fb_data->lut_update_order[lut] >=
++ fb_data->cur_update->update_desc->update_order) {
++ dev_dbg(fb_data->dev,
++ "Ignoring collision with"
++ "newer update.\n");
++ ignore_collision = true;
++ break;
++ }
++ }
++
++ if (!ignore_collision) {
++ free_update = false;
++ /*
++ * If update has markers, clear the LUTs to
++ * avoid signalling that they have completed.
++ */
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->cur_update->update_desc->upd_marker_list,
++ upd_list)
++ next_marker->lut_num = INVALID_LUT;
++
++ /* Move to collision list */
++ list_add_tail(&fb_data->cur_update->list,
++ &fb_data->upd_buf_collision_list);
++ }
++ }
++
++ /* Do we need to free the current update descriptor? */
++ if (free_update) {
++ /* Handle condition where WB & LUT are both complete */
++ if (wb_lut_done)
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->cur_update->update_desc->upd_marker_list,
++ upd_list) {
++
++ /* Del from per-update & full list */
++ list_del_init(&next_marker->upd_list);
++ list_del_init(&next_marker->full_list);
++
++ /* Signal completion of update */
++ dev_dbg(fb_data->dev,
++ "Signaling marker (wb) %d\n",
++ next_marker->update_marker);
++ if (next_marker->waiting)
++ complete(&next_marker->update_completion);
++ else
++ kfree(next_marker);
++ }
++
++ /* Free marker list and update descriptor */
++ kfree(fb_data->cur_update->update_desc);
++
++ /* Add to free buffer list */
++ list_add_tail(&fb_data->cur_update->list,
++ &fb_data->upd_buf_free_list);
++
++ /* Check to see if all updates have completed */
++ if (list_empty(&fb_data->upd_pending_list) &&
++ is_free_list_full(fb_data) &&
++ !epdc_luts_active) {
++
++ fb_data->updates_active = false;
++
++ if (fb_data->pwrdown_delay !=
++ FB_POWERDOWN_DISABLE) {
++ /*
++ * Set variable to prevent overlapping
++ * enable/disable requests
++ */
++ fb_data->powering_down = true;
++
++ /* Schedule EPDC disable */
++ schedule_delayed_work(&fb_data->epdc_done_work,
++ msecs_to_jiffies(fb_data->pwrdown_delay));
++
++ /* Reset counter to reduce chance of overflow */
++ fb_data->order_cnt = 0;
++ }
++
++ if (fb_data->waiting_for_idle)
++ complete(&fb_data->updates_done);
++ }
++ }
++
++ /* Clear current update */
++ fb_data->cur_update = NULL;
++
++ /* Clear IRQ for working buffer */
++ epdc_working_buf_intr(false);
++ epdc_clear_working_buf_irq();
++ }
++
++ if (fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT) {
++ /* Queued update scheme processing */
++
++ /* Schedule task to submit collision and pending update */
++ if (!fb_data->powering_down)
++ queue_work(fb_data->epdc_submit_workqueue,
++ &fb_data->epdc_submit_work);
++
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++
++ return;
++ }
++
++ /* Snapshot update scheme processing */
++
++ /* Check to see if any LUTs are free */
++ if (!epdc_luts_avail) {
++ dev_dbg(fb_data->dev, "No luts available.\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ epdc_next_lut_15 = epdc_choose_next_lut(fb_data->rev, &next_lut);
++ /* Check to see if there is a valid LUT to use */
++ if (epdc_next_lut_15 && fb_data->tce_prevent && (fb_data->rev < 20)) {
++ dev_dbg(fb_data->dev, "Must wait for LUT15\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ /*
++ * Are any of our collision updates able to go now?
++ * Go through all updates in the collision list and check to see
++ * if the collision mask has been fully cleared
++ */
++ list_for_each_entry(collision_update,
++ &fb_data->upd_buf_collision_list, list) {
++
++ if (collision_update->collision_mask != 0)
++ continue;
++
++ dev_dbg(fb_data->dev, "A collision update is ready to go!\n");
++ /*
++ * We have a collision cleared, so select it
++ * and we will retry the update
++ */
++ fb_data->cur_update = collision_update;
++ list_del_init(&fb_data->cur_update->list);
++ break;
++ }
++
++ /*
++ * If we didn't find a collision update ready to go,
++ * we try to grab one from the update queue
++ */
++ if (fb_data->cur_update == NULL) {
++ /* Is update list empty? */
++ if (list_empty(&fb_data->upd_buf_queue)) {
++ dev_dbg(fb_data->dev, "No pending updates.\n");
++
++ /* No updates pending, so we are done */
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ } else {
++ dev_dbg(fb_data->dev, "Found a pending update!\n");
++
++ /* Process next item in update list */
++ fb_data->cur_update =
++ list_entry(fb_data->upd_buf_queue.next,
++ struct update_data_list, list);
++ list_del_init(&fb_data->cur_update->list);
++ }
++ }
++
++ /* Use LUT selected above */
++ fb_data->cur_update->lut_num = next_lut;
++
++ /* Associate LUT with update markers */
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->cur_update->update_desc->upd_marker_list, upd_list)
++ next_marker->lut_num = fb_data->cur_update->lut_num;
++
++ /* Mark LUT as containing new update */
++ fb_data->lut_update_order[fb_data->cur_update->lut_num] =
++ fb_data->cur_update->update_desc->update_order;
++
++ /* Enable Collision and WB complete IRQs */
++ epdc_working_buf_intr(true);
++ epdc_lut_complete_intr(fb_data->rev, fb_data->cur_update->lut_num, true);
++
++ /* Program EPDC update to process buffer */
++ next_upd_region =
++ &fb_data->cur_update->update_desc->upd_data.update_region;
++ if (fb_data->cur_update->update_desc->upd_data.temp
++ != TEMP_USE_AMBIENT) {
++ temp_index = mxc_epdc_fb_get_temp_index(fb_data,
++ fb_data->cur_update->update_desc->upd_data.temp);
++ epdc_set_temp(temp_index);
++ } else
++ epdc_set_temp(fb_data->temp_index);
++ epdc_set_update_addr(fb_data->cur_update->phys_addr +
++ fb_data->cur_update->update_desc->epdc_offs);
++ epdc_set_update_coord(next_upd_region->left, next_upd_region->top);
++ epdc_set_update_dimensions(next_upd_region->width,
++ next_upd_region->height);
++ if (fb_data->rev > 20)
++ epdc_set_update_stride(fb_data->cur_update->update_desc->epdc_stride);
++ if (fb_data->wv_modes_update &&
++ (fb_data->cur_update->update_desc->upd_data.waveform_mode
++ == WAVEFORM_MODE_AUTO)) {
++ epdc_set_update_waveform(&fb_data->wv_modes);
++ fb_data->wv_modes_update = false;
++ }
++
++ epdc_submit_update(fb_data->cur_update->lut_num,
++ fb_data->cur_update->update_desc->upd_data.waveform_mode,
++ fb_data->cur_update->update_desc->upd_data.update_mode,
++ false, false, 0);
++
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++
++ return;
++}
++
++static void draw_mode0(struct mxc_epdc_fb_data *fb_data)
++{
++ u32 *upd_buf_ptr;
++ int i;
++ struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var;
++ u32 xres, yres;
++
++ upd_buf_ptr = (u32 *)fb_data->info.screen_base;
++
++ epdc_working_buf_intr(true);
++ epdc_lut_complete_intr(fb_data->rev, 0, true);
++
++ /* Use unrotated (native) width/height */
++ if ((screeninfo->rotate == FB_ROTATE_CW) ||
++ (screeninfo->rotate == FB_ROTATE_CCW)) {
++ xres = screeninfo->yres;
++ yres = screeninfo->xres;
++ } else {
++ xres = screeninfo->xres;
++ yres = screeninfo->yres;
++ }
++
++ /* Program EPDC update to process buffer */
++ epdc_set_update_addr(fb_data->phys_start);
++ epdc_set_update_coord(0, 0);
++ epdc_set_update_dimensions(xres, yres);
++ if (fb_data->rev > 20)
++ epdc_set_update_stride(0);
++ epdc_submit_update(0, fb_data->wv_modes.mode_init, UPDATE_MODE_FULL,
++ false, true, 0xFF);
++
++ dev_dbg(fb_data->dev, "Mode0 update - Waiting for LUT to complete...\n");
++
++ /* Will timeout after ~4-5 seconds */
++
++ for (i = 0; i < 40; i++) {
++ if (!epdc_is_lut_active(0)) {
++ dev_dbg(fb_data->dev, "Mode0 init complete\n");
++ return;
++ }
++ msleep(100);
++ }
++
++ dev_err(fb_data->dev, "Mode0 init failed!\n");
++
++ return;
++}
++
++
++static void mxc_epdc_fb_fw_handler(const struct firmware *fw,
++ void *context)
++{
++ struct mxc_epdc_fb_data *fb_data = context;
++ int ret;
++ struct mxcfb_waveform_data_file *wv_file;
++ int wv_data_offs;
++ int i;
++ struct mxcfb_update_data update;
++ struct mxcfb_update_marker_data upd_marker_data;
++ struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var;
++ u32 xres, yres;
++ struct clk *epdc_parent;
++ unsigned long rounded_parent_rate, epdc_pix_rate,
++ rounded_pix_clk, target_pix_clk;
++
++ if (fw == NULL) {
++ /* If default FW file load failed, we give up */
++ if (fb_data->fw_default_load)
++ return;
++
++ /* Try to load default waveform */
++ dev_dbg(fb_data->dev,
++ "Can't find firmware. Trying fallback fw\n");
++ fb_data->fw_default_load = true;
++ ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
++ "imx/epdc.fw", fb_data->dev, GFP_KERNEL, fb_data,
++ mxc_epdc_fb_fw_handler);
++ if (ret)
++ dev_err(fb_data->dev,
++ "Failed request_firmware_nowait err %d\n", ret);
++
++ return;
++ }
++
++ wv_file = (struct mxcfb_waveform_data_file *)fw->data;
++
++ /* Get size and allocate temperature range table */
++ fb_data->trt_entries = wv_file->wdh.trc + 1;
++ fb_data->temp_range_bounds = kzalloc(fb_data->trt_entries, GFP_KERNEL);
++
++ for (i = 0; i < fb_data->trt_entries; i++)
++ dev_dbg(fb_data->dev, "trt entry #%d = 0x%x\n", i, *((u8 *)&wv_file->data + i));
++
++ /* Copy TRT data */
++ memcpy(fb_data->temp_range_bounds, &wv_file->data, fb_data->trt_entries);
++
++ /* Set default temperature index using TRT and room temp */
++ fb_data->temp_index = mxc_epdc_fb_get_temp_index(fb_data, DEFAULT_TEMP);
++
++ /* Get offset and size for waveform data */
++ wv_data_offs = sizeof(wv_file->wdh) + fb_data->trt_entries + 1;
++ fb_data->waveform_buffer_size = fw->size - wv_data_offs;
++
++ /* Allocate memory for waveform data */
++ fb_data->waveform_buffer_virt = dma_alloc_coherent(fb_data->dev,
++ fb_data->waveform_buffer_size,
++ &fb_data->waveform_buffer_phys,
++ GFP_DMA | GFP_KERNEL);
++ if (fb_data->waveform_buffer_virt == NULL) {
++ dev_err(fb_data->dev, "Can't allocate mem for waveform!\n");
++ return;
++ }
++
++ memcpy(fb_data->waveform_buffer_virt, (u8 *)(fw->data) + wv_data_offs,
++ fb_data->waveform_buffer_size);
++
++ release_firmware(fw);
++
++ /* Enable clocks to access EPDC regs */
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++
++ target_pix_clk = fb_data->cur_mode->vmode->pixclock;
++ /* Enable pix clk for EPDC */
++ clk_prepare_enable(fb_data->epdc_clk_pix);
++ rounded_pix_clk = clk_round_rate(fb_data->epdc_clk_pix, target_pix_clk);
++
++ if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/100) ||
++ (rounded_pix_clk <= target_pix_clk - target_pix_clk/100))) {
++ /* Can't get close enough without changing parent clk */
++ epdc_parent = clk_get_parent(fb_data->epdc_clk_pix);
++ rounded_parent_rate = clk_round_rate(epdc_parent, target_pix_clk);
++
++ epdc_pix_rate = target_pix_clk;
++ while (epdc_pix_rate < rounded_parent_rate)
++ epdc_pix_rate *= 2;
++ clk_set_rate(epdc_parent, epdc_pix_rate);
++
++ rounded_pix_clk = clk_round_rate(fb_data->epdc_clk_pix, target_pix_clk);
++ if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/100) ||
++ (rounded_pix_clk <= target_pix_clk - target_pix_clk/100)))
++ /* Still can't get a good clock, provide warning */
++ dev_err(fb_data->dev, "Unable to get an accurate EPDC pix clk"
++ "desired = %lu, actual = %lu\n", target_pix_clk,
++ rounded_pix_clk);
++ }
++
++ clk_set_rate(fb_data->epdc_clk_pix, rounded_pix_clk);
++
++ epdc_init_sequence(fb_data);
++
++ /* Disable clocks */
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++ clk_disable_unprepare(fb_data->epdc_clk_pix);
++
++ fb_data->hw_ready = true;
++ fb_data->hw_initializing = false;
++
++ /* Use unrotated (native) width/height */
++ if ((screeninfo->rotate == FB_ROTATE_CW) ||
++ (screeninfo->rotate == FB_ROTATE_CCW)) {
++ xres = screeninfo->yres;
++ yres = screeninfo->xres;
++ } else {
++ xres = screeninfo->xres;
++ yres = screeninfo->yres;
++ }
++
++ update.update_region.left = 0;
++ update.update_region.width = xres;
++ update.update_region.top = 0;
++ update.update_region.height = yres;
++ update.update_mode = UPDATE_MODE_FULL;
++ update.waveform_mode = WAVEFORM_MODE_AUTO;
++ update.update_marker = INIT_UPDATE_MARKER;
++ update.temp = TEMP_USE_AMBIENT;
++ update.flags = 0;
++
++ upd_marker_data.update_marker = update.update_marker;
++
++ mxc_epdc_fb_send_update(&update, &fb_data->info);
++
++ /* Block on initial update */
++ ret = mxc_epdc_fb_wait_update_complete(&upd_marker_data,
++ &fb_data->info);
++ if (ret < 0)
++ dev_err(fb_data->dev,
++ "Wait for initial update complete failed."
++ " Error = 0x%x", ret);
++}
++
++static int mxc_epdc_fb_init_hw(struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ int ret;
++
++ /*
++ * Create fw search string based on ID string in selected videomode.
++ * Format is "imx/epdc_[panel string].fw"
++ */
++ if (fb_data->cur_mode) {
++ strcat(fb_data->fw_str, "imx/epdc_");
++ strcat(fb_data->fw_str, fb_data->cur_mode->vmode->name);
++ strcat(fb_data->fw_str, ".fw");
++ }
++
++ fb_data->fw_default_load = false;
++
++ ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
++ fb_data->fw_str, fb_data->dev, GFP_KERNEL,
++ fb_data, mxc_epdc_fb_fw_handler);
++ if (ret)
++ dev_dbg(fb_data->dev,
++ "Failed request_firmware_nowait err %d\n", ret);
++
++ return ret;
++}
++
++static ssize_t store_update(struct device *device,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct mxcfb_update_data update;
++ struct fb_info *info = dev_get_drvdata(device);
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++
++ if (strncmp(buf, "direct", 6) == 0)
++ update.waveform_mode = fb_data->wv_modes.mode_du;
++ else if (strncmp(buf, "gc16", 4) == 0)
++ update.waveform_mode = fb_data->wv_modes.mode_gc16;
++ else if (strncmp(buf, "gc4", 3) == 0)
++ update.waveform_mode = fb_data->wv_modes.mode_gc4;
++
++ /* Now, request full screen update */
++ update.update_region.left = 0;
++ update.update_region.width = fb_data->epdc_fb_var.xres;
++ update.update_region.top = 0;
++ update.update_region.height = fb_data->epdc_fb_var.yres;
++ update.update_mode = UPDATE_MODE_FULL;
++ update.temp = TEMP_USE_AMBIENT;
++ update.update_marker = 0;
++ update.flags = 0;
++
++ mxc_epdc_fb_send_update(&update, info);
++
++ return count;
++}
++
++static struct device_attribute fb_attrs[] = {
++ __ATTR(update, S_IRUGO|S_IWUSR, NULL, store_update),
++};
++
++static const struct of_device_id imx_epdc_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-epdc", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_epdc_dt_ids);
++
++int mxc_epdc_fb_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++ struct pinctrl *pinctrl;
++ struct mxc_epdc_fb_data *fb_data;
++ struct resource *res;
++ struct fb_info *info;
++ char *options, *opt;
++ char *panel_str = NULL;
++ char name[] = "mxcepdcfb";
++ struct fb_videomode *vmode;
++ int xres_virt, yres_virt, buf_size;
++ int xres_virt_rot, yres_virt_rot, pix_size_rot;
++ struct fb_var_screeninfo *var_info;
++ struct fb_fix_screeninfo *fix_info;
++ struct pxp_config_data *pxp_conf;
++ struct pxp_proc_data *proc_data;
++ struct scatterlist *sg;
++ struct update_data_list *upd_list;
++ struct update_data_list *plist, *temp_list;
++ int i;
++ unsigned long x_mem_size = 0;
++ u32 val;
++ int irq;
++
++ fb_data = (struct mxc_epdc_fb_data *)framebuffer_alloc(
++ sizeof(struct mxc_epdc_fb_data), &pdev->dev);
++ if (fb_data == NULL) {
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* Get platform data and check validity */
++ fb_data->pdata = &epdc_data;
++ if ((fb_data->pdata == NULL) || (fb_data->pdata->num_modes < 1)
++ || (fb_data->pdata->epdc_mode == NULL)
++ || (fb_data->pdata->epdc_mode->vmode == NULL)) {
++ ret = -EINVAL;
++ goto out_fbdata;
++ }
++
++ if (fb_get_options(name, &options)) {
++ ret = -ENODEV;
++ goto out_fbdata;
++ }
++
++ fb_data->tce_prevent = 0;
++
++ if (options)
++ while ((opt = strsep(&options, ",")) != NULL) {
++ if (!*opt)
++ continue;
++
++ if (!strncmp(opt, "bpp=", 4))
++ fb_data->default_bpp =
++ simple_strtoul(opt + 4, NULL, 0);
++ else if (!strncmp(opt, "x_mem=", 6))
++ x_mem_size = memparse(opt + 6, NULL);
++ else if (!strncmp(opt, "tce_prevent", 11))
++ fb_data->tce_prevent = 1;
++ else
++ panel_str = opt;
++ }
++
++ fb_data->dev = &pdev->dev;
++
++ if (!fb_data->default_bpp)
++ fb_data->default_bpp = 16;
++
++ /* Set default (first defined mode) before searching for a match */
++ fb_data->cur_mode = &fb_data->pdata->epdc_mode[0];
++
++ if (panel_str)
++ for (i = 0; i < fb_data->pdata->num_modes; i++)
++ if (!strcmp(fb_data->pdata->epdc_mode[i].vmode->name,
++ panel_str)) {
++ fb_data->cur_mode =
++ &fb_data->pdata->epdc_mode[i];
++ break;
++ }
++
++ vmode = fb_data->cur_mode->vmode;
++
++ platform_set_drvdata(pdev, fb_data);
++ info = &fb_data->info;
++
++ /* Allocate color map for the FB */
++ ret = fb_alloc_cmap(&info->cmap, 256, 0);
++ if (ret)
++ goto out_fbdata;
++
++ dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n",
++ vmode->xres, vmode->yres, fb_data->default_bpp);
++
++ /*
++ * GPU alignment restrictions dictate framebuffer parameters:
++ * - 32-byte alignment for buffer width
++ * - 128-byte alignment for buffer height
++ * => 4K buffer alignment for buffer start
++ */
++ xres_virt = ALIGN(vmode->xres, 32);
++ yres_virt = ALIGN(vmode->yres, 128);
++ fb_data->max_pix_size = PAGE_ALIGN(xres_virt * yres_virt);
++
++ /*
++ * Have to check to see if aligned buffer size when rotated
++ * is bigger than when not rotated, and use the max
++ */
++ xres_virt_rot = ALIGN(vmode->yres, 32);
++ yres_virt_rot = ALIGN(vmode->xres, 128);
++ pix_size_rot = PAGE_ALIGN(xres_virt_rot * yres_virt_rot);
++ fb_data->max_pix_size = (fb_data->max_pix_size > pix_size_rot) ?
++ fb_data->max_pix_size : pix_size_rot;
++
++ buf_size = fb_data->max_pix_size * fb_data->default_bpp/8;
++
++ /* Compute the number of screens needed based on X memory requested */
++ if (x_mem_size > 0) {
++ fb_data->num_screens = DIV_ROUND_UP(x_mem_size, buf_size);
++ if (fb_data->num_screens < NUM_SCREENS_MIN)
++ fb_data->num_screens = NUM_SCREENS_MIN;
++ else if (buf_size * fb_data->num_screens > SZ_16M)
++ fb_data->num_screens = SZ_16M / buf_size;
++ } else
++ fb_data->num_screens = NUM_SCREENS_MIN;
++
++ fb_data->map_size = buf_size * fb_data->num_screens;
++ dev_dbg(&pdev->dev, "memory to allocate: %d\n", fb_data->map_size);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res == NULL) {
++ ret = -ENODEV;
++ goto out_cmap;
++ }
++
++ epdc_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (epdc_base == NULL) {
++ ret = -ENOMEM;
++ goto out_cmap;
++ }
++
++ /* Allocate FB memory */
++ info->screen_base = dma_alloc_writecombine(&pdev->dev,
++ fb_data->map_size,
++ &fb_data->phys_start,
++ GFP_DMA | GFP_KERNEL);
++
++ if (info->screen_base == NULL) {
++ ret = -ENOMEM;
++ goto out_cmap;
++ }
++ dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", info->screen_base,
++ fb_data->phys_start);
++
++ var_info = &info->var;
++ var_info->activate = FB_ACTIVATE_TEST;
++ var_info->bits_per_pixel = fb_data->default_bpp;
++ var_info->xres = vmode->xres;
++ var_info->yres = vmode->yres;
++ var_info->xres_virtual = xres_virt;
++ /* Additional screens allow for panning and buffer flipping */
++ var_info->yres_virtual = yres_virt * fb_data->num_screens;
++
++ var_info->pixclock = vmode->pixclock;
++ var_info->left_margin = vmode->left_margin;
++ var_info->right_margin = vmode->right_margin;
++ var_info->upper_margin = vmode->upper_margin;
++ var_info->lower_margin = vmode->lower_margin;
++ var_info->hsync_len = vmode->hsync_len;
++ var_info->vsync_len = vmode->vsync_len;
++ var_info->vmode = FB_VMODE_NONINTERLACED;
++
++ switch (fb_data->default_bpp) {
++ case 32:
++ case 24:
++ var_info->red.offset = 16;
++ var_info->red.length = 8;
++ var_info->green.offset = 8;
++ var_info->green.length = 8;
++ var_info->blue.offset = 0;
++ var_info->blue.length = 8;
++ break;
++
++ case 16:
++ var_info->red.offset = 11;
++ var_info->red.length = 5;
++ var_info->green.offset = 5;
++ var_info->green.length = 6;
++ var_info->blue.offset = 0;
++ var_info->blue.length = 5;
++ break;
++
++ case 8:
++ /*
++ * For 8-bit grayscale, R, G, and B offset are equal.
++ *
++ */
++ var_info->grayscale = GRAYSCALE_8BIT;
++
++ var_info->red.length = 8;
++ var_info->red.offset = 0;
++ var_info->red.msb_right = 0;
++ var_info->green.length = 8;
++ var_info->green.offset = 0;
++ var_info->green.msb_right = 0;
++ var_info->blue.length = 8;
++ var_info->blue.offset = 0;
++ var_info->blue.msb_right = 0;
++ break;
++
++ default:
++ dev_err(&pdev->dev, "unsupported bitwidth %d\n",
++ fb_data->default_bpp);
++ ret = -EINVAL;
++ goto out_dma_fb;
++ }
++
++ fix_info = &info->fix;
++
++ strcpy(fix_info->id, "mxc_epdc_fb");
++ fix_info->type = FB_TYPE_PACKED_PIXELS;
++ fix_info->visual = FB_VISUAL_TRUECOLOR;
++ fix_info->xpanstep = 0;
++ fix_info->ypanstep = 0;
++ fix_info->ywrapstep = 0;
++ fix_info->accel = FB_ACCEL_NONE;
++ fix_info->smem_start = fb_data->phys_start;
++ fix_info->smem_len = fb_data->map_size;
++ fix_info->ypanstep = 0;
++
++ fb_data->native_width = vmode->xres;
++ fb_data->native_height = vmode->yres;
++
++ info->fbops = &mxc_epdc_fb_ops;
++ info->var.activate = FB_ACTIVATE_NOW;
++ info->pseudo_palette = fb_data->pseudo_palette;
++ info->screen_size = info->fix.smem_len;
++ info->flags = FBINFO_FLAG_DEFAULT;
++
++ mxc_epdc_fb_set_fix(info);
++
++ fb_data->auto_mode = AUTO_UPDATE_MODE_REGION_MODE;
++ fb_data->upd_scheme = UPDATE_SCHEME_QUEUE_AND_MERGE;
++
++ /* Initialize our internal copy of the screeninfo */
++ fb_data->epdc_fb_var = *var_info;
++ fb_data->fb_offset = 0;
++ fb_data->eof_sync_period = 0;
++
++ fb_data->epdc_clk_axi = clk_get(fb_data->dev, "epdc_axi");
++ if (IS_ERR(fb_data->epdc_clk_axi)) {
++ dev_err(&pdev->dev, "Unable to get EPDC AXI clk."
++ "err = %d\n", (int)fb_data->epdc_clk_axi);
++ ret = -ENODEV;
++ goto out_dma_fb;
++ }
++ fb_data->epdc_clk_pix = clk_get(fb_data->dev, "epdc_pix");
++ if (IS_ERR(fb_data->epdc_clk_pix)) {
++ dev_err(&pdev->dev, "Unable to get EPDC pix clk."
++ "err = %d\n", (int)fb_data->epdc_clk_pix);
++ ret = -ENODEV;
++ goto out_dma_fb;
++ }
++
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++ val = __raw_readl(EPDC_VERSION);
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++ fb_data->rev = ((val & EPDC_VERSION_MAJOR_MASK) >>
++ EPDC_VERSION_MAJOR_OFFSET) * 10
++ + ((val & EPDC_VERSION_MINOR_MASK) >>
++ EPDC_VERSION_MINOR_OFFSET);
++ dev_dbg(&pdev->dev, "EPDC version = %d\n", fb_data->rev);
++
++ if (fb_data->rev < 20) {
++ fb_data->num_luts = EPDC_V1_NUM_LUTS;
++ fb_data->max_num_updates = EPDC_V1_MAX_NUM_UPDATES;
++ } else {
++ fb_data->num_luts = EPDC_V2_NUM_LUTS;
++ fb_data->max_num_updates = EPDC_V2_MAX_NUM_UPDATES;
++ if (vmode->xres > EPDC_V2_MAX_UPDATE_WIDTH)
++ fb_data->restrict_width = true;
++ }
++ fb_data->max_num_buffers = EPDC_MAX_NUM_BUFFERS;
++
++ /*
++ * Initialize lists for pending updates,
++ * active update requests, update collisions,
++ * and freely available updates.
++ */
++ INIT_LIST_HEAD(&fb_data->upd_pending_list);
++ INIT_LIST_HEAD(&fb_data->upd_buf_queue);
++ INIT_LIST_HEAD(&fb_data->upd_buf_free_list);
++ INIT_LIST_HEAD(&fb_data->upd_buf_collision_list);
++
++ /* Allocate update buffers and add them to the list */
++ for (i = 0; i < fb_data->max_num_updates; i++) {
++ upd_list = kzalloc(sizeof(*upd_list), GFP_KERNEL);
++ if (upd_list == NULL) {
++ ret = -ENOMEM;
++ goto out_upd_lists;
++ }
++
++ /* Add newly allocated buffer to free list */
++ list_add(&upd_list->list, &fb_data->upd_buf_free_list);
++ }
++
++ fb_data->virt_addr_updbuf =
++ kzalloc(sizeof(void *) * fb_data->max_num_buffers, GFP_KERNEL);
++ fb_data->phys_addr_updbuf =
++ kzalloc(sizeof(dma_addr_t) * fb_data->max_num_buffers,
++ GFP_KERNEL);
++ for (i = 0; i < fb_data->max_num_buffers; i++) {
++ /*
++ * Allocate memory for PxP output buffer.
++ * Each update buffer is 1 byte per pixel, and can
++ * be as big as the full-screen frame buffer
++ */
++ fb_data->virt_addr_updbuf[i] =
++ kmalloc(fb_data->max_pix_size, GFP_KERNEL);
++ fb_data->phys_addr_updbuf[i] =
++ virt_to_phys(fb_data->virt_addr_updbuf[i]);
++ if (fb_data->virt_addr_updbuf[i] == NULL) {
++ ret = -ENOMEM;
++ goto out_upd_buffers;
++ }
++
++ dev_dbg(fb_data->info.device, "allocated %d bytes @ 0x%08X\n",
++ fb_data->max_pix_size, fb_data->phys_addr_updbuf[i]);
++ }
++
++ /* Counter indicating which update buffer should be used next. */
++ fb_data->upd_buffer_num = 0;
++
++ /*
++ * Allocate memory for PxP SW workaround buffer
++ * These buffers are used to hold copy of the update region,
++ * before sending it to PxP for processing.
++ */
++ fb_data->virt_addr_copybuf =
++ dma_alloc_coherent(fb_data->info.device, fb_data->max_pix_size*2,
++ &fb_data->phys_addr_copybuf,
++ GFP_DMA | GFP_KERNEL);
++ if (fb_data->virt_addr_copybuf == NULL) {
++ ret = -ENOMEM;
++ goto out_upd_buffers;
++ }
++
++ fb_data->working_buffer_size = vmode->yres * vmode->xres * 2;
++ /* Allocate memory for EPDC working buffer */
++ fb_data->working_buffer_virt =
++ dma_alloc_coherent(&pdev->dev, fb_data->working_buffer_size,
++ &fb_data->working_buffer_phys,
++ GFP_DMA | GFP_KERNEL);
++ if (fb_data->working_buffer_virt == NULL) {
++ dev_err(&pdev->dev, "Can't allocate mem for working buf!\n");
++ ret = -ENOMEM;
++ goto out_copybuffer;
++ }
++
++ /* Initialize EPDC pins */
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "can't get/select pinctrl\n");
++ ret = PTR_ERR(pinctrl);
++ goto out_copybuffer;
++ }
++
++ fb_data->in_init = false;
++
++ fb_data->hw_ready = false;
++ fb_data->hw_initializing = false;
++
++ /*
++ * Set default waveform mode values.
++ * Should be overwritten via ioctl.
++ */
++ fb_data->wv_modes.mode_init = 0;
++ fb_data->wv_modes.mode_du = 1;
++ fb_data->wv_modes.mode_gc4 = 3;
++ fb_data->wv_modes.mode_gc8 = 2;
++ fb_data->wv_modes.mode_gc16 = 2;
++ fb_data->wv_modes.mode_gc32 = 2;
++ fb_data->wv_modes_update = true;
++
++ /* Initialize marker list */
++ INIT_LIST_HEAD(&fb_data->full_marker_list);
++
++ /* Initialize all LUTs to inactive */
++ fb_data->lut_update_order =
++ kzalloc(fb_data->num_luts * sizeof(u32 *), GFP_KERNEL);
++ for (i = 0; i < fb_data->num_luts; i++)
++ fb_data->lut_update_order[i] = 0;
++
++ INIT_DELAYED_WORK(&fb_data->epdc_done_work, epdc_done_work_func);
++ fb_data->epdc_submit_workqueue = alloc_workqueue("EPDC Submit",
++ WQ_MEM_RECLAIM | WQ_HIGHPRI |
++ WQ_CPU_INTENSIVE | WQ_UNBOUND, 1);
++ INIT_WORK(&fb_data->epdc_submit_work, epdc_submit_work_func);
++ fb_data->epdc_intr_workqueue = alloc_workqueue("EPDC Interrupt",
++ WQ_MEM_RECLAIM | WQ_HIGHPRI |
++ WQ_CPU_INTENSIVE | WQ_UNBOUND, 1);
++ INIT_WORK(&fb_data->epdc_intr_work, epdc_intr_work_func);
++
++ /* Retrieve EPDC IRQ num */
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(&pdev->dev, "cannot get IRQ resource\n");
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++ fb_data->epdc_irq = irq;
++
++ /* Register IRQ handler */
++ ret = devm_request_irq(&pdev->dev, fb_data->epdc_irq,
++ mxc_epdc_irq_handler, 0, "epdc", fb_data);
++ if (ret) {
++ dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
++ fb_data->epdc_irq, ret);
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++
++ info->fbdefio = &mxc_epdc_fb_defio;
++#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
++ fb_deferred_io_init(info);
++#endif
++
++ /* get pmic regulators */
++ fb_data->display_regulator = devm_regulator_get(&pdev->dev, "DISPLAY");
++ if (IS_ERR(fb_data->display_regulator)) {
++ dev_err(&pdev->dev, "Unable to get display PMIC regulator."
++ "err = 0x%x\n", (int)fb_data->display_regulator);
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++ fb_data->vcom_regulator = devm_regulator_get(&pdev->dev, "VCOM");
++ if (IS_ERR(fb_data->vcom_regulator)) {
++ dev_err(&pdev->dev, "Unable to get VCOM regulator."
++ "err = 0x%x\n", (int)fb_data->vcom_regulator);
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++ fb_data->v3p3_regulator = devm_regulator_get(&pdev->dev, "V3P3");
++ if (IS_ERR(fb_data->v3p3_regulator)) {
++ dev_err(&pdev->dev, "Unable to get V3P3 regulator."
++ "err = 0x%x\n", (int)fb_data->vcom_regulator);
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++
++ if (device_create_file(info->dev, &fb_attrs[0]))
++ dev_err(&pdev->dev, "Unable to create file from fb_attrs\n");
++
++ fb_data->cur_update = NULL;
++
++ mutex_init(&fb_data->queue_mutex);
++ mutex_init(&fb_data->pxp_mutex);
++ mutex_init(&fb_data->power_mutex);
++
++ /*
++ * Fill out PxP config data structure based on FB info and
++ * processing tasks required
++ */
++ pxp_conf = &fb_data->pxp_conf;
++ proc_data = &pxp_conf->proc_data;
++
++ /* Initialize non-channel-specific PxP parameters */
++ proc_data->drect.left = proc_data->srect.left = 0;
++ proc_data->drect.top = proc_data->srect.top = 0;
++ proc_data->drect.width = proc_data->srect.width = fb_data->info.var.xres;
++ proc_data->drect.height = proc_data->srect.height = fb_data->info.var.yres;
++ proc_data->scaling = 0;
++ proc_data->hflip = 0;
++ proc_data->vflip = 0;
++ proc_data->rotate = 0;
++ proc_data->bgcolor = 0;
++ proc_data->overlay_state = 0;
++ proc_data->lut_transform = PXP_LUT_NONE;
++ proc_data->lut_map = NULL;
++
++ /*
++ * We initially configure PxP for RGB->YUV conversion,
++ * and only write out Y component of the result.
++ */
++
++ /*
++ * Initialize S0 channel parameters
++ * Parameters should match FB format/width/height
++ */
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++ pxp_conf->s0_param.width = fb_data->info.var.xres_virtual;
++ pxp_conf->s0_param.height = fb_data->info.var.yres;
++ pxp_conf->s0_param.color_key = -1;
++ pxp_conf->s0_param.color_key_enable = false;
++
++ /*
++ * Initialize OL0 channel parameters
++ * No overlay will be used for PxP operation
++ */
++ for (i = 0; i < 8; i++) {
++ pxp_conf->ol_param[i].combine_enable = false;
++ pxp_conf->ol_param[i].width = 0;
++ pxp_conf->ol_param[i].height = 0;
++ pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565;
++ pxp_conf->ol_param[i].color_key_enable = false;
++ pxp_conf->ol_param[i].color_key = -1;
++ pxp_conf->ol_param[i].global_alpha_enable = false;
++ pxp_conf->ol_param[i].global_alpha = 0;
++ pxp_conf->ol_param[i].local_alpha_enable = false;
++ }
++
++ /*
++ * Initialize Output channel parameters
++ * Output is Y-only greyscale
++ * Output width/height will vary based on update region size
++ */
++ pxp_conf->out_param.width = fb_data->info.var.xres;
++ pxp_conf->out_param.height = fb_data->info.var.yres;
++ pxp_conf->out_param.stride = pxp_conf->out_param.width;
++ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
++
++ /* Initialize color map for conversion of 8-bit gray pixels */
++ fb_data->pxp_conf.proc_data.lut_map = kmalloc(256, GFP_KERNEL);
++ if (fb_data->pxp_conf.proc_data.lut_map == NULL) {
++ dev_err(&pdev->dev, "Can't allocate mem for lut map!\n");
++ ret = -ENOMEM;
++ goto out_dma_work_buf;
++ }
++ for (i = 0; i < 256; i++)
++ fb_data->pxp_conf.proc_data.lut_map[i] = i;
++
++ fb_data->pxp_conf.proc_data.lut_map_updated = true;
++
++ /*
++ * Ensure this is set to NULL here...we will initialize pxp_chan
++ * later in our thread.
++ */
++ fb_data->pxp_chan = NULL;
++
++ /* Initialize Scatter-gather list containing 2 buffer addresses. */
++ sg = fb_data->sg;
++ sg_init_table(sg, 2);
++
++ /*
++ * For use in PxP transfers:
++ * sg[0] holds the FB buffer pointer
++ * sg[1] holds the Output buffer pointer (configured before TX request)
++ */
++ sg_dma_address(&sg[0]) = info->fix.smem_start;
++ sg_set_page(&sg[0], virt_to_page(info->screen_base),
++ info->fix.smem_len, offset_in_page(info->screen_base));
++
++ fb_data->order_cnt = 0;
++ fb_data->waiting_for_wb = false;
++ fb_data->waiting_for_lut = false;
++ fb_data->waiting_for_lut15 = false;
++ fb_data->waiting_for_idle = false;
++ fb_data->blank = FB_BLANK_UNBLANK;
++ fb_data->power_state = POWER_STATE_OFF;
++ fb_data->powering_down = false;
++ fb_data->wait_for_powerdown = false;
++ fb_data->updates_active = false;
++ fb_data->pwrdown_delay = 0;
++
++ /* Register FB */
++ ret = register_framebuffer(info);
++ if (ret) {
++ dev_err(&pdev->dev,
++ "register_framebuffer failed with error %d\n", ret);
++ goto out_lutmap;
++ }
++
++ g_fb_data = fb_data;
++
++ pm_runtime_enable(fb_data->dev);
++
++#ifdef DEFAULT_PANEL_HW_INIT
++ ret = mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to initialize HW!\n");
++ }
++#endif
++
++ goto out;
++
++out_lutmap:
++ kfree(fb_data->pxp_conf.proc_data.lut_map);
++out_dma_work_buf:
++ dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
++ fb_data->working_buffer_virt, fb_data->working_buffer_phys);
++out_copybuffer:
++ dma_free_writecombine(&pdev->dev, fb_data->max_pix_size*2,
++ fb_data->virt_addr_copybuf,
++ fb_data->phys_addr_copybuf);
++out_upd_buffers:
++ for (i = 0; i < fb_data->max_num_buffers; i++)
++ if (fb_data->virt_addr_updbuf[i] != NULL)
++ kfree(fb_data->virt_addr_updbuf[i]);
++ if (fb_data->virt_addr_updbuf != NULL)
++ kfree(fb_data->virt_addr_updbuf);
++ if (fb_data->phys_addr_updbuf != NULL)
++ kfree(fb_data->phys_addr_updbuf);
++out_upd_lists:
++ list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list,
++ list) {
++ list_del(&plist->list);
++ kfree(plist);
++ }
++out_dma_fb:
++ dma_free_writecombine(&pdev->dev, fb_data->map_size, info->screen_base,
++ fb_data->phys_start);
++
++out_cmap:
++ fb_dealloc_cmap(&info->cmap);
++out_fbdata:
++ kfree(fb_data);
++out:
++ return ret;
++}
++
++static int mxc_epdc_fb_remove(struct platform_device *pdev)
++{
++ struct update_data_list *plist, *temp_list;
++ struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev);
++ int i;
++
++ mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &fb_data->info);
++
++ flush_workqueue(fb_data->epdc_submit_workqueue);
++ destroy_workqueue(fb_data->epdc_submit_workqueue);
++
++ unregister_framebuffer(&fb_data->info);
++
++ for (i = 0; i < fb_data->max_num_buffers; i++)
++ if (fb_data->virt_addr_updbuf[i] != NULL)
++ kfree(fb_data->virt_addr_updbuf[i]);
++ if (fb_data->virt_addr_updbuf != NULL)
++ kfree(fb_data->virt_addr_updbuf);
++ if (fb_data->phys_addr_updbuf != NULL)
++ kfree(fb_data->phys_addr_updbuf);
++
++ dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
++ fb_data->working_buffer_virt,
++ fb_data->working_buffer_phys);
++ if (fb_data->waveform_buffer_virt != NULL)
++ dma_free_writecombine(&pdev->dev, fb_data->waveform_buffer_size,
++ fb_data->waveform_buffer_virt,
++ fb_data->waveform_buffer_phys);
++ if (fb_data->virt_addr_copybuf != NULL)
++ dma_free_writecombine(&pdev->dev, fb_data->max_pix_size*2,
++ fb_data->virt_addr_copybuf,
++ fb_data->phys_addr_copybuf);
++ list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list,
++ list) {
++ list_del(&plist->list);
++ kfree(plist);
++ }
++#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
++ fb_deferred_io_cleanup(&fb_data->info);
++#endif
++
++ dma_free_writecombine(&pdev->dev, fb_data->map_size, fb_data->info.screen_base,
++ fb_data->phys_start);
++
++ /* Release PxP-related resources */
++ if (fb_data->pxp_chan != NULL)
++ dma_release_channel(&fb_data->pxp_chan->dma_chan);
++
++ fb_dealloc_cmap(&fb_data->info.cmap);
++
++ framebuffer_release(&fb_data->info);
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int mxc_epdc_fb_suspend(struct device *dev)
++{
++ struct mxc_epdc_fb_data *data = dev_get_drvdata(dev);
++ int ret;
++
++ data->pwrdown_delay = FB_POWERDOWN_DISABLE;
++ ret = mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &data->info);
++ if (ret)
++ goto out;
++
++out:
++ return ret;
++}
++
++static int mxc_epdc_fb_resume(struct device *dev)
++{
++ struct mxc_epdc_fb_data *data = dev_get_drvdata(dev);
++
++ mxc_epdc_fb_blank(FB_BLANK_UNBLANK, &data->info);
++ epdc_init_settings(data);
++ data->updates_active = false;
++
++ return 0;
++}
++#else
++#define mxc_epdc_fb_suspend NULL
++#define mxc_epdc_fb_resume NULL
++#endif
++
++#ifdef CONFIG_PM_RUNTIME
++static int mxc_epdc_fb_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "epdc busfreq high release.\n");
++
++ return 0;
++}
++
++static int mxc_epdc_fb_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "epdc busfreq high request.\n");
++
++ return 0;
++}
++#else
++#define mxc_epdc_fb_runtime_suspend NULL
++#define mxc_epdc_fb_runtime_resume NULL
++#endif
++
++static const struct dev_pm_ops mxc_epdc_fb_pm_ops = {
++ SET_RUNTIME_PM_OPS(mxc_epdc_fb_runtime_suspend,
++ mxc_epdc_fb_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(mxc_epdc_fb_suspend, mxc_epdc_fb_resume)
++};
++
++static void mxc_epdc_fb_shutdown(struct platform_device *pdev)
++{
++ struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev);
++
++ /* Disable power to the EPD panel */
++ if (regulator_is_enabled(fb_data->vcom_regulator))
++ regulator_disable(fb_data->vcom_regulator);
++ if (regulator_is_enabled(fb_data->display_regulator))
++ regulator_disable(fb_data->display_regulator);
++
++ /* Disable clocks to EPDC */
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++ clk_prepare_enable(fb_data->epdc_clk_pix);
++ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET);
++ clk_disable_unprepare(fb_data->epdc_clk_pix);
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++
++ /* turn off the V3p3 */
++ if (regulator_is_enabled(fb_data->v3p3_regulator))
++ regulator_disable(fb_data->v3p3_regulator);
++}
++
++static struct platform_driver mxc_epdc_fb_driver = {
++ .probe = mxc_epdc_fb_probe,
++ .remove = mxc_epdc_fb_remove,
++ .shutdown = mxc_epdc_fb_shutdown,
++ .driver = {
++ .name = "imx_epdc_fb",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(imx_epdc_dt_ids),
++ .pm = &mxc_epdc_fb_pm_ops,
++ },
++};
++
++/* Callback function triggered after PxP receives an EOF interrupt */
++static void pxp_dma_done(void *arg)
++{
++ struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
++ struct dma_chan *chan = tx_desc->txd.chan;
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct mxc_epdc_fb_data *fb_data = pxp_chan->client;
++
++ /* This call will signal wait_for_completion_timeout() in send_buffer_to_pxp */
++ complete(&fb_data->pxp_tx_cmpl);
++}
++
++static bool chan_filter(struct dma_chan *chan, void *arg)
++{
++ if (imx_dma_is_pxp(chan))
++ return true;
++ else
++ return false;
++}
++
++/* Function to request PXP DMA channel */
++static int pxp_chan_init(struct mxc_epdc_fb_data *fb_data)
++{
++ dma_cap_mask_t mask;
++ struct dma_chan *chan;
++
++ /*
++ * Request a free channel
++ */
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_PRIVATE, mask);
++ chan = dma_request_channel(mask, chan_filter, NULL);
++ if (!chan) {
++ dev_err(fb_data->dev, "Unsuccessfully received channel!!!!\n");
++ return -EBUSY;
++ }
++
++ fb_data->pxp_chan = to_pxp_channel(chan);
++ fb_data->pxp_chan->client = fb_data;
++
++ init_completion(&fb_data->pxp_tx_cmpl);
++
++ return 0;
++}
++
++/*
++ * Function to call PxP DMA driver and send our latest FB update region
++ * through the PxP and out to an intermediate buffer.
++ * Note: This is a blocking call, so upon return the PxP tx should be complete.
++ */
++static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
++ u32 src_width, u32 src_height,
++ struct mxcfb_rect *update_region)
++{
++ dma_cookie_t cookie;
++ struct scatterlist *sg = fb_data->sg;
++ struct dma_chan *dma_chan;
++ struct pxp_tx_desc *desc;
++ struct dma_async_tx_descriptor *txd;
++ struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
++ struct pxp_proc_data *proc_data = &fb_data->pxp_conf.proc_data;
++ int i, ret;
++ int length;
++
++ dev_dbg(fb_data->dev, "Starting PxP Send Buffer\n");
++
++ /* First, check to see that we have acquired a PxP Channel object */
++ if (fb_data->pxp_chan == NULL) {
++ /*
++ * PxP Channel has not yet been created and initialized,
++ * so let's go ahead and try
++ */
++ ret = pxp_chan_init(fb_data);
++ if (ret) {
++ /*
++ * PxP channel init failed, and we can't use the
++ * PxP until the PxP DMA driver has loaded, so we abort
++ */
++ dev_err(fb_data->dev, "PxP chan init failed\n");
++ return -ENODEV;
++ }
++ }
++
++ /*
++ * Init completion, so that we
++ * can be properly informed of the completion
++ * of the PxP task when it is done.
++ */
++ init_completion(&fb_data->pxp_tx_cmpl);
++
++ dma_chan = &fb_data->pxp_chan->dma_chan;
++
++ txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2,
++ DMA_TO_DEVICE,
++ DMA_PREP_INTERRUPT,
++ NULL);
++ if (!txd) {
++ dev_err(fb_data->info.device,
++ "Error preparing a DMA transaction descriptor.\n");
++ return -EIO;
++ }
++
++ txd->callback_param = txd;
++ txd->callback = pxp_dma_done;
++
++ /*
++ * Configure PxP for processing of new update region
++ * The rest of our config params were set up in
++ * probe() and should not need to be changed.
++ */
++ pxp_conf->s0_param.width = src_width;
++ pxp_conf->s0_param.height = src_height;
++ proc_data->srect.top = update_region->top;
++ proc_data->srect.left = update_region->left;
++ proc_data->srect.width = update_region->width;
++ proc_data->srect.height = update_region->height;
++
++ /*
++ * Because only YUV/YCbCr image can be scaled, configure
++ * drect equivalent to srect, as such do not perform scaling.
++ */
++ proc_data->drect.top = 0;
++ proc_data->drect.left = 0;
++ proc_data->drect.width = proc_data->srect.width;
++ proc_data->drect.height = proc_data->srect.height;
++
++ /* PXP expects rotation in terms of degrees */
++ proc_data->rotate = fb_data->epdc_fb_var.rotate * 90;
++ if (proc_data->rotate > 270)
++ proc_data->rotate = 0;
++
++ pxp_conf->out_param.width = update_region->width;
++ pxp_conf->out_param.height = update_region->height;
++
++ if ((proc_data->rotate == 90) || (proc_data->rotate == 270))
++ pxp_conf->out_param.stride = update_region->height;
++ else
++ pxp_conf->out_param.stride = update_region->width;
++
++ /* For EPDC v2.0, we need output to be 64-bit
++ * aligned since EPDC stride does not work. */
++ if (fb_data->rev <= 20)
++ pxp_conf->out_param.stride = ALIGN(pxp_conf->out_param.stride, 8);
++
++
++ desc = to_tx_desc(txd);
++ length = desc->len;
++ for (i = 0; i < length; i++) {
++ if (i == 0) {/* S0 */
++ memcpy(&desc->proc_data, proc_data, sizeof(struct pxp_proc_data));
++ pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]);
++ memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param,
++ sizeof(struct pxp_layer_param));
++ } else if (i == 1) {
++ pxp_conf->out_param.paddr = sg_dma_address(&sg[1]);
++ memcpy(&desc->layer_param.out_param, &pxp_conf->out_param,
++ sizeof(struct pxp_layer_param));
++ }
++ /* TODO: OverLay */
++
++ desc = desc->next;
++ }
++
++ /* Submitting our TX starts the PxP processing task */
++ cookie = txd->tx_submit(txd);
++ if (cookie < 0) {
++ dev_err(fb_data->info.device, "Error sending FB through PxP\n");
++ return -EIO;
++ }
++
++ fb_data->txd = txd;
++
++ /* trigger ePxP */
++ dma_async_issue_pending(dma_chan);
++
++ return 0;
++}
++
++static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat)
++{
++ int ret;
++ /*
++ * Wait for completion event, which will be set
++ * through our TX callback function.
++ */
++ ret = wait_for_completion_timeout(&fb_data->pxp_tx_cmpl, HZ / 10);
++ if (ret <= 0) {
++ dev_info(fb_data->info.device,
++ "PxP operation failed due to %s\n",
++ ret < 0 ? "user interrupt" : "timeout");
++ dma_release_channel(&fb_data->pxp_chan->dma_chan);
++ fb_data->pxp_chan = NULL;
++ return ret ? : -ETIMEDOUT;
++ }
++
++ if ((fb_data->pxp_conf.proc_data.lut_transform & EPDC_FLAG_USE_CMAP) &&
++ fb_data->pxp_conf.proc_data.lut_map_updated)
++ fb_data->pxp_conf.proc_data.lut_map_updated = false;
++
++ *hist_stat = to_tx_desc(fb_data->txd)->hist_status;
++ dma_release_channel(&fb_data->pxp_chan->dma_chan);
++ fb_data->pxp_chan = NULL;
++
++ dev_dbg(fb_data->dev, "TX completed\n");
++
++ return 0;
++}
++
++/*
++ * Different dithering algorithm can be used. We chose
++ * to implement Bill Atkinson's algorithm as an example
++ * Thanks Bill Atkinson for his dithering algorithm.
++ */
++
++/*
++ * Dithering algorithm implementation - Y8->Y1 version 1.0 for i.MX
++ */
++static void do_dithering_processing_Y1_v1_0(
++ unsigned char *update_region_ptr,
++ struct mxcfb_rect *update_region,
++ unsigned long update_region_stride,
++ int *err_dist)
++{
++
++ /* create a temp error distribution array */
++ int bwPix;
++ int y;
++ int col;
++ int *err_dist_l0, *err_dist_l1, *err_dist_l2, distrib_error;
++ int width_3 = update_region->width + 3;
++ char *y8buf;
++ int x_offset = 0;
++
++ /* prime a few elements the error distribution array */
++ for (y = 0; y < update_region->height; y++) {
++ /* Dithering the Y8 in sbuf to BW suitable for A2 waveform */
++ err_dist_l0 = err_dist + (width_3) * (y % 3);
++ err_dist_l1 = err_dist + (width_3) * ((y + 1) % 3);
++ err_dist_l2 = err_dist + (width_3) * ((y + 2) % 3);
++
++ y8buf = update_region_ptr + x_offset;
++
++ /* scan the line and convert the Y8 to BW */
++ for (col = 1; col <= update_region->width; col++) {
++ bwPix = *(err_dist_l0 + col) + *y8buf;
++
++ if (bwPix >= 128) {
++ *y8buf++ = 0xff;
++ distrib_error = (bwPix - 255) >> 3;
++ } else {
++ *y8buf++ = 0;
++ distrib_error = bwPix >> 3;
++ }
++
++ /* modify the error distribution buffer */
++ *(err_dist_l0 + col + 2) += distrib_error;
++ *(err_dist_l1 + col + 1) += distrib_error;
++ *(err_dist_l0 + col + 1) += distrib_error;
++ *(err_dist_l1 + col - 1) += distrib_error;
++ *(err_dist_l1 + col) += distrib_error;
++ *(err_dist_l2 + col) = distrib_error;
++ }
++ x_offset += update_region_stride;
++ }
++
++ flush_cache_all();
++ outer_flush_all();
++}
++
++/*
++ * Dithering algorithm implementation - Y8->Y4 version 1.0 for i.MX
++ */
++
++static void do_dithering_processing_Y4_v1_0(
++ unsigned char *update_region_ptr,
++ struct mxcfb_rect *update_region,
++ unsigned long update_region_stride,
++ int *err_dist)
++{
++
++ /* create a temp error distribution array */
++ int gcPix;
++ int y;
++ int col;
++ int *err_dist_l0, *err_dist_l1, *err_dist_l2, distrib_error;
++ int width_3 = update_region->width + 3;
++ char *y8buf;
++ int x_offset = 0;
++
++ /* prime a few elements the error distribution array */
++ for (y = 0; y < update_region->height; y++) {
++ /* Dithering the Y8 in sbuf to Y4 */
++ err_dist_l0 = err_dist + (width_3) * (y % 3);
++ err_dist_l1 = err_dist + (width_3) * ((y + 1) % 3);
++ err_dist_l2 = err_dist + (width_3) * ((y + 2) % 3);
++
++ y8buf = update_region_ptr + x_offset;
++
++ /* scan the line and convert the Y8 to Y4 */
++ for (col = 1; col <= update_region->width; col++) {
++ gcPix = *(err_dist_l0 + col) + *y8buf;
++
++ if (gcPix > 255)
++ gcPix = 255;
++ else if (gcPix < 0)
++ gcPix = 0;
++
++ distrib_error = (*y8buf - (gcPix & 0xf0)) >> 3;
++
++ *y8buf++ = gcPix & 0xf0;
++
++ /* modify the error distribution buffer */
++ *(err_dist_l0 + col + 2) += distrib_error;
++ *(err_dist_l1 + col + 1) += distrib_error;
++ *(err_dist_l0 + col + 1) += distrib_error;
++ *(err_dist_l1 + col - 1) += distrib_error;
++ *(err_dist_l1 + col) += distrib_error;
++ *(err_dist_l2 + col) = distrib_error;
++ }
++ x_offset += update_region_stride;
++ }
++
++ flush_cache_all();
++ outer_flush_all();
++}
++
++module_platform_driver(mxc_epdc_fb_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC EPDC framebuffer driver");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("fb");
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxcfb_hx8369_wvga.c linux-linaro-stable-mx6/drivers/video/mxc/mxcfb_hx8369_wvga.c
+--- linux-3.10.30.orig/drivers/video/mxc/mxcfb_hx8369_wvga.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxcfb_hx8369_wvga.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,449 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/spinlock.h>
++#include <linux/mipi_dsi.h>
++#include <linux/mxcfb.h>
++#include <linux/backlight.h>
++#include <video/mipi_display.h>
++
++#include "mipi_dsi.h"
++
++#define MIPI_DSI_MAX_RET_PACK_SIZE (0x4)
++
++#define HX8369BL_MAX_BRIGHT (255)
++#define HX8369BL_DEF_BRIGHT (255)
++
++#define HX8369_MAX_DPHY_CLK (800)
++#define HX8369_ONE_DATA_LANE (0x1)
++#define HX8369_TWO_DATA_LANE (0x2)
++
++#define HX8369_CMD_SETEXTC (0xB9)
++#define HX8369_CMD_SETEXTC_LEN (0x4)
++#define HX8369_CMD_SETEXTC_PARAM_1 (0x6983ff)
++
++#define HX8369_CMD_GETHXID (0xF4)
++#define HX8369_CMD_GETHXID_LEN (0x4)
++#define HX8369_ID (0x69)
++#define HX8369_ID_MASK (0xFF)
++
++#define HX8369_CMD_SETDISP (0xB2)
++#define HX8369_CMD_SETDISP_LEN (16)
++#define HX8369_CMD_SETDISP_1_HALT (0x00)
++#define HX8369_CMD_SETDISP_2_RES_MODE (0x23)
++#define HX8369_CMD_SETDISP_3_BP (0x03)
++#define HX8369_CMD_SETDISP_4_FP (0x03)
++#define HX8369_CMD_SETDISP_5_SAP (0x70)
++#define HX8369_CMD_SETDISP_6_GENON (0x00)
++#define HX8369_CMD_SETDISP_7_GENOFF (0xff)
++#define HX8369_CMD_SETDISP_8_RTN (0x00)
++#define HX8369_CMD_SETDISP_9_TEI (0x00)
++#define HX8369_CMD_SETDISP_10_TEP_UP (0x00)
++#define HX8369_CMD_SETDISP_11_TEP_LOW (0x00)
++#define HX8369_CMD_SETDISP_12_BP_PE (0x03)
++#define HX8369_CMD_SETDISP_13_FP_PE (0x03)
++#define HX8369_CMD_SETDISP_14_RTN_PE (0x00)
++#define HX8369_CMD_SETDISP_15_GON (0x01)
++
++#define HX8369_CMD_SETCYC (0xB4)
++#define HX8369_CMD_SETCYC_LEN (6)
++#define HX8369_CMD_SETCYC_PARAM_1 (0x5f1d00)
++#define HX8369_CMD_SETCYC_PARAM_2 (0x060e)
++
++#define HX8369_CMD_SETGIP (0xD5)
++#define HX8369_CMD_SETGIP_LEN (27)
++#define HX8369_CMD_SETGIP_PARAM_1 (0x030400)
++#define HX8369_CMD_SETGIP_PARAM_2 (0x1c050100)
++#define HX8369_CMD_SETGIP_PARAM_3 (0x00030170)
++#define HX8369_CMD_SETGIP_PARAM_4 (0x51064000)
++#define HX8369_CMD_SETGIP_PARAM_5 (0x41000007)
++#define HX8369_CMD_SETGIP_PARAM_6 (0x07075006)
++#define HX8369_CMD_SETGIP_PARAM_7 (0x040f)
++
++#define HX8369_CMD_SETPOWER (0xB1)
++#define HX8369_CMD_SETPOWER_LEN (20)
++#define HX8369_CMD_SETPOWER_PARAM_1 (0x340001)
++#define HX8369_CMD_SETPOWER_PARAM_2 (0x0f0f0006)
++#define HX8369_CMD_SETPOWER_PARAM_3 (0x3f3f322a)
++#define HX8369_CMD_SETPOWER_PARAM_4 (0xe6013a07)
++#define HX8369_CMD_SETPOWER_PARAM_5 (0xe6e6e6e6)
++
++#define HX8369_CMD_SETVCOM (0xB6)
++#define HX8369_CMD_SETVCOM_LEN (3)
++#define HX8369_CMD_SETVCOM_PARAM_1 (0x5656)
++
++#define HX8369_CMD_SETPANEL (0xCC)
++#define HX8369_CMD_SETPANEL_PARAM_1 (0x02)
++
++#define HX8369_CMD_SETGAMMA (0xE0)
++#define HX8369_CMD_SETGAMMA_LEN (35)
++#define HX8369_CMD_SETGAMMA_PARAM_1 (0x221d00)
++#define HX8369_CMD_SETGAMMA_PARAM_2 (0x2e3f3d38)
++#define HX8369_CMD_SETGAMMA_PARAM_3 (0x0f0d064a)
++#define HX8369_CMD_SETGAMMA_PARAM_4 (0x16131513)
++#define HX8369_CMD_SETGAMMA_PARAM_5 (0x1d001910)
++#define HX8369_CMD_SETGAMMA_PARAM_6 (0x3f3d3822)
++#define HX8369_CMD_SETGAMMA_PARAM_7 (0x0d064a2e)
++#define HX8369_CMD_SETGAMMA_PARAM_8 (0x1315130f)
++#define HX8369_CMD_SETGAMMA_PARAM_9 (0x191016)
++
++#define HX8369_CMD_SETMIPI (0xBA)
++#define HX8369_CMD_SETMIPI_LEN (14)
++#define HX8369_CMD_SETMIPI_PARAM_1 (0xc6a000)
++#define HX8369_CMD_SETMIPI_PARAM_2 (0x10000a00)
++#define HX8369_CMD_SETMIPI_ONELANE (0x10 << 24)
++#define HX8369_CMD_SETMIPI_TWOLANE (0x11 << 24)
++#define HX8369_CMD_SETMIPI_PARAM_3 (0x00026f30)
++#define HX8369_CMD_SETMIPI_PARAM_4 (0x4018)
++
++#define HX8369_CMD_SETPIXEL_FMT (0x3A)
++#define HX8369_CMD_SETPIXEL_FMT_24BPP (0x77)
++#define HX8369_CMD_SETPIXEL_FMT_18BPP (0x66)
++#define HX8369_CMD_SETPIXEL_FMT_16BPP (0x55)
++
++#define HX8369_CMD_SETCLUMN_ADDR (0x2A)
++#define HX8369_CMD_SETCLUMN_ADDR_LEN (5)
++#define HX8369_CMD_SETCLUMN_ADDR_PARAM_1 (0xdf0000)
++#define HX8369_CMD_SETCLUMN_ADDR_PARAM_2 (0x01)
++
++#define HX8369_CMD_SETPAGE_ADDR (0x2B)
++#define HX8369_CMD_SETPAGE_ADDR_LEN (5)
++#define HX8369_CMD_SETPAGE_ADDR_PARAM_1 (0x1f0000)
++#define HX8369_CMD_SETPAGE_ADDR_PARAM_2 (0x03)
++
++#define HX8369_CMD_WRT_DISP_BRIGHT (0x51)
++#define HX8369_CMD_WRT_DISP_BRIGHT_PARAM_1 (0xFF)
++
++#define HX8369_CMD_WRT_CABC_MIN_BRIGHT (0x5E)
++#define HX8369_CMD_WRT_CABC_MIN_BRIGHT_PARAM_1 (0x20)
++
++#define HX8369_CMD_WRT_CABC_CTRL (0x55)
++#define HX8369_CMD_WRT_CABC_CTRL_PARAM_1 (0x1)
++
++#define HX8369_CMD_WRT_CTRL_DISP (0x53)
++#define HX8369_CMD_WRT_CTRL_DISP_PARAM_1 (0x24)
++
++#define CHECK_RETCODE(ret) \
++do { \
++ if (ret < 0) { \
++ dev_err(&mipi_dsi->pdev->dev, \
++ "%s ERR: ret:%d, line:%d.\n", \
++ __func__, ret, __LINE__); \
++ return ret; \
++ } \
++} while (0)
++
++static int hx8369bl_brightness;
++static int mipid_init_backlight(struct mipi_dsi_info *mipi_dsi);
++
++static struct fb_videomode truly_lcd_modedb[] = {
++ {
++ "TRULY-WVGA", 64, 480, 800, 37880,
++ 8, 8,
++ 6, 6,
++ 8, 6,
++ FB_SYNC_OE_LOW_ACT,
++ FB_VMODE_NONINTERLACED,
++ 0,
++ },
++};
++
++static struct mipi_lcd_config lcd_config = {
++ .virtual_ch = 0x0,
++ .data_lane_num = HX8369_TWO_DATA_LANE,
++ .max_phy_clk = HX8369_MAX_DPHY_CLK,
++ .dpi_fmt = MIPI_RGB888,
++};
++void mipid_hx8369_get_lcd_videomode(struct fb_videomode **mode, int *size,
++ struct mipi_lcd_config **data)
++{
++ *mode = &truly_lcd_modedb[0];
++ *size = ARRAY_SIZE(truly_lcd_modedb);
++ *data = &lcd_config;
++}
++
++int mipid_hx8369_lcd_setup(struct mipi_dsi_info *mipi_dsi)
++{
++ u32 buf[DSI_CMD_BUF_MAXSIZE];
++ int err;
++
++ dev_dbg(&mipi_dsi->pdev->dev, "MIPI DSI LCD setup.\n");
++ buf[0] = HX8369_CMD_SETEXTC | (HX8369_CMD_SETEXTC_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETEXTC_LEN);
++ CHECK_RETCODE(err);
++ buf[0] = MIPI_DSI_MAX_RET_PACK_SIZE;
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
++ buf, 0);
++ CHECK_RETCODE(err);
++ buf[0] = HX8369_CMD_GETHXID;
++ err = mipi_dsi_pkt_read(mipi_dsi,
++ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM,
++ buf, HX8369_CMD_GETHXID_LEN);
++ if (!err && ((buf[0] & HX8369_ID_MASK) == HX8369_ID)) {
++ dev_info(&mipi_dsi->pdev->dev,
++ "MIPI DSI LCD ID:0x%x.\n", buf[0]);
++ } else {
++ dev_err(&mipi_dsi->pdev->dev,
++ "mipi_dsi_pkt_read err:%d, data:0x%x.\n",
++ err, buf[0]);
++ dev_info(&mipi_dsi->pdev->dev,
++ "MIPI DSI LCD not detected!\n");
++ return err;
++ }
++
++ /* set LCD resolution as 480RGBx800, DPI interface,
++ * display operation mode: RGB data bypass GRAM mode.
++ */
++ buf[0] = HX8369_CMD_SETDISP | (HX8369_CMD_SETDISP_1_HALT << 8) |
++ (HX8369_CMD_SETDISP_2_RES_MODE << 16) |
++ (HX8369_CMD_SETDISP_3_BP << 24);
++ buf[1] = HX8369_CMD_SETDISP_4_FP | (HX8369_CMD_SETDISP_5_SAP << 8) |
++ (HX8369_CMD_SETDISP_6_GENON << 16) |
++ (HX8369_CMD_SETDISP_7_GENOFF << 24);
++ buf[2] = HX8369_CMD_SETDISP_8_RTN | (HX8369_CMD_SETDISP_9_TEI << 8) |
++ (HX8369_CMD_SETDISP_10_TEP_UP << 16) |
++ (HX8369_CMD_SETDISP_11_TEP_LOW << 24);
++ buf[3] = HX8369_CMD_SETDISP_12_BP_PE |
++ (HX8369_CMD_SETDISP_13_FP_PE << 8) |
++ (HX8369_CMD_SETDISP_14_RTN_PE << 16) |
++ (HX8369_CMD_SETDISP_15_GON << 24);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETDISP_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set display waveform cycle */
++ buf[0] = HX8369_CMD_SETCYC | (HX8369_CMD_SETCYC_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETCYC_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETCYC_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set GIP timing output control */
++ buf[0] = HX8369_CMD_SETGIP | (HX8369_CMD_SETGIP_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETGIP_PARAM_2;
++ buf[2] = HX8369_CMD_SETGIP_PARAM_3;
++ buf[3] = HX8369_CMD_SETGIP_PARAM_4;
++ buf[4] = HX8369_CMD_SETGIP_PARAM_5;
++ buf[5] = HX8369_CMD_SETGIP_PARAM_6;
++ buf[6] = HX8369_CMD_SETGIP_PARAM_7;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETGIP_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set power: standby, DC etc. */
++ buf[0] = HX8369_CMD_SETPOWER | (HX8369_CMD_SETPOWER_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETPOWER_PARAM_2;
++ buf[2] = HX8369_CMD_SETPOWER_PARAM_3;
++ buf[3] = HX8369_CMD_SETPOWER_PARAM_4;
++ buf[4] = HX8369_CMD_SETPOWER_PARAM_5;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETPOWER_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set VCOM voltage. */
++ buf[0] = HX8369_CMD_SETVCOM | (HX8369_CMD_SETVCOM_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETVCOM_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set Panel: BGR/RGB or Inversion. */
++ buf[0] = HX8369_CMD_SETPANEL | (HX8369_CMD_SETPANEL_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM, buf, 0);
++ CHECK_RETCODE(err);
++
++ /* Set gamma curve related setting */
++ buf[0] = HX8369_CMD_SETGAMMA | (HX8369_CMD_SETGAMMA_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETGAMMA_PARAM_2;
++ buf[2] = HX8369_CMD_SETGAMMA_PARAM_3;
++ buf[3] = HX8369_CMD_SETGAMMA_PARAM_4;
++ buf[4] = HX8369_CMD_SETGAMMA_PARAM_5;
++ buf[5] = HX8369_CMD_SETGAMMA_PARAM_6;
++ buf[7] = HX8369_CMD_SETGAMMA_PARAM_7;
++ buf[7] = HX8369_CMD_SETGAMMA_PARAM_8;
++ buf[8] = HX8369_CMD_SETGAMMA_PARAM_9;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETGAMMA_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set MIPI: DPHYCMD & DSICMD, data lane number */
++ buf[0] = HX8369_CMD_SETMIPI | (HX8369_CMD_SETMIPI_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETMIPI_PARAM_2;
++ buf[2] = HX8369_CMD_SETMIPI_PARAM_3;
++ if (lcd_config.data_lane_num == HX8369_ONE_DATA_LANE)
++ buf[2] |= HX8369_CMD_SETMIPI_ONELANE;
++ else
++ buf[2] |= HX8369_CMD_SETMIPI_TWOLANE;
++ buf[3] = HX8369_CMD_SETMIPI_PARAM_4;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETMIPI_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set pixel format:24bpp */
++ buf[0] = HX8369_CMD_SETPIXEL_FMT;
++ switch (lcd_config.dpi_fmt) {
++ case MIPI_RGB565_PACKED:
++ case MIPI_RGB565_LOOSELY:
++ case MIPI_RGB565_CONFIG3:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_16BPP << 8);
++ break;
++
++ case MIPI_RGB666_LOOSELY:
++ case MIPI_RGB666_PACKED:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_18BPP << 8);
++ break;
++
++ case MIPI_RGB888:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_24BPP << 8);
++ break;
++
++ default:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_24BPP << 8);
++ break;
++ }
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ /* Set column address: 0~479 */
++ buf[0] = HX8369_CMD_SETCLUMN_ADDR |
++ (HX8369_CMD_SETCLUMN_ADDR_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETCLUMN_ADDR_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETCLUMN_ADDR_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set page address: 0~799 */
++ buf[0] = HX8369_CMD_SETPAGE_ADDR |
++ (HX8369_CMD_SETPAGE_ADDR_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETPAGE_ADDR_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETPAGE_ADDR_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set display brightness related */
++ buf[0] = HX8369_CMD_WRT_DISP_BRIGHT |
++ (HX8369_CMD_WRT_DISP_BRIGHT_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ buf[0] = HX8369_CMD_WRT_CABC_CTRL |
++ (HX8369_CMD_WRT_CABC_CTRL_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ buf[0] = HX8369_CMD_WRT_CTRL_DISP |
++ (HX8369_CMD_WRT_CTRL_DISP_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ /* exit sleep mode and set display on */
++ buf[0] = MIPI_DCS_EXIT_SLEEP_MODE;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++ /* To allow time for the supply voltages
++ * and clock circuits to stabilize.
++ */
++ msleep(5);
++ buf[0] = MIPI_DCS_SET_DISPLAY_ON;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ err = mipid_init_backlight(mipi_dsi);
++ return err;
++}
++
++static int mipid_bl_update_status(struct backlight_device *bl)
++{
++ u32 buf;
++ int brightness = bl->props.brightness;
++ struct mipi_dsi_info *mipi_dsi = bl_get_data(bl);
++
++ if (bl->props.power != FB_BLANK_UNBLANK ||
++ bl->props.fb_blank != FB_BLANK_UNBLANK)
++ brightness = 0;
++
++ buf = HX8369_CMD_WRT_DISP_BRIGHT |
++ ((brightness & HX8369BL_MAX_BRIGHT) << 8);
++ mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ &buf, 0);
++
++ hx8369bl_brightness = brightness & HX8369BL_MAX_BRIGHT;
++
++ dev_dbg(&bl->dev, "mipid backlight bringtness:%d.\n", brightness);
++ return 0;
++}
++
++static int mipid_bl_get_brightness(struct backlight_device *bl)
++{
++ return hx8369bl_brightness;
++}
++
++static int mipi_bl_check_fb(struct backlight_device *bl, struct fb_info *fbi)
++{
++ return 0;
++}
++
++static const struct backlight_ops mipid_lcd_bl_ops = {
++ .update_status = mipid_bl_update_status,
++ .get_brightness = mipid_bl_get_brightness,
++ .check_fb = mipi_bl_check_fb,
++};
++
++static int mipid_init_backlight(struct mipi_dsi_info *mipi_dsi)
++{
++ struct backlight_properties props;
++ struct backlight_device *bl;
++
++ if (mipi_dsi->bl) {
++ pr_debug("mipid backlight already init!\n");
++ return 0;
++ }
++ memset(&props, 0, sizeof(struct backlight_properties));
++ props.max_brightness = HX8369BL_MAX_BRIGHT;
++ props.type = BACKLIGHT_RAW;
++ bl = backlight_device_register("mipid-bl", &mipi_dsi->pdev->dev,
++ mipi_dsi, &mipid_lcd_bl_ops, &props);
++ if (IS_ERR(bl)) {
++ pr_err("error %ld on backlight register\n", PTR_ERR(bl));
++ return PTR_ERR(bl);
++ }
++ mipi_dsi->bl = bl;
++ bl->props.power = FB_BLANK_UNBLANK;
++ bl->props.fb_blank = FB_BLANK_UNBLANK;
++ bl->props.brightness = HX8369BL_DEF_BRIGHT;
++
++ mipid_bl_update_status(bl);
++ return 0;
++}
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxc_hdmi.c linux-linaro-stable-mx6/drivers/video/mxc/mxc_hdmi.c
+--- linux-3.10.30.orig/drivers/video/mxc/mxc_hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxc_hdmi.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,2935 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
++ * for SLISHDMI13T and SLIPHDMIT IP cores
++ *
++ * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/io.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/uaccess.h>
++#include <linux/cpufreq.h>
++#include <linux/firmware.h>
++#include <linux/kthread.h>
++#include <linux/regulator/driver.h>
++#include <linux/fsl_devices.h>
++#include <linux/ipu.h>
++#include <linux/regmap.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/of_device.h>
++
++#include <linux/console.h>
++#include <linux/types.h>
++
++#include "../edid.h"
++#include <video/mxc_edid.h>
++#include <video/mxc_hdmi.h>
++#include "mxc_dispdrv.h"
++
++#include <linux/mfd/mxc-hdmi-core.h>
++
++#define DISPDRV_HDMI "hdmi"
++#define HDMI_EDID_LEN 512
++
++/* status codes for reading edid */
++#define HDMI_EDID_SUCCESS 0
++#define HDMI_EDID_FAIL -1
++#define HDMI_EDID_SAME -2
++#define HDMI_EDID_NO_MODES -3
++
++#define NUM_CEA_VIDEO_MODES 64
++#define DEFAULT_VIDEO_MODE 16 /* 1080P */
++
++#define RGB 0
++#define YCBCR444 1
++#define YCBCR422_16BITS 2
++#define YCBCR422_8BITS 3
++#define XVYCC444 4
++
++/*
++ * We follow a flowchart which is in the "Synopsys DesignWare Courses
++ * HDMI Transmitter Controller User Guide, 1.30a", section 3.1
++ * (dwc_hdmi_tx_user.pdf)
++ *
++ * Below are notes that say "HDMI Initialization Step X"
++ * These correspond to the flowchart.
++ */
++
++/*
++ * We are required to configure VGA mode before reading edid
++ * in HDMI Initialization Step B
++ */
++static const struct fb_videomode vga_mode = {
++ /* 640x480 @ 60 Hz, 31.5 kHz hsync */
++ NULL, 60, 640, 480, 39721, 48, 16, 33, 10, 96, 2, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, FB_MODE_IS_VESA,
++};
++
++static const struct fb_videomode xga_mode = {
++ /* 13 1024x768-60 VESA */
++ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
++ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA
++};
++
++static const struct fb_videomode sxga_mode = {
++ /* 20 1280x1024-60 VESA */
++ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA
++};
++
++enum hdmi_datamap {
++ RGB444_8B = 0x01,
++ RGB444_10B = 0x03,
++ RGB444_12B = 0x05,
++ RGB444_16B = 0x07,
++ YCbCr444_8B = 0x09,
++ YCbCr444_10B = 0x0B,
++ YCbCr444_12B = 0x0D,
++ YCbCr444_16B = 0x0F,
++ YCbCr422_8B = 0x16,
++ YCbCr422_10B = 0x14,
++ YCbCr422_12B = 0x12,
++};
++
++enum hdmi_colorimetry {
++ eITU601,
++ eITU709,
++};
++
++struct hdmi_vmode {
++ bool mDVI;
++ bool mHSyncPolarity;
++ bool mVSyncPolarity;
++ bool mInterlaced;
++ bool mDataEnablePolarity;
++
++ unsigned int mPixelClock;
++ unsigned int mPixelRepetitionInput;
++ unsigned int mPixelRepetitionOutput;
++};
++
++struct hdmi_data_info {
++ unsigned int enc_in_format;
++ unsigned int enc_out_format;
++ unsigned int enc_color_depth;
++ unsigned int colorimetry;
++ unsigned int pix_repet_factor;
++ unsigned int hdcp_enable;
++ unsigned int rgb_out_enable;
++ struct hdmi_vmode video_mode;
++};
++
++struct hdmi_phy_reg_config {
++ /* HDMI PHY register config for pass HCT */
++ u16 reg_vlev;
++ u16 reg_cksymtx;
++};
++
++struct mxc_hdmi {
++ struct platform_device *pdev;
++ struct platform_device *core_pdev;
++ struct mxc_dispdrv_handle *disp_mxc_hdmi;
++ struct fb_info *fbi;
++ struct clk *hdmi_isfr_clk;
++ struct clk *hdmi_iahb_clk;
++ struct delayed_work hotplug_work;
++ struct delayed_work hdcp_hdp_work;
++
++ struct notifier_block nb;
++
++ struct hdmi_data_info hdmi_data;
++ int vic;
++ struct mxc_edid_cfg edid_cfg;
++ u8 edid[HDMI_EDID_LEN];
++ bool fb_reg;
++ bool cable_plugin;
++ u8 blank;
++ bool dft_mode_set;
++ char *dft_mode_str;
++ int default_bpp;
++ bool irq_enabled;
++ spinlock_t irq_lock;
++ bool phy_enabled;
++ struct fb_videomode previous_mode;
++ struct fb_videomode previous_non_vga_mode;
++ bool requesting_vga_for_initialization;
++
++ int *gpr_base;
++ int *gpr_hdmi_base;
++ int *gpr_sdma_base;
++ int cpu_type;
++ int cpu_version;
++ struct hdmi_phy_reg_config phy_config;
++
++ struct pinctrl *pinctrl;
++};
++
++static int hdmi_major;
++static struct class *hdmi_class;
++
++struct i2c_client *hdmi_i2c;
++struct mxc_hdmi *g_hdmi;
++
++static bool hdmi_inited;
++static bool hdcp_init;
++
++extern const struct fb_videomode mxc_cea_mode[64];
++extern void mxc_hdmi_cec_handle(u16 cec_stat);
++
++static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event);
++static void hdmi_enable_overflow_interrupts(void);
++static void hdmi_disable_overflow_interrupts(void);
++
++static struct platform_device_id imx_hdmi_devtype[] = {
++ {
++ .name = "hdmi-imx6DL",
++ .driver_data = IMX6DL_HDMI,
++ }, {
++ .name = "hdmi-imx6Q",
++ .driver_data = IMX6Q_HDMI,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-hdmi-video", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
++ { .compatible = "fsl,imx6q-hdmi-video", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
++
++static inline int cpu_is_imx6dl(struct mxc_hdmi *hdmi)
++{
++ return hdmi->cpu_type == IMX6DL_HDMI;
++}
++#ifdef DEBUG
++static void dump_fb_videomode(struct fb_videomode *m)
++{
++ pr_debug("fb_videomode = %d %d %d %d %d %d %d %d %d %d %d %d %d\n",
++ m->refresh, m->xres, m->yres, m->pixclock, m->left_margin,
++ m->right_margin, m->upper_margin, m->lower_margin,
++ m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
++}
++#else
++static void dump_fb_videomode(struct fb_videomode *m)
++{}
++#endif
++
++static ssize_t mxc_hdmi_show_name(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ strcpy(buf, hdmi->fbi->fix.id);
++ sprintf(buf+strlen(buf), "\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(fb_name, S_IRUGO, mxc_hdmi_show_name, NULL);
++
++static ssize_t mxc_hdmi_show_state(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (hdmi->cable_plugin == false)
++ strcpy(buf, "plugout\n");
++ else
++ strcpy(buf, "plugin\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(cable_state, S_IRUGO, mxc_hdmi_show_state, NULL);
++
++static ssize_t mxc_hdmi_show_edid(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ int i, j, len = 0;
++
++ for (j = 0; j < HDMI_EDID_LEN/16; j++) {
++ for (i = 0; i < 16; i++)
++ len += sprintf(buf+len, "0x%02X ",
++ hdmi->edid[j*16 + i]);
++ len += sprintf(buf+len, "\n");
++ }
++
++ return len;
++}
++
++static DEVICE_ATTR(edid, S_IRUGO, mxc_hdmi_show_edid, NULL);
++
++static ssize_t mxc_hdmi_show_rgb_out_enable(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (hdmi->hdmi_data.rgb_out_enable == true)
++ strcpy(buf, "RGB out\n");
++ else
++ strcpy(buf, "YCbCr out\n");
++
++ return strlen(buf);
++}
++
++static ssize_t mxc_hdmi_store_rgb_out_enable(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ unsigned long value;
++ int ret;
++
++ ret = strict_strtoul(buf, 10, &value);
++ if (ret)
++ return ret;
++
++ hdmi->hdmi_data.rgb_out_enable = value;
++
++ /* Reconfig HDMI for output color space change */
++ mxc_hdmi_setup(hdmi, 0);
++
++ return count;
++}
++
++static DEVICE_ATTR(rgb_out_enable, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_rgb_out_enable,
++ mxc_hdmi_store_rgb_out_enable);
++
++static ssize_t mxc_hdmi_show_hdcp_enable(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (hdmi->hdmi_data.hdcp_enable == false)
++ strcpy(buf, "hdcp disable\n");
++ else
++ strcpy(buf, "hdcp enable\n");
++
++ return strlen(buf);
++
++}
++
++static ssize_t mxc_hdmi_store_hdcp_enable(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++ unsigned long value;
++ int ret;
++
++ ret = strict_strtoul(buf, 10, &value);
++ if (ret)
++ return ret;
++
++ hdmi->hdmi_data.hdcp_enable = value;
++
++ /* Reconfig HDMI for HDCP */
++ mxc_hdmi_setup(hdmi, 0);
++
++ if (hdmi->hdmi_data.hdcp_enable == false) {
++ sprintf(event_string, "EVENT=hdcpdisable");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++ } else {
++ sprintf(event_string, "EVENT=hdcpenable");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++ }
++
++ return count;
++
++}
++
++static DEVICE_ATTR(hdcp_enable, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_hdcp_enable, mxc_hdmi_store_hdcp_enable);
++
++/*!
++ * this submodule is responsible for the video data synchronization.
++ * for example, for RGB 4:4:4 input, the data map is defined as
++ * pin{47~40} <==> R[7:0]
++ * pin{31~24} <==> G[7:0]
++ * pin{15~8} <==> B[7:0]
++ */
++static void hdmi_video_sample(struct mxc_hdmi *hdmi)
++{
++ int color_format = 0;
++ u8 val;
++
++ if (hdmi->hdmi_data.enc_in_format == RGB) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x01;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x03;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x05;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_format = 0x07;
++ else
++ return;
++ } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x09;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x0B;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x0D;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_format = 0x0F;
++ else
++ return;
++ } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x16;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x14;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x12;
++ else
++ return;
++ }
++
++ val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
++ ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
++ hdmi_writeb(val, HDMI_TX_INVID0);
++
++ /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
++ val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
++ hdmi_writeb(val, HDMI_TX_INSTUFFING);
++ hdmi_writeb(0x0, HDMI_TX_GYDATA0);
++ hdmi_writeb(0x0, HDMI_TX_GYDATA1);
++ hdmi_writeb(0x0, HDMI_TX_RCRDATA0);
++ hdmi_writeb(0x0, HDMI_TX_RCRDATA1);
++ hdmi_writeb(0x0, HDMI_TX_BCBDATA0);
++ hdmi_writeb(0x0, HDMI_TX_BCBDATA1);
++}
++
++static int isColorSpaceConversion(struct mxc_hdmi *hdmi)
++{
++ return (hdmi->hdmi_data.enc_in_format !=
++ hdmi->hdmi_data.enc_out_format);
++}
++
++static int isColorSpaceDecimation(struct mxc_hdmi *hdmi)
++{
++ return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
++ (hdmi->hdmi_data.enc_in_format == RGB ||
++ hdmi->hdmi_data.enc_in_format == YCBCR444));
++}
++
++static int isColorSpaceInterpolation(struct mxc_hdmi *hdmi)
++{
++ return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
++ (hdmi->hdmi_data.enc_out_format == RGB
++ || hdmi->hdmi_data.enc_out_format == YCBCR444));
++}
++
++/*!
++ * update the color space conversion coefficients.
++ */
++static void update_csc_coeffs(struct mxc_hdmi *hdmi)
++{
++ unsigned short csc_coeff[3][4];
++ unsigned int csc_scale = 1;
++ u8 val;
++ bool coeff_selected = false;
++
++ if (isColorSpaceConversion(hdmi)) { /* csc needed */
++ if (hdmi->hdmi_data.enc_out_format == RGB) {
++ if (hdmi->hdmi_data.colorimetry == eITU601) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x6926;
++ csc_coeff[0][2] = 0x74fd;
++ csc_coeff[0][3] = 0x010e;
++
++ csc_coeff[1][0] = 0x2000;
++ csc_coeff[1][1] = 0x2cdd;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x7e9a;
++
++ csc_coeff[2][0] = 0x2000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x38b4;
++ csc_coeff[2][3] = 0x7e3b;
++
++ csc_scale = 1;
++ coeff_selected = true;
++ } else if (hdmi->hdmi_data.colorimetry == eITU709) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x7106;
++ csc_coeff[0][2] = 0x7a02;
++ csc_coeff[0][3] = 0x00a7;
++
++ csc_coeff[1][0] = 0x2000;
++ csc_coeff[1][1] = 0x3264;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x7e6d;
++
++ csc_coeff[2][0] = 0x2000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x3b61;
++ csc_coeff[2][3] = 0x7e25;
++
++ csc_scale = 1;
++ coeff_selected = true;
++ }
++ } else if (hdmi->hdmi_data.enc_in_format == RGB) {
++ if (hdmi->hdmi_data.colorimetry == eITU601) {
++ csc_coeff[0][0] = 0x2591;
++ csc_coeff[0][1] = 0x1322;
++ csc_coeff[0][2] = 0x074b;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x6535;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x7acc;
++ csc_coeff[1][3] = 0x0200;
++
++ csc_coeff[2][0] = 0x6acd;
++ csc_coeff[2][1] = 0x7534;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0200;
++
++ csc_scale = 0;
++ coeff_selected = true;
++ } else if (hdmi->hdmi_data.colorimetry == eITU709) {
++ csc_coeff[0][0] = 0x2dc5;
++ csc_coeff[0][1] = 0x0d9b;
++ csc_coeff[0][2] = 0x049e;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x62f0;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x7d11;
++ csc_coeff[1][3] = 0x0200;
++
++ csc_coeff[2][0] = 0x6756;
++ csc_coeff[2][1] = 0x78ab;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0200;
++
++ csc_scale = 0;
++ coeff_selected = true;
++ }
++ }
++ }
++
++ if (!coeff_selected) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x0000;
++ csc_coeff[0][2] = 0x0000;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x0000;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x0000;
++
++ csc_coeff[2][0] = 0x0000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0000;
++
++ csc_scale = 1;
++ }
++
++ /* Update CSC parameters in HDMI CSC registers */
++ hdmi_writeb((unsigned char)(csc_coeff[0][0] & 0xFF),
++ HDMI_CSC_COEF_A1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][0] >> 8),
++ HDMI_CSC_COEF_A1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][1] & 0xFF),
++ HDMI_CSC_COEF_A2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][1] >> 8),
++ HDMI_CSC_COEF_A2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][2] & 0xFF),
++ HDMI_CSC_COEF_A3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][2] >> 8),
++ HDMI_CSC_COEF_A3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][3] & 0xFF),
++ HDMI_CSC_COEF_A4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][3] >> 8),
++ HDMI_CSC_COEF_A4_MSB);
++
++ hdmi_writeb((unsigned char)(csc_coeff[1][0] & 0xFF),
++ HDMI_CSC_COEF_B1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][0] >> 8),
++ HDMI_CSC_COEF_B1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][1] & 0xFF),
++ HDMI_CSC_COEF_B2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][1] >> 8),
++ HDMI_CSC_COEF_B2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][2] & 0xFF),
++ HDMI_CSC_COEF_B3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][2] >> 8),
++ HDMI_CSC_COEF_B3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][3] & 0xFF),
++ HDMI_CSC_COEF_B4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][3] >> 8),
++ HDMI_CSC_COEF_B4_MSB);
++
++ hdmi_writeb((unsigned char)(csc_coeff[2][0] & 0xFF),
++ HDMI_CSC_COEF_C1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][0] >> 8),
++ HDMI_CSC_COEF_C1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][1] & 0xFF),
++ HDMI_CSC_COEF_C2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][1] >> 8),
++ HDMI_CSC_COEF_C2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][2] & 0xFF),
++ HDMI_CSC_COEF_C3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][2] >> 8),
++ HDMI_CSC_COEF_C3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][3] & 0xFF),
++ HDMI_CSC_COEF_C4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][3] >> 8),
++ HDMI_CSC_COEF_C4_MSB);
++
++ val = hdmi_readb(HDMI_CSC_SCALE);
++ val &= ~HDMI_CSC_SCALE_CSCSCALE_MASK;
++ val |= csc_scale & HDMI_CSC_SCALE_CSCSCALE_MASK;
++ hdmi_writeb(val, HDMI_CSC_SCALE);
++}
++
++static void hdmi_video_csc(struct mxc_hdmi *hdmi)
++{
++ int color_depth = 0;
++ int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
++ int decimation = 0;
++ u8 val;
++
++ /* YCC422 interpolation to 444 mode */
++ if (isColorSpaceInterpolation(hdmi))
++ interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
++ else if (isColorSpaceDecimation(hdmi))
++ decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
++
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
++ else
++ return;
++
++ /*configure the CSC registers */
++ hdmi_writeb(interpolation | decimation, HDMI_CSC_CFG);
++ val = hdmi_readb(HDMI_CSC_SCALE);
++ val &= ~HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK;
++ val |= color_depth;
++ hdmi_writeb(val, HDMI_CSC_SCALE);
++
++ update_csc_coeffs(hdmi);
++}
++
++/*!
++ * HDMI video packetizer is used to packetize the data.
++ * for example, if input is YCC422 mode or repeater is used,
++ * data should be repacked this module can be bypassed.
++ */
++static void hdmi_video_packetize(struct mxc_hdmi *hdmi)
++{
++ unsigned int color_depth = 0;
++ unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
++ unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
++ struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
++ u8 val;
++
++ if (hdmi_data->enc_out_format == RGB
++ || hdmi_data->enc_out_format == YCBCR444) {
++ if (hdmi_data->enc_color_depth == 0)
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
++ else if (hdmi_data->enc_color_depth == 8) {
++ color_depth = 4;
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
++ } else if (hdmi_data->enc_color_depth == 10)
++ color_depth = 5;
++ else if (hdmi_data->enc_color_depth == 12)
++ color_depth = 6;
++ else if (hdmi_data->enc_color_depth == 16)
++ color_depth = 7;
++ else
++ return;
++ } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
++ if (hdmi_data->enc_color_depth == 0 ||
++ hdmi_data->enc_color_depth == 8)
++ remap_size = HDMI_VP_REMAP_YCC422_16bit;
++ else if (hdmi_data->enc_color_depth == 10)
++ remap_size = HDMI_VP_REMAP_YCC422_20bit;
++ else if (hdmi_data->enc_color_depth == 12)
++ remap_size = HDMI_VP_REMAP_YCC422_24bit;
++ else
++ return;
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
++ } else
++ return;
++
++ /* HDMI not support deep color,
++ * because IPU MAX support color depth is 24bit */
++ color_depth = 0;
++
++ /* set the packetizer registers */
++ val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
++ ((hdmi_data->pix_repet_factor <<
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
++ hdmi_writeb(val, HDMI_VP_PR_CD);
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~HDMI_VP_STUFF_PR_STUFFING_MASK;
++ val |= HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ /* Data from pixel repeater block */
++ if (hdmi_data->pix_repet_factor > 1) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_PR_EN_MASK |
++ HDMI_VP_CONF_BYPASS_SELECT_MASK);
++ val |= HDMI_VP_CONF_PR_EN_ENABLE |
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else { /* data from packetizer block */
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_PR_EN_MASK |
++ HDMI_VP_CONF_BYPASS_SELECT_MASK);
++ val |= HDMI_VP_CONF_PR_EN_DISABLE |
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ }
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~HDMI_VP_STUFF_IDEFAULT_PHASE_MASK;
++ val |= 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ hdmi_writeb(remap_size, HDMI_VP_REMAP);
++
++ if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
++ HDMI_VP_CONF_PP_EN_ENABLE |
++ HDMI_VP_CONF_YCC422_EN_DISABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
++ HDMI_VP_CONF_PP_EN_DISABLE |
++ HDMI_VP_CONF_YCC422_EN_ENABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_ENABLE |
++ HDMI_VP_CONF_PP_EN_DISABLE |
++ HDMI_VP_CONF_YCC422_EN_DISABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else {
++ return;
++ }
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~(HDMI_VP_STUFF_PP_STUFFING_MASK |
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK);
++ val |= HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~HDMI_VP_CONF_OUTPUT_SELECTOR_MASK;
++ val |= output_select;
++ hdmi_writeb(val, HDMI_VP_CONF);
++}
++
++#if 0
++/* Force a fixed color screen */
++static void hdmi_video_force_output(struct mxc_hdmi *hdmi, unsigned char force)
++{
++ u8 val;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (force) {
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
++ hdmi_writeb(0xFF, HDMI_FC_DBGTMDS0); /* B */
++ val = hdmi_readb(HDMI_FC_DBGFORCE);
++ val |= HDMI_FC_DBGFORCE_FORCEVIDEO;
++ hdmi_writeb(val, HDMI_FC_DBGFORCE);
++ } else {
++ val = hdmi_readb(HDMI_FC_DBGFORCE);
++ val &= ~HDMI_FC_DBGFORCE_FORCEVIDEO;
++ hdmi_writeb(val, HDMI_FC_DBGFORCE);
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS0); /* B */
++ }
++}
++#endif
++
++static inline void hdmi_phy_test_clear(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTCLR_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) &
++ HDMI_PHY_TST0_TSTCLR_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_enable(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTEN_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTEN_OFFSET) &
++ HDMI_PHY_TST0_TSTEN_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_clock(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTCLK_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTCLK_OFFSET) &
++ HDMI_PHY_TST0_TSTCLK_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_din(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_writeb(bit, HDMI_PHY_TST1);
++}
++
++static inline void hdmi_phy_test_dout(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_writeb(bit, HDMI_PHY_TST2);
++}
++
++static bool hdmi_phy_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
++{
++ unsigned char val = 0;
++ val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
++ while (val == 0) {
++ udelay(1000);
++ if (msec-- == 0)
++ return false;
++ val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
++ }
++ return true;
++}
++
++static void hdmi_phy_i2c_write(struct mxc_hdmi *hdmi, unsigned short data,
++ unsigned char addr)
++{
++ hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
++ hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
++ hdmi_writeb((unsigned char)(data >> 8),
++ HDMI_PHY_I2CM_DATAO_1_ADDR);
++ hdmi_writeb((unsigned char)(data >> 0),
++ HDMI_PHY_I2CM_DATAO_0_ADDR);
++ hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
++ HDMI_PHY_I2CM_OPERATION_ADDR);
++ hdmi_phy_wait_i2c_done(hdmi, 1000);
++}
++
++#if 0
++static unsigned short hdmi_phy_i2c_read(struct mxc_hdmi *hdmi,
++ unsigned char addr)
++{
++ unsigned short data;
++ unsigned char msb = 0, lsb = 0;
++ hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
++ hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
++ hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_READ,
++ HDMI_PHY_I2CM_OPERATION_ADDR);
++ hdmi_phy_wait_i2c_done(hdmi, 1000);
++ msb = hdmi_readb(HDMI_PHY_I2CM_DATAI_1_ADDR);
++ lsb = hdmi_readb(HDMI_PHY_I2CM_DATAI_0_ADDR);
++ data = (msb << 8) | lsb;
++ return data;
++}
++
++static int hdmi_phy_i2c_write_verify(struct mxc_hdmi *hdmi, unsigned short data,
++ unsigned char addr)
++{
++ unsigned short val = 0;
++ hdmi_phy_i2c_write(hdmi, data, addr);
++ val = hdmi_phy_i2c_read(hdmi, addr);
++ return (val == data);
++}
++#endif
++
++static bool hdmi_edid_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
++{
++ unsigned char val = 0;
++ val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
++ while (val == 0) {
++
++ udelay(1000);
++ if (msec-- == 0) {
++ dev_dbg(&hdmi->pdev->dev,
++ "HDMI EDID i2c operation time out!!\n");
++ return false;
++ }
++ val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
++ }
++ return true;
++}
++
++static u8 hdmi_edid_i2c_read(struct mxc_hdmi *hdmi,
++ u8 addr, u8 blockno)
++{
++ u8 spointer = blockno / 2;
++ u8 edidaddress = ((blockno % 2) * 0x80) + addr;
++ u8 data;
++
++ hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
++ hdmi_writeb(edidaddress, HDMI_I2CM_ADDRESS);
++ hdmi_writeb(spointer, HDMI_I2CM_SEGADDR);
++ if (spointer == 0)
++ hdmi_writeb(HDMI_I2CM_OPERATION_READ,
++ HDMI_I2CM_OPERATION);
++ else
++ hdmi_writeb(HDMI_I2CM_OPERATION_READ_EXT,
++ HDMI_I2CM_OPERATION);
++
++ hdmi_edid_wait_i2c_done(hdmi, 1000);
++ data = hdmi_readb(HDMI_I2CM_DATAI);
++ hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
++ return data;
++}
++
++
++/* "Power-down enable (active low)"
++ * That mean that power up == 1! */
++static void mxc_hdmi_phy_enable_power(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_PDZ_OFFSET,
++ HDMI_PHY_CONF0_PDZ_MASK);
++}
++
++static void mxc_hdmi_phy_enable_tmds(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET,
++ HDMI_PHY_CONF0_ENTMDS_MASK);
++}
++
++static void mxc_hdmi_phy_gen2_pddq(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
++}
++
++static void mxc_hdmi_phy_gen2_txpwron(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
++}
++
++#if 0
++static void mxc_hdmi_phy_gen2_enhpdrxsense(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK);
++}
++#endif
++
++static void mxc_hdmi_phy_sel_data_en_pol(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK);
++}
++
++static void mxc_hdmi_phy_sel_interface_control(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET,
++ HDMI_PHY_CONF0_SELDIPIF_MASK);
++}
++
++static int hdmi_phy_configure(struct mxc_hdmi *hdmi, unsigned char pRep,
++ unsigned char cRes, int cscOn)
++{
++ u8 val;
++ u8 msec;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* color resolution 0 is 8 bit colour depth */
++ if (cRes == 0)
++ cRes = 8;
++
++ if (pRep != 0)
++ return false;
++ else if (cRes != 8 && cRes != 12)
++ return false;
++
++ /* Enable csc path */
++ if (cscOn)
++ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
++ else
++ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
++
++ hdmi_writeb(val, HDMI_MC_FLOWCTRL);
++
++ /* gen2 tx power off */
++ mxc_hdmi_phy_gen2_txpwron(0);
++
++ /* gen2 pddq */
++ mxc_hdmi_phy_gen2_pddq(1);
++
++ /* PHY reset */
++ hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
++ hdmi_writeb(HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
++
++ hdmi_writeb(HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
++
++ hdmi_phy_test_clear(hdmi, 1);
++ hdmi_writeb(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
++ HDMI_PHY_I2CM_SLAVE_ADDR);
++ hdmi_phy_test_clear(hdmi, 0);
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock < 0) {
++ dev_dbg(&hdmi->pdev->dev, "Pixel clock (%d) must be positive\n",
++ hdmi->hdmi_data.video_mode.mPixelClock);
++ return false;
++ }
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock <= 45250000) {
++ switch (cRes) {
++ case 8:
++ /* PLL/MPLL Cfg */
++ hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); /* GMPCTRL */
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x21e1, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x41e2, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 92500000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x0140, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x2141, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x4142, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 148500000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x20a1, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x40a2, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ default:
++ return false;
++ }
++ } else {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x2001, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x4002, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
++ default:
++ return false;
++ }
++ }
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock <= 54000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); /* CURRCTRL */
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 58400000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 72000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 74250000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 118800000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 216000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else {
++ dev_err(&hdmi->pdev->dev,
++ "Pixel clock %d - unsupported by HDMI\n",
++ hdmi->hdmi_data.video_mode.mPixelClock);
++ return false;
++ }
++
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
++ hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
++ /* RESISTANCE TERM 133Ohm Cfg */
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
++ /* PREEMP Cgf 0.00 */
++ hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */
++ /* TX/CK LVL 10 */
++ hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
++
++ /* Board specific setting for PHY register 0x09, 0x0e to pass HCT */
++ if (hdmi->phy_config.reg_cksymtx != 0)
++ hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_cksymtx, 0x09);
++
++ if (hdmi->phy_config.reg_vlev != 0)
++ hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_vlev, 0x0E);
++
++ /* REMOVE CLK TERM */
++ hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock > 148500000) {
++ hdmi_phy_i2c_write(hdmi, 0x800b, 0x09);
++ hdmi_phy_i2c_write(hdmi, 0x0129, 0x0E);
++ }
++
++ mxc_hdmi_phy_enable_power(1);
++
++ /* toggle TMDS enable */
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_tmds(1);
++
++ /* gen2 tx power on */
++ mxc_hdmi_phy_gen2_txpwron(1);
++ mxc_hdmi_phy_gen2_pddq(0);
++
++ /*Wait for PHY PLL lock */
++ msec = 4;
++ val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
++ while (val == 0) {
++ udelay(1000);
++ if (msec-- == 0) {
++ dev_dbg(&hdmi->pdev->dev, "PHY PLL not locked\n");
++ return false;
++ }
++ val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
++ }
++
++ return true;
++}
++
++static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi)
++{
++ int i;
++ bool cscon = false;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Never do phy init if pixel clock is gated.
++ * Otherwise HDMI PHY will get messed up and generate an overflow
++ * interrupt that can't be cleared or detected by accessing the
++ * status register. */
++ if (!hdmi->fb_reg || !hdmi->cable_plugin
++ || (hdmi->blank != FB_BLANK_UNBLANK))
++ return;
++
++ /*check csc whether needed activated in HDMI mode */
++ cscon = (isColorSpaceConversion(hdmi) &&
++ !hdmi->hdmi_data.video_mode.mDVI);
++
++ /* HDMI Phy spec says to do the phy initialization sequence twice */
++ for (i = 0 ; i < 2 ; i++) {
++ mxc_hdmi_phy_sel_data_en_pol(1);
++ mxc_hdmi_phy_sel_interface_control(0);
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_power(0);
++
++ /* Enable CSC */
++ hdmi_phy_configure(hdmi, 0, 8, cscon);
++ }
++
++ hdmi->phy_enabled = true;
++ if (!hdmi->hdmi_data.video_mode.mDVI)
++ hdmi_enable_overflow_interrupts();
++}
++
++static void hdmi_config_AVI(struct mxc_hdmi *hdmi)
++{
++ u8 val;
++ u8 pix_fmt;
++ u8 under_scan;
++ u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
++ struct fb_videomode mode;
++ const struct fb_videomode *edid_mode;
++ bool aspect_16_9;
++
++ dev_dbg(&hdmi->pdev->dev, "set up AVI frame\n");
++
++ fb_var_to_videomode(&mode, &hdmi->fbi->var);
++ /* Use mode from list extracted from EDID to get aspect ratio */
++ if (!list_empty(&hdmi->fbi->modelist)) {
++ edid_mode = fb_find_nearest_mode(&mode, &hdmi->fbi->modelist);
++ if (edid_mode->vmode & FB_VMODE_ASPECT_16_9)
++ aspect_16_9 = true;
++ else
++ aspect_16_9 = false;
++ } else
++ aspect_16_9 = false;
++
++ /********************************************
++ * AVI Data Byte 1
++ ********************************************/
++ if (hdmi->hdmi_data.enc_out_format == YCBCR444)
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
++ else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
++ else
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
++
++ if (hdmi->edid_cfg.cea_underscan)
++ under_scan = HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN;
++ else
++ under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
++
++ /*
++ * Active format identification data is present in the AVI InfoFrame.
++ * Under scan info, no bar data
++ */
++ val = pix_fmt | under_scan |
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
++
++ hdmi_writeb(val, HDMI_FC_AVICONF0);
++
++ /********************************************
++ * AVI Data Byte 2
++ ********************************************/
++
++ /* Set the Aspect Ratio */
++ if (aspect_16_9) {
++ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
++ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
++ } else {
++ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
++ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
++ }
++
++ /* Set up colorimetry */
++ if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
++ if (hdmi->hdmi_data.colorimetry == eITU601)
++ ext_colorimetry =
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ else /* hdmi->hdmi_data.colorimetry == eITU709 */
++ ext_colorimetry =
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
++ } else if (hdmi->hdmi_data.enc_out_format != RGB) {
++ if (hdmi->hdmi_data.colorimetry == eITU601)
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
++ else /* hdmi->hdmi_data.colorimetry == eITU709 */
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
++ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ } else { /* Carries no data */
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
++ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ }
++
++ val = colorimetry | coded_ratio | act_ratio;
++ hdmi_writeb(val, HDMI_FC_AVICONF1);
++
++ /********************************************
++ * AVI Data Byte 3
++ ********************************************/
++
++ val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
++ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT |
++ HDMI_FC_AVICONF2_SCALING_NONE;
++ hdmi_writeb(val, HDMI_FC_AVICONF2);
++
++ /********************************************
++ * AVI Data Byte 4
++ ********************************************/
++ hdmi_writeb(hdmi->vic, HDMI_FC_AVIVID);
++
++ /********************************************
++ * AVI Data Byte 5
++ ********************************************/
++
++ /* Set up input and output pixel repetition */
++ val = (((hdmi->hdmi_data.video_mode.mPixelRepetitionInput + 1) <<
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
++ ((hdmi->hdmi_data.video_mode.mPixelRepetitionOutput <<
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
++ hdmi_writeb(val, HDMI_FC_PRCONF);
++
++ /* IT Content and quantization range = don't care */
++ val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
++ hdmi_writeb(val, HDMI_FC_AVICONF3);
++
++ /********************************************
++ * AVI Data Bytes 6-13
++ ********************************************/
++ hdmi_writeb(0, HDMI_FC_AVIETB0);
++ hdmi_writeb(0, HDMI_FC_AVIETB1);
++ hdmi_writeb(0, HDMI_FC_AVISBB0);
++ hdmi_writeb(0, HDMI_FC_AVISBB1);
++ hdmi_writeb(0, HDMI_FC_AVIELB0);
++ hdmi_writeb(0, HDMI_FC_AVIELB1);
++ hdmi_writeb(0, HDMI_FC_AVISRB0);
++ hdmi_writeb(0, HDMI_FC_AVISRB1);
++}
++
++/*!
++ * this submodule is responsible for the video/audio data composition.
++ */
++static void hdmi_av_composer(struct mxc_hdmi *hdmi)
++{
++ u8 inv_val;
++ struct fb_info *fbi = hdmi->fbi;
++ struct fb_videomode fb_mode;
++ struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
++ int hblank, vblank;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_var_to_videomode(&fb_mode, &fbi->var);
++
++ vmode->mHSyncPolarity = ((fb_mode.sync & FB_SYNC_HOR_HIGH_ACT) != 0);
++ vmode->mVSyncPolarity = ((fb_mode.sync & FB_SYNC_VERT_HIGH_ACT) != 0);
++ vmode->mInterlaced = ((fb_mode.vmode & FB_VMODE_INTERLACED) != 0);
++ vmode->mPixelClock = (fb_mode.xres + fb_mode.left_margin +
++ fb_mode.right_margin + fb_mode.hsync_len) * (fb_mode.yres +
++ fb_mode.upper_margin + fb_mode.lower_margin +
++ fb_mode.vsync_len) * fb_mode.refresh;
++
++ dev_dbg(&hdmi->pdev->dev, "final pixclk = %d\n", vmode->mPixelClock);
++
++ /* Set up HDMI_FC_INVIDCONF */
++ inv_val = (vmode->mVSyncPolarity ?
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
++
++ inv_val |= (vmode->mHSyncPolarity ?
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
++
++ inv_val |= (vmode->mDataEnablePolarity ?
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
++
++ if (hdmi->vic == 39)
++ inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
++ else
++ inv_val |= (vmode->mInterlaced ?
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
++
++ inv_val |= (vmode->mInterlaced ?
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
++
++ inv_val |= (vmode->mDVI ?
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
++
++ hdmi_writeb(inv_val, HDMI_FC_INVIDCONF);
++
++ /* Set up horizontal active pixel region width */
++ hdmi_writeb(fb_mode.xres >> 8, HDMI_FC_INHACTV1);
++ hdmi_writeb(fb_mode.xres, HDMI_FC_INHACTV0);
++
++ /* Set up vertical blanking pixel region width */
++ hdmi_writeb(fb_mode.yres >> 8, HDMI_FC_INVACTV1);
++ hdmi_writeb(fb_mode.yres, HDMI_FC_INVACTV0);
++
++ /* Set up horizontal blanking pixel region width */
++ hblank = fb_mode.left_margin + fb_mode.right_margin +
++ fb_mode.hsync_len;
++ hdmi_writeb(hblank >> 8, HDMI_FC_INHBLANK1);
++ hdmi_writeb(hblank, HDMI_FC_INHBLANK0);
++
++ /* Set up vertical blanking pixel region width */
++ vblank = fb_mode.upper_margin + fb_mode.lower_margin +
++ fb_mode.vsync_len;
++ hdmi_writeb(vblank, HDMI_FC_INVBLANK);
++
++ /* Set up HSYNC active edge delay width (in pixel clks) */
++ hdmi_writeb(fb_mode.right_margin >> 8, HDMI_FC_HSYNCINDELAY1);
++ hdmi_writeb(fb_mode.right_margin, HDMI_FC_HSYNCINDELAY0);
++
++ /* Set up VSYNC active edge delay (in pixel clks) */
++ hdmi_writeb(fb_mode.lower_margin, HDMI_FC_VSYNCINDELAY);
++
++ /* Set up HSYNC active pulse width (in pixel clks) */
++ hdmi_writeb(fb_mode.hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
++ hdmi_writeb(fb_mode.hsync_len, HDMI_FC_HSYNCINWIDTH0);
++
++ /* Set up VSYNC active edge delay (in pixel clks) */
++ hdmi_writeb(fb_mode.vsync_len, HDMI_FC_VSYNCINWIDTH);
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++static int mxc_edid_read_internal(struct mxc_hdmi *hdmi, unsigned char *edid,
++ struct mxc_edid_cfg *cfg, struct fb_info *fbi)
++{
++ int extblknum;
++ int i, j, ret;
++ unsigned char *ediddata = edid;
++ unsigned char tmpedid[EDID_LENGTH];
++
++ dev_info(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (!edid || !cfg || !fbi)
++ return -EINVAL;
++
++ /* init HDMI I2CM for read edid*/
++ hdmi_writeb(0x0, HDMI_I2CM_DIV);
++ hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
++ hdmi_writeb(0x79, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
++ hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
++ hdmi_writeb(0x91, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
++
++ hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_HCNT_1_ADDR);
++ hdmi_writeb(0x0F, HDMI_I2CM_FS_SCL_HCNT_0_ADDR);
++ hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_LCNT_1_ADDR);
++ hdmi_writeb(0x21, HDMI_I2CM_FS_SCL_LCNT_0_ADDR);
++
++ hdmi_writeb(0x50, HDMI_I2CM_SLAVE);
++ hdmi_writeb(0x30, HDMI_I2CM_SEGADDR);
++
++ /* Umask edid interrupt */
++ hdmi_writeb(HDMI_I2CM_INT_DONE_POL,
++ HDMI_I2CM_INT);
++
++ hdmi_writeb(HDMI_I2CM_CTLINT_NAC_POL |
++ HDMI_I2CM_CTLINT_ARBITRATION_POL,
++ HDMI_I2CM_CTLINT);
++
++ /* reset edid data zero */
++ memset(edid, 0, EDID_LENGTH*4);
++ memset(cfg, 0, sizeof(struct mxc_edid_cfg));
++
++ /* Check first three byte of EDID head */
++ if (!(hdmi_edid_i2c_read(hdmi, 0, 0) == 0x00) ||
++ !(hdmi_edid_i2c_read(hdmi, 1, 0) == 0xFF) ||
++ !(hdmi_edid_i2c_read(hdmi, 2, 0) == 0xFF)) {
++ dev_info(&hdmi->pdev->dev, "EDID head check failed!");
++ return -ENOENT;
++ }
++
++ for (i = 0; i < 128; i++) {
++ *ediddata = hdmi_edid_i2c_read(hdmi, i, 0);
++ ediddata++;
++ }
++
++ extblknum = edid[0x7E];
++ if (extblknum < 0)
++ return extblknum;
++
++ if (extblknum) {
++ ediddata = edid + EDID_LENGTH;
++ for (i = 0; i < 128; i++) {
++ *ediddata = hdmi_edid_i2c_read(hdmi, i, 1);
++ ediddata++;
++ }
++ }
++
++ /* edid first block parsing */
++ memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
++ fb_edid_to_monspecs(edid, &fbi->monspecs);
++
++ ret = mxc_edid_parse_ext_blk(edid + EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ if (ret < 0) {
++ fb_edid_add_monspecs(edid + EDID_LENGTH, &fbi->monspecs);
++ if (fbi->monspecs.modedb_len > 0)
++ hdmi->edid_cfg.hdmi_cap = false;
++ else
++ return -ENOENT;
++ }
++
++ /* need read segment block? */
++ if (extblknum > 1) {
++ for (j = 1; j <= extblknum; j++) {
++ for (i = 0; i < 128; i++)
++ *(tmpedid + 1) = hdmi_edid_i2c_read(hdmi, i, j);
++
++ /* edid ext block parsing */
++ ret = mxc_edid_parse_ext_blk(tmpedid + EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ if (ret < 0)
++ return -ENOENT;
++ }
++ }
++
++ return 0;
++}
++
++static int mxc_hdmi_read_edid(struct mxc_hdmi *hdmi)
++{
++ int ret;
++ u8 edid_old[HDMI_EDID_LEN];
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* save old edid */
++ memcpy(edid_old, hdmi->edid, HDMI_EDID_LEN);
++
++ /* Read EDID via HDMI DDC when HDCP Enable */
++ if (!hdcp_init)
++ ret = mxc_edid_read(hdmi_i2c->adapter, hdmi_i2c->addr,
++ hdmi->edid, &hdmi->edid_cfg, hdmi->fbi);
++ else {
++
++ /* Disable HDCP clk */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++
++ ret = mxc_edid_read_internal(hdmi, hdmi->edid,
++ &hdmi->edid_cfg, hdmi->fbi);
++
++ /* Enable HDCP clk */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis &= ~HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++
++ }
++ if (ret < 0)
++ return HDMI_EDID_FAIL;
++
++ /* Save edid cfg for audio driver */
++ hdmi_set_edid_cfg(&hdmi->edid_cfg);
++
++ if (!memcmp(edid_old, hdmi->edid, HDMI_EDID_LEN)) {
++ dev_info(&hdmi->pdev->dev, "same edid\n");
++ return HDMI_EDID_SAME;
++ }
++
++ if (hdmi->fbi->monspecs.modedb_len == 0) {
++ dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
++ return HDMI_EDID_NO_MODES;
++ }
++
++ return HDMI_EDID_SUCCESS;
++}
++
++static void mxc_hdmi_phy_disable(struct mxc_hdmi *hdmi)
++{
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (!hdmi->phy_enabled)
++ return;
++
++ hdmi_disable_overflow_interrupts();
++
++ /* Setting PHY to reset status */
++ hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
++
++ /* Power down PHY */
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_power(0);
++ mxc_hdmi_phy_gen2_txpwron(0);
++ mxc_hdmi_phy_gen2_pddq(1);
++
++ hdmi->phy_enabled = false;
++ dev_dbg(&hdmi->pdev->dev, "%s - exit\n", __func__);
++}
++
++/* HDMI Initialization Step B.4 */
++static void mxc_hdmi_enable_video_path(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* control period minimum duration */
++ hdmi_writeb(12, HDMI_FC_CTRLDUR);
++ hdmi_writeb(32, HDMI_FC_EXCTRLDUR);
++ hdmi_writeb(1, HDMI_FC_EXCTRLSPAC);
++
++ /* Set to fill TMDS data channels */
++ hdmi_writeb(0x0B, HDMI_FC_CH0PREAM);
++ hdmi_writeb(0x16, HDMI_FC_CH1PREAM);
++ hdmi_writeb(0x21, HDMI_FC_CH2PREAM);
++
++ /* Save CEC clock */
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ clkdis |= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++
++ /* Enable pixel clock and tmds data path */
++ clkdis = 0x7F & clkdis;
++ clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++
++ clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++
++ /* Enable csc path */
++ if (isColorSpaceConversion(hdmi)) {
++ clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++}
++
++static void hdmi_enable_audio_clk(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++}
++
++/* Workaround to clear the overflow condition */
++static void mxc_hdmi_clear_overflow(struct mxc_hdmi *hdmi)
++{
++ int count;
++ u8 val;
++
++ /* TMDS software reset */
++ hdmi_writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
++
++ val = hdmi_readb(HDMI_FC_INVIDCONF);
++
++ if (cpu_is_imx6dl(hdmi)) {
++ hdmi_writeb(val, HDMI_FC_INVIDCONF);
++ return;
++ }
++
++ for (count = 0 ; count < 5 ; count++)
++ hdmi_writeb(val, HDMI_FC_INVIDCONF);
++}
++
++static void hdmi_enable_overflow_interrupts(void)
++{
++ pr_debug("%s\n", __func__);
++ hdmi_writeb(0, HDMI_FC_MASK2);
++ hdmi_writeb(0, HDMI_IH_MUTE_FC_STAT2);
++}
++
++static void hdmi_disable_overflow_interrupts(void)
++{
++ pr_debug("%s\n", __func__);
++ hdmi_writeb(HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
++ HDMI_IH_MUTE_FC_STAT2);
++ hdmi_writeb(0xff, HDMI_FC_MASK2);
++}
++
++static void mxc_hdmi_notify_fb(struct mxc_hdmi *hdmi)
++{
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Don't notify if we aren't registered yet */
++ WARN_ON(!hdmi->fb_reg);
++
++ /* disable the phy before ipu changes mode */
++ mxc_hdmi_phy_disable(hdmi);
++
++ /*
++ * Note that fb_set_var will block. During this time,
++ * FB_EVENT_MODE_CHANGE callback will happen.
++ * So by the end of this function, mxc_hdmi_setup()
++ * will be done.
++ */
++ hdmi->fbi->var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ hdmi->fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_set_var(hdmi->fbi, &hdmi->fbi->var);
++ hdmi->fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
++{
++ int i;
++ struct fb_videomode *mode;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++ fb_add_videomode(&vga_mode, &hdmi->fbi->modelist);
++
++ for (i = 0; i < hdmi->fbi->monspecs.modedb_len; i++) {
++ /*
++ * We might check here if mode is supported by HDMI.
++ * We do not currently support interlaced modes.
++ * And add CEA modes in the modelist.
++ */
++ mode = &hdmi->fbi->monspecs.modedb[i];
++
++ if ((mode->vmode & FB_VMODE_INTERLACED) ||
++ (hdmi->edid_cfg.hdmi_cap &&
++ (mxc_edid_mode_to_vic(mode) == 0)))
++ continue;
++
++ dev_dbg(&hdmi->pdev->dev, "Added mode %d:", i);
++ dev_dbg(&hdmi->pdev->dev,
++ "xres = %d, yres = %d, freq = %d, vmode = %d, flag = %d\n",
++ hdmi->fbi->monspecs.modedb[i].xres,
++ hdmi->fbi->monspecs.modedb[i].yres,
++ hdmi->fbi->monspecs.modedb[i].refresh,
++ hdmi->fbi->monspecs.modedb[i].vmode,
++ hdmi->fbi->monspecs.modedb[i].flag);
++
++ fb_add_videomode(mode, &hdmi->fbi->modelist);
++ }
++
++ console_unlock();
++}
++
++static void mxc_hdmi_default_edid_cfg(struct mxc_hdmi *hdmi)
++{
++ /* Default setting HDMI working in HDMI mode */
++ hdmi->edid_cfg.hdmi_cap = true;
++}
++
++static void mxc_hdmi_default_modelist(struct mxc_hdmi *hdmi)
++{
++ u32 i;
++ const struct fb_videomode *mode;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* If not EDID data read, set up default modelist */
++ dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
++ dev_info(&hdmi->pdev->dev, "create default modelist\n");
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++
++ /*Add XGA and SXGA to default modelist */
++ fb_add_videomode(&vga_mode, &hdmi->fbi->modelist);
++ fb_add_videomode(&xga_mode, &hdmi->fbi->modelist);
++ fb_add_videomode(&sxga_mode, &hdmi->fbi->modelist);
++
++ /*Add all no interlaced CEA mode to default modelist */
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ mode = &mxc_cea_mode[i];
++ if (!(mode->vmode & FB_VMODE_INTERLACED) && (mode->xres != 0))
++ fb_add_videomode(mode, &hdmi->fbi->modelist);
++ }
++
++ console_unlock();
++}
++
++static void mxc_hdmi_set_mode_to_vga_dvi(struct mxc_hdmi *hdmi)
++{
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ hdmi_disable_overflow_interrupts();
++
++ fb_videomode_to_var(&hdmi->fbi->var, &vga_mode);
++
++ hdmi->requesting_vga_for_initialization = true;
++ mxc_hdmi_notify_fb(hdmi);
++ hdmi->requesting_vga_for_initialization = false;
++}
++
++static void mxc_hdmi_set_mode(struct mxc_hdmi *hdmi)
++{
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++ struct fb_var_screeninfo var;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Set the default mode only once. */
++ if (!hdmi->dft_mode_set) {
++ dev_dbg(&hdmi->pdev->dev, "%s: setting to default=%s bpp=%d\n",
++ __func__, hdmi->dft_mode_str, hdmi->default_bpp);
++
++ fb_find_mode(&var, hdmi->fbi,
++ hdmi->dft_mode_str, NULL, 0, NULL,
++ hdmi->default_bpp);
++
++ hdmi->dft_mode_set = true;
++ } else
++ fb_videomode_to_var(&var, &hdmi->previous_non_vga_mode);
++
++ fb_var_to_videomode(&m, &var);
++ dump_fb_videomode(&m);
++
++ mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
++ if (!mode) {
++ pr_err("%s: could not find mode in modelist\n", __func__);
++ return;
++ }
++
++ /* If video mode same as previous, init HDMI again */
++ if (fb_mode_is_equal(&hdmi->previous_non_vga_mode, mode)) {
++ dev_dbg(&hdmi->pdev->dev,
++ "%s: Video mode same as previous\n", __func__);
++ /* update fbi mode in case modelist is updated */
++ hdmi->fbi->mode = (struct fb_videomode *)mode;
++ /* update hdmi setting in case EDID data updated */
++ mxc_hdmi_setup(hdmi, 0);
++ } else {
++ dev_dbg(&hdmi->pdev->dev, "%s: New video mode\n", __func__);
++ mxc_hdmi_set_mode_to_vga_dvi(hdmi);
++ fb_videomode_to_var(&hdmi->fbi->var, mode);
++ dump_fb_videomode((struct fb_videomode *)mode);
++ mxc_hdmi_notify_fb(hdmi);
++ }
++
++}
++
++static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi)
++{
++ int edid_status;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ hdmi->cable_plugin = true;
++
++ /* HDMI Initialization Step C */
++ edid_status = mxc_hdmi_read_edid(hdmi);
++
++ /* Read EDID again if first EDID read failed */
++ if (edid_status == HDMI_EDID_NO_MODES ||
++ edid_status == HDMI_EDID_FAIL) {
++ dev_info(&hdmi->pdev->dev, "Read EDID again\n");
++ edid_status = mxc_hdmi_read_edid(hdmi);
++ }
++
++ /* HDMI Initialization Steps D, E, F */
++ switch (edid_status) {
++ case HDMI_EDID_SUCCESS:
++ mxc_hdmi_edid_rebuild_modelist(hdmi);
++ break;
++
++ /* Nothing to do if EDID same */
++ case HDMI_EDID_SAME:
++ break;
++
++ case HDMI_EDID_FAIL:
++ mxc_hdmi_default_edid_cfg(hdmi);
++ /* No break here */
++ case HDMI_EDID_NO_MODES:
++ default:
++ mxc_hdmi_default_modelist(hdmi);
++ break;
++ }
++
++ /* Setting video mode */
++ mxc_hdmi_set_mode(hdmi);
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++static int mxc_hdmi_power_on(struct mxc_dispdrv_handle *disp)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++ mxc_hdmi_phy_init(hdmi);
++ return 0;
++}
++
++static void mxc_hdmi_power_off(struct mxc_dispdrv_handle *disp)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++ mxc_hdmi_phy_disable(hdmi);
++}
++
++static void mxc_hdmi_cable_disconnected(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Save CEC clock */
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ clkdis |= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++
++ /* Disable All HDMI clock */
++ hdmi_writeb(0xff & clkdis, HDMI_MC_CLKDIS);
++
++ mxc_hdmi_phy_disable(hdmi);
++
++ hdmi_disable_overflow_interrupts();
++
++ hdmi->cable_plugin = false;
++}
++
++static void hotplug_worker(struct work_struct *work)
++{
++ struct delayed_work *delay_work = to_delayed_work(work);
++ struct mxc_hdmi *hdmi =
++ container_of(delay_work, struct mxc_hdmi, hotplug_work);
++ u32 hdmi_phy_stat0, hdmi_phy_pol0, hdmi_phy_mask0;
++ unsigned long flags;
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++
++ hdmi_phy_stat0 = hdmi_readb(HDMI_PHY_STAT0);
++ hdmi_phy_pol0 = hdmi_readb(HDMI_PHY_POL0);
++
++ dev_dbg(&hdmi->pdev->dev, "hdmi_phy_stat0=0x%x, hdmi_phy_pol0=0x%x\n",
++ hdmi_phy_stat0, hdmi_phy_pol0);
++
++ /* Make HPD intr active low to capture unplug event or
++ * active high to capture plugin event */
++ hdmi_writeb((HDMI_DVI_STAT & ~hdmi_phy_stat0), HDMI_PHY_POL0);
++
++ /* check cable status */
++ if (hdmi_phy_stat0 & HDMI_DVI_STAT) {
++ /* Plugin event */
++ dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
++ mxc_hdmi_cable_connected(hdmi);
++
++ sprintf(event_string, "EVENT=plugin");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++#ifdef CONFIG_MXC_HDMI_CEC
++ mxc_hdmi_cec_handle(0x80);
++#endif
++ hdmi_set_cable_state(1);
++
++ } else {
++ /* Plugout event */
++ dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
++ hdmi_set_cable_state(0);
++ mxc_hdmi_abort_stream();
++ mxc_hdmi_cable_disconnected(hdmi);
++
++ sprintf(event_string, "EVENT=plugout");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++#ifdef CONFIG_MXC_HDMI_CEC
++ mxc_hdmi_cec_handle(0x100);
++#endif
++
++ }
++
++ /* Lock here to ensure full powerdown sequence
++ * completed before next interrupt processed */
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ /* Re-enable HPD interrupts */
++ hdmi_phy_mask0 = hdmi_readb(HDMI_PHY_MASK0);
++ hdmi_phy_mask0 &= ~HDMI_DVI_STAT;
++ hdmi_writeb(hdmi_phy_mask0, HDMI_PHY_MASK0);
++
++ /* Unmute interrupts */
++ hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0);
++
++ if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK)
++ mxc_hdmi_clear_overflow(hdmi);
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++}
++
++static void hdcp_hdp_worker(struct work_struct *work)
++{
++ struct delayed_work *delay_work = to_delayed_work(work);
++ struct mxc_hdmi *hdmi =
++ container_of(delay_work, struct mxc_hdmi, hdcp_hdp_work);
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++
++ /* HDCP interrupt */
++ sprintf(event_string, "EVENT=hdcpint");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++
++ /* Unmute interrupts in HDCP application*/
++}
++
++static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
++{
++ struct mxc_hdmi *hdmi = data;
++ u8 val;
++ unsigned long flags;
++
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ /* Check and clean packet overflow interrupt.*/
++ if (hdmi_readb(HDMI_IH_FC_STAT2) &
++ HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
++ mxc_hdmi_clear_overflow(hdmi);
++
++ dev_dbg(&hdmi->pdev->dev, "Overflow interrupt received\n");
++ /* clear irq status */
++ hdmi_writeb(HDMI_IH_FC_STAT2_OVERFLOW_MASK,
++ HDMI_IH_FC_STAT2);
++ }
++
++ /*
++ * We could not disable the irq. Probably the audio driver
++ * has enabled it. Masking off the HDMI interrupts using
++ * HDMI registers.
++ */
++ /* Capture status - used in hotplug_worker ISR */
++ if (hdmi_readb(HDMI_IH_PHY_STAT0) & HDMI_DVI_IH_STAT) {
++
++ dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
++
++ /* Mute interrupts until handled */
++
++ val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
++ val |= HDMI_DVI_IH_STAT;
++ hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
++
++ val = hdmi_readb(HDMI_PHY_MASK0);
++ val |= HDMI_DVI_STAT;
++ hdmi_writeb(val, HDMI_PHY_MASK0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
++
++ schedule_delayed_work(&(hdmi->hotplug_work), msecs_to_jiffies(20));
++ }
++
++ /* Check HDCP interrupt state */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ val = hdmi_readb(HDMI_A_APIINTSTAT);
++ if (val != 0) {
++ /* Mute interrupts until interrupt handled */
++ val = 0xFF;
++ hdmi_writeb(val, HDMI_A_APIINTMSK);
++ schedule_delayed_work(&(hdmi->hdcp_hdp_work), msecs_to_jiffies(50));
++ }
++ }
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++ return IRQ_HANDLED;
++}
++
++static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event)
++{
++ struct fb_videomode m;
++ const struct fb_videomode *edid_mode;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_var_to_videomode(&m, &hdmi->fbi->var);
++ dump_fb_videomode(&m);
++
++ dev_dbg(&hdmi->pdev->dev, "%s - video mode changed\n", __func__);
++
++ /* Save mode as 'previous_mode' so that we can know if mode changed. */
++ memcpy(&hdmi->previous_mode, &m, sizeof(struct fb_videomode));
++
++ hdmi->vic = 0;
++ if (!hdmi->requesting_vga_for_initialization) {
++ /* Save mode if this isn't the result of requesting
++ * vga default. */
++ memcpy(&hdmi->previous_non_vga_mode, &m,
++ sizeof(struct fb_videomode));
++ if (!list_empty(&hdmi->fbi->modelist)) {
++ edid_mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
++ pr_debug("edid mode ");
++ dump_fb_videomode((struct fb_videomode *)edid_mode);
++ hdmi->vic = mxc_edid_mode_to_vic(edid_mode);
++ }
++ }
++
++ hdmi_disable_overflow_interrupts();
++
++ dev_dbg(&hdmi->pdev->dev, "CEA mode used vic=%d\n", hdmi->vic);
++ if (hdmi->edid_cfg.hdmi_cap)
++ hdmi->hdmi_data.video_mode.mDVI = false;
++ else {
++ dev_dbg(&hdmi->pdev->dev, "CEA mode vic=%d work in DVI\n", hdmi->vic);
++ hdmi->hdmi_data.video_mode.mDVI = true;
++ }
++
++ if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
++ (hdmi->vic == 21) || (hdmi->vic == 22) ||
++ (hdmi->vic == 2) || (hdmi->vic == 3) ||
++ (hdmi->vic == 17) || (hdmi->vic == 18))
++ hdmi->hdmi_data.colorimetry = eITU601;
++ else
++ hdmi->hdmi_data.colorimetry = eITU709;
++
++ if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
++ (hdmi->vic == 12) || (hdmi->vic == 13) ||
++ (hdmi->vic == 14) || (hdmi->vic == 15) ||
++ (hdmi->vic == 25) || (hdmi->vic == 26) ||
++ (hdmi->vic == 27) || (hdmi->vic == 28) ||
++ (hdmi->vic == 29) || (hdmi->vic == 30) ||
++ (hdmi->vic == 35) || (hdmi->vic == 36) ||
++ (hdmi->vic == 37) || (hdmi->vic == 38))
++ hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 1;
++ else
++ hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 0;
++
++ hdmi->hdmi_data.video_mode.mPixelRepetitionInput = 0;
++
++ /* TODO: Get input format from IPU (via FB driver iface) */
++ hdmi->hdmi_data.enc_in_format = RGB;
++
++ hdmi->hdmi_data.enc_out_format = RGB;
++
++ /* YCbCr only enabled in HDMI mode */
++ if (!hdmi->hdmi_data.video_mode.mDVI &&
++ !hdmi->hdmi_data.rgb_out_enable) {
++ if (hdmi->edid_cfg.cea_ycbcr444)
++ hdmi->hdmi_data.enc_out_format = YCBCR444;
++ else if (hdmi->edid_cfg.cea_ycbcr422)
++ hdmi->hdmi_data.enc_out_format = YCBCR422_8BITS;
++ }
++
++ /* IPU not support depth color output */
++ hdmi->hdmi_data.enc_color_depth = 8;
++ hdmi->hdmi_data.pix_repet_factor = 0;
++ hdmi->hdmi_data.video_mode.mDataEnablePolarity = true;
++
++ /* HDMI Initialization Step B.1 */
++ hdmi_av_composer(hdmi);
++
++ /* HDMI Initializateion Step B.2 */
++ mxc_hdmi_phy_init(hdmi);
++
++ /* HDMI Initialization Step B.3 */
++ mxc_hdmi_enable_video_path(hdmi);
++
++ /* not for DVI mode */
++ if (hdmi->hdmi_data.video_mode.mDVI)
++ dev_dbg(&hdmi->pdev->dev, "%s DVI mode\n", __func__);
++ else {
++ dev_dbg(&hdmi->pdev->dev, "%s CEA mode\n", __func__);
++
++ /* HDMI Initialization Step E - Configure audio */
++ hdmi_clk_regenerator_update_pixel_clock(hdmi->fbi->var.pixclock);
++ hdmi_enable_audio_clk(hdmi);
++
++ /* HDMI Initialization Step F - Configure AVI InfoFrame */
++ hdmi_config_AVI(hdmi);
++ }
++
++ hdmi_video_packetize(hdmi);
++ hdmi_video_csc(hdmi);
++ hdmi_video_sample(hdmi);
++
++ mxc_hdmi_clear_overflow(hdmi);
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n\n", __func__);
++
++}
++
++/* Wait until we are registered to enable interrupts */
++static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi)
++{
++ unsigned long flags;
++
++ if (hdmi->fb_reg)
++ return;
++
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ hdmi_writeb(HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
++ HDMI_PHY_I2CM_INT_ADDR);
++
++ hdmi_writeb(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
++ HDMI_PHY_I2CM_CTLINT_ADDR);
++
++ /* enable cable hot plug irq */
++ hdmi_writeb((u8)~HDMI_DVI_STAT, HDMI_PHY_MASK0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
++
++ /* Unmute interrupts */
++ hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0);
++
++ hdmi->fb_reg = true;
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++
++}
++
++static int mxc_hdmi_fb_event(struct notifier_block *nb,
++ unsigned long val, void *v)
++{
++ struct fb_event *event = v;
++ struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb);
++
++ if (strcmp(event->info->fix.id, hdmi->fbi->fix.id))
++ return 0;
++
++ switch (val) {
++ case FB_EVENT_FB_REGISTERED:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_REGISTERED\n");
++ mxc_hdmi_fb_registered(hdmi);
++ hdmi_set_registered(1);
++ break;
++
++ case FB_EVENT_FB_UNREGISTERED:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_UNREGISTERED\n");
++ hdmi->fb_reg = false;
++ hdmi_set_registered(0);
++ break;
++
++ case FB_EVENT_MODE_CHANGE:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_MODE_CHANGE\n");
++ if (hdmi->fb_reg)
++ mxc_hdmi_setup(hdmi, val);
++ break;
++
++ case FB_EVENT_BLANK:
++ if ((*((int *)event->data) == FB_BLANK_UNBLANK) &&
++ (*((int *)event->data) != hdmi->blank)) {
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_BLANK - UNBLANK\n");
++
++ hdmi->blank = *((int *)event->data);
++
++ if (hdmi->fb_reg && hdmi->cable_plugin)
++ mxc_hdmi_setup(hdmi, val);
++ hdmi_set_blank_state(1);
++
++ } else if (*((int *)event->data) != hdmi->blank) {
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_BLANK - BLANK\n");
++ hdmi_set_blank_state(0);
++ mxc_hdmi_abort_stream();
++
++ mxc_hdmi_phy_disable(hdmi);
++
++ hdmi->blank = *((int *)event->data);
++ } else
++ dev_dbg(&hdmi->pdev->dev,
++ "FB BLANK state no changed!\n");
++
++ break;
++
++ case FB_EVENT_SUSPEND:
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_SUSPEND\n");
++
++ if (hdmi->blank == FB_BLANK_UNBLANK) {
++ mxc_hdmi_phy_disable(hdmi);
++ clk_disable(hdmi->hdmi_iahb_clk);
++ clk_disable(hdmi->hdmi_isfr_clk);
++ }
++ break;
++
++ case FB_EVENT_RESUME:
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_RESUME\n");
++
++ if (hdmi->blank == FB_BLANK_UNBLANK) {
++ clk_enable(hdmi->hdmi_iahb_clk);
++ clk_enable(hdmi->hdmi_isfr_clk);
++ mxc_hdmi_phy_init(hdmi);
++ }
++ break;
++
++ }
++ return 0;
++}
++
++static void hdmi_init_route(struct mxc_hdmi *hdmi)
++{
++ uint32_t hdmi_mux_setting, reg;
++ int ipu_id, disp_id;
++
++ ipu_id = mxc_hdmi_ipu_id;
++ disp_id = mxc_hdmi_disp_id;
++
++ if ((ipu_id > 1) || (ipu_id < 0)) {
++ pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
++ ipu_id = 0;
++ }
++
++ if ((disp_id > 1) || (disp_id < 0)) {
++ pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
++ disp_id = 0;
++ }
++
++ reg = readl(hdmi->gpr_hdmi_base);
++
++ /* Configure the connection between IPU1/2 and HDMI */
++ hdmi_mux_setting = 2*ipu_id + disp_id;
++
++ /* GPR3, bits 2-3 = HDMI_MUX_CTL */
++ reg &= ~0xd;
++ reg |= hdmi_mux_setting << 2;
++
++ writel(reg, hdmi->gpr_hdmi_base);
++
++ /* Set HDMI event as SDMA event2 for HDMI audio */
++ reg = readl(hdmi->gpr_sdma_base);
++ reg |= 0x1;
++ writel(reg, hdmi->gpr_sdma_base);
++}
++
++static void hdmi_hdcp_get_property(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++
++ /* Check hdcp enable by dts.*/
++ hdcp_init = of_property_read_bool(np, "fsl,hdcp");
++ if (hdcp_init)
++ dev_dbg(&pdev->dev, "hdcp enable\n");
++ else
++ dev_dbg(&pdev->dev, "hdcp disable\n");
++}
++
++static void hdmi_get_of_property(struct mxc_hdmi *hdmi)
++{
++ struct platform_device *pdev = hdmi->pdev;
++ struct device_node *np = pdev->dev.of_node;
++ const struct of_device_id *of_id =
++ of_match_device(imx_hdmi_dt_ids, &pdev->dev);
++ int ret;
++ u32 phy_reg_vlev = 0, phy_reg_cksymtx = 0;
++
++ if (of_id) {
++ pdev->id_entry = of_id->data;
++ hdmi->cpu_type = pdev->id_entry->driver_data;
++ }
++
++ /* HDMI PHY register vlev and cksymtx preperty is optional.
++ * It is for specific board to pass HCT electrical part.
++ * Default value will been setting in HDMI PHY config function
++ * if it is not define in device tree.
++ */
++ ret = of_property_read_u32(np, "fsl,phy_reg_vlev", &phy_reg_vlev);
++ if (ret)
++ dev_dbg(&pdev->dev, "No board specific HDMI PHY vlev\n");
++
++ ret = of_property_read_u32(np, "fsl,phy_reg_cksymtx", &phy_reg_cksymtx);
++ if (ret)
++ dev_dbg(&pdev->dev, "No board specific HDMI PHY cksymtx\n");
++
++ /* Specific phy config */
++ hdmi->phy_config.reg_cksymtx = phy_reg_cksymtx;
++ hdmi->phy_config.reg_vlev = phy_reg_vlev;
++
++}
++
++/* HDMI Initialization Step A */
++static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret = 0;
++ u32 i;
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++ int irq = platform_get_irq(hdmi->pdev, 0);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Check hdmi disp init once */
++ if (hdmi_inited) {
++ dev_err(&hdmi->pdev->dev,
++ "Error only one HDMI output support now!\n");
++ return -1;
++ }
++
++ hdmi_get_of_property(hdmi);
++
++ if (irq < 0)
++ return -ENODEV;
++
++ hdmi->dft_mode_set = false;
++
++ /* Setting HDMI default to blank state */
++ hdmi->blank = FB_BLANK_POWERDOWN;
++
++ setting->dev_id = mxc_hdmi_ipu_id;
++ setting->disp_id = mxc_hdmi_disp_id;
++ setting->if_fmt = IPU_PIX_FMT_RGB24;
++
++ hdmi->dft_mode_str = setting->dft_mode_str;
++ hdmi->default_bpp = setting->default_bpp;
++ dev_dbg(&hdmi->pdev->dev, "%s - default mode %s bpp=%d\n",
++ __func__, hdmi->dft_mode_str, hdmi->default_bpp);
++
++ hdmi->fbi = setting->fbi;
++
++ hdmi_init_route(hdmi);
++
++ hdmi->hdmi_isfr_clk = clk_get(&hdmi->pdev->dev, "hdmi_isfr");
++ if (IS_ERR(hdmi->hdmi_isfr_clk)) {
++ ret = PTR_ERR(hdmi->hdmi_isfr_clk);
++ dev_err(&hdmi->pdev->dev,
++ "Unable to get HDMI clk: %d\n", ret);
++ goto egetclk1;
++ }
++
++ ret = clk_prepare_enable(hdmi->hdmi_isfr_clk);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Cannot enable HDMI isfr clock: %d\n", ret);
++ goto erate1;
++ }
++
++ hdmi->hdmi_iahb_clk = clk_get(&hdmi->pdev->dev, "hdmi_iahb");
++ if (IS_ERR(hdmi->hdmi_iahb_clk)) {
++ ret = PTR_ERR(hdmi->hdmi_iahb_clk);
++ dev_err(&hdmi->pdev->dev,
++ "Unable to get HDMI clk: %d\n", ret);
++ goto egetclk2;
++ }
++
++ ret = clk_prepare_enable(hdmi->hdmi_iahb_clk);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Cannot enable HDMI iahb clock: %d\n", ret);
++ goto erate2;
++ }
++
++ dev_dbg(&hdmi->pdev->dev, "Enabled HDMI clocks\n");
++
++ /* Init DDC pins for HDCP */
++ if (hdcp_init) {
++ hdmi->pinctrl = devm_pinctrl_get_select_default(&hdmi->pdev->dev);
++ if (IS_ERR(hdmi->pinctrl)) {
++ dev_err(&hdmi->pdev->dev, "can't get/select DDC pinctrl\n");
++ goto erate2;
++ }
++ }
++
++ /* Product and revision IDs */
++ dev_info(&hdmi->pdev->dev,
++ "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
++ hdmi_readb(HDMI_DESIGN_ID),
++ hdmi_readb(HDMI_REVISION_ID),
++ hdmi_readb(HDMI_PRODUCT_ID0),
++ hdmi_readb(HDMI_PRODUCT_ID1));
++
++ /* To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
++ * N and cts values before enabling phy */
++ hdmi_init_clk_regenerator();
++
++ INIT_LIST_HEAD(&hdmi->fbi->modelist);
++
++ spin_lock_init(&hdmi->irq_lock);
++
++ /* Set the default mode and modelist when disp init. */
++ fb_find_mode(&hdmi->fbi->var, hdmi->fbi,
++ hdmi->dft_mode_str, NULL, 0, NULL,
++ hdmi->default_bpp);
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++
++ /*Add all no interlaced CEA mode to default modelist */
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ mode = &mxc_cea_mode[i];
++ if (!(mode->vmode & FB_VMODE_INTERLACED) && (mode->xres != 0))
++ fb_add_videomode(mode, &hdmi->fbi->modelist);
++ }
++
++ /*Add XGA and SXGA to default modelist */
++ fb_add_videomode(&xga_mode, &hdmi->fbi->modelist);
++ fb_add_videomode(&sxga_mode, &hdmi->fbi->modelist);
++
++ console_unlock();
++
++ /* Find a nearest mode in default modelist */
++ fb_var_to_videomode(&m, &hdmi->fbi->var);
++ dump_fb_videomode(&m);
++
++ mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
++ if (!mode) {
++ pr_err("%s: could not find mode in modelist\n", __func__);
++ return -1;
++ }
++
++ fb_videomode_to_var(&hdmi->fbi->var, mode);
++
++ /* Default setting HDMI working in HDMI mode*/
++ hdmi->edid_cfg.hdmi_cap = true;
++
++ INIT_DELAYED_WORK(&hdmi->hotplug_work, hotplug_worker);
++ INIT_DELAYED_WORK(&hdmi->hdcp_hdp_work, hdcp_hdp_worker);
++
++ /* Configure registers related to HDMI interrupt
++ * generation before registering IRQ. */
++ hdmi_writeb(HDMI_DVI_STAT, HDMI_PHY_POL0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
++
++ hdmi->nb.notifier_call = mxc_hdmi_fb_event;
++ ret = fb_register_client(&hdmi->nb);
++ if (ret < 0)
++ goto efbclient;
++
++ memset(&hdmi->hdmi_data, 0, sizeof(struct hdmi_data_info));
++
++ /* Default HDMI working in RGB mode */
++ hdmi->hdmi_data.rgb_out_enable = true;
++
++ ret = devm_request_irq(&hdmi->pdev->dev, irq, mxc_hdmi_hotplug, IRQF_SHARED,
++ dev_name(&hdmi->pdev->dev), hdmi);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Unable to request irq: %d\n", ret);
++ goto ereqirq;
++ }
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_fb_name);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for fb name\n");
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_cable_state);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for cable state\n");
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_edid);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for edid\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_rgb_out_enable);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for rgb out enable\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_hdcp_enable);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for hdcp enable\n");
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++
++ hdmi_inited = true;
++
++ return ret;
++
++efbclient:
++ free_irq(irq, hdmi);
++ereqirq:
++ clk_disable_unprepare(hdmi->hdmi_iahb_clk);
++erate2:
++ clk_put(hdmi->hdmi_iahb_clk);
++egetclk2:
++ clk_disable_unprepare(hdmi->hdmi_isfr_clk);
++erate1:
++ clk_put(hdmi->hdmi_isfr_clk);
++egetclk1:
++ dev_dbg(&hdmi->pdev->dev, "%s error exit\n", __func__);
++
++ return ret;
++}
++
++static void mxc_hdmi_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_unregister_client(&hdmi->nb);
++
++ clk_disable_unprepare(hdmi->hdmi_isfr_clk);
++ clk_put(hdmi->hdmi_isfr_clk);
++ clk_disable_unprepare(hdmi->hdmi_iahb_clk);
++ clk_put(hdmi->hdmi_iahb_clk);
++
++ platform_device_unregister(hdmi->pdev);
++
++ hdmi_inited = false;
++}
++
++static struct mxc_dispdrv_driver mxc_hdmi_drv = {
++ .name = DISPDRV_HDMI,
++ .init = mxc_hdmi_disp_init,
++ .deinit = mxc_hdmi_disp_deinit,
++ .enable = mxc_hdmi_power_on,
++ .disable = mxc_hdmi_power_off,
++};
++
++
++static int mxc_hdmi_open(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++static long mxc_hdmi_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int __user *argp = (void __user *)arg;
++ int ret = 0;
++
++ switch (cmd) {
++ case HDMI_IOC_GET_RESOURCE:
++ ret = copy_to_user(argp, &g_hdmi->hdmi_data,
++ sizeof(g_hdmi->hdmi_data)) ? -EFAULT : 0;
++ break;
++ case HDMI_IOC_GET_CPU_TYPE:
++ *argp = g_hdmi->cpu_type;
++ break;
++ default:
++ pr_debug("Unsupport cmd %d\n", cmd);
++ break;
++ }
++ return ret;
++}
++
++static int mxc_hdmi_release(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++static const struct file_operations mxc_hdmi_fops = {
++ .owner = THIS_MODULE,
++ .open = mxc_hdmi_open,
++ .release = mxc_hdmi_release,
++ .unlocked_ioctl = mxc_hdmi_ioctl,
++};
++
++
++static int mxc_hdmi_probe(struct platform_device *pdev)
++{
++ struct mxc_hdmi *hdmi;
++ struct device *temp_class;
++ struct resource *res;
++ int ret = 0;
++
++ /* Check I2C driver is loaded and available
++ * check hdcp function is enable by dts */
++ hdmi_hdcp_get_property(pdev);
++ if (!hdmi_i2c && !hdcp_init)
++ return -ENODEV;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENOENT;
++
++ hdmi = devm_kzalloc(&pdev->dev,
++ sizeof(struct mxc_hdmi),
++ GFP_KERNEL);
++ if (!hdmi) {
++ dev_err(&pdev->dev, "Cannot allocate device data\n");
++ ret = -ENOMEM;
++ goto ealloc;
++ }
++ g_hdmi = hdmi;
++
++ hdmi_major = register_chrdev(hdmi_major, "mxc_hdmi", &mxc_hdmi_fops);
++ if (hdmi_major < 0) {
++ printk(KERN_ERR "HDMI: unable to get a major for HDMI\n");
++ ret = -EBUSY;
++ goto ealloc;
++ }
++
++ hdmi_class = class_create(THIS_MODULE, "mxc_hdmi");
++ if (IS_ERR(hdmi_class)) {
++ ret = PTR_ERR(hdmi_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(hdmi_class, NULL, MKDEV(hdmi_major, 0),
++ NULL, "mxc_hdmi");
++ if (IS_ERR(temp_class)) {
++ ret = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ hdmi->pdev = pdev;
++
++ hdmi->core_pdev = platform_device_alloc("mxc_hdmi_core", -1);
++ if (!hdmi->core_pdev) {
++ pr_err("%s failed platform_device_alloc for hdmi core\n",
++ __func__);
++ ret = -ENOMEM;
++ goto ecore;
++ }
++
++ hdmi->gpr_base = ioremap(res->start, resource_size(res));
++ if (!hdmi->gpr_base) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto eiomap;
++ }
++
++ hdmi->gpr_hdmi_base = hdmi->gpr_base + 3;
++ hdmi->gpr_sdma_base = hdmi->gpr_base;
++
++ hdmi_inited = false;
++
++ hdmi->disp_mxc_hdmi = mxc_dispdrv_register(&mxc_hdmi_drv);
++ if (IS_ERR(hdmi->disp_mxc_hdmi)) {
++ dev_err(&pdev->dev, "Failed to register dispdrv - 0x%x\n",
++ (int)hdmi->disp_mxc_hdmi);
++ ret = (int)hdmi->disp_mxc_hdmi;
++ goto edispdrv;
++ }
++ mxc_dispdrv_setdata(hdmi->disp_mxc_hdmi, hdmi);
++
++ platform_set_drvdata(pdev, hdmi);
++
++ return 0;
++edispdrv:
++ iounmap(hdmi->gpr_base);
++eiomap:
++ platform_device_put(hdmi->core_pdev);
++ecore:
++ kfree(hdmi);
++err_out_class:
++ device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
++ class_destroy(hdmi_class);
++err_out_chrdev:
++ unregister_chrdev(hdmi_major, "mxc_hdmi");
++ealloc:
++ return ret;
++}
++
++static int mxc_hdmi_remove(struct platform_device *pdev)
++{
++ struct mxc_hdmi *hdmi = platform_get_drvdata(pdev);
++ int irq = platform_get_irq(pdev, 0);
++
++ fb_unregister_client(&hdmi->nb);
++
++ mxc_dispdrv_puthandle(hdmi->disp_mxc_hdmi);
++ mxc_dispdrv_unregister(hdmi->disp_mxc_hdmi);
++ iounmap(hdmi->gpr_base);
++ /* No new work will be scheduled, wait for running ISR */
++ free_irq(irq, hdmi);
++ kfree(hdmi);
++ g_hdmi = NULL;
++
++ return 0;
++}
++
++static struct platform_driver mxc_hdmi_driver = {
++ .probe = mxc_hdmi_probe,
++ .remove = mxc_hdmi_remove,
++ .driver = {
++ .name = "mxc_hdmi",
++ .of_match_table = imx_hdmi_dt_ids,
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init mxc_hdmi_init(void)
++{
++ return platform_driver_register(&mxc_hdmi_driver);
++}
++module_init(mxc_hdmi_init);
++
++static void __exit mxc_hdmi_exit(void)
++{
++ if (hdmi_major > 0) {
++ device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
++ class_destroy(hdmi_class);
++ unregister_chrdev(hdmi_major, "mxc_hdmi");
++ hdmi_major = 0;
++ }
++
++ platform_driver_unregister(&mxc_hdmi_driver);
++}
++module_exit(mxc_hdmi_exit);
++
++static int mxc_hdmi_i2c_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ if (!i2c_check_functionality(client->adapter,
++ I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
++ return -ENODEV;
++
++ hdmi_i2c = client;
++
++ return 0;
++}
++
++static int mxc_hdmi_i2c_remove(struct i2c_client *client)
++{
++ hdmi_i2c = NULL;
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_i2c_match[] = {
++ { .compatible = "fsl,imx6-hdmi-i2c", },
++ { /* sentinel */ }
++};
++
++static const struct i2c_device_id mxc_hdmi_i2c_id[] = {
++ { "mxc_hdmi_i2c", 0 },
++ {},
++};
++MODULE_DEVICE_TABLE(i2c, mxc_hdmi_i2c_id);
++
++static struct i2c_driver mxc_hdmi_i2c_driver = {
++ .driver = {
++ .name = "mxc_hdmi_i2c",
++ .of_match_table = imx_hdmi_i2c_match,
++ },
++ .probe = mxc_hdmi_i2c_probe,
++ .remove = mxc_hdmi_i2c_remove,
++ .id_table = mxc_hdmi_i2c_id,
++};
++
++static int __init mxc_hdmi_i2c_init(void)
++{
++ return i2c_add_driver(&mxc_hdmi_i2c_driver);
++}
++
++static void __exit mxc_hdmi_i2c_exit(void)
++{
++ i2c_del_driver(&mxc_hdmi_i2c_driver);
++}
++
++module_init(mxc_hdmi_i2c_init);
++module_exit(mxc_hdmi_i2c_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxc_ipuv3_fb.c linux-linaro-stable-mx6/drivers/video/mxc/mxc_ipuv3_fb.c
+--- linux-3.10.30.orig/drivers/video/mxc/mxc_ipuv3_fb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxc_ipuv3_fb.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,2577 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxcfb.c
++ *
++ * @brief MXC Frame buffer driver for SDC
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/errno.h>
++#include <linux/fb.h>
++#include <linux/fsl_devices.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/ipu.h>
++#include <linux/ipu-v3.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/uaccess.h>
++
++#include "mxc_dispdrv.h"
++
++/*
++ * Driver name
++ */
++#define MXCFB_NAME "mxc_sdc_fb"
++
++/* Display port number */
++#define MXCFB_PORT_NUM 2
++/*!
++ * Structure containing the MXC specific framebuffer information.
++ */
++struct mxcfb_info {
++ int default_bpp;
++ int cur_blank;
++ int next_blank;
++ ipu_channel_t ipu_ch;
++ int ipu_id;
++ int ipu_di;
++ u32 ipu_di_pix_fmt;
++ bool ipu_int_clk;
++ bool overlay;
++ bool alpha_chan_en;
++ bool late_init;
++ bool first_set_par;
++ dma_addr_t alpha_phy_addr0;
++ dma_addr_t alpha_phy_addr1;
++ void *alpha_virt_addr0;
++ void *alpha_virt_addr1;
++ uint32_t alpha_mem_len;
++ uint32_t ipu_ch_irq;
++ uint32_t ipu_ch_nf_irq;
++ uint32_t ipu_alp_ch_irq;
++ uint32_t cur_ipu_buf;
++ uint32_t cur_ipu_alpha_buf;
++
++ u32 pseudo_palette[16];
++
++ bool mode_found;
++ struct completion flip_complete;
++ struct completion alpha_flip_complete;
++ struct completion vsync_complete;
++
++ void *ipu;
++ struct fb_info *ovfbi;
++
++ struct mxc_dispdrv_handle *dispdrv;
++
++ struct fb_var_screeninfo cur_var;
++};
++
++struct mxcfb_pfmt {
++ u32 fb_pix_fmt;
++ int bpp;
++ struct fb_bitfield red;
++ struct fb_bitfield green;
++ struct fb_bitfield blue;
++ struct fb_bitfield transp;
++};
++
++static const struct mxcfb_pfmt mxcfb_pfmts[] = {
++ /* pixel bpp red green blue transp */
++ {IPU_PIX_FMT_RGB565, 16, {11, 5, 0}, { 5, 6, 0}, { 0, 5, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_RGB24, 24, { 0, 8, 0}, { 8, 8, 0}, {16, 8, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_BGR24, 24, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_RGB32, 32, { 0, 8, 0}, { 8, 8, 0}, {16, 8, 0}, {24, 8, 0} },
++ {IPU_PIX_FMT_BGR32, 32, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, {24, 8, 0} },
++ {IPU_PIX_FMT_ABGR32, 32, {24, 8, 0}, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0} },
++};
++
++struct mxcfb_alloc_list {
++ struct list_head list;
++ dma_addr_t phy_addr;
++ void *cpu_addr;
++ u32 size;
++};
++
++enum {
++ BOTH_ON,
++ SRC_ON,
++ TGT_ON,
++ BOTH_OFF
++};
++
++static bool g_dp_in_use[2];
++LIST_HEAD(fb_alloc_list);
++
++/* Return default standard(RGB) pixel format */
++static uint32_t bpp_to_pixfmt(int bpp)
++{
++ uint32_t pixfmt = 0;
++
++ switch (bpp) {
++ case 24:
++ pixfmt = IPU_PIX_FMT_BGR24;
++ break;
++ case 32:
++ pixfmt = IPU_PIX_FMT_BGR32;
++ break;
++ case 16:
++ pixfmt = IPU_PIX_FMT_RGB565;
++ break;
++ }
++ return pixfmt;
++}
++
++static inline int bitfield_is_equal(struct fb_bitfield f1,
++ struct fb_bitfield f2)
++{
++ return !memcmp(&f1, &f2, sizeof(f1));
++}
++
++static int pixfmt_to_var(uint32_t pixfmt, struct fb_var_screeninfo *var)
++{
++ int i, ret = -1;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (pixfmt == mxcfb_pfmts[i].fb_pix_fmt) {
++ var->red = mxcfb_pfmts[i].red;
++ var->green = mxcfb_pfmts[i].green;
++ var->blue = mxcfb_pfmts[i].blue;
++ var->transp = mxcfb_pfmts[i].transp;
++ var->bits_per_pixel = mxcfb_pfmts[i].bpp;
++ ret = 0;
++ break;
++ }
++ }
++ return ret;
++}
++
++static int bpp_to_var(int bpp, struct fb_var_screeninfo *var)
++{
++ uint32_t pixfmt = 0;
++
++ pixfmt = bpp_to_pixfmt(bpp);
++ if (pixfmt)
++ return pixfmt_to_var(pixfmt, var);
++ else
++ return -1;
++}
++
++static int check_var_pixfmt(struct fb_var_screeninfo *var)
++{
++ int i, ret = -1;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (bitfield_is_equal(var->red, mxcfb_pfmts[i].red) &&
++ bitfield_is_equal(var->green, mxcfb_pfmts[i].green) &&
++ bitfield_is_equal(var->blue, mxcfb_pfmts[i].blue) &&
++ bitfield_is_equal(var->transp, mxcfb_pfmts[i].transp) &&
++ var->bits_per_pixel == mxcfb_pfmts[i].bpp) {
++ ret = 0;
++ break;
++ }
++ }
++ return ret;
++}
++
++static uint32_t fbi_to_pixfmt(struct fb_info *fbi)
++{
++ int i;
++ uint32_t pixfmt = 0;
++
++ if (fbi->var.nonstd)
++ return fbi->var.nonstd;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (bitfield_is_equal(fbi->var.red, mxcfb_pfmts[i].red) &&
++ bitfield_is_equal(fbi->var.green, mxcfb_pfmts[i].green) &&
++ bitfield_is_equal(fbi->var.blue, mxcfb_pfmts[i].blue) &&
++ bitfield_is_equal(fbi->var.transp, mxcfb_pfmts[i].transp)) {
++ pixfmt = mxcfb_pfmts[i].fb_pix_fmt;
++ break;
++ }
++ }
++
++ if (pixfmt == 0)
++ dev_err(fbi->device, "cannot get pixel format\n");
++
++ return pixfmt;
++}
++
++static struct fb_info *found_registered_fb(ipu_channel_t ipu_ch, int ipu_id)
++{
++ int i;
++ struct mxcfb_info *mxc_fbi;
++ struct fb_info *fbi = NULL;
++
++ for (i = 0; i < num_registered_fb; i++) {
++ mxc_fbi =
++ ((struct mxcfb_info *)(registered_fb[i]->par));
++
++ if ((mxc_fbi->ipu_ch == ipu_ch) &&
++ (mxc_fbi->ipu_id == ipu_id)) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++ return fbi;
++}
++
++static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id);
++static irqreturn_t mxcfb_nf_irq_handler(int irq, void *dev_id);
++static int mxcfb_blank(int blank, struct fb_info *info);
++static int mxcfb_map_video_memory(struct fb_info *fbi);
++static int mxcfb_unmap_video_memory(struct fb_info *fbi);
++
++/*
++ * Set fixed framebuffer parameters based on variable settings.
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_set_fix(struct fb_info *info)
++{
++ struct fb_fix_screeninfo *fix = &info->fix;
++ struct fb_var_screeninfo *var = &info->var;
++
++ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
++
++ fix->type = FB_TYPE_PACKED_PIXELS;
++ fix->accel = FB_ACCEL_NONE;
++ fix->visual = FB_VISUAL_TRUECOLOR;
++ fix->xpanstep = 1;
++ fix->ywrapstep = 1;
++ fix->ypanstep = 1;
++
++ return 0;
++}
++
++static int _setup_disp_channel1(struct fb_info *fbi)
++{
++ ipu_channel_params_t params;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ memset(&params, 0, sizeof(params));
++
++ if (mxc_fbi->ipu_ch == MEM_DC_SYNC) {
++ params.mem_dc_sync.di = mxc_fbi->ipu_di;
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ params.mem_dc_sync.interlaced = true;
++ params.mem_dc_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ params.mem_dc_sync.in_pixel_fmt = fbi_to_pixfmt(fbi);
++ } else {
++ params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ params.mem_dp_bg_sync.interlaced = true;
++ params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ params.mem_dp_bg_sync.in_pixel_fmt = fbi_to_pixfmt(fbi);
++ if (mxc_fbi->alpha_chan_en)
++ params.mem_dp_bg_sync.alpha_chan_en = true;
++ }
++ ipu_init_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, &params);
++
++ return 0;
++}
++
++static int _setup_disp_channel2(struct fb_info *fbi)
++{
++ int retval = 0;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++ int fb_stride;
++ unsigned long base;
++ unsigned int fr_xoff, fr_yoff, fr_w, fr_h;
++
++ switch (fbi_to_pixfmt(fbi)) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YUV444P:
++ fb_stride = fbi->var.xres_virtual;
++ break;
++ default:
++ fb_stride = fbi->fix.line_length;
++ }
++
++ base = fbi->fix.smem_start;
++ fr_xoff = fbi->var.xoffset;
++ fr_w = fbi->var.xres_virtual;
++ if (!(fbi->var.vmode & FB_VMODE_YWRAP)) {
++ dev_dbg(fbi->device, "Y wrap disabled\n");
++ fr_yoff = fbi->var.yoffset % fbi->var.yres;
++ fr_h = fbi->var.yres;
++ base += fbi->fix.line_length * fbi->var.yres *
++ (fbi->var.yoffset / fbi->var.yres);
++ } else {
++ dev_dbg(fbi->device, "Y wrap enabled\n");
++ fr_yoff = fbi->var.yoffset;
++ fr_h = fbi->var.yres_virtual;
++ }
++ base += fr_yoff * fb_stride + fr_xoff;
++
++ mxc_fbi->cur_ipu_buf = 2;
++ init_completion(&mxc_fbi->flip_complete);
++ /*
++ * We don't need to wait for vsync at the first time
++ * we do pan display after fb is initialized, as IPU will
++ * switch to the newly selected buffer automatically,
++ * so we call complete() for both mxc_fbi->flip_complete
++ * and mxc_fbi->alpha_flip_complete.
++ */
++ complete(&mxc_fbi->flip_complete);
++ if (mxc_fbi->alpha_chan_en) {
++ mxc_fbi->cur_ipu_alpha_buf = 1;
++ init_completion(&mxc_fbi->alpha_flip_complete);
++ complete(&mxc_fbi->alpha_flip_complete);
++ }
++
++ retval = ipu_init_channel_buffer(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(fbi),
++ fbi->var.xres, fbi->var.yres,
++ fb_stride,
++ fbi->var.rotate,
++ base,
++ base,
++ fbi->var.accel_flags &
++ FB_ACCEL_DOUBLE_FLAG ? 0 : base,
++ 0, 0);
++ if (retval) {
++ dev_err(fbi->device,
++ "ipu_init_channel_buffer error %d\n", retval);
++ return retval;
++ }
++
++ /* update u/v offset */
++ ipu_update_channel_offset(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(fbi),
++ fr_w,
++ fr_h,
++ fr_w,
++ 0, 0,
++ fr_yoff,
++ fr_xoff);
++
++ if (mxc_fbi->alpha_chan_en) {
++ retval = ipu_init_channel_buffer(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ IPU_PIX_FMT_GENERIC,
++ fbi->var.xres, fbi->var.yres,
++ fbi->var.xres,
++ fbi->var.rotate,
++ mxc_fbi->alpha_phy_addr1,
++ mxc_fbi->alpha_phy_addr0,
++ 0,
++ 0, 0);
++ if (retval) {
++ dev_err(fbi->device,
++ "ipu_init_channel_buffer error %d\n", retval);
++ return retval;
++ }
++ }
++
++ return retval;
++}
++
++static bool mxcfb_need_to_set_par(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ if ((fbi->var.activate & FB_ACTIVATE_FORCE) &&
++ (fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
++ return true;
++
++ /*
++ * Ignore xoffset and yoffset update,
++ * because pan display handles this case.
++ */
++ mxc_fbi->cur_var.xoffset = fbi->var.xoffset;
++ mxc_fbi->cur_var.yoffset = fbi->var.yoffset;
++
++ return !!memcmp(&mxc_fbi->cur_var, &fbi->var,
++ sizeof(struct fb_var_screeninfo));
++}
++
++/*
++ * Set framebuffer parameters and change the operating mode.
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_set_par(struct fb_info *fbi)
++{
++ int retval = 0;
++ u32 mem_len, alpha_mem_len;
++ ipu_di_signal_cfg_t sig_cfg;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ int16_t ov_pos_x = 0, ov_pos_y = 0;
++ int ov_pos_ret = 0;
++ struct mxcfb_info *mxc_fbi_fg = NULL;
++ bool ovfbi_enable = false;
++
++ if (ipu_ch_param_bad_alpha_pos(fbi_to_pixfmt(fbi)) &&
++ mxc_fbi->alpha_chan_en) {
++ dev_err(fbi->device, "Bad pixel format for "
++ "graphics plane fb\n");
++ return -EINVAL;
++ }
++
++ if (mxc_fbi->ovfbi)
++ mxc_fbi_fg = (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++
++ if (mxc_fbi->ovfbi && mxc_fbi_fg)
++ if (mxc_fbi_fg->next_blank == FB_BLANK_UNBLANK)
++ ovfbi_enable = true;
++
++ if (!mxcfb_need_to_set_par(fbi))
++ return 0;
++
++ dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
++
++ if (fbi->var.xres == 0 || fbi->var.yres == 0)
++ return 0;
++
++ if (ovfbi_enable) {
++ ov_pos_ret = ipu_disp_get_window_pos(
++ mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch,
++ &ov_pos_x, &ov_pos_y);
++ if (ov_pos_ret < 0)
++ dev_err(fbi->device, "Get overlay pos failed, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++
++ ipu_clear_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_irq);
++ ipu_disable_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_nf_irq);
++ ipu_disable_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_nf_irq);
++ ipu_disable_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++ }
++
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++
++ /*
++ * Disable IPU hsp clock if it is enabled for an
++ * additional time in ipu common driver.
++ */
++ if (mxc_fbi->first_set_par && mxc_fbi->late_init)
++ ipu_disable_hsp_clk(mxc_fbi->ipu);
++
++ mxcfb_set_fix(fbi);
++
++ mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
++ if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
++ if (fbi->fix.smem_start)
++ mxcfb_unmap_video_memory(fbi);
++
++ if (mxcfb_map_video_memory(fbi) < 0)
++ return -ENOMEM;
++ }
++
++ if (mxc_fbi->first_set_par) {
++ /*
++ * Clear the screen in case uboot fb pixel format is not
++ * the same to kernel fb pixel format.
++ */
++ if (mxc_fbi->late_init)
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ mxc_fbi->first_set_par = false;
++ }
++
++ if (mxc_fbi->alpha_chan_en) {
++ alpha_mem_len = fbi->var.xres * fbi->var.yres;
++ if ((!mxc_fbi->alpha_phy_addr0 && !mxc_fbi->alpha_phy_addr1) ||
++ (alpha_mem_len > mxc_fbi->alpha_mem_len)) {
++ if (mxc_fbi->alpha_phy_addr0)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr0,
++ mxc_fbi->alpha_phy_addr0);
++ if (mxc_fbi->alpha_phy_addr1)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr1,
++ mxc_fbi->alpha_phy_addr1);
++
++ mxc_fbi->alpha_virt_addr0 =
++ dma_alloc_coherent(fbi->device,
++ alpha_mem_len,
++ &mxc_fbi->alpha_phy_addr0,
++ GFP_DMA | GFP_KERNEL);
++
++ mxc_fbi->alpha_virt_addr1 =
++ dma_alloc_coherent(fbi->device,
++ alpha_mem_len,
++ &mxc_fbi->alpha_phy_addr1,
++ GFP_DMA | GFP_KERNEL);
++ if (mxc_fbi->alpha_virt_addr0 == NULL ||
++ mxc_fbi->alpha_virt_addr1 == NULL) {
++ dev_err(fbi->device, "mxcfb: dma alloc for"
++ " alpha buffer failed.\n");
++ if (mxc_fbi->alpha_virt_addr0)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr0,
++ mxc_fbi->alpha_phy_addr0);
++ if (mxc_fbi->alpha_virt_addr1)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr1,
++ mxc_fbi->alpha_phy_addr1);
++ return -ENOMEM;
++ }
++ mxc_fbi->alpha_mem_len = alpha_mem_len;
++ }
++ }
++
++ if (mxc_fbi->next_blank != FB_BLANK_UNBLANK)
++ return retval;
++
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->setup) {
++ retval = mxc_fbi->dispdrv->drv->setup(mxc_fbi->dispdrv, fbi);
++ if (retval < 0) {
++ dev_err(fbi->device, "setup error, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++ return -EINVAL;
++ }
++ }
++
++ _setup_disp_channel1(fbi);
++ if (ovfbi_enable)
++ _setup_disp_channel1(mxc_fbi->ovfbi);
++
++ if (!mxc_fbi->overlay) {
++ uint32_t out_pixel_fmt;
++
++ memset(&sig_cfg, 0, sizeof(sig_cfg));
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ sig_cfg.interlaced = true;
++ out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
++ sig_cfg.odd_field_first = true;
++ if (mxc_fbi->ipu_int_clk)
++ sig_cfg.int_clk = true;
++ if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
++ sig_cfg.Hsync_pol = true;
++ if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
++ sig_cfg.Vsync_pol = true;
++ if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
++ sig_cfg.clk_pol = true;
++ if (fbi->var.sync & FB_SYNC_DATA_INVERT)
++ sig_cfg.data_pol = true;
++ if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
++ sig_cfg.enable_pol = true;
++ if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
++ sig_cfg.clkidle_en = true;
++
++ dev_dbg(fbi->device, "pixclock = %ul Hz\n",
++ (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
++
++ if (ipu_init_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di,
++ (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
++ fbi->var.xres, fbi->var.yres,
++ out_pixel_fmt,
++ fbi->var.left_margin,
++ fbi->var.hsync_len,
++ fbi->var.right_margin,
++ fbi->var.upper_margin,
++ fbi->var.vsync_len,
++ fbi->var.lower_margin,
++ 0, sig_cfg) != 0) {
++ dev_err(fbi->device,
++ "mxcfb: Error initializing panel.\n");
++ return -EINVAL;
++ }
++
++ fbi->mode =
++ (struct fb_videomode *)fb_match_mode(&fbi->var,
++ &fbi->modelist);
++
++ ipu_disp_set_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, 0, 0);
++ }
++
++ retval = _setup_disp_channel2(fbi);
++ if (retval) {
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ return retval;
++ }
++
++ if (ovfbi_enable) {
++ if (ov_pos_ret >= 0)
++ ipu_disp_set_window_pos(
++ mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch,
++ ov_pos_x, ov_pos_y);
++ retval = _setup_disp_channel2(mxc_fbi->ovfbi);
++ if (retval) {
++ ipu_uninit_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ return retval;
++ }
++ }
++
++ ipu_enable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ if (ovfbi_enable)
++ ipu_enable_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->enable) {
++ retval = mxc_fbi->dispdrv->drv->enable(mxc_fbi->dispdrv);
++ if (retval < 0) {
++ dev_err(fbi->device, "enable error, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++ return -EINVAL;
++ }
++ }
++
++ mxc_fbi->cur_var = fbi->var;
++
++ return retval;
++}
++
++static int _swap_channels(struct fb_info *fbi_from,
++ struct fb_info *fbi_to, bool both_on)
++{
++ int retval, tmp;
++ ipu_channel_t old_ch;
++ struct fb_info *ovfbi;
++ struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi_from->par;
++ struct mxcfb_info *mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
++
++ if (both_on) {
++ ipu_disable_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch);
++ }
++
++ /* switch the mxc fbi parameters */
++ old_ch = mxc_fbi_from->ipu_ch;
++ mxc_fbi_from->ipu_ch = mxc_fbi_to->ipu_ch;
++ mxc_fbi_to->ipu_ch = old_ch;
++ tmp = mxc_fbi_from->ipu_ch_irq;
++ mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
++ mxc_fbi_to->ipu_ch_irq = tmp;
++ tmp = mxc_fbi_from->ipu_ch_nf_irq;
++ mxc_fbi_from->ipu_ch_nf_irq = mxc_fbi_to->ipu_ch_nf_irq;
++ mxc_fbi_to->ipu_ch_nf_irq = tmp;
++ ovfbi = mxc_fbi_from->ovfbi;
++ mxc_fbi_from->ovfbi = mxc_fbi_to->ovfbi;
++ mxc_fbi_to->ovfbi = ovfbi;
++
++ _setup_disp_channel1(fbi_from);
++ retval = _setup_disp_channel2(fbi_from);
++ if (retval)
++ return retval;
++
++ /* switch between dp and dc, disable old idmac, enable new idmac */
++ retval = ipu_swap_channel(mxc_fbi_from->ipu, old_ch, mxc_fbi_from->ipu_ch);
++ ipu_uninit_channel(mxc_fbi_from->ipu, old_ch);
++
++ if (both_on) {
++ _setup_disp_channel1(fbi_to);
++ retval = _setup_disp_channel2(fbi_to);
++ if (retval)
++ return retval;
++ ipu_enable_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch);
++ }
++
++ return retval;
++}
++
++static int swap_channels(struct fb_info *fbi_from)
++{
++ int i;
++ int swap_mode;
++ ipu_channel_t ch_to;
++ struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi_from->par;
++ struct fb_info *fbi_to = NULL;
++ struct mxcfb_info *mxc_fbi_to;
++
++ /* what's the target channel? */
++ if (mxc_fbi_from->ipu_ch == MEM_BG_SYNC)
++ ch_to = MEM_DC_SYNC;
++ else
++ ch_to = MEM_BG_SYNC;
++
++ fbi_to = found_registered_fb(ch_to, mxc_fbi_from->ipu_id);
++ if (!fbi_to)
++ return -1;
++ mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
++
++ ipu_clear_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq);
++ ipu_free_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq, fbi_from);
++ ipu_free_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq, fbi_to);
++ ipu_clear_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq);
++ ipu_clear_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq);
++ ipu_free_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq, fbi_from);
++ ipu_free_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq, fbi_to);
++
++ if (mxc_fbi_from->cur_blank == FB_BLANK_UNBLANK) {
++ if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
++ swap_mode = BOTH_ON;
++ else
++ swap_mode = SRC_ON;
++ } else {
++ if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
++ swap_mode = TGT_ON;
++ else
++ swap_mode = BOTH_OFF;
++ }
++
++ switch (swap_mode) {
++ case BOTH_ON:
++ /* disable target->switch src->enable target */
++ _swap_channels(fbi_from, fbi_to, true);
++ break;
++ case SRC_ON:
++ /* just switch src */
++ _swap_channels(fbi_from, fbi_to, false);
++ break;
++ case TGT_ON:
++ /* just switch target */
++ _swap_channels(fbi_to, fbi_from, false);
++ break;
++ case BOTH_OFF:
++ /* switch directly, no more need to do */
++ mxc_fbi_to->ipu_ch = mxc_fbi_from->ipu_ch;
++ mxc_fbi_from->ipu_ch = ch_to;
++ i = mxc_fbi_from->ipu_ch_irq;
++ mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
++ mxc_fbi_to->ipu_ch_irq = i;
++ i = mxc_fbi_from->ipu_ch_nf_irq;
++ mxc_fbi_from->ipu_ch_nf_irq = mxc_fbi_to->ipu_ch_nf_irq;
++ mxc_fbi_to->ipu_ch_nf_irq = i;
++ break;
++ default:
++ break;
++ }
++
++ if (ipu_request_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_from) != 0) {
++ dev_err(fbi_from->device, "Error registering irq %d\n",
++ mxc_fbi_from->ipu_ch_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq);
++ if (ipu_request_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_to) != 0) {
++ dev_err(fbi_to->device, "Error registering irq %d\n",
++ mxc_fbi_to->ipu_ch_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq);
++ if (ipu_request_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_from) != 0) {
++ dev_err(fbi_from->device, "Error registering irq %d\n",
++ mxc_fbi_from->ipu_ch_nf_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq);
++ if (ipu_request_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_to) != 0) {
++ dev_err(fbi_to->device, "Error registering irq %d\n",
++ mxc_fbi_to->ipu_ch_nf_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq);
++
++ return 0;
++}
++
++/*
++ * Check framebuffer variable parameters and adjust to valid values.
++ *
++ * @param var framebuffer variable parameters
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ u32 vtotal;
++ u32 htotal;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
++
++
++ if (var->xres == 0 || var->yres == 0)
++ return 0;
++
++ /* fg should not bigger than bg */
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ struct fb_info *fbi_tmp;
++ int bg_xres = 0, bg_yres = 0;
++ int16_t pos_x, pos_y;
++
++ bg_xres = var->xres;
++ bg_yres = var->yres;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp) {
++ bg_xres = fbi_tmp->var.xres;
++ bg_yres = fbi_tmp->var.yres;
++ }
++
++ ipu_disp_get_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, &pos_x, &pos_y);
++
++ if ((var->xres + pos_x) > bg_xres)
++ var->xres = bg_xres - pos_x;
++ if ((var->yres + pos_y) > bg_yres)
++ var->yres = bg_yres - pos_y;
++ }
++
++ if (var->rotate > IPU_ROTATE_VERT_FLIP)
++ var->rotate = IPU_ROTATE_NONE;
++
++ if (var->xres_virtual < var->xres)
++ var->xres_virtual = var->xres;
++
++ if (var->yres_virtual < var->yres)
++ var->yres_virtual = var->yres * 3;
++
++ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
++ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 12) &&
++ (var->bits_per_pixel != 8))
++ var->bits_per_pixel = 16;
++
++ if (check_var_pixfmt(var))
++ /* Fall back to default */
++ bpp_to_var(var->bits_per_pixel, var);
++
++ if (var->pixclock < 1000) {
++ htotal = var->xres + var->right_margin + var->hsync_len +
++ var->left_margin;
++ vtotal = var->yres + var->lower_margin + var->vsync_len +
++ var->upper_margin;
++ var->pixclock = (vtotal * htotal * 6UL) / 100UL;
++ var->pixclock = KHZ2PICOS(var->pixclock);
++ dev_dbg(info->device,
++ "pixclock set for 60Hz refresh = %u ps\n",
++ var->pixclock);
++ }
++
++ var->height = -1;
++ var->width = -1;
++ var->grayscale = 0;
++
++ return 0;
++}
++
++static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
++{
++ chan &= 0xffff;
++ chan >>= 16 - bf->length;
++ return chan << bf->offset;
++}
++
++static int mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
++ u_int trans, struct fb_info *fbi)
++{
++ unsigned int val;
++ int ret = 1;
++
++ /*
++ * If greyscale is true, then we convert the RGB value
++ * to greyscale no matter what visual we are using.
++ */
++ if (fbi->var.grayscale)
++ red = green = blue = (19595 * red + 38470 * green +
++ 7471 * blue) >> 16;
++ switch (fbi->fix.visual) {
++ case FB_VISUAL_TRUECOLOR:
++ /*
++ * 16-bit True Colour. We encode the RGB value
++ * according to the RGB bitfield information.
++ */
++ if (regno < 16) {
++ u32 *pal = fbi->pseudo_palette;
++
++ val = _chan_to_field(red, &fbi->var.red);
++ val |= _chan_to_field(green, &fbi->var.green);
++ val |= _chan_to_field(blue, &fbi->var.blue);
++
++ pal[regno] = val;
++ ret = 0;
++ }
++ break;
++
++ case FB_VISUAL_STATIC_PSEUDOCOLOR:
++ case FB_VISUAL_PSEUDOCOLOR:
++ break;
++ }
++
++ return ret;
++}
++
++/*
++ * Function to handle custom ioctls for MXC framebuffer.
++ *
++ * @param inode inode struct
++ *
++ * @param file file struct
++ *
++ * @param cmd Ioctl command to handle
++ *
++ * @param arg User pointer to command arguments
++ *
++ * @param fbi framebuffer information pointer
++ */
++static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
++{
++ int retval = 0;
++ int __user *argp = (void __user *)arg;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ switch (cmd) {
++ case MXCFB_SET_GBL_ALPHA:
++ {
++ struct mxcfb_gbl_alpha ga;
++
++ if (copy_from_user(&ga, (void *)arg, sizeof(ga))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (ipu_disp_set_global_alpha(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ (bool)ga.enable,
++ ga.alpha)) {
++ retval = -EINVAL;
++ break;
++ }
++
++ if (ga.enable)
++ mxc_fbi->alpha_chan_en = false;
++
++ if (ga.enable)
++ dev_dbg(fbi->device,
++ "Set global alpha of %s to %d\n",
++ fbi->fix.id, ga.alpha);
++ break;
++ }
++ case MXCFB_SET_LOC_ALPHA:
++ {
++ struct mxcfb_loc_alpha la;
++ bool bad_pixfmt =
++ ipu_ch_param_bad_alpha_pos(fbi_to_pixfmt(fbi));
++
++ if (copy_from_user(&la, (void *)arg, sizeof(la))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (la.enable && !la.alpha_in_pixel) {
++ struct fb_info *fbi_tmp;
++ ipu_channel_t ipu_ch;
++
++ if (bad_pixfmt) {
++ dev_err(fbi->device, "Bad pixel format "
++ "for graphics plane fb\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ mxc_fbi->alpha_chan_en = true;
++
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
++ ipu_ch = MEM_BG_SYNC;
++ else if (mxc_fbi->ipu_ch == MEM_BG_SYNC)
++ ipu_ch = MEM_FG_SYNC;
++ else {
++ retval = -EINVAL;
++ break;
++ }
++
++ fbi_tmp = found_registered_fb(ipu_ch, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ ((struct mxcfb_info *)(fbi_tmp->par))->alpha_chan_en = false;
++ } else
++ mxc_fbi->alpha_chan_en = false;
++
++ if (ipu_disp_set_global_alpha(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ !(bool)la.enable, 0)) {
++ retval = -EINVAL;
++ break;
++ }
++
++ fbi->var.activate = (fbi->var.activate & ~FB_ACTIVATE_MASK) |
++ FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE;
++ mxcfb_set_par(fbi);
++
++ la.alpha_phy_addr0 = mxc_fbi->alpha_phy_addr0;
++ la.alpha_phy_addr1 = mxc_fbi->alpha_phy_addr1;
++ if (copy_to_user((void *)arg, &la, sizeof(la))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (la.enable)
++ dev_dbg(fbi->device,
++ "Enable DP local alpha for %s\n",
++ fbi->fix.id);
++ break;
++ }
++ case MXCFB_SET_LOC_ALP_BUF:
++ {
++ unsigned long base;
++ uint32_t ipu_alp_ch_irq;
++
++ if (!(((mxc_fbi->ipu_ch == MEM_FG_SYNC) ||
++ (mxc_fbi->ipu_ch == MEM_BG_SYNC)) &&
++ (mxc_fbi->alpha_chan_en))) {
++ dev_err(fbi->device,
++ "Should use background or overlay "
++ "framebuffer to set the alpha buffer "
++ "number\n");
++ return -EINVAL;
++ }
++
++ if (get_user(base, argp))
++ return -EFAULT;
++
++ if (base != mxc_fbi->alpha_phy_addr0 &&
++ base != mxc_fbi->alpha_phy_addr1) {
++ dev_err(fbi->device,
++ "Wrong alpha buffer physical address "
++ "%lu\n", base);
++ return -EINVAL;
++ }
++
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
++ ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
++ else
++ ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
++
++ retval = wait_for_completion_timeout(
++ &mxc_fbi->alpha_flip_complete, HZ/2);
++ if (retval == 0) {
++ dev_err(fbi->device, "timeout when waiting for alpha flip irq\n");
++ retval = -ETIMEDOUT;
++ break;
++ }
++
++ mxc_fbi->cur_ipu_alpha_buf =
++ !mxc_fbi->cur_ipu_alpha_buf;
++ if (ipu_update_channel_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->
++ cur_ipu_alpha_buf,
++ base) == 0) {
++ ipu_select_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf);
++ ipu_clear_irq(mxc_fbi->ipu, ipu_alp_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, ipu_alp_ch_irq);
++ } else {
++ dev_err(fbi->device,
++ "Error updating %s SDC alpha buf %d "
++ "to address=0x%08lX\n",
++ fbi->fix.id,
++ mxc_fbi->cur_ipu_alpha_buf, base);
++ }
++ break;
++ }
++ case MXCFB_SET_CLR_KEY:
++ {
++ struct mxcfb_color_key key;
++ if (copy_from_user(&key, (void *)arg, sizeof(key))) {
++ retval = -EFAULT;
++ break;
++ }
++ retval = ipu_disp_set_color_key(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ key.enable,
++ key.color_key);
++ dev_dbg(fbi->device, "Set color key to 0x%08X\n",
++ key.color_key);
++ break;
++ }
++ case MXCFB_SET_GAMMA:
++ {
++ struct mxcfb_gamma gamma;
++ if (copy_from_user(&gamma, (void *)arg, sizeof(gamma))) {
++ retval = -EFAULT;
++ break;
++ }
++ retval = ipu_disp_set_gamma_correction(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ gamma.enable,
++ gamma.constk,
++ gamma.slopek);
++ break;
++ }
++ case MXCFB_WAIT_FOR_VSYNC:
++ {
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ /* BG should poweron */
++ struct mxcfb_info *bg_mxcfbi = NULL;
++ struct fb_info *fbi_tmp;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ bg_mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
++
++ if (!bg_mxcfbi) {
++ retval = -EINVAL;
++ break;
++ }
++ if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK) {
++ retval = -EINVAL;
++ break;
++ }
++ }
++ if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK) {
++ retval = -EINVAL;
++ break;
++ }
++
++ init_completion(&mxc_fbi->vsync_complete);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ retval = wait_for_completion_interruptible_timeout(
++ &mxc_fbi->vsync_complete, 1 * HZ);
++ if (retval == 0) {
++ dev_err(fbi->device,
++ "MXCFB_WAIT_FOR_VSYNC: timeout %d\n",
++ retval);
++ retval = -ETIME;
++ } else if (retval > 0) {
++ retval = 0;
++ }
++ break;
++ }
++ case FBIO_ALLOC:
++ {
++ int size;
++ struct mxcfb_alloc_list *mem;
++
++ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
++ if (mem == NULL)
++ return -ENOMEM;
++
++ if (get_user(size, argp))
++ return -EFAULT;
++
++ mem->size = PAGE_ALIGN(size);
++
++ mem->cpu_addr = dma_alloc_coherent(fbi->device, size,
++ &mem->phy_addr,
++ GFP_KERNEL);
++ if (mem->cpu_addr == NULL) {
++ kfree(mem);
++ return -ENOMEM;
++ }
++
++ list_add(&mem->list, &fb_alloc_list);
++
++ dev_dbg(fbi->device, "allocated %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ if (put_user(mem->phy_addr, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case FBIO_FREE:
++ {
++ unsigned long offset;
++ struct mxcfb_alloc_list *mem;
++
++ if (get_user(offset, argp))
++ return -EFAULT;
++
++ retval = -EINVAL;
++ list_for_each_entry(mem, &fb_alloc_list, list) {
++ if (mem->phy_addr == offset) {
++ list_del(&mem->list);
++ dma_free_coherent(fbi->device,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ kfree(mem);
++ retval = 0;
++ break;
++ }
++ }
++
++ break;
++ }
++ case MXCFB_SET_OVERLAY_POS:
++ {
++ struct mxcfb_pos pos;
++ struct fb_info *bg_fbi = NULL;
++ struct mxcfb_info *bg_mxcfbi = NULL;
++
++ if (mxc_fbi->ipu_ch != MEM_FG_SYNC) {
++ dev_err(fbi->device, "Should use the overlay "
++ "framebuffer to set the position of "
++ "the overlay window\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ if (copy_from_user(&pos, (void *)arg, sizeof(pos))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ bg_fbi = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (bg_fbi)
++ bg_mxcfbi = ((struct mxcfb_info *)(bg_fbi->par));
++
++ if (bg_fbi == NULL) {
++ dev_err(fbi->device, "Cannot find the "
++ "background framebuffer\n");
++ retval = -ENOENT;
++ break;
++ }
++
++ /* if fb is unblank, check if the pos fit the display */
++ if (mxc_fbi->cur_blank == FB_BLANK_UNBLANK) {
++ if (fbi->var.xres + pos.x > bg_fbi->var.xres) {
++ if (bg_fbi->var.xres < fbi->var.xres)
++ pos.x = 0;
++ else
++ pos.x = bg_fbi->var.xres - fbi->var.xres;
++ }
++ if (fbi->var.yres + pos.y > bg_fbi->var.yres) {
++ if (bg_fbi->var.yres < fbi->var.yres)
++ pos.y = 0;
++ else
++ pos.y = bg_fbi->var.yres - fbi->var.yres;
++ }
++ }
++
++ retval = ipu_disp_set_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ pos.x, pos.y);
++
++ if (copy_to_user((void *)arg, &pos, sizeof(pos))) {
++ retval = -EFAULT;
++ break;
++ }
++ break;
++ }
++ case MXCFB_GET_FB_IPU_CHAN:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_ch, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_DIFMT:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_di_pix_fmt, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_FB_IPU_DI:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_di, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_FB_BLANK:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->cur_blank, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_SET_DIFMT:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (get_user(mxc_fbi->ipu_di_pix_fmt, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case MXCFB_CSC_UPDATE:
++ {
++ struct mxcfb_csc_matrix csc;
++
++ if (copy_from_user(&csc, (void *) arg, sizeof(csc)))
++ return -EFAULT;
++
++ if ((mxc_fbi->ipu_ch != MEM_FG_SYNC) &&
++ (mxc_fbi->ipu_ch != MEM_BG_SYNC) &&
++ (mxc_fbi->ipu_ch != MEM_BG_ASYNC0))
++ return -EFAULT;
++ ipu_set_csc_coefficients(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ csc.param);
++ }
++ default:
++ retval = -EINVAL;
++ }
++ return retval;
++}
++
++/*
++ * mxcfb_blank():
++ * Blank the display.
++ */
++static int mxcfb_blank(int blank, struct fb_info *info)
++{
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
++ int ret = 0;
++
++ dev_dbg(info->device, "blank = %d\n", blank);
++
++ if (mxc_fbi->cur_blank == blank)
++ return 0;
++
++ mxc_fbi->next_blank = blank;
++
++ switch (blank) {
++ case FB_BLANK_POWERDOWN:
++ case FB_BLANK_VSYNC_SUSPEND:
++ case FB_BLANK_HSYNC_SUSPEND:
++ case FB_BLANK_NORMAL:
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->disable)
++ mxc_fbi->dispdrv->drv->disable(mxc_fbi->dispdrv);
++ ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
++ if (mxc_fbi->ipu_di >= 0)
++ ipu_uninit_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ break;
++ case FB_BLANK_UNBLANK:
++ info->var.activate = (info->var.activate & ~FB_ACTIVATE_MASK) |
++ FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE;
++ ret = mxcfb_set_par(info);
++ break;
++ }
++ if (!ret)
++ mxc_fbi->cur_blank = blank;
++ return ret;
++}
++
++/*
++ * Pan or Wrap the Display
++ *
++ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
++ *
++ * @param var Variable screen buffer information
++ * @param info Framebuffer information pointer
++ */
++static int
++mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par,
++ *mxc_graphic_fbi = NULL;
++ u_int y_bottom;
++ unsigned int fr_xoff, fr_yoff, fr_w, fr_h;
++ unsigned long base, active_alpha_phy_addr = 0;
++ bool loc_alpha_en = false;
++ int fb_stride;
++ int i;
++ int ret;
++
++ /* no pan display during fb blank */
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ struct mxcfb_info *bg_mxcfbi = NULL;
++ struct fb_info *fbi_tmp;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ bg_mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
++ if (!bg_mxcfbi)
++ return -EINVAL;
++ if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK)
++ return -EINVAL;
++ }
++ if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK)
++ return -EINVAL;
++
++ y_bottom = var->yoffset;
++
++ if (y_bottom > info->var.yres_virtual)
++ return -EINVAL;
++
++ switch (fbi_to_pixfmt(info)) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YUV444P:
++ fb_stride = info->var.xres_virtual;
++ break;
++ default:
++ fb_stride = info->fix.line_length;
++ }
++
++ base = info->fix.smem_start;
++ fr_xoff = var->xoffset;
++ fr_w = info->var.xres_virtual;
++ if (!(var->vmode & FB_VMODE_YWRAP)) {
++ dev_dbg(info->device, "Y wrap disabled\n");
++ fr_yoff = var->yoffset % info->var.yres;
++ fr_h = info->var.yres;
++ base += info->fix.line_length * info->var.yres *
++ (var->yoffset / info->var.yres);
++ } else {
++ dev_dbg(info->device, "Y wrap enabled\n");
++ fr_yoff = var->yoffset;
++ fr_h = info->var.yres_virtual;
++ }
++ base += fr_yoff * fb_stride + fr_xoff;
++
++ /* Check if DP local alpha is enabled and find the graphic fb */
++ if (mxc_fbi->ipu_ch == MEM_BG_SYNC || mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ for (i = 0; i < num_registered_fb; i++) {
++ char bg_id[] = "DISP3 BG";
++ char fg_id[] = "DISP3 FG";
++ char *idstr = registered_fb[i]->fix.id;
++ bg_id[4] += mxc_fbi->ipu_id;
++ fg_id[4] += mxc_fbi->ipu_id;
++ if ((strcmp(idstr, bg_id) == 0 ||
++ strcmp(idstr, fg_id) == 0) &&
++ ((struct mxcfb_info *)
++ (registered_fb[i]->par))->alpha_chan_en) {
++ loc_alpha_en = true;
++ mxc_graphic_fbi = (struct mxcfb_info *)
++ (registered_fb[i]->par);
++ active_alpha_phy_addr =
++ mxc_fbi->cur_ipu_alpha_buf ?
++ mxc_graphic_fbi->alpha_phy_addr1 :
++ mxc_graphic_fbi->alpha_phy_addr0;
++ dev_dbg(info->device, "Updating SDC alpha "
++ "buf %d address=0x%08lX\n",
++ !mxc_fbi->cur_ipu_alpha_buf,
++ active_alpha_phy_addr);
++ break;
++ }
++ }
++ }
++
++ ret = wait_for_completion_timeout(&mxc_fbi->flip_complete, HZ/2);
++ if (ret == 0) {
++ dev_err(info->device, "timeout when waiting for flip irq\n");
++ return -ETIMEDOUT;
++ }
++
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
++
++ dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n",
++ info->fix.id, mxc_fbi->cur_ipu_buf, base);
++
++ if (ipu_update_channel_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ mxc_fbi->cur_ipu_buf, base) == 0) {
++ /* Update the DP local alpha buffer only for graphic plane */
++ if (loc_alpha_en && mxc_graphic_fbi == mxc_fbi &&
++ ipu_update_channel_buffer(mxc_graphic_fbi->ipu, mxc_graphic_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf,
++ active_alpha_phy_addr) == 0) {
++ ipu_select_buffer(mxc_graphic_fbi->ipu, mxc_graphic_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf);
++ }
++
++ /* update u/v offset */
++ ipu_update_channel_offset(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(info),
++ fr_w,
++ fr_h,
++ fr_w,
++ 0, 0,
++ fr_yoff,
++ fr_xoff);
++
++ ipu_select_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ mxc_fbi->cur_ipu_buf);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ } else {
++ dev_err(info->device,
++ "Error updating SDC buf %d to address=0x%08lX, "
++ "current buf %d, buf0 ready %d, buf1 ready %d, "
++ "buf2 ready %d\n", mxc_fbi->cur_ipu_buf, base,
++ ipu_get_cur_buffer_idx(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 0),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 1),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 2));
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ return -EBUSY;
++ }
++
++ dev_dbg(info->device, "Update complete\n");
++
++ info->var.yoffset = var->yoffset;
++
++ return 0;
++}
++
++/*
++ * Function to handle custom mmap for MXC framebuffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @param vma Pointer to vm_area_struct
++ */
++static int mxcfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
++{
++ bool found = false;
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++ struct mxcfb_alloc_list *mem;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ if (offset < fbi->fix.smem_len) {
++ /* mapping framebuffer memory */
++ len = fbi->fix.smem_len - offset;
++ vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT;
++ } else if ((vma->vm_pgoff ==
++ (mxc_fbi->alpha_phy_addr0 >> PAGE_SHIFT)) ||
++ (vma->vm_pgoff ==
++ (mxc_fbi->alpha_phy_addr1 >> PAGE_SHIFT))) {
++ len = mxc_fbi->alpha_mem_len;
++ } else {
++ list_for_each_entry(mem, &fb_alloc_list, list) {
++ if (offset == mem->phy_addr) {
++ found = true;
++ len = mem->size;
++ break;
++ }
++ }
++ if (!found)
++ return -EINVAL;
++ }
++
++ len = PAGE_ALIGN(len);
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ /* make buffers bufferable */
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ vma->vm_flags |= VM_IO;
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++ dev_dbg(fbi->device, "mmap remap_pfn_range failed\n");
++ return -ENOBUFS;
++ }
++
++ return 0;
++}
++
++/*!
++ * This structure contains the pointers to the control functions that are
++ * invoked by the core framebuffer driver to perform operations like
++ * blitting, rectangle filling, copy regions and cursor definition.
++ */
++static struct fb_ops mxcfb_ops = {
++ .owner = THIS_MODULE,
++ .fb_set_par = mxcfb_set_par,
++ .fb_check_var = mxcfb_check_var,
++ .fb_setcolreg = mxcfb_setcolreg,
++ .fb_pan_display = mxcfb_pan_display,
++ .fb_ioctl = mxcfb_ioctl,
++ .fb_mmap = mxcfb_mmap,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++ .fb_blank = mxcfb_blank,
++};
++
++static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->flip_complete);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mxcfb_nf_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->vsync_complete);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mxcfb_alpha_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->alpha_flip_complete);
++ return IRQ_HANDLED;
++}
++
++/*
++ * Suspends the framebuffer and blanks the screen. Power management support
++ */
++static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++ int saved_blank;
++#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY
++ void *fbmem;
++#endif
++
++ if (mxc_fbi->ovfbi) {
++ struct mxcfb_info *mxc_fbi_fg =
++ (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++
++ console_lock();
++ fb_set_suspend(mxc_fbi->ovfbi, 1);
++ saved_blank = mxc_fbi_fg->cur_blank;
++ mxcfb_blank(FB_BLANK_POWERDOWN, mxc_fbi->ovfbi);
++ mxc_fbi_fg->next_blank = saved_blank;
++ console_unlock();
++ }
++
++ console_lock();
++ fb_set_suspend(fbi, 1);
++ saved_blank = mxc_fbi->cur_blank;
++ mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
++ mxc_fbi->next_blank = saved_blank;
++ console_unlock();
++
++ return 0;
++}
++
++/*
++ * Resumes the framebuffer and unblanks the screen. Power management support
++ */
++static int mxcfb_resume(struct platform_device *pdev)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ console_lock();
++ mxcfb_blank(mxc_fbi->next_blank, fbi);
++ fb_set_suspend(fbi, 0);
++ console_unlock();
++
++ if (mxc_fbi->ovfbi) {
++ struct mxcfb_info *mxc_fbi_fg =
++ (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++ console_lock();
++ mxcfb_blank(mxc_fbi_fg->next_blank, mxc_fbi->ovfbi);
++ fb_set_suspend(mxc_fbi->ovfbi, 0);
++ console_unlock();
++ }
++
++ return 0;
++}
++
++/*
++ * Main framebuffer functions
++ */
++
++/*!
++ * Allocates the DRAM memory for the frame buffer. This buffer is remapped
++ * into a non-cached, non-buffered, memory region to allow palette and pixel
++ * writes to occur without flushing the cache. Once this area is remapped,
++ * all virtual memory access to the video memory should occur at the new region.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxcfb_map_video_memory(struct fb_info *fbi)
++{
++ if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
++ fbi->fix.smem_len = fbi->var.yres_virtual *
++ fbi->fix.line_length;
++
++ fbi->screen_base = dma_alloc_writecombine(fbi->device,
++ fbi->fix.smem_len,
++ (dma_addr_t *)&fbi->fix.smem_start,
++ GFP_DMA | GFP_KERNEL);
++ if (fbi->screen_base == 0) {
++ dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
++ fbi->fix.smem_len = 0;
++ fbi->fix.smem_start = 0;
++ return -EBUSY;
++ }
++
++ dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
++ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
++
++ fbi->screen_size = fbi->fix.smem_len;
++
++ /* Clear the screen */
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ return 0;
++}
++
++/*!
++ * De-allocates the DRAM memory for the frame buffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxcfb_unmap_video_memory(struct fb_info *fbi)
++{
++ dma_free_writecombine(fbi->device, fbi->fix.smem_len,
++ fbi->screen_base, fbi->fix.smem_start);
++ fbi->screen_base = 0;
++ fbi->fix.smem_start = 0;
++ fbi->fix.smem_len = 0;
++ return 0;
++}
++
++/*!
++ * Initializes the framebuffer information pointer. After allocating
++ * sufficient memory for the framebuffer structure, the fields are
++ * filled with custom information passed in from the configurable
++ * structures. This includes information such as bits per pixel,
++ * color maps, screen width/height and RGBA offsets.
++ *
++ * @return Framebuffer structure initialized with our information
++ */
++static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops)
++{
++ struct fb_info *fbi;
++ struct mxcfb_info *mxcfbi;
++
++ /*
++ * Allocate sufficient memory for the fb structure
++ */
++ fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev);
++ if (!fbi)
++ return NULL;
++
++ mxcfbi = (struct mxcfb_info *)fbi->par;
++
++ fbi->var.activate = FB_ACTIVATE_NOW;
++
++ fbi->fbops = ops;
++ fbi->flags = FBINFO_FLAG_DEFAULT;
++ fbi->pseudo_palette = mxcfbi->pseudo_palette;
++
++ /*
++ * Allocate colormap
++ */
++ fb_alloc_cmap(&fbi->cmap, 16, 0);
++
++ return fbi;
++}
++
++static ssize_t show_disp_chan(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++
++ if (mxcfbi->ipu_ch == MEM_BG_SYNC)
++ return sprintf(buf, "2-layer-fb-bg\n");
++ else if (mxcfbi->ipu_ch == MEM_FG_SYNC)
++ return sprintf(buf, "2-layer-fb-fg\n");
++ else if (mxcfbi->ipu_ch == MEM_DC_SYNC)
++ return sprintf(buf, "1-layer-fb\n");
++ else
++ return sprintf(buf, "err: no display chan\n");
++}
++
++static ssize_t swap_disp_chan(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++ struct mxcfb_info *fg_mxcfbi = NULL;
++
++ console_lock();
++ /* swap only happen between DP-BG and DC, while DP-FG disable */
++ if (((mxcfbi->ipu_ch == MEM_BG_SYNC) &&
++ (strstr(buf, "1-layer-fb") != NULL)) ||
++ ((mxcfbi->ipu_ch == MEM_DC_SYNC) &&
++ (strstr(buf, "2-layer-fb-bg") != NULL))) {
++ struct fb_info *fbi_fg;
++
++ fbi_fg = found_registered_fb(MEM_FG_SYNC, mxcfbi->ipu_id);
++ if (fbi_fg)
++ fg_mxcfbi = (struct mxcfb_info *)fbi_fg->par;
++
++ if (!fg_mxcfbi ||
++ fg_mxcfbi->cur_blank == FB_BLANK_UNBLANK) {
++ dev_err(dev,
++ "Can not switch while fb2(fb-fg) is on.\n");
++ console_unlock();
++ return count;
++ }
++
++ if (swap_channels(info) < 0)
++ dev_err(dev, "Swap display channel failed.\n");
++ }
++
++ console_unlock();
++ return count;
++}
++static DEVICE_ATTR(fsl_disp_property, 644, show_disp_chan, swap_disp_chan);
++
++static ssize_t show_disp_dev(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++
++ if (mxcfbi->ipu_ch == MEM_FG_SYNC)
++ return sprintf(buf, "overlay\n");
++ else
++ return sprintf(buf, "%s\n", mxcfbi->dispdrv->drv->name);
++}
++static DEVICE_ATTR(fsl_disp_dev_property, S_IRUGO, show_disp_dev, NULL);
++
++static int mxcfb_dispdrv_init(struct platform_device *pdev,
++ struct fb_info *fbi)
++{
++ struct ipuv3_fb_platform_data *plat_data = pdev->dev.platform_data;
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++ struct mxc_dispdrv_setting setting;
++ char disp_dev[32], *default_dev = "lcd";
++ int ret = 0;
++
++ setting.if_fmt = plat_data->interface_pix_fmt;
++ setting.dft_mode_str = plat_data->mode_str;
++ setting.default_bpp = plat_data->default_bpp;
++ if (!setting.default_bpp)
++ setting.default_bpp = 16;
++ setting.fbi = fbi;
++ if (!strlen(plat_data->disp_dev)) {
++ memcpy(disp_dev, default_dev, strlen(default_dev));
++ disp_dev[strlen(default_dev)] = '\0';
++ } else {
++ memcpy(disp_dev, plat_data->disp_dev,
++ strlen(plat_data->disp_dev));
++ disp_dev[strlen(plat_data->disp_dev)] = '\0';
++ }
++
++ dev_info(&pdev->dev, "register mxc display driver %s\n", disp_dev);
++
++ mxcfbi->dispdrv = mxc_dispdrv_gethandle(disp_dev, &setting);
++ if (IS_ERR(mxcfbi->dispdrv)) {
++ ret = PTR_ERR(mxcfbi->dispdrv);
++ dev_err(&pdev->dev, "NO mxc display driver found!\n");
++ return ret;
++ } else {
++ /* fix-up */
++ mxcfbi->ipu_di_pix_fmt = setting.if_fmt;
++ mxcfbi->default_bpp = setting.default_bpp;
++
++ /* setting */
++ mxcfbi->ipu_id = setting.dev_id;
++ mxcfbi->ipu_di = setting.disp_id;
++ dev_dbg(&pdev->dev, "di_pixfmt:0x%x, bpp:0x%x, di:%d, ipu:%d\n",
++ setting.if_fmt, setting.default_bpp,
++ setting.disp_id, setting.dev_id);
++ }
++
++ return ret;
++}
++
++/*
++ * Parse user specified options (`video=trident:')
++ * example:
++ * video=mxcfb0:dev=lcd,800x480M-16@55,if=RGB565,bpp=16,noaccel
++ * video=mxcfb0:dev=lcd,800x480M-16@55,if=RGB565,fbpix=RGB565
++ */
++static int mxcfb_option_setup(struct platform_device *pdev, struct fb_info *fbi)
++{
++ struct ipuv3_fb_platform_data *pdata = pdev->dev.platform_data;
++ char *options, *opt, *fb_mode_str = NULL;
++ char name[] = "mxcfb0";
++ uint32_t fb_pix_fmt = 0;
++
++ name[5] += pdev->id;
++ if (fb_get_options(name, &options)) {
++ dev_err(&pdev->dev, "Can't get fb option for %s!\n", name);
++ return -ENODEV;
++ }
++
++ if (!options || !*options)
++ return 0;
++
++ while ((opt = strsep(&options, ",")) != NULL) {
++ if (!*opt)
++ continue;
++
++ if (!strncmp(opt, "dev=", 4)) {
++ memcpy(pdata->disp_dev, opt + 4, strlen(opt) - 4);
++ pdata->disp_dev[strlen(opt) - 4] = '\0';
++ } else if (!strncmp(opt, "if=", 3)) {
++ if (!strncmp(opt+3, "RGB24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(opt+3, "BGR24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(opt+3, "GBR24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(opt+3, "RGB565", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(opt+3, "RGB666", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(opt+3, "YUV444", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(opt+3, "LVDS666", 7))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(opt+3, "YUYV16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(opt+3, "UYVY16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(opt+3, "YVYU16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(opt+3, "VYUY16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_VYUY;
++ } else if (!strncmp(opt, "fbpix=", 6)) {
++ if (!strncmp(opt+6, "RGB24", 5))
++ fb_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(opt+6, "BGR24", 5))
++ fb_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(opt+6, "RGB32", 5))
++ fb_pix_fmt = IPU_PIX_FMT_RGB32;
++ else if (!strncmp(opt+6, "BGR32", 5))
++ fb_pix_fmt = IPU_PIX_FMT_BGR32;
++ else if (!strncmp(opt+6, "ABGR32", 6))
++ fb_pix_fmt = IPU_PIX_FMT_ABGR32;
++ else if (!strncmp(opt+6, "RGB565", 6))
++ fb_pix_fmt = IPU_PIX_FMT_RGB565;
++
++ if (fb_pix_fmt) {
++ pixfmt_to_var(fb_pix_fmt, &fbi->var);
++ pdata->default_bpp =
++ fbi->var.bits_per_pixel;
++ }
++ } else if (!strncmp(opt, "int_clk", 7)) {
++ pdata->int_clk = true;
++ continue;
++ } else if (!strncmp(opt, "bpp=", 4)) {
++ /* bpp setting cannot overwirte fbpix setting */
++ if (fb_pix_fmt)
++ continue;
++
++ pdata->default_bpp =
++ simple_strtoul(opt + 4, NULL, 0);
++
++ fb_pix_fmt = bpp_to_pixfmt(pdata->default_bpp);
++ if (fb_pix_fmt)
++ pixfmt_to_var(fb_pix_fmt, &fbi->var);
++ } else
++ fb_mode_str = opt;
++ }
++
++ if (fb_mode_str)
++ pdata->mode_str = fb_mode_str;
++
++ return 0;
++}
++
++static int mxcfb_register(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++ struct fb_videomode m;
++ int ret = 0;
++ char bg0_id[] = "DISP3 BG";
++ char bg1_id[] = "DISP3 BG - DI1";
++ char fg_id[] = "DISP3 FG";
++
++ if (mxcfbi->ipu_di == 0) {
++ bg0_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, bg0_id);
++ } else if (mxcfbi->ipu_di == 1) {
++ bg1_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, bg1_id);
++ } else { /* Overlay */
++ fg_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, fg_id);
++ }
++
++ mxcfb_check_var(&fbi->var, fbi);
++
++ mxcfb_set_fix(fbi);
++
++ /* Added first mode to fbi modelist. */
++ if (!fbi->modelist.next || !fbi->modelist.prev)
++ INIT_LIST_HEAD(&fbi->modelist);
++ fb_var_to_videomode(&m, &fbi->var);
++ fb_add_videomode(&m, &fbi->modelist);
++
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering EOF irq handler.\n");
++ ret = -EBUSY;
++ goto err0;
++ }
++ ipu_disable_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq);
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering NFACK irq handler.\n");
++ ret = -EBUSY;
++ goto err1;
++ }
++ ipu_disable_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq);
++
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq,
++ mxcfb_alpha_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering alpha irq "
++ "handler.\n");
++ ret = -EBUSY;
++ goto err2;
++ }
++
++ if (!mxcfbi->late_init) {
++ fbi->var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ ret = fb_set_var(fbi, &fbi->var);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ if (ret < 0) {
++ dev_err(fbi->device, "Error fb_set_var ret:%d\n", ret);
++ goto err3;
++ }
++
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ ret = fb_blank(fbi, FB_BLANK_UNBLANK);
++ console_unlock();
++ if (ret < 0) {
++ dev_err(fbi->device,
++ "Error fb_blank ret:%d\n", ret);
++ goto err4;
++ }
++ }
++ } else {
++ /*
++ * Setup the channel again though bootloader
++ * has done this, then set_par() can stop the
++ * channel neatly and re-initialize it .
++ */
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ _setup_disp_channel1(fbi);
++ ipu_enable_channel(mxcfbi->ipu, mxcfbi->ipu_ch);
++ console_unlock();
++ }
++ }
++
++
++ ret = register_framebuffer(fbi);
++ if (ret < 0)
++ goto err5;
++
++ return ret;
++err5:
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ if (!mxcfbi->late_init)
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ else {
++ ipu_disable_channel(mxcfbi->ipu, mxcfbi->ipu_ch,
++ true);
++ ipu_uninit_channel(mxcfbi->ipu, mxcfbi->ipu_ch);
++ }
++ console_unlock();
++ }
++err4:
++err3:
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq, fbi);
++err2:
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq, fbi);
++err1:
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, fbi);
++err0:
++ return ret;
++}
++
++static void mxcfb_unregister(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq, fbi);
++ if (mxcfbi->ipu_ch_irq)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, fbi);
++ if (mxcfbi->ipu_ch_nf_irq)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq, fbi);
++
++ unregister_framebuffer(fbi);
++}
++
++static int mxcfb_setup_overlay(struct platform_device *pdev,
++ struct fb_info *fbi_bg, struct resource *res)
++{
++ struct fb_info *ovfbi;
++ struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
++ struct mxcfb_info *mxcfbi_fg;
++ int ret = 0;
++
++ ovfbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
++ if (!ovfbi) {
++ ret = -ENOMEM;
++ goto init_ovfbinfo_failed;
++ }
++ mxcfbi_fg = (struct mxcfb_info *)ovfbi->par;
++
++ mxcfbi_fg->ipu = ipu_get_soc(mxcfbi_bg->ipu_id);
++ if (IS_ERR(mxcfbi_fg->ipu)) {
++ ret = -ENODEV;
++ goto get_ipu_failed;
++ }
++ mxcfbi_fg->ipu_id = mxcfbi_bg->ipu_id;
++ mxcfbi_fg->ipu_ch_irq = IPU_IRQ_FG_SYNC_EOF;
++ mxcfbi_fg->ipu_ch_nf_irq = IPU_IRQ_FG_SYNC_NFACK;
++ mxcfbi_fg->ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
++ mxcfbi_fg->ipu_ch = MEM_FG_SYNC;
++ mxcfbi_fg->ipu_di = -1;
++ mxcfbi_fg->ipu_di_pix_fmt = mxcfbi_bg->ipu_di_pix_fmt;
++ mxcfbi_fg->overlay = true;
++ mxcfbi_fg->cur_blank = mxcfbi_fg->next_blank = FB_BLANK_POWERDOWN;
++
++ /* Need dummy values until real panel is configured */
++ ovfbi->var.xres = 240;
++ ovfbi->var.yres = 320;
++
++ if (res && res->start && res->end) {
++ ovfbi->fix.smem_len = res->end - res->start + 1;
++ ovfbi->fix.smem_start = res->start;
++ ovfbi->screen_base = ioremap(
++ ovfbi->fix.smem_start,
++ ovfbi->fix.smem_len);
++ }
++
++ ret = mxcfb_register(ovfbi);
++ if (ret < 0)
++ goto register_ov_failed;
++
++ mxcfbi_bg->ovfbi = ovfbi;
++
++ return ret;
++
++register_ov_failed:
++get_ipu_failed:
++ fb_dealloc_cmap(&ovfbi->cmap);
++ framebuffer_release(ovfbi);
++init_ovfbinfo_failed:
++ return ret;
++}
++
++static void mxcfb_unsetup_overlay(struct fb_info *fbi_bg)
++{
++ struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
++ struct fb_info *ovfbi = mxcfbi_bg->ovfbi;
++
++ mxcfb_unregister(ovfbi);
++
++ if (&ovfbi->cmap)
++ fb_dealloc_cmap(&ovfbi->cmap);
++ framebuffer_release(ovfbi);
++}
++
++static bool ipu_usage[2][2];
++static int ipu_test_set_usage(int ipu, int di)
++{
++ if (ipu_usage[ipu][di])
++ return -EBUSY;
++ else
++ ipu_usage[ipu][di] = true;
++ return 0;
++}
++
++static void ipu_clear_usage(int ipu, int di)
++{
++ ipu_usage[ipu][di] = false;
++}
++
++static int mxcfb_get_of_property(struct platform_device *pdev,
++ struct ipuv3_fb_platform_data *plat_data)
++{
++ struct device_node *np = pdev->dev.of_node;
++ const char *disp_dev;
++ const char *mode_str;
++ const char *pixfmt;
++ int err;
++ int len;
++ u32 bpp, int_clk;
++ u32 late_init;
++
++ err = of_property_read_string(np, "disp_dev", &disp_dev);
++ if (err < 0) {
++ dev_dbg(&pdev->dev, "get of property disp_dev fail\n");
++ return err;
++ }
++ err = of_property_read_string(np, "mode_str", &mode_str);
++ if (err < 0) {
++ dev_dbg(&pdev->dev, "get of property mode_str fail\n");
++ return err;
++ }
++ err = of_property_read_string(np, "interface_pix_fmt", &pixfmt);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property pix fmt fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "default_bpp", &bpp);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property bpp fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "int_clk", &int_clk);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property int_clk fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "late_init", &late_init);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property late_init fail\n");
++ return err;
++ }
++
++ if (!strncmp(pixfmt, "RGB24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(pixfmt, "BGR24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(pixfmt, "GBR24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(pixfmt, "RGB565", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(pixfmt, "RGB666", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(pixfmt, "YUV444", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(pixfmt, "LVDS666", 7))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(pixfmt, "YUYV16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(pixfmt, "UYVY16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(pixfmt, "YVYU16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(pixfmt, "VYUY16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_VYUY;
++ else {
++ dev_err(&pdev->dev, "err interface_pix_fmt!\n");
++ return -ENOENT;
++ }
++
++ len = min(sizeof(plat_data->disp_dev) - 1, strlen(disp_dev));
++ memcpy(plat_data->disp_dev, disp_dev, len);
++ plat_data->disp_dev[len] = '\0';
++ plat_data->mode_str = (char *)mode_str;
++ plat_data->default_bpp = bpp;
++ plat_data->int_clk = (bool)int_clk;
++ plat_data->late_init = (bool)late_init;
++ return err;
++}
++
++/*!
++ * Probe routine for the framebuffer driver. It is called during the
++ * driver binding process. The following functions are performed in
++ * this routine: Framebuffer initialization, Memory allocation and
++ * mapping, Framebuffer registration, IPU initialization.
++ *
++ * @return Appropriate error code to the kernel common code
++ */
++static int mxcfb_probe(struct platform_device *pdev)
++{
++ struct ipuv3_fb_platform_data *plat_data;
++ struct fb_info *fbi;
++ struct mxcfb_info *mxcfbi;
++ struct resource *res;
++ int ret = 0;
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ pdev->id = of_alias_get_id(pdev->dev.of_node, "mxcfb");
++ if (pdev->id < 0) {
++ dev_err(&pdev->dev, "can not get alias id\n");
++ return pdev->id;
++ }
++
++ plat_data = devm_kzalloc(&pdev->dev, sizeof(struct
++ ipuv3_fb_platform_data), GFP_KERNEL);
++ if (!plat_data)
++ return -ENOMEM;
++ pdev->dev.platform_data = plat_data;
++
++ ret = mxcfb_get_of_property(pdev, plat_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get mxcfb of property fail\n");
++ return ret;
++ }
++
++ /* Initialize FB structures */
++ fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
++ if (!fbi) {
++ ret = -ENOMEM;
++ goto init_fbinfo_failed;
++ }
++
++ ret = mxcfb_option_setup(pdev, fbi);
++ if (ret)
++ goto get_fb_option_failed;
++
++ mxcfbi = (struct mxcfb_info *)fbi->par;
++ mxcfbi->ipu_int_clk = plat_data->int_clk;
++ mxcfbi->late_init = plat_data->late_init;
++ mxcfbi->first_set_par = true;
++ ret = mxcfb_dispdrv_init(pdev, fbi);
++ if (ret < 0)
++ goto init_dispdrv_failed;
++
++ ret = ipu_test_set_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "ipu%d-di%d already in use\n",
++ mxcfbi->ipu_id, mxcfbi->ipu_di);
++ goto ipu_in_busy;
++ }
++
++ if (mxcfbi->dispdrv->drv->post_init) {
++ ret = mxcfbi->dispdrv->drv->post_init(mxcfbi->dispdrv,
++ mxcfbi->ipu_id,
++ mxcfbi->ipu_di);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "post init failed\n");
++ goto post_init_failed;
++ }
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res && res->start && res->end) {
++ fbi->fix.smem_len = res->end - res->start + 1;
++ fbi->fix.smem_start = res->start;
++ fbi->screen_base = ioremap(fbi->fix.smem_start, fbi->fix.smem_len);
++ /* Do not clear the fb content drawn in bootloader. */
++ if (!mxcfbi->late_init)
++ memset(fbi->screen_base, 0, fbi->fix.smem_len);
++ }
++
++ mxcfbi->ipu = ipu_get_soc(mxcfbi->ipu_id);
++ if (IS_ERR(mxcfbi->ipu)) {
++ ret = -ENODEV;
++ goto get_ipu_failed;
++ }
++
++ /* first user uses DP with alpha feature */
++ if (!g_dp_in_use[mxcfbi->ipu_id]) {
++ mxcfbi->ipu_ch_irq = IPU_IRQ_BG_SYNC_EOF;
++ mxcfbi->ipu_ch_nf_irq = IPU_IRQ_BG_SYNC_NFACK;
++ mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
++ mxcfbi->ipu_ch = MEM_BG_SYNC;
++ /* Unblank the primary fb only by default */
++ if (pdev->id == 0)
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK;
++ else
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
++
++ ret = mxcfb_register(fbi);
++ if (ret < 0)
++ goto mxcfb_register_failed;
++
++ ipu_disp_set_global_alpha(mxcfbi->ipu, mxcfbi->ipu_ch,
++ true, 0x80);
++ ipu_disp_set_color_key(mxcfbi->ipu, mxcfbi->ipu_ch, false, 0);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ ret = mxcfb_setup_overlay(pdev, fbi, res);
++
++ if (ret < 0) {
++ mxcfb_unregister(fbi);
++ goto mxcfb_setupoverlay_failed;
++ }
++
++ g_dp_in_use[mxcfbi->ipu_id] = true;
++
++ ret = device_create_file(mxcfbi->ovfbi->dev,
++ &dev_attr_fsl_disp_property);
++ if (ret)
++ dev_err(mxcfbi->ovfbi->dev, "Error %d on creating "
++ "file for disp property\n",
++ ret);
++
++ ret = device_create_file(mxcfbi->ovfbi->dev,
++ &dev_attr_fsl_disp_dev_property);
++ if (ret)
++ dev_err(mxcfbi->ovfbi->dev, "Error %d on creating "
++ "file for disp device "
++ "propety\n", ret);
++ } else {
++ mxcfbi->ipu_ch_irq = IPU_IRQ_DC_SYNC_EOF;
++ mxcfbi->ipu_ch_nf_irq = IPU_IRQ_DC_SYNC_NFACK;
++ mxcfbi->ipu_alp_ch_irq = -1;
++ mxcfbi->ipu_ch = MEM_DC_SYNC;
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
++
++ ret = mxcfb_register(fbi);
++ if (ret < 0)
++ goto mxcfb_register_failed;
++ }
++
++ platform_set_drvdata(pdev, fbi);
++
++ ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_property);
++ if (ret)
++ dev_err(&pdev->dev, "Error %d on creating file for disp "
++ "property\n", ret);
++
++ ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_dev_property);
++ if (ret)
++ dev_err(&pdev->dev, "Error %d on creating file for disp "
++ " device propety\n", ret);
++
++ return 0;
++
++mxcfb_setupoverlay_failed:
++mxcfb_register_failed:
++get_ipu_failed:
++post_init_failed:
++ ipu_clear_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
++ipu_in_busy:
++init_dispdrv_failed:
++ fb_dealloc_cmap(&fbi->cmap);
++ framebuffer_release(fbi);
++get_fb_option_failed:
++init_fbinfo_failed:
++ return ret;
++}
++
++static int mxcfb_remove(struct platform_device *pdev)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ if (!fbi)
++ return 0;
++
++ device_remove_file(fbi->dev, &dev_attr_fsl_disp_dev_property);
++ device_remove_file(fbi->dev, &dev_attr_fsl_disp_property);
++ mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
++ mxcfb_unregister(fbi);
++ mxcfb_unmap_video_memory(fbi);
++
++ if (mxc_fbi->ovfbi) {
++ device_remove_file(mxc_fbi->ovfbi->dev,
++ &dev_attr_fsl_disp_dev_property);
++ device_remove_file(mxc_fbi->ovfbi->dev,
++ &dev_attr_fsl_disp_property);
++ mxcfb_blank(FB_BLANK_POWERDOWN, mxc_fbi->ovfbi);
++ mxcfb_unsetup_overlay(fbi);
++ mxcfb_unmap_video_memory(mxc_fbi->ovfbi);
++ }
++
++ ipu_clear_usage(mxc_fbi->ipu_id, mxc_fbi->ipu_di);
++ if (&fbi->cmap)
++ fb_dealloc_cmap(&fbi->cmap);
++ framebuffer_release(fbi);
++ return 0;
++}
++
++static const struct of_device_id imx_mxcfb_dt_ids[] = {
++ { .compatible = "fsl,mxc_sdc_fb"},
++ { /* sentinel */ }
++};
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxcfb_driver = {
++ .driver = {
++ .name = MXCFB_NAME,
++ .of_match_table = imx_mxcfb_dt_ids,
++ },
++ .probe = mxcfb_probe,
++ .remove = mxcfb_remove,
++ .suspend = mxcfb_suspend,
++ .resume = mxcfb_resume,
++};
++
++/*!
++ * Main entry function for the framebuffer. The function registers the power
++ * management callback functions with the kernel and also registers the MXCFB
++ * callback functions with the core Linux framebuffer driver \b fbmem.c
++ *
++ * @return Error code indicating success or failure
++ */
++int __init mxcfb_init(void)
++{
++ return platform_driver_register(&mxcfb_driver);
++}
++
++void mxcfb_exit(void)
++{
++ platform_driver_unregister(&mxcfb_driver);
++}
++
++module_init(mxcfb_init);
++module_exit(mxcfb_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC framebuffer driver");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("fb");
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxc_lcdif.c linux-linaro-stable-mx6/drivers/video/mxc/mxc_lcdif.c
+--- linux-3.10.30.orig/drivers/video/mxc/mxc_lcdif.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxc_lcdif.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,235 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/init.h>
++#include <linux/ipu.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_device.h>
++
++#include "mxc_dispdrv.h"
++
++struct mxc_lcd_platform_data {
++ u32 default_ifmt;
++ u32 ipu_id;
++ u32 disp_id;
++};
++
++struct mxc_lcdif_data {
++ struct platform_device *pdev;
++ struct mxc_dispdrv_handle *disp_lcdif;
++};
++
++#define DISPDRV_LCD "lcd"
++
++static struct fb_videomode lcdif_modedb[] = {
++ {
++ /* 800x480 @ 57 Hz , pixel clk @ 27MHz */
++ "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
++ FB_SYNC_CLK_LAT_FALL,
++ FB_VMODE_NONINTERLACED,
++ 0,},
++ {
++ /* 800x480 @ 60 Hz , pixel clk @ 32MHz */
++ "SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10,
++ FB_SYNC_CLK_LAT_FALL,
++ FB_VMODE_NONINTERLACED,
++ 0,},
++};
++static int lcdif_modedb_sz = ARRAY_SIZE(lcdif_modedb);
++
++static int lcdif_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret, i;
++ struct mxc_lcdif_data *lcdif = mxc_dispdrv_getdata(disp);
++ struct mxc_lcd_platform_data *plat_data
++ = lcdif->pdev->dev.platform_data;
++ struct fb_videomode *modedb = lcdif_modedb;
++ int modedb_sz = lcdif_modedb_sz;
++
++ /* use platform defined ipu/di */
++ setting->dev_id = plat_data->ipu_id;
++ setting->disp_id = plat_data->disp_id;
++
++ ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
++ modedb, modedb_sz, NULL, setting->default_bpp);
++ if (!ret) {
++ fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
++ setting->if_fmt = plat_data->default_ifmt;
++ }
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < modedb_sz; i++) {
++ struct fb_videomode m;
++ fb_var_to_videomode(&m, &setting->fbi->var);
++ if (fb_mode_is_equal(&m, &modedb[i])) {
++ fb_add_videomode(&modedb[i],
++ &setting->fbi->modelist);
++ break;
++ }
++ }
++
++ return ret;
++}
++
++void lcdif_deinit(struct mxc_dispdrv_handle *disp)
++{
++ /*TODO*/
++}
++
++static struct mxc_dispdrv_driver lcdif_drv = {
++ .name = DISPDRV_LCD,
++ .init = lcdif_init,
++ .deinit = lcdif_deinit,
++};
++
++static int lcd_get_of_property(struct platform_device *pdev,
++ struct mxc_lcd_platform_data *plat_data)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++ u32 ipu_id, disp_id;
++ const char *default_ifmt;
++
++ err = of_property_read_string(np, "default_ifmt", &default_ifmt);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property default_ifmt fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "disp_id", &disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
++ return err;
++ }
++
++ plat_data->ipu_id = ipu_id;
++ plat_data->disp_id = disp_id;
++ if (!strncmp(default_ifmt, "RGB24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(default_ifmt, "BGR24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(default_ifmt, "GBR24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(default_ifmt, "RGB565", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(default_ifmt, "RGB666", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(default_ifmt, "YUV444", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(default_ifmt, "LVDS666", 7))
++ plat_data->default_ifmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(default_ifmt, "YUYV16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(default_ifmt, "UYVY16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(default_ifmt, "YVYU16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(default_ifmt, "VYUY16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_VYUY;
++ else {
++ dev_err(&pdev->dev, "err default_ifmt!\n");
++ return -ENOENT;
++ }
++
++ return err;
++}
++
++static int mxc_lcdif_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct pinctrl *pinctrl;
++ struct mxc_lcdif_data *lcdif;
++ struct mxc_lcd_platform_data *plat_data;
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ lcdif = devm_kzalloc(&pdev->dev, sizeof(struct mxc_lcdif_data),
++ GFP_KERNEL);
++ if (!lcdif)
++ return -ENOMEM;
++ plat_data = devm_kzalloc(&pdev->dev,
++ sizeof(struct mxc_lcd_platform_data),
++ GFP_KERNEL);
++ if (!plat_data)
++ return -ENOMEM;
++ pdev->dev.platform_data = plat_data;
++
++ ret = lcd_get_of_property(pdev, plat_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get lcd of property fail\n");
++ return ret;
++ }
++
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "can't get/select pinctrl\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ lcdif->pdev = pdev;
++ lcdif->disp_lcdif = mxc_dispdrv_register(&lcdif_drv);
++ mxc_dispdrv_setdata(lcdif->disp_lcdif, lcdif);
++
++ dev_set_drvdata(&pdev->dev, lcdif);
++ dev_dbg(&pdev->dev, "%s exit\n", __func__);
++
++ return ret;
++}
++
++static int mxc_lcdif_remove(struct platform_device *pdev)
++{
++ struct mxc_lcdif_data *lcdif = dev_get_drvdata(&pdev->dev);
++
++ mxc_dispdrv_puthandle(lcdif->disp_lcdif);
++ mxc_dispdrv_unregister(lcdif->disp_lcdif);
++ kfree(lcdif);
++ return 0;
++}
++
++static const struct of_device_id imx_lcd_dt_ids[] = {
++ { .compatible = "fsl,lcd"},
++ { /* sentinel */ }
++};
++static struct platform_driver mxc_lcdif_driver = {
++ .driver = {
++ .name = "mxc_lcdif",
++ .of_match_table = imx_lcd_dt_ids,
++ },
++ .probe = mxc_lcdif_probe,
++ .remove = mxc_lcdif_remove,
++};
++
++static int __init mxc_lcdif_init(void)
++{
++ return platform_driver_register(&mxc_lcdif_driver);
++}
++
++static void __exit mxc_lcdif_exit(void)
++{
++ platform_driver_unregister(&mxc_lcdif_driver);
++}
++
++module_init(mxc_lcdif_init);
++module_exit(mxc_lcdif_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX ipuv3 LCD extern port driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/video/mxc/mxsfb_sii902x.c linux-linaro-stable-mx6/drivers/video/mxc/mxsfb_sii902x.c
+--- linux-3.10.30.orig/drivers/video/mxc/mxsfb_sii902x.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxc/mxsfb_sii902x.c 2014-05-15 20:34:09.738098449 +0200
+@@ -0,0 +1,532 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for Sii902x.
++ */
++
++/*!
++ * @file mxsfb_sii902x.c
++ *
++ * @brief Frame buffer driver for SII902x
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/console.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/i2c.h>
++#include <linux/fsl_devices.h>
++#include <linux/interrupt.h>
++#include <linux/reset.h>
++#include <asm/mach-types.h>
++#include <video/mxc_edid.h>
++
++#define SII_EDID_LEN 512
++#define DRV_NAME "sii902x"
++
++struct sii902x_data {
++ struct i2c_client *client;
++ struct delayed_work det_work;
++ struct fb_info *fbi;
++ struct mxc_edid_cfg edid_cfg;
++ u8 cable_plugin;
++ u8 edid[SII_EDID_LEN];
++ bool waiting_for_fb;
++ bool dft_mode_set;
++ const char *mode_str;
++ int bits_per_pixel;
++} sii902x;
++
++static void sii902x_poweron(void);
++static void sii902x_poweroff(void);
++
++#ifdef DEBUG
++static void dump_fb_videomode(struct fb_videomode *m)
++{
++ pr_debug("fb_videomode = %d %d %d %d %d %d %d %d %d %d %d %d %d\n",
++ m->refresh, m->xres, m->yres, m->pixclock, m->left_margin,
++ m->right_margin, m->upper_margin, m->lower_margin,
++ m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
++}
++#else
++static void dump_fb_videomode(struct fb_videomode *m)
++{}
++#endif
++
++static __attribute__ ((unused)) void dump_regs(u8 reg, int len)
++{
++ u8 buf[50];
++ int i;
++
++ i2c_smbus_read_i2c_block_data(sii902x.client, reg, len, buf);
++ for (i = 0; i < len; i++)
++ dev_dbg(&sii902x.client->dev, "reg[0x%02X]: 0x%02X\n",
++ i+reg, buf[i]);
++}
++
++static ssize_t sii902x_show_name(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ strcpy(buf, sii902x.fbi->fix.id);
++ sprintf(buf+strlen(buf), "\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(fb_name, S_IRUGO, sii902x_show_name, NULL);
++
++static ssize_t sii902x_show_state(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ if (sii902x.cable_plugin == 0)
++ strcpy(buf, "plugout\n");
++ else
++ strcpy(buf, "plugin\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(cable_state, S_IRUGO, sii902x_show_state, NULL);
++
++static ssize_t sii902x_show_edid(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ int i, j, len = 0;
++
++ for (j = 0; j < SII_EDID_LEN/16; j++) {
++ for (i = 0; i < 16; i++)
++ len += sprintf(buf+len, "0x%02X ",
++ sii902x.edid[j*16 + i]);
++ len += sprintf(buf+len, "\n");
++ }
++
++ return len;
++}
++
++static DEVICE_ATTR(edid, S_IRUGO, sii902x_show_edid, NULL);
++
++static void sii902x_setup(struct fb_info *fbi)
++{
++ u16 data[4];
++ u32 refresh;
++ u8 *tmp;
++ int i;
++
++ dev_dbg(&sii902x.client->dev, "Sii902x: setup..\n");
++
++ /* Power up */
++ i2c_smbus_write_byte_data(sii902x.client, 0x1E, 0x00);
++
++ /* set TPI video mode */
++ data[0] = PICOS2KHZ(fbi->var.pixclock) / 10;
++ data[2] = fbi->var.hsync_len + fbi->var.left_margin +
++ fbi->var.xres + fbi->var.right_margin;
++ data[3] = fbi->var.vsync_len + fbi->var.upper_margin +
++ fbi->var.yres + fbi->var.lower_margin;
++ refresh = data[2] * data[3];
++ refresh = (PICOS2KHZ(fbi->var.pixclock) * 1000) / refresh;
++ data[1] = refresh * 100;
++ tmp = (u8 *)data;
++ for (i = 0; i < 8; i++)
++ i2c_smbus_write_byte_data(sii902x.client, i, tmp[i]);
++
++ /* input bus/pixel: full pixel wide (24bit), rising edge */
++ i2c_smbus_write_byte_data(sii902x.client, 0x08, 0x70);
++ /* Set input format to RGB */
++ i2c_smbus_write_byte_data(sii902x.client, 0x09, 0x00);
++ /* set output format to RGB */
++ i2c_smbus_write_byte_data(sii902x.client, 0x0A, 0x00);
++ /* audio setup */
++ i2c_smbus_write_byte_data(sii902x.client, 0x25, 0x00);
++ i2c_smbus_write_byte_data(sii902x.client, 0x26, 0x40);
++ i2c_smbus_write_byte_data(sii902x.client, 0x27, 0x00);
++}
++
++#ifdef CONFIG_FB_MODE_HELPERS
++static int sii902x_read_edid(struct fb_info *fbi)
++{
++ int old, dat, ret, cnt = 100;
++ unsigned short addr = 0x50;
++
++ dev_dbg(&sii902x.client->dev, "%s\n", __func__);
++
++ old = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
++
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, old | 0x4);
++ do {
++ cnt--;
++ msleep(10);
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
++ } while ((!(dat & 0x2)) && cnt);
++
++ if (!cnt) {
++ ret = -1;
++ goto done;
++ }
++
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, old | 0x06);
++
++ /* edid reading */
++ ret = mxc_edid_read(sii902x.client->adapter, addr,
++ sii902x.edid, &sii902x.edid_cfg, fbi);
++
++ cnt = 100;
++ do {
++ cnt--;
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, old & ~0x6);
++ msleep(10);
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
++ } while ((dat & 0x6) && cnt);
++
++ if (!cnt)
++ ret = -1;
++
++done:
++
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, old);
++ return ret;
++}
++#else
++static int sii902x_read_edid(struct fb_info *fbi)
++{
++ return -1;
++}
++#endif
++
++static void sii902x_cable_connected(void)
++{
++ int i;
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++
++ if (sii902x_read_edid(sii902x.fbi) < 0)
++ dev_err(&sii902x.client->dev,
++ "Sii902x: read edid fail\n");
++ else {
++ if (sii902x.fbi->monspecs.modedb_len > 0) {
++
++ fb_destroy_modelist(&sii902x.fbi->modelist);
++
++ for (i = 0; i < sii902x.fbi->monspecs.modedb_len; i++) {
++
++ mode = &sii902x.fbi->monspecs.modedb[i];
++
++ if (!(mode->vmode & FB_VMODE_INTERLACED)) {
++
++ dev_dbg(&sii902x.client->dev, "Added mode %d:", i);
++ dev_dbg(&sii902x.client->dev,
++ "xres = %d, yres = %d, freq = %d, vmode = %d, flag = %d\n",
++ mode->xres, mode->yres, mode->refresh,
++ mode->vmode, mode->flag);
++
++ fb_add_videomode(mode, &sii902x.fbi->modelist);
++ }
++ }
++
++ /* Set the default mode only once. */
++ if (!sii902x.dft_mode_set &&
++ sii902x.mode_str && sii902x.bits_per_pixel) {
++
++ dev_dbg(&sii902x.client->dev, "%s: setting to default=%s bpp=%d\n",
++ __func__, sii902x.mode_str, sii902x.bits_per_pixel);
++
++ fb_find_mode(&sii902x.fbi->var, sii902x.fbi,
++ sii902x.mode_str, NULL, 0, NULL,
++ sii902x.bits_per_pixel);
++
++ sii902x.dft_mode_set = true;
++ }
++
++ fb_var_to_videomode(&m, &sii902x.fbi->var);
++ dump_fb_videomode(&m);
++
++ mode = fb_find_nearest_mode(&m,
++ &sii902x.fbi->modelist);
++
++ /* update fbi mode */
++ sii902x.fbi->mode = (struct fb_videomode *)mode;
++
++ fb_videomode_to_var(&sii902x.fbi->var, mode);
++
++ sii902x.fbi->var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ sii902x.fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_set_var(sii902x.fbi, &sii902x.fbi->var);
++ sii902x.fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ }
++ /* Power on sii902x */
++ sii902x_poweron();
++ }
++}
++
++static void det_worker(struct work_struct *work)
++{
++ int dat;
++ char event_string[16];
++ char *envp[] = { event_string, NULL };
++
++ dev_dbg(&sii902x.client->dev, "%s\n", __func__);
++
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x3D);
++ if (dat & 0x1) {
++ /* cable connection changes */
++ if (dat & 0x4) {
++ sii902x.cable_plugin = 1;
++ dev_dbg(&sii902x.client->dev, "EVENT=plugin\n");
++ sprintf(event_string, "EVENT=plugin");
++ sii902x_cable_connected();
++ } else {
++ sii902x.cable_plugin = 0;
++ dev_dbg(&sii902x.client->dev, "EVENT=plugout\n");
++ sprintf(event_string, "EVENT=plugout");
++ /* Power off sii902x */
++ sii902x_poweroff();
++ }
++ kobject_uevent_env(&sii902x.client->dev.kobj, KOBJ_CHANGE, envp);
++ }
++ i2c_smbus_write_byte_data(sii902x.client, 0x3D, dat);
++
++ dev_dbg(&sii902x.client->dev, "exit %s\n", __func__);
++
++}
++
++static irqreturn_t sii902x_detect_handler(int irq, void *data)
++{
++ if (sii902x.fbi)
++ schedule_delayed_work(&(sii902x.det_work), msecs_to_jiffies(20));
++ else
++ sii902x.waiting_for_fb = true;
++
++ return IRQ_HANDLED;
++}
++
++static int sii902x_fb_event(struct notifier_block *nb, unsigned long val, void *v)
++{
++ struct fb_event *event = v;
++ struct fb_info *fbi = event->info;
++
++ dev_dbg(&sii902x.client->dev, "%s event=0x%lx\n", __func__, val);
++
++ switch (val) {
++ case FB_EVENT_FB_REGISTERED:
++ if (sii902x.fbi == NULL) {
++ sii902x.fbi = fbi;
++ if (sii902x.waiting_for_fb)
++ det_worker(NULL);
++ }
++ fb_show_logo(fbi, 0);
++ break;
++ case FB_EVENT_MODE_CHANGE:
++ sii902x_setup(fbi);
++ break;
++ case FB_EVENT_BLANK:
++ if (*((int *)event->data) == FB_BLANK_UNBLANK) {
++ dev_dbg(&sii902x.client->dev, "FB_BLANK_UNBLANK\n");
++ sii902x_poweron();
++ } else {
++ dev_dbg(&sii902x.client->dev, "FB_BLANK_BLANK\n");
++ sii902x_poweroff();
++ }
++ break;
++ }
++ return 0;
++}
++
++static struct notifier_block nb = {
++ .notifier_call = sii902x_fb_event,
++};
++
++static int mxsfb_get_of_property(void)
++{
++ struct device_node *np = sii902x.client->dev.of_node;
++ const char *mode_str;
++ int bits_per_pixel, ret;
++
++ ret = of_property_read_string(np, "mode_str", &mode_str);
++ if (ret < 0) {
++ dev_warn(&sii902x.client->dev, "get of property mode_str fail\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "bits-per-pixel", &bits_per_pixel);
++ if (ret) {
++ dev_warn(&sii902x.client->dev, "get of property bpp fail\n");
++ return ret;
++ }
++
++ sii902x.mode_str = mode_str;
++ sii902x.bits_per_pixel = bits_per_pixel;
++
++ return ret;
++}
++
++static int sii902x_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ int i, dat, ret;
++ struct fb_info edid_fbi;
++
++ memset(&sii902x, 0, sizeof(sii902x));
++
++ sii902x.client = client;
++
++ dev_dbg(&sii902x.client->dev, "%s\n", __func__);;
++
++ /* Reset sii902x */
++ ret = device_reset(&sii902x.client->dev);
++ if (ret) {
++ dev_err(&sii902x.client->dev, "failed to reset: %d\n", ret);
++ return -ENODEV;
++ }
++
++ /* Set 902x in hardware TPI mode on and jump out of D3 state */
++ if (i2c_smbus_write_byte_data(sii902x.client, 0xc7, 0x00) < 0) {
++ dev_err(&sii902x.client->dev,
++ "Sii902x: cound not find device\n");
++ return -ENODEV;
++ }
++
++ /* read device ID */
++ for (i = 10; i > 0; i--) {
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1B);
++ printk(KERN_DEBUG "Sii902x: read id = 0x%02X", dat);
++ if (dat == 0xb0) {
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1C);
++ printk(KERN_DEBUG "-0x%02X", dat);
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1D);
++ printk(KERN_DEBUG "-0x%02X", dat);
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x30);
++ printk(KERN_DEBUG "-0x%02X\n", dat);
++ break;
++ }
++ }
++ if (i == 0) {
++ dev_err(&sii902x.client->dev,
++ "Sii902x: cound not find device\n");
++ return -ENODEV;
++ }
++
++ /* try to read edid */
++ ret = sii902x_read_edid(&edid_fbi);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev, "Can not read edid\n");
++
++ if (sii902x.client->irq) {
++ ret = request_irq(sii902x.client->irq, sii902x_detect_handler,
++ IRQF_TRIGGER_FALLING,
++ "SII902x_det", &sii902x);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev,
++ "Sii902x: cound not request det irq %d\n",
++ sii902x.client->irq);
++ else {
++ /*enable cable hot plug irq*/
++ i2c_smbus_write_byte_data(sii902x.client, 0x3c, 0x01);
++ INIT_DELAYED_WORK(&(sii902x.det_work), det_worker);
++ }
++ ret = device_create_file(&sii902x.client->dev, &dev_attr_fb_name);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev,
++ "Sii902x: cound not create sys node for fb name\n");
++ ret = device_create_file(&sii902x.client->dev, &dev_attr_cable_state);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev,
++ "Sii902x: cound not create sys node for cable state\n");
++ ret = device_create_file(&sii902x.client->dev, &dev_attr_edid);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev,
++ "Sii902x: cound not create sys node for edid\n");
++
++ }
++
++ mxsfb_get_of_property();
++ fb_register_client(&nb);
++
++ return 0;
++}
++
++static int sii902x_remove(struct i2c_client *client)
++{
++ fb_unregister_client(&nb);
++ sii902x_poweroff();
++
++ return 0;
++}
++
++static void sii902x_poweron(void)
++{
++ /* Turn on DVI or HDMI */
++ if (sii902x.edid_cfg.hdmi_cap)
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x01);
++ else
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x00);
++ return;
++}
++
++static void sii902x_poweroff(void)
++{
++ /* disable tmds before changing resolution */
++ if (sii902x.edid_cfg.hdmi_cap)
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x11);
++ else
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x10);
++
++ return;
++}
++
++static const struct i2c_device_id sii902x_id[] = {
++ { DRV_NAME, 0},
++ { },
++};
++MODULE_DEVICE_TABLE(i2c, sii902x_id);
++
++static const struct of_device_id sii902x_dt_ids[] = {
++ { .compatible = "SiI,sii902x", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, sii902x_dt_ids);
++
++static struct i2c_driver sii902x_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = sii902x_dt_ids,
++ },
++ .probe = sii902x_probe,
++ .remove = sii902x_remove,
++ .id_table = sii902x_id,
++};
++
++module_i2c_driver(sii902x_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("SII902x DVI/HDMI driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/drivers/video/mxsfb.c linux-linaro-stable-mx6/drivers/video/mxsfb.c
+--- linux-3.10.30.orig/drivers/video/mxsfb.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/mxsfb.c 2014-05-15 20:34:09.738098449 +0200
+@@ -4,7 +4,7 @@
+ * This code is based on:
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+@@ -39,15 +39,20 @@
+ * the required value in the imx_fb_videomode structure.
+ */
+
++#include <linux/busfreq-imx6.h>
++#include <linux/console.h>
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/interrupt.h>
+ #include <linux/clk.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/io.h>
+ #include <linux/pinctrl/consumer.h>
+ #include <linux/fb.h>
++#include <linux/mxcfb.h>
+ #include <linux/regulator/consumer.h>
+ #include <video/of_display_timing.h>
+ #include <video/videomode.h>
+@@ -96,9 +101,18 @@
+ #define CTRL_DF24 (1 << 1)
+ #define CTRL_RUN (1 << 0)
+
+-#define CTRL1_FIFO_CLEAR (1 << 21)
+-#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
+-#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
++#define CTRL1_RECOVERY_ON_UNDERFLOW (1 << 24)
++#define CTRL1_FIFO_CLEAR (1 << 21)
++#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
++#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
++#define CTRL1_OVERFLOW_IRQ_EN (1 << 15)
++#define CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
++#define CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
++#define CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
++#define CTRL1_OVERFLOW_IRQ (1 << 11)
++#define CTRL1_UNDERFLOW_IRQ (1 << 10)
++#define CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
++#define CTRL1_VSYNC_EDGE_IRQ (1 << 8)
+
+ #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
+ #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
+@@ -149,8 +163,8 @@
+ #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
+ #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
+
+-#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
+-#define MXSFB_SYNC_DOTCLK_FALLING_ACT (1 << 7) /* negtive edge sampling */
++#define FB_SYNC_OE_LOW_ACT 0x80000000
++#define FB_SYNC_CLK_LAT_FALL 0x40000000
+
+ enum mxsfb_devtype {
+ MXSFB_V3,
+@@ -171,15 +185,21 @@
+ struct mxsfb_info {
+ struct fb_info fb_info;
+ struct platform_device *pdev;
+- struct clk *clk;
++ struct clk *clk_pix;
++ struct clk *clk_axi;
++ bool clk_axi_enabled;
+ void __iomem *base; /* registers */
+ unsigned allocated_size;
+ int enabled;
+ unsigned ld_intf_width;
+ unsigned dotclk_delay;
+ const struct mxsfb_devdata *devdata;
+- u32 sync;
+ struct regulator *reg_lcd;
++ bool wait4vsync;
++ struct completion vsync_complete;
++ struct semaphore flip_sem;
++ int cur_blank;
++ int restore_blank;
+ };
+
+ #define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
+@@ -208,6 +228,29 @@
+
+ #define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
+
++static int mxsfb_map_videomem(struct fb_info *info);
++static int mxsfb_unmap_videomem(struct fb_info *info);
++
++/* enable lcdif axi clock */
++static inline void clk_enable_axi(struct mxsfb_info *host)
++{
++ if (!host->clk_axi_enabled && host &&
++ host->clk_axi && !IS_ERR(host->clk_axi)) {
++ clk_prepare_enable(host->clk_axi);
++ host->clk_axi_enabled = true;
++ }
++}
++
++/* disable lcdif axi clock */
++static inline void clk_disable_axi(struct mxsfb_info *host)
++{
++ if (host->clk_axi_enabled && host &&
++ host->clk_axi && !IS_ERR(host->clk_axi)) {
++ clk_disable_unprepare(host->clk_axi);
++ host->clk_axi_enabled = false;
++ }
++}
++
+ /* mask and shift depends on architecture */
+ static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
+ {
+@@ -282,6 +325,37 @@
+ return chan << bf->offset;
+ }
+
++static irqreturn_t mxsfb_irq_handler(int irq, void *dev_id)
++{
++ struct mxsfb_info *host = dev_id;
++ u32 status_lcd = readl(host->base + LCDC_CTRL1);
++
++ if ((status_lcd & CTRL1_VSYNC_EDGE_IRQ) &&
++ host->wait4vsync) {
++ writel(CTRL1_VSYNC_EDGE_IRQ_EN,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ host->wait4vsync = 0;
++ complete(&host->vsync_complete);
++ }
++
++ if (status_lcd & CTRL1_CUR_FRAME_DONE_IRQ) {
++ writel(CTRL1_CUR_FRAME_DONE_IRQ_EN,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ up(&host->flip_sem);
++ }
++
++ if (status_lcd & CTRL1_UNDERFLOW_IRQ) {
++ writel(CTRL1_UNDERFLOW_IRQ,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ }
++
++ if (status_lcd & CTRL1_OVERFLOW_IRQ) {
++ writel(CTRL1_OVERFLOW_IRQ,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ }
++ return IRQ_HANDLED;
++}
++
+ static int mxsfb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *fb_info)
+ {
+@@ -293,9 +367,10 @@
+ if (var->yres < MIN_YRES)
+ var->yres = MIN_YRES;
+
+- var->xres_virtual = var->xres;
+-
+- var->yres_virtual = var->yres;
++ if (var->xres_virtual < var->xres)
++ var->xres_virtual = var->xres;
++ if (var->yres_virtual < var->yres)
++ var->yres_virtual = var->yres;
+
+ switch (var->bits_per_pixel) {
+ case 16:
+@@ -352,8 +427,12 @@
+ }
+ }
+
+- clk_prepare_enable(host->clk);
+- clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
++ pm_runtime_get_sync(&host->pdev->dev);
++
++ clk_enable_axi(host);
++
++ clk_prepare_enable(host->clk_pix);
++ clk_set_rate(host->clk_pix, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
+
+ /* if it was disabled, re-enable the mode again */
+ writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
+@@ -363,8 +442,12 @@
+ reg |= VDCTRL4_SYNC_SIGNALS_ON;
+ writel(reg, host->base + LCDC_VDCTRL4);
+
++ writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_SET);
+ writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
+
++ /* Recovery on underflow */
++ writel(CTRL1_RECOVERY_ON_UNDERFLOW, host->base + LCDC_CTRL1 + REG_SET);
++
+ host->enabled = 1;
+ }
+
+@@ -377,6 +460,7 @@
+
+ dev_dbg(&host->pdev->dev, "%s\n", __func__);
+
++ clk_enable_axi(host);
+ /*
+ * Even if we disable the controller here, it will still continue
+ * until its FIFOs are running out of data
+@@ -391,10 +475,14 @@
+ loop--;
+ }
+
++ writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_CLR);
++
+ reg = readl(host->base + LCDC_VDCTRL4);
+ writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
+
+- clk_disable_unprepare(host->clk);
++ clk_disable_unprepare(host->clk_pix);
++
++ pm_runtime_put_sync_suspend(&host->pdev->dev);
+
+ host->enabled = 0;
+
+@@ -413,14 +501,9 @@
+ int line_size, fb_size;
+ int reenable = 0;
+
+- line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
+- fb_size = fb_info->var.yres_virtual * line_size;
+-
+- if (fb_size > fb_info->fix.smem_len)
+- return -ENOMEM;
+-
+- fb_info->fix.line_length = line_size;
++ clk_enable_axi(host);
+
++ dev_dbg(&host->pdev->dev, "%s\n", __func__);
+ /*
+ * It seems, you can't re-program the controller if it is still running.
+ * This may lead into shifted pictures (FIFO issue?).
+@@ -431,9 +514,24 @@
+ mxsfb_disable_controller(fb_info);
+ }
+
++ sema_init(&host->flip_sem, 1);
++
+ /* clear the FIFOs */
+ writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
+
++ line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
++ fb_info->fix.line_length = line_size;
++ fb_size = fb_info->var.yres_virtual * line_size;
++
++ /* Reallocate memory */
++ if (!fb_info->fix.smem_start || (fb_size > fb_info->fix.smem_len)) {
++ if (fb_info->fix.smem_start)
++ mxsfb_unmap_videomem(fb_info);
++
++ if (mxsfb_map_videomem(fb_info) < 0)
++ return -ENOMEM;
++ }
++
+ ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
+ CTRL_SET_BUS_WIDTH(host->ld_intf_width);
+
+@@ -485,9 +583,9 @@
+ vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
+ if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
+ vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
+- if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
++ if (!(fb_info->var.sync & FB_SYNC_OE_LOW_ACT))
+ vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
+- if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
++ if (fb_info->var.sync & FB_SYNC_CLK_LAT_FALL)
+ vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
+
+ writel(vdctrl0, host->base + LCDC_VDCTRL0);
+@@ -565,10 +663,58 @@
+ return ret;
+ }
+
++static int mxsfb_wait_for_vsync(struct fb_info *fb_info)
++{
++ struct mxsfb_info *host = to_imxfb_host(fb_info);
++ int ret = 0;
++
++ if (host->cur_blank != FB_BLANK_UNBLANK) {
++ dev_err(fb_info->device, "can't wait for VSYNC when fb "
++ "is blank\n");
++ return -EINVAL;
++ }
++
++ init_completion(&host->vsync_complete);
++
++ writel(CTRL1_VSYNC_EDGE_IRQ,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ host->wait4vsync = 1;
++ writel(CTRL1_VSYNC_EDGE_IRQ_EN,
++ host->base + LCDC_CTRL1 + REG_SET);
++ ret = wait_for_completion_interruptible_timeout(
++ &host->vsync_complete, 1 * HZ);
++ if (ret == 0) {
++ dev_err(fb_info->device,
++ "mxs wait for vsync timeout\n");
++ host->wait4vsync = 0;
++ ret = -ETIME;
++ } else if (ret > 0) {
++ ret = 0;
++ }
++ return ret;
++}
++
++static int mxsfb_ioctl(struct fb_info *fb_info, unsigned int cmd,
++ unsigned long arg)
++{
++ int ret = -EINVAL;
++
++ switch (cmd) {
++ case MXCFB_WAIT_FOR_VSYNC:
++ ret = mxsfb_wait_for_vsync(fb_info);
++ break;
++ default:
++ break;
++ }
++ return ret;
++}
++
+ static int mxsfb_blank(int blank, struct fb_info *fb_info)
+ {
+ struct mxsfb_info *host = to_imxfb_host(fb_info);
+
++ host->cur_blank = blank;
++
+ switch (blank) {
+ case FB_BLANK_POWERDOWN:
+ case FB_BLANK_VSYNC_SUSPEND:
+@@ -576,6 +722,8 @@
+ case FB_BLANK_NORMAL:
+ if (host->enabled)
+ mxsfb_disable_controller(fb_info);
++
++ clk_disable_axi(host);
+ break;
+
+ case FB_BLANK_UNBLANK:
+@@ -592,15 +740,68 @@
+ struct mxsfb_info *host = to_imxfb_host(fb_info);
+ unsigned offset;
+
+- if (var->xoffset != 0)
++ if (host->cur_blank != FB_BLANK_UNBLANK) {
++ dev_dbg(fb_info->device, "can't do pan display when fb "
++ "is blank\n");
++ return -EINVAL;
++ }
++
++ if (var->xoffset > 0) {
++ dev_dbg(fb_info->device, "x panning not supported\n");
+ return -EINVAL;
++ }
++
++ if ((var->yoffset + var->yres > var->yres_virtual)) {
++ dev_err(fb_info->device, "y panning exceeds\n");
++ return -EINVAL;
++ }
++
++ clk_enable_axi(host);
+
+ offset = fb_info->fix.line_length * var->yoffset;
+
++ if (down_timeout(&host->flip_sem, HZ / 2)) {
++ dev_err(fb_info->device, "timeout when waiting for flip irq\n");
++ return -ETIMEDOUT;
++ }
++
+ /* update on next VSYNC */
+ writel(fb_info->fix.smem_start + offset,
+ host->base + host->devdata->next_buf);
+
++ writel(CTRL1_CUR_FRAME_DONE_IRQ,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ writel(CTRL1_CUR_FRAME_DONE_IRQ_EN,
++ host->base + LCDC_CTRL1 + REG_SET);
++
++ return 0;
++}
++
++static int mxsfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
++{
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++
++ if (offset < info->fix.smem_len) {
++ /* mapping framebuffer memory */
++ len = info->fix.smem_len - offset;
++ vma->vm_pgoff = (info->fix.smem_start + offset) >> PAGE_SHIFT;
++ } else
++ return -EINVAL;
++
++ len = PAGE_ALIGN(len);
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ /* make buffers bufferable */
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++ dev_dbg(info->device, "mmap remap_pfn_range failed\n");
++ return -ENOBUFS;
++ }
++
+ return 0;
+ }
+
+@@ -609,8 +810,10 @@
+ .fb_check_var = mxsfb_check_var,
+ .fb_set_par = mxsfb_set_par,
+ .fb_setcolreg = mxsfb_setcolreg,
++ .fb_ioctl = mxsfb_ioctl,
+ .fb_blank = mxsfb_blank,
+ .fb_pan_display = mxsfb_pan_display,
++ .fb_mmap = mxsfb_mmap,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+@@ -626,6 +829,8 @@
+ u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
+ struct fb_videomode vmode;
+
++ clk_enable_axi(host);
++
+ /* Only restore the mode when the controller is running */
+ ctrl = readl(host->base + LCDC_CTRL);
+ if (!(ctrl & CTRL_RUN))
+@@ -654,7 +859,7 @@
+
+ fb_info->var.bits_per_pixel = bits_per_pixel;
+
+- vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
++ vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk_pix) / 1000U);
+ vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
+ vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
+ vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
+@@ -701,7 +906,7 @@
+ line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
+ fb_info->fix.ypanstep = 1;
+
+- clk_prepare_enable(host->clk);
++ clk_prepare_enable(host->clk_pix);
+ host->enabled = 1;
+
+ return 0;
+@@ -784,10 +989,10 @@
+ if (ret < 0)
+ goto put_timings_node;
+
+- if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
+- host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
++ if (!(vm.flags & DISPLAY_FLAGS_DE_HIGH))
++ fb_vm.sync |= FB_SYNC_OE_LOW_ACT;
+ if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+- host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
++ fb_vm.sync |= FB_SYNC_CLK_LAT_FALL;
+ fb_add_videomode(&fb_vm, &fb_info->modelist);
+ }
+
+@@ -802,9 +1007,7 @@
+ {
+ struct fb_info *fb_info = &host->fb_info;
+ struct fb_var_screeninfo *var = &fb_info->var;
+- dma_addr_t fb_phys;
+- void *fb_virt;
+- unsigned fb_size;
++ struct fb_modelist *modelist;
+ int ret;
+
+ fb_info->fbops = &mxsfb_ops;
+@@ -819,25 +1022,28 @@
+ if (ret)
+ return ret;
+
++ /* first video mode in the modelist as default video mode */
++ modelist = list_first_entry(&fb_info->modelist,
++ struct fb_modelist, list);
++ fb_videomode_to_var(var, &modelist->mode);
++
+ var->nonstd = 0;
+ var->activate = FB_ACTIVATE_NOW;
+ var->accel_flags = 0;
+ var->vmode = FB_VMODE_NONINTERLACED;
+
+- /* Memory allocation for framebuffer */
+- fb_size = SZ_2M;
+- fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
+- if (!fb_virt)
+- return -ENOMEM;
++ /* init the color fields */
++ mxsfb_check_var(var, fb_info);
+
+- fb_phys = virt_to_phys(fb_virt);
++ fb_info->fix.line_length =
++ fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
+
+- fb_info->fix.smem_start = fb_phys;
+- fb_info->screen_base = fb_virt;
+- fb_info->screen_size = fb_info->fix.smem_len = fb_size;
++ /* Memory allocation for framebuffer */
++ if (mxsfb_map_videomem(fb_info) < 0)
++ return -ENOMEM;
+
+ if (mxsfb_restore_mode(host))
+- memset(fb_virt, 0, fb_size);
++ memset((char *)fb_info->screen_base, 0, fb_info->fix.smem_len);
+
+ return 0;
+ }
+@@ -846,7 +1052,62 @@
+ {
+ struct fb_info *fb_info = &host->fb_info;
+
+- free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
++ mxsfb_unmap_videomem(fb_info);
++}
++
++/*!
++ * Allocates the DRAM memory for the frame buffer. This buffer is remapped
++ * into a non-cached, non-buffered, memory region to allow palette and pixel
++ * writes to occur without flushing the cache. Once this area is remapped,
++ * all virtual memory access to the video memory should occur at the new region.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxsfb_map_videomem(struct fb_info *fbi)
++{
++ if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
++ fbi->fix.smem_len = fbi->var.yres_virtual *
++ fbi->fix.line_length;
++
++ fbi->screen_base = dma_alloc_writecombine(fbi->device,
++ fbi->fix.smem_len,
++ (dma_addr_t *)&fbi->fix.smem_start,
++ GFP_DMA | GFP_KERNEL);
++ if (fbi->screen_base == 0) {
++ dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
++ fbi->fix.smem_len = 0;
++ fbi->fix.smem_start = 0;
++ return -EBUSY;
++ }
++
++ dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
++ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
++
++ fbi->screen_size = fbi->fix.smem_len;
++
++ /* Clear the screen */
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ return 0;
++}
++
++/*!
++ * De-allocates the DRAM memory for the frame buffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxsfb_unmap_videomem(struct fb_info *fbi)
++{
++ dma_free_writecombine(fbi->device, fbi->fix.smem_len,
++ fbi->screen_base, fbi->fix.smem_start);
++ fbi->screen_base = 0;
++ fbi->fix.smem_start = 0;
++ fbi->fix.smem_len = 0;
++ return 0;
+ }
+
+ static struct platform_device_id mxsfb_devtype[] = {
+@@ -876,8 +1137,8 @@
+ struct resource *res;
+ struct mxsfb_info *host;
+ struct fb_info *fb_info;
+- struct fb_modelist *modelist;
+ struct pinctrl *pinctrl;
++ int irq = platform_get_irq(pdev, 0);
+ int ret;
+
+ if (of_id)
+@@ -897,6 +1158,14 @@
+
+ host = to_imxfb_host(fb_info);
+
++ ret = devm_request_irq(&pdev->dev, irq, mxsfb_irq_handler, 0,
++ dev_name(&pdev->dev), host);
++ if (ret) {
++ dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
++ irq, ret);
++ return -ENODEV;
++ }
++
+ host->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(host->base)) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+@@ -915,9 +1184,15 @@
+ goto fb_release;
+ }
+
+- host->clk = devm_clk_get(&host->pdev->dev, NULL);
+- if (IS_ERR(host->clk)) {
+- ret = PTR_ERR(host->clk);
++ host->clk_pix = devm_clk_get(&host->pdev->dev, "pix");
++ if (IS_ERR(host->clk_pix)) {
++ ret = PTR_ERR(host->clk_pix);
++ goto fb_release;
++ }
++
++ host->clk_axi = devm_clk_get(&host->pdev->dev, "axi");
++ if (IS_ERR(host->clk_axi)) {
++ ret = PTR_ERR(host->clk_axi);
+ goto fb_release;
+ }
+
+@@ -934,39 +1209,36 @@
+
+ INIT_LIST_HEAD(&fb_info->modelist);
+
++ pm_runtime_enable(&host->pdev->dev);
++
+ ret = mxsfb_init_fbinfo(host);
+ if (ret != 0)
+- goto fb_release;
+-
+- modelist = list_first_entry(&fb_info->modelist,
+- struct fb_modelist, list);
+- fb_videomode_to_var(&fb_info->var, &modelist->mode);
+-
+- /* init the color fields */
+- mxsfb_check_var(&fb_info->var, fb_info);
++ goto fb_pm_runtime_disable;
+
+ platform_set_drvdata(pdev, fb_info);
+
+- ret = register_framebuffer(fb_info);
+- if (ret != 0) {
+- dev_err(&pdev->dev,"Failed to register framebuffer\n");
+- goto fb_destroy;
+- }
+-
+ if (!host->enabled) {
+ writel(0, host->base + LCDC_CTRL);
+ mxsfb_set_par(fb_info);
+ mxsfb_enable_controller(fb_info);
+ }
+
++ ret = register_framebuffer(fb_info);
++ if (ret != 0) {
++ dev_err(&pdev->dev, "Failed to register framebuffer\n");
++ goto fb_destroy;
++ }
++
+ dev_info(&pdev->dev, "initialized\n");
+
+ return 0;
+
+ fb_destroy:
+ if (host->enabled)
+- clk_disable_unprepare(host->clk);
++ clk_disable_unprepare(host->clk_pix);
+ fb_destroy_modelist(&fb_info->modelist);
++fb_pm_runtime_disable:
++ pm_runtime_disable(&host->pdev->dev);
+ fb_release:
+ framebuffer_release(fb_info);
+
+@@ -981,6 +1253,7 @@
+ if (host->enabled)
+ mxsfb_disable_controller(fb_info);
+
++ pm_runtime_disable(&host->pdev->dev);
+ unregister_framebuffer(fb_info);
+ mxsfb_free_videomem(host);
+
+@@ -996,13 +1269,75 @@
+ struct fb_info *fb_info = platform_get_drvdata(pdev);
+ struct mxsfb_info *host = to_imxfb_host(fb_info);
+
++ clk_enable_axi(host);
+ /*
+ * Force stop the LCD controller as keeping it running during reboot
+ * might interfere with the BootROM's boot mode pads sampling.
+ */
+ writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
++ writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_CLR);
++ clk_disable_axi(host);
+ }
+
++#ifdef CONFIG_PM_RUNTIME
++static int mxsfb_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "mxsfb busfreq high release.\n");
++
++ return 0;
++}
++
++static int mxsfb_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "mxsfb busfreq high request.\n");
++
++ return 0;
++}
++#else
++#define mxsfb_runtime_suspend NULL
++#define mxsfb_runtime_resume NULL
++#endif
++
++#ifdef CONFIG_PM
++static int mxsfb_suspend(struct device *pdev)
++{
++ struct fb_info *fb_info = dev_get_drvdata(pdev);
++ struct mxsfb_info *host = to_imxfb_host(fb_info);
++ int saved_blank;
++
++ console_lock();
++ fb_set_suspend(fb_info, 1);
++ saved_blank = host->cur_blank;
++ mxsfb_blank(FB_BLANK_POWERDOWN, fb_info);
++ host->restore_blank = saved_blank;
++ console_unlock();
++ return 0;
++}
++
++static int mxsfb_resume(struct device *pdev)
++{
++ struct fb_info *fb_info = dev_get_drvdata(pdev);
++ struct mxsfb_info *host = to_imxfb_host(fb_info);
++
++ console_lock();
++ mxsfb_blank(host->restore_blank, fb_info);
++ fb_set_suspend(fb_info, 0);
++ console_unlock();
++
++ return 0;
++}
++#else
++#define mxsfb_suspend NULL
++#define mxsfb_resume NULL
++#endif
++
++static const struct dev_pm_ops mxsfb_pm_ops = {
++ SET_RUNTIME_PM_OPS(mxsfb_runtime_suspend, mxsfb_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(mxsfb_suspend, mxsfb_resume)
++};
++
+ static struct platform_driver mxsfb_driver = {
+ .probe = mxsfb_probe,
+ .remove = mxsfb_remove,
+@@ -1011,6 +1346,7 @@
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = mxsfb_dt_ids,
++ .pm = &mxsfb_pm_ops,
+ },
+ };
+
+diff -Nur linux-3.10.30.orig/drivers/video/vexpress-dvi.c linux-linaro-stable-mx6/drivers/video/vexpress-dvi.c
+--- linux-3.10.30.orig/drivers/video/vexpress-dvi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/drivers/video/vexpress-dvi.c 2014-05-15 20:34:10.370103002 +0200
+@@ -0,0 +1,220 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Copyright (C) 2012 ARM Limited
++ */
++
++#define pr_fmt(fmt) "vexpress-dvi: " fmt
++
++#include <linux/fb.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/vexpress.h>
++
++
++static struct vexpress_config_func *vexpress_dvimode_func;
++
++static struct {
++ u32 xres, yres, mode;
++} vexpress_dvi_dvimodes[] = {
++ { 640, 480, 0 }, /* VGA */
++ { 800, 600, 1 }, /* SVGA */
++ { 1024, 768, 2 }, /* XGA */
++ { 1280, 1024, 3 }, /* SXGA */
++ { 1600, 1200, 4 }, /* UXGA */
++ { 1920, 1080, 5 }, /* HD1080 */
++};
++
++static void vexpress_dvi_mode_set(struct fb_info *info, u32 xres, u32 yres)
++{
++ int err = -ENOENT;
++ int i;
++
++ if (!vexpress_dvimode_func)
++ return;
++
++ for (i = 0; i < ARRAY_SIZE(vexpress_dvi_dvimodes); i++) {
++ if (vexpress_dvi_dvimodes[i].xres == xres &&
++ vexpress_dvi_dvimodes[i].yres == yres) {
++ pr_debug("mode: %ux%u = %d\n", xres, yres,
++ vexpress_dvi_dvimodes[i].mode);
++ err = vexpress_config_write(vexpress_dvimode_func, 0,
++ vexpress_dvi_dvimodes[i].mode);
++ break;
++ }
++ }
++
++ if (err)
++ pr_warn("Failed to set %ux%u mode! (%d)\n", xres, yres, err);
++}
++
++
++static struct vexpress_config_func *vexpress_muxfpga_func;
++static int vexpress_dvi_fb = -1;
++
++static int vexpress_dvi_mux_set(struct fb_info *info)
++{
++ int err;
++ u32 site = vexpress_get_site_by_dev(info->device);
++
++ if (!vexpress_muxfpga_func)
++ return -ENXIO;
++
++ err = vexpress_config_write(vexpress_muxfpga_func, 0, site);
++ if (!err) {
++ pr_debug("Selected MUXFPGA input %d (fb%d)\n", site,
++ info->node);
++ vexpress_dvi_fb = info->node;
++ vexpress_dvi_mode_set(info, info->var.xres,
++ info->var.yres);
++ } else {
++ pr_warn("Failed to select MUXFPGA input %d (fb%d)! (%d)\n",
++ site, info->node, err);
++ }
++
++ return err;
++}
++
++static int vexpress_dvi_fb_select(int fb)
++{
++ int err;
++ struct fb_info *info;
++
++ /* fb0 is the default */
++ if (fb < 0)
++ fb = 0;
++
++ info = registered_fb[fb];
++ if (!info || !lock_fb_info(info))
++ return -ENODEV;
++
++ err = vexpress_dvi_mux_set(info);
++
++ unlock_fb_info(info);
++
++ return err;
++}
++
++static ssize_t vexpress_dvi_fb_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "%d\n", vexpress_dvi_fb);
++}
++
++static ssize_t vexpress_dvi_fb_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ long value;
++ int err = kstrtol(buf, 0, &value);
++
++ if (!err)
++ err = vexpress_dvi_fb_select(value);
++
++ return err ? err : count;
++}
++
++DEVICE_ATTR(fb, S_IRUGO | S_IWUSR, vexpress_dvi_fb_show,
++ vexpress_dvi_fb_store);
++
++
++static int vexpress_dvi_fb_event_notify(struct notifier_block *self,
++ unsigned long action, void *data)
++{
++ struct fb_event *event = data;
++ struct fb_info *info = event->info;
++ struct fb_videomode *mode = event->data;
++
++ switch (action) {
++ case FB_EVENT_FB_REGISTERED:
++ if (vexpress_dvi_fb < 0)
++ vexpress_dvi_mux_set(info);
++ break;
++ case FB_EVENT_MODE_CHANGE:
++ case FB_EVENT_MODE_CHANGE_ALL:
++ if (info->node == vexpress_dvi_fb)
++ vexpress_dvi_mode_set(info, mode->xres, mode->yres);
++ break;
++ }
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block vexpress_dvi_fb_notifier = {
++ .notifier_call = vexpress_dvi_fb_event_notify,
++};
++static bool vexpress_dvi_fb_notifier_registered;
++
++
++enum vexpress_dvi_func { FUNC_MUXFPGA, FUNC_DVIMODE };
++
++static struct of_device_id vexpress_dvi_of_match[] = {
++ {
++ .compatible = "arm,vexpress-muxfpga",
++ .data = (void *)FUNC_MUXFPGA,
++ }, {
++ .compatible = "arm,vexpress-dvimode",
++ .data = (void *)FUNC_DVIMODE,
++ },
++ {}
++};
++
++static int vexpress_dvi_probe(struct platform_device *pdev)
++{
++ enum vexpress_dvi_func func;
++ const struct of_device_id *match =
++ of_match_device(vexpress_dvi_of_match, &pdev->dev);
++
++ if (match)
++ func = (enum vexpress_dvi_func)match->data;
++ else
++ func = pdev->id_entry->driver_data;
++
++ switch (func) {
++ case FUNC_MUXFPGA:
++ vexpress_muxfpga_func =
++ vexpress_config_func_get_by_dev(&pdev->dev);
++ device_create_file(&pdev->dev, &dev_attr_fb);
++ break;
++ case FUNC_DVIMODE:
++ vexpress_dvimode_func =
++ vexpress_config_func_get_by_dev(&pdev->dev);
++ break;
++ }
++
++ if (!vexpress_dvi_fb_notifier_registered) {
++ fb_register_client(&vexpress_dvi_fb_notifier);
++ vexpress_dvi_fb_notifier_registered = true;
++ }
++
++ vexpress_dvi_fb_select(vexpress_dvi_fb);
++
++ return 0;
++}
++
++static const struct platform_device_id vexpress_dvi_id_table[] = {
++ { .name = "vexpress-muxfpga", .driver_data = FUNC_MUXFPGA, },
++ { .name = "vexpress-dvimode", .driver_data = FUNC_DVIMODE, },
++ {}
++};
++
++static struct platform_driver vexpress_dvi_driver = {
++ .probe = vexpress_dvi_probe,
++ .driver = {
++ .name = "vexpress-dvi",
++ .of_match_table = vexpress_dvi_of_match,
++ },
++ .id_table = vexpress_dvi_id_table,
++};
++
++static int __init vexpress_dvi_init(void)
++{
++ return platform_driver_register(&vexpress_dvi_driver);
++}
++device_initcall(vexpress_dvi_init);
+diff -Nur linux-3.10.30.orig/firmware/imx/epdc_E060SCM.fw.ihex linux-linaro-stable-mx6/firmware/imx/epdc_E060SCM.fw.ihex
+--- linux-3.10.30.orig/firmware/imx/epdc_E060SCM.fw.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/firmware/imx/epdc_E060SCM.fw.ihex 2014-05-15 20:34:10.970107323 +0200
+@@ -0,0 +1,61613 @@
++:100000003488C47C012D0100DD0900000706A4002E
++:100010000358211D3CCA018502000000400000FE7B
++:100020004700000100040D00FFFC00000000005428
++:10003000000306090C0F1215181B1E21262B302851
++:1000400000000000000000083E050000000000E87D
++:10005000CB060000000000C88D0A0000000000A8C8
++:100060004F0E00000000009800000000000000A0FB
++:1000700065000000000000A8BC000000000000B007
++:100080000B010000000000B85A010000000000C091
++:10009000AA010000000000C831020000000000D0EA
++:1000A000AC020000000000D81B030000000000E0CC
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+--- linux-3.10.30.orig/firmware/imx/epdc_E60_V110.fw.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/firmware/imx/epdc_E60_V110.fw.ihex 2014-05-15 20:34:11.098108245 +0200
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+--- linux-3.10.30.orig/firmware/imx/epdc_E60_V220.fw.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/firmware/imx/epdc_E60_V220.fw.ihex 2014-05-15 20:34:11.306109744 +0200
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+--- linux-3.10.30.orig/firmware/imx/epdc_E97_V110.fw.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/firmware/imx/epdc_E97_V110.fw.ihex 2014-05-15 20:34:11.450110781 +0200
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+diff -Nur linux-3.10.30.orig/firmware/imx/sdma/sdma-imx6q.bin.ihex linux-linaro-stable-mx6/firmware/imx/sdma/sdma-imx6q.bin.ihex
+--- linux-3.10.30.orig/firmware/imx/sdma/sdma-imx6q.bin.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/firmware/imx/sdma/sdma-imx6q.bin.ihex 2014-05-15 20:34:11.450110781 +0200
+@@ -0,0 +1,116 @@
++:1000000053444D4101000000010000001C000000AD
++:1000100026000000B40000007A0600008202000002
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+diff -Nur linux-3.10.30.orig/firmware/Makefile linux-linaro-stable-mx6/firmware/Makefile
+--- linux-3.10.30.orig/firmware/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/firmware/Makefile 2014-05-15 20:34:10.566104413 +0200
+@@ -61,6 +61,7 @@
+ radeon/RV770_pfp.bin radeon/RV770_me.bin \
+ radeon/RV730_pfp.bin radeon/RV730_me.bin \
+ radeon/RV710_pfp.bin radeon/RV710_me.bin
++fw-shipped-$(CONFIG_IMX_SDMA) += imx/sdma/sdma-imx6q.bin
+ fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin
+ fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
+ fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
+@@ -135,6 +136,10 @@
+ fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
+ fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
+ fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
++fw-shipped-$(CONFIG_FB_MXC_EINK_PANEL) += imx/epdc_E60_V110.fw \
++ imx/epdc_E60_V220.fw \
++ imx/epdc_E97_V110.fw \
++ imx/epdc_E060SCM.fw
+
+ fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
+
+@@ -210,6 +215,8 @@
+ $(obj)/%: $(obj)/%.ihex | $(objtree)/$(obj)/$$(dir %)
+ $(call cmd,ihex)
+
++.NOTPARALLEL: $(obj)/%
++
+ # Don't depend on ihex2fw if we're installing and it already exists.
+ # Putting it after | in the dependencies doesn't seem sufficient when
+ # we're installing after a cross-compile, because ihex2fw has dependencies
+diff -Nur linux-3.10.30.orig/fs/debugfs/file.c linux-linaro-stable-mx6/fs/debugfs/file.c
+--- linux-3.10.30.orig/fs/debugfs/file.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/debugfs/file.c 2014-05-15 20:34:12.254116572 +0200
+@@ -21,6 +21,7 @@
+ #include <linux/debugfs.h>
+ #include <linux/io.h>
+ #include <linux/slab.h>
++#include <linux/atomic.h>
+
+ static ssize_t default_read_file(struct file *file, char __user *buf,
+ size_t count, loff_t *ppos)
+@@ -403,6 +404,47 @@
+ }
+ EXPORT_SYMBOL_GPL(debugfs_create_size_t);
+
++static int debugfs_atomic_t_set(void *data, u64 val)
++{
++ atomic_set((atomic_t *)data, val);
++ return 0;
++}
++static int debugfs_atomic_t_get(void *data, u64 *val)
++{
++ *val = atomic_read((atomic_t *)data);
++ return 0;
++}
++DEFINE_SIMPLE_ATTRIBUTE(fops_atomic_t, debugfs_atomic_t_get,
++ debugfs_atomic_t_set, "%llu\n");
++DEFINE_SIMPLE_ATTRIBUTE(fops_atomic_t_ro, debugfs_atomic_t_get, NULL, "%llu\n");
++DEFINE_SIMPLE_ATTRIBUTE(fops_atomic_t_wo, NULL, debugfs_atomic_t_set, "%llu\n");
++
++/**
++ * debugfs_create_atomic_t - create a debugfs file that is used to read and
++ * write an atomic_t value
++ * <at> name: a pointer to a string containing the name of the file to create.
++ * <at> mode: the permission that the file should have
++ * <at> parent: a pointer to the parent dentry for this file. This should be a
++ * directory dentry if set. If this parameter is %NULL, then the
++ * file will be created in the root of the debugfs filesystem.
++ * <at> value: a pointer to the variable that the file should read to and write
++ * from.
++ */
++struct dentry *debugfs_create_atomic_t(const char *name, umode_t mode,
++ struct dentry *parent, atomic_t *value)
++{
++ /* if there are no write bits set, make read only */
++ if (!(mode & S_IWUGO))
++ return debugfs_create_file(name, mode, parent, value,
++ &fops_atomic_t_ro);
++ /* if there are no read bits set, make write only */
++ if (!(mode & S_IRUGO))
++ return debugfs_create_file(name, mode, parent, value,
++ &fops_atomic_t_wo);
++
++ return debugfs_create_file(name, mode, parent, value, &fops_atomic_t);
++}
++EXPORT_SYMBOL_GPL(debugfs_create_atomic_t);
+
+ static ssize_t read_file_bool(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+diff -Nur linux-3.10.30.orig/fs/f2fs/acl.c linux-linaro-stable-mx6/fs/f2fs/acl.c
+--- linux-3.10.30.orig/fs/f2fs/acl.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/acl.c 2014-05-15 20:34:12.430117839 +0200
+@@ -205,7 +205,8 @@
+ return acl;
+ }
+
+-static int f2fs_set_acl(struct inode *inode, int type, struct posix_acl *acl)
++static int f2fs_set_acl(struct inode *inode, int type,
++ struct posix_acl *acl, struct page *ipage)
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+ struct f2fs_inode_info *fi = F2FS_I(inode);
+@@ -250,7 +251,7 @@
+ }
+ }
+
+- error = f2fs_setxattr(inode, name_index, "", value, size);
++ error = f2fs_setxattr(inode, name_index, "", value, size, ipage);
+
+ kfree(value);
+ if (!error)
+@@ -260,10 +261,10 @@
+ return error;
+ }
+
+-int f2fs_init_acl(struct inode *inode, struct inode *dir)
++int f2fs_init_acl(struct inode *inode, struct inode *dir, struct page *ipage)
+ {
+- struct posix_acl *acl = NULL;
+ struct f2fs_sb_info *sbi = F2FS_SB(dir->i_sb);
++ struct posix_acl *acl = NULL;
+ int error = 0;
+
+ if (!S_ISLNK(inode->i_mode)) {
+@@ -276,19 +277,19 @@
+ inode->i_mode &= ~current_umask();
+ }
+
+- if (test_opt(sbi, POSIX_ACL) && acl) {
++ if (!test_opt(sbi, POSIX_ACL) || !acl)
++ goto cleanup;
+
+- if (S_ISDIR(inode->i_mode)) {
+- error = f2fs_set_acl(inode, ACL_TYPE_DEFAULT, acl);
+- if (error)
+- goto cleanup;
+- }
+- error = posix_acl_create(&acl, GFP_KERNEL, &inode->i_mode);
+- if (error < 0)
+- return error;
+- if (error > 0)
+- error = f2fs_set_acl(inode, ACL_TYPE_ACCESS, acl);
++ if (S_ISDIR(inode->i_mode)) {
++ error = f2fs_set_acl(inode, ACL_TYPE_DEFAULT, acl, ipage);
++ if (error)
++ goto cleanup;
+ }
++ error = posix_acl_create(&acl, GFP_KERNEL, &inode->i_mode);
++ if (error < 0)
++ return error;
++ if (error > 0)
++ error = f2fs_set_acl(inode, ACL_TYPE_ACCESS, acl, ipage);
+ cleanup:
+ posix_acl_release(acl);
+ return error;
+@@ -313,7 +314,8 @@
+ error = posix_acl_chmod(&acl, GFP_KERNEL, mode);
+ if (error)
+ return error;
+- error = f2fs_set_acl(inode, ACL_TYPE_ACCESS, acl);
++
++ error = f2fs_set_acl(inode, ACL_TYPE_ACCESS, acl, NULL);
+ posix_acl_release(acl);
+ return error;
+ }
+@@ -388,7 +390,7 @@
+ acl = NULL;
+ }
+
+- error = f2fs_set_acl(inode, type, acl);
++ error = f2fs_set_acl(inode, type, acl, NULL);
+
+ release_and_out:
+ posix_acl_release(acl);
+diff -Nur linux-3.10.30.orig/fs/f2fs/acl.h linux-linaro-stable-mx6/fs/f2fs/acl.h
+--- linux-3.10.30.orig/fs/f2fs/acl.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/acl.h 2014-05-15 20:34:12.430117839 +0200
+@@ -36,9 +36,9 @@
+
+ #ifdef CONFIG_F2FS_FS_POSIX_ACL
+
+-extern struct posix_acl *f2fs_get_acl(struct inode *inode, int type);
+-extern int f2fs_acl_chmod(struct inode *inode);
+-extern int f2fs_init_acl(struct inode *inode, struct inode *dir);
++extern struct posix_acl *f2fs_get_acl(struct inode *, int);
++extern int f2fs_acl_chmod(struct inode *);
++extern int f2fs_init_acl(struct inode *, struct inode *, struct page *);
+ #else
+ #define f2fs_check_acl NULL
+ #define f2fs_get_acl NULL
+@@ -49,7 +49,8 @@
+ return 0;
+ }
+
+-static inline int f2fs_init_acl(struct inode *inode, struct inode *dir)
++static inline int f2fs_init_acl(struct inode *inode, struct inode *dir,
++ struct page *page)
+ {
+ return 0;
+ }
+diff -Nur linux-3.10.30.orig/fs/f2fs/checkpoint.c linux-linaro-stable-mx6/fs/f2fs/checkpoint.c
+--- linux-3.10.30.orig/fs/f2fs/checkpoint.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/checkpoint.c 2014-05-15 20:34:12.430117839 +0200
+@@ -81,7 +81,7 @@
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+
+ /* Should not write any meta pages, if any IO error was occurred */
+- if (wbc->for_reclaim ||
++ if (wbc->for_reclaim || sbi->por_doing ||
+ is_set_ckpt_flags(F2FS_CKPT(sbi), CP_ERROR_FLAG)) {
+ dec_page_count(sbi, F2FS_DIRTY_META);
+ wbc->pages_skipped++;
+@@ -142,8 +142,8 @@
+ for (i = 0; i < nr_pages; i++) {
+ struct page *page = pvec.pages[i];
+ lock_page(page);
+- BUG_ON(page->mapping != mapping);
+- BUG_ON(!PageDirty(page));
++ f2fs_bug_on(page->mapping != mapping);
++ f2fs_bug_on(!PageDirty(page));
+ clear_page_dirty_for_io(page);
+ if (f2fs_write_meta_page(page, &wbc)) {
+ unlock_page(page);
+@@ -167,6 +167,8 @@
+ struct address_space *mapping = page->mapping;
+ struct f2fs_sb_info *sbi = F2FS_SB(mapping->host->i_sb);
+
++ trace_f2fs_set_page_dirty(page, META);
++
+ SetPageUptodate(page);
+ if (!PageDirty(page)) {
+ __set_page_dirty_nobuffers(page);
+@@ -182,7 +184,7 @@
+ .set_page_dirty = f2fs_set_meta_page_dirty,
+ };
+
+-int check_orphan_space(struct f2fs_sb_info *sbi)
++int acquire_orphan_inode(struct f2fs_sb_info *sbi)
+ {
+ unsigned int max_orphans;
+ int err = 0;
+@@ -197,10 +199,20 @@
+ mutex_lock(&sbi->orphan_inode_mutex);
+ if (sbi->n_orphans >= max_orphans)
+ err = -ENOSPC;
++ else
++ sbi->n_orphans++;
+ mutex_unlock(&sbi->orphan_inode_mutex);
+ return err;
+ }
+
++void release_orphan_inode(struct f2fs_sb_info *sbi)
++{
++ mutex_lock(&sbi->orphan_inode_mutex);
++ f2fs_bug_on(sbi->n_orphans == 0);
++ sbi->n_orphans--;
++ mutex_unlock(&sbi->orphan_inode_mutex);
++}
++
+ void add_orphan_inode(struct f2fs_sb_info *sbi, nid_t ino)
+ {
+ struct list_head *head, *this;
+@@ -216,12 +228,8 @@
+ break;
+ orphan = NULL;
+ }
+-retry:
+- new = kmem_cache_alloc(orphan_entry_slab, GFP_ATOMIC);
+- if (!new) {
+- cond_resched();
+- goto retry;
+- }
++
++ new = f2fs_kmem_cache_alloc(orphan_entry_slab, GFP_ATOMIC);
+ new->ino = ino;
+
+ /* add new_oentry into list which is sorted by inode number */
+@@ -229,24 +237,22 @@
+ list_add(&new->list, this->prev);
+ else
+ list_add_tail(&new->list, head);
+-
+- sbi->n_orphans++;
+ out:
+ mutex_unlock(&sbi->orphan_inode_mutex);
+ }
+
+ void remove_orphan_inode(struct f2fs_sb_info *sbi, nid_t ino)
+ {
+- struct list_head *this, *next, *head;
++ struct list_head *head;
+ struct orphan_inode_entry *orphan;
+
+ mutex_lock(&sbi->orphan_inode_mutex);
+ head = &sbi->orphan_inode_list;
+- list_for_each_safe(this, next, head) {
+- orphan = list_entry(this, struct orphan_inode_entry, list);
++ list_for_each_entry(orphan, head, list) {
+ if (orphan->ino == ino) {
+ list_del(&orphan->list);
+ kmem_cache_free(orphan_entry_slab, orphan);
++ f2fs_bug_on(sbi->n_orphans == 0);
+ sbi->n_orphans--;
+ break;
+ }
+@@ -257,7 +263,7 @@
+ static void recover_orphan_inode(struct f2fs_sb_info *sbi, nid_t ino)
+ {
+ struct inode *inode = f2fs_iget(sbi->sb, ino);
+- BUG_ON(IS_ERR(inode));
++ f2fs_bug_on(IS_ERR(inode));
+ clear_nlink(inode);
+
+ /* truncate all the data during iput */
+@@ -271,7 +277,7 @@
+ if (!is_set_ckpt_flags(F2FS_CKPT(sbi), CP_ORPHAN_PRESENT_FLAG))
+ return 0;
+
+- sbi->por_doing = 1;
++ sbi->por_doing = true;
+ start_blk = __start_cp_addr(sbi) + 1;
+ orphan_blkaddr = __start_sum_addr(sbi) - 1;
+
+@@ -288,7 +294,7 @@
+ }
+ /* clear Orphan Flag */
+ clear_ckpt_flags(F2FS_CKPT(sbi), CP_ORPHAN_PRESENT_FLAG);
+- sbi->por_doing = 0;
++ sbi->por_doing = false;
+ return 0;
+ }
+
+@@ -357,8 +363,8 @@
+ unsigned long blk_size = sbi->blocksize;
+ struct f2fs_checkpoint *cp_block;
+ unsigned long long cur_version = 0, pre_version = 0;
+- unsigned int crc = 0;
+ size_t crc_offset;
++ __u32 crc = 0;
+
+ /* Read the 1st cp block in this CP pack */
+ cp_page_1 = get_meta_page(sbi, cp_addr);
+@@ -369,11 +375,11 @@
+ if (crc_offset >= blk_size)
+ goto invalid_cp1;
+
+- crc = *(unsigned int *)((unsigned char *)cp_block + crc_offset);
++ crc = le32_to_cpu(*((__u32 *)((unsigned char *)cp_block + crc_offset)));
+ if (!f2fs_crc_valid(crc, cp_block, crc_offset))
+ goto invalid_cp1;
+
+- pre_version = le64_to_cpu(cp_block->checkpoint_ver);
++ pre_version = cur_cp_version(cp_block);
+
+ /* Read the 2nd cp block in this CP pack */
+ cp_addr += le32_to_cpu(cp_block->cp_pack_total_block_count) - 1;
+@@ -384,11 +390,11 @@
+ if (crc_offset >= blk_size)
+ goto invalid_cp2;
+
+- crc = *(unsigned int *)((unsigned char *)cp_block + crc_offset);
++ crc = le32_to_cpu(*((__u32 *)((unsigned char *)cp_block + crc_offset)));
+ if (!f2fs_crc_valid(crc, cp_block, crc_offset))
+ goto invalid_cp2;
+
+- cur_version = le64_to_cpu(cp_block->checkpoint_ver);
++ cur_version = cur_cp_version(cp_block);
+
+ if (cur_version == pre_version) {
+ *version = cur_version;
+@@ -450,42 +456,57 @@
+ return -EINVAL;
+ }
+
+-void set_dirty_dir_page(struct inode *inode, struct page *page)
++static int __add_dirty_inode(struct inode *inode, struct dir_inode_entry *new)
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+ struct list_head *head = &sbi->dir_inode_list;
+- struct dir_inode_entry *new;
+ struct list_head *this;
+
++ list_for_each(this, head) {
++ struct dir_inode_entry *entry;
++ entry = list_entry(this, struct dir_inode_entry, list);
++ if (entry->inode == inode)
++ return -EEXIST;
++ }
++ list_add_tail(&new->list, head);
++ stat_inc_dirty_dir(sbi);
++ return 0;
++}
++
++void set_dirty_dir_page(struct inode *inode, struct page *page)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
++ struct dir_inode_entry *new;
++
+ if (!S_ISDIR(inode->i_mode))
+ return;
+-retry:
+- new = kmem_cache_alloc(inode_entry_slab, GFP_NOFS);
+- if (!new) {
+- cond_resched();
+- goto retry;
+- }
++
++ new = f2fs_kmem_cache_alloc(inode_entry_slab, GFP_NOFS);
+ new->inode = inode;
+ INIT_LIST_HEAD(&new->list);
+
+ spin_lock(&sbi->dir_inode_lock);
+- list_for_each(this, head) {
+- struct dir_inode_entry *entry;
+- entry = list_entry(this, struct dir_inode_entry, list);
+- if (entry->inode == inode) {
+- kmem_cache_free(inode_entry_slab, new);
+- goto out;
+- }
+- }
+- list_add_tail(&new->list, head);
+- sbi->n_dirty_dirs++;
++ if (__add_dirty_inode(inode, new))
++ kmem_cache_free(inode_entry_slab, new);
+
+- BUG_ON(!S_ISDIR(inode->i_mode));
+-out:
+ inc_page_count(sbi, F2FS_DIRTY_DENTS);
+ inode_inc_dirty_dents(inode);
+ SetPagePrivate(page);
++ spin_unlock(&sbi->dir_inode_lock);
++}
++
++void add_dirty_dir_inode(struct inode *inode)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
++ struct dir_inode_entry *new =
++ f2fs_kmem_cache_alloc(inode_entry_slab, GFP_NOFS);
+
++ new->inode = inode;
++ INIT_LIST_HEAD(&new->list);
++
++ spin_lock(&sbi->dir_inode_lock);
++ if (__add_dirty_inode(inode, new))
++ kmem_cache_free(inode_entry_slab, new);
+ spin_unlock(&sbi->dir_inode_lock);
+ }
+
+@@ -499,8 +520,10 @@
+ return;
+
+ spin_lock(&sbi->dir_inode_lock);
+- if (atomic_read(&F2FS_I(inode)->dirty_dents))
+- goto out;
++ if (atomic_read(&F2FS_I(inode)->dirty_dents)) {
++ spin_unlock(&sbi->dir_inode_lock);
++ return;
++ }
+
+ list_for_each(this, head) {
+ struct dir_inode_entry *entry;
+@@ -508,12 +531,36 @@
+ if (entry->inode == inode) {
+ list_del(&entry->list);
+ kmem_cache_free(inode_entry_slab, entry);
+- sbi->n_dirty_dirs--;
++ stat_dec_dirty_dir(sbi);
++ break;
++ }
++ }
++ spin_unlock(&sbi->dir_inode_lock);
++
++ /* Only from the recovery routine */
++ if (is_inode_flag_set(F2FS_I(inode), FI_DELAY_IPUT)) {
++ clear_inode_flag(F2FS_I(inode), FI_DELAY_IPUT);
++ iput(inode);
++ }
++}
++
++struct inode *check_dirty_dir_inode(struct f2fs_sb_info *sbi, nid_t ino)
++{
++ struct list_head *head = &sbi->dir_inode_list;
++ struct list_head *this;
++ struct inode *inode = NULL;
++
++ spin_lock(&sbi->dir_inode_lock);
++ list_for_each(this, head) {
++ struct dir_inode_entry *entry;
++ entry = list_entry(this, struct dir_inode_entry, list);
++ if (entry->inode->i_ino == ino) {
++ inode = entry->inode;
+ break;
+ }
+ }
+-out:
+ spin_unlock(&sbi->dir_inode_lock);
++ return inode;
+ }
+
+ void sync_dirty_dir_inodes(struct f2fs_sb_info *sbi)
+@@ -558,11 +605,10 @@
+ blk_start_plug(&plug);
+
+ retry_flush_dents:
+- mutex_lock_all(sbi);
+-
++ f2fs_lock_all(sbi);
+ /* write all the dirty dentry pages */
+ if (get_pages(sbi, F2FS_DIRTY_DENTS)) {
+- mutex_unlock_all(sbi);
++ f2fs_unlock_all(sbi);
+ sync_dirty_dir_inodes(sbi);
+ goto retry_flush_dents;
+ }
+@@ -585,7 +631,22 @@
+ static void unblock_operations(struct f2fs_sb_info *sbi)
+ {
+ mutex_unlock(&sbi->node_write);
+- mutex_unlock_all(sbi);
++ f2fs_unlock_all(sbi);
++}
++
++static void wait_on_all_pages_writeback(struct f2fs_sb_info *sbi)
++{
++ DEFINE_WAIT(wait);
++
++ for (;;) {
++ prepare_to_wait(&sbi->cp_wait, &wait, TASK_UNINTERRUPTIBLE);
++
++ if (!get_pages(sbi, F2FS_WRITEBACK))
++ break;
++
++ io_schedule();
++ }
++ finish_wait(&sbi->cp_wait, &wait);
+ }
+
+ static void do_checkpoint(struct f2fs_sb_info *sbi, bool is_umount)
+@@ -595,7 +656,7 @@
+ block_t start_blk;
+ struct page *cp_page;
+ unsigned int data_sum_blocks, orphan_blocks;
+- unsigned int crc32 = 0;
++ __u32 crc32 = 0;
+ void *kaddr;
+ int i;
+
+@@ -664,8 +725,8 @@
+ get_nat_bitmap(sbi, __bitmap_ptr(sbi, NAT_BITMAP));
+
+ crc32 = f2fs_crc32(ckpt, le32_to_cpu(ckpt->checksum_offset));
+- *(__le32 *)((unsigned char *)ckpt +
+- le32_to_cpu(ckpt->checksum_offset))
++ *((__le32 *)((unsigned char *)ckpt +
++ le32_to_cpu(ckpt->checksum_offset)))
+ = cpu_to_le32(crc32);
+
+ start_blk = __start_cp_addr(sbi);
+@@ -697,8 +758,7 @@
+ f2fs_put_page(cp_page, 1);
+
+ /* wait for previous submitted node/meta pages writeback */
+- while (get_pages(sbi, F2FS_WRITEBACK))
+- congestion_wait(BLK_RW_ASYNC, HZ / 50);
++ wait_on_all_pages_writeback(sbi);
+
+ filemap_fdatawait_range(sbi->node_inode->i_mapping, 0, LONG_MAX);
+ filemap_fdatawait_range(sbi->meta_inode->i_mapping, 0, LONG_MAX);
+@@ -740,7 +800,7 @@
+ * Increase the version number so that
+ * SIT entries and seg summaries are written at correct place
+ */
+- ckpt_ver = le64_to_cpu(ckpt->checkpoint_ver);
++ ckpt_ver = cur_cp_version(ckpt);
+ ckpt->checkpoint_ver = cpu_to_le64(++ckpt_ver);
+
+ /* write cached NAT/SIT entries to NAT/SIT area */
+diff -Nur linux-3.10.30.orig/fs/f2fs/data.c linux-linaro-stable-mx6/fs/f2fs/data.c
+--- linux-3.10.30.orig/fs/f2fs/data.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/data.c 2014-05-15 20:34:12.430117839 +0200
+@@ -37,9 +37,9 @@
+ struct page *node_page = dn->node_page;
+ unsigned int ofs_in_node = dn->ofs_in_node;
+
+- wait_on_page_writeback(node_page);
++ f2fs_wait_on_page_writeback(node_page, NODE, false);
+
+- rn = (struct f2fs_node *)page_address(node_page);
++ rn = F2FS_NODE(node_page);
+
+ /* Get physical address of data block */
+ addr_array = blkaddr_in_node(rn);
+@@ -68,7 +68,6 @@
+ struct buffer_head *bh_result)
+ {
+ struct f2fs_inode_info *fi = F2FS_I(inode);
+- struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+ pgoff_t start_fofs, end_fofs;
+ block_t start_blkaddr;
+
+@@ -78,7 +77,8 @@
+ return 0;
+ }
+
+- sbi->total_hit_ext++;
++ stat_inc_total_hit(inode->i_sb);
++
+ start_fofs = fi->ext.fofs;
+ end_fofs = fi->ext.fofs + fi->ext.len - 1;
+ start_blkaddr = fi->ext.blk_addr;
+@@ -96,7 +96,7 @@
+ else
+ bh_result->b_size = UINT_MAX;
+
+- sbi->read_hit_ext++;
++ stat_inc_read_hit(inode->i_sb);
+ read_unlock(&fi->ext.ext_lock);
+ return 1;
+ }
+@@ -110,8 +110,9 @@
+ pgoff_t fofs, start_fofs, end_fofs;
+ block_t start_blkaddr, end_blkaddr;
+
+- BUG_ON(blk_addr == NEW_ADDR);
+- fofs = start_bidx_of_node(ofs_of_node(dn->node_page)) + dn->ofs_in_node;
++ f2fs_bug_on(blk_addr == NEW_ADDR);
++ fofs = start_bidx_of_node(ofs_of_node(dn->node_page), fi) +
++ dn->ofs_in_node;
+
+ /* Update the page address in the parent node */
+ __set_data_blkaddr(dn, blk_addr);
+@@ -170,7 +171,6 @@
+ end_update:
+ write_unlock(&fi->ext.ext_lock);
+ sync_inode_page(dn);
+- return;
+ }
+
+ struct page *find_data_page(struct inode *inode, pgoff_t index, bool sync)
+@@ -199,7 +199,7 @@
+ if (dn.data_blkaddr == NEW_ADDR)
+ return ERR_PTR(-EINVAL);
+
+- page = grab_cache_page(mapping, index);
++ page = grab_cache_page_write_begin(mapping, index, AOP_FLAG_NOFS);
+ if (!page)
+ return ERR_PTR(-ENOMEM);
+
+@@ -233,24 +233,38 @@
+ struct page *page;
+ int err;
+
++repeat:
++ page = grab_cache_page_write_begin(mapping, index, AOP_FLAG_NOFS);
++ if (!page)
++ return ERR_PTR(-ENOMEM);
++
+ set_new_dnode(&dn, inode, NULL, NULL, 0);
+ err = get_dnode_of_data(&dn, index, LOOKUP_NODE);
+- if (err)
++ if (err) {
++ f2fs_put_page(page, 1);
+ return ERR_PTR(err);
++ }
+ f2fs_put_dnode(&dn);
+
+- if (dn.data_blkaddr == NULL_ADDR)
++ if (dn.data_blkaddr == NULL_ADDR) {
++ f2fs_put_page(page, 1);
+ return ERR_PTR(-ENOENT);
+-repeat:
+- page = grab_cache_page(mapping, index);
+- if (!page)
+- return ERR_PTR(-ENOMEM);
++ }
+
+ if (PageUptodate(page))
+ return page;
+
+- BUG_ON(dn.data_blkaddr == NEW_ADDR);
+- BUG_ON(dn.data_blkaddr == NULL_ADDR);
++ /*
++ * A new dentry page is allocated but not able to be written, since its
++ * new inode page couldn't be allocated due to -ENOSPC.
++ * In such the case, its blkaddr can be remained as NEW_ADDR.
++ * see, f2fs_add_link -> get_new_data_page -> init_inode_metadata.
++ */
++ if (dn.data_blkaddr == NEW_ADDR) {
++ zero_user_segment(page, 0, PAGE_CACHE_SIZE);
++ SetPageUptodate(page);
++ return page;
++ }
+
+ err = f2fs_readpage(sbi, page, dn.data_blkaddr, READ_SYNC);
+ if (err)
+@@ -274,9 +288,10 @@
+ *
+ * Also, caller should grab and release a mutex by calling mutex_lock_op() and
+ * mutex_unlock_op().
++ * Note that, npage is set only by make_empty_dir.
+ */
+-struct page *get_new_data_page(struct inode *inode, pgoff_t index,
+- bool new_i_size)
++struct page *get_new_data_page(struct inode *inode,
++ struct page *npage, pgoff_t index, bool new_i_size)
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+ struct address_space *mapping = inode->i_mapping;
+@@ -284,18 +299,20 @@
+ struct dnode_of_data dn;
+ int err;
+
+- set_new_dnode(&dn, inode, NULL, NULL, 0);
++ set_new_dnode(&dn, inode, npage, npage, 0);
+ err = get_dnode_of_data(&dn, index, ALLOC_NODE);
+ if (err)
+ return ERR_PTR(err);
+
+ if (dn.data_blkaddr == NULL_ADDR) {
+ if (reserve_new_block(&dn)) {
+- f2fs_put_dnode(&dn);
++ if (!npage)
++ f2fs_put_dnode(&dn);
+ return ERR_PTR(-ENOSPC);
+ }
+ }
+- f2fs_put_dnode(&dn);
++ if (!npage)
++ f2fs_put_dnode(&dn);
+ repeat:
+ page = grab_cache_page(mapping, index);
+ if (!page)
+@@ -325,6 +342,8 @@
+ if (new_i_size &&
+ i_size_read(inode) < ((index + 1) << PAGE_CACHE_SHIFT)) {
+ i_size_write(inode, ((index + 1) << PAGE_CACHE_SHIFT));
++ /* Only the directory inode sets new_i_size */
++ set_inode_flag(F2FS_I(inode), FI_UPDATE_DIR);
+ mark_inode_dirty_sync(inode);
+ }
+ return page;
+@@ -349,7 +368,6 @@
+ }
+ unlock_page(page);
+ } while (bvec >= bio->bi_io_vec);
+- kfree(bio->bi_private);
+ bio_put(bio);
+ }
+
+@@ -375,7 +393,6 @@
+ bio->bi_end_io = read_end_io;
+
+ if (bio_add_page(bio, page, PAGE_CACHE_SIZE, 0) < PAGE_CACHE_SIZE) {
+- kfree(bio->bi_private);
+ bio_put(bio);
+ up_read(&sbi->bio_sem);
+ f2fs_put_page(page, 1);
+@@ -419,14 +436,14 @@
+ }
+
+ /* It does not support data allocation */
+- BUG_ON(create);
++ f2fs_bug_on(create);
+
+ if (dn.data_blkaddr != NEW_ADDR && dn.data_blkaddr != NULL_ADDR) {
+ int i;
+ unsigned int end_offset;
+
+ end_offset = IS_INODE(dn.node_page) ?
+- ADDRS_PER_INODE :
++ ADDRS_PER_INODE(F2FS_I(inode)) :
+ ADDRS_PER_BLOCK;
+
+ clear_buffer_new(bh_result);
+@@ -481,8 +498,9 @@
+ * If current allocation needs SSR,
+ * it had better in-place writes for updated data.
+ */
+- if (old_blk_addr != NEW_ADDR && !is_cold_data(page) &&
+- need_inplace_update(inode)) {
++ if (unlikely(old_blk_addr != NEW_ADDR &&
++ !is_cold_data(page) &&
++ need_inplace_update(inode))) {
+ rewrite_data_page(F2FS_SB(inode->i_sb), page,
+ old_blk_addr);
+ } else {
+@@ -536,9 +554,9 @@
+ inode_dec_dirty_dents(inode);
+ err = do_write_data_page(page);
+ } else {
+- int ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ err = do_write_data_page(page);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ need_balance_fs = true;
+ }
+ if (err == -ENOENT)
+@@ -617,10 +635,6 @@
+ pgoff_t index = ((unsigned long long) pos) >> PAGE_CACHE_SHIFT;
+ struct dnode_of_data dn;
+ int err = 0;
+- int ilock;
+-
+- /* for nobh_write_end */
+- *fsdata = NULL;
+
+ f2fs_balance_fs(sbi);
+ repeat:
+@@ -629,7 +643,7 @@
+ return -ENOMEM;
+ *pagep = page;
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+
+ set_new_dnode(&dn, inode, NULL, NULL, 0);
+ err = get_dnode_of_data(&dn, index, ALLOC_NODE);
+@@ -643,7 +657,7 @@
+ if (err)
+ goto err;
+
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+
+ if ((len == PAGE_CACHE_SIZE) || PageUptodate(page))
+ return 0;
+@@ -679,11 +693,32 @@
+ return 0;
+
+ err:
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ f2fs_put_page(page, 1);
+ return err;
+ }
+
++static int f2fs_write_end(struct file *file,
++ struct address_space *mapping,
++ loff_t pos, unsigned len, unsigned copied,
++ struct page *page, void *fsdata)
++{
++ struct inode *inode = page->mapping->host;
++
++ SetPageUptodate(page);
++ set_page_dirty(page);
++
++ if (pos + copied > i_size_read(inode)) {
++ i_size_write(inode, pos + copied);
++ mark_inode_dirty(inode);
++ update_inode_page(inode);
++ }
++
++ unlock_page(page);
++ page_cache_release(page);
++ return copied;
++}
++
+ static ssize_t f2fs_direct_IO(int rw, struct kiocb *iocb,
+ const struct iovec *iov, loff_t offset, unsigned long nr_segs)
+ {
+@@ -698,7 +733,8 @@
+ get_data_block_ro);
+ }
+
+-static void f2fs_invalidate_data_page(struct page *page, unsigned long offset)
++static void f2fs_invalidate_data_page(struct page *page, unsigned int offset,
++ unsigned int length)
+ {
+ struct inode *inode = page->mapping->host;
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+@@ -720,6 +756,8 @@
+ struct address_space *mapping = page->mapping;
+ struct inode *inode = mapping->host;
+
++ trace_f2fs_set_page_dirty(page, DATA);
++
+ SetPageUptodate(page);
+ if (!PageDirty(page)) {
+ __set_page_dirty_nobuffers(page);
+@@ -740,7 +778,7 @@
+ .writepage = f2fs_write_data_page,
+ .writepages = f2fs_write_data_pages,
+ .write_begin = f2fs_write_begin,
+- .write_end = nobh_write_end,
++ .write_end = f2fs_write_end,
+ .set_page_dirty = f2fs_set_data_page_dirty,
+ .invalidatepage = f2fs_invalidate_data_page,
+ .releasepage = f2fs_release_data_page,
+diff -Nur linux-3.10.30.orig/fs/f2fs/debug.c linux-linaro-stable-mx6/fs/f2fs/debug.c
+--- linux-3.10.30.orig/fs/f2fs/debug.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/debug.c 2014-05-15 20:34:12.430117839 +0200
+@@ -29,7 +29,7 @@
+
+ static void update_general_status(struct f2fs_sb_info *sbi)
+ {
+- struct f2fs_stat_info *si = sbi->stat_info;
++ struct f2fs_stat_info *si = F2FS_STAT(sbi);
+ int i;
+
+ /* valid check of the segment numbers */
+@@ -83,7 +83,7 @@
+ */
+ static void update_sit_info(struct f2fs_sb_info *sbi)
+ {
+- struct f2fs_stat_info *si = sbi->stat_info;
++ struct f2fs_stat_info *si = F2FS_STAT(sbi);
+ unsigned int blks_per_sec, hblks_per_sec, total_vblocks, bimodal, dist;
+ struct sit_info *sit_i = SIT_I(sbi);
+ unsigned int segno, vblocks;
+@@ -118,7 +118,7 @@
+ */
+ static void update_mem_info(struct f2fs_sb_info *sbi)
+ {
+- struct f2fs_stat_info *si = sbi->stat_info;
++ struct f2fs_stat_info *si = F2FS_STAT(sbi);
+ unsigned npages;
+
+ if (si->base_mem)
+@@ -175,12 +175,12 @@
+
+ static int stat_show(struct seq_file *s, void *v)
+ {
+- struct f2fs_stat_info *si, *next;
++ struct f2fs_stat_info *si;
+ int i = 0;
+ int j;
+
+ mutex_lock(&f2fs_stat_mutex);
+- list_for_each_entry_safe(si, next, &f2fs_stat_list, stat_list) {
++ list_for_each_entry(si, &f2fs_stat_list, stat_list) {
+ char devname[BDEVNAME_SIZE];
+
+ update_general_status(si->sbi);
+@@ -253,21 +253,21 @@
+ si->nats, NM_WOUT_THRESHOLD);
+ seq_printf(s, " - SITs: %5d\n - free_nids: %5d\n",
+ si->sits, si->fnids);
+- seq_printf(s, "\nDistribution of User Blocks:");
+- seq_printf(s, " [ valid | invalid | free ]\n");
+- seq_printf(s, " [");
++ seq_puts(s, "\nDistribution of User Blocks:");
++ seq_puts(s, " [ valid | invalid | free ]\n");
++ seq_puts(s, " [");
+
+ for (j = 0; j < si->util_valid; j++)
+- seq_printf(s, "-");
+- seq_printf(s, "|");
++ seq_putc(s, '-');
++ seq_putc(s, '|');
+
+ for (j = 0; j < si->util_invalid; j++)
+- seq_printf(s, "-");
+- seq_printf(s, "|");
++ seq_putc(s, '-');
++ seq_putc(s, '|');
+
+ for (j = 0; j < si->util_free; j++)
+- seq_printf(s, "-");
+- seq_printf(s, "]\n\n");
++ seq_putc(s, '-');
++ seq_puts(s, "]\n\n");
+ seq_printf(s, "SSR: %u blocks in %u segments\n",
+ si->block_count[SSR], si->segment_count[SSR]);
+ seq_printf(s, "LFS: %u blocks in %u segments\n",
+@@ -305,11 +305,10 @@
+ struct f2fs_super_block *raw_super = F2FS_RAW_SUPER(sbi);
+ struct f2fs_stat_info *si;
+
+- sbi->stat_info = kzalloc(sizeof(struct f2fs_stat_info), GFP_KERNEL);
+- if (!sbi->stat_info)
++ si = kzalloc(sizeof(struct f2fs_stat_info), GFP_KERNEL);
++ if (!si)
+ return -ENOMEM;
+
+- si = sbi->stat_info;
+ si->all_area_segs = le32_to_cpu(raw_super->segment_count);
+ si->sit_area_segs = le32_to_cpu(raw_super->segment_count_sit);
+ si->nat_area_segs = le32_to_cpu(raw_super->segment_count_nat);
+@@ -319,6 +318,7 @@
+ si->main_area_zones = si->main_area_sections /
+ le32_to_cpu(raw_super->secs_per_zone);
+ si->sbi = sbi;
++ sbi->stat_info = si;
+
+ mutex_lock(&f2fs_stat_mutex);
+ list_add_tail(&si->stat_list, &f2fs_stat_list);
+@@ -329,13 +329,13 @@
+
+ void f2fs_destroy_stats(struct f2fs_sb_info *sbi)
+ {
+- struct f2fs_stat_info *si = sbi->stat_info;
++ struct f2fs_stat_info *si = F2FS_STAT(sbi);
+
+ mutex_lock(&f2fs_stat_mutex);
+ list_del(&si->stat_list);
+ mutex_unlock(&f2fs_stat_mutex);
+
+- kfree(sbi->stat_info);
++ kfree(si);
+ }
+
+ void __init f2fs_create_root_stats(void)
+diff -Nur linux-3.10.30.orig/fs/f2fs/dir.c linux-linaro-stable-mx6/fs/f2fs/dir.c
+--- linux-3.10.30.orig/fs/f2fs/dir.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/dir.c 2014-05-15 20:34:12.430117839 +0200
+@@ -13,6 +13,7 @@
+ #include "f2fs.h"
+ #include "node.h"
+ #include "acl.h"
++#include "xattr.h"
+
+ static unsigned long dir_blocks(struct inode *inode)
+ {
+@@ -138,7 +139,7 @@
+ bool room = false;
+ int max_slots = 0;
+
+- BUG_ON(level > MAX_DIR_HASH_DEPTH);
++ f2fs_bug_on(level > MAX_DIR_HASH_DEPTH);
+
+ nbucket = dir_buckets(level);
+ nblock = bucket_blocks(level);
+@@ -215,9 +216,9 @@
+
+ struct f2fs_dir_entry *f2fs_parent_dir(struct inode *dir, struct page **p)
+ {
+- struct page *page = NULL;
+- struct f2fs_dir_entry *de = NULL;
+- struct f2fs_dentry_block *dentry_blk = NULL;
++ struct page *page;
++ struct f2fs_dir_entry *de;
++ struct f2fs_dentry_block *dentry_blk;
+
+ page = get_lock_data_page(dir, 0);
+ if (IS_ERR(page))
+@@ -264,30 +265,41 @@
+ f2fs_put_page(page, 1);
+ }
+
+-void init_dent_inode(const struct qstr *name, struct page *ipage)
++static void init_dent_inode(const struct qstr *name, struct page *ipage)
+ {
+ struct f2fs_node *rn;
+
+- if (IS_ERR(ipage))
+- return;
+-
+- wait_on_page_writeback(ipage);
+-
+ /* copy name info. to this inode page */
+- rn = (struct f2fs_node *)page_address(ipage);
++ rn = F2FS_NODE(ipage);
+ rn->i.i_namelen = cpu_to_le32(name->len);
+ memcpy(rn->i.i_name, name->name, name->len);
+ set_page_dirty(ipage);
+ }
+
+-static int make_empty_dir(struct inode *inode, struct inode *parent)
++int update_dent_inode(struct inode *inode, const struct qstr *name)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
++ struct page *page;
++
++ page = get_node_page(sbi, inode->i_ino);
++ if (IS_ERR(page))
++ return PTR_ERR(page);
++
++ init_dent_inode(name, page);
++ f2fs_put_page(page, 1);
++
++ return 0;
++}
++
++static int make_empty_dir(struct inode *inode,
++ struct inode *parent, struct page *page)
+ {
+ struct page *dentry_page;
+ struct f2fs_dentry_block *dentry_blk;
+ struct f2fs_dir_entry *de;
+ void *kaddr;
+
+- dentry_page = get_new_data_page(inode, 0, true);
++ dentry_page = get_new_data_page(inode, page, 0, true);
+ if (IS_ERR(dentry_page))
+ return PTR_ERR(dentry_page);
+
+@@ -317,63 +329,76 @@
+ return 0;
+ }
+
+-static int init_inode_metadata(struct inode *inode,
++static struct page *init_inode_metadata(struct inode *inode,
+ struct inode *dir, const struct qstr *name)
+ {
++ struct page *page;
++ int err;
++
+ if (is_inode_flag_set(F2FS_I(inode), FI_NEW_INODE)) {
+- int err;
+- err = new_inode_page(inode, name);
+- if (err)
+- return err;
++ page = new_inode_page(inode, name);
++ if (IS_ERR(page))
++ return page;
+
+ if (S_ISDIR(inode->i_mode)) {
+- err = make_empty_dir(inode, dir);
+- if (err) {
+- remove_inode_page(inode);
+- return err;
+- }
++ err = make_empty_dir(inode, dir, page);
++ if (err)
++ goto error;
+ }
+
+- err = f2fs_init_acl(inode, dir);
+- if (err) {
+- remove_inode_page(inode);
+- return err;
+- }
++ err = f2fs_init_acl(inode, dir, page);
++ if (err)
++ goto error;
++
++ err = f2fs_init_security(inode, dir, name, page);
++ if (err)
++ goto error;
++
++ wait_on_page_writeback(page);
+ } else {
+- struct page *ipage;
+- ipage = get_node_page(F2FS_SB(dir->i_sb), inode->i_ino);
+- if (IS_ERR(ipage))
+- return PTR_ERR(ipage);
+- set_cold_node(inode, ipage);
+- init_dent_inode(name, ipage);
+- f2fs_put_page(ipage, 1);
++ page = get_node_page(F2FS_SB(dir->i_sb), inode->i_ino);
++ if (IS_ERR(page))
++ return page;
++
++ wait_on_page_writeback(page);
++ set_cold_node(inode, page);
+ }
++
++ init_dent_inode(name, page);
++
++ /*
++ * This file should be checkpointed during fsync.
++ * We lost i_pino from now on.
++ */
+ if (is_inode_flag_set(F2FS_I(inode), FI_INC_LINK)) {
++ file_lost_pino(inode);
+ inc_nlink(inode);
+- update_inode_page(inode);
+ }
+- return 0;
++ return page;
++
++error:
++ f2fs_put_page(page, 1);
++ remove_inode_page(inode);
++ return ERR_PTR(err);
+ }
+
+ static void update_parent_metadata(struct inode *dir, struct inode *inode,
+ unsigned int current_depth)
+ {
+- bool need_dir_update = false;
+-
+ if (is_inode_flag_set(F2FS_I(inode), FI_NEW_INODE)) {
+ if (S_ISDIR(inode->i_mode)) {
+ inc_nlink(dir);
+- need_dir_update = true;
++ set_inode_flag(F2FS_I(dir), FI_UPDATE_DIR);
+ }
+ clear_inode_flag(F2FS_I(inode), FI_NEW_INODE);
+ }
+ dir->i_mtime = dir->i_ctime = CURRENT_TIME;
+ if (F2FS_I(dir)->i_current_depth != current_depth) {
+ F2FS_I(dir)->i_current_depth = current_depth;
+- need_dir_update = true;
++ set_inode_flag(F2FS_I(dir), FI_UPDATE_DIR);
+ }
+
+- if (need_dir_update)
++ if (is_inode_flag_set(F2FS_I(dir), FI_UPDATE_DIR))
+ update_inode_page(dir);
+ else
+ mark_inode_dirty(dir);
+@@ -423,6 +448,7 @@
+ struct page *dentry_page = NULL;
+ struct f2fs_dentry_block *dentry_blk = NULL;
+ int slots = GET_DENTRY_SLOTS(namelen);
++ struct page *page;
+ int err = 0;
+ int i;
+
+@@ -448,7 +474,7 @@
+ bidx = dir_block_index(level, (le32_to_cpu(dentry_hash) % nbucket));
+
+ for (block = bidx; block <= (bidx + nblock - 1); block++) {
+- dentry_page = get_new_data_page(dir, block, true);
++ dentry_page = get_new_data_page(dir, NULL, block, true);
+ if (IS_ERR(dentry_page))
+ return PTR_ERR(dentry_page);
+
+@@ -465,12 +491,13 @@
+ ++level;
+ goto start;
+ add_dentry:
+- err = init_inode_metadata(inode, dir, name);
+- if (err)
+- goto fail;
+-
+ wait_on_page_writeback(dentry_page);
+
++ page = init_inode_metadata(inode, dir, name);
++ if (IS_ERR(page)) {
++ err = PTR_ERR(page);
++ goto fail;
++ }
+ de = &dentry_blk->dentry[bit_pos];
+ de->hash_code = dentry_hash;
+ de->name_len = cpu_to_le16(namelen);
+@@ -481,11 +508,14 @@
+ test_and_set_bit_le(bit_pos + i, &dentry_blk->dentry_bitmap);
+ set_page_dirty(dentry_page);
+
+- update_parent_metadata(dir, inode, current_depth);
+-
+- /* update parent inode number before releasing dentry page */
++ /* we don't need to mark_inode_dirty now */
+ F2FS_I(inode)->i_pino = dir->i_ino;
++ update_inode(inode, page);
++ f2fs_put_page(page, 1);
++
++ update_parent_metadata(dir, inode, current_depth);
+ fail:
++ clear_inode_flag(F2FS_I(dir), FI_UPDATE_DIR);
+ kunmap(dentry_page);
+ f2fs_put_page(dentry_page, 1);
+ return err;
+@@ -542,6 +572,8 @@
+
+ if (inode->i_nlink == 0)
+ add_orphan_inode(sbi, inode->i_ino);
++ else
++ release_orphan_inode(sbi);
+ }
+
+ if (bit_pos == NR_DENTRY_IN_BLOCK) {
+diff -Nur linux-3.10.30.orig/fs/f2fs/f2fs.h linux-linaro-stable-mx6/fs/f2fs/f2fs.h
+--- linux-3.10.30.orig/fs/f2fs/f2fs.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/f2fs.h 2014-05-15 20:34:12.458118041 +0200
+@@ -17,6 +17,14 @@
+ #include <linux/slab.h>
+ #include <linux/crc32.h>
+ #include <linux/magic.h>
++#include <linux/kobject.h>
++#include <linux/sched.h>
++
++#ifdef CONFIG_F2FS_CHECK_FS
++#define f2fs_bug_on(condition) BUG_ON(condition)
++#else
++#define f2fs_bug_on(condition)
++#endif
+
+ /*
+ * For mount options
+@@ -28,6 +36,7 @@
+ #define F2FS_MOUNT_XATTR_USER 0x00000010
+ #define F2FS_MOUNT_POSIX_ACL 0x00000020
+ #define F2FS_MOUNT_DISABLE_EXT_IDENTIFY 0x00000040
++#define F2FS_MOUNT_INLINE_XATTR 0x00000080
+
+ #define clear_opt(sbi, option) (sbi->mount_opt.opt &= ~F2FS_MOUNT_##option)
+ #define set_opt(sbi, option) (sbi->mount_opt.opt |= F2FS_MOUNT_##option)
+@@ -37,21 +46,35 @@
+ typecheck(unsigned long long, b) && \
+ ((long long)((a) - (b)) > 0))
+
+-typedef u64 block_t;
++typedef u32 block_t; /*
++ * should not change u32, since it is the on-disk block
++ * address format, __le32.
++ */
+ typedef u32 nid_t;
+
+ struct f2fs_mount_info {
+ unsigned int opt;
+ };
+
+-static inline __u32 f2fs_crc32(void *buff, size_t len)
++#define CRCPOLY_LE 0xedb88320
++
++static inline __u32 f2fs_crc32(void *buf, size_t len)
+ {
+- return crc32_le(F2FS_SUPER_MAGIC, buff, len);
++ unsigned char *p = (unsigned char *)buf;
++ __u32 crc = F2FS_SUPER_MAGIC;
++ int i;
++
++ while (len--) {
++ crc ^= *p++;
++ for (i = 0; i < 8; i++)
++ crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
++ }
++ return crc;
+ }
+
+-static inline bool f2fs_crc_valid(__u32 blk_crc, void *buff, size_t buff_size)
++static inline bool f2fs_crc_valid(__u32 blk_crc, void *buf, size_t buf_size)
+ {
+- return f2fs_crc32(buff, buff_size) == blk_crc;
++ return f2fs_crc32(buf, buf_size) == blk_crc;
+ }
+
+ /*
+@@ -120,11 +143,13 @@
+ /*
+ * For INODE and NODE manager
+ */
+-#define XATTR_NODE_OFFSET (-1) /*
+- * store xattrs to one node block per
+- * file keeping -1 as its node offset to
+- * distinguish from index node blocks.
+- */
++/*
++ * XATTR_NODE_OFFSET stores xattrs to one node block per file keeping -1
++ * as its node offset to distinguish from index node blocks.
++ * But some bits are used to mark the node block.
++ */
++#define XATTR_NODE_OFFSET ((((unsigned int)-1) << OFFSET_BIT_SHIFT) \
++ >> OFFSET_BIT_SHIFT)
+ enum {
+ ALLOC_NODE, /* allocate a new node page if needed */
+ LOOKUP_NODE, /* look up a node without readahead */
+@@ -148,7 +173,7 @@
+ * i_advise uses FADVISE_XXX_BIT. We can add additional hints later.
+ */
+ #define FADVISE_COLD_BIT 0x01
+-#define FADVISE_CP_BIT 0x02
++#define FADVISE_LOST_PINO_BIT 0x02
+
+ struct f2fs_inode_info {
+ struct inode vfs_inode; /* serve a vfs inode */
+@@ -164,6 +189,7 @@
+ f2fs_hash_t chash; /* hash value of given file name */
+ unsigned int clevel; /* maximum level of given file name */
+ nid_t i_xattr_nid; /* node id that contains xattrs */
++ unsigned long long xattr_ver; /* cp version of xattr modification */
+ struct extent_info ext; /* in-memory extent cache entry */
+ };
+
+@@ -279,16 +305,10 @@
+ unsigned int main_segments; /* # of segments in main area */
+ unsigned int reserved_segments; /* # of reserved segments */
+ unsigned int ovp_segments; /* # of overprovision segments */
+-};
+
+-/*
+- * For directory operation
+- */
+-#define NODE_DIR1_BLOCK (ADDRS_PER_INODE + 1)
+-#define NODE_DIR2_BLOCK (ADDRS_PER_INODE + 2)
+-#define NODE_IND1_BLOCK (ADDRS_PER_INODE + 3)
+-#define NODE_IND2_BLOCK (ADDRS_PER_INODE + 4)
+-#define NODE_DIND_BLOCK (ADDRS_PER_INODE + 5)
++ /* a threshold to reclaim prefree segments */
++ unsigned int rec_prefree_segments;
++};
+
+ /*
+ * For superblock
+@@ -308,14 +328,6 @@
+ };
+
+ /*
+- * Uses as sbi->fs_lock[NR_GLOBAL_LOCKS].
+- * The checkpoint procedure blocks all the locks in this fs_lock array.
+- * Some FS operations grab free locks, and if there is no free lock,
+- * then wait to grab a lock in a round-robin manner.
+- */
+-#define NR_GLOBAL_LOCKS 8
+-
+-/*
+ * The below are the page types of bios used in submti_bio().
+ * The available types are:
+ * DATA User data pages. It operates as async mode.
+@@ -336,6 +348,7 @@
+
+ struct f2fs_sb_info {
+ struct super_block *sb; /* pointer to VFS super block */
++ struct proc_dir_entry *s_proc; /* proc entry */
+ struct buffer_head *raw_super_buf; /* buffer head of raw sb */
+ struct f2fs_super_block *raw_super; /* raw super block pointer */
+ int s_dirty; /* dirty flag for checkpoint */
+@@ -354,12 +367,12 @@
+ struct f2fs_checkpoint *ckpt; /* raw checkpoint pointer */
+ struct inode *meta_inode; /* cache meta blocks */
+ struct mutex cp_mutex; /* checkpoint procedure lock */
+- struct mutex fs_lock[NR_GLOBAL_LOCKS]; /* blocking FS operations */
++ struct rw_semaphore cp_rwsem; /* blocking FS operations */
+ struct mutex node_write; /* locking node writes */
+ struct mutex writepages; /* mutex for writepages() */
+- unsigned char next_lock_num; /* round-robin global locks */
+- int por_doing; /* recovery is doing or not */
+- int on_build_free_nids; /* build_free_nids is doing */
++ bool por_doing; /* recovery is doing or not */
++ bool on_build_free_nids; /* build_free_nids is doing */
++ wait_queue_head_t cp_wait;
+
+ /* for orphan inode management */
+ struct list_head orphan_inode_list; /* orphan inode list */
+@@ -369,7 +382,6 @@
+ /* for directory inode management */
+ struct list_head dir_inode_list; /* dir inode list */
+ spinlock_t dir_inode_lock; /* for dir inode list lock */
+- unsigned int n_dirty_dirs; /* # of dir inodes */
+
+ /* basic file system units */
+ unsigned int log_sectors_per_block; /* log2 sectors per block */
+@@ -406,13 +418,20 @@
+ * for stat information.
+ * one is for the LFS mode, and the other is for the SSR mode.
+ */
++#ifdef CONFIG_F2FS_STAT_FS
+ struct f2fs_stat_info *stat_info; /* FS status information */
+ unsigned int segment_count[2]; /* # of allocated segments */
+ unsigned int block_count[2]; /* # of allocated blocks */
+- unsigned int last_victim[2]; /* last victim segment # */
+ int total_hit_ext, read_hit_ext; /* extent cache hit ratio */
+ int bg_gc; /* background gc calls */
++ unsigned int n_dirty_dirs; /* # of dir inodes */
++#endif
++ unsigned int last_victim[2]; /* last victim segment # */
+ spinlock_t stat_lock; /* lock for stat operations */
++
++ /* For sysfs suppport */
++ struct kobject s_kobj;
++ struct completion s_kobj_unregister;
+ };
+
+ /*
+@@ -438,6 +457,11 @@
+ return (struct f2fs_checkpoint *)(sbi->ckpt);
+ }
+
++static inline struct f2fs_node *F2FS_NODE(struct page *page)
++{
++ return (struct f2fs_node *)page_address(page);
++}
++
+ static inline struct f2fs_nm_info *NM_I(struct f2fs_sb_info *sbi)
+ {
+ return (struct f2fs_nm_info *)(sbi->nm_info);
+@@ -473,6 +497,11 @@
+ sbi->s_dirty = 0;
+ }
+
++static inline unsigned long long cur_cp_version(struct f2fs_checkpoint *cp)
++{
++ return le64_to_cpu(cp->checkpoint_ver);
++}
++
+ static inline bool is_set_ckpt_flags(struct f2fs_checkpoint *cp, unsigned int f)
+ {
+ unsigned int ckpt_flags = le32_to_cpu(cp->ckpt_flags);
+@@ -493,40 +522,24 @@
+ cp->ckpt_flags = cpu_to_le32(ckpt_flags);
+ }
+
+-static inline void mutex_lock_all(struct f2fs_sb_info *sbi)
++static inline void f2fs_lock_op(struct f2fs_sb_info *sbi)
+ {
+- int i = 0;
+- for (; i < NR_GLOBAL_LOCKS; i++)
+- mutex_lock(&sbi->fs_lock[i]);
++ down_read(&sbi->cp_rwsem);
+ }
+
+-static inline void mutex_unlock_all(struct f2fs_sb_info *sbi)
++static inline void f2fs_unlock_op(struct f2fs_sb_info *sbi)
+ {
+- int i = 0;
+- for (; i < NR_GLOBAL_LOCKS; i++)
+- mutex_unlock(&sbi->fs_lock[i]);
++ up_read(&sbi->cp_rwsem);
+ }
+
+-static inline int mutex_lock_op(struct f2fs_sb_info *sbi)
++static inline void f2fs_lock_all(struct f2fs_sb_info *sbi)
+ {
+- unsigned char next_lock = sbi->next_lock_num % NR_GLOBAL_LOCKS;
+- int i = 0;
+-
+- for (; i < NR_GLOBAL_LOCKS; i++)
+- if (mutex_trylock(&sbi->fs_lock[i]))
+- return i;
+-
+- mutex_lock(&sbi->fs_lock[next_lock]);
+- sbi->next_lock_num++;
+- return next_lock;
++ down_write_nest_lock(&sbi->cp_rwsem, &sbi->cp_mutex);
+ }
+
+-static inline void mutex_unlock_op(struct f2fs_sb_info *sbi, int ilock)
++static inline void f2fs_unlock_all(struct f2fs_sb_info *sbi)
+ {
+- if (ilock < 0)
+- return;
+- BUG_ON(ilock >= NR_GLOBAL_LOCKS);
+- mutex_unlock(&sbi->fs_lock[ilock]);
++ up_write(&sbi->cp_rwsem);
+ }
+
+ /*
+@@ -577,8 +590,8 @@
+ blkcnt_t count)
+ {
+ spin_lock(&sbi->stat_lock);
+- BUG_ON(sbi->total_valid_block_count < (block_t) count);
+- BUG_ON(inode->i_blocks < count);
++ f2fs_bug_on(sbi->total_valid_block_count < (block_t) count);
++ f2fs_bug_on(inode->i_blocks < count);
+ inode->i_blocks -= count;
+ sbi->total_valid_block_count -= (block_t)count;
+ spin_unlock(&sbi->stat_lock);
+@@ -653,7 +666,7 @@
+ {
+ block_t start_addr;
+ struct f2fs_checkpoint *ckpt = F2FS_CKPT(sbi);
+- unsigned long long ckpt_version = le64_to_cpu(ckpt->checkpoint_ver);
++ unsigned long long ckpt_version = cur_cp_version(ckpt);
+
+ start_addr = le32_to_cpu(F2FS_RAW_SUPER(sbi)->cp_blkaddr);
+
+@@ -710,9 +723,9 @@
+ {
+ spin_lock(&sbi->stat_lock);
+
+- BUG_ON(sbi->total_valid_block_count < count);
+- BUG_ON(sbi->total_valid_node_count < count);
+- BUG_ON(inode->i_blocks < count);
++ f2fs_bug_on(sbi->total_valid_block_count < count);
++ f2fs_bug_on(sbi->total_valid_node_count < count);
++ f2fs_bug_on(inode->i_blocks < count);
+
+ inode->i_blocks -= count;
+ sbi->total_valid_node_count -= count;
+@@ -733,7 +746,7 @@
+ static inline void inc_valid_inode_count(struct f2fs_sb_info *sbi)
+ {
+ spin_lock(&sbi->stat_lock);
+- BUG_ON(sbi->total_valid_inode_count == sbi->total_node_count);
++ f2fs_bug_on(sbi->total_valid_inode_count == sbi->total_node_count);
+ sbi->total_valid_inode_count++;
+ spin_unlock(&sbi->stat_lock);
+ }
+@@ -741,7 +754,7 @@
+ static inline int dec_valid_inode_count(struct f2fs_sb_info *sbi)
+ {
+ spin_lock(&sbi->stat_lock);
+- BUG_ON(!sbi->total_valid_inode_count);
++ f2fs_bug_on(!sbi->total_valid_inode_count);
+ sbi->total_valid_inode_count--;
+ spin_unlock(&sbi->stat_lock);
+ return 0;
+@@ -762,7 +775,7 @@
+ return;
+
+ if (unlock) {
+- BUG_ON(!PageLocked(page));
++ f2fs_bug_on(!PageLocked(page));
+ unlock_page(page);
+ }
+ page_cache_release(page);
+@@ -784,11 +797,25 @@
+ return kmem_cache_create(name, size, 0, SLAB_RECLAIM_ACCOUNT, ctor);
+ }
+
++static inline void *f2fs_kmem_cache_alloc(struct kmem_cache *cachep,
++ gfp_t flags)
++{
++ void *entry;
++retry:
++ entry = kmem_cache_alloc(cachep, flags);
++ if (!entry) {
++ cond_resched();
++ goto retry;
++ }
++
++ return entry;
++}
++
+ #define RAW_IS_INODE(p) ((p)->footer.nid == (p)->footer.ino)
+
+ static inline bool IS_INODE(struct page *page)
+ {
+- struct f2fs_node *p = (struct f2fs_node *)page_address(page);
++ struct f2fs_node *p = F2FS_NODE(page);
+ return RAW_IS_INODE(p);
+ }
+
+@@ -802,7 +829,7 @@
+ {
+ struct f2fs_node *raw_node;
+ __le32 *addr_array;
+- raw_node = (struct f2fs_node *)page_address(node_page);
++ raw_node = F2FS_NODE(node_page);
+ addr_array = blkaddr_in_node(raw_node);
+ return le32_to_cpu(addr_array[offset]);
+ }
+@@ -843,9 +870,13 @@
+ /* used for f2fs_inode_info->flags */
+ enum {
+ FI_NEW_INODE, /* indicate newly allocated inode */
++ FI_DIRTY_INODE, /* indicate inode is dirty or not */
+ FI_INC_LINK, /* need to increment i_nlink */
+ FI_ACL_MODE, /* indicate acl mode */
+ FI_NO_ALLOC, /* should not allocate any blocks */
++ FI_UPDATE_DIR, /* should update inode block for consistency */
++ FI_DELAY_IPUT, /* used for the recovery */
++ FI_INLINE_XATTR, /* used for inline xattr */
+ };
+
+ static inline void set_inode_flag(struct f2fs_inode_info *fi, int flag)
+@@ -878,14 +909,60 @@
+ return 0;
+ }
+
++static inline void get_inline_info(struct f2fs_inode_info *fi,
++ struct f2fs_inode *ri)
++{
++ if (ri->i_inline & F2FS_INLINE_XATTR)
++ set_inode_flag(fi, FI_INLINE_XATTR);
++}
++
++static inline void set_raw_inline(struct f2fs_inode_info *fi,
++ struct f2fs_inode *ri)
++{
++ ri->i_inline = 0;
++
++ if (is_inode_flag_set(fi, FI_INLINE_XATTR))
++ ri->i_inline |= F2FS_INLINE_XATTR;
++}
++
++static inline unsigned int addrs_per_inode(struct f2fs_inode_info *fi)
++{
++ if (is_inode_flag_set(fi, FI_INLINE_XATTR))
++ return DEF_ADDRS_PER_INODE - F2FS_INLINE_XATTR_ADDRS;
++ return DEF_ADDRS_PER_INODE;
++}
++
++static inline void *inline_xattr_addr(struct page *page)
++{
++ struct f2fs_inode *ri;
++ ri = (struct f2fs_inode *)page_address(page);
++ return (void *)&(ri->i_addr[DEF_ADDRS_PER_INODE -
++ F2FS_INLINE_XATTR_ADDRS]);
++}
++
++static inline int inline_xattr_size(struct inode *inode)
++{
++ if (is_inode_flag_set(F2FS_I(inode), FI_INLINE_XATTR))
++ return F2FS_INLINE_XATTR_ADDRS << 2;
++ else
++ return 0;
++}
++
++static inline int f2fs_readonly(struct super_block *sb)
++{
++ return sb->s_flags & MS_RDONLY;
++}
++
+ /*
+ * file.c
+ */
+ int f2fs_sync_file(struct file *, loff_t, loff_t, int);
+ void truncate_data_blocks(struct dnode_of_data *);
+ void f2fs_truncate(struct inode *);
++int f2fs_getattr(struct vfsmount *, struct dentry *, struct kstat *);
+ int f2fs_setattr(struct dentry *, struct iattr *);
+ int truncate_hole(struct inode *, pgoff_t, pgoff_t);
++int truncate_data_blocks_range(struct dnode_of_data *, int);
+ long f2fs_ioctl(struct file *, unsigned int, unsigned long);
+ long f2fs_compat_ioctl(struct file *, unsigned int, unsigned long);
+
+@@ -894,6 +971,7 @@
+ */
+ void f2fs_set_inode_flags(struct inode *);
+ struct inode *f2fs_iget(struct super_block *, unsigned long);
++int try_to_free_nats(struct f2fs_sb_info *, int);
+ void update_inode(struct inode *, struct page *);
+ int update_inode_page(struct inode *);
+ int f2fs_write_inode(struct inode *, struct writeback_control *);
+@@ -913,7 +991,7 @@
+ ino_t f2fs_inode_by_name(struct inode *, struct qstr *);
+ void f2fs_set_link(struct inode *, struct f2fs_dir_entry *,
+ struct page *, struct inode *);
+-void init_dent_inode(const struct qstr *, struct page *);
++int update_dent_inode(struct inode *, const struct qstr *);
+ int __f2fs_add_link(struct inode *, const struct qstr *, struct inode *);
+ void f2fs_delete_entry(struct f2fs_dir_entry *, struct page *, struct inode *);
+ int f2fs_make_empty(struct inode *, struct inode *);
+@@ -947,9 +1025,11 @@
+ void get_node_info(struct f2fs_sb_info *, nid_t, struct node_info *);
+ int get_dnode_of_data(struct dnode_of_data *, pgoff_t, int);
+ int truncate_inode_blocks(struct inode *, pgoff_t);
++int truncate_xattr_node(struct inode *, struct page *);
++int wait_on_node_pages_writeback(struct f2fs_sb_info *, nid_t);
+ int remove_inode_page(struct inode *);
+-int new_inode_page(struct inode *, const struct qstr *);
+-struct page *new_node_page(struct dnode_of_data *, unsigned int);
++struct page *new_inode_page(struct inode *, const struct qstr *);
++struct page *new_node_page(struct dnode_of_data *, unsigned int, struct page *);
+ void ra_node_page(struct f2fs_sb_info *, nid_t);
+ struct page *get_node_page(struct f2fs_sb_info *, pgoff_t);
+ struct page *get_node_page_ra(struct page *, int);
+@@ -973,14 +1053,15 @@
+ * segment.c
+ */
+ void f2fs_balance_fs(struct f2fs_sb_info *);
++void f2fs_balance_fs_bg(struct f2fs_sb_info *);
+ void invalidate_blocks(struct f2fs_sb_info *, block_t);
+-void locate_dirty_segment(struct f2fs_sb_info *, unsigned int);
+ void clear_prefree_segments(struct f2fs_sb_info *);
+ int npages_for_summary_flush(struct f2fs_sb_info *);
+ void allocate_new_segments(struct f2fs_sb_info *);
+ struct page *get_sum_page(struct f2fs_sb_info *, unsigned int);
+ struct bio *f2fs_bio_alloc(struct block_device *, int);
+-void f2fs_submit_bio(struct f2fs_sb_info *, enum page_type, bool sync);
++void f2fs_submit_bio(struct f2fs_sb_info *, enum page_type, bool);
++void f2fs_wait_on_page_writeback(struct page *, enum page_type, bool);
+ void write_meta_page(struct f2fs_sb_info *, struct page *);
+ void write_node_page(struct f2fs_sb_info *, struct page *, unsigned int,
+ block_t, block_t *);
+@@ -1005,13 +1086,16 @@
+ struct page *grab_meta_page(struct f2fs_sb_info *, pgoff_t);
+ struct page *get_meta_page(struct f2fs_sb_info *, pgoff_t);
+ long sync_meta_pages(struct f2fs_sb_info *, enum page_type, long);
+-int check_orphan_space(struct f2fs_sb_info *);
++int acquire_orphan_inode(struct f2fs_sb_info *);
++void release_orphan_inode(struct f2fs_sb_info *);
+ void add_orphan_inode(struct f2fs_sb_info *, nid_t);
+ void remove_orphan_inode(struct f2fs_sb_info *, nid_t);
+ int recover_orphan_inodes(struct f2fs_sb_info *);
+ int get_valid_checkpoint(struct f2fs_sb_info *);
+ void set_dirty_dir_page(struct inode *, struct page *);
++void add_dirty_dir_inode(struct inode *);
+ void remove_dirty_dir_inode(struct inode *);
++struct inode *check_dirty_dir_inode(struct f2fs_sb_info *, nid_t);
+ void sync_dirty_dir_inodes(struct f2fs_sb_info *);
+ void write_checkpoint(struct f2fs_sb_info *, bool);
+ void init_orphan_info(struct f2fs_sb_info *);
+@@ -1025,7 +1109,7 @@
+ void update_extent_cache(block_t, struct dnode_of_data *);
+ struct page *find_data_page(struct inode *, pgoff_t, bool);
+ struct page *get_lock_data_page(struct inode *, pgoff_t);
+-struct page *get_new_data_page(struct inode *, pgoff_t, bool);
++struct page *get_new_data_page(struct inode *, struct page *, pgoff_t, bool);
+ int f2fs_readpage(struct f2fs_sb_info *, struct page *, block_t, int);
+ int do_write_data_page(struct page *);
+
+@@ -1034,7 +1118,7 @@
+ */
+ int start_gc_thread(struct f2fs_sb_info *);
+ void stop_gc_thread(struct f2fs_sb_info *);
+-block_t start_bidx_of_node(unsigned int);
++block_t start_bidx_of_node(unsigned int, struct f2fs_inode_info *);
+ int f2fs_gc(struct f2fs_sb_info *);
+ void build_gc_manager(struct f2fs_sb_info *);
+ int __init create_gc_caches(void);
+@@ -1078,11 +1162,25 @@
+ unsigned base_mem, cache_mem;
+ };
+
+-#define stat_inc_call_count(si) ((si)->call_count++)
++static inline struct f2fs_stat_info *F2FS_STAT(struct f2fs_sb_info *sbi)
++{
++ return (struct f2fs_stat_info*)sbi->stat_info;
++}
++
++#define stat_inc_call_count(si) ((si)->call_count++)
++#define stat_inc_bggc_count(sbi) ((sbi)->bg_gc++)
++#define stat_inc_dirty_dir(sbi) ((sbi)->n_dirty_dirs++)
++#define stat_dec_dirty_dir(sbi) ((sbi)->n_dirty_dirs--)
++#define stat_inc_total_hit(sb) ((F2FS_SB(sb))->total_hit_ext++)
++#define stat_inc_read_hit(sb) ((F2FS_SB(sb))->read_hit_ext++)
++#define stat_inc_seg_type(sbi, curseg) \
++ ((sbi)->segment_count[(curseg)->alloc_type]++)
++#define stat_inc_block_count(sbi, curseg) \
++ ((sbi)->block_count[(curseg)->alloc_type]++)
+
+ #define stat_inc_seg_count(sbi, type) \
+ do { \
+- struct f2fs_stat_info *si = sbi->stat_info; \
++ struct f2fs_stat_info *si = F2FS_STAT(sbi); \
+ (si)->tot_segs++; \
+ if (type == SUM_TYPE_DATA) \
+ si->data_segs++; \
+@@ -1095,14 +1193,14 @@
+
+ #define stat_inc_data_blk_count(sbi, blks) \
+ do { \
+- struct f2fs_stat_info *si = sbi->stat_info; \
++ struct f2fs_stat_info *si = F2FS_STAT(sbi); \
+ stat_inc_tot_blk_count(si, blks); \
+ si->data_blks += (blks); \
+ } while (0)
+
+ #define stat_inc_node_blk_count(sbi, blks) \
+ do { \
+- struct f2fs_stat_info *si = sbi->stat_info; \
++ struct f2fs_stat_info *si = F2FS_STAT(sbi); \
+ stat_inc_tot_blk_count(si, blks); \
+ si->node_blks += (blks); \
+ } while (0)
+@@ -1113,6 +1211,13 @@
+ void f2fs_destroy_root_stats(void);
+ #else
+ #define stat_inc_call_count(si)
++#define stat_inc_bggc_count(si)
++#define stat_inc_dirty_dir(sbi)
++#define stat_dec_dirty_dir(sbi)
++#define stat_inc_total_hit(sb)
++#define stat_inc_read_hit(sb)
++#define stat_inc_seg_type(sbi, curseg)
++#define stat_inc_block_count(sbi, curseg)
+ #define stat_inc_seg_count(si, type)
+ #define stat_inc_tot_blk_count(si, blks)
+ #define stat_inc_data_blk_count(si, blks)
+diff -Nur linux-3.10.30.orig/fs/f2fs/file.c linux-linaro-stable-mx6/fs/f2fs/file.c
+--- linux-3.10.30.orig/fs/f2fs/file.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/file.c 2014-05-15 20:34:12.458118041 +0200
+@@ -35,18 +35,18 @@
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+ block_t old_blk_addr;
+ struct dnode_of_data dn;
+- int err, ilock;
++ int err;
+
+ f2fs_balance_fs(sbi);
+
+ sb_start_pagefault(inode->i_sb);
+
+ /* block allocation */
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ set_new_dnode(&dn, inode, NULL, NULL, 0);
+ err = get_dnode_of_data(&dn, page->index, ALLOC_NODE);
+ if (err) {
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ goto out;
+ }
+
+@@ -56,16 +56,17 @@
+ err = reserve_new_block(&dn);
+ if (err) {
+ f2fs_put_dnode(&dn);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ goto out;
+ }
+ }
+ f2fs_put_dnode(&dn);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+
++ file_update_time(vma->vm_file);
+ lock_page(page);
+ if (page->mapping != inode->i_mapping ||
+- page_offset(page) >= i_size_read(inode) ||
++ page_offset(page) > i_size_read(inode) ||
+ !PageUptodate(page)) {
+ unlock_page(page);
+ err = -EFAULT;
+@@ -76,10 +77,7 @@
+ * check to see if the page is mapped already (no holes)
+ */
+ if (PageMappedToDisk(page))
+- goto out;
+-
+- /* fill the page */
+- wait_on_page_writeback(page);
++ goto mapped;
+
+ /* page is wholly or partially inside EOF */
+ if (((page->index + 1) << PAGE_CACHE_SHIFT) > i_size_read(inode)) {
+@@ -90,7 +88,10 @@
+ set_page_dirty(page);
+ SetPageUptodate(page);
+
+- file_update_time(vma->vm_file);
++ trace_f2fs_vm_page_mkwrite(page, DATA);
++mapped:
++ /* fill the page */
++ wait_on_page_writeback(page);
+ out:
+ sb_end_pagefault(inode->i_sb);
+ return block_page_mkwrite_return(err);
+@@ -102,6 +103,26 @@
+ .remap_pages = generic_file_remap_pages,
+ };
+
++static int get_parent_ino(struct inode *inode, nid_t *pino)
++{
++ struct dentry *dentry;
++
++ inode = igrab(inode);
++ dentry = d_find_any_alias(inode);
++ iput(inode);
++ if (!dentry)
++ return 0;
++
++ if (update_dent_inode(inode, &dentry->d_name)) {
++ dput(dentry);
++ return 0;
++ }
++
++ *pino = parent_ino(dentry);
++ dput(dentry);
++ return 1;
++}
++
+ int f2fs_sync_file(struct file *file, loff_t start, loff_t end, int datasync)
+ {
+ struct inode *inode = file->f_mapping->host;
+@@ -114,7 +135,7 @@
+ .for_reclaim = 0,
+ };
+
+- if (inode->i_sb->s_flags & MS_RDONLY)
++ if (f2fs_readonly(inode->i_sb))
+ return 0;
+
+ trace_f2fs_sync_file_enter(inode);
+@@ -129,30 +150,48 @@
+
+ mutex_lock(&inode->i_mutex);
+
+- if (datasync && !(inode->i_state & I_DIRTY_DATASYNC))
+- goto out;
+-
++ /*
++ * Both of fdatasync() and fsync() are able to be recovered from
++ * sudden-power-off.
++ */
+ if (!S_ISREG(inode->i_mode) || inode->i_nlink != 1)
+ need_cp = true;
+- else if (is_cp_file(inode))
++ else if (file_wrong_pino(inode))
+ need_cp = true;
+ else if (!space_for_roll_forward(sbi))
+ need_cp = true;
+ else if (!is_checkpointed_node(sbi, F2FS_I(inode)->i_pino))
+ need_cp = true;
++ else if (F2FS_I(inode)->xattr_ver == cur_cp_version(F2FS_CKPT(sbi)))
++ need_cp = true;
+
+ if (need_cp) {
++ nid_t pino;
++
++ F2FS_I(inode)->xattr_ver = 0;
++
+ /* all the dirty node pages should be flushed for POR */
+ ret = f2fs_sync_fs(inode->i_sb, 1);
++ if (file_wrong_pino(inode) && inode->i_nlink == 1 &&
++ get_parent_ino(inode, &pino)) {
++ F2FS_I(inode)->i_pino = pino;
++ file_got_pino(inode);
++ mark_inode_dirty_sync(inode);
++ ret = f2fs_write_inode(inode, NULL);
++ if (ret)
++ goto out;
++ }
+ } else {
+ /* if there is no written node page, write its inode page */
+ while (!sync_node_pages(sbi, inode->i_ino, &wbc)) {
++ mark_inode_dirty_sync(inode);
+ ret = f2fs_write_inode(inode, NULL);
+ if (ret)
+ goto out;
+ }
+- filemap_fdatawait_range(sbi->node_inode->i_mapping,
+- 0, LONG_MAX);
++ ret = wait_on_node_pages_writeback(sbi, inode->i_ino);
++ if (ret)
++ goto out;
+ ret = blkdev_issue_flush(inode->i_sb->s_bdev, GFP_KERNEL, NULL);
+ }
+ out:
+@@ -168,14 +207,14 @@
+ return 0;
+ }
+
+-static int truncate_data_blocks_range(struct dnode_of_data *dn, int count)
++int truncate_data_blocks_range(struct dnode_of_data *dn, int count)
+ {
+ int nr_free = 0, ofs = dn->ofs_in_node;
+ struct f2fs_sb_info *sbi = F2FS_SB(dn->inode->i_sb);
+ struct f2fs_node *raw_node;
+ __le32 *addr;
+
+- raw_node = page_address(dn->node_page);
++ raw_node = F2FS_NODE(dn->node_page);
+ addr = blkaddr_in_node(raw_node) + ofs;
+
+ for ( ; count > 0; count--, addr++, dn->ofs_in_node++) {
+@@ -185,10 +224,10 @@
+
+ update_extent_cache(NULL_ADDR, dn);
+ invalidate_blocks(sbi, blkaddr);
+- dec_valid_block_count(sbi, dn->inode, 1);
+ nr_free++;
+ }
+ if (nr_free) {
++ dec_valid_block_count(sbi, dn->inode, nr_free);
+ set_page_dirty(dn->node_page);
+ sync_inode_page(dn);
+ }
+@@ -233,7 +272,7 @@
+ unsigned int blocksize = inode->i_sb->s_blocksize;
+ struct dnode_of_data dn;
+ pgoff_t free_from;
+- int count = 0, ilock = -1;
++ int count = 0;
+ int err;
+
+ trace_f2fs_truncate_blocks_enter(inode, from);
+@@ -241,24 +280,24 @@
+ free_from = (pgoff_t)
+ ((from + blocksize - 1) >> (sbi->log_blocksize));
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ set_new_dnode(&dn, inode, NULL, NULL, 0);
+ err = get_dnode_of_data(&dn, free_from, LOOKUP_NODE);
+ if (err) {
+ if (err == -ENOENT)
+ goto free_next;
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ trace_f2fs_truncate_blocks_exit(inode, err);
+ return err;
+ }
+
+ if (IS_INODE(dn.node_page))
+- count = ADDRS_PER_INODE;
++ count = ADDRS_PER_INODE(F2FS_I(inode));
+ else
+ count = ADDRS_PER_BLOCK;
+
+ count -= dn.ofs_in_node;
+- BUG_ON(count < 0);
++ f2fs_bug_on(count < 0);
+
+ if (dn.ofs_in_node || IS_INODE(dn.node_page)) {
+ truncate_data_blocks_range(&dn, count);
+@@ -268,7 +307,7 @@
+ f2fs_put_dnode(&dn);
+ free_next:
+ err = truncate_inode_blocks(inode, free_from);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+
+ /* lastly zero out the first data page */
+ truncate_partial_data_page(inode, from);
+@@ -291,7 +330,7 @@
+ }
+ }
+
+-static int f2fs_getattr(struct vfsmount *mnt,
++int f2fs_getattr(struct vfsmount *mnt,
+ struct dentry *dentry, struct kstat *stat)
+ {
+ struct inode *inode = dentry->d_inode;
+@@ -379,16 +418,15 @@
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+ struct page *page;
+- int ilock;
+
+ if (!len)
+ return;
+
+ f2fs_balance_fs(sbi);
+
+- ilock = mutex_lock_op(sbi);
+- page = get_new_data_page(inode, index, false);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_lock_op(sbi);
++ page = get_new_data_page(inode, NULL, index, false);
++ f2fs_unlock_op(sbi);
+
+ if (!IS_ERR(page)) {
+ wait_on_page_writeback(page);
+@@ -447,7 +485,6 @@
+ struct address_space *mapping = inode->i_mapping;
+ loff_t blk_start, blk_end;
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+- int ilock;
+
+ f2fs_balance_fs(sbi);
+
+@@ -456,9 +493,9 @@
+ truncate_inode_pages_range(mapping, blk_start,
+ blk_end - 1);
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ ret = truncate_hole(inode, pg_start, pg_end);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ }
+ }
+
+@@ -492,13 +529,12 @@
+
+ for (index = pg_start; index <= pg_end; index++) {
+ struct dnode_of_data dn;
+- int ilock;
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ set_new_dnode(&dn, inode, NULL, NULL, 0);
+ ret = get_dnode_of_data(&dn, index, ALLOC_NODE);
+ if (ret) {
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ break;
+ }
+
+@@ -506,12 +542,12 @@
+ ret = reserve_new_block(&dn);
+ if (ret) {
+ f2fs_put_dnode(&dn);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ break;
+ }
+ }
+ f2fs_put_dnode(&dn);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+
+ if (pg_start == pg_end)
+ new_size = offset + len;
+@@ -575,10 +611,10 @@
+ int ret;
+
+ switch (cmd) {
+- case FS_IOC_GETFLAGS:
++ case F2FS_IOC_GETFLAGS:
+ flags = fi->i_flags & FS_FL_USER_VISIBLE;
+ return put_user(flags, (int __user *) arg);
+- case FS_IOC_SETFLAGS:
++ case F2FS_IOC_SETFLAGS:
+ {
+ unsigned int oldflags;
+
+diff -Nur linux-3.10.30.orig/fs/f2fs/gc.c linux-linaro-stable-mx6/fs/f2fs/gc.c
+--- linux-3.10.30.orig/fs/f2fs/gc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/gc.c 2014-05-15 20:34:12.458118041 +0200
+@@ -29,10 +29,11 @@
+ static int gc_thread_func(void *data)
+ {
+ struct f2fs_sb_info *sbi = data;
++ struct f2fs_gc_kthread *gc_th = sbi->gc_thread;
+ wait_queue_head_t *wq = &sbi->gc_thread->gc_wait_queue_head;
+ long wait_ms;
+
+- wait_ms = GC_THREAD_MIN_SLEEP_TIME;
++ wait_ms = gc_th->min_sleep_time;
+
+ do {
+ if (try_to_freeze())
+@@ -45,7 +46,7 @@
+ break;
+
+ if (sbi->sb->s_writers.frozen >= SB_FREEZE_WRITE) {
+- wait_ms = GC_THREAD_MAX_SLEEP_TIME;
++ wait_ms = increase_sleep_time(gc_th, wait_ms);
+ continue;
+ }
+
+@@ -66,21 +67,25 @@
+ continue;
+
+ if (!is_idle(sbi)) {
+- wait_ms = increase_sleep_time(wait_ms);
++ wait_ms = increase_sleep_time(gc_th, wait_ms);
+ mutex_unlock(&sbi->gc_mutex);
+ continue;
+ }
+
+ if (has_enough_invalid_blocks(sbi))
+- wait_ms = decrease_sleep_time(wait_ms);
++ wait_ms = decrease_sleep_time(gc_th, wait_ms);
+ else
+- wait_ms = increase_sleep_time(wait_ms);
++ wait_ms = increase_sleep_time(gc_th, wait_ms);
+
+- sbi->bg_gc++;
++ stat_inc_bggc_count(sbi);
+
+ /* if return value is not zero, no victim was selected */
+ if (f2fs_gc(sbi))
+- wait_ms = GC_THREAD_NOGC_SLEEP_TIME;
++ wait_ms = gc_th->no_gc_sleep_time;
++
++ /* balancing f2fs's metadata periodically */
++ f2fs_balance_fs_bg(sbi);
++
+ } while (!kthread_should_stop());
+ return 0;
+ }
+@@ -89,23 +94,34 @@
+ {
+ struct f2fs_gc_kthread *gc_th;
+ dev_t dev = sbi->sb->s_bdev->bd_dev;
++ int err = 0;
+
+ if (!test_opt(sbi, BG_GC))
+- return 0;
++ goto out;
+ gc_th = kmalloc(sizeof(struct f2fs_gc_kthread), GFP_KERNEL);
+- if (!gc_th)
+- return -ENOMEM;
++ if (!gc_th) {
++ err = -ENOMEM;
++ goto out;
++ }
++
++ gc_th->min_sleep_time = DEF_GC_THREAD_MIN_SLEEP_TIME;
++ gc_th->max_sleep_time = DEF_GC_THREAD_MAX_SLEEP_TIME;
++ gc_th->no_gc_sleep_time = DEF_GC_THREAD_NOGC_SLEEP_TIME;
++
++ gc_th->gc_idle = 0;
+
+ sbi->gc_thread = gc_th;
+ init_waitqueue_head(&sbi->gc_thread->gc_wait_queue_head);
+ sbi->gc_thread->f2fs_gc_task = kthread_run(gc_thread_func, sbi,
+ "f2fs_gc-%u:%u", MAJOR(dev), MINOR(dev));
+ if (IS_ERR(gc_th->f2fs_gc_task)) {
++ err = PTR_ERR(gc_th->f2fs_gc_task);
+ kfree(gc_th);
+ sbi->gc_thread = NULL;
+- return -ENOMEM;
+ }
+- return 0;
++
++out:
++ return err;
+ }
+
+ void stop_gc_thread(struct f2fs_sb_info *sbi)
+@@ -118,9 +134,17 @@
+ sbi->gc_thread = NULL;
+ }
+
+-static int select_gc_type(int gc_type)
++static int select_gc_type(struct f2fs_gc_kthread *gc_th, int gc_type)
+ {
+- return (gc_type == BG_GC) ? GC_CB : GC_GREEDY;
++ int gc_mode = (gc_type == BG_GC) ? GC_CB : GC_GREEDY;
++
++ if (gc_th && gc_th->gc_idle) {
++ if (gc_th->gc_idle == 1)
++ gc_mode = GC_CB;
++ else if (gc_th->gc_idle == 2)
++ gc_mode = GC_GREEDY;
++ }
++ return gc_mode;
+ }
+
+ static void select_policy(struct f2fs_sb_info *sbi, int gc_type,
+@@ -131,12 +155,18 @@
+ if (p->alloc_mode == SSR) {
+ p->gc_mode = GC_GREEDY;
+ p->dirty_segmap = dirty_i->dirty_segmap[type];
++ p->max_search = dirty_i->nr_dirty[type];
+ p->ofs_unit = 1;
+ } else {
+- p->gc_mode = select_gc_type(gc_type);
++ p->gc_mode = select_gc_type(sbi->gc_thread, gc_type);
+ p->dirty_segmap = dirty_i->dirty_segmap[DIRTY];
++ p->max_search = dirty_i->nr_dirty[DIRTY];
+ p->ofs_unit = sbi->segs_per_sec;
+ }
++
++ if (p->max_search > MAX_VICTIM_SEARCH)
++ p->max_search = MAX_VICTIM_SEARCH;
++
+ p->offset = sbi->last_victim[p->gc_mode];
+ }
+
+@@ -208,8 +238,8 @@
+ return UINT_MAX - ((100 * (100 - u) * age) / (100 + u));
+ }
+
+-static unsigned int get_gc_cost(struct f2fs_sb_info *sbi, unsigned int segno,
+- struct victim_sel_policy *p)
++static inline unsigned int get_gc_cost(struct f2fs_sb_info *sbi,
++ unsigned int segno, struct victim_sel_policy *p)
+ {
+ if (p->alloc_mode == SSR)
+ return get_seg_entry(sbi, segno)->ckpt_valid_blocks;
+@@ -234,14 +264,14 @@
+ {
+ struct dirty_seglist_info *dirty_i = DIRTY_I(sbi);
+ struct victim_sel_policy p;
+- unsigned int secno;
++ unsigned int secno, max_cost;
+ int nsearched = 0;
+
+ p.alloc_mode = alloc_mode;
+ select_policy(sbi, gc_type, type, &p);
+
+ p.min_segno = NULL_SEGNO;
+- p.min_cost = get_max_cost(sbi, &p);
++ p.min_cost = max_cost = get_max_cost(sbi, &p);
+
+ mutex_lock(&dirty_i->seglist_lock);
+
+@@ -265,7 +295,11 @@
+ }
+ break;
+ }
+- p.offset = ((segno / p.ofs_unit) * p.ofs_unit) + p.ofs_unit;
++
++ p.offset = segno + p.ofs_unit;
++ if (p.ofs_unit > 1)
++ p.offset -= segno % p.ofs_unit;
++
+ secno = GET_SECNO(sbi, segno);
+
+ if (sec_usage_check(sbi, secno))
+@@ -278,18 +312,17 @@
+ if (p.min_cost > cost) {
+ p.min_segno = segno;
+ p.min_cost = cost;
+- }
+-
+- if (cost == get_max_cost(sbi, &p))
++ } else if (unlikely(cost == max_cost)) {
+ continue;
++ }
+
+- if (nsearched++ >= MAX_VICTIM_SEARCH) {
++ if (nsearched++ >= p.max_search) {
+ sbi->last_victim[p.gc_mode] = segno;
+ break;
+ }
+ }
+-got_it:
+ if (p.min_segno != NULL_SEGNO) {
++got_it:
+ if (p.alloc_mode == LFS) {
+ secno = GET_SECNO(sbi, p.min_segno);
+ if (gc_type == FG_GC)
+@@ -314,35 +347,24 @@
+
+ static struct inode *find_gc_inode(nid_t ino, struct list_head *ilist)
+ {
+- struct list_head *this;
+ struct inode_entry *ie;
+
+- list_for_each(this, ilist) {
+- ie = list_entry(this, struct inode_entry, list);
++ list_for_each_entry(ie, ilist, list)
+ if (ie->inode->i_ino == ino)
+ return ie->inode;
+- }
+ return NULL;
+ }
+
+ static void add_gc_inode(struct inode *inode, struct list_head *ilist)
+ {
+- struct list_head *this;
+- struct inode_entry *new_ie, *ie;
++ struct inode_entry *new_ie;
+
+- list_for_each(this, ilist) {
+- ie = list_entry(this, struct inode_entry, list);
+- if (ie->inode == inode) {
+- iput(inode);
+- return;
+- }
+- }
+-repeat:
+- new_ie = kmem_cache_alloc(winode_slab, GFP_NOFS);
+- if (!new_ie) {
+- cond_resched();
+- goto repeat;
++ if (inode == find_gc_inode(inode->i_ino, ilist)) {
++ iput(inode);
++ return;
+ }
++
++ new_ie = f2fs_kmem_cache_alloc(winode_slab, GFP_NOFS);
+ new_ie->inode = inode;
+ list_add_tail(&new_ie->list, ilist);
+ }
+@@ -407,8 +429,7 @@
+
+ /* set page dirty and write it */
+ if (gc_type == FG_GC) {
+- f2fs_submit_bio(sbi, NODE, true);
+- wait_on_page_writeback(node_page);
++ f2fs_wait_on_page_writeback(node_page, NODE, true);
+ set_page_dirty(node_page);
+ } else {
+ if (!PageWriteback(node_page))
+@@ -447,7 +468,7 @@
+ * as indirect or double indirect node blocks, are given, it must be a caller's
+ * bug.
+ */
+-block_t start_bidx_of_node(unsigned int node_ofs)
++block_t start_bidx_of_node(unsigned int node_ofs, struct f2fs_inode_info *fi)
+ {
+ unsigned int indirect_blks = 2 * NIDS_PER_BLOCK + 4;
+ unsigned int bidx;
+@@ -464,7 +485,7 @@
+ int dec = (node_ofs - indirect_blks - 3) / (NIDS_PER_BLOCK + 1);
+ bidx = node_ofs - 5 - dec;
+ }
+- return bidx * ADDRS_PER_BLOCK + ADDRS_PER_INODE;
++ return bidx * ADDRS_PER_BLOCK + ADDRS_PER_INODE(fi);
+ }
+
+ static int check_dnode(struct f2fs_sb_info *sbi, struct f2fs_summary *sum,
+@@ -508,10 +529,7 @@
+ } else {
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+
+- if (PageWriteback(page)) {
+- f2fs_submit_bio(sbi, DATA, true);
+- wait_on_page_writeback(page);
+- }
++ f2fs_wait_on_page_writeback(page, DATA, true);
+
+ if (clear_page_dirty_for_io(page) &&
+ S_ISDIR(inode->i_mode)) {
+@@ -575,7 +593,6 @@
+ continue;
+ }
+
+- start_bidx = start_bidx_of_node(nofs);
+ ofs_in_node = le16_to_cpu(entry->ofs_in_node);
+
+ if (phase == 2) {
+@@ -583,6 +600,8 @@
+ if (IS_ERR(inode))
+ continue;
+
++ start_bidx = start_bidx_of_node(nofs, F2FS_I(inode));
++
+ data_page = find_data_page(inode,
+ start_bidx + ofs_in_node, false);
+ if (IS_ERR(data_page))
+@@ -593,6 +612,8 @@
+ } else {
+ inode = find_gc_inode(dni.ino, ilist);
+ if (inode) {
++ start_bidx = start_bidx_of_node(nofs,
++ F2FS_I(inode));
+ data_page = get_lock_data_page(inode,
+ start_bidx + ofs_in_node);
+ if (IS_ERR(data_page))
+diff -Nur linux-3.10.30.orig/fs/f2fs/gc.h linux-linaro-stable-mx6/fs/f2fs/gc.h
+--- linux-3.10.30.orig/fs/f2fs/gc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/gc.h 2014-05-15 20:34:12.458118041 +0200
+@@ -13,18 +13,26 @@
+ * whether IO subsystem is idle
+ * or not
+ */
+-#define GC_THREAD_MIN_SLEEP_TIME 30000 /* milliseconds */
+-#define GC_THREAD_MAX_SLEEP_TIME 60000
+-#define GC_THREAD_NOGC_SLEEP_TIME 300000 /* wait 5 min */
++#define DEF_GC_THREAD_MIN_SLEEP_TIME 30000 /* milliseconds */
++#define DEF_GC_THREAD_MAX_SLEEP_TIME 60000
++#define DEF_GC_THREAD_NOGC_SLEEP_TIME 300000 /* wait 5 min */
+ #define LIMIT_INVALID_BLOCK 40 /* percentage over total user space */
+ #define LIMIT_FREE_BLOCK 40 /* percentage over invalid + free space */
+
+ /* Search max. number of dirty segments to select a victim segment */
+-#define MAX_VICTIM_SEARCH 20
++#define MAX_VICTIM_SEARCH 4096 /* covers 8GB */
+
+ struct f2fs_gc_kthread {
+ struct task_struct *f2fs_gc_task;
+ wait_queue_head_t gc_wait_queue_head;
++
++ /* for gc sleep time */
++ unsigned int min_sleep_time;
++ unsigned int max_sleep_time;
++ unsigned int no_gc_sleep_time;
++
++ /* for changing gc mode */
++ unsigned int gc_idle;
+ };
+
+ struct inode_entry {
+@@ -56,25 +64,25 @@
+ return (long)(reclaimable_user_blocks * LIMIT_FREE_BLOCK) / 100;
+ }
+
+-static inline long increase_sleep_time(long wait)
++static inline long increase_sleep_time(struct f2fs_gc_kthread *gc_th, long wait)
+ {
+- if (wait == GC_THREAD_NOGC_SLEEP_TIME)
++ if (wait == gc_th->no_gc_sleep_time)
+ return wait;
+
+- wait += GC_THREAD_MIN_SLEEP_TIME;
+- if (wait > GC_THREAD_MAX_SLEEP_TIME)
+- wait = GC_THREAD_MAX_SLEEP_TIME;
++ wait += gc_th->min_sleep_time;
++ if (wait > gc_th->max_sleep_time)
++ wait = gc_th->max_sleep_time;
+ return wait;
+ }
+
+-static inline long decrease_sleep_time(long wait)
++static inline long decrease_sleep_time(struct f2fs_gc_kthread *gc_th, long wait)
+ {
+- if (wait == GC_THREAD_NOGC_SLEEP_TIME)
+- wait = GC_THREAD_MAX_SLEEP_TIME;
++ if (wait == gc_th->no_gc_sleep_time)
++ wait = gc_th->max_sleep_time;
+
+- wait -= GC_THREAD_MIN_SLEEP_TIME;
+- if (wait <= GC_THREAD_MIN_SLEEP_TIME)
+- wait = GC_THREAD_MIN_SLEEP_TIME;
++ wait -= gc_th->min_sleep_time;
++ if (wait <= gc_th->min_sleep_time)
++ wait = gc_th->min_sleep_time;
+ return wait;
+ }
+
+diff -Nur linux-3.10.30.orig/fs/f2fs/inode.c linux-linaro-stable-mx6/fs/f2fs/inode.c
+--- linux-3.10.30.orig/fs/f2fs/inode.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/inode.c 2014-05-15 20:34:12.458118041 +0200
+@@ -37,6 +37,31 @@
+ inode->i_flags |= S_DIRSYNC;
+ }
+
++static void __get_inode_rdev(struct inode *inode, struct f2fs_inode *ri)
++{
++ if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode) ||
++ S_ISFIFO(inode->i_mode) || S_ISSOCK(inode->i_mode)) {
++ if (ri->i_addr[0])
++ inode->i_rdev = old_decode_dev(le32_to_cpu(ri->i_addr[0]));
++ else
++ inode->i_rdev = new_decode_dev(le32_to_cpu(ri->i_addr[1]));
++ }
++}
++
++static void __set_inode_rdev(struct inode *inode, struct f2fs_inode *ri)
++{
++ if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode)) {
++ if (old_valid_dev(inode->i_rdev)) {
++ ri->i_addr[0] = cpu_to_le32(old_encode_dev(inode->i_rdev));
++ ri->i_addr[1] = 0;
++ } else {
++ ri->i_addr[0] = 0;
++ ri->i_addr[1] = cpu_to_le32(new_encode_dev(inode->i_rdev));
++ ri->i_addr[2] = 0;
++ }
++ }
++}
++
+ static int do_read_inode(struct inode *inode)
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+@@ -56,7 +81,7 @@
+ if (IS_ERR(node_page))
+ return PTR_ERR(node_page);
+
+- rn = page_address(node_page);
++ rn = F2FS_NODE(node_page);
+ ri = &(rn->i);
+
+ inode->i_mode = le16_to_cpu(ri->i_mode);
+@@ -73,10 +98,6 @@
+ inode->i_ctime.tv_nsec = le32_to_cpu(ri->i_ctime_nsec);
+ inode->i_mtime.tv_nsec = le32_to_cpu(ri->i_mtime_nsec);
+ inode->i_generation = le32_to_cpu(ri->i_generation);
+- if (ri->i_addr[0])
+- inode->i_rdev = old_decode_dev(le32_to_cpu(ri->i_addr[0]));
+- else
+- inode->i_rdev = new_decode_dev(le32_to_cpu(ri->i_addr[1]));
+
+ fi->i_current_depth = le32_to_cpu(ri->i_current_depth);
+ fi->i_xattr_nid = le32_to_cpu(ri->i_xattr_nid);
+@@ -84,7 +105,13 @@
+ fi->flags = 0;
+ fi->i_advise = ri->i_advise;
+ fi->i_pino = le32_to_cpu(ri->i_pino);
++
+ get_extent_info(&fi->ext, ri->i_ext);
++ get_inline_info(fi, ri);
++
++ /* get rdev by using inline_info */
++ __get_inode_rdev(inode, ri);
++
+ f2fs_put_page(node_page, 1);
+ return 0;
+ }
+@@ -109,12 +136,6 @@
+ ret = do_read_inode(inode);
+ if (ret)
+ goto bad_inode;
+-
+- if (!sbi->por_doing && inode->i_nlink == 0) {
+- ret = -ENOENT;
+- goto bad_inode;
+- }
+-
+ make_now:
+ if (ino == F2FS_NODE_INO(sbi)) {
+ inode->i_mapping->a_ops = &f2fs_node_aops;
+@@ -130,8 +151,7 @@
+ inode->i_op = &f2fs_dir_inode_operations;
+ inode->i_fop = &f2fs_dir_operations;
+ inode->i_mapping->a_ops = &f2fs_dblock_aops;
+- mapping_set_gfp_mask(inode->i_mapping, GFP_HIGHUSER_MOVABLE |
+- __GFP_ZERO);
++ mapping_set_gfp_mask(inode->i_mapping, GFP_F2FS_ZERO);
+ } else if (S_ISLNK(inode->i_mode)) {
+ inode->i_op = &f2fs_symlink_inode_operations;
+ inode->i_mapping->a_ops = &f2fs_dblock_aops;
+@@ -158,9 +178,9 @@
+ struct f2fs_node *rn;
+ struct f2fs_inode *ri;
+
+- wait_on_page_writeback(node_page);
++ f2fs_wait_on_page_writeback(node_page, NODE, false);
+
+- rn = page_address(node_page);
++ rn = F2FS_NODE(node_page);
+ ri = &(rn->i);
+
+ ri->i_mode = cpu_to_le16(inode->i_mode);
+@@ -171,6 +191,7 @@
+ ri->i_size = cpu_to_le64(i_size_read(inode));
+ ri->i_blocks = cpu_to_le64(inode->i_blocks);
+ set_raw_extent(&F2FS_I(inode)->ext, &ri->i_ext);
++ set_raw_inline(F2FS_I(inode), ri);
+
+ ri->i_atime = cpu_to_le64(inode->i_atime.tv_sec);
+ ri->i_ctime = cpu_to_le64(inode->i_ctime.tv_sec);
+@@ -184,21 +205,11 @@
+ ri->i_pino = cpu_to_le32(F2FS_I(inode)->i_pino);
+ ri->i_generation = cpu_to_le32(inode->i_generation);
+
+- if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode)) {
+- if (old_valid_dev(inode->i_rdev)) {
+- ri->i_addr[0] =
+- cpu_to_le32(old_encode_dev(inode->i_rdev));
+- ri->i_addr[1] = 0;
+- } else {
+- ri->i_addr[0] = 0;
+- ri->i_addr[1] =
+- cpu_to_le32(new_encode_dev(inode->i_rdev));
+- ri->i_addr[2] = 0;
+- }
+- }
+-
++ __set_inode_rdev(inode, ri);
+ set_cold_node(inode, node_page);
+ set_page_dirty(node_page);
++
++ clear_inode_flag(F2FS_I(inode), FI_DIRTY_INODE);
+ }
+
+ int update_inode_page(struct inode *inode)
+@@ -218,22 +229,26 @@
+ int f2fs_write_inode(struct inode *inode, struct writeback_control *wbc)
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+- int ret, ilock;
++ int ret;
+
+ if (inode->i_ino == F2FS_NODE_INO(sbi) ||
+ inode->i_ino == F2FS_META_INO(sbi))
+ return 0;
+
+- if (wbc)
+- f2fs_balance_fs(sbi);
++ if (!is_inode_flag_set(F2FS_I(inode), FI_DIRTY_INODE))
++ return 0;
+
+ /*
+ * We need to lock here to prevent from producing dirty node pages
+ * during the urgent cleaning time when runing out of free sections.
+ */
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ ret = update_inode_page(inode);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
++
++ if (wbc)
++ f2fs_balance_fs(sbi);
++
+ return ret;
+ }
+
+@@ -243,7 +258,6 @@
+ void f2fs_evict_inode(struct inode *inode)
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+- int ilock;
+
+ trace_f2fs_evict_inode(inode);
+ truncate_inode_pages(&inode->i_data, 0);
+@@ -252,7 +266,7 @@
+ inode->i_ino == F2FS_META_INO(sbi))
+ goto no_delete;
+
+- BUG_ON(atomic_read(&F2FS_I(inode)->dirty_dents));
++ f2fs_bug_on(atomic_read(&F2FS_I(inode)->dirty_dents));
+ remove_dirty_dir_inode(inode);
+
+ if (inode->i_nlink || is_bad_inode(inode))
+@@ -265,9 +279,9 @@
+ if (F2FS_HAS_BLOCKS(inode))
+ f2fs_truncate(inode);
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ remove_inode_page(inode);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+
+ sb_end_intwrite(inode->i_sb);
+ no_delete:
+diff -Nur linux-3.10.30.orig/fs/f2fs/Kconfig linux-linaro-stable-mx6/fs/f2fs/Kconfig
+--- linux-3.10.30.orig/fs/f2fs/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/Kconfig 2014-05-15 20:34:12.430117839 +0200
+@@ -51,3 +51,23 @@
+ Linux website <http://acl.bestbits.at/>.
+
+ If you don't know what Access Control Lists are, say N
++
++config F2FS_FS_SECURITY
++ bool "F2FS Security Labels"
++ depends on F2FS_FS_XATTR
++ help
++ Security labels provide an access control facility to support Linux
++ Security Models (LSMs) accepted by AppArmor, SELinux, Smack and TOMOYO
++ Linux. This option enables an extended attribute handler for file
++ security labels in the f2fs filesystem, so that it requires enabling
++ the extended attribute support in advance.
++
++ If you are not using a security module, say N.
++
++config F2FS_CHECK_FS
++ bool "F2FS consistency checking feature"
++ depends on F2FS_FS
++ help
++ Enables BUG_ONs which check the file system consistency in runtime.
++
++ If you want to improve the performance, say N.
+diff -Nur linux-3.10.30.orig/fs/f2fs/namei.c linux-linaro-stable-mx6/fs/f2fs/namei.c
+--- linux-3.10.30.orig/fs/f2fs/namei.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/namei.c 2014-05-15 20:34:12.458118041 +0200
+@@ -27,19 +27,19 @@
+ nid_t ino;
+ struct inode *inode;
+ bool nid_free = false;
+- int err, ilock;
++ int err;
+
+ inode = new_inode(sb);
+ if (!inode)
+ return ERR_PTR(-ENOMEM);
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ if (!alloc_nid(sbi, &ino)) {
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ err = -ENOSPC;
+ goto fail;
+ }
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+
+ inode->i_uid = current_fsuid();
+
+@@ -83,21 +83,11 @@
+ {
+ size_t slen = strlen(s);
+ size_t sublen = strlen(sub);
+- int ret;
+
+ if (sublen > slen)
+ return 0;
+
+- ret = memcmp(s + slen - sublen, sub, sublen);
+- if (ret) { /* compare upper case */
+- int i;
+- char upper_sub[8];
+- for (i = 0; i < sublen && i < sizeof(upper_sub); i++)
+- upper_sub[i] = toupper(sub[i]);
+- return !memcmp(s + slen - sublen, upper_sub, sublen);
+- }
+-
+- return !ret;
++ return !strncasecmp(s + slen - sublen, sub, sublen);
+ }
+
+ /*
+@@ -112,7 +102,7 @@
+ int count = le32_to_cpu(sbi->raw_super->extension_count);
+ for (i = 0; i < count; i++) {
+ if (is_multimedia_file(name, extlist[i])) {
+- set_cold_file(inode);
++ file_set_cold(inode);
+ break;
+ }
+ }
+@@ -125,7 +115,7 @@
+ struct f2fs_sb_info *sbi = F2FS_SB(sb);
+ struct inode *inode;
+ nid_t ino = 0;
+- int err, ilock;
++ int err;
+
+ f2fs_balance_fs(sbi);
+
+@@ -141,16 +131,15 @@
+ inode->i_mapping->a_ops = &f2fs_dblock_aops;
+ ino = inode->i_ino;
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ err = f2fs_add_link(dentry, inode);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ if (err)
+ goto out;
+
+ alloc_nid_done(sbi, ino);
+
+- if (!sbi->por_doing)
+- d_instantiate(dentry, inode);
++ d_instantiate(dentry, inode);
+ unlock_new_inode(inode);
+ return 0;
+ out:
+@@ -168,31 +157,24 @@
+ struct inode *inode = old_dentry->d_inode;
+ struct super_block *sb = dir->i_sb;
+ struct f2fs_sb_info *sbi = F2FS_SB(sb);
+- int err, ilock;
++ int err;
+
+ f2fs_balance_fs(sbi);
+
+ inode->i_ctime = CURRENT_TIME;
+- atomic_inc(&inode->i_count);
++ ihold(inode);
+
+ set_inode_flag(F2FS_I(inode), FI_INC_LINK);
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ err = f2fs_add_link(dentry, inode);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ if (err)
+ goto out;
+
+- /*
+- * This file should be checkpointed during fsync.
+- * We lost i_pino from now on.
+- */
+- set_cp_file(inode);
+-
+ d_instantiate(dentry, inode);
+ return 0;
+ out:
+ clear_inode_flag(F2FS_I(inode), FI_INC_LINK);
+- make_bad_inode(inode);
+ iput(inode);
+ return err;
+ }
+@@ -238,7 +220,6 @@
+ struct f2fs_dir_entry *de;
+ struct page *page;
+ int err = -ENOENT;
+- int ilock;
+
+ trace_f2fs_unlink_enter(dir, dentry);
+ f2fs_balance_fs(sbi);
+@@ -247,16 +228,16 @@
+ if (!de)
+ goto fail;
+
+- err = check_orphan_space(sbi);
++ f2fs_lock_op(sbi);
++ err = acquire_orphan_inode(sbi);
+ if (err) {
++ f2fs_unlock_op(sbi);
+ kunmap(page);
+ f2fs_put_page(page, 0);
+ goto fail;
+ }
+-
+- ilock = mutex_lock_op(sbi);
+ f2fs_delete_entry(de, page, inode);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+
+ /* In order to evict this inode, we set it dirty */
+ mark_inode_dirty(inode);
+@@ -272,7 +253,7 @@
+ struct f2fs_sb_info *sbi = F2FS_SB(sb);
+ struct inode *inode;
+ size_t symlen = strlen(symname) + 1;
+- int err, ilock;
++ int err;
+
+ f2fs_balance_fs(sbi);
+
+@@ -283,9 +264,9 @@
+ inode->i_op = &f2fs_symlink_inode_operations;
+ inode->i_mapping->a_ops = &f2fs_dblock_aops;
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ err = f2fs_add_link(dentry, inode);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ if (err)
+ goto out;
+
+@@ -308,7 +289,7 @@
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(dir->i_sb);
+ struct inode *inode;
+- int err, ilock;
++ int err;
+
+ f2fs_balance_fs(sbi);
+
+@@ -322,9 +303,9 @@
+ mapping_set_gfp_mask(inode->i_mapping, GFP_F2FS_ZERO);
+
+ set_inode_flag(F2FS_I(inode), FI_INC_LINK);
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ err = f2fs_add_link(dentry, inode);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ if (err)
+ goto out_fail;
+
+@@ -360,7 +341,6 @@
+ struct f2fs_sb_info *sbi = F2FS_SB(sb);
+ struct inode *inode;
+ int err = 0;
+- int ilock;
+
+ if (!new_valid_dev(rdev))
+ return -EINVAL;
+@@ -374,9 +354,9 @@
+ init_special_inode(inode, inode->i_mode, rdev);
+ inode->i_op = &f2fs_special_inode_operations;
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ err = f2fs_add_link(dentry, inode);
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ if (err)
+ goto out;
+
+@@ -401,11 +381,11 @@
+ struct inode *old_inode = old_dentry->d_inode;
+ struct inode *new_inode = new_dentry->d_inode;
+ struct page *old_dir_page;
+- struct page *old_page;
++ struct page *old_page, *new_page;
+ struct f2fs_dir_entry *old_dir_entry = NULL;
+ struct f2fs_dir_entry *old_entry;
+ struct f2fs_dir_entry *new_entry;
+- int err = -ENOENT, ilock = -1;
++ int err = -ENOENT;
+
+ f2fs_balance_fs(sbi);
+
+@@ -420,10 +400,9 @@
+ goto out_old;
+ }
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+
+ if (new_inode) {
+- struct page *new_page;
+
+ err = -ENOTEMPTY;
+ if (old_dir_entry && !f2fs_empty_dir(new_inode))
+@@ -435,14 +414,28 @@
+ if (!new_entry)
+ goto out_dir;
+
++ err = acquire_orphan_inode(sbi);
++ if (err)
++ goto put_out_dir;
++
++ if (update_dent_inode(old_inode, &new_dentry->d_name)) {
++ release_orphan_inode(sbi);
++ goto put_out_dir;
++ }
++
+ f2fs_set_link(new_dir, new_entry, new_page, old_inode);
+
+ new_inode->i_ctime = CURRENT_TIME;
+ if (old_dir_entry)
+ drop_nlink(new_inode);
+ drop_nlink(new_inode);
++
+ if (!new_inode->i_nlink)
+ add_orphan_inode(sbi, new_inode->i_ino);
++ else
++ release_orphan_inode(sbi);
++
++ update_inode_page(old_inode);
+ update_inode_page(new_inode);
+ } else {
+ err = f2fs_add_link(new_dentry, old_inode);
+@@ -472,15 +465,17 @@
+ update_inode_page(old_dir);
+ }
+
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ return 0;
+
++put_out_dir:
++ f2fs_put_page(new_page, 1);
+ out_dir:
+ if (old_dir_entry) {
+ kunmap(old_dir_page);
+ f2fs_put_page(old_dir_page, 0);
+ }
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ out_old:
+ kunmap(old_page);
+ f2fs_put_page(old_page, 0);
+@@ -498,6 +493,7 @@
+ .rmdir = f2fs_rmdir,
+ .mknod = f2fs_mknod,
+ .rename = f2fs_rename,
++ .getattr = f2fs_getattr,
+ .setattr = f2fs_setattr,
+ .get_acl = f2fs_get_acl,
+ #ifdef CONFIG_F2FS_FS_XATTR
+@@ -512,6 +508,7 @@
+ .readlink = generic_readlink,
+ .follow_link = page_follow_link_light,
+ .put_link = page_put_link,
++ .getattr = f2fs_getattr,
+ .setattr = f2fs_setattr,
+ #ifdef CONFIG_F2FS_FS_XATTR
+ .setxattr = generic_setxattr,
+@@ -522,6 +519,7 @@
+ };
+
+ const struct inode_operations f2fs_special_inode_operations = {
++ .getattr = f2fs_getattr,
+ .setattr = f2fs_setattr,
+ .get_acl = f2fs_get_acl,
+ #ifdef CONFIG_F2FS_FS_XATTR
+diff -Nur linux-3.10.30.orig/fs/f2fs/node.c linux-linaro-stable-mx6/fs/f2fs/node.c
+--- linux-3.10.30.orig/fs/f2fs/node.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/node.c 2014-05-15 20:34:12.458118041 +0200
+@@ -204,7 +204,7 @@
+ }
+ e->ni = *ni;
+ e->checkpointed = true;
+- BUG_ON(ni->blk_addr == NEW_ADDR);
++ f2fs_bug_on(ni->blk_addr == NEW_ADDR);
+ } else if (new_blkaddr == NEW_ADDR) {
+ /*
+ * when nid is reallocated,
+@@ -212,19 +212,19 @@
+ * So, reinitialize it with new information.
+ */
+ e->ni = *ni;
+- BUG_ON(ni->blk_addr != NULL_ADDR);
++ f2fs_bug_on(ni->blk_addr != NULL_ADDR);
+ }
+
+ if (new_blkaddr == NEW_ADDR)
+ e->checkpointed = false;
+
+ /* sanity check */
+- BUG_ON(nat_get_blkaddr(e) != ni->blk_addr);
+- BUG_ON(nat_get_blkaddr(e) == NULL_ADDR &&
++ f2fs_bug_on(nat_get_blkaddr(e) != ni->blk_addr);
++ f2fs_bug_on(nat_get_blkaddr(e) == NULL_ADDR &&
+ new_blkaddr == NULL_ADDR);
+- BUG_ON(nat_get_blkaddr(e) == NEW_ADDR &&
++ f2fs_bug_on(nat_get_blkaddr(e) == NEW_ADDR &&
+ new_blkaddr == NEW_ADDR);
+- BUG_ON(nat_get_blkaddr(e) != NEW_ADDR &&
++ f2fs_bug_on(nat_get_blkaddr(e) != NEW_ADDR &&
+ nat_get_blkaddr(e) != NULL_ADDR &&
+ new_blkaddr == NEW_ADDR);
+
+@@ -240,7 +240,7 @@
+ write_unlock(&nm_i->nat_tree_lock);
+ }
+
+-static int try_to_free_nats(struct f2fs_sb_info *sbi, int nr_shrink)
++int try_to_free_nats(struct f2fs_sb_info *sbi, int nr_shrink)
+ {
+ struct f2fs_nm_info *nm_i = NM_I(sbi);
+
+@@ -315,9 +315,10 @@
+ * The maximum depth is four.
+ * Offset[0] will have raw inode offset.
+ */
+-static int get_node_path(long block, int offset[4], unsigned int noffset[4])
++static int get_node_path(struct f2fs_inode_info *fi, long block,
++ int offset[4], unsigned int noffset[4])
+ {
+- const long direct_index = ADDRS_PER_INODE;
++ const long direct_index = ADDRS_PER_INODE(fi);
+ const long direct_blks = ADDRS_PER_BLOCK;
+ const long dptrs_per_blk = NIDS_PER_BLOCK;
+ const long indirect_blks = ADDRS_PER_BLOCK * NIDS_PER_BLOCK;
+@@ -405,13 +406,16 @@
+ int level, i;
+ int err = 0;
+
+- level = get_node_path(index, offset, noffset);
++ level = get_node_path(F2FS_I(dn->inode), index, offset, noffset);
+
+ nids[0] = dn->inode->i_ino;
+- npage[0] = get_node_page(sbi, nids[0]);
+- if (IS_ERR(npage[0]))
+- return PTR_ERR(npage[0]);
++ npage[0] = dn->inode_page;
+
++ if (!npage[0]) {
++ npage[0] = get_node_page(sbi, nids[0]);
++ if (IS_ERR(npage[0]))
++ return PTR_ERR(npage[0]);
++ }
+ parent = npage[0];
+ if (level != 0)
+ nids[1] = get_nid(parent, offset[0], true);
+@@ -430,7 +434,7 @@
+ }
+
+ dn->nid = nids[i];
+- npage[i] = new_node_page(dn, noffset[i]);
++ npage[i] = new_node_page(dn, noffset[i], NULL);
+ if (IS_ERR(npage[i])) {
+ alloc_nid_failed(sbi, nids[i]);
+ err = PTR_ERR(npage[i]);
+@@ -491,10 +495,10 @@
+
+ get_node_info(sbi, dn->nid, &ni);
+ if (dn->inode->i_blocks == 0) {
+- BUG_ON(ni.blk_addr != NULL_ADDR);
++ f2fs_bug_on(ni.blk_addr != NULL_ADDR);
+ goto invalidate;
+ }
+- BUG_ON(ni.blk_addr == NULL_ADDR);
++ f2fs_bug_on(ni.blk_addr == NULL_ADDR);
+
+ /* Deallocate node address */
+ invalidate_blocks(sbi, ni.blk_addr);
+@@ -562,7 +566,7 @@
+ return PTR_ERR(page);
+ }
+
+- rn = (struct f2fs_node *)page_address(page);
++ rn = F2FS_NODE(page);
+ if (depth < 3) {
+ for (i = ofs; i < NIDS_PER_BLOCK; i++, freed++) {
+ child_nid = le32_to_cpu(rn->in.nid[i]);
+@@ -684,7 +688,7 @@
+
+ trace_f2fs_truncate_inode_blocks_enter(inode, from);
+
+- level = get_node_path(from, offset, noffset);
++ level = get_node_path(F2FS_I(inode), from, offset, noffset);
+ restart:
+ page = get_node_page(sbi, inode->i_ino);
+ if (IS_ERR(page)) {
+@@ -695,7 +699,7 @@
+ set_new_dnode(&dn, inode, page, NULL, 0);
+ unlock_page(page);
+
+- rn = page_address(page);
++ rn = F2FS_NODE(page);
+ switch (level) {
+ case 0:
+ case 1:
+@@ -768,6 +772,33 @@
+ return err > 0 ? 0 : err;
+ }
+
++int truncate_xattr_node(struct inode *inode, struct page *page)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
++ nid_t nid = F2FS_I(inode)->i_xattr_nid;
++ struct dnode_of_data dn;
++ struct page *npage;
++
++ if (!nid)
++ return 0;
++
++ npage = get_node_page(sbi, nid);
++ if (IS_ERR(npage))
++ return PTR_ERR(npage);
++
++ F2FS_I(inode)->i_xattr_nid = 0;
++
++ /* need to do checkpoint during fsync */
++ F2FS_I(inode)->xattr_ver = cur_cp_version(F2FS_CKPT(sbi));
++
++ set_new_dnode(&dn, inode, page, npage, nid);
++
++ if (page)
++ dn.inode_page_locked = 1;
++ truncate_node(&dn);
++ return 0;
++}
++
+ /*
+ * Caller should grab and release a mutex by calling mutex_lock_op() and
+ * mutex_unlock_op().
+@@ -778,47 +809,38 @@
+ struct page *page;
+ nid_t ino = inode->i_ino;
+ struct dnode_of_data dn;
++ int err;
+
+ page = get_node_page(sbi, ino);
+ if (IS_ERR(page))
+ return PTR_ERR(page);
+
+- if (F2FS_I(inode)->i_xattr_nid) {
+- nid_t nid = F2FS_I(inode)->i_xattr_nid;
+- struct page *npage = get_node_page(sbi, nid);
+-
+- if (IS_ERR(npage))
+- return PTR_ERR(npage);
+-
+- F2FS_I(inode)->i_xattr_nid = 0;
+- set_new_dnode(&dn, inode, page, npage, nid);
+- dn.inode_page_locked = 1;
+- truncate_node(&dn);
++ err = truncate_xattr_node(inode, page);
++ if (err) {
++ f2fs_put_page(page, 1);
++ return err;
+ }
+
+ /* 0 is possible, after f2fs_new_inode() is failed */
+- BUG_ON(inode->i_blocks != 0 && inode->i_blocks != 1);
++ f2fs_bug_on(inode->i_blocks != 0 && inode->i_blocks != 1);
+ set_new_dnode(&dn, inode, page, page, ino);
+ truncate_node(&dn);
+ return 0;
+ }
+
+-int new_inode_page(struct inode *inode, const struct qstr *name)
++struct page *new_inode_page(struct inode *inode, const struct qstr *name)
+ {
+- struct page *page;
+ struct dnode_of_data dn;
+
+ /* allocate inode page for new inode */
+ set_new_dnode(&dn, inode, NULL, NULL, inode->i_ino);
+- page = new_node_page(&dn, 0);
+- init_dent_inode(name, page);
+- if (IS_ERR(page))
+- return PTR_ERR(page);
+- f2fs_put_page(page, 1);
+- return 0;
++
++ /* caller should f2fs_put_page(page, 1); */
++ return new_node_page(&dn, 0, NULL);
+ }
+
+-struct page *new_node_page(struct dnode_of_data *dn, unsigned int ofs)
++struct page *new_node_page(struct dnode_of_data *dn,
++ unsigned int ofs, struct page *ipage)
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(dn->inode->i_sb);
+ struct address_space *mapping = sbi->node_inode->i_mapping;
+@@ -833,26 +855,32 @@
+ if (!page)
+ return ERR_PTR(-ENOMEM);
+
+- get_node_info(sbi, dn->nid, &old_ni);
++ if (!inc_valid_node_count(sbi, dn->inode, 1)) {
++ err = -ENOSPC;
++ goto fail;
++ }
+
+- SetPageUptodate(page);
+- fill_node_footer(page, dn->nid, dn->inode->i_ino, ofs, true);
++ get_node_info(sbi, dn->nid, &old_ni);
+
+ /* Reinitialize old_ni with new node page */
+- BUG_ON(old_ni.blk_addr != NULL_ADDR);
++ f2fs_bug_on(old_ni.blk_addr != NULL_ADDR);
+ new_ni = old_ni;
+ new_ni.ino = dn->inode->i_ino;
+-
+- if (!inc_valid_node_count(sbi, dn->inode, 1)) {
+- err = -ENOSPC;
+- goto fail;
+- }
+ set_node_addr(sbi, &new_ni, NEW_ADDR);
++
++ fill_node_footer(page, dn->nid, dn->inode->i_ino, ofs, true);
+ set_cold_node(dn->inode, page);
++ SetPageUptodate(page);
++ set_page_dirty(page);
++
++ if (ofs == XATTR_NODE_OFFSET)
++ F2FS_I(dn->inode)->i_xattr_nid = dn->nid;
+
+ dn->node_page = page;
+- sync_inode_page(dn);
+- set_page_dirty(page);
++ if (ipage)
++ update_inode(dn->inode, ipage);
++ else
++ sync_inode_page(dn);
+ if (ofs == 0)
+ inc_valid_inode_count(sbi);
+
+@@ -913,7 +941,6 @@
+ f2fs_put_page(apage, 0);
+ else if (err == LOCKED_PAGE)
+ f2fs_put_page(apage, 1);
+- return;
+ }
+
+ struct page *get_node_page(struct f2fs_sb_info *sbi, pgoff_t nid)
+@@ -942,7 +969,7 @@
+ goto repeat;
+ }
+ got_it:
+- BUG_ON(nid != nid_of_node(page));
++ f2fs_bug_on(nid != nid_of_node(page));
+ mark_page_accessed(page);
+ return page;
+ }
+@@ -1121,6 +1148,47 @@
+ return nwritten;
+ }
+
++int wait_on_node_pages_writeback(struct f2fs_sb_info *sbi, nid_t ino)
++{
++ struct address_space *mapping = sbi->node_inode->i_mapping;
++ pgoff_t index = 0, end = LONG_MAX;
++ struct pagevec pvec;
++ int nr_pages;
++ int ret2 = 0, ret = 0;
++
++ pagevec_init(&pvec, 0);
++ while ((index <= end) &&
++ (nr_pages = pagevec_lookup_tag(&pvec, mapping, &index,
++ PAGECACHE_TAG_WRITEBACK,
++ min(end - index, (pgoff_t)PAGEVEC_SIZE-1) + 1)) != 0) {
++ unsigned i;
++
++ for (i = 0; i < nr_pages; i++) {
++ struct page *page = pvec.pages[i];
++
++ /* until radix tree lookup accepts end_index */
++ if (page->index > end)
++ continue;
++
++ if (ino && ino_of_node(page) == ino) {
++ wait_on_page_writeback(page);
++ if (TestClearPageError(page))
++ ret = -EIO;
++ }
++ }
++ pagevec_release(&pvec);
++ cond_resched();
++ }
++
++ if (test_and_clear_bit(AS_ENOSPC, &mapping->flags))
++ ret2 = -ENOSPC;
++ if (test_and_clear_bit(AS_EIO, &mapping->flags))
++ ret2 = -EIO;
++ if (!ret)
++ ret = ret2;
++ return ret;
++}
++
+ static int f2fs_write_node_page(struct page *page,
+ struct writeback_control *wbc)
+ {
+@@ -1129,11 +1197,14 @@
+ block_t new_addr;
+ struct node_info ni;
+
++ if (sbi->por_doing)
++ goto redirty_out;
++
+ wait_on_page_writeback(page);
+
+ /* get old block addr of this node page */
+ nid = nid_of_node(page);
+- BUG_ON(page->index != nid);
++ f2fs_bug_on(page->index != nid);
+
+ get_node_info(sbi, nid, &ni);
+
+@@ -1144,12 +1215,8 @@
+ return 0;
+ }
+
+- if (wbc->for_reclaim) {
+- dec_page_count(sbi, F2FS_DIRTY_NODES);
+- wbc->pages_skipped++;
+- set_page_dirty(page);
+- return AOP_WRITEPAGE_ACTIVATE;
+- }
++ if (wbc->for_reclaim)
++ goto redirty_out;
+
+ mutex_lock(&sbi->node_write);
+ set_page_writeback(page);
+@@ -1159,34 +1226,38 @@
+ mutex_unlock(&sbi->node_write);
+ unlock_page(page);
+ return 0;
++
++redirty_out:
++ dec_page_count(sbi, F2FS_DIRTY_NODES);
++ wbc->pages_skipped++;
++ set_page_dirty(page);
++ return AOP_WRITEPAGE_ACTIVATE;
+ }
+
+ /*
+ * It is very important to gather dirty pages and write at once, so that we can
+ * submit a big bio without interfering other data writes.
+- * Be default, 512 pages (2MB), a segment size, is quite reasonable.
++ * Be default, 512 pages (2MB) * 3 node types, is more reasonable.
+ */
+-#define COLLECT_DIRTY_NODES 512
++#define COLLECT_DIRTY_NODES 1536
+ static int f2fs_write_node_pages(struct address_space *mapping,
+ struct writeback_control *wbc)
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(mapping->host->i_sb);
+ long nr_to_write = wbc->nr_to_write;
+
+- /* First check balancing cached NAT entries */
+- if (try_to_free_nats(sbi, NAT_ENTRY_PER_BLOCK)) {
+- f2fs_sync_fs(sbi->sb, true);
+- return 0;
+- }
++ /* balancing f2fs's metadata in background */
++ f2fs_balance_fs_bg(sbi);
+
+ /* collect a number of dirty node pages and write together */
+ if (get_pages(sbi, F2FS_DIRTY_NODES) < COLLECT_DIRTY_NODES)
+ return 0;
+
+ /* if mounting is failed, skip writing node pages */
+- wbc->nr_to_write = max_hw_blocks(sbi);
++ wbc->nr_to_write = 3 * max_hw_blocks(sbi);
+ sync_node_pages(sbi, 0, wbc);
+- wbc->nr_to_write = nr_to_write - (max_hw_blocks(sbi) - wbc->nr_to_write);
++ wbc->nr_to_write = nr_to_write - (3 * max_hw_blocks(sbi) -
++ wbc->nr_to_write);
+ return 0;
+ }
+
+@@ -1195,6 +1266,8 @@
+ struct address_space *mapping = page->mapping;
+ struct f2fs_sb_info *sbi = F2FS_SB(mapping->host->i_sb);
+
++ trace_f2fs_set_page_dirty(page, NODE);
++
+ SetPageUptodate(page);
+ if (!PageDirty(page)) {
+ __set_page_dirty_nobuffers(page);
+@@ -1205,7 +1278,8 @@
+ return 0;
+ }
+
+-static void f2fs_invalidate_node_page(struct page *page, unsigned long offset)
++static void f2fs_invalidate_node_page(struct page *page, unsigned int offset,
++ unsigned int length)
+ {
+ struct inode *inode = page->mapping->host;
+ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+@@ -1262,23 +1336,18 @@
+ if (nid == 0)
+ return 0;
+
+- if (!build)
+- goto retry;
+-
+- /* do not add allocated nids */
+- read_lock(&nm_i->nat_tree_lock);
+- ne = __lookup_nat_cache(nm_i, nid);
+- if (ne && nat_get_blkaddr(ne) != NULL_ADDR)
+- allocated = true;
+- read_unlock(&nm_i->nat_tree_lock);
+- if (allocated)
+- return 0;
+-retry:
+- i = kmem_cache_alloc(free_nid_slab, GFP_NOFS);
+- if (!i) {
+- cond_resched();
+- goto retry;
++ if (build) {
++ /* do not add allocated nids */
++ read_lock(&nm_i->nat_tree_lock);
++ ne = __lookup_nat_cache(nm_i, nid);
++ if (ne && nat_get_blkaddr(ne) != NULL_ADDR)
++ allocated = true;
++ read_unlock(&nm_i->nat_tree_lock);
++ if (allocated)
++ return 0;
+ }
++
++ i = f2fs_kmem_cache_alloc(free_nid_slab, GFP_NOFS);
+ i->nid = nid;
+ i->state = NID_NEW;
+
+@@ -1321,7 +1390,7 @@
+ break;
+
+ blk_addr = le32_to_cpu(nat_blk->entries[i].block_addr);
+- BUG_ON(blk_addr == NEW_ADDR);
++ f2fs_bug_on(blk_addr == NEW_ADDR);
+ if (blk_addr == NULL_ADDR) {
+ if (add_free_nid(nm_i, start_nid, true) < 0)
+ break;
+@@ -1392,14 +1461,14 @@
+
+ /* We should not use stale free nids created by build_free_nids */
+ if (nm_i->fcnt && !sbi->on_build_free_nids) {
+- BUG_ON(list_empty(&nm_i->free_nid_list));
++ f2fs_bug_on(list_empty(&nm_i->free_nid_list));
+ list_for_each(this, &nm_i->free_nid_list) {
+ i = list_entry(this, struct free_nid, list);
+ if (i->state == NID_NEW)
+ break;
+ }
+
+- BUG_ON(i->state != NID_NEW);
++ f2fs_bug_on(i->state != NID_NEW);
+ *nid = i->nid;
+ i->state = NID_ALLOC;
+ nm_i->fcnt--;
+@@ -1410,9 +1479,9 @@
+
+ /* Let's scan nat pages and its caches to get free nids */
+ mutex_lock(&nm_i->build_lock);
+- sbi->on_build_free_nids = 1;
++ sbi->on_build_free_nids = true;
+ build_free_nids(sbi);
+- sbi->on_build_free_nids = 0;
++ sbi->on_build_free_nids = false;
+ mutex_unlock(&nm_i->build_lock);
+ goto retry;
+ }
+@@ -1427,7 +1496,7 @@
+
+ spin_lock(&nm_i->free_nid_list_lock);
+ i = __lookup_free_nid_list(nid, &nm_i->free_nid_list);
+- BUG_ON(!i || i->state != NID_ALLOC);
++ f2fs_bug_on(!i || i->state != NID_ALLOC);
+ __del_from_free_nid_list(i);
+ spin_unlock(&nm_i->free_nid_list_lock);
+ }
+@@ -1440,9 +1509,12 @@
+ struct f2fs_nm_info *nm_i = NM_I(sbi);
+ struct free_nid *i;
+
++ if (!nid)
++ return;
++
+ spin_lock(&nm_i->free_nid_list_lock);
+ i = __lookup_free_nid_list(nid, &nm_i->free_nid_list);
+- BUG_ON(!i || i->state != NID_ALLOC);
++ f2fs_bug_on(!i || i->state != NID_ALLOC);
+ if (nm_i->fcnt > 2 * MAX_FREE_NIDS) {
+ __del_from_free_nid_list(i);
+ } else {
+@@ -1480,8 +1552,8 @@
+ SetPageUptodate(ipage);
+ fill_node_footer(ipage, ino, ino, 0, true);
+
+- src = (struct f2fs_node *)page_address(page);
+- dst = (struct f2fs_node *)page_address(ipage);
++ src = F2FS_NODE(page);
++ dst = F2FS_NODE(ipage);
+
+ memcpy(dst, src, (unsigned long)&src->i.i_ext - (unsigned long)&src->i);
+ dst->i.i_size = 0;
+@@ -1492,9 +1564,10 @@
+ new_ni = old_ni;
+ new_ni.ino = ino;
+
++ if (!inc_valid_node_count(sbi, NULL, 1))
++ WARN_ON(1);
+ set_node_addr(sbi, &new_ni, NEW_ADDR);
+ inc_valid_inode_count(sbi);
+-
+ f2fs_put_page(ipage, 1);
+ return 0;
+ }
+@@ -1510,8 +1583,8 @@
+
+ /* alloc temporal page for read node */
+ page = alloc_page(GFP_NOFS | __GFP_ZERO);
+- if (IS_ERR(page))
+- return PTR_ERR(page);
++ if (!page)
++ return -ENOMEM;
+ lock_page(page);
+
+ /* scan the node segment */
+@@ -1530,7 +1603,7 @@
+ goto out;
+
+ lock_page(page);
+- rn = (struct f2fs_node *)page_address(page);
++ rn = F2FS_NODE(page);
+ sum_entry->nid = rn->footer.nid;
+ sum_entry->version = 0;
+ sum_entry->ofs_in_node = 0;
+@@ -1644,7 +1717,7 @@
+ nat_blk = page_address(page);
+ }
+
+- BUG_ON(!nat_blk);
++ f2fs_bug_on(!nat_blk);
+ raw_ne = nat_blk->entries[nid - start_nid];
+ flush_now:
+ new_blkaddr = nat_get_blkaddr(ne);
+@@ -1748,11 +1821,11 @@
+ /* destroy free nid list */
+ spin_lock(&nm_i->free_nid_list_lock);
+ list_for_each_entry_safe(i, next_i, &nm_i->free_nid_list, list) {
+- BUG_ON(i->state == NID_ALLOC);
++ f2fs_bug_on(i->state == NID_ALLOC);
+ __del_from_free_nid_list(i);
+ nm_i->fcnt--;
+ }
+- BUG_ON(nm_i->fcnt);
++ f2fs_bug_on(nm_i->fcnt);
+ spin_unlock(&nm_i->free_nid_list_lock);
+
+ /* destroy nat cache */
+@@ -1766,7 +1839,7 @@
+ __del_from_nat_cache(nm_i, e);
+ }
+ }
+- BUG_ON(nm_i->nat_cnt);
++ f2fs_bug_on(nm_i->nat_cnt);
+ write_unlock(&nm_i->nat_tree_lock);
+
+ kfree(nm_i->nat_bitmap);
+diff -Nur linux-3.10.30.orig/fs/f2fs/node.h linux-linaro-stable-mx6/fs/f2fs/node.h
+--- linux-3.10.30.orig/fs/f2fs/node.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/node.h 2014-05-15 20:34:12.458118041 +0200
+@@ -155,8 +155,7 @@
+ static inline void fill_node_footer(struct page *page, nid_t nid,
+ nid_t ino, unsigned int ofs, bool reset)
+ {
+- void *kaddr = page_address(page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
++ struct f2fs_node *rn = F2FS_NODE(page);
+ if (reset)
+ memset(rn, 0, sizeof(*rn));
+ rn->footer.nid = cpu_to_le32(nid);
+@@ -166,10 +165,8 @@
+
+ static inline void copy_node_footer(struct page *dst, struct page *src)
+ {
+- void *src_addr = page_address(src);
+- void *dst_addr = page_address(dst);
+- struct f2fs_node *src_rn = (struct f2fs_node *)src_addr;
+- struct f2fs_node *dst_rn = (struct f2fs_node *)dst_addr;
++ struct f2fs_node *src_rn = F2FS_NODE(src);
++ struct f2fs_node *dst_rn = F2FS_NODE(dst);
+ memcpy(&dst_rn->footer, &src_rn->footer, sizeof(struct node_footer));
+ }
+
+@@ -177,45 +174,40 @@
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(page->mapping->host->i_sb);
+ struct f2fs_checkpoint *ckpt = F2FS_CKPT(sbi);
+- void *kaddr = page_address(page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
++ struct f2fs_node *rn = F2FS_NODE(page);
++
+ rn->footer.cp_ver = ckpt->checkpoint_ver;
+ rn->footer.next_blkaddr = cpu_to_le32(blkaddr);
+ }
+
+ static inline nid_t ino_of_node(struct page *node_page)
+ {
+- void *kaddr = page_address(node_page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
++ struct f2fs_node *rn = F2FS_NODE(node_page);
+ return le32_to_cpu(rn->footer.ino);
+ }
+
+ static inline nid_t nid_of_node(struct page *node_page)
+ {
+- void *kaddr = page_address(node_page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
++ struct f2fs_node *rn = F2FS_NODE(node_page);
+ return le32_to_cpu(rn->footer.nid);
+ }
+
+ static inline unsigned int ofs_of_node(struct page *node_page)
+ {
+- void *kaddr = page_address(node_page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
++ struct f2fs_node *rn = F2FS_NODE(node_page);
+ unsigned flag = le32_to_cpu(rn->footer.flag);
+ return flag >> OFFSET_BIT_SHIFT;
+ }
+
+ static inline unsigned long long cpver_of_node(struct page *node_page)
+ {
+- void *kaddr = page_address(node_page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
++ struct f2fs_node *rn = F2FS_NODE(node_page);
+ return le64_to_cpu(rn->footer.cp_ver);
+ }
+
+ static inline block_t next_blkaddr_of_node(struct page *node_page)
+ {
+- void *kaddr = page_address(node_page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
++ struct f2fs_node *rn = F2FS_NODE(node_page);
+ return le32_to_cpu(rn->footer.next_blkaddr);
+ }
+
+@@ -237,6 +229,10 @@
+ static inline bool IS_DNODE(struct page *node_page)
+ {
+ unsigned int ofs = ofs_of_node(node_page);
++
++ if (ofs == XATTR_NODE_OFFSET)
++ return false;
++
+ if (ofs == 3 || ofs == 4 + NIDS_PER_BLOCK ||
+ ofs == 5 + 2 * NIDS_PER_BLOCK)
+ return false;
+@@ -250,7 +246,7 @@
+
+ static inline void set_nid(struct page *p, int off, nid_t nid, bool i)
+ {
+- struct f2fs_node *rn = (struct f2fs_node *)page_address(p);
++ struct f2fs_node *rn = F2FS_NODE(p);
+
+ wait_on_page_writeback(p);
+
+@@ -263,7 +259,8 @@
+
+ static inline nid_t get_nid(struct page *p, int off, bool i)
+ {
+- struct f2fs_node *rn = (struct f2fs_node *)page_address(p);
++ struct f2fs_node *rn = F2FS_NODE(p);
++
+ if (i)
+ return le32_to_cpu(rn->i.i_nid[off - NODE_DIR1_BLOCK]);
+ return le32_to_cpu(rn->in.nid[off]);
+@@ -275,25 +272,27 @@
+ * - Mark cold node blocks in their node footer
+ * - Mark cold data pages in page cache
+ */
+-static inline int is_cold_file(struct inode *inode)
++static inline int is_file(struct inode *inode, int type)
+ {
+- return F2FS_I(inode)->i_advise & FADVISE_COLD_BIT;
++ return F2FS_I(inode)->i_advise & type;
+ }
+
+-static inline void set_cold_file(struct inode *inode)
++static inline void set_file(struct inode *inode, int type)
+ {
+- F2FS_I(inode)->i_advise |= FADVISE_COLD_BIT;
++ F2FS_I(inode)->i_advise |= type;
+ }
+
+-static inline int is_cp_file(struct inode *inode)
++static inline void clear_file(struct inode *inode, int type)
+ {
+- return F2FS_I(inode)->i_advise & FADVISE_CP_BIT;
++ F2FS_I(inode)->i_advise &= ~type;
+ }
+
+-static inline void set_cp_file(struct inode *inode)
+-{
+- F2FS_I(inode)->i_advise |= FADVISE_CP_BIT;
+-}
++#define file_is_cold(inode) is_file(inode, FADVISE_COLD_BIT)
++#define file_wrong_pino(inode) is_file(inode, FADVISE_LOST_PINO_BIT)
++#define file_set_cold(inode) set_file(inode, FADVISE_COLD_BIT)
++#define file_lost_pino(inode) set_file(inode, FADVISE_LOST_PINO_BIT)
++#define file_clear_cold(inode) clear_file(inode, FADVISE_COLD_BIT)
++#define file_got_pino(inode) clear_file(inode, FADVISE_LOST_PINO_BIT)
+
+ static inline int is_cold_data(struct page *page)
+ {
+@@ -310,33 +309,19 @@
+ ClearPageChecked(page);
+ }
+
+-static inline int is_cold_node(struct page *page)
+-{
+- void *kaddr = page_address(page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
+- unsigned int flag = le32_to_cpu(rn->footer.flag);
+- return flag & (0x1 << COLD_BIT_SHIFT);
+-}
+-
+-static inline unsigned char is_fsync_dnode(struct page *page)
++static inline int is_node(struct page *page, int type)
+ {
+- void *kaddr = page_address(page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
+- unsigned int flag = le32_to_cpu(rn->footer.flag);
+- return flag & (0x1 << FSYNC_BIT_SHIFT);
++ struct f2fs_node *rn = F2FS_NODE(page);
++ return le32_to_cpu(rn->footer.flag) & (1 << type);
+ }
+
+-static inline unsigned char is_dent_dnode(struct page *page)
+-{
+- void *kaddr = page_address(page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
+- unsigned int flag = le32_to_cpu(rn->footer.flag);
+- return flag & (0x1 << DENT_BIT_SHIFT);
+-}
++#define is_cold_node(page) is_node(page, COLD_BIT_SHIFT)
++#define is_fsync_dnode(page) is_node(page, FSYNC_BIT_SHIFT)
++#define is_dent_dnode(page) is_node(page, DENT_BIT_SHIFT)
+
+ static inline void set_cold_node(struct inode *inode, struct page *page)
+ {
+- struct f2fs_node *rn = (struct f2fs_node *)page_address(page);
++ struct f2fs_node *rn = F2FS_NODE(page);
+ unsigned int flag = le32_to_cpu(rn->footer.flag);
+
+ if (S_ISDIR(inode->i_mode))
+@@ -346,26 +331,15 @@
+ rn->footer.flag = cpu_to_le32(flag);
+ }
+
+-static inline void set_fsync_mark(struct page *page, int mark)
+-{
+- void *kaddr = page_address(page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
+- unsigned int flag = le32_to_cpu(rn->footer.flag);
+- if (mark)
+- flag |= (0x1 << FSYNC_BIT_SHIFT);
+- else
+- flag &= ~(0x1 << FSYNC_BIT_SHIFT);
+- rn->footer.flag = cpu_to_le32(flag);
+-}
+-
+-static inline void set_dentry_mark(struct page *page, int mark)
++static inline void set_mark(struct page *page, int mark, int type)
+ {
+- void *kaddr = page_address(page);
+- struct f2fs_node *rn = (struct f2fs_node *)kaddr;
++ struct f2fs_node *rn = F2FS_NODE(page);
+ unsigned int flag = le32_to_cpu(rn->footer.flag);
+ if (mark)
+- flag |= (0x1 << DENT_BIT_SHIFT);
++ flag |= (0x1 << type);
+ else
+- flag &= ~(0x1 << DENT_BIT_SHIFT);
++ flag &= ~(0x1 << type);
+ rn->footer.flag = cpu_to_le32(flag);
+ }
++#define set_dentry_mark(page, mark) set_mark(page, mark, DENT_BIT_SHIFT)
++#define set_fsync_mark(page, mark) set_mark(page, mark, FSYNC_BIT_SHIFT)
+diff -Nur linux-3.10.30.orig/fs/f2fs/recovery.c linux-linaro-stable-mx6/fs/f2fs/recovery.c
+--- linux-3.10.30.orig/fs/f2fs/recovery.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/recovery.c 2014-05-15 20:34:12.458118041 +0200
+@@ -40,45 +40,71 @@
+
+ static int recover_dentry(struct page *ipage, struct inode *inode)
+ {
+- struct f2fs_node *raw_node = (struct f2fs_node *)kmap(ipage);
++ struct f2fs_node *raw_node = F2FS_NODE(ipage);
+ struct f2fs_inode *raw_inode = &(raw_node->i);
+- struct qstr name;
++ nid_t pino = le32_to_cpu(raw_inode->i_pino);
+ struct f2fs_dir_entry *de;
++ struct qstr name;
+ struct page *page;
+- struct inode *dir;
++ struct inode *dir, *einode;
+ int err = 0;
+
+- if (!is_dent_dnode(ipage))
+- goto out;
+-
+- dir = f2fs_iget(inode->i_sb, le32_to_cpu(raw_inode->i_pino));
+- if (IS_ERR(dir)) {
+- err = PTR_ERR(dir);
+- goto out;
++ dir = check_dirty_dir_inode(F2FS_SB(inode->i_sb), pino);
++ if (!dir) {
++ dir = f2fs_iget(inode->i_sb, pino);
++ if (IS_ERR(dir)) {
++ err = PTR_ERR(dir);
++ goto out;
++ }
++ set_inode_flag(F2FS_I(dir), FI_DELAY_IPUT);
++ add_dirty_dir_inode(dir);
+ }
+
+ name.len = le32_to_cpu(raw_inode->i_namelen);
+ name.name = raw_inode->i_name;
+-
++retry:
+ de = f2fs_find_entry(dir, &name, &page);
++ if (de && inode->i_ino == le32_to_cpu(de->ino))
++ goto out_unmap_put;
+ if (de) {
+- kunmap(page);
+- f2fs_put_page(page, 0);
+- } else {
+- err = __f2fs_add_link(dir, &name, inode);
++ einode = f2fs_iget(inode->i_sb, le32_to_cpu(de->ino));
++ if (IS_ERR(einode)) {
++ WARN_ON(1);
++ if (PTR_ERR(einode) == -ENOENT)
++ err = -EEXIST;
++ goto out_unmap_put;
++ }
++ err = acquire_orphan_inode(F2FS_SB(inode->i_sb));
++ if (err) {
++ iput(einode);
++ goto out_unmap_put;
++ }
++ f2fs_delete_entry(de, page, einode);
++ iput(einode);
++ goto retry;
+ }
+- iput(dir);
++ err = __f2fs_add_link(dir, &name, inode);
++ goto out;
++
++out_unmap_put:
++ kunmap(page);
++ f2fs_put_page(page, 0);
+ out:
+- kunmap(ipage);
++ f2fs_msg(inode->i_sb, KERN_NOTICE, "recover_inode and its dentry: "
++ "ino = %x, name = %s, dir = %lx, err = %d",
++ ino_of_node(ipage), raw_inode->i_name,
++ IS_ERR(dir) ? 0 : dir->i_ino, err);
+ return err;
+ }
+
+ static int recover_inode(struct inode *inode, struct page *node_page)
+ {
+- void *kaddr = page_address(node_page);
+- struct f2fs_node *raw_node = (struct f2fs_node *)kaddr;
++ struct f2fs_node *raw_node = F2FS_NODE(node_page);
+ struct f2fs_inode *raw_inode = &(raw_node->i);
+
++ if (!IS_INODE(node_page))
++ return 0;
++
+ inode->i_mode = le16_to_cpu(raw_inode->i_mode);
+ i_size_write(inode, le64_to_cpu(raw_inode->i_size));
+ inode->i_atime.tv_sec = le64_to_cpu(raw_inode->i_mtime);
+@@ -88,12 +114,17 @@
+ inode->i_ctime.tv_nsec = le32_to_cpu(raw_inode->i_ctime_nsec);
+ inode->i_mtime.tv_nsec = le32_to_cpu(raw_inode->i_mtime_nsec);
+
+- return recover_dentry(node_page, inode);
++ if (is_dent_dnode(node_page))
++ return recover_dentry(node_page, inode);
++
++ f2fs_msg(inode->i_sb, KERN_NOTICE, "recover_inode: ino = %x, name = %s",
++ ino_of_node(node_page), raw_inode->i_name);
++ return 0;
+ }
+
+ static int find_fsync_dnodes(struct f2fs_sb_info *sbi, struct list_head *head)
+ {
+- unsigned long long cp_ver = le64_to_cpu(sbi->ckpt->checkpoint_ver);
++ unsigned long long cp_ver = cur_cp_version(F2FS_CKPT(sbi));
+ struct curseg_info *curseg;
+ struct page *page;
+ block_t blkaddr;
+@@ -105,8 +136,8 @@
+
+ /* read node page */
+ page = alloc_page(GFP_F2FS_ZERO);
+- if (IS_ERR(page))
+- return PTR_ERR(page);
++ if (!page)
++ return -ENOMEM;
+ lock_page(page);
+
+ while (1) {
+@@ -119,14 +150,13 @@
+ lock_page(page);
+
+ if (cp_ver != cpver_of_node(page))
+- goto unlock_out;
++ break;
+
+ if (!is_fsync_dnode(page))
+ goto next;
+
+ entry = get_fsync_inode(head, ino_of_node(page));
+ if (entry) {
+- entry->blkaddr = blkaddr;
+ if (IS_INODE(page) && is_dent_dnode(page))
+ set_inode_flag(F2FS_I(entry->inode),
+ FI_INC_LINK);
+@@ -134,48 +164,40 @@
+ if (IS_INODE(page) && is_dent_dnode(page)) {
+ err = recover_inode_page(sbi, page);
+ if (err)
+- goto unlock_out;
++ break;
+ }
+
+ /* add this fsync inode to the list */
+ entry = kmem_cache_alloc(fsync_entry_slab, GFP_NOFS);
+ if (!entry) {
+ err = -ENOMEM;
+- goto unlock_out;
++ break;
+ }
+
+ entry->inode = f2fs_iget(sbi->sb, ino_of_node(page));
+ if (IS_ERR(entry->inode)) {
+ err = PTR_ERR(entry->inode);
+ kmem_cache_free(fsync_entry_slab, entry);
+- goto unlock_out;
++ break;
+ }
+-
+ list_add_tail(&entry->list, head);
+- entry->blkaddr = blkaddr;
+- }
+- if (IS_INODE(page)) {
+- err = recover_inode(entry->inode, page);
+- if (err == -ENOENT) {
+- goto next;
+- } else if (err) {
+- err = -EINVAL;
+- goto unlock_out;
+- }
+ }
++ entry->blkaddr = blkaddr;
++
++ err = recover_inode(entry->inode, page);
++ if (err && err != -ENOENT)
++ break;
+ next:
+ /* check next segment */
+ blkaddr = next_blkaddr_of_node(page);
+ }
+-unlock_out:
+ unlock_page(page);
+ out:
+ __free_pages(page, 0);
+ return err;
+ }
+
+-static void destroy_fsync_dnodes(struct f2fs_sb_info *sbi,
+- struct list_head *head)
++static void destroy_fsync_dnodes(struct list_head *head)
+ {
+ struct fsync_inode_entry *entry, *tmp;
+
+@@ -186,24 +208,25 @@
+ }
+ }
+
+-static void check_index_in_prev_nodes(struct f2fs_sb_info *sbi,
+- block_t blkaddr)
++static int check_index_in_prev_nodes(struct f2fs_sb_info *sbi,
++ block_t blkaddr, struct dnode_of_data *dn)
+ {
+ struct seg_entry *sentry;
+ unsigned int segno = GET_SEGNO(sbi, blkaddr);
+ unsigned short blkoff = GET_SEGOFF_FROM_SEG0(sbi, blkaddr) &
+ (sbi->blocks_per_seg - 1);
+ struct f2fs_summary sum;
+- nid_t ino;
++ nid_t ino, nid;
+ void *kaddr;
+ struct inode *inode;
+ struct page *node_page;
++ unsigned int offset;
+ block_t bidx;
+ int i;
+
+ sentry = get_seg_entry(sbi, segno);
+ if (!f2fs_test_bit(blkoff, sentry->cur_valid_map))
+- return;
++ return 0;
+
+ /* Get the previous summary */
+ for (i = CURSEG_WARM_DATA; i <= CURSEG_COLD_DATA; i++) {
+@@ -222,52 +245,74 @@
+ f2fs_put_page(sum_page, 1);
+ }
+
++ /* Use the locked dnode page and inode */
++ nid = le32_to_cpu(sum.nid);
++ if (dn->inode->i_ino == nid) {
++ struct dnode_of_data tdn = *dn;
++ tdn.nid = nid;
++ tdn.node_page = dn->inode_page;
++ tdn.ofs_in_node = le16_to_cpu(sum.ofs_in_node);
++ truncate_data_blocks_range(&tdn, 1);
++ return 0;
++ } else if (dn->nid == nid) {
++ struct dnode_of_data tdn = *dn;
++ tdn.ofs_in_node = le16_to_cpu(sum.ofs_in_node);
++ truncate_data_blocks_range(&tdn, 1);
++ return 0;
++ }
++
+ /* Get the node page */
+- node_page = get_node_page(sbi, le32_to_cpu(sum.nid));
+- bidx = start_bidx_of_node(ofs_of_node(node_page)) +
+- le16_to_cpu(sum.ofs_in_node);
++ node_page = get_node_page(sbi, nid);
++ if (IS_ERR(node_page))
++ return PTR_ERR(node_page);
++
++ offset = ofs_of_node(node_page);
+ ino = ino_of_node(node_page);
+ f2fs_put_page(node_page, 1);
+
+ /* Deallocate previous index in the node page */
+ inode = f2fs_iget(sbi->sb, ino);
+ if (IS_ERR(inode))
+- return;
++ return PTR_ERR(inode);
++
++ bidx = start_bidx_of_node(offset, F2FS_I(inode)) +
++ le16_to_cpu(sum.ofs_in_node);
+
+ truncate_hole(inode, bidx, bidx + 1);
+ iput(inode);
++ return 0;
+ }
+
+ static int do_recover_data(struct f2fs_sb_info *sbi, struct inode *inode,
+ struct page *page, block_t blkaddr)
+ {
++ struct f2fs_inode_info *fi = F2FS_I(inode);
+ unsigned int start, end;
+ struct dnode_of_data dn;
+ struct f2fs_summary sum;
+ struct node_info ni;
+- int err = 0;
+- int ilock;
++ int err = 0, recovered = 0;
+
+- start = start_bidx_of_node(ofs_of_node(page));
++ start = start_bidx_of_node(ofs_of_node(page), fi);
+ if (IS_INODE(page))
+- end = start + ADDRS_PER_INODE;
++ end = start + ADDRS_PER_INODE(fi);
+ else
+ end = start + ADDRS_PER_BLOCK;
+
+- ilock = mutex_lock_op(sbi);
++ f2fs_lock_op(sbi);
+ set_new_dnode(&dn, inode, NULL, NULL, 0);
+
+ err = get_dnode_of_data(&dn, start, ALLOC_NODE);
+ if (err) {
+- mutex_unlock_op(sbi, ilock);
++ f2fs_unlock_op(sbi);
+ return err;
+ }
+
+ wait_on_page_writeback(dn.node_page);
+
+ get_node_info(sbi, dn.nid, &ni);
+- BUG_ON(ni.ino != ino_of_node(page));
+- BUG_ON(ofs_of_node(dn.node_page) != ofs_of_node(page));
++ f2fs_bug_on(ni.ino != ino_of_node(page));
++ f2fs_bug_on(ofs_of_node(dn.node_page) != ofs_of_node(page));
+
+ for (; start < end; start++) {
+ block_t src, dest;
+@@ -277,19 +322,22 @@
+
+ if (src != dest && dest != NEW_ADDR && dest != NULL_ADDR) {
+ if (src == NULL_ADDR) {
+- int err = reserve_new_block(&dn);
++ err = reserve_new_block(&dn);
+ /* We should not get -ENOSPC */
+- BUG_ON(err);
++ f2fs_bug_on(err);
+ }
+
+ /* Check the previous node page having this index */
+- check_index_in_prev_nodes(sbi, dest);
++ err = check_index_in_prev_nodes(sbi, dest, &dn);
++ if (err)
++ goto err;
+
+ set_summary(&sum, dn.nid, dn.ofs_in_node, ni.version);
+
+ /* write dummy data page */
+ recover_data_page(sbi, NULL, &sum, src, dest);
+ update_extent_cache(dest, &dn);
++ recovered++;
+ }
+ dn.ofs_in_node++;
+ }
+@@ -305,15 +353,20 @@
+ set_page_dirty(dn.node_page);
+
+ recover_node_page(sbi, dn.node_page, &sum, &ni, blkaddr);
++err:
+ f2fs_put_dnode(&dn);
+- mutex_unlock_op(sbi, ilock);
+- return 0;
++ f2fs_unlock_op(sbi);
++
++ f2fs_msg(sbi->sb, KERN_NOTICE, "recover_data: ino = %lx, "
++ "recovered_data = %d blocks, err = %d",
++ inode->i_ino, recovered, err);
++ return err;
+ }
+
+ static int recover_data(struct f2fs_sb_info *sbi,
+ struct list_head *head, int type)
+ {
+- unsigned long long cp_ver = le64_to_cpu(sbi->ckpt->checkpoint_ver);
++ unsigned long long cp_ver = cur_cp_version(F2FS_CKPT(sbi));
+ struct curseg_info *curseg;
+ struct page *page;
+ int err = 0;
+@@ -325,7 +378,7 @@
+
+ /* read node page */
+ page = alloc_page(GFP_NOFS | __GFP_ZERO);
+- if (IS_ERR(page))
++ if (!page)
+ return -ENOMEM;
+
+ lock_page(page);
+@@ -340,7 +393,7 @@
+ lock_page(page);
+
+ if (cp_ver != cpver_of_node(page))
+- goto unlock_out;
++ break;
+
+ entry = get_fsync_inode(head, ino_of_node(page));
+ if (!entry)
+@@ -348,7 +401,7 @@
+
+ err = do_recover_data(sbi, entry->inode, page, blkaddr);
+ if (err)
+- goto out;
++ break;
+
+ if (entry->blkaddr == blkaddr) {
+ iput(entry->inode);
+@@ -359,7 +412,6 @@
+ /* check next segment */
+ blkaddr = next_blkaddr_of_node(page);
+ }
+-unlock_out:
+ unlock_page(page);
+ out:
+ __free_pages(page, 0);
+@@ -373,6 +425,7 @@
+ {
+ struct list_head inode_list;
+ int err;
++ bool need_writecp = false;
+
+ fsync_entry_slab = f2fs_kmem_cache_create("f2fs_fsync_inode_entry",
+ sizeof(struct fsync_inode_entry), NULL);
+@@ -382,6 +435,7 @@
+ INIT_LIST_HEAD(&inode_list);
+
+ /* step #1: find fsynced inode numbers */
++ sbi->por_doing = true;
+ err = find_fsync_dnodes(sbi, &inode_list);
+ if (err)
+ goto out;
+@@ -389,14 +443,16 @@
+ if (list_empty(&inode_list))
+ goto out;
+
++ need_writecp = true;
++
+ /* step #2: recover data */
+- sbi->por_doing = 1;
+ err = recover_data(sbi, &inode_list, CURSEG_WARM_NODE);
+- sbi->por_doing = 0;
+- BUG_ON(!list_empty(&inode_list));
++ f2fs_bug_on(!list_empty(&inode_list));
+ out:
+- destroy_fsync_dnodes(sbi, &inode_list);
++ destroy_fsync_dnodes(&inode_list);
+ kmem_cache_destroy(fsync_entry_slab);
+- write_checkpoint(sbi, false);
++ sbi->por_doing = false;
++ if (!err && need_writecp)
++ write_checkpoint(sbi, false);
+ return err;
+ }
+diff -Nur linux-3.10.30.orig/fs/f2fs/segment.c linux-linaro-stable-mx6/fs/f2fs/segment.c
+--- linux-3.10.30.orig/fs/f2fs/segment.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/segment.c 2014-05-15 20:34:12.458118041 +0200
+@@ -36,6 +36,14 @@
+ }
+ }
+
++void f2fs_balance_fs_bg(struct f2fs_sb_info *sbi)
++{
++ /* check the # of cached NAT entries and prefree segments */
++ if (try_to_free_nats(sbi, NAT_ENTRY_PER_BLOCK) ||
++ excess_prefree_segs(sbi))
++ f2fs_sync_fs(sbi->sb, true);
++}
++
+ static void __locate_dirty_segment(struct f2fs_sb_info *sbi, unsigned int segno,
+ enum dirty_type dirty_type)
+ {
+@@ -50,20 +58,10 @@
+
+ if (dirty_type == DIRTY) {
+ struct seg_entry *sentry = get_seg_entry(sbi, segno);
+- enum dirty_type t = DIRTY_HOT_DATA;
+-
+- dirty_type = sentry->type;
+-
+- if (!test_and_set_bit(segno, dirty_i->dirty_segmap[dirty_type]))
+- dirty_i->nr_dirty[dirty_type]++;
++ enum dirty_type t = sentry->type;
+
+- /* Only one bitmap should be set */
+- for (; t <= DIRTY_COLD_NODE; t++) {
+- if (t == dirty_type)
+- continue;
+- if (test_and_clear_bit(segno, dirty_i->dirty_segmap[t]))
+- dirty_i->nr_dirty[t]--;
+- }
++ if (!test_and_set_bit(segno, dirty_i->dirty_segmap[t]))
++ dirty_i->nr_dirty[t]++;
+ }
+ }
+
+@@ -76,12 +74,11 @@
+ dirty_i->nr_dirty[dirty_type]--;
+
+ if (dirty_type == DIRTY) {
+- enum dirty_type t = DIRTY_HOT_DATA;
++ struct seg_entry *sentry = get_seg_entry(sbi, segno);
++ enum dirty_type t = sentry->type;
+
+- /* clear all the bitmaps */
+- for (; t <= DIRTY_COLD_NODE; t++)
+- if (test_and_clear_bit(segno, dirty_i->dirty_segmap[t]))
+- dirty_i->nr_dirty[t]--;
++ if (test_and_clear_bit(segno, dirty_i->dirty_segmap[t]))
++ dirty_i->nr_dirty[t]--;
+
+ if (get_valid_blocks(sbi, segno, sbi->segs_per_sec) == 0)
+ clear_bit(GET_SECNO(sbi, segno),
+@@ -94,7 +91,7 @@
+ * Adding dirty entry into seglist is not critical operation.
+ * If a given segment is one of current working segments, it won't be added.
+ */
+-void locate_dirty_segment(struct f2fs_sb_info *sbi, unsigned int segno)
++static void locate_dirty_segment(struct f2fs_sb_info *sbi, unsigned int segno)
+ {
+ struct dirty_seglist_info *dirty_i = DIRTY_I(sbi);
+ unsigned short valid_blocks;
+@@ -117,7 +114,6 @@
+ }
+
+ mutex_unlock(&dirty_i->seglist_lock);
+- return;
+ }
+
+ /*
+@@ -126,17 +122,16 @@
+ static void set_prefree_as_free_segments(struct f2fs_sb_info *sbi)
+ {
+ struct dirty_seglist_info *dirty_i = DIRTY_I(sbi);
+- unsigned int segno, offset = 0;
++ unsigned int segno = -1;
+ unsigned int total_segs = TOTAL_SEGS(sbi);
+
+ mutex_lock(&dirty_i->seglist_lock);
+ while (1) {
+ segno = find_next_bit(dirty_i->dirty_segmap[PRE], total_segs,
+- offset);
++ segno + 1);
+ if (segno >= total_segs)
+ break;
+ __set_test_and_free(sbi, segno);
+- offset = segno + 1;
+ }
+ mutex_unlock(&dirty_i->seglist_lock);
+ }
+@@ -144,28 +139,33 @@
+ void clear_prefree_segments(struct f2fs_sb_info *sbi)
+ {
+ struct dirty_seglist_info *dirty_i = DIRTY_I(sbi);
+- unsigned int segno, offset = 0;
++ unsigned long *prefree_map = dirty_i->dirty_segmap[PRE];
+ unsigned int total_segs = TOTAL_SEGS(sbi);
++ unsigned int start = 0, end = -1;
+
+ mutex_lock(&dirty_i->seglist_lock);
++
+ while (1) {
+- segno = find_next_bit(dirty_i->dirty_segmap[PRE], total_segs,
+- offset);
+- if (segno >= total_segs)
++ int i;
++ start = find_next_bit(prefree_map, total_segs, end + 1);
++ if (start >= total_segs)
+ break;
++ end = find_next_zero_bit(prefree_map, total_segs, start + 1);
+
+- offset = segno + 1;
+- if (test_and_clear_bit(segno, dirty_i->dirty_segmap[PRE]))
+- dirty_i->nr_dirty[PRE]--;
++ for (i = start; i < end; i++)
++ clear_bit(i, prefree_map);
++
++ dirty_i->nr_dirty[PRE] -= end - start;
++
++ if (!test_opt(sbi, DISCARD))
++ continue;
+
+- /* Let's use trim */
+- if (test_opt(sbi, DISCARD))
+- blkdev_issue_discard(sbi->sb->s_bdev,
+- START_BLOCK(sbi, segno) <<
+- sbi->log_sectors_per_block,
+- 1 << (sbi->log_sectors_per_block +
+- sbi->log_blocks_per_seg),
+- GFP_NOFS, 0);
++ blkdev_issue_discard(sbi->sb->s_bdev,
++ START_BLOCK(sbi, start) <<
++ sbi->log_sectors_per_block,
++ (1 << (sbi->log_sectors_per_block +
++ sbi->log_blocks_per_seg)) * (end - start),
++ GFP_NOFS, 0);
+ }
+ mutex_unlock(&dirty_i->seglist_lock);
+ }
+@@ -198,7 +198,7 @@
+ new_vblocks = se->valid_blocks + del;
+ offset = GET_SEGOFF_FROM_SEG0(sbi, blkaddr) & (sbi->blocks_per_seg - 1);
+
+- BUG_ON((new_vblocks >> (sizeof(unsigned short) << 3) ||
++ f2fs_bug_on((new_vblocks >> (sizeof(unsigned short) << 3) ||
+ (new_vblocks > sbi->blocks_per_seg)));
+
+ se->valid_blocks = new_vblocks;
+@@ -238,7 +238,7 @@
+ unsigned int segno = GET_SEGNO(sbi, addr);
+ struct sit_info *sit_i = SIT_I(sbi);
+
+- BUG_ON(addr == NULL_ADDR);
++ f2fs_bug_on(addr == NULL_ADDR);
+ if (addr == NEW_ADDR)
+ return;
+
+@@ -257,13 +257,12 @@
+ * This function should be resided under the curseg_mutex lock
+ */
+ static void __add_sum_entry(struct f2fs_sb_info *sbi, int type,
+- struct f2fs_summary *sum, unsigned short offset)
++ struct f2fs_summary *sum)
+ {
+ struct curseg_info *curseg = CURSEG_I(sbi, type);
+ void *addr = curseg->sum_blk;
+- addr += offset * sizeof(struct f2fs_summary);
++ addr += curseg->next_blkoff * sizeof(struct f2fs_summary);
+ memcpy(addr, sum, sizeof(struct f2fs_summary));
+- return;
+ }
+
+ /*
+@@ -271,9 +270,8 @@
+ */
+ int npages_for_summary_flush(struct f2fs_sb_info *sbi)
+ {
+- int total_size_bytes = 0;
+ int valid_sum_count = 0;
+- int i, sum_space;
++ int i, sum_in_page;
+
+ for (i = CURSEG_HOT_DATA; i <= CURSEG_COLD_DATA; i++) {
+ if (sbi->ckpt->alloc_type[i] == SSR)
+@@ -282,13 +280,12 @@
+ valid_sum_count += curseg_blkoff(sbi, i);
+ }
+
+- total_size_bytes = valid_sum_count * (SUMMARY_SIZE + 1)
+- + sizeof(struct nat_journal) + 2
+- + sizeof(struct sit_journal) + 2;
+- sum_space = PAGE_CACHE_SIZE - SUM_FOOTER_SIZE;
+- if (total_size_bytes < sum_space)
++ sum_in_page = (PAGE_CACHE_SIZE - 2 * SUM_JOURNAL_SIZE -
++ SUM_FOOTER_SIZE) / SUMMARY_SIZE;
++ if (valid_sum_count <= sum_in_page)
+ return 1;
+- else if (total_size_bytes < 2 * sum_space)
++ else if ((valid_sum_count - sum_in_page) <=
++ (PAGE_CACHE_SIZE - SUM_FOOTER_SIZE) / SUMMARY_SIZE)
+ return 2;
+ return 3;
+ }
+@@ -311,64 +308,14 @@
+ f2fs_put_page(page, 1);
+ }
+
+-static unsigned int check_prefree_segments(struct f2fs_sb_info *sbi, int type)
+-{
+- struct dirty_seglist_info *dirty_i = DIRTY_I(sbi);
+- unsigned long *prefree_segmap = dirty_i->dirty_segmap[PRE];
+- unsigned int segno;
+- unsigned int ofs = 0;
+-
+- /*
+- * If there is not enough reserved sections,
+- * we should not reuse prefree segments.
+- */
+- if (has_not_enough_free_secs(sbi, 0))
+- return NULL_SEGNO;
+-
+- /*
+- * NODE page should not reuse prefree segment,
+- * since those information is used for SPOR.
+- */
+- if (IS_NODESEG(type))
+- return NULL_SEGNO;
+-next:
+- segno = find_next_bit(prefree_segmap, TOTAL_SEGS(sbi), ofs);
+- ofs += sbi->segs_per_sec;
+-
+- if (segno < TOTAL_SEGS(sbi)) {
+- int i;
+-
+- /* skip intermediate segments in a section */
+- if (segno % sbi->segs_per_sec)
+- goto next;
+-
+- /* skip if the section is currently used */
+- if (sec_usage_check(sbi, GET_SECNO(sbi, segno)))
+- goto next;
+-
+- /* skip if whole section is not prefree */
+- for (i = 1; i < sbi->segs_per_sec; i++)
+- if (!test_bit(segno + i, prefree_segmap))
+- goto next;
+-
+- /* skip if whole section was not free at the last checkpoint */
+- for (i = 0; i < sbi->segs_per_sec; i++)
+- if (get_seg_entry(sbi, segno + i)->ckpt_valid_blocks)
+- goto next;
+-
+- return segno;
+- }
+- return NULL_SEGNO;
+-}
+-
+ static int is_next_segment_free(struct f2fs_sb_info *sbi, int type)
+ {
+ struct curseg_info *curseg = CURSEG_I(sbi, type);
+- unsigned int segno = curseg->segno;
++ unsigned int segno = curseg->segno + 1;
+ struct free_segmap_info *free_i = FREE_I(sbi);
+
+- if (segno + 1 < TOTAL_SEGS(sbi) && (segno + 1) % sbi->segs_per_sec)
+- return !test_bit(segno + 1, free_i->free_segmap);
++ if (segno < TOTAL_SEGS(sbi) && segno % sbi->segs_per_sec)
++ return !test_bit(segno, free_i->free_segmap);
+ return 0;
+ }
+
+@@ -404,7 +351,7 @@
+ if (dir == ALLOC_RIGHT) {
+ secno = find_next_zero_bit(free_i->free_secmap,
+ TOTAL_SECS(sbi), 0);
+- BUG_ON(secno >= TOTAL_SECS(sbi));
++ f2fs_bug_on(secno >= TOTAL_SECS(sbi));
+ } else {
+ go_left = 1;
+ left_start = hint - 1;
+@@ -420,7 +367,7 @@
+ }
+ left_start = find_next_zero_bit(free_i->free_secmap,
+ TOTAL_SECS(sbi), 0);
+- BUG_ON(left_start >= TOTAL_SECS(sbi));
++ f2fs_bug_on(left_start >= TOTAL_SECS(sbi));
+ break;
+ }
+ secno = left_start;
+@@ -459,7 +406,7 @@
+ }
+ got_it:
+ /* set it as dirty segment in free segmap */
+- BUG_ON(test_bit(segno, free_i->free_segmap));
++ f2fs_bug_on(test_bit(segno, free_i->free_segmap));
+ __set_inuse(sbi, segno);
+ *newseg = segno;
+ write_unlock(&free_i->segmap_lock);
+@@ -495,7 +442,7 @@
+ int dir = ALLOC_LEFT;
+
+ write_sum_page(sbi, curseg->sum_blk,
+- GET_SUM_BLOCK(sbi, curseg->segno));
++ GET_SUM_BLOCK(sbi, segno));
+ if (type == CURSEG_WARM_DATA || type == CURSEG_COLD_DATA)
+ dir = ALLOC_RIGHT;
+
+@@ -594,15 +541,8 @@
+ {
+ struct curseg_info *curseg = CURSEG_I(sbi, type);
+
+- if (force) {
++ if (force)
+ new_curseg(sbi, type, true);
+- goto out;
+- }
+-
+- curseg->next_segno = check_prefree_segments(sbi, type);
+-
+- if (curseg->next_segno != NULL_SEGNO)
+- change_curseg(sbi, type, false);
+ else if (type == CURSEG_WARM_NODE)
+ new_curseg(sbi, type, false);
+ else if (curseg->alloc_type == LFS && is_next_segment_free(sbi, type))
+@@ -611,8 +551,8 @@
+ change_curseg(sbi, type, true);
+ else
+ new_curseg(sbi, type, false);
+-out:
+- sbi->segment_count[curseg->alloc_type]++;
++
++ stat_inc_seg_type(sbi, curseg);
+ }
+
+ void allocate_new_segments(struct f2fs_sb_info *sbi)
+@@ -657,6 +597,11 @@
+
+ if (p->is_sync)
+ complete(p->wait);
++
++ if (!get_pages(p->sbi, F2FS_WRITEBACK) &&
++ !list_empty(&p->sbi->cp_wait.task_list))
++ wake_up(&p->sbi->cp_wait);
++
+ kfree(p);
+ bio_put(bio);
+ }
+@@ -664,18 +609,12 @@
+ struct bio *f2fs_bio_alloc(struct block_device *bdev, int npages)
+ {
+ struct bio *bio;
+- struct bio_private *priv;
+-retry:
+- priv = kmalloc(sizeof(struct bio_private), GFP_NOFS);
+- if (!priv) {
+- cond_resched();
+- goto retry;
+- }
+
+ /* No failure on bio allocation */
+ bio = bio_alloc(GFP_NOIO, npages);
+ bio->bi_bdev = bdev;
+- bio->bi_private = priv;
++ bio->bi_private = NULL;
++
+ return bio;
+ }
+
+@@ -723,6 +662,7 @@
+ block_t blk_addr, enum page_type type)
+ {
+ struct block_device *bdev = sbi->sb->s_bdev;
++ int bio_blocks;
+
+ verify_block_addr(sbi, blk_addr);
+
+@@ -734,8 +674,18 @@
+ do_submit_bio(sbi, type, false);
+ alloc_new:
+ if (sbi->bio[type] == NULL) {
+- sbi->bio[type] = f2fs_bio_alloc(bdev, max_hw_blocks(sbi));
++ struct bio_private *priv;
++retry:
++ priv = kmalloc(sizeof(struct bio_private), GFP_NOFS);
++ if (!priv) {
++ cond_resched();
++ goto retry;
++ }
++
++ bio_blocks = MAX_BIO_BLOCKS(max_hw_blocks(sbi));
++ sbi->bio[type] = f2fs_bio_alloc(bdev, bio_blocks);
+ sbi->bio[type]->bi_sector = SECTOR_FROM_BLOCK(sbi, blk_addr);
++ sbi->bio[type]->bi_private = priv;
+ /*
+ * The end_io will be assigned at the sumbission phase.
+ * Until then, let bio_add_page() merge consecutive IOs as much
+@@ -755,6 +705,16 @@
+ trace_f2fs_submit_write_page(page, blk_addr, type);
+ }
+
++void f2fs_wait_on_page_writeback(struct page *page,
++ enum page_type type, bool sync)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(page->mapping->host->i_sb);
++ if (PageWriteback(page)) {
++ f2fs_submit_bio(sbi, type, sync);
++ wait_on_page_writeback(page);
++ }
++}
++
+ static bool __has_curseg_space(struct f2fs_sb_info *sbi, int type)
+ {
+ struct curseg_info *curseg = CURSEG_I(sbi, type);
+@@ -795,7 +755,7 @@
+
+ if (S_ISDIR(inode->i_mode))
+ return CURSEG_HOT_DATA;
+- else if (is_cold_data(page) || is_cold_file(inode))
++ else if (is_cold_data(page) || file_is_cold(inode))
+ return CURSEG_COLD_DATA;
+ else
+ return CURSEG_WARM_DATA;
+@@ -818,7 +778,7 @@
+ return __get_segment_type_4(page, p_type);
+ }
+ /* NR_CURSEG_TYPE(6) logs by default */
+- BUG_ON(sbi->active_logs != NR_CURSEG_TYPE);
++ f2fs_bug_on(sbi->active_logs != NR_CURSEG_TYPE);
+ return __get_segment_type_6(page, p_type);
+ }
+
+@@ -844,11 +804,12 @@
+ * because, this function updates a summary entry in the
+ * current summary block.
+ */
+- __add_sum_entry(sbi, type, sum, curseg->next_blkoff);
++ __add_sum_entry(sbi, type, sum);
+
+ mutex_lock(&sit_i->sentry_lock);
+ __refresh_next_blkoff(sbi, curseg);
+- sbi->block_count[curseg->alloc_type]++;
++
++ stat_inc_block_count(sbi, curseg);
+
+ /*
+ * SIT information should be updated before segment allocation,
+@@ -894,7 +855,7 @@
+ struct f2fs_summary sum;
+ struct node_info ni;
+
+- BUG_ON(old_blkaddr == NULL_ADDR);
++ f2fs_bug_on(old_blkaddr == NULL_ADDR);
+ get_node_info(sbi, dn->nid, &ni);
+ set_summary(&sum, dn->nid, dn->ofs_in_node, ni.version);
+
+@@ -943,7 +904,7 @@
+
+ curseg->next_blkoff = GET_SEGOFF_FROM_SEG0(sbi, new_blkaddr) &
+ (sbi->blocks_per_seg - 1);
+- __add_sum_entry(sbi, type, sum, curseg->next_blkoff);
++ __add_sum_entry(sbi, type, sum);
+
+ refresh_sit_entry(sbi, old_blkaddr, new_blkaddr);
+
+@@ -980,7 +941,7 @@
+ }
+ curseg->next_blkoff = GET_SEGOFF_FROM_SEG0(sbi, new_blkaddr) &
+ (sbi->blocks_per_seg - 1);
+- __add_sum_entry(sbi, type, sum, curseg->next_blkoff);
++ __add_sum_entry(sbi, type, sum);
+
+ /* change the current log to the next block addr in advance */
+ if (next_segno != segno) {
+@@ -1167,8 +1128,6 @@
+ SUM_JOURNAL_SIZE);
+ written_size += SUM_JOURNAL_SIZE;
+
+- set_page_dirty(page);
+-
+ /* Step 3: write summary entries */
+ for (i = CURSEG_HOT_DATA; i <= CURSEG_COLD_DATA; i++) {
+ unsigned short blkoff;
+@@ -1187,18 +1146,20 @@
+ summary = (struct f2fs_summary *)(kaddr + written_size);
+ *summary = seg_i->sum_blk->entries[j];
+ written_size += SUMMARY_SIZE;
+- set_page_dirty(page);
+
+ if (written_size + SUMMARY_SIZE <= PAGE_CACHE_SIZE -
+ SUM_FOOTER_SIZE)
+ continue;
+
++ set_page_dirty(page);
+ f2fs_put_page(page, 1);
+ page = NULL;
+ }
+ }
+- if (page)
++ if (page) {
++ set_page_dirty(page);
+ f2fs_put_page(page, 1);
++ }
+ }
+
+ static void write_normal_summaries(struct f2fs_sb_info *sbi,
+@@ -1230,7 +1191,6 @@
+ {
+ if (is_set_ckpt_flags(F2FS_CKPT(sbi), CP_UMOUNT_FLAG))
+ write_normal_summaries(sbi, start_blk, CURSEG_HOT_NODE);
+- return;
+ }
+
+ int lookup_journal_in_cursum(struct f2fs_summary_block *sum, int type,
+@@ -1285,7 +1245,7 @@
+ /* get current sit block page without lock */
+ src_page = get_meta_page(sbi, src_off);
+ dst_page = grab_meta_page(sbi, dst_off);
+- BUG_ON(PageDirty(src_page));
++ f2fs_bug_on(PageDirty(src_page));
+
+ src_addr = page_address(src_page);
+ dst_addr = page_address(dst_page);
+@@ -1317,9 +1277,9 @@
+ __mark_sit_entry_dirty(sbi, segno);
+ }
+ update_sits_in_cursum(sum, -sits_in_cursum(sum));
+- return 1;
++ return true;
+ }
+- return 0;
++ return false;
+ }
+
+ /*
+@@ -1579,13 +1539,13 @@
+ {
+ struct dirty_seglist_info *dirty_i = DIRTY_I(sbi);
+ struct free_segmap_info *free_i = FREE_I(sbi);
+- unsigned int segno = 0, offset = 0;
++ unsigned int segno = 0, offset = 0, total_segs = TOTAL_SEGS(sbi);
+ unsigned short valid_blocks;
+
+- while (segno < TOTAL_SEGS(sbi)) {
++ while (1) {
+ /* find dirty segment based on free segmap */
+- segno = find_next_inuse(free_i, TOTAL_SEGS(sbi), offset);
+- if (segno >= TOTAL_SEGS(sbi))
++ segno = find_next_inuse(free_i, total_segs, offset);
++ if (segno >= total_segs)
+ break;
+ offset = segno + 1;
+ valid_blocks = get_valid_blocks(sbi, segno, 0);
+@@ -1683,6 +1643,7 @@
+ sm_info->ovp_segments = le32_to_cpu(ckpt->overprov_segment_count);
+ sm_info->main_segments = le32_to_cpu(raw_super->segment_count_main);
+ sm_info->ssa_blkaddr = le32_to_cpu(raw_super->ssa_blkaddr);
++ sm_info->rec_prefree_segments = DEF_RECLAIM_PREFREE_SEGMENTS;
+
+ err = build_sit_info(sbi);
+ if (err)
+@@ -1790,6 +1751,8 @@
+ void destroy_segment_manager(struct f2fs_sb_info *sbi)
+ {
+ struct f2fs_sm_info *sm_info = SM_I(sbi);
++ if (!sm_info)
++ return;
+ destroy_dirty_segmap(sbi);
+ destroy_curseg(sbi);
+ destroy_free_segmap(sbi);
+diff -Nur linux-3.10.30.orig/fs/f2fs/segment.h linux-linaro-stable-mx6/fs/f2fs/segment.h
+--- linux-3.10.30.orig/fs/f2fs/segment.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/segment.h 2014-05-15 20:34:12.458118041 +0200
+@@ -14,6 +14,8 @@
+ #define NULL_SEGNO ((unsigned int)(~0))
+ #define NULL_SECNO ((unsigned int)(~0))
+
++#define DEF_RECLAIM_PREFREE_SEGMENTS 100 /* 200MB of prefree segments */
++
+ /* L: Logical segment # in volume, R: Relative segment # in main area */
+ #define GET_L2R_SEGNO(free_i, segno) (segno - free_i->start_segno)
+ #define GET_R2L_SEGNO(free_i, segno) (segno + free_i->start_segno)
+@@ -90,6 +92,8 @@
+ (blk_addr << ((sbi)->log_blocksize - F2FS_LOG_SECTOR_SIZE))
+ #define SECTOR_TO_BLOCK(sbi, sectors) \
+ (sectors >> ((sbi)->log_blocksize - F2FS_LOG_SECTOR_SIZE))
++#define MAX_BIO_BLOCKS(max_hw_blocks) \
++ (min((int)max_hw_blocks, BIO_MAX_PAGES))
+
+ /* during checkpoint, bio_private is used to synchronize the last bio */
+ struct bio_private {
+@@ -142,6 +146,7 @@
+ int alloc_mode; /* LFS or SSR */
+ int gc_mode; /* GC_CB or GC_GREEDY */
+ unsigned long *dirty_segmap; /* dirty segment bitmap */
++ unsigned int max_search; /* maximum # of segments to search */
+ unsigned int offset; /* last scanned bitmap offset */
+ unsigned int ofs_unit; /* bitmap search unit */
+ unsigned int min_cost; /* minimum cost */
+@@ -453,7 +458,8 @@
+
+ static inline bool need_SSR(struct f2fs_sb_info *sbi)
+ {
+- return (free_sections(sbi) < overprovision_sections(sbi));
++ return ((prefree_segments(sbi) / sbi->segs_per_sec)
++ + free_sections(sbi) < overprovision_sections(sbi));
+ }
+
+ static inline bool has_not_enough_free_secs(struct f2fs_sb_info *sbi, int freed)
+@@ -468,9 +474,14 @@
+ reserved_sections(sbi)));
+ }
+
++static inline bool excess_prefree_segs(struct f2fs_sb_info *sbi)
++{
++ return (prefree_segments(sbi) > SM_I(sbi)->rec_prefree_segments);
++}
++
+ static inline int utilization(struct f2fs_sb_info *sbi)
+ {
+- return div_u64(valid_user_blocks(sbi) * 100, sbi->user_block_count);
++ return div_u64((u64)valid_user_blocks(sbi) * 100, sbi->user_block_count);
+ }
+
+ /*
+@@ -511,16 +522,13 @@
+ return curseg->next_blkoff;
+ }
+
++#ifdef CONFIG_F2FS_CHECK_FS
+ static inline void check_seg_range(struct f2fs_sb_info *sbi, unsigned int segno)
+ {
+ unsigned int end_segno = SM_I(sbi)->segment_count - 1;
+ BUG_ON(segno > end_segno);
+ }
+
+-/*
+- * This function is used for only debugging.
+- * NOTE: In future, we have to remove this function.
+- */
+ static inline void verify_block_addr(struct f2fs_sb_info *sbi, block_t blk_addr)
+ {
+ struct f2fs_sm_info *sm_info = SM_I(sbi);
+@@ -539,8 +547,9 @@
+ {
+ struct f2fs_sm_info *sm_info = SM_I(sbi);
+ unsigned int end_segno = sm_info->segment_count - 1;
++ bool is_valid = test_bit_le(0, raw_sit->valid_map) ? true : false;
+ int valid_blocks = 0;
+- int i;
++ int cur_pos = 0, next_pos;
+
+ /* check segment usage */
+ BUG_ON(GET_SIT_VBLOCKS(raw_sit) > sbi->blocks_per_seg);
+@@ -549,11 +558,26 @@
+ BUG_ON(segno > end_segno);
+
+ /* check bitmap with valid block count */
+- for (i = 0; i < sbi->blocks_per_seg; i++)
+- if (f2fs_test_bit(i, raw_sit->valid_map))
+- valid_blocks++;
++ do {
++ if (is_valid) {
++ next_pos = find_next_zero_bit_le(&raw_sit->valid_map,
++ sbi->blocks_per_seg,
++ cur_pos);
++ valid_blocks += next_pos - cur_pos;
++ } else
++ next_pos = find_next_bit_le(&raw_sit->valid_map,
++ sbi->blocks_per_seg,
++ cur_pos);
++ cur_pos = next_pos;
++ is_valid = !is_valid;
++ } while (cur_pos < sbi->blocks_per_seg);
+ BUG_ON(GET_SIT_VBLOCKS(raw_sit) != valid_blocks);
+ }
++#else
++#define check_seg_range(sbi, segno)
++#define verify_block_addr(sbi, blk_addr)
++#define check_block_count(sbi, segno, raw_sit)
++#endif
+
+ static inline pgoff_t current_sit_addr(struct f2fs_sb_info *sbi,
+ unsigned int start)
+diff -Nur linux-3.10.30.orig/fs/f2fs/super.c linux-linaro-stable-mx6/fs/f2fs/super.c
+--- linux-3.10.30.orig/fs/f2fs/super.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/super.c 2014-05-15 20:34:12.474118156 +0200
+@@ -18,45 +18,185 @@
+ #include <linux/parser.h>
+ #include <linux/mount.h>
+ #include <linux/seq_file.h>
++#include <linux/proc_fs.h>
+ #include <linux/random.h>
+ #include <linux/exportfs.h>
+ #include <linux/blkdev.h>
+ #include <linux/f2fs_fs.h>
++#include <linux/sysfs.h>
+
+ #include "f2fs.h"
+ #include "node.h"
+ #include "segment.h"
+ #include "xattr.h"
++#include "gc.h"
+
+ #define CREATE_TRACE_POINTS
+ #include <trace/events/f2fs.h>
+
++static struct proc_dir_entry *f2fs_proc_root;
+ static struct kmem_cache *f2fs_inode_cachep;
++static struct kset *f2fs_kset;
+
+ enum {
+- Opt_gc_background_off,
++ Opt_gc_background,
+ Opt_disable_roll_forward,
+ Opt_discard,
+ Opt_noheap,
++ Opt_user_xattr,
+ Opt_nouser_xattr,
++ Opt_acl,
+ Opt_noacl,
+ Opt_active_logs,
+ Opt_disable_ext_identify,
++ Opt_inline_xattr,
+ Opt_err,
+ };
+
+ static match_table_t f2fs_tokens = {
+- {Opt_gc_background_off, "background_gc_off"},
++ {Opt_gc_background, "background_gc=%s"},
+ {Opt_disable_roll_forward, "disable_roll_forward"},
+ {Opt_discard, "discard"},
+ {Opt_noheap, "no_heap"},
++ {Opt_user_xattr, "user_xattr"},
+ {Opt_nouser_xattr, "nouser_xattr"},
++ {Opt_acl, "acl"},
+ {Opt_noacl, "noacl"},
+ {Opt_active_logs, "active_logs=%u"},
+ {Opt_disable_ext_identify, "disable_ext_identify"},
++ {Opt_inline_xattr, "inline_xattr"},
+ {Opt_err, NULL},
+ };
+
++/* Sysfs support for f2fs */
++enum {
++ GC_THREAD, /* struct f2fs_gc_thread */
++ SM_INFO, /* struct f2fs_sm_info */
++};
++
++struct f2fs_attr {
++ struct attribute attr;
++ ssize_t (*show)(struct f2fs_attr *, struct f2fs_sb_info *, char *);
++ ssize_t (*store)(struct f2fs_attr *, struct f2fs_sb_info *,
++ const char *, size_t);
++ int struct_type;
++ int offset;
++};
++
++static unsigned char *__struct_ptr(struct f2fs_sb_info *sbi, int struct_type)
++{
++ if (struct_type == GC_THREAD)
++ return (unsigned char *)sbi->gc_thread;
++ else if (struct_type == SM_INFO)
++ return (unsigned char *)SM_I(sbi);
++ return NULL;
++}
++
++static ssize_t f2fs_sbi_show(struct f2fs_attr *a,
++ struct f2fs_sb_info *sbi, char *buf)
++{
++ unsigned char *ptr = NULL;
++ unsigned int *ui;
++
++ ptr = __struct_ptr(sbi, a->struct_type);
++ if (!ptr)
++ return -EINVAL;
++
++ ui = (unsigned int *)(ptr + a->offset);
++
++ return snprintf(buf, PAGE_SIZE, "%u\n", *ui);
++}
++
++static ssize_t f2fs_sbi_store(struct f2fs_attr *a,
++ struct f2fs_sb_info *sbi,
++ const char *buf, size_t count)
++{
++ unsigned char *ptr;
++ unsigned long t;
++ unsigned int *ui;
++ ssize_t ret;
++
++ ptr = __struct_ptr(sbi, a->struct_type);
++ if (!ptr)
++ return -EINVAL;
++
++ ui = (unsigned int *)(ptr + a->offset);
++
++ ret = kstrtoul(skip_spaces(buf), 0, &t);
++ if (ret < 0)
++ return ret;
++ *ui = t;
++ return count;
++}
++
++static ssize_t f2fs_attr_show(struct kobject *kobj,
++ struct attribute *attr, char *buf)
++{
++ struct f2fs_sb_info *sbi = container_of(kobj, struct f2fs_sb_info,
++ s_kobj);
++ struct f2fs_attr *a = container_of(attr, struct f2fs_attr, attr);
++
++ return a->show ? a->show(a, sbi, buf) : 0;
++}
++
++static ssize_t f2fs_attr_store(struct kobject *kobj, struct attribute *attr,
++ const char *buf, size_t len)
++{
++ struct f2fs_sb_info *sbi = container_of(kobj, struct f2fs_sb_info,
++ s_kobj);
++ struct f2fs_attr *a = container_of(attr, struct f2fs_attr, attr);
++
++ return a->store ? a->store(a, sbi, buf, len) : 0;
++}
++
++static void f2fs_sb_release(struct kobject *kobj)
++{
++ struct f2fs_sb_info *sbi = container_of(kobj, struct f2fs_sb_info,
++ s_kobj);
++ complete(&sbi->s_kobj_unregister);
++}
++
++#define F2FS_ATTR_OFFSET(_struct_type, _name, _mode, _show, _store, _offset) \
++static struct f2fs_attr f2fs_attr_##_name = { \
++ .attr = {.name = __stringify(_name), .mode = _mode }, \
++ .show = _show, \
++ .store = _store, \
++ .struct_type = _struct_type, \
++ .offset = _offset \
++}
++
++#define F2FS_RW_ATTR(struct_type, struct_name, name, elname) \
++ F2FS_ATTR_OFFSET(struct_type, name, 0644, \
++ f2fs_sbi_show, f2fs_sbi_store, \
++ offsetof(struct struct_name, elname))
++
++F2FS_RW_ATTR(GC_THREAD, f2fs_gc_kthread, gc_min_sleep_time, min_sleep_time);
++F2FS_RW_ATTR(GC_THREAD, f2fs_gc_kthread, gc_max_sleep_time, max_sleep_time);
++F2FS_RW_ATTR(GC_THREAD, f2fs_gc_kthread, gc_no_gc_sleep_time, no_gc_sleep_time);
++F2FS_RW_ATTR(GC_THREAD, f2fs_gc_kthread, gc_idle, gc_idle);
++F2FS_RW_ATTR(SM_INFO, f2fs_sm_info, reclaim_segments, rec_prefree_segments);
++
++#define ATTR_LIST(name) (&f2fs_attr_##name.attr)
++static struct attribute *f2fs_attrs[] = {
++ ATTR_LIST(gc_min_sleep_time),
++ ATTR_LIST(gc_max_sleep_time),
++ ATTR_LIST(gc_no_gc_sleep_time),
++ ATTR_LIST(gc_idle),
++ ATTR_LIST(reclaim_segments),
++ NULL,
++};
++
++static const struct sysfs_ops f2fs_attr_ops = {
++ .show = f2fs_attr_show,
++ .store = f2fs_attr_store,
++};
++
++static struct kobj_type f2fs_ktype = {
++ .default_attrs = f2fs_attrs,
++ .sysfs_ops = &f2fs_attr_ops,
++ .release = f2fs_sb_release,
++};
++
+ void f2fs_msg(struct super_block *sb, const char *level, const char *fmt, ...)
+ {
+ struct va_format vaf;
+@@ -76,6 +216,111 @@
+ inode_init_once(&fi->vfs_inode);
+ }
+
++static int parse_options(struct super_block *sb, char *options)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(sb);
++ substring_t args[MAX_OPT_ARGS];
++ char *p, *name;
++ int arg = 0;
++
++ if (!options)
++ return 0;
++
++ while ((p = strsep(&options, ",")) != NULL) {
++ int token;
++ if (!*p)
++ continue;
++ /*
++ * Initialize args struct so we know whether arg was
++ * found; some options take optional arguments.
++ */
++ args[0].to = args[0].from = NULL;
++ token = match_token(p, f2fs_tokens, args);
++
++ switch (token) {
++ case Opt_gc_background:
++ name = match_strdup(&args[0]);
++
++ if (!name)
++ return -ENOMEM;
++ if (!strncmp(name, "on", 2))
++ set_opt(sbi, BG_GC);
++ else if (!strncmp(name, "off", 3))
++ clear_opt(sbi, BG_GC);
++ else {
++ kfree(name);
++ return -EINVAL;
++ }
++ kfree(name);
++ break;
++ case Opt_disable_roll_forward:
++ set_opt(sbi, DISABLE_ROLL_FORWARD);
++ break;
++ case Opt_discard:
++ set_opt(sbi, DISCARD);
++ break;
++ case Opt_noheap:
++ set_opt(sbi, NOHEAP);
++ break;
++#ifdef CONFIG_F2FS_FS_XATTR
++ case Opt_user_xattr:
++ set_opt(sbi, XATTR_USER);
++ break;
++ case Opt_nouser_xattr:
++ clear_opt(sbi, XATTR_USER);
++ break;
++ case Opt_inline_xattr:
++ set_opt(sbi, INLINE_XATTR);
++ break;
++#else
++ case Opt_user_xattr:
++ f2fs_msg(sb, KERN_INFO,
++ "user_xattr options not supported");
++ break;
++ case Opt_nouser_xattr:
++ f2fs_msg(sb, KERN_INFO,
++ "nouser_xattr options not supported");
++ break;
++ case Opt_inline_xattr:
++ f2fs_msg(sb, KERN_INFO,
++ "inline_xattr options not supported");
++ break;
++#endif
++#ifdef CONFIG_F2FS_FS_POSIX_ACL
++ case Opt_acl:
++ set_opt(sbi, POSIX_ACL);
++ break;
++ case Opt_noacl:
++ clear_opt(sbi, POSIX_ACL);
++ break;
++#else
++ case Opt_acl:
++ f2fs_msg(sb, KERN_INFO, "acl options not supported");
++ break;
++ case Opt_noacl:
++ f2fs_msg(sb, KERN_INFO, "noacl options not supported");
++ break;
++#endif
++ case Opt_active_logs:
++ if (args->from && match_int(args, &arg))
++ return -EINVAL;
++ if (arg != 2 && arg != 4 && arg != NR_CURSEG_TYPE)
++ return -EINVAL;
++ sbi->active_logs = arg;
++ break;
++ case Opt_disable_ext_identify:
++ set_opt(sbi, DISABLE_EXT_IDENTIFY);
++ break;
++ default:
++ f2fs_msg(sb, KERN_ERR,
++ "Unrecognized mount option \"%s\" or missing value",
++ p);
++ return -EINVAL;
++ }
++ }
++ return 0;
++}
++
+ static struct inode *f2fs_alloc_inode(struct super_block *sb)
+ {
+ struct f2fs_inode_info *fi;
+@@ -95,6 +340,9 @@
+
+ set_inode_flag(fi, FI_NEW_INODE);
+
++ if (test_opt(F2FS_SB(sb), INLINE_XATTR))
++ set_inode_flag(fi, FI_INLINE_XATTR);
++
+ return &fi->vfs_inode;
+ }
+
+@@ -112,6 +360,16 @@
+ return generic_drop_inode(inode);
+ }
+
++/*
++ * f2fs_dirty_inode() is called from __mark_inode_dirty()
++ *
++ * We should call set_dirty_inode to write the dirty inode through write_inode.
++ */
++static void f2fs_dirty_inode(struct inode *inode, int flags)
++{
++ set_inode_flag(F2FS_I(inode), FI_DIRTY_INODE);
++}
++
+ static void f2fs_i_callback(struct rcu_head *head)
+ {
+ struct inode *inode = container_of(head, struct inode, i_rcu);
+@@ -127,10 +385,18 @@
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(sb);
+
++ if (sbi->s_proc) {
++ remove_proc_entry("segment_info", sbi->s_proc);
++ remove_proc_entry(sb->s_id, f2fs_proc_root);
++ }
++ kobject_del(&sbi->s_kobj);
++
+ f2fs_destroy_stats(sbi);
+ stop_gc_thread(sbi);
+
+- write_checkpoint(sbi, true);
++ /* We don't need to do checkpoint when it's clean */
++ if (sbi->s_dirty && get_pages(sbi, F2FS_DIRTY_NODES))
++ write_checkpoint(sbi, true);
+
+ iput(sbi->node_inode);
+ iput(sbi->meta_inode);
+@@ -140,6 +406,8 @@
+ destroy_segment_manager(sbi);
+
+ kfree(sbi->ckpt);
++ kobject_put(&sbi->s_kobj);
++ wait_for_completion(&sbi->s_kobj_unregister);
+
+ sb->s_fs_info = NULL;
+ brelse(sbi->raw_super_buf);
+@@ -170,7 +438,7 @@
+ {
+ int err;
+
+- if (sb->s_flags & MS_RDONLY)
++ if (f2fs_readonly(sb))
+ return 0;
+
+ err = f2fs_sync_fs(sb, 1);
+@@ -214,10 +482,10 @@
+ {
+ struct f2fs_sb_info *sbi = F2FS_SB(root->d_sb);
+
+- if (test_opt(sbi, BG_GC))
+- seq_puts(seq, ",background_gc_on");
++ if (!(root->d_sb->s_flags & MS_RDONLY) && test_opt(sbi, BG_GC))
++ seq_printf(seq, ",background_gc=%s", "on");
+ else
+- seq_puts(seq, ",background_gc_off");
++ seq_printf(seq, ",background_gc=%s", "off");
+ if (test_opt(sbi, DISABLE_ROLL_FORWARD))
+ seq_puts(seq, ",disable_roll_forward");
+ if (test_opt(sbi, DISCARD))
+@@ -229,6 +497,8 @@
+ seq_puts(seq, ",user_xattr");
+ else
+ seq_puts(seq, ",nouser_xattr");
++ if (test_opt(sbi, INLINE_XATTR))
++ seq_puts(seq, ",inline_xattr");
+ #endif
+ #ifdef CONFIG_F2FS_FS_POSIX_ACL
+ if (test_opt(sbi, POSIX_ACL))
+@@ -244,11 +514,94 @@
+ return 0;
+ }
+
++static int segment_info_seq_show(struct seq_file *seq, void *offset)
++{
++ struct super_block *sb = seq->private;
++ struct f2fs_sb_info *sbi = F2FS_SB(sb);
++ unsigned int total_segs = le32_to_cpu(sbi->raw_super->segment_count_main);
++ int i;
++
++ for (i = 0; i < total_segs; i++) {
++ seq_printf(seq, "%u", get_valid_blocks(sbi, i, 1));
++ if (i != 0 && (i % 10) == 0)
++ seq_puts(seq, "\n");
++ else
++ seq_puts(seq, " ");
++ }
++ return 0;
++}
++
++static int segment_info_open_fs(struct inode *inode, struct file *file)
++{
++ return single_open(file, segment_info_seq_show, PDE_DATA(inode));
++}
++
++static const struct file_operations f2fs_seq_segment_info_fops = {
++ .owner = THIS_MODULE,
++ .open = segment_info_open_fs,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++static int f2fs_remount(struct super_block *sb, int *flags, char *data)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(sb);
++ struct f2fs_mount_info org_mount_opt;
++ int err, active_logs;
++
++ /*
++ * Save the old mount options in case we
++ * need to restore them.
++ */
++ org_mount_opt = sbi->mount_opt;
++ active_logs = sbi->active_logs;
++
++ /* parse mount options */
++ err = parse_options(sb, data);
++ if (err)
++ goto restore_opts;
++
++ /*
++ * Previous and new state of filesystem is RO,
++ * so no point in checking GC conditions.
++ */
++ if ((sb->s_flags & MS_RDONLY) && (*flags & MS_RDONLY))
++ goto skip;
++
++ /*
++ * We stop the GC thread if FS is mounted as RO
++ * or if background_gc = off is passed in mount
++ * option. Also sync the filesystem.
++ */
++ if ((*flags & MS_RDONLY) || !test_opt(sbi, BG_GC)) {
++ if (sbi->gc_thread) {
++ stop_gc_thread(sbi);
++ f2fs_sync_fs(sb, 1);
++ }
++ } else if (test_opt(sbi, BG_GC) && !sbi->gc_thread) {
++ err = start_gc_thread(sbi);
++ if (err)
++ goto restore_opts;
++ }
++skip:
++ /* Update the POSIXACL Flag */
++ sb->s_flags = (sb->s_flags & ~MS_POSIXACL) |
++ (test_opt(sbi, POSIX_ACL) ? MS_POSIXACL : 0);
++ return 0;
++
++restore_opts:
++ sbi->mount_opt = org_mount_opt;
++ sbi->active_logs = active_logs;
++ return err;
++}
++
+ static struct super_operations f2fs_sops = {
+ .alloc_inode = f2fs_alloc_inode,
+ .drop_inode = f2fs_drop_inode,
+ .destroy_inode = f2fs_destroy_inode,
+ .write_inode = f2fs_write_inode,
++ .dirty_inode = f2fs_dirty_inode,
+ .show_options = f2fs_show_options,
+ .evict_inode = f2fs_evict_inode,
+ .put_super = f2fs_put_super,
+@@ -256,6 +609,7 @@
+ .freeze_fs = f2fs_freeze,
+ .unfreeze_fs = f2fs_unfreeze,
+ .statfs = f2fs_statfs,
++ .remount_fs = f2fs_remount,
+ };
+
+ static struct inode *f2fs_nfs_get_inode(struct super_block *sb,
+@@ -303,82 +657,9 @@
+ .get_parent = f2fs_get_parent,
+ };
+
+-static int parse_options(struct super_block *sb, struct f2fs_sb_info *sbi,
+- char *options)
+-{
+- substring_t args[MAX_OPT_ARGS];
+- char *p;
+- int arg = 0;
+-
+- if (!options)
+- return 0;
+-
+- while ((p = strsep(&options, ",")) != NULL) {
+- int token;
+- if (!*p)
+- continue;
+- /*
+- * Initialize args struct so we know whether arg was
+- * found; some options take optional arguments.
+- */
+- args[0].to = args[0].from = NULL;
+- token = match_token(p, f2fs_tokens, args);
+-
+- switch (token) {
+- case Opt_gc_background_off:
+- clear_opt(sbi, BG_GC);
+- break;
+- case Opt_disable_roll_forward:
+- set_opt(sbi, DISABLE_ROLL_FORWARD);
+- break;
+- case Opt_discard:
+- set_opt(sbi, DISCARD);
+- break;
+- case Opt_noheap:
+- set_opt(sbi, NOHEAP);
+- break;
+-#ifdef CONFIG_F2FS_FS_XATTR
+- case Opt_nouser_xattr:
+- clear_opt(sbi, XATTR_USER);
+- break;
+-#else
+- case Opt_nouser_xattr:
+- f2fs_msg(sb, KERN_INFO,
+- "nouser_xattr options not supported");
+- break;
+-#endif
+-#ifdef CONFIG_F2FS_FS_POSIX_ACL
+- case Opt_noacl:
+- clear_opt(sbi, POSIX_ACL);
+- break;
+-#else
+- case Opt_noacl:
+- f2fs_msg(sb, KERN_INFO, "noacl options not supported");
+- break;
+-#endif
+- case Opt_active_logs:
+- if (args->from && match_int(args, &arg))
+- return -EINVAL;
+- if (arg != 2 && arg != 4 && arg != NR_CURSEG_TYPE)
+- return -EINVAL;
+- sbi->active_logs = arg;
+- break;
+- case Opt_disable_ext_identify:
+- set_opt(sbi, DISABLE_EXT_IDENTIFY);
+- break;
+- default:
+- f2fs_msg(sb, KERN_ERR,
+- "Unrecognized mount option \"%s\" or missing value",
+- p);
+- return -EINVAL;
+- }
+- }
+- return 0;
+-}
+-
+ static loff_t max_file_size(unsigned bits)
+ {
+- loff_t result = ADDRS_PER_INODE;
++ loff_t result = (DEF_ADDRS_PER_INODE - F2FS_INLINE_XATTR_ADDRS);
+ loff_t leaf_count = ADDRS_PER_BLOCK;
+
+ /* two direct node blocks */
+@@ -487,30 +768,47 @@
+ atomic_set(&sbi->nr_pages[i], 0);
+ }
+
+-static int validate_superblock(struct super_block *sb,
+- struct f2fs_super_block **raw_super,
+- struct buffer_head **raw_super_buf, sector_t block)
++/*
++ * Read f2fs raw super block.
++ * Because we have two copies of super block, so read the first one at first,
++ * if the first one is invalid, move to read the second one.
++ */
++static int read_raw_super_block(struct super_block *sb,
++ struct f2fs_super_block **raw_super,
++ struct buffer_head **raw_super_buf)
+ {
+- const char *super = (block == 0 ? "first" : "second");
++ int block = 0;
+
+- /* read f2fs raw super block */
++retry:
+ *raw_super_buf = sb_bread(sb, block);
+ if (!*raw_super_buf) {
+- f2fs_msg(sb, KERN_ERR, "unable to read %s superblock",
+- super);
+- return -EIO;
++ f2fs_msg(sb, KERN_ERR, "Unable to read %dth superblock",
++ block + 1);
++ if (block == 0) {
++ block++;
++ goto retry;
++ } else {
++ return -EIO;
++ }
+ }
+
+ *raw_super = (struct f2fs_super_block *)
+ ((char *)(*raw_super_buf)->b_data + F2FS_SUPER_OFFSET);
+
+ /* sanity checking of raw super */
+- if (!sanity_check_raw_super(sb, *raw_super))
+- return 0;
++ if (sanity_check_raw_super(sb, *raw_super)) {
++ brelse(*raw_super_buf);
++ f2fs_msg(sb, KERN_ERR, "Can't find a valid F2FS filesystem "
++ "in %dth superblock", block + 1);
++ if(block == 0) {
++ block++;
++ goto retry;
++ } else {
++ return -EINVAL;
++ }
++ }
+
+- f2fs_msg(sb, KERN_ERR, "Can't find a valid F2FS filesystem "
+- "in %s superblock", super);
+- return -EINVAL;
++ return 0;
+ }
+
+ static int f2fs_fill_super(struct super_block *sb, void *data, int silent)
+@@ -520,7 +818,6 @@
+ struct buffer_head *raw_super_buf;
+ struct inode *root;
+ long err = -EINVAL;
+- int i;
+
+ /* allocate memory for f2fs-specific super block info */
+ sbi = kzalloc(sizeof(struct f2fs_sb_info), GFP_KERNEL);
+@@ -533,14 +830,11 @@
+ goto free_sbi;
+ }
+
+- err = validate_superblock(sb, &raw_super, &raw_super_buf, 0);
+- if (err) {
+- brelse(raw_super_buf);
+- /* check secondary superblock when primary failed */
+- err = validate_superblock(sb, &raw_super, &raw_super_buf, 1);
+- if (err)
+- goto free_sb_buf;
+- }
++ err = read_raw_super_block(sb, &raw_super, &raw_super_buf);
++ if (err)
++ goto free_sbi;
++
++ sb->s_fs_info = sbi;
+ /* init some FS parameters */
+ sbi->active_logs = NR_CURSEG_TYPE;
+
+@@ -553,7 +847,7 @@
+ set_opt(sbi, POSIX_ACL);
+ #endif
+ /* parse mount options */
+- err = parse_options(sb, sbi, (char *)data);
++ err = parse_options(sb, (char *)data);
+ if (err)
+ goto free_sb_buf;
+
+@@ -565,7 +859,6 @@
+ sb->s_xattr = f2fs_xattr_handlers;
+ sb->s_export_op = &f2fs_export_ops;
+ sb->s_magic = F2FS_SUPER_MAGIC;
+- sb->s_fs_info = sbi;
+ sb->s_time_gran = 1;
+ sb->s_flags = (sb->s_flags & ~MS_POSIXACL) |
+ (test_opt(sbi, POSIX_ACL) ? MS_POSIXACL : 0);
+@@ -578,12 +871,12 @@
+ mutex_init(&sbi->gc_mutex);
+ mutex_init(&sbi->writepages);
+ mutex_init(&sbi->cp_mutex);
+- for (i = 0; i < NR_GLOBAL_LOCKS; i++)
+- mutex_init(&sbi->fs_lock[i]);
+ mutex_init(&sbi->node_write);
+- sbi->por_doing = 0;
++ sbi->por_doing = false;
+ spin_lock_init(&sbi->stat_lock);
+ init_rwsem(&sbi->bio_sem);
++ init_rwsem(&sbi->cp_rwsem);
++ init_waitqueue_head(&sbi->cp_wait);
+ init_sb_info(sbi);
+
+ /* get an inode for meta space */
+@@ -674,14 +967,27 @@
+ "Cannot recover all fsync data errno=%ld", err);
+ }
+
+- /* After POR, we can run background GC thread */
+- err = start_gc_thread(sbi);
+- if (err)
+- goto fail;
++ /*
++ * If filesystem is not mounted as read-only then
++ * do start the gc_thread.
++ */
++ if (!(sb->s_flags & MS_RDONLY)) {
++ /* After POR, we can run background GC thread.*/
++ err = start_gc_thread(sbi);
++ if (err)
++ goto free_gc;
++ }
+
+ err = f2fs_build_stats(sbi);
+ if (err)
+- goto fail;
++ goto free_gc;
++
++ if (f2fs_proc_root)
++ sbi->s_proc = proc_mkdir(sb->s_id, f2fs_proc_root);
++
++ if (sbi->s_proc)
++ proc_create_data("segment_info", S_IRUGO, sbi->s_proc,
++ &f2fs_seq_segment_info_fops, sb);
+
+ if (test_opt(sbi, DISCARD)) {
+ struct request_queue *q = bdev_get_queue(sb->s_bdev);
+@@ -691,8 +997,21 @@
+ "the device does not support discard");
+ }
+
++ sbi->s_kobj.kset = f2fs_kset;
++ init_completion(&sbi->s_kobj_unregister);
++ err = kobject_init_and_add(&sbi->s_kobj, &f2fs_ktype, NULL,
++ "%s", sb->s_id);
++ if (err)
++ goto fail;
++
+ return 0;
+ fail:
++ if (sbi->s_proc) {
++ remove_proc_entry("segment_info", sbi->s_proc);
++ remove_proc_entry(sb->s_id, f2fs_proc_root);
++ }
++ f2fs_destroy_stats(sbi);
++free_gc:
+ stop_gc_thread(sbi);
+ free_root_inode:
+ dput(sb->s_root);
+@@ -758,29 +1077,49 @@
+ goto fail;
+ err = create_node_manager_caches();
+ if (err)
+- goto fail;
++ goto free_inodecache;
+ err = create_gc_caches();
+ if (err)
+- goto fail;
++ goto free_node_manager_caches;
+ err = create_checkpoint_caches();
+ if (err)
+- goto fail;
++ goto free_gc_caches;
++ f2fs_kset = kset_create_and_add("f2fs", NULL, fs_kobj);
++ if (!f2fs_kset) {
++ err = -ENOMEM;
++ goto free_checkpoint_caches;
++ }
+ err = register_filesystem(&f2fs_fs_type);
+ if (err)
+- goto fail;
++ goto free_kset;
+ f2fs_create_root_stats();
++ f2fs_proc_root = proc_mkdir("fs/f2fs", NULL);
++ return 0;
++
++free_kset:
++ kset_unregister(f2fs_kset);
++free_checkpoint_caches:
++ destroy_checkpoint_caches();
++free_gc_caches:
++ destroy_gc_caches();
++free_node_manager_caches:
++ destroy_node_manager_caches();
++free_inodecache:
++ destroy_inodecache();
+ fail:
+ return err;
+ }
+
+ static void __exit exit_f2fs_fs(void)
+ {
++ remove_proc_entry("fs/f2fs", NULL);
+ f2fs_destroy_root_stats();
+ unregister_filesystem(&f2fs_fs_type);
+ destroy_checkpoint_caches();
+ destroy_gc_caches();
+ destroy_node_manager_caches();
+ destroy_inodecache();
++ kset_unregister(f2fs_kset);
+ }
+
+ module_init(init_f2fs_fs)
+diff -Nur linux-3.10.30.orig/fs/f2fs/xattr.c linux-linaro-stable-mx6/fs/f2fs/xattr.c
+--- linux-3.10.30.orig/fs/f2fs/xattr.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/xattr.c 2014-05-15 20:34:12.474118156 +0200
+@@ -20,6 +20,7 @@
+ */
+ #include <linux/rwsem.h>
+ #include <linux/f2fs_fs.h>
++#include <linux/security.h>
+ #include "f2fs.h"
+ #include "xattr.h"
+
+@@ -43,6 +44,10 @@
+ prefix = XATTR_TRUSTED_PREFIX;
+ prefix_len = XATTR_TRUSTED_PREFIX_LEN;
+ break;
++ case F2FS_XATTR_INDEX_SECURITY:
++ prefix = XATTR_SECURITY_PREFIX;
++ prefix_len = XATTR_SECURITY_PREFIX_LEN;
++ break;
+ default:
+ return -EINVAL;
+ }
+@@ -50,7 +55,7 @@
+ total_len = prefix_len + name_len + 1;
+ if (list && total_len <= list_size) {
+ memcpy(list, prefix, prefix_len);
+- memcpy(list+prefix_len, name, name_len);
++ memcpy(list + prefix_len, name, name_len);
+ list[prefix_len + name_len] = '\0';
+ }
+ return total_len;
+@@ -70,13 +75,14 @@
+ if (!capable(CAP_SYS_ADMIN))
+ return -EPERM;
+ break;
++ case F2FS_XATTR_INDEX_SECURITY:
++ break;
+ default:
+ return -EINVAL;
+ }
+ if (strcmp(name, "") == 0)
+ return -EINVAL;
+- return f2fs_getxattr(dentry->d_inode, type, name,
+- buffer, size);
++ return f2fs_getxattr(dentry->d_inode, type, name, buffer, size);
+ }
+
+ static int f2fs_xattr_generic_set(struct dentry *dentry, const char *name,
+@@ -93,13 +99,15 @@
+ if (!capable(CAP_SYS_ADMIN))
+ return -EPERM;
+ break;
++ case F2FS_XATTR_INDEX_SECURITY:
++ break;
+ default:
+ return -EINVAL;
+ }
+ if (strcmp(name, "") == 0)
+ return -EINVAL;
+
+- return f2fs_setxattr(dentry->d_inode, type, name, value, size);
++ return f2fs_setxattr(dentry->d_inode, type, name, value, size, NULL);
+ }
+
+ static size_t f2fs_xattr_advise_list(struct dentry *dentry, char *list,
+@@ -145,6 +153,34 @@
+ return 0;
+ }
+
++#ifdef CONFIG_F2FS_FS_SECURITY
++static int __f2fs_setxattr(struct inode *inode, int name_index,
++ const char *name, const void *value, size_t value_len,
++ struct page *ipage);
++static int f2fs_initxattrs(struct inode *inode, const struct xattr *xattr_array,
++ void *page)
++{
++ const struct xattr *xattr;
++ int err = 0;
++
++ for (xattr = xattr_array; xattr->name != NULL; xattr++) {
++ err = __f2fs_setxattr(inode, F2FS_XATTR_INDEX_SECURITY,
++ xattr->name, xattr->value,
++ xattr->value_len, (struct page *)page);
++ if (err < 0)
++ break;
++ }
++ return err;
++}
++
++int f2fs_init_security(struct inode *inode, struct inode *dir,
++ const struct qstr *qstr, struct page *ipage)
++{
++ return security_inode_init_security(inode, dir, qstr,
++ &f2fs_initxattrs, ipage);
++}
++#endif
++
+ const struct xattr_handler f2fs_xattr_user_handler = {
+ .prefix = XATTR_USER_PREFIX,
+ .flags = F2FS_XATTR_INDEX_USER,
+@@ -169,6 +205,14 @@
+ .set = f2fs_xattr_advise_set,
+ };
+
++const struct xattr_handler f2fs_xattr_security_handler = {
++ .prefix = XATTR_SECURITY_PREFIX,
++ .flags = F2FS_XATTR_INDEX_SECURITY,
++ .list = f2fs_xattr_generic_list,
++ .get = f2fs_xattr_generic_get,
++ .set = f2fs_xattr_generic_set,
++};
++
+ static const struct xattr_handler *f2fs_xattr_handler_map[] = {
+ [F2FS_XATTR_INDEX_USER] = &f2fs_xattr_user_handler,
+ #ifdef CONFIG_F2FS_FS_POSIX_ACL
+@@ -176,6 +220,9 @@
+ [F2FS_XATTR_INDEX_POSIX_ACL_DEFAULT] = &f2fs_xattr_acl_default_handler,
+ #endif
+ [F2FS_XATTR_INDEX_TRUSTED] = &f2fs_xattr_trusted_handler,
++#ifdef CONFIG_F2FS_FS_SECURITY
++ [F2FS_XATTR_INDEX_SECURITY] = &f2fs_xattr_security_handler,
++#endif
+ [F2FS_XATTR_INDEX_ADVISE] = &f2fs_xattr_advise_handler,
+ };
+
+@@ -186,6 +233,9 @@
+ &f2fs_xattr_acl_default_handler,
+ #endif
+ &f2fs_xattr_trusted_handler,
++#ifdef CONFIG_F2FS_FS_SECURITY
++ &f2fs_xattr_security_handler,
++#endif
+ &f2fs_xattr_advise_handler,
+ NULL,
+ };
+@@ -199,38 +249,170 @@
+ return handler;
+ }
+
++static struct f2fs_xattr_entry *__find_xattr(void *base_addr, int name_index,
++ size_t name_len, const char *name)
++{
++ struct f2fs_xattr_entry *entry;
++
++ list_for_each_xattr(entry, base_addr) {
++ if (entry->e_name_index != name_index)
++ continue;
++ if (entry->e_name_len != name_len)
++ continue;
++ if (!memcmp(entry->e_name, name, name_len))
++ break;
++ }
++ return entry;
++}
++
++static void *read_all_xattrs(struct inode *inode, struct page *ipage)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
++ struct f2fs_xattr_header *header;
++ size_t size = PAGE_SIZE, inline_size = 0;
++ void *txattr_addr;
++
++ inline_size = inline_xattr_size(inode);
++
++ txattr_addr = kzalloc(inline_size + size, GFP_KERNEL);
++ if (!txattr_addr)
++ return NULL;
++
++ /* read from inline xattr */
++ if (inline_size) {
++ struct page *page = NULL;
++ void *inline_addr;
++
++ if (ipage) {
++ inline_addr = inline_xattr_addr(ipage);
++ } else {
++ page = get_node_page(sbi, inode->i_ino);
++ if (IS_ERR(page))
++ goto fail;
++ inline_addr = inline_xattr_addr(page);
++ }
++ memcpy(txattr_addr, inline_addr, inline_size);
++ f2fs_put_page(page, 1);
++ }
++
++ /* read from xattr node block */
++ if (F2FS_I(inode)->i_xattr_nid) {
++ struct page *xpage;
++ void *xattr_addr;
++
++ /* The inode already has an extended attribute block. */
++ xpage = get_node_page(sbi, F2FS_I(inode)->i_xattr_nid);
++ if (IS_ERR(xpage))
++ goto fail;
++
++ xattr_addr = page_address(xpage);
++ memcpy(txattr_addr + inline_size, xattr_addr, PAGE_SIZE);
++ f2fs_put_page(xpage, 1);
++ }
++
++ header = XATTR_HDR(txattr_addr);
++
++ /* never been allocated xattrs */
++ if (le32_to_cpu(header->h_magic) != F2FS_XATTR_MAGIC) {
++ header->h_magic = cpu_to_le32(F2FS_XATTR_MAGIC);
++ header->h_refcount = cpu_to_le32(1);
++ }
++ return txattr_addr;
++fail:
++ kzfree(txattr_addr);
++ return NULL;
++}
++
++static inline int write_all_xattrs(struct inode *inode, __u32 hsize,
++ void *txattr_addr, struct page *ipage)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
++ size_t inline_size = 0;
++ void *xattr_addr;
++ struct page *xpage;
++ nid_t new_nid = 0;
++ int err;
++
++ inline_size = inline_xattr_size(inode);
++
++ if (hsize > inline_size && !F2FS_I(inode)->i_xattr_nid)
++ if (!alloc_nid(sbi, &new_nid))
++ return -ENOSPC;
++
++ /* write to inline xattr */
++ if (inline_size) {
++ struct page *page = NULL;
++ void *inline_addr;
++
++ if (ipage) {
++ inline_addr = inline_xattr_addr(ipage);
++ } else {
++ page = get_node_page(sbi, inode->i_ino);
++ if (IS_ERR(page)) {
++ alloc_nid_failed(sbi, new_nid);
++ return PTR_ERR(page);
++ }
++ inline_addr = inline_xattr_addr(page);
++ }
++ memcpy(inline_addr, txattr_addr, inline_size);
++ f2fs_put_page(page, 1);
++
++ /* no need to use xattr node block */
++ if (hsize <= inline_size) {
++ err = truncate_xattr_node(inode, ipage);
++ alloc_nid_failed(sbi, new_nid);
++ return err;
++ }
++ }
++
++ /* write to xattr node block */
++ if (F2FS_I(inode)->i_xattr_nid) {
++ xpage = get_node_page(sbi, F2FS_I(inode)->i_xattr_nid);
++ if (IS_ERR(xpage)) {
++ alloc_nid_failed(sbi, new_nid);
++ return PTR_ERR(xpage);
++ }
++ f2fs_bug_on(new_nid);
++ } else {
++ struct dnode_of_data dn;
++ set_new_dnode(&dn, inode, NULL, NULL, new_nid);
++ xpage = new_node_page(&dn, XATTR_NODE_OFFSET, ipage);
++ if (IS_ERR(xpage)) {
++ alloc_nid_failed(sbi, new_nid);
++ return PTR_ERR(xpage);
++ }
++ alloc_nid_done(sbi, new_nid);
++ }
++
++ xattr_addr = page_address(xpage);
++ memcpy(xattr_addr, txattr_addr + inline_size, PAGE_SIZE -
++ sizeof(struct node_footer));
++ set_page_dirty(xpage);
++ f2fs_put_page(xpage, 1);
++
++ /* need to checkpoint during fsync */
++ F2FS_I(inode)->xattr_ver = cur_cp_version(F2FS_CKPT(sbi));
++ return 0;
++}
++
+ int f2fs_getxattr(struct inode *inode, int name_index, const char *name,
+ void *buffer, size_t buffer_size)
+ {
+- struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+- struct f2fs_inode_info *fi = F2FS_I(inode);
+ struct f2fs_xattr_entry *entry;
+- struct page *page;
+ void *base_addr;
+- int error = 0, found = 0;
++ int error = 0;
+ size_t value_len, name_len;
+
+ if (name == NULL)
+ return -EINVAL;
+ name_len = strlen(name);
+
+- if (!fi->i_xattr_nid)
+- return -ENODATA;
+-
+- page = get_node_page(sbi, fi->i_xattr_nid);
+- base_addr = page_address(page);
++ base_addr = read_all_xattrs(inode, NULL);
++ if (!base_addr)
++ return -ENOMEM;
+
+- list_for_each_xattr(entry, base_addr) {
+- if (entry->e_name_index != name_index)
+- continue;
+- if (entry->e_name_len != name_len)
+- continue;
+- if (!memcmp(entry->e_name, name, name_len)) {
+- found = 1;
+- break;
+- }
+- }
+- if (!found) {
++ entry = __find_xattr(base_addr, name_index, name_len, name);
++ if (IS_XATTR_LAST_ENTRY(entry)) {
+ error = -ENODATA;
+ goto cleanup;
+ }
+@@ -249,26 +431,21 @@
+ error = value_len;
+
+ cleanup:
+- f2fs_put_page(page, 1);
++ kzfree(base_addr);
+ return error;
+ }
+
+ ssize_t f2fs_listxattr(struct dentry *dentry, char *buffer, size_t buffer_size)
+ {
+ struct inode *inode = dentry->d_inode;
+- struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+- struct f2fs_inode_info *fi = F2FS_I(inode);
+ struct f2fs_xattr_entry *entry;
+- struct page *page;
+ void *base_addr;
+ int error = 0;
+ size_t rest = buffer_size;
+
+- if (!fi->i_xattr_nid)
+- return 0;
+-
+- page = get_node_page(sbi, fi->i_xattr_nid);
+- base_addr = page_address(page);
++ base_addr = read_all_xattrs(inode, NULL);
++ if (!base_addr)
++ return -ENOMEM;
+
+ list_for_each_xattr(entry, base_addr) {
+ const struct xattr_handler *handler =
+@@ -291,23 +468,21 @@
+ }
+ error = buffer_size - rest;
+ cleanup:
+- f2fs_put_page(page, 1);
++ kzfree(base_addr);
+ return error;
+ }
+
+-int f2fs_setxattr(struct inode *inode, int name_index, const char *name,
+- const void *value, size_t value_len)
++static int __f2fs_setxattr(struct inode *inode, int name_index,
++ const char *name, const void *value, size_t value_len,
++ struct page *ipage)
+ {
+- struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
+ struct f2fs_inode_info *fi = F2FS_I(inode);
+- struct f2fs_xattr_header *header = NULL;
+ struct f2fs_xattr_entry *here, *last;
+- struct page *page;
+ void *base_addr;
+- int error, found, free, newsize;
++ int found, newsize;
+ size_t name_len;
+- char *pval;
+- int ilock;
++ __u32 new_hsize;
++ int error = -ENOMEM;
+
+ if (name == NULL)
+ return -EINVAL;
+@@ -317,67 +492,17 @@
+
+ name_len = strlen(name);
+
+- if (name_len > F2FS_NAME_LEN || value_len > MAX_VALUE_LEN)
++ if (name_len > F2FS_NAME_LEN || value_len > MAX_VALUE_LEN(inode))
+ return -ERANGE;
+
+- f2fs_balance_fs(sbi);
+-
+- ilock = mutex_lock_op(sbi);
+-
+- if (!fi->i_xattr_nid) {
+- /* Allocate new attribute block */
+- struct dnode_of_data dn;
+-
+- if (!alloc_nid(sbi, &fi->i_xattr_nid)) {
+- error = -ENOSPC;
+- goto exit;
+- }
+- set_new_dnode(&dn, inode, NULL, NULL, fi->i_xattr_nid);
+- mark_inode_dirty(inode);
+-
+- page = new_node_page(&dn, XATTR_NODE_OFFSET);
+- if (IS_ERR(page)) {
+- alloc_nid_failed(sbi, fi->i_xattr_nid);
+- fi->i_xattr_nid = 0;
+- error = PTR_ERR(page);
+- goto exit;
+- }
+-
+- alloc_nid_done(sbi, fi->i_xattr_nid);
+- base_addr = page_address(page);
+- header = XATTR_HDR(base_addr);
+- header->h_magic = cpu_to_le32(F2FS_XATTR_MAGIC);
+- header->h_refcount = cpu_to_le32(1);
+- } else {
+- /* The inode already has an extended attribute block. */
+- page = get_node_page(sbi, fi->i_xattr_nid);
+- if (IS_ERR(page)) {
+- error = PTR_ERR(page);
+- goto exit;
+- }
+-
+- base_addr = page_address(page);
+- header = XATTR_HDR(base_addr);
+- }
+-
+- if (le32_to_cpu(header->h_magic) != F2FS_XATTR_MAGIC) {
+- error = -EIO;
+- goto cleanup;
+- }
++ base_addr = read_all_xattrs(inode, ipage);
++ if (!base_addr)
++ goto exit;
+
+ /* find entry with wanted name. */
+- found = 0;
+- list_for_each_xattr(here, base_addr) {
+- if (here->e_name_index != name_index)
+- continue;
+- if (here->e_name_len != name_len)
+- continue;
+- if (!memcmp(here->e_name, name, name_len)) {
+- found = 1;
+- break;
+- }
+- }
++ here = __find_xattr(base_addr, name_index, name_len, name);
+
++ found = IS_XATTR_LAST_ENTRY(here) ? 0 : 1;
+ last = here;
+
+ while (!IS_XATTR_LAST_ENTRY(last))
+@@ -388,22 +513,25 @@
+
+ /* 1. Check space */
+ if (value) {
+- /* If value is NULL, it is remove operation.
++ int free;
++ /*
++ * If value is NULL, it is remove operation.
+ * In case of update operation, we caculate free.
+ */
+- free = MIN_OFFSET - ((char *)last - (char *)header);
++ free = MIN_OFFSET(inode) - ((char *)last - (char *)base_addr);
+ if (found)
+- free = free - ENTRY_SIZE(here);
++ free = free + ENTRY_SIZE(here);
+
+ if (free < newsize) {
+ error = -ENOSPC;
+- goto cleanup;
++ goto exit;
+ }
+ }
+
+ /* 2. Remove old entry */
+ if (found) {
+- /* If entry is found, remove old entry.
++ /*
++ * If entry is found, remove old entry.
+ * If not found, remove operation is not needed.
+ */
+ struct f2fs_xattr_entry *next = XATTR_NEXT_ENTRY(here);
+@@ -414,10 +542,15 @@
+ memset(last, 0, oldsize);
+ }
+
++ new_hsize = (char *)last - (char *)base_addr;
++
+ /* 3. Write new entry */
+ if (value) {
+- /* Before we come here, old entry is removed.
+- * We just write new entry. */
++ char *pval;
++ /*
++ * Before we come here, old entry is removed.
++ * We just write new entry.
++ */
+ memset(last, 0, newsize);
+ last->e_name_index = name_index;
+ last->e_name_len = name_len;
+@@ -425,23 +558,39 @@
+ pval = last->e_name + name_len;
+ memcpy(pval, value, value_len);
+ last->e_value_size = cpu_to_le16(value_len);
++ new_hsize += newsize;
+ }
+
+- set_page_dirty(page);
+- f2fs_put_page(page, 1);
++ error = write_all_xattrs(inode, new_hsize, base_addr, ipage);
++ if (error)
++ goto exit;
+
+ if (is_inode_flag_set(fi, FI_ACL_MODE)) {
+ inode->i_mode = fi->i_acl_mode;
+ inode->i_ctime = CURRENT_TIME;
+ clear_inode_flag(fi, FI_ACL_MODE);
+ }
+- update_inode_page(inode);
+- mutex_unlock_op(sbi, ilock);
+
+- return 0;
+-cleanup:
+- f2fs_put_page(page, 1);
++ if (ipage)
++ update_inode(inode, ipage);
++ else
++ update_inode_page(inode);
+ exit:
+- mutex_unlock_op(sbi, ilock);
++ kzfree(base_addr);
+ return error;
+ }
++
++int f2fs_setxattr(struct inode *inode, int name_index, const char *name,
++ const void *value, size_t value_len, struct page *ipage)
++{
++ struct f2fs_sb_info *sbi = F2FS_SB(inode->i_sb);
++ int err;
++
++ f2fs_balance_fs(sbi);
++
++ f2fs_lock_op(sbi);
++ err = __f2fs_setxattr(inode, name_index, name, value, value_len, ipage);
++ f2fs_unlock_op(sbi);
++
++ return err;
++}
+diff -Nur linux-3.10.30.orig/fs/f2fs/xattr.h linux-linaro-stable-mx6/fs/f2fs/xattr.h
+--- linux-3.10.30.orig/fs/f2fs/xattr.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/f2fs/xattr.h 2014-05-15 20:34:12.474118156 +0200
+@@ -51,7 +51,7 @@
+
+ #define XATTR_HDR(ptr) ((struct f2fs_xattr_header *)(ptr))
+ #define XATTR_ENTRY(ptr) ((struct f2fs_xattr_entry *)(ptr))
+-#define XATTR_FIRST_ENTRY(ptr) (XATTR_ENTRY(XATTR_HDR(ptr)+1))
++#define XATTR_FIRST_ENTRY(ptr) (XATTR_ENTRY(XATTR_HDR(ptr) + 1))
+ #define XATTR_ROUND (3)
+
+ #define XATTR_ALIGN(size) ((size + XATTR_ROUND) & ~XATTR_ROUND)
+@@ -69,17 +69,16 @@
+ !IS_XATTR_LAST_ENTRY(entry);\
+ entry = XATTR_NEXT_ENTRY(entry))
+
++#define MIN_OFFSET(i) XATTR_ALIGN(inline_xattr_size(i) + PAGE_SIZE - \
++ sizeof(struct node_footer) - sizeof(__u32))
+
+-#define MIN_OFFSET XATTR_ALIGN(PAGE_SIZE - \
+- sizeof(struct node_footer) - \
+- sizeof(__u32))
+-
+-#define MAX_VALUE_LEN (MIN_OFFSET - sizeof(struct f2fs_xattr_header) - \
+- sizeof(struct f2fs_xattr_entry))
++#define MAX_VALUE_LEN(i) (MIN_OFFSET(i) - \
++ sizeof(struct f2fs_xattr_header) - \
++ sizeof(struct f2fs_xattr_entry))
+
+ /*
+ * On-disk structure of f2fs_xattr
+- * We use only 1 block for xattr.
++ * We use inline xattrs space + 1 block for xattr.
+ *
+ * +--------------------+
+ * | f2fs_xattr_header |
+@@ -112,21 +111,19 @@
+ extern const struct xattr_handler f2fs_xattr_acl_access_handler;
+ extern const struct xattr_handler f2fs_xattr_acl_default_handler;
+ extern const struct xattr_handler f2fs_xattr_advise_handler;
++extern const struct xattr_handler f2fs_xattr_security_handler;
+
+ extern const struct xattr_handler *f2fs_xattr_handlers[];
+
+-extern int f2fs_setxattr(struct inode *inode, int name_index, const char *name,
+- const void *value, size_t value_len);
+-extern int f2fs_getxattr(struct inode *inode, int name_index, const char *name,
+- void *buffer, size_t buffer_size);
+-extern ssize_t f2fs_listxattr(struct dentry *dentry, char *buffer,
+- size_t buffer_size);
+-
++extern int f2fs_setxattr(struct inode *, int, const char *,
++ const void *, size_t, struct page *);
++extern int f2fs_getxattr(struct inode *, int, const char *, void *, size_t);
++extern ssize_t f2fs_listxattr(struct dentry *, char *, size_t);
+ #else
+
+ #define f2fs_xattr_handlers NULL
+ static inline int f2fs_setxattr(struct inode *inode, int name_index,
+- const char *name, const void *value, size_t value_len)
++ const char *name, const void *value, size_t value_len)
+ {
+ return -EOPNOTSUPP;
+ }
+@@ -142,4 +139,14 @@
+ }
+ #endif
+
++#ifdef CONFIG_F2FS_FS_SECURITY
++extern int f2fs_init_security(struct inode *, struct inode *,
++ const struct qstr *, struct page *);
++#else
++static inline int f2fs_init_security(struct inode *inode, struct inode *dir,
++ const struct qstr *qstr, struct page *ipage)
++{
++ return 0;
++}
++#endif
+ #endif /* __F2FS_XATTR_H__ */
+diff -Nur linux-3.10.30.orig/fs/jffs2/fs.c linux-linaro-stable-mx6/fs/jffs2/fs.c
+--- linux-3.10.30.orig/fs/jffs2/fs.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/fs/jffs2/fs.c 2014-05-15 20:34:12.782120374 +0200
+@@ -515,6 +515,10 @@
+
+ c = JFFS2_SB_INFO(sb);
+
++ /* Do not support the MLC nand */
++ if (c->mtd->type == MTD_MLCNANDFLASH)
++ return -EINVAL;
++
+ #ifndef CONFIG_JFFS2_FS_WRITEBUFFER
+ if (c->mtd->type == MTD_NANDFLASH) {
+ pr_err("Cannot operate on NAND flash unless jffs2 NAND support is compiled in\n");
+diff -Nur linux-3.10.30.orig/include/asm-generic/gpio.h linux-linaro-stable-mx6/include/asm-generic/gpio.h
+--- linux-3.10.30.orig/include/asm-generic/gpio.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/asm-generic/gpio.h 2014-05-15 20:34:13.914128527 +0200
+@@ -10,6 +10,8 @@
+ #ifdef CONFIG_GPIOLIB
+
+ #include <linux/compiler.h>
++#include <linux/gpio/driver.h>
++#include <linux/gpio/consumer.h>
+
+ /* Platforms may implement their GPIO interface with library code,
+ * at a small performance cost for non-inlined operations and some
+@@ -49,122 +51,11 @@
+ struct device_node;
+ struct gpio_desc;
+
+-/**
+- * struct gpio_chip - abstract a GPIO controller
+- * @label: for diagnostics
+- * @dev: optional device providing the GPIOs
+- * @owner: helps prevent removal of modules exporting active GPIOs
+- * @list: links gpio_chips together for traversal
+- * @request: optional hook for chip-specific activation, such as
+- * enabling module power and clock; may sleep
+- * @free: optional hook for chip-specific deactivation, such as
+- * disabling module power and clock; may sleep
+- * @get_direction: returns direction for signal "offset", 0=out, 1=in,
+- * (same as GPIOF_DIR_XXX), or negative error
+- * @direction_input: configures signal "offset" as input, or returns error
+- * @get: returns value for signal "offset"; for output signals this
+- * returns either the value actually sensed, or zero
+- * @direction_output: configures signal "offset" as output, or returns error
+- * @set_debounce: optional hook for setting debounce time for specified gpio in
+- * interrupt triggered gpio chips
+- * @set: assigns output value for signal "offset"
+- * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
+- * implementation may not sleep
+- * @dbg_show: optional routine to show contents in debugfs; default code
+- * will be used when this is omitted, but custom code can show extra
+- * state (such as pullup/pulldown configuration).
+- * @base: identifies the first GPIO number handled by this chip; or, if
+- * negative during registration, requests dynamic ID allocation.
+- * @ngpio: the number of GPIOs handled by this controller; the last GPIO
+- * handled is (base + ngpio - 1).
+- * @desc: array of ngpio descriptors. Private.
+- * @can_sleep: flag must be set iff get()/set() methods sleep, as they
+- * must while accessing GPIO expander chips over I2C or SPI
+- * @names: if set, must be an array of strings to use as alternative
+- * names for the GPIOs in this chip. Any entry in the array
+- * may be NULL if there is no alias for the GPIO, however the
+- * array must be @ngpio entries long. A name can include a single printk
+- * format specifier for an unsigned int. It is substituted by the actual
+- * number of the gpio.
+- *
+- * A gpio_chip can help platforms abstract various sources of GPIOs so
+- * they can all be accessed through a common programing interface.
+- * Example sources would be SOC controllers, FPGAs, multifunction
+- * chips, dedicated GPIO expanders, and so on.
+- *
+- * Each chip controls a number of signals, identified in method calls
+- * by "offset" values in the range 0..(@ngpio - 1). When those signals
+- * are referenced through calls like gpio_get_value(gpio), the offset
+- * is calculated by subtracting @base from the gpio number.
+- */
+-struct gpio_chip {
+- const char *label;
+- struct device *dev;
+- struct module *owner;
+- struct list_head list;
+-
+- int (*request)(struct gpio_chip *chip,
+- unsigned offset);
+- void (*free)(struct gpio_chip *chip,
+- unsigned offset);
+- int (*get_direction)(struct gpio_chip *chip,
+- unsigned offset);
+- int (*direction_input)(struct gpio_chip *chip,
+- unsigned offset);
+- int (*get)(struct gpio_chip *chip,
+- unsigned offset);
+- int (*direction_output)(struct gpio_chip *chip,
+- unsigned offset, int value);
+- int (*set_debounce)(struct gpio_chip *chip,
+- unsigned offset, unsigned debounce);
+-
+- void (*set)(struct gpio_chip *chip,
+- unsigned offset, int value);
+-
+- int (*to_irq)(struct gpio_chip *chip,
+- unsigned offset);
+-
+- void (*dbg_show)(struct seq_file *s,
+- struct gpio_chip *chip);
+- int base;
+- u16 ngpio;
+- struct gpio_desc *desc;
+- const char *const *names;
+- unsigned can_sleep:1;
+- unsigned exported:1;
+-
+-#if defined(CONFIG_OF_GPIO)
+- /*
+- * If CONFIG_OF is enabled, then all GPIO controllers described in the
+- * device tree automatically may have an OF translation
+- */
+- struct device_node *of_node;
+- int of_gpio_n_cells;
+- int (*of_xlate)(struct gpio_chip *gc,
+- const struct of_phandle_args *gpiospec, u32 *flags);
+-#endif
+-#ifdef CONFIG_PINCTRL
+- /*
+- * If CONFIG_PINCTRL is enabled, then gpio controllers can optionally
+- * describe the actual pin range which they serve in an SoC. This
+- * information would be used by pinctrl subsystem to configure
+- * corresponding pins for gpio usage.
+- */
+- struct list_head pin_ranges;
+-#endif
+-};
+-
+-extern const char *gpiochip_is_requested(struct gpio_chip *chip,
+- unsigned offset);
+-extern struct gpio_chip *gpio_to_chip(unsigned gpio);
+-
+-/* add/remove chips */
+-extern int gpiochip_add(struct gpio_chip *chip);
+-extern int __must_check gpiochip_remove(struct gpio_chip *chip);
+-extern struct gpio_chip *gpiochip_find(void *data,
+- int (*match)(struct gpio_chip *chip,
+- void *data));
+-
++/* caller holds gpio_lock *OR* gpio is marked as requested */
++static inline struct gpio_chip *gpio_to_chip(unsigned gpio)
++{
++ return gpiod_to_chip(gpio_to_desc(gpio));
++}
+
+ /* Always use the library code for GPIO management calls,
+ * or when sleeping may be involved.
+@@ -172,43 +63,84 @@
+ extern int gpio_request(unsigned gpio, const char *label);
+ extern void gpio_free(unsigned gpio);
+
+-extern int gpio_direction_input(unsigned gpio);
+-extern int gpio_direction_output(unsigned gpio, int value);
++static inline int gpio_direction_input(unsigned gpio)
++{
++ return gpiod_direction_input(gpio_to_desc(gpio));
++}
++static inline int gpio_direction_output(unsigned gpio, int value)
++{
++ return gpiod_direction_output(gpio_to_desc(gpio), value);
++}
+
+-extern int gpio_set_debounce(unsigned gpio, unsigned debounce);
++static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
++{
++ return gpiod_set_debounce(gpio_to_desc(gpio), debounce);
++}
+
+-extern int gpio_get_value_cansleep(unsigned gpio);
+-extern void gpio_set_value_cansleep(unsigned gpio, int value);
++static inline int gpio_get_value_cansleep(unsigned gpio)
++{
++ return gpiod_get_raw_value_cansleep(gpio_to_desc(gpio));
++}
++static inline void gpio_set_value_cansleep(unsigned gpio, int value)
++{
++ return gpiod_set_raw_value_cansleep(gpio_to_desc(gpio), value);
++}
+
+
+ /* A platform's <asm/gpio.h> code may want to inline the I/O calls when
+ * the GPIO is constant and refers to some always-present controller,
+ * giving direct access to chip registers and tight bitbanging loops.
+ */
+-extern int __gpio_get_value(unsigned gpio);
+-extern void __gpio_set_value(unsigned gpio, int value);
++static inline int __gpio_get_value(unsigned gpio)
++{
++ return gpiod_get_raw_value(gpio_to_desc(gpio));
++}
++static inline void __gpio_set_value(unsigned gpio, int value)
++{
++ return gpiod_set_raw_value(gpio_to_desc(gpio), value);
++}
++
++static inline int __gpio_cansleep(unsigned gpio)
++{
++ return gpiod_cansleep(gpio_to_desc(gpio));
++}
+
+-extern int __gpio_cansleep(unsigned gpio);
++static inline int __gpio_to_irq(unsigned gpio)
++{
++ return gpiod_to_irq(gpio_to_desc(gpio));
++}
+
+-extern int __gpio_to_irq(unsigned gpio);
++extern int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
++extern void gpio_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
+
+ extern int gpio_request_one(unsigned gpio, unsigned long flags, const char *label);
+ extern int gpio_request_array(const struct gpio *array, size_t num);
+ extern void gpio_free_array(const struct gpio *array, size_t num);
+
+-#ifdef CONFIG_GPIO_SYSFS
+-
+ /*
+ * A sysfs interface can be exported by individual drivers if they want,
+ * but more typically is configured entirely from userspace.
+ */
+-extern int gpio_export(unsigned gpio, bool direction_may_change);
+-extern int gpio_export_link(struct device *dev, const char *name,
+- unsigned gpio);
+-extern int gpio_sysfs_set_active_low(unsigned gpio, int value);
+-extern void gpio_unexport(unsigned gpio);
++static inline int gpio_export(unsigned gpio, bool direction_may_change)
++{
++ return gpiod_export(gpio_to_desc(gpio), direction_may_change);
++}
+
+-#endif /* CONFIG_GPIO_SYSFS */
++static inline int gpio_export_link(struct device *dev, const char *name,
++ unsigned gpio)
++{
++ return gpiod_export_link(dev, name, gpio_to_desc(gpio));
++}
++
++static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
++{
++ return gpiod_sysfs_set_active_low(gpio_to_desc(gpio), value);
++}
++
++static inline void gpio_unexport(unsigned gpio)
++{
++ gpiod_unexport(gpio_to_desc(gpio));
++}
+
+ #ifdef CONFIG_PINCTRL
+
+@@ -278,31 +210,4 @@
+
+ #endif /* !CONFIG_GPIOLIB */
+
+-#ifndef CONFIG_GPIO_SYSFS
+-
+-struct device;
+-
+-/* sysfs support is only available with gpiolib, where it's optional */
+-
+-static inline int gpio_export(unsigned gpio, bool direction_may_change)
+-{
+- return -ENOSYS;
+-}
+-
+-static inline int gpio_export_link(struct device *dev, const char *name,
+- unsigned gpio)
+-{
+- return -ENOSYS;
+-}
+-
+-static inline int gpio_sysfs_set_active_low(unsigned gpio, int value)
+-{
+- return -ENOSYS;
+-}
+-
+-static inline void gpio_unexport(unsigned gpio)
+-{
+-}
+-#endif /* CONFIG_GPIO_SYSFS */
+-
+ #endif /* _ASM_GENERIC_GPIO_H */
+diff -Nur linux-3.10.30.orig/include/drm/drm_crtc_helper.h linux-linaro-stable-mx6/include/drm/drm_crtc_helper.h
+--- linux-3.10.30.orig/include/drm/drm_crtc_helper.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/drm/drm_crtc_helper.h 2014-05-15 20:34:13.990129074 +0200
+@@ -127,6 +127,7 @@
+
+ extern int drm_helper_probe_single_connector_modes(struct drm_connector *connector, uint32_t maxX, uint32_t maxY);
+ extern void drm_helper_disable_unused_functions(struct drm_device *dev);
++extern uint32_t drm_helper_crtc_possible_mask(struct drm_crtc *crtc);
+ extern int drm_crtc_helper_set_config(struct drm_mode_set *set);
+ extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+diff -Nur linux-3.10.30.orig/include/dt-bindings/clock/imx6sl-clock.h linux-linaro-stable-mx6/include/dt-bindings/clock/imx6sl-clock.h
+--- linux-3.10.30.orig/include/dt-bindings/clock/imx6sl-clock.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/dt-bindings/clock/imx6sl-clock.h 2014-05-15 20:34:14.046129478 +0200
+@@ -0,0 +1,152 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_IMX6SL_H
++#define __DT_BINDINGS_CLOCK_IMX6SL_H
++
++#define IMX6SL_CLK_DUMMY 0
++#define IMX6SL_CLK_CKIL 1
++#define IMX6SL_CLK_OSC 2
++#define IMX6SL_CLK_PLL1_SYS 3
++#define IMX6SL_CLK_PLL2_BUS 4
++#define IMX6SL_CLK_PLL3_USB_OTG 5
++#define IMX6SL_CLK_PLL4_AUDIO 6
++#define IMX6SL_CLK_PLL5_VIDEO 7
++#define IMX6SL_CLK_PLL6_ENET 8
++#define IMX6SL_CLK_PLL7_USB_HOST 9
++#define IMX6SL_CLK_USBPHY1 10
++#define IMX6SL_CLK_USBPHY2 11
++#define IMX6SL_CLK_USBPHY1_GATE 12
++#define IMX6SL_CLK_USBPHY2_GATE 13
++#define IMX6SL_CLK_PLL4_POST_DIV 14
++#define IMX6SL_CLK_PLL5_POST_DIV 15
++#define IMX6SL_CLK_PLL5_VIDEO_DIV 16
++#define IMX6SL_CLK_ENET_REF 17
++#define IMX6SL_CLK_PLL2_PFD0 18
++#define IMX6SL_CLK_PLL2_PFD1 19
++#define IMX6SL_CLK_PLL2_PFD2 20
++#define IMX6SL_CLK_PLL3_PFD0 21
++#define IMX6SL_CLK_PLL3_PFD1 22
++#define IMX6SL_CLK_PLL3_PFD2 23
++#define IMX6SL_CLK_PLL3_PFD3 24
++#define IMX6SL_CLK_PLL2_198M 25
++#define IMX6SL_CLK_PLL3_120M 26
++#define IMX6SL_CLK_PLL3_80M 27
++#define IMX6SL_CLK_PLL3_60M 28
++#define IMX6SL_CLK_STEP 29
++#define IMX6SL_CLK_PLL1_SW 30
++#define IMX6SL_CLK_OCRAM_ALT_SEL 31
++#define IMX6SL_CLK_OCRAM_SEL 32
++#define IMX6SL_CLK_PRE_PERIPH2_SEL 33
++#define IMX6SL_CLK_PRE_PERIPH_SEL 34
++#define IMX6SL_CLK_PERIPH2_CLK2_SEL 35
++#define IMX6SL_CLK_PERIPH_CLK2_SEL 36
++#define IMX6SL_CLK_CSI_SEL 37
++#define IMX6SL_CLK_LCDIF_AXI_SEL 38
++#define IMX6SL_CLK_USDHC1_SEL 39
++#define IMX6SL_CLK_USDHC2_SEL 40
++#define IMX6SL_CLK_USDHC3_SEL 41
++#define IMX6SL_CLK_USDHC4_SEL 42
++#define IMX6SL_CLK_SSI1_SEL 43
++#define IMX6SL_CLK_SSI2_SEL 44
++#define IMX6SL_CLK_SSI3_SEL 45
++#define IMX6SL_CLK_PERCLK_SEL 46
++#define IMX6SL_CLK_PXP_AXI_SEL 47
++#define IMX6SL_CLK_EPDC_AXI_SEL 48
++#define IMX6SL_CLK_GPU2D_OVG_SEL 49
++#define IMX6SL_CLK_GPU2D_SEL 50
++#define IMX6SL_CLK_LCDIF_PIX_SEL 51
++#define IMX6SL_CLK_EPDC_PIX_SEL 52
++#define IMX6SL_CLK_SPDIF0_SEL 53
++#define IMX6SL_CLK_SPDIF1_SEL 54
++#define IMX6SL_CLK_EXTERN_AUDIO_SEL 55
++#define IMX6SL_CLK_ECSPI_SEL 56
++#define IMX6SL_CLK_UART_SEL 57
++#define IMX6SL_CLK_PERIPH 58
++#define IMX6SL_CLK_PERIPH2 59
++#define IMX6SL_CLK_OCRAM_PODF 60
++#define IMX6SL_CLK_PERIPH_CLK2 61
++#define IMX6SL_CLK_PERIPH2_CLK2 62
++#define IMX6SL_CLK_IPG 63
++#define IMX6SL_CLK_CSI_PODF 64
++#define IMX6SL_CLK_LCDIF_AXI_PODF 65
++#define IMX6SL_CLK_USDHC1_PODF 66
++#define IMX6SL_CLK_USDHC2_PODF 67
++#define IMX6SL_CLK_USDHC3_PODF 68
++#define IMX6SL_CLK_USDHC4_PODF 69
++#define IMX6SL_CLK_SSI1_PRED 70
++#define IMX6SL_CLK_SSI1_PODF 71
++#define IMX6SL_CLK_SSI2_PRED 72
++#define IMX6SL_CLK_SSI2_PODF 73
++#define IMX6SL_CLK_SSI3_PRED 74
++#define IMX6SL_CLK_SSI3_PODF 75
++#define IMX6SL_CLK_PERCLK 76
++#define IMX6SL_CLK_PXP_AXI_PODF 77
++#define IMX6SL_CLK_EPDC_AXI_PODF 78
++#define IMX6SL_CLK_GPU2D_OVG_PODF 79
++#define IMX6SL_CLK_GPU2D_PODF 80
++#define IMX6SL_CLK_LCDIF_PIX_PRED 81
++#define IMX6SL_CLK_EPDC_PIX_PRED 82
++#define IMX6SL_CLK_LCDIF_PIX_PODF 83
++#define IMX6SL_CLK_EPDC_PIX_PODF 84
++#define IMX6SL_CLK_SPDIF0_PRED 85
++#define IMX6SL_CLK_SPDIF0_PODF 86
++#define IMX6SL_CLK_SPDIF1_PRED 87
++#define IMX6SL_CLK_SPDIF1_PODF 88
++#define IMX6SL_CLK_EXTERN_AUDIO_PRED 89
++#define IMX6SL_CLK_EXTERN_AUDIO_PODF 90
++#define IMX6SL_CLK_ECSPI_ROOT 91
++#define IMX6SL_CLK_UART_ROOT 92
++#define IMX6SL_CLK_AHB 93
++#define IMX6SL_CLK_MMDC_ROOT 94
++#define IMX6SL_CLK_ARM 95
++#define IMX6SL_CLK_ECSPI1 96
++#define IMX6SL_CLK_ECSPI2 97
++#define IMX6SL_CLK_ECSPI3 98
++#define IMX6SL_CLK_ECSPI4 99
++#define IMX6SL_CLK_EPIT1 100
++#define IMX6SL_CLK_EPIT2 101
++#define IMX6SL_CLK_EXTERN_AUDIO 102
++#define IMX6SL_CLK_GPT 103
++#define IMX6SL_CLK_GPT_SERIAL 104
++#define IMX6SL_CLK_GPU2D_OVG 105
++#define IMX6SL_CLK_I2C1 106
++#define IMX6SL_CLK_I2C2 107
++#define IMX6SL_CLK_I2C3 108
++#define IMX6SL_CLK_OCOTP 109
++#define IMX6SL_CLK_CSI 110
++#define IMX6SL_CLK_PXP_AXI 111
++#define IMX6SL_CLK_EPDC_AXI 112
++#define IMX6SL_CLK_LCDIF_AXI 113
++#define IMX6SL_CLK_LCDIF_PIX 114
++#define IMX6SL_CLK_EPDC_PIX 115
++#define IMX6SL_CLK_OCRAM 116
++#define IMX6SL_CLK_PWM1 117
++#define IMX6SL_CLK_PWM2 118
++#define IMX6SL_CLK_PWM3 119
++#define IMX6SL_CLK_PWM4 120
++#define IMX6SL_CLK_SDMA 121
++#define IMX6SL_CLK_SPDIF 122
++#define IMX6SL_CLK_SSI1 123
++#define IMX6SL_CLK_SSI2 124
++#define IMX6SL_CLK_SSI3 125
++#define IMX6SL_CLK_UART 126
++#define IMX6SL_CLK_UART_SERIAL 127
++#define IMX6SL_CLK_USBOH3 128
++#define IMX6SL_CLK_USDHC1 129
++#define IMX6SL_CLK_USDHC2 130
++#define IMX6SL_CLK_USDHC3 131
++#define IMX6SL_CLK_USDHC4 132
++#define IMX6SL_CLK_PLL4_AUDIO_DIV 133
++#define IMX6SL_CLK_ENET 134
++#define IMX6SL_CLK_UART_OSC_4M 135
++#define IMX6SL_CLK_SPBA 136
++#define IMX6SL_CLK_CLK_END 137
++
++#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
+diff -Nur linux-3.10.30.orig/include/dt-bindings/clock/vf610-clock.h linux-linaro-stable-mx6/include/dt-bindings/clock/vf610-clock.h
+--- linux-3.10.30.orig/include/dt-bindings/clock/vf610-clock.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/dt-bindings/clock/vf610-clock.h 2014-05-15 20:34:14.046129478 +0200
+@@ -0,0 +1,165 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_VF610_H
++#define __DT_BINDINGS_CLOCK_VF610_H
++
++#define VF610_CLK_DUMMY 0
++#define VF610_CLK_SIRC_128K 1
++#define VF610_CLK_SIRC_32K 2
++#define VF610_CLK_FIRC 3
++#define VF610_CLK_SXOSC 4
++#define VF610_CLK_FXOSC 5
++#define VF610_CLK_FXOSC_HALF 6
++#define VF610_CLK_SLOW_CLK_SEL 7
++#define VF610_CLK_FASK_CLK_SEL 8
++#define VF610_CLK_AUDIO_EXT 9
++#define VF610_CLK_ENET_EXT 10
++#define VF610_CLK_PLL1_MAIN 11
++#define VF610_CLK_PLL1_PFD1 12
++#define VF610_CLK_PLL1_PFD2 13
++#define VF610_CLK_PLL1_PFD3 14
++#define VF610_CLK_PLL1_PFD4 15
++#define VF610_CLK_PLL2_MAIN 16
++#define VF610_CLK_PLL2_PFD1 17
++#define VF610_CLK_PLL2_PFD2 18
++#define VF610_CLK_PLL2_PFD3 19
++#define VF610_CLK_PLL2_PFD4 20
++#define VF610_CLK_PLL3_MAIN 21
++#define VF610_CLK_PLL3_PFD1 22
++#define VF610_CLK_PLL3_PFD2 23
++#define VF610_CLK_PLL3_PFD3 24
++#define VF610_CLK_PLL3_PFD4 25
++#define VF610_CLK_PLL4_MAIN 26
++#define VF610_CLK_PLL5_MAIN 27
++#define VF610_CLK_PLL6_MAIN 28
++#define VF610_CLK_PLL3_MAIN_DIV 29
++#define VF610_CLK_PLL4_MAIN_DIV 30
++#define VF610_CLK_PLL6_MAIN_DIV 31
++#define VF610_CLK_PLL1_PFD_SEL 32
++#define VF610_CLK_PLL2_PFD_SEL 33
++#define VF610_CLK_SYS_SEL 34
++#define VF610_CLK_DDR_SEL 35
++#define VF610_CLK_SYS_BUS 36
++#define VF610_CLK_PLATFORM_BUS 37
++#define VF610_CLK_IPG_BUS 38
++#define VF610_CLK_UART0 39
++#define VF610_CLK_UART1 40
++#define VF610_CLK_UART2 41
++#define VF610_CLK_UART3 42
++#define VF610_CLK_UART4 43
++#define VF610_CLK_UART5 44
++#define VF610_CLK_PIT 45
++#define VF610_CLK_I2C0 46
++#define VF610_CLK_I2C1 47
++#define VF610_CLK_I2C2 48
++#define VF610_CLK_I2C3 49
++#define VF610_CLK_FTM0_EXT_SEL 50
++#define VF610_CLK_FTM0_FIX_SEL 51
++#define VF610_CLK_FTM0_EXT_FIX_EN 52
++#define VF610_CLK_FTM1_EXT_SEL 53
++#define VF610_CLK_FTM1_FIX_SEL 54
++#define VF610_CLK_FTM1_EXT_FIX_EN 55
++#define VF610_CLK_FTM2_EXT_SEL 56
++#define VF610_CLK_FTM2_FIX_SEL 57
++#define VF610_CLK_FTM2_EXT_FIX_EN 58
++#define VF610_CLK_FTM3_EXT_SEL 59
++#define VF610_CLK_FTM3_FIX_SEL 60
++#define VF610_CLK_FTM3_EXT_FIX_EN 61
++#define VF610_CLK_FTM0 62
++#define VF610_CLK_FTM1 63
++#define VF610_CLK_FTM2 64
++#define VF610_CLK_FTM3 65
++#define VF610_CLK_ENET_50M 66
++#define VF610_CLK_ENET_25M 67
++#define VF610_CLK_ENET_SEL 68
++#define VF610_CLK_ENET 69
++#define VF610_CLK_ENET_TS_SEL 70
++#define VF610_CLK_ENET_TS 71
++#define VF610_CLK_DSPI0 72
++#define VF610_CLK_DSPI1 73
++#define VF610_CLK_DSPI2 74
++#define VF610_CLK_DSPI3 75
++#define VF610_CLK_WDT 76
++#define VF610_CLK_ESDHC0_SEL 77
++#define VF610_CLK_ESDHC0_EN 78
++#define VF610_CLK_ESDHC0_DIV 79
++#define VF610_CLK_ESDHC0 80
++#define VF610_CLK_ESDHC1_SEL 81
++#define VF610_CLK_ESDHC1_EN 82
++#define VF610_CLK_ESDHC1_DIV 83
++#define VF610_CLK_ESDHC1 84
++#define VF610_CLK_DCU0_SEL 85
++#define VF610_CLK_DCU0_EN 86
++#define VF610_CLK_DCU0_DIV 87
++#define VF610_CLK_DCU0 88
++#define VF610_CLK_DCU1_SEL 89
++#define VF610_CLK_DCU1_EN 90
++#define VF610_CLK_DCU1_DIV 91
++#define VF610_CLK_DCU1 92
++#define VF610_CLK_ESAI_SEL 93
++#define VF610_CLK_ESAI_EN 94
++#define VF610_CLK_ESAI_DIV 95
++#define VF610_CLK_ESAI 96
++#define VF610_CLK_SAI0_SEL 97
++#define VF610_CLK_SAI0_EN 98
++#define VF610_CLK_SAI0_DIV 99
++#define VF610_CLK_SAI0 100
++#define VF610_CLK_SAI1_SEL 101
++#define VF610_CLK_SAI1_EN 102
++#define VF610_CLK_SAI1_DIV 103
++#define VF610_CLK_SAI1 104
++#define VF610_CLK_SAI2_SEL 105
++#define VF610_CLK_SAI2_EN 106
++#define VF610_CLK_SAI2_DIV 107
++#define VF610_CLK_SAI2 108
++#define VF610_CLK_SAI3_SEL 109
++#define VF610_CLK_SAI3_EN 110
++#define VF610_CLK_SAI3_DIV 111
++#define VF610_CLK_SAI3 112
++#define VF610_CLK_USBC0 113
++#define VF610_CLK_USBC1 114
++#define VF610_CLK_QSPI0_SEL 115
++#define VF610_CLK_QSPI0_EN 116
++#define VF610_CLK_QSPI0_X4_DIV 117
++#define VF610_CLK_QSPI0_X2_DIV 118
++#define VF610_CLK_QSPI0_X1_DIV 119
++#define VF610_CLK_QSPI1_SEL 120
++#define VF610_CLK_QSPI1_EN 121
++#define VF610_CLK_QSPI1_X4_DIV 122
++#define VF610_CLK_QSPI1_X2_DIV 123
++#define VF610_CLK_QSPI1_X1_DIV 124
++#define VF610_CLK_QSPI0 125
++#define VF610_CLK_QSPI1 126
++#define VF610_CLK_NFC_SEL 127
++#define VF610_CLK_NFC_EN 128
++#define VF610_CLK_NFC_PRE_DIV 129
++#define VF610_CLK_NFC_FRAC_DIV 130
++#define VF610_CLK_NFC_INV 131
++#define VF610_CLK_NFC 132
++#define VF610_CLK_VADC_SEL 133
++#define VF610_CLK_VADC_EN 134
++#define VF610_CLK_VADC_DIV 135
++#define VF610_CLK_VADC_DIV_HALF 136
++#define VF610_CLK_VADC 137
++#define VF610_CLK_ADC0 138
++#define VF610_CLK_ADC1 139
++#define VF610_CLK_DAC0 140
++#define VF610_CLK_DAC1 141
++#define VF610_CLK_FLEXCAN0 142
++#define VF610_CLK_FLEXCAN1 143
++#define VF610_CLK_ASRC 144
++#define VF610_CLK_GPU_SEL 145
++#define VF610_CLK_GPU_EN 146
++#define VF610_CLK_GPU2D 147
++#define VF610_CLK_ENET0 148
++#define VF610_CLK_ENET1 149
++#define VF610_CLK_END 150
++
++#endif /* __DT_BINDINGS_CLOCK_VF610_H */
+diff -Nur linux-3.10.30.orig/include/linux/arm-cci.h linux-linaro-stable-mx6/include/linux/arm-cci.h
+--- linux-3.10.30.orig/include/linux/arm-cci.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/arm-cci.h 2014-05-15 20:34:14.146130198 +0200
+@@ -0,0 +1,61 @@
++/*
++ * CCI cache coherent interconnect support
++ *
++ * Copyright (C) 2013 ARM Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef __LINUX_ARM_CCI_H
++#define __LINUX_ARM_CCI_H
++
++#include <linux/errno.h>
++#include <linux/types.h>
++
++struct device_node;
++
++#ifdef CONFIG_ARM_CCI
++extern bool cci_probed(void);
++extern int cci_ace_get_port(struct device_node *dn);
++extern int cci_disable_port_by_cpu(u64 mpidr);
++extern int __cci_control_port_by_device(struct device_node *dn, bool enable);
++extern int __cci_control_port_by_index(u32 port, bool enable);
++#else
++static inline bool cci_probed(void) { return false; }
++static inline int cci_ace_get_port(struct device_node *dn)
++{
++ return -ENODEV;
++}
++static inline int cci_disable_port_by_cpu(u64 mpidr) { return -ENODEV; }
++static inline int __cci_control_port_by_device(struct device_node *dn,
++ bool enable)
++{
++ return -ENODEV;
++}
++static inline int __cci_control_port_by_index(u32 port, bool enable)
++{
++ return -ENODEV;
++}
++#endif
++#define cci_disable_port_by_device(dev) \
++ __cci_control_port_by_device(dev, false)
++#define cci_enable_port_by_device(dev) \
++ __cci_control_port_by_device(dev, true)
++#define cci_disable_port_by_index(dev) \
++ __cci_control_port_by_index(dev, false)
++#define cci_enable_port_by_index(dev) \
++ __cci_control_port_by_index(dev, true)
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/arm-hdlcd.h linux-linaro-stable-mx6/include/linux/arm-hdlcd.h
+--- linux-3.10.30.orig/include/linux/arm-hdlcd.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/arm-hdlcd.h 2014-05-15 20:34:14.146130198 +0200
+@@ -0,0 +1,122 @@
++/*
++ * include/linux/arm-hdlcd.h
++ *
++ * Copyright (C) 2011 ARM Limited
++ *
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License. See the file COPYING in the main directory of this archive
++ * for more details.
++ *
++ * ARM HDLCD Controller register definition
++ */
++
++#include <linux/fb.h>
++#include <linux/completion.h>
++
++/* register offsets */
++#define HDLCD_REG_VERSION 0x0000 /* ro */
++#define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
++#define HDLCD_REG_INT_CLEAR 0x0014 /* wo */
++#define HDLCD_REG_INT_MASK 0x0018 /* rw */
++#define HDLCD_REG_INT_STATUS 0x001c /* ro */
++#define HDLCD_REG_USER_OUT 0x0020 /* rw */
++#define HDLCD_REG_FB_BASE 0x0100 /* rw */
++#define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
++#define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
++#define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
++#define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
++#define HDLCD_REG_V_SYNC 0x0200 /* rw */
++#define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
++#define HDLCD_REG_V_DATA 0x0208 /* rw */
++#define HDLCD_REG_V_FRONT_PORCH 0x020c /* rw */
++#define HDLCD_REG_H_SYNC 0x0210 /* rw */
++#define HDLCD_REG_H_BACK_PORCH 0x0214 /* rw */
++#define HDLCD_REG_H_DATA 0x0218 /* rw */
++#define HDLCD_REG_H_FRONT_PORCH 0x021c /* rw */
++#define HDLCD_REG_POLARITIES 0x0220 /* rw */
++#define HDLCD_REG_COMMAND 0x0230 /* rw */
++#define HDLCD_REG_PIXEL_FORMAT 0x0240 /* rw */
++#define HDLCD_REG_BLUE_SELECT 0x0244 /* rw */
++#define HDLCD_REG_GREEN_SELECT 0x0248 /* rw */
++#define HDLCD_REG_RED_SELECT 0x024c /* rw */
++
++/* version */
++#define HDLCD_PRODUCT_ID 0x1CDC0000
++#define HDLCD_PRODUCT_MASK 0xFFFF0000
++#define HDLCD_VERSION_MAJOR_MASK 0x0000FF00
++#define HDLCD_VERSION_MINOR_MASK 0x000000FF
++
++/* interrupts */
++#define HDLCD_INTERRUPT_DMA_END (1 << 0)
++#define HDLCD_INTERRUPT_BUS_ERROR (1 << 1)
++#define HDLCD_INTERRUPT_VSYNC (1 << 2)
++#define HDLCD_INTERRUPT_UNDERRUN (1 << 3)
++
++/* polarity */
++#define HDLCD_POLARITY_VSYNC (1 << 0)
++#define HDLCD_POLARITY_HSYNC (1 << 1)
++#define HDLCD_POLARITY_DATAEN (1 << 2)
++#define HDLCD_POLARITY_DATA (1 << 3)
++#define HDLCD_POLARITY_PIXELCLK (1 << 4)
++
++/* commands */
++#define HDLCD_COMMAND_DISABLE (0 << 0)
++#define HDLCD_COMMAND_ENABLE (1 << 0)
++
++/* pixel format */
++#define HDLCD_PIXEL_FMT_LITTLE_ENDIAN (0 << 31)
++#define HDLCD_PIXEL_FMT_BIG_ENDIAN (1 << 31)
++#define HDLCD_BYTES_PER_PIXEL_MASK (3 << 3)
++
++/* bus options */
++#define HDLCD_BUS_BURST_MASK 0x01f
++#define HDLCD_BUS_MAX_OUTSTAND 0xf00
++#define HDLCD_BUS_BURST_NONE (0 << 0)
++#define HDLCD_BUS_BURST_1 (1 << 0)
++#define HDLCD_BUS_BURST_2 (1 << 1)
++#define HDLCD_BUS_BURST_4 (1 << 2)
++#define HDLCD_BUS_BURST_8 (1 << 3)
++#define HDLCD_BUS_BURST_16 (1 << 4)
++
++/* Max resolution supported is 4096x4096, 8 bit per color component,
++ 8 bit alpha, but we are going to choose the usual hardware default
++ (2048x2048, 32 bpp) and enable double buffering */
++#define HDLCD_MAX_XRES 2048
++#define HDLCD_MAX_YRES 2048
++#define HDLCD_MAX_FRAMEBUFFER_SIZE (HDLCD_MAX_XRES * HDLCD_MAX_YRES << 2)
++
++#define HDLCD_MEM_BASE (CONFIG_PAGE_OFFSET - 0x1000000)
++
++#define NR_PALETTE 256
++
++/* OEMs using HDLCD may wish to enable these settings if
++ * display disruption is apparent and you suspect HDLCD
++ * access to RAM may be starved.
++ */
++/* Turn HDLCD default color red instead of black so
++ * that it's easy to see pixel clock data underruns
++ * (compared to other visual disruption)
++ */
++//#define HDLCD_RED_DEFAULT_COLOUR
++/* Add a counter in the IRQ handler to count buffer underruns
++ * and /proc/hdlcd_underrun to read the counter
++ */
++//#define HDLCD_COUNT_BUFFERUNDERRUNS
++/* Restrict height to 1x screen size
++ *
++ */
++//#define HDLCD_NO_VIRTUAL_SCREEN
++
++#ifdef CONFIG_ANDROID
++#define HDLCD_NO_VIRTUAL_SCREEN
++#endif
++
++struct hdlcd_device {
++ struct fb_info fb;
++ struct device *dev;
++ struct clk *clk;
++ void __iomem *base;
++ int irq;
++ struct completion vsync_completion;
++ unsigned char *edid;
++};
+diff -Nur linux-3.10.30.orig/include/linux/backlight.h linux-linaro-stable-mx6/include/linux/backlight.h
+--- linux-3.10.30.orig/include/linux/backlight.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/backlight.h 2014-05-15 20:34:14.166130342 +0200
+@@ -9,6 +9,7 @@
+ #define _LINUX_BACKLIGHT_H
+
+ #include <linux/device.h>
++#include <linux/fb.h>
+ #include <linux/mutex.h>
+ #include <linux/notifier.h>
+
+@@ -101,6 +102,11 @@
+ struct notifier_block fb_notif;
+
+ struct device dev;
++
++ /* Multiple framebuffers may share one backlight device */
++ bool fb_bl_on[FB_MAX];
++
++ int use_count;
+ };
+
+ static inline void backlight_update_status(struct backlight_device *bd)
+diff -Nur linux-3.10.30.orig/include/linux/busfreq-imx6.h linux-linaro-stable-mx6/include/linux/busfreq-imx6.h
+--- linux-3.10.30.orig/include/linux/busfreq-imx6.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/busfreq-imx6.h 2014-05-15 20:34:14.174130400 +0200
+@@ -0,0 +1,23 @@
++/*
++ * Copyright 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_MXC_BUSFREQ_H__
++#define __ASM_ARCH_MXC_BUSFREQ_H__
++
++/*
++ * This enumerates busfreq mode.
++ */
++enum bus_freq_mode {
++ BUS_FREQ_HIGH,
++ BUS_FREQ_MED,
++ BUS_FREQ_AUDIO,
++ BUS_FREQ_LOW,
++};
++void request_bus_freq(enum bus_freq_mode mode);
++void release_bus_freq(enum bus_freq_mode mode);
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/component.h linux-linaro-stable-mx6/include/linux/component.h
+--- linux-3.10.30.orig/include/linux/component.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/component.h 2014-05-15 20:34:14.222130745 +0200
+@@ -0,0 +1,32 @@
++#ifndef COMPONENT_H
++#define COMPONENT_H
++
++struct device;
++
++struct component_ops {
++ int (*bind)(struct device *, struct device *, void *);
++ void (*unbind)(struct device *, struct device *, void *);
++};
++
++int component_add(struct device *, const struct component_ops *);
++void component_del(struct device *, const struct component_ops *);
++
++int component_bind_all(struct device *, void *);
++void component_unbind_all(struct device *, void *);
++
++struct master;
++
++struct component_master_ops {
++ int (*add_components)(struct device *, struct master *);
++ int (*bind)(struct device *);
++ void (*unbind)(struct device *);
++};
++
++int component_master_add(struct device *, const struct component_master_ops *);
++void component_master_del(struct device *,
++ const struct component_master_ops *);
++
++int component_master_add_child(struct master *master,
++ int (*compare)(struct device *, void *), void *compare_data);
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/cpufreq.h linux-linaro-stable-mx6/include/linux/cpufreq.h
+--- linux-3.10.30.orig/include/linux/cpufreq.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/cpufreq.h 2014-05-15 20:34:14.242130890 +0200
+@@ -393,6 +393,9 @@
+ #elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE)
+ extern struct cpufreq_governor cpufreq_gov_conservative;
+ #define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_conservative)
++#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE)
++extern struct cpufreq_governor cpufreq_gov_interactive;
++#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_interactive)
+ #endif
+
+
+diff -Nur linux-3.10.30.orig/include/linux/cpu.h linux-linaro-stable-mx6/include/linux/cpu.h
+--- linux-3.10.30.orig/include/linux/cpu.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/cpu.h 2014-05-15 20:34:14.242130890 +0200
+@@ -29,6 +29,7 @@
+ extern int register_cpu(struct cpu *cpu, int num);
+ extern struct device *get_cpu_device(unsigned cpu);
+ extern bool cpu_is_hotpluggable(unsigned cpu);
++extern bool arch_match_cpu_phys_id(int cpu, u64 phys_id);
+
+ extern int cpu_add_dev_attr(struct device_attribute *attr);
+ extern void cpu_remove_dev_attr(struct device_attribute *attr);
+@@ -232,4 +233,11 @@
+ void arch_cpu_idle_exit(void);
+ void arch_cpu_idle_dead(void);
+
++#define IDLE_START 1
++#define IDLE_END 2
++
++void idle_notifier_register(struct notifier_block *n);
++void idle_notifier_unregister(struct notifier_block *n);
++void idle_notifier_call_chain(unsigned long val);
++
+ #endif /* _LINUX_CPU_H_ */
+diff -Nur linux-3.10.30.orig/include/linux/debugfs.h linux-linaro-stable-mx6/include/linux/debugfs.h
+--- linux-3.10.30.orig/include/linux/debugfs.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/debugfs.h 2014-05-15 20:34:14.246130918 +0200
+@@ -79,6 +79,8 @@
+ struct dentry *parent, u64 *value);
+ struct dentry *debugfs_create_size_t(const char *name, umode_t mode,
+ struct dentry *parent, size_t *value);
++struct dentry *debugfs_create_atomic_t(const char *name, umode_t mode,
++ struct dentry *parent, atomic_t *value);
+ struct dentry *debugfs_create_bool(const char *name, umode_t mode,
+ struct dentry *parent, u32 *value);
+
+diff -Nur linux-3.10.30.orig/include/linux/device_cooling.h linux-linaro-stable-mx6/include/linux/device_cooling.h
+--- linux-3.10.30.orig/include/linux/device_cooling.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/device_cooling.h 2014-05-15 20:34:14.278131149 +0200
+@@ -0,0 +1,45 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DEVICE_THERMAL_H__
++#define __DEVICE_THERMAL_H__
++
++#include <linux/thermal.h>
++
++#ifdef CONFIG_DEVICE_THERMAL
++int register_devfreq_cooling_notifier(struct notifier_block *nb);
++int unregister_devfreq_cooling_notifier(struct notifier_block *nb);
++struct thermal_cooling_device *devfreq_cooling_register(void);
++void devfreq_cooling_unregister(struct thermal_cooling_device *cdev);
++#else
++static inline
++int register_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return 0;
++}
++
++static inline
++int unregister_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return 0;
++}
++
++static inline
++struct thermal_cooling_device *devfreq_cooling_register(void)
++{
++ return NULL;
++}
++
++static inline
++void devfreq_cooling_unregister(struct thermal_cooling_device *cdev)
++{
++ return;
++}
++#endif
++#endif /* __DEVICE_THERMAL_H__ */
+diff -Nur linux-3.10.30.orig/include/linux/device.h linux-linaro-stable-mx6/include/linux/device.h
+--- linux-3.10.30.orig/include/linux/device.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/device.h 2014-05-15 20:34:14.278131149 +0200
+@@ -47,7 +47,11 @@
+ };
+
+ #define BUS_ATTR(_name, _mode, _show, _store) \
+-struct bus_attribute bus_attr_##_name = __ATTR(_name, _mode, _show, _store)
++ struct bus_attribute bus_attr_##_name = __ATTR(_name, _mode, _show, _store)
++#define BUS_ATTR_RW(_name) \
++ struct bus_attribute bus_attr_##_name = __ATTR_RW(_name)
++#define BUS_ATTR_RO(_name) \
++ struct bus_attribute bus_attr_##_name = __ATTR_RO(_name)
+
+ extern int __must_check bus_create_file(struct bus_type *,
+ struct bus_attribute *);
+@@ -62,6 +66,7 @@
+ * @bus_attrs: Default attributes of the bus.
+ * @dev_attrs: Default attributes of the devices on the bus.
+ * @drv_attrs: Default attributes of the device drivers on the bus.
++ * @dev_groups: Default attributes of the devices on the bus.
+ * @match: Called, perhaps multiple times, whenever a new device or driver
+ * is added for this bus. It should return a nonzero value if the
+ * given device can be handled by the given driver.
+@@ -95,8 +100,9 @@
+ const char *dev_name;
+ struct device *dev_root;
+ struct bus_attribute *bus_attrs;
+- struct device_attribute *dev_attrs;
++ struct device_attribute *dev_attrs; /* use dev_groups instead */
+ struct driver_attribute *drv_attrs;
++ const struct attribute_group **dev_groups;
+
+ int (*match)(struct device *dev, struct device_driver *drv);
+ int (*uevent)(struct device *dev, struct kobj_uevent_env *env);
+@@ -253,9 +259,12 @@
+ size_t count);
+ };
+
+-#define DRIVER_ATTR(_name, _mode, _show, _store) \
+-struct driver_attribute driver_attr_##_name = \
+- __ATTR(_name, _mode, _show, _store)
++#define DRIVER_ATTR(_name, _mode, _show, _store) \
++ struct driver_attribute driver_attr_##_name = __ATTR(_name, _mode, _show, _store)
++#define DRIVER_ATTR_RW(_name) \
++ struct driver_attribute driver_attr_##_name = __ATTR_RW(_name)
++#define DRIVER_ATTR_RO(_name) \
++ struct driver_attribute driver_attr_##_name = __ATTR_RO(_name)
+
+ extern int __must_check driver_create_file(struct device_driver *driver,
+ const struct driver_attribute *attr);
+@@ -406,8 +415,12 @@
+ const struct class_attribute *attr);
+ };
+
+-#define CLASS_ATTR(_name, _mode, _show, _store) \
+-struct class_attribute class_attr_##_name = __ATTR(_name, _mode, _show, _store)
++#define CLASS_ATTR(_name, _mode, _show, _store) \
++ struct class_attribute class_attr_##_name = __ATTR(_name, _mode, _show, _store)
++#define CLASS_ATTR_RW(_name) \
++ struct class_attribute class_attr_##_name = __ATTR_RW(_name)
++#define CLASS_ATTR_RO(_name) \
++ struct class_attribute class_attr_##_name = __ATTR_RO(_name)
+
+ extern int __must_check class_create_file(struct class *class,
+ const struct class_attribute *attr);
+@@ -415,7 +428,6 @@
+ const struct class_attribute *attr);
+
+ /* Simple class attribute that is just a static string */
+-
+ struct class_attribute_string {
+ struct class_attribute attr;
+ char *str;
+@@ -504,6 +516,10 @@
+
+ #define DEVICE_ATTR(_name, _mode, _show, _store) \
+ struct device_attribute dev_attr_##_name = __ATTR(_name, _mode, _show, _store)
++#define DEVICE_ATTR_RW(_name) \
++ struct device_attribute dev_attr_##_name = __ATTR_RW(_name)
++#define DEVICE_ATTR_RO(_name) \
++ struct device_attribute dev_attr_##_name = __ATTR_RO(_name)
+ #define DEVICE_ULONG_ATTR(_name, _mode, _var) \
+ struct dev_ext_attribute dev_attr_##_name = \
+ { __ATTR(_name, _mode, device_show_ulong, device_store_ulong), &(_var) }
+diff -Nur linux-3.10.30.orig/include/linux/dmaengine.h linux-linaro-stable-mx6/include/linux/dmaengine.h
+--- linux-3.10.30.orig/include/linux/dmaengine.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/dmaengine.h 2014-05-15 20:34:14.282131177 +0200
+@@ -341,6 +341,8 @@
+ * @slave_id: Slave requester id. Only valid for slave channels. The dma
+ * slave peripheral will have unique id as dma requester which need to be
+ * pass as slave config.
++ * @dma_request0: this is the first dma request of this dma channel.
++ * @dma_request1: this is the second dma request of this dma channel.
+ *
+ * This struct is passed in as configuration data to a DMA engine
+ * in order to set up a certain channel for DMA transport at runtime.
+@@ -369,6 +371,8 @@
+ u32 dst_maxburst;
+ bool device_fc;
+ unsigned int slave_id;
++ int dma_request0;
++ int dma_request1;
+ };
+
+ static inline const char *dma_chan_name(struct dma_chan *chan)
+diff -Nur linux-3.10.30.orig/include/linux/err.h linux-linaro-stable-mx6/include/linux/err.h
+--- linux-3.10.30.orig/include/linux/err.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/err.h 2014-05-15 20:34:14.286131207 +0200
+@@ -52,7 +52,7 @@
+ return (void *) ptr;
+ }
+
+-static inline int __must_check PTR_RET(const void *ptr)
++static inline int __must_check PTR_ERR_OR_ZERO(__force const void *ptr)
+ {
+ if (IS_ERR(ptr))
+ return PTR_ERR(ptr);
+@@ -60,6 +60,9 @@
+ return 0;
+ }
+
++/* Deprecated */
++#define PTR_RET(p) PTR_ERR_OR_ZERO(p)
++
+ #endif
+
+ #endif /* _LINUX_ERR_H */
+diff -Nur linux-3.10.30.orig/include/linux/f2fs_fs.h linux-linaro-stable-mx6/include/linux/f2fs_fs.h
+--- linux-3.10.30.orig/include/linux/f2fs_fs.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/f2fs_fs.h 2014-05-15 20:34:14.310131379 +0200
+@@ -140,14 +140,24 @@
+ } __packed;
+
+ #define F2FS_NAME_LEN 255
+-#define ADDRS_PER_INODE 923 /* Address Pointers in an Inode */
+-#define ADDRS_PER_BLOCK 1018 /* Address Pointers in a Direct Block */
+-#define NIDS_PER_BLOCK 1018 /* Node IDs in an Indirect Block */
++#define F2FS_INLINE_XATTR_ADDRS 50 /* 200 bytes for inline xattrs */
++#define DEF_ADDRS_PER_INODE 923 /* Address Pointers in an Inode */
++#define ADDRS_PER_INODE(fi) addrs_per_inode(fi)
++#define ADDRS_PER_BLOCK 1018 /* Address Pointers in a Direct Block */
++#define NIDS_PER_BLOCK 1018 /* Node IDs in an Indirect Block */
++
++#define NODE_DIR1_BLOCK (DEF_ADDRS_PER_INODE + 1)
++#define NODE_DIR2_BLOCK (DEF_ADDRS_PER_INODE + 2)
++#define NODE_IND1_BLOCK (DEF_ADDRS_PER_INODE + 3)
++#define NODE_IND2_BLOCK (DEF_ADDRS_PER_INODE + 4)
++#define NODE_DIND_BLOCK (DEF_ADDRS_PER_INODE + 5)
++
++#define F2FS_INLINE_XATTR 0x01 /* file inline xattr flag */
+
+ struct f2fs_inode {
+ __le16 i_mode; /* file mode */
+ __u8 i_advise; /* file hints */
+- __u8 i_reserved; /* reserved */
++ __u8 i_inline; /* file inline flags */
+ __le32 i_uid; /* user ID */
+ __le32 i_gid; /* group ID */
+ __le32 i_links; /* links count */
+@@ -170,7 +180,7 @@
+
+ struct f2fs_extent i_ext; /* caching a largest extent */
+
+- __le32 i_addr[ADDRS_PER_INODE]; /* Pointers to data blocks */
++ __le32 i_addr[DEF_ADDRS_PER_INODE]; /* Pointers to data blocks */
+
+ __le32 i_nid[5]; /* direct(2), indirect(2),
+ double_indirect(1) node id */
+diff -Nur linux-3.10.30.orig/include/linux/genalloc.h linux-linaro-stable-mx6/include/linux/genalloc.h
+--- linux-3.10.30.orig/include/linux/genalloc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/genalloc.h 2014-05-15 20:34:14.458132445 +0200
+@@ -94,6 +94,8 @@
+ }
+ extern void gen_pool_destroy(struct gen_pool *);
+ extern unsigned long gen_pool_alloc(struct gen_pool *, size_t);
++extern void *gen_pool_dma_alloc(struct gen_pool *pool, size_t size,
++ dma_addr_t *dma);
+ extern void gen_pool_free(struct gen_pool *, unsigned long, size_t);
+ extern void gen_pool_for_each_chunk(struct gen_pool *,
+ void (*)(struct gen_pool *, struct gen_pool_chunk *, void *), void *);
+diff -Nur linux-3.10.30.orig/include/linux/gpio/consumer.h linux-linaro-stable-mx6/include/linux/gpio/consumer.h
+--- linux-3.10.30.orig/include/linux/gpio/consumer.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/gpio/consumer.h 2014-05-15 20:34:14.462132474 +0200
+@@ -0,0 +1,253 @@
++#ifndef __LINUX_GPIO_CONSUMER_H
++#define __LINUX_GPIO_CONSUMER_H
++
++#include <linux/err.h>
++#include <linux/kernel.h>
++
++#ifdef CONFIG_GPIOLIB
++
++struct device;
++struct gpio_chip;
++
++/**
++ * Opaque descriptor for a GPIO. These are obtained using gpiod_get() and are
++ * preferable to the old integer-based handles.
++ *
++ * Contrary to integers, a pointer to a gpio_desc is guaranteed to be valid
++ * until the GPIO is released.
++ */
++struct gpio_desc;
++
++/* Acquire and dispose GPIOs */
++struct gpio_desc *__must_check gpiod_get(struct device *dev,
++ const char *con_id);
++struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
++ const char *con_id,
++ unsigned int idx);
++void gpiod_put(struct gpio_desc *desc);
++
++struct gpio_desc *__must_check devm_gpiod_get(struct device *dev,
++ const char *con_id);
++struct gpio_desc *__must_check devm_gpiod_get_index(struct device *dev,
++ const char *con_id,
++ unsigned int idx);
++void devm_gpiod_put(struct device *dev, struct gpio_desc *desc);
++
++int gpiod_get_direction(const struct gpio_desc *desc);
++int gpiod_direction_input(struct gpio_desc *desc);
++int gpiod_direction_output(struct gpio_desc *desc, int value);
++
++/* Value get/set from non-sleeping context */
++int gpiod_get_value(const struct gpio_desc *desc);
++void gpiod_set_value(struct gpio_desc *desc, int value);
++int gpiod_get_raw_value(const struct gpio_desc *desc);
++void gpiod_set_raw_value(struct gpio_desc *desc, int value);
++
++/* Value get/set from sleeping context */
++int gpiod_get_value_cansleep(const struct gpio_desc *desc);
++void gpiod_set_value_cansleep(struct gpio_desc *desc, int value);
++int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc);
++void gpiod_set_raw_value_cansleep(struct gpio_desc *desc, int value);
++
++int gpiod_set_debounce(struct gpio_desc *desc, unsigned debounce);
++
++int gpiod_is_active_low(const struct gpio_desc *desc);
++int gpiod_cansleep(const struct gpio_desc *desc);
++
++int gpiod_to_irq(const struct gpio_desc *desc);
++
++/* Convert between the old gpio_ and new gpiod_ interfaces */
++struct gpio_desc *gpio_to_desc(unsigned gpio);
++int desc_to_gpio(const struct gpio_desc *desc);
++struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
++
++#else /* CONFIG_GPIOLIB */
++
++static inline struct gpio_desc *__must_check gpiod_get(struct device *dev,
++ const char *con_id)
++{
++ return ERR_PTR(-ENOSYS);
++}
++static inline struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
++ const char *con_id,
++ unsigned int idx)
++{
++ return ERR_PTR(-ENOSYS);
++}
++static inline void gpiod_put(struct gpio_desc *desc)
++{
++ might_sleep();
++
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++}
++
++static inline struct gpio_desc *__must_check devm_gpiod_get(struct device *dev,
++ const char *con_id)
++{
++ return ERR_PTR(-ENOSYS);
++}
++static inline
++struct gpio_desc *__must_check devm_gpiod_get_index(struct device *dev,
++ const char *con_id,
++ unsigned int idx)
++{
++ return ERR_PTR(-ENOSYS);
++}
++static inline void devm_gpiod_put(struct device *dev, struct gpio_desc *desc)
++{
++ might_sleep();
++
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++}
++
++
++static inline int gpiod_get_direction(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return -ENOSYS;
++}
++static inline int gpiod_direction_input(struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return -ENOSYS;
++}
++static inline int gpiod_direction_output(struct gpio_desc *desc, int value)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return -ENOSYS;
++}
++
++
++static inline int gpiod_get_value(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return 0;
++}
++static inline void gpiod_set_value(struct gpio_desc *desc, int value)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++}
++static inline int gpiod_get_raw_value(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return 0;
++}
++static inline void gpiod_set_raw_value(struct gpio_desc *desc, int value)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++}
++
++static inline int gpiod_get_value_cansleep(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return 0;
++}
++static inline void gpiod_set_value_cansleep(struct gpio_desc *desc, int value)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++}
++static inline int gpiod_get_raw_value_cansleep(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return 0;
++}
++static inline void gpiod_set_raw_value_cansleep(struct gpio_desc *desc,
++ int value)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++}
++
++static inline int gpiod_set_debounce(struct gpio_desc *desc, unsigned debounce)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return -ENOSYS;
++}
++
++static inline int gpiod_is_active_low(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return 0;
++}
++static inline int gpiod_cansleep(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return 0;
++}
++
++static inline int gpiod_to_irq(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return -EINVAL;
++}
++
++static inline struct gpio_desc *gpio_to_desc(unsigned gpio)
++{
++ return ERR_PTR(-EINVAL);
++}
++static inline int desc_to_gpio(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return -EINVAL;
++}
++static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
++{
++ /* GPIO can never have been requested */
++ WARN_ON(1);
++ return ERR_PTR(-ENODEV);
++}
++
++
++#endif /* CONFIG_GPIOLIB */
++
++#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
++
++int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
++int gpiod_export_link(struct device *dev, const char *name,
++ struct gpio_desc *desc);
++int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value);
++void gpiod_unexport(struct gpio_desc *desc);
++
++#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
++
++static inline int gpiod_export(struct gpio_desc *desc,
++ bool direction_may_change)
++{
++ return -ENOSYS;
++}
++
++static inline int gpiod_export_link(struct device *dev, const char *name,
++ struct gpio_desc *desc)
++{
++ return -ENOSYS;
++}
++
++static inline int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value)
++{
++ return -ENOSYS;
++}
++
++static inline void gpiod_unexport(struct gpio_desc *desc)
++{
++}
++
++#endif /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/gpio/driver.h linux-linaro-stable-mx6/include/linux/gpio/driver.h
+--- linux-3.10.30.orig/include/linux/gpio/driver.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/gpio/driver.h 2014-05-15 20:34:14.462132474 +0200
+@@ -0,0 +1,190 @@
++#ifndef __LINUX_GPIO_DRIVER_H
++#define __LINUX_GPIO_DRIVER_H
++
++#include <linux/types.h>
++
++struct device;
++struct gpio_desc;
++
++/**
++ * struct gpio_chip - abstract a GPIO controller
++ * @label: for diagnostics
++ * @dev: optional device providing the GPIOs
++ * @owner: helps prevent removal of modules exporting active GPIOs
++ * @list: links gpio_chips together for traversal
++ * @request: optional hook for chip-specific activation, such as
++ * enabling module power and clock; may sleep
++ * @free: optional hook for chip-specific deactivation, such as
++ * disabling module power and clock; may sleep
++ * @get_direction: returns direction for signal "offset", 0=out, 1=in,
++ * (same as GPIOF_DIR_XXX), or negative error
++ * @direction_input: configures signal "offset" as input, or returns error
++ * @direction_output: configures signal "offset" as output, or returns error
++ * @get: returns value for signal "offset"; for output signals this
++ * returns either the value actually sensed, or zero
++ * @set: assigns output value for signal "offset"
++ * @set_debounce: optional hook for setting debounce time for specified gpio in
++ * interrupt triggered gpio chips
++ * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
++ * implementation may not sleep
++ * @dbg_show: optional routine to show contents in debugfs; default code
++ * will be used when this is omitted, but custom code can show extra
++ * state (such as pullup/pulldown configuration).
++ * @base: identifies the first GPIO number handled by this chip; or, if
++ * negative during registration, requests dynamic ID allocation.
++ * @ngpio: the number of GPIOs handled by this controller; the last GPIO
++ * handled is (base + ngpio - 1).
++ * @desc: array of ngpio descriptors. Private.
++ * @can_sleep: flag must be set iff get()/set() methods sleep, as they
++ * must while accessing GPIO expander chips over I2C or SPI
++ * @names: if set, must be an array of strings to use as alternative
++ * names for the GPIOs in this chip. Any entry in the array
++ * may be NULL if there is no alias for the GPIO, however the
++ * array must be @ngpio entries long. A name can include a single printk
++ * format specifier for an unsigned int. It is substituted by the actual
++ * number of the gpio.
++ *
++ * A gpio_chip can help platforms abstract various sources of GPIOs so
++ * they can all be accessed through a common programing interface.
++ * Example sources would be SOC controllers, FPGAs, multifunction
++ * chips, dedicated GPIO expanders, and so on.
++ *
++ * Each chip controls a number of signals, identified in method calls
++ * by "offset" values in the range 0..(@ngpio - 1). When those signals
++ * are referenced through calls like gpio_get_value(gpio), the offset
++ * is calculated by subtracting @base from the gpio number.
++ */
++struct gpio_chip {
++ const char *label;
++ struct device *dev;
++ struct module *owner;
++ struct list_head list;
++
++ int (*request)(struct gpio_chip *chip,
++ unsigned offset);
++ void (*free)(struct gpio_chip *chip,
++ unsigned offset);
++ int (*get_direction)(struct gpio_chip *chip,
++ unsigned offset);
++ int (*direction_input)(struct gpio_chip *chip,
++ unsigned offset);
++ int (*direction_output)(struct gpio_chip *chip,
++ unsigned offset, int value);
++ int (*get)(struct gpio_chip *chip,
++ unsigned offset);
++ void (*set)(struct gpio_chip *chip,
++ unsigned offset, int value);
++ int (*set_debounce)(struct gpio_chip *chip,
++ unsigned offset,
++ unsigned debounce);
++
++ int (*to_irq)(struct gpio_chip *chip,
++ unsigned offset);
++
++ void (*dbg_show)(struct seq_file *s,
++ struct gpio_chip *chip);
++ int base;
++ u16 ngpio;
++ struct gpio_desc *desc;
++ const char *const *names;
++ unsigned can_sleep:1;
++ unsigned exported:1;
++
++#if defined(CONFIG_OF_GPIO)
++ /*
++ * If CONFIG_OF is enabled, then all GPIO controllers described in the
++ * device tree automatically may have an OF translation
++ */
++ struct device_node *of_node;
++ int of_gpio_n_cells;
++ int (*of_xlate)(struct gpio_chip *gc,
++ const struct of_phandle_args *gpiospec, u32 *flags);
++#endif
++#ifdef CONFIG_PINCTRL
++ /*
++ * If CONFIG_PINCTRL is enabled, then gpio controllers can optionally
++ * describe the actual pin range which they serve in an SoC. This
++ * information would be used by pinctrl subsystem to configure
++ * corresponding pins for gpio usage.
++ */
++ struct list_head pin_ranges;
++#endif
++};
++
++extern const char *gpiochip_is_requested(struct gpio_chip *chip,
++ unsigned offset);
++
++/* add/remove chips */
++extern int gpiochip_add(struct gpio_chip *chip);
++extern int __must_check gpiochip_remove(struct gpio_chip *chip);
++extern struct gpio_chip *gpiochip_find(void *data,
++ int (*match)(struct gpio_chip *chip, void *data));
++
++/* lock/unlock as IRQ */
++int gpiod_lock_as_irq(struct gpio_desc *desc);
++void gpiod_unlock_as_irq(struct gpio_desc *desc);
++
++enum gpio_lookup_flags {
++ GPIO_ACTIVE_HIGH = (0 << 0),
++ GPIO_ACTIVE_LOW = (1 << 0),
++ GPIO_OPEN_DRAIN = (1 << 1),
++ GPIO_OPEN_SOURCE = (1 << 2),
++};
++
++/**
++ * Lookup table for associating GPIOs to specific devices and functions using
++ * platform data.
++ */
++struct gpiod_lookup {
++ struct list_head list;
++ /*
++ * name of the chip the GPIO belongs to
++ */
++ const char *chip_label;
++ /*
++ * hardware number (i.e. relative to the chip) of the GPIO
++ */
++ u16 chip_hwnum;
++ /*
++ * name of device that can claim this GPIO
++ */
++ const char *dev_id;
++ /*
++ * name of the GPIO from the device's point of view
++ */
++ const char *con_id;
++ /*
++ * index of the GPIO in case several GPIOs share the same name
++ */
++ unsigned int idx;
++ /*
++ * mask of GPIO_* values
++ */
++ enum gpio_lookup_flags flags;
++};
++
++/*
++ * Simple definition of a single GPIO under a con_id
++ */
++#define GPIO_LOOKUP(_chip_label, _chip_hwnum, _dev_id, _con_id, _flags) \
++ GPIO_LOOKUP_IDX(_chip_label, _chip_hwnum, _dev_id, _con_id, 0, _flags)
++
++/*
++ * Use this macro if you need to have several GPIOs under the same con_id.
++ * Each GPIO needs to use a different index and can be accessed using
++ * gpiod_get_index()
++ */
++#define GPIO_LOOKUP_IDX(_chip_label, _chip_hwnum, _dev_id, _con_id, _idx, \
++ _flags) \
++{ \
++ .chip_label = _chip_label, \
++ .chip_hwnum = _chip_hwnum, \
++ .dev_id = _dev_id, \
++ .con_id = _con_id, \
++ .idx = _idx, \
++ .flags = _flags, \
++}
++
++void gpiod_add_table(struct gpiod_lookup *table, size_t size);
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/gpio.h linux-linaro-stable-mx6/include/linux/gpio.h
+--- linux-3.10.30.orig/include/linux/gpio.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/gpio.h 2014-05-15 20:34:14.458132445 +0200
+@@ -16,14 +16,17 @@
+ #define GPIOF_OUT_INIT_LOW (GPIOF_DIR_OUT | GPIOF_INIT_LOW)
+ #define GPIOF_OUT_INIT_HIGH (GPIOF_DIR_OUT | GPIOF_INIT_HIGH)
+
++/* Gpio pin is active-low */
++#define GPIOF_ACTIVE_LOW (1 << 2)
++
+ /* Gpio pin is open drain */
+-#define GPIOF_OPEN_DRAIN (1 << 2)
++#define GPIOF_OPEN_DRAIN (1 << 3)
+
+ /* Gpio pin is open source */
+-#define GPIOF_OPEN_SOURCE (1 << 3)
++#define GPIOF_OPEN_SOURCE (1 << 4)
+
+-#define GPIOF_EXPORT (1 << 4)
+-#define GPIOF_EXPORT_CHANGEABLE (1 << 5)
++#define GPIOF_EXPORT (1 << 5)
++#define GPIOF_EXPORT_CHANGEABLE (1 << 6)
+ #define GPIOF_EXPORT_DIR_FIXED (GPIOF_EXPORT)
+ #define GPIOF_EXPORT_DIR_CHANGEABLE (GPIOF_EXPORT | GPIOF_EXPORT_CHANGEABLE)
+
+@@ -204,6 +207,18 @@
+ return -EINVAL;
+ }
+
++static inline int gpio_lock_as_irq(struct gpio_chip *chip, unsigned int offset)
++{
++ WARN_ON(1);
++ return -EINVAL;
++}
++
++static inline void gpio_unlock_as_irq(struct gpio_chip *chip,
++ unsigned int offset)
++{
++ WARN_ON(1);
++}
++
+ static inline int irq_to_gpio(unsigned irq)
+ {
+ /* irq can never have been returned from gpio_to_irq() */
+diff -Nur linux-3.10.30.orig/include/linux/hardirq.h linux-linaro-stable-mx6/include/linux/hardirq.h
+--- linux-3.10.30.orig/include/linux/hardirq.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/hardirq.h 2014-05-15 20:34:14.462132474 +0200
+@@ -124,8 +124,10 @@
+
+ #if defined(CONFIG_SMP) || defined(CONFIG_GENERIC_HARDIRQS)
+ extern void synchronize_irq(unsigned int irq);
++extern void synchronize_hardirq(unsigned int irq);
+ #else
+ # define synchronize_irq(irq) barrier()
++# define synchronize_hardirq(irq) barrier()
+ #endif
+
+ #if defined(CONFIG_TINY_RCU) || defined(CONFIG_TINY_PREEMPT_RCU)
+diff -Nur linux-3.10.30.orig/include/linux/interrupt.h linux-linaro-stable-mx6/include/linux/interrupt.h
+--- linux-3.10.30.orig/include/linux/interrupt.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/interrupt.h 2014-05-15 20:34:14.566133223 +0200
+@@ -219,6 +219,7 @@
+ extern void disable_percpu_irq(unsigned int irq);
+ extern void enable_irq(unsigned int irq);
+ extern void enable_percpu_irq(unsigned int irq, unsigned int type);
++extern void irq_wake_thread(unsigned int irq, void *dev_id);
+
+ /* The following three functions are for the core kernel use only. */
+ #ifdef CONFIG_GENERIC_HARDIRQS
+diff -Nur linux-3.10.30.orig/include/linux/ipu.h linux-linaro-stable-mx6/include/linux/ipu.h
+--- linux-3.10.30.orig/include/linux/ipu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/ipu.h 2014-05-15 20:34:14.570133252 +0200
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*!
++ * @defgroup IPU MXC Image Processing Unit (IPU) Driver
++ */
++/*!
++ * @file linux/ipu.h
++ *
++ * @brief This file contains the IPU driver API declarations.
++ *
++ * @ingroup IPU
++ */
++
++#ifndef __LINUX_IPU_H__
++#define __LINUX_IPU_H__
++
++#include <linux/interrupt.h>
++#include <uapi/linux/ipu.h>
++
++unsigned int fmt_to_bpp(unsigned int pixelformat);
++cs_t colorspaceofpixel(int fmt);
++int need_csc(int ifmt, int ofmt);
++
++int ipu_queue_task(struct ipu_task *task);
++int ipu_check_task(struct ipu_task *task);
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/ipu-v3.h linux-linaro-stable-mx6/include/linux/ipu-v3.h
+--- linux-3.10.30.orig/include/linux/ipu-v3.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/ipu-v3.h 2014-05-15 20:34:14.570133252 +0200
+@@ -0,0 +1,752 @@
++/*
++ * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#ifndef __LINUX_IPU_V3_H_
++#define __LINUX_IPU_V3_H_
++
++#include <linux/ipu.h>
++
++/* IPU Driver channels definitions. */
++/* Note these are different from IDMA channels */
++#define IPU_MAX_CH 32
++#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
++ ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
++#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
++#define IPU_CHAN_ID(ch) (ch >> 24)
++#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
++#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
++#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
++#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
++#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
++#define NO_DMA 0x3F
++#define ALT 1
++/*!
++ * Enumeration of IPU logical channels. An IPU logical channel is defined as a
++ * combination of an input (memory to IPU), output (IPU to memory), and/or
++ * secondary input IDMA channels and in some cases an Image Converter task.
++ * Some channels consist of only an input or output.
++ */
++typedef enum {
++ CHAN_NONE = -1,
++ MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48),
++ MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49),
++ MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50),
++
++ MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20),
++ MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21),
++ MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22),
++
++ MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
++ MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
++ MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
++ MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
++
++ MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
++ MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
++ MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
++ MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
++
++ DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++ DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++
++ CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0),
++ CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1),
++ CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2),
++ CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3),
++
++ CSI_MEM = CSI_MEM0,
++
++ CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20),
++ CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21),
++
++ /* for vdi mem->vdi->ic->mem , add graphics plane and alpha*/
++ MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21),
++ MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21),
++ MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21),
++
++ /* for vdi mem->vdi->mem */
++ MEM_VDI_MEM_P = _MAKE_CHAN(24, 8, NO_DMA, NO_DMA, 5),
++ MEM_VDI_MEM = _MAKE_CHAN(25, 9, NO_DMA, NO_DMA, 5),
++ MEM_VDI_MEM_N = _MAKE_CHAN(26, 10, NO_DMA, NO_DMA, 5),
++
++ /* fake channel for vdoa to link with IPU */
++ MEM_VDOA_MEM = _MAKE_CHAN(27, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++
++ MEM_PP_ADC = CHAN_NONE,
++ ADC_SYS2 = CHAN_NONE,
++
++} ipu_channel_t;
++
++/*!
++ * Enumeration of types of buffers for a logical channel.
++ */
++typedef enum {
++ IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */
++ IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */
++ IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */
++ IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */
++ IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
++ IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
++} ipu_buffer_t;
++
++#define IPU_PANEL_SERIAL 1
++#define IPU_PANEL_PARALLEL 2
++
++/*!
++ * Enumeration of ADC channel operation mode.
++ */
++typedef enum {
++ Disable,
++ WriteTemplateNonSeq,
++ ReadTemplateNonSeq,
++ WriteTemplateUnCon,
++ ReadTemplateUnCon,
++ WriteDataWithRS,
++ WriteDataWoRS,
++ WriteCmd
++} mcu_mode_t;
++
++/*!
++ * Enumeration of ADC channel addressing mode.
++ */
++typedef enum {
++ FullWoBE,
++ FullWithBE,
++ XY
++} display_addressing_t;
++
++/*!
++ * Union of initialization parameters for a logical channel.
++ */
++typedef union {
++ struct {
++ uint32_t csi;
++ uint32_t mipi_id;
++ uint32_t mipi_vc;
++ bool mipi_en;
++ bool interlaced;
++ } csi_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ uint32_t csi;
++ uint32_t mipi_id;
++ uint32_t mipi_vc;
++ bool mipi_en;
++ } csi_prp_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ } mem_prp_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ } mem_rot_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ ipu_motion_sel motion_sel;
++ enum v4l2_field field_fmt;
++ uint32_t csi;
++ uint32_t mipi_id;
++ uint32_t mipi_vc;
++ bool mipi_en;
++ } csi_prp_vf_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ display_port_t disp;
++ uint32_t out_left;
++ uint32_t out_top;
++ } csi_prp_vf_adc;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ ipu_motion_sel motion_sel;
++ enum v4l2_field field_fmt;
++ } mem_prp_vf_mem;
++ struct {
++ uint32_t temp;
++ } mem_prp_vf_adc;
++ struct {
++ uint32_t temp;
++ } mem_rot_vf_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ } mem_pp_mem;
++ struct {
++ uint32_t temp;
++ } mem_rot_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ display_port_t disp;
++ uint32_t out_left;
++ uint32_t out_top;
++ } mem_pp_adc;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ } mem_dc_sync;
++ struct {
++ uint32_t temp;
++ } mem_sdc_fg;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ bool alpha_chan_en;
++ } mem_dp_bg_sync;
++ struct {
++ uint32_t temp;
++ } mem_sdc_bg;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ bool alpha_chan_en;
++ } mem_dp_fg_sync;
++ struct {
++ uint32_t di;
++ } direct_async;
++ struct {
++ display_port_t disp;
++ mcu_mode_t ch_mode;
++ uint32_t out_left;
++ uint32_t out_top;
++ } adc_sys1;
++ struct {
++ display_port_t disp;
++ mcu_mode_t ch_mode;
++ uint32_t out_left;
++ uint32_t out_top;
++ } adc_sys2;
++} ipu_channel_params_t;
++
++/*
++ * IPU_IRQF_ONESHOT - Interrupt is not reenabled after the irq handler finished.
++ */
++#define IPU_IRQF_NONE 0x00000000
++#define IPU_IRQF_ONESHOT 0x00000001
++
++/*!
++ * Enumeration of IPU interrupt sources.
++ */
++enum ipu_irq_line {
++ IPU_IRQ_CSI0_OUT_EOF = 0,
++ IPU_IRQ_CSI1_OUT_EOF = 1,
++ IPU_IRQ_CSI2_OUT_EOF = 2,
++ IPU_IRQ_CSI3_OUT_EOF = 3,
++ IPU_IRQ_VDIC_OUT_EOF = 5,
++ IPU_IRQ_VDI_P_IN_EOF = 8,
++ IPU_IRQ_VDI_C_IN_EOF = 9,
++ IPU_IRQ_VDI_N_IN_EOF = 10,
++ IPU_IRQ_PP_IN_EOF = 11,
++ IPU_IRQ_PRP_IN_EOF = 12,
++ IPU_IRQ_PRP_GRAPH_IN_EOF = 14,
++ IPU_IRQ_PP_GRAPH_IN_EOF = 15,
++ IPU_IRQ_PRP_ALPHA_IN_EOF = 17,
++ IPU_IRQ_PP_ALPHA_IN_EOF = 18,
++ IPU_IRQ_PRP_ENC_OUT_EOF = 20,
++ IPU_IRQ_PRP_VF_OUT_EOF = 21,
++ IPU_IRQ_PP_OUT_EOF = 22,
++ IPU_IRQ_BG_SYNC_EOF = 23,
++ IPU_IRQ_BG_ASYNC_EOF = 24,
++ IPU_IRQ_FG_SYNC_EOF = 27,
++ IPU_IRQ_DC_SYNC_EOF = 28,
++ IPU_IRQ_FG_ASYNC_EOF = 29,
++ IPU_IRQ_FG_ALPHA_SYNC_EOF = 31,
++
++ IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33,
++ IPU_IRQ_DC_READ_EOF = 40,
++ IPU_IRQ_DC_ASYNC_EOF = 41,
++ IPU_IRQ_DC_CMD1_EOF = 42,
++ IPU_IRQ_DC_CMD2_EOF = 43,
++ IPU_IRQ_DC_MASK_EOF = 44,
++ IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45,
++ IPU_IRQ_PRP_VF_ROT_IN_EOF = 46,
++ IPU_IRQ_PP_ROT_IN_EOF = 47,
++ IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48,
++ IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49,
++ IPU_IRQ_PP_ROT_OUT_EOF = 50,
++ IPU_IRQ_BG_ALPHA_SYNC_EOF = 51,
++ IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52,
++
++ IPU_IRQ_BG_SYNC_NFACK = 64 + 23,
++ IPU_IRQ_FG_SYNC_NFACK = 64 + 27,
++ IPU_IRQ_DC_SYNC_NFACK = 64 + 28,
++
++ IPU_IRQ_DP_SF_START = 448 + 2,
++ IPU_IRQ_DP_SF_END = 448 + 3,
++ IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END,
++ IPU_IRQ_DC_FC_0 = 448 + 8,
++ IPU_IRQ_DC_FC_1 = 448 + 9,
++ IPU_IRQ_DC_FC_2 = 448 + 10,
++ IPU_IRQ_DC_FC_3 = 448 + 11,
++ IPU_IRQ_DC_FC_4 = 448 + 12,
++ IPU_IRQ_DC_FC_6 = 448 + 13,
++ IPU_IRQ_VSYNC_PRE_0 = 448 + 14,
++ IPU_IRQ_VSYNC_PRE_1 = 448 + 15,
++
++ IPU_IRQ_COUNT
++};
++
++/*!
++ * Bitfield of Display Interface signal polarities.
++ */
++typedef struct {
++ unsigned datamask_en:1;
++ unsigned int_clk:1;
++ unsigned interlaced:1;
++ unsigned odd_field_first:1;
++ unsigned clksel_en:1;
++ unsigned clkidle_en:1;
++ unsigned data_pol:1; /* true = inverted */
++ unsigned clk_pol:1; /* true = rising edge */
++ unsigned enable_pol:1;
++ unsigned Hsync_pol:1; /* true = active high */
++ unsigned Vsync_pol:1;
++} ipu_di_signal_cfg_t;
++
++/*!
++ * Bitfield of CSI signal polarities and modes.
++ */
++
++typedef struct {
++ unsigned data_width:4;
++ unsigned clk_mode:3;
++ unsigned ext_vsync:1;
++ unsigned Vsync_pol:1;
++ unsigned Hsync_pol:1;
++ unsigned pixclk_pol:1;
++ unsigned data_pol:1;
++ unsigned sens_clksrc:1;
++ unsigned pack_tight:1;
++ unsigned force_eof:1;
++ unsigned data_en_pol:1;
++ unsigned data_fmt;
++ unsigned csi;
++ unsigned mclk;
++} ipu_csi_signal_cfg_t;
++
++/*!
++ * Enumeration of CSI data bus widths.
++ */
++enum {
++ IPU_CSI_DATA_WIDTH_4 = 0,
++ IPU_CSI_DATA_WIDTH_8 = 1,
++ IPU_CSI_DATA_WIDTH_10 = 3,
++ IPU_CSI_DATA_WIDTH_16 = 9,
++};
++
++/*!
++ * Enumeration of CSI clock modes.
++ */
++enum {
++ IPU_CSI_CLK_MODE_GATED_CLK,
++ IPU_CSI_CLK_MODE_NONGATED_CLK,
++ IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
++ IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
++};
++
++enum {
++ IPU_CSI_MIPI_DI0,
++ IPU_CSI_MIPI_DI1,
++ IPU_CSI_MIPI_DI2,
++ IPU_CSI_MIPI_DI3,
++};
++
++typedef enum {
++ RGB,
++ YCbCr,
++ YUV
++} ipu_color_space_t;
++
++/*!
++ * Enumeration of ADC vertical sync mode.
++ */
++typedef enum {
++ VsyncNone,
++ VsyncInternal,
++ VsyncCSI,
++ VsyncExternal
++} vsync_t;
++
++typedef enum {
++ DAT,
++ CMD
++} cmddata_t;
++
++/*!
++ * Enumeration of ADC display update mode.
++ */
++typedef enum {
++ IPU_ADC_REFRESH_NONE,
++ IPU_ADC_AUTO_REFRESH,
++ IPU_ADC_AUTO_REFRESH_SNOOP,
++ IPU_ADC_SNOOPING,
++} ipu_adc_update_mode_t;
++
++/*!
++ * Enumeration of ADC display interface types (serial or parallel).
++ */
++enum {
++ IPU_ADC_IFC_MODE_SYS80_TYPE1,
++ IPU_ADC_IFC_MODE_SYS80_TYPE2,
++ IPU_ADC_IFC_MODE_SYS68K_TYPE1,
++ IPU_ADC_IFC_MODE_SYS68K_TYPE2,
++ IPU_ADC_IFC_MODE_3WIRE_SERIAL,
++ IPU_ADC_IFC_MODE_4WIRE_SERIAL,
++ IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK,
++ IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS,
++};
++
++enum {
++ IPU_ADC_IFC_WIDTH_8,
++ IPU_ADC_IFC_WIDTH_16,
++};
++
++/*!
++ * Enumeration of ADC display interface burst mode.
++ */
++enum {
++ IPU_ADC_BURST_WCS,
++ IPU_ADC_BURST_WBLCK,
++ IPU_ADC_BURST_NONE,
++ IPU_ADC_BURST_SERIAL,
++};
++
++/*!
++ * Enumeration of ADC display interface RW signal timing modes.
++ */
++enum {
++ IPU_ADC_SER_NO_RW,
++ IPU_ADC_SER_RW_BEFORE_RS,
++ IPU_ADC_SER_RW_AFTER_RS,
++};
++
++/*!
++ * Bitfield of ADC signal polarities and modes.
++ */
++typedef struct {
++ unsigned data_pol:1;
++ unsigned clk_pol:1;
++ unsigned cs_pol:1;
++ unsigned rs_pol:1;
++ unsigned addr_pol:1;
++ unsigned read_pol:1;
++ unsigned write_pol:1;
++ unsigned Vsync_pol:1;
++ unsigned burst_pol:1;
++ unsigned burst_mode:2;
++ unsigned ifc_mode:3;
++ unsigned ifc_width:5;
++ unsigned ser_preamble_len:4;
++ unsigned ser_preamble:8;
++ unsigned ser_rw_mode:2;
++} ipu_adc_sig_cfg_t;
++
++/*!
++ * Enumeration of ADC template commands.
++ */
++enum {
++ RD_DATA,
++ RD_ACK,
++ RD_WAIT,
++ WR_XADDR,
++ WR_YADDR,
++ WR_ADDR,
++ WR_CMND,
++ WR_DATA,
++};
++
++/*!
++ * Enumeration of ADC template command flow control.
++ */
++enum {
++ SINGLE_STEP,
++ PAUSE,
++ STOP,
++};
++
++
++/*Define template constants*/
++#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */
++#define TEMPLATE_BUF_SIZE 0x20 /*size of template */
++
++/*!
++ * Define to create ADC template command entry.
++ */
++#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \
++ ((oc) << 24) | (dat))
++
++typedef struct {
++ u32 reg;
++ u32 value;
++} ipu_lpmc_reg_t;
++
++#define IPU_LPMC_REG_READ 0x80000000L
++
++#define CSI_MCLK_VF 1
++#define CSI_MCLK_ENC 2
++#define CSI_MCLK_RAW 4
++#define CSI_MCLK_I2C 8
++
++struct ipu_soc;
++/* Common IPU API */
++struct ipu_soc *ipu_get_soc(int id);
++int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
++void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel);
++void ipu_disable_hsp_clk(struct ipu_soc *ipu);
++
++static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot)
++{
++#ifdef CONFIG_MXC_IPU_V3D
++ return (rot < IPU_ROTATE_HORIZ_FLIP);
++#else
++ return (rot < IPU_ROTATE_90_RIGHT);
++#endif
++}
++
++int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ ipu_rotate_mode_t rot_mode,
++ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
++ dma_addr_t phyaddr_2,
++ uint32_t u_offset, uint32_t v_offset);
++
++int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum, dma_addr_t phyaddr);
++
++int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t vertical_offset, uint32_t horizontal_offset);
++
++int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum);
++int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum);
++
++int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
++int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
++
++int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel);
++int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum);
++void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum);
++uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type);
++int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel);
++int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop);
++int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch);
++uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
++
++int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi);
++int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi);
++
++int ipu_lowpwr_display_enable(void);
++int ipu_lowpwr_display_disable(void);
++
++int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq);
++void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq);
++void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq);
++int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
++ irqreturn_t(*handler) (int, void *),
++ uint32_t irq_flags, const char *devname, void *dev_id);
++void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id);
++bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq);
++void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
++int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t band_height);
++
++/* two stripe calculations */
++struct stripe_param{
++ unsigned int input_width; /* width of the input stripe */
++ unsigned int output_width; /* width of the output stripe */
++ unsigned int input_column; /* the first column on the input stripe */
++ unsigned int output_column; /* the first column on the output stripe */
++ unsigned int idr;
++ /* inverse downisizing ratio parameter; expressed as a power of 2 */
++ unsigned int irr;
++ /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */
++};
++int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
++ unsigned int output_frame_width,
++ const unsigned int maximal_stripe_width,
++ const unsigned long long cirr,
++ const unsigned int equal_stripes,
++ u32 input_pixelformat,
++ u32 output_pixelformat,
++ struct stripe_param *left,
++ struct stripe_param *right);
++
++/* SDC API */
++int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp,
++ uint32_t pixel_clk,
++ uint16_t width, uint16_t height,
++ uint32_t pixel_fmt,
++ uint16_t h_start_width, uint16_t h_sync_width,
++ uint16_t h_end_width, uint16_t v_start_width,
++ uint16_t v_sync_width, uint16_t v_end_width,
++ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
++
++void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp);
++
++int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos,
++ int16_t y_pos);
++int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos,
++ int16_t *y_pos);
++int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ uint8_t alpha);
++int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ uint32_t colorKey);
++int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ int constk[], int slopek[]);
++
++int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
++ uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig);
++void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset);
++void ipu_reset_disp_panel(struct ipu_soc *ipu);
++
++/* CMOS Sensor Interface API */
++int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
++ uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig);
++
++int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi);
++
++int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait);
++
++static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi,
++ bool flag, bool wait)
++{
++ return ipu_csi_enable_mclk(ipu, csi, flag, wait);
++}
++
++int ipu_csi_read_mclk_flag(void);
++
++void ipu_csi_flash_strobe(bool flag);
++
++void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi);
++
++void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi);
++
++void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi);
++
++uint32_t bytes_per_pixel(uint32_t fmt);
++
++bool ipu_ch_param_bad_alpha_pos(uint32_t fmt);
++
++struct ipuv3_fb_platform_data {
++ char disp_dev[32];
++ u32 interface_pix_fmt;
++ char *mode_str;
++ int default_bpp;
++ bool int_clk;
++
++ /* reserved mem */
++ resource_size_t res_base[2];
++ resource_size_t res_size[2];
++
++ /*
++ * Late init to avoid display channel being
++ * re-initialized as we've probably setup the
++ * channel in bootloader.
++ */
++ bool late_init;
++};
++
++#endif /* __LINUX_IPU_V3_H_ */
+diff -Nur linux-3.10.30.orig/include/linux/irqchip/arm-gic.h linux-linaro-stable-mx6/include/linux/irqchip/arm-gic.h
+--- linux-3.10.30.orig/include/linux/irqchip/arm-gic.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/irqchip/arm-gic.h 2014-05-15 20:34:14.574133281 +0200
+@@ -31,6 +31,8 @@
+ #define GIC_DIST_TARGET 0x800
+ #define GIC_DIST_CONFIG 0xc00
+ #define GIC_DIST_SOFTINT 0xf00
++#define GIC_DIST_SGI_PENDING_CLEAR 0xf10
++#define GIC_DIST_SGI_PENDING_SET 0xf20
+
+ #define GICH_HCR 0x0
+ #define GICH_VTR 0x4
+@@ -67,12 +69,19 @@
+ u32 offset, struct device_node *);
+ void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
+
++void gic_cpu_if_down(void);
++
+ static inline void gic_init(unsigned int nr, int start,
+ void __iomem *dist , void __iomem *cpu)
+ {
+ gic_init_bases(nr, start, dist, cpu, 0, NULL);
+ }
+
++void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
++int gic_get_cpu_id(unsigned int cpu);
++void gic_migrate_target(unsigned int new_cpu_id);
++unsigned long gic_get_sgir_physaddr(void);
++
+ #endif /* __ASSEMBLY */
+
+ #endif
+diff -Nur linux-3.10.30.orig/include/linux/isl29023.h linux-linaro-stable-mx6/include/linux/isl29023.h
+--- linux-3.10.30.orig/include/linux/isl29023.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/isl29023.h 2014-05-15 20:34:14.574133281 +0200
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __ISL29023_H__
++#define __ISL29023_H__
++
++#include <linux/types.h>
++
++#define ISL29023_PD_MODE 0x0
++#define ISL29023_ALS_ONCE_MODE 0x1
++#define ISL29023_IR_ONCE_MODE 0x2
++#define ISL29023_ALS_CONT_MODE 0x5
++#define ISL29023_IR_CONT_MODE 0x6
++
++#define ISL29023_INT_PERSISTS_1 0x0
++#define ISL29023_INT_PERSISTS_4 0x1
++#define ISL29023_INT_PERSISTS_8 0x2
++#define ISL29023_INT_PERSISTS_16 0x3
++
++#define ISL29023_RES_16 0x0
++#define ISL29023_RES_12 0x1
++#define ISL29023_RES_8 0x2
++#define ISL29023_RES_4 0x3
++
++#define ISL29023_RANGE_1K 0x0
++#define ISL29023_RANGE_4K 0x1
++#define ISL29023_RANGE_16K 0x2
++#define ISL29023_RANGE_64K 0x3
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/mfd/max17135.h linux-linaro-stable-mx6/include/linux/mfd/max17135.h
+--- linux-3.10.30.orig/include/linux/mfd/max17135.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mfd/max17135.h 2014-05-15 20:34:14.638133742 +0200
+@@ -0,0 +1,220 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef __LINUX_REGULATOR_MAX17135_H_
++#define __LINUX_REGULATOR_MAX17135_H_
++
++/*
++ * PMIC Register Addresses
++ */
++enum {
++ REG_MAX17135_EXT_TEMP = 0x0,
++ REG_MAX17135_CONFIG,
++ REG_MAX17135_INT_TEMP = 0x4,
++ REG_MAX17135_STATUS,
++ REG_MAX17135_PRODUCT_REV,
++ REG_MAX17135_PRODUCT_ID,
++ REG_MAX17135_DVR,
++ REG_MAX17135_ENABLE,
++ REG_MAX17135_FAULT, /*0x0A*/
++ REG_MAX17135_HVINP,
++ REG_MAX17135_PRGM_CTRL,
++ REG_MAX17135_TIMING1 = 0x10, /* Timing regs base address is 0x10 */
++ REG_MAX17135_TIMING2,
++ REG_MAX17135_TIMING3,
++ REG_MAX17135_TIMING4,
++ REG_MAX17135_TIMING5,
++ REG_MAX17135_TIMING6,
++ REG_MAX17135_TIMING7,
++ REG_MAX17135_TIMING8,
++};
++#define MAX17135_REG_NUM 21
++#define MAX17135_MAX_REGISTER 0xFF
++
++/*
++ * Bitfield macros that use rely on bitfield width/shift information.
++ */
++#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH))
++#define BITFVAL(field, val) ((val) << (field ## _LSH))
++#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH))
++
++/*
++ * Shift and width values for each register bitfield
++ */
++#define EXT_TEMP_LSH 7
++#define EXT_TEMP_WID 9
++
++#define THERMAL_SHUTDOWN_LSH 0
++#define THERMAL_SHUTDOWN_WID 1
++
++#define INT_TEMP_LSH 7
++#define INT_TEMP_WID 9
++
++#define STAT_BUSY_LSH 0
++#define STAT_BUSY_WID 1
++#define STAT_OPEN_LSH 1
++#define STAT_OPEN_WID 1
++#define STAT_SHRT_LSH 2
++#define STAT_SHRT_WID 1
++
++#define PROD_REV_LSH 0
++#define PROD_REV_WID 8
++
++#define PROD_ID_LSH 0
++#define PROD_ID_WID 8
++
++#define DVR_LSH 0
++#define DVR_WID 8
++
++#define ENABLE_LSH 0
++#define ENABLE_WID 1
++#define VCOM_ENABLE_LSH 1
++#define VCOM_ENABLE_WID 1
++
++#define FAULT_FBPG_LSH 0
++#define FAULT_FBPG_WID 1
++#define FAULT_HVINP_LSH 1
++#define FAULT_HVINP_WID 1
++#define FAULT_HVINN_LSH 2
++#define FAULT_HVINN_WID 1
++#define FAULT_FBNG_LSH 3
++#define FAULT_FBNG_WID 1
++#define FAULT_HVINPSC_LSH 4
++#define FAULT_HVINPSC_WID 1
++#define FAULT_HVINNSC_LSH 5
++#define FAULT_HVINNSC_WID 1
++#define FAULT_OT_LSH 6
++#define FAULT_OT_WID 1
++#define FAULT_POK_LSH 7
++#define FAULT_POK_WID 1
++
++#define HVINP_LSH 0
++#define HVINP_WID 4
++
++#define CTRL_DVR_LSH 0
++#define CTRL_DVR_WID 1
++#define CTRL_TIMING_LSH 1
++#define CTRL_TIMING_WID 1
++
++#define TIMING1_LSH 0
++#define TIMING1_WID 8
++#define TIMING2_LSH 0
++#define TIMING2_WID 8
++#define TIMING3_LSH 0
++#define TIMING3_WID 8
++#define TIMING4_LSH 0
++#define TIMING4_WID 8
++#define TIMING5_LSH 0
++#define TIMING5_WID 8
++#define TIMING6_LSH 0
++#define TIMING6_WID 8
++#define TIMING7_LSH 0
++#define TIMING7_WID 8
++#define TIMING8_LSH 0
++#define TIMING8_WID 8
++
++struct max17135 {
++ /* chip revision */
++ int rev;
++
++ struct device *dev;
++ struct max17135_platform_data *pdata;
++
++ /* Platform connection */
++ struct i2c_client *i2c_client;
++
++ /* Timings */
++ unsigned int gvee_pwrup;
++ unsigned int vneg_pwrup;
++ unsigned int vpos_pwrup;
++ unsigned int gvdd_pwrup;
++ unsigned int gvdd_pwrdn;
++ unsigned int vpos_pwrdn;
++ unsigned int vneg_pwrdn;
++ unsigned int gvee_pwrdn;
++
++ /* GPIOs */
++ int gpio_pmic_pwrgood;
++ int gpio_pmic_vcom_ctrl;
++ int gpio_pmic_wakeup;
++ int gpio_pmic_v3p3;
++ int gpio_pmic_intr;
++
++ /* MAX17135 part variables */
++ int pass_num;
++ int vcom_uV;
++
++ /* One-time VCOM setup marker */
++ bool vcom_setup;
++
++ /* powerup/powerdown wait time */
++ int max_wait;
++};
++
++enum {
++ /* In alphabetical order */
++ MAX17135_DISPLAY, /* virtual master enable */
++ MAX17135_GVDD,
++ MAX17135_GVEE,
++ MAX17135_HVINN,
++ MAX17135_HVINP,
++ MAX17135_VCOM,
++ MAX17135_VNEG,
++ MAX17135_VPOS,
++ MAX17135_V3P3,
++ MAX17135_NUM_REGULATORS,
++};
++
++/*
++ * Declarations
++ */
++struct regulator_init_data;
++struct max17135_regulator_data;
++
++struct max17135_platform_data {
++ unsigned int gvee_pwrup;
++ unsigned int vneg_pwrup;
++ unsigned int vpos_pwrup;
++ unsigned int gvdd_pwrup;
++ unsigned int gvdd_pwrdn;
++ unsigned int vpos_pwrdn;
++ unsigned int vneg_pwrdn;
++ unsigned int gvee_pwrdn;
++ int gpio_pmic_pwrgood;
++ int gpio_pmic_vcom_ctrl;
++ int gpio_pmic_wakeup;
++ int gpio_pmic_v3p3;
++ int gpio_pmic_intr;
++ int pass_num;
++ int vcom_uV;
++
++ /* PMIC */
++ struct max17135_regulator_data *regulators;
++ int num_regulators;
++};
++
++struct max17135_regulator_data {
++ int id;
++ struct regulator_init_data *initdata;
++ struct device_node *reg_node;
++};
++
++int max17135_reg_read(int reg_num, unsigned int *reg_val);
++int max17135_reg_write(int reg_num, const unsigned int reg_val);
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/mfd/mxc-hdmi-core.h linux-linaro-stable-mx6/include/linux/mfd/mxc-hdmi-core.h
+--- linux-3.10.30.orig/include/linux/mfd/mxc-hdmi-core.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mfd/mxc-hdmi-core.h 2014-05-15 20:34:14.658133885 +0200
+@@ -0,0 +1,64 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef __LINUX_MXC_HDMI_CORE_H_
++#define __LINUX_MXC_HDMI_CORE_H_
++
++#include <video/mxc_edid.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#define IRQ_DISABLE_SUCCEED 0
++#define IRQ_DISABLE_FAIL 1
++
++bool hdmi_check_overflow(void);
++
++u8 hdmi_readb(unsigned int reg);
++void hdmi_writeb(u8 value, unsigned int reg);
++void hdmi_mask_writeb(u8 data, unsigned int addr, u8 shift, u8 mask);
++unsigned int hdmi_read4(unsigned int reg);
++void hdmi_write4(unsigned int value, unsigned int reg);
++
++void hdmi_irq_init(void);
++void hdmi_irq_enable(int irq);
++unsigned int hdmi_irq_disable(int irq);
++
++void hdmi_set_sample_rate(unsigned int rate);
++void hdmi_set_dma_mode(unsigned int dma_running);
++void hdmi_init_clk_regenerator(void);
++void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock);
++
++void hdmi_set_edid_cfg(struct mxc_edid_cfg *cfg);
++void hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg);
++
++extern int mxc_hdmi_ipu_id;
++extern int mxc_hdmi_disp_id;
++
++void hdmi_set_registered(int registered);
++int hdmi_get_registered(void);
++int mxc_hdmi_abort_stream(void);
++int mxc_hdmi_register_audio(struct snd_pcm_substream *substream);
++void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream);
++unsigned int hdmi_set_cable_state(unsigned int state);
++unsigned int hdmi_set_blank_state(unsigned int state);
++int check_hdmi_state(void);
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h linux-linaro-stable-mx6/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+--- linux-3.10.30.orig/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h 2014-05-15 20:34:14.694134145 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -103,15 +103,15 @@
+ #define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
+ #define IMX6Q_GPR1_EXC_MON_OKAY 0x0
+ #define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
+-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
+-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
+-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
+-#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
+-#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
+-#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
+-#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
++#define IMX6Q_GPR1_ENET_CLK_SEL_MASK BIT(21)
++#define IMX6Q_GPR1_ENET_CLK_SEL_PAD 0
++#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP BIT(21)
++#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(20)
+ #define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
+-#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
++#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
++#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(19)
++#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
++#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
+ #define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
+ #define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
+ #define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
+@@ -122,7 +122,9 @@
+ #define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
+ #define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
+ #define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
+-#define IMX6Q_GPR1_GINT BIT(12)
++#define IMX6Q_GPR1_GINT_MASK BIT(12)
++#define IMX6Q_GPR1_GINT_CLEAR 0x0
++#define IMX6Q_GPR1_GINT_ASSERT BIT(12)
+ #define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
+ #define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
+ #define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
+@@ -212,6 +214,7 @@
+ #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)
+ #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4)
+ #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4)
++#define IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT 2
+ #define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2)
+ #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2)
+ #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2)
+@@ -241,6 +244,12 @@
+
+ #define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
+
++#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
++#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6)
++#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0)
++
+ #define IMX6Q_GPR9_TZASC2_BYP BIT(1)
+ #define IMX6Q_GPR9_TZASC1_BYP BIT(0)
+
+@@ -273,47 +282,101 @@
+ #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
+ #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
+ #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
++#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
+ #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
++#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
+
+ #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
+ #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
+ #define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
+ #define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
+-#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
+-#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
+-#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
+-#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
+-#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
+-#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
+-#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
+-#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
+-#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
+-#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
+-#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
+-#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
+-#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
+-#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
+-#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
+-#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
+-#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK (0x7 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB (0x0 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB (0x1 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB (0x2 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB (0x3 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB (0x4 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB (0x5 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB (0x6 << 24)
++#define IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB (0x7 << 24)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK (0x1f << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1I (0x10 << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1M (0x10 << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA1X (0x1a << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2I (0x12 << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M (0x12 << 19)
++#define IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2X (0x1a << 19)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK (0x7 << 16)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F (0x0 << 16)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F (0x1 << 16)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F (0x2 << 16)
++#define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F (0x3 << 16)
++#define IMX6Q_GPR13_SATA_SPD_MODE_MASK BIT(15)
++#define IMX6Q_GPR13_SATA_SPD_MODE_1P5G 0x0
++#define IMX6Q_GPR13_SATA_SPD_MODE_3P0G BIT(15)
++#define IMX6Q_GPR13_SATA_MPLL_SS_EN BIT(14)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_MASK (0x7 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_16_16 (0x0 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_14_16 (0x1 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_12_16 (0x2 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_10_16 (0x3 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_9_16 (0x4 << 11)
++#define IMX6Q_GPR13_SATA_TX_ATTEN_8_16 (0x5 << 11)
++#define IMX6Q_GPR13_SATA_TX_BOOST_MASK (0xf << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB (0x0 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB (0x1 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB (0x2 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB (0x3 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB (0x4 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB (0x5 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB (0x6 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB (0x7 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB (0x8 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB (0x9 << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB (0xa << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB (0xb << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB (0xc << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB (0xd << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB (0xe << 7)
++#define IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB (0xf << 7)
++#define IMX6Q_GPR13_SATA_TX_LVL_MASK (0x1f << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_937_V (0x00 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_947_V (0x01 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_957_V (0x02 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_966_V (0x03 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_976_V (0x04 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_986_V (0x05 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_0_996_V (0x06 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_005_V (0x07 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_015_V (0x08 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_025_V (0x09 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_035_V (0x0a << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_045_V (0x0b << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_054_V (0x0c << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_064_V (0x0d << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_074_V (0x0e << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_084_V (0x0f << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_094_V (0x10 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_104_V (0x11 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_113_V (0x12 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_123_V (0x13 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_133_V (0x14 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_143_V (0x15 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_152_V (0x16 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_162_V (0x17 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_172_V (0x18 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_182_V (0x19 << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_191_V (0x1a << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_201_V (0x1b << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_211_V (0x1c << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_221_V (0x1d << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_230_V (0x1e << 2)
++#define IMX6Q_GPR13_SATA_TX_LVL_1_240_V (0x1f << 2)
++#define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
++#define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
++
++/* For imx6sl iomux gpr register field define */
++#define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
++#define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+
+ #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
+diff -Nur linux-3.10.30.orig/include/linux/mipi_csi2.h linux-linaro-stable-mx6/include/linux/mipi_csi2.h
+--- linux-3.10.30.orig/include/linux/mipi_csi2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mipi_csi2.h 2014-05-15 20:34:14.794134865 +0200
+@@ -0,0 +1,91 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __INCLUDE_MIPI_CSI2_H
++#define __INCLUDE_MIPI_CSI2_H
++
++/* mipi csi2 register */
++#define CSI2_VERSION 0x000
++#define CSI2_N_LANES (0x004/4)
++#define CSI2_PHY_SHUTDOWNZ (0x008/4)
++#define CSI2_DPHY_RSTZ (0x00c/4)
++#define CSI2_RESETN (0x010/4)
++#define CSI2_PHY_STATE (0x014/4)
++#define CSI2_DATA_IDS_1 (0x018/4)
++#define CSI2_DATA_IDS_2 (0x01c/4)
++#define CSI2_ERR1 (0x020/4)
++#define CSI2_ERR2 (0x024/4)
++#define CSI2_MSK1 (0x028/4)
++#define CSI2_MSK2 (0x02c/4)
++#define CSI2_PHY_TST_CTRL0 (0x030/4)
++#define CSI2_PHY_TST_CTRL1 (0x034/4)
++#define CSI2_SFT_RESET (0xf00/4)
++
++/* mipi data type */
++#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */
++#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */
++#define MIPI_DT_YUV422 0x1e /* UYVY... */
++#define MIPI_DT_RGB444 0x20
++#define MIPI_DT_RGB555 0x21
++#define MIPI_DT_RGB565 0x22
++#define MIPI_DT_RGB666 0x23
++#define MIPI_DT_RGB888 0x24
++#define MIPI_DT_RAW6 0x28
++#define MIPI_DT_RAW7 0x29
++#define MIPI_DT_RAW8 0x2a
++#define MIPI_DT_RAW10 0x2b
++#define MIPI_DT_RAW12 0x2c
++#define MIPI_DT_RAW14 0x2d
++
++
++struct mipi_csi2_info;
++/* mipi csi2 API */
++struct mipi_csi2_info *mipi_csi2_get_info(void);
++
++bool mipi_csi2_enable(struct mipi_csi2_info *info);
++
++bool mipi_csi2_disable(struct mipi_csi2_info *info);
++
++bool mipi_csi2_get_status(struct mipi_csi2_info *info);
++
++int mipi_csi2_get_bind_ipu(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_bind_csi(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_virtual_channel(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_set_lanes(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info,
++ unsigned int datatype);
++
++unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info);
++
++int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info);
++
++void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info);
++
++int mipi_csi2_reset(struct mipi_csi2_info *info);
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/mipi_dsi.h linux-linaro-stable-mx6/include/linux/mipi_dsi.h
+--- linux-3.10.30.orig/include/linux/mipi_dsi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mipi_dsi.h 2014-05-15 20:34:14.794134865 +0200
+@@ -0,0 +1,171 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __INCLUDE_MIPI_DSI_H
++#define __INCLUDE_MIPI_DSI_H
++
++#define MIPI_DSI_VERSION (0x000)
++#define MIPI_DSI_PWR_UP (0x004)
++#define MIPI_DSI_CLKMGR_CFG (0x008)
++#define MIPI_DSI_DPI_CFG (0x00c)
++#define MIPI_DSI_DBI_CFG (0x010)
++#define MIPI_DSI_DBIS_CMDSIZE (0x014)
++#define MIPI_DSI_PCKHDL_CFG (0x018)
++#define MIPI_DSI_VID_MODE_CFG (0x01c)
++#define MIPI_DSI_VID_PKT_CFG (0x020)
++#define MIPI_DSI_CMD_MODE_CFG (0x024)
++#define MIPI_DSI_TMR_LINE_CFG (0x028)
++#define MIPI_DSI_VTIMING_CFG (0x02c)
++#define MIPI_DSI_PHY_TMR_CFG (0x030)
++#define MIPI_DSI_GEN_HDR (0x034)
++#define MIPI_DSI_GEN_PLD_DATA (0x038)
++#define MIPI_DSI_CMD_PKT_STATUS (0x03c)
++#define MIPI_DSI_TO_CNT_CFG (0x040)
++#define MIPI_DSI_ERROR_ST0 (0x044)
++#define MIPI_DSI_ERROR_ST1 (0x048)
++#define MIPI_DSI_ERROR_MSK0 (0x04c)
++#define MIPI_DSI_ERROR_MSK1 (0x050)
++#define MIPI_DSI_PHY_RSTZ (0x054)
++#define MIPI_DSI_PHY_IF_CFG (0x058)
++#define MIPI_DSI_PHY_IF_CTRL (0x05c)
++#define MIPI_DSI_PHY_STATUS (0x060)
++#define MIPI_DSI_PHY_TST_CTRL0 (0x064)
++#define MIPI_DSI_PHY_TST_CTRL1 (0x068)
++
++#define DSI_PWRUP_RESET (0x0 << 0)
++#define DSI_PWRUP_POWERUP (0x1 << 0)
++
++#define DSI_DPI_CFG_VID_SHIFT (0)
++#define DSI_DPI_CFG_VID_MASK (0x3)
++#define DSI_DPI_CFG_COLORCODE_SHIFT (2)
++#define DSI_DPI_CFG_COLORCODE_MASK (0x7)
++#define DSI_DPI_CFG_DATAEN_ACT_LOW (0x1 << 5)
++#define DSI_DPI_CFG_DATAEN_ACT_HIGH (0x0 << 5)
++#define DSI_DPI_CFG_VSYNC_ACT_LOW (0x1 << 6)
++#define DSI_DPI_CFG_VSYNC_ACT_HIGH (0x0 << 6)
++#define DSI_DPI_CFG_HSYNC_ACT_LOW (0x1 << 7)
++#define DSI_DPI_CFG_HSYNC_ACT_HIGH (0x0 << 7)
++#define DSI_DPI_CFG_SHUTD_ACT_LOW (0x1 << 8)
++#define DSI_DPI_CFG_SHUTD_ACT_HIGH (0x0 << 8)
++#define DSI_DPI_CFG_COLORMODE_ACT_LOW (0x1 << 9)
++#define DSI_DPI_CFG_COLORMODE_ACT_HIGH (0x0 << 9)
++#define DSI_DPI_CFG_EN18LOOSELY (0x1 << 10)
++
++#define DSI_PCKHDL_CFG_EN_EOTP_TX (0x1 << 0)
++#define DSI_PCKHDL_CFG_EN_EOTP_RX (0x1 << 1)
++#define DSI_PCKHDL_CFG_EN_BTA (0x1 << 2)
++#define DSI_PCKHDL_CFG_EN_ECC_RX (0x1 << 3)
++#define DSI_PCKHDL_CFG_EN_CRC_RX (0x1 << 4)
++#define DSI_PCKHDL_CFG_GEN_VID_RX_MASK (0x3)
++#define DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT (5)
++
++#define DSI_VID_MODE_CFG_EN (0x1 << 0)
++#define DSI_VID_MODE_CFG_EN_BURSTMODE (0x3 << 1)
++#define DSI_VID_MODE_CFG_TYPE_MASK (0x3)
++#define DSI_VID_MODE_CFG_TYPE_SHIFT (1)
++#define DSI_VID_MODE_CFG_EN_LP_VSA (0x1 << 3)
++#define DSI_VID_MODE_CFG_EN_LP_VBP (0x1 << 4)
++#define DSI_VID_MODE_CFG_EN_LP_VFP (0x1 << 5)
++#define DSI_VID_MODE_CFG_EN_LP_VACT (0x1 << 6)
++#define DSI_VID_MODE_CFG_EN_LP_HBP (0x1 << 7)
++#define DSI_VID_MODE_CFG_EN_LP_HFP (0x1 << 8)
++#define DSI_VID_MODE_CFG_EN_MULTI_PKT (0x1 << 9)
++#define DSI_VID_MODE_CFG_EN_NULL_PKT (0x1 << 10)
++#define DSI_VID_MODE_CFG_EN_FRAME_ACK (0x1 << 11)
++#define DSI_VID_MODE_CFG_EN_LP_MODE (DSI_VID_MODE_CFG_EN_LP_VSA | \
++ DSI_VID_MODE_CFG_EN_LP_VBP | \
++ DSI_VID_MODE_CFG_EN_LP_VFP | \
++ DSI_VID_MODE_CFG_EN_LP_HFP | \
++ DSI_VID_MODE_CFG_EN_LP_HBP | \
++ DSI_VID_MODE_CFG_EN_LP_VACT)
++
++
++
++#define DSI_VID_PKT_CFG_VID_PKT_SZ_MASK (0x7ff)
++#define DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT (0)
++#define DSI_VID_PKT_CFG_NUM_CHUNKS_MASK (0x3ff)
++#define DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT (11)
++#define DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK (0x3ff)
++#define DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT (21)
++
++#define MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER (0x1FFF)
++#define MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE (0x1 << 0)
++
++#define DSI_TME_LINE_CFG_HSA_TIME_MASK (0x1ff)
++#define DSI_TME_LINE_CFG_HSA_TIME_SHIFT (0)
++#define DSI_TME_LINE_CFG_HBP_TIME_MASK (0x1ff)
++#define DSI_TME_LINE_CFG_HBP_TIME_SHIFT (9)
++#define DSI_TME_LINE_CFG_HLINE_TIME_MASK (0x3fff)
++#define DSI_TME_LINE_CFG_HLINE_TIME_SHIFT (18)
++
++#define DSI_VTIMING_CFG_VSA_LINES_MASK (0xf)
++#define DSI_VTIMING_CFG_VSA_LINES_SHIFT (0)
++#define DSI_VTIMING_CFG_VBP_LINES_MASK (0x3f)
++#define DSI_VTIMING_CFG_VBP_LINES_SHIFT (4)
++#define DSI_VTIMING_CFG_VFP_LINES_MASK (0x3f)
++#define DSI_VTIMING_CFG_VFP_LINES_SHIFT (10)
++#define DSI_VTIMING_CFG_V_ACT_LINES_MASK (0x7ff)
++#define DSI_VTIMING_CFG_V_ACT_LINES_SHIFT (16)
++
++#define DSI_PHY_TMR_CFG_BTA_TIME_MASK (0xfff)
++#define DSI_PHY_TMR_CFG_BTA_TIME_SHIFT (0)
++#define DSI_PHY_TMR_CFG_LP2HS_TIME_MASK (0xff)
++#define DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT (12)
++#define DSI_PHY_TMR_CFG_HS2LP_TIME_MASK (0xff)
++#define DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT (20)
++
++#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3)
++#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0)
++#define DSI_PHY_IF_CFG_WAIT_TIME_MASK (0xff)
++#define DSI_PHY_IF_CFG_WAIT_TIME_SHIFT (2)
++
++#define DSI_PHY_RSTZ_EN_CLK (0x1 << 2)
++#define DSI_PHY_RSTZ_DISABLE_RST (0x1 << 1)
++#define DSI_PHY_RSTZ_DISABLE_SHUTDOWN (0x1 << 0)
++#define DSI_PHY_RSTZ_RST (0x0)
++
++#define DSI_PHY_STATUS_LOCK (0x1 << 0)
++#define DSI_PHY_STATUS_STOPSTATE_CLK_LANE (0x1 << 2)
++
++#define DSI_GEN_HDR_TYPE_MASK (0xff)
++#define DSI_GEN_HDR_TYPE_SHIFT (0)
++#define DSI_GEN_HDR_DATA_MASK (0xffff)
++#define DSI_GEN_HDR_DATA_SHIFT (8)
++
++#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY (0x1 << 0)
++#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL (0x1 << 1)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (0x1 << 2)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL (0x1 << 3)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (0x1 << 4)
++#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (0x1 << 6)
++
++#define DSI_ERROR_MSK0_ALL_MASK (0x1fffff)
++#define DSI_ERROR_MSK1_ALL_MASK (0x3ffff)
++
++#define DSI_PHY_IF_CTRL_RESET (0x0)
++#define DSI_PHY_IF_CTRL_TX_REQ_CLK_HS (0x1 << 0)
++#define DSI_PHY_IF_CTRL_TX_REQ_CLK_ULPS (0x1 << 1)
++#define DSI_PHY_IF_CTRL_TX_EXIT_CLK_ULPS (0x1 << 2)
++#define DSI_PHY_IF_CTRL_TX_REQ_DATA_ULPS (0x1 << 3)
++#define DSI_PHY_IF_CTRL_TX_EXIT_DATA_ULPS (0x1 << 4)
++#define DSI_PHY_IF_CTRL_TX_TRIG_MASK (0xF)
++#define DSI_PHY_IF_CTRL_TX_TRIG_SHIFT (5)
++
++#define DSI_PHY_CLK_INIT_COMMAND (0x44)
++#define DSI_GEN_PLD_DATA_BUF_SIZE (0x4)
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/mmc/card.h linux-linaro-stable-mx6/include/linux/mmc/card.h
+--- linux-3.10.30.orig/include/linux/mmc/card.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mmc/card.h 2014-05-15 20:34:14.798134894 +0200
+@@ -86,10 +86,13 @@
+ unsigned int data_sector_size; /* 512 bytes or 4KB */
+ unsigned int data_tag_unit_size; /* DATA TAG UNIT size */
+ unsigned int boot_ro_lock; /* ro lock support */
++ unsigned int boot_size;
+ bool boot_ro_lockable;
+ u8 raw_exception_status; /* 54 */
+ u8 raw_partition_support; /* 160 */
+ u8 raw_rpmb_size_mult; /* 168 */
++ u8 boot_bus_width; /* 177 */
++ u8 boot_config; /* 179 */
+ u8 raw_erased_mem_count; /* 181 */
+ u8 raw_ext_csd_structure; /* 194 */
+ u8 raw_card_type; /* 196 */
+@@ -98,6 +101,7 @@
+ u8 raw_hc_erase_gap_size; /* 221 */
+ u8 raw_erase_timeout_mult; /* 223 */
+ u8 raw_hc_erase_grp_size; /* 224 */
++ u8 boot_info; /* 228 */
+ u8 raw_sec_trim_mult; /* 229 */
+ u8 raw_sec_erase_mult; /* 230 */
+ u8 raw_sec_feature_support;/* 231 */
+diff -Nur linux-3.10.30.orig/include/linux/mmc/core.h linux-linaro-stable-mx6/include/linux/mmc/core.h
+--- linux-3.10.30.orig/include/linux/mmc/core.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mmc/core.h 2014-05-15 20:34:14.798134894 +0200
+@@ -96,6 +96,8 @@
+ */
+
+ unsigned int cmd_timeout_ms; /* in milliseconds */
++ /* Set this flag only for blocking sanitize request */
++ bool sanitize_busy;
+
+ struct mmc_data *data; /* data segment associated with cmd */
+ struct mmc_request *mrq; /* associated request */
+diff -Nur linux-3.10.30.orig/include/linux/mmc/host.h linux-linaro-stable-mx6/include/linux/mmc/host.h
+--- linux-3.10.30.orig/include/linux/mmc/host.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mmc/host.h 2014-05-15 20:34:14.798134894 +0200
+@@ -281,6 +281,8 @@
+ #define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \
+ MMC_CAP2_PACKED_WR)
+ #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */
++#define MMC_CAP2_SANITIZE (1 << 15) /* Support Sanitize */
++#define MMC_CAP2_SDIO_NOTHREAD (1 << 16) /* don't have separate thread */
+
+ mmc_pm_flag_t pm_caps; /* supported pm features */
+
+@@ -296,6 +298,11 @@
+ unsigned long clkgate_delay;
+ #endif
+
++ /* card specific properties to deal with power and reset */
++ struct regulator *card_regulator; /* External VCC needed by the card */
++ struct gpio_desc *card_reset_gpios[2]; /* External resets, active low */
++ struct clk *card_clk; /* External clock needed by the card */
++
+ /* host specific block data */
+ unsigned int max_seg_size; /* see blk_queue_max_segment_size */
+ unsigned short max_segs; /* see blk_queue_max_segments */
+@@ -369,7 +376,7 @@
+ int mmc_add_host(struct mmc_host *);
+ void mmc_remove_host(struct mmc_host *);
+ void mmc_free_host(struct mmc_host *);
+-void mmc_of_parse(struct mmc_host *host);
++int mmc_of_parse(struct mmc_host *host);
+
+ static inline void *mmc_priv(struct mmc_host *host)
+ {
+@@ -400,6 +407,8 @@
+ wake_up_process(host->sdio_irq_thread);
+ }
+
++void sdio_run_irqs(struct mmc_host *host);
++
+ #ifdef CONFIG_REGULATOR
+ int mmc_regulator_get_ocrmask(struct regulator *supply);
+ int mmc_regulator_set_ocr(struct mmc_host *mmc,
+diff -Nur linux-3.10.30.orig/include/linux/mmc/mmc.h linux-linaro-stable-mx6/include/linux/mmc/mmc.h
+--- linux-3.10.30.orig/include/linux/mmc/mmc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mmc/mmc.h 2014-05-15 20:34:14.798134894 +0200
+@@ -292,6 +292,7 @@
+ #define EXT_CSD_RPMB_MULT 168 /* RO */
+ #define EXT_CSD_BOOT_WP 173 /* R/W */
+ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
++#define EXT_CSD_BOOT_BUS_WIDTH 177 /* R/W */
+ #define EXT_CSD_PART_CONFIG 179 /* R/W */
+ #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
+ #define EXT_CSD_BUS_WIDTH 183 /* R/W */
+@@ -313,6 +314,7 @@
+ #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
+ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
+ #define EXT_CSD_BOOT_MULT 226 /* RO */
++#define EXT_CSD_BOOT_INFO 228 /* RO, 1 bytes */
+ #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
+ #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
+ #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
+@@ -378,6 +380,29 @@
+ #define EXT_CSD_SEC_GB_CL_EN BIT(4)
+ #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
+
++#define EXT_CSD_BOOT_BUS_WIDTH_MASK (0x1F)
++#define EXT_CSD_BOOT_BUS_WIDTH_MODE_MASK (0x3 << 3)
++#define EXT_CSD_BOOT_BUS_WIDTH_MODE_SDR_NORMAL (0x0)
++#define EXT_CSD_BOOT_BUS_WIDTH_MODE_SDR_HIGH (0x1)
++#define EXT_CSD_BOOT_BUS_WIDTH_MODE_DDR (0x2)
++#define EXT_CSD_BOOT_BUS_WIDTH_RST_WIDTH (1 << 2)
++#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH_MASK (0x3)
++#define EXT_CSD_BOOT_BUS_WIDTH_1_SDR_4_DDR (0x0)
++#define EXT_CSD_BOOT_BUS_WIDTH_4_SDR_4_DDR (0x1)
++#define EXT_CSD_BOOT_BUS_WIDTH_8_SDR_8_DDR (0x2)
++
++#define EXT_CSD_BOOT_ACK_ENABLE (0x1 << 6)
++#define EXT_CSD_BOOT_PARTITION_ENABLE_MASK (0x7 << 3)
++#define EXT_CSD_BOOT_PARTITION_DISABLE (0x0)
++#define EXT_CSD_BOOT_PARTITION_PART1 (0x1 << 3)
++#define EXT_CSD_BOOT_PARTITION_PART2 (0x2 << 3)
++#define EXT_CSD_BOOT_PARTITION_USER (0x7 << 3)
++
++#define EXT_CSD_BOOT_PARTITION_ACCESS_MASK (0x7)
++#define EXT_CSD_BOOT_PARTITION_ACCESS_DISABLE (0x0)
++#define EXT_CSD_BOOT_PARTITION_ACCESS_PART1 (0x1)
++#define EXT_CSD_BOOT_PARTITION_ACCESS_PART2 (0x2)
++
+ #define EXT_CSD_RST_N_EN_MASK 0x3
+ #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
+
+diff -Nur linux-3.10.30.orig/include/linux/mmc/sdhci.h linux-linaro-stable-mx6/include/linux/mmc/sdhci.h
+--- linux-3.10.30.orig/include/linux/mmc/sdhci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mmc/sdhci.h 2014-05-15 20:34:14.798134894 +0200
+@@ -57,12 +57,8 @@
+ #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
+ /* Controller reports inverted write-protect state */
+ #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
+-/* Controller has nonstandard clock management */
+-#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
+ /* Controller does not like fast PIO transfers */
+ #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
+-/* Controller losing signal/interrupt enable states after reset */
+-#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
+ /* Controller has to be forced to use block size of 2048 bytes */
+ #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
+ /* Controller cannot do multi-block transfers */
+@@ -95,6 +91,8 @@
+ /* The system physically doesn't support 1.8v, even if the host does */
+ #define SDHCI_QUIRK2_NO_1_8_V (1<<2)
+ #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
++#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
++#define SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER (1<<5)
+
+ int irq; /* Device IRQ */
+ void __iomem *ioaddr; /* Mapped address */
+@@ -126,7 +124,7 @@
+ #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
+ #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
+ #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
+-#define SDHCI_HS200_NEEDS_TUNING (1<<10) /* HS200 needs tuning */
++#define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
+ #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
+
+ unsigned int version; /* SDHCI spec. version */
+@@ -139,6 +137,7 @@
+ u8 pwr; /* Current voltage */
+
+ bool runtime_suspended; /* Host is runtime suspended */
++ bool bus_on; /* Bus power prevents runtime suspend */
+
+ struct mmc_request *mrq; /* Current request */
+ struct mmc_command *cmd; /* Current command */
+@@ -156,8 +155,7 @@
+ dma_addr_t adma_addr; /* Mapped ADMA descr. table */
+ dma_addr_t align_addr; /* Mapped bounce buffer */
+
+- struct tasklet_struct card_tasklet; /* Tasklet structures */
+- struct tasklet_struct finish_tasklet;
++ struct tasklet_struct finish_tasklet; /* Tasklet structures */
+
+ struct timer_list timer; /* Timer for timeouts */
+
+@@ -168,6 +166,13 @@
+ unsigned int ocr_avail_sd;
+ unsigned int ocr_avail_mmc;
+
++ unsigned timing; /* Current timing */
++
++ u32 thread_isr;
++
++ /* cached registers */
++ u32 ier;
++
+ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
+ unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
+
+diff -Nur linux-3.10.30.orig/include/linux/mmc/sdio_ids.h linux-linaro-stable-mx6/include/linux/mmc/sdio_ids.h
+--- linux-3.10.30.orig/include/linux/mmc/sdio_ids.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mmc/sdio_ids.h 2014-05-15 20:34:14.818135038 +0200
+@@ -23,6 +23,15 @@
+ /*
+ * Vendors and devices. Sort key: vendor first, device next.
+ */
++#define SDIO_VENDOR_ID_BROADCOM 0x02d0
++#define SDIO_DEVICE_ID_BROADCOM_43143 43143
++#define SDIO_DEVICE_ID_BROADCOM_43241 0x4324
++#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
++#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
++#define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
++#define SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335
++#define SDIO_DEVICE_ID_BROADCOM_43362 43362
++
+ #define SDIO_VENDOR_ID_INTEL 0x0089
+ #define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX 0x1402
+ #define SDIO_DEVICE_ID_INTEL_IWMC3200WIFI 0x1403
+diff -Nur linux-3.10.30.orig/include/linux/mmc/slot-gpio.h linux-linaro-stable-mx6/include/linux/mmc/slot-gpio.h
+--- linux-3.10.30.orig/include/linux/mmc/slot-gpio.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mmc/slot-gpio.h 2014-05-15 20:34:14.818135038 +0200
+@@ -18,7 +18,8 @@
+ void mmc_gpio_free_ro(struct mmc_host *host);
+
+ int mmc_gpio_get_cd(struct mmc_host *host);
+-int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio);
++int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio,
++ unsigned int debounce);
+ void mmc_gpio_free_cd(struct mmc_host *host);
+
+ #endif
+diff -Nur linux-3.10.30.orig/include/linux/msi.h linux-linaro-stable-mx6/include/linux/msi.h
+--- linux-3.10.30.orig/include/linux/msi.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/msi.h 2014-05-15 20:34:14.822135067 +0200
+@@ -35,6 +35,7 @@
+
+ u32 masked; /* mask bits */
+ unsigned int irq;
++ unsigned int nvec_used; /* number of messages */
+ struct list_head list;
+
+ union {
+@@ -50,12 +51,31 @@
+ };
+
+ /*
+- * The arch hook for setup up msi irqs
++ * The arch hooks to setup up msi irqs. Those functions are
++ * implemented as weak symbols so that they /can/ be overriden by
++ * architecture specific code if needed.
+ */
+ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc);
+ void arch_teardown_msi_irq(unsigned int irq);
+ int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
+ void arch_teardown_msi_irqs(struct pci_dev *dev);
+ int arch_msi_check_device(struct pci_dev* dev, int nvec, int type);
++void arch_restore_msi_irqs(struct pci_dev *dev, int irq);
++
++void default_teardown_msi_irqs(struct pci_dev *dev);
++void default_restore_msi_irqs(struct pci_dev *dev, int irq);
++
++struct msi_chip {
++ struct module *owner;
++ struct device *dev;
++ struct device_node *of_node;
++ struct list_head list;
++
++ int (*setup_irq)(struct msi_chip *chip, struct pci_dev *dev,
++ struct msi_desc *desc);
++ void (*teardown_irq)(struct msi_chip *chip, unsigned int irq);
++ int (*check_device)(struct msi_chip *chip, struct pci_dev *dev,
++ int nvec, int type);
++};
+
+ #endif /* LINUX_MSI_H */
+diff -Nur linux-3.10.30.orig/include/linux/mtd/bbm.h linux-linaro-stable-mx6/include/linux/mtd/bbm.h
+--- linux-3.10.30.orig/include/linux/mtd/bbm.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mtd/bbm.h 2014-05-15 20:34:14.822135067 +0200
+@@ -91,10 +91,6 @@
+ * with NAND_BBT_CREATE.
+ */
+ #define NAND_BBT_CREATE_EMPTY 0x00000400
+-/* Search good / bad pattern through all pages of a block */
+-#define NAND_BBT_SCANALLPAGES 0x00000800
+-/* Scan block empty during good / bad block scan */
+-#define NAND_BBT_SCANEMPTY 0x00001000
+ /* Write bbt if neccecary */
+ #define NAND_BBT_WRITE 0x00002000
+ /* Read and write back block contents when writing bbt */
+diff -Nur linux-3.10.30.orig/include/linux/mtd/map.h linux-linaro-stable-mx6/include/linux/mtd/map.h
+--- linux-3.10.30.orig/include/linux/mtd/map.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mtd/map.h 2014-05-15 20:34:14.822135067 +0200
+@@ -438,7 +438,7 @@
+ if (map->cached)
+ memcpy(to, (char *)map->cached + from, len);
+ else
+- memcpy_fromio(to, map->virt + from, len);
++ memcpy(to, map->virt + from, len);
+ }
+
+ static inline void inline_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
+diff -Nur linux-3.10.30.orig/include/linux/mtd/mtd.h linux-linaro-stable-mx6/include/linux/mtd/mtd.h
+--- linux-3.10.30.orig/include/linux/mtd/mtd.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mtd/mtd.h 2014-05-15 20:34:14.822135067 +0200
+@@ -173,6 +173,9 @@
+ /* ECC layout structure pointer - read only! */
+ struct nand_ecclayout *ecclayout;
+
++ /* the ecc step size. */
++ unsigned int ecc_step_size;
++
+ /* max number of correctible bit errors per ecc step */
+ unsigned int ecc_strength;
+
+@@ -351,6 +354,11 @@
+ return mtd->_read_oob && mtd->_write_oob;
+ }
+
++static inline int mtd_type_is_nand(const struct mtd_info *mtd)
++{
++ return mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH;
++}
++
+ static inline int mtd_can_have_bb(const struct mtd_info *mtd)
+ {
+ return !!mtd->_block_isbad;
+diff -Nur linux-3.10.30.orig/include/linux/mtd/nand.h linux-linaro-stable-mx6/include/linux/mtd/nand.h
+--- linux-3.10.30.orig/include/linux/mtd/nand.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mtd/nand.h 2014-05-15 20:34:14.834135153 +0200
+@@ -56,7 +56,7 @@
+ * is supported now. If you add a chip with bigger oobsize/page
+ * adjust this accordingly.
+ */
+-#define NAND_MAX_OOBSIZE 640
++#define NAND_MAX_OOBSIZE 744
+ #define NAND_MAX_PAGESIZE 8192
+
+ /*
+@@ -198,10 +198,15 @@
+ /* Cell info constants */
+ #define NAND_CI_CHIPNR_MSK 0x03
+ #define NAND_CI_CELLTYPE_MSK 0x0C
++#define NAND_CI_CELLTYPE_SHIFT 2
+
+ /* Keep gcc happy */
+ struct nand_chip;
+
++/* ONFI features */
++#define ONFI_FEATURE_16_BIT_BUS (1 << 0)
++#define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
++
+ /* ONFI timing mode, used in both asynchronous and synchronous mode */
+ #define ONFI_TIMING_MODE_0 (1 << 0)
+ #define ONFI_TIMING_MODE_1 (1 << 1)
+@@ -217,6 +222,9 @@
+ /* ONFI subfeature parameters length */
+ #define ONFI_SUBFEATURE_PARAM_LEN 4
+
++/* ONFI optional commands SET/GET FEATURES supported? */
++#define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
++
+ struct nand_onfi_params {
+ /* rev info and features block */
+ /* 'O' 'N' 'F' 'I' */
+@@ -224,7 +232,10 @@
+ __le16 revision;
+ __le16 features;
+ __le16 opt_cmd;
+- u8 reserved[22];
++ u8 reserved0[2];
++ __le16 ext_param_page_length; /* since ONFI 2.1 */
++ u8 num_of_param_pages; /* since ONFI 2.1 */
++ u8 reserved1[17];
+
+ /* manufacturer information block */
+ char manufacturer[12];
+@@ -281,6 +292,40 @@
+
+ #define ONFI_CRC_BASE 0x4F4E
+
++/* Extended ECC information Block Definition (since ONFI 2.1) */
++struct onfi_ext_ecc_info {
++ u8 ecc_bits;
++ u8 codeword_size;
++ __le16 bb_per_lun;
++ __le16 block_endurance;
++ u8 reserved[2];
++} __packed;
++
++#define ONFI_SECTION_TYPE_0 0 /* Unused section. */
++#define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
++#define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
++struct onfi_ext_section {
++ u8 type;
++ u8 length;
++} __packed;
++
++#define ONFI_EXT_SECTION_MAX 8
++
++/* Extended Parameter Page Definition (since ONFI 2.1) */
++struct onfi_ext_param_page {
++ __le16 crc;
++ u8 sig[4]; /* 'E' 'P' 'P' 'S' */
++ u8 reserved0[10];
++ struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
++
++ /*
++ * The actual size of the Extended Parameter Page is in
++ * @ext_param_page_length of nand_onfi_params{}.
++ * The following are the variable length sections.
++ * So we do not add any fields below. Please see the ONFI spec.
++ */
++} __packed;
++
+ /**
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
+ * @lock: protection lock
+@@ -390,8 +435,8 @@
+ * @write_buf: [REPLACEABLE] write data from the buffer to the chip
+ * @read_buf: [REPLACEABLE] read data from the chip into the buffer
+ * @select_chip: [REPLACEABLE] select chip nr
+- * @block_bad: [REPLACEABLE] check, if the block is bad
+- * @block_markbad: [REPLACEABLE] mark the block bad
++ * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
++ * @block_markbad: [REPLACEABLE] mark a block bad
+ * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
+ * ALE/CLE/nCE. Also used to write command and address
+ * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
+@@ -433,7 +478,13 @@
+ * @badblockbits: [INTERN] minimum number of set bits in a good block's
+ * bad block marker position; i.e., BBM == 11110111b is
+ * not bad when badblockbits == 7
+- * @cellinfo: [INTERN] MLC/multichip data from chip ident
++ * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
++ * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
++ * Minimum amount of bit errors per @ecc_step_ds guaranteed
++ * to be correctable. If unknown, set to zero.
++ * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
++ * also from the datasheet. It is the recommended ECC step
++ * size, if known; if unknown, set to zero.
+ * @numchips: [INTERN] number of physical chips
+ * @chipsize: [INTERN] the size of one chip for multichip arrays
+ * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
+@@ -448,7 +499,6 @@
+ * supported, 0 otherwise.
+ * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
+- * @ecclayout: [REPLACEABLE] the default ECC placement scheme
+ * @bbt: [INTERN] bad block table pointer
+ * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
+ * lookup.
+@@ -509,7 +559,9 @@
+ int pagebuf;
+ unsigned int pagebuf_bitflips;
+ int subpagesize;
+- uint8_t cellinfo;
++ uint8_t bits_per_cell;
++ uint16_t ecc_strength_ds;
++ uint16_t ecc_step_ds;
+ int badblockpos;
+ int badblockbits;
+
+@@ -520,7 +572,6 @@
+
+ uint8_t *oob_poi;
+ struct nand_hw_control *controller;
+- struct nand_ecclayout *ecclayout;
+
+ struct nand_ecc_ctrl ecc;
+ struct nand_buffers *buffers;
+@@ -576,6 +627,11 @@
+ { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
+ .options = (opts) }
+
++#define NAND_ECC_INFO(_strength, _step) \
++ { .strength_ds = (_strength), .step_ds = (_step) }
++#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
++#define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
++
+ /**
+ * struct nand_flash_dev - NAND Flash Device ID Structure
+ * @name: a human-readable name of the NAND chip
+@@ -593,6 +649,12 @@
+ * @options: stores various chip bit options
+ * @id_len: The valid length of the @id.
+ * @oobsize: OOB size
++ * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
++ * @ecc_strength_ds in nand_chip{}.
++ * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
++ * @ecc_step_ds in nand_chip{}, also from the datasheet.
++ * For example, the "4bit ECC for each 512Byte" can be set with
++ * NAND_ECC_INFO(4, 512).
+ */
+ struct nand_flash_dev {
+ char *name;
+@@ -609,6 +671,10 @@
+ unsigned int options;
+ uint16_t id_len;
+ uint16_t oobsize;
++ struct {
++ uint16_t strength_ds;
++ uint16_t step_ds;
++ } ecc;
+ };
+
+ /**
+@@ -625,8 +691,8 @@
+ extern struct nand_manufacturers nand_manuf_ids[];
+
+ extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
+-extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
+ extern int nand_default_bbt(struct mtd_info *mtd);
++extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
+ extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
+ extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
+ int allowbbt);
+@@ -708,6 +774,12 @@
+ return chip->priv;
+ }
+
++/* return the supported features. */
++static inline int onfi_feature(struct nand_chip *chip)
++{
++ return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
++}
++
+ /* return the supported asynchronous timing mode. */
+ static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+ {
+@@ -724,4 +796,13 @@
+ return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
+ }
+
++/*
++ * Check if it is a SLC nand.
++ * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
++ * We do not distinguish the MLC and TLC now.
++ */
++static inline bool nand_is_slc(struct nand_chip *chip)
++{
++ return chip->bits_per_cell == 1;
++}
+ #endif /* __LINUX_MTD_NAND_H */
+diff -Nur linux-3.10.30.orig/include/linux/mxc_asrc.h linux-linaro-stable-mx6/include/linux/mxc_asrc.h
+--- linux-3.10.30.orig/include/linux/mxc_asrc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mxc_asrc.h 2014-05-15 20:34:14.870135413 +0200
+@@ -0,0 +1,386 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ *
++ * @file mxc_asrc.h
++ *
++ * @brief i.MX Asynchronous Sample Rate Converter
++ *
++ * @ingroup Audio
++ */
++
++#ifndef __MXC_ASRC_H__
++#define __MXC_ASRC_H__
++
++#include <uapi/linux/mxc_asrc.h>
++#include <linux/scatterlist.h>
++
++#define ASRC_DMA_BUFFER_NUM 2
++#define ASRC_INPUTFIFO_THRESHOLD 32
++#define ASRC_OUTPUTFIFO_THRESHOLD 32
++#define ASRC_FIFO_THRESHOLD_MIN 0
++#define ASRC_FIFO_THRESHOLD_MAX 63
++#define ASRC_DMA_BUFFER_SIZE (1024 * 48 * 4)
++#define ASRC_MAX_BUFFER_SIZE (1024 * 48)
++#define ASRC_OUTPUT_LAST_SAMPLE_DEFAULT 8
++
++
++/* Ideal Ratio mode doesn't care the outclk frequency, so be fixed */
++#define ASRC_PRESCALER_IDEAL_RATIO 5
++/* SPDIF rxclk pulse rate is 128 * samplerate, so 2 ^ 7 */
++#define ASRC_PRESCALER_SPDIF_RX 7
++/* SPDIF txclk pulse rate is 64 * samplerate, so 2 ^ 6 */
++#define ASRC_PRESCALER_SPDIF_TX 6
++/* I2S bclk is 16 * 2 = 32, so 2 ^ 5 */
++#define ASRC_PRESCALER_I2S_16BIT 5
++/* I2S bclk is 24 * 2 = 48 -> 64, so 2 ^ 6 */
++#define ASRC_PRESCALER_I2S_24BIT 6
++
++
++#define REG_ASRCTR 0x00
++#define REG_ASRIER 0x04
++#define REG_ASRCNCR 0x0C
++#define REG_ASRCFG 0x10
++#define REG_ASRCSR 0x14
++
++#define REG_ASRCDR1 0x18
++#define REG_ASRCDR2 0x1C
++#define REG_ASRCDR(x) ((x < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
++
++#define REG_ASRSTR 0x20
++#define REG_ASRRA 0x24
++#define REG_ASRRB 0x28
++#define REG_ASRRC 0x2C
++#define REG_ASRPM1 0x40
++#define REG_ASRPM2 0x44
++#define REG_ASRPM3 0x48
++#define REG_ASRPM4 0x4C
++#define REG_ASRPM5 0x50
++#define REG_ASRTFR1 0x54
++#define REG_ASRCCR 0x5C
++
++#define REG_ASRDIA 0x60
++#define REG_ASRDOA 0x64
++#define REG_ASRDIB 0x68
++#define REG_ASRDOB 0x6C
++#define REG_ASRDIC 0x70
++#define REG_ASRDOC 0x74
++#define REG_ASRDI(x) (REG_ASRDIA + (x << 3))
++#define REG_ASRDO(x) (REG_ASRDOA + (x << 3))
++
++#define REG_ASRIDRHA 0x80
++#define REG_ASRIDRLA 0x84
++#define REG_ASRIDRHB 0x88
++#define REG_ASRIDRLB 0x8C
++#define REG_ASRIDRHC 0x90
++#define REG_ASRIDRLC 0x94
++#define REG_ASRIDRH(x) (REG_ASRIDRHA + (x << 3))
++#define REG_ASRIDRL(x) (REG_ASRIDRLA + (x << 3))
++
++#define REG_ASR76K 0x98
++#define REG_ASR56K 0x9C
++
++#define REG_ASRMCRA 0xA0
++#define REG_ASRFSTA 0xA4
++#define REG_ASRMCRB 0xA8
++#define REG_ASRFSTB 0xAC
++#define REG_ASRMCRC 0xB0
++#define REG_ASRFSTC 0xB4
++#define REG_ASRMCR(x) (REG_ASRMCRA + (x << 3))
++#define REG_ASRFST(x) (REG_ASRFSTA + (x << 3))
++
++#define REG_ASRMCR1A 0xC0
++#define REG_ASRMCR1B 0xC4
++#define REG_ASRMCR1C 0xC8
++#define REG_ASRMCR1(x) (REG_ASRMCR1A + (x << 2))
++
++
++/* REG0 0x00 REG_ASRCTR */
++#define ASRCTR_ATSx_SHIFT(x) (20 + x)
++#define ASRCTR_ATSx_MASK(x) (1 << ASRCTR_ATSx_SHIFT(x))
++#define ASRCTR_ATS(x) (1 << ASRCTR_ATSx_SHIFT(x))
++#define ASRCTR_USRx_SHIFT(x) (14 + (x << 1))
++#define ASRCTR_USRx_MASK(x) (1 << ASRCTR_USRx_SHIFT(x))
++#define ASRCTR_USR(x) (1 << ASRCTR_USRx_SHIFT(x))
++#define ASRCTR_IDRx_SHIFT(x) (13 + (x << 1))
++#define ASRCTR_IDRx_MASK(x) (1 << ASRCTR_IDRx_SHIFT(x))
++#define ASRCTR_IDR(x) (1 << ASRCTR_IDRx_SHIFT(x))
++#define ASRCTR_SRST_SHIFT 4
++#define ASRCTR_SRST_MASK (1 << ASRCTR_SRST_SHIFT)
++#define ASRCTR_SRST (1 << ASRCTR_SRST_SHIFT)
++#define ASRCTR_ASRCEx_SHIFT(x) (1 + x)
++#define ASRCTR_ASRCEx_MASK(x) (1 << ASRCTR_ASRCEx_SHIFT(x))
++#define ASRCTR_ASRCE(x) (1 << ASRCTR_ASRCEx_SHIFT(x))
++#define ASRCTR_ASRCEN_SHIFT 0
++#define ASRCTR_ASRCEN_MASK (1 << ASRCTR_ASRCEN_SHIFT)
++#define ASRCTR_ASRCEN (1 << ASRCTR_ASRCEN_SHIFT)
++
++/* REG1 0x04 REG_ASRIER */
++#define ASRIER_AFPWE_SHIFT 7
++#define ASRIER_AFPWE_MASK (1 << ASRIER_AFPWE_SHIFT)
++#define ASRIER_AFPWE (1 << ASRIER_AFPWE_SHIFT)
++#define ASRIER_AOLIE_SHIFT 6
++#define ASRIER_AOLIE_MASK (1 << ASRIER_AOLIE_SHIFT)
++#define ASRIER_AOLIE (1 << ASRIER_AOLIE_SHIFT)
++#define ASRIER_ADOEx_SHIFT(x) (3 + x)
++#define ASRIER_ADOEx_MASK(x) (1 << ASRIER_ADOEx_SHIFT(x))
++#define ASRIER_ADOE(x) (1 << ASRIER_ADOEx_SHIFT(x))
++#define ASRIER_ADIEx_SHIFT(x) (0 + x)
++#define ASRIER_ADIEx_MASK(x) (1 << ASRIER_ADIEx_SHIFT(x))
++#define ASRIER_ADIE(x) (1 << ASRIER_ADIEx_SHIFT(x))
++
++/* REG2 0x0C REG_ASRCNCR */
++#define ASRCNCR_ANCx_SHIFT(x, b) (b * x)
++#define ASRCNCR_ANCx_MASK(x, b) (((1 << b) - 1) << ASRCNCR_ANCx_SHIFT(x, b))
++#define ASRCNCR_ANCx_get(x, v, b) ((v & ASRCNCR_ANCx_MASK(x, b)) >> ASRCNCR_ANCx_SHIFT(x, b))
++#define ASRCNCR_ANCx_set(x, v, b) ((v << ASRCNCR_ANCx_SHIFT(x, b)) & ASRCNCR_ANCx_MASK(x, b))
++
++/* REG3 0x10 REG_ASRCFG */
++#define ASRCFG_INIRQx_SHIFT(x) (21 + x)
++#define ASRCFG_INIRQx_MASK(x) (1 << ASRCFG_INIRQx_SHIFT(x))
++#define ASRCFG_INIRQx (1 << ASRCFG_INIRQx_SHIFT(x))
++#define ASRCFG_NDPRx_SHIFT(x) (18 + x)
++#define ASRCFG_NDPRx_MASK(x) (1 << ASRCFG_NDPRx_SHIFT(x))
++#define ASRCFG_NDPRx (1 << ASRCFG_NDPRx_SHIFT(x))
++#define ASRCFG_POSTMODx_SHIFT(x) (8 + (x << 2))
++#define ASRCFG_POSTMODx_WIDTH 2
++#define ASRCFG_POSTMODx_MASK(x) (((1 << ASRCFG_POSTMODx_WIDTH) - 1) << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_POSTMOD(x, v) ((v) << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_POSTMODx_UP(x) (0 << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_POSTMODx_DCON(x) (1 << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_POSTMODx_DOWN(x) (2 << ASRCFG_POSTMODx_SHIFT(x))
++#define ASRCFG_PREMODx_SHIFT(x) (6 + (x << 2))
++#define ASRCFG_PREMODx_WIDTH 2
++#define ASRCFG_PREMODx_MASK(x) (((1 << ASRCFG_PREMODx_WIDTH) - 1) << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMOD(x, v) ((v) << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMODx_UP(x) (0 << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMODx_DCON(x) (1 << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMODx_DOWN(x) (2 << ASRCFG_PREMODx_SHIFT(x))
++#define ASRCFG_PREMODx_BYPASS(x) (3 << ASRCFG_PREMODx_SHIFT(x))
++
++/* REG4 0x14 REG_ASRCSR */
++#define ASRCSR_AxCSx_WIDTH 4
++#define ASRCSR_AxCSx_MASK ((1 << ASRCSR_AxCSx_WIDTH) - 1)
++#define ASRCSR_AOCSx_SHIFT(x) (12 + (x << 2))
++#define ASRCSR_AOCSx_MASK(x) (((1 << ASRCSR_AxCSx_WIDTH) - 1) << ASRCSR_AOCSx_SHIFT(x))
++#define ASRCSR_AOCS(x, v) ((v) << ASRCSR_AOCSx_SHIFT(x))
++#define ASRCSR_AICSx_SHIFT(x) (x << 2)
++#define ASRCSR_AICSx_MASK(x) (((1 << ASRCSR_AxCSx_WIDTH) - 1) << ASRCSR_AICSx_SHIFT(x))
++#define ASRCSR_AICS(x, v) ((v) << ASRCSR_AICSx_SHIFT(x))
++
++/* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
++#define ASRCDRx_AxCPx_WIDTH 3
++#define ASRCDRx_AICPx_SHIFT(x) (0 + (x % 2) * 6)
++#define ASRCDRx_AICPx_MASK(x) (((1 << ASRCDRx_AxCPx_WIDTH) - 1) << ASRCDRx_AICPx_SHIFT(x))
++#define ASRCDRx_AICP(x, v) ((v) << ASRCDRx_AICPx_SHIFT(x))
++#define ASRCDRx_AICDx_SHIFT(x) (3 + (x % 2) * 6)
++#define ASRCDRx_AICDx_MASK(x) (((1 << ASRCDRx_AxCPx_WIDTH) - 1) << ASRCDRx_AICDx_SHIFT(x))
++#define ASRCDRx_AICD(x, v) ((v) << ASRCDRx_AICDx_SHIFT(x))
++#define ASRCDRx_AOCPx_SHIFT(x) ((x < 2) ? 12 + x * 6 : 6)
++#define ASRCDRx_AOCPx_MASK(x) (((1 << ASRCDRx_AxCPx_WIDTH) - 1) << ASRCDRx_AOCPx_SHIFT(x))
++#define ASRCDRx_AOCP(x, v) ((v) << ASRCDRx_AOCPx_SHIFT(x))
++#define ASRCDRx_AOCDx_SHIFT(x) ((x < 2) ? 15 + x * 6 : 9)
++#define ASRCDRx_AOCDx_MASK(x) (((1 << ASRCDRx_AxCPx_WIDTH) - 1) << ASRCDRx_AOCDx_SHIFT(x))
++#define ASRCDRx_AOCD(x, v) ((v) << ASRCDRx_AOCDx_SHIFT(x))
++
++/* REG7 0x20 REG_ASRSTR */
++#define ASRSTR_DSLCNT_SHIFT 21
++#define ASRSTR_DSLCNT_MASK (1 << ASRSTR_DSLCNT_SHIFT)
++#define ASRSTR_DSLCNT (1 << ASRSTR_DSLCNT_SHIFT)
++#define ASRSTR_ATQOL_SHIFT 20
++#define ASRSTR_ATQOL_MASK (1 << ASRSTR_ATQOL_SHIFT)
++#define ASRSTR_ATQOL (1 << ASRSTR_ATQOL_SHIFT)
++#define ASRSTR_AOOLx_SHIFT(x) (17 + x)
++#define ASRSTR_AOOLx_MASK(x) (1 << ASRSTR_AOOLx_SHIFT(x))
++#define ASRSTR_AOOL(x) (1 << ASRSTR_AOOLx_SHIFT(x))
++#define ASRSTR_AIOLx_SHIFT(x) (14 + x)
++#define ASRSTR_AIOLx_MASK(x) (1 << ASRSTR_AIOLx_SHIFT(x))
++#define ASRSTR_AIOL(x) (1 << ASRSTR_AIOLx_SHIFT(x))
++#define ASRSTR_AODOx_SHIFT(x) (11 + x)
++#define ASRSTR_AODOx_MASK(x) (1 << ASRSTR_AODOx_SHIFT(x))
++#define ASRSTR_AODO(x) (1 << ASRSTR_AODOx_SHIFT(x))
++#define ASRSTR_AIDUx_SHIFT(x) (8 + x)
++#define ASRSTR_AIDUx_MASK(x) (1 << ASRSTR_AIDUx_SHIFT(x))
++#define ASRSTR_AIDU(x) (1 << ASRSTR_AIDUx_SHIFT(x))
++#define ASRSTR_FPWT_SHIFT 7
++#define ASRSTR_FPWT_MASK (1 << ASRSTR_FPWT_SHIFT)
++#define ASRSTR_FPWT (1 << ASRSTR_FPWT_SHIFT)
++#define ASRSTR_AOLE_SHIFT 6
++#define ASRSTR_AOLE_MASK (1 << ASRSTR_AOLE_SHIFT)
++#define ASRSTR_AOLE (1 << ASRSTR_AOLE_SHIFT)
++#define ASRSTR_AODEx_SHIFT(x) (3 + x)
++#define ASRSTR_AODFx_MASK(x) (1 << ASRSTR_AODEx_SHIFT(x))
++#define ASRSTR_AODF(x) (1 << ASRSTR_AODEx_SHIFT(x))
++#define ASRSTR_AIDEx_SHIFT(x) (0 + x)
++#define ASRSTR_AIDEx_MASK(x) (1 << ASRSTR_AIDEx_SHIFT(x))
++#define ASRSTR_AIDE(x) (1 << ASRSTR_AIDEx_SHIFT(x))
++
++/* REG10 0x54 REG_ASRTFR1 */
++#define ASRTFR1_TF_BASE_WIDTH 7
++#define ASRTFR1_TF_BASE_SHIFT 6
++#define ASRTFR1_TF_BASE_MASK (((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
++#define ASRTFR1_TF_BASE(x) ((x) << ASRTFR1_TF_BASE_SHIFT)
++
++/*
++ * REG22 0xA0 REG_ASRMCRA
++ * REG24 0xA8 REG_ASRMCRB
++ * REG26 0xB0 REG_ASRMCRC
++ */
++#define ASRMCRx_ZEROBUFx_SHIFT 23
++#define ASRMCRx_ZEROBUFxCLR_MASK (1 << ASRMCRx_ZEROBUFx_SHIFT)
++#define ASRMCRx_ZEROBUFxCLR (1 << ASRMCRx_ZEROBUFx_SHIFT)
++#define ASRMCRx_EXTTHRSHx_SHIFT 22
++#define ASRMCRx_EXTTHRSHx_MASK (1 << ASRMCRx_EXTTHRSHx_SHIFT)
++#define ASRMCRx_EXTTHRSHx (1 << ASRMCRx_EXTTHRSHx_SHIFT)
++#define ASRMCRx_BUFSTALLx_SHIFT 21
++#define ASRMCRx_BUFSTALLx_MASK (1 << ASRMCRx_BUFSTALLx_SHIFT)
++#define ASRMCRx_BUFSTALLx (1 << ASRMCRx_BUFSTALLx_SHIFT)
++#define ASRMCRx_BYPASSPOLYx_SHIFT 20
++#define ASRMCRx_BYPASSPOLYx_MASK (1 << ASRMCRx_BYPASSPOLYx_SHIFT)
++#define ASRMCRx_BYPASSPOLYx (1 << ASRMCRx_BYPASSPOLYx_SHIFT)
++#define ASRMCRx_OUTFIFO_THRESHOLD_WIDTH 6
++#define ASRMCRx_OUTFIFO_THRESHOLD_SHIFT 12
++#define ASRMCRx_OUTFIFO_THRESHOLD_MASK (((1 << ASRMCRx_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRx_OUTFIFO_THRESHOLD_SHIFT)
++#define ASRMCRx_OUTFIFO_THRESHOLD(v) (((v) << ASRMCRx_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRx_OUTFIFO_THRESHOLD_MASK)
++#define ASRMCRx_RSYNIFx_SHIFT 11
++#define ASRMCRx_RSYNIFx_MASK (1 << ASRMCRx_RSYNIFx_SHIFT)
++#define ASRMCRx_RSYNIFx (1 << ASRMCRx_RSYNIFx_SHIFT)
++#define ASRMCRx_RSYNOFx_SHIFT 10
++#define ASRMCRx_RSYNOFx_MASK (1 << ASRMCRx_RSYNOFx_SHIFT)
++#define ASRMCRx_RSYNOFx (1 << ASRMCRx_RSYNOFx_SHIFT)
++#define ASRMCRx_INFIFO_THRESHOLD_WIDTH 6
++#define ASRMCRx_INFIFO_THRESHOLD_SHIFT 0
++#define ASRMCRx_INFIFO_THRESHOLD_MASK (((1 << ASRMCRx_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRx_INFIFO_THRESHOLD_SHIFT)
++#define ASRMCRx_INFIFO_THRESHOLD(v) (((v) << ASRMCRx_INFIFO_THRESHOLD_SHIFT) & ASRMCRx_INFIFO_THRESHOLD_MASK)
++
++/*
++ * REG23 0xA4 REG_ASRFSTA
++ * REG25 0xAC REG_ASRFSTB
++ * REG27 0xB4 REG_ASRFSTC
++ */
++#define ASRFSTx_OAFx_SHIFT 23
++#define ASRFSTx_OAFx_MASK (1 << ASRFSTx_OAFx_SHIFT)
++#define ASRFSTx_OAFx (1 << ASRFSTx_OAFx_SHIFT)
++#define ASRFSTx_OUTPUT_FIFO_WIDTH 7
++#define ASRFSTx_OUTPUT_FIFO_SHIFT 12
++#define ASRFSTx_OUTPUT_FIFO_MASK (((1 << ASRFSTx_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTx_OUTPUT_FIFO_SHIFT)
++#define ASRFSTx_IAEx_SHIFT 11
++#define ASRFSTx_IAEx_MASK (1 << ASRFSTx_OAFx_SHIFT)
++#define ASRFSTx_IAEx (1 << ASRFSTx_OAFx_SHIFT)
++#define ASRFSTx_INPUT_FIFO_WIDTH 7
++#define ASRFSTx_INPUT_FIFO_SHIFT 0
++#define ASRFSTx_INPUT_FIFO_MASK ((1 << ASRFSTx_INPUT_FIFO_WIDTH) - 1)
++
++/* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1x */
++#define ASRMCR1x_IWD_WIDTH 3
++#define ASRMCR1x_IWD_SHIFT 9
++#define ASRMCR1x_IWD_MASK (((1 << ASRMCR1x_IWD_WIDTH) - 1) << ASRMCR1x_IWD_SHIFT)
++#define ASRMCR1x_IWD(v) ((v) << ASRMCR1x_IWD_SHIFT)
++#define ASRMCR1x_IMSB_SHIFT 8
++#define ASRMCR1x_IMSB_MASK (1 << ASRMCR1x_IMSB_SHIFT)
++#define ASRMCR1x_IMSB_MSB (1 << ASRMCR1x_IMSB_SHIFT)
++#define ASRMCR1x_IMSB_LSB (0 << ASRMCR1x_IMSB_SHIFT)
++#define ASRMCR1x_OMSB_SHIFT 2
++#define ASRMCR1x_OMSB_MASK (1 << ASRMCR1x_OMSB_SHIFT)
++#define ASRMCR1x_OMSB_MSB (1 << ASRMCR1x_OMSB_SHIFT)
++#define ASRMCR1x_OMSB_LSB (0 << ASRMCR1x_OMSB_SHIFT)
++#define ASRMCR1x_OSGN_SHIFT 1
++#define ASRMCR1x_OSGN_MASK (1 << ASRMCR1x_OSGN_SHIFT)
++#define ASRMCR1x_OSGN (1 << ASRMCR1x_OSGN_SHIFT)
++#define ASRMCR1x_OW16_SHIFT 0
++#define ASRMCR1x_OW16_MASK (1 << ASRMCR1x_OW16_SHIFT)
++#define ASRMCR1x_OW16(v) ((v) << ASRMCR1x_OW16_SHIFT)
++
++
++struct dma_block {
++ unsigned int index;
++ unsigned int length;
++ void *dma_vaddr;
++ dma_addr_t dma_paddr;
++ struct list_head queue;
++};
++
++struct asrc_p2p_params {
++ u32 p2p_rate; /* ASRC output rate for p2p */
++ enum asrc_word_width p2p_width; /* ASRC output wordwidth for p2p */
++};
++
++struct asrc_pair_params {
++ enum asrc_pair_index index;
++ struct completion input_complete;
++ struct completion output_complete;
++ struct completion lastperiod_complete;
++ struct dma_chan *input_dma_channel;
++ struct dma_chan *output_dma_channel;
++ unsigned int input_buffer_size;
++ unsigned int output_buffer_size;
++ unsigned int buffer_num;
++ unsigned int pair_hold;
++ unsigned int asrc_active;
++ unsigned int channel_nums;
++ struct dma_block input_dma_total;
++ struct dma_block input_dma[ASRC_DMA_BUFFER_NUM];
++ struct dma_block output_dma_total;
++ struct dma_block output_dma[ASRC_DMA_BUFFER_NUM];
++ struct dma_block output_last_period;
++ struct dma_async_tx_descriptor *desc_in;
++ struct dma_async_tx_descriptor *desc_out;
++ struct work_struct task_output_work;
++ unsigned int input_sg_nodes;
++ unsigned int output_sg_nodes;
++ struct scatterlist input_sg[4], output_sg[4];
++ enum asrc_word_width input_word_width;
++ enum asrc_word_width output_word_width;
++ u32 input_sample_rate;
++ u32 output_sample_rate;
++ u32 input_wm;
++ u32 output_wm;
++ unsigned int last_period_sample;
++};
++
++struct asrc_data {
++ struct asrc_pair asrc_pair[ASRC_PAIR_MAX_NUM];
++ struct proc_dir_entry *proc_asrc;
++ struct class *asrc_class;
++ struct regmap *regmap;
++ struct clk *asrc_clk;
++ struct clk *dma_clk;
++ unsigned long paddr;
++ unsigned int channel_bits;
++ int asrc_major;
++ int irq;
++ struct device *dev;
++};
++
++struct asrc_p2p_ops {
++ void (*asrc_p2p_start_conv)(enum asrc_pair_index);
++ void (*asrc_p2p_stop_conv)(enum asrc_pair_index);
++ int (*asrc_p2p_get_dma_request)(enum asrc_pair_index, bool);
++ u32 (*asrc_p2p_per_addr)(enum asrc_pair_index, bool);
++ int (*asrc_p2p_req_pair)(int, enum asrc_pair_index *index);
++ int (*asrc_p2p_config_pair)(struct asrc_config *config);
++ void (*asrc_p2p_release_pair)(enum asrc_pair_index);
++ void (*asrc_p2p_finish_conv)(enum asrc_pair_index);
++};
++
++extern void asrc_p2p_hook(struct asrc_p2p_ops *asrc_p2p_ct);
++
++extern int asrc_req_pair(int chn_num, enum asrc_pair_index *index);
++extern void asrc_release_pair(enum asrc_pair_index index);
++extern int asrc_config_pair(struct asrc_config *config);
++extern void asrc_get_status(struct asrc_status_flags *flags);
++extern void asrc_start_conv(enum asrc_pair_index index);
++extern void asrc_stop_conv(enum asrc_pair_index index);
++extern u32 asrc_get_per_addr(enum asrc_pair_index index, bool i);
++extern int asrc_get_dma_request(enum asrc_pair_index index, bool i);
++extern void asrc_finish_conv(enum asrc_pair_index index);
++extern int asrc_set_watermark(enum asrc_pair_index index,
++ u32 in_wm, u32 out_wm);
++
++#endif/* __MXC_ASRC_H__ */
+diff -Nur linux-3.10.30.orig/include/linux/mxcfb_epdc.h linux-linaro-stable-mx6/include/linux/mxcfb_epdc.h
+--- linux-3.10.30.orig/include/linux/mxcfb_epdc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mxcfb_epdc.h 2014-05-15 20:34:14.870135413 +0200
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _MXCFB_EPDC_KERNEL
++#define _MXCFB_EPDC_KERNEL
++
++struct imx_epdc_fb_mode {
++ struct fb_videomode *vmode;
++ int vscan_holdoff;
++ int sdoed_width;
++ int sdoed_delay;
++ int sdoez_width;
++ int sdoez_delay;
++ int gdclk_hp_offs;
++ int gdsp_offs;
++ int gdoe_offs;
++ int gdclk_offs;
++ int num_ce;
++};
++
++struct imx_epdc_fb_platform_data {
++ struct imx_epdc_fb_mode *epdc_mode;
++ int num_modes;
++ int (*get_pins) (void);
++ void (*put_pins) (void);
++ void (*enable_pins) (void);
++ void (*disable_pins) (void);
++};
++
++void mxc_epdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
++ struct fb_info *info);
++int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info);
++int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info);
++int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
++ struct fb_info *info);
++int mxc_epdc_fb_wait_update_complete(
++ struct mxcfb_update_marker_data *marker_data,
++ struct fb_info *info);
++int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
++ struct fb_info *info);
++int mxc_epdc_get_pwrdown_delay(struct fb_info *info);
++int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info);
++
++void mxc_spdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
++ struct fb_info *info);
++int mxc_spdc_fb_set_temperature(int temperature, struct fb_info *info);
++int mxc_spdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info);
++int mxc_spdc_fb_send_update(struct mxcfb_update_data *upd_data,
++ struct fb_info *info);
++int mxc_spdc_fb_wait_update_complete(
++ struct mxcfb_update_marker_data *marker_data,
++ struct fb_info *info);
++int mxc_spdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
++ struct fb_info *info);
++int mxc_spdc_get_pwrdown_delay(struct fb_info *info);
++int mxc_spdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info);
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/mxcfb.h linux-linaro-stable-mx6/include/linux/mxcfb.h
+--- linux-3.10.30.orig/include/linux/mxcfb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mxcfb.h 2014-05-15 20:34:14.870135413 +0200
+@@ -0,0 +1,46 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*
++ * @file linux/mxcfb.h
++ *
++ * @brief Global header file for the MXC Frame buffer
++ *
++ * @ingroup Framebuffer
++ */
++#ifndef __LINUX_MXCFB_H__
++#define __LINUX_MXCFB_H__
++
++#include <uapi/linux/mxcfb.h>
++
++extern struct fb_videomode mxcfb_modedb[];
++extern int mxcfb_modedb_sz;
++
++enum {
++ MXC_DISP_SPEC_DEV = 0,
++ MXC_DISP_DDC_DEV = 1,
++};
++
++enum {
++ MXCFB_REFRESH_OFF,
++ MXCFB_REFRESH_AUTO,
++ MXCFB_REFRESH_PARTIAL,
++};
++
++int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode,
++ struct mxcfb_rect *update_region);
++int mxc_elcdif_frame_addr_setup(dma_addr_t phys);
++void mxcfb_elcdif_register_mode(const struct fb_videomode *modedb,
++ int num_modes, int dev_mode);
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/mxc_mlb.h linux-linaro-stable-mx6/include/linux/mxc_mlb.h
+--- linux-3.10.30.orig/include/linux/mxc_mlb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mxc_mlb.h 2014-05-15 20:34:14.870135413 +0200
+@@ -0,0 +1,55 @@
++/*
++ * mxc_mlb.h
++ *
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef _MXC_MLB_H
++#define _MXC_MLB_H
++
++/* define IOCTL command */
++#define MLB_DBG_RUNTIME _IO('S', 0x09)
++#define MLB_SET_FPS _IOW('S', 0x10, unsigned int)
++#define MLB_GET_VER _IOR('S', 0x11, unsigned long)
++#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char)
++
++/*!
++ * set channel address for each logical channel
++ * the MSB 16bits is for tx channel, the left LSB is for rx channel
++ */
++#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int)
++#define MLB_CHAN_STARTUP _IO('S', 0x14)
++#define MLB_CHAN_SHUTDOWN _IO('S', 0x15)
++#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long)
++
++#define MLB_SET_ISOC_BLKSIZE_188 _IO('S', 0x17)
++#define MLB_SET_ISOC_BLKSIZE_196 _IO('S', 0x18)
++#define MLB_SET_SYNC_QUAD _IOW('S', 0x19, unsigned int)
++#define MLB_IRQ_ENABLE _IO('S', 0x20)
++#define MLB_IRQ_DISABLE _IO('S', 0x21)
++
++/*!
++ * MLB event define
++ */
++enum {
++ MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0,
++ MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1,
++ MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8,
++ MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9,
++ MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16,
++ MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17,
++ MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24,
++ MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25,
++};
++
++
++#endif /* _MXC_MLB_H */
+diff -Nur linux-3.10.30.orig/include/linux/mxc_v4l2.h linux-linaro-stable-mx6/include/linux/mxc_v4l2.h
+--- linux-3.10.30.orig/include/linux/mxc_v4l2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mxc_v4l2.h 2014-05-15 20:34:14.870135413 +0200
+@@ -0,0 +1,27 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*!
++ * @file linux/mxc_v4l2.h
++ *
++ * @brief MXC V4L2 private header file
++ *
++ * @ingroup MXC V4L2
++ */
++
++#ifndef __LINUX_MXC_V4L2_H__
++#define __LINUX_MXC_V4L2_H__
++
++#include <uapi/linux/mxc_v4l2.h>
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/mxc_vpu.h linux-linaro-stable-mx6/include/linux/mxc_vpu.h
+--- linux-3.10.30.orig/include/linux/mxc_vpu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/mxc_vpu.h 2014-05-15 20:34:14.870135413 +0200
+@@ -0,0 +1,118 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*!
++ * @defgroup VPU Video Processor Unit Driver
++ */
++
++/*!
++ * @file linux/mxc_vpu.h
++ *
++ * @brief VPU system initialization and file operation definition
++ *
++ * @ingroup VPU
++ */
++
++#ifndef __LINUX_MXC_VPU_H__
++#define __LINUX_MXC_VPU_H__
++
++#include <linux/fs.h>
++
++struct mxc_vpu_platform_data {
++ bool iram_enable;
++ int iram_size;
++ void (*reset) (void);
++ void (*pg) (int);
++};
++
++struct vpu_mem_desc {
++ u32 size;
++ dma_addr_t phy_addr;
++ u32 cpu_addr; /* cpu address to free the dma mem */
++ u32 virt_uaddr; /* virtual user space address */
++};
++
++#define VPU_IOC_MAGIC 'V'
++
++#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0)
++#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1)
++#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2)
++#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3)
++#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4)
++#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6)
++#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7)
++#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8)
++#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9)
++#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11)
++#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12)
++#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13)
++#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14)
++#define VPU_IOC_PHYMEM_CHECK _IO(VPU_IOC_MAGIC, 15)
++#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 16)
++
++#define BIT_CODE_RUN 0x000
++#define BIT_CODE_DOWN 0x004
++#define BIT_INT_CLEAR 0x00C
++#define BIT_INT_STATUS 0x010
++#define BIT_CUR_PC 0x018
++#define BIT_INT_REASON 0x174
++
++#define MJPEG_PIC_STATUS_REG 0x3004
++#define MBC_SET_SUBBLK_EN 0x4A0
++
++#define BIT_WORK_CTRL_BUF_BASE 0x100
++#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4)
++#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0)
++#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1)
++#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2)
++#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3)
++#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4)
++#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5)
++
++#ifndef CONFIG_SOC_IMX6Q
++#define BIT_RESET_CTRL 0x11C
++#else
++#define BIT_RESET_CTRL 0x128
++#endif
++
++/* i could be 0, 1, 2, 3 */
++#define BIT_RD_PTR_BASE 0x120
++#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8)
++#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4)
++
++/* i could be 0, 1, 2, 3 */
++#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140)
++#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4)
++
++#define BIT_BUSY_FLAG 0x160
++#define BIT_RUN_COMMAND 0x164
++#define BIT_INT_ENABLE 0x170
++
++#define BITVAL_PIC_RUN 8
++
++#define VPU_SLEEP_REG_VALUE 10
++#define VPU_WAKE_REG_VALUE 11
++
++int vl2cc_init(u32 vl2cc_hw_base);
++void vl2cc_enable(void);
++void vl2cc_flush(void);
++void vl2cc_disable(void);
++void vl2cc_cleanup(void);
++
++int vl2cc_init(u32 vl2cc_hw_base);
++void vl2cc_enable(void);
++void vl2cc_flush(void);
++void vl2cc_disable(void);
++void vl2cc_cleanup(void);
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/of_address.h linux-linaro-stable-mx6/include/linux/of_address.h
+--- linux-3.10.30.orig/include/linux/of_address.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/of_address.h 2014-05-15 20:34:14.886135528 +0200
+@@ -4,6 +4,36 @@
+ #include <linux/errno.h>
+ #include <linux/of.h>
+
++struct of_pci_range_parser {
++ struct device_node *node;
++ const __be32 *range;
++ const __be32 *end;
++ int np;
++ int pna;
++};
++
++struct of_pci_range {
++ u32 pci_space;
++ u64 pci_addr;
++ u64 cpu_addr;
++ u64 size;
++ u32 flags;
++};
++
++#define for_each_of_pci_range(parser, range) \
++ for (; of_pci_range_parser_one(parser, range);)
++
++static inline void of_pci_range_to_resource(struct of_pci_range *range,
++ struct device_node *np,
++ struct resource *res)
++{
++ res->flags = range->flags;
++ res->start = range->cpu_addr;
++ res->end = range->cpu_addr + range->size - 1;
++ res->parent = res->child = res->sibling = NULL;
++ res->name = np->full_name;
++}
++
+ #ifdef CONFIG_OF_ADDRESS
+ extern u64 of_translate_address(struct device_node *np, const __be32 *addr);
+ extern bool of_can_translate_address(struct device_node *dev);
+@@ -27,6 +57,11 @@
+ #define pci_address_to_pio pci_address_to_pio
+ #endif
+
++extern int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++ struct device_node *node);
++extern struct of_pci_range *of_pci_range_parser_one(
++ struct of_pci_range_parser *parser,
++ struct of_pci_range *range);
+ #else /* CONFIG_OF_ADDRESS */
+ #ifndef of_address_to_resource
+ static inline int of_address_to_resource(struct device_node *dev, int index,
+@@ -53,6 +88,19 @@
+ {
+ return NULL;
+ }
++
++static inline int of_pci_range_parser_init(struct of_pci_range_parser *parser,
++ struct device_node *node)
++{
++ return -1;
++}
++
++static inline struct of_pci_range *of_pci_range_parser_one(
++ struct of_pci_range_parser *parser,
++ struct of_pci_range *range)
++{
++ return NULL;
++}
+ #endif /* CONFIG_OF_ADDRESS */
+
+
+diff -Nur linux-3.10.30.orig/include/linux/of_gpio.h linux-linaro-stable-mx6/include/linux/of_gpio.h
+--- linux-3.10.30.orig/include/linux/of_gpio.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/of_gpio.h 2014-05-15 20:34:14.886135528 +0200
+@@ -19,8 +19,10 @@
+ #include <linux/errno.h>
+ #include <linux/gpio.h>
+ #include <linux/of.h>
++#include <linux/gpio/consumer.h>
+
+ struct device_node;
++struct gpio_desc;
+
+ /*
+ * This is Linux-specific flags. By default controllers' and Linux' mapping
+@@ -47,7 +49,7 @@
+ return container_of(gc, struct of_mm_gpio_chip, gc);
+ }
+
+-extern int of_get_named_gpio_flags(struct device_node *np,
++extern struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np,
+ const char *list_name, int index, enum of_gpio_flags *flags);
+
+ extern int of_mm_gpiochip_add(struct device_node *np,
+@@ -62,10 +64,10 @@
+ #else /* CONFIG_OF_GPIO */
+
+ /* Drivers may not strictly depend on the GPIO support, so let them link. */
+-static inline int of_get_named_gpio_flags(struct device_node *np,
++static inline struct gpio_desc *of_get_named_gpiod_flags(struct device_node *np,
+ const char *list_name, int index, enum of_gpio_flags *flags)
+ {
+- return -ENOSYS;
++ return ERR_PTR(-ENOSYS);
+ }
+
+ static inline int of_gpio_simple_xlate(struct gpio_chip *gc,
+@@ -80,6 +82,18 @@
+
+ #endif /* CONFIG_OF_GPIO */
+
++static inline int of_get_named_gpio_flags(struct device_node *np,
++ const char *list_name, int index, enum of_gpio_flags *flags)
++{
++ struct gpio_desc *desc;
++ desc = of_get_named_gpiod_flags(np, list_name, index, flags);
++
++ if (IS_ERR(desc))
++ return PTR_ERR(desc);
++ else
++ return desc_to_gpio(desc);
++}
++
+ /**
+ * of_gpio_named_count() - Count GPIOs for a device
+ * @np: device node to count GPIOs for
+@@ -117,15 +131,21 @@
+ }
+
+ /**
+- * of_get_gpio_flags() - Get a GPIO number and flags to use with GPIO API
++ * of_get_gpiod_flags() - Get a GPIO descriptor and flags to use with GPIO API
+ * @np: device node to get GPIO from
+ * @index: index of the GPIO
+ * @flags: a flags pointer to fill in
+ *
+- * Returns GPIO number to use with Linux generic GPIO API, or one of the errno
++ * Returns GPIO descriptor to use with Linux generic GPIO API, or a errno
+ * value on the error condition. If @flags is not NULL the function also fills
+ * in flags for the GPIO.
+ */
++static inline struct gpio_desc *of_get_gpiod_flags(struct device_node *np,
++ int index, enum of_gpio_flags *flags)
++{
++ return of_get_named_gpiod_flags(np, "gpios", index, flags);
++}
++
+ static inline int of_get_gpio_flags(struct device_node *np, int index,
+ enum of_gpio_flags *flags)
+ {
+diff -Nur linux-3.10.30.orig/include/linux/of.h linux-linaro-stable-mx6/include/linux/of.h
+--- linux-3.10.30.orig/include/linux/of.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/of.h 2014-05-15 20:34:14.886135528 +0200
+@@ -266,6 +266,7 @@
+ extern const void *of_get_property(const struct device_node *node,
+ const char *name,
+ int *lenp);
++extern struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
+ #define for_each_property_of_node(dn, pp) \
+ for (pp = dn->properties; pp != NULL; pp = pp->next)
+
+@@ -280,6 +281,9 @@
+ extern int of_parse_phandle_with_args(const struct device_node *np,
+ const char *list_name, const char *cells_name, int index,
+ struct of_phandle_args *out_args);
++extern int of_parse_phandle_with_fixed_args(const struct device_node *np,
++ const char *list_name, int cells_count, int index,
++ struct of_phandle_args *out_args);
+ extern int of_count_phandle_with_args(const struct device_node *np,
+ const char *list_name, const char *cells_name);
+
+@@ -343,6 +347,8 @@
+ s; \
+ s = of_prop_next_string(prop, s))
+
++int of_device_is_stdout_path(struct device_node *dn);
++
+ #else /* CONFIG_OF */
+
+ static inline const char* of_node_full_name(struct device_node *np)
+@@ -459,6 +465,12 @@
+ return NULL;
+ }
+
++static inline struct device_node *of_get_cpu_node(int cpu,
++ unsigned int *thread)
++{
++ return NULL;
++}
++
+ static inline int of_property_read_u64(const struct device_node *np,
+ const char *propname, u64 *out_value)
+ {
+@@ -488,6 +500,13 @@
+ return -ENOSYS;
+ }
+
++static inline int of_parse_phandle_with_fixed_args(const struct device_node *np,
++ const char *list_name, int cells_count, int index,
++ struct of_phandle_args *out_args)
++{
++ return -ENOSYS;
++}
++
+ static inline int of_count_phandle_with_args(struct device_node *np,
+ const char *list_name,
+ const char *cells_name)
+@@ -504,6 +523,11 @@
+ {
+ return 0;
+ }
++
++static inline int of_device_is_stdout_path(struct device_node *dn)
++{
++ return 0;
++}
+
+ #define of_match_ptr(_ptr) NULL
+ #define of_match_node(_matches, _node) NULL
+diff -Nur linux-3.10.30.orig/include/linux/of_pci.h linux-linaro-stable-mx6/include/linux/of_pci.h
+--- linux-3.10.30.orig/include/linux/of_pci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/of_pci.h 2014-05-15 20:34:14.886135528 +0200
+@@ -2,6 +2,7 @@
+ #define __OF_PCI_H
+
+ #include <linux/pci.h>
++#include <linux/msi.h>
+
+ struct pci_dev;
+ struct of_irq;
+@@ -10,5 +11,18 @@
+ struct device_node;
+ struct device_node *of_pci_find_child_device(struct device_node *parent,
+ unsigned int devfn);
++int of_pci_get_devfn(struct device_node *np);
++int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
++
++#if defined(CONFIG_OF) && defined(CONFIG_PCI_MSI)
++int of_pci_msi_chip_add(struct msi_chip *chip);
++void of_pci_msi_chip_remove(struct msi_chip *chip);
++struct msi_chip *of_pci_find_msi_chip_by_node(struct device_node *of_node);
++#else
++static inline int of_pci_msi_chip_add(struct msi_chip *chip) { return -EINVAL; }
++static inline void of_pci_msi_chip_remove(struct msi_chip *chip) { }
++static inline struct msi_chip *
++of_pci_find_msi_chip_by_node(struct device_node *of_node) { return NULL; }
++#endif
+
+ #endif
+diff -Nur linux-3.10.30.orig/include/linux/pci.h linux-linaro-stable-mx6/include/linux/pci.h
+--- linux-3.10.30.orig/include/linux/pci.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/pci.h 2014-05-15 20:34:14.914135729 +0200
+@@ -432,6 +432,7 @@
+ struct resource busn_res; /* bus numbers routed to this bus */
+
+ struct pci_ops *ops; /* configuration access functions */
++ struct msi_chip *msi; /* MSI controller */
+ void *sysdata; /* hook for sys-specific extension */
+ struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
+
+diff -Nur linux-3.10.30.orig/include/linux/pinctrl/consumer.h linux-linaro-stable-mx6/include/linux/pinctrl/consumer.h
+--- linux-3.10.30.orig/include/linux/pinctrl/consumer.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/pinctrl/consumer.h 2014-05-15 20:34:14.914135729 +0200
+@@ -40,6 +40,25 @@
+ extern struct pinctrl * __must_check devm_pinctrl_get(struct device *dev);
+ extern void devm_pinctrl_put(struct pinctrl *p);
+
++#ifdef CONFIG_PM
++extern int pinctrl_pm_select_default_state(struct device *dev);
++extern int pinctrl_pm_select_sleep_state(struct device *dev);
++extern int pinctrl_pm_select_idle_state(struct device *dev);
++#else
++static inline int pinctrl_pm_select_default_state(struct device *dev)
++{
++ return 0;
++}
++static inline int pinctrl_pm_select_sleep_state(struct device *dev)
++{
++ return 0;
++}
++static inline int pinctrl_pm_select_idle_state(struct device *dev)
++{
++ return 0;
++}
++#endif
++
+ #else /* !CONFIG_PINCTRL */
+
+ static inline int pinctrl_request_gpio(unsigned gpio)
+@@ -198,6 +217,21 @@
+ {
+ return 0;
+ }
++
++static inline int pinctrl_pm_select_default_state(struct device *dev)
++{
++ return 0;
++}
++
++static inline int pinctrl_pm_select_sleep_state(struct device *dev)
++{
++ return 0;
++}
++
++static inline int pinctrl_pm_select_idle_state(struct device *dev)
++{
++ return 0;
++}
+
+ #endif
+
+diff -Nur linux-3.10.30.orig/include/linux/pinctrl/devinfo.h linux-linaro-stable-mx6/include/linux/pinctrl/devinfo.h
+--- linux-3.10.30.orig/include/linux/pinctrl/devinfo.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/pinctrl/devinfo.h 2014-05-15 20:34:14.914135729 +0200
+@@ -28,6 +28,10 @@
+ struct dev_pin_info {
+ struct pinctrl *p;
+ struct pinctrl_state *default_state;
++#ifdef CONFIG_PM
++ struct pinctrl_state *sleep_state;
++ struct pinctrl_state *idle_state;
++#endif
+ };
+
+ extern int pinctrl_bind_pins(struct device *dev);
+diff -Nur linux-3.10.30.orig/include/linux/pinctrl/pinctrl.h linux-linaro-stable-mx6/include/linux/pinctrl/pinctrl.h
+--- linux-3.10.30.orig/include/linux/pinctrl/pinctrl.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/pinctrl/pinctrl.h 2014-05-15 20:34:14.914135729 +0200
+@@ -49,7 +49,8 @@
+ * @name: a name for the chip in this range
+ * @id: an ID number for the chip in this range
+ * @base: base offset of the GPIO range
+- * @pin_base: base pin number of the GPIO range
++ * @pin_base: base pin number of the GPIO range if pins != NULL
++ * @pins: enumeration of pins in GPIO range or NULL
+ * @npins: number of pins in the GPIO range, including the base number
+ * @gc: an optional pointer to a gpio_chip
+ */
+@@ -59,6 +60,7 @@
+ unsigned int id;
+ unsigned int base;
+ unsigned int pin_base;
++ unsigned const *pins;
+ unsigned int npins;
+ struct gpio_chip *gc;
+ };
+diff -Nur linux-3.10.30.orig/include/linux/platform_data/brcmfmac-sdio.h linux-linaro-stable-mx6/include/linux/platform_data/brcmfmac-sdio.h
+--- linux-3.10.30.orig/include/linux/platform_data/brcmfmac-sdio.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/platform_data/brcmfmac-sdio.h 2014-05-15 20:34:14.934135873 +0200
+@@ -90,6 +90,14 @@
+ * oob_irq_nr, oob_irq_flags: the OOB interrupt information. The values are
+ * used for registering the irq using request_irq function.
+ *
++ * broken_sg_support: flag for broken sg list support of SDIO host controller.
++ * Set this to true if the SDIO host controller has higher align requirement
++ * than 32 bytes for each scatterlist item.
++ *
++ * sd_head_align: alignment requirement for start of data buffer
++ *
++ * sd_sgentry_align: length alignment requirement for each sg entry
++ *
+ * power_on: This function is called by the brcmfmac when the module gets
+ * loaded. This can be particularly useful for low power devices. The platform
+ * spcific routine may for example decide to power up the complete device.
+@@ -116,6 +124,9 @@
+ bool oob_irq_supported;
+ unsigned int oob_irq_nr;
+ unsigned long oob_irq_flags;
++ bool broken_sg_support;
++ unsigned short sd_head_align;
++ unsigned short sd_sgentry_align;
+ void (*power_on)(void);
+ void (*power_off)(void);
+ void (*reset)(void);
+diff -Nur linux-3.10.30.orig/include/linux/platform_data/dma-imx.h linux-linaro-stable-mx6/include/linux/platform_data/dma-imx.h
+--- linux-3.10.30.orig/include/linux/platform_data/dma-imx.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/platform_data/dma-imx.h 2014-05-15 20:34:14.938135903 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -39,6 +39,7 @@
+ IMX_DMATYPE_IPU_MEMORY, /* IPU Memory */
+ IMX_DMATYPE_ASRC, /* ASRC */
+ IMX_DMATYPE_ESAI, /* ESAI */
++ IMX_DMATYPE_HDMI, /* HDMI Audio */
+ };
+
+ enum imx_dma_prio {
+@@ -48,9 +49,11 @@
+ };
+
+ struct imx_dma_data {
+- int dma_request; /* DMA request line */
++ int dma_request0; /* DMA request line */
++ int dma_request1;
+ enum sdma_peripheral_type peripheral_type;
+ int priority;
++ void *data_addr1, *data_addr2;
+ };
+
+ static inline int imx_dma_is_ipu(struct dma_chan *chan)
+@@ -58,6 +61,11 @@
+ return !strcmp(dev_name(chan->device->dev), "ipu-core");
+ }
+
++static inline int imx_dma_is_pxp(struct dma_chan *chan)
++{
++ return strstr(dev_name(chan->device->dev), "pxp") != NULL;
++}
++
+ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
+ {
+ return strstr(dev_name(chan->device->dev), "sdma") ||
+diff -Nur linux-3.10.30.orig/include/linux/platform_data/dma-imx-sdma.h linux-linaro-stable-mx6/include/linux/platform_data/dma-imx-sdma.h
+--- linux-3.10.30.orig/include/linux/platform_data/dma-imx-sdma.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/platform_data/dma-imx-sdma.h 2014-05-15 20:34:14.938135903 +0200
+@@ -43,6 +43,9 @@
+ s32 dptc_dvfs_addr;
+ s32 utra_addr;
+ s32 ram_code_start_addr;
++ s32 mcu_2_ssish_addr;
++ s32 ssish_2_mcu_addr;
++ s32 hdmi_dma_addr;
+ };
+
+ /**
+diff -Nur linux-3.10.30.orig/include/linux/platform_data/mmc-esdhc-imx.h linux-linaro-stable-mx6/include/linux/platform_data/mmc-esdhc-imx.h
+--- linux-3.10.30.orig/include/linux/platform_data/mmc-esdhc-imx.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/platform_data/mmc-esdhc-imx.h 2014-05-15 20:34:14.958136046 +0200
+@@ -10,6 +10,8 @@
+ #ifndef __ASM_ARCH_IMX_ESDHC_H
+ #define __ASM_ARCH_IMX_ESDHC_H
+
++#include <linux/types.h>
++
+ enum wp_types {
+ ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
+ ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
+@@ -32,6 +34,7 @@
+ * @cd_gpio: gpio for card_detect interrupt
+ * @wp_type: type of write_protect method (see wp_types enum above)
+ * @cd_type: type of card_detect method (see cd_types enum above)
++ * @support_vsel: indicate it supports 1.8v switching
+ */
+
+ struct esdhc_platform_data {
+@@ -40,5 +43,7 @@
+ enum wp_types wp_type;
+ enum cd_types cd_type;
+ int max_bus_width;
++ bool support_vsel;
++ unsigned int delay_line;
+ };
+ #endif /* __ASM_ARCH_IMX_ESDHC_H */
+diff -Nur linux-3.10.30.orig/include/linux/pmic_status.h linux-linaro-stable-mx6/include/linux/pmic_status.h
+--- linux-3.10.30.orig/include/linux/pmic_status.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/pmic_status.h 2014-05-15 20:34:15.010136421 +0200
+@@ -0,0 +1,82 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++#ifndef __ASM_ARCH_MXC_PMIC_STATUS_H__
++#define __ASM_ARCH_MXC_PMIC_STATUS_H__
++#include <asm-generic/errno-base.h>
++#ifdef __KERNEL__
++#include <asm/uaccess.h> /* copy_{from,to}_user() */
++#endif
++/*!
++ * @file arch-mxc/pmic_status.h
++ * @brief PMIC APIs return code definition.
++ *
++ * @ingroup PMIC_CORE
++ */
++
++/*!
++ * @enum PMIC_STATUS
++ * @brief Define return values for all PMIC APIs.
++ *
++ * These return values are used by all of the PMIC APIs.
++ *
++ * @ingroup PMIC
++ */
++typedef enum {
++ PMIC_SUCCESS = 0, /*!< The requested operation was successfully
++ completed. */
++ PMIC_ERROR = -1, /*!< The requested operation could not be completed
++ due to an error. */
++ PMIC_PARAMETER_ERROR = -2, /*!< The requested operation failed because
++ one or more of the parameters was
++ invalid. */
++ PMIC_NOT_SUPPORTED = -3, /*!< The requested operation could not be
++ completed because the PMIC hardware
++ does not support it. */
++ PMIC_SYSTEM_ERROR_EINTR = -EINTR,
++
++ PMIC_MALLOC_ERROR = -5, /*!< Error in malloc function */
++ PMIC_UNSUBSCRIBE_ERROR = -6, /*!< Error in un-subscribe event */
++ PMIC_EVENT_NOT_SUBSCRIBED = -7, /*!< Event occur and not subscribed */
++ PMIC_EVENT_CALL_BACK = -8, /*!< Error - bad call back */
++ PMIC_CLIENT_NBOVERFLOW = -9, /*!< The requested operation could not be
++ completed because there are too many
++ PMIC client requests */
++} PMIC_STATUS;
++
++/*
++ * Bitfield macros that use rely on bitfield width/shift information.
++ */
++#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH))
++#define BITFVAL(field, val) ((val) << (field ## _LSH))
++#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH))
++
++/*
++ * Macros implementing error handling
++ */
++#define CHECK_ERROR(a) \
++do { \
++ int ret = (a); \
++ if (ret != PMIC_SUCCESS) \
++ return ret; \
++} while (0)
++
++#define CHECK_ERROR_KFREE(func, freeptrs) \
++do { \
++ int ret = (func); \
++ if (ret != PMIC_SUCCESS) { \
++ freeptrs; \
++ return ret; \
++ } \
++} while (0);
++
++#endif /* __ASM_ARCH_MXC_PMIC_STATUS_H__ */
+diff -Nur linux-3.10.30.orig/include/linux/power/imx6_usb_charger.h linux-linaro-stable-mx6/include/linux/power/imx6_usb_charger.h
+--- linux-3.10.30.orig/include/linux/power/imx6_usb_charger.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/power/imx6_usb_charger.h 2014-05-15 20:34:15.010136421 +0200
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef __IMXUSB6_CHARGER_H
++#define __IMXUSB6_CHARGER_H
++
++#include <linux/power_supply.h>
++enum battery_charging_spec {
++ BATTERY_CHARGING_SPEC_NONE = 0,
++ BATTERY_CHARGING_SPEC_UNKNOWN,
++ BATTERY_CHARGING_SPEC_1_0,
++ BATTERY_CHARGING_SPEC_1_1,
++ BATTERY_CHARGING_SPEC_1_2,
++};
++
++struct usb_charger {
++ /* The anatop regmap */
++ struct regmap *anatop;
++ /* USB controller */
++ struct device *dev;
++ struct power_supply psy;
++ struct mutex lock;
++
++ /* Compliant with Battery Charging Specification version (if any) */
++ enum battery_charging_spec bc;
++
++ /* properties */
++ unsigned present:1;
++ unsigned online:1;
++ unsigned max_current;
++ int (*connect)(struct usb_charger *charger);
++ int (*disconnect)(struct usb_charger *charger);
++ int (*set_power)(struct usb_charger *charger, unsigned mA);
++
++ int (*detect)(struct usb_charger *charger);
++};
++
++#ifdef CONFIG_IMX6_USB_CHARGER
++extern void imx6_usb_remove_charger(struct usb_charger *charger);
++extern int imx6_usb_create_charger(struct usb_charger *charger,
++ const char *name);
++extern int imx6_usb_vbus_disconnect(struct usb_charger *charger);
++extern int imx6_usb_vbus_connect(struct usb_charger *charger);
++extern int imx6_usb_charger_detect_post(struct usb_charger *charger);
++#else
++void imx6_usb_remove_charger(struct usb_charger *charger)
++{
++
++}
++
++int imx6_usb_create_charger(struct usb_charger *charger,
++ const char *name)
++{
++ return -ENODEV;
++}
++
++int imx6_usb_vbus_disconnect(struct usb_charger *charger)
++{
++ return -ENODEV;
++}
++
++int imx6_usb_vbus_connect(struct usb_charger *charger)
++{
++ return -ENODEV;
++}
++int imx6_usb_charger_detect_post(struct usb_charger *charger)
++{
++ return -ENODEV;
++}
++#endif
++
++#endif /* __IMXUSB6_CHARGER_H */
+diff -Nur linux-3.10.30.orig/include/linux/power/sabresd_battery.h linux-linaro-stable-mx6/include/linux/power/sabresd_battery.h
+--- linux-3.10.30.orig/include/linux/power/sabresd_battery.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/power/sabresd_battery.h 2014-05-15 20:34:15.010136421 +0200
+@@ -0,0 +1,65 @@
++/*
++ * sabresd_battery.h - Maxim 8903 USB/Adapter Charger Driver
++ *
++ * Copyright (C) 2011 Samsung Electronics
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ * Based on max8903_charger.h
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#ifndef __MAX8903_SABRESD_H__
++#define __MAX8903_SABRESD_H__
++
++struct max8903_pdata {
++ /*
++ * GPIOs
++ * cen, chg, flt, and usus are optional.
++ * dok, dcm, and uok are not optional depending on the status of
++ * dc_valid and usb_valid.
++ */
++ int cen; /* Charger Enable input */
++ int dok; /* DC(Adapter) Power OK output */
++ int uok; /* USB Power OK output */
++ int chg; /* Charger status output */
++ int flt; /* Fault output */
++ int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */
++ int usus; /* USB Suspend Input (1: suspended) */
++ int feature_flag;/* battery capacity feature(0:enable, 1:disable) */
++
++ /*
++ * DCM wired to Logic High Set this true when DCM pin connect to
++ * Logic high.
++ */
++ bool dcm_always_high;
++
++ /*
++ * DC(Adapter/TA) is wired
++ * When dc_valid is true,
++ * dok and dcm should be valid.
++ *
++ * At least one of dc_valid or usb_valid should be true.
++ */
++ bool dc_valid;
++ /*
++ * USB is wired
++ * When usb_valid is true,
++ * uok should be valid.
++ */
++ bool usb_valid;
++};
++
++#endif /* __SABRESD_BATTERY_H__ */
+diff -Nur linux-3.10.30.orig/include/linux/pxp_dma.h linux-linaro-stable-mx6/include/linux/pxp_dma.h
+--- linux-3.10.30.orig/include/linux/pxp_dma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/pxp_dma.h 2014-05-15 20:34:15.034136593 +0200
+@@ -0,0 +1,79 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _PXP_DMA
++#define _PXP_DMA
++
++#include <uapi/linux/pxp_dma.h>
++
++struct pxp_tx_desc {
++ struct dma_async_tx_descriptor txd;
++ struct list_head tx_list;
++ struct list_head list;
++ int len;
++ union {
++ struct pxp_layer_param s0_param;
++ struct pxp_layer_param out_param;
++ struct pxp_layer_param ol_param;
++ } layer_param;
++ struct pxp_proc_data proc_data;
++
++ u32 hist_status; /* Histogram output status */
++
++ struct pxp_tx_desc *next;
++};
++
++struct pxp_channel {
++ struct dma_chan dma_chan;
++ dma_cookie_t completed; /* last completed cookie */
++ enum pxp_channel_status status;
++ void *client; /* Only one client per channel */
++ unsigned int n_tx_desc;
++ struct pxp_tx_desc *desc; /* allocated tx-descriptors */
++ struct list_head active_list; /* active tx-descriptors */
++ struct list_head free_list; /* free tx-descriptors */
++ struct list_head queue; /* queued tx-descriptors */
++ struct list_head list; /* track queued channel number */
++ spinlock_t lock; /* protects sg[0,1], queue */
++ struct mutex chan_mutex; /* protects status, cookie, free_list */
++ int active_buffer;
++ unsigned int eof_irq;
++ char eof_name[16]; /* EOF IRQ name for request_irq() */
++};
++
++struct pxp_irq_info {
++ wait_queue_head_t waitq;
++ int irq_pending;
++ int hist_status;
++};
++
++#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd)
++#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan)
++
++void pxp_txd_ack(struct dma_async_tx_descriptor *txd,
++ struct pxp_channel *pxp_chan);
++
++#ifdef CONFIG_MXC_PXP_CLIENT_DEVICE
++int register_pxp_device(void);
++void unregister_pxp_device(void);
++#else
++int register_pxp_device(void) { return 0; }
++void unregister_pxp_device(void) {}
++#endif
++
++#endif
+diff -Nur linux-3.10.30.orig/include/linux/regulator/consumer.h linux-linaro-stable-mx6/include/linux/regulator/consumer.h
+--- linux-3.10.30.orig/include/linux/regulator/consumer.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/regulator/consumer.h 2014-05-15 20:34:15.054136738 +0200
+@@ -2,6 +2,7 @@
+ * consumer.h -- SoC Regulator consumer support.
+ *
+ * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Liam Girdwood <lrg@slimlogic.co.uk>
+ *
+@@ -105,6 +106,8 @@
+ #define REGULATOR_EVENT_FORCE_DISABLE 0x20
+ #define REGULATOR_EVENT_VOLTAGE_CHANGE 0x40
+ #define REGULATOR_EVENT_DISABLE 0x80
++#define REGULATOR_EVENT_PRE_DISABLE 0x100
++#define REGULATOR_EVENT_ENABLE 0x200
+
+ struct regulator;
+
+diff -Nur linux-3.10.30.orig/include/linux/regulator/pfuze100.h linux-linaro-stable-mx6/include/linux/regulator/pfuze100.h
+--- linux-3.10.30.orig/include/linux/regulator/pfuze100.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/regulator/pfuze100.h 2014-05-15 20:34:15.090136997 +0200
+@@ -0,0 +1,44 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++#ifndef __LINUX_REG_PFUZE100_H
++#define __LINUX_REG_PFUZE100_H
++
++#define PFUZE100_SW1AB 0
++#define PFUZE100_SW1C 1
++#define PFUZE100_SW2 2
++#define PFUZE100_SW3A 3
++#define PFUZE100_SW3B 4
++#define PFUZE100_SW4 5
++#define PFUZE100_SWBST 6
++#define PFUZE100_VSNVS 7
++#define PFUZE100_VREFDDR 8
++#define PFUZE100_VGEN1 9
++#define PFUZE100_VGEN2 10
++#define PFUZE100_VGEN3 11
++#define PFUZE100_VGEN4 12
++#define PFUZE100_VGEN5 13
++#define PFUZE100_VGEN6 14
++#define PFUZE100_MAX_REGULATOR 15
++
++struct regulator_init_data;
++
++struct pfuze_regulator_platform_data {
++ struct regulator_init_data *init_data[PFUZE100_MAX_REGULATOR];
++};
++
++#endif /* __LINUX_REG_PFUZE100_H */
+diff -Nur linux-3.10.30.orig/include/linux/reset.h linux-linaro-stable-mx6/include/linux/reset.h
+--- linux-3.10.30.orig/include/linux/reset.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/reset.h 2014-05-15 20:34:15.094137026 +0200
+@@ -12,6 +12,13 @@
+ void reset_control_put(struct reset_control *rstc);
+ struct reset_control *devm_reset_control_get(struct device *dev, const char *id);
+
++#ifdef CONFIG_RESET_CONTROLLER
+ int device_reset(struct device *dev);
++#else
++static inline int device_reset(struct device *dev)
++{
++ return 0;
++}
++#endif /* CONFIG_RESET_CONTROLLER */
+
+ #endif
+diff -Nur linux-3.10.30.orig/include/linux/sched.h linux-linaro-stable-mx6/include/linux/sched.h
+--- linux-3.10.30.orig/include/linux/sched.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/sched.h 2014-05-15 20:34:15.098137054 +0200
+@@ -889,6 +889,13 @@
+
+ bool cpus_share_cache(int this_cpu, int that_cpu);
+
++#ifdef CONFIG_SCHED_HMP
++struct hmp_domain {
++ struct cpumask cpus;
++ struct cpumask possible_cpus;
++ struct list_head hmp_domains;
++};
++#endif /* CONFIG_SCHED_HMP */
+ #else /* CONFIG_SMP */
+
+ struct sched_domain_attr;
+@@ -935,6 +942,12 @@
+ u64 last_runnable_update;
+ s64 decay_count;
+ unsigned long load_avg_contrib;
++ unsigned long load_avg_ratio;
++#ifdef CONFIG_SCHED_HMP
++ u64 hmp_last_up_migration;
++ u64 hmp_last_down_migration;
++#endif
++ u32 usage_avg_sum;
+ };
+
+ #ifdef CONFIG_SCHEDSTATS
+diff -Nur linux-3.10.30.orig/include/linux/serial_core.h linux-linaro-stable-mx6/include/linux/serial_core.h
+--- linux-3.10.30.orig/include/linux/serial_core.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/serial_core.h 2014-05-15 20:34:15.114137169 +0200
+@@ -31,6 +31,13 @@
+ #include <linux/sysrq.h>
+ #include <uapi/linux/serial_core.h>
+
++#ifdef CONFIG_SERIAL_CORE_CONSOLE
++#define uart_console(port) \
++ ((port)->cons && (port)->cons->index == (port)->line)
++#else
++#define uart_console(port) (0)
++#endif
++
+ struct uart_port;
+ struct serial_struct;
+ struct device;
+diff -Nur linux-3.10.30.orig/include/linux/spi/spi_bitbang.h linux-linaro-stable-mx6/include/linux/spi/spi_bitbang.h
+--- linux-3.10.30.orig/include/linux/spi/spi_bitbang.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/spi/spi_bitbang.h 2014-05-15 20:34:15.222137947 +0200
+@@ -4,11 +4,7 @@
+ #include <linux/workqueue.h>
+
+ struct spi_bitbang {
+- struct workqueue_struct *workqueue;
+- struct work_struct work;
+-
+ spinlock_t lock;
+- struct list_head queue;
+ u8 busy;
+ u8 use_dma;
+ u8 flags; /* extra spi->mode support */
+@@ -41,7 +37,6 @@
+ */
+ extern int spi_bitbang_setup(struct spi_device *spi);
+ extern void spi_bitbang_cleanup(struct spi_device *spi);
+-extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
+ extern int spi_bitbang_setup_transfer(struct spi_device *spi,
+ struct spi_transfer *t);
+
+diff -Nur linux-3.10.30.orig/include/linux/spi/spi.h linux-linaro-stable-mx6/include/linux/spi/spi.h
+--- linux-3.10.30.orig/include/linux/spi/spi.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/spi/spi.h 2014-05-15 20:34:15.222137947 +0200
+@@ -23,6 +23,7 @@
+ #include <linux/mod_devicetable.h>
+ #include <linux/slab.h>
+ #include <linux/kthread.h>
++#include <linux/completion.h>
+
+ /*
+ * INTERFACES between SPI master-side drivers and SPI infrastructure.
+@@ -74,7 +75,7 @@
+ struct spi_master *master;
+ u32 max_speed_hz;
+ u8 chip_select;
+- u8 mode;
++ u16 mode;
+ #define SPI_CPHA 0x01 /* clock phase */
+ #define SPI_CPOL 0x02 /* clock polarity */
+ #define SPI_MODE_0 (0|0) /* (original MicroWire) */
+@@ -87,6 +88,10 @@
+ #define SPI_LOOP 0x20 /* loopback mode */
+ #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
+ #define SPI_READY 0x80 /* slave pulls low to pause */
++#define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
++#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
++#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
++#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
+ u8 bits_per_word;
+ int irq;
+ void *controller_state;
+@@ -146,8 +151,7 @@
+ }
+
+ struct spi_message;
+-
+-
++struct spi_transfer;
+
+ /**
+ * struct spi_driver - Host side "protocol" driver
+@@ -233,6 +237,8 @@
+ * suported. If set, the SPI core will reject any transfer with an
+ * unsupported bits_per_word. If not set, this value is simply ignored,
+ * and it's up to the individual driver to perform any validation.
++ * @min_speed_hz: Lowest supported transfer speed
++ * @max_speed_hz: Highest supported transfer speed
+ * @flags: other constraints relevant to this driver
+ * @bus_lock_spinlock: spinlock for SPI bus locking
+ * @bus_lock_mutex: mutex for SPI bus locking
+@@ -251,9 +257,15 @@
+ * @queue_lock: spinlock to syncronise access to message queue
+ * @queue: message queue
+ * @cur_msg: the currently in-flight message
++ * @cur_msg_prepared: spi_prepare_message was called for the currently
++ * in-flight message
++ * @xfer_completion: used by core tranfer_one_message()
+ * @busy: message pump is busy
+ * @running: message pump is running
+ * @rt: whether this queue is set to run as a realtime task
++ * @auto_runtime_pm: the core should ensure a runtime PM reference is held
++ * while the hardware is prepared, using the parent
++ * device for the spidev
+ * @prepare_transfer_hardware: a message will soon arrive from the queue
+ * so the subsystem requests the driver to prepare the transfer hardware
+ * by issuing this call
+@@ -265,6 +277,16 @@
+ * @unprepare_transfer_hardware: there are currently no more messages on the
+ * queue so the subsystem notifies the driver that it may relax the
+ * hardware by issuing this call
++ * @set_cs: assert or deassert chip select, true to assert. May be called
++ * from interrupt context.
++ * @prepare_message: set up the controller to transfer a single message,
++ * for example doing DMA mapping. Called from threaded
++ * context.
++ * @transfer_one: transfer a single spi_transfer. When the
++ * driver is finished with this transfer it must call
++ * spi_finalize_current_transfer() so the subsystem can issue
++ * the next transfer
++ * @unprepare_message: undo any work done by prepare_message().
+ * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS
+ * number. Any individual value may be -ENOENT for CS lines that
+ * are not GPIOs (driven by the SPI controller itself).
+@@ -308,6 +330,13 @@
+
+ /* bitmask of supported bits_per_word for transfers */
+ u32 bits_per_word_mask;
++#define SPI_BPW_MASK(bits) BIT((bits) - 1)
++#define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1))
++#define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1))
++
++ /* limits on transfer speed */
++ u32 min_speed_hz;
++ u32 max_speed_hz;
+
+ /* other constraints relevant to this driver */
+ u16 flags;
+@@ -371,11 +400,27 @@
+ bool busy;
+ bool running;
+ bool rt;
++ bool auto_runtime_pm;
++ bool cur_msg_prepared;
++ struct completion xfer_completion;
+
+ int (*prepare_transfer_hardware)(struct spi_master *master);
+ int (*transfer_one_message)(struct spi_master *master,
+ struct spi_message *mesg);
+ int (*unprepare_transfer_hardware)(struct spi_master *master);
++ int (*prepare_message)(struct spi_master *master,
++ struct spi_message *message);
++ int (*unprepare_message)(struct spi_master *master,
++ struct spi_message *message);
++
++ /*
++ * These hooks are for drivers that use a generic implementation
++ * of transfer_one_message() provied by the core.
++ */
++ void (*set_cs)(struct spi_device *spi, bool enable);
++ int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
++ struct spi_transfer *transfer);
++
+ /* gpio chip select */
+ int *cs_gpios;
+ };
+@@ -410,12 +455,15 @@
+ /* Calls the driver make to interact with the message queue */
+ extern struct spi_message *spi_get_next_queued_message(struct spi_master *master);
+ extern void spi_finalize_current_message(struct spi_master *master);
++extern void spi_finalize_current_transfer(struct spi_master *master);
+
+ /* the spi driver core manages memory for the spi_master classdev */
+ extern struct spi_master *
+ spi_alloc_master(struct device *host, unsigned size);
+
+ extern int spi_register_master(struct spi_master *master);
++extern int devm_spi_register_master(struct device *dev,
++ struct spi_master *master);
+ extern void spi_unregister_master(struct spi_master *master);
+
+ extern struct spi_master *spi_busnum_to_master(u16 busnum);
+@@ -445,6 +493,10 @@
+ * @rx_buf: data to be read (dma-safe memory), or NULL
+ * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
+ * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
++ * @tx_nbits: number of bits used for writting. If 0 the default
++ * (SPI_NBITS_SINGLE) is used.
++ * @rx_nbits: number of bits used for reading. If 0 the default
++ * (SPI_NBITS_SINGLE) is used.
+ * @len: size of rx and tx buffers (in bytes)
+ * @speed_hz: Select a speed other than the device default for this
+ * transfer. If 0 the default (from @spi_device) is used.
+@@ -499,6 +551,11 @@
+ * by the results of previous messages and where the whole transaction
+ * ends when the chipselect goes intactive.
+ *
++ * When SPI can transfer in 1x,2x or 4x. It can get this tranfer information
++ * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
++ * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
++ * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
++ *
+ * The code that submits an spi_message (and its spi_transfers)
+ * to the lower layers is responsible for managing its memory.
+ * Zero-initialize every field you don't set up explicitly, to
+@@ -519,6 +576,11 @@
+ dma_addr_t rx_dma;
+
+ unsigned cs_change:1;
++ u8 tx_nbits;
++ u8 rx_nbits;
++#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
++#define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
++#define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
+ u8 bits_per_word;
+ u16 delay_usecs;
+ u32 speed_hz;
+@@ -575,6 +637,7 @@
+ /* completion is reported through a callback */
+ void (*complete)(void *context);
+ void *context;
++ unsigned frame_length;
+ unsigned actual_length;
+ int status;
+
+@@ -866,7 +929,7 @@
+ /* mode becomes spi_device.mode, and is essential for chips
+ * where the default of SPI_CS_HIGH = 0 is wrong.
+ */
+- u8 mode;
++ u16 mode;
+
+ /* ... may need additional spi_device chip config data here.
+ * avoid stuff protocol drivers can set; but include stuff
+diff -Nur linux-3.10.30.orig/include/linux/sysfs.h linux-linaro-stable-mx6/include/linux/sysfs.h
+--- linux-3.10.30.orig/include/linux/sysfs.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/sysfs.h 2014-05-15 20:34:15.330138726 +0200
+@@ -92,6 +92,15 @@
+ #define __ATTR_IGNORE_LOCKDEP __ATTR
+ #endif
+
++#define ATTRIBUTE_GROUPS(name) \
++static const struct attribute_group name##_group = { \
++ .attrs = name##_attrs, \
++}; \
++static const struct attribute_group *name##_groups[] = { \
++ &name##_group, \
++ NULL, \
++}
++
+ #define attr_name(_attr) (_attr).attr.name
+
+ struct file;
+diff -Nur linux-3.10.30.orig/include/linux/usb/chipidea.h linux-linaro-stable-mx6/include/linux/usb/chipidea.h
+--- linux-3.10.30.orig/include/linux/usb/chipidea.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/usb/chipidea.h 2014-05-15 20:34:15.374139042 +0200
+@@ -7,32 +7,44 @@
+
+ #include <linux/usb/otg.h>
+
+-struct ci13xxx;
+-struct ci13xxx_platform_data {
++struct ci_hdrc;
++struct ci_hdrc_platform_data {
+ const char *name;
+ /* offset of the capability registers */
+ uintptr_t capoffset;
+ unsigned power_budget;
+ struct usb_phy *phy;
++ enum usb_phy_interface phy_mode;
+ unsigned long flags;
+-#define CI13XXX_REGS_SHARED BIT(0)
+-#define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)
+-#define CI13XXX_PULLUP_ON_VBUS BIT(2)
+-#define CI13XXX_DISABLE_STREAMING BIT(3)
+-
+-#define CI13XXX_CONTROLLER_RESET_EVENT 0
+-#define CI13XXX_CONTROLLER_STOPPED_EVENT 1
+- void (*notify_event) (struct ci13xxx *ci, unsigned event);
++#define CI_HDRC_REGS_SHARED BIT(0)
++#define CI_HDRC_REQUIRE_TRANSCEIVER BIT(1)
++#define CI_HDRC_SUPPORTS_RUNTIME_PM BIT(2)
++#define CI_HDRC_DISABLE_STREAMING BIT(3)
++ /*
++ * Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1,
++ * but otg is not supported (no register otgsc).
++ */
++#define CI_HDRC_DUAL_ROLE_NOT_OTG BIT(4)
++#define CI_HDRC_IMX28_WRITE_FIX BIT(5)
++#define CI_HDRC_IMX_EHCI_QUIRK BIT(6)
++ enum usb_dr_mode dr_mode;
++#define CI_HDRC_CONTROLLER_RESET_EVENT 0
++#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
++#define CI_HDRC_CONTROLLER_CHARGER_EVENT 2
++#define CI_HDRC_CONTROLLER_CHARGER_POST_EVENT 3
++ int (*notify_event) (struct ci_hdrc *ci, unsigned event);
++#define CI_HDRC_NOTIFY_RET_DEFER_EVENT 1
++ struct regulator *reg_vbus;
+ };
+
+ /* Default offset of capability registers */
+ #define DEF_CAPOFFSET 0x100
+
+-/* Add ci13xxx device */
+-struct platform_device *ci13xxx_add_device(struct device *dev,
++/* Add ci hdrc device */
++struct platform_device *ci_hdrc_add_device(struct device *dev,
+ struct resource *res, int nres,
+- struct ci13xxx_platform_data *platdata);
+-/* Remove ci13xxx device */
+-void ci13xxx_remove_device(struct platform_device *pdev);
++ struct ci_hdrc_platform_data *platdata);
++/* Remove ci hdrc device */
++void ci_hdrc_remove_device(struct platform_device *pdev);
+
+ #endif
+diff -Nur linux-3.10.30.orig/include/linux/usb/of.h linux-linaro-stable-mx6/include/linux/usb/of.h
+--- linux-3.10.30.orig/include/linux/usb/of.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/usb/of.h 2014-05-15 20:34:15.390139157 +0200
+@@ -0,0 +1,32 @@
++/*
++ * OF helpers for usb devices.
++ *
++ * This file is released under the GPLv2
++ */
++
++#ifndef __LINUX_USB_OF_H
++#define __LINUX_USB_OF_H
++
++#include <linux/usb/otg.h>
++#include <linux/usb/phy.h>
++
++#if IS_ENABLED(CONFIG_OF)
++enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
++#else
++static inline enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
++{
++ return USB_DR_MODE_UNKNOWN;
++}
++#endif
++
++#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_USB_PHY)
++enum usb_phy_interface of_usb_get_phy_mode(struct device_node *np);
++#else
++static inline enum usb_phy_interface of_usb_get_phy_mode(struct device_node *np)
++{
++ return USBPHY_INTERFACE_MODE_UNKNOWN;
++}
++
++#endif
++
++#endif /* __LINUX_USB_OF_H */
+diff -Nur linux-3.10.30.orig/include/linux/usb/otg.h linux-linaro-stable-mx6/include/linux/usb/otg.h
+--- linux-3.10.30.orig/include/linux/usb/otg.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/usb/otg.h 2014-05-15 20:34:15.398139215 +0200
+@@ -92,4 +92,11 @@
+ /* for OTG controller drivers (and maybe other stuff) */
+ extern int usb_bus_start_enum(struct usb_bus *bus, unsigned port_num);
+
++enum usb_dr_mode {
++ USB_DR_MODE_UNKNOWN,
++ USB_DR_MODE_HOST,
++ USB_DR_MODE_PERIPHERAL,
++ USB_DR_MODE_OTG,
++};
++
+ #endif /* __LINUX_USB_OTG_H */
+diff -Nur linux-3.10.30.orig/include/linux/usb/phy.h linux-linaro-stable-mx6/include/linux/usb/phy.h
+--- linux-3.10.30.orig/include/linux/usb/phy.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/usb/phy.h 2014-05-15 20:34:15.398139215 +0200
+@@ -12,6 +12,15 @@
+ #include <linux/notifier.h>
+ #include <linux/usb.h>
+
++enum usb_phy_interface {
++ USBPHY_INTERFACE_MODE_UNKNOWN,
++ USBPHY_INTERFACE_MODE_UTMI,
++ USBPHY_INTERFACE_MODE_UTMIW,
++ USBPHY_INTERFACE_MODE_ULPI,
++ USBPHY_INTERFACE_MODE_SERIAL,
++ USBPHY_INTERFACE_MODE_HSIC,
++};
++
+ enum usb_phy_events {
+ USB_EVENT_NONE, /* no events or cable disconnected */
+ USB_EVENT_VBUS, /* vbus valid event */
+@@ -102,11 +111,23 @@
+ int (*set_suspend)(struct usb_phy *x,
+ int suspend);
+
++ /*
++ * Set wakeup enable for PHY, in that case, the PHY can be
++ * waken up from suspend status due to external events,
++ * like vbus change, dp/dm change and id.
++ */
++ int (*set_wakeup)(struct usb_phy *x, bool enabled);
++
+ /* notify phy connect status change */
+ int (*notify_connect)(struct usb_phy *x,
+ enum usb_device_speed speed);
+ int (*notify_disconnect)(struct usb_phy *x,
+ enum usb_device_speed speed);
++ int (*notify_suspend)(struct usb_phy *x,
++ enum usb_device_speed speed);
++ int (*notify_resume)(struct usb_phy *x,
++ enum usb_device_speed speed);
++
+ };
+
+ /**
+@@ -256,6 +277,15 @@
+ }
+
+ static inline int
++usb_phy_set_wakeup(struct usb_phy *x, bool enabled)
++{
++ if (x && x->set_wakeup)
++ return x->set_wakeup(x, enabled);
++ else
++ return 0;
++}
++
++static inline int
+ usb_phy_notify_connect(struct usb_phy *x, enum usb_device_speed speed)
+ {
+ if (x->notify_connect)
+@@ -272,6 +302,24 @@
+ else
+ return 0;
+ }
++
++static inline int usb_phy_notify_suspend
++ (struct usb_phy *x, enum usb_device_speed speed)
++{
++ if (x && x->notify_suspend)
++ return x->notify_suspend(x, speed);
++ else
++ return 0;
++}
++
++static inline int usb_phy_notify_resume
++ (struct usb_phy *x, enum usb_device_speed speed)
++{
++ if (x && x->notify_resume)
++ return x->notify_resume(x, speed);
++ else
++ return 0;
++}
+
+ /* notifiers */
+ static inline int
+diff -Nur linux-3.10.30.orig/include/linux/vexpress.h linux-linaro-stable-mx6/include/linux/vexpress.h
+--- linux-3.10.30.orig/include/linux/vexpress.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/vexpress.h 2014-05-15 20:34:15.402139244 +0200
+@@ -68,7 +68,8 @@
+ */
+ struct vexpress_config_bridge_info {
+ const char *name;
+- void *(*func_get)(struct device *dev, struct device_node *node);
++ void *(*func_get)(struct device *dev, struct device_node *node,
++ const char *id);
+ void (*func_put)(void *func);
+ int (*func_exec)(void *func, int offset, bool write, u32 *data);
+ };
+@@ -87,12 +88,17 @@
+
+ struct vexpress_config_func;
+
+-struct vexpress_config_func *__vexpress_config_func_get(struct device *dev,
+- struct device_node *node);
++struct vexpress_config_func *__vexpress_config_func_get(
++ struct vexpress_config_bridge *bridge,
++ struct device *dev,
++ struct device_node *node,
++ const char *id);
++#define vexpress_config_func_get(bridge, id) \
++ __vexpress_config_func_get(bridge, NULL, NULL, id)
+ #define vexpress_config_func_get_by_dev(dev) \
+- __vexpress_config_func_get(dev, NULL)
++ __vexpress_config_func_get(NULL, dev, NULL, NULL)
+ #define vexpress_config_func_get_by_node(node) \
+- __vexpress_config_func_get(NULL, node)
++ __vexpress_config_func_get(NULL, NULL, node, NULL)
+ void vexpress_config_func_put(struct vexpress_config_func *func);
+
+ /* Both may sleep! */
+@@ -120,7 +126,53 @@
+ struct clk *vexpress_osc_setup(struct device *dev);
+ void vexpress_osc_of_setup(struct device_node *node);
+
++struct clk *vexpress_clk_register_spc(const char *name, int cluster_id);
++void vexpress_clk_of_register_spc(void);
++
+ void vexpress_clk_init(void __iomem *sp810_base);
+ void vexpress_clk_of_init(void);
+
++/* SPC */
++
++#define VEXPRESS_SPC_WAKE_INTR_IRQ(cluster, cpu) \
++ (1 << (4 * (cluster) + (cpu)))
++#define VEXPRESS_SPC_WAKE_INTR_FIQ(cluster, cpu) \
++ (1 << (7 * (cluster) + (cpu)))
++#define VEXPRESS_SPC_WAKE_INTR_SWDOG (1 << 10)
++#define VEXPRESS_SPC_WAKE_INTR_GTIMER (1 << 11)
++#define VEXPRESS_SPC_WAKE_INTR_MASK 0xFFF
++
++#ifdef CONFIG_VEXPRESS_SPC
++extern bool vexpress_spc_check_loaded(void);
++extern void vexpress_spc_set_cpu_wakeup_irq(u32 cpu, u32 cluster, bool set);
++extern void vexpress_spc_set_global_wakeup_intr(bool set);
++extern int vexpress_spc_get_freq_table(u32 cluster, u32 **fptr);
++extern int vexpress_spc_get_performance(u32 cluster, u32 *freq);
++extern int vexpress_spc_set_performance(u32 cluster, u32 freq);
++extern void vexpress_spc_write_resume_reg(u32 cluster, u32 cpu, u32 addr);
++extern int vexpress_spc_get_nb_cpus(u32 cluster);
++extern void vexpress_spc_powerdown_enable(u32 cluster, bool enable);
++#else
++static inline bool vexpress_spc_check_loaded(void) { return false; }
++static inline void vexpress_spc_set_cpu_wakeup_irq(u32 cpu, u32 cluster,
++ bool set) { }
++static inline void vexpress_spc_set_global_wakeup_intr(bool set) { }
++static inline int vexpress_spc_get_freq_table(u32 cluster, u32 **fptr)
++{
++ return -ENODEV;
++}
++static inline int vexpress_spc_get_performance(u32 cluster, u32 *freq)
++{
++ return -ENODEV;
++}
++static inline int vexpress_spc_set_performance(u32 cluster, u32 freq)
++{
++ return -ENODEV;
++}
++static inline void vexpress_spc_write_resume_reg(u32 cluster,
++ u32 cpu, u32 addr) { }
++static inline int vexpress_spc_get_nb_cpus(u32 cluster) { return -ENODEV; }
++static inline void vexpress_spc_powerdown_enable(u32 cluster, bool enable) { }
++#endif
++
+ #endif
+diff -Nur linux-3.10.30.orig/include/linux/vmstat.h linux-linaro-stable-mx6/include/linux/vmstat.h
+--- linux-3.10.30.orig/include/linux/vmstat.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/vmstat.h 2014-05-15 20:34:15.406139273 +0200
+@@ -195,7 +195,7 @@
+ extern void dec_zone_state(struct zone *, enum zone_stat_item);
+ extern void __dec_zone_state(struct zone *, enum zone_stat_item);
+
+-void refresh_cpu_vm_stats(int);
++bool refresh_cpu_vm_stats(int);
+ void refresh_zone_stat_thresholds(void);
+
+ void drain_zonestat(struct zone *zone, struct per_cpu_pageset *);
+diff -Nur linux-3.10.30.orig/include/linux/workqueue.h linux-linaro-stable-mx6/include/linux/workqueue.h
+--- linux-3.10.30.orig/include/linux/workqueue.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/workqueue.h 2014-05-15 20:34:15.430139445 +0200
+@@ -303,6 +303,33 @@
+ WQ_CPU_INTENSIVE = 1 << 5, /* cpu instensive workqueue */
+ WQ_SYSFS = 1 << 6, /* visible in sysfs, see wq_sysfs_register() */
+
++ /*
++ * Per-cpu workqueues are generally preferred because they tend to
++ * show better performance thanks to cache locality. Per-cpu
++ * workqueues exclude the scheduler from choosing the CPU to
++ * execute the worker threads, which has an unfortunate side effect
++ * of increasing power consumption.
++ *
++ * The scheduler considers a CPU idle if it doesn't have any task
++ * to execute and tries to keep idle cores idle to conserve power;
++ * however, for example, a per-cpu work item scheduled from an
++ * interrupt handler on an idle CPU will force the scheduler to
++ * excute the work item on that CPU breaking the idleness, which in
++ * turn may lead to more scheduling choices which are sub-optimal
++ * in terms of power consumption.
++ *
++ * Workqueues marked with WQ_POWER_EFFICIENT are per-cpu by default
++ * but become unbound if workqueue.power_efficient kernel param is
++ * specified. Per-cpu workqueues which are identified to
++ * contribute significantly to power-consumption are identified and
++ * marked with this flag and enabling the power_efficient mode
++ * leads to noticeable power saving at the cost of small
++ * performance disadvantage.
++ *
++ * http://thread.gmane.org/gmane.linux.kernel/1480396
++ */
++ WQ_POWER_EFFICIENT = 1 << 7,
++
+ __WQ_DRAINING = 1 << 16, /* internal: workqueue is draining */
+ __WQ_ORDERED = 1 << 17, /* internal: workqueue is ordered */
+
+@@ -333,11 +360,19 @@
+ *
+ * system_freezable_wq is equivalent to system_wq except that it's
+ * freezable.
++ *
++ * *_power_efficient_wq are inclined towards saving power and converted
++ * into WQ_UNBOUND variants if 'wq_power_efficient' is enabled; otherwise,
++ * they are same as their non-power-efficient counterparts - e.g.
++ * system_power_efficient_wq is identical to system_wq if
++ * 'wq_power_efficient' is disabled. See WQ_POWER_EFFICIENT for more info.
+ */
+ extern struct workqueue_struct *system_wq;
+ extern struct workqueue_struct *system_long_wq;
+ extern struct workqueue_struct *system_unbound_wq;
+ extern struct workqueue_struct *system_freezable_wq;
++extern struct workqueue_struct *system_power_efficient_wq;
++extern struct workqueue_struct *system_freezable_power_efficient_wq;
+
+ static inline struct workqueue_struct * __deprecated __system_nrt_wq(void)
+ {
+diff -Nur linux-3.10.30.orig/include/linux/zbud.h linux-linaro-stable-mx6/include/linux/zbud.h
+--- linux-3.10.30.orig/include/linux/zbud.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/linux/zbud.h 2014-05-15 20:34:15.430139445 +0200
+@@ -0,0 +1,22 @@
++#ifndef _ZBUD_H_
++#define _ZBUD_H_
++
++#include <linux/types.h>
++
++struct zbud_pool;
++
++struct zbud_ops {
++ int (*evict)(struct zbud_pool *pool, unsigned long handle);
++};
++
++struct zbud_pool *zbud_create_pool(gfp_t gfp, struct zbud_ops *ops);
++void zbud_destroy_pool(struct zbud_pool *pool);
++int zbud_alloc(struct zbud_pool *pool, int size, gfp_t gfp,
++ unsigned long *handle);
++void zbud_free(struct zbud_pool *pool, unsigned long handle);
++int zbud_reclaim_page(struct zbud_pool *pool, unsigned int retries);
++void *zbud_map(struct zbud_pool *pool, unsigned long handle);
++void zbud_unmap(struct zbud_pool *pool, unsigned long handle);
++int zbud_get_pool_size(struct zbud_pool *pool);
++
++#endif /* _ZBUD_H_ */
+diff -Nur linux-3.10.30.orig/include/sound/memalloc.h linux-linaro-stable-mx6/include/sound/memalloc.h
+--- linux-3.10.30.orig/include/sound/memalloc.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/sound/memalloc.h 2014-05-15 20:34:15.798142096 +0200
+@@ -52,6 +52,11 @@
+ #else
+ #define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_DEV /* no SG-buf support */
+ #endif
++#ifdef CONFIG_GENERIC_ALLOCATOR
++#define SNDRV_DMA_TYPE_DEV_IRAM 4 /* generic device iram-buffer */
++#else
++#define SNDRV_DMA_TYPE_DEV_IRAM SNDRV_DMA_TYPE_DEV
++#endif
+
+ /*
+ * info for buffer allocation
+diff -Nur linux-3.10.30.orig/include/sound/wm8962.h linux-linaro-stable-mx6/include/sound/wm8962.h
+--- linux-3.10.30.orig/include/sound/wm8962.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/sound/wm8962.h 2014-05-15 20:34:15.834142355 +0200
+@@ -55,6 +55,9 @@
+ * in a DC measurement configuration.
+ */
+ bool in4_dc_measure;
++
++ /* MCLK for wm8962 */
++ struct clk *codec_mclk;
+ };
+
+ #endif
+diff -Nur linux-3.10.30.orig/include/trace/events/arm-ipi.h linux-linaro-stable-mx6/include/trace/events/arm-ipi.h
+--- linux-3.10.30.orig/include/trace/events/arm-ipi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/trace/events/arm-ipi.h 2014-05-15 20:34:15.846142441 +0200
+@@ -0,0 +1,100 @@
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM arm-ipi
++
++#if !defined(_TRACE_ARM_IPI_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _TRACE_ARM_IPI_H
++
++#include <linux/tracepoint.h>
++
++#define show_arm_ipi_name(val) \
++ __print_symbolic(val, \
++ { 0, "IPI_WAKEUP" }, \
++ { 1, "IPI_TIMER" }, \
++ { 2, "IPI_RESCHEDULE" }, \
++ { 3, "IPI_CALL_FUNC" }, \
++ { 4, "IPI_CALL_FUNC_SINGLE" }, \
++ { 5, "IPI_CPU_STOP" }, \
++ { 6, "IPI_COMPLETION" }, \
++ { 7, "IPI_CPU_BACKTRACE" })
++
++DECLARE_EVENT_CLASS(arm_ipi,
++
++ TP_PROTO(unsigned int ipi_nr),
++
++ TP_ARGS(ipi_nr),
++
++ TP_STRUCT__entry(
++ __field( unsigned int, ipi )
++ ),
++
++ TP_fast_assign(
++ __entry->ipi = ipi_nr;
++ ),
++
++ TP_printk("ipi=%u [action=%s]", __entry->ipi,
++ show_arm_ipi_name(__entry->ipi))
++);
++
++/**
++ * arm_ipi_entry - called in the arm-generic ipi handler immediately before
++ * entering ipi-type handler
++ * @ipi_nr: ipi number
++ *
++ * When used in combination with the arm_ipi_exit tracepoint
++ * we can determine the ipi handler runtine.
++ */
++DEFINE_EVENT(arm_ipi, arm_ipi_entry,
++
++ TP_PROTO(unsigned int ipi_nr),
++
++ TP_ARGS(ipi_nr)
++);
++
++/**
++ * arm_ipi_exit - called in the arm-generic ipi handler immediately
++ * after the ipi-type handler returns
++ * @ipi_nr: ipi number
++ *
++ * When used in combination with the arm_ipi_entry tracepoint
++ * we can determine the ipi handler runtine.
++ */
++DEFINE_EVENT(arm_ipi, arm_ipi_exit,
++
++ TP_PROTO(unsigned int ipi_nr),
++
++ TP_ARGS(ipi_nr)
++);
++
++/**
++ * arm_ipi_send - called as the ipi target mask is built, immediately
++ * before the register is written
++ * @ipi_nr: ipi number
++ * @dest: cpu to send to
++ *
++ * When used in combination with the arm_ipi_entry tracepoint
++ * we can determine the ipi raise to run latency.
++ */
++TRACE_EVENT(arm_ipi_send,
++
++ TP_PROTO(unsigned int ipi_nr, int dest),
++
++ TP_ARGS(ipi_nr, dest),
++
++ TP_STRUCT__entry(
++ __field( unsigned int, ipi )
++ __field( int , dest )
++ ),
++
++ TP_fast_assign(
++ __entry->ipi = ipi_nr;
++ __entry->dest = dest;
++ ),
++
++ TP_printk("dest=%d ipi=%u [action=%s]", __entry->dest,
++ __entry->ipi, show_arm_ipi_name(__entry->ipi))
++);
++
++#endif /* _TRACE_ARM_IPI_H */
++
++/* This part must be outside protection */
++#include <trace/define_trace.h>
+diff -Nur linux-3.10.30.orig/include/trace/events/f2fs.h linux-linaro-stable-mx6/include/trace/events/f2fs.h
+--- linux-3.10.30.orig/include/trace/events/f2fs.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/trace/events/f2fs.h 2014-05-15 20:34:15.858142528 +0200
+@@ -36,6 +36,11 @@
+ { CURSEG_COLD_NODE, "Cold NODE" }, \
+ { NO_CHECK_TYPE, "No TYPE" })
+
++#define show_file_type(type) \
++ __print_symbolic(type, \
++ { 0, "FILE" }, \
++ { 1, "DIR" })
++
+ #define show_gc_type(type) \
+ __print_symbolic(type, \
+ { FG_GC, "Foreground GC" }, \
+@@ -623,6 +628,52 @@
+ __entry->size)
+ );
+
++DECLARE_EVENT_CLASS(f2fs__page,
++
++ TP_PROTO(struct page *page, int type),
++
++ TP_ARGS(page, type),
++
++ TP_STRUCT__entry(
++ __field(dev_t, dev)
++ __field(ino_t, ino)
++ __field(int, type)
++ __field(int, dir)
++ __field(pgoff_t, index)
++ __field(int, dirty)
++ ),
++
++ TP_fast_assign(
++ __entry->dev = page->mapping->host->i_sb->s_dev;
++ __entry->ino = page->mapping->host->i_ino;
++ __entry->type = type;
++ __entry->dir = S_ISDIR(page->mapping->host->i_mode);
++ __entry->index = page->index;
++ __entry->dirty = PageDirty(page);
++ ),
++
++ TP_printk("dev = (%d,%d), ino = %lu, %s, %s, index = %lu, dirty = %d",
++ show_dev_ino(__entry),
++ show_block_type(__entry->type),
++ show_file_type(__entry->dir),
++ (unsigned long)__entry->index,
++ __entry->dirty)
++);
++
++DEFINE_EVENT(f2fs__page, f2fs_set_page_dirty,
++
++ TP_PROTO(struct page *page, int type),
++
++ TP_ARGS(page, type)
++);
++
++DEFINE_EVENT(f2fs__page, f2fs_vm_page_mkwrite,
++
++ TP_PROTO(struct page *page, int type),
++
++ TP_ARGS(page, type)
++);
++
+ TRACE_EVENT(f2fs_submit_write_page,
+
+ TP_PROTO(struct page *page, block_t blk_addr, int type),
+diff -Nur linux-3.10.30.orig/include/trace/events/power_cpu_migrate.h linux-linaro-stable-mx6/include/trace/events/power_cpu_migrate.h
+--- linux-3.10.30.orig/include/trace/events/power_cpu_migrate.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/trace/events/power_cpu_migrate.h 2014-05-15 20:34:15.870142615 +0200
+@@ -0,0 +1,67 @@
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM power
++
++#if !defined(_TRACE_POWER_CPU_MIGRATE_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _TRACE_POWER_CPU_MIGRATE_H
++
++#include <linux/tracepoint.h>
++
++#define __cpu_migrate_proto \
++ TP_PROTO(u64 timestamp, \
++ u32 cpu_hwid)
++#define __cpu_migrate_args \
++ TP_ARGS(timestamp, \
++ cpu_hwid)
++
++DECLARE_EVENT_CLASS(cpu_migrate,
++
++ __cpu_migrate_proto,
++ __cpu_migrate_args,
++
++ TP_STRUCT__entry(
++ __field(u64, timestamp )
++ __field(u32, cpu_hwid )
++ ),
++
++ TP_fast_assign(
++ __entry->timestamp = timestamp;
++ __entry->cpu_hwid = cpu_hwid;
++ ),
++
++ TP_printk("timestamp=%llu cpu_hwid=0x%08lX",
++ (unsigned long long)__entry->timestamp,
++ (unsigned long)__entry->cpu_hwid
++ )
++);
++
++#define __define_cpu_migrate_event(name) \
++ DEFINE_EVENT(cpu_migrate, cpu_migrate_##name, \
++ __cpu_migrate_proto, \
++ __cpu_migrate_args \
++ )
++
++__define_cpu_migrate_event(begin);
++__define_cpu_migrate_event(finish);
++__define_cpu_migrate_event(current);
++
++#undef __define_cpu_migrate
++#undef __cpu_migrate_proto
++#undef __cpu_migrate_args
++
++/* This file can get included multiple times, TRACE_HEADER_MULTI_READ at top */
++#ifndef _PWR_CPU_MIGRATE_EVENT_AVOID_DOUBLE_DEFINING
++#define _PWR_CPU_MIGRATE_EVENT_AVOID_DOUBLE_DEFINING
++
++/*
++ * Set from_phys_cpu and to_phys_cpu to CPU_MIGRATE_ALL_CPUS to indicate
++ * a whole-cluster migration:
++ */
++#define CPU_MIGRATE_ALL_CPUS 0x80000000U
++#endif
++
++#endif /* _TRACE_POWER_CPU_MIGRATE_H */
++
++/* This part must be outside protection */
++#undef TRACE_INCLUDE_FILE
++#define TRACE_INCLUDE_FILE power_cpu_migrate
++#include <trace/define_trace.h>
+diff -Nur linux-3.10.30.orig/include/trace/events/sched.h linux-linaro-stable-mx6/include/trace/events/sched.h
+--- linux-3.10.30.orig/include/trace/events/sched.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/trace/events/sched.h 2014-05-15 20:34:15.882142701 +0200
+@@ -430,6 +430,280 @@
+ __entry->oldprio, __entry->newprio)
+ );
+
++/*
++ * Tracepoint for showing tracked load contribution.
++ */
++TRACE_EVENT(sched_task_load_contrib,
++
++ TP_PROTO(struct task_struct *tsk, unsigned long load_contrib),
++
++ TP_ARGS(tsk, load_contrib),
++
++ TP_STRUCT__entry(
++ __array(char, comm, TASK_COMM_LEN)
++ __field(pid_t, pid)
++ __field(unsigned long, load_contrib)
++ ),
++
++ TP_fast_assign(
++ memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN);
++ __entry->pid = tsk->pid;
++ __entry->load_contrib = load_contrib;
++ ),
++
++ TP_printk("comm=%s pid=%d load_contrib=%lu",
++ __entry->comm, __entry->pid,
++ __entry->load_contrib)
++);
++
++/*
++ * Tracepoint for showing tracked task runnable ratio [0..1023].
++ */
++TRACE_EVENT(sched_task_runnable_ratio,
++
++ TP_PROTO(struct task_struct *tsk, unsigned long ratio),
++
++ TP_ARGS(tsk, ratio),
++
++ TP_STRUCT__entry(
++ __array(char, comm, TASK_COMM_LEN)
++ __field(pid_t, pid)
++ __field(unsigned long, ratio)
++ ),
++
++ TP_fast_assign(
++ memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN);
++ __entry->pid = tsk->pid;
++ __entry->ratio = ratio;
++ ),
++
++ TP_printk("comm=%s pid=%d ratio=%lu",
++ __entry->comm, __entry->pid,
++ __entry->ratio)
++);
++
++/*
++ * Tracepoint for showing tracked rq runnable ratio [0..1023].
++ */
++TRACE_EVENT(sched_rq_runnable_ratio,
++
++ TP_PROTO(int cpu, unsigned long ratio),
++
++ TP_ARGS(cpu, ratio),
++
++ TP_STRUCT__entry(
++ __field(int, cpu)
++ __field(unsigned long, ratio)
++ ),
++
++ TP_fast_assign(
++ __entry->cpu = cpu;
++ __entry->ratio = ratio;
++ ),
++
++ TP_printk("cpu=%d ratio=%lu",
++ __entry->cpu,
++ __entry->ratio)
++);
++
++/*
++ * Tracepoint for showing tracked rq runnable load.
++ */
++TRACE_EVENT(sched_rq_runnable_load,
++
++ TP_PROTO(int cpu, u64 load),
++
++ TP_ARGS(cpu, load),
++
++ TP_STRUCT__entry(
++ __field(int, cpu)
++ __field(u64, load)
++ ),
++
++ TP_fast_assign(
++ __entry->cpu = cpu;
++ __entry->load = load;
++ ),
++
++ TP_printk("cpu=%d load=%llu",
++ __entry->cpu,
++ __entry->load)
++);
++
++TRACE_EVENT(sched_rq_nr_running,
++
++ TP_PROTO(int cpu, unsigned int nr_running, int nr_iowait),
++
++ TP_ARGS(cpu, nr_running, nr_iowait),
++
++ TP_STRUCT__entry(
++ __field(int, cpu)
++ __field(unsigned int, nr_running)
++ __field(int, nr_iowait)
++ ),
++
++ TP_fast_assign(
++ __entry->cpu = cpu;
++ __entry->nr_running = nr_running;
++ __entry->nr_iowait = nr_iowait;
++ ),
++
++ TP_printk("cpu=%d nr_running=%u nr_iowait=%d",
++ __entry->cpu,
++ __entry->nr_running, __entry->nr_iowait)
++);
++
++/*
++ * Tracepoint for showing tracked task cpu usage ratio [0..1023].
++ */
++TRACE_EVENT(sched_task_usage_ratio,
++
++ TP_PROTO(struct task_struct *tsk, unsigned long ratio),
++
++ TP_ARGS(tsk, ratio),
++
++ TP_STRUCT__entry(
++ __array(char, comm, TASK_COMM_LEN)
++ __field(pid_t, pid)
++ __field(unsigned long, ratio)
++ ),
++
++ TP_fast_assign(
++ memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN);
++ __entry->pid = tsk->pid;
++ __entry->ratio = ratio;
++ ),
++
++ TP_printk("comm=%s pid=%d ratio=%lu",
++ __entry->comm, __entry->pid,
++ __entry->ratio)
++);
++
++/*
++ * Tracepoint for HMP (CONFIG_SCHED_HMP) task migrations,
++ * marking the forced transition of runnable or running tasks.
++ */
++TRACE_EVENT(sched_hmp_migrate_force_running,
++
++ TP_PROTO(struct task_struct *tsk, int running),
++
++ TP_ARGS(tsk, running),
++
++ TP_STRUCT__entry(
++ __array(char, comm, TASK_COMM_LEN)
++ __field(int, running)
++ ),
++
++ TP_fast_assign(
++ memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN);
++ __entry->running = running;
++ ),
++
++ TP_printk("running=%d comm=%s",
++ __entry->running, __entry->comm)
++);
++
++/*
++ * Tracepoint for HMP (CONFIG_SCHED_HMP) task migrations,
++ * marking the forced transition of runnable or running
++ * tasks when a task is about to go idle.
++ */
++TRACE_EVENT(sched_hmp_migrate_idle_running,
++
++ TP_PROTO(struct task_struct *tsk, int running),
++
++ TP_ARGS(tsk, running),
++
++ TP_STRUCT__entry(
++ __array(char, comm, TASK_COMM_LEN)
++ __field(int, running)
++ ),
++
++ TP_fast_assign(
++ memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN);
++ __entry->running = running;
++ ),
++
++ TP_printk("running=%d comm=%s",
++ __entry->running, __entry->comm)
++);
++
++/*
++ * Tracepoint for HMP (CONFIG_SCHED_HMP) task migrations.
++ */
++#define HMP_MIGRATE_WAKEUP 0
++#define HMP_MIGRATE_FORCE 1
++#define HMP_MIGRATE_OFFLOAD 2
++#define HMP_MIGRATE_IDLE_PULL 3
++TRACE_EVENT(sched_hmp_migrate,
++
++ TP_PROTO(struct task_struct *tsk, int dest, int force),
++
++ TP_ARGS(tsk, dest, force),
++
++ TP_STRUCT__entry(
++ __array(char, comm, TASK_COMM_LEN)
++ __field(pid_t, pid)
++ __field(int, dest)
++ __field(int, force)
++ ),
++
++ TP_fast_assign(
++ memcpy(__entry->comm, tsk->comm, TASK_COMM_LEN);
++ __entry->pid = tsk->pid;
++ __entry->dest = dest;
++ __entry->force = force;
++ ),
++
++ TP_printk("comm=%s pid=%d dest=%d force=%d",
++ __entry->comm, __entry->pid,
++ __entry->dest, __entry->force)
++);
++
++TRACE_EVENT(sched_hmp_offload_abort,
++
++ TP_PROTO(int cpu, int data, char *label),
++
++ TP_ARGS(cpu,data,label),
++
++ TP_STRUCT__entry(
++ __array(char, label, 64)
++ __field(int, cpu)
++ __field(int, data)
++ ),
++
++ TP_fast_assign(
++ strncpy(__entry->label, label, 64);
++ __entry->cpu = cpu;
++ __entry->data = data;
++ ),
++
++ TP_printk("cpu=%d data=%d label=%63s",
++ __entry->cpu, __entry->data,
++ __entry->label)
++);
++
++TRACE_EVENT(sched_hmp_offload_succeed,
++
++ TP_PROTO(int cpu, int dest_cpu),
++
++ TP_ARGS(cpu,dest_cpu),
++
++ TP_STRUCT__entry(
++ __field(int, cpu)
++ __field(int, dest_cpu)
++ ),
++
++ TP_fast_assign(
++ __entry->cpu = cpu;
++ __entry->dest_cpu = dest_cpu;
++ ),
++
++ TP_printk("cpu=%d dest=%d",
++ __entry->cpu,
++ __entry->dest_cpu)
++);
++
+ #endif /* _TRACE_SCHED_H */
+
+ /* This part must be outside protection */
+diff -Nur linux-3.10.30.orig/include/trace/events/smp.h linux-linaro-stable-mx6/include/trace/events/smp.h
+--- linux-3.10.30.orig/include/trace/events/smp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/trace/events/smp.h 2014-05-15 20:34:15.882142701 +0200
+@@ -0,0 +1,90 @@
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM smp
++
++#if !defined(_TRACE_SMP_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _TRACE_SMP_H
++
++#include <linux/tracepoint.h>
++
++DECLARE_EVENT_CLASS(smp_call_class,
++
++ TP_PROTO(void * fnc),
++
++ TP_ARGS(fnc),
++
++ TP_STRUCT__entry(
++ __field( void *, func )
++ ),
++
++ TP_fast_assign(
++ __entry->func = fnc;
++ ),
++
++ TP_printk("func=%pf", __entry->func)
++);
++
++/**
++ * smp_call_func_entry - called in the generic smp-cross-call-handler
++ * immediately before calling the destination
++ * function
++ * @func: function pointer
++ *
++ * When used in combination with the smp_call_func_exit tracepoint
++ * we can determine the cross-call runtime.
++ */
++DEFINE_EVENT(smp_call_class, smp_call_func_entry,
++
++ TP_PROTO(void * fnc),
++
++ TP_ARGS(fnc)
++);
++
++/**
++ * smp_call_func_exit - called in the generic smp-cross-call-handler
++ * immediately after the destination function
++ * returns
++ * @func: function pointer
++ *
++ * When used in combination with the smp_call_entry tracepoint
++ * we can determine the cross-call runtime.
++ */
++DEFINE_EVENT(smp_call_class, smp_call_func_exit,
++
++ TP_PROTO(void * fnc),
++
++ TP_ARGS(fnc)
++);
++
++/**
++ * smp_call_func_send - called as destination function is set
++ * in the per-cpu storage
++ * @func: function pointer
++ * @dest: cpu to send to
++ *
++ * When used in combination with the smp_cross_call_entry tracepoint
++ * we can determine the call-to-run latency.
++ */
++TRACE_EVENT(smp_call_func_send,
++
++ TP_PROTO(void * func, int dest),
++
++ TP_ARGS(func, dest),
++
++ TP_STRUCT__entry(
++ __field( void * , func )
++ __field( int , dest )
++ ),
++
++ TP_fast_assign(
++ __entry->func = func;
++ __entry->dest = dest;
++ ),
++
++ TP_printk("dest=%d func=%pf", __entry->dest,
++ __entry->func)
++);
++
++#endif /* _TRACE_SMP_H */
++
++/* This part must be outside protection */
++#include <trace/define_trace.h>
+diff -Nur linux-3.10.30.orig/include/trace/events/spi.h linux-linaro-stable-mx6/include/trace/events/spi.h
+--- linux-3.10.30.orig/include/trace/events/spi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/trace/events/spi.h 2014-05-15 20:34:15.882142701 +0200
+@@ -0,0 +1,156 @@
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM spi
++
++#if !defined(_TRACE_SPI_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _TRACE_SPI_H
++
++#include <linux/ktime.h>
++#include <linux/tracepoint.h>
++
++DECLARE_EVENT_CLASS(spi_master,
++
++ TP_PROTO(struct spi_master *master),
++
++ TP_ARGS(master),
++
++ TP_STRUCT__entry(
++ __field( int, bus_num )
++ ),
++
++ TP_fast_assign(
++ __entry->bus_num = master->bus_num;
++ ),
++
++ TP_printk("spi%d", (int)__entry->bus_num)
++
++);
++
++DEFINE_EVENT(spi_master, spi_master_idle,
++
++ TP_PROTO(struct spi_master *master),
++
++ TP_ARGS(master)
++
++);
++
++DEFINE_EVENT(spi_master, spi_master_busy,
++
++ TP_PROTO(struct spi_master *master),
++
++ TP_ARGS(master)
++
++);
++
++DECLARE_EVENT_CLASS(spi_message,
++
++ TP_PROTO(struct spi_message *msg),
++
++ TP_ARGS(msg),
++
++ TP_STRUCT__entry(
++ __field( int, bus_num )
++ __field( int, chip_select )
++ __field( struct spi_message *, msg )
++ ),
++
++ TP_fast_assign(
++ __entry->bus_num = msg->spi->master->bus_num;
++ __entry->chip_select = msg->spi->chip_select;
++ __entry->msg = msg;
++ ),
++
++ TP_printk("spi%d.%d %p", (int)__entry->bus_num,
++ (int)__entry->chip_select,
++ (struct spi_message *)__entry->msg)
++);
++
++DEFINE_EVENT(spi_message, spi_message_submit,
++
++ TP_PROTO(struct spi_message *msg),
++
++ TP_ARGS(msg)
++
++);
++
++DEFINE_EVENT(spi_message, spi_message_start,
++
++ TP_PROTO(struct spi_message *msg),
++
++ TP_ARGS(msg)
++
++);
++
++TRACE_EVENT(spi_message_done,
++
++ TP_PROTO(struct spi_message *msg),
++
++ TP_ARGS(msg),
++
++ TP_STRUCT__entry(
++ __field( int, bus_num )
++ __field( int, chip_select )
++ __field( struct spi_message *, msg )
++ __field( unsigned, frame )
++ __field( unsigned, actual )
++ ),
++
++ TP_fast_assign(
++ __entry->bus_num = msg->spi->master->bus_num;
++ __entry->chip_select = msg->spi->chip_select;
++ __entry->msg = msg;
++ __entry->frame = msg->frame_length;
++ __entry->actual = msg->actual_length;
++ ),
++
++ TP_printk("spi%d.%d %p len=%u/%u", (int)__entry->bus_num,
++ (int)__entry->chip_select,
++ (struct spi_message *)__entry->msg,
++ (unsigned)__entry->actual, (unsigned)__entry->frame)
++);
++
++DECLARE_EVENT_CLASS(spi_transfer,
++
++ TP_PROTO(struct spi_message *msg, struct spi_transfer *xfer),
++
++ TP_ARGS(msg, xfer),
++
++ TP_STRUCT__entry(
++ __field( int, bus_num )
++ __field( int, chip_select )
++ __field( struct spi_transfer *, xfer )
++ __field( int, len )
++ ),
++
++ TP_fast_assign(
++ __entry->bus_num = msg->spi->master->bus_num;
++ __entry->chip_select = msg->spi->chip_select;
++ __entry->xfer = xfer;
++ __entry->len = xfer->len;
++ ),
++
++ TP_printk("spi%d.%d %p len=%d", (int)__entry->bus_num,
++ (int)__entry->chip_select,
++ (struct spi_message *)__entry->xfer,
++ (int)__entry->len)
++);
++
++DEFINE_EVENT(spi_transfer, spi_transfer_start,
++
++ TP_PROTO(struct spi_message *msg, struct spi_transfer *xfer),
++
++ TP_ARGS(msg, xfer)
++
++);
++
++DEFINE_EVENT(spi_transfer, spi_transfer_stop,
++
++ TP_PROTO(struct spi_message *msg, struct spi_transfer *xfer),
++
++ TP_ARGS(msg, xfer)
++
++);
++
++#endif /* _TRACE_POWER_H */
++
++/* This part must be outside protection */
++#include <trace/define_trace.h>
+diff -Nur linux-3.10.30.orig/include/uapi/linux/ipu.h linux-linaro-stable-mx6/include/uapi/linux/ipu.h
+--- linux-3.10.30.orig/include/uapi/linux/ipu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/ipu.h 2014-05-15 20:34:16.118144400 +0200
+@@ -0,0 +1,282 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @defgroup IPU MXC Image Processing Unit (IPU) Driver
++ */
++/*!
++ * @file uapi/linux/ipu.h
++ *
++ * @brief This file contains the IPU driver API declarations.
++ *
++ * @ingroup IPU
++ */
++
++#ifndef __ASM_ARCH_IPU_H__
++#define __ASM_ARCH_IPU_H__
++
++#include <linux/types.h>
++#include <linux/videodev2.h>
++
++#ifndef __KERNEL__
++#ifndef __cplusplus
++typedef unsigned char bool;
++#endif
++#define irqreturn_t int
++#define dma_addr_t int
++#define uint32_t unsigned int
++#define uint16_t unsigned short
++#define uint8_t unsigned char
++#define u32 unsigned int
++#define u8 unsigned char
++#define __u32 u32
++#endif
++
++/*!
++ * Enumeration of IPU rotation modes
++ */
++typedef enum {
++ /* Note the enum values correspond to BAM value */
++ IPU_ROTATE_NONE = 0,
++ IPU_ROTATE_VERT_FLIP = 1,
++ IPU_ROTATE_HORIZ_FLIP = 2,
++ IPU_ROTATE_180 = 3,
++ IPU_ROTATE_90_RIGHT = 4,
++ IPU_ROTATE_90_RIGHT_VFLIP = 5,
++ IPU_ROTATE_90_RIGHT_HFLIP = 6,
++ IPU_ROTATE_90_LEFT = 7,
++} ipu_rotate_mode_t;
++
++/*!
++ * Enumeration of VDI MOTION select
++ */
++typedef enum {
++ MED_MOTION = 0,
++ LOW_MOTION = 1,
++ HIGH_MOTION = 2,
++} ipu_motion_sel;
++
++/*!
++ * Enumeration of DI ports for ADC.
++ */
++typedef enum {
++ DISP0,
++ DISP1,
++ DISP2,
++ DISP3
++} display_port_t;
++
++/* IPU Pixel format definitions */
++/* Four-character-code (FOURCC) */
++#define fourcc(a, b, c, d)\
++ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
++
++/*!
++ * @name IPU Pixel Formats
++ *
++ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
++ * the same used by V4L2 API.
++ */
++
++/*! @{ */
++/*! @name Generic or Raw Data Formats */
++/*! @{ */
++#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_GENERIC_16 fourcc('I', 'P', 'U', '2') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') /*!< IPU Generic Data */
++/*! @} */
++/*! @name RGB Formats */
++/*! @{ */
++#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */
++#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */
++#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */
++#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */
++#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */
++#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */
++#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */
++#define IPU_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */
++#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */
++#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */
++#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */
++#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */
++#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */
++/*! @} */
++/*! @name YUV Interleaved Formats */
++/*! @{ */
++#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */
++#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */
++#define IPU_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */
++#define IPU_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */
++#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */
++#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */
++#define IPU_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */
++/* two planes -- one Y, one Cb + Cr interleaved */
++#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
++/* two planes -- 12 tiled Y/CbCr 4:2:0 */
++#define IPU_PIX_FMT_TILED_NV12 fourcc('T', 'N', 'V', 'P')
++#define IPU_PIX_FMT_TILED_NV12F fourcc('T', 'N', 'V', 'F')
++
++/*! @} */
++/*! @name YUV Planar Formats */
++/*! @{ */
++#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */
++#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */
++#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */
++#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */
++#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */
++#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */
++#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */
++#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */
++/* non-interleaved 4:4:4 */
++#define IPU_PIX_FMT_YUV444P fourcc('4', '4', '4', 'P') /*!< 24 YUV 4:4:4 */
++/*! @} */
++#define IPU_PIX_FMT_TILED_NV12_MBALIGN (16)
++#define TILED_NV12_FRAME_SIZE(w, h) \
++ (ALIGN((w) * (h), SZ_4K) + ALIGN((w) * (h) / 2, SZ_4K))
++/* IPU device */
++typedef enum {
++ RGB_CS,
++ YUV_CS,
++ NULL_CS
++} cs_t;
++
++struct ipu_pos {
++ u32 x;
++ u32 y;
++};
++
++struct ipu_crop {
++ struct ipu_pos pos;
++ u32 w;
++ u32 h;
++};
++
++struct ipu_deinterlace {
++ bool enable;
++ u8 motion; /*see ipu_motion_sel*/
++#define IPU_DEINTERLACE_FIELD_TOP 0
++#define IPU_DEINTERLACE_FIELD_BOTTOM 1
++#define IPU_DEINTERLACE_FIELD_MASK \
++ (IPU_DEINTERLACE_FIELD_TOP | IPU_DEINTERLACE_FIELD_BOTTOM)
++ /* deinterlace frame rate double flags */
++#define IPU_DEINTERLACE_RATE_EN 0x80
++#define IPU_DEINTERLACE_RATE_FRAME1 0x40
++#define IPU_DEINTERLACE_RATE_MASK \
++ (IPU_DEINTERLACE_RATE_EN | IPU_DEINTERLACE_RATE_FRAME1)
++#define IPU_DEINTERLACE_MAX_FRAME 2
++ u8 field_fmt;
++};
++
++struct ipu_input {
++ u32 width;
++ u32 height;
++ u32 format;
++ struct ipu_crop crop;
++ dma_addr_t paddr;
++
++ struct ipu_deinterlace deinterlace;
++ dma_addr_t paddr_n; /*valid when deinterlace enable*/
++};
++
++struct ipu_alpha {
++#define IPU_ALPHA_MODE_GLOBAL 0
++#define IPU_ALPHA_MODE_LOCAL 1
++ u8 mode;
++ u8 gvalue; /* 0~255 */
++ dma_addr_t loc_alp_paddr;
++};
++
++struct ipu_colorkey {
++ bool enable;
++ u32 value; /* RGB 24bit */
++};
++
++struct ipu_overlay {
++ u32 width;
++ u32 height;
++ u32 format;
++ struct ipu_crop crop;
++ struct ipu_alpha alpha;
++ struct ipu_colorkey colorkey;
++ dma_addr_t paddr;
++};
++
++struct ipu_output {
++ u32 width;
++ u32 height;
++ u32 format;
++ u8 rotate;
++ struct ipu_crop crop;
++ dma_addr_t paddr;
++};
++
++struct ipu_task {
++ struct ipu_input input;
++ struct ipu_output output;
++
++ bool overlay_en;
++ struct ipu_overlay overlay;
++
++#define IPU_TASK_PRIORITY_NORMAL 0
++#define IPU_TASK_PRIORITY_HIGH 1
++ u8 priority;
++
++#define IPU_TASK_ID_ANY 0
++#define IPU_TASK_ID_VF 1
++#define IPU_TASK_ID_PP 2
++#define IPU_TASK_ID_MAX 3
++ u8 task_id;
++
++ int timeout;
++};
++
++enum {
++ IPU_CHECK_OK = 0,
++ IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN = 0x1,
++ IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN = 0x2,
++ IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN = 0x4,
++ IPU_CHECK_ERR_MIN,
++ IPU_CHECK_ERR_INPUT_CROP,
++ IPU_CHECK_ERR_OUTPUT_CROP,
++ IPU_CHECK_ERR_OVERLAY_CROP,
++ IPU_CHECK_ERR_INPUT_OVER_LIMIT,
++ IPU_CHECK_ERR_OV_OUT_NO_FIT,
++ IPU_CHECK_ERR_OVERLAY_WITH_VDI,
++ IPU_CHECK_ERR_PROC_NO_NEED,
++ IPU_CHECK_ERR_SPLIT_INPUTW_OVER,
++ IPU_CHECK_ERR_SPLIT_INPUTH_OVER,
++ IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER,
++ IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER,
++ IPU_CHECK_ERR_SPLIT_WITH_ROT,
++ IPU_CHECK_ERR_NOT_SUPPORT,
++ IPU_CHECK_ERR_NOT16ALIGN,
++ IPU_CHECK_ERR_W_DOWNSIZE_OVER,
++ IPU_CHECK_ERR_H_DOWNSIZE_OVER,
++};
++
++/* IOCTL commands */
++#define IPU_CHECK_TASK _IOWR('I', 0x1, struct ipu_task)
++#define IPU_QUEUE_TASK _IOW('I', 0x2, struct ipu_task)
++#define IPU_ALLOC _IOWR('I', 0x3, int)
++#define IPU_FREE _IOW('I', 0x4, int)
++
++#endif
+diff -Nur linux-3.10.30.orig/include/uapi/linux/isl29023.h linux-linaro-stable-mx6/include/uapi/linux/isl29023.h
+--- linux-3.10.30.orig/include/uapi/linux/isl29023.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/isl29023.h 2014-05-15 20:34:16.150144631 +0200
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __UAPI_LINUX_ISL29023_H__
++#define __UAPI_LINUX_ISL29023_H__
++
++#include <linux/types.h>
++
++#define ISL29023_PD_MODE 0x0
++#define ISL29023_ALS_ONCE_MODE 0x1
++#define ISL29023_IR_ONCE_MODE 0x2
++#define ISL29023_ALS_CONT_MODE 0x5
++#define ISL29023_IR_CONT_MODE 0x6
++
++#define ISL29023_INT_PERSISTS_1 0x0
++#define ISL29023_INT_PERSISTS_4 0x1
++#define ISL29023_INT_PERSISTS_8 0x2
++#define ISL29023_INT_PERSISTS_16 0x3
++
++#define ISL29023_RES_16 0x0
++#define ISL29023_RES_12 0x1
++#define ISL29023_RES_8 0x2
++#define ISL29023_RES_4 0x3
++
++#define ISL29023_RANGE_1K 0x0
++#define ISL29023_RANGE_4K 0x1
++#define ISL29023_RANGE_16K 0x2
++#define ISL29023_RANGE_64K 0x3
++
++#endif
+diff -Nur linux-3.10.30.orig/include/uapi/linux/Kbuild linux-linaro-stable-mx6/include/uapi/linux/Kbuild
+--- linux-3.10.30.orig/include/uapi/linux/Kbuild 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/Kbuild 2014-05-15 20:34:15.974143363 +0200
+@@ -225,6 +225,7 @@
+ header-y += kvm_para.h
+ endif
+
++header-y += ipu.h
+ header-y += l2tp.h
+ header-y += limits.h
+ header-y += llc.h
+@@ -249,6 +250,9 @@
+ header-y += msdos_fs.h
+ header-y += msg.h
+ header-y += mtio.h
++header-y += mxcfb.h
++header-y += mxc_asrc.h
++header-y += mxc_v4l2.h
+ header-y += n_r3964.h
+ header-y += nbd.h
+ header-y += ncp.h
+@@ -313,6 +317,7 @@
+ header-y += prctl.h
+ header-y += ptp_clock.h
+ header-y += ptrace.h
++header-y += pxp_dma.h
+ header-y += qnx4_fs.h
+ header-y += qnxtypes.h
+ header-y += quota.h
+diff -Nur linux-3.10.30.orig/include/uapi/linux/mxc_asrc.h linux-linaro-stable-mx6/include/uapi/linux/mxc_asrc.h
+--- linux-3.10.30.orig/include/uapi/linux/mxc_asrc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/mxc_asrc.h 2014-05-15 20:34:16.154144659 +0200
+@@ -0,0 +1,143 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ *
++ * @file mxc_asrc.h
++ *
++ * @brief i.MX Asynchronous Sample Rate Converter
++ *
++ * @ingroup Audio
++ */
++
++#ifndef __MXC_ASRC_UAPI_H__
++#define __MXC_ASRC_UAPI_H__
++
++#define ASRC_IOC_MAGIC 'C'
++
++#define ASRC_REQ_PAIR _IOWR(ASRC_IOC_MAGIC, 0, struct asrc_req)
++#define ASRC_CONFIG_PAIR _IOWR(ASRC_IOC_MAGIC, 1, struct asrc_config)
++#define ASRC_RELEASE_PAIR _IOW(ASRC_IOC_MAGIC, 2, enum asrc_pair_index)
++#define ASRC_CONVERT _IOW(ASRC_IOC_MAGIC, 3, struct asrc_convert_buffer)
++#define ASRC_START_CONV _IOW(ASRC_IOC_MAGIC, 4, enum asrc_pair_index)
++#define ASRC_STOP_CONV _IOW(ASRC_IOC_MAGIC, 5, enum asrc_pair_index)
++#define ASRC_STATUS _IOW(ASRC_IOC_MAGIC, 6, struct asrc_status_flags)
++#define ASRC_FLUSH _IOW(ASRC_IOC_MAGIC, 7, enum asrc_pair_index)
++
++enum asrc_pair_index {
++ ASRC_UNVALID_PAIR = -1,
++ ASRC_PAIR_A = 0,
++ ASRC_PAIR_B = 1,
++ ASRC_PAIR_C = 2,
++};
++
++#define ASRC_PAIR_MAX_NUM (ASRC_PAIR_C + 1)
++
++enum asrc_inclk {
++ INCLK_NONE = 0x03,
++ INCLK_ESAI_RX = 0x00,
++ INCLK_SSI1_RX = 0x01,
++ INCLK_SSI2_RX = 0x02,
++ INCLK_SSI3_RX = 0x07,
++ INCLK_SPDIF_RX = 0x04,
++ INCLK_MLB_CLK = 0x05,
++ INCLK_PAD = 0x06,
++ INCLK_ESAI_TX = 0x08,
++ INCLK_SSI1_TX = 0x09,
++ INCLK_SSI2_TX = 0x0a,
++ INCLK_SSI3_TX = 0x0b,
++ INCLK_SPDIF_TX = 0x0c,
++ INCLK_ASRCK1_CLK = 0x0f,
++};
++
++enum asrc_outclk {
++ OUTCLK_NONE = 0x03,
++ OUTCLK_ESAI_TX = 0x00,
++ OUTCLK_SSI1_TX = 0x01,
++ OUTCLK_SSI2_TX = 0x02,
++ OUTCLK_SSI3_TX = 0x07,
++ OUTCLK_SPDIF_TX = 0x04,
++ OUTCLK_MLB_CLK = 0x05,
++ OUTCLK_PAD = 0x06,
++ OUTCLK_ESAI_RX = 0x08,
++ OUTCLK_SSI1_RX = 0x09,
++ OUTCLK_SSI2_RX = 0x0a,
++ OUTCLK_SSI3_RX = 0x0b,
++ OUTCLK_SPDIF_RX = 0x0c,
++ OUTCLK_ASRCK1_CLK = 0x0f,
++};
++
++enum asrc_word_width {
++ ASRC_WIDTH_24_BIT = 0,
++ ASRC_WIDTH_16_BIT = 1,
++ ASRC_WIDTH_8_BIT = 2,
++};
++
++struct asrc_config {
++ enum asrc_pair_index pair;
++ unsigned int channel_num;
++ unsigned int buffer_num;
++ unsigned int dma_buffer_size;
++ unsigned int input_sample_rate;
++ unsigned int output_sample_rate;
++ enum asrc_word_width input_word_width;
++ enum asrc_word_width output_word_width;
++ enum asrc_inclk inclk;
++ enum asrc_outclk outclk;
++};
++
++struct asrc_pair {
++ unsigned int start_channel;
++ unsigned int chn_num;
++ unsigned int chn_max;
++ unsigned int active;
++ unsigned int overload_error;
++};
++
++struct asrc_req {
++ unsigned int chn_num;
++ enum asrc_pair_index index;
++};
++
++struct asrc_querybuf {
++ unsigned int buffer_index;
++ unsigned int input_length;
++ unsigned int output_length;
++ unsigned long input_offset;
++ unsigned long output_offset;
++};
++
++struct asrc_convert_buffer {
++ void *input_buffer_vaddr;
++ void *output_buffer_vaddr;
++ unsigned int input_buffer_length;
++ unsigned int output_buffer_length;
++};
++
++struct asrc_buffer {
++ unsigned int index;
++ unsigned int length;
++ unsigned int output_last_length;
++ int buf_valid;
++};
++
++struct asrc_status_flags {
++ enum asrc_pair_index index;
++ unsigned int overload_error;
++};
++
++#define ASRC_BUF_NA -35 /* ASRC DQ's buffer is NOT available */
++#define ASRC_BUF_AV 35 /* ASRC DQ's buffer is available */
++enum asrc_error_status {
++ ASRC_TASK_Q_OVERLOAD = 0x01,
++ ASRC_OUTPUT_TASK_OVERLOAD = 0x02,
++ ASRC_INPUT_TASK_OVERLOAD = 0x04,
++ ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
++ ASRC_INPUT_BUFFER_UNDERRUN = 0x10,
++};
++#endif/* __MXC_ASRC_UAPI_H__ */
+diff -Nur linux-3.10.30.orig/include/uapi/linux/mxcfb.h linux-linaro-stable-mx6/include/uapi/linux/mxcfb.h
+--- linux-3.10.30.orig/include/uapi/linux/mxcfb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/mxcfb.h 2014-05-15 20:34:16.154144659 +0200
+@@ -0,0 +1,174 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*
++ * @file uapi/linux/mxcfb.h
++ *
++ * @brief Global header file for the MXC frame buffer
++ *
++ * @ingroup Framebuffer
++ */
++#ifndef __ASM_ARCH_MXCFB_H__
++#define __ASM_ARCH_MXCFB_H__
++
++#include <linux/fb.h>
++
++#define FB_SYNC_OE_LOW_ACT 0x80000000
++#define FB_SYNC_CLK_LAT_FALL 0x40000000
++#define FB_SYNC_DATA_INVERT 0x20000000
++#define FB_SYNC_CLK_IDLE_EN 0x10000000
++#define FB_SYNC_SHARP_MODE 0x08000000
++#define FB_SYNC_SWAP_RGB 0x04000000
++#define FB_ACCEL_TRIPLE_FLAG 0x00000000
++#define FB_ACCEL_DOUBLE_FLAG 0x00000001
++
++struct mxcfb_gbl_alpha {
++ int enable;
++ int alpha;
++};
++
++struct mxcfb_loc_alpha {
++ int enable;
++ int alpha_in_pixel;
++ unsigned long alpha_phy_addr0;
++ unsigned long alpha_phy_addr1;
++};
++
++struct mxcfb_color_key {
++ int enable;
++ __u32 color_key;
++};
++
++struct mxcfb_pos {
++ __u16 x;
++ __u16 y;
++};
++
++struct mxcfb_gamma {
++ int enable;
++ int constk[16];
++ int slopek[16];
++};
++
++struct mxcfb_rect {
++ __u32 top;
++ __u32 left;
++ __u32 width;
++ __u32 height;
++};
++
++#define GRAYSCALE_8BIT 0x1
++#define GRAYSCALE_8BIT_INVERTED 0x2
++#define GRAYSCALE_4BIT 0x3
++#define GRAYSCALE_4BIT_INVERTED 0x4
++
++#define AUTO_UPDATE_MODE_REGION_MODE 0
++#define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1
++
++#define UPDATE_SCHEME_SNAPSHOT 0
++#define UPDATE_SCHEME_QUEUE 1
++#define UPDATE_SCHEME_QUEUE_AND_MERGE 2
++
++#define UPDATE_MODE_PARTIAL 0x0
++#define UPDATE_MODE_FULL 0x1
++
++#define WAVEFORM_MODE_AUTO 257
++
++#define TEMP_USE_AMBIENT 0x1000
++
++#define EPDC_FLAG_ENABLE_INVERSION 0x01
++#define EPDC_FLAG_FORCE_MONOCHROME 0x02
++#define EPDC_FLAG_USE_CMAP 0x04
++#define EPDC_FLAG_USE_ALT_BUFFER 0x100
++#define EPDC_FLAG_TEST_COLLISION 0x200
++#define EPDC_FLAG_GROUP_UPDATE 0x400
++#define EPDC_FLAG_USE_DITHERING_Y1 0x2000
++#define EPDC_FLAG_USE_DITHERING_Y4 0x4000
++
++#define FB_POWERDOWN_DISABLE -1
++
++struct mxcfb_alt_buffer_data {
++ __u32 phys_addr;
++ __u32 width; /* width of entire buffer */
++ __u32 height; /* height of entire buffer */
++ struct mxcfb_rect alt_update_region; /* region within buffer to update */
++};
++
++struct mxcfb_update_data {
++ struct mxcfb_rect update_region;
++ __u32 waveform_mode;
++ __u32 update_mode;
++ __u32 update_marker;
++ int temp;
++ unsigned int flags;
++ struct mxcfb_alt_buffer_data alt_buffer_data;
++};
++
++struct mxcfb_update_marker_data {
++ __u32 update_marker;
++ __u32 collision_test;
++};
++
++/*
++ * Structure used to define waveform modes for driver
++ * Needed for driver to perform auto-waveform selection
++ */
++struct mxcfb_waveform_modes {
++ int mode_init;
++ int mode_du;
++ int mode_gc4;
++ int mode_gc8;
++ int mode_gc16;
++ int mode_gc32;
++};
++
++/*
++ * Structure used to define a 5*3 matrix of parameters for
++ * setting IPU DP CSC module related to this framebuffer.
++ */
++struct mxcfb_csc_matrix {
++ int param[5][3];
++};
++
++#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t)
++#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha)
++#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key)
++#define MXCFB_SET_OVERLAY_POS _IOWR('F', 0x24, struct mxcfb_pos)
++#define MXCFB_GET_FB_IPU_CHAN _IOR('F', 0x25, u_int32_t)
++#define MXCFB_SET_LOC_ALPHA _IOWR('F', 0x26, struct mxcfb_loc_alpha)
++#define MXCFB_SET_LOC_ALP_BUF _IOW('F', 0x27, unsigned long)
++#define MXCFB_SET_GAMMA _IOW('F', 0x28, struct mxcfb_gamma)
++#define MXCFB_GET_FB_IPU_DI _IOR('F', 0x29, u_int32_t)
++#define MXCFB_GET_DIFMT _IOR('F', 0x2A, u_int32_t)
++#define MXCFB_GET_FB_BLANK _IOR('F', 0x2B, u_int32_t)
++#define MXCFB_SET_DIFMT _IOW('F', 0x2C, u_int32_t)
++#define MXCFB_CSC_UPDATE _IOW('F', 0x2D, struct mxcfb_csc_matrix)
++
++/* IOCTLs for E-ink panel updates */
++#define MXCFB_SET_WAVEFORM_MODES _IOW('F', 0x2B, struct mxcfb_waveform_modes)
++#define MXCFB_SET_TEMPERATURE _IOW('F', 0x2C, int32_t)
++#define MXCFB_SET_AUTO_UPDATE_MODE _IOW('F', 0x2D, __u32)
++#define MXCFB_SEND_UPDATE _IOW('F', 0x2E, struct mxcfb_update_data)
++#define MXCFB_WAIT_FOR_UPDATE_COMPLETE _IOWR('F', 0x2F, struct mxcfb_update_marker_data)
++#define MXCFB_SET_PWRDOWN_DELAY _IOW('F', 0x30, int32_t)
++#define MXCFB_GET_PWRDOWN_DELAY _IOR('F', 0x31, int32_t)
++#define MXCFB_SET_UPDATE_SCHEME _IOW('F', 0x32, __u32)
++#define MXCFB_GET_WORK_BUFFER _IOWR('F', 0x34, unsigned long)
++#endif
+diff -Nur linux-3.10.30.orig/include/uapi/linux/mxc_mlb.h linux-linaro-stable-mx6/include/uapi/linux/mxc_mlb.h
+--- linux-3.10.30.orig/include/uapi/linux/mxc_mlb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/mxc_mlb.h 2014-05-15 20:34:16.154144659 +0200
+@@ -0,0 +1,55 @@
++/*
++ * mxc_mlb.h
++ *
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef _MXC_MLB_UAPI_H
++#define _MXC_MLB_UAPI_H
++
++/* define IOCTL command */
++#define MLB_DBG_RUNTIME _IO('S', 0x09)
++#define MLB_SET_FPS _IOW('S', 0x10, unsigned int)
++#define MLB_GET_VER _IOR('S', 0x11, unsigned long)
++#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char)
++
++/*!
++ * set channel address for each logical channel
++ * the MSB 16bits is for tx channel, the left LSB is for rx channel
++ */
++#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int)
++#define MLB_CHAN_STARTUP _IO('S', 0x14)
++#define MLB_CHAN_SHUTDOWN _IO('S', 0x15)
++#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long)
++
++#define MLB_SET_ISOC_BLKSIZE_188 _IO('S', 0x17)
++#define MLB_SET_ISOC_BLKSIZE_196 _IO('S', 0x18)
++#define MLB_SET_SYNC_QUAD _IOW('S', 0x19, unsigned int)
++#define MLB_IRQ_ENABLE _IO('S', 0x20)
++#define MLB_IRQ_DISABLE _IO('S', 0x21)
++
++/*!
++ * MLB event define
++ */
++enum {
++ MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0,
++ MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1,
++ MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8,
++ MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9,
++ MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16,
++ MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17,
++ MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24,
++ MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25,
++};
++
++
++#endif /* _MXC_MLB_H */
+diff -Nur linux-3.10.30.orig/include/uapi/linux/mxc_v4l2.h linux-linaro-stable-mx6/include/uapi/linux/mxc_v4l2.h
+--- linux-3.10.30.orig/include/uapi/linux/mxc_v4l2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/mxc_v4l2.h 2014-05-15 20:34:16.154144659 +0200
+@@ -0,0 +1,56 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file uapi/linux/mxc_v4l2.h
++ *
++ * @brief MXC V4L2 private header file
++ *
++ * @ingroup MXC V4L2
++ */
++
++#ifndef __ASM_ARCH_MXC_V4L2_H__
++#define __ASM_ARCH_MXC_V4L2_H__
++
++/*
++ * For IPUv1 and IPUv3, V4L2_CID_MXC_ROT means encoder ioctl ID.
++ * And V4L2_CID_MXC_VF_ROT is viewfinder ioctl ID only for IPUv1 and IPUv3.
++ */
++#define V4L2_CID_MXC_ROT (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_MXC_FLASH (V4L2_CID_PRIVATE_BASE + 1)
++#define V4L2_CID_MXC_VF_ROT (V4L2_CID_PRIVATE_BASE + 2)
++#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 3)
++#define V4L2_CID_MXC_SWITCH_CAM (V4L2_CID_PRIVATE_BASE + 6)
++
++#define V4L2_MXC_ROTATE_NONE 0
++#define V4L2_MXC_ROTATE_VERT_FLIP 1
++#define V4L2_MXC_ROTATE_HORIZ_FLIP 2
++#define V4L2_MXC_ROTATE_180 3
++#define V4L2_MXC_ROTATE_90_RIGHT 4
++#define V4L2_MXC_ROTATE_90_RIGHT_VFLIP 5
++#define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6
++#define V4L2_MXC_ROTATE_90_LEFT 7
++
++struct v4l2_mxc_offset {
++ uint32_t u_offset;
++ uint32_t v_offset;
++};
++
++#endif
+diff -Nur linux-3.10.30.orig/include/uapi/linux/pxp_dma.h linux-linaro-stable-mx6/include/uapi/linux/pxp_dma.h
+--- linux-3.10.30.orig/include/uapi/linux/pxp_dma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/pxp_dma.h 2014-05-15 20:34:16.354146099 +0200
+@@ -0,0 +1,189 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _UAPI_PXP_DMA
++#define _UAPI_PXP_DMA
++
++#include <linux/posix_types.h>
++
++#ifndef __KERNEL__
++typedef unsigned long dma_addr_t;
++typedef unsigned char bool;
++#endif
++#define __u32 unsigned int
++
++/* PXP Pixel format definitions */
++/* Four-character-code (FOURCC) */
++#define fourcc(a, b, c, d)\
++ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
++
++/*!
++ * @name PXP Pixel Formats
++ *
++ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
++ * the same used by V4L2 API.
++ */
++
++/*! @} */
++/*! @name RGB Formats */
++/*! @{ */
++#define PXP_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */
++#define PXP_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */
++#define PXP_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */
++#define PXP_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */
++#define PXP_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */
++#define PXP_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */
++#define PXP_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */
++#define PXP_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */
++#define PXP_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */
++#define PXP_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */
++#define PXP_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */
++#define PXP_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */
++/*! @} */
++/*! @name YUV Interleaved Formats */
++/*! @{ */
++#define PXP_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */
++#define PXP_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */
++#define PXP_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */
++#define PXP_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */
++/* two planes -- one Y, one Cb + Cr interleaved */
++#define PXP_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
++#define PXP_PIX_FMT_NV21 fourcc('N', 'V', '2', '1') /* 12 Y/CbCr 4:2:0 */
++#define PXP_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 12 Y/CbCr 4:2:2 */
++#define PXP_PIX_FMT_NV61 fourcc('N', 'V', '6', '1') /* 12 Y/CbCr 4:2:2 */
++/*! @} */
++/*! @name YUV Planar Formats */
++/*! @{ */
++#define PXP_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */
++#define PXP_PIX_FMT_GY04 fourcc('G', 'Y', '0', '4') /*!< 4 Greyscale */
++#define PXP_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */
++#define PXP_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */
++#define PXP_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */
++#define PXP_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */
++#define PXP_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */
++#define PXP_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */
++/*! @} */
++
++#define PXP_LUT_NONE 0x0
++#define PXP_LUT_INVERT 0x1
++#define PXP_LUT_BLACK_WHITE 0x2
++#define PXP_LUT_USE_CMAP 0x4
++
++#define NR_PXP_VIRT_CHANNEL 16
++
++#define PXP_IOC_MAGIC 'P'
++
++#define PXP_IOC_GET_CHAN _IOR(PXP_IOC_MAGIC, 0, struct pxp_mem_desc)
++#define PXP_IOC_PUT_CHAN _IOW(PXP_IOC_MAGIC, 1, struct pxp_mem_desc)
++#define PXP_IOC_CONFIG_CHAN _IOW(PXP_IOC_MAGIC, 2, struct pxp_mem_desc)
++#define PXP_IOC_START_CHAN _IOW(PXP_IOC_MAGIC, 3, struct pxp_mem_desc)
++#define PXP_IOC_GET_PHYMEM _IOWR(PXP_IOC_MAGIC, 4, struct pxp_mem_desc)
++#define PXP_IOC_PUT_PHYMEM _IOW(PXP_IOC_MAGIC, 5, struct pxp_mem_desc)
++#define PXP_IOC_WAIT4CMPLT _IOWR(PXP_IOC_MAGIC, 6, struct pxp_mem_desc)
++
++/* Order significant! */
++enum pxp_channel_status {
++ PXP_CHANNEL_FREE,
++ PXP_CHANNEL_INITIALIZED,
++ PXP_CHANNEL_READY,
++};
++
++struct rect {
++ int top; /* Upper left coordinate of rectangle */
++ int left;
++ int width;
++ int height;
++};
++
++struct pxp_layer_param {
++ unsigned short width;
++ unsigned short height;
++ unsigned short stride; /* aka pitch */
++ unsigned int pixel_fmt;
++
++ /* layers combining parameters
++ * (these are ignored for S0 and output
++ * layers, and only apply for OL layer)
++ */
++ bool combine_enable;
++ unsigned int color_key_enable;
++ unsigned int color_key;
++ bool global_alpha_enable;
++ /* global alpha is either override or multiply */
++ bool global_override;
++ unsigned char global_alpha;
++ bool alpha_invert;
++ bool local_alpha_enable;
++
++ dma_addr_t paddr;
++};
++
++struct pxp_proc_data {
++ /* S0 Transformation Info */
++ int scaling;
++ int hflip;
++ int vflip;
++ int rotate;
++ int rot_pos;
++ int yuv;
++
++ /* Source rectangle (srect) defines the sub-rectangle
++ * within S0 to undergo processing.
++ */
++ struct rect srect;
++ /* Dest rect (drect) defines how to position the processed
++ * source rectangle (after resizing) within the output frame,
++ * whose dimensions are defined in pxp->pxp_conf_state.out_param
++ */
++ struct rect drect;
++
++ /* Current S0 configuration */
++ unsigned int bgcolor;
++
++ /* Output overlay support */
++ int overlay_state;
++
++ /* LUT transformation on Y data */
++ int lut_transform;
++ unsigned char *lut_map; /* 256 entries */
++ bool lut_map_updated; /* Map recently changed */
++ bool combine_enable;
++};
++
++struct pxp_config_data {
++ struct pxp_layer_param s0_param;
++ struct pxp_layer_param ol_param[8];
++ struct pxp_layer_param out_param;
++ struct pxp_proc_data proc_data;
++ int layer_nr;
++
++ /* Users don't touch */
++ int chan_id;
++};
++
++struct pxp_mem_desc {
++ unsigned int size;
++ dma_addr_t phys_addr;
++ unsigned int cpu_addr; /* cpu address to free the dma mem */
++ unsigned int virt_uaddr; /* virtual user space address */
++};
++
++#endif
+diff -Nur linux-3.10.30.orig/include/uapi/linux/serial_core.h linux-linaro-stable-mx6/include/uapi/linux/serial_core.h
+--- linux-3.10.30.orig/include/uapi/linux/serial_core.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/linux/serial_core.h 2014-05-15 20:34:16.590147800 +0200
+@@ -226,4 +226,7 @@
+ /* Rocketport EXPRESS/INFINITY */
+ #define PORT_RP2 102
+
++/* Freescale lpuart */
++#define PORT_LPUART 103
++
+ #endif /* _UAPILINUX_SERIAL_CORE_H */
+diff -Nur linux-3.10.30.orig/include/uapi/mtd/mtd-abi.h linux-linaro-stable-mx6/include/uapi/mtd/mtd-abi.h
+--- linux-3.10.30.orig/include/uapi/mtd/mtd-abi.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/include/uapi/mtd/mtd-abi.h 2014-05-15 20:34:16.754148981 +0200
+@@ -94,10 +94,10 @@
+ #define MTD_RAM 1
+ #define MTD_ROM 2
+ #define MTD_NORFLASH 3
+-#define MTD_NANDFLASH 4
++#define MTD_NANDFLASH 4 /* SLC NAND */
+ #define MTD_DATAFLASH 6
+ #define MTD_UBIVOLUME 7
+-#define MTD_MLCNANDFLASH 8
++#define MTD_MLCNANDFLASH 8 /* MLC NAND (including TLC) */
+
+ #define MTD_WRITEABLE 0x400 /* Device is writeable */
+ #define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */
+@@ -275,4 +275,9 @@
+ MTD_FILE_MODE_RAW,
+ };
+
++static inline int mtd_type_is_nand_user(const struct mtd_info_user *mtd)
++{
++ return mtd->type == MTD_NANDFLASH || mtd->type == MTD_MLCNANDFLASH;
++}
++
+ #endif /* __MTD_ABI_H__ */
+diff -Nur linux-3.10.30.orig/include/video/mxc_edid.h linux-linaro-stable-mx6/include/video/mxc_edid.h
+--- linux-3.10.30.orig/include/video/mxc_edid.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/video/mxc_edid.h 2014-05-15 20:34:16.834149557 +0200
+@@ -0,0 +1,105 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxc_edid.h
++ *
++ * @brief MXC EDID tools
++ *
++ * @ingroup Framebuffer
++ */
++
++#ifndef MXC_EDID_H
++#define MXC_EDID_H
++
++#include <linux/fb.h>
++
++#define FB_VMODE_ASPECT_4_3 0x10
++#define FB_VMODE_ASPECT_16_9 0x20
++#define FB_VMODE_ASPECT_MASK (FB_VMODE_ASPECT_4_3 | FB_VMODE_ASPECT_16_9)
++
++enum cea_audio_coding_types {
++ AUDIO_CODING_TYPE_REF_STREAM_HEADER = 0,
++ AUDIO_CODING_TYPE_LPCM = 1,
++ AUDIO_CODING_TYPE_AC3 = 2,
++ AUDIO_CODING_TYPE_MPEG1 = 3,
++ AUDIO_CODING_TYPE_MP3 = 4,
++ AUDIO_CODING_TYPE_MPEG2 = 5,
++ AUDIO_CODING_TYPE_AACLC = 6,
++ AUDIO_CODING_TYPE_DTS = 7,
++ AUDIO_CODING_TYPE_ATRAC = 8,
++ AUDIO_CODING_TYPE_SACD = 9,
++ AUDIO_CODING_TYPE_EAC3 = 10,
++ AUDIO_CODING_TYPE_DTS_HD = 11,
++ AUDIO_CODING_TYPE_MLP = 12,
++ AUDIO_CODING_TYPE_DST = 13,
++ AUDIO_CODING_TYPE_WMAPRO = 14,
++ AUDIO_CODING_TYPE_RESERVED = 15,
++};
++
++struct mxc_hdmi_3d_format {
++ unsigned char vic_order_2d;
++ unsigned char struct_3d;
++ unsigned char detail_3d;
++ unsigned char reserved;
++};
++
++struct mxc_edid_cfg {
++ bool cea_underscan;
++ bool cea_basicaudio;
++ bool cea_ycbcr444;
++ bool cea_ycbcr422;
++ bool hdmi_cap;
++
++ /*VSD*/
++ bool vsd_support_ai;
++ bool vsd_dc_48bit;
++ bool vsd_dc_36bit;
++ bool vsd_dc_30bit;
++ bool vsd_dc_y444;
++ bool vsd_dvi_dual;
++
++ bool vsd_cnc0;
++ bool vsd_cnc1;
++ bool vsd_cnc2;
++ bool vsd_cnc3;
++
++ u8 vsd_video_latency;
++ u8 vsd_audio_latency;
++ u8 vsd_I_video_latency;
++ u8 vsd_I_audio_latency;
++
++ u8 physical_address[4];
++ u8 hdmi_vic[64];
++ struct mxc_hdmi_3d_format hdmi_3d_format[64];
++ u16 hdmi_3d_mask_all;
++ u16 hdmi_3d_struct_all;
++ u32 vsd_max_tmdsclk_rate;
++
++ u8 max_channels;
++ u8 sample_sizes;
++ u8 sample_rates;
++ u8 speaker_alloc;
++};
++
++int mxc_edid_var_to_vic(struct fb_var_screeninfo *var);
++int mxc_edid_mode_to_vic(const struct fb_videomode *mode);
++int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi);
++int mxc_edid_parse_ext_blk(unsigned char *edid, struct mxc_edid_cfg *cfg,
++ struct fb_monspecs *specs);
++#endif
+diff -Nur linux-3.10.30.orig/include/video/mxc_hdmi.h linux-linaro-stable-mx6/include/video/mxc_hdmi.h
+--- linux-3.10.30.orig/include/video/mxc_hdmi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/include/video/mxc_hdmi.h 2014-05-15 20:34:16.834149557 +0200
+@@ -0,0 +1,1026 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MXC_HDMI_H__
++#define __MXC_HDMI_H__
++
++/*
++ * Hdmi controller registers
++ */
++
++/* Identification Registers */
++#define HDMI_DESIGN_ID 0x0000
++#define HDMI_REVISION_ID 0x0001
++#define HDMI_PRODUCT_ID0 0x0002
++#define HDMI_PRODUCT_ID1 0x0003
++#define HDMI_CONFIG0_ID 0x0004
++#define HDMI_CONFIG1_ID 0x0005
++#define HDMI_CONFIG2_ID 0x0006
++#define HDMI_CONFIG3_ID 0x0007
++
++/* Interrupt Registers */
++#define HDMI_IH_FC_STAT0 0x0100
++#define HDMI_IH_FC_STAT1 0x0101
++#define HDMI_IH_FC_STAT2 0x0102
++#define HDMI_IH_AS_STAT0 0x0103
++#define HDMI_IH_PHY_STAT0 0x0104
++#define HDMI_IH_I2CM_STAT0 0x0105
++#define HDMI_IH_CEC_STAT0 0x0106
++#define HDMI_IH_VP_STAT0 0x0107
++#define HDMI_IH_I2CMPHY_STAT0 0x0108
++#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
++
++#define HDMI_IH_MUTE_FC_STAT0 0x0180
++#define HDMI_IH_MUTE_FC_STAT1 0x0181
++#define HDMI_IH_MUTE_FC_STAT2 0x0182
++#define HDMI_IH_MUTE_AS_STAT0 0x0183
++#define HDMI_IH_MUTE_PHY_STAT0 0x0184
++#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
++#define HDMI_IH_MUTE_CEC_STAT0 0x0186
++#define HDMI_IH_MUTE_VP_STAT0 0x0187
++#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
++#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
++#define HDMI_IH_MUTE 0x01FF
++
++/* Video Sample Registers */
++#define HDMI_TX_INVID0 0x0200
++#define HDMI_TX_INSTUFFING 0x0201
++#define HDMI_TX_GYDATA0 0x0202
++#define HDMI_TX_GYDATA1 0x0203
++#define HDMI_TX_RCRDATA0 0x0204
++#define HDMI_TX_RCRDATA1 0x0205
++#define HDMI_TX_BCBDATA0 0x0206
++#define HDMI_TX_BCBDATA1 0x0207
++
++/* Video Packetizer Registers */
++#define HDMI_VP_STATUS 0x0800
++#define HDMI_VP_PR_CD 0x0801
++#define HDMI_VP_STUFF 0x0802
++#define HDMI_VP_REMAP 0x0803
++#define HDMI_VP_CONF 0x0804
++#define HDMI_VP_STAT 0x0805
++#define HDMI_VP_INT 0x0806
++#define HDMI_VP_MASK 0x0807
++#define HDMI_VP_POL 0x0808
++
++/* Frame Composer Registers */
++#define HDMI_FC_INVIDCONF 0x1000
++#define HDMI_FC_INHACTV0 0x1001
++#define HDMI_FC_INHACTV1 0x1002
++#define HDMI_FC_INHBLANK0 0x1003
++#define HDMI_FC_INHBLANK1 0x1004
++#define HDMI_FC_INVACTV0 0x1005
++#define HDMI_FC_INVACTV1 0x1006
++#define HDMI_FC_INVBLANK 0x1007
++#define HDMI_FC_HSYNCINDELAY0 0x1008
++#define HDMI_FC_HSYNCINDELAY1 0x1009
++#define HDMI_FC_HSYNCINWIDTH0 0x100A
++#define HDMI_FC_HSYNCINWIDTH1 0x100B
++#define HDMI_FC_VSYNCINDELAY 0x100C
++#define HDMI_FC_VSYNCINWIDTH 0x100D
++#define HDMI_FC_INFREQ0 0x100E
++#define HDMI_FC_INFREQ1 0x100F
++#define HDMI_FC_INFREQ2 0x1010
++#define HDMI_FC_CTRLDUR 0x1011
++#define HDMI_FC_EXCTRLDUR 0x1012
++#define HDMI_FC_EXCTRLSPAC 0x1013
++#define HDMI_FC_CH0PREAM 0x1014
++#define HDMI_FC_CH1PREAM 0x1015
++#define HDMI_FC_CH2PREAM 0x1016
++#define HDMI_FC_AVICONF3 0x1017
++#define HDMI_FC_GCP 0x1018
++#define HDMI_FC_AVICONF0 0x1019
++#define HDMI_FC_AVICONF1 0x101A
++#define HDMI_FC_AVICONF2 0x101B
++#define HDMI_FC_AVIVID 0x101C
++#define HDMI_FC_AVIETB0 0x101D
++#define HDMI_FC_AVIETB1 0x101E
++#define HDMI_FC_AVISBB0 0x101F
++#define HDMI_FC_AVISBB1 0x1020
++#define HDMI_FC_AVIELB0 0x1021
++#define HDMI_FC_AVIELB1 0x1022
++#define HDMI_FC_AVISRB0 0x1023
++#define HDMI_FC_AVISRB1 0x1024
++#define HDMI_FC_AUDICONF0 0x1025
++#define HDMI_FC_AUDICONF1 0x1026
++#define HDMI_FC_AUDICONF2 0x1027
++#define HDMI_FC_AUDICONF3 0x1028
++#define HDMI_FC_VSDIEEEID0 0x1029
++#define HDMI_FC_VSDSIZE 0x102A
++#define HDMI_FC_VSDIEEEID1 0x1030
++#define HDMI_FC_VSDIEEEID2 0x1031
++#define HDMI_FC_VSDPAYLOAD0 0x1032
++#define HDMI_FC_VSDPAYLOAD1 0x1033
++#define HDMI_FC_VSDPAYLOAD2 0x1034
++#define HDMI_FC_VSDPAYLOAD3 0x1035
++#define HDMI_FC_VSDPAYLOAD4 0x1036
++#define HDMI_FC_VSDPAYLOAD5 0x1037
++#define HDMI_FC_VSDPAYLOAD6 0x1038
++#define HDMI_FC_VSDPAYLOAD7 0x1039
++#define HDMI_FC_VSDPAYLOAD8 0x103A
++#define HDMI_FC_VSDPAYLOAD9 0x103B
++#define HDMI_FC_VSDPAYLOAD10 0x103C
++#define HDMI_FC_VSDPAYLOAD11 0x103D
++#define HDMI_FC_VSDPAYLOAD12 0x103E
++#define HDMI_FC_VSDPAYLOAD13 0x103F
++#define HDMI_FC_VSDPAYLOAD14 0x1040
++#define HDMI_FC_VSDPAYLOAD15 0x1041
++#define HDMI_FC_VSDPAYLOAD16 0x1042
++#define HDMI_FC_VSDPAYLOAD17 0x1043
++#define HDMI_FC_VSDPAYLOAD18 0x1044
++#define HDMI_FC_VSDPAYLOAD19 0x1045
++#define HDMI_FC_VSDPAYLOAD20 0x1046
++#define HDMI_FC_VSDPAYLOAD21 0x1047
++#define HDMI_FC_VSDPAYLOAD22 0x1048
++#define HDMI_FC_VSDPAYLOAD23 0x1049
++#define HDMI_FC_SPDVENDORNAME0 0x104A
++#define HDMI_FC_SPDVENDORNAME1 0x104B
++#define HDMI_FC_SPDVENDORNAME2 0x104C
++#define HDMI_FC_SPDVENDORNAME3 0x104D
++#define HDMI_FC_SPDVENDORNAME4 0x104E
++#define HDMI_FC_SPDVENDORNAME5 0x104F
++#define HDMI_FC_SPDVENDORNAME6 0x1050
++#define HDMI_FC_SPDVENDORNAME7 0x1051
++#define HDMI_FC_SDPPRODUCTNAME0 0x1052
++#define HDMI_FC_SDPPRODUCTNAME1 0x1053
++#define HDMI_FC_SDPPRODUCTNAME2 0x1054
++#define HDMI_FC_SDPPRODUCTNAME3 0x1055
++#define HDMI_FC_SDPPRODUCTNAME4 0x1056
++#define HDMI_FC_SDPPRODUCTNAME5 0x1057
++#define HDMI_FC_SDPPRODUCTNAME6 0x1058
++#define HDMI_FC_SDPPRODUCTNAME7 0x1059
++#define HDMI_FC_SDPPRODUCTNAME8 0x105A
++#define HDMI_FC_SDPPRODUCTNAME9 0x105B
++#define HDMI_FC_SDPPRODUCTNAME10 0x105C
++#define HDMI_FC_SDPPRODUCTNAME11 0x105D
++#define HDMI_FC_SDPPRODUCTNAME12 0x105E
++#define HDMI_FC_SDPPRODUCTNAME13 0x105F
++#define HDMI_FC_SDPPRODUCTNAME14 0x1060
++#define HDMI_FC_SPDPRODUCTNAME15 0x1061
++#define HDMI_FC_SPDDEVICEINF 0x1062
++#define HDMI_FC_AUDSCONF 0x1063
++#define HDMI_FC_AUDSSTAT 0x1064
++#define HDMI_FC_DATACH0FILL 0x1070
++#define HDMI_FC_DATACH1FILL 0x1071
++#define HDMI_FC_DATACH2FILL 0x1072
++#define HDMI_FC_CTRLQHIGH 0x1073
++#define HDMI_FC_CTRLQLOW 0x1074
++#define HDMI_FC_ACP0 0x1075
++#define HDMI_FC_ACP28 0x1076
++#define HDMI_FC_ACP27 0x1077
++#define HDMI_FC_ACP26 0x1078
++#define HDMI_FC_ACP25 0x1079
++#define HDMI_FC_ACP24 0x107A
++#define HDMI_FC_ACP23 0x107B
++#define HDMI_FC_ACP22 0x107C
++#define HDMI_FC_ACP21 0x107D
++#define HDMI_FC_ACP20 0x107E
++#define HDMI_FC_ACP19 0x107F
++#define HDMI_FC_ACP18 0x1080
++#define HDMI_FC_ACP17 0x1081
++#define HDMI_FC_ACP16 0x1082
++#define HDMI_FC_ACP15 0x1083
++#define HDMI_FC_ACP14 0x1084
++#define HDMI_FC_ACP13 0x1085
++#define HDMI_FC_ACP12 0x1086
++#define HDMI_FC_ACP11 0x1087
++#define HDMI_FC_ACP10 0x1088
++#define HDMI_FC_ACP9 0x1089
++#define HDMI_FC_ACP8 0x108A
++#define HDMI_FC_ACP7 0x108B
++#define HDMI_FC_ACP6 0x108C
++#define HDMI_FC_ACP5 0x108D
++#define HDMI_FC_ACP4 0x108E
++#define HDMI_FC_ACP3 0x108F
++#define HDMI_FC_ACP2 0x1090
++#define HDMI_FC_ACP1 0x1091
++#define HDMI_FC_ISCR1_0 0x1092
++#define HDMI_FC_ISCR1_16 0x1093
++#define HDMI_FC_ISCR1_15 0x1094
++#define HDMI_FC_ISCR1_14 0x1095
++#define HDMI_FC_ISCR1_13 0x1096
++#define HDMI_FC_ISCR1_12 0x1097
++#define HDMI_FC_ISCR1_11 0x1098
++#define HDMI_FC_ISCR1_10 0x1099
++#define HDMI_FC_ISCR1_9 0x109A
++#define HDMI_FC_ISCR1_8 0x109B
++#define HDMI_FC_ISCR1_7 0x109C
++#define HDMI_FC_ISCR1_6 0x109D
++#define HDMI_FC_ISCR1_5 0x109E
++#define HDMI_FC_ISCR1_4 0x109F
++#define HDMI_FC_ISCR1_3 0x10A0
++#define HDMI_FC_ISCR1_2 0x10A1
++#define HDMI_FC_ISCR1_1 0x10A2
++#define HDMI_FC_ISCR2_15 0x10A3
++#define HDMI_FC_ISCR2_14 0x10A4
++#define HDMI_FC_ISCR2_13 0x10A5
++#define HDMI_FC_ISCR2_12 0x10A6
++#define HDMI_FC_ISCR2_11 0x10A7
++#define HDMI_FC_ISCR2_10 0x10A8
++#define HDMI_FC_ISCR2_9 0x10A9
++#define HDMI_FC_ISCR2_8 0x10AA
++#define HDMI_FC_ISCR2_7 0x10AB
++#define HDMI_FC_ISCR2_6 0x10AC
++#define HDMI_FC_ISCR2_5 0x10AD
++#define HDMI_FC_ISCR2_4 0x10AE
++#define HDMI_FC_ISCR2_3 0x10AF
++#define HDMI_FC_ISCR2_2 0x10B0
++#define HDMI_FC_ISCR2_1 0x10B1
++#define HDMI_FC_ISCR2_0 0x10B2
++#define HDMI_FC_DATAUTO0 0x10B3
++#define HDMI_FC_DATAUTO1 0x10B4
++#define HDMI_FC_DATAUTO2 0x10B5
++#define HDMI_FC_DATMAN 0x10B6
++#define HDMI_FC_DATAUTO3 0x10B7
++#define HDMI_FC_RDRB0 0x10B8
++#define HDMI_FC_RDRB1 0x10B9
++#define HDMI_FC_RDRB2 0x10BA
++#define HDMI_FC_RDRB3 0x10BB
++#define HDMI_FC_RDRB4 0x10BC
++#define HDMI_FC_RDRB5 0x10BD
++#define HDMI_FC_RDRB6 0x10BE
++#define HDMI_FC_RDRB7 0x10BF
++#define HDMI_FC_STAT0 0x10D0
++#define HDMI_FC_INT0 0x10D1
++#define HDMI_FC_MASK0 0x10D2
++#define HDMI_FC_POL0 0x10D3
++#define HDMI_FC_STAT1 0x10D4
++#define HDMI_FC_INT1 0x10D5
++#define HDMI_FC_MASK1 0x10D6
++#define HDMI_FC_POL1 0x10D7
++#define HDMI_FC_STAT2 0x10D8
++#define HDMI_FC_INT2 0x10D9
++#define HDMI_FC_MASK2 0x10DA
++#define HDMI_FC_POL2 0x10DB
++#define HDMI_FC_PRCONF 0x10E0
++
++#define HDMI_FC_GMD_STAT 0x1100
++#define HDMI_FC_GMD_EN 0x1101
++#define HDMI_FC_GMD_UP 0x1102
++#define HDMI_FC_GMD_CONF 0x1103
++#define HDMI_FC_GMD_HB 0x1104
++#define HDMI_FC_GMD_PB0 0x1105
++#define HDMI_FC_GMD_PB1 0x1106
++#define HDMI_FC_GMD_PB2 0x1107
++#define HDMI_FC_GMD_PB3 0x1108
++#define HDMI_FC_GMD_PB4 0x1109
++#define HDMI_FC_GMD_PB5 0x110A
++#define HDMI_FC_GMD_PB6 0x110B
++#define HDMI_FC_GMD_PB7 0x110C
++#define HDMI_FC_GMD_PB8 0x110D
++#define HDMI_FC_GMD_PB9 0x110E
++#define HDMI_FC_GMD_PB10 0x110F
++#define HDMI_FC_GMD_PB11 0x1110
++#define HDMI_FC_GMD_PB12 0x1111
++#define HDMI_FC_GMD_PB13 0x1112
++#define HDMI_FC_GMD_PB14 0x1113
++#define HDMI_FC_GMD_PB15 0x1114
++#define HDMI_FC_GMD_PB16 0x1115
++#define HDMI_FC_GMD_PB17 0x1116
++#define HDMI_FC_GMD_PB18 0x1117
++#define HDMI_FC_GMD_PB19 0x1118
++#define HDMI_FC_GMD_PB20 0x1119
++#define HDMI_FC_GMD_PB21 0x111A
++#define HDMI_FC_GMD_PB22 0x111B
++#define HDMI_FC_GMD_PB23 0x111C
++#define HDMI_FC_GMD_PB24 0x111D
++#define HDMI_FC_GMD_PB25 0x111E
++#define HDMI_FC_GMD_PB26 0x111F
++#define HDMI_FC_GMD_PB27 0x1120
++
++#define HDMI_FC_DBGFORCE 0x1200
++#define HDMI_FC_DBGAUD0CH0 0x1201
++#define HDMI_FC_DBGAUD1CH0 0x1202
++#define HDMI_FC_DBGAUD2CH0 0x1203
++#define HDMI_FC_DBGAUD0CH1 0x1204
++#define HDMI_FC_DBGAUD1CH1 0x1205
++#define HDMI_FC_DBGAUD2CH1 0x1206
++#define HDMI_FC_DBGAUD0CH2 0x1207
++#define HDMI_FC_DBGAUD1CH2 0x1208
++#define HDMI_FC_DBGAUD2CH2 0x1209
++#define HDMI_FC_DBGAUD0CH3 0x120A
++#define HDMI_FC_DBGAUD1CH3 0x120B
++#define HDMI_FC_DBGAUD2CH3 0x120C
++#define HDMI_FC_DBGAUD0CH4 0x120D
++#define HDMI_FC_DBGAUD1CH4 0x120E
++#define HDMI_FC_DBGAUD2CH4 0x120F
++#define HDMI_FC_DBGAUD0CH5 0x1210
++#define HDMI_FC_DBGAUD1CH5 0x1211
++#define HDMI_FC_DBGAUD2CH5 0x1212
++#define HDMI_FC_DBGAUD0CH6 0x1213
++#define HDMI_FC_DBGAUD1CH6 0x1214
++#define HDMI_FC_DBGAUD2CH6 0x1215
++#define HDMI_FC_DBGAUD0CH7 0x1216
++#define HDMI_FC_DBGAUD1CH7 0x1217
++#define HDMI_FC_DBGAUD2CH7 0x1218
++#define HDMI_FC_DBGTMDS0 0x1219
++#define HDMI_FC_DBGTMDS1 0x121A
++#define HDMI_FC_DBGTMDS2 0x121B
++
++/* HDMI Source PHY Registers */
++#define HDMI_PHY_CONF0 0x3000
++#define HDMI_PHY_TST0 0x3001
++#define HDMI_PHY_TST1 0x3002
++#define HDMI_PHY_TST2 0x3003
++#define HDMI_PHY_STAT0 0x3004
++#define HDMI_PHY_INT0 0x3005
++#define HDMI_PHY_MASK0 0x3006
++#define HDMI_PHY_POL0 0x3007
++
++/* HDMI Master PHY Registers */
++#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
++#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
++#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
++#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
++#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
++#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
++#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
++#define HDMI_PHY_I2CM_INT_ADDR 0x3027
++#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
++#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
++#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
++
++/* Audio Sampler Registers */
++#define HDMI_AUD_CONF0 0x3100
++#define HDMI_AUD_CONF1 0x3101
++#define HDMI_AUD_INT 0x3102
++#define HDMI_AUD_CONF2 0x3103
++#define HDMI_AUD_N1 0x3200
++#define HDMI_AUD_N2 0x3201
++#define HDMI_AUD_N3 0x3202
++#define HDMI_AUD_CTS1 0x3203
++#define HDMI_AUD_CTS2 0x3204
++#define HDMI_AUD_CTS3 0x3205
++#define HDMI_AUD_INPUTCLKFS 0x3206
++#define HDMI_AUD_SPDIFINT 0x3302
++#define HDMI_AUD_CONF0_HBR 0x3400
++#define HDMI_AUD_HBR_STATUS 0x3401
++#define HDMI_AUD_HBR_INT 0x3402
++#define HDMI_AUD_HBR_POL 0x3403
++#define HDMI_AUD_HBR_MASK 0x3404
++
++/* Generic Parallel Audio Interface Registers */
++/* Not used as GPAUD interface is not enabled in hw */
++#define HDMI_GP_CONF0 0x3500
++#define HDMI_GP_CONF1 0x3501
++#define HDMI_GP_CONF2 0x3502
++#define HDMI_GP_STAT 0x3503
++#define HDMI_GP_INT 0x3504
++#define HDMI_GP_MASK 0x3505
++#define HDMI_GP_POL 0x3506
++
++/* Audio DMA Registers */
++#define HDMI_AHB_DMA_CONF0 0x3600
++#define HDMI_AHB_DMA_START 0x3601
++#define HDMI_AHB_DMA_STOP 0x3602
++#define HDMI_AHB_DMA_THRSLD 0x3603
++#define HDMI_AHB_DMA_STRADDR0 0x3604
++#define HDMI_AHB_DMA_STRADDR1 0x3605
++#define HDMI_AHB_DMA_STRADDR2 0x3606
++#define HDMI_AHB_DMA_STRADDR3 0x3607
++#define HDMI_AHB_DMA_STPADDR0 0x3608
++#define HDMI_AHB_DMA_STPADDR1 0x3609
++#define HDMI_AHB_DMA_STPADDR2 0x360a
++#define HDMI_AHB_DMA_STPADDR3 0x360b
++#define HDMI_AHB_DMA_BSTADDR0 0x360c
++#define HDMI_AHB_DMA_BSTADDR1 0x360d
++#define HDMI_AHB_DMA_BSTADDR2 0x360e
++#define HDMI_AHB_DMA_BSTADDR3 0x360f
++#define HDMI_AHB_DMA_MBLENGTH0 0x3610
++#define HDMI_AHB_DMA_MBLENGTH1 0x3611
++#define HDMI_AHB_DMA_STAT 0x3612
++#define HDMI_AHB_DMA_INT 0x3613
++#define HDMI_AHB_DMA_MASK 0x3614
++#define HDMI_AHB_DMA_POL 0x3615
++#define HDMI_AHB_DMA_CONF1 0x3616
++#define HDMI_AHB_DMA_BUFFSTAT 0x3617
++#define HDMI_AHB_DMA_BUFFINT 0x3618
++#define HDMI_AHB_DMA_BUFFMASK 0x3619
++#define HDMI_AHB_DMA_BUFFPOL 0x361a
++
++/* Main Controller Registers */
++#define HDMI_MC_SFRDIV 0x4000
++#define HDMI_MC_CLKDIS 0x4001
++#define HDMI_MC_SWRSTZ 0x4002
++#define HDMI_MC_OPCTRL 0x4003
++#define HDMI_MC_FLOWCTRL 0x4004
++#define HDMI_MC_PHYRSTZ 0x4005
++#define HDMI_MC_LOCKONCLOCK 0x4006
++#define HDMI_MC_HEACPHY_RST 0x4007
++
++/* Color Space Converter Registers */
++#define HDMI_CSC_CFG 0x4100
++#define HDMI_CSC_SCALE 0x4101
++#define HDMI_CSC_COEF_A1_MSB 0x4102
++#define HDMI_CSC_COEF_A1_LSB 0x4103
++#define HDMI_CSC_COEF_A2_MSB 0x4104
++#define HDMI_CSC_COEF_A2_LSB 0x4105
++#define HDMI_CSC_COEF_A3_MSB 0x4106
++#define HDMI_CSC_COEF_A3_LSB 0x4107
++#define HDMI_CSC_COEF_A4_MSB 0x4108
++#define HDMI_CSC_COEF_A4_LSB 0x4109
++#define HDMI_CSC_COEF_B1_MSB 0x410A
++#define HDMI_CSC_COEF_B1_LSB 0x410B
++#define HDMI_CSC_COEF_B2_MSB 0x410C
++#define HDMI_CSC_COEF_B2_LSB 0x410D
++#define HDMI_CSC_COEF_B3_MSB 0x410E
++#define HDMI_CSC_COEF_B3_LSB 0x410F
++#define HDMI_CSC_COEF_B4_MSB 0x4110
++#define HDMI_CSC_COEF_B4_LSB 0x4111
++#define HDMI_CSC_COEF_C1_MSB 0x4112
++#define HDMI_CSC_COEF_C1_LSB 0x4113
++#define HDMI_CSC_COEF_C2_MSB 0x4114
++#define HDMI_CSC_COEF_C2_LSB 0x4115
++#define HDMI_CSC_COEF_C3_MSB 0x4116
++#define HDMI_CSC_COEF_C3_LSB 0x4117
++#define HDMI_CSC_COEF_C4_MSB 0x4118
++#define HDMI_CSC_COEF_C4_LSB 0x4119
++
++/* HDCP Interrupt Registers */
++#define HDMI_A_APIINTCLR 0x5006
++#define HDMI_A_APIINTSTAT 0x5007
++#define HDMI_A_APIINTMSK 0x5008
++
++/* CEC Engine Registers */
++#define HDMI_CEC_CTRL 0x7D00
++#define HDMI_CEC_STAT 0x7D01
++#define HDMI_CEC_MASK 0x7D02
++#define HDMI_CEC_POLARITY 0x7D03
++#define HDMI_CEC_INT 0x7D04
++#define HDMI_CEC_ADDR_L 0x7D05
++#define HDMI_CEC_ADDR_H 0x7D06
++#define HDMI_CEC_TX_CNT 0x7D07
++#define HDMI_CEC_RX_CNT 0x7D08
++#define HDMI_CEC_TX_DATA0 0x7D10
++#define HDMI_CEC_TX_DATA1 0x7D11
++#define HDMI_CEC_TX_DATA2 0x7D12
++#define HDMI_CEC_TX_DATA3 0x7D13
++#define HDMI_CEC_TX_DATA4 0x7D14
++#define HDMI_CEC_TX_DATA5 0x7D15
++#define HDMI_CEC_TX_DATA6 0x7D16
++#define HDMI_CEC_TX_DATA7 0x7D17
++#define HDMI_CEC_TX_DATA8 0x7D18
++#define HDMI_CEC_TX_DATA9 0x7D19
++#define HDMI_CEC_TX_DATA10 0x7D1a
++#define HDMI_CEC_TX_DATA11 0x7D1b
++#define HDMI_CEC_TX_DATA12 0x7D1c
++#define HDMI_CEC_TX_DATA13 0x7D1d
++#define HDMI_CEC_TX_DATA14 0x7D1e
++#define HDMI_CEC_TX_DATA15 0x7D1f
++#define HDMI_CEC_RX_DATA0 0x7D20
++#define HDMI_CEC_RX_DATA1 0x7D21
++#define HDMI_CEC_RX_DATA2 0x7D22
++#define HDMI_CEC_RX_DATA3 0x7D23
++#define HDMI_CEC_RX_DATA4 0x7D24
++#define HDMI_CEC_RX_DATA5 0x7D25
++#define HDMI_CEC_RX_DATA6 0x7D26
++#define HDMI_CEC_RX_DATA7 0x7D27
++#define HDMI_CEC_RX_DATA8 0x7D28
++#define HDMI_CEC_RX_DATA9 0x7D29
++#define HDMI_CEC_RX_DATA10 0x7D2a
++#define HDMI_CEC_RX_DATA11 0x7D2b
++#define HDMI_CEC_RX_DATA12 0x7D2c
++#define HDMI_CEC_RX_DATA13 0x7D2d
++#define HDMI_CEC_RX_DATA14 0x7D2e
++#define HDMI_CEC_RX_DATA15 0x7D2f
++#define HDMI_CEC_LOCK 0x7D30
++#define HDMI_CEC_WKUPCTRL 0x7D31
++
++/* I2C Master Registers (E-DDC) */
++#define HDMI_I2CM_SLAVE 0x7E00
++#define HDMI_I2CM_ADDRESS 0x7E01
++#define HDMI_I2CM_DATAO 0x7E02
++#define HDMI_I2CM_DATAI 0x7E03
++#define HDMI_I2CM_OPERATION 0x7E04
++#define HDMI_I2CM_INT 0x7E05
++#define HDMI_I2CM_CTLINT 0x7E06
++#define HDMI_I2CM_DIV 0x7E07
++#define HDMI_I2CM_SEGADDR 0x7E08
++#define HDMI_I2CM_SOFTRSTZ 0x7E09
++#define HDMI_I2CM_SEGPTR 0x7E0A
++#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
++#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
++#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
++#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
++#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
++#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
++#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
++#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
++
++/* Random Number Generator Registers (RNG) */
++#define HDMI_RNG_BASE 0x8000
++
++
++/*
++ * Register field definitions
++ */
++enum {
++/* IH_FC_INT2 field values */
++ HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_FC_STAT2 field values */
++ HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_PHY_STAT0 field values */
++ HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
++ HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
++ HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
++ HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
++ HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
++ HDMI_IH_PHY_STAT0_HPD = 0x1,
++
++/* IH_CEC_STAT0 field values */
++ HDMI_IH_CEC_STAT0_WAKEUP = 0x40,
++ HDMI_IH_CEC_STAT0_ERROR_FOLL = 0x20,
++ HDMI_IH_CEC_STAT0_ERROR_INIT = 0x10,
++ HDMI_IH_CEC_STAT0_ARB_LOST = 0x8,
++ HDMI_IH_CEC_STAT0_NACK = 0x4,
++ HDMI_IH_CEC_STAT0_EOM = 0x2,
++ HDMI_IH_CEC_STAT0_DONE = 0x1,
++
++
++/* IH_MUTE_I2CMPHY_STAT0 field values */
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
++
++/* IH_PHY_STAT0 field values */
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE3 = 0x20,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE2 = 0x10,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE1 = 0x8,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE0 = 0x4,
++ HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2,
++ HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1,
++
++/* IH and IH_MUTE convenience macro RX_SENSE | HPD*/
++ HDMI_DVI_IH_STAT = 0x3D,
++
++
++/* IH_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE_FC_STAT2 field values */
++ HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_MUTE_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE field values */
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
++
++/* TX_INVID0 field values */
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
++ HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
++
++/* TX_INSTUFFING field values */
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
++
++/* VP_PR_CD field values */
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
++ HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
++
++/* VP_STUFF field values */
++ HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
++ HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
++
++/* VP_CONF field values */
++ HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
++ HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
++ HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PR_EN_MASK = 0x10,
++ HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
++ HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
++ HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
++ HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
++ HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
++
++/* VP_REMAP field values */
++ HDMI_VP_REMAP_MASK = 0x3,
++ HDMI_VP_REMAP_YCC422_24bit = 0x2,
++ HDMI_VP_REMAP_YCC422_20bit = 0x1,
++ HDMI_VP_REMAP_YCC422_16bit = 0x0,
++
++/* FC_INVIDCONF field values */
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
++ HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
++
++/* FC_AUDICONF0 field values */
++ HDMI_FC_AUDICONF0_CC_OFFSET = 4,
++ HDMI_FC_AUDICONF0_CC_MASK = 0x70,
++ HDMI_FC_AUDICONF0_CT_OFFSET = 0,
++ HDMI_FC_AUDICONF0_CT_MASK = 0xF,
++
++/* FC_AUDICONF1 field values */
++ HDMI_FC_AUDICONF1_SS_OFFSET = 3,
++ HDMI_FC_AUDICONF1_SS_MASK = 0x18,
++ HDMI_FC_AUDICONF1_SF_OFFSET = 0,
++ HDMI_FC_AUDICONF1_SF_MASK = 0x7,
++
++/* FC_AUDICONF3 field values */
++ HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
++ HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
++ HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
++ HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
++ HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
++ HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
++
++/* FC_AUDSCHNLS0 field values */
++ HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
++
++/* FC_AUDSCHNLS3-6 field values */
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
++
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
++
++/* HDMI_FC_AUDSCHNLS7 field values */
++ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
++
++/* HDMI_FC_AUDSCHNLS8 field values */
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
++
++/* FC_AUDSCONF field values */
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
++
++/* FC_STAT2 field values */
++ HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_INT2 field values */
++ HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_MASK2 field values */
++ HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_PRCONF field values */
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
++
++/* FC_AVICONF0-FC_AVICONF3 field values */
++ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
++ HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
++ HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
++ HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
++ HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
++ HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
++ HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
++
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
++ HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
++ HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
++ HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
++ HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
++
++ HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
++ HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
++ HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
++ HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
++ HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
++ HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
++ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
++ HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
++ HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
++ HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
++ HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
++ HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
++
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
++ HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
++ HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
++
++/* FC_DBGFORCE field values */
++ HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
++ HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
++
++/* PHY_CONF0 field values */
++ HDMI_PHY_CONF0_PDZ_MASK = 0x80,
++ HDMI_PHY_CONF0_PDZ_OFFSET = 7,
++ HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
++ HDMI_PHY_CONF0_SPARECTRL = 0x20,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
++ HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
++
++/* PHY_TST0 field values */
++ HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
++ HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
++ HDMI_PHY_TST0_TSTEN_MASK = 0x10,
++ HDMI_PHY_TST0_TSTEN_OFFSET = 4,
++ HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
++ HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
++
++/* PHY_STAT0 field values */
++ HDMI_PHY_RX_SENSE3 = 0x80,
++ HDMI_PHY_RX_SENSE2 = 0x40,
++ HDMI_PHY_RX_SENSE1 = 0x20,
++ HDMI_PHY_RX_SENSE0 = 0x10,
++ HDMI_PHY_HPD = 0x02,
++ HDMI_PHY_TX_PHY_LOCK = 0x01,
++
++/* HDMI STAT convenience RX_SENSE | HPD */
++ HDMI_DVI_STAT = 0xF2,
++
++/* PHY_I2CM_SLAVE_ADDR field values */
++ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
++ HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
++
++/* PHY_I2CM_OPERATION_ADDR field values */
++ HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
++ HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
++
++/* HDMI_PHY_I2CM_INT_ADDR */
++ HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
++ HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
++
++/* HDMI_PHY_I2CM_CTLINT_ADDR */
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
++
++/* AUD_CTS3 field values */
++ HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
++ HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
++ HDMI_AUD_CTS3_N_SHIFT_1 = 0,
++ HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
++ HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
++ HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
++ HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
++ HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
++ /* note that the CTS3 MANUAL bit has been removed
++ from our part. Can't set it, will read as 0. */
++ HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
++ HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
++
++/* AHB_DMA_CONF0 field values */
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
++ HDMI_AHB_DMA_CONF0_HBR = 0x10,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
++ HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
++ HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
++ HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
++ HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
++
++/* HDMI_AHB_DMA_START field values */
++ HDMI_AHB_DMA_START_START_OFFSET = 0,
++ HDMI_AHB_DMA_START_START_MASK = 0x01,
++
++/* HDMI_AHB_DMA_STOP field values */
++ HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
++ HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
++
++/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
++ HDMI_AHB_DMA_DONE = 0x80,
++ HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
++ HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
++ HDMI_AHB_DMA_ERROR = 0x10,
++ HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
++ HDMI_AHB_DMA_FIFO_FULL = 0x02,
++ HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
++
++/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
++ HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
++ HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
++
++/* MC_CLKDIS field values */
++ HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
++ HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
++ HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
++ HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
++ HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
++ HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
++ HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
++
++/* MC_SWRSTZ field values */
++ HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
++
++/* MC_FLOWCTRL field values */
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
++
++/* MC_PHYRSTZ field values */
++ HDMI_MC_PHYRSTZ_ASSERT = 0x0,
++ HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
++
++/* MC_HEACPHY_RST field values */
++ HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
++ HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
++
++/* CSC_CFG field values */
++ HDMI_CSC_CFG_INTMODE_MASK = 0x30,
++ HDMI_CSC_CFG_INTMODE_OFFSET = 4,
++ HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
++ HDMI_CSC_CFG_DECMODE_MASK = 0x3,
++ HDMI_CSC_CFG_DECMODE_OFFSET = 0,
++ HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
++
++/* CSC_SCALE field values */
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
++ HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
++
++/* I2CM_OPERATION field values */
++ HDMI_I2CM_OPERATION_WRITE = 0x10,
++ HDMI_I2CM_OPERATION_READ_EXT = 0x2,
++ HDMI_I2CM_OPERATION_READ = 0x1,
++
++/* HDMI_I2CM_INT */
++ HDMI_I2CM_INT_DONE_POL = 0x08,
++ HDMI_I2CM_INT_DONE_MASK = 0x04,
++
++/* HDMI_I2CM_CTLINT */
++ HDMI_I2CM_CTLINT_NAC_POL = 0x80,
++ HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
++ HDMI_I2CM_CTLINT_ARBITRATION_POL = 0x08,
++ HDMI_I2CM_CTLINT_ARBITRATION_MASK = 0x04,
++
++};
++
++enum imx_hdmi_type {
++ IMX6DL_HDMI,
++ IMX6Q_HDMI,
++};
++
++/* IOCTL commands */
++#define HDMI_IOC_MAGIC 'H'
++
++#define HDMI_IOC_GET_RESOURCE _IO(HDMI_IOC_MAGIC, 0)
++#define HDMI_IOC_GET_CPU_TYPE _IO(HDMI_IOC_MAGIC, 1)
++
++
++#endif /* __MXC_HDMI_H__ */
+diff -Nur linux-3.10.30.orig/kernel/auditfilter.c linux-linaro-stable-mx6/kernel/auditfilter.c
+--- linux-3.10.30.orig/kernel/auditfilter.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/auditfilter.c 2014-05-15 20:34:16.930150248 +0200
+@@ -423,7 +423,7 @@
+ f->lsm_rule = NULL;
+
+ /* Support legacy tests for a valid loginuid */
+- if ((f->type == AUDIT_LOGINUID) && (f->val == 4294967295)) {
++ if ((f->type == AUDIT_LOGINUID) && (f->val == ~0U)) {
+ f->type = AUDIT_LOGINUID_SET;
+ f->val = 0;
+ }
+diff -Nur linux-3.10.30.orig/kernel/cpu.c linux-linaro-stable-mx6/kernel/cpu.c
+--- linux-3.10.30.orig/kernel/cpu.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/cpu.c 2014-05-15 20:34:16.930150248 +0200
+@@ -726,3 +726,22 @@
+ {
+ cpumask_copy(to_cpumask(cpu_online_bits), src);
+ }
++
++static ATOMIC_NOTIFIER_HEAD(idle_notifier);
++void idle_notifier_register(struct notifier_block *n)
++{
++ atomic_notifier_chain_register(&idle_notifier, n);
++}
++EXPORT_SYMBOL_GPL(idle_notifier_register);
++
++void idle_notifier_unregister(struct notifier_block *n)
++{
++ atomic_notifier_chain_unregister(&idle_notifier, n);
++}
++EXPORT_SYMBOL_GPL(idle_notifier_unregister);
++
++void idle_notifier_call_chain(unsigned long val)
++{
++ atomic_notifier_call_chain(&idle_notifier, val, NULL);
++}
++EXPORT_SYMBOL_GPL(idle_notifier_call_chain);
+diff -Nur linux-3.10.30.orig/kernel/irq/handle.c linux-linaro-stable-mx6/kernel/irq/handle.c
+--- linux-3.10.30.orig/kernel/irq/handle.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/irq/handle.c 2014-05-15 20:34:16.950150392 +0200
+@@ -51,7 +51,7 @@
+ "but no thread function available.", irq, action->name);
+ }
+
+-static void irq_wake_thread(struct irq_desc *desc, struct irqaction *action)
++void __irq_wake_thread(struct irq_desc *desc, struct irqaction *action)
+ {
+ /*
+ * In case the thread crashed and was killed we just pretend that
+@@ -157,7 +157,7 @@
+ break;
+ }
+
+- irq_wake_thread(desc, action);
++ __irq_wake_thread(desc, action);
+
+ /* Fall through to add to randomness */
+ case IRQ_HANDLED:
+diff -Nur linux-3.10.30.orig/kernel/irq/internals.h linux-linaro-stable-mx6/kernel/irq/internals.h
+--- linux-3.10.30.orig/kernel/irq/internals.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/irq/internals.h 2014-05-15 20:34:16.950150392 +0200
+@@ -82,6 +82,7 @@
+ /* Resending of interrupts :*/
+ void check_irq_resend(struct irq_desc *desc, unsigned int irq);
+ bool irq_wait_for_poll(struct irq_desc *desc);
++void __irq_wake_thread(struct irq_desc *desc, struct irqaction *action);
+
+ #ifdef CONFIG_PROC_FS
+ extern void register_irq_proc(unsigned int irq, struct irq_desc *desc);
+diff -Nur linux-3.10.30.orig/kernel/irq/irqdesc.c linux-linaro-stable-mx6/kernel/irq/irqdesc.c
+--- linux-3.10.30.orig/kernel/irq/irqdesc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/irq/irqdesc.c 2014-05-15 20:34:16.950150392 +0200
+@@ -23,10 +23,35 @@
+ static struct lock_class_key irq_desc_lock_class;
+
+ #if defined(CONFIG_SMP)
++static int __init irq_affinity_setup(char *str)
++{
++ zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
++ cpulist_parse(str, irq_default_affinity);
++ /*
++ * Set at least the boot cpu. We don't want to end up with
++ * bugreports caused by random comandline masks
++ */
++ cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
++ return 1;
++}
++__setup("irqaffinity=", irq_affinity_setup);
++
++extern struct cpumask hmp_slow_cpu_mask;
++
+ static void __init init_irq_default_affinity(void)
+ {
+- alloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
+- cpumask_setall(irq_default_affinity);
++#ifdef CONFIG_CPUMASK_OFFSTACK
++ if (!irq_default_affinity)
++ zalloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT);
++#endif
++#ifdef CONFIG_SCHED_HMP
++ if (!cpumask_empty(&hmp_slow_cpu_mask)) {
++ cpumask_copy(irq_default_affinity, &hmp_slow_cpu_mask);
++ return;
++ }
++#endif
++ if (cpumask_empty(irq_default_affinity))
++ cpumask_setall(irq_default_affinity);
+ }
+ #else
+ static void __init init_irq_default_affinity(void)
+diff -Nur linux-3.10.30.orig/kernel/irq/manage.c linux-linaro-stable-mx6/kernel/irq/manage.c
+--- linux-3.10.30.orig/kernel/irq/manage.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/irq/manage.c 2014-05-15 20:34:16.978150594 +0200
+@@ -32,24 +32,10 @@
+ early_param("threadirqs", setup_forced_irqthreads);
+ #endif
+
+-/**
+- * synchronize_irq - wait for pending IRQ handlers (on other CPUs)
+- * @irq: interrupt number to wait for
+- *
+- * This function waits for any pending IRQ handlers for this interrupt
+- * to complete before returning. If you use this function while
+- * holding a resource the IRQ handler may need you will deadlock.
+- *
+- * This function may be called - with care - from IRQ context.
+- */
+-void synchronize_irq(unsigned int irq)
++static void __synchronize_hardirq(struct irq_desc *desc)
+ {
+- struct irq_desc *desc = irq_to_desc(irq);
+ bool inprogress;
+
+- if (!desc)
+- return;
+-
+ do {
+ unsigned long flags;
+
+@@ -67,12 +53,53 @@
+
+ /* Oops, that failed? */
+ } while (inprogress);
++}
+
+- /*
+- * We made sure that no hardirq handler is running. Now verify
+- * that no threaded handlers are active.
+- */
+- wait_event(desc->wait_for_threads, !atomic_read(&desc->threads_active));
++/**
++ * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
++ * @irq: interrupt number to wait for
++ *
++ * This function waits for any pending hard IRQ handlers for this
++ * interrupt to complete before returning. If you use this
++ * function while holding a resource the IRQ handler may need you
++ * will deadlock. It does not take associated threaded handlers into
++ * account.
++ *
++ * This function may be called - with care - from IRQ context.
++ */
++void synchronize_hardirq(unsigned int irq)
++{
++ struct irq_desc *desc = irq_to_desc(irq);
++
++ if (desc)
++ __synchronize_hardirq(desc);
++}
++EXPORT_SYMBOL(synchronize_hardirq);
++
++/**
++ * synchronize_irq - wait for pending IRQ handlers (on other CPUs)
++ * @irq: interrupt number to wait for
++ *
++ * This function waits for any pending IRQ handlers for this interrupt
++ * to complete before returning. If you use this function while
++ * holding a resource the IRQ handler may need you will deadlock.
++ *
++ * This function may be called - with care - from IRQ context.
++ */
++void synchronize_irq(unsigned int irq)
++{
++ struct irq_desc *desc = irq_to_desc(irq);
++
++ if (desc) {
++ __synchronize_hardirq(desc);
++ /*
++ * We made sure that no hardirq handler is
++ * running. Now verify that no threaded handlers are
++ * active.
++ */
++ wait_event(desc->wait_for_threads,
++ !atomic_read(&desc->threads_active));
++ }
+ }
+ EXPORT_SYMBOL(synchronize_irq);
+
+@@ -886,6 +913,33 @@
+ return 0;
+ }
+
++/**
++ * irq_wake_thread - wake the irq thread for the action identified by dev_id
++ * @irq: Interrupt line
++ * @dev_id: Device identity for which the thread should be woken
++ *
++ */
++void irq_wake_thread(unsigned int irq, void *dev_id)
++{
++ struct irq_desc *desc = irq_to_desc(irq);
++ struct irqaction *action;
++ unsigned long flags;
++
++ if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc)))
++ return;
++
++ raw_spin_lock_irqsave(&desc->lock, flags);
++ for (action = desc->action; action; action = action->next) {
++ if (action->dev_id == dev_id) {
++ if (action->thread)
++ __irq_wake_thread(desc, action);
++ break;
++ }
++ }
++ raw_spin_unlock_irqrestore(&desc->lock, flags);
++}
++EXPORT_SYMBOL_GPL(irq_wake_thread);
++
+ static void irq_setup_forced_threading(struct irqaction *new)
+ {
+ if (!force_irqthreads)
+diff -Nur linux-3.10.30.orig/kernel/power/Kconfig linux-linaro-stable-mx6/kernel/power/Kconfig
+--- linux-3.10.30.orig/kernel/power/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/power/Kconfig 2014-05-15 20:34:17.006150795 +0200
+@@ -263,6 +263,26 @@
+ bool
+ depends on PM
+
++config WQ_POWER_EFFICIENT_DEFAULT
++ bool "Enable workqueue power-efficient mode by default"
++ depends on PM
++ default n
++ help
++ Per-cpu workqueues are generally preferred because they show
++ better performance thanks to cache locality; unfortunately,
++ per-cpu workqueues tend to be more power hungry than unbound
++ workqueues.
++
++ Enabling workqueue.power_efficient kernel parameter makes the
++ per-cpu workqueues which were observed to contribute
++ significantly to power consumption unbound, leading to measurably
++ lower power usage at the cost of small performance overhead.
++
++ This config option determines whether workqueue.power_efficient
++ is enabled by default.
++
++ If in doubt, say N.
++
+ config PM_GENERIC_DOMAINS_SLEEP
+ def_bool y
+ depends on PM_SLEEP && PM_GENERIC_DOMAINS
+diff -Nur linux-3.10.30.orig/kernel/sched/core.c linux-linaro-stable-mx6/kernel/sched/core.c
+--- linux-3.10.30.orig/kernel/sched/core.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/sched/core.c 2014-05-15 20:34:17.086151372 +0200
+@@ -1623,6 +1623,20 @@
+ #if defined(CONFIG_SMP) && defined(CONFIG_FAIR_GROUP_SCHED)
+ p->se.avg.runnable_avg_period = 0;
+ p->se.avg.runnable_avg_sum = 0;
++#ifdef CONFIG_SCHED_HMP
++ /* keep LOAD_AVG_MAX in sync with fair.c if load avg series is changed */
++#define LOAD_AVG_MAX 47742
++ if (p->mm) {
++ p->se.avg.hmp_last_up_migration = 0;
++ p->se.avg.hmp_last_down_migration = 0;
++ p->se.avg.load_avg_ratio = 1023;
++ p->se.avg.load_avg_contrib =
++ (1023 * scale_load_down(p->se.load.weight));
++ p->se.avg.runnable_avg_period = LOAD_AVG_MAX;
++ p->se.avg.runnable_avg_sum = LOAD_AVG_MAX;
++ p->se.avg.usage_avg_sum = LOAD_AVG_MAX;
++ }
++#endif
+ #endif
+ #ifdef CONFIG_SCHEDSTATS
+ memset(&p->se.statistics, 0, sizeof(p->se.statistics));
+@@ -3825,6 +3839,8 @@
+ return pid ? find_task_by_vpid(pid) : current;
+ }
+
++extern struct cpumask hmp_slow_cpu_mask;
++
+ /* Actually do priority change: must hold rq lock. */
+ static void
+ __setscheduler(struct rq *rq, struct task_struct *p, int policy, int prio)
+@@ -3834,8 +3850,17 @@
+ p->normal_prio = normal_prio(p);
+ /* we are holding p->pi_lock already */
+ p->prio = rt_mutex_getprio(p);
+- if (rt_prio(p->prio))
++ if (rt_prio(p->prio)) {
+ p->sched_class = &rt_sched_class;
++#ifdef CONFIG_SCHED_HMP
++ if (!cpumask_empty(&hmp_slow_cpu_mask))
++ if (cpumask_equal(&p->cpus_allowed, cpu_all_mask)) {
++ p->nr_cpus_allowed =
++ cpumask_weight(&hmp_slow_cpu_mask);
++ do_set_cpus_allowed(p, &hmp_slow_cpu_mask);
++ }
++#endif
++ }
+ else
+ p->sched_class = &fair_sched_class;
+ set_load_weight(p);
+diff -Nur linux-3.10.30.orig/kernel/sched/debug.c linux-linaro-stable-mx6/kernel/sched/debug.c
+--- linux-3.10.30.orig/kernel/sched/debug.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/sched/debug.c 2014-05-15 20:34:17.086151372 +0200
+@@ -94,6 +94,7 @@
+ #ifdef CONFIG_SMP
+ P(se->avg.runnable_avg_sum);
+ P(se->avg.runnable_avg_period);
++ P(se->avg.usage_avg_sum);
+ P(se->avg.load_avg_contrib);
+ P(se->avg.decay_count);
+ #endif
+@@ -223,6 +224,8 @@
+ cfs_rq->tg_runnable_contrib);
+ SEQ_printf(m, " .%-30s: %d\n", "tg->runnable_avg",
+ atomic_read(&cfs_rq->tg->runnable_avg));
++ SEQ_printf(m, " .%-30s: %d\n", "tg->usage_avg",
++ atomic_read(&cfs_rq->tg->usage_avg));
+ #endif
+ #ifdef CONFIG_CFS_BANDWIDTH
+ SEQ_printf(m, " .%-30s: %d\n", "tg->cfs_bandwidth.timer_active",
+@@ -574,6 +577,12 @@
+ "nr_involuntary_switches", (long long)p->nivcsw);
+
+ P(se.load.weight);
++#if defined(CONFIG_SMP) && defined(CONFIG_FAIR_GROUP_SCHED)
++ P(se.avg.runnable_avg_sum);
++ P(se.avg.runnable_avg_period);
++ P(se.avg.load_avg_contrib);
++ P(se.avg.decay_count);
++#endif
+ P(policy);
+ P(prio);
+ #undef PN
+diff -Nur linux-3.10.30.orig/kernel/sched/fair.c linux-linaro-stable-mx6/kernel/sched/fair.c
+--- linux-3.10.30.orig/kernel/sched/fair.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/sched/fair.c 2014-05-15 20:34:17.086151372 +0200
+@@ -31,9 +31,18 @@
+ #include <linux/task_work.h>
+
+ #include <trace/events/sched.h>
++#include <linux/sysfs.h>
++#include <linux/vmalloc.h>
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++/* Include cpufreq header to add a notifier so that cpu frequency
++ * scaling can track the current CPU frequency
++ */
++#include <linux/cpufreq.h>
++#endif /* CONFIG_HMP_FREQUENCY_INVARIANT_SCALE */
+
+ #include "sched.h"
+
++
+ /*
+ * Targeted preemption latency for CPU-bound tasks:
+ * (default: 6ms * (1 + ilog(ncpus)), units: nanoseconds)
+@@ -1208,8 +1217,91 @@
+ return contrib + runnable_avg_yN_sum[n];
+ }
+
+-/*
+- * We can represent the historical contribution to runnable average as the
++#ifdef CONFIG_SCHED_HMP
++#define HMP_VARIABLE_SCALE_SHIFT 16ULL
++struct hmp_global_attr {
++ struct attribute attr;
++ ssize_t (*show)(struct kobject *kobj,
++ struct attribute *attr, char *buf);
++ ssize_t (*store)(struct kobject *a, struct attribute *b,
++ const char *c, size_t count);
++ int *value;
++ int (*to_sysfs)(int);
++ int (*from_sysfs)(int);
++ ssize_t (*to_sysfs_text)(char *buf, int buf_size);
++};
++
++#define HMP_DATA_SYSFS_MAX 8
++
++struct hmp_data_struct {
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ int freqinvar_load_scale_enabled;
++#endif
++ int multiplier; /* used to scale the time delta */
++ struct attribute_group attr_group;
++ struct attribute *attributes[HMP_DATA_SYSFS_MAX + 1];
++ struct hmp_global_attr attr[HMP_DATA_SYSFS_MAX];
++} hmp_data;
++
++static u64 hmp_variable_scale_convert(u64 delta);
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++/* Frequency-Invariant Load Modification:
++ * Loads are calculated as in PJT's patch however we also scale the current
++ * contribution in line with the frequency of the CPU that the task was
++ * executed on.
++ * In this version, we use a simple linear scale derived from the maximum
++ * frequency reported by CPUFreq. As an example:
++ *
++ * Consider that we ran a task for 100% of the previous interval.
++ *
++ * Our CPU was under asynchronous frequency control through one of the
++ * CPUFreq governors.
++ *
++ * The CPUFreq governor reports that it is able to scale the CPU between
++ * 500MHz and 1GHz.
++ *
++ * During the period, the CPU was running at 1GHz.
++ *
++ * In this case, our load contribution for that period is calculated as
++ * 1 * (number_of_active_microseconds)
++ *
++ * This results in our task being able to accumulate maximum load as normal.
++ *
++ *
++ * Consider now that our CPU was executing at 500MHz.
++ *
++ * We now scale the load contribution such that it is calculated as
++ * 0.5 * (number_of_active_microseconds)
++ *
++ * Our task can only record 50% maximum load during this period.
++ *
++ * This represents the task consuming 50% of the CPU's *possible* compute
++ * capacity. However the task did consume 100% of the CPU's *available*
++ * compute capacity which is the value seen by the CPUFreq governor and
++ * user-side CPU Utilization tools.
++ *
++ * Restricting tracked load to be scaled by the CPU's frequency accurately
++ * represents the consumption of possible compute capacity and allows the
++ * HMP migration's simple threshold migration strategy to interact more
++ * predictably with CPUFreq's asynchronous compute capacity changes.
++ */
++#define SCHED_FREQSCALE_SHIFT 10
++struct cpufreq_extents {
++ u32 curr_scale;
++ u32 min;
++ u32 max;
++ u32 flags;
++};
++/* Flag set when the governor in use only allows one frequency.
++ * Disables scaling.
++ */
++#define SCHED_LOAD_FREQINVAR_SINGLEFREQ 0x01
++
++static struct cpufreq_extents freq_scale[CONFIG_NR_CPUS];
++#endif /* CONFIG_HMP_FREQUENCY_INVARIANT_SCALE */
++#endif /* CONFIG_SCHED_HMP */
++
++/* We can represent the historical contribution to runnable average as the
+ * coefficients of a geometric series. To do this we sub-divide our runnable
+ * history into segments of approximately 1ms (1024us); label the segment that
+ * occurred N-ms ago p_N, with p_0 corresponding to the current period, e.g.
+@@ -1238,13 +1330,24 @@
+ */
+ static __always_inline int __update_entity_runnable_avg(u64 now,
+ struct sched_avg *sa,
+- int runnable)
++ int runnable,
++ int running,
++ int cpu)
+ {
+ u64 delta, periods;
+ u32 runnable_contrib;
+ int delta_w, decayed = 0;
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ u64 scaled_delta;
++ u32 scaled_runnable_contrib;
++ int scaled_delta_w;
++ u32 curr_scale = 1024;
++#endif /* CONFIG_HMP_FREQUENCY_INVARIANT_SCALE */
+
+ delta = now - sa->last_runnable_update;
++#ifdef CONFIG_SCHED_HMP
++ delta = hmp_variable_scale_convert(delta);
++#endif
+ /*
+ * This should only happen when time goes backwards, which it
+ * unfortunately does during sched clock init when we swap over to TSC.
+@@ -1263,6 +1366,12 @@
+ return 0;
+ sa->last_runnable_update = now;
+
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ /* retrieve scale factor for load */
++ if (hmp_data.freqinvar_load_scale_enabled)
++ curr_scale = freq_scale[cpu].curr_scale;
++#endif /* CONFIG_HMP_FREQUENCY_INVARIANT_SCALE */
++
+ /* delta_w is the amount already accumulated against our next period */
+ delta_w = sa->runnable_avg_period % 1024;
+ if (delta + delta_w >= 1024) {
+@@ -1275,8 +1384,20 @@
+ * period and accrue it.
+ */
+ delta_w = 1024 - delta_w;
++ /* scale runnable time if necessary */
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ scaled_delta_w = (delta_w * curr_scale)
++ >> SCHED_FREQSCALE_SHIFT;
++ if (runnable)
++ sa->runnable_avg_sum += scaled_delta_w;
++ if (running)
++ sa->usage_avg_sum += scaled_delta_w;
++#else
+ if (runnable)
+ sa->runnable_avg_sum += delta_w;
++ if (running)
++ sa->usage_avg_sum += delta_w;
++#endif /* #ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE */
+ sa->runnable_avg_period += delta_w;
+
+ delta -= delta_w;
+@@ -1284,22 +1405,49 @@
+ /* Figure out how many additional periods this update spans */
+ periods = delta / 1024;
+ delta %= 1024;
+-
++ /* decay the load we have accumulated so far */
+ sa->runnable_avg_sum = decay_load(sa->runnable_avg_sum,
+ periods + 1);
+ sa->runnable_avg_period = decay_load(sa->runnable_avg_period,
+ periods + 1);
+-
++ sa->usage_avg_sum = decay_load(sa->usage_avg_sum, periods + 1);
++ /* add the contribution from this period */
+ /* Efficiently calculate \sum (1..n_period) 1024*y^i */
+ runnable_contrib = __compute_runnable_contrib(periods);
++ /* Apply load scaling if necessary.
++ * Note that multiplying the whole series is same as
++ * multiplying all terms
++ */
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ scaled_runnable_contrib = (runnable_contrib * curr_scale)
++ >> SCHED_FREQSCALE_SHIFT;
++ if (runnable)
++ sa->runnable_avg_sum += scaled_runnable_contrib;
++ if (running)
++ sa->usage_avg_sum += scaled_runnable_contrib;
++#else
+ if (runnable)
+ sa->runnable_avg_sum += runnable_contrib;
++ if (running)
++ sa->usage_avg_sum += runnable_contrib;
++#endif /* CONFIG_HMP_FREQUENCY_INVARIANT_SCALE */
+ sa->runnable_avg_period += runnable_contrib;
+ }
+
+ /* Remainder of delta accrued against u_0` */
++ /* scale if necessary */
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ scaled_delta = ((delta * curr_scale) >> SCHED_FREQSCALE_SHIFT);
++ if (runnable)
++ sa->runnable_avg_sum += scaled_delta;
++ if (running)
++ sa->usage_avg_sum += scaled_delta;
++#else
+ if (runnable)
+ sa->runnable_avg_sum += delta;
++ if (running)
++ sa->usage_avg_sum += delta;
++#endif /* CONFIG_HMP_FREQUENCY_INVARIANT_SCALE */
+ sa->runnable_avg_period += delta;
+
+ return decayed;
+@@ -1312,12 +1460,9 @@
+ u64 decays = atomic64_read(&cfs_rq->decay_counter);
+
+ decays -= se->avg.decay_count;
+- if (!decays)
+- return 0;
+-
+- se->avg.load_avg_contrib = decay_load(se->avg.load_avg_contrib, decays);
++ if (decays)
++ se->avg.load_avg_contrib = decay_load(se->avg.load_avg_contrib, decays);
+ se->avg.decay_count = 0;
+-
+ return decays;
+ }
+
+@@ -1345,16 +1490,28 @@
+ struct cfs_rq *cfs_rq)
+ {
+ struct task_group *tg = cfs_rq->tg;
+- long contrib;
++ long contrib, usage_contrib;
+
+ /* The fraction of a cpu used by this cfs_rq */
+ contrib = div_u64(sa->runnable_avg_sum << NICE_0_SHIFT,
+ sa->runnable_avg_period + 1);
+ contrib -= cfs_rq->tg_runnable_contrib;
+
+- if (abs(contrib) > cfs_rq->tg_runnable_contrib / 64) {
++ usage_contrib = div_u64(sa->usage_avg_sum << NICE_0_SHIFT,
++ sa->runnable_avg_period + 1);
++ usage_contrib -= cfs_rq->tg_usage_contrib;
++
++ /*
++ * contrib/usage at this point represent deltas, only update if they
++ * are substantive.
++ */
++ if ((abs(contrib) > cfs_rq->tg_runnable_contrib / 64) ||
++ (abs(usage_contrib) > cfs_rq->tg_usage_contrib / 64)) {
+ atomic_add(contrib, &tg->runnable_avg);
+ cfs_rq->tg_runnable_contrib += contrib;
++
++ atomic_add(usage_contrib, &tg->usage_avg);
++ cfs_rq->tg_usage_contrib += usage_contrib;
+ }
+ }
+
+@@ -1415,12 +1572,18 @@
+ contrib = se->avg.runnable_avg_sum * scale_load_down(se->load.weight);
+ contrib /= (se->avg.runnable_avg_period + 1);
+ se->avg.load_avg_contrib = scale_load(contrib);
++ trace_sched_task_load_contrib(task_of(se), se->avg.load_avg_contrib);
++ contrib = se->avg.runnable_avg_sum * scale_load_down(NICE_0_LOAD);
++ contrib /= (se->avg.runnable_avg_period + 1);
++ se->avg.load_avg_ratio = scale_load(contrib);
++ trace_sched_task_runnable_ratio(task_of(se), se->avg.load_avg_ratio);
+ }
+
+ /* Compute the current contribution to load_avg by se, return any delta */
+-static long __update_entity_load_avg_contrib(struct sched_entity *se)
++static long __update_entity_load_avg_contrib(struct sched_entity *se, long *ratio)
+ {
+ long old_contrib = se->avg.load_avg_contrib;
++ long old_ratio = se->avg.load_avg_ratio;
+
+ if (entity_is_task(se)) {
+ __update_task_entity_contrib(se);
+@@ -1429,6 +1592,8 @@
+ __update_group_entity_contrib(se);
+ }
+
++ if (ratio)
++ *ratio = se->avg.load_avg_ratio - old_ratio;
+ return se->avg.load_avg_contrib - old_contrib;
+ }
+
+@@ -1448,9 +1613,13 @@
+ int update_cfs_rq)
+ {
+ struct cfs_rq *cfs_rq = cfs_rq_of(se);
+- long contrib_delta;
++ long contrib_delta, ratio_delta;
+ u64 now;
++ int cpu = -1; /* not used in normal case */
+
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ cpu = cfs_rq->rq->cpu;
++#endif
+ /*
+ * For a group entity we need to use their owned cfs_rq_clock_task() in
+ * case they are the parent of a throttled hierarchy.
+@@ -1460,18 +1629,21 @@
+ else
+ now = cfs_rq_clock_task(group_cfs_rq(se));
+
+- if (!__update_entity_runnable_avg(now, &se->avg, se->on_rq))
++ if (!__update_entity_runnable_avg(now, &se->avg, se->on_rq,
++ cfs_rq->curr == se, cpu))
+ return;
+
+- contrib_delta = __update_entity_load_avg_contrib(se);
++ contrib_delta = __update_entity_load_avg_contrib(se, &ratio_delta);
+
+ if (!update_cfs_rq)
+ return;
+
+- if (se->on_rq)
++ if (se->on_rq) {
+ cfs_rq->runnable_load_avg += contrib_delta;
+- else
++ rq_of(cfs_rq)->avg.load_avg_ratio += ratio_delta;
++ } else {
+ subtract_blocked_load_contrib(cfs_rq, -contrib_delta);
++ }
+ }
+
+ /*
+@@ -1504,8 +1676,17 @@
+
+ static inline void update_rq_runnable_avg(struct rq *rq, int runnable)
+ {
+- __update_entity_runnable_avg(rq->clock_task, &rq->avg, runnable);
++ int cpu = -1; /* not used in normal case */
++
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ cpu = rq->cpu;
++#endif
++ __update_entity_runnable_avg(rq->clock_task, &rq->avg, runnable,
++ runnable, cpu);
+ __update_tg_runnable_avg(&rq->avg, &rq->cfs);
++ trace_sched_rq_runnable_ratio(cpu_of(rq), rq->avg.load_avg_ratio);
++ trace_sched_rq_runnable_load(cpu_of(rq), rq->cfs.runnable_load_avg);
++ trace_sched_rq_nr_running(cpu_of(rq), rq->nr_running, rq->nr_iowait.counter);
+ }
+
+ /* Add the load generated by se into cfs_rq's child load-average */
+@@ -1547,6 +1728,8 @@
+ }
+
+ cfs_rq->runnable_load_avg += se->avg.load_avg_contrib;
++ rq_of(cfs_rq)->avg.load_avg_ratio += se->avg.load_avg_ratio;
++
+ /* we force update consideration on load-balancer moves */
+ update_cfs_rq_blocked_load(cfs_rq, !wakeup);
+ }
+@@ -1565,6 +1748,8 @@
+ update_cfs_rq_blocked_load(cfs_rq, !sleep);
+
+ cfs_rq->runnable_load_avg -= se->avg.load_avg_contrib;
++ rq_of(cfs_rq)->avg.load_avg_ratio -= se->avg.load_avg_ratio;
++
+ if (sleep) {
+ cfs_rq->blocked_load_avg += se->avg.load_avg_contrib;
+ se->avg.decay_count = atomic64_read(&cfs_rq->decay_counter);
+@@ -1893,6 +2078,7 @@
+ */
+ update_stats_wait_end(cfs_rq, se);
+ __dequeue_entity(cfs_rq, se);
++ update_entity_load_avg(se, 1);
+ }
+
+ update_stats_curr_start(cfs_rq, se);
+@@ -3341,6 +3527,708 @@
+ return target;
+ }
+
++#ifdef CONFIG_SCHED_HMP
++/*
++ * Heterogenous multiprocessor (HMP) optimizations
++ *
++ * The cpu types are distinguished using a list of hmp_domains
++ * which each represent one cpu type using a cpumask.
++ * The list is assumed ordered by compute capacity with the
++ * fastest domain first.
++ */
++DEFINE_PER_CPU(struct hmp_domain *, hmp_cpu_domain);
++static const int hmp_max_tasks = 5;
++
++extern void __init arch_get_hmp_domains(struct list_head *hmp_domains_list);
++
++/* Setup hmp_domains */
++static int __init hmp_cpu_mask_setup(void)
++{
++ char buf[64];
++ struct hmp_domain *domain;
++ struct list_head *pos;
++ int dc, cpu;
++
++ pr_debug("Initializing HMP scheduler:\n");
++
++ /* Initialize hmp_domains using platform code */
++ arch_get_hmp_domains(&hmp_domains);
++ if (list_empty(&hmp_domains)) {
++ pr_debug("HMP domain list is empty!\n");
++ return 0;
++ }
++
++ /* Print hmp_domains */
++ dc = 0;
++ list_for_each(pos, &hmp_domains) {
++ domain = list_entry(pos, struct hmp_domain, hmp_domains);
++ cpulist_scnprintf(buf, 64, &domain->possible_cpus);
++ pr_debug(" HMP domain %d: %s\n", dc, buf);
++
++ for_each_cpu_mask(cpu, domain->possible_cpus) {
++ per_cpu(hmp_cpu_domain, cpu) = domain;
++ }
++ dc++;
++ }
++
++ return 1;
++}
++
++static struct hmp_domain *hmp_get_hmp_domain_for_cpu(int cpu)
++{
++ struct hmp_domain *domain;
++ struct list_head *pos;
++
++ list_for_each(pos, &hmp_domains) {
++ domain = list_entry(pos, struct hmp_domain, hmp_domains);
++ if(cpumask_test_cpu(cpu, &domain->possible_cpus))
++ return domain;
++ }
++ return NULL;
++}
++
++static void hmp_online_cpu(int cpu)
++{
++ struct hmp_domain *domain = hmp_get_hmp_domain_for_cpu(cpu);
++
++ if(domain)
++ cpumask_set_cpu(cpu, &domain->cpus);
++}
++
++static void hmp_offline_cpu(int cpu)
++{
++ struct hmp_domain *domain = hmp_get_hmp_domain_for_cpu(cpu);
++
++ if(domain)
++ cpumask_clear_cpu(cpu, &domain->cpus);
++}
++/*
++ * Needed to determine heaviest tasks etc.
++ */
++static inline unsigned int hmp_cpu_is_fastest(int cpu);
++static inline unsigned int hmp_cpu_is_slowest(int cpu);
++static inline struct hmp_domain *hmp_slower_domain(int cpu);
++static inline struct hmp_domain *hmp_faster_domain(int cpu);
++
++/* must hold runqueue lock for queue se is currently on */
++static struct sched_entity *hmp_get_heaviest_task(
++ struct sched_entity *se, int migrate_up)
++{
++ int num_tasks = hmp_max_tasks;
++ struct sched_entity *max_se = se;
++ unsigned long int max_ratio = se->avg.load_avg_ratio;
++ const struct cpumask *hmp_target_mask = NULL;
++
++ if (migrate_up) {
++ struct hmp_domain *hmp;
++ if (hmp_cpu_is_fastest(cpu_of(se->cfs_rq->rq)))
++ return max_se;
++
++ hmp = hmp_faster_domain(cpu_of(se->cfs_rq->rq));
++ hmp_target_mask = &hmp->cpus;
++ }
++ /* The currently running task is not on the runqueue */
++ se = __pick_first_entity(cfs_rq_of(se));
++
++ while (num_tasks && se) {
++ if (entity_is_task(se) &&
++ (se->avg.load_avg_ratio > max_ratio &&
++ hmp_target_mask &&
++ cpumask_intersects(hmp_target_mask,
++ tsk_cpus_allowed(task_of(se))))) {
++ max_se = se;
++ max_ratio = se->avg.load_avg_ratio;
++ }
++ se = __pick_next_entity(se);
++ num_tasks--;
++ }
++ return max_se;
++}
++
++static struct sched_entity *hmp_get_lightest_task(
++ struct sched_entity *se, int migrate_down)
++{
++ int num_tasks = hmp_max_tasks;
++ struct sched_entity *min_se = se;
++ unsigned long int min_ratio = se->avg.load_avg_ratio;
++ const struct cpumask *hmp_target_mask = NULL;
++
++ if (migrate_down) {
++ struct hmp_domain *hmp;
++ if (hmp_cpu_is_slowest(cpu_of(se->cfs_rq->rq)))
++ return min_se;
++ hmp = hmp_slower_domain(cpu_of(se->cfs_rq->rq));
++ hmp_target_mask = &hmp->cpus;
++ }
++ /* The currently running task is not on the runqueue */
++ se = __pick_first_entity(cfs_rq_of(se));
++
++ while (num_tasks && se) {
++ if (entity_is_task(se) &&
++ (se->avg.load_avg_ratio < min_ratio &&
++ hmp_target_mask &&
++ cpumask_intersects(hmp_target_mask,
++ tsk_cpus_allowed(task_of(se))))) {
++ min_se = se;
++ min_ratio = se->avg.load_avg_ratio;
++ }
++ se = __pick_next_entity(se);
++ num_tasks--;
++ }
++ return min_se;
++}
++
++/*
++ * Migration thresholds should be in the range [0..1023]
++ * hmp_up_threshold: min. load required for migrating tasks to a faster cpu
++ * hmp_down_threshold: max. load allowed for tasks migrating to a slower cpu
++ *
++ * hmp_up_prio: Only up migrate task with high priority (<hmp_up_prio)
++ * hmp_next_up_threshold: Delay before next up migration (1024 ~= 1 ms)
++ * hmp_next_down_threshold: Delay before next down migration (1024 ~= 1 ms)
++ *
++ * Small Task Packing:
++ * We can choose to fill the littlest CPUs in an HMP system rather than
++ * the typical spreading mechanic. This behavior is controllable using
++ * two variables.
++ * hmp_packing_enabled: runtime control over pack/spread
++ * hmp_full_threshold: Consider a CPU with this much unweighted load full
++ */
++unsigned int hmp_up_threshold = 700;
++unsigned int hmp_down_threshold = 512;
++#ifdef CONFIG_SCHED_HMP_PRIO_FILTER
++unsigned int hmp_up_prio = NICE_TO_PRIO(CONFIG_SCHED_HMP_PRIO_FILTER_VAL);
++#endif
++unsigned int hmp_next_up_threshold = 4096;
++unsigned int hmp_next_down_threshold = 4096;
++
++#ifdef CONFIG_SCHED_HMP_LITTLE_PACKING
++#ifndef CONFIG_ARCH_VEXPRESS_TC2
++unsigned int hmp_packing_enabled = 1;
++unsigned int hmp_full_threshold = (NICE_0_LOAD * 9) / 8;
++#else
++/* TC2 has a sharp consumption curve @ around 800Mhz, so
++ we aim to spread the load around that frequency. */
++unsigned int hmp_packing_enabled;
++unsigned int hmp_full_threshold = 650; /* 80% of the 800Mhz freq * NICE_0_LOAD */
++#endif
++#endif
++
++static unsigned int hmp_up_migration(int cpu, int *target_cpu, struct sched_entity *se);
++static unsigned int hmp_down_migration(int cpu, struct sched_entity *se);
++static inline unsigned int hmp_domain_min_load(struct hmp_domain *hmpd,
++ int *min_cpu, struct cpumask *affinity);
++
++static inline struct hmp_domain *hmp_smallest_domain(void)
++{
++ return list_entry(hmp_domains.prev, struct hmp_domain, hmp_domains);
++}
++
++/* Check if cpu is in fastest hmp_domain */
++static inline unsigned int hmp_cpu_is_fastest(int cpu)
++{
++ struct list_head *pos;
++
++ pos = &hmp_cpu_domain(cpu)->hmp_domains;
++ return pos == hmp_domains.next;
++}
++
++/* Check if cpu is in slowest hmp_domain */
++static inline unsigned int hmp_cpu_is_slowest(int cpu)
++{
++ struct list_head *pos;
++
++ pos = &hmp_cpu_domain(cpu)->hmp_domains;
++ return list_is_last(pos, &hmp_domains);
++}
++
++/* Next (slower) hmp_domain relative to cpu */
++static inline struct hmp_domain *hmp_slower_domain(int cpu)
++{
++ struct list_head *pos;
++
++ pos = &hmp_cpu_domain(cpu)->hmp_domains;
++ return list_entry(pos->next, struct hmp_domain, hmp_domains);
++}
++
++/* Previous (faster) hmp_domain relative to cpu */
++static inline struct hmp_domain *hmp_faster_domain(int cpu)
++{
++ struct list_head *pos;
++
++ pos = &hmp_cpu_domain(cpu)->hmp_domains;
++ return list_entry(pos->prev, struct hmp_domain, hmp_domains);
++}
++
++/*
++ * Selects a cpu in previous (faster) hmp_domain
++ */
++static inline unsigned int hmp_select_faster_cpu(struct task_struct *tsk,
++ int cpu)
++{
++ int lowest_cpu=NR_CPUS;
++ __always_unused int lowest_ratio;
++ struct hmp_domain *hmp;
++
++ if (hmp_cpu_is_fastest(cpu))
++ hmp = hmp_cpu_domain(cpu);
++ else
++ hmp = hmp_faster_domain(cpu);
++
++ lowest_ratio = hmp_domain_min_load(hmp, &lowest_cpu,
++ tsk_cpus_allowed(tsk));
++
++ return lowest_cpu;
++}
++
++/*
++ * Selects a cpu in next (slower) hmp_domain
++ * Note that cpumask_any_and() returns the first cpu in the cpumask
++ */
++static inline unsigned int hmp_select_slower_cpu(struct task_struct *tsk,
++ int cpu)
++{
++ int lowest_cpu=NR_CPUS;
++ struct hmp_domain *hmp;
++ __always_unused int lowest_ratio;
++
++ if (hmp_cpu_is_slowest(cpu))
++ hmp = hmp_cpu_domain(cpu);
++ else
++ hmp = hmp_slower_domain(cpu);
++
++ lowest_ratio = hmp_domain_min_load(hmp, &lowest_cpu,
++ tsk_cpus_allowed(tsk));
++
++ return lowest_cpu;
++}
++#ifdef CONFIG_SCHED_HMP_LITTLE_PACKING
++/*
++ * Select the 'best' candidate little CPU to wake up on.
++ * Implements a packing strategy which examines CPU in
++ * logical CPU order, and selects the first which will
++ * have at least 10% capacity available, according to
++ * both tracked load of the runqueue and the task.
++ */
++static inline unsigned int hmp_best_little_cpu(struct task_struct *tsk,
++ int cpu) {
++ int tmp_cpu;
++ unsigned long estimated_load;
++ struct hmp_domain *hmp;
++ struct sched_avg *avg;
++ struct cpumask allowed_hmp_cpus;
++
++ if(!hmp_packing_enabled ||
++ tsk->se.avg.load_avg_ratio > ((NICE_0_LOAD * 90)/100))
++ return hmp_select_slower_cpu(tsk, cpu);
++
++ if (hmp_cpu_is_slowest(cpu))
++ hmp = hmp_cpu_domain(cpu);
++ else
++ hmp = hmp_slower_domain(cpu);
++
++ /* respect affinity */
++ cpumask_and(&allowed_hmp_cpus, &hmp->cpus,
++ tsk_cpus_allowed(tsk));
++
++ for_each_cpu_mask(tmp_cpu, allowed_hmp_cpus) {
++ avg = &cpu_rq(tmp_cpu)->avg;
++ /* estimate new rq load if we add this task */
++ estimated_load = avg->load_avg_ratio +
++ tsk->se.avg.load_avg_ratio;
++ if (estimated_load <= hmp_full_threshold) {
++ cpu = tmp_cpu;
++ break;
++ }
++ }
++ /* if no match was found, the task uses the initial value */
++ return cpu;
++}
++#endif
++static inline void hmp_next_up_delay(struct sched_entity *se, int cpu)
++{
++ /* hack - always use clock from first online CPU */
++ u64 now = cpu_rq(cpumask_first(cpu_online_mask))->clock_task;
++ se->avg.hmp_last_up_migration = now;
++ se->avg.hmp_last_down_migration = 0;
++ cpu_rq(cpu)->avg.hmp_last_up_migration = now;
++ cpu_rq(cpu)->avg.hmp_last_down_migration = 0;
++}
++
++static inline void hmp_next_down_delay(struct sched_entity *se, int cpu)
++{
++ /* hack - always use clock from first online CPU */
++ u64 now = cpu_rq(cpumask_first(cpu_online_mask))->clock_task;
++ se->avg.hmp_last_down_migration = now;
++ se->avg.hmp_last_up_migration = 0;
++ cpu_rq(cpu)->avg.hmp_last_down_migration = now;
++ cpu_rq(cpu)->avg.hmp_last_up_migration = 0;
++}
++
++/*
++ * Heterogenous multiprocessor (HMP) optimizations
++ *
++ * These functions allow to change the growing speed of the load_avg_ratio
++ * by default it goes from 0 to 0.5 in LOAD_AVG_PERIOD = 32ms
++ * This can now be changed with /sys/kernel/hmp/load_avg_period_ms.
++ *
++ * These functions also allow to change the up and down threshold of HMP
++ * using /sys/kernel/hmp/{up,down}_threshold.
++ * Both must be between 0 and 1023. The threshold that is compared
++ * to the load_avg_ratio is up_threshold/1024 and down_threshold/1024.
++ *
++ * For instance, if load_avg_period = 64 and up_threshold = 512, an idle
++ * task with a load of 0 will reach the threshold after 64ms of busy loop.
++ *
++ * Changing load_avg_periods_ms has the same effect than changing the
++ * default scaling factor Y=1002/1024 in the load_avg_ratio computation to
++ * (1002/1024.0)^(LOAD_AVG_PERIOD/load_avg_period_ms), but the last one
++ * could trigger overflows.
++ * For instance, with Y = 1023/1024 in __update_task_entity_contrib()
++ * "contrib = se->avg.runnable_avg_sum * scale_load_down(se->load.weight);"
++ * could be overflowed for a weight > 2^12 even is the load_avg_contrib
++ * should still be a 32bits result. This would not happen by multiplicating
++ * delta time by 1/22 and setting load_avg_period_ms = 706.
++ */
++
++/*
++ * By scaling the delta time it end-up increasing or decrease the
++ * growing speed of the per entity load_avg_ratio
++ * The scale factor hmp_data.multiplier is a fixed point
++ * number: (32-HMP_VARIABLE_SCALE_SHIFT).HMP_VARIABLE_SCALE_SHIFT
++ */
++static inline u64 hmp_variable_scale_convert(u64 delta)
++{
++#ifdef CONFIG_HMP_VARIABLE_SCALE
++ u64 high = delta >> 32ULL;
++ u64 low = delta & 0xffffffffULL;
++ low *= hmp_data.multiplier;
++ high *= hmp_data.multiplier;
++ return (low >> HMP_VARIABLE_SCALE_SHIFT)
++ + (high << (32ULL - HMP_VARIABLE_SCALE_SHIFT));
++#else
++ return delta;
++#endif
++}
++
++static ssize_t hmp_show(struct kobject *kobj,
++ struct attribute *attr, char *buf)
++{
++ struct hmp_global_attr *hmp_attr =
++ container_of(attr, struct hmp_global_attr, attr);
++ int temp;
++
++ if (hmp_attr->to_sysfs_text != NULL)
++ return hmp_attr->to_sysfs_text(buf, PAGE_SIZE);
++
++ temp = *(hmp_attr->value);
++ if (hmp_attr->to_sysfs != NULL)
++ temp = hmp_attr->to_sysfs(temp);
++
++ return (ssize_t)sprintf(buf, "%d\n", temp);
++}
++
++static ssize_t hmp_store(struct kobject *a, struct attribute *attr,
++ const char *buf, size_t count)
++{
++ int temp;
++ ssize_t ret = count;
++ struct hmp_global_attr *hmp_attr =
++ container_of(attr, struct hmp_global_attr, attr);
++ char *str = vmalloc(count + 1);
++ if (str == NULL)
++ return -ENOMEM;
++ memcpy(str, buf, count);
++ str[count] = 0;
++ if (sscanf(str, "%d", &temp) < 1)
++ ret = -EINVAL;
++ else {
++ if (hmp_attr->from_sysfs != NULL)
++ temp = hmp_attr->from_sysfs(temp);
++ if (temp < 0)
++ ret = -EINVAL;
++ else
++ *(hmp_attr->value) = temp;
++ }
++ vfree(str);
++ return ret;
++}
++
++static ssize_t hmp_print_domains(char *outbuf, int outbufsize)
++{
++ char buf[64];
++ const char nospace[] = "%s", space[] = " %s";
++ const char *fmt = nospace;
++ struct hmp_domain *domain;
++ struct list_head *pos;
++ int outpos = 0;
++ list_for_each(pos, &hmp_domains) {
++ domain = list_entry(pos, struct hmp_domain, hmp_domains);
++ if (cpumask_scnprintf(buf, 64, &domain->possible_cpus)) {
++ outpos += sprintf(outbuf+outpos, fmt, buf);
++ fmt = space;
++ }
++ }
++ strcat(outbuf, "\n");
++ return outpos+1;
++}
++
++#ifdef CONFIG_HMP_VARIABLE_SCALE
++static int hmp_period_tofrom_sysfs(int value)
++{
++ return (LOAD_AVG_PERIOD << HMP_VARIABLE_SCALE_SHIFT) / value;
++}
++#endif
++/* max value for threshold is 1024 */
++static int hmp_theshold_from_sysfs(int value)
++{
++ if (value > 1024)
++ return -1;
++ return value;
++}
++#if defined(CONFIG_SCHED_HMP_LITTLE_PACKING) || \
++ defined(CONFIG_HMP_FREQUENCY_INVARIANT_SCALE)
++/* toggle control is only 0,1 off/on */
++static int hmp_toggle_from_sysfs(int value)
++{
++ if (value < 0 || value > 1)
++ return -1;
++ return value;
++}
++#endif
++#ifdef CONFIG_SCHED_HMP_LITTLE_PACKING
++/* packing value must be non-negative */
++static int hmp_packing_from_sysfs(int value)
++{
++ if (value < 0)
++ return -1;
++ return value;
++}
++#endif
++static void hmp_attr_add(
++ const char *name,
++ int *value,
++ int (*to_sysfs)(int),
++ int (*from_sysfs)(int),
++ ssize_t (*to_sysfs_text)(char *, int),
++ umode_t mode)
++{
++ int i = 0;
++ while (hmp_data.attributes[i] != NULL) {
++ i++;
++ if (i >= HMP_DATA_SYSFS_MAX)
++ return;
++ }
++ if (mode)
++ hmp_data.attr[i].attr.mode = mode;
++ else
++ hmp_data.attr[i].attr.mode = 0644;
++ hmp_data.attr[i].show = hmp_show;
++ hmp_data.attr[i].store = hmp_store;
++ hmp_data.attr[i].attr.name = name;
++ hmp_data.attr[i].value = value;
++ hmp_data.attr[i].to_sysfs = to_sysfs;
++ hmp_data.attr[i].from_sysfs = from_sysfs;
++ hmp_data.attr[i].to_sysfs_text = to_sysfs_text;
++ hmp_data.attributes[i] = &hmp_data.attr[i].attr;
++ hmp_data.attributes[i + 1] = NULL;
++}
++
++static int hmp_attr_init(void)
++{
++ int ret;
++ memset(&hmp_data, sizeof(hmp_data), 0);
++ hmp_attr_add("hmp_domains",
++ NULL,
++ NULL,
++ NULL,
++ hmp_print_domains,
++ 0444);
++ hmp_attr_add("up_threshold",
++ &hmp_up_threshold,
++ NULL,
++ hmp_theshold_from_sysfs,
++ NULL,
++ 0);
++ hmp_attr_add("down_threshold",
++ &hmp_down_threshold,
++ NULL,
++ hmp_theshold_from_sysfs,
++ NULL,
++ 0);
++#ifdef CONFIG_HMP_VARIABLE_SCALE
++ /* by default load_avg_period_ms == LOAD_AVG_PERIOD
++ * meaning no change
++ */
++ hmp_data.multiplier = hmp_period_tofrom_sysfs(LOAD_AVG_PERIOD);
++ hmp_attr_add("load_avg_period_ms",
++ &hmp_data.multiplier,
++ hmp_period_tofrom_sysfs,
++ hmp_period_tofrom_sysfs,
++ NULL,
++ 0);
++#endif
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++ /* default frequency-invariant scaling ON */
++ hmp_data.freqinvar_load_scale_enabled = 1;
++ hmp_attr_add("frequency_invariant_load_scale",
++ &hmp_data.freqinvar_load_scale_enabled,
++ NULL,
++ hmp_toggle_from_sysfs,
++ NULL,
++ 0);
++#endif
++#ifdef CONFIG_SCHED_HMP_LITTLE_PACKING
++ hmp_attr_add("packing_enable",
++ &hmp_packing_enabled,
++ NULL,
++ hmp_toggle_from_sysfs,
++ NULL,
++ 0);
++ hmp_attr_add("packing_limit",
++ &hmp_full_threshold,
++ NULL,
++ hmp_packing_from_sysfs,
++ NULL,
++ 0);
++#endif
++ hmp_data.attr_group.name = "hmp";
++ hmp_data.attr_group.attrs = hmp_data.attributes;
++ ret = sysfs_create_group(kernel_kobj,
++ &hmp_data.attr_group);
++ return 0;
++}
++late_initcall(hmp_attr_init);
++/*
++ * return the load of the lowest-loaded CPU in a given HMP domain
++ * min_cpu optionally points to an int to receive the CPU.
++ * affinity optionally points to a cpumask containing the
++ * CPUs to be considered. note:
++ * + min_cpu = NR_CPUS only if no CPUs are in the set of
++ * affinity && hmp_domain cpus
++ * + min_cpu will always otherwise equal one of the CPUs in
++ * the hmp domain
++ * + when more than one CPU has the same load, the one which
++ * is least-recently-disturbed by an HMP migration will be
++ * selected
++ * + if all CPUs are equally loaded or idle and the times are
++ * all the same, the first in the set will be used
++ * + if affinity is not set, cpu_online_mask is used
++ */
++static inline unsigned int hmp_domain_min_load(struct hmp_domain *hmpd,
++ int *min_cpu, struct cpumask *affinity)
++{
++ int cpu;
++ int min_cpu_runnable_temp = NR_CPUS;
++ u64 min_target_last_migration = ULLONG_MAX;
++ u64 curr_last_migration;
++ unsigned long min_runnable_load = INT_MAX;
++ unsigned long contrib;
++ struct sched_avg *avg;
++ struct cpumask temp_cpumask;
++ /*
++ * only look at CPUs allowed if specified,
++ * otherwise look at all online CPUs in the
++ * right HMP domain
++ */
++ cpumask_and(&temp_cpumask, &hmpd->cpus, affinity ? affinity : cpu_online_mask);
++
++ for_each_cpu_mask(cpu, temp_cpumask) {
++ avg = &cpu_rq(cpu)->avg;
++ /* used for both up and down migration */
++ curr_last_migration = avg->hmp_last_up_migration ?
++ avg->hmp_last_up_migration : avg->hmp_last_down_migration;
++
++ contrib = avg->load_avg_ratio;
++ /*
++ * Consider a runqueue completely busy if there is any load
++ * on it. Definitely not the best for overall fairness, but
++ * does well in typical Android use cases.
++ */
++ if (contrib)
++ contrib = 1023;
++
++ if ((contrib < min_runnable_load) ||
++ (contrib == min_runnable_load &&
++ curr_last_migration < min_target_last_migration)) {
++ /*
++ * if the load is the same target the CPU with
++ * the longest time since a migration.
++ * This is to spread migration load between
++ * members of a domain more evenly when the
++ * domain is fully loaded
++ */
++ min_runnable_load = contrib;
++ min_cpu_runnable_temp = cpu;
++ min_target_last_migration = curr_last_migration;
++ }
++ }
++
++ if (min_cpu)
++ *min_cpu = min_cpu_runnable_temp;
++
++ return min_runnable_load;
++}
++
++/*
++ * Calculate the task starvation
++ * This is the ratio of actually running time vs. runnable time.
++ * If the two are equal the task is getting the cpu time it needs or
++ * it is alone on the cpu and the cpu is fully utilized.
++ */
++static inline unsigned int hmp_task_starvation(struct sched_entity *se)
++{
++ u32 starvation;
++
++ starvation = se->avg.usage_avg_sum * scale_load_down(NICE_0_LOAD);
++ starvation /= (se->avg.runnable_avg_sum + 1);
++
++ return scale_load(starvation);
++}
++
++static inline unsigned int hmp_offload_down(int cpu, struct sched_entity *se)
++{
++ int min_usage;
++ int dest_cpu = NR_CPUS;
++
++ if (hmp_cpu_is_slowest(cpu))
++ return NR_CPUS;
++
++ /* Is there an idle CPU in the current domain */
++ min_usage = hmp_domain_min_load(hmp_cpu_domain(cpu), NULL, NULL);
++ if (min_usage == 0) {
++ trace_sched_hmp_offload_abort(cpu, min_usage, "load");
++ return NR_CPUS;
++ }
++
++ /* Is the task alone on the cpu? */
++ if (cpu_rq(cpu)->cfs.h_nr_running < 2) {
++ trace_sched_hmp_offload_abort(cpu,
++ cpu_rq(cpu)->cfs.h_nr_running, "nr_running");
++ return NR_CPUS;
++ }
++
++ /* Is the task actually starving? */
++ /* >=25% ratio running/runnable = starving */
++ if (hmp_task_starvation(se) > 768) {
++ trace_sched_hmp_offload_abort(cpu, hmp_task_starvation(se),
++ "starvation");
++ return NR_CPUS;
++ }
++
++ /* Does the slower domain have any idle CPUs? */
++ min_usage = hmp_domain_min_load(hmp_slower_domain(cpu), &dest_cpu,
++ tsk_cpus_allowed(task_of(se)));
++
++ if (min_usage == 0) {
++ trace_sched_hmp_offload_succeed(cpu, dest_cpu);
++ return dest_cpu;
++ } else
++ trace_sched_hmp_offload_abort(cpu,min_usage,"slowdomain");
++ return NR_CPUS;
++}
++#endif /* CONFIG_SCHED_HMP */
++
+ /*
+ * sched_balance_self: balance the current task (running on cpu) in domains
+ * that have the 'flag' flag set. In practice, this is SD_BALANCE_FORK and
+@@ -3365,6 +4253,19 @@
+ if (p->nr_cpus_allowed == 1)
+ return prev_cpu;
+
++#ifdef CONFIG_SCHED_HMP
++ /* always put non-kernel forking tasks on a big domain */
++ if (p->mm && (sd_flag & SD_BALANCE_FORK)) {
++ new_cpu = hmp_select_faster_cpu(p, prev_cpu);
++ if (new_cpu != NR_CPUS) {
++ hmp_next_up_delay(&p->se, new_cpu);
++ return new_cpu;
++ }
++ /* failed to perform HMP fork balance, use normal balance */
++ new_cpu = cpu;
++ }
++#endif
++
+ if (sd_flag & SD_BALANCE_WAKE) {
+ if (cpumask_test_cpu(cpu, tsk_cpus_allowed(p)))
+ want_affine = 1;
+@@ -3439,6 +4340,31 @@
+ unlock:
+ rcu_read_unlock();
+
++#ifdef CONFIG_SCHED_HMP
++ prev_cpu = task_cpu(p);
++
++ if (hmp_up_migration(prev_cpu, &new_cpu, &p->se)) {
++ hmp_next_up_delay(&p->se, new_cpu);
++ trace_sched_hmp_migrate(p, new_cpu, HMP_MIGRATE_WAKEUP);
++ return new_cpu;
++ }
++ if (hmp_down_migration(prev_cpu, &p->se)) {
++#ifdef CONFIG_SCHED_HMP_LITTLE_PACKING
++ new_cpu = hmp_best_little_cpu(p, prev_cpu);
++#else
++ new_cpu = hmp_select_slower_cpu(p, prev_cpu);
++#endif
++ if (new_cpu != prev_cpu) {
++ hmp_next_down_delay(&p->se, new_cpu);
++ trace_sched_hmp_migrate(p, new_cpu, HMP_MIGRATE_WAKEUP);
++ return new_cpu;
++ }
++ }
++ /* Make sure that the task stays in its previous hmp domain */
++ if (!cpumask_test_cpu(new_cpu, &hmp_cpu_domain(prev_cpu)->cpus))
++ return prev_cpu;
++#endif
++
+ return new_cpu;
+ }
+
+@@ -3448,9 +4374,19 @@
+ * load-balance).
+ */
+ #ifdef CONFIG_FAIR_GROUP_SCHED
+-/*
+- * Called immediately before a task is migrated to a new cpu; task_cpu(p) and
+- * cfs_rq_of(p) references at time of call are still valid and identify the
++
++#ifdef CONFIG_NO_HZ_COMMON
++static int nohz_test_cpu(int cpu);
++#else
++static inline int nohz_test_cpu(int cpu)
++{
++ return 0;
++}
++#endif
++
++/*
++ * Called immediately before a task is migrated to a new cpu; task_cpu(p) and
++ * cfs_rq_of(p) references at time of call are still valid and identify the
+ * previous cpu. However, the caller only guarantees p->pi_lock is held; no
+ * other assumptions, including the state of rq->lock, should be made.
+ */
+@@ -3467,6 +4403,25 @@
+ * be negative here since on-rq tasks have decay-count == 0.
+ */
+ if (se->avg.decay_count) {
++ /*
++ * If we migrate a sleeping task away from a CPU
++ * which has the tick stopped, then both the clock_task
++ * and decay_counter will be out of date for that CPU
++ * and we will not decay load correctly.
++ */
++ if (!se->on_rq && nohz_test_cpu(task_cpu(p))) {
++ struct rq *rq = cpu_rq(task_cpu(p));
++ unsigned long flags;
++ /*
++ * Current CPU cannot be holding rq->lock in this
++ * circumstance, but another might be. We must hold
++ * rq->lock before we go poking around in its clocks
++ */
++ raw_spin_lock_irqsave(&rq->lock, flags);
++ update_rq_clock(rq);
++ update_cfs_rq_blocked_load(cfs_rq, 0);
++ raw_spin_unlock_irqrestore(&rq->lock, flags);
++ }
+ se->avg.decay_count = -__synchronize_entity_decay(se);
+ atomic64_add(se->avg.load_avg_contrib, &cfs_rq->removed_load);
+ }
+@@ -3972,7 +4927,6 @@
+ * 1) task is cache cold, or
+ * 2) too many balance attempts have failed.
+ */
+-
+ tsk_cache_hot = task_hot(p, env->src_rq->clock_task, env->sd);
+ if (!tsk_cache_hot ||
+ env->sd->nr_balance_failed > env->sd->cache_nice_tries) {
+@@ -5257,7 +6211,9 @@
+ out:
+ return ld_moved;
+ }
+-
++#ifdef CONFIG_SCHED_HMP
++static unsigned int hmp_idle_pull(int this_cpu);
++#endif
+ /*
+ * idle_balance is called by schedule() if this_cpu is about to become
+ * idle. Attempts to pull tasks from other CPUs.
+@@ -5302,7 +6258,10 @@
+ }
+ }
+ rcu_read_unlock();
+-
++#ifdef CONFIG_SCHED_HMP
++ if (!pulled_task)
++ pulled_task = hmp_idle_pull(this_cpu);
++#endif
+ raw_spin_lock(&this_rq->lock);
+
+ if (pulled_task || time_after(jiffies, this_rq->next_balance)) {
+@@ -5395,12 +6354,65 @@
+ unsigned long next_balance; /* in jiffy units */
+ } nohz ____cacheline_aligned;
+
++/*
++ * nohz_test_cpu used when load tracking is enabled. FAIR_GROUP_SCHED
++ * dependency below may be removed when load tracking guards are
++ * removed.
++ */
++#ifdef CONFIG_FAIR_GROUP_SCHED
++static int nohz_test_cpu(int cpu)
++{
++ return cpumask_test_cpu(cpu, nohz.idle_cpus_mask);
++}
++#endif
++
++#ifdef CONFIG_SCHED_HMP_LITTLE_PACKING
++/*
++ * Decide if the tasks on the busy CPUs in the
++ * littlest domain would benefit from an idle balance
++ */
++static int hmp_packing_ilb_needed(int cpu)
++{
++ struct hmp_domain *hmp;
++ /* always allow ilb on non-slowest domain */
++ if (!hmp_cpu_is_slowest(cpu))
++ return 1;
++
++ /* if disabled, use normal ILB behaviour */
++ if (!hmp_packing_enabled)
++ return 1;
++
++ hmp = hmp_cpu_domain(cpu);
++ for_each_cpu_and(cpu, &hmp->cpus, nohz.idle_cpus_mask) {
++ /* only idle balance if a CPU is loaded over threshold */
++ if (cpu_rq(cpu)->avg.load_avg_ratio > hmp_full_threshold)
++ return 1;
++ }
++ return 0;
++}
++#endif
++
+ static inline int find_new_ilb(int call_cpu)
+ {
+ int ilb = cpumask_first(nohz.idle_cpus_mask);
++#ifdef CONFIG_SCHED_HMP
++ int ilb_needed = 1;
++
++ /* restrict nohz balancing to occur in the same hmp domain */
++ ilb = cpumask_first_and(nohz.idle_cpus_mask,
++ &((struct hmp_domain *)hmp_cpu_domain(call_cpu))->cpus);
++
++#ifdef CONFIG_SCHED_HMP_LITTLE_PACKING
++ if (ilb < nr_cpu_ids)
++ ilb_needed = hmp_packing_ilb_needed(ilb);
++#endif
+
++ if (ilb_needed && ilb < nr_cpu_ids && idle_cpu(ilb))
++ return ilb;
++#else
+ if (ilb < nr_cpu_ids && idle_cpu(ilb))
+ return ilb;
++#endif
+
+ return nr_cpu_ids;
+ }
+@@ -5677,6 +6689,18 @@
+ if (time_before(now, nohz.next_balance))
+ return 0;
+
++#ifdef CONFIG_SCHED_HMP
++ /*
++ * Bail out if there are no nohz CPUs in our
++ * HMP domain, since we will move tasks between
++ * domains through wakeup and force balancing
++ * as necessary based upon task load.
++ */
++ if (cpumask_first_and(nohz.idle_cpus_mask,
++ &((struct hmp_domain *)hmp_cpu_domain(cpu))->cpus) >= nr_cpu_ids)
++ return 0;
++#endif
++
+ if (rq->nr_running >= 2)
+ goto need_kick;
+
+@@ -5709,6 +6733,558 @@
+ static void nohz_idle_balance(int this_cpu, enum cpu_idle_type idle) { }
+ #endif
+
++#ifdef CONFIG_SCHED_HMP
++/* Check if task should migrate to a faster cpu */
++static unsigned int hmp_up_migration(int cpu, int *target_cpu, struct sched_entity *se)
++{
++ struct task_struct *p = task_of(se);
++ int temp_target_cpu;
++ u64 now;
++
++ if (hmp_cpu_is_fastest(cpu))
++ return 0;
++
++#ifdef CONFIG_SCHED_HMP_PRIO_FILTER
++ /* Filter by task priority */
++ if (p->prio >= hmp_up_prio)
++ return 0;
++#endif
++ if (se->avg.load_avg_ratio < hmp_up_threshold)
++ return 0;
++
++ /* Let the task load settle before doing another up migration */
++ /* hack - always use clock from first online CPU */
++ now = cpu_rq(cpumask_first(cpu_online_mask))->clock_task;
++ if (((now - se->avg.hmp_last_up_migration) >> 10)
++ < hmp_next_up_threshold)
++ return 0;
++
++ /* hmp_domain_min_load only returns 0 for an
++ * idle CPU or 1023 for any partly-busy one.
++ * Be explicit about requirement for an idle CPU.
++ */
++ if (hmp_domain_min_load(hmp_faster_domain(cpu), &temp_target_cpu,
++ tsk_cpus_allowed(p)) == 0 && temp_target_cpu != NR_CPUS) {
++ if(target_cpu)
++ *target_cpu = temp_target_cpu;
++ return 1;
++ }
++ return 0;
++}
++
++/* Check if task should migrate to a slower cpu */
++static unsigned int hmp_down_migration(int cpu, struct sched_entity *se)
++{
++ struct task_struct *p = task_of(se);
++ u64 now;
++
++ if (hmp_cpu_is_slowest(cpu)) {
++#ifdef CONFIG_SCHED_HMP_LITTLE_PACKING
++ if(hmp_packing_enabled)
++ return 1;
++ else
++#endif
++ return 0;
++ }
++
++#ifdef CONFIG_SCHED_HMP_PRIO_FILTER
++ /* Filter by task priority */
++ if ((p->prio >= hmp_up_prio) &&
++ cpumask_intersects(&hmp_slower_domain(cpu)->cpus,
++ tsk_cpus_allowed(p))) {
++ return 1;
++ }
++#endif
++
++ /* Let the task load settle before doing another down migration */
++ /* hack - always use clock from first online CPU */
++ now = cpu_rq(cpumask_first(cpu_online_mask))->clock_task;
++ if (((now - se->avg.hmp_last_down_migration) >> 10)
++ < hmp_next_down_threshold)
++ return 0;
++
++ if (cpumask_intersects(&hmp_slower_domain(cpu)->cpus,
++ tsk_cpus_allowed(p))
++ && se->avg.load_avg_ratio < hmp_down_threshold) {
++ return 1;
++ }
++ return 0;
++}
++
++/*
++ * hmp_can_migrate_task - may task p from runqueue rq be migrated to this_cpu?
++ * Ideally this function should be merged with can_migrate_task() to avoid
++ * redundant code.
++ */
++static int hmp_can_migrate_task(struct task_struct *p, struct lb_env *env)
++{
++ int tsk_cache_hot = 0;
++
++ /*
++ * We do not migrate tasks that are:
++ * 1) running (obviously), or
++ * 2) cannot be migrated to this CPU due to cpus_allowed
++ */
++ if (!cpumask_test_cpu(env->dst_cpu, tsk_cpus_allowed(p))) {
++ schedstat_inc(p, se.statistics.nr_failed_migrations_affine);
++ return 0;
++ }
++ env->flags &= ~LBF_ALL_PINNED;
++
++ if (task_running(env->src_rq, p)) {
++ schedstat_inc(p, se.statistics.nr_failed_migrations_running);
++ return 0;
++ }
++
++ /*
++ * Aggressive migration if:
++ * 1) task is cache cold, or
++ * 2) too many balance attempts have failed.
++ */
++
++ tsk_cache_hot = task_hot(p, env->src_rq->clock_task, env->sd);
++ if (!tsk_cache_hot ||
++ env->sd->nr_balance_failed > env->sd->cache_nice_tries) {
++#ifdef CONFIG_SCHEDSTATS
++ if (tsk_cache_hot) {
++ schedstat_inc(env->sd, lb_hot_gained[env->idle]);
++ schedstat_inc(p, se.statistics.nr_forced_migrations);
++ }
++#endif
++ return 1;
++ }
++
++ return 1;
++}
++
++/*
++ * move_specific_task tries to move a specific task.
++ * Returns 1 if successful and 0 otherwise.
++ * Called with both runqueues locked.
++ */
++static int move_specific_task(struct lb_env *env, struct task_struct *pm)
++{
++ struct task_struct *p, *n;
++
++ list_for_each_entry_safe(p, n, &env->src_rq->cfs_tasks, se.group_node) {
++ if (throttled_lb_pair(task_group(p), env->src_rq->cpu,
++ env->dst_cpu))
++ continue;
++
++ if (!hmp_can_migrate_task(p, env))
++ continue;
++ /* Check if we found the right task */
++ if (p != pm)
++ continue;
++
++ move_task(p, env);
++ /*
++ * Right now, this is only the third place move_task()
++ * is called, so we can safely collect move_task()
++ * stats here rather than inside move_task().
++ */
++ schedstat_inc(env->sd, lb_gained[env->idle]);
++ return 1;
++ }
++ return 0;
++}
++
++/*
++ * hmp_active_task_migration_cpu_stop is run by cpu stopper and used to
++ * migrate a specific task from one runqueue to another.
++ * hmp_force_up_migration uses this to push a currently running task
++ * off a runqueue.
++ * Based on active_load_balance_stop_cpu and can potentially be merged.
++ */
++static int hmp_active_task_migration_cpu_stop(void *data)
++{
++ struct rq *busiest_rq = data;
++ struct task_struct *p = busiest_rq->migrate_task;
++ int busiest_cpu = cpu_of(busiest_rq);
++ int target_cpu = busiest_rq->push_cpu;
++ struct rq *target_rq = cpu_rq(target_cpu);
++ struct sched_domain *sd;
++
++ raw_spin_lock_irq(&busiest_rq->lock);
++ /* make sure the requested cpu hasn't gone down in the meantime */
++ if (unlikely(busiest_cpu != smp_processor_id() ||
++ !busiest_rq->active_balance)) {
++ goto out_unlock;
++ }
++ /* Is there any task to move? */
++ if (busiest_rq->nr_running <= 1)
++ goto out_unlock;
++ /* Task has migrated meanwhile, abort forced migration */
++ if (task_rq(p) != busiest_rq)
++ goto out_unlock;
++ /*
++ * This condition is "impossible", if it occurs
++ * we need to fix it. Originally reported by
++ * Bjorn Helgaas on a 128-cpu setup.
++ */
++ BUG_ON(busiest_rq == target_rq);
++
++ /* move a task from busiest_rq to target_rq */
++ double_lock_balance(busiest_rq, target_rq);
++
++ /* Search for an sd spanning us and the target CPU. */
++ rcu_read_lock();
++ for_each_domain(target_cpu, sd) {
++ if (cpumask_test_cpu(busiest_cpu, sched_domain_span(sd)))
++ break;
++ }
++
++ if (likely(sd)) {
++ struct lb_env env = {
++ .sd = sd,
++ .dst_cpu = target_cpu,
++ .dst_rq = target_rq,
++ .src_cpu = busiest_rq->cpu,
++ .src_rq = busiest_rq,
++ .idle = CPU_IDLE,
++ };
++
++ schedstat_inc(sd, alb_count);
++
++ if (move_specific_task(&env, p))
++ schedstat_inc(sd, alb_pushed);
++ else
++ schedstat_inc(sd, alb_failed);
++ }
++ rcu_read_unlock();
++ double_unlock_balance(busiest_rq, target_rq);
++out_unlock:
++ put_task_struct(p);
++ busiest_rq->active_balance = 0;
++ raw_spin_unlock_irq(&busiest_rq->lock);
++ return 0;
++}
++
++/*
++ * hmp_idle_pull_cpu_stop is run by cpu stopper and used to
++ * migrate a specific task from one runqueue to another.
++ * hmp_idle_pull uses this to push a currently running task
++ * off a runqueue to a faster CPU.
++ * Locking is slightly different than usual.
++ * Based on active_load_balance_stop_cpu and can potentially be merged.
++ */
++static int hmp_idle_pull_cpu_stop(void *data)
++{
++ struct rq *busiest_rq = data;
++ struct task_struct *p = busiest_rq->migrate_task;
++ int busiest_cpu = cpu_of(busiest_rq);
++ int target_cpu = busiest_rq->push_cpu;
++ struct rq *target_rq = cpu_rq(target_cpu);
++ struct sched_domain *sd;
++
++ raw_spin_lock_irq(&busiest_rq->lock);
++
++ /* make sure the requested cpu hasn't gone down in the meantime */
++ if (unlikely(busiest_cpu != smp_processor_id() ||
++ !busiest_rq->active_balance))
++ goto out_unlock;
++
++ /* Is there any task to move? */
++ if (busiest_rq->nr_running <= 1)
++ goto out_unlock;
++
++ /* Task has migrated meanwhile, abort forced migration */
++ if (task_rq(p) != busiest_rq)
++ goto out_unlock;
++
++ /*
++ * This condition is "impossible", if it occurs
++ * we need to fix it. Originally reported by
++ * Bjorn Helgaas on a 128-cpu setup.
++ */
++ BUG_ON(busiest_rq == target_rq);
++
++ /* move a task from busiest_rq to target_rq */
++ double_lock_balance(busiest_rq, target_rq);
++
++ /* Search for an sd spanning us and the target CPU. */
++ rcu_read_lock();
++ for_each_domain(target_cpu, sd) {
++ if (cpumask_test_cpu(busiest_cpu, sched_domain_span(sd)))
++ break;
++ }
++ if (likely(sd)) {
++ struct lb_env env = {
++ .sd = sd,
++ .dst_cpu = target_cpu,
++ .dst_rq = target_rq,
++ .src_cpu = busiest_rq->cpu,
++ .src_rq = busiest_rq,
++ .idle = CPU_IDLE,
++ };
++
++ schedstat_inc(sd, alb_count);
++
++ if (move_specific_task(&env, p))
++ schedstat_inc(sd, alb_pushed);
++ else
++ schedstat_inc(sd, alb_failed);
++ }
++ rcu_read_unlock();
++ double_unlock_balance(busiest_rq, target_rq);
++out_unlock:
++ put_task_struct(p);
++ busiest_rq->active_balance = 0;
++ raw_spin_unlock_irq(&busiest_rq->lock);
++ return 0;
++}
++
++/*
++ * Move task in a runnable state to another CPU.
++ *
++ * Tailored on 'active_load_balance_stop_cpu' with slight
++ * modification to locking and pre-transfer checks. Note
++ * rq->lock must be held before calling.
++ */
++static void hmp_migrate_runnable_task(struct rq *rq)
++{
++ struct sched_domain *sd;
++ int src_cpu = cpu_of(rq);
++ struct rq *src_rq = rq;
++ int dst_cpu = rq->push_cpu;
++ struct rq *dst_rq = cpu_rq(dst_cpu);
++ struct task_struct *p = rq->migrate_task;
++ /*
++ * One last check to make sure nobody else is playing
++ * with the source rq.
++ */
++ if (src_rq->active_balance)
++ goto out;
++
++ if (src_rq->nr_running <= 1)
++ goto out;
++
++ if (task_rq(p) != src_rq)
++ goto out;
++ /*
++ * Not sure if this applies here but one can never
++ * be too cautious
++ */
++ BUG_ON(src_rq == dst_rq);
++
++ double_lock_balance(src_rq, dst_rq);
++
++ rcu_read_lock();
++ for_each_domain(dst_cpu, sd) {
++ if (cpumask_test_cpu(src_cpu, sched_domain_span(sd)))
++ break;
++ }
++
++ if (likely(sd)) {
++ struct lb_env env = {
++ .sd = sd,
++ .dst_cpu = dst_cpu,
++ .dst_rq = dst_rq,
++ .src_cpu = src_cpu,
++ .src_rq = src_rq,
++ .idle = CPU_IDLE,
++ };
++
++ schedstat_inc(sd, alb_count);
++
++ if (move_specific_task(&env, p))
++ schedstat_inc(sd, alb_pushed);
++ else
++ schedstat_inc(sd, alb_failed);
++ }
++
++ rcu_read_unlock();
++ double_unlock_balance(src_rq, dst_rq);
++out:
++ put_task_struct(p);
++}
++
++static DEFINE_SPINLOCK(hmp_force_migration);
++
++/*
++ * hmp_force_up_migration checks runqueues for tasks that need to
++ * be actively migrated to a faster cpu.
++ */
++static void hmp_force_up_migration(int this_cpu)
++{
++ int cpu, target_cpu;
++ struct sched_entity *curr, *orig;
++ struct rq *target;
++ unsigned long flags;
++ unsigned int force, got_target;
++ struct task_struct *p;
++
++ if (!spin_trylock(&hmp_force_migration))
++ return;
++ for_each_online_cpu(cpu) {
++ force = 0;
++ got_target = 0;
++ target = cpu_rq(cpu);
++ raw_spin_lock_irqsave(&target->lock, flags);
++ curr = target->cfs.curr;
++ if (!curr) {
++ raw_spin_unlock_irqrestore(&target->lock, flags);
++ continue;
++ }
++ if (!entity_is_task(curr)) {
++ struct cfs_rq *cfs_rq;
++
++ cfs_rq = group_cfs_rq(curr);
++ while (cfs_rq) {
++ curr = cfs_rq->curr;
++ cfs_rq = group_cfs_rq(curr);
++ }
++ }
++ orig = curr;
++ curr = hmp_get_heaviest_task(curr, 1);
++ p = task_of(curr);
++ if (hmp_up_migration(cpu, &target_cpu, curr)) {
++ if (!target->active_balance) {
++ get_task_struct(p);
++ target->push_cpu = target_cpu;
++ target->migrate_task = p;
++ got_target = 1;
++ trace_sched_hmp_migrate(p, target->push_cpu, HMP_MIGRATE_FORCE);
++ hmp_next_up_delay(&p->se, target->push_cpu);
++ }
++ }
++ if (!got_target && !target->active_balance) {
++ /*
++ * For now we just check the currently running task.
++ * Selecting the lightest task for offloading will
++ * require extensive book keeping.
++ */
++ curr = hmp_get_lightest_task(orig, 1);
++ p = task_of(curr);
++ target->push_cpu = hmp_offload_down(cpu, curr);
++ if (target->push_cpu < NR_CPUS) {
++ get_task_struct(p);
++ target->migrate_task = p;
++ got_target = 1;
++ trace_sched_hmp_migrate(p, target->push_cpu, HMP_MIGRATE_OFFLOAD);
++ hmp_next_down_delay(&p->se, target->push_cpu);
++ }
++ }
++ /*
++ * We have a target with no active_balance. If the task
++ * is not currently running move it, otherwise let the
++ * CPU stopper take care of it.
++ */
++ if (got_target && !target->active_balance) {
++ if (!task_running(target, p)) {
++ trace_sched_hmp_migrate_force_running(p, 0);
++ hmp_migrate_runnable_task(target);
++ } else {
++ target->active_balance = 1;
++ force = 1;
++ }
++ }
++
++ raw_spin_unlock_irqrestore(&target->lock, flags);
++
++ if (force)
++ stop_one_cpu_nowait(cpu_of(target),
++ hmp_active_task_migration_cpu_stop,
++ target, &target->active_balance_work);
++ }
++ spin_unlock(&hmp_force_migration);
++}
++/*
++ * hmp_idle_pull looks at little domain runqueues to see
++ * if a task should be pulled.
++ *
++ * Reuses hmp_force_migration spinlock.
++ *
++ */
++static unsigned int hmp_idle_pull(int this_cpu)
++{
++ int cpu;
++ struct sched_entity *curr, *orig;
++ struct hmp_domain *hmp_domain = NULL;
++ struct rq *target = NULL, *rq;
++ unsigned long flags, ratio = 0;
++ unsigned int force = 0;
++ struct task_struct *p = NULL;
++
++ if (!hmp_cpu_is_slowest(this_cpu))
++ hmp_domain = hmp_slower_domain(this_cpu);
++ if (!hmp_domain)
++ return 0;
++
++ if (!spin_trylock(&hmp_force_migration))
++ return 0;
++
++ /* first select a task */
++ for_each_cpu(cpu, &hmp_domain->cpus) {
++ rq = cpu_rq(cpu);
++ raw_spin_lock_irqsave(&rq->lock, flags);
++ curr = rq->cfs.curr;
++ if (!curr) {
++ raw_spin_unlock_irqrestore(&rq->lock, flags);
++ continue;
++ }
++ if (!entity_is_task(curr)) {
++ struct cfs_rq *cfs_rq;
++
++ cfs_rq = group_cfs_rq(curr);
++ while (cfs_rq) {
++ curr = cfs_rq->curr;
++ if (!entity_is_task(curr))
++ cfs_rq = group_cfs_rq(curr);
++ else
++ cfs_rq = NULL;
++ }
++ }
++ orig = curr;
++ curr = hmp_get_heaviest_task(curr, 1);
++ if (curr->avg.load_avg_ratio > hmp_up_threshold &&
++ curr->avg.load_avg_ratio > ratio) {
++ p = task_of(curr);
++ target = rq;
++ ratio = curr->avg.load_avg_ratio;
++ }
++ raw_spin_unlock_irqrestore(&rq->lock, flags);
++ }
++
++ if (!p)
++ goto done;
++
++ /* now we have a candidate */
++ raw_spin_lock_irqsave(&target->lock, flags);
++ if (!target->active_balance && task_rq(p) == target) {
++ get_task_struct(p);
++ target->push_cpu = this_cpu;
++ target->migrate_task = p;
++ trace_sched_hmp_migrate(p, target->push_cpu, HMP_MIGRATE_IDLE_PULL);
++ hmp_next_up_delay(&p->se, target->push_cpu);
++ /*
++ * if the task isn't running move it right away.
++ * Otherwise setup the active_balance mechanic and let
++ * the CPU stopper do its job.
++ */
++ if (!task_running(target, p)) {
++ trace_sched_hmp_migrate_idle_running(p, 0);
++ hmp_migrate_runnable_task(target);
++ } else {
++ target->active_balance = 1;
++ force = 1;
++ }
++ }
++ raw_spin_unlock_irqrestore(&target->lock, flags);
++
++ if (force) {
++ stop_one_cpu_nowait(cpu_of(target),
++ hmp_idle_pull_cpu_stop,
++ target, &target->active_balance_work);
++ }
++done:
++ spin_unlock(&hmp_force_migration);
++ return force;
++}
++#else
++static void hmp_force_up_migration(int this_cpu) { }
++#endif /* CONFIG_SCHED_HMP */
++
+ /*
+ * run_rebalance_domains is triggered when needed from the scheduler tick.
+ * Also triggered for nohz idle balancing (with nohz_balancing_kick set).
+@@ -5720,6 +7296,8 @@
+ enum cpu_idle_type idle = this_rq->idle_balance ?
+ CPU_IDLE : CPU_NOT_IDLE;
+
++ hmp_force_up_migration(this_cpu);
++
+ rebalance_domains(this_cpu, idle);
+
+ /*
+@@ -5752,11 +7330,17 @@
+
+ static void rq_online_fair(struct rq *rq)
+ {
++#ifdef CONFIG_SCHED_HMP
++ hmp_online_cpu(rq->cpu);
++#endif
+ update_sysctl();
+ }
+
+ static void rq_offline_fair(struct rq *rq)
+ {
++#ifdef CONFIG_SCHED_HMP
++ hmp_offline_cpu(rq->cpu);
++#endif
+ update_sysctl();
+
+ /* Ensure any throttled groups are reachable by pick_next_task */
+@@ -6224,6 +7808,139 @@
+ zalloc_cpumask_var(&nohz.idle_cpus_mask, GFP_NOWAIT);
+ cpu_notifier(sched_ilb_notifier, 0);
+ #endif
++
++#ifdef CONFIG_SCHED_HMP
++ hmp_cpu_mask_setup();
++#endif
+ #endif /* SMP */
+
+ }
++
++#ifdef CONFIG_HMP_FREQUENCY_INVARIANT_SCALE
++static u32 cpufreq_calc_scale(u32 min, u32 max, u32 curr)
++{
++ u32 result = curr / max;
++ return result;
++}
++
++/* Called when the CPU Frequency is changed.
++ * Once for each CPU.
++ */
++static int cpufreq_callback(struct notifier_block *nb,
++ unsigned long val, void *data)
++{
++ struct cpufreq_freqs *freq = data;
++ int cpu = freq->cpu;
++ struct cpufreq_extents *extents;
++
++ if (freq->flags & CPUFREQ_CONST_LOOPS)
++ return NOTIFY_OK;
++
++ if (val != CPUFREQ_POSTCHANGE)
++ return NOTIFY_OK;
++
++ /* if dynamic load scale is disabled, set the load scale to 1.0 */
++ if (!hmp_data.freqinvar_load_scale_enabled) {
++ freq_scale[cpu].curr_scale = 1024;
++ return NOTIFY_OK;
++ }
++
++ extents = &freq_scale[cpu];
++ if (extents->flags & SCHED_LOAD_FREQINVAR_SINGLEFREQ) {
++ /* If our governor was recognised as a single-freq governor,
++ * use 1.0
++ */
++ extents->curr_scale = 1024;
++ } else {
++ extents->curr_scale = cpufreq_calc_scale(extents->min,
++ extents->max, freq->new);
++ }
++
++ return NOTIFY_OK;
++}
++
++/* Called when the CPUFreq governor is changed.
++ * Only called for the CPUs which are actually changed by the
++ * userspace.
++ */
++static int cpufreq_policy_callback(struct notifier_block *nb,
++ unsigned long event, void *data)
++{
++ struct cpufreq_policy *policy = data;
++ struct cpufreq_extents *extents;
++ int cpu, singleFreq = 0;
++ static const char performance_governor[] = "performance";
++ static const char powersave_governor[] = "powersave";
++
++ if (event == CPUFREQ_START)
++ return 0;
++
++ if (event != CPUFREQ_INCOMPATIBLE)
++ return 0;
++
++ /* CPUFreq governors do not accurately report the range of
++ * CPU Frequencies they will choose from.
++ * We recognise performance and powersave governors as
++ * single-frequency only.
++ */
++ if (!strncmp(policy->governor->name, performance_governor,
++ strlen(performance_governor)) ||
++ !strncmp(policy->governor->name, powersave_governor,
++ strlen(powersave_governor)))
++ singleFreq = 1;
++
++ /* Make sure that all CPUs impacted by this policy are
++ * updated since we will only get a notification when the
++ * user explicitly changes the policy on a CPU.
++ */
++ for_each_cpu(cpu, policy->cpus) {
++ extents = &freq_scale[cpu];
++ extents->max = policy->max >> SCHED_FREQSCALE_SHIFT;
++ extents->min = policy->min >> SCHED_FREQSCALE_SHIFT;
++ if (!hmp_data.freqinvar_load_scale_enabled) {
++ extents->curr_scale = 1024;
++ } else if (singleFreq) {
++ extents->flags |= SCHED_LOAD_FREQINVAR_SINGLEFREQ;
++ extents->curr_scale = 1024;
++ } else {
++ extents->flags &= ~SCHED_LOAD_FREQINVAR_SINGLEFREQ;
++ extents->curr_scale = cpufreq_calc_scale(extents->min,
++ extents->max, policy->cur);
++ }
++ }
++
++ return 0;
++}
++
++static struct notifier_block cpufreq_notifier = {
++ .notifier_call = cpufreq_callback,
++};
++static struct notifier_block cpufreq_policy_notifier = {
++ .notifier_call = cpufreq_policy_callback,
++};
++
++static int __init register_sched_cpufreq_notifier(void)
++{
++ int ret = 0;
++
++ /* init safe defaults since there are no policies at registration */
++ for (ret = 0; ret < CONFIG_NR_CPUS; ret++) {
++ /* safe defaults */
++ freq_scale[ret].max = 1024;
++ freq_scale[ret].min = 1024;
++ freq_scale[ret].curr_scale = 1024;
++ }
++
++ pr_info("sched: registering cpufreq notifiers for scale-invariant loads\n");
++ ret = cpufreq_register_notifier(&cpufreq_policy_notifier,
++ CPUFREQ_POLICY_NOTIFIER);
++
++ if (ret != -EINVAL)
++ ret = cpufreq_register_notifier(&cpufreq_notifier,
++ CPUFREQ_TRANSITION_NOTIFIER);
++
++ return ret;
++}
++
++core_initcall(register_sched_cpufreq_notifier);
++#endif /* CONFIG_HMP_FREQUENCY_INVARIANT_SCALE */
+diff -Nur linux-3.10.30.orig/kernel/sched/sched.h linux-linaro-stable-mx6/kernel/sched/sched.h
+--- linux-3.10.30.orig/kernel/sched/sched.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/sched/sched.h 2014-05-15 20:34:17.090151400 +0200
+@@ -142,7 +142,7 @@
+
+ atomic_t load_weight;
+ atomic64_t load_avg;
+- atomic_t runnable_avg;
++ atomic_t runnable_avg, usage_avg;
+ #endif
+
+ #ifdef CONFIG_RT_GROUP_SCHED
+@@ -279,7 +279,7 @@
+ #endif /* CONFIG_FAIR_GROUP_SCHED */
+ /* These always depend on CONFIG_FAIR_GROUP_SCHED */
+ #ifdef CONFIG_FAIR_GROUP_SCHED
+- u32 tg_runnable_contrib;
++ u32 tg_runnable_contrib, tg_usage_contrib;
+ u64 tg_load_contrib;
+ #endif /* CONFIG_FAIR_GROUP_SCHED */
+
+@@ -464,6 +464,9 @@
+ int active_balance;
+ int push_cpu;
+ struct cpu_stop_work active_balance_work;
++#ifdef CONFIG_SCHED_HMP
++ struct task_struct *migrate_task;
++#endif
+ /* cpu of this runqueue: */
+ int cpu;
+ int online;
+@@ -642,6 +645,12 @@
+
+ extern int group_balance_cpu(struct sched_group *sg);
+
++#ifdef CONFIG_SCHED_HMP
++static LIST_HEAD(hmp_domains);
++DECLARE_PER_CPU(struct hmp_domain *, hmp_cpu_domain);
++#define hmp_cpu_domain(cpu) (per_cpu(hmp_cpu_domain, (cpu)))
++#endif /* CONFIG_SCHED_HMP */
++
+ #endif /* CONFIG_SMP */
+
+ #include "stats.h"
+diff -Nur linux-3.10.30.orig/kernel/smp.c linux-linaro-stable-mx6/kernel/smp.c
+--- linux-3.10.30.orig/kernel/smp.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/smp.c 2014-05-15 20:34:17.090151400 +0200
+@@ -12,6 +12,8 @@
+ #include <linux/gfp.h>
+ #include <linux/smp.h>
+ #include <linux/cpu.h>
++#define CREATE_TRACE_POINTS
++#include <trace/events/smp.h>
+
+ #include "smpboot.h"
+
+@@ -159,8 +161,10 @@
+ * locking and barrier primitives. Generic code isn't really
+ * equipped to do the right thing...
+ */
+- if (ipi)
++ if (ipi) {
++ trace_smp_call_func_send(csd->func, cpu);
+ arch_send_call_function_single_ipi(cpu);
++ }
+
+ if (wait)
+ csd_lock_wait(csd);
+@@ -197,8 +201,9 @@
+ * so save them away before making the call:
+ */
+ csd_flags = csd->flags;
+-
++ trace_smp_call_func_entry(csd->func);
+ csd->func(csd->info);
++ trace_smp_call_func_exit(csd->func);
+
+ /*
+ * Unlocked CSDs are valid through generic_exec_single():
+@@ -228,6 +233,7 @@
+ int this_cpu;
+ int err = 0;
+
++ trace_smp_call_func_send(func, cpu);
+ /*
+ * prevent preemption and reschedule on another processor,
+ * as well as CPU removal
+@@ -245,7 +251,9 @@
+
+ if (cpu == this_cpu) {
+ local_irq_save(flags);
++ trace_smp_call_func_entry(func);
+ func(info);
++ trace_smp_call_func_exit(func);
+ local_irq_restore(flags);
+ } else {
+ if ((unsigned)cpu < nr_cpu_ids && cpu_online(cpu)) {
+diff -Nur linux-3.10.30.orig/kernel/workqueue.c linux-linaro-stable-mx6/kernel/workqueue.c
+--- linux-3.10.30.orig/kernel/workqueue.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/kernel/workqueue.c 2014-05-15 20:34:17.134151717 +0200
+@@ -272,6 +272,15 @@
+ static bool wq_disable_numa;
+ module_param_named(disable_numa, wq_disable_numa, bool, 0444);
+
++/* see the comment above the definition of WQ_POWER_EFFICIENT */
++#ifdef CONFIG_WQ_POWER_EFFICIENT_DEFAULT
++static bool wq_power_efficient = true;
++#else
++static bool wq_power_efficient;
++#endif
++
++module_param_named(power_efficient, wq_power_efficient, bool, 0444);
++
+ static bool wq_numa_enabled; /* unbound NUMA affinity enabled */
+
+ /* buf for wq_update_unbound_numa_attrs(), protected by CPU hotplug exclusion */
+@@ -308,6 +317,10 @@
+ EXPORT_SYMBOL_GPL(system_unbound_wq);
+ struct workqueue_struct *system_freezable_wq __read_mostly;
+ EXPORT_SYMBOL_GPL(system_freezable_wq);
++struct workqueue_struct *system_power_efficient_wq __read_mostly;
++EXPORT_SYMBOL_GPL(system_power_efficient_wq);
++struct workqueue_struct *system_freezable_power_efficient_wq __read_mostly;
++EXPORT_SYMBOL_GPL(system_freezable_power_efficient_wq);
+
+ static int worker_thread(void *__worker);
+ static void copy_workqueue_attrs(struct workqueue_attrs *to,
+@@ -4117,6 +4130,10 @@
+ struct workqueue_struct *wq;
+ struct pool_workqueue *pwq;
+
++ /* see the comment above the definition of WQ_POWER_EFFICIENT */
++ if ((flags & WQ_POWER_EFFICIENT) && wq_power_efficient)
++ flags |= WQ_UNBOUND;
++
+ /* allocate wq and format name */
+ if (flags & WQ_UNBOUND)
+ tbl_size = wq_numa_tbl_len * sizeof(wq->numa_pwq_tbl[0]);
+@@ -5026,8 +5043,15 @@
+ WQ_UNBOUND_MAX_ACTIVE);
+ system_freezable_wq = alloc_workqueue("events_freezable",
+ WQ_FREEZABLE, 0);
++ system_power_efficient_wq = alloc_workqueue("events_power_efficient",
++ WQ_POWER_EFFICIENT, 0);
++ system_freezable_power_efficient_wq = alloc_workqueue("events_freezable_power_efficient",
++ WQ_FREEZABLE | WQ_POWER_EFFICIENT,
++ 0);
+ BUG_ON(!system_wq || !system_highpri_wq || !system_long_wq ||
+- !system_unbound_wq || !system_freezable_wq);
++ !system_unbound_wq || !system_freezable_wq ||
++ !system_power_efficient_wq ||
++ !system_freezable_power_efficient_wq);
+ return 0;
+ }
+ early_initcall(init_workqueues);
+diff -Nur linux-3.10.30.orig/lib/genalloc.c linux-linaro-stable-mx6/lib/genalloc.c
+--- linux-3.10.30.orig/lib/genalloc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/lib/genalloc.c 2014-05-15 20:34:17.254152582 +0200
+@@ -313,6 +313,34 @@
+ EXPORT_SYMBOL(gen_pool_alloc);
+
+ /**
++ * gen_pool_dma_alloc - allocate special memory from the pool for DMA usage
++ * @pool: pool to allocate from
++ * @size: number of bytes to allocate from the pool
++ * @dma: dma-view physical address
++ *
++ * Allocate the requested number of bytes from the specified pool.
++ * Uses the pool allocation function (with first-fit algorithm by default).
++ * Can not be used in NMI handler on architectures without
++ * NMI-safe cmpxchg implementation.
++ */
++void *gen_pool_dma_alloc(struct gen_pool *pool, size_t size, dma_addr_t *dma)
++{
++ unsigned long vaddr;
++
++ if (!pool)
++ return NULL;
++
++ vaddr = gen_pool_alloc(pool, size);
++ if (!vaddr)
++ return NULL;
++
++ *dma = gen_pool_virt_to_phys(pool, vaddr);
++
++ return (void *)vaddr;
++}
++EXPORT_SYMBOL(gen_pool_dma_alloc);
++
++/**
+ * gen_pool_free - free allocated special memory back to the pool
+ * @pool: pool to free to
+ * @addr: starting address of memory to free back to pool
+diff -Nur linux-3.10.30.orig/linaro/configs/android.conf linux-linaro-stable-mx6/linaro/configs/android.conf
+--- linux-3.10.30.orig/linaro/configs/android.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/android.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,40 @@
++CONFIG_IPV6=y
++# CONFIG_IPV6_SIT is not set
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_HAS_WAKELOCK=y
++CONFIG_WAKELOCK=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_DM_CRYPT=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_ANDROID_PARANOID_NETWORK=y
++CONFIG_NET_ACTIVITY_STATS=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_UINPUT=y
++CONFIG_INPUT_GPIO=y
++CONFIG_USB_G_ANDROID=y
++CONFIG_SWITCH=y
++CONFIG_STAGING=y
++CONFIG_ANDROID=y
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ASHMEM=y
++CONFIG_ANDROID_LOGGER=y
++CONFIG_ANDROID_TIMED_OUTPUT=y
++CONFIG_ANDROID_TIMED_GPIO=y
++CONFIG_ANDROID_LOW_MEMORY_KILLER=y
++CONFIG_ANDROID_INTF_ALARM_DEV=y
++CONFIG_CRYPTO_TWOFISH=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_RAM_SIZE=16384
++CONFIG_FUSE_FS=y
++CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_ION=y
++CONFIG_SYNC=y
++CONFIG_SW_SYNC=y
++CONFIG_SW_SYNC_USER=y
++CONFIG_ION_TEST=y
++CONFIG_ADF=y
++CONFIG_ADF_FBDEV=y
++CONFIG_ADF_MEMBLOCK=y
++CONFIG_DMA_SHARED_BUFFER=y
+diff -Nur linux-3.10.30.orig/linaro/configs/arndale.conf linux-linaro-stable-mx6/linaro/configs/arndale.conf
+--- linux-3.10.30.orig/linaro/configs/arndale.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/arndale.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,66 @@
++CONFIG_KALLSYMS_ALL=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_BSD_DISKLABEL=y
++CONFIG_SOLARIS_X86_PARTITION=y
++CONFIG_ARCH_EXYNOS=y
++CONFIG_S3C_LOWLEVEL_UART_PORT=2
++CONFIG_ARCH_EXYNOS5=y
++# CONFIG_EXYNOS_ATAGS is not set
++CONFIG_MACH_EXYNOS4_DT=y
++CONFIG_VMSPLIT_2G=y
++CONFIG_NR_CPUS=2
++CONFIG_HIGHMEM=y
++# CONFIG_COMPACTION is not set
++CONFIG_ARM_APPENDED_DTB=y
++CONFIG_ARM_ATAG_DTB_COMPAT=y
++CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init= mem=256M"
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_PM_RUNTIME=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_CHR_DEV_SG=y
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_SATA_EXYNOS=y
++CONFIG_AX88796=y
++CONFIG_AX88796_93CX6=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_SAMSUNG=y
++CONFIG_SERIAL_SAMSUNG_CONSOLE=y
++CONFIG_HW_RANDOM=y
++CONFIG_I2C=y
++CONFIG_I2C_S3C2410=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_EXYNOS_THERMAL=y
++CONFIG_MFD_SEC_CORE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_S5M8767=y
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_EXYNOS=y
++CONFIG_DRM_EXYNOS_DMABUF=y
++CONFIG_DRM_EXYNOS_HDMI=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_LOGO=y
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_IDMAC=y
++CONFIG_MMC_DW_EXYNOS=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_S3C=y
++CONFIG_DEBUG_KERNEL=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_DEBUG_RT_MUTEXES=y
++CONFIG_DEBUG_SPINLOCK=y
++CONFIG_DEBUG_INFO=y
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++CONFIG_DEBUG_USER=y
++CONFIG_TUN=y
+diff -Nur linux-3.10.30.orig/linaro/configs/big-LITTLE-IKS.conf linux-linaro-stable-mx6/linaro/configs/big-LITTLE-IKS.conf
+--- linux-3.10.30.orig/linaro/configs/big-LITTLE-IKS.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/big-LITTLE-IKS.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,5 @@
++CONFIG_BIG_LITTLE=y
++CONFIG_BL_SWITCHER=y
++CONFIG_ARM_DT_BL_CPUFREQ=y
++CONFIG_ARM_VEXPRESS_BL_CPUFREQ=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
+diff -Nur linux-3.10.30.orig/linaro/configs/big-LITTLE-MP.conf linux-linaro-stable-mx6/linaro/configs/big-LITTLE-MP.conf
+--- linux-3.10.30.orig/linaro/configs/big-LITTLE-MP.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/big-LITTLE-MP.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,12 @@
++CONFIG_CGROUPS=y
++CONFIG_CGROUP_SCHED=y
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_NO_HZ=y
++CONFIG_SCHED_MC=y
++CONFIG_DISABLE_CPU_SCHED_DOMAIN_BALANCE=y
++CONFIG_SCHED_HMP=y
++CONFIG_HMP_FAST_CPU_MASK=""
++CONFIG_HMP_SLOW_CPU_MASK=""
++CONFIG_HMP_VARIABLE_SCALE=y
++CONFIG_HMP_FREQUENCY_INVARIANT_SCALE=y
++CONFIG_SCHED_HMP_LITTLE_PACKING=y
+diff -Nur linux-3.10.30.orig/linaro/configs/debug.conf linux-linaro-stable-mx6/linaro/configs/debug.conf
+--- linux-3.10.30.orig/linaro/configs/debug.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/debug.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1 @@
++CONFIG_PROVE_LOCKING=y
+diff -Nur linux-3.10.30.orig/linaro/configs/distribution.conf linux-linaro-stable-mx6/linaro/configs/distribution.conf
+--- linux-3.10.30.orig/linaro/configs/distribution.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/distribution.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,44 @@
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_CGROUPS=y
++# CONFIG_COMPAT_BRK is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
++CONFIG_SECCOMP=y
++CONFIG_CC_STACKPROTECTOR=y
++CONFIG_SYN_COOKIES=y
++CONFIG_IPV6=y
++CONFIG_NETLABEL=y
++CONFIG_BRIDGE_NETFILTER=y
++CONFIG_NF_CONNTRACK=m
++CONFIG_NETFILTER_XT_CONNMARK=m
++CONFIG_NETFILTER_XT_MARK=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NF_CONNTRACK_IPV4=m
++CONFIG_NF_NAT_IPV4=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_NF_CONNTRACK_IPV6=m
++CONFIG_NF_NAT_IPV6=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_BRIDGE_NF_EBTABLES=m
++CONFIG_BRIDGE_EBT_MARK_T=m
++CONFIG_BRIDGE=m
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_UINPUT=y
++# CONFIG_DEVKMEM is not set
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_AUTOFS4_FS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_STRICT_DEVMEM=y
++CONFIG_SECURITY=y
++CONFIG_LSM_MMAP_MIN_ADDR=0
++CONFIG_SECURITY_SELINUX=y
++CONFIG_SECURITY_SMACK=y
++CONFIG_SECURITY_APPARMOR=y
++CONFIG_DEFAULT_SECURITY_APPARMOR=y
+diff -Nur linux-3.10.30.orig/linaro/configs/highbank.conf linux-linaro-stable-mx6/linaro/configs/highbank.conf
+--- linux-3.10.30.orig/linaro/configs/highbank.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/highbank.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,40 @@
++CONFIG_EXPERIMENTAL=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_ARCH_HIGHBANK=y
++CONFIG_ARM_ERRATA_754322=y
++CONFIG_SMP=y
++CONFIG_SCHED_MC=y
++CONFIG_AEABI=y
++CONFIG_CMDLINE="console=ttyAMA0"
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_NET=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_SATA_HIGHBANK=y
++CONFIG_NETDEVICES=y
++CONFIG_NET_CALXEDA_XGMAC=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_IPMI_HANDLER=y
++CONFIG_IPMI_SI=y
++CONFIG_I2C=y
++CONFIG_I2C_DESIGNWARE_PLATFORM=y
++CONFIG_SPI=y
++CONFIG_SPI_PL022=y
++CONFIG_GPIO_PL061=y
++CONFIG_MMC=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_EDAC=y
++CONFIG_EDAC_MM_EDAC=y
++CONFIG_EDAC_HIGHBANK_MC=y
++CONFIG_EDAC_HIGHBANK_L2=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_PL031=y
++CONFIG_DMADEVICES=y
++CONFIG_PL330_DMA=y
+diff -Nur linux-3.10.30.orig/linaro/configs/kvm-guest.conf linux-linaro-stable-mx6/linaro/configs/kvm-guest.conf
+--- linux-3.10.30.orig/linaro/configs/kvm-guest.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/kvm-guest.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,11 @@
++CONFIG_BALLOON_COMPACTION=y
++CONFIG_VIRTIO_BLK=y
++CONFIG_VIRTIO_NET=y
++CONFIG_HVC_DRIVER=y
++CONFIG_VIRTIO_CONSOLE=y
++CONFIG_VIRTIO=y
++CONFIG_VIRTIO_BALLOON=y
++CONFIG_VIRTIO_MMIO=y
++CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
++CONFIG_VIRTUALIZATION=y
++# CONFIG_THUMB2_KERNEL is not set
+diff -Nur linux-3.10.30.orig/linaro/configs/kvm-host.conf linux-linaro-stable-mx6/linaro/configs/kvm-host.conf
+--- linux-3.10.30.orig/linaro/configs/kvm-host.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/kvm-host.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,11 @@
++CONFIG_VIRTUALIZATION=y
++CONFIG_ARM_LPAE=y
++CONFIG_ARM_VIRT_EXT=y
++CONFIG_HAVE_KVM_IRQCHIP=y
++CONFIG_KVM_ARM_HOST=y
++CONFIG_KVM_ARM_MAX_VCPUS=4
++CONFIG_KVM_ARM_TIMER=y
++CONFIG_KVM_ARM_VGIC=y
++CONFIG_KVM_MMIO=y
++CONFIG_KVM=y
++CONFIG_BLK_DEV_NBD=m
+diff -Nur linux-3.10.30.orig/linaro/configs/linaro-base.conf linux-linaro-stable-mx6/linaro/configs/linaro-base.conf
+--- linux-3.10.30.orig/linaro/configs/linaro-base.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/linaro-base.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,94 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=16
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EMBEDDED=y
++CONFIG_HOTPLUG=y
++CONFIG_PERF_EVENTS=y
++CONFIG_SLAB=y
++CONFIG_PROFILING=y
++CONFIG_OPROFILE=y
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_SMP=y
++CONFIG_SCHED_MC=y
++CONFIG_SCHED_SMT=y
++CONFIG_THUMB2_KERNEL=y
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
++CONFIG_CPU_IDLE=y
++CONFIG_BINFMT_MISC=y
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=y
++CONFIG_NET_KEY_MIGRATE=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++CONFIG_IP_PNP_BOOTP=y
++CONFIG_IP_PNP_RARP=y
++# CONFIG_INET_LRO is not set
++CONFIG_NETFILTER=y
++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
++CONFIG_CONNECTOR=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_OOPS=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_NAND=y
++CONFIG_NETDEVICES=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT4_FS=y
++CONFIG_BTRFS_FS=y
++CONFIG_QUOTA=y
++CONFIG_QFMT_V2=y
++CONFIG_MSDOS_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_ECRYPT_FS=y
++CONFIG_JFFS2_FS=y
++CONFIG_JFFS2_SUMMARY=y
++CONFIG_JFFS2_FS_XATTR=y
++CONFIG_JFFS2_COMPRESSION_OPTIONS=y
++CONFIG_JFFS2_LZO=y
++CONFIG_JFFS2_RUBIN=y
++CONFIG_CRAMFS=y
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V2 is not set
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_PRINTK_TIME=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_SCHEDSTATS=y
++CONFIG_TIMER_STATS=y
++CONFIG_KEYS=y
++CONFIG_CRYPTO_MICHAEL_MIC=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC_ITU_T=y
++CONFIG_CRC7=y
++CONFIG_HW_PERF_EVENTS=y
++CONFIG_FUNCTION_TRACER=y
++CONFIG_ENABLE_DEFAULT_TRACERS=y
++CONFIG_PROC_DEVICETREE=y
+diff -Nur linux-3.10.30.orig/linaro/configs/omap4.conf linux-linaro-stable-mx6/linaro/configs/omap4.conf
+--- linux-3.10.30.orig/linaro/configs/omap4.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/omap4.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,194 @@
++CONFIG_EXPERT=y
++CONFIG_KPROBES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_FORCE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_GPIO_PCA953X=y
++CONFIG_OMAP_RESET_CLOCKS=y
++CONFIG_OMAP_MUX_DEBUG=y
++CONFIG_ARCH_OMAP2PLUS=y
++CONFIG_SOC_OMAP5=y
++# CONFIG_ARCH_OMAP2 is not set
++CONFIG_ARCH_VEXPRESS_CA9X4=y
++CONFIG_ARM_THUMBEE=y
++CONFIG_ARM_ERRATA_411920=y
++CONFIG_NR_CPUS=2
++CONFIG_ZBOOT_ROM_TEXT=0x0
++CONFIG_ZBOOT_ROM_BSS=0x0
++CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
++CONFIG_KEXEC=y
++CONFIG_PM_DEBUG=y
++CONFIG_CAN=m
++CONFIG_CAN_C_CAN=m
++CONFIG_CAN_C_CAN_PLATFORM=m
++CONFIG_BT=m
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_H4=y
++CONFIG_BT_HCIUART_BCSP=y
++CONFIG_BT_HCIUART_LL=y
++CONFIG_BT_HCIBCM203X=m
++CONFIG_BT_HCIBPA10X=m
++CONFIG_CFG80211=m
++CONFIG_MAC80211=m
++CONFIG_MAC80211_RC_PID=y
++CONFIG_MAC80211_RC_DEFAULT_PID=y
++CONFIG_CMA=y
++CONFIG_MTD_NAND_OMAP2=y
++CONFIG_MTD_ONENAND=y
++CONFIG_MTD_ONENAND_VERIFY_WRITE=y
++CONFIG_MTD_ONENAND_OMAP2=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM_SIZE=16384
++CONFIG_SENSORS_TSL2550=m
++CONFIG_SENSORS_LIS3_I2C=m
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_SCAN_ASYNC=y
++CONFIG_KS8851=y
++CONFIG_KS8851_MLL=y
++CONFIG_SMC91X=y
++CONFIG_SMSC911X=y
++CONFIG_TI_CPSW=y
++CONFIG_SMSC_PHY=y
++CONFIG_USB_USBNET=y
++CONFIG_USB_NET_SMSC95XX=y
++CONFIG_USB_ALI_M5632=y
++CONFIG_USB_AN2720=y
++CONFIG_USB_EPSON2888=y
++CONFIG_USB_KC2190=y
++CONFIG_LIBERTAS=m
++CONFIG_LIBERTAS_USB=m
++CONFIG_LIBERTAS_SDIO=m
++CONFIG_LIBERTAS_DEBUG=y
++CONFIG_INPUT_JOYDEV=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_MATRIX=m
++CONFIG_KEYBOARD_TWL4030=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_ADS7846=y
++CONFIG_INPUT_TWL4030_PWRBUTTON=y
++CONFIG_VT_HW_CONSOLE_BINDING=y
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_DETECT_IRQ=y
++CONFIG_SERIAL_8250_RSA=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_OMAP=y
++CONFIG_SERIAL_OMAP_CONSOLE=y
++CONFIG_HW_RANDOM=y
++CONFIG_I2C_CHARDEV=y
++CONFIG_SPI=y
++CONFIG_SPI_OMAP24XX=y
++CONFIG_PINCTRL_SINGLE=y
++CONFIG_DEBUG_GPIO=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_GPIO_TWL4030=y
++CONFIG_W1=y
++CONFIG_SENSORS_LM75=m
++CONFIG_WATCHDOG=y
++CONFIG_OMAP_WATCHDOG=y
++CONFIG_TWL4030_WATCHDOG=y
++CONFIG_MFD_TPS65217=y
++CONFIG_MFD_TPS65910=y
++CONFIG_TWL6040_CORE=y
++CONFIG_REGULATOR_TPS65023=y
++CONFIG_REGULATOR_TPS6507X=y
++CONFIG_REGULATOR_TPS65217=y
++CONFIG_REGULATOR_TPS65910=y
++CONFIG_REGULATOR_TWL4030=y
++CONFIG_FB=y
++CONFIG_FIRMWARE_EDID=y
++CONFIG_FB_MODE_HELPERS=y
++CONFIG_FB_TILEBLITTING=y
++CONFIG_OMAP2_DSS=m
++CONFIG_OMAP2_DSS_RFBI=y
++CONFIG_OMAP2_DSS_SDI=y
++CONFIG_OMAP2_DSS_DSI=y
++CONFIG_FB_OMAP2=m
++CONFIG_PANEL_GENERIC_DPI=m
++CONFIG_PANEL_TFP410=m
++CONFIG_PANEL_SHARP_LS037V7DW01=m
++CONFIG_PANEL_NEC_NL8048HL11_01B=m
++CONFIG_PANEL_TAAL=m
++CONFIG_PANEL_TPO_TD043MTEA1=m
++CONFIG_PANEL_ACX565AKM=m
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_LCD_PLATFORM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_VERBOSE_PRINTK=y
++CONFIG_SND_DEBUG=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=m
++CONFIG_SND_OMAP_SOC=m
++CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
++CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
++CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
++CONFIG_USB=y
++CONFIG_USB_DEBUG=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_MON=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_WDM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_TEST=y
++CONFIG_USB_PHY=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DEBUG=y
++CONFIG_USB_GADGET_DEBUG_FILES=y
++CONFIG_USB_GADGET_DEBUG_FS=y
++CONFIG_USB_ZERO=m
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_SDIO_UART=y
++CONFIG_MMC_ARMMMCI=y
++CONFIG_MMC_OMAP=y
++CONFIG_MMC_OMAP_HS=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_TWL92330=y
++CONFIG_RTC_DRV_TWL4030=y
++CONFIG_RTC_DRV_OMAP=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_OMAP=y
++# CONFIG_EXT3_FS_XATTR is not set
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++# CONFIG_DEBUG_BUGVERBOSE is not set
++CONFIG_DEBUG_INFO=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_LIBCRC32C=y
++# CONFIG_CPU_FREQ is not set
+diff -Nur linux-3.10.30.orig/linaro/configs/ubuntu-minimal.conf linux-linaro-stable-mx6/linaro/configs/ubuntu-minimal.conf
+--- linux-3.10.30.orig/linaro/configs/ubuntu-minimal.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/ubuntu-minimal.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1,44 @@
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_CGROUPS=y
++# CONFIG_COMPAT_BRK is not set
++CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
++CONFIG_SECCOMP=y
++CONFIG_CC_STACKPROTECTOR=y
++CONFIG_SYN_COOKIES=y
++CONFIG_IPV6=y
++CONFIG_NETLABEL=y
++CONFIG_BRIDGE_NETFILTER=y
++CONFIG_NF_CONNTRACK=m
++CONFIG_NETFILTER_XT_CONNMARK=m
++CONFIG_NETFILTER_XT_MARK=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NF_CONNTRACK_IPV4=m
++CONFIG_NF_NAT_IPV4=m
++CONFIG_IP_NF_IPTABLES=m
++CONFIG_IP_NF_FILTER=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_NF_CONNTRACK_IPV6=m
++CONFIG_NF_NAT_IPV6=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_BRIDGE_NF_EBTABLES=m
++CONFIG_BRIDGE_EBT_MARK_T=m
++CONFIG_BRIDGE=m
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_UINPUT=y
++# CONFIG_DEVKMEM is not set
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_AUTOFS4_FS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_STRICT_DEVMEM=y
++CONFIG_SECURITY=y
++CONFIG_LSM_MMAP_MIN_ADDR=0
++CONFIG_SECURITY_SELINUX=y
++CONFIG_SECURITY_SMACK=y
++CONFIG_SECURITY_APPARMOR=y
++CONFIG_DEFAULT_SECURITY_APPARMOR=y
+diff -Nur linux-3.10.30.orig/linaro/configs/vexpress64.conf linux-linaro-stable-mx6/linaro/configs/vexpress64.conf
+--- linux-3.10.30.orig/linaro/configs/vexpress64.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/vexpress64.conf 2014-05-15 20:34:17.646155404 +0200
+@@ -0,0 +1,32 @@
++CONFIG_ARCH_VEXPRESS=y
++CONFIG_SMP=y
++CONFIG_NR_CPUS=8
++CONFIG_CMDLINE="console=ttyAMA0"
++CONFIG_COMPAT=y
++CONFIG_SMC91X=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_SERIO_AMBAKMI=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++# CONFIG_SERIO_I8042 is not set
++CONFIG_FB=y
++CONFIG_FB_ARMCLCD=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++# CONFIG_VGA_CONSOLE is not set
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_MMC=y
++CONFIG_MMC_ARMMMCI=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_PL031=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_VIRTIO=y
++CONFIG_VIRTIO_BLK=y
++CONFIG_VIRTIO_MMIO=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
+diff -Nur linux-3.10.30.orig/linaro/configs/vexpress.conf linux-linaro-stable-mx6/linaro/configs/vexpress.conf
+--- linux-3.10.30.orig/linaro/configs/vexpress.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/vexpress.conf 2014-05-15 20:34:17.646155404 +0200
+@@ -0,0 +1,63 @@
++CONFIG_ARCH_VEXPRESS=y
++CONFIG_ARCH_VEXPRESS_CA9X4=y
++CONFIG_BIG_LITTLE=y
++CONFIG_ARCH_VEXPRESS_TC2=y
++CONFIG_ARCH_VEXPRESS_DCSCB=y
++CONFIG_ARM_VEXPRESS_BL_CPUFREQ=y
++CONFIG_PM_OPP=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_ARM_PSCI=y
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_NR_CPUS=8
++CONFIG_HIGHMEM=y
++CONFIG_HIGHPTE=y
++CONFIG_CMDLINE="console=ttyAMA0,38400n8 root=/dev/mmcblk0p2 rootwait mmci.fmax=4000000"
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++CONFIG_SMSC911X=y
++CONFIG_SMC91X=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_SERIO_AMBAKMI=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_FB=y
++CONFIG_FB_ARMCLCD=y
++CONFIG_FB_ARMHDLCD=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_ARMAACI=y
++CONFIG_USB=y
++CONFIG_USB_ISP1760_HCD=y
++CONFIG_USB_STORAGE=y
++CONFIG_MMC=y
++CONFIG_MMC_ARMMMCI=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_PL031=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_VEXPRESS_CONFIG=y
++CONFIG_SENSORS_VEXPRESS=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_VEXPRESS=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_VIRTIO=y
++CONFIG_VIRTIO_BLK=y
++CONFIG_VIRTIO_MMIO=y
++CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+diff -Nur linux-3.10.30.orig/linaro/configs/vexpress-tuning.conf linux-linaro-stable-mx6/linaro/configs/vexpress-tuning.conf
+--- linux-3.10.30.orig/linaro/configs/vexpress-tuning.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/vexpress-tuning.conf 2014-05-15 20:34:17.638155346 +0200
+@@ -0,0 +1 @@
++# CONFIG_PROVE_LOCKING is not set
+diff -Nur linux-3.10.30.orig/linaro/configs/xen.conf linux-linaro-stable-mx6/linaro/configs/xen.conf
+--- linux-3.10.30.orig/linaro/configs/xen.conf 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/linaro/configs/xen.conf 2014-05-15 20:34:17.646155404 +0200
+@@ -0,0 +1,7 @@
++CONFIG_XEN=y
++CONFIG_XEN_NETDEV_FRONTEND=y
++CONFIG_XEN_NETDEV_BACKEND=y
++CONFIG_XEN_BLKDEV_FRONTEND=y
++CONFIG_XEN_BLKDEV_BACKEND=y
++CONFIG_XENFS=y
++CONFIG_XEN_COMPAT_XENFS=y
+diff -Nur linux-3.10.30.orig/mm/Kconfig linux-linaro-stable-mx6/mm/Kconfig
+--- linux-3.10.30.orig/mm/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/mm/Kconfig 2014-05-15 20:34:17.646155404 +0200
+@@ -477,3 +477,28 @@
+ and swap data is stored as normal on the matching swap device.
+
+ If unsure, say Y to enable frontswap.
++
++config ZBUD
++ tristate "Buddy allocator for compressed pages"
++ default n
++ help
++ zbud is an special purpose allocator for storing compressed pages.
++ It is designed to store up to two compressed pages per physical page.
++ While this design limits storage density, it has simple and
++ deterministic reclaim properties that make it preferable to a higher
++ density approach when reclaim will be used.
++
++config ZSWAP
++ bool "In-kernel swap page compression"
++ depends on FRONTSWAP && CRYPTO
++ select CRYPTO_LZO
++ select ZBUD
++ default n
++ help
++ Zswap is a backend for the frontswap mechanism in the VMM.
++ It receives pages from frontswap and attempts to store them
++ in a compressed memory pool, resulting in an effective
++ partial memory reclaim. In addition, pages and be retrieved
++ from this compressed store much faster than most tradition
++ swap devices resulting in reduced I/O and faster performance
++ for many workloads.
+diff -Nur linux-3.10.30.orig/mm/Makefile linux-linaro-stable-mx6/mm/Makefile
+--- linux-3.10.30.orig/mm/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/mm/Makefile 2014-05-15 20:34:17.646155404 +0200
+@@ -32,6 +32,7 @@
+ obj-$(CONFIG_BOUNCE) += bounce.o
+ obj-$(CONFIG_SWAP) += page_io.o swap_state.o swapfile.o
+ obj-$(CONFIG_FRONTSWAP) += frontswap.o
++obj-$(CONFIG_ZSWAP) += zswap.o
+ obj-$(CONFIG_HAS_DMA) += dmapool.o
+ obj-$(CONFIG_HUGETLBFS) += hugetlb.o
+ obj-$(CONFIG_NUMA) += mempolicy.o
+@@ -58,3 +59,4 @@
+ obj-$(CONFIG_DEBUG_KMEMLEAK_TEST) += kmemleak-test.o
+ obj-$(CONFIG_CLEANCACHE) += cleancache.o
+ obj-$(CONFIG_MEMORY_ISOLATION) += page_isolation.o
++obj-$(CONFIG_ZBUD) += zbud.o
+diff -Nur linux-3.10.30.orig/mm/vmstat.c linux-linaro-stable-mx6/mm/vmstat.c
+--- linux-3.10.30.orig/mm/vmstat.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/mm/vmstat.c 2014-05-15 20:34:17.774156326 +0200
+@@ -14,6 +14,7 @@
+ #include <linux/module.h>
+ #include <linux/slab.h>
+ #include <linux/cpu.h>
++#include <linux/cpumask.h>
+ #include <linux/vmstat.h>
+ #include <linux/sched.h>
+ #include <linux/math64.h>
+@@ -432,11 +433,12 @@
+ * with the global counters. These could cause remote node cache line
+ * bouncing and will have to be only done when necessary.
+ */
+-void refresh_cpu_vm_stats(int cpu)
++bool refresh_cpu_vm_stats(int cpu)
+ {
+ struct zone *zone;
+ int i;
+ int global_diff[NR_VM_ZONE_STAT_ITEMS] = { 0, };
++ bool vm_activity = false;
+
+ for_each_populated_zone(zone) {
+ struct per_cpu_pageset *p;
+@@ -483,14 +485,21 @@
+ if (p->expire)
+ continue;
+
+- if (p->pcp.count)
++ if (p->pcp.count) {
++ vm_activity = true;
+ drain_zone_pages(zone, &p->pcp);
++ }
+ #endif
+ }
+
+ for (i = 0; i < NR_VM_ZONE_STAT_ITEMS; i++)
+- if (global_diff[i])
++ if (global_diff[i]) {
+ atomic_long_add(global_diff[i], &vm_stat[i]);
++ vm_activity = true;
++ }
++
++ return vm_activity;
++
+ }
+
+ /*
+@@ -1175,22 +1184,72 @@
+ #ifdef CONFIG_SMP
+ static DEFINE_PER_CPU(struct delayed_work, vmstat_work);
+ int sysctl_stat_interval __read_mostly = HZ;
++static struct cpumask vmstat_off_cpus;
++struct delayed_work vmstat_monitor_work;
+
+-static void vmstat_update(struct work_struct *w)
++static inline bool need_vmstat(int cpu)
+ {
+- refresh_cpu_vm_stats(smp_processor_id());
+- schedule_delayed_work(&__get_cpu_var(vmstat_work),
+- round_jiffies_relative(sysctl_stat_interval));
++ struct zone *zone;
++ int i;
++
++ for_each_populated_zone(zone) {
++ struct per_cpu_pageset *p;
++
++ p = per_cpu_ptr(zone->pageset, cpu);
++
++ for (i = 0; i < NR_VM_ZONE_STAT_ITEMS; i++)
++ if (p->vm_stat_diff[i])
++ return true;
++
++ if (zone_to_nid(zone) != numa_node_id() && p->pcp.count)
++ return true;
++ }
++
++ return false;
+ }
+
+-static void __cpuinit start_cpu_timer(int cpu)
++static void vmstat_update(struct work_struct *w);
++
++static void start_cpu_timer(int cpu)
+ {
+ struct delayed_work *work = &per_cpu(vmstat_work, cpu);
+
+- INIT_DEFERRABLE_WORK(work, vmstat_update);
++ cpumask_clear_cpu(cpu, &vmstat_off_cpus);
+ schedule_delayed_work_on(cpu, work, __round_jiffies_relative(HZ, cpu));
+ }
+
++static void __cpuinit setup_cpu_timer(int cpu)
++{
++ struct delayed_work *work = &per_cpu(vmstat_work, cpu);
++
++ INIT_DEFERRABLE_WORK(work, vmstat_update);
++ start_cpu_timer(cpu);
++}
++
++static void vmstat_update_monitor(struct work_struct *w)
++{
++ int cpu;
++
++ for_each_cpu_and(cpu, &vmstat_off_cpus, cpu_online_mask)
++ if (need_vmstat(cpu))
++ start_cpu_timer(cpu);
++
++ queue_delayed_work(system_unbound_wq, &vmstat_monitor_work,
++ round_jiffies_relative(sysctl_stat_interval));
++}
++
++
++static void vmstat_update(struct work_struct *w)
++{
++ int cpu = smp_processor_id();
++
++ if (likely(refresh_cpu_vm_stats(cpu)))
++ schedule_delayed_work(&__get_cpu_var(vmstat_work),
++ round_jiffies_relative(sysctl_stat_interval));
++ else
++ cpumask_set_cpu(cpu, &vmstat_off_cpus);
++}
++
+ /*
+ * Use the cpu notifier to insure that the thresholds are recalculated
+ * when necessary.
+@@ -1205,17 +1264,19 @@
+ case CPU_ONLINE:
+ case CPU_ONLINE_FROZEN:
+ refresh_zone_stat_thresholds();
+- start_cpu_timer(cpu);
++ setup_cpu_timer(cpu);
+ node_set_state(cpu_to_node(cpu), N_CPU);
+ break;
+ case CPU_DOWN_PREPARE:
+ case CPU_DOWN_PREPARE_FROZEN:
+- cancel_delayed_work_sync(&per_cpu(vmstat_work, cpu));
+- per_cpu(vmstat_work, cpu).work.func = NULL;
++ if (!cpumask_test_cpu(cpu, &vmstat_off_cpus)) {
++ cancel_delayed_work_sync(&per_cpu(vmstat_work, cpu));
++ per_cpu(vmstat_work, cpu).work.func = NULL;
++ }
+ break;
+ case CPU_DOWN_FAILED:
+ case CPU_DOWN_FAILED_FROZEN:
+- start_cpu_timer(cpu);
++ setup_cpu_timer(cpu);
+ break;
+ case CPU_DEAD:
+ case CPU_DEAD_FROZEN:
+@@ -1238,8 +1299,14 @@
+
+ register_cpu_notifier(&vmstat_notifier);
+
++ INIT_DEFERRABLE_WORK(&vmstat_monitor_work,
++ vmstat_update_monitor);
++ queue_delayed_work(system_unbound_wq,
++ &vmstat_monitor_work,
++ round_jiffies_relative(HZ));
++
+ for_each_online_cpu(cpu)
+- start_cpu_timer(cpu);
++ setup_cpu_timer(cpu);
+ #endif
+ #ifdef CONFIG_PROC_FS
+ proc_create("buddyinfo", S_IRUGO, NULL, &fragmentation_file_operations);
+diff -Nur linux-3.10.30.orig/mm/zbud.c linux-linaro-stable-mx6/mm/zbud.c
+--- linux-3.10.30.orig/mm/zbud.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/mm/zbud.c 2014-05-15 20:34:17.786156413 +0200
+@@ -0,0 +1,564 @@
++/*
++ * zbud.c - Buddy Allocator for Compressed Pages
++ *
++ * Copyright (C) 2013, Seth Jennings, IBM
++ *
++ * Concepts based on zcache internal zbud allocator by Dan Magenheimer.
++ *
++ * zbud is an special purpose allocator for storing compressed pages. It is
++ * designed to store up to two compressed pages per physical page. While this
++ * design limits storage density, it has simple and deterministic reclaim
++ * properties that make it preferable to a higher density approach when reclaim
++ * will be used.
++ *
++ * zbud works by storing compressed pages, or "zpages", together in pairs in a
++ * single memory page called a "zbud page". The first buddy is "left
++ * justifed" at the beginning of the zbud page, and the last buddy is "right
++ * justified" at the end of the zbud page. The benefit is that if either
++ * buddy is freed, the freed buddy space, coalesced with whatever slack space
++ * that existed between the buddies, results in the largest possible free region
++ * within the zbud page.
++ *
++ * zbud also provides an attractive lower bound on density. The ratio of zpages
++ * to zbud pages can not be less than 1. This ensures that zbud can never "do
++ * harm" by using more pages to store zpages than the uncompressed zpages would
++ * have used on their own.
++ *
++ * zbud pages are divided into "chunks". The size of the chunks is fixed at
++ * compile time and determined by NCHUNKS_ORDER below. Dividing zbud pages
++ * into chunks allows organizing unbuddied zbud pages into a manageable number
++ * of unbuddied lists according to the number of free chunks available in the
++ * zbud page.
++ *
++ * The zbud API differs from that of conventional allocators in that the
++ * allocation function, zbud_alloc(), returns an opaque handle to the user,
++ * not a dereferenceable pointer. The user must map the handle using
++ * zbud_map() in order to get a usable pointer by which to access the
++ * allocation data and unmap the handle with zbud_unmap() when operations
++ * on the allocation data are complete.
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/atomic.h>
++#include <linux/list.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/preempt.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/zbud.h>
++
++/*****************
++ * Structures
++*****************/
++/**
++ * struct zbud_page - zbud page metadata overlay
++ * <at> page: typed reference to the underlying struct page
++ * <at> donotuse: this overlays the page flags and should not be used
++ * <at> first_chunks: the size of the first buddy in chunks, 0 if free
++ * <at> last_chunks: the size of the last buddy in chunks, 0 if free
++ * <at> buddy: links the zbud page into the unbuddied/buddied lists in the pool
++ * <at> lru: links the zbud page into the lru list in the pool
++ *
++ * This structure overlays the struct page to store metadata needed for a
++ * single storage page in for zbud. There is a BUILD_BUG_ON in zbud_init()
++ * that ensures this structure is not larger that struct page.
++ *
++ * The PG_reclaim flag of the underlying page is used for indicating
++ * that this zbud page is under reclaim (see zbud_reclaim_page())
++ */
++struct zbud_page {
++ union {
++ struct page page;
++ struct {
++ unsigned long donotuse;
++ u16 first_chunks;
++ u16 last_chunks;
++ struct list_head buddy;
++ struct list_head lru;
++ };
++ };
++};
++
++/*
++ * NCHUNKS_ORDER determines the internal allocation granularity, effectively
++ * adjusting internal fragmentation. It also determines the number of
++ * freelists maintained in each pool. NCHUNKS_ORDER of 6 means that the
++ * allocation granularity will be in chunks of size PAGE_SIZE/64, and there
++ * will be 64 freelists per pool.
++ */
++#define NCHUNKS_ORDER 6
++
++#define CHUNK_SHIFT (PAGE_SHIFT - NCHUNKS_ORDER)
++#define CHUNK_SIZE (1 << CHUNK_SHIFT)
++#define NCHUNKS (PAGE_SIZE >> CHUNK_SHIFT)
++
++/**
++ * struct zbud_pool - stores metadata for each zbud pool
++ * <at> lock: protects all pool lists and first|last_chunk fields of any
++ * zbud page in the pool
++ * <at> unbuddied: array of lists tracking zbud pages that only contain one buddy;
++ * the lists each zbud page is added to depends on the size of
++ * its free region.
++ * <at> buddied: list tracking the zbud pages that contain two buddies;
++ * these zbud pages are full
++ * <at> pages_nr: number of zbud pages in the pool.
++ * <at> ops: pointer to a structure of user defined operations specified at
++ * pool creation time.
++ *
++ * This structure is allocated at pool creation time and maintains metadata
++ * pertaining to a particular zbud pool.
++ */
++struct zbud_pool {
++ spinlock_t lock;
++ struct list_head unbuddied[NCHUNKS];
++ struct list_head buddied;
++ struct list_head lru;
++ atomic_t pages_nr;
++ struct zbud_ops *ops;
++};
++
++/*****************
++ * Helpers
++*****************/
++/* Just to make the code easier to read */
++enum buddy {
++ FIRST,
++ LAST
++};
++
++/* Converts an allocation size in bytes to size in zbud chunks */
++static inline int size_to_chunks(int size)
++{
++ return (size + CHUNK_SIZE - 1) >> CHUNK_SHIFT;
++}
++
++#define for_each_unbuddied_list(_iter, _begin) \
++ for ((_iter) = (_begin); (_iter) < NCHUNKS; (_iter)++)
++
++/* Initializes a zbud page from a newly allocated page */
++static inline struct zbud_page *init_zbud_page(struct page *page)
++{
++ struct zbud_page *zbpage = (struct zbud_page *)page;
++ zbpage->first_chunks = 0;
++ zbpage->last_chunks = 0;
++ INIT_LIST_HEAD(&zbpage->buddy);
++ INIT_LIST_HEAD(&zbpage->lru);
++ return zbpage;
++}
++
++/* Resets a zbud page so that it can be properly freed */
++static inline struct page *reset_zbud_page(struct zbud_page *zbpage)
++{
++ struct page *page = &zbpage->page;
++ set_page_private(page, 0);
++ page->mapping = NULL;
++ page->index = 0;
++ page_mapcount_reset(page);
++ init_page_count(page);
++ INIT_LIST_HEAD(&page->lru);
++ return page;
++}
++
++/*
++ * Encodes the handle of a particular buddy within a zbud page
++ * Pool lock should be held as this function accesses first|last_chunks
++ */
++static inline unsigned long encode_handle(struct zbud_page *zbpage,
++ enum buddy bud)
++{
++ unsigned long handle;
++
++ /*
++ * For now, the encoded handle is actually just the pointer to the data
++ * but this might not always be the case. A little information hiding.
++ */
++ handle = (unsigned long)page_address(&zbpage->page);
++ if (bud == FIRST)
++ return handle;
++ handle += PAGE_SIZE - (zbpage->last_chunks << CHUNK_SHIFT);
++ return handle;
++}
++
++/* Returns the zbud page where a given handle is stored */
++static inline struct zbud_page *handle_to_zbud_page(unsigned long handle)
++{
++ return (struct zbud_page *)(virt_to_page(handle));
++}
++
++/* Returns the number of free chunks in a zbud page */
++static inline int num_free_chunks(struct zbud_page *zbpage)
++{
++ /*
++ * Rather than branch for different situations, just use the fact that
++ * free buddies have a length of zero to simplify everything.
++ */
++ return NCHUNKS - zbpage->first_chunks - zbpage->last_chunks;
++}
++
++/*****************
++ * API Functions
++*****************/
++/**
++ * zbud_create_pool() - create a new zbud pool
++ * <at> gfp: gfp flags when allocating the zbud pool structure
++ * <at> ops: user-defined operations for the zbud pool
++ *
++ * Return: pointer to the new zbud pool or NULL if the metadata allocation
++ * failed.
++ */
++struct zbud_pool *zbud_create_pool(gfp_t gfp, struct zbud_ops *ops)
++{
++ struct zbud_pool *pool;
++ int i;
++
++ pool = kmalloc(sizeof(struct zbud_pool), gfp);
++ if (!pool)
++ return NULL;
++ spin_lock_init(&pool->lock);
++ for_each_unbuddied_list(i, 0)
++ INIT_LIST_HEAD(&pool->unbuddied[i]);
++ INIT_LIST_HEAD(&pool->buddied);
++ INIT_LIST_HEAD(&pool->lru);
++ atomic_set(&pool->pages_nr, 0);
++ pool->ops = ops;
++ return pool;
++}
++EXPORT_SYMBOL_GPL(zbud_create_pool);
++
++/**
++ * zbud_destroy_pool() - destroys an existing zbud pool
++ * <at> pool: the zbud pool to be destroyed
++ */
++void zbud_destroy_pool(struct zbud_pool *pool)
++{
++ kfree(pool);
++}
++EXPORT_SYMBOL_GPL(zbud_destroy_pool);
++
++/**
++ * zbud_alloc() - allocates a region of a given size
++ * <at> pool: zbud pool from which to allocate
++ * <at> size: size in bytes of the desired allocation
++ * <at> gfp: gfp flags used if the pool needs to grow
++ * <at> handle: handle of the new allocation
++ *
++ * This function will attempt to find a free region in the pool large
++ * enough to satisfy the allocation request. First, it tries to use
++ * free space in the most recently used zbud page, at the beginning of
++ * the pool LRU list. If that zbud page is full or doesn't have the
++ * required free space, a best fit search of the unbuddied lists is
++ * performed. If no suitable free region is found, then a new page
++ * is allocated and added to the pool to satisfy the request.
++ *
++ * gfp should not set __GFP_HIGHMEM as highmem pages cannot be used
++ * as zbud pool pages.
++ *
++ * Return: 0 if success and handle is set, otherwise -EINVAL is the size or
++ * gfp arguments are invalid or -ENOMEM if the pool was unable to allocate
++ * a new page.
++ */
++int zbud_alloc(struct zbud_pool *pool, int size, gfp_t gfp,
++ unsigned long *handle)
++{
++ int chunks, i, freechunks;
++ struct zbud_page *zbpage = NULL;
++ enum buddy bud;
++ struct page *page;
++
++ if (size <= 0 || size > PAGE_SIZE || gfp & __GFP_HIGHMEM)
++ return -EINVAL;
++ chunks = size_to_chunks(size);
++ spin_lock(&pool->lock);
++
++ /*
++ * First, try to use the zbpage we last used (at the head of the
++ * LRU) to increase LRU locality of the buddies. This is first fit.
++ */
++ if (!list_empty(&pool->lru)) {
++ zbpage = list_first_entry(&pool->lru, struct zbud_page, lru);
++ if (num_free_chunks(zbpage) >= chunks) {
++ if (zbpage->first_chunks == 0) {
++ list_del(&zbpage->buddy);
++ bud = FIRST;
++ goto found;
++ }
++ if (zbpage->last_chunks == 0) {
++ list_del(&zbpage->buddy);
++ bud = LAST;
++ goto found;
++ }
++ }
++ }
++
++ /* Second, try to find an unbuddied zbpage. This is best fit. */
++ zbpage = NULL;
++ for_each_unbuddied_list(i, chunks) {
++ if (!list_empty(&pool->unbuddied[i])) {
++ zbpage = list_first_entry(&pool->unbuddied[i],
++ struct zbud_page, buddy);
++ list_del(&zbpage->buddy);
++ if (zbpage->first_chunks == 0)
++ bud = FIRST;
++ else
++ bud = LAST;
++ goto found;
++ }
++ }
++
++ /* Lastly, couldn't find unbuddied zbpage, create new one */
++ spin_unlock(&pool->lock);
++ page = alloc_page(gfp);
++ if (!page)
++ return -ENOMEM;
++ spin_lock(&pool->lock);
++ atomic_inc(&pool->pages_nr);
++ zbpage = init_zbud_page(page);
++ bud = FIRST;
++
++found:
++ if (bud == FIRST)
++ zbpage->first_chunks = chunks;
++ else
++ zbpage->last_chunks = chunks;
++
++ if (zbpage->first_chunks == 0 || zbpage->last_chunks == 0) {
++ /* Add to unbuddied list */
++ freechunks = num_free_chunks(zbpage);
++ list_add(&zbpage->buddy, &pool->unbuddied[freechunks]);
++ } else {
++ /* Add to buddied list */
++ list_add(&zbpage->buddy, &pool->buddied);
++ }
++
++ /* Add/move zbpage to beginning of LRU */
++ if (!list_empty(&zbpage->lru))
++ list_del(&zbpage->lru);
++ list_add(&zbpage->lru, &pool->lru);
++
++ *handle = encode_handle(zbpage, bud);
++ spin_unlock(&pool->lock);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(zbud_alloc);
++
++/**
++ * zbud_free() - frees the allocation associated with the given handle
++ * <at> pool: pool in which the allocation resided
++ * <at> handle: handle associated with the allocation returned by zbud_alloc()
++ *
++ * In the case that the zbud page in which the allocation resides is under
++ * reclaim, as indicated by the PG_reclaim flag being set, this function
++ * only sets the first|last_chunks to 0. The page is actually freed
++ * once both buddies are evicted (see zbud_reclaim_page() below).
++ */
++void zbud_free(struct zbud_pool *pool, unsigned long handle)
++{
++ struct zbud_page *zbpage;
++ int freechunks;
++
++ spin_lock(&pool->lock);
++ zbpage = handle_to_zbud_page(handle);
++
++ /* If first buddy, handle will be page aligned */
++ if (handle & ~PAGE_MASK)
++ zbpage->last_chunks = 0;
++ else
++ zbpage->first_chunks = 0;
++
++ if (PageReclaim(&zbpage->page)) {
++ /* zbpage is under reclaim, reclaim will free */
++ spin_unlock(&pool->lock);
++ return;
++ }
++
++ /* Remove from existing buddy list */
++ list_del(&zbpage->buddy);
++
++ if (zbpage->first_chunks == 0 && zbpage->last_chunks == 0) {
++ /* zbpage is empty, free */
++ list_del(&zbpage->lru);
++ __free_page(reset_zbud_page(zbpage));
++ atomic_dec(&pool->pages_nr);
++ } else {
++ /* Add to unbuddied list */
++ freechunks = num_free_chunks(zbpage);
++ list_add(&zbpage->buddy, &pool->unbuddied[freechunks]);
++ }
++
++ spin_unlock(&pool->lock);
++}
++EXPORT_SYMBOL_GPL(zbud_free);
++
++#define list_tail_entry(ptr, type, member) \
++ list_entry((ptr)->prev, type, member)
++
++/**
++ * zbud_reclaim_page() - evicts allocations from a pool page and frees it
++ * <at> pool: pool from which a page will attempt to be evicted
++ * <at> retires: number of pages on the LRU list for which eviction will
++ * be attempted before failing
++ *
++ * zbud reclaim is different from normal system reclaim in that the reclaim is
++ * done from the bottom, up. This is because only the bottom layer, zbud, has
++ * information on how the allocations are organized within each zbud page. This
++ * has the potential to create interesting locking situations between zbud and
++ * the user, however.
++ *
++ * To avoid these, this is how zbud_reclaim_page() should be called:
++
++ * The user detects a page should be reclaimed and calls zbud_reclaim_page().
++ * zbud_reclaim_page() will remove a zbud page from the pool LRU list and call
++ * the user-defined eviction handler with the pool and handle as arguments.
++ *
++ * If the handle can not be evicted, the eviction handler should return
++ * non-zero. zbud_reclaim_page() will add the zbud page back to the
++ * appropriate list and try the next zbud page on the LRU up to
++ * a user defined number of retries.
++ *
++ * If the handle is successfully evicted, the eviction handler should
++ * return 0 _and_ should have called zbud_free() on the handle. zbud_free()
++ * contains logic to delay freeing the page if the page is under reclaim,
++ * as indicated by the setting of the PG_reclaim flag on the underlying page.
++ *
++ * If all buddies in the zbud page are successfully evicted, then the
++ * zbud page can be freed.
++ *
++ * Returns: 0 if page is successfully freed, otherwise -EINVAL if there are
++ * no pages to evict or an eviction handler is not registered, -EAGAIN if
++ * the retry limit was hit.
++ */
++int zbud_reclaim_page(struct zbud_pool *pool, unsigned int retries)
++{
++ int i, ret, freechunks;
++ struct zbud_page *zbpage;
++ unsigned long first_handle = 0, last_handle = 0;
++
++ spin_lock(&pool->lock);
++ if (!pool->ops || !pool->ops->evict || list_empty(&pool->lru) ||
++ retries == 0) {
++ spin_unlock(&pool->lock);
++ return -EINVAL;
++ }
++ for (i = 0; i < retries; i++) {
++ zbpage = list_tail_entry(&pool->lru, struct zbud_page, lru);
++ list_del(&zbpage->lru);
++ list_del(&zbpage->buddy);
++ /* Protect zbpage against free */
++ SetPageReclaim(&zbpage->page);
++ /*
++ * We need encode the handles before unlocking, since we can
++ * race with free that will set (first|last)_chunks to 0
++ */
++ first_handle = 0;
++ last_handle = 0;
++ if (zbpage->first_chunks)
++ first_handle = encode_handle(zbpage, FIRST);
++ if (zbpage->last_chunks)
++ last_handle = encode_handle(zbpage, LAST);
++ spin_unlock(&pool->lock);
++
++ /* Issue the eviction callback(s) */
++ if (first_handle) {
++ ret = pool->ops->evict(pool, first_handle);
++ if (ret)
++ goto next;
++ }
++ if (last_handle) {
++ ret = pool->ops->evict(pool, last_handle);
++ if (ret)
++ goto next;
++ }
++next:
++ spin_lock(&pool->lock);
++ ClearPageReclaim(&zbpage->page);
++ if (zbpage->first_chunks == 0 && zbpage->last_chunks == 0) {
++ /*
++ * Both buddies are now free, free the zbpage and
++ * return success.
++ */
++ __free_page(reset_zbud_page(zbpage));
++ atomic_dec(&pool->pages_nr);
++ spin_unlock(&pool->lock);
++ return 0;
++ } else if (zbpage->first_chunks == 0 ||
++ zbpage->last_chunks == 0) {
++ /* add to unbuddied list */
++ freechunks = num_free_chunks(zbpage);
++ list_add(&zbpage->buddy, &pool->unbuddied[freechunks]);
++ } else {
++ /* add to buddied list */
++ list_add(&zbpage->buddy, &pool->buddied);
++ }
++
++ /* add to beginning of LRU */
++ list_add(&zbpage->lru, &pool->lru);
++ }
++ spin_unlock(&pool->lock);
++ return -EAGAIN;
++}
++EXPORT_SYMBOL_GPL(zbud_reclaim_page);
++
++/**
++ * zbud_map() - maps the allocation associated with the given handle
++ * <at> pool: pool in which the allocation resides
++ * <at> handle: handle associated with the allocation to be mapped
++ *
++ * While trivial for zbud, the mapping functions for others allocators
++ * implementing this allocation API could have more complex information encoded
++ * in the handle and could create temporary mappings to make the data
++ * accessible to the user.
++ *
++ * Returns: a pointer to the mapped allocation
++ */
++void *zbud_map(struct zbud_pool *pool, unsigned long handle)
++{
++ return (void *)(handle);
++}
++EXPORT_SYMBOL_GPL(zbud_map);
++
++/**
++ * zbud_unmap() - maps the allocation associated with the given handle
++ * <at> pool: pool in which the allocation resides
++ * <at> handle: handle associated with the allocation to be unmapped
++ */
++void zbud_unmap(struct zbud_pool *pool, unsigned long handle)
++{
++}
++EXPORT_SYMBOL_GPL(zbud_unmap);
++
++/**
++ * zbud_get_pool_size() - gets the zbud pool size in pages
++ * <at> pool: pool whose size is being queried
++ *
++ * Returns: size in pages of the given pool
++ */
++int zbud_get_pool_size(struct zbud_pool *pool)
++{
++ return atomic_read(&pool->pages_nr);
++}
++EXPORT_SYMBOL_GPL(zbud_get_pool_size);
++
++static int __init init_zbud(void)
++{
++ /* Make sure we aren't overflowing the underlying struct page */
++ BUILD_BUG_ON(sizeof(struct zbud_page) != sizeof(struct page));
++ /* Make sure we can represent any chunk offset with a u16 */
++ BUILD_BUG_ON(sizeof(u16) * BITS_PER_BYTE < PAGE_SHIFT - CHUNK_SHIFT);
++ pr_info("loaded\n");
++ return 0;
++}
++
++static void __exit exit_zbud(void)
++{
++ pr_info("unloaded\n");
++}
++
++module_init(init_zbud);
++module_exit(exit_zbud);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Seth Jennings <sjenning <at> linux.vnet.ibm.com>");
++MODULE_DESCRIPTION("Buddy Allocator for Compressed Pages");
+diff -Nur linux-3.10.30.orig/mm/zswap.c linux-linaro-stable-mx6/mm/zswap.c
+--- linux-3.10.30.orig/mm/zswap.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/mm/zswap.c 2014-05-15 20:34:17.786156413 +0200
+@@ -0,0 +1,952 @@
++/*
++ * zswap.c - zswap driver file
++ *
++ * zswap is a backend for frontswap that takes pages that are in the
++ * process of being swapped out and attempts to compress them and store
++ * them in a RAM-based memory pool. This results in a significant I/O
++ * reduction on the real swap device and, in the case of a slow swap
++ * device, can also improve workload performance.
++ *
++ * Copyright (C) 2012 Seth Jennings <sjenning <at> linux.vnet.ibm.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++*/
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/module.h>
++#include <linux/cpu.h>
++#include <linux/highmem.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++#include <linux/atomic.h>
++#include <linux/frontswap.h>
++#include <linux/rbtree.h>
++#include <linux/swap.h>
++#include <linux/crypto.h>
++#include <linux/mempool.h>
++#include <linux/zbud.h>
++
++#include <linux/mm_types.h>
++#include <linux/page-flags.h>
++#include <linux/swapops.h>
++#include <linux/writeback.h>
++#include <linux/pagemap.h>
++
++/*********************************
++* statistics
++**********************************/
++/* Number of memory pages used by the compressed pool */
++static atomic_t zswap_pool_pages = ATOMIC_INIT(0);
++/* The number of compressed pages currently stored in zswap */
++static atomic_t zswap_stored_pages = ATOMIC_INIT(0);
++
++/*
++ * The statistics below are not protected from concurrent access for
++ * performance reasons so they may not be a 100% accurate. However,
++ * they do provide useful information on roughly how many times a
++ * certain event is occurring.
++*/
++static u64 zswap_pool_limit_hit;
++static u64 zswap_written_back_pages;
++static u64 zswap_reject_reclaim_fail;
++static u64 zswap_reject_compress_poor;
++static u64 zswap_reject_alloc_fail;
++static u64 zswap_reject_kmemcache_fail;
++static u64 zswap_duplicate_entry;
++
++/*********************************
++* tunables
++**********************************/
++/* Enable/disable zswap (disabled by default, fixed at boot for now) */
++static bool zswap_enabled;
++module_param_named(enabled, zswap_enabled, bool, 0);
++
++/* Compressor to be used by zswap (fixed at boot for now) */
++#define ZSWAP_COMPRESSOR_DEFAULT "lzo"
++static char *zswap_compressor = ZSWAP_COMPRESSOR_DEFAULT;
++module_param_named(compressor, zswap_compressor, charp, 0);
++
++/* The maximum percentage of memory that the compressed pool can occupy */
++static unsigned int zswap_max_pool_percent = 20;
++module_param_named(max_pool_percent,
++ zswap_max_pool_percent, uint, 0644);
++
++/*
++ * Maximum compression ratio, as as percentage, for an acceptable
++ * compressed page. Any pages that do not compress by at least
++ * this ratio will be rejected.
++*/
++static unsigned int zswap_max_compression_ratio = 80;
++module_param_named(max_compression_ratio,
++ zswap_max_compression_ratio, uint, 0644);
++
++/*********************************
++* compression functions
++**********************************/
++/* per-cpu compression transforms */
++static struct crypto_comp * __percpu *zswap_comp_pcpu_tfms;
++
++enum comp_op {
++ ZSWAP_COMPOP_COMPRESS,
++ ZSWAP_COMPOP_DECOMPRESS
++};
++
++static int zswap_comp_op(enum comp_op op, const u8 *src, unsigned int slen,
++ u8 *dst, unsigned int *dlen)
++{
++ struct crypto_comp *tfm;
++ int ret;
++
++ tfm = *per_cpu_ptr(zswap_comp_pcpu_tfms, get_cpu());
++ switch (op) {
++ case ZSWAP_COMPOP_COMPRESS:
++ ret = crypto_comp_compress(tfm, src, slen, dst, dlen);
++ break;
++ case ZSWAP_COMPOP_DECOMPRESS:
++ ret = crypto_comp_decompress(tfm, src, slen, dst, dlen);
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ put_cpu();
++ return ret;
++}
++
++static int __init zswap_comp_init(void)
++{
++ if (!crypto_has_comp(zswap_compressor, 0, 0)) {
++ pr_info("%s compressor not available\n", zswap_compressor);
++ /* fall back to default compressor */
++ zswap_compressor = ZSWAP_COMPRESSOR_DEFAULT;
++ if (!crypto_has_comp(zswap_compressor, 0, 0))
++ /* can't even load the default compressor */
++ return -ENODEV;
++ }
++ pr_info("using %s compressor\n", zswap_compressor);
++
++ /* alloc percpu transforms */
++ zswap_comp_pcpu_tfms = alloc_percpu(struct crypto_comp *);
++ if (!zswap_comp_pcpu_tfms)
++ return -ENOMEM;
++ return 0;
++}
++
++static void zswap_comp_exit(void)
++{
++ /* free percpu transforms */
++ if (zswap_comp_pcpu_tfms)
++ free_percpu(zswap_comp_pcpu_tfms);
++}
++
++/*********************************
++* data structures
++**********************************/
++/*
++ * struct zswap_entry
++ *
++ * This structure contains the metadata for tracking a single compressed
++ * page within zswap.
++ *
++ * rbnode - links the entry into red-black tree for the appropriate swap type
++ * refcount - the number of outstanding reference to the entry. This is needed
++ * to protect against premature freeing of the entry by code
++ * concurent calls to load, invalidate, and writeback. The lock
++ * for the zswap_tree structure that contains the entry must
++ * be held while changing the refcount. Since the lock must
++ * be held, there is no reason to also make refcount atomic.
++ * type - the swap type for the entry. Used to map back to the zswap_tree
++ * structure that contains the entry.
++ * offset - the swap offset for the entry. Index into the red-black tree.
++ * handle - zsmalloc allocation handle that stores the compressed page data
++ * length - the length in bytes of the compressed page data. Needed during
++ * decompression
++ */
++struct zswap_entry {
++ struct rb_node rbnode;
++ pgoff_t offset;
++ int refcount;
++ unsigned int length;
++ unsigned long handle;
++};
++
++struct zswap_header {
++ swp_entry_t swpentry;
++};
++
++/*
++ * The tree lock in the zswap_tree struct protects a few things:
++ * - the rbtree
++ * - the refcount field of each entry in the tree
++ */
++struct zswap_tree {
++ struct rb_root rbroot;
++ spinlock_t lock;
++ struct zbud_pool *pool;
++ unsigned type;
++};
++
++static struct zswap_tree *zswap_trees[MAX_SWAPFILES];
++
++/*********************************
++* zswap entry functions
++**********************************/
++#define ZSWAP_KMEM_CACHE_NAME "zswap_entry_cache"
++static struct kmem_cache *zswap_entry_cache;
++
++static inline int zswap_entry_cache_create(void)
++{
++ zswap_entry_cache =
++ kmem_cache_create(ZSWAP_KMEM_CACHE_NAME,
++ sizeof(struct zswap_entry), 0, 0, NULL);
++ return (zswap_entry_cache == NULL);
++}
++
++static inline void zswap_entry_cache_destory(void)
++{
++ kmem_cache_destroy(zswap_entry_cache);
++}
++
++static inline struct zswap_entry *zswap_entry_cache_alloc(gfp_t gfp)
++{
++ struct zswap_entry *entry;
++ entry = kmem_cache_alloc(zswap_entry_cache, gfp);
++ if (!entry)
++ return NULL;
++ entry->refcount = 1;
++ return entry;
++}
++
++static inline void zswap_entry_cache_free(struct zswap_entry *entry)
++{
++ kmem_cache_free(zswap_entry_cache, entry);
++}
++
++static inline void zswap_entry_get(struct zswap_entry *entry)
++{
++ entry->refcount++;
++}
++
++static inline int zswap_entry_put(struct zswap_entry *entry)
++{
++ entry->refcount--;
++ return entry->refcount;
++}
++
++/*********************************
++* rbtree functions
++**********************************/
++static struct zswap_entry *zswap_rb_search(struct rb_root *root, pgoff_t offset)
++{
++ struct rb_node *node = root->rb_node;
++ struct zswap_entry *entry;
++
++ while (node) {
++ entry = rb_entry(node, struct zswap_entry, rbnode);
++ if (entry->offset > offset)
++ node = node->rb_left;
++ else if (entry->offset < offset)
++ node = node->rb_right;
++ else
++ return entry;
++ }
++ return NULL;
++}
++
++/*
++ * In the case that a entry with the same offset is found, it a pointer to
++ * the existing entry is stored in dupentry and the function returns -EEXIST
++*/
++static int zswap_rb_insert(struct rb_root *root, struct zswap_entry *entry,
++ struct zswap_entry **dupentry)
++{
++ struct rb_node **link = &root->rb_node, *parent = NULL;
++ struct zswap_entry *myentry;
++
++ while (*link) {
++ parent = *link;
++ myentry = rb_entry(parent, struct zswap_entry, rbnode);
++ if (myentry->offset > entry->offset)
++ link = &(*link)->rb_left;
++ else if (myentry->offset < entry->offset)
++ link = &(*link)->rb_right;
++ else {
++ *dupentry = myentry;
++ return -EEXIST;
++ }
++ }
++ rb_link_node(&entry->rbnode, parent, link);
++ rb_insert_color(&entry->rbnode, root);
++ return 0;
++}
++
++/*********************************
++* per-cpu code
++**********************************/
++static DEFINE_PER_CPU(u8 *, zswap_dstmem);
++
++static int __zswap_cpu_notifier(unsigned long action, unsigned long cpu)
++{
++ struct crypto_comp *tfm;
++ u8 *dst;
++
++ switch (action) {
++ case CPU_UP_PREPARE:
++ tfm = crypto_alloc_comp(zswap_compressor, 0, 0);
++ if (IS_ERR(tfm)) {
++ pr_err("can't allocate compressor transform\n");
++ return NOTIFY_BAD;
++ }
++ *per_cpu_ptr(zswap_comp_pcpu_tfms, cpu) = tfm;
++ dst = kmalloc(PAGE_SIZE * 2, GFP_KERNEL);
++ if (!dst) {
++ pr_err("can't allocate compressor buffer\n");
++ crypto_free_comp(tfm);
++ *per_cpu_ptr(zswap_comp_pcpu_tfms, cpu) = NULL;
++ return NOTIFY_BAD;
++ }
++ per_cpu(zswap_dstmem, cpu) = dst;
++ break;
++ case CPU_DEAD:
++ case CPU_UP_CANCELED:
++ tfm = *per_cpu_ptr(zswap_comp_pcpu_tfms, cpu);
++ if (tfm) {
++ crypto_free_comp(tfm);
++ *per_cpu_ptr(zswap_comp_pcpu_tfms, cpu) = NULL;
++ }
++ dst = per_cpu(zswap_dstmem, cpu);
++ kfree(dst);
++ per_cpu(zswap_dstmem, cpu) = NULL;
++ break;
++ default:
++ break;
++ }
++ return NOTIFY_OK;
++}
++
++static int zswap_cpu_notifier(struct notifier_block *nb,
++ unsigned long action, void *pcpu)
++{
++ unsigned long cpu = (unsigned long)pcpu;
++ return __zswap_cpu_notifier(action, cpu);
++}
++
++static struct notifier_block zswap_cpu_notifier_block = {
++ .notifier_call = zswap_cpu_notifier
++};
++
++static int zswap_cpu_init(void)
++{
++ unsigned long cpu;
++
++ get_online_cpus();
++ for_each_online_cpu(cpu)
++ if (__zswap_cpu_notifier(CPU_UP_PREPARE, cpu) != NOTIFY_OK)
++ goto cleanup;
++ register_cpu_notifier(&zswap_cpu_notifier_block);
++ put_online_cpus();
++ return 0;
++
++cleanup:
++ for_each_online_cpu(cpu)
++ __zswap_cpu_notifier(CPU_UP_CANCELED, cpu);
++ put_online_cpus();
++ return -ENOMEM;
++}
++
++/*********************************
++* helpers
++**********************************/
++static inline bool zswap_is_full(void)
++{
++ int pool_pages = atomic_read(&zswap_pool_pages);
++ return (totalram_pages * zswap_max_pool_percent / 100 < pool_pages);
++}
++
++/*
++ * Carries out the common pattern of freeing and entry's zsmalloc allocation,
++ * freeing the entry itself, and decrementing the number of stored pages.
++ */
++static void zswap_free_entry(struct zswap_tree *tree, struct zswap_entry *entry)
++{
++ zbud_free(tree->pool, entry->handle);
++ zswap_entry_cache_free(entry);
++ atomic_dec(&zswap_stored_pages);
++ atomic_set(&zswap_pool_pages, zbud_get_pool_size(tree->pool));
++}
++
++/*********************************
++* writeback code
++**********************************/
++/* return enum for zswap_get_swap_cache_page */
++enum zswap_get_swap_ret {
++ ZSWAP_SWAPCACHE_NEW,
++ ZSWAP_SWAPCACHE_EXIST,
++ ZSWAP_SWAPCACHE_NOMEM
++};
++
++/*
++ * zswap_get_swap_cache_page
++ *
++ * This is an adaption of read_swap_cache_async()
++ *
++ * This function tries to find a page with the given swap entry
++ * in the swapper_space address space (the swap cache). If the page
++ * is found, it is returned in retpage. Otherwise, a page is allocated,
++ * added to the swap cache, and returned in retpage.
++ *
++ * If success, the swap cache page is returned in retpage
++ * Returns 0 if page was already in the swap cache, page is not locked
++ * Returns 1 if the new page needs to be populated, page is locked
++ * Returns <0 on error
++ */
++static int zswap_get_swap_cache_page(swp_entry_t entry,
++ struct page **retpage)
++{
++ struct page *found_page, *new_page = NULL;
++ struct address_space *swapper_space = &swapper_spaces[swp_type(entry)];
++ int err;
++
++ *retpage = NULL;
++ do {
++ /*
++ * First check the swap cache. Since this is normally
++ * called after lookup_swap_cache() failed, re-calling
++ * that would confuse statistics.
++ */
++ found_page = find_get_page(swapper_space, entry.val);
++ if (found_page)
++ break;
++
++ /*
++ * Get a new page to read into from swap.
++ */
++ if (!new_page) {
++ new_page = alloc_page(GFP_KERNEL);
++ if (!new_page)
++ break; /* Out of memory */
++ }
++
++ /*
++ * call radix_tree_preload() while we can wait.
++ */
++ err = radix_tree_preload(GFP_KERNEL);
++ if (err)
++ break;
++
++ /*
++ * Swap entry may have been freed since our caller observed it.
++ */
++ err = swapcache_prepare(entry);
++ if (err == -EEXIST) { /* seems racy */
++ radix_tree_preload_end();
++ continue;
++ }
++ if (err) { /* swp entry is obsolete ? */
++ radix_tree_preload_end();
++ break;
++ }
++
++ /* May fail (-ENOMEM) if radix-tree node allocation failed. */
++ __set_page_locked(new_page);
++ SetPageSwapBacked(new_page);
++ err = __add_to_swap_cache(new_page, entry);
++ if (likely(!err)) {
++ radix_tree_preload_end();
++ lru_cache_add_anon(new_page);
++ *retpage = new_page;
++ return ZSWAP_SWAPCACHE_NEW;
++ }
++ radix_tree_preload_end();
++ ClearPageSwapBacked(new_page);
++ __clear_page_locked(new_page);
++ /*
++ * add_to_swap_cache() doesn't return -EEXIST, so we can safely
++ * clear SWAP_HAS_CACHE flag.
++ */
++ swapcache_free(entry, NULL);
++ } while (err != -ENOMEM);
++
++ if (new_page)
++ page_cache_release(new_page);
++ if (!found_page)
++ return ZSWAP_SWAPCACHE_NOMEM;
++ *retpage = found_page;
++ return ZSWAP_SWAPCACHE_EXIST;
++}
++
++/*
++ * Attempts to free and entry by adding a page to the swap cache,
++ * decompressing the entry data into the page, and issuing a
++ * bio write to write the page back to the swap device.
++ *
++ * This can be thought of as a "resumed writeback" of the page
++ * to the swap device. We are basically resuming the same swap
++ * writeback path that was intercepted with the frontswap_store()
++ * in the first place. After the page has been decompressed into
++ * the swap cache, the compressed version stored by zswap can be
++ * freed.
++ */
++static int zswap_writeback_entry(struct zbud_pool *pool, unsigned long handle)
++{
++ struct zswap_header *zhdr;
++ swp_entry_t swpentry;
++ struct zswap_tree *tree;
++ pgoff_t offset;
++ struct zswap_entry *entry;
++ struct page *page;
++ u8 *src, *dst;
++ unsigned int dlen;
++ int ret, refcount;
++ struct writeback_control wbc = {
++ .sync_mode = WB_SYNC_NONE,
++ };
++
++ /* extract swpentry from data */
++ zhdr = zbud_map(pool, handle);
++ swpentry = zhdr->swpentry; /* here */
++ zbud_unmap(pool, handle);
++ tree = zswap_trees[swp_type(swpentry)];
++ offset = swp_offset(swpentry);
++ BUG_ON(pool != tree->pool);
++
++ /* find and ref zswap entry */
++ spin_lock(&tree->lock);
++ entry = zswap_rb_search(&tree->rbroot, offset);
++ if (!entry) {
++ /* entry was invalidated */
++ spin_unlock(&tree->lock);
++ return 0;
++ }
++ zswap_entry_get(entry);
++ spin_unlock(&tree->lock);
++ BUG_ON(offset != entry->offset);
++
++ /* try to allocate swap cache page */
++ switch (zswap_get_swap_cache_page(swpentry, &page)) {
++ case ZSWAP_SWAPCACHE_NOMEM: /* no memory */
++ ret = -ENOMEM;
++ goto fail;
++
++ case ZSWAP_SWAPCACHE_EXIST: /* page is unlocked */
++ /* page is already in the swap cache, ignore for now */
++ page_cache_release(page);
++ ret = -EEXIST;
++ goto fail;
++
++ case ZSWAP_SWAPCACHE_NEW: /* page is locked */
++ /* decompress */
++ dlen = PAGE_SIZE;
++ src = (u8 *)zbud_map(tree->pool, entry->handle) +
++ sizeof(struct zswap_header);
++ dst = kmap_atomic(page);
++ ret = zswap_comp_op(ZSWAP_COMPOP_DECOMPRESS, src,
++ entry->length, dst, &dlen);
++ kunmap_atomic(dst);
++ zbud_unmap(tree->pool, entry->handle);
++ BUG_ON(ret);
++ BUG_ON(dlen != PAGE_SIZE);
++
++ /* page is up to date */
++ SetPageUptodate(page);
++ }
++
++ /* start writeback */
++ SetPageReclaim(page);
++ __swap_writepage(page, &wbc, end_swap_bio_write);
++ page_cache_release(page);
++ zswap_written_back_pages++;
++
++ spin_lock(&tree->lock);
++
++ /* drop local reference */
++ zswap_entry_put(entry);
++ /* drop the initial reference from entry creation */
++ refcount = zswap_entry_put(entry);
++
++ /*
++ * There are three possible values for refcount here:
++ * (1) refcount is 1, load is in progress, unlink from rbtree,
++ * load will free
++ * (2) refcount is 0, (normal case) entry is valid,
++ * remove from rbtree and free entry
++ * (3) refcount is -1, invalidate happened during writeback,
++ * free entry
++ */
++ if (refcount >= 0) {
++ /* no invalidate yet, remove from rbtree */
++ rb_erase(&entry->rbnode, &tree->rbroot);
++ }
++ spin_unlock(&tree->lock);
++ if (refcount <= 0) {
++ /* free the entry */
++ zswap_free_entry(tree, entry);
++ return 0;
++ }
++ return -EAGAIN;
++
++fail:
++ spin_lock(&tree->lock);
++ zswap_entry_put(entry);
++ spin_unlock(&tree->lock);
++ return ret;
++}
++
++/*********************************
++* frontswap hooks
++**********************************/
++/* attempts to compress and store an single page */
++static int zswap_frontswap_store(unsigned type, pgoff_t offset,
++ struct page *page)
++{
++ struct zswap_tree *tree = zswap_trees[type];
++ struct zswap_entry *entry, *dupentry;
++ int ret;
++ unsigned int dlen = PAGE_SIZE, len;
++ unsigned long handle;
++ char *buf;
++ u8 *src, *dst;
++ struct zswap_header *zhdr;
++
++ if (!tree) {
++ ret = -ENODEV;
++ goto reject;
++ }
++
++ /* reclaim space if needed */
++ if (zswap_is_full()) {
++ zswap_pool_limit_hit++;
++ if (zbud_reclaim_page(tree->pool, 8)) {
++ zswap_reject_reclaim_fail++;
++ ret = -ENOMEM;
++ goto reject;
++ }
++ }
++
++ /* allocate entry */
++ entry = zswap_entry_cache_alloc(GFP_KERNEL);
++ if (!entry) {
++ zswap_reject_kmemcache_fail++;
++ ret = -ENOMEM;
++ goto reject;
++ }
++
++ /* compress */
++ dst = get_cpu_var(zswap_dstmem);
++ src = kmap_atomic(page);
++ ret = zswap_comp_op(ZSWAP_COMPOP_COMPRESS, src, PAGE_SIZE, dst, &dlen);
++ kunmap_atomic(src);
++ if (ret) {
++ ret = -EINVAL;
++ goto freepage;
++ }
++ len = dlen + sizeof(struct zswap_header);
++ if ((len * 100 / PAGE_SIZE) > zswap_max_compression_ratio) {
++ zswap_reject_compress_poor++;
++ ret = -E2BIG;
++ goto freepage;
++ }
++
++ /* store */
++ ret = zbud_alloc(tree->pool, len, __GFP_NORETRY | __GFP_NOWARN,
++ &handle);
++ if (ret) {
++ zswap_reject_alloc_fail++;
++ goto freepage;
++ }
++ zhdr = zbud_map(tree->pool, handle);
++ zhdr->swpentry = swp_entry(type, offset);
++ buf = (u8 *)(zhdr + 1);
++ memcpy(buf, dst, dlen);
++ zbud_unmap(tree->pool, handle);
++ put_cpu_var(zswap_dstmem);
++
++ /* populate entry */
++ entry->offset = offset;
++ entry->handle = handle;
++ entry->length = dlen;
++
++ /* map */
++ spin_lock(&tree->lock);
++ do {
++ ret = zswap_rb_insert(&tree->rbroot, entry, &dupentry);
++ if (ret == -EEXIST) {
++ zswap_duplicate_entry++;
++ /* remove from rbtree */
++ rb_erase(&dupentry->rbnode, &tree->rbroot);
++ if (!zswap_entry_put(dupentry)) {
++ /* free */
++ zswap_free_entry(tree, dupentry);
++ }
++ }
++ } while (ret == -EEXIST);
++ spin_unlock(&tree->lock);
++
++ /* update stats */
++ atomic_inc(&zswap_stored_pages);
++ atomic_set(&zswap_pool_pages, zbud_get_pool_size(tree->pool));
++
++ return 0;
++
++freepage:
++ put_cpu_var(zswap_dstmem);
++ zswap_entry_cache_free(entry);
++reject:
++ return ret;
++}
++
++/*
++ * returns 0 if the page was successfully decompressed
++ * return -1 on entry not found or error
++*/
++static int zswap_frontswap_load(unsigned type, pgoff_t offset,
++ struct page *page)
++{
++ struct zswap_tree *tree = zswap_trees[type];
++ struct zswap_entry *entry;
++ u8 *src, *dst;
++ unsigned int dlen;
++ int refcount, ret;
++
++ /* find */
++ spin_lock(&tree->lock);
++ entry = zswap_rb_search(&tree->rbroot, offset);
++ if (!entry) {
++ /* entry was written back */
++ spin_unlock(&tree->lock);
++ return -1;
++ }
++ zswap_entry_get(entry);
++ spin_unlock(&tree->lock);
++
++ /* decompress */
++ dlen = PAGE_SIZE;
++ src = (u8 *)zbud_map(tree->pool, entry->handle) +
++ sizeof(struct zswap_header);
++ dst = kmap_atomic(page);
++ ret = zswap_comp_op(ZSWAP_COMPOP_DECOMPRESS, src, entry->length,
++ dst, &dlen);
++ kunmap_atomic(dst);
++ zbud_unmap(tree->pool, entry->handle);
++ BUG_ON(ret);
++
++ spin_lock(&tree->lock);
++ refcount = zswap_entry_put(entry);
++ if (likely(refcount)) {
++ spin_unlock(&tree->lock);
++ return 0;
++ }
++ spin_unlock(&tree->lock);
++
++ /*
++ * We don't have to unlink from the rbtree because
++ * zswap_writeback_entry() or zswap_frontswap_invalidate page()
++ * has already done this for us if we are the last reference.
++ */
++ /* free */
++
++ zswap_free_entry(tree, entry);
++
++ return 0;
++}
++
++/* invalidates a single page */
++static void zswap_frontswap_invalidate_page(unsigned type, pgoff_t offset)
++{
++ struct zswap_tree *tree = zswap_trees[type];
++ struct zswap_entry *entry;
++ int refcount;
++
++ /* find */
++ spin_lock(&tree->lock);
++ entry = zswap_rb_search(&tree->rbroot, offset);
++ if (!entry) {
++ /* entry was written back */
++ spin_unlock(&tree->lock);
++ return;
++ }
++
++ /* remove from rbtree */
++ rb_erase(&entry->rbnode, &tree->rbroot);
++
++ /* drop the initial reference from entry creation */
++ refcount = zswap_entry_put(entry);
++
++ spin_unlock(&tree->lock);
++
++ if (refcount) {
++ /* writeback in progress, writeback will free */
++ return;
++ }
++
++ /* free */
++ zswap_free_entry(tree, entry);
++}
++
++/* invalidates all pages for the given swap type */
++static void zswap_frontswap_invalidate_area(unsigned type)
++{
++ struct zswap_tree *tree = zswap_trees[type];
++ struct rb_node *node;
++ struct zswap_entry *entry;
++
++ if (!tree)
++ return;
++
++ /* walk the tree and free everything */
++ spin_lock(&tree->lock);
++ /*
++ * TODO: Even though this code should not be executed because
++ * the try_to_unuse() in swapoff should have emptied the tree,
++ * it is very wasteful to rebalance the tree after every
++ * removal when we are freeing the whole tree.
++ *
++ * If post-order traversal code is ever added to the rbtree
++ * implementation, it should be used here.
++ */
++ while ((node = rb_first(&tree->rbroot))) {
++ entry = rb_entry(node, struct zswap_entry, rbnode);
++ rb_erase(&entry->rbnode, &tree->rbroot);
++ zbud_free(tree->pool, entry->handle);
++ zswap_entry_cache_free(entry);
++ atomic_dec(&zswap_stored_pages);
++ }
++ tree->rbroot = RB_ROOT;
++ spin_unlock(&tree->lock);
++}
++
++static struct zbud_ops zswap_zbud_ops = {
++ .evict = zswap_writeback_entry
++};
++
++/* NOTE: this is called in atomic context from swapon and must not sleep */
++static void zswap_frontswap_init(unsigned type)
++{
++ struct zswap_tree *tree;
++
++ tree = kzalloc(sizeof(struct zswap_tree), GFP_ATOMIC);
++ if (!tree)
++ goto err;
++ tree->pool = zbud_create_pool(GFP_NOWAIT, &zswap_zbud_ops);
++ if (!tree->pool)
++ goto freetree;
++ tree->rbroot = RB_ROOT;
++ spin_lock_init(&tree->lock);
++ tree->type = type;
++ zswap_trees[type] = tree;
++ return;
++
++freetree:
++ kfree(tree);
++err:
++ pr_err("alloc failed, zswap disabled for swap type %d\n", type);
++}
++
++static struct frontswap_ops zswap_frontswap_ops = {
++ .store = zswap_frontswap_store,
++ .load = zswap_frontswap_load,
++ .invalidate_page = zswap_frontswap_invalidate_page,
++ .invalidate_area = zswap_frontswap_invalidate_area,
++ .init = zswap_frontswap_init
++};
++
++/*********************************
++* debugfs functions
++**********************************/
++#ifdef CONFIG_DEBUG_FS
++#include <linux/debugfs.h>
++
++static struct dentry *zswap_debugfs_root;
++
++static int __init zswap_debugfs_init(void)
++{
++ if (!debugfs_initialized())
++ return -ENODEV;
++
++ zswap_debugfs_root = debugfs_create_dir("zswap", NULL);
++ if (!zswap_debugfs_root)
++ return -ENOMEM;
++
++ debugfs_create_u64("pool_limit_hit", S_IRUGO,
++ zswap_debugfs_root, &zswap_pool_limit_hit);
++ debugfs_create_u64("reject_reclaim_fail", S_IRUGO,
++ zswap_debugfs_root, &zswap_reject_reclaim_fail);
++ debugfs_create_u64("reject_alloc_fail", S_IRUGO,
++ zswap_debugfs_root, &zswap_reject_alloc_fail);
++ debugfs_create_u64("reject_kmemcache_fail", S_IRUGO,
++ zswap_debugfs_root, &zswap_reject_kmemcache_fail);
++ debugfs_create_u64("reject_compress_poor", S_IRUGO,
++ zswap_debugfs_root, &zswap_reject_compress_poor);
++ debugfs_create_u64("written_back_pages", S_IRUGO,
++ zswap_debugfs_root, &zswap_written_back_pages);
++ debugfs_create_u64("duplicate_entry", S_IRUGO,
++ zswap_debugfs_root, &zswap_duplicate_entry);
++ debugfs_create_atomic_t("pool_pages", S_IRUGO,
++ zswap_debugfs_root, &zswap_pool_pages);
++ debugfs_create_atomic_t("stored_pages", S_IRUGO,
++ zswap_debugfs_root, &zswap_stored_pages);
++
++ return 0;
++}
++
++static void __exit zswap_debugfs_exit(void)
++{
++ debugfs_remove_recursive(zswap_debugfs_root);
++}
++#else
++static inline int __init zswap_debugfs_init(void)
++{
++ return 0;
++}
++
++static inline void __exit zswap_debugfs_exit(void) { }
++#endif
++
++/*********************************
++* module init and exit
++**********************************/
++static int __init init_zswap(void)
++{
++ if (!zswap_enabled)
++ return 0;
++
++ pr_info("loading zswap\n");
++ if (zswap_entry_cache_create()) {
++ pr_err("entry cache creation failed\n");
++ goto error;
++ }
++ if (zswap_comp_init()) {
++ pr_err("compressor initialization failed\n");
++ goto compfail;
++ }
++ if (zswap_cpu_init()) {
++ pr_err("per-cpu initialization failed\n");
++ goto pcpufail;
++ }
++ frontswap_register_ops(&zswap_frontswap_ops);
++ if (zswap_debugfs_init())
++ pr_warn("debugfs initialization failed\n");
++ return 0;
++pcpufail:
++ zswap_comp_exit();
++compfail:
++ zswap_entry_cache_destory();
++error:
++ return -ENOMEM;
++}
++/* must be late so crypto has time to come up */
++late_initcall(init_zswap);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Seth Jennings <sjenning <at> linux.vnet.ibm.com>");
++MODULE_DESCRIPTION("Compressed cache for swap pages");
+diff -Nur linux-3.10.30.orig/sound/core/memalloc.c linux-linaro-stable-mx6/sound/core/memalloc.c
+--- linux-3.10.30.orig/sound/core/memalloc.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/core/memalloc.c 2014-05-15 20:34:21.794185273 +0200
+@@ -30,6 +30,7 @@
+ #include <linux/seq_file.h>
+ #include <asm/uaccess.h>
+ #include <linux/dma-mapping.h>
++#include <linux/genalloc.h>
+ #include <linux/moduleparam.h>
+ #include <linux/mutex.h>
+ #include <sound/memalloc.h>
+@@ -157,6 +158,44 @@
+ dec_snd_pages(pg);
+ dma_free_coherent(dev, PAGE_SIZE << pg, ptr, dma);
+ }
++
++#ifdef CONFIG_GENERIC_ALLOCATOR
++/**
++ * snd_malloc_dev_iram - allocate memory from on-chip internal ram
++ * @dmab: buffer allocation record to store the allocated data
++ * @size: number of bytes to allocate from the iram
++ *
++ * This function requires iram phandle provided via of_node
++ */
++void snd_malloc_dev_iram(struct snd_dma_buffer *dmab, size_t size)
++{
++ struct device *dev = dmab->dev.dev;
++ struct gen_pool *pool = NULL;
++
++ if (dev->of_node)
++ pool = of_get_named_gen_pool(dev->of_node, "iram", 0);
++
++ if (!pool)
++ return;
++
++ /* Assign the pool into private_data field */
++ dmab->private_data = pool;
++
++ dmab->area = gen_pool_dma_alloc(pool, size, &dmab->addr);
++}
++
++/**
++ * snd_free_dev_iram - free allocated specific memory from on-chip internal ram
++ * @dmab: buffer allocation record to store the allocated data
++ */
++void snd_free_dev_iram(struct snd_dma_buffer *dmab)
++{
++ struct gen_pool *pool = dmab->private_data;
++
++ if (pool && dmab->area)
++ gen_pool_free(pool, (unsigned long)dmab->area, dmab->bytes);
++}
++#endif /* CONFIG_GENERIC_ALLOCATOR */
+ #endif /* CONFIG_HAS_DMA */
+
+ /*
+@@ -197,6 +236,16 @@
+ dmab->addr = 0;
+ break;
+ #ifdef CONFIG_HAS_DMA
++#ifdef CONFIG_GENERIC_ALLOCATOR
++ case SNDRV_DMA_TYPE_DEV_IRAM:
++ snd_malloc_dev_iram(dmab, size);
++ if (dmab->area)
++ break;
++ /* Internal memory might have limited size and no enough space,
++ * so if we fail to malloc, try to fetch memory traditionally.
++ */
++ dmab->dev.type = SNDRV_DMA_TYPE_DEV;
++#endif /* CONFIG_GENERIC_ALLOCATOR */
+ case SNDRV_DMA_TYPE_DEV:
+ dmab->area = snd_malloc_dev_pages(device, size, &dmab->addr);
+ break;
+@@ -269,6 +318,11 @@
+ snd_free_pages(dmab->area, dmab->bytes);
+ break;
+ #ifdef CONFIG_HAS_DMA
++#ifdef CONFIG_GENERIC_ALLOCATOR
++ case SNDRV_DMA_TYPE_DEV_IRAM:
++ snd_free_dev_iram(dmab);
++ break;
++#endif /* CONFIG_GENERIC_ALLOCATOR */
+ case SNDRV_DMA_TYPE_DEV:
+ snd_free_dev_pages(dmab->dev.dev, dmab->bytes, dmab->area, dmab->addr);
+ break;
+diff -Nur linux-3.10.30.orig/sound/core/pcm_native.c linux-linaro-stable-mx6/sound/core/pcm_native.c
+--- linux-3.10.30.orig/sound/core/pcm_native.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/core/pcm_native.c 2014-05-15 20:34:21.818185446 +0200
+@@ -3209,6 +3209,14 @@
+ struct vm_area_struct *area)
+ {
+ area->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP;
++#ifdef CONFIG_GENERIC_ALLOCATOR
++ if (substream->dma_buffer.dev.type == SNDRV_DMA_TYPE_DEV_IRAM) {
++ area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
++ return remap_pfn_range(area, area->vm_start,
++ substream->dma_buffer.addr >> PAGE_SHIFT,
++ area->vm_end - area->vm_start, area->vm_page_prot);
++ }
++#endif /* CONFIG_GENERIC_ALLOCATOR */
+ #ifdef ARCH_HAS_DMA_MMAP_COHERENT
+ if (!substream->ops->page &&
+ substream->dma_buffer.dev.type == SNDRV_DMA_TYPE_DEV)
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/cs42888.c linux-linaro-stable-mx6/sound/soc/codecs/cs42888.c
+--- linux-3.10.30.orig/sound/soc/codecs/cs42888.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/cs42888.c 2014-05-15 20:34:23.350196475 +0200
+@@ -0,0 +1,934 @@
++/*
++ * cs42888.c -- CS42888 ALSA SoC Audio Driver
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/pm.h>
++#include <linux/i2c.h>
++#include <linux/spi/spi.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++#include <sound/initval.h>
++#include <asm/div64.h>
++#include "cs42888.h"
++
++#define CS42888_NUM_SUPPLIES 4
++static const char *cs42888_supply_names[CS42888_NUM_SUPPLIES] = {
++ "VA",
++ "VD",
++ "VLS",
++ "VLC",
++};
++
++#define CS42888_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
++ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
++
++/* Private data for the CS42888 */
++struct cs42888_private {
++ struct clk *clk;
++ struct snd_soc_codec *codec;
++ u8 reg_cache[CS42888_NUMREGS + 1];
++ unsigned int mclk; /* Input frequency of the MCLK pin */
++ unsigned int slave_mode;
++ struct regulator_bulk_data supplies[CS42888_NUM_SUPPLIES];
++};
++
++/**
++ * cs42888_fill_cache - pre-fill the CS42888 register cache.
++ * @codec: the codec for this CS42888
++ *
++ * This function fills in the CS42888 register cache by reading the register
++ * values from the hardware.
++ *
++ * This CS42888 registers are cached to avoid excessive I2C I/O operations.
++ * After the initial read to pre-fill the cache, the CS42888 never updates
++ * the register values, so we won't have a cache coherency problem.
++ *
++ * We use the auto-increment feature of the CS42888 to read all registers in
++ * one shot.
++ */
++static int cs42888_fill_cache(struct snd_soc_codec *codec)
++{
++ u8 *cache = codec->reg_cache;
++ struct i2c_client *i2c_client = to_i2c_client(codec->dev);
++ s32 length;
++
++ length = i2c_smbus_read_i2c_block_data(i2c_client,
++ CS42888_FIRSTREG | CS42888_I2C_INCR, CS42888_NUMREGS, \
++ cache + 1);
++
++ if (length != CS42888_NUMREGS) {
++ dev_err(codec->dev, "i2c read failure, addr=0x%x\n",
++ i2c_client->addr);
++ return -EIO;
++ }
++ return 0;
++}
++
++#ifdef DEBUG
++static void dump_reg(struct snd_soc_codec *codec)
++{
++ int i, reg;
++ int ret;
++ u8 *cache = codec->reg_cache + 1;
++
++ dev_dbg(codec->dev, "dump begin\n");
++ dev_dbg(codec->dev, "reg value in cache\n");
++ for (i = 0; i < CS42888_NUMREGS; i++)
++ dev_dbg(codec->dev, "reg[%d] = 0x%x\n", i, cache[i]);
++
++ dev_dbg(codec->dev, "real reg value\n");
++ ret = cs42888_fill_cache(codec);
++ if (ret < 0) {
++ dev_err(codec->dev, "failed to fill register cache\n");
++ return ret;
++ }
++ for (i = 0; i < CS42888_NUMREGS; i++)
++ dev_dbg(codec->dev, "reg[%d] = 0x%x\n", i, cache[i]);
++
++ dev_dbg(codec->dev, "dump end\n");
++}
++#else
++static void dump_reg(struct snd_soc_codec *codec)
++{
++}
++#endif
++
++/* -127.5dB to 0dB with step of 0.5dB */
++static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
++/* -64dB to 24dB with step of 0.5dB */
++static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 1);
++
++static int cs42888_out_vu(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ return snd_soc_put_volsw_2r(kcontrol, ucontrol);
++}
++
++static int cs42888_info_volsw_s8(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ struct soc_mixer_control *mc =
++ (struct soc_mixer_control *)kcontrol->private_value;
++
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 2;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = mc->max - mc->min;
++ return 0;
++}
++
++static int cs42888_get_volsw_s8(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct soc_mixer_control *mc =
++ (struct soc_mixer_control *)kcontrol->private_value;
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
++ s8 val = snd_soc_read(codec, mc->reg);
++ ucontrol->value.integer.value[0] = val - mc->min;
++
++ val = snd_soc_read(codec, mc->rreg);
++ ucontrol->value.integer.value[1] = val - mc->min;
++ return 0;
++}
++
++int cs42888_put_volsw_s8(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct soc_mixer_control *mc =
++ (struct soc_mixer_control *)kcontrol->private_value;
++ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
++ unsigned short val;
++ int ret;
++
++ val = ucontrol->value.integer.value[0] + mc->min;
++ ret = snd_soc_write(codec, mc->reg, val);
++ if (ret < 0) {
++ dev_err(codec->dev, "i2c write failed\n");
++ return ret;
++ }
++
++ val = ucontrol->value.integer.value[1] + mc->min;
++ ret = snd_soc_write(codec, mc->rreg, val);
++ if (ret < 0) {
++ dev_err(codec->dev, "i2c write failed\n");
++ return ret;
++ }
++ return 0;
++}
++
++#define SOC_CS42888_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
++ xinvert, tlv_array) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
++ .name = (xname), \
++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
++ SNDRV_CTL_ELEM_ACCESS_READWRITE, \
++ .tlv.p = (tlv_array), \
++ .info = snd_soc_info_volsw, \
++ .get = snd_soc_get_volsw, \
++ .put = cs42888_out_vu, \
++ .private_value = (unsigned long)&(struct soc_mixer_control) \
++ {.reg = reg_left, \
++ .rreg = reg_right, \
++ .shift = xshift, \
++ .max = xmax, \
++ .invert = xinvert} \
++}
++
++#define SOC_CS42888_DOUBLE_R_S8_TLV(xname, reg_left, reg_right, xmin, xmax, \
++ tlv_array) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
++ SNDRV_CTL_ELEM_ACCESS_READWRITE, \
++ .tlv.p = (tlv_array), \
++ .info = cs42888_info_volsw_s8, \
++ .get = cs42888_get_volsw_s8, \
++ .put = cs42888_put_volsw_s8, \
++ .private_value = (unsigned long)&(struct soc_mixer_control) \
++ {.reg = reg_left, \
++ .rreg = reg_right, \
++ .min = xmin, \
++ .max = xmax} \
++}
++
++static const char *cs42888_adcfilter[] = { "None", "High Pass" };
++static const char *cs42888_dacinvert[] = { "Disabled", "Enabled" };
++static const char *cs42888_adcinvert[] = { "Disabled", "Enabled" };
++static const char *cs42888_dacamute[] = { "Disabled", "AutoMute" };
++static const char *cs42888_dac_sngvol[] = { "Disabled", "Enabled" };
++static const char *cs42888_dac_szc[] = { "Immediate Change", "Zero Cross",
++ "Soft Ramp", "Soft Ramp on Zero Cross" };
++static const char *cs42888_mute_adc[] = { "UnMute", "Mute" };
++static const char *cs42888_adc_sngvol[] = { "Disabled", "Enabled" };
++static const char *cs42888_adc_szc[] = { "Immediate Change", "Zero Cross",
++ "Soft Ramp", "Soft Ramp on Zero Cross" };
++static const char *cs42888_dac_dem[] = { "No-De-Emphasis", "De-Emphasis" };
++static const char *cs42888_adc_single[] = { "Differential", "Single-Ended" };
++
++static const struct soc_enum cs42888_enum[] = {
++ SOC_ENUM_SINGLE(CS42888_ADCCTL, 7, 2, cs42888_adcfilter),
++ SOC_ENUM_DOUBLE(CS42888_DACINV, 0, 1, 2, cs42888_dacinvert),
++ SOC_ENUM_DOUBLE(CS42888_DACINV, 2, 3, 2, cs42888_dacinvert),
++ SOC_ENUM_DOUBLE(CS42888_DACINV, 4, 5, 2, cs42888_dacinvert),
++ SOC_ENUM_DOUBLE(CS42888_DACINV, 6, 7, 2, cs42888_dacinvert),
++ SOC_ENUM_DOUBLE(CS42888_ADCINV, 0, 1, 2, cs42888_adcinvert),
++ SOC_ENUM_DOUBLE(CS42888_ADCINV, 2, 3, 2, cs42888_adcinvert),
++ SOC_ENUM_SINGLE(CS42888_TRANS, 4, 2, cs42888_dacamute),
++ SOC_ENUM_SINGLE(CS42888_TRANS, 7, 2, cs42888_dac_sngvol),
++ SOC_ENUM_SINGLE(CS42888_TRANS, 5, 4, cs42888_dac_szc),
++ SOC_ENUM_SINGLE(CS42888_TRANS, 3, 2, cs42888_mute_adc),
++ SOC_ENUM_SINGLE(CS42888_TRANS, 2, 2, cs42888_adc_sngvol),
++ SOC_ENUM_SINGLE(CS42888_TRANS, 0, 4, cs42888_adc_szc),
++ SOC_ENUM_SINGLE(CS42888_ADCCTL, 5, 2, cs42888_dac_dem),
++ SOC_ENUM_SINGLE(CS42888_ADCCTL, 4, 2, cs42888_adc_single),
++ SOC_ENUM_SINGLE(CS42888_ADCCTL, 3, 2, cs42888_adc_single),
++};
++
++static const struct snd_kcontrol_new cs42888_snd_controls[] = {
++ SOC_CS42888_DOUBLE_R_TLV("DAC1 Playback Volume", CS42888_VOLAOUT1,
++ CS42888_VOLAOUT2, 0, 0xff, 1, dac_tlv),
++ SOC_CS42888_DOUBLE_R_TLV("DAC2 Playback Volume", CS42888_VOLAOUT3,
++ CS42888_VOLAOUT4, 0, 0xff, 1, dac_tlv),
++ SOC_CS42888_DOUBLE_R_TLV("DAC3 Playback Volume", CS42888_VOLAOUT5,
++ CS42888_VOLAOUT6, 0, 0xff, 1, dac_tlv),
++ SOC_CS42888_DOUBLE_R_TLV("DAC4 Playback Volume", CS42888_VOLAOUT7,
++ CS42888_VOLAOUT8, 0, 0xff, 1, dac_tlv),
++ SOC_CS42888_DOUBLE_R_S8_TLV("ADC1 Capture Volume", CS42888_VOLAIN1,
++ CS42888_VOLAIN2, -128, 48, adc_tlv),
++ SOC_CS42888_DOUBLE_R_S8_TLV("ADC2 Capture Volume", CS42888_VOLAIN3,
++ CS42888_VOLAIN4, -128, 48, adc_tlv),
++ SOC_ENUM("ADC High-Pass Filter Switch", cs42888_enum[0]),
++ SOC_ENUM("DAC1 Invert Switch", cs42888_enum[1]),
++ SOC_ENUM("DAC2 Invert Switch", cs42888_enum[2]),
++ SOC_ENUM("DAC3 Invert Switch", cs42888_enum[3]),
++ SOC_ENUM("DAC4 Invert Switch", cs42888_enum[4]),
++ SOC_ENUM("ADC1 Invert Switch", cs42888_enum[5]),
++ SOC_ENUM("ADC2 Invert Switch", cs42888_enum[6]),
++ SOC_ENUM("DAC Auto Mute Switch", cs42888_enum[7]),
++ SOC_ENUM("DAC Single Volume Control Switch", cs42888_enum[8]),
++ SOC_ENUM("DAC Soft Ramp and Zero Cross Control Switch", cs42888_enum[9]),
++ SOC_ENUM("Mute ADC Serial Port Switch", cs42888_enum[10]),
++ SOC_ENUM("ADC Single Volume Control Switch", cs42888_enum[11]),
++ SOC_ENUM("ADC Soft Ramp and Zero Cross Control Switch", cs42888_enum[12]),
++ SOC_ENUM("DAC Deemphasis Switch", cs42888_enum[13]),
++ SOC_ENUM("ADC1 Single Ended Mode Switch", cs42888_enum[14]),
++ SOC_ENUM("ADC2 Single Ended Mode Switch", cs42888_enum[15]),
++};
++
++
++static const struct snd_soc_dapm_widget cs42888_dapm_widgets[] = {
++ SND_SOC_DAPM_DAC("DAC1", "codec-Playback", CS42888_PWRCTL, 1, 1),
++ SND_SOC_DAPM_DAC("DAC2", "codec-Playback", CS42888_PWRCTL, 2, 1),
++ SND_SOC_DAPM_DAC("DAC3", "codec-Playback", CS42888_PWRCTL, 3, 1),
++ SND_SOC_DAPM_DAC("DAC4", "codec-Playback", CS42888_PWRCTL, 4, 1),
++
++ SND_SOC_DAPM_OUTPUT("AOUT1L"),
++ SND_SOC_DAPM_OUTPUT("AOUT1R"),
++ SND_SOC_DAPM_OUTPUT("AOUT2L"),
++ SND_SOC_DAPM_OUTPUT("AOUT2R"),
++ SND_SOC_DAPM_OUTPUT("AOUT3L"),
++ SND_SOC_DAPM_OUTPUT("AOUT3R"),
++ SND_SOC_DAPM_OUTPUT("AOUT4L"),
++ SND_SOC_DAPM_OUTPUT("AOUT4R"),
++
++ SND_SOC_DAPM_ADC("ADC1", "codec-Capture", CS42888_PWRCTL, 5, 1),
++ SND_SOC_DAPM_ADC("ADC2", "codec-Capture", CS42888_PWRCTL, 6, 1),
++
++ SND_SOC_DAPM_INPUT("AIN1L"),
++ SND_SOC_DAPM_INPUT("AIN1R"),
++ SND_SOC_DAPM_INPUT("AIN2L"),
++ SND_SOC_DAPM_INPUT("AIN2R"),
++
++ SND_SOC_DAPM_PGA_E("PWR", CS42888_PWRCTL, 0, 1, NULL, 0,
++ NULL, 0),
++};
++
++static const struct snd_soc_dapm_route audio_map[] = {
++ /* Playback */
++ { "PWR", NULL, "DAC1" },
++ { "PWR", NULL, "DAC1" },
++
++ { "PWR", NULL, "DAC2" },
++ { "PWR", NULL, "DAC2" },
++
++ { "PWR", NULL, "DAC3" },
++ { "PWR", NULL, "DAC3" },
++
++ { "PWR", NULL, "DAC4" },
++ { "PWR", NULL, "DAC4" },
++
++ { "AOUT1L", NULL, "PWR" },
++ { "AOUT1R", NULL, "PWR" },
++
++ { "AOUT2L", NULL, "PWR" },
++ { "AOUT2R", NULL, "PWR" },
++
++ { "AOUT3L", NULL, "PWR" },
++ { "AOUT3R", NULL, "PWR" },
++
++ { "AOUT4L", NULL, "PWR" },
++ { "AOUT4R", NULL, "PWR" },
++
++ /* Capture */
++ { "PWR", NULL, "AIN1L" },
++ { "PWR", NULL, "AIN1R" },
++
++ { "PWR", NULL, "AIN2L" },
++ { "PWR", NULL, "AIN2R" },
++
++ { "ADC1", NULL, "PWR" },
++ { "ADC1", NULL, "PWR" },
++
++ { "ADC2", NULL, "PWR" },
++ { "ADC2", NULL, "PWR" },
++};
++
++
++static int cs42888_add_widgets(struct snd_soc_codec *codec)
++{
++ snd_soc_dapm_new_controls(&codec->dapm, cs42888_dapm_widgets,
++ ARRAY_SIZE(cs42888_dapm_widgets));
++
++ snd_soc_dapm_add_routes(&codec->dapm, audio_map, ARRAY_SIZE(audio_map));
++
++ snd_soc_dapm_new_widgets(&codec->dapm);
++ return 0;
++}
++
++/**
++ * struct cs42888_mode_ratios - clock ratio tables
++ * @ratio: the ratio of MCLK to the sample rate
++ * @speed_mode: the Speed Mode bits to set in the Mode Control register for
++ * this ratio
++ * @mclk: the Ratio Select bits to set in the Mode Control register for this
++ * ratio
++ *
++ * The data for this chart is taken from Table 10 of the CS42888 reference
++ * manual.
++ *
++ * This table is used to determine how to program the Functional Mode register.
++ * It is also used by cs42888_set_dai_sysclk() to tell ALSA which sampling
++ * rates the CS42888 currently supports.
++ *
++ * @speed_mode is the corresponding bit pattern to be written to the
++ * MODE bits of the Mode Control Register
++ *
++ * @mclk is the corresponding bit pattern to be wirten to the MCLK bits of
++ * the Mode Control Register.
++ *
++ */
++struct cs42888_mode_ratios {
++ unsigned int ratio;
++ u8 speed_mode;
++ u8 mclk;
++};
++
++static struct cs42888_mode_ratios cs42888_mode_ratios[] = {
++ {64, CS42888_MODE_4X, CS42888_MODE_DIV1},
++ {96, CS42888_MODE_4X, CS42888_MODE_DIV2},
++ {128, CS42888_MODE_2X, CS42888_MODE_DIV1},
++ {192, CS42888_MODE_2X, CS42888_MODE_DIV2},
++ {256, CS42888_MODE_1X, CS42888_MODE_DIV1},
++ {384, CS42888_MODE_2X, CS42888_MODE_DIV4},
++ {512, CS42888_MODE_1X, CS42888_MODE_DIV3},
++ {768, CS42888_MODE_1X, CS42888_MODE_DIV4},
++ {1024, CS42888_MODE_1X, CS42888_MODE_DIV5}
++};
++
++/* The number of MCLK/LRCK ratios supported by the CS42888 */
++#define NUM_MCLK_RATIOS ARRAY_SIZE(cs42888_mode_ratios)
++
++/**
++ * cs42888_set_dai_sysclk - determine the CS42888 samples rates.
++ * @codec_dai: the codec DAI
++ * @clk_id: the clock ID (ignored)
++ * @freq: the MCLK input frequency
++ * @dir: the clock direction (ignored)
++ *
++ * This function is used to tell the codec driver what the input MCLK
++ * frequency is.
++ *
++ */
++static int cs42888_set_dai_sysclk(struct snd_soc_dai *codec_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct cs42888_private *cs42888 = snd_soc_codec_get_drvdata(codec);
++
++ cs42888->mclk = freq;
++ return 0;
++}
++
++/**
++ * cs42888_set_dai_fmt - configure the codec for the selected audio format
++ * @codec_dai: the codec DAI
++ * @format: a SND_SOC_DAIFMT_x value indicating the data format
++ *
++ * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
++ * codec accordingly.
++ *
++ * Currently, this function only supports SND_SOC_DAIFMT_I2S and
++ * SND_SOC_DAIFMT_LEFT_J. The CS42888 codec also supports right-justified
++ * data for playback only, but ASoC currently does not support different
++ * formats for playback vs. record.
++ */
++static int cs42888_set_dai_fmt(struct snd_soc_dai *codec_dai,
++ unsigned int format)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct cs42888_private *cs42888 = snd_soc_codec_get_drvdata(codec);
++ int ret = 0;
++ u8 val;
++
++ val = snd_soc_read(codec, CS42888_FORMAT);
++ val &= ~CS42888_FORMAT_DAC_DIF_MASK;
++ val &= ~CS42888_FORMAT_ADC_DIF_MASK;
++ /* set DAI format */
++ switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_LEFT_J:
++ val |= DIF_LEFT_J << CS42888_FORMAT_DAC_DIF_OFFSET;
++ val |= DIF_LEFT_J << CS42888_FORMAT_ADC_DIF_OFFSET;
++ break;
++ case SND_SOC_DAIFMT_I2S:
++ val |= DIF_I2S << CS42888_FORMAT_DAC_DIF_OFFSET;
++ val |= DIF_I2S << CS42888_FORMAT_ADC_DIF_OFFSET;
++ break;
++ case SND_SOC_DAIFMT_RIGHT_J:
++ val |= DIF_RIGHT_J << CS42888_FORMAT_DAC_DIF_OFFSET;
++ val |= DIF_RIGHT_J << CS42888_FORMAT_ADC_DIF_OFFSET;
++ break;
++ default:
++ dev_err(codec->dev, "invalid dai format\n");
++ return -EINVAL;
++ }
++
++ ret = snd_soc_write(codec, CS42888_FORMAT, val);
++ if (ret < 0) {
++ dev_err(codec->dev, "i2c write failed\n");
++ return ret;
++ }
++
++ val = snd_soc_read(codec, CS42888_MODE);
++ /* set master/slave audio interface */
++ switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ cs42888->slave_mode = 1;
++ val &= ~CS42888_MODE_SPEED_MASK;
++ val |= CS42888_MODE_SLAVE;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFM:
++ cs42888->slave_mode = 0;
++ break;
++ default:
++ /* all other modes are unsupported by the hardware */
++ return -EINVAL;
++ }
++
++ ret = snd_soc_write(codec, CS42888_MODE, val);
++ if (ret < 0) {
++ dev_err(codec->dev, "i2c write failed\n");
++ return ret;
++ }
++
++ dump_reg(codec);
++ return ret;
++}
++
++/**
++ * cs42888_hw_params - program the CS42888 with the given hardware parameters.
++ * @substream: the audio stream
++ * @params: the hardware parameters to set
++
++ * @dai: the SOC DAI (ignored)
++ *
++ * This function programs the hardware with the values provided.
++ * Specifically, the sample rate and the data format.
++ *
++ * The .ops functions are used to provide board-specific data, like input
++ * frequencies, to this driver. This function takes that information,
++ * combines it with the hardware parameters provided, and programs the
++ * hardware accordingly.
++ */
++static int cs42888_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ struct cs42888_private *cs42888 = snd_soc_codec_get_drvdata(codec);
++ int ret;
++ u32 i, rate, ratio, val;
++
++ rate = params_rate(params); /* Sampling rate, in Hz */
++ ratio = cs42888->mclk / rate; /* MCLK/LRCK ratio */
++ for (i = 0; i < NUM_MCLK_RATIOS; i++) {
++ if (cs42888_mode_ratios[i].ratio == ratio)
++ break;
++ }
++
++ if (i == NUM_MCLK_RATIOS) {
++ /* We did not find a matching ratio */
++ dev_err(codec->dev, "could not find matching ratio\n");
++ return -EINVAL;
++ }
++
++ if (!cs42888->slave_mode) {
++ val = snd_soc_read(codec, CS42888_MODE);
++ val &= ~CS42888_MODE_SPEED_MASK;
++ val |= cs42888_mode_ratios[i].speed_mode;
++ val &= ~CS42888_MODE_DIV_MASK;
++ val |= cs42888_mode_ratios[i].mclk;
++ } else {
++ val = snd_soc_read(codec, CS42888_MODE);
++ val &= ~CS42888_MODE_SPEED_MASK;
++ val |= CS42888_MODE_SLAVE;
++ val &= ~CS42888_MODE_DIV_MASK;
++ val |= cs42888_mode_ratios[i].mclk;
++ }
++ ret = snd_soc_write(codec, CS42888_MODE, val);
++ if (ret < 0) {
++ dev_err(codec->dev, "i2c write failed\n");
++ return ret;
++ }
++
++ /* Unmute all the channels */
++ val = snd_soc_read(codec, CS42888_MUTE);
++ val &= ~CS42888_MUTE_ALL;
++ ret = snd_soc_write(codec, CS42888_MUTE, val);
++ if (ret < 0) {
++ dev_err(codec->dev, "i2c write failed\n");
++ return ret;
++ }
++
++ ret = cs42888_fill_cache(codec);
++ if (ret < 0) {
++ dev_err(codec->dev, "failed to fill register cache\n");
++ return ret;
++ }
++
++ dump_reg(codec);
++ return ret;
++}
++
++/**
++ * cs42888_shutdown - cs42888 enters into low power mode again.
++ * @substream: the audio stream
++ * @dai: the SOC DAI (ignored)
++ *
++ * The .ops functions are used to provide board-specific data, like input
++ * frequencies, to this driver. This function takes that information,
++ * combines it with the hardware parameters provided, and programs the
++ * hardware accordingly.
++ */
++static void cs42888_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ int ret;
++ u8 val;
++
++ /* Mute all the channels */
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ val = snd_soc_read(codec, CS42888_MUTE);
++ val |= CS42888_MUTE_ALL;
++ ret = snd_soc_write(codec, CS42888_MUTE, val);
++ if (ret < 0)
++ dev_err(codec->dev, "i2c write failed\n");
++ }
++}
++
++static int cs42888_prepare(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_card *card = rtd->card;
++ struct snd_soc_dai *tmp_codec_dai;
++ struct snd_soc_pcm_runtime *tmp_rtd;
++ u32 i;
++
++ for (i = 0; i < card->num_rtd; i++) {
++ tmp_codec_dai = card->rtd[i].codec_dai;
++ tmp_rtd = (struct snd_soc_pcm_runtime *)(card->rtd + i);
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ cancel_delayed_work(&tmp_rtd->delayed_work);
++ }
++ return 0;
++}
++
++static struct snd_soc_dai_ops cs42888_dai_ops = {
++ .set_fmt = cs42888_set_dai_fmt,
++ .set_sysclk = cs42888_set_dai_sysclk,
++ .hw_params = cs42888_hw_params,
++ .shutdown = cs42888_shutdown,
++ .prepare = cs42888_prepare,
++};
++
++
++static struct snd_soc_dai_driver cs42888_dai = {
++ .name = "CS42888",
++ .playback = {
++ .stream_name = "codec-Playback",
++ .channels_min = 2,
++ .channels_max = 8,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = CS42888_FORMATS,
++ },
++ .capture = {
++ .stream_name = "codec-Capture",
++ .channels_min = 2,
++ .channels_max = 4,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = CS42888_FORMATS,
++ },
++ .ops = &cs42888_dai_ops,
++};
++
++/**
++ * cs42888_probe - ASoC probe function
++ * @pdev: platform device
++ *
++ * This function is called when ASoC has all the pieces it needs to
++ * instantiate a sound driver.
++ */
++static int cs42888_probe(struct snd_soc_codec *codec)
++{
++ struct cs42888_private *cs42888 = snd_soc_codec_get_drvdata(codec);
++ int ret, i, val;
++
++ cs42888->codec = codec;
++ /* setup i2c data ops */
++ ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
++ if (ret < 0) {
++ dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
++ return ret;
++ }
++
++ for (i = 0; i < ARRAY_SIZE(cs42888->supplies); i++)
++ cs42888->supplies[i].supply = cs42888_supply_names[i];
++
++ ret = devm_regulator_bulk_get(codec->dev,
++ ARRAY_SIZE(cs42888->supplies), cs42888->supplies);
++ if (ret) {
++ dev_err(codec->dev, "Failed to request supplies: %d\n",
++ ret);
++ return ret;
++ }
++
++ ret = regulator_bulk_enable(ARRAY_SIZE(cs42888->supplies),
++ cs42888->supplies);
++ if (ret) {
++ dev_err(codec->dev, "Failed to enable supplies: %d\n",
++ ret);
++ goto err;
++ }
++ msleep(1);
++
++ /* The I2C interface is set up, so pre-fill our register cache */
++ ret = cs42888_fill_cache(codec);
++ if (ret < 0) {
++ dev_err(codec->dev, "failed to fill register cache\n");
++ goto err;
++ }
++
++ /* Enter low power state */
++ val = snd_soc_read(codec, CS42888_PWRCTL);
++ val |= CS42888_PWRCTL_PDN_MASK;
++ ret = snd_soc_write(codec, CS42888_PWRCTL, val);
++ if (ret < 0) {
++ dev_err(codec->dev, "i2c write failed\n");
++ goto err;
++ }
++
++ /* Disable auto-mute */
++ val = snd_soc_read(codec, CS42888_TRANS);
++ val &= ~CS42888_TRANS_AMUTE_MASK;
++ val &= ~CS42888_TRANS_DAC_SZC_MASK;
++ val |= CS42888_TRANS_DAC_SZC_SR;
++ ret = snd_soc_write(codec, CS42888_TRANS, val);
++ if (ret < 0) {
++ dev_err(codec->dev, "i2c write failed\n");
++ goto err;
++ }
++ /* Add the non-DAPM controls */
++ snd_soc_add_codec_controls(codec, cs42888_snd_controls,
++ ARRAY_SIZE(cs42888_snd_controls));
++
++ /* Add DAPM controls */
++ cs42888_add_widgets(codec);
++ return 0;
++err:
++ regulator_bulk_disable(ARRAY_SIZE(cs42888->supplies),
++ cs42888->supplies);
++ return ret;
++}
++
++/**
++ * cs42888_remove - ASoC remove function
++ * @pdev: platform device
++ *
++ * This function is the counterpart to cs42888_probe().
++ */
++static int cs42888_remove(struct snd_soc_codec *codec)
++{
++ struct cs42888_private *cs42888 = snd_soc_codec_get_drvdata(codec);
++
++ regulator_bulk_disable(ARRAY_SIZE(cs42888->supplies),
++ cs42888->supplies);
++
++ return 0;
++};
++
++/*
++ * ASoC codec device structure
++ *
++ * Assign this variable to the codec_dev field of the machine driver's
++ * snd_soc_device structure.
++ */
++static struct snd_soc_codec_driver cs42888_driver = {
++ .probe = cs42888_probe,
++ .remove = cs42888_remove,
++ .reg_cache_size = CS42888_NUMREGS + 1,
++ .reg_word_size = sizeof(u8),
++ .reg_cache_step = 1,
++};
++
++/**
++ * cs42888_i2c_probe - initialize the I2C interface of the CS42888
++ * @i2c_client: the I2C client object
++ * @id: the I2C device ID (ignored)
++ *
++ * This function is called whenever the I2C subsystem finds a device that
++ * matches the device ID given via a prior call to i2c_add_driver().
++ */
++static int cs42888_i2c_probe(struct i2c_client *i2c_client,
++ const struct i2c_device_id *id)
++{
++ struct cs42888_private *cs42888;
++ int ret, val;
++
++ /* Verify that we have a CS42888 */
++ val = i2c_smbus_read_byte_data(i2c_client, CS42888_CHIPID);
++ if (val < 0) {
++ dev_err(&i2c_client->dev, "Device with ID register %x is not a CS42888", val);
++ return -ENODEV;
++ }
++ /* The top four bits of the chip ID should be 0000. */
++ if ((val & CS42888_CHIPID_ID_MASK) != 0x00) {
++ dev_err(&i2c_client->dev, "device is not a CS42888\n");
++ return -ENODEV;
++ }
++
++ dev_info(&i2c_client->dev, "found device at i2c address %X\n",
++ i2c_client->addr);
++ dev_info(&i2c_client->dev, "hardware revision %X\n", val & 0xF);
++
++ /* Allocate enough space for the snd_soc_codec structure
++ and our private data together. */
++ cs42888 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs42888_private), GFP_KERNEL);
++ if (!cs42888) {
++ dev_err(&i2c_client->dev, "could not allocate codec\n");
++ return -ENOMEM;
++ }
++
++ i2c_set_clientdata(i2c_client, cs42888);
++
++ cs42888->clk = devm_clk_get(&i2c_client->dev, NULL);
++ if (IS_ERR(cs42888->clk)) {
++ ret = PTR_ERR(cs42888->clk);
++ dev_err(&i2c_client->dev, "Cannot get the clock: %d\n", ret);
++ return ret;
++ }
++
++ cs42888->mclk = clk_get_rate(cs42888->clk);
++ switch (cs42888->mclk) {
++ case 24576000:
++ cs42888_dai.playback.rates = SNDRV_PCM_RATE_48000 |
++ SNDRV_PCM_RATE_96000 |
++ SNDRV_PCM_RATE_192000;
++ cs42888_dai.capture.rates = SNDRV_PCM_RATE_48000 |
++ SNDRV_PCM_RATE_96000 |
++ SNDRV_PCM_RATE_192000;
++ break;
++ case 16934400:
++ cs42888_dai.playback.rates = SNDRV_PCM_RATE_44100 |
++ SNDRV_PCM_RATE_88200 |
++ SNDRV_PCM_RATE_176400;
++ cs42888_dai.capture.rates = SNDRV_PCM_RATE_44100 |
++ SNDRV_PCM_RATE_88200 |
++ SNDRV_PCM_RATE_176400;
++ break;
++ default:
++ dev_err(&i2c_client->dev, "codec mclk is not supported %d\n", cs42888->mclk);
++ break;
++ }
++
++ ret = snd_soc_register_codec(&i2c_client->dev,
++ &cs42888_driver, &cs42888_dai, 1);
++ if (ret) {
++ dev_err(&i2c_client->dev, "Failed to register codec:%d\n", ret);
++ return ret;
++ }
++ return 0;
++}
++
++/**
++ * cs42888_i2c_remove - remove an I2C device
++ * @i2c_client: the I2C client object
++ *
++ * This function is the counterpart to cs42888_i2c_probe().
++ */
++static int cs42888_i2c_remove(struct i2c_client *i2c_client)
++{
++ snd_soc_unregister_codec(&i2c_client->dev);
++ return 0;
++}
++
++/*
++ * cs42888_i2c_id - I2C device IDs supported by this driver
++ */
++static struct i2c_device_id cs42888_i2c_id[] = {
++ {"cs42888", 0},
++ {}
++};
++MODULE_DEVICE_TABLE(i2c, cs42888_i2c_id);
++
++#ifdef CONFIG_PM
++/* This suspend/resume implementation can handle both - a simple standby
++ * where the codec remains powered, and a full suspend, where the voltage
++ * domain the codec is connected to is teared down and/or any other hardware
++ * reset condition is asserted.
++ *
++ * The codec's own power saving features are enabled in the suspend callback,
++ * and all registers are written back to the hardware when resuming.
++ */
++
++static int cs42888_i2c_suspend(struct i2c_client *client, pm_message_t mesg)
++{
++ struct cs42888_private *cs42888 = i2c_get_clientdata(client);
++ struct snd_soc_codec *codec = cs42888->codec;
++ int reg = snd_soc_read(codec, CS42888_PWRCTL) | CS42888_PWRCTL_PDN_MASK;
++ return snd_soc_write(codec, CS42888_PWRCTL, reg);
++}
++
++static int cs42888_i2c_resume(struct i2c_client *client)
++{
++ struct cs42888_private *cs42888 = i2c_get_clientdata(client);
++ struct snd_soc_codec *codec = cs42888->codec;
++ int reg;
++
++ /* In case the device was put to hard reset during sleep, we need to
++ * wait 500ns here before any I2C communication. */
++ ndelay(500);
++
++ /* first restore the entire register cache ... */
++ for (reg = CS42888_FIRSTREG; reg <= CS42888_LASTREG; reg++) {
++ u8 val = snd_soc_read(codec, reg);
++
++ if (i2c_smbus_write_byte_data(client, reg, val)) {
++ dev_err(codec->dev, "i2c write failed\n");
++ return -EIO;
++ }
++ }
++
++ /* ... then disable the power-down bits */
++ reg = snd_soc_read(codec, CS42888_PWRCTL);
++ reg &= ~CS42888_PWRCTL_PDN_MASK;
++ return snd_soc_write(codec, CS42888_PWRCTL, reg);
++}
++#else
++#define cs42888_i2c_suspend NULL
++#define cs42888_i2c_resume NULL
++#endif /* CONFIG_PM */
++
++/*
++ * cs42888_i2c_driver - I2C device identification
++ *
++ * This structure tells the I2C subsystem how to identify and support a
++ * given I2C device type.
++ */
++
++static const struct of_device_id cs42888_dt_ids[] = {
++ { .compatible = "cirrus,cs42888", },
++ { /* sentinel */ }
++};
++
++static struct i2c_driver cs42888_i2c_driver = {
++ .driver = {
++ .name = "cs42888",
++ .owner = THIS_MODULE,
++ .of_match_table = cs42888_dt_ids,
++ },
++ .probe = cs42888_i2c_probe,
++ .remove = cs42888_i2c_remove,
++ .suspend = cs42888_i2c_suspend,
++ .resume = cs42888_i2c_resume,
++ .id_table = cs42888_i2c_id,
++};
++
++module_i2c_driver(cs42888_i2c_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Cirrus Logic CS42888 ALSA SoC Codec Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/cs42888.h linux-linaro-stable-mx6/sound/soc/codecs/cs42888.h
+--- linux-3.10.30.orig/sound/soc/codecs/cs42888.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/cs42888.h 2014-05-15 20:34:23.350196475 +0200
+@@ -0,0 +1,123 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef _CS42888_H
++#define _CS42888_H
++
++/* CS42888 registers addresses */
++#define CS42888_CHIPID 0x01 /* Chip ID */
++#define CS42888_PWRCTL 0x02 /* Power Control */
++#define CS42888_MODE 0x03 /* Functional Mode */
++#define CS42888_FORMAT 0x04 /* Interface Formats */
++#define CS42888_ADCCTL 0x05 /* ADC Control */
++#define CS42888_TRANS 0x06 /* Transition Control */
++#define CS42888_MUTE 0x07 /* Mute Control */
++#define CS42888_VOLAOUT1 0x08 /* Volume Control AOUT1*/
++#define CS42888_VOLAOUT2 0x09 /* Volume Control AOUT2*/
++#define CS42888_VOLAOUT3 0x0A /* Volume Control AOUT3*/
++#define CS42888_VOLAOUT4 0x0B /* Volume Control AOUT4*/
++#define CS42888_VOLAOUT5 0x0C /* Volume Control AOUT5*/
++#define CS42888_VOLAOUT6 0x0D /* Volume Control AOUT6*/
++#define CS42888_VOLAOUT7 0x0E /* Volume Control AOUT7*/
++#define CS42888_VOLAOUT8 0x0F /* Volume Control AOUT8*/
++#define CS42888_DACINV 0x10 /* DAC Channel Invert */
++#define CS42888_VOLAIN1 0x11 /* Volume Control AIN1 */
++#define CS42888_VOLAIN2 0x12 /* Volume Control AIN2 */
++#define CS42888_VOLAIN3 0x13 /* Volume Control AIN3 */
++#define CS42888_VOLAIN4 0x14 /* Volume Control AIN4 */
++#define CS42888_ADCINV 0x17 /* ADC Channel Invert */
++#define CS42888_STATUSCTL 0x18 /* Status Control */
++#define CS42888_STATUS 0x19 /* Status */
++#define CS42888_STATUSMASK 0x1A /* Status Mask */
++
++#define CS42888_FIRSTREG 0x01
++#define CS42888_LASTREG 0x1A
++#define CS42888_NUMREGS (CS42888_LASTREG - CS42888_FIRSTREG + 1)
++#define CS42888_I2C_INCR 0x80
++
++/* Bit masks for the CS42888 registers */
++#define CS42888_CHIPID_ID_MASK 0xF0
++#define CS42888_CHIPID_REV 0x0F
++#define CS42888_PWRCTL_PDN_ADC2_OFFSET 6
++#define CS42888_PWRCTL_PDN_ADC1_OFFSET 5
++#define CS42888_PWRCTL_PDN_DAC4_OFFSET 4
++#define CS42888_PWRCTL_PDN_DAC3_OFFSET 3
++#define CS42888_PWRCTL_PDN_DAC2_OFFSET 2
++#define CS42888_PWRCTL_PDN_DAC1_OFFSET 1
++#define CS42888_PWRCTL_PDN_OFFSET 0
++#define CS42888_PWRCTL_PDN_ADC2_MASK (1 << CS42888_PWRCTL_PDN_ADC2_OFFSET)
++#define CS42888_PWRCTL_PDN_ADC1_MASK (1 << CS42888_PWRCTL_PDN_ADC1_OFFSET)
++#define CS42888_PWRCTL_PDN_DAC4_MASK (1 << CS42888_PWRCTL_PDN_DAC4_OFFSET)
++#define CS42888_PWRCTL_PDN_DAC3_MASK (1 << CS42888_PWRCTL_PDN_DAC3_OFFSET)
++#define CS42888_PWRCTL_PDN_DAC2_MASK (1 << CS42888_PWRCTL_PDN_DAC2_OFFSET)
++#define CS42888_PWRCTL_PDN_DAC1_MASK (1 << CS42888_PWRCTL_PDN_DAC1_OFFSET)
++#define CS42888_PWRCTL_PDN_MASK (1 << CS42888_PWRCTL_PDN_OFFSET)
++
++#define CS42888_MODE_SPEED_MASK 0xF0
++#define CS42888_MODE_1X 0x00
++#define CS42888_MODE_2X 0x50
++#define CS42888_MODE_4X 0xA0
++#define CS42888_MODE_SLAVE 0xF0
++#define CS42888_MODE_DIV_MASK 0x0E
++#define CS42888_MODE_DIV1 0x00
++#define CS42888_MODE_DIV2 0x02
++#define CS42888_MODE_DIV3 0x04
++#define CS42888_MODE_DIV4 0x06
++#define CS42888_MODE_DIV5 0x08
++
++#define CS42888_FORMAT_FREEZE_OFFSET 7
++#define CS42888_FORMAT_AUX_DIF_OFFSET 6
++#define CS42888_FORMAT_DAC_DIF_OFFSET 3
++#define CS42888_FORMAT_ADC_DIF_OFFSET 0
++#define CS42888_FORMAT_FREEZE_MASK (1 << CS42888_FORMAT_FREEZE_OFFSET)
++#define CS42888_FORMAT_AUX_DIF_MASK (1 << CS42888_FORMAT_AUX_DIF_OFFSET)
++#define CS42888_FORMAT_DAC_DIF_MASK (7 << CS42888_FORMAT_DAC_DIF_OFFSET)
++#define CS42888_FORMAT_ADC_DIF_MASK (7 << CS42888_FORMAT_ADC_DIF_OFFSET)
++
++#define CS42888_TRANS_DAC_SNGVOL_OFFSET 7
++#define CS42888_TRANS_DAC_SZC_OFFSET 5
++#define CS42888_TRANS_AMUTE_OFFSET 4
++#define CS42888_TRANS_MUTE_ADC_SP_OFFSET 3
++#define CS42888_TRANS_ADC_SNGVOL_OFFSET 2
++#define CS42888_TRANS_ADC_SZC_OFFSET 0
++#define CS42888_TRANS_DAC_SNGVOL_MASK (1 << CS42888_TRANS_DAC_SNGVOL_OFFSET)
++#define CS42888_TRANS_DAC_SZC_MASK (3 << CS42888_TRANS_DAC_SZC_OFFSET)
++#define CS42888_TRANS_AMUTE_MASK (1 << CS42888_TRANS_AMUTE_OFFSET)
++#define CS42888_TRANS_MUTE_ADC_SP_MASK (1 << CS42888_TRANS_MUTE_ADC_SP_OFFSET)
++#define CS42888_TRANS_ADC_SNGVOL_MASK (1 << CS42888_TRANS_ADC_SNGVOL_OFFSET)
++#define CS42888_TRANS_ADC_SZC_MASK (3 << CS42888_TRANS_ADC_SZC_OFFSET)
++#define CS42888_TRANS_DAC_SZC_IC (0 << CS42888_TRANS_DAC_SZC_OFFSET)
++#define CS42888_TRANS_DAC_SZC_ZC (1 << CS42888_TRANS_DAC_SZC_OFFSET)
++#define CS42888_TRANS_DAC_SZC_SR (2 << CS42888_TRANS_DAC_SZC_OFFSET)
++#define CS42888_TRANS_DAC_SZC_SRZC (3 << CS42888_TRANS_DAC_SZC_OFFSET)
++
++#define CS42888_MUTE_AOUT8 (0x1 << 7)
++#define CS42888_MUTE_AOUT7 (0x1 << 6)
++#define CS42888_MUTE_AOUT6 (0x1 << 5)
++#define CS42888_MUTE_AOUT5 (0x1 << 4)
++#define CS42888_MUTE_AOUT4 (0x1 << 3)
++#define CS42888_MUTE_AOUT3 (0x1 << 2)
++#define CS42888_MUTE_AOUT2 (0x1 << 1)
++#define CS42888_MUTE_AOUT1 (0x1 << 0)
++#define CS42888_MUTE_ALL (CS42888_MUTE_AOUT1 | CS42888_MUTE_AOUT2 | \
++ CS42888_MUTE_AOUT3 | CS42888_MUTE_AOUT4 | \
++ CS42888_MUTE_AOUT5 | CS42888_MUTE_AOUT6 | \
++ CS42888_MUTE_AOUT7 | CS42888_MUTE_AOUT8)
++
++#define DIF_LEFT_J 0
++#define DIF_I2S 1
++#define DIF_RIGHT_J 2
++#define DIF_TDM 6
++
++
++#endif
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/Kconfig linux-linaro-stable-mx6/sound/soc/codecs/Kconfig
+--- linux-3.10.30.orig/sound/soc/codecs/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/Kconfig 2014-05-15 20:34:23.322196274 +0200
+@@ -35,6 +35,7 @@
+ select SND_SOC_CS42L73 if I2C
+ select SND_SOC_CS4270 if I2C
+ select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI
++ select SND_SOC_CS42888 if I2C
+ select SND_SOC_CX20442 if TTY
+ select SND_SOC_DA7210 if I2C
+ select SND_SOC_DA7213 if I2C
+@@ -53,7 +54,7 @@
+ select SND_SOC_MAX9877 if I2C
+ select SND_SOC_MC13783 if MFD_MC13XXX
+ select SND_SOC_ML26124 if I2C
+- select SND_SOC_OMAP_HDMI_CODEC if OMAP4_DSS_HDMI
++ select SND_SOC_OMAP_HDMI_CODEC
+ select SND_SOC_PCM3008
+ select SND_SOC_RT5631 if I2C
+ select SND_SOC_SGTL5000 if I2C
+@@ -240,6 +241,9 @@
+ config SND_SOC_CS4271
+ tristate
+
++config SND_SOC_CS42888
++ tristate
++
+ config SND_SOC_CX20442
+ tristate
+ depends on TTY
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/Makefile linux-linaro-stable-mx6/sound/soc/codecs/Makefile
+--- linux-3.10.30.orig/sound/soc/codecs/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/Makefile 2014-05-15 20:34:23.322196274 +0200
+@@ -22,6 +22,7 @@
+ snd-soc-cs42l73-objs := cs42l73.o
+ snd-soc-cs4270-objs := cs4270.o
+ snd-soc-cs4271-objs := cs4271.o
++snd-soc-cs42888-objs := cs42888.o
+ snd-soc-cx20442-objs := cx20442.o
+ snd-soc-da7210-objs := da7210.o
+ snd-soc-da7213-objs := da7213.o
+@@ -50,7 +51,7 @@
+ snd-soc-sigmadsp-objs := sigmadsp.o
+ snd-soc-si476x-objs := si476x.o
+ snd-soc-sn95031-objs := sn95031.o
+-snd-soc-spdif-tx-objs := spdif_transciever.o
++snd-soc-spdif-tx-objs := spdif_transmitter.o
+ snd-soc-spdif-rx-objs := spdif_receiver.o
+ snd-soc-ssm2602-objs := ssm2602.o
+ snd-soc-sta32x-objs := sta32x.o
+@@ -149,6 +150,7 @@
+ obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o
+ obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
+ obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o
++obj-$(CONFIG_SND_SOC_CS42888) += snd-soc-cs42888.o
+ obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
+ obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o
+ obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/omap-hdmi.c linux-linaro-stable-mx6/sound/soc/codecs/omap-hdmi.c
+--- linux-3.10.30.orig/sound/soc/codecs/omap-hdmi.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/omap-hdmi.c 2014-05-15 20:34:23.578198118 +0200
+@@ -26,7 +26,7 @@
+ static struct snd_soc_codec_driver omap_hdmi_codec;
+
+ static struct snd_soc_dai_driver omap_hdmi_codec_dai = {
+- .name = "omap-hdmi-hifi",
++ .name = "hdmi-hifi",
+ .playback = {
+ .channels_min = 2,
+ .channels_max = 8,
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/spdif_receiver.c linux-linaro-stable-mx6/sound/soc/codecs/spdif_receiver.c
+--- linux-3.10.30.orig/sound/soc/codecs/spdif_receiver.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/spdif_receiver.c 2014-05-15 20:34:23.578198118 +0200
+@@ -24,6 +24,8 @@
+
+ #define STUB_RATES SNDRV_PCM_RATE_8000_192000
+ #define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
++ SNDRV_PCM_FMTBIT_S20_3LE | \
++ SNDRV_PCM_FMTBIT_S24_LE | \
+ SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
+
+ static struct snd_soc_codec_driver soc_codec_spdif_dir;
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/spdif_transciever.c linux-linaro-stable-mx6/sound/soc/codecs/spdif_transciever.c
+--- linux-3.10.30.orig/sound/soc/codecs/spdif_transciever.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/spdif_transciever.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,69 +0,0 @@
+-/*
+- * ALSA SoC SPDIF DIT driver
+- *
+- * This driver is used by controllers which can operate in DIT (SPDI/F) where
+- * no codec is needed. This file provides stub codec that can be used
+- * in these configurations. TI DaVinci Audio controller uses this driver.
+- *
+- * Author: Steve Chen, <schen@mvista.com>
+- * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
+- * Copyright: (C) 2009 Texas Instruments, India
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/slab.h>
+-#include <sound/soc.h>
+-#include <sound/pcm.h>
+-#include <sound/initval.h>
+-
+-#define DRV_NAME "spdif-dit"
+-
+-#define STUB_RATES SNDRV_PCM_RATE_8000_96000
+-#define STUB_FORMATS SNDRV_PCM_FMTBIT_S16_LE
+-
+-
+-static struct snd_soc_codec_driver soc_codec_spdif_dit;
+-
+-static struct snd_soc_dai_driver dit_stub_dai = {
+- .name = "dit-hifi",
+- .playback = {
+- .stream_name = "Playback",
+- .channels_min = 1,
+- .channels_max = 384,
+- .rates = STUB_RATES,
+- .formats = STUB_FORMATS,
+- },
+-};
+-
+-static int spdif_dit_probe(struct platform_device *pdev)
+-{
+- return snd_soc_register_codec(&pdev->dev, &soc_codec_spdif_dit,
+- &dit_stub_dai, 1);
+-}
+-
+-static int spdif_dit_remove(struct platform_device *pdev)
+-{
+- snd_soc_unregister_codec(&pdev->dev);
+- return 0;
+-}
+-
+-static struct platform_driver spdif_dit_driver = {
+- .probe = spdif_dit_probe,
+- .remove = spdif_dit_remove,
+- .driver = {
+- .name = DRV_NAME,
+- .owner = THIS_MODULE,
+- },
+-};
+-
+-module_platform_driver(spdif_dit_driver);
+-
+-MODULE_AUTHOR("Steve Chen <schen@mvista.com>");
+-MODULE_DESCRIPTION("SPDIF dummy codec driver");
+-MODULE_LICENSE("GPL");
+-MODULE_ALIAS("platform:" DRV_NAME);
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/spdif_transmitter.c linux-linaro-stable-mx6/sound/soc/codecs/spdif_transmitter.c
+--- linux-3.10.30.orig/sound/soc/codecs/spdif_transmitter.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/spdif_transmitter.c 2014-05-15 20:34:23.578198118 +0200
+@@ -0,0 +1,77 @@
++/*
++ * ALSA SoC SPDIF DIT driver
++ *
++ * This driver is used by controllers which can operate in DIT (SPDI/F) where
++ * no codec is needed. This file provides stub codec that can be used
++ * in these configurations. TI DaVinci Audio controller uses this driver.
++ *
++ * Author: Steve Chen, <schen@mvista.com>
++ * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
++ * Copyright: (C) 2009 Texas Instruments, India
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/slab.h>
++#include <linux/of_device.h>
++#include <sound/soc.h>
++#include <sound/pcm.h>
++#include <sound/initval.h>
++
++#define DRV_NAME "spdif-dit"
++
++#define STUB_RATES SNDRV_PCM_RATE_8000_96000
++#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
++ SNDRV_PCM_FMTBIT_S20_3LE | \
++ SNDRV_PCM_FMTBIT_S24_LE)
++
++static struct snd_soc_codec_driver soc_codec_spdif_dit;
++
++static struct snd_soc_dai_driver dit_stub_dai = {
++ .name = "dit-hifi",
++ .playback = {
++ .stream_name = "Playback",
++ .channels_min = 1,
++ .channels_max = 384,
++ .rates = STUB_RATES,
++ .formats = STUB_FORMATS,
++ },
++};
++
++static int spdif_dit_probe(struct platform_device *pdev)
++{
++ return snd_soc_register_codec(&pdev->dev, &soc_codec_spdif_dit,
++ &dit_stub_dai, 1);
++}
++
++static int spdif_dit_remove(struct platform_device *pdev)
++{
++ snd_soc_unregister_codec(&pdev->dev);
++ return 0;
++}
++
++static const struct of_device_id spdif_dit_dt_ids[] = {
++ { .compatible = "linux,spdif-dit"},
++ { }
++};
++
++static struct platform_driver spdif_dit_driver = {
++ .probe = spdif_dit_probe,
++ .remove = spdif_dit_remove,
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = spdif_dit_dt_ids,
++ },
++};
++
++module_platform_driver(spdif_dit_driver);
++
++MODULE_AUTHOR("Steve Chen <schen@mvista.com>");
++MODULE_DESCRIPTION("SPDIF dummy codec driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRV_NAME);
+diff -Nur linux-3.10.30.orig/sound/soc/codecs/wm8962.c linux-linaro-stable-mx6/sound/soc/codecs/wm8962.c
+--- linux-3.10.30.orig/sound/soc/codecs/wm8962.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/codecs/wm8962.c 2014-05-15 20:34:23.698198982 +0200
+@@ -16,6 +16,7 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/pm.h>
++#include <linux/clk.h>
+ #include <linux/gcd.h>
+ #include <linux/gpio.h>
+ #include <linux/i2c.h>
+@@ -51,6 +52,7 @@
+
+ /* codec private data */
+ struct wm8962_priv {
++ struct wm8962_pdata pdata;
+ struct regmap *regmap;
+ struct snd_soc_codec *codec;
+
+@@ -2347,12 +2349,13 @@
+
+ static int wm8962_add_widgets(struct snd_soc_codec *codec)
+ {
+- struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
++ struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
++ struct wm8962_pdata *pdata = &wm8962->pdata;
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+
+ snd_soc_add_codec_controls(codec, wm8962_snd_controls,
+ ARRAY_SIZE(wm8962_snd_controls));
+- if (pdata && pdata->spk_mono)
++ if (pdata->spk_mono)
+ snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
+ ARRAY_SIZE(wm8962_spk_mono_controls));
+ else
+@@ -2362,7 +2365,7 @@
+
+ snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
+ ARRAY_SIZE(wm8962_dapm_widgets));
+- if (pdata && pdata->spk_mono)
++ if (pdata->spk_mono)
+ snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
+ ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
+ else
+@@ -2371,7 +2374,7 @@
+
+ snd_soc_dapm_add_routes(dapm, wm8962_intercon,
+ ARRAY_SIZE(wm8962_intercon));
+- if (pdata && pdata->spk_mono)
++ if (pdata->spk_mono)
+ snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
+ ARRAY_SIZE(wm8962_spk_mono_intercon));
+ else
+@@ -2619,8 +2622,6 @@
+
+ wm8962->sysclk_rate = freq;
+
+- wm8962_configure_bclk(codec);
+-
+ return 0;
+ }
+
+@@ -2912,7 +2913,8 @@
+ WM8962_DAC_MUTE, val);
+ }
+
+-#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
++#define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\
++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
+
+ #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+@@ -3335,14 +3337,14 @@
+ static void wm8962_init_gpio(struct snd_soc_codec *codec)
+ {
+ struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+- struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
++ struct wm8962_pdata *pdata = &wm8962->pdata;
+ int ret;
+
+ wm8962->gpio_chip = wm8962_template_chip;
+ wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
+ wm8962->gpio_chip.dev = codec->dev;
+
+- if (pdata && pdata->gpio_base)
++ if (pdata->gpio_base)
+ wm8962->gpio_chip.base = pdata->gpio_base;
+ else
+ wm8962->gpio_chip.base = -1;
+@@ -3375,7 +3377,7 @@
+ {
+ int ret;
+ struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
+- struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
++ struct wm8962_pdata *pdata = &wm8962->pdata;
+ int i, trigger, irq_pol;
+ bool dmicclk, dmicdat;
+
+@@ -3422,31 +3424,49 @@
+ WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
+ 0);
+
+- if (pdata) {
+- /* Apply static configuration for GPIOs */
+- for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
+- if (pdata->gpio_init[i]) {
+- wm8962_set_gpio_mode(codec, i + 1);
+- snd_soc_write(codec, 0x200 + i,
+- pdata->gpio_init[i] & 0xffff);
+- }
++ /* Apply static configuration for GPIOs */
++ for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
++ if (pdata->gpio_init[i]) {
++ wm8962_set_gpio_mode(codec, i + 1);
++ snd_soc_write(codec, 0x200 + i,
++ pdata->gpio_init[i] & 0xffff);
++ }
+
+- /* Put the speakers into mono mode? */
+- if (pdata->spk_mono)
+- snd_soc_update_bits(codec, WM8962_CLASS_D_CONTROL_2,
++ /* Put the speakers into mono mode? */
++ if (pdata->spk_mono)
++ snd_soc_update_bits(codec, WM8962_CLASS_D_CONTROL_2,
+ WM8962_SPK_MONO_MASK, WM8962_SPK_MONO);
+
++ /* Micbias setup, detection enable and detection
++ * threasholds. */
++ if (pdata->mic_cfg)
++ snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
++ WM8962_MICDET_ENA |
++ WM8962_MICDET_THR_MASK |
++ WM8962_MICSHORT_THR_MASK |
++ WM8962_MICBIAS_LVL,
++ pdata->mic_cfg);
+
+- /* Micbias setup, detection enable and detection
+- * threasholds. */
+- if (pdata->mic_cfg)
+- snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
+- WM8962_MICDET_ENA |
+- WM8962_MICDET_THR_MASK |
+- WM8962_MICSHORT_THR_MASK |
+- WM8962_MICBIAS_LVL,
+- pdata->mic_cfg);
+- }
++ /* set the default volume for playback and record*/
++ snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
++ WM8962_HPOUTL_VOL_MASK, 0x5d);
++ snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
++ WM8962_HPOUTR_VOL_MASK, 0x5d);
++ snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
++ WM8962_SPKOUTL_VOL_MASK, 0x72);
++ snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
++ WM8962_SPKOUTR_VOL_MASK, 0x72);
++
++ snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
++ WM8962_INL_VOL_MASK, 0x3f);
++ snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
++ WM8962_INR_VOL_MASK, 0x3f);
++ snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
++ WM8962_ADCL_VOL_MASK, 0xd8);
++ snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
++ WM8962_ADCR_VOL_MASK, 0xd8);
++ snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_MIXER_VOLUME,
++ WM8962_IN3R_MIXINR_VOL_MASK, 0x7);
+
+ /* Latch volume update bits */
+ snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
+@@ -3508,7 +3528,7 @@
+ wm8962_init_gpio(codec);
+
+ if (wm8962->irq) {
+- if (pdata && pdata->irq_active_low) {
++ if (pdata->irq_active_low) {
+ trigger = IRQF_TRIGGER_LOW;
+ irq_pol = WM8962_IRQ_POL;
+ } else {
+@@ -3586,6 +3606,43 @@
+ .cache_type = REGCACHE_RBTREE,
+ };
+
++static int wm8962_set_pdata_from_of(struct i2c_client *i2c,
++ struct wm8962_pdata *pdata)
++{
++ const struct device_node *np = i2c->dev.of_node;
++ u32 val32;
++ int i;
++
++ if (of_property_read_bool(np, "spk-mono"))
++ pdata->spk_mono = true;
++
++ if (of_property_read_u32(np, "mic-cfg", &val32) >= 0)
++ pdata->mic_cfg = val32;
++
++ if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_init,
++ ARRAY_SIZE(pdata->gpio_init)) >= 0)
++ for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) {
++ /*
++ * The range of GPIO register value is [0x0, 0xffff]
++ * While the default value of each register is 0x0
++ * Any other value will be regarded as default value
++ */
++ if (pdata->gpio_init[i] > 0xffff)
++ pdata->gpio_init[i] = 0x0;
++ }
++
++ pdata->codec_mclk = devm_clk_get(&i2c->dev, NULL);
++
++ /*
++ * If clk_get() failed, we assume that clock's enabled by default.
++ * Otherwise, we let driver prepare and control the clock source.
++ */
++ if (IS_ERR(pdata->codec_mclk))
++ pdata->codec_mclk = NULL;
++
++ return 0;
++}
++
+ static int wm8962_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+ {
+@@ -3605,6 +3662,18 @@
+ init_completion(&wm8962->fll_lock);
+ wm8962->irq = i2c->irq;
+
++ /* If platform data was supplied, update the default data in priv */
++ if (pdata) {
++ memcpy(&wm8962->pdata, pdata, sizeof(struct wm8962_pdata));
++ } else if (i2c->dev.of_node) {
++ ret = wm8962_set_pdata_from_of(i2c, &wm8962->pdata);
++ if (ret != 0)
++ return ret;
++ }
++
++ if (wm8962->pdata.codec_mclk)
++ clk_prepare(wm8962->pdata.codec_mclk);
++
+ for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
+ wm8962->supplies[i].supply = wm8962_supply_names[i];
+
+@@ -3668,7 +3737,7 @@
+ goto err_enable;
+ }
+
+- if (pdata && pdata->in4_dc_measure) {
++ if (wm8962->pdata.in4_dc_measure) {
+ ret = regmap_register_patch(wm8962->regmap,
+ wm8962_dc_measure,
+ ARRAY_SIZE(wm8962_dc_measure));
+@@ -3688,6 +3757,9 @@
+
+ regcache_cache_only(wm8962->regmap, true);
+
++ /* The cache-only should be turned on before we power down the codec */
++ regcache_cache_only(wm8962->regmap, true);
++
+ /* The drivers should power up as needed */
+ regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
+
+@@ -3696,11 +3768,19 @@
+ err_enable:
+ regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
+ err:
++ if (wm8962->pdata.codec_mclk)
++ clk_unprepare(wm8962->pdata.codec_mclk);
++
+ return ret;
+ }
+
+ static int wm8962_i2c_remove(struct i2c_client *client)
+ {
++ struct wm8962_priv *wm8962 = dev_get_drvdata(&client->dev);
++
++ if (wm8962->pdata.codec_mclk)
++ clk_unprepare(wm8962->pdata.codec_mclk);
++
+ snd_soc_unregister_codec(&client->dev);
+ return 0;
+ }
+@@ -3711,6 +3791,9 @@
+ struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
+ int ret;
+
++ if (wm8962->pdata.codec_mclk)
++ clk_enable(wm8962->pdata.codec_mclk);
++
+ ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
+ wm8962->supplies);
+ if (ret != 0) {
+@@ -3723,8 +3806,34 @@
+
+ wm8962_reset(wm8962);
+
++ /* SYSCLK defaults to on; make sure it is off so we can safely
++ * write to registers if the device is declocked.
++ */
++ regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
++ WM8962_SYSCLK_ENA, 0);
++
++ /* Ensure we have soft control over all registers */
++ regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2,
++ WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
++
++ /* Ensure that the oscillator and PLLs are disabled */
++ regmap_update_bits(wm8962->regmap, WM8962_PLL2,
++ WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
++ 0);
++
+ regcache_sync(wm8962->regmap);
+
++ regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
++ WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA,
++ WM8962_STARTUP_BIAS_ENA | WM8962_VMID_BUF_ENA);
++
++ /* Bias enable at 2*5k (fast start-up) */
++ regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
++ WM8962_BIAS_ENA | WM8962_VMID_SEL_MASK,
++ WM8962_BIAS_ENA | 0x180);
++
++ msleep(5);
++
+ return 0;
+ }
+
+@@ -3744,6 +3853,10 @@
+ regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
+ wm8962->supplies);
+
++ if (wm8962->pdata.codec_mclk)
++ clk_disable(wm8962->pdata.codec_mclk);
++
++
+ return 0;
+ }
+ #endif
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/eukrea-tlv320.c linux-linaro-stable-mx6/sound/soc/fsl/eukrea-tlv320.c
+--- linux-3.10.30.orig/sound/soc/fsl/eukrea-tlv320.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/eukrea-tlv320.c 2014-05-15 20:34:23.822199874 +0200
+@@ -80,7 +80,7 @@
+ .name = "tlv320aic23",
+ .stream_name = "TLV320AIC23",
+ .codec_dai_name = "tlv320aic23-hifi",
+- .platform_name = "imx-fiq-pcm-audio.0",
++ .platform_name = "imx-ssi.0",
+ .codec_name = "tlv320aic23-codec.0-001a",
+ .cpu_dai_name = "imx-ssi.0",
+ .ops = &eukrea_tlv320_snd_ops,
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_asrc.c linux-linaro-stable-mx6/sound/soc/fsl/fsl_asrc.c
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_asrc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_asrc.c 2014-05-15 20:34:23.822199874 +0200
+@@ -0,0 +1,500 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/of_i2c.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/mxc_asrc.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/initval.h>
++#include <sound/dmaengine_pcm.h>
++
++#include "fsl_asrc.h"
++#include "imx-pcm.h"
++
++static bool filter(struct dma_chan *chan, void *param)
++{
++ if (!imx_dma_is_general_purpose(chan))
++ return false;
++
++ chan->private = param;
++
++ return true;
++}
++
++static int asrc_p2p_request_channel(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct fsl_asrc_p2p *asrc_p2p = snd_soc_dai_get_drvdata(cpu_dai);
++ enum dma_slave_buswidth buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++ struct snd_dmaengine_dai_dma_data *dma_params_be = NULL;
++ struct snd_dmaengine_dai_dma_data *dma_params_fe = NULL;
++ struct imx_dma_data *fe_filter_data = NULL;
++ struct imx_dma_data *be_filter_data = NULL;
++
++ struct dma_slave_config slave_config;
++ dma_cap_mask_t mask;
++ struct dma_chan *chan;
++ int ret;
++ struct snd_soc_dpcm *dpcm;
++
++ /* find the be for this fe stream */
++ list_for_each_entry(dpcm, &rtd->dpcm[substream->stream].be_clients, list_be) {
++ if (dpcm->fe == rtd) {
++ struct snd_soc_pcm_runtime *be = dpcm->be;
++ struct snd_soc_dai *dai = be->cpu_dai;
++ struct snd_pcm_substream *be_substream;
++ be_substream = snd_soc_dpcm_get_substream(be, substream->stream);
++ dma_params_be = snd_soc_dai_get_dma_data(dai, be_substream);
++ break;
++ }
++ }
++
++ if (!dma_params_be) {
++ dev_err(rtd->card->dev, "can not get be substream\n");
++ return -EINVAL;
++ }
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ dma_params_fe = &asrc_p2p->dma_params_tx;
++ else
++ dma_params_fe = &asrc_p2p->dma_params_rx;
++
++ fe_filter_data = dma_params_fe->filter_data;
++ be_filter_data = dma_params_be->filter_data;
++
++ if (asrc_p2p->output_width == 16)
++ buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++ else
++ buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++
++ /* reconfig memory to FIFO dma request */
++ dma_params_fe->addr = asrc_p2p->asrc_ops.asrc_p2p_per_addr(
++ asrc_p2p->asrc_index, 1);
++ fe_filter_data->dma_request0 = asrc_p2p->dmarx[asrc_p2p->asrc_index];
++ dma_params_fe->maxburst = dma_params_be->maxburst;
++
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_CYCLIC, mask);
++
++ /* config p2p dma channel */
++ asrc_p2p->asrc_p2p_dma_data.peripheral_type = IMX_DMATYPE_ASRC;
++ asrc_p2p->asrc_p2p_dma_data.priority = DMA_PRIO_HIGH;
++ asrc_p2p->asrc_p2p_dma_data.dma_request1 = asrc_p2p->dmatx[asrc_p2p->asrc_index];
++ /* need to get target device's dma dma_addr, burstsize */
++ asrc_p2p->asrc_p2p_dma_data.dma_request0 = be_filter_data->dma_request0;
++
++ /* Request channel */
++ asrc_p2p->asrc_p2p_dma_chan =
++ dma_request_channel(mask, filter, &asrc_p2p->asrc_p2p_dma_data);
++
++ if (!asrc_p2p->asrc_p2p_dma_chan) {
++ dev_err(rtd->card->dev, "can not request dma channel\n");
++ goto error;
++ }
++ chan = asrc_p2p->asrc_p2p_dma_chan;
++
++ /*
++ * Buswidth is not used in the sdma for p2p. Here we set the maxburst fix to
++ * twice of dma_params's burstsize.
++ */
++ slave_config.direction = DMA_DEV_TO_DEV;
++ slave_config.src_addr = asrc_p2p->asrc_ops.asrc_p2p_per_addr(asrc_p2p->asrc_index, 0);
++ slave_config.src_addr_width = buswidth;
++ slave_config.src_maxburst = dma_params_be->maxburst * 2;
++ slave_config.dst_addr = dma_params_be->addr;
++ slave_config.dst_addr_width = buswidth;
++ slave_config.dst_maxburst = dma_params_be->maxburst * 2;
++ slave_config.dma_request0 = be_filter_data->dma_request0;
++ slave_config.dma_request1 = asrc_p2p->dmatx[asrc_p2p->asrc_index];
++
++ ret = dmaengine_slave_config(asrc_p2p->asrc_p2p_dma_chan,
++ &slave_config);
++ if (ret) {
++ dev_err(rtd->card->dev, "can not config dma channel\n");
++ goto error;
++ }
++
++ return 0;
++error:
++ if (asrc_p2p->asrc_p2p_dma_chan) {
++ dma_release_channel(asrc_p2p->asrc_p2p_dma_chan);
++ asrc_p2p->asrc_p2p_dma_chan = NULL;
++ }
++
++ return -EINVAL;
++}
++
++static int config_asrc(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct fsl_asrc_p2p *asrc_p2p = snd_soc_dai_get_drvdata(cpu_dai);
++ unsigned int rate = params_rate(params);
++ unsigned int channel = params_channels(params);
++ struct asrc_config config = {0};
++ int output_word_width = 0;
++ int input_word_width = 0;
++ int ret = 0;
++ if ((channel != 2) && (channel != 4) && (channel != 6)) {
++ dev_err(cpu_dai->dev, "param channel is not correct\n");
++ return -EINVAL;
++ }
++
++ ret = asrc_p2p->asrc_ops.asrc_p2p_req_pair(channel, &asrc_p2p->asrc_index);
++ if (ret < 0) {
++ dev_err(cpu_dai->dev, "Fail to request asrc pair\n");
++ return -EINVAL;
++ }
++
++ if (asrc_p2p->output_width == 16)
++ output_word_width = ASRC_WIDTH_16_BIT;
++ else
++ output_word_width = ASRC_WIDTH_24_BIT;
++
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_U16:
++ case SNDRV_PCM_FORMAT_S16_LE:
++ case SNDRV_PCM_FORMAT_S16_BE:
++ input_word_width = ASRC_WIDTH_16_BIT;
++ break;
++ case SNDRV_PCM_FORMAT_S20_3LE:
++ case SNDRV_PCM_FORMAT_S20_3BE:
++ case SNDRV_PCM_FORMAT_S24_3LE:
++ case SNDRV_PCM_FORMAT_S24_3BE:
++ case SNDRV_PCM_FORMAT_S24_BE:
++ case SNDRV_PCM_FORMAT_S24_LE:
++ case SNDRV_PCM_FORMAT_U24_BE:
++ case SNDRV_PCM_FORMAT_U24_LE:
++ case SNDRV_PCM_FORMAT_U24_3BE:
++ case SNDRV_PCM_FORMAT_U24_3LE:
++ input_word_width = ASRC_WIDTH_24_BIT;
++ break;
++ case SNDRV_PCM_FORMAT_S8:
++ case SNDRV_PCM_FORMAT_U8:
++ case SNDRV_PCM_FORMAT_S32:
++ case SNDRV_PCM_FORMAT_U32:
++ default:
++ dev_err(cpu_dai->dev, "Format is not support!\n");
++ return -EINVAL;
++ }
++
++ config.input_word_width = input_word_width;
++ config.output_word_width = output_word_width;
++ config.pair = asrc_p2p->asrc_index;
++ config.channel_num = channel;
++ config.input_sample_rate = rate;
++ config.output_sample_rate = asrc_p2p->output_rate;
++ config.inclk = INCLK_NONE;
++
++ switch (asrc_p2p->per_dev) {
++ case SSI1:
++ config.outclk = OUTCLK_SSI1_TX;
++ break;
++ case SSI2:
++ config.outclk = OUTCLK_SSI2_TX;
++ break;
++ case SSI3:
++ config.outclk = OUTCLK_SSI3_TX;
++ break;
++ case ESAI:
++ config.outclk = OUTCLK_ESAI_TX;
++ break;
++ default:
++ dev_err(cpu_dai->dev, "peripheral device is not correct\n");
++ return -EINVAL;
++ }
++
++ ret = asrc_p2p->asrc_ops.asrc_p2p_config_pair(&config);
++ if (ret < 0) {
++ dev_err(cpu_dai->dev, "Fail to config asrc\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static int fsl_asrc_p2p_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *cpu_dai)
++{
++ int ret = 0;
++
++ ret = config_asrc(substream, params);
++ if (ret < 0)
++ return ret;
++
++ return asrc_p2p_request_channel(substream);
++}
++
++static int fsl_asrc_p2p_hw_free(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_asrc_p2p *asrc_p2p = snd_soc_dai_get_drvdata(cpu_dai);
++
++ if (asrc_p2p->asrc_p2p_dma_chan) {
++ /* Release p2p dma resource */
++ dma_release_channel(asrc_p2p->asrc_p2p_dma_chan);
++ asrc_p2p->asrc_p2p_dma_chan = NULL;
++ }
++
++ if (asrc_p2p->asrc_index != -1) {
++ asrc_p2p->asrc_ops.asrc_p2p_release_pair(asrc_p2p->asrc_index);
++ asrc_p2p->asrc_ops.asrc_p2p_finish_conv(asrc_p2p->asrc_index);
++ }
++ asrc_p2p->asrc_index = -1;
++
++ return 0;
++}
++
++static int fsl_asrc_dma_prepare_and_submit(struct snd_pcm_substream *substream,
++ struct fsl_asrc_p2p *asrc_p2p)
++{
++ struct dma_async_tx_descriptor *desc = asrc_p2p->asrc_p2p_desc;
++ struct dma_chan *chan = asrc_p2p->asrc_p2p_dma_chan;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++
++ desc = dmaengine_prep_dma_cyclic(chan, 0xffff, 64, 64, DMA_DEV_TO_DEV, 0);
++ if (!desc) {
++ dev_err(dev, "failed to prepare slave dma\n");
++ return -EINVAL;
++ }
++
++ dmaengine_submit(desc);
++
++ return 0;
++}
++
++static int fsl_asrc_p2p_trigger(struct snd_pcm_substream *substream, int cmd,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_asrc_p2p *asrc_p2p = snd_soc_dai_get_drvdata(cpu_dai);
++ int ret;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ ret = fsl_asrc_dma_prepare_and_submit(substream, asrc_p2p);
++ if (ret)
++ return ret;
++ dma_async_issue_pending(asrc_p2p->asrc_p2p_dma_chan);
++ asrc_p2p->asrc_ops.asrc_p2p_start_conv(asrc_p2p->asrc_index);
++ break;
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ case SNDRV_PCM_TRIGGER_STOP:
++ dmaengine_terminate_all(asrc_p2p->asrc_p2p_dma_chan);
++ asrc_p2p->asrc_ops.asrc_p2p_stop_conv(asrc_p2p->asrc_index);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++#define IMX_ASRC_RATES SNDRV_PCM_RATE_8000_192000
++
++#define IMX_ASRC_FORMATS \
++ (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE | \
++ SNDRV_PCM_FORMAT_S20_3LE)
++
++static struct snd_soc_dai_ops fsl_asrc_p2p_dai_ops = {
++ .trigger = fsl_asrc_p2p_trigger,
++ .hw_params = fsl_asrc_p2p_hw_params,
++ .hw_free = fsl_asrc_p2p_hw_free,
++};
++
++static int fsl_asrc_p2p_dai_probe(struct snd_soc_dai *dai)
++{
++ struct fsl_asrc_p2p *asrc_p2p = snd_soc_dai_get_drvdata(dai);
++
++ dai->playback_dma_data = &asrc_p2p->dma_params_tx;
++ dai->capture_dma_data = &asrc_p2p->dma_params_rx;
++
++ return 0;
++}
++
++static struct snd_soc_dai_driver fsl_asrc_p2p_dai = {
++ .probe = fsl_asrc_p2p_dai_probe,
++ .playback = {
++ .stream_name = "asrc-Playback",
++ .channels_min = 1,
++ .channels_max = 10,
++ .rates = IMX_ASRC_RATES,
++ .formats = IMX_ASRC_FORMATS,
++ },
++ .capture = {
++ .stream_name = "asrc-Capture",
++ .channels_min = 1,
++ .channels_max = 4,
++ .rates = IMX_ASRC_RATES,
++ .formats = IMX_ASRC_FORMATS,
++ },
++ .ops = &fsl_asrc_p2p_dai_ops,
++};
++
++static const struct snd_soc_component_driver fsl_asrc_p2p_component = {
++ .name = "fsl-asrc-p2p",
++};
++
++/*
++ * This function will register the snd_soc_pcm_link drivers.
++ */
++static int fsl_asrc_p2p_probe(struct platform_device *pdev)
++{
++ struct fsl_asrc_p2p *asrc_p2p;
++ struct device_node *np = pdev->dev.of_node;
++ const char *p;
++ const uint32_t *iprop_rate, *iprop_width;
++ int ret = 0;
++
++ if (!of_device_is_available(np)) {
++ dev_err(&pdev->dev, "There is no device node\n");
++ return -ENODEV;
++ }
++
++ asrc_p2p = devm_kzalloc(&pdev->dev, sizeof(struct fsl_asrc_p2p), GFP_KERNEL);
++ if (!asrc_p2p) {
++ dev_err(&pdev->dev, "can not alloc memory\n");
++ return -ENOMEM;
++ }
++ asrc_p2p->asrc_ops.asrc_p2p_start_conv = asrc_start_conv;
++ asrc_p2p->asrc_ops.asrc_p2p_stop_conv = asrc_stop_conv;
++ asrc_p2p->asrc_ops.asrc_p2p_per_addr = asrc_get_per_addr;
++ asrc_p2p->asrc_ops.asrc_p2p_req_pair = asrc_req_pair;
++ asrc_p2p->asrc_ops.asrc_p2p_config_pair = asrc_config_pair;
++ asrc_p2p->asrc_ops.asrc_p2p_release_pair = asrc_release_pair;
++ asrc_p2p->asrc_ops.asrc_p2p_finish_conv = asrc_finish_conv;
++
++ asrc_p2p->asrc_index = -1;
++
++ iprop_rate = of_get_property(np, "fsl,output-rate", NULL);
++ if (iprop_rate)
++ asrc_p2p->output_rate = be32_to_cpup(iprop_rate);
++ else {
++ dev_err(&pdev->dev, "There is no output-rate in dts\n");
++ return -EINVAL;
++ }
++ iprop_width = of_get_property(np, "fsl,output-width", NULL);
++ if (iprop_width)
++ asrc_p2p->output_width = be32_to_cpup(iprop_width);
++
++ if (asrc_p2p->output_width != 16 && asrc_p2p->output_width != 24) {
++ dev_err(&pdev->dev, "output_width is not acceptable\n");
++ return -EINVAL;
++ }
++
++ ret = of_property_read_u32_array(np,
++ "fsl,asrc-dma-tx-events", asrc_p2p->dmatx, 3);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to get fsl,asrc-dma-tx-events.\n");
++ return -EINVAL;
++ }
++
++ ret = of_property_read_u32_array(np,
++ "fsl,asrc-dma-rx-events", asrc_p2p->dmarx, 3);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to get fsl,asrc-dma-rx-events.\n");
++ return -EINVAL;
++ }
++
++ asrc_p2p->filter_data_tx.peripheral_type = IMX_DMATYPE_ASRC;
++ asrc_p2p->filter_data_rx.peripheral_type = IMX_DMATYPE_ASRC;
++
++ asrc_p2p->dma_params_tx.filter_data = &asrc_p2p->filter_data_tx;
++ asrc_p2p->dma_params_rx.filter_data = &asrc_p2p->filter_data_rx;
++
++ platform_set_drvdata(pdev, asrc_p2p);
++
++ p = strrchr(np->full_name, '/') + 1;
++ strcpy(asrc_p2p->name, p);
++ fsl_asrc_p2p_dai.name = asrc_p2p->name;
++
++ ret = snd_soc_register_component(&pdev->dev, &fsl_asrc_p2p_component,
++ &fsl_asrc_p2p_dai, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "register DAI failed\n");
++ goto failed_register;
++ }
++
++ asrc_p2p->soc_platform_pdev = platform_device_register_simple(
++ "imx-pcm-asrc", -1, NULL, 0);
++ if (IS_ERR(asrc_p2p->soc_platform_pdev)) {
++ ret = PTR_ERR(asrc_p2p->soc_platform_pdev);
++ goto failed_pdev_alloc;
++ }
++
++ ret = imx_pcm_dma_init(asrc_p2p->soc_platform_pdev, SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
++ SND_DMAENGINE_PCM_FLAG_NO_DT |
++ SND_DMAENGINE_PCM_FLAG_COMPAT,
++ IMX_ASRC_DMABUF_SIZE);
++ if (ret) {
++ dev_err(&pdev->dev, "init pcm dma failed\n");
++ goto failed_pcm_init;
++ }
++
++ return 0;
++
++failed_pcm_init:
++ platform_device_unregister(asrc_p2p->soc_platform_pdev);
++failed_pdev_alloc:
++ snd_soc_unregister_component(&pdev->dev);
++failed_register:
++
++ return ret;
++}
++
++static int fsl_asrc_p2p_remove(struct platform_device *pdev)
++{
++ struct fsl_asrc_p2p *asrc_p2p = platform_get_drvdata(pdev);
++
++ imx_pcm_dma_exit(asrc_p2p->soc_platform_pdev);
++ platform_device_unregister(asrc_p2p->soc_platform_pdev);
++ snd_soc_unregister_component(&pdev->dev);
++
++ return 0;
++}
++
++static const struct of_device_id fsl_asrc_p2p_dt_ids[] = {
++ { .compatible = "fsl,imx6q-asrc-p2p", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver fsl_asrc_p2p_driver = {
++ .probe = fsl_asrc_p2p_probe,
++ .remove = fsl_asrc_p2p_remove,
++ .driver = {
++ .name = "fsl-asrc-p2p",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_asrc_p2p_dt_ids,
++ },
++};
++module_platform_driver(fsl_asrc_p2p_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX ASoC ASRC P2P driver");
++MODULE_ALIAS("platform:fsl-asrc-p2p");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_asrc.h linux-linaro-stable-mx6/sound/soc/fsl/fsl_asrc.h
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_asrc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_asrc.h 2014-05-15 20:34:23.822199874 +0200
+@@ -0,0 +1,48 @@
++/*
++ * fsl_asrc.h - ALSA ASRC interface
++ *
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. This file is licensed
++ * under the terms of the GNU General Public License version 2. This
++ * program is licensed "as is" without any warranty of any kind, whether
++ * express or implied.
++ */
++
++#ifndef _FSL_ASRC_P2P_H
++#define _FSL_ASRC_P2P_H
++
++#include <linux/mxc_asrc.h>
++#include <sound/dmaengine_pcm.h>
++#include <linux/platform_data/dma-imx.h>
++
++enum peripheral_device_type {
++ UNKNOWN,
++ SSI1,
++ SSI2,
++ SSI3,
++ ESAI,
++};
++
++struct fsl_asrc_p2p {
++ int output_rate;
++ int output_width;
++ enum asrc_pair_index asrc_index;
++ enum peripheral_device_type per_dev;
++ struct asrc_p2p_ops asrc_ops;
++
++ struct snd_dmaengine_dai_dma_data dma_params_rx;
++ struct snd_dmaengine_dai_dma_data dma_params_tx;
++ struct imx_dma_data filter_data_tx;
++ struct imx_dma_data filter_data_rx;
++
++ struct dma_async_tx_descriptor *asrc_p2p_desc;
++ struct dma_chan *asrc_p2p_dma_chan;
++ struct imx_dma_data asrc_p2p_dma_data;
++ struct platform_device *soc_platform_pdev;
++
++ int dmarx[3];
++ int dmatx[3];
++
++ char name[32];
++};
++
++#endif
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_asrc_pcm.c linux-linaro-stable-mx6/sound/soc/fsl/fsl_asrc_pcm.c
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_asrc_pcm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_asrc_pcm.c 2014-05-15 20:34:23.822199874 +0200
+@@ -0,0 +1,41 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++
++/*
++ * Here add one platform module "imx-pcm-asrc" as pcm platform module.
++ * If we use the asrc_p2p node as the pcm platform, there will be one issue.
++ * snd_soc_dapm_new_dai_widgets will be called twice, one in probe link_dais,
++ * one in probe platform. so there will be two dai_widgets added to widget list.
++ * but only the seconed one will be recorded in dai->playback_widget.
++ * Machine driver will add the audio route, but when it go through the
++ * widget list, it will found the cpu_dai widget is the first one in the list.
++ * add use the first one to link the audio route.
++ * when use the fe/be architecture for asrc p2p, it need to go through from
++ * the fe->cpu_dai->playback_widget. but this is the second widget, so the
++ * result is that it can't find a availble audio route for p2p case. So here
++ * use another pcm platform to avoid this issue.
++ */
++static struct platform_driver imx_pcm_driver = {
++ .driver = {
++ .name = "imx-pcm-asrc",
++ .owner = THIS_MODULE,
++ },
++};
++
++module_platform_driver(imx_pcm_driver);
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX ASoC PCM driver");
++MODULE_ALIAS("platform:imx-pcm-asrc");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_esai.c linux-linaro-stable-mx6/sound/soc/fsl/fsl_esai.c
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_esai.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_esai.c 2014-05-15 20:34:23.822199874 +0200
+@@ -0,0 +1,710 @@
++/*
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++ /*!
++ * @file fsl-esai.c
++ * @brief this file implements the esai interface
++ * in according to ASoC architeture
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++#include <linux/clk.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#include "fsl_esai.h"
++#include "imx-pcm.h"
++
++#define IMX_ESAI_NET (1 << 0)
++#define IMX_ESAI_SYN (1 << 1)
++
++static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 ecr, tccr, rccr;
++
++ ecr = readl(esai->base + ESAI_ECR);
++ tccr = readl(esai->base + ESAI_TCCR);
++ rccr = readl(esai->base + ESAI_RCCR);
++
++ if (dir == SND_SOC_CLOCK_IN) {
++ tccr &= ~(ESAI_TCCR_THCKD | ESAI_TCCR_TCKD | ESAI_TCCR_TFSD);
++ rccr &= ~(ESAI_RCCR_RHCKD | ESAI_RCCR_RCKD | ESAI_RCCR_RFSD);
++ } else {
++ tccr |= ESAI_TCCR_THCKD | ESAI_TCCR_TCKD | ESAI_TCCR_TFSD;
++ rccr |= ESAI_RCCR_RHCKD | ESAI_RCCR_RCKD | ESAI_RCCR_RFSD;
++
++ if (clk_id == ESAI_CLK_FSYS) {
++ ecr &= ~(ESAI_ECR_ETI | ESAI_ECR_ETO);
++ ecr &= ~(ESAI_ECR_ERI | ESAI_ECR_ERO);
++ } else if (clk_id == ESAI_CLK_EXTAL) {
++ ecr |= ESAI_ECR_ETI;
++ ecr |= ESAI_ECR_ETO;
++ ecr |= ESAI_ECR_ERI;
++ ecr |= ESAI_ECR_ERO;
++ } else if (clk_id == ESAI_CLK_EXTAL_DIV) {
++ ecr |= ESAI_ECR_ETI;
++ ecr &= ~ESAI_ECR_ETO;
++ ecr |= ESAI_ECR_ERI;
++ ecr &= ~ESAI_ECR_ERO;
++ }
++ }
++
++ writel(ecr, esai->base + ESAI_ECR);
++ writel(tccr, esai->base + ESAI_TCCR);
++ writel(rccr, esai->base + ESAI_RCCR);
++
++ ESAI_DUMP();
++ return 0;
++}
++
++static int fsl_esai_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
++ int div_id, int div)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 tccr, rccr;
++
++ tccr = readl(esai->base + ESAI_TCCR);
++ rccr = readl(esai->base + ESAI_RCCR);
++
++ switch (div_id) {
++ case ESAI_TX_DIV_PSR:
++ if ((div << ESAI_TCCR_TPSR_SHIFT) & ESAI_TCCR_TPSR_MASK)
++ return -EINVAL;
++ tccr &= ESAI_TCCR_TPSR_MASK;
++ if (div)
++ tccr |= ESAI_TCCR_TPSR_BYPASS;
++ else
++ tccr &= ~ESAI_TCCR_TPSR_DIV8;
++ break;
++ case ESAI_TX_DIV_PM:
++ if ((div << ESAI_TCCR_TPM_SHIFT) & ESAI_TCCR_TPM_MASK)
++ return -EINVAL;
++ tccr &= ESAI_TCCR_TPM_MASK;
++ tccr |= ESAI_TCCR_TPM(div);
++ break;
++ case ESAI_TX_DIV_FP:
++ if ((div << ESAI_TCCR_TFP_SHIFT) & ESAI_TCCR_TFP_MASK)
++ return -EINVAL;
++ tccr &= ESAI_TCCR_TFP_MASK;
++ tccr |= ESAI_TCCR_TFP(div);
++ break;
++ case ESAI_RX_DIV_PSR:
++ if ((div << ESAI_RCCR_RPSR_SHIFT) & ESAI_RCCR_RPSR_MASK)
++ return -EINVAL;
++ rccr &= ESAI_RCCR_RPSR_MASK;
++ if (div)
++ rccr |= ESAI_RCCR_RPSR_BYPASS;
++ else
++ rccr &= ~ESAI_RCCR_RPSR_DIV8;
++ break;
++ case ESAI_RX_DIV_PM:
++ if ((div << ESAI_RCCR_RPM_SHIFT) & ESAI_RCCR_RPM_MASK)
++ return -EINVAL;
++ rccr &= ESAI_RCCR_RPM_MASK;
++ rccr |= ESAI_RCCR_RPM(div);
++ break;
++ case ESAI_RX_DIV_FP:
++ if ((div << ESAI_RCCR_RFP_SHIFT) & ESAI_RCCR_RFP_MASK)
++ return -EINVAL;
++ rccr &= ESAI_RCCR_RFP_MASK;
++ rccr |= ESAI_RCCR_RFP(div);
++ break;
++ default:
++ return -EINVAL;
++ }
++ writel(tccr, esai->base + ESAI_TCCR);
++ writel(rccr, esai->base + ESAI_RCCR);
++ return 0;
++}
++
++/*
++ * ESAI Network Mode or TDM slots configuration.
++ */
++static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
++ unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 tccr, rccr;
++
++ tccr = readl(esai->base + ESAI_TCCR);
++
++ tccr &= ESAI_TCCR_TDC_MASK;
++ tccr |= ESAI_TCCR_TDC(slots - 1);
++
++ writel(tccr, esai->base + ESAI_TCCR);
++ writel((tx_mask & 0xffff), esai->base + ESAI_TSMA);
++ writel(((tx_mask >> 16) & 0xffff), esai->base + ESAI_TSMB);
++
++ rccr = readl(esai->base + ESAI_RCCR);
++
++ rccr &= ESAI_RCCR_RDC_MASK;
++ rccr |= ESAI_RCCR_RDC(slots - 1);
++
++ writel(rccr, esai->base + ESAI_RCCR);
++ writel((rx_mask & 0xffff), esai->base + ESAI_RSMA);
++ writel(((rx_mask >> 16) & 0xffff), esai->base + ESAI_RSMB);
++
++ ESAI_DUMP();
++ return 0;
++}
++
++/*
++ * ESAI DAI format configuration.
++ */
++static int fsl_esai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 tcr, tccr, rcr, rccr, saicr;
++
++ tcr = readl(esai->base + ESAI_TCR);
++ tccr = readl(esai->base + ESAI_TCCR);
++ rcr = readl(esai->base + ESAI_RCR);
++ rccr = readl(esai->base + ESAI_RCCR);
++ saicr = readl(esai->base + ESAI_SAICR);
++
++ /* DAI mode */
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ /* data on rising edge of bclk, frame low 1clk before data */
++ tcr &= ~ESAI_TCR_TFSL;
++ tcr |= ESAI_TCR_TFSR;
++ rcr &= ~ESAI_RCR_RFSL;
++ rcr |= ESAI_RCR_RFSR;
++ break;
++ case SND_SOC_DAIFMT_LEFT_J:
++ /* data on rising edge of bclk, frame high with data */
++ tcr &= ~(ESAI_TCR_TFSL | ESAI_TCR_TFSR);
++ rcr &= ~(ESAI_RCR_RFSL | ESAI_RCR_RFSR);
++ break;
++ case SND_SOC_DAIFMT_DSP_B:
++ /* data on rising edge of bclk, frame high with data */
++ tcr |= ESAI_TCR_TFSL;
++ rcr |= ESAI_RCR_RFSL;
++ break;
++ case SND_SOC_DAIFMT_DSP_A:
++ /* data on rising edge of bclk, frame high 1clk before data */
++ tcr |= ESAI_TCR_TFSL;
++ rcr |= ESAI_RCR_RFSL;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* DAI clock inversion */
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_IB_IF:
++ tccr |= ESAI_TCCR_TFSP;
++ tccr &= ~(ESAI_TCCR_TCKP | ESAI_TCCR_THCKP);
++ rccr &= ~(ESAI_RCCR_RCKP | ESAI_RCCR_RHCKP);
++ rccr |= ESAI_RCCR_RFSP;
++ break;
++ case SND_SOC_DAIFMT_IB_NF:
++ tccr &= ~(ESAI_TCCR_TCKP | ESAI_TCCR_THCKP | ESAI_TCCR_TFSP);
++ rccr &= ~(ESAI_RCCR_RCKP | ESAI_RCCR_RHCKP | ESAI_RCCR_RFSP);
++ break;
++ case SND_SOC_DAIFMT_NB_IF:
++ tccr |= ESAI_TCCR_TCKP | ESAI_TCCR_THCKP | ESAI_TCCR_TFSP;
++ rccr |= ESAI_RCCR_RCKP | ESAI_RCCR_RHCKP | ESAI_RCCR_RFSP;
++ break;
++ case SND_SOC_DAIFMT_NB_NF:
++ tccr &= ~ESAI_TCCR_TFSP;
++ tccr |= ESAI_TCCR_TCKP | ESAI_TCCR_THCKP;
++ rccr &= ~ESAI_RCCR_RFSP;
++ rccr |= ESAI_RCCR_RCKP | ESAI_RCCR_RHCKP;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* DAI clock master masks */
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBM_CFM:
++ tccr &= ~(ESAI_TCCR_TFSD | ESAI_TCCR_TCKD);
++ rccr &= ~(ESAI_RCCR_RFSD | ESAI_RCCR_RCKD);
++ break;
++ case SND_SOC_DAIFMT_CBS_CFM:
++ tccr &= ~ESAI_TCCR_TFSD;
++ tccr |= ESAI_TCCR_TCKD;
++ rccr &= ~ESAI_RCCR_RFSD;
++ rccr |= ESAI_RCCR_RCKD;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFS:
++ tccr &= ~ESAI_TCCR_TCKD;
++ tccr |= ESAI_TCCR_TFSD;
++ rccr &= ~ESAI_RCCR_RCKD;
++ rccr |= ESAI_RCCR_RFSD;
++ break;
++ case SND_SOC_DAIFMT_CBS_CFS:
++ tccr |= (ESAI_TCCR_TFSD | ESAI_TCCR_TCKD);
++ rccr |= (ESAI_RCCR_RFSD | ESAI_RCCR_RCKD);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* sync */
++ if (esai->flags & IMX_ESAI_SYN)
++ saicr |= ESAI_SAICR_SYNC;
++ else
++ saicr &= ~ESAI_SAICR_SYNC;
++
++ tcr &= ESAI_TCR_TMOD_MASK;
++ rcr &= ESAI_RCR_RMOD_MASK;
++ if (esai->flags & IMX_ESAI_NET) {
++ tcr |= ESAI_TCR_TMOD_NETWORK;
++ rcr |= ESAI_RCR_RMOD_NETWORK;
++ } else {
++ tcr |= ESAI_TCR_TMOD_NORMAL;
++ rcr |= ESAI_RCR_RMOD_NORMAL;
++ }
++
++ writel(tcr, esai->base + ESAI_TCR);
++ writel(tccr, esai->base + ESAI_TCCR);
++ writel(rcr, esai->base + ESAI_RCR);
++ writel(rccr, esai->base + ESAI_RCCR);
++
++ writel(saicr, esai->base + ESAI_SAICR);
++
++ ESAI_DUMP();
++ return 0;
++}
++
++static int fsl_esai_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++
++ clk_enable(esai->clk);
++ clk_prepare_enable(esai->dmaclk);
++ if (!cpu_dai->active) {
++ writel(ESAI_GPIO_ESAI, esai->base + ESAI_PRRC);
++ writel(ESAI_GPIO_ESAI, esai->base + ESAI_PCRC);
++ }
++ ESAI_DUMP();
++ return 0;
++}
++
++/*
++ * This function is called to initialize the TX port before enable
++ * the tx port.
++ */
++static int fsl_esai_hw_tx_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 tcr, tfcr;
++ unsigned int channels;
++
++ tcr = readl(esai->base + ESAI_TCR);
++ tfcr = readl(esai->base + ESAI_TFCR);
++
++ tfcr |= ESAI_TFCR_TFR;
++ writel(tfcr, esai->base + ESAI_TFCR);
++ tfcr &= ~ESAI_TFCR_TFR;
++ /* DAI data (word) size */
++ tfcr &= ESAI_TFCR_TWA_MASK;
++ tcr &= ESAI_TCR_TSWS_MASK;
++
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ tfcr |= ESAI_WORD_LEN_16;
++ tcr |= ESAI_TCR_TSHFD_MSB | ESAI_TCR_TSWS_STL32_WDL16;
++ break;
++ case SNDRV_PCM_FORMAT_S20_3LE:
++ tfcr |= ESAI_WORD_LEN_20;
++ tcr |= ESAI_TCR_TSHFD_MSB | ESAI_TCR_TSWS_STL32_WDL20;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ tfcr |= ESAI_WORD_LEN_24;
++ tcr |= ESAI_TCR_TSHFD_MSB | ESAI_TCR_TSWS_STL32_WDL24;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ channels = params_channels(params);
++ tfcr &= ESAI_TFCR_TE_MASK;
++ tfcr |= ESAI_TFCR_TE(channels);
++
++ tfcr |= ESAI_TFCR_TFWM(esai->fifo_depth);
++
++ /* Left aligned, Zero padding */
++ tcr |= ESAI_TCR_PADC;
++ /* TDR initialized from the FIFO */
++ tfcr |= ESAI_TFCR_TIEN;
++
++ writel(tcr, esai->base + ESAI_TCR);
++ writel(tfcr, esai->base + ESAI_TFCR);
++
++ ESAI_DUMP();
++ return 0;
++}
++
++/*
++ * This function is called to initialize the RX port before enable
++ * the rx port.
++ */
++static int fsl_esai_hw_rx_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 rcr, rfcr;
++ unsigned int channels;
++
++ rcr = readl(esai->base + ESAI_RCR);
++ rfcr = readl(esai->base + ESAI_RFCR);
++
++ rfcr |= ESAI_RFCR_RFR;
++ writel(rfcr, esai->base + ESAI_RFCR);
++ rfcr &= ~ESAI_RFCR_RFR;
++
++ rfcr &= ESAI_RFCR_RWA_MASK;
++ rcr &= ESAI_RCR_RSWS_MASK;
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ rfcr |= ESAI_WORD_LEN_16;
++ rcr |= ESAI_RCR_RSHFD_MSB | ESAI_RCR_RSWS_STL32_WDL16;
++ break;
++ case SNDRV_PCM_FORMAT_S20_3LE:
++ rfcr |= ESAI_WORD_LEN_20;
++ rcr |= ESAI_RCR_RSHFD_MSB | ESAI_RCR_RSWS_STL32_WDL20;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ rfcr |= ESAI_WORD_LEN_24;
++ rcr |= ESAI_RCR_RSHFD_MSB | ESAI_RCR_RSWS_STL32_WDL24;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ channels = params_channels(params);
++ rfcr &= ESAI_RFCR_RE_MASK;
++ rfcr |= ESAI_RFCR_RE(channels);
++
++ rfcr |= ESAI_RFCR_RFWM(esai->fifo_depth);
++
++ writel(rcr, esai->base + ESAI_RCR);
++ writel(rfcr, esai->base + ESAI_RFCR);
++
++ ESAI_DUMP();
++ return 0;
++}
++
++/*
++ * This function is called to initialize the TX or RX port,
++ */
++static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++
++ /* Tx/Rx config */
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ if (readl(esai->base + ESAI_TCR) & ESAI_TCR_TE0)
++ return 0;
++
++ return fsl_esai_hw_tx_params(substream, params, cpu_dai);
++ } else {
++ if (readl(esai->base + ESAI_RCR) & ESAI_RCR_RE1)
++ return 0;
++
++ return fsl_esai_hw_rx_params(substream, params, cpu_dai);
++ }
++}
++
++static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++
++ clk_disable_unprepare(esai->dmaclk);
++ clk_disable(esai->clk);
++}
++
++static int fsl_esai_trigger(struct snd_pcm_substream *substream, int cmd,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 reg, tfcr = 0, rfcr = 0;
++ int i;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ tfcr = readl(esai->base + ESAI_TFCR);
++ reg = readl(esai->base + ESAI_TCR);
++ } else {
++ rfcr = readl(esai->base + ESAI_RFCR);
++ reg = readl(esai->base + ESAI_RCR);
++ }
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ tfcr |= ESAI_TFCR_TFEN;
++ writel(tfcr, esai->base + ESAI_TFCR);
++ /* write initial words to ETDR register */
++ for (i = 0; i < substream->runtime->channels; i++)
++ writel(0x0, esai->base + ESAI_ETDR);
++ reg |= ESAI_TCR_TE(substream->runtime->channels);
++ writel(reg, esai->base + ESAI_TCR);
++ } else {
++ rfcr |= ESAI_RFCR_RFEN;
++ writel(rfcr, esai->base + ESAI_RFCR);
++ reg |= ESAI_RCR_RE(substream->runtime->channels);
++ writel(reg, esai->base + ESAI_RCR);
++ }
++ break;
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ reg &= ~ESAI_TCR_TE(substream->runtime->channels);
++ writel(reg, esai->base + ESAI_TCR);
++ tfcr |= ESAI_TFCR_TFR;
++ tfcr &= ~ESAI_TFCR_TFEN;
++ writel(tfcr, esai->base + ESAI_TFCR);
++ tfcr &= ~ESAI_TFCR_TFR;
++ writel(tfcr, esai->base + ESAI_TFCR);
++ } else {
++ reg &= ~ESAI_RCR_RE(substream->runtime->channels);
++ writel(reg, esai->base + ESAI_RCR);
++ rfcr |= ESAI_RFCR_RFR;
++ rfcr &= ~ESAI_RFCR_RFEN;
++ writel(rfcr, esai->base + ESAI_RFCR);
++ rfcr &= ~ESAI_RFCR_RFR;
++ writel(rfcr, esai->base + ESAI_RFCR);
++ }
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ ESAI_DUMP();
++ return 0;
++}
++
++#define IMX_ESAI_RATES SNDRV_PCM_RATE_8000_192000
++
++#define IMX_ESAI_FORMATS \
++ (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
++ SNDRV_PCM_FMTBIT_S24_LE)
++
++static struct snd_soc_dai_ops fsl_esai_dai_ops = {
++ .startup = fsl_esai_startup,
++ .shutdown = fsl_esai_shutdown,
++ .trigger = fsl_esai_trigger,
++ .hw_params = fsl_esai_hw_params,
++ .set_sysclk = fsl_esai_set_dai_sysclk,
++ .set_clkdiv = fsl_esai_set_dai_clkdiv,
++ .set_fmt = fsl_esai_set_dai_fmt,
++ .set_tdm_slot = fsl_esai_set_dai_tdm_slot,
++};
++
++static int fsl_esai_dai_probe(struct snd_soc_dai *dai)
++{
++ struct fsl_esai *esai = snd_soc_dai_get_drvdata(dai);
++
++ dai->playback_dma_data = &esai->dma_params_tx;
++ dai->capture_dma_data = &esai->dma_params_rx;
++ return 0;
++}
++
++static struct snd_soc_dai_driver fsl_esai_dai = {
++ .probe = fsl_esai_dai_probe,
++ .playback = {
++ .stream_name = "esai-Playback",
++ .channels_min = 1,
++ .channels_max = 12,
++ .rates = IMX_ESAI_RATES,
++ .formats = IMX_ESAI_FORMATS,
++ },
++ .capture = {
++ .stream_name = "esai-Capture",
++ .channels_min = 1,
++ .channels_max = 8,
++ .rates = IMX_ESAI_RATES,
++ .formats = IMX_ESAI_FORMATS,
++ },
++ .ops = &fsl_esai_dai_ops,
++};
++
++static const struct snd_soc_component_driver fsl_esai_component = {
++ .name = "fsl-esai",
++};
++
++static int fsl_esai_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct resource res;
++ struct fsl_esai *esai;
++ const uint32_t *iprop;
++ uint32_t flag;
++ const char *p;
++ u32 dma_events[2];
++ int ret = 0;
++
++ esai = devm_kzalloc(&pdev->dev, sizeof(*esai), GFP_KERNEL);
++ if (!esai) {
++ dev_err(&pdev->dev, "mem allocation failed\n");
++ return -ENOMEM;
++ }
++
++ ret = of_property_read_u32(np, "fsl,flags", &flag);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "There is no flag for esai\n");
++ return -EINVAL;
++ }
++ esai->flags = flag;
++
++ esai->clk = devm_clk_get(&pdev->dev, "core");
++ if (IS_ERR(esai->clk)) {
++ ret = PTR_ERR(esai->clk);
++ dev_err(&pdev->dev, "Cannot get the clock: %d\n", ret);
++ return ret;
++ }
++ clk_prepare(esai->clk);
++
++ esai->dmaclk = devm_clk_get(&pdev->dev, "dma");
++ if (IS_ERR(esai->dmaclk)) {
++ ret = PTR_ERR(esai->dmaclk);
++ dev_err(&pdev->dev, "Cannot get dma clock: %d\n", ret);
++ goto failed_get_resource;
++ }
++
++ ret = of_address_to_resource(np, 0, &res);
++ if (ret) {
++ dev_err(&pdev->dev, "could not determine device resources\n");
++ goto failed_get_resource;
++ }
++
++ esai->base = of_iomap(np, 0);
++ if (!esai->base) {
++ dev_err(&pdev->dev, "could not map device resources\n");
++ ret = -ENOMEM;
++ goto failed_iomap;
++ }
++
++ esai->irq = irq_of_parse_and_map(np, 0);
++
++ /* Determine the FIFO depth. */
++ iprop = of_get_property(np, "fsl,fifo-depth", NULL);
++ if (iprop)
++ esai->fifo_depth = be32_to_cpup(iprop);
++ else
++ esai->fifo_depth = 64;
++
++ esai->dma_params_tx.maxburst = 16;
++ esai->dma_params_rx.maxburst = 16;
++
++ esai->dma_params_tx.addr = res.start + ESAI_ETDR;
++ esai->dma_params_rx.addr = res.start + ESAI_ERDR;
++
++ esai->dma_params_tx.filter_data = &esai->filter_data_tx;
++ esai->dma_params_rx.filter_data = &esai->filter_data_rx;
++
++ ret = of_property_read_u32_array(pdev->dev.of_node,
++ "fsl,esai-dma-events", dma_events, 2);
++ if (ret) {
++ dev_err(&pdev->dev, "could not get dma events\n");
++ goto failed_get_dma;
++ }
++
++ esai->filter_data_tx.dma_request0 = dma_events[0];
++ esai->filter_data_rx.dma_request0 = dma_events[1];
++ esai->filter_data_tx.peripheral_type = IMX_DMATYPE_ESAI;
++ esai->filter_data_rx.peripheral_type = IMX_DMATYPE_ESAI;
++
++ platform_set_drvdata(pdev, esai);
++
++ p = strrchr(np->full_name, '/') + 1;
++ strcpy(esai->name, p);
++ fsl_esai_dai.name = esai->name;
++
++ ret = snd_soc_register_component(&pdev->dev, &fsl_esai_component,
++ &fsl_esai_dai, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "register DAI failed\n");
++ goto failed_register;
++ }
++
++ ret = imx_pcm_dma_init(pdev, SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
++ SND_DMAENGINE_PCM_FLAG_NO_DT |
++ SND_DMAENGINE_PCM_FLAG_COMPAT,
++ IMX_ESAI_DMABUF_SIZE);
++ if (ret) {
++ dev_err(&pdev->dev, "init pcm dma failed\n");
++ goto failed_pcm_init;
++ }
++
++ writel(ESAI_ECR_ERST, esai->base + ESAI_ECR);
++ writel(ESAI_ECR_ESAIEN, esai->base + ESAI_ECR);
++ return 0;
++
++failed_pcm_init:
++ snd_soc_unregister_component(&pdev->dev);
++failed_register:
++failed_get_dma:
++ irq_dispose_mapping(esai->irq);
++ iounmap(esai->base);
++failed_iomap:
++failed_get_resource:
++ clk_unprepare(esai->clk);
++ return ret;
++}
++
++static int fsl_esai_remove(struct platform_device *pdev)
++{
++ struct fsl_esai *esai = platform_get_drvdata(pdev);
++
++ imx_pcm_dma_exit(pdev);
++ snd_soc_unregister_component(&pdev->dev);
++
++ irq_dispose_mapping(esai->irq);
++ iounmap(esai->base);
++ clk_unprepare(esai->clk);
++ return 0;
++}
++
++static const struct of_device_id fsl_esai_ids[] = {
++ { .compatible = "fsl,imx6q-esai", },
++ {}
++};
++
++static struct platform_driver fsl_esai_driver = {
++ .probe = fsl_esai_probe,
++ .remove = fsl_esai_remove,
++ .driver = {
++ .name = "fsl-esai-dai",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_esai_ids,
++ },
++};
++
++module_platform_driver(fsl_esai_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX ASoC ESAI driver");
++MODULE_ALIAS("platform:fsl-esai-dai");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_esai.h linux-linaro-stable-mx6/sound/soc/fsl/fsl_esai.h
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_esai.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_esai.h 2014-05-15 20:34:23.822199874 +0200
+@@ -0,0 +1,335 @@
++/*
++ * imx-esai.h -- ESAI driver header file for Freescale IMX
++ *
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef _MXC_ESAI_H
++#define _MXC_ESAI_H
++
++#ifdef IMX_ESAI_DUMP
++#define ESAI_DUMP() \
++ do {pr_info("dump @ %s\n", __func__); \
++ pr_info("ESAI_ECR 0x%08x\n", readl(esai->base + ESAI_ECR)); \
++ pr_info("ESAI_ESR 0x%08x\n", readl(esai->base + ESAI_ESR)); \
++ pr_info("ESAI_TFCR 0x%08x\n", readl(esai->base + ESAI_TFCR)); \
++ pr_info("ESAI_TFSR 0x%08x\n", readl(esai->base + ESAI_TFSR)); \
++ pr_info("ESAI_RFCR 0x%08x\n", readl(esai->base + ESAI_RFCR)); \
++ pr_info("ESAI_RFSR 0x%08x\n", readl(esai->base + ESAI_RFSR)); \
++ pr_info("ESAI_TSR 0x%08x\n", readl(esai->base + ESAI_TSR)); \
++ pr_info("ESAI_SAISR 0x%08x\n", readl(esai->base + ESAI_SAISR)); \
++ pr_info("ESAI_SAICR 0x%08x\n", readl(esai->base + ESAI_SAICR)); \
++ pr_info("ESAI_TCR 0x%08x\n", readl(esai->base + ESAI_TCR)); \
++ pr_info("ESAI_TCCR 0x%08x\n", readl(esai->base + ESAI_TCCR)); \
++ pr_info("ESAI_RCR 0x%08x\n", readl(esai->base + ESAI_RCR)); \
++ pr_info("ESAI_RCCR 0x%08x\n", readl(esai->base + ESAI_RCCR)); \
++ pr_info("ESAI_TSMA 0x%08x\n", readl(esai->base + ESAI_TSMA)); \
++ pr_info("ESAI_TSMB 0x%08x\n", readl(esai->base + ESAI_TSMB)); \
++ pr_info("ESAI_RSMA 0x%08x\n", readl(esai->base + ESAI_RSMA)); \
++ pr_info("ESAI_RSMB 0x%08x\n", readl(esai->base + ESAI_RSMB)); \
++ pr_info("ESAI_PRRC 0x%08x\n", readl(esai->base + ESAI_PRRC)); \
++ pr_info("ESAI_PCRC 0x%08x\n", readl(esai->base + ESAI_PCRC)); \
++ } while (0);
++#else
++#define ESAI_DUMP()
++#endif
++
++#define ESAI_ETDR 0x00
++#define ESAI_ERDR 0x04
++#define ESAI_ECR 0x08
++#define ESAI_ESR 0x0C
++#define ESAI_TFCR 0x10
++#define ESAI_TFSR 0x14
++#define ESAI_RFCR 0x18
++#define ESAI_RFSR 0x1C
++#define ESAI_TX0 0x80
++#define ESAI_TX1 0x84
++#define ESAI_TX2 0x88
++#define ESAI_TX3 0x8C
++#define ESAI_TX4 0x90
++#define ESAI_TX5 0x94
++#define ESAI_TSR 0x98
++#define ESAI_RX0 0xA0
++#define ESAI_RX1 0xA4
++#define ESAI_RX2 0xA8
++#define ESAI_RX3 0xAC
++#define ESAI_SAISR 0xCC
++#define ESAI_SAICR 0xD0
++#define ESAI_TCR 0xD4
++#define ESAI_TCCR 0xD8
++#define ESAI_RCR 0xDC
++#define ESAI_RCCR 0xE0
++#define ESAI_TSMA 0xE4
++#define ESAI_TSMB 0xE8
++#define ESAI_RSMA 0xEC
++#define ESAI_RSMB 0xF0
++#define ESAI_PRRC 0xF8
++#define ESAI_PCRC 0xFC
++
++#define ESAI_ECR_ETI (1 << 19)
++#define ESAI_ECR_ETO (1 << 18)
++#define ESAI_ECR_ERI (1 << 17)
++#define ESAI_ECR_ERO (1 << 16)
++#define ESAI_ECR_ERST (1 << 1)
++#define ESAI_ECR_ESAIEN (1 << 0)
++
++#define ESAI_ESR_TINIT (1 << 10)
++#define ESAI_ESR_RFF (1 << 9)
++#define ESAI_ESR_TFE (1 << 8)
++#define ESAI_ESR_TLS (1 << 7)
++#define ESAI_ESR_TDE (1 << 6)
++#define ESAI_ESR_TED (1 << 5)
++#define ESAI_ESR_TD (1 << 4)
++#define ESAI_ESR_RLS (1 << 3)
++#define ESAI_ESR_RDE (1 << 2)
++#define ESAI_ESR_RED (1 << 1)
++#define ESAI_ESR_RD (1 << 0)
++
++#define ESAI_TFCR_TIEN (1 << 19)
++#define ESAI_TFCR_TE5 (1 << 7)
++#define ESAI_TFCR_TE4 (1 << 6)
++#define ESAI_TFCR_TE3 (1 << 5)
++#define ESAI_TFCR_TE2 (1 << 4)
++#define ESAI_TFCR_TE1 (1 << 3)
++#define ESAI_TFCR_TE0 (1 << 2)
++#define ESAI_TFCR_TFR (1 << 1)
++#define ESAI_TFCR_TFEN (1 << 0)
++#define ESAI_TFCR_TE(x) ((0x3f >> (6 - ((x + 1) >> 1))) << 2)
++#define ESAI_TFCR_TE_MASK 0xfff03
++#define ESAI_TFCR_TFWM(x) ((x - 1) << 8)
++#define ESAI_TFCR_TWA_MASK 0xf8ffff
++
++#define ESAI_RFCR_REXT (1 << 19)
++#define ESAI_RFCR_RE3 (1 << 5)
++#define ESAI_RFCR_RE2 (1 << 4)
++#define ESAI_RFCR_RE1 (1 << 3)
++#define ESAI_RFCR_RE0 (1 << 2)
++#define ESAI_RFCR_RFR (1 << 1)
++#define ESAI_RFCR_RFEN (1 << 0)
++#define ESAI_RFCR_RE(x) ((0xf >> (4 - ((x + 1) >> 1))) << 2)
++#define ESAI_RFCR_RE_MASK 0xfffc3
++#define ESAI_RFCR_RFWM(x) ((x-1) << 8)
++#define ESAI_RFCR_RWA_MASK 0xf8ffff
++
++#define ESAI_WORD_LEN_32 (0x00 << 16)
++#define ESAI_WORD_LEN_28 (0x01 << 16)
++#define ESAI_WORD_LEN_24 (0x02 << 16)
++#define ESAI_WORD_LEN_20 (0x03 << 16)
++#define ESAI_WORD_LEN_16 (0x04 << 16)
++#define ESAI_WORD_LEN_12 (0x05 << 16)
++#define ESAI_WORD_LEN_8 (0x06 << 16)
++#define ESAI_WORD_LEN_4 (0x07 << 16)
++
++#define ESAI_SAISR_TODFE (1 << 17)
++#define ESAI_SAISR_TEDE (1 << 16)
++#define ESAI_SAISR_TDE (1 << 15)
++#define ESAI_SAISR_TUE (1 << 14)
++#define ESAI_SAISR_TFS (1 << 13)
++#define ESAI_SAISR_RODF (1 << 10)
++#define ESAI_SAISR_REDF (1 << 9)
++#define ESAI_SAISR_RDF (1 << 8)
++#define ESAI_SAISR_ROE (1 << 7)
++#define ESAI_SAISR_RFS (1 << 6)
++#define ESAI_SAISR_IF2 (1 << 2)
++#define ESAI_SAISR_IF1 (1 << 1)
++#define ESAI_SAISR_IF0 (1 << 0)
++
++#define ESAI_SAICR_ALC (1 << 8)
++#define ESAI_SAICR_TEBE (1 << 7)
++#define ESAI_SAICR_SYNC (1 << 6)
++#define ESAI_SAICR_OF2 (1 << 2)
++#define ESAI_SAICR_OF1 (1 << 1)
++#define ESAI_SAICR_OF0 (1 << 0)
++
++#define ESAI_TCR_TLIE (1 << 23)
++#define ESAI_TCR_TIE (1 << 22)
++#define ESAI_TCR_TEDIE (1 << 21)
++#define ESAI_TCR_TEIE (1 << 20)
++#define ESAI_TCR_TPR (1 << 19)
++#define ESAI_TCR_PADC (1 << 17)
++#define ESAI_TCR_TFSR (1 << 16)
++#define ESAI_TCR_TFSL (1 << 15)
++#define ESAI_TCR_TWA (1 << 7)
++#define ESAI_TCR_TSHFD_MSB (0 << 6)
++#define ESAI_TCR_TSHFD_LSB (1 << 6)
++#define ESAI_TCR_TE5 (1 << 5)
++#define ESAI_TCR_TE4 (1 << 4)
++#define ESAI_TCR_TE3 (1 << 3)
++#define ESAI_TCR_TE2 (1 << 2)
++#define ESAI_TCR_TE1 (1 << 1)
++#define ESAI_TCR_TE0 (1 << 0)
++#define ESAI_TCR_TE(x) (0x3f >> (6 - ((x + 1) >> 1)))
++
++#define ESAI_TCR_TSWS_MASK 0xff83ff
++#define ESAI_TCR_TSWS_STL8_WDL8 (0x00 << 10)
++#define ESAI_TCR_TSWS_STL12_WDL8 (0x04 << 10)
++#define ESAI_TCR_TSWS_STL12_WDL12 (0x01 << 10)
++#define ESAI_TCR_TSWS_STL16_WDL8 (0x08 << 10)
++#define ESAI_TCR_TSWS_STL16_WDL12 (0x05 << 10)
++#define ESAI_TCR_TSWS_STL16_WDL16 (0x02 << 10)
++#define ESAI_TCR_TSWS_STL20_WDL8 (0x0c << 10)
++#define ESAI_TCR_TSWS_STL20_WDL12 (0x09 << 10)
++#define ESAI_TCR_TSWS_STL20_WDL16 (0x06 << 10)
++#define ESAI_TCR_TSWS_STL20_WDL20 (0x03 << 10)
++#define ESAI_TCR_TSWS_STL24_WDL8 (0x10 << 10)
++#define ESAI_TCR_TSWS_STL24_WDL12 (0x0d << 10)
++#define ESAI_TCR_TSWS_STL24_WDL16 (0x0a << 10)
++#define ESAI_TCR_TSWS_STL24_WDL20 (0x07 << 10)
++#define ESAI_TCR_TSWS_STL24_WDL24 (0x1e << 10)
++#define ESAI_TCR_TSWS_STL32_WDL8 (0x18 << 10)
++#define ESAI_TCR_TSWS_STL32_WDL12 (0x15 << 10)
++#define ESAI_TCR_TSWS_STL32_WDL16 (0x12 << 10)
++#define ESAI_TCR_TSWS_STL32_WDL20 (0x0f << 10)
++#define ESAI_TCR_TSWS_STL32_WDL24 (0x1f << 10)
++
++#define ESAI_TCR_TMOD_MASK 0xfffcff
++#define ESAI_TCR_TMOD_NORMAL (0x00 << 8)
++#define ESAI_TCR_TMOD_ONDEMAND (0x01 << 8)
++#define ESAI_TCR_TMOD_NETWORK (0x01 << 8)
++#define ESAI_TCR_TMOD_RESERVED (0x02 << 8)
++#define ESAI_TCR_TMOD_AC97 (0x03 << 8)
++
++#define ESAI_TCCR_THCKD (1 << 23)
++#define ESAI_TCCR_TFSD (1 << 22)
++#define ESAI_TCCR_TCKD (1 << 21)
++#define ESAI_TCCR_THCKP (1 << 20)
++#define ESAI_TCCR_TFSP (1 << 19)
++#define ESAI_TCCR_TCKP (1 << 18)
++
++#define ESAI_TCCR_TPSR_MASK 0xfffeff
++#define ESAI_TCCR_TPSR_SHIFT 8
++#define ESAI_TCCR_TPSR_BYPASS (1 << 8)
++#define ESAI_TCCR_TPSR_DIV8 (0 << 8)
++
++#define ESAI_TCCR_TFP_MASK 0xfc3fff
++#define ESAI_TCCR_TFP_SHIFT 14
++#define ESAI_TCCR_TFP(x) ((x & 0xf) << 14)
++
++#define ESAI_TCCR_TDC_MASK 0xffc1ff
++#define ESAI_TCCR_TDC_SHIFT 9
++#define ESAI_TCCR_TDC(x) (((x) & 0x1f) << 9)
++
++#define ESAI_TCCR_TPM_MASK 0xffff00
++#define ESAI_TCCR_TPM_SHIFT 0
++#define ESAI_TCCR_TPM(x) (x & 0xff)
++
++#define ESAI_RCR_RLIE (1 << 23)
++#define ESAI_RCR_RIE (1 << 22)
++#define ESAI_RCR_REDIE (1 << 21)
++#define ESAI_RCR_REIE (1 << 20)
++#define ESAI_RCR_RPR (1 << 19)
++#define ESAI_RCR_RFSR (1 << 16)
++#define ESAI_RCR_RFSL (1 << 15)
++#define ESAI_RCR_RWA (1 << 7)
++#define ESAI_RCR_RSHFD_MSB (0 << 6)
++#define ESAI_RCR_RSHFD_LSB (1 << 6)
++#define ESAI_RCR_RE3 (1 << 3)
++#define ESAI_RCR_RE2 (1 << 2)
++#define ESAI_RCR_RE1 (1 << 1)
++#define ESAI_RCR_RE0 (1 << 0)
++#define ESAI_RCR_RE(x) (0xf >> (4 - ((x + 1) >> 1)))
++
++#define ESAI_RCR_RSWS_MASK 0xff83ff
++#define ESAI_RCR_RSWS_STL8_WDL8 (0x00 << 10)
++#define ESAI_RCR_RSWS_STL12_WDL8 (0x04 << 10)
++#define ESAI_RCR_RSWS_STL12_WDL12 (0x01 << 10)
++#define ESAI_RCR_RSWS_STL16_WDL8 (0x08 << 10)
++#define ESAI_RCR_RSWS_STL16_WDL12 (0x05 << 10)
++#define ESAI_RCR_RSWS_STL16_WDL16 (0x02 << 10)
++#define ESAI_RCR_RSWS_STL20_WDL8 (0x0c << 10)
++#define ESAI_RCR_RSWS_STL20_WDL12 (0x09 << 10)
++#define ESAI_RCR_RSWS_STL20_WDL16 (0x06 << 10)
++#define ESAI_RCR_RSWS_STL20_WDL20 (0x03 << 10)
++#define ESAI_RCR_RSWS_STL24_WDL8 (0x10 << 10)
++#define ESAI_RCR_RSWS_STL24_WDL12 (0x0d << 10)
++#define ESAI_RCR_RSWS_STL24_WDL16 (0x0a << 10)
++#define ESAI_RCR_RSWS_STL24_WDL20 (0x07 << 10)
++#define ESAI_RCR_RSWS_STL24_WDL24 (0x1e << 10)
++#define ESAI_RCR_RSWS_STL32_WDL8 (0x18 << 10)
++#define ESAI_RCR_RSWS_STL32_WDL12 (0x15 << 10)
++#define ESAI_RCR_RSWS_STL32_WDL16 (0x12 << 10)
++#define ESAI_RCR_RSWS_STL32_WDL20 (0x0f << 10)
++#define ESAI_RCR_RSWS_STL32_WDL24 (0x1f << 10)
++
++#define ESAI_RCR_RMOD_MASK 0xfffcff
++#define ESAI_RCR_RMOD_NORMAL (0x00 << 8)
++#define ESAI_RCR_RMOD_ONDEMAND (0x01 << 8)
++#define ESAI_RCR_RMOD_NETWORK (0x01 << 8)
++#define ESAI_RCR_RMOD_RESERVED (0x02 << 8)
++#define ESAI_RCR_RMOD_AC97 (0x03 << 8)
++
++#define ESAI_RCCR_RHCKD (1 << 23)
++#define ESAI_RCCR_RFSD (1 << 22)
++#define ESAI_RCCR_RCKD (1 << 21)
++#define ESAI_RCCR_RHCKP (1 << 20)
++#define ESAI_RCCR_RFSP (1 << 19)
++#define ESAI_RCCR_RCKP (1 << 18)
++
++#define ESAI_RCCR_RPSR_MASK 0xfffeff
++#define ESAI_RCCR_RPSR_SHIFT 8
++#define ESAI_RCCR_RPSR_BYPASS (1 << 8)
++#define ESAI_RCCR_RPSR_DIV8 (0 << 8)
++
++#define ESAI_RCCR_RFP_MASK 0xfc3fff
++#define ESAI_RCCR_RFP_SHIFT 14
++#define ESAI_RCCR_RFP(x) ((x & 0xf) << 14)
++
++#define ESAI_RCCR_RDC_MASK 0xffc1ff
++#define ESAI_RCCR_RDC_SHIFT 9
++#define ESAI_RCCR_RDC(x) (((x) & 0x1f) << 9)
++
++#define ESAI_RCCR_RPM_MASK 0xffff00
++#define ESAI_RCCR_RPM_SHIFT 0
++#define ESAI_RCCR_RPM(x) (x & 0xff)
++
++#define ESAI_GPIO_ESAI 0xfff
++
++/* ESAI clock source */
++#define ESAI_CLK_FSYS 0
++#define ESAI_CLK_EXTAL 1
++#define ESAI_CLK_EXTAL_DIV 2
++
++/* ESAI clock divider */
++#define ESAI_TX_DIV_PSR 0
++#define ESAI_TX_DIV_PM 1
++#define ESAI_TX_DIV_FP 2
++#define ESAI_RX_DIV_PSR 3
++#define ESAI_RX_DIV_PM 4
++#define ESAI_RX_DIV_FP 5
++
++#define DRV_NAME "imx-esai"
++
++#include <linux/dmaengine.h>
++#include <sound/dmaengine_pcm.h>
++#include <linux/platform_data/dma-imx.h>
++
++#define IMX_DAI_ESAI_TX 0x04
++#define IMX_DAI_ESAI_RX 0x08
++#define IMX_DAI_ESAI_TXRX (IMX_DAI_ESAI_TX | IMX_DAI_ESAI_RX)
++
++struct fsl_esai {
++ struct clk *clk;
++ struct clk *dmaclk;
++ void __iomem *base;
++ int irq;
++ unsigned int flags;
++ unsigned int fifo_depth;
++
++ struct snd_dmaengine_dai_dma_data dma_params_rx;
++ struct snd_dmaengine_dai_dma_data dma_params_tx;
++ struct imx_dma_data filter_data_tx;
++ struct imx_dma_data filter_data_rx;
++
++ char name[32];
++};
++
++#endif
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_hdmi.c linux-linaro-stable-mx6/sound/soc/fsl/fsl_hdmi.c
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_hdmi.c 2014-05-15 20:34:23.822199874 +0200
+@@ -0,0 +1,614 @@
++/*
++ * ALSA SoC HDMI Audio Layer for Freescale i.MX
++ *
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * Some code from patch_hdmi.c
++ * Copyright (c) 2008-2010 Intel Corporation. All rights reserved.
++ * Copyright (c) 2006 ATI Technologies Inc.
++ * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
++ * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/asoundef.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "imx-hdmi.h"
++
++
++static struct mxc_edid_cfg edid_cfg;
++
++static u32 playback_rates[HDMI_MAX_RATES];
++static u32 playback_sample_size[HDMI_MAX_SAMPLE_SIZE];
++static u32 playback_channels[HDMI_MAX_CHANNEL_CONSTRAINTS];
++
++static struct snd_pcm_hw_constraint_list playback_constraint_rates;
++static struct snd_pcm_hw_constraint_list playback_constraint_bits;
++static struct snd_pcm_hw_constraint_list playback_constraint_channels;
++
++#ifdef DEBUG
++static void dumpregs(struct snd_soc_dai *dai)
++{
++ u32 n, cts;
++
++ cts = (hdmi_readb(HDMI_AUD_CTS3) << 16) |
++ (hdmi_readb(HDMI_AUD_CTS2) << 8) |
++ hdmi_readb(HDMI_AUD_CTS1);
++
++ n = (hdmi_readb(HDMI_AUD_N3) << 16) |
++ (hdmi_readb(HDMI_AUD_N2) << 8) |
++ hdmi_readb(HDMI_AUD_N1);
++
++ dev_debug(dai->dev, "HDMI_PHY_CONF0 0x%02x\n",
++ hdmi_readb(HDMI_PHY_CONF0));
++ dev_debug(dai->dev, "HDMI_MC_CLKDIS 0x%02x\n",
++ hdmi_readb(HDMI_MC_CLKDIS));
++ dev_debug(dai->dev, "HDMI_AUD_N[1-3] 0x%06x (%d)\n",
++ n, n);
++ dev_debug(dai->dev, "HDMI_AUD_CTS[1-3] 0x%06x (%d)\n",
++ cts, cts);
++ dev_debug(dai->dev, "HDMI_FC_AUDSCONF 0x%02x\n",
++ hdmi_readb(HDMI_FC_AUDSCONF));
++}
++#else
++static void dumpregs(struct snd_soc_dai *dai) {}
++#endif
++
++enum cea_speaker_placement {
++ FL = (1 << 0), /* Front Left */
++ FC = (1 << 1), /* Front Center */
++ FR = (1 << 2), /* Front Right */
++ FLC = (1 << 3), /* Front Left Center */
++ FRC = (1 << 4), /* Front Right Center */
++ RL = (1 << 5), /* Rear Left */
++ RC = (1 << 6), /* Rear Center */
++ RR = (1 << 7), /* Rear Right */
++ RLC = (1 << 8), /* Rear Left Center */
++ RRC = (1 << 9), /* Rear Right Center */
++ LFE = (1 << 10), /* Low Frequency Effect */
++ FLW = (1 << 11), /* Front Left Wide */
++ FRW = (1 << 12), /* Front Right Wide */
++ FLH = (1 << 13), /* Front Left High */
++ FCH = (1 << 14), /* Front Center High */
++ FRH = (1 << 15), /* Front Right High */
++ TC = (1 << 16), /* Top Center */
++};
++
++/*
++ * EDID SA bits in the CEA Speaker Allocation data block
++ */
++static int edid_speaker_allocation_bits[] = {
++ [0] = FL | FR,
++ [1] = LFE,
++ [2] = FC,
++ [3] = RL | RR,
++ [4] = RC,
++ [5] = FLC | FRC,
++ [6] = RLC | RRC,
++ [7] = FLW | FRW,
++ [8] = FLH | FRH,
++ [9] = TC,
++ [10] = FCH,
++};
++
++struct cea_channel_speaker_allocation {
++ int ca_index;
++ int speakers[8];
++
++ /* Derived values, just for convenience */
++ int channels;
++ int spk_mask;
++};
++
++/*
++ * This is an ordered list!
++ *
++ * The preceding ones have better chances to be selected by
++ * hdmi_channel_allocation().
++ */
++static struct cea_channel_speaker_allocation channel_allocations[] = {
++ /* channel: 7 6 5 4 3 2 1 0 */
++ { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL },},
++ /* 2.1 */
++ { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL },},
++ /* Dolby Surround */
++ { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL },},
++ { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL },},
++ { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL },},
++ { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL },},
++ { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL },},
++ { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL },},
++ { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL },},
++ /* surround51 */
++ { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL },},
++ /* 6.1 */
++ { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL },},
++ /* surround71 */
++ { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL },},
++ { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL },},
++ { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL },},
++ { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL },},
++ { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL },},
++ { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL },},
++ { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL },},
++ { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL },},
++ { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL },},
++};
++
++/* Compute derived values in channel_allocations[] */
++static void init_channel_allocations(void)
++{
++ struct cea_channel_speaker_allocation *p;
++ int i, j;
++
++ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
++ p = channel_allocations + i;
++ p->channels = 0;
++ p->spk_mask = 0;
++ for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
++ if (p->speakers[j]) {
++ p->channels++;
++ p->spk_mask |= p->speakers[j];
++ }
++ }
++}
++
++/*
++ * The transformation takes two steps:
++ *
++ * speaker_alloc => (edid_speaker_allocation_bits[]) => spk_mask
++ * spk_mask => (channel_allocations[]) => CA
++ *
++ * TODO: it could select the wrong CA from multiple candidates.
++*/
++static int hdmi_channel_allocation(int channels)
++{
++ int spk_mask = 0, ca = 0, i, tmpchn, tmpspk;
++
++ /* CA defaults to 0 for basic stereo audio */
++ if (channels <= 2)
++ return 0;
++
++ /*
++ * Expand EDID's speaker allocation mask
++ *
++ * EDID tells the speaker mask in a compact(paired) form,
++ * expand EDID's notions to match the ones used by Audio InfoFrame.
++ */
++ for (i = 0; i < ARRAY_SIZE(edid_speaker_allocation_bits); i++) {
++ if (edid_cfg.speaker_alloc & (1 << i))
++ spk_mask |= edid_speaker_allocation_bits[i];
++ }
++
++ /* Search for the first working match in the CA table */
++ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
++ tmpchn = channel_allocations[i].channels;
++ tmpspk = channel_allocations[i].spk_mask;
++
++ if (channels == tmpchn && (spk_mask & tmpspk) == tmpspk) {
++ ca = channel_allocations[i].ca_index;
++ break;
++ }
++ }
++
++ return ca;
++}
++
++static void hdmi_set_audio_infoframe(unsigned int channels)
++{
++ u8 audiconf0, audiconf2;
++
++ /*
++ * From CEA-861-D spec:
++ * HDMI requires the CT, SS and SF fields to be set to 0 ("Refer
++ * to Stream Header") as these items are carried in the audio stream.
++ *
++ * So we only set the CC and CA fields.
++ */
++ audiconf0 = ((channels - 1) << HDMI_FC_AUDICONF0_CC_OFFSET) &
++ HDMI_FC_AUDICONF0_CC_MASK;
++
++ audiconf2 = hdmi_channel_allocation(channels);
++
++ hdmi_writeb(audiconf0, HDMI_FC_AUDICONF0);
++ hdmi_writeb(0, HDMI_FC_AUDICONF1);
++ hdmi_writeb(audiconf2, HDMI_FC_AUDICONF2);
++ hdmi_writeb(0, HDMI_FC_AUDICONF3);
++}
++
++static int cea_audio_rates[HDMI_MAX_RATES] = {
++ 32000, 44100, 48000, 88200, 96000, 176400, 192000,
++};
++
++static void fsl_hdmi_get_playback_rates(void)
++{
++ int i, count = 0;
++ u8 rates;
++
++ /* Always assume basic audio support */
++ rates = edid_cfg.sample_rates | 0x7;
++
++ for (i = 0 ; i < HDMI_MAX_RATES ; i++)
++ if ((rates & (1 << i)) != 0)
++ playback_rates[count++] = cea_audio_rates[i];
++
++ playback_constraint_rates.list = playback_rates;
++ playback_constraint_rates.count = count;
++
++ for (i = 0 ; i < playback_constraint_rates.count ; i++)
++ pr_debug("%s: constraint = %d Hz\n", __func__, playback_rates[i]);
++}
++
++static void fsl_hdmi_get_playback_sample_size(void)
++{
++ int i = 0;
++
++ /* Always assume basic audio support */
++ playback_sample_size[i++] = 16;
++
++ if (edid_cfg.sample_sizes & 0x4)
++ playback_sample_size[i++] = 24;
++
++ playback_constraint_bits.list = playback_sample_size;
++ playback_constraint_bits.count = i;
++
++ for (i = 0 ; i < playback_constraint_bits.count ; i++)
++ pr_debug("%s: constraint = %d bits\n", __func__, playback_sample_size[i]);
++}
++
++static void fsl_hdmi_get_playback_channels(void)
++{
++ int channels = 2, i = 0;
++
++ /* Always assume basic audio support */
++ playback_channels[i++] = channels;
++ channels += 2;
++
++ while ((i < HDMI_MAX_CHANNEL_CONSTRAINTS) &&
++ (channels <= edid_cfg.max_channels)) {
++ playback_channels[i++] = channels;
++ channels += 2;
++ }
++
++ playback_constraint_channels.list = playback_channels;
++ playback_constraint_channels.count = i;
++
++ for (i = 0 ; i < playback_constraint_channels.count ; i++)
++ pr_debug("%s: constraint = %d channels\n", __func__, playback_channels[i]);
++}
++
++static int fsl_hdmi_update_constraints(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ int ret;
++
++ hdmi_get_edid_cfg(&edid_cfg);
++
++ if (!edid_cfg.hdmi_cap)
++ return -1;
++
++ fsl_hdmi_get_playback_rates();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
++ &playback_constraint_rates);
++ if (ret)
++ return ret;
++
++ fsl_hdmi_get_playback_sample_size();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
++ &playback_constraint_bits);
++ if (ret)
++ return ret;
++
++ fsl_hdmi_get_playback_channels();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
++ &playback_constraint_channels);
++ if (ret)
++ return ret;
++
++ ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int fsl_hdmi_soc_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct imx_hdmi *hdmi_data = snd_soc_dai_get_drvdata(dai);
++ int ret;
++
++ ret = fsl_hdmi_update_constraints(substream);
++ if (ret < 0)
++ return ret;
++
++ clk_prepare_enable(hdmi_data->isfr_clk);
++ clk_prepare_enable(hdmi_data->iahb_clk);
++
++ dev_dbg(dai->dev, "%s hdmi clks: isfr:%d iahb:%d\n", __func__,
++ (int)clk_get_rate(hdmi_data->isfr_clk),
++ (int)clk_get_rate(hdmi_data->iahb_clk));
++
++ /* Indicates the subpacket represents a flatline sample */
++ hdmi_audio_writeb(FC_AUDSCONF, AUD_PACKET_SAMPFIT, 0x0);
++
++ return 0;
++}
++
++static void fsl_hdmi_soc_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct imx_hdmi *hdmi_data = snd_soc_dai_get_drvdata(dai);
++
++ clk_disable_unprepare(hdmi_data->iahb_clk);
++ clk_disable_unprepare(hdmi_data->isfr_clk);
++}
++
++static int fsl_hdmi_soc_prepare(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++
++ hdmi_set_audio_infoframe(runtime->channels);
++ hdmi_audio_writeb(FC_AUDSCONF, AUD_PACKET_LAYOUT,
++ (runtime->channels > 2) ? 0x1 : 0x0);
++ hdmi_set_sample_rate(runtime->rate);
++ dumpregs(dai);
++
++ return 0;
++}
++
++static struct snd_soc_dai_ops fsl_hdmi_soc_dai_ops = {
++ .startup = fsl_hdmi_soc_startup,
++ .shutdown = fsl_hdmi_soc_shutdown,
++ .prepare = fsl_hdmi_soc_prepare,
++};
++
++/* IEC60958 status functions */
++static int fsl_hdmi_iec_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
++ uinfo->count = 1;
++
++ return 0;
++}
++
++
++static int fsl_hdmi_iec_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++
++ for (i = 0 ; i < 4 ; i++)
++ uvalue->value.iec958.status[i] = iec_header.status[i];
++
++ return 0;
++}
++
++static int fsl_hdmi_iec_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++
++ /* Do not allow professional mode */
++ if (uvalue->value.iec958.status[0] & IEC958_AES0_PROFESSIONAL)
++ return -EPERM;
++
++ for (i = 0 ; i < 4 ; i++) {
++ iec_header.status[i] = uvalue->value.iec958.status[i];
++ pr_debug("%s status[%d]=0x%02x\n", __func__, i, iec_header.status[i]);
++ }
++
++ return 0;
++}
++
++static struct snd_kcontrol_new fsl_hdmi_ctrls[] = {
++ /* Status cchanel controller */
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_WRITE |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_hdmi_iec_info,
++ .get = fsl_hdmi_iec_get,
++ .put = fsl_hdmi_iec_put,
++ },
++};
++
++static int fsl_hdmi_soc_dai_probe(struct snd_soc_dai *dai)
++{
++ int ret;
++
++ init_channel_allocations();
++
++ ret = snd_soc_add_dai_controls(dai, fsl_hdmi_ctrls,
++ ARRAY_SIZE(fsl_hdmi_ctrls));
++ if (ret)
++ dev_warn(dai->dev, "failed to add dai controls\n");
++
++ return 0;
++}
++
++static struct snd_soc_dai_driver fsl_hdmi_dai = {
++ .probe = &fsl_hdmi_soc_dai_probe,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 8,
++ .rates = MXC_HDMI_RATES_PLAYBACK,
++ .formats = MXC_HDMI_FORMATS_PLAYBACK,
++ },
++ .ops = &fsl_hdmi_soc_dai_ops,
++};
++
++static const struct snd_soc_component_driver fsl_hdmi_component = {
++ .name = "fsl-hdmi",
++};
++
++static int fsl_hdmi_dai_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct imx_hdmi *hdmi_data;
++ int ret = 0;
++
++ if (!np)
++ return -ENODEV;
++
++ if (!hdmi_get_registered()) {
++ dev_err(&pdev->dev, "failed to probe. Load HDMI-video first.\n");
++ return -ENOMEM;
++ }
++
++ hdmi_data = devm_kzalloc(&pdev->dev, sizeof(*hdmi_data), GFP_KERNEL);
++ if (!hdmi_data) {
++ dev_err(&pdev->dev, "failed to alloc hdmi_data\n");
++ return -ENOMEM;
++ }
++
++ hdmi_data->pdev = pdev;
++
++ memcpy(&hdmi_data->cpu_dai_drv, &fsl_hdmi_dai, sizeof(fsl_hdmi_dai));
++ hdmi_data->cpu_dai_drv.name = np->name;
++
++ hdmi_data->isfr_clk = devm_clk_get(&pdev->dev, "hdmi_isfr");
++ if (IS_ERR(hdmi_data->isfr_clk)) {
++ ret = PTR_ERR(hdmi_data->isfr_clk);
++ dev_err(&pdev->dev, "failed to get HDMI isfr clk: %d\n", ret);
++ return -EINVAL;
++ }
++
++ hdmi_data->iahb_clk = devm_clk_get(&pdev->dev, "hdmi_iahb");
++ if (IS_ERR(hdmi_data->iahb_clk)) {
++ ret = PTR_ERR(hdmi_data->iahb_clk);
++ dev_err(&pdev->dev, "failed to get HDMI ahb clk: %d\n", ret);
++ return -EINVAL;
++ }
++
++ dev_set_drvdata(&pdev->dev, hdmi_data);
++ ret = snd_soc_register_component(&pdev->dev, &fsl_hdmi_component,
++ &hdmi_data->cpu_dai_drv, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "register DAI failed\n");
++ return ret;
++ }
++
++ hdmi_data->codec_dev = platform_device_register_simple(
++ "hdmi-audio-codec", -1, NULL, 0);
++ if (IS_ERR(hdmi_data->codec_dev)) {
++ dev_err(&pdev->dev, "failed to register HDMI audio codec\n");
++ ret = PTR_ERR(hdmi_data->codec_dev);
++ goto fail;
++ }
++
++ hdmi_data->dma_dev = platform_device_alloc("imx-hdmi-audio", -1);
++ if (IS_ERR(hdmi_data->dma_dev)) {
++ ret = PTR_ERR(hdmi_data->dma_dev);
++ goto fail_dma;
++ }
++
++ platform_set_drvdata(hdmi_data->dma_dev, hdmi_data);
++
++ ret = platform_device_add(hdmi_data->dma_dev);
++ if (ret) {
++ platform_device_put(hdmi_data->dma_dev);
++ goto fail_dma;
++ }
++
++ return 0;
++
++fail_dma:
++ platform_device_unregister(hdmi_data->codec_dev);
++fail:
++ snd_soc_unregister_component(&pdev->dev);
++
++ return ret;
++}
++
++static int fsl_hdmi_dai_remove(struct platform_device *pdev)
++{
++ struct imx_hdmi *hdmi_data = platform_get_drvdata(pdev);
++
++ platform_device_unregister(hdmi_data->dma_dev);
++ platform_device_unregister(hdmi_data->codec_dev);
++ snd_soc_unregister_component(&pdev->dev);
++
++ return 0;
++}
++
++static const struct of_device_id fsl_hdmi_dai_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-hdmi-audio", },
++ { .compatible = "fsl,imx6q-hdmi-audio", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, fsl_hdmi_dai_dt_ids);
++
++static struct platform_driver fsl_hdmi_driver = {
++ .probe = fsl_hdmi_dai_probe,
++ .remove = fsl_hdmi_dai_remove,
++ .driver = {
++ .name = "fsl-hdmi-dai",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_hdmi_dai_dt_ids,
++ },
++};
++module_platform_driver(fsl_hdmi_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IMX HDMI TX DAI");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:fsl-hdmi-dai");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_spdif.c linux-linaro-stable-mx6/sound/soc/fsl/fsl_spdif.c
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_spdif.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_spdif.c 2014-05-15 20:34:23.822199874 +0200
+@@ -0,0 +1,1282 @@
++/*
++ * Freescale S/PDIF ALSA SoC Digital Audio Interface (DAI) driver
++ *
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * Based on stmp3xxx_spdif_dai.c
++ * Vladimir Barinov <vbarinov@embeddedalley.com>
++ * Copyright 2008 SigmaTel, Inc
++ * Copyright 2008 Embedded Alley Solutions, Inc
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/clk-private.h>
++#include <linux/bitrev.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/of_irq.h>
++#include <linux/pm_runtime.h>
++#include <linux/busfreq-imx6.h>
++
++#include <sound/asoundef.h>
++#include <sound/soc.h>
++#include <sound/dmaengine_pcm.h>
++
++#include "fsl_spdif.h"
++#include "imx-pcm.h"
++
++#define FSL_SPDIF_TXFIFO_WML 0x8
++#define FSL_SPDIF_RXFIFO_WML 0x8
++
++#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
++#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV|\
++ INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
++ INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
++
++/* Index list for the values that has if (DPLL Locked) condition */
++static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
++#define SRPC_NODPLL_START1 0x5
++#define SRPC_NODPLL_START2 0xc
++
++#define DEFAULT_RXCLK_SRC 1
++
++/*
++ * SPDIF control structure
++ * Defines channel status, subcode and Q sub
++ */
++struct spdif_mixer_control {
++ /* spinlock to access control data */
++ spinlock_t ctl_lock;
++
++ /* IEC958 channel tx status bit */
++ unsigned char ch_status[4];
++
++ /* User bits */
++ unsigned char subcode[2 * SPDIF_UBITS_SIZE];
++
++ /* Q subcode part of user bits */
++ unsigned char qsub[2 * SPDIF_QSUB_SIZE];
++
++ /* Buffer offset for U/Q */
++ u32 upos;
++ u32 qpos;
++
++ /* Ready buffer index of the two buffers */
++ u32 ready_buf;
++};
++
++struct fsl_spdif_priv {
++ struct spdif_mixer_control fsl_spdif_control;
++ struct snd_soc_dai_driver cpu_dai_drv;
++ struct platform_device *pdev;
++ struct regmap *regmap;
++ bool dpll_locked;
++ u8 txclk_div[SPDIF_TXRATE_MAX];
++ u8 txclk_src[SPDIF_TXRATE_MAX];
++ u8 rxclk_src;
++ struct clk *txclk[SPDIF_TXRATE_MAX];
++ struct clk *rxclk;
++ struct clk *sysclk;
++ struct clk *dmaclk;
++ struct snd_dmaengine_dai_dma_data dma_params_tx;
++ struct snd_dmaengine_dai_dma_data dma_params_rx;
++
++ /* The name space will be allocated dynamically */
++ char name[0];
++};
++
++
++/* DPLL locked and lock loss interrupt handler */
++static void spdif_irq_dpll_lock(struct fsl_spdif_priv *spdif_priv)
++{
++ struct regmap *regmap = spdif_priv->regmap;
++ struct platform_device *pdev = spdif_priv->pdev;
++ u32 locked;
++
++ regmap_read(regmap, REG_SPDIF_SRPC, &locked);
++ locked &= SRPC_DPLL_LOCKED;
++
++ dev_dbg(&pdev->dev, "isr: Rx dpll %s \n",
++ locked ? "locked" : "loss lock");
++
++ spdif_priv->dpll_locked = locked ? true : false;
++}
++
++/* Receiver found illegal symbol interrupt handler */
++static void spdif_irq_sym_error(struct fsl_spdif_priv *spdif_priv)
++{
++ struct regmap *regmap = spdif_priv->regmap;
++ struct platform_device *pdev = spdif_priv->pdev;
++
++ dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
++
++ if (!spdif_priv->dpll_locked) {
++ /* DPLL unlocked seems no audio stream */
++ regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
++ }
++}
++
++/* U/Q Channel receive register full */
++static void spdif_irq_uqrx_full(struct fsl_spdif_priv *spdif_priv, char name)
++{
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++ struct regmap *regmap = spdif_priv->regmap;
++ struct platform_device *pdev = spdif_priv->pdev;
++ u32 *pos, size, val, reg;
++
++ switch (name) {
++ case 'U':
++ pos = &ctrl->upos;
++ size = SPDIF_UBITS_SIZE;
++ reg = REG_SPDIF_SRU;
++ break;
++ case 'Q':
++ pos = &ctrl->qpos;
++ size = SPDIF_QSUB_SIZE;
++ reg = REG_SPDIF_SRQ;
++ break;
++ default:
++ dev_err(&pdev->dev, "unsupported channel name\n");
++ return;
++ }
++
++ dev_dbg(&pdev->dev, "isr: %c Channel receive register full\n", name);
++
++ if (*pos >= size * 2) {
++ *pos = 0;
++ } else if (unlikely((*pos % size) + 3 > size)) {
++ dev_err(&pdev->dev, "User bit receivce buffer overflow\n");
++ return;
++ }
++
++ regmap_read(regmap, reg, &val);
++ ctrl->subcode[*pos++] = val >> 16;
++ ctrl->subcode[*pos++] = val >> 8;
++ ctrl->subcode[*pos++] = val;
++}
++
++/* U/Q Channel sync found */
++static void spdif_irq_uq_sync(struct fsl_spdif_priv *spdif_priv)
++{
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++ struct platform_device *pdev = spdif_priv->pdev;
++
++ dev_dbg(&pdev->dev, "isr: U/Q Channel sync found\n");
++
++ /* U/Q buffer reset */
++ if (ctrl->qpos == 0)
++ return;
++
++ /* Set ready to this buffer */
++ ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1;
++}
++
++/* U/Q Channel framing error */
++static void spdif_irq_uq_err(struct fsl_spdif_priv *spdif_priv)
++{
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++ struct regmap *regmap = spdif_priv->regmap;
++ struct platform_device *pdev = spdif_priv->pdev;
++ u32 val;
++
++ dev_dbg(&pdev->dev, "isr: U/Q Channel framing error\n");
++
++ /* Read U/Q data to clear the irq and do buffer reset */
++ regmap_read(regmap, REG_SPDIF_SRU, &val);
++ regmap_read(regmap, REG_SPDIF_SRQ, &val);
++
++ /* Drop this U/Q buffer */
++ ctrl->ready_buf = 0;
++ ctrl->upos = 0;
++ ctrl->qpos = 0;
++}
++
++/* Get spdif interrupt status and clear the interrupt */
++static u32 spdif_intr_status_clear(struct fsl_spdif_priv *spdif_priv)
++{
++ struct regmap *regmap = spdif_priv->regmap;
++ u32 val, val2;
++
++ regmap_read(regmap, REG_SPDIF_SIS, &val);
++ regmap_read(regmap, REG_SPDIF_SIE, &val2);
++
++ regmap_write(regmap, REG_SPDIF_SIC, val & val2);
++
++ return val;
++}
++
++static irqreturn_t spdif_isr(int irq, void *devid)
++{
++ struct fsl_spdif_priv *spdif_priv = (struct fsl_spdif_priv *)devid;
++ struct platform_device *pdev = spdif_priv->pdev;
++ u32 sis;
++
++ sis = spdif_intr_status_clear(spdif_priv);
++
++ if (sis & INT_DPLL_LOCKED)
++ spdif_irq_dpll_lock(spdif_priv);
++
++ if (sis & INT_TXFIFO_UNOV)
++ dev_dbg(&pdev->dev, "isr: Tx FIFO under/overrun\n");
++
++ if (sis & INT_TXFIFO_RESYNC)
++ dev_dbg(&pdev->dev, "isr: Tx FIFO resync\n");
++
++ if (sis & INT_CNEW)
++ dev_dbg(&pdev->dev, "isr: cstatus new\n");
++
++ if (sis & INT_VAL_NOGOOD)
++ dev_dbg(&pdev->dev, "isr: validity flag no good\n");
++
++ if (sis & INT_SYM_ERR)
++ spdif_irq_sym_error(spdif_priv);
++
++ if (sis & INT_BIT_ERR)
++ dev_dbg(&pdev->dev, "isr: receiver found parity bit error\n");
++
++ if (sis & INT_URX_FUL)
++ spdif_irq_uqrx_full(spdif_priv, 'U');
++
++ if (sis & INT_URX_OV)
++ dev_dbg(&pdev->dev, "isr: U Channel receive register overrun\n");
++
++ if (sis & INT_QRX_FUL)
++ spdif_irq_uqrx_full(spdif_priv, 'Q');
++
++ if (sis & INT_QRX_OV)
++ dev_dbg(&pdev->dev, "isr: Q Channel receive register overrun\n");
++
++ if (sis & INT_UQ_SYNC)
++ spdif_irq_uq_sync(spdif_priv);
++
++ if (sis & INT_UQ_ERR)
++ spdif_irq_uq_err(spdif_priv);
++
++ if (sis & INT_RXFIFO_UNOV)
++ dev_dbg(&pdev->dev, "isr: Rx FIFO under/overrun\n");
++
++ if (sis & INT_RXFIFO_RESYNC)
++ dev_dbg(&pdev->dev, "isr: Rx FIFO resync\n");
++
++ if (sis & INT_LOSS_LOCK)
++ spdif_irq_dpll_lock(spdif_priv);
++
++ /* FIXME: Write Tx FIFO to clear TxEm */
++ if (sis & INT_TX_EM)
++ dev_dbg(&pdev->dev, "isr: Tx FIFO empty\n");
++
++ /* FIXME: Read Rx FIFO to clear RxFIFOFul */
++ if (sis & INT_RXFIFO_FUL)
++ dev_dbg(&pdev->dev, "isr: Rx FIFO full\n");
++
++ return IRQ_HANDLED;
++}
++
++static int spdif_softreset(struct fsl_spdif_priv *spdif_priv)
++{
++ struct regmap *regmap = spdif_priv->regmap;
++ u32 val, cycle = 1000;
++
++ regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
++
++ /*
++ * RESET bit would be cleared after finishing its reset procedure,
++ * which typically lasts 8 cycles. 1000 cycles will keep it safe.
++ */
++ do {
++ regmap_read(regmap, REG_SPDIF_SCR, &val);
++ } while ((val & SCR_SOFT_RESET) && cycle--);
++
++ if (cycle)
++ return 0;
++ else
++ return -EBUSY;
++}
++
++static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
++ u8 mask, u8 cstatus)
++{
++ ctrl->ch_status[3] &= ~mask;
++ ctrl->ch_status[3] |= cstatus & mask;
++}
++
++static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
++{
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++ struct regmap *regmap = spdif_priv->regmap;
++ struct platform_device *pdev = spdif_priv->pdev;
++ u32 ch_status;
++
++ ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
++ (bitrev8(ctrl->ch_status[1]) << 8) |
++ bitrev8(ctrl->ch_status[2]);
++ regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
++
++ dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
++
++ ch_status = bitrev8(ctrl->ch_status[3]) << 16;
++ regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
++
++ dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
++}
++
++/* Set SPDIF PhaseConfig register for rx clock */
++static int spdif_set_rx_clksrc(struct fsl_spdif_priv *spdif_priv,
++ enum spdif_gainsel gainsel, int dpll_locked)
++{
++ struct regmap *regmap = spdif_priv->regmap;
++ u8 clksrc = spdif_priv->rxclk_src;
++
++ if (clksrc >= SRPC_CLKSRC_MAX || gainsel >= GAINSEL_MULTI_MAX)
++ return -EINVAL;
++
++ regmap_update_bits(regmap, REG_SPDIF_SRPC,
++ SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
++ SRPC_CLKSRC_SEL_SET(clksrc) | SRPC_GAINSEL_SET(gainsel));
++
++ return 0;
++}
++
++static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
++ int sample_rate)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++ struct regmap *regmap = spdif_priv->regmap;
++ struct platform_device *pdev = spdif_priv->pdev;
++ unsigned long csfs = 0;
++ u32 stc, mask, rate;
++ u8 clk, div;
++ int ret;
++
++ switch (sample_rate) {
++ case 32000:
++ rate = SPDIF_TXRATE_32000;
++ csfs = IEC958_AES3_CON_FS_32000;
++ break;
++ case 44100:
++ rate = SPDIF_TXRATE_44100;
++ csfs = IEC958_AES3_CON_FS_44100;
++ break;
++ case 48000:
++ rate = SPDIF_TXRATE_48000;
++ csfs = IEC958_AES3_CON_FS_48000;
++ break;
++ default:
++ dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
++ return -EINVAL;
++ }
++
++ clk = spdif_priv->txclk_src[rate];
++ if (clk >= STC_TXCLK_SRC_MAX) {
++ dev_err(&pdev->dev, "tx clock source is out of range\n");
++ return -EINVAL;
++ }
++
++ div = spdif_priv->txclk_div[rate];
++ if (div == 0) {
++ dev_err(&pdev->dev, "the divisor can't be zero\n");
++ return -EINVAL;
++ }
++
++ /*
++ * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
++ * will divide by (div). So request 64 * fs * (div+1) which will
++ * get rounded.
++ */
++ ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div + 1));
++ if (ret) {
++ dev_err(&pdev->dev, "failed to set tx clock rate\n");
++ return ret;
++ }
++
++ dev_dbg(&pdev->dev, "expected clock rate = %d\n",
++ (64 * sample_rate * div));
++ dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
++ clk_get_rate(spdif_priv->txclk[rate]));
++
++ /* set fs field in consumer channel status */
++ spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
++
++ /* select clock source and divisor */
++ stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
++ mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | STC_TXCLK_DIV_MASK;
++ regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
++
++ dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
++
++ return 0;
++}
++
++static int fsl_spdif_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
++ struct platform_device *pdev = spdif_priv->pdev;
++ struct regmap *regmap = spdif_priv->regmap;
++ u32 scr, mask, i;
++ int ret;
++
++ pm_runtime_get_sync(cpu_dai->dev);
++ clk_prepare_enable(spdif_priv->dmaclk);
++
++ /* Reset module and interrupts only for first initialization */
++ if (!cpu_dai->active) {
++ ret = spdif_softreset(spdif_priv);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to soft reset\n");
++ return ret;
++ }
++
++ /* Disable all the interrupts */
++ regmap_update_bits(regmap, REG_SPDIF_SIE, 0xffffff, 0);
++ }
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
++ SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
++ SCR_TXFIFO_FSEL_IF8;
++ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
++ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
++ SCR_TXFIFO_FSEL_MASK;
++ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
++ clk_prepare_enable(spdif_priv->txclk[i]);
++ } else {
++ scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
++ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
++ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
++ clk_prepare_enable(spdif_priv->rxclk);
++ }
++ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
++
++ /* Power up SPDIF module */
++ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
++
++ return 0;
++}
++
++static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
++ struct regmap *regmap = spdif_priv->regmap;
++ u32 scr, mask, i;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ scr = 0;
++ mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
++ SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
++ SCR_TXFIFO_FSEL_MASK;
++ for (i = 0; i < SPDIF_TXRATE_MAX; i++)
++ clk_disable_unprepare(spdif_priv->txclk[i]);
++ } else {
++ scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
++ mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
++ SCR_RXFIFO_CTL_MASK | SCR_RXFIFO_OFF_MASK;
++ clk_disable_unprepare(spdif_priv->rxclk);
++ }
++ regmap_update_bits(regmap, REG_SPDIF_SCR, mask, scr);
++
++ /* Power down SPDIF module only if tx&rx are both inactive */
++ if (!cpu_dai->active) {
++ spdif_intr_status_clear(spdif_priv);
++ regmap_update_bits(regmap, REG_SPDIF_SCR,
++ SCR_LOW_POWER, SCR_LOW_POWER);
++ }
++
++ clk_disable_unprepare(spdif_priv->dmaclk);
++ pm_runtime_put_sync(cpu_dai->dev);
++}
++
++static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++ struct platform_device *pdev = spdif_priv->pdev;
++ u32 sample_rate = params_rate(params);
++ int ret = 0;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ ret = spdif_set_sample_rate(substream, sample_rate);
++ if (ret) {
++ dev_err(&pdev->dev, "%s: set sample rate failed: %d\n",
++ __func__, sample_rate);
++ return ret;
++ }
++ spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
++ IEC958_AES3_CON_CLOCK_1000PPM);
++ spdif_write_channel_status(spdif_priv);
++ } else {
++ /* Setup rx clock source */
++ ret = spdif_set_rx_clksrc(spdif_priv, SPDIF_DEFAULT_GAINSEL, 1);
++ }
++
++ return ret;
++}
++
++static int fsl_spdif_trigger(struct snd_pcm_substream *substream,
++ int cmd, struct snd_soc_dai *dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
++ struct regmap *regmap = spdif_priv->regmap;
++ int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
++ u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
++ u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, intr);
++ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, dmaen);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0);
++ regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static struct snd_soc_dai_ops fsl_spdif_dai_ops = {
++ .startup = fsl_spdif_startup,
++ .hw_params = fsl_spdif_hw_params,
++ .trigger = fsl_spdif_trigger,
++ .shutdown = fsl_spdif_shutdown,
++};
++
++
++/*
++ * FSL SPDIF IEC958 controller(mixer) functions
++ *
++ * Channel status get/put control
++ * User bit value get/put control
++ * Valid bit value get control
++ * DPLL lock status get control
++ * User bit sync mode selection control
++ */
++
++static int fsl_spdif_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
++ uinfo->count = 1;
++
++ return 0;
++}
++
++static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++
++ uvalue->value.iec958.status[0] = ctrl->ch_status[0];
++ uvalue->value.iec958.status[1] = ctrl->ch_status[1];
++ uvalue->value.iec958.status[2] = ctrl->ch_status[2];
++ uvalue->value.iec958.status[3] = ctrl->ch_status[3];
++
++ return 0;
++}
++
++static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++
++ ctrl->ch_status[0] = uvalue->value.iec958.status[0];
++ ctrl->ch_status[1] = uvalue->value.iec958.status[1];
++ ctrl->ch_status[2] = uvalue->value.iec958.status[2];
++ ctrl->ch_status[3] = uvalue->value.iec958.status[3];
++
++ spdif_write_channel_status(spdif_priv);
++
++ return 0;
++}
++
++/* Get channel status from SPDIF_RX_CCHAN register */
++static int fsl_spdif_capture_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct regmap *regmap = spdif_priv->regmap;
++ u32 cstatus, val;
++
++ regmap_read(regmap, REG_SPDIF_SIS, &val);
++ if (!(val & INT_CNEW)) {
++ return -EAGAIN;
++ }
++
++ regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
++ ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
++ ucontrol->value.iec958.status[1] = (cstatus >> 8) & 0xFF;
++ ucontrol->value.iec958.status[2] = cstatus & 0xFF;
++
++ regmap_read(regmap, REG_SPDIF_SRCSL, &cstatus);
++ ucontrol->value.iec958.status[3] = (cstatus >> 16) & 0xFF;
++ ucontrol->value.iec958.status[4] = (cstatus >> 8) & 0xFF;
++ ucontrol->value.iec958.status[5] = cstatus & 0xFF;
++
++ /* Clear intr */
++ regmap_write(regmap, REG_SPDIF_SIC, INT_CNEW);
++
++ return 0;
++}
++
++/*
++ * Get User bits (subcode) from chip value which readed out
++ * in UChannel register.
++ */
++static int fsl_spdif_subcode_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++ unsigned long flags;
++ int ret = 0;
++
++ spin_lock_irqsave(&ctrl->ctl_lock, flags);
++ if (ctrl->ready_buf) {
++ int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
++ memcpy(&ucontrol->value.iec958.subcode[0],
++ &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
++ } else {
++ ret = -EAGAIN;
++ }
++ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
++
++ return ret;
++}
++
++/* Q-subcode infomation. The byte size is SPDIF_UBITS_SIZE/8 */
++static int fsl_spdif_qinfo(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
++ uinfo->count = SPDIF_QSUB_SIZE;
++
++ return 0;
++}
++
++/* Get Q subcode from chip value which readed out in QChannel register */
++static int fsl_spdif_qget(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
++ unsigned long flags;
++ int ret = 0;
++
++ spin_lock_irqsave(&ctrl->ctl_lock, flags);
++ if (ctrl->ready_buf) {
++ int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
++ memcpy(&ucontrol->value.bytes.data[0],
++ &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
++ } else {
++ ret = -EAGAIN;
++ }
++ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
++
++ return ret;
++}
++
++/* Valid bit infomation */
++static int fsl_spdif_vbit_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = 1;
++
++ return 0;
++}
++
++/* Get valid good bit from interrupt status register */
++static int fsl_spdif_vbit_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct regmap *regmap = spdif_priv->regmap;
++ u32 val;
++
++ val = regmap_read(regmap, REG_SPDIF_SIS, &val);
++ ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
++ regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
++
++ return 0;
++}
++
++/* DPLL lock infomation */
++static int fsl_spdif_rxrate_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 16000;
++ uinfo->value.integer.max = 96000;
++
++ return 0;
++}
++
++static u32 gainsel_multi[GAINSEL_MULTI_MAX] = {
++ 24, 16, 12, 8, 6, 4, 3,
++};
++
++/* Get RX data clock rate given the SPDIF bus_clk */
++static int spdif_get_rxclk_rate(struct fsl_spdif_priv *spdif_priv,
++ enum spdif_gainsel gainsel)
++{
++ struct regmap *regmap = spdif_priv->regmap;
++ struct platform_device *pdev = spdif_priv->pdev;
++ u64 tmpval64, busclk_freq = 0;
++ u32 freqmeas, phaseconf;
++ u8 clksrc;
++
++ regmap_read(regmap, REG_SPDIF_SRFM, &freqmeas);
++ regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
++
++ clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
++ if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
++ /* Get bus clock from system */
++ busclk_freq = clk_get_rate(spdif_priv->sysclk);
++ }
++
++ /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
++ tmpval64 = (u64) busclk_freq * freqmeas;
++ do_div(tmpval64, gainsel_multi[gainsel] * 1024);
++ do_div(tmpval64, 128 * 1024);
++
++ dev_dbg(&pdev->dev, "FreqMeas: %d\n", freqmeas);
++ dev_dbg(&pdev->dev, "BusclkFreq: %lld\n", busclk_freq);
++ dev_dbg(&pdev->dev, "RxRate: %lld\n", tmpval64);
++
++ return (int)tmpval64;
++}
++
++/*
++ * Get DPLL lock or not info from stable interrupt status register.
++ * User application must use this control to get locked,
++ * then can do next PCM operation
++ */
++static int fsl_spdif_rxrate_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
++
++ if (spdif_priv->dpll_locked)
++ ucontrol->value.integer.value[0] = rate;
++ else
++ ucontrol->value.integer.value[0] = 0;
++
++ return 0;
++}
++
++/* User bit sync mode info */
++static int fsl_spdif_usync_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
++ uinfo->count = 1;
++ uinfo->value.integer.min = 0;
++ uinfo->value.integer.max = 1;
++
++ return 0;
++}
++
++/*
++ * User bit sync mode:
++ * 1 CD User channel subcode
++ * 0 Non-CD data
++ */
++static int fsl_spdif_usync_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct regmap *regmap = spdif_priv->regmap;
++ u32 val;
++
++ regmap_read(regmap, REG_SPDIF_SRCD, &val);
++ ucontrol->value.integer.value[0] = (val & SRCD_CD_USER) != 0;
++
++ return 0;
++}
++
++/*
++ * User bit sync mode:
++ * 1 CD User channel subcode
++ * 0 Non-CD data
++ */
++static int fsl_spdif_usync_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *ucontrol)
++{
++ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
++ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct regmap *regmap = spdif_priv->regmap;
++ u32 val = ucontrol->value.integer.value[0] << SRCD_CD_USER_OFFSET;
++
++ regmap_update_bits(regmap, REG_SPDIF_SRCD, SRCD_CD_USER, val);
++
++ return 0;
++}
++
++/* FSL SPDIF IEC958 controller defines */
++static struct snd_kcontrol_new fsl_spdif_ctrls[] = {
++ /* Status cchanel controller */
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_WRITE |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_spdif_info,
++ .get = fsl_spdif_pb_get,
++ .put = fsl_spdif_pb_put,
++ },
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_spdif_info,
++ .get = fsl_spdif_capture_get,
++ },
++ /* User bits controller */
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = "IEC958 Subcode Capture Default",
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_spdif_info,
++ .get = fsl_spdif_subcode_get,
++ },
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = "IEC958 Q-subcode Capture Default",
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_spdif_qinfo,
++ .get = fsl_spdif_qget,
++ },
++ /* Valid bit error controller */
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = "IEC958 V-Bit Errors",
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_spdif_vbit_info,
++ .get = fsl_spdif_vbit_get,
++ },
++ /* DPLL lock info get controller */
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = "RX Sample Rate",
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_spdif_rxrate_info,
++ .get = fsl_spdif_rxrate_get,
++ },
++ /* User bit sync mode set/get controller */
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_PCM,
++ .name = "IEC958 USyncMode CDText",
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_WRITE |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_spdif_usync_info,
++ .get = fsl_spdif_usync_get,
++ .put = fsl_spdif_usync_put,
++ },
++};
++
++static int fsl_spdif_dai_probe(struct snd_soc_dai *dai)
++{
++ struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
++
++ dai->playback_dma_data = &spdif_private->dma_params_tx;
++ dai->capture_dma_data = &spdif_private->dma_params_rx;
++
++ snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
++
++ return 0;
++}
++
++static struct snd_soc_dai_driver fsl_spdif_dai = {
++ .probe = &fsl_spdif_dai_probe,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = FSL_SPDIF_RATES_PLAYBACK,
++ .formats = FSL_SPDIF_FORMATS_PLAYBACK,
++ },
++ .capture = {
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = FSL_SPDIF_RATES_CAPTURE,
++ .formats = FSL_SPDIF_FORMATS_CAPTURE,
++ },
++ .ops = &fsl_spdif_dai_ops,
++};
++
++static const struct snd_soc_component_driver fsl_spdif_component = {
++ .name = "fsl-spdif",
++};
++
++/* FSL SPDIF REGMAP */
++
++static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_SPDIF_SCR:
++ case REG_SPDIF_SRCD:
++ case REG_SPDIF_SRPC:
++ case REG_SPDIF_SIE:
++ case REG_SPDIF_SIS:
++ case REG_SPDIF_SRL:
++ case REG_SPDIF_SRR:
++ case REG_SPDIF_SRCSH:
++ case REG_SPDIF_SRCSL:
++ case REG_SPDIF_SRU:
++ case REG_SPDIF_SRQ:
++ case REG_SPDIF_STCSCH:
++ case REG_SPDIF_STCSCL:
++ case REG_SPDIF_SRFM:
++ case REG_SPDIF_STC:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_SPDIF_SCR:
++ case REG_SPDIF_SRCD:
++ case REG_SPDIF_SRPC:
++ case REG_SPDIF_SIE:
++ case REG_SPDIF_SIC:
++ case REG_SPDIF_STL:
++ case REG_SPDIF_STR:
++ case REG_SPDIF_STCSCH:
++ case REG_SPDIF_STCSCL:
++ case REG_SPDIF_STC:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static const struct regmap_config fsl_spdif_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++
++ .max_register = REG_SPDIF_STC,
++ .readable_reg = fsl_spdif_readable_reg,
++ .writeable_reg = fsl_spdif_writeable_reg,
++};
++
++static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
++ struct clk *clk, u64 savesub,
++ enum spdif_txrate index)
++{
++ const u32 rate[] = { 32000, 44100, 48000 };
++ u64 rate_ideal, rate_actual, sub;
++ u32 div, arate;
++
++ for (div = 1; div <= 128; div++) {
++ rate_ideal = rate[index] * (div + 1) * 64;
++ rate_actual = clk_round_rate(clk, rate_ideal);
++
++ arate = rate_actual / 64;
++ arate /= div;
++
++ if (arate == rate[index]) {
++ /* We are lucky */
++ savesub = 0;
++ spdif_priv->txclk_div[index] = div;
++ break;
++ } else if (arate / rate[index] == 1) {
++ /* A little bigger than expect */
++ sub = (arate - rate[index]) * 100000;
++ do_div(sub, rate[index]);
++ if (sub < savesub) {
++ savesub = sub;
++ spdif_priv->txclk_div[index] = div;
++ }
++ } else if (rate[index] / arate == 1) {
++ /* A little smaller than expect */
++ sub = (rate[index] - arate) * 100000;
++ do_div(sub, rate[index]);
++ if (sub < savesub) {
++ savesub = sub;
++ spdif_priv->txclk_div[index] = div;
++ }
++ }
++ }
++
++ return savesub;
++}
++
++static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
++ enum spdif_txrate index)
++{
++ const u32 rate[] = { 32000, 44100, 48000 };
++ struct platform_device *pdev = spdif_priv->pdev;
++ struct device *dev = &pdev->dev;
++ u64 savesub = 100000, ret;
++ struct clk *clk;
++ char tmp[16];
++ int i;
++
++ for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
++ sprintf(tmp, "rxtx%d", i);
++ clk = devm_clk_get(&pdev->dev, tmp);
++ if (IS_ERR(clk)) {
++ dev_err(dev, "no rxtx%d clock in devicetree\n", i);
++ return PTR_ERR(clk);
++ }
++ if (!clk_get_rate(clk))
++ continue;
++
++ /* TODO: We here ignore sysclk source due to imperfect clock
++ * selecting mechanism: sysclk is a bit different which we can
++ * not change its clock rate but use another inner divider to
++ * derive a proper clock rate. */
++ if (i == SPDIF_CLK_SRC_SYSCLK)
++ continue;
++
++ ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index);
++ if (savesub == ret)
++ continue;
++
++ savesub = ret;
++ spdif_priv->txclk[index] = clk;
++ spdif_priv->txclk_src[index] = i;
++
++ /* To quick catch a divisor, we allow a 0.1% deviation */
++ if (savesub < 100)
++ break;
++ }
++
++ dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
++ spdif_priv->txclk_src[index], rate[index]);
++ dev_dbg(&pdev->dev, "use divisor %d for %dHz sample rate\n",
++ spdif_priv->txclk_div[index], rate[index]);
++
++ return 0;
++}
++
++static int fsl_spdif_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct fsl_spdif_priv *spdif_priv;
++ struct spdif_mixer_control *ctrl;
++ struct resource *res;
++ void __iomem *regs;
++ int irq, ret, i;
++
++ if (!np)
++ return -ENODEV;
++
++ spdif_priv = devm_kzalloc(&pdev->dev,
++ sizeof(struct fsl_spdif_priv) + strlen(np->name) + 1,
++ GFP_KERNEL);
++ if (!spdif_priv)
++ return -ENOMEM;
++
++ strcpy(spdif_priv->name, np->name);
++
++ spdif_priv->pdev = pdev;
++
++ /* Initialize this copy of the CPU DAI driver structure */
++ memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
++ spdif_priv->cpu_dai_drv.name = spdif_priv->name;
++
++ /* Get the addresses and IRQ */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (IS_ERR(res)) {
++ dev_err(&pdev->dev, "could not determine device resources\n");
++ return PTR_ERR(res);
++ }
++
++ regs = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(regs)) {
++ dev_err(&pdev->dev, "could not map device resources\n");
++ return PTR_ERR(regs);
++ }
++
++ spdif_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
++ "core", regs, &fsl_spdif_regmap_config);
++ if (IS_ERR(spdif_priv->regmap)) {
++ dev_err(&pdev->dev, "regmap init failed\n");
++ return PTR_ERR(spdif_priv->regmap);
++ }
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
++ return irq;
++ }
++
++ ret = devm_request_irq(&pdev->dev, irq, spdif_isr, 0,
++ spdif_priv->name, spdif_priv);
++ if (ret) {
++ dev_err(&pdev->dev, "could not claim irq %u\n", irq);
++ return ret;
++ }
++
++ /* Get system clock for rx clock rate calculation */
++ spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
++ if (IS_ERR(spdif_priv->sysclk)) {
++ dev_err(&pdev->dev, "no system clock(rxtx5) in devicetree\n");
++ return PTR_ERR(spdif_priv->sysclk);
++ }
++
++ /* Get dma clock for dma script operation */
++ spdif_priv->dmaclk = devm_clk_get(&pdev->dev, "dma");
++ if (IS_ERR(spdif_priv->dmaclk)) {
++ dev_err(&pdev->dev, "no dma clock in devicetree\n");
++ return PTR_ERR(spdif_priv->dmaclk);
++ }
++
++ /* Select clock source for rx/tx clock */
++ spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
++ if (IS_ERR(spdif_priv->rxclk)) {
++ dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
++ return PTR_ERR(spdif_priv->rxclk);
++ }
++ spdif_priv->rxclk_src = DEFAULT_RXCLK_SRC;
++
++ for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
++ ret = fsl_spdif_probe_txclk(spdif_priv, i);
++ if (ret)
++ return ret;
++ }
++
++ /* Initial spinlock for control data */
++ ctrl = &spdif_priv->fsl_spdif_control;
++ spin_lock_init(&ctrl->ctl_lock);
++
++ /* Init tx channel status default value */
++ ctrl->ch_status[0] =
++ IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
++ ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
++ ctrl->ch_status[2] = 0x00;
++ ctrl->ch_status[3] =
++ IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
++
++ spdif_priv->dpll_locked = false;
++
++ spdif_priv->dma_params_tx.maxburst = FSL_SPDIF_TXFIFO_WML;
++ spdif_priv->dma_params_rx.maxburst = FSL_SPDIF_RXFIFO_WML;
++ spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
++ spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
++
++ pm_runtime_enable(&pdev->dev);
++
++ /* Register with ASoC */
++ dev_set_drvdata(&pdev->dev, spdif_priv);
++
++ ret = snd_soc_register_component(&pdev->dev, &fsl_spdif_component,
++ &spdif_priv->cpu_dai_drv, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
++ return ret;
++ }
++
++ ret = imx_pcm_dma_init(pdev, SND_DMAENGINE_PCM_FLAG_NO_RESIDUE,
++ IMX_SPDIF_DMABUF_SIZE);
++ if (ret) {
++ dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
++ goto error_component;
++ }
++
++ return ret;
++
++error_component:
++ snd_soc_unregister_component(&pdev->dev);
++
++ return ret;
++}
++
++static int fsl_spdif_remove(struct platform_device *pdev)
++{
++ imx_pcm_dma_exit(pdev);
++ snd_soc_unregister_component(&pdev->dev);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_RUNTIME
++static int fsl_spdif_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int fsl_spdif_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++#endif
++
++static const struct dev_pm_ops fsl_spdif_pm = {
++ SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend,
++ fsl_spdif_runtime_resume,
++ NULL)
++};
++
++static const struct of_device_id fsl_spdif_dt_ids[] = {
++ { .compatible = "fsl,imx35-spdif", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
++
++static struct platform_driver fsl_spdif_driver = {
++ .driver = {
++ .name = "fsl-spdif-dai",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_spdif_dt_ids,
++ .pm = &fsl_spdif_pm,
++ },
++ .probe = fsl_spdif_probe,
++ .remove = fsl_spdif_remove,
++};
++
++module_platform_driver(fsl_spdif_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Freescale S/PDIF CPU DAI Driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:fsl-spdif-dai");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_spdif.h linux-linaro-stable-mx6/sound/soc/fsl/fsl_spdif.h
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_spdif.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_spdif.h 2014-05-15 20:34:23.822199874 +0200
+@@ -0,0 +1,193 @@
++/*
++ * fsl_spdif.h - ALSA S/PDIF interface for the Freescale i.MX SoC
++ *
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * Author: Nicolin Chen <b42378@freescale.com>
++ *
++ * Based on fsl_ssi.h
++ * Author: Timur Tabi <timur@freescale.com>
++ * Copyright 2007-2008 Freescale Semiconductor, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#ifndef _FSL_SPDIF_DAI_H
++#define _FSL_SPDIF_DAI_H
++
++/* S/PDIF Register Map */
++#define REG_SPDIF_SCR 0x0 /* SPDIF Configuration Register */
++#define REG_SPDIF_SRCD 0x4 /* CDText Control Register */
++#define REG_SPDIF_SRPC 0x8 /* PhaseConfig Register */
++#define REG_SPDIF_SIE 0xc /* InterruptEn Register */
++#define REG_SPDIF_SIS 0x10 /* InterruptStat Register */
++#define REG_SPDIF_SIC 0x10 /* InterruptClear Register */
++#define REG_SPDIF_SRL 0x14 /* SPDIFRxLeft Register */
++#define REG_SPDIF_SRR 0x18 /* SPDIFRxRight Register */
++#define REG_SPDIF_SRCSH 0x1c /* SPDIFRxCChannel_h Register */
++#define REG_SPDIF_SRCSL 0x20 /* SPDIFRxCChannel_l Register */
++#define REG_SPDIF_SRU 0x24 /* UchannelRx Register */
++#define REG_SPDIF_SRQ 0x28 /* QchannelRx Register */
++#define REG_SPDIF_STL 0x2C /* SPDIFTxLeft Register */
++#define REG_SPDIF_STR 0x30 /* SPDIFTxRight Register */
++#define REG_SPDIF_STCSCH 0x34 /* SPDIFTxCChannelCons_h Register */
++#define REG_SPDIF_STCSCL 0x38 /* SPDIFTxCChannelCons_l Register */
++#define REG_SPDIF_SRFM 0x44 /* FreqMeas Register */
++#define REG_SPDIF_STC 0x50 /* SPDIFTxClk Register */
++
++
++/* SPDIF Configuration register */
++#define SCR_RXFIFO_CTL_OFFSET 23
++#define SCR_RXFIFO_CTL_MASK (1 << SCR_RXFIFO_CTL_OFFSET)
++#define SCR_RXFIFO_CTL_ZERO (1 << SCR_RXFIFO_CTL_OFFSET)
++#define SCR_RXFIFO_OFF_OFFSET 22
++#define SCR_RXFIFO_OFF_MASK (1 << SCR_RXFIFO_OFF_OFFSET)
++#define SCR_RXFIFO_OFF (1 << SCR_RXFIFO_OFF_OFFSET)
++#define SCR_RXFIFO_RST_OFFSET 21
++#define SCR_RXFIFO_RST_MASK (1 << SCR_RXFIFO_RST_OFFSET)
++#define SCR_RXFIFO_RST (1 << SCR_RXFIFO_RST_OFFSET)
++#define SCR_RXFIFO_FSEL_OFFSET 19
++#define SCR_RXFIFO_FSEL_MASK (0x3 << SCR_RXFIFO_FSEL_OFFSET)
++#define SCR_RXFIFO_FSEL_IF0 (0x0 << SCR_RXFIFO_FSEL_OFFSET)
++#define SCR_RXFIFO_FSEL_IF4 (0x1 << SCR_RXFIFO_FSEL_OFFSET)
++#define SCR_RXFIFO_FSEL_IF8 (0x2 << SCR_RXFIFO_FSEL_OFFSET)
++#define SCR_RXFIFO_FSEL_IF12 (0x3 << SCR_RXFIFO_FSEL_OFFSET)
++#define SCR_RXFIFO_AUTOSYNC_OFFSET 18
++#define SCR_RXFIFO_AUTOSYNC_MASK (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
++#define SCR_RXFIFO_AUTOSYNC (1 << SCR_RXFIFO_AUTOSYNC_OFFSET)
++#define SCR_TXFIFO_AUTOSYNC_OFFSET 17
++#define SCR_TXFIFO_AUTOSYNC_MASK (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
++#define SCR_TXFIFO_AUTOSYNC (1 << SCR_TXFIFO_AUTOSYNC_OFFSET)
++#define SCR_TXFIFO_FSEL_OFFSET 15
++#define SCR_TXFIFO_FSEL_MASK (0x3 << SCR_TXFIFO_FSEL_OFFSET)
++#define SCR_TXFIFO_FSEL_IF0 (0x0 << SCR_TXFIFO_FSEL_OFFSET)
++#define SCR_TXFIFO_FSEL_IF4 (0x1 << SCR_TXFIFO_FSEL_OFFSET)
++#define SCR_TXFIFO_FSEL_IF8 (0x2 << SCR_TXFIFO_FSEL_OFFSET)
++#define SCR_TXFIFO_FSEL_IF12 (0x3 << SCR_TXFIFO_FSEL_OFFSET)
++#define SCR_LOW_POWER (1 << 13)
++#define SCR_SOFT_RESET (1 << 12)
++#define SCR_TXFIFO_CTRL_OFFSET 10
++#define SCR_TXFIFO_CTRL_MASK (0x3 << SCR_TXFIFO_CTRL_OFFSET)
++#define SCR_TXFIFO_CTRL_ZERO (0x0 << SCR_TXFIFO_CTRL_OFFSET)
++#define SCR_TXFIFO_CTRL_NORMAL (0x1 << SCR_TXFIFO_CTRL_OFFSET)
++#define SCR_TXFIFO_CTRL_ONESAMPLE (0x2 << SCR_TXFIFO_CTRL_OFFSET)
++#define SCR_DMA_RX_EN_OFFSET 9
++#define SCR_DMA_RX_EN_MASK (1 << SCR_DMA_RX_EN_OFFSET)
++#define SCR_DMA_RX_EN (1 << SCR_DMA_RX_EN_OFFSET)
++#define SCR_DMA_TX_EN_OFFSET 8
++#define SCR_DMA_TX_EN_MASK (1 << SCR_DMA_TX_EN_OFFSET)
++#define SCR_DMA_TX_EN (1 << SCR_DMA_TX_EN_OFFSET)
++#define SCR_VAL_OFFSET 5
++#define SCR_VAL_MASK (1 << SCR_VAL_OFFSET)
++#define SCR_VAL_CLEAR (1 << SCR_VAL_OFFSET)
++#define SCR_TXSEL_OFFSET 2
++#define SCR_TXSEL_MASK (0x7 << SCR_TXSEL_OFFSET)
++#define SCR_TXSEL_OFF (0 << SCR_TXSEL_OFFSET)
++#define SCR_TXSEL_RX (1 << SCR_TXSEL_OFFSET)
++#define SCR_TXSEL_NORMAL (0x5 << SCR_TXSEL_OFFSET)
++#define SCR_USRC_SEL_OFFSET 0x0
++#define SCR_USRC_SEL_MASK (0x3 << SCR_USRC_SEL_OFFSET)
++#define SCR_USRC_SEL_NONE (0x0 << SCR_USRC_SEL_OFFSET)
++#define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
++#define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
++
++/* SPDIF CDText control */
++#define SRCD_CD_USER_OFFSET 1
++#define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
++
++/* SPDIF Phase Configuration register */
++#define SRPC_DPLL_LOCKED (1 << 6)
++#define SRPC_CLKSRC_SEL_OFFSET 7
++#define SRPC_CLKSRC_SEL_MASK (0xf << SRPC_CLKSRC_SEL_OFFSET)
++#define SRPC_CLKSRC_SEL_SET(x) ((x << SRPC_CLKSRC_SEL_OFFSET) & SRPC_CLKSRC_SEL_MASK)
++#define SRPC_CLKSRC_SEL_LOCKED_OFFSET1 5
++#define SRPC_CLKSRC_SEL_LOCKED_OFFSET2 2
++#define SRPC_GAINSEL_OFFSET 3
++#define SRPC_GAINSEL_MASK (0x7 << SRPC_GAINSEL_OFFSET)
++#define SRPC_GAINSEL_SET(x) ((x << SRPC_GAINSEL_OFFSET) & SRPC_GAINSEL_MASK)
++
++#define SRPC_CLKSRC_MAX 16
++
++enum spdif_gainsel {
++ GAINSEL_MULTI_24 = 0,
++ GAINSEL_MULTI_16,
++ GAINSEL_MULTI_12,
++ GAINSEL_MULTI_8,
++ GAINSEL_MULTI_6,
++ GAINSEL_MULTI_4,
++ GAINSEL_MULTI_3,
++};
++#define GAINSEL_MULTI_MAX (GAINSEL_MULTI_3 + 1)
++#define SPDIF_DEFAULT_GAINSEL GAINSEL_MULTI_8
++
++/* SPDIF interrupt mask define */
++#define INT_DPLL_LOCKED (1 << 20)
++#define INT_TXFIFO_UNOV (1 << 19)
++#define INT_TXFIFO_RESYNC (1 << 18)
++#define INT_CNEW (1 << 17)
++#define INT_VAL_NOGOOD (1 << 16)
++#define INT_SYM_ERR (1 << 15)
++#define INT_BIT_ERR (1 << 14)
++#define INT_URX_FUL (1 << 10)
++#define INT_URX_OV (1 << 9)
++#define INT_QRX_FUL (1 << 8)
++#define INT_QRX_OV (1 << 7)
++#define INT_UQ_SYNC (1 << 6)
++#define INT_UQ_ERR (1 << 5)
++#define INT_RXFIFO_UNOV (1 << 4)
++#define INT_RXFIFO_RESYNC (1 << 3)
++#define INT_LOSS_LOCK (1 << 2)
++#define INT_TX_EM (1 << 1)
++#define INT_RXFIFO_FUL (1 << 0)
++
++/* SPDIF Clock register */
++#define STC_SYSCLK_DIV_OFFSET 11
++#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
++#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)
++#define STC_TXCLK_SRC_OFFSET 8
++#define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
++#define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
++#define STC_TXCLK_ALL_EN_OFFSET 7
++#define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
++#define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
++#define STC_TXCLK_DIV_OFFSET 0
++#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
++#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK)
++#define STC_TXCLK_SRC_MAX 8
++
++#define SPDIF_CLK_SRC_SYSCLK 5
++
++/* SPDIF tx rate */
++enum spdif_txrate {
++ SPDIF_TXRATE_32000 = 0,
++ SPDIF_TXRATE_44100,
++ SPDIF_TXRATE_48000,
++};
++#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
++
++
++#define SPDIF_CSTATUS_BYTE 6
++#define SPDIF_UBITS_SIZE 96
++#define SPDIF_QSUB_SIZE (SPDIF_UBITS_SIZE / 8)
++
++
++#define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
++ SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000)
++
++#define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
++ SNDRV_PCM_RATE_32000 | \
++ SNDRV_PCM_RATE_44100 | \
++ SNDRV_PCM_RATE_48000 | \
++ SNDRV_PCM_RATE_64000 | \
++ SNDRV_PCM_RATE_96000)
++
++#define FSL_SPDIF_FORMATS_PLAYBACK (SNDRV_PCM_FMTBIT_S16_LE | \
++ SNDRV_PCM_FMTBIT_S20_3LE | \
++ SNDRV_PCM_FMTBIT_S24_LE)
++
++#define FSL_SPDIF_FORMATS_CAPTURE (SNDRV_PCM_FMTBIT_S24_LE)
++
++#endif /* _FSL_SPDIF_DAI_H */
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_ssi.c linux-linaro-stable-mx6/sound/soc/fsl/fsl_ssi.c
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_ssi.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_ssi.c 2014-05-15 20:34:23.822199874 +0200
+@@ -3,13 +3,14 @@
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+- * Copyright 2007-2010 Freescale Semiconductor, Inc.
++ * Copyright (C) 2007-2013 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
++#include <linux/busfreq-imx6.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+@@ -21,6 +22,7 @@
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
+
+ #include <sound/core.h>
+ #include <sound/pcm.h>
+@@ -51,6 +53,24 @@
+ }
+ #endif
+
++#ifdef DEBUG
++#define NUM_OF_SSI_REG (sizeof(struct ccsr_ssi) / sizeof(__be32))
++
++void dump_reg(struct ccsr_ssi __iomem *ssi)
++{
++ u32 val, i;
++
++ for (i = 0; i < NUM_OF_SSI_REG; i++) {
++ if (&ssi->stx0 + i == NULL)
++ continue;
++ val = read_ssi(&ssi->stx0 + i);
++ pr_debug("REG %x = %x\n", (u32)(&ssi->stx0 + i) & 0xff, val);
++ }
++}
++#else
++void dump_reg(struct ccsr_ssi __iomem *ssi) {}
++#endif
++
+ /**
+ * FSLSSI_I2S_RATES: sample rates supported by the I2S
+ *
+@@ -87,10 +107,9 @@
+ #endif
+
+ /* SIER bitflag of interrupts to enable */
+-#define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
+- CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
+- CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
+- CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
++#define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TIE | \
++ CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TUE1_EN | \
++ CCSR_SSI_SIER_RFRC_EN | CCSR_SSI_SIER_RIE | \
+ CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
+
+ /**
+@@ -119,14 +138,15 @@
+ struct device_attribute dev_attr;
+ struct platform_device *pdev;
+
++ unsigned long sysrate;
+ bool new_binding;
+ bool ssi_on_imx;
++ bool use_dual_fifo;
++ u8 i2s_mode;
++ struct clk *coreclk;
+ struct clk *clk;
+- struct platform_device *imx_pcm_pdev;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+- struct imx_dma_data filter_data_tx;
+- struct imx_dma_data filter_data_rx;
+
+ struct {
+ unsigned int rfrc;
+@@ -315,6 +335,22 @@
+ snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
+
++ if (ssi_private->ssi_on_imx) {
++ pm_runtime_get_sync(dai->dev);
++
++ clk_prepare_enable(ssi_private->coreclk);
++ clk_prepare_enable(ssi_private->clk);
++
++ /* When using dual fifo mode, it would be safer if we ensure
++ * its period size to be an even number. If appearing to an
++ * odd number, the 2nd fifo might be neglected by SDMA sciprt
++ * at the end of each period.
++ */
++ if (ssi_private->use_dual_fifo)
++ snd_pcm_hw_constraint_step(substream->runtime, 0,
++ SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
++ }
++
+ /*
+ * If this is the first stream opened, then request the IRQ
+ * and initialize the SSI registers.
+@@ -337,9 +373,10 @@
+ *
+ * FIXME: Little-endian samples require a different shift dir
+ */
++ ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
+ write_ssi_mask(&ssi->scr,
+ CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
+- CCSR_SSI_SCR_TFR_CLK_DIS | CCSR_SSI_SCR_I2S_MODE_SLAVE
++ CCSR_SSI_SCR_TFR_CLK_DIS | ssi_private->i2s_mode
+ | (synchronous ? CCSR_SSI_SCR_SYN : 0));
+
+ write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
+@@ -372,9 +409,22 @@
+ * data will be written to memory as soon as it's available.
+ */
+ write_ssi(CCSR_SSI_SFCSR_TFWM0(ssi_private->fifo_depth - 2) |
+- CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2),
++ CCSR_SSI_SFCSR_RFWM0(ssi_private->fifo_depth - 2) |
++ CCSR_SSI_SFCSR_TFWM1(ssi_private->fifo_depth - 2) |
++ CCSR_SSI_SFCSR_RFWM1(ssi_private->fifo_depth - 2),
+ &ssi->sfcsr);
+
++ /* Select Single/Dual fifo mode */
++ if (ssi_private->use_dual_fifo) {
++ write_ssi_mask(&ssi->srcr, 0, CCSR_SSI_SRCR_RFEN1);
++ write_ssi_mask(&ssi->stcr, 0, CCSR_SSI_STCR_TFEN1);
++ write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TCH_EN);
++ } else {
++ write_ssi_mask(&ssi->srcr, CCSR_SSI_SRCR_RFEN1, 0);
++ write_ssi_mask(&ssi->stcr, CCSR_SSI_STCR_TFEN1, 0);
++ write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TCH_EN, 0);
++ }
++
+ /*
+ * We keep the SSI disabled because if we enable it, then the
+ * DMA controller will start. It's not supposed to start until
+@@ -385,43 +435,6 @@
+ * finished initializing the DMA controller.
+ */
+ } else {
+- if (synchronous) {
+- struct snd_pcm_runtime *first_runtime =
+- ssi_private->first_stream->runtime;
+- /*
+- * This is the second stream open, and we're in
+- * synchronous mode, so we need to impose sample
+- * sample size constraints. This is because STCCR is
+- * used for playback and capture in synchronous mode,
+- * so there's no way to specify different word
+- * lengths.
+- *
+- * Note that this can cause a race condition if the
+- * second stream is opened before the first stream is
+- * fully initialized. We provide some protection by
+- * checking to make sure the first stream is
+- * initialized, but it's not perfect. ALSA sometimes
+- * re-initializes the driver with a different sample
+- * rate or size. If the second stream is opened
+- * before the first stream has received its final
+- * parameters, then the second stream may be
+- * constrained to the wrong sample rate or size.
+- */
+- if (!first_runtime->sample_bits) {
+- dev_err(substream->pcm->card->dev,
+- "set sample size in %s stream first\n",
+- substream->stream ==
+- SNDRV_PCM_STREAM_PLAYBACK
+- ? "capture" : "playback");
+- return -EAGAIN;
+- }
+-
+- snd_pcm_hw_constraint_minmax(substream->runtime,
+- SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
+- first_runtime->sample_bits,
+- first_runtime->sample_bits);
+- }
+-
+ ssi_private->second_stream = substream;
+ }
+
+@@ -450,6 +463,8 @@
+ snd_pcm_format_width(params_format(hw_params));
+ u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
+ int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
++ unsigned int channels = params_channels(hw_params);
++ int ret;
+
+ /*
+ * If we're in synchronous mode, and the SSI is already enabled,
+@@ -458,6 +473,14 @@
+ if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
+ return 0;
+
++ if (ssi_private->sysrate) {
++ ret = clk_set_rate(ssi_private->clk, ssi_private->sysrate);
++ if (ret) {
++ dev_err(cpu_dai->dev, "failed to set clock rate\n");
++ return ret;
++ }
++ }
++
+ /*
+ * FIXME: The documentation says that SxCCR[WL] should not be
+ * modified while the SSI is enabled. The only time this can
+@@ -475,6 +498,9 @@
+ else
+ write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
+
++ write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
++ channels == 1 ? 0 : ssi_private->i2s_mode);
++
+ return 0;
+ }
+
+@@ -496,27 +522,248 @@
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ write_ssi_mask(&ssi->scr, 0,
+ CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
+- else
++ write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TDMAE);
++ } else {
+ write_ssi_mask(&ssi->scr, 0,
+ CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
++ write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RDMAE);
++ }
++ dump_reg(ssi);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+ write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
+- else
++ write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TDMAE, 0);
++ } else {
+ write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
++ write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RDMAE, 0);
++ }
++ if ((read_ssi(&ssi->scr) & (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
++ write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
++{
++ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ u32 strcr = 0, stcr, srcr, scr, mask;
++
++ scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_NET);
++
++ mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR
++ | CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL
++ | CCSR_SSI_STCR_TEFS;
++ stcr = read_ssi(&ssi->stcr) & ~mask;
++ srcr = read_ssi(&ssi->srcr) & ~mask;
++
++ /* DAI format */
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ scr |= CCSR_SSI_SCR_NET;
++
++ /* Pre-set SSI I2S mode */
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFM:
++ ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
++ break;
++ default:
++ dev_err(cpu_dai->dev, "unsupported SND_SOC_DAIFMT_MASTER: %d",
++ fmt & SND_SOC_DAIFMT_MASTER_MASK);
++ return -EINVAL;
++ }
++ scr &= ~CCSR_SSI_SCR_I2S_MODE_MASK;
++ scr |= ssi_private->i2s_mode;
++
++ /* Data on rising edge of bclk, frame low, 1clk before data */
++ strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP
++ | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
++ break;
++ case SND_SOC_DAIFMT_LEFT_J:
++ /* Data on rising edge of bclk, frame high */
++ strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
++ break;
++ case SND_SOC_DAIFMT_DSP_A:
++ /* Data on rising edge of bclk, frame high, 1clk before data */
++ strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP
++ | CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
++ break;
++ case SND_SOC_DAIFMT_DSP_B:
++ /* Data on rising edge of bclk, frame high */
++ strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP
++ | CCSR_SSI_STCR_TXBIT0;
++ break;
++ default:
++ dev_err(cpu_dai->dev, "unsupported SND_SOC_DAIFMT: %d",
++ fmt & SND_SOC_DAIFMT_FORMAT_MASK);
++ return -EINVAL;
++ }
++
++ /* DAI clock inversion */
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_NB_NF:
++ /* Nothing to do for both normal cases */
++ break;
++ case SND_SOC_DAIFMT_IB_NF:
++ /* Invert bit clock */
++ strcr ^= CCSR_SSI_STCR_TSCKP;
++ break;
++ case SND_SOC_DAIFMT_NB_IF:
++ /* Invert frame clock */
++ strcr ^= CCSR_SSI_STCR_TFSI;
+ break;
++ case SND_SOC_DAIFMT_IB_IF:
++ /* Invert both clocks */
++ strcr ^= CCSR_SSI_STCR_TSCKP;
++ strcr ^= CCSR_SSI_STCR_TFSI;
++ break;
++ default:
++ dev_err(cpu_dai->dev, "unsupported SND_SOC_DAIFMT_INV: %d",
++ fmt & SND_SOC_DAIFMT_INV_MASK);
++ return -EINVAL;
++ }
+
++ /* DAI clock master masks */
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ scr |= CCSR_SSI_SCR_SYS_CLK_EN;
++ strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFM:
++ scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
++ break;
+ default:
++ dev_err(cpu_dai->dev, "unsupported SND_SOC_DAIFMT_MASTER: %d",
++ fmt & SND_SOC_DAIFMT_MASTER_MASK);
++ return -EINVAL;
++ }
++
++ stcr |= strcr;
++ srcr |= strcr;
++
++ if (ssi_private->cpu_dai_drv.symmetric_rates) {
++ scr |= CCSR_SSI_SCR_SYN;
++
++ /* Need to clear RXDIR when using SYNC mode */
++ srcr &= ~CCSR_SSI_SRCR_RXDIR;
++ }
++
++ write_ssi(stcr, &ssi->stcr);
++ write_ssi(srcr, &ssi->srcr);
++ write_ssi(scr, &ssi->scr);
++
++ return 0;
++}
++
++static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
++ u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
++ unsigned long clkrate, sysrate = 0;
++ u64 sub, savesub = 100000;
++
++ /*
++ * It should be already enough to divide clock by setting pm.
++ * So we here keep psr and div2 to 0.
++ */
++ psr = 0;
++ div2 = 0;
++
++ factor = (div2 + 1) * (7 * psr + 1) * 2;
++
++ for (i = 0; i < 255; i++) {
++ /* The bclk rate must be smaller than 1/5 sysclk rate */
++ if (factor * (i + 1) < 5)
++ continue;
++
++ sysrate = freq * factor * (i + 2);
++ clkrate = clk_round_rate(ssi_private->clk, sysrate);
++
++ do_div(clkrate, factor);
++ afreq = (u32)clkrate / (i + 1);
++
++ if (freq == afreq)
++ sub = 0;
++ else if (freq / afreq == 1)
++ sub = freq - afreq;
++ else if (afreq / freq == 1)
++ sub = afreq - freq;
++ else
++ continue;
++
++ /* Calculate the fraction */
++ sub *= 100000;
++ do_div(sub, freq);
++
++ if (sub < savesub) {
++ ssi_private->sysrate = sysrate;
++ savesub = sub;
++ pm = i;
++ }
++
++ /* We are lucky */
++ if (savesub == 0)
++ break;
++ }
++
++ /* No proper pm found if it is still remaining the initial value */
++ if (pm == 999) {
++ dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
+ return -EINVAL;
+ }
+
++ stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0)
++ | (psr ? CCSR_SSI_SxCCR_PSR : 0);
++ mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2_MASK
++ | CCSR_SSI_SxCCR_PSR_MASK;
++
++ if (dir == SND_SOC_CLOCK_OUT || synchronous)
++ write_ssi_mask(&ssi->stccr, mask, stccr);
++ else
++ write_ssi_mask(&ssi->srccr, mask, stccr);
++
++ return 0;
++}
++
++static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
++ u32 rx_mask, int slots, int slot_width)
++{
++ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
++ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++
++ write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
++ CCSR_SSI_SxCCR_DC(slots));
++ write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
++ CCSR_SSI_SxCCR_DC(slots));
++
++ /* The register SxMSKs need SSI to provide essential clock due to
++ * hardware design. So we here temporarily enable SSI to set them.
++ */
++ write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
++ write_ssi(tx_mask, &ssi->stmsk);
++ write_ssi(rx_mask, &ssi->srmsk);
++ write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
++
+ return 0;
+ }
+
+@@ -536,13 +783,20 @@
+
+ ssi_private->second_stream = NULL;
+
+- /*
+- * If this is the last active substream, disable the SSI.
+- */
++ /* If this is the last active substream, disable the interrupts. */
+ if (!ssi_private->first_stream) {
+ struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+
+- write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
++ write_ssi_mask(&ssi->sier, SIER_FLAGS, 0);
++
++ ssi_private->sysrate = 0;
++ }
++
++ if (ssi_private->ssi_on_imx) {
++ clk_disable_unprepare(ssi_private->clk);
++ clk_disable_unprepare(ssi_private->coreclk);
++
++ pm_runtime_put_sync(dai->dev);
+ }
+ }
+
+@@ -561,6 +815,9 @@
+ static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
+ .startup = fsl_ssi_startup,
+ .hw_params = fsl_ssi_hw_params,
++ .set_fmt = fsl_ssi_set_dai_fmt,
++ .set_sysclk = fsl_ssi_set_dai_sysclk,
++ .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
+ .shutdown = fsl_ssi_shutdown,
+ .trigger = fsl_ssi_trigger,
+ };
+@@ -569,14 +826,13 @@
+ static struct snd_soc_dai_driver fsl_ssi_dai_template = {
+ .probe = fsl_ssi_dai_probe,
+ .playback = {
+- /* The SSI does not support monaural audio. */
+- .channels_min = 2,
++ .channels_min = 1,
+ .channels_max = 2,
+ .rates = FSLSSI_I2S_RATES,
+ .formats = FSLSSI_I2S_FORMATS,
+ },
+ .capture = {
+- .channels_min = 2,
++ .channels_min = 1,
+ .channels_max = 2,
+ .rates = FSLSSI_I2S_RATES,
+ .formats = FSLSSI_I2S_FORMATS,
+@@ -663,7 +919,6 @@
+ const uint32_t *iprop;
+ struct resource res;
+ char name[64];
+- bool shared;
+
+ /* SSIs that are not connected on the board should have a
+ * status = "disabled"
+@@ -672,13 +927,6 @@
+ if (!of_device_is_available(np))
+ return -ENODEV;
+
+- /* We only support the SSI in "I2S Slave" mode */
+- sprop = of_get_property(np, "fsl,mode", NULL);
+- if (!sprop || strcmp(sprop, "i2s-slave")) {
+- dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
+- return -ENODEV;
+- }
+-
+ /* The DAI name is the last part of the full name of the node. */
+ p = strrchr(np->full_name, '/') + 1;
+ ssi_private = kzalloc(sizeof(struct fsl_ssi_private) + strlen(p),
+@@ -737,16 +985,20 @@
+ ssi_private->fifo_depth = 8;
+
+ if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
+- u32 dma_events[2];
+ ssi_private->ssi_on_imx = true;
+
+- ssi_private->clk = clk_get(&pdev->dev, NULL);
++ ssi_private->coreclk = devm_clk_get(&pdev->dev, "ipg");
++ if (IS_ERR(ssi_private->coreclk)) {
++ ret = PTR_ERR(ssi_private->coreclk);
++ dev_err(&pdev->dev, "could not get ipg clock: %d\n", ret);
++ goto error_irq;
++ }
++ ssi_private->clk = devm_clk_get(&pdev->dev, "baud");
+ if (IS_ERR(ssi_private->clk)) {
+ ret = PTR_ERR(ssi_private->clk);
+- dev_err(&pdev->dev, "could not get clock: %d\n", ret);
++ dev_err(&pdev->dev, "could not get baud clock: %d\n", ret);
+ goto error_irq;
+ }
+- clk_prepare_enable(ssi_private->clk);
+
+ /*
+ * We have burstsize be "fifo_depth - 2" to match the SSI
+@@ -760,30 +1012,10 @@
+ ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
+ ssi_private->dma_params_rx.addr =
+ ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
+- ssi_private->dma_params_tx.filter_data =
+- &ssi_private->filter_data_tx;
+- ssi_private->dma_params_rx.filter_data =
+- &ssi_private->filter_data_rx;
+- /*
+- * TODO: This is a temporary solution and should be changed
+- * to use generic DMA binding later when the helplers get in.
+- */
+- ret = of_property_read_u32_array(pdev->dev.of_node,
+- "fsl,ssi-dma-events", dma_events, 2);
+- if (ret) {
+- dev_err(&pdev->dev, "could not get dma events\n");
+- goto error_clk;
+- }
+-
+- shared = of_device_is_compatible(of_get_parent(np),
+- "fsl,spba-bus");
+-
+- imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
+- dma_events[0], shared);
+- imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
+- dma_events[1], shared);
+ }
+
++ ssi_private->sysrate = 0;
++
+ /* Initialize the the device_attribute structure */
+ dev_attr = &ssi_private->dev_attr;
+ sysfs_attr_init(&dev_attr->attr);
+@@ -798,6 +1030,8 @@
+ goto error_irq;
+ }
+
++ pm_runtime_enable(&pdev->dev);
++
+ /* Register with ASoC */
+ dev_set_drvdata(&pdev->dev, ssi_private);
+
+@@ -809,15 +1043,15 @@
+ }
+
+ if (ssi_private->ssi_on_imx) {
+- ssi_private->imx_pcm_pdev =
+- platform_device_register_simple("imx-pcm-audio",
+- -1, NULL, 0);
+- if (IS_ERR(ssi_private->imx_pcm_pdev)) {
+- ret = PTR_ERR(ssi_private->imx_pcm_pdev);
++ ret = imx_pcm_dma_init(pdev, SND_DMAENGINE_PCM_FLAG_NO_RESIDUE,
++ IMX_SSI_DMABUF_SIZE);
++ if (ret)
+ goto error_dev;
+- }
+ }
+
++ /* Enable dual fifo feature as default */
++ ssi_private->use_dual_fifo = true;
++
+ /*
+ * If codec-handle property is missing from SSI node, we assume
+ * that the machine driver uses new binding which does not require
+@@ -854,19 +1088,13 @@
+
+ error_dai:
+ if (ssi_private->ssi_on_imx)
+- platform_device_unregister(ssi_private->imx_pcm_pdev);
++ imx_pcm_dma_exit(pdev);
+ snd_soc_unregister_component(&pdev->dev);
+
+ error_dev:
+ dev_set_drvdata(&pdev->dev, NULL);
+ device_remove_file(&pdev->dev, dev_attr);
+
+-error_clk:
+- if (ssi_private->ssi_on_imx) {
+- clk_disable_unprepare(ssi_private->clk);
+- clk_put(ssi_private->clk);
+- }
+-
+ error_irq:
+ free_irq(ssi_private->irq, ssi_private);
+
+@@ -888,11 +1116,9 @@
+
+ if (!ssi_private->new_binding)
+ platform_device_unregister(ssi_private->pdev);
+- if (ssi_private->ssi_on_imx) {
+- platform_device_unregister(ssi_private->imx_pcm_pdev);
+- clk_disable_unprepare(ssi_private->clk);
+- clk_put(ssi_private->clk);
+- }
++ if (ssi_private->ssi_on_imx)
++ imx_pcm_dma_exit(pdev);
++
+ snd_soc_unregister_component(&pdev->dev);
+ device_remove_file(&pdev->dev, &ssi_private->dev_attr);
+
+@@ -905,6 +1131,26 @@
+ return 0;
+ }
+
++#ifdef CONFIG_PM_RUNTIME
++static int fsl_ssi_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_AUDIO);
++ return 0;
++}
++
++static int fsl_ssi_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_AUDIO);
++ return 0;
++}
++#endif
++
++static const struct dev_pm_ops fsl_ssi_pm = {
++ SET_RUNTIME_PM_OPS(fsl_ssi_runtime_suspend,
++ fsl_ssi_runtime_resume,
++ NULL)
++};
++
+ static const struct of_device_id fsl_ssi_ids[] = {
+ { .compatible = "fsl,mpc8610-ssi", },
+ { .compatible = "fsl,imx21-ssi", },
+@@ -917,6 +1163,7 @@
+ .name = "fsl-ssi-dai",
+ .owner = THIS_MODULE,
+ .of_match_table = fsl_ssi_ids,
++ .pm = &fsl_ssi_pm,
+ },
+ .probe = fsl_ssi_probe,
+ .remove = fsl_ssi_remove,
+@@ -924,6 +1171,7 @@
+
+ module_platform_driver(fsl_ssi_driver);
+
++MODULE_ALIAS("platform:fsl-ssi-dai");
+ MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
+ MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
+ MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/fsl_ssi.h linux-linaro-stable-mx6/sound/soc/fsl/fsl_ssi.h
+--- linux-3.10.30.orig/sound/soc/fsl/fsl_ssi.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/fsl_ssi.h 2014-05-15 20:34:23.822199874 +0200
+@@ -3,7 +3,7 @@
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+- * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed
++ * Copyright 2007-2013 Freescale Semiconductor, Inc. This file is licensed
+ * under the terms of the GNU General Public License version 2. This
+ * program is licensed "as is" without any warranty of any kind, whether
+ * express or implied.
+@@ -125,7 +125,11 @@
+ #define CCSR_SSI_SRCR_REFS 0x00000001
+
+ /* STCCR and SRCCR */
++#define CCSR_SSI_SxCCR_DIV2_SHIFT 18
++#define CCSR_SSI_SxCCR_DIV2_MASK 0x00040000
+ #define CCSR_SSI_SxCCR_DIV2 0x00040000
++#define CCSR_SSI_SxCCR_PSR_SHIFT 17
++#define CCSR_SSI_SxCCR_PSR_MASK 0x00020000
+ #define CCSR_SSI_SxCCR_PSR 0x00020000
+ #define CCSR_SSI_SxCCR_WL_SHIFT 13
+ #define CCSR_SSI_SxCCR_WL_MASK 0x0001E000
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-cs42888.c linux-linaro-stable-mx6/sound/soc/fsl/imx-cs42888.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-cs42888.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-cs42888.c 2014-05-15 20:34:23.826199902 +0200
+@@ -0,0 +1,370 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/of_i2c.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/initval.h>
++#include <sound/pcm_params.h>
++
++#include "fsl_esai.h"
++#include "fsl_asrc.h"
++
++#define CODEC_CLK_EXTER_OSC 1
++#define CODEC_CLK_ESAI_HCKT 2
++
++struct imx_priv {
++ int hw;
++ int fe_output_rate;
++ int fe_output_width;
++ unsigned int mclk_freq;
++ unsigned int codec_mclk;
++ struct platform_device *pdev;
++};
++
++static struct imx_priv card_priv;
++
++static int imx_cs42888_startup(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct imx_priv *priv = &card_priv;
++
++ if (!cpu_dai->active)
++ priv->hw = 0;
++ return 0;
++}
++
++static void imx_cs42888_shutdown(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct imx_priv *priv = &card_priv;
++
++ if (!cpu_dai->active)
++ priv->hw = 0;
++}
++
++static const struct {
++ int rate;
++ int ratio1;
++ int ratio2;
++} sr_vals[] = {
++ { 32000, 5, 3 },
++ { 48000, 5, 3 },
++ { 64000, 2, 1 },
++ { 96000, 2, 1 },
++ { 128000, 2, 1 },
++ { 44100, 5, 3 },
++ { 88200, 2, 1 },
++ { 176400, 0, 0 },
++ { 192000, 0, 0 },
++};
++
++static int imx_cs42888_surround_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct imx_priv *priv = &card_priv;
++ unsigned int rate = params_rate(params);
++ unsigned int lrclk_ratio = 0, i;
++ u32 dai_format = 0;
++
++ if (priv->hw)
++ return 0;
++
++ priv->hw = 1;
++
++ if (priv->codec_mclk & CODEC_CLK_ESAI_HCKT) {
++ for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
++ if (sr_vals[i].rate == rate) {
++ lrclk_ratio = sr_vals[i].ratio1;
++ break;
++ }
++ }
++ if (i == ARRAY_SIZE(sr_vals)) {
++ dev_err(&priv->pdev->dev, "Unsupported rate %dHz\n", rate);
++ return -EINVAL;
++ }
++
++ dai_format = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS;
++
++ /* set the ESAI system clock as output */
++ snd_soc_dai_set_sysclk(cpu_dai, ESAI_CLK_EXTAL_DIV,
++ priv->mclk_freq, SND_SOC_CLOCK_OUT);
++ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PM, 2);
++ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PM, 2);
++ /* set codec Master clock */
++ snd_soc_dai_set_sysclk(codec_dai, 0, priv->mclk_freq,\
++ SND_SOC_CLOCK_IN);
++ } else if (priv->codec_mclk & CODEC_CLK_EXTER_OSC) {
++ for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
++ if (sr_vals[i].rate == rate) {
++ lrclk_ratio = sr_vals[i].ratio2;
++ break;
++ }
++ }
++ if (i == ARRAY_SIZE(sr_vals)) {
++ dev_err(&priv->pdev->dev, "Unsupported rate %dHz\n", rate);
++ return -EINVAL;
++ }
++
++ dai_format = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ snd_soc_dai_set_sysclk(cpu_dai, ESAI_CLK_EXTAL,
++ priv->mclk_freq, SND_SOC_CLOCK_IN);
++ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PM, 0);
++ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PM, 0);
++ snd_soc_dai_set_sysclk(codec_dai, 0, priv->mclk_freq,\
++ SND_SOC_CLOCK_OUT);
++ }
++
++ /* set cpu DAI configuration */
++ snd_soc_dai_set_fmt(cpu_dai, dai_format);
++ /* set i.MX active slot mask */
++ snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 2, 32);
++ /* set the ratio */
++ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PSR, 1);
++ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_FP, lrclk_ratio);
++ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PSR, 1);
++ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_FP, lrclk_ratio);
++
++ /* set codec DAI configuration */
++ snd_soc_dai_set_fmt(codec_dai, dai_format);
++ return 0;
++}
++
++static struct snd_soc_ops imx_cs42888_surround_ops = {
++ .startup = imx_cs42888_startup,
++ .shutdown = imx_cs42888_shutdown,
++ .hw_params = imx_cs42888_surround_hw_params,
++};
++
++static const struct snd_soc_dapm_widget imx_cs42888_dapm_widgets[] = {
++ SND_SOC_DAPM_LINE("Line Out Jack", NULL),
++ SND_SOC_DAPM_LINE("Line In Jack", NULL),
++};
++
++static const struct snd_soc_dapm_route audio_map[] = {
++ /* Line out jack */
++ {"Line Out Jack", NULL, "AOUT1L"},
++ {"Line Out Jack", NULL, "AOUT1R"},
++ {"Line Out Jack", NULL, "AOUT2L"},
++ {"Line Out Jack", NULL, "AOUT2R"},
++ {"Line Out Jack", NULL, "AOUT3L"},
++ {"Line Out Jack", NULL, "AOUT3R"},
++ {"Line Out Jack", NULL, "AOUT4L"},
++ {"Line Out Jack", NULL, "AOUT4R"},
++ {"AIN1L", NULL, "Line In Jack"},
++ {"AIN1R", NULL, "Line In Jack"},
++ {"AIN2L", NULL, "Line In Jack"},
++ {"AIN2R", NULL, "Line In Jack"},
++ {"esai-Playback", NULL, "asrc-Playback"},
++ {"codec-Playback", NULL, "esai-Playback"},/*Playback is the codec dai*/
++};
++
++static int be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
++ struct snd_pcm_hw_params *params) {
++
++ struct imx_priv *priv = &card_priv;
++
++ hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE)->min = priv->fe_output_rate;
++ hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE)->max = priv->fe_output_rate;
++ snd_mask_none(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT));
++ if (priv->fe_output_width == 16)
++ snd_mask_set(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
++ SNDRV_PCM_FORMAT_S16_LE);
++ else
++ snd_mask_set(hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT),
++ SNDRV_PCM_FORMAT_S24_LE);
++ return 0;
++}
++
++static struct snd_soc_dai_link imx_cs42888_dai[] = {
++ {
++ .name = "HiFi",
++ .stream_name = "HiFi",
++ .codec_dai_name = "CS42888",
++ .ops = &imx_cs42888_surround_ops,
++ },
++ {
++ .name = "HiFi-ASRC-FE",
++ .stream_name = "HiFi-ASRC-FE",
++ .codec_name = "snd-soc-dummy",
++ .codec_dai_name = "snd-soc-dummy-dai",
++ .dynamic = 1,
++ },
++ {
++ .name = "HiFi-ASRC-BE",
++ .stream_name = "HiFi-ASRC-BE",
++ .codec_dai_name = "CS42888",
++ .platform_name = "snd-soc-dummy",
++ .no_pcm = 1,
++ .ops = &imx_cs42888_surround_ops,
++ .be_hw_params_fixup = be_hw_params_fixup,
++ },
++};
++
++static struct snd_soc_card snd_soc_card_imx_cs42888 = {
++ .name = "cs42888-audio",
++ .dai_link = imx_cs42888_dai,
++ .dapm_widgets = imx_cs42888_dapm_widgets,
++ .num_dapm_widgets = ARRAY_SIZE(imx_cs42888_dapm_widgets),
++ .dapm_routes = audio_map,
++ .num_dapm_routes = ARRAY_SIZE(audio_map),
++};
++
++/*
++ * This function will register the snd_soc_pcm_link drivers.
++ */
++static int imx_cs42888_probe(struct platform_device *pdev)
++{
++ struct device_node *esai_np, *codec_np;
++ struct device_node *asrc_np;
++ struct platform_device *esai_pdev;
++ struct platform_device *asrc_pdev = NULL;
++ struct i2c_client *codec_dev;
++ struct imx_priv *priv = &card_priv;
++ struct clk *codec_clk = NULL;
++ const char *mclk_name;
++ int ret;
++
++ priv->pdev = pdev;
++
++ esai_np = of_parse_phandle(pdev->dev.of_node, "esai-controller", 0);
++ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
++ if (!esai_np || !codec_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ asrc_np = of_parse_phandle(pdev->dev.of_node, "asrc-controller", 0);
++ if (asrc_np) {
++ asrc_pdev = of_find_device_by_node(asrc_np);
++ if (asrc_pdev) {
++ struct fsl_asrc_p2p *asrc_p2p;
++ asrc_p2p = platform_get_drvdata(asrc_pdev);
++ asrc_p2p->per_dev = ESAI;
++ priv->fe_output_rate = asrc_p2p->output_rate;
++ priv->fe_output_width = asrc_p2p->output_width;
++ }
++ }
++
++ esai_pdev = of_find_device_by_node(esai_np);
++ if (!esai_pdev) {
++ dev_err(&pdev->dev, "failed to find ESAI platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++ codec_dev = of_find_i2c_device_by_node(codec_np);
++ if (!codec_dev || !codec_dev->driver) {
++ dev_err(&pdev->dev, "failed to find codec platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ /*if there is no asrc controller, we only enable one device*/
++ if (!asrc_pdev) {
++ imx_cs42888_dai[0].codec_of_node = codec_np;
++ imx_cs42888_dai[0].cpu_dai_name = dev_name(&esai_pdev->dev);
++ imx_cs42888_dai[0].platform_of_node = esai_np;
++ snd_soc_card_imx_cs42888.num_links = 1;
++ } else {
++ imx_cs42888_dai[0].codec_of_node = codec_np;
++ imx_cs42888_dai[0].cpu_dai_name = dev_name(&esai_pdev->dev);
++ imx_cs42888_dai[0].platform_of_node = esai_np;
++ imx_cs42888_dai[1].cpu_dai_name = dev_name(&asrc_pdev->dev);
++ imx_cs42888_dai[1].platform_name = "imx-pcm-asrc";
++ imx_cs42888_dai[2].codec_of_node = codec_np;
++ imx_cs42888_dai[2].cpu_dai_name = dev_name(&esai_pdev->dev);
++ snd_soc_card_imx_cs42888.num_links = 3;
++ }
++
++ codec_clk = devm_clk_get(&codec_dev->dev, NULL);
++ if (IS_ERR(codec_clk)) {
++ ret = PTR_ERR(codec_clk);
++ dev_err(&codec_dev->dev, "failed to get codec clk: %d\n", ret);
++ goto fail;
++ }
++ priv->mclk_freq = clk_get_rate(codec_clk);
++
++ ret = of_property_read_string(codec_np, "clock-names", &mclk_name);
++ if (ret) {
++ dev_err(&pdev->dev, "%s: failed to get mclk source\n", __func__);
++ goto fail;
++ }
++ if (!strcmp(mclk_name, "codec_osc"))
++ priv->codec_mclk = CODEC_CLK_EXTER_OSC;
++ else if (!strcmp(mclk_name, "esai"))
++ priv->codec_mclk = CODEC_CLK_ESAI_HCKT;
++ else {
++ dev_err(&pdev->dev, "mclk source is not correct %s\n", mclk_name);
++ goto fail;
++ }
++
++ snd_soc_card_imx_cs42888.dev = &pdev->dev;
++
++ platform_set_drvdata(pdev, &snd_soc_card_imx_cs42888);
++
++ ret = snd_soc_register_card(&snd_soc_card_imx_cs42888);
++ if (ret)
++ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
++fail:
++ if (esai_np)
++ of_node_put(esai_np);
++ if (codec_np)
++ of_node_put(codec_np);
++ return ret;
++}
++
++static int imx_cs42888_remove(struct platform_device *pdev)
++{
++ snd_soc_unregister_card(&snd_soc_card_imx_cs42888);
++ return 0;
++}
++
++static const struct of_device_id imx_cs42888_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-cs42888", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver imx_cs42888_driver = {
++ .probe = imx_cs42888_probe,
++ .remove = imx_cs42888_remove,
++ .driver = {
++ .name = "imx-cs42888",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ .of_match_table = imx_cs42888_dt_ids,
++ },
++};
++module_platform_driver(imx_cs42888_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("ALSA SoC cs42888 Machine Layer Driver");
++MODULE_ALIAS("platform:imx-cs42888");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-hdmi.c linux-linaro-stable-mx6/sound/soc/fsl/imx-hdmi.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-hdmi.c 2014-05-15 20:34:23.826199902 +0200
+@@ -0,0 +1,113 @@
++/*
++ * ASoC HDMI Transmitter driver for IMX development boards
++ *
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * based on stmp3780_devb_hdmi.c
++ *
++ * Vladimir Barinov <vbarinov@embeddedalley.com>
++ *
++ * Copyright 2008 SigmaTel, Inc
++ * Copyright 2008 Embedded Alley Solutions, Inc
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <sound/soc.h>
++
++#include "imx-hdmi.h"
++
++/* imx digital audio interface glue - connects codec <--> CPU */
++static struct snd_soc_dai_link imx_hdmi_dai_link = {
++ .name = "i.MX HDMI Audio Tx",
++ .stream_name = "i.MX HDMI Audio Tx",
++ .codec_dai_name = "hdmi-hifi",
++ .codec_name = "hdmi-audio-codec",
++ .platform_name = "imx-hdmi-audio",
++};
++
++static struct snd_soc_card snd_soc_card_imx_hdmi = {
++ .name = "imx-hdmi-soc",
++ .dai_link = &imx_hdmi_dai_link,
++ .num_links = 1,
++};
++
++static int imx_hdmi_audio_probe(struct platform_device *pdev)
++{
++ struct device_node *hdmi_np, *np = pdev->dev.of_node;
++ struct snd_soc_card *card = &snd_soc_card_imx_hdmi;
++ struct platform_device *hdmi_pdev;
++ int ret = 0;
++
++ if (!hdmi_get_registered()) {
++ dev_err(&pdev->dev, "initialize HDMI-audio failed. load HDMI-video first!\n");
++ return -ENODEV;
++ }
++
++ hdmi_np = of_parse_phandle(np, "hdmi-controller", 0);
++ if (!hdmi_np) {
++ dev_err(&pdev->dev, "failed to find hdmi-audio cpudai\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ hdmi_pdev = of_find_device_by_node(hdmi_np);
++ if (!hdmi_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ card->dev = &pdev->dev;
++ card->dai_link->cpu_dai_name = dev_name(&hdmi_pdev->dev);
++
++ platform_set_drvdata(pdev, card);
++
++ ret = snd_soc_register_card(card);
++ if (ret)
++ dev_err(&pdev->dev, "failed to register card: %d\n", ret);
++
++end:
++ if (hdmi_np)
++ of_node_put(hdmi_np);
++
++ return ret;
++}
++
++static int imx_hdmi_audio_remove(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++ snd_soc_unregister_card(card);
++
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-hdmi", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
++
++static struct platform_driver imx_hdmi_audio_driver = {
++ .probe = imx_hdmi_audio_probe,
++ .remove = imx_hdmi_audio_remove,
++ .driver = {
++ .of_match_table = imx_hdmi_dt_ids,
++ .name = "imx-audio-hdmi",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ },
++};
++
++module_platform_driver(imx_hdmi_audio_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IMX HDMI TX ASoC driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-audio-hdmi");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-hdmi-dma.c linux-linaro-stable-mx6/sound/soc/fsl/imx-hdmi-dma.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-hdmi-dma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-hdmi-dma.c 2014-05-15 20:34:23.826199902 +0200
+@@ -0,0 +1,1104 @@
++/*
++ * imx-hdmi-dma.c -- HDMI DMA driver for ALSA Soc Audio Layer
++ *
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * based on imx-pcm-dma-mx2.c
++ * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
++ *
++ * This code is based on code copyrighted by Freescale,
++ * Liam Girdwood, Javier Martin and probably others.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/platform_data/dma-imx.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "imx-hdmi.h"
++
++#define HDMI_DMA_BURST_UNSPECIFIED_LEGNTH 0
++#define HDMI_DMA_BURST_INCR4 1
++#define HDMI_DMA_BURST_INCR8 2
++#define HDMI_DMA_BURST_INCR16 3
++
++#define HDMI_BASE_ADDR 0x00120000
++
++struct hdmi_sdma_script {
++ int control_reg_addr;
++ int status_reg_addr;
++ int dma_start_addr;
++ u32 buffer[20];
++};
++
++struct hdmi_dma_priv {
++ struct snd_pcm_substream *substream;
++ struct platform_device *pdev;
++
++ struct snd_dma_buffer hw_buffer;
++ unsigned long buffer_bytes;
++ unsigned long appl_bytes;
++
++ int periods;
++ int period_time;
++ int period_bytes;
++ int dma_period_bytes;
++ int buffer_ratio;
++
++ unsigned long offset;
++
++ snd_pcm_format_t format;
++ int sample_align;
++ int sample_bits;
++ int channels;
++ int rate;
++
++ int frame_idx;
++
++ bool tx_active;
++ spinlock_t irq_lock;
++
++ /* SDMA part */
++ dma_addr_t phy_hdmi_sdma_t;
++ struct hdmi_sdma_script *hdmi_sdma_t;
++ struct dma_chan *dma_channel;
++ struct imx_dma_data dma_data;
++ struct dma_async_tx_descriptor *desc;
++ struct imx_hdmi_sdma_params sdma_params;
++};
++
++/* bit 0:0:0:b:p(0):c:(u)0:(v)0 */
++/* max 8 channels supported; channels are interleaved */
++static u8 g_packet_head_table[48 * 8];
++
++union hdmi_audio_header_t iec_header;
++EXPORT_SYMBOL(iec_header);
++
++/*
++ * Note that the period size for DMA != period size for ALSA because the
++ * driver adds iec frame info to the audio samples (in hdmi_dma_copy).
++ *
++ * Each 4 byte subframe = 1 byte of iec data + 3 byte audio sample.
++ *
++ * A 16 bit audio sample becomes 32 bits including the frame info. Ratio=2
++ * A 24 bit audio sample becomes 32 bits including the frame info. Ratio=3:4
++ * If the 24 bit raw audio is in 32 bit words, the
++ *
++ * Original Packed into subframe Ratio of size Format
++ * sample how many size of DMA buffer
++ * (bits) bits to ALSA buffer
++ * -------- ----------- -------- -------------- ------------------------
++ * 16 16 32 2 SNDRV_PCM_FORMAT_S16_LE
++ * 24 24 32 1.33 SNDRV_PCM_FORMAT_S24_3LE*
++ * 24 32 32 1 SNDRV_PCM_FORMAT_S24_LE
++ *
++ * *so SNDRV_PCM_FORMAT_S24_3LE is not supported.
++ */
++
++/*
++ * The minimum dma period is one IEC audio frame (192 * 4 * channels).
++ * The maximum dma period for the HDMI DMA is 8K.
++ *
++ * channels minimum maximum
++ * dma period dma period
++ * -------- ------------------ ----------
++ * 2 192 * 4 * 2 = 1536 * 4 = 6144
++ * 4 192 * 4 * 4 = 3072 * 2 = 6144
++ * 6 192 * 4 * 6 = 4608 * 1 = 4608
++ * 8 192 * 4 * 8 = 6144 * 1 = 6144
++ *
++ * Bottom line:
++ * 1. Must keep the ratio of DMA buffer to ALSA buffer consistent.
++ * 2. frame_idx is saved in the private data, so even if a frame cannot be
++ * transmitted in a period, it can be continued in the next period. This
++ * is necessary for 6 ch.
++ */
++#define HDMI_DMA_PERIOD_BYTES (6144)
++#define HDMI_DMA_BUF_SIZE (64 * 1024)
++#define HDMI_PCM_BUF_SIZE (64 * 1024)
++
++#define hdmi_audio_debug(dev, reg) \
++ dev_dbg(dev, #reg ": 0x%02x\n", hdmi_readb(reg))
++
++#ifdef DEBUG
++static void dumpregs(struct device *dev)
++{
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_CONF0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_START);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STOP);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_THRSLD);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STRADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STPADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BSTADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MBLENGTH0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MBLENGTH1);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STAT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_INT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MASK);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_POL);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_CONF1);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFSTAT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFINT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFMASK);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFPOL);
++ hdmi_audio_debug(dev, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_audio_debug(dev, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_audio_debug(dev, HDMI_IH_MUTE);
++}
++
++static void dumppriv(struct device *dev, struct hdmi_dma_priv *priv)
++{
++ dev_dbg(dev, "channels = %d\n", priv->channels);
++ dev_dbg(dev, "periods = %d\n", priv->periods);
++ dev_dbg(dev, "period_bytes = %d\n", priv->period_bytes);
++ dev_dbg(dev, "dma period_bytes = %d\n", priv->dma_period_bytes);
++ dev_dbg(dev, "buffer_ratio = %d\n", priv->buffer_ratio);
++ dev_dbg(dev, "hw dma buffer = 0x%08x\n", (int)priv->hw_buffer.addr);
++ dev_dbg(dev, "dma buf size = %d\n", (int)priv->buffer_bytes);
++ dev_dbg(dev, "sample_rate = %d\n", (int)priv->rate);
++}
++#else
++static void dumpregs(struct device *dev) {}
++static void dumppriv(struct device *dev, struct hdmi_dma_priv *priv) {}
++#endif
++
++/*
++ * Conditions for DMA to work:
++ * ((final_addr - initial_addr)>>2)+1) < 2k. So max period is 8k.
++ * (inital_addr & 0x3) == 0
++ * (final_addr & 0x3) == 0x3
++ *
++ * The DMA Period should be an integer multiple of the IEC 60958 audio
++ * frame size, which is 768 bytes (192 * 4).
++ */
++static void hdmi_dma_set_addr(int start_addr, int dma_period_bytes)
++{
++ int final_addr = start_addr + dma_period_bytes - 1;
++
++ hdmi_write4(start_addr, HDMI_AHB_DMA_STRADDR0);
++ hdmi_write4(final_addr, HDMI_AHB_DMA_STPADDR0);
++}
++
++static void hdmi_dma_irq_set(bool set)
++{
++ u8 val = hdmi_readb(HDMI_AHB_DMA_MASK);
++
++ if (set)
++ val |= HDMI_AHB_DMA_DONE;
++ else
++ val &= (u8)~HDMI_AHB_DMA_DONE;
++
++ hdmi_writeb(val, HDMI_AHB_DMA_MASK);
++}
++
++static void hdmi_mask(int mask)
++{
++ u8 regval = hdmi_readb(HDMI_AHB_DMA_MASK);
++
++ if (mask)
++ regval |= HDMI_AHB_DMA_ERROR | HDMI_AHB_DMA_FIFO_EMPTY;
++ else
++ regval &= (u8)~(HDMI_AHB_DMA_ERROR | HDMI_AHB_DMA_FIFO_EMPTY);
++
++ hdmi_writeb(regval, HDMI_AHB_DMA_MASK);
++}
++
++int odd_ones(unsigned a)
++{
++ a ^= a >> 8;
++ a ^= a >> 4;
++ a ^= a >> 2;
++ a ^= a >> 1;
++
++ return a & 1;
++}
++
++/* Add frame information for one pcm subframe */
++static u32 hdmi_dma_add_frame_info(struct hdmi_dma_priv *priv,
++ u32 pcm_data, int subframe_idx)
++{
++ union hdmi_audio_dma_data_t subframe;
++
++ subframe.U = 0;
++ iec_header.B.channel = subframe_idx;
++
++ /* fill b (start-of-block) */
++ subframe.B.b = (priv->frame_idx == 0) ? 1 : 0;
++
++ /* fill c (channel status) */
++ if (priv->frame_idx < 42)
++ subframe.B.c = (iec_header.U >> priv->frame_idx) & 0x1;
++ else
++ subframe.B.c = 0;
++
++ subframe.B.p = odd_ones(pcm_data);
++ subframe.B.p ^= subframe.B.c;
++ subframe.B.p ^= subframe.B.u;
++ subframe.B.p ^= subframe.B.v;
++
++ /* fill data */
++ if (priv->sample_bits == 16)
++ subframe.B.data = pcm_data << 8;
++ else
++ subframe.B.data = pcm_data;
++
++ return subframe.U;
++}
++
++static void init_table(int channels)
++{
++ unsigned char *p = g_packet_head_table;
++ int i, ch = 0;
++
++ for (i = 0; i < 48; i++) {
++ int b = 0;
++ if (i == 0)
++ b = 1;
++
++ for (ch = 0; ch < channels; ch++) {
++ int c = 0;
++ if (i < 42) {
++ iec_header.B.channel = ch+1;
++ c = (iec_header.U >> i) & 0x1;
++ }
++ /* preset bit p as c */
++ *p++ = (b << 4) | (c << 2) | (c << 3);
++ }
++ }
++}
++
++/* Optimization for IEC head */
++static void hdmi_dma_copy_16_c_lut(u16 *src, u32 *dst, int samples,
++ u8 *lookup_table)
++{
++ u32 sample, head, p;
++ int i;
++
++ for (i = 0; i < samples; i++) {
++ /* get source sample */
++ sample = *src++;
++
++ /* xor every bit */
++ p = sample ^ (sample >> 8);
++ p ^= (p >> 4);
++ p ^= (p >> 2);
++ p ^= (p >> 1);
++ p &= 1; /* only want last bit */
++ p <<= 3; /* bit p */
++
++ /* get packet header */
++ head = *lookup_table++;
++
++ /* fix head */
++ head ^= p;
++
++ /* store */
++ *dst++ = (head << 24) | (sample << 8);
++ }
++}
++
++static void hdmi_dma_copy_16_c_fast(u16 *src, u32 *dst, int samples)
++{
++ u32 sample, p;
++ int i;
++
++ for (i = 0; i < samples; i++) {
++ /* get source sample */
++ sample = *src++;
++
++ /* xor every bit */
++ p = sample ^ (sample >> 8);
++ p ^= (p >> 4);
++ p ^= (p >> 2);
++ p ^= (p >> 1);
++ p &= 1; /* only want last bit */
++ p <<= 3; /* bit p */
++
++ /* store */
++ *dst++ = (p << 24) | (sample << 8);
++ }
++}
++
++static void hdmi_dma_copy_16(u16 *src, u32 *dst, int framecnt, int channelcnt)
++{
++ /* split input frames into 192-frame each */
++ int count_in_192 = (framecnt + 191) / 192;
++ int i;
++
++ for (i = 0; i < count_in_192; i++) {
++ int count, samples;
++
++ /* handles frame index [0, 48) */
++ count = (framecnt < 48) ? framecnt : 48;
++ samples = count * channelcnt;
++ hdmi_dma_copy_16_c_lut(src, dst, samples, g_packet_head_table);
++ framecnt -= count;
++ if (framecnt == 0)
++ break;
++
++ src += samples;
++ dst += samples;
++
++ /* handles frame index [48, 192) */
++ count = (framecnt < 192 - 48) ? framecnt : 192 - 48;
++ samples = count * channelcnt;
++ hdmi_dma_copy_16_c_fast(src, dst, samples);
++ framecnt -= count;
++ src += samples;
++ dst += samples;
++ }
++}
++
++static void hdmi_dma_mmap_copy(struct snd_pcm_substream *substream,
++ int offset, int count)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++ u32 framecount, *dst;
++ u16 *src16;
++
++ framecount = count / (priv->sample_align * priv->channels);
++
++ /* hw_buffer is the destination for pcm data plus frame info. */
++ dst = (u32 *)(priv->hw_buffer.area + (offset * priv->buffer_ratio));
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ /* dma_buffer is the mmapped buffer we are copying pcm from. */
++ src16 = (u16 *)(runtime->dma_area + offset);
++ hdmi_dma_copy_16(src16, dst, framecount, priv->channels);
++ break;
++ default:
++ dev_err(dev, "unsupported sample format %s\n",
++ snd_pcm_format_name(priv->format));
++ return;
++ }
++}
++
++static void hdmi_dma_data_copy(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv, char type)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ unsigned long offset, count, appl_bytes, space_to_end;
++
++ if (runtime->access != SNDRV_PCM_ACCESS_MMAP_INTERLEAVED)
++ return;
++
++ appl_bytes = frames_to_bytes(runtime, runtime->status->hw_ptr);
++ if (type == 'p')
++ appl_bytes += 2 * priv->period_bytes;
++ offset = appl_bytes % priv->buffer_bytes;
++
++ switch (type) {
++ case 'p':
++ count = priv->period_bytes;
++ space_to_end = priv->period_bytes;
++ break;
++ case 'b':
++ count = priv->buffer_bytes;
++ space_to_end = priv->buffer_bytes - offset;
++
++ break;
++ default:
++ return;
++ }
++
++ if (count <= space_to_end) {
++ hdmi_dma_mmap_copy(substream, offset, count);
++ } else {
++ hdmi_dma_mmap_copy(substream, offset, space_to_end);
++ hdmi_dma_mmap_copy(substream, 0, count - space_to_end);
++ }
++}
++
++static void hdmi_sdma_callback(void *data)
++{
++ struct hdmi_dma_priv *priv = (struct hdmi_dma_priv *)data;
++ struct snd_pcm_substream *substream = priv->substream;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ if (runtime && runtime->dma_area && priv->tx_active) {
++ priv->offset += priv->period_bytes;
++ priv->offset %= priv->period_bytes * priv->periods;
++
++ /* Copy data by period_bytes */
++ hdmi_dma_data_copy(substream, priv, 'p');
++
++ snd_pcm_period_elapsed(substream);
++ }
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++
++ return;
++}
++
++static int hdmi_dma_set_thrsld_incrtype(struct device *dev, int channels)
++{
++ u8 mask = HDMI_AHB_DMA_CONF0_BURST_MODE | HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK;
++ u8 val = hdmi_readb(HDMI_AHB_DMA_CONF0) & ~mask;
++ int incr_type, threshold;
++
++ switch (hdmi_readb(HDMI_REVISION_ID)) {
++ case 0x0a:
++ incr_type = HDMI_DMA_BURST_INCR4;
++ if (channels == 2)
++ threshold = 126;
++ else
++ threshold = 124;
++ break;
++ case 0x1a:
++ incr_type = HDMI_DMA_BURST_INCR8;
++ threshold = 128;
++ break;
++ default:
++ dev_err(dev, "unknown hdmi controller!\n");
++ return -ENODEV;
++ }
++
++ hdmi_writeb(threshold, HDMI_AHB_DMA_THRSLD);
++
++ switch (incr_type) {
++ case HDMI_DMA_BURST_UNSPECIFIED_LEGNTH:
++ break;
++ case HDMI_DMA_BURST_INCR4:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE;
++ break;
++ case HDMI_DMA_BURST_INCR8:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE |
++ HDMI_AHB_DMA_CONF0_INCR8;
++ break;
++ case HDMI_DMA_BURST_INCR16:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE |
++ HDMI_AHB_DMA_CONF0_INCR16;
++ break;
++ default:
++ dev_err(dev, "invalid increment type: %d!", incr_type);
++ return -EINVAL;
++ }
++
++ hdmi_writeb(val, HDMI_AHB_DMA_CONF0);
++
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_THRSLD);
++
++ return 0;
++}
++
++static int hdmi_dma_configure_dma(struct device *dev, int channels)
++{
++ u8 i, val = 0;
++ int ret;
++
++ if (channels <= 0 || channels > 8 || channels % 2 != 0) {
++ dev_err(dev, "unsupported channel number: %d\n", channels);
++ return -EINVAL;
++ }
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, EN_HLOCK, 0x1);
++
++ ret = hdmi_dma_set_thrsld_incrtype(dev, channels);
++ if (ret)
++ return ret;
++
++ for (i = 0; i < channels; i += 2)
++ val |= 0x3 << i;
++
++ hdmi_writeb(val, HDMI_AHB_DMA_CONF1);
++
++ return 0;
++}
++
++static void hdmi_dma_init_iec_header(void)
++{
++ iec_header.U = 0;
++
++ iec_header.B.consumer = 0; /* Consumer use */
++ iec_header.B.linear_pcm = 0; /* linear pcm audio */
++ iec_header.B.copyright = 1; /* no copyright */
++ iec_header.B.pre_emphasis = 0; /* 2 channels without pre-emphasis */
++ iec_header.B.mode = 0; /* Mode 0 */
++
++ iec_header.B.category_code = 0;
++
++ iec_header.B.source = 2; /* stereo */
++ iec_header.B.channel = 0;
++
++ iec_header.B.sample_freq = 0x02; /* 48 KHz */
++ iec_header.B.clock_acc = 0; /* Level II */
++
++ iec_header.B.word_length = 0x02; /* 16 bits */
++ iec_header.B.org_sample_freq = 0x0D; /* 48 KHz */
++
++ iec_header.B.cgms_a = 0; /* Copying is permitted without restriction */
++}
++
++static int hdmi_dma_update_iec_header(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++
++ iec_header.B.source = priv->channels;
++
++ switch (priv->rate) {
++ case 32000:
++ iec_header.B.sample_freq = 0x03;
++ iec_header.B.org_sample_freq = 0x0C;
++ break;
++ case 44100:
++ iec_header.B.sample_freq = 0x00;
++ iec_header.B.org_sample_freq = 0x0F;
++ break;
++ case 48000:
++ iec_header.B.sample_freq = 0x02;
++ iec_header.B.org_sample_freq = 0x0D;
++ break;
++ case 88200:
++ iec_header.B.sample_freq = 0x08;
++ iec_header.B.org_sample_freq = 0x07;
++ break;
++ case 96000:
++ iec_header.B.sample_freq = 0x0A;
++ iec_header.B.org_sample_freq = 0x05;
++ break;
++ case 176400:
++ iec_header.B.sample_freq = 0x0C;
++ iec_header.B.org_sample_freq = 0x03;
++ break;
++ case 192000:
++ iec_header.B.sample_freq = 0x0E;
++ iec_header.B.org_sample_freq = 0x01;
++ break;
++ default:
++ dev_err(dev, "unsupported sample rate\n");
++ return -EFAULT;
++ }
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ iec_header.B.word_length = 0x02;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ iec_header.B.word_length = 0x0b;
++ break;
++ default:
++ return -EFAULT;
++ }
++
++ return 0;
++}
++
++/*
++ * The HDMI block transmits the audio data without adding any of the audio
++ * frame bits. So we have to copy the raw dma data from the ALSA buffer
++ * to the DMA buffer, adding the frame information.
++ */
++static int hdmi_dma_copy(struct snd_pcm_substream *substream, int channel,
++ snd_pcm_uframes_t pos, void __user *buf,
++ snd_pcm_uframes_t frames)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ unsigned int count = frames_to_bytes(runtime, frames);
++ unsigned int pos_bytes = frames_to_bytes(runtime, pos);
++ u32 *hw_buf;
++ int subframe_idx;
++ u32 pcm_data;
++
++ /* Adding frame info to pcm data from userspace and copy to hw_buffer */
++ hw_buf = (u32 *)(priv->hw_buffer.area + (pos_bytes * priv->buffer_ratio));
++
++ while (count > 0) {
++ for (subframe_idx = 1 ; subframe_idx <= priv->channels ; subframe_idx++) {
++ if (copy_from_user(&pcm_data, buf, priv->sample_align))
++ return -EFAULT;
++
++ buf += priv->sample_align;
++ count -= priv->sample_align;
++
++ /* Save the header info to the audio dma buffer */
++ *hw_buf++ = hdmi_dma_add_frame_info(priv, pcm_data, subframe_idx);
++ }
++
++ priv->frame_idx++;
++ if (priv->frame_idx == 192)
++ priv->frame_idx = 0;
++ }
++
++ return 0;
++}
++
++static int hdmi_sdma_initbuf(struct device *dev, struct hdmi_dma_priv *priv)
++{
++ struct hdmi_sdma_script *hdmi_sdma_t = priv->hdmi_sdma_t;
++ u32 *head, *tail, i;
++
++ if (!hdmi_sdma_t) {
++ dev_err(dev, "hdmi private addr invalid!!!\n");
++ return -EINVAL;
++ }
++
++ hdmi_sdma_t->control_reg_addr = HDMI_BASE_ADDR + HDMI_AHB_DMA_START;
++ hdmi_sdma_t->status_reg_addr = HDMI_BASE_ADDR + HDMI_IH_AHBDMAAUD_STAT0;
++ hdmi_sdma_t->dma_start_addr = HDMI_BASE_ADDR + HDMI_AHB_DMA_STRADDR0;
++
++ head = &hdmi_sdma_t->buffer[0];
++ tail = &hdmi_sdma_t->buffer[1];
++
++ for (i = 0; i < priv->sdma_params.buffer_num; i++) {
++ *head = priv->hw_buffer.addr + i * priv->period_bytes * priv->buffer_ratio;
++ *tail = *head + priv->dma_period_bytes - 1;
++ head += 2;
++ tail += 2;
++ }
++
++ return 0;
++}
++
++static int hdmi_sdma_config(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dai_dev = &priv->pdev->dev;
++ struct device *dev = rtd->platform->dev;
++ struct dma_slave_config slave_config;
++ int ret;
++
++ priv->dma_channel = dma_request_slave_channel(dai_dev, "tx");
++ if (priv->dma_channel == NULL) {
++ dev_err(dev, "failed to alloc dma channel\n");
++ return -EBUSY;
++ }
++
++ priv->dma_data.data_addr1 = &priv->sdma_params.buffer_num;
++ priv->dma_data.data_addr2 = &priv->sdma_params.phyaddr;
++ priv->dma_channel->private = &priv->dma_data;
++
++ slave_config.direction = DMA_TRANS_NONE;
++ slave_config.dma_request0 = 0;
++ slave_config.dma_request1 = 0;
++
++ ret = dmaengine_slave_config(priv->dma_channel, &slave_config);
++ if (ret) {
++ dev_err(dev, "failed to config slave dma\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int hdmi_dma_hw_free(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ if (priv->dma_channel) {
++ dma_release_channel(priv->dma_channel);
++ priv->dma_channel = NULL;
++ }
++
++ return 0;
++}
++
++static int hdmi_dma_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++ int ret;
++
++ priv->buffer_bytes = params_buffer_bytes(params);
++ priv->periods = params_periods(params);
++ priv->period_bytes = params_period_bytes(params);
++ priv->channels = params_channels(params);
++ priv->format = params_format(params);
++ priv->rate = params_rate(params);
++
++ priv->offset = 0;
++ priv->period_time = HZ / (priv->rate / params_period_size(params));
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ priv->buffer_ratio = 2;
++ priv->sample_align = 2;
++ priv->sample_bits = 16;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ /* 24 bit audio in 32 bit word */
++ priv->buffer_ratio = 1;
++ priv->sample_align = 4;
++ priv->sample_bits = 24;
++ break;
++ default:
++ dev_err(dev, "unsupported sample format: %d\n", priv->format);
++ return -EINVAL;
++ }
++
++ priv->dma_period_bytes = priv->period_bytes * priv->buffer_ratio;
++ priv->sdma_params.buffer_num = priv->periods;
++ priv->sdma_params.phyaddr = priv->phy_hdmi_sdma_t;
++
++ ret = hdmi_sdma_initbuf(dev, priv);
++ if (ret)
++ return ret;
++
++ ret = hdmi_sdma_config(substream, priv);
++ if (ret)
++ return ret;
++
++ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
++
++ ret = hdmi_dma_configure_dma(dev, priv->channels);
++ if (ret)
++ return ret;
++
++ hdmi_dma_set_addr(priv->hw_buffer.addr, priv->dma_period_bytes);
++
++ dumppriv(dev, priv);
++
++ hdmi_dma_update_iec_header(substream);
++
++ /* Init par for mmap optimizate */
++ init_table(priv->channels);
++
++ priv->appl_bytes = 0;
++
++ return 0;
++}
++
++static void hdmi_dma_trigger_init(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ unsigned long status;
++
++ priv->frame_idx = 0;
++
++ /* Copy data by buffer_bytes */
++ hdmi_dma_data_copy(substream, priv, 'b');
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, SW_FIFO_RST, 0x1);
++
++ /* Delay after reset */
++ udelay(1);
++
++ status = hdmi_readb(HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_writeb(status, HDMI_IH_AHBDMAAUD_STAT0);
++}
++
++static int hdmi_dma_prepare_and_submit(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++
++ priv->desc = dmaengine_prep_dma_cyclic(priv->dma_channel, 0, 0, 0,
++ DMA_TRANS_NONE, 0);
++ if (!priv->desc) {
++ dev_err(dev, "failed to prepare slave dma\n");
++ return -EINVAL;
++ }
++
++ priv->desc->callback = hdmi_sdma_callback;
++ priv->desc->callback_param = (void *)priv;
++ dmaengine_submit(priv->desc);
++
++ return 0;
++}
++
++static int hdmi_dma_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++ int ret;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ if (!check_hdmi_state())
++ return 0;
++ hdmi_dma_trigger_init(substream, priv);
++
++ dumpregs(dev);
++
++ priv->tx_active = true;
++ hdmi_audio_writeb(AHB_DMA_START, START, 0x1);
++ hdmi_dma_irq_set(false);
++ hdmi_set_dma_mode(1);
++ ret = hdmi_dma_prepare_and_submit(substream, priv);
++ if (ret)
++ return ret;
++ dma_async_issue_pending(priv->desc->chan);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ dmaengine_terminate_all(priv->dma_channel);
++ hdmi_set_dma_mode(0);
++ hdmi_dma_irq_set(true);
++ hdmi_audio_writeb(AHB_DMA_STOP, STOP, 0x1);
++ priv->tx_active = false;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static snd_pcm_uframes_t hdmi_dma_pointer(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ return bytes_to_frames(runtime, priv->offset);
++}
++
++static struct snd_pcm_hardware snd_imx_hardware = {
++ .info = SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID |
++ SNDRV_PCM_INFO_PAUSE |
++ SNDRV_PCM_INFO_RESUME,
++ .formats = MXC_HDMI_FORMATS_PLAYBACK,
++ .rate_min = 32000,
++ .channels_min = 2,
++ .channels_max = 8,
++ .buffer_bytes_max = HDMI_PCM_BUF_SIZE,
++ .period_bytes_min = HDMI_DMA_PERIOD_BYTES / 2,
++ .period_bytes_max = HDMI_DMA_PERIOD_BYTES / 2,
++ .periods_min = 8,
++ .periods_max = 8,
++ .fifo_size = 0,
++};
++
++static void hdmi_dma_irq_enable(struct hdmi_dma_priv *priv)
++{
++ unsigned long flags;
++
++ hdmi_writeb(0xff, HDMI_AHB_DMA_POL);
++ hdmi_writeb(0xff, HDMI_AHB_DMA_BUFFPOL);
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ hdmi_writeb(0xff, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_dma_irq_set(false);
++ hdmi_mask(0);
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++}
++
++static void hdmi_dma_irq_disable(struct hdmi_dma_priv *priv)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ hdmi_dma_irq_set(true);
++ hdmi_writeb(0x0, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_mask(1);
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++}
++
++static int hdmi_dma_open(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++ struct hdmi_dma_priv *priv = dev_get_drvdata(dev);
++ int ret;
++
++ runtime->private_data = priv;
++
++ ret = mxc_hdmi_register_audio(substream);
++ if (ret < 0) {
++ dev_err(dev, "HDMI Video is not ready!\n");
++ return ret;
++ }
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, SW_FIFO_RST, 0x1);
++
++ ret = snd_pcm_hw_constraint_integer(substream->runtime,
++ SNDRV_PCM_HW_PARAM_PERIODS);
++ if (ret < 0)
++ return ret;
++
++ snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
++
++ hdmi_dma_irq_enable(priv);
++
++ return 0;
++}
++
++static int hdmi_dma_close(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ hdmi_dma_irq_disable(priv);
++ mxc_hdmi_unregister_audio(substream);
++
++ return 0;
++}
++
++static struct snd_pcm_ops imx_hdmi_dma_pcm_ops = {
++ .open = hdmi_dma_open,
++ .close = hdmi_dma_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = hdmi_dma_hw_params,
++ .hw_free = hdmi_dma_hw_free,
++ .trigger = hdmi_dma_trigger,
++ .pointer = hdmi_dma_pointer,
++ .copy = hdmi_dma_copy,
++};
++
++static int imx_hdmi_dma_pcm_new(struct snd_soc_pcm_runtime *rtd)
++{
++ struct hdmi_dma_priv *priv = dev_get_drvdata(rtd->platform->dev);
++ struct snd_card *card = rtd->card->snd_card;
++ struct snd_pcm_substream *substream;
++ struct snd_pcm *pcm = rtd->pcm;
++ u64 dma_mask = DMA_BIT_MASK(32);
++ int ret = 0;
++
++ if (!card->dev->dma_mask)
++ card->dev->dma_mask = &dma_mask;
++ if (!card->dev->coherent_dma_mask)
++ card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
++
++ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
++ HDMI_PCM_BUF_SIZE, &substream->dma_buffer);
++ if (ret) {
++ dev_err(card->dev, "failed to alloc playback dma buffer\n");
++ return ret;
++ }
++
++ priv->substream = substream;
++
++ /* Alloc the hw_buffer */
++ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
++ HDMI_DMA_BUF_SIZE, &priv->hw_buffer);
++ if (ret) {
++ dev_err(card->dev, "failed to alloc hw dma buffer\n");
++ return ret;
++ }
++
++ return ret;
++}
++
++static void imx_hdmi_dma_pcm_free(struct snd_pcm *pcm)
++{
++ int stream = SNDRV_PCM_STREAM_PLAYBACK;
++ struct snd_pcm_substream *substream = pcm->streams[stream].substream;
++ struct snd_soc_pcm_runtime *rtd = pcm->private_data;
++ struct hdmi_dma_priv *priv = dev_get_drvdata(rtd->platform->dev);
++
++ if (substream) {
++ snd_dma_free_pages(&substream->dma_buffer);
++ substream->dma_buffer.area = NULL;
++ substream->dma_buffer.addr = 0;
++ }
++
++ /* Free the hw_buffer */
++ snd_dma_free_pages(&priv->hw_buffer);
++ priv->hw_buffer.area = NULL;
++ priv->hw_buffer.addr = 0;
++}
++
++static struct snd_soc_platform_driver imx_hdmi_platform = {
++ .ops = &imx_hdmi_dma_pcm_ops,
++ .pcm_new = imx_hdmi_dma_pcm_new,
++ .pcm_free = imx_hdmi_dma_pcm_free,
++};
++
++static int imx_soc_platform_probe(struct platform_device *pdev)
++{
++ struct imx_hdmi *hdmi_drvdata = platform_get_drvdata(pdev);
++ struct hdmi_dma_priv *priv;
++ int ret = 0;
++
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv) {
++ dev_err(&pdev->dev, "Failed to alloc hdmi_dma\n");
++ return -ENOMEM;
++ }
++
++ priv->hdmi_sdma_t = dma_alloc_coherent(NULL,
++ sizeof(struct hdmi_sdma_script),
++ &priv->phy_hdmi_sdma_t, GFP_KERNEL);
++ if (!priv->hdmi_sdma_t) {
++ dev_err(&pdev->dev, "Failed to alloc hdmi_sdma_t\n");
++ return -ENOMEM;
++ }
++
++ priv->tx_active = false;
++ spin_lock_init(&priv->irq_lock);
++
++ priv->pdev = hdmi_drvdata->pdev;
++
++ hdmi_dma_init_iec_header();
++
++ dev_set_drvdata(&pdev->dev, priv);
++
++ ret = snd_soc_register_platform(&pdev->dev, &imx_hdmi_platform);
++ if (ret)
++ goto err_plat;
++
++ return 0;
++
++err_plat:
++ dma_free_coherent(NULL, sizeof(struct hdmi_sdma_script),
++ priv->hdmi_sdma_t, priv->phy_hdmi_sdma_t);
++
++ return ret;
++}
++
++static int imx_soc_platform_remove(struct platform_device *pdev)
++{
++ struct hdmi_dma_priv *priv = dev_get_drvdata(&pdev->dev);
++
++ dma_free_coherent(NULL, sizeof(struct hdmi_sdma_script),
++ priv->hdmi_sdma_t, priv->phy_hdmi_sdma_t);
++
++ snd_soc_unregister_platform(&pdev->dev);
++
++ return 0;
++}
++
++static struct platform_driver imx_hdmi_dma_driver = {
++ .driver = {
++ .name = "imx-hdmi-audio",
++ .owner = THIS_MODULE,
++ },
++ .probe = imx_soc_platform_probe,
++ .remove = imx_soc_platform_remove,
++};
++
++module_platform_driver(imx_hdmi_dma_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX HDMI audio DMA");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-hdmi.h linux-linaro-stable-mx6/sound/soc/fsl/imx-hdmi.h
+--- linux-3.10.30.orig/sound/soc/fsl/imx-hdmi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-hdmi.h 2014-05-15 20:34:23.826199902 +0200
+@@ -0,0 +1,105 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __IMX_HDMI_H
++#define __IMX_HDMI_H
++
++struct imx_hdmi_sdma_params {
++ dma_addr_t phyaddr;
++ u32 buffer_num;
++ int dma;
++};
++
++struct imx_hdmi {
++ struct snd_soc_dai_driver cpu_dai_drv;
++ struct platform_device *codec_dev;
++ struct platform_device *dma_dev;
++ struct platform_device *pdev;
++ struct clk *isfr_clk;
++ struct clk *iahb_clk;
++};
++
++#define HDMI_MAX_RATES 7
++#define HDMI_MAX_SAMPLE_SIZE 3
++#define HDMI_MAX_CHANNEL_CONSTRAINTS 4
++
++#define MXC_HDMI_RATES_PLAYBACK \
++ (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
++ SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
++
++#define MXC_HDMI_FORMATS_PLAYBACK \
++ (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
++
++union hdmi_audio_header_t {
++ uint64_t U;
++ struct {
++ unsigned consumer:1;
++ unsigned linear_pcm:1;
++ unsigned copyright:1;
++ unsigned pre_emphasis:3;
++ unsigned mode:2;
++
++ unsigned category_code:8;
++
++ unsigned source:4;
++ unsigned channel:4;
++
++ unsigned sample_freq:4;
++ unsigned clock_acc:2;
++ unsigned reserved0:2;
++
++ unsigned word_length:4;
++ unsigned org_sample_freq:4;
++
++ unsigned cgms_a:2;
++ unsigned reserved1:6;
++
++ unsigned reserved2:8;
++
++ unsigned reserved3:8;
++ } B;
++ unsigned char status[8];
++};
++
++union hdmi_audio_dma_data_t {
++ uint32_t U;
++ struct {
++ unsigned data:24;
++ unsigned v:1;
++ unsigned u:1;
++ unsigned c:1;
++ unsigned p:1;
++ unsigned b:1;
++ unsigned reserved:3;
++ } B;
++};
++
++extern union hdmi_audio_header_t iec_header;
++
++#define hdmi_audio_writeb(reg, bit, val) \
++ do { \
++ hdmi_mask_writeb(val, HDMI_ ## reg, \
++ HDMI_ ## reg ## _ ## bit ## _OFFSET, \
++ HDMI_ ## reg ## _ ## bit ## _MASK); \
++ pr_debug("Set reg: HDMI_" #reg " (0x%x) "\
++ "bit: HDMI_" #reg "_" #bit " (%d) to val: %x\n", \
++ HDMI_ ## reg, HDMI_ ## reg ## _ ## bit ## _OFFSET, val); \
++ } while (0)
++
++#endif /* __IMX_HDMI_H */
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-mc13783.c linux-linaro-stable-mx6/sound/soc/fsl/imx-mc13783.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-mc13783.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-mc13783.c 2014-05-15 20:34:23.826199902 +0200
+@@ -64,7 +64,7 @@
+ .codec_dai_name = "mc13783-hifi",
+ .codec_name = "mc13783-codec",
+ .cpu_dai_name = "imx-ssi.0",
+- .platform_name = "imx-pcm-audio.0",
++ .platform_name = "imx-ssi.0",
+ .ops = &imx_mc13783_hifi_ops,
+ .symmetric_rates = 1,
+ .dai_fmt = FMT_SSI,
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-pcm.c linux-linaro-stable-mx6/sound/soc/fsl/imx-pcm.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-pcm.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-pcm.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,145 +0,0 @@
+-/*
+- * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
+- *
+- * This code is based on code copyrighted by Freescale,
+- * Liam Girdwood, Javier Martin and probably others.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- */
+-
+-#include <linux/dma-mapping.h>
+-#include <linux/module.h>
+-#include <sound/pcm.h>
+-#include <sound/soc.h>
+-#include "imx-pcm.h"
+-
+-int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
+- struct vm_area_struct *vma)
+-{
+- struct snd_pcm_runtime *runtime = substream->runtime;
+- int ret;
+-
+- ret = dma_mmap_writecombine(substream->pcm->card->dev, vma,
+- runtime->dma_area, runtime->dma_addr, runtime->dma_bytes);
+-
+- pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
+- runtime->dma_area,
+- runtime->dma_addr,
+- runtime->dma_bytes);
+- return ret;
+-}
+-EXPORT_SYMBOL_GPL(snd_imx_pcm_mmap);
+-
+-static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+-{
+- struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+- struct snd_dma_buffer *buf = &substream->dma_buffer;
+- size_t size = IMX_SSI_DMABUF_SIZE;
+-
+- buf->dev.type = SNDRV_DMA_TYPE_DEV;
+- buf->dev.dev = pcm->card->dev;
+- buf->private_data = NULL;
+- buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+- &buf->addr, GFP_KERNEL);
+- if (!buf->area)
+- return -ENOMEM;
+- buf->bytes = size;
+-
+- return 0;
+-}
+-
+-static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
+-
+-int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
+-{
+- struct snd_card *card = rtd->card->snd_card;
+- struct snd_pcm *pcm = rtd->pcm;
+- int ret = 0;
+-
+- if (!card->dev->dma_mask)
+- card->dev->dma_mask = &imx_pcm_dmamask;
+- if (!card->dev->coherent_dma_mask)
+- card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
+- if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
+- ret = imx_pcm_preallocate_dma_buffer(pcm,
+- SNDRV_PCM_STREAM_PLAYBACK);
+- if (ret)
+- goto out;
+- }
+-
+- if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
+- ret = imx_pcm_preallocate_dma_buffer(pcm,
+- SNDRV_PCM_STREAM_CAPTURE);
+- if (ret)
+- goto out;
+- }
+-
+-out:
+- return ret;
+-}
+-EXPORT_SYMBOL_GPL(imx_pcm_new);
+-
+-void imx_pcm_free(struct snd_pcm *pcm)
+-{
+- struct snd_pcm_substream *substream;
+- struct snd_dma_buffer *buf;
+- int stream;
+-
+- for (stream = 0; stream < 2; stream++) {
+- substream = pcm->streams[stream].substream;
+- if (!substream)
+- continue;
+-
+- buf = &substream->dma_buffer;
+- if (!buf->area)
+- continue;
+-
+- dma_free_writecombine(pcm->card->dev, buf->bytes,
+- buf->area, buf->addr);
+- buf->area = NULL;
+- }
+-}
+-EXPORT_SYMBOL_GPL(imx_pcm_free);
+-
+-static int imx_pcm_probe(struct platform_device *pdev)
+-{
+- if (strcmp(pdev->id_entry->name, "imx-fiq-pcm-audio") == 0)
+- return imx_pcm_fiq_init(pdev);
+-
+- return imx_pcm_dma_init(pdev);
+-}
+-
+-static int imx_pcm_remove(struct platform_device *pdev)
+-{
+- if (strcmp(pdev->id_entry->name, "imx-fiq-pcm-audio") == 0)
+- snd_soc_unregister_platform(&pdev->dev);
+- else
+- imx_pcm_dma_exit(pdev);
+-
+- return 0;
+-}
+-
+-static struct platform_device_id imx_pcm_devtype[] = {
+- { .name = "imx-pcm-audio", },
+- { .name = "imx-fiq-pcm-audio", },
+- { /* sentinel */ }
+-};
+-MODULE_DEVICE_TABLE(platform, imx_pcm_devtype);
+-
+-static struct platform_driver imx_pcm_driver = {
+- .driver = {
+- .name = "imx-pcm",
+- .owner = THIS_MODULE,
+- },
+- .id_table = imx_pcm_devtype,
+- .probe = imx_pcm_probe,
+- .remove = imx_pcm_remove,
+-};
+-module_platform_driver(imx_pcm_driver);
+-
+-MODULE_DESCRIPTION("Freescale i.MX PCM driver");
+-MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-pcm-dma.c linux-linaro-stable-mx6/sound/soc/fsl/imx-pcm-dma.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-pcm-dma.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-pcm-dma.c 2014-05-15 20:34:23.826199902 +0200
+@@ -11,9 +11,14 @@
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/device.h>
+ #include <linux/platform_device.h>
+ #include <linux/dmaengine.h>
+ #include <linux/types.h>
++#include <linux/platform_data/dma-imx.h>
+
+ #include <sound/core.h>
+ #include <sound/pcm.h>
+@@ -41,34 +46,105 @@
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+- .formats = SNDRV_PCM_FMTBIT_S16_LE,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE |
++ SNDRV_PCM_FMTBIT_S24_LE |
++ SNDRV_PCM_FMTBIT_S20_3LE,
+ .rate_min = 8000,
+ .channels_min = 2,
+ .channels_max = 2,
+- .buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
++ .buffer_bytes_max = IMX_DEFAULT_DMABUF_SIZE,
+ .period_bytes_min = 128,
+ .period_bytes_max = 65535, /* Limited by SDMA engine */
+- .periods_min = 2,
++ .periods_min = 4,
+ .periods_max = 255,
+ .fifo_size = 0,
+ };
+
++static void imx_pcm_dma_set_config_from_dai_data(
++ const struct snd_pcm_substream *substream,
++ const struct snd_dmaengine_dai_dma_data *dma_data,
++ struct dma_slave_config *slave_config)
++{
++ struct imx_dma_data *filter_data = dma_data->filter_data;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ slave_config->dst_addr = dma_data->addr;
++ slave_config->dst_maxburst = dma_data->maxburst;
++ if (dma_data->addr_width != DMA_SLAVE_BUSWIDTH_UNDEFINED)
++ slave_config->dst_addr_width = dma_data->addr_width;
++ } else {
++ slave_config->src_addr = dma_data->addr;
++ slave_config->src_maxburst = dma_data->maxburst;
++ if (dma_data->addr_width != DMA_SLAVE_BUSWIDTH_UNDEFINED)
++ slave_config->src_addr_width = dma_data->addr_width;
++ }
++
++ slave_config->slave_id = dma_data->slave_id;
++
++ /*
++ * In dma binding mode, there is no filter_data, so dma_request need to be
++ * set to zero.
++ */
++ if (filter_data) {
++ slave_config->dma_request0 = filter_data->dma_request0;
++ slave_config->dma_request1 = filter_data->dma_request1;
++ } else {
++ slave_config->dma_request0 = 0;
++ slave_config->dma_request1 = 0;
++ }
++}
++
++static int imx_pcm_dma_prepare_slave_config(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params, struct dma_slave_config *slave_config)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_dmaengine_dai_dma_data *dma_data;
++ int ret;
++
++ dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
++
++ ret = snd_hwparams_to_dma_slave_config(substream, params, slave_config);
++ if (ret)
++ return ret;
++
++ imx_pcm_dma_set_config_from_dai_data(substream, dma_data,
++ slave_config);
++
++ return 0;
++}
++
+ static const struct snd_dmaengine_pcm_config imx_dmaengine_pcm_config = {
+ .pcm_hardware = &imx_pcm_hardware,
+- .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
++ .prepare_slave_config = imx_pcm_dma_prepare_slave_config,
+ .compat_filter_fn = filter,
+- .prealloc_buffer_size = IMX_SSI_DMABUF_SIZE,
++ .prealloc_buffer_size = IMX_DEFAULT_DMABUF_SIZE,
+ };
+
+-int imx_pcm_dma_init(struct platform_device *pdev)
++int imx_pcm_dma_init(struct platform_device *pdev, unsigned int flags, size_t size)
+ {
+- return snd_dmaengine_pcm_register(&pdev->dev, &imx_dmaengine_pcm_config,
+- SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
+- SND_DMAENGINE_PCM_FLAG_NO_DT |
+- SND_DMAENGINE_PCM_FLAG_COMPAT);
++ struct snd_dmaengine_pcm_config *config;
++ struct snd_pcm_hardware *pcm_hardware;
++
++ config = devm_kzalloc(&pdev->dev,
++ sizeof(struct snd_dmaengine_pcm_config), GFP_KERNEL);
++ *config = imx_dmaengine_pcm_config;
++ if (size)
++ config->prealloc_buffer_size = size;
++
++ pcm_hardware = devm_kzalloc(&pdev->dev,
++ sizeof(struct snd_pcm_hardware), GFP_KERNEL);
++ *pcm_hardware = imx_pcm_hardware;
++ if (size)
++ pcm_hardware->buffer_bytes_max = size;
++
++ config->pcm_hardware = pcm_hardware;
++
++ return snd_dmaengine_pcm_register(&pdev->dev, config, flags);
+ }
++EXPORT_SYMBOL_GPL(imx_pcm_dma_init);
+
+ void imx_pcm_dma_exit(struct platform_device *pdev)
+ {
+ snd_dmaengine_pcm_unregister(&pdev->dev);
+ }
++EXPORT_SYMBOL_GPL(imx_pcm_dma_exit);
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-pcm-fiq.c linux-linaro-stable-mx6/sound/soc/fsl/imx-pcm-fiq.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-pcm-fiq.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-pcm-fiq.c 2014-05-15 20:34:23.826199902 +0200
+@@ -230,6 +230,22 @@
+ return 0;
+ }
+
++static int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
++ struct vm_area_struct *vma)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ int ret;
++
++ ret = dma_mmap_writecombine(substream->pcm->card->dev, vma,
++ runtime->dma_area, runtime->dma_addr, runtime->dma_bytes);
++
++ pr_debug("%s: ret: %d %p 0x%08x 0x%08x\n", __func__, ret,
++ runtime->dma_area,
++ runtime->dma_addr,
++ runtime->dma_bytes);
++ return ret;
++}
++
+ static struct snd_pcm_ops imx_pcm_ops = {
+ .open = snd_imx_open,
+ .close = snd_imx_close,
+@@ -241,6 +257,54 @@
+ .mmap = snd_imx_pcm_mmap,
+ };
+
++static int imx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
++{
++ struct snd_pcm_substream *substream = pcm->streams[stream].substream;
++ struct snd_dma_buffer *buf = &substream->dma_buffer;
++ size_t size = IMX_SSI_DMABUF_SIZE;
++
++ buf->dev.type = SNDRV_DMA_TYPE_DEV;
++ buf->dev.dev = pcm->card->dev;
++ buf->private_data = NULL;
++ buf->area = dma_alloc_writecombine(pcm->card->dev, size,
++ &buf->addr, GFP_KERNEL);
++ if (!buf->area)
++ return -ENOMEM;
++ buf->bytes = size;
++
++ return 0;
++}
++
++static u64 imx_pcm_dmamask = DMA_BIT_MASK(32);
++
++static int imx_pcm_new(struct snd_soc_pcm_runtime *rtd)
++{
++ struct snd_card *card = rtd->card->snd_card;
++ struct snd_pcm *pcm = rtd->pcm;
++ int ret = 0;
++
++ if (!card->dev->dma_mask)
++ card->dev->dma_mask = &imx_pcm_dmamask;
++ if (!card->dev->coherent_dma_mask)
++ card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
++ if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
++ ret = imx_pcm_preallocate_dma_buffer(pcm,
++ SNDRV_PCM_STREAM_PLAYBACK);
++ if (ret)
++ goto out;
++ }
++
++ if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
++ ret = imx_pcm_preallocate_dma_buffer(pcm,
++ SNDRV_PCM_STREAM_CAPTURE);
++ if (ret)
++ goto out;
++ }
++
++out:
++ return ret;
++}
++
+ static int ssi_irq = 0;
+
+ static int imx_pcm_fiq_new(struct snd_soc_pcm_runtime *rtd)
+@@ -273,6 +337,27 @@
+ return 0;
+ }
+
++static void imx_pcm_free(struct snd_pcm *pcm)
++{
++ struct snd_pcm_substream *substream;
++ struct snd_dma_buffer *buf;
++ int stream;
++
++ for (stream = 0; stream < 2; stream++) {
++ substream = pcm->streams[stream].substream;
++ if (!substream)
++ continue;
++
++ buf = &substream->dma_buffer;
++ if (!buf->area)
++ continue;
++
++ dma_free_writecombine(pcm->card->dev, buf->bytes,
++ buf->area, buf->addr);
++ buf->area = NULL;
++ }
++}
++
+ static void imx_pcm_fiq_free(struct snd_pcm *pcm)
+ {
+ mxc_set_irq_fiq(ssi_irq, 0);
+@@ -319,3 +404,10 @@
+
+ return ret;
+ }
++EXPORT_SYMBOL_GPL(imx_pcm_fiq_init);
++
++void imx_pcm_fiq_exit(struct platform_device *pdev)
++{
++ snd_soc_unregister_platform(&pdev->dev);
++}
++EXPORT_SYMBOL_GPL(imx_pcm_fiq_exit);
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-pcm.h linux-linaro-stable-mx6/sound/soc/fsl/imx-pcm.h
+--- linux-3.10.30.orig/sound/soc/fsl/imx-pcm.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-pcm.h 2014-05-15 20:34:23.826199902 +0200
+@@ -18,13 +18,17 @@
+ /*
+ * Do not change this as the FIQ handler depends on this size
+ */
++#define IMX_DEFAULT_DMABUF_SIZE (256 * 1024)
+ #define IMX_SSI_DMABUF_SIZE (64 * 1024)
++#define IMX_SPDIF_DMABUF_SIZE (64 * 1024)
++#define IMX_ESAI_DMABUF_SIZE (256 * 1024)
++#define IMX_ASRC_DMABUF_SIZE (256 * 1024)
+
+ static inline void
+ imx_pcm_dma_params_init_data(struct imx_dma_data *dma_data,
+ int dma, bool shared)
+ {
+- dma_data->dma_request = dma;
++ dma_data->dma_request0 = dma;
+ dma_data->priority = DMA_PRIO_HIGH;
+ if (shared)
+ dma_data->peripheral_type = IMX_DMATYPE_SSI_SP;
+@@ -32,16 +36,12 @@
+ dma_data->peripheral_type = IMX_DMATYPE_SSI;
+ }
+
+-int snd_imx_pcm_mmap(struct snd_pcm_substream *substream,
+- struct vm_area_struct *vma);
+-int imx_pcm_new(struct snd_soc_pcm_runtime *rtd);
+-void imx_pcm_free(struct snd_pcm *pcm);
+-
+ #ifdef CONFIG_SND_SOC_IMX_PCM_DMA
+-int imx_pcm_dma_init(struct platform_device *pdev);
++int imx_pcm_dma_init(struct platform_device *pdev, unsigned int flags, size_t size);
+ void imx_pcm_dma_exit(struct platform_device *pdev);
+ #else
+-static inline int imx_pcm_dma_init(struct platform_device *pdev)
++static inline int imx_pcm_dma_init(struct platform_device *pdev,
++ unsigned int flags, size_t size)
+ {
+ return -ENODEV;
+ }
+@@ -53,11 +53,16 @@
+
+ #ifdef CONFIG_SND_SOC_IMX_PCM_FIQ
+ int imx_pcm_fiq_init(struct platform_device *pdev);
++void imx_pcm_fiq_exit(struct platform_device *pdev);
+ #else
+ static inline int imx_pcm_fiq_init(struct platform_device *pdev)
+ {
+ return -ENODEV;
+ }
++
++static inline void imx_pcm_fiq_exit(struct platform_device *pdev)
++{
++}
+ #endif
+
+ #endif /* _IMX_PCM_H */
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-sgtl5000.c linux-linaro-stable-mx6/sound/soc/fsl/imx-sgtl5000.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-sgtl5000.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-sgtl5000.c 2014-05-15 20:34:23.826199902 +0200
+@@ -149,7 +149,7 @@
+ data->dai.codec_dai_name = "sgtl5000";
+ data->dai.codec_of_node = codec_np;
+ data->dai.cpu_of_node = ssi_np;
+- data->dai.platform_name = "imx-pcm-audio";
++ data->dai.platform_of_node = ssi_np;
+ data->dai.init = &imx_sgtl5000_dai_init;
+ data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM;
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-si476x.c linux-linaro-stable-mx6/sound/soc/fsl/imx-si476x.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-si476x.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-si476x.c 2014-05-15 20:34:23.826199902 +0200
+@@ -0,0 +1,195 @@
++/*
++ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/of_i2c.h>
++#include <sound/soc.h>
++
++#include "imx-audmux.h"
++
++static int imx_audmux_config(int slave, int master)
++{
++ unsigned int ptcr, pdcr;
++ slave = slave - 1;
++ master = master - 1;
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN |
++ IMX_AUDMUX_V2_PTCR_TFSDIR |
++ IMX_AUDMUX_V2_PTCR_TFSEL(slave) |
++ IMX_AUDMUX_V2_PTCR_TCLKDIR |
++ IMX_AUDMUX_V2_PTCR_TCSEL(slave);
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(slave);
++ imx_audmux_v2_configure_port(master, ptcr, pdcr);
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN;
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(master);
++ imx_audmux_v2_configure_port(slave, ptcr, pdcr);
++
++ return 0;
++}
++
++static int imx_si476x_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ u32 channels = params_channels(params);
++ u32 rate = params_rate(params);
++ u32 bclk = rate * channels * 32;
++ int ret = 0;
++
++ /* set cpu DAI configuration */
++ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
++ | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
++ if (ret) {
++ dev_err(cpu_dai->dev, "failed to set dai fmt\n");
++ return ret;
++ }
++
++ ret = snd_soc_dai_set_tdm_slot(cpu_dai,
++ channels == 1 ? 0xfffffffe : 0xfffffffc,
++ channels == 1 ? 0xfffffffe : 0xfffffffc,
++ 2, 32);
++ if (ret) {
++ dev_err(cpu_dai->dev, "failed to set dai tdm slot\n");
++ return ret;
++ }
++
++ ret = snd_soc_dai_set_sysclk(cpu_dai, 0, bclk, SND_SOC_CLOCK_OUT);
++ if (ret)
++ dev_err(cpu_dai->dev, "failed to set sysclk\n");
++
++ return ret;
++}
++
++static struct snd_soc_ops imx_si476x_ops = {
++ .hw_params = imx_si476x_hw_params,
++};
++
++static struct snd_soc_dai_link imx_dai = {
++ .name = "imx-si476x",
++ .stream_name = "imx-si476x",
++ .codec_dai_name = "si476x-codec",
++ .codec_name = "si476x-codec.99",
++ .ops = &imx_si476x_ops,
++};
++
++static struct snd_soc_card snd_soc_card_imx_3stack = {
++ .name = "imx-audio-si476x",
++ .dai_link = &imx_dai,
++ .num_links = 1,
++};
++
++static int imx_si476x_probe(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = &snd_soc_card_imx_3stack;
++ struct device_node *ssi_np, *np = pdev->dev.of_node;
++ struct platform_device *ssi_pdev;
++ struct i2c_client *fm_dev;
++ struct device_node *fm_np;
++ int int_port, ext_port, ret;
++
++ ret = of_property_read_u32(np, "mux-int-port", &int_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
++ return ret;
++ }
++
++ imx_audmux_config(int_port, ext_port);
++
++ ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
++ if (!ssi_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ return -EINVAL;
++ }
++
++ ssi_pdev = of_find_device_by_node(ssi_np);
++ if (!ssi_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ fm_np = of_parse_phandle(pdev->dev.of_node, "fm-controller", 0);
++ if (!fm_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ fm_dev = of_find_i2c_device_by_node(fm_np);
++ if (!fm_dev || !fm_dev->driver) {
++ dev_err(&pdev->dev, "failed to find FM platform device\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ card->dev = &pdev->dev;
++ card->dai_link->cpu_dai_name = dev_name(&ssi_pdev->dev);
++ card->dai_link->platform_of_node = ssi_np;
++
++ platform_set_drvdata(pdev, card);
++
++ ret = snd_soc_register_card(card);
++ if (ret)
++ dev_err(&pdev->dev, "Failed to register card: %d\n", ret);
++
++end:
++ if (ssi_np)
++ of_node_put(ssi_np);
++ if (fm_np)
++ of_node_put(fm_np);
++
++ return ret;
++}
++
++static int imx_si476x_remove(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = &snd_soc_card_imx_3stack;
++
++ snd_soc_unregister_card(card);
++
++ return 0;
++}
++
++static const struct of_device_id imx_si476x_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-si476x", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_si476x_dt_ids);
++
++static struct platform_driver imx_si476x_driver = {
++ .driver = {
++ .name = "imx-tuner-si476x",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ .of_match_table = imx_si476x_dt_ids,
++ },
++ .probe = imx_si476x_probe,
++ .remove = imx_si476x_remove,
++};
++
++module_platform_driver(imx_si476x_driver);
++
++/* Module information */
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("ALSA SoC i.MX si476x");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-tuner-si476x");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-spdif.c linux-linaro-stable-mx6/sound/soc/fsl/imx-spdif.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-spdif.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-spdif.c 2014-05-15 20:34:23.854200105 +0200
+@@ -0,0 +1,151 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <sound/soc.h>
++
++struct imx_spdif_data {
++ struct snd_soc_dai_link dai[2];
++ struct snd_soc_card card;
++ struct platform_device *txdev;
++ struct platform_device *rxdev;
++};
++
++static int imx_spdif_audio_probe(struct platform_device *pdev)
++{
++ struct device_node *spdif_np, *np = pdev->dev.of_node;
++ struct imx_spdif_data *data;
++ int ret = 0, num_links = 0;
++
++ spdif_np = of_parse_phandle(np, "spdif-controller", 0);
++ if (!spdif_np) {
++ dev_err(&pdev->dev, "failed to find spdif-controller\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++ if (!data) {
++ dev_err(&pdev->dev, "failed to allocate memory\n");
++ ret = -ENOMEM;
++ goto end;
++ }
++
++ if (of_property_read_bool(np, "spdif-out")) {
++ data->dai[num_links].name = "S/PDIF TX";
++ data->dai[num_links].stream_name = "S/PDIF PCM Playback";
++ data->dai[num_links].codec_dai_name = "dit-hifi";
++ data->dai[num_links].codec_name = "spdif-dit";
++ data->dai[num_links].cpu_of_node = spdif_np;
++ data->dai[num_links].platform_of_node = spdif_np;
++ num_links++;
++
++ data->txdev = platform_device_register_simple("spdif-dit", -1, NULL, 0);
++ if (IS_ERR(data->txdev)) {
++ ret = PTR_ERR(data->txdev);
++ dev_err(&pdev->dev, "register dit failed: %d\n", ret);
++ goto end;
++ }
++ }
++
++ if (of_property_read_bool(np, "spdif-in")) {
++ data->dai[num_links].name = "S/PDIF RX";
++ data->dai[num_links].stream_name = "S/PDIF PCM Capture";
++ data->dai[num_links].codec_dai_name = "dir-hifi";
++ data->dai[num_links].codec_name = "spdif-dir";
++ data->dai[num_links].cpu_of_node = spdif_np;
++ data->dai[num_links].platform_of_node = spdif_np;
++ num_links++;
++
++ data->rxdev = platform_device_register_simple("spdif-dir", -1, NULL, 0);
++ if (IS_ERR(data->rxdev)) {
++ ret = PTR_ERR(data->rxdev);
++ dev_err(&pdev->dev, "register dir failed: %d\n", ret);
++ goto error_dit;
++ }
++ }
++
++ if (!num_links) {
++ dev_err(&pdev->dev, "no enabled S/PDIF DAI link\n");
++ goto error_dir;
++ }
++
++ data->card.dev = &pdev->dev;
++ data->card.num_links = num_links;
++ data->card.dai_link = data->dai;
++
++ ret = snd_soc_of_parse_card_name(&data->card, "model");
++ if (ret)
++ goto error_dir;
++
++ platform_set_drvdata(pdev, &data->card);
++ snd_soc_card_set_drvdata(&data->card, data);
++
++ ret = snd_soc_register_card(&data->card);
++ if (ret) {
++ dev_err(&pdev->dev, "snd_soc_register_card failed: %d\n", ret);
++ goto error_dir;
++ }
++
++ goto end;
++
++error_dir:
++ if (data->rxdev)
++ platform_device_unregister(data->rxdev);
++error_dit:
++ if (data->txdev)
++ platform_device_unregister(data->txdev);
++end:
++ if (spdif_np)
++ of_node_put(spdif_np);
++
++ return ret;
++}
++
++static int imx_spdif_audio_remove(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = platform_get_drvdata(pdev);
++ struct imx_spdif_data *data = snd_soc_card_get_drvdata(card);
++
++ snd_soc_unregister_card(card);
++
++ if (data->rxdev)
++ platform_device_unregister(data->rxdev);
++ if (data->txdev)
++ platform_device_unregister(data->txdev);
++
++ return 0;
++}
++
++static const struct of_device_id imx_spdif_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-spdif", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_spdif_dt_ids);
++
++static struct platform_driver imx_spdif_driver = {
++ .driver = {
++ .name = "imx-spdif",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ .of_match_table = imx_spdif_dt_ids,
++ },
++ .probe = imx_spdif_audio_probe,
++ .remove = imx_spdif_audio_remove,
++};
++
++module_platform_driver(imx_spdif_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Freescale i.MX S/PDIF machine driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:imx-spdif");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-ssi.c linux-linaro-stable-mx6/sound/soc/fsl/imx-ssi.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-ssi.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-ssi.c 2014-05-15 20:34:23.854200105 +0200
+@@ -590,41 +590,22 @@
+ goto failed_register;
+ }
+
+- ssi->soc_platform_pdev_fiq = platform_device_alloc("imx-fiq-pcm-audio", pdev->id);
+- if (!ssi->soc_platform_pdev_fiq) {
+- ret = -ENOMEM;
+- goto failed_pdev_fiq_alloc;
+- }
+-
+- platform_set_drvdata(ssi->soc_platform_pdev_fiq, ssi);
+- ret = platform_device_add(ssi->soc_platform_pdev_fiq);
+- if (ret) {
+- dev_err(&pdev->dev, "failed to add platform device\n");
+- goto failed_pdev_fiq_add;
+- }
+-
+- ssi->soc_platform_pdev = platform_device_alloc("imx-pcm-audio", pdev->id);
+- if (!ssi->soc_platform_pdev) {
+- ret = -ENOMEM;
+- goto failed_pdev_alloc;
+- }
+-
+- platform_set_drvdata(ssi->soc_platform_pdev, ssi);
+- ret = platform_device_add(ssi->soc_platform_pdev);
+- if (ret) {
+- dev_err(&pdev->dev, "failed to add platform device\n");
+- goto failed_pdev_add;
+- }
++ ret = imx_pcm_fiq_init(pdev);
++ if (ret)
++ goto failed_pcm_fiq;
++
++ ret = imx_pcm_dma_init(pdev, SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
++ SND_DMAENGINE_PCM_FLAG_NO_DT |
++ SND_DMAENGINE_PCM_FLAG_COMPAT,
++ IMX_SSI_DMABUF_SIZE);
++ if (ret)
++ goto failed_pcm_dma;
+
+ return 0;
+
+-failed_pdev_add:
+- platform_device_put(ssi->soc_platform_pdev);
+-failed_pdev_alloc:
+- platform_device_del(ssi->soc_platform_pdev_fiq);
+-failed_pdev_fiq_add:
+- platform_device_put(ssi->soc_platform_pdev_fiq);
+-failed_pdev_fiq_alloc:
++failed_pcm_dma:
++ imx_pcm_fiq_exit(pdev);
++failed_pcm_fiq:
+ snd_soc_unregister_component(&pdev->dev);
+ failed_register:
+ release_mem_region(res->start, resource_size(res));
+@@ -639,8 +620,8 @@
+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct imx_ssi *ssi = platform_get_drvdata(pdev);
+
+- platform_device_unregister(ssi->soc_platform_pdev);
+- platform_device_unregister(ssi->soc_platform_pdev_fiq);
++ imx_pcm_dma_exit(pdev);
++ imx_pcm_fiq_exit(pdev);
+
+ snd_soc_unregister_component(&pdev->dev);
+
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-ssi.h linux-linaro-stable-mx6/sound/soc/fsl/imx-ssi.h
+--- linux-3.10.30.orig/sound/soc/fsl/imx-ssi.h 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-ssi.h 2014-05-15 20:34:23.854200105 +0200
+@@ -211,9 +211,6 @@
+ struct imx_dma_data filter_data_rx;
+
+ int enabled;
+-
+- struct platform_device *soc_platform_pdev;
+- struct platform_device *soc_platform_pdev_fiq;
+ };
+
+ #endif /* _IMX_SSI_H */
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/imx-wm8962.c linux-linaro-stable-mx6/sound/soc/fsl/imx-wm8962.c
+--- linux-3.10.30.orig/sound/soc/fsl/imx-wm8962.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/imx-wm8962.c 2014-05-15 20:34:23.854200105 +0200
+@@ -0,0 +1,575 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * Based on imx-sgtl5000.c
++ * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/of_i2c.h>
++#include <linux/of_gpio.h>
++#include <linux/slab.h>
++#include <linux/gpio.h>
++#include <linux/clk.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++#include <sound/pcm_params.h>
++#include <sound/soc-dapm.h>
++#include <linux/pinctrl/consumer.h>
++
++#include "../codecs/wm8962.h"
++#include "imx-audmux.h"
++
++#define DAI_NAME_SIZE 32
++
++struct imx_wm8962_data {
++ struct snd_soc_dai_link dai;
++ struct snd_soc_card card;
++ char codec_dai_name[DAI_NAME_SIZE];
++ char platform_name[DAI_NAME_SIZE];
++ unsigned int clk_frequency;
++};
++
++struct imx_priv {
++ int hp_gpio;
++ int hp_active_low;
++ int mic_gpio;
++ int mic_active_low;
++ bool amic_mono;
++ bool dmic_mono;
++ struct snd_soc_codec *codec;
++ struct platform_device *pdev;
++ struct snd_pcm_substream *first_stream;
++ struct snd_pcm_substream *second_stream;
++};
++static struct imx_priv card_priv;
++
++static struct snd_soc_jack imx_hp_jack;
++static struct snd_soc_jack_pin imx_hp_jack_pins[] = {
++ {
++ .pin = "Headphone Jack",
++ .mask = SND_JACK_HEADPHONE,
++ },
++};
++static struct snd_soc_jack_gpio imx_hp_jack_gpio = {
++ .name = "headphone detect",
++ .report = SND_JACK_HEADPHONE,
++ .debounce_time = 250,
++ .invert = 0,
++};
++
++static struct snd_soc_jack imx_mic_jack;
++static struct snd_soc_jack_pin imx_mic_jack_pins[] = {
++ {
++ .pin = "AMIC",
++ .mask = SND_JACK_MICROPHONE,
++ },
++};
++static struct snd_soc_jack_gpio imx_mic_jack_gpio = {
++ .name = "microphone detect",
++ .report = SND_JACK_MICROPHONE,
++ .debounce_time = 250,
++ .invert = 0,
++};
++
++static int hpjack_status_check(void)
++{
++ struct imx_priv *priv = &card_priv;
++ struct platform_device *pdev = priv->pdev;
++ char *envp[3], *buf;
++ int hp_status, ret;
++
++ if (!gpio_is_valid(priv->hp_gpio))
++ return 0;
++
++ hp_status = gpio_get_value(priv->hp_gpio) ? 1 : 0;
++
++ buf = kmalloc(32, GFP_ATOMIC);
++ if (!buf) {
++ dev_err(&pdev->dev, "%s kmalloc failed\n", __func__);
++ return -ENOMEM;
++ }
++
++ if (hp_status != priv->hp_active_low) {
++ snprintf(buf, 32, "STATE=%d", 2);
++ snd_soc_dapm_disable_pin(&priv->codec->dapm, "Ext Spk");
++ ret = imx_hp_jack_gpio.report;
++ } else {
++ snprintf(buf, 32, "STATE=%d", 0);
++ snd_soc_dapm_enable_pin(&priv->codec->dapm, "Ext Spk");
++ ret = 0;
++ }
++
++ envp[0] = "NAME=headphone";
++ envp[1] = buf;
++ envp[2] = NULL;
++ kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, envp);
++ kfree(buf);
++
++ return ret;
++}
++
++static int micjack_status_check(void)
++{
++ struct imx_priv *priv = &card_priv;
++ struct platform_device *pdev = priv->pdev;
++ char *envp[3], *buf;
++ int mic_status, ret;
++
++ if (!gpio_is_valid(priv->mic_gpio))
++ return 0;
++
++ mic_status = gpio_get_value(priv->mic_gpio) ? 1 : 0;
++
++ if ((mic_status != priv->mic_active_low && priv->amic_mono)
++ || (mic_status == priv->mic_active_low && priv->dmic_mono))
++ snd_soc_update_bits(priv->codec, WM8962_THREED1,
++ WM8962_ADC_MONOMIX_MASK, WM8962_ADC_MONOMIX);
++ else
++ snd_soc_update_bits(priv->codec, WM8962_THREED1,
++ WM8962_ADC_MONOMIX_MASK, 0);
++
++ buf = kmalloc(32, GFP_ATOMIC);
++ if (!buf) {
++ dev_err(&pdev->dev, "%s kmalloc failed\n", __func__);
++ return -ENOMEM;
++ }
++
++ if (mic_status != priv->mic_active_low) {
++ snprintf(buf, 32, "STATE=%d", 2);
++ snd_soc_dapm_disable_pin(&priv->codec->dapm, "DMIC");
++ ret = imx_mic_jack_gpio.report;
++ } else {
++ snprintf(buf, 32, "STATE=%d", 0);
++ snd_soc_dapm_enable_pin(&priv->codec->dapm, "DMIC");
++ ret = 0;
++ }
++
++ envp[0] = "NAME=microphone";
++ envp[1] = buf;
++ envp[2] = NULL;
++ kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, envp);
++ kfree(buf);
++
++ return ret;
++}
++
++
++static const struct snd_soc_dapm_widget imx_wm8962_dapm_widgets[] = {
++ SND_SOC_DAPM_HP("Headphone Jack", NULL),
++ SND_SOC_DAPM_SPK("Ext Spk", NULL),
++ SND_SOC_DAPM_MIC("AMIC", NULL),
++ SND_SOC_DAPM_MIC("DMIC", NULL),
++};
++
++static int imx_hifi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct imx_priv *priv = &card_priv;
++ struct device *dev = &priv->pdev->dev;
++ struct snd_soc_card *card = codec_dai->codec->card;
++ struct imx_wm8962_data *data = snd_soc_card_get_drvdata(card);
++ unsigned int sample_rate = params_rate(params);
++ snd_pcm_format_t sample_format = params_format(params);
++ u32 dai_format, pll_out;
++ int ret = 0;
++
++ if (!priv->first_stream) {
++ priv->first_stream = substream;
++ } else {
++ priv->second_stream = substream;
++
++ /* We suppose the two substream are using same params */
++ return 0;
++ }
++
++ dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ /* set codec DAI configuration */
++ ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
++ if (ret) {
++ dev_err(dev, "failed to set codec dai fmt: %d\n", ret);
++ return ret;
++ }
++
++ if (sample_format == SNDRV_PCM_FORMAT_S24_LE)
++ pll_out = sample_rate * 192;
++ else
++ pll_out = sample_rate * 256;
++
++ ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL, WM8962_FLL_MCLK,
++ data->clk_frequency, pll_out);
++ if (ret) {
++ dev_err(dev, "failed to start FLL: %d\n", ret);
++ return ret;
++ }
++
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_FLL,
++ pll_out, SND_SOC_CLOCK_IN);
++ if (ret) {
++ dev_err(dev, "failed to set SYSCLK: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int imx_hifi_hw_free(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct imx_priv *priv = &card_priv;
++ struct device *dev = &priv->pdev->dev;
++ int ret;
++
++ /* We don't need to handle anything if there's no substream running */
++ if (!priv->first_stream)
++ return 0;
++
++ if (priv->first_stream == substream)
++ priv->first_stream = priv->second_stream;
++ priv->second_stream = NULL;
++
++ if (!priv->first_stream) {
++ /*
++ * Continuously setting FLL would cause playback distortion.
++ * We can fix it just by mute codec after playback.
++ */
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ snd_soc_dai_digital_mute(codec_dai, 1, substream->stream);
++
++ /*
++ * WM8962 doesn't allow us to continuously setting FLL,
++ * So we set MCLK as sysclk once, which'd remove the limitation.
++ */
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK,
++ 0, SND_SOC_CLOCK_IN);
++ if (ret < 0) {
++ dev_err(dev, "failed to switch away from FLL: %d\n", ret);
++ return ret;
++ }
++
++ /* Disable FLL and let codec do pm_runtime_put() */
++ ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL,
++ WM8962_FLL_MCLK, 0, 0);
++ if (ret < 0) {
++ dev_err(dev, "failed to stop FLL: %d\n", ret);
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static struct snd_soc_ops imx_hifi_ops = {
++ .hw_params = imx_hifi_hw_params,
++ .hw_free = imx_hifi_hw_free,
++};
++
++static int imx_wm8962_gpio_init(struct snd_soc_pcm_runtime *rtd)
++{
++ struct snd_soc_codec *codec = rtd->codec;
++ struct imx_priv *priv = &card_priv;
++
++ priv->codec = codec;
++
++ if (gpio_is_valid(priv->hp_gpio)) {
++ imx_hp_jack_gpio.gpio = priv->hp_gpio;
++ imx_hp_jack_gpio.jack_status_check = hpjack_status_check;
++
++ snd_soc_jack_new(codec, "Headphone Jack", SND_JACK_HEADPHONE, &imx_hp_jack);
++ snd_soc_jack_add_pins(&imx_hp_jack,
++ ARRAY_SIZE(imx_hp_jack_pins), imx_hp_jack_pins);
++ snd_soc_jack_add_gpios(&imx_hp_jack, 1, &imx_hp_jack_gpio);
++ }
++
++ if (gpio_is_valid(priv->mic_gpio)) {
++ imx_mic_jack_gpio.gpio = priv->mic_gpio;
++ imx_mic_jack_gpio.jack_status_check = micjack_status_check;
++
++ snd_soc_jack_new(codec, "AMIC", SND_JACK_MICROPHONE, &imx_mic_jack);
++ snd_soc_jack_add_pins(&imx_mic_jack,
++ ARRAY_SIZE(imx_mic_jack_pins), imx_mic_jack_pins);
++ snd_soc_jack_add_gpios(&imx_mic_jack, 1, &imx_mic_jack_gpio);
++ } else if (priv->amic_mono || priv->dmic_mono) {
++ /*
++ * Permanent set monomix bit if only one microphone
++ * is present on the board while it needs monomix.
++ */
++ snd_soc_update_bits(priv->codec, WM8962_THREED1,
++ WM8962_ADC_MONOMIX_MASK, WM8962_ADC_MONOMIX);
++ }
++
++ return 0;
++}
++
++static ssize_t show_headphone(struct device_driver *dev, char *buf)
++{
++ struct imx_priv *priv = &card_priv;
++ int hp_status;
++
++ if (!gpio_is_valid(priv->hp_gpio)) {
++ strcpy(buf, "no detect gpio connected\n");
++ return strlen(buf);
++ }
++
++ /* Check if headphone is plugged in */
++ hp_status = gpio_get_value(priv->hp_gpio) ? 1 : 0;
++
++ if (hp_status != priv->hp_active_low)
++ strcpy(buf, "headphone\n");
++ else
++ strcpy(buf, "speaker\n");
++
++ return strlen(buf);
++}
++
++static DRIVER_ATTR(headphone, S_IRUGO | S_IWUSR, show_headphone, NULL);
++
++static ssize_t show_mic(struct device_driver *dev, char *buf)
++{
++ struct imx_priv *priv = &card_priv;
++ int mic_status;
++
++ if (!gpio_is_valid(priv->mic_gpio)) {
++ strcpy(buf, "no detect gpio connected\n");
++ return strlen(buf);
++ }
++
++ /* Check if analog microphone is plugged in */
++ mic_status = gpio_get_value(priv->mic_gpio) ? 1 : 0;
++
++ if (mic_status != priv->mic_active_low)
++ strcpy(buf, "amic\n");
++ else
++ strcpy(buf, "dmic\n");
++
++ return strlen(buf);
++}
++
++static DRIVER_ATTR(microphone, S_IRUGO | S_IWUSR, show_mic, NULL);
++
++static int imx_wm8962_late_probe(struct snd_soc_card *card)
++{
++ struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
++ struct imx_priv *priv = &card_priv;
++ struct imx_wm8962_data *data = snd_soc_card_get_drvdata(card);
++ struct device *dev = &priv->pdev->dev;
++ int ret;
++
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK,
++ data->clk_frequency, SND_SOC_CLOCK_IN);
++ if (ret < 0)
++ dev_err(dev, "failed to set sysclk in %s\n", __func__);
++
++ return ret;
++}
++
++static int imx_wm8962_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct device_node *ssi_np, *codec_np;
++ struct platform_device *ssi_pdev;
++ struct imx_priv *priv = &card_priv;
++ struct i2c_client *codec_dev;
++ struct imx_wm8962_data *data;
++ struct clk *codec_clk = NULL;
++ int int_port, ext_port;
++ int ret;
++
++ priv->pdev = pdev;
++
++ ret = of_property_read_u32(np, "mux-int-port", &int_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
++ return ret;
++ }
++
++ /*
++ * The port numbering in the hardware manual starts at 1, while
++ * the audmux API expects it starts at 0.
++ */
++ int_port--;
++ ext_port--;
++ ret = imx_audmux_v2_configure_port(int_port,
++ IMX_AUDMUX_V2_PTCR_SYN |
++ IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
++ IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
++ IMX_AUDMUX_V2_PTCR_TFSDIR |
++ IMX_AUDMUX_V2_PTCR_TCLKDIR,
++ IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
++ if (ret) {
++ dev_err(&pdev->dev, "audmux internal port setup failed\n");
++ return ret;
++ }
++ imx_audmux_v2_configure_port(ext_port,
++ IMX_AUDMUX_V2_PTCR_SYN,
++ IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
++ if (ret) {
++ dev_err(&pdev->dev, "audmux external port setup failed\n");
++ return ret;
++ }
++
++ ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
++ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
++ if (!ssi_np || !codec_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ ssi_pdev = of_find_device_by_node(ssi_np);
++ if (!ssi_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++ codec_dev = of_find_i2c_device_by_node(codec_np);
++ if (!codec_dev || !codec_dev->driver) {
++ dev_err(&pdev->dev, "failed to find codec platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ priv->first_stream = NULL;
++ priv->second_stream = NULL;
++
++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++ if (!data) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ codec_clk = devm_clk_get(&codec_dev->dev, NULL);
++ if (IS_ERR(codec_clk)) {
++ ret = PTR_ERR(codec_clk);
++ dev_err(&codec_dev->dev, "failed to get codec clk: %d\n", ret);
++ goto fail;
++ }
++
++ data->clk_frequency = clk_get_rate(codec_clk);
++
++ priv->amic_mono = of_property_read_bool(codec_np, "amic-mono");
++ priv->dmic_mono = of_property_read_bool(codec_np, "dmic-mono");
++
++ priv->hp_gpio = of_get_named_gpio_flags(np, "hp-det-gpios", 0,
++ (enum of_gpio_flags *)&priv->hp_active_low);
++ priv->mic_gpio = of_get_named_gpio_flags(np, "mic-det-gpios", 0,
++ (enum of_gpio_flags *)&priv->mic_active_low);
++
++ data->dai.name = "HiFi";
++ data->dai.stream_name = "HiFi";
++ data->dai.codec_dai_name = "wm8962";
++ data->dai.codec_of_node = codec_np;
++ data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
++ data->dai.platform_of_node = ssi_np;
++ data->dai.ops = &imx_hifi_ops;
++ data->dai.init = &imx_wm8962_gpio_init;
++ data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ data->card.dev = &pdev->dev;
++ ret = snd_soc_of_parse_card_name(&data->card, "model");
++ if (ret)
++ goto fail;
++ ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
++ if (ret)
++ goto fail;
++ data->card.num_links = 1;
++ data->card.dai_link = &data->dai;
++ data->card.dapm_widgets = imx_wm8962_dapm_widgets;
++ data->card.num_dapm_widgets = ARRAY_SIZE(imx_wm8962_dapm_widgets);
++
++ data->card.late_probe = imx_wm8962_late_probe;
++
++ platform_set_drvdata(pdev, &data->card);
++ snd_soc_card_set_drvdata(&data->card, data);
++
++ ret = snd_soc_register_card(&data->card);
++ if (ret) {
++ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
++ goto fail;
++ }
++
++ if (gpio_is_valid(priv->hp_gpio)) {
++ ret = driver_create_file(pdev->dev.driver, &driver_attr_headphone);
++ if (ret) {
++ dev_err(&pdev->dev, "create hp attr failed (%d)\n", ret);
++ goto fail_hp;
++ }
++ }
++
++ if (gpio_is_valid(priv->mic_gpio)) {
++ ret = driver_create_file(pdev->dev.driver, &driver_attr_microphone);
++ if (ret) {
++ dev_err(&pdev->dev, "create mic attr failed (%d)\n", ret);
++ goto fail_mic;
++ }
++ }
++
++ goto fail;
++
++fail_mic:
++ driver_remove_file(pdev->dev.driver, &driver_attr_headphone);
++fail_hp:
++ snd_soc_unregister_card(&data->card);
++fail:
++ if (ssi_np)
++ of_node_put(ssi_np);
++ if (codec_np)
++ of_node_put(codec_np);
++
++ return ret;
++}
++
++static int imx_wm8962_remove(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++ driver_remove_file(pdev->dev.driver, &driver_attr_microphone);
++ driver_remove_file(pdev->dev.driver, &driver_attr_headphone);
++
++ snd_soc_unregister_card(card);
++
++ return 0;
++}
++
++static const struct of_device_id imx_wm8962_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-wm8962", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_wm8962_dt_ids);
++
++static struct platform_driver imx_wm8962_driver = {
++ .driver = {
++ .name = "imx-wm8962",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ .of_match_table = imx_wm8962_dt_ids,
++ },
++ .probe = imx_wm8962_probe,
++ .remove = imx_wm8962_remove,
++};
++module_platform_driver(imx_wm8962_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Freescale i.MX WM8962 ASoC machine driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:imx-wm8962");
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/Kconfig linux-linaro-stable-mx6/sound/soc/fsl/Kconfig
+--- linux-3.10.30.orig/sound/soc/fsl/Kconfig 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/Kconfig 2014-05-15 20:34:23.790199644 +0200
+@@ -1,6 +1,18 @@
+ config SND_SOC_FSL_SSI
+ tristate
+
++config SND_SOC_FSL_ASRC
++ tristate
++
++config SND_SOC_FSL_ESAI
++ tristate
++
++config SND_SOC_FSL_SPDIF
++ tristate
++
++config SND_SOC_FSL_HDMI
++ tristate
++
+ config SND_SOC_FSL_UTILS
+ tristate
+
+@@ -108,18 +120,18 @@
+ config SND_SOC_IMX_SSI
+ tristate
+
+-config SND_SOC_IMX_PCM
+- tristate
+-
+ config SND_SOC_IMX_PCM_FIQ
+ bool
+ select FIQ
+- select SND_SOC_IMX_PCM
+
+ config SND_SOC_IMX_PCM_DMA
+ bool
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+- select SND_SOC_IMX_PCM
++
++config SND_SOC_IMX_HDMI_DMA
++ bool
++ select SND_SOC_GENERIC_DMAENGINE_PCM
++ select SND_SOC_IMX_PCM_DMA
+
+ config SND_SOC_IMX_AUDMUX
+ tristate
+@@ -173,6 +185,30 @@
+ Enable I2S based access to the TLV320AIC23B codec attached
+ to the SSI interface
+
++config SND_SOC_IMX_CS42888
++ tristate "SoC Audio support for i.MX boards with cs42888"
++ depends on OF && I2C
++ select SND_SOC_CS42888
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_FSL_ESAI
++ select SND_SOC_FSL_UTILS
++ help
++ SoC Audio support for i.MX boards with cs42888
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ a cs42888 codec.
++
++config SND_SOC_IMX_WM8962
++ tristate "SoC Audio support for i.MX boards with wm8962"
++ depends on OF && I2C
++ select SND_SOC_WM8962
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SSI
++ select SND_SOC_FSL_UTILS
++ help
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ a wm8962 codec.
++
+ config SND_SOC_IMX_SGTL5000
+ tristate "SoC Audio support for i.MX boards with sgtl5000"
+ depends on OF && I2C
+@@ -185,6 +221,17 @@
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a sgtl5000 codec.
+
++config SND_SOC_IMX_SPDIF
++ tristate "SoC Audio support for i.MX boards with S/PDIF"
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_FSL_SPDIF
++ select SND_SOC_SPDIF
++ select REGMAP_MMIO
++ help
++ SoC Audio support for i.MX boards with S/PDIF
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ a S/DPDIF.
++
+ config SND_SOC_IMX_MC13783
+ tristate "SoC Audio support for I.MX boards with mc13783"
+ depends on MFD_MC13783
+@@ -193,4 +240,27 @@
+ select SND_SOC_MC13783
+ select SND_SOC_IMX_PCM_DMA
+
++config SND_SOC_IMX_HDMI
++ tristate "SoC Audio support for i.MX boards with HDMI port"
++ depends on MFD_MXC_HDMI
++ select SND_SOC_IMX_HDMI_DMA
++ select SND_SOC_FSL_HDMI
++ select SND_SOC_OMAP_HDMI_CODEC
++ help
++ SoC Audio support for i.MX boards with HDMI audio
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ IMX HDMI.
++
++config SND_SOC_IMX_SI476X
++ tristate "SoC Audio support for i.MX boards with si476x"
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SSI
++ select SND_SOC_FSL_UTILS
++ select SND_SOC_SI476X
++ help
++ SoC Audio support for i.MX boards with SI476x
++ Say Y if you want to add support for Soc audio for the AMFM Tuner chip
++ SI476x module.
++
+ endif # SND_IMX_SOC
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/Makefile linux-linaro-stable-mx6/sound/soc/fsl/Makefile
+--- linux-3.10.30.orig/sound/soc/fsl/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/Makefile 2014-05-15 20:34:23.790199644 +0200
+@@ -10,11 +10,21 @@
+ snd-soc-p1022-rdk-objs := p1022_rdk.o
+ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
+
+-# Freescale PowerPC SSI/DMA Platform Support
++# Freescale PowerPC SSI/DMA/ASRC/ESAI Platform Support
+ snd-soc-fsl-ssi-objs := fsl_ssi.o
++snd-soc-fsl-asrc-pcm-objs := fsl_asrc_pcm.o
++snd-soc-fsl-asrc-objs := fsl_asrc.o
++snd-soc-fsl-esai-objs := fsl_esai.o
++snd-soc-fsl-spdif-objs := fsl_spdif.o
++snd-soc-fsl-hdmi-objs := fsl_hdmi.o
+ snd-soc-fsl-utils-objs := fsl_utils.o
+ snd-soc-fsl-dma-objs := fsl_dma.o
+ obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
++obj-$(CONFIG_SND_SOC_FSL_ASRC) += snd-soc-fsl-asrc-pcm.o
++obj-$(CONFIG_SND_SOC_FSL_ASRC) += snd-soc-fsl-asrc.o
++obj-$(CONFIG_SND_SOC_FSL_ESAI) += snd-soc-fsl-esai.o
++obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
++obj-$(CONFIG_SND_SOC_FSL_HDMI) += snd-soc-fsl-hdmi.o
+ obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
+ obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
+
+@@ -30,30 +40,34 @@
+ # i.MX Platform Support
+ snd-soc-imx-ssi-objs := imx-ssi.o
+ snd-soc-imx-audmux-objs := imx-audmux.o
+-snd-soc-imx-pcm-objs := imx-pcm.o
+-ifneq ($(CONFIG_SND_SOC_IMX_PCM_FIQ),)
+- snd-soc-imx-pcm-objs += imx-pcm-fiq.o
+-endif
+-ifneq ($(CONFIG_SND_SOC_IMX_PCM_DMA),)
+- snd-soc-imx-pcm-objs += imx-pcm-dma.o
+-endif
+-
+ obj-$(CONFIG_SND_SOC_IMX_SSI) += snd-soc-imx-ssi.o
+ obj-$(CONFIG_SND_SOC_IMX_AUDMUX) += snd-soc-imx-audmux.o
+
+-obj-$(CONFIG_SND_SOC_IMX_PCM) += snd-soc-imx-pcm.o
++obj-$(CONFIG_SND_SOC_IMX_PCM_FIQ) += imx-pcm-fiq.o
++obj-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o
++obj-$(CONFIG_SND_SOC_IMX_HDMI_DMA) += imx-hdmi-dma.o
+
+ # i.MX Machine Support
+ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+ snd-soc-phycore-ac97-objs := phycore-ac97.o
+ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
+ snd-soc-wm1133-ev1-objs := wm1133-ev1.o
++snd-soc-imx-cs42888-objs := imx-cs42888.o
+ snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
++snd-soc-imx-wm8962-objs := imx-wm8962.o
++snd-soc-imx-spdif-objs := imx-spdif.o
+ snd-soc-imx-mc13783-objs := imx-mc13783.o
++snd-soc-imx-hdmi-objs := imx-hdmi.o
++snd-soc-imx-si476x-objs := imx-si476x.o
+
+ obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+ obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+ obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
+ obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
++obj-$(CONFIG_SND_SOC_IMX_CS42888) += snd-soc-imx-cs42888.o
+ obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
++obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o
++obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
+ obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
++obj-$(CONFIG_SND_SOC_IMX_HDMI) += snd-soc-imx-hdmi.o
++obj-$(CONFIG_SND_SOC_IMX_SI476X) += snd-soc-imx-si476x.o
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/mx27vis-aic32x4.c linux-linaro-stable-mx6/sound/soc/fsl/mx27vis-aic32x4.c
+--- linux-3.10.30.orig/sound/soc/fsl/mx27vis-aic32x4.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/mx27vis-aic32x4.c 2014-05-15 20:34:23.858200133 +0200
+@@ -161,7 +161,7 @@
+ .name = "tlv320aic32x4",
+ .stream_name = "TLV320AIC32X4",
+ .codec_dai_name = "tlv320aic32x4-hifi",
+- .platform_name = "imx-pcm-audio.0",
++ .platform_name = "imx-ssi.0",
+ .codec_name = "tlv320aic32x4.0-0018",
+ .cpu_dai_name = "imx-ssi.0",
+ .ops = &mx27vis_aic32x4_snd_ops,
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/phycore-ac97.c linux-linaro-stable-mx6/sound/soc/fsl/phycore-ac97.c
+--- linux-3.10.30.orig/sound/soc/fsl/phycore-ac97.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/phycore-ac97.c 2014-05-15 20:34:23.858200133 +0200
+@@ -33,7 +33,7 @@
+ .codec_dai_name = "wm9712-hifi",
+ .codec_name = "wm9712-codec",
+ .cpu_dai_name = "imx-ssi.0",
+- .platform_name = "imx-fiq-pcm-audio.0",
++ .platform_name = "imx-ssi.0",
+ .ops = &imx_phycore_hifi_ops,
+ },
+ };
+diff -Nur linux-3.10.30.orig/sound/soc/fsl/wm1133-ev1.c linux-linaro-stable-mx6/sound/soc/fsl/wm1133-ev1.c
+--- linux-3.10.30.orig/sound/soc/fsl/wm1133-ev1.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/fsl/wm1133-ev1.c 2014-05-15 20:34:23.858200133 +0200
+@@ -245,7 +245,7 @@
+ .stream_name = "Audio",
+ .cpu_dai_name = "imx-ssi.0",
+ .codec_dai_name = "wm8350-hifi",
+- .platform_name = "imx-fiq-pcm-audio.0",
++ .platform_name = "imx-ssi.0",
+ .codec_name = "wm8350-codec.0-0x1a",
+ .init = wm1133_ev1_init,
+ .ops = &wm1133_ev1_ops,
+diff -Nur linux-3.10.30.orig/sound/soc/soc-compress.c linux-linaro-stable-mx6/sound/soc/soc-compress.c
+--- linux-3.10.30.orig/sound/soc/soc-compress.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/soc-compress.c 2014-05-15 20:34:24.142202177 +0200
+@@ -149,8 +149,9 @@
+ SND_SOC_DAPM_STREAM_STOP);
+ } else {
+ rtd->pop_wait = 1;
+- schedule_delayed_work(&rtd->delayed_work,
+- msecs_to_jiffies(rtd->pmdown_time));
++ queue_delayed_work(system_power_efficient_wq,
++ &rtd->delayed_work,
++ msecs_to_jiffies(rtd->pmdown_time));
+ }
+ } else {
+ /* capture streams can be powered down now */
+diff -Nur linux-3.10.30.orig/sound/soc/soc-generic-dmaengine-pcm.c linux-linaro-stable-mx6/sound/soc/soc-generic-dmaengine-pcm.c
+--- linux-3.10.30.orig/sound/soc/soc-generic-dmaengine-pcm.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/soc-generic-dmaengine-pcm.c 2014-05-15 20:34:24.142202177 +0200
+@@ -163,7 +163,7 @@
+ }
+
+ ret = snd_pcm_lib_preallocate_pages(substream,
+- SNDRV_DMA_TYPE_DEV,
++ SNDRV_DMA_TYPE_DEV_IRAM,
+ dmaengine_dma_dev(pcm, substream),
+ config->prealloc_buffer_size,
+ config->pcm_hardware->buffer_bytes_max);
+diff -Nur linux-3.10.30.orig/sound/soc/soc-jack.c linux-linaro-stable-mx6/sound/soc/soc-jack.c
+--- linux-3.10.30.orig/sound/soc/soc-jack.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/soc-jack.c 2014-05-15 20:34:24.142202177 +0200
+@@ -263,7 +263,7 @@
+ if (device_may_wakeup(dev))
+ pm_wakeup_event(dev, gpio->debounce_time + 50);
+
+- schedule_delayed_work(&gpio->work,
++ queue_delayed_work(system_power_efficient_wq, &gpio->work,
+ msecs_to_jiffies(gpio->debounce_time));
+
+ return IRQ_HANDLED;
+diff -Nur linux-3.10.30.orig/sound/soc/soc-pcm.c linux-linaro-stable-mx6/sound/soc/soc-pcm.c
+--- linux-3.10.30.orig/sound/soc/soc-pcm.c 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/sound/soc/soc-pcm.c 2014-05-15 20:34:24.142202177 +0200
+@@ -408,8 +408,9 @@
+ } else {
+ /* start delayed pop wq here for playback streams */
+ rtd->pop_wait = 1;
+- schedule_delayed_work(&rtd->delayed_work,
+- msecs_to_jiffies(rtd->pmdown_time));
++ queue_delayed_work(system_power_efficient_wq,
++ &rtd->delayed_work,
++ msecs_to_jiffies(rtd->pmdown_time));
+ }
+ } else {
+ /* capture streams can be powered down now */
+@@ -817,7 +818,7 @@
+ }
+ }
+
+- dev_err(card->dev, "ASoC: can't get %s BE for %s\n",
++ dev_dbg(card->dev, "ASoC: can't get %s BE for %s\n",
+ stream ? "capture" : "playback", widget->name);
+ return NULL;
+ }
+@@ -939,7 +940,7 @@
+ /* is there a valid BE rtd for this widget */
+ be = dpcm_get_be(card, list->widgets[i], stream);
+ if (!be) {
+- dev_err(fe->dev, "ASoC: no BE found for %s\n",
++ dev_dbg(fe->dev, "ASoC: no BE found for %s\n",
+ list->widgets[i]->name);
+ continue;
+ }
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Android.mk linux-linaro-stable-mx6/tools/gator/daemon/Android.mk
+--- linux-3.10.30.orig/tools/gator/daemon/Android.mk 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Android.mk 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,52 @@
++LOCAL_PATH := $(call my-dir)
++include $(CLEAR_VARS)
++
++XML_H := $(shell cd $(LOCAL_PATH) && make events_xml.h configuration_xml.h)
++
++LOCAL_CFLAGS += -Wall -O3 -mthumb-interwork -fno-exceptions -DETCDIR=\"/etc\" -Ilibsensors
++
++LOCAL_SRC_FILES := \
++ Buffer.cpp \
++ CapturedXML.cpp \
++ Child.cpp \
++ Collector.cpp \
++ ConfigurationXML.cpp \
++ Driver.cpp \
++ EventsXML.cpp \
++ Fifo.cpp \
++ Hwmon.cpp \
++ KMod.cpp \
++ LocalCapture.cpp \
++ Logging.cpp \
++ main.cpp \
++ OlySocket.cpp \
++ OlyUtility.cpp \
++ Sender.cpp \
++ SessionData.cpp \
++ SessionXML.cpp \
++ StreamlineSetup.cpp \
++ libsensors/access.c \
++ libsensors/conf-lex.c \
++ libsensors/conf-parse.c \
++ libsensors/data.c \
++ libsensors/error.c \
++ libsensors/general.c \
++ libsensors/init.c \
++ libsensors/sysfs.c \
++ mxml/mxml-attr.c \
++ mxml/mxml-entity.c \
++ mxml/mxml-file.c \
++ mxml/mxml-get.c \
++ mxml/mxml-index.c \
++ mxml/mxml-node.c \
++ mxml/mxml-private.c \
++ mxml/mxml-search.c \
++ mxml/mxml-set.c \
++ mxml/mxml-string.c
++
++LOCAL_C_INCLUDES := $(LOCAL_PATH)
++
++LOCAL_MODULE := gatord
++LOCAL_MODULE_TAGS := optional
++
++include $(BUILD_EXECUTABLE)
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Buffer.cpp linux-linaro-stable-mx6/tools/gator/daemon/Buffer.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/Buffer.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Buffer.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,228 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "Buffer.h"
++
++#include "Logging.h"
++#include "Sender.h"
++#include "SessionData.h"
++
++#define mask (size - 1)
++
++Buffer::Buffer (const int32_t core, const int32_t buftype, const int size, sem_t *const readerSem) : core(core), buftype(buftype), size(size), readPos(0), writePos(0), commitPos(0), available(true), done(false), buf(new char[size]), commitTime(gSessionData->mLiveRate), readerSem(readerSem) {
++ if ((size & mask) != 0) {
++ logg->logError(__FILE__, __LINE__, "Buffer size is not a power of 2");
++ handleException();
++ }
++ frame();
++}
++
++Buffer::~Buffer () {
++ delete [] buf;
++}
++
++void Buffer::write (Sender * const sender) {
++ if (!commitReady()) {
++ return;
++ }
++
++ // determine the size of two halves
++ int length1 = commitPos - readPos;
++ char * buffer1 = buf + readPos;
++ int length2 = 0;
++ char * buffer2 = buf;
++ if (length1 < 0) {
++ length1 = size - readPos;
++ length2 = commitPos;
++ }
++
++ logg->logMessage("Sending data length1: %i length2: %i", length1, length2);
++
++ // start, middle or end
++ if (length1 > 0) {
++ sender->writeData(buffer1, length1, RESPONSE_APC_DATA);
++ }
++
++ // possible wrap around
++ if (length2 > 0) {
++ sender->writeData(buffer2, length2, RESPONSE_APC_DATA);
++ }
++
++ readPos = commitPos;
++}
++
++bool Buffer::commitReady () const {
++ return commitPos != readPos;
++}
++
++int Buffer::bytesAvailable () const {
++ int filled = writePos - readPos;
++ if (filled < 0) {
++ filled += size;
++ }
++
++ int remaining = size - filled;
++
++ if (available) {
++ // Give some extra room; also allows space to insert the overflow error packet
++ remaining -= 200;
++ } else {
++ // Hysteresis, prevents multiple overflow messages
++ remaining -= 2000;
++ }
++
++ return remaining;
++}
++
++bool Buffer::checkSpace (const int bytes) {
++ const int remaining = bytesAvailable();
++
++ if (remaining < bytes) {
++ available = false;
++ } else {
++ available = true;
++ }
++
++ return available;
++}
++
++void Buffer::commit (const uint64_t time) {
++ // post-populate the length, which does not include the response type length nor the length itself, i.e. only the length of the payload
++ const int typeLength = gSessionData->mLocalCapture ? 0 : 1;
++ int length = writePos - commitPos;
++ if (length < 0) {
++ length += size;
++ }
++ length = length - typeLength - sizeof(int32_t);
++ for (size_t byte = 0; byte < sizeof(int32_t); byte++) {
++ buf[(commitPos + typeLength + byte) & mask] = (length >> byte * 8) & 0xFF;
++ }
++
++ logg->logMessage("Committing data readPos: %i writePos: %i commitPos: %i", readPos, writePos, commitPos);
++ commitPos = writePos;
++
++ if (gSessionData->mLiveRate > 0) {
++ while (time > commitTime) {
++ commitTime += gSessionData->mLiveRate;
++ }
++ }
++
++ if (!done) {
++ frame();
++ }
++
++ // send a notification that data is ready
++ sem_post(readerSem);
++}
++
++void Buffer::check (const uint64_t time) {
++ int filled = writePos - commitPos;
++ if (filled < 0) {
++ filled += size;
++ }
++ if (filled >= ((size * 3) / 4) || (gSessionData->mLiveRate > 0 && time >= commitTime)) {
++ commit(time);
++ }
++}
++
++void Buffer::packInt (int32_t x) {
++ int packedBytes = 0;
++ int more = true;
++ while (more) {
++ // low order 7 bits of x
++ char b = x & 0x7f;
++ x >>= 7;
++
++ if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
++ more = false;
++ } else {
++ b |= 0x80;
++ }
++
++ buf[(writePos + packedBytes) & mask] = b;
++ packedBytes++;
++ }
++
++ writePos = (writePos + packedBytes) & mask;
++}
++
++void Buffer::packInt64 (int64_t x) {
++ int packedBytes = 0;
++ int more = true;
++ while (more) {
++ // low order 7 bits of x
++ char b = x & 0x7f;
++ x >>= 7;
++
++ if ((x == 0 && (b & 0x40) == 0) || (x == -1 && (b & 0x40) != 0)) {
++ more = false;
++ } else {
++ b |= 0x80;
++ }
++
++ buf[(writePos + packedBytes) & mask] = b;
++ packedBytes++;
++ }
++
++ writePos = (writePos + packedBytes) & mask;
++}
++
++void Buffer::frame () {
++ if (!gSessionData->mLocalCapture) {
++ packInt(RESPONSE_APC_DATA);
++ }
++ // Reserve space for the length
++ writePos += sizeof(int32_t);
++ packInt(buftype);
++ packInt(core);
++}
++
++bool Buffer::eventHeader (const uint64_t curr_time) {
++ bool retval = false;
++ if (checkSpace(MAXSIZE_PACK32 + MAXSIZE_PACK64)) {
++ packInt(0); // key of zero indicates a timestamp
++ packInt64(curr_time);
++ retval = true;
++ }
++
++ return retval;
++}
++
++bool Buffer::eventTid (const int tid) {
++ bool retval = false;
++ if (checkSpace(2*MAXSIZE_PACK32)) {
++ packInt(1); // key of 1 indicates a tid
++ packInt(tid);
++ retval = true;
++ }
++
++ return retval;
++}
++
++void Buffer::event (const int32_t key, const int32_t value) {
++ if (checkSpace(2 * MAXSIZE_PACK32)) {
++ packInt(key);
++ packInt(value);
++ }
++}
++
++void Buffer::event64 (const int64_t key, const int64_t value) {
++ if (checkSpace(2 * MAXSIZE_PACK64)) {
++ packInt64(key);
++ packInt64(value);
++ }
++}
++
++void Buffer::setDone () {
++ done = true;
++ commit(0);
++}
++
++bool Buffer::isDone () const {
++ return done && readPos == commitPos && commitPos == writePos;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Buffer.h linux-linaro-stable-mx6/tools/gator/daemon/Buffer.h
+--- linux-3.10.30.orig/tools/gator/daemon/Buffer.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Buffer.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,66 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef BUFFER_H
++#define BUFFER_H
++
++#include <stddef.h>
++#include <stdint.h>
++#include <semaphore.h>
++
++class Sender;
++
++class Buffer {
++public:
++ static const size_t MAXSIZE_PACK32 = 5;
++ static const size_t MAXSIZE_PACK64 = 10;
++
++ Buffer (int32_t core, int32_t buftype, const int size, sem_t *const readerSem);
++ ~Buffer ();
++
++ void write (Sender * sender);
++
++ int bytesAvailable () const;
++ void commit (const uint64_t time);
++ void check (const uint64_t time);
++
++ void frame ();
++
++ bool eventHeader (uint64_t curr_time);
++ bool eventTid (int tid);
++ void event (int32_t key, int32_t value);
++ void event64 (int64_t key, int64_t value);
++
++ void setDone ();
++ bool isDone () const;
++
++private:
++ bool commitReady () const;
++ bool checkSpace (int bytes);
++
++ void packInt (int32_t x);
++ void packInt64 (int64_t x);
++
++ const int32_t core;
++ const int32_t buftype;
++ const int size;
++ int readPos;
++ int writePos;
++ int commitPos;
++ bool available;
++ bool done;
++ char *const buf;
++ uint64_t commitTime;
++ sem_t *const readerSem;
++
++ // Intentionally unimplemented
++ Buffer(const Buffer &);
++ Buffer &operator=(const Buffer &);
++};
++
++#endif // BUFFER_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/CapturedXML.cpp linux-linaro-stable-mx6/tools/gator/daemon/CapturedXML.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/CapturedXML.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/CapturedXML.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,134 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <stdlib.h>
++#include <string.h>
++#include <dirent.h>
++#include "SessionData.h"
++#include "CapturedXML.h"
++#include "Logging.h"
++#include "OlyUtility.h"
++
++CapturedXML::CapturedXML() {
++}
++
++CapturedXML::~CapturedXML() {
++}
++
++mxml_node_t* CapturedXML::getTree(bool includeTime) {
++ mxml_node_t *xml;
++ mxml_node_t *captured;
++ mxml_node_t *target;
++ int x;
++
++ xml = mxmlNewXML("1.0");
++
++ captured = mxmlNewElement(xml, "captured");
++ mxmlElementSetAttr(captured, "version", "1");
++ mxmlElementSetAttrf(captured, "protocol", "%d", PROTOCOL_VERSION);
++ if (includeTime) { // Send the following only after the capture is complete
++ if (time(NULL) > 1267000000) { // If the time is reasonable (after Feb 23, 2010)
++ mxmlElementSetAttrf(captured, "created", "%lu", time(NULL)); // Valid until the year 2038
++ }
++ }
++
++ target = mxmlNewElement(captured, "target");
++ mxmlElementSetAttr(target, "name", gSessionData->mCoreName);
++ mxmlElementSetAttrf(target, "sample_rate", "%d", gSessionData->mSampleRate);
++ mxmlElementSetAttrf(target, "cores", "%d", gSessionData->mCores);
++ mxmlElementSetAttrf(target, "cpuid", "0x%x", gSessionData->mCpuId);
++
++ if (!gSessionData->mOneShot && (gSessionData->mSampleRate > 0)) {
++ mxmlElementSetAttr(target, "supports_live", "yes");
++ }
++
++ if (gSessionData->mLocalCapture) {
++ mxmlElementSetAttr(target, "local_capture", "yes");
++ }
++
++ mxml_node_t *counters = NULL;
++ for (x = 0; x < MAX_PERFORMANCE_COUNTERS; x++) {
++ const Counter & counter = gSessionData->mCounters[x];
++ if (counter.isEnabled()) {
++ if (counters == NULL) {
++ counters = mxmlNewElement(captured, "counters");
++ }
++ mxml_node_t *const node = mxmlNewElement(counters, "counter");
++ mxmlElementSetAttrf(node, "key", "0x%x", counter.getKey());
++ mxmlElementSetAttr(node, "type", counter.getType());
++ mxmlElementSetAttrf(node, "event", "0x%x", counter.getEvent());
++ if (counter.getCount() > 0) {
++ mxmlElementSetAttrf(node, "count", "%d", counter.getCount());
++ }
++ }
++ }
++
++ return xml;
++}
++
++char* CapturedXML::getXML(bool includeTime) {
++ char* xml_string;
++ mxml_node_t *xml = getTree(includeTime);
++ xml_string = mxmlSaveAllocString(xml, mxmlWhitespaceCB);
++ mxmlDelete(xml);
++ return xml_string;
++}
++
++void CapturedXML::write(char* path) {
++ char file[PATH_MAX];
++
++ // Set full path
++ snprintf(file, PATH_MAX, "%s/captured.xml", path);
++
++ char* xml = getXML(true);
++ if (util->writeToDisk(file, xml) < 0) {
++ logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
++ handleException();
++ }
++
++ free(xml);
++}
++
++// whitespace callback utility function used with mini-xml
++const char * mxmlWhitespaceCB(mxml_node_t *node, int loc) {
++ const char *name;
++
++ name = mxmlGetElement(node);
++
++ if (loc == MXML_WS_BEFORE_OPEN) {
++ // Single indentation
++ if (!strcmp(name, "target") || !strcmp(name, "counters"))
++ return("\n ");
++
++ // Double indentation
++ if (!strcmp(name, "counter"))
++ return("\n ");
++
++ // Avoid a carriage return on the first line of the xml file
++ if (!strncmp(name, "?xml", 4))
++ return(NULL);
++
++ // Default - no indentation
++ return("\n");
++ }
++
++ if (loc == MXML_WS_BEFORE_CLOSE) {
++ // No indentation
++ if (!strcmp(name, "captured"))
++ return("\n");
++
++ // Single indentation
++ if (!strcmp(name, "counters"))
++ return("\n ");
++
++ // Default - no carriage return
++ return(NULL);
++ }
++
++ return(NULL);
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/CapturedXML.h linux-linaro-stable-mx6/tools/gator/daemon/CapturedXML.h
+--- linux-3.10.30.orig/tools/gator/daemon/CapturedXML.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/CapturedXML.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,26 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __CAPTURED_XML_H__
++#define __CAPTURED_XML_H__
++
++#include "mxml/mxml.h"
++
++class CapturedXML {
++public:
++ CapturedXML();
++ ~CapturedXML();
++ char* getXML(bool includeTime); // the string should be freed by the caller
++ void write(char* path);
++private:
++ mxml_node_t* getTree(bool includeTime);
++};
++
++const char * mxmlWhitespaceCB(mxml_node_t *node, int where);
++
++#endif //__CAPTURED_XML_H__
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Child.cpp linux-linaro-stable-mx6/tools/gator/daemon/Child.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/Child.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Child.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,409 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <stdlib.h>
++#include <string.h>
++#include <signal.h>
++#include <unistd.h>
++#include <sys/prctl.h>
++#include "Logging.h"
++#include "CapturedXML.h"
++#include "SessionData.h"
++#include "Child.h"
++#include "LocalCapture.h"
++#include "Collector.h"
++#include "Sender.h"
++#include "OlyUtility.h"
++#include "StreamlineSetup.h"
++#include "ConfigurationXML.h"
++#include "Driver.h"
++#include "Fifo.h"
++#include "Buffer.h"
++
++#define NS_PER_S ((uint64_t)1000000000)
++#define NS_PER_US 1000
++
++static sem_t haltPipeline, senderThreadStarted, startProfile, senderSem; // Shared by Child and spawned threads
++static Fifo* collectorFifo = NULL; // Shared by Child.cpp and spawned threads
++static Buffer* buffer = NULL;
++static Sender* sender = NULL; // Shared by Child.cpp and spawned threads
++static Collector* collector = NULL;
++Child* child = NULL; // shared by Child.cpp and main.cpp
++
++extern void cleanUp();
++void handleException() {
++ if (child && child->numExceptions++ > 0) {
++ // it is possible one of the below functions itself can cause an exception, thus allow only one exception
++ logg->logMessage("Received multiple exceptions, terminating the child");
++ exit(1);
++ }
++ fprintf(stderr, "%s", logg->getLastError());
++
++ if (child && child->socket) {
++ if (sender) {
++ // send the error, regardless of the command sent by Streamline
++ sender->writeData(logg->getLastError(), strlen(logg->getLastError()), RESPONSE_ERROR);
++
++ // cannot close the socket before Streamline issues the command, so wait for the command before exiting
++ if (gSessionData->mWaitingOnCommand) {
++ char discard;
++ child->socket->receiveNBytes(&discard, 1);
++ }
++
++ // Ensure all data is flushed
++ child->socket->shutdownConnection();
++
++ // this indirectly calls close socket which will ensure the data has been sent
++ delete sender;
++ }
++ }
++
++ if (gSessionData->mLocalCapture)
++ cleanUp();
++
++ exit(1);
++}
++
++// CTRL C Signal Handler for child process
++static void child_handler(int signum) {
++ static bool beenHere = false;
++ if (beenHere == true) {
++ logg->logMessage("Gator is being forced to shut down.");
++ exit(1);
++ }
++ beenHere = true;
++ logg->logMessage("Gator is shutting down.");
++ if (signum == SIGALRM || !collector) {
++ exit(1);
++ } else {
++ child->endSession();
++ alarm(5); // Safety net in case endSession does not complete within 5 seconds
++ }
++}
++
++static void *durationThread(void *) {
++ prctl(PR_SET_NAME, (unsigned long)&"gatord-duration", 0, 0, 0);
++ sem_wait(&startProfile);
++ if (gSessionData->mSessionIsActive) {
++ // Time out after duration seconds
++ // Add a second for host-side filtering
++ sleep(gSessionData->mDuration + 1);
++ if (gSessionData->mSessionIsActive) {
++ logg->logMessage("Duration expired.");
++ child->endSession();
++ }
++ }
++ logg->logMessage("Exit duration thread");
++ return 0;
++}
++
++static void *stopThread(void *) {
++ OlySocket* socket = child->socket;
++
++ prctl(PR_SET_NAME, (unsigned long)&"gatord-stopper", 0, 0, 0);
++ while (gSessionData->mSessionIsActive) {
++ // This thread will stall until the APC_STOP or PING command is received over the socket or the socket is disconnected
++ unsigned char header[5];
++ const int result = socket->receiveNBytes((char*)&header, sizeof(header));
++ const char type = header[0];
++ const int length = (header[1] << 0) | (header[2] << 8) | (header[3] << 16) | (header[4] << 24);
++ if (result == -1) {
++ child->endSession();
++ } else if (result > 0) {
++ if ((type != COMMAND_APC_STOP) && (type != COMMAND_PING)) {
++ logg->logMessage("INVESTIGATE: Received unknown command type %d", type);
++ } else {
++ // verify a length of zero
++ if (length == 0) {
++ if (type == COMMAND_APC_STOP) {
++ logg->logMessage("Stop command received.");
++ child->endSession();
++ } else {
++ // Ping is used to make sure gator is alive and requires an ACK as the response
++ logg->logMessage("Ping command received.");
++ sender->writeData(NULL, 0, RESPONSE_ACK);
++ }
++ } else {
++ logg->logMessage("INVESTIGATE: Received stop command but with length = %d", length);
++ }
++ }
++ }
++ }
++
++ logg->logMessage("Exit stop thread");
++ return 0;
++}
++
++static void *countersThread(void *) {
++ prctl(PR_SET_NAME, (unsigned long)&"gatord-counters", 0, 0, 0);
++
++ gSessionData->hwmon.start();
++
++ int64_t monotonic_started = 0;
++ while (monotonic_started <= 0) {
++ usleep(10);
++
++ if (Collector::readInt64Driver("/dev/gator/started", &monotonic_started) == -1) {
++ logg->logError(__FILE__, __LINE__, "Error reading gator driver start time");
++ handleException();
++ }
++ }
++
++ uint64_t next_time = 0;
++ while (gSessionData->mSessionIsActive) {
++ struct timespec ts;
++#ifndef CLOCK_MONOTONIC_RAW
++ // Android doesn't have this defined but it was added in Linux 2.6.28
++#define CLOCK_MONOTONIC_RAW 4
++#endif
++ if (clock_gettime(CLOCK_MONOTONIC_RAW, &ts) != 0) {
++ logg->logError(__FILE__, __LINE__, "Failed to get uptime");
++ handleException();
++ }
++ const uint64_t curr_time = (NS_PER_S*ts.tv_sec + ts.tv_nsec) - monotonic_started;
++ // Sample ten times a second ignoring gSessionData->mSampleRate
++ next_time += NS_PER_S/10;//gSessionData->mSampleRate;
++ if (next_time < curr_time) {
++ logg->logMessage("Too slow, curr_time: %lli next_time: %lli", curr_time, next_time);
++ next_time = curr_time;
++ }
++
++ if (buffer->eventHeader(curr_time)) {
++ gSessionData->hwmon.read(buffer);
++ // Only check after writing all counters so that time and corresponding counters appear in the same frame
++ buffer->check(curr_time);
++ }
++
++ if (buffer->bytesAvailable() <= 0) {
++ logg->logMessage("One shot (counters)");
++ child->endSession();
++ }
++
++ usleep((next_time - curr_time)/NS_PER_US);
++ }
++
++ buffer->setDone();
++
++ return NULL;
++}
++
++static void *senderThread(void *) {
++ int length = 1;
++ char* data;
++ char end_sequence[] = {RESPONSE_APC_DATA, 0, 0, 0, 0};
++
++ sem_post(&senderThreadStarted);
++ prctl(PR_SET_NAME, (unsigned long)&"gatord-sender", 0, 0, 0);
++ sem_wait(&haltPipeline);
++
++ while (length > 0 || !buffer->isDone()) {
++ sem_wait(&senderSem);
++ data = collectorFifo->read(&length);
++ if (data != NULL) {
++ sender->writeData(data, length, RESPONSE_APC_DATA);
++ collectorFifo->release();
++ }
++ if (!buffer->isDone()) {
++ buffer->write(sender);
++ }
++ }
++
++ // write end-of-capture sequence
++ if (!gSessionData->mLocalCapture) {
++ sender->writeData(end_sequence, sizeof(end_sequence), RESPONSE_APC_DATA);
++ }
++
++ logg->logMessage("Exit sender thread");
++ return 0;
++}
++
++Child::Child() {
++ initialization();
++ gSessionData->mLocalCapture = true;
++}
++
++Child::Child(OlySocket* sock, int conn) {
++ initialization();
++ socket = sock;
++ mNumConnections = conn;
++}
++
++Child::~Child() {
++}
++
++void Child::initialization() {
++ // Set up different handlers for signals
++ gSessionData->mSessionIsActive = true;
++ signal(SIGINT, child_handler);
++ signal(SIGTERM, child_handler);
++ signal(SIGABRT, child_handler);
++ signal(SIGALRM, child_handler);
++ socket = NULL;
++ numExceptions = 0;
++ mNumConnections = 0;
++
++ // Initialize semaphores
++ sem_init(&senderThreadStarted, 0, 0);
++ sem_init(&startProfile, 0, 0);
++ sem_init(&senderSem, 0, 0);
++}
++
++void Child::endSession() {
++ gSessionData->mSessionIsActive = false;
++ collector->stop();
++ sem_post(&haltPipeline);
++}
++
++void Child::run() {
++ char* collectBuffer;
++ int bytesCollected = 0;
++ LocalCapture* localCapture = NULL;
++ pthread_t durationThreadID, stopThreadID, senderThreadID, countersThreadID;
++
++ prctl(PR_SET_NAME, (unsigned long)&"gatord-child", 0, 0, 0);
++
++ // Disable line wrapping when generating xml files; carriage returns and indentation to be added manually
++ mxmlSetWrapMargin(0);
++
++ // Instantiate the Sender - must be done first, after which error messages can be sent
++ sender = new Sender(socket);
++
++ if (mNumConnections > 1) {
++ logg->logError(__FILE__, __LINE__, "Session already in progress");
++ handleException();
++ }
++
++ // Populate gSessionData with the configuration
++ { ConfigurationXML configuration; }
++
++ // Set up the driver; must be done after gSessionData->mPerfCounterType[] is populated
++ collector = new Collector();
++
++ // Initialize all drivers
++ for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
++ driver->resetCounters();
++ }
++
++ // Set up counters using the associated driver's setup function
++ for (int i = 0; i < MAX_PERFORMANCE_COUNTERS; i++) {
++ Counter & counter = gSessionData->mCounters[i];
++ if (counter.isEnabled()) {
++ counter.getDriver()->setupCounter(counter);
++ }
++ }
++
++ // Start up and parse session xml
++ if (socket) {
++ // Respond to Streamline requests
++ StreamlineSetup ss(socket);
++ } else {
++ char* xmlString;
++ xmlString = util->readFromDisk(gSessionData->mSessionXMLPath);
++ if (xmlString == 0) {
++ logg->logError(__FILE__, __LINE__, "Unable to read session xml file: %s", gSessionData->mSessionXMLPath);
++ handleException();
++ }
++ gSessionData->parseSessionXML(xmlString);
++ localCapture = new LocalCapture();
++ localCapture->createAPCDirectory(gSessionData->mTargetPath);
++ localCapture->copyImages(gSessionData->mImages);
++ localCapture->write(xmlString);
++ sender->createDataFile(gSessionData->mAPCDir);
++ free(xmlString);
++ }
++
++ // Create user-space buffers, add 5 to the size to account for the 1-byte type and 4-byte length
++ logg->logMessage("Created %d MB collector buffer with a %d-byte ragged end", gSessionData->mTotalBufferSize, collector->getBufferSize());
++ collectorFifo = new Fifo(collector->getBufferSize() + 5, gSessionData->mTotalBufferSize*1024*1024, &senderSem);
++
++ // Get the initial pointer to the collect buffer
++ collectBuffer = collectorFifo->start();
++
++ // Create a new Block Counter Buffer
++ buffer = new Buffer(0, 5, gSessionData->mTotalBufferSize*1024*1024, &senderSem);
++
++ // Sender thread shall be halted until it is signaled for one shot mode
++ sem_init(&haltPipeline, 0, gSessionData->mOneShot ? 0 : 2);
++
++ // Create the duration, stop, and sender threads
++ bool thread_creation_success = true;
++ if (gSessionData->mDuration > 0 && pthread_create(&durationThreadID, NULL, durationThread, NULL)) {
++ thread_creation_success = false;
++ } else if (socket && pthread_create(&stopThreadID, NULL, stopThread, NULL)) {
++ thread_creation_success = false;
++ } else if (pthread_create(&senderThreadID, NULL, senderThread, NULL)){
++ thread_creation_success = false;
++ }
++
++ bool startcountersThread = gSessionData->hwmon.countersEnabled();
++ if (startcountersThread) {
++ if (pthread_create(&countersThreadID, NULL, countersThread, this)) {
++ thread_creation_success = false;
++ }
++ } else {
++ // Let senderThread know there is no buffer data to send
++ buffer->setDone();
++ }
++
++ if (!thread_creation_success) {
++ logg->logError(__FILE__, __LINE__, "Failed to create gator threads");
++ handleException();
++ }
++
++ // Wait until thread has started
++ sem_wait(&senderThreadStarted);
++
++ // Start profiling
++ logg->logMessage("********** Profiling started **********");
++ collector->start();
++ sem_post(&startProfile);
++
++ // Collect Data
++ do {
++ // This command will stall until data is received from the driver
++ bytesCollected = collector->collect(collectBuffer);
++
++ // In one shot mode, stop collection once all the buffers are filled
++ if (gSessionData->mOneShot && gSessionData->mSessionIsActive) {
++ if (bytesCollected == -1 || collectorFifo->willFill(bytesCollected)) {
++ logg->logMessage("One shot");
++ endSession();
++ }
++ }
++ collectBuffer = collectorFifo->write(bytesCollected);
++ } while (bytesCollected > 0);
++ logg->logMessage("Exit collect data loop");
++
++ if (startcountersThread) {
++ pthread_join(countersThreadID, NULL);
++ }
++
++ // Wait for the other threads to exit
++ pthread_join(senderThreadID, NULL);
++
++ // Shutting down the connection should break the stop thread which is stalling on the socket recv() function
++ if (socket) {
++ logg->logMessage("Waiting on stop thread");
++ socket->shutdownConnection();
++ pthread_join(stopThreadID, NULL);
++ }
++
++ // Write the captured xml file
++ if (gSessionData->mLocalCapture) {
++ CapturedXML capturedXML;
++ capturedXML.write(gSessionData->mAPCDir);
++ }
++
++ logg->logMessage("Profiling ended.");
++
++ delete buffer;
++ delete collectorFifo;
++ delete sender;
++ delete collector;
++ delete localCapture;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Child.h linux-linaro-stable-mx6/tools/gator/daemon/Child.h
+--- linux-3.10.30.orig/tools/gator/daemon/Child.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Child.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,35 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __CHILD_H__
++#define __CHILD_H__
++
++#include <pthread.h>
++
++class OlySocket;
++
++class Child {
++public:
++ Child();
++ Child(OlySocket* sock, int numConnections);
++ ~Child();
++ void run();
++ OlySocket *socket;
++ void endSession();
++ int numExceptions;
++private:
++ int mNumConnections;
++
++ void initialization();
++
++ // Intentionally unimplemented
++ Child(const Child &);
++ Child &operator=(const Child &);
++};
++
++#endif //__CHILD_H__
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Collector.cpp linux-linaro-stable-mx6/tools/gator/daemon/Collector.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/Collector.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Collector.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,221 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#define __STDC_FORMAT_MACROS
++
++#include <fcntl.h>
++#include <unistd.h>
++#include <string.h>
++#include <stdlib.h>
++#include <errno.h>
++#include <sys/time.h>
++#include <inttypes.h>
++#include "Collector.h"
++#include "SessionData.h"
++#include "Logging.h"
++#include "Sender.h"
++
++// Driver initialization independent of session settings
++Collector::Collector() {
++ mBufferFD = 0;
++
++ checkVersion();
++
++ int enable = -1;
++ if (readIntDriver("/dev/gator/enable", &enable) != 0 || enable != 0) {
++ logg->logError(__FILE__, __LINE__, "Driver already enabled, possibly a session is already in progress.");
++ handleException();
++ }
++
++ readIntDriver("/dev/gator/cpu_cores", &gSessionData->mCores);
++ if (gSessionData->mCores == 0) {
++ gSessionData->mCores = 1;
++ }
++
++ mBufferSize = 0;
++ if (readIntDriver("/dev/gator/buffer_size", &mBufferSize) || mBufferSize <= 0) {
++ logg->logError(__FILE__, __LINE__, "Unable to read the driver buffer size");
++ handleException();
++ }
++}
++
++Collector::~Collector() {
++ // Write zero for safety, as a zero should have already been written
++ writeDriver("/dev/gator/enable", "0");
++
++ // Calls event_buffer_release in the driver
++ if (mBufferFD) {
++ close(mBufferFD);
++ }
++}
++
++void Collector::checkVersion() {
++ int driver_version = 0;
++
++ if (readIntDriver("/dev/gator/version", &driver_version) == -1) {
++ logg->logError(__FILE__, __LINE__, "Error reading gator driver version");
++ handleException();
++ }
++
++ // Verify the driver version matches the daemon version
++ if (driver_version != PROTOCOL_VERSION) {
++ if ((driver_version > PROTOCOL_DEV) || (PROTOCOL_VERSION > PROTOCOL_DEV)) {
++ // One of the mismatched versions is development version
++ logg->logError(__FILE__, __LINE__,
++ "DEVELOPMENT BUILD MISMATCH: gator driver version \"%d\" is not in sync with gator daemon version \"%d\".\n"
++ ">> The following must be synchronized from engineering repository:\n"
++ ">> * gator driver\n"
++ ">> * gator daemon\n"
++ ">> * Streamline", driver_version, PROTOCOL_VERSION);
++ handleException();
++ } else {
++ // Release version mismatch
++ logg->logError(__FILE__, __LINE__,
++ "gator driver version \"%d\" is different than gator daemon version \"%d\".\n"
++ ">> Please upgrade the driver and daemon to the latest versions.", driver_version, PROTOCOL_VERSION);
++ handleException();
++ }
++ }
++}
++
++void Collector::start() {
++ // Set the maximum backtrace depth
++ if (writeReadDriver("/dev/gator/backtrace_depth", &gSessionData->mBacktraceDepth)) {
++ logg->logError(__FILE__, __LINE__, "Unable to set the driver backtrace depth");
++ handleException();
++ }
++
++ // open the buffer which calls userspace_buffer_open() in the driver
++ mBufferFD = open("/dev/gator/buffer", O_RDONLY);
++ if (mBufferFD < 0) {
++ logg->logError(__FILE__, __LINE__, "The gator driver did not set up properly. Please view the linux console or dmesg log for more information on the failure.");
++ handleException();
++ }
++
++ // set the tick rate of the profiling timer
++ if (writeReadDriver("/dev/gator/tick", &gSessionData->mSampleRate) != 0) {
++ logg->logError(__FILE__, __LINE__, "Unable to set the driver tick");
++ handleException();
++ }
++
++ // notify the kernel of the response type
++ int response_type = gSessionData->mLocalCapture ? 0 : RESPONSE_APC_DATA;
++ if (writeDriver("/dev/gator/response_type", response_type)) {
++ logg->logError(__FILE__, __LINE__, "Unable to write the response type");
++ handleException();
++ }
++
++ // Set the live rate
++ if (writeReadDriver("/dev/gator/live_rate", &gSessionData->mLiveRate)) {
++ logg->logError(__FILE__, __LINE__, "Unable to set the driver live rate");
++ handleException();
++ }
++
++ logg->logMessage("Start the driver");
++
++ // This command makes the driver start profiling by calling gator_op_start() in the driver
++ if (writeDriver("/dev/gator/enable", "1") != 0) {
++ logg->logError(__FILE__, __LINE__, "The gator driver did not start properly. Please view the linux console or dmesg log for more information on the failure.");
++ handleException();
++ }
++
++ lseek(mBufferFD, 0, SEEK_SET);
++}
++
++// These commands should cause the read() function in collect() to return
++void Collector::stop() {
++ // This will stop the driver from profiling
++ if (writeDriver("/dev/gator/enable", "0") != 0) {
++ logg->logMessage("Stopping kernel failed");
++ }
++}
++
++int Collector::collect(char* buffer) {
++ // Calls event_buffer_read in the driver
++ int bytesRead;
++
++ errno = 0;
++ bytesRead = read(mBufferFD, buffer, mBufferSize);
++
++ // If read() returned due to an interrupt signal, re-read to obtain the last bit of collected data
++ if (bytesRead == -1 && errno == EINTR) {
++ bytesRead = read(mBufferFD, buffer, mBufferSize);
++ }
++
++ // return the total bytes written
++ logg->logMessage("Driver read of %d bytes", bytesRead);
++ return bytesRead;
++}
++
++int Collector::readIntDriver(const char* fullpath, int* value) {
++ FILE* file = fopen(fullpath, "r");
++ if (file == NULL) {
++ return -1;
++ }
++ if (fscanf(file, "%u", value) != 1) {
++ fclose(file);
++ logg->logMessage("Invalid value in file %s", fullpath);
++ return -1;
++ }
++ fclose(file);
++ return 0;
++}
++
++int Collector::readInt64Driver(const char* fullpath, int64_t* value) {
++ FILE* file = fopen(fullpath, "r");
++ if (file == NULL) {
++ return -1;
++ }
++ if (fscanf(file, "%" SCNi64, value) != 1) {
++ fclose(file);
++ logg->logMessage("Invalid value in file %s", fullpath);
++ return -1;
++ }
++ fclose(file);
++ return 0;
++}
++
++int Collector::writeDriver(const char* path, int value) {
++ char data[40]; // Sufficiently large to hold any integer
++ snprintf(data, sizeof(data), "%d", value);
++ return writeDriver(path, data);
++}
++
++int Collector::writeDriver(const char* path, int64_t value) {
++ char data[40]; // Sufficiently large to hold any integer
++ snprintf(data, sizeof(data), "%" PRIi64, value);
++ return writeDriver(path, data);
++}
++
++int Collector::writeDriver(const char* fullpath, const char* data) {
++ int fd = open(fullpath, O_WRONLY);
++ if (fd < 0) {
++ return -1;
++ }
++ if (write(fd, data, strlen(data)) < 0) {
++ close(fd);
++ logg->logMessage("Opened but could not write to %s", fullpath);
++ return -1;
++ }
++ close(fd);
++ return 0;
++}
++
++int Collector::writeReadDriver(const char* path, int* value) {
++ if (writeDriver(path, *value) || readIntDriver(path, value)) {
++ return -1;
++ }
++ return 0;
++}
++
++int Collector::writeReadDriver(const char* path, int64_t* value) {
++ if (writeDriver(path, *value) || readInt64Driver(path, value)) {
++ return -1;
++ }
++ return 0;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Collector.h linux-linaro-stable-mx6/tools/gator/daemon/Collector.h
+--- linux-3.10.30.orig/tools/gator/daemon/Collector.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Collector.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,38 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __COLLECTOR_H__
++#define __COLLECTOR_H__
++
++#include <stdio.h>
++
++class Collector {
++public:
++ Collector();
++ ~Collector();
++ void start();
++ void stop();
++ int collect(char* buffer);
++ int getBufferSize() {return mBufferSize;}
++
++ static int readIntDriver(const char* path, int* value);
++ static int readInt64Driver(const char* path, int64_t* value);
++ static int writeDriver(const char* path, int value);
++ static int writeDriver(const char* path, int64_t value);
++ static int writeDriver(const char* path, const char* data);
++ static int writeReadDriver(const char* path, int* value);
++ static int writeReadDriver(const char* path, int64_t* value);
++
++private:
++ int mBufferSize;
++ int mBufferFD;
++
++ void checkVersion();
++};
++
++#endif //__COLLECTOR_H__
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/common.mk linux-linaro-stable-mx6/tools/gator/daemon/common.mk
+--- linux-3.10.30.orig/tools/gator/daemon/common.mk 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/common.mk 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,50 @@
++# -g produces debugging information
++# -O3 maximum optimization
++# -O0 no optimization, used for debugging
++# -Wall enables most warnings
++# -Werror treats warnings as errors
++# -std=c++0x is the planned new c++ standard
++# -std=c++98 is the 1998 c++ standard
++CFLAGS += -O3 -Wall -fno-exceptions -pthread -MMD -DETCDIR=\"/etc\" -Ilibsensors
++CXXFLAGS += -fno-rtti -Wextra # -Weffc++
++ifeq ($(WERROR),1)
++ CFLAGS += -Werror
++endif
++# -s strips the binary of debug info
++LDFLAGS += -s
++TARGET = gatord
++C_SRC = $(wildcard mxml/*.c) $(wildcard libsensors/*.c)
++CPP_SRC = $(wildcard *.cpp)
++
++all: $(TARGET)
++
++events.xml: events_header.xml $(wildcard events-*.xml) events_footer.xml
++ cat $^ > $@
++
++include $(wildcard *.d)
++include $(wildcard mxml/*.d)
++
++EventsXML.cpp: events_xml.h
++ConfigurationXML.cpp: configuration_xml.h
++
++# Don't regenerate conf-lex.c or conf-parse.c
++libsensors/conf-lex.c: ;
++libsensors/conf-parse.c: ;
++
++%_xml.h: %.xml escape
++ ./escape $< > $@
++
++%.o: %.c
++ $(GCC) -c $(CFLAGS) -o $@ $<
++
++%.o: %.cpp
++ $(CPP) -c $(CFLAGS) $(CXXFLAGS) -o $@ $<
++
++$(TARGET): $(CPP_SRC:%.cpp=%.o) $(C_SRC:%.c=%.o)
++ $(CPP) $(LDFLAGS) -o $@ $^ -lrt -pthread
++
++escape: escape.c
++ gcc $^ -o $@
++
++clean:
++ rm -f *.d *.o mxml/*.d mxml/*.o libsensors/*.d libsensors/*.o $(TARGET) escape events.xml events_xml.h configuration_xml.h
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/configuration.xml linux-linaro-stable-mx6/tools/gator/daemon/configuration.xml
+--- linux-3.10.30.orig/tools/gator/daemon/configuration.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/configuration.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,57 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<configurations revision="3">
++ <configuration counter="ARM_ARM11_ccnt" event="0xff"/>
++ <configuration counter="ARM_ARM11_cnt0" event="0x7"/>
++ <configuration counter="ARM_ARM11_cnt1" event="0xb"/>
++ <configuration counter="ARM_ARM11MPCore_ccnt" event="0xff"/>
++ <configuration counter="ARM_ARM11MPCore_cnt0" event="0x08"/>
++ <configuration counter="ARM_ARM11MPCore_cnt1" event="0x0b"/>
++ <configuration counter="ARM_Cortex-A5_ccnt" event="0xff"/>
++ <configuration counter="ARM_Cortex-A5_cnt0" event="0x8"/>
++ <configuration counter="ARM_Cortex-A5_cnt1" event="0x1"/>
++ <configuration counter="ARM_Cortex-A7_ccnt" event="0xff"/>
++ <configuration counter="ARM_Cortex-A7_cnt0" event="0x08"/>
++ <configuration counter="ARM_Cortex-A7_cnt1" event="0x10"/>
++ <configuration counter="ARM_Cortex-A7_cnt2" event="0x16"/>
++ <configuration counter="ARM_Cortex-A8_ccnt" event="0xff"/>
++ <configuration counter="ARM_Cortex-A8_cnt0" event="0x8"/>
++ <configuration counter="ARM_Cortex-A8_cnt1" event="0x44"/>
++ <configuration counter="ARM_Cortex-A8_cnt2" event="0x43"/>
++ <configuration counter="ARM_Cortex-A8_cnt3" event="0x10"/>
++ <configuration counter="ARM_Cortex-A9_ccnt" event="0xff"/>
++ <configuration counter="ARM_Cortex-A9_cnt0" event="0x68"/>
++ <configuration counter="ARM_Cortex-A9_cnt1" event="0x06"/>
++ <configuration counter="ARM_Cortex-A9_cnt2" event="0x07"/>
++ <configuration counter="ARM_Cortex-A9_cnt3" event="0x03"/>
++ <configuration counter="ARM_Cortex-A9_cnt4" event="0x04"/>
++ <configuration counter="ARM_Cortex-A15_ccnt" event="0xff"/>
++ <configuration counter="ARM_Cortex-A15_cnt0" event="0x8"/>
++ <configuration counter="ARM_Cortex-A15_cnt1" event="0x16"/>
++ <configuration counter="ARM_Cortex-A15_cnt2" event="0x10"/>
++ <configuration counter="ARM_Cortex-A15_cnt3" event="0x19"/>
++ <configuration counter="ARM_Cortex-A53_ccnt" event="0x11"/>
++ <configuration counter="ARM_Cortex-A53_cnt0" event="0x8"/>
++ <configuration counter="ARM_Cortex-A53_cnt1" event="0x16"/>
++ <configuration counter="ARM_Cortex-A53_cnt2" event="0x10"/>
++ <configuration counter="ARM_Cortex-A53_cnt3" event="0x19"/>
++ <configuration counter="ARM_Cortex-A57_ccnt" event="0x11"/>
++ <configuration counter="ARM_Cortex-A57_cnt0" event="0x8"/>
++ <configuration counter="ARM_Cortex-A57_cnt1" event="0x16"/>
++ <configuration counter="ARM_Cortex-A57_cnt2" event="0x10"/>
++ <configuration counter="ARM_Cortex-A57_cnt3" event="0x19"/>
++ <configuration counter="Scorpion_ccnt" event="0xff"/>
++ <configuration counter="Scorpion_cnt0" event="0x08"/>
++ <configuration counter="Scorpion_cnt1" event="0x10"/>
++ <configuration counter="ScorpionMP_ccnt" event="0xff"/>
++ <configuration counter="ScorpionMP_cnt0" event="0x08"/>
++ <configuration counter="ScorpionMP_cnt1" event="0x10"/>
++ <configuration counter="Krait_ccnt" event="0xff"/>
++ <configuration counter="Krait_cnt0" event="0x08"/>
++ <configuration counter="Krait_cnt1" event="0x10"/>
++ <configuration counter="Linux_block_rq_wr"/>
++ <configuration counter="Linux_block_rq_rd"/>
++ <configuration counter="Linux_meminfo_memused"/>
++ <configuration counter="Linux_meminfo_memfree"/>
++ <configuration counter="Linux_power_cpu_freq"/>
++ <configuration counter="L2C-310_cnt0" event="0x1"/>
++</configurations>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/ConfigurationXML.cpp linux-linaro-stable-mx6/tools/gator/daemon/ConfigurationXML.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/ConfigurationXML.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/ConfigurationXML.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,209 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <string.h>
++#include <stdlib.h>
++#include <dirent.h>
++#include "ConfigurationXML.h"
++#include "Driver.h"
++#include "Logging.h"
++#include "OlyUtility.h"
++#include "SessionData.h"
++
++static const char* ATTR_COUNTER = "counter";
++static const char* ATTR_REVISION = "revision";
++static const char* ATTR_EVENT = "event";
++static const char* ATTR_COUNT = "count";
++
++ConfigurationXML::ConfigurationXML() {
++ const char * configuration_xml;
++ unsigned int configuration_xml_len;
++ getDefaultConfigurationXml(configuration_xml, configuration_xml_len);
++
++ char path[PATH_MAX];
++
++ getPath(path);
++ mConfigurationXML = util->readFromDisk(path);
++
++ for (int retryCount = 0; retryCount < 2; ++retryCount) {
++ if (mConfigurationXML == NULL) {
++ logg->logMessage("Unable to locate configuration.xml, using default in binary");
++ // null-terminate configuration_xml
++ mConfigurationXML = (char*)malloc(configuration_xml_len + 1);
++ memcpy(mConfigurationXML, (const void*)configuration_xml, configuration_xml_len);
++ mConfigurationXML[configuration_xml_len] = 0;
++ }
++
++ int ret = parse(mConfigurationXML);
++ if (ret == 1) {
++ remove();
++
++ // Free the current configuration and reload
++ free((void*)mConfigurationXML);
++ mConfigurationXML = NULL;
++ continue;
++ }
++
++ break;
++ }
++
++ validate();
++}
++
++ConfigurationXML::~ConfigurationXML() {
++ if (mConfigurationXML) {
++ free((void*)mConfigurationXML);
++ }
++}
++
++int ConfigurationXML::parse(const char* configurationXML) {
++ mxml_node_t *tree, *node;
++ int ret;
++
++ // clear counter overflow
++ gSessionData->mCounterOverflow = 0;
++ mIndex = 0;
++
++ // disable all counters prior to parsing the configuration xml
++ for (int i = 0; i < MAX_PERFORMANCE_COUNTERS; i++) {
++ gSessionData->mCounters[i].setEnabled(false);
++ }
++
++ tree = mxmlLoadString(NULL, configurationXML, MXML_NO_CALLBACK);
++
++ node = mxmlGetFirstChild(tree);
++ while (node && mxmlGetType(node) != MXML_ELEMENT)
++ node = mxmlWalkNext(node, tree, MXML_NO_DESCEND);
++
++ ret = configurationsTag(node);
++
++ node = mxmlGetFirstChild(node);
++ while (node) {
++ if (mxmlGetType(node) != MXML_ELEMENT) {
++ node = mxmlWalkNext(node, tree, MXML_NO_DESCEND);
++ continue;
++ }
++ configurationTag(node);
++ node = mxmlWalkNext(node, tree, MXML_NO_DESCEND);
++ }
++
++ mxmlDelete(tree);
++
++ return ret;
++}
++
++void ConfigurationXML::validate(void) {
++ for (int i = 0; i < MAX_PERFORMANCE_COUNTERS; i++) {
++ const Counter & counter = gSessionData->mCounters[i];
++ if (counter.isEnabled()) {
++ if (strcmp(counter.getType(), "") == 0) {
++ logg->logError(__FILE__, __LINE__, "Invalid required attribute in configuration.xml:\n counter=\"%s\"\n event=%d\n", counter.getType(), counter.getEvent());
++ handleException();
++ }
++
++ // iterate through the remaining enabled performance counters
++ for (int j = i + 1; j < MAX_PERFORMANCE_COUNTERS; j++) {
++ const Counter & counter2 = gSessionData->mCounters[j];
++ if (counter2.isEnabled()) {
++ // check if the types are the same
++ if (strcmp(counter.getType(), counter2.getType()) == 0) {
++ logg->logError(__FILE__, __LINE__, "Duplicate performance counter type in configuration.xml: %s", counter.getType());
++ handleException();
++ }
++ }
++ }
++ }
++ }
++}
++
++#define CONFIGURATION_REVISION 3
++int ConfigurationXML::configurationsTag(mxml_node_t *node) {
++ const char* revision_string;
++
++ revision_string = mxmlElementGetAttr(node, ATTR_REVISION);
++ if (!revision_string) {
++ return 1; //revision issue;
++ }
++
++ int revision = strtol(revision_string, NULL, 10);
++ if (revision < CONFIGURATION_REVISION) {
++ return 1; // revision issue
++ }
++
++ // A revision >= CONFIGURATION_REVISION is okay
++ // Greater than can occur when Streamline is newer than gator
++
++ return 0;
++}
++
++void ConfigurationXML::configurationTag(mxml_node_t *node) {
++ // handle all other performance counters
++ if (mIndex >= MAX_PERFORMANCE_COUNTERS) {
++ mIndex++;
++ gSessionData->mCounterOverflow = mIndex;
++ return;
++ }
++
++ // read attributes
++ Counter & counter = gSessionData->mCounters[mIndex];
++ counter.clear();
++ if (mxmlElementGetAttr(node, ATTR_COUNTER)) counter.setType(mxmlElementGetAttr(node, ATTR_COUNTER));
++ if (mxmlElementGetAttr(node, ATTR_EVENT)) counter.setEvent(strtol(mxmlElementGetAttr(node, ATTR_EVENT), NULL, 16));
++ if (mxmlElementGetAttr(node, ATTR_COUNT)) counter.setCount(strtol(mxmlElementGetAttr(node, ATTR_COUNT), NULL, 10));
++ counter.setEnabled(true);
++
++ // Associate a driver with each counter
++ for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
++ if (driver->claimCounter(counter)) {
++ if (counter.getDriver() != NULL) {
++ logg->logError(__FILE__, __LINE__, "More than one driver has claimed %s:%i", counter.getType(), counter.getEvent());
++ handleException();
++ }
++ counter.setDriver(driver);
++ }
++ }
++
++ // If no driver is associated with the counter, disable it
++ if (counter.getDriver() == NULL) {
++ logg->logMessage("No driver has claimed %s:%i", counter.getType(), counter.getEvent());
++ counter.setEnabled(false);
++ }
++
++ if (counter.isEnabled()) {
++ // update counter index
++ mIndex++;
++ }
++}
++
++void ConfigurationXML::getDefaultConfigurationXml(const char * & xml, unsigned int & len) {
++#include "configuration_xml.h" // defines and initializes char configuration_xml[] and int configuration_xml_len
++ xml = (const char *)configuration_xml;
++ len = configuration_xml_len;
++}
++
++void ConfigurationXML::getPath(char* path) {
++ if (gSessionData->mConfigurationXMLPath) {
++ strncpy(path, gSessionData->mConfigurationXMLPath, PATH_MAX);
++ } else {
++ if (util->getApplicationFullPath(path, PATH_MAX) != 0) {
++ logg->logMessage("Unable to determine the full path of gatord, the cwd will be used");
++ }
++ strncat(path, "configuration.xml", PATH_MAX - strlen(path) - 1);
++ }
++}
++
++void ConfigurationXML::remove() {
++ char path[PATH_MAX];
++ getPath(path);
++
++ if (::remove(path) != 0) {
++ logg->logError(__FILE__, __LINE__, "Invalid configuration.xml file detected and unable to delete it. To resolve, delete configuration.xml on disk");
++ handleException();
++ }
++ logg->logMessage("Invalid configuration.xml file detected and removed");
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/ConfigurationXML.h linux-linaro-stable-mx6/tools/gator/daemon/ConfigurationXML.h
+--- linux-3.10.30.orig/tools/gator/daemon/ConfigurationXML.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/ConfigurationXML.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,38 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef COUNTERS_H
++#define COUNTERS_H
++
++#include "mxml/mxml.h"
++
++class ConfigurationXML {
++public:
++ static void getDefaultConfigurationXml(const char * & xml, unsigned int & len);
++ static void getPath(char* path);
++ static void remove();
++
++ ConfigurationXML();
++ ~ConfigurationXML();
++ const char* getConfigurationXML() {return mConfigurationXML;}
++ void validate(void);
++
++private:
++ char* mConfigurationXML;
++ int mIndex;
++
++ int parse(const char* xmlFile);
++ int configurationsTag(mxml_node_t *node);
++ void configurationTag(mxml_node_t *node);
++
++ // Intentionally unimplemented
++ ConfigurationXML(const ConfigurationXML &);
++ ConfigurationXML &operator=(const ConfigurationXML &);
++};
++
++#endif // COUNTERS_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Counter.h linux-linaro-stable-mx6/tools/gator/daemon/Counter.h
+--- linux-3.10.30.orig/tools/gator/daemon/Counter.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Counter.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,61 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef COUNTER_H
++#define COUNTER_H
++
++#include <string.h>
++
++class Driver;
++
++class Counter {
++public:
++ static const size_t MAX_STRING_LEN = 80;
++ static const size_t MAX_DESCRIPTION_LEN = 400;
++
++ Counter () {
++ clear();
++ }
++
++ void clear () {
++ mType[0] = '\0';
++ mEnabled = false;
++ mEvent = 0;
++ mCount = 0;
++ mKey = 0;
++ mDriver = NULL;
++ }
++
++ void setType(const char *const type) { strncpy(mType, type, sizeof(mType)); mType[sizeof(mType) - 1] = '\0'; }
++ void setEnabled(const bool enabled) { mEnabled = enabled; }
++ void setEvent(const int event) { mEvent = event; }
++ void setCount(const int count) { mCount = count; }
++ void setKey(const int key) { mKey = key; }
++ void setDriver(Driver *const driver) { mDriver = driver; }
++
++ const char *getType() const { return mType;}
++ bool isEnabled() const { return mEnabled; }
++ int getEvent() const { return mEvent; }
++ int getCount() const { return mCount; }
++ int getKey() const { return mKey; }
++ Driver *getDriver() const { return mDriver; }
++
++private:
++ // Intentionally unimplemented
++ Counter(const Counter &);
++ Counter & operator=(const Counter &);
++
++ char mType[MAX_STRING_LEN];
++ bool mEnabled;
++ int mEvent;
++ int mCount;
++ int mKey;
++ Driver *mDriver;
++};
++
++#endif // COUNTER_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Driver.cpp linux-linaro-stable-mx6/tools/gator/daemon/Driver.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/Driver.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Driver.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,15 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "Driver.h"
++
++Driver *Driver::head = NULL;
++
++Driver::Driver() : next(head) {
++ head = this;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Driver.h linux-linaro-stable-mx6/tools/gator/daemon/Driver.h
+--- linux-3.10.30.orig/tools/gator/daemon/Driver.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Driver.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,48 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef DRIVER_H
++#define DRIVER_H
++
++#include "mxml/mxml.h"
++
++class Counter;
++
++class Driver {
++public:
++ static Driver *getHead() { return head; }
++
++ virtual ~Driver() {}
++
++ // Returns true if this driver can manage the counter
++ virtual bool claimCounter(const Counter &counter) const = 0;
++ // Clears and disables all counters
++ virtual void resetCounters() = 0;
++ // Enables and prepares the counter for capture
++ virtual void setupCounter(Counter &counter) = 0;
++
++ // Emits available counters
++ virtual void writeCounters(mxml_node_t *root) const = 0;
++ // Emits possible dynamically generated events/counters
++ virtual void writeEvents(mxml_node_t *) const {}
++
++ Driver *getNext() const { return next; }
++
++protected:
++ Driver ();
++
++private:
++ static Driver *head;
++ Driver *next;
++
++ // Intentionally unimplemented
++ Driver(const Driver &);
++ Driver &operator=(const Driver &);
++};
++
++#endif // DRIVER_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/escape.c linux-linaro-stable-mx6/tools/gator/daemon/escape.c
+--- linux-3.10.30.orig/tools/gator/daemon/escape.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/escape.c 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,75 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/*
++ * The Makefile in the daemon folder builds and executes 'escape'
++ * 'escape' creates configuration_xml.h from configuration.xml and events_xml.h from events-*.xml
++ * these genereated xml files are then #included and built as part of the gatord binary
++ */
++
++#include <errno.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++#include <ctype.h>
++
++static void print_escaped_path(char *path) {
++ if (isdigit(*path)) {
++ printf("__");
++ }
++ for (; *path != '\0'; ++path) {
++ printf("%c", isalnum(*path) ? *path : '_');
++ }
++}
++
++int main(int argc, char *argv[]) {
++ int i;
++ char *path;
++ FILE *in = NULL;
++ int ch;
++ unsigned int len = 0;
++
++ for (i = 1; i < argc && argv[i][0] == '-'; ++i) ;
++ if (i == argc) {
++ fprintf(stderr, "Usage: %s <filename>\n", argv[0]);
++ return EXIT_FAILURE;
++ }
++ path = argv[i];
++
++ errno = 0;
++ if ((in = fopen(path, "r")) == NULL) {
++ fprintf(stderr, "Unable to open '%s': %s\n", path, strerror(errno));
++ return EXIT_FAILURE;
++ }
++
++ printf("static const unsigned char ");
++ print_escaped_path(path);
++ printf("[] = {");
++ for (;;) {
++ ch = fgetc(in);
++ if (len != 0) {
++ printf(",");
++ }
++ if (len % 12 == 0) {
++ printf("\n ");
++ }
++ // Write out a null character after the contents of the file but do not increment len
++ printf(" 0x%.2x", (ch == EOF ? 0 : ch));
++ if (ch == EOF) {
++ break;
++ }
++ ++len;
++ }
++ printf("\n};\nstatic const unsigned int ");
++ print_escaped_path(path);
++ printf("_len = %i;\n", len);
++
++ fclose(in);
++
++ return EXIT_SUCCESS;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-ARM11MPCore.xml linux-linaro-stable-mx6/tools/gator/daemon/events-ARM11MPCore.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-ARM11MPCore.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-ARM11MPCore.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,26 @@
++ <counter_set name="ARM_ARM11MPCore_cnt" count="3"/>
++ <category name="ARM11MPCore" counter_set="ARM_ARM11MPCore_cnt" per_cpu="yes">
++ <event counter="ARM_ARM11MPCore_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
++ <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
++ <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
++ <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>
++ <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
++ <event event="0x05" title="Branch" name="Instruction executed" description="Branch instructions executed, branch might or might not have changed program flow"/>
++ <event event="0x06" title="Branch" name="Not predicted" description="Branch not predicted"/>
++ <event event="0x07" title="Branch" name="Mispredicted" description="Branch mispredicted"/>
++ <event event="0x08" title="Core" name="Instructions" description="Instructions executed"/>
++ <event event="0x09" title="Core" name="Folded Instructions" description="Folded instructions executed"/>
++ <event event="0x0a" title="Cache" name="Data read access" description="Data cache read access, not including cache operations"/>
++ <event event="0x0b" title="Cache" name="Data read miss" description="Data cache miss, not including Cache Operations"/>
++ <event event="0x0c" title="Cache" name="Data write access" description="Data cache write access"/>
++ <event event="0x0d" title="Cache" name="Data write miss" description="Data cache write miss"/>
++ <event event="0x0e" title="Cache" name="Data line eviction" description="Data cache line eviction, not including cache operations"/>
++ <event event="0x0f" title="Branch" name="PC change w/o mode change" description="Software changed the PC and there is not a mode change"/>
++ <event event="0x10" title="Cache " name="TLB miss" description="Main TLB miss"/>
++ <event event="0x11" title="External" name="External Memory request" description="External memory request (cache refill, noncachable, write-back)"/>
++ <event event="0x12" title="Cache" name="Stall" description="Stall because of Load Store Unit request queue being full"/>
++ <event event="0x13" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of LSU ordering constraints or CP15 operations (Data Synchronization Barrier command) or Strongly Ordered operation"/>
++ <event event="0x14" title="Write Buffer" name="Write Merges" description="Buffered write merged in a store buffer slot"/>
++ <event event="0xFF" title="Core" name="Cycle counter" description="An increment each cycle"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-ARM11.xml linux-linaro-stable-mx6/tools/gator/daemon/events-ARM11.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-ARM11.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-ARM11.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,39 @@
++ <counter_set name="ARM_ARM11_cnt" count="3"/>
++ <category name="ARM11" counter_set="ARM_ARM11_cnt" per_cpu="yes">
++ <event counter="ARM_ARM11_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Cache" name="Inst miss" description="Instruction cache miss to a cacheable location, which requires a fetch from external memory"/>
++ <event event="0x01" title="Pipeline" name="Instruction stall" description="Stall because instruction buffer cannot deliver an instruction"/>
++ <event event="0x02" title="Pipeline" name="Data stall" description="Stall because of a data dependency"/>
++ <event event="0x03" title="Cache" name="Inst micro TLB miss" description="Instruction MicroTLB miss (unused on ARM1156)"/>
++ <event event="0x04" title="Cache" name="Data micro TLB miss" description="Data MicroTLB miss (unused on ARM1156)"/>
++ <event event="0x05" title="Branch" name="Instruction executed" description="Branch instruction executed, branch might or might not have changed program flow"/>
++ <event event="0x06" title="Branch" name="Mispredicted" description="Branch mis-predicted"/>
++ <event event="0x07" title="Instruction" name="Executed" description="Instructions executed"/>
++ <event event="0x09" title="Cache" name="Data access" description="Data cache access, not including Cache operations"/>
++ <event event="0x0a" title="Cache" name="Data all access" description="Data cache access, not including Cache Operations regardless of whether or not the location is cacheable"/>
++ <event event="0x0b" title="Cache" name="Data miss" description="Data cache miss, not including Cache Operations"/>
++ <event event="0x0c" title="Cache" name="Write-back" description="Data cache write-back"/>
++ <event event="0x0d" title="Program Counter" name="SW change" description="Software changed the PC"/>
++ <event event="0x0f" title="Cache " name="TLB miss" description="Main TLB miss (unused on ARM1156)"/>
++ <event event="0x10" title="External" name="Access" description="Explicit external data or peripheral access"/>
++ <event event="0x11" title="Cache" name="Data miss" description="Stall because of Load Store Unit request queue being full"/>
++ <event event="0x12" title="Write Buffer" name="Drains" description="The number of times the Write Buffer was drained because of a Data Synchronization Barrier command or Strongly Ordered operation"/>
++ <event event="0x13" title="Disable Interrupts" name="FIQ" description="The number of cycles which FIQ interrupts are disabled (ARM1156 only)"/>
++ <event event="0x14" title="Disable Interrupts" name="IRQ" description="The number of cycles which IRQ interrupts are disabled (ARM1156 only)"/>
++ <event event="0x20" title="ETM" name="ETMEXTOUT[0]" description="ETMEXTOUT[0] signal was asserted for a cycle"/>
++ <event event="0x21" title="ETM" name="ETMEXTOUT[1]" description="ETMEXTOUT[1] signal was asserted for a cycle"/>
++ <event event="0x22" title="ETM" name="ETMEXTOUT[0,1]" description="ETMEXTOUT[0] or ETMEXTOUT[1] was asserted"/>
++ <event event="0x23" title="Procedure" name="Calls" description="Procedure call instruction executed"/>
++ <event event="0x24" title="Procedure" name="Returns" description="Procedure return instruction executed"/>
++ <event event="0x25" title="Procedure" name="Return and predicted" description="Procedure return instruction executed and return address predicted"/>
++ <event event="0x26" title="Procedure" name="Return and mispredicted" description="Procedure return instruction executed and return address predicted incorrectly"/>
++ <event event="0x30" title="Cache" name="Inst tag or parity error" description="Instruction cache Tag or Valid RAM parity error (ARM1156 only)"/>
++ <event event="0x31" title="Cache" name="Inst parity error" description="Instruction cache RAM parity error (ARM1156 only)"/>
++ <event event="0x32" title="Cache" name="Data tag or parity error" description="Data cache Tag or Valid RAM parity error (ARM1156 only)"/>
++ <event event="0x33" title="Cache" name="Data parity error" description="Data cache RAM parity error (ARM1156 only)"/>
++ <event event="0x34" title="ITCM" name="Error" description="ITCM error (ARM1156 only)"/>
++ <event event="0x35" title="DTCM" name="Error" description="DTCM error (ARM1156 only)"/>
++ <event event="0x36" title="Procedure" name="Return address pop" description="Procedure return address popped off the return stack (ARM1156 only)"/>
++ <event event="0x37" title="Procedure" name="Return address misprediction" description="Procedure return address popped off the return stack has been incorrectly predicted by the PFU (ARM1156 only)"/>
++ <event event="0x38" title="Cache" name="Data dirty parity error" description="Data cache Dirty RAM parity error (ARM1156 only)"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-CCI-400.xml linux-linaro-stable-mx6/tools/gator/daemon/events-CCI-400.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-CCI-400.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-CCI-400.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,107 @@
++ <counter_set name="cci-400_cnt" count="4"/>
++ <category name="CCI-400" counter_set="cci-400_cnt" per_cpu="no" supports_event_based_sampling="yes">
++ <event counter="cci-400_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
++
++ <option_set name="Slave">
++ <option event_delta="0x00" name="S0" description="Slave interface 0"/>
++ <option event_delta="0x20" name="S1" description="Slave interface 1"/>
++ <option event_delta="0x40" name="S2" description="Slave interface 2"/>
++ <option event_delta="0x60" name="S3" description="Slave interface 3"/>
++ <option event_delta="0x80" name="S4" description="Slave interface 4"/>
++ </option_set>
++
++ <event event="0x00" option_set="Slave" title="CCI-400" name="Read: any" description="Read request handshake: any"/>
++ <event event="0x01" option_set="Slave" title="CCI-400" name="Read: transaction" description="Read request handshake: device transaction"/>
++ <event event="0x02" option_set="Slave" title="CCI-400" name="Read: normal" description="Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation"/>
++ <event event="0x03" option_set="Slave" title="CCI-400" name="Read: shareable" description="Read request handshake: inner- or outer-shareable, but not barrier, DVM message or cache maintenance operation"/>
++ <event event="0x04" option_set="Slave" title="CCI-400" name="Read: cache" description="Read request handshake: cache maintenance operation, CleanInvalid, CleanShared, MakeInvalid"/>
++ <event event="0x05" option_set="Slave" title="CCI-400" name="Read: memory barrier" description="Read request handshake: memory barrier"/>
++ <event event="0x06" option_set="Slave" title="CCI-400" name="Read: sync barrier" description="Read request handshake: synchronization barrier"/>
++ <event event="0x07" option_set="Slave" title="CCI-400" name="Read: DVM message, no sync" description="Read request handshake: DVM message, not synchronization"/>
++ <event event="0x08" option_set="Slave" title="CCI-400" name="Read: DVM message, sync" description="Read request handshake: DVM message, synchronization"/>
++ <event event="0x09" option_set="Slave" title="CCI-400" name="Read: stall" description="Read request stall cycle because the transaction tracker is full. Increase SIx_R_MAX to avoid this stall"/>
++ <event event="0x0a" option_set="Slave" title="CCI-400" name="Read data last handshake" description="Read data last handshake: data returned from the snoop instead of from downstream"/>
++ <event event="0x0b" option_set="Slave" title="CCI-400" name="Read data stall cycle" description="Read data stall cycle: RVALIDS is HIGH, RREADYS is LOW"/>
++ <event event="0x0c" option_set="Slave" title="CCI-400" name="Write: any" description="Write request handshake: any"/>
++ <event event="0x0d" option_set="Slave" title="CCI-400" name="Write: transaction" description="Write request handshake: device transaction"/>
++ <event event="0x0e" option_set="Slave" title="CCI-400" name="Write: normal" description="Write request handshake: normal, non-shareable, or system-shareable, but not barrier"/>
++ <event event="0x0f" option_set="Slave" title="CCI-400" name="Write: shareable" description="Write request handshake: inner- or outer-shareable, WriteBack or WriteClean"/>
++ <event event="0x10" option_set="Slave" title="CCI-400" name="Write: WriteUnique" description="Write request handshake: WriteUnique"/>
++ <event event="0x11" option_set="Slave" title="CCI-400" name="Write: WriteLineUnique" description="Write request handshake: WriteLineUnique"/>
++ <event event="0x12" option_set="Slave" title="CCI-400" name="Write: Evict" description="Write request handshake: Evict"/>
++ <event event="0x13" option_set="Slave" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall"/>
++
++ <option_set name="Master">
++ <option event_delta="0xa0" name="M0" description="Master interface 0"/>
++ <option event_delta="0xc0" name="M1" description="Master interface 1"/>
++ <option event_delta="0xe0" name="M2" description="Master interface 2"/>
++ </option_set>
++
++ <event event="0x14" option_set="Master" title="CCI-400" name="Retry fetch" description="RETRY of speculative fetch transaction"/>
++ <event event="0x15" option_set="Master" title="CCI-400" name="Read stall: address hazard" description="Read request stall cycle because of an address hazard"/>
++ <event event="0x16" option_set="Master" title="CCI-400" name="Read stall: ID hazard" description="Read request stall cycle because of an ID hazard"/>
++ <event event="0x17" option_set="Master" title="CCI-400" name="Read stall: tracker full" description="Read request stall cycle because the transaction tracker is full. Increase MIx_R_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual"/>
++ <event event="0x18" option_set="Master" title="CCI-400" name="Read stall: barrier hazard" description="Read request stall cycle because of a barrier hazard"/>
++ <event event="0x19" option_set="Master" title="CCI-400" name="Write stall: barrier hazard" description="Write request stall cycle because of a barrier hazard"/>
++ <event event="0x1a" option_set="Master" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase MIx_W_MAX to avoid this stall. See the CoreLink CCI-400 Cache Coherent Interconnect Integration Manual"/>
++ </category>
++
++ <counter_set name="cci-400-r1_cnt" count="4"/>
++ <category name="CCI-400" counter_set="cci-400-r1_cnt" per_cpu="no" supports_event_based_sampling="yes">
++ <event counter="cci-400-r1_ccnt" event="0xff" title="CCI-400 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
++
++ <option_set name="Slave">
++ <option event_delta="0x00" name="S0" description="Slave interface 0"/>
++ <option event_delta="0x20" name="S1" description="Slave interface 1"/>
++ <option event_delta="0x40" name="S2" description="Slave interface 2"/>
++ <option event_delta="0x60" name="S3" description="Slave interface 3"/>
++ <option event_delta="0x80" name="S4" description="Slave interface 4"/>
++ </option_set>
++
++ <event event="0x00" option_set="Slave" title="CCI-400" name="Read: any" description="Read request handshake: any"/>
++ <event event="0x01" option_set="Slave" title="CCI-400" name="Read: transaction" description="Read request handshake: device transaction"/>
++ <event event="0x02" option_set="Slave" title="CCI-400" name="Read: normal" description="Read request handshake: normal, non-shareable or system-shareable, but not barrier or cache maintenance operation"/>
++ <event event="0x03" option_set="Slave" title="CCI-400" name="Read: shareable" description="Read request handshake: inner- or outer-shareable, but not barrier, DVM message or cache maintenance operation"/>
++ <event event="0x04" option_set="Slave" title="CCI-400" name="Read: cache" description="Read request handshake: cache maintenance operation"/>
++ <event event="0x05" option_set="Slave" title="CCI-400" name="Read: memory barrier" description="Read request handshake: memory barrier"/>
++ <event event="0x06" option_set="Slave" title="CCI-400" name="Read: sync barrier" description="Read request handshake: synchronization barrier"/>
++ <event event="0x07" option_set="Slave" title="CCI-400" name="Read: DVM message, no sync" description="Read request handshake: DVM message, not synchronization"/>
++ <event event="0x08" option_set="Slave" title="CCI-400" name="Read: DVM message, sync" description="Read request handshake: DVM message, synchronization"/>
++ <event event="0x09" option_set="Slave" title="CCI-400" name="Read: stall" description="Read request stall cycle because the transaction tracker is full. Increase SIx_R_MAX to avoid this stall"/>
++ <event event="0x0a" option_set="Slave" title="CCI-400" name="Read data last handshake" description="Read data last handshake: data returned from the snoop instead of from downstream"/>
++ <event event="0x0b" option_set="Slave" title="CCI-400" name="Read data stall cycle" description="Read data stall cycle: RVALIDS is HIGH, RREADYS is LOW"/>
++ <event event="0x0c" option_set="Slave" title="CCI-400" name="Write: any" description="Write request handshake: any"/>
++ <event event="0x0d" option_set="Slave" title="CCI-400" name="Write: transaction" description="Write request handshake: device transaction"/>
++ <event event="0x0e" option_set="Slave" title="CCI-400" name="Write: normal" description="Write request handshake: normal, non-shareable, or system-shareable, but not barrier"/>
++ <event event="0x0f" option_set="Slave" title="CCI-400" name="Write: shareable" description="Write request handshake: inner- or outer-shareable, WriteBack or WriteClean"/>
++ <event event="0x10" option_set="Slave" title="CCI-400" name="Write: WriteUnique" description="Write request handshake: WriteUnique"/>
++ <event event="0x11" option_set="Slave" title="CCI-400" name="Write: WriteLineUnique" description="Write request handshake: WriteLineUnique"/>
++ <event event="0x12" option_set="Slave" title="CCI-400" name="Write: Evict" description="Write request handshake: Evict"/>
++ <event event="0x13" option_set="Slave" title="CCI-400" name="Write stall: tracker full" description="Write request stall cycle because the transaction tracker is full. Increase SIx_W_MAX to avoid this stall"/>
++ <event event="0x14" option_set="Slave" title="CCI-400" name="Read stall: slave hazard" description="Read request stall cycle because of a slave interface ID hazard"/>
++
++ <option_set name="Master">
++ <option event_delta="0xa0" name="M0" description="Master interface 0"/>
++ <option event_delta="0xc0" name="M1" description="Master interface 1"/>
++ <option event_delta="0xe0" name="M2" description="Master interface 2"/>
++ </option_set>
++
++ <event event="0x00" option_set="Master" title="CCI-400" name="Retry fetch" description="RETRY of speculative fetch transaction"/>
++ <event event="0x01" option_set="Master" title="CCI-400" name="Read stall: address hazard" description="Stall cycle because of an address hazard. A read or write invalidation is stalled because of an outstanding transaction to an overlapping address"/>
++ <event event="0x02" option_set="Master" title="CCI-400" name="Read stall: ID hazard" description="Read request stall cycle because of a master interface ID hazard"/>
++ <event event="0x03" option_set="Master" title="CCI-400" name="Read stall: tracker full" description="A read request with a QoS value in the high priority group is stalled for a cycle because the read transaction queue is full. Increase MIx_R_MAX to avoid this stall"/>
++ <event event="0x04" option_set="Master" title="CCI-400" name="Read stall: barrier hazard" description="Read request stall cycle because of a barrier hazard"/>
++ <event event="0x05" option_set="Master" title="CCI-400" name="Write stall: barrier hazard" description="Write request stall cycle because of a barrier hazard"/>
++ <event event="0x06" option_set="Master" title="CCI-400" name="Write stall: tracker full" description="A write request is stalled for a cycle because the write transaction tracker is full. Increase MIx_W_MAX to avoid this stall"/>
++ <event event="0x07" option_set="Master" title="CCI-400" name="Read Stall: Low Priority" description="A read request with a QoS value in the low priority group is stalled for a cycle because there are no slots available in the read queue for the low priority group"/>
++ <event event="0x08" option_set="Master" title="CCI-400" name="Read Stall: Medium Priority" description="A read request with a QoS value in the medium priority group is stalled for a cycle because there are no slots available in the read queue for the medium priority group"/>
++ <event event="0x09" option_set="Master" title="CCI-400" name="Read Stall: VN0" description="A read request is stalled for a cycle while it was waiting for a QVN token on VN0"/>
++ <event event="0x0a" option_set="Master" title="CCI-400" name="Read Stall: VN1" description="A read request is stalled for a cycle while it was waiting for a QVN token on VN1"/>
++ <event event="0x0b" option_set="Master" title="CCI-400" name="Read Stall: VN2" description="A read request is stalled for a cycle while it was waiting for a QVN token on VN2"/>
++ <event event="0x0c" option_set="Master" title="CCI-400" name="Read Stall: VN3" description="A read request is stalled for a cycle while it was waiting for a QVN token on VN3"/>
++ <event event="0x0d" option_set="Master" title="CCI-400" name="Write Stall: VN0" description="A write request is stalled for a cycle while it was waiting for a QVN token on VN0"/>
++ <event event="0x0e" option_set="Master" title="CCI-400" name="Write Stall: VN1" description="A write request is stalled for a cycle while it was waiting for a QVN token on VN1"/>
++ <event event="0x0f" option_set="Master" title="CCI-400" name="Write Stall: VN2" description="A write request is stalled for a cycle while it was waiting for a QVN token on VN2"/>
++ <event event="0x10" option_set="Master" title="CCI-400" name="Write Stall: VN" description="A write request is stalled for a cycle while it was waiting for a QVN token on VN"/>
++ <event event="0x11" option_set="Master" title="CCI-400" name="WriteUnique or WriteLineUnique Stall" description="A WriteUnique or WriteLineUnique request is stalled for a cycle because of an address hazard"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-CCN-504.xml linux-linaro-stable-mx6/tools/gator/daemon/events-CCN-504.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-CCN-504.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-CCN-504.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,122 @@
++ <counter_set name="CCN-504_cnt" count="4"/>
++ <category name="CCN-504" counter_set="CCN-504_cnt">
++ <event counter="CCN-504_ccnt" title="CCN-504 Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" description="The number of core clock cycles"/>
++
++ <option_set name="XP_Region">
++ <option event_delta="0x400000" name="XP 0" description="Crosspoint 0"/>
++ <option event_delta="0x410000" name="XP 1" description="Crosspoint 1"/>
++ <option event_delta="0x420000" name="XP 2" description="Crosspoint 2"/>
++ <option event_delta="0x430000" name="XP 3" description="Crosspoint 3"/>
++ <option event_delta="0x440000" name="XP 4" description="Crosspoint 4"/>
++ <option event_delta="0x450000" name="XP 5" description="Crosspoint 5"/>
++ <option event_delta="0x460000" name="XP 6" description="Crosspoint 6"/>
++ <option event_delta="0x470000" name="XP 7" description="Crosspoint 7"/>
++ <option event_delta="0x480000" name="XP 8" description="Crosspoint 8"/>
++ <option event_delta="0x490000" name="XP 9" description="Crosspoint 9"/>
++ <option event_delta="0x4A0000" name="XP 10" description="Crosspoint 10"/>
++ </option_set>
++
++ <event event="0x0801" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: H-bit" description="Bus 0: REQ: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x0802" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: S-bit" description="Bus 0: REQ: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x0803" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: P-Cnt" description="Bus 0: REQ: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x0804" option_set="XP_Region" title="CCN-504" name="Bus 0: REQ: TknV" description="Bus 0: REQ: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0809" option_set="XP_Region" title="CCN-504" name="Bus 1: REQ: H-bit" description="Bus 1: REQ: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x080A" option_set="XP_Region" title="CCN-504" name="Bus 1: REQ: S-bit" description="Bus 1: REQ: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x080B" option_set="XP_Region" title="CCN-504" name="Bus 1: REQ: P-Cnt" description="Bus 1: REQ: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x080C" option_set="XP_Region" title="CCN-504" name="Bus 1: REQ: TknV" description="Bus 1: REQ: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0811" option_set="XP_Region" title="CCN-504" name="Bus 0: RSP: H-bit" description="Bus 0: RSP: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x0812" option_set="XP_Region" title="CCN-504" name="Bus 0: RSP: S-bit" description="Bus 0: RSP: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x0813" option_set="XP_Region" title="CCN-504" name="Bus 0: RSP: P-Cnt" description="Bus 0: RSP: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x0814" option_set="XP_Region" title="CCN-504" name="Bus 0: RSP: TknV" description="Bus 0: RSP: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0819" option_set="XP_Region" title="CCN-504" name="Bus 1: RSP: H-bit" description="Bus 1: RSP: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x081A" option_set="XP_Region" title="CCN-504" name="Bus 1: RSP: S-bit" description="Bus 1: RSP: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x081B" option_set="XP_Region" title="CCN-504" name="Bus 1: RSP: P-Cnt" description="Bus 1: RSP: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x081C" option_set="XP_Region" title="CCN-504" name="Bus 1: RSP: TknV" description="Bus 1: RSP: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0821" option_set="XP_Region" title="CCN-504" name="Bus 0: SNP: H-bit" description="Bus 0: SNP: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x0822" option_set="XP_Region" title="CCN-504" name="Bus 0: SNP: S-bit" description="Bus 0: SNP: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x0823" option_set="XP_Region" title="CCN-504" name="Bus 0: SNP: P-Cnt" description="Bus 0: SNP: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x0824" option_set="XP_Region" title="CCN-504" name="Bus 0: SNP: TknV" description="Bus 0: SNP: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0829" option_set="XP_Region" title="CCN-504" name="Bus 1: SNP: H-bit" description="Bus 1: SNP: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x082A" option_set="XP_Region" title="CCN-504" name="Bus 1: SNP: S-bit" description="Bus 1: SNP: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x082B" option_set="XP_Region" title="CCN-504" name="Bus 1: SNP: P-Cnt" description="Bus 1: SNP: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x082C" option_set="XP_Region" title="CCN-504" name="Bus 1: SNP: TknV" description="Bus 1: SNP: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0831" option_set="XP_Region" title="CCN-504" name="Bus 0: DAT: H-bit" description="Bus 0: DAT: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x0832" option_set="XP_Region" title="CCN-504" name="Bus 0: DAT: S-bit" description="Bus 0: DAT: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x0833" option_set="XP_Region" title="CCN-504" name="Bus 0: DAT: P-Cnt" description="Bus 0: DAT: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x0834" option_set="XP_Region" title="CCN-504" name="Bus 0: DAT: TknV" description="Bus 0: DAT: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0839" option_set="XP_Region" title="CCN-504" name="Bus 1: DAT: H-bit" description="Bus 1: DAT: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x083A" option_set="XP_Region" title="CCN-504" name="Bus 1: DAT: S-bit" description="Bus 1: DAT: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x083B" option_set="XP_Region" title="CCN-504" name="Bus 1: DAT: P-Cnt" description="Bus 1: DAT: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x083C" option_set="XP_Region" title="CCN-504" name="Bus 1: DAT: TknV" description="Bus 1: DAT: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0871" option_set="XP_Region" title="CCN-504" name="Bus 0: DATB: H-bit" description="Bus 0: DATB: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x0872" option_set="XP_Region" title="CCN-504" name="Bus 0: DATB: S-bit" description="Bus 0: DATB: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x0873" option_set="XP_Region" title="CCN-504" name="Bus 0: DATB: P-Cnt" description="Bus 0: DATB: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x0874" option_set="XP_Region" title="CCN-504" name="Bus 0: DATB: TknV" description="Bus 0: DATB: No TknV, signaled when this XP transmits a valid packet."/>
++ <event event="0x0879" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: H-bit" description="Bus 1: DATB: Set H-bit, signaled when this XP sets the H-bit."/>
++ <event event="0x087A" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: S-bit" description="Bus 1: DATB: Set S-bit, signaled when this XP sets the S-bit."/>
++ <event event="0x087B" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: P-Cnt" description="Bus 1: DATB: Set P-Cnt, signaled when this XP sets the P-Cnt. This is not applicable for the SNP VC."/>
++ <event event="0x087C" option_set="XP_Region" title="CCN-504" name="Bus 1: DATB: TknV" description="Bus 1: DATB: No TknV, signaled when this XP transmits a valid packet."/>
++
++ <option_set name="HN-F_Region">
++ <option event_delta="0x200000" name="HN-F 3" description="Fully-coherent Home Node 3"/>
++ <option event_delta="0x210000" name="HN-F 5" description="Fully-coherent Home Node 5"/>
++ <option event_delta="0x220000" name="HN-F 7" description="Fully-coherent Home Node 7"/>
++ <option event_delta="0x230000" name="HN-F 8" description="Fully-coherent Home Node 8"/>
++ <option event_delta="0x240000" name="HN-F 13" description="Fully-coherent Home Node 13"/>
++ <option event_delta="0x250000" name="HN-F 15" description="Fully-coherent Home Node 15"/>
++ <option event_delta="0x260000" name="HN-F 17" description="Fully-coherent Home Node 17"/>
++ <option event_delta="0x270000" name="HN-F 18" description="Fully-coherent Home Node 18"/>
++ </option_set>
++
++ <event event="0x0401" option_set="HN-F_Region" title="CCN-504" name="Cache Miss" description="Counts the total cache misses. This is the first time lookup result, and is high priority."/>
++ <event event="0x0402" option_set="HN-F_Region" title="CCN-504" name="L3 SF Cache Access" description="Counts the number of cache accesses. This is the first time access, and is high priority."/>
++ <event event="0x0403" option_set="HN-F_Region" title="CCN-504" name="Cache Fill" description="Counts the total allocations in the HN L3 cache, and all cache line allocations to the L3 cache."/>
++ <event event="0x0404" option_set="HN-F_Region" title="CCN-504" name="POCQ Retry" description="Counts the number of requests that have been retried."/>
++ <event event="0x0405" option_set="HN-F_Region" title="CCN-504" name="POCQ Reqs Recvd" description="Counts the number of requests received by HN."/>
++ <event event="0x0406" option_set="HN-F_Region" title="CCN-504" name="SF Hit" description="Counts the number of snoop filter hits."/>
++ <event event="0x0407" option_set="HN-F_Region" title="CCN-504" name="SF Evictions" description="Counts the number of snoop filter evictions. Cache invalidations are initiated."/>
++ <event event="0x0408" option_set="HN-F_Region" title="CCN-504" name="Snoops Sent" description="Counts the number of snoops sent. Does not differentiate between broadcast or directed snoops."/>
++ <event event="0x0409" option_set="HN-F_Region" title="CCN-504" name="Snoops Broadcast" description="Counts the number of snoop broadcasts sent."/>
++ <event event="0x040A" option_set="HN-F_Region" title="CCN-504" name="L3 Eviction" description="Counts the number of L3 evictions."/>
++ <event event="0x040B" option_set="HN-F_Region" title="CCN-504" name="L3 Fill Invalid Way" description="Counts the number of L3 fills to an invalid way."/>
++ <event event="0x040C" option_set="HN-F_Region" title="CCN-504" name="MC Retries" description="Counts the number of transactions retried by the memory controller."/>
++ <event event="0x040D" option_set="HN-F_Region" title="CCN-504" name="MC Reqs" description="Counts the number of requests to the memory controller."/>
++ <event event="0x040E" option_set="HN-F_Region" title="CCN-504" name="QOS HH Retry" description="Counts the number of times a highest-priority QoS class was retried at the HN-F."/>
++
++ <option_set name="RN-I_Region">
++ <option event_delta="0x800000" name="RN-I 0" description="I/O-coherent Requesting Node 0"/>
++ <option event_delta="0x820000" name="RN-I 2" description="I/O-coherent Requesting Node 2"/>
++ <option event_delta="0x860000" name="RN-I 6" description="I/O-coherent Requesting Node 6"/>
++ <option event_delta="0x8C0000" name="RN-I 12" description="I/O-coherent Requesting Node 12"/>
++ <option event_delta="0x900000" name="RN-I 16" description="I/O-coherent Requesting Node 16"/>
++ <option event_delta="0x940000" name="RN-I 20" description="I/O-coherent Requesting Node 20"/>
++ </option_set>
++
++ <event event="0x1601" option_set="RN-I_Region" title="CCN-504" name="S0 RDataBeats" description="S0 RDataBeats."/>
++ <event event="0x1602" option_set="RN-I_Region" title="CCN-504" name="S1 RDataBeats" description="S1 RDataBeats."/>
++ <event event="0x1603" option_set="RN-I_Region" title="CCN-504" name="S2 RDataBeats" description="S2 RDataBeats."/>
++ <event event="0x1604" option_set="RN-I_Region" title="CCN-504" name="RXDAT Flits received" description="RXDAT Flits received."/>
++ <event event="0x1605" option_set="RN-I_Region" title="CCN-504" name="TXDAT Flits sent" description="TXDAT Flits sent."/>
++ <event event="0x1606" option_set="RN-I_Region" title="CCN-504" name="Total TXREQ Flits sent" description="Total TXREQ Flits sent."/>
++ <event event="0x1607" option_set="RN-I_Region" title="CCN-504" name="Retried TXREQ Flits sent" description="Retried TXREQ Flits sent."/>
++ <event event="0x1608" option_set="RN-I_Region" title="CCN-504" name="RRT full" description="RRT full."/>
++ <event event="0x1609" option_set="RN-I_Region" title="CCN-504" name="WRT full" description="WRT full."/>
++ <event event="0x160A" option_set="RN-I_Region" title="CCN-504" name="Replayed TXREQ Flits" description="Replayed TXREQ Flits."/>
++
++ <option_set name="SBAS_Region">
++ <option event_delta="0x810000" name="SBAS 1" description="ACE master to CHI protocol bridge 1"/>
++ <option event_delta="0x890000" name="SBAS 9" description="ACE master to CHI protocol bridge 9"/>
++ <option event_delta="0x8B0000" name="SBAS 11" description="ACE master to CHI protocol bridge 11"/>
++ <option event_delta="0x930000" name="SBAS 19" description="ACE master to CHI protocol bridge 19"/>
++ </option_set>
++
++ <event event="0x1001" option_set="SBAS_Region" title="CCN-504" name="S0 RDataBeats" description="S0 RDataBeats."/>
++ <event event="0x1004" option_set="SBAS_Region" title="CCN-504" name="RXDAT Flits received" description="RXDAT Flits received."/>
++ <event event="0x1005" option_set="SBAS_Region" title="CCN-504" name="TXDAT Flits sent" description="TXDAT Flits sent."/>
++ <event event="0x1006" option_set="SBAS_Region" title="CCN-504" name="Total TXREQ Flits sent" description="Total TXREQ Flits sent."/>
++ <event event="0x1007" option_set="SBAS_Region" title="CCN-504" name="Retried TXREQ Flits sent" description="Retried TXREQ Flits sent."/>
++ <event event="0x1008" option_set="SBAS_Region" title="CCN-504" name="RRT full" description="RRT full."/>
++ <event event="0x1009" option_set="SBAS_Region" title="CCN-504" name="WRT full" description="WRT full."/>
++ <event event="0x100A" option_set="SBAS_Region" title="CCN-504" name="Replayed TXREQ Flits" description="Replayed TXREQ Flits."/>
++
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A12.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A12.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A12.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A12.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,86 @@
++ <counter_set name="ARM_Cortex-A12_cnt" count="6"/>
++ <category name="Cortex-A12" counter_set="ARM_Cortex-A12_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="ARM_Cortex-A12_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
++ <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
++ <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
++ <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
++ <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
++ <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
++ <event event="0x19" title="Bus" name="Access" description="Bus - Access"/>
++ <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>
++ <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>
++ <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/>
++ <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
++ <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
++ <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
++ <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
++ <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>
++ <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>
++ <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
++ <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
++ <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
++ <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
++ <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
++ <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
++ <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
++ <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
++ <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
++ <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
++ <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>
++ <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>
++ <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>
++ <event event="0x6f" title="Intrinsic" name="STREX" description="Exclusive instruction speculatively executed - STREX"/>
++ <event event="0x70" title="Instruction" name="Load" description="Instruction speculatively executed - Load"/>
++ <event event="0x71" title="Instruction" name="Store" description="Instruction speculatively executed - Store"/>
++ <event event="0x72" title="Instruction" name="Load/Store" description="Instruction speculatively executed - Load or store"/>
++ <event event="0x73" title="Instruction" name="Integer" description="Instruction speculatively executed - Integer data processing"/>
++ <event event="0x74" title="Instruction" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>
++ <event event="0x75" title="Instruction" name="VFP" description="Instruction speculatively executed - VFP"/>
++ <event event="0x76" title="Instruction" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>
++ <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
++ <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
++ <event event="0x7a" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
++ <event event="0x7c" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
++ <event event="0x7d" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
++ <event event="0x7e" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
++ <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
++ <event event="0x8a" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
++ <event event="0xc0" title="Instruction" name="Stalled Linefill" description="Instruction side stalled due to a Linefill"/>
++ <event event="0xc1" title="Instruction" name="Stalled Page Table Walk" description="Instruction Side stalled due to a Page Table Walk"/>
++ <event event="0xc2" title="Cache" name="4 Ways Read" description="Number of set of 4 ways read in the instruction cache - Tag RAM"/>
++ <event event="0xc3" title="Cache" name="Ways Read" description="Number of ways read in the instruction cache - Data RAM"/>
++ <event event="0xc4" title="Cache" name="BATC Read" description="Number of ways read in the instruction BTAC RAM"/>
++ <event event="0xca" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local Cortex-A12 cluster, rather than accessing the L2 cache or issuing an external read. It increments on each transaction, rather than on each beat of data"/>
++ <event event="0xd3" title="Slots" name="Load-Store Unit" description="Duration during which all slots in the Load-Store Unit are busy"/>
++ <event event="0xd8" title="Slots" name="Load-Store Issue Queue" description="Duration during which all slots in the Load-Store Issue queue are busy"/>
++ <event event="0xd9" title="Slots" name="Data Processing Issue Queue" description="Duration during which all slots in the Data Processing issue queue are busy"/>
++ <event event="0xda" title="Slots" name="Data Engine Issue Queue" description="Duration during which all slots in the Data Engine issue queue are busy"/>
++ <event event="0xdb" title="NEON" name="Flush" description="Number of NEON instruction which fail their condition code and lead to a flush of the DE pipe"/>
++ <event event="0xdc" title="Hypervisor" name="Traps" description="Number of Trap to hypervisor"/>
++ <event event="0xde" title="PTM" name="EXTOUT 0" description="PTM EXTOUT 0"/>
++ <event event="0xdf" title="PTM" name="EXTOUT 1" description="PTM EXTOUT 1"/>
++ <event event="0xe0" title="MMU" name="Table Walk" description="Duration during which the MMU handle a Page table walk"/>
++ <event event="0xe1" title="MMU" name="Stage1 Table Walk" description="Duration during which the MMU handle a Stage1 Page table walk"/>
++ <event event="0xe2" title="MMU" name="Stage2 Table Walk" description="Duration during which the MMU handle a Stage2 Page table walk"/>
++ <event event="0xe3" title="MMU" name="LSU Table Walk" description="Duration during which the MMU handle a Page table walk requested by the Load Store Unit"/>
++ <event event="0xe4" title="MMU" name="Instruction Table Walk" description="Duration during which the MMU handle a Page table walk requested by the Instruction side"/>
++ <event event="0xe5" title="MMU" name="Preload Table Walk" description="Duration during which the MMU handle a Page table walk requested by a Preload instruction or Prefetch request"/>
++ <event event="0xe6" title="MMU" name="cp15 Table Walk" description="Duration during which the MMU handle a Page table walk requested by a cp15 operation (maintenance by MVA and VA-to-PA operation)"/>
++ <event event="0xe7" title="Cache" name="L1 PLD TLB refill" description="Level 1 PLD TLB refill"/>
++ <event event="0xe8" title="Cache" name="L1 CP15 TLB refill" description="Level 1 CP15 TLB refill"/>
++ <event event="0xe9" title="Cache" name="L1 TLB flush" description="Level 1 TLB flush"/>
++ <event event="0xea" title="Cache" name="L2 TLB access" description="Level 2 TLB access"/>
++ <event event="0xeb" title="Cache" name="L2 TLB miss" description="Level 2 TLB miss"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A15.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A15.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A15.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A15.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,68 @@
++ <counter_set name="ARM_Cortex-A15_cnt" count="6"/>
++ <category name="Cortex-A15" counter_set="ARM_Cortex-A15_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="ARM_Cortex-A15_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
++ <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
++ <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
++ <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
++ <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
++ <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
++ <event event="0x19" title="Bus" name="Access" description="Bus - Access"/>
++ <event event="0x1a" title="Memory" name="Error" description="Local memory error"/>
++ <event event="0x1b" title="Instruction" name="Speculative" description="Instruction speculatively executed"/>
++ <event event="0x1c" title="Memory" name="Translation table" description="Write to translation table base architecturally executed"/>
++ <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/>
++ <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
++ <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
++ <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
++ <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
++ <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-Back - Victim"/>
++ <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-Back - Cleaning and coherency"/>
++ <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
++ <event event="0x4c" title="TLB" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
++ <event event="0x4d" title="TLB" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
++ <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
++ <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
++ <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
++ <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
++ <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-Back - Victim"/>
++ <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-Back - Cleaning and coherency"/>
++ <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
++ <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
++ <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
++ <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
++ <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
++ <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
++ <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
++ <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
++ <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
++ <event event="0x6a" title="Memory" name="Unaligned" description="Unaligned access"/>
++ <event event="0x6c" title="Intrinsic" name="LDREX" description="Exclusive instruction speculatively executed - LDREX"/>
++ <event event="0x6d" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
++ <event event="0x6e" title="Intrinsic" name="STREX fail" description="Exclusive instruction speculatively executed - STREX fail"/>
++ <event event="0x70" title="Instruction" name="Load" description="Instruction speculatively executed - Load"/>
++ <event event="0x71" title="Instruction" name="Store" description="Instruction speculatively executed - Store"/>
++ <event event="0x72" title="Instruction" name="Load/Store" description="Instruction speculatively executed - Load or store"/>
++ <event event="0x73" title="Instruction" name="Integer" description="Instruction speculatively executed - Integer data processing"/>
++ <event event="0x74" title="Instruction" name="Advanced SIMD" description="Instruction speculatively executed - Advanced SIMD"/>
++ <event event="0x75" title="Instruction" name="VFP" description="Instruction speculatively executed - VFP"/>
++ <event event="0x76" title="Instruction" name="Software change" description="Instruction speculatively executed - Software change of the PC"/>
++ <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
++ <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
++ <event event="0x7a" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
++ <event event="0x7c" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
++ <event event="0x7d" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
++ <event event="0x7e" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A53.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A53.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A53.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A53.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,171 @@
++ <counter_set name="ARM_Cortex-A53_cnt" count="6"/>
++ <category name="Cortex-A53" counter_set="ARM_Cortex-A53_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <!-- 0x11 CPU_CYCLES - Cycle -->
++ <event counter="ARM_Cortex-A53_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
++ <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
++ <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <!-- 0x02 L1I_TLB_REFILL - Level 1 instruction TLB refill -->
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <!-- 0x03 L1D_CACHE_REFILL - Level 1 data cache refill -->
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <!-- 0x04 L1D_CACHE - Level 1 data cache access -->
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <!-- 0x09 EXC_TAKEN - Exception taken -->
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <!-- 0x0B CID_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR -->
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <!-- 0x10 BR_MIS_PRED - Mispredicted or not predicted branch speculatively executed -->
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <!-- 0x13 MEM_ACCESS - Data memory access -->
++ <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
++ <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
++ <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
++ <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
++ <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
++ <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
++ <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
++ <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
++ <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
++ <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
++ <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
++ <!-- 0x19 BUS_ACCESS - Bus access -->
++ <event event="0x19" title="Bus" name="Access" description="Bus access"/>
++ <!-- 0x1A MEMORY_ERROR - Local memory error -->
++ <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
++ <!-- 0x1B INST_SPEC - Operation speculatively executed -->
++ <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
++ <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
++ <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
++ <!-- 0x1D BUS_CYCLES - Bus cycle -->
++ <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
++ <!-- 0x1E CHAIN - Odd performance counter chain mode -->
++ <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
++ <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
++ <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
++ <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
++ <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
++ <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
++ <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
++ <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
++ <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
++ <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
++ <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
++ <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
++ <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
++ <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
++ <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
++ <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
++ <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
++ <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
++ <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
++ <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
++ <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
++ <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
++ <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
++ <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
++ <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
++ <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
++ <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
++ <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
++ <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
++ <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
++ <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
++ <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
++ <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
++ <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
++ <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
++ <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
++ <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
++ <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
++ <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
++ <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
++ <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
++ <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
++ <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
++ <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
++ <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
++ <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
++ <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
++ <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
++ <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
++ <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
++ <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
++ <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
++ <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
++ <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
++ <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
++ <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
++ <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
++ <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
++ <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
++ <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
++ <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
++ <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
++ <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
++ <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
++ <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
++ <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
++ <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
++ <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
++ <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
++ <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
++ <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
++ <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
++ <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
++ <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
++ <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
++ <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
++ <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
++ <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
++ <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
++ <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
++ <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
++ <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
++ <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
++ <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
++ <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
++ <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
++ <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
++ <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
++ <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
++ <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
++ <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
++ <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
++ <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
++ <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
++ <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
++ <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
++ <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
++ <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
++ <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
++ <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
++ <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
++ <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
++ <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
++ <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
++ <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
++ <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
++ <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
++ <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
++ <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
++ <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
++ <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
++ <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
++ <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
++ <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
++ <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
++ <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
++ <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
++ <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
++ <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A57.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A57.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A57.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A57.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,171 @@
++ <counter_set name="ARM_Cortex-A57_cnt" count="6"/>
++ <category name="Cortex-A57" counter_set="ARM_Cortex-A57_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <!-- 0x11 CPU_CYCLES - Cycle -->
++ <event counter="ARM_Cortex-A57_ccnt" event="0x11" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <!-- 0x00 SW_INCR - Instruction architecturally executed (condition check pass) - Software increment -->
++ <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
++ <!-- 0x01 L1I_CACHE_REFILL - Level 1 instruction cache refill -->
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <!-- 0x02 L1I_TLB_REFILL - Level 1 instruction TLB refill -->
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <!-- 0x03 L1D_CACHE_REFILL - Level 1 data cache refill -->
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <!-- 0x04 L1D_CACHE - Level 1 data cache access -->
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <!-- 0x05 L1D_TLB_REFILL - Level 1 data TLB refill -->
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <!-- 0x08 INST_RETIRED - Instruction architecturally executed -->
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <!-- 0x09 EXC_TAKEN - Exception taken -->
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <!-- 0x0A EXC_RETURN - Instruction architecturally executed (condition check pass) - Exception return -->
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <!-- 0x0B CID_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to CONTEXTIDR -->
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <!-- 0x10 BR_MIS_PRED - Mispredicted or not predicted branch speculatively executed -->
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <!-- 0x12 BR_PRED - Predictable branch speculatively executed -->
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <!-- 0x13 MEM_ACCESS - Data memory access -->
++ <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
++ <!-- 0x14 L1I_CACHE - Level 1 instruction cache access -->
++ <event event="0x14" title="Cache" name="L1 inst access" description="Level 1 instruction cache access"/>
++ <!-- 0x15 L1D_CACHE_WB - Level 1 data cache Write-Back -->
++ <event event="0x15" title="Cache" name="L1 data write" description="Level 1 data cache Write-Back"/>
++ <!-- 0x16 L2D_CACHE - Level 2 data cache access -->
++ <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
++ <!-- 0x17 L2D_CACHE_REFILL - Level 2 data cache refill -->
++ <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
++ <!-- 0x18 L2D_CACHE_WB - Level 2 data cache Write-Back -->
++ <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
++ <!-- 0x19 BUS_ACCESS - Bus access -->
++ <event event="0x19" title="Bus" name="Access" description="Bus access"/>
++ <!-- 0x1A MEMORY_ERROR - Local memory error -->
++ <event event="0x1A" title="Memory" name="Error" description="Local memory error"/>
++ <!-- 0x1B INST_SPEC - Operation speculatively executed -->
++ <event event="0x1B" title="Instruction" name="Speculative" description="Operation speculatively executed"/>
++ <!-- 0x1C TTBR_WRITE_RETIRED - Instruction architecturally executed (condition check pass) - Write to translation table base -->
++ <event event="0x1C" title="Memory" name="Translation table" description="Instruction architecturally executed (condition check pass) - Write to translation table base"/>
++ <!-- 0x1D BUS_CYCLES - Bus cycle -->
++ <event event="0x1D" title="Bus" name="Cycle" description="Bus cycle"/>
++ <!-- 0x1E CHAIN - Odd performance counter chain mode -->
++ <event event="0x1E" title="Counter chain" name="Odd Performance" description="Odd performance counter chain mode"/>
++ <!-- 0x40 L1D_CACHE_LD - Level 1 data cache access - Read -->
++ <event event="0x40" title="Cache" name="L1 data read" description="Level 1 data cache access - Read"/>
++ <!-- 0x41 L1D_CACHE_ST - Level 1 data cache access - Write -->
++ <event event="0x41" title="Cache" name="L1 data access write" description="Level 1 data cache access - Write"/>
++ <!-- 0x42 L1D_CACHE_REFILL_LD - Level 1 data cache refill - Read -->
++ <event event="0x42" title="Cache" name="L1 data refill read" description="Level 1 data cache refill - Read"/>
++ <!-- 0x43 L1D_CACHE_REFILL_ST - Level 1 data cache refill - Write -->
++ <event event="0x43" title="Cache" name="L1 data refill write" description="Level 1 data cache refill - Write"/>
++ <!-- 0x46 L1D_CACHE_WB_VICTIM - Level 1 data cache Write-back - Victim -->
++ <event event="0x46" title="Cache" name="L1 data victim" description="Level 1 data cache Write-back - Victim"/>
++ <!-- 0x47 L1D_CACHE_WB_CLEAN - Level 1 data cache Write-back - Cleaning and coherency -->
++ <event event="0x47" title="Cache" name="L1 data clean" description="Level 1 data cache Write-back - Cleaning and coherency"/>
++ <!-- 0x48 L1D_CACHE_INVAL - Level 1 data cache invalidate -->
++ <event event="0x48" title="Cache" name="L1 data invalidate" description="Level 1 data cache invalidate"/>
++ <!-- 0x4C L1D_TLB_REFILL_LD - Level 1 data TLB refill - Read -->
++ <event event="0x4C" title="Cache" name="L1 data refill read" description="Level 1 data TLB refill - Read"/>
++ <!-- 0x4D L1D_TLB_REFILL_ST - Level 1 data TLB refill - Write -->
++ <event event="0x4D" title="Cache" name="L1 data refill write" description="Level 1 data TLB refill - Write"/>
++ <!-- 0x50 L2D_CACHE_LD - Level 2 data cache access - Read -->
++ <event event="0x50" title="Cache" name="L2 data read" description="Level 2 data cache access - Read"/>
++ <!-- 0x51 L2D_CACHE_ST - Level 2 data cache access - Write -->
++ <event event="0x51" title="Cache" name="L2 data access write" description="Level 2 data cache access - Write"/>
++ <!-- 0x52 L2D_CACHE_REFILL_LD - Level 2 data cache refill - Read -->
++ <event event="0x52" title="Cache" name="L2 data refill read" description="Level 2 data cache refill - Read"/>
++ <!-- 0x53 L2D_CACHE_REFILL_ST - Level 2 data cache refill - Write -->
++ <event event="0x53" title="Cache" name="L2 data refill write" description="Level 2 data cache refill - Write"/>
++ <!-- 0x56 L2D_CACHE_WB_VICTIM - Level 2 data cache Write-back - Victim -->
++ <event event="0x56" title="Cache" name="L2 data victim" description="Level 2 data cache Write-back - Victim"/>
++ <!-- 0x57 L2D_CACHE_WB_CLEAN - Level 2 data cache Write-back - Cleaning and coherency -->
++ <event event="0x57" title="Cache" name="L2 data clean" description="Level 2 data cache Write-back - Cleaning and coherency"/>
++ <!-- 0x58 L2D_CACHE_INVAL - Level 2 data cache invalidate -->
++ <event event="0x58" title="Cache" name="L2 data invalidate" description="Level 2 data cache invalidate"/>
++ <!-- 0x60 BUS_ACCESS_LD - Bus access - Read -->
++ <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
++ <!-- 0x61 BUS_ACCESS_ST - Bus access - Write -->
++ <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
++ <!-- 0x62 BUS_ACCESS_SHARED - Bus access - Normal -->
++ <event event="0x62" title="Bus" name="Access shared" description="Bus access - Normal"/>
++ <!-- 0x63 BUS_ACCESS_NOT_SHARED - Bus access - Not normal -->
++ <event event="0x63" title="Bus" name="Access not shared" description="Bus access - Not normal"/>
++ <!-- 0x64 BUS_ACCESS_NORMAL - Bus access - Normal -->
++ <event event="0x64" title="Bus" name="Access normal" description="Bus access - Normal"/>
++ <!-- 0x65 BUS_ACCESS_PERIPH - Bus access - Peripheral -->
++ <event event="0x65" title="Bus" name="Peripheral" description="Bus access - Peripheral"/>
++ <!-- 0x66 MEM_ACCESS_LD - Data memory access - Read -->
++ <event event="0x66" title="Memory" name="Read" description="Data memory access - Read"/>
++ <!-- 0x67 MEM_ACCESS_ST - Data memory access - Write -->
++ <event event="0x67" title="Memory" name="Write" description="Data memory access - Write"/>
++ <!-- 0x68 UNALIGNED_LD_SPEC - Unaligned access - Read -->
++ <event event="0x68" title="Memory" name="Unaligned Read" description="Unaligned access - Read"/>
++ <!-- 0x69 UNALIGNED_ST_SPEC - Unaligned access - Write -->
++ <event event="0x69" title="Memory" name="Unaligned Write" description="Unaligned access - Write"/>
++ <!-- 0x6A UNALIGNED_LDST_SPEC - Unaligned access -->
++ <event event="0x6A" title="Memory" name="Unaligned" description="Unaligned access"/>
++ <!-- 0x6C LDREX_SPEC - Exclusive operation speculatively executed - LDREX -->
++ <event event="0x6C" title="Intrinsic" name="LDREX" description="Exclusive operation speculatively executed - LDREX"/>
++ <!-- 0x6D STREX_PASS_SPEC - Exclusive instruction speculatively executed - STREX pass -->
++ <event event="0x6D" title="Intrinsic" name="STREX pass" description="Exclusive instruction speculatively executed - STREX pass"/>
++ <!-- 0x6E STREX_FAIL_SPEC - Exclusive operation speculatively executed - STREX fail -->
++ <event event="0x6E" title="Intrinsic" name="STREX fail" description="Exclusive operation speculatively executed - STREX fail"/>
++ <!-- 0x70 LD_SPEC - Operation speculatively executed - Load -->
++ <event event="0x70" title="Instruction" name="Load" description="Operation speculatively executed - Load"/>
++ <!-- 0x71 ST_SPEC - Operation speculatively executed - Store -->
++ <event event="0x71" title="Instruction" name="Store" description="Operation speculatively executed - Store"/>
++ <!-- 0x72 LDST_SPEC - Operation speculatively executed - Load or store -->
++ <event event="0x72" title="Instruction" name="Load/Store" description="Operation speculatively executed - Load or store"/>
++ <!-- 0x73 DP_SPEC - Operation speculatively executed - Integer data processing -->
++ <event event="0x73" title="Instruction" name="Integer" description="Operation speculatively executed - Integer data processing"/>
++ <!-- 0x74 ASE_SPEC - Operation speculatively executed - Advanced SIMD -->
++ <event event="0x74" title="Instruction" name="Advanced SIMD" description="Operation speculatively executed - Advanced SIMD"/>
++ <!-- 0x75 VFP_SPEC - Operation speculatively executed - VFP -->
++ <event event="0x75" title="Instruction" name="VFP" description="Operation speculatively executed - VFP"/>
++ <!-- 0x76 PC_WRITE_SPEC - Operation speculatively executed - Software change of the PC -->
++ <event event="0x76" title="Instruction" name="Software change" description="Operation speculatively executed - Software change of the PC"/>
++ <!-- 0x77 CRYPTO_SPEC - Operation speculatively executed, crypto data processing -->
++ <event event="0x77" title="Instruction" name="Crypto" description="Operation speculatively executed, crypto data processing"/>
++ <!-- 0x78 BR_IMMED_SPEC - Branch speculatively executed - Immediate branch -->
++ <event event="0x78" title="Instruction" name="Immediate branch" description="Branch speculatively executed - Immediate branch"/>
++ <!-- 0x79 BR_RETURN_SPEC - Branch speculatively executed - Procedure return -->
++ <event event="0x79" title="Instruction" name="Procedure return" description="Branch speculatively executed - Procedure return"/>
++ <!-- 0x7A BR_INDIRECT_SPEC - Branch speculatively executed - Indirect branch -->
++ <event event="0x7A" title="Instruction" name="Indirect branch" description="Branch speculatively executed - Indirect branch"/>
++ <!-- 0x7C ISB_SPEC - Barrier speculatively executed - ISB -->
++ <event event="0x7C" title="Instruction" name="ISB" description="Barrier speculatively executed - ISB"/>
++ <!-- 0x7D DSB_SPEC - Barrier speculatively executed - DSB -->
++ <event event="0x7D" title="Instruction" name="DSB" description="Barrier speculatively executed - DSB"/>
++ <!-- 0x7E DMB_SPEC - Barrier speculatively executed - DMB -->
++ <event event="0x7E" title="Instruction" name="DMB" description="Barrier speculatively executed - DMB"/>
++ <!-- 0x81 EXC_UNDEF - Exception taken, other synchronous -->
++ <event event="0x81" title="Exception" name="Undefined" description="Exception taken, other synchronous"/>
++ <!-- 0x82 EXC_SVC - Exception taken, Supervisor Call -->
++ <event event="0x82" title="Exception" name="Supervisor" description="Exception taken, Supervisor Call"/>
++ <!-- 0x83 EXC_PABORT - Exception taken, Instruction Abort -->
++ <event event="0x83" title="Exception" name="Instruction abort" description="Exception taken, Instruction Abort"/>
++ <!-- 0x84 EXC_DABORT - Exception taken, Data Abort or SError -->
++ <event event="0x84" title="Exception" name="Data abort" description="Exception taken, Data Abort or SError"/>
++ <!-- 0x86 EXC_IRQ - Exception taken, IRQ -->
++ <event event="0x86" title="Interrupts" name="IRQ" description="Exception taken, IRQ"/>
++ <!-- 0x87 EXC_FIQ - Exception taken, FIQ -->
++ <event event="0x87" title="Interrupts" name="FIQ" description="Exception taken, FIQ"/>
++ <!-- 0x88 EXC_SMC - Exception taken, Secure Monitor Call -->
++ <event event="0x88" title="Exception" name="Secure monitor call" description="Exception taken, Secure Monitor Call"/>
++ <!-- 0x8A EXC_HVC - Exception taken, Hypervisor Call -->
++ <event event="0x8A" title="Exception" name="Hypervisor call" description="Exception taken, Hypervisor Call"/>
++ <!-- 0x8B EXC_TRAP_PABORT - Exception taken, Instruction Abort not taken locally -->
++ <event event="0x8B" title="Exception" name="Instruction abort non-local" description="Exception taken, Instruction Abort not taken locally"/>
++ <!-- 0x8C EXC_TRAP_DABORT - Exception taken, Data Abort or SError not taken locally -->
++ <event event="0x8C" title="Exception" name="Data abort non-local" description="Exception taken, Data Abort or SError not taken locally"/>
++ <!-- 0x8D EXC_TRAP_OTHER - Exception taken - Other traps not taken locally -->
++ <event event="0x8D" title="Exception" name="Other non-local" description="Exception taken - Other traps not taken locally"/>
++ <!-- 0x8E EXC_TRAP_IRQ - Exception taken, IRQ not taken locally -->
++ <event event="0x8E" title="Exception" name="IRQ non-local" description="Exception taken, IRQ not taken locally"/>
++ <!-- 0x8F EXC_TRAP_FIQ - Exception taken, FIQ not taken locally -->
++ <event event="0x8F" title="Exception" name="FIQ non-local" description="Exception taken, FIQ not taken locally"/>
++ <!-- 0x90 RC_LD_SPEC - Release consistency instruction speculatively executed - Load Acquire -->
++ <event event="0x90" title="Release Consistency" name="Load" description="Release consistency instruction speculatively executed - Load Acquire"/>
++ <!-- 0x91 RC_ST_SPEC - Release consistency instruction speculatively executed - Store Release -->
++ <event event="0x91" title="Release Consistency" name="Store" description="Release consistency instruction speculatively executed - Store Release"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A5.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A5.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A5.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A5.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,36 @@
++ <counter_set name="ARM_Cortex-A5_cnt" count="2"/>
++ <category name="Cortex-A5" counter_set="ARM_Cortex-A5_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="ARM_Cortex-A5_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
++ <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
++ <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
++ <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>
++ <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
++ <event event="0x14" title="Cache" name="Instruction access" description="Instruction cache access"/>
++ <event event="0x15" title="Cache" name="Data eviction" description="Data cache eviction"/>
++ <event event="0x86" title="Interrupts" name="IRQ" description="IRQ exception taken"/>
++ <event event="0x87" title="Interrupts" name="FIQ" description="FIQ exception taken"/>
++ <event event="0xC0" title="Memory" name="External request" description="External memory request"/>
++ <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
++ <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
++ <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>
++ <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
++ <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
++ <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description="ETM - ETM Ext Out[0]"/>
++ <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description="ETM - ETM Ext Out[1]"/>
++ <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A7.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A7.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A7.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A7.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,43 @@
++ <counter_set name="ARM_Cortex-A7_cnt" count="4"/>
++ <category name="Cortex-A7" counter_set="ARM_Cortex-A7_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="ARM_Cortex-A7_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Software" name="Increment" description="Software increment architecturally executed"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x06" title="Memory" name="Data Read" description="Data read architecturally executed"/>
++ <event event="0x07" title="Memory" name="Data Write" description="Data write architecturally executed"/>
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
++ <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
++ <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <event event="0x13" title="Memory" name="Memory access" description="Data memory access"/>
++ <event event="0x14" title="Cache" name="L1 inst access" description="Instruction cache access"/>
++ <event event="0x15" title="Cache" name="L1 data eviction" description="Level 1 data cache eviction"/>
++ <event event="0x16" title="Cache" name="L2 data access" description="Level 2 data cache access"/>
++ <event event="0x17" title="Cache" name="L2 data refill" description="Level 2 data cache refill"/>
++ <event event="0x18" title="Cache" name="L2 data write" description="Level 2 data cache Write-Back"/>
++ <event event="0x19" title="Bus" name="Access" description="Bus - Access"/>
++ <event event="0x1d" title="Bus" name="Cycle" description="Bus - Cycle"/>
++ <event event="0x60" title="Bus" name="Read" description="Bus access - Read"/>
++ <event event="0x61" title="Bus" name="Write" description="Bus access - Write"/>
++ <event event="0x86" title="Exception" name="IRQ" description="IRQ exception taken"/>
++ <event event="0x87" title="Exception" name="FIQ" description="FIQ exception taken"/>
++ <event event="0xC0" title="Memory" name="External request" description="External memory request"/>
++ <event event="0xC1" title="Memory" name="Non-cacheable ext req" description="Non-cacheable external memory request"/>
++ <event event="0xC2" title="Cache" name="Linefill" description="Linefill because of prefetch"/>
++ <event event="0xC3" title="Cache" name="Linefill dropped" description="Prefetch linefill dropped"/>
++ <event event="0xC4" title="Cache" name="Allocate mode enter" description="Entering read allocate mode"/>
++ <event event="0xC5" title="Cache" name="Allocate mode" description="Read allocate mode"/>
++ <event event="0xC7" title="ETM" name="ETM Ext Out[0]" description="ETM - ETM Ext Out[0]"/>
++ <event event="0xC8" title="ETM" name="ETM Ext Out[1]" description="ETM - ETM Ext Out[1]"/>
++ <event event="0xC9" title="Instruction" name="Pipeline stall" description="Data Write operation that stalls the pipeline because the store buffer is full"/>
++ <event event="0xCA" title="Memory" name="Snoop" description="Data snooped from other processor. This event counts memory-read operations that read data from another processor within the local cluster, rather than accessing the L2 cache or issuing an external read."/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A8.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A8.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A8.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A8.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,52 @@
++ <counter_set name="ARM_Cortex-A8_cnt" count="4"/>
++ <category name="Cortex-A8" counter_set="ARM_Cortex-A8_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="ARM_Cortex-A8_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
++ <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
++ <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
++ <event event="0x0e" title="Procedure" name="Return" description="Procedure return, other than exception return, architecturally executed"/>
++ <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <event event="0x40" title="Cache" name="Write buffer full" description="Any write buffer full cycle"/>
++ <event event="0x41" title="Cache" name="L2 store" description="Any store that is merged in the L2 memory system"/>
++ <event event="0x42" title="Cache" name="Bufferable transaction" description="Any bufferable store transaction from load/store to L2 cache, excluding eviction or cast out data"/>
++ <event event="0x43" title="Cache" name="L2 access" description="Any accesses to the L2 cache"/>
++ <event event="0x44" title="Cache" name="L2 miss" description="Any cacheable miss in the L2 cache"/>
++ <event event="0x45" title="AXI" name="Read" description="The number of AXI read data transfers"/>
++ <event event="0x46" title="AXI" name="Write" description="The number of AXI write data transfers"/>
++ <event event="0x47" title="Memory" name="Replay event" description="Any replay event in the memory system"/>
++ <event event="0x48" title="Memory" name="Unaligned access replay" description="Any unaligned memory access that results in a replay"/>
++ <event event="0x49" title="Cache" name="L1 data hash miss" description="Any L1 data memory access that misses in the cache as a result of the hashing algorithm"/>
++ <event event="0x4a" title="Cache" name="L1 inst hash miss" description="Any L1 instruction memory access that misses in the cache as a result of the hashing algorithm"/>
++ <event event="0x4b" title="Cache" name="L1 page coloring" description="Any L1 data memory access in which a page coloring alias occurs"/>
++ <event event="0x4c" title="NEON" name="L1 cache hit" description="Any NEON access that hits in the L1 data cache"/>
++ <event event="0x4d" title="NEON" name="L1 cache access" description="Any NEON cacheable data accesses for L1 data cache"/>
++ <event event="0x4e" title="NEON" name="L2 cache access" description="Any L2 cache accesses as a result of a NEON memory access"/>
++ <event event="0x4f" title="NEON" name="L2 cache hit" description="Any NEON hit in the L2 cache"/>
++ <event event="0x50" title="Cache" name="L1 inst access" description="Any L1 instruction cache access, excluding CP15 cache accesses"/>
++ <event event="0x51" title="Branch" name="Return stack misprediction" description="Any return stack misprediction because of incorrect target address for a taken return stack pop"/>
++ <event event="0x52" title="Branch" name="Direction misprediction" description="Branch direction misprediction"/>
++ <event event="0x53" title="Branch" name="Taken prediction" description="Any predictable branch that is predicted to be taken"/>
++ <event event="0x54" title="Branch" name="Executed and taken prediction" description="Any predictable branch that is executed and taken"/>
++ <event event="0x55" title="Core" name="Operations issued" description="Number of operations issued, where an operation is either: an instruction or one operation in a sequence of operations that make up a multi-cycle instruction"/>
++ <event event="0x56" title="Core" name="No issue cycles" description="Increment for every cycle that no instructions are available for issue"/>
++ <event event="0x57" title="Core" name="Issue cycles" description="For every cycle, this event counts the number of instructions issued in that cycle. Multi-cycle instructions are only counted once"/>
++ <event event="0x58" title="NEON" name="MRC data wait" description="Number of cycles the processor stalls waiting on MRC data from NEON"/>
++ <event event="0x59" title="NEON" name="Full queue" description="Number of cycles that the processor stalls as a result of a full NEON instruction queue or NEON load queue"/>
++ <event event="0x5a" title="NEON" name="Idle" description="Number of cycles that NEON and integer processors are both not idle"/>
++ <event event="0x70" title="External" name="PMUEXTIN[0]" description="Counts any event from external input source PMUEXTIN[0]"/>
++ <event event="0x71" title="External" name="PMUEXTIN[1]" description="Counts any event from external input source PMUEXTIN[1]"/>
++ <event event="0x72" title="External" name="PMUEXTIN[0,1]" description="Counts any event from both external input sources PMUEXTIN[0] and PMUEXTIN[1]"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A9.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A9.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Cortex-A9.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Cortex-A9.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,65 @@
++ <counter_set name="ARM_Cortex-A9_cnt" count="6"/>
++ <category name="Cortex-A9" counter_set="ARM_Cortex-A9_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="ARM_Cortex-A9_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
++ <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x0c" title="Branch" name="PC change" description="Software change of the Program Counter, except by an exception, architecturally executed"/>
++ <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
++ <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <event event="0x40" title="Java" name="Bytecode execute" description="Counts the number of Java bytecodes being decoded, including speculative ones"/>
++ <event event="0x41" title="Java" name="SW bytecode execute" description="Counts the number of software java bytecodes being decoded, including speculative ones"/>
++ <event event="0x42" title="Jazelle" name="Backward branch execute" description="Counts the number of Jazelle taken branches being executed"/>
++ <event event="0x50" title="Cache" name="Coherency miss" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which also miss in all the other Cortex-A9 processors, meaning that the request is sent to the external memory"/>
++ <event event="0x51" title="Cache" name="Coherency hit" description="Counts the number of coherent linefill requests performed by the Cortex-A9 processor which hit in another Cortex-A9 processor, meaning that the linefill data is fetched directly from the relevant Cortex-A9 cache"/>
++ <event event="0x60" title="Cache" name="Inst dependent stall" description="Counts the number of cycles where the processor is ready to accept new instructions, but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill"/>
++ <event event="0x61" title="Cache" name="Data dependent stall" description="Counts the number of cycles where the core has some instructions that it cannot issue to any pipeline, and the Load Store unit has at least one pending linefill request, and no pending TLB requests"/>
++ <event event="0x62" title="Cache" name="TLB stall" description="Counts the number of cycles where the processor is stalled waiting for the completion of translation table walks from the main TLB"/>
++ <event event="0x63" title="Intrinsic" name="STREX pass" description="Counts the number of STREX instructions architecturally executed and passed"/>
++ <event event="0x64" title="Intrinsic" name="STREX fail" description="Counts the number of STREX instructions architecturally executed and failed"/>
++ <event event="0x65" title="Cache" name="Data eviction" description="Counts the number of eviction requests because of a linefill in the data cache"/>
++ <event event="0x66" title="Pipeline" name="Issue stage no dispatch" description="Counts the number of cycles where the issue stage does not dispatch any instruction because it is empty or cannot dispatch any instructions"/>
++ <event event="0x67" title="Pipeline" name="Issue stage empty" description="Counts the number of cycles where the issue stage is empty"/>
++ <event event="0x68" title="Instruction" name="Executed" description="Counts the number of instructions going through the Register Renaming stage. This number is an approximate number of the total number of instructions speculatively executed, and even more approximate of the total number of instructions architecturally executed"/>
++ <event event="0x69" title="Cache" name="Data linefills" description="Counts the number of linefills performed on the external AXI bus"/>
++ <event event="0x6A" title="Cache" name="Prefetch linefills" description="Counts the number of data linefills caused by prefetcher requests"/>
++ <event event="0x6B" title="Cache" name="Prefetch hits" description="Counts the number of cache hits in a line that belongs to a stream followed by the prefetcher"/>
++ <event event="0x6E" title="Core" name="Functions" description="Counts the number of procedure returns whose condition codes do not fail, excluding all returns from exception"/>
++ <event event="0x70" title="Instruction" name="Main execution unit" description="Counts the number of instructions being executed in the main execution pipeline of the processor, the multiply pipeline and arithmetic logic unit pipeline"/>
++ <event event="0x71" title="Instruction" name="Second execution unit" description="Counts the number of instructions being executed in the processor second execution pipeline (ALU)"/>
++ <event event="0x72" title="Instruction" name="Load/Store" description="Counts the number of instructions being executed in the Load/Store unit"/>
++ <event event="0x73" title="Instruction" name="Floating point" description="Counts the number of Floating-point instructions going through the Register Rename stage"/>
++ <event event="0x74" title="Instruction" name="NEON" description="Counts the number of NEON instructions going through the Register Rename stage"/>
++ <event event="0x80" title="Stalls" name="PLD" description="Counts the number of cycles where the processor is stalled because PLD slots are all full"/>
++ <event event="0x81" title="Stalls" name="Memory write" description="Counts the number of cycles when the processor is stalled and the data side is stalled too because it is full and executing writes to the external memory"/>
++ <event event="0x82" title="Stalls" name="Inst main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the instruction side"/>
++ <event event="0x83" title="Stalls" name="Data main TLB miss" description="Counts the number of stall cycles because of main TLB misses on requests issued by the data side"/>
++ <event event="0x84" title="Stalls" name="Inst micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the instruction side"/>
++ <event event="0x85" title="Stalls" name="Data micro TLB miss" description="Counts the number of stall cycles because of micro TLB misses on the data side"/>
++ <event event="0x86" title="Stalls" name="DMB" description="Counts the number of stall cycles because of the execution of a DMB memory barrier"/>
++ <event event="0x8A" title="Clock" name="Integer core" description="Counts the number of cycles during which the integer core clock is enabled"/>
++ <event event="0x8B" title="Clock" name="Data engine" description="Counts the number of cycles during which the Data Engine clock is enabled"/>
++ <event event="0x8C" title="Clock" name="NEON" description="Counts the number of cycles when the NEON SIMD clock is enabled"/>
++ <event event="0x8D" title="Memory" name="TLB inst allocations" description="Counts the number of TLB allocations because of Instruction requests"/>
++ <event event="0x8E" title="Memory" name="TLB data allocations" description="Counts the number of TLB allocations because of Data requests"/>
++ <event event="0x90" title="Instruction" name="ISB" description="Counts the number of ISB instructions architecturally executed"/>
++ <event event="0x91" title="Instruction" name="DSB" description="Counts the number of DSB instructions architecturally executed"/>
++ <event event="0x92" title="Instruction" name="DMB" description="Counts the number of DMB instructions speculatively executed"/>
++ <event event="0x93" title="External" name="Interrupts" description="Counts the number of external interrupts executed by the processor"/>
++ <event event="0xA0" title="PLE" name="Cache line rq completed" description="Counts the number of PLE cache line requests completed"/>
++ <event event="0xA1" title="PLE" name="Cache line rq skipped" description="Counts the number of PLE cache line requests skipped"/>
++ <event event="0xA2" title="PLE" name="FIFO flush" description="Counts the number of PLE FIFO flush requests"/>
++ <event event="0xA3" title="PLE" name="Request completed" description="Counts the number of PLE FIFO flush completed"/>
++ <event event="0xA4" title="PLE" name="FIFO overflow" description="Counts the number of PLE FIFO flush overflowed"/>
++ <event event="0xA5" title="PLE" name="Request programmed" description="Counts the number of PLE FIFO flush program requests"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events_footer.xml linux-linaro-stable-mx6/tools/gator/daemon/events_footer.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events_footer.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events_footer.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1 @@
++</events>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events_header.xml linux-linaro-stable-mx6/tools/gator/daemon/events_header.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events_header.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events_header.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,2 @@
++<?xml version="1.0" encoding="UTF-8"?>
++<events>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Krait-architected.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Krait-architected.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Krait-architected.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Krait-architected.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,22 @@
++ <counter_set name="Krait_cnt" count="4"/>
++ <category name="Krait" counter_set="Krait_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="Krait_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
++ <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
++ <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
++ <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
++ <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-L2C-310.xml linux-linaro-stable-mx6/tools/gator/daemon/events-L2C-310.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-L2C-310.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-L2C-310.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,18 @@
++ <counter_set name="L2C-310_cnt" count="2"/>
++ <category name="L2C-310" counter_set="L2C-310_cnt" per_cpu="no">
++ <event event="0x1" title="L2 Cache" name="CO" description="Eviction, CastOUT, of a line from the L2 cache"/>
++ <event event="0x2" title="L2 Cache" name="DRH" description="Data read hit"/>
++ <event event="0x3" title="L2 Cache" name="DRREQ" description="Data read request"/>
++ <event event="0x4" title="L2 Cache" name="DWHIT" description="Data write hit"/>
++ <event event="0x5" title="L2 Cache" name="DWREQ" description="Data write request"/>
++ <event event="0x6" title="L2 Cache" name="DWTREQ" description="Data write request with write-through attribute"/>
++ <event event="0x7" title="L2 Cache" name="IRHIT" description="Instruction read hit"/>
++ <event event="0x8" title="L2 Cache" name="IRREQ" description="Instruction read request"/>
++ <event event="0x9" title="L2 Cache" name="WA" description="Write allocate"/>
++ <event event="0xa" title="L2 Cache" name="IPFALLOC" description="Allocation of a prefetch generated by L2C-310 into the L2 cache"/>
++ <event event="0xb" title="L2 Cache" name="EPFHIT" description="Prefetch hint hits in the L2 cache"/>
++ <event event="0xc" title="L2 Cache" name="EPFALLOC" description="Prefetch hint allocated into the L2 cache"/>
++ <event event="0xd" title="L2 Cache" name="SRRCVD" description="Speculative read received"/>
++ <event event="0xe" title="L2 Cache" name="SRCONF" description="Speculative read confirmed"/>
++ <event event="0xf" title="L2 Cache" name="EPFRCVD" description="Prefetch hint received"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Linux.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Linux.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Linux.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Linux.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,17 @@
++ <category name="Linux">
++ <event counter="Linux_irq_softirq" title="Interrupts" name="SoftIRQ" per_cpu="yes" description="Linux SoftIRQ taken"/>
++ <event counter="Linux_irq_irq" title="Interrupts" name="IRQ" per_cpu="yes" description="Linux IRQ taken"/>
++ <event counter="Linux_block_rq_wr" title="Disk IO" name="Write" units="B" description="Disk IO Bytes Written"/>
++ <event counter="Linux_block_rq_rd" title="Disk IO" name="Read" units="B" description="Disk IO Bytes Read"/>
++ <event counter="Linux_net_rx" title="Network" name="Receive" units="B" description="Receive network traffic, including effect from Streamline"/>
++ <event counter="Linux_net_tx" title="Network" name="Transmit" units="B" description="Transmit network traffic, including effect from Streamline"/>
++ <event counter="Linux_sched_switch" title="Scheduler" name="Switch" per_cpu="yes" description="Context switch events"/>
++ <event counter="Linux_meminfo_memused" title="Memory" name="Used" display="maximum" units="B" proc="yes" description="Total used memory size. Note: a process' used memory includes shared memory that may be counted more than once (equivalent to RES from top). Kernel threads are not filterable."/>
++ <event counter="Linux_meminfo_memfree" title="Memory" name="Free" display="minimum" units="B" description="Available memory size"/>
++ <event counter="Linux_meminfo_bufferram" title="Memory" name="Buffer" display="maximum" units="B" description="Memory used by OS disk buffers"/>
++ <event counter="Linux_power_cpu_freq" title="Clock" name="Frequency" per_cpu="yes" display="maximum" units="Hz" series_composition="overlay" average_cores="yes" description="Frequency setting of the CPU"/>
++ <event counter="Linux_power_cpu_idle" title="Idle" name="State" per_cpu="yes" display="maximum" description="CPU Idle State + 1, set the Sample Rate to None to prevent the hrtimer from interrupting the system"/>
++ <event counter="Linux_cpu_wait_contention" title="CPU Contention" name="Wait" per_cpu="no" display="average" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on contended resource"/>
++ <event counter="Linux_cpu_wait_io" title="CPU I/O" name="Wait" per_cpu="no" display="average" derived="yes" rendering_type="bar" average_selection="yes" percentage="yes" modifier="10000" description="Thread waiting on I/O resource"/>
++ </category>
++
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Mali-4xx.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Mali-4xx.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Mali-4xx.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Mali-4xx.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,251 @@
++ <counter_set name="ARM_Mali-4xx_VP_0_cnt" count="2"/>
++ <counter_set name="ARM_Mali-4xx_SW_cnt" count="0"/>
++ <counter_set name="ARM_Mali-4xx_Filmstrip_cnt" count="1"/>
++ <category name="Mali-4xx-VP" counter_set="ARM_Mali-4xx_VP_0_cnt" per_cpu="no">
++ <event event="0x01" title="Mali GPU Vertex Processor" name="Active cycles" description="Number of cycles per frame the MaliGP2 was active."/>
++ <event event="0x02" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader" description="Number of cycles per frame the vertex shader unit was active."/>
++ <event event="0x03" title="Mali GPU Vertex Processor" name="Active cycles, vertex storer" description="Number of cycles per frame the vertex storer unit was active."/>
++ <event event="0x04" title="Mali GPU Vertex Processor" name="Active cycles, vertex loader" description="Number of cycles per frame the vertex loader unit was active."/>
++ <event event="0x05" title="Mali GPU Vertex Processor" name="Cycles vertex loader waiting for vertex shader" description="Number of cycles per frame the vertex loader was idle while waiting on the vertex shader."/>
++ <event event="0x06" title="Mali GPU Vertex Processor" name="Words read, system bus" description="Total number of 64 bit words read by the GP2 from the system bus per frame."/>
++ <event event="0x07" title="Mali GPU Vertex Processor" name="Words written, system bus" description="Total number of 64 bit words written by the GP2 to the system bus per frame."/>
++ <event event="0x08" title="Mali GPU Vertex Processor" name="Read bursts, system bus" description="Number of read bursts by the GP2 from the system bus per frame."/>
++ <event event="0x09" title="Mali GPU Vertex Processor" name="Write bursts, system bus" description="Number of write bursts from the MaliGP2 to the system bus per frame."/>
++ <event event="0x0a" title="Mali GPU Vertex Processor" name="Vertices processed" description="Number of vertices processed by the MaliGP2 per frame."/>
++ <event event="0x0b" title="Mali GPU Vertex Processor" name="Vertices fetched" description="Number of vertices fetched by the MaliGP2 per frame."/>
++ <event event="0x0c" title="Mali GPU Vertex Processor" name="Primitives fetched" description="Number of graphics primitives fetched by the MaliGP2 per frame."/>
++ <event event="0x0e" title="Mali GPU Vertex Processor" name="Primitives culled" description="Number of graphics primitives discarded per frame, because they were seen from the back or were offscreen."/>
++ <event event="0x0f" title="Mali GPU Vertex Processor" name="Commands written to tiles" description="Number of commands (8 Bytes, mainly primitives) written by GP2 to the PP input data structure per frame."/>
++ <event event="0x10" title="Mali GPU Vertex Processor" name="Memory blocks allocated" description="Number of overflow data blocks needed for outputting the PP input data structure per frame ."/>
++ <event event="0x13" title="Mali GPU Vertex Processor" name="Vertex loader cache misses" description="Number of cache misses for the vertex shader's vertex input unit per frame."/>
++ <event event="0x16" title="Mali GPU Vertex Processor" name="Active cycles, vertex shader command processor" description="Number of cycles per frame the GP2 vertex shader command processor was active. This includes time waiting for semaphores."/>
++ <event event="0x17" title="Mali GPU Vertex Processor" name="Active cycles, PLBU command processor" description="Number of cycles per frame the MaliGP2 PLBU command processor was active. This includes time waiting for semaphores."/>
++ <event event="0x18" title="Mali GPU Vertex Processor" name="MaliGP2 PLBU cycles per frame" description="Number of cycles per frame the MaliGP2 PLBU output unit was active. This includes time spent waiting on the bus."/>
++ <event event="0x19" title="Mali GPU Vertex Processor" name="Active cycles, PLBU geometry processing" description="Number of cycles per frame the MaliGP2 PLBU was active, excepting final data output. In other words: active cycles through the prepare list commands. This includes time spent waiting on the bus."/>
++ <event event="0x1b" title="Mali GPU Vertex Processor" name="Active cycles, PLBU primitive assembly" description="Number of active cycles per frame spent by the MaliGP2 PLBU doing primitive assembly. This does not include scissoring or final output. This includes time spent waiting on the bus."/>
++ <event event="0x1c" title="Mali GPU Vertex Processor" name="Active cycles, PLBU vertex fetcher" description="Number of active cycles per frame spent by the MaliGP2 PLBU fetching vertex data. This includes time spent waiting on the bus."/>
++ <event event="0x1e" title="Mali GPU Vertex Processor" name="Active cycles, Bounding-box and command generator" description="Number of active cycles per frame spent by the MaliGP2 PLBU setting up bounding boxes and commands (mainly graphics primitives). This includes time spent waiting on the bus."/>
++ <event event="0x20" title="Mali GPU Vertex Processor" name="Active cycles, Scissor tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over tiles to perform scissoring. This includes time spent waiting on the bus."/>
++ <event event="0x21" title="Mali GPU Vertex Processor" name="Active cycles, PLBU tile iterator" description="Number of active cycles per frame spent by the MaliGP2 PLBU iterating over the tiles in the bounding box generating commands (mainly graphics primitives). This includes time spent waiting on the bus."/>
++ </category>
++ <category name="Mali GPU Fragment Processor" per_cpu="no">
++ <counter_set name="ARM_Mali-4xx_FP_0_cnt" title="Mali-4xx FP0" description="Mali GPU Fragment Processor 0" count="2"/>
++ <counter_set name="ARM_Mali-4xx_FP_1_cnt" title="Mali-4xx FP1" description="Mali GPU Fragment Processor 1" count="2"/>
++ <counter_set name="ARM_Mali-4xx_FP_2_cnt" title="Mali-4xx FP2" description="Mali GPU Fragment Processor 2" count="2"/>
++ <counter_set name="ARM_Mali-4xx_FP_3_cnt" title="Mali-4xx FP3" description="Mali GPU Fragment Processor 3" count="2"/>
++ <counter_set name="ARM_Mali-4xx_FP_4_cnt" title="Mali-4xx FP4" description="Mali GPU Fragment Processor 4" count="2"/>
++ <counter_set name="ARM_Mali-4xx_FP_5_cnt" title="Mali-4xx FP5" description="Mali GPU Fragment Processor 5" count="2"/>
++ <counter_set name="ARM_Mali-4xx_FP_6_cnt" title="Mali-4xx FP6" description="Mali GPU Fragment Processor 6" count="2"/>
++ <counter_set name="ARM_Mali-4xx_FP_7_cnt" title="Mali-4xx FP7" description="Mali GPU Fragment Processor 7" count="2"/>
++
++ <event event="0x00" title="Mali-4xx FP" name="Active clock cycles" description="Active clock cycles, between polygon start and IRQ."/>
++ <event event="0x02" title="Mali-4xx FP" name="Total bus reads" description="Total number of 64-bit words read from the bus."/>
++ <event event="0x03" title="Mali-4xx FP" name="Total bus writes" description="Total number of 64-bit words written to the bus."/>
++ <event event="0x04" title="Mali-4xx FP" name="Bus read request cycles" description="Number of cycles during which the bus read request signal was HIGH."/>
++ <event event="0x05" title="Mali-4xx FP" name="Bus write request cycles" description="Number of cycles during which the bus write request signal was HIGH."/>
++ <event event="0x06" title="Mali-4xx FP" name="Bus read transactions count" description="Number of read requests accepted by the bus."/>
++ <event event="0x07" title="Mali-4xx FP" name="Bus write transactions" description="Number of write requests accepted by the bus."/>
++ <event event="0x09" title="Mali-4xx FP" name="Tile writeback writes" description="64-bit words written to the bus by the writeback unit."/>
++ <event event="0x0a" title="Mali-4xx FP" name="Store unit writes" description="64-bit words written to the bus by the store unit."/>
++ <event event="0x0d" title="Mali-4xx FP" name="Texture cache uncompressed reads" description="Number of 64-bit words read from the bus into the uncompressed textures cache."/>
++ <event event="0x0e" title="Mali-4xx FP" name="Polygon list reads" description="Number of 64-bit words read from the bus by the polygon list reader."/>
++ <event event="0x0f" title="Mali-4xx FP" name="RSW reads" description="Number of 64-bit words read from the bus into the Render State Word register."/>
++ <event event="0x10" title="Mali-4xx FP" name="Vertex cache reads" description="Number of 64-bit words read from the bus into the vertex cache."/>
++ <event event="0x11" title="Mali-4xx FP" name="Uniform remapping reads" description="Number of 64-bit words read from the bus when reading from the uniform remapping table."/>
++ <event event="0x12" title="Mali-4xx FP" name="Program cache reads" description="Number of 64-bit words read from the bus into the fragment shader program cache."/>
++ <event event="0x13" title="Mali-4xx FP" name="Varying reads" description="Number of 64-bit words containing varyings generated by the vertex processing read from the bus."/>
++ <event event="0x14" title="Mali-4xx FP" name="Texture descriptors reads" description="Number of 64-bit words containing texture descriptors read from the bus."/>
++ <event event="0x15" title="Mali-4xx FP" name="Texture descriptor remapping reads" description="Number of 64-bit words read from the bus when reading from the texture descriptor remapping table."/>
++ <event event="0x17" title="Mali-4xx FP" name="Load unit reads" description="Number of 64-bit words read from the bus by the LOAD sub-instruction."/>
++ <event event="0x18" title="Mali-4xx FP" name="Polygon count" description="Number of triangles read from the polygon list."/>
++ <event event="0x19" title="Mali-4xx FP" name="Pixel rectangle count" description="Number of pixel rectangles read from the polygon list."/>
++ <event event="0x1a" title="Mali-4xx FP" name="Lines count" description="Number of lines read from the polygon list."/>
++ <event event="0x1b" title="Mali-4xx FP" name="Points count" description="Number of points read from the polygon list."/>
++ <event event="0x1c" title="Mali-4xx FP" name="Stall cycles PolygonListReader" description="Number of clock cycles the Polygon List Reader waited for output being collected."/>
++ <event event="0x1d" title="Mali-4xx FP" name="Stall cycles triangle setup" description="Number of clock cycles the TSC waited for input."/>
++ <event event="0x1e" title="Mali-4xx FP" name="Quad rasterized count" description="Number of 2x?2 quads output from rasterizer."/>
++ <event event="0x1f" title="Mali-4xx FP" name="Fragment rasterized count" description="Number of fragment rasterized. Fragments/(Quads*4) gives average actual fragments per quad."/>
++ <event event="0x20" title="Mali-4xx FP" name="Fragment rejected fragment-kill count" description="Number of fragments exiting the fragment shader as killed."/>
++ <event event="0x21" title="Mali-4xx FP" name="Fragment rejected fwd-fragment-kill count" description="Number of fragments killed by forward fragment kill."/>
++ <event event="0x22" title="Mali-4xx FP" name="Fragment passed z/stencil count" description="Number of fragments passing Z and stencil test."/>
++ <event event="0x23" title="Mali-4xx FP" name="Patches rejected early z/stencil count" description="Number of patches rejected by EarlyZ. A patch can be 8x8, 4x4 or 2x2 pixels."/>
++ <event event="0x24" title="Mali-4xx FP" name="Patches evaluated" description="Number of patches evaluated for EarlyZ rejection."/>
++ <event event="0x25" title="Mali-4xx FP" name="Instruction completed count" description="Number of fragment shader instruction words completed. It is a function of pixels processed and the length of the shader programs."/>
++ <event event="0x26" title="Mali-4xx FP" name="Instruction failed rendezvous count" description="Number of fragment shader instructions not completed because of failed Rendezvous."/>
++ <event event="0x27" title="Mali-4xx FP" name="Instruction failed varying-miss count" description="Number of fragment shader instructions not completed because of failed varying operation."/>
++ <event event="0x28" title="Mali-4xx FP" name="Instruction failed texture-miss count" description="Number of fragment shader instructions not completed because of failed texture operation."/>
++ <event event="0x29" title="Mali-4xx FP" name="Instruction failed load-miss count" description="Number of fragment shader instructions not completed because of failed load operation."/>
++ <event event="0x2a" title="Mali-4xx FP" name="Instruction failed tile read-miss count" description="Number of fragment shader instructions not completed because of failed read from the tilebuffer."/>
++ <event event="0x2b" title="Mali-4xx FP" name="Instruction failed store-miss count" description="Number of fragment shader instructions not completed because of failed store operation."/>
++ <event event="0x2c" title="Mali-4xx FP" name="Rendezvous breakage count" description="Number of Rendezvous breakages reported."/>
++ <event event="0x2d" title="Mali-4xx FP" name="Pipeline bubbles cycle count" description="Number of unused cycles in the fragment shader while rendering is active."/>
++ <event event="0x2e" title="Mali-4xx FP" name="Texture mapper multipass count" description="Number of texture operations looped because of more texture passes needed."/>
++ <event event="0x2f" title="Mali-4xx FP" name="Texture mapper cycle count" description="Number of texture operation cycles."/>
++ <event event="0x30" title="Mali-4xx FP" name="Vertex cache hit count" description="Number of times a requested vertex was found in the cache (Number of vertex cache hits)."/>
++ <event event="0x31" title="Mali-4xx FP" name="Vertex cache miss count" description="Number of times a requested vertex was not found in the cache (Number of vertex cache misses)."/>
++ <event event="0x32" title="Mali-4xx FP" name="Varying cache hit count" description="Number of times a requested varying was found in the cache (Number of varying cache hits)."/>
++ <event event="0x33" title="Mali-4xx FP" name="Varying cache miss count" description="Number of times a requested varying was not found in the cache (Number of varying cache misses)."/>
++ <event event="0x34" title="Mali-4xx FP" name="Varying cache conflict miss count" description="Number of times a requested varying was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
++ <event event="0x35" title="Mali-4xx FP" name="Texture cache hit count" description="Number of times a requested texel was found in the texture cache (Number of texture cache hits)."/>
++ <event event="0x36" title="Mali-4xx FP" name="Texture cache miss count" description="Number of times a requested texel was not found in the texture cache (Number of texture cache misses)."/>
++ <event event="0x37" title="Mali-4xx FP" name="Texture cache conflict miss count" description="Number of times a requested texel was not in the cache and its value, retrieved from memory, must overwrite an older cache entry. This happens when an access pattern cannot be serviced by the cache."/>
++ <event event="0x38" title="Mali-4xx FP" name="Compressed texture cache hit count" description="Number of times a requested item was found in the cache."/>
++ <event event="0x39" title="Mali-4xx FP" name="Compressed texture cache miss count" description="Number of times a requested item was not found in the cache."/>
++ <event event="0x3a" title="Mali-4xx FP" name="Load/Store cache hit count" description="Number of hits in the load/store cache."/>
++ <event event="0x3b" title="Mali-4xx FP" name="Load/Store cache miss count" description="Number of misses in the load/store cache."/>
++ <event event="0x3c" title="Mali-4xx FP" name="Program cache hit count" description="Number of hits in the program cache."/>
++ <event event="0x3d" title="Mali-4xx FP" name="Program cache miss count" description="Number of misses in the program cache."/>
++ </category>
++ <counter_set name="ARM_Mali-4xx_L2_0_cnt" title="Mali-4xx L2 0" description="Mali GPU L2 Cache Core 0" count="2"/>
++ <category name="Mali-4xx-L2_0" counter_set="ARM_Mali-4xx_L2_0_cnt" per_cpu="no">
++ <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
++ <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
++
++ <option_set name="All">
++ <option event_delta="0x08" name="Master" description="Master"/>
++ <option event_delta="0x10" name="All slaves" description="All slaves"/>
++ <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
++ <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
++ <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
++ <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
++ <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
++ </option_set>
++
++ <option_set name="Slaves">
++ <option event_delta="0x10" name="All slaves" description="All slaves"/>
++ <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
++ <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
++ <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
++ <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
++ <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
++ </option_set>
++
++ <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
++ <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
++ <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
++ <event event="0x03" option_set="All" title="Mali L2 Cache" name="Words written" description="Words written"/>
++ <event event="0x04" option_set="Slaves" title="Mali L2 Cache" name="Read hits" description="Read hits"/>
++ <event event="0x05" option_set="Slaves" title="Mali L2 Cache" name="Read misses" description="Read misses"/>
++ <event event="0x06" option_set="Slaves" title="Mali L2 Cache" name="Write invalidates" description="Write invalidates"/>
++ <event event="0x07" option_set="Slaves" title="Mali L2 Cache" name="Read invalidates" description="Read invalidates"/>
++ <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
++ </category>
++ <counter_set name="ARM_Mali-4xx_L2_1_cnt" title="Mali-4xx L2 1" description="Mali GPU L2 Cache Core 1" count="2"/>
++ <category name="Mali-4xx-L2_1" counter_set="ARM_Mali-4xx_L2_1_cnt" per_cpu="no">
++ <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
++ <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
++
++ <option_set name="All">
++ <option event_delta="0x08" name="Master" description="Master"/>
++ <option event_delta="0x10" name="All slaves" description="All slaves"/>
++ <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
++ <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
++ <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
++ <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
++ <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
++ </option_set>
++
++ <option_set name="Slaves">
++ <option event_delta="0x10" name="All slaves" description="All slaves"/>
++ <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
++ <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
++ <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
++ <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
++ <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
++ </option_set>
++
++ <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
++ <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
++ <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
++ <event event="0x03" option_set="All" title="Mali L2 Cache" name="Words written" description="Words written"/>
++ <event event="0x04" option_set="Slaves" title="Mali L2 Cache" name="Read hits" description="Read hits"/>
++ <event event="0x05" option_set="Slaves" title="Mali L2 Cache" name="Read misses" description="Read misses"/>
++ <event event="0x06" option_set="Slaves" title="Mali L2 Cache" name="Write invalidates" description="Write invalidates"/>
++ <event event="0x07" option_set="Slaves" title="Mali L2 Cache" name="Read invalidates" description="Read invalidates"/>
++ <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
++ </category>
++ <counter_set name="ARM_Mali-4xx_L2_2_cnt" title="Mali-4xx L2 2" description="Mali GPU L2 Cache Core 2" count="2"/>
++ <category name="Mali-4xx-L2_2" counter_set="ARM_Mali-4xx_L2_2_cnt" per_cpu="no">
++ <event event="0x01" title="Mali L2 Cache" name="Total clock cycles" description="Total clock cycles"/>
++ <event event="0x02" title="Mali L2 Cache" name="Active clock cycles" description="Active clock cycles"/>
++
++ <option_set name="All">
++ <option event_delta="0x08" name="Master" description="Master"/>
++ <option event_delta="0x10" name="All slaves" description="All slaves"/>
++ <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
++ <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
++ <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
++ <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
++ <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
++ </option_set>
++
++ <option_set name="Slaves">
++ <option event_delta="0x10" name="All slaves" description="All slaves"/>
++ <option event_delta="0x20" name="Slave 0" description="Slave 0"/>
++ <option event_delta="0x30" name="Slave 1" description="Slave 1"/>
++ <option event_delta="0x40" name="Slave 2" description="Slave 2"/>
++ <option event_delta="0x50" name="Slave 3" description="Slave 3"/>
++ <option event_delta="0x60" name="Slave 4" description="Slave 4"/>
++ </option_set>
++
++ <event event="0x00" option_set="All" title="Mali L2 Cache" name="Read transactions" description="Read transactions"/>
++ <event event="0x01" option_set="All" title="Mali L2 Cache" name="Write transactions" description="Write transactions"/>
++ <event event="0x02" option_set="All" title="Mali L2 Cache" name="Words read" description="Words read"/>
++ <event event="0x03" option_set="All" title="Mali L2 Cache" name="Words written" description="Words written"/>
++ <event event="0x04" option_set="Slaves" title="Mali L2 Cache" name="Read hits" description="Read hits"/>
++ <event event="0x05" option_set="Slaves" title="Mali L2 Cache" name="Read misses" description="Read misses"/>
++ <event event="0x06" option_set="Slaves" title="Mali L2 Cache" name="Write invalidates" description="Write invalidates"/>
++ <event event="0x07" option_set="Slaves" title="Mali L2 Cache" name="Read invalidates" description="Read invalidates"/>
++ <event event="0x08" option_set="Slaves" title="Mali L2 Cache" name="Cacheable read transactions" description="Cacheable read transactions"/>
++ </category>
++ <category name="ARM Mali-4xx Filmstrip" counter_set="ARM_Mali-4xx_Filmstrip_cnt" per_cpu="no">
++ <option_set name="fs">
++ <option event_delta="0x3c" name="1:60" description="captures every 60th frame"/>
++ <option event_delta="0x1e" name="1:30" description="captures every 30th frame"/>
++ <option event_delta="0xa" name="1:10" description="captures every 10th frame"/>
++ </option_set>
++ <event event="0x0400" option_set="fs" title="ARM Mali-4xx" name="Filmstrip" description="Scaled framebuffer"/>
++ </category>
++ <category name="ARM_Mali-4xx_Voltage" per_cpu="no">
++ <event counter="ARM_Mali-4xx_Voltage" title="Mali GPU Voltage" name="Voltage" display="average" average_selection="yes" units="mV" description="GPU core voltage."/>
++ </category>
++ <category name="ARM_Mali-4xx_Frequency" per_cpu="no">
++ <event counter="ARM_Mali-4xx_Frequency" title="Mali GPU Frequency" name="Frequency" display="average" average_selection="yes" units="MHz" description="GPU core frequency."/>
++ </category>
++ <category name="Mali-4xx-SW" counter_set="ARM_Mali-4xx_SW_cnt" per_cpu="no">
++ <!-- EGL Counters -->
++ <event counter="ARM_Mali-4xx_SW_0" title="Mali EGL Software Counters" name="Blit Time" description="Time spent blitting the framebuffer from video memory to framebuffer."/>
++ <!-- glDrawElements Counters -->
++ <event counter="ARM_Mali-4xx_SW_1" title="glDrawElements Statistics" name="Calls to glDrawElements" description="Number of calls to glDrawElements."/>
++ <event counter="ARM_Mali-4xx_SW_2" title="glDrawElements Statistics" name="Indices to glDrawElements" description="Number of indices to glDrawElements."/>
++ <event counter="ARM_Mali-4xx_SW_3" title="glDrawElements Statistics" name="Transformed by glDrawElements" description="Number of vertices transformed by glDrawElements."/>
++ <!-- glDrawArrays Counters -->
++ <event counter="ARM_Mali-4xx_SW_4" title="glDrawArrays Statistics" name="Calls to glDrawArrays" description="Number of calls to glDrawArrays."/>
++ <event counter="ARM_Mali-4xx_SW_5" title="glDrawArrays Statistics" name="Transformed by glDrawArrays" description="Number of vertices transformed by glDrawArrays."/>
++ <!-- Draw Call Counters -->
++ <event counter="ARM_Mali-4xx_SW_6" title="Drawcall Statistics" name="Points" description="Number of calls to glDraw* with parameter GL_POINTS."/>
++ <event counter="ARM_Mali-4xx_SW_7" title="Drawcall Statistics" name="Lines" description="Number of calls to glDraw* with parameter GL_LINES."/>
++ <event counter="ARM_Mali-4xx_SW_8" title="Drawcall Statistics" name="Lineloop" description="Number of calls to glDraw* with parameter GL_LINE_LOOP."/>
++ <event counter="ARM_Mali-4xx_SW_9" title="Drawcall Statistics" name="Linestrip" description="Number of calls to glDraw* with parameter GL_LINE_STRIP."/>
++ <event counter="ARM_Mali-4xx_SW_10" title="Drawcall Statistics" name="Triangles" description="Number of calls to glDraw* with parameter GL_TRIANGLES."/>
++ <event counter="ARM_Mali-4xx_SW_11" title="Drawcall Statistics" name="Trianglestrip" description="Number of calls to glDraw* with parameter GL_TRIANGLE_STRIP."/>
++ <event counter="ARM_Mali-4xx_SW_12" title="Drawcall Statistics" name="Trianglefan" description="Number of calls to glDraw* with parameter GL_TRIANGLE_FAN."/>
++ <event counter="ARM_Mali-4xx_SW_13" title="Drawcall Statistics" name="Vertex Upload Time (us)" description="Time spent uploading vertex attributes and faceindex data not present in a VBO."/>
++ <event counter="ARM_Mali-4xx_SW_14" title="Drawcall Statistics" name="Uniform Bytes Copied (bytes)" description="Number of bytes copied to Mali memory as a result of uniforms update."/>
++ <!-- Buffer Profiling Counters -->
++ <event counter="ARM_Mali-4xx_SW_15" title="Buffer Profiling" name="Texture Upload Time (ms)" description="Time spent uploading textures."/>
++ <event counter="ARM_Mali-4xx_SW_16" title="Buffer Profiling" name="VBO Upload Time (ms)" description="Time spent uploading vertex buffer objects."/>
++ <event counter="ARM_Mali-4xx_SW_17" title="Buffer Profiling" name="FBO Flushes" description="Number of flushed on framebuffer attachment."/>
++ <!-- OpenGL ES 1.1 Emulation -->
++ <event counter="ARM_Mali-4xx_SW_18" title="Fixed-function Emulation" name="# Vertex Shaders Generated" description="Number of vertex shaders generated."/>
++ <event counter="ARM_Mali-4xx_SW_19" title="Fixed-function Emulation" name="# Fragment Shaders Generated" description="Number of fragment shaders generated."/>
++ <!-- Geometry Statistics -->
++ <event counter="ARM_Mali-4xx_SW_33" title="Geometry Statistics" name="Triangles" description="The total number of triangles passed to GLES per-frame."/>
++ <event counter="ARM_Mali-4xx_SW_34" title="Geometry Statistics" name="Independent Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLES."/>
++ <event counter="ARM_Mali-4xx_SW_35" title="Geometry Statistics" name="Strip Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_STRIP."/>
++ <event counter="ARM_Mali-4xx_SW_36" title="Geometry Statistics" name="Fan Triangles" description="Number of triangles passed to GLES using the mode GL_TRIANGLE_FAN."/>
++ <event counter="ARM_Mali-4xx_SW_37" title="Geometry Statistics" name="Lines" description="Number of lines passed to GLES per-frame."/>
++ <event counter="ARM_Mali-4xx_SW_38" title="Geometry Statistics" name="Independent Lines" description="Number of lines passed to GLES using the mode GL_LINES."/>
++ <event counter="ARM_Mali-4xx_SW_39" title="Geometry Statistics" name="Strip Lines" description="Number of lines passed to GLES using the mode GL_LINE_STRIP."/>
++ <event counter="ARM_Mali-4xx_SW_40" title="Geometry Statistics" name="Loop Lines" description="Number of lines passed to GLES using the mode GL_LINE_LOOP."/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Mali-T6xx_hw.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Mali-T6xx_hw.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Mali-T6xx_hw.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Mali-T6xx_hw.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,116 @@
++
++ <category name="Mali-T6xx-JobManager" per_cpu="no">
++
++ <event counter="ARM_Mali-T6xx_GPU_ACTIVE" title="Mali Job Manager Cycles" name="GPU cycles" description="Number of cycles the GPU was active"/>
++ <event counter="ARM_Mali-T6xx_IRQ_ACTIVE" title="Mali Job Manager Cycles" name="IRQ cycles" description="Number of cycles the GPU had a pending interrupt"/>
++ <event counter="ARM_Mali-T6xx_JS0_ACTIVE" title="Mali Job Manager Cycles" name="JS0 cycles" description="Number of cycles JS0 (fragment) was active"/>
++ <event counter="ARM_Mali-T6xx_JS1_ACTIVE" title="Mali Job Manager Cycles" name="JS1 cycles" description="Number of cycles JS1 (vertex/tiler/compute) was active"/>
++ <event counter="ARM_Mali-T6xx_JS2_ACTIVE" title="Mali Job Manager Cycles" name="JS2 cycles" description="Number of cycles JS2 (vertex/compute) was active"/>
++
++ <event counter="ARM_Mali-T6xx_JS0_JOBS" title="Mali Job Manager Work" name="JS0 jobs" description="Number of Jobs (fragment) completed in JS0"/>
++ <event counter="ARM_Mali-T6xx_JS0_TASKS" title="Mali Job Manager Work" name="JS0 tasks" description="Number of Tasks completed in JS0"/>
++ <event counter="ARM_Mali-T6xx_JS1_JOBS" title="Mali Job Manager Work" name="JS1 jobs" description="Number of Jobs (vertex/tiler/compute) completed in JS1"/>
++ <event counter="ARM_Mali-T6xx_JS1_TASKS" title="Mali Job Manager Work" name="JS1 tasks" description="Number of Tasks completed in JS1"/>
++ <event counter="ARM_Mali-T6xx_JS2_TASKS" title="Mali Job Manager Work" name="JS2 tasks" description="Number of Tasks completed in JS2"/>
++ <event counter="ARM_Mali-T6xx_JS2_JOBS" title="Mali Job Manager Work" name="JS2 jobs" description="Number of Jobs (vertex/compute) completed in JS2"/>
++
++ </category>
++
++ <category name="Mali-T6xx-Tiler" per_cpu="no">
++
++ <event counter="ARM_Mali-T6xx_POLYGONS" title="Mali Tiler Primitives" name="Polygons" description="Number of polygons processed"/>
++ <event counter="ARM_Mali-T6xx_QUADS" title="Mali Tiler Primitives" name="Quads" description="Number of quads processed"/>
++ <event counter="ARM_Mali-T6xx_TRIANGLES" title="Mali Tiler Primitives" name="Triangles" description="Number of triangles processed"/>
++ <event counter="ARM_Mali-T6xx_LINES" title="Mali Tiler Primitives" name="Lines" description="Number of lines processed"/>
++ <event counter="ARM_Mali-T6xx_POINTS" title="Mali Tiler Primitives" name="Points" description="Number of points processed"/>
++
++ <event counter="ARM_Mali-T6xx_FRONT_FACING" title="Mali Tiler Culling" name="Front facing prims" description="Number of front facing primitives"/>
++ <event counter="ARM_Mali-T6xx_BACK_FACING" title="Mali Tiler Culling" name="Back facing prims" description="Number of back facing primitives"/>
++ <event counter="ARM_Mali-T6xx_PRIM_VISIBLE" title="Mali Tiler Culling" name="Visible prims" description="Number of visible primitives"/>
++ <event counter="ARM_Mali-T6xx_PRIM_CULLED" title="Mali Tiler Culling" name="Culled prims" description="Number of culled primitives"/>
++ <event counter="ARM_Mali-T6xx_PRIM_CLIPPED" title="Mali Tiler Culling" name="Clipped prims" description="Number of clipped primitives"/>
++
++ <event counter="ARM_Mali-T6xx_LEVEL0" title="Mali Tiler Hierarchy" name="L0 prims" description="Number of primitives in hierarchy level 0"/>
++ <event counter="ARM_Mali-T6xx_LEVEL1" title="Mali Tiler Hierarchy" name="L1 prims" description="Number of primitives in hierarchy level 1"/>
++ <event counter="ARM_Mali-T6xx_LEVEL2" title="Mali Tiler Hierarchy" name="L2 prims" description="Number of primitives in hierarchy level 2"/>
++ <event counter="ARM_Mali-T6xx_LEVEL3" title="Mali Tiler Hierarchy" name="L3 prims" description="Number of primitives in hierarchy level 3"/>
++ <event counter="ARM_Mali-T6xx_LEVEL4" title="Mali Tiler Hierarchy" name="L4 prims" description="Number of primitives in hierarchy level 4"/>
++ <event counter="ARM_Mali-T6xx_LEVEL5" title="Mali Tiler Hierarchy" name="L5 prims" description="Number of primitives in hierarchy level 5"/>
++ <event counter="ARM_Mali-T6xx_LEVEL6" title="Mali Tiler Hierarchy" name="L6 prims" description="Number of primitives in hierarchy level 6"/>
++ <event counter="ARM_Mali-T6xx_LEVEL7" title="Mali Tiler Hierarchy" name="L7 prims" description="Number of primitives in hierarchy level 7"/>
++
++ <event counter="ARM_Mali-T6xx_COMMAND_1" title="Mali Tiler Commands" name="Prims in 1 command" description="Number of primitives producing 1 command"/>
++ <event counter="ARM_Mali-T6xx_COMMAND_2" title="Mali Tiler Commands" name="Prims in 2 command" description="Number of primitives producing 2 commands"/>
++ <event counter="ARM_Mali-T6xx_COMMAND_3" title="Mali Tiler Commands" name="Prims in 3 command" description="Number of primitives producing 3 commands"/>
++ <event counter="ARM_Mali-T6xx_COMMAND_4" title="Mali Tiler Commands" name="Prims in 4 command" description="Number of primitives producing 4 commands"/>
++ <event counter="ARM_Mali-T6xx_COMMAND_4_7" title="Mali Tiler Commands" name="Prims in 4-7 commands" description="Number of primitives producing 4-7 commands"/>
++ <event counter="ARM_Mali-T6xx_COMMAND_5_7" title="Mali Tiler Commands" name="Prims in 5-7 commands" description="Number of primitives producing 5-7 commands"/>
++ <event counter="ARM_Mali-T6xx_COMMAND_8_15" title="Mali Tiler Commands" name="Prims in 8-15 commands" description="Number of primitives producing 8-15 commands"/>
++ <event counter="ARM_Mali-T6xx_COMMAND_16_63" title="Mali Tiler Commands" name="Prims in 16-63 commands" description="Number of primitives producing 16-63 commands"/>
++ <event counter="ARM_Mali-T6xx_COMMAND_64" title="Mali Tiler Commands" name="Prims in &gt;= 64 commands" description="Number of primitives producing &gt;= 64 commands"/>
++
++ </category>
++
++ <category name="Mali-T6xx-ShaderCore" per_cpu="no">
++
++ <event counter="ARM_Mali-T6xx_TRIPIPE_ACTIVE" title="Mali Core Cycles" name="Tripipe cycles" description="Number of cycles the Tripipe was active"/>
++ <event counter="ARM_Mali-T6xx_FRAG_ACTIVE" title="Mali Core Cycles" name="Fragment cycles" description="Number of cycles fragment processing was active"/>
++ <event counter="ARM_Mali-T6xx_COMPUTE_ACTIVE" title="Mali Core Cycles" name="Compute cycles" description="Number of cycles vertex\compute processing was active"/>
++ <event counter="ARM_Mali-T6xx_FRAG_CYCLE_NO_TILE" title="Mali Core Cycles" name="Fragment cycles waiting for tile" description="Number of cycles spent waiting for a physical tile buffer"/>
++
++ <event counter="ARM_Mali-T6xx_FRAG_THREADS" title="Mali Core Threads" name="Fragment threads" description="Number of fragment threads started"/>
++ <event counter="ARM_Mali-T6xx_FRAG_DUMMY_THREADS" title="Mali Core Threads" name="Dummy fragment threads" description="Number of dummy fragment threads started"/>
++ <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
++ <event counter="ARM_Mali-T6xx_FRAG_QUADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
++ <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_TEST" title="Mali Core Threads" name="Frag threads doing late ZS" description="Number of threads doing late ZS test"/>
++ <event counter="ARM_Mali-T6xx_FRAG_THREADS_LZS_KILLED" title="Mali Core Threads" name="Frag threads killed late ZS" description="Number of threads killed by late ZS test"/>
++
++ <event counter="ARM_Mali-T6xx_COMPUTE_TASKS" title="Mali Compute Threads" name="Compute tasks" description="Number of compute tasks"/>
++ <event counter="ARM_Mali-T6xx_COMPUTE_THREADS" title="Mali Compute Threads" name="Compute threads started" description="Number of compute threads started"/>
++ <event counter="ARM_Mali-T6xx_COMPUTE_CYCLES_DESC" title="Mali Compute Threads" name="Compute cycles awaiting descriptors" description="Number of compute cycles spent waiting for descriptors"/>
++
++ <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
++ <event counter="ARM_Mali-T6xx_FRAG_PRIMATIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
++ <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES" title="Mali Fragment Primitives" name="Primitives loaded" description="Number of primitives loaded from tiler"/>
++ <event counter="ARM_Mali-T6xx_FRAG_PRIMITIVES_DROPPED" title="Mali Fragment Primitives" name="Primitives dropped" description="Number of primitives dropped because out of tile"/>
++
++ <event counter="ARM_Mali-T6xx_FRAG_QUADS_RAST" title="Mali Fragment Quads" name="Quads rasterized" description="Number of quads rasterized"/>
++ <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_TEST" title="Mali Fragment Quads" name="Quads doing early ZS" description="Number of quads doing early ZS test"/>
++ <event counter="ARM_Mali-T6xx_FRAG_QUADS_EZS_KILLED" title="Mali Fragment Quads" name="Quads killed early Z" description="Number of quads killed by early ZS test"/>
++
++ <event counter="ARM_Mali-T6xx_FRAG_NUM_TILES" title="Mali Fragment Tasks" name="Tiles rendered" description="Number of tiles rendered"/>
++ <event counter="ARM_Mali-T6xx_FRAG_TRANS_ELIM" title="Mali Fragment Tasks" name="Tile writes killed by TE" description="Number of tile writes skipped by transaction elimination"/>
++
++ <event counter="ARM_Mali-T6xx_ARITH_WORDS" title="Mali Arithmetic Pipe" name="A instructions" description="Number of instructions completed by the the A-pipe (normalized per pipeline)"/>
++
++ <event counter="ARM_Mali-T6xx_LS_WORDS" title="Mali Load/Store Pipe" name="LS instructions" description="Number of instructions completed by the LS-pipe"/>
++ <event counter="ARM_Mali-T6xx_LS_ISSUES" title="Mali Load/Store Pipe" name="LS instruction issues" description="Number of instructions issued to the LS-pipe, including restarts"/>
++
++ <event counter="ARM_Mali-T6xx_TEX_WORDS" title="Mali Texture Pipe" name="T instructions" description="Number of instructions completed by the T-pipe"/>
++ <event counter="ARM_Mali-T6xx_TEX_THREADS" title="Mali Texture Pipe" name="T instruction issues" description="Number of instructions issused to the T-pipe, including restarts"/>
++ <event counter="ARM_Mali-T6xx_TEX_RECIRC_FMISS" title="Mali Texture Pipe" name="Cache misses" description="Number of instructions in the T-pipe, recirculated due to cache miss"/>
++
++ <event counter="ARM_Mali-T6xx_LSC_READ_HITS" title="Mali Load/Store Cache" name="Read hits" description="Number of read hits in the Load/Store cache"/>
++ <event counter="ARM_Mali-T6xx_LSC_READ_MISSES" title="Mali Load/Store Cache" name="Read misses" description="Number of read misses in the Load/Store cache"/>
++ <event counter="ARM_Mali-T6xx_LSC_WRITE_HITS" title="Mali Load/Store Cache" name="Write hits" description="Number of write hits in the Load/Store cache"/>
++ <event counter="ARM_Mali-T6xx_LSC_WRITE_MISSES" title="Mali Load/Store Cache" name="Write misses" description="Number of write misses in the Load/Store cache"/>
++ <event counter="ARM_Mali-T6xx_LSC_ATOMIC_HITS" title="Mali Load/Store Cache" name="Atomic hits" description="Number of atomic hits in the Load/Store cache"/>
++ <event counter="ARM_Mali-T6xx_LSC_ATOMIC_MISSES" title="Mali Load/Store Cache" name="Atomic misses" description="Number of atomic misses in the Load/Store cache"/>
++ <event counter="ARM_Mali-T6xx_LSC_LINE_FETCHES" title="Mali Load/Store Cache" name="Line fetches" description="Number of line fetches in the Load/Store cache"/>
++ <event counter="ARM_Mali-T6xx_LSC_DIRTY_LINE" title="Mali Load/Store Cache" name="Dirty line evictions" description="Number of dirty line evictions in the Load/Store cache"/>
++ <event counter="ARM_Mali-T6xx_LSC_SNOOPS" title="Mali Load/Store Cache" name="Snoops in to LSC" description="Number of coherent memory snoops in to the Load/Store cache"/>
++
++ </category>
++
++ <category name="Mali-T6xx-L2AndMMU" per_cpu="no">
++
++ <event counter="ARM_Mali-T6xx_L2_WRITE_BEATS" title="Mali L2 Cache" name="External write beats" description="Number of external bus write beats"/>
++ <event counter="ARM_Mali-T6xx_L2_READ_BEATS" title="Mali L2 Cache" name="External read beats" description="Number of external bus read beats"/>
++ <event counter="ARM_Mali-T6xx_L2_READ_SNOOP" title="Mali L2 Cache" name="Read snoops" description="Number of read transaction snoops"/>
++ <event counter="ARM_Mali-T6xx_L2_READ_HIT" title="Mali L2 Cache" name="L2 read hits" description="Number of reads hitting in the L2 cache"/>
++ <event counter="ARM_Mali-T6xx_L2_WRITE_SNOOP" title="Mali L2 Cache" name="Write snoops" description="Number of write transaction snoops"/>
++ <event counter="ARM_Mali-T6xx_L2_WRITE_HIT" title="Mali L2 Cache" name="L2 write hits" description="Number of writes hitting in the L2 cache"/>
++ <event counter="ARM_Mali-T6xx_L2_EXT_AR_STALL" title="Mali L2 Cache" name="External bus stalls (AR)" description="Number of cycles a valid read address (AR) is stalled by the external interconnect"/>
++ <event counter="ARM_Mali-T6xx_L2_EXT_W_STALL" title="Mali L2 Cache" name="External bus stalls (W)" description="Number of cycles a valid write data (W channel) is stalled by the external interconnect"/>
++
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Mali-T6xx.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Mali-T6xx.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Mali-T6xx.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Mali-T6xx.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,48 @@
++
++ <category name="Mali-T6xx-SW-counters" per_cpu="no">
++ <event counter="ARM_Mali-T6xx_TOTAL_ALLOC_PAGES" title="Mali Total Alloc Pages" name="Total number of allocated pages" description="Mali total number of allocated pages."/>
++ </category>
++
++ <category name="Mali-T6xx-PMShader" per_cpu="no">
++ <event counter="ARM_Mali-T6xx_PM_SHADER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 0" description="Mali PM Shader: PM Shader Core 0."/>
++ <event counter="ARM_Mali-T6xx_PM_SHADER_1" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 1" description="Mali PM Shader: PM Shader Core 1."/>
++ <event counter="ARM_Mali-T6xx_PM_SHADER_2" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 2" description="Mali PM Shader: PM Shader Core 2."/>
++ <event counter="ARM_Mali-T6xx_PM_SHADER_3" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 3" description="Mali PM Shader: PM Shader Core 3."/>
++ <event counter="ARM_Mali-T6xx_PM_SHADER_4" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 4" description="Mali PM Shader: PM Shader Core 4."/>
++ <event counter="ARM_Mali-T6xx_PM_SHADER_5" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 5" description="Mali PM Shader: PM Shader Core 5."/>
++ <event counter="ARM_Mali-T6xx_PM_SHADER_6" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 6" description="Mali PM Shader: PM Shader Core 6."/>
++ <event counter="ARM_Mali-T6xx_PM_SHADER_7" display="average" average_selection="yes" percentage="yes" title="Mali PM Shader" name="PM Shader Core 7" description="Mali PM Shader: PM Shader Core 7."/>
++ </category>
++
++ <category name="Mali-T6xx-PMTiler" per_cpu="no">
++ <event counter="ARM_Mali-T6xx_PM_TILER_0" display="average" average_selection="yes" percentage="yes" title="Mali PM Tiler" name="PM Tiler Core 0" description="Mali PM Tiler: PM Tiler Core 0."/>
++ </category>
++
++ <category name="Mali-T6xx-PML2" per_cpu="no">
++ <event counter="ARM_Mali-T6xx_PM_L2_0" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 0" description="Mali PM L2: PM L2 Core 0."/>
++ <event counter="ARM_Mali-T6xx_PM_L2_1" display="average" average_selection="yes" percentage="yes" title="Mali PM L2" name="PM L2 Core 1" description="Mali PM L2: PM L2 Core 1."/>
++ </category>
++
++ <category name="Mali-T6xx-MMU_AS" per_cpu="no">
++ <event counter="ARM_Mali-T6xx_MMU_AS_0" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 0" description="Mali MMU Address Space 0 usage."/>
++ <event counter="ARM_Mali-T6xx_MMU_AS_1" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 1" description="Mali MMU Address Space 1 usage."/>
++ <event counter="ARM_Mali-T6xx_MMU_AS_2" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 2" description="Mali MMU Address Space 2 usage."/>
++ <event counter="ARM_Mali-T6xx_MMU_AS_3" display="average" average_selection="yes" percentage="yes" title="Mali MMU Address Space" name="MMU Address Space 3" description="Mali MMU Address Space 3 usage."/>
++ </category>
++
++ <category name="Mali-T6xx-MMU_page_fault" per_cpu="no">
++ <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_0" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 0" description="Reports the number of newly allocated pages after a MMU page fault in address space 0."/>
++ <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_1" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 1" description="Reports the number of newly allocated pages after a MMU page fault in address space 1."/>
++ <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_2" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 2" description="Reports the number of newly allocated pages after a MMU page fault in address space 2."/>
++ <event counter="ARM_Mali-T6xx_MMU_PAGE_FAULT_3" title="Mali MMU Page Fault Add. Space" name="Mali MMU Page Fault Add. Space 3" description="Reports the number of newly allocated pages after a MMU page fault in address space 3."/>
++ </category>
++
++ <counter_set name="ARM_Mali-T6xx_Filmstrip_cnt" count="1"/>
++ <category name="ARM Mali-T6xx Filmstrip" counter_set="ARM_Mali-T6xx_Filmstrip_cnt" per_cpu="no">
++ <option_set name="fs">
++ <option event_delta="0x3c" name="1:60" description="captures every 60th frame"/>
++ <option event_delta="0x1e" name="1:30" description="captures every 30th frame"/>
++ <option event_delta="0xa" name="1:10" description="captures every 10th frame"/>
++ </option_set>
++ <event event="0x0400" option_set="fs" title="ARM Mali-T6xx" name="Filmstrip" description="Scaled framebuffer"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-ScorpionMP.xml linux-linaro-stable-mx6/tools/gator/daemon/events-ScorpionMP.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-ScorpionMP.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-ScorpionMP.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,90 @@
++ <counter_set name="ScorpionMP_cnt" count="4"/>
++ <category name="ScorpionMP" counter_set="ScorpionMP_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="ScorpionMP_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
++ <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
++ <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
++ <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
++ <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/>
++ <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/>
++ <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/>
++ <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/>
++ <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/>
++ <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/>
++ <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/>
++ <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/>
++ <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/>
++ <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/>
++ <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/>
++ <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/>
++ <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/>
++ <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/>
++ <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/>
++ <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/>
++ <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/>
++ <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/>
++ <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/>
++ <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/>
++ <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/>
++ <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/>
++ <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/>
++ <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/>
++ <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/>
++ <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/>
++ <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/>
++ <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/>
++ <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/>
++ <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/>
++ <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/>
++ <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/>
++ <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/>
++ <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/>
++ <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/>
++ <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/>
++ <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/>
++ <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/>
++ <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/>
++ <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/>
++ <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/>
++ <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/>
++ <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/>
++ <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/>
++ <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/>
++ <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/>
++ <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/>
++ <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/>
++ <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/>
++ <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/>
++ <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/>
++ <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/>
++ <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/>
++ <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/>
++ <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/>
++ <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/>
++ <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/>
++ <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/>
++ <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/>
++ <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/>
++ <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/>
++ <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/>
++ <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/>
++ <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/>
++ <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/>
++ <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/>
++ <event event="0x8e" title="ScorpionMP" name="NUM_BARRIERS" description="Barriers"/>
++ <event event="0x8f" title="ScorpionMP" name="BARRIER_CYCLES" description="Barrier cycles"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/events-Scorpion.xml linux-linaro-stable-mx6/tools/gator/daemon/events-Scorpion.xml
+--- linux-3.10.30.orig/tools/gator/daemon/events-Scorpion.xml 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/events-Scorpion.xml 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,107 @@
++ <counter_set name="Scorpion_cnt" count="4"/>
++ <category name="Scorpion" counter_set="Scorpion_cnt" per_cpu="yes" supports_event_based_sampling="yes">
++ <event counter="Scorpion_ccnt" event="0xff" title="Clock" name="Cycles" display="hertz" units="Hz" average_selection="yes" average_cores="yes" description="The number of core clock cycles"/>
++ <event event="0x00" title="Software" name="Increment" description="Incremented only on writes to the Software Increment Register"/>
++ <event event="0x01" title="Cache" name="Instruction refill" description="Instruction fetch that causes a refill of at least the level of instruction or unified cache closest to the processor"/>
++ <event event="0x02" title="Cache" name="Inst TLB refill" description="Instruction fetch that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x03" title="Cache" name="Data refill" description="Memory Read or Write operation that causes a refill of at least the level of data or unified cache closest to the processor"/>
++ <event event="0x04" title="Cache" name="Data access" description="Memory Read or Write operation that causes a cache access to at least the level of data or unified cache closest to the processor"/>
++ <event event="0x05" title="Cache" name="Data TLB refill" description="Memory Read or Write operation that causes a TLB refill of at least the level of TLB closest to the processor"/>
++ <event event="0x06" title="Instruction" name="Memory read" description="Memory-reading instruction architecturally executed"/>
++ <event event="0x07" title="Instruction" name="Memory write" description="Memory-writing instruction architecturally executed"/>
++ <event event="0x08" title="Instruction" name="Executed" description="Instruction architecturally executed"/>
++ <event event="0x09" title="Exception" name="Taken" description="Exceptions taken"/>
++ <event event="0x0a" title="Exception" name="Return" description="Exception return architecturally executed"/>
++ <event event="0x0b" title="Instruction" name="CONTEXTIDR" description="Instruction that writes to the CONTEXTIDR architecturally executed"/>
++ <event event="0x0c" title="Program Counter" name="SW change" description="Software change of PC, except by an exception, architecturally executed"/>
++ <event event="0x0d" title="Branch" name="Immediate" description="Immediate branch architecturally executed"/>
++ <event event="0x0e" title="Branch" name="Procedure Return" description="Procedure return architecturally executed (not by exceptions)"/>
++ <event event="0x0f" title="Memory" name="Unaligned access" description="Unaligned access architecturally executed"/>
++ <event event="0x10" title="Branch" name="Mispredicted" description="Branch mispredicted or not predicted"/>
++ <event event="0x12" title="Branch" name="Potential prediction" description="Branch or other change in program flow that could have been predicted by the branch prediction resources of the processor"/>
++ <event event="0x4c" title="Scorpion" name="ICACHE_EXPL_INV" description="I-cache explicit invalidates"/>
++ <event event="0x4d" title="Scorpion" name="ICACHE_MISS" description="I-cache misses"/>
++ <event event="0x4e" title="Scorpion" name="ICACHE_ACCESS" description="I-cache accesses"/>
++ <event event="0x4f" title="Scorpion" name="ICACHE_CACHEREQ_L2" description="I-cache cacheable requests to L2"/>
++ <event event="0x50" title="Scorpion" name="ICACHE_NOCACHE_L2" description="I-cache non-cacheable requests to L2"/>
++ <event event="0x51" title="Scorpion" name="HIQUP_NOPED" description="Conditional instructions HIQUPs NOPed"/>
++ <event event="0x52" title="Scorpion" name="DATA_ABORT" description="Interrupts and Exceptions Data Abort"/>
++ <event event="0x53" title="Scorpion" name="IRQ" description="Interrupts and Exceptions IRQ"/>
++ <event event="0x54" title="Scorpion" name="FIQ" description="Interrupts and Exceptions FIQ"/>
++ <event event="0x55" title="Scorpion" name="ALL_EXCPT" description="Interrupts and Exceptions All interrupts"/>
++ <event event="0x56" title="Scorpion" name="UNDEF" description="Interrupts and Exceptions Undefined"/>
++ <event event="0x57" title="Scorpion" name="SVC" description="Interrupts and Exceptions SVC"/>
++ <event event="0x58" title="Scorpion" name="SMC" description="Interrupts and Exceptions SMC"/>
++ <event event="0x59" title="Scorpion" name="PREFETCH_ABORT" description="Interrupts and Exceptions Prefetch Abort"/>
++ <event event="0x5a" title="Scorpion" name="INDEX_CHECK" description="Interrupts and Exceptions Index Check"/>
++ <event event="0x5b" title="Scorpion" name="NULL_CHECK" description="Interrupts and Exceptions Null Check"/>
++ <event event="0x5c" title="Scorpion" name="EXPL_ICIALLU" description="I-cache and BTAC Invalidates Explicit ICIALLU"/>
++ <event event="0x5d" title="Scorpion" name="IMPL_ICIALLU" description="I-cache and BTAC Invalidates Implicit ICIALLU"/>
++ <event event="0x5e" title="Scorpion" name="NONICIALLU_BTAC_INV" description="I-cache and BTAC Invalidates Non-ICIALLU BTAC Invalidate"/>
++ <event event="0x5f" title="Scorpion" name="ICIMVAU_IMPL_ICIALLU" description="I-cache and BTAC Invalidates ICIMVAU-implied ICIALLU"/>
++ <event event="0x60" title="Scorpion" name="SPIPE_ONLY_CYCLES" description="Issue S-pipe only issue cycles"/>
++ <event event="0x61" title="Scorpion" name="XPIPE_ONLY_CYCLES" description="Issue X-pipe only issue cycles"/>
++ <event event="0x62" title="Scorpion" name="DUAL_CYCLES" description="Issue dual issue cycles"/>
++ <event event="0x63" title="Scorpion" name="DISPATCH_ANY_CYCLES" description="Dispatch any dispatch cycles"/>
++ <event event="0x64" title="Scorpion" name="FIFO_FULLBLK_CMT" description="Commits Trace FIFO full Blk CMT"/>
++ <event event="0x65" title="Scorpion" name="FAIL_COND_INST" description="Conditional instructions failing conditional instrs (excluding branches)"/>
++ <event event="0x66" title="Scorpion" name="PASS_COND_INST" description="Conditional instructions passing conditional instrs (excluding branches)"/>
++ <event event="0x67" title="Scorpion" name="ALLOW_VU_CLK" description="Unit Clock Gating Allow VU Clks"/>
++ <event event="0x68" title="Scorpion" name="VU_IDLE" description="Unit Clock Gating VU Idle"/>
++ <event event="0x69" title="Scorpion" name="ALLOW_L2_CLK" description="Unit Clock Gating Allow L2 Clks"/>
++ <event event="0x6a" title="Scorpion" name="L2_IDLE" description="Unit Clock Gating L2 Idle"/>
++ <event event="0x6b" title="Scorpion" name="DTLB_IMPL_INV_SCTLR_DACR" description="DTLB implicit invalidates writes to SCTLR and DACR"/>
++ <event event="0x6c" title="Scorpion" name="DTLB_EXPL_INV" description="DTLB explicit invalidates"/>
++ <event event="0x6d" title="Scorpion" name="DTLB_MISS" description="DTLB misses"/>
++ <event event="0x6e" title="Scorpion" name="DTLB_ACCESS" description="DTLB accesses"/>
++ <event event="0x6f" title="Scorpion" name="ITLB_MISS" description="ITLB misses"/>
++ <event event="0x70" title="Scorpion" name="ITLB_IMPL_INV" description="ITLB implicit ITLB invalidates"/>
++ <event event="0x71" title="Scorpion" name="ITLB_EXPL_INV" description="ITLB explicit ITLB invalidates"/>
++ <event event="0x72" title="Scorpion" name="UTLB_D_MISS" description="UTLB d-side misses"/>
++ <event event="0x73" title="Scorpion" name="UTLB_D_ACCESS" description="UTLB d-side accesses"/>
++ <event event="0x74" title="Scorpion" name="UTLB_I_MISS" description="UTLB i-side misses"/>
++ <event event="0x75" title="Scorpion" name="UTLB_I_ACCESS" description="UTLB i-side accesses"/>
++ <event event="0x76" title="Scorpion" name="UTLB_INV_ASID" description="UTLB invalidate by ASID"/>
++ <event event="0x77" title="Scorpion" name="UTLB_INV_MVA" description="UTLB invalidate by MVA"/>
++ <event event="0x78" title="Scorpion" name="UTLB_INV_ALL" description="UTLB invalidate all"/>
++ <event event="0x79" title="Scorpion" name="S2_HOLD_RDQ_UNAVAIL" description="S2 hold RDQ unavail"/>
++ <event event="0x7a" title="Scorpion" name="S2_HOLD" description="S2 hold"/>
++ <event event="0x7b" title="Scorpion" name="S2_HOLD_DEV_OP" description="S2 hold device op"/>
++ <event event="0x7c" title="Scorpion" name="S2_HOLD_ORDER" description="S2 hold strongly ordered op"/>
++ <event event="0x7d" title="Scorpion" name="S2_HOLD_BARRIER" description="S2 hold barrier"/>
++ <event event="0x7e" title="Scorpion" name="VIU_DUAL_CYCLE" description="Scorpion VIU dual cycle"/>
++ <event event="0x7f" title="Scorpion" name="VIU_SINGLE_CYCLE" description="Scorpion VIU single cycle"/>
++ <event event="0x80" title="Scorpion" name="VX_PIPE_WAR_STALL_CYCLES" description="Scorpion VX pipe WAR cycles"/>
++ <event event="0x81" title="Scorpion" name="VX_PIPE_WAW_STALL_CYCLES" description="Scorpion VX pipe WAW cycles"/>
++ <event event="0x82" title="Scorpion" name="VX_PIPE_RAW_STALL_CYCLES" description="Scorpion VX pipe RAW cycles"/>
++ <event event="0x83" title="Scorpion" name="VX_PIPE_LOAD_USE_STALL" description="Scorpion VX pipe load use stall"/>
++ <event event="0x84" title="Scorpion" name="VS_PIPE_WAR_STALL_CYCLES" description="Scorpion VS pipe WAR stall cycles"/>
++ <event event="0x85" title="Scorpion" name="VS_PIPE_WAW_STALL_CYCLES" description="Scorpion VS pipe WAW stall cycles"/>
++ <event event="0x86" title="Scorpion" name="VS_PIPE_RAW_STALL_CYCLES" description="Scorpion VS pipe RAW stall cycles"/>
++ <event event="0x87" title="Scorpion" name="EXCEPTIONS_INV_OPERATION" description="Scorpion invalid operation exceptions"/>
++ <event event="0x88" title="Scorpion" name="EXCEPTIONS_DIV_BY_ZERO" description="Scorpion divide by zero exceptions"/>
++ <event event="0x89" title="Scorpion" name="COND_INST_FAIL_VX_PIPE" description="Scorpion conditional instruction fail VX pipe"/>
++ <event event="0x8a" title="Scorpion" name="COND_INST_FAIL_VS_PIPE" description="Scorpion conditional instruction fail VS pipe"/>
++ <event event="0x8b" title="Scorpion" name="EXCEPTIONS_OVERFLOW" description="Scorpion overflow exceptions"/>
++ <event event="0x8c" title="Scorpion" name="EXCEPTIONS_UNDERFLOW" description="Scorpion underflow exceptions"/>
++ <event event="0x8d" title="Scorpion" name="EXCEPTIONS_DENORM" description="Scorpion denorm exceptions"/>
++ <event event="0x8e" title="Scorpion" name="BANK_AB_HIT" description="L2 hit rates bank A/B hits"/>
++ <event event="0x8f" title="Scorpion" name="BANK_AB_ACCESS" description="L2 hit rates bank A/B accesses"/>
++ <event event="0x90" title="Scorpion" name="BANK_CD_HIT" description="L2 hit rates bank C/D hits"/>
++ <event event="0x91" title="Scorpion" name="BANK_CD_ACCESS" description="L2 hit rates bank C/D accesses"/>
++ <event event="0x92" title="Scorpion" name="BANK_AB_DSIDE_HIT" description="L2 hit rates bank A/B d-side hits"/>
++ <event event="0x93" title="Scorpion" name="BANK_AB_DSIDE_ACCESS" description="L2 hit rates bank A/B d-side accesses"/>
++ <event event="0x94" title="Scorpion" name="BANK_CD_DSIDE_HIT" description="L2 hit rates bank C/D d-side hits"/>
++ <event event="0x95" title="Scorpion" name="BANK_CD_DSIDE_ACCESS" description="L2 hit rates bank C/D d-side accesses"/>
++ <event event="0x96" title="Scorpion" name="BANK_AB_ISIDE_HIT" description="L2 hit rates bank A/B i-side hits"/>
++ <event event="0x97" title="Scorpion" name="BANK_AB_ISIDE_ACCESS" description="L2 hit rates bank A/B i-side accesses"/>
++ <event event="0x98" title="Scorpion" name="BANK_CD_ISIDE_HIT" description="L2 hit rates bank C/D i-side hits"/>
++ <event event="0x99" title="Scorpion" name="BANK_CD_ISIDE_ACCESS" description="L2 hit rates bank C/D i-side accesses"/>
++ <event event="0x9a" title="Scorpion" name="ISIDE_RD_WAIT" description="fills and castouts cycles that i-side RD requests wait on data from bus"/>
++ <event event="0x9b" title="Scorpion" name="DSIDE_RD_WAIT" description="fills and castouts cycles that d-side RD requests wait on data from bus"/>
++ <event event="0x9c" title="Scorpion" name="BANK_BYPASS_WRITE" description="fills and castouts bank bypass writes"/>
++ <event event="0x9d" title="Scorpion" name="BANK_AB_NON_CASTOUT" description="fills and castouts bank A/B non-castout writes to bus"/>
++ <event event="0x9e" title="Scorpion" name="BANK_AB_L2_CASTOUT" description="fills and castouts bank A/B L2 castouts (granules)"/>
++ <event event="0x9f" title="Scorpion" name="BANK_CD_NON_CASTOUT" description="fills and castouts bank C/D non-castout writes to bus"/>
++ <event event="0xa0" title="Scorpion" name="BANK_CD_L2_CASTOUT" description="fills and castouts bank C/D L2 castouts (granules)"/>
++ </category>
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/EventsXML.cpp linux-linaro-stable-mx6/tools/gator/daemon/EventsXML.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/EventsXML.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/EventsXML.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,70 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "EventsXML.h"
++
++#include "CapturedXML.h"
++#include "Logging.h"
++#include "OlyUtility.h"
++#include "SessionData.h"
++
++char* EventsXML::getXML() {
++#include "events_xml.h" // defines and initializes char events_xml[] and int events_xml_len
++ char path[PATH_MAX];
++ mxml_node_t *xml;
++ FILE *fl;
++
++ // Avoid unused variable warning
++ (void)events_xml_len;
++
++ // Load the provided or default events xml
++ if (gSessionData->mEventsXMLPath) {
++ strncpy(path, gSessionData->mEventsXMLPath, PATH_MAX);
++ } else {
++ util->getApplicationFullPath(path, PATH_MAX);
++ strncat(path, "events.xml", PATH_MAX - strlen(path) - 1);
++ }
++ fl = fopen(path, "r");
++ if (fl) {
++ xml = mxmlLoadFile(NULL, fl, MXML_NO_CALLBACK);
++ fclose(fl);
++ } else {
++ logg->logMessage("Unable to locate events.xml, using default");
++ xml = mxmlLoadString(NULL, (char *)events_xml, MXML_NO_CALLBACK);
++ }
++
++ // Add dynamic events from the drivers
++ mxml_node_t *events = mxmlFindElement(xml, xml, "events", NULL, NULL, MXML_DESCEND);
++ if (!events) {
++ logg->logMessage("Unable to find <events> node in the events.xml");
++ handleException();
++ }
++ for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
++ driver->writeEvents(events);
++ }
++
++ char* string = mxmlSaveAllocString(xml, mxmlWhitespaceCB);
++ mxmlDelete(xml);
++
++ return string;
++}
++
++void EventsXML::write(const char* path) {
++ char file[PATH_MAX];
++
++ // Set full path
++ snprintf(file, PATH_MAX, "%s/events.xml", path);
++
++ char* buf = getXML();
++ if (util->writeToDisk(file, buf) < 0) {
++ logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
++ handleException();
++ }
++
++ free(buf);
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/EventsXML.h linux-linaro-stable-mx6/tools/gator/daemon/EventsXML.h
+--- linux-3.10.30.orig/tools/gator/daemon/EventsXML.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/EventsXML.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,18 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef EVENTS_XML
++#define EVENTS_XML
++
++class EventsXML {
++public:
++ char* getXML();
++ void write(const char* path);
++};
++
++#endif // EVENTS_XML
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Fifo.cpp linux-linaro-stable-mx6/tools/gator/daemon/Fifo.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/Fifo.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Fifo.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,130 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "Fifo.h"
++
++#include <stdlib.h>
++#ifdef WIN32
++#define valloc malloc
++#endif
++
++#include "Logging.h"
++
++// bufferSize is the amount of data to be filled
++// singleBufferSize is the maximum size that may be filled during a single write
++// (bufferSize + singleBufferSize) will be allocated
++Fifo::Fifo(int singleBufferSize, int bufferSize, sem_t* readerSem) {
++ mWrite = mRead = mReadCommit = mRaggedEnd = 0;
++ mWrapThreshold = bufferSize;
++ mSingleBufferSize = singleBufferSize;
++ mReaderSem = readerSem;
++ mBuffer = (char*)valloc(bufferSize + singleBufferSize);
++ mEnd = false;
++
++ if (mBuffer == NULL) {
++ logg->logError(__FILE__, __LINE__, "failed to allocate %d bytes", bufferSize + singleBufferSize);
++ handleException();
++ }
++
++ if (sem_init(&mWaitForSpaceSem, 0, 0)) {
++ logg->logError(__FILE__, __LINE__, "sem_init() failed");
++ handleException();
++ }
++}
++
++Fifo::~Fifo() {
++ free(mBuffer);
++ sem_destroy(&mWaitForSpaceSem);
++}
++
++int Fifo::numBytesFilled() const {
++ return mWrite - mRead + mRaggedEnd;
++}
++
++char* Fifo::start() const {
++ return mBuffer;
++}
++
++bool Fifo::isEmpty() const {
++ return mRead == mWrite && mRaggedEnd == 0;
++}
++
++bool Fifo::isFull() const {
++ return willFill(0);
++}
++
++// Determines if the buffer will fill assuming 'additional' bytes will be added to the buffer
++// 'full' means there is less than singleBufferSize bytes available contiguously; it does not mean there are zero bytes available
++bool Fifo::willFill(int additional) const {
++ if (mWrite > mRead) {
++ if (numBytesFilled() + additional < mWrapThreshold) {
++ return false;
++ }
++ } else {
++ if (numBytesFilled() + additional < mWrapThreshold - mSingleBufferSize) {
++ return false;
++ }
++ }
++ return true;
++}
++
++// This function will stall until contiguous singleBufferSize bytes are available
++char* Fifo::write(int length) {
++ if (length <= 0) {
++ length = 0;
++ mEnd = true;
++ }
++
++ // update the write pointer
++ mWrite += length;
++
++ // handle the wrap-around
++ if (mWrite >= mWrapThreshold) {
++ mRaggedEnd = mWrite;
++ mWrite = 0;
++ }
++
++ // send a notification that data is ready
++ sem_post(mReaderSem);
++
++ // wait for space
++ while (isFull()) {
++ sem_wait(&mWaitForSpaceSem);
++ }
++
++ return &mBuffer[mWrite];
++}
++
++void Fifo::release() {
++ // update the read pointer now that the data has been handled
++ mRead = mReadCommit;
++
++ // handle the wrap-around
++ if (mRead >= mWrapThreshold) {
++ mRaggedEnd = mRead = mReadCommit = 0;
++ }
++
++ // send a notification that data is free (space is available)
++ sem_post(&mWaitForSpaceSem);
++}
++
++// This function will return null if no data is available
++char* Fifo::read(int *const length) {
++ // wait for data
++ if (isEmpty() && !mEnd) {
++ return NULL;
++ }
++
++ // obtain the length
++ do {
++ mReadCommit = mRaggedEnd ? mRaggedEnd : mWrite;
++ *length = mReadCommit - mRead;
++ } while (*length < 0); // plugs race condition without using semaphores
++
++ return &mBuffer[mRead];
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Fifo.h linux-linaro-stable-mx6/tools/gator/daemon/Fifo.h
+--- linux-3.10.30.orig/tools/gator/daemon/Fifo.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Fifo.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,48 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __FIFO_H__
++#define __FIFO_H__
++
++#ifdef WIN32
++#include <windows.h>
++#define sem_t HANDLE
++#define sem_init(sem, pshared, value) ((*(sem) = CreateSemaphore(NULL, value, INFINITE, NULL)) == NULL)
++#define sem_wait(sem) WaitForSingleObject(*(sem), INFINITE)
++#define sem_post(sem) ReleaseSemaphore(*(sem), 1, NULL)
++#define sem_destroy(sem) CloseHandle(*(sem))
++#else
++#include <semaphore.h>
++#endif
++
++class Fifo {
++public:
++ Fifo(int singleBufferSize, int totalBufferSize, sem_t* readerSem);
++ ~Fifo();
++ int numBytesFilled() const;
++ bool isEmpty() const;
++ bool isFull() const;
++ bool willFill(int additional) const;
++ char* start() const;
++ char* write(int length);
++ void release();
++ char* read(int *const length);
++
++private:
++ int mSingleBufferSize, mWrite, mRead, mReadCommit, mRaggedEnd, mWrapThreshold;
++ sem_t mWaitForSpaceSem;
++ sem_t* mReaderSem;
++ char* mBuffer;
++ bool mEnd;
++
++ // Intentionally unimplemented
++ Fifo(const Fifo &);
++ Fifo &operator=(const Fifo &);
++};
++
++#endif //__FIFO_H__
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Hwmon.cpp linux-linaro-stable-mx6/tools/gator/daemon/Hwmon.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/Hwmon.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Hwmon.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,330 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "Hwmon.h"
++
++#include "libsensors/sensors.h"
++
++#include "Buffer.h"
++#include "Counter.h"
++#include "Logging.h"
++#include "SessionData.h"
++
++class HwmonCounter {
++public:
++ HwmonCounter(HwmonCounter *next, int key, const sensors_chip_name *chip, const sensors_feature *feature);
++ ~HwmonCounter();
++
++ HwmonCounter *getNext() const { return next; }
++ int getKey() const { return key; }
++ bool isEnabled() const { return enabled; }
++ const char *getName() const { return name; }
++ const char *getLabel() const { return label; }
++ const char *getTitle() const { return title; }
++ bool isDuplicate() const { return duplicate; }
++ const char *getDisplay() const { return display; }
++ const char *getUnit() const { return unit; }
++ int getModifier() const { return modifier; }
++
++ void setEnabled(const bool enabled) {
++ this->enabled = enabled;
++ // canRead will clear enabled if the counter is not readable
++ canRead();
++ }
++
++ double read();
++ bool canRead();
++
++private:
++ void init(const sensors_chip_name *chip, const sensors_feature *feature);
++
++ HwmonCounter *const next;
++ const int key;
++ int polled : 1,
++ readable : 1,
++ enabled : 1,
++ monotonic: 1,
++ duplicate : 1;
++
++ const sensors_chip_name *chip;
++ const sensors_feature *feature;
++
++ char *name;
++ char *label;
++ const char *title;
++ const char *display;
++ const char *unit;
++ int modifier;
++ double previous_value;
++
++ sensors_subfeature_type input;
++
++ // Intentionally unimplemented
++ HwmonCounter(const HwmonCounter &);
++ HwmonCounter &operator=(const HwmonCounter &);
++};
++
++HwmonCounter::HwmonCounter(HwmonCounter *next, int key, const sensors_chip_name *chip, const sensors_feature *feature) : next(next), key(key), polled(false), readable(false), enabled(false), duplicate(false), chip(chip), feature(feature) {
++
++ int len = sensors_snprintf_chip_name(NULL, 0, chip) + 1;
++ char *chip_name = new char[len];
++ sensors_snprintf_chip_name(chip_name, len, chip);
++
++ len = snprintf(NULL, 0, "hwmon_%s_%d", chip_name, feature->number) + 1;
++ name = new char[len];
++ snprintf(name, len, "hwmon_%s_%d", chip_name, feature->number);
++
++ delete [] chip_name;
++
++ label = sensors_get_label(chip, feature);
++
++ switch (feature->type) {
++ case SENSORS_FEATURE_IN:
++ title = "Voltage";
++ input = SENSORS_SUBFEATURE_IN_INPUT;
++ display = "average";
++ unit = "V";
++ modifier = 1000;
++ monotonic = false;
++ break;
++ case SENSORS_FEATURE_FAN:
++ title = "Fan";
++ input = SENSORS_SUBFEATURE_FAN_INPUT;
++ display = "average";
++ unit = "RPM";
++ modifier = 1;
++ monotonic = false;
++ break;
++ case SENSORS_FEATURE_TEMP:
++ title = "Temperature";
++ input = SENSORS_SUBFEATURE_TEMP_INPUT;
++ display = "maximum";
++ unit = "°C";
++ modifier = 1000;
++ monotonic = false;
++ break;
++ case SENSORS_FEATURE_POWER:
++ title = "Power";
++ input = SENSORS_SUBFEATURE_POWER_INPUT;
++ display = "average";
++ unit = "W";
++ modifier = 1000000;
++ monotonic = false;
++ break;
++ case SENSORS_FEATURE_ENERGY:
++ title = "Energy";
++ input = SENSORS_SUBFEATURE_ENERGY_INPUT;
++ display = "accumulate";
++ unit = "J";
++ modifier = 1000000;
++ monotonic = true;
++ break;
++ case SENSORS_FEATURE_CURR:
++ title = "Current";
++ input = SENSORS_SUBFEATURE_CURR_INPUT;
++ display = "average";
++ unit = "A";
++ modifier = 1000;
++ monotonic = false;
++ break;
++ case SENSORS_FEATURE_HUMIDITY:
++ title = "Humidity";
++ input = SENSORS_SUBFEATURE_HUMIDITY_INPUT;
++ display = "average";
++ unit = "%";
++ modifier = 1000;
++ monotonic = false;
++ break;
++ default:
++ logg->logError(__FILE__, __LINE__, "Unsupported hwmon feature %i", feature->type);
++ handleException();
++ }
++
++ for (HwmonCounter * counter = next; counter != NULL; counter = counter->getNext()) {
++ if (strcmp(label, counter->getLabel()) == 0 && strcmp(title, counter->getTitle()) == 0) {
++ duplicate = true;
++ counter->duplicate = true;
++ break;
++ }
++ }
++}
++
++HwmonCounter::~HwmonCounter() {
++ free((void *)label);
++ delete [] name;
++}
++
++double HwmonCounter::read() {
++ double value;
++ double result;
++ const sensors_subfeature *subfeature;
++
++ // Keep in sync with canRead
++ subfeature = sensors_get_subfeature(chip, feature, input);
++ if (!subfeature) {
++ logg->logError(__FILE__, __LINE__, "No input value for hwmon sensor %s", label);
++ handleException();
++ }
++
++ if (sensors_get_value(chip, subfeature->number, &value) != 0) {
++ logg->logError(__FILE__, __LINE__, "Can't get input value for hwmon sensor %s", label);
++ handleException();
++ }
++
++ result = (monotonic ? value - previous_value : value);
++ previous_value = value;
++
++ return result;
++}
++
++bool HwmonCounter::canRead() {
++ if (!polled) {
++ double value;
++ const sensors_subfeature *subfeature;
++ bool result = true;
++
++ subfeature = sensors_get_subfeature(chip, feature, input);
++ if (!subfeature) {
++ result = false;
++ } else {
++ result = sensors_get_value(chip, subfeature->number, &value) == 0;
++ }
++
++ polled = true;
++ readable = result;
++ }
++
++ enabled &= readable;
++
++ return readable;
++}
++
++Hwmon::Hwmon() : counters(NULL) {
++ int err = sensors_init(NULL);
++ if (err) {
++ logg->logMessage("Failed to initialize libsensors! (%d)", err);
++ return;
++ }
++ sensors_sysfs_no_scaling = 1;
++
++ int chip_nr = 0;
++ const sensors_chip_name *chip;
++ while ((chip = sensors_get_detected_chips(NULL, &chip_nr))) {
++ int feature_nr = 0;
++ const sensors_feature *feature;
++ while ((feature = sensors_get_features(chip, &feature_nr))) {
++ counters = new HwmonCounter(counters, getEventKey(), chip, feature);
++ }
++ }
++}
++
++Hwmon::~Hwmon() {
++ while (counters != NULL) {
++ HwmonCounter * counter = counters;
++ counters = counter->getNext();
++ delete counter;
++ }
++ sensors_cleanup();
++}
++
++HwmonCounter *Hwmon::findCounter(const Counter &counter) const {
++ for (HwmonCounter * hwmonCounter = counters; hwmonCounter != NULL; hwmonCounter = hwmonCounter->getNext()) {
++ if (hwmonCounter->canRead() && strcmp(hwmonCounter->getName(), counter.getType()) == 0) {
++ return hwmonCounter;
++ }
++ }
++
++ return NULL;
++}
++
++bool Hwmon::claimCounter(const Counter &counter) const {
++ return findCounter(counter) != NULL;
++}
++
++bool Hwmon::countersEnabled() const {
++ for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
++ if (counter->isEnabled()) {
++ return true;
++ }
++ }
++ return false;
++}
++
++void Hwmon::resetCounters() {
++ for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
++ counter->setEnabled(false);
++ }
++}
++
++void Hwmon::setupCounter(Counter &counter) {
++ HwmonCounter *const hwmonCounter = findCounter(counter);
++ if (hwmonCounter == NULL) {
++ counter.setEnabled(false);
++ return;
++ }
++ hwmonCounter->setEnabled(true);
++ counter.setKey(hwmonCounter->getKey());
++}
++
++void Hwmon::writeCounters(mxml_node_t *root) const {
++ for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
++ if (!counter->canRead()) {
++ continue;
++ }
++ mxml_node_t *node = mxmlNewElement(root, "counter");
++ mxmlElementSetAttr(node, "name", counter->getName());
++ }
++}
++
++void Hwmon::writeEvents(mxml_node_t *root) const {
++ root = mxmlNewElement(root, "category");
++ mxmlElementSetAttr(root, "name", "hwmon");
++
++ char buf[1024];
++ for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
++ if (!counter->canRead()) {
++ continue;
++ }
++ mxml_node_t *node = mxmlNewElement(root, "event");
++ mxmlElementSetAttr(node, "counter", counter->getName());
++ mxmlElementSetAttr(node, "title", counter->getTitle());
++ if (counter->isDuplicate()) {
++ mxmlElementSetAttrf(node, "name", "%s (0x%x)", counter->getLabel(), counter->getKey());
++ } else {
++ mxmlElementSetAttr(node, "name", counter->getLabel());
++ }
++ mxmlElementSetAttr(node, "display", counter->getDisplay());
++ mxmlElementSetAttr(node, "units", counter->getUnit());
++ if (counter->getModifier() != 1) {
++ mxmlElementSetAttrf(node, "modifier", "%d", counter->getModifier());
++ }
++ if (strcmp(counter->getDisplay(), "average") == 0 || strcmp(counter->getDisplay(), "maximum") == 0) {
++ mxmlElementSetAttr(node, "average_selection", "yes");
++ }
++ snprintf(buf, sizeof(buf), "libsensors %s sensor %s (%s)", counter->getTitle(), counter->getLabel(), counter->getName());
++ mxmlElementSetAttr(node, "description", buf);
++ }
++}
++
++void Hwmon::start() {
++ for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
++ if (!counter->isEnabled()) {
++ continue;
++ }
++ counter->read();
++ }
++}
++
++void Hwmon::read(Buffer * const buffer) {
++ for (HwmonCounter * counter = counters; counter != NULL; counter = counter->getNext()) {
++ if (!counter->isEnabled()) {
++ continue;
++ }
++ buffer->event(counter->getKey(), counter->read());
++ }
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Hwmon.h linux-linaro-stable-mx6/tools/gator/daemon/Hwmon.h
+--- linux-3.10.30.orig/tools/gator/daemon/Hwmon.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Hwmon.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,43 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef HWMON_H
++#define HWMON_H
++
++#include "Driver.h"
++
++class Buffer;
++class HwmonCounter;
++
++class Hwmon : public Driver {
++public:
++ Hwmon();
++ ~Hwmon();
++
++ bool claimCounter(const Counter &counter) const;
++ bool countersEnabled() const;
++ void resetCounters();
++ void setupCounter(Counter &counter);
++
++ void writeCounters(mxml_node_t *root) const;
++ void writeEvents(mxml_node_t *root) const;
++
++ void start();
++ void read(Buffer * buffer);
++
++private:
++ HwmonCounter *findCounter(const Counter &counter) const;
++
++ HwmonCounter *counters;
++
++ // Intentionally unimplemented
++ Hwmon(const Hwmon &);
++ Hwmon &operator=(const Hwmon &);
++};
++
++#endif // HWMON_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/KMod.cpp linux-linaro-stable-mx6/tools/gator/daemon/KMod.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/KMod.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/KMod.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,102 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "KMod.h"
++
++#include <sys/types.h>
++#include <dirent.h>
++#include <unistd.h>
++
++#include "Collector.h"
++#include "ConfigurationXML.h"
++#include "Counter.h"
++#include "Logging.h"
++
++// Claim all the counters in /dev/gator/events
++bool KMod::claimCounter(const Counter &counter) const {
++ char text[128];
++ snprintf(text, sizeof(text), "/dev/gator/events/%s", counter.getType());
++ return access(text, F_OK) == 0;
++}
++
++void KMod::resetCounters() {
++ char base[128];
++ char text[128];
++
++ // Initialize all perf counters in the driver, i.e. set enabled to zero
++ struct dirent *ent;
++ DIR* dir = opendir("/dev/gator/events");
++ if (dir) {
++ while ((ent = readdir(dir)) != NULL) {
++ // skip hidden files, current dir, and parent dir
++ if (ent->d_name[0] == '.')
++ continue;
++ snprintf(base, sizeof(base), "/dev/gator/events/%s", ent->d_name);
++ snprintf(text, sizeof(text), "%s/enabled", base);
++ Collector::writeDriver(text, 0);
++ snprintf(text, sizeof(text), "%s/count", base);
++ Collector::writeDriver(text, 0);
++ }
++ closedir(dir);
++ }
++}
++
++void KMod::setupCounter(Counter &counter) {
++ char base[128];
++ char text[128];
++ snprintf(base, sizeof(base), "/dev/gator/events/%s", counter.getType());
++
++ snprintf(text, sizeof(text), "%s/enabled", base);
++ int enabled = true;
++ if (Collector::writeReadDriver(text, &enabled) || !enabled) {
++ counter.setEnabled(false);
++ return;
++ }
++
++ snprintf(text, sizeof(text), "%s/key", base);
++ int key = 0;
++ Collector::readIntDriver(text, &key);
++ counter.setKey(key);
++
++ snprintf(text, sizeof(text), "%s/event", base);
++ Collector::writeDriver(text, counter.getEvent());
++ snprintf(text, sizeof(text), "%s/count", base);
++ if (access(text, F_OK) == 0) {
++ int count = counter.getCount();
++ if (Collector::writeReadDriver(text, &count) && counter.getCount() > 0) {
++ logg->logError(__FILE__, __LINE__, "Cannot enable EBS for %s:%i with a count of %d\n", counter.getType(), counter.getEvent(), counter.getCount());
++ handleException();
++ }
++ counter.setCount(count);
++ } else if (counter.getCount() > 0) {
++ ConfigurationXML::remove();
++ logg->logError(__FILE__, __LINE__, "Event Based Sampling is only supported with kernel versions 3.0.0 and higher with CONFIG_PERF_EVENTS=y, and CONFIG_HW_PERF_EVENTS=y. The invalid configuration.xml has been removed.\n");
++ handleException();
++ }
++}
++
++void KMod::writeCounters(mxml_node_t *root) const {
++ struct dirent *ent;
++ mxml_node_t *counter;
++
++ // counters.xml is simply a file listing of /dev/gator/events
++ DIR* dir = opendir("/dev/gator/events");
++ if (dir == NULL) {
++ logg->logError(__FILE__, __LINE__, "Cannot create counters.xml since unable to read /dev/gator/events");
++ handleException();
++ }
++
++ while ((ent = readdir(dir)) != NULL) {
++ // skip hidden files, current dir, and parent dir
++ if (ent->d_name[0] == '.')
++ continue;
++ counter = mxmlNewElement(root, "counter");
++ mxmlElementSetAttr(counter, "name", ent->d_name);
++ }
++ closedir(dir);
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/KMod.h linux-linaro-stable-mx6/tools/gator/daemon/KMod.h
+--- linux-3.10.30.orig/tools/gator/daemon/KMod.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/KMod.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,27 @@
++/**
++ * Copyright (C) ARM Limited 2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef KMOD_H
++#define KMOD_H
++
++#include "Driver.h"
++
++// Driver for the gator kernel module
++class KMod : public Driver {
++public:
++ KMod() {}
++ ~KMod() {}
++
++ bool claimCounter(const Counter &counter) const;
++ void resetCounters();
++ void setupCounter(Counter &counter);
++
++ void writeCounters(mxml_node_t *root) const;
++};
++
++#endif // KMOD_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/access.c linux-linaro-stable-mx6/tools/gator/daemon/libsensors/access.c
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/access.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/access.c 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,561 @@
++/*
++ access.c - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++ Copyright (C) 2007-2009 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#include <stdlib.h>
++#include <string.h>
++#include <math.h>
++#include "access.h"
++#include "sensors.h"
++#include "data.h"
++#include "error.h"
++#include "sysfs.h"
++
++/* We watch the recursion depth for variables only, as an easy way to
++ detect cycles. */
++#define DEPTH_MAX 8
++
++static int sensors_eval_expr(const sensors_chip_features *chip_features,
++ const sensors_expr *expr,
++ double val, int depth, double *result);
++
++/* Compare two chips name descriptions, to see whether they could match.
++ Return 0 if it does not match, return 1 if it does match. */
++static int sensors_match_chip(const sensors_chip_name *chip1,
++ const sensors_chip_name *chip2)
++{
++ if ((chip1->prefix != SENSORS_CHIP_NAME_PREFIX_ANY) &&
++ (chip2->prefix != SENSORS_CHIP_NAME_PREFIX_ANY) &&
++ strcmp(chip1->prefix, chip2->prefix))
++ return 0;
++
++ if ((chip1->bus.type != SENSORS_BUS_TYPE_ANY) &&
++ (chip2->bus.type != SENSORS_BUS_TYPE_ANY) &&
++ (chip1->bus.type != chip2->bus.type))
++ return 0;
++
++ if ((chip1->bus.nr != SENSORS_BUS_NR_ANY) &&
++ (chip2->bus.nr != SENSORS_BUS_NR_ANY) &&
++ (chip1->bus.nr != chip2->bus.nr))
++ return 0;
++
++ if ((chip1->addr != chip2->addr) &&
++ (chip1->addr != SENSORS_CHIP_NAME_ADDR_ANY) &&
++ (chip2->addr != SENSORS_CHIP_NAME_ADDR_ANY))
++ return 0;
++
++ return 1;
++}
++
++/* Returns, one by one, a pointer to all sensor_chip structs of the
++ config file which match with the given chip name. Last should be
++ the value returned by the last call, or NULL if this is the first
++ call. Returns NULL if no more matches are found. Do not modify
++ the struct the return value points to!
++ Note that this visits the list of chips from last to first. Usually,
++ you want the match that was latest in the config file. */
++static sensors_chip *
++sensors_for_all_config_chips(const sensors_chip_name *name,
++ const sensors_chip *last)
++{
++ int nr, i;
++ sensors_chip_name_list chips;
++
++ for (nr = last ? last - sensors_config_chips - 1 :
++ sensors_config_chips_count - 1; nr >= 0; nr--) {
++
++ chips = sensors_config_chips[nr].chips;
++ for (i = 0; i < chips.fits_count; i++) {
++ if (sensors_match_chip(&chips.fits[i], name))
++ return sensors_config_chips + nr;
++ }
++ }
++ return NULL;
++}
++
++/* Look up a chip in the intern chip list, and return a pointer to it.
++ Do not modify the struct the return value points to! Returns NULL if
++ not found.*/
++static const sensors_chip_features *
++sensors_lookup_chip(const sensors_chip_name *name)
++{
++ int i;
++
++ for (i = 0; i < sensors_proc_chips_count; i++)
++ if (sensors_match_chip(&sensors_proc_chips[i].chip, name))
++ return &sensors_proc_chips[i];
++
++ return NULL;
++}
++
++/* Look up a subfeature of the given chip, and return a pointer to it.
++ Do not modify the struct the return value points to! Returns NULL if
++ not found.*/
++static const sensors_subfeature *
++sensors_lookup_subfeature_nr(const sensors_chip_features *chip,
++ int subfeat_nr)
++{
++ if (subfeat_nr < 0 ||
++ subfeat_nr >= chip->subfeature_count)
++ return NULL;
++ return chip->subfeature + subfeat_nr;
++}
++
++/* Look up a feature of the given chip, and return a pointer to it.
++ Do not modify the struct the return value points to! Returns NULL if
++ not found.*/
++static const sensors_feature *
++sensors_lookup_feature_nr(const sensors_chip_features *chip, int feat_nr)
++{
++ if (feat_nr < 0 ||
++ feat_nr >= chip->feature_count)
++ return NULL;
++ return chip->feature + feat_nr;
++}
++
++/* Look up a subfeature by name, and return a pointer to it.
++ Do not modify the struct the return value points to! Returns NULL if
++ not found.*/
++static const sensors_subfeature *
++sensors_lookup_subfeature_name(const sensors_chip_features *chip,
++ const char *name)
++{
++ int j;
++
++ for (j = 0; j < chip->subfeature_count; j++)
++ if (!strcmp(chip->subfeature[j].name, name))
++ return chip->subfeature + j;
++ return NULL;
++}
++
++/* Check whether the chip name is an 'absolute' name, which can only match
++ one chip, or whether it has wildcards. Returns 0 if it is absolute, 1
++ if there are wildcards. */
++int sensors_chip_name_has_wildcards(const sensors_chip_name *chip)
++{
++ if ((chip->prefix == SENSORS_CHIP_NAME_PREFIX_ANY) ||
++ (chip->bus.type == SENSORS_BUS_TYPE_ANY) ||
++ (chip->bus.nr == SENSORS_BUS_NR_ANY) ||
++ (chip->addr == SENSORS_CHIP_NAME_ADDR_ANY))
++ return 1;
++ else
++ return 0;
++}
++
++/* Look up the label for a given feature. Note that chip should not
++ contain wildcard values! The returned string is newly allocated (free it
++ yourself). On failure, NULL is returned.
++ If no label exists for this feature, its name is returned itself. */
++char *sensors_get_label(const sensors_chip_name *name,
++ const sensors_feature *feature)
++{
++ char *label;
++ const sensors_chip *chip;
++ char buf[PATH_MAX];
++ FILE *f;
++ int i;
++
++ if (sensors_chip_name_has_wildcards(name))
++ return NULL;
++
++ for (chip = NULL; (chip = sensors_for_all_config_chips(name, chip));)
++ for (i = 0; i < chip->labels_count; i++)
++ if (!strcmp(feature->name, chip->labels[i].name)) {
++ label = chip->labels[i].value;
++ goto sensors_get_label_exit;
++ }
++
++ /* No user specified label, check for a _label sysfs file */
++ snprintf(buf, PATH_MAX, "%s/%s_label", name->path, feature->name);
++
++ if ((f = fopen(buf, "r"))) {
++ i = fread(buf, 1, sizeof(buf), f);
++ fclose(f);
++ if (i > 0) {
++ /* i - 1 to strip the '\n' at the end */
++ buf[i - 1] = 0;
++ label = buf;
++ goto sensors_get_label_exit;
++ }
++ }
++
++ /* No label, return the feature name instead */
++ label = feature->name;
++
++sensors_get_label_exit:
++ label = strdup(label);
++ if (!label)
++ sensors_fatal_error(__func__, "Allocating label text");
++ return label;
++}
++
++/* Looks up whether a feature should be ignored. Returns
++ 1 if it should be ignored, 0 if not. */
++static int sensors_get_ignored(const sensors_chip_name *name,
++ const sensors_feature *feature)
++{
++ const sensors_chip *chip;
++ int i;
++
++ for (chip = NULL; (chip = sensors_for_all_config_chips(name, chip));)
++ for (i = 0; i < chip->ignores_count; i++)
++ if (!strcmp(feature->name, chip->ignores[i].name))
++ return 1;
++ return 0;
++}
++
++/* Read the value of a subfeature of a certain chip. Note that chip should not
++ contain wildcard values! This function will return 0 on success, and <0
++ on failure. */
++static int __sensors_get_value(const sensors_chip_name *name, int subfeat_nr,
++ int depth, double *result)
++{
++ const sensors_chip_features *chip_features;
++ const sensors_subfeature *subfeature;
++ const sensors_expr *expr = NULL;
++ double val;
++ int res, i;
++
++ if (depth >= DEPTH_MAX)
++ return -SENSORS_ERR_RECURSION;
++ if (sensors_chip_name_has_wildcards(name))
++ return -SENSORS_ERR_WILDCARDS;
++ if (!(chip_features = sensors_lookup_chip(name)))
++ return -SENSORS_ERR_NO_ENTRY;
++ if (!(subfeature = sensors_lookup_subfeature_nr(chip_features,
++ subfeat_nr)))
++ return -SENSORS_ERR_NO_ENTRY;
++ if (!(subfeature->flags & SENSORS_MODE_R))
++ return -SENSORS_ERR_ACCESS_R;
++
++ /* Apply compute statement if it exists */
++ if (subfeature->flags & SENSORS_COMPUTE_MAPPING) {
++ const sensors_feature *feature;
++ const sensors_chip *chip;
++
++ feature = sensors_lookup_feature_nr(chip_features,
++ subfeature->mapping);
++
++ chip = NULL;
++ while (!expr &&
++ (chip = sensors_for_all_config_chips(name, chip)))
++ for (i = 0; i < chip->computes_count; i++) {
++ if (!strcmp(feature->name,
++ chip->computes[i].name)) {
++ expr = chip->computes[i].from_proc;
++ break;
++ }
++ }
++ }
++
++ res = sensors_read_sysfs_attr(name, subfeature, &val);
++ if (res)
++ return res;
++ if (!expr)
++ *result = val;
++ else if ((res = sensors_eval_expr(chip_features, expr, val, depth,
++ result)))
++ return res;
++ return 0;
++}
++
++int sensors_get_value(const sensors_chip_name *name, int subfeat_nr,
++ double *result)
++{
++ return __sensors_get_value(name, subfeat_nr, 0, result);
++}
++
++/* Set the value of a subfeature of a certain chip. Note that chip should not
++ contain wildcard values! This function will return 0 on success, and <0
++ on failure. */
++int sensors_set_value(const sensors_chip_name *name, int subfeat_nr,
++ double value)
++{
++ const sensors_chip_features *chip_features;
++ const sensors_subfeature *subfeature;
++ const sensors_expr *expr = NULL;
++ int i, res;
++ double to_write;
++
++ if (sensors_chip_name_has_wildcards(name))
++ return -SENSORS_ERR_WILDCARDS;
++ if (!(chip_features = sensors_lookup_chip(name)))
++ return -SENSORS_ERR_NO_ENTRY;
++ if (!(subfeature = sensors_lookup_subfeature_nr(chip_features,
++ subfeat_nr)))
++ return -SENSORS_ERR_NO_ENTRY;
++ if (!(subfeature->flags & SENSORS_MODE_W))
++ return -SENSORS_ERR_ACCESS_W;
++
++ /* Apply compute statement if it exists */
++ if (subfeature->flags & SENSORS_COMPUTE_MAPPING) {
++ const sensors_feature *feature;
++ const sensors_chip *chip;
++
++ feature = sensors_lookup_feature_nr(chip_features,
++ subfeature->mapping);
++
++ chip = NULL;
++ while (!expr &&
++ (chip = sensors_for_all_config_chips(name, chip)))
++ for (i = 0; i < chip->computes_count; i++) {
++ if (!strcmp(feature->name,
++ chip->computes[i].name)) {
++ expr = chip->computes[i].to_proc;
++ break;
++ }
++ }
++ }
++
++ to_write = value;
++ if (expr)
++ if ((res = sensors_eval_expr(chip_features, expr,
++ value, 0, &to_write)))
++ return res;
++ return sensors_write_sysfs_attr(name, subfeature, to_write);
++}
++
++const sensors_chip_name *sensors_get_detected_chips(const sensors_chip_name
++ *match, int *nr)
++{
++ const sensors_chip_name *res;
++
++ while (*nr < sensors_proc_chips_count) {
++ res = &sensors_proc_chips[(*nr)++].chip;
++ if (!match || sensors_match_chip(res, match))
++ return res;
++ }
++ return NULL;
++}
++
++const char *sensors_get_adapter_name(const sensors_bus_id *bus)
++{
++ int i;
++
++ /* bus types with a single instance */
++ switch (bus->type) {
++ case SENSORS_BUS_TYPE_ISA:
++ return "ISA adapter";
++ case SENSORS_BUS_TYPE_PCI:
++ return "PCI adapter";
++ /* SPI should not be here, but for now SPI adapters have no name
++ so we don't have any custom string to return. */
++ case SENSORS_BUS_TYPE_SPI:
++ return "SPI adapter";
++ case SENSORS_BUS_TYPE_VIRTUAL:
++ return "Virtual device";
++ case SENSORS_BUS_TYPE_ACPI:
++ return "ACPI interface";
++ /* HID should probably not be there either, but I don't know if
++ HID buses have a name nor where to find it. */
++ case SENSORS_BUS_TYPE_HID:
++ return "HID adapter";
++ }
++
++ /* bus types with several instances */
++ for (i = 0; i < sensors_proc_bus_count; i++)
++ if (sensors_proc_bus[i].bus.type == bus->type &&
++ sensors_proc_bus[i].bus.nr == bus->nr)
++ return sensors_proc_bus[i].adapter;
++ return NULL;
++}
++
++const sensors_feature *
++sensors_get_features(const sensors_chip_name *name, int *nr)
++{
++ const sensors_chip_features *chip;
++
++ if (!(chip = sensors_lookup_chip(name)))
++ return NULL; /* No such chip */
++
++ while (*nr < chip->feature_count
++ && sensors_get_ignored(name, &chip->feature[*nr]))
++ (*nr)++;
++ if (*nr >= chip->feature_count)
++ return NULL;
++ return &chip->feature[(*nr)++];
++}
++
++const sensors_subfeature *
++sensors_get_all_subfeatures(const sensors_chip_name *name,
++ const sensors_feature *feature, int *nr)
++{
++ const sensors_chip_features *chip;
++ const sensors_subfeature *subfeature;
++
++ if (!(chip = sensors_lookup_chip(name)))
++ return NULL; /* No such chip */
++
++ /* Seek directly to the first subfeature */
++ if (*nr < feature->first_subfeature)
++ *nr = feature->first_subfeature;
++
++ if (*nr >= chip->subfeature_count)
++ return NULL; /* end of list */
++ subfeature = &chip->subfeature[(*nr)++];
++ if (subfeature->mapping == feature->number)
++ return subfeature;
++ return NULL; /* end of subfeature list */
++}
++
++const sensors_subfeature *
++sensors_get_subfeature(const sensors_chip_name *name,
++ const sensors_feature *feature,
++ sensors_subfeature_type type)
++{
++ const sensors_chip_features *chip;
++ int i;
++
++ if (!(chip = sensors_lookup_chip(name)))
++ return NULL; /* No such chip */
++
++ for (i = feature->first_subfeature; i < chip->subfeature_count &&
++ chip->subfeature[i].mapping == feature->number; i++) {
++ if (chip->subfeature[i].type == type)
++ return &chip->subfeature[i];
++ }
++ return NULL; /* No such subfeature */
++}
++
++/* Evaluate an expression */
++int sensors_eval_expr(const sensors_chip_features *chip_features,
++ const sensors_expr *expr,
++ double val, int depth, double *result)
++{
++ double res1, res2;
++ int res;
++ const sensors_subfeature *subfeature;
++
++ if (expr->kind == sensors_kind_val) {
++ *result = expr->data.val;
++ return 0;
++ }
++ if (expr->kind == sensors_kind_source) {
++ *result = val;
++ return 0;
++ }
++ if (expr->kind == sensors_kind_var) {
++ if (!(subfeature = sensors_lookup_subfeature_name(chip_features,
++ expr->data.var)))
++ return -SENSORS_ERR_NO_ENTRY;
++ return __sensors_get_value(&chip_features->chip,
++ subfeature->number, depth + 1,
++ result);
++ }
++ if ((res = sensors_eval_expr(chip_features, expr->data.subexpr.sub1,
++ val, depth, &res1)))
++ return res;
++ if (expr->data.subexpr.sub2 &&
++ (res = sensors_eval_expr(chip_features, expr->data.subexpr.sub2,
++ val, depth, &res2)))
++ return res;
++ switch (expr->data.subexpr.op) {
++ case sensors_add:
++ *result = res1 + res2;
++ return 0;
++ case sensors_sub:
++ *result = res1 - res2;
++ return 0;
++ case sensors_multiply:
++ *result = res1 * res2;
++ return 0;
++ case sensors_divide:
++ if (res2 == 0.0)
++ return -SENSORS_ERR_DIV_ZERO;
++ *result = res1 / res2;
++ return 0;
++ case sensors_negate:
++ *result = -res1;
++ return 0;
++ case sensors_exp:
++ *result = exp(res1);
++ return 0;
++ case sensors_log:
++ if (res1 < 0.0)
++ return -SENSORS_ERR_DIV_ZERO;
++ *result = log(res1);
++ return 0;
++ }
++ return 0;
++}
++
++/* Execute all set statements for this particular chip. The chip may not
++ contain wildcards! This function will return 0 on success, and <0 on
++ failure. */
++static int sensors_do_this_chip_sets(const sensors_chip_name *name)
++{
++ const sensors_chip_features *chip_features;
++ sensors_chip *chip;
++ double value;
++ int i;
++ int err = 0, res;
++ const sensors_subfeature *subfeature;
++
++ chip_features = sensors_lookup_chip(name); /* Can't fail */
++
++ for (chip = NULL; (chip = sensors_for_all_config_chips(name, chip));)
++ for (i = 0; i < chip->sets_count; i++) {
++ subfeature = sensors_lookup_subfeature_name(chip_features,
++ chip->sets[i].name);
++ if (!subfeature) {
++ sensors_parse_error_wfn("Unknown feature name",
++ chip->sets[i].line.filename,
++ chip->sets[i].line.lineno);
++ err = -SENSORS_ERR_NO_ENTRY;
++ continue;
++ }
++
++ res = sensors_eval_expr(chip_features,
++ chip->sets[i].value, 0,
++ 0, &value);
++ if (res) {
++ sensors_parse_error_wfn("Error parsing expression",
++ chip->sets[i].line.filename,
++ chip->sets[i].line.lineno);
++ err = res;
++ continue;
++ }
++ if ((res = sensors_set_value(name, subfeature->number,
++ value))) {
++ sensors_parse_error_wfn("Failed to set value",
++ chip->sets[i].line.filename,
++ chip->sets[i].line.lineno);
++ err = res;
++ continue;
++ }
++ }
++ return err;
++}
++
++/* Execute all set statements for this particular chip. The chip may contain
++ wildcards! This function will return 0 on success, and <0 on failure. */
++int sensors_do_chip_sets(const sensors_chip_name *name)
++{
++ int nr, this_res;
++ const sensors_chip_name *found_name;
++ int res = 0;
++
++ for (nr = 0; (found_name = sensors_get_detected_chips(name, &nr));) {
++ this_res = sensors_do_this_chip_sets(found_name);
++ if (this_res)
++ res = this_res;
++ }
++ return res;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/access.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/access.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/access.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/access.h 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,33 @@
++/*
++ access.h - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++ Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#ifndef LIB_SENSORS_ACCESS_H
++#define LIB_SENSORS_ACCESS_H
++
++#include "sensors.h"
++#include "data.h"
++
++/* Check whether the chip name is an 'absolute' name, which can only match
++ one chip, or whether it has wildcards. Returns 0 if it is absolute, 1
++ if there are wildcards. */
++int sensors_chip_name_has_wildcards(const sensors_chip_name *chip);
++
++#endif /* def LIB_SENSORS_ACCESS_H */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/conf.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/conf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,34 @@
++/*
++ conf.h - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#ifndef LIB_SENSORS_CONF_H
++#define LIB_SENSORS_CONF_H
++
++/* This is defined in conf-lex.l */
++int sensors_yylex(void);
++extern char sensors_lex_error[];
++extern const char *sensors_yyfilename;
++extern int sensors_yylineno;
++extern FILE *sensors_yyin;
++
++/* This is defined in conf-parse.y */
++int sensors_yyparse(void);
++
++#endif /* LIB_SENSORS_CONF_H */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-lex.c linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-lex.c
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-lex.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-lex.c 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,2881 @@
++
++#line 3 "<stdout>"
++
++#define YY_INT_ALIGNED short int
++
++/* A lexical scanner generated by flex */
++
++#define yy_create_buffer sensors_yy_create_buffer
++#define yy_delete_buffer sensors_yy_delete_buffer
++#define yy_flex_debug sensors_yy_flex_debug
++#define yy_init_buffer sensors_yy_init_buffer
++#define yy_flush_buffer sensors_yy_flush_buffer
++#define yy_load_buffer_state sensors_yy_load_buffer_state
++#define yy_switch_to_buffer sensors_yy_switch_to_buffer
++#define yyin sensors_yyin
++#define yyleng sensors_yyleng
++#define yylex sensors_yylex
++#define yylineno sensors_yylineno
++#define yyout sensors_yyout
++#define yyrestart sensors_yyrestart
++#define yytext sensors_yytext
++#define yywrap sensors_yywrap
++#define yyalloc sensors_yyalloc
++#define yyrealloc sensors_yyrealloc
++#define yyfree sensors_yyfree
++
++#define FLEX_SCANNER
++#define YY_FLEX_MAJOR_VERSION 2
++#define YY_FLEX_MINOR_VERSION 5
++#define YY_FLEX_SUBMINOR_VERSION 35
++#if YY_FLEX_SUBMINOR_VERSION > 0
++#define FLEX_BETA
++#endif
++
++/* First, we deal with platform-specific or compiler-specific issues. */
++
++/* begin standard C headers. */
++#include <stdio.h>
++#include <string.h>
++#include <errno.h>
++#include <stdlib.h>
++
++/* end standard C headers. */
++
++/* flex integer type definitions */
++
++#ifndef FLEXINT_H
++#define FLEXINT_H
++
++/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
++
++#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
++
++/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
++ * if you want the limit (max/min) macros for int types.
++ */
++#ifndef __STDC_LIMIT_MACROS
++#define __STDC_LIMIT_MACROS 1
++#endif
++
++#include <inttypes.h>
++typedef int8_t flex_int8_t;
++typedef uint8_t flex_uint8_t;
++typedef int16_t flex_int16_t;
++typedef uint16_t flex_uint16_t;
++typedef int32_t flex_int32_t;
++typedef uint32_t flex_uint32_t;
++#else
++typedef signed char flex_int8_t;
++typedef short int flex_int16_t;
++typedef int flex_int32_t;
++typedef unsigned char flex_uint8_t;
++typedef unsigned short int flex_uint16_t;
++typedef unsigned int flex_uint32_t;
++
++/* Limits of integral types. */
++#ifndef INT8_MIN
++#define INT8_MIN (-128)
++#endif
++#ifndef INT16_MIN
++#define INT16_MIN (-32767-1)
++#endif
++#ifndef INT32_MIN
++#define INT32_MIN (-2147483647-1)
++#endif
++#ifndef INT8_MAX
++#define INT8_MAX (127)
++#endif
++#ifndef INT16_MAX
++#define INT16_MAX (32767)
++#endif
++#ifndef INT32_MAX
++#define INT32_MAX (2147483647)
++#endif
++#ifndef UINT8_MAX
++#define UINT8_MAX (255U)
++#endif
++#ifndef UINT16_MAX
++#define UINT16_MAX (65535U)
++#endif
++#ifndef UINT32_MAX
++#define UINT32_MAX (4294967295U)
++#endif
++
++#endif /* ! C99 */
++
++#endif /* ! FLEXINT_H */
++
++#ifdef __cplusplus
++
++/* The "const" storage-class-modifier is valid. */
++#define YY_USE_CONST
++
++#else /* ! __cplusplus */
++
++/* C99 requires __STDC__ to be defined as 1. */
++#if defined (__STDC__)
++
++#define YY_USE_CONST
++
++#endif /* defined (__STDC__) */
++#endif /* ! __cplusplus */
++
++#ifdef YY_USE_CONST
++#define yyconst const
++#else
++#define yyconst
++#endif
++
++/* Returned upon end-of-file. */
++#define YY_NULL 0
++
++/* Promotes a possibly negative, possibly signed char to an unsigned
++ * integer for use as an array index. If the signed char is negative,
++ * we want to instead treat it as an 8-bit unsigned char, hence the
++ * double cast.
++ */
++#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
++
++/* Enter a start condition. This macro really ought to take a parameter,
++ * but we do it the disgusting crufty way forced on us by the ()-less
++ * definition of BEGIN.
++ */
++#define BEGIN (yy_start) = 1 + 2 *
++
++/* Translate the current start state into a value that can be later handed
++ * to BEGIN to return to the state. The YYSTATE alias is for lex
++ * compatibility.
++ */
++#define YY_START (((yy_start) - 1) / 2)
++#define YYSTATE YY_START
++
++/* Action number for EOF rule of a given start state. */
++#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
++
++/* Special action meaning "start processing a new file". */
++#define YY_NEW_FILE sensors_yyrestart(sensors_yyin )
++
++#define YY_END_OF_BUFFER_CHAR 0
++
++/* Size of default input buffer. */
++#ifndef YY_BUF_SIZE
++#ifdef __ia64__
++/* On IA-64, the buffer size is 16k, not 8k.
++ * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case.
++ * Ditto for the __ia64__ case accordingly.
++ */
++#define YY_BUF_SIZE 32768
++#else
++#define YY_BUF_SIZE 16384
++#endif /* __ia64__ */
++#endif
++
++/* The state buf must be large enough to hold one state per character in the main buffer.
++ */
++#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
++
++#ifndef YY_TYPEDEF_YY_BUFFER_STATE
++#define YY_TYPEDEF_YY_BUFFER_STATE
++typedef struct yy_buffer_state *YY_BUFFER_STATE;
++#endif
++
++extern int sensors_yyleng;
++
++extern FILE *sensors_yyin, *sensors_yyout;
++
++#define EOB_ACT_CONTINUE_SCAN 0
++#define EOB_ACT_END_OF_FILE 1
++#define EOB_ACT_LAST_MATCH 2
++
++ #define YY_LESS_LINENO(n)
++
++/* Return all but the first "n" matched characters back to the input stream. */
++#define yyless(n) \
++ do \
++ { \
++ /* Undo effects of setting up sensors_yytext. */ \
++ int yyless_macro_arg = (n); \
++ YY_LESS_LINENO(yyless_macro_arg);\
++ *yy_cp = (yy_hold_char); \
++ YY_RESTORE_YY_MORE_OFFSET \
++ (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
++ YY_DO_BEFORE_ACTION; /* set up sensors_yytext again */ \
++ } \
++ while ( 0 )
++
++#define unput(c) yyunput( c, (yytext_ptr) )
++
++#ifndef YY_TYPEDEF_YY_SIZE_T
++#define YY_TYPEDEF_YY_SIZE_T
++typedef size_t yy_size_t;
++#endif
++
++#ifndef YY_STRUCT_YY_BUFFER_STATE
++#define YY_STRUCT_YY_BUFFER_STATE
++struct yy_buffer_state
++ {
++ FILE *yy_input_file;
++
++ char *yy_ch_buf; /* input buffer */
++ char *yy_buf_pos; /* current position in input buffer */
++
++ /* Size of input buffer in bytes, not including room for EOB
++ * characters.
++ */
++ yy_size_t yy_buf_size;
++
++ /* Number of characters read into yy_ch_buf, not including EOB
++ * characters.
++ */
++ int yy_n_chars;
++
++ /* Whether we "own" the buffer - i.e., we know we created it,
++ * and can realloc() it to grow it, and should free() it to
++ * delete it.
++ */
++ int yy_is_our_buffer;
++
++ /* Whether this is an "interactive" input source; if so, and
++ * if we're using stdio for input, then we want to use getc()
++ * instead of fread(), to make sure we stop fetching input after
++ * each newline.
++ */
++ int yy_is_interactive;
++
++ /* Whether we're considered to be at the beginning of a line.
++ * If so, '^' rules will be active on the next match, otherwise
++ * not.
++ */
++ int yy_at_bol;
++
++ int yy_bs_lineno; /**< The line count. */
++ int yy_bs_column; /**< The column count. */
++
++ /* Whether to try to fill the input buffer when we reach the
++ * end of it.
++ */
++ int yy_fill_buffer;
++
++ int yy_buffer_status;
++
++#define YY_BUFFER_NEW 0
++#define YY_BUFFER_NORMAL 1
++ /* When an EOF's been seen but there's still some text to process
++ * then we mark the buffer as YY_EOF_PENDING, to indicate that we
++ * shouldn't try reading from the input source any more. We might
++ * still have a bunch of tokens to match, though, because of
++ * possible backing-up.
++ *
++ * When we actually see the EOF, we change the status to "new"
++ * (via sensors_yyrestart()), so that the user can continue scanning by
++ * just pointing sensors_yyin at a new input file.
++ */
++#define YY_BUFFER_EOF_PENDING 2
++
++ };
++#endif /* !YY_STRUCT_YY_BUFFER_STATE */
++
++/* Stack of input buffers. */
++static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
++static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
++static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
++
++/* We provide macros for accessing buffer states in case in the
++ * future we want to put the buffer states in a more general
++ * "scanner state".
++ *
++ * Returns the top of the stack, or NULL.
++ */
++#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
++ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
++ : NULL)
++
++/* Same as previous macro, but useful when we know that the buffer stack is not
++ * NULL or when we need an lvalue. For internal use only.
++ */
++#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
++
++/* yy_hold_char holds the character lost when sensors_yytext is formed. */
++static char yy_hold_char;
++static int yy_n_chars; /* number of characters read into yy_ch_buf */
++int sensors_yyleng;
++
++/* Points to current character in buffer. */
++static char *yy_c_buf_p = (char *) 0;
++static int yy_init = 0; /* whether we need to initialize */
++static int yy_start = 0; /* start state number */
++
++/* Flag which is used to allow sensors_yywrap()'s to do buffer switches
++ * instead of setting up a fresh sensors_yyin. A bit of a hack ...
++ */
++static int yy_did_buffer_switch_on_eof;
++
++void sensors_yyrestart (FILE *input_file );
++void sensors_yy_switch_to_buffer (YY_BUFFER_STATE new_buffer );
++YY_BUFFER_STATE sensors_yy_create_buffer (FILE *file,int size );
++void sensors_yy_delete_buffer (YY_BUFFER_STATE b );
++void sensors_yy_flush_buffer (YY_BUFFER_STATE b );
++void sensors_yypush_buffer_state (YY_BUFFER_STATE new_buffer );
++void sensors_yypop_buffer_state (void );
++
++static void sensors_yyensure_buffer_stack (void );
++static void sensors_yy_load_buffer_state (void );
++static void sensors_yy_init_buffer (YY_BUFFER_STATE b,FILE *file );
++
++#define YY_FLUSH_BUFFER sensors_yy_flush_buffer(YY_CURRENT_BUFFER )
++
++YY_BUFFER_STATE sensors_yy_scan_buffer (char *base,yy_size_t size );
++YY_BUFFER_STATE sensors_yy_scan_string (yyconst char *yy_str );
++YY_BUFFER_STATE sensors_yy_scan_bytes (yyconst char *bytes,int len );
++
++void *sensors_yyalloc (yy_size_t );
++void *sensors_yyrealloc (void *,yy_size_t );
++void sensors_yyfree (void * );
++
++#define yy_new_buffer sensors_yy_create_buffer
++
++#define yy_set_interactive(is_interactive) \
++ { \
++ if ( ! YY_CURRENT_BUFFER ){ \
++ sensors_yyensure_buffer_stack (); \
++ YY_CURRENT_BUFFER_LVALUE = \
++ sensors_yy_create_buffer(sensors_yyin,YY_BUF_SIZE ); \
++ } \
++ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
++ }
++
++#define yy_set_bol(at_bol) \
++ { \
++ if ( ! YY_CURRENT_BUFFER ){\
++ sensors_yyensure_buffer_stack (); \
++ YY_CURRENT_BUFFER_LVALUE = \
++ sensors_yy_create_buffer(sensors_yyin,YY_BUF_SIZE ); \
++ } \
++ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
++ }
++
++#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
++
++/* Begin user sect3 */
++
++#define sensors_yywrap(n) 1
++#define YY_SKIP_YYWRAP
++
++typedef unsigned char YY_CHAR;
++
++FILE *sensors_yyin = (FILE *) 0, *sensors_yyout = (FILE *) 0;
++
++typedef int yy_state_type;
++
++extern int sensors_yylineno;
++
++int sensors_yylineno = 1;
++
++extern char *sensors_yytext;
++#define yytext_ptr sensors_yytext
++static yyconst flex_int16_t yy_nxt[][39] =
++ {
++ {
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0, 0, 0
++ },
++
++ {
++ 9, 10, 11, 12, 10, 13, 10, 10, 10, 10,
++ 10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
++ 14, 15, 16, 14, 14, 14, 14, 14, 17, 18,
++ 14, 14, 14, 14, 14, 19, 14, 14, 14
++ },
++
++ {
++ 9, 10, 11, 12, 10, 13, 10, 10, 10, 10,
++ 10, 10, 10, 10, 10, 10, 10, 10, 10, 10,
++
++ 14, 15, 16, 14, 14, 14, 14, 14, 17, 18,
++ 14, 14, 14, 14, 14, 19, 14, 14, 14
++ },
++
++ {
++ 9, 20, 21, 22, 23, 24, 25, 26, 27, 28,
++ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
++ 35, 35, 35, 35, 35, 35, 35, 35, 35, 35,
++ 35, 35, 35, 35, 35, 35, 35, 35, 35
++ },
++
++ {
++ 9, 20, 21, 22, 23, 24, 25, 26, 27, 28,
++ 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
++ 35, 35, 35, 35, 35, 35, 35, 35, 35, 35,
++ 35, 35, 35, 35, 35, 35, 35, 35, 35
++
++ },
++
++ {
++ 9, 39, 39, 40, 41, 39, 39, 39, 39, 39,
++ 39, 39, 39, 39, 39, 39, 39, 42, 39, 39,
++ 39, 39, 39, 39, 39, 39, 39, 39, 39, 39,
++ 39, 39, 39, 39, 39, 39, 39, 39, 39
++ },
++
++ {
++ 9, 39, 39, 40, 41, 39, 39, 39, 39, 39,
++ 39, 39, 39, 39, 39, 39, 39, 42, 39, 39,
++ 39, 39, 39, 39, 39, 39, 39, 39, 39, 39,
++ 39, 39, 39, 39, 39, 39, 39, 39, 39
++ },
++
++ {
++ 9, 43, 43, 44, 43, 43, 43, 43, 43, 43,
++ 43, 43, 43, 43, 43, 43, 43, 43, 43, 43,
++
++ 43, 43, 43, 43, 43, 43, 43, 43, 43, 43,
++ 43, 43, 43, 43, 43, 43, 43, 43, 43
++ },
++
++ {
++ 9, 43, 43, 44, 43, 43, 43, 43, 43, 43,
++ 43, 43, 43, 43, 43, 43, 43, 43, 43, 43,
++ 43, 43, 43, 43, 43, 43, 43, 43, 43, 43,
++ 43, 43, 43, 43, 43, 43, 43, 43, 43
++ },
++
++ {
++ -9, -9, -9, -9, -9, -9, -9, -9, -9, -9,
++ -9, -9, -9, -9, -9, -9, -9, -9, -9, -9,
++ -9, -9, -9, -9, -9, -9, -9, -9, -9, -9,
++ -9, -9, -9, -9, -9, -9, -9, -9, -9
++
++ },
++
++ {
++ 9, -10, -10, -10, -10, -10, -10, -10, -10, -10,
++ -10, -10, -10, -10, -10, -10, -10, -10, -10, -10,
++ -10, -10, -10, -10, -10, -10, -10, -10, -10, -10,
++ -10, -10, -10, -10, -10, -10, -10, -10, -10
++ },
++
++ {
++ 9, -11, 45, 46, -11, -11, -11, -11, -11, -11,
++ -11, -11, -11, -11, -11, -11, -11, -11, -11, -11,
++ -11, -11, -11, -11, -11, -11, -11, -11, -11, -11,
++ -11, -11, -11, -11, -11, -11, -11, -11, -11
++ },
++
++ {
++ 9, -12, -12, -12, -12, -12, -12, -12, -12, -12,
++ -12, -12, -12, -12, -12, -12, -12, -12, -12, -12,
++
++ -12, -12, -12, -12, -12, -12, -12, -12, -12, -12,
++ -12, -12, -12, -12, -12, -12, -12, -12, -12
++ },
++
++ {
++ 9, 47, 47, 48, 47, 47, 47, 47, 47, 47,
++ 47, 47, 47, 47, 47, 47, 47, 47, 47, 47,
++ 47, 47, 47, 47, 47, 47, 47, 47, 47, 47,
++ 47, 47, 47, 47, 47, 47, 47, 47, 47
++ },
++
++ {
++ 9, -14, -14, -14, -14, -14, -14, -14, -14, -14,
++ -14, -14, -14, -14, -14, -14, -14, -14, -14, -14,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++
++ },
++
++ {
++ 9, -15, -15, -15, -15, -15, -15, -15, -15, -15,
++ -15, -15, -15, -15, -15, -15, -15, -15, -15, -15,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 50, 49
++ },
++
++ {
++ 9, -16, -16, -16, -16, -16, -16, -16, -16, -16,
++ -16, -16, -16, -16, -16, -16, -16, -16, -16, -16,
++ 49, 49, 49, 49, 49, 49, 49, 51, 49, 49,
++ 49, 49, 52, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -17, -17, -17, -17, -17, -17, -17, -17, -17,
++ -17, -17, -17, -17, -17, -17, -17, -17, -17, -17,
++
++ 49, 49, 49, 49, 49, 49, 53, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -18, -18, -18, -18, -18, -18, -18, -18, -18,
++ -18, -18, -18, -18, -18, -18, -18, -18, -18, -18,
++ 54, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -19, -19, -19, -19, -19, -19, -19, -19, -19,
++ -19, -19, -19, -19, -19, -19, -19, -19, -19, -19,
++ 49, 49, 49, 49, 55, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++
++ },
++
++ {
++ 9, -20, -20, -20, -20, -20, -20, -20, -20, -20,
++ -20, -20, -20, -20, -20, -20, -20, -20, -20, -20,
++ -20, -20, -20, -20, -20, -20, -20, -20, -20, -20,
++ -20, -20, -20, -20, -20, -20, -20, -20, -20
++ },
++
++ {
++ 9, -21, 56, -21, -21, -21, -21, -21, -21, -21,
++ -21, -21, -21, -21, -21, -21, -21, -21, -21, -21,
++ -21, -21, -21, -21, -21, -21, -21, -21, -21, -21,
++ -21, -21, -21, -21, -21, -21, -21, -21, -21
++ },
++
++ {
++ 9, -22, -22, -22, -22, -22, -22, -22, -22, -22,
++ -22, -22, -22, -22, -22, -22, -22, -22, -22, -22,
++
++ -22, -22, -22, -22, -22, -22, -22, -22, -22, -22,
++ -22, -22, -22, -22, -22, -22, -22, -22, -22
++ },
++
++ {
++ 9, -23, -23, -23, -23, -23, -23, -23, -23, -23,
++ -23, -23, -23, -23, -23, -23, -23, -23, -23, -23,
++ -23, -23, -23, -23, -23, -23, -23, -23, -23, -23,
++ -23, -23, -23, -23, -23, -23, -23, -23, -23
++ },
++
++ {
++ 9, 57, 57, 58, 57, 57, 57, 57, 57, 57,
++ 57, 57, 57, 57, 57, 57, 57, 57, 57, 57,
++ 57, 57, 57, 57, 57, 57, 57, 57, 57, 57,
++ 57, 57, 57, 57, 57, 57, 57, 57, 57
++
++ },
++
++ {
++ 9, -25, -25, -25, -25, -25, -25, -25, -25, -25,
++ -25, -25, -25, -25, -25, -25, -25, -25, -25, -25,
++ -25, -25, -25, -25, -25, -25, -25, -25, -25, -25,
++ -25, -25, -25, -25, -25, -25, -25, -25, -25
++ },
++
++ {
++ 9, -26, -26, -26, -26, -26, -26, -26, -26, -26,
++ -26, -26, -26, -26, -26, -26, -26, -26, -26, -26,
++ -26, -26, -26, -26, -26, -26, -26, -26, -26, -26,
++ -26, -26, -26, -26, -26, -26, -26, -26, -26
++ },
++
++ {
++ 9, -27, -27, -27, -27, -27, -27, -27, -27, -27,
++ -27, -27, -27, -27, -27, -27, -27, -27, -27, -27,
++
++ -27, -27, -27, -27, -27, -27, -27, -27, -27, -27,
++ -27, -27, -27, -27, -27, -27, -27, -27, -27
++ },
++
++ {
++ 9, -28, -28, -28, -28, -28, -28, -28, -28, -28,
++ -28, -28, -28, -28, -28, -28, -28, -28, -28, -28,
++ -28, -28, -28, -28, -28, -28, -28, -28, -28, -28,
++ -28, -28, -28, -28, -28, -28, -28, -28, -28
++ },
++
++ {
++ 9, -29, -29, -29, -29, -29, -29, -29, -29, -29,
++ -29, -29, -29, -29, -29, -29, -29, -29, -29, -29,
++ -29, -29, -29, -29, -29, -29, -29, -29, -29, -29,
++ -29, -29, -29, -29, -29, -29, -29, -29, -29
++
++ },
++
++ {
++ 9, -30, -30, -30, -30, -30, -30, -30, -30, -30,
++ -30, -30, -30, -30, -30, -30, -30, -30, -30, -30,
++ -30, -30, -30, -30, -30, -30, -30, -30, -30, -30,
++ -30, -30, -30, -30, -30, -30, -30, -30, -30
++ },
++
++ {
++ 9, -31, -31, -31, -31, -31, -31, -31, -31, -31,
++ -31, -31, -31, -31, 59, -31, -31, -31, -31, -31,
++ -31, -31, -31, -31, -31, -31, -31, -31, -31, -31,
++ -31, -31, -31, -31, -31, -31, -31, -31, -31
++ },
++
++ {
++ 9, -32, -32, -32, -32, -32, -32, -32, -32, -32,
++ -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
++
++ -32, -32, -32, -32, -32, -32, -32, -32, -32, -32,
++ -32, -32, -32, -32, -32, -32, -32, -32, -32
++ },
++
++ {
++ 9, -33, -33, -33, -33, -33, -33, -33, -33, -33,
++ -33, -33, 60, -33, 61, -33, 62, -33, -33, -33,
++ 62, 62, 62, 62, 62, 62, 62, 62, 62, 62,
++ 62, 62, 62, 62, 62, 62, 62, 62, 62
++ },
++
++ {
++ 9, -34, -34, -34, -34, -34, -34, -34, -34, -34,
++ -34, -34, -34, -34, -34, -34, -34, -34, -34, -34,
++ -34, -34, -34, -34, -34, -34, -34, -34, -34, -34,
++ -34, -34, -34, -34, -34, -34, -34, -34, -34
++
++ },
++
++ {
++ 9, -35, -35, -35, -35, -35, -35, -35, -35, -35,
++ -35, -35, -35, -35, 62, -35, 62, -35, -35, -35,
++ 62, 62, 62, 62, 62, 62, 62, 62, 62, 62,
++ 62, 62, 62, 62, 62, 62, 62, 62, 62
++ },
++
++ {
++ 9, -36, 63, 64, -36, -36, -36, -36, -36, -36,
++ -36, -36, -36, -36, -36, -36, -36, -36, -36, -36,
++ -36, -36, -36, -36, -36, -36, -36, -36, -36, -36,
++ -36, -36, -36, -36, -36, -36, -36, -36, -36
++ },
++
++ {
++ 9, -37, -37, -37, -37, -37, -37, -37, -37, -37,
++ -37, -37, -37, -37, -37, -37, -37, -37, -37, -37,
++
++ -37, -37, -37, -37, -37, -37, -37, -37, -37, -37,
++ -37, -37, -37, -37, -37, -37, -37, -37, -37
++ },
++
++ {
++ 9, -38, -38, -38, -38, -38, -38, -38, -38, -38,
++ -38, -38, -38, -38, -38, -38, -38, -38, -38, -38,
++ -38, -38, -38, -38, -38, -38, -38, -38, -38, -38,
++ -38, -38, -38, -38, -38, -38, -38, -38, -38
++ },
++
++ {
++ 9, 65, 65, -39, -39, 65, 65, 65, 65, 65,
++ 65, 65, 65, 65, 65, 65, 65, -39, 65, 65,
++ 65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
++ 65, 65, 65, 65, 65, 65, 65, 65, 65
++
++ },
++
++ {
++ 9, -40, -40, -40, -40, -40, -40, -40, -40, -40,
++ -40, -40, -40, -40, -40, -40, -40, -40, -40, -40,
++ -40, -40, -40, -40, -40, -40, -40, -40, -40, -40,
++ -40, -40, -40, -40, -40, -40, -40, -40, -40
++ },
++
++ {
++ 9, -41, -41, -41, 66, -41, -41, -41, -41, -41,
++ -41, -41, -41, -41, -41, -41, -41, -41, -41, -41,
++ -41, -41, -41, -41, -41, -41, -41, -41, -41, -41,
++ -41, -41, -41, -41, -41, -41, -41, -41, -41
++ },
++
++ {
++ 9, 67, 67, 68, 67, 67, 67, 67, 67, 67,
++ 67, 67, 67, 67, 67, 67, 67, 67, 67, 67,
++
++ 69, 70, 67, 67, 67, 71, 67, 67, 67, 67,
++ 67, 72, 67, 67, 73, 67, 74, 67, 75
++ },
++
++ {
++ 9, 76, 76, -43, 76, 76, 76, 76, 76, 76,
++ 76, 76, 76, 76, 76, 76, 76, 76, 76, 76,
++ 76, 76, 76, 76, 76, 76, 76, 76, 76, 76,
++ 76, 76, 76, 76, 76, 76, 76, 76, 76
++ },
++
++ {
++ 9, -44, -44, -44, -44, -44, -44, -44, -44, -44,
++ -44, -44, -44, -44, -44, -44, -44, -44, -44, -44,
++ -44, -44, -44, -44, -44, -44, -44, -44, -44, -44,
++ -44, -44, -44, -44, -44, -44, -44, -44, -44
++
++ },
++
++ {
++ 9, -45, 45, 46, -45, -45, -45, -45, -45, -45,
++ -45, -45, -45, -45, -45, -45, -45, -45, -45, -45,
++ -45, -45, -45, -45, -45, -45, -45, -45, -45, -45,
++ -45, -45, -45, -45, -45, -45, -45, -45, -45
++ },
++
++ {
++ 9, -46, -46, -46, -46, -46, -46, -46, -46, -46,
++ -46, -46, -46, -46, -46, -46, -46, -46, -46, -46,
++ -46, -46, -46, -46, -46, -46, -46, -46, -46, -46,
++ -46, -46, -46, -46, -46, -46, -46, -46, -46
++ },
++
++ {
++ 9, 47, 47, 48, 47, 47, 47, 47, 47, 47,
++ 47, 47, 47, 47, 47, 47, 47, 47, 47, 47,
++
++ 47, 47, 47, 47, 47, 47, 47, 47, 47, 47,
++ 47, 47, 47, 47, 47, 47, 47, 47, 47
++ },
++
++ {
++ 9, -48, -48, -48, -48, -48, -48, -48, -48, -48,
++ -48, -48, -48, -48, -48, -48, -48, -48, -48, -48,
++ -48, -48, -48, -48, -48, -48, -48, -48, -48, -48,
++ -48, -48, -48, -48, -48, -48, -48, -48, -48
++ },
++
++ {
++ 9, -49, -49, -49, -49, -49, -49, -49, -49, -49,
++ -49, -49, -49, -49, -49, -49, -49, -49, -49, -49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++
++ },
++
++ {
++ 9, -50, -50, -50, -50, -50, -50, -50, -50, -50,
++ -50, -50, -50, -50, -50, -50, -50, -50, -50, -50,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 77, 49, 49, 49
++ },
++
++ {
++ 9, -51, -51, -51, -51, -51, -51, -51, -51, -51,
++ -51, -51, -51, -51, -51, -51, -51, -51, -51, -51,
++ 49, 49, 49, 49, 49, 49, 49, 49, 78, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -52, -52, -52, -52, -52, -52, -52, -52, -52,
++ -52, -52, -52, -52, -52, -52, -52, -52, -52, -52,
++
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 79, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -53, -53, -53, -53, -53, -53, -53, -53, -53,
++ -53, -53, -53, -53, -53, -53, -53, -53, -53, -53,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 80, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -54, -54, -54, -54, -54, -54, -54, -54, -54,
++ -54, -54, -54, -54, -54, -54, -54, -54, -54, -54,
++ 49, 81, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++
++ },
++
++ {
++ 9, -55, -55, -55, -55, -55, -55, -55, -55, -55,
++ -55, -55, -55, -55, -55, -55, -55, -55, -55, -55,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 82, 49, 49
++ },
++
++ {
++ 9, -56, 56, -56, -56, -56, -56, -56, -56, -56,
++ -56, -56, -56, -56, -56, -56, -56, -56, -56, -56,
++ -56, -56, -56, -56, -56, -56, -56, -56, -56, -56,
++ -56, -56, -56, -56, -56, -56, -56, -56, -56
++ },
++
++ {
++ 9, 57, 57, 58, 57, 57, 57, 57, 57, 57,
++ 57, 57, 57, 57, 57, 57, 57, 57, 57, 57,
++
++ 57, 57, 57, 57, 57, 57, 57, 57, 57, 57,
++ 57, 57, 57, 57, 57, 57, 57, 57, 57
++ },
++
++ {
++ 9, -58, -58, -58, -58, -58, -58, -58, -58, -58,
++ -58, -58, -58, -58, -58, -58, -58, -58, -58, -58,
++ -58, -58, -58, -58, -58, -58, -58, -58, -58, -58,
++ -58, -58, -58, -58, -58, -58, -58, -58, -58
++ },
++
++ {
++ 9, -59, -59, -59, -59, -59, -59, -59, -59, -59,
++ -59, -59, -59, -59, 59, -59, -59, -59, -59, -59,
++ -59, -59, -59, -59, -59, -59, -59, -59, -59, -59,
++ -59, -59, -59, -59, -59, -59, -59, -59, -59
++
++ },
++
++ {
++ 9, -60, -60, -60, -60, -60, -60, -60, -60, -60,
++ -60, -60, -60, -60, 59, -60, -60, -60, -60, -60,
++ -60, -60, -60, -60, -60, -60, -60, -60, -60, -60,
++ -60, -60, -60, -60, -60, -60, -60, -60, -60
++ },
++
++ {
++ 9, -61, -61, -61, -61, -61, -61, -61, -61, -61,
++ -61, -61, 60, -61, 61, -61, 62, -61, -61, -61,
++ 62, 62, 62, 62, 62, 62, 62, 62, 62, 62,
++ 62, 62, 62, 62, 62, 62, 62, 62, 62
++ },
++
++ {
++ 9, -62, -62, -62, -62, -62, -62, -62, -62, -62,
++ -62, -62, -62, -62, 62, -62, 62, -62, -62, -62,
++
++ 62, 62, 62, 62, 62, 62, 62, 62, 62, 62,
++ 62, 62, 62, 62, 62, 62, 62, 62, 62
++ },
++
++ {
++ 9, -63, 63, 64, -63, -63, -63, -63, -63, -63,
++ -63, -63, -63, -63, -63, -63, -63, -63, -63, -63,
++ -63, -63, -63, -63, -63, -63, -63, -63, -63, -63,
++ -63, -63, -63, -63, -63, -63, -63, -63, -63
++ },
++
++ {
++ 9, -64, -64, -64, -64, -64, -64, -64, -64, -64,
++ -64, -64, -64, -64, -64, -64, -64, -64, -64, -64,
++ -64, -64, -64, -64, -64, -64, -64, -64, -64, -64,
++ -64, -64, -64, -64, -64, -64, -64, -64, -64
++
++ },
++
++ {
++ 9, 65, 65, -65, -65, 65, 65, 65, 65, 65,
++ 65, 65, 65, 65, 65, 65, 65, -65, 65, 65,
++ 65, 65, 65, 65, 65, 65, 65, 65, 65, 65,
++ 65, 65, 65, 65, 65, 65, 65, 65, 65
++ },
++
++ {
++ 9, -66, -66, -66, -66, -66, -66, -66, -66, -66,
++ -66, -66, -66, -66, -66, -66, -66, -66, -66, -66,
++ -66, -66, -66, -66, -66, -66, -66, -66, -66, -66,
++ -66, -66, -66, -66, -66, -66, -66, -66, -66
++ },
++
++ {
++ 9, -67, -67, -67, -67, -67, -67, -67, -67, -67,
++ -67, -67, -67, -67, -67, -67, -67, -67, -67, -67,
++
++ -67, -67, -67, -67, -67, -67, -67, -67, -67, -67,
++ -67, -67, -67, -67, -67, -67, -67, -67, -67
++ },
++
++ {
++ 9, -68, -68, -68, -68, -68, -68, -68, -68, -68,
++ -68, -68, -68, -68, -68, -68, -68, -68, -68, -68,
++ -68, -68, -68, -68, -68, -68, -68, -68, -68, -68,
++ -68, -68, -68, -68, -68, -68, -68, -68, -68
++ },
++
++ {
++ 9, -69, -69, -69, -69, -69, -69, -69, -69, -69,
++ -69, -69, -69, -69, -69, -69, -69, -69, -69, -69,
++ -69, -69, -69, -69, -69, -69, -69, -69, -69, -69,
++ -69, -69, -69, -69, -69, -69, -69, -69, -69
++
++ },
++
++ {
++ 9, -70, -70, -70, -70, -70, -70, -70, -70, -70,
++ -70, -70, -70, -70, -70, -70, -70, -70, -70, -70,
++ -70, -70, -70, -70, -70, -70, -70, -70, -70, -70,
++ -70, -70, -70, -70, -70, -70, -70, -70, -70
++ },
++
++ {
++ 9, -71, -71, -71, -71, -71, -71, -71, -71, -71,
++ -71, -71, -71, -71, -71, -71, -71, -71, -71, -71,
++ -71, -71, -71, -71, -71, -71, -71, -71, -71, -71,
++ -71, -71, -71, -71, -71, -71, -71, -71, -71
++ },
++
++ {
++ 9, -72, -72, -72, -72, -72, -72, -72, -72, -72,
++ -72, -72, -72, -72, -72, -72, -72, -72, -72, -72,
++
++ -72, -72, -72, -72, -72, -72, -72, -72, -72, -72,
++ -72, -72, -72, -72, -72, -72, -72, -72, -72
++ },
++
++ {
++ 9, -73, -73, -73, -73, -73, -73, -73, -73, -73,
++ -73, -73, -73, -73, -73, -73, -73, -73, -73, -73,
++ -73, -73, -73, -73, -73, -73, -73, -73, -73, -73,
++ -73, -73, -73, -73, -73, -73, -73, -73, -73
++ },
++
++ {
++ 9, -74, -74, -74, -74, -74, -74, -74, -74, -74,
++ -74, -74, -74, -74, -74, -74, -74, -74, -74, -74,
++ -74, -74, -74, -74, -74, -74, -74, -74, -74, -74,
++ -74, -74, -74, -74, -74, -74, -74, -74, -74
++
++ },
++
++ {
++ 9, -75, -75, -75, -75, -75, -75, -75, -75, -75,
++ -75, -75, -75, -75, -75, -75, -75, -75, -75, -75,
++ -75, -75, -75, -75, -75, -75, -75, -75, -75, -75,
++ -75, -75, -75, -75, -75, -75, -75, -75, -75
++ },
++
++ {
++ 9, 76, 76, -76, 76, 76, 76, 76, 76, 76,
++ 76, 76, 76, 76, 76, 76, 76, 76, 76, 76,
++ 76, 76, 76, 76, 76, 76, 76, 76, 76, 76,
++ 76, 76, 76, 76, 76, 76, 76, 76, 76
++ },
++
++ {
++ 9, -77, 83, -77, -77, -77, -77, -77, -77, -77,
++ -77, -77, -77, -77, -77, -77, -77, -77, -77, -77,
++
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -78, -78, -78, -78, -78, -78, -78, -78, -78,
++ -78, -78, -78, -78, -78, -78, -78, -78, -78, -78,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 84, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -79, -79, -79, -79, -79, -79, -79, -79, -79,
++ -79, -79, -79, -79, -79, -79, -79, -79, -79, -79,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 85, 49, 49, 49, 49, 49
++
++ },
++
++ {
++ 9, -80, -80, -80, -80, -80, -80, -80, -80, -80,
++ -80, -80, -80, -80, -80, -80, -80, -80, -80, -80,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 86, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -81, -81, -81, -81, -81, -81, -81, -81, -81,
++ -81, -81, -81, -81, -81, -81, -81, -81, -81, -81,
++ 49, 49, 49, 49, 87, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -82, 88, -82, -82, -82, -82, -82, -82, -82,
++ -82, -82, -82, -82, -82, -82, -82, -82, -82, -82,
++
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -83, 83, -83, -83, -83, -83, -83, -83, -83,
++ -83, -83, -83, -83, -83, -83, -83, -83, -83, -83,
++ -83, -83, -83, -83, -83, -83, -83, -83, -83, -83,
++ -83, -83, -83, -83, -83, -83, -83, -83, -83
++ },
++
++ {
++ 9, -84, 89, -84, -84, -84, -84, -84, -84, -84,
++ -84, -84, -84, -84, -84, -84, -84, -84, -84, -84,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++
++ },
++
++ {
++ 9, -85, -85, -85, -85, -85, -85, -85, -85, -85,
++ -85, -85, -85, -85, -85, -85, -85, -85, -85, -85,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 90, 49
++ },
++
++ {
++ 9, -86, -86, -86, -86, -86, -86, -86, -86, -86,
++ -86, -86, -86, -86, -86, -86, -86, -86, -86, -86,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 91, 49, 49, 49, 49
++ },
++
++ {
++ 9, -87, -87, -87, -87, -87, -87, -87, -87, -87,
++ -87, -87, -87, -87, -87, -87, -87, -87, -87, -87,
++
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 92,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -88, 88, -88, -88, -88, -88, -88, -88, -88,
++ -88, -88, -88, -88, -88, -88, -88, -88, -88, -88,
++ -88, -88, -88, -88, -88, -88, -88, -88, -88, -88,
++ -88, -88, -88, -88, -88, -88, -88, -88, -88
++ },
++
++ {
++ 9, -89, 89, -89, -89, -89, -89, -89, -89, -89,
++ -89, -89, -89, -89, -89, -89, -89, -89, -89, -89,
++ -89, -89, -89, -89, -89, -89, -89, -89, -89, -89,
++ -89, -89, -89, -89, -89, -89, -89, -89, -89
++
++ },
++
++ {
++ 9, -90, -90, -90, -90, -90, -90, -90, -90, -90,
++ -90, -90, -90, -90, -90, -90, -90, -90, -90, -90,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 93, 49, 49
++ },
++
++ {
++ 9, -91, -91, -91, -91, -91, -91, -91, -91, -91,
++ -91, -91, -91, -91, -91, -91, -91, -91, -91, -91,
++ 49, 49, 49, 49, 94, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -92, 95, -92, -92, -92, -92, -92, -92, -92,
++ -92, -92, -92, -92, -92, -92, -92, -92, -92, -92,
++
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -93, -93, -93, -93, -93, -93, -93, -93, -93,
++ -93, -93, -93, -93, -93, -93, -93, -93, -93, -93,
++ 49, 49, 49, 49, 96, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -94, 97, -94, -94, -94, -94, -94, -94, -94,
++ -94, -94, -94, -94, -94, -94, -94, -94, -94, -94,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++
++ },
++
++ {
++ 9, -95, 95, -95, -95, -95, -95, -95, -95, -95,
++ -95, -95, -95, -95, -95, -95, -95, -95, -95, -95,
++ -95, -95, -95, -95, -95, -95, -95, -95, -95, -95,
++ -95, -95, -95, -95, -95, -95, -95, -95, -95
++ },
++
++ {
++ 9, -96, 98, -96, -96, -96, -96, -96, -96, -96,
++ -96, -96, -96, -96, -96, -96, -96, -96, -96, -96,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49, 49,
++ 49, 49, 49, 49, 49, 49, 49, 49, 49
++ },
++
++ {
++ 9, -97, 97, -97, -97, -97, -97, -97, -97, -97,
++ -97, -97, -97, -97, -97, -97, -97, -97, -97, -97,
++
++ -97, -97, -97, -97, -97, -97, -97, -97, -97, -97,
++ -97, -97, -97, -97, -97, -97, -97, -97, -97
++ },
++
++ {
++ 9, -98, 98, -98, -98, -98, -98, -98, -98, -98,
++ -98, -98, -98, -98, -98, -98, -98, -98, -98, -98,
++ -98, -98, -98, -98, -98, -98, -98, -98, -98, -98,
++ -98, -98, -98, -98, -98, -98, -98, -98, -98
++ },
++
++ } ;
++
++static yy_state_type yy_get_previous_state (void );
++static yy_state_type yy_try_NUL_trans (yy_state_type current_state );
++static int yy_get_next_buffer (void );
++static void yy_fatal_error (yyconst char msg[] );
++
++/* Done after the current pattern has been matched and before the
++ * corresponding action - sets up sensors_yytext.
++ */
++#define YY_DO_BEFORE_ACTION \
++ (yytext_ptr) = yy_bp; \
++ sensors_yyleng = (size_t) (yy_cp - yy_bp); \
++ (yy_hold_char) = *yy_cp; \
++ *yy_cp = '\0'; \
++ (yy_c_buf_p) = yy_cp;
++
++#define YY_NUM_RULES 50
++#define YY_END_OF_BUFFER 51
++/* This struct is not used in this scanner,
++ but its presence is necessary. */
++struct yy_trans_info
++ {
++ flex_int32_t yy_verify;
++ flex_int32_t yy_nxt;
++ };
++static yyconst flex_int16_t yy_accept[99] =
++ { 0,
++ 0, 0, 0, 0, 0, 0, 13, 13, 51, 12,
++ 1, 2, 3, 11, 11, 11, 11, 11, 11, 33,
++ 15, 16, 31, 18, 25, 26, 23, 21, 27, 22,
++ 33, 24, 20, 28, 32, 33, 29, 30, 49, 36,
++ 39, 48, 13, 14, 1, 2, 3, 4, 11, 11,
++ 11, 11, 11, 11, 11, 15, 18, 19, 20, 34,
++ 20, 32, 35, 17, 49, 38, 47, 37, 40, 41,
++ 42, 43, 44, 45, 46, 13, 8, 11, 11, 11,
++ 11, 6, 8, 9, 11, 11, 11, 6, 9, 11,
++ 11, 5, 11, 10, 5, 7, 10, 7
++
++ } ;
++
++static yyconst flex_int32_t yy_ec[256] =
++ { 0,
++ 1, 1, 1, 1, 1, 1, 1, 1, 2, 3,
++ 2, 2, 2, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 2, 1, 4, 5, 1, 1, 1, 1, 6,
++ 7, 8, 9, 10, 11, 12, 13, 14, 14, 14,
++ 14, 14, 14, 14, 14, 14, 14, 1, 1, 1,
++ 1, 1, 1, 15, 16, 16, 16, 16, 16, 16,
++ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
++ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
++ 1, 17, 1, 18, 16, 19, 20, 21, 22, 23,
++
++ 24, 25, 26, 27, 28, 23, 23, 29, 30, 31,
++ 32, 33, 23, 34, 35, 36, 37, 38, 23, 23,
++ 23, 23, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
++ 1, 1, 1, 1, 1
++ } ;
++
++extern int sensors_yy_flex_debug;
++int sensors_yy_flex_debug = 0;
++
++/* The intent behind this definition is that it'll catch
++ * any uses of REJECT which flex missed.
++ */
++#define REJECT reject_used_but_not_detected
++#define yymore() yymore_used_but_not_detected
++#define YY_MORE_ADJ 0
++#define YY_RESTORE_YY_MORE_OFFSET
++char *sensors_yytext;
++#line 1 "lib/conf-lex.l"
++#line 2 "lib/conf-lex.l"
++/*
++ conf-lex.l - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#include <stdlib.h>
++#include <string.h>
++
++#include "general.h"
++#include "data.h"
++#include "conf-parse.h"
++#include "error.h"
++#include "scanner.h"
++
++static int buffer_count;
++static int buffer_max;
++static char *buffer;
++
++char sensors_lex_error[100];
++
++const char *sensors_yyfilename;
++int sensors_yylineno;
++
++#define buffer_malloc() sensors_malloc_array(&buffer,&buffer_count,\
++ &buffer_max,1)
++#define buffer_free() sensors_free_array(&buffer,&buffer_count,\
++ &buffer_max)
++#define buffer_add_char(c) sensors_add_array_el(c,&buffer,\
++ &buffer_count,\
++ &buffer_max,1)
++#define buffer_add_string(s) sensors_add_array_els(s,strlen(s),\
++ &buffer, \
++ &buffer_count,&buffer_max,1)
++
++/* Scanner for configuration files */
++/* All states are exclusive */
++
++
++
++/* Any whitespace-like character */
++/* Note: `10', `10.4' and `.4' are valid, `10.' is not */
++/* Only positive whole numbers are recognized here */
++#line 1255 "<stdout>"
++
++#define INITIAL 0
++#define MIDDLE 1
++#define STRING 2
++#define ERR 3
++
++#ifndef YY_NO_UNISTD_H
++/* Special case for "unistd.h", since it is non-ANSI. We include it way
++ * down here because we want the user's section 1 to have been scanned first.
++ * The user has a chance to override it with an option.
++ */
++#include <unistd.h>
++#endif
++
++#ifndef YY_EXTRA_TYPE
++#define YY_EXTRA_TYPE void *
++#endif
++
++static int yy_init_globals (void );
++
++/* Accessor methods to globals.
++ These are made visible to non-reentrant scanners for convenience. */
++
++int sensors_yylex_destroy (void );
++
++int sensors_yyget_debug (void );
++
++void sensors_yyset_debug (int debug_flag );
++
++YY_EXTRA_TYPE sensors_yyget_extra (void );
++
++void sensors_yyset_extra (YY_EXTRA_TYPE user_defined );
++
++FILE *sensors_yyget_in (void );
++
++void sensors_yyset_in (FILE * in_str );
++
++FILE *sensors_yyget_out (void );
++
++void sensors_yyset_out (FILE * out_str );
++
++int sensors_yyget_leng (void );
++
++char *sensors_yyget_text (void );
++
++int sensors_yyget_lineno (void );
++
++void sensors_yyset_lineno (int line_number );
++
++/* Macros after this point can all be overridden by user definitions in
++ * section 1.
++ */
++
++#ifndef YY_SKIP_YYWRAP
++#ifdef __cplusplus
++extern "C" int sensors_yywrap (void );
++#else
++extern int sensors_yywrap (void );
++#endif
++#endif
++
++#ifndef yytext_ptr
++static void yy_flex_strncpy (char *,yyconst char *,int );
++#endif
++
++#ifdef YY_NEED_STRLEN
++static int yy_flex_strlen (yyconst char * );
++#endif
++
++#ifndef YY_NO_INPUT
++
++#ifdef __cplusplus
++static int yyinput (void );
++#else
++static int input (void );
++#endif
++
++#endif
++
++/* Amount of stuff to slurp up with each read. */
++#ifndef YY_READ_BUF_SIZE
++#ifdef __ia64__
++/* On IA-64, the buffer size is 16k, not 8k */
++#define YY_READ_BUF_SIZE 16384
++#else
++#define YY_READ_BUF_SIZE 8192
++#endif /* __ia64__ */
++#endif
++
++/* Copy whatever the last rule matched to the standard output. */
++#ifndef ECHO
++/* This used to be an fputs(), but since the string might contain NUL's,
++ * we now use fwrite().
++ */
++#define ECHO do { if (fwrite( sensors_yytext, sensors_yyleng, 1, sensors_yyout )) {} } while (0)
++#endif
++
++/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL,
++ * is returned in "result".
++ */
++#ifndef YY_INPUT
++#define YY_INPUT(buf,result,max_size) \
++ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
++ { \
++ int c = '*'; \
++ size_t n; \
++ for ( n = 0; n < max_size && \
++ (c = getc( sensors_yyin )) != EOF && c != '\n'; ++n ) \
++ buf[n] = (char) c; \
++ if ( c == '\n' ) \
++ buf[n++] = (char) c; \
++ if ( c == EOF && ferror( sensors_yyin ) ) \
++ YY_FATAL_ERROR( "input in flex scanner failed" ); \
++ result = n; \
++ } \
++ else \
++ { \
++ errno=0; \
++ while ( (result = fread(buf, 1, max_size, sensors_yyin))==0 && ferror(sensors_yyin)) \
++ { \
++ if( errno != EINTR) \
++ { \
++ YY_FATAL_ERROR( "input in flex scanner failed" ); \
++ break; \
++ } \
++ errno=0; \
++ clearerr(sensors_yyin); \
++ } \
++ }\
++\
++
++#endif
++
++/* No semi-colon after return; correct usage is to write "yyterminate();" -
++ * we don't want an extra ';' after the "return" because that will cause
++ * some compilers to complain about unreachable statements.
++ */
++#ifndef yyterminate
++#define yyterminate() return YY_NULL
++#endif
++
++/* Number of entries by which start-condition stack grows. */
++#ifndef YY_START_STACK_INCR
++#define YY_START_STACK_INCR 25
++#endif
++
++/* Report a fatal error. */
++#ifndef YY_FATAL_ERROR
++#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
++#endif
++
++/* end tables serialization structures and prototypes */
++
++/* Default declaration of generated scanner - a define so the user can
++ * easily add parameters.
++ */
++#ifndef YY_DECL
++#define YY_DECL_IS_OURS 1
++
++extern int sensors_yylex (void);
++
++#define YY_DECL int sensors_yylex (void)
++#endif /* !YY_DECL */
++
++/* Code executed at the beginning of each rule, after sensors_yytext and sensors_yyleng
++ * have been set up.
++ */
++#ifndef YY_USER_ACTION
++#define YY_USER_ACTION
++#endif
++
++/* Code executed at the end of each rule. */
++#ifndef YY_BREAK
++#define YY_BREAK break;
++#endif
++
++#define YY_RULE_SETUP \
++ YY_USER_ACTION
++
++/** The main scanner function which does all the work.
++ */
++YY_DECL
++{
++ register yy_state_type yy_current_state;
++ register char *yy_cp, *yy_bp;
++ register int yy_act;
++
++#line 80 "lib/conf-lex.l"
++
++
++ /*
++ * STATE: INITIAL
++ */
++
++#line 1450 "<stdout>"
++
++ if ( !(yy_init) )
++ {
++ (yy_init) = 1;
++
++#ifdef YY_USER_INIT
++ YY_USER_INIT;
++#endif
++
++ if ( ! (yy_start) )
++ (yy_start) = 1; /* first start state */
++
++ if ( ! sensors_yyin )
++ sensors_yyin = stdin;
++
++ if ( ! sensors_yyout )
++ sensors_yyout = stdout;
++
++ if ( ! YY_CURRENT_BUFFER ) {
++ sensors_yyensure_buffer_stack ();
++ YY_CURRENT_BUFFER_LVALUE =
++ sensors_yy_create_buffer(sensors_yyin,YY_BUF_SIZE );
++ }
++
++ sensors_yy_load_buffer_state( );
++ }
++
++ while ( 1 ) /* loops until end-of-file is reached */
++ {
++ yy_cp = (yy_c_buf_p);
++
++ /* Support of sensors_yytext. */
++ *yy_cp = (yy_hold_char);
++
++ /* yy_bp points to the position in yy_ch_buf of the start of
++ * the current run.
++ */
++ yy_bp = yy_cp;
++
++ yy_current_state = (yy_start);
++yy_match:
++ while ( (yy_current_state = yy_nxt[yy_current_state][ yy_ec[YY_SC_TO_UI(*yy_cp)] ]) > 0 )
++ ++yy_cp;
++
++ yy_current_state = -yy_current_state;
++
++yy_find_action:
++ yy_act = yy_accept[yy_current_state];
++
++ YY_DO_BEFORE_ACTION;
++
++do_action: /* This label is used only to access EOF actions. */
++
++ switch ( yy_act )
++ { /* beginning of action switch */
++
++case YY_STATE_EOF(INITIAL):
++#line 88 "lib/conf-lex.l"
++{ /* EOF from this state terminates */
++ return 0;
++ }
++ YY_BREAK
++case 1:
++YY_RULE_SETUP
++#line 92 "lib/conf-lex.l"
++; /* eat as many blanks as possible at once */
++ YY_BREAK
++case 2:
++/* rule 2 can match eol */
++YY_RULE_SETUP
++#line 94 "lib/conf-lex.l"
++{ /* eat a bare newline (possibly preceded by blanks) */
++ sensors_yylineno++;
++ }
++ YY_BREAK
++/* comments */
++case 3:
++YY_RULE_SETUP
++#line 100 "lib/conf-lex.l"
++; /* eat the rest of the line after comment char */
++ YY_BREAK
++case 4:
++/* rule 4 can match eol */
++YY_RULE_SETUP
++#line 102 "lib/conf-lex.l"
++{ /* eat the rest of the line after comment char */
++ sensors_yylineno++;
++ }
++ YY_BREAK
++/*
++ * Keywords must be followed by whitespace - eat that too.
++ * If there isn't trailing whitespace, we still need to
++ * accept it as lexically correct (even though the parser
++ * will reject it anyway.)
++ */
++case 5:
++YY_RULE_SETUP
++#line 113 "lib/conf-lex.l"
++{
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return LABEL;
++ }
++ YY_BREAK
++case 6:
++YY_RULE_SETUP
++#line 120 "lib/conf-lex.l"
++{
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return SET;
++ }
++ YY_BREAK
++case 7:
++YY_RULE_SETUP
++#line 127 "lib/conf-lex.l"
++{
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return COMPUTE;
++ }
++ YY_BREAK
++case 8:
++YY_RULE_SETUP
++#line 134 "lib/conf-lex.l"
++{
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return BUS;
++ }
++ YY_BREAK
++case 9:
++YY_RULE_SETUP
++#line 141 "lib/conf-lex.l"
++{
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return CHIP;
++ }
++ YY_BREAK
++case 10:
++YY_RULE_SETUP
++#line 148 "lib/conf-lex.l"
++{
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return IGNORE;
++ }
++ YY_BREAK
++/* Anything else at the beginning of a line is an error */
++case 11:
++#line 158 "lib/conf-lex.l"
++case 12:
++YY_RULE_SETUP
++#line 158 "lib/conf-lex.l"
++{
++ BEGIN(ERR);
++ strcpy(sensors_lex_error,"Invalid keyword");
++ return ERROR;
++ }
++ YY_BREAK
++
++/*
++ * STATE: ERROR
++ */
++
++case 13:
++YY_RULE_SETUP
++#line 171 "lib/conf-lex.l"
++; /* eat whatever is left on this line */
++ YY_BREAK
++case 14:
++/* rule 14 can match eol */
++YY_RULE_SETUP
++#line 173 "lib/conf-lex.l"
++{
++ BEGIN(INITIAL);
++ sensors_yylineno++;
++ return EOL;
++ }
++ YY_BREAK
++
++/*
++ * STATE: MIDDLE
++ */
++
++case 15:
++YY_RULE_SETUP
++#line 186 "lib/conf-lex.l"
++; /* eat as many blanks as possible at once */
++ YY_BREAK
++case 16:
++/* rule 16 can match eol */
++YY_RULE_SETUP
++#line 188 "lib/conf-lex.l"
++{ /* newline here sends EOL token to parser */
++ BEGIN(INITIAL);
++ sensors_yylineno++;
++ return EOL;
++ }
++ YY_BREAK
++case YY_STATE_EOF(MIDDLE):
++#line 194 "lib/conf-lex.l"
++{ /* EOF here sends EOL token to parser also */
++ BEGIN(INITIAL);
++ return EOL;
++ }
++ YY_BREAK
++case 17:
++/* rule 17 can match eol */
++YY_RULE_SETUP
++#line 199 "lib/conf-lex.l"
++{ /* eat an escaped newline with no state change */
++ sensors_yylineno++;
++ }
++ YY_BREAK
++/* comments */
++case 18:
++YY_RULE_SETUP
++#line 205 "lib/conf-lex.l"
++; /* eat the rest of the line after comment char */
++ YY_BREAK
++case 19:
++/* rule 19 can match eol */
++YY_RULE_SETUP
++#line 207 "lib/conf-lex.l"
++{ /* eat the rest of the line after comment char */
++ BEGIN(INITIAL);
++ sensors_yylineno++;
++ return EOL;
++ }
++ YY_BREAK
++/* A number */
++case 20:
++YY_RULE_SETUP
++#line 215 "lib/conf-lex.l"
++{
++ sensors_yylval.value = atof(sensors_yytext);
++ return FLOAT;
++ }
++ YY_BREAK
++/* Some operators */
++case 21:
++YY_RULE_SETUP
++#line 222 "lib/conf-lex.l"
++return '+';
++ YY_BREAK
++case 22:
++YY_RULE_SETUP
++#line 223 "lib/conf-lex.l"
++return '-';
++ YY_BREAK
++case 23:
++YY_RULE_SETUP
++#line 224 "lib/conf-lex.l"
++return '*';
++ YY_BREAK
++case 24:
++YY_RULE_SETUP
++#line 225 "lib/conf-lex.l"
++return '/';
++ YY_BREAK
++case 25:
++YY_RULE_SETUP
++#line 226 "lib/conf-lex.l"
++return '(';
++ YY_BREAK
++case 26:
++YY_RULE_SETUP
++#line 227 "lib/conf-lex.l"
++return ')';
++ YY_BREAK
++case 27:
++YY_RULE_SETUP
++#line 228 "lib/conf-lex.l"
++return ',';
++ YY_BREAK
++case 28:
++YY_RULE_SETUP
++#line 229 "lib/conf-lex.l"
++return '@';
++ YY_BREAK
++case 29:
++YY_RULE_SETUP
++#line 230 "lib/conf-lex.l"
++return '^';
++ YY_BREAK
++case 30:
++YY_RULE_SETUP
++#line 231 "lib/conf-lex.l"
++return '`';
++ YY_BREAK
++/* Quoted string */
++case 31:
++YY_RULE_SETUP
++#line 235 "lib/conf-lex.l"
++{
++ buffer_malloc();
++ BEGIN(STRING);
++ }
++ YY_BREAK
++/* A normal, unquoted identifier */
++case 32:
++YY_RULE_SETUP
++#line 242 "lib/conf-lex.l"
++{
++ sensors_yylval.name = strdup(sensors_yytext);
++ if (! sensors_yylval.name)
++ sensors_fatal_error("conf-lex.l",
++ "Allocating a new string");
++
++ return NAME;
++ }
++ YY_BREAK
++/* anything else is bogus */
++case 33:
++#line 254 "lib/conf-lex.l"
++case 34:
++#line 255 "lib/conf-lex.l"
++case 35:
++YY_RULE_SETUP
++#line 255 "lib/conf-lex.l"
++{
++ BEGIN(ERR);
++ return ERROR;
++ }
++ YY_BREAK
++
++/*
++ * STATE: STRING
++ */
++
++/* Oops, newline or EOF while in a string is not good */
++case 36:
++/* rule 36 can match eol */
++#line 270 "lib/conf-lex.l"
++case 37:
++/* rule 37 can match eol */
++YY_RULE_SETUP
++#line 270 "lib/conf-lex.l"
++{
++ buffer_add_char("\0");
++ strcpy(sensors_lex_error,
++ "No matching double quote.");
++ buffer_free();
++ yyless(0);
++ BEGIN(ERR);
++ return ERROR;
++ }
++ YY_BREAK
++case YY_STATE_EOF(STRING):
++#line 280 "lib/conf-lex.l"
++{
++ strcpy(sensors_lex_error,
++ "Reached end-of-file without a matching double quote.");
++ buffer_free();
++ BEGIN(MIDDLE);
++ return ERROR;
++ }
++ YY_BREAK
++/* At the end */
++case 38:
++YY_RULE_SETUP
++#line 290 "lib/conf-lex.l"
++{
++ buffer_add_char("\0");
++ strcpy(sensors_lex_error,
++ "Quoted strings must be separated by whitespace.");
++ buffer_free();
++ BEGIN(ERR);
++ return ERROR;
++ }
++ YY_BREAK
++case 39:
++YY_RULE_SETUP
++#line 299 "lib/conf-lex.l"
++{
++ buffer_add_char("\0");
++ sensors_yylval.name = strdup(buffer);
++ if (! sensors_yylval.name)
++ sensors_fatal_error("conf-lex.l",
++ "Allocating a new string");
++ buffer_free();
++ BEGIN(MIDDLE);
++ return NAME;
++ }
++ YY_BREAK
++case 40:
++YY_RULE_SETUP
++#line 310 "lib/conf-lex.l"
++buffer_add_char("\a");
++ YY_BREAK
++case 41:
++YY_RULE_SETUP
++#line 311 "lib/conf-lex.l"
++buffer_add_char("\b");
++ YY_BREAK
++case 42:
++YY_RULE_SETUP
++#line 312 "lib/conf-lex.l"
++buffer_add_char("\f");
++ YY_BREAK
++case 43:
++YY_RULE_SETUP
++#line 313 "lib/conf-lex.l"
++buffer_add_char("\n");
++ YY_BREAK
++case 44:
++YY_RULE_SETUP
++#line 314 "lib/conf-lex.l"
++buffer_add_char("\r");
++ YY_BREAK
++case 45:
++YY_RULE_SETUP
++#line 315 "lib/conf-lex.l"
++buffer_add_char("\t");
++ YY_BREAK
++case 46:
++YY_RULE_SETUP
++#line 316 "lib/conf-lex.l"
++buffer_add_char("\v");
++ YY_BREAK
++/* Other escapes: just copy the character behind the slash */
++case 47:
++YY_RULE_SETUP
++#line 320 "lib/conf-lex.l"
++{
++ buffer_add_char(&sensors_yytext[1]);
++ }
++ YY_BREAK
++/* Anything else (including a bare '\' which may be followed by EOF) */
++case 48:
++#line 327 "lib/conf-lex.l"
++case 49:
++YY_RULE_SETUP
++#line 327 "lib/conf-lex.l"
++{
++ buffer_add_string(sensors_yytext);
++ }
++ YY_BREAK
++
++case 50:
++YY_RULE_SETUP
++#line 332 "lib/conf-lex.l"
++YY_FATAL_ERROR( "flex scanner jammed" );
++ YY_BREAK
++#line 1903 "<stdout>"
++ case YY_STATE_EOF(ERR):
++ yyterminate();
++
++ case YY_END_OF_BUFFER:
++ {
++ /* Amount of text matched not including the EOB char. */
++ int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
++
++ /* Undo the effects of YY_DO_BEFORE_ACTION. */
++ *yy_cp = (yy_hold_char);
++ YY_RESTORE_YY_MORE_OFFSET
++
++ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
++ {
++ /* We're scanning a new file or input source. It's
++ * possible that this happened because the user
++ * just pointed sensors_yyin at a new source and called
++ * sensors_yylex(). If so, then we have to assure
++ * consistency between YY_CURRENT_BUFFER and our
++ * globals. Here is the right place to do so, because
++ * this is the first action (other than possibly a
++ * back-up) that will match for the new input source.
++ */
++ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
++ YY_CURRENT_BUFFER_LVALUE->yy_input_file = sensors_yyin;
++ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
++ }
++
++ /* Note that here we test for yy_c_buf_p "<=" to the position
++ * of the first EOB in the buffer, since yy_c_buf_p will
++ * already have been incremented past the NUL character
++ * (since all states make transitions on EOB to the
++ * end-of-buffer state). Contrast this with the test
++ * in input().
++ */
++ if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
++ { /* This was really a NUL. */
++ yy_state_type yy_next_state;
++
++ (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
++
++ yy_current_state = yy_get_previous_state( );
++
++ /* Okay, we're now positioned to make the NUL
++ * transition. We couldn't have
++ * yy_get_previous_state() go ahead and do it
++ * for us because it doesn't know how to deal
++ * with the possibility of jamming (and we don't
++ * want to build jamming into it because then it
++ * will run more slowly).
++ */
++
++ yy_next_state = yy_try_NUL_trans( yy_current_state );
++
++ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
++
++ if ( yy_next_state )
++ {
++ /* Consume the NUL. */
++ yy_cp = ++(yy_c_buf_p);
++ yy_current_state = yy_next_state;
++ goto yy_match;
++ }
++
++ else
++ {
++ yy_cp = (yy_c_buf_p);
++ goto yy_find_action;
++ }
++ }
++
++ else switch ( yy_get_next_buffer( ) )
++ {
++ case EOB_ACT_END_OF_FILE:
++ {
++ (yy_did_buffer_switch_on_eof) = 0;
++
++ if ( sensors_yywrap( ) )
++ {
++ /* Note: because we've taken care in
++ * yy_get_next_buffer() to have set up
++ * sensors_yytext, we can now set up
++ * yy_c_buf_p so that if some total
++ * hoser (like flex itself) wants to
++ * call the scanner after we return the
++ * YY_NULL, it'll still work - another
++ * YY_NULL will get returned.
++ */
++ (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
++
++ yy_act = YY_STATE_EOF(YY_START);
++ goto do_action;
++ }
++
++ else
++ {
++ if ( ! (yy_did_buffer_switch_on_eof) )
++ YY_NEW_FILE;
++ }
++ break;
++ }
++
++ case EOB_ACT_CONTINUE_SCAN:
++ (yy_c_buf_p) =
++ (yytext_ptr) + yy_amount_of_matched_text;
++
++ yy_current_state = yy_get_previous_state( );
++
++ yy_cp = (yy_c_buf_p);
++ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
++ goto yy_match;
++
++ case EOB_ACT_LAST_MATCH:
++ (yy_c_buf_p) =
++ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
++
++ yy_current_state = yy_get_previous_state( );
++
++ yy_cp = (yy_c_buf_p);
++ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
++ goto yy_find_action;
++ }
++ break;
++ }
++
++ default:
++ YY_FATAL_ERROR(
++ "fatal flex scanner internal error--no action found" );
++ } /* end of action switch */
++ } /* end of scanning one token */
++} /* end of sensors_yylex */
++
++/* yy_get_next_buffer - try to read in a new buffer
++ *
++ * Returns a code representing an action:
++ * EOB_ACT_LAST_MATCH -
++ * EOB_ACT_CONTINUE_SCAN - continue scanning from current position
++ * EOB_ACT_END_OF_FILE - end of file
++ */
++static int yy_get_next_buffer (void)
++{
++ register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
++ register char *source = (yytext_ptr);
++ register int number_to_move, i;
++ int ret_val;
++
++ if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
++ YY_FATAL_ERROR(
++ "fatal flex scanner internal error--end of buffer missed" );
++
++ if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
++ { /* Don't try to fill the buffer, so this is an EOF. */
++ if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
++ {
++ /* We matched a single character, the EOB, so
++ * treat this as a final EOF.
++ */
++ return EOB_ACT_END_OF_FILE;
++ }
++
++ else
++ {
++ /* We matched some text prior to the EOB, first
++ * process it.
++ */
++ return EOB_ACT_LAST_MATCH;
++ }
++ }
++
++ /* Try to read more data. */
++
++ /* First move last chars to start of buffer. */
++ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
++
++ for ( i = 0; i < number_to_move; ++i )
++ *(dest++) = *(source++);
++
++ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
++ /* don't do the read, it's not guaranteed to return an EOF,
++ * just force an EOF
++ */
++ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
++
++ else
++ {
++ int num_to_read =
++ YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
++
++ while ( num_to_read <= 0 )
++ { /* Not enough room in the buffer - grow it. */
++
++ /* just a shorter name for the current buffer */
++ YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
++
++ int yy_c_buf_p_offset =
++ (int) ((yy_c_buf_p) - b->yy_ch_buf);
++
++ if ( b->yy_is_our_buffer )
++ {
++ int new_size = b->yy_buf_size * 2;
++
++ if ( new_size <= 0 )
++ b->yy_buf_size += b->yy_buf_size / 8;
++ else
++ b->yy_buf_size *= 2;
++
++ b->yy_ch_buf = (char *)
++ /* Include room in for 2 EOB chars. */
++ sensors_yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 );
++ }
++ else
++ /* Can't grow it, we don't own it. */
++ b->yy_ch_buf = 0;
++
++ if ( ! b->yy_ch_buf )
++ YY_FATAL_ERROR(
++ "fatal error - scanner input buffer overflow" );
++
++ (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
++
++ num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
++ number_to_move - 1;
++
++ }
++
++ if ( num_to_read > YY_READ_BUF_SIZE )
++ num_to_read = YY_READ_BUF_SIZE;
++
++ /* Read in more data. */
++ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
++ (yy_n_chars), (size_t) num_to_read );
++
++ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
++ }
++
++ if ( (yy_n_chars) == 0 )
++ {
++ if ( number_to_move == YY_MORE_ADJ )
++ {
++ ret_val = EOB_ACT_END_OF_FILE;
++ sensors_yyrestart(sensors_yyin );
++ }
++
++ else
++ {
++ ret_val = EOB_ACT_LAST_MATCH;
++ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
++ YY_BUFFER_EOF_PENDING;
++ }
++ }
++
++ else
++ ret_val = EOB_ACT_CONTINUE_SCAN;
++
++ if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) {
++ /* Extend the array by 50%, plus the number we really need. */
++ yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1);
++ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) sensors_yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size );
++ if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
++ YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" );
++ }
++
++ (yy_n_chars) += number_to_move;
++ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
++ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
++
++ (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
++
++ return ret_val;
++}
++
++/* yy_get_previous_state - get the state just before the EOB char was reached */
++
++ static yy_state_type yy_get_previous_state (void)
++{
++ register yy_state_type yy_current_state;
++ register char *yy_cp;
++
++ yy_current_state = (yy_start);
++
++ for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
++ {
++ yy_current_state = yy_nxt[yy_current_state][(*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1)];
++ }
++
++ return yy_current_state;
++}
++
++/* yy_try_NUL_trans - try to make a transition on the NUL character
++ *
++ * synopsis
++ * next_state = yy_try_NUL_trans( current_state );
++ */
++ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state )
++{
++ register int yy_is_jam;
++
++ yy_current_state = yy_nxt[yy_current_state][1];
++ yy_is_jam = (yy_current_state <= 0);
++
++ return yy_is_jam ? 0 : yy_current_state;
++}
++
++#ifndef YY_NO_INPUT
++#ifdef __cplusplus
++ static int yyinput (void)
++#else
++ static int input (void)
++#endif
++
++{
++ int c;
++
++ *(yy_c_buf_p) = (yy_hold_char);
++
++ if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
++ {
++ /* yy_c_buf_p now points to the character we want to return.
++ * If this occurs *before* the EOB characters, then it's a
++ * valid NUL; if not, then we've hit the end of the buffer.
++ */
++ if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
++ /* This was really a NUL. */
++ *(yy_c_buf_p) = '\0';
++
++ else
++ { /* need more input */
++ int offset = (yy_c_buf_p) - (yytext_ptr);
++ ++(yy_c_buf_p);
++
++ switch ( yy_get_next_buffer( ) )
++ {
++ case EOB_ACT_LAST_MATCH:
++ /* This happens because yy_g_n_b()
++ * sees that we've accumulated a
++ * token and flags that we need to
++ * try matching the token before
++ * proceeding. But for input(),
++ * there's no matching to consider.
++ * So convert the EOB_ACT_LAST_MATCH
++ * to EOB_ACT_END_OF_FILE.
++ */
++
++ /* Reset buffer status. */
++ sensors_yyrestart(sensors_yyin );
++
++ /*FALLTHROUGH*/
++
++ case EOB_ACT_END_OF_FILE:
++ {
++ if ( sensors_yywrap( ) )
++ return EOF;
++
++ if ( ! (yy_did_buffer_switch_on_eof) )
++ YY_NEW_FILE;
++#ifdef __cplusplus
++ return yyinput();
++#else
++ return input();
++#endif
++ }
++
++ case EOB_ACT_CONTINUE_SCAN:
++ (yy_c_buf_p) = (yytext_ptr) + offset;
++ break;
++ }
++ }
++ }
++
++ c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */
++ *(yy_c_buf_p) = '\0'; /* preserve sensors_yytext */
++ (yy_hold_char) = *++(yy_c_buf_p);
++
++ return c;
++}
++#endif /* ifndef YY_NO_INPUT */
++
++/** Immediately switch to a different input stream.
++ * @param input_file A readable stream.
++ *
++ * @note This function does not reset the start condition to @c INITIAL .
++ */
++ void sensors_yyrestart (FILE * input_file )
++{
++
++ if ( ! YY_CURRENT_BUFFER ){
++ sensors_yyensure_buffer_stack ();
++ YY_CURRENT_BUFFER_LVALUE =
++ sensors_yy_create_buffer(sensors_yyin,YY_BUF_SIZE );
++ }
++
++ sensors_yy_init_buffer(YY_CURRENT_BUFFER,input_file );
++ sensors_yy_load_buffer_state( );
++}
++
++/** Switch to a different input buffer.
++ * @param new_buffer The new input buffer.
++ *
++ */
++ void sensors_yy_switch_to_buffer (YY_BUFFER_STATE new_buffer )
++{
++
++ /* TODO. We should be able to replace this entire function body
++ * with
++ * sensors_yypop_buffer_state();
++ * sensors_yypush_buffer_state(new_buffer);
++ */
++ sensors_yyensure_buffer_stack ();
++ if ( YY_CURRENT_BUFFER == new_buffer )
++ return;
++
++ if ( YY_CURRENT_BUFFER )
++ {
++ /* Flush out information for old buffer. */
++ *(yy_c_buf_p) = (yy_hold_char);
++ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
++ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
++ }
++
++ YY_CURRENT_BUFFER_LVALUE = new_buffer;
++ sensors_yy_load_buffer_state( );
++
++ /* We don't actually know whether we did this switch during
++ * EOF (sensors_yywrap()) processing, but the only time this flag
++ * is looked at is after sensors_yywrap() is called, so it's safe
++ * to go ahead and always set it.
++ */
++ (yy_did_buffer_switch_on_eof) = 1;
++}
++
++static void sensors_yy_load_buffer_state (void)
++{
++ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
++ (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
++ sensors_yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
++ (yy_hold_char) = *(yy_c_buf_p);
++}
++
++/** Allocate and initialize an input buffer state.
++ * @param file A readable stream.
++ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
++ *
++ * @return the allocated buffer state.
++ */
++ YY_BUFFER_STATE sensors_yy_create_buffer (FILE * file, int size )
++{
++ YY_BUFFER_STATE b;
++
++ b = (YY_BUFFER_STATE) sensors_yyalloc(sizeof( struct yy_buffer_state ) );
++ if ( ! b )
++ YY_FATAL_ERROR( "out of dynamic memory in sensors_yy_create_buffer()" );
++
++ b->yy_buf_size = size;
++
++ /* yy_ch_buf has to be 2 characters longer than the size given because
++ * we need to put in 2 end-of-buffer characters.
++ */
++ b->yy_ch_buf = (char *) sensors_yyalloc(b->yy_buf_size + 2 );
++ if ( ! b->yy_ch_buf )
++ YY_FATAL_ERROR( "out of dynamic memory in sensors_yy_create_buffer()" );
++
++ b->yy_is_our_buffer = 1;
++
++ sensors_yy_init_buffer(b,file );
++
++ return b;
++}
++
++/** Destroy the buffer.
++ * @param b a buffer created with sensors_yy_create_buffer()
++ *
++ */
++ void sensors_yy_delete_buffer (YY_BUFFER_STATE b )
++{
++
++ if ( ! b )
++ return;
++
++ if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
++ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
++
++ if ( b->yy_is_our_buffer )
++ sensors_yyfree((void *) b->yy_ch_buf );
++
++ sensors_yyfree((void *) b );
++}
++
++#ifndef __cplusplus
++extern int isatty (int );
++#endif /* __cplusplus */
++
++/* Initializes or reinitializes a buffer.
++ * This function is sometimes called more than once on the same buffer,
++ * such as during a sensors_yyrestart() or at EOF.
++ */
++ static void sensors_yy_init_buffer (YY_BUFFER_STATE b, FILE * file )
++
++{
++ int oerrno = errno;
++
++ sensors_yy_flush_buffer(b );
++
++ b->yy_input_file = file;
++ b->yy_fill_buffer = 1;
++
++ /* If b is the current buffer, then sensors_yy_init_buffer was _probably_
++ * called from sensors_yyrestart() or through yy_get_next_buffer.
++ * In that case, we don't want to reset the lineno or column.
++ */
++ if (b != YY_CURRENT_BUFFER){
++ b->yy_bs_lineno = 1;
++ b->yy_bs_column = 0;
++ }
++
++ b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
++
++ errno = oerrno;
++}
++
++/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
++ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
++ *
++ */
++ void sensors_yy_flush_buffer (YY_BUFFER_STATE b )
++{
++ if ( ! b )
++ return;
++
++ b->yy_n_chars = 0;
++
++ /* We always need two end-of-buffer characters. The first causes
++ * a transition to the end-of-buffer state. The second causes
++ * a jam in that state.
++ */
++ b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
++ b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
++
++ b->yy_buf_pos = &b->yy_ch_buf[0];
++
++ b->yy_at_bol = 1;
++ b->yy_buffer_status = YY_BUFFER_NEW;
++
++ if ( b == YY_CURRENT_BUFFER )
++ sensors_yy_load_buffer_state( );
++}
++
++/** Pushes the new state onto the stack. The new state becomes
++ * the current state. This function will allocate the stack
++ * if necessary.
++ * @param new_buffer The new state.
++ *
++ */
++void sensors_yypush_buffer_state (YY_BUFFER_STATE new_buffer )
++{
++ if (new_buffer == NULL)
++ return;
++
++ sensors_yyensure_buffer_stack();
++
++ /* This block is copied from sensors_yy_switch_to_buffer. */
++ if ( YY_CURRENT_BUFFER )
++ {
++ /* Flush out information for old buffer. */
++ *(yy_c_buf_p) = (yy_hold_char);
++ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
++ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
++ }
++
++ /* Only push if top exists. Otherwise, replace top. */
++ if (YY_CURRENT_BUFFER)
++ (yy_buffer_stack_top)++;
++ YY_CURRENT_BUFFER_LVALUE = new_buffer;
++
++ /* copied from sensors_yy_switch_to_buffer. */
++ sensors_yy_load_buffer_state( );
++ (yy_did_buffer_switch_on_eof) = 1;
++}
++
++/** Removes and deletes the top of the stack, if present.
++ * The next element becomes the new top.
++ *
++ */
++void sensors_yypop_buffer_state (void)
++{
++ if (!YY_CURRENT_BUFFER)
++ return;
++
++ sensors_yy_delete_buffer(YY_CURRENT_BUFFER );
++ YY_CURRENT_BUFFER_LVALUE = NULL;
++ if ((yy_buffer_stack_top) > 0)
++ --(yy_buffer_stack_top);
++
++ if (YY_CURRENT_BUFFER) {
++ sensors_yy_load_buffer_state( );
++ (yy_did_buffer_switch_on_eof) = 1;
++ }
++}
++
++/* Allocates the stack if it does not exist.
++ * Guarantees space for at least one push.
++ */
++static void sensors_yyensure_buffer_stack (void)
++{
++ int num_to_alloc;
++
++ if (!(yy_buffer_stack)) {
++
++ /* First allocation is just for 2 elements, since we don't know if this
++ * scanner will even need a stack. We use 2 instead of 1 to avoid an
++ * immediate realloc on the next call.
++ */
++ num_to_alloc = 1;
++ (yy_buffer_stack) = (struct yy_buffer_state**)sensors_yyalloc
++ (num_to_alloc * sizeof(struct yy_buffer_state*)
++ );
++ if ( ! (yy_buffer_stack) )
++ YY_FATAL_ERROR( "out of dynamic memory in sensors_yyensure_buffer_stack()" );
++
++ memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
++
++ (yy_buffer_stack_max) = num_to_alloc;
++ (yy_buffer_stack_top) = 0;
++ return;
++ }
++
++ if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
++
++ /* Increase the buffer to prepare for a possible push. */
++ int grow_size = 8 /* arbitrary grow size */;
++
++ num_to_alloc = (yy_buffer_stack_max) + grow_size;
++ (yy_buffer_stack) = (struct yy_buffer_state**)sensors_yyrealloc
++ ((yy_buffer_stack),
++ num_to_alloc * sizeof(struct yy_buffer_state*)
++ );
++ if ( ! (yy_buffer_stack) )
++ YY_FATAL_ERROR( "out of dynamic memory in sensors_yyensure_buffer_stack()" );
++
++ /* zero only the new slots.*/
++ memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
++ (yy_buffer_stack_max) = num_to_alloc;
++ }
++}
++
++/** Setup the input buffer state to scan directly from a user-specified character buffer.
++ * @param base the character buffer
++ * @param size the size in bytes of the character buffer
++ *
++ * @return the newly allocated buffer state object.
++ */
++YY_BUFFER_STATE sensors_yy_scan_buffer (char * base, yy_size_t size )
++{
++ YY_BUFFER_STATE b;
++
++ if ( size < 2 ||
++ base[size-2] != YY_END_OF_BUFFER_CHAR ||
++ base[size-1] != YY_END_OF_BUFFER_CHAR )
++ /* They forgot to leave room for the EOB's. */
++ return 0;
++
++ b = (YY_BUFFER_STATE) sensors_yyalloc(sizeof( struct yy_buffer_state ) );
++ if ( ! b )
++ YY_FATAL_ERROR( "out of dynamic memory in sensors_yy_scan_buffer()" );
++
++ b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */
++ b->yy_buf_pos = b->yy_ch_buf = base;
++ b->yy_is_our_buffer = 0;
++ b->yy_input_file = 0;
++ b->yy_n_chars = b->yy_buf_size;
++ b->yy_is_interactive = 0;
++ b->yy_at_bol = 1;
++ b->yy_fill_buffer = 0;
++ b->yy_buffer_status = YY_BUFFER_NEW;
++
++ sensors_yy_switch_to_buffer(b );
++
++ return b;
++}
++
++/** Setup the input buffer state to scan a string. The next call to sensors_yylex() will
++ * scan from a @e copy of @a str.
++ * @param yystr a NUL-terminated string to scan
++ *
++ * @return the newly allocated buffer state object.
++ * @note If you want to scan bytes that may contain NUL values, then use
++ * sensors_yy_scan_bytes() instead.
++ */
++YY_BUFFER_STATE sensors_yy_scan_string (yyconst char * yystr )
++{
++
++ return sensors_yy_scan_bytes(yystr,strlen(yystr) );
++}
++
++/** Setup the input buffer state to scan the given bytes. The next call to sensors_yylex() will
++ * scan from a @e copy of @a bytes.
++ * @param yybytes the byte buffer to scan
++ * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes.
++ *
++ * @return the newly allocated buffer state object.
++ */
++YY_BUFFER_STATE sensors_yy_scan_bytes (yyconst char * yybytes, int _yybytes_len )
++{
++ YY_BUFFER_STATE b;
++ char *buf;
++ yy_size_t n;
++ int i;
++
++ /* Get memory for full buffer, including space for trailing EOB's. */
++ n = _yybytes_len + 2;
++ buf = (char *) sensors_yyalloc(n );
++ if ( ! buf )
++ YY_FATAL_ERROR( "out of dynamic memory in sensors_yy_scan_bytes()" );
++
++ for ( i = 0; i < _yybytes_len; ++i )
++ buf[i] = yybytes[i];
++
++ buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
++
++ b = sensors_yy_scan_buffer(buf,n );
++ if ( ! b )
++ YY_FATAL_ERROR( "bad buffer in sensors_yy_scan_bytes()" );
++
++ /* It's okay to grow etc. this buffer, and we should throw it
++ * away when we're done.
++ */
++ b->yy_is_our_buffer = 1;
++
++ return b;
++}
++
++#ifndef YY_EXIT_FAILURE
++#define YY_EXIT_FAILURE 2
++#endif
++
++static void yy_fatal_error (yyconst char* msg )
++{
++ (void) fprintf( stderr, "%s\n", msg );
++ exit( YY_EXIT_FAILURE );
++}
++
++/* Redefine yyless() so it works in section 3 code. */
++
++#undef yyless
++#define yyless(n) \
++ do \
++ { \
++ /* Undo effects of setting up sensors_yytext. */ \
++ int yyless_macro_arg = (n); \
++ YY_LESS_LINENO(yyless_macro_arg);\
++ sensors_yytext[sensors_yyleng] = (yy_hold_char); \
++ (yy_c_buf_p) = sensors_yytext + yyless_macro_arg; \
++ (yy_hold_char) = *(yy_c_buf_p); \
++ *(yy_c_buf_p) = '\0'; \
++ sensors_yyleng = yyless_macro_arg; \
++ } \
++ while ( 0 )
++
++/* Accessor methods (get/set functions) to struct members. */
++
++/** Get the current line number.
++ *
++ */
++int sensors_yyget_lineno (void)
++{
++
++ return sensors_yylineno;
++}
++
++/** Get the input stream.
++ *
++ */
++FILE *sensors_yyget_in (void)
++{
++ return sensors_yyin;
++}
++
++/** Get the output stream.
++ *
++ */
++FILE *sensors_yyget_out (void)
++{
++ return sensors_yyout;
++}
++
++/** Get the length of the current token.
++ *
++ */
++int sensors_yyget_leng (void)
++{
++ return sensors_yyleng;
++}
++
++/** Get the current token.
++ *
++ */
++
++char *sensors_yyget_text (void)
++{
++ return sensors_yytext;
++}
++
++/** Set the current line number.
++ * @param line_number
++ *
++ */
++void sensors_yyset_lineno (int line_number )
++{
++
++ sensors_yylineno = line_number;
++}
++
++/** Set the input stream. This does not discard the current
++ * input buffer.
++ * @param in_str A readable stream.
++ *
++ * @see sensors_yy_switch_to_buffer
++ */
++void sensors_yyset_in (FILE * in_str )
++{
++ sensors_yyin = in_str ;
++}
++
++void sensors_yyset_out (FILE * out_str )
++{
++ sensors_yyout = out_str ;
++}
++
++int sensors_yyget_debug (void)
++{
++ return sensors_yy_flex_debug;
++}
++
++void sensors_yyset_debug (int bdebug )
++{
++ sensors_yy_flex_debug = bdebug ;
++}
++
++static int yy_init_globals (void)
++{
++ /* Initialization is the same as for the non-reentrant scanner.
++ * This function is called from sensors_yylex_destroy(), so don't allocate here.
++ */
++
++ (yy_buffer_stack) = 0;
++ (yy_buffer_stack_top) = 0;
++ (yy_buffer_stack_max) = 0;
++ (yy_c_buf_p) = (char *) 0;
++ (yy_init) = 0;
++ (yy_start) = 0;
++
++/* Defined in main.c */
++#ifdef YY_STDINIT
++ sensors_yyin = stdin;
++ sensors_yyout = stdout;
++#else
++ sensors_yyin = (FILE *) 0;
++ sensors_yyout = (FILE *) 0;
++#endif
++
++ /* For future reference: Set errno on error, since we are called by
++ * sensors_yylex_init()
++ */
++ return 0;
++}
++
++/* sensors_yylex_destroy is for both reentrant and non-reentrant scanners. */
++int sensors_yylex_destroy (void)
++{
++
++ /* Pop the buffer stack, destroying each element. */
++ while(YY_CURRENT_BUFFER){
++ sensors_yy_delete_buffer(YY_CURRENT_BUFFER );
++ YY_CURRENT_BUFFER_LVALUE = NULL;
++ sensors_yypop_buffer_state();
++ }
++
++ /* Destroy the stack itself. */
++ sensors_yyfree((yy_buffer_stack) );
++ (yy_buffer_stack) = NULL;
++
++ /* Reset the globals. This is important in a non-reentrant scanner so the next time
++ * sensors_yylex() is called, initialization will occur. */
++ yy_init_globals( );
++
++ return 0;
++}
++
++/*
++ * Internal utility routines.
++ */
++
++#ifndef yytext_ptr
++static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
++{
++ register int i;
++ for ( i = 0; i < n; ++i )
++ s1[i] = s2[i];
++}
++#endif
++
++#ifdef YY_NEED_STRLEN
++static int yy_flex_strlen (yyconst char * s )
++{
++ register int n;
++ for ( n = 0; s[n]; ++n )
++ ;
++
++ return n;
++}
++#endif
++
++void *sensors_yyalloc (yy_size_t size )
++{
++ return (void *) malloc( size );
++}
++
++void *sensors_yyrealloc (void * ptr, yy_size_t size )
++{
++ /* The cast to (char *) in the following accommodates both
++ * implementations that use char* generic pointers, and those
++ * that use void* generic pointers. It works with the latter
++ * because both ANSI C and C++ allow castless assignment from
++ * any pointer type to void*, and deal with argument conversions
++ * as though doing an assignment.
++ */
++ return (void *) realloc( (char *) ptr, size );
++}
++
++void sensors_yyfree (void * ptr )
++{
++ free( (char *) ptr ); /* see sensors_yyrealloc() for (char *) cast */
++}
++
++#define YYTABLES_NAME "yytables"
++
++#line 332 "lib/conf-lex.l"
++
++
++
++/*
++ Do the buffer handling manually. This allows us to scan as many
++ config files as we need to, while cleaning up properly after each
++ one. The "BEGIN(0)" line ensures that we start in the default state,
++ even if e.g. the previous config file was syntactically broken.
++
++ Returns 0 if successful, !0 otherwise.
++*/
++
++static YY_BUFFER_STATE scan_buf = (YY_BUFFER_STATE)0;
++
++int sensors_scanner_init(FILE *input, const char *filename)
++{
++ BEGIN(0);
++ if (!(scan_buf = sensors_yy_create_buffer(input, YY_BUF_SIZE)))
++ return -1;
++
++ sensors_yy_switch_to_buffer(scan_buf);
++ sensors_yyfilename = filename;
++ sensors_yylineno = 1;
++ return 0;
++}
++
++void sensors_scanner_exit(void)
++{
++ sensors_yy_delete_buffer(scan_buf);
++ scan_buf = (YY_BUFFER_STATE)0;
++
++/* As of flex 2.5.9, sensors_yylex_destroy() must be called when done with the
++ scaller, otherwise we'll leak memory. */
++#if defined(YY_FLEX_MAJOR_VERSION) && defined(YY_FLEX_MINOR_VERSION) && defined(YY_FLEX_SUBMINOR_VERSION)
++#if YY_FLEX_MAJOR_VERSION > 2 || \
++ (YY_FLEX_MAJOR_VERSION == 2 && (YY_FLEX_MINOR_VERSION > 5 || \
++ (YY_FLEX_MINOR_VERSION == 5 && YY_FLEX_SUBMINOR_VERSION >= 9)))
++ sensors_yylex_destroy();
++#endif
++#endif
++}
++
++
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-lex.l linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-lex.l
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-lex.l 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-lex.l 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,372 @@
++%{
++/*
++ conf-lex.l - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#include <stdlib.h>
++#include <string.h>
++
++#include "general.h"
++#include "data.h"
++#include "conf-parse.h"
++#include "error.h"
++#include "scanner.h"
++
++static int buffer_count;
++static int buffer_max;
++static char *buffer;
++
++char sensors_lex_error[100];
++
++const char *sensors_yyfilename;
++int sensors_yylineno;
++
++#define buffer_malloc() sensors_malloc_array(&buffer,&buffer_count,\
++ &buffer_max,1)
++#define buffer_free() sensors_free_array(&buffer,&buffer_count,\
++ &buffer_max)
++#define buffer_add_char(c) sensors_add_array_el(c,&buffer,\
++ &buffer_count,\
++ &buffer_max,1)
++#define buffer_add_string(s) sensors_add_array_els(s,strlen(s),\
++ &buffer, \
++ &buffer_count,&buffer_max,1)
++
++%}
++
++ /* Scanner for configuration files */
++
++%option nodefault
++%option noyywrap
++%option nounput
++
++ /* All states are exclusive */
++
++%x MIDDLE
++%x STRING
++%x ERR
++
++ /* Any whitespace-like character */
++
++BLANK [ \f\r\t\v]
++
++IDCHAR [[:alnum:]_]
++
++ /* Note: `10', `10.4' and `.4' are valid, `10.' is not */
++
++FLOAT [[:digit:]]*\.?[[:digit:]]+
++
++ /* Only positive whole numbers are recognized here */
++
++NUM 0|([1-9][[:digit:]]*)
++
++
++%%
++
++ /*
++ * STATE: INITIAL
++ */
++
++<INITIAL>{
++
++<<EOF>> { /* EOF from this state terminates */
++ return 0;
++ }
++
++{BLANK}+ ; /* eat as many blanks as possible at once */
++
++{BLANK}*\n { /* eat a bare newline (possibly preceded by blanks) */
++ sensors_yylineno++;
++ }
++
++ /* comments */
++
++#.* ; /* eat the rest of the line after comment char */
++
++#.*\n { /* eat the rest of the line after comment char */
++ sensors_yylineno++;
++ }
++
++ /*
++ * Keywords must be followed by whitespace - eat that too.
++ * If there isn't trailing whitespace, we still need to
++ * accept it as lexically correct (even though the parser
++ * will reject it anyway.)
++ */
++
++label{BLANK}* {
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return LABEL;
++ }
++
++set{BLANK}* {
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return SET;
++ }
++
++compute{BLANK}* {
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return COMPUTE;
++ }
++
++bus{BLANK}* {
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return BUS;
++ }
++
++chip{BLANK}* {
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return CHIP;
++ }
++
++ignore{BLANK}* {
++ sensors_yylval.line.filename = sensors_yyfilename;
++ sensors_yylval.line.lineno = sensors_yylineno;
++ BEGIN(MIDDLE);
++ return IGNORE;
++ }
++
++ /* Anything else at the beginning of a line is an error */
++
++[a-z]+ |
++. {
++ BEGIN(ERR);
++ strcpy(sensors_lex_error,"Invalid keyword");
++ return ERROR;
++ }
++}
++
++ /*
++ * STATE: ERROR
++ */
++
++<ERR>{
++
++.* ; /* eat whatever is left on this line */
++
++\n {
++ BEGIN(INITIAL);
++ sensors_yylineno++;
++ return EOL;
++ }
++}
++
++ /*
++ * STATE: MIDDLE
++ */
++
++<MIDDLE>{
++
++{BLANK}+ ; /* eat as many blanks as possible at once */
++
++\n { /* newline here sends EOL token to parser */
++ BEGIN(INITIAL);
++ sensors_yylineno++;
++ return EOL;
++ }
++
++<<EOF>> { /* EOF here sends EOL token to parser also */
++ BEGIN(INITIAL);
++ return EOL;
++ }
++
++\\{BLANK}*\n { /* eat an escaped newline with no state change */
++ sensors_yylineno++;
++ }
++
++ /* comments */
++
++#.* ; /* eat the rest of the line after comment char */
++
++#.*\n { /* eat the rest of the line after comment char */
++ BEGIN(INITIAL);
++ sensors_yylineno++;
++ return EOL;
++ }
++
++ /* A number */
++
++{FLOAT} {
++ sensors_yylval.value = atof(sensors_yytext);
++ return FLOAT;
++ }
++
++ /* Some operators */
++
++"+" return '+';
++"-" return '-';
++"*" return '*';
++"/" return '/';
++"(" return '(';
++")" return ')';
++"," return ',';
++"@" return '@';
++"^" return '^';
++"`" return '`';
++
++ /* Quoted string */
++
++\" {
++ buffer_malloc();
++ BEGIN(STRING);
++ }
++
++ /* A normal, unquoted identifier */
++
++{IDCHAR}+ {
++ sensors_yylval.name = strdup(sensors_yytext);
++ if (! sensors_yylval.name)
++ sensors_fatal_error("conf-lex.l",
++ "Allocating a new string");
++
++ return NAME;
++ }
++
++ /* anything else is bogus */
++
++. |
++[[:digit:]]*\. |
++\\{BLANK}* {
++ BEGIN(ERR);
++ return ERROR;
++ }
++}
++
++ /*
++ * STATE: STRING
++ */
++
++<STRING>{
++
++ /* Oops, newline or EOF while in a string is not good */
++
++\n |
++\\\n {
++ buffer_add_char("\0");
++ strcpy(sensors_lex_error,
++ "No matching double quote.");
++ buffer_free();
++ yyless(0);
++ BEGIN(ERR);
++ return ERROR;
++ }
++
++<<EOF>> {
++ strcpy(sensors_lex_error,
++ "Reached end-of-file without a matching double quote.");
++ buffer_free();
++ BEGIN(MIDDLE);
++ return ERROR;
++ }
++
++ /* At the end */
++
++\"\" {
++ buffer_add_char("\0");
++ strcpy(sensors_lex_error,
++ "Quoted strings must be separated by whitespace.");
++ buffer_free();
++ BEGIN(ERR);
++ return ERROR;
++ }
++
++\" {
++ buffer_add_char("\0");
++ sensors_yylval.name = strdup(buffer);
++ if (! sensors_yylval.name)
++ sensors_fatal_error("conf-lex.l",
++ "Allocating a new string");
++ buffer_free();
++ BEGIN(MIDDLE);
++ return NAME;
++ }
++
++\\a buffer_add_char("\a");
++\\b buffer_add_char("\b");
++\\f buffer_add_char("\f");
++\\n buffer_add_char("\n");
++\\r buffer_add_char("\r");
++\\t buffer_add_char("\t");
++\\v buffer_add_char("\v");
++
++ /* Other escapes: just copy the character behind the slash */
++
++\\. {
++ buffer_add_char(&sensors_yytext[1]);
++ }
++
++ /* Anything else (including a bare '\' which may be followed by EOF) */
++
++\\ |
++[^\\\n\"]+ {
++ buffer_add_string(sensors_yytext);
++ }
++}
++
++%%
++
++/*
++ Do the buffer handling manually. This allows us to scan as many
++ config files as we need to, while cleaning up properly after each
++ one. The "BEGIN(0)" line ensures that we start in the default state,
++ even if e.g. the previous config file was syntactically broken.
++
++ Returns 0 if successful, !0 otherwise.
++*/
++
++static YY_BUFFER_STATE scan_buf = (YY_BUFFER_STATE)0;
++
++int sensors_scanner_init(FILE *input, const char *filename)
++{
++ BEGIN(0);
++ if (!(scan_buf = sensors_yy_create_buffer(input, YY_BUF_SIZE)))
++ return -1;
++
++ sensors_yy_switch_to_buffer(scan_buf);
++ sensors_yyfilename = filename;
++ sensors_yylineno = 1;
++ return 0;
++}
++
++void sensors_scanner_exit(void)
++{
++ sensors_yy_delete_buffer(scan_buf);
++ scan_buf = (YY_BUFFER_STATE)0;
++
++/* As of flex 2.5.9, yylex_destroy() must be called when done with the
++ scaller, otherwise we'll leak memory. */
++#if defined(YY_FLEX_MAJOR_VERSION) && defined(YY_FLEX_MINOR_VERSION) && defined(YY_FLEX_SUBMINOR_VERSION)
++#if YY_FLEX_MAJOR_VERSION > 2 || \
++ (YY_FLEX_MAJOR_VERSION == 2 && (YY_FLEX_MINOR_VERSION > 5 || \
++ (YY_FLEX_MINOR_VERSION == 5 && YY_FLEX_SUBMINOR_VERSION >= 9)))
++ sensors_yylex_destroy();
++#endif
++#endif
++}
++
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-parse.c linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-parse.c
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-parse.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-parse.c 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,2042 @@
++/* A Bison parser, made by GNU Bison 2.5. */
++
++/* Bison implementation for Yacc-like parsers in C
++
++ Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc.
++
++ This program is free software: you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation, either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++/* As a special exception, you may create a larger work that contains
++ part or all of the Bison parser skeleton and distribute that work
++ under terms of your choice, so long as that work isn't itself a
++ parser generator using the skeleton or a modified version thereof
++ as a parser skeleton. Alternatively, if you modify or redistribute
++ the parser skeleton itself, you may (at your option) remove this
++ special exception, which will cause the skeleton and the resulting
++ Bison output files to be licensed under the GNU General Public
++ License without this special exception.
++
++ This special exception was added by the Free Software Foundation in
++ version 2.2 of Bison. */
++
++/* C LALR(1) parser skeleton written by Richard Stallman, by
++ simplifying the original so-called "semantic" parser. */
++
++/* All symbols defined below should begin with yy or YY, to avoid
++ infringing on user name space. This should be done even for local
++ variables, as they might otherwise be expanded by user macros.
++ There are some unavoidable exceptions within include files to
++ define necessary library symbols; they are noted "INFRINGES ON
++ USER NAME SPACE" below. */
++
++/* Identify Bison output. */
++#define YYBISON 1
++
++/* Bison version. */
++#define YYBISON_VERSION "2.5"
++
++/* Skeleton name. */
++#define YYSKELETON_NAME "yacc.c"
++
++/* Pure parsers. */
++#define YYPURE 0
++
++/* Push parsers. */
++#define YYPUSH 0
++
++/* Pull parsers. */
++#define YYPULL 1
++
++/* Using locations. */
++#define YYLSP_NEEDED 0
++
++/* Substitute the variable and function names. */
++#define yyparse sensors_yyparse
++#define yylex sensors_yylex
++#define yyerror sensors_yyerror
++#define yylval sensors_yylval
++#define yychar sensors_yychar
++#define yydebug sensors_yydebug
++#define yynerrs sensors_yynerrs
++
++
++/* Copy the first part of user declarations. */
++
++/* Line 268 of yacc.c */
++#line 1 "lib/conf-parse.y"
++
++/*
++ conf-parse.y - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#define YYERROR_VERBOSE
++
++#include <stdio.h>
++#include <string.h>
++#include <stdlib.h>
++
++#include "data.h"
++#include "general.h"
++#include "error.h"
++#include "conf.h"
++#include "access.h"
++#include "init.h"
++
++static void sensors_yyerror(const char *err);
++static sensors_expr *malloc_expr(void);
++
++static sensors_chip *current_chip = NULL;
++
++#define bus_add_el(el) sensors_add_array_el(el,\
++ &sensors_config_busses,\
++ &sensors_config_busses_count,\
++ &sensors_config_busses_max,\
++ sizeof(sensors_bus))
++#define label_add_el(el) sensors_add_array_el(el,\
++ &current_chip->labels,\
++ &current_chip->labels_count,\
++ &current_chip->labels_max,\
++ sizeof(sensors_label));
++#define set_add_el(el) sensors_add_array_el(el,\
++ &current_chip->sets,\
++ &current_chip->sets_count,\
++ &current_chip->sets_max,\
++ sizeof(sensors_set));
++#define compute_add_el(el) sensors_add_array_el(el,\
++ &current_chip->computes,\
++ &current_chip->computes_count,\
++ &current_chip->computes_max,\
++ sizeof(sensors_compute));
++#define ignore_add_el(el) sensors_add_array_el(el,\
++ &current_chip->ignores,\
++ &current_chip->ignores_count,\
++ &current_chip->ignores_max,\
++ sizeof(sensors_ignore));
++#define chip_add_el(el) sensors_add_array_el(el,\
++ &sensors_config_chips,\
++ &sensors_config_chips_count,\
++ &sensors_config_chips_max,\
++ sizeof(sensors_chip));
++
++#define fits_add_el(el,list) sensors_add_array_el(el,\
++ &(list).fits,\
++ &(list).fits_count,\
++ &(list).fits_max, \
++ sizeof(sensors_chip_name));
++
++
++
++/* Line 268 of yacc.c */
++#line 158 "lib/conf-parse.c"
++
++/* Enabling traces. */
++#ifndef YYDEBUG
++# define YYDEBUG 0
++#endif
++
++/* Enabling verbose error messages. */
++#ifdef YYERROR_VERBOSE
++# undef YYERROR_VERBOSE
++# define YYERROR_VERBOSE 1
++#else
++# define YYERROR_VERBOSE 0
++#endif
++
++/* Enabling the token table. */
++#ifndef YYTOKEN_TABLE
++# define YYTOKEN_TABLE 0
++#endif
++
++
++/* Tokens. */
++#ifndef YYTOKENTYPE
++# define YYTOKENTYPE
++ /* Put the tokens into the symbol table, so that GDB and other debuggers
++ know about them. */
++ enum yytokentype {
++ NEG = 258,
++ EOL = 259,
++ BUS = 260,
++ LABEL = 261,
++ SET = 262,
++ CHIP = 263,
++ COMPUTE = 264,
++ IGNORE = 265,
++ FLOAT = 266,
++ NAME = 267,
++ ERROR = 268
++ };
++#endif
++
++
++
++#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
++typedef union YYSTYPE
++{
++
++/* Line 293 of yacc.c */
++#line 79 "lib/conf-parse.y"
++
++ double value;
++ char *name;
++ void *nothing;
++ sensors_chip_name_list chips;
++ sensors_expr *expr;
++ sensors_bus_id bus;
++ sensors_chip_name chip;
++ sensors_config_line line;
++
++
++
++/* Line 293 of yacc.c */
++#line 220 "lib/conf-parse.c"
++} YYSTYPE;
++# define YYSTYPE_IS_TRIVIAL 1
++# define yystype YYSTYPE /* obsolescent; will be withdrawn */
++# define YYSTYPE_IS_DECLARED 1
++#endif
++
++
++/* Copy the second part of user declarations. */
++
++
++/* Line 343 of yacc.c */
++#line 232 "lib/conf-parse.c"
++
++#ifdef short
++# undef short
++#endif
++
++#ifdef YYTYPE_UINT8
++typedef YYTYPE_UINT8 yytype_uint8;
++#else
++typedef unsigned char yytype_uint8;
++#endif
++
++#ifdef YYTYPE_INT8
++typedef YYTYPE_INT8 yytype_int8;
++#elif (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++typedef signed char yytype_int8;
++#else
++typedef short int yytype_int8;
++#endif
++
++#ifdef YYTYPE_UINT16
++typedef YYTYPE_UINT16 yytype_uint16;
++#else
++typedef unsigned short int yytype_uint16;
++#endif
++
++#ifdef YYTYPE_INT16
++typedef YYTYPE_INT16 yytype_int16;
++#else
++typedef short int yytype_int16;
++#endif
++
++#ifndef YYSIZE_T
++# ifdef __SIZE_TYPE__
++# define YYSIZE_T __SIZE_TYPE__
++# elif defined size_t
++# define YYSIZE_T size_t
++# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
++# define YYSIZE_T size_t
++# else
++# define YYSIZE_T unsigned int
++# endif
++#endif
++
++#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
++
++#ifndef YY_
++# if defined YYENABLE_NLS && YYENABLE_NLS
++# if ENABLE_NLS
++# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
++# define YY_(msgid) dgettext ("bison-runtime", msgid)
++# endif
++# endif
++# ifndef YY_
++# define YY_(msgid) msgid
++# endif
++#endif
++
++/* Suppress unused-variable warnings by "using" E. */
++#if ! defined lint || defined __GNUC__
++# define YYUSE(e) ((void) (e))
++#else
++# define YYUSE(e) /* empty */
++#endif
++
++/* Identity function, used to suppress warnings about constant conditions. */
++#ifndef lint
++# define YYID(n) (n)
++#else
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++static int
++YYID (int yyi)
++#else
++static int
++YYID (yyi)
++ int yyi;
++#endif
++{
++ return yyi;
++}
++#endif
++
++#if ! defined yyoverflow || YYERROR_VERBOSE
++
++/* The parser invokes alloca or malloc; define the necessary symbols. */
++
++# ifdef YYSTACK_USE_ALLOCA
++# if YYSTACK_USE_ALLOCA
++# ifdef __GNUC__
++# define YYSTACK_ALLOC __builtin_alloca
++# elif defined __BUILTIN_VA_ARG_INCR
++# include <alloca.h> /* INFRINGES ON USER NAME SPACE */
++# elif defined _AIX
++# define YYSTACK_ALLOC __alloca
++# elif defined _MSC_VER
++# include <malloc.h> /* INFRINGES ON USER NAME SPACE */
++# define alloca _alloca
++# else
++# define YYSTACK_ALLOC alloca
++# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
++# ifndef EXIT_SUCCESS
++# define EXIT_SUCCESS 0
++# endif
++# endif
++# endif
++# endif
++# endif
++
++# ifdef YYSTACK_ALLOC
++ /* Pacify GCC's `empty if-body' warning. */
++# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0))
++# ifndef YYSTACK_ALLOC_MAXIMUM
++ /* The OS might guarantee only one guard page at the bottom of the stack,
++ and a page size can be as small as 4096 bytes. So we cannot safely
++ invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
++ to allow for a few compiler-allocated temporary stack slots. */
++# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
++# endif
++# else
++# define YYSTACK_ALLOC YYMALLOC
++# define YYSTACK_FREE YYFREE
++# ifndef YYSTACK_ALLOC_MAXIMUM
++# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
++# endif
++# if (defined __cplusplus && ! defined EXIT_SUCCESS \
++ && ! ((defined YYMALLOC || defined malloc) \
++ && (defined YYFREE || defined free)))
++# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
++# ifndef EXIT_SUCCESS
++# define EXIT_SUCCESS 0
++# endif
++# endif
++# ifndef YYMALLOC
++# define YYMALLOC malloc
++# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
++# endif
++# endif
++# ifndef YYFREE
++# define YYFREE free
++# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++void free (void *); /* INFRINGES ON USER NAME SPACE */
++# endif
++# endif
++# endif
++#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
++
++
++#if (! defined yyoverflow \
++ && (! defined __cplusplus \
++ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
++
++/* A type that is properly aligned for any stack member. */
++union yyalloc
++{
++ yytype_int16 yyss_alloc;
++ YYSTYPE yyvs_alloc;
++};
++
++/* The size of the maximum gap between one aligned stack and the next. */
++# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
++
++/* The size of an array large to enough to hold all stacks, each with
++ N elements. */
++# define YYSTACK_BYTES(N) \
++ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
++ + YYSTACK_GAP_MAXIMUM)
++
++# define YYCOPY_NEEDED 1
++
++/* Relocate STACK from its old location to the new one. The
++ local variables YYSIZE and YYSTACKSIZE give the old and new number of
++ elements in the stack, and YYPTR gives the new location of the
++ stack. Advance YYPTR to a properly aligned location for the next
++ stack. */
++# define YYSTACK_RELOCATE(Stack_alloc, Stack) \
++ do \
++ { \
++ YYSIZE_T yynewbytes; \
++ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \
++ Stack = &yyptr->Stack_alloc; \
++ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
++ yyptr += yynewbytes / sizeof (*yyptr); \
++ } \
++ while (YYID (0))
++
++#endif
++
++#if defined YYCOPY_NEEDED && YYCOPY_NEEDED
++/* Copy COUNT objects from FROM to TO. The source and destination do
++ not overlap. */
++# ifndef YYCOPY
++# if defined __GNUC__ && 1 < __GNUC__
++# define YYCOPY(To, From, Count) \
++ __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
++# else
++# define YYCOPY(To, From, Count) \
++ do \
++ { \
++ YYSIZE_T yyi; \
++ for (yyi = 0; yyi < (Count); yyi++) \
++ (To)[yyi] = (From)[yyi]; \
++ } \
++ while (YYID (0))
++# endif
++# endif
++#endif /* !YYCOPY_NEEDED */
++
++/* YYFINAL -- State number of the termination state. */
++#define YYFINAL 2
++/* YYLAST -- Last index in YYTABLE. */
++#define YYLAST 58
++
++/* YYNTOKENS -- Number of terminals. */
++#define YYNTOKENS 24
++/* YYNNTS -- Number of nonterminals. */
++#define YYNNTS 16
++/* YYNRULES -- Number of rules. */
++#define YYNRULES 34
++/* YYNRULES -- Number of states. */
++#define YYNSTATES 63
++
++/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */
++#define YYUNDEFTOK 2
++#define YYMAXUTOK 268
++
++#define YYTRANSLATE(YYX) \
++ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
++
++/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */
++static const yytype_uint8 yytranslate[] =
++{
++ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 22, 23, 5, 4, 10, 3, 2, 6, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 21, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 8, 2, 9, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
++ 2, 2, 2, 2, 2, 2, 1, 2, 7, 11,
++ 12, 13, 14, 15, 16, 17, 18, 19, 20
++};
++
++#if YYDEBUG
++/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
++ YYRHS. */
++static const yytype_uint8 yyprhs[] =
++{
++ 0, 0, 3, 4, 7, 10, 13, 16, 19, 22,
++ 25, 28, 32, 36, 40, 46, 49, 52, 54, 57,
++ 59, 61, 63, 67, 71, 75, 79, 82, 86, 89,
++ 92, 94, 96, 98, 100
++};
++
++/* YYRHS -- A `-1'-separated list of the rules' RHS. */
++static const yytype_int8 yyrhs[] =
++{
++ 25, 0, -1, -1, 25, 26, -1, 27, 11, -1,
++ 28, 11, -1, 29, 11, -1, 32, 11, -1, 30,
++ 11, -1, 31, 11, -1, 1, 11, -1, 12, 35,
++ 36, -1, 13, 37, 38, -1, 14, 37, 34, -1,
++ 16, 37, 34, 10, 34, -1, 17, 37, -1, 15,
++ 33, -1, 39, -1, 33, 39, -1, 18, -1, 19,
++ -1, 21, -1, 34, 4, 34, -1, 34, 3, 34,
++ -1, 34, 5, 34, -1, 34, 6, 34, -1, 3,
++ 34, -1, 22, 34, 23, -1, 8, 34, -1, 9,
++ 34, -1, 19, -1, 19, -1, 19, -1, 19, -1,
++ 19, -1
++};
++
++/* YYRLINE[YYN] -- source line where rule number YYN was defined. */
++static const yytype_uint16 yyrline[] =
++{
++ 0, 119, 119, 120, 123, 124, 125, 126, 127, 128,
++ 129, 132, 141, 156, 171, 188, 201, 219, 225, 231,
++ 236, 241, 245, 252, 259, 266, 273, 280, 282, 289,
++ 298, 308, 312, 316, 320
++};
++#endif
++
++#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
++/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
++ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
++static const char *const yytname[] =
++{
++ "$end", "error", "$undefined", "'-'", "'+'", "'*'", "'/'", "NEG", "'^'",
++ "'`'", "','", "EOL", "BUS", "LABEL", "SET", "CHIP", "COMPUTE", "IGNORE",
++ "FLOAT", "NAME", "ERROR", "'@'", "'('", "')'", "$accept", "input",
++ "line", "bus_statement", "label_statement", "set_statement",
++ "compute_statement", "ignore_statement", "chip_statement",
++ "chip_name_list", "expression", "bus_id", "adapter_name",
++ "function_name", "string", "chip_name", 0
++};
++#endif
++
++# ifdef YYPRINT
++/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
++ token YYLEX-NUM. */
++static const yytype_uint16 yytoknum[] =
++{
++ 0, 256, 257, 45, 43, 42, 47, 258, 94, 96,
++ 44, 259, 260, 261, 262, 263, 264, 265, 266, 267,
++ 268, 64, 40, 41
++};
++# endif
++
++/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
++static const yytype_uint8 yyr1[] =
++{
++ 0, 24, 25, 25, 26, 26, 26, 26, 26, 26,
++ 26, 27, 28, 29, 30, 31, 32, 33, 33, 34,
++ 34, 34, 34, 34, 34, 34, 34, 34, 34, 34,
++ 35, 36, 37, 38, 39
++};
++
++/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */
++static const yytype_uint8 yyr2[] =
++{
++ 0, 2, 0, 2, 2, 2, 2, 2, 2, 2,
++ 2, 3, 3, 3, 5, 2, 2, 1, 2, 1,
++ 1, 1, 3, 3, 3, 3, 2, 3, 2, 2,
++ 1, 1, 1, 1, 1
++};
++
++/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM.
++ Performed when YYTABLE doesn't specify something else to do. Zero
++ means the default is an error. */
++static const yytype_uint8 yydefact[] =
++{
++ 2, 0, 1, 0, 0, 0, 0, 0, 0, 0,
++ 3, 0, 0, 0, 0, 0, 0, 10, 30, 0,
++ 32, 0, 0, 34, 16, 17, 0, 15, 4, 5,
++ 6, 8, 9, 7, 31, 11, 33, 12, 0, 0,
++ 0, 19, 20, 21, 0, 13, 18, 0, 26, 28,
++ 29, 0, 0, 0, 0, 0, 0, 27, 23, 22,
++ 24, 25, 14
++};
++
++/* YYDEFGOTO[NTERM-NUM]. */
++static const yytype_int8 yydefgoto[] =
++{
++ -1, 1, 10, 11, 12, 13, 14, 15, 16, 24,
++ 45, 19, 35, 21, 37, 25
++};
++
++/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
++ STATE-NUM. */
++#define YYPACT_NINF -27
++static const yytype_int8 yypact[] =
++{
++ -27, 37, -27, -4, -3, 1, 1, 6, 1, 1,
++ -27, 8, 13, 20, 23, 32, 34, -27, -27, 29,
++ -27, 39, 14, -27, 6, -27, 14, -27, -27, -27,
++ -27, -27, -27, -27, -27, -27, -27, -27, 14, 14,
++ 14, -27, -27, -27, 14, 36, -27, 5, -27, -27,
++ -27, -2, 14, 14, 14, 14, 14, -27, 0, 0,
++ -27, -27, 36
++};
++
++/* YYPGOTO[NTERM-NUM]. */
++static const yytype_int8 yypgoto[] =
++{
++ -27, -27, -27, -27, -27, -27, -27, -27, -27, -27,
++ -26, -27, -27, 38, -27, 31
++};
++
++/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If
++ positive, shift that token. If negative, reduce the rule which
++ number is the opposite. If YYTABLE_NINF, syntax error. */
++#define YYTABLE_NINF -1
++static const yytype_uint8 yytable[] =
++{
++ 47, 52, 53, 54, 55, 54, 55, 17, 52, 53,
++ 54, 55, 48, 49, 50, 56, 18, 38, 51, 28,
++ 20, 57, 39, 40, 29, 23, 58, 59, 60, 61,
++ 62, 30, 41, 42, 31, 43, 44, 2, 3, 52,
++ 53, 54, 55, 32, 22, 33, 26, 27, 34, 4,
++ 5, 6, 7, 8, 9, 46, 0, 0, 36
++};
++
++#define yypact_value_is_default(yystate) \
++ ((yystate) == (-27))
++
++#define yytable_value_is_error(yytable_value) \
++ YYID (0)
++
++static const yytype_int8 yycheck[] =
++{
++ 26, 3, 4, 5, 6, 5, 6, 11, 3, 4,
++ 5, 6, 38, 39, 40, 10, 19, 3, 44, 11,
++ 19, 23, 8, 9, 11, 19, 52, 53, 54, 55,
++ 56, 11, 18, 19, 11, 21, 22, 0, 1, 3,
++ 4, 5, 6, 11, 6, 11, 8, 9, 19, 12,
++ 13, 14, 15, 16, 17, 24, -1, -1, 19
++};
++
++/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
++ symbol of state STATE-NUM. */
++static const yytype_uint8 yystos[] =
++{
++ 0, 25, 0, 1, 12, 13, 14, 15, 16, 17,
++ 26, 27, 28, 29, 30, 31, 32, 11, 19, 35,
++ 19, 37, 37, 19, 33, 39, 37, 37, 11, 11,
++ 11, 11, 11, 11, 19, 36, 19, 38, 3, 8,
++ 9, 18, 19, 21, 22, 34, 39, 34, 34, 34,
++ 34, 34, 3, 4, 5, 6, 10, 23, 34, 34,
++ 34, 34, 34
++};
++
++#define yyerrok (yyerrstatus = 0)
++#define yyclearin (yychar = YYEMPTY)
++#define YYEMPTY (-2)
++#define YYEOF 0
++
++#define YYACCEPT goto yyacceptlab
++#define YYABORT goto yyabortlab
++#define YYERROR goto yyerrorlab
++
++
++/* Like YYERROR except do call yyerror. This remains here temporarily
++ to ease the transition to the new meaning of YYERROR, for GCC.
++ Once GCC version 2 has supplanted version 1, this can go. However,
++ YYFAIL appears to be in use. Nevertheless, it is formally deprecated
++ in Bison 2.4.2's NEWS entry, where a plan to phase it out is
++ discussed. */
++
++#define YYFAIL goto yyerrlab
++#if defined YYFAIL
++ /* This is here to suppress warnings from the GCC cpp's
++ -Wunused-macros. Normally we don't worry about that warning, but
++ some users do, and we want to make it easy for users to remove
++ YYFAIL uses, which will produce warnings from Bison 2.5. */
++#endif
++
++#define YYRECOVERING() (!!yyerrstatus)
++
++#define YYBACKUP(Token, Value) \
++do \
++ if (yychar == YYEMPTY && yylen == 1) \
++ { \
++ yychar = (Token); \
++ yylval = (Value); \
++ YYPOPSTACK (1); \
++ goto yybackup; \
++ } \
++ else \
++ { \
++ yyerror (YY_("syntax error: cannot back up")); \
++ YYERROR; \
++ } \
++while (YYID (0))
++
++
++#define YYTERROR 1
++#define YYERRCODE 256
++
++
++/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
++ If N is 0, then set CURRENT to the empty location which ends
++ the previous symbol: RHS[0] (always defined). */
++
++#define YYRHSLOC(Rhs, K) ((Rhs)[K])
++#ifndef YYLLOC_DEFAULT
++# define YYLLOC_DEFAULT(Current, Rhs, N) \
++ do \
++ if (YYID (N)) \
++ { \
++ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \
++ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \
++ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \
++ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \
++ } \
++ else \
++ { \
++ (Current).first_line = (Current).last_line = \
++ YYRHSLOC (Rhs, 0).last_line; \
++ (Current).first_column = (Current).last_column = \
++ YYRHSLOC (Rhs, 0).last_column; \
++ } \
++ while (YYID (0))
++#endif
++
++
++/* This macro is provided for backward compatibility. */
++
++#ifndef YY_LOCATION_PRINT
++# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
++#endif
++
++
++/* YYLEX -- calling `yylex' with the right arguments. */
++
++#ifdef YYLEX_PARAM
++# define YYLEX yylex (YYLEX_PARAM)
++#else
++# define YYLEX yylex ()
++#endif
++
++/* Enable debugging if requested. */
++#if YYDEBUG
++
++# ifndef YYFPRINTF
++# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
++# define YYFPRINTF fprintf
++# endif
++
++# define YYDPRINTF(Args) \
++do { \
++ if (yydebug) \
++ YYFPRINTF Args; \
++} while (YYID (0))
++
++# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
++do { \
++ if (yydebug) \
++ { \
++ YYFPRINTF (stderr, "%s ", Title); \
++ yy_symbol_print (stderr, \
++ Type, Value); \
++ YYFPRINTF (stderr, "\n"); \
++ } \
++} while (YYID (0))
++
++
++/*--------------------------------.
++| Print this symbol on YYOUTPUT. |
++`--------------------------------*/
++
++/*ARGSUSED*/
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++static void
++yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
++#else
++static void
++yy_symbol_value_print (yyoutput, yytype, yyvaluep)
++ FILE *yyoutput;
++ int yytype;
++ YYSTYPE const * const yyvaluep;
++#endif
++{
++ if (!yyvaluep)
++ return;
++# ifdef YYPRINT
++ if (yytype < YYNTOKENS)
++ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
++# else
++ YYUSE (yyoutput);
++# endif
++ switch (yytype)
++ {
++ default:
++ break;
++ }
++}
++
++
++/*--------------------------------.
++| Print this symbol on YYOUTPUT. |
++`--------------------------------*/
++
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++static void
++yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
++#else
++static void
++yy_symbol_print (yyoutput, yytype, yyvaluep)
++ FILE *yyoutput;
++ int yytype;
++ YYSTYPE const * const yyvaluep;
++#endif
++{
++ if (yytype < YYNTOKENS)
++ YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
++ else
++ YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
++
++ yy_symbol_value_print (yyoutput, yytype, yyvaluep);
++ YYFPRINTF (yyoutput, ")");
++}
++
++/*------------------------------------------------------------------.
++| yy_stack_print -- Print the state stack from its BOTTOM up to its |
++| TOP (included). |
++`------------------------------------------------------------------*/
++
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++static void
++yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop)
++#else
++static void
++yy_stack_print (yybottom, yytop)
++ yytype_int16 *yybottom;
++ yytype_int16 *yytop;
++#endif
++{
++ YYFPRINTF (stderr, "Stack now");
++ for (; yybottom <= yytop; yybottom++)
++ {
++ int yybot = *yybottom;
++ YYFPRINTF (stderr, " %d", yybot);
++ }
++ YYFPRINTF (stderr, "\n");
++}
++
++# define YY_STACK_PRINT(Bottom, Top) \
++do { \
++ if (yydebug) \
++ yy_stack_print ((Bottom), (Top)); \
++} while (YYID (0))
++
++
++/*------------------------------------------------.
++| Report that the YYRULE is going to be reduced. |
++`------------------------------------------------*/
++
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++static void
++yy_reduce_print (YYSTYPE *yyvsp, int yyrule)
++#else
++static void
++yy_reduce_print (yyvsp, yyrule)
++ YYSTYPE *yyvsp;
++ int yyrule;
++#endif
++{
++ int yynrhs = yyr2[yyrule];
++ int yyi;
++ unsigned long int yylno = yyrline[yyrule];
++ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
++ yyrule - 1, yylno);
++ /* The symbols being reduced. */
++ for (yyi = 0; yyi < yynrhs; yyi++)
++ {
++ YYFPRINTF (stderr, " $%d = ", yyi + 1);
++ yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi],
++ &(yyvsp[(yyi + 1) - (yynrhs)])
++ );
++ YYFPRINTF (stderr, "\n");
++ }
++}
++
++# define YY_REDUCE_PRINT(Rule) \
++do { \
++ if (yydebug) \
++ yy_reduce_print (yyvsp, Rule); \
++} while (YYID (0))
++
++/* Nonzero means print parse trace. It is left uninitialized so that
++ multiple parsers can coexist. */
++int yydebug;
++#else /* !YYDEBUG */
++# define YYDPRINTF(Args)
++# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
++# define YY_STACK_PRINT(Bottom, Top)
++# define YY_REDUCE_PRINT(Rule)
++#endif /* !YYDEBUG */
++
++
++/* YYINITDEPTH -- initial size of the parser's stacks. */
++#ifndef YYINITDEPTH
++# define YYINITDEPTH 200
++#endif
++
++/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
++ if the built-in stack extension method is used).
++
++ Do not make this value too large; the results are undefined if
++ YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
++ evaluated with infinite-precision integer arithmetic. */
++
++#ifndef YYMAXDEPTH
++# define YYMAXDEPTH 10000
++#endif
++
++
++#if YYERROR_VERBOSE
++
++# ifndef yystrlen
++# if defined __GLIBC__ && defined _STRING_H
++# define yystrlen strlen
++# else
++/* Return the length of YYSTR. */
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++static YYSIZE_T
++yystrlen (const char *yystr)
++#else
++static YYSIZE_T
++yystrlen (yystr)
++ const char *yystr;
++#endif
++{
++ YYSIZE_T yylen;
++ for (yylen = 0; yystr[yylen]; yylen++)
++ continue;
++ return yylen;
++}
++# endif
++# endif
++
++# ifndef yystpcpy
++# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
++# define yystpcpy stpcpy
++# else
++/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
++ YYDEST. */
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++static char *
++yystpcpy (char *yydest, const char *yysrc)
++#else
++static char *
++yystpcpy (yydest, yysrc)
++ char *yydest;
++ const char *yysrc;
++#endif
++{
++ char *yyd = yydest;
++ const char *yys = yysrc;
++
++ while ((*yyd++ = *yys++) != '\0')
++ continue;
++
++ return yyd - 1;
++}
++# endif
++# endif
++
++# ifndef yytnamerr
++/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
++ quotes and backslashes, so that it's suitable for yyerror. The
++ heuristic is that double-quoting is unnecessary unless the string
++ contains an apostrophe, a comma, or backslash (other than
++ backslash-backslash). YYSTR is taken from yytname. If YYRES is
++ null, do not copy; instead, return the length of what the result
++ would have been. */
++static YYSIZE_T
++yytnamerr (char *yyres, const char *yystr)
++{
++ if (*yystr == '"')
++ {
++ YYSIZE_T yyn = 0;
++ char const *yyp = yystr;
++
++ for (;;)
++ switch (*++yyp)
++ {
++ case '\'':
++ case ',':
++ goto do_not_strip_quotes;
++
++ case '\\':
++ if (*++yyp != '\\')
++ goto do_not_strip_quotes;
++ /* Fall through. */
++ default:
++ if (yyres)
++ yyres[yyn] = *yyp;
++ yyn++;
++ break;
++
++ case '"':
++ if (yyres)
++ yyres[yyn] = '\0';
++ return yyn;
++ }
++ do_not_strip_quotes: ;
++ }
++
++ if (! yyres)
++ return yystrlen (yystr);
++
++ return yystpcpy (yyres, yystr) - yyres;
++}
++# endif
++
++/* Copy into *YYMSG, which is of size *YYMSG_ALLOC, an error message
++ about the unexpected token YYTOKEN for the state stack whose top is
++ YYSSP.
++
++ Return 0 if *YYMSG was successfully written. Return 1 if *YYMSG is
++ not large enough to hold the message. In that case, also set
++ *YYMSG_ALLOC to the required number of bytes. Return 2 if the
++ required number of bytes is too large to store. */
++static int
++yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg,
++ yytype_int16 *yyssp, int yytoken)
++{
++ YYSIZE_T yysize0 = yytnamerr (0, yytname[yytoken]);
++ YYSIZE_T yysize = yysize0;
++ YYSIZE_T yysize1;
++ enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
++ /* Internationalized format string. */
++ const char *yyformat = 0;
++ /* Arguments of yyformat. */
++ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
++ /* Number of reported tokens (one for the "unexpected", one per
++ "expected"). */
++ int yycount = 0;
++
++ /* There are many possibilities here to consider:
++ - Assume YYFAIL is not used. It's too flawed to consider. See
++ <http://lists.gnu.org/archive/html/bison-patches/2009-12/msg00024.html>
++ for details. YYERROR is fine as it does not invoke this
++ function.
++ - If this state is a consistent state with a default action, then
++ the only way this function was invoked is if the default action
++ is an error action. In that case, don't check for expected
++ tokens because there are none.
++ - The only way there can be no lookahead present (in yychar) is if
++ this state is a consistent state with a default action. Thus,
++ detecting the absence of a lookahead is sufficient to determine
++ that there is no unexpected or expected token to report. In that
++ case, just report a simple "syntax error".
++ - Don't assume there isn't a lookahead just because this state is a
++ consistent state with a default action. There might have been a
++ previous inconsistent state, consistent state with a non-default
++ action, or user semantic action that manipulated yychar.
++ - Of course, the expected token list depends on states to have
++ correct lookahead information, and it depends on the parser not
++ to perform extra reductions after fetching a lookahead from the
++ scanner and before detecting a syntax error. Thus, state merging
++ (from LALR or IELR) and default reductions corrupt the expected
++ token list. However, the list is correct for canonical LR with
++ one exception: it will still contain any token that will not be
++ accepted due to an error action in a later state.
++ */
++ if (yytoken != YYEMPTY)
++ {
++ int yyn = yypact[*yyssp];
++ yyarg[yycount++] = yytname[yytoken];
++ if (!yypact_value_is_default (yyn))
++ {
++ /* Start YYX at -YYN if negative to avoid negative indexes in
++ YYCHECK. In other words, skip the first -YYN actions for
++ this state because they are default actions. */
++ int yyxbegin = yyn < 0 ? -yyn : 0;
++ /* Stay within bounds of both yycheck and yytname. */
++ int yychecklim = YYLAST - yyn + 1;
++ int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
++ int yyx;
++
++ for (yyx = yyxbegin; yyx < yyxend; ++yyx)
++ if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR
++ && !yytable_value_is_error (yytable[yyx + yyn]))
++ {
++ if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
++ {
++ yycount = 1;
++ yysize = yysize0;
++ break;
++ }
++ yyarg[yycount++] = yytname[yyx];
++ yysize1 = yysize + yytnamerr (0, yytname[yyx]);
++ if (! (yysize <= yysize1
++ && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
++ return 2;
++ yysize = yysize1;
++ }
++ }
++ }
++
++ switch (yycount)
++ {
++# define YYCASE_(N, S) \
++ case N: \
++ yyformat = S; \
++ break
++ YYCASE_(0, YY_("syntax error"));
++ YYCASE_(1, YY_("syntax error, unexpected %s"));
++ YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s"));
++ YYCASE_(3, YY_("syntax error, unexpected %s, expecting %s or %s"));
++ YYCASE_(4, YY_("syntax error, unexpected %s, expecting %s or %s or %s"));
++ YYCASE_(5, YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"));
++# undef YYCASE_
++ }
++
++ yysize1 = yysize + yystrlen (yyformat);
++ if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM))
++ return 2;
++ yysize = yysize1;
++
++ if (*yymsg_alloc < yysize)
++ {
++ *yymsg_alloc = 2 * yysize;
++ if (! (yysize <= *yymsg_alloc
++ && *yymsg_alloc <= YYSTACK_ALLOC_MAXIMUM))
++ *yymsg_alloc = YYSTACK_ALLOC_MAXIMUM;
++ return 1;
++ }
++
++ /* Avoid sprintf, as that infringes on the user's name space.
++ Don't have undefined behavior even if the translation
++ produced a string with the wrong number of "%s"s. */
++ {
++ char *yyp = *yymsg;
++ int yyi = 0;
++ while ((*yyp = *yyformat) != '\0')
++ if (*yyp == '%' && yyformat[1] == 's' && yyi < yycount)
++ {
++ yyp += yytnamerr (yyp, yyarg[yyi++]);
++ yyformat += 2;
++ }
++ else
++ {
++ yyp++;
++ yyformat++;
++ }
++ }
++ return 0;
++}
++#endif /* YYERROR_VERBOSE */
++
++/*-----------------------------------------------.
++| Release the memory associated to this symbol. |
++`-----------------------------------------------*/
++
++/*ARGSUSED*/
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++static void
++yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
++#else
++static void
++yydestruct (yymsg, yytype, yyvaluep)
++ const char *yymsg;
++ int yytype;
++ YYSTYPE *yyvaluep;
++#endif
++{
++ YYUSE (yyvaluep);
++
++ if (!yymsg)
++ yymsg = "Deleting";
++ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
++
++ switch (yytype)
++ {
++
++ default:
++ break;
++ }
++}
++
++
++/* Prevent warnings from -Wmissing-prototypes. */
++#ifdef YYPARSE_PARAM
++#if defined __STDC__ || defined __cplusplus
++int yyparse (void *YYPARSE_PARAM);
++#else
++int yyparse ();
++#endif
++#else /* ! YYPARSE_PARAM */
++#if defined __STDC__ || defined __cplusplus
++int yyparse (void);
++#else
++int yyparse ();
++#endif
++#endif /* ! YYPARSE_PARAM */
++
++
++/* The lookahead symbol. */
++int yychar;
++
++/* The semantic value of the lookahead symbol. */
++YYSTYPE yylval;
++
++/* Number of syntax errors so far. */
++int yynerrs;
++
++
++/*----------.
++| yyparse. |
++`----------*/
++
++#ifdef YYPARSE_PARAM
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++int
++yyparse (void *YYPARSE_PARAM)
++#else
++int
++yyparse (YYPARSE_PARAM)
++ void *YYPARSE_PARAM;
++#endif
++#else /* ! YYPARSE_PARAM */
++#if (defined __STDC__ || defined __C99__FUNC__ \
++ || defined __cplusplus || defined _MSC_VER)
++int
++yyparse (void)
++#else
++int
++yyparse ()
++
++#endif
++#endif
++{
++ int yystate;
++ /* Number of tokens to shift before error messages enabled. */
++ int yyerrstatus;
++
++ /* The stacks and their tools:
++ `yyss': related to states.
++ `yyvs': related to semantic values.
++
++ Refer to the stacks thru separate pointers, to allow yyoverflow
++ to reallocate them elsewhere. */
++
++ /* The state stack. */
++ yytype_int16 yyssa[YYINITDEPTH];
++ yytype_int16 *yyss;
++ yytype_int16 *yyssp;
++
++ /* The semantic value stack. */
++ YYSTYPE yyvsa[YYINITDEPTH];
++ YYSTYPE *yyvs;
++ YYSTYPE *yyvsp;
++
++ YYSIZE_T yystacksize;
++
++ int yyn;
++ int yyresult;
++ /* Lookahead token as an internal (translated) token number. */
++ int yytoken;
++ /* The variables used to return semantic value and location from the
++ action routines. */
++ YYSTYPE yyval;
++
++#if YYERROR_VERBOSE
++ /* Buffer for error messages, and its allocated size. */
++ char yymsgbuf[128];
++ char *yymsg = yymsgbuf;
++ YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
++#endif
++
++#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
++
++ /* The number of symbols on the RHS of the reduced rule.
++ Keep to zero when no symbol should be popped. */
++ int yylen = 0;
++
++ yytoken = 0;
++ yyss = yyssa;
++ yyvs = yyvsa;
++ yystacksize = YYINITDEPTH;
++
++ YYDPRINTF ((stderr, "Starting parse\n"));
++
++ yystate = 0;
++ yyerrstatus = 0;
++ yynerrs = 0;
++ yychar = YYEMPTY; /* Cause a token to be read. */
++
++ /* Initialize stack pointers.
++ Waste one element of value and location stack
++ so that they stay on the same level as the state stack.
++ The wasted elements are never initialized. */
++ yyssp = yyss;
++ yyvsp = yyvs;
++
++ goto yysetstate;
++
++/*------------------------------------------------------------.
++| yynewstate -- Push a new state, which is found in yystate. |
++`------------------------------------------------------------*/
++ yynewstate:
++ /* In all cases, when you get here, the value and location stacks
++ have just been pushed. So pushing a state here evens the stacks. */
++ yyssp++;
++
++ yysetstate:
++ *yyssp = yystate;
++
++ if (yyss + yystacksize - 1 <= yyssp)
++ {
++ /* Get the current used size of the three stacks, in elements. */
++ YYSIZE_T yysize = yyssp - yyss + 1;
++
++#ifdef yyoverflow
++ {
++ /* Give user a chance to reallocate the stack. Use copies of
++ these so that the &'s don't force the real ones into
++ memory. */
++ YYSTYPE *yyvs1 = yyvs;
++ yytype_int16 *yyss1 = yyss;
++
++ /* Each stack pointer address is followed by the size of the
++ data in use in that stack, in bytes. This used to be a
++ conditional around just the two extra args, but that might
++ be undefined if yyoverflow is a macro. */
++ yyoverflow (YY_("memory exhausted"),
++ &yyss1, yysize * sizeof (*yyssp),
++ &yyvs1, yysize * sizeof (*yyvsp),
++ &yystacksize);
++
++ yyss = yyss1;
++ yyvs = yyvs1;
++ }
++#else /* no yyoverflow */
++# ifndef YYSTACK_RELOCATE
++ goto yyexhaustedlab;
++# else
++ /* Extend the stack our own way. */
++ if (YYMAXDEPTH <= yystacksize)
++ goto yyexhaustedlab;
++ yystacksize *= 2;
++ if (YYMAXDEPTH < yystacksize)
++ yystacksize = YYMAXDEPTH;
++
++ {
++ yytype_int16 *yyss1 = yyss;
++ union yyalloc *yyptr =
++ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
++ if (! yyptr)
++ goto yyexhaustedlab;
++ YYSTACK_RELOCATE (yyss_alloc, yyss);
++ YYSTACK_RELOCATE (yyvs_alloc, yyvs);
++# undef YYSTACK_RELOCATE
++ if (yyss1 != yyssa)
++ YYSTACK_FREE (yyss1);
++ }
++# endif
++#endif /* no yyoverflow */
++
++ yyssp = yyss + yysize - 1;
++ yyvsp = yyvs + yysize - 1;
++
++ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
++ (unsigned long int) yystacksize));
++
++ if (yyss + yystacksize - 1 <= yyssp)
++ YYABORT;
++ }
++
++ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
++
++ if (yystate == YYFINAL)
++ YYACCEPT;
++
++ goto yybackup;
++
++/*-----------.
++| yybackup. |
++`-----------*/
++yybackup:
++
++ /* Do appropriate processing given the current state. Read a
++ lookahead token if we need one and don't already have one. */
++
++ /* First try to decide what to do without reference to lookahead token. */
++ yyn = yypact[yystate];
++ if (yypact_value_is_default (yyn))
++ goto yydefault;
++
++ /* Not known => get a lookahead token if don't already have one. */
++
++ /* YYCHAR is either YYEMPTY or YYEOF or a valid lookahead symbol. */
++ if (yychar == YYEMPTY)
++ {
++ YYDPRINTF ((stderr, "Reading a token: "));
++ yychar = YYLEX;
++ }
++
++ if (yychar <= YYEOF)
++ {
++ yychar = yytoken = YYEOF;
++ YYDPRINTF ((stderr, "Now at end of input.\n"));
++ }
++ else
++ {
++ yytoken = YYTRANSLATE (yychar);
++ YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
++ }
++
++ /* If the proper action on seeing token YYTOKEN is to reduce or to
++ detect an error, take that action. */
++ yyn += yytoken;
++ if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
++ goto yydefault;
++ yyn = yytable[yyn];
++ if (yyn <= 0)
++ {
++ if (yytable_value_is_error (yyn))
++ goto yyerrlab;
++ yyn = -yyn;
++ goto yyreduce;
++ }
++
++ /* Count tokens shifted since error; after three, turn off error
++ status. */
++ if (yyerrstatus)
++ yyerrstatus--;
++
++ /* Shift the lookahead token. */
++ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
++
++ /* Discard the shifted token. */
++ yychar = YYEMPTY;
++
++ yystate = yyn;
++ *++yyvsp = yylval;
++
++ goto yynewstate;
++
++
++/*-----------------------------------------------------------.
++| yydefault -- do the default action for the current state. |
++`-----------------------------------------------------------*/
++yydefault:
++ yyn = yydefact[yystate];
++ if (yyn == 0)
++ goto yyerrlab;
++ goto yyreduce;
++
++
++/*-----------------------------.
++| yyreduce -- Do a reduction. |
++`-----------------------------*/
++yyreduce:
++ /* yyn is the number of a rule to reduce with. */
++ yylen = yyr2[yyn];
++
++ /* If YYLEN is nonzero, implement the default value of the action:
++ `$$ = $1'.
++
++ Otherwise, the following line sets YYVAL to garbage.
++ This behavior is undocumented and Bison
++ users should not rely upon it. Assigning to YYVAL
++ unconditionally makes the parser a bit smaller, and it avoids a
++ GCC warning that YYVAL may be used uninitialized. */
++ yyval = yyvsp[1-yylen];
++
++
++ YY_REDUCE_PRINT (yyn);
++ switch (yyn)
++ {
++ case 11:
++
++/* Line 1806 of yacc.c */
++#line 133 "lib/conf-parse.y"
++ { sensors_bus new_el;
++ new_el.line = (yyvsp[(1) - (3)].line);
++ new_el.bus = (yyvsp[(2) - (3)].bus);
++ new_el.adapter = (yyvsp[(3) - (3)].name);
++ bus_add_el(&new_el);
++ }
++ break;
++
++ case 12:
++
++/* Line 1806 of yacc.c */
++#line 142 "lib/conf-parse.y"
++ { sensors_label new_el;
++ if (!current_chip) {
++ sensors_yyerror("Label statement before first chip statement");
++ free((yyvsp[(2) - (3)].name));
++ free((yyvsp[(3) - (3)].name));
++ YYERROR;
++ }
++ new_el.line = (yyvsp[(1) - (3)].line);
++ new_el.name = (yyvsp[(2) - (3)].name);
++ new_el.value = (yyvsp[(3) - (3)].name);
++ label_add_el(&new_el);
++ }
++ break;
++
++ case 13:
++
++/* Line 1806 of yacc.c */
++#line 157 "lib/conf-parse.y"
++ { sensors_set new_el;
++ if (!current_chip) {
++ sensors_yyerror("Set statement before first chip statement");
++ free((yyvsp[(2) - (3)].name));
++ sensors_free_expr((yyvsp[(3) - (3)].expr));
++ YYERROR;
++ }
++ new_el.line = (yyvsp[(1) - (3)].line);
++ new_el.name = (yyvsp[(2) - (3)].name);
++ new_el.value = (yyvsp[(3) - (3)].expr);
++ set_add_el(&new_el);
++ }
++ break;
++
++ case 14:
++
++/* Line 1806 of yacc.c */
++#line 172 "lib/conf-parse.y"
++ { sensors_compute new_el;
++ if (!current_chip) {
++ sensors_yyerror("Compute statement before first chip statement");
++ free((yyvsp[(2) - (5)].name));
++ sensors_free_expr((yyvsp[(3) - (5)].expr));
++ sensors_free_expr((yyvsp[(5) - (5)].expr));
++ YYERROR;
++ }
++ new_el.line = (yyvsp[(1) - (5)].line);
++ new_el.name = (yyvsp[(2) - (5)].name);
++ new_el.from_proc = (yyvsp[(3) - (5)].expr);
++ new_el.to_proc = (yyvsp[(5) - (5)].expr);
++ compute_add_el(&new_el);
++ }
++ break;
++
++ case 15:
++
++/* Line 1806 of yacc.c */
++#line 189 "lib/conf-parse.y"
++ { sensors_ignore new_el;
++ if (!current_chip) {
++ sensors_yyerror("Ignore statement before first chip statement");
++ free((yyvsp[(2) - (2)].name));
++ YYERROR;
++ }
++ new_el.line = (yyvsp[(1) - (2)].line);
++ new_el.name = (yyvsp[(2) - (2)].name);
++ ignore_add_el(&new_el);
++ }
++ break;
++
++ case 16:
++
++/* Line 1806 of yacc.c */
++#line 202 "lib/conf-parse.y"
++ { sensors_chip new_el;
++ new_el.line = (yyvsp[(1) - (2)].line);
++ new_el.labels = NULL;
++ new_el.sets = NULL;
++ new_el.computes = NULL;
++ new_el.ignores = NULL;
++ new_el.labels_count = new_el.labels_max = 0;
++ new_el.sets_count = new_el.sets_max = 0;
++ new_el.computes_count = new_el.computes_max = 0;
++ new_el.ignores_count = new_el.ignores_max = 0;
++ new_el.chips = (yyvsp[(2) - (2)].chips);
++ chip_add_el(&new_el);
++ current_chip = sensors_config_chips +
++ sensors_config_chips_count - 1;
++ }
++ break;
++
++ case 17:
++
++/* Line 1806 of yacc.c */
++#line 220 "lib/conf-parse.y"
++ {
++ (yyval.chips).fits = NULL;
++ (yyval.chips).fits_count = (yyval.chips).fits_max = 0;
++ fits_add_el(&(yyvsp[(1) - (1)].chip),(yyval.chips));
++ }
++ break;
++
++ case 18:
++
++/* Line 1806 of yacc.c */
++#line 226 "lib/conf-parse.y"
++ { (yyval.chips) = (yyvsp[(1) - (2)].chips);
++ fits_add_el(&(yyvsp[(2) - (2)].chip),(yyval.chips));
++ }
++ break;
++
++ case 19:
++
++/* Line 1806 of yacc.c */
++#line 232 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->data.val = (yyvsp[(1) - (1)].value);
++ (yyval.expr)->kind = sensors_kind_val;
++ }
++ break;
++
++ case 20:
++
++/* Line 1806 of yacc.c */
++#line 237 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->data.var = (yyvsp[(1) - (1)].name);
++ (yyval.expr)->kind = sensors_kind_var;
++ }
++ break;
++
++ case 21:
++
++/* Line 1806 of yacc.c */
++#line 242 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->kind = sensors_kind_source;
++ }
++ break;
++
++ case 22:
++
++/* Line 1806 of yacc.c */
++#line 246 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->kind = sensors_kind_sub;
++ (yyval.expr)->data.subexpr.op = sensors_add;
++ (yyval.expr)->data.subexpr.sub1 = (yyvsp[(1) - (3)].expr);
++ (yyval.expr)->data.subexpr.sub2 = (yyvsp[(3) - (3)].expr);
++ }
++ break;
++
++ case 23:
++
++/* Line 1806 of yacc.c */
++#line 253 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->kind = sensors_kind_sub;
++ (yyval.expr)->data.subexpr.op = sensors_sub;
++ (yyval.expr)->data.subexpr.sub1 = (yyvsp[(1) - (3)].expr);
++ (yyval.expr)->data.subexpr.sub2 = (yyvsp[(3) - (3)].expr);
++ }
++ break;
++
++ case 24:
++
++/* Line 1806 of yacc.c */
++#line 260 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->kind = sensors_kind_sub;
++ (yyval.expr)->data.subexpr.op = sensors_multiply;
++ (yyval.expr)->data.subexpr.sub1 = (yyvsp[(1) - (3)].expr);
++ (yyval.expr)->data.subexpr.sub2 = (yyvsp[(3) - (3)].expr);
++ }
++ break;
++
++ case 25:
++
++/* Line 1806 of yacc.c */
++#line 267 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->kind = sensors_kind_sub;
++ (yyval.expr)->data.subexpr.op = sensors_divide;
++ (yyval.expr)->data.subexpr.sub1 = (yyvsp[(1) - (3)].expr);
++ (yyval.expr)->data.subexpr.sub2 = (yyvsp[(3) - (3)].expr);
++ }
++ break;
++
++ case 26:
++
++/* Line 1806 of yacc.c */
++#line 274 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->kind = sensors_kind_sub;
++ (yyval.expr)->data.subexpr.op = sensors_negate;
++ (yyval.expr)->data.subexpr.sub1 = (yyvsp[(2) - (2)].expr);
++ (yyval.expr)->data.subexpr.sub2 = NULL;
++ }
++ break;
++
++ case 27:
++
++/* Line 1806 of yacc.c */
++#line 281 "lib/conf-parse.y"
++ { (yyval.expr) = (yyvsp[(2) - (3)].expr); }
++ break;
++
++ case 28:
++
++/* Line 1806 of yacc.c */
++#line 283 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->kind = sensors_kind_sub;
++ (yyval.expr)->data.subexpr.op = sensors_exp;
++ (yyval.expr)->data.subexpr.sub1 = (yyvsp[(2) - (2)].expr);
++ (yyval.expr)->data.subexpr.sub2 = NULL;
++ }
++ break;
++
++ case 29:
++
++/* Line 1806 of yacc.c */
++#line 290 "lib/conf-parse.y"
++ { (yyval.expr) = malloc_expr();
++ (yyval.expr)->kind = sensors_kind_sub;
++ (yyval.expr)->data.subexpr.op = sensors_log;
++ (yyval.expr)->data.subexpr.sub1 = (yyvsp[(2) - (2)].expr);
++ (yyval.expr)->data.subexpr.sub2 = NULL;
++ }
++ break;
++
++ case 30:
++
++/* Line 1806 of yacc.c */
++#line 299 "lib/conf-parse.y"
++ { int res = sensors_parse_bus_id((yyvsp[(1) - (1)].name),&(yyval.bus));
++ free((yyvsp[(1) - (1)].name));
++ if (res) {
++ sensors_yyerror("Parse error in bus id");
++ YYERROR;
++ }
++ }
++ break;
++
++ case 31:
++
++/* Line 1806 of yacc.c */
++#line 309 "lib/conf-parse.y"
++ { (yyval.name) = (yyvsp[(1) - (1)].name); }
++ break;
++
++ case 32:
++
++/* Line 1806 of yacc.c */
++#line 313 "lib/conf-parse.y"
++ { (yyval.name) = (yyvsp[(1) - (1)].name); }
++ break;
++
++ case 33:
++
++/* Line 1806 of yacc.c */
++#line 317 "lib/conf-parse.y"
++ { (yyval.name) = (yyvsp[(1) - (1)].name); }
++ break;
++
++ case 34:
++
++/* Line 1806 of yacc.c */
++#line 321 "lib/conf-parse.y"
++ { int res = sensors_parse_chip_name((yyvsp[(1) - (1)].name),&(yyval.chip));
++ free((yyvsp[(1) - (1)].name));
++ if (res) {
++ sensors_yyerror("Parse error in chip name");
++ YYERROR;
++ }
++ }
++ break;
++
++
++
++/* Line 1806 of yacc.c */
++#line 1793 "lib/conf-parse.c"
++ default: break;
++ }
++ /* User semantic actions sometimes alter yychar, and that requires
++ that yytoken be updated with the new translation. We take the
++ approach of translating immediately before every use of yytoken.
++ One alternative is translating here after every semantic action,
++ but that translation would be missed if the semantic action invokes
++ YYABORT, YYACCEPT, or YYERROR immediately after altering yychar or
++ if it invokes YYBACKUP. In the case of YYABORT or YYACCEPT, an
++ incorrect destructor might then be invoked immediately. In the
++ case of YYERROR or YYBACKUP, subsequent parser actions might lead
++ to an incorrect destructor call or verbose syntax error message
++ before the lookahead is translated. */
++ YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
++
++ YYPOPSTACK (yylen);
++ yylen = 0;
++ YY_STACK_PRINT (yyss, yyssp);
++
++ *++yyvsp = yyval;
++
++ /* Now `shift' the result of the reduction. Determine what state
++ that goes to, based on the state we popped back to and the rule
++ number reduced by. */
++
++ yyn = yyr1[yyn];
++
++ yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
++ if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
++ yystate = yytable[yystate];
++ else
++ yystate = yydefgoto[yyn - YYNTOKENS];
++
++ goto yynewstate;
++
++
++/*------------------------------------.
++| yyerrlab -- here on detecting error |
++`------------------------------------*/
++yyerrlab:
++ /* Make sure we have latest lookahead translation. See comments at
++ user semantic actions for why this is necessary. */
++ yytoken = yychar == YYEMPTY ? YYEMPTY : YYTRANSLATE (yychar);
++
++ /* If not already recovering from an error, report this error. */
++ if (!yyerrstatus)
++ {
++ ++yynerrs;
++#if ! YYERROR_VERBOSE
++ yyerror (YY_("syntax error"));
++#else
++# define YYSYNTAX_ERROR yysyntax_error (&yymsg_alloc, &yymsg, \
++ yyssp, yytoken)
++ {
++ char const *yymsgp = YY_("syntax error");
++ int yysyntax_error_status;
++ yysyntax_error_status = YYSYNTAX_ERROR;
++ if (yysyntax_error_status == 0)
++ yymsgp = yymsg;
++ else if (yysyntax_error_status == 1)
++ {
++ if (yymsg != yymsgbuf)
++ YYSTACK_FREE (yymsg);
++ yymsg = (char *) YYSTACK_ALLOC (yymsg_alloc);
++ if (!yymsg)
++ {
++ yymsg = yymsgbuf;
++ yymsg_alloc = sizeof yymsgbuf;
++ yysyntax_error_status = 2;
++ }
++ else
++ {
++ yysyntax_error_status = YYSYNTAX_ERROR;
++ yymsgp = yymsg;
++ }
++ }
++ yyerror (yymsgp);
++ if (yysyntax_error_status == 2)
++ goto yyexhaustedlab;
++ }
++# undef YYSYNTAX_ERROR
++#endif
++ }
++
++
++
++ if (yyerrstatus == 3)
++ {
++ /* If just tried and failed to reuse lookahead token after an
++ error, discard it. */
++
++ if (yychar <= YYEOF)
++ {
++ /* Return failure if at end of input. */
++ if (yychar == YYEOF)
++ YYABORT;
++ }
++ else
++ {
++ yydestruct ("Error: discarding",
++ yytoken, &yylval);
++ yychar = YYEMPTY;
++ }
++ }
++
++ /* Else will try to reuse lookahead token after shifting the error
++ token. */
++ goto yyerrlab1;
++
++
++/*---------------------------------------------------.
++| yyerrorlab -- error raised explicitly by YYERROR. |
++`---------------------------------------------------*/
++yyerrorlab:
++
++ /* Pacify compilers like GCC when the user code never invokes
++ YYERROR and the label yyerrorlab therefore never appears in user
++ code. */
++ if (/*CONSTCOND*/ 0)
++ goto yyerrorlab;
++
++ /* Do not reclaim the symbols of the rule which action triggered
++ this YYERROR. */
++ YYPOPSTACK (yylen);
++ yylen = 0;
++ YY_STACK_PRINT (yyss, yyssp);
++ yystate = *yyssp;
++ goto yyerrlab1;
++
++
++/*-------------------------------------------------------------.
++| yyerrlab1 -- common code for both syntax error and YYERROR. |
++`-------------------------------------------------------------*/
++yyerrlab1:
++ yyerrstatus = 3; /* Each real token shifted decrements this. */
++
++ for (;;)
++ {
++ yyn = yypact[yystate];
++ if (!yypact_value_is_default (yyn))
++ {
++ yyn += YYTERROR;
++ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
++ {
++ yyn = yytable[yyn];
++ if (0 < yyn)
++ break;
++ }
++ }
++
++ /* Pop the current state because it cannot handle the error token. */
++ if (yyssp == yyss)
++ YYABORT;
++
++
++ yydestruct ("Error: popping",
++ yystos[yystate], yyvsp);
++ YYPOPSTACK (1);
++ yystate = *yyssp;
++ YY_STACK_PRINT (yyss, yyssp);
++ }
++
++ *++yyvsp = yylval;
++
++
++ /* Shift the error token. */
++ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
++
++ yystate = yyn;
++ goto yynewstate;
++
++
++/*-------------------------------------.
++| yyacceptlab -- YYACCEPT comes here. |
++`-------------------------------------*/
++yyacceptlab:
++ yyresult = 0;
++ goto yyreturn;
++
++/*-----------------------------------.
++| yyabortlab -- YYABORT comes here. |
++`-----------------------------------*/
++yyabortlab:
++ yyresult = 1;
++ goto yyreturn;
++
++#if !defined(yyoverflow) || YYERROR_VERBOSE
++/*-------------------------------------------------.
++| yyexhaustedlab -- memory exhaustion comes here. |
++`-------------------------------------------------*/
++yyexhaustedlab:
++ yyerror (YY_("memory exhausted"));
++ yyresult = 2;
++ /* Fall through. */
++#endif
++
++yyreturn:
++ if (yychar != YYEMPTY)
++ {
++ /* Make sure we have latest lookahead translation. See comments at
++ user semantic actions for why this is necessary. */
++ yytoken = YYTRANSLATE (yychar);
++ yydestruct ("Cleanup: discarding lookahead",
++ yytoken, &yylval);
++ }
++ /* Do not reclaim the symbols of the rule which action triggered
++ this YYABORT or YYACCEPT. */
++ YYPOPSTACK (yylen);
++ YY_STACK_PRINT (yyss, yyssp);
++ while (yyssp != yyss)
++ {
++ yydestruct ("Cleanup: popping",
++ yystos[*yyssp], yyvsp);
++ YYPOPSTACK (1);
++ }
++#ifndef yyoverflow
++ if (yyss != yyssa)
++ YYSTACK_FREE (yyss);
++#endif
++#if YYERROR_VERBOSE
++ if (yymsg != yymsgbuf)
++ YYSTACK_FREE (yymsg);
++#endif
++ /* Make sure YYID is used. */
++ return YYID (yyresult);
++}
++
++
++
++/* Line 2067 of yacc.c */
++#line 330 "lib/conf-parse.y"
++
++
++void sensors_yyerror(const char *err)
++{
++ if (sensors_lex_error[0]) {
++ sensors_parse_error_wfn(sensors_lex_error, sensors_yyfilename, sensors_yylineno);
++ sensors_lex_error[0] = '\0';
++ } else
++ sensors_parse_error_wfn(err, sensors_yyfilename, sensors_yylineno);
++}
++
++sensors_expr *malloc_expr(void)
++{
++ sensors_expr *res = malloc(sizeof(sensors_expr));
++ if (! res)
++ sensors_fatal_error(__func__, "Allocating a new expression");
++ return res;
++}
++
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-parse.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-parse.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-parse.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-parse.h 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,84 @@
++/* A Bison parser, made by GNU Bison 2.5. */
++
++/* Bison interface for Yacc-like parsers in C
++
++ Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc.
++
++ This program is free software: you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation, either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program. If not, see <http://www.gnu.org/licenses/>. */
++
++/* As a special exception, you may create a larger work that contains
++ part or all of the Bison parser skeleton and distribute that work
++ under terms of your choice, so long as that work isn't itself a
++ parser generator using the skeleton or a modified version thereof
++ as a parser skeleton. Alternatively, if you modify or redistribute
++ the parser skeleton itself, you may (at your option) remove this
++ special exception, which will cause the skeleton and the resulting
++ Bison output files to be licensed under the GNU General Public
++ License without this special exception.
++
++ This special exception was added by the Free Software Foundation in
++ version 2.2 of Bison. */
++
++
++/* Tokens. */
++#ifndef YYTOKENTYPE
++# define YYTOKENTYPE
++ /* Put the tokens into the symbol table, so that GDB and other debuggers
++ know about them. */
++ enum yytokentype {
++ NEG = 258,
++ EOL = 259,
++ BUS = 260,
++ LABEL = 261,
++ SET = 262,
++ CHIP = 263,
++ COMPUTE = 264,
++ IGNORE = 265,
++ FLOAT = 266,
++ NAME = 267,
++ ERROR = 268
++ };
++#endif
++
++
++
++#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
++typedef union YYSTYPE
++{
++
++/* Line 2068 of yacc.c */
++#line 79 "lib/conf-parse.y"
++
++ double value;
++ char *name;
++ void *nothing;
++ sensors_chip_name_list chips;
++ sensors_expr *expr;
++ sensors_bus_id bus;
++ sensors_chip_name chip;
++ sensors_config_line line;
++
++
++
++/* Line 2068 of yacc.c */
++#line 76 "lib/conf-parse.h"
++} YYSTYPE;
++# define YYSTYPE_IS_TRIVIAL 1
++# define yystype YYSTYPE /* obsolescent; will be withdrawn */
++# define YYSTYPE_IS_DECLARED 1
++#endif
++
++extern YYSTYPE sensors_yylval;
++
++
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-parse.y linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-parse.y
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/conf-parse.y 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/conf-parse.y 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,347 @@
++%{
++/*
++ conf-parse.y - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#define YYERROR_VERBOSE
++
++#include <stdio.h>
++#include <string.h>
++#include <stdlib.h>
++
++#include "data.h"
++#include "general.h"
++#include "error.h"
++#include "conf.h"
++#include "access.h"
++#include "init.h"
++
++static void sensors_yyerror(const char *err);
++static sensors_expr *malloc_expr(void);
++
++static sensors_chip *current_chip = NULL;
++
++#define bus_add_el(el) sensors_add_array_el(el,\
++ &sensors_config_busses,\
++ &sensors_config_busses_count,\
++ &sensors_config_busses_max,\
++ sizeof(sensors_bus))
++#define label_add_el(el) sensors_add_array_el(el,\
++ &current_chip->labels,\
++ &current_chip->labels_count,\
++ &current_chip->labels_max,\
++ sizeof(sensors_label));
++#define set_add_el(el) sensors_add_array_el(el,\
++ &current_chip->sets,\
++ &current_chip->sets_count,\
++ &current_chip->sets_max,\
++ sizeof(sensors_set));
++#define compute_add_el(el) sensors_add_array_el(el,\
++ &current_chip->computes,\
++ &current_chip->computes_count,\
++ &current_chip->computes_max,\
++ sizeof(sensors_compute));
++#define ignore_add_el(el) sensors_add_array_el(el,\
++ &current_chip->ignores,\
++ &current_chip->ignores_count,\
++ &current_chip->ignores_max,\
++ sizeof(sensors_ignore));
++#define chip_add_el(el) sensors_add_array_el(el,\
++ &sensors_config_chips,\
++ &sensors_config_chips_count,\
++ &sensors_config_chips_max,\
++ sizeof(sensors_chip));
++
++#define fits_add_el(el,list) sensors_add_array_el(el,\
++ &(list).fits,\
++ &(list).fits_count,\
++ &(list).fits_max, \
++ sizeof(sensors_chip_name));
++
++%}
++
++%union {
++ double value;
++ char *name;
++ void *nothing;
++ sensors_chip_name_list chips;
++ sensors_expr *expr;
++ sensors_bus_id bus;
++ sensors_chip_name chip;
++ sensors_config_line line;
++}
++
++%left <nothing> '-' '+'
++%left <nothing> '*' '/'
++%left <nothing> NEG
++%right <nothing> '^' '`'
++
++%token <nothing> ','
++%token <nothing> EOL
++%token <line> BUS
++%token <line> LABEL
++%token <line> SET
++%token <line> CHIP
++%token <line> COMPUTE
++%token <line> IGNORE
++%token <value> FLOAT
++%token <name> NAME
++%token <nothing> ERROR
++
++%type <chips> chip_name_list
++%type <expr> expression
++%type <bus> bus_id
++%type <name> adapter_name
++%type <name> function_name
++%type <name> string
++%type <chip> chip_name
++
++%start input
++
++%%
++
++input: /* empty */
++ | input line
++;
++
++line: bus_statement EOL
++ | label_statement EOL
++ | set_statement EOL
++ | chip_statement EOL
++ | compute_statement EOL
++ | ignore_statement EOL
++ | error EOL
++;
++
++bus_statement: BUS bus_id adapter_name
++ { sensors_bus new_el;
++ new_el.line = $1;
++ new_el.bus = $2;
++ new_el.adapter = $3;
++ bus_add_el(&new_el);
++ }
++;
++
++label_statement: LABEL function_name string
++ { sensors_label new_el;
++ if (!current_chip) {
++ sensors_yyerror("Label statement before first chip statement");
++ free($2);
++ free($3);
++ YYERROR;
++ }
++ new_el.line = $1;
++ new_el.name = $2;
++ new_el.value = $3;
++ label_add_el(&new_el);
++ }
++;
++
++set_statement: SET function_name expression
++ { sensors_set new_el;
++ if (!current_chip) {
++ sensors_yyerror("Set statement before first chip statement");
++ free($2);
++ sensors_free_expr($3);
++ YYERROR;
++ }
++ new_el.line = $1;
++ new_el.name = $2;
++ new_el.value = $3;
++ set_add_el(&new_el);
++ }
++;
++
++compute_statement: COMPUTE function_name expression ',' expression
++ { sensors_compute new_el;
++ if (!current_chip) {
++ sensors_yyerror("Compute statement before first chip statement");
++ free($2);
++ sensors_free_expr($3);
++ sensors_free_expr($5);
++ YYERROR;
++ }
++ new_el.line = $1;
++ new_el.name = $2;
++ new_el.from_proc = $3;
++ new_el.to_proc = $5;
++ compute_add_el(&new_el);
++ }
++;
++
++ignore_statement: IGNORE function_name
++ { sensors_ignore new_el;
++ if (!current_chip) {
++ sensors_yyerror("Ignore statement before first chip statement");
++ free($2);
++ YYERROR;
++ }
++ new_el.line = $1;
++ new_el.name = $2;
++ ignore_add_el(&new_el);
++ }
++;
++
++chip_statement: CHIP chip_name_list
++ { sensors_chip new_el;
++ new_el.line = $1;
++ new_el.labels = NULL;
++ new_el.sets = NULL;
++ new_el.computes = NULL;
++ new_el.ignores = NULL;
++ new_el.labels_count = new_el.labels_max = 0;
++ new_el.sets_count = new_el.sets_max = 0;
++ new_el.computes_count = new_el.computes_max = 0;
++ new_el.ignores_count = new_el.ignores_max = 0;
++ new_el.chips = $2;
++ chip_add_el(&new_el);
++ current_chip = sensors_config_chips +
++ sensors_config_chips_count - 1;
++ }
++;
++
++chip_name_list: chip_name
++ {
++ $$.fits = NULL;
++ $$.fits_count = $$.fits_max = 0;
++ fits_add_el(&$1,$$);
++ }
++ | chip_name_list chip_name
++ { $$ = $1;
++ fits_add_el(&$2,$$);
++ }
++;
++
++expression: FLOAT
++ { $$ = malloc_expr();
++ $$->data.val = $1;
++ $$->kind = sensors_kind_val;
++ }
++ | NAME
++ { $$ = malloc_expr();
++ $$->data.var = $1;
++ $$->kind = sensors_kind_var;
++ }
++ | '@'
++ { $$ = malloc_expr();
++ $$->kind = sensors_kind_source;
++ }
++ | expression '+' expression
++ { $$ = malloc_expr();
++ $$->kind = sensors_kind_sub;
++ $$->data.subexpr.op = sensors_add;
++ $$->data.subexpr.sub1 = $1;
++ $$->data.subexpr.sub2 = $3;
++ }
++ | expression '-' expression
++ { $$ = malloc_expr();
++ $$->kind = sensors_kind_sub;
++ $$->data.subexpr.op = sensors_sub;
++ $$->data.subexpr.sub1 = $1;
++ $$->data.subexpr.sub2 = $3;
++ }
++ | expression '*' expression
++ { $$ = malloc_expr();
++ $$->kind = sensors_kind_sub;
++ $$->data.subexpr.op = sensors_multiply;
++ $$->data.subexpr.sub1 = $1;
++ $$->data.subexpr.sub2 = $3;
++ }
++ | expression '/' expression
++ { $$ = malloc_expr();
++ $$->kind = sensors_kind_sub;
++ $$->data.subexpr.op = sensors_divide;
++ $$->data.subexpr.sub1 = $1;
++ $$->data.subexpr.sub2 = $3;
++ }
++ | '-' expression %prec NEG
++ { $$ = malloc_expr();
++ $$->kind = sensors_kind_sub;
++ $$->data.subexpr.op = sensors_negate;
++ $$->data.subexpr.sub1 = $2;
++ $$->data.subexpr.sub2 = NULL;
++ }
++ | '(' expression ')'
++ { $$ = $2; }
++ | '^' expression
++ { $$ = malloc_expr();
++ $$->kind = sensors_kind_sub;
++ $$->data.subexpr.op = sensors_exp;
++ $$->data.subexpr.sub1 = $2;
++ $$->data.subexpr.sub2 = NULL;
++ }
++ | '`' expression
++ { $$ = malloc_expr();
++ $$->kind = sensors_kind_sub;
++ $$->data.subexpr.op = sensors_log;
++ $$->data.subexpr.sub1 = $2;
++ $$->data.subexpr.sub2 = NULL;
++ }
++;
++
++bus_id: NAME
++ { int res = sensors_parse_bus_id($1,&$$);
++ free($1);
++ if (res) {
++ sensors_yyerror("Parse error in bus id");
++ YYERROR;
++ }
++ }
++;
++
++adapter_name: NAME
++ { $$ = $1; }
++;
++
++function_name: NAME
++ { $$ = $1; }
++;
++
++string: NAME
++ { $$ = $1; }
++;
++
++chip_name: NAME
++ { int res = sensors_parse_chip_name($1,&$$);
++ free($1);
++ if (res) {
++ sensors_yyerror("Parse error in chip name");
++ YYERROR;
++ }
++ }
++;
++
++%%
++
++void sensors_yyerror(const char *err)
++{
++ if (sensors_lex_error[0]) {
++ sensors_parse_error_wfn(sensors_lex_error, sensors_yyfilename, sensors_yylineno);
++ sensors_lex_error[0] = '\0';
++ } else
++ sensors_parse_error_wfn(err, sensors_yyfilename, sensors_yylineno);
++}
++
++sensors_expr *malloc_expr(void)
++{
++ sensors_expr *res = malloc(sizeof(sensors_expr));
++ if (! res)
++ sensors_fatal_error(__func__, "Allocating a new expression");
++ return res;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/COPYING.LGPL linux-linaro-stable-mx6/tools/gator/daemon/libsensors/COPYING.LGPL
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/COPYING.LGPL 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/COPYING.LGPL 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,502 @@
++ GNU LESSER GENERAL PUBLIC LICENSE
++ Version 2.1, February 1999
++
++ Copyright (C) 1991, 1999 Free Software Foundation, Inc.
++ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
++ Everyone is permitted to copy and distribute verbatim copies
++ of this license document, but changing it is not allowed.
++
++[This is the first released version of the Lesser GPL. It also counts
++ as the successor of the GNU Library Public License, version 2, hence
++ the version number 2.1.]
++
++ Preamble
++
++ The licenses for most software are designed to take away your
++freedom to share and change it. By contrast, the GNU General Public
++Licenses are intended to guarantee your freedom to share and change
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++can use it too, but we suggest you first think carefully about whether
++this license or the ordinary General Public License is the better
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++
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+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/data.c linux-linaro-stable-mx6/tools/gator/daemon/libsensors/data.c
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/data.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/data.c 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,278 @@
++/*
++ data.c - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++ Copyright (C) 2007, 2009 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++/*** This file modified by ARM on Jan 23, 2013 to move version.h to the current directory. ***/
++
++/* this define needed for strndup() */
++#define _GNU_SOURCE
++
++#include <stdlib.h>
++#include <string.h>
++
++#include "access.h"
++#include "error.h"
++#include "data.h"
++#include "sensors.h"
++#include "version.h"
++
++const char *libsensors_version = LM_VERSION;
++
++char **sensors_config_files = NULL;
++int sensors_config_files_count = 0;
++int sensors_config_files_max = 0;
++
++sensors_chip *sensors_config_chips = NULL;
++int sensors_config_chips_count = 0;
++int sensors_config_chips_subst = 0;
++int sensors_config_chips_max = 0;
++
++sensors_bus *sensors_config_busses = NULL;
++int sensors_config_busses_count = 0;
++int sensors_config_busses_max = 0;
++
++sensors_chip_features *sensors_proc_chips = NULL;
++int sensors_proc_chips_count = 0;
++int sensors_proc_chips_max = 0;
++
++sensors_bus *sensors_proc_bus = NULL;
++int sensors_proc_bus_count = 0;
++int sensors_proc_bus_max = 0;
++
++void sensors_free_chip_name(sensors_chip_name *chip)
++{
++ free(chip->prefix);
++}
++
++/*
++ Parse a chip name to the internal representation. These are valid names:
++
++ lm78-i2c-10-5e *-i2c-10-5e
++ lm78-i2c-10-* *-i2c-10-*
++ lm78-i2c-*-5e *-i2c-*-5e
++ lm78-i2c-*-* *-i2c-*-*
++ lm78-isa-10dd *-isa-10dd
++ lm78-isa-* *-isa-*
++ lm78-* *-*
++
++ Here 'lm78' can be any prefix. 'i2c' and 'isa' are
++ literal strings, just like all dashes '-' and wildcards '*'. '10' can
++ be any decimal i2c bus number. '5e' can be any hexadecimal i2c device
++ address, and '10dd' any hexadecimal isa address.
++
++ The 'prefix' part in the result is freshly allocated. All old contents
++ of res is overwritten. res itself is not allocated. In case of an error
++ return (ie. != 0), res is undefined, but all allocations are undone.
++*/
++
++int sensors_parse_chip_name(const char *name, sensors_chip_name *res)
++{
++ char *dash;
++
++ /* First, the prefix. It's either "*" or a real chip name. */
++ if (!strncmp(name, "*-", 2)) {
++ res->prefix = SENSORS_CHIP_NAME_PREFIX_ANY;
++ name += 2;
++ } else {
++ if (!(dash = strchr(name, '-')))
++ return -SENSORS_ERR_CHIP_NAME;
++ res->prefix = strndup(name, dash - name);
++ if (!res->prefix)
++ sensors_fatal_error(__func__,
++ "Allocating name prefix");
++ name = dash + 1;
++ }
++
++ /* Then we have either a sole "*" (all chips with this name) or a bus
++ type and an address. */
++ if (!strcmp(name, "*")) {
++ res->bus.type = SENSORS_BUS_TYPE_ANY;
++ res->bus.nr = SENSORS_BUS_NR_ANY;
++ res->addr = SENSORS_CHIP_NAME_ADDR_ANY;
++ return 0;
++ }
++
++ if (!(dash = strchr(name, '-')))
++ goto ERROR;
++ if (!strncmp(name, "i2c", dash - name))
++ res->bus.type = SENSORS_BUS_TYPE_I2C;
++ else if (!strncmp(name, "isa", dash - name))
++ res->bus.type = SENSORS_BUS_TYPE_ISA;
++ else if (!strncmp(name, "pci", dash - name))
++ res->bus.type = SENSORS_BUS_TYPE_PCI;
++ else if (!strncmp(name, "spi", dash - name))
++ res->bus.type = SENSORS_BUS_TYPE_SPI;
++ else if (!strncmp(name, "virtual", dash - name))
++ res->bus.type = SENSORS_BUS_TYPE_VIRTUAL;
++ else if (!strncmp(name, "acpi", dash - name))
++ res->bus.type = SENSORS_BUS_TYPE_ACPI;
++ else if (!strncmp(name, "hid", dash - name))
++ res->bus.type = SENSORS_BUS_TYPE_HID;
++ else
++ goto ERROR;
++ name = dash + 1;
++
++ /* Some bus types (i2c, spi) have an additional bus number.
++ For these, the next part is either a "*" (any bus of that type)
++ or a decimal number. */
++ switch (res->bus.type) {
++ case SENSORS_BUS_TYPE_I2C:
++ case SENSORS_BUS_TYPE_SPI:
++ case SENSORS_BUS_TYPE_HID:
++ if (!strncmp(name, "*-", 2)) {
++ res->bus.nr = SENSORS_BUS_NR_ANY;
++ name += 2;
++ break;
++ }
++
++ res->bus.nr = strtoul(name, &dash, 10);
++ if (*name == '\0' || *dash != '-' || res->bus.nr < 0)
++ goto ERROR;
++ name = dash + 1;
++ break;
++ default:
++ res->bus.nr = SENSORS_BUS_NR_ANY;
++ }
++
++ /* Last part is the chip address, or "*" for any address. */
++ if (!strcmp(name, "*")) {
++ res->addr = SENSORS_CHIP_NAME_ADDR_ANY;
++ } else {
++ res->addr = strtoul(name, &dash, 16);
++ if (*name == '\0' || *dash != '\0' || res->addr < 0)
++ goto ERROR;
++ }
++
++ return 0;
++
++ERROR:
++ free(res->prefix);
++ return -SENSORS_ERR_CHIP_NAME;
++}
++
++int sensors_snprintf_chip_name(char *str, size_t size,
++ const sensors_chip_name *chip)
++{
++ if (sensors_chip_name_has_wildcards(chip))
++ return -SENSORS_ERR_WILDCARDS;
++
++ switch (chip->bus.type) {
++ case SENSORS_BUS_TYPE_ISA:
++ return snprintf(str, size, "%s-isa-%04x", chip->prefix,
++ chip->addr);
++ case SENSORS_BUS_TYPE_PCI:
++ return snprintf(str, size, "%s-pci-%04x", chip->prefix,
++ chip->addr);
++ case SENSORS_BUS_TYPE_I2C:
++ return snprintf(str, size, "%s-i2c-%hd-%02x", chip->prefix,
++ chip->bus.nr, chip->addr);
++ case SENSORS_BUS_TYPE_SPI:
++ return snprintf(str, size, "%s-spi-%hd-%x", chip->prefix,
++ chip->bus.nr, chip->addr);
++ case SENSORS_BUS_TYPE_VIRTUAL:
++ return snprintf(str, size, "%s-virtual-%x", chip->prefix,
++ chip->addr);
++ case SENSORS_BUS_TYPE_ACPI:
++ return snprintf(str, size, "%s-acpi-%x", chip->prefix,
++ chip->addr);
++ case SENSORS_BUS_TYPE_HID:
++ return snprintf(str, size, "%s-hid-%hd-%x", chip->prefix,
++ chip->bus.nr, chip->addr);
++ }
++
++ return -SENSORS_ERR_CHIP_NAME;
++}
++
++int sensors_parse_bus_id(const char *name, sensors_bus_id *bus)
++{
++ char *endptr;
++
++ if (strncmp(name, "i2c-", 4)) {
++ return -SENSORS_ERR_BUS_NAME;
++ }
++ name += 4;
++ bus->type = SENSORS_BUS_TYPE_I2C;
++ bus->nr = strtoul(name, &endptr, 10);
++ if (*name == '\0' || *endptr != '\0' || bus->nr < 0)
++ return -SENSORS_ERR_BUS_NAME;
++ return 0;
++}
++
++static int sensors_substitute_chip(sensors_chip_name *name,
++ const char *filename, int lineno)
++{
++ int i, j;
++ for (i = 0; i < sensors_config_busses_count; i++)
++ if (sensors_config_busses[i].bus.type == name->bus.type &&
++ sensors_config_busses[i].bus.nr == name->bus.nr)
++ break;
++
++ if (i == sensors_config_busses_count) {
++ sensors_parse_error_wfn("Undeclared bus id referenced",
++ filename, lineno);
++ name->bus.nr = SENSORS_BUS_NR_IGNORE;
++ return -SENSORS_ERR_BUS_NAME;
++ }
++
++ /* Compare the adapter names */
++ for (j = 0; j < sensors_proc_bus_count; j++) {
++ if (!strcmp(sensors_config_busses[i].adapter,
++ sensors_proc_bus[j].adapter)) {
++ name->bus.nr = sensors_proc_bus[j].bus.nr;
++ return 0;
++ }
++ }
++
++ /* We did not find a matching bus name, simply ignore this chip
++ config entry. */
++ name->bus.nr = SENSORS_BUS_NR_IGNORE;
++ return 0;
++}
++
++/* Bus substitution is on a per-configuration file basis, so we keep
++ memory (in sensors_config_chips_subst) of which chip entries have been
++ already substituted. */
++int sensors_substitute_busses(void)
++{
++ int err, i, j, lineno;
++ sensors_chip_name_list *chips;
++ const char *filename;
++ int res = 0;
++
++ for (i = sensors_config_chips_subst;
++ i < sensors_config_chips_count; i++) {
++ filename = sensors_config_chips[i].line.filename;
++ lineno = sensors_config_chips[i].line.lineno;
++ chips = &sensors_config_chips[i].chips;
++ for (j = 0; j < chips->fits_count; j++) {
++ /* We can only substitute if a specific bus number
++ is given. */
++ if (chips->fits[j].bus.nr == SENSORS_BUS_NR_ANY)
++ continue;
++
++ err = sensors_substitute_chip(&chips->fits[j],
++ filename, lineno);
++ if (err)
++ res = err;
++ }
++ }
++ sensors_config_chips_subst = sensors_config_chips_count;
++ return res;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/data.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/data.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/data.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/data.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,184 @@
++/*
++ data.h - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++ Copyright (C) 2007, 2009 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#ifndef LIB_SENSORS_DATA_H
++#define LIB_SENSORS_DATA_H
++
++#include "sensors.h"
++#include "general.h"
++
++/* This header file contains all kinds of data structures which are used
++ for the representation of the config file data and the sensors
++ data. */
++
++/* Kinds of expression operators recognized */
++typedef enum sensors_operation {
++ sensors_add, sensors_sub, sensors_multiply, sensors_divide,
++ sensors_negate, sensors_exp, sensors_log,
++} sensors_operation;
++
++/* An expression can have several forms */
++typedef enum sensors_expr_kind {
++ sensors_kind_val, sensors_kind_source, sensors_kind_var,
++ sensors_kind_sub
++} sensors_expr_kind;
++
++/* An expression. It is either a floating point value, a variable name,
++ an operation on subexpressions, or the special value 'sub' } */
++struct sensors_expr;
++
++typedef struct sensors_subexpr {
++ sensors_operation op;
++ struct sensors_expr *sub1;
++ struct sensors_expr *sub2;
++} sensors_subexpr;
++
++typedef struct sensors_expr {
++ sensors_expr_kind kind;
++ union {
++ double val;
++ char *var;
++ sensors_subexpr subexpr;
++ } data;
++} sensors_expr;
++
++/* Config file line reference */
++typedef struct sensors_config_line {
++ const char *filename;
++ int lineno;
++} sensors_config_line;
++
++/* Config file label declaration: a feature name, combined with the label
++ value */
++typedef struct sensors_label {
++ char *name;
++ char *value;
++ sensors_config_line line;
++} sensors_label;
++
++/* Config file set declaration: a subfeature name, combined with an
++ expression */
++typedef struct sensors_set {
++ char *name;
++ sensors_expr *value;
++ sensors_config_line line;
++} sensors_set;
++
++/* Config file compute declaration: a feature name, combined with two
++ expressions */
++typedef struct sensors_compute {
++ char *name;
++ sensors_expr *from_proc;
++ sensors_expr *to_proc;
++ sensors_config_line line;
++} sensors_compute;
++
++/* Config file ignore declaration: a feature name */
++typedef struct sensors_ignore {
++ char *name;
++ sensors_config_line line;
++} sensors_ignore;
++
++/* A list of chip names, used to represent a config file chips declaration */
++typedef struct sensors_chip_name_list {
++ sensors_chip_name *fits;
++ int fits_count;
++ int fits_max;
++} sensors_chip_name_list;
++
++/* A config file chip block */
++typedef struct sensors_chip {
++ sensors_chip_name_list chips;
++ sensors_label *labels;
++ int labels_count;
++ int labels_max;
++ sensors_set *sets;
++ int sets_count;
++ int sets_max;
++ sensors_compute *computes;
++ int computes_count;
++ int computes_max;
++ sensors_ignore *ignores;
++ int ignores_count;
++ int ignores_max;
++ sensors_config_line line;
++} sensors_chip;
++
++/* Config file bus declaration: the bus type and number, combined with adapter
++ name */
++typedef struct sensors_bus {
++ char *adapter;
++ sensors_bus_id bus;
++ sensors_config_line line;
++} sensors_bus;
++
++/* Internal data about all features and subfeatures of a chip */
++typedef struct sensors_chip_features {
++ struct sensors_chip_name chip;
++ struct sensors_feature *feature;
++ struct sensors_subfeature *subfeature;
++ int feature_count;
++ int subfeature_count;
++} sensors_chip_features;
++
++extern char **sensors_config_files;
++extern int sensors_config_files_count;
++extern int sensors_config_files_max;
++
++#define sensors_add_config_files(el) sensors_add_array_el( \
++ (el), &sensors_config_files, &sensors_config_files_count, \
++ &sensors_config_files_max, sizeof(char *))
++
++extern sensors_chip *sensors_config_chips;
++extern int sensors_config_chips_count;
++extern int sensors_config_chips_subst;
++extern int sensors_config_chips_max;
++
++extern sensors_bus *sensors_config_busses;
++extern int sensors_config_busses_count;
++extern int sensors_config_busses_max;
++
++extern sensors_chip_features *sensors_proc_chips;
++extern int sensors_proc_chips_count;
++extern int sensors_proc_chips_max;
++
++#define sensors_add_proc_chips(el) sensors_add_array_el( \
++ (el), &sensors_proc_chips, &sensors_proc_chips_count,\
++ &sensors_proc_chips_max, sizeof(struct sensors_chip_features))
++
++extern sensors_bus *sensors_proc_bus;
++extern int sensors_proc_bus_count;
++extern int sensors_proc_bus_max;
++
++#define sensors_add_proc_bus(el) sensors_add_array_el( \
++ (el), &sensors_proc_bus, &sensors_proc_bus_count,\
++ &sensors_proc_bus_max, sizeof(struct sensors_bus))
++
++/* Substitute configuration bus numbers with real-world bus numbers
++ in the chips lists */
++int sensors_substitute_busses(void);
++
++
++/* Parse a bus id into its components. Returns 0 on success, a value from
++ error.h on failure. */
++int sensors_parse_bus_id(const char *name, sensors_bus_id *bus);
++
++#endif /* def LIB_SENSORS_DATA_H */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/error.c linux-linaro-stable-mx6/tools/gator/daemon/libsensors/error.c
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/error.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/error.c 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,92 @@
++/*
++ error.c - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++ Copyright (C) 2007-2009 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#include <stdlib.h>
++#include <stdio.h>
++#include "error.h"
++#include "general.h"
++
++static void sensors_default_parse_error(const char *err, int lineno);
++static void sensors_default_parse_error_wfn(const char *err,
++ const char *filename, int lineno);
++static void sensors_default_fatal_error(const char *proc, const char *err);
++
++void (*sensors_parse_error) (const char *err, int lineno) =
++ sensors_default_parse_error;
++void (*sensors_parse_error_wfn) (const char *err, const char *filename,
++ int lineno) = sensors_default_parse_error_wfn;
++void (*sensors_fatal_error) (const char *proc, const char *err) =
++ sensors_default_fatal_error;
++
++static const char *errorlist[] = {
++ /* Invalid error code */ "Unknown error",
++ /* SENSORS_ERR_WILDCARDS */ "Wildcard found in chip name",
++ /* SENSORS_ERR_NO_ENTRY */ "No such subfeature known",
++ /* SENSORS_ERR_ACCESS_R */ "Can't read",
++ /* SENSORS_ERR_KERNEL */ "Kernel interface error",
++ /* SENSORS_ERR_DIV_ZERO */ "Divide by zero",
++ /* SENSORS_ERR_CHIP_NAME */ "Can't parse chip name",
++ /* SENSORS_ERR_BUS_NAME */ "Can't parse bus name",
++ /* SENSORS_ERR_PARSE */ "General parse error",
++ /* SENSORS_ERR_ACCESS_W */ "Can't write",
++ /* SENSORS_ERR_IO */ "I/O error",
++ /* SENSORS_ERR_RECURSION */ "Evaluation recurses too deep",
++};
++
++const char *sensors_strerror(int errnum)
++{
++ if (errnum < 0)
++ errnum = -errnum;
++ if (errnum >= ARRAY_SIZE(errorlist))
++ errnum = 0;
++ return errorlist[errnum];
++}
++
++void sensors_default_parse_error(const char *err, int lineno)
++{
++ if (lineno)
++ fprintf(stderr, "Error: Line %d: %s\n", lineno, err);
++ else
++ fprintf(stderr, "Error: %s\n", err);
++}
++
++void sensors_default_parse_error_wfn(const char *err,
++ const char *filename, int lineno)
++{
++ /* If application provided a custom parse error reporting function
++ but not the variant with the filename, fall back to the original
++ variant without the filename, for backwards compatibility. */
++ if (sensors_parse_error != sensors_default_parse_error ||
++ !filename)
++ return sensors_parse_error(err, lineno);
++
++ if (lineno)
++ fprintf(stderr, "Error: File %s, line %d: %s\n", filename,
++ lineno, err);
++ else
++ fprintf(stderr, "Error: File %s: %s\n", filename, err);
++}
++
++void sensors_default_fatal_error(const char *proc, const char *err)
++{
++ fprintf(stderr, "Fatal error in `%s': %s\n", proc, err);
++ exit(1);
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/error.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/error.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/error.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/error.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,74 @@
++/*
++ error.h - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++ Copyright (C) 2007-2009 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#ifndef LIB_SENSORS_ERROR_H
++#define LIB_SENSORS_ERROR_H
++
++#define SENSORS_ERR_WILDCARDS 1 /* Wildcard found in chip name */
++#define SENSORS_ERR_NO_ENTRY 2 /* No such subfeature known */
++#define SENSORS_ERR_ACCESS_R 3 /* Can't read */
++#define SENSORS_ERR_KERNEL 4 /* Kernel interface error */
++#define SENSORS_ERR_DIV_ZERO 5 /* Divide by zero */
++#define SENSORS_ERR_CHIP_NAME 6 /* Can't parse chip name */
++#define SENSORS_ERR_BUS_NAME 7 /* Can't parse bus name */
++#define SENSORS_ERR_PARSE 8 /* General parse error */
++#define SENSORS_ERR_ACCESS_W 9 /* Can't write */
++#define SENSORS_ERR_IO 10 /* I/O error */
++#define SENSORS_ERR_RECURSION 11 /* Evaluation recurses too deep */
++
++#ifdef __cplusplus
++extern "C" {
++#endif /* __cplusplus */
++
++
++/* This function returns a pointer to a string which describes the error.
++ errnum may be negative (the corresponding positive error is returned).
++ You may not modify the result! */
++const char *sensors_strerror(int errnum);
++
++/* These functions are called when a parse error is detected. Give them new
++ values, and your own functions are called instead of the default (which
++ print to stderr). These functions may terminate the program, but they
++ usually output an error and return. The first function is the original
++ one, the second one was added later when support for multiple
++ configuration files was added.
++ The library code now only calls the second function. However, for
++ backwards compatibility, if an application provides a custom handling
++ function for the first function but not the second, then all parse
++ errors will be reported using the first function (that is, the filename
++ is never reported.)
++ Note that filename can be NULL (if filename isn't known) and lineno
++ can be 0 (if the error occurs before the actual parsing starts.) */
++extern void (*sensors_parse_error) (const char *err, int lineno);
++extern void (*sensors_parse_error_wfn) (const char *err,
++ const char *filename, int lineno);
++
++/* This function is called when an immediately fatal error (like no
++ memory left) is detected. Give it a new value, and your own function
++ is called instead of the default (which prints to stderr and ends
++ the program). Never let it return! */
++extern void (*sensors_fatal_error) (const char *proc, const char *err);
++
++#ifdef __cplusplus
++}
++#endif /* __cplusplus */
++
++#endif /* def LIB_SENSORS_ERROR_H */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/general.c linux-linaro-stable-mx6/tools/gator/daemon/libsensors/general.c
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/general.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/general.c 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,85 @@
++/*
++ general.c - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#include "error.h"
++#include "general.h"
++#include <errno.h>
++#include <stdio.h>
++#include <string.h>
++#include <stdlib.h>
++
++
++#define A_BUNCH 16
++
++void sensors_malloc_array(void *list, int *num_el, int *max_el, int el_size)
++{
++ void **my_list = (void **)list;
++
++ *my_list = malloc(el_size*A_BUNCH);
++ if (! *my_list)
++ sensors_fatal_error(__func__, "Allocating new elements");
++ *max_el = A_BUNCH;
++ *num_el = 0;
++}
++
++void sensors_free_array(void *list, int *num_el, int *max_el)
++{
++ void **my_list = (void **)list;
++
++ free(*my_list);
++ *my_list = NULL;
++ *num_el = 0;
++ *max_el = 0;
++}
++
++void sensors_add_array_el(const void *el, void *list, int *num_el,
++ int *max_el, int el_size)
++{
++ int new_max_el;
++ void **my_list = (void *)list;
++ if (*num_el + 1 > *max_el) {
++ new_max_el = *max_el + A_BUNCH;
++ *my_list = realloc(*my_list, new_max_el * el_size);
++ if (! *my_list)
++ sensors_fatal_error(__func__,
++ "Allocating new elements");
++ *max_el = new_max_el;
++ }
++ memcpy(((char *) *my_list) + *num_el * el_size, el, el_size);
++ (*num_el) ++;
++}
++
++void sensors_add_array_els(const void *els, int nr_els, void *list,
++ int *num_el, int *max_el, int el_size)
++{
++ int new_max_el;
++ void **my_list = (void *)list;
++ if (*num_el + nr_els > *max_el) {
++ new_max_el = (*max_el + nr_els + A_BUNCH);
++ new_max_el -= new_max_el % A_BUNCH;
++ *my_list = realloc(*my_list, new_max_el * el_size);
++ if (! *my_list)
++ sensors_fatal_error(__func__,
++ "Allocating new elements");
++ *max_el = new_max_el;
++ }
++ memcpy(((char *)*my_list) + *num_el * el_size, els, el_size * nr_els);
++ *num_el += nr_els;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/general.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/general.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/general.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/general.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,39 @@
++/*
++ general.h - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#ifndef LIB_SENSORS_GENERAL
++#define LIB_SENSORS_GENERAL
++
++/* These are general purpose functions. They allow you to use variable-
++ length arrays, which are extended automatically. A distinction is
++ made between the current number of elements and the maximum number.
++ You can only add elements at the end. Primitive, but very useful
++ for internal use. */
++void sensors_malloc_array(void *list, int *num_el, int *max_el,
++ int el_size);
++void sensors_free_array(void *list, int *num_el, int *max_el);
++void sensors_add_array_el(const void *el, void *list, int *num_el,
++ int *max_el, int el_size);
++void sensors_add_array_els(const void *els, int nr_els, void *list,
++ int *num_el, int *max_el, int el_size);
++
++#define ARRAY_SIZE(arr) (int)(sizeof(arr) / sizeof((arr)[0]))
++
++#endif /* LIB_SENSORS_GENERAL */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/init.c linux-linaro-stable-mx6/tools/gator/daemon/libsensors/init.c
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/init.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/init.c 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,341 @@
++/*
++ init.c - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++ Copyright (C) 2007, 2009 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++/*** This file modified by ARM on Jan 23, 2013 to cast alphasort to supress a warning as it's prototype is different on android. ***/
++
++/* Needed for scandir() and alphasort() */
++#define _BSD_SOURCE
++
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <locale.h>
++#include <stdlib.h>
++#include <stdio.h>
++#include <string.h>
++#include <errno.h>
++#include <dirent.h>
++#include <unistd.h>
++#include "sensors.h"
++#include "data.h"
++#include "error.h"
++#include "access.h"
++#include "conf.h"
++#include "sysfs.h"
++#include "scanner.h"
++#include "init.h"
++
++#define DEFAULT_CONFIG_FILE ETCDIR "/sensors3.conf"
++#define ALT_CONFIG_FILE ETCDIR "/sensors.conf"
++#define DEFAULT_CONFIG_DIR ETCDIR "/sensors.d"
++
++/* Wrapper around sensors_yyparse(), which clears the locale so that
++ the decimal numbers are always parsed properly. */
++static int sensors_parse(void)
++{
++ int res;
++ char *locale;
++
++ /* Remember the current locale and clear it */
++ locale = setlocale(LC_ALL, NULL);
++ if (locale) {
++ locale = strdup(locale);
++ if (!locale)
++ sensors_fatal_error(__func__, "Out of memory");
++
++ setlocale(LC_ALL, "C");
++ }
++
++ res = sensors_yyparse();
++
++ /* Restore the old locale */
++ if (locale) {
++ setlocale(LC_ALL, locale);
++ free(locale);
++ }
++
++ return res;
++}
++
++static void free_bus(sensors_bus *bus)
++{
++ free(bus->adapter);
++}
++
++static void free_config_busses(void)
++{
++ int i;
++
++ for (i = 0; i < sensors_config_busses_count; i++)
++ free_bus(&sensors_config_busses[i]);
++ free(sensors_config_busses);
++ sensors_config_busses = NULL;
++ sensors_config_busses_count = sensors_config_busses_max = 0;
++}
++
++static int parse_config(FILE *input, const char *name)
++{
++ int err;
++ char *name_copy;
++
++ if (name) {
++ /* Record configuration file name for error reporting */
++ name_copy = strdup(name);
++ if (!name_copy)
++ sensors_fatal_error(__func__, "Out of memory");
++ sensors_add_config_files(&name_copy);
++ } else
++ name_copy = NULL;
++
++ if (sensors_scanner_init(input, name_copy)) {
++ err = -SENSORS_ERR_PARSE;
++ goto exit_cleanup;
++ }
++ err = sensors_parse();
++ sensors_scanner_exit();
++ if (err) {
++ err = -SENSORS_ERR_PARSE;
++ goto exit_cleanup;
++ }
++
++ err = sensors_substitute_busses();
++
++exit_cleanup:
++ free_config_busses();
++ return err;
++}
++
++static int config_file_filter(const struct dirent *entry)
++{
++ return entry->d_name[0] != '.'; /* Skip hidden files */
++}
++
++static int add_config_from_dir(const char *dir)
++{
++ int count, res, i;
++ struct dirent **namelist;
++
++ count = scandir(dir, &namelist, config_file_filter, (int (*)(const struct dirent **, const struct dirent **))alphasort);
++ if (count < 0) {
++ /* Do not return an error if directory does not exist */
++ if (errno == ENOENT)
++ return 0;
++
++ sensors_parse_error_wfn(strerror(errno), NULL, 0);
++ return -SENSORS_ERR_PARSE;
++ }
++
++ for (res = 0, i = 0; !res && i < count; i++) {
++ int len;
++ char path[PATH_MAX];
++ FILE *input;
++ struct stat st;
++
++ len = snprintf(path, sizeof(path), "%s/%s", dir,
++ namelist[i]->d_name);
++ if (len < 0 || len >= (int)sizeof(path)) {
++ res = -SENSORS_ERR_PARSE;
++ continue;
++ }
++
++ /* Only accept regular files */
++ if (stat(path, &st) < 0 || !S_ISREG(st.st_mode))
++ continue;
++
++ input = fopen(path, "r");
++ if (input) {
++ res = parse_config(input, path);
++ fclose(input);
++ } else {
++ res = -SENSORS_ERR_PARSE;
++ sensors_parse_error_wfn(strerror(errno), path, 0);
++ }
++ }
++
++ /* Free memory allocated by scandir() */
++ for (i = 0; i < count; i++)
++ free(namelist[i]);
++ free(namelist);
++
++ return res;
++}
++
++int sensors_init(FILE *input)
++{
++ int res;
++
++ if (!sensors_init_sysfs())
++ return -SENSORS_ERR_KERNEL;
++ if ((res = sensors_read_sysfs_bus()) ||
++ (res = sensors_read_sysfs_chips()))
++ goto exit_cleanup;
++
++ if (input) {
++ res = parse_config(input, NULL);
++ if (res)
++ goto exit_cleanup;
++ } else {
++ const char* name;
++
++ /* No configuration provided, use default */
++ input = fopen(name = DEFAULT_CONFIG_FILE, "r");
++ if (!input && errno == ENOENT)
++ input = fopen(name = ALT_CONFIG_FILE, "r");
++ if (input) {
++ res = parse_config(input, name);
++ fclose(input);
++ if (res)
++ goto exit_cleanup;
++
++ } else if (errno != ENOENT) {
++ sensors_parse_error_wfn(strerror(errno), name, 0);
++ res = -SENSORS_ERR_PARSE;
++ goto exit_cleanup;
++ }
++
++ /* Also check for files in default directory */
++ res = add_config_from_dir(DEFAULT_CONFIG_DIR);
++ if (res)
++ goto exit_cleanup;
++ }
++
++ return 0;
++
++exit_cleanup:
++ sensors_cleanup();
++ return res;
++}
++
++static void free_chip_name(sensors_chip_name *name)
++{
++ free(name->prefix);
++ free(name->path);
++}
++
++static void free_chip_features(sensors_chip_features *features)
++{
++ int i;
++
++ for (i = 0; i < features->subfeature_count; i++)
++ free(features->subfeature[i].name);
++ free(features->subfeature);
++ for (i = 0; i < features->feature_count; i++)
++ free(features->feature[i].name);
++ free(features->feature);
++}
++
++static void free_label(sensors_label *label)
++{
++ free(label->name);
++ free(label->value);
++}
++
++void sensors_free_expr(sensors_expr *expr)
++{
++ if (expr->kind == sensors_kind_var)
++ free(expr->data.var);
++ else if (expr->kind == sensors_kind_sub) {
++ if (expr->data.subexpr.sub1)
++ sensors_free_expr(expr->data.subexpr.sub1);
++ if (expr->data.subexpr.sub2)
++ sensors_free_expr(expr->data.subexpr.sub2);
++ }
++ free(expr);
++}
++
++static void free_set(sensors_set *set)
++{
++ free(set->name);
++ sensors_free_expr(set->value);
++}
++
++static void free_compute(sensors_compute *compute)
++{
++ free(compute->name);
++ sensors_free_expr(compute->from_proc);
++ sensors_free_expr(compute->to_proc);
++}
++
++static void free_ignore(sensors_ignore *ignore)
++{
++ free(ignore->name);
++}
++
++static void free_chip(sensors_chip *chip)
++{
++ int i;
++
++ for (i = 0; i < chip->chips.fits_count; i++)
++ free_chip_name(&chip->chips.fits[i]);
++ free(chip->chips.fits);
++ chip->chips.fits_count = chip->chips.fits_max = 0;
++
++ for (i = 0; i < chip->labels_count; i++)
++ free_label(&chip->labels[i]);
++ free(chip->labels);
++ chip->labels_count = chip->labels_max = 0;
++
++ for (i = 0; i < chip->sets_count; i++)
++ free_set(&chip->sets[i]);
++ free(chip->sets);
++ chip->sets_count = chip->sets_max = 0;
++
++ for (i = 0; i < chip->computes_count; i++)
++ free_compute(&chip->computes[i]);
++ free(chip->computes);
++ chip->computes_count = chip->computes_max = 0;
++
++ for (i = 0; i < chip->ignores_count; i++)
++ free_ignore(&chip->ignores[i]);
++ free(chip->ignores);
++ chip->ignores_count = chip->ignores_max = 0;
++}
++
++void sensors_cleanup(void)
++{
++ int i;
++
++ for (i = 0; i < sensors_proc_chips_count; i++) {
++ free_chip_name(&sensors_proc_chips[i].chip);
++ free_chip_features(&sensors_proc_chips[i]);
++ }
++ free(sensors_proc_chips);
++ sensors_proc_chips = NULL;
++ sensors_proc_chips_count = sensors_proc_chips_max = 0;
++
++ for (i = 0; i < sensors_config_chips_count; i++)
++ free_chip(&sensors_config_chips[i]);
++ free(sensors_config_chips);
++ sensors_config_chips = NULL;
++ sensors_config_chips_count = sensors_config_chips_max = 0;
++ sensors_config_chips_subst = 0;
++
++ for (i = 0; i < sensors_proc_bus_count; i++)
++ free_bus(&sensors_proc_bus[i]);
++ free(sensors_proc_bus);
++ sensors_proc_bus = NULL;
++ sensors_proc_bus_count = sensors_proc_bus_max = 0;
++
++ for (i = 0; i < sensors_config_files_count; i++)
++ free(sensors_config_files[i]);
++ free(sensors_config_files);
++ sensors_config_files = NULL;
++ sensors_config_files_count = sensors_config_files_max = 0;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/init.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/init.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/init.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/init.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,28 @@
++/*
++ init.h - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#ifndef LIB_SENSORS_INIT_H
++#define LIB_SENSORS_INIT_H
++
++#include "data.h"
++
++void sensors_free_expr(sensors_expr *expr);
++
++#endif /* def LIB_SENSORS_INIT_H */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/scanner.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/scanner.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/scanner.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/scanner.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,32 @@
++/*
++ scanner.h - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 2006 Mark M. Hoffman <mhoffman@lightlink.com>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++/*** This file modified by ARM on Jan 23, 2013 to fix input defined but not used warning from conf-lex.c. ***/
++
++#ifndef LIB_SENSORS_SCANNER_H
++#define LIB_SENSORS_SCANNER_H
++
++int sensors_scanner_init(FILE *input, const char *filename);
++void sensors_scanner_exit(void);
++
++#define YY_NO_INPUT
++
++#endif
++
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/sensors.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/sensors.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/sensors.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/sensors.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,311 @@
++/*
++ sensors.h - Part of libsensors, a Linux library for reading sensor data.
++ Copyright (c) 1998, 1999 Frodo Looijaard <frodol@dds.nl>
++ Copyright (C) 2007, 2010 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++/*** This file modified by ARM on Jan 23, 2013 to read non-scaled values. ***/
++
++#ifndef LIB_SENSORS_SENSORS_H
++#define LIB_SENSORS_SENSORS_H
++
++#include <stdio.h>
++#include <limits.h>
++
++/* Publicly accessible library functions */
++
++/* libsensors API version define, first digit is the major version (changed
++ when the API + ABI breaks), the third digit is incremented to track small
++ API additions like new flags / enum values. The second digit is for tracking
++ larger additions like new methods. */
++#define SENSORS_API_VERSION 0x432
++
++#define SENSORS_CHIP_NAME_PREFIX_ANY NULL
++#define SENSORS_CHIP_NAME_ADDR_ANY (-1)
++
++#define SENSORS_BUS_TYPE_ANY (-1)
++#define SENSORS_BUS_TYPE_I2C 0
++#define SENSORS_BUS_TYPE_ISA 1
++#define SENSORS_BUS_TYPE_PCI 2
++#define SENSORS_BUS_TYPE_SPI 3
++#define SENSORS_BUS_TYPE_VIRTUAL 4
++#define SENSORS_BUS_TYPE_ACPI 5
++#define SENSORS_BUS_TYPE_HID 6
++#define SENSORS_BUS_NR_ANY (-1)
++#define SENSORS_BUS_NR_IGNORE (-2)
++
++#ifdef __cplusplus
++extern "C" {
++#endif /* __cplusplus */
++
++extern const char *libsensors_version;
++
++extern int sensors_sysfs_no_scaling;
++
++typedef struct sensors_bus_id {
++ short type;
++ short nr;
++} sensors_bus_id;
++
++/* A chip name is encoded in this structure */
++typedef struct sensors_chip_name {
++ char *prefix;
++ sensors_bus_id bus;
++ int addr;
++ char *path;
++} sensors_chip_name;
++
++/* Load the configuration file and the detected chips list. If this
++ returns a value unequal to zero, you are in trouble; you can not
++ assume anything will be initialized properly. If you want to
++ reload the configuration file, call sensors_cleanup() below before
++ calling sensors_init() again. */
++int sensors_init(FILE *input);
++
++/* Clean-up function: You can't access anything after
++ this, until the next sensors_init() call! */
++void sensors_cleanup(void);
++
++/* Parse a chip name to the internal representation. Return 0 on success, <0
++ on error. */
++int sensors_parse_chip_name(const char *orig_name, sensors_chip_name *res);
++
++/* Free memory allocated for the internal representation of a chip name. */
++void sensors_free_chip_name(sensors_chip_name *chip);
++
++/* Print a chip name from its internal representation. Note that chip should
++ not contain wildcard values! Return the number of characters printed on
++ success (same as snprintf), <0 on error. */
++int sensors_snprintf_chip_name(char *str, size_t size,
++ const sensors_chip_name *chip);
++
++/* This function returns the adapter name of a bus,
++ as used within the sensors_chip_name structure. If it could not be found,
++ it returns NULL */
++const char *sensors_get_adapter_name(const sensors_bus_id *bus);
++
++typedef struct sensors_feature sensors_feature;
++
++/* Look up the label for a given feature. Note that chip should not
++ contain wildcard values! The returned string is newly allocated (free it
++ yourself). On failure, NULL is returned.
++ If no label exists for this feature, its name is returned itself. */
++char *sensors_get_label(const sensors_chip_name *name,
++ const sensors_feature *feature);
++
++/* Read the value of a subfeature of a certain chip. Note that chip should not
++ contain wildcard values! This function will return 0 on success, and <0
++ on failure. */
++int sensors_get_value(const sensors_chip_name *name, int subfeat_nr,
++ double *value);
++
++/* Set the value of a subfeature of a certain chip. Note that chip should not
++ contain wildcard values! This function will return 0 on success, and <0
++ on failure. */
++int sensors_set_value(const sensors_chip_name *name, int subfeat_nr,
++ double value);
++
++/* Execute all set statements for this particular chip. The chip may contain
++ wildcards! This function will return 0 on success, and <0 on failure. */
++int sensors_do_chip_sets(const sensors_chip_name *name);
++
++/* This function returns all detected chips that match a given chip name,
++ one by one. If no chip name is provided, all detected chips are returned.
++ To start at the beginning of the list, use 0 for nr; NULL is returned if
++ we are at the end of the list. Do not try to change these chip names, as
++ they point to internal structures! */
++const sensors_chip_name *sensors_get_detected_chips(const sensors_chip_name
++ *match, int *nr);
++
++/* These defines are used in the flags field of sensors_subfeature */
++#define SENSORS_MODE_R 1
++#define SENSORS_MODE_W 2
++#define SENSORS_COMPUTE_MAPPING 4
++
++typedef enum sensors_feature_type {
++ SENSORS_FEATURE_IN = 0x00,
++ SENSORS_FEATURE_FAN = 0x01,
++ SENSORS_FEATURE_TEMP = 0x02,
++ SENSORS_FEATURE_POWER = 0x03,
++ SENSORS_FEATURE_ENERGY = 0x04,
++ SENSORS_FEATURE_CURR = 0x05,
++ SENSORS_FEATURE_HUMIDITY = 0x06,
++ SENSORS_FEATURE_MAX_MAIN,
++ SENSORS_FEATURE_VID = 0x10,
++ SENSORS_FEATURE_INTRUSION = 0x11,
++ SENSORS_FEATURE_MAX_OTHER,
++ SENSORS_FEATURE_BEEP_ENABLE = 0x18,
++ SENSORS_FEATURE_UNKNOWN = INT_MAX,
++} sensors_feature_type;
++
++/* All the sensor types (in, fan, temp, vid) are a multiple of 0x100 apart,
++ and sensor subfeatures which have no compute mapping have bit 7 set. */
++typedef enum sensors_subfeature_type {
++ SENSORS_SUBFEATURE_IN_INPUT = SENSORS_FEATURE_IN << 8,
++ SENSORS_SUBFEATURE_IN_MIN,
++ SENSORS_SUBFEATURE_IN_MAX,
++ SENSORS_SUBFEATURE_IN_LCRIT,
++ SENSORS_SUBFEATURE_IN_CRIT,
++ SENSORS_SUBFEATURE_IN_AVERAGE,
++ SENSORS_SUBFEATURE_IN_LOWEST,
++ SENSORS_SUBFEATURE_IN_HIGHEST,
++ SENSORS_SUBFEATURE_IN_ALARM = (SENSORS_FEATURE_IN << 8) | 0x80,
++ SENSORS_SUBFEATURE_IN_MIN_ALARM,
++ SENSORS_SUBFEATURE_IN_MAX_ALARM,
++ SENSORS_SUBFEATURE_IN_BEEP,
++ SENSORS_SUBFEATURE_IN_LCRIT_ALARM,
++ SENSORS_SUBFEATURE_IN_CRIT_ALARM,
++
++ SENSORS_SUBFEATURE_FAN_INPUT = SENSORS_FEATURE_FAN << 8,
++ SENSORS_SUBFEATURE_FAN_MIN,
++ SENSORS_SUBFEATURE_FAN_MAX,
++ SENSORS_SUBFEATURE_FAN_ALARM = (SENSORS_FEATURE_FAN << 8) | 0x80,
++ SENSORS_SUBFEATURE_FAN_FAULT,
++ SENSORS_SUBFEATURE_FAN_DIV,
++ SENSORS_SUBFEATURE_FAN_BEEP,
++ SENSORS_SUBFEATURE_FAN_PULSES,
++ SENSORS_SUBFEATURE_FAN_MIN_ALARM,
++ SENSORS_SUBFEATURE_FAN_MAX_ALARM,
++
++ SENSORS_SUBFEATURE_TEMP_INPUT = SENSORS_FEATURE_TEMP << 8,
++ SENSORS_SUBFEATURE_TEMP_MAX,
++ SENSORS_SUBFEATURE_TEMP_MAX_HYST,
++ SENSORS_SUBFEATURE_TEMP_MIN,
++ SENSORS_SUBFEATURE_TEMP_CRIT,
++ SENSORS_SUBFEATURE_TEMP_CRIT_HYST,
++ SENSORS_SUBFEATURE_TEMP_LCRIT,
++ SENSORS_SUBFEATURE_TEMP_EMERGENCY,
++ SENSORS_SUBFEATURE_TEMP_EMERGENCY_HYST,
++ SENSORS_SUBFEATURE_TEMP_LOWEST,
++ SENSORS_SUBFEATURE_TEMP_HIGHEST,
++ SENSORS_SUBFEATURE_TEMP_ALARM = (SENSORS_FEATURE_TEMP << 8) | 0x80,
++ SENSORS_SUBFEATURE_TEMP_MAX_ALARM,
++ SENSORS_SUBFEATURE_TEMP_MIN_ALARM,
++ SENSORS_SUBFEATURE_TEMP_CRIT_ALARM,
++ SENSORS_SUBFEATURE_TEMP_FAULT,
++ SENSORS_SUBFEATURE_TEMP_TYPE,
++ SENSORS_SUBFEATURE_TEMP_OFFSET,
++ SENSORS_SUBFEATURE_TEMP_BEEP,
++ SENSORS_SUBFEATURE_TEMP_EMERGENCY_ALARM,
++ SENSORS_SUBFEATURE_TEMP_LCRIT_ALARM,
++
++ SENSORS_SUBFEATURE_POWER_AVERAGE = SENSORS_FEATURE_POWER << 8,
++ SENSORS_SUBFEATURE_POWER_AVERAGE_HIGHEST,
++ SENSORS_SUBFEATURE_POWER_AVERAGE_LOWEST,
++ SENSORS_SUBFEATURE_POWER_INPUT,
++ SENSORS_SUBFEATURE_POWER_INPUT_HIGHEST,
++ SENSORS_SUBFEATURE_POWER_INPUT_LOWEST,
++ SENSORS_SUBFEATURE_POWER_CAP,
++ SENSORS_SUBFEATURE_POWER_CAP_HYST,
++ SENSORS_SUBFEATURE_POWER_MAX,
++ SENSORS_SUBFEATURE_POWER_CRIT,
++ SENSORS_SUBFEATURE_POWER_AVERAGE_INTERVAL = (SENSORS_FEATURE_POWER << 8) | 0x80,
++ SENSORS_SUBFEATURE_POWER_ALARM,
++ SENSORS_SUBFEATURE_POWER_CAP_ALARM,
++ SENSORS_SUBFEATURE_POWER_MAX_ALARM,
++ SENSORS_SUBFEATURE_POWER_CRIT_ALARM,
++
++ SENSORS_SUBFEATURE_ENERGY_INPUT = SENSORS_FEATURE_ENERGY << 8,
++
++ SENSORS_SUBFEATURE_CURR_INPUT = SENSORS_FEATURE_CURR << 8,
++ SENSORS_SUBFEATURE_CURR_MIN,
++ SENSORS_SUBFEATURE_CURR_MAX,
++ SENSORS_SUBFEATURE_CURR_LCRIT,
++ SENSORS_SUBFEATURE_CURR_CRIT,
++ SENSORS_SUBFEATURE_CURR_AVERAGE,
++ SENSORS_SUBFEATURE_CURR_LOWEST,
++ SENSORS_SUBFEATURE_CURR_HIGHEST,
++ SENSORS_SUBFEATURE_CURR_ALARM = (SENSORS_FEATURE_CURR << 8) | 0x80,
++ SENSORS_SUBFEATURE_CURR_MIN_ALARM,
++ SENSORS_SUBFEATURE_CURR_MAX_ALARM,
++ SENSORS_SUBFEATURE_CURR_BEEP,
++ SENSORS_SUBFEATURE_CURR_LCRIT_ALARM,
++ SENSORS_SUBFEATURE_CURR_CRIT_ALARM,
++
++ SENSORS_SUBFEATURE_HUMIDITY_INPUT = SENSORS_FEATURE_HUMIDITY << 8,
++
++ SENSORS_SUBFEATURE_VID = SENSORS_FEATURE_VID << 8,
++
++ SENSORS_SUBFEATURE_INTRUSION_ALARM = SENSORS_FEATURE_INTRUSION << 8,
++ SENSORS_SUBFEATURE_INTRUSION_BEEP,
++
++ SENSORS_SUBFEATURE_BEEP_ENABLE = SENSORS_FEATURE_BEEP_ENABLE << 8,
++
++ SENSORS_SUBFEATURE_UNKNOWN = INT_MAX,
++} sensors_subfeature_type;
++
++/* Data about a single chip feature (or category leader) */
++struct sensors_feature {
++ char *name;
++ int number;
++ sensors_feature_type type;
++ /* Members below are for libsensors internal use only */
++ int first_subfeature;
++ int padding1;
++};
++
++/* Data about a single chip subfeature:
++ name is the string name used to refer to this subfeature (in config files)
++ number is the internal subfeature number, used in many functions to refer
++ to this subfeature
++ type is the subfeature type
++ mapping is the number of a main feature this subfeature belongs to
++ (for example subfeatures fan1_input, fan1_min, fan1_div and fan1_alarm
++ are mapped to main feature fan1)
++ flags is a bitfield, its value is a combination of SENSORS_MODE_R (readable),
++ SENSORS_MODE_W (writable) and SENSORS_COMPUTE_MAPPING (affected by the
++ computation rules of the main feature) */
++typedef struct sensors_subfeature {
++ char *name;
++ int number;
++ sensors_subfeature_type type;
++ int mapping;
++ unsigned int flags;
++} sensors_subfeature;
++
++/* This returns all main features of a specific chip. nr is an internally
++ used variable. Set it to zero to start at the begin of the list. If no
++ more features are found NULL is returned.
++ Do not try to change the returned structure; you will corrupt internal
++ data structures. */
++const sensors_feature *
++sensors_get_features(const sensors_chip_name *name, int *nr);
++
++/* This returns all subfeatures of a given main feature. nr is an internally
++ used variable. Set it to zero to start at the begin of the list. If no
++ more features are found NULL is returned.
++ Do not try to change the returned structure; you will corrupt internal
++ data structures. */
++const sensors_subfeature *
++sensors_get_all_subfeatures(const sensors_chip_name *name,
++ const sensors_feature *feature, int *nr);
++
++/* This returns the subfeature of the given type for a given main feature,
++ if it exists, NULL otherwise.
++ Do not try to change the returned structure; you will corrupt internal
++ data structures. */
++const sensors_subfeature *
++sensors_get_subfeature(const sensors_chip_name *name,
++ const sensors_feature *feature,
++ sensors_subfeature_type type);
++
++#ifdef __cplusplus
++}
++#endif /* __cplusplus */
++
++#endif /* def LIB_SENSORS_ERROR_H */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/sysfs.c linux-linaro-stable-mx6/tools/gator/daemon/libsensors/sysfs.c
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/sysfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/sysfs.c 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,926 @@
++/*
++ sysfs.c - Part of libsensors, a library for reading Linux sensor data
++ Copyright (c) 2005 Mark M. Hoffman <mhoffman@lightlink.com>
++ Copyright (C) 2007-2010 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++/*** This file modified by ARM on Jan 23, 2013 to improve performance by substituting calls to fread() with calls to read() and to read non-scaled values. ***/
++
++/* this define needed for strndup() */
++#define _GNU_SOURCE
++
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <sys/vfs.h>
++#include <unistd.h>
++#include <string.h>
++#include <stdlib.h>
++#include <limits.h>
++#include <errno.h>
++#include <dirent.h>
++#include <fcntl.h>
++#include "data.h"
++#include "error.h"
++#include "access.h"
++#include "general.h"
++#include "sysfs.h"
++
++
++/****************************************************************************/
++
++#define ATTR_MAX 128
++#define SYSFS_MAGIC 0x62656572
++
++int sensors_sysfs_no_scaling;
++
++/*
++ * Read an attribute from sysfs
++ * Returns a pointer to a freshly allocated string; free it yourself.
++ * If the file doesn't exist or can't be read, NULL is returned.
++ */
++static char *sysfs_read_attr(const char *device, const char *attr)
++{
++ char path[NAME_MAX];
++ char buf[ATTR_MAX], *p;
++ FILE *f;
++
++ snprintf(path, NAME_MAX, "%s/%s", device, attr);
++
++ if (!(f = fopen(path, "r")))
++ return NULL;
++ p = fgets(buf, ATTR_MAX, f);
++ fclose(f);
++ if (!p)
++ return NULL;
++
++ /* Last byte is a '\n'; chop that off */
++ p = strndup(buf, strlen(buf) - 1);
++ if (!p)
++ sensors_fatal_error(__func__, "Out of memory");
++ return p;
++}
++
++/*
++ * Call an arbitrary function for each class device of the given class
++ * Returns 0 on success (all calls returned 0), a positive errno for
++ * local errors, or a negative error value if any call fails.
++ */
++static int sysfs_foreach_classdev(const char *class_name,
++ int (*func)(const char *, const char *))
++{
++ char path[NAME_MAX];
++ int path_off, ret;
++ DIR *dir;
++ struct dirent *ent;
++
++ path_off = snprintf(path, NAME_MAX, "%s/class/%s",
++ sensors_sysfs_mount, class_name);
++ if (!(dir = opendir(path)))
++ return errno;
++
++ ret = 0;
++ while (!ret && (ent = readdir(dir))) {
++ if (ent->d_name[0] == '.') /* skip hidden entries */
++ continue;
++
++ snprintf(path + path_off, NAME_MAX - path_off, "/%s",
++ ent->d_name);
++ ret = func(path, ent->d_name);
++ }
++
++ closedir(dir);
++ return ret;
++}
++
++/*
++ * Call an arbitrary function for each device of the given bus type
++ * Returns 0 on success (all calls returned 0), a positive errno for
++ * local errors, or a negative error value if any call fails.
++ */
++static int sysfs_foreach_busdev(const char *bus_type,
++ int (*func)(const char *, const char *))
++{
++ char path[NAME_MAX];
++ int path_off, ret;
++ DIR *dir;
++ struct dirent *ent;
++
++ path_off = snprintf(path, NAME_MAX, "%s/bus/%s/devices",
++ sensors_sysfs_mount, bus_type);
++ if (!(dir = opendir(path)))
++ return errno;
++
++ ret = 0;
++ while (!ret && (ent = readdir(dir))) {
++ if (ent->d_name[0] == '.') /* skip hidden entries */
++ continue;
++
++ snprintf(path + path_off, NAME_MAX - path_off, "/%s",
++ ent->d_name);
++ ret = func(path, ent->d_name);
++ }
++
++ closedir(dir);
++ return ret;
++}
++
++/****************************************************************************/
++
++char sensors_sysfs_mount[NAME_MAX];
++
++#define MAX_MAIN_SENSOR_TYPES (SENSORS_FEATURE_MAX_MAIN - SENSORS_FEATURE_IN)
++#define MAX_OTHER_SENSOR_TYPES (SENSORS_FEATURE_MAX_OTHER - SENSORS_FEATURE_VID)
++#define MAX_SENSORS_PER_TYPE 24
++/* max_subfeatures is now computed dynamically */
++#define FEATURE_SIZE (max_subfeatures * 2)
++#define FEATURE_TYPE_SIZE (MAX_SENSORS_PER_TYPE * FEATURE_SIZE)
++
++/*
++ * Room for all 7 main types (in, fan, temp, power, energy, current, humidity)
++ * and 2 other types (VID, intrusion) with all their subfeatures + misc features
++ */
++#define SUB_OFFSET_OTHER (MAX_MAIN_SENSOR_TYPES * FEATURE_TYPE_SIZE)
++#define SUB_OFFSET_MISC (SUB_OFFSET_OTHER + \
++ MAX_OTHER_SENSOR_TYPES * FEATURE_TYPE_SIZE)
++#define ALL_POSSIBLE_SUBFEATURES (SUB_OFFSET_MISC + 1)
++
++static
++int get_type_scaling(sensors_subfeature_type type)
++{
++ /* Multipliers for subfeatures */
++ switch (type & 0xFF80) {
++ case SENSORS_SUBFEATURE_IN_INPUT:
++ case SENSORS_SUBFEATURE_TEMP_INPUT:
++ case SENSORS_SUBFEATURE_CURR_INPUT:
++ case SENSORS_SUBFEATURE_HUMIDITY_INPUT:
++ return 1000;
++ case SENSORS_SUBFEATURE_FAN_INPUT:
++ return 1;
++ case SENSORS_SUBFEATURE_POWER_AVERAGE:
++ case SENSORS_SUBFEATURE_ENERGY_INPUT:
++ return 1000000;
++ }
++
++ /* Multipliers for second class subfeatures
++ that need their own multiplier */
++ switch (type) {
++ case SENSORS_SUBFEATURE_POWER_AVERAGE_INTERVAL:
++ case SENSORS_SUBFEATURE_VID:
++ case SENSORS_SUBFEATURE_TEMP_OFFSET:
++ return 1000;
++ default:
++ return 1;
++ }
++}
++
++static
++char *get_feature_name(sensors_feature_type ftype, char *sfname)
++{
++ char *name, *underscore;
++
++ switch (ftype) {
++ case SENSORS_FEATURE_IN:
++ case SENSORS_FEATURE_FAN:
++ case SENSORS_FEATURE_TEMP:
++ case SENSORS_FEATURE_POWER:
++ case SENSORS_FEATURE_ENERGY:
++ case SENSORS_FEATURE_CURR:
++ case SENSORS_FEATURE_HUMIDITY:
++ case SENSORS_FEATURE_INTRUSION:
++ underscore = strchr(sfname, '_');
++ name = strndup(sfname, underscore - sfname);
++ if (!name)
++ sensors_fatal_error(__func__, "Out of memory");
++
++ break;
++ default:
++ name = strdup(sfname);
++ if (!name)
++ sensors_fatal_error(__func__, "Out of memory");
++ }
++
++ return name;
++}
++
++/* Static mappings for use by sensors_subfeature_get_type() */
++struct subfeature_type_match
++{
++ const char *name;
++ sensors_subfeature_type type;
++};
++
++struct feature_type_match
++{
++ const char *name;
++ const struct subfeature_type_match *submatches;
++};
++
++static const struct subfeature_type_match temp_matches[] = {
++ { "input", SENSORS_SUBFEATURE_TEMP_INPUT },
++ { "max", SENSORS_SUBFEATURE_TEMP_MAX },
++ { "max_hyst", SENSORS_SUBFEATURE_TEMP_MAX_HYST },
++ { "min", SENSORS_SUBFEATURE_TEMP_MIN },
++ { "crit", SENSORS_SUBFEATURE_TEMP_CRIT },
++ { "crit_hyst", SENSORS_SUBFEATURE_TEMP_CRIT_HYST },
++ { "lcrit", SENSORS_SUBFEATURE_TEMP_LCRIT },
++ { "emergency", SENSORS_SUBFEATURE_TEMP_EMERGENCY },
++ { "emergency_hyst", SENSORS_SUBFEATURE_TEMP_EMERGENCY_HYST },
++ { "lowest", SENSORS_SUBFEATURE_TEMP_LOWEST },
++ { "highest", SENSORS_SUBFEATURE_TEMP_HIGHEST },
++ { "alarm", SENSORS_SUBFEATURE_TEMP_ALARM },
++ { "min_alarm", SENSORS_SUBFEATURE_TEMP_MIN_ALARM },
++ { "max_alarm", SENSORS_SUBFEATURE_TEMP_MAX_ALARM },
++ { "crit_alarm", SENSORS_SUBFEATURE_TEMP_CRIT_ALARM },
++ { "emergency_alarm", SENSORS_SUBFEATURE_TEMP_EMERGENCY_ALARM },
++ { "lcrit_alarm", SENSORS_SUBFEATURE_TEMP_LCRIT_ALARM },
++ { "fault", SENSORS_SUBFEATURE_TEMP_FAULT },
++ { "type", SENSORS_SUBFEATURE_TEMP_TYPE },
++ { "offset", SENSORS_SUBFEATURE_TEMP_OFFSET },
++ { "beep", SENSORS_SUBFEATURE_TEMP_BEEP },
++ { NULL, 0 }
++};
++
++static const struct subfeature_type_match in_matches[] = {
++ { "input", SENSORS_SUBFEATURE_IN_INPUT },
++ { "min", SENSORS_SUBFEATURE_IN_MIN },
++ { "max", SENSORS_SUBFEATURE_IN_MAX },
++ { "lcrit", SENSORS_SUBFEATURE_IN_LCRIT },
++ { "crit", SENSORS_SUBFEATURE_IN_CRIT },
++ { "average", SENSORS_SUBFEATURE_IN_AVERAGE },
++ { "lowest", SENSORS_SUBFEATURE_IN_LOWEST },
++ { "highest", SENSORS_SUBFEATURE_IN_HIGHEST },
++ { "alarm", SENSORS_SUBFEATURE_IN_ALARM },
++ { "min_alarm", SENSORS_SUBFEATURE_IN_MIN_ALARM },
++ { "max_alarm", SENSORS_SUBFEATURE_IN_MAX_ALARM },
++ { "lcrit_alarm", SENSORS_SUBFEATURE_IN_LCRIT_ALARM },
++ { "crit_alarm", SENSORS_SUBFEATURE_IN_CRIT_ALARM },
++ { "beep", SENSORS_SUBFEATURE_IN_BEEP },
++ { NULL, 0 }
++};
++
++static const struct subfeature_type_match fan_matches[] = {
++ { "input", SENSORS_SUBFEATURE_FAN_INPUT },
++ { "min", SENSORS_SUBFEATURE_FAN_MIN },
++ { "max", SENSORS_SUBFEATURE_FAN_MAX },
++ { "div", SENSORS_SUBFEATURE_FAN_DIV },
++ { "pulses", SENSORS_SUBFEATURE_FAN_PULSES },
++ { "alarm", SENSORS_SUBFEATURE_FAN_ALARM },
++ { "min_alarm", SENSORS_SUBFEATURE_FAN_MIN_ALARM },
++ { "max_alarm", SENSORS_SUBFEATURE_FAN_MAX_ALARM },
++ { "fault", SENSORS_SUBFEATURE_FAN_FAULT },
++ { "beep", SENSORS_SUBFEATURE_FAN_BEEP },
++ { NULL, 0 }
++};
++
++static const struct subfeature_type_match power_matches[] = {
++ { "average", SENSORS_SUBFEATURE_POWER_AVERAGE },
++ { "average_highest", SENSORS_SUBFEATURE_POWER_AVERAGE_HIGHEST },
++ { "average_lowest", SENSORS_SUBFEATURE_POWER_AVERAGE_LOWEST },
++ { "input", SENSORS_SUBFEATURE_POWER_INPUT },
++ { "input_highest", SENSORS_SUBFEATURE_POWER_INPUT_HIGHEST },
++ { "input_lowest", SENSORS_SUBFEATURE_POWER_INPUT_LOWEST },
++ { "cap", SENSORS_SUBFEATURE_POWER_CAP },
++ { "cap_hyst", SENSORS_SUBFEATURE_POWER_CAP_HYST },
++ { "cap_alarm", SENSORS_SUBFEATURE_POWER_CAP_ALARM },
++ { "alarm", SENSORS_SUBFEATURE_POWER_ALARM },
++ { "max", SENSORS_SUBFEATURE_POWER_MAX },
++ { "max_alarm", SENSORS_SUBFEATURE_POWER_MAX_ALARM },
++ { "crit", SENSORS_SUBFEATURE_POWER_CRIT },
++ { "crit_alarm", SENSORS_SUBFEATURE_POWER_CRIT_ALARM },
++ { "average_interval", SENSORS_SUBFEATURE_POWER_AVERAGE_INTERVAL },
++ { NULL, 0 }
++};
++
++static const struct subfeature_type_match energy_matches[] = {
++ { "input", SENSORS_SUBFEATURE_ENERGY_INPUT },
++ { NULL, 0 }
++};
++
++static const struct subfeature_type_match curr_matches[] = {
++ { "input", SENSORS_SUBFEATURE_CURR_INPUT },
++ { "min", SENSORS_SUBFEATURE_CURR_MIN },
++ { "max", SENSORS_SUBFEATURE_CURR_MAX },
++ { "lcrit", SENSORS_SUBFEATURE_CURR_LCRIT },
++ { "crit", SENSORS_SUBFEATURE_CURR_CRIT },
++ { "average", SENSORS_SUBFEATURE_CURR_AVERAGE },
++ { "lowest", SENSORS_SUBFEATURE_CURR_LOWEST },
++ { "highest", SENSORS_SUBFEATURE_CURR_HIGHEST },
++ { "alarm", SENSORS_SUBFEATURE_CURR_ALARM },
++ { "min_alarm", SENSORS_SUBFEATURE_CURR_MIN_ALARM },
++ { "max_alarm", SENSORS_SUBFEATURE_CURR_MAX_ALARM },
++ { "lcrit_alarm", SENSORS_SUBFEATURE_CURR_LCRIT_ALARM },
++ { "crit_alarm", SENSORS_SUBFEATURE_CURR_CRIT_ALARM },
++ { "beep", SENSORS_SUBFEATURE_CURR_BEEP },
++ { NULL, 0 }
++};
++
++static const struct subfeature_type_match humidity_matches[] = {
++ { "input", SENSORS_SUBFEATURE_HUMIDITY_INPUT },
++ { NULL, 0 }
++};
++
++static const struct subfeature_type_match cpu_matches[] = {
++ { "vid", SENSORS_SUBFEATURE_VID },
++ { NULL, 0 }
++};
++
++static const struct subfeature_type_match intrusion_matches[] = {
++ { "alarm", SENSORS_SUBFEATURE_INTRUSION_ALARM },
++ { "beep", SENSORS_SUBFEATURE_INTRUSION_BEEP },
++ { NULL, 0 }
++};
++static struct feature_type_match matches[] = {
++ { "temp%d%c", temp_matches },
++ { "in%d%c", in_matches },
++ { "fan%d%c", fan_matches },
++ { "cpu%d%c", cpu_matches },
++ { "power%d%c", power_matches },
++ { "curr%d%c", curr_matches },
++ { "energy%d%c", energy_matches },
++ { "intrusion%d%c", intrusion_matches },
++ { "humidity%d%c", humidity_matches },
++};
++
++/* Return the subfeature type and channel number based on the subfeature
++ name */
++static
++sensors_subfeature_type sensors_subfeature_get_type(const char *name, int *nr)
++{
++ char c;
++ int i, count;
++ const struct subfeature_type_match *submatches;
++
++ /* Special case */
++ if (!strcmp(name, "beep_enable")) {
++ *nr = 0;
++ return SENSORS_SUBFEATURE_BEEP_ENABLE;
++ }
++
++ for (i = 0; i < ARRAY_SIZE(matches); i++)
++ if ((count = sscanf(name, matches[i].name, nr, &c)))
++ break;
++
++ if (i == ARRAY_SIZE(matches) || count != 2 || c != '_')
++ return SENSORS_SUBFEATURE_UNKNOWN; /* no match */
++
++ submatches = matches[i].submatches;
++ name = strchr(name + 3, '_') + 1;
++ for (i = 0; submatches[i].name != NULL; i++)
++ if (!strcmp(name, submatches[i].name))
++ return submatches[i].type;
++
++ return SENSORS_SUBFEATURE_UNKNOWN;
++}
++
++static int sensors_compute_max(void)
++{
++ int i, j, max, offset;
++ const struct subfeature_type_match *submatches;
++ sensors_feature_type ftype;
++
++ max = 0;
++ for (i = 0; i < ARRAY_SIZE(matches); i++) {
++ submatches = matches[i].submatches;
++ for (j = 0; submatches[j].name != NULL; j++) {
++ ftype = submatches[j].type >> 8;
++
++ if (ftype < SENSORS_FEATURE_VID) {
++ offset = submatches[j].type & 0x7F;
++ if (offset >= max)
++ max = offset + 1;
++ } else {
++ offset = submatches[j].type & 0xFF;
++ if (offset >= max * 2)
++ max = ((offset + 1) + 1) / 2;
++ }
++ }
++ }
++
++ return max;
++}
++
++static int sensors_get_attr_mode(const char *device, const char *attr)
++{
++ char path[NAME_MAX];
++ struct stat st;
++ int mode = 0;
++
++ snprintf(path, NAME_MAX, "%s/%s", device, attr);
++ if (!stat(path, &st)) {
++ if (st.st_mode & S_IRUSR)
++ mode |= SENSORS_MODE_R;
++ if (st.st_mode & S_IWUSR)
++ mode |= SENSORS_MODE_W;
++ }
++ return mode;
++}
++
++static int sensors_read_dynamic_chip(sensors_chip_features *chip,
++ const char *dev_path)
++{
++ int i, fnum = 0, sfnum = 0, prev_slot;
++ static int max_subfeatures;
++ DIR *dir;
++ struct dirent *ent;
++ sensors_subfeature *all_subfeatures;
++ sensors_subfeature *dyn_subfeatures;
++ sensors_feature *dyn_features;
++ sensors_feature_type ftype;
++ sensors_subfeature_type sftype;
++
++ if (!(dir = opendir(dev_path)))
++ return -errno;
++
++ /* Dynamically figure out the max number of subfeatures */
++ if (!max_subfeatures)
++ max_subfeatures = sensors_compute_max();
++
++ /* We use a large sparse table at first to store all found
++ subfeatures, so that we can store them sorted at type and index
++ and then later create a dense sorted table. */
++ all_subfeatures = calloc(ALL_POSSIBLE_SUBFEATURES,
++ sizeof(sensors_subfeature));
++ if (!all_subfeatures)
++ sensors_fatal_error(__func__, "Out of memory");
++
++ while ((ent = readdir(dir))) {
++ char *name;
++ int nr;
++
++ /* Skip directories and symlinks */
++ if (ent->d_type != DT_REG)
++ continue;
++
++ name = ent->d_name;
++
++ sftype = sensors_subfeature_get_type(name, &nr);
++ if (sftype == SENSORS_SUBFEATURE_UNKNOWN)
++ continue;
++ ftype = sftype >> 8;
++
++ /* Adjust the channel number */
++ switch (ftype) {
++ case SENSORS_FEATURE_FAN:
++ case SENSORS_FEATURE_TEMP:
++ case SENSORS_FEATURE_POWER:
++ case SENSORS_FEATURE_ENERGY:
++ case SENSORS_FEATURE_CURR:
++ case SENSORS_FEATURE_HUMIDITY:
++ nr--;
++ break;
++ default:
++ break;
++ }
++
++ if (nr < 0 || nr >= MAX_SENSORS_PER_TYPE) {
++ /* More sensors of one type than MAX_SENSORS_PER_TYPE,
++ we have to ignore it */
++#ifdef DEBUG
++ sensors_fatal_error(__func__,
++ "Increase MAX_SENSORS_PER_TYPE!");
++#endif
++ continue;
++ }
++
++ /* "calculate" a place to store the subfeature in our sparse,
++ sorted table */
++ switch (ftype) {
++ case SENSORS_FEATURE_VID:
++ case SENSORS_FEATURE_INTRUSION:
++ i = SUB_OFFSET_OTHER +
++ (ftype - SENSORS_FEATURE_VID) * FEATURE_TYPE_SIZE +
++ nr * FEATURE_SIZE + (sftype & 0xFF);
++ break;
++ case SENSORS_FEATURE_BEEP_ENABLE:
++ i = SUB_OFFSET_MISC +
++ (ftype - SENSORS_FEATURE_BEEP_ENABLE);
++ break;
++ default:
++ i = ftype * FEATURE_TYPE_SIZE +
++ nr * FEATURE_SIZE +
++ ((sftype & 0x80) >> 7) * max_subfeatures +
++ (sftype & 0x7F);
++ }
++
++ if (all_subfeatures[i].name) {
++#ifdef DEBUG
++ sensors_fatal_error(__func__, "Duplicate subfeature");
++#endif
++ continue;
++ }
++
++ /* fill in the subfeature members */
++ all_subfeatures[i].type = sftype;
++ all_subfeatures[i].name = strdup(name);
++ if (!all_subfeatures[i].name)
++ sensors_fatal_error(__func__, "Out of memory");
++
++ /* Other and misc subfeatures are never scaled */
++ if (sftype < SENSORS_SUBFEATURE_VID && !(sftype & 0x80))
++ all_subfeatures[i].flags |= SENSORS_COMPUTE_MAPPING;
++ all_subfeatures[i].flags |= sensors_get_attr_mode(dev_path, name);
++
++ sfnum++;
++ }
++ closedir(dir);
++
++ if (!sfnum) { /* No subfeature */
++ chip->subfeature = NULL;
++ goto exit_free;
++ }
++
++ /* How many main features? */
++ prev_slot = -1;
++ for (i = 0; i < ALL_POSSIBLE_SUBFEATURES; i++) {
++ if (!all_subfeatures[i].name)
++ continue;
++
++ if (i >= SUB_OFFSET_MISC || i / FEATURE_SIZE != prev_slot) {
++ fnum++;
++ prev_slot = i / FEATURE_SIZE;
++ }
++ }
++
++ dyn_subfeatures = calloc(sfnum, sizeof(sensors_subfeature));
++ dyn_features = calloc(fnum, sizeof(sensors_feature));
++ if (!dyn_subfeatures || !dyn_features)
++ sensors_fatal_error(__func__, "Out of memory");
++
++ /* Copy from the sparse array to the compact array */
++ sfnum = 0;
++ fnum = -1;
++ prev_slot = -1;
++ for (i = 0; i < ALL_POSSIBLE_SUBFEATURES; i++) {
++ if (!all_subfeatures[i].name)
++ continue;
++
++ /* New main feature? */
++ if (i >= SUB_OFFSET_MISC || i / FEATURE_SIZE != prev_slot) {
++ ftype = all_subfeatures[i].type >> 8;
++ fnum++;
++ prev_slot = i / FEATURE_SIZE;
++
++ dyn_features[fnum].name = get_feature_name(ftype,
++ all_subfeatures[i].name);
++ dyn_features[fnum].number = fnum;
++ dyn_features[fnum].first_subfeature = sfnum;
++ dyn_features[fnum].type = ftype;
++ }
++
++ dyn_subfeatures[sfnum] = all_subfeatures[i];
++ dyn_subfeatures[sfnum].number = sfnum;
++ /* Back to the feature */
++ dyn_subfeatures[sfnum].mapping = fnum;
++
++ sfnum++;
++ }
++
++ chip->subfeature = dyn_subfeatures;
++ chip->subfeature_count = sfnum;
++ chip->feature = dyn_features;
++ chip->feature_count = ++fnum;
++
++exit_free:
++ free(all_subfeatures);
++ return 0;
++}
++
++/* returns !0 if sysfs filesystem was found, 0 otherwise */
++int sensors_init_sysfs(void)
++{
++ struct statfs statfsbuf;
++
++ snprintf(sensors_sysfs_mount, NAME_MAX, "%s", "/sys");
++ if (statfs(sensors_sysfs_mount, &statfsbuf) < 0
++ || statfsbuf.f_type != SYSFS_MAGIC)
++ return 0;
++
++ return 1;
++}
++
++/* returns: number of devices added (0 or 1) if successful, <0 otherwise */
++static int sensors_read_one_sysfs_chip(const char *dev_path,
++ const char *dev_name,
++ const char *hwmon_path)
++{
++ int domain, bus, slot, fn, vendor, product, id;
++ int err = -SENSORS_ERR_KERNEL;
++ char *bus_attr;
++ char bus_path[NAME_MAX];
++ char linkpath[NAME_MAX];
++ char subsys_path[NAME_MAX], *subsys;
++ int sub_len;
++ sensors_chip_features entry;
++
++ /* ignore any device without name attribute */
++ if (!(entry.chip.prefix = sysfs_read_attr(hwmon_path, "name")))
++ return 0;
++
++ entry.chip.path = strdup(hwmon_path);
++ if (!entry.chip.path)
++ sensors_fatal_error(__func__, "Out of memory");
++
++ if (dev_path == NULL) {
++ /* Virtual device */
++ entry.chip.bus.type = SENSORS_BUS_TYPE_VIRTUAL;
++ entry.chip.bus.nr = 0;
++ /* For now we assume that virtual devices are unique */
++ entry.chip.addr = 0;
++ goto done;
++ }
++
++ /* Find bus type */
++ snprintf(linkpath, NAME_MAX, "%s/subsystem", dev_path);
++ sub_len = readlink(linkpath, subsys_path, NAME_MAX - 1);
++ if (sub_len < 0 && errno == ENOENT) {
++ /* Fallback to "bus" link for kernels <= 2.6.17 */
++ snprintf(linkpath, NAME_MAX, "%s/bus", dev_path);
++ sub_len = readlink(linkpath, subsys_path, NAME_MAX - 1);
++ }
++ if (sub_len < 0) {
++ /* Older kernels (<= 2.6.11) have neither the subsystem
++ symlink nor the bus symlink */
++ if (errno == ENOENT)
++ subsys = NULL;
++ else
++ goto exit_free;
++ } else {
++ subsys_path[sub_len] = '\0';
++ subsys = strrchr(subsys_path, '/') + 1;
++ }
++
++ if ((!subsys || !strcmp(subsys, "i2c")) &&
++ sscanf(dev_name, "%hd-%x", &entry.chip.bus.nr,
++ &entry.chip.addr) == 2) {
++ /* find out if legacy ISA or not */
++ if (entry.chip.bus.nr == 9191) {
++ entry.chip.bus.type = SENSORS_BUS_TYPE_ISA;
++ entry.chip.bus.nr = 0;
++ } else {
++ entry.chip.bus.type = SENSORS_BUS_TYPE_I2C;
++ snprintf(bus_path, sizeof(bus_path),
++ "%s/class/i2c-adapter/i2c-%d/device",
++ sensors_sysfs_mount, entry.chip.bus.nr);
++
++ if ((bus_attr = sysfs_read_attr(bus_path, "name"))) {
++ if (!strncmp(bus_attr, "ISA ", 4)) {
++ entry.chip.bus.type = SENSORS_BUS_TYPE_ISA;
++ entry.chip.bus.nr = 0;
++ }
++
++ free(bus_attr);
++ }
++ }
++ } else
++ if ((!subsys || !strcmp(subsys, "spi")) &&
++ sscanf(dev_name, "spi%hd.%d", &entry.chip.bus.nr,
++ &entry.chip.addr) == 2) {
++ /* SPI */
++ entry.chip.bus.type = SENSORS_BUS_TYPE_SPI;
++ } else
++ if ((!subsys || !strcmp(subsys, "pci")) &&
++ sscanf(dev_name, "%x:%x:%x.%x", &domain, &bus, &slot, &fn) == 4) {
++ /* PCI */
++ entry.chip.addr = (domain << 16) + (bus << 8) + (slot << 3) + fn;
++ entry.chip.bus.type = SENSORS_BUS_TYPE_PCI;
++ entry.chip.bus.nr = 0;
++ } else
++ if ((!subsys || !strcmp(subsys, "platform") ||
++ !strcmp(subsys, "of_platform"))) {
++ /* must be new ISA (platform driver) */
++ if (sscanf(dev_name, "%*[a-z0-9_].%d", &entry.chip.addr) != 1)
++ entry.chip.addr = 0;
++ entry.chip.bus.type = SENSORS_BUS_TYPE_ISA;
++ entry.chip.bus.nr = 0;
++ } else if (subsys && !strcmp(subsys, "acpi")) {
++ entry.chip.bus.type = SENSORS_BUS_TYPE_ACPI;
++ /* For now we assume that acpi devices are unique */
++ entry.chip.bus.nr = 0;
++ entry.chip.addr = 0;
++ } else
++ if (subsys && !strcmp(subsys, "hid") &&
++ sscanf(dev_name, "%x:%x:%x.%x", &bus, &vendor, &product, &id) == 4) {
++ entry.chip.bus.type = SENSORS_BUS_TYPE_HID;
++ /* As of kernel 2.6.32, the hid device names don't look good */
++ entry.chip.bus.nr = bus;
++ entry.chip.addr = id;
++ } else {
++ /* Ignore unknown device */
++ err = 0;
++ goto exit_free;
++ }
++
++done:
++ if (sensors_read_dynamic_chip(&entry, hwmon_path) < 0)
++ goto exit_free;
++ if (!entry.subfeature) { /* No subfeature, discard chip */
++ err = 0;
++ goto exit_free;
++ }
++ sensors_add_proc_chips(&entry);
++
++ return 1;
++
++exit_free:
++ free(entry.chip.prefix);
++ free(entry.chip.path);
++ return err;
++}
++
++static int sensors_add_hwmon_device_compat(const char *path,
++ const char *dev_name)
++{
++ int err;
++
++ err = sensors_read_one_sysfs_chip(path, dev_name, path);
++ if (err < 0)
++ return err;
++ return 0;
++}
++
++/* returns 0 if successful, !0 otherwise */
++static int sensors_read_sysfs_chips_compat(void)
++{
++ int ret;
++
++ ret = sysfs_foreach_busdev("i2c", sensors_add_hwmon_device_compat);
++ if (ret && ret != ENOENT)
++ return -SENSORS_ERR_KERNEL;
++
++ return 0;
++}
++
++static int sensors_add_hwmon_device(const char *path, const char *classdev)
++{
++ char linkpath[NAME_MAX];
++ char device[NAME_MAX], *device_p;
++ int dev_len, err;
++ (void)classdev; /* hide warning */
++
++ snprintf(linkpath, NAME_MAX, "%s/device", path);
++ dev_len = readlink(linkpath, device, NAME_MAX - 1);
++ if (dev_len < 0) {
++ /* No device link? Treat as virtual */
++ err = sensors_read_one_sysfs_chip(NULL, NULL, path);
++ } else {
++ device[dev_len] = '\0';
++ device_p = strrchr(device, '/') + 1;
++
++ /* The attributes we want might be those of the hwmon class
++ device, or those of the device itself. */
++ err = sensors_read_one_sysfs_chip(linkpath, device_p, path);
++ if (err == 0)
++ err = sensors_read_one_sysfs_chip(linkpath, device_p,
++ linkpath);
++ }
++ if (err < 0)
++ return err;
++ return 0;
++}
++
++/* returns 0 if successful, !0 otherwise */
++int sensors_read_sysfs_chips(void)
++{
++ int ret;
++
++ ret = sysfs_foreach_classdev("hwmon", sensors_add_hwmon_device);
++ if (ret == ENOENT) {
++ /* compatibility function for kernel 2.6.n where n <= 13 */
++ return sensors_read_sysfs_chips_compat();
++ }
++
++ if (ret > 0)
++ ret = -SENSORS_ERR_KERNEL;
++ return ret;
++}
++
++/* returns 0 if successful, !0 otherwise */
++static int sensors_add_i2c_bus(const char *path, const char *classdev)
++{
++ sensors_bus entry;
++
++ if (sscanf(classdev, "i2c-%hd", &entry.bus.nr) != 1 ||
++ entry.bus.nr == 9191) /* legacy ISA */
++ return 0;
++ entry.bus.type = SENSORS_BUS_TYPE_I2C;
++
++ /* Get the adapter name from the classdev "name" attribute
++ * (Linux 2.6.20 and later). If it fails, fall back to
++ * the device "name" attribute (for older kernels). */
++ entry.adapter = sysfs_read_attr(path, "name");
++ if (!entry.adapter)
++ entry.adapter = sysfs_read_attr(path, "device/name");
++ if (entry.adapter)
++ sensors_add_proc_bus(&entry);
++
++ return 0;
++}
++
++/* returns 0 if successful, !0 otherwise */
++int sensors_read_sysfs_bus(void)
++{
++ int ret;
++
++ ret = sysfs_foreach_classdev("i2c-adapter", sensors_add_i2c_bus);
++ if (ret == ENOENT)
++ ret = sysfs_foreach_busdev("i2c", sensors_add_i2c_bus);
++ if (ret && ret != ENOENT)
++ return -SENSORS_ERR_KERNEL;
++
++ return 0;
++}
++
++int sensors_read_sysfs_attr(const sensors_chip_name *name,
++ const sensors_subfeature *subfeature,
++ double *value)
++{
++ char n[NAME_MAX];
++ int f;
++
++ snprintf(n, NAME_MAX, "%s/%s", name->path, subfeature->name);
++ if ((f = open(n, O_RDONLY)) != -1) {
++ int res, err = 0;
++ char buf[512];
++ int count;
++
++ errno = 0;
++ if ((count = read(f, buf, sizeof(buf) - 1)) == -1) {
++ if (errno == EIO)
++ err = -SENSORS_ERR_IO;
++ else
++ err = -SENSORS_ERR_ACCESS_R;
++ } else {
++ buf[count] = '\0';
++ errno = 0;
++ res = sscanf(buf, "%lf", value);
++ if (res == EOF && errno == EIO)
++ err = -SENSORS_ERR_IO;
++ else if (res != 1)
++ err = -SENSORS_ERR_ACCESS_R;
++ }
++ res = close(f);
++ if (err)
++ return err;
++
++ if (res != 0) {
++ if (errno == EIO)
++ return -SENSORS_ERR_IO;
++ else
++ return -SENSORS_ERR_ACCESS_R;
++ }
++ if (!sensors_sysfs_no_scaling)
++ *value /= get_type_scaling(subfeature->type);
++ } else
++ return -SENSORS_ERR_KERNEL;
++
++ return 0;
++}
++
++int sensors_write_sysfs_attr(const sensors_chip_name *name,
++ const sensors_subfeature *subfeature,
++ double value)
++{
++ char n[NAME_MAX];
++ FILE *f;
++
++ snprintf(n, NAME_MAX, "%s/%s", name->path, subfeature->name);
++ if ((f = fopen(n, "w"))) {
++ int res, err = 0;
++
++ if (!sensors_sysfs_no_scaling)
++ value *= get_type_scaling(subfeature->type);
++ res = fprintf(f, "%d", (int) value);
++ if (res == -EIO)
++ err = -SENSORS_ERR_IO;
++ else if (res < 0)
++ err = -SENSORS_ERR_ACCESS_W;
++ res = fclose(f);
++ if (err)
++ return err;
++
++ if (res == EOF) {
++ if (errno == EIO)
++ return -SENSORS_ERR_IO;
++ else
++ return -SENSORS_ERR_ACCESS_W;
++ }
++ } else
++ return -SENSORS_ERR_KERNEL;
++
++ return 0;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/sysfs.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/sysfs.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/sysfs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/sysfs.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,43 @@
++/*
++ sysfs.h - part of libsensors, a library for reading Linux sensor data
++ Copyright (C) Mark M. Hoffman <mhoffman@lightlink.com>
++ Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
++
++ This library is free software; you can redistribute it and/or
++ modify it under the terms of the GNU Lesser General Public
++ License as published by the Free Software Foundation; either
++ version 2.1 of the License, or (at your option) any later version.
++
++ This library is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU Lesser General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
++ MA 02110-1301 USA.
++*/
++
++#ifndef SENSORS_LIB_SYSFS_H
++#define SENSORS_LIB_SYSFS_H
++
++extern char sensors_sysfs_mount[];
++
++int sensors_init_sysfs(void);
++
++int sensors_read_sysfs_chips(void);
++
++int sensors_read_sysfs_bus(void);
++
++/* Read a value out of a sysfs attribute file */
++int sensors_read_sysfs_attr(const sensors_chip_name *name,
++ const sensors_subfeature *subfeature,
++ double *value);
++
++/* Write a value to a sysfs attribute file */
++int sensors_write_sysfs_attr(const sensors_chip_name *name,
++ const sensors_subfeature *subfeature,
++ double value);
++
++#endif /* !SENSORS_LIB_SYSFS_H */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/libsensors/version.h linux-linaro-stable-mx6/tools/gator/daemon/libsensors/version.h
+--- linux-3.10.30.orig/tools/gator/daemon/libsensors/version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/libsensors/version.h 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1 @@
++#define LM_VERSION "3.3.2"
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/LocalCapture.cpp linux-linaro-stable-mx6/tools/gator/daemon/LocalCapture.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/LocalCapture.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/LocalCapture.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,129 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <sys/stat.h>
++#include <sys/types.h>
++#include <dirent.h>
++#include <string.h>
++#include <stdlib.h>
++#include <unistd.h>
++#include "LocalCapture.h"
++#include "SessionData.h"
++#include "Logging.h"
++#include "OlyUtility.h"
++#include "EventsXML.h"
++
++LocalCapture::LocalCapture() {}
++
++LocalCapture::~LocalCapture() {}
++
++void LocalCapture::createAPCDirectory(char* target_path) {
++ gSessionData->mAPCDir = createUniqueDirectory(target_path, ".apc");
++ if ((removeDirAndAllContents(gSessionData->mAPCDir) != 0 || mkdir(gSessionData->mAPCDir, S_IRWXU | S_IRWXG | S_IROTH | S_IXOTH) != 0)) {
++ logg->logError(__FILE__, __LINE__, "Unable to create directory %s", gSessionData->mAPCDir);
++ handleException();
++ }
++}
++
++void LocalCapture::write(char* string) {
++ char file[PATH_MAX];
++
++ // Set full path
++ snprintf(file, PATH_MAX, "%s/session.xml", gSessionData->mAPCDir);
++
++ // Write the file
++ if (util->writeToDisk(file, string) < 0) {
++ logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify the path.", file);
++ handleException();
++ }
++
++ // Write events XML
++ EventsXML eventsXML;
++ eventsXML.write(gSessionData->mAPCDir);
++}
++
++char* LocalCapture::createUniqueDirectory(const char* initialPath, const char* ending) {
++ char* output;
++ char path[PATH_MAX];
++
++ // Ensure the path is an absolute path, i.e. starts with a slash
++ if (initialPath == 0 || strlen(initialPath) == 0) {
++ logg->logError(__FILE__, __LINE__, "Missing -o command line option required for a local capture.");
++ handleException();
++ } else if (initialPath[0] != '/') {
++ if (getcwd(path, PATH_MAX) == 0) {
++ logg->logMessage("Unable to retrieve the current working directory");
++ }
++ strncat(path, "/", PATH_MAX - strlen(path) - 1);
++ strncat(path, initialPath, PATH_MAX - strlen(path) - 1);
++ } else {
++ strncpy(path, initialPath, PATH_MAX);
++ path[PATH_MAX - 1] = 0; // strncpy does not guarantee a null-terminated string
++ }
++
++ // Add ending if it is not already there
++ if (strcmp(&path[strlen(path) - strlen(ending)], ending) != 0) {
++ strncat(path, ending, PATH_MAX - strlen(path) - 1);
++ }
++
++ output = strdup(path);
++
++ return output;
++}
++
++int LocalCapture::removeDirAndAllContents(char* path) {
++ int error = 0;
++ struct stat mFileInfo;
++ // Does the path exist?
++ if (stat(path, &mFileInfo) == 0) {
++ // Is it a directory?
++ if (mFileInfo.st_mode & S_IFDIR) {
++ DIR * dir = opendir(path);
++ dirent* entry = readdir(dir);
++ while (entry) {
++ if (strcmp(entry->d_name, ".") != 0 && strcmp(entry->d_name, "..") != 0) {
++ char* newpath = (char*)malloc(strlen(path) + strlen(entry->d_name) + 2);
++ sprintf(newpath, "%s/%s", path, entry->d_name);
++ error = removeDirAndAllContents(newpath);
++ free(newpath);
++ if (error) {
++ break;
++ }
++ }
++ entry = readdir(dir);
++ }
++ closedir(dir);
++ if (error == 0) {
++ error = rmdir(path);
++ }
++ } else {
++ error = remove(path);
++ }
++ }
++ return error;
++}
++
++void LocalCapture::copyImages(ImageLinkList* ptr) {
++ char dstfilename[PATH_MAX];
++
++ while (ptr) {
++ strncpy(dstfilename, gSessionData->mAPCDir, PATH_MAX);
++ dstfilename[PATH_MAX - 1] = 0; // strncpy does not guarantee a null-terminated string
++ if (gSessionData->mAPCDir[strlen(gSessionData->mAPCDir) - 1] != '/') {
++ strncat(dstfilename, "/", PATH_MAX - strlen(dstfilename) - 1);
++ }
++ strncat(dstfilename, util->getFilePart(ptr->path), PATH_MAX - strlen(dstfilename) - 1);
++ if (util->copyFile(ptr->path, dstfilename)) {
++ logg->logMessage("copied file %s to %s", ptr->path, dstfilename);
++ } else {
++ logg->logMessage("copy of file %s to %s failed", ptr->path, dstfilename);
++ }
++
++ ptr = ptr->next;
++ }
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/LocalCapture.h linux-linaro-stable-mx6/tools/gator/daemon/LocalCapture.h
+--- linux-3.10.30.orig/tools/gator/daemon/LocalCapture.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/LocalCapture.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,26 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __LOCAL_CAPTURE_H__
++#define __LOCAL_CAPTURE_H__
++
++struct ImageLinkList;
++
++class LocalCapture {
++public:
++ LocalCapture();
++ ~LocalCapture();
++ void write(char* string);
++ void copyImages(ImageLinkList* ptr);
++ void createAPCDirectory(char* target_path);
++private:
++ char* createUniqueDirectory(const char* path, const char* ending);
++ int removeDirAndAllContents(char* path);
++};
++
++#endif //__LOCAL_CAPTURE_H__
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Logging.cpp linux-linaro-stable-mx6/tools/gator/daemon/Logging.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/Logging.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Logging.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,78 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <stdio.h>
++#include <stdlib.h>
++#include <stdarg.h>
++#include <string.h>
++
++#ifdef WIN32
++#define MUTEX_INIT() mLoggingMutex = CreateMutex(NULL, false, NULL);
++#define MUTEX_LOCK() WaitForSingleObject(mLoggingMutex, 0xFFFFFFFF);
++#define MUTEX_UNLOCK() ReleaseMutex(mLoggingMutex);
++#define snprintf _snprintf
++#else
++#include <pthread.h>
++#define MUTEX_INIT() pthread_mutex_init(&mLoggingMutex, NULL)
++#define MUTEX_LOCK() pthread_mutex_lock(&mLoggingMutex)
++#define MUTEX_UNLOCK() pthread_mutex_unlock(&mLoggingMutex)
++#endif
++
++#include "Logging.h"
++
++// Global thread-safe logging
++Logging* logg = NULL;
++
++Logging::Logging(bool debug) {
++ mDebug = debug;
++ MUTEX_INIT();
++
++ strcpy(mErrBuf, "Unknown Error");
++ strcpy(mLogBuf, "Unknown Message");
++}
++
++Logging::~Logging() {
++}
++
++void Logging::logError(const char* file, int line, const char* fmt, ...) {
++ va_list args;
++
++ MUTEX_LOCK();
++ if (mDebug) {
++ snprintf(mErrBuf, sizeof(mErrBuf), "ERROR[%s:%d]: ", file, line);
++ } else {
++ mErrBuf[0] = 0;
++ }
++
++ va_start(args, fmt);
++ vsnprintf(mErrBuf + strlen(mErrBuf), sizeof(mErrBuf) - 2 - strlen(mErrBuf), fmt, args); // subtract 2 for \n and \0
++ va_end(args);
++
++ if (strlen(mErrBuf) > 0) {
++ strcat(mErrBuf, "\n");
++ }
++ MUTEX_UNLOCK();
++}
++
++void Logging::logMessage(const char* fmt, ...) {
++ if (mDebug) {
++ va_list args;
++
++ MUTEX_LOCK();
++ strcpy(mLogBuf, "INFO: ");
++
++ va_start(args, fmt);
++ vsnprintf(mLogBuf + strlen(mLogBuf), sizeof(mLogBuf) - 2 - strlen(mLogBuf), fmt, args); // subtract 2 for \n and \0
++ va_end(args);
++ strcat(mLogBuf, "\n");
++
++ fprintf(stdout, "%s", mLogBuf);
++ fflush(stdout);
++ MUTEX_UNLOCK();
++ }
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Logging.h linux-linaro-stable-mx6/tools/gator/daemon/Logging.h
+--- linux-3.10.30.orig/tools/gator/daemon/Logging.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Logging.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,47 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __LOGGING_H__
++#define __LOGGING_H__
++
++#include <stdio.h>
++#include <string.h>
++#include <limits.h>
++#ifdef WIN32
++#include <windows.h>
++#else
++#include <pthread.h>
++#endif
++
++#define DRIVER_ERROR "\n Driver issue:\n >> gator.ko must be built against the current kernel version & configuration\n >> gator.ko should be co-located with gatord in the same directory\n >> OR insmod gator.ko prior to launching gatord"
++
++class Logging {
++public:
++ Logging(bool debug);
++ ~Logging();
++ void logError(const char* file, int line, const char* fmt, ...);
++ void logMessage(const char* fmt, ...);
++ char* getLastError() {return mErrBuf;}
++ char* getLastMessage() {return mLogBuf;}
++
++private:
++ char mErrBuf[4096]; // Arbitrarily large buffer to hold a string
++ char mLogBuf[4096]; // Arbitrarily large buffer to hold a string
++ bool mDebug;
++#ifdef WIN32
++ HANDLE mLoggingMutex;
++#else
++ pthread_mutex_t mLoggingMutex;
++#endif
++};
++
++extern Logging* logg;
++
++extern void handleException() __attribute__ ((noreturn));
++
++#endif //__LOGGING_H__
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/main.cpp linux-linaro-stable-mx6/tools/gator/daemon/main.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/main.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/main.cpp 2014-05-15 20:34:24.402204050 +0200
+@@ -0,0 +1,485 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <stdlib.h>
++#include <signal.h>
++#include <sys/wait.h>
++#include <unistd.h>
++#include <sys/syscall.h>
++#include <sys/prctl.h>
++#include <sys/types.h>
++#include <sys/stat.h>
++#include <sys/mount.h>
++#include <fcntl.h>
++#include <sys/mman.h>
++#include <sys/time.h>
++#include <sys/resource.h>
++#include <arpa/inet.h>
++#include <sys/socket.h>
++#include "Child.h"
++#include "SessionData.h"
++#include "OlySocket.h"
++#include "Logging.h"
++#include "OlyUtility.h"
++#include "KMod.h"
++
++#define DEBUG false
++
++extern Child* child;
++static int shutdownFilesystem();
++static pthread_mutex_t numSessions_mutex;
++static int numSessions = 0;
++static OlySocket* sock = NULL;
++static bool driverRunningAtStart = false;
++static bool driverMountedAtStart = false;
++
++struct cmdline_t {
++ int port;
++ char* module;
++};
++
++#define DEFAULT_PORT 8080
++
++void cleanUp() {
++ if (shutdownFilesystem() == -1) {
++ logg->logMessage("Error shutting down gator filesystem");
++ }
++ delete sock;
++ delete util;
++ delete logg;
++}
++
++// CTRL C Signal Handler
++static void handler(int signum) {
++ logg->logMessage("Received signal %d, gator daemon exiting", signum);
++
++ // Case 1: both child and parent receive the signal
++ if (numSessions > 0) {
++ // Arbitrary sleep of 1 second to give time for the child to exit;
++ // if something bad happens, continue the shutdown process regardless
++ sleep(1);
++ }
++
++ // Case 2: only the parent received the signal
++ if (numSessions > 0) {
++ // Kill child threads - the first signal exits gracefully
++ logg->logMessage("Killing process group as %d child was running when signal was received", numSessions);
++ kill(0, SIGINT);
++
++ // Give time for the child to exit
++ sleep(1);
++
++ if (numSessions > 0) {
++ // The second signal force kills the child
++ logg->logMessage("Force kill the child");
++ kill(0, SIGINT);
++ // Again, sleep for 1 second
++ sleep(1);
++
++ if (numSessions > 0) {
++ // Something bad has really happened; the child is not exiting and therefore may hold the /dev/gator resource open
++ printf("Unable to kill the gatord child process, thus gator.ko may still be loaded.\n");
++ }
++ }
++ }
++
++ cleanUp();
++ exit(0);
++}
++
++// Child exit Signal Handler
++static void child_exit(int) {
++ int status;
++ int pid = wait(&status);
++ if (pid != -1) {
++ pthread_mutex_lock(&numSessions_mutex);
++ numSessions--;
++ pthread_mutex_unlock(&numSessions_mutex);
++ logg->logMessage("Child process %d exited with status %d", pid, status);
++ }
++}
++
++static int udpPort(int port) {
++ int s;
++ struct sockaddr_in6 sockaddr;
++ int on;
++ int family = AF_INET6;
++
++ s = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP);
++ if (s == -1) {
++ family = AF_INET;
++ s = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
++ if (s == -1) {
++ logg->logError(__FILE__, __LINE__, "socket failed");
++ handleException();
++ }
++ }
++
++ on = 1;
++ if (setsockopt(s, SOL_SOCKET, SO_REUSEADDR, (const char*)&on, sizeof(on)) != 0) {
++ logg->logError(__FILE__, __LINE__, "setsockopt failed");
++ handleException();
++ }
++
++ memset((void*)&sockaddr, 0, sizeof(sockaddr));
++ sockaddr.sin6_family = family;
++ sockaddr.sin6_port = htons(port);
++ sockaddr.sin6_addr = in6addr_any;
++ if (bind(s, (struct sockaddr *)&sockaddr, sizeof(sockaddr)) < 0) {
++ logg->logError(__FILE__, __LINE__, "socket failed");
++ handleException();
++ }
++
++ return s;
++}
++
++#define UDP_ANS_PORT 30000
++#define UDP_REQ_PORT 30001
++
++typedef struct {
++ char rviHeader[8];
++ uint32_t messageID;
++ uint8_t ethernetAddress[8];
++ uint32_t ethernetType;
++ uint32_t dhcp;
++ char dhcpName[40];
++ uint32_t ipAddress;
++ uint32_t defaultGateway;
++ uint32_t subnetMask;
++ uint32_t activeConnections;
++} RVIConfigureInfo;
++
++static const char DST_REQ[] = { 'D', 'S', 'T', '_', 'R', 'E', 'Q', ' ', 0, 0, 0, 0x64 };
++
++static void* answerThread(void* pVoid) {
++ const struct cmdline_t * const cmdline = (struct cmdline_t *)pVoid;
++ RVIConfigureInfo dstAns;
++ int req = udpPort(UDP_REQ_PORT);
++ int ans = udpPort(UDP_ANS_PORT);
++
++ // Format the answer buffer
++ memset(&dstAns, 0, sizeof(dstAns));
++ memcpy(dstAns.rviHeader, "STR_ANS ", sizeof(dstAns.rviHeader));
++ if (gethostname(dstAns.dhcpName, sizeof(dstAns.dhcpName) - 1) != 0) {
++ logg->logError(__FILE__, __LINE__, "gethostname failed");
++ handleException();
++ }
++ // Subvert the defaultGateway field for the port number
++ if (cmdline->port != DEFAULT_PORT) {
++ dstAns.defaultGateway = cmdline->port;
++ }
++ // Subvert the subnetMask field for the protocol version
++ dstAns.subnetMask = PROTOCOL_VERSION;
++
++ for (;;) {
++ char buf[128];
++ struct sockaddr_in6 sockaddr;
++ socklen_t addrlen;
++ int read;
++ addrlen = sizeof(sockaddr);
++ read = recvfrom(req, &buf, sizeof(buf), 0, (struct sockaddr *)&sockaddr, &addrlen);
++ if (read < 0) {
++ logg->logError(__FILE__, __LINE__, "recvfrom failed");
++ handleException();
++ } else if ((read == 12) && (memcmp(buf, DST_REQ, sizeof(DST_REQ)) == 0)) {
++ if (sendto(ans, &dstAns, sizeof(dstAns), 0, (struct sockaddr *)&sockaddr, addrlen) != sizeof(dstAns)) {
++ logg->logError(__FILE__, __LINE__, "sendto failed");
++ handleException();
++ }
++ }
++ }
++}
++
++// retval: -1 = failure; 0 = was already mounted; 1 = successfully mounted
++static int mountGatorFS() {
++ // If already mounted,
++ if (access("/dev/gator/buffer", F_OK) == 0) {
++ return 0;
++ }
++
++ // else, mount the filesystem
++ mkdir("/dev/gator", S_IRWXU | S_IRWXG | S_IROTH | S_IXOTH);
++ if (mount("nodev", "/dev/gator", "gatorfs", 0, NULL) != 0) {
++ return -1;
++ } else {
++ return 1;
++ }
++}
++
++static bool init_module (const char * const location) {
++ bool ret(false);
++ const int fd = open(location, O_RDONLY);
++ if (fd >= 0) {
++ struct stat st;
++ if (fstat(fd, &st) == 0) {
++ void * const p = mmap(NULL, st.st_size, PROT_READ, MAP_PRIVATE, fd, 0);
++ if (p != MAP_FAILED) {
++ if (syscall(__NR_init_module, p, st.st_size, "") == 0) {
++ ret = true;
++ }
++ munmap(p, st.st_size);
++ }
++ }
++ close(fd);
++ }
++
++ return ret;
++}
++
++static int setupFilesystem(char* module) {
++ int retval;
++
++ // Verify root permissions
++ uid_t euid = geteuid();
++ if (euid) {
++ logg->logError(__FILE__, __LINE__, "gatord must be launched with root privileges");
++ handleException();
++ }
++
++ if (module) {
++ // unmount and rmmod if the module was specified on the commandline, i.e. ensure that the specified module is indeed running
++ shutdownFilesystem();
++
++ // if still mounted
++ if (access("/dev/gator/buffer", F_OK) == 0) {
++ logg->logError(__FILE__, __LINE__, "Unable to remove the running gator.ko. Manually remove the module or use the running module by not specifying one on the commandline");
++ handleException();
++ }
++ }
++
++ retval = mountGatorFS();
++ if (retval == 1) {
++ logg->logMessage("Driver already running at startup");
++ driverRunningAtStart = true;
++ } else if (retval == 0) {
++ logg->logMessage("Driver already mounted at startup");
++ driverRunningAtStart = driverMountedAtStart = true;
++ } else {
++ char command[256]; // arbitrarily large amount
++ char location[256]; // arbitrarily large amount
++
++ if (module) {
++ strncpy(location, module, sizeof(location));
++ } else {
++ // Is the driver co-located in the same directory?
++ if (util->getApplicationFullPath(location, sizeof(location)) != 0) { // allow some buffer space
++ logg->logMessage("Unable to determine the full path of gatord, the cwd will be used");
++ }
++ strncat(location, "gator.ko", sizeof(location) - strlen(location) - 1);
++ }
++
++ if (access(location, F_OK) == -1) {
++ logg->logError(__FILE__, __LINE__, "Unable to locate gator.ko driver:\n >>> gator.ko should be co-located with gatord in the same directory\n >>> OR insmod gator.ko prior to launching gatord\n >>> OR specify the location of gator.ko on the command line");
++ handleException();
++ }
++
++ // Load driver
++ bool success = init_module(location);
++ if (!success) {
++ logg->logMessage("init_module failed, trying insmod");
++ snprintf(command, sizeof(command), "insmod %s >/dev/null 2>&1", location);
++ if (system(command) != 0) {
++ logg->logMessage("Unable to load gator.ko driver with command: %s", command);
++ logg->logError(__FILE__, __LINE__, "Unable to load (insmod) gator.ko driver:\n >>> gator.ko must be built against the current kernel version & configuration\n >>> See dmesg for more details");
++ handleException();
++ }
++ }
++
++ if (mountGatorFS() == -1) {
++ logg->logError(__FILE__, __LINE__, "Unable to mount the gator filesystem needed for profiling.");
++ handleException();
++ }
++ }
++
++ return 0;
++}
++
++static int shutdownFilesystem() {
++ if (driverMountedAtStart == false) {
++ umount("/dev/gator");
++ }
++ if (driverRunningAtStart == false) {
++ if (syscall(__NR_delete_module, "gator", O_NONBLOCK) != 0) {
++ logg->logMessage("delete_module failed, trying rmmod");
++ if (system("rmmod gator >/dev/null 2>&1") != 0) {
++ return -1;
++ }
++ }
++ }
++
++ return 0; // success
++}
++
++static struct cmdline_t parseCommandLine(int argc, char** argv) {
++ struct cmdline_t cmdline;
++ cmdline.port = DEFAULT_PORT;
++ cmdline.module = NULL;
++ char version_string[256]; // arbitrary length to hold the version information
++ int c;
++
++ // build the version string
++ if (PROTOCOL_VERSION < PROTOCOL_DEV) {
++ snprintf(version_string, sizeof(version_string), "Streamline gatord version %d (DS-5 v5.%d)", PROTOCOL_VERSION, PROTOCOL_VERSION);
++ } else {
++ snprintf(version_string, sizeof(version_string), "Streamline gatord development version %d", PROTOCOL_VERSION);
++ }
++
++ while ((c = getopt(argc, argv, "hvp:s:c:e:m:o:")) != -1) {
++ switch(c) {
++ case 'c':
++ gSessionData->mConfigurationXMLPath = optarg;
++ break;
++ case 'e':
++ gSessionData->mEventsXMLPath = optarg;
++ break;
++ case 'm':
++ cmdline.module = optarg;
++ break;
++ case 'p':
++ cmdline.port = strtol(optarg, NULL, 10);
++ break;
++ case 's':
++ gSessionData->mSessionXMLPath = optarg;
++ break;
++ case 'o':
++ gSessionData->mTargetPath = optarg;
++ break;
++ case 'h':
++ case '?':
++ logg->logError(__FILE__, __LINE__,
++ "%s. All parameters are optional:\n"
++ "-c config_xml path and filename of the configuration.xml to use\n"
++ "-e events_xml path and filename of the events.xml to use\n"
++ "-h this help page\n"
++ "-m module path and filename of gator.ko\n"
++ "-p port_number port upon which the server listens; default is 8080\n"
++ "-s session_xml path and filename of a session xml used for local capture\n"
++ "-o apc_dir path and name of the output for a local capture\n"
++ "-v version information\n"
++ , version_string);
++ handleException();
++ break;
++ case 'v':
++ logg->logError(__FILE__, __LINE__, version_string);
++ handleException();
++ break;
++ }
++ }
++
++ // Error checking
++ if (cmdline.port != DEFAULT_PORT && gSessionData->mSessionXMLPath != NULL) {
++ logg->logError(__FILE__, __LINE__, "Only a port or a session xml can be specified, not both");
++ handleException();
++ }
++
++ if (gSessionData->mTargetPath != NULL && gSessionData->mSessionXMLPath == NULL) {
++ logg->logError(__FILE__, __LINE__, "Missing -s command line option required for a local capture.");
++ handleException();
++ }
++
++ if (optind < argc) {
++ logg->logError(__FILE__, __LINE__, "Unknown argument: %s. Use '-h' for help.", argv[optind]);
++ handleException();
++ }
++
++ return cmdline;
++}
++
++// Gator data flow: collector -> collector fifo -> sender
++int main(int argc, char** argv) {
++ // Ensure proper signal handling by making gatord the process group leader
++ // e.g. it may not be the group leader when launched as 'sudo gatord'
++ setsid();
++
++ logg = new Logging(DEBUG); // Set up global thread-safe logging
++ gSessionData = new SessionData(); // Global data class
++ util = new OlyUtility(); // Set up global utility class
++
++ // Initialize drivers
++ new KMod();
++
++ prctl(PR_SET_NAME, (unsigned long)&"gatord-main", 0, 0, 0);
++ pthread_mutex_init(&numSessions_mutex, NULL);
++
++ signal(SIGINT, handler);
++ signal(SIGTERM, handler);
++ signal(SIGABRT, handler);
++
++ // Set to high priority
++ if (setpriority(PRIO_PROCESS, syscall(__NR_gettid), -19) == -1) {
++ logg->logMessage("setpriority() failed");
++ }
++
++ // Parse the command line parameters
++ struct cmdline_t cmdline = parseCommandLine(argc, argv);
++
++ // Call before setting up the SIGCHLD handler, as system() spawns child processes
++ setupFilesystem(cmdline.module);
++
++ // Handle child exit codes
++ signal(SIGCHLD, child_exit);
++
++ // Ignore the SIGPIPE signal so that any send to a broken socket will return an error code instead of asserting a signal
++ // Handling the error at the send function call is much easier than trying to do anything intelligent in the sig handler
++ signal(SIGPIPE, SIG_IGN);
++
++ // If the command line argument is a session xml file, no need to open a socket
++ if (gSessionData->mSessionXMLPath) {
++ child = new Child();
++ child->run();
++ delete child;
++ } else {
++ pthread_t answerThreadID;
++ if (pthread_create(&answerThreadID, NULL, answerThread, &cmdline)) {
++ logg->logError(__FILE__, __LINE__, "Failed to create answer thread");
++ handleException();
++ }
++ sock = new OlySocket(cmdline.port, true);
++ // Forever loop, can be exited via a signal or exception
++ while (1) {
++ logg->logMessage("Waiting on connection...");
++ sock->acceptConnection();
++
++ int pid = fork();
++ if (pid < 0) {
++ // Error
++ logg->logError(__FILE__, __LINE__, "Fork process failed. Please power cycle the target device if this error persists.");
++ } else if (pid == 0) {
++ // Child
++ sock->closeServerSocket();
++ child = new Child(sock, numSessions + 1);
++ child->run();
++ delete child;
++ exit(0);
++ } else {
++ // Parent
++ sock->closeSocket();
++
++ pthread_mutex_lock(&numSessions_mutex);
++ numSessions++;
++ pthread_mutex_unlock(&numSessions_mutex);
++
++ // Maximum number of connections is 2
++ int wait = 0;
++ while (numSessions > 1) {
++ // Throttle until one of the children exits before continuing to accept another socket connection
++ logg->logMessage("%d sessions active!", numSessions);
++ if (wait++ >= 10) { // Wait no more than 10 seconds
++ // Kill last created child
++ kill(pid, SIGALRM);
++ break;
++ }
++ sleep(1);
++ }
++ }
++ }
++ }
++
++ cleanUp();
++ return 0;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Makefile linux-linaro-stable-mx6/tools/gator/daemon/Makefile
+--- linux-3.10.30.orig/tools/gator/daemon/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Makefile 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,25 @@
++#
++# Makefile for ARM Streamline - Gator Daemon
++#
++
++# Uncomment and define CROSS_COMPILE if it is not already defined
++# CROSS_COMPILE=/path/to/cross-compiler/arm-linux-gnueabihf-
++# NOTE: This toolchain uses the hardfloat abi by default. For non-hardfloat
++# targets run 'make SOFTFLOAT=1 SYSROOT=/path/to/sysroot', see
++# README_Streamline.txt for more details
++
++CPP = $(CROSS_COMPILE)g++
++GCC = $(CROSS_COMPILE)gcc
++
++# -mthumb-interwork is required for interworking to ARM or Thumb stdlibc
++CFLAGS += -mthumb-interwork
++
++ifeq ($(SOFTFLOAT),1)
++ CFLAGS += -marm -march=armv4t -mfloat-abi=soft
++ LDFLAGS += -marm -march=armv4t -mfloat-abi=soft
++endif
++ifneq ($(SYSROOT),)
++ LDFLAGS += --sysroot=$(SYSROOT)
++endif
++
++include common.mk
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Makefile_aarch64 linux-linaro-stable-mx6/tools/gator/daemon/Makefile_aarch64
+--- linux-3.10.30.orig/tools/gator/daemon/Makefile_aarch64 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Makefile_aarch64 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,15 @@
++#
++# Makefile for ARM Streamline - Gator Daemon
++# make -f Makefile_aarch64
++#
++
++# Uncomment and define CROSS_COMPILE if it is not already defined
++# CROSS_COMPILE=/path/to/cross-compiler/arm-linux-gnueabihf-
++# NOTE: This toolchain uses the hardfloat abi by default. For non-hardfloat
++# targets it is necessary to add options
++# '-marm -march=armv4t -mfloat-abi=soft'.
++
++CPP = $(CROSS_COMPILE)g++
++GCC = $(CROSS_COMPILE)gcc
++
++include common.mk
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/config.h linux-linaro-stable-mx6/tools/gator/daemon/mxml/config.h
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/config.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/config.h 2014-05-15 20:34:24.406204078 +0200
+@@ -0,0 +1,96 @@
++/* config.h. Generated from config.h.in by configure. */
++/*
++ * "$Id: config.h.in 408 2010-09-19 05:26:46Z mike $"
++ *
++ * Configuration file for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2010 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++#include <stdarg.h>
++#include <ctype.h>
++
++
++/*
++ * Version number...
++ */
++
++#define MXML_VERSION "Mini-XML v2.7"
++
++
++/*
++ * Inline function support...
++ */
++
++#define inline
++
++
++/*
++ * Long long support...
++ */
++
++#define HAVE_LONG_LONG 1
++
++
++/*
++ * Do we have the snprintf() and vsnprintf() functions?
++ */
++
++#define HAVE_SNPRINTF 1
++#define HAVE_VSNPRINTF 1
++
++
++/*
++ * Do we have the strXXX() functions?
++ */
++
++#define HAVE_STRDUP 1
++
++
++/*
++ * Do we have threading support?
++ */
++
++#define HAVE_PTHREAD_H 1
++
++
++/*
++ * Define prototypes for string functions as needed...
++ */
++
++# ifndef HAVE_STRDUP
++extern char *_mxml_strdup(const char *);
++# define strdup _mxml_strdup
++# endif /* !HAVE_STRDUP */
++
++extern char *_mxml_strdupf(const char *, ...);
++extern char *_mxml_vstrdupf(const char *, va_list);
++
++# ifndef HAVE_SNPRINTF
++extern int _mxml_snprintf(char *, size_t, const char *, ...);
++# define snprintf _mxml_snprintf
++# endif /* !HAVE_SNPRINTF */
++
++# ifndef HAVE_VSNPRINTF
++extern int _mxml_vsnprintf(char *, size_t, const char *, va_list);
++# define vsnprintf _mxml_vsnprintf
++# endif /* !HAVE_VSNPRINTF */
++
++/*
++ * End of "$Id: config.h.in 408 2010-09-19 05:26:46Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/COPYING linux-linaro-stable-mx6/tools/gator/daemon/mxml/COPYING
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/COPYING 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/COPYING 2014-05-15 20:34:24.406204078 +0200
+@@ -0,0 +1,507 @@
++ Mini-XML License
++ September 18, 2010
++
++
++The Mini-XML library and included programs are provided under the
++terms of the GNU Library General Public License version 2 (LGPL2)
++with the following exceptions:
++
++ 1. Static linking of applications to the Mini-XML library
++does not constitute a derivative work and does not require
++the author to provide source code for the application, use
++the shared Mini-XML libraries, or link their applications
++against a user-supplied version of Mini-XML.
++
++If you link the application to a modified version of
++Mini-XML, then the changes to Mini-XML must be provided
++under the terms of the LGPL2 in sections 1, 2, and 4.
++
++ 2. You do not have to provide a copy of the Mini-XML license
++with programs that are linked to the Mini-XML library, nor
++do you have to identify the Mini-XML license in your
++program or documentation as required by section 6 of the
++LGPL2.
++
++
++ GNU LIBRARY GENERAL PUBLIC LICENSE
++ Version 2, June 1991
++
++ Copyright (C) 1991 Free Software Foundation, Inc.
++ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++
++ Everyone is permitted to copy and distribute verbatim copies
++ of this license document, but changing it is not allowed.
++
++ [This is the first released version of the library GPL. It is
++ numbered 2 because it goes with version 2 of the ordinary GPL.]
++
++ Preamble
++
++ The licenses for most software are designed to take away your
++freedom to share and change it. By contrast, the GNU General Public
++Licenses are intended to guarantee your freedom to share and change
++free software--to make sure the software is free for all its users.
++
++ This license, the Library General Public License, applies to some
++specially designated Free Software Foundation software, and to any
++other libraries whose authors decide to use it. You can use it for
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++
++ When we speak of free software, we are referring to freedom, not
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++anyone to deny you these rights or to ask you to surrender the rights.
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++you distribute copies of the library, or if you modify it.
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++That's all there is to it!
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-attr.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-attr.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-attr.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-attr.c 2014-05-15 20:34:24.406204078 +0200
+@@ -0,0 +1,319 @@
++/*
++ * "$Id: mxml-attr.c 408 2010-09-19 05:26:46Z mike $"
++ *
++ * Attribute support code for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2010 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * mxmlElementDeleteAttr() - Delete an attribute.
++ * mxmlElementGetAttr() - Get an attribute.
++ * mxmlElementSetAttr() - Set an attribute.
++ * mxmlElementSetAttrf() - Set an attribute with a formatted value.
++ * mxml_set_attr() - Set or add an attribute name/value pair.
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "config.h"
++#include "mxml.h"
++
++
++/*
++ * Local functions...
++ */
++
++static int mxml_set_attr(mxml_node_t *node, const char *name,
++ char *value);
++
++
++/*
++ * 'mxmlElementDeleteAttr()' - Delete an attribute.
++ *
++ * @since Mini-XML 2.4@
++ */
++
++void
++mxmlElementDeleteAttr(mxml_node_t *node,/* I - Element */
++ const char *name)/* I - Attribute name */
++{
++ int i; /* Looping var */
++ mxml_attr_t *attr; /* Cirrent attribute */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlElementDeleteAttr(node=%p, name=\"%s\")\n",
++ node, name ? name : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT || !name)
++ return;
++
++ /*
++ * Look for the attribute...
++ */
++
++ for (i = node->value.element.num_attrs, attr = node->value.element.attrs;
++ i > 0;
++ i --, attr ++)
++ {
++#ifdef DEBUG
++ printf(" %s=\"%s\"\n", attr->name, attr->value);
++#endif /* DEBUG */
++
++ if (!strcmp(attr->name, name))
++ {
++ /*
++ * Delete this attribute...
++ */
++
++ free(attr->name);
++ free(attr->value);
++
++ i --;
++ if (i > 0)
++ memmove(attr, attr + 1, i * sizeof(mxml_attr_t));
++
++ node->value.element.num_attrs --;
++ return;
++ }
++ }
++}
++
++
++/*
++ * 'mxmlElementGetAttr()' - Get an attribute.
++ *
++ * This function returns NULL if the node is not an element or the
++ * named attribute does not exist.
++ */
++
++const char * /* O - Attribute value or NULL */
++mxmlElementGetAttr(mxml_node_t *node, /* I - Element node */
++ const char *name) /* I - Name of attribute */
++{
++ int i; /* Looping var */
++ mxml_attr_t *attr; /* Cirrent attribute */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlElementGetAttr(node=%p, name=\"%s\")\n",
++ node, name ? name : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT || !name)
++ return (NULL);
++
++ /*
++ * Look for the attribute...
++ */
++
++ for (i = node->value.element.num_attrs, attr = node->value.element.attrs;
++ i > 0;
++ i --, attr ++)
++ {
++#ifdef DEBUG
++ printf(" %s=\"%s\"\n", attr->name, attr->value);
++#endif /* DEBUG */
++
++ if (!strcmp(attr->name, name))
++ {
++#ifdef DEBUG
++ printf(" Returning \"%s\"!\n", attr->value);
++#endif /* DEBUG */
++ return (attr->value);
++ }
++ }
++
++ /*
++ * Didn't find attribute, so return NULL...
++ */
++
++#ifdef DEBUG
++ puts(" Returning NULL!\n");
++#endif /* DEBUG */
++
++ return (NULL);
++}
++
++
++/*
++ * 'mxmlElementSetAttr()' - Set an attribute.
++ *
++ * If the named attribute already exists, the value of the attribute
++ * is replaced by the new string value. The string value is copied
++ * into the element node. This function does nothing if the node is
++ * not an element.
++ */
++
++void
++mxmlElementSetAttr(mxml_node_t *node, /* I - Element node */
++ const char *name, /* I - Name of attribute */
++ const char *value) /* I - Attribute value */
++{
++ char *valuec; /* Copy of value */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlElementSetAttr(node=%p, name=\"%s\", value=\"%s\")\n",
++ node, name ? name : "(null)", value ? value : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT || !name)
++ return;
++
++ if (value)
++ valuec = strdup(value);
++ else
++ valuec = NULL;
++
++ if (mxml_set_attr(node, name, valuec))
++ free(valuec);
++}
++
++
++/*
++ * 'mxmlElementSetAttrf()' - Set an attribute with a formatted value.
++ *
++ * If the named attribute already exists, the value of the attribute
++ * is replaced by the new formatted string. The formatted string value is
++ * copied into the element node. This function does nothing if the node
++ * is not an element.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++void
++mxmlElementSetAttrf(mxml_node_t *node, /* I - Element node */
++ const char *name, /* I - Name of attribute */
++ const char *format,/* I - Printf-style attribute value */
++ ...) /* I - Additional arguments as needed */
++{
++ va_list ap; /* Argument pointer */
++ char *value; /* Value */
++
++
++#ifdef DEBUG
++ fprintf(stderr,
++ "mxmlElementSetAttrf(node=%p, name=\"%s\", format=\"%s\", ...)\n",
++ node, name ? name : "(null)", format ? format : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT || !name || !format)
++ return;
++
++ /*
++ * Format the value...
++ */
++
++ va_start(ap, format);
++ value = _mxml_vstrdupf(format, ap);
++ va_end(ap);
++
++ if (!value)
++ mxml_error("Unable to allocate memory for attribute '%s' in element %s!",
++ name, node->value.element.name);
++ else if (mxml_set_attr(node, name, value))
++ free(value);
++}
++
++
++/*
++ * 'mxml_set_attr()' - Set or add an attribute name/value pair.
++ */
++
++static int /* O - 0 on success, -1 on failure */
++mxml_set_attr(mxml_node_t *node, /* I - Element node */
++ const char *name, /* I - Attribute name */
++ char *value) /* I - Attribute value */
++{
++ int i; /* Looping var */
++ mxml_attr_t *attr; /* New attribute */
++
++
++ /*
++ * Look for the attribute...
++ */
++
++ for (i = node->value.element.num_attrs, attr = node->value.element.attrs;
++ i > 0;
++ i --, attr ++)
++ if (!strcmp(attr->name, name))
++ {
++ /*
++ * Free the old value as needed...
++ */
++
++ if (attr->value)
++ free(attr->value);
++
++ attr->value = value;
++
++ return (0);
++ }
++
++ /*
++ * Add a new attribute...
++ */
++
++ if (node->value.element.num_attrs == 0)
++ attr = malloc(sizeof(mxml_attr_t));
++ else
++ attr = realloc(node->value.element.attrs,
++ (node->value.element.num_attrs + 1) * sizeof(mxml_attr_t));
++
++ if (!attr)
++ {
++ mxml_error("Unable to allocate memory for attribute '%s' in element %s!",
++ name, node->value.element.name);
++ return (-1);
++ }
++
++ node->value.element.attrs = attr;
++ attr += node->value.element.num_attrs;
++
++ if ((attr->name = strdup(name)) == NULL)
++ {
++ mxml_error("Unable to allocate memory for attribute '%s' in element %s!",
++ name, node->value.element.name);
++ return (-1);
++ }
++
++ attr->value = value;
++
++ node->value.element.num_attrs ++;
++
++ return (0);
++}
++
++
++/*
++ * End of "$Id: mxml-attr.c 408 2010-09-19 05:26:46Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-entity.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-entity.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-entity.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-entity.c 2014-05-15 20:34:24.406204078 +0200
+@@ -0,0 +1,460 @@
++/*
++ * "$Id: mxml-entity.c 408 2010-09-19 05:26:46Z mike $"
++ *
++ * Character entity support code for Mini-XML, a small XML-like
++ * file parsing library.
++ *
++ * Copyright 2003-2010 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * mxmlEntityAddCallback() - Add a callback to convert entities to
++ * Unicode.
++ * mxmlEntityGetName() - Get the name that corresponds to the
++ * character value.
++ * mxmlEntityGetValue() - Get the character corresponding to a named
++ * entity.
++ * mxmlEntityRemoveCallback() - Remove a callback.
++ * _mxml_entity_cb() - Lookup standard (X)HTML entities.
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "mxml-private.h"
++
++
++/*
++ * 'mxmlEntityAddCallback()' - Add a callback to convert entities to Unicode.
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlEntityAddCallback(
++ mxml_entity_cb_t cb) /* I - Callback function to add */
++{
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ if (global->num_entity_cbs < (int)(sizeof(global->entity_cbs) / sizeof(global->entity_cbs[0])))
++ {
++ global->entity_cbs[global->num_entity_cbs] = cb;
++ global->num_entity_cbs ++;
++
++ return (0);
++ }
++ else
++ {
++ mxml_error("Unable to add entity callback!");
++
++ return (-1);
++ }
++}
++
++
++/*
++ * 'mxmlEntityGetName()' - Get the name that corresponds to the character value.
++ *
++ * If val does not need to be represented by a named entity, NULL is returned.
++ */
++
++const char * /* O - Entity name or NULL */
++mxmlEntityGetName(int val) /* I - Character value */
++{
++ switch (val)
++ {
++ case '&' :
++ return ("amp");
++
++ case '<' :
++ return ("lt");
++
++ case '>' :
++ return ("gt");
++
++ case '\"' :
++ return ("quot");
++
++ default :
++ return (NULL);
++ }
++}
++
++
++/*
++ * 'mxmlEntityGetValue()' - Get the character corresponding to a named entity.
++ *
++ * The entity name can also be a numeric constant. -1 is returned if the
++ * name is not known.
++ */
++
++int /* O - Character value or -1 on error */
++mxmlEntityGetValue(const char *name) /* I - Entity name */
++{
++ int i; /* Looping var */
++ int ch; /* Character value */
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ for (i = 0; i < global->num_entity_cbs; i ++)
++ if ((ch = (global->entity_cbs[i])(name)) >= 0)
++ return (ch);
++
++ return (-1);
++}
++
++
++/*
++ * 'mxmlEntityRemoveCallback()' - Remove a callback.
++ */
++
++void
++mxmlEntityRemoveCallback(
++ mxml_entity_cb_t cb) /* I - Callback function to remove */
++{
++ int i; /* Looping var */
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ for (i = 0; i < global->num_entity_cbs; i ++)
++ if (cb == global->entity_cbs[i])
++ {
++ /*
++ * Remove the callback...
++ */
++
++ global->num_entity_cbs --;
++
++ if (i < global->num_entity_cbs)
++ memmove(global->entity_cbs + i, global->entity_cbs + i + 1,
++ (global->num_entity_cbs - i) * sizeof(global->entity_cbs[0]));
++
++ return;
++ }
++}
++
++
++/*
++ * '_mxml_entity_cb()' - Lookup standard (X)HTML entities.
++ */
++
++int /* O - Unicode value or -1 */
++_mxml_entity_cb(const char *name) /* I - Entity name */
++{
++ int diff, /* Difference between names */
++ current, /* Current entity in search */
++ first, /* First entity in search */
++ last; /* Last entity in search */
++ static const struct
++ {
++ const char *name; /* Entity name */
++ int val; /* Character value */
++ } entities[] =
++ {
++ { "AElig", 198 },
++ { "Aacute", 193 },
++ { "Acirc", 194 },
++ { "Agrave", 192 },
++ { "Alpha", 913 },
++ { "Aring", 197 },
++ { "Atilde", 195 },
++ { "Auml", 196 },
++ { "Beta", 914 },
++ { "Ccedil", 199 },
++ { "Chi", 935 },
++ { "Dagger", 8225 },
++ { "Delta", 916 },
++ { "Dstrok", 208 },
++ { "ETH", 208 },
++ { "Eacute", 201 },
++ { "Ecirc", 202 },
++ { "Egrave", 200 },
++ { "Epsilon", 917 },
++ { "Eta", 919 },
++ { "Euml", 203 },
++ { "Gamma", 915 },
++ { "Iacute", 205 },
++ { "Icirc", 206 },
++ { "Igrave", 204 },
++ { "Iota", 921 },
++ { "Iuml", 207 },
++ { "Kappa", 922 },
++ { "Lambda", 923 },
++ { "Mu", 924 },
++ { "Ntilde", 209 },
++ { "Nu", 925 },
++ { "OElig", 338 },
++ { "Oacute", 211 },
++ { "Ocirc", 212 },
++ { "Ograve", 210 },
++ { "Omega", 937 },
++ { "Omicron", 927 },
++ { "Oslash", 216 },
++ { "Otilde", 213 },
++ { "Ouml", 214 },
++ { "Phi", 934 },
++ { "Pi", 928 },
++ { "Prime", 8243 },
++ { "Psi", 936 },
++ { "Rho", 929 },
++ { "Scaron", 352 },
++ { "Sigma", 931 },
++ { "THORN", 222 },
++ { "Tau", 932 },
++ { "Theta", 920 },
++ { "Uacute", 218 },
++ { "Ucirc", 219 },
++ { "Ugrave", 217 },
++ { "Upsilon", 933 },
++ { "Uuml", 220 },
++ { "Xi", 926 },
++ { "Yacute", 221 },
++ { "Yuml", 376 },
++ { "Zeta", 918 },
++ { "aacute", 225 },
++ { "acirc", 226 },
++ { "acute", 180 },
++ { "aelig", 230 },
++ { "agrave", 224 },
++ { "alefsym", 8501 },
++ { "alpha", 945 },
++ { "amp", '&' },
++ { "and", 8743 },
++ { "ang", 8736 },
++ { "apos", '\'' },
++ { "aring", 229 },
++ { "asymp", 8776 },
++ { "atilde", 227 },
++ { "auml", 228 },
++ { "bdquo", 8222 },
++ { "beta", 946 },
++ { "brkbar", 166 },
++ { "brvbar", 166 },
++ { "bull", 8226 },
++ { "cap", 8745 },
++ { "ccedil", 231 },
++ { "cedil", 184 },
++ { "cent", 162 },
++ { "chi", 967 },
++ { "circ", 710 },
++ { "clubs", 9827 },
++ { "cong", 8773 },
++ { "copy", 169 },
++ { "crarr", 8629 },
++ { "cup", 8746 },
++ { "curren", 164 },
++ { "dArr", 8659 },
++ { "dagger", 8224 },
++ { "darr", 8595 },
++ { "deg", 176 },
++ { "delta", 948 },
++ { "diams", 9830 },
++ { "die", 168 },
++ { "divide", 247 },
++ { "eacute", 233 },
++ { "ecirc", 234 },
++ { "egrave", 232 },
++ { "empty", 8709 },
++ { "emsp", 8195 },
++ { "ensp", 8194 },
++ { "epsilon", 949 },
++ { "equiv", 8801 },
++ { "eta", 951 },
++ { "eth", 240 },
++ { "euml", 235 },
++ { "euro", 8364 },
++ { "exist", 8707 },
++ { "fnof", 402 },
++ { "forall", 8704 },
++ { "frac12", 189 },
++ { "frac14", 188 },
++ { "frac34", 190 },
++ { "frasl", 8260 },
++ { "gamma", 947 },
++ { "ge", 8805 },
++ { "gt", '>' },
++ { "hArr", 8660 },
++ { "harr", 8596 },
++ { "hearts", 9829 },
++ { "hellip", 8230 },
++ { "hibar", 175 },
++ { "iacute", 237 },
++ { "icirc", 238 },
++ { "iexcl", 161 },
++ { "igrave", 236 },
++ { "image", 8465 },
++ { "infin", 8734 },
++ { "int", 8747 },
++ { "iota", 953 },
++ { "iquest", 191 },
++ { "isin", 8712 },
++ { "iuml", 239 },
++ { "kappa", 954 },
++ { "lArr", 8656 },
++ { "lambda", 955 },
++ { "lang", 9001 },
++ { "laquo", 171 },
++ { "larr", 8592 },
++ { "lceil", 8968 },
++ { "ldquo", 8220 },
++ { "le", 8804 },
++ { "lfloor", 8970 },
++ { "lowast", 8727 },
++ { "loz", 9674 },
++ { "lrm", 8206 },
++ { "lsaquo", 8249 },
++ { "lsquo", 8216 },
++ { "lt", '<' },
++ { "macr", 175 },
++ { "mdash", 8212 },
++ { "micro", 181 },
++ { "middot", 183 },
++ { "minus", 8722 },
++ { "mu", 956 },
++ { "nabla", 8711 },
++ { "nbsp", 160 },
++ { "ndash", 8211 },
++ { "ne", 8800 },
++ { "ni", 8715 },
++ { "not", 172 },
++ { "notin", 8713 },
++ { "nsub", 8836 },
++ { "ntilde", 241 },
++ { "nu", 957 },
++ { "oacute", 243 },
++ { "ocirc", 244 },
++ { "oelig", 339 },
++ { "ograve", 242 },
++ { "oline", 8254 },
++ { "omega", 969 },
++ { "omicron", 959 },
++ { "oplus", 8853 },
++ { "or", 8744 },
++ { "ordf", 170 },
++ { "ordm", 186 },
++ { "oslash", 248 },
++ { "otilde", 245 },
++ { "otimes", 8855 },
++ { "ouml", 246 },
++ { "para", 182 },
++ { "part", 8706 },
++ { "permil", 8240 },
++ { "perp", 8869 },
++ { "phi", 966 },
++ { "pi", 960 },
++ { "piv", 982 },
++ { "plusmn", 177 },
++ { "pound", 163 },
++ { "prime", 8242 },
++ { "prod", 8719 },
++ { "prop", 8733 },
++ { "psi", 968 },
++ { "quot", '\"' },
++ { "rArr", 8658 },
++ { "radic", 8730 },
++ { "rang", 9002 },
++ { "raquo", 187 },
++ { "rarr", 8594 },
++ { "rceil", 8969 },
++ { "rdquo", 8221 },
++ { "real", 8476 },
++ { "reg", 174 },
++ { "rfloor", 8971 },
++ { "rho", 961 },
++ { "rlm", 8207 },
++ { "rsaquo", 8250 },
++ { "rsquo", 8217 },
++ { "sbquo", 8218 },
++ { "scaron", 353 },
++ { "sdot", 8901 },
++ { "sect", 167 },
++ { "shy", 173 },
++ { "sigma", 963 },
++ { "sigmaf", 962 },
++ { "sim", 8764 },
++ { "spades", 9824 },
++ { "sub", 8834 },
++ { "sube", 8838 },
++ { "sum", 8721 },
++ { "sup", 8835 },
++ { "sup1", 185 },
++ { "sup2", 178 },
++ { "sup3", 179 },
++ { "supe", 8839 },
++ { "szlig", 223 },
++ { "tau", 964 },
++ { "there4", 8756 },
++ { "theta", 952 },
++ { "thetasym", 977 },
++ { "thinsp", 8201 },
++ { "thorn", 254 },
++ { "tilde", 732 },
++ { "times", 215 },
++ { "trade", 8482 },
++ { "uArr", 8657 },
++ { "uacute", 250 },
++ { "uarr", 8593 },
++ { "ucirc", 251 },
++ { "ugrave", 249 },
++ { "uml", 168 },
++ { "upsih", 978 },
++ { "upsilon", 965 },
++ { "uuml", 252 },
++ { "weierp", 8472 },
++ { "xi", 958 },
++ { "yacute", 253 },
++ { "yen", 165 },
++ { "yuml", 255 },
++ { "zeta", 950 },
++ { "zwj", 8205 },
++ { "zwnj", 8204 }
++ };
++
++
++ /*
++ * Do a binary search for the named entity...
++ */
++
++ first = 0;
++ last = (int)(sizeof(entities) / sizeof(entities[0]) - 1);
++
++ while ((last - first) > 1)
++ {
++ current = (first + last) / 2;
++
++ if ((diff = strcmp(name, entities[current].name)) == 0)
++ return (entities[current].val);
++ else if (diff < 0)
++ last = current;
++ else
++ first = current;
++ }
++
++ /*
++ * If we get here, there is a small chance that there is still
++ * a match; check first and last...
++ */
++
++ if (!strcmp(name, entities[first].name))
++ return (entities[first].val);
++ else if (!strcmp(name, entities[last].name))
++ return (entities[last].val);
++ else
++ return (-1);
++}
++
++
++/*
++ * End of "$Id: mxml-entity.c 408 2010-09-19 05:26:46Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-file.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-file.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-file.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-file.c 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,3082 @@
++/*
++ * "$Id: mxml-file.c 438 2011-03-24 05:47:51Z mike $"
++ *
++ * File loading code for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2011 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * mxmlLoadFd() - Load a file descriptor into an XML node tree.
++ * mxmlLoadFile() - Load a file into an XML node tree.
++ * mxmlLoadString() - Load a string into an XML node tree.
++ * mxmlSaveAllocString() - Save an XML tree to an allocated string.
++ * mxmlSaveFd() - Save an XML tree to a file descriptor.
++ * mxmlSaveFile() - Save an XML tree to a file.
++ * mxmlSaveString() - Save an XML node tree to a string.
++ * mxmlSAXLoadFd() - Load a file descriptor into an XML node tree
++ * using a SAX callback.
++ * mxmlSAXLoadFile() - Load a file into an XML node tree
++ * using a SAX callback.
++ * mxmlSAXLoadString() - Load a string into an XML node tree
++ * using a SAX callback.
++ * mxmlSetCustomHandlers() - Set the handling functions for custom data.
++ * mxmlSetErrorCallback() - Set the error message callback.
++ * mxmlSetWrapMargin() - Set the wrap margin when saving XML data.
++ * mxml_add_char() - Add a character to a buffer, expanding as needed.
++ * mxml_fd_getc() - Read a character from a file descriptor.
++ * mxml_fd_putc() - Write a character to a file descriptor.
++ * mxml_fd_read() - Read a buffer of data from a file descriptor.
++ * mxml_fd_write() - Write a buffer of data to a file descriptor.
++ * mxml_file_getc() - Get a character from a file.
++ * mxml_file_putc() - Write a character to a file.
++ * mxml_get_entity() - Get the character corresponding to an entity...
++ * mxml_load_data() - Load data into an XML node tree.
++ * mxml_parse_element() - Parse an element for any attributes...
++ * mxml_string_getc() - Get a character from a string.
++ * mxml_string_putc() - Write a character to a string.
++ * mxml_write_name() - Write a name string.
++ * mxml_write_node() - Save an XML node to a file.
++ * mxml_write_string() - Write a string, escaping & and < as needed.
++ * mxml_write_ws() - Do whitespace callback...
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#ifndef WIN32
++# include <unistd.h>
++#endif /* !WIN32 */
++#include "mxml-private.h"
++
++
++/*
++ * Character encoding...
++ */
++
++#define ENCODE_UTF8 0 /* UTF-8 */
++#define ENCODE_UTF16BE 1 /* UTF-16 Big-Endian */
++#define ENCODE_UTF16LE 2 /* UTF-16 Little-Endian */
++
++
++/*
++ * Macro to test for a bad XML character...
++ */
++
++#define mxml_bad_char(ch) ((ch) < ' ' && (ch) != '\n' && (ch) != '\r' && (ch) != '\t')
++
++
++/*
++ * Types and structures...
++ */
++
++typedef int (*_mxml_getc_cb_t)(void *, int *);
++typedef int (*_mxml_putc_cb_t)(int, void *);
++
++typedef struct _mxml_fdbuf_s /**** File descriptor buffer ****/
++{
++ int fd; /* File descriptor */
++ unsigned char *current, /* Current position in buffer */
++ *end, /* End of buffer */
++ buffer[8192]; /* Character buffer */
++} _mxml_fdbuf_t;
++
++
++/*
++ * Local functions...
++ */
++
++static int mxml_add_char(int ch, char **ptr, char **buffer,
++ int *bufsize);
++static int mxml_fd_getc(void *p, int *encoding);
++static int mxml_fd_putc(int ch, void *p);
++static int mxml_fd_read(_mxml_fdbuf_t *buf);
++static int mxml_fd_write(_mxml_fdbuf_t *buf);
++static int mxml_file_getc(void *p, int *encoding);
++static int mxml_file_putc(int ch, void *p);
++static int mxml_get_entity(mxml_node_t *parent, void *p,
++ int *encoding,
++ _mxml_getc_cb_t getc_cb);
++static inline int mxml_isspace(int ch)
++ {
++ return (ch == ' ' || ch == '\t' || ch == '\r' ||
++ ch == '\n');
++ }
++static mxml_node_t *mxml_load_data(mxml_node_t *top, void *p,
++ mxml_load_cb_t cb,
++ _mxml_getc_cb_t getc_cb,
++ mxml_sax_cb_t sax_cb, void *sax_data);
++static int mxml_parse_element(mxml_node_t *node, void *p,
++ int *encoding,
++ _mxml_getc_cb_t getc_cb);
++static int mxml_string_getc(void *p, int *encoding);
++static int mxml_string_putc(int ch, void *p);
++static int mxml_write_name(const char *s, void *p,
++ _mxml_putc_cb_t putc_cb);
++static int mxml_write_node(mxml_node_t *node, void *p,
++ mxml_save_cb_t cb, int col,
++ _mxml_putc_cb_t putc_cb,
++ _mxml_global_t *global);
++static int mxml_write_string(const char *s, void *p,
++ _mxml_putc_cb_t putc_cb);
++static int mxml_write_ws(mxml_node_t *node, void *p,
++ mxml_save_cb_t cb, int ws,
++ int col, _mxml_putc_cb_t putc_cb);
++
++
++/*
++ * 'mxmlLoadFd()' - Load a file descriptor into an XML node tree.
++ *
++ * The nodes in the specified file are added to the specified top node.
++ * If no top node is provided, the XML file MUST be well-formed with a
++ * single parent node like <?xml> for the entire file. The callback
++ * function returns the value type that should be used for child nodes.
++ * If MXML_NO_CALLBACK is specified then all child nodes will be either
++ * MXML_ELEMENT or MXML_TEXT nodes.
++ *
++ * The constants MXML_INTEGER_CALLBACK, MXML_OPAQUE_CALLBACK,
++ * MXML_REAL_CALLBACK, and MXML_TEXT_CALLBACK are defined for loading
++ * child nodes of the specified type.
++ */
++
++mxml_node_t * /* O - First node or NULL if the file could not be read. */
++mxmlLoadFd(mxml_node_t *top, /* I - Top node */
++ int fd, /* I - File descriptor to read from */
++ mxml_load_cb_t cb) /* I - Callback function or MXML_NO_CALLBACK */
++{
++ _mxml_fdbuf_t buf; /* File descriptor buffer */
++
++
++ /*
++ * Initialize the file descriptor buffer...
++ */
++
++ buf.fd = fd;
++ buf.current = buf.buffer;
++ buf.end = buf.buffer;
++
++ /*
++ * Read the XML data...
++ */
++
++ return (mxml_load_data(top, &buf, cb, mxml_fd_getc, MXML_NO_CALLBACK, NULL));
++}
++
++
++/*
++ * 'mxmlLoadFile()' - Load a file into an XML node tree.
++ *
++ * The nodes in the specified file are added to the specified top node.
++ * If no top node is provided, the XML file MUST be well-formed with a
++ * single parent node like <?xml> for the entire file. The callback
++ * function returns the value type that should be used for child nodes.
++ * If MXML_NO_CALLBACK is specified then all child nodes will be either
++ * MXML_ELEMENT or MXML_TEXT nodes.
++ *
++ * The constants MXML_INTEGER_CALLBACK, MXML_OPAQUE_CALLBACK,
++ * MXML_REAL_CALLBACK, and MXML_TEXT_CALLBACK are defined for loading
++ * child nodes of the specified type.
++ */
++
++mxml_node_t * /* O - First node or NULL if the file could not be read. */
++mxmlLoadFile(mxml_node_t *top, /* I - Top node */
++ FILE *fp, /* I - File to read from */
++ mxml_load_cb_t cb) /* I - Callback function or MXML_NO_CALLBACK */
++{
++ /*
++ * Read the XML data...
++ */
++
++ return (mxml_load_data(top, fp, cb, mxml_file_getc, MXML_NO_CALLBACK, NULL));
++}
++
++
++/*
++ * 'mxmlLoadString()' - Load a string into an XML node tree.
++ *
++ * The nodes in the specified string are added to the specified top node.
++ * If no top node is provided, the XML string MUST be well-formed with a
++ * single parent node like <?xml> for the entire string. The callback
++ * function returns the value type that should be used for child nodes.
++ * If MXML_NO_CALLBACK is specified then all child nodes will be either
++ * MXML_ELEMENT or MXML_TEXT nodes.
++ *
++ * The constants MXML_INTEGER_CALLBACK, MXML_OPAQUE_CALLBACK,
++ * MXML_REAL_CALLBACK, and MXML_TEXT_CALLBACK are defined for loading
++ * child nodes of the specified type.
++ */
++
++mxml_node_t * /* O - First node or NULL if the string has errors. */
++mxmlLoadString(mxml_node_t *top, /* I - Top node */
++ const char *s, /* I - String to load */
++ mxml_load_cb_t cb) /* I - Callback function or MXML_NO_CALLBACK */
++{
++ /*
++ * Read the XML data...
++ */
++
++ return (mxml_load_data(top, (void *)&s, cb, mxml_string_getc, MXML_NO_CALLBACK,
++ NULL));
++}
++
++
++/*
++ * 'mxmlSaveAllocString()' - Save an XML tree to an allocated string.
++ *
++ * This function returns a pointer to a string containing the textual
++ * representation of the XML node tree. The string should be freed
++ * using the free() function when you are done with it. NULL is returned
++ * if the node would produce an empty string or if the string cannot be
++ * allocated.
++ *
++ * The callback argument specifies a function that returns a whitespace
++ * string or NULL before and after each element. If MXML_NO_CALLBACK
++ * is specified, whitespace will only be added before MXML_TEXT nodes
++ * with leading whitespace and before attribute names inside opening
++ * element tags.
++ */
++
++char * /* O - Allocated string or NULL */
++mxmlSaveAllocString(
++ mxml_node_t *node, /* I - Node to write */
++ mxml_save_cb_t cb) /* I - Whitespace callback or MXML_NO_CALLBACK */
++{
++ int bytes; /* Required bytes */
++ char buffer[8192]; /* Temporary buffer */
++ char *s; /* Allocated string */
++
++
++ /*
++ * Write the node to the temporary buffer...
++ */
++
++ bytes = mxmlSaveString(node, buffer, sizeof(buffer), cb);
++
++ if (bytes <= 0)
++ return (NULL);
++
++ if (bytes < (int)(sizeof(buffer) - 1))
++ {
++ /*
++ * Node fit inside the buffer, so just duplicate that string and
++ * return...
++ */
++
++ return (strdup(buffer));
++ }
++
++ /*
++ * Allocate a buffer of the required size and save the node to the
++ * new buffer...
++ */
++
++ if ((s = malloc(bytes + 1)) == NULL)
++ return (NULL);
++
++ mxmlSaveString(node, s, bytes + 1, cb);
++
++ /*
++ * Return the allocated string...
++ */
++
++ return (s);
++}
++
++
++/*
++ * 'mxmlSaveFd()' - Save an XML tree to a file descriptor.
++ *
++ * The callback argument specifies a function that returns a whitespace
++ * string or NULL before and after each element. If MXML_NO_CALLBACK
++ * is specified, whitespace will only be added before MXML_TEXT nodes
++ * with leading whitespace and before attribute names inside opening
++ * element tags.
++ */
++
++int /* O - 0 on success, -1 on error. */
++mxmlSaveFd(mxml_node_t *node, /* I - Node to write */
++ int fd, /* I - File descriptor to write to */
++ mxml_save_cb_t cb) /* I - Whitespace callback or MXML_NO_CALLBACK */
++{
++ int col; /* Final column */
++ _mxml_fdbuf_t buf; /* File descriptor buffer */
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ /*
++ * Initialize the file descriptor buffer...
++ */
++
++ buf.fd = fd;
++ buf.current = buf.buffer;
++ buf.end = buf.buffer + sizeof(buf.buffer);
++
++ /*
++ * Write the node...
++ */
++
++ if ((col = mxml_write_node(node, &buf, cb, 0, mxml_fd_putc, global)) < 0)
++ return (-1);
++
++ if (col > 0)
++ if (mxml_fd_putc('\n', &buf) < 0)
++ return (-1);
++
++ /*
++ * Flush and return...
++ */
++
++ return (mxml_fd_write(&buf));
++}
++
++
++/*
++ * 'mxmlSaveFile()' - Save an XML tree to a file.
++ *
++ * The callback argument specifies a function that returns a whitespace
++ * string or NULL before and after each element. If MXML_NO_CALLBACK
++ * is specified, whitespace will only be added before MXML_TEXT nodes
++ * with leading whitespace and before attribute names inside opening
++ * element tags.
++ */
++
++int /* O - 0 on success, -1 on error. */
++mxmlSaveFile(mxml_node_t *node, /* I - Node to write */
++ FILE *fp, /* I - File to write to */
++ mxml_save_cb_t cb) /* I - Whitespace callback or MXML_NO_CALLBACK */
++{
++ int col; /* Final column */
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ /*
++ * Write the node...
++ */
++
++ if ((col = mxml_write_node(node, fp, cb, 0, mxml_file_putc, global)) < 0)
++ return (-1);
++
++ if (col > 0)
++ if (putc('\n', fp) < 0)
++ return (-1);
++
++ /*
++ * Return 0 (success)...
++ */
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSaveString()' - Save an XML node tree to a string.
++ *
++ * This function returns the total number of bytes that would be
++ * required for the string but only copies (bufsize - 1) characters
++ * into the specified buffer.
++ *
++ * The callback argument specifies a function that returns a whitespace
++ * string or NULL before and after each element. If MXML_NO_CALLBACK
++ * is specified, whitespace will only be added before MXML_TEXT nodes
++ * with leading whitespace and before attribute names inside opening
++ * element tags.
++ */
++
++int /* O - Size of string */
++mxmlSaveString(mxml_node_t *node, /* I - Node to write */
++ char *buffer, /* I - String buffer */
++ int bufsize, /* I - Size of string buffer */
++ mxml_save_cb_t cb) /* I - Whitespace callback or MXML_NO_CALLBACK */
++{
++ int col; /* Final column */
++ char *ptr[2]; /* Pointers for putc_cb */
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ /*
++ * Write the node...
++ */
++
++ ptr[0] = buffer;
++ ptr[1] = buffer + bufsize;
++
++ if ((col = mxml_write_node(node, ptr, cb, 0, mxml_string_putc, global)) < 0)
++ return (-1);
++
++ if (col > 0)
++ mxml_string_putc('\n', ptr);
++
++ /*
++ * Nul-terminate the buffer...
++ */
++
++ if (ptr[0] >= ptr[1])
++ buffer[bufsize - 1] = '\0';
++ else
++ ptr[0][0] = '\0';
++
++ /*
++ * Return the number of characters...
++ */
++
++ return (ptr[0] - buffer);
++}
++
++
++/*
++ * 'mxmlSAXLoadFd()' - Load a file descriptor into an XML node tree
++ * using a SAX callback.
++ *
++ * The nodes in the specified file are added to the specified top node.
++ * If no top node is provided, the XML file MUST be well-formed with a
++ * single parent node like <?xml> for the entire file. The callback
++ * function returns the value type that should be used for child nodes.
++ * If MXML_NO_CALLBACK is specified then all child nodes will be either
++ * MXML_ELEMENT or MXML_TEXT nodes.
++ *
++ * The constants MXML_INTEGER_CALLBACK, MXML_OPAQUE_CALLBACK,
++ * MXML_REAL_CALLBACK, and MXML_TEXT_CALLBACK are defined for loading
++ * child nodes of the specified type.
++ *
++ * The SAX callback must call mxmlRetain() for any nodes that need to
++ * be kept for later use. Otherwise, nodes are deleted when the parent
++ * node is closed or after each data, comment, CDATA, or directive node.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++mxml_node_t * /* O - First node or NULL if the file could not be read. */
++mxmlSAXLoadFd(mxml_node_t *top, /* I - Top node */
++ int fd, /* I - File descriptor to read from */
++ mxml_load_cb_t cb, /* I - Callback function or MXML_NO_CALLBACK */
++ mxml_sax_cb_t sax_cb, /* I - SAX callback or MXML_NO_CALLBACK */
++ void *sax_data) /* I - SAX user data */
++{
++ _mxml_fdbuf_t buf; /* File descriptor buffer */
++
++
++ /*
++ * Initialize the file descriptor buffer...
++ */
++
++ buf.fd = fd;
++ buf.current = buf.buffer;
++ buf.end = buf.buffer;
++
++ /*
++ * Read the XML data...
++ */
++
++ return (mxml_load_data(top, &buf, cb, mxml_fd_getc, sax_cb, sax_data));
++}
++
++
++/*
++ * 'mxmlSAXLoadFile()' - Load a file into an XML node tree
++ * using a SAX callback.
++ *
++ * The nodes in the specified file are added to the specified top node.
++ * If no top node is provided, the XML file MUST be well-formed with a
++ * single parent node like <?xml> for the entire file. The callback
++ * function returns the value type that should be used for child nodes.
++ * If MXML_NO_CALLBACK is specified then all child nodes will be either
++ * MXML_ELEMENT or MXML_TEXT nodes.
++ *
++ * The constants MXML_INTEGER_CALLBACK, MXML_OPAQUE_CALLBACK,
++ * MXML_REAL_CALLBACK, and MXML_TEXT_CALLBACK are defined for loading
++ * child nodes of the specified type.
++ *
++ * The SAX callback must call mxmlRetain() for any nodes that need to
++ * be kept for later use. Otherwise, nodes are deleted when the parent
++ * node is closed or after each data, comment, CDATA, or directive node.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++mxml_node_t * /* O - First node or NULL if the file could not be read. */
++mxmlSAXLoadFile(
++ mxml_node_t *top, /* I - Top node */
++ FILE *fp, /* I - File to read from */
++ mxml_load_cb_t cb, /* I - Callback function or MXML_NO_CALLBACK */
++ mxml_sax_cb_t sax_cb, /* I - SAX callback or MXML_NO_CALLBACK */
++ void *sax_data) /* I - SAX user data */
++{
++ /*
++ * Read the XML data...
++ */
++
++ return (mxml_load_data(top, fp, cb, mxml_file_getc, sax_cb, sax_data));
++}
++
++
++/*
++ * 'mxmlSAXLoadString()' - Load a string into an XML node tree
++ * using a SAX callback.
++ *
++ * The nodes in the specified string are added to the specified top node.
++ * If no top node is provided, the XML string MUST be well-formed with a
++ * single parent node like <?xml> for the entire string. The callback
++ * function returns the value type that should be used for child nodes.
++ * If MXML_NO_CALLBACK is specified then all child nodes will be either
++ * MXML_ELEMENT or MXML_TEXT nodes.
++ *
++ * The constants MXML_INTEGER_CALLBACK, MXML_OPAQUE_CALLBACK,
++ * MXML_REAL_CALLBACK, and MXML_TEXT_CALLBACK are defined for loading
++ * child nodes of the specified type.
++ *
++ * The SAX callback must call mxmlRetain() for any nodes that need to
++ * be kept for later use. Otherwise, nodes are deleted when the parent
++ * node is closed or after each data, comment, CDATA, or directive node.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++mxml_node_t * /* O - First node or NULL if the string has errors. */
++mxmlSAXLoadString(
++ mxml_node_t *top, /* I - Top node */
++ const char *s, /* I - String to load */
++ mxml_load_cb_t cb, /* I - Callback function or MXML_NO_CALLBACK */
++ mxml_sax_cb_t sax_cb, /* I - SAX callback or MXML_NO_CALLBACK */
++ void *sax_data) /* I - SAX user data */
++{
++ /*
++ * Read the XML data...
++ */
++
++ return (mxml_load_data(top, (void *)&s, cb, mxml_string_getc, sax_cb, sax_data));
++}
++
++
++/*
++ * 'mxmlSetCustomHandlers()' - Set the handling functions for custom data.
++ *
++ * The load function accepts a node pointer and a data string and must
++ * return 0 on success and non-zero on error.
++ *
++ * The save function accepts a node pointer and must return a malloc'd
++ * string on success and NULL on error.
++ *
++ */
++
++void
++mxmlSetCustomHandlers(
++ mxml_custom_load_cb_t load, /* I - Load function */
++ mxml_custom_save_cb_t save) /* I - Save function */
++{
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ global->custom_load_cb = load;
++ global->custom_save_cb = save;
++}
++
++
++/*
++ * 'mxmlSetErrorCallback()' - Set the error message callback.
++ */
++
++void
++mxmlSetErrorCallback(mxml_error_cb_t cb)/* I - Error callback function */
++{
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ global->error_cb = cb;
++}
++
++
++/*
++ * 'mxmlSetWrapMargin()' - Set the wrap margin when saving XML data.
++ *
++ * Wrapping is disabled when "column" is 0.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++void
++mxmlSetWrapMargin(int column) /* I - Column for wrapping, 0 to disable wrapping */
++{
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ global->wrap = column;
++}
++
++
++/*
++ * 'mxml_add_char()' - Add a character to a buffer, expanding as needed.
++ */
++
++static int /* O - 0 on success, -1 on error */
++mxml_add_char(int ch, /* I - Character to add */
++ char **bufptr, /* IO - Current position in buffer */
++ char **buffer, /* IO - Current buffer */
++ int *bufsize) /* IO - Current buffer size */
++{
++ char *newbuffer; /* New buffer value */
++
++
++ if (*bufptr >= (*buffer + *bufsize - 4))
++ {
++ /*
++ * Increase the size of the buffer...
++ */
++
++ if (*bufsize < 1024)
++ (*bufsize) *= 2;
++ else
++ (*bufsize) += 1024;
++
++ if ((newbuffer = realloc(*buffer, *bufsize)) == NULL)
++ {
++ free(*buffer);
++
++ mxml_error("Unable to expand string buffer to %d bytes!", *bufsize);
++
++ return (-1);
++ }
++
++ *bufptr = newbuffer + (*bufptr - *buffer);
++ *buffer = newbuffer;
++ }
++
++ if (ch < 0x80)
++ {
++ /*
++ * Single byte ASCII...
++ */
++
++ *(*bufptr)++ = ch;
++ }
++ else if (ch < 0x800)
++ {
++ /*
++ * Two-byte UTF-8...
++ */
++
++ *(*bufptr)++ = 0xc0 | (ch >> 6);
++ *(*bufptr)++ = 0x80 | (ch & 0x3f);
++ }
++ else if (ch < 0x10000)
++ {
++ /*
++ * Three-byte UTF-8...
++ */
++
++ *(*bufptr)++ = 0xe0 | (ch >> 12);
++ *(*bufptr)++ = 0x80 | ((ch >> 6) & 0x3f);
++ *(*bufptr)++ = 0x80 | (ch & 0x3f);
++ }
++ else
++ {
++ /*
++ * Four-byte UTF-8...
++ */
++
++ *(*bufptr)++ = 0xf0 | (ch >> 18);
++ *(*bufptr)++ = 0x80 | ((ch >> 12) & 0x3f);
++ *(*bufptr)++ = 0x80 | ((ch >> 6) & 0x3f);
++ *(*bufptr)++ = 0x80 | (ch & 0x3f);
++ }
++
++ return (0);
++}
++
++
++/*
++ * 'mxml_fd_getc()' - Read a character from a file descriptor.
++ */
++
++static int /* O - Character or EOF */
++mxml_fd_getc(void *p, /* I - File descriptor buffer */
++ int *encoding) /* IO - Encoding */
++{
++ _mxml_fdbuf_t *buf; /* File descriptor buffer */
++ int ch, /* Current character */
++ temp; /* Temporary character */
++
++
++ /*
++ * Grab the next character in the buffer...
++ */
++
++ buf = (_mxml_fdbuf_t *)p;
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ ch = *(buf->current)++;
++
++ switch (*encoding)
++ {
++ case ENCODE_UTF8 :
++ /*
++ * Got a UTF-8 character; convert UTF-8 to Unicode and return...
++ */
++
++ if (!(ch & 0x80))
++ {
++#if DEBUG > 1
++ printf("mxml_fd_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++
++ return (ch);
++ }
++ else if (ch == 0xfe)
++ {
++ /*
++ * UTF-16 big-endian BOM?
++ */
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ ch = *(buf->current)++;
++
++ if (ch != 0xff)
++ return (EOF);
++
++ *encoding = ENCODE_UTF16BE;
++
++ return (mxml_fd_getc(p, encoding));
++ }
++ else if (ch == 0xff)
++ {
++ /*
++ * UTF-16 little-endian BOM?
++ */
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ ch = *(buf->current)++;
++
++ if (ch != 0xfe)
++ return (EOF);
++
++ *encoding = ENCODE_UTF16LE;
++
++ return (mxml_fd_getc(p, encoding));
++ }
++ else if ((ch & 0xe0) == 0xc0)
++ {
++ /*
++ * Two-byte value...
++ */
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ if ((temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((ch & 0x1f) << 6) | (temp & 0x3f);
++
++ if (ch < 0x80)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++ }
++ else if ((ch & 0xf0) == 0xe0)
++ {
++ /*
++ * Three-byte value...
++ */
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ if ((temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((ch & 0x0f) << 6) | (temp & 0x3f);
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ if ((temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = (ch << 6) | (temp & 0x3f);
++
++ if (ch < 0x800)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++
++ /*
++ * Ignore (strip) Byte Order Mark (BOM)...
++ */
++
++ if (ch == 0xfeff)
++ return (mxml_fd_getc(p, encoding));
++ }
++ else if ((ch & 0xf8) == 0xf0)
++ {
++ /*
++ * Four-byte value...
++ */
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ if ((temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((ch & 0x07) << 6) | (temp & 0x3f);
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ if ((temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = (ch << 6) | (temp & 0x3f);
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ if ((temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = (ch << 6) | (temp & 0x3f);
++
++ if (ch < 0x10000)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++ }
++ else
++ return (EOF);
++ break;
++
++ case ENCODE_UTF16BE :
++ /*
++ * Read UTF-16 big-endian char...
++ */
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ ch = (ch << 8) | temp;
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++ else if (ch >= 0xd800 && ch <= 0xdbff)
++ {
++ /*
++ * Multi-word UTF-16 char...
++ */
++
++ int lch;
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ lch = *(buf->current)++;
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ lch = (lch << 8) | temp;
++
++ if (lch < 0xdc00 || lch >= 0xdfff)
++ return (EOF);
++
++ ch = (((ch & 0x3ff) << 10) | (lch & 0x3ff)) + 0x10000;
++ }
++ break;
++
++ case ENCODE_UTF16LE :
++ /*
++ * Read UTF-16 little-endian char...
++ */
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ ch |= (temp << 8);
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++ else if (ch >= 0xd800 && ch <= 0xdbff)
++ {
++ /*
++ * Multi-word UTF-16 char...
++ */
++
++ int lch;
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ lch = *(buf->current)++;
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_read(buf) < 0)
++ return (EOF);
++
++ temp = *(buf->current)++;
++
++ lch |= (temp << 8);
++
++ if (lch < 0xdc00 || lch >= 0xdfff)
++ return (EOF);
++
++ ch = (((ch & 0x3ff) << 10) | (lch & 0x3ff)) + 0x10000;
++ }
++ break;
++ }
++
++#if DEBUG > 1
++ printf("mxml_fd_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ return (ch);
++}
++
++
++/*
++ * 'mxml_fd_putc()' - Write a character to a file descriptor.
++ */
++
++static int /* O - 0 on success, -1 on error */
++mxml_fd_putc(int ch, /* I - Character */
++ void *p) /* I - File descriptor buffer */
++{
++ _mxml_fdbuf_t *buf; /* File descriptor buffer */
++
++
++ /*
++ * Flush the write buffer as needed...
++ */
++
++ buf = (_mxml_fdbuf_t *)p;
++
++ if (buf->current >= buf->end)
++ if (mxml_fd_write(buf) < 0)
++ return (-1);
++
++ *(buf->current)++ = ch;
++
++ /*
++ * Return successfully...
++ */
++
++ return (0);
++}
++
++
++/*
++ * 'mxml_fd_read()' - Read a buffer of data from a file descriptor.
++ */
++
++static int /* O - 0 on success, -1 on error */
++mxml_fd_read(_mxml_fdbuf_t *buf) /* I - File descriptor buffer */
++{
++ int bytes; /* Bytes read... */
++
++
++ /*
++ * Range check input...
++ */
++
++ if (!buf)
++ return (-1);
++
++ /*
++ * Read from the file descriptor...
++ */
++
++ while ((bytes = read(buf->fd, buf->buffer, sizeof(buf->buffer))) < 0)
++#ifdef EINTR
++ if (errno != EAGAIN && errno != EINTR)
++#else
++ if (errno != EAGAIN)
++#endif /* EINTR */
++ return (-1);
++
++ if (bytes == 0)
++ return (-1);
++
++ /*
++ * Update the pointers and return success...
++ */
++
++ buf->current = buf->buffer;
++ buf->end = buf->buffer + bytes;
++
++ return (0);
++}
++
++
++/*
++ * 'mxml_fd_write()' - Write a buffer of data to a file descriptor.
++ */
++
++static int /* O - 0 on success, -1 on error */
++mxml_fd_write(_mxml_fdbuf_t *buf) /* I - File descriptor buffer */
++{
++ int bytes; /* Bytes written */
++ unsigned char *ptr; /* Pointer into buffer */
++
++
++ /*
++ * Range check...
++ */
++
++ if (!buf)
++ return (-1);
++
++ /*
++ * Return 0 if there is nothing to write...
++ */
++
++ if (buf->current == buf->buffer)
++ return (0);
++
++ /*
++ * Loop until we have written everything...
++ */
++
++ for (ptr = buf->buffer; ptr < buf->current; ptr += bytes)
++ if ((bytes = write(buf->fd, ptr, buf->current - ptr)) < 0)
++ return (-1);
++
++ /*
++ * All done, reset pointers and return success...
++ */
++
++ buf->current = buf->buffer;
++
++ return (0);
++}
++
++
++/*
++ * 'mxml_file_getc()' - Get a character from a file.
++ */
++
++static int /* O - Character or EOF */
++mxml_file_getc(void *p, /* I - Pointer to file */
++ int *encoding) /* IO - Encoding */
++{
++ int ch, /* Character from file */
++ temp; /* Temporary character */
++ FILE *fp; /* Pointer to file */
++
++
++ /*
++ * Read a character from the file and see if it is EOF or ASCII...
++ */
++
++ fp = (FILE *)p;
++ ch = getc(fp);
++
++ if (ch == EOF)
++ return (EOF);
++
++ switch (*encoding)
++ {
++ case ENCODE_UTF8 :
++ /*
++ * Got a UTF-8 character; convert UTF-8 to Unicode and return...
++ */
++
++ if (!(ch & 0x80))
++ {
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++
++#if DEBUG > 1
++ printf("mxml_file_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ return (ch);
++ }
++ else if (ch == 0xfe)
++ {
++ /*
++ * UTF-16 big-endian BOM?
++ */
++
++ ch = getc(fp);
++ if (ch != 0xff)
++ return (EOF);
++
++ *encoding = ENCODE_UTF16BE;
++
++ return (mxml_file_getc(p, encoding));
++ }
++ else if (ch == 0xff)
++ {
++ /*
++ * UTF-16 little-endian BOM?
++ */
++
++ ch = getc(fp);
++ if (ch != 0xfe)
++ return (EOF);
++
++ *encoding = ENCODE_UTF16LE;
++
++ return (mxml_file_getc(p, encoding));
++ }
++ else if ((ch & 0xe0) == 0xc0)
++ {
++ /*
++ * Two-byte value...
++ */
++
++ if ((temp = getc(fp)) == EOF || (temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((ch & 0x1f) << 6) | (temp & 0x3f);
++
++ if (ch < 0x80)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++ }
++ else if ((ch & 0xf0) == 0xe0)
++ {
++ /*
++ * Three-byte value...
++ */
++
++ if ((temp = getc(fp)) == EOF || (temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((ch & 0x0f) << 6) | (temp & 0x3f);
++
++ if ((temp = getc(fp)) == EOF || (temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = (ch << 6) | (temp & 0x3f);
++
++ if (ch < 0x800)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++
++ /*
++ * Ignore (strip) Byte Order Mark (BOM)...
++ */
++
++ if (ch == 0xfeff)
++ return (mxml_file_getc(p, encoding));
++ }
++ else if ((ch & 0xf8) == 0xf0)
++ {
++ /*
++ * Four-byte value...
++ */
++
++ if ((temp = getc(fp)) == EOF || (temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((ch & 0x07) << 6) | (temp & 0x3f);
++
++ if ((temp = getc(fp)) == EOF || (temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = (ch << 6) | (temp & 0x3f);
++
++ if ((temp = getc(fp)) == EOF || (temp & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = (ch << 6) | (temp & 0x3f);
++
++ if (ch < 0x10000)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++ }
++ else
++ return (EOF);
++ break;
++
++ case ENCODE_UTF16BE :
++ /*
++ * Read UTF-16 big-endian char...
++ */
++
++ ch = (ch << 8) | getc(fp);
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++ else if (ch >= 0xd800 && ch <= 0xdbff)
++ {
++ /*
++ * Multi-word UTF-16 char...
++ */
++
++ int lch = (getc(fp) << 8);
++ lch |= getc(fp);
++
++ if (lch < 0xdc00 || lch >= 0xdfff)
++ return (EOF);
++
++ ch = (((ch & 0x3ff) << 10) | (lch & 0x3ff)) + 0x10000;
++ }
++ break;
++
++ case ENCODE_UTF16LE :
++ /*
++ * Read UTF-16 little-endian char...
++ */
++
++ ch |= (getc(fp) << 8);
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++ else if (ch >= 0xd800 && ch <= 0xdbff)
++ {
++ /*
++ * Multi-word UTF-16 char...
++ */
++
++ int lch = getc(fp);
++ lch |= (getc(fp) << 8);
++
++ if (lch < 0xdc00 || lch >= 0xdfff)
++ return (EOF);
++
++ ch = (((ch & 0x3ff) << 10) | (lch & 0x3ff)) + 0x10000;
++ }
++ break;
++ }
++
++#if DEBUG > 1
++ printf("mxml_file_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ return (ch);
++}
++
++
++/*
++ * 'mxml_file_putc()' - Write a character to a file.
++ */
++
++static int /* O - 0 on success, -1 on failure */
++mxml_file_putc(int ch, /* I - Character to write */
++ void *p) /* I - Pointer to file */
++{
++ return (putc(ch, (FILE *)p) == EOF ? -1 : 0);
++}
++
++
++/*
++ * 'mxml_get_entity()' - Get the character corresponding to an entity...
++ */
++
++static int /* O - Character value or EOF on error */
++mxml_get_entity(mxml_node_t *parent, /* I - Parent node */
++ void *p, /* I - Pointer to source */
++ int *encoding, /* IO - Character encoding */
++ int (*getc_cb)(void *, int *))
++ /* I - Get character function */
++{
++ int ch; /* Current character */
++ char entity[64], /* Entity string */
++ *entptr; /* Pointer into entity */
++
++
++ entptr = entity;
++
++ while ((ch = (*getc_cb)(p, encoding)) != EOF)
++ if (ch > 126 || (!isalnum(ch) && ch != '#'))
++ break;
++ else if (entptr < (entity + sizeof(entity) - 1))
++ *entptr++ = ch;
++ else
++ {
++ mxml_error("Entity name too long under parent <%s>!",
++ parent ? parent->value.element.name : "null");
++ break;
++ }
++
++ *entptr = '\0';
++
++ if (ch != ';')
++ {
++ mxml_error("Character entity \"%s\" not terminated under parent <%s>!",
++ entity, parent ? parent->value.element.name : "null");
++ return (EOF);
++ }
++
++ if (entity[0] == '#')
++ {
++ if (entity[1] == 'x')
++ ch = strtol(entity + 2, NULL, 16);
++ else
++ ch = strtol(entity + 1, NULL, 10);
++ }
++ else if ((ch = mxmlEntityGetValue(entity)) < 0)
++ mxml_error("Entity name \"%s;\" not supported under parent <%s>!",
++ entity, parent ? parent->value.element.name : "null");
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x under parent <%s> not allowed by XML standard!",
++ ch, parent ? parent->value.element.name : "null");
++ return (EOF);
++ }
++
++ return (ch);
++}
++
++
++/*
++ * 'mxml_load_data()' - Load data into an XML node tree.
++ */
++
++static mxml_node_t * /* O - First node or NULL if the file could not be read. */
++mxml_load_data(
++ mxml_node_t *top, /* I - Top node */
++ void *p, /* I - Pointer to data */
++ mxml_load_cb_t cb, /* I - Callback function or MXML_NO_CALLBACK */
++ _mxml_getc_cb_t getc_cb, /* I - Read function */
++ mxml_sax_cb_t sax_cb, /* I - SAX callback or MXML_NO_CALLBACK */
++ void *sax_data) /* I - SAX user data */
++{
++ mxml_node_t *node, /* Current node */
++ *first, /* First node added */
++ *parent; /* Current parent node */
++ int ch, /* Character from file */
++ whitespace; /* Non-zero if whitespace seen */
++ char *buffer, /* String buffer */
++ *bufptr; /* Pointer into buffer */
++ int bufsize; /* Size of buffer */
++ mxml_type_t type; /* Current node type */
++ int encoding; /* Character encoding */
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++ static const char * const types[] = /* Type strings... */
++ {
++ "MXML_ELEMENT", /* XML element with attributes */
++ "MXML_INTEGER", /* Integer value */
++ "MXML_OPAQUE", /* Opaque string */
++ "MXML_REAL", /* Real value */
++ "MXML_TEXT", /* Text fragment */
++ "MXML_CUSTOM" /* Custom data */
++ };
++
++
++ /*
++ * Read elements and other nodes from the file...
++ */
++
++ if ((buffer = malloc(64)) == NULL)
++ {
++ mxml_error("Unable to allocate string buffer!");
++ return (NULL);
++ }
++
++ bufsize = 64;
++ bufptr = buffer;
++ parent = top;
++ first = NULL;
++ whitespace = 0;
++ encoding = ENCODE_UTF8;
++
++ if (cb && parent)
++ type = (*cb)(parent);
++ else
++ type = MXML_TEXT;
++
++ while ((ch = (*getc_cb)(p, &encoding)) != EOF)
++ {
++ if ((ch == '<' ||
++ (mxml_isspace(ch) && type != MXML_OPAQUE && type != MXML_CUSTOM)) &&
++ bufptr > buffer)
++ {
++ /*
++ * Add a new value node...
++ */
++
++ *bufptr = '\0';
++
++ switch (type)
++ {
++ case MXML_INTEGER :
++ node = mxmlNewInteger(parent, strtol(buffer, &bufptr, 0));
++ break;
++
++ case MXML_OPAQUE :
++ node = mxmlNewOpaque(parent, buffer);
++ break;
++
++ case MXML_REAL :
++ node = mxmlNewReal(parent, strtod(buffer, &bufptr));
++ break;
++
++ case MXML_TEXT :
++ node = mxmlNewText(parent, whitespace, buffer);
++ break;
++
++ case MXML_CUSTOM :
++ if (global->custom_load_cb)
++ {
++ /*
++ * Use the callback to fill in the custom data...
++ */
++
++ node = mxmlNewCustom(parent, NULL, NULL);
++
++ if ((*global->custom_load_cb)(node, buffer))
++ {
++ mxml_error("Bad custom value '%s' in parent <%s>!",
++ buffer, parent ? parent->value.element.name : "null");
++ mxmlDelete(node);
++ node = NULL;
++ }
++ break;
++ }
++
++ default : /* Ignore... */
++ node = NULL;
++ break;
++ }
++
++ if (*bufptr)
++ {
++ /*
++ * Bad integer/real number value...
++ */
++
++ mxml_error("Bad %s value '%s' in parent <%s>!",
++ type == MXML_INTEGER ? "integer" : "real", buffer,
++ parent ? parent->value.element.name : "null");
++ break;
++ }
++
++ bufptr = buffer;
++ whitespace = mxml_isspace(ch) && type == MXML_TEXT;
++
++ if (!node && type != MXML_IGNORE)
++ {
++ /*
++ * Print error and return...
++ */
++
++ mxml_error("Unable to add value node of type %s to parent <%s>!",
++ types[type], parent ? parent->value.element.name : "null");
++ goto error;
++ }
++
++ if (sax_cb)
++ {
++ (*sax_cb)(node, MXML_SAX_DATA, sax_data);
++
++ if (!mxmlRelease(node))
++ node = NULL;
++ }
++
++ if (!first && node)
++ first = node;
++ }
++ else if (mxml_isspace(ch) && type == MXML_TEXT)
++ whitespace = 1;
++
++ /*
++ * Add lone whitespace node if we have an element and existing
++ * whitespace...
++ */
++
++ if (ch == '<' && whitespace && type == MXML_TEXT)
++ {
++ if (parent)
++ {
++ node = mxmlNewText(parent, whitespace, "");
++
++ if (sax_cb)
++ {
++ (*sax_cb)(node, MXML_SAX_DATA, sax_data);
++
++ if (!mxmlRelease(node))
++ node = NULL;
++ }
++
++ if (!first && node)
++ first = node;
++ }
++
++ whitespace = 0;
++ }
++
++ if (ch == '<')
++ {
++ /*
++ * Start of open/close tag...
++ */
++
++ bufptr = buffer;
++
++ while ((ch = (*getc_cb)(p, &encoding)) != EOF)
++ if (mxml_isspace(ch) || ch == '>' || (ch == '/' && bufptr > buffer))
++ break;
++ else if (ch == '<')
++ {
++ mxml_error("Bare < in element!");
++ goto error;
++ }
++ else if (ch == '&')
++ {
++ if ((ch = mxml_get_entity(parent, p, &encoding, getc_cb)) == EOF)
++ goto error;
++
++ if (mxml_add_char(ch, &bufptr, &buffer, &bufsize))
++ goto error;
++ }
++ else if (mxml_add_char(ch, &bufptr, &buffer, &bufsize))
++ goto error;
++ else if (((bufptr - buffer) == 1 && buffer[0] == '?') ||
++ ((bufptr - buffer) == 3 && !strncmp(buffer, "!--", 3)) ||
++ ((bufptr - buffer) == 8 && !strncmp(buffer, "![CDATA[", 8)))
++ break;
++
++ *bufptr = '\0';
++
++ if (!strcmp(buffer, "!--"))
++ {
++ /*
++ * Gather rest of comment...
++ */
++
++ while ((ch = (*getc_cb)(p, &encoding)) != EOF)
++ {
++ if (ch == '>' && bufptr > (buffer + 4) &&
++ bufptr[-3] != '-' && bufptr[-2] == '-' && bufptr[-1] == '-')
++ break;
++ else if (mxml_add_char(ch, &bufptr, &buffer, &bufsize))
++ goto error;
++ }
++
++ /*
++ * Error out if we didn't get the whole comment...
++ */
++
++ if (ch != '>')
++ {
++ /*
++ * Print error and return...
++ */
++
++ mxml_error("Early EOF in comment node!");
++ goto error;
++ }
++
++
++ /*
++ * Otherwise add this as an element under the current parent...
++ */
++
++ *bufptr = '\0';
++
++ if (!parent && first)
++ {
++ /*
++ * There can only be one root element!
++ */
++
++ mxml_error("<%s> cannot be a second root node after <%s>",
++ buffer, first->value.element.name);
++ goto error;
++ }
++
++ if ((node = mxmlNewElement(parent, buffer)) == NULL)
++ {
++ /*
++ * Just print error for now...
++ */
++
++ mxml_error("Unable to add comment node to parent <%s>!",
++ parent ? parent->value.element.name : "null");
++ break;
++ }
++
++ if (sax_cb)
++ {
++ (*sax_cb)(node, MXML_SAX_COMMENT, sax_data);
++
++ if (!mxmlRelease(node))
++ node = NULL;
++ }
++
++ if (node && !first)
++ first = node;
++ }
++ else if (!strcmp(buffer, "![CDATA["))
++ {
++ /*
++ * Gather CDATA section...
++ */
++
++ while ((ch = (*getc_cb)(p, &encoding)) != EOF)
++ {
++ if (ch == '>' && !strncmp(bufptr - 2, "]]", 2))
++ break;
++ else if (mxml_add_char(ch, &bufptr, &buffer, &bufsize))
++ goto error;
++ }
++
++ /*
++ * Error out if we didn't get the whole comment...
++ */
++
++ if (ch != '>')
++ {
++ /*
++ * Print error and return...
++ */
++
++ mxml_error("Early EOF in CDATA node!");
++ goto error;
++ }
++
++
++ /*
++ * Otherwise add this as an element under the current parent...
++ */
++
++ *bufptr = '\0';
++
++ if (!parent && first)
++ {
++ /*
++ * There can only be one root element!
++ */
++
++ mxml_error("<%s> cannot be a second root node after <%s>",
++ buffer, first->value.element.name);
++ goto error;
++ }
++
++ if ((node = mxmlNewElement(parent, buffer)) == NULL)
++ {
++ /*
++ * Print error and return...
++ */
++
++ mxml_error("Unable to add CDATA node to parent <%s>!",
++ parent ? parent->value.element.name : "null");
++ goto error;
++ }
++
++ if (sax_cb)
++ {
++ (*sax_cb)(node, MXML_SAX_CDATA, sax_data);
++
++ if (!mxmlRelease(node))
++ node = NULL;
++ }
++
++ if (node && !first)
++ first = node;
++ }
++ else if (buffer[0] == '?')
++ {
++ /*
++ * Gather rest of processing instruction...
++ */
++
++ while ((ch = (*getc_cb)(p, &encoding)) != EOF)
++ {
++ if (ch == '>' && bufptr > buffer && bufptr[-1] == '?')
++ break;
++ else if (mxml_add_char(ch, &bufptr, &buffer, &bufsize))
++ goto error;
++ }
++
++ /*
++ * Error out if we didn't get the whole processing instruction...
++ */
++
++ if (ch != '>')
++ {
++ /*
++ * Print error and return...
++ */
++
++ mxml_error("Early EOF in processing instruction node!");
++ goto error;
++ }
++
++ /*
++ * Otherwise add this as an element under the current parent...
++ */
++
++ *bufptr = '\0';
++
++ if (!parent && first)
++ {
++ /*
++ * There can only be one root element!
++ */
++
++ mxml_error("<%s> cannot be a second root node after <%s>",
++ buffer, first->value.element.name);
++ goto error;
++ }
++
++ if ((node = mxmlNewElement(parent, buffer)) == NULL)
++ {
++ /*
++ * Print error and return...
++ */
++
++ mxml_error("Unable to add processing instruction node to parent <%s>!",
++ parent ? parent->value.element.name : "null");
++ goto error;
++ }
++
++ if (sax_cb)
++ {
++ (*sax_cb)(node, MXML_SAX_DIRECTIVE, sax_data);
++
++ if (!mxmlRelease(node))
++ node = NULL;
++ }
++
++ if (node)
++ {
++ if (!first)
++ first = node;
++
++ if (!parent)
++ {
++ parent = node;
++
++ if (cb)
++ type = (*cb)(parent);
++ }
++ }
++ }
++ else if (buffer[0] == '!')
++ {
++ /*
++ * Gather rest of declaration...
++ */
++
++ do
++ {
++ if (ch == '>')
++ break;
++ else
++ {
++ if (ch == '&')
++ if ((ch = mxml_get_entity(parent, p, &encoding, getc_cb)) == EOF)
++ goto error;
++
++ if (mxml_add_char(ch, &bufptr, &buffer, &bufsize))
++ goto error;
++ }
++ }
++ while ((ch = (*getc_cb)(p, &encoding)) != EOF);
++
++ /*
++ * Error out if we didn't get the whole declaration...
++ */
++
++ if (ch != '>')
++ {
++ /*
++ * Print error and return...
++ */
++
++ mxml_error("Early EOF in declaration node!");
++ goto error;
++ }
++
++ /*
++ * Otherwise add this as an element under the current parent...
++ */
++
++ *bufptr = '\0';
++
++ if (!parent && first)
++ {
++ /*
++ * There can only be one root element!
++ */
++
++ mxml_error("<%s> cannot be a second root node after <%s>",
++ buffer, first->value.element.name);
++ goto error;
++ }
++
++ if ((node = mxmlNewElement(parent, buffer)) == NULL)
++ {
++ /*
++ * Print error and return...
++ */
++
++ mxml_error("Unable to add declaration node to parent <%s>!",
++ parent ? parent->value.element.name : "null");
++ goto error;
++ }
++
++ if (sax_cb)
++ {
++ (*sax_cb)(node, MXML_SAX_DIRECTIVE, sax_data);
++
++ if (!mxmlRelease(node))
++ node = NULL;
++ }
++
++ if (node)
++ {
++ if (!first)
++ first = node;
++
++ if (!parent)
++ {
++ parent = node;
++
++ if (cb)
++ type = (*cb)(parent);
++ }
++ }
++ }
++ else if (buffer[0] == '/')
++ {
++ /*
++ * Handle close tag...
++ */
++
++ if (!parent || strcmp(buffer + 1, parent->value.element.name))
++ {
++ /*
++ * Close tag doesn't match tree; print an error for now...
++ */
++
++ mxml_error("Mismatched close tag <%s> under parent <%s>!",
++ buffer, parent ? parent->value.element.name : "(null)");
++ goto error;
++ }
++
++ /*
++ * Keep reading until we see >...
++ */
++
++ while (ch != '>' && ch != EOF)
++ ch = (*getc_cb)(p, &encoding);
++
++ node = parent;
++ parent = parent->parent;
++
++ if (sax_cb)
++ {
++ (*sax_cb)(node, MXML_SAX_ELEMENT_CLOSE, sax_data);
++
++ if (!mxmlRelease(node) && first == node)
++ first = NULL;
++ }
++
++ /*
++ * Ascend into the parent and set the value type as needed...
++ */
++
++ if (cb && parent)
++ type = (*cb)(parent);
++ }
++ else
++ {
++ /*
++ * Handle open tag...
++ */
++
++ if (!parent && first)
++ {
++ /*
++ * There can only be one root element!
++ */
++
++ mxml_error("<%s> cannot be a second root node after <%s>",
++ buffer, first->value.element.name);
++ goto error;
++ }
++
++ if ((node = mxmlNewElement(parent, buffer)) == NULL)
++ {
++ /*
++ * Just print error for now...
++ */
++
++ mxml_error("Unable to add element node to parent <%s>!",
++ parent ? parent->value.element.name : "null");
++ goto error;
++ }
++
++ if (mxml_isspace(ch))
++ {
++ if ((ch = mxml_parse_element(node, p, &encoding, getc_cb)) == EOF)
++ goto error;
++ }
++ else if (ch == '/')
++ {
++ if ((ch = (*getc_cb)(p, &encoding)) != '>')
++ {
++ mxml_error("Expected > but got '%c' instead for element <%s/>!",
++ ch, buffer);
++ mxmlDelete(node);
++ goto error;
++ }
++
++ ch = '/';
++ }
++
++ if (sax_cb)
++ (*sax_cb)(node, MXML_SAX_ELEMENT_OPEN, sax_data);
++
++ if (!first)
++ first = node;
++
++ if (ch == EOF)
++ break;
++
++ if (ch != '/')
++ {
++ /*
++ * Descend into this node, setting the value type as needed...
++ */
++
++ parent = node;
++
++ if (cb && parent)
++ type = (*cb)(parent);
++ }
++ else if (sax_cb)
++ {
++ (*sax_cb)(node, MXML_SAX_ELEMENT_CLOSE, sax_data);
++
++ if (!mxmlRelease(node) && first == node)
++ first = NULL;
++ }
++ }
++
++ bufptr = buffer;
++ }
++ else if (ch == '&')
++ {
++ /*
++ * Add character entity to current buffer...
++ */
++
++ if ((ch = mxml_get_entity(parent, p, &encoding, getc_cb)) == EOF)
++ goto error;
++
++ if (mxml_add_char(ch, &bufptr, &buffer, &bufsize))
++ goto error;
++ }
++ else if (type == MXML_OPAQUE || type == MXML_CUSTOM || !mxml_isspace(ch))
++ {
++ /*
++ * Add character to current buffer...
++ */
++
++ if (mxml_add_char(ch, &bufptr, &buffer, &bufsize))
++ goto error;
++ }
++ }
++
++ /*
++ * Free the string buffer - we don't need it anymore...
++ */
++
++ free(buffer);
++
++ /*
++ * Find the top element and return it...
++ */
++
++ if (parent)
++ {
++ node = parent;
++
++ while (parent->parent != top && parent->parent)
++ parent = parent->parent;
++
++ if (node != parent)
++ {
++ mxml_error("Missing close tag </%s> under parent <%s>!",
++ node->value.element.name,
++ node->parent ? node->parent->value.element.name : "(null)");
++
++ mxmlDelete(first);
++
++ return (NULL);
++ }
++ }
++
++ if (parent)
++ return (parent);
++ else
++ return (first);
++
++ /*
++ * Common error return...
++ */
++
++error:
++
++ mxmlDelete(first);
++
++ free(buffer);
++
++ return (NULL);
++}
++
++
++/*
++ * 'mxml_parse_element()' - Parse an element for any attributes...
++ */
++
++static int /* O - Terminating character */
++mxml_parse_element(
++ mxml_node_t *node, /* I - Element node */
++ void *p, /* I - Data to read from */
++ int *encoding, /* IO - Encoding */
++ _mxml_getc_cb_t getc_cb) /* I - Data callback */
++{
++ int ch, /* Current character in file */
++ quote; /* Quoting character */
++ char *name, /* Attribute name */
++ *value, /* Attribute value */
++ *ptr; /* Pointer into name/value */
++ int namesize, /* Size of name string */
++ valsize; /* Size of value string */
++
++
++ /*
++ * Initialize the name and value buffers...
++ */
++
++ if ((name = malloc(64)) == NULL)
++ {
++ mxml_error("Unable to allocate memory for name!");
++ return (EOF);
++ }
++
++ namesize = 64;
++
++ if ((value = malloc(64)) == NULL)
++ {
++ free(name);
++ mxml_error("Unable to allocate memory for value!");
++ return (EOF);
++ }
++
++ valsize = 64;
++
++ /*
++ * Loop until we hit a >, /, ?, or EOF...
++ */
++
++ while ((ch = (*getc_cb)(p, encoding)) != EOF)
++ {
++#if DEBUG > 1
++ fprintf(stderr, "parse_element: ch='%c'\n", ch);
++#endif /* DEBUG > 1 */
++
++ /*
++ * Skip leading whitespace...
++ */
++
++ if (mxml_isspace(ch))
++ continue;
++
++ /*
++ * Stop at /, ?, or >...
++ */
++
++ if (ch == '/' || ch == '?')
++ {
++ /*
++ * Grab the > character and print an error if it isn't there...
++ */
++
++ quote = (*getc_cb)(p, encoding);
++
++ if (quote != '>')
++ {
++ mxml_error("Expected '>' after '%c' for element %s, but got '%c'!",
++ ch, node->value.element.name, quote);
++ goto error;
++ }
++
++ break;
++ }
++ else if (ch == '<')
++ {
++ mxml_error("Bare < in element %s!", node->value.element.name);
++ goto error;
++ }
++ else if (ch == '>')
++ break;
++
++ /*
++ * Read the attribute name...
++ */
++
++ name[0] = ch;
++ ptr = name + 1;
++
++ if (ch == '\"' || ch == '\'')
++ {
++ /*
++ * Name is in quotes, so get a quoted string...
++ */
++
++ quote = ch;
++
++ while ((ch = (*getc_cb)(p, encoding)) != EOF)
++ {
++ if (ch == '&')
++ if ((ch = mxml_get_entity(node, p, encoding, getc_cb)) == EOF)
++ goto error;
++
++ if (mxml_add_char(ch, &ptr, &name, &namesize))
++ goto error;
++
++ if (ch == quote)
++ break;
++ }
++ }
++ else
++ {
++ /*
++ * Grab an normal, non-quoted name...
++ */
++
++ while ((ch = (*getc_cb)(p, encoding)) != EOF)
++ if (mxml_isspace(ch) || ch == '=' || ch == '/' || ch == '>' ||
++ ch == '?')
++ break;
++ else
++ {
++ if (ch == '&')
++ if ((ch = mxml_get_entity(node, p, encoding, getc_cb)) == EOF)
++ goto error;
++
++ if (mxml_add_char(ch, &ptr, &name, &namesize))
++ goto error;
++ }
++ }
++
++ *ptr = '\0';
++
++ if (mxmlElementGetAttr(node, name))
++ goto error;
++
++ while (ch != EOF && mxml_isspace(ch))
++ ch = (*getc_cb)(p, encoding);
++
++ if (ch == '=')
++ {
++ /*
++ * Read the attribute value...
++ */
++
++ while ((ch = (*getc_cb)(p, encoding)) != EOF && mxml_isspace(ch));
++
++ if (ch == EOF)
++ {
++ mxml_error("Missing value for attribute '%s' in element %s!",
++ name, node->value.element.name);
++ goto error;
++ }
++
++ if (ch == '\'' || ch == '\"')
++ {
++ /*
++ * Read quoted value...
++ */
++
++ quote = ch;
++ ptr = value;
++
++ while ((ch = (*getc_cb)(p, encoding)) != EOF)
++ if (ch == quote)
++ break;
++ else
++ {
++ if (ch == '&')
++ if ((ch = mxml_get_entity(node, p, encoding, getc_cb)) == EOF)
++ goto error;
++
++ if (mxml_add_char(ch, &ptr, &value, &valsize))
++ goto error;
++ }
++
++ *ptr = '\0';
++ }
++ else
++ {
++ /*
++ * Read unquoted value...
++ */
++
++ value[0] = ch;
++ ptr = value + 1;
++
++ while ((ch = (*getc_cb)(p, encoding)) != EOF)
++ if (mxml_isspace(ch) || ch == '=' || ch == '/' || ch == '>')
++ break;
++ else
++ {
++ if (ch == '&')
++ if ((ch = mxml_get_entity(node, p, encoding, getc_cb)) == EOF)
++ goto error;
++
++ if (mxml_add_char(ch, &ptr, &value, &valsize))
++ goto error;
++ }
++
++ *ptr = '\0';
++ }
++
++ /*
++ * Set the attribute with the given string value...
++ */
++
++ mxmlElementSetAttr(node, name, value);
++ }
++ else
++ {
++ mxml_error("Missing value for attribute '%s' in element %s!",
++ name, node->value.element.name);
++ goto error;
++ }
++
++ /*
++ * Check the end character...
++ */
++
++ if (ch == '/' || ch == '?')
++ {
++ /*
++ * Grab the > character and print an error if it isn't there...
++ */
++
++ quote = (*getc_cb)(p, encoding);
++
++ if (quote != '>')
++ {
++ mxml_error("Expected '>' after '%c' for element %s, but got '%c'!",
++ ch, node->value.element.name, quote);
++ ch = EOF;
++ }
++
++ break;
++ }
++ else if (ch == '>')
++ break;
++ }
++
++ /*
++ * Free the name and value buffers and return...
++ */
++
++ free(name);
++ free(value);
++
++ return (ch);
++
++ /*
++ * Common error return point...
++ */
++
++error:
++
++ free(name);
++ free(value);
++
++ return (EOF);
++}
++
++
++/*
++ * 'mxml_string_getc()' - Get a character from a string.
++ */
++
++static int /* O - Character or EOF */
++mxml_string_getc(void *p, /* I - Pointer to file */
++ int *encoding) /* IO - Encoding */
++{
++ int ch; /* Character */
++ const char **s; /* Pointer to string pointer */
++
++
++ s = (const char **)p;
++
++ if ((ch = (*s)[0] & 255) != 0 || *encoding == ENCODE_UTF16LE)
++ {
++ /*
++ * Got character; convert UTF-8 to integer and return...
++ */
++
++ (*s)++;
++
++ switch (*encoding)
++ {
++ case ENCODE_UTF8 :
++ if (!(ch & 0x80))
++ {
++#if DEBUG > 1
++ printf("mxml_string_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++
++ return (ch);
++ }
++ else if (ch == 0xfe)
++ {
++ /*
++ * UTF-16 big-endian BOM?
++ */
++
++ if (((*s)[0] & 255) != 0xff)
++ return (EOF);
++
++ *encoding = ENCODE_UTF16BE;
++ (*s)++;
++
++ return (mxml_string_getc(p, encoding));
++ }
++ else if (ch == 0xff)
++ {
++ /*
++ * UTF-16 little-endian BOM?
++ */
++
++ if (((*s)[0] & 255) != 0xfe)
++ return (EOF);
++
++ *encoding = ENCODE_UTF16LE;
++ (*s)++;
++
++ return (mxml_string_getc(p, encoding));
++ }
++ else if ((ch & 0xe0) == 0xc0)
++ {
++ /*
++ * Two-byte value...
++ */
++
++ if (((*s)[0] & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((ch & 0x1f) << 6) | ((*s)[0] & 0x3f);
++
++ (*s)++;
++
++ if (ch < 0x80)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++
++#if DEBUG > 1
++ printf("mxml_string_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ return (ch);
++ }
++ else if ((ch & 0xf0) == 0xe0)
++ {
++ /*
++ * Three-byte value...
++ */
++
++ if (((*s)[0] & 0xc0) != 0x80 ||
++ ((*s)[1] & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((((ch & 0x0f) << 6) | ((*s)[0] & 0x3f)) << 6) | ((*s)[1] & 0x3f);
++
++ (*s) += 2;
++
++ if (ch < 0x800)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++
++ /*
++ * Ignore (strip) Byte Order Mark (BOM)...
++ */
++
++ if (ch == 0xfeff)
++ return (mxml_string_getc(p, encoding));
++
++#if DEBUG > 1
++ printf("mxml_string_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ return (ch);
++ }
++ else if ((ch & 0xf8) == 0xf0)
++ {
++ /*
++ * Four-byte value...
++ */
++
++ if (((*s)[0] & 0xc0) != 0x80 ||
++ ((*s)[1] & 0xc0) != 0x80 ||
++ ((*s)[2] & 0xc0) != 0x80)
++ return (EOF);
++
++ ch = ((((((ch & 0x07) << 6) | ((*s)[0] & 0x3f)) << 6) |
++ ((*s)[1] & 0x3f)) << 6) | ((*s)[2] & 0x3f);
++
++ (*s) += 3;
++
++ if (ch < 0x10000)
++ {
++ mxml_error("Invalid UTF-8 sequence for character 0x%04x!", ch);
++ return (EOF);
++ }
++
++#if DEBUG > 1
++ printf("mxml_string_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ return (ch);
++ }
++ else
++ return (EOF);
++
++ case ENCODE_UTF16BE :
++ /*
++ * Read UTF-16 big-endian char...
++ */
++
++ ch = (ch << 8) | ((*s)[0] & 255);
++ (*s) ++;
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++ else if (ch >= 0xd800 && ch <= 0xdbff)
++ {
++ /*
++ * Multi-word UTF-16 char...
++ */
++
++ int lch; /* Lower word */
++
++
++ if (!(*s)[0])
++ return (EOF);
++
++ lch = (((*s)[0] & 255) << 8) | ((*s)[1] & 255);
++ (*s) += 2;
++
++ if (lch < 0xdc00 || lch >= 0xdfff)
++ return (EOF);
++
++ ch = (((ch & 0x3ff) << 10) | (lch & 0x3ff)) + 0x10000;
++ }
++
++#if DEBUG > 1
++ printf("mxml_string_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ return (ch);
++
++ case ENCODE_UTF16LE :
++ /*
++ * Read UTF-16 little-endian char...
++ */
++
++ ch = ch | (((*s)[0] & 255) << 8);
++
++ if (!ch)
++ {
++ (*s) --;
++ return (EOF);
++ }
++
++ (*s) ++;
++
++ if (mxml_bad_char(ch))
++ {
++ mxml_error("Bad control character 0x%02x not allowed by XML standard!",
++ ch);
++ return (EOF);
++ }
++ else if (ch >= 0xd800 && ch <= 0xdbff)
++ {
++ /*
++ * Multi-word UTF-16 char...
++ */
++
++ int lch; /* Lower word */
++
++
++ if (!(*s)[1])
++ return (EOF);
++
++ lch = (((*s)[1] & 255) << 8) | ((*s)[0] & 255);
++ (*s) += 2;
++
++ if (lch < 0xdc00 || lch >= 0xdfff)
++ return (EOF);
++
++ ch = (((ch & 0x3ff) << 10) | (lch & 0x3ff)) + 0x10000;
++ }
++
++#if DEBUG > 1
++ printf("mxml_string_getc: %c (0x%04x)\n", ch < ' ' ? '.' : ch, ch);
++#endif /* DEBUG > 1 */
++
++ return (ch);
++ }
++ }
++
++ return (EOF);
++}
++
++
++/*
++ * 'mxml_string_putc()' - Write a character to a string.
++ */
++
++static int /* O - 0 on success, -1 on failure */
++mxml_string_putc(int ch, /* I - Character to write */
++ void *p) /* I - Pointer to string pointers */
++{
++ char **pp; /* Pointer to string pointers */
++
++
++ pp = (char **)p;
++
++ if (pp[0] < pp[1])
++ pp[0][0] = ch;
++
++ pp[0] ++;
++
++ return (0);
++}
++
++
++/*
++ * 'mxml_write_name()' - Write a name string.
++ */
++
++static int /* O - 0 on success, -1 on failure */
++mxml_write_name(const char *s, /* I - Name to write */
++ void *p, /* I - Write pointer */
++ int (*putc_cb)(int, void *))
++ /* I - Write callback */
++{
++ char quote; /* Quote character */
++ const char *name; /* Entity name */
++
++
++ if (*s == '\"' || *s == '\'')
++ {
++ /*
++ * Write a quoted name string...
++ */
++
++ if ((*putc_cb)(*s, p) < 0)
++ return (-1);
++
++ quote = *s++;
++
++ while (*s && *s != quote)
++ {
++ if ((name = mxmlEntityGetName(*s)) != NULL)
++ {
++ if ((*putc_cb)('&', p) < 0)
++ return (-1);
++
++ while (*name)
++ {
++ if ((*putc_cb)(*name, p) < 0)
++ return (-1);
++
++ name ++;
++ }
++
++ if ((*putc_cb)(';', p) < 0)
++ return (-1);
++ }
++ else if ((*putc_cb)(*s, p) < 0)
++ return (-1);
++
++ s ++;
++ }
++
++ /*
++ * Write the end quote...
++ */
++
++ if ((*putc_cb)(quote, p) < 0)
++ return (-1);
++ }
++ else
++ {
++ /*
++ * Write a non-quoted name string...
++ */
++
++ while (*s)
++ {
++ if ((*putc_cb)(*s, p) < 0)
++ return (-1);
++
++ s ++;
++ }
++ }
++
++ return (0);
++}
++
++
++/*
++ * 'mxml_write_node()' - Save an XML node to a file.
++ */
++
++static int /* O - Column or -1 on error */
++mxml_write_node(mxml_node_t *node, /* I - Node to write */
++ void *p, /* I - File to write to */
++ mxml_save_cb_t cb, /* I - Whitespace callback */
++ int col, /* I - Current column */
++ _mxml_putc_cb_t putc_cb,/* I - Output callback */
++ _mxml_global_t *global)/* I - Global data */
++{
++ int i, /* Looping var */
++ width; /* Width of attr + value */
++ mxml_attr_t *attr; /* Current attribute */
++ char s[255]; /* Temporary string */
++
++
++ /*
++ * Print the node value...
++ */
++
++ switch (node->type)
++ {
++ case MXML_ELEMENT :
++ col = mxml_write_ws(node, p, cb, MXML_WS_BEFORE_OPEN, col, putc_cb);
++
++ if ((*putc_cb)('<', p) < 0)
++ return (-1);
++ if (node->value.element.name[0] == '?' ||
++ !strncmp(node->value.element.name, "!--", 3) ||
++ !strncmp(node->value.element.name, "![CDATA[", 8))
++ {
++ /*
++ * Comments, CDATA, and processing instructions do not
++ * use character entities.
++ */
++
++ const char *ptr; /* Pointer into name */
++
++
++ for (ptr = node->value.element.name; *ptr; ptr ++)
++ if ((*putc_cb)(*ptr, p) < 0)
++ return (-1);
++ }
++ else if (mxml_write_name(node->value.element.name, p, putc_cb) < 0)
++ return (-1);
++
++ col += strlen(node->value.element.name) + 1;
++
++ for (i = node->value.element.num_attrs, attr = node->value.element.attrs;
++ i > 0;
++ i --, attr ++)
++ {
++ width = strlen(attr->name);
++
++ if (attr->value)
++ width += strlen(attr->value) + 3;
++
++ if (global->wrap > 0 && (col + width) > global->wrap)
++ {
++ if ((*putc_cb)('\n', p) < 0)
++ return (-1);
++
++ col = 0;
++ }
++ else
++ {
++ if ((*putc_cb)(' ', p) < 0)
++ return (-1);
++
++ col ++;
++ }
++
++ if (mxml_write_name(attr->name, p, putc_cb) < 0)
++ return (-1);
++
++ if (attr->value)
++ {
++ if ((*putc_cb)('=', p) < 0)
++ return (-1);
++ if ((*putc_cb)('\"', p) < 0)
++ return (-1);
++ if (mxml_write_string(attr->value, p, putc_cb) < 0)
++ return (-1);
++ if ((*putc_cb)('\"', p) < 0)
++ return (-1);
++ }
++
++ col += width;
++ }
++
++ if (node->child)
++ {
++ /*
++ * Write children...
++ */
++
++ mxml_node_t *child; /* Current child */
++
++
++ if ((*putc_cb)('>', p) < 0)
++ return (-1);
++ else
++ col ++;
++
++ col = mxml_write_ws(node, p, cb, MXML_WS_AFTER_OPEN, col, putc_cb);
++
++ for (child = node->child; child; child = child->next)
++ {
++ if ((col = mxml_write_node(child, p, cb, col, putc_cb, global)) < 0)
++ return (-1);
++ }
++
++ /*
++ * The ? and ! elements are special-cases and have no end tags...
++ */
++
++ if (node->value.element.name[0] != '!' &&
++ node->value.element.name[0] != '?')
++ {
++ col = mxml_write_ws(node, p, cb, MXML_WS_BEFORE_CLOSE, col, putc_cb);
++
++ if ((*putc_cb)('<', p) < 0)
++ return (-1);
++ if ((*putc_cb)('/', p) < 0)
++ return (-1);
++ if (mxml_write_string(node->value.element.name, p, putc_cb) < 0)
++ return (-1);
++ if ((*putc_cb)('>', p) < 0)
++ return (-1);
++
++ col += strlen(node->value.element.name) + 3;
++
++ col = mxml_write_ws(node, p, cb, MXML_WS_AFTER_CLOSE, col, putc_cb);
++ }
++ }
++ else if (node->value.element.name[0] == '!' ||
++ node->value.element.name[0] == '?')
++ {
++ /*
++ * The ? and ! elements are special-cases...
++ */
++
++ if ((*putc_cb)('>', p) < 0)
++ return (-1);
++ else
++ col ++;
++
++ col = mxml_write_ws(node, p, cb, MXML_WS_AFTER_OPEN, col, putc_cb);
++ }
++ else
++ {
++ if ((*putc_cb)(' ', p) < 0)
++ return (-1);
++ if ((*putc_cb)('/', p) < 0)
++ return (-1);
++ if ((*putc_cb)('>', p) < 0)
++ return (-1);
++
++ col += 3;
++
++ col = mxml_write_ws(node, p, cb, MXML_WS_AFTER_OPEN, col, putc_cb);
++ }
++ break;
++
++ case MXML_INTEGER :
++ if (node->prev)
++ {
++ if (global->wrap > 0 && col > global->wrap)
++ {
++ if ((*putc_cb)('\n', p) < 0)
++ return (-1);
++
++ col = 0;
++ }
++ else if ((*putc_cb)(' ', p) < 0)
++ return (-1);
++ else
++ col ++;
++ }
++
++ sprintf(s, "%d", node->value.integer);
++ if (mxml_write_string(s, p, putc_cb) < 0)
++ return (-1);
++
++ col += strlen(s);
++ break;
++
++ case MXML_OPAQUE :
++ if (mxml_write_string(node->value.opaque, p, putc_cb) < 0)
++ return (-1);
++
++ col += strlen(node->value.opaque);
++ break;
++
++ case MXML_REAL :
++ if (node->prev)
++ {
++ if (global->wrap > 0 && col > global->wrap)
++ {
++ if ((*putc_cb)('\n', p) < 0)
++ return (-1);
++
++ col = 0;
++ }
++ else if ((*putc_cb)(' ', p) < 0)
++ return (-1);
++ else
++ col ++;
++ }
++
++ sprintf(s, "%f", node->value.real);
++ if (mxml_write_string(s, p, putc_cb) < 0)
++ return (-1);
++
++ col += strlen(s);
++ break;
++
++ case MXML_TEXT :
++ if (node->value.text.whitespace && col > 0)
++ {
++ if (global->wrap > 0 && col > global->wrap)
++ {
++ if ((*putc_cb)('\n', p) < 0)
++ return (-1);
++
++ col = 0;
++ }
++ else if ((*putc_cb)(' ', p) < 0)
++ return (-1);
++ else
++ col ++;
++ }
++
++ if (mxml_write_string(node->value.text.string, p, putc_cb) < 0)
++ return (-1);
++
++ col += strlen(node->value.text.string);
++ break;
++
++ case MXML_CUSTOM :
++ if (global->custom_save_cb)
++ {
++ char *data; /* Custom data string */
++ const char *newline; /* Last newline in string */
++
++
++ if ((data = (*global->custom_save_cb)(node)) == NULL)
++ return (-1);
++
++ if (mxml_write_string(data, p, putc_cb) < 0)
++ return (-1);
++
++ if ((newline = strrchr(data, '\n')) == NULL)
++ col += strlen(data);
++ else
++ col = strlen(newline);
++
++ free(data);
++ break;
++ }
++
++ default : /* Should never happen */
++ return (-1);
++ }
++
++ return (col);
++}
++
++
++/*
++ * 'mxml_write_string()' - Write a string, escaping & and < as needed.
++ */
++
++static int /* O - 0 on success, -1 on failure */
++mxml_write_string(
++ const char *s, /* I - String to write */
++ void *p, /* I - Write pointer */
++ _mxml_putc_cb_t putc_cb) /* I - Write callback */
++{
++ const char *name; /* Entity name, if any */
++
++
++ while (*s)
++ {
++ if ((name = mxmlEntityGetName(*s)) != NULL)
++ {
++ if ((*putc_cb)('&', p) < 0)
++ return (-1);
++
++ while (*name)
++ {
++ if ((*putc_cb)(*name, p) < 0)
++ return (-1);
++ name ++;
++ }
++
++ if ((*putc_cb)(';', p) < 0)
++ return (-1);
++ }
++ else if ((*putc_cb)(*s, p) < 0)
++ return (-1);
++
++ s ++;
++ }
++
++ return (0);
++}
++
++
++/*
++ * 'mxml_write_ws()' - Do whitespace callback...
++ */
++
++static int /* O - New column */
++mxml_write_ws(mxml_node_t *node, /* I - Current node */
++ void *p, /* I - Write pointer */
++ mxml_save_cb_t cb, /* I - Callback function */
++ int ws, /* I - Where value */
++ int col, /* I - Current column */
++ _mxml_putc_cb_t putc_cb) /* I - Write callback */
++{
++ const char *s; /* Whitespace string */
++
++
++ if (cb && (s = (*cb)(node, ws)) != NULL)
++ {
++ while (*s)
++ {
++ if ((*putc_cb)(*s, p) < 0)
++ return (-1);
++ else if (*s == '\n')
++ col = 0;
++ else if (*s == '\t')
++ {
++ col += MXML_TAB;
++ col = col - (col % MXML_TAB);
++ }
++ else
++ col ++;
++
++ s ++;
++ }
++ }
++
++ return (col);
++}
++
++
++/*
++ * End of "$Id: mxml-file.c 438 2011-03-24 05:47:51Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-get.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-get.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-get.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-get.c 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,471 @@
++/*
++ * "$Id: mxml-get.c 427 2011-01-03 02:03:29Z mike $"
++ *
++ * Node get functions for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2011 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * mxmlGetCDATA() - Get the value for a CDATA node.
++ * mxmlGetCustom() - Get the value for a custom node.
++ * mxmlGetElement() - Get the name for an element node.
++ * mxmlGetFirstChild() - Get the first child of an element node.
++ * mxmlGetInteger() - Get the integer value from the specified node or its
++ * first child.
++ * mxmlGetLastChild() - Get the last child of an element node.
++ * mxmlGetNextSibling() - Get the next node for the current parent.
++ * mxmlGetOpaque() - Get an opaque string value for a node or its first
++ * child.
++ * mxmlGetParent() - Get the parent node.
++ * mxmlGetPrevSibling() - Get the previous node for the current parent.
++ * mxmlGetReal() - Get the real value for a node or its first child.
++ * mxmlGetText() - Get the text value for a node or its first child.
++ * mxmlGetType() - Get the node type.
++ * mxmlGetUserData() - Get the user data pointer for a node.
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "config.h"
++#include "mxml.h"
++
++
++/*
++ * 'mxmlGetCDATA()' - Get the value for a CDATA node.
++ *
++ * @code NULL@ is returned if the node is not a CDATA element.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++const char * /* O - CDATA value or NULL */
++mxmlGetCDATA(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT ||
++ strncmp(node->value.element.name, "![CDATA[", 8))
++ return (NULL);
++
++ /*
++ * Return the text following the CDATA declaration...
++ */
++
++ return (node->value.element.name + 8);
++}
++
++
++/*
++ * 'mxmlGetCustom()' - Get the value for a custom node.
++ *
++ * @code NULL@ is returned if the node (or its first child) is not a custom
++ * value node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++const void * /* O - Custom value or NULL */
++mxmlGetCustom(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (NULL);
++
++ /*
++ * Return the integer value...
++ */
++
++ if (node->type == MXML_CUSTOM)
++ return (node->value.custom.data);
++ else if (node->type == MXML_ELEMENT &&
++ node->child &&
++ node->child->type == MXML_CUSTOM)
++ return (node->child->value.custom.data);
++ else
++ return (NULL);
++}
++
++
++/*
++ * 'mxmlGetElement()' - Get the name for an element node.
++ *
++ * @code NULL@ is returned if the node is not an element node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++const char * /* O - Element name or NULL */
++mxmlGetElement(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT)
++ return (NULL);
++
++ /*
++ * Return the element name...
++ */
++
++ return (node->value.element.name);
++}
++
++
++/*
++ * 'mxmlGetFirstChild()' - Get the first child of an element node.
++ *
++ * @code NULL@ is returned if the node is not an element node or if the node
++ * has no children.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++mxml_node_t * /* O - First child or NULL */
++mxmlGetFirstChild(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT)
++ return (NULL);
++
++ /*
++ * Return the first child node...
++ */
++
++ return (node->child);
++}
++
++
++/*
++ * 'mxmlGetInteger()' - Get the integer value from the specified node or its
++ * first child.
++ *
++ * 0 is returned if the node (or its first child) is not an integer value node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++int /* O - Integer value or 0 */
++mxmlGetInteger(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (0);
++
++ /*
++ * Return the integer value...
++ */
++
++ if (node->type == MXML_INTEGER)
++ return (node->value.integer);
++ else if (node->type == MXML_ELEMENT &&
++ node->child &&
++ node->child->type == MXML_INTEGER)
++ return (node->child->value.integer);
++ else
++ return (0);
++}
++
++
++/*
++ * 'mxmlGetLastChild()' - Get the last child of an element node.
++ *
++ * @code NULL@ is returned if the node is not an element node or if the node
++ * has no children.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++mxml_node_t * /* O - Last child or NULL */
++mxmlGetLastChild(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT)
++ return (NULL);
++
++ /*
++ * Return the node type...
++ */
++
++ return (node->last_child);
++}
++
++
++/*
++ * 'mxmlGetNextSibling()' - Get the next node for the current parent.
++ *
++ * @code NULL@ is returned if this is the last child for the current parent.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++mxml_node_t *
++mxmlGetNextSibling(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (NULL);
++
++ /*
++ * Return the node type...
++ */
++
++ return (node->next);
++}
++
++
++/*
++ * 'mxmlGetOpaque()' - Get an opaque string value for a node or its first child.
++ *
++ * @code NULL@ is returned if the node (or its first child) is not an opaque
++ * value node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++const char * /* O - Opaque string or NULL */
++mxmlGetOpaque(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (NULL);
++
++ /*
++ * Return the integer value...
++ */
++
++ if (node->type == MXML_OPAQUE)
++ return (node->value.opaque);
++ else if (node->type == MXML_ELEMENT &&
++ node->child &&
++ node->child->type == MXML_OPAQUE)
++ return (node->child->value.opaque);
++ else
++ return (NULL);
++}
++
++
++/*
++ * 'mxmlGetParent()' - Get the parent node.
++ *
++ * @code NULL@ is returned for a root node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++mxml_node_t * /* O - Parent node or NULL */
++mxmlGetParent(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (NULL);
++
++ /*
++ * Return the node type...
++ */
++
++ return (node->parent);
++}
++
++
++/*
++ * 'mxmlGetPrevSibling()' - Get the previous node for the current parent.
++ *
++ * @code NULL@ is returned if this is the first child for the current parent.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++mxml_node_t * /* O - Previous node or NULL */
++mxmlGetPrevSibling(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (NULL);
++
++ /*
++ * Return the node type...
++ */
++
++ return (node->prev);
++}
++
++
++/*
++ * 'mxmlGetReal()' - Get the real value for a node or its first child.
++ *
++ * 0.0 is returned if the node (or its first child) is not a real value node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++double /* O - Real value or 0.0 */
++mxmlGetReal(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (0.0);
++
++ /*
++ * Return the integer value...
++ */
++
++ if (node->type == MXML_REAL)
++ return (node->value.real);
++ else if (node->type == MXML_ELEMENT &&
++ node->child &&
++ node->child->type == MXML_REAL)
++ return (node->child->value.real);
++ else
++ return (0.0);
++}
++
++
++/*
++ * 'mxmlGetText()' - Get the text value for a node or its first child.
++ *
++ * @code NULL@ is returned if the node (or its first child) is not a text node.
++ * The "whitespace" argument can be NULL.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++const char * /* O - Text string or NULL */
++mxmlGetText(mxml_node_t *node, /* I - Node to get */
++ int *whitespace) /* O - 1 if string is preceded by whitespace, 0 otherwise */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ {
++ if (whitespace)
++ *whitespace = 0;
++
++ return (NULL);
++ }
++
++ /*
++ * Return the integer value...
++ */
++
++ if (node->type == MXML_TEXT)
++ {
++ if (whitespace)
++ *whitespace = node->value.text.whitespace;
++
++ return (node->value.text.string);
++ }
++ else if (node->type == MXML_ELEMENT &&
++ node->child &&
++ node->child->type == MXML_TEXT)
++ {
++ if (whitespace)
++ *whitespace = node->child->value.text.whitespace;
++
++ return (node->child->value.text.string);
++ }
++ else
++ {
++ if (whitespace)
++ *whitespace = 0;
++
++ return (NULL);
++ }
++}
++
++
++/*
++ * 'mxmlGetType()' - Get the node type.
++ *
++ * @code MXML_IGNORE@ is returned if "node" is @code NULL@.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++mxml_type_t /* O - Type of node */
++mxmlGetType(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (MXML_IGNORE);
++
++ /*
++ * Return the node type...
++ */
++
++ return (node->type);
++}
++
++
++/*
++ * 'mxmlGetUserData()' - Get the user data pointer for a node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++void * /* O - User data pointer */
++mxmlGetUserData(mxml_node_t *node) /* I - Node to get */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (NULL);
++
++ /*
++ * Return the user data pointer...
++ */
++
++ return (node->user_data);
++}
++
++
++/*
++ * End of "$Id: mxml-get.c 427 2011-01-03 02:03:29Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml.h linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml.h
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml.h 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,329 @@
++/*
++ * "$Id: mxml.h 427 2011-01-03 02:03:29Z mike $"
++ *
++ * Header file for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2011 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ */
++
++/*
++ * Prevent multiple inclusion...
++ */
++
++#ifndef _mxml_h_
++# define _mxml_h_
++
++/*
++ * Include necessary headers...
++ */
++
++# include <stdio.h>
++# include <stdlib.h>
++# include <string.h>
++# include <ctype.h>
++# include <errno.h>
++
++
++/*
++ * Constants...
++ */
++
++# define MXML_TAB 8 /* Tabs every N columns */
++
++# define MXML_NO_CALLBACK 0 /* Don't use a type callback */
++# define MXML_INTEGER_CALLBACK mxml_integer_cb
++ /* Treat all data as integers */
++# define MXML_OPAQUE_CALLBACK mxml_opaque_cb
++ /* Treat all data as opaque */
++# define MXML_REAL_CALLBACK mxml_real_cb
++ /* Treat all data as real numbers */
++# define MXML_TEXT_CALLBACK 0 /* Treat all data as text */
++# define MXML_IGNORE_CALLBACK mxml_ignore_cb
++ /* Ignore all non-element content */
++
++# define MXML_NO_PARENT 0 /* No parent for the node */
++
++# define MXML_DESCEND 1 /* Descend when finding/walking */
++# define MXML_NO_DESCEND 0 /* Don't descend when finding/walking */
++# define MXML_DESCEND_FIRST -1 /* Descend for first find */
++
++# define MXML_WS_BEFORE_OPEN 0 /* Callback for before open tag */
++# define MXML_WS_AFTER_OPEN 1 /* Callback for after open tag */
++# define MXML_WS_BEFORE_CLOSE 2 /* Callback for before close tag */
++# define MXML_WS_AFTER_CLOSE 3 /* Callback for after close tag */
++
++# define MXML_ADD_BEFORE 0 /* Add node before specified node */
++# define MXML_ADD_AFTER 1 /* Add node after specified node */
++# define MXML_ADD_TO_PARENT NULL /* Add node relative to parent */
++
++
++/*
++ * Data types...
++ */
++
++typedef enum mxml_sax_event_e /**** SAX event type. ****/
++{
++ MXML_SAX_CDATA, /* CDATA node */
++ MXML_SAX_COMMENT, /* Comment node */
++ MXML_SAX_DATA, /* Data node */
++ MXML_SAX_DIRECTIVE, /* Processing directive node */
++ MXML_SAX_ELEMENT_CLOSE, /* Element closed */
++ MXML_SAX_ELEMENT_OPEN /* Element opened */
++} mxml_sax_event_t;
++
++typedef enum mxml_type_e /**** The XML node type. ****/
++{
++ MXML_IGNORE = -1, /* Ignore/throw away node @since Mini-XML 2.3@ */
++ MXML_ELEMENT, /* XML element with attributes */
++ MXML_INTEGER, /* Integer value */
++ MXML_OPAQUE, /* Opaque string */
++ MXML_REAL, /* Real value */
++ MXML_TEXT, /* Text fragment */
++ MXML_CUSTOM /* Custom data @since Mini-XML 2.1@ */
++} mxml_type_t;
++
++typedef void (*mxml_custom_destroy_cb_t)(void *);
++ /**** Custom data destructor ****/
++
++typedef void (*mxml_error_cb_t)(const char *);
++ /**** Error callback function ****/
++
++typedef struct mxml_attr_s /**** An XML element attribute value. @private@ ****/
++{
++ char *name; /* Attribute name */
++ char *value; /* Attribute value */
++} mxml_attr_t;
++
++typedef struct mxml_element_s /**** An XML element value. @private@ ****/
++{
++ char *name; /* Name of element */
++ int num_attrs; /* Number of attributes */
++ mxml_attr_t *attrs; /* Attributes */
++} mxml_element_t;
++
++typedef struct mxml_text_s /**** An XML text value. @private@ ****/
++{
++ int whitespace; /* Leading whitespace? */
++ char *string; /* Fragment string */
++} mxml_text_t;
++
++typedef struct mxml_custom_s /**** An XML custom value. @private@ ****/
++{
++ void *data; /* Pointer to (allocated) custom data */
++ mxml_custom_destroy_cb_t destroy; /* Pointer to destructor function */
++} mxml_custom_t;
++
++typedef union mxml_value_u /**** An XML node value. @private@ ****/
++{
++ mxml_element_t element; /* Element */
++ int integer; /* Integer number */
++ char *opaque; /* Opaque string */
++ double real; /* Real number */
++ mxml_text_t text; /* Text fragment */
++ mxml_custom_t custom; /* Custom data @since Mini-XML 2.1@ */
++} mxml_value_t;
++
++struct mxml_node_s /**** An XML node. @private@ ****/
++{
++ mxml_type_t type; /* Node type */
++ struct mxml_node_s *next; /* Next node under same parent */
++ struct mxml_node_s *prev; /* Previous node under same parent */
++ struct mxml_node_s *parent; /* Parent node */
++ struct mxml_node_s *child; /* First child node */
++ struct mxml_node_s *last_child; /* Last child node */
++ mxml_value_t value; /* Node value */
++ int ref_count; /* Use count */
++ void *user_data; /* User data */
++};
++
++typedef struct mxml_node_s mxml_node_t; /**** An XML node. ****/
++
++struct mxml_index_s /**** An XML node index. @private@ ****/
++{
++ char *attr; /* Attribute used for indexing or NULL */
++ int num_nodes; /* Number of nodes in index */
++ int alloc_nodes; /* Allocated nodes in index */
++ int cur_node; /* Current node */
++ mxml_node_t **nodes; /* Node array */
++};
++
++typedef struct mxml_index_s mxml_index_t;
++ /**** An XML node index. ****/
++
++typedef int (*mxml_custom_load_cb_t)(mxml_node_t *, const char *);
++ /**** Custom data load callback function ****/
++
++typedef char *(*mxml_custom_save_cb_t)(mxml_node_t *);
++ /**** Custom data save callback function ****/
++
++typedef int (*mxml_entity_cb_t)(const char *);
++ /**** Entity callback function */
++
++typedef mxml_type_t (*mxml_load_cb_t)(mxml_node_t *);
++ /**** Load callback function ****/
++
++typedef const char *(*mxml_save_cb_t)(mxml_node_t *, int);
++ /**** Save callback function ****/
++
++typedef void (*mxml_sax_cb_t)(mxml_node_t *, mxml_sax_event_t, void *);
++ /**** SAX callback function ****/
++
++
++/*
++ * C++ support...
++ */
++
++# ifdef __cplusplus
++extern "C" {
++# endif /* __cplusplus */
++
++/*
++ * Prototypes...
++ */
++
++extern void mxmlAdd(mxml_node_t *parent, int where,
++ mxml_node_t *child, mxml_node_t *node);
++extern void mxmlDelete(mxml_node_t *node);
++extern void mxmlElementDeleteAttr(mxml_node_t *node,
++ const char *name);
++extern const char *mxmlElementGetAttr(mxml_node_t *node, const char *name);
++extern void mxmlElementSetAttr(mxml_node_t *node, const char *name,
++ const char *value);
++extern void mxmlElementSetAttrf(mxml_node_t *node, const char *name,
++ const char *format, ...)
++# ifdef __GNUC__
++__attribute__ ((__format__ (__printf__, 3, 4)))
++# endif /* __GNUC__ */
++;
++extern int mxmlEntityAddCallback(mxml_entity_cb_t cb);
++extern const char *mxmlEntityGetName(int val);
++extern int mxmlEntityGetValue(const char *name);
++extern void mxmlEntityRemoveCallback(mxml_entity_cb_t cb);
++extern mxml_node_t *mxmlFindElement(mxml_node_t *node, mxml_node_t *top,
++ const char *name, const char *attr,
++ const char *value, int descend);
++extern mxml_node_t *mxmlFindPath(mxml_node_t *node, const char *path);
++extern const char *mxmlGetCDATA(mxml_node_t *node);
++extern const void *mxmlGetCustom(mxml_node_t *node);
++extern const char *mxmlGetElement(mxml_node_t *node);
++extern mxml_node_t *mxmlGetFirstChild(mxml_node_t *node);
++extern int mxmlGetInteger(mxml_node_t *node);
++extern mxml_node_t *mxmlGetLastChild(mxml_node_t *node);
++extern mxml_node_t *mxmlGetNextSibling(mxml_node_t *node);
++extern const char *mxmlGetOpaque(mxml_node_t *node);
++extern mxml_node_t *mxmlGetParent(mxml_node_t *node);
++extern mxml_node_t *mxmlGetPrevSibling(mxml_node_t *node);
++extern double mxmlGetReal(mxml_node_t *node);
++extern int mxmlGetRefCount(mxml_node_t *node);
++extern const char *mxmlGetText(mxml_node_t *node, int *whitespace);
++extern mxml_type_t mxmlGetType(mxml_node_t *node);
++extern void *mxmlGetUserData(mxml_node_t *node);
++extern void mxmlIndexDelete(mxml_index_t *ind);
++extern mxml_node_t *mxmlIndexEnum(mxml_index_t *ind);
++extern mxml_node_t *mxmlIndexFind(mxml_index_t *ind,
++ const char *element,
++ const char *value);
++extern int mxmlIndexGetCount(mxml_index_t *ind);
++extern mxml_index_t *mxmlIndexNew(mxml_node_t *node, const char *element,
++ const char *attr);
++extern mxml_node_t *mxmlIndexReset(mxml_index_t *ind);
++extern mxml_node_t *mxmlLoadFd(mxml_node_t *top, int fd,
++ mxml_type_t (*cb)(mxml_node_t *));
++extern mxml_node_t *mxmlLoadFile(mxml_node_t *top, FILE *fp,
++ mxml_type_t (*cb)(mxml_node_t *));
++extern mxml_node_t *mxmlLoadString(mxml_node_t *top, const char *s,
++ mxml_type_t (*cb)(mxml_node_t *));
++extern mxml_node_t *mxmlNewCDATA(mxml_node_t *parent, const char *string);
++extern mxml_node_t *mxmlNewCustom(mxml_node_t *parent, void *data,
++ mxml_custom_destroy_cb_t destroy);
++extern mxml_node_t *mxmlNewElement(mxml_node_t *parent, const char *name);
++extern mxml_node_t *mxmlNewInteger(mxml_node_t *parent, int integer);
++extern mxml_node_t *mxmlNewOpaque(mxml_node_t *parent, const char *opaque);
++extern mxml_node_t *mxmlNewReal(mxml_node_t *parent, double real);
++extern mxml_node_t *mxmlNewText(mxml_node_t *parent, int whitespace,
++ const char *string);
++extern mxml_node_t *mxmlNewTextf(mxml_node_t *parent, int whitespace,
++ const char *format, ...)
++# ifdef __GNUC__
++__attribute__ ((__format__ (__printf__, 3, 4)))
++# endif /* __GNUC__ */
++;
++extern mxml_node_t *mxmlNewXML(const char *version);
++extern int mxmlRelease(mxml_node_t *node);
++extern void mxmlRemove(mxml_node_t *node);
++extern int mxmlRetain(mxml_node_t *node);
++extern char *mxmlSaveAllocString(mxml_node_t *node,
++ mxml_save_cb_t cb);
++extern int mxmlSaveFd(mxml_node_t *node, int fd,
++ mxml_save_cb_t cb);
++extern int mxmlSaveFile(mxml_node_t *node, FILE *fp,
++ mxml_save_cb_t cb);
++extern int mxmlSaveString(mxml_node_t *node, char *buffer,
++ int bufsize, mxml_save_cb_t cb);
++extern mxml_node_t *mxmlSAXLoadFd(mxml_node_t *top, int fd,
++ mxml_type_t (*cb)(mxml_node_t *),
++ mxml_sax_cb_t sax, void *sax_data);
++extern mxml_node_t *mxmlSAXLoadFile(mxml_node_t *top, FILE *fp,
++ mxml_type_t (*cb)(mxml_node_t *),
++ mxml_sax_cb_t sax, void *sax_data);
++extern mxml_node_t *mxmlSAXLoadString(mxml_node_t *top, const char *s,
++ mxml_type_t (*cb)(mxml_node_t *),
++ mxml_sax_cb_t sax, void *sax_data);
++extern int mxmlSetCDATA(mxml_node_t *node, const char *data);
++extern int mxmlSetCustom(mxml_node_t *node, void *data,
++ mxml_custom_destroy_cb_t destroy);
++extern void mxmlSetCustomHandlers(mxml_custom_load_cb_t load,
++ mxml_custom_save_cb_t save);
++extern int mxmlSetElement(mxml_node_t *node, const char *name);
++extern void mxmlSetErrorCallback(mxml_error_cb_t cb);
++extern int mxmlSetInteger(mxml_node_t *node, int integer);
++extern int mxmlSetOpaque(mxml_node_t *node, const char *opaque);
++extern int mxmlSetReal(mxml_node_t *node, double real);
++extern int mxmlSetText(mxml_node_t *node, int whitespace,
++ const char *string);
++extern int mxmlSetTextf(mxml_node_t *node, int whitespace,
++ const char *format, ...)
++# ifdef __GNUC__
++__attribute__ ((__format__ (__printf__, 3, 4)))
++# endif /* __GNUC__ */
++;
++extern int mxmlSetUserData(mxml_node_t *node, void *data);
++extern void mxmlSetWrapMargin(int column);
++extern mxml_node_t *mxmlWalkNext(mxml_node_t *node, mxml_node_t *top,
++ int descend);
++extern mxml_node_t *mxmlWalkPrev(mxml_node_t *node, mxml_node_t *top,
++ int descend);
++
++
++/*
++ * Semi-private functions...
++ */
++
++extern void mxml_error(const char *format, ...);
++extern mxml_type_t mxml_ignore_cb(mxml_node_t *node);
++extern mxml_type_t mxml_integer_cb(mxml_node_t *node);
++extern mxml_type_t mxml_opaque_cb(mxml_node_t *node);
++extern mxml_type_t mxml_real_cb(mxml_node_t *node);
++
++
++/*
++ * C++ support...
++ */
++
++# ifdef __cplusplus
++}
++# endif /* __cplusplus */
++#endif /* !_mxml_h_ */
++
++
++/*
++ * End of "$Id: mxml.h 427 2011-01-03 02:03:29Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-index.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-index.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-index.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-index.c 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,662 @@
++/*
++ * "$Id: mxml-index.c 426 2011-01-01 23:42:17Z mike $"
++ *
++ * Index support code for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2011 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "config.h"
++#include "mxml.h"
++
++
++/*
++ * Sort functions...
++ */
++
++static int index_compare(mxml_index_t *ind, mxml_node_t *first,
++ mxml_node_t *second);
++static int index_find(mxml_index_t *ind, const char *element,
++ const char *value, mxml_node_t *node);
++static void index_sort(mxml_index_t *ind, int left, int right);
++
++
++/*
++ * 'mxmlIndexDelete()' - Delete an index.
++ */
++
++void
++mxmlIndexDelete(mxml_index_t *ind) /* I - Index to delete */
++{
++ /*
++ * Range check input..
++ */
++
++ if (!ind)
++ return;
++
++ /*
++ * Free memory...
++ */
++
++ if (ind->attr)
++ free(ind->attr);
++
++ if (ind->alloc_nodes)
++ free(ind->nodes);
++
++ free(ind);
++}
++
++
++/*
++ * 'mxmlIndexEnum()' - Return the next node in the index.
++ *
++ * Nodes are returned in the sorted order of the index.
++ */
++
++mxml_node_t * /* O - Next node or NULL if there is none */
++mxmlIndexEnum(mxml_index_t *ind) /* I - Index to enumerate */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!ind)
++ return (NULL);
++
++ /*
++ * Return the next node...
++ */
++
++ if (ind->cur_node < ind->num_nodes)
++ return (ind->nodes[ind->cur_node ++]);
++ else
++ return (NULL);
++}
++
++
++/*
++ * 'mxmlIndexFind()' - Find the next matching node.
++ *
++ * You should call mxmlIndexReset() prior to using this function for
++ * the first time with a particular set of "element" and "value"
++ * strings. Passing NULL for both "element" and "value" is equivalent
++ * to calling mxmlIndexEnum().
++ */
++
++mxml_node_t * /* O - Node or NULL if none found */
++mxmlIndexFind(mxml_index_t *ind, /* I - Index to search */
++ const char *element, /* I - Element name to find, if any */
++ const char *value) /* I - Attribute value, if any */
++{
++ int diff, /* Difference between names */
++ current, /* Current entity in search */
++ first, /* First entity in search */
++ last; /* Last entity in search */
++
++
++#ifdef DEBUG
++ printf("mxmlIndexFind(ind=%p, element=\"%s\", value=\"%s\")\n",
++ ind, element ? element : "(null)", value ? value : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!ind || (!ind->attr && value))
++ {
++#ifdef DEBUG
++ puts(" returning NULL...");
++ printf(" ind->attr=\"%s\"\n", ind->attr ? ind->attr : "(null)");
++#endif /* DEBUG */
++
++ return (NULL);
++ }
++
++ /*
++ * If both element and value are NULL, just enumerate the nodes in the
++ * index...
++ */
++
++ if (!element && !value)
++ return (mxmlIndexEnum(ind));
++
++ /*
++ * If there are no nodes in the index, return NULL...
++ */
++
++ if (!ind->num_nodes)
++ {
++#ifdef DEBUG
++ puts(" returning NULL...");
++ puts(" no nodes!");
++#endif /* DEBUG */
++
++ return (NULL);
++ }
++
++ /*
++ * If cur_node == 0, then find the first matching node...
++ */
++
++ if (ind->cur_node == 0)
++ {
++ /*
++ * Find the first node using a modified binary search algorithm...
++ */
++
++ first = 0;
++ last = ind->num_nodes - 1;
++
++#ifdef DEBUG
++ printf(" find first time, num_nodes=%d...\n", ind->num_nodes);
++#endif /* DEBUG */
++
++ while ((last - first) > 1)
++ {
++ current = (first + last) / 2;
++
++#ifdef DEBUG
++ printf(" first=%d, last=%d, current=%d\n", first, last, current);
++#endif /* DEBUG */
++
++ if ((diff = index_find(ind, element, value, ind->nodes[current])) == 0)
++ {
++ /*
++ * Found a match, move back to find the first...
++ */
++
++#ifdef DEBUG
++ puts(" match!");
++#endif /* DEBUG */
++
++ while (current > 0 &&
++ !index_find(ind, element, value, ind->nodes[current - 1]))
++ current --;
++
++#ifdef DEBUG
++ printf(" returning first match=%d\n", current);
++#endif /* DEBUG */
++
++ /*
++ * Return the first match and save the index to the next...
++ */
++
++ ind->cur_node = current + 1;
++
++ return (ind->nodes[current]);
++ }
++ else if (diff < 0)
++ last = current;
++ else
++ first = current;
++
++#ifdef DEBUG
++ printf(" diff=%d\n", diff);
++#endif /* DEBUG */
++ }
++
++ /*
++ * If we get this far, then we found exactly 0 or 1 matches...
++ */
++
++ for (current = first; current <= last; current ++)
++ if (!index_find(ind, element, value, ind->nodes[current]))
++ {
++ /*
++ * Found exactly one (or possibly two) match...
++ */
++
++#ifdef DEBUG
++ printf(" returning only match %d...\n", current);
++#endif /* DEBUG */
++
++ ind->cur_node = current + 1;
++
++ return (ind->nodes[current]);
++ }
++
++ /*
++ * No matches...
++ */
++
++ ind->cur_node = ind->num_nodes;
++
++#ifdef DEBUG
++ puts(" returning NULL...");
++#endif /* DEBUG */
++
++ return (NULL);
++ }
++ else if (ind->cur_node < ind->num_nodes &&
++ !index_find(ind, element, value, ind->nodes[ind->cur_node]))
++ {
++ /*
++ * Return the next matching node...
++ */
++
++#ifdef DEBUG
++ printf(" returning next match %d...\n", ind->cur_node);
++#endif /* DEBUG */
++
++ return (ind->nodes[ind->cur_node ++]);
++ }
++
++ /*
++ * If we get this far, then we have no matches...
++ */
++
++ ind->cur_node = ind->num_nodes;
++
++#ifdef DEBUG
++ puts(" returning NULL...");
++#endif /* DEBUG */
++
++ return (NULL);
++}
++
++
++/*
++ * 'mxmlIndexGetCount()' - Get the number of nodes in an index.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++int /* I - Number of nodes in index */
++mxmlIndexGetCount(mxml_index_t *ind) /* I - Index of nodes */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!ind)
++ return (0);
++
++ /*
++ * Return the number of nodes in the index...
++ */
++
++ return (ind->num_nodes);
++}
++
++
++/*
++ * 'mxmlIndexNew()' - Create a new index.
++ *
++ * The index will contain all nodes that contain the named element and/or
++ * attribute. If both "element" and "attr" are NULL, then the index will
++ * contain a sorted list of the elements in the node tree. Nodes are
++ * sorted by element name and optionally by attribute value if the "attr"
++ * argument is not NULL.
++ */
++
++mxml_index_t * /* O - New index */
++mxmlIndexNew(mxml_node_t *node, /* I - XML node tree */
++ const char *element, /* I - Element to index or NULL for all */
++ const char *attr) /* I - Attribute to index or NULL for none */
++{
++ mxml_index_t *ind; /* New index */
++ mxml_node_t *current, /* Current node in index */
++ **temp; /* Temporary node pointer array */
++
++
++ /*
++ * Range check input...
++ */
++
++#ifdef DEBUG
++ printf("mxmlIndexNew(node=%p, element=\"%s\", attr=\"%s\")\n",
++ node, element ? element : "(null)", attr ? attr : "(null)");
++#endif /* DEBUG */
++
++ if (!node)
++ return (NULL);
++
++ /*
++ * Create a new index...
++ */
++
++ if ((ind = calloc(1, sizeof(mxml_index_t))) == NULL)
++ {
++ mxml_error("Unable to allocate %d bytes for index - %s",
++ sizeof(mxml_index_t), strerror(errno));
++ return (NULL);
++ }
++
++ if (attr)
++ ind->attr = strdup(attr);
++
++ if (!element && !attr)
++ current = node;
++ else
++ current = mxmlFindElement(node, node, element, attr, NULL, MXML_DESCEND);
++
++ while (current)
++ {
++ if (ind->num_nodes >= ind->alloc_nodes)
++ {
++ if (!ind->alloc_nodes)
++ temp = malloc(64 * sizeof(mxml_node_t *));
++ else
++ temp = realloc(ind->nodes, (ind->alloc_nodes + 64) * sizeof(mxml_node_t *));
++
++ if (!temp)
++ {
++ /*
++ * Unable to allocate memory for the index, so abort...
++ */
++
++ mxml_error("Unable to allocate %d bytes for index: %s",
++ (ind->alloc_nodes + 64) * sizeof(mxml_node_t *),
++ strerror(errno));
++
++ mxmlIndexDelete(ind);
++ return (NULL);
++ }
++
++ ind->nodes = temp;
++ ind->alloc_nodes += 64;
++ }
++
++ ind->nodes[ind->num_nodes ++] = current;
++
++ current = mxmlFindElement(current, node, element, attr, NULL, MXML_DESCEND);
++ }
++
++ /*
++ * Sort nodes based upon the search criteria...
++ */
++
++#ifdef DEBUG
++ {
++ int i; /* Looping var */
++
++
++ printf("%d node(s) in index.\n\n", ind->num_nodes);
++
++ if (attr)
++ {
++ printf("Node Address Element %s\n", attr);
++ puts("-------- -------- -------------- ------------------------------");
++
++ for (i = 0; i < ind->num_nodes; i ++)
++ printf("%8d %-8p %-14.14s %s\n", i, ind->nodes[i],
++ ind->nodes[i]->value.element.name,
++ mxmlElementGetAttr(ind->nodes[i], attr));
++ }
++ else
++ {
++ puts("Node Address Element");
++ puts("-------- -------- --------------");
++
++ for (i = 0; i < ind->num_nodes; i ++)
++ printf("%8d %-8p %s\n", i, ind->nodes[i],
++ ind->nodes[i]->value.element.name);
++ }
++
++ putchar('\n');
++ }
++#endif /* DEBUG */
++
++ if (ind->num_nodes > 1)
++ index_sort(ind, 0, ind->num_nodes - 1);
++
++#ifdef DEBUG
++ {
++ int i; /* Looping var */
++
++
++ puts("After sorting:\n");
++
++ if (attr)
++ {
++ printf("Node Address Element %s\n", attr);
++ puts("-------- -------- -------------- ------------------------------");
++
++ for (i = 0; i < ind->num_nodes; i ++)
++ printf("%8d %-8p %-14.14s %s\n", i, ind->nodes[i],
++ ind->nodes[i]->value.element.name,
++ mxmlElementGetAttr(ind->nodes[i], attr));
++ }
++ else
++ {
++ puts("Node Address Element");
++ puts("-------- -------- --------------");
++
++ for (i = 0; i < ind->num_nodes; i ++)
++ printf("%8d %-8p %s\n", i, ind->nodes[i],
++ ind->nodes[i]->value.element.name);
++ }
++
++ putchar('\n');
++ }
++#endif /* DEBUG */
++
++ /*
++ * Return the new index...
++ */
++
++ return (ind);
++}
++
++
++/*
++ * 'mxmlIndexReset()' - Reset the enumeration/find pointer in the index and
++ * return the first node in the index.
++ *
++ * This function should be called prior to using mxmlIndexEnum() or
++ * mxmlIndexFind() for the first time.
++ */
++
++mxml_node_t * /* O - First node or NULL if there is none */
++mxmlIndexReset(mxml_index_t *ind) /* I - Index to reset */
++{
++#ifdef DEBUG
++ printf("mxmlIndexReset(ind=%p)\n", ind);
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!ind)
++ return (NULL);
++
++ /*
++ * Set the index to the first element...
++ */
++
++ ind->cur_node = 0;
++
++ /*
++ * Return the first node...
++ */
++
++ if (ind->num_nodes)
++ return (ind->nodes[0]);
++ else
++ return (NULL);
++}
++
++
++/*
++ * 'index_compare()' - Compare two nodes.
++ */
++
++static int /* O - Result of comparison */
++index_compare(mxml_index_t *ind, /* I - Index */
++ mxml_node_t *first, /* I - First node */
++ mxml_node_t *second) /* I - Second node */
++{
++ int diff; /* Difference */
++
++
++ /*
++ * Check the element name...
++ */
++
++ if ((diff = strcmp(first->value.element.name,
++ second->value.element.name)) != 0)
++ return (diff);
++
++ /*
++ * Check the attribute value...
++ */
++
++ if (ind->attr)
++ {
++ if ((diff = strcmp(mxmlElementGetAttr(first, ind->attr),
++ mxmlElementGetAttr(second, ind->attr))) != 0)
++ return (diff);
++ }
++
++ /*
++ * No difference, return 0...
++ */
++
++ return (0);
++}
++
++
++/*
++ * 'index_find()' - Compare a node with index values.
++ */
++
++static int /* O - Result of comparison */
++index_find(mxml_index_t *ind, /* I - Index */
++ const char *element, /* I - Element name or NULL */
++ const char *value, /* I - Attribute value or NULL */
++ mxml_node_t *node) /* I - Node */
++{
++ int diff; /* Difference */
++
++
++ /*
++ * Check the element name...
++ */
++
++ if (element)
++ {
++ if ((diff = strcmp(element, node->value.element.name)) != 0)
++ return (diff);
++ }
++
++ /*
++ * Check the attribute value...
++ */
++
++ if (value)
++ {
++ if ((diff = strcmp(value, mxmlElementGetAttr(node, ind->attr))) != 0)
++ return (diff);
++ }
++
++ /*
++ * No difference, return 0...
++ */
++
++ return (0);
++}
++
++
++/*
++ * 'index_sort()' - Sort the nodes in the index...
++ *
++ * This function implements the classic quicksort algorithm...
++ */
++
++static void
++index_sort(mxml_index_t *ind, /* I - Index to sort */
++ int left, /* I - Left node in partition */
++ int right) /* I - Right node in partition */
++{
++ mxml_node_t *pivot, /* Pivot node */
++ *temp; /* Swap node */
++ int templ, /* Temporary left node */
++ tempr; /* Temporary right node */
++
++
++ /*
++ * Loop until we have sorted all the way to the right...
++ */
++
++ do
++ {
++ /*
++ * Sort the pivot in the current partition...
++ */
++
++ pivot = ind->nodes[left];
++
++ for (templ = left, tempr = right; templ < tempr;)
++ {
++ /*
++ * Move left while left node <= pivot node...
++ */
++
++ while ((templ < right) &&
++ index_compare(ind, ind->nodes[templ], pivot) <= 0)
++ templ ++;
++
++ /*
++ * Move right while right node > pivot node...
++ */
++
++ while ((tempr > left) &&
++ index_compare(ind, ind->nodes[tempr], pivot) > 0)
++ tempr --;
++
++ /*
++ * Swap nodes if needed...
++ */
++
++ if (templ < tempr)
++ {
++ temp = ind->nodes[templ];
++ ind->nodes[templ] = ind->nodes[tempr];
++ ind->nodes[tempr] = temp;
++ }
++ }
++
++ /*
++ * When we get here, the right (tempr) node is the new position for the
++ * pivot node...
++ */
++
++ if (index_compare(ind, pivot, ind->nodes[tempr]) > 0)
++ {
++ ind->nodes[left] = ind->nodes[tempr];
++ ind->nodes[tempr] = pivot;
++ }
++
++ /*
++ * Recursively sort the left partition as needed...
++ */
++
++ if (left < (tempr - 1))
++ index_sort(ind, left, tempr - 1);
++ }
++ while (right > (left = tempr + 1));
++}
++
++
++/*
++ * End of "$Id: mxml-index.c 426 2011-01-01 23:42:17Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-node.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-node.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-node.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-node.c 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,807 @@
++/*
++ * "$Id: mxml-node.c 436 2011-01-22 01:02:05Z mike $"
++ *
++ * Node support code for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2011 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * mxmlAdd() - Add a node to a tree.
++ * mxmlDelete() - Delete a node and all of its children.
++ * mxmlGetRefCount() - Get the current reference (use) count for a node.
++ * mxmlNewCDATA() - Create a new CDATA node.
++ * mxmlNewCustom() - Create a new custom data node.
++ * mxmlNewElement() - Create a new element node.
++ * mxmlNewInteger() - Create a new integer node.
++ * mxmlNewOpaque() - Create a new opaque string.
++ * mxmlNewReal() - Create a new real number node.
++ * mxmlNewText() - Create a new text fragment node.
++ * mxmlNewTextf() - Create a new formatted text fragment node.
++ * mxmlRemove() - Remove a node from its parent.
++ * mxmlNewXML() - Create a new XML document tree.
++ * mxmlRelease() - Release a node.
++ * mxmlRetain() - Retain a node.
++ * mxml_new() - Create a new node.
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "config.h"
++#include "mxml.h"
++
++
++/*
++ * Local functions...
++ */
++
++static mxml_node_t *mxml_new(mxml_node_t *parent, mxml_type_t type);
++
++
++/*
++ * 'mxmlAdd()' - Add a node to a tree.
++ *
++ * Adds the specified node to the parent. If the child argument is not
++ * NULL, puts the new node before or after the specified child depending
++ * on the value of the where argument. If the child argument is NULL,
++ * puts the new node at the beginning of the child list (MXML_ADD_BEFORE)
++ * or at the end of the child list (MXML_ADD_AFTER). The constant
++ * MXML_ADD_TO_PARENT can be used to specify a NULL child pointer.
++ */
++
++void
++mxmlAdd(mxml_node_t *parent, /* I - Parent node */
++ int where, /* I - Where to add, MXML_ADD_BEFORE or MXML_ADD_AFTER */
++ mxml_node_t *child, /* I - Child node for where or MXML_ADD_TO_PARENT */
++ mxml_node_t *node) /* I - Node to add */
++{
++#ifdef DEBUG
++ fprintf(stderr, "mxmlAdd(parent=%p, where=%d, child=%p, node=%p)\n", parent,
++ where, child, node);
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!parent || !node)
++ return;
++
++#if DEBUG > 1
++ fprintf(stderr, " BEFORE: node->parent=%p\n", node->parent);
++ if (parent)
++ {
++ fprintf(stderr, " BEFORE: parent->child=%p\n", parent->child);
++ fprintf(stderr, " BEFORE: parent->last_child=%p\n", parent->last_child);
++ fprintf(stderr, " BEFORE: parent->prev=%p\n", parent->prev);
++ fprintf(stderr, " BEFORE: parent->next=%p\n", parent->next);
++ }
++#endif /* DEBUG > 1 */
++
++ /*
++ * Remove the node from any existing parent...
++ */
++
++ if (node->parent)
++ mxmlRemove(node);
++
++ /*
++ * Reset pointers...
++ */
++
++ node->parent = parent;
++
++ switch (where)
++ {
++ case MXML_ADD_BEFORE :
++ if (!child || child == parent->child || child->parent != parent)
++ {
++ /*
++ * Insert as first node under parent...
++ */
++
++ node->next = parent->child;
++
++ if (parent->child)
++ parent->child->prev = node;
++ else
++ parent->last_child = node;
++
++ parent->child = node;
++ }
++ else
++ {
++ /*
++ * Insert node before this child...
++ */
++
++ node->next = child;
++ node->prev = child->prev;
++
++ if (child->prev)
++ child->prev->next = node;
++ else
++ parent->child = node;
++
++ child->prev = node;
++ }
++ break;
++
++ case MXML_ADD_AFTER :
++ if (!child || child == parent->last_child || child->parent != parent)
++ {
++ /*
++ * Insert as last node under parent...
++ */
++
++ node->parent = parent;
++ node->prev = parent->last_child;
++
++ if (parent->last_child)
++ parent->last_child->next = node;
++ else
++ parent->child = node;
++
++ parent->last_child = node;
++ }
++ else
++ {
++ /*
++ * Insert node after this child...
++ */
++
++ node->prev = child;
++ node->next = child->next;
++
++ if (child->next)
++ child->next->prev = node;
++ else
++ parent->last_child = node;
++
++ child->next = node;
++ }
++ break;
++ }
++
++#if DEBUG > 1
++ fprintf(stderr, " AFTER: node->parent=%p\n", node->parent);
++ if (parent)
++ {
++ fprintf(stderr, " AFTER: parent->child=%p\n", parent->child);
++ fprintf(stderr, " AFTER: parent->last_child=%p\n", parent->last_child);
++ fprintf(stderr, " AFTER: parent->prev=%p\n", parent->prev);
++ fprintf(stderr, " AFTER: parent->next=%p\n", parent->next);
++ }
++#endif /* DEBUG > 1 */
++}
++
++
++/*
++ * 'mxmlDelete()' - Delete a node and all of its children.
++ *
++ * If the specified node has a parent, this function first removes the
++ * node from its parent using the mxmlRemove() function.
++ */
++
++void
++mxmlDelete(mxml_node_t *node) /* I - Node to delete */
++{
++ int i; /* Looping var */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlDelete(node=%p)\n", node);
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return;
++
++ /*
++ * Remove the node from its parent, if any...
++ */
++
++ mxmlRemove(node);
++
++ /*
++ * Delete children...
++ */
++
++ while (node->child)
++ mxmlDelete(node->child);
++
++ /*
++ * Now delete any node data...
++ */
++
++ switch (node->type)
++ {
++ case MXML_ELEMENT :
++ if (node->value.element.name)
++ free(node->value.element.name);
++
++ if (node->value.element.num_attrs)
++ {
++ for (i = 0; i < node->value.element.num_attrs; i ++)
++ {
++ if (node->value.element.attrs[i].name)
++ free(node->value.element.attrs[i].name);
++ if (node->value.element.attrs[i].value)
++ free(node->value.element.attrs[i].value);
++ }
++
++ free(node->value.element.attrs);
++ }
++ break;
++ case MXML_INTEGER :
++ /* Nothing to do */
++ break;
++ case MXML_OPAQUE :
++ if (node->value.opaque)
++ free(node->value.opaque);
++ break;
++ case MXML_REAL :
++ /* Nothing to do */
++ break;
++ case MXML_TEXT :
++ if (node->value.text.string)
++ free(node->value.text.string);
++ break;
++ case MXML_CUSTOM :
++ if (node->value.custom.data &&
++ node->value.custom.destroy)
++ (*(node->value.custom.destroy))(node->value.custom.data);
++ break;
++ default :
++ break;
++ }
++
++ /*
++ * Free this node...
++ */
++
++ free(node);
++}
++
++
++/*
++ * 'mxmlGetRefCount()' - Get the current reference (use) count for a node.
++ *
++ * The initial reference count of new nodes is 1. Use the @link mxmlRetain@
++ * and @link mxmlRelease@ functions to increment and decrement a node's
++ * reference count.
++ *
++ * @since Mini-XML 2.7@.
++ */
++
++int /* O - Reference count */
++mxmlGetRefCount(mxml_node_t *node) /* I - Node */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (0);
++
++ /*
++ * Return the reference count...
++ */
++
++ return (node->ref_count);
++}
++
++
++/*
++ * 'mxmlNewCDATA()' - Create a new CDATA node.
++ *
++ * The new CDATA node is added to the end of the specified parent's child
++ * list. The constant MXML_NO_PARENT can be used to specify that the new
++ * CDATA node has no parent. The data string must be nul-terminated and
++ * is copied into the new node. CDATA nodes use the MXML_ELEMENT type.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++mxml_node_t * /* O - New node */
++mxmlNewCDATA(mxml_node_t *parent, /* I - Parent node or MXML_NO_PARENT */
++ const char *data) /* I - Data string */
++{
++ mxml_node_t *node; /* New node */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlNewCDATA(parent=%p, data=\"%s\")\n",
++ parent, data ? data : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!data)
++ return (NULL);
++
++ /*
++ * Create the node and set the name value...
++ */
++
++ if ((node = mxml_new(parent, MXML_ELEMENT)) != NULL)
++ node->value.element.name = _mxml_strdupf("![CDATA[%s]]", data);
++
++ return (node);
++}
++
++
++/*
++ * 'mxmlNewCustom()' - Create a new custom data node.
++ *
++ * The new custom node is added to the end of the specified parent's child
++ * list. The constant MXML_NO_PARENT can be used to specify that the new
++ * element node has no parent. NULL can be passed when the data in the
++ * node is not dynamically allocated or is separately managed.
++ *
++ * @since Mini-XML 2.1@
++ */
++
++mxml_node_t * /* O - New node */
++mxmlNewCustom(
++ mxml_node_t *parent, /* I - Parent node or MXML_NO_PARENT */
++ void *data, /* I - Pointer to data */
++ mxml_custom_destroy_cb_t destroy) /* I - Function to destroy data */
++{
++ mxml_node_t *node; /* New node */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlNewCustom(parent=%p, data=%p, destroy=%p)\n", parent,
++ data, destroy);
++#endif /* DEBUG */
++
++ /*
++ * Create the node and set the value...
++ */
++
++ if ((node = mxml_new(parent, MXML_CUSTOM)) != NULL)
++ {
++ node->value.custom.data = data;
++ node->value.custom.destroy = destroy;
++ }
++
++ return (node);
++}
++
++
++/*
++ * 'mxmlNewElement()' - Create a new element node.
++ *
++ * The new element node is added to the end of the specified parent's child
++ * list. The constant MXML_NO_PARENT can be used to specify that the new
++ * element node has no parent.
++ */
++
++mxml_node_t * /* O - New node */
++mxmlNewElement(mxml_node_t *parent, /* I - Parent node or MXML_NO_PARENT */
++ const char *name) /* I - Name of element */
++{
++ mxml_node_t *node; /* New node */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlNewElement(parent=%p, name=\"%s\")\n", parent,
++ name ? name : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!name)
++ return (NULL);
++
++ /*
++ * Create the node and set the element name...
++ */
++
++ if ((node = mxml_new(parent, MXML_ELEMENT)) != NULL)
++ node->value.element.name = strdup(name);
++
++ return (node);
++}
++
++
++/*
++ * 'mxmlNewInteger()' - Create a new integer node.
++ *
++ * The new integer node is added to the end of the specified parent's child
++ * list. The constant MXML_NO_PARENT can be used to specify that the new
++ * integer node has no parent.
++ */
++
++mxml_node_t * /* O - New node */
++mxmlNewInteger(mxml_node_t *parent, /* I - Parent node or MXML_NO_PARENT */
++ int integer) /* I - Integer value */
++{
++ mxml_node_t *node; /* New node */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlNewInteger(parent=%p, integer=%d)\n", parent, integer);
++#endif /* DEBUG */
++
++ /*
++ * Create the node and set the element name...
++ */
++
++ if ((node = mxml_new(parent, MXML_INTEGER)) != NULL)
++ node->value.integer = integer;
++
++ return (node);
++}
++
++
++/*
++ * 'mxmlNewOpaque()' - Create a new opaque string.
++ *
++ * The new opaque node is added to the end of the specified parent's child
++ * list. The constant MXML_NO_PARENT can be used to specify that the new
++ * opaque node has no parent. The opaque string must be nul-terminated and
++ * is copied into the new node.
++ */
++
++mxml_node_t * /* O - New node */
++mxmlNewOpaque(mxml_node_t *parent, /* I - Parent node or MXML_NO_PARENT */
++ const char *opaque) /* I - Opaque string */
++{
++ mxml_node_t *node; /* New node */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlNewOpaque(parent=%p, opaque=\"%s\")\n", parent,
++ opaque ? opaque : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!opaque)
++ return (NULL);
++
++ /*
++ * Create the node and set the element name...
++ */
++
++ if ((node = mxml_new(parent, MXML_OPAQUE)) != NULL)
++ node->value.opaque = strdup(opaque);
++
++ return (node);
++}
++
++
++/*
++ * 'mxmlNewReal()' - Create a new real number node.
++ *
++ * The new real number node is added to the end of the specified parent's
++ * child list. The constant MXML_NO_PARENT can be used to specify that
++ * the new real number node has no parent.
++ */
++
++mxml_node_t * /* O - New node */
++mxmlNewReal(mxml_node_t *parent, /* I - Parent node or MXML_NO_PARENT */
++ double real) /* I - Real number value */
++{
++ mxml_node_t *node; /* New node */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlNewReal(parent=%p, real=%g)\n", parent, real);
++#endif /* DEBUG */
++
++ /*
++ * Create the node and set the element name...
++ */
++
++ if ((node = mxml_new(parent, MXML_REAL)) != NULL)
++ node->value.real = real;
++
++ return (node);
++}
++
++
++/*
++ * 'mxmlNewText()' - Create a new text fragment node.
++ *
++ * The new text node is added to the end of the specified parent's child
++ * list. The constant MXML_NO_PARENT can be used to specify that the new
++ * text node has no parent. The whitespace parameter is used to specify
++ * whether leading whitespace is present before the node. The text
++ * string must be nul-terminated and is copied into the new node.
++ */
++
++mxml_node_t * /* O - New node */
++mxmlNewText(mxml_node_t *parent, /* I - Parent node or MXML_NO_PARENT */
++ int whitespace, /* I - 1 = leading whitespace, 0 = no whitespace */
++ const char *string) /* I - String */
++{
++ mxml_node_t *node; /* New node */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlNewText(parent=%p, whitespace=%d, string=\"%s\")\n",
++ parent, whitespace, string ? string : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!string)
++ return (NULL);
++
++ /*
++ * Create the node and set the text value...
++ */
++
++ if ((node = mxml_new(parent, MXML_TEXT)) != NULL)
++ {
++ node->value.text.whitespace = whitespace;
++ node->value.text.string = strdup(string);
++ }
++
++ return (node);
++}
++
++
++/*
++ * 'mxmlNewTextf()' - Create a new formatted text fragment node.
++ *
++ * The new text node is added to the end of the specified parent's child
++ * list. The constant MXML_NO_PARENT can be used to specify that the new
++ * text node has no parent. The whitespace parameter is used to specify
++ * whether leading whitespace is present before the node. The format
++ * string must be nul-terminated and is formatted into the new node.
++ */
++
++mxml_node_t * /* O - New node */
++mxmlNewTextf(mxml_node_t *parent, /* I - Parent node or MXML_NO_PARENT */
++ int whitespace, /* I - 1 = leading whitespace, 0 = no whitespace */
++ const char *format, /* I - Printf-style frmat string */
++ ...) /* I - Additional args as needed */
++{
++ mxml_node_t *node; /* New node */
++ va_list ap; /* Pointer to arguments */
++
++
++#ifdef DEBUG
++ fprintf(stderr, "mxmlNewTextf(parent=%p, whitespace=%d, format=\"%s\", ...)\n",
++ parent, whitespace, format ? format : "(null)");
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!format)
++ return (NULL);
++
++ /*
++ * Create the node and set the text value...
++ */
++
++ if ((node = mxml_new(parent, MXML_TEXT)) != NULL)
++ {
++ va_start(ap, format);
++
++ node->value.text.whitespace = whitespace;
++ node->value.text.string = _mxml_vstrdupf(format, ap);
++
++ va_end(ap);
++ }
++
++ return (node);
++}
++
++
++/*
++ * 'mxmlRemove()' - Remove a node from its parent.
++ *
++ * Does not free memory used by the node - use mxmlDelete() for that.
++ * This function does nothing if the node has no parent.
++ */
++
++void
++mxmlRemove(mxml_node_t *node) /* I - Node to remove */
++{
++#ifdef DEBUG
++ fprintf(stderr, "mxmlRemove(node=%p)\n", node);
++#endif /* DEBUG */
++
++ /*
++ * Range check input...
++ */
++
++ if (!node || !node->parent)
++ return;
++
++ /*
++ * Remove from parent...
++ */
++
++#if DEBUG > 1
++ fprintf(stderr, " BEFORE: node->parent=%p\n", node->parent);
++ if (node->parent)
++ {
++ fprintf(stderr, " BEFORE: node->parent->child=%p\n", node->parent->child);
++ fprintf(stderr, " BEFORE: node->parent->last_child=%p\n", node->parent->last_child);
++ }
++ fprintf(stderr, " BEFORE: node->child=%p\n", node->child);
++ fprintf(stderr, " BEFORE: node->last_child=%p\n", node->last_child);
++ fprintf(stderr, " BEFORE: node->prev=%p\n", node->prev);
++ fprintf(stderr, " BEFORE: node->next=%p\n", node->next);
++#endif /* DEBUG > 1 */
++
++ if (node->prev)
++ node->prev->next = node->next;
++ else
++ node->parent->child = node->next;
++
++ if (node->next)
++ node->next->prev = node->prev;
++ else
++ node->parent->last_child = node->prev;
++
++ node->parent = NULL;
++ node->prev = NULL;
++ node->next = NULL;
++
++#if DEBUG > 1
++ fprintf(stderr, " AFTER: node->parent=%p\n", node->parent);
++ if (node->parent)
++ {
++ fprintf(stderr, " AFTER: node->parent->child=%p\n", node->parent->child);
++ fprintf(stderr, " AFTER: node->parent->last_child=%p\n", node->parent->last_child);
++ }
++ fprintf(stderr, " AFTER: node->child=%p\n", node->child);
++ fprintf(stderr, " AFTER: node->last_child=%p\n", node->last_child);
++ fprintf(stderr, " AFTER: node->prev=%p\n", node->prev);
++ fprintf(stderr, " AFTER: node->next=%p\n", node->next);
++#endif /* DEBUG > 1 */
++}
++
++
++/*
++ * 'mxmlNewXML()' - Create a new XML document tree.
++ *
++ * The "version" argument specifies the version number to put in the
++ * ?xml element node. If NULL, version 1.0 is assumed.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++mxml_node_t * /* O - New ?xml node */
++mxmlNewXML(const char *version) /* I - Version number to use */
++{
++ char element[1024]; /* Element text */
++
++
++ snprintf(element, sizeof(element), "?xml version=\"%s\" encoding=\"utf-8\"?",
++ version ? version : "1.0");
++
++ return (mxmlNewElement(NULL, element));
++}
++
++
++/*
++ * 'mxmlRelease()' - Release a node.
++ *
++ * When the reference count reaches zero, the node (and any children)
++ * is deleted via mxmlDelete().
++ *
++ * @since Mini-XML 2.3@
++ */
++
++int /* O - New reference count */
++mxmlRelease(mxml_node_t *node) /* I - Node */
++{
++ if (node)
++ {
++ if ((-- node->ref_count) <= 0)
++ {
++ mxmlDelete(node);
++ return (0);
++ }
++ else
++ return (node->ref_count);
++ }
++ else
++ return (-1);
++}
++
++
++/*
++ * 'mxmlRetain()' - Retain a node.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++int /* O - New reference count */
++mxmlRetain(mxml_node_t *node) /* I - Node */
++{
++ if (node)
++ return (++ node->ref_count);
++ else
++ return (-1);
++}
++
++
++/*
++ * 'mxml_new()' - Create a new node.
++ */
++
++static mxml_node_t * /* O - New node */
++mxml_new(mxml_node_t *parent, /* I - Parent node */
++ mxml_type_t type) /* I - Node type */
++{
++ mxml_node_t *node; /* New node */
++
++
++#if DEBUG > 1
++ fprintf(stderr, "mxml_new(parent=%p, type=%d)\n", parent, type);
++#endif /* DEBUG > 1 */
++
++ /*
++ * Allocate memory for the node...
++ */
++
++ if ((node = calloc(1, sizeof(mxml_node_t))) == NULL)
++ {
++#if DEBUG > 1
++ fputs(" returning NULL\n", stderr);
++#endif /* DEBUG > 1 */
++
++ return (NULL);
++ }
++
++#if DEBUG > 1
++ fprintf(stderr, " returning %p\n", node);
++#endif /* DEBUG > 1 */
++
++ /*
++ * Set the node type...
++ */
++
++ node->type = type;
++ node->ref_count = 1;
++
++ /*
++ * Add to the parent if present...
++ */
++
++ if (parent)
++ mxmlAdd(parent, MXML_ADD_AFTER, MXML_ADD_TO_PARENT, node);
++
++ /*
++ * Return the new node...
++ */
++
++ return (node);
++}
++
++
++/*
++ * End of "$Id: mxml-node.c 436 2011-01-22 01:02:05Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-private.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-private.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-private.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-private.c 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,331 @@
++/*
++ * "$Id: mxml-private.c 422 2010-11-07 22:55:11Z mike $"
++ *
++ * Private functions for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2010 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * mxml_error() - Display an error message.
++ * mxml_integer_cb() - Default callback for integer values.
++ * mxml_opaque_cb() - Default callback for opaque values.
++ * mxml_real_cb() - Default callback for real number values.
++ * _mxml_global() - Get global data.
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "mxml-private.h"
++
++
++/*
++ * Some crazy people think that unloading a shared object is a good or safe
++ * thing to do. Unfortunately, most objects are simply *not* safe to unload
++ * and bad things *will* happen.
++ *
++ * The following mess of conditional code allows us to provide a destructor
++ * function in Mini-XML for our thread-global storage so that it can possibly
++ * be unloaded safely, although since there is no standard way to do so I
++ * can't even provide any guarantees that you can do it safely on all platforms.
++ *
++ * This code currently supports AIX, HP-UX, Linux, Mac OS X, Solaris, and
++ * Windows. It might work on the BSDs and IRIX, but I haven't tested that.
++ */
++
++#if defined(__sun) || defined(_AIX)
++# pragma fini(_mxml_fini)
++# define _MXML_FINI _mxml_fini
++#elif defined(__hpux)
++# pragma FINI _mxml_fini
++# define _MXML_FINI _mxml_fini
++#elif defined(__GNUC__) /* Linux and Mac OS X */
++# define _MXML_FINI __attribute((destructor)) _mxml_fini
++#else
++# define _MXML_FINI _fini
++#endif /* __sun */
++
++
++/*
++ * 'mxml_error()' - Display an error message.
++ */
++
++void
++mxml_error(const char *format, /* I - Printf-style format string */
++ ...) /* I - Additional arguments as needed */
++{
++ va_list ap; /* Pointer to arguments */
++ char s[1024]; /* Message string */
++ _mxml_global_t *global = _mxml_global();
++ /* Global data */
++
++
++ /*
++ * Range check input...
++ */
++
++ if (!format)
++ return;
++
++ /*
++ * Format the error message string...
++ */
++
++ va_start(ap, format);
++
++ vsnprintf(s, sizeof(s), format, ap);
++
++ va_end(ap);
++
++ /*
++ * And then display the error message...
++ */
++
++ if (global->error_cb)
++ (*global->error_cb)(s);
++ else
++ fprintf(stderr, "mxml: %s\n", s);
++}
++
++
++/*
++ * 'mxml_ignore_cb()' - Default callback for ignored values.
++ */
++
++mxml_type_t /* O - Node type */
++mxml_ignore_cb(mxml_node_t *node) /* I - Current node */
++{
++ (void)node;
++
++ return (MXML_IGNORE);
++}
++
++
++/*
++ * 'mxml_integer_cb()' - Default callback for integer values.
++ */
++
++mxml_type_t /* O - Node type */
++mxml_integer_cb(mxml_node_t *node) /* I - Current node */
++{
++ (void)node;
++
++ return (MXML_INTEGER);
++}
++
++
++/*
++ * 'mxml_opaque_cb()' - Default callback for opaque values.
++ */
++
++mxml_type_t /* O - Node type */
++mxml_opaque_cb(mxml_node_t *node) /* I - Current node */
++{
++ (void)node;
++
++ return (MXML_OPAQUE);
++}
++
++
++/*
++ * 'mxml_real_cb()' - Default callback for real number values.
++ */
++
++mxml_type_t /* O - Node type */
++mxml_real_cb(mxml_node_t *node) /* I - Current node */
++{
++ (void)node;
++
++ return (MXML_REAL);
++}
++
++
++#ifdef HAVE_PTHREAD_H /**** POSIX threading ****/
++# include <pthread.h>
++
++static pthread_key_t _mxml_key = -1; /* Thread local storage key */
++static pthread_once_t _mxml_key_once = PTHREAD_ONCE_INIT;
++ /* One-time initialization object */
++static void _mxml_init(void);
++static void _mxml_destructor(void *g);
++
++
++/*
++ * '_mxml_destructor()' - Free memory used for globals...
++ */
++
++static void
++_mxml_destructor(void *g) /* I - Global data */
++{
++ free(g);
++}
++
++
++/*
++ * '_mxml_fini()' - Clean up when unloaded.
++ */
++
++static void
++_MXML_FINI(void)
++{
++ _mxml_global_t *global; /* Global data */
++
++
++ if (_mxml_key != -1)
++ {
++ if ((global = (_mxml_global_t *)pthread_getspecific(_mxml_key)) != NULL)
++ _mxml_destructor(global);
++
++ pthread_key_delete(_mxml_key);
++ _mxml_key = -1;
++ }
++}
++
++
++/*
++ * '_mxml_global()' - Get global data.
++ */
++
++_mxml_global_t * /* O - Global data */
++_mxml_global(void)
++{
++ _mxml_global_t *global; /* Global data */
++
++
++ pthread_once(&_mxml_key_once, _mxml_init);
++
++ if ((global = (_mxml_global_t *)pthread_getspecific(_mxml_key)) == NULL)
++ {
++ global = (_mxml_global_t *)calloc(1, sizeof(_mxml_global_t));
++ pthread_setspecific(_mxml_key, global);
++
++ global->num_entity_cbs = 1;
++ global->entity_cbs[0] = _mxml_entity_cb;
++ global->wrap = 72;
++ }
++
++ return (global);
++}
++
++
++/*
++ * '_mxml_init()' - Initialize global data...
++ */
++
++static void
++_mxml_init(void)
++{
++ pthread_key_create(&_mxml_key, _mxml_destructor);
++}
++
++
++#elif defined(WIN32) && defined(MXML1_EXPORTS) /**** WIN32 threading ****/
++# include <windows.h>
++
++static DWORD _mxml_tls_index; /* Index for global storage */
++
++
++/*
++ * 'DllMain()' - Main entry for library.
++ */
++
++BOOL WINAPI /* O - Success/failure */
++DllMain(HINSTANCE hinst, /* I - DLL module handle */
++ DWORD reason, /* I - Reason */
++ LPVOID reserved) /* I - Unused */
++{
++ _mxml_global_t *global; /* Global data */
++
++
++ (void)hinst;
++ (void)reserved;
++
++ switch (reason)
++ {
++ case DLL_PROCESS_ATTACH : /* Called on library initialization */
++ if ((_mxml_tls_index = TlsAlloc()) == TLS_OUT_OF_INDEXES)
++ return (FALSE);
++ break;
++
++ case DLL_THREAD_DETACH : /* Called when a thread terminates */
++ if ((global = (_mxml_global_t *)TlsGetValue(_mxml_tls_index)) != NULL)
++ free(global);
++ break;
++
++ case DLL_PROCESS_DETACH : /* Called when library is unloaded */
++ if ((global = (_mxml_global_t *)TlsGetValue(_mxml_tls_index)) != NULL)
++ free(global);
++
++ TlsFree(_mxml_tls_index);
++ break;
++
++ default:
++ break;
++ }
++
++ return (TRUE);
++}
++
++
++/*
++ * '_mxml_global()' - Get global data.
++ */
++
++_mxml_global_t * /* O - Global data */
++_mxml_global(void)
++{
++ _mxml_global_t *global; /* Global data */
++
++
++ if ((global = (_mxml_global_t *)TlsGetValue(_mxml_tls_index)) == NULL)
++ {
++ global = (_mxml_global_t *)calloc(1, sizeof(_mxml_global_t));
++
++ global->num_entity_cbs = 1;
++ global->entity_cbs[0] = _mxml_entity_cb;
++ global->wrap = 72;
++
++ TlsSetValue(_mxml_tls_index, (LPVOID)global);
++ }
++
++ return (global);
++}
++
++
++#else /**** No threading ****/
++/*
++ * '_mxml_global()' - Get global data.
++ */
++
++_mxml_global_t * /* O - Global data */
++_mxml_global(void)
++{
++ static _mxml_global_t global = /* Global data */
++ {
++ NULL, /* error_cb */
++ 1, /* num_entity_cbs */
++ { _mxml_entity_cb }, /* entity_cbs */
++ 72, /* wrap */
++ NULL, /* custom_load_cb */
++ NULL /* custom_save_cb */
++ };
++
++
++ return (&global);
++}
++#endif /* HAVE_PTHREAD_H */
++
++
++/*
++ * End of "$Id: mxml-private.c 422 2010-11-07 22:55:11Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-private.h linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-private.h
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-private.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-private.h 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,50 @@
++/*
++ * "$Id: mxml-private.h 408 2010-09-19 05:26:46Z mike $"
++ *
++ * Private definitions for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2010 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "config.h"
++#include "mxml.h"
++
++
++/*
++ * Global, per-thread data...
++ */
++
++typedef struct _mxml_global_s
++{
++ void (*error_cb)(const char *);
++ int num_entity_cbs;
++ int (*entity_cbs[100])(const char *name);
++ int wrap;
++ mxml_custom_load_cb_t custom_load_cb;
++ mxml_custom_save_cb_t custom_save_cb;
++} _mxml_global_t;
++
++
++/*
++ * Functions...
++ */
++
++extern _mxml_global_t *_mxml_global(void);
++extern int _mxml_entity_cb(const char *name);
++
++
++/*
++ * End of "$Id: mxml-private.h 408 2010-09-19 05:26:46Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-search.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-search.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-search.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-search.c 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,287 @@
++/*
++ * "$Id: mxml-search.c 427 2011-01-03 02:03:29Z mike $"
++ *
++ * Search/navigation functions for Mini-XML, a small XML-like file
++ * parsing library.
++ *
++ * Copyright 2003-2010 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * mxmlFindElement() - Find the named element.
++ * mxmlFindValue() - Find a value with the given path.
++ * mxmlWalkNext() - Walk to the next logical node in the tree.
++ * mxmlWalkPrev() - Walk to the previous logical node in the tree.
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "config.h"
++#include "mxml.h"
++
++
++/*
++ * 'mxmlFindElement()' - Find the named element.
++ *
++ * The search is constrained by the name, attribute name, and value; any
++ * NULL names or values are treated as wildcards, so different kinds of
++ * searches can be implemented by looking for all elements of a given name
++ * or all elements with a specific attribute. The descend argument determines
++ * whether the search descends into child nodes; normally you will use
++ * MXML_DESCEND_FIRST for the initial search and MXML_NO_DESCEND to find
++ * additional direct descendents of the node. The top node argument
++ * constrains the search to a particular node's children.
++ */
++
++mxml_node_t * /* O - Element node or NULL */
++mxmlFindElement(mxml_node_t *node, /* I - Current node */
++ mxml_node_t *top, /* I - Top node */
++ const char *name, /* I - Element name or NULL for any */
++ const char *attr, /* I - Attribute name, or NULL for none */
++ const char *value, /* I - Attribute value, or NULL for any */
++ int descend) /* I - Descend into tree - MXML_DESCEND, MXML_NO_DESCEND, or MXML_DESCEND_FIRST */
++{
++ const char *temp; /* Current attribute value */
++
++
++ /*
++ * Range check input...
++ */
++
++ if (!node || !top || (!attr && value))
++ return (NULL);
++
++ /*
++ * Start with the next node...
++ */
++
++ node = mxmlWalkNext(node, top, descend);
++
++ /*
++ * Loop until we find a matching element...
++ */
++
++ while (node != NULL)
++ {
++ /*
++ * See if this node matches...
++ */
++
++ if (node->type == MXML_ELEMENT &&
++ node->value.element.name &&
++ (!name || !strcmp(node->value.element.name, name)))
++ {
++ /*
++ * See if we need to check for an attribute...
++ */
++
++ if (!attr)
++ return (node); /* No attribute search, return it... */
++
++ /*
++ * Check for the attribute...
++ */
++
++ if ((temp = mxmlElementGetAttr(node, attr)) != NULL)
++ {
++ /*
++ * OK, we have the attribute, does it match?
++ */
++
++ if (!value || !strcmp(value, temp))
++ return (node); /* Yes, return it... */
++ }
++ }
++
++ /*
++ * No match, move on to the next node...
++ */
++
++ if (descend == MXML_DESCEND)
++ node = mxmlWalkNext(node, top, MXML_DESCEND);
++ else
++ node = node->next;
++ }
++
++ return (NULL);
++}
++
++
++/*
++ * 'mxmlFindPath()' - Find a node with the given path.
++ *
++ * The "path" is a slash-separated list of element names. The name "*" is
++ * considered a wildcard for one or more levels of elements. For example,
++ * "foo/one/two", "bar/two/one", "*\/one", and so forth.
++ *
++ * The first child node of the found node is returned if the given node has
++ * children and the first child is a value node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++mxml_node_t * /* O - Found node or NULL */
++mxmlFindPath(mxml_node_t *top, /* I - Top node */
++ const char *path) /* I - Path to element */
++{
++ mxml_node_t *node; /* Current node */
++ char element[256]; /* Current element name */
++ const char *pathsep; /* Separator in path */
++ int descend; /* mxmlFindElement option */
++
++
++ /*
++ * Range check input...
++ */
++
++ if (!top || !path || !*path)
++ return (NULL);
++
++ /*
++ * Search each element in the path...
++ */
++
++ node = top;
++ while (*path)
++ {
++ /*
++ * Handle wildcards...
++ */
++
++ if (!strncmp(path, "*/", 2))
++ {
++ path += 2;
++ descend = MXML_DESCEND;
++ }
++ else
++ descend = MXML_DESCEND_FIRST;
++
++ /*
++ * Get the next element in the path...
++ */
++
++ if ((pathsep = strchr(path, '/')) == NULL)
++ pathsep = path + strlen(path);
++
++ if (pathsep == path || (pathsep - path) >= sizeof(element))
++ return (NULL);
++
++ memcpy(element, path, pathsep - path);
++ element[pathsep - path] = '\0';
++
++ if (*pathsep)
++ path = pathsep + 1;
++ else
++ path = pathsep;
++
++ /*
++ * Search for the element...
++ */
++
++ if ((node = mxmlFindElement(node, node, element, NULL, NULL,
++ descend)) == NULL)
++ return (NULL);
++ }
++
++ /*
++ * If we get this far, return the node or its first child...
++ */
++
++ if (node->child && node->child->type != MXML_ELEMENT)
++ return (node->child);
++ else
++ return (node);
++}
++
++
++/*
++ * 'mxmlWalkNext()' - Walk to the next logical node in the tree.
++ *
++ * The descend argument controls whether the first child is considered
++ * to be the next node. The top node argument constrains the walk to
++ * the node's children.
++ */
++
++mxml_node_t * /* O - Next node or NULL */
++mxmlWalkNext(mxml_node_t *node, /* I - Current node */
++ mxml_node_t *top, /* I - Top node */
++ int descend) /* I - Descend into tree - MXML_DESCEND, MXML_NO_DESCEND, or MXML_DESCEND_FIRST */
++{
++ if (!node)
++ return (NULL);
++ else if (node->child && descend)
++ return (node->child);
++ else if (node == top)
++ return (NULL);
++ else if (node->next)
++ return (node->next);
++ else if (node->parent && node->parent != top)
++ {
++ node = node->parent;
++
++ while (!node->next)
++ if (node->parent == top || !node->parent)
++ return (NULL);
++ else
++ node = node->parent;
++
++ return (node->next);
++ }
++ else
++ return (NULL);
++}
++
++
++/*
++ * 'mxmlWalkPrev()' - Walk to the previous logical node in the tree.
++ *
++ * The descend argument controls whether the previous node's last child
++ * is considered to be the previous node. The top node argument constrains
++ * the walk to the node's children.
++ */
++
++mxml_node_t * /* O - Previous node or NULL */
++mxmlWalkPrev(mxml_node_t *node, /* I - Current node */
++ mxml_node_t *top, /* I - Top node */
++ int descend) /* I - Descend into tree - MXML_DESCEND, MXML_NO_DESCEND, or MXML_DESCEND_FIRST */
++{
++ if (!node || node == top)
++ return (NULL);
++ else if (node->prev)
++ {
++ if (node->prev->last_child && descend)
++ {
++ /*
++ * Find the last child under the previous node...
++ */
++
++ node = node->prev->last_child;
++
++ while (node->last_child)
++ node = node->last_child;
++
++ return (node);
++ }
++ else
++ return (node->prev);
++ }
++ else if (node->parent != top)
++ return (node->parent);
++ else
++ return (NULL);
++}
++
++
++/*
++ * End of "$Id: mxml-search.c 427 2011-01-03 02:03:29Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-set.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-set.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-set.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-set.c 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,349 @@
++/*
++ * "$Id: mxml-set.c 441 2011-12-09 23:49:00Z mike $"
++ *
++ * Node set functions for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2011 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * mxmlSetCDATA() - Set the element name of a CDATA node.
++ * mxmlSetCustom() - Set the data and destructor of a custom data node.
++ * mxmlSetElement() - Set the name of an element node.
++ * mxmlSetInteger() - Set the value of an integer node.
++ * mxmlSetOpaque() - Set the value of an opaque node.
++ * mxmlSetReal() - Set the value of a real number node.
++ * mxmlSetText() - Set the value of a text node.
++ * mxmlSetTextf() - Set the value of a text node to a formatted string.
++ * mxmlSetUserData() - Set the user data pointer for a node.
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "config.h"
++#include "mxml.h"
++
++
++/*
++ * 'mxmlSetCDATA()' - Set the element name of a CDATA node.
++ *
++ * The node is not changed if it (or its first child) is not a CDATA element node.
++ *
++ * @since Mini-XML 2.3@
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetCDATA(mxml_node_t *node, /* I - Node to set */
++ const char *data) /* I - New data string */
++{
++ /*
++ * Range check input...
++ */
++
++ if (node && node->type == MXML_ELEMENT &&
++ strncmp(node->value.element.name, "![CDATA[", 8) &&
++ node->child && node->child->type == MXML_ELEMENT &&
++ !strncmp(node->child->value.element.name, "![CDATA[", 8))
++ node = node->child;
++
++ if (!node || node->type != MXML_ELEMENT || !data ||
++ strncmp(node->value.element.name, "![CDATA[", 8))
++ return (-1);
++
++ /*
++ * Free any old element value and set the new value...
++ */
++
++ if (node->value.element.name)
++ free(node->value.element.name);
++
++ node->value.element.name = _mxml_strdupf("![CDATA[%s]]", data);
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSetCustom()' - Set the data and destructor of a custom data node.
++ *
++ * The node is not changed if it (or its first child) is not a custom node.
++ *
++ * @since Mini-XML 2.1@
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetCustom(
++ mxml_node_t *node, /* I - Node to set */
++ void *data, /* I - New data pointer */
++ mxml_custom_destroy_cb_t destroy) /* I - New destructor function */
++{
++ /*
++ * Range check input...
++ */
++
++ if (node && node->type == MXML_ELEMENT &&
++ node->child && node->child->type == MXML_CUSTOM)
++ node = node->child;
++
++ if (!node || node->type != MXML_CUSTOM)
++ return (-1);
++
++ /*
++ * Free any old element value and set the new value...
++ */
++
++ if (node->value.custom.data && node->value.custom.destroy)
++ (*(node->value.custom.destroy))(node->value.custom.data);
++
++ node->value.custom.data = data;
++ node->value.custom.destroy = destroy;
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSetElement()' - Set the name of an element node.
++ *
++ * The node is not changed if it is not an element node.
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetElement(mxml_node_t *node, /* I - Node to set */
++ const char *name) /* I - New name string */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node || node->type != MXML_ELEMENT || !name)
++ return (-1);
++
++ /*
++ * Free any old element value and set the new value...
++ */
++
++ if (node->value.element.name)
++ free(node->value.element.name);
++
++ node->value.element.name = strdup(name);
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSetInteger()' - Set the value of an integer node.
++ *
++ * The node is not changed if it (or its first child) is not an integer node.
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetInteger(mxml_node_t *node, /* I - Node to set */
++ int integer) /* I - Integer value */
++{
++ /*
++ * Range check input...
++ */
++
++ if (node && node->type == MXML_ELEMENT &&
++ node->child && node->child->type == MXML_INTEGER)
++ node = node->child;
++
++ if (!node || node->type != MXML_INTEGER)
++ return (-1);
++
++ /*
++ * Set the new value and return...
++ */
++
++ node->value.integer = integer;
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSetOpaque()' - Set the value of an opaque node.
++ *
++ * The node is not changed if it (or its first child) is not an opaque node.
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetOpaque(mxml_node_t *node, /* I - Node to set */
++ const char *opaque) /* I - Opaque string */
++{
++ /*
++ * Range check input...
++ */
++
++ if (node && node->type == MXML_ELEMENT &&
++ node->child && node->child->type == MXML_OPAQUE)
++ node = node->child;
++
++ if (!node || node->type != MXML_OPAQUE || !opaque)
++ return (-1);
++
++ /*
++ * Free any old opaque value and set the new value...
++ */
++
++ if (node->value.opaque)
++ free(node->value.opaque);
++
++ node->value.opaque = strdup(opaque);
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSetReal()' - Set the value of a real number node.
++ *
++ * The node is not changed if it (or its first child) is not a real number node.
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetReal(mxml_node_t *node, /* I - Node to set */
++ double real) /* I - Real number value */
++{
++ /*
++ * Range check input...
++ */
++
++ if (node && node->type == MXML_ELEMENT &&
++ node->child && node->child->type == MXML_REAL)
++ node = node->child;
++
++ if (!node || node->type != MXML_REAL)
++ return (-1);
++
++ /*
++ * Set the new value and return...
++ */
++
++ node->value.real = real;
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSetText()' - Set the value of a text node.
++ *
++ * The node is not changed if it (or its first child) is not a text node.
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetText(mxml_node_t *node, /* I - Node to set */
++ int whitespace, /* I - 1 = leading whitespace, 0 = no whitespace */
++ const char *string) /* I - String */
++{
++ /*
++ * Range check input...
++ */
++
++ if (node && node->type == MXML_ELEMENT &&
++ node->child && node->child->type == MXML_TEXT)
++ node = node->child;
++
++ if (!node || node->type != MXML_TEXT || !string)
++ return (-1);
++
++ /*
++ * Free any old string value and set the new value...
++ */
++
++ if (node->value.text.string)
++ free(node->value.text.string);
++
++ node->value.text.whitespace = whitespace;
++ node->value.text.string = strdup(string);
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSetTextf()' - Set the value of a text node to a formatted string.
++ *
++ * The node is not changed if it (or its first child) is not a text node.
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetTextf(mxml_node_t *node, /* I - Node to set */
++ int whitespace, /* I - 1 = leading whitespace, 0 = no whitespace */
++ const char *format, /* I - Printf-style format string */
++ ...) /* I - Additional arguments as needed */
++{
++ va_list ap; /* Pointer to arguments */
++
++
++ /*
++ * Range check input...
++ */
++
++ if (node && node->type == MXML_ELEMENT &&
++ node->child && node->child->type == MXML_TEXT)
++ node = node->child;
++
++ if (!node || node->type != MXML_TEXT || !format)
++ return (-1);
++
++ /*
++ * Free any old string value and set the new value...
++ */
++
++ if (node->value.text.string)
++ free(node->value.text.string);
++
++ va_start(ap, format);
++
++ node->value.text.whitespace = whitespace;
++ node->value.text.string = _mxml_strdupf(format, ap);
++
++ va_end(ap);
++
++ return (0);
++}
++
++
++/*
++ * 'mxmlSetUserData()' - Set the user data pointer for a node.
++ *
++ * @since Mini-XML 2.7@
++ */
++
++int /* O - 0 on success, -1 on failure */
++mxmlSetUserData(mxml_node_t *node, /* I - Node to set */
++ void *data) /* I - User data pointer */
++{
++ /*
++ * Range check input...
++ */
++
++ if (!node)
++ return (-1);
++
++ /*
++ * Set the user data pointer and return...
++ */
++
++ node->user_data = data;
++ return (0);
++}
++
++
++/*
++ * End of "$Id: mxml-set.c 441 2011-12-09 23:49:00Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-string.c linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-string.c
+--- linux-3.10.30.orig/tools/gator/daemon/mxml/mxml-string.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/mxml/mxml-string.c 2014-05-15 20:34:24.450204395 +0200
+@@ -0,0 +1,476 @@
++/*
++ * "$Id: mxml-string.c 424 2010-12-25 16:21:50Z mike $"
++ *
++ * String functions for Mini-XML, a small XML-like file parsing library.
++ *
++ * Copyright 2003-2010 by Michael R Sweet.
++ *
++ * These coded instructions, statements, and computer programs are the
++ * property of Michael R Sweet and are protected by Federal copyright
++ * law. Distribution and use rights are outlined in the file "COPYING"
++ * which should have been included with this file. If this file is
++ * missing or damaged, see the license at:
++ *
++ * http://www.minixml.org/
++ *
++ * Contents:
++ *
++ * _mxml_snprintf() - Format a string.
++ * _mxml_strdup() - Duplicate a string.
++ * _mxml_strdupf() - Format and duplicate a string.
++ * _mxml_vsnprintf() - Format a string into a fixed size buffer.
++ * _mxml_vstrdupf() - Format and duplicate a string.
++ */
++
++/*
++ * Include necessary headers...
++ */
++
++#include "config.h"
++
++
++/*
++ * The va_copy macro is part of C99, but many compilers don't implement it.
++ * Provide a "direct assignment" implmentation when va_copy isn't defined...
++ */
++
++#ifndef va_copy
++# ifdef __va_copy
++# define va_copy(dst,src) __va_copy(dst,src)
++# else
++# define va_copy(dst,src) memcpy(&dst, &src, sizeof(va_list))
++# endif /* __va_copy */
++#endif /* va_copy */
++
++
++#ifndef HAVE_SNPRINTF
++/*
++ * '_mxml_snprintf()' - Format a string.
++ */
++
++int /* O - Number of bytes formatted */
++_mxml_snprintf(char *buffer, /* I - Output buffer */
++ size_t bufsize, /* I - Size of output buffer */
++ const char *format, /* I - Printf-style format string */
++ ...) /* I - Additional arguments as needed */
++{
++ va_list ap; /* Argument list */
++ int bytes; /* Number of bytes formatted */
++
++
++ va_start(ap, format);
++ bytes = vsnprintf(buffer, bufsize, format, ap);
++ va_end(ap);
++
++ return (bytes);
++}
++#endif /* !HAVE_SNPRINTF */
++
++
++/*
++ * '_mxml_strdup()' - Duplicate a string.
++ */
++
++#ifndef HAVE_STRDUP
++char * /* O - New string pointer */
++_mxml_strdup(const char *s) /* I - String to duplicate */
++{
++ char *t; /* New string pointer */
++
++
++ if (s == NULL)
++ return (NULL);
++
++ if ((t = malloc(strlen(s) + 1)) == NULL)
++ return (NULL);
++
++ return (strcpy(t, s));
++}
++#endif /* !HAVE_STRDUP */
++
++
++/*
++ * '_mxml_strdupf()' - Format and duplicate a string.
++ */
++
++char * /* O - New string pointer */
++_mxml_strdupf(const char *format, /* I - Printf-style format string */
++ ...) /* I - Additional arguments as needed */
++{
++ va_list ap; /* Pointer to additional arguments */
++ char *s; /* Pointer to formatted string */
++
++
++ /*
++ * Get a pointer to the additional arguments, format the string,
++ * and return it...
++ */
++
++ va_start(ap, format);
++ s = _mxml_vstrdupf(format, ap);
++ va_end(ap);
++
++ return (s);
++}
++
++
++#ifndef HAVE_VSNPRINTF
++/*
++ * '_mxml_vsnprintf()' - Format a string into a fixed size buffer.
++ */
++
++int /* O - Number of bytes formatted */
++_mxml_vsnprintf(char *buffer, /* O - Output buffer */
++ size_t bufsize, /* O - Size of output buffer */
++ const char *format, /* I - Printf-style format string */
++ va_list ap) /* I - Pointer to additional arguments */
++{
++ char *bufptr, /* Pointer to position in buffer */
++ *bufend, /* Pointer to end of buffer */
++ sign, /* Sign of format width */
++ size, /* Size character (h, l, L) */
++ type; /* Format type character */
++ int width, /* Width of field */
++ prec; /* Number of characters of precision */
++ char tformat[100], /* Temporary format string for sprintf() */
++ *tptr, /* Pointer into temporary format */
++ temp[1024]; /* Buffer for formatted numbers */
++ char *s; /* Pointer to string */
++ int slen; /* Length of string */
++ int bytes; /* Total number of bytes needed */
++
++
++ /*
++ * Loop through the format string, formatting as needed...
++ */
++
++ bufptr = buffer;
++ bufend = buffer + bufsize - 1;
++ bytes = 0;
++
++ while (*format)
++ {
++ if (*format == '%')
++ {
++ tptr = tformat;
++ *tptr++ = *format++;
++
++ if (*format == '%')
++ {
++ if (bufptr && bufptr < bufend) *bufptr++ = *format;
++ bytes ++;
++ format ++;
++ continue;
++ }
++ else if (strchr(" -+#\'", *format))
++ {
++ *tptr++ = *format;
++ sign = *format++;
++ }
++ else
++ sign = 0;
++
++ if (*format == '*')
++ {
++ /*
++ * Get width from argument...
++ */
++
++ format ++;
++ width = va_arg(ap, int);
++
++ snprintf(tptr, sizeof(tformat) - (tptr - tformat), "%d", width);
++ tptr += strlen(tptr);
++ }
++ else
++ {
++ width = 0;
++
++ while (isdigit(*format & 255))
++ {
++ if (tptr < (tformat + sizeof(tformat) - 1))
++ *tptr++ = *format;
++
++ width = width * 10 + *format++ - '0';
++ }
++ }
++
++ if (*format == '.')
++ {
++ if (tptr < (tformat + sizeof(tformat) - 1))
++ *tptr++ = *format;
++
++ format ++;
++
++ if (*format == '*')
++ {
++ /*
++ * Get precision from argument...
++ */
++
++ format ++;
++ prec = va_arg(ap, int);
++
++ snprintf(tptr, sizeof(tformat) - (tptr - tformat), "%d", prec);
++ tptr += strlen(tptr);
++ }
++ else
++ {
++ prec = 0;
++
++ while (isdigit(*format & 255))
++ {
++ if (tptr < (tformat + sizeof(tformat) - 1))
++ *tptr++ = *format;
++
++ prec = prec * 10 + *format++ - '0';
++ }
++ }
++ }
++ else
++ prec = -1;
++
++ if (*format == 'l' && format[1] == 'l')
++ {
++ size = 'L';
++
++ if (tptr < (tformat + sizeof(tformat) - 2))
++ {
++ *tptr++ = 'l';
++ *tptr++ = 'l';
++ }
++
++ format += 2;
++ }
++ else if (*format == 'h' || *format == 'l' || *format == 'L')
++ {
++ if (tptr < (tformat + sizeof(tformat) - 1))
++ *tptr++ = *format;
++
++ size = *format++;
++ }
++
++ if (!*format)
++ break;
++
++ if (tptr < (tformat + sizeof(tformat) - 1))
++ *tptr++ = *format;
++
++ type = *format++;
++ *tptr = '\0';
++
++ switch (type)
++ {
++ case 'E' : /* Floating point formats */
++ case 'G' :
++ case 'e' :
++ case 'f' :
++ case 'g' :
++ if ((width + 2) > sizeof(temp))
++ break;
++
++ sprintf(temp, tformat, va_arg(ap, double));
++
++ bytes += strlen(temp);
++
++ if (bufptr)
++ {
++ if ((bufptr + strlen(temp)) > bufend)
++ {
++ strncpy(bufptr, temp, (size_t)(bufend - bufptr));
++ bufptr = bufend;
++ }
++ else
++ {
++ strcpy(bufptr, temp);
++ bufptr += strlen(temp);
++ }
++ }
++ break;
++
++ case 'B' : /* Integer formats */
++ case 'X' :
++ case 'b' :
++ case 'd' :
++ case 'i' :
++ case 'o' :
++ case 'u' :
++ case 'x' :
++ if ((width + 2) > sizeof(temp))
++ break;
++
++#ifdef HAVE_LONG_LONG
++ if (size == 'L')
++ sprintf(temp, tformat, va_arg(ap, long long));
++ else
++#endif /* HAVE_LONG_LONG */
++ sprintf(temp, tformat, va_arg(ap, int));
++
++ bytes += strlen(temp);
++
++ if (bufptr)
++ {
++ if ((bufptr + strlen(temp)) > bufend)
++ {
++ strncpy(bufptr, temp, (size_t)(bufend - bufptr));
++ bufptr = bufend;
++ }
++ else
++ {
++ strcpy(bufptr, temp);
++ bufptr += strlen(temp);
++ }
++ }
++ break;
++
++ case 'p' : /* Pointer value */
++ if ((width + 2) > sizeof(temp))
++ break;
++
++ sprintf(temp, tformat, va_arg(ap, void *));
++
++ bytes += strlen(temp);
++
++ if (bufptr)
++ {
++ if ((bufptr + strlen(temp)) > bufend)
++ {
++ strncpy(bufptr, temp, (size_t)(bufend - bufptr));
++ bufptr = bufend;
++ }
++ else
++ {
++ strcpy(bufptr, temp);
++ bufptr += strlen(temp);
++ }
++ }
++ break;
++
++ case 'c' : /* Character or character array */
++ bytes += width;
++
++ if (bufptr)
++ {
++ if (width <= 1)
++ *bufptr++ = va_arg(ap, int);
++ else
++ {
++ if ((bufptr + width) > bufend)
++ width = bufend - bufptr;
++
++ memcpy(bufptr, va_arg(ap, char *), (size_t)width);
++ bufptr += width;
++ }
++ }
++ break;
++
++ case 's' : /* String */
++ if ((s = va_arg(ap, char *)) == NULL)
++ s = "(null)";
++
++ slen = strlen(s);
++ if (slen > width && prec != width)
++ width = slen;
++
++ bytes += width;
++
++ if (bufptr)
++ {
++ if ((bufptr + width) > bufend)
++ width = bufend - bufptr;
++
++ if (slen > width)
++ slen = width;
++
++ if (sign == '-')
++ {
++ strncpy(bufptr, s, (size_t)slen);
++ memset(bufptr + slen, ' ', (size_t)(width - slen));
++ }
++ else
++ {
++ memset(bufptr, ' ', (size_t)(width - slen));
++ strncpy(bufptr + width - slen, s, (size_t)slen);
++ }
++
++ bufptr += width;
++ }
++ break;
++
++ case 'n' : /* Output number of chars so far */
++ *(va_arg(ap, int *)) = bytes;
++ break;
++ }
++ }
++ else
++ {
++ bytes ++;
++
++ if (bufptr && bufptr < bufend)
++ *bufptr++ = *format;
++
++ format ++;
++ }
++ }
++
++ /*
++ * Nul-terminate the string and return the number of characters needed.
++ */
++
++ *bufptr = '\0';
++
++ return (bytes);
++}
++#endif /* !HAVE_VSNPRINTF */
++
++
++/*
++ * '_mxml_vstrdupf()' - Format and duplicate a string.
++ */
++
++char * /* O - New string pointer */
++_mxml_vstrdupf(const char *format, /* I - Printf-style format string */
++ va_list ap) /* I - Pointer to additional arguments */
++{
++ int bytes; /* Number of bytes required */
++ char *buffer, /* String buffer */
++ temp[256]; /* Small buffer for first vsnprintf */
++ va_list apcopy; /* Copy of argument list */
++
++
++ /*
++ * First format with a tiny buffer; this will tell us how many bytes are
++ * needed...
++ */
++
++ va_copy(apcopy, ap);
++ bytes = vsnprintf(temp, sizeof(temp), format, apcopy);
++
++ if (bytes < sizeof(temp))
++ {
++ /*
++ * Hey, the formatted string fits in the tiny buffer, so just dup that...
++ */
++
++ return (strdup(temp));
++ }
++
++ /*
++ * Allocate memory for the whole thing and reformat to the new, larger
++ * buffer...
++ */
++
++ if ((buffer = calloc(1, bytes + 1)) != NULL)
++ vsnprintf(buffer, bytes + 1, format, ap);
++
++ /*
++ * Return the new string...
++ */
++
++ return (buffer);
++}
++
++
++/*
++ * End of "$Id: mxml-string.c 424 2010-12-25 16:21:50Z mike $".
++ */
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/OlySocket.cpp linux-linaro-stable-mx6/tools/gator/daemon/OlySocket.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/OlySocket.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/OlySocket.cpp 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,268 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "OlySocket.h"
++
++#include <stdio.h>
++#ifdef WIN32
++#include <Winsock2.h>
++#include <ws2tcpip.h>
++#else
++#include <netinet/in.h>
++#include <sys/socket.h>
++#include <unistd.h>
++#include <netdb.h>
++#endif
++
++#include "Logging.h"
++
++#ifdef WIN32
++#define CLOSE_SOCKET(x) closesocket(x)
++#define SHUTDOWN_RX_TX SD_BOTH
++#define snprintf _snprintf
++#else
++#define CLOSE_SOCKET(x) close(x)
++#define SHUTDOWN_RX_TX SHUT_RDWR
++#endif
++
++OlySocket::OlySocket(int port, bool multiple) {
++#ifdef WIN32
++ WSADATA wsaData;
++ if (WSAStartup(0x0202, &wsaData) != 0) {
++ logg->logError(__FILE__, __LINE__, "Windows socket initialization failed");
++ handleException();
++ }
++#endif
++
++ if (multiple) {
++ createServerSocket(port);
++ } else {
++ createSingleServerConnection(port);
++ }
++}
++
++OlySocket::OlySocket(int port, char* host) {
++ mFDServer = 0;
++ createClientSocket(host, port);
++}
++
++OlySocket::~OlySocket() {
++ if (mSocketID > 0) {
++ CLOSE_SOCKET(mSocketID);
++ }
++}
++
++void OlySocket::shutdownConnection() {
++ // Shutdown is primarily used to unblock other threads that are blocking on send/receive functions
++ shutdown(mSocketID, SHUTDOWN_RX_TX);
++}
++
++void OlySocket::closeSocket() {
++ // Used for closing an accepted socket but keeping the server socket active
++ if (mSocketID > 0) {
++ CLOSE_SOCKET(mSocketID);
++ mSocketID = -1;
++ }
++}
++
++void OlySocket::closeServerSocket() {
++ if (CLOSE_SOCKET(mFDServer) != 0) {
++ logg->logError(__FILE__, __LINE__, "Failed to close server socket.");
++ handleException();
++ }
++ mFDServer = 0;
++}
++
++void OlySocket::createClientSocket(char* hostname, int portno) {
++#ifdef WIN32
++ // TODO: Implement for Windows
++#else
++ char buf[32];
++ struct addrinfo hints, *res, *res0;
++
++ snprintf(buf, sizeof(buf), "%d", portno);
++ mSocketID = -1;
++ memset((void*)&hints, 0, sizeof(hints));
++ hints.ai_family = PF_UNSPEC;
++ hints.ai_socktype = SOCK_STREAM;
++
++ if (getaddrinfo(hostname, buf, &hints, &res0)) {
++ logg->logError(__FILE__, __LINE__, "Client socket failed to get address info for %s", hostname);
++ handleException();
++ }
++ for (res=res0; res!=NULL; res = res->ai_next) {
++ if ( res->ai_family != PF_INET || res->ai_socktype != SOCK_STREAM ) {
++ continue;
++ }
++ mSocketID = socket(res->ai_family, res->ai_socktype, res->ai_protocol);
++ if (mSocketID < 0) {
++ continue;
++ }
++ if (connect(mSocketID, res->ai_addr, res->ai_addrlen) < 0) {
++ close(mSocketID);
++ mSocketID = -1;
++ }
++ if (mSocketID > 0) {
++ break;
++ }
++ }
++ freeaddrinfo(res0);
++ if (mSocketID <= 0) {
++ logg->logError(__FILE__, __LINE__, "Could not connect to client socket. Ensure ARM Streamline is running.");
++ handleException();
++ }
++#endif
++}
++
++void OlySocket::createSingleServerConnection(int port) {
++ createServerSocket(port);
++
++ mSocketID = acceptConnection();
++ closeServerSocket();
++}
++
++void OlySocket::createServerSocket(int port) {
++ int family = AF_INET6;
++
++ // Create socket
++ mFDServer = socket(PF_INET6, SOCK_STREAM, IPPROTO_TCP);
++ if (mFDServer < 0) {
++ family = AF_INET;
++ mFDServer = socket(PF_INET, SOCK_STREAM, IPPROTO_TCP);
++ if (mFDServer < 0) {
++ logg->logError(__FILE__, __LINE__, "Error creating server socket");
++ handleException();
++ }
++ }
++
++ // Enable address reuse, another solution would be to create the server socket once and only close it when the object exits
++ int on = 1;
++ if (setsockopt(mFDServer, SOL_SOCKET, SO_REUSEADDR, (const char*)&on, sizeof(on)) != 0) {
++ logg->logError(__FILE__, __LINE__, "Setting server socket options failed");
++ handleException();
++ }
++
++ // Create sockaddr_in structure, ensuring non-populated fields are zero
++ struct sockaddr_in6 sockaddr;
++ memset((void*)&sockaddr, 0, sizeof(sockaddr));
++ sockaddr.sin6_family = family;
++ sockaddr.sin6_port = htons(port);
++ sockaddr.sin6_addr = in6addr_any;
++
++ // Bind the socket to an address
++ if (bind(mFDServer, (const struct sockaddr*)&sockaddr, sizeof(sockaddr)) < 0) {
++ logg->logError(__FILE__, __LINE__, "Binding of server socket failed.\nIs an instance already running?");
++ handleException();
++ }
++
++ // Listen for connections on this socket
++ if (listen(mFDServer, 1) < 0) {
++ logg->logError(__FILE__, __LINE__, "Listening of server socket failed");
++ handleException();
++ }
++}
++
++// mSocketID is always set to the most recently accepted connection
++// The user of this class should maintain the different socket connections, e.g. by forking the process
++int OlySocket::acceptConnection() {
++ if (mFDServer <= 0) {
++ logg->logError(__FILE__, __LINE__, "Attempting multiple connections on a single connection server socket or attempting to accept on a client socket");
++ handleException();
++ }
++
++ // Accept a connection, note that this call blocks until a client connects
++ mSocketID = accept(mFDServer, NULL, NULL);
++ if (mSocketID < 0) {
++ logg->logError(__FILE__, __LINE__, "Socket acceptance failed");
++ handleException();
++ }
++ return mSocketID;
++}
++
++void OlySocket::send(char* buffer, int size) {
++ if (size <= 0 || buffer == NULL) {
++ return;
++ }
++
++ while (size > 0) {
++ int n = ::send(mSocketID, buffer, size, 0);
++ if (n < 0) {
++ logg->logError(__FILE__, __LINE__, "Socket send error");
++ handleException();
++ }
++ size -= n;
++ buffer += n;
++ }
++}
++
++// Returns the number of bytes received
++int OlySocket::receive(char* buffer, int size) {
++ if (size <= 0 || buffer == NULL) {
++ return 0;
++ }
++
++ int bytes = recv(mSocketID, buffer, size, 0);
++ if (bytes < 0) {
++ logg->logError(__FILE__, __LINE__, "Socket receive error");
++ handleException();
++ } else if (bytes == 0) {
++ logg->logMessage("Socket disconnected");
++ return -1;
++ }
++ return bytes;
++}
++
++// Receive exactly size bytes of data. Note, this function will block until all bytes are received
++int OlySocket::receiveNBytes(char* buffer, int size) {
++ int bytes = 0;
++ while (size > 0 && buffer != NULL) {
++ bytes = recv(mSocketID, buffer, size, 0);
++ if (bytes < 0) {
++ logg->logError(__FILE__, __LINE__, "Socket receive error");
++ handleException();
++ } else if (bytes == 0) {
++ logg->logMessage("Socket disconnected");
++ return -1;
++ }
++ buffer += bytes;
++ size -= bytes;
++ }
++ return bytes;
++}
++
++// Receive data until a carriage return, line feed, or null is encountered, or the buffer fills
++int OlySocket::receiveString(char* buffer, int size) {
++ int bytes_received = 0;
++ bool found = false;
++
++ if (buffer == 0) {
++ return 0;
++ }
++
++ while (!found && bytes_received < size) {
++ // Receive a single character
++ int bytes = recv(mSocketID, &buffer[bytes_received], 1, 0);
++ if (bytes < 0) {
++ logg->logError(__FILE__, __LINE__, "Socket receive error");
++ handleException();
++ } else if (bytes == 0) {
++ logg->logMessage("Socket disconnected");
++ return -1;
++ }
++
++ // Replace carriage returns and line feeds with zero
++ if (buffer[bytes_received] == '\n' || buffer[bytes_received] == '\r' || buffer[bytes_received] == '\0') {
++ buffer[bytes_received] = '\0';
++ found = true;
++ }
++
++ bytes_received++;
++ }
++
++ return bytes_received;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/OlySocket.h linux-linaro-stable-mx6/tools/gator/daemon/OlySocket.h
+--- linux-3.10.30.orig/tools/gator/daemon/OlySocket.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/OlySocket.h 2014-05-15 20:34:24.394203992 +0200
+@@ -0,0 +1,36 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __OLY_SOCKET_H__
++#define __OLY_SOCKET_H__
++
++#include <string.h>
++
++class OlySocket {
++public:
++ OlySocket(int port, bool multipleConnections = false);
++ OlySocket(int port, char* hostname);
++ ~OlySocket();
++ int acceptConnection();
++ void closeSocket();
++ void closeServerSocket();
++ void shutdownConnection();
++ void send(char* buffer, int size);
++ void sendString(const char* string) {send((char*)string, strlen(string));}
++ int receive(char* buffer, int size);
++ int receiveNBytes(char* buffer, int size);
++ int receiveString(char* buffer, int size);
++ int getSocketID() {return mSocketID;}
++private:
++ int mSocketID, mFDServer;
++ void createClientSocket(char* hostname, int port);
++ void createSingleServerConnection(int port);
++ void createServerSocket(int port);
++};
++
++#endif //__OLY_SOCKET_H__
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/OlyUtility.cpp linux-linaro-stable-mx6/tools/gator/daemon/OlyUtility.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/OlyUtility.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/OlyUtility.cpp 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,227 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "OlyUtility.h"
++
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++#include <ctype.h>
++
++#if defined(WIN32)
++#include <windows.h>
++#elif defined(__linux__)
++#include <unistd.h>
++#elif defined(DARWIN)
++#include <mach-o/dyld.h>
++#endif
++
++OlyUtility* util = NULL;
++
++bool OlyUtility::stringToBool(const char* string, bool defValue) {
++ char value[32];
++
++ if (string == NULL) {
++ return defValue;
++ }
++
++ strncpy(value, string, sizeof(value));
++ if (value[0] == 0) {
++ return defValue;
++ }
++ value[sizeof(value) - 1] = 0; // strncpy does not guarantee a null-terminated string
++
++ // Convert to lowercase
++ int i = 0;
++ while (value[i]) {
++ value[i] = tolower(value[i]);
++ i++;
++ }
++
++ if (strcmp(value, "true") == 0 || strcmp(value, "yes") == 0 || strcmp(value, "1") == 0 || strcmp(value, "on") == 0) {
++ return true;
++ } else if (strcmp(value, "false") == 0 || strcmp(value, "no") == 0 || strcmp(value, "0") == 0 || strcmp(value, "off") == 0) {
++ return false;
++ } else {
++ return defValue;
++ }
++}
++
++void OlyUtility::stringToLower(char* string) {
++ if (string == NULL) {
++ return;
++ }
++
++ while (*string) {
++ *string = tolower(*string);
++ string++;
++ }
++}
++
++// Modifies fullpath with the path part including the trailing path separator
++int OlyUtility::getApplicationFullPath(char* fullpath, int sizeOfPath) {
++ memset(fullpath, 0, sizeOfPath);
++#if defined(WIN32)
++ int length = GetModuleFileName(NULL, fullpath, sizeOfPath);
++#elif defined(__linux__)
++ int length = readlink("/proc/self/exe", fullpath, sizeOfPath);
++#elif defined(DARWIN)
++ uint32_t length_u = (uint32_t)sizeOfPath;
++ int length = sizeOfPath;
++ if (_NSGetExecutablePath(fullpath, &length_u) == 0) {
++ length = strlen(fullpath);
++ }
++#endif
++
++ if (length == sizeOfPath) {
++ return -1;
++ }
++
++ fullpath[length] = 0;
++ getPathPart(fullpath);
++
++ return 0;
++}
++
++char* OlyUtility::readFromDisk(const char* file, unsigned int *size, bool appendNull) {
++ // Open the file
++ FILE* pFile = fopen(file, "rb");
++ if (pFile==NULL) {
++ return NULL;
++ }
++
++ // Obtain file size
++ fseek(pFile , 0 , SEEK_END);
++ unsigned int lSize = ftell(pFile);
++ rewind(pFile);
++
++ // Allocate memory to contain the whole file
++ char* buffer = (char*)malloc(lSize + (int)appendNull);
++ if (buffer == NULL) {
++ fclose(pFile);
++ return NULL;
++ }
++
++ // Copy the file into the buffer
++ if (fread(buffer, 1, lSize, pFile) != lSize) {
++ free(buffer);
++ fclose(pFile);
++ return NULL;
++ }
++
++ // Terminate
++ fclose(pFile);
++
++ if (appendNull) {
++ buffer[lSize] = 0;
++ }
++
++ if (size) {
++ *size = lSize;
++ }
++
++ return buffer;
++}
++
++int OlyUtility::writeToDisk(const char* path, const char* data) {
++ // Open the file
++ FILE* pFile = fopen(path, "wb");
++ if (pFile == NULL) {
++ return -1;
++ }
++
++ // Write the data to disk
++ if (fwrite(data, 1, strlen(data), pFile) != strlen(data)) {
++ fclose(pFile);
++ return -1;
++ }
++
++ // Terminate
++ fclose(pFile);
++ return 0;
++}
++
++int OlyUtility::appendToDisk(const char* path, const char* data) {
++ // Open the file
++ FILE* pFile = fopen(path, "a");
++ if (pFile == NULL) {
++ return -1;
++ }
++
++ // Write the data to disk
++ if (fwrite(data, 1, strlen(data), pFile) != strlen(data)) {
++ fclose(pFile);
++ return -1;
++ }
++
++ // Terminate
++ fclose(pFile);
++ return 0;
++}
++
++/**
++ * Copies the srcFile into dstFile in 1kB chunks.
++ * The dstFile will be overwritten if it exists.
++ * 0 is returned on an error; otherwise 1.
++ */
++#define TRANSFER_SIZE 1024
++int OlyUtility::copyFile(const char* srcFile, const char* dstFile) {
++ char buffer[TRANSFER_SIZE];
++ FILE * f_src = fopen(srcFile,"rb");
++ if (!f_src) {
++ return 0;
++ }
++ FILE * f_dst = fopen(dstFile,"wb");
++ if (!f_dst) {
++ fclose(f_src);
++ return 0;
++ }
++ while (!feof(f_src)) {
++ int num_bytes_read = fread(buffer, 1, TRANSFER_SIZE, f_src);
++ if (num_bytes_read < TRANSFER_SIZE && !feof(f_src)) {
++ fclose(f_src);
++ fclose(f_dst);
++ return 0;
++ }
++ int num_bytes_written = fwrite(buffer, 1, num_bytes_read, f_dst);
++ if (num_bytes_written != num_bytes_read) {
++ fclose(f_src);
++ fclose(f_dst);
++ return 0;
++ }
++ }
++ fclose(f_src);
++ fclose(f_dst);
++ return 1;
++}
++
++const char* OlyUtility::getFilePart(const char* path) {
++ const char* last_sep = strrchr(path, PATH_SEPARATOR);
++
++ // in case path is not a full path
++ if (last_sep == NULL) {
++ return path;
++ }
++
++ return last_sep++;
++}
++
++// getPathPart may modify the contents of path
++// returns the path including the trailing path separator
++char* OlyUtility::getPathPart(char* path) {
++ char* last_sep = strrchr(path, PATH_SEPARATOR);
++
++ // in case path is not a full path
++ if (last_sep == NULL) {
++ return 0;
++ }
++ last_sep++;
++ *last_sep = 0;
++
++ return (path);
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/OlyUtility.h linux-linaro-stable-mx6/tools/gator/daemon/OlyUtility.h
+--- linux-3.10.30.orig/tools/gator/daemon/OlyUtility.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/OlyUtility.h 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,42 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef OLY_UTILITY_H
++#define OLY_UTILITY_H
++
++#include <stddef.h>
++
++#ifdef WIN32
++#define PATH_SEPARATOR '\\'
++#define CAIMAN_PATH_MAX MAX_PATH
++#define snprintf _snprintf
++#else
++#include <limits.h>
++#define PATH_SEPARATOR '/'
++#define CAIMAN_PATH_MAX PATH_MAX
++#endif
++
++class OlyUtility {
++public:
++ OlyUtility() {};
++ ~OlyUtility() {};
++ bool stringToBool(const char* string, bool defValue);
++ void stringToLower(char* string);
++ int getApplicationFullPath(char* path, int sizeOfPath);
++ char* readFromDisk(const char* file, unsigned int *size = NULL, bool appendNull = true);
++ int writeToDisk(const char* path, const char* file);
++ int appendToDisk(const char* path, const char* file);
++ int copyFile(const char* srcFile, const char* dstFile);
++ const char* getFilePart(const char* path);
++ char* getPathPart(char* path);
++private:
++};
++
++extern OlyUtility* util;
++
++#endif // OLY_UTILITY_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Sender.cpp linux-linaro-stable-mx6/tools/gator/daemon/Sender.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/Sender.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Sender.cpp 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,135 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <string.h>
++#include <sys/socket.h>
++#include <netinet/in.h>
++#include <sys/types.h>
++#include <arpa/inet.h>
++#include <stdlib.h>
++#include <unistd.h>
++#include "Sender.h"
++#include "Logging.h"
++#include "OlySocket.h"
++#include "SessionData.h"
++
++Sender::Sender(OlySocket* socket) {
++ mDataFile = NULL;
++ mDataSocket = NULL;
++
++ // Set up the socket connection
++ if (socket) {
++ char streamline[64] = {0};
++ mDataSocket = socket;
++
++ // Receive magic sequence - can wait forever
++ // Streamline will send data prior to the magic sequence for legacy support, which should be ignored for v4+
++ while (strcmp("STREAMLINE", streamline) != 0) {
++ if (mDataSocket->receiveString(streamline, sizeof(streamline)) == -1) {
++ logg->logError(__FILE__, __LINE__, "Socket disconnected");
++ handleException();
++ }
++ }
++
++ // Send magic sequence - must be done first, after which error messages can be sent
++ char magic[32];
++ snprintf(magic, 32, "GATOR %i\n", PROTOCOL_VERSION);
++ mDataSocket->send(magic, strlen(magic));
++
++ gSessionData->mWaitingOnCommand = true;
++ logg->logMessage("Completed magic sequence");
++ }
++
++ pthread_mutex_init(&mSendMutex, NULL);
++}
++
++Sender::~Sender() {
++ delete mDataSocket;
++ mDataSocket = NULL;
++ if (mDataFile) {
++ fclose(mDataFile);
++ }
++}
++
++void Sender::createDataFile(char* apcDir) {
++ if (apcDir == NULL) {
++ return;
++ }
++
++ mDataFileName = (char*)malloc(strlen(apcDir) + 12);
++ sprintf(mDataFileName, "%s/0000000000", apcDir);
++ mDataFile = fopen(mDataFileName, "wb");
++ if (!mDataFile) {
++ logg->logError(__FILE__, __LINE__, "Failed to open binary file: %s", mDataFileName);
++ handleException();
++ }
++}
++
++template<typename T>
++inline T min(const T a, const T b) {
++ return (a < b ? a : b);
++}
++
++void Sender::writeData(const char* data, int length, int type) {
++ if (length < 0 || (data == NULL && length > 0)) {
++ return;
++ }
++
++ // Multiple threads call writeData()
++ pthread_mutex_lock(&mSendMutex);
++
++ // Send data over the socket connection
++ if (mDataSocket) {
++ // Start alarm
++ const int alarmDuration = 8;
++ alarm(alarmDuration);
++
++ // Send data over the socket, sending the type and size first
++ logg->logMessage("Sending data with length %d", length);
++ if (type != RESPONSE_APC_DATA) {
++ // type and length already added by the Collector for apc data
++ unsigned char header[5];
++ header[0] = type;
++ header[1] = (length >> 0) & 0xff;
++ header[2] = (length >> 8) & 0xff;
++ header[3] = (length >> 16) & 0xff;
++ header[4] = (length >> 24) & 0xff;
++ mDataSocket->send((char*)&header, sizeof(header));
++ }
++
++ // 100Kbits/sec * alarmDuration sec / 8 bits/byte
++ const int chunkSize = 100*1000 * alarmDuration / 8;
++ int pos = 0;
++ while (true) {
++ mDataSocket->send((char*)data + pos, min(length - pos, chunkSize));
++ pos += chunkSize;
++ if (pos >= length) {
++ break;
++ }
++
++ // Reset the alarm
++ alarm(alarmDuration);
++ logg->logMessage("Resetting the alarm");
++ }
++
++ // Stop alarm
++ alarm(0);
++ }
++
++ // Write data to disk as long as it is not meta data
++ if (mDataFile && type == RESPONSE_APC_DATA) {
++ logg->logMessage("Writing data with length %d", length);
++ // Send data to the data file
++ if (fwrite(data, 1, length, mDataFile) != (unsigned int)length) {
++ logg->logError(__FILE__, __LINE__, "Failed writing binary file %s", mDataFileName);
++ handleException();
++ }
++ }
++
++ pthread_mutex_unlock(&mSendMutex);
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/Sender.h linux-linaro-stable-mx6/tools/gator/daemon/Sender.h
+--- linux-3.10.30.orig/tools/gator/daemon/Sender.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/Sender.h 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,42 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __SENDER_H__
++#define __SENDER_H__
++
++#include <stdio.h>
++#include <pthread.h>
++
++class OlySocket;
++
++enum {
++ RESPONSE_XML = 1,
++ RESPONSE_APC_DATA = 3,
++ RESPONSE_ACK = 4,
++ RESPONSE_NAK = 5,
++ RESPONSE_ERROR = 0xFF
++};
++
++class Sender {
++public:
++ Sender(OlySocket* socket);
++ ~Sender();
++ void writeData(const char* data, int length, int type);
++ void createDataFile(char* apcDir);
++private:
++ OlySocket* mDataSocket;
++ FILE* mDataFile;
++ char* mDataFileName;
++ pthread_mutex_t mSendMutex;
++
++ // Intentionally unimplemented
++ Sender(const Sender &);
++ Sender &operator=(const Sender &);
++};
++
++#endif //__SENDER_H__
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/SessionData.cpp linux-linaro-stable-mx6/tools/gator/daemon/SessionData.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/SessionData.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/SessionData.cpp 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,150 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <string.h>
++#include "SessionData.h"
++#include "SessionXML.h"
++#include "Logging.h"
++
++SessionData* gSessionData = NULL;
++
++SessionData::SessionData() {
++ initialize();
++}
++
++SessionData::~SessionData() {
++}
++
++void SessionData::initialize() {
++ mWaitingOnCommand = false;
++ mSessionIsActive = false;
++ mLocalCapture = false;
++ mOneShot = false;
++ readCpuInfo();
++ mConfigurationXMLPath = NULL;
++ mSessionXMLPath = NULL;
++ mEventsXMLPath = NULL;
++ mTargetPath = NULL;
++ mAPCDir = NULL;
++ mSampleRate = 0;
++ mLiveRate = 0;
++ mDuration = 0;
++ mBacktraceDepth = 0;
++ mTotalBufferSize = 0;
++ // sysconf(_SC_NPROCESSORS_CONF) is unreliable on 2.6 Android, get the value from the kernel module
++ mCores = 1;
++}
++
++void SessionData::parseSessionXML(char* xmlString) {
++ SessionXML session(xmlString);
++ session.parse();
++
++ // Set session data values - use prime numbers just below the desired value to reduce the chance of events firing at the same time
++ if (strcmp(session.parameters.sample_rate, "high") == 0) {
++ mSampleRate = 9973; // 10000
++ } else if (strcmp(session.parameters.sample_rate, "normal") == 0) {
++ mSampleRate = 997; // 1000
++ } else if (strcmp(session.parameters.sample_rate, "low") == 0) {
++ mSampleRate = 97; // 100
++ } else if (strcmp(session.parameters.sample_rate, "none") == 0) {
++ mSampleRate = 0;
++ } else {
++ logg->logError(__FILE__, __LINE__, "Invalid sample rate (%s) in session xml.", session.parameters.sample_rate);
++ handleException();
++ }
++ mBacktraceDepth = session.parameters.call_stack_unwinding == true ? 128 : 0;
++ mDuration = session.parameters.duration;
++
++ // Determine buffer size (in MB) based on buffer mode
++ mOneShot = true;
++ if (strcmp(session.parameters.buffer_mode, "streaming") == 0) {
++ mOneShot = false;
++ mTotalBufferSize = 1;
++ } else if (strcmp(session.parameters.buffer_mode, "small") == 0) {
++ mTotalBufferSize = 1;
++ } else if (strcmp(session.parameters.buffer_mode, "normal") == 0) {
++ mTotalBufferSize = 4;
++ } else if (strcmp(session.parameters.buffer_mode, "large") == 0) {
++ mTotalBufferSize = 16;
++ } else {
++ logg->logError(__FILE__, __LINE__, "Invalid value for buffer mode in session xml.");
++ handleException();
++ }
++
++ mImages = session.parameters.images;
++ // Convert milli- to nanoseconds
++ mLiveRate = session.parameters.live_rate * (int64_t)1000000;
++ if (mLiveRate > 0 && mLocalCapture) {
++ logg->logMessage("Local capture is not compatable with live, disabling live");
++ mLiveRate = 0;
++ }
++}
++
++void SessionData::readCpuInfo() {
++ char temp[256]; // arbitrarily large amount
++ strcpy(mCoreName, "unknown");
++ mCpuId = -1;
++
++ FILE* f = fopen("/proc/cpuinfo", "r");
++ if (f == NULL) {
++ logg->logMessage("Error opening /proc/cpuinfo\n"
++ "The core name in the captured xml file will be 'unknown'.");
++ return;
++ }
++
++ bool foundCoreName = false;
++ bool foundCpuId = false;
++ while (fgets(temp, sizeof(temp), f) && (!foundCoreName || !foundCpuId)) {
++ if (strlen(temp) > 0) {
++ temp[strlen(temp) - 1] = 0; // Replace the line feed with a null
++ }
++
++ const bool foundHardware = strstr(temp, "Hardware") != 0;
++ const bool foundCPUPart = strstr(temp, "CPU part") != 0;
++ if (foundHardware || foundCPUPart) {
++ char* position = strchr(temp, ':');
++ if (position == NULL || (unsigned int)(position - temp) + 2 >= strlen(temp)) {
++ logg->logMessage("Unknown format of /proc/cpuinfo\n"
++ "The core name in the captured xml file will be 'unknown'.");
++ return;
++ }
++ position += 2;
++
++ if (foundHardware) {
++ strncpy(mCoreName, position, sizeof(mCoreName));
++ mCoreName[sizeof(mCoreName) - 1] = 0; // strncpy does not guarantee a null-terminated string
++ foundCoreName = true;
++ }
++
++ if (foundCPUPart) {
++ int cpuId = strtol(position, NULL, 16);
++ if (cpuId > mCpuId) {
++ mCpuId = cpuId;
++ }
++ foundCpuId = true;
++ }
++ }
++ }
++
++ if (!foundCoreName) {
++ logg->logMessage("Could not determine core name from /proc/cpuinfo\n"
++ "The core name in the captured xml file will be 'unknown'.");
++ }
++ fclose(f);
++ }
++
++int getEventKey() {
++ // key 0 is reserved as a timestamp
++ // key 1 is reserved as the marker for thread specific counters
++ // Odd keys are assigned by the driver, even keys by the daemon
++ static int key = 2;
++
++ const int ret = key;
++ key += 2;
++ return ret;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/SessionData.h linux-linaro-stable-mx6/tools/gator/daemon/SessionData.h
+--- linux-3.10.30.orig/tools/gator/daemon/SessionData.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/SessionData.h 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,75 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef SESSION_DATA_H
++#define SESSION_DATA_H
++
++#include <stdint.h>
++
++#include "Counter.h"
++#include "Hwmon.h"
++
++#define MAX_PERFORMANCE_COUNTERS 50
++
++#define PROTOCOL_VERSION 17
++#define PROTOCOL_DEV 1000 // Differentiates development versions (timestamp) from release versions
++
++struct ImageLinkList {
++ char* path;
++ struct ImageLinkList *next;
++};
++
++class SessionData {
++public:
++ static const size_t MAX_STRING_LEN = 80;
++
++ SessionData();
++ ~SessionData();
++ void initialize();
++ void parseSessionXML(char* xmlString);
++
++ Hwmon hwmon;
++
++ char mCoreName[MAX_STRING_LEN];
++ struct ImageLinkList *mImages;
++ char* mConfigurationXMLPath;
++ char* mSessionXMLPath;
++ char* mEventsXMLPath;
++ char* mTargetPath;
++ char* mAPCDir;
++
++ bool mWaitingOnCommand;
++ bool mSessionIsActive;
++ bool mLocalCapture;
++ bool mOneShot; // halt processing of the driver data until profiling is complete or the buffer is filled
++
++ int mBacktraceDepth;
++ int mTotalBufferSize; // number of MB to use for the entire collection buffer
++ int mSampleRate;
++ int64_t mLiveRate;
++ int mDuration;
++ int mCores;
++ int mCpuId;
++
++ // PMU Counters
++ int mCounterOverflow;
++ Counter mCounters[MAX_PERFORMANCE_COUNTERS];
++
++private:
++ void readCpuInfo();
++
++ // Intentionally unimplemented
++ SessionData(const SessionData &);
++ SessionData &operator=(const SessionData &);
++};
++
++extern SessionData* gSessionData;
++
++int getEventKey();
++
++#endif // SESSION_DATA_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/SessionXML.cpp linux-linaro-stable-mx6/tools/gator/daemon/SessionXML.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/SessionXML.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/SessionXML.cpp 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,109 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <string.h>
++#include <stdlib.h>
++#include <limits.h>
++#include "SessionXML.h"
++#include "Logging.h"
++#include "OlyUtility.h"
++#include "SessionData.h"
++
++static const char* TAG_SESSION = "session";
++static const char* TAG_IMAGE = "image";
++
++static const char* ATTR_VERSION = "version";
++static const char* ATTR_CALL_STACK_UNWINDING = "call_stack_unwinding";
++static const char* ATTR_BUFFER_MODE = "buffer_mode";
++static const char* ATTR_SAMPLE_RATE = "sample_rate";
++static const char* ATTR_DURATION = "duration";
++static const char* ATTR_PATH = "path";
++static const char* ATTR_LIVE_RATE = "live_rate";
++
++SessionXML::SessionXML(const char* str) {
++ parameters.buffer_mode[0] = 0;
++ parameters.sample_rate[0] = 0;
++ parameters.duration = 0;
++ parameters.call_stack_unwinding = false;
++ parameters.live_rate = 0;
++ parameters.images = NULL;
++ mPath = 0;
++ mSessionXML = (char*)str;
++ logg->logMessage(mSessionXML);
++}
++
++SessionXML::~SessionXML() {
++ if (mPath != 0) {
++ free(mSessionXML);
++ }
++}
++
++void SessionXML::parse() {
++ mxml_node_t *tree;
++ mxml_node_t *node;
++
++ tree = mxmlLoadString(NULL, mSessionXML, MXML_NO_CALLBACK);
++ node = mxmlFindElement(tree, tree, TAG_SESSION, NULL, NULL, MXML_DESCEND);
++
++ if (node) {
++ sessionTag(tree, node);
++ mxmlDelete(tree);
++ return;
++ }
++
++ logg->logError(__FILE__, __LINE__, "No session tag found in the session.xml file");
++ handleException();
++}
++
++void SessionXML::sessionTag(mxml_node_t *tree, mxml_node_t *node) {
++ int version = 0;
++ if (mxmlElementGetAttr(node, ATTR_VERSION)) version = strtol(mxmlElementGetAttr(node, ATTR_VERSION), NULL, 10);
++ if (version != 1) {
++ logg->logError(__FILE__, __LINE__, "Invalid session.xml version: %d", version);
++ handleException();
++ }
++
++ // copy to pre-allocated strings
++ if (mxmlElementGetAttr(node, ATTR_BUFFER_MODE)) {
++ strncpy(parameters.buffer_mode, mxmlElementGetAttr(node, ATTR_BUFFER_MODE), sizeof(parameters.buffer_mode));
++ parameters.buffer_mode[sizeof(parameters.buffer_mode) - 1] = 0; // strncpy does not guarantee a null-terminated string
++ }
++ if (mxmlElementGetAttr(node, ATTR_SAMPLE_RATE)) {
++ strncpy(parameters.sample_rate, mxmlElementGetAttr(node, ATTR_SAMPLE_RATE), sizeof(parameters.sample_rate));
++ parameters.sample_rate[sizeof(parameters.sample_rate) - 1] = 0; // strncpy does not guarantee a null-terminated string
++ }
++
++ // integers/bools
++ parameters.call_stack_unwinding = util->stringToBool(mxmlElementGetAttr(node, ATTR_CALL_STACK_UNWINDING), false);
++ if (mxmlElementGetAttr(node, ATTR_DURATION)) parameters.duration = strtol(mxmlElementGetAttr(node, ATTR_DURATION), NULL, 10);
++ if (mxmlElementGetAttr(node, ATTR_LIVE_RATE)) parameters.live_rate = strtol(mxmlElementGetAttr(node, ATTR_LIVE_RATE), NULL, 10);
++
++ // parse subtags
++ node = mxmlGetFirstChild(node);
++ while (node) {
++ if (mxmlGetType(node) != MXML_ELEMENT) {
++ node = mxmlWalkNext(node, tree, MXML_NO_DESCEND);
++ continue;
++ }
++ if (strcmp(TAG_IMAGE, mxmlGetElement(node)) == 0) {
++ sessionImage(node);
++ }
++ node = mxmlWalkNext(node, tree, MXML_NO_DESCEND);
++ }
++}
++
++void SessionXML::sessionImage(mxml_node_t *node) {
++ int length = strlen(mxmlElementGetAttr(node, ATTR_PATH));
++ struct ImageLinkList *image;
++
++ image = (struct ImageLinkList *)malloc(sizeof(struct ImageLinkList));
++ image->path = (char*)malloc(length + 1);
++ image->path = strdup(mxmlElementGetAttr(node, ATTR_PATH));
++ image->next = parameters.images;
++ parameters.images = image;
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/SessionXML.h linux-linaro-stable-mx6/tools/gator/daemon/SessionXML.h
+--- linux-3.10.30.orig/tools/gator/daemon/SessionXML.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/SessionXML.h 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,42 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef SESSION_XML_H
++#define SESSION_XML_H
++
++#include "mxml/mxml.h"
++
++struct ImageLinkList;
++
++struct ConfigParameters {
++ char buffer_mode[64]; // buffer mode, "streaming", "low", "normal", "high" defines oneshot and buffer size
++ char sample_rate[64]; // capture mode, "high", "normal", or "low"
++ int duration; // length of profile in seconds
++ bool call_stack_unwinding; // whether stack unwinding is performed
++ int live_rate;
++ struct ImageLinkList *images; // linked list of image strings
++};
++
++class SessionXML {
++public:
++ SessionXML(const char* str);
++ ~SessionXML();
++ void parse();
++ ConfigParameters parameters;
++private:
++ char* mSessionXML;
++ char* mPath;
++ void sessionTag(mxml_node_t *tree, mxml_node_t *node);
++ void sessionImage(mxml_node_t *node);
++
++ // Intentionally unimplemented
++ SessionXML(const SessionXML &);
++ SessionXML &operator=(const SessionXML &);
++};
++
++#endif // SESSION_XML_H
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/StreamlineSetup.cpp linux-linaro-stable-mx6/tools/gator/daemon/StreamlineSetup.cpp
+--- linux-3.10.30.orig/tools/gator/daemon/StreamlineSetup.cpp 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/StreamlineSetup.cpp 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,272 @@
++/**
++ * Copyright (C) ARM Limited 2011-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <string.h>
++#include <stdlib.h>
++#include <unistd.h>
++#include <arpa/inet.h>
++#include <sys/socket.h>
++#include <netinet/in.h>
++#include "Sender.h"
++#include "Logging.h"
++#include "OlyUtility.h"
++#include "SessionData.h"
++#include "CapturedXML.h"
++#include "StreamlineSetup.h"
++#include "ConfigurationXML.h"
++#include "Driver.h"
++#include "EventsXML.h"
++
++static const char* TAG_SESSION = "session";
++static const char* TAG_REQUEST = "request";
++static const char* TAG_CONFIGURATIONS = "configurations";
++
++static const char* ATTR_TYPE = "type";
++static const char* VALUE_EVENTS = "events";
++static const char* VALUE_CONFIGURATION = "configuration";
++static const char* VALUE_COUNTERS = "counters";
++static const char* VALUE_CAPTURED = "captured";
++static const char* VALUE_DEFAULTS = "defaults";
++
++StreamlineSetup::StreamlineSetup(OlySocket* s) {
++ bool ready = false;
++ char* data = NULL;
++ int type;
++
++ mSocket = s;
++
++ // Receive commands from Streamline (master)
++ while (!ready) {
++ // receive command over socket
++ gSessionData->mWaitingOnCommand = true;
++ data = readCommand(&type);
++
++ // parse and handle data
++ switch (type) {
++ case COMMAND_REQUEST_XML:
++ handleRequest(data);
++ break;
++ case COMMAND_DELIVER_XML:
++ handleDeliver(data);
++ break;
++ case COMMAND_APC_START:
++ logg->logMessage("Received apc start request");
++ ready = true;
++ break;
++ case COMMAND_APC_STOP:
++ logg->logMessage("Received apc stop request before apc start request");
++ exit(0);
++ break;
++ case COMMAND_DISCONNECT:
++ logg->logMessage("Received disconnect command");
++ exit(0);
++ break;
++ case COMMAND_PING:
++ logg->logMessage("Received ping command");
++ sendData(NULL, 0, RESPONSE_ACK);
++ break;
++ default:
++ logg->logError(__FILE__, __LINE__, "Target error: Unknown command type, %d", type);
++ handleException();
++ }
++
++ free(data);
++ }
++
++ if (gSessionData->mCounterOverflow > 0) {
++ logg->logError(__FILE__, __LINE__, "Only %i performance counters are permitted, %i are selected", MAX_PERFORMANCE_COUNTERS, gSessionData->mCounterOverflow);
++ handleException();
++ }
++}
++
++StreamlineSetup::~StreamlineSetup() {
++}
++
++char* StreamlineSetup::readCommand(int* command) {
++ unsigned char header[5];
++ char* data;
++ int response;
++
++ // receive type and length
++ response = mSocket->receiveNBytes((char*)&header, sizeof(header));
++
++ // After receiving a single byte, we are no longer waiting on a command
++ gSessionData->mWaitingOnCommand = false;
++
++ if (response < 0) {
++ logg->logError(__FILE__, __LINE__, "Target error: Unexpected socket disconnect");
++ handleException();
++ }
++
++ const char type = header[0];
++ const int length = (header[1] << 0) | (header[2] << 8) | (header[3] << 16) | (header[4] << 24);
++
++ // add artificial limit
++ if ((length < 0) || length > 1024 * 1024) {
++ logg->logError(__FILE__, __LINE__, "Target error: Invalid length received, %d", length);
++ handleException();
++ }
++
++ // allocate memory to contain the xml file, size of zero returns a zero size object
++ data = (char*)calloc(length + 1, 1);
++ if (data == NULL) {
++ logg->logError(__FILE__, __LINE__, "Unable to allocate memory for xml");
++ handleException();
++ }
++
++ // receive data
++ response = mSocket->receiveNBytes(data, length);
++ if (response < 0) {
++ logg->logError(__FILE__, __LINE__, "Target error: Unexpected socket disconnect");
++ handleException();
++ }
++
++ // null terminate the data for string parsing
++ if (length > 0) {
++ data[length] = 0;
++ }
++
++ *command = type;
++ return data;
++}
++
++void StreamlineSetup::handleRequest(char* xml) {
++ mxml_node_t *tree, *node;
++ const char * attr = NULL;
++
++ tree = mxmlLoadString(NULL, xml, MXML_NO_CALLBACK);
++ node = mxmlFindElement(tree, tree, TAG_REQUEST, ATTR_TYPE, NULL, MXML_DESCEND_FIRST);
++ if (node) {
++ attr = mxmlElementGetAttr(node, ATTR_TYPE);
++ }
++ if (attr && strcmp(attr, VALUE_EVENTS) == 0) {
++ sendEvents();
++ logg->logMessage("Sent events xml response");
++ } else if (attr && strcmp(attr, VALUE_CONFIGURATION) == 0) {
++ sendConfiguration();
++ logg->logMessage("Sent configuration xml response");
++ } else if (attr && strcmp(attr, VALUE_COUNTERS) == 0) {
++ sendCounters();
++ logg->logMessage("Sent counters xml response");
++ } else if (attr && strcmp(attr, VALUE_CAPTURED) == 0) {
++ CapturedXML capturedXML;
++ char* capturedText = capturedXML.getXML(false);
++ sendData(capturedText, strlen(capturedText), RESPONSE_XML);
++ free(capturedText);
++ logg->logMessage("Sent captured xml response");
++ } else if (attr && strcmp(attr, VALUE_DEFAULTS) == 0) {
++ sendDefaults();
++ logg->logMessage("Sent default configuration xml response");
++ } else {
++ char error[] = "Unknown request";
++ sendData(error, strlen(error), RESPONSE_NAK);
++ logg->logMessage("Received unknown request:\n%s", xml);
++ }
++
++ mxmlDelete(tree);
++}
++
++void StreamlineSetup::handleDeliver(char* xml) {
++ mxml_node_t *tree;
++
++ // Determine xml type
++ tree = mxmlLoadString(NULL, xml, MXML_NO_CALLBACK);
++ if (mxmlFindElement(tree, tree, TAG_SESSION, NULL, NULL, MXML_DESCEND_FIRST)) {
++ // Session XML
++ gSessionData->parseSessionXML(xml);
++ sendData(NULL, 0, RESPONSE_ACK);
++ logg->logMessage("Received session xml");
++ } else if (mxmlFindElement(tree, tree, TAG_CONFIGURATIONS, NULL, NULL, MXML_DESCEND_FIRST)) {
++ // Configuration XML
++ writeConfiguration(xml);
++ sendData(NULL, 0, RESPONSE_ACK);
++ logg->logMessage("Received configuration xml");
++ } else {
++ // Unknown XML
++ logg->logMessage("Received unknown XML delivery type");
++ sendData(NULL, 0, RESPONSE_NAK);
++ }
++
++ mxmlDelete(tree);
++}
++
++void StreamlineSetup::sendData(const char* data, uint32_t length, char type) {
++ unsigned char header[5];
++ header[0] = type;
++ header[1] = (length >> 0) & 0xff;
++ header[2] = (length >> 8) & 0xff;
++ header[3] = (length >> 16) & 0xff;
++ header[4] = (length >> 24) & 0xff;
++ mSocket->send((char*)&header, sizeof(header));
++ mSocket->send((char*)data, length);
++}
++
++void StreamlineSetup::sendEvents() {
++ EventsXML eventsXML;
++ char* string = eventsXML.getXML();
++ sendString(string, RESPONSE_XML);
++ free(string);
++}
++
++void StreamlineSetup::sendConfiguration() {
++ ConfigurationXML xml;
++
++ const char* string = xml.getConfigurationXML();
++ sendData(string, strlen(string), RESPONSE_XML);
++}
++
++void StreamlineSetup::sendDefaults() {
++ // Send the config built into the binary
++ const char* xml;
++ unsigned int size;
++ ConfigurationXML::getDefaultConfigurationXml(xml, size);
++
++ // Artificial size restriction
++ if (size > 1024*1024) {
++ logg->logError(__FILE__, __LINE__, "Corrupt default configuration file");
++ handleException();
++ }
++
++ sendData(xml, size, RESPONSE_XML);
++}
++
++void StreamlineSetup::sendCounters() {
++ mxml_node_t *xml;
++ mxml_node_t *counters;
++
++ xml = mxmlNewXML("1.0");
++ counters = mxmlNewElement(xml, "counters");
++ for (Driver *driver = Driver::getHead(); driver != NULL; driver = driver->getNext()) {
++ driver->writeCounters(counters);
++ }
++
++ char* string = mxmlSaveAllocString(xml, mxmlWhitespaceCB);
++ sendString(string, RESPONSE_XML);
++
++ free(string);
++ mxmlDelete(xml);
++}
++
++void StreamlineSetup::writeConfiguration(char* xml) {
++ char path[PATH_MAX];
++
++ ConfigurationXML::getPath(path);
++
++ if (util->writeToDisk(path, xml) < 0) {
++ logg->logError(__FILE__, __LINE__, "Error writing %s\nPlease verify write permissions to this path.", path);
++ handleException();
++ }
++
++ // Re-populate gSessionData with the configuration, as it has now changed
++ { ConfigurationXML configuration; }
++
++ if (gSessionData->mCounterOverflow > 0) {
++ logg->logError(__FILE__, __LINE__, "Only %i performance counters counters are permitted, %i are selected", MAX_PERFORMANCE_COUNTERS, gSessionData->mCounterOverflow);
++ handleException();
++ }
++}
+diff -Nur linux-3.10.30.orig/tools/gator/daemon/StreamlineSetup.h linux-linaro-stable-mx6/tools/gator/daemon/StreamlineSetup.h
+--- linux-3.10.30.orig/tools/gator/daemon/StreamlineSetup.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-linaro-stable-mx6/tools/gator/daemon/StreamlineSetup.h 2014-05-15 20:34:24.398204021 +0200
+@@ -0,0 +1,47 @@
++/**
++ * Copyright (C) ARM Limited 2010-2013. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __STREAMLINE_SETUP_H__
++#define __STREAMLINE_SETUP_H__
++
++#include "OlySocket.h"
++
++// Commands from Streamline
++enum {
++ COMMAND_REQUEST_XML = 0,
++ COMMAND_DELIVER_XML = 1,
++ COMMAND_APC_START = 2,
++ COMMAND_APC_STOP = 3,
++ COMMAND_DISCONNECT = 4,
++ COMMAND_PING = 5
++};
++
++class StreamlineSetup {
++public:
++ StreamlineSetup(OlySocket *socket);
++ ~StreamlineSetup();
++private:
++ OlySocket* mSocket;
++
++ char* readCommand(int*);
++ void handleRequest(char* xml);
++ void handleDeliver(char* xml);
++ void sendData(const char* data, uint32_t length, char type);
++ void sendString(const char* string, int type) {sendData(string, strlen(string), type);}
++ void sendEvents();
++ void sendConfiguration();
++ void sendDefaults();
++ void sendCounters();
++ void writeConfiguration(char* xml);
++
++ // Intentionally unimplemented
++ StreamlineSetup(const StreamlineSetup &);
++ StreamlineSetup &operator=(const StreamlineSetup &);
++};
++
++#endif //__STREAMLINE_SETUP_H__
+diff -Nur linux-3.10.30.orig/tools/lib/lk/Makefile linux-linaro-stable-mx6/tools/lib/lk/Makefile
+--- linux-3.10.30.orig/tools/lib/lk/Makefile 2014-02-13 22:48:15.000000000 +0100
++++ linux-linaro-stable-mx6/tools/lib/lk/Makefile 2014-05-15 20:34:24.454204424 +0200
+@@ -1,5 +1,8 @@
+ include ../../scripts/Makefile.include
+
++CC = $(CROSS_COMPILE)gcc
++AR = $(CROSS_COMPILE)ar
++
+ # guard against environment variables
+ LIB_H=
+ LIB_OBJS=
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